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1 | /*++\r |
2 | \r | |
3 | Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>\r | |
4 | \r\r | |
5 | This program and the accompanying materials are licensed and made available under\r\r | |
6 | the terms and conditions of the BSD License that accompanies this distribution. \r\r | |
7 | The full text of the license may be found at \r\r | |
8 | http://opensource.org/licenses/bsd-license.php. \r\r | |
9 | \r\r | |
10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r\r | |
11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r\r | |
12 | \r\r | |
13 | \r | |
14 | \r | |
15 | Module Name:\r | |
16 | \r | |
17 | PlatformCpuInfo.h\r | |
18 | \r | |
19 | Abstract:\r | |
20 | \r | |
21 | GUID used for Platform CPU Info Data entries in the HOB list.\r | |
22 | \r | |
23 | --*/\r | |
24 | \r | |
25 | #ifndef _PLATFORM_CPU_INFO_GUID_H_\r | |
26 | #define _PLATFORM_CPU_INFO_GUID_H_\r | |
27 | \r | |
28 | #include "CpuType.h"\r | |
29 | #include <Library/CpuIA32.h>\r | |
30 | \r | |
31 | #define EFI_PLATFORM_CPU_INFO_GUID \\r | |
32 | {\\r | |
33 | 0xbb9c7ab7, 0xb8d9, 0x4bf3, 0x9c, 0x29, 0x9b, 0xf3, 0x41, 0xe2, 0x17, 0xbc \\r | |
34 | }\r | |
35 | \r | |
36 | extern EFI_GUID gEfiPlatformCpuInfoGuid;\r | |
37 | extern CHAR16 EfiPlatformCpuInfoVariable[];\r | |
38 | \r | |
39 | //\r | |
40 | // Tri-state for feature capabilities and enable/disable.\r | |
41 | // [0] clear=feature isn't capable\r | |
42 | // [0] set =feature is capable\r | |
43 | // [1] clear=feature is disabled\r | |
44 | // [1] set =feature is enabled\r | |
45 | //\r | |
46 | #define CPU_FEATURES_CAPABLE BIT0\r | |
47 | #define CPU_FEATURES_ENABLE BIT1\r | |
48 | \r | |
49 | #define MAX_CACHE_DESCRIPTORS 64\r | |
50 | #define MAXIMUM_CPU_BRAND_STRING_LENGTH 48\r | |
51 | \r | |
52 | #pragma pack(1)\r | |
53 | \r | |
54 | typedef struct {\r | |
55 | UINT32 FullCpuId; // [31:0] & 0x0FFF0FFF\r | |
56 | UINT32 FullFamilyModelId; // [31:0] & 0x0FFF0FF0\r | |
57 | UINT8 ExtendedFamilyId; // [27:20]\r | |
58 | UINT8 ExtendedModelId; // [19:16]\r | |
59 | UINT8 ProcessorType; // [13:11]\r | |
60 | UINT8 FamilyId; // [11:8]\r | |
61 | UINT8 Model; // [7:4]\r | |
62 | UINT8 SteppingId; // [3:0]\r | |
63 | } EFI_CPU_VERSION_INFO; // CPUID.1.EAX\r | |
64 | \r | |
65 | typedef struct {\r | |
66 | UINT32 L1InstructionCacheSize;\r | |
67 | UINT32 L1DataCacheSize;\r | |
68 | UINT32 L2CacheSize;\r | |
69 | UINT32 L3CacheSize;\r | |
70 | UINT32 TraceCacheSize;\r | |
71 | UINT8 CacheDescriptor[MAX_CACHE_DESCRIPTORS];\r | |
72 | } EFI_CPU_CACHE_INFO; // CPUID.2.EAX\r | |
73 | \r | |
74 | typedef struct {\r | |
75 | UINT8 PhysicalPackages;\r | |
76 | UINT8 LogicalProcessorsPerPhysicalPackage;\r | |
77 | UINT8 CoresPerPhysicalPackage;\r | |
78 | UINT8 ThreadsPerCore;\r | |
79 | } EFI_CPU_PACKAGE_INFO; // CPUID.4.EAX\r | |
80 | \r | |
81 | typedef struct {\r | |
82 | UINT32 RegEdx; // CPUID.5.EAX\r | |
83 | UINT8 MaxCState;\r | |
84 | UINT8 C0SubCStatesMwait; // EDX [3:0]\r | |
85 | UINT8 C1SubCStatesMwait; // EDX [7:4]\r | |
86 | UINT8 C2SubCStatesMwait; // EDX [11:8]\r | |
87 | UINT8 C3SubCStatesMwait; // EDX [15:12]\r | |
88 | UINT8 C4SubCStatesMwait; // EDX [19:16]\r | |
89 | UINT8 C5SubCStatesMwait; // EDX [23:20]\r | |
90 | UINT8 C6SubCStatesMwait; // EDX [27:24]\r | |
91 | UINT8 C7SubCStatesMwait; // EDX [31:28]\r | |
92 | UINT8 MonitorMwaitSupport; // ECX [0]\r | |
93 | UINT8 InterruptsBreakMwait; // ECX [1]\r | |
94 | } EFI_CPU_CSTATE_INFO; // CPUID.5.EAX\r | |
95 | \r | |
96 | typedef struct {\r | |
97 | UINT8 Turbo; // EAX [1]\r | |
98 | UINT8 PECI; // EAX [0]\r | |
99 | UINT8 NumIntThresholds; // EBX [3:0]\r | |
100 | UINT8 HwCoordinationFeedback; // ECX [0]\r | |
101 | } EFI_CPU_POWER_MANAGEMENT; // CPUID.6.EAX\r | |
102 | \r | |
103 | //\r | |
104 | // IMPORTANT: Each CPU feature enabling entry is assumed a tri-state variable.\r | |
105 | // - Keep the respective feature entry variable as default value (0x00)\r | |
106 | // if the CPU is not capable for the feature.\r | |
107 | // - Use the specially defined programming convention to update the variable\r | |
108 | // to indicate capable, enable or disable.\r | |
109 | // ie. F_CAPABLE for feature available\r | |
110 | // F_ENABLE for feature enable\r | |
111 | // F_DISABLE for feature disable\r | |
112 | //\r | |
113 | typedef struct {\r | |
114 | EFI_CPUID_REGISTER Regs; // CPUID.1.EAX\r | |
115 | UINT8 Xapic; // ECX [21]\r | |
116 | UINT8 SSE4_2; // ECX [20]\r | |
117 | UINT8 SSE4_1; // ECX [19]\r | |
118 | UINT8 Dca; // ECX [18]\r | |
119 | UINT8 SupSSE3; // ECX [9]\r | |
120 | UINT8 Tm2; // ECX [8]\r | |
121 | UINT8 Eist; // ECX [7]\r | |
122 | UINT8 Lt; // ECX [6]\r | |
123 | UINT8 Vt; // ECX [5]\r | |
124 | UINT8 Mwait; // ECX [3]\r | |
125 | UINT8 SSE3; // ECX [0]\r | |
126 | UINT8 Tcc; // EDX [29]\r | |
127 | UINT8 Mt; // EDX [28]\r | |
128 | UINT8 SSE2; // EDX [26]\r | |
129 | UINT8 SSE; // EDX [25]\r | |
130 | UINT8 MMX; // EDX [23]\r | |
131 | EFI_CPUID_REGISTER ExtRegs; // CPUID.80000001.EAX\r | |
132 | UINT8 ExtLahfSahf64; // ECX [0]\r | |
133 | UINT8 ExtIntel64; // EDX [29]\r | |
134 | UINT8 ExtXd; // EDX [20]\r | |
135 | UINT8 ExtSysCallRet64; // EDX [11]\r | |
136 | UINT16 Ht; // CPUID.0B.EAX EBX [15:0]\r | |
137 | } EFI_CPU_FEATURES; // CPUID.1.EAX, CPUID.0B.EAX, CPUID.80000001.EAX\r | |
138 | \r | |
139 | typedef struct {\r | |
140 | UINT8 PhysicalBits;\r | |
141 | UINT8 VirtualBits;\r | |
142 | } EFI_CPU_ADDRESS_BITS; // CPUID.80000008.EAX\r | |
143 | \r | |
144 | typedef struct {\r | |
145 | UINT8 PlatformID; // MSR 0x17 [52:50]\r | |
146 | UINT32 MicrocodeRevision; // MSR 0x8B [63:32]\r | |
147 | UINT8 MaxEfficiencyRatio; // MSR 0xCE [47:40]\r | |
148 | UINT8 DdrRatioUnlockCap; // MSR 0xCE [30]\r | |
149 | UINT8 TdcTdpLimitsTurbo; // MSR 0xCE [29]\r | |
150 | UINT8 RatioLimitsTurbo; // MSR 0xCE [28]\r | |
151 | UINT8 PreProduction; // MSR 0xCE [27]\r | |
152 | UINT8 DcuModeSelect; // MSR 0xCE [26]\r | |
153 | UINT8 MaxNonTurboRatio; // MSR 0xCE [15:8]\r | |
154 | UINT8 Emrr; // MSR 0xFE [12]\r | |
155 | UINT8 Smrr; // MSR 0xFE [11]\r | |
156 | UINT8 VariableMtrrCount; // MSR 0xFE [7:0]\r | |
157 | UINT16 PState; // MSR 0x198 [15:0]\r | |
158 | UINT8 TccActivationTemperature; // MSR 0x1A2 [23:16]\r | |
159 | UINT8 TemperatureControlOffset; // MSR 0x1A2 [15:8]\r | |
160 | UINT32 PCIeBar; // MSR 0x300 [39:20]\r | |
161 | UINT8 PCIeBarSizeMB; // MSR 0x300 [3:1]\r | |
162 | } EFI_MSR_FEATURES;\r | |
163 | \r | |
164 | typedef struct {\r | |
165 | BOOLEAN IsIntelProcessor;\r | |
166 | UINT8 BrandString[MAXIMUM_CPU_BRAND_STRING_LENGTH + 1];\r | |
167 | UINT32 CpuidMaxInputValue;\r | |
168 | UINT32 CpuidMaxExtInputValue;\r | |
169 | EFI_CPU_UARCH CpuUarch;\r | |
170 | EFI_CPU_FAMILY CpuFamily;\r | |
171 | EFI_CPU_PLATFORM CpuPlatform;\r | |
172 | EFI_CPU_TYPE CpuType;\r | |
173 | EFI_CPU_VERSION_INFO CpuVersion;\r | |
174 | EFI_CPU_CACHE_INFO CpuCache;\r | |
175 | EFI_CPU_FEATURES CpuFeatures;\r | |
176 | EFI_CPU_CSTATE_INFO CpuCState;\r | |
177 | EFI_CPU_PACKAGE_INFO CpuPackage;\r | |
178 | EFI_CPU_POWER_MANAGEMENT CpuPowerManagement;\r | |
179 | EFI_CPU_ADDRESS_BITS CpuAddress;\r | |
180 | EFI_MSR_FEATURES Msr;\r | |
181 | } EFI_PLATFORM_CPU_INFO;\r | |
182 | \r | |
183 | #pragma pack()\r | |
184 | \r | |
185 | #endif\r |