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DW		 1/*++\r
2\r
3 Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>\r
4 \r\r
5 This program and the accompanying materials are licensed and made available under\r\r
6 the terms and conditions of the BSD License that accompanies this distribution. \r\r
7 The full text of the license may be found at \r\r
8 http://opensource.org/licenses/bsd-license.php. \r\r
9 \r\r
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r\r
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r\r
12 \r\r
13\r
14\r
15\r
16Module Name:\r
17\r
18 PlatformInfo.h\r
19\r
20Abstract:\r
21\r
22 GUID used for Platform Info Data entries in the HOB list.\r
23\r
24--*/\r
25\r
26#ifndef _PLATFORM_INFO_GUID_H_\r
27#define _PLATFORM_INFO_GUID_H_\r
28\r
29#ifndef ECP_FLAG\r
30#include <PiPei.h>\r
31\r
32#include <Library/HobLib.h>\r
33#include <Library/IoLib.h>\r
34#include <Library/DebugLib.h>\r
35#include <Library/SmbusLib.h>\r
36#include <IndustryStandard/SmBus.h>\r
37#endif\r
38\r
39#define PLATFORM_INFO_REVISION = 1 // Revision id for current platform information struct.\r
40\r
41//\r
42// Start::BayLake Board Defines\r
43//\r
44#define BOARD_REVISION_DEFAULT = 0xff\r
45#define UNKNOWN_FABID 0x0F\r
46#define FAB_ID_MASK 0x0F\r
47#define BOARD_ID_2 0x01\r
48#define BOARD_ID_1 0x40\r
49#define BOARD_ID_0 0x04\r
50\r
51#define BOARD_ID_DT_CRB 0x0\r
52#define BOARD_ID_DT_VLVR 0x1\r
53#define BOARD_ID_SVP_VLV 0xC\r
54#define BOARD_ID_SVP_EV_VLV 0xD\r
55//\r
56// End::BayLake Board Defines\r
57//\r
58\r
59//\r
60// Start::Alpine Valley Board Defines\r
61//\r
62#define DC_ID_DDR3L 0x00\r
63#define DC_ID_DDR3 0x04\r
64#define DC_ID_LPDDR3 0x02\r
65#define DC_ID_LPDDR2 0x06\r
66#define DC_ID_DDR4 0x01\r
67#define DC_ID_DDR3L_ECC 0x05\r
68#define DC_ID_NO_MEM 0x07\r
69//\r
70// End::Alpine Valley Board Defines\r
71//\r
72\r
73#define MAX_FAB_ID_RETRY_COUNT 100\r
74#define MAX_FAB_ID_CHECK_COUNT 3\r
75\r
76#define PLATFORM_INFO_HOB_REVISION 0x1\r
77\r
78#define EFI_PLATFORM_INFO_GUID \\r
79 { \\r
80 0x1e2acc41, 0xe26a, 0x483d, 0xaf, 0xc7, 0xa0, 0x56, 0xc3, 0x4e, 0x8, 0x7b \\r
81 }\r
82\r
83extern EFI_GUID gEfiPlatformInfoGuid;\r
84\r
85typedef enum {\r
86 FlavorUnknown = 0,\r
87\r
88 //\r
89 // Mobile\r
90 //\r
91 FlavorMobile = 1,\r
92\r
93 //\r
94 // Desktop\r
95 //\r
96 FlavorDesktop = 2,\r
97\r
98 //\r
99 // Tablet\r
100 //\r
101 FlavorTablet = 3\r
102} PLATFORM_FLAVOR;\r
103\r
104#pragma pack(1)\r
105\r
106typedef struct {\r
107 UINT16 PciResourceIoBase;\r
108 UINT16 PciResourceIoLimit;\r
109 UINT32 PciResourceMem32Base;\r
110 UINT32 PciResourceMem32Limit;\r
111 UINT64 PciResourceMem64Base;\r
112 UINT64 PciResourceMem64Limit;\r
113 UINT64 PciExpressBase;\r
114 UINT32 PciExpressSize;\r
115 UINT8 PciHostAddressWidth;\r
116 UINT8 PciResourceMinSecBus;\r
117} EFI_PLATFORM_PCI_DATA;\r
118\r
119typedef struct {\r
120 UINT8 CpuAddressWidth;\r
121 UINT32 CpuFamilyStepping;\r
122} EFI_PLATFORM_CPU_DATA;\r
123\r
124typedef struct {\r
125 UINT8 SysIoApicEnable;\r
126 UINT8 SysSioExist;\r
127} EFI_PLATFORM_SYS_DATA;\r
128\r
129typedef struct {\r
130 UINT32 MemTolm;\r
131 UINT32 MemMaxTolm;\r
132 UINT32 MemTsegSize;\r
133 UINT32 MemTsegBase;\r
134 UINT32 MemIedSize;\r
135 UINT32 MemIgdSize;\r
136 UINT32 MemIgdBase;\r
137 UINT32 MemIgdGttSize;\r
138 UINT32 MemIgdGttBase;\r
139 UINT64 MemMir0;\r
140 UINT64 MemMir1;\r
141 UINT32 MemConfigSize;\r
142 UINT16 MmioSize;\r
143 UINT8 DdrFreq;\r
144 UINT8 DdrType; \r
145 UINT32 MemSize;\r
146 BOOLEAN EccSupport;\r
147 UINT8 Reserved[3];\r
148 UINT16 DimmSize[2];\r
149} EFI_PLATFORM_MEM_DATA;\r
150\r
151\r
152typedef struct {\r
153 UINT32 IgdOpRegionAddress; // IGD OpRegion Starting Address\r
154 UINT8 IgdBootType; // IGD Boot Display Device\r
155 UINT8 IgdPanelType; // IGD Panel Type CMOs option\r
156 UINT8 IgdTvFormat; // IGD TV Format CMOS option\r
157 UINT8 IgdTvMinor; // IGD TV Minor Format CMOS option\r
158 UINT8 IgdPanelScaling; // IGD Panel Scaling\r
159 UINT8 IgdBlcConfig; // IGD BLC Configuration\r
160 UINT8 IgdBiaConfig; // IGD BIA Configuration\r
161 UINT8 IgdSscConfig; // IGD SSC Configuration\r
162 UINT8 IgdDvmtMemSize; // IGD DVMT Memory Size\r
163 UINT8 IgdFunc1Enable; // IGD Function 1 Enable\r
164 UINT8 IgdHpllVco; // HPLL VCO\r
165 UINT8 IgdSciSmiMode; // GMCH SMI/SCI mode (0=SCI)\r
166 UINT8 IgdPAVP; // IGD PAVP data\r
167} EFI_PLATFORM_IGD_DATA;\r
168\r
169typedef enum {\r
170 BOARD_ID_AV_SVP = 0x0, // Alpine Valley Board\r
171 BOARD_ID_BL_RVP = 0x2, // BayLake Board (RVP)\r
172 BOARD_ID_BL_FFRD8 = 0x3, // FFRD8 b'0011\r
173 BOARD_ID_BL_FFRD = 0x4, // BayLake Board (FFRD)\r
174 BOARD_ID_BL_RVP_DDR3L = 0x5, // BayLake Board (RVP DDR3L)\r
175 BOARD_ID_BL_STHI = 0x7, // PPV- STHI Board\r
176 BOARD_ID_BB_RVP = 0x20, // Bayley Bay Board\r
177 BOARD_ID_BS_RVP = 0x30, // Bakersport Board\r
178 BOARD_ID_CVH = 0x90, // Crestview Hills\r
179 BOARD_ID_MINNOW2 = 0xA0 // Minnow2\r
180\r
181} BOARD_ID_LIST;\r
182\r
183typedef enum {\r
184 FAB1 = 0,\r
185 FAB2 = 1,\r
186 FAB3 = 2\r
187} FAB_ID_LIST;\r
188\r
189typedef enum {\r
190 PR0 = 0, // FFRD PR0\r
191 PR05 = 1, // FFRD PR0.3 and PR 0.5\r
192 PR1 = 2, // FFRD PR1\r
193 PR11 = 3 // FFRD PR1.1\r
194} FFRD_ID_LIST;\r
195\r
196\r
197//\r
198// VLV2 GPIO GROUP OFFSET\r
199//\r
200#define GPIO_SCORE_OFFSET 0x0000\r
201#define GPIO_NCORE_OFFSET 0x1000\r
202#define GPIO_SSUS_OFFSET 0x2000\r
203\r
204//\r
205// GPIO Initialization Data Structure for BayLake.\r
206// SC = SCORE, SS= SSUS\r
207// Note: NC doesn't support GPIO functionality in IO access mode, only support in MMIO access mode.\r
208//\r
209\r
210//\r
211// IO space\r
212//\r
213typedef struct{\r
214 UINT32 Use_Sel_SC0;\r
215 UINT32 Use_Sel_SC1;\r
216 UINT32 Use_Sel_SC2;\r
217 UINT32 Use_Sel_SS;\r
218\r
219 UINT32 Io_Sel_SC0;\r
220 UINT32 Io_Sel_SC1;\r
221 UINT32 Io_Sel_SC2;\r
222 UINT32 Io_Sel_SS;\r
223\r
224 UINT32 GP_Lvl_SC0;\r
225 UINT32 GP_Lvl_SC1;\r
226 UINT32 GP_Lvl_SC2;\r
227 UINT32 GP_Lvl_SS;\r
228\r
229 UINT32 TPE_SC0;\r
230 UINT32 TPE_SS;\r
231\r
232 UINT32 TNE_SC0;\r
233 UINT32 TNE_SS;\r
234\r
235 UINT32 TS_SC0;\r
236 UINT32 TS_SS;\r
237\r
238 UINT32 WE_SS;\r
239} CFIO_INIT_STRUCT;\r
240\r
241\r
242\r
243//\r
244// CFIO PAD configuration Registers\r
245//\r
246//\r
247// Memory space\r
248//\r
249typedef union {\r
250 UINT32 dw;\r
251 struct {\r
252 UINT32 Func_Pin_Mux:3; // 0:2 Function of CFIO selection\r
253 UINT32 ipslew:2; // 3:4 Pad (P) Slew Rate Controls PAD slew rate check Width\r
254 UINT32 inslew:2; // 5:6 Pad (N) Slew Rate Controls PAD slew rate\r
255 UINT32 Pull_assign:2; // 7:8 Pull assignment\r
256 UINT32 Pull_strength:2; // 9:10 Pull strength\r
257 UINT32 Bypass_flop:1; // 11 Bypass flop\r
258 UINT32 Filter_en:1; // 12 Filter Enable\r
259 UINT32 Hist_ctrl:2; // 13:14 hysteresis control\r
260 UINT32 Hist_enb:1; // 15 Hysteresis enable, active low\r
261 UINT32 Delay_line:6; // 16:21 Delay line values - Delay values for input or output\r
262 UINT32 Reserved:3; // 22:24 Reserved\r
263 UINT32 TPE:1; // 25 Trigger Positive Edge Enable\r
264 UINT32 TNE:1; // 26 Trigger Negative Edge Enable\r
265 UINT32 Reserved2:3; // 27:29 Reserved\r
266 UINT32 i1p5sel:1; // 30\r
267 UINT32 IODEN:1; // 31 : Open Drain enable. Active high\r
268 } r;\r
269} PAD_CONF0;\r
270\r
271typedef union{\r
272 UINT32 dw;\r
273 struct {\r
274 UINT32 instr:16; // 0:15 Pad (N) strength.\r
275 UINT32 ipstr:16; // 16:31 Pad (P) strength.\r
276 }r;\r
277} PAD_CONF1;\r
278\r
279typedef union{\r
280 UINT32 dw;\r
281 struct {\r
282 UINT32 pad_val:1; // 0 These registers are implemented as dual read/write with dedicated storage each.\r
283 UINT32 ioutenb:1; // 1 output enable\r
284 UINT32 iinenb:1; // 2 input enable\r
285 UINT32 Reserved:29; // 3:31 Reserved\r
286 }r;\r
287} PAD_VAL;\r
288\r
289typedef union{\r
290 UINT32 GPI;\r
291 struct {\r
292 UINT32 ihbpen:1; // 0 Pad high by pass enable\r
293 UINT32 ihbpinen:1; // 1 Pad high by pass input\r
294 UINT32 instaticen:1; // 2 TBD\r
295 UINT32 ipstaticen:1; // 3 TBD\r
296 UINT32 Overide_strap_pin :1; // 4 DFX indicates if it wants to override the strap pin value on this pad, if exists.\r
297 UINT32 Overide_strap_pin_val:1; // 5 In case DFX need to override strap pin value and it exist for the specific pad, this value will be used.\r
298 UINT32 TestMode_Pin_Mux:3; // 6:9 DFX Pin Muxing\r
299 }r;\r
300} PAD_DFT;\r
301\r
302//\r
303// GPIO_USAGE value need to matche the PAD_VAL input/output enable bits.\r
304//\r
305typedef enum {\r
306 Native = 0xFF, // Native, no need to set PAD_VALUE\r
307 GPI = 2, // GPI, input only in PAD_VALUE\r
308 GPO = 4, // GPO, output only in PAD_VALUE\r
309 GPIO = 0, // GPIO, input & output\r
310 TRISTS = 6, // Tri-State\r
311 GPIO_NONE\r
312} GPIO_USAGE;\r
313\r
314typedef enum {\r
315 LO = 0,\r
316 HI = 1,\r
317 NA = 0xFF\r
318} GPO_D4;\r
319\r
320typedef enum {\r
321 F0 = 0,\r
322 F1 = 1,\r
323 F2 = 2,\r
324 F3 = 3,\r
325 F4 = 4,\r
326 F5 = 5,\r
327 F6 = 6,\r
328 F7 = 7\r
329} GPIO_FUNC_NUM;\r
330\r
331//\r
332// Mapping to CONF0 bit 27:24\r
333// Note: Assume "Direct Irq En" is not set, unless specially notified.\r
334//\r
335typedef enum {\r
336 TRIG_ = 0,\r
337 TRIG_Edge_High = /*BIT3 |*/ BIT1, // Positive Edge (Rasing)\r
338 TRIG_Edge_Low = /*BIT3 |*/ BIT2, // Negative Edge (Falling)\r
339 TRIG_Edge_Both = /*BIT3 |*/ BIT2 | BIT1, // Both Edge\r
340 TRIG_Level_High= /*BIT3 |*/ BIT1 | BIT0, // Level High\r
341 TRIG_Level_Low = /*BIT3 |*/ BIT2 | BIT0, // Level Low\r
342} INT_TYPE;\r
343\r
344typedef enum {\r
345 P_20K_H, // Pull Up 20K\r
346 P_20K_L, // Pull Down 20K\r
347 P_10K_H, // Pull Up 10K\r
348 P_10K_L, // Pull Down 10K\r
349 P_2K_H, // Pull Up 2K\r
350 P_2K_L, // Pull Down 2K\r
351 P_NONE // Pull None\r
352} PULL_TYPE;\r
353\r
354#ifdef EFI_DEBUG\r
355 #define GPIO_INIT_ITEM(pad_name, usage, gpod4, func, int_cap, int_type, pull, offset) {pad_name, usage, gpod4, func, /*int_cap,*/ TRIG_##int_type, P_##pull, offset}\r
356#else\r
357 #define GPIO_INIT_ITEM(pad_name, usage, gpod4, func, int_cap, int_type, pull, offset) { usage, gpod4, func, /*int_cap,*/ TRIG_##int_type, P_##pull, offset}\r
358#endif\r
359\r
360//\r
361// GPIO CONF & PAD Initialization Data Structure for BayLake GPIOs bits.\r
362// NC = NCORE, SC = SCORE, SS= SSUS\r
363//\r
364typedef struct {\r
365\r
366#ifdef EFI_DEBUG\r
367 char pad_name[32];// GPIO Pin Name for debug purpose\r
368#endif\r
369\r
370 GPIO_USAGE usage; // GPIO pin used as Native mode or GPI/GPO/GPIO mode\r
371 GPO_D4 gpod4; // GPO default value\r
372 GPIO_FUNC_NUM func; // Function Number (F0~F7)\r
373 INT_TYPE int_type; // Edge or Level trigger, low or high active\r
374 PULL_TYPE pull; // Pull Up or Down\r
375 UINT8 offset; // Equal with (PCONF0 register offset >> 4 bits)\r
376} GPIO_CONF_PAD_INIT;\r
377\r
378//\r
379//typedef UINT64 BOARD_FEATURES\r
380//\r
381typedef struct _EFI_PLATFORM_INFO_HOB {\r
382 UINT16 PlatformType; // Platform Type\r
383 UINT8 BoardId; // Board ID\r
384 UINT8 BoardRev; // Board Revision\r
385 PLATFORM_FLAVOR PlatformFlavor; // Platform Flavor\r
386 UINT8 DDRDaughterCardCh0Id;// DDR daughter card channel 0 id\r
387 UINT8 DDRDaughterCardCh1Id;// DDR daughter card channel 1 id\r
388 UINT8 ECOId; // ECO applied on platform\r
389 UINT16 IohSku;\r
390 UINT8 IohRevision;\r
391 UINT16 IchSku;\r
392 UINT8 IchRevision;\r
393 EFI_PLATFORM_PCI_DATA PciData;\r
394 EFI_PLATFORM_CPU_DATA CpuData;\r
395 EFI_PLATFORM_MEM_DATA MemData;\r
396 EFI_PLATFORM_SYS_DATA SysData;\r
397 EFI_PLATFORM_IGD_DATA IgdData;\r
398 UINT8 RevisonId; // Structure Revision ID\r
399 EFI_PHYSICAL_ADDRESS PlatformCfioData;\r
400 EFI_PHYSICAL_ADDRESS PlatformGpioData_NC;\r
401 EFI_PHYSICAL_ADDRESS PlatformGpioData_SC;\r
402 EFI_PHYSICAL_ADDRESS PlatformGpioData_SUS;\r
403 EFI_PHYSICAL_ADDRESS PlatformGpioData_NC_TRI;\r
404 EFI_PHYSICAL_ADDRESS PlatformGpioData_SC_TRI;\r
405 EFI_PHYSICAL_ADDRESS PlatformGpioData_SUS_TRI;\r
406 EFI_PHYSICAL_ADDRESS PlatformGpioData_SUS_PR1;\r
407 EFI_PHYSICAL_ADDRESS PlatformGpioData_SC_PR1_1;\r
408 EFI_PHYSICAL_ADDRESS PlatformGpioData_SUS_PR1_1;\r
409\r
410 UINT8 CfioEnabled;\r
411 UINT32 SsidSvid;\r
412 UINT16 AudioSubsystemDeviceId;\r
413 UINT64 AcpiOemId;\r
414 UINT64 AcpiOemTableId;\r
415 UINT16 MemCfgID;\r
416} EFI_PLATFORM_INFO_HOB;\r
417\r
418#pragma pack()\r
419\r
420EFI_STATUS\r
421GetPlatformInfoHob (\r
422 IN CONST EFI_PEI_SERVICES **PeiServices,\r
423 OUT EFI_PLATFORM_INFO_HOB **PlatformInfoHob\r
424 );\r
425\r
426\r
427EFI_STATUS\r
428InstallPlatformClocksNotify (\r
429 IN CONST EFI_PEI_SERVICES **PeiServices\r
430 );\r
431\r
432EFI_STATUS\r
433InstallPlatformSysCtrlGPIONotify (\r
434 IN CONST EFI_PEI_SERVICES **PeiServices\r
435 );\r
436\r
437#endif\r
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