projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| 3cbfba02 DW |
1 | /*++\r |
| 2 | \r | |
| 3 | Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>\r | |
| 4 | \r\r | |
| 5 | This program and the accompanying materials are licensed and made available under\r\r | |
| 6 | the terms and conditions of the BSD License that accompanies this distribution. \r\r | |
| 7 | The full text of the license may be found at \r\r | |
| 8 | http://opensource.org/licenses/bsd-license.php. \r\r | |
| 9 | \r\r | |
| 10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r\r | |
| 11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r\r | |
| 12 | \r\r | |
| 13 | \r | |
| 14 | \r | |
| 15 | \r | |
| 16 | Module Name:\r | |
| 17 | \r | |
| 18 | Fd.h\r | |
| 19 | \r | |
| 20 | Abstract:\r | |
| 21 | \r | |
| 22 | EFI Intel82802AB/82802AC Firmware Hub.\r | |
| 23 | \r | |
| 24 | \r | |
| 25 | --*/\r | |
| 26 | \r | |
| 27 | \r | |
| 28 | //\r | |
| 29 | // Supported SPI devices\r | |
| 30 | //\r | |
| 31 | \r | |
| 32 | //\r | |
| 33 | // MFG and Device code\r | |
| 34 | //\r | |
| 35 | #define SST_25LF040A 0x0044BF\r | |
| 36 | #define SST_25LF040 0x0040BF\r | |
| 37 | #define SST_25LF080A 0x0080BF\r | |
| 38 | #define SST_25VF080B 0x008EBF\r | |
| 39 | #define SST_25VF016B 0x0041BF\r | |
| 40 | #define SST_25VF032B 0x004ABF\r | |
| 41 | \r | |
| 42 | #define PMC_25LV040 0x007E9D\r | |
| 43 | \r | |
| 44 | #define ATMEL_26DF041 0x00441F\r | |
| 45 | #define Atmel_AT26F004 0x00041F\r | |
| 46 | #define Atmel_AT26DF081A 0x01451F\r | |
| 47 | #define Atmel_AT25DF161 0x02461F\r | |
| 48 | #define Atmel_AT26DF161 0x00461F\r | |
| 49 | #define Atmel_AT25DF641 0x00481F\r | |
| 50 | #define Atmel_AT26DF321 0x00471F\r | |
| 51 | \r | |
| 52 | #define Macronix_MX25L8005 0x1420C2\r | |
| 53 | #define Macronix_MX25L1605A 0x1520C2\r | |
| 54 | #define Macronix_MX25L3205D 0x1620C2\r | |
| 55 | \r | |
| 56 | #define STMicro_M25PE80 0x148020\r | |
| 57 | \r | |
| 58 | #define Winbond_W25X40 0x1330EF\r | |
| 59 | #define Winbond_W25X80 0x1430EF\r | |
| 60 | #define Winbond_W25Q80 0x1440EF\r | |
| 61 | \r | |
| 62 | #define Winbond_W25X16 0x1540EF // W25Q16\r | |
| 63 | #define Winbond_W25X32 0x1630EF\r | |
| 64 | \r | |
| 65 | //\r | |
| 66 | // NOTE: Assuming that 8Mbit flash will only contain a 4Mbit binary.\r | |
| 67 | // Treating 4Mbit and 8Mbit devices the same.\r | |
| 68 | //\r | |
| 69 | \r | |
| 70 | //\r | |
| 71 | // BIOS Base Address\r | |
| 72 | //\r | |
| 73 | #define BIOS_BASE_ADDRESS_4M 0xFFF80000\r | |
| 74 | #define BIOS_BASE_ADDRESS_8M 0xFFF00000\r | |
| 75 | #define BIOS_BASE_ADDRESS_16M 0xFFE00000\r | |
| 76 | \r | |
| 77 | //\r | |
| 78 | // block and sector sizes\r | |
| 79 | //\r | |
| 80 | #define SECTOR_SIZE_256BYTE 0x100 // 256byte page size\r | |
| 81 | #define SECTOR_SIZE_4KB 0x1000 // 4kBytes sector size\r | |
| 82 | #define BLOCK_SIZE_32KB 0x00008000 // 32Kbytes block size\r | |
| 83 | #define MAX_FLASH_SIZE 0x00400000 // 32Mbit (Note that this can also be used for the 4Mbit & 8Mbit)\r | |
| 84 | \r | |
| 85 | //\r | |
| 86 | // Flash commands\r | |
| 87 | //\r | |
| 88 | #define SPI_SST25LF_COMMAND_WRITE 0x02\r | |
| 89 | #define SPI_SST25LF_COMMAND_READ 0x03\r | |
| 90 | #define SPI_SST25LF_COMMAND_ERASE 0x20\r | |
| 91 | #define SPI_SST25LF_COMMAND_WRITE_DISABLE 0x04\r | |
| 92 | #define SPI_SST25LF_COMMAND_READ_STATUS 0x05\r | |
| 93 | #define SPI_SST25LF_COMMAND_WRITE_ENABLE 0x06\r | |
| 94 | #define SPI_SST25LF_COMMAND_READ_ID 0xAB\r | |
| 95 | #define SPI_SST25LF_COMMAND_WRITE_S_EN 0x50\r | |
| 96 | #define SPI_SST25LF_COMMAND_WRITE_S 0x01\r | |
| 97 | \r | |
| 98 | #define SPI_PMC25LV_COMMAND_WRITE 0x02\r | |
| 99 | #define SPI_PMC25LV_COMMAND_READ 0x03\r | |
| 100 | #define SPI_PMC25LV_COMMAND_ERASE 0xD7\r | |
| 101 | #define SPI_PMC25LV_COMMAND_WRITE_DISABLE 0x04\r | |
| 102 | #define SPI_PMC25LV_COMMAND_READ_STATUS 0x05\r | |
| 103 | #define SPI_PMC25LV_COMMAND_WRITE_ENABLE 0x06\r | |
| 104 | #define SPI_PMC25LV_COMMAND_READ_ID 0xAB\r | |
| 105 | #define SPI_PMC25LV_COMMAND_WRITE_S_EN 0x06\r | |
| 106 | #define SPI_PMC25LV_COMMAND_WRITE_S 0x01\r | |
| 107 | \r | |
| 108 | #define SPI_AT26DF_COMMAND_WRITE 0x02\r | |
| 109 | #define SPI_AT26DF_COMMAND_READ 0x03\r | |
| 110 | #define SPI_AT26DF_COMMAND_ERASE 0x20\r | |
| 111 | #define SPI_AT26DF_COMMAND_WRITE_DISABLE 0x00\r | |
| 112 | #define SPI_AT26DF_COMMAND_READ_STATUS 0x05\r | |
| 113 | #define SPI_AT26DF_COMMAND_WRITE_ENABLE 0x00\r | |
| 114 | #define SPI_AT26DF_COMMAND_READ_ID 0x9F\r | |
| 115 | #define SPI_AT26DF_COMMAND_WRITE_S_EN 0x00\r | |
| 116 | #define SPI_AT26DF_COMMAND_WRITE_S 0x00\r | |
| 117 | \r | |
| 118 | #define SPI_AT26F_COMMAND_WRITE 0x02\r | |
| 119 | #define SPI_AT26F_COMMAND_READ 0x03\r | |
| 120 | #define SPI_AT26F_COMMAND_ERASE 0x20\r | |
| 121 | #define SPI_AT26F_COMMAND_WRITE_DISABLE 0x04\r | |
| 122 | #define SPI_AT26F_COMMAND_READ_STATUS 0x05\r | |
| 123 | #define SPI_AT26F_COMMAND_WRITE_ENABLE 0x06\r | |
| 124 | #define SPI_AT26F_COMMAND_JEDEC_ID 0x9F\r | |
| 125 | #define SPI_AT26F_COMMAND_WRITE_S_EN 0x00\r | |
| 126 | #define SPI_AT26F_COMMAND_WRITE_S 0x01\r | |
| 127 | #define SPI_AT26F_COMMAND_WRITE_UNPROTECT 0x39\r | |
| 128 | \r | |
| 129 | #define SPI_SST25VF_COMMAND_WRITE 0x02\r | |
| 130 | #define SPI_SST25VF_COMMAND_READ 0x03\r | |
| 131 | #define SPI_SST25VF_COMMAND_ERASE 0x20\r | |
| 132 | #define SPI_SST25VF_COMMAND_WRITE_DISABLE 0x04\r | |
| 133 | #define SPI_SST25VF_COMMAND_READ_STATUS 0x05\r | |
| 134 | #define SPI_SST25VF_COMMAND_WRITE_ENABLE 0x06\r | |
| 135 | #define SPI_SST25VF_COMMAND_READ_ID 0xAB\r | |
| 136 | #define SPI_SST25VF_COMMAND_JEDEC_ID 0x9F\r | |
| 137 | #define SPI_SST25VF_COMMAND_WRITE_S_EN 0x50\r | |
| 138 | #define SPI_SST25VF_COMMAND_WRITE_S 0x01\r | |
| 139 | \r | |
| 140 | #define SPI_STM25PE_COMMAND_WRITE 0x02\r | |
| 141 | #define SPI_STM25PE_COMMAND_READ 0x03\r | |
| 142 | #define SPI_STM25PE_COMMAND_ERASE 0xDB\r | |
| 143 | #define SPI_STM25PE_COMMAND_WRITE_DISABLE 0x04\r | |
| 144 | #define SPI_STM25PE_COMMAND_READ_STATUS 0x05\r | |
| 145 | #define SPI_STM25PE_COMMAND_WRITE_ENABLE 0x06\r | |
| 146 | #define SPI_STM25PE_COMMAND_JEDEC_ID 0x9F\r | |
| 147 | \r | |
| 148 | #define SPI_WinbondW25X_COMMAND_WRITE_S 0x01\r | |
| 149 | #define SPI_WinbondW25X_COMMAND_WRITE 0x02\r | |
| 150 | #define SPI_WinbondW25X_COMMAND_READ 0x03\r | |
| 151 | #define SPI_WinbondW25X_COMMAND_READ_STATUS 0x05\r | |
| 152 | #define SPI_WinbondW25X_COMMAND_ERASE_S 0x20\r | |
| 153 | #define SPI_WinbondW25X_COMMAND_WRITE_ENABLE 0x06\r | |
| 154 | #define SPI_WinbondW25X_COMMAND_JEDEC_ID 0x9F\r | |
| 155 | \r | |
| 156 | //\r | |
| 157 | // SPI default opcode slots\r | |
| 158 | //\r | |
| 159 | #define SPI_OPCODE_WRITE_INDEX 0\r | |
| 160 | #define SPI_OPCODE_READ_INDEX 1\r | |
| 161 | #define SPI_OPCODE_ERASE_INDEX 2\r | |
| 162 | #define SPI_OPCODE_READ_S_INDEX 3\r | |
| 163 | #define SPI_OPCODE_READ_ID_INDEX 4\r | |
| 164 | #define SPI_OPCODE_WRITE_S_INDEX 6\r | |
| 165 | #define SPI_OPCODE_WRITE_UNPROTECT_INDEX 7\r | |
| 166 | \r | |
| 167 | #define SPI_PREFIX_WRITE_S_EN 1\r | |
| 168 | #define SPI_PREFIX_WRITE_EN 0\r | |
| 169 | \r | |
| 170 | //\r | |
| 171 | // Atmel AT26F00x\r | |
| 172 | //\r | |
| 173 | #define B_AT26F_STS_REG_SPRL 0x80\r | |
| 174 | #define B_AT26F_STS_REG_SWP 0x0C\r | |
| 175 | \r | |
| 176 | //\r | |
| 177 | // Block lock bit definitions:\r | |
| 178 | //\r | |
| 179 | #define READ_LOCK 0x04\r | |
| 180 | #define LOCK_DOWN 0x02\r | |
| 181 | #define WRITE_LOCK 0x01\r | |
| 182 | #define FULL_ACCESS 0x00\r | |
| 183 | \r | |
| 184 | //\r | |
| 185 | // Function Prototypes\r | |
| 186 | //\r | |
| 187 | EFI_STATUS\r | |
| 188 | FlashGetNextBlock (\r | |
| 189 | IN UINTN* Key,\r | |
| 190 | OUT EFI_PHYSICAL_ADDRESS* BlockAddress,\r | |
| 191 | OUT UINTN* BlockSize\r | |
| 192 | );\r | |
| 193 | \r | |
| 194 | EFI_STATUS\r | |
| 195 | FlashGetSize (\r | |
| 196 | OUT UINTN* Size\r | |
| 197 | );\r | |
| 198 | \r | |
| 199 | EFI_STATUS\r | |
| 200 | FlashGetUniformBlockSize (\r | |
| 201 | OUT UINTN* Size\r | |
| 202 | );\r | |
| 203 | \r | |
| 204 | EFI_STATUS\r | |
| 205 | FlashEraseWithNoTopSwapping (\r | |
| 206 | IN UINT8 *BaseAddress,\r | |
| 207 | IN UINTN NumBytes\r | |
| 208 | );\r | |
| 209 | \r | |
| 210 | EFI_STATUS\r | |
| 211 | FlashErase (\r | |
| 212 | IN UINT8 *BaseAddress,\r | |
| 213 | IN UINTN NumBytes\r | |
| 214 | );\r | |
| 215 | \r | |
| 216 | EFI_STATUS\r | |
| 217 | FlashWriteWithNoTopSwapping (\r | |
| 218 | IN UINT8* DstBufferPtr,\r | |
| 219 | IN UINT8* SrcBufferPtr,\r | |
| 220 | IN UINTN NumBytes\r | |
| 221 | );\r | |
| 222 | \r | |
| 223 | EFI_STATUS\r | |
| 224 | FlashWrite (\r | |
| 225 | IN UINT8 *DstBufferPtr,\r | |
| 226 | IN UINT8 *SrcBufferPtr,\r | |
| 227 | IN UINTN NumBytes\r | |
| 228 | );\r | |
| 229 | \r | |
| 230 | EFI_STATUS\r | |
| 231 | FlashReadWithNoTopSwapping (\r | |
| 232 | IN UINT8 *BaseAddress,\r | |
| 233 | IN UINT8 *DstBufferPtr,\r | |
| 234 | IN UINTN NumBytes\r | |
| 235 | );\r | |
| 236 | \r | |
| 237 | EFI_STATUS\r | |
| 238 | FlashRead (\r | |
| 239 | IN UINT8 *BaseAddress,\r | |
| 240 | IN UINT8 *DstBufferPtr,\r | |
| 241 | IN UINTN NumBytes\r | |
| 242 | );\r | |
| 243 | \r | |
| 244 | EFI_STATUS\r | |
| 245 | FlashLockWithNoTopSwapping (\r | |
| 246 | IN UINT8* BaseAddress,\r | |
| 247 | IN UINTN NumBytes,\r | |
| 248 | IN UINT8 LockState\r | |
| 249 | );\r | |
| 250 | \r | |
| 251 | EFI_STATUS\r | |
| 252 | FlashLock(\r | |
| 253 | IN UINT8 *BaseAddress,\r | |
| 254 | IN UINTN NumBytes,\r | |
| 255 | IN UINT8 LockState\r | |
| 256 | );\r | |
| 257 | \r | |
| 258 | EFI_STATUS\r | |
| 259 | CheckIfErased(\r | |
| 260 | IN UINT8 *DstBufferPtr,\r | |
| 261 | IN UINTN NumBytes\r | |
| 262 | );\r | |
| 263 | \r | |
| 264 | EFI_STATUS\r | |
| 265 | CheckIfFlashIsReadyForWrite (\r | |
| 266 | IN UINT8 *DstBufferPtr,\r | |
| 267 | IN UINT8 *SrcBufferPtr,\r | |
| 268 | IN UINTN NumBytes\r | |
| 269 | );\r |