projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| 3cbfba02 DW |
1 | #\r |
| 2 | #\r | |
| 3 | # Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved\r | |
| 4 | # \r\r | |
| 9dc8036d MK |
5 | # SPDX-License-Identifier: BSD-2-Clause-Patent\r |
| 6 | \r | |
| 3cbfba02 DW |
7 | # \r\r |
| 8 | #\r | |
| 9 | #\r | |
| 10 | #Module Name:\r | |
| 11 | #\r | |
| 12 | # CpuIA32.c\r | |
| 13 | #\r | |
| 14 | #Abstract:\r | |
| 15 | #\r | |
| 16 | #--*/\r | |
| 17 | \r | |
| 18 | ##include "CpuIA32.h"\r | |
| 19 | #include "EfiBind.h"\r | |
| 20 | \r | |
| 21 | #---------------------------------------------------------------------------\r | |
| 22 | .586p:\r | |
| 23 | #.MODEL flat,C\r | |
| 24 | .code:\r | |
| 25 | \r | |
| 26 | #---------------------------------------------------------------------------\r | |
| 27 | \r | |
| 28 | .globl ASM_PFX(EfiHalt)\r | |
| 29 | .globl ASM_PFX(EfiWbinvd)\r | |
| 30 | .globl ASM_PFX(EfiInvd)\r | |
| 31 | .globl ASM_PFX(EfiCpuid)\r | |
| 32 | .globl ASM_PFX(EfiReadMsr)\r | |
| 33 | .globl ASM_PFX(EfiWriteMsr)\r | |
| 34 | .globl ASM_PFX(EfiReadTsc)\r | |
| 35 | .globl ASM_PFX(EfiDisableCache)\r | |
| 36 | .globl ASM_PFX(EfiEnableCache)\r | |
| 37 | .globl ASM_PFX(EfiGetEflags)\r | |
| 38 | .globl ASM_PFX(EfiDisableInterrupts)\r | |
| 39 | .globl ASM_PFX(EfiEnableInterrupts)\r | |
| 40 | .globl ASM_PFX(EfiCpuidExt)\r | |
| 41 | \r | |
| 42 | \r | |
| 43 | #VOID\r | |
| 44 | #EfiHalt (\r | |
| 45 | # VOID\r | |
| 46 | #)\r | |
| 47 | ASM_PFX(EfiHalt):\r | |
| 48 | hlt\r | |
| 49 | ret\r | |
| 50 | #EfiHalt ENDP\r | |
| 51 | \r | |
| 52 | #VOID\r | |
| 53 | #EfiWbinvd (\r | |
| 54 | # VOID\r | |
| 55 | #)\r | |
| 56 | ASM_PFX(EfiWbinvd):\r | |
| 57 | wbinvd\r | |
| 58 | ret\r | |
| 59 | #EfiWbinvd ENDP\r | |
| 60 | \r | |
| 61 | #VOID\r | |
| 62 | #EfiInvd (\r | |
| 63 | # VOID\r | |
| 64 | #)\r | |
| 65 | ASM_PFX(EfiInvd):\r | |
| 66 | invd\r | |
| 67 | ret\r | |
| 68 | #EfiInvd ENDP\r | |
| 69 | \r | |
| 70 | #VOID\r | |
| 71 | #EfiCpuid (IN UINT32 RegisterInEax,\r | |
| 72 | # OUT EFI_CPUID_REGISTER *Reg OPTIONAL)\r | |
| 73 | ASM_PFX(EfiCpuid):\r | |
| 74 | pushl %ebp\r | |
| 75 | movl %esp, %ebp\r | |
| 76 | pushl %ebx\r | |
| 77 | pushl %esi\r | |
| 78 | pushl %edi\r | |
| 79 | pushal\r | |
| 80 | \r | |
| 81 | movl 8(%ebp), %eax #RegisterInEax\r | |
| 82 | cpuid\r | |
| 83 | cmpl $0, 0xC(%ebp) # Reg\r | |
| 84 | je L1\r | |
| 85 | movl 0xC(%ebp), %edi # Reg\r | |
| 86 | \r | |
| 87 | movl %eax, (%edi) # Reg->RegEax\r | |
| 88 | movl %ebx, 4(%edi) # Reg->RegEbx\r | |
| 89 | movl %ecx, 8(%edi) # Reg->RegEcx\r | |
| 90 | movl %edx, 0xC(%edi) # Reg->RegEdx\r | |
| 91 | \r | |
| 92 | L1:\r | |
| 93 | popal\r | |
| 94 | popl %edi\r | |
| 95 | popl %esi\r | |
| 96 | popl %ebx\r | |
| 97 | popl %ebp\r | |
| 98 | \r | |
| 99 | ret\r | |
| 100 | #EfiCpuid ENDP\r | |
| 101 | \r | |
| 102 | \r | |
| 103 | #UINT64\r | |
| 104 | #EfiReadMsr (\r | |
| 105 | # IN UINT32 Index\r | |
| 106 | # );\r | |
| 107 | ASM_PFX(EfiReadMsr):\r | |
| 108 | movl 4(%esp), %ecx # Index\r | |
| 109 | rdmsr\r | |
| 110 | ret\r | |
| 111 | #EfiReadMsr ENDP\r | |
| 112 | \r | |
| 113 | #VOID\r | |
| 114 | #EfiWriteMsr (\r | |
| 115 | # IN UINT32 Index,\r | |
| 116 | # IN UINT64 Value\r | |
| 117 | # );\r | |
| 118 | ASM_PFX(EfiWriteMsr):\r | |
| 119 | movl 4(%esp), %ecx # Index\r | |
| 120 | movl 8(%esp), %eax # DWORD PTR Value[0]\r | |
| 121 | movl 0xC(%esp), %edx # DWORD PTR Value[4]\r | |
| 122 | wrmsr\r | |
| 123 | ret\r | |
| 124 | #EfiWriteMsr ENDP\r | |
| 125 | \r | |
| 126 | #UINT64\r | |
| 127 | #EfiReadTsc (\r | |
| 128 | # VOID\r | |
| 129 | # )\r | |
| 130 | ASM_PFX(EfiReadTsc):\r | |
| 131 | rdtsc\r | |
| 132 | ret\r | |
| 133 | #EfiReadTsc ENDP\r | |
| 134 | \r | |
| 135 | #VOID\r | |
| 136 | #EfiDisableCache (\r | |
| 137 | # VOID\r | |
| 138 | #)\r | |
| 139 | ASM_PFX(EfiDisableCache):\r | |
| 140 | movl %cr0, %eax\r | |
| 141 | bswapl %eax\r | |
| 142 | andb $0x60, %al\r | |
| 143 | cmpb $0x60, %al\r | |
| 144 | je L2\r | |
| 145 | movl %cr0, %eax\r | |
| 146 | orl $0x60000000, %eax\r | |
| 147 | movl %eax, %cr0\r | |
| 148 | wbinvd\r | |
| 149 | L2:\r | |
| 150 | ret\r | |
| 151 | #EfiDisableCache ENDP\r | |
| 152 | \r | |
| 153 | #VOID\r | |
| 154 | #EfiEnableCache (\r | |
| 155 | # VOID\r | |
| 156 | # )\r | |
| 157 | ASM_PFX(EfiEnableCache):\r | |
| 158 | wbinvd\r | |
| 159 | movl %cr0, %eax\r | |
| 160 | andl $0x9fffffff, %eax\r | |
| 161 | movl %eax, %cr0\r | |
| 162 | ret\r | |
| 163 | #EfiEnableCache ENDP\r | |
| 164 | \r | |
| 165 | #UINT32\r | |
| 166 | #EfiGetEflags (\r | |
| 167 | # VOID\r | |
| 168 | # )\r | |
| 169 | ASM_PFX(EfiGetEflags):\r | |
| 170 | pushfl\r | |
| 171 | popl %eax\r | |
| 172 | ret\r | |
| 173 | #EfiGetEflags ENDP\r | |
| 174 | \r | |
| 175 | #VOID\r | |
| 176 | #EfiDisableInterrupts (\r | |
| 177 | # VOID\r | |
| 178 | # )\r | |
| 179 | ASM_PFX(EfiDisableInterrupts):\r | |
| 180 | cli\r | |
| 181 | ret\r | |
| 182 | #EfiDisableInterrupts ENDP\r | |
| 183 | \r | |
| 184 | #VOID\r | |
| 185 | #EfiEnableInterrupts (\r | |
| 186 | # VOID\r | |
| 187 | # )\r | |
| 188 | ASM_PFX(EfiEnableInterrupts):\r | |
| 189 | sti\r | |
| 190 | ret\r | |
| 191 | #EfiEnableInterrupts ENDP\r | |
| 192 | \r | |
| 193 | #VOID\r | |
| 194 | #EfiCpuidExt (\r | |
| 195 | # IN UINT32 RegisterInEax,\r | |
| 196 | # IN UINT32 CacheLevel,\r | |
| 197 | # OUT EFI_CPUID_REGISTER *Regs\r | |
| 198 | # )\r | |
| 199 | ASM_PFX(EfiCpuidExt):\r | |
| 200 | push %ebx\r | |
| 201 | push %edi\r | |
| 202 | push %esi\r | |
| 203 | pushal\r | |
| 204 | \r | |
| 205 | movl 0x30(%esp), %eax # RegisterInEax\r | |
| 206 | movl 0x34(%esp), %ecx # CacheLevel\r | |
| 207 | cpuid\r | |
| 208 | movl 0x38(%esp), %edi # DWORD PTR Regs\r | |
| 209 | \r | |
| 210 | movl %eax, (%edi) # Reg->RegEax\r | |
| 211 | movl %ebx, 4(%edi) # Reg->RegEbx\r | |
| 212 | movl %ecx, 8(%edi) # Reg->RegEcx\r | |
| 213 | movl %edx, 0xC(%edi) # Reg->RegEdx\r | |
| 214 | \r | |
| 215 | popal\r | |
| 216 | pop %esi\r | |
| 217 | pop %edi\r | |
| 218 | pop %ebx\r | |
| 219 | ret\r | |
| 220 | #EfiCpuidExt ENDP\r | |
| 221 | \r | |
| 222 | \r | |
| 223 | \r |