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Vlv2TbltDevicePkg: Sync FLASH libraries from UDK2017 branch
[mirror_edk2.git] / Vlv2TbltDevicePkg / Library / FlashDeviceLib / SpiChipDefinitions.h
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7a0a32f1
JY		 1/** @file\r
2\r
3 Copyright (c) 2004 - 2016, Intel Corporation. All rights reserved.<BR>\r
4\r
5 This program and the accompanying materials are licensed and made available under\r
6 the terms and conditions of the BSD License that accompanies this distribution.\r
7 The full text of the license may be found at\r
8 http://opensource.org/licenses/bsd-license.php.\r
9\r
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
3cbfba02 12\r
3cbfba02
DW		 13\r
14\r
15**/\r
16\r
17#include <Library/SpiFlash.H>\r
18\r
7a0a32f1 19#define FLASH_SIZE 0x400000\r
27f44846 20#define FLASH_DEVICE_BASE_ADDRESS (0xFFFFFFFF-FLASH_SIZE+1)\r
3cbfba02
DW		 21\r
22//\r
23// Serial Flash device initialization data table provided to the\r
24// Intel(R) SPI Host Controller Compatibility Interface.\r
25//\r
26SPI_INIT_TABLE mInitTable[] = {\r
27 {\r
28 SF_VENDOR_ID_WINBOND, // VendorId\r
29 SF_DEVICE_ID0_W25QXX, // DeviceId 0\r
30 SF_DEVICE_ID1_W25Q64, // DeviceId 1\r
31 {\r
32 SF_INST_WREN, // Prefix Opcode 0: Write Enable\r
33 SF_INST_EWSR // Prefix Opcode 1: Enable Write Status Register\r
34 },\r
35 {\r
36 {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID\r
37 {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData }, // Opcode 1: Read\r
38 {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register\r
39 {EnumSpiOpcodeRead, SF_INST_SFDP, EnumSpiCycle50MHz, EnumSpiOperationDiscoveryParameters}, // Opcode 3: Serial Flash Discovery Parameters\r
40 {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)\r
41 {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB\r
42 {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program\r
43 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register\r
44 },\r
45\r
46 //\r
47 // The offset of the start of the BIOS image in flash. This value is platform specific\r
48 // and depends on the system flash map. If BIOS size is bigger than flash return -1.\r
49 //\r
50 ((WINBOND_W25Q64_SIZE >= FLASH_SIZE) ? WINBOND_W25Q64_SIZE - FLASH_SIZE : (UINTN) (-1)),\r
51\r
52 //\r
53 // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.\r
54 //\r
55 FLASH_SIZE\r
56 },\r
57 {\r
58 SF_VENDOR_ID_ATMEL, // VendorId\r
59 SF_DEVICE_ID0_AT25DF321A, // DeviceId 0\r
60 SF_DEVICE_ID1_AT25DF321A, // DeviceId 1\r
61 {\r
62 SF_INST_WREN, // Prefix Opcode 0: Write Enable\r
63 SF_INST_WREN // Prefix Opcode 1: Write Enable (this part doesn't support EWSR).\r
64 },\r
65 {\r
66 {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID\r
67 {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData }, // Opcode 1: Read\r
68 {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register\r
69 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI, EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3: Write Disable\r
70 {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)\r
71 {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (32KB)\r
72 {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program\r
73 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register\r
74 },\r
75\r
76 //\r
77 // The offset of the start of the BIOS image in flash. This value is platform specific\r
78 // and depends on the system flash map. If BIOS size is bigger than flash return -1.\r
79 //\r
80 ((ATMEL_AT25DF321A_SIZE >= FLASH_SIZE) ? ATMEL_AT25DF321A_SIZE - FLASH_SIZE : (UINTN) (-1)),\r
81\r
82 //\r
83 // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.\r
84 //\r
85 FLASH_SIZE\r
86 },\r
87 {\r
88 SF_VENDOR_ID_ATMEL, // VendorId\r
89 SF_DEVICE_ID0_AT26DF321, // DeviceId 0\r
90 SF_DEVICE_ID1_AT26DF321, // DeviceId 1\r
91 {\r
92 SF_INST_WREN, // Prefix Opcode 0: Write Enable\r
93 SF_INST_WREN // Prefix Opcode 1: Write Enable (this part doesn't support EWSR).\r
94 },\r
95 {\r
96 {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID\r
97 {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData }, // Opcode 1: Read\r
98 {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register\r
99 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI, EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3: Write Disable\r
100 {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)\r
101 {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (32KB)\r
102 {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program\r
103 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register\r
104 },\r
105\r
106 //\r
107 // The offset of the start of the BIOS image in flash. This value is platform specific\r
108 // and depends on the system flash map. If BIOS size is bigger than flash return -1.\r
109 //\r
110 ((ATMEL_AT26DF321_SIZE >= FLASH_SIZE) ? ATMEL_AT26DF321_SIZE - FLASH_SIZE : (UINTN) (-1)),\r
111\r
112 //\r
113 // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.\r
114 //\r
115 FLASH_SIZE\r
116 },\r
117 {\r
118 SF_VENDOR_ID_ATMEL, // VendorId\r
119 SF_DEVICE_ID0_AT25DF641, // DeviceId 0\r
120 SF_DEVICE_ID1_AT25DF641, // DeviceId 1\r
121 {\r
122 SF_INST_WREN, // Prefix Opcode 0: Write Enable\r
123 SF_INST_WREN // Prefix Opcode 1: Write Enable (this part doesn't support EWSR).\r
124 },\r
125 {\r
126 {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID\r
127 {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData }, // Opcode 1: Read\r
128 {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register\r
129 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI, EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3: Write Disable\r
130 {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)\r
131 {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (32KB)\r
132 {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program\r
133 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register\r
134 },\r
135\r
136 //\r
137 // The offset of the start of the BIOS image in flash. This value is platform specific\r
138 // and depends on the system flash map. If BIOS size is bigger than flash return -1.\r
139 //\r
140 ((ATMEL_AT25DF641_SIZE >= FLASH_SIZE) ? ATMEL_AT25DF641_SIZE - FLASH_SIZE : (UINTN) (-1)),\r
141\r
142 //\r
143 // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.\r
144 //\r
145 FLASH_SIZE\r
146 },\r
147 {\r
148 SF_VENDOR_ID_WINBOND, // VendorId\r
149 SF_DEVICE_ID0_W25QXX, // DeviceId 0\r
150 SF_DEVICE_ID1_W25Q16, // DeviceId 1\r
151 {\r
152 SF_INST_WREN, // Prefix Opcode 0: Write Enable\r
153 SF_INST_EWSR // Prefix Opcode 1: Enable Write Status Register\r
154 },\r
155 {\r
156 {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID\r
157 {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData }, // Opcode 1: Read\r
158 {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register\r
159 {EnumSpiOpcodeRead, SF_INST_SFDP, EnumSpiCycle50MHz, EnumSpiOperationDiscoveryParameters}, // Opcode 3: Serial Flash Discovery Parameters\r
160 {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)\r
161 {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB\r
162 {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program\r
163 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register\r
164 },\r
165\r
166 //\r
167 // The offset of the start of the BIOS image in flash. This value is platform specific\r
168 // and depends on the system flash map. If BIOS size is bigger than flash return -1.\r
169 //\r
170 ((WINBOND_W25Q16_SIZE >= FLASH_SIZE) ? WINBOND_W25Q16_SIZE - FLASH_SIZE : (UINTN) (-1)),\r
171\r
172 //\r
173 // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.\r
174 //\r
175 FLASH_SIZE\r
176 },\r
177 {\r
178 SF_VENDOR_ID_WINBOND, // VendorId\r
179 SF_DEVICE_ID0_W25QXX, // DeviceId 0\r
180 SF_DEVICE_ID1_W25Q32, // DeviceId 1\r
181 {\r
182 SF_INST_WREN, // Prefix Opcode 0: Write Enable\r
183 SF_INST_EWSR // Prefix Opcode 1: Enable Write Status Register.\r
184 },\r
185 {\r
186 {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID\r
187 {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData }, // Opcode 1: Read\r
188 {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register\r
189 {EnumSpiOpcodeRead, SF_INST_SFDP, EnumSpiCycle50MHz, EnumSpiOperationDiscoveryParameters}, // Opcode 3: Serial Flash Discovery Parameters\r
190 {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)\r
191 {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB\r
192 {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program\r
193 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register\r
194 },\r
195\r
196 //\r
197 // The offset of the start of the BIOS image in flash. This value is platform specific\r
198 // and depends on the system flash map. If BIOS size is bigger than flash return -1.\r
199 //\r
200 ((WINBOND_W25Q32_SIZE >= FLASH_SIZE) ? WINBOND_W25Q32_SIZE - FLASH_SIZE : (UINTN) (-1)),\r
201\r
202 //\r
203 // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.\r
204 //\r
205 FLASH_SIZE\r
206 },\r
207 {\r
208 SF_VENDOR_ID_WINBOND, // VendorId\r
209 SF_DEVICE_ID0_W25XXX, // DeviceId 0\r
210 SF_DEVICE_ID1_W25X32, // DeviceId 1\r
211 {\r
212 SF_INST_WREN, // Prefix Opcode 0: Write Enable\r
213 SF_INST_EWSR // Prefix Opcode 1: Enable Write Status Register\r
214 },\r
215 {\r
216 {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID\r
217 {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData }, // Opcode 1: Read\r
218 {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register\r
219 {EnumSpiOpcodeRead, SF_INST_SFDP, EnumSpiCycle50MHz, EnumSpiOperationDiscoveryParameters}, // Opcode 3: Serial Flash Discovery Parameters\r
220 {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)\r
221 {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB\r
222 {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program\r
223 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register\r
224 },\r
225\r
226 //\r
227 // The offset of the start of the BIOS image in flash. This value is platform specific\r
228 // and depends on the system flash map. If BIOS size is bigger than flash return -1.\r
229 //\r
230 ((WINBOND_W25X32_SIZE >= FLASH_SIZE) ? WINBOND_W25X32_SIZE - FLASH_SIZE : (UINTN) (-1)),\r
231\r
232 //\r
233 // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.\r
234 //\r
235 FLASH_SIZE\r
236 },\r
237 {\r
238 SF_VENDOR_ID_WINBOND, // VendorId\r
239 SF_DEVICE_ID0_W25XXX, // DeviceId 0\r
240 SF_DEVICE_ID1_W25X64, // DeviceId 1\r
241 {\r
242 SF_INST_WREN, // Prefix Opcode 0: Write Enable\r
243 SF_INST_EWSR // Prefix Opcode 1: Enable Write Status Register\r
244 },\r
245 {\r
246 {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID\r
247 {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData }, // Opcode 1: Read\r
248 {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register\r
249 {EnumSpiOpcodeRead, SF_INST_SFDP, EnumSpiCycle50MHz, EnumSpiOperationDiscoveryParameters}, // Opcode 3: Serial Flash Discovery Parameters\r
250 {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)\r
251 {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB\r
252 {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program\r
253 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register\r
254 },\r
255\r
256 //\r
257 // The offset of the start of the BIOS image in flash. This value is platform specific\r
258 // and depends on the system flash map. If BIOS size is bigger than flash return -1.\r
259 //\r
260 ((WINBOND_W25X64_SIZE >= FLASH_SIZE) ? WINBOND_W25X64_SIZE - FLASH_SIZE : (UINTN) (-1)),\r
261\r
262 //\r
263 // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.\r
264 //\r
265 FLASH_SIZE\r
266 },\r
267 {\r
268 SF_VENDOR_ID_WINBOND, // VendorId\r
269 SF_DEVICE_ID0_W25QXX, // DeviceId 0\r
270 SF_DEVICE_ID1_W25Q128, // DeviceId 1\r
271 {\r
272 SF_INST_WREN, // Prefix Opcode 0: Write Enable\r
273 SF_INST_EWSR // Prefix Opcode 1: Enable Write Status Register\r
274 },\r
275 {\r
276 {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID\r
277 {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData }, // Opcode 1: Read\r
278 {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register\r
279 {EnumSpiOpcodeRead, SF_INST_SFDP, EnumSpiCycle50MHz, EnumSpiOperationDiscoveryParameters}, // Opcode 3: Serial Flash Discovery Parameters\r
280 {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)\r
281 {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB\r
282 {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program\r
283 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register\r
284 },\r
285\r
286 //\r
287 // The offset of the start of the BIOS image in flash. This value is platform specific\r
288 // and depends on the system flash map. If BIOS size is bigger than flash return -1.\r
289 //\r
290 ((WINBOND_W25Q128_SIZE >= FLASH_SIZE) ? WINBOND_W25Q128_SIZE - FLASH_SIZE : (UINTN) (-1)),\r
291\r
292 //\r
293 // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.\r
294 //\r
295 FLASH_SIZE\r
296 },\r
297 {\r
298 SF_VENDOR_ID_MACRONIX, // VendorId\r
299 SF_DEVICE_ID0_MX25LXX, // DeviceId 0\r
300 SF_DEVICE_ID1_MX25L16, // DeviceId 1\r
301 {\r
302 SF_INST_WREN, // Prefix Opcode 0: Write Enable\r
303 SF_INST_EWSR // Prefix Opcode 1: Write Enable (this part doesn't support EWSR).\r
304 },\r
305 {\r
306 {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID\r
307 {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle33MHz, EnumSpiOperationReadData }, // Opcode 1: Read\r
308 {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register\r
309 {EnumSpiOpcodeRead, SF_INST_SFDP, EnumSpiCycle50MHz, EnumSpiOperationDiscoveryParameters}, // Opcode 3: Serial Flash Discovery Parameters\r
310 {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)\r
311 {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB\r
312 {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program\r
313 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register\r
314 },\r
315\r
316 //\r
317 // The offset of the start of the BIOS image in flash. This value is platform specific\r
318 // and depends on the system flash map. If BIOS size is bigger than flash return -1.\r
319 //\r
320 ((MACRONIX_MX25L16_SIZE >= FLASH_SIZE) ? MACRONIX_MX25L16_SIZE - FLASH_SIZE : (UINTN) (-1)),\r
321\r
322 //\r
323 // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.\r
324 //\r
325 FLASH_SIZE\r
326 },\r
327 {\r
328 SF_VENDOR_ID_MACRONIX, // VendorId\r
329 SF_DEVICE_ID0_MX25LXX, // DeviceId 0\r
330 SF_DEVICE_ID1_MX25L32, // DeviceId 1\r
331 {\r
332 SF_INST_WREN, // Prefix Opcode 0: Write Enable\r
333 SF_INST_EWSR // Prefix Opcode 1: Write Enable (this part doesn't support EWSR).\r
334 },\r
335 {\r
336 {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID\r
337 {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle33MHz, EnumSpiOperationReadData }, // Opcode 1: Read\r
338 {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register\r
339 {EnumSpiOpcodeRead, SF_INST_SFDP, EnumSpiCycle50MHz, EnumSpiOperationDiscoveryParameters}, // Opcode 3: Serial Flash Discovery Parameters\r
340 {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)\r
341 {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB\r
342 {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program\r
343 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register\r
344 },\r
345\r
346 //\r
347 // The offset of the start of the BIOS image in flash. This value is platform specific\r
348 // and depends on the system flash map. If BIOS size is bigger than flash return -1.\r
349 //\r
350 ((MACRONIX_MX25L32_SIZE >= FLASH_SIZE) ? MACRONIX_MX25L32_SIZE - FLASH_SIZE : (UINTN) (-1)),\r
351\r
352 //\r
353 // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.\r
354 //\r
355 FLASH_SIZE\r
356 },\r
357 {\r
358 SF_VENDOR_ID_MACRONIX, // VendorId\r
359 SF_DEVICE_ID0_MX25LXX, // DeviceId 0\r
360 SF_DEVICE_ID1_MX25L64, // DeviceId 1\r
361 {\r
362 SF_INST_WREN, // Prefix Opcode 0: Write Enable\r
363 SF_INST_EWSR // Prefix Opcode 1: Write Enable (this part doesn't support EWSR)\r
364 },\r
365 {\r
366 {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID\r
367 {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle33MHz, EnumSpiOperationReadData }, // Opcode 1: Read\r
368 {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register\r
369 {EnumSpiOpcodeRead, SF_INST_SFDP, EnumSpiCycle50MHz, EnumSpiOperationDiscoveryParameters}, // Opcode 3: Serial Flash Discovery Parameters\r
370 {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)\r
371 {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB\r
372 {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program\r
373 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register\r
374 },\r
375\r
376 //\r
377 // The offset of the start of the BIOS image in flash. This value is platform specific\r
378 // and depends on the system flash map. If BIOS size is bigger than flash return -1.\r
379 //\r
380 ((MACRONIX_MX25L64_SIZE >= FLASH_SIZE) ? MACRONIX_MX25L64_SIZE - FLASH_SIZE : (UINTN) (-1)),\r
381\r
382 //\r
383 // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.\r
384 //\r
385 FLASH_SIZE\r
386 },\r
387 {\r
388 SF_VENDOR_ID_MACRONIX, // VendorId\r
389 SF_DEVICE_ID0_MX25LXX, // DeviceId 0\r
390 SF_DEVICE_ID1_MX25L128, // DeviceId 1\r
391 {\r
392 SF_INST_WREN, // Prefix Opcode 0: Write Enable\r
393 SF_INST_EWSR // Prefix Opcode 1: Write Enable (this part doesn't support EWSR)\r
394 },\r
395 {\r
396 {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID\r
397 {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle33MHz, EnumSpiOperationReadData }, // Opcode 1: Read\r
398 {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register\r
399 {EnumSpiOpcodeRead, SF_INST_SFDP, EnumSpiCycle50MHz, EnumSpiOperationDiscoveryParameters}, // Opcode 3: Serial Flash Discovery Parameters\r
400 {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)\r
401 {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB\r
402 {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program\r
403 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register\r
404 },\r
405\r
406 //\r
407 // The offset of the start of the BIOS image in flash. This value is platform specific\r
408 // and depends on the system flash map. If BIOS size is bigger than flash return -1.\r
409 //\r
410 ((MACRONIX_MX25L128_SIZE >= FLASH_SIZE) ? MACRONIX_MX25L128_SIZE - FLASH_SIZE : (UINTN) (-1)),\r
411\r
412 //\r
413 // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.\r
414 //\r
415 FLASH_SIZE\r
416 },\r
417 {\r
418 SF_VENDOR_ID_MACRONIX, // VendorId\r
419 SF_DEVICE_ID0_MX25UXX, // DeviceId 0\r
420 SF_DEVICE_ID1_MX25U6435F, // DeviceId 1\r
421 {\r
422 SF_INST_WREN, // Prefix Opcode 0: Write Enable\r
423 SF_INST_EWSR // Prefix Opcode 1: Write Enable (this part doesn't support EWSR)\r
424 },\r
425 {\r
426 {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID\r
427 {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle33MHz, EnumSpiOperationReadData }, // Opcode 1: Read\r
428 {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register\r
429 {EnumSpiOpcodeRead, SF_INST_SFDP, EnumSpiCycle50MHz, EnumSpiOperationDiscoveryParameters}, // Opcode 3: Serial Flash Discovery Parameters\r
430 {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)\r
431 {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB\r
432 {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program\r
433 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register\r
434 },\r
435\r
436 //\r
437 // The offset of the start of the BIOS image in flash. This value is platform specific\r
438 // and depends on the system flash map. If BIOS size is bigger than flash return -1.\r
439 //\r
440 ((MACRONIX_MX25U64_SIZE >= FLASH_SIZE) ? MACRONIX_MX25U64_SIZE - FLASH_SIZE : (UINTN) (-1)),\r
441\r
442 //\r
443 // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.\r
444 //\r
445 FLASH_SIZE\r
446 },\r
447 {\r
448 SF_VENDOR_ID_SST, // VendorId\r
449 SF_DEVICE_ID0_SST25VF0XXX,// DeviceId 0\r
450 SF_DEVICE_ID1_SST25VF016B,// DeviceId 1\r
451 {\r
452 SF_INST_WREN, // Prefix Opcode 0: Write Enable\r
453 SF_INST_EWSR // Prefix Opcode 1: Enable Write Status Register\r
454 },\r
455 {\r
456 {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID\r
457 {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle20MHz, EnumSpiOperationReadData }, // Opcode 1: Read\r
458 {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register\r
459 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI, EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3: Write Disable\r
460 {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)\r
461 {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (32KB)\r
462 {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program\r
463 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register\r
464 },\r
465\r
466 //\r
467 // The offset of the start of the BIOS image in flash. This value is platform specific\r
468 // and depends on the system flash map. If BIOS size is bigger than flash return -1.\r
469 //\r
470 ((SST_SST25VF016B_SIZE >= FLASH_SIZE) ? SST_SST25VF016B_SIZE - FLASH_SIZE : (UINTN) (-1)),\r
471\r
472 //\r
473 // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.\r
474 //\r
475 FLASH_SIZE\r
476 },\r
477 {\r
478 SF_VENDOR_ID_SST, // VendorId\r
479 SF_DEVICE_ID0_SST25VF0XXX,// DeviceId 0\r
480 SF_DEVICE_ID1_SST25VF064C,// DeviceId 1\r
481 {\r
482 SF_INST_WREN, // Prefix Opcode 0: Write Enable\r
483 SF_INST_EWSR // Prefix Opcode 1: Enable Write Status Register\r
484 },\r
485 {\r
486 {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID\r
487 {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle20MHz, EnumSpiOperationReadData }, // Opcode 1: Read\r
488 {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register\r
489 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI, EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3: Write Disable\r
490 {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)\r
491 {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (32KB)\r
492 {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program\r
493 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register\r
494 },\r
495\r
496 //\r
497 // The offset of the start of the BIOS image in flash. This value is platform specific\r
498 // and depends on the system flash map. If BIOS size is bigger than flash return -1.\r
499 //\r
500 ((SST_SST25VF064C_SIZE >= FLASH_SIZE) ? SST_SST25VF064C_SIZE - FLASH_SIZE : (UINTN) (-1)),\r
501\r
502 //\r
503 // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.\r
504 //\r
505 FLASH_SIZE\r
506 },\r
507 {\r
508 //\r
509 // Minnow2 SPI type\r
510 //\r
511 SF_VENDOR_ID_NUMONYX, // VendorId\r
512 SF_DEVICE_ID0_N25Q064, // DeviceId 0\r
513 SF_DEVICE_ID1_N25Q064, // DeviceId 1\r
514 {\r
515 SF_INST_WREN, // Prefix Opcode 0: Write Enable\r
516 SF_INST_WREN // Prefix Opcode 1: Write Enable (this part doesn't support EWSR)\r
517 },\r
518 {\r
519 {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle20MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID\r
520 {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle20MHz, EnumSpiOperationReadData }, // Opcode 1: Read\r
521 {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle20MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register\r
522 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI, EnumSpiCycle20MHz, EnumSpiOperationWriteDisable }, // Opcode 3: Write Disable\r
523 {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle20MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)\r
524 {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle20MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB\r
525 {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle20MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program\r
526 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle20MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register\r
527 },\r
528\r
529 //\r
530 // The offset of the start of the BIOS image in flash. This value is platform specific\r
531 // and depends on the system flash map. If BIOS size is bigger than flash return -1.\r
532 //\r
533 ((NUMONYX_N25Q064_SIZE >= FLASH_SIZE) ? NUMONYX_N25Q064_SIZE - FLASH_SIZE : (UINTN) (-1)),\r
534\r
535 //\r
536 // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.\r
537 //\r
538 FLASH_SIZE\r
539 },\r
540 {\r
541 SF_VENDOR_ID_NUMONYX, // VendorId\r
542 SF_DEVICE_ID0_M25PXXX, // DeviceId 0\r
543 SF_DEVICE_ID1_M25PX16, // DeviceId 1\r
544 {\r
545 SF_INST_WREN, // Prefix Opcode 0: Write Enable\r
546 SF_INST_WREN // Prefix Opcode 1: Write Enable (this part doesn't support EWSR).\r
547 },\r
548 {\r
549 {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID\r
550 {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle33MHz, EnumSpiOperationReadData }, // Opcode 1: Read\r
551 {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register\r
552 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI, EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3: Write Disable\r
553 {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)\r
554 {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB\r
555 {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program\r
556 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register\r
557 },\r
558\r
559 //\r
560 // The offset of the start of the BIOS image in flash. This value is platform specific\r
561 // and depends on the system flash map. If BIOS size is bigger than flash return -1.\r
562 //\r
563 ((NUMONYX_M25PX16_SIZE >= FLASH_SIZE) ? NUMONYX_M25PX16_SIZE - FLASH_SIZE : (UINTN) (-1)),\r
564\r
565 //\r
566 // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.\r
567 //\r
568 FLASH_SIZE\r
569 },\r
570 {\r
571 SF_VENDOR_ID_NUMONYX, // VendorId\r
572 SF_DEVICE_ID0_N25QXXX, // DeviceId 0\r
573 SF_DEVICE_ID1_N25Q032, // DeviceId 1\r
574 {\r
575 SF_INST_WREN, // Prefix Opcode 0: Write Enable\r
576 SF_INST_WREN // Prefix Opcode 1: Write Enable (this part doesn't support EWSR).\r
577 },\r
578 {\r
579 {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID\r
580 {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle33MHz, EnumSpiOperationReadData }, // Opcode 1: Read\r
581 {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register\r
582 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI, EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3: Write Disable\r
583 {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)\r
584 {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB\r
585 {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program\r
586 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register\r
587 },\r
588\r
589 //\r
590 // The offset of the start of the BIOS image in flash. This value is platform specific\r
591 // and depends on the system flash map. If BIOS size is bigger than flash return -1.\r
592 //\r
593 ((NUMONYX_N25Q032_SIZE >= FLASH_SIZE) ? NUMONYX_N25Q032_SIZE - FLASH_SIZE : (UINTN) (-1)),\r
594\r
595 //\r
596 // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.\r
597 //\r
598 FLASH_SIZE\r
599 },\r
600 {\r
601 SF_VENDOR_ID_NUMONYX, // VendorId\r
602 SF_DEVICE_ID0_M25PXXX, // DeviceId 0\r
603 SF_DEVICE_ID1_M25PX32, // DeviceId 1\r
604 {\r
605 SF_INST_WREN, // Prefix Opcode 0: Write Enable\r
606 SF_INST_WREN // Prefix Opcode 1: Write Enable (this part doesn't support EWSR).\r
607 },\r
608 {\r
609 {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID\r
610 {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle33MHz, EnumSpiOperationReadData }, // Opcode 1: Read\r
611 {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register\r
612 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI, EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3: Write Disable\r
613 {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)\r
614 {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB\r
615 {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program\r
616 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register\r
617 },\r
618\r
619 //\r
620 // The offset of the start of the BIOS image in flash. This value is platform specific\r
621 // and depends on the system flash map. If BIOS size is bigger than flash return -1.\r
622 //\r
623 ((NUMONYX_M25PX32_SIZE >= FLASH_SIZE) ? NUMONYX_M25PX32_SIZE - FLASH_SIZE : (UINTN) (-1)),\r
624\r
625 //\r
626 // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.\r
627 //\r
628 FLASH_SIZE\r
629 },\r
630 {\r
631 SF_VENDOR_ID_NUMONYX, // VendorId\r
632 SF_DEVICE_ID0_M25PXXX, // DeviceId 0\r
633 SF_DEVICE_ID1_M25PX64, // DeviceId 1\r
634 {\r
635 SF_INST_WREN, // Prefix Opcode 0: Write Enable\r
636 SF_INST_WREN // Prefix Opcode 1: Write Enable (this part doesn't support EWSR)\r
637 },\r
638 {\r
639 {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID\r
640 {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle33MHz, EnumSpiOperationReadData }, // Opcode 1: Read\r
641 {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register\r
642 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI, EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3: Write Disable\r
643 {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)\r
644 {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB\r
645 {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program\r
646 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register\r
647 },\r
648\r
649 //\r
650 // The offset of the start of the BIOS image in flash. This value is platform specific\r
651 // and depends on the system flash map. If BIOS size is bigger than flash return -1.\r
652 //\r
653 ((NUMONYX_M25PX64_SIZE >= FLASH_SIZE) ? NUMONYX_M25PX64_SIZE - FLASH_SIZE : (UINTN) (-1)),\r
654\r
655 //\r
656 // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.\r
657 //\r
658 FLASH_SIZE\r
659 },\r
660 {\r
661 SF_VENDOR_ID_NUMONYX, // VendorId\r
662 SF_DEVICE_ID0_N25QXXX, // DeviceId 0\r
663 SF_DEVICE_ID1_N25Q128, // DeviceId 1\r
664 {\r
665 SF_INST_WREN, // Prefix Opcode 0: Write Enable\r
666 SF_INST_WREN // Prefix Opcode 1: Write Enable (this part doesn't support EWSR)\r
667 },\r
668 {\r
669 {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID\r
670 {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle33MHz, EnumSpiOperationReadData }, // Opcode 1: Read\r
671 {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register\r
672 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI, EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3: Write Disable\r
673 {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)\r
674 {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB\r
675 {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program\r
676 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register\r
677 },\r
678\r
679 //\r
680 // The offset of the start of the BIOS image in flash. This value is platform specific\r
681 // and depends on the system flash map. If BIOS size is bigger than flash return -1.\r
682 //\r
683 ((NUMONYX_N25Q128_SIZE >= FLASH_SIZE) ? NUMONYX_N25Q128_SIZE - FLASH_SIZE : (UINTN) (-1)),\r
684\r
685 //\r
686 // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.\r
687 //\r
688 FLASH_SIZE\r
689 },\r
690 {\r
691 SF_VENDOR_ID_EON, // VendorId\r
692 SF_DEVICE_ID0_EN25QXX, // DeviceId 0\r
693 SF_DEVICE_ID1_EN25Q16, // DeviceId 1\r
694 {\r
695 SF_INST_WREN, // Prefix Opcode 0: Write Enable\r
696 SF_INST_WREN // Prefix Opcode 1: Write Enable (this part doesn't support EWSR)\r
697 },\r
698 {\r
699 {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID\r
700 {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData }, // Opcode 1: Read\r
701 {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register\r
702 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI, EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3: Write Disable\r
703 {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)\r
704 {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB\r
705 {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program\r
706 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register\r
707 },\r
708\r
709 //\r
710 // The offset of the start of the BIOS image in flash. This value is platform specific\r
711 // and depends on the system flash map. If BIOS size is bigger than flash return -1.\r
712 //\r
713 ((EON_EN25Q16_SIZE >= FLASH_SIZE) ? EON_EN25Q16_SIZE - FLASH_SIZE : (UINTN) (-1)),\r
714\r
715 //\r
716 // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.\r
717 //\r
718 FLASH_SIZE\r
719 },\r
720 {\r
721 SF_VENDOR_ID_EON, // VendorId\r
722 SF_DEVICE_ID0_EN25QXX, // DeviceId 0\r
723 SF_DEVICE_ID1_EN25Q32, // DeviceId 1\r
724 {\r
725 SF_INST_WREN, // Prefix Opcode 0: Write Enable\r
726 SF_INST_WREN // Prefix Opcode 1: Write Enable (this part doesn't support EWSR)\r
727 },\r
728 {\r
729 {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID\r
730 {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle33MHz, EnumSpiOperationReadData }, // Opcode 1: Read\r
731 {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register\r
732 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI, EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3: Write Disable\r
733 {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)\r
734 {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB\r
735 {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program\r
736 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register\r
737 },\r
738\r
739 //\r
740 // The offset of the start of the BIOS image in flash. This value is platform specific\r
741 // and depends on the system flash map. If BIOS size is bigger than flash return -1.\r
742 //\r
743 ((EON_EN25Q32_SIZE >= FLASH_SIZE) ? EON_EN25Q32_SIZE - FLASH_SIZE : (UINTN) (-1)),\r
744\r
745 //\r
746 // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.\r
747 //\r
748 FLASH_SIZE\r
749 },\r
750 {\r
751 SF_VENDOR_ID_EON, // VendorId\r
752 SF_DEVICE_ID0_EN25QXX, // DeviceId 0\r
753 SF_DEVICE_ID1_EN25Q64, // DeviceId 1\r
754 {\r
755 SF_INST_WREN, // Prefix Opcode 0: Write Enable\r
756 SF_INST_WREN // Prefix Opcode 1: Write Enable (this part doesn't support EWSR).\r
757 },\r
758 {\r
759 {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID\r
760 {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData }, // Opcode 1: Read\r
761 {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register\r
762 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI, EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3: Write Disable\r
763 {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)\r
764 {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB\r
765 {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program\r
766 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register\r
767 },\r
768\r
769 //\r
770 // The offset of the start of the BIOS image in flash. This value is platform specific\r
771 // and depends on the system flash map. If BIOS size is bigger than flash return -1.\r
772 //\r
773 ((EON_EN25Q64_SIZE >= FLASH_SIZE) ? EON_EN25Q64_SIZE - FLASH_SIZE : (UINTN) (-1)),\r
774\r
775 //\r
776 // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.\r
777 //\r
778 FLASH_SIZE\r
779 },\r
780 {\r
781 SF_VENDOR_ID_EON, // VendorId\r
782 SF_DEVICE_ID0_EN25QXX, // DeviceId 0\r
783 SF_DEVICE_ID1_EN25Q128, // DeviceId 1\r
784 {\r
785 SF_INST_WREN, // Prefix Opcode 0: Write Enable\r
786 SF_INST_WREN // Prefix Opcode 1: Write Enable (this part doesn't support EWSR)\r
787 },\r
788 {\r
789 {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID\r
790 {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData }, // Opcode 1: Read\r
791 {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register\r
792 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI, EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3: Write Disable\r
793 {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)\r
794 {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB\r
795 {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program\r
796 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register\r
797 },\r
798\r
799 //\r
800 // The offset of the start of the BIOS image in flash. This value is platform specific\r
801 // and depends on the system flash map. If BIOS size is bigger than flash return -1.\r
802 //\r
803 ((EON_EN25Q128_SIZE >= FLASH_SIZE) ? EON_EN25Q128_SIZE - FLASH_SIZE : (UINTN) (-1)),\r
804\r
805 //\r
806 // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.\r
807 //\r
808 FLASH_SIZE\r
809 },\r
810 {\r
811 SF_VENDOR_ID_AMIC, // VendorId\r
812 SF_DEVICE_ID0_A25L016, // DeviceId 0\r
813 SF_DEVICE_ID1_A25L016, // DeviceId 1\r
814 {\r
815 SF_INST_WREN, // Prefix Opcode 0: Write Enable\r
816 SF_INST_WREN // Prefix Opcode 1: Write Enable (this part doesn't support EWSR)\r
817 },\r
818 {\r
819 {EnumSpiOpcodeReadNoAddr, SF_INST_JEDEC_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId }, // Opcode 0: Read ID\r
820 {EnumSpiOpcodeRead, SF_INST_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData }, // Opcode 1: Read\r
821 {EnumSpiOpcodeReadNoAddr, SF_INST_RDSR, EnumSpiCycle50MHz, EnumSpiOperationReadStatus }, // Opcode 2: Read Status Register\r
822 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRDI, EnumSpiCycle50MHz, EnumSpiOperationWriteDisable }, // Opcode 3: Write Disable\r
823 {EnumSpiOpcodeWrite, SF_INST_SERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte }, // Opcode 4: Sector Erase (4KB)\r
824 {EnumSpiOpcodeWrite, SF_INST_64KB_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte }, // Opcode 5: Block Erase (64KB\r
825 {EnumSpiOpcodeWrite, SF_INST_PROG, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, // Opcode 6: Byte Program\r
826 {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus }, // Opcode 7: Write Status Register\r
827 },\r
828\r
829 //\r
830 // The offset of the start of the BIOS image in flash. This value is platform specific\r
831 // and depends on the system flash map. If BIOS size is bigger than flash return -1.\r
832 //\r
833 ((AMIC_A25L16_SIZE >= FLASH_SIZE) ? AMIC_A25L16_SIZE - FLASH_SIZE : (UINTN) (-1)),\r
834\r
835 //\r
836 // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.\r
837 //\r
838 FLASH_SIZE\r
839 }\r
840};\r
7a0a32f1 841\r
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