Vlv2TbltDevicePkg:Signal EndOfDxe Event.

[mirror_edk2.git] / Vlv2TbltDevicePkg / Library / I2CLibPei / I2CAccess.h

/** @file\r
  Misc Registers Definition.\r
  \r
  Copyright (c) 2011  - 2015, Intel Corporation. All rights reserved.<BR>\r
                                                                                   \r
  This program and the accompanying materials are licensed and made available under\r
  the terms and conditions of the BSD License that accompanies this distribution.  \r
  The full text of the license may be found at                                     \r
  http://opensource.org/licenses/bsd-license.php.                                  \r
                                                                                  \r
  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r
  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r
                                                                               \r
--*/\r
\r
#ifndef _I2C_ACCESS_H_\r
#define _I2C_ACCESS_H_\r
\r
#include "I2CIoLibPei.h"\r
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#define DEFAULT_PCI_BUS_NUMBER_PCH             0\r
\r
#define PCI_DEVICE_NUMBER_PCH_LPC              31\r
#define PCI_FUNCTION_NUMBER_PCH_LPC            0\r
\r
#define R_PCH_LPC_ACPI_BASE                    0x40            // ABASE, 16bit\r
#define R_PCH_LPC_ACPI_BASEADR                 0x400           // ABASE, 16bit\r
#define B_PCH_LPC_ACPI_BASE_EN                 BIT1            // Enable Bit\r
#define B_PCH_LPC_ACPI_BASE_BAR                0x0000FF80      // Base Address, 128 Bytes\r
#define V_PCH_ACPI_PM1_TMR_MAX_VAL             0x1000000       // The timer is 24 bit overflow\r
#define B_PCH_ACPI_PM1_TMR_VAL                 0xFFFFFF        // The timer value mask\r
\r
#define R_PCH_ACPI_PM1_TMR                     0x08            // Power Management 1 Timer\r
#define V_PCH_ACPI_PM1_TMR_FREQUENCY           3579545         // Timer Frequency\r
\r
\r
#define PchLpcPciCfg8(Register) I2CLibPeiMmioRead8 (MmPciAddress (0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0, Register))\r
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#define PCIEX_BASE_ADDRESS                     0xE0000000\r
#define PCI_EXPRESS_BASE_ADDRESS               ((VOID *) (UINTN) PCIEX_BASE_ADDRESS)\r
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#define MmPciAddress( Segment, Bus, Device, Function, Register ) \\r
  ( (UINTN)PCI_EXPRESS_BASE_ADDRESS + \\r
    (UINTN)(Bus << 20) + \\r
    (UINTN)(Device << 15) + \\r
    (UINTN)(Function << 12) + \\r
    (UINTN)(Register) \\r
  )\r
#endif\r
\r