projects / mirror_edk2.git / blame
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1 | /** @file\r |
| 2 | I2C PEI Lib Instance.\r | |
| 3 | \r | |
| 4 | Copyright (c) 1999- 2015, Intel Corporation. All rights reserved.<BR>\r | |
| 5 | This program and the accompanying materials\r | |
| 6 | are licensed and made available under the terms and conditions of the BSD License\r | |
| 7 | which accompanies this distribution. The full text of the license may be found at\r | |
| 8 | http://opensource.org/licenses/bsd-license.php\r | |
| 9 | \r | |
| 10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
| 11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
| 12 | \r | |
| 13 | **/\r | |
| 14 | \r | |
| 15 | #ifndef I2C_PEI_REGS_H\r | |
| 16 | #define I2C_PEI_REGS_H\r | |
| 17 | \r | |
| 18 | #include "PiPei.h"\r | |
| 19 | \r | |
| 20 | #define R_PCH_LPC_PMC_BASE 0x44\r | |
| 21 | #define B_PCH_LPC_PMC_BASE_BAR 0xFFFFFE00\r | |
| 22 | #define R_PCH_PMC_FUNC_DIS 0x34 // Function Disable Register\r | |
| 23 | #define PCIEX_BASE_ADDRESS 0xE0000000\r | |
| 24 | #define PciD31F0RegBase PCIEX_BASE_ADDRESS + (UINT32) (31 << 15)\r | |
| 25 | #define B_PCH_PMC_FUNC_DIS_LPSS_FUNC7 BIT7 // LPSS SPI Disable\r | |
| 26 | #define B_PCH_PMC_FUNC_DIS_LPSS_FUNC6 BIT6 // LPSS HSUART #2 Disable\r | |
| 27 | #define B_PCH_PMC_FUNC_DIS_LPSS_FUNC5 BIT5 // LPSS HSUART #1 Disable\r | |
| 28 | #define B_PCH_PMC_FUNC_DIS_LPSS_FUNC4 BIT4 // LPSS I2S Disable\r | |
| 29 | #define B_PCH_PMC_FUNC_DIS_LPSS_FUNC3 BIT3 // LPSS PCM Disable\r | |
| 30 | #define B_PCH_PMC_FUNC_DIS_LPSS_FUNC2 BIT2 // LPSS I2C #2 Disable\r | |
| 31 | #define B_PCH_PMC_FUNC_DIS_LPSS_FUNC1 BIT1 // LPSS I2C #1 Disable\r | |
| 32 | #define B_PCH_PMC_FUNC_DIS_LPSS_FUNC0 BIT0 // LPSS DMA Disable\r | |
| 33 | \r | |
| 34 | \r | |
| 35 | #define DEFAULT_PCI_BUS_NUMBER_PCH 0\r | |
| 36 | \r | |
| 37 | #define R_PCH_LPSS_I2C_STSCMD 0x04 // Status & Command\r | |
| 38 | #define B_PCH_LPSS_I2C_STSCMD_RMA BIT29 // RMA\r | |
| 39 | #define B_PCH_LPSS_I2C_STSCMD_RCA BIT28 // RCA\r | |
| 40 | #define B_PCH_LPSS_I2C_STSCMD_CAPLIST BIT20 // Capability List\r | |
| 41 | #define B_PCH_LPSS_I2C_STSCMD_INTRSTS BIT19 // Interrupt Status\r | |
| 42 | #define B_PCH_LPSS_I2C_STSCMD_INTRDIS BIT10 // Interrupt Disable\r | |
| 43 | #define B_PCH_LPSS_I2C_STSCMD_SERREN BIT8 // SERR# Enable\r | |
| 44 | #define B_PCH_LPSS_I2C_STSCMD_BME BIT2 // Bus Master Enable\r | |
| 45 | #define B_PCH_LPSS_I2C_STSCMD_MSE BIT1 // Memory Space Enable\r | |
| 46 | \r | |
| 47 | #define R_PCH_LPSS_I2C_BAR 0x10 // BAR\r | |
| 48 | #define B_PCH_LPSS_I2C_BAR_BA 0xFFFFF000 // Base Address\r | |
| 49 | #define B_PCH_LPSS_I2C_BAR_SI 0x00000FF0 // Size Indicator\r | |
| 50 | #define B_PCH_LPSS_I2C_BAR_PF BIT3 // Prefetchable\r | |
| 51 | #define B_PCH_LPSS_I2C_BAR_TYPE (BIT2 | BIT1) // Type\r | |
| 52 | #define B_PCH_LPSS_I2C_BAR_MS BIT0 // Message Space\r | |
| 53 | \r | |
| 54 | #define R_PCH_LPSS_I2C_BAR1 0x14 // BAR 1\r | |
| 55 | #define B_PCH_LPSS_I2C_BAR1_BA 0xFFFFF000 // Base Address\r | |
| 56 | #define B_PCH_LPSS_I2C_BAR1_SI 0x00000FF0 // Size Indicator\r | |
| 57 | #define B_PCH_LPSS_I2C_BAR1_PF BIT3 // Prefetchable\r | |
| 58 | #define B_PCH_LPSS_I2C_BAR1_TYPE (BIT2 | BIT1) // Type\r | |
| 59 | #define B_PCH_LPSS_I2C_BAR1_MS BIT0 // Message Space\r | |
| 60 | \r | |
| 61 | #define NUM_RETRIES 0xFFFF\r | |
| 62 | \r | |
| 63 | //\r | |
| 64 | // LPIO I2C Module Memory Space Registers\r | |
| 65 | //\r | |
| 66 | #define R_PCH_LPIO_I2C_MEM_RESETS 0x804 // Software Reset\r | |
| 67 | #define B_PCH_LPIO_I2C_MEM_RESETS_FUNC BIT1 // Function Clock Domain Reset\r | |
| 68 | #define B_PCH_LPIO_I2C_MEM_RESETS_APB BIT0 // APB Domain Reset\r | |
| 69 | \r | |
| 70 | #define R_PCH_LPSS_I2C_MEM_PCP 0x800 // Private Clock Parameters\r | |
| 71 | \r | |
| 72 | #define bit(a) 1 << (a)\r | |
| 73 | \r | |
| 74 | //\r | |
| 75 | // MMIO Register Definitions\r | |
| 76 | //\r | |
| 77 | \r | |
| 78 | #define I2C0_REG_SPACE_ADDR_BASE 0xFF138000 //01K\r | |
| 79 | \r | |
| 80 | #define R_IC_CON ( 0x00) // I2C Control\r | |
| 81 | #define B_IC_RESTART_EN BIT5\r | |
| 82 | #define B_IC_SLAVE_DISABLE BIT6\r | |
| 83 | #define V_SPEED_STANDARD 0x02\r | |
| 84 | #define V_SPEED_FAST 0x04\r | |
| 85 | #define V_SPEED_HIGH 0x06\r | |
| 86 | #define B_MASTER_MODE BIT0\r | |
| 87 | \r | |
| 88 | #define R_IC_TAR ( 0x04) // I2C Target Address\r | |
| 89 | #define IC_TAR_10BITADDR_MASTER BIT12\r | |
| 90 | \r | |
| 91 | #define R_IC_SAR ( 0x08) // I2C Slave Address\r | |
| 92 | #define R_IC_HS_MADDR ( 0x0C) // I2C HS MasterMode Code Address\r | |
| 93 | #define R_IC_DATA_CMD ( 0x10) // I2C Rx/Tx Data Buffer and Command\r | |
| 94 | \r | |
| 95 | #define B_READ_CMD BIT8 // 1 = read, 0 = write\r | |
| 96 | #define B_CMD_STOP BIT9 // 1 = STOP\r | |
| 97 | #define B_CMD_RESTART BIT10 // 1 = IC_RESTART_EN\r | |
| 98 | \r | |
| 99 | #define V_WRITE_CMD_MASK ( 0xFF)\r | |
| 100 | \r | |
| 101 | #define R_IC_SS_SCL_HCNT ( 0x14) // Standard Speed I2C Clock SCL High Count\r | |
| 102 | #define R_IC_SS_SCL_LCNT ( 0x18) // Standard Speed I2C Clock SCL Low Count\r | |
| 103 | #define R_IC_FS_SCL_HCNT ( 0x1C) // Full Speed I2C Clock SCL High Count\r | |
| 104 | #define R_IC_FS_SCL_LCNT ( 0x20) // Full Speed I2C Clock SCL Low Count\r | |
| 105 | #define R_IC_HS_SCL_HCNT ( 0x24) // High Speed I2C Clock SCL High Count\r | |
| 106 | #define R_IC_HS_SCL_LCNT ( 0x28) // High Speed I2C Clock SCL Low Count\r | |
| 107 | #define R_IC_INTR_STAT ( 0x2C) // I2C Inetrrupt Status\r | |
| 108 | #define R_IC_INTR_MASK ( 0x30) // I2C Interrupt Mask\r | |
| 109 | #define I2C_INTR_GEN_CALL BIT11 // General call received\r | |
| 110 | #define I2C_INTR_START_DET BIT10\r | |
| 111 | #define I2C_INTR_STOP_DET BIT9\r | |
| 112 | #define I2C_INTR_ACTIVITY BIT8\r | |
| 113 | #define I2C_INTR_TX_ABRT BIT6 // Set on NACK\r | |
| 114 | #define I2C_INTR_TX_EMPTY BIT4\r | |
| 115 | #define I2C_INTR_TX_OVER BIT3\r | |
| 116 | #define I2C_INTR_RX_FULL BIT2 // Data bytes in RX FIFO over threshold\r | |
| 117 | #define I2C_INTR_RX_OVER BIT1\r | |
| 118 | #define I2C_INTR_RX_UNDER BIT0\r | |
| 119 | #define R_IC_RawIntrStat ( 0x34) // I2C Raw Interrupt Status\r | |
| 120 | #define R_IC_RX_TL ( 0x38) // I2C Receive FIFO Threshold\r | |
| 121 | #define R_IC_TX_TL ( 0x3C) // I2C Transmit FIFO Threshold\r | |
| 122 | #define R_IC_CLR_INTR ( 0x40) // Clear Combined and Individual Interrupts\r | |
| 123 | #define R_IC_CLR_RX_UNDER ( 0x44) // Clear RX_UNDER Interrupt\r | |
| 124 | #define R_IC_CLR_RX_OVER ( 0x48) // Clear RX_OVERinterrupt\r | |
| 125 | #define R_IC_CLR_TX_OVER ( 0x4C) // Clear TX_OVER interrupt\r | |
| 126 | #define R_IC_CLR_RD_REQ ( 0x50) // Clear RD_REQ interrupt\r | |
| 127 | #define R_IC_CLR_TX_ABRT ( 0x54) // Clear TX_ABRT interrupt\r | |
| 128 | #define R_IC_CLR_RX_DONE ( 0x58) // Clear RX_DONE interrupt\r | |
| 129 | #define R_IC_CLR_ACTIVITY ( 0x5C) // Clear ACTIVITY interrupt\r | |
| 130 | #define R_IC_CLR_STOP_DET ( 0x60) // Clear STOP_DET interrupt\r | |
| 131 | #define R_IC_CLR_START_DET ( 0x64) // Clear START_DET interrupt\r | |
| 132 | #define R_IC_CLR_GEN_CALL ( 0x68) // Clear GEN_CALL interrupt\r | |
| 133 | #define R_IC_ENABLE ( 0x6C) // I2C Enable\r | |
| 134 | #define R_IC_STATUS ( 0x70) // I2C Status\r | |
| 135 | \r | |
| 136 | #define R_IC_SDA_HOLD ( 0x7C) // I2C IC_DEFAULT_SDA_HOLD//16bits\r | |
| 137 | \r | |
| 138 | #define STAT_MST_ACTIVITY BIT5 // Master FSM Activity Status.\r | |
| 139 | #define STAT_RFF BIT4 // RX FIFO is completely full\r | |
| 140 | #define STAT_RFNE BIT3 // RX FIFO is not empty\r | |
| 141 | #define STAT_TFE BIT2 // TX FIFO is completely empty\r | |
| 142 | #define STAT_TFNF BIT1 // TX FIFO is not full\r | |
| 143 | \r | |
| 144 | #define R_IC_TXFLR ( 0x74) // Transmit FIFO Level Register\r | |
| 145 | #define R_IC_RXFLR ( 0x78) // Receive FIFO Level Register\r | |
| 146 | #define R_IC_TX_ABRT_SOURCE ( 0x80) // I2C Transmit Abort Status Register\r | |
| 147 | #define R_IC_SLV_DATA_NACK_ONLY ( 0x84) // Generate SLV_DATA_NACK Register\r | |
| 148 | #define R_IC_DMA_CR ( 0x88) // DMA Control Register\r | |
| 149 | #define R_IC_DMA_TDLR ( 0x8C) // DMA Transmit Data Level\r | |
| 150 | #define R_IC_DMA_RDLR ( 0x90) // DMA Receive Data Level\r | |
| 151 | #define R_IC_SDA_SETUP ( 0x94) // I2C SDA Setup Register\r | |
| 152 | #define R_IC_ACK_GENERAL_CALL ( 0x98) // I2C ACK General Call Register\r | |
| 153 | #define R_IC_ENABLE_STATUS ( 0x9C) // I2C Enable Status Register\r | |
| 154 | #define R_IC_COMP_PARAM ( 0xF4) // Component Parameter Register\r | |
| 155 | #define R_IC_COMP_VERSION ( 0xF8) // Component Version ID\r | |
| 156 | #define R_IC_COMP_TYPE ( 0xFC) // Component Type\r | |
| 157 | \r | |
| 158 | #define I2C_SS_SCL_HCNT_VALUE_100M 0x1DD\r | |
| 159 | #define I2C_SS_SCL_LCNT_VALUE_100M 0x1E4\r | |
| 160 | #define I2C_FS_SCL_HCNT_VALUE_100M 0x54\r | |
| 161 | #define I2C_FS_SCL_LCNT_VALUE_100M 0x9a\r | |
| 162 | #define I2C_HS_SCL_HCNT_VALUE_100M 0x7\r | |
| 163 | #define I2C_HS_SCL_LCNT_VALUE_100M 0xE\r | |
| 164 | \r | |
| 165 | //\r | |
| 166 | // FIFO write workaround value.\r | |
| 167 | //\r | |
| 168 | #define FIFO_WRITE_DELAY 2\r | |
| 169 | #define IC_TAR_10BITADDR_MASTER BIT12\r | |
| 170 | #define FIFO_SIZE 32\r | |
| 171 | #define R_IC_INTR_STAT ( 0x2C) // I2c Inetrrupt Status\r | |
| 172 | #define R_IC_INTR_MASK ( 0x30) // I2c Interrupt Mask\r | |
| 173 | #define I2C_INTR_GEN_CALL BIT11 // General call received\r | |
| 174 | #define I2C_INTR_START_DET BIT10\r | |
| 175 | #define I2C_INTR_STOP_DET BIT9\r | |
| 176 | #define I2C_INTR_ACTIVITY BIT8\r | |
| 177 | #define I2C_INTR_TX_ABRT BIT6 // Set on NACK\r | |
| 178 | #define I2C_INTR_TX_EMPTY BIT4\r | |
| 179 | #define I2C_INTR_TX_OVER BIT3\r | |
| 180 | #define I2C_INTR_RX_FULL BIT2 // Data bytes in RX FIFO over threshold\r | |
| 181 | #define I2C_INTR_RX_OVER BIT1\r | |
| 182 | #define I2C_INTR_RX_UNDER BIT0\r | |
| 183 | \r | |
| 184 | /**\r | |
| 185 | Programe all I2C controllers on LPSS. \r | |
| 186 | \r | |
| 187 | I2C0 is function 1 of LPSS. I2C1 is function 2 of LPSS, etc..\r | |
| 188 | \r | |
| 189 | @param VOID\r | |
| 190 | \r | |
| 191 | @return EFI_SUCCESS\r | |
| 192 | **/\r | |
| 193 | EFI_STATUS\r | |
| 194 | ProgramPciLpssI2C (\r | |
| 195 | VOID\r | |
| 196 | );\r | |
| 197 | \r | |
| 198 | /**\r | |
| 199 | Reads a Byte from I2C Device.\r | |
| 200 | \r | |
| 201 | @param I2cControllerIndex I2C Bus no to which the I2C device has been connected\r | |
| 202 | @param SlaveAddress Device Address from which the byte value has to be read\r | |
| 203 | @param Offset Offset from which the data has to be read\r | |
| 204 | @param *Byte Address to which the value read has to be stored\r | |
| 205 | @param Start Whether a RESTART is issued before the byte is sent or received\r | |
| 206 | @param End Whether STOP is generated after a data byte is sent or received \r | |
| 207 | \r | |
| 208 | @return EFI_SUCCESS If the byte value has been successfully read\r | |
| 209 | @return EFI_DEVICE_ERROR Operation Failed, Device Error\r | |
| 210 | **/\r | |
| 211 | EFI_STATUS\r | |
| 212 | ByteReadI2CBasic(\r | |
| 213 | IN UINT8 I2cControllerIndex,\r | |
| 214 | IN UINT8 SlaveAddress,\r | |
| 215 | IN UINTN ReadBytes,\r | |
| 216 | OUT UINT8 *ReadBuffer,\r | |
| 217 | IN UINT8 Start,\r | |
| 218 | IN UINT8 End\r | |
| 219 | );\r | |
| 220 | \r | |
| 221 | /**\r | |
| 222 | Writes a Byte to I2C Device.\r | |
| 223 | \r | |
| 224 | @param I2cControllerIndex I2C Bus no to which the I2C device has been connected\r | |
| 225 | @param SlaveAddress Device Address from which the byte value has to be written\r | |
| 226 | @param Offset Offset from which the data has to be read\r | |
| 227 | @param *Byte Address to which the value written is stored\r | |
| 228 | @param Start Whether a RESTART is issued before the byte is sent or received\r | |
| 229 | @param End Whether STOP is generated after a data byte is sent or received \r | |
| 230 | \r | |
| 231 | @return EFI_SUCCESS IF the byte value has been successfully written\r | |
| 232 | @return EFI_DEVICE_ERROR Operation Failed, Device Error\r | |
| 233 | **/\r | |
| 234 | EFI_STATUS\r | |
| 235 | ByteWriteI2CBasic(\r | |
| 236 | IN UINT8 I2cControllerIndex,\r | |
| 237 | IN UINT8 SlaveAddress,\r | |
| 238 | IN UINTN WriteBytes,\r | |
| 239 | IN UINT8 *WriteBuffer,\r | |
| 240 | IN UINT8 Start,\r | |
| 241 | IN UINT8 End\r | |
| 242 | );\r | |
| 243 | \r | |
| 244 | /**\r | |
| 245 | Reads a Byte from I2C Device.\r | |
| 246 | \r | |
| 247 | @param I2cControllerIndex I2C Bus no to which the I2C device has been connected\r | |
| 248 | @param SlaveAddress Device Address from which the byte value has to be read\r | |
| 249 | @param Offset Offset from which the data has to be read\r | |
| 250 | @param ReadBytes Number of bytes to be read\r | |
| 251 | @param *ReadBuffer Address to which the value read has to be stored\r | |
| 252 | \r | |
| 253 | @return EFI_SUCCESS IF the byte value has been successfully read\r | |
| 254 | @return EFI_DEVICE_ERROR Operation Failed, Device Error\r | |
| 255 | **/\r | |
| 256 | EFI_STATUS\r | |
| 257 | ByteReadI2C(\r | |
| 258 | IN UINT8 I2cControllerIndex,\r | |
| 259 | IN UINT8 SlaveAddress,\r | |
| 260 | IN UINT8 Offset,\r | |
| 261 | IN UINTN ReadBytes,\r | |
| 262 | OUT UINT8 *ReadBuffer\r | |
| 263 | );\r | |
| 264 | \r | |
| 265 | /**\r | |
| 266 | Writes a Byte to I2C Device.\r | |
| 267 | \r | |
| 268 | @param I2cControllerIndex I2C Bus no to which the I2C device has been connected\r | |
| 269 | @param SlaveAddress Device Address from which the byte value has to be written\r | |
| 270 | @param Offset Offset from which the data has to be written\r | |
| 271 | @param WriteBytes Number of bytes to be written\r | |
| 272 | @param *Byte Address to which the value written is stored\r | |
| 273 | \r | |
| 274 | @return EFI_SUCCESS IF the byte value has been successfully read\r | |
| 275 | @return EFI_DEVICE_ERROR Operation Failed, Device Error\r | |
| 276 | **/\r | |
| 277 | EFI_STATUS\r | |
| 278 | ByteWriteI2C(\r | |
| 279 | IN UINT8 I2cControllerIndex,\r | |
| 280 | IN UINT8 SlaveAddress,\r | |
| 281 | IN UINT8 Offset,\r | |
| 282 | IN UINTN WriteBytes,\r | |
| 283 | IN UINT8 *WriteBuffer\r | |
| 284 | );\r | |
| 285 | \r | |
| 286 | #endif\r |