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1 | /** @file\r |
2 | \r | |
3 | Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>\r | |
4 | \r\r | |
5 | This program and the accompanying materials are licensed and made available under\r\r | |
6 | the terms and conditions of the BSD License that accompanies this distribution. \r\r | |
7 | The full text of the license may be found at \r\r | |
8 | http://opensource.org/licenses/bsd-license.php. \r\r | |
9 | \r\r | |
10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r\r | |
11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r\r | |
12 | \r\r | |
13 | \r | |
14 | Module Name:\r | |
15 | \r | |
16 | \r | |
17 | IchRegTable.c\r | |
18 | \r | |
19 | Abstract:\r | |
20 | \r | |
21 | Register initialization table for Ich.\r | |
22 | \r | |
23 | \r | |
24 | \r | |
25 | --*/\r | |
26 | \r | |
27 | #include <Library/EfiRegTableLib.h>\r | |
28 | #include "PlatformDxe.h"\r | |
29 | extern EFI_PLATFORM_INFO_HOB mPlatformInfo;\r | |
30 | \r | |
31 | #define R_EFI_PCI_SVID 0x2C\r | |
32 | \r | |
33 | EFI_REG_TABLE mSubsystemIdRegs [] = {\r | |
34 | \r | |
35 | //\r | |
36 | // Program SVID and SID for PCI devices.\r | |
37 | // Combine two 16 bit PCI_WRITE into one 32 bit PCI_WRITE in order to boost performance\r | |
38 | //\r | |
39 | PCI_WRITE (\r | |
40 | MC_BUS, MC_DEV, MC_FUN, R_EFI_PCI_SVID, EfiPciWidthUint32,\r | |
41 | V_PCH_DEFAULT_SVID_SID, OPCODE_FLAG_S3SAVE\r | |
42 | ),\r | |
43 | \r | |
44 | PCI_WRITE (\r | |
45 | IGD_BUS, IGD_DEV, IGD_FUN_0, R_EFI_PCI_SVID, EfiPciWidthUint32,\r | |
46 | V_PCH_DEFAULT_SVID_SID, OPCODE_FLAG_S3SAVE\r | |
47 | ),\r | |
48 | \r | |
49 | PCI_WRITE(\r | |
50 | DEFAULT_PCI_BUS_NUMBER_PCH, 0, 0, R_EFI_PCI_SVID, EfiPciWidthUint32,\r | |
51 | V_PCH_DEFAULT_SVID_SID, OPCODE_FLAG_S3SAVE\r | |
52 | ),\r | |
53 | PCI_WRITE (\r | |
54 | DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, PCI_FUNCTION_NUMBER_PCH_LPC, R_PCH_LPC_SS, EfiPciWidthUint32,\r | |
55 | V_PCH_DEFAULT_SVID_SID, OPCODE_FLAG_S3SAVE\r | |
56 | ),\r | |
57 | PCI_WRITE (\r | |
58 | DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_SATA, PCI_FUNCTION_NUMBER_PCH_SATA, R_PCH_SATA_SS, EfiPciWidthUint32,\r | |
59 | V_PCH_DEFAULT_SVID_SID, OPCODE_FLAG_S3SAVE\r | |
60 | ),\r | |
61 | PCI_WRITE (\r | |
62 | DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_SMBUS, PCI_FUNCTION_NUMBER_PCH_SMBUS, R_PCH_SMBUS_SVID, EfiPciWidthUint32,\r | |
63 | V_PCH_DEFAULT_SVID_SID, OPCODE_FLAG_S3SAVE\r | |
64 | ),\r | |
65 | PCI_WRITE (\r | |
66 | DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_USB, PCI_FUNCTION_NUMBER_PCH_EHCI, R_PCH_EHCI_SVID, EfiPciWidthUint32,\r | |
67 | V_PCH_DEFAULT_SVID_SID, OPCODE_FLAG_S3SAVE\r | |
68 | ),\r | |
69 | PCI_WRITE (\r | |
70 | DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORTS, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_1, R_PCH_PCIE_SVID, EfiPciWidthUint32,\r | |
71 | V_PCH_DEFAULT_SVID_SID, OPCODE_FLAG_S3SAVE\r | |
72 | ),\r | |
73 | PCI_WRITE (\r | |
74 | DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORTS, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_2, R_PCH_PCIE_SVID, EfiPciWidthUint32,\r | |
75 | V_PCH_DEFAULT_SVID_SID, OPCODE_FLAG_S3SAVE\r | |
76 | ),\r | |
77 | PCI_WRITE (\r | |
78 | DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORTS, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_3, R_PCH_PCIE_SVID, EfiPciWidthUint32,\r | |
79 | V_PCH_DEFAULT_SVID_SID, OPCODE_FLAG_S3SAVE\r | |
80 | ),\r | |
81 | PCI_WRITE (\r | |
82 | DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORTS, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_4, R_PCH_PCIE_SVID, EfiPciWidthUint32,\r | |
83 | V_PCH_DEFAULT_SVID_SID, OPCODE_FLAG_S3SAVE\r | |
84 | ),\r | |
85 | TERMINATE_TABLE\r | |
86 | };\r | |
87 | \r | |
88 | /**\r | |
89 | Updates the mSubsystemIdRegs table, and processes it. This should program\r | |
90 | the Subsystem Vendor and Device IDs.\r | |
91 | \r | |
92 | @retval Returns VOID\r | |
93 | \r | |
94 | **/\r | |
95 | VOID\r | |
96 | InitializeSubsystemIds (\r | |
97 | )\r | |
98 | {\r | |
99 | \r | |
100 | EFI_REG_TABLE *RegTablePtr;\r | |
101 | UINT32 SubsystemVidDid;\r | |
3cbfba02 DW |
102 | \r |
103 | SubsystemVidDid = mPlatformInfo.SsidSvid;\r | |
3cbfba02 DW |
104 | \r |
105 | RegTablePtr = mSubsystemIdRegs;\r | |
106 | \r | |
107 | //\r | |
108 | // While we are not at the end of the table\r | |
109 | //\r | |
110 | while (RegTablePtr->Generic.OpCode != OP_TERMINATE_TABLE) {\r | |
111 | //\r | |
112 | // If the data to write is the original SSID\r | |
113 | //\r | |
114 | if (RegTablePtr->PciWrite.Data ==\r | |
115 | ((V_PCH_DEFAULT_SID << 16) |\r | |
116 | V_PCH_INTEL_VENDOR_ID)\r | |
117 | ) {\r | |
118 | \r | |
119 | //\r | |
120 | // Then overwrite it to use the alternate SSID\r | |
121 | //\r | |
122 | RegTablePtr->PciWrite.Data = SubsystemVidDid;\r | |
123 | }\r | |
124 | \r | |
125 | //\r | |
126 | // Go to next table entry\r | |
127 | //\r | |
128 | RegTablePtr++;\r | |
129 | }\r | |
130 | \r | |
131 | RegTablePtr = mSubsystemIdRegs;\r | |
132 | \r | |
133 | \r | |
134 | //\r | |
135 | // Program the SSVID/SSDID\r | |
136 | //\r | |
137 | ProcessRegTablePci (mSubsystemIdRegs, mPciRootBridgeIo, NULL);\r | |
138 | \r | |
139 | }\r |