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b2441318 | 1 | // SPDX-License-Identifier: GPL-2.0 |
1353ebb4 | 2 | /* |
1353ebb4 JF |
3 | * Copyright (C) 1994 Linus Torvalds |
4 | * | |
5 | * Cyrix stuff, June 1998 by: | |
6 | * - Rafael R. Reilova (moved everything from head.S), | |
7 | * <rreilova@ececs.uc.edu> | |
8 | * - Channing Corn (tests & fixes), | |
9 | * - Andrew D. Balsa (code cleanup). | |
10 | */ | |
11 | #include <linux/init.h> | |
12 | #include <linux/utsname.h> | |
61dc0f55 | 13 | #include <linux/cpu.h> |
d280282b | 14 | #include <linux/module.h> |
574dcf89 TG |
15 | #include <linux/nospec.h> |
16 | #include <linux/prctl.h> | |
da285121 | 17 | |
d7a6a163 | 18 | #include <asm/spec-ctrl.h> |
da285121 | 19 | #include <asm/cmdline.h> |
91eb1b79 | 20 | #include <asm/bugs.h> |
1353ebb4 | 21 | #include <asm/processor.h> |
7ebad705 | 22 | #include <asm/processor-flags.h> |
952f07ec | 23 | #include <asm/fpu/internal.h> |
1353ebb4 | 24 | #include <asm/msr.h> |
b9cfedcd | 25 | #include <asm/vmx.h> |
1353ebb4 JF |
26 | #include <asm/paravirt.h> |
27 | #include <asm/alternative.h> | |
62a67e12 | 28 | #include <asm/pgtable.h> |
d1163651 | 29 | #include <asm/set_memory.h> |
c995efd5 | 30 | #include <asm/intel-family.h> |
05516ad8 | 31 | #include <asm/e820/api.h> |
1353ebb4 | 32 | |
da285121 | 33 | static void __init spectre_v2_select_mitigation(void); |
e63490c8 | 34 | static void __init ssb_select_mitigation(void); |
05516ad8 | 35 | static void __init l1tf_select_mitigation(void); |
da285121 | 36 | |
296b454a KRW |
37 | /* |
38 | * Our boot-time value of the SPEC_CTRL MSR. We read it once so that any | |
39 | * writes to SPEC_CTRL contain whatever reserved bits have been set. | |
40 | */ | |
5407b7f8 | 41 | u64 __ro_after_init x86_spec_ctrl_base; |
4ac9b1f9 | 42 | EXPORT_SYMBOL_GPL(x86_spec_ctrl_base); |
296b454a | 43 | |
d0c3bedd KRW |
44 | /* |
45 | * The vendor and possibly platform specific bits which can be modified in | |
46 | * x86_spec_ctrl_base. | |
47 | */ | |
e5f984ed | 48 | static u64 __ro_after_init x86_spec_ctrl_mask = SPEC_CTRL_IBRS; |
d0c3bedd | 49 | |
c37b94dd KRW |
50 | /* |
51 | * AMD specific MSR info for Speculative Store Bypass control. | |
8fe36c9d | 52 | * x86_amd_ls_cfg_ssbd_mask is initialized in identify_boot_cpu(). |
c37b94dd KRW |
53 | */ |
54 | u64 __ro_after_init x86_amd_ls_cfg_base; | |
8fe36c9d | 55 | u64 __ro_after_init x86_amd_ls_cfg_ssbd_mask; |
c37b94dd | 56 | |
1353ebb4 JF |
57 | void __init check_bugs(void) |
58 | { | |
59 | identify_boot_cpu(); | |
55a36b65 | 60 | |
483ec3c6 TG |
61 | /* |
62 | * identify_boot_cpu() initialized SMT support information, let the | |
63 | * core code know. | |
64 | */ | |
ade31b9e | 65 | cpu_smt_check_topology_early(); |
483ec3c6 | 66 | |
62a67e12 BP |
67 | if (!IS_ENABLED(CONFIG_SMP)) { |
68 | pr_info("CPU: "); | |
69 | print_cpu_info(&boot_cpu_data); | |
70 | } | |
71 | ||
296b454a KRW |
72 | /* |
73 | * Read the SPEC_CTRL MSR to account for reserved bits which may | |
c37b94dd KRW |
74 | * have unknown values. AMD64_LS_CFG MSR is cached in the early AMD |
75 | * init code as it is not enumerated and depends on the family. | |
296b454a | 76 | */ |
50f9b919 | 77 | if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) |
296b454a KRW |
78 | rdmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); |
79 | ||
e5f984ed TG |
80 | /* Allow STIBP in MSR_SPEC_CTRL if supported */ |
81 | if (boot_cpu_has(X86_FEATURE_STIBP)) | |
82 | x86_spec_ctrl_mask |= SPEC_CTRL_STIBP; | |
83 | ||
da285121 DW |
84 | /* Select the proper spectre mitigation before patching alternatives */ |
85 | spectre_v2_select_mitigation(); | |
86 | ||
e63490c8 KRW |
87 | /* |
88 | * Select proper mitigation for any exposure to the Speculative Store | |
89 | * Bypass vulnerability. | |
90 | */ | |
91 | ssb_select_mitigation(); | |
92 | ||
05516ad8 AK |
93 | l1tf_select_mitigation(); |
94 | ||
62a67e12 | 95 | #ifdef CONFIG_X86_32 |
55a36b65 BP |
96 | /* |
97 | * Check whether we are able to run this kernel safely on SMP. | |
98 | * | |
99 | * - i386 is no longer supported. | |
100 | * - In order to run on anything without a TSC, we need to be | |
101 | * compiled for a i486. | |
102 | */ | |
103 | if (boot_cpu_data.x86 < 4) | |
104 | panic("Kernel requires i486+ for 'invlpg' and other features"); | |
105 | ||
bfe4bb15 MV |
106 | init_utsname()->machine[1] = |
107 | '0' + (boot_cpu_data.x86 > 6 ? 6 : boot_cpu_data.x86); | |
1353ebb4 | 108 | alternative_instructions(); |
304bceda | 109 | |
4d164092 | 110 | fpu__init_check_bugs(); |
62a67e12 BP |
111 | #else /* CONFIG_X86_64 */ |
112 | alternative_instructions(); | |
113 | ||
114 | /* | |
115 | * Make sure the first 2MB area is not mapped by huge pages | |
116 | * There are typically fixed size MTRRs in there and overlapping | |
117 | * MTRRs into large pages causes slow downs. | |
118 | * | |
119 | * Right now we don't do that with gbpages because there seems | |
120 | * very little benefit for that case. | |
121 | */ | |
122 | if (!direct_gbpages) | |
123 | set_memory_4k((unsigned long)__va(0), 1); | |
124 | #endif | |
1353ebb4 | 125 | } |
61dc0f55 | 126 | |
da285121 DW |
127 | /* The kernel command line selection */ |
128 | enum spectre_v2_mitigation_cmd { | |
129 | SPECTRE_V2_CMD_NONE, | |
130 | SPECTRE_V2_CMD_AUTO, | |
131 | SPECTRE_V2_CMD_FORCE, | |
132 | SPECTRE_V2_CMD_RETPOLINE, | |
133 | SPECTRE_V2_CMD_RETPOLINE_GENERIC, | |
134 | SPECTRE_V2_CMD_RETPOLINE_AMD, | |
135 | }; | |
136 | ||
137 | static const char *spectre_v2_strings[] = { | |
138 | [SPECTRE_V2_NONE] = "Vulnerable", | |
139 | [SPECTRE_V2_RETPOLINE_MINIMAL] = "Vulnerable: Minimal generic ASM retpoline", | |
140 | [SPECTRE_V2_RETPOLINE_MINIMAL_AMD] = "Vulnerable: Minimal AMD ASM retpoline", | |
141 | [SPECTRE_V2_RETPOLINE_GENERIC] = "Mitigation: Full generic retpoline", | |
142 | [SPECTRE_V2_RETPOLINE_AMD] = "Mitigation: Full AMD retpoline", | |
1044fde9 | 143 | [SPECTRE_V2_IBRS_ENHANCED] = "Mitigation: Enhanced IBRS", |
da285121 DW |
144 | }; |
145 | ||
146 | #undef pr_fmt | |
bbb5e08b | 147 | #define pr_fmt(fmt) "Spectre V2 : " fmt |
da285121 | 148 | |
b5e6d77d KC |
149 | static enum spectre_v2_mitigation spectre_v2_enabled __ro_after_init = |
150 | SPECTRE_V2_NONE; | |
d280282b | 151 | |
12376b62 BP |
152 | void |
153 | x86_virt_spec_ctrl(u64 guest_spec_ctrl, u64 guest_virt_spec_ctrl, bool setguest) | |
19fff03f | 154 | { |
e5f984ed | 155 | u64 msrval, guestval, hostval = x86_spec_ctrl_base; |
12376b62 | 156 | struct thread_info *ti = current_thread_info(); |
5407b7f8 | 157 | |
50f9b919 | 158 | /* Is MSR_SPEC_CTRL implemented ? */ |
12376b62 | 159 | if (static_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) { |
e5f984ed TG |
160 | /* |
161 | * Restrict guest_spec_ctrl to supported values. Clear the | |
162 | * modifiable bits in the host base value and or the | |
163 | * modifiable bits from the guest value. | |
164 | */ | |
165 | guestval = hostval & ~x86_spec_ctrl_mask; | |
166 | guestval |= guest_spec_ctrl & x86_spec_ctrl_mask; | |
167 | ||
12376b62 BP |
168 | /* SSBD controlled in MSR_SPEC_CTRL */ |
169 | if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD)) | |
e5f984ed | 170 | hostval |= ssbd_tif_to_spec_ctrl(ti->flags); |
12376b62 | 171 | |
e5f984ed TG |
172 | if (hostval != guestval) { |
173 | msrval = setguest ? guestval : hostval; | |
174 | wrmsrl(MSR_IA32_SPEC_CTRL, msrval); | |
12376b62 BP |
175 | } |
176 | } | |
1238ed31 TG |
177 | |
178 | /* | |
179 | * If SSBD is not handled in MSR_SPEC_CTRL on AMD, update | |
180 | * MSR_AMD64_L2_CFG or MSR_VIRT_SPEC_CTRL if supported. | |
181 | */ | |
182 | if (!static_cpu_has(X86_FEATURE_LS_CFG_SSBD) && | |
183 | !static_cpu_has(X86_FEATURE_VIRT_SSBD)) | |
184 | return; | |
185 | ||
186 | /* | |
187 | * If the host has SSBD mitigation enabled, force it in the host's | |
188 | * virtual MSR value. If its not permanently enabled, evaluate | |
189 | * current's TIF_SSBD thread flag. | |
190 | */ | |
191 | if (static_cpu_has(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE)) | |
192 | hostval = SPEC_CTRL_SSBD; | |
193 | else | |
194 | hostval = ssbd_tif_to_spec_ctrl(ti->flags); | |
195 | ||
196 | /* Sanitize the guest value */ | |
197 | guestval = guest_virt_spec_ctrl & SPEC_CTRL_SSBD; | |
198 | ||
199 | if (hostval != guestval) { | |
200 | unsigned long tif; | |
201 | ||
202 | tif = setguest ? ssbd_spec_ctrl_to_tif(guestval) : | |
203 | ssbd_spec_ctrl_to_tif(hostval); | |
204 | ||
205 | speculative_store_bypass_update(tif); | |
206 | } | |
19fff03f | 207 | } |
12376b62 | 208 | EXPORT_SYMBOL_GPL(x86_virt_spec_ctrl); |
19fff03f | 209 | |
8fe36c9d | 210 | static void x86_amd_ssb_disable(void) |
c37b94dd | 211 | { |
8fe36c9d | 212 | u64 msrval = x86_amd_ls_cfg_base | x86_amd_ls_cfg_ssbd_mask; |
c37b94dd | 213 | |
65e02bbd TL |
214 | if (boot_cpu_has(X86_FEATURE_VIRT_SSBD)) |
215 | wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, SPEC_CTRL_SSBD); | |
216 | else if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD)) | |
c37b94dd KRW |
217 | wrmsrl(MSR_AMD64_LS_CFG, msrval); |
218 | } | |
219 | ||
d280282b | 220 | #ifdef RETPOLINE |
bb3c2578 TG |
221 | static bool spectre_v2_bad_module; |
222 | ||
d280282b AK |
223 | bool retpoline_module_ok(bool has_retpoline) |
224 | { | |
225 | if (spectre_v2_enabled == SPECTRE_V2_NONE || has_retpoline) | |
226 | return true; | |
227 | ||
c8b8e109 | 228 | pr_err("System may be vulnerable to spectre v2\n"); |
d280282b AK |
229 | spectre_v2_bad_module = true; |
230 | return false; | |
231 | } | |
bb3c2578 TG |
232 | |
233 | static inline const char *spectre_v2_module_string(void) | |
234 | { | |
235 | return spectre_v2_bad_module ? " - vulnerable module loaded" : ""; | |
236 | } | |
237 | #else | |
238 | static inline const char *spectre_v2_module_string(void) { return ""; } | |
d280282b | 239 | #endif |
da285121 DW |
240 | |
241 | static void __init spec2_print_if_insecure(const char *reason) | |
242 | { | |
243 | if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2)) | |
17c33e7c | 244 | pr_info("%s selected on command line.\n", reason); |
da285121 DW |
245 | } |
246 | ||
247 | static void __init spec2_print_if_secure(const char *reason) | |
248 | { | |
249 | if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2)) | |
17c33e7c | 250 | pr_info("%s selected on command line.\n", reason); |
da285121 DW |
251 | } |
252 | ||
253 | static inline bool retp_compiler(void) | |
254 | { | |
255 | return __is_defined(RETPOLINE); | |
256 | } | |
257 | ||
258 | static inline bool match_option(const char *arg, int arglen, const char *opt) | |
259 | { | |
260 | int len = strlen(opt); | |
261 | ||
262 | return len == arglen && !strncmp(arg, opt, len); | |
263 | } | |
264 | ||
17c33e7c KA |
265 | static const struct { |
266 | const char *option; | |
267 | enum spectre_v2_mitigation_cmd cmd; | |
268 | bool secure; | |
269 | } mitigation_options[] = { | |
270 | { "off", SPECTRE_V2_CMD_NONE, false }, | |
271 | { "on", SPECTRE_V2_CMD_FORCE, true }, | |
272 | { "retpoline", SPECTRE_V2_CMD_RETPOLINE, false }, | |
273 | { "retpoline,amd", SPECTRE_V2_CMD_RETPOLINE_AMD, false }, | |
274 | { "retpoline,generic", SPECTRE_V2_CMD_RETPOLINE_GENERIC, false }, | |
275 | { "auto", SPECTRE_V2_CMD_AUTO, false }, | |
276 | }; | |
277 | ||
da285121 DW |
278 | static enum spectre_v2_mitigation_cmd __init spectre_v2_parse_cmdline(void) |
279 | { | |
280 | char arg[20]; | |
17c33e7c KA |
281 | int ret, i; |
282 | enum spectre_v2_mitigation_cmd cmd = SPECTRE_V2_CMD_AUTO; | |
283 | ||
284 | if (cmdline_find_option_bool(boot_command_line, "nospectre_v2")) | |
285 | return SPECTRE_V2_CMD_NONE; | |
286 | else { | |
713f1b95 | 287 | ret = cmdline_find_option(boot_command_line, "spectre_v2", arg, sizeof(arg)); |
17c33e7c KA |
288 | if (ret < 0) |
289 | return SPECTRE_V2_CMD_AUTO; | |
290 | ||
291 | for (i = 0; i < ARRAY_SIZE(mitigation_options); i++) { | |
292 | if (!match_option(arg, ret, mitigation_options[i].option)) | |
293 | continue; | |
294 | cmd = mitigation_options[i].cmd; | |
295 | break; | |
296 | } | |
297 | ||
298 | if (i >= ARRAY_SIZE(mitigation_options)) { | |
ecad7915 | 299 | pr_err("unknown option (%s). Switching to AUTO select\n", arg); |
da285121 DW |
300 | return SPECTRE_V2_CMD_AUTO; |
301 | } | |
302 | } | |
303 | ||
17c33e7c KA |
304 | if ((cmd == SPECTRE_V2_CMD_RETPOLINE || |
305 | cmd == SPECTRE_V2_CMD_RETPOLINE_AMD || | |
306 | cmd == SPECTRE_V2_CMD_RETPOLINE_GENERIC) && | |
307 | !IS_ENABLED(CONFIG_RETPOLINE)) { | |
713f1b95 | 308 | pr_err("%s selected but not compiled in. Switching to AUTO select\n", mitigation_options[i].option); |
da285121 | 309 | return SPECTRE_V2_CMD_AUTO; |
17c33e7c KA |
310 | } |
311 | ||
312 | if (cmd == SPECTRE_V2_CMD_RETPOLINE_AMD && | |
313 | boot_cpu_data.x86_vendor != X86_VENDOR_AMD) { | |
314 | pr_err("retpoline,amd selected but CPU is not AMD. Switching to AUTO select\n"); | |
315 | return SPECTRE_V2_CMD_AUTO; | |
316 | } | |
317 | ||
318 | if (mitigation_options[i].secure) | |
319 | spec2_print_if_secure(mitigation_options[i].option); | |
320 | else | |
321 | spec2_print_if_insecure(mitigation_options[i].option); | |
322 | ||
323 | return cmd; | |
da285121 DW |
324 | } |
325 | ||
326 | static void __init spectre_v2_select_mitigation(void) | |
327 | { | |
328 | enum spectre_v2_mitigation_cmd cmd = spectre_v2_parse_cmdline(); | |
329 | enum spectre_v2_mitigation mode = SPECTRE_V2_NONE; | |
330 | ||
331 | /* | |
332 | * If the CPU is not affected and the command line mode is NONE or AUTO | |
333 | * then nothing to do. | |
334 | */ | |
335 | if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2) && | |
336 | (cmd == SPECTRE_V2_CMD_NONE || cmd == SPECTRE_V2_CMD_AUTO)) | |
337 | return; | |
338 | ||
339 | switch (cmd) { | |
340 | case SPECTRE_V2_CMD_NONE: | |
341 | return; | |
342 | ||
343 | case SPECTRE_V2_CMD_FORCE: | |
da285121 | 344 | case SPECTRE_V2_CMD_AUTO: |
1044fde9 SP |
345 | if (boot_cpu_has(X86_FEATURE_IBRS_ENHANCED)) { |
346 | mode = SPECTRE_V2_IBRS_ENHANCED; | |
347 | /* Force it so VMEXIT will restore correctly */ | |
348 | x86_spec_ctrl_base |= SPEC_CTRL_IBRS; | |
349 | wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); | |
350 | goto specv2_set_mode; | |
351 | } | |
d0f293e0 DL |
352 | if (IS_ENABLED(CONFIG_RETPOLINE)) |
353 | goto retpoline_auto; | |
354 | break; | |
da285121 DW |
355 | case SPECTRE_V2_CMD_RETPOLINE_AMD: |
356 | if (IS_ENABLED(CONFIG_RETPOLINE)) | |
357 | goto retpoline_amd; | |
358 | break; | |
359 | case SPECTRE_V2_CMD_RETPOLINE_GENERIC: | |
360 | if (IS_ENABLED(CONFIG_RETPOLINE)) | |
361 | goto retpoline_generic; | |
362 | break; | |
363 | case SPECTRE_V2_CMD_RETPOLINE: | |
364 | if (IS_ENABLED(CONFIG_RETPOLINE)) | |
365 | goto retpoline_auto; | |
366 | break; | |
367 | } | |
713f1b95 | 368 | pr_err("Spectre mitigation: kernel not compiled with retpoline; no mitigation available!"); |
da285121 DW |
369 | return; |
370 | ||
371 | retpoline_auto: | |
372 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) { | |
373 | retpoline_amd: | |
374 | if (!boot_cpu_has(X86_FEATURE_LFENCE_RDTSC)) { | |
713f1b95 | 375 | pr_err("Spectre mitigation: LFENCE not serializing, switching to generic retpoline\n"); |
da285121 DW |
376 | goto retpoline_generic; |
377 | } | |
378 | mode = retp_compiler() ? SPECTRE_V2_RETPOLINE_AMD : | |
379 | SPECTRE_V2_RETPOLINE_MINIMAL_AMD; | |
380 | setup_force_cpu_cap(X86_FEATURE_RETPOLINE_AMD); | |
381 | setup_force_cpu_cap(X86_FEATURE_RETPOLINE); | |
382 | } else { | |
383 | retpoline_generic: | |
384 | mode = retp_compiler() ? SPECTRE_V2_RETPOLINE_GENERIC : | |
385 | SPECTRE_V2_RETPOLINE_MINIMAL; | |
386 | setup_force_cpu_cap(X86_FEATURE_RETPOLINE); | |
387 | } | |
388 | ||
1044fde9 | 389 | specv2_set_mode: |
da285121 DW |
390 | spectre_v2_enabled = mode; |
391 | pr_info("%s\n", spectre_v2_strings[mode]); | |
c995efd5 DW |
392 | |
393 | /* | |
14623a43 JK |
394 | * If spectre v2 protection has been enabled, unconditionally fill |
395 | * RSB during a context switch; this protects against two independent | |
396 | * issues: | |
c995efd5 | 397 | * |
14623a43 JK |
398 | * - RSB underflow (and switch to BTB) on Skylake+ |
399 | * - SpectreRSB variant of spectre v2 on X86_BUG_SPECTRE_V2 CPUs | |
c995efd5 | 400 | */ |
14623a43 JK |
401 | setup_force_cpu_cap(X86_FEATURE_RSB_CTXSW); |
402 | pr_info("Spectre v2 / SpectreRSB mitigation: Filling RSB on context switch\n"); | |
bd12e896 DW |
403 | |
404 | /* Initialize Indirect Branch Prediction Barrier if supported */ | |
581abf91 DW |
405 | if (boot_cpu_has(X86_FEATURE_IBPB)) { |
406 | setup_force_cpu_cap(X86_FEATURE_USE_IBPB); | |
713f1b95 | 407 | pr_info("Spectre v2 mitigation: Enabling Indirect Branch Prediction Barrier\n"); |
bd12e896 | 408 | } |
390b99c3 DW |
409 | |
410 | /* | |
411 | * Retpoline means the kernel is safe because it has no indirect | |
1044fde9 SP |
412 | * branches. Enhanced IBRS protects firmware too, so, enable restricted |
413 | * speculation around firmware calls only when Enhanced IBRS isn't | |
414 | * supported. | |
415 | * | |
416 | * Use "mode" to check Enhanced IBRS instead of boot_cpu_has(), because | |
417 | * the user might select retpoline on the kernel command line and if | |
418 | * the CPU supports Enhanced IBRS, kernel might un-intentionally not | |
419 | * enable IBRS around firmware calls. | |
390b99c3 | 420 | */ |
1044fde9 | 421 | if (boot_cpu_has(X86_FEATURE_IBRS) && mode != SPECTRE_V2_IBRS_ENHANCED) { |
390b99c3 DW |
422 | setup_force_cpu_cap(X86_FEATURE_USE_IBRS_FW); |
423 | pr_info("Enabling Restricted Speculation for firmware calls\n"); | |
424 | } | |
da285121 DW |
425 | } |
426 | ||
e63490c8 KRW |
427 | #undef pr_fmt |
428 | #define pr_fmt(fmt) "Speculative Store Bypass: " fmt | |
429 | ||
b5e6d77d | 430 | static enum ssb_mitigation ssb_mode __ro_after_init = SPEC_STORE_BYPASS_NONE; |
e63490c8 KRW |
431 | |
432 | /* The kernel command line selection */ | |
433 | enum ssb_mitigation_cmd { | |
434 | SPEC_STORE_BYPASS_CMD_NONE, | |
435 | SPEC_STORE_BYPASS_CMD_AUTO, | |
436 | SPEC_STORE_BYPASS_CMD_ON, | |
574dcf89 | 437 | SPEC_STORE_BYPASS_CMD_PRCTL, |
c7416003 | 438 | SPEC_STORE_BYPASS_CMD_SECCOMP, |
e63490c8 KRW |
439 | }; |
440 | ||
441 | static const char *ssb_strings[] = { | |
442 | [SPEC_STORE_BYPASS_NONE] = "Vulnerable", | |
574dcf89 | 443 | [SPEC_STORE_BYPASS_DISABLE] = "Mitigation: Speculative Store Bypass disabled", |
c7416003 KC |
444 | [SPEC_STORE_BYPASS_PRCTL] = "Mitigation: Speculative Store Bypass disabled via prctl", |
445 | [SPEC_STORE_BYPASS_SECCOMP] = "Mitigation: Speculative Store Bypass disabled via prctl and seccomp", | |
e63490c8 KRW |
446 | }; |
447 | ||
448 | static const struct { | |
449 | const char *option; | |
450 | enum ssb_mitigation_cmd cmd; | |
451 | } ssb_mitigation_options[] = { | |
c7416003 KC |
452 | { "auto", SPEC_STORE_BYPASS_CMD_AUTO }, /* Platform decides */ |
453 | { "on", SPEC_STORE_BYPASS_CMD_ON }, /* Disable Speculative Store Bypass */ | |
454 | { "off", SPEC_STORE_BYPASS_CMD_NONE }, /* Don't touch Speculative Store Bypass */ | |
455 | { "prctl", SPEC_STORE_BYPASS_CMD_PRCTL }, /* Disable Speculative Store Bypass via prctl */ | |
456 | { "seccomp", SPEC_STORE_BYPASS_CMD_SECCOMP }, /* Disable Speculative Store Bypass via prctl and seccomp */ | |
e63490c8 KRW |
457 | }; |
458 | ||
459 | static enum ssb_mitigation_cmd __init ssb_parse_cmdline(void) | |
460 | { | |
461 | enum ssb_mitigation_cmd cmd = SPEC_STORE_BYPASS_CMD_AUTO; | |
462 | char arg[20]; | |
463 | int ret, i; | |
464 | ||
465 | if (cmdline_find_option_bool(boot_command_line, "nospec_store_bypass_disable")) { | |
466 | return SPEC_STORE_BYPASS_CMD_NONE; | |
467 | } else { | |
468 | ret = cmdline_find_option(boot_command_line, "spec_store_bypass_disable", | |
469 | arg, sizeof(arg)); | |
470 | if (ret < 0) | |
471 | return SPEC_STORE_BYPASS_CMD_AUTO; | |
472 | ||
473 | for (i = 0; i < ARRAY_SIZE(ssb_mitigation_options); i++) { | |
474 | if (!match_option(arg, ret, ssb_mitigation_options[i].option)) | |
475 | continue; | |
476 | ||
477 | cmd = ssb_mitigation_options[i].cmd; | |
478 | break; | |
479 | } | |
480 | ||
481 | if (i >= ARRAY_SIZE(ssb_mitigation_options)) { | |
482 | pr_err("unknown option (%s). Switching to AUTO select\n", arg); | |
483 | return SPEC_STORE_BYPASS_CMD_AUTO; | |
484 | } | |
485 | } | |
486 | ||
487 | return cmd; | |
488 | } | |
489 | ||
dbe3009d | 490 | static enum ssb_mitigation __init __ssb_select_mitigation(void) |
e63490c8 KRW |
491 | { |
492 | enum ssb_mitigation mode = SPEC_STORE_BYPASS_NONE; | |
493 | enum ssb_mitigation_cmd cmd; | |
494 | ||
8fe36c9d | 495 | if (!boot_cpu_has(X86_FEATURE_SSBD)) |
e63490c8 KRW |
496 | return mode; |
497 | ||
498 | cmd = ssb_parse_cmdline(); | |
499 | if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS) && | |
500 | (cmd == SPEC_STORE_BYPASS_CMD_NONE || | |
501 | cmd == SPEC_STORE_BYPASS_CMD_AUTO)) | |
502 | return mode; | |
503 | ||
504 | switch (cmd) { | |
505 | case SPEC_STORE_BYPASS_CMD_AUTO: | |
c7416003 KC |
506 | case SPEC_STORE_BYPASS_CMD_SECCOMP: |
507 | /* | |
508 | * Choose prctl+seccomp as the default mode if seccomp is | |
509 | * enabled. | |
510 | */ | |
511 | if (IS_ENABLED(CONFIG_SECCOMP)) | |
512 | mode = SPEC_STORE_BYPASS_SECCOMP; | |
513 | else | |
514 | mode = SPEC_STORE_BYPASS_PRCTL; | |
574dcf89 | 515 | break; |
e63490c8 KRW |
516 | case SPEC_STORE_BYPASS_CMD_ON: |
517 | mode = SPEC_STORE_BYPASS_DISABLE; | |
518 | break; | |
574dcf89 TG |
519 | case SPEC_STORE_BYPASS_CMD_PRCTL: |
520 | mode = SPEC_STORE_BYPASS_PRCTL; | |
521 | break; | |
e63490c8 KRW |
522 | case SPEC_STORE_BYPASS_CMD_NONE: |
523 | break; | |
524 | } | |
525 | ||
23b9eab9 KRW |
526 | /* |
527 | * We have three CPU feature flags that are in play here: | |
528 | * - X86_BUG_SPEC_STORE_BYPASS - CPU is susceptible. | |
8fe36c9d | 529 | * - X86_FEATURE_SSBD - CPU is able to turn off speculative store bypass |
23b9eab9 KRW |
530 | * - X86_FEATURE_SPEC_STORE_BYPASS_DISABLE - engage the mitigation |
531 | */ | |
574dcf89 | 532 | if (mode == SPEC_STORE_BYPASS_DISABLE) { |
e63490c8 | 533 | setup_force_cpu_cap(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE); |
23b9eab9 | 534 | /* |
3b881627 KRW |
535 | * Intel uses the SPEC CTRL MSR Bit(2) for this, while AMD may |
536 | * use a completely different MSR and bit dependent on family. | |
23b9eab9 | 537 | */ |
733c54c9 KRW |
538 | if (!static_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) |
539 | x86_amd_ssb_disable(); | |
540 | else { | |
8fe36c9d | 541 | x86_spec_ctrl_base |= SPEC_CTRL_SSBD; |
e5f984ed | 542 | x86_spec_ctrl_mask |= SPEC_CTRL_SSBD; |
208efa83 | 543 | wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); |
23b9eab9 KRW |
544 | } |
545 | } | |
546 | ||
e63490c8 KRW |
547 | return mode; |
548 | } | |
549 | ||
043d480e | 550 | static void ssb_select_mitigation(void) |
e63490c8 KRW |
551 | { |
552 | ssb_mode = __ssb_select_mitigation(); | |
553 | ||
554 | if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) | |
555 | pr_info("%s\n", ssb_strings[ssb_mode]); | |
556 | } | |
557 | ||
da285121 | 558 | #undef pr_fmt |
c7416003 | 559 | #define pr_fmt(fmt) "Speculation prctl: " fmt |
da285121 | 560 | |
199bfed2 | 561 | static int ssb_prctl_set(struct task_struct *task, unsigned long ctrl) |
574dcf89 | 562 | { |
733f4234 | 563 | bool update; |
574dcf89 | 564 | |
c7416003 KC |
565 | if (ssb_mode != SPEC_STORE_BYPASS_PRCTL && |
566 | ssb_mode != SPEC_STORE_BYPASS_SECCOMP) | |
574dcf89 TG |
567 | return -ENXIO; |
568 | ||
733f4234 TG |
569 | switch (ctrl) { |
570 | case PR_SPEC_ENABLE: | |
571 | /* If speculation is force disabled, enable is not allowed */ | |
572 | if (task_spec_ssb_force_disable(task)) | |
573 | return -EPERM; | |
574 | task_clear_spec_ssb_disable(task); | |
8fe36c9d | 575 | update = test_and_clear_tsk_thread_flag(task, TIF_SSBD); |
733f4234 TG |
576 | break; |
577 | case PR_SPEC_DISABLE: | |
578 | task_set_spec_ssb_disable(task); | |
8fe36c9d | 579 | update = !test_and_set_tsk_thread_flag(task, TIF_SSBD); |
733f4234 TG |
580 | break; |
581 | case PR_SPEC_FORCE_DISABLE: | |
582 | task_set_spec_ssb_disable(task); | |
583 | task_set_spec_ssb_force_disable(task); | |
8fe36c9d | 584 | update = !test_and_set_tsk_thread_flag(task, TIF_SSBD); |
733f4234 TG |
585 | break; |
586 | default: | |
587 | return -ERANGE; | |
588 | } | |
574dcf89 | 589 | |
199bfed2 KC |
590 | /* |
591 | * If being set on non-current task, delay setting the CPU | |
592 | * mitigation until it is next scheduled. | |
593 | */ | |
733f4234 | 594 | if (task == current && update) |
8a3ba093 | 595 | speculative_store_bypass_update_current(); |
574dcf89 TG |
596 | |
597 | return 0; | |
598 | } | |
599 | ||
5b38e244 TG |
600 | int arch_prctl_spec_ctrl_set(struct task_struct *task, unsigned long which, |
601 | unsigned long ctrl) | |
602 | { | |
603 | switch (which) { | |
604 | case PR_SPEC_STORE_BYPASS: | |
605 | return ssb_prctl_set(task, ctrl); | |
606 | default: | |
607 | return -ENODEV; | |
608 | } | |
609 | } | |
610 | ||
611 | #ifdef CONFIG_SECCOMP | |
612 | void arch_seccomp_spec_mitigate(struct task_struct *task) | |
613 | { | |
c7416003 KC |
614 | if (ssb_mode == SPEC_STORE_BYPASS_SECCOMP) |
615 | ssb_prctl_set(task, PR_SPEC_FORCE_DISABLE); | |
5b38e244 TG |
616 | } |
617 | #endif | |
618 | ||
199bfed2 | 619 | static int ssb_prctl_get(struct task_struct *task) |
574dcf89 TG |
620 | { |
621 | switch (ssb_mode) { | |
622 | case SPEC_STORE_BYPASS_DISABLE: | |
623 | return PR_SPEC_DISABLE; | |
c7416003 | 624 | case SPEC_STORE_BYPASS_SECCOMP: |
574dcf89 | 625 | case SPEC_STORE_BYPASS_PRCTL: |
733f4234 TG |
626 | if (task_spec_ssb_force_disable(task)) |
627 | return PR_SPEC_PRCTL | PR_SPEC_FORCE_DISABLE; | |
628 | if (task_spec_ssb_disable(task)) | |
574dcf89 TG |
629 | return PR_SPEC_PRCTL | PR_SPEC_DISABLE; |
630 | return PR_SPEC_PRCTL | PR_SPEC_ENABLE; | |
631 | default: | |
632 | if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) | |
633 | return PR_SPEC_ENABLE; | |
634 | return PR_SPEC_NOT_AFFECTED; | |
635 | } | |
636 | } | |
637 | ||
199bfed2 | 638 | int arch_prctl_spec_ctrl_get(struct task_struct *task, unsigned long which) |
574dcf89 TG |
639 | { |
640 | switch (which) { | |
641 | case PR_SPEC_STORE_BYPASS: | |
199bfed2 | 642 | return ssb_prctl_get(task); |
574dcf89 TG |
643 | default: |
644 | return -ENODEV; | |
645 | } | |
646 | } | |
647 | ||
23b9eab9 KRW |
648 | void x86_spec_ctrl_setup_ap(void) |
649 | { | |
50f9b919 | 650 | if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) |
208efa83 | 651 | wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); |
c37b94dd KRW |
652 | |
653 | if (ssb_mode == SPEC_STORE_BYPASS_DISABLE) | |
8fe36c9d | 654 | x86_amd_ssb_disable(); |
23b9eab9 KRW |
655 | } |
656 | ||
73ca9f47 KRW |
657 | #undef pr_fmt |
658 | #define pr_fmt(fmt) "L1TF: " fmt | |
b9cfedcd | 659 | |
24fcb53c JK |
660 | /* Default mitigation for L1TF-affected CPUs */ |
661 | enum l1tf_mitigations l1tf_mitigation __ro_after_init = L1TF_MITIGATION_FLUSH; | |
b9cfedcd | 662 | #if IS_ENABLED(CONFIG_KVM_INTEL) |
24fcb53c JK |
663 | EXPORT_SYMBOL_GPL(l1tf_mitigation); |
664 | ||
522c7bed | 665 | enum vmx_l1d_flush_state l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO; |
b9cfedcd TG |
666 | EXPORT_SYMBOL_GPL(l1tf_vmx_mitigation); |
667 | #endif | |
668 | ||
f1f016ed AK |
669 | /* |
670 | * These CPUs all support 44bits physical address space internally in the | |
671 | * cache but CPUID can report a smaller number of physical address bits. | |
672 | * | |
673 | * The L1TF mitigation uses the top most address bit for the inversion of | |
674 | * non present PTEs. When the installed memory reaches into the top most | |
675 | * address bit due to memory holes, which has been observed on machines | |
676 | * which report 36bits physical address bits and have 32G RAM installed, | |
677 | * then the mitigation range check in l1tf_select_mitigation() triggers. | |
678 | * This is a false positive because the mitigation is still possible due to | |
679 | * the fact that the cache uses 44bit internally. Use the cache bits | |
680 | * instead of the reported physical bits and adjust them on the affected | |
681 | * machines to 44bit if the reported bits are less than 44. | |
682 | */ | |
683 | static void override_cache_bits(struct cpuinfo_x86 *c) | |
684 | { | |
685 | if (c->x86 != 6) | |
686 | return; | |
687 | ||
688 | switch (c->x86_model) { | |
689 | case INTEL_FAM6_NEHALEM: | |
690 | case INTEL_FAM6_WESTMERE: | |
691 | case INTEL_FAM6_SANDYBRIDGE: | |
692 | case INTEL_FAM6_IVYBRIDGE: | |
693 | case INTEL_FAM6_HASWELL_CORE: | |
694 | case INTEL_FAM6_HASWELL_ULT: | |
695 | case INTEL_FAM6_HASWELL_GT3E: | |
696 | case INTEL_FAM6_BROADWELL_CORE: | |
697 | case INTEL_FAM6_BROADWELL_GT3E: | |
698 | case INTEL_FAM6_SKYLAKE_MOBILE: | |
699 | case INTEL_FAM6_SKYLAKE_DESKTOP: | |
700 | case INTEL_FAM6_KABYLAKE_MOBILE: | |
701 | case INTEL_FAM6_KABYLAKE_DESKTOP: | |
702 | if (c->x86_cache_bits < 44) | |
703 | c->x86_cache_bits = 44; | |
704 | break; | |
705 | } | |
706 | } | |
707 | ||
73ca9f47 KRW |
708 | static void __init l1tf_select_mitigation(void) |
709 | { | |
710 | u64 half_pa; | |
711 | ||
712 | if (!boot_cpu_has_bug(X86_BUG_L1TF)) | |
713 | return; | |
714 | ||
f1f016ed AK |
715 | override_cache_bits(&boot_cpu_data); |
716 | ||
24fcb53c JK |
717 | switch (l1tf_mitigation) { |
718 | case L1TF_MITIGATION_OFF: | |
719 | case L1TF_MITIGATION_FLUSH_NOWARN: | |
720 | case L1TF_MITIGATION_FLUSH: | |
721 | break; | |
722 | case L1TF_MITIGATION_FLUSH_NOSMT: | |
723 | case L1TF_MITIGATION_FULL: | |
724 | cpu_smt_disable(false); | |
725 | break; | |
726 | case L1TF_MITIGATION_FULL_FORCE: | |
727 | cpu_smt_disable(true); | |
728 | break; | |
729 | } | |
730 | ||
73ca9f47 KRW |
731 | #if CONFIG_PGTABLE_LEVELS == 2 |
732 | pr_warn("Kernel not compiled for PAE. No mitigation for L1TF\n"); | |
733 | return; | |
734 | #endif | |
735 | ||
73ca9f47 KRW |
736 | half_pa = (u64)l1tf_pfn_limit() << PAGE_SHIFT; |
737 | if (e820__mapped_any(half_pa, ULLONG_MAX - half_pa, E820_TYPE_RAM)) { | |
738 | pr_warn("System has more than MAX_PA/2 memory. L1TF mitigation not effective.\n"); | |
739 | return; | |
740 | } | |
741 | ||
742 | setup_force_cpu_cap(X86_FEATURE_L1TF_PTEINV); | |
743 | } | |
24fcb53c JK |
744 | |
745 | static int __init l1tf_cmdline(char *str) | |
746 | { | |
747 | if (!boot_cpu_has_bug(X86_BUG_L1TF)) | |
748 | return 0; | |
749 | ||
750 | if (!str) | |
751 | return -EINVAL; | |
752 | ||
753 | if (!strcmp(str, "off")) | |
754 | l1tf_mitigation = L1TF_MITIGATION_OFF; | |
755 | else if (!strcmp(str, "flush,nowarn")) | |
756 | l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOWARN; | |
757 | else if (!strcmp(str, "flush")) | |
758 | l1tf_mitigation = L1TF_MITIGATION_FLUSH; | |
759 | else if (!strcmp(str, "flush,nosmt")) | |
760 | l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOSMT; | |
761 | else if (!strcmp(str, "full")) | |
762 | l1tf_mitigation = L1TF_MITIGATION_FULL; | |
763 | else if (!strcmp(str, "full,force")) | |
764 | l1tf_mitigation = L1TF_MITIGATION_FULL_FORCE; | |
765 | ||
766 | return 0; | |
767 | } | |
768 | early_param("l1tf", l1tf_cmdline); | |
769 | ||
73ca9f47 KRW |
770 | #undef pr_fmt |
771 | ||
61dc0f55 | 772 | #ifdef CONFIG_SYSFS |
d2b8fc2d | 773 | |
b9cfedcd TG |
774 | #define L1TF_DEFAULT_MSG "Mitigation: PTE Inversion" |
775 | ||
776 | #if IS_ENABLED(CONFIG_KVM_INTEL) | |
777 | static const char *l1tf_vmx_states[] = { | |
1ead4979 TG |
778 | [VMENTER_L1D_FLUSH_AUTO] = "auto", |
779 | [VMENTER_L1D_FLUSH_NEVER] = "vulnerable", | |
780 | [VMENTER_L1D_FLUSH_COND] = "conditional cache flushes", | |
781 | [VMENTER_L1D_FLUSH_ALWAYS] = "cache flushes", | |
782 | [VMENTER_L1D_FLUSH_EPT_DISABLED] = "EPT disabled", | |
364a4311 | 783 | [VMENTER_L1D_FLUSH_NOT_REQUIRED] = "flush not necessary" |
b9cfedcd TG |
784 | }; |
785 | ||
786 | static ssize_t l1tf_show_state(char *buf) | |
787 | { | |
788 | if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO) | |
789 | return sprintf(buf, "%s\n", L1TF_DEFAULT_MSG); | |
790 | ||
3899f7b1 PB |
791 | if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_EPT_DISABLED || |
792 | (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER && | |
793 | cpu_smt_control == CPU_SMT_ENABLED)) | |
794 | return sprintf(buf, "%s; VMX: %s\n", L1TF_DEFAULT_MSG, | |
795 | l1tf_vmx_states[l1tf_vmx_mitigation]); | |
796 | ||
797 | return sprintf(buf, "%s; VMX: %s, SMT %s\n", L1TF_DEFAULT_MSG, | |
798 | l1tf_vmx_states[l1tf_vmx_mitigation], | |
799 | cpu_smt_control == CPU_SMT_ENABLED ? "vulnerable" : "disabled"); | |
b9cfedcd TG |
800 | } |
801 | #else | |
802 | static ssize_t l1tf_show_state(char *buf) | |
803 | { | |
804 | return sprintf(buf, "%s\n", L1TF_DEFAULT_MSG); | |
805 | } | |
806 | #endif | |
807 | ||
ace051d5 | 808 | static ssize_t cpu_show_common(struct device *dev, struct device_attribute *attr, |
043d480e | 809 | char *buf, unsigned int bug) |
61dc0f55 | 810 | { |
d2b8fc2d | 811 | if (!boot_cpu_has_bug(bug)) |
61dc0f55 | 812 | return sprintf(buf, "Not affected\n"); |
d2b8fc2d KRW |
813 | |
814 | switch (bug) { | |
815 | case X86_BUG_CPU_MELTDOWN: | |
816 | if (boot_cpu_has(X86_FEATURE_PTI)) | |
817 | return sprintf(buf, "Mitigation: PTI\n"); | |
818 | ||
819 | break; | |
820 | ||
821 | case X86_BUG_SPECTRE_V1: | |
822 | return sprintf(buf, "Mitigation: __user pointer sanitization\n"); | |
823 | ||
824 | case X86_BUG_SPECTRE_V2: | |
825 | return sprintf(buf, "%s%s%s%s\n", spectre_v2_strings[spectre_v2_enabled], | |
826 | boot_cpu_has(X86_FEATURE_USE_IBPB) ? ", IBPB" : "", | |
827 | boot_cpu_has(X86_FEATURE_USE_IBRS_FW) ? ", IBRS_FW" : "", | |
828 | spectre_v2_module_string()); | |
829 | ||
e63490c8 KRW |
830 | case X86_BUG_SPEC_STORE_BYPASS: |
831 | return sprintf(buf, "%s\n", ssb_strings[ssb_mode]); | |
832 | ||
05516ad8 AK |
833 | case X86_BUG_L1TF: |
834 | if (boot_cpu_has(X86_FEATURE_L1TF_PTEINV)) | |
b9cfedcd | 835 | return l1tf_show_state(buf); |
05516ad8 | 836 | break; |
d2b8fc2d KRW |
837 | default: |
838 | break; | |
839 | } | |
840 | ||
61dc0f55 TG |
841 | return sprintf(buf, "Vulnerable\n"); |
842 | } | |
843 | ||
d2b8fc2d KRW |
844 | ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, char *buf) |
845 | { | |
846 | return cpu_show_common(dev, attr, buf, X86_BUG_CPU_MELTDOWN); | |
847 | } | |
848 | ||
713f1b95 | 849 | ssize_t cpu_show_spectre_v1(struct device *dev, struct device_attribute *attr, char *buf) |
61dc0f55 | 850 | { |
d2b8fc2d | 851 | return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V1); |
61dc0f55 TG |
852 | } |
853 | ||
713f1b95 | 854 | ssize_t cpu_show_spectre_v2(struct device *dev, struct device_attribute *attr, char *buf) |
61dc0f55 | 855 | { |
d2b8fc2d | 856 | return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V2); |
61dc0f55 | 857 | } |
d7de9182 KRW |
858 | |
859 | ssize_t cpu_show_spec_store_bypass(struct device *dev, struct device_attribute *attr, char *buf) | |
860 | { | |
861 | return cpu_show_common(dev, attr, buf, X86_BUG_SPEC_STORE_BYPASS); | |
862 | } | |
05516ad8 AK |
863 | |
864 | ssize_t cpu_show_l1tf(struct device *dev, struct device_attribute *attr, char *buf) | |
865 | { | |
866 | return cpu_show_common(dev, attr, buf, X86_BUG_L1TF); | |
867 | } | |
61dc0f55 | 868 | #endif |