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b2441318 | 1 | // SPDX-License-Identifier: GPL-2.0 |
1353ebb4 | 2 | /* |
1353ebb4 JF |
3 | * Copyright (C) 1994 Linus Torvalds |
4 | * | |
5 | * Cyrix stuff, June 1998 by: | |
6 | * - Rafael R. Reilova (moved everything from head.S), | |
7 | * <rreilova@ececs.uc.edu> | |
8 | * - Channing Corn (tests & fixes), | |
9 | * - Andrew D. Balsa (code cleanup). | |
10 | */ | |
11 | #include <linux/init.h> | |
12 | #include <linux/utsname.h> | |
61dc0f55 | 13 | #include <linux/cpu.h> |
d280282b | 14 | #include <linux/module.h> |
574dcf89 TG |
15 | #include <linux/nospec.h> |
16 | #include <linux/prctl.h> | |
da285121 | 17 | |
d7a6a163 | 18 | #include <asm/spec-ctrl.h> |
da285121 | 19 | #include <asm/cmdline.h> |
91eb1b79 | 20 | #include <asm/bugs.h> |
1353ebb4 | 21 | #include <asm/processor.h> |
7ebad705 | 22 | #include <asm/processor-flags.h> |
952f07ec | 23 | #include <asm/fpu/internal.h> |
1353ebb4 | 24 | #include <asm/msr.h> |
b9cfedcd | 25 | #include <asm/vmx.h> |
1353ebb4 JF |
26 | #include <asm/paravirt.h> |
27 | #include <asm/alternative.h> | |
62a67e12 | 28 | #include <asm/pgtable.h> |
d1163651 | 29 | #include <asm/set_memory.h> |
c995efd5 | 30 | #include <asm/intel-family.h> |
05516ad8 | 31 | #include <asm/e820/api.h> |
1353ebb4 | 32 | |
da285121 | 33 | static void __init spectre_v2_select_mitigation(void); |
e63490c8 | 34 | static void __init ssb_select_mitigation(void); |
05516ad8 | 35 | static void __init l1tf_select_mitigation(void); |
da285121 | 36 | |
7011f443 JK |
37 | /* The base value of the SPEC_CTRL MSR that always has to be preserved. */ |
38 | u64 x86_spec_ctrl_base; | |
4ac9b1f9 | 39 | EXPORT_SYMBOL_GPL(x86_spec_ctrl_base); |
7011f443 | 40 | static DEFINE_MUTEX(spec_ctrl_mutex); |
296b454a | 41 | |
d0c3bedd KRW |
42 | /* |
43 | * The vendor and possibly platform specific bits which can be modified in | |
44 | * x86_spec_ctrl_base. | |
45 | */ | |
e5f984ed | 46 | static u64 __ro_after_init x86_spec_ctrl_mask = SPEC_CTRL_IBRS; |
d0c3bedd | 47 | |
c37b94dd KRW |
48 | /* |
49 | * AMD specific MSR info for Speculative Store Bypass control. | |
8fe36c9d | 50 | * x86_amd_ls_cfg_ssbd_mask is initialized in identify_boot_cpu(). |
c37b94dd KRW |
51 | */ |
52 | u64 __ro_after_init x86_amd_ls_cfg_base; | |
8fe36c9d | 53 | u64 __ro_after_init x86_amd_ls_cfg_ssbd_mask; |
c37b94dd | 54 | |
1353ebb4 JF |
55 | void __init check_bugs(void) |
56 | { | |
57 | identify_boot_cpu(); | |
55a36b65 | 58 | |
483ec3c6 TG |
59 | /* |
60 | * identify_boot_cpu() initialized SMT support information, let the | |
61 | * core code know. | |
62 | */ | |
ade31b9e | 63 | cpu_smt_check_topology_early(); |
483ec3c6 | 64 | |
62a67e12 BP |
65 | if (!IS_ENABLED(CONFIG_SMP)) { |
66 | pr_info("CPU: "); | |
67 | print_cpu_info(&boot_cpu_data); | |
68 | } | |
69 | ||
296b454a KRW |
70 | /* |
71 | * Read the SPEC_CTRL MSR to account for reserved bits which may | |
c37b94dd KRW |
72 | * have unknown values. AMD64_LS_CFG MSR is cached in the early AMD |
73 | * init code as it is not enumerated and depends on the family. | |
296b454a | 74 | */ |
50f9b919 | 75 | if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) |
296b454a KRW |
76 | rdmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); |
77 | ||
e5f984ed TG |
78 | /* Allow STIBP in MSR_SPEC_CTRL if supported */ |
79 | if (boot_cpu_has(X86_FEATURE_STIBP)) | |
80 | x86_spec_ctrl_mask |= SPEC_CTRL_STIBP; | |
81 | ||
da285121 DW |
82 | /* Select the proper spectre mitigation before patching alternatives */ |
83 | spectre_v2_select_mitigation(); | |
84 | ||
e63490c8 KRW |
85 | /* |
86 | * Select proper mitigation for any exposure to the Speculative Store | |
87 | * Bypass vulnerability. | |
88 | */ | |
89 | ssb_select_mitigation(); | |
90 | ||
05516ad8 AK |
91 | l1tf_select_mitigation(); |
92 | ||
62a67e12 | 93 | #ifdef CONFIG_X86_32 |
55a36b65 BP |
94 | /* |
95 | * Check whether we are able to run this kernel safely on SMP. | |
96 | * | |
97 | * - i386 is no longer supported. | |
98 | * - In order to run on anything without a TSC, we need to be | |
99 | * compiled for a i486. | |
100 | */ | |
101 | if (boot_cpu_data.x86 < 4) | |
102 | panic("Kernel requires i486+ for 'invlpg' and other features"); | |
103 | ||
bfe4bb15 MV |
104 | init_utsname()->machine[1] = |
105 | '0' + (boot_cpu_data.x86 > 6 ? 6 : boot_cpu_data.x86); | |
1353ebb4 | 106 | alternative_instructions(); |
304bceda | 107 | |
4d164092 | 108 | fpu__init_check_bugs(); |
62a67e12 BP |
109 | #else /* CONFIG_X86_64 */ |
110 | alternative_instructions(); | |
111 | ||
112 | /* | |
113 | * Make sure the first 2MB area is not mapped by huge pages | |
114 | * There are typically fixed size MTRRs in there and overlapping | |
115 | * MTRRs into large pages causes slow downs. | |
116 | * | |
117 | * Right now we don't do that with gbpages because there seems | |
118 | * very little benefit for that case. | |
119 | */ | |
120 | if (!direct_gbpages) | |
121 | set_memory_4k((unsigned long)__va(0), 1); | |
122 | #endif | |
1353ebb4 | 123 | } |
61dc0f55 | 124 | |
da285121 DW |
125 | /* The kernel command line selection */ |
126 | enum spectre_v2_mitigation_cmd { | |
127 | SPECTRE_V2_CMD_NONE, | |
128 | SPECTRE_V2_CMD_AUTO, | |
129 | SPECTRE_V2_CMD_FORCE, | |
130 | SPECTRE_V2_CMD_RETPOLINE, | |
131 | SPECTRE_V2_CMD_RETPOLINE_GENERIC, | |
132 | SPECTRE_V2_CMD_RETPOLINE_AMD, | |
133 | }; | |
134 | ||
135 | static const char *spectre_v2_strings[] = { | |
136 | [SPECTRE_V2_NONE] = "Vulnerable", | |
137 | [SPECTRE_V2_RETPOLINE_MINIMAL] = "Vulnerable: Minimal generic ASM retpoline", | |
138 | [SPECTRE_V2_RETPOLINE_MINIMAL_AMD] = "Vulnerable: Minimal AMD ASM retpoline", | |
139 | [SPECTRE_V2_RETPOLINE_GENERIC] = "Mitigation: Full generic retpoline", | |
140 | [SPECTRE_V2_RETPOLINE_AMD] = "Mitigation: Full AMD retpoline", | |
1044fde9 | 141 | [SPECTRE_V2_IBRS_ENHANCED] = "Mitigation: Enhanced IBRS", |
da285121 DW |
142 | }; |
143 | ||
144 | #undef pr_fmt | |
bbb5e08b | 145 | #define pr_fmt(fmt) "Spectre V2 : " fmt |
da285121 | 146 | |
b5e6d77d KC |
147 | static enum spectre_v2_mitigation spectre_v2_enabled __ro_after_init = |
148 | SPECTRE_V2_NONE; | |
d280282b | 149 | |
12376b62 BP |
150 | void |
151 | x86_virt_spec_ctrl(u64 guest_spec_ctrl, u64 guest_virt_spec_ctrl, bool setguest) | |
19fff03f | 152 | { |
e5f984ed | 153 | u64 msrval, guestval, hostval = x86_spec_ctrl_base; |
12376b62 | 154 | struct thread_info *ti = current_thread_info(); |
5407b7f8 | 155 | |
50f9b919 | 156 | /* Is MSR_SPEC_CTRL implemented ? */ |
12376b62 | 157 | if (static_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) { |
e5f984ed TG |
158 | /* |
159 | * Restrict guest_spec_ctrl to supported values. Clear the | |
160 | * modifiable bits in the host base value and or the | |
161 | * modifiable bits from the guest value. | |
162 | */ | |
163 | guestval = hostval & ~x86_spec_ctrl_mask; | |
164 | guestval |= guest_spec_ctrl & x86_spec_ctrl_mask; | |
165 | ||
12376b62 | 166 | /* SSBD controlled in MSR_SPEC_CTRL */ |
5005c716 TL |
167 | if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) || |
168 | static_cpu_has(X86_FEATURE_AMD_SSBD)) | |
e5f984ed | 169 | hostval |= ssbd_tif_to_spec_ctrl(ti->flags); |
12376b62 | 170 | |
e5f984ed TG |
171 | if (hostval != guestval) { |
172 | msrval = setguest ? guestval : hostval; | |
173 | wrmsrl(MSR_IA32_SPEC_CTRL, msrval); | |
12376b62 BP |
174 | } |
175 | } | |
1238ed31 TG |
176 | |
177 | /* | |
178 | * If SSBD is not handled in MSR_SPEC_CTRL on AMD, update | |
179 | * MSR_AMD64_L2_CFG or MSR_VIRT_SPEC_CTRL if supported. | |
180 | */ | |
181 | if (!static_cpu_has(X86_FEATURE_LS_CFG_SSBD) && | |
182 | !static_cpu_has(X86_FEATURE_VIRT_SSBD)) | |
183 | return; | |
184 | ||
185 | /* | |
186 | * If the host has SSBD mitigation enabled, force it in the host's | |
187 | * virtual MSR value. If its not permanently enabled, evaluate | |
188 | * current's TIF_SSBD thread flag. | |
189 | */ | |
190 | if (static_cpu_has(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE)) | |
191 | hostval = SPEC_CTRL_SSBD; | |
192 | else | |
193 | hostval = ssbd_tif_to_spec_ctrl(ti->flags); | |
194 | ||
195 | /* Sanitize the guest value */ | |
196 | guestval = guest_virt_spec_ctrl & SPEC_CTRL_SSBD; | |
197 | ||
198 | if (hostval != guestval) { | |
199 | unsigned long tif; | |
200 | ||
201 | tif = setguest ? ssbd_spec_ctrl_to_tif(guestval) : | |
202 | ssbd_spec_ctrl_to_tif(hostval); | |
203 | ||
204 | speculative_store_bypass_update(tif); | |
205 | } | |
19fff03f | 206 | } |
12376b62 | 207 | EXPORT_SYMBOL_GPL(x86_virt_spec_ctrl); |
19fff03f | 208 | |
8fe36c9d | 209 | static void x86_amd_ssb_disable(void) |
c37b94dd | 210 | { |
8fe36c9d | 211 | u64 msrval = x86_amd_ls_cfg_base | x86_amd_ls_cfg_ssbd_mask; |
c37b94dd | 212 | |
65e02bbd TL |
213 | if (boot_cpu_has(X86_FEATURE_VIRT_SSBD)) |
214 | wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, SPEC_CTRL_SSBD); | |
215 | else if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD)) | |
c37b94dd KRW |
216 | wrmsrl(MSR_AMD64_LS_CFG, msrval); |
217 | } | |
218 | ||
d280282b | 219 | #ifdef RETPOLINE |
bb3c2578 TG |
220 | static bool spectre_v2_bad_module; |
221 | ||
d280282b AK |
222 | bool retpoline_module_ok(bool has_retpoline) |
223 | { | |
224 | if (spectre_v2_enabled == SPECTRE_V2_NONE || has_retpoline) | |
225 | return true; | |
226 | ||
c8b8e109 | 227 | pr_err("System may be vulnerable to spectre v2\n"); |
d280282b AK |
228 | spectre_v2_bad_module = true; |
229 | return false; | |
230 | } | |
bb3c2578 TG |
231 | |
232 | static inline const char *spectre_v2_module_string(void) | |
233 | { | |
234 | return spectre_v2_bad_module ? " - vulnerable module loaded" : ""; | |
235 | } | |
236 | #else | |
237 | static inline const char *spectre_v2_module_string(void) { return ""; } | |
d280282b | 238 | #endif |
da285121 DW |
239 | |
240 | static void __init spec2_print_if_insecure(const char *reason) | |
241 | { | |
242 | if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2)) | |
17c33e7c | 243 | pr_info("%s selected on command line.\n", reason); |
da285121 DW |
244 | } |
245 | ||
246 | static void __init spec2_print_if_secure(const char *reason) | |
247 | { | |
248 | if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2)) | |
17c33e7c | 249 | pr_info("%s selected on command line.\n", reason); |
da285121 DW |
250 | } |
251 | ||
252 | static inline bool retp_compiler(void) | |
253 | { | |
254 | return __is_defined(RETPOLINE); | |
255 | } | |
256 | ||
257 | static inline bool match_option(const char *arg, int arglen, const char *opt) | |
258 | { | |
259 | int len = strlen(opt); | |
260 | ||
261 | return len == arglen && !strncmp(arg, opt, len); | |
262 | } | |
263 | ||
17c33e7c KA |
264 | static const struct { |
265 | const char *option; | |
266 | enum spectre_v2_mitigation_cmd cmd; | |
267 | bool secure; | |
268 | } mitigation_options[] = { | |
269 | { "off", SPECTRE_V2_CMD_NONE, false }, | |
270 | { "on", SPECTRE_V2_CMD_FORCE, true }, | |
271 | { "retpoline", SPECTRE_V2_CMD_RETPOLINE, false }, | |
272 | { "retpoline,amd", SPECTRE_V2_CMD_RETPOLINE_AMD, false }, | |
273 | { "retpoline,generic", SPECTRE_V2_CMD_RETPOLINE_GENERIC, false }, | |
274 | { "auto", SPECTRE_V2_CMD_AUTO, false }, | |
275 | }; | |
276 | ||
da285121 DW |
277 | static enum spectre_v2_mitigation_cmd __init spectre_v2_parse_cmdline(void) |
278 | { | |
279 | char arg[20]; | |
17c33e7c KA |
280 | int ret, i; |
281 | enum spectre_v2_mitigation_cmd cmd = SPECTRE_V2_CMD_AUTO; | |
282 | ||
283 | if (cmdline_find_option_bool(boot_command_line, "nospectre_v2")) | |
284 | return SPECTRE_V2_CMD_NONE; | |
285 | else { | |
713f1b95 | 286 | ret = cmdline_find_option(boot_command_line, "spectre_v2", arg, sizeof(arg)); |
17c33e7c KA |
287 | if (ret < 0) |
288 | return SPECTRE_V2_CMD_AUTO; | |
289 | ||
290 | for (i = 0; i < ARRAY_SIZE(mitigation_options); i++) { | |
291 | if (!match_option(arg, ret, mitigation_options[i].option)) | |
292 | continue; | |
293 | cmd = mitigation_options[i].cmd; | |
294 | break; | |
295 | } | |
296 | ||
297 | if (i >= ARRAY_SIZE(mitigation_options)) { | |
ecad7915 | 298 | pr_err("unknown option (%s). Switching to AUTO select\n", arg); |
da285121 DW |
299 | return SPECTRE_V2_CMD_AUTO; |
300 | } | |
301 | } | |
302 | ||
17c33e7c KA |
303 | if ((cmd == SPECTRE_V2_CMD_RETPOLINE || |
304 | cmd == SPECTRE_V2_CMD_RETPOLINE_AMD || | |
305 | cmd == SPECTRE_V2_CMD_RETPOLINE_GENERIC) && | |
306 | !IS_ENABLED(CONFIG_RETPOLINE)) { | |
713f1b95 | 307 | pr_err("%s selected but not compiled in. Switching to AUTO select\n", mitigation_options[i].option); |
da285121 | 308 | return SPECTRE_V2_CMD_AUTO; |
17c33e7c KA |
309 | } |
310 | ||
311 | if (cmd == SPECTRE_V2_CMD_RETPOLINE_AMD && | |
312 | boot_cpu_data.x86_vendor != X86_VENDOR_AMD) { | |
313 | pr_err("retpoline,amd selected but CPU is not AMD. Switching to AUTO select\n"); | |
314 | return SPECTRE_V2_CMD_AUTO; | |
315 | } | |
316 | ||
317 | if (mitigation_options[i].secure) | |
318 | spec2_print_if_secure(mitigation_options[i].option); | |
319 | else | |
320 | spec2_print_if_insecure(mitigation_options[i].option); | |
321 | ||
322 | return cmd; | |
da285121 DW |
323 | } |
324 | ||
7011f443 JK |
325 | static bool stibp_needed(void) |
326 | { | |
327 | if (spectre_v2_enabled == SPECTRE_V2_NONE) | |
328 | return false; | |
329 | ||
330 | if (!boot_cpu_has(X86_FEATURE_STIBP)) | |
331 | return false; | |
332 | ||
333 | return true; | |
334 | } | |
335 | ||
336 | static void update_stibp_msr(void *info) | |
337 | { | |
338 | wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); | |
339 | } | |
340 | ||
341 | void arch_smt_update(void) | |
342 | { | |
343 | u64 mask; | |
344 | ||
345 | if (!stibp_needed()) | |
346 | return; | |
347 | ||
348 | mutex_lock(&spec_ctrl_mutex); | |
349 | mask = x86_spec_ctrl_base; | |
350 | if (cpu_smt_control == CPU_SMT_ENABLED) | |
351 | mask |= SPEC_CTRL_STIBP; | |
352 | else | |
353 | mask &= ~SPEC_CTRL_STIBP; | |
354 | ||
355 | if (mask != x86_spec_ctrl_base) { | |
356 | pr_info("Spectre v2 cross-process SMT mitigation: %s STIBP\n", | |
357 | cpu_smt_control == CPU_SMT_ENABLED ? | |
358 | "Enabling" : "Disabling"); | |
359 | x86_spec_ctrl_base = mask; | |
360 | on_each_cpu(update_stibp_msr, NULL, 1); | |
361 | } | |
362 | mutex_unlock(&spec_ctrl_mutex); | |
363 | } | |
364 | ||
da285121 DW |
365 | static void __init spectre_v2_select_mitigation(void) |
366 | { | |
367 | enum spectre_v2_mitigation_cmd cmd = spectre_v2_parse_cmdline(); | |
368 | enum spectre_v2_mitigation mode = SPECTRE_V2_NONE; | |
369 | ||
370 | /* | |
371 | * If the CPU is not affected and the command line mode is NONE or AUTO | |
372 | * then nothing to do. | |
373 | */ | |
374 | if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2) && | |
375 | (cmd == SPECTRE_V2_CMD_NONE || cmd == SPECTRE_V2_CMD_AUTO)) | |
376 | return; | |
377 | ||
378 | switch (cmd) { | |
379 | case SPECTRE_V2_CMD_NONE: | |
380 | return; | |
381 | ||
382 | case SPECTRE_V2_CMD_FORCE: | |
da285121 | 383 | case SPECTRE_V2_CMD_AUTO: |
1044fde9 SP |
384 | if (boot_cpu_has(X86_FEATURE_IBRS_ENHANCED)) { |
385 | mode = SPECTRE_V2_IBRS_ENHANCED; | |
386 | /* Force it so VMEXIT will restore correctly */ | |
387 | x86_spec_ctrl_base |= SPEC_CTRL_IBRS; | |
388 | wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); | |
389 | goto specv2_set_mode; | |
390 | } | |
d0f293e0 DL |
391 | if (IS_ENABLED(CONFIG_RETPOLINE)) |
392 | goto retpoline_auto; | |
393 | break; | |
da285121 DW |
394 | case SPECTRE_V2_CMD_RETPOLINE_AMD: |
395 | if (IS_ENABLED(CONFIG_RETPOLINE)) | |
396 | goto retpoline_amd; | |
397 | break; | |
398 | case SPECTRE_V2_CMD_RETPOLINE_GENERIC: | |
399 | if (IS_ENABLED(CONFIG_RETPOLINE)) | |
400 | goto retpoline_generic; | |
401 | break; | |
402 | case SPECTRE_V2_CMD_RETPOLINE: | |
403 | if (IS_ENABLED(CONFIG_RETPOLINE)) | |
404 | goto retpoline_auto; | |
405 | break; | |
406 | } | |
713f1b95 | 407 | pr_err("Spectre mitigation: kernel not compiled with retpoline; no mitigation available!"); |
da285121 DW |
408 | return; |
409 | ||
410 | retpoline_auto: | |
411 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) { | |
412 | retpoline_amd: | |
413 | if (!boot_cpu_has(X86_FEATURE_LFENCE_RDTSC)) { | |
713f1b95 | 414 | pr_err("Spectre mitigation: LFENCE not serializing, switching to generic retpoline\n"); |
da285121 DW |
415 | goto retpoline_generic; |
416 | } | |
417 | mode = retp_compiler() ? SPECTRE_V2_RETPOLINE_AMD : | |
418 | SPECTRE_V2_RETPOLINE_MINIMAL_AMD; | |
419 | setup_force_cpu_cap(X86_FEATURE_RETPOLINE_AMD); | |
420 | setup_force_cpu_cap(X86_FEATURE_RETPOLINE); | |
421 | } else { | |
422 | retpoline_generic: | |
423 | mode = retp_compiler() ? SPECTRE_V2_RETPOLINE_GENERIC : | |
424 | SPECTRE_V2_RETPOLINE_MINIMAL; | |
425 | setup_force_cpu_cap(X86_FEATURE_RETPOLINE); | |
426 | } | |
427 | ||
1044fde9 | 428 | specv2_set_mode: |
da285121 DW |
429 | spectre_v2_enabled = mode; |
430 | pr_info("%s\n", spectre_v2_strings[mode]); | |
c995efd5 DW |
431 | |
432 | /* | |
14623a43 JK |
433 | * If spectre v2 protection has been enabled, unconditionally fill |
434 | * RSB during a context switch; this protects against two independent | |
435 | * issues: | |
c995efd5 | 436 | * |
14623a43 JK |
437 | * - RSB underflow (and switch to BTB) on Skylake+ |
438 | * - SpectreRSB variant of spectre v2 on X86_BUG_SPECTRE_V2 CPUs | |
c995efd5 | 439 | */ |
14623a43 JK |
440 | setup_force_cpu_cap(X86_FEATURE_RSB_CTXSW); |
441 | pr_info("Spectre v2 / SpectreRSB mitigation: Filling RSB on context switch\n"); | |
bd12e896 DW |
442 | |
443 | /* Initialize Indirect Branch Prediction Barrier if supported */ | |
581abf91 DW |
444 | if (boot_cpu_has(X86_FEATURE_IBPB)) { |
445 | setup_force_cpu_cap(X86_FEATURE_USE_IBPB); | |
713f1b95 | 446 | pr_info("Spectre v2 mitigation: Enabling Indirect Branch Prediction Barrier\n"); |
bd12e896 | 447 | } |
390b99c3 DW |
448 | |
449 | /* | |
450 | * Retpoline means the kernel is safe because it has no indirect | |
1044fde9 SP |
451 | * branches. Enhanced IBRS protects firmware too, so, enable restricted |
452 | * speculation around firmware calls only when Enhanced IBRS isn't | |
453 | * supported. | |
454 | * | |
455 | * Use "mode" to check Enhanced IBRS instead of boot_cpu_has(), because | |
456 | * the user might select retpoline on the kernel command line and if | |
457 | * the CPU supports Enhanced IBRS, kernel might un-intentionally not | |
458 | * enable IBRS around firmware calls. | |
390b99c3 | 459 | */ |
1044fde9 | 460 | if (boot_cpu_has(X86_FEATURE_IBRS) && mode != SPECTRE_V2_IBRS_ENHANCED) { |
390b99c3 DW |
461 | setup_force_cpu_cap(X86_FEATURE_USE_IBRS_FW); |
462 | pr_info("Enabling Restricted Speculation for firmware calls\n"); | |
463 | } | |
7011f443 JK |
464 | |
465 | /* Enable STIBP if appropriate */ | |
466 | arch_smt_update(); | |
da285121 DW |
467 | } |
468 | ||
e63490c8 KRW |
469 | #undef pr_fmt |
470 | #define pr_fmt(fmt) "Speculative Store Bypass: " fmt | |
471 | ||
b5e6d77d | 472 | static enum ssb_mitigation ssb_mode __ro_after_init = SPEC_STORE_BYPASS_NONE; |
e63490c8 KRW |
473 | |
474 | /* The kernel command line selection */ | |
475 | enum ssb_mitigation_cmd { | |
476 | SPEC_STORE_BYPASS_CMD_NONE, | |
477 | SPEC_STORE_BYPASS_CMD_AUTO, | |
478 | SPEC_STORE_BYPASS_CMD_ON, | |
574dcf89 | 479 | SPEC_STORE_BYPASS_CMD_PRCTL, |
c7416003 | 480 | SPEC_STORE_BYPASS_CMD_SECCOMP, |
e63490c8 KRW |
481 | }; |
482 | ||
483 | static const char *ssb_strings[] = { | |
484 | [SPEC_STORE_BYPASS_NONE] = "Vulnerable", | |
574dcf89 | 485 | [SPEC_STORE_BYPASS_DISABLE] = "Mitigation: Speculative Store Bypass disabled", |
c7416003 KC |
486 | [SPEC_STORE_BYPASS_PRCTL] = "Mitigation: Speculative Store Bypass disabled via prctl", |
487 | [SPEC_STORE_BYPASS_SECCOMP] = "Mitigation: Speculative Store Bypass disabled via prctl and seccomp", | |
e63490c8 KRW |
488 | }; |
489 | ||
490 | static const struct { | |
491 | const char *option; | |
492 | enum ssb_mitigation_cmd cmd; | |
493 | } ssb_mitigation_options[] = { | |
c7416003 KC |
494 | { "auto", SPEC_STORE_BYPASS_CMD_AUTO }, /* Platform decides */ |
495 | { "on", SPEC_STORE_BYPASS_CMD_ON }, /* Disable Speculative Store Bypass */ | |
496 | { "off", SPEC_STORE_BYPASS_CMD_NONE }, /* Don't touch Speculative Store Bypass */ | |
497 | { "prctl", SPEC_STORE_BYPASS_CMD_PRCTL }, /* Disable Speculative Store Bypass via prctl */ | |
498 | { "seccomp", SPEC_STORE_BYPASS_CMD_SECCOMP }, /* Disable Speculative Store Bypass via prctl and seccomp */ | |
e63490c8 KRW |
499 | }; |
500 | ||
501 | static enum ssb_mitigation_cmd __init ssb_parse_cmdline(void) | |
502 | { | |
503 | enum ssb_mitigation_cmd cmd = SPEC_STORE_BYPASS_CMD_AUTO; | |
504 | char arg[20]; | |
505 | int ret, i; | |
506 | ||
507 | if (cmdline_find_option_bool(boot_command_line, "nospec_store_bypass_disable")) { | |
508 | return SPEC_STORE_BYPASS_CMD_NONE; | |
509 | } else { | |
510 | ret = cmdline_find_option(boot_command_line, "spec_store_bypass_disable", | |
511 | arg, sizeof(arg)); | |
512 | if (ret < 0) | |
513 | return SPEC_STORE_BYPASS_CMD_AUTO; | |
514 | ||
515 | for (i = 0; i < ARRAY_SIZE(ssb_mitigation_options); i++) { | |
516 | if (!match_option(arg, ret, ssb_mitigation_options[i].option)) | |
517 | continue; | |
518 | ||
519 | cmd = ssb_mitigation_options[i].cmd; | |
520 | break; | |
521 | } | |
522 | ||
523 | if (i >= ARRAY_SIZE(ssb_mitigation_options)) { | |
524 | pr_err("unknown option (%s). Switching to AUTO select\n", arg); | |
525 | return SPEC_STORE_BYPASS_CMD_AUTO; | |
526 | } | |
527 | } | |
528 | ||
529 | return cmd; | |
530 | } | |
531 | ||
dbe3009d | 532 | static enum ssb_mitigation __init __ssb_select_mitigation(void) |
e63490c8 KRW |
533 | { |
534 | enum ssb_mitigation mode = SPEC_STORE_BYPASS_NONE; | |
535 | enum ssb_mitigation_cmd cmd; | |
536 | ||
8fe36c9d | 537 | if (!boot_cpu_has(X86_FEATURE_SSBD)) |
e63490c8 KRW |
538 | return mode; |
539 | ||
540 | cmd = ssb_parse_cmdline(); | |
541 | if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS) && | |
542 | (cmd == SPEC_STORE_BYPASS_CMD_NONE || | |
543 | cmd == SPEC_STORE_BYPASS_CMD_AUTO)) | |
544 | return mode; | |
545 | ||
546 | switch (cmd) { | |
547 | case SPEC_STORE_BYPASS_CMD_AUTO: | |
c7416003 KC |
548 | case SPEC_STORE_BYPASS_CMD_SECCOMP: |
549 | /* | |
550 | * Choose prctl+seccomp as the default mode if seccomp is | |
551 | * enabled. | |
552 | */ | |
553 | if (IS_ENABLED(CONFIG_SECCOMP)) | |
554 | mode = SPEC_STORE_BYPASS_SECCOMP; | |
555 | else | |
556 | mode = SPEC_STORE_BYPASS_PRCTL; | |
574dcf89 | 557 | break; |
e63490c8 KRW |
558 | case SPEC_STORE_BYPASS_CMD_ON: |
559 | mode = SPEC_STORE_BYPASS_DISABLE; | |
560 | break; | |
574dcf89 TG |
561 | case SPEC_STORE_BYPASS_CMD_PRCTL: |
562 | mode = SPEC_STORE_BYPASS_PRCTL; | |
563 | break; | |
e63490c8 KRW |
564 | case SPEC_STORE_BYPASS_CMD_NONE: |
565 | break; | |
566 | } | |
567 | ||
23b9eab9 KRW |
568 | /* |
569 | * We have three CPU feature flags that are in play here: | |
570 | * - X86_BUG_SPEC_STORE_BYPASS - CPU is susceptible. | |
8fe36c9d | 571 | * - X86_FEATURE_SSBD - CPU is able to turn off speculative store bypass |
23b9eab9 KRW |
572 | * - X86_FEATURE_SPEC_STORE_BYPASS_DISABLE - engage the mitigation |
573 | */ | |
574dcf89 | 574 | if (mode == SPEC_STORE_BYPASS_DISABLE) { |
e63490c8 | 575 | setup_force_cpu_cap(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE); |
23b9eab9 | 576 | /* |
3b881627 KRW |
577 | * Intel uses the SPEC CTRL MSR Bit(2) for this, while AMD may |
578 | * use a completely different MSR and bit dependent on family. | |
23b9eab9 | 579 | */ |
5005c716 TL |
580 | if (!static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) && |
581 | !static_cpu_has(X86_FEATURE_AMD_SSBD)) { | |
733c54c9 | 582 | x86_amd_ssb_disable(); |
5005c716 | 583 | } else { |
8fe36c9d | 584 | x86_spec_ctrl_base |= SPEC_CTRL_SSBD; |
e5f984ed | 585 | x86_spec_ctrl_mask |= SPEC_CTRL_SSBD; |
208efa83 | 586 | wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); |
23b9eab9 KRW |
587 | } |
588 | } | |
589 | ||
e63490c8 KRW |
590 | return mode; |
591 | } | |
592 | ||
043d480e | 593 | static void ssb_select_mitigation(void) |
e63490c8 KRW |
594 | { |
595 | ssb_mode = __ssb_select_mitigation(); | |
596 | ||
597 | if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) | |
598 | pr_info("%s\n", ssb_strings[ssb_mode]); | |
599 | } | |
600 | ||
da285121 | 601 | #undef pr_fmt |
c7416003 | 602 | #define pr_fmt(fmt) "Speculation prctl: " fmt |
da285121 | 603 | |
199bfed2 | 604 | static int ssb_prctl_set(struct task_struct *task, unsigned long ctrl) |
574dcf89 | 605 | { |
733f4234 | 606 | bool update; |
574dcf89 | 607 | |
c7416003 KC |
608 | if (ssb_mode != SPEC_STORE_BYPASS_PRCTL && |
609 | ssb_mode != SPEC_STORE_BYPASS_SECCOMP) | |
574dcf89 TG |
610 | return -ENXIO; |
611 | ||
733f4234 TG |
612 | switch (ctrl) { |
613 | case PR_SPEC_ENABLE: | |
614 | /* If speculation is force disabled, enable is not allowed */ | |
615 | if (task_spec_ssb_force_disable(task)) | |
616 | return -EPERM; | |
617 | task_clear_spec_ssb_disable(task); | |
8fe36c9d | 618 | update = test_and_clear_tsk_thread_flag(task, TIF_SSBD); |
733f4234 TG |
619 | break; |
620 | case PR_SPEC_DISABLE: | |
621 | task_set_spec_ssb_disable(task); | |
8fe36c9d | 622 | update = !test_and_set_tsk_thread_flag(task, TIF_SSBD); |
733f4234 TG |
623 | break; |
624 | case PR_SPEC_FORCE_DISABLE: | |
625 | task_set_spec_ssb_disable(task); | |
626 | task_set_spec_ssb_force_disable(task); | |
8fe36c9d | 627 | update = !test_and_set_tsk_thread_flag(task, TIF_SSBD); |
733f4234 TG |
628 | break; |
629 | default: | |
630 | return -ERANGE; | |
631 | } | |
574dcf89 | 632 | |
199bfed2 KC |
633 | /* |
634 | * If being set on non-current task, delay setting the CPU | |
635 | * mitigation until it is next scheduled. | |
636 | */ | |
733f4234 | 637 | if (task == current && update) |
8a3ba093 | 638 | speculative_store_bypass_update_current(); |
574dcf89 TG |
639 | |
640 | return 0; | |
641 | } | |
642 | ||
5b38e244 TG |
643 | int arch_prctl_spec_ctrl_set(struct task_struct *task, unsigned long which, |
644 | unsigned long ctrl) | |
645 | { | |
646 | switch (which) { | |
647 | case PR_SPEC_STORE_BYPASS: | |
648 | return ssb_prctl_set(task, ctrl); | |
649 | default: | |
650 | return -ENODEV; | |
651 | } | |
652 | } | |
653 | ||
654 | #ifdef CONFIG_SECCOMP | |
655 | void arch_seccomp_spec_mitigate(struct task_struct *task) | |
656 | { | |
c7416003 KC |
657 | if (ssb_mode == SPEC_STORE_BYPASS_SECCOMP) |
658 | ssb_prctl_set(task, PR_SPEC_FORCE_DISABLE); | |
5b38e244 TG |
659 | } |
660 | #endif | |
661 | ||
199bfed2 | 662 | static int ssb_prctl_get(struct task_struct *task) |
574dcf89 TG |
663 | { |
664 | switch (ssb_mode) { | |
665 | case SPEC_STORE_BYPASS_DISABLE: | |
666 | return PR_SPEC_DISABLE; | |
c7416003 | 667 | case SPEC_STORE_BYPASS_SECCOMP: |
574dcf89 | 668 | case SPEC_STORE_BYPASS_PRCTL: |
733f4234 TG |
669 | if (task_spec_ssb_force_disable(task)) |
670 | return PR_SPEC_PRCTL | PR_SPEC_FORCE_DISABLE; | |
671 | if (task_spec_ssb_disable(task)) | |
574dcf89 TG |
672 | return PR_SPEC_PRCTL | PR_SPEC_DISABLE; |
673 | return PR_SPEC_PRCTL | PR_SPEC_ENABLE; | |
674 | default: | |
675 | if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) | |
676 | return PR_SPEC_ENABLE; | |
677 | return PR_SPEC_NOT_AFFECTED; | |
678 | } | |
679 | } | |
680 | ||
199bfed2 | 681 | int arch_prctl_spec_ctrl_get(struct task_struct *task, unsigned long which) |
574dcf89 TG |
682 | { |
683 | switch (which) { | |
684 | case PR_SPEC_STORE_BYPASS: | |
199bfed2 | 685 | return ssb_prctl_get(task); |
574dcf89 TG |
686 | default: |
687 | return -ENODEV; | |
688 | } | |
689 | } | |
690 | ||
23b9eab9 KRW |
691 | void x86_spec_ctrl_setup_ap(void) |
692 | { | |
50f9b919 | 693 | if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) |
208efa83 | 694 | wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); |
c37b94dd KRW |
695 | |
696 | if (ssb_mode == SPEC_STORE_BYPASS_DISABLE) | |
8fe36c9d | 697 | x86_amd_ssb_disable(); |
23b9eab9 KRW |
698 | } |
699 | ||
73ca9f47 KRW |
700 | #undef pr_fmt |
701 | #define pr_fmt(fmt) "L1TF: " fmt | |
b9cfedcd | 702 | |
24fcb53c JK |
703 | /* Default mitigation for L1TF-affected CPUs */ |
704 | enum l1tf_mitigations l1tf_mitigation __ro_after_init = L1TF_MITIGATION_FLUSH; | |
b9cfedcd | 705 | #if IS_ENABLED(CONFIG_KVM_INTEL) |
24fcb53c JK |
706 | EXPORT_SYMBOL_GPL(l1tf_mitigation); |
707 | ||
522c7bed | 708 | enum vmx_l1d_flush_state l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO; |
b9cfedcd TG |
709 | EXPORT_SYMBOL_GPL(l1tf_vmx_mitigation); |
710 | #endif | |
711 | ||
f1f016ed AK |
712 | /* |
713 | * These CPUs all support 44bits physical address space internally in the | |
714 | * cache but CPUID can report a smaller number of physical address bits. | |
715 | * | |
716 | * The L1TF mitigation uses the top most address bit for the inversion of | |
717 | * non present PTEs. When the installed memory reaches into the top most | |
718 | * address bit due to memory holes, which has been observed on machines | |
719 | * which report 36bits physical address bits and have 32G RAM installed, | |
720 | * then the mitigation range check in l1tf_select_mitigation() triggers. | |
721 | * This is a false positive because the mitigation is still possible due to | |
722 | * the fact that the cache uses 44bit internally. Use the cache bits | |
723 | * instead of the reported physical bits and adjust them on the affected | |
724 | * machines to 44bit if the reported bits are less than 44. | |
725 | */ | |
726 | static void override_cache_bits(struct cpuinfo_x86 *c) | |
727 | { | |
728 | if (c->x86 != 6) | |
729 | return; | |
730 | ||
731 | switch (c->x86_model) { | |
732 | case INTEL_FAM6_NEHALEM: | |
733 | case INTEL_FAM6_WESTMERE: | |
734 | case INTEL_FAM6_SANDYBRIDGE: | |
735 | case INTEL_FAM6_IVYBRIDGE: | |
736 | case INTEL_FAM6_HASWELL_CORE: | |
737 | case INTEL_FAM6_HASWELL_ULT: | |
738 | case INTEL_FAM6_HASWELL_GT3E: | |
739 | case INTEL_FAM6_BROADWELL_CORE: | |
740 | case INTEL_FAM6_BROADWELL_GT3E: | |
741 | case INTEL_FAM6_SKYLAKE_MOBILE: | |
742 | case INTEL_FAM6_SKYLAKE_DESKTOP: | |
743 | case INTEL_FAM6_KABYLAKE_MOBILE: | |
744 | case INTEL_FAM6_KABYLAKE_DESKTOP: | |
745 | if (c->x86_cache_bits < 44) | |
746 | c->x86_cache_bits = 44; | |
747 | break; | |
748 | } | |
749 | } | |
750 | ||
73ca9f47 KRW |
751 | static void __init l1tf_select_mitigation(void) |
752 | { | |
753 | u64 half_pa; | |
754 | ||
755 | if (!boot_cpu_has_bug(X86_BUG_L1TF)) | |
756 | return; | |
757 | ||
f1f016ed AK |
758 | override_cache_bits(&boot_cpu_data); |
759 | ||
24fcb53c JK |
760 | switch (l1tf_mitigation) { |
761 | case L1TF_MITIGATION_OFF: | |
762 | case L1TF_MITIGATION_FLUSH_NOWARN: | |
763 | case L1TF_MITIGATION_FLUSH: | |
764 | break; | |
765 | case L1TF_MITIGATION_FLUSH_NOSMT: | |
766 | case L1TF_MITIGATION_FULL: | |
767 | cpu_smt_disable(false); | |
768 | break; | |
769 | case L1TF_MITIGATION_FULL_FORCE: | |
770 | cpu_smt_disable(true); | |
771 | break; | |
772 | } | |
773 | ||
73ca9f47 KRW |
774 | #if CONFIG_PGTABLE_LEVELS == 2 |
775 | pr_warn("Kernel not compiled for PAE. No mitigation for L1TF\n"); | |
776 | return; | |
777 | #endif | |
778 | ||
73ca9f47 KRW |
779 | half_pa = (u64)l1tf_pfn_limit() << PAGE_SHIFT; |
780 | if (e820__mapped_any(half_pa, ULLONG_MAX - half_pa, E820_TYPE_RAM)) { | |
781 | pr_warn("System has more than MAX_PA/2 memory. L1TF mitigation not effective.\n"); | |
782 | return; | |
783 | } | |
784 | ||
785 | setup_force_cpu_cap(X86_FEATURE_L1TF_PTEINV); | |
786 | } | |
24fcb53c JK |
787 | |
788 | static int __init l1tf_cmdline(char *str) | |
789 | { | |
790 | if (!boot_cpu_has_bug(X86_BUG_L1TF)) | |
791 | return 0; | |
792 | ||
793 | if (!str) | |
794 | return -EINVAL; | |
795 | ||
796 | if (!strcmp(str, "off")) | |
797 | l1tf_mitigation = L1TF_MITIGATION_OFF; | |
798 | else if (!strcmp(str, "flush,nowarn")) | |
799 | l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOWARN; | |
800 | else if (!strcmp(str, "flush")) | |
801 | l1tf_mitigation = L1TF_MITIGATION_FLUSH; | |
802 | else if (!strcmp(str, "flush,nosmt")) | |
803 | l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOSMT; | |
804 | else if (!strcmp(str, "full")) | |
805 | l1tf_mitigation = L1TF_MITIGATION_FULL; | |
806 | else if (!strcmp(str, "full,force")) | |
807 | l1tf_mitigation = L1TF_MITIGATION_FULL_FORCE; | |
808 | ||
809 | return 0; | |
810 | } | |
811 | early_param("l1tf", l1tf_cmdline); | |
812 | ||
73ca9f47 KRW |
813 | #undef pr_fmt |
814 | ||
61dc0f55 | 815 | #ifdef CONFIG_SYSFS |
d2b8fc2d | 816 | |
b9cfedcd TG |
817 | #define L1TF_DEFAULT_MSG "Mitigation: PTE Inversion" |
818 | ||
819 | #if IS_ENABLED(CONFIG_KVM_INTEL) | |
820 | static const char *l1tf_vmx_states[] = { | |
1ead4979 TG |
821 | [VMENTER_L1D_FLUSH_AUTO] = "auto", |
822 | [VMENTER_L1D_FLUSH_NEVER] = "vulnerable", | |
823 | [VMENTER_L1D_FLUSH_COND] = "conditional cache flushes", | |
824 | [VMENTER_L1D_FLUSH_ALWAYS] = "cache flushes", | |
825 | [VMENTER_L1D_FLUSH_EPT_DISABLED] = "EPT disabled", | |
364a4311 | 826 | [VMENTER_L1D_FLUSH_NOT_REQUIRED] = "flush not necessary" |
b9cfedcd TG |
827 | }; |
828 | ||
829 | static ssize_t l1tf_show_state(char *buf) | |
830 | { | |
831 | if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO) | |
832 | return sprintf(buf, "%s\n", L1TF_DEFAULT_MSG); | |
833 | ||
3899f7b1 PB |
834 | if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_EPT_DISABLED || |
835 | (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER && | |
836 | cpu_smt_control == CPU_SMT_ENABLED)) | |
837 | return sprintf(buf, "%s; VMX: %s\n", L1TF_DEFAULT_MSG, | |
838 | l1tf_vmx_states[l1tf_vmx_mitigation]); | |
839 | ||
840 | return sprintf(buf, "%s; VMX: %s, SMT %s\n", L1TF_DEFAULT_MSG, | |
841 | l1tf_vmx_states[l1tf_vmx_mitigation], | |
842 | cpu_smt_control == CPU_SMT_ENABLED ? "vulnerable" : "disabled"); | |
b9cfedcd TG |
843 | } |
844 | #else | |
845 | static ssize_t l1tf_show_state(char *buf) | |
846 | { | |
847 | return sprintf(buf, "%s\n", L1TF_DEFAULT_MSG); | |
848 | } | |
849 | #endif | |
850 | ||
ace051d5 | 851 | static ssize_t cpu_show_common(struct device *dev, struct device_attribute *attr, |
043d480e | 852 | char *buf, unsigned int bug) |
61dc0f55 | 853 | { |
7011f443 JK |
854 | int ret; |
855 | ||
d2b8fc2d | 856 | if (!boot_cpu_has_bug(bug)) |
61dc0f55 | 857 | return sprintf(buf, "Not affected\n"); |
d2b8fc2d KRW |
858 | |
859 | switch (bug) { | |
860 | case X86_BUG_CPU_MELTDOWN: | |
861 | if (boot_cpu_has(X86_FEATURE_PTI)) | |
862 | return sprintf(buf, "Mitigation: PTI\n"); | |
863 | ||
864 | break; | |
865 | ||
866 | case X86_BUG_SPECTRE_V1: | |
867 | return sprintf(buf, "Mitigation: __user pointer sanitization\n"); | |
868 | ||
869 | case X86_BUG_SPECTRE_V2: | |
5e2fafd5 | 870 | ret = sprintf(buf, "%s%s%s%s%s%s\n", spectre_v2_strings[spectre_v2_enabled], |
d2b8fc2d KRW |
871 | boot_cpu_has(X86_FEATURE_USE_IBPB) ? ", IBPB" : "", |
872 | boot_cpu_has(X86_FEATURE_USE_IBRS_FW) ? ", IBRS_FW" : "", | |
7011f443 | 873 | (x86_spec_ctrl_base & SPEC_CTRL_STIBP) ? ", STIBP" : "", |
5e2fafd5 | 874 | boot_cpu_has(X86_FEATURE_RSB_CTXSW) ? ", RSB filling" : "", |
d2b8fc2d | 875 | spectre_v2_module_string()); |
7011f443 | 876 | return ret; |
d2b8fc2d | 877 | |
e63490c8 KRW |
878 | case X86_BUG_SPEC_STORE_BYPASS: |
879 | return sprintf(buf, "%s\n", ssb_strings[ssb_mode]); | |
880 | ||
05516ad8 AK |
881 | case X86_BUG_L1TF: |
882 | if (boot_cpu_has(X86_FEATURE_L1TF_PTEINV)) | |
b9cfedcd | 883 | return l1tf_show_state(buf); |
05516ad8 | 884 | break; |
d2b8fc2d KRW |
885 | default: |
886 | break; | |
887 | } | |
888 | ||
61dc0f55 TG |
889 | return sprintf(buf, "Vulnerable\n"); |
890 | } | |
891 | ||
d2b8fc2d KRW |
892 | ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, char *buf) |
893 | { | |
894 | return cpu_show_common(dev, attr, buf, X86_BUG_CPU_MELTDOWN); | |
895 | } | |
896 | ||
713f1b95 | 897 | ssize_t cpu_show_spectre_v1(struct device *dev, struct device_attribute *attr, char *buf) |
61dc0f55 | 898 | { |
d2b8fc2d | 899 | return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V1); |
61dc0f55 TG |
900 | } |
901 | ||
713f1b95 | 902 | ssize_t cpu_show_spectre_v2(struct device *dev, struct device_attribute *attr, char *buf) |
61dc0f55 | 903 | { |
d2b8fc2d | 904 | return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V2); |
61dc0f55 | 905 | } |
d7de9182 KRW |
906 | |
907 | ssize_t cpu_show_spec_store_bypass(struct device *dev, struct device_attribute *attr, char *buf) | |
908 | { | |
909 | return cpu_show_common(dev, attr, buf, X86_BUG_SPEC_STORE_BYPASS); | |
910 | } | |
05516ad8 AK |
911 | |
912 | ssize_t cpu_show_l1tf(struct device *dev, struct device_attribute *attr, char *buf) | |
913 | { | |
914 | return cpu_show_common(dev, attr, buf, X86_BUG_L1TF); | |
915 | } | |
61dc0f55 | 916 | #endif |