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Commit | Line | Data |
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f0fc4aff | 1 | #include <linux/bootmem.h> |
9766cdbc | 2 | #include <linux/linkage.h> |
f0fc4aff | 3 | #include <linux/bitops.h> |
9766cdbc | 4 | #include <linux/kernel.h> |
186f4360 | 5 | #include <linux/export.h> |
9766cdbc JSR |
6 | #include <linux/percpu.h> |
7 | #include <linux/string.h> | |
ee098e1a | 8 | #include <linux/ctype.h> |
1da177e4 | 9 | #include <linux/delay.h> |
68e21be2 | 10 | #include <linux/sched/mm.h> |
e6017571 | 11 | #include <linux/sched/clock.h> |
9164bb4a | 12 | #include <linux/sched/task.h> |
9766cdbc | 13 | #include <linux/init.h> |
0f46efeb | 14 | #include <linux/kprobes.h> |
9766cdbc | 15 | #include <linux/kgdb.h> |
1da177e4 | 16 | #include <linux/smp.h> |
9766cdbc | 17 | #include <linux/io.h> |
b51ef52d | 18 | #include <linux/syscore_ops.h> |
9766cdbc JSR |
19 | |
20 | #include <asm/stackprotector.h> | |
cdd6c482 | 21 | #include <asm/perf_event.h> |
1da177e4 | 22 | #include <asm/mmu_context.h> |
49d859d7 | 23 | #include <asm/archrandom.h> |
9766cdbc JSR |
24 | #include <asm/hypervisor.h> |
25 | #include <asm/processor.h> | |
1e02ce4c | 26 | #include <asm/tlbflush.h> |
f649e938 | 27 | #include <asm/debugreg.h> |
9766cdbc | 28 | #include <asm/sections.h> |
f40c3300 | 29 | #include <asm/vsyscall.h> |
8bdbd962 AC |
30 | #include <linux/topology.h> |
31 | #include <linux/cpumask.h> | |
9766cdbc | 32 | #include <asm/pgtable.h> |
60063497 | 33 | #include <linux/atomic.h> |
9766cdbc JSR |
34 | #include <asm/proto.h> |
35 | #include <asm/setup.h> | |
36 | #include <asm/apic.h> | |
37 | #include <asm/desc.h> | |
78f7f1e5 | 38 | #include <asm/fpu/internal.h> |
27b07da7 | 39 | #include <asm/mtrr.h> |
0274f955 | 40 | #include <asm/hwcap2.h> |
8bdbd962 | 41 | #include <linux/numa.h> |
9766cdbc | 42 | #include <asm/asm.h> |
0f6ff2bc | 43 | #include <asm/bugs.h> |
9766cdbc | 44 | #include <asm/cpu.h> |
a03a3e28 | 45 | #include <asm/mce.h> |
9766cdbc | 46 | #include <asm/msr.h> |
8d4a4300 | 47 | #include <asm/pat.h> |
d288e1cf FY |
48 | #include <asm/microcode.h> |
49 | #include <asm/microcode_intel.h> | |
6b593f57 DW |
50 | #include <asm/intel-family.h> |
51 | #include <asm/cpu_device_id.h> | |
e641f5f5 IM |
52 | |
53 | #ifdef CONFIG_X86_LOCAL_APIC | |
bdbcdd48 | 54 | #include <asm/uv/uv.h> |
1da177e4 LT |
55 | #endif |
56 | ||
57 | #include "cpu.h" | |
58 | ||
0274f955 GA |
59 | u32 elf_hwcap2 __read_mostly; |
60 | ||
c2d1cec1 | 61 | /* all of these masks are initialized in setup_cpu_local_masks() */ |
c2d1cec1 | 62 | cpumask_var_t cpu_initialized_mask; |
9766cdbc JSR |
63 | cpumask_var_t cpu_callout_mask; |
64 | cpumask_var_t cpu_callin_mask; | |
c2d1cec1 MT |
65 | |
66 | /* representing cpus for which sibling maps can be computed */ | |
67 | cpumask_var_t cpu_sibling_setup_mask; | |
68 | ||
2f2f52ba | 69 | /* correctly size the local cpu masks */ |
4369f1fb | 70 | void __init setup_cpu_local_masks(void) |
2f2f52ba BG |
71 | { |
72 | alloc_bootmem_cpumask_var(&cpu_initialized_mask); | |
73 | alloc_bootmem_cpumask_var(&cpu_callin_mask); | |
74 | alloc_bootmem_cpumask_var(&cpu_callout_mask); | |
75 | alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask); | |
76 | } | |
77 | ||
148f9bb8 | 78 | static void default_init(struct cpuinfo_x86 *c) |
e8055139 OZ |
79 | { |
80 | #ifdef CONFIG_X86_64 | |
27c13ece | 81 | cpu_detect_cache_sizes(c); |
e8055139 OZ |
82 | #else |
83 | /* Not much we can do here... */ | |
84 | /* Check if at least it has cpuid */ | |
85 | if (c->cpuid_level == -1) { | |
86 | /* No cpuid. It must be an ancient CPU */ | |
87 | if (c->x86 == 4) | |
88 | strcpy(c->x86_model_id, "486"); | |
89 | else if (c->x86 == 3) | |
90 | strcpy(c->x86_model_id, "386"); | |
91 | } | |
92 | #endif | |
93 | } | |
94 | ||
148f9bb8 | 95 | static const struct cpu_dev default_cpu = { |
e8055139 OZ |
96 | .c_init = default_init, |
97 | .c_vendor = "Unknown", | |
98 | .c_x86_vendor = X86_VENDOR_UNKNOWN, | |
99 | }; | |
100 | ||
148f9bb8 | 101 | static const struct cpu_dev *this_cpu = &default_cpu; |
0a488a53 | 102 | |
06deef89 | 103 | DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = { |
950ad7ff | 104 | #ifdef CONFIG_X86_64 |
06deef89 BG |
105 | /* |
106 | * We need valid kernel segments for data and code in long mode too | |
107 | * IRET will check the segment types kkeil 2000/10/28 | |
108 | * Also sysret mandates a special GDT layout | |
109 | * | |
9766cdbc | 110 | * TLS descriptors are currently at a different place compared to i386. |
06deef89 BG |
111 | * Hopefully nobody expects them at a fixed place (Wine?) |
112 | */ | |
1e5de182 AM |
113 | [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff), |
114 | [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff), | |
115 | [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff), | |
116 | [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff), | |
117 | [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff), | |
118 | [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff), | |
950ad7ff | 119 | #else |
1e5de182 AM |
120 | [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff), |
121 | [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), | |
122 | [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff), | |
123 | [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff), | |
bf504672 RR |
124 | /* |
125 | * Segments used for calling PnP BIOS have byte granularity. | |
126 | * They code segments and data segments have fixed 64k limits, | |
127 | * the transfer segment sizes are set at run time. | |
128 | */ | |
6842ef0e | 129 | /* 32-bit code */ |
1e5de182 | 130 | [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), |
6842ef0e | 131 | /* 16-bit code */ |
1e5de182 | 132 | [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), |
6842ef0e | 133 | /* 16-bit data */ |
1e5de182 | 134 | [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(0x0092, 0, 0xffff), |
6842ef0e | 135 | /* 16-bit data */ |
1e5de182 | 136 | [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(0x0092, 0, 0), |
6842ef0e | 137 | /* 16-bit data */ |
1e5de182 | 138 | [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(0x0092, 0, 0), |
bf504672 RR |
139 | /* |
140 | * The APM segments have byte granularity and their bases | |
141 | * are set at run time. All have 64k limits. | |
142 | */ | |
6842ef0e | 143 | /* 32-bit code */ |
1e5de182 | 144 | [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), |
bf504672 | 145 | /* 16-bit code */ |
1e5de182 | 146 | [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), |
6842ef0e | 147 | /* data */ |
72c4d853 | 148 | [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff), |
bf504672 | 149 | |
1e5de182 AM |
150 | [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), |
151 | [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), | |
60a5317f | 152 | GDT_STACK_CANARY_INIT |
950ad7ff | 153 | #endif |
06deef89 | 154 | } }; |
7a61d35d | 155 | EXPORT_PER_CPU_SYMBOL_GPL(gdt_page); |
ae1ee11b | 156 | |
8c3641e9 | 157 | static int __init x86_mpx_setup(char *s) |
0c752a93 | 158 | { |
8c3641e9 | 159 | /* require an exact match without trailing characters */ |
2cd3949f DH |
160 | if (strlen(s)) |
161 | return 0; | |
0c752a93 | 162 | |
8c3641e9 DH |
163 | /* do not emit a message if the feature is not present */ |
164 | if (!boot_cpu_has(X86_FEATURE_MPX)) | |
165 | return 1; | |
6bad06b7 | 166 | |
8c3641e9 DH |
167 | setup_clear_cpu_cap(X86_FEATURE_MPX); |
168 | pr_info("nompx: Intel Memory Protection Extensions (MPX) disabled\n"); | |
b6f42a4a FY |
169 | return 1; |
170 | } | |
8c3641e9 | 171 | __setup("nompx", x86_mpx_setup); |
b6f42a4a | 172 | |
62d3a636 | 173 | #ifdef CONFIG_X86_64 |
0e6a37a4 | 174 | static int __init x86_nopcid_setup(char *s) |
62d3a636 | 175 | { |
0e6a37a4 AL |
176 | /* nopcid doesn't accept parameters */ |
177 | if (s) | |
178 | return -EINVAL; | |
62d3a636 AL |
179 | |
180 | /* do not emit a message if the feature is not present */ | |
181 | if (!boot_cpu_has(X86_FEATURE_PCID)) | |
0e6a37a4 | 182 | return 0; |
62d3a636 AL |
183 | |
184 | setup_clear_cpu_cap(X86_FEATURE_PCID); | |
185 | pr_info("nopcid: PCID feature disabled\n"); | |
0e6a37a4 | 186 | return 0; |
62d3a636 | 187 | } |
0e6a37a4 | 188 | early_param("nopcid", x86_nopcid_setup); |
62d3a636 AL |
189 | #endif |
190 | ||
d12a72b8 AL |
191 | static int __init x86_noinvpcid_setup(char *s) |
192 | { | |
193 | /* noinvpcid doesn't accept parameters */ | |
194 | if (s) | |
195 | return -EINVAL; | |
196 | ||
197 | /* do not emit a message if the feature is not present */ | |
198 | if (!boot_cpu_has(X86_FEATURE_INVPCID)) | |
199 | return 0; | |
200 | ||
201 | setup_clear_cpu_cap(X86_FEATURE_INVPCID); | |
202 | pr_info("noinvpcid: INVPCID feature disabled\n"); | |
203 | return 0; | |
204 | } | |
205 | early_param("noinvpcid", x86_noinvpcid_setup); | |
206 | ||
ba51dced | 207 | #ifdef CONFIG_X86_32 |
148f9bb8 PG |
208 | static int cachesize_override = -1; |
209 | static int disable_x86_serial_nr = 1; | |
1da177e4 | 210 | |
0a488a53 YL |
211 | static int __init cachesize_setup(char *str) |
212 | { | |
213 | get_option(&str, &cachesize_override); | |
214 | return 1; | |
215 | } | |
216 | __setup("cachesize=", cachesize_setup); | |
217 | ||
0a488a53 YL |
218 | static int __init x86_sep_setup(char *s) |
219 | { | |
220 | setup_clear_cpu_cap(X86_FEATURE_SEP); | |
221 | return 1; | |
222 | } | |
223 | __setup("nosep", x86_sep_setup); | |
224 | ||
225 | /* Standard macro to see if a specific flag is changeable */ | |
226 | static inline int flag_is_changeable_p(u32 flag) | |
227 | { | |
228 | u32 f1, f2; | |
229 | ||
94f6bac1 KH |
230 | /* |
231 | * Cyrix and IDT cpus allow disabling of CPUID | |
232 | * so the code below may return different results | |
233 | * when it is executed before and after enabling | |
234 | * the CPUID. Add "volatile" to not allow gcc to | |
235 | * optimize the subsequent calls to this function. | |
236 | */ | |
0f3fa48a IM |
237 | asm volatile ("pushfl \n\t" |
238 | "pushfl \n\t" | |
239 | "popl %0 \n\t" | |
240 | "movl %0, %1 \n\t" | |
241 | "xorl %2, %0 \n\t" | |
242 | "pushl %0 \n\t" | |
243 | "popfl \n\t" | |
244 | "pushfl \n\t" | |
245 | "popl %0 \n\t" | |
246 | "popfl \n\t" | |
247 | ||
94f6bac1 KH |
248 | : "=&r" (f1), "=&r" (f2) |
249 | : "ir" (flag)); | |
0a488a53 YL |
250 | |
251 | return ((f1^f2) & flag) != 0; | |
252 | } | |
253 | ||
254 | /* Probe for the CPUID instruction */ | |
148f9bb8 | 255 | int have_cpuid_p(void) |
0a488a53 YL |
256 | { |
257 | return flag_is_changeable_p(X86_EFLAGS_ID); | |
258 | } | |
259 | ||
148f9bb8 | 260 | static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) |
0a488a53 | 261 | { |
0f3fa48a IM |
262 | unsigned long lo, hi; |
263 | ||
264 | if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr) | |
265 | return; | |
266 | ||
267 | /* Disable processor serial number: */ | |
268 | ||
269 | rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi); | |
270 | lo |= 0x200000; | |
271 | wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi); | |
272 | ||
1b74dde7 | 273 | pr_notice("CPU serial number disabled.\n"); |
0f3fa48a IM |
274 | clear_cpu_cap(c, X86_FEATURE_PN); |
275 | ||
276 | /* Disabling the serial number may affect the cpuid level */ | |
277 | c->cpuid_level = cpuid_eax(0); | |
0a488a53 YL |
278 | } |
279 | ||
280 | static int __init x86_serial_nr_setup(char *s) | |
281 | { | |
282 | disable_x86_serial_nr = 0; | |
283 | return 1; | |
284 | } | |
285 | __setup("serialnumber", x86_serial_nr_setup); | |
ba51dced | 286 | #else |
102bbe3a YL |
287 | static inline int flag_is_changeable_p(u32 flag) |
288 | { | |
289 | return 1; | |
290 | } | |
102bbe3a YL |
291 | static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) |
292 | { | |
293 | } | |
ba51dced | 294 | #endif |
0a488a53 | 295 | |
de5397ad FY |
296 | static __init int setup_disable_smep(char *arg) |
297 | { | |
b2cc2a07 | 298 | setup_clear_cpu_cap(X86_FEATURE_SMEP); |
0f6ff2bc DH |
299 | /* Check for things that depend on SMEP being enabled: */ |
300 | check_mpx_erratum(&boot_cpu_data); | |
de5397ad FY |
301 | return 1; |
302 | } | |
303 | __setup("nosmep", setup_disable_smep); | |
304 | ||
b2cc2a07 | 305 | static __always_inline void setup_smep(struct cpuinfo_x86 *c) |
de5397ad | 306 | { |
b2cc2a07 | 307 | if (cpu_has(c, X86_FEATURE_SMEP)) |
375074cc | 308 | cr4_set_bits(X86_CR4_SMEP); |
de5397ad FY |
309 | } |
310 | ||
52b6179a PA |
311 | static __init int setup_disable_smap(char *arg) |
312 | { | |
b2cc2a07 | 313 | setup_clear_cpu_cap(X86_FEATURE_SMAP); |
52b6179a PA |
314 | return 1; |
315 | } | |
316 | __setup("nosmap", setup_disable_smap); | |
317 | ||
b2cc2a07 PA |
318 | static __always_inline void setup_smap(struct cpuinfo_x86 *c) |
319 | { | |
581b7f15 | 320 | unsigned long eflags = native_save_fl(); |
b2cc2a07 PA |
321 | |
322 | /* This should have been cleared long ago */ | |
b2cc2a07 PA |
323 | BUG_ON(eflags & X86_EFLAGS_AC); |
324 | ||
03bbd596 PA |
325 | if (cpu_has(c, X86_FEATURE_SMAP)) { |
326 | #ifdef CONFIG_X86_SMAP | |
375074cc | 327 | cr4_set_bits(X86_CR4_SMAP); |
03bbd596 | 328 | #else |
375074cc | 329 | cr4_clear_bits(X86_CR4_SMAP); |
03bbd596 PA |
330 | #endif |
331 | } | |
de5397ad FY |
332 | } |
333 | ||
06976945 DH |
334 | /* |
335 | * Protection Keys are not available in 32-bit mode. | |
336 | */ | |
337 | static bool pku_disabled; | |
338 | ||
339 | static __always_inline void setup_pku(struct cpuinfo_x86 *c) | |
340 | { | |
e8df1a95 DH |
341 | /* check the boot processor, plus compile options for PKU: */ |
342 | if (!cpu_feature_enabled(X86_FEATURE_PKU)) | |
343 | return; | |
344 | /* checks the actual processor's cpuid bits: */ | |
06976945 DH |
345 | if (!cpu_has(c, X86_FEATURE_PKU)) |
346 | return; | |
347 | if (pku_disabled) | |
348 | return; | |
349 | ||
350 | cr4_set_bits(X86_CR4_PKE); | |
351 | /* | |
352 | * Seting X86_CR4_PKE will cause the X86_FEATURE_OSPKE | |
353 | * cpuid bit to be set. We need to ensure that we | |
354 | * update that bit in this CPU's "cpu_info". | |
355 | */ | |
356 | get_cpu_cap(c); | |
357 | } | |
358 | ||
359 | #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS | |
360 | static __init int setup_disable_pku(char *arg) | |
361 | { | |
362 | /* | |
363 | * Do not clear the X86_FEATURE_PKU bit. All of the | |
364 | * runtime checks are against OSPKE so clearing the | |
365 | * bit does nothing. | |
366 | * | |
367 | * This way, we will see "pku" in cpuinfo, but not | |
368 | * "ospke", which is exactly what we want. It shows | |
369 | * that the CPU has PKU, but the OS has not enabled it. | |
370 | * This happens to be exactly how a system would look | |
371 | * if we disabled the config option. | |
372 | */ | |
373 | pr_info("x86: 'nopku' specified, disabling Memory Protection Keys\n"); | |
374 | pku_disabled = true; | |
375 | return 1; | |
376 | } | |
377 | __setup("nopku", setup_disable_pku); | |
378 | #endif /* CONFIG_X86_64 */ | |
379 | ||
b38b0665 PA |
380 | /* |
381 | * Some CPU features depend on higher CPUID levels, which may not always | |
382 | * be available due to CPUID level capping or broken virtualization | |
383 | * software. Add those features to this table to auto-disable them. | |
384 | */ | |
385 | struct cpuid_dependent_feature { | |
386 | u32 feature; | |
387 | u32 level; | |
388 | }; | |
0f3fa48a | 389 | |
148f9bb8 | 390 | static const struct cpuid_dependent_feature |
b38b0665 PA |
391 | cpuid_dependent_features[] = { |
392 | { X86_FEATURE_MWAIT, 0x00000005 }, | |
393 | { X86_FEATURE_DCA, 0x00000009 }, | |
394 | { X86_FEATURE_XSAVE, 0x0000000d }, | |
395 | { 0, 0 } | |
396 | }; | |
397 | ||
148f9bb8 | 398 | static void filter_cpuid_features(struct cpuinfo_x86 *c, bool warn) |
b38b0665 PA |
399 | { |
400 | const struct cpuid_dependent_feature *df; | |
9766cdbc | 401 | |
b38b0665 | 402 | for (df = cpuid_dependent_features; df->feature; df++) { |
0f3fa48a IM |
403 | |
404 | if (!cpu_has(c, df->feature)) | |
405 | continue; | |
b38b0665 PA |
406 | /* |
407 | * Note: cpuid_level is set to -1 if unavailable, but | |
408 | * extended_extended_level is set to 0 if unavailable | |
409 | * and the legitimate extended levels are all negative | |
410 | * when signed; hence the weird messing around with | |
411 | * signs here... | |
412 | */ | |
0f3fa48a | 413 | if (!((s32)df->level < 0 ? |
f6db44df | 414 | (u32)df->level > (u32)c->extended_cpuid_level : |
0f3fa48a IM |
415 | (s32)df->level > (s32)c->cpuid_level)) |
416 | continue; | |
417 | ||
418 | clear_cpu_cap(c, df->feature); | |
419 | if (!warn) | |
420 | continue; | |
421 | ||
1b74dde7 CY |
422 | pr_warn("CPU: CPU feature " X86_CAP_FMT " disabled, no CPUID level 0x%x\n", |
423 | x86_cap_flag(df->feature), df->level); | |
b38b0665 | 424 | } |
f6db44df | 425 | } |
b38b0665 | 426 | |
102bbe3a YL |
427 | /* |
428 | * Naming convention should be: <Name> [(<Codename>)] | |
429 | * This table only is used unless init_<vendor>() below doesn't set it; | |
0f3fa48a IM |
430 | * in particular, if CPUID levels 0x80000002..4 are supported, this |
431 | * isn't used | |
102bbe3a YL |
432 | */ |
433 | ||
434 | /* Look up CPU names by table lookup. */ | |
148f9bb8 | 435 | static const char *table_lookup_model(struct cpuinfo_x86 *c) |
102bbe3a | 436 | { |
09dc68d9 JB |
437 | #ifdef CONFIG_X86_32 |
438 | const struct legacy_cpu_model_info *info; | |
102bbe3a YL |
439 | |
440 | if (c->x86_model >= 16) | |
441 | return NULL; /* Range check */ | |
442 | ||
443 | if (!this_cpu) | |
444 | return NULL; | |
445 | ||
09dc68d9 | 446 | info = this_cpu->legacy_models; |
102bbe3a | 447 | |
09dc68d9 | 448 | while (info->family) { |
102bbe3a YL |
449 | if (info->family == c->x86) |
450 | return info->model_names[c->x86_model]; | |
451 | info++; | |
452 | } | |
09dc68d9 | 453 | #endif |
102bbe3a YL |
454 | return NULL; /* Not found */ |
455 | } | |
456 | ||
aab40a66 TG |
457 | __u32 cpu_caps_cleared[NCAPINTS + NBUGINTS]; |
458 | __u32 cpu_caps_set[NCAPINTS + NBUGINTS]; | |
7d851c8d | 459 | |
11e3a840 JF |
460 | void load_percpu_segment(int cpu) |
461 | { | |
462 | #ifdef CONFIG_X86_32 | |
463 | loadsegment(fs, __KERNEL_PERCPU); | |
464 | #else | |
45e876f7 | 465 | __loadsegment_simple(gs, 0); |
11e3a840 JF |
466 | wrmsrl(MSR_GS_BASE, (unsigned long)per_cpu(irq_stack_union.gs_base, cpu)); |
467 | #endif | |
60a5317f | 468 | load_stack_canary_segment(); |
11e3a840 JF |
469 | } |
470 | ||
475b37e7 AL |
471 | #ifdef CONFIG_X86_32 |
472 | /* The 32-bit entry code needs to find cpu_entry_area. */ | |
473 | DEFINE_PER_CPU(struct cpu_entry_area *, cpu_entry_area); | |
474 | #endif | |
475 | ||
88e72777 AL |
476 | #ifdef CONFIG_X86_64 |
477 | /* | |
478 | * Special IST stacks which the CPU switches to when it calls | |
479 | * an IST-marked descriptor entry. Up to 7 stacks (hardware | |
480 | * limit), all of them are 4K, except the debug stack which | |
481 | * is 8K. | |
482 | */ | |
483 | static const unsigned int exception_stack_sizes[N_EXCEPTION_STACKS] = { | |
484 | [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STKSZ, | |
485 | [DEBUG_STACK - 1] = DEBUG_STKSZ | |
486 | }; | |
45fc8757 | 487 | #endif |
69218e47 | 488 | |
45fc8757 TG |
489 | /* Load the original GDT from the per-cpu structure */ |
490 | void load_direct_gdt(int cpu) | |
491 | { | |
492 | struct desc_ptr gdt_descr; | |
493 | ||
494 | gdt_descr.address = (long)get_cpu_gdt_rw(cpu); | |
495 | gdt_descr.size = GDT_SIZE - 1; | |
496 | load_gdt(&gdt_descr); | |
497 | } | |
498 | EXPORT_SYMBOL_GPL(load_direct_gdt); | |
499 | ||
69218e47 TG |
500 | /* Load a fixmap remapping of the per-cpu GDT */ |
501 | void load_fixmap_gdt(int cpu) | |
502 | { | |
503 | struct desc_ptr gdt_descr; | |
504 | ||
505 | gdt_descr.address = (long)get_cpu_gdt_ro(cpu); | |
506 | gdt_descr.size = GDT_SIZE - 1; | |
507 | load_gdt(&gdt_descr); | |
508 | } | |
45fc8757 | 509 | EXPORT_SYMBOL_GPL(load_fixmap_gdt); |
69218e47 | 510 | |
0f3fa48a IM |
511 | /* |
512 | * Current gdt points %fs at the "master" per-cpu area: after this, | |
513 | * it's on the real one. | |
514 | */ | |
552be871 | 515 | void switch_to_new_gdt(int cpu) |
9d31d35b | 516 | { |
45fc8757 TG |
517 | /* Load the original GDT */ |
518 | load_direct_gdt(cpu); | |
2697fbd5 | 519 | /* Reload the per-cpu base */ |
11e3a840 | 520 | load_percpu_segment(cpu); |
9d31d35b YL |
521 | } |
522 | ||
148f9bb8 | 523 | static const struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {}; |
1da177e4 | 524 | |
148f9bb8 | 525 | static void get_model_name(struct cpuinfo_x86 *c) |
1da177e4 LT |
526 | { |
527 | unsigned int *v; | |
ee098e1a | 528 | char *p, *q, *s; |
1da177e4 | 529 | |
3da99c97 | 530 | if (c->extended_cpuid_level < 0x80000004) |
1b05d60d | 531 | return; |
1da177e4 | 532 | |
0f3fa48a | 533 | v = (unsigned int *)c->x86_model_id; |
1da177e4 LT |
534 | cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); |
535 | cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); | |
536 | cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); | |
537 | c->x86_model_id[48] = 0; | |
538 | ||
ee098e1a BP |
539 | /* Trim whitespace */ |
540 | p = q = s = &c->x86_model_id[0]; | |
541 | ||
542 | while (*p == ' ') | |
543 | p++; | |
544 | ||
545 | while (*p) { | |
546 | /* Note the last non-whitespace index */ | |
547 | if (!isspace(*p)) | |
548 | s = q; | |
549 | ||
550 | *q++ = *p++; | |
551 | } | |
552 | ||
553 | *(s + 1) = '\0'; | |
1da177e4 LT |
554 | } |
555 | ||
148f9bb8 | 556 | void cpu_detect_cache_sizes(struct cpuinfo_x86 *c) |
1da177e4 | 557 | { |
9d31d35b | 558 | unsigned int n, dummy, ebx, ecx, edx, l2size; |
1da177e4 | 559 | |
3da99c97 | 560 | n = c->extended_cpuid_level; |
1da177e4 LT |
561 | |
562 | if (n >= 0x80000005) { | |
9d31d35b | 563 | cpuid(0x80000005, &dummy, &ebx, &ecx, &edx); |
9d31d35b | 564 | c->x86_cache_size = (ecx>>24) + (edx>>24); |
140fc727 YL |
565 | #ifdef CONFIG_X86_64 |
566 | /* On K8 L1 TLB is inclusive, so don't count it */ | |
567 | c->x86_tlbsize = 0; | |
568 | #endif | |
1da177e4 LT |
569 | } |
570 | ||
571 | if (n < 0x80000006) /* Some chips just has a large L1. */ | |
572 | return; | |
573 | ||
0a488a53 | 574 | cpuid(0x80000006, &dummy, &ebx, &ecx, &edx); |
1da177e4 | 575 | l2size = ecx >> 16; |
34048c9e | 576 | |
140fc727 YL |
577 | #ifdef CONFIG_X86_64 |
578 | c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff); | |
579 | #else | |
1da177e4 | 580 | /* do processor-specific cache resizing */ |
09dc68d9 JB |
581 | if (this_cpu->legacy_cache_size) |
582 | l2size = this_cpu->legacy_cache_size(c, l2size); | |
1da177e4 LT |
583 | |
584 | /* Allow user to override all this if necessary. */ | |
585 | if (cachesize_override != -1) | |
586 | l2size = cachesize_override; | |
587 | ||
34048c9e | 588 | if (l2size == 0) |
1da177e4 | 589 | return; /* Again, no L2 cache is possible */ |
140fc727 | 590 | #endif |
1da177e4 LT |
591 | |
592 | c->x86_cache_size = l2size; | |
1da177e4 LT |
593 | } |
594 | ||
e0ba94f1 AS |
595 | u16 __read_mostly tlb_lli_4k[NR_INFO]; |
596 | u16 __read_mostly tlb_lli_2m[NR_INFO]; | |
597 | u16 __read_mostly tlb_lli_4m[NR_INFO]; | |
598 | u16 __read_mostly tlb_lld_4k[NR_INFO]; | |
599 | u16 __read_mostly tlb_lld_2m[NR_INFO]; | |
600 | u16 __read_mostly tlb_lld_4m[NR_INFO]; | |
dd360393 | 601 | u16 __read_mostly tlb_lld_1g[NR_INFO]; |
e0ba94f1 | 602 | |
f94fe119 | 603 | static void cpu_detect_tlb(struct cpuinfo_x86 *c) |
e0ba94f1 AS |
604 | { |
605 | if (this_cpu->c_detect_tlb) | |
606 | this_cpu->c_detect_tlb(c); | |
607 | ||
f94fe119 | 608 | pr_info("Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n", |
e0ba94f1 | 609 | tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES], |
f94fe119 SH |
610 | tlb_lli_4m[ENTRIES]); |
611 | ||
612 | pr_info("Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n", | |
613 | tlb_lld_4k[ENTRIES], tlb_lld_2m[ENTRIES], | |
614 | tlb_lld_4m[ENTRIES], tlb_lld_1g[ENTRIES]); | |
e0ba94f1 AS |
615 | } |
616 | ||
148f9bb8 | 617 | void detect_ht(struct cpuinfo_x86 *c) |
1da177e4 | 618 | { |
c8e56d20 | 619 | #ifdef CONFIG_SMP |
0a488a53 YL |
620 | u32 eax, ebx, ecx, edx; |
621 | int index_msb, core_bits; | |
2eaad1fd | 622 | static bool printed; |
1da177e4 | 623 | |
0a488a53 | 624 | if (!cpu_has(c, X86_FEATURE_HT)) |
9d31d35b | 625 | return; |
1da177e4 | 626 | |
0a488a53 YL |
627 | if (cpu_has(c, X86_FEATURE_CMP_LEGACY)) |
628 | goto out; | |
1da177e4 | 629 | |
1cd78776 YL |
630 | if (cpu_has(c, X86_FEATURE_XTOPOLOGY)) |
631 | return; | |
1da177e4 | 632 | |
0a488a53 | 633 | cpuid(1, &eax, &ebx, &ecx, &edx); |
1da177e4 | 634 | |
9d31d35b YL |
635 | smp_num_siblings = (ebx & 0xff0000) >> 16; |
636 | ||
637 | if (smp_num_siblings == 1) { | |
1b74dde7 | 638 | pr_info_once("CPU0: Hyper-Threading is disabled\n"); |
0f3fa48a IM |
639 | goto out; |
640 | } | |
9d31d35b | 641 | |
0f3fa48a IM |
642 | if (smp_num_siblings <= 1) |
643 | goto out; | |
9d31d35b | 644 | |
0f3fa48a IM |
645 | index_msb = get_count_order(smp_num_siblings); |
646 | c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb); | |
9d31d35b | 647 | |
0f3fa48a | 648 | smp_num_siblings = smp_num_siblings / c->x86_max_cores; |
9d31d35b | 649 | |
0f3fa48a | 650 | index_msb = get_count_order(smp_num_siblings); |
9d31d35b | 651 | |
0f3fa48a | 652 | core_bits = get_count_order(c->x86_max_cores); |
9d31d35b | 653 | |
0f3fa48a IM |
654 | c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) & |
655 | ((1 << core_bits) - 1); | |
1da177e4 | 656 | |
0a488a53 | 657 | out: |
2eaad1fd | 658 | if (!printed && (c->x86_max_cores * smp_num_siblings) > 1) { |
1b74dde7 CY |
659 | pr_info("CPU: Physical Processor ID: %d\n", |
660 | c->phys_proc_id); | |
661 | pr_info("CPU: Processor Core ID: %d\n", | |
662 | c->cpu_core_id); | |
2eaad1fd | 663 | printed = 1; |
9d31d35b | 664 | } |
9d31d35b | 665 | #endif |
97e4db7c | 666 | } |
1da177e4 | 667 | |
148f9bb8 | 668 | static void get_cpu_vendor(struct cpuinfo_x86 *c) |
1da177e4 LT |
669 | { |
670 | char *v = c->x86_vendor_id; | |
0f3fa48a | 671 | int i; |
1da177e4 LT |
672 | |
673 | for (i = 0; i < X86_VENDOR_NUM; i++) { | |
10a434fc YL |
674 | if (!cpu_devs[i]) |
675 | break; | |
676 | ||
677 | if (!strcmp(v, cpu_devs[i]->c_ident[0]) || | |
678 | (cpu_devs[i]->c_ident[1] && | |
679 | !strcmp(v, cpu_devs[i]->c_ident[1]))) { | |
0f3fa48a | 680 | |
10a434fc YL |
681 | this_cpu = cpu_devs[i]; |
682 | c->x86_vendor = this_cpu->c_x86_vendor; | |
683 | return; | |
1da177e4 LT |
684 | } |
685 | } | |
10a434fc | 686 | |
1b74dde7 CY |
687 | pr_err_once("CPU: vendor_id '%s' unknown, using generic init.\n" \ |
688 | "CPU: Your system may be unstable.\n", v); | |
10a434fc | 689 | |
fe38d855 CE |
690 | c->x86_vendor = X86_VENDOR_UNKNOWN; |
691 | this_cpu = &default_cpu; | |
1da177e4 LT |
692 | } |
693 | ||
148f9bb8 | 694 | void cpu_detect(struct cpuinfo_x86 *c) |
1da177e4 | 695 | { |
1da177e4 | 696 | /* Get vendor name */ |
4a148513 HH |
697 | cpuid(0x00000000, (unsigned int *)&c->cpuid_level, |
698 | (unsigned int *)&c->x86_vendor_id[0], | |
699 | (unsigned int *)&c->x86_vendor_id[8], | |
700 | (unsigned int *)&c->x86_vendor_id[4]); | |
1da177e4 | 701 | |
1da177e4 | 702 | c->x86 = 4; |
9d31d35b | 703 | /* Intel-defined flags: level 0x00000001 */ |
1da177e4 LT |
704 | if (c->cpuid_level >= 0x00000001) { |
705 | u32 junk, tfms, cap0, misc; | |
0f3fa48a | 706 | |
1da177e4 | 707 | cpuid(0x00000001, &tfms, &misc, &junk, &cap0); |
99f925ce BP |
708 | c->x86 = x86_family(tfms); |
709 | c->x86_model = x86_model(tfms); | |
710 | c->x86_mask = x86_stepping(tfms); | |
0f3fa48a | 711 | |
d4387bd3 | 712 | if (cap0 & (1<<19)) { |
d4387bd3 | 713 | c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; |
9d31d35b | 714 | c->x86_cache_alignment = c->x86_clflush_size; |
d4387bd3 | 715 | } |
1da177e4 | 716 | } |
1da177e4 | 717 | } |
3da99c97 | 718 | |
8bf1ebca AL |
719 | static void apply_forced_caps(struct cpuinfo_x86 *c) |
720 | { | |
721 | int i; | |
722 | ||
aab40a66 | 723 | for (i = 0; i < NCAPINTS + NBUGINTS; i++) { |
8bf1ebca AL |
724 | c->x86_capability[i] &= ~cpu_caps_cleared[i]; |
725 | c->x86_capability[i] |= cpu_caps_set[i]; | |
726 | } | |
727 | } | |
728 | ||
148f9bb8 | 729 | void get_cpu_cap(struct cpuinfo_x86 *c) |
093af8d7 | 730 | { |
39c06df4 | 731 | u32 eax, ebx, ecx, edx; |
093af8d7 | 732 | |
3da99c97 YL |
733 | /* Intel-defined flags: level 0x00000001 */ |
734 | if (c->cpuid_level >= 0x00000001) { | |
39c06df4 | 735 | cpuid(0x00000001, &eax, &ebx, &ecx, &edx); |
0f3fa48a | 736 | |
39c06df4 BP |
737 | c->x86_capability[CPUID_1_ECX] = ecx; |
738 | c->x86_capability[CPUID_1_EDX] = edx; | |
3da99c97 | 739 | } |
093af8d7 | 740 | |
3df8d920 AL |
741 | /* Thermal and Power Management Leaf: level 0x00000006 (eax) */ |
742 | if (c->cpuid_level >= 0x00000006) | |
743 | c->x86_capability[CPUID_6_EAX] = cpuid_eax(0x00000006); | |
744 | ||
bdc802dc PA |
745 | /* Additional Intel-defined flags: level 0x00000007 */ |
746 | if (c->cpuid_level >= 0x00000007) { | |
bdc802dc | 747 | cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx); |
39c06df4 | 748 | c->x86_capability[CPUID_7_0_EBX] = ebx; |
dfb4a70f | 749 | c->x86_capability[CPUID_7_ECX] = ecx; |
bdc802dc PA |
750 | } |
751 | ||
6229ad27 FY |
752 | /* Extended state features: level 0x0000000d */ |
753 | if (c->cpuid_level >= 0x0000000d) { | |
6229ad27 FY |
754 | cpuid_count(0x0000000d, 1, &eax, &ebx, &ecx, &edx); |
755 | ||
39c06df4 | 756 | c->x86_capability[CPUID_D_1_EAX] = eax; |
6229ad27 FY |
757 | } |
758 | ||
cbc82b17 PWJ |
759 | /* Additional Intel-defined flags: level 0x0000000F */ |
760 | if (c->cpuid_level >= 0x0000000F) { | |
cbc82b17 PWJ |
761 | |
762 | /* QoS sub-leaf, EAX=0Fh, ECX=0 */ | |
763 | cpuid_count(0x0000000F, 0, &eax, &ebx, &ecx, &edx); | |
39c06df4 BP |
764 | c->x86_capability[CPUID_F_0_EDX] = edx; |
765 | ||
cbc82b17 PWJ |
766 | if (cpu_has(c, X86_FEATURE_CQM_LLC)) { |
767 | /* will be overridden if occupancy monitoring exists */ | |
768 | c->x86_cache_max_rmid = ebx; | |
769 | ||
770 | /* QoS sub-leaf, EAX=0Fh, ECX=1 */ | |
771 | cpuid_count(0x0000000F, 1, &eax, &ebx, &ecx, &edx); | |
39c06df4 BP |
772 | c->x86_capability[CPUID_F_1_EDX] = edx; |
773 | ||
33c3cc7a VS |
774 | if ((cpu_has(c, X86_FEATURE_CQM_OCCUP_LLC)) || |
775 | ((cpu_has(c, X86_FEATURE_CQM_MBM_TOTAL)) || | |
776 | (cpu_has(c, X86_FEATURE_CQM_MBM_LOCAL)))) { | |
cbc82b17 PWJ |
777 | c->x86_cache_max_rmid = ecx; |
778 | c->x86_cache_occ_scale = ebx; | |
779 | } | |
780 | } else { | |
781 | c->x86_cache_max_rmid = -1; | |
782 | c->x86_cache_occ_scale = -1; | |
783 | } | |
784 | } | |
785 | ||
3da99c97 | 786 | /* AMD-defined flags: level 0x80000001 */ |
39c06df4 BP |
787 | eax = cpuid_eax(0x80000000); |
788 | c->extended_cpuid_level = eax; | |
789 | ||
790 | if ((eax & 0xffff0000) == 0x80000000) { | |
791 | if (eax >= 0x80000001) { | |
792 | cpuid(0x80000001, &eax, &ebx, &ecx, &edx); | |
0f3fa48a | 793 | |
39c06df4 BP |
794 | c->x86_capability[CPUID_8000_0001_ECX] = ecx; |
795 | c->x86_capability[CPUID_8000_0001_EDX] = edx; | |
093af8d7 | 796 | } |
093af8d7 | 797 | } |
093af8d7 | 798 | |
71faad43 YG |
799 | if (c->extended_cpuid_level >= 0x80000007) { |
800 | cpuid(0x80000007, &eax, &ebx, &ecx, &edx); | |
801 | ||
802 | c->x86_capability[CPUID_8000_0007_EBX] = ebx; | |
803 | c->x86_power = edx; | |
804 | } | |
805 | ||
5122c890 | 806 | if (c->extended_cpuid_level >= 0x80000008) { |
39c06df4 | 807 | cpuid(0x80000008, &eax, &ebx, &ecx, &edx); |
5122c890 YL |
808 | |
809 | c->x86_virt_bits = (eax >> 8) & 0xff; | |
810 | c->x86_phys_bits = eax & 0xff; | |
39c06df4 | 811 | c->x86_capability[CPUID_8000_0008_EBX] = ebx; |
093af8d7 | 812 | } |
13c6c532 JB |
813 | #ifdef CONFIG_X86_32 |
814 | else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36)) | |
815 | c->x86_phys_bits = 36; | |
5122c890 | 816 | #endif |
e3224234 | 817 | |
2ccd71f1 | 818 | if (c->extended_cpuid_level >= 0x8000000a) |
39c06df4 | 819 | c->x86_capability[CPUID_8000_000A_EDX] = cpuid_edx(0x8000000a); |
093af8d7 | 820 | |
1dedefd1 | 821 | init_scattered_cpuid_features(c); |
60d34501 AL |
822 | |
823 | /* | |
824 | * Clear/Set all flags overridden by options, after probe. | |
825 | * This needs to happen each time we re-probe, which may happen | |
826 | * several times during CPU initialization. | |
827 | */ | |
828 | apply_forced_caps(c); | |
093af8d7 | 829 | } |
1da177e4 | 830 | |
148f9bb8 | 831 | static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c) |
aef93c8b YL |
832 | { |
833 | #ifdef CONFIG_X86_32 | |
834 | int i; | |
835 | ||
836 | /* | |
837 | * First of all, decide if this is a 486 or higher | |
838 | * It's a 486 if we can modify the AC flag | |
839 | */ | |
840 | if (flag_is_changeable_p(X86_EFLAGS_AC)) | |
841 | c->x86 = 4; | |
842 | else | |
843 | c->x86 = 3; | |
844 | ||
845 | for (i = 0; i < X86_VENDOR_NUM; i++) | |
846 | if (cpu_devs[i] && cpu_devs[i]->c_identify) { | |
847 | c->x86_vendor_id[0] = 0; | |
848 | cpu_devs[i]->c_identify(c); | |
849 | if (c->x86_vendor_id[0]) { | |
850 | get_cpu_vendor(c); | |
851 | break; | |
852 | } | |
853 | } | |
854 | #endif | |
855 | } | |
856 | ||
6b593f57 DW |
857 | static const __initdata struct x86_cpu_id cpu_no_speculation[] = { |
858 | { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_CEDARVIEW, X86_FEATURE_ANY }, | |
859 | { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_CLOVERVIEW, X86_FEATURE_ANY }, | |
860 | { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_LINCROFT, X86_FEATURE_ANY }, | |
861 | { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_PENWELL, X86_FEATURE_ANY }, | |
862 | { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_PINEVIEW, X86_FEATURE_ANY }, | |
863 | { X86_VENDOR_CENTAUR, 5 }, | |
864 | { X86_VENDOR_INTEL, 5 }, | |
865 | { X86_VENDOR_NSC, 5 }, | |
866 | { X86_VENDOR_ANY, 4 }, | |
867 | {} | |
868 | }; | |
869 | ||
870 | static const __initdata struct x86_cpu_id cpu_no_meltdown[] = { | |
871 | { X86_VENDOR_AMD }, | |
872 | {} | |
873 | }; | |
874 | ||
abe4b60b KRW |
875 | static const __initconst struct x86_cpu_id cpu_no_spec_store_bypass[] = { |
876 | { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_PINEVIEW }, | |
877 | { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_LINCROFT }, | |
878 | { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_PENWELL }, | |
879 | { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_CLOVERVIEW }, | |
880 | { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_CEDARVIEW }, | |
881 | { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_SILVERMONT1 }, | |
882 | { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_AIRMONT }, | |
883 | { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_SILVERMONT2 }, | |
884 | { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_MERRIFIELD }, | |
885 | { X86_VENDOR_INTEL, 6, INTEL_FAM6_CORE_YONAH }, | |
886 | { X86_VENDOR_INTEL, 6, INTEL_FAM6_XEON_PHI_KNL }, | |
887 | { X86_VENDOR_INTEL, 6, INTEL_FAM6_XEON_PHI_KNM }, | |
888 | { X86_VENDOR_CENTAUR, 5, }, | |
889 | { X86_VENDOR_INTEL, 5, }, | |
890 | { X86_VENDOR_NSC, 5, }, | |
891 | { X86_VENDOR_ANY, 4, }, | |
892 | {} | |
893 | }; | |
894 | ||
8642262e | 895 | static void __init cpu_set_bug_bits(struct cpuinfo_x86 *c) |
6b593f57 DW |
896 | { |
897 | u64 ia32_cap = 0; | |
898 | ||
2b83aba8 KRW |
899 | if (cpu_has(c, X86_FEATURE_ARCH_CAPABILITIES)) |
900 | rdmsrl(MSR_IA32_ARCH_CAPABILITIES, ia32_cap); | |
901 | ||
902 | if (!x86_match_cpu(cpu_no_spec_store_bypass) && | |
903 | !(ia32_cap & ARCH_CAP_RDS_NO)) | |
abe4b60b KRW |
904 | setup_force_cpu_bug(X86_BUG_SPEC_STORE_BYPASS); |
905 | ||
8642262e KRW |
906 | if (x86_match_cpu(cpu_no_speculation)) |
907 | return; | |
908 | ||
909 | setup_force_cpu_bug(X86_BUG_SPECTRE_V1); | |
910 | setup_force_cpu_bug(X86_BUG_SPECTRE_V2); | |
911 | ||
6b593f57 | 912 | if (x86_match_cpu(cpu_no_meltdown)) |
8642262e | 913 | return; |
6b593f57 | 914 | |
6b593f57 DW |
915 | /* Rogue Data Cache Load? No! */ |
916 | if (ia32_cap & ARCH_CAP_RDCL_NO) | |
8642262e | 917 | return; |
6b593f57 | 918 | |
8642262e | 919 | setup_force_cpu_bug(X86_BUG_CPU_MELTDOWN); |
6b593f57 DW |
920 | } |
921 | ||
34048c9e PC |
922 | /* |
923 | * Do minimum CPU detection early. | |
924 | * Fields really needed: vendor, cpuid_level, family, model, mask, | |
925 | * cache alignment. | |
926 | * The others are not touched to avoid unwanted side effects. | |
927 | * | |
928 | * WARNING: this function is only called on the BP. Don't add code here | |
929 | * that is supposed to run on all CPUs. | |
930 | */ | |
3da99c97 | 931 | static void __init early_identify_cpu(struct cpuinfo_x86 *c) |
d7cd5611 | 932 | { |
6627d242 YL |
933 | #ifdef CONFIG_X86_64 |
934 | c->x86_clflush_size = 64; | |
13c6c532 JB |
935 | c->x86_phys_bits = 36; |
936 | c->x86_virt_bits = 48; | |
6627d242 | 937 | #else |
d4387bd3 | 938 | c->x86_clflush_size = 32; |
13c6c532 JB |
939 | c->x86_phys_bits = 32; |
940 | c->x86_virt_bits = 32; | |
6627d242 | 941 | #endif |
0a488a53 | 942 | c->x86_cache_alignment = c->x86_clflush_size; |
d7cd5611 | 943 | |
3da99c97 | 944 | memset(&c->x86_capability, 0, sizeof c->x86_capability); |
0a488a53 | 945 | c->extended_cpuid_level = 0; |
d7cd5611 | 946 | |
aef93c8b | 947 | /* cyrix could have cpuid enabled via c_identify()*/ |
05fb3c19 AL |
948 | if (have_cpuid_p()) { |
949 | cpu_detect(c); | |
950 | get_cpu_vendor(c); | |
951 | get_cpu_cap(c); | |
78d1b296 | 952 | setup_force_cpu_cap(X86_FEATURE_CPUID); |
d7cd5611 | 953 | |
05fb3c19 AL |
954 | if (this_cpu->c_early_init) |
955 | this_cpu->c_early_init(c); | |
12cf105c | 956 | |
05fb3c19 AL |
957 | c->cpu_index = 0; |
958 | filter_cpuid_features(c, false); | |
093af8d7 | 959 | |
05fb3c19 AL |
960 | if (this_cpu->c_bsp_init) |
961 | this_cpu->c_bsp_init(c); | |
78d1b296 BP |
962 | } else { |
963 | identify_cpu_without_cpuid(c); | |
964 | setup_clear_cpu_cap(X86_FEATURE_CPUID); | |
05fb3c19 | 965 | } |
c3b83598 BP |
966 | |
967 | setup_force_cpu_cap(X86_FEATURE_ALWAYS); | |
3b0dffb3 | 968 | |
8642262e | 969 | cpu_set_bug_bits(c); |
de861dbf | 970 | |
db52ef74 | 971 | fpu__init_system(c); |
d7cd5611 RR |
972 | } |
973 | ||
9d31d35b YL |
974 | void __init early_cpu_init(void) |
975 | { | |
02dde8b4 | 976 | const struct cpu_dev *const *cdev; |
10a434fc YL |
977 | int count = 0; |
978 | ||
ac23f253 | 979 | #ifdef CONFIG_PROCESSOR_SELECT |
1b74dde7 | 980 | pr_info("KERNEL supported cpus:\n"); |
31c997ca IM |
981 | #endif |
982 | ||
10a434fc | 983 | for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) { |
02dde8b4 | 984 | const struct cpu_dev *cpudev = *cdev; |
9d31d35b | 985 | |
10a434fc YL |
986 | if (count >= X86_VENDOR_NUM) |
987 | break; | |
988 | cpu_devs[count] = cpudev; | |
989 | count++; | |
990 | ||
ac23f253 | 991 | #ifdef CONFIG_PROCESSOR_SELECT |
31c997ca IM |
992 | { |
993 | unsigned int j; | |
994 | ||
995 | for (j = 0; j < 2; j++) { | |
996 | if (!cpudev->c_ident[j]) | |
997 | continue; | |
1b74dde7 | 998 | pr_info(" %s %s\n", cpudev->c_vendor, |
31c997ca IM |
999 | cpudev->c_ident[j]); |
1000 | } | |
10a434fc | 1001 | } |
0388423d | 1002 | #endif |
10a434fc | 1003 | } |
9d31d35b | 1004 | early_identify_cpu(&boot_cpu_data); |
d7cd5611 | 1005 | } |
093af8d7 | 1006 | |
b6734c35 | 1007 | /* |
366d4a43 BP |
1008 | * The NOPL instruction is supposed to exist on all CPUs of family >= 6; |
1009 | * unfortunately, that's not true in practice because of early VIA | |
1010 | * chips and (more importantly) broken virtualizers that are not easy | |
1011 | * to detect. In the latter case it doesn't even *fail* reliably, so | |
1012 | * probing for it doesn't even work. Disable it completely on 32-bit | |
ba0593bf | 1013 | * unless we can find a reliable way to detect all the broken cases. |
366d4a43 | 1014 | * Enable it explicitly on 64-bit for non-constant inputs of cpu_has(). |
b6734c35 | 1015 | */ |
148f9bb8 | 1016 | static void detect_nopl(struct cpuinfo_x86 *c) |
b6734c35 | 1017 | { |
366d4a43 | 1018 | #ifdef CONFIG_X86_32 |
b6734c35 | 1019 | clear_cpu_cap(c, X86_FEATURE_NOPL); |
366d4a43 BP |
1020 | #else |
1021 | set_cpu_cap(c, X86_FEATURE_NOPL); | |
58a5aac5 | 1022 | #endif |
d7cd5611 | 1023 | } |
58a5aac5 | 1024 | |
7a5d6704 AL |
1025 | static void detect_null_seg_behavior(struct cpuinfo_x86 *c) |
1026 | { | |
1027 | #ifdef CONFIG_X86_64 | |
58a5aac5 | 1028 | /* |
7a5d6704 AL |
1029 | * Empirically, writing zero to a segment selector on AMD does |
1030 | * not clear the base, whereas writing zero to a segment | |
1031 | * selector on Intel does clear the base. Intel's behavior | |
1032 | * allows slightly faster context switches in the common case | |
1033 | * where GS is unused by the prev and next threads. | |
58a5aac5 | 1034 | * |
7a5d6704 AL |
1035 | * Since neither vendor documents this anywhere that I can see, |
1036 | * detect it directly instead of hardcoding the choice by | |
1037 | * vendor. | |
1038 | * | |
1039 | * I've designated AMD's behavior as the "bug" because it's | |
1040 | * counterintuitive and less friendly. | |
58a5aac5 | 1041 | */ |
7a5d6704 AL |
1042 | |
1043 | unsigned long old_base, tmp; | |
1044 | rdmsrl(MSR_FS_BASE, old_base); | |
1045 | wrmsrl(MSR_FS_BASE, 1); | |
1046 | loadsegment(fs, 0); | |
1047 | rdmsrl(MSR_FS_BASE, tmp); | |
1048 | if (tmp != 0) | |
1049 | set_cpu_bug(c, X86_BUG_NULL_SEG); | |
1050 | wrmsrl(MSR_FS_BASE, old_base); | |
366d4a43 | 1051 | #endif |
d7cd5611 RR |
1052 | } |
1053 | ||
148f9bb8 | 1054 | static void generic_identify(struct cpuinfo_x86 *c) |
1da177e4 | 1055 | { |
aef93c8b | 1056 | c->extended_cpuid_level = 0; |
1da177e4 | 1057 | |
3da99c97 | 1058 | if (!have_cpuid_p()) |
aef93c8b | 1059 | identify_cpu_without_cpuid(c); |
1d67953f | 1060 | |
aef93c8b | 1061 | /* cyrix could have cpuid enabled via c_identify()*/ |
a9853dd6 | 1062 | if (!have_cpuid_p()) |
aef93c8b | 1063 | return; |
1da177e4 | 1064 | |
3da99c97 | 1065 | cpu_detect(c); |
1da177e4 | 1066 | |
3da99c97 | 1067 | get_cpu_vendor(c); |
1da177e4 | 1068 | |
3da99c97 | 1069 | get_cpu_cap(c); |
1da177e4 | 1070 | |
3da99c97 YL |
1071 | if (c->cpuid_level >= 0x00000001) { |
1072 | c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF; | |
b89d3b3e | 1073 | #ifdef CONFIG_X86_32 |
c8e56d20 | 1074 | # ifdef CONFIG_SMP |
cb8cc442 | 1075 | c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); |
b89d3b3e | 1076 | # else |
3da99c97 | 1077 | c->apicid = c->initial_apicid; |
b89d3b3e YL |
1078 | # endif |
1079 | #endif | |
b89d3b3e | 1080 | c->phys_proc_id = c->initial_apicid; |
3da99c97 | 1081 | } |
1da177e4 | 1082 | |
1b05d60d | 1083 | get_model_name(c); /* Default name */ |
1da177e4 | 1084 | |
3da99c97 | 1085 | detect_nopl(c); |
7a5d6704 AL |
1086 | |
1087 | detect_null_seg_behavior(c); | |
0230bb03 AL |
1088 | |
1089 | /* | |
1090 | * ESPFIX is a strange bug. All real CPUs have it. Paravirt | |
1091 | * systems that run Linux at CPL > 0 may or may not have the | |
1092 | * issue, but, even if they have the issue, there's absolutely | |
1093 | * nothing we can do about it because we can't use the real IRET | |
1094 | * instruction. | |
1095 | * | |
1096 | * NB: For the time being, only 32-bit kernels support | |
1097 | * X86_BUG_ESPFIX as such. 64-bit kernels directly choose | |
1098 | * whether to apply espfix using paravirt hooks. If any | |
1099 | * non-paravirt system ever shows up that does *not* have the | |
1100 | * ESPFIX issue, we can change this. | |
1101 | */ | |
1102 | #ifdef CONFIG_X86_32 | |
1103 | # ifdef CONFIG_PARAVIRT | |
1104 | do { | |
1105 | extern void native_iret(void); | |
1106 | if (pv_cpu_ops.iret == native_iret) | |
1107 | set_cpu_bug(c, X86_BUG_ESPFIX); | |
1108 | } while (0); | |
1109 | # else | |
1110 | set_cpu_bug(c, X86_BUG_ESPFIX); | |
1111 | # endif | |
1112 | #endif | |
1da177e4 | 1113 | } |
1da177e4 | 1114 | |
cbc82b17 PWJ |
1115 | static void x86_init_cache_qos(struct cpuinfo_x86 *c) |
1116 | { | |
1117 | /* | |
1118 | * The heavy lifting of max_rmid and cache_occ_scale are handled | |
1119 | * in get_cpu_cap(). Here we just set the max_rmid for the boot_cpu | |
1120 | * in case CQM bits really aren't there in this CPU. | |
1121 | */ | |
1122 | if (c != &boot_cpu_data) { | |
1123 | boot_cpu_data.x86_cache_max_rmid = | |
1124 | min(boot_cpu_data.x86_cache_max_rmid, | |
1125 | c->x86_cache_max_rmid); | |
1126 | } | |
1127 | } | |
1128 | ||
d49597fd | 1129 | /* |
9d85eb91 TG |
1130 | * Validate that ACPI/mptables have the same information about the |
1131 | * effective APIC id and update the package map. | |
d49597fd | 1132 | */ |
9d85eb91 | 1133 | static void validate_apic_and_package_id(struct cpuinfo_x86 *c) |
d49597fd TG |
1134 | { |
1135 | #ifdef CONFIG_SMP | |
9d85eb91 | 1136 | unsigned int apicid, cpu = smp_processor_id(); |
d49597fd TG |
1137 | |
1138 | apicid = apic->cpu_present_to_apicid(cpu); | |
d49597fd | 1139 | |
9d85eb91 TG |
1140 | if (apicid != c->apicid) { |
1141 | pr_err(FW_BUG "CPU%u: APIC id mismatch. Firmware: %x APIC: %x\n", | |
d49597fd | 1142 | cpu, apicid, c->initial_apicid); |
d49597fd | 1143 | } |
9d85eb91 | 1144 | BUG_ON(topology_update_package_map(c->phys_proc_id, cpu)); |
d49597fd TG |
1145 | #else |
1146 | c->logical_proc_id = 0; | |
1147 | #endif | |
1148 | } | |
1149 | ||
1da177e4 LT |
1150 | /* |
1151 | * This does the hard work of actually picking apart the CPU stuff... | |
1152 | */ | |
148f9bb8 | 1153 | static void identify_cpu(struct cpuinfo_x86 *c) |
1da177e4 LT |
1154 | { |
1155 | int i; | |
1156 | ||
1157 | c->loops_per_jiffy = loops_per_jiffy; | |
1158 | c->x86_cache_size = -1; | |
1159 | c->x86_vendor = X86_VENDOR_UNKNOWN; | |
1da177e4 LT |
1160 | c->x86_model = c->x86_mask = 0; /* So far unknown... */ |
1161 | c->x86_vendor_id[0] = '\0'; /* Unset */ | |
1162 | c->x86_model_id[0] = '\0'; /* Unset */ | |
94605eff | 1163 | c->x86_max_cores = 1; |
102bbe3a | 1164 | c->x86_coreid_bits = 0; |
79a8b9aa | 1165 | c->cu_id = 0xff; |
11fdd252 | 1166 | #ifdef CONFIG_X86_64 |
102bbe3a | 1167 | c->x86_clflush_size = 64; |
13c6c532 JB |
1168 | c->x86_phys_bits = 36; |
1169 | c->x86_virt_bits = 48; | |
102bbe3a YL |
1170 | #else |
1171 | c->cpuid_level = -1; /* CPUID not detected */ | |
770d132f | 1172 | c->x86_clflush_size = 32; |
13c6c532 JB |
1173 | c->x86_phys_bits = 32; |
1174 | c->x86_virt_bits = 32; | |
102bbe3a YL |
1175 | #endif |
1176 | c->x86_cache_alignment = c->x86_clflush_size; | |
1da177e4 LT |
1177 | memset(&c->x86_capability, 0, sizeof c->x86_capability); |
1178 | ||
1da177e4 LT |
1179 | generic_identify(c); |
1180 | ||
3898534d | 1181 | if (this_cpu->c_identify) |
1da177e4 LT |
1182 | this_cpu->c_identify(c); |
1183 | ||
6a6256f9 | 1184 | /* Clear/Set all flags overridden by options, after probe */ |
8bf1ebca | 1185 | apply_forced_caps(c); |
2759c328 | 1186 | |
102bbe3a | 1187 | #ifdef CONFIG_X86_64 |
cb8cc442 | 1188 | c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); |
102bbe3a YL |
1189 | #endif |
1190 | ||
1da177e4 LT |
1191 | /* |
1192 | * Vendor-specific initialization. In this section we | |
1193 | * canonicalize the feature flags, meaning if there are | |
1194 | * features a certain CPU supports which CPUID doesn't | |
1195 | * tell us, CPUID claiming incorrect flags, or other bugs, | |
1196 | * we handle them here. | |
1197 | * | |
1198 | * At the end of this section, c->x86_capability better | |
1199 | * indicate the features this CPU genuinely supports! | |
1200 | */ | |
1201 | if (this_cpu->c_init) | |
1202 | this_cpu->c_init(c); | |
1203 | ||
1204 | /* Disable the PN if appropriate */ | |
1205 | squash_the_stupid_serial_number(c); | |
1206 | ||
b2cc2a07 PA |
1207 | /* Set up SMEP/SMAP */ |
1208 | setup_smep(c); | |
1209 | setup_smap(c); | |
1210 | ||
1da177e4 | 1211 | /* |
0f3fa48a IM |
1212 | * The vendor-specific functions might have changed features. |
1213 | * Now we do "generic changes." | |
1da177e4 LT |
1214 | */ |
1215 | ||
b38b0665 PA |
1216 | /* Filter out anything that depends on CPUID levels we don't have */ |
1217 | filter_cpuid_features(c, true); | |
1218 | ||
1da177e4 | 1219 | /* If the model name is still unset, do table lookup. */ |
34048c9e | 1220 | if (!c->x86_model_id[0]) { |
02dde8b4 | 1221 | const char *p; |
1da177e4 | 1222 | p = table_lookup_model(c); |
34048c9e | 1223 | if (p) |
1da177e4 LT |
1224 | strcpy(c->x86_model_id, p); |
1225 | else | |
1226 | /* Last resort... */ | |
1227 | sprintf(c->x86_model_id, "%02x/%02x", | |
54a20f8c | 1228 | c->x86, c->x86_model); |
1da177e4 LT |
1229 | } |
1230 | ||
102bbe3a YL |
1231 | #ifdef CONFIG_X86_64 |
1232 | detect_ht(c); | |
1233 | #endif | |
1234 | ||
49d859d7 | 1235 | x86_init_rdrand(c); |
cbc82b17 | 1236 | x86_init_cache_qos(c); |
06976945 | 1237 | setup_pku(c); |
3e0c3737 YL |
1238 | |
1239 | /* | |
6a6256f9 | 1240 | * Clear/Set all flags overridden by options, need do it |
3e0c3737 YL |
1241 | * before following smp all cpus cap AND. |
1242 | */ | |
8bf1ebca | 1243 | apply_forced_caps(c); |
3e0c3737 | 1244 | |
1da177e4 LT |
1245 | /* |
1246 | * On SMP, boot_cpu_data holds the common feature set between | |
1247 | * all CPUs; so make sure that we indicate which features are | |
1248 | * common between the CPUs. The first time this routine gets | |
1249 | * executed, c == &boot_cpu_data. | |
1250 | */ | |
34048c9e | 1251 | if (c != &boot_cpu_data) { |
1da177e4 | 1252 | /* AND the already accumulated flags with these */ |
9d31d35b | 1253 | for (i = 0; i < NCAPINTS; i++) |
1da177e4 | 1254 | boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; |
65fc985b BP |
1255 | |
1256 | /* OR, i.e. replicate the bug flags */ | |
1257 | for (i = NCAPINTS; i < NCAPINTS + NBUGINTS; i++) | |
1258 | c->x86_capability[i] |= boot_cpu_data.x86_capability[i]; | |
1da177e4 LT |
1259 | } |
1260 | ||
1261 | /* Init Machine Check Exception if available. */ | |
5e09954a | 1262 | mcheck_cpu_init(c); |
30d432df AK |
1263 | |
1264 | select_idle_routine(c); | |
102bbe3a | 1265 | |
de2d9445 | 1266 | #ifdef CONFIG_NUMA |
102bbe3a YL |
1267 | numa_add_cpu(smp_processor_id()); |
1268 | #endif | |
a6c4e076 | 1269 | } |
31ab269a | 1270 | |
8b6c0ab1 IM |
1271 | /* |
1272 | * Set up the CPU state needed to execute SYSENTER/SYSEXIT instructions | |
1273 | * on 32-bit kernels: | |
1274 | */ | |
cfda7bb9 AL |
1275 | #ifdef CONFIG_X86_32 |
1276 | void enable_sep_cpu(void) | |
1277 | { | |
8b6c0ab1 IM |
1278 | struct tss_struct *tss; |
1279 | int cpu; | |
cfda7bb9 | 1280 | |
b3edfda4 BP |
1281 | if (!boot_cpu_has(X86_FEATURE_SEP)) |
1282 | return; | |
1283 | ||
8b6c0ab1 | 1284 | cpu = get_cpu(); |
785be108 | 1285 | tss = &per_cpu(cpu_tss_rw, cpu); |
8b6c0ab1 | 1286 | |
8b6c0ab1 | 1287 | /* |
cf9328cc AL |
1288 | * We cache MSR_IA32_SYSENTER_CS's value in the TSS's ss1 field -- |
1289 | * see the big comment in struct x86_hw_tss's definition. | |
8b6c0ab1 | 1290 | */ |
cfda7bb9 AL |
1291 | |
1292 | tss->x86_tss.ss1 = __KERNEL_CS; | |
8b6c0ab1 | 1293 | wrmsr(MSR_IA32_SYSENTER_CS, tss->x86_tss.ss1, 0); |
e0437c47 | 1294 | wrmsr(MSR_IA32_SYSENTER_ESP, (unsigned long)(cpu_entry_stack(cpu) + 1), 0); |
4c8cd0c5 | 1295 | wrmsr(MSR_IA32_SYSENTER_EIP, (unsigned long)entry_SYSENTER_32, 0); |
8b6c0ab1 | 1296 | |
cfda7bb9 AL |
1297 | put_cpu(); |
1298 | } | |
e04d645f GC |
1299 | #endif |
1300 | ||
a6c4e076 JF |
1301 | void __init identify_boot_cpu(void) |
1302 | { | |
1303 | identify_cpu(&boot_cpu_data); | |
102bbe3a | 1304 | #ifdef CONFIG_X86_32 |
a6c4e076 | 1305 | sysenter_setup(); |
6fe940d6 | 1306 | enable_sep_cpu(); |
102bbe3a | 1307 | #endif |
5b556332 | 1308 | cpu_detect_tlb(&boot_cpu_data); |
a6c4e076 | 1309 | } |
3b520b23 | 1310 | |
148f9bb8 | 1311 | void identify_secondary_cpu(struct cpuinfo_x86 *c) |
a6c4e076 JF |
1312 | { |
1313 | BUG_ON(c == &boot_cpu_data); | |
1314 | identify_cpu(c); | |
102bbe3a | 1315 | #ifdef CONFIG_X86_32 |
a6c4e076 | 1316 | enable_sep_cpu(); |
102bbe3a | 1317 | #endif |
a6c4e076 | 1318 | mtrr_ap_init(); |
9d85eb91 | 1319 | validate_apic_and_package_id(c); |
2b83aba8 | 1320 | x86_spec_ctrl_setup_ap(); |
1da177e4 LT |
1321 | } |
1322 | ||
191679fd AK |
1323 | static __init int setup_noclflush(char *arg) |
1324 | { | |
840d2830 | 1325 | setup_clear_cpu_cap(X86_FEATURE_CLFLUSH); |
da4aaa7d | 1326 | setup_clear_cpu_cap(X86_FEATURE_CLFLUSHOPT); |
191679fd AK |
1327 | return 1; |
1328 | } | |
1329 | __setup("noclflush", setup_noclflush); | |
1330 | ||
148f9bb8 | 1331 | void print_cpu_info(struct cpuinfo_x86 *c) |
1da177e4 | 1332 | { |
02dde8b4 | 1333 | const char *vendor = NULL; |
1da177e4 | 1334 | |
0f3fa48a | 1335 | if (c->x86_vendor < X86_VENDOR_NUM) { |
1da177e4 | 1336 | vendor = this_cpu->c_vendor; |
0f3fa48a IM |
1337 | } else { |
1338 | if (c->cpuid_level >= 0) | |
1339 | vendor = c->x86_vendor_id; | |
1340 | } | |
1da177e4 | 1341 | |
bd32a8cf | 1342 | if (vendor && !strstr(c->x86_model_id, vendor)) |
1b74dde7 | 1343 | pr_cont("%s ", vendor); |
1da177e4 | 1344 | |
9d31d35b | 1345 | if (c->x86_model_id[0]) |
1b74dde7 | 1346 | pr_cont("%s", c->x86_model_id); |
1da177e4 | 1347 | else |
1b74dde7 | 1348 | pr_cont("%d86", c->x86); |
1da177e4 | 1349 | |
1b74dde7 | 1350 | pr_cont(" (family: 0x%x, model: 0x%x", c->x86, c->x86_model); |
924e101a | 1351 | |
34048c9e | 1352 | if (c->x86_mask || c->cpuid_level >= 0) |
1b74dde7 | 1353 | pr_cont(", stepping: 0x%x)\n", c->x86_mask); |
1da177e4 | 1354 | else |
1b74dde7 | 1355 | pr_cont(")\n"); |
1da177e4 LT |
1356 | } |
1357 | ||
27deb452 AK |
1358 | /* |
1359 | * clearcpuid= was already parsed in fpu__init_parse_early_param. | |
1360 | * But we need to keep a dummy __setup around otherwise it would | |
1361 | * show up as an environment variable for init. | |
1362 | */ | |
1363 | static __init int setup_clearcpuid(char *arg) | |
ac72e788 | 1364 | { |
ac72e788 AK |
1365 | return 1; |
1366 | } | |
27deb452 | 1367 | __setup("clearcpuid=", setup_clearcpuid); |
ac72e788 | 1368 | |
d5494d4f | 1369 | #ifdef CONFIG_X86_64 |
404f6aac KC |
1370 | struct desc_ptr idt_descr __ro_after_init = { |
1371 | .size = NR_VECTORS * 16 - 1, | |
1372 | .address = (unsigned long) idt_table, | |
1373 | }; | |
1374 | const struct desc_ptr debug_idt_descr = { | |
1375 | .size = NR_VECTORS * 16 - 1, | |
1376 | .address = (unsigned long) debug_idt_table, | |
1377 | }; | |
d5494d4f | 1378 | |
947e76cd | 1379 | DEFINE_PER_CPU_FIRST(union irq_stack_union, |
277d5b40 | 1380 | irq_stack_union) __aligned(PAGE_SIZE) __visible; |
0f3fa48a | 1381 | |
bdf977b3 | 1382 | /* |
a7fcf28d AL |
1383 | * The following percpu variables are hot. Align current_task to |
1384 | * cacheline size such that they fall in the same cacheline. | |
bdf977b3 TH |
1385 | */ |
1386 | DEFINE_PER_CPU(struct task_struct *, current_task) ____cacheline_aligned = | |
1387 | &init_task; | |
1388 | EXPORT_PER_CPU_SYMBOL(current_task); | |
d5494d4f | 1389 | |
bdf977b3 | 1390 | DEFINE_PER_CPU(char *, irq_stack_ptr) = |
4950d6d4 | 1391 | init_per_cpu_var(irq_stack_union.irq_stack) + IRQ_STACK_SIZE; |
bdf977b3 | 1392 | |
277d5b40 | 1393 | DEFINE_PER_CPU(unsigned int, irq_count) __visible = -1; |
d5494d4f | 1394 | |
c2daa3be PZ |
1395 | DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT; |
1396 | EXPORT_PER_CPU_SYMBOL(__preempt_count); | |
1397 | ||
d5494d4f YL |
1398 | /* May not be marked __init: used by software suspend */ |
1399 | void syscall_init(void) | |
1da177e4 | 1400 | { |
9fec5954 AL |
1401 | extern char _entry_trampoline[]; |
1402 | extern char entry_SYSCALL_64_trampoline[]; | |
1403 | ||
475b37e7 | 1404 | int cpu = smp_processor_id(); |
9fec5954 AL |
1405 | unsigned long SYSCALL64_entry_trampoline = |
1406 | (unsigned long)get_cpu_entry_area(cpu)->entry_trampoline + | |
1407 | (entry_SYSCALL_64_trampoline - _entry_trampoline); | |
475b37e7 | 1408 | |
31ac34ca | 1409 | wrmsr(MSR_STAR, 0, (__USER32_CS << 16) | __KERNEL_CS); |
9ae1ea48 TG |
1410 | if (static_cpu_has(X86_FEATURE_PTI)) |
1411 | wrmsrl(MSR_LSTAR, SYSCALL64_entry_trampoline); | |
1412 | else | |
1413 | wrmsrl(MSR_LSTAR, (unsigned long)entry_SYSCALL_64); | |
d56fe4bf IM |
1414 | |
1415 | #ifdef CONFIG_IA32_EMULATION | |
47edb651 | 1416 | wrmsrl(MSR_CSTAR, (unsigned long)entry_SYSCALL_compat); |
a76c7f46 | 1417 | /* |
487d1edb DV |
1418 | * This only works on Intel CPUs. |
1419 | * On AMD CPUs these MSRs are 32-bit, CPU truncates MSR_IA32_SYSENTER_EIP. | |
1420 | * This does not cause SYSENTER to jump to the wrong location, because | |
1421 | * AMD doesn't allow SYSENTER in long mode (either 32- or 64-bit). | |
a76c7f46 DV |
1422 | */ |
1423 | wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS); | |
e0437c47 | 1424 | wrmsrl_safe(MSR_IA32_SYSENTER_ESP, (unsigned long)(cpu_entry_stack(cpu) + 1)); |
4c8cd0c5 | 1425 | wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (u64)entry_SYSENTER_compat); |
d56fe4bf | 1426 | #else |
47edb651 | 1427 | wrmsrl(MSR_CSTAR, (unsigned long)ignore_sysret); |
6b51311c | 1428 | wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)GDT_ENTRY_INVALID_SEG); |
d56fe4bf IM |
1429 | wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL); |
1430 | wrmsrl_safe(MSR_IA32_SYSENTER_EIP, 0ULL); | |
d5494d4f | 1431 | #endif |
03ae5768 | 1432 | |
d5494d4f YL |
1433 | /* Flags to clear on syscall */ |
1434 | wrmsrl(MSR_SYSCALL_MASK, | |
63bcff2a | 1435 | X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF| |
8c7aa698 | 1436 | X86_EFLAGS_IOPL|X86_EFLAGS_AC|X86_EFLAGS_NT); |
1da177e4 | 1437 | } |
62111195 | 1438 | |
d5494d4f YL |
1439 | /* |
1440 | * Copies of the original ist values from the tss are only accessed during | |
1441 | * debugging, no special alignment required. | |
1442 | */ | |
1443 | DEFINE_PER_CPU(struct orig_ist, orig_ist); | |
1444 | ||
228bdaa9 | 1445 | static DEFINE_PER_CPU(unsigned long, debug_stack_addr); |
42181186 | 1446 | DEFINE_PER_CPU(int, debug_stack_usage); |
228bdaa9 SR |
1447 | |
1448 | int is_debug_stack(unsigned long addr) | |
1449 | { | |
89cbc767 CL |
1450 | return __this_cpu_read(debug_stack_usage) || |
1451 | (addr <= __this_cpu_read(debug_stack_addr) && | |
1452 | addr > (__this_cpu_read(debug_stack_addr) - DEBUG_STKSZ)); | |
228bdaa9 | 1453 | } |
0f46efeb | 1454 | NOKPROBE_SYMBOL(is_debug_stack); |
228bdaa9 | 1455 | |
629f4f9d | 1456 | DEFINE_PER_CPU(u32, debug_idt_ctr); |
f8988175 | 1457 | |
228bdaa9 SR |
1458 | void debug_stack_set_zero(void) |
1459 | { | |
629f4f9d SA |
1460 | this_cpu_inc(debug_idt_ctr); |
1461 | load_current_idt(); | |
228bdaa9 | 1462 | } |
0f46efeb | 1463 | NOKPROBE_SYMBOL(debug_stack_set_zero); |
228bdaa9 SR |
1464 | |
1465 | void debug_stack_reset(void) | |
1466 | { | |
629f4f9d | 1467 | if (WARN_ON(!this_cpu_read(debug_idt_ctr))) |
f8988175 | 1468 | return; |
629f4f9d SA |
1469 | if (this_cpu_dec_return(debug_idt_ctr) == 0) |
1470 | load_current_idt(); | |
228bdaa9 | 1471 | } |
0f46efeb | 1472 | NOKPROBE_SYMBOL(debug_stack_reset); |
228bdaa9 | 1473 | |
0f3fa48a | 1474 | #else /* CONFIG_X86_64 */ |
d5494d4f | 1475 | |
bdf977b3 TH |
1476 | DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task; |
1477 | EXPORT_PER_CPU_SYMBOL(current_task); | |
c2daa3be PZ |
1478 | DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT; |
1479 | EXPORT_PER_CPU_SYMBOL(__preempt_count); | |
bdf977b3 | 1480 | |
a7fcf28d AL |
1481 | /* |
1482 | * On x86_32, vm86 modifies tss.sp0, so sp0 isn't a reliable way to find | |
1483 | * the top of the kernel stack. Use an extra percpu variable to track the | |
1484 | * top of the kernel stack directly. | |
1485 | */ | |
1486 | DEFINE_PER_CPU(unsigned long, cpu_current_top_of_stack) = | |
1487 | (unsigned long)&init_thread_union + THREAD_SIZE; | |
1488 | EXPORT_PER_CPU_SYMBOL(cpu_current_top_of_stack); | |
1489 | ||
60a5317f | 1490 | #ifdef CONFIG_CC_STACKPROTECTOR |
53f82452 | 1491 | DEFINE_PER_CPU_ALIGNED(struct stack_canary, stack_canary); |
60a5317f | 1492 | #endif |
d5494d4f | 1493 | |
0f3fa48a | 1494 | #endif /* CONFIG_X86_64 */ |
c5413fbe | 1495 | |
9766cdbc JSR |
1496 | /* |
1497 | * Clear all 6 debug registers: | |
1498 | */ | |
1499 | static void clear_all_debug_regs(void) | |
1500 | { | |
1501 | int i; | |
1502 | ||
1503 | for (i = 0; i < 8; i++) { | |
1504 | /* Ignore db4, db5 */ | |
1505 | if ((i == 4) || (i == 5)) | |
1506 | continue; | |
1507 | ||
1508 | set_debugreg(0, i); | |
1509 | } | |
1510 | } | |
c5413fbe | 1511 | |
0bb9fef9 JW |
1512 | #ifdef CONFIG_KGDB |
1513 | /* | |
1514 | * Restore debug regs if using kgdbwait and you have a kernel debugger | |
1515 | * connection established. | |
1516 | */ | |
1517 | static void dbg_restore_debug_regs(void) | |
1518 | { | |
1519 | if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break)) | |
1520 | arch_kgdb_ops.correct_hw_break(); | |
1521 | } | |
1522 | #else /* ! CONFIG_KGDB */ | |
1523 | #define dbg_restore_debug_regs() | |
1524 | #endif /* ! CONFIG_KGDB */ | |
1525 | ||
ce4b1b16 IM |
1526 | static void wait_for_master_cpu(int cpu) |
1527 | { | |
1528 | #ifdef CONFIG_SMP | |
1529 | /* | |
1530 | * wait for ACK from master CPU before continuing | |
1531 | * with AP initialization | |
1532 | */ | |
1533 | WARN_ON(cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)); | |
1534 | while (!cpumask_test_cpu(cpu, cpu_callout_mask)) | |
1535 | cpu_relax(); | |
1536 | #endif | |
1537 | } | |
1538 | ||
d2cbcc49 RR |
1539 | /* |
1540 | * cpu_init() initializes state that is per-CPU. Some data is already | |
1541 | * initialized (naturally) in the bootstrap process, such as the GDT | |
1542 | * and IDT. We reload them nevertheless, this function acts as a | |
1543 | * 'CPU state barrier', nothing should get across. | |
1ba76586 | 1544 | * A lot of state is already set up in PDA init for 64 bit |
d2cbcc49 | 1545 | */ |
1ba76586 | 1546 | #ifdef CONFIG_X86_64 |
0f3fa48a | 1547 | |
148f9bb8 | 1548 | void cpu_init(void) |
1ba76586 | 1549 | { |
0fe1e009 | 1550 | struct orig_ist *oist; |
1ba76586 | 1551 | struct task_struct *me; |
0f3fa48a IM |
1552 | struct tss_struct *t; |
1553 | unsigned long v; | |
fb59831b | 1554 | int cpu = raw_smp_processor_id(); |
1ba76586 YL |
1555 | int i; |
1556 | ||
ce4b1b16 IM |
1557 | wait_for_master_cpu(cpu); |
1558 | ||
1e02ce4c AL |
1559 | /* |
1560 | * Initialize the CR4 shadow before doing anything that could | |
1561 | * try to read it. | |
1562 | */ | |
1563 | cr4_init_shadow(); | |
1564 | ||
777284b6 BP |
1565 | if (cpu) |
1566 | load_ucode_ap(); | |
e6ebf5de | 1567 | |
785be108 | 1568 | t = &per_cpu(cpu_tss_rw, cpu); |
0fe1e009 | 1569 | oist = &per_cpu(orig_ist, cpu); |
0f3fa48a | 1570 | |
e7a22c1e | 1571 | #ifdef CONFIG_NUMA |
27fd185f | 1572 | if (this_cpu_read(numa_node) == 0 && |
e534c7c5 LS |
1573 | early_cpu_to_node(cpu) != NUMA_NO_NODE) |
1574 | set_numa_node(early_cpu_to_node(cpu)); | |
e7a22c1e | 1575 | #endif |
1ba76586 YL |
1576 | |
1577 | me = current; | |
1578 | ||
2eaad1fd | 1579 | pr_debug("Initializing CPU#%d\n", cpu); |
1ba76586 | 1580 | |
375074cc | 1581 | cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); |
1ba76586 YL |
1582 | |
1583 | /* | |
1584 | * Initialize the per-CPU GDT with the boot GDT, | |
1585 | * and set up the GDT descriptor: | |
1586 | */ | |
1587 | ||
552be871 | 1588 | switch_to_new_gdt(cpu); |
2697fbd5 BG |
1589 | loadsegment(fs, 0); |
1590 | ||
cf910e83 | 1591 | load_current_idt(); |
1ba76586 YL |
1592 | |
1593 | memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8); | |
1594 | syscall_init(); | |
1595 | ||
1596 | wrmsrl(MSR_FS_BASE, 0); | |
1597 | wrmsrl(MSR_KERNEL_GS_BASE, 0); | |
1598 | barrier(); | |
1599 | ||
4763ed4d | 1600 | x86_configure_nx(); |
659006bf | 1601 | x2apic_setup(); |
1ba76586 YL |
1602 | |
1603 | /* | |
1604 | * set up and load the per-CPU TSS | |
1605 | */ | |
0fe1e009 | 1606 | if (!oist->ist[0]) { |
88e72777 | 1607 | char *estacks = get_cpu_entry_area(cpu)->exception_stacks; |
0f3fa48a | 1608 | |
1ba76586 | 1609 | for (v = 0; v < N_EXCEPTION_STACKS; v++) { |
0f3fa48a | 1610 | estacks += exception_stack_sizes[v]; |
0fe1e009 | 1611 | oist->ist[v] = t->x86_tss.ist[v] = |
1ba76586 | 1612 | (unsigned long)estacks; |
228bdaa9 SR |
1613 | if (v == DEBUG_STACK-1) |
1614 | per_cpu(debug_stack_addr, cpu) = (unsigned long)estacks; | |
1ba76586 YL |
1615 | } |
1616 | } | |
1617 | ||
7123a5de | 1618 | t->x86_tss.io_bitmap_base = IO_BITMAP_OFFSET; |
0f3fa48a | 1619 | |
1ba76586 YL |
1620 | /* |
1621 | * <= is required because the CPU will access up to | |
1622 | * 8 bits beyond the end of the IO permission bitmap. | |
1623 | */ | |
1624 | for (i = 0; i <= IO_BITMAP_LONGS; i++) | |
1625 | t->io_bitmap[i] = ~0UL; | |
1626 | ||
f1f10076 | 1627 | mmgrab(&init_mm); |
1ba76586 | 1628 | me->active_mm = &init_mm; |
8c5dfd25 | 1629 | BUG_ON(me->mm); |
c4b58902 | 1630 | initialize_tlbstate_and_flush(); |
1ba76586 YL |
1631 | enter_lazy_tlb(&init_mm, me); |
1632 | ||
8c6b12e8 | 1633 | /* |
bfb2d0ed AL |
1634 | * Initialize the TSS. sp0 points to the entry trampoline stack |
1635 | * regardless of what task is running. | |
8c6b12e8 | 1636 | */ |
475b37e7 | 1637 | set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss); |
1ba76586 | 1638 | load_TR_desc(); |
e0437c47 | 1639 | load_sp0((unsigned long)(cpu_entry_stack(cpu) + 1)); |
8c6b12e8 | 1640 | |
37868fe1 | 1641 | load_mm_ldt(&init_mm); |
1ba76586 | 1642 | |
0bb9fef9 JW |
1643 | clear_all_debug_regs(); |
1644 | dbg_restore_debug_regs(); | |
1ba76586 | 1645 | |
21c4cd10 | 1646 | fpu__init_cpu(); |
1ba76586 | 1647 | |
1ba76586 YL |
1648 | if (is_uv_system()) |
1649 | uv_cpu_init(); | |
69218e47 | 1650 | |
69218e47 | 1651 | load_fixmap_gdt(cpu); |
1ba76586 YL |
1652 | } |
1653 | ||
1654 | #else | |
1655 | ||
148f9bb8 | 1656 | void cpu_init(void) |
9ee79a3d | 1657 | { |
d2cbcc49 RR |
1658 | int cpu = smp_processor_id(); |
1659 | struct task_struct *curr = current; | |
785be108 | 1660 | struct tss_struct *t = &per_cpu(cpu_tss_rw, cpu); |
62111195 | 1661 | |
ce4b1b16 | 1662 | wait_for_master_cpu(cpu); |
e6ebf5de | 1663 | |
5b2bdbc8 SR |
1664 | /* |
1665 | * Initialize the CR4 shadow before doing anything that could | |
1666 | * try to read it. | |
1667 | */ | |
1668 | cr4_init_shadow(); | |
1669 | ||
ce4b1b16 | 1670 | show_ucode_info_early(); |
62111195 | 1671 | |
1b74dde7 | 1672 | pr_info("Initializing CPU#%d\n", cpu); |
62111195 | 1673 | |
362f924b | 1674 | if (cpu_feature_enabled(X86_FEATURE_VME) || |
59e21e3d | 1675 | boot_cpu_has(X86_FEATURE_TSC) || |
362f924b | 1676 | boot_cpu_has(X86_FEATURE_DE)) |
375074cc | 1677 | cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); |
62111195 | 1678 | |
cf910e83 | 1679 | load_current_idt(); |
552be871 | 1680 | switch_to_new_gdt(cpu); |
1da177e4 | 1681 | |
1da177e4 LT |
1682 | /* |
1683 | * Set up and load the per-CPU TSS and LDT | |
1684 | */ | |
f1f10076 | 1685 | mmgrab(&init_mm); |
62111195 | 1686 | curr->active_mm = &init_mm; |
8c5dfd25 | 1687 | BUG_ON(curr->mm); |
c4b58902 | 1688 | initialize_tlbstate_and_flush(); |
62111195 | 1689 | enter_lazy_tlb(&init_mm, curr); |
1da177e4 | 1690 | |
8c6b12e8 AL |
1691 | /* |
1692 | * Initialize the TSS. Don't bother initializing sp0, as the initial | |
1693 | * task never enters user mode. | |
1694 | */ | |
475b37e7 | 1695 | set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss); |
1da177e4 | 1696 | load_TR_desc(); |
8c6b12e8 | 1697 | |
37868fe1 | 1698 | load_mm_ldt(&init_mm); |
1da177e4 | 1699 | |
7123a5de | 1700 | t->x86_tss.io_bitmap_base = IO_BITMAP_OFFSET; |
f9a196b8 | 1701 | |
22c4e308 | 1702 | #ifdef CONFIG_DOUBLEFAULT |
1da177e4 LT |
1703 | /* Set up doublefault TSS pointer in the GDT */ |
1704 | __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss); | |
22c4e308 | 1705 | #endif |
1da177e4 | 1706 | |
9766cdbc | 1707 | clear_all_debug_regs(); |
0bb9fef9 | 1708 | dbg_restore_debug_regs(); |
1da177e4 | 1709 | |
21c4cd10 | 1710 | fpu__init_cpu(); |
69218e47 | 1711 | |
69218e47 | 1712 | load_fixmap_gdt(cpu); |
1da177e4 | 1713 | } |
1ba76586 | 1714 | #endif |
5700f743 | 1715 | |
b51ef52d LA |
1716 | static void bsp_resume(void) |
1717 | { | |
1718 | if (this_cpu->c_bsp_resume) | |
1719 | this_cpu->c_bsp_resume(&boot_cpu_data); | |
1720 | } | |
1721 | ||
1722 | static struct syscore_ops cpu_syscore_ops = { | |
1723 | .resume = bsp_resume, | |
1724 | }; | |
1725 | ||
1726 | static int __init init_cpu_syscore(void) | |
1727 | { | |
1728 | register_syscore_ops(&cpu_syscore_ops); | |
1729 | return 0; | |
1730 | } | |
1731 | core_initcall(init_cpu_syscore); |