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KVM: Do not report TPR write to userspace if new value bigger or equal to a previous...
[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
8 *
9 * Authors:
10 * Avi Kivity <avi@qumranet.com>
11 * Yaniv Kamay <yaniv@qumranet.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
15 *
16 */
17
85f455f7 18#include "irq.h"
1d737c8a 19#include "mmu.h"
e495606d 20
edf88417 21#include <linux/kvm_host.h>
6aa8b732 22#include <linux/module.h>
9d8f549d 23#include <linux/kernel.h>
6aa8b732
AK		 24#include <linux/mm.h>
25#include <linux/highmem.h>
e8edc6e0 26#include <linux/sched.h>
c7addb90 27#include <linux/moduleparam.h>
5fdbf976 28#include "kvm_cache_regs.h"
35920a35 29#include "x86.h"
e495606d 30
6aa8b732 31#include <asm/io.h>
3b3be0d1 32#include <asm/desc.h>
13673a90 33#include <asm/vmx.h>
6210e37b 34#include <asm/virtext.h>
6aa8b732 35
4ecac3fd
AK		 36#define __ex(x) __kvm_handle_fault_on_reboot(x)
37
6aa8b732
AK		 38MODULE_AUTHOR("Qumranet");
39MODULE_LICENSE("GPL");
40
4462d21a 41static int __read_mostly bypass_guest_pf = 1;
c1f8bc04 42module_param(bypass_guest_pf, bool, S_IRUGO);
c7addb90 43
4462d21a 44static int __read_mostly enable_vpid = 1;
736caefe 45module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 46
4462d21a 47static int __read_mostly flexpriority_enabled = 1;
736caefe 48module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 49
4462d21a 50static int __read_mostly enable_ept = 1;
736caefe 51module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 52
4462d21a 53static int __read_mostly emulate_invalid_guest_state = 0;
c1f8bc04 54module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 55
a2fa3e9f
GH		 56struct vmcs {
57 u32 revision_id;
58 u32 abort;
59 char data[0];
60};
61
62struct vcpu_vmx {
fb3f0f51 63 struct kvm_vcpu vcpu;
543e4243 64 struct list_head local_vcpus_link;
313dbd49 65 unsigned long host_rsp;
a2fa3e9f 66 int launched;
29bd8a78 67 u8 fail;
1155f76a 68 u32 idt_vectoring_info;
a2fa3e9f
GH		 69 struct kvm_msr_entry *guest_msrs;
70 struct kvm_msr_entry *host_msrs;
71 int nmsrs;
72 int save_nmsrs;
73 int msr_offset_efer;
74#ifdef CONFIG_X86_64
75 int msr_offset_kernel_gs_base;
76#endif
77 struct vmcs *vmcs;
78 struct {
79 int loaded;
80 u16 fs_sel, gs_sel, ldt_sel;
152d3f2f
LV		 81 int gs_ldt_reload_needed;
82 int fs_reload_needed;
51c6cf66 83 int guest_efer_loaded;
d77c26fc 84 } host_state;
9c8cba37
AK		 85 struct {
86 struct {
87 bool pending;
88 u8 vector;
89 unsigned rip;
90 } irq;
91 } rmode;
2384d2b3 92 int vpid;
04fa4d32 93 bool emulation_required;
8b3079a5 94 enum emulation_result invalid_state_emulation_result;
3b86cd99
JK		 95
96 /* Support for vnmi-less CPUs */
97 int soft_vnmi_blocked;
98 ktime_t entry_time;
99 s64 vnmi_blocked_time;
a2fa3e9f
GH		 100};
101
102static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
103{
fb3f0f51 104 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 105}
106
b7ebfb05 107static int init_rmode(struct kvm *kvm);
4e1096d2 108static u64 construct_eptp(unsigned long root_hpa);
75880a01 109
6aa8b732
AK		 110static DEFINE_PER_CPU(struct vmcs *, vmxarea);
111static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
543e4243 112static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu);
6aa8b732 113
3e7c73e9
AK		 114static unsigned long *vmx_io_bitmap_a;
115static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 116static unsigned long *vmx_msr_bitmap_legacy;
117static unsigned long *vmx_msr_bitmap_longmode;
fdef3ad1 118
2384d2b3
SY		 119static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
120static DEFINE_SPINLOCK(vmx_vpid_lock);
121
1c3d14fe 122static struct vmcs_config {
6aa8b732
AK		 123 int size;
124 int order;
125 u32 revision_id;
1c3d14fe
YS		 126 u32 pin_based_exec_ctrl;
127 u32 cpu_based_exec_ctrl;
f78e0e2e 128 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 129 u32 vmexit_ctrl;
130 u32 vmentry_ctrl;
131} vmcs_config;
6aa8b732 132
efff9e53 133static struct vmx_capability {
d56f546d
SY		 134 u32 ept;
135 u32 vpid;
136} vmx_capability;
137
6aa8b732
AK		 138#define VMX_SEGMENT_FIELD(seg) \
139 [VCPU_SREG_##seg] = { \
140 .selector = GUEST_##seg##_SELECTOR, \
141 .base = GUEST_##seg##_BASE, \
142 .limit = GUEST_##seg##_LIMIT, \
143 .ar_bytes = GUEST_##seg##_AR_BYTES, \
144 }
145
146static struct kvm_vmx_segment_field {
147 unsigned selector;
148 unsigned base;
149 unsigned limit;
150 unsigned ar_bytes;
151} kvm_vmx_segment_fields[] = {
152 VMX_SEGMENT_FIELD(CS),
153 VMX_SEGMENT_FIELD(DS),
154 VMX_SEGMENT_FIELD(ES),
155 VMX_SEGMENT_FIELD(FS),
156 VMX_SEGMENT_FIELD(GS),
157 VMX_SEGMENT_FIELD(SS),
158 VMX_SEGMENT_FIELD(TR),
159 VMX_SEGMENT_FIELD(LDTR),
160};
161
4d56c8a7
AK		 162/*
163 * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
164 * away by decrementing the array size.
165 */
6aa8b732 166static const u32 vmx_msr_index[] = {
05b3e0c2 167#ifdef CONFIG_X86_64
6aa8b732
AK		 168 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, MSR_KERNEL_GS_BASE,
169#endif
170 MSR_EFER, MSR_K6_STAR,
171};
9d8f549d 172#define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
6aa8b732 173
a2fa3e9f
GH		 174static void load_msrs(struct kvm_msr_entry *e, int n)
175{
176 int i;
177
178 for (i = 0; i < n; ++i)
179 wrmsrl(e[i].index, e[i].data);
180}
181
182static void save_msrs(struct kvm_msr_entry *e, int n)
183{
184 int i;
185
186 for (i = 0; i < n; ++i)
187 rdmsrl(e[i].index, e[i].data);
188}
189
6aa8b732
AK		 190static inline int is_page_fault(u32 intr_info)
191{
192 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
193 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 194 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 195}
196
2ab455cc
AL		 197static inline int is_no_device(u32 intr_info)
198{
199 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
200 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 201 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 202}
203
7aa81cc0
AL		 204static inline int is_invalid_opcode(u32 intr_info)
205{
206 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
207 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 208 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 209}
210
6aa8b732
AK		 211static inline int is_external_interrupt(u32 intr_info)
212{
213 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
214 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
215}
216
25c5f225
SY		 217static inline int cpu_has_vmx_msr_bitmap(void)
218{
04547156 219 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 220}
221
6e5d865c
YS		 222static inline int cpu_has_vmx_tpr_shadow(void)
223{
04547156 224 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 225}
226
227static inline int vm_need_tpr_shadow(struct kvm *kvm)
228{
04547156 229 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
6e5d865c
YS		 230}
231
f78e0e2e
SY		 232static inline int cpu_has_secondary_exec_ctrls(void)
233{
04547156
SY		 234 return vmcs_config.cpu_based_exec_ctrl &
235 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 236}
237
774ead3a 238static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 239{
04547156
SY		 240 return vmcs_config.cpu_based_2nd_exec_ctrl &
241 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
242}
243
244static inline bool cpu_has_vmx_flexpriority(void)
245{
246 return cpu_has_vmx_tpr_shadow() &&
247 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 248}
249
d56f546d
SY		 250static inline int cpu_has_vmx_invept_individual_addr(void)
251{
04547156 252 return !!(vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT);
d56f546d
SY		 253}
254
255static inline int cpu_has_vmx_invept_context(void)
256{
04547156 257 return !!(vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT);
d56f546d
SY		 258}
259
260static inline int cpu_has_vmx_invept_global(void)
261{
04547156 262 return !!(vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT);
d56f546d
SY		 263}
264
265static inline int cpu_has_vmx_ept(void)
266{
04547156
SY		 267 return vmcs_config.cpu_based_2nd_exec_ctrl &
268 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 269}
270
f78e0e2e
SY		 271static inline int vm_need_virtualize_apic_accesses(struct kvm *kvm)
272{
04547156
SY		 273 return flexpriority_enabled &&
274 (cpu_has_vmx_virtualize_apic_accesses()) &&
275 (irqchip_in_kernel(kvm));
f78e0e2e
SY		 276}
277
2384d2b3
SY		 278static inline int cpu_has_vmx_vpid(void)
279{
04547156
SY		 280 return vmcs_config.cpu_based_2nd_exec_ctrl &
281 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 282}
283
f08864b4
SY		 284static inline int cpu_has_virtual_nmis(void)
285{
286 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
287}
288
04547156
SY		 289static inline bool report_flexpriority(void)
290{
291 return flexpriority_enabled;
292}
293
8b9cf98c 294static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 295{
296 int i;
297
a2fa3e9f
GH		 298 for (i = 0; i < vmx->nmsrs; ++i)
299 if (vmx->guest_msrs[i].index == msr)
a75beee6
ED		 300 return i;
301 return -1;
302}
303
2384d2b3
SY		 304static inline void __invvpid(int ext, u16 vpid, gva_t gva)
305{
306 struct {
307 u64 vpid : 16;
308 u64 rsvd : 48;
309 u64 gva;
310 } operand = { vpid, 0, gva };
311
4ecac3fd 312 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 313 /* CF==1 or ZF==1 --> rc = -1 */
314 "; ja 1f ; ud2 ; 1:"
315 : : "a"(&operand), "c"(ext) : "cc", "memory");
316}
317
1439442c
SY		 318static inline void __invept(int ext, u64 eptp, gpa_t gpa)
319{
320 struct {
321 u64 eptp, gpa;
322 } operand = {eptp, gpa};
323
4ecac3fd 324 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 325 /* CF==1 or ZF==1 --> rc = -1 */
326 "; ja 1f ; ud2 ; 1:\n"
327 : : "a" (&operand), "c" (ext) : "cc", "memory");
328}
329
8b9cf98c 330static struct kvm_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 331{
332 int i;
333
8b9cf98c 334 i = __find_msr_index(vmx, msr);
a75beee6 335 if (i >= 0)
a2fa3e9f 336 return &vmx->guest_msrs[i];
8b6d44c7 337 return NULL;
7725f0ba
AK		 338}
339
6aa8b732
AK		 340static void vmcs_clear(struct vmcs *vmcs)
341{
342 u64 phys_addr = __pa(vmcs);
343 u8 error;
344
4ecac3fd 345 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
6aa8b732
AK		 346 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
347 : "cc", "memory");
348 if (error)
349 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
350 vmcs, phys_addr);
351}
352
353static void __vcpu_clear(void *arg)
354{
8b9cf98c 355 struct vcpu_vmx *vmx = arg;
d3b2c338 356 int cpu = raw_smp_processor_id();
6aa8b732 357
8b9cf98c 358 if (vmx->vcpu.cpu == cpu)
a2fa3e9f
GH		 359 vmcs_clear(vmx->vmcs);
360 if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
6aa8b732 361 per_cpu(current_vmcs, cpu) = NULL;
ad312c7c 362 rdtscll(vmx->vcpu.arch.host_tsc);
543e4243
AK		 363 list_del(&vmx->local_vcpus_link);
364 vmx->vcpu.cpu = -1;
365 vmx->launched = 0;
6aa8b732
AK		 366}
367
8b9cf98c 368static void vcpu_clear(struct vcpu_vmx *vmx)
8d0be2b3 369{
eae5ecb5
AK		 370 if (vmx->vcpu.cpu == -1)
371 return;
8691e5a8 372 smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1);
8d0be2b3
AK		 373}
374
2384d2b3
SY		 375static inline void vpid_sync_vcpu_all(struct vcpu_vmx *vmx)
376{
377 if (vmx->vpid == 0)
378 return;
379
380 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
381}
382
1439442c
SY		 383static inline void ept_sync_global(void)
384{
385 if (cpu_has_vmx_invept_global())
386 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
387}
388
389static inline void ept_sync_context(u64 eptp)
390{
089d034e 391 if (enable_ept) {
1439442c
SY		 392 if (cpu_has_vmx_invept_context())
393 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
394 else
395 ept_sync_global();
396 }
397}
398
399static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
400{
089d034e 401 if (enable_ept) {
1439442c
SY		 402 if (cpu_has_vmx_invept_individual_addr())
403 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
404 eptp, gpa);
405 else
406 ept_sync_context(eptp);
407 }
408}
409
6aa8b732
AK		 410static unsigned long vmcs_readl(unsigned long field)
411{
412 unsigned long value;
413
4ecac3fd 414 asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX)
6aa8b732
AK		 415 : "=a"(value) : "d"(field) : "cc");
416 return value;
417}
418
419static u16 vmcs_read16(unsigned long field)
420{
421 return vmcs_readl(field);
422}
423
424static u32 vmcs_read32(unsigned long field)
425{
426 return vmcs_readl(field);
427}
428
429static u64 vmcs_read64(unsigned long field)
430{
05b3e0c2 431#ifdef CONFIG_X86_64
6aa8b732
AK		 432 return vmcs_readl(field);
433#else
434 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
435#endif
436}
437
e52de1b8
AK		 438static noinline void vmwrite_error(unsigned long field, unsigned long value)
439{
440 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
441 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
442 dump_stack();
443}
444
6aa8b732
AK		 445static void vmcs_writel(unsigned long field, unsigned long value)
446{
447 u8 error;
448
4ecac3fd 449 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 450 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 451 if (unlikely(error))
452 vmwrite_error(field, value);
6aa8b732
AK		 453}
454
455static void vmcs_write16(unsigned long field, u16 value)
456{
457 vmcs_writel(field, value);
458}
459
460static void vmcs_write32(unsigned long field, u32 value)
461{
462 vmcs_writel(field, value);
463}
464
465static void vmcs_write64(unsigned long field, u64 value)
466{
6aa8b732 467 vmcs_writel(field, value);
7682f2d0 468#ifndef CONFIG_X86_64
6aa8b732
AK		 469 asm volatile ("");
470 vmcs_writel(field+1, value >> 32);
471#endif
472}
473
2ab455cc
AL		 474static void vmcs_clear_bits(unsigned long field, u32 mask)
475{
476 vmcs_writel(field, vmcs_readl(field) & ~mask);
477}
478
479static void vmcs_set_bits(unsigned long field, u32 mask)
480{
481 vmcs_writel(field, vmcs_readl(field) | mask);
482}
483
abd3f2d6
AK		 484static void update_exception_bitmap(struct kvm_vcpu *vcpu)
485{
486 u32 eb;
487
7aa81cc0 488 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR);
abd3f2d6
AK		 489 if (!vcpu->fpu_active)
490 eb |= 1u << NM_VECTOR;
d0bfb940
JK		 491 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
492 if (vcpu->guest_debug &
493 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
494 eb |= 1u << DB_VECTOR;
495 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
496 eb |= 1u << BP_VECTOR;
497 }
ad312c7c 498 if (vcpu->arch.rmode.active)
abd3f2d6 499 eb = ~0;
089d034e 500 if (enable_ept)
1439442c 501 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
abd3f2d6
AK		 502 vmcs_write32(EXCEPTION_BITMAP, eb);
503}
504
33ed6329
AK		 505static void reload_tss(void)
506{
33ed6329
AK		 507 /*
508 * VT restores TR but not its size. Useless.
509 */
510 struct descriptor_table gdt;
a5f61300 511 struct desc_struct *descs;
33ed6329 512
d6e88aec 513 kvm_get_gdt(&gdt);
33ed6329
AK		 514 descs = (void *)gdt.base;
515 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
516 load_TR_desc();
33ed6329
AK		 517}
518
8b9cf98c 519static void load_transition_efer(struct vcpu_vmx *vmx)
2cc51560 520{
a2fa3e9f 521 int efer_offset = vmx->msr_offset_efer;
51c6cf66
AK		 522 u64 host_efer = vmx->host_msrs[efer_offset].data;
523 u64 guest_efer = vmx->guest_msrs[efer_offset].data;
524 u64 ignore_bits;
525
526 if (efer_offset < 0)
527 return;
528 /*
529 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
530 * outside long mode
531 */
532 ignore_bits = EFER_NX | EFER_SCE;
533#ifdef CONFIG_X86_64
534 ignore_bits |= EFER_LMA | EFER_LME;
535 /* SCE is meaningful only in long mode on Intel */
536 if (guest_efer & EFER_LMA)
537 ignore_bits &= ~(u64)EFER_SCE;
538#endif
539 if ((guest_efer & ~ignore_bits) == (host_efer & ~ignore_bits))
540 return;
2cc51560 541
51c6cf66
AK		 542 vmx->host_state.guest_efer_loaded = 1;
543 guest_efer &= ~ignore_bits;
544 guest_efer |= host_efer & ignore_bits;
545 wrmsrl(MSR_EFER, guest_efer);
8b9cf98c 546 vmx->vcpu.stat.efer_reload++;
2cc51560
ED		 547}
548
51c6cf66
AK		 549static void reload_host_efer(struct vcpu_vmx *vmx)
550{
551 if (vmx->host_state.guest_efer_loaded) {
552 vmx->host_state.guest_efer_loaded = 0;
553 load_msrs(vmx->host_msrs + vmx->msr_offset_efer, 1);
554 }
555}
556
04d2cc77 557static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 558{
04d2cc77
AK		 559 struct vcpu_vmx *vmx = to_vmx(vcpu);
560
a2fa3e9f 561 if (vmx->host_state.loaded)
33ed6329
AK		 562 return;
563
a2fa3e9f 564 vmx->host_state.loaded = 1;
33ed6329
AK		 565 /*
566 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
567 * allow segment selectors with cpl > 0 or ti == 1.
568 */
d6e88aec 569 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 570 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
d6e88aec 571 vmx->host_state.fs_sel = kvm_read_fs();
152d3f2f 572 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 573 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 574 vmx->host_state.fs_reload_needed = 0;
575 } else {
33ed6329 576 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 577 vmx->host_state.fs_reload_needed = 1;
33ed6329 578 }
d6e88aec 579 vmx->host_state.gs_sel = kvm_read_gs();
a2fa3e9f
GH		 580 if (!(vmx->host_state.gs_sel & 7))
581 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 582 else {
583 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 584 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 585 }
586
587#ifdef CONFIG_X86_64
588 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
589 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
590#else
a2fa3e9f
GH		 591 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
592 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 593#endif
707c0874
AK		 594
595#ifdef CONFIG_X86_64
d77c26fc 596 if (is_long_mode(&vmx->vcpu))
a2fa3e9f
GH		 597 save_msrs(vmx->host_msrs +
598 vmx->msr_offset_kernel_gs_base, 1);
d77c26fc 599
707c0874 600#endif
a2fa3e9f 601 load_msrs(vmx->guest_msrs, vmx->save_nmsrs);
51c6cf66 602 load_transition_efer(vmx);
33ed6329
AK		 603}
604
a9b21b62 605static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 606{
15ad7146 607 unsigned long flags;
33ed6329 608
a2fa3e9f 609 if (!vmx->host_state.loaded)
33ed6329
AK		 610 return;
611
e1beb1d3 612 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 613 vmx->host_state.loaded = 0;
152d3f2f 614 if (vmx->host_state.fs_reload_needed)
d6e88aec 615 kvm_load_fs(vmx->host_state.fs_sel);
152d3f2f 616 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 617 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329
AK		 618 /*
619 * If we have to reload gs, we must take care to
620 * preserve our gs base.
621 */
15ad7146 622 local_irq_save(flags);
d6e88aec 623 kvm_load_gs(vmx->host_state.gs_sel);
33ed6329
AK		 624#ifdef CONFIG_X86_64
625 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
626#endif
15ad7146 627 local_irq_restore(flags);
33ed6329 628 }
152d3f2f 629 reload_tss();
a2fa3e9f
GH		 630 save_msrs(vmx->guest_msrs, vmx->save_nmsrs);
631 load_msrs(vmx->host_msrs, vmx->save_nmsrs);
51c6cf66 632 reload_host_efer(vmx);
33ed6329
AK		 633}
634
a9b21b62
AK		 635static void vmx_load_host_state(struct vcpu_vmx *vmx)
636{
637 preempt_disable();
638 __vmx_load_host_state(vmx);
639 preempt_enable();
640}
641
6aa8b732
AK		 642/*
643 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
644 * vcpu mutex is already taken.
645 */
15ad7146 646static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 647{
a2fa3e9f
GH		 648 struct vcpu_vmx *vmx = to_vmx(vcpu);
649 u64 phys_addr = __pa(vmx->vmcs);
019960ae 650 u64 tsc_this, delta, new_offset;
6aa8b732 651
a3d7f85f 652 if (vcpu->cpu != cpu) {
8b9cf98c 653 vcpu_clear(vmx);
2f599714 654 kvm_migrate_timers(vcpu);
2384d2b3 655 vpid_sync_vcpu_all(vmx);
543e4243
AK		 656 local_irq_disable();
657 list_add(&vmx->local_vcpus_link,
658 &per_cpu(vcpus_on_cpu, cpu));
659 local_irq_enable();
a3d7f85f 660 }
6aa8b732 661
a2fa3e9f 662 if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
6aa8b732
AK		 663 u8 error;
664
a2fa3e9f 665 per_cpu(current_vmcs, cpu) = vmx->vmcs;
4ecac3fd 666 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
6aa8b732
AK		 667 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
668 : "cc");
669 if (error)
670 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
a2fa3e9f 671 vmx->vmcs, phys_addr);
6aa8b732
AK		 672 }
673
674 if (vcpu->cpu != cpu) {
675 struct descriptor_table dt;
676 unsigned long sysenter_esp;
677
678 vcpu->cpu = cpu;
679 /*
680 * Linux uses per-cpu TSS and GDT, so set these when switching
681 * processors.
682 */
d6e88aec
AK		 683 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
684 kvm_get_gdt(&dt);
6aa8b732
AK		 685 vmcs_writel(HOST_GDTR_BASE, dt.base); /* 22.2.4 */
686
687 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
688 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
7700270e
AK		 689
690 /*
691 * Make sure the time stamp counter is monotonous.
692 */
693 rdtscll(tsc_this);
019960ae
AK		 694 if (tsc_this < vcpu->arch.host_tsc) {
695 delta = vcpu->arch.host_tsc - tsc_this;
696 new_offset = vmcs_read64(TSC_OFFSET) + delta;
697 vmcs_write64(TSC_OFFSET, new_offset);
698 }
6aa8b732 699 }
6aa8b732
AK		 700}
701
702static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
703{
a9b21b62 704 __vmx_load_host_state(to_vmx(vcpu));
6aa8b732
AK		 705}
706
5fd86fcf
AK		 707static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
708{
709 if (vcpu->fpu_active)
710 return;
711 vcpu->fpu_active = 1;
707d92fa 712 vmcs_clear_bits(GUEST_CR0, X86_CR0_TS);
ad312c7c 713 if (vcpu->arch.cr0 & X86_CR0_TS)
707d92fa 714 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
5fd86fcf
AK		 715 update_exception_bitmap(vcpu);
716}
717
718static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
719{
720 if (!vcpu->fpu_active)
721 return;
722 vcpu->fpu_active = 0;
707d92fa 723 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
5fd86fcf
AK		 724 update_exception_bitmap(vcpu);
725}
726
6aa8b732
AK		 727static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
728{
729 return vmcs_readl(GUEST_RFLAGS);
730}
731
732static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
733{
ad312c7c 734 if (vcpu->arch.rmode.active)
053de044 735 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 736 vmcs_writel(GUEST_RFLAGS, rflags);
737}
738
739static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
740{
741 unsigned long rip;
742 u32 interruptibility;
743
5fdbf976 744 rip = kvm_rip_read(vcpu);
6aa8b732 745 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 746 kvm_rip_write(vcpu, rip);
6aa8b732
AK		 747
748 /*
749 * We emulated an instruction, so temporary interrupt blocking
750 * should be removed, if set.
751 */
752 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
753 if (interruptibility & 3)
754 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
755 interruptibility & ~3);
ad312c7c 756 vcpu->arch.interrupt_window_open = 1;
6aa8b732
AK		 757}
758
298101da
AK		 759static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
760 bool has_error_code, u32 error_code)
761{
77ab6db0 762 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 763 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 764
8ab2d2e2 765 if (has_error_code) {
77ab6db0 766 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 767 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
768 }
77ab6db0
JK		 769
770 if (vcpu->arch.rmode.active) {
771 vmx->rmode.irq.pending = true;
772 vmx->rmode.irq.vector = nr;
773 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
8ab2d2e2 774 if (nr == BP_VECTOR || nr == OF_VECTOR)
77ab6db0 775 vmx->rmode.irq.rip++;
8ab2d2e2
JK		 776 intr_info |= INTR_TYPE_SOFT_INTR;
777 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
77ab6db0
JK		 778 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
779 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
780 return;
781 }
782
8ab2d2e2
JK		 783 if (nr == BP_VECTOR || nr == OF_VECTOR) {
784 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
785 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
786 } else
787 intr_info |= INTR_TYPE_HARD_EXCEPTION;
788
789 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
298101da
AK		 790}
791
a75beee6
ED		 792/*
793 * Swap MSR entry in host/guest MSR entry array.
794 */
54e11fa1 795#ifdef CONFIG_X86_64
8b9cf98c 796static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 797{
a2fa3e9f
GH		 798 struct kvm_msr_entry tmp;
799
800 tmp = vmx->guest_msrs[to];
801 vmx->guest_msrs[to] = vmx->guest_msrs[from];
802 vmx->guest_msrs[from] = tmp;
803 tmp = vmx->host_msrs[to];
804 vmx->host_msrs[to] = vmx->host_msrs[from];
805 vmx->host_msrs[from] = tmp;
a75beee6 806}
54e11fa1 807#endif
a75beee6 808
e38aea3e
AK		 809/*
810 * Set up the vmcs to automatically save and restore system
811 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
812 * mode, as fiddling with msrs is very expensive.
813 */
8b9cf98c 814static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 815{
2cc51560 816 int save_nmsrs;
5897297b 817 unsigned long *msr_bitmap;
e38aea3e 818
33f9c505 819 vmx_load_host_state(vmx);
a75beee6
ED		 820 save_nmsrs = 0;
821#ifdef CONFIG_X86_64
8b9cf98c 822 if (is_long_mode(&vmx->vcpu)) {
2cc51560
ED		 823 int index;
824
8b9cf98c 825 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 826 if (index >= 0)
8b9cf98c
RR		 827 move_msr_up(vmx, index, save_nmsrs++);
828 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 829 if (index >= 0)
8b9cf98c
RR		 830 move_msr_up(vmx, index, save_nmsrs++);
831 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 832 if (index >= 0)
8b9cf98c
RR		 833 move_msr_up(vmx, index, save_nmsrs++);
834 index = __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
a75beee6 835 if (index >= 0)
8b9cf98c 836 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 837 /*
838 * MSR_K6_STAR is only needed on long mode guests, and only
839 * if efer.sce is enabled.
840 */
8b9cf98c 841 index = __find_msr_index(vmx, MSR_K6_STAR);
ad312c7c 842 if ((index >= 0) && (vmx->vcpu.arch.shadow_efer & EFER_SCE))
8b9cf98c 843 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 844 }
845#endif
a2fa3e9f 846 vmx->save_nmsrs = save_nmsrs;
e38aea3e 847
4d56c8a7 848#ifdef CONFIG_X86_64
a2fa3e9f 849 vmx->msr_offset_kernel_gs_base =
8b9cf98c 850 __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
4d56c8a7 851#endif
8b9cf98c 852 vmx->msr_offset_efer = __find_msr_index(vmx, MSR_EFER);
5897297b
AK		 853
854 if (cpu_has_vmx_msr_bitmap()) {
855 if (is_long_mode(&vmx->vcpu))
856 msr_bitmap = vmx_msr_bitmap_longmode;
857 else
858 msr_bitmap = vmx_msr_bitmap_legacy;
859
860 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
861 }
e38aea3e
AK		 862}
863
6aa8b732
AK		 864/*
865 * reads and returns guest's timestamp counter "register"
866 * guest_tsc = host_tsc + tsc_offset -- 21.3
867 */
868static u64 guest_read_tsc(void)
869{
870 u64 host_tsc, tsc_offset;
871
872 rdtscll(host_tsc);
873 tsc_offset = vmcs_read64(TSC_OFFSET);
874 return host_tsc + tsc_offset;
875}
876
877/*
878 * writes 'guest_tsc' into guest's timestamp counter "register"
879 * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
880 */
53f658b3 881static void guest_write_tsc(u64 guest_tsc, u64 host_tsc)
6aa8b732 882{
6aa8b732
AK		 883 vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
884}
885
6aa8b732
AK		 886/*
887 * Reads an msr value (of 'msr_index') into 'pdata'.
888 * Returns 0 on success, non-0 otherwise.
889 * Assumes vcpu_load() was already called.
890 */
891static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
892{
893 u64 data;
a2fa3e9f 894 struct kvm_msr_entry *msr;
6aa8b732
AK		 895
896 if (!pdata) {
897 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
898 return -EINVAL;
899 }
900
901 switch (msr_index) {
05b3e0c2 902#ifdef CONFIG_X86_64
6aa8b732
AK		 903 case MSR_FS_BASE:
904 data = vmcs_readl(GUEST_FS_BASE);
905 break;
906 case MSR_GS_BASE:
907 data = vmcs_readl(GUEST_GS_BASE);
908 break;
909 case MSR_EFER:
3bab1f5d 910 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 911#endif
912 case MSR_IA32_TIME_STAMP_COUNTER:
913 data = guest_read_tsc();
914 break;
915 case MSR_IA32_SYSENTER_CS:
916 data = vmcs_read32(GUEST_SYSENTER_CS);
917 break;
918 case MSR_IA32_SYSENTER_EIP:
f5b42c33 919 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 920 break;
921 case MSR_IA32_SYSENTER_ESP:
f5b42c33 922 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 923 break;
6aa8b732 924 default:
516a1a7e 925 vmx_load_host_state(to_vmx(vcpu));
8b9cf98c 926 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d
AK		 927 if (msr) {
928 data = msr->data;
929 break;
6aa8b732 930 }
3bab1f5d 931 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 932 }
933
934 *pdata = data;
935 return 0;
936}
937
938/*
939 * Writes msr value into into the appropriate "register".
940 * Returns 0 on success, non-0 otherwise.
941 * Assumes vcpu_load() was already called.
942 */
943static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
944{
a2fa3e9f
GH		 945 struct vcpu_vmx *vmx = to_vmx(vcpu);
946 struct kvm_msr_entry *msr;
53f658b3 947 u64 host_tsc;
2cc51560
ED		 948 int ret = 0;
949
6aa8b732 950 switch (msr_index) {
3bab1f5d 951 case MSR_EFER:
a9b21b62 952 vmx_load_host_state(vmx);
2cc51560 953 ret = kvm_set_msr_common(vcpu, msr_index, data);
2cc51560 954 break;
16175a79 955#ifdef CONFIG_X86_64
6aa8b732
AK		 956 case MSR_FS_BASE:
957 vmcs_writel(GUEST_FS_BASE, data);
958 break;
959 case MSR_GS_BASE:
960 vmcs_writel(GUEST_GS_BASE, data);
961 break;
962#endif
963 case MSR_IA32_SYSENTER_CS:
964 vmcs_write32(GUEST_SYSENTER_CS, data);
965 break;
966 case MSR_IA32_SYSENTER_EIP:
f5b42c33 967 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 968 break;
969 case MSR_IA32_SYSENTER_ESP:
f5b42c33 970 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 971 break;
d27d4aca 972 case MSR_IA32_TIME_STAMP_COUNTER:
53f658b3
MT		 973 rdtscll(host_tsc);
974 guest_write_tsc(data, host_tsc);
efa67e0d
CL		 975 break;
976 case MSR_P6_PERFCTR0:
977 case MSR_P6_PERFCTR1:
978 case MSR_P6_EVNTSEL0:
979 case MSR_P6_EVNTSEL1:
980 /*
981 * Just discard all writes to the performance counters; this
982 * should keep both older linux and windows 64-bit guests
983 * happy
984 */
985 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: 0x%x data 0x%llx\n", msr_index, data);
986
6aa8b732 987 break;
468d472f
SY		 988 case MSR_IA32_CR_PAT:
989 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
990 vmcs_write64(GUEST_IA32_PAT, data);
991 vcpu->arch.pat = data;
992 break;
993 }
994 /* Otherwise falls through to kvm_set_msr_common */
6aa8b732 995 default:
a9b21b62 996 vmx_load_host_state(vmx);
8b9cf98c 997 msr = find_msr_entry(vmx, msr_index);
3bab1f5d
AK		 998 if (msr) {
999 msr->data = data;
1000 break;
6aa8b732 1001 }
2cc51560 1002 ret = kvm_set_msr_common(vcpu, msr_index, data);
6aa8b732
AK		 1003 }
1004
2cc51560 1005 return ret;
6aa8b732
AK		 1006}
1007
5fdbf976 1008static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 1009{
5fdbf976
MT		 1010 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
1011 switch (reg) {
1012 case VCPU_REGS_RSP:
1013 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
1014 break;
1015 case VCPU_REGS_RIP:
1016 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
1017 break;
1018 default:
1019 break;
1020 }
6aa8b732
AK		 1021}
1022
d0bfb940 1023static int set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
6aa8b732 1024{
d0bfb940
JK		 1025 int old_debug = vcpu->guest_debug;
1026 unsigned long flags;
6aa8b732 1027
d0bfb940
JK		 1028 vcpu->guest_debug = dbg->control;
1029 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
1030 vcpu->guest_debug = 0;
6aa8b732 1031
ae675ef0
JK		 1032 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1033 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
1034 else
1035 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
1036
d0bfb940
JK		 1037 flags = vmcs_readl(GUEST_RFLAGS);
1038 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
1039 flags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
1040 else if (old_debug & KVM_GUESTDBG_SINGLESTEP)
6aa8b732 1041 flags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
d0bfb940 1042 vmcs_writel(GUEST_RFLAGS, flags);
6aa8b732 1043
abd3f2d6 1044 update_exception_bitmap(vcpu);
6aa8b732
AK		 1045
1046 return 0;
1047}
1048
2a8067f1
ED		 1049static int vmx_get_irq(struct kvm_vcpu *vcpu)
1050{
f7d9238f
AK		 1051 if (!vcpu->arch.interrupt.pending)
1052 return -1;
1053 return vcpu->arch.interrupt.nr;
2a8067f1
ED		 1054}
1055
6aa8b732
AK		 1056static __init int cpu_has_kvm_support(void)
1057{
6210e37b 1058 return cpu_has_vmx();
6aa8b732
AK		 1059}
1060
1061static __init int vmx_disabled_by_bios(void)
1062{
1063 u64 msr;
1064
1065 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
9ea542fa
SY		 1066 return (msr & (FEATURE_CONTROL_LOCKED |
1067 FEATURE_CONTROL_VMXON_ENABLED))
1068 == FEATURE_CONTROL_LOCKED;
62b3ffb8 1069 /* locked but not enabled */
6aa8b732
AK		 1070}
1071
774c47f1 1072static void hardware_enable(void *garbage)
6aa8b732
AK		 1073{
1074 int cpu = raw_smp_processor_id();
1075 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1076 u64 old;
1077
543e4243 1078 INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu));
6aa8b732 1079 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
9ea542fa
SY		 1080 if ((old & (FEATURE_CONTROL_LOCKED |
1081 FEATURE_CONTROL_VMXON_ENABLED))
1082 != (FEATURE_CONTROL_LOCKED |
1083 FEATURE_CONTROL_VMXON_ENABLED))
6aa8b732 1084 /* enable and lock */
62b3ffb8 1085 wrmsrl(MSR_IA32_FEATURE_CONTROL, old |
9ea542fa
SY		 1086 FEATURE_CONTROL_LOCKED |
1087 FEATURE_CONTROL_VMXON_ENABLED);
66aee91a 1088 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
4ecac3fd
AK		 1089 asm volatile (ASM_VMX_VMXON_RAX
1090 : : "a"(&phys_addr), "m"(phys_addr)
6aa8b732
AK		 1091 : "memory", "cc");
1092}
1093
543e4243
AK		 1094static void vmclear_local_vcpus(void)
1095{
1096 int cpu = raw_smp_processor_id();
1097 struct vcpu_vmx *vmx, *n;
1098
1099 list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu),
1100 local_vcpus_link)
1101 __vcpu_clear(vmx);
1102}
1103
710ff4a8
EH		 1104
1105/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
1106 * tricks.
1107 */
1108static void kvm_cpu_vmxoff(void)
6aa8b732 1109{
4ecac3fd 1110 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
e693d71b 1111 write_cr4(read_cr4() & ~X86_CR4_VMXE);
6aa8b732
AK		 1112}
1113
710ff4a8
EH		 1114static void hardware_disable(void *garbage)
1115{
1116 vmclear_local_vcpus();
1117 kvm_cpu_vmxoff();
1118}
1119
1c3d14fe 1120static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 1121 u32 msr, u32 *result)
1c3d14fe
YS		 1122{
1123 u32 vmx_msr_low, vmx_msr_high;
1124 u32 ctl = ctl_min | ctl_opt;
1125
1126 rdmsr(msr, vmx_msr_low, vmx_msr_high);
1127
1128 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1129 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
1130
1131 /* Ensure minimum (required) set of control bits are supported. */
1132 if (ctl_min & ~ctl)
002c7f7c 1133 return -EIO;
1c3d14fe
YS		 1134
1135 *result = ctl;
1136 return 0;
1137}
1138
002c7f7c 1139static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 1140{
1141 u32 vmx_msr_low, vmx_msr_high;
d56f546d 1142 u32 min, opt, min2, opt2;
1c3d14fe
YS		 1143 u32 _pin_based_exec_control = 0;
1144 u32 _cpu_based_exec_control = 0;
f78e0e2e 1145 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 1146 u32 _vmexit_control = 0;
1147 u32 _vmentry_control = 0;
1148
1149 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
f08864b4 1150 opt = PIN_BASED_VIRTUAL_NMIS;
1c3d14fe
YS		 1151 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1152 &_pin_based_exec_control) < 0)
002c7f7c 1153 return -EIO;
1c3d14fe
YS		 1154
1155 min = CPU_BASED_HLT_EXITING |
1156#ifdef CONFIG_X86_64
1157 CPU_BASED_CR8_LOAD_EXITING |
1158 CPU_BASED_CR8_STORE_EXITING |
1159#endif
d56f546d
SY		 1160 CPU_BASED_CR3_LOAD_EXITING |
1161 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 1162 CPU_BASED_USE_IO_BITMAPS |
1163 CPU_BASED_MOV_DR_EXITING |
a7052897
MT		 1164 CPU_BASED_USE_TSC_OFFSETING |
1165 CPU_BASED_INVLPG_EXITING;
f78e0e2e 1166 opt = CPU_BASED_TPR_SHADOW |
25c5f225 1167 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 1168 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 1169 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1170 &_cpu_based_exec_control) < 0)
002c7f7c 1171 return -EIO;
6e5d865c
YS		 1172#ifdef CONFIG_X86_64
1173 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1174 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1175 ~CPU_BASED_CR8_STORE_EXITING;
1176#endif
f78e0e2e 1177 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 1178 min2 = 0;
1179 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2384d2b3 1180 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d
SY		 1181 SECONDARY_EXEC_ENABLE_VPID |
1182 SECONDARY_EXEC_ENABLE_EPT;
1183 if (adjust_vmx_controls(min2, opt2,
1184 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 1185 &_cpu_based_2nd_exec_control) < 0)
1186 return -EIO;
1187 }
1188#ifndef CONFIG_X86_64
1189 if (!(_cpu_based_2nd_exec_control &
1190 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1191 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1192#endif
d56f546d 1193 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 1194 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
1195 enabled */
d56f546d 1196 min &= ~(CPU_BASED_CR3_LOAD_EXITING |
a7052897
MT		 1197 CPU_BASED_CR3_STORE_EXITING |
1198 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 1199 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1200 &_cpu_based_exec_control) < 0)
1201 return -EIO;
1202 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1203 vmx_capability.ept, vmx_capability.vpid);
1204 }
1c3d14fe
YS		 1205
1206 min = 0;
1207#ifdef CONFIG_X86_64
1208 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1209#endif
468d472f 1210 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1c3d14fe
YS		 1211 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1212 &_vmexit_control) < 0)
002c7f7c 1213 return -EIO;
1c3d14fe 1214
468d472f
SY		 1215 min = 0;
1216 opt = VM_ENTRY_LOAD_IA32_PAT;
1c3d14fe
YS		 1217 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1218 &_vmentry_control) < 0)
002c7f7c 1219 return -EIO;
6aa8b732 1220
c68876fd 1221 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 1222
1223 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1224 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 1225 return -EIO;
1c3d14fe
YS		 1226
1227#ifdef CONFIG_X86_64
1228 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1229 if (vmx_msr_high & (1u<<16))
002c7f7c 1230 return -EIO;
1c3d14fe
YS		 1231#endif
1232
1233 /* Require Write-Back (WB) memory type for VMCS accesses. */
1234 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 1235 return -EIO;
1c3d14fe 1236
002c7f7c
YS		 1237 vmcs_conf->size = vmx_msr_high & 0x1fff;
1238 vmcs_conf->order = get_order(vmcs_config.size);
1239 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 1240
002c7f7c
YS		 1241 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1242 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 1243 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 1244 vmcs_conf->vmexit_ctrl = _vmexit_control;
1245 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe
YS		 1246
1247 return 0;
c68876fd 1248}
6aa8b732
AK		 1249
1250static struct vmcs *alloc_vmcs_cpu(int cpu)
1251{
1252 int node = cpu_to_node(cpu);
1253 struct page *pages;
1254 struct vmcs *vmcs;
1255
1c3d14fe 1256 pages = alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 1257 if (!pages)
1258 return NULL;
1259 vmcs = page_address(pages);
1c3d14fe
YS		 1260 memset(vmcs, 0, vmcs_config.size);
1261 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 1262 return vmcs;
1263}
1264
1265static struct vmcs *alloc_vmcs(void)
1266{
d3b2c338 1267 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 1268}
1269
1270static void free_vmcs(struct vmcs *vmcs)
1271{
1c3d14fe 1272 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 1273}
1274
39959588 1275static void free_kvm_area(void)
6aa8b732
AK		 1276{
1277 int cpu;
1278
1279 for_each_online_cpu(cpu)
1280 free_vmcs(per_cpu(vmxarea, cpu));
1281}
1282
6aa8b732
AK		 1283static __init int alloc_kvm_area(void)
1284{
1285 int cpu;
1286
1287 for_each_online_cpu(cpu) {
1288 struct vmcs *vmcs;
1289
1290 vmcs = alloc_vmcs_cpu(cpu);
1291 if (!vmcs) {
1292 free_kvm_area();
1293 return -ENOMEM;
1294 }
1295
1296 per_cpu(vmxarea, cpu) = vmcs;
1297 }
1298 return 0;
1299}
1300
1301static __init int hardware_setup(void)
1302{
002c7f7c
YS		 1303 if (setup_vmcs_config(&vmcs_config) < 0)
1304 return -EIO;
50a37eb4
JR		 1305
1306 if (boot_cpu_has(X86_FEATURE_NX))
1307 kvm_enable_efer_bits(EFER_NX);
1308
93ba03c2
SY		 1309 if (!cpu_has_vmx_vpid())
1310 enable_vpid = 0;
1311
1312 if (!cpu_has_vmx_ept())
1313 enable_ept = 0;
1314
1315 if (!cpu_has_vmx_flexpriority())
1316 flexpriority_enabled = 0;
1317
6aa8b732
AK		 1318 return alloc_kvm_area();
1319}
1320
1321static __exit void hardware_unsetup(void)
1322{
1323 free_kvm_area();
1324}
1325
6aa8b732
AK		 1326static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1327{
1328 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1329
6af11b9e 1330 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
6aa8b732
AK		 1331 vmcs_write16(sf->selector, save->selector);
1332 vmcs_writel(sf->base, save->base);
1333 vmcs_write32(sf->limit, save->limit);
1334 vmcs_write32(sf->ar_bytes, save->ar);
1335 } else {
1336 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1337 << AR_DPL_SHIFT;
1338 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1339 }
1340}
1341
1342static void enter_pmode(struct kvm_vcpu *vcpu)
1343{
1344 unsigned long flags;
a89a8fb9 1345 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 1346
a89a8fb9 1347 vmx->emulation_required = 1;
ad312c7c 1348 vcpu->arch.rmode.active = 0;
6aa8b732 1349
ad312c7c
ZX		 1350 vmcs_writel(GUEST_TR_BASE, vcpu->arch.rmode.tr.base);
1351 vmcs_write32(GUEST_TR_LIMIT, vcpu->arch.rmode.tr.limit);
1352 vmcs_write32(GUEST_TR_AR_BYTES, vcpu->arch.rmode.tr.ar);
6aa8b732
AK		 1353
1354 flags = vmcs_readl(GUEST_RFLAGS);
053de044 1355 flags &= ~(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
ad312c7c 1356 flags |= (vcpu->arch.rmode.save_iopl << IOPL_SHIFT);
6aa8b732
AK		 1357 vmcs_writel(GUEST_RFLAGS, flags);
1358
66aee91a
RR		 1359 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1360 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 1361
1362 update_exception_bitmap(vcpu);
1363
a89a8fb9
MG		 1364 if (emulate_invalid_guest_state)
1365 return;
1366
ad312c7c
ZX		 1367 fix_pmode_dataseg(VCPU_SREG_ES, &vcpu->arch.rmode.es);
1368 fix_pmode_dataseg(VCPU_SREG_DS, &vcpu->arch.rmode.ds);
1369 fix_pmode_dataseg(VCPU_SREG_GS, &vcpu->arch.rmode.gs);
1370 fix_pmode_dataseg(VCPU_SREG_FS, &vcpu->arch.rmode.fs);
6aa8b732
AK		 1371
1372 vmcs_write16(GUEST_SS_SELECTOR, 0);
1373 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1374
1375 vmcs_write16(GUEST_CS_SELECTOR,
1376 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1377 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1378}
1379
d77c26fc 1380static gva_t rmode_tss_base(struct kvm *kvm)
6aa8b732 1381{
bfc6d222 1382 if (!kvm->arch.tss_addr) {
cbc94022
IE		 1383 gfn_t base_gfn = kvm->memslots[0].base_gfn +
1384 kvm->memslots[0].npages - 3;
1385 return base_gfn << PAGE_SHIFT;
1386 }
bfc6d222 1387 return kvm->arch.tss_addr;
6aa8b732
AK		 1388}
1389
1390static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1391{
1392 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1393
1394 save->selector = vmcs_read16(sf->selector);
1395 save->base = vmcs_readl(sf->base);
1396 save->limit = vmcs_read32(sf->limit);
1397 save->ar = vmcs_read32(sf->ar_bytes);
15b00f32
JK		 1398 vmcs_write16(sf->selector, save->base >> 4);
1399 vmcs_write32(sf->base, save->base & 0xfffff);
6aa8b732
AK		 1400 vmcs_write32(sf->limit, 0xffff);
1401 vmcs_write32(sf->ar_bytes, 0xf3);
1402}
1403
1404static void enter_rmode(struct kvm_vcpu *vcpu)
1405{
1406 unsigned long flags;
a89a8fb9 1407 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 1408
a89a8fb9 1409 vmx->emulation_required = 1;
ad312c7c 1410 vcpu->arch.rmode.active = 1;
6aa8b732 1411
ad312c7c 1412 vcpu->arch.rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
6aa8b732
AK		 1413 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1414
ad312c7c 1415 vcpu->arch.rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
6aa8b732
AK		 1416 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1417
ad312c7c 1418 vcpu->arch.rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
6aa8b732
AK		 1419 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1420
1421 flags = vmcs_readl(GUEST_RFLAGS);
ad312c7c
ZX		 1422 vcpu->arch.rmode.save_iopl
1423 = (flags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
6aa8b732 1424
053de044 1425 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 1426
1427 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 1428 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 1429 update_exception_bitmap(vcpu);
1430
a89a8fb9
MG		 1431 if (emulate_invalid_guest_state)
1432 goto continue_rmode;
1433
6aa8b732
AK		 1434 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1435 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1436 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1437
1438 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
abacf8df 1439 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
8cb5b033
AK		 1440 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1441 vmcs_writel(GUEST_CS_BASE, 0xf0000);
6aa8b732
AK		 1442 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1443
ad312c7c
ZX		 1444 fix_rmode_seg(VCPU_SREG_ES, &vcpu->arch.rmode.es);
1445 fix_rmode_seg(VCPU_SREG_DS, &vcpu->arch.rmode.ds);
1446 fix_rmode_seg(VCPU_SREG_GS, &vcpu->arch.rmode.gs);
1447 fix_rmode_seg(VCPU_SREG_FS, &vcpu->arch.rmode.fs);
75880a01 1448
a89a8fb9 1449continue_rmode:
8668a3c4 1450 kvm_mmu_reset_context(vcpu);
b7ebfb05 1451 init_rmode(vcpu->kvm);
6aa8b732
AK		 1452}
1453
401d10de
AS		 1454static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1455{
1456 struct vcpu_vmx *vmx = to_vmx(vcpu);
1457 struct kvm_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1458
1459 vcpu->arch.shadow_efer = efer;
1460 if (!msr)
1461 return;
1462 if (efer & EFER_LMA) {
1463 vmcs_write32(VM_ENTRY_CONTROLS,
1464 vmcs_read32(VM_ENTRY_CONTROLS) |
1465 VM_ENTRY_IA32E_MODE);
1466 msr->data = efer;
1467 } else {
1468 vmcs_write32(VM_ENTRY_CONTROLS,
1469 vmcs_read32(VM_ENTRY_CONTROLS) &
1470 ~VM_ENTRY_IA32E_MODE);
1471
1472 msr->data = efer & ~EFER_LME;
1473 }
1474 setup_msrs(vmx);
1475}
1476
05b3e0c2 1477#ifdef CONFIG_X86_64
6aa8b732
AK		 1478
1479static void enter_lmode(struct kvm_vcpu *vcpu)
1480{
1481 u32 guest_tr_ar;
1482
1483 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1484 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1485 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
b8688d51 1486 __func__);
6aa8b732
AK		 1487 vmcs_write32(GUEST_TR_AR_BYTES,
1488 (guest_tr_ar & ~AR_TYPE_MASK)
1489 | AR_TYPE_BUSY_64_TSS);
1490 }
ad312c7c 1491 vcpu->arch.shadow_efer |= EFER_LMA;
401d10de 1492 vmx_set_efer(vcpu, vcpu->arch.shadow_efer);
6aa8b732
AK		 1493}
1494
1495static void exit_lmode(struct kvm_vcpu *vcpu)
1496{
ad312c7c 1497 vcpu->arch.shadow_efer &= ~EFER_LMA;
6aa8b732
AK		 1498
1499 vmcs_write32(VM_ENTRY_CONTROLS,
1500 vmcs_read32(VM_ENTRY_CONTROLS)
1e4e6e00 1501 & ~VM_ENTRY_IA32E_MODE);
6aa8b732
AK		 1502}
1503
1504#endif
1505
2384d2b3
SY		 1506static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1507{
1508 vpid_sync_vcpu_all(to_vmx(vcpu));
089d034e 1509 if (enable_ept)
4e1096d2 1510 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
2384d2b3
SY		 1511}
1512
25c4c276 1513static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 1514{
ad312c7c
ZX		 1515 vcpu->arch.cr4 &= KVM_GUEST_CR4_MASK;
1516 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & ~KVM_GUEST_CR4_MASK;
399badf3
AK		 1517}
1518
1439442c
SY		 1519static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
1520{
1521 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1522 if (!load_pdptrs(vcpu, vcpu->arch.cr3)) {
1523 printk(KERN_ERR "EPT: Fail to load pdptrs!\n");
1524 return;
1525 }
1526 vmcs_write64(GUEST_PDPTR0, vcpu->arch.pdptrs[0]);
1527 vmcs_write64(GUEST_PDPTR1, vcpu->arch.pdptrs[1]);
1528 vmcs_write64(GUEST_PDPTR2, vcpu->arch.pdptrs[2]);
1529 vmcs_write64(GUEST_PDPTR3, vcpu->arch.pdptrs[3]);
1530 }
1531}
1532
1533static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1534
1535static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
1536 unsigned long cr0,
1537 struct kvm_vcpu *vcpu)
1538{
1539 if (!(cr0 & X86_CR0_PG)) {
1540 /* From paging/starting to nonpaging */
1541 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 1542 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 1543 (CPU_BASED_CR3_LOAD_EXITING |
1544 CPU_BASED_CR3_STORE_EXITING));
1545 vcpu->arch.cr0 = cr0;
1546 vmx_set_cr4(vcpu, vcpu->arch.cr4);
1547 *hw_cr0 |= X86_CR0_PE | X86_CR0_PG;
1548 *hw_cr0 &= ~X86_CR0_WP;
1549 } else if (!is_paging(vcpu)) {
1550 /* From nonpaging to paging */
1551 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 1552 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 1553 ~(CPU_BASED_CR3_LOAD_EXITING |
1554 CPU_BASED_CR3_STORE_EXITING));
1555 vcpu->arch.cr0 = cr0;
1556 vmx_set_cr4(vcpu, vcpu->arch.cr4);
1557 if (!(vcpu->arch.cr0 & X86_CR0_WP))
1558 *hw_cr0 &= ~X86_CR0_WP;
1559 }
1560}
1561
1562static void ept_update_paging_mode_cr4(unsigned long *hw_cr4,
1563 struct kvm_vcpu *vcpu)
1564{
1565 if (!is_paging(vcpu)) {
1566 *hw_cr4 &= ~X86_CR4_PAE;
1567 *hw_cr4 |= X86_CR4_PSE;
1568 } else if (!(vcpu->arch.cr4 & X86_CR4_PAE))
1569 *hw_cr4 &= ~X86_CR4_PAE;
1570}
1571
6aa8b732
AK		 1572static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1573{
1439442c
SY		 1574 unsigned long hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) |
1575 KVM_VM_CR0_ALWAYS_ON;
1576
5fd86fcf
AK		 1577 vmx_fpu_deactivate(vcpu);
1578
ad312c7c 1579 if (vcpu->arch.rmode.active && (cr0 & X86_CR0_PE))
6aa8b732
AK		 1580 enter_pmode(vcpu);
1581
ad312c7c 1582 if (!vcpu->arch.rmode.active && !(cr0 & X86_CR0_PE))
6aa8b732
AK		 1583 enter_rmode(vcpu);
1584
05b3e0c2 1585#ifdef CONFIG_X86_64
ad312c7c 1586 if (vcpu->arch.shadow_efer & EFER_LME) {
707d92fa 1587 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 1588 enter_lmode(vcpu);
707d92fa 1589 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 1590 exit_lmode(vcpu);
1591 }
1592#endif
1593
089d034e 1594 if (enable_ept)
1439442c
SY		 1595 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
1596
6aa8b732 1597 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 1598 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 1599 vcpu->arch.cr0 = cr0;
5fd86fcf 1600
707d92fa 1601 if (!(cr0 & X86_CR0_TS) || !(cr0 & X86_CR0_PE))
5fd86fcf 1602 vmx_fpu_activate(vcpu);
6aa8b732
AK		 1603}
1604
1439442c
SY		 1605static u64 construct_eptp(unsigned long root_hpa)
1606{
1607 u64 eptp;
1608
1609 /* TODO write the value reading from MSR */
1610 eptp = VMX_EPT_DEFAULT_MT |
1611 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
1612 eptp |= (root_hpa & PAGE_MASK);
1613
1614 return eptp;
1615}
1616
6aa8b732
AK		 1617static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1618{
1439442c
SY		 1619 unsigned long guest_cr3;
1620 u64 eptp;
1621
1622 guest_cr3 = cr3;
089d034e 1623 if (enable_ept) {
1439442c
SY		 1624 eptp = construct_eptp(cr3);
1625 vmcs_write64(EPT_POINTER, eptp);
1626 ept_sync_context(eptp);
1627 ept_load_pdptrs(vcpu);
1628 guest_cr3 = is_paging(vcpu) ? vcpu->arch.cr3 :
1629 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
1630 }
1631
2384d2b3 1632 vmx_flush_tlb(vcpu);
1439442c 1633 vmcs_writel(GUEST_CR3, guest_cr3);
ad312c7c 1634 if (vcpu->arch.cr0 & X86_CR0_PE)
5fd86fcf 1635 vmx_fpu_deactivate(vcpu);
6aa8b732
AK		 1636}
1637
1638static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1639{
1439442c
SY		 1640 unsigned long hw_cr4 = cr4 | (vcpu->arch.rmode.active ?
1641 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1642
ad312c7c 1643 vcpu->arch.cr4 = cr4;
089d034e 1644 if (enable_ept)
1439442c
SY		 1645 ept_update_paging_mode_cr4(&hw_cr4, vcpu);
1646
1647 vmcs_writel(CR4_READ_SHADOW, cr4);
1648 vmcs_writel(GUEST_CR4, hw_cr4);
6aa8b732
AK		 1649}
1650
6aa8b732
AK		 1651static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1652{
1653 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1654
1655 return vmcs_readl(sf->base);
1656}
1657
1658static void vmx_get_segment(struct kvm_vcpu *vcpu,
1659 struct kvm_segment *var, int seg)
1660{
1661 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1662 u32 ar;
1663
1664 var->base = vmcs_readl(sf->base);
1665 var->limit = vmcs_read32(sf->limit);
1666 var->selector = vmcs_read16(sf->selector);
1667 ar = vmcs_read32(sf->ar_bytes);
9fd4a3b7 1668 if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
6aa8b732
AK		 1669 ar = 0;
1670 var->type = ar & 15;
1671 var->s = (ar >> 4) & 1;
1672 var->dpl = (ar >> 5) & 3;
1673 var->present = (ar >> 7) & 1;
1674 var->avl = (ar >> 12) & 1;
1675 var->l = (ar >> 13) & 1;
1676 var->db = (ar >> 14) & 1;
1677 var->g = (ar >> 15) & 1;
1678 var->unusable = (ar >> 16) & 1;
1679}
1680
2e4d2653
IE		 1681static int vmx_get_cpl(struct kvm_vcpu *vcpu)
1682{
1683 struct kvm_segment kvm_seg;
1684
1685 if (!(vcpu->arch.cr0 & X86_CR0_PE)) /* if real mode */
1686 return 0;
1687
1688 if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */
1689 return 3;
1690
1691 vmx_get_segment(vcpu, &kvm_seg, VCPU_SREG_CS);
1692 return kvm_seg.selector & 3;
1693}
1694
653e3108 1695static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 1696{
6aa8b732
AK		 1697 u32 ar;
1698
653e3108 1699 if (var->unusable)
6aa8b732
AK		 1700 ar = 1 << 16;
1701 else {
1702 ar = var->type & 15;
1703 ar |= (var->s & 1) << 4;
1704 ar |= (var->dpl & 3) << 5;
1705 ar |= (var->present & 1) << 7;
1706 ar |= (var->avl & 1) << 12;
1707 ar |= (var->l & 1) << 13;
1708 ar |= (var->db & 1) << 14;
1709 ar |= (var->g & 1) << 15;
1710 }
f7fbf1fd
UL		 1711 if (ar == 0) /* a 0 value means unusable */
1712 ar = AR_UNUSABLE_MASK;
653e3108
AK		 1713
1714 return ar;
1715}
1716
1717static void vmx_set_segment(struct kvm_vcpu *vcpu,
1718 struct kvm_segment *var, int seg)
1719{
1720 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1721 u32 ar;
1722
ad312c7c
ZX		 1723 if (vcpu->arch.rmode.active && seg == VCPU_SREG_TR) {
1724 vcpu->arch.rmode.tr.selector = var->selector;
1725 vcpu->arch.rmode.tr.base = var->base;
1726 vcpu->arch.rmode.tr.limit = var->limit;
1727 vcpu->arch.rmode.tr.ar = vmx_segment_access_rights(var);
653e3108
AK		 1728 return;
1729 }
1730 vmcs_writel(sf->base, var->base);
1731 vmcs_write32(sf->limit, var->limit);
1732 vmcs_write16(sf->selector, var->selector);
ad312c7c 1733 if (vcpu->arch.rmode.active && var->s) {
653e3108
AK		 1734 /*
1735 * Hack real-mode segments into vm86 compatibility.
1736 */
1737 if (var->base == 0xffff0000 && var->selector == 0xf000)
1738 vmcs_writel(sf->base, 0xf0000);
1739 ar = 0xf3;
1740 } else
1741 ar = vmx_segment_access_rights(var);
6aa8b732
AK		 1742 vmcs_write32(sf->ar_bytes, ar);
1743}
1744
6aa8b732
AK		 1745static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
1746{
1747 u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
1748
1749 *db = (ar >> 14) & 1;
1750 *l = (ar >> 13) & 1;
1751}
1752
1753static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1754{
1755 dt->limit = vmcs_read32(GUEST_IDTR_LIMIT);
1756 dt->base = vmcs_readl(GUEST_IDTR_BASE);
1757}
1758
1759static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1760{
1761 vmcs_write32(GUEST_IDTR_LIMIT, dt->limit);
1762 vmcs_writel(GUEST_IDTR_BASE, dt->base);
1763}
1764
1765static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1766{
1767 dt->limit = vmcs_read32(GUEST_GDTR_LIMIT);
1768 dt->base = vmcs_readl(GUEST_GDTR_BASE);
1769}
1770
1771static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1772{
1773 vmcs_write32(GUEST_GDTR_LIMIT, dt->limit);
1774 vmcs_writel(GUEST_GDTR_BASE, dt->base);
1775}
1776
648dfaa7
MG		 1777static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
1778{
1779 struct kvm_segment var;
1780 u32 ar;
1781
1782 vmx_get_segment(vcpu, &var, seg);
1783 ar = vmx_segment_access_rights(&var);
1784
1785 if (var.base != (var.selector << 4))
1786 return false;
1787 if (var.limit != 0xffff)
1788 return false;
1789 if (ar != 0xf3)
1790 return false;
1791
1792 return true;
1793}
1794
1795static bool code_segment_valid(struct kvm_vcpu *vcpu)
1796{
1797 struct kvm_segment cs;
1798 unsigned int cs_rpl;
1799
1800 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
1801 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
1802
1872a3f4
AK		 1803 if (cs.unusable)
1804 return false;
648dfaa7
MG		 1805 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
1806 return false;
1807 if (!cs.s)
1808 return false;
1872a3f4 1809 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 1810 if (cs.dpl > cs_rpl)
1811 return false;
1872a3f4 1812 } else {
648dfaa7
MG		 1813 if (cs.dpl != cs_rpl)
1814 return false;
1815 }
1816 if (!cs.present)
1817 return false;
1818
1819 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
1820 return true;
1821}
1822
1823static bool stack_segment_valid(struct kvm_vcpu *vcpu)
1824{
1825 struct kvm_segment ss;
1826 unsigned int ss_rpl;
1827
1828 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
1829 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
1830
1872a3f4
AK		 1831 if (ss.unusable)
1832 return true;
1833 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 1834 return false;
1835 if (!ss.s)
1836 return false;
1837 if (ss.dpl != ss_rpl) /* DPL != RPL */
1838 return false;
1839 if (!ss.present)
1840 return false;
1841
1842 return true;
1843}
1844
1845static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
1846{
1847 struct kvm_segment var;
1848 unsigned int rpl;
1849
1850 vmx_get_segment(vcpu, &var, seg);
1851 rpl = var.selector & SELECTOR_RPL_MASK;
1852
1872a3f4
AK		 1853 if (var.unusable)
1854 return true;
648dfaa7
MG		 1855 if (!var.s)
1856 return false;
1857 if (!var.present)
1858 return false;
1859 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
1860 if (var.dpl < rpl) /* DPL < RPL */
1861 return false;
1862 }
1863
1864 /* TODO: Add other members to kvm_segment_field to allow checking for other access
1865 * rights flags
1866 */
1867 return true;
1868}
1869
1870static bool tr_valid(struct kvm_vcpu *vcpu)
1871{
1872 struct kvm_segment tr;
1873
1874 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
1875
1872a3f4
AK		 1876 if (tr.unusable)
1877 return false;
648dfaa7
MG		 1878 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
1879 return false;
1872a3f4 1880 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 1881 return false;
1882 if (!tr.present)
1883 return false;
1884
1885 return true;
1886}
1887
1888static bool ldtr_valid(struct kvm_vcpu *vcpu)
1889{
1890 struct kvm_segment ldtr;
1891
1892 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
1893
1872a3f4
AK		 1894 if (ldtr.unusable)
1895 return true;
648dfaa7
MG		 1896 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
1897 return false;
1898 if (ldtr.type != 2)
1899 return false;
1900 if (!ldtr.present)
1901 return false;
1902
1903 return true;
1904}
1905
1906static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
1907{
1908 struct kvm_segment cs, ss;
1909
1910 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
1911 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
1912
1913 return ((cs.selector & SELECTOR_RPL_MASK) ==
1914 (ss.selector & SELECTOR_RPL_MASK));
1915}
1916
1917/*
1918 * Check if guest state is valid. Returns true if valid, false if
1919 * not.
1920 * We assume that registers are always usable
1921 */
1922static bool guest_state_valid(struct kvm_vcpu *vcpu)
1923{
1924 /* real mode guest state checks */
1925 if (!(vcpu->arch.cr0 & X86_CR0_PE)) {
1926 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
1927 return false;
1928 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
1929 return false;
1930 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
1931 return false;
1932 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
1933 return false;
1934 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
1935 return false;
1936 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
1937 return false;
1938 } else {
1939 /* protected mode guest state checks */
1940 if (!cs_ss_rpl_check(vcpu))
1941 return false;
1942 if (!code_segment_valid(vcpu))
1943 return false;
1944 if (!stack_segment_valid(vcpu))
1945 return false;
1946 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
1947 return false;
1948 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
1949 return false;
1950 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
1951 return false;
1952 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
1953 return false;
1954 if (!tr_valid(vcpu))
1955 return false;
1956 if (!ldtr_valid(vcpu))
1957 return false;
1958 }
1959 /* TODO:
1960 * - Add checks on RIP
1961 * - Add checks on RFLAGS
1962 */
1963
1964 return true;
1965}
1966
d77c26fc 1967static int init_rmode_tss(struct kvm *kvm)
6aa8b732 1968{
6aa8b732 1969 gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
195aefde 1970 u16 data = 0;
10589a46 1971 int ret = 0;
195aefde 1972 int r;
6aa8b732 1973
195aefde
IE		 1974 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
1975 if (r < 0)
10589a46 1976 goto out;
195aefde 1977 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 1978 r = kvm_write_guest_page(kvm, fn++, &data,
1979 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 1980 if (r < 0)
10589a46 1981 goto out;
195aefde
IE		 1982 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
1983 if (r < 0)
10589a46 1984 goto out;
195aefde
IE		 1985 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
1986 if (r < 0)
10589a46 1987 goto out;
195aefde 1988 data = ~0;
10589a46
MT		 1989 r = kvm_write_guest_page(kvm, fn, &data,
1990 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
1991 sizeof(u8));
195aefde 1992 if (r < 0)
10589a46
MT		 1993 goto out;
1994
1995 ret = 1;
1996out:
10589a46 1997 return ret;
6aa8b732
AK		 1998}
1999
b7ebfb05
SY		 2000static int init_rmode_identity_map(struct kvm *kvm)
2001{
2002 int i, r, ret;
2003 pfn_t identity_map_pfn;
2004 u32 tmp;
2005
089d034e 2006 if (!enable_ept)
b7ebfb05
SY		 2007 return 1;
2008 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
2009 printk(KERN_ERR "EPT: identity-mapping pagetable "
2010 "haven't been allocated!\n");
2011 return 0;
2012 }
2013 if (likely(kvm->arch.ept_identity_pagetable_done))
2014 return 1;
2015 ret = 0;
2016 identity_map_pfn = VMX_EPT_IDENTITY_PAGETABLE_ADDR >> PAGE_SHIFT;
2017 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
2018 if (r < 0)
2019 goto out;
2020 /* Set up identity-mapping pagetable for EPT in real mode */
2021 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
2022 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
2023 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
2024 r = kvm_write_guest_page(kvm, identity_map_pfn,
2025 &tmp, i * sizeof(tmp), sizeof(tmp));
2026 if (r < 0)
2027 goto out;
2028 }
2029 kvm->arch.ept_identity_pagetable_done = true;
2030 ret = 1;
2031out:
2032 return ret;
2033}
2034
6aa8b732
AK		 2035static void seg_setup(int seg)
2036{
2037 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2038
2039 vmcs_write16(sf->selector, 0);
2040 vmcs_writel(sf->base, 0);
2041 vmcs_write32(sf->limit, 0xffff);
a16b20da 2042 vmcs_write32(sf->ar_bytes, 0xf3);
6aa8b732
AK		 2043}
2044
f78e0e2e
SY		 2045static int alloc_apic_access_page(struct kvm *kvm)
2046{
2047 struct kvm_userspace_memory_region kvm_userspace_mem;
2048 int r = 0;
2049
72dc67a6 2050 down_write(&kvm->slots_lock);
bfc6d222 2051 if (kvm->arch.apic_access_page)
f78e0e2e
SY		 2052 goto out;
2053 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
2054 kvm_userspace_mem.flags = 0;
2055 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
2056 kvm_userspace_mem.memory_size = PAGE_SIZE;
2057 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2058 if (r)
2059 goto out;
72dc67a6 2060
bfc6d222 2061 kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
f78e0e2e 2062out:
72dc67a6 2063 up_write(&kvm->slots_lock);
f78e0e2e
SY		 2064 return r;
2065}
2066
b7ebfb05
SY		 2067static int alloc_identity_pagetable(struct kvm *kvm)
2068{
2069 struct kvm_userspace_memory_region kvm_userspace_mem;
2070 int r = 0;
2071
2072 down_write(&kvm->slots_lock);
2073 if (kvm->arch.ept_identity_pagetable)
2074 goto out;
2075 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
2076 kvm_userspace_mem.flags = 0;
2077 kvm_userspace_mem.guest_phys_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR;
2078 kvm_userspace_mem.memory_size = PAGE_SIZE;
2079 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2080 if (r)
2081 goto out;
2082
b7ebfb05
SY		 2083 kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
2084 VMX_EPT_IDENTITY_PAGETABLE_ADDR >> PAGE_SHIFT);
b7ebfb05
SY		 2085out:
2086 up_write(&kvm->slots_lock);
2087 return r;
2088}
2089
2384d2b3
SY		 2090static void allocate_vpid(struct vcpu_vmx *vmx)
2091{
2092 int vpid;
2093
2094 vmx->vpid = 0;
919818ab 2095 if (!enable_vpid)
2384d2b3
SY		 2096 return;
2097 spin_lock(&vmx_vpid_lock);
2098 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
2099 if (vpid < VMX_NR_VPIDS) {
2100 vmx->vpid = vpid;
2101 __set_bit(vpid, vmx_vpid_bitmap);
2102 }
2103 spin_unlock(&vmx_vpid_lock);
2104}
2105
5897297b 2106static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
25c5f225 2107{
3e7c73e9 2108 int f = sizeof(unsigned long);
25c5f225
SY		 2109
2110 if (!cpu_has_vmx_msr_bitmap())
2111 return;
2112
2113 /*
2114 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2115 * have the write-low and read-high bitmap offsets the wrong way round.
2116 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2117 */
25c5f225 2118 if (msr <= 0x1fff) {
3e7c73e9
AK		 2119 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
2120 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
25c5f225
SY		 2121 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2122 msr &= 0x1fff;
3e7c73e9
AK		 2123 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
2124 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
25c5f225 2125 }
25c5f225
SY		 2126}
2127
5897297b
AK		 2128static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
2129{
2130 if (!longmode_only)
2131 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
2132 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
2133}
2134
6aa8b732
AK		 2135/*
2136 * Sets up the vmcs for emulated real mode.
2137 */
8b9cf98c 2138static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 2139{
468d472f 2140 u32 host_sysenter_cs, msr_low, msr_high;
6aa8b732 2141 u32 junk;
53f658b3 2142 u64 host_pat, tsc_this, tsc_base;
6aa8b732
AK		 2143 unsigned long a;
2144 struct descriptor_table dt;
2145 int i;
cd2276a7 2146 unsigned long kvm_vmx_return;
6e5d865c 2147 u32 exec_control;
6aa8b732 2148
6aa8b732 2149 /* I/O */
3e7c73e9
AK		 2150 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
2151 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 2152
25c5f225 2153 if (cpu_has_vmx_msr_bitmap())
5897297b 2154 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 2155
6aa8b732
AK		 2156 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
2157
6aa8b732 2158 /* Control */
1c3d14fe
YS		 2159 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
2160 vmcs_config.pin_based_exec_ctrl);
6e5d865c
YS		 2161
2162 exec_control = vmcs_config.cpu_based_exec_ctrl;
2163 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
2164 exec_control &= ~CPU_BASED_TPR_SHADOW;
2165#ifdef CONFIG_X86_64
2166 exec_control |= CPU_BASED_CR8_STORE_EXITING |
2167 CPU_BASED_CR8_LOAD_EXITING;
2168#endif
2169 }
089d034e 2170 if (!enable_ept)
d56f546d 2171 exec_control |= CPU_BASED_CR3_STORE_EXITING |
83dbc83a
MT		 2172 CPU_BASED_CR3_LOAD_EXITING |
2173 CPU_BASED_INVLPG_EXITING;
6e5d865c 2174 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
6aa8b732 2175
83ff3b9d
SY		 2176 if (cpu_has_secondary_exec_ctrls()) {
2177 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
2178 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2179 exec_control &=
2180 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2384d2b3
SY		 2181 if (vmx->vpid == 0)
2182 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
089d034e 2183 if (!enable_ept)
d56f546d 2184 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
83ff3b9d
SY		 2185 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
2186 }
f78e0e2e 2187
c7addb90
AK		 2188 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
2189 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
6aa8b732
AK		 2190 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
2191
2192 vmcs_writel(HOST_CR0, read_cr0()); /* 22.2.3 */
2193 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
2194 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
2195
2196 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
2197 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2198 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
d6e88aec
AK		 2199 vmcs_write16(HOST_FS_SELECTOR, kvm_read_fs()); /* 22.2.4 */
2200 vmcs_write16(HOST_GS_SELECTOR, kvm_read_gs()); /* 22.2.4 */
6aa8b732 2201 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
05b3e0c2 2202#ifdef CONFIG_X86_64
6aa8b732
AK		 2203 rdmsrl(MSR_FS_BASE, a);
2204 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
2205 rdmsrl(MSR_GS_BASE, a);
2206 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
2207#else
2208 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
2209 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
2210#endif
2211
2212 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
2213
d6e88aec 2214 kvm_get_idt(&dt);
6aa8b732
AK		 2215 vmcs_writel(HOST_IDTR_BASE, dt.base); /* 22.2.4 */
2216
d77c26fc 2217 asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
cd2276a7 2218 vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2cc51560
ED		 2219 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
2220 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
2221 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
6aa8b732
AK		 2222
2223 rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
2224 vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
2225 rdmsrl(MSR_IA32_SYSENTER_ESP, a);
2226 vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */
2227 rdmsrl(MSR_IA32_SYSENTER_EIP, a);
2228 vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */
2229
468d472f
SY		 2230 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
2231 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2232 host_pat = msr_low | ((u64) msr_high << 32);
2233 vmcs_write64(HOST_IA32_PAT, host_pat);
2234 }
2235 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2236 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2237 host_pat = msr_low | ((u64) msr_high << 32);
2238 /* Write the default value follow host pat */
2239 vmcs_write64(GUEST_IA32_PAT, host_pat);
2240 /* Keep arch.pat sync with GUEST_IA32_PAT */
2241 vmx->vcpu.arch.pat = host_pat;
2242 }
2243
6aa8b732
AK		 2244 for (i = 0; i < NR_VMX_MSR; ++i) {
2245 u32 index = vmx_msr_index[i];
2246 u32 data_low, data_high;
2247 u64 data;
a2fa3e9f 2248 int j = vmx->nmsrs;
6aa8b732
AK		 2249
2250 if (rdmsr_safe(index, &data_low, &data_high) < 0)
2251 continue;
432bd6cb
AK		 2252 if (wrmsr_safe(index, data_low, data_high) < 0)
2253 continue;
6aa8b732 2254 data = data_low | ((u64)data_high << 32);
a2fa3e9f
GH		 2255 vmx->host_msrs[j].index = index;
2256 vmx->host_msrs[j].reserved = 0;
2257 vmx->host_msrs[j].data = data;
2258 vmx->guest_msrs[j] = vmx->host_msrs[j];
2259 ++vmx->nmsrs;
6aa8b732 2260 }
6aa8b732 2261
1c3d14fe 2262 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 2263
2264 /* 22.2.1, 20.8.1 */
1c3d14fe
YS		 2265 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
2266
e00c8cf2
AK		 2267 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
2268 vmcs_writel(CR4_GUEST_HOST_MASK, KVM_GUEST_CR4_MASK);
2269
53f658b3
MT		 2270 tsc_base = vmx->vcpu.kvm->arch.vm_init_tsc;
2271 rdtscll(tsc_this);
2272 if (tsc_this < vmx->vcpu.kvm->arch.vm_init_tsc)
2273 tsc_base = tsc_this;
2274
2275 guest_write_tsc(0, tsc_base);
f78e0e2e 2276
e00c8cf2
AK		 2277 return 0;
2278}
2279
b7ebfb05
SY		 2280static int init_rmode(struct kvm *kvm)
2281{
2282 if (!init_rmode_tss(kvm))
2283 return 0;
2284 if (!init_rmode_identity_map(kvm))
2285 return 0;
2286 return 1;
2287}
2288
e00c8cf2
AK		 2289static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
2290{
2291 struct vcpu_vmx *vmx = to_vmx(vcpu);
2292 u64 msr;
2293 int ret;
2294
5fdbf976 2295 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
3200f405 2296 down_read(&vcpu->kvm->slots_lock);
b7ebfb05 2297 if (!init_rmode(vmx->vcpu.kvm)) {
e00c8cf2
AK		 2298 ret = -ENOMEM;
2299 goto out;
2300 }
2301
ad312c7c 2302 vmx->vcpu.arch.rmode.active = 0;
e00c8cf2 2303
3b86cd99
JK		 2304 vmx->soft_vnmi_blocked = 0;
2305
ad312c7c 2306 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 2307 kvm_set_cr8(&vmx->vcpu, 0);
e00c8cf2
AK		 2308 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
2309 if (vmx->vcpu.vcpu_id == 0)
2310 msr |= MSR_IA32_APICBASE_BSP;
2311 kvm_set_apic_base(&vmx->vcpu, msr);
2312
2313 fx_init(&vmx->vcpu);
2314
5706be0d 2315 seg_setup(VCPU_SREG_CS);
e00c8cf2
AK		 2316 /*
2317 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2318 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
2319 */
2320 if (vmx->vcpu.vcpu_id == 0) {
2321 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2322 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2323 } else {
ad312c7c
ZX		 2324 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2325 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
e00c8cf2 2326 }
e00c8cf2
AK		 2327
2328 seg_setup(VCPU_SREG_DS);
2329 seg_setup(VCPU_SREG_ES);
2330 seg_setup(VCPU_SREG_FS);
2331 seg_setup(VCPU_SREG_GS);
2332 seg_setup(VCPU_SREG_SS);
2333
2334 vmcs_write16(GUEST_TR_SELECTOR, 0);
2335 vmcs_writel(GUEST_TR_BASE, 0);
2336 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
2337 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2338
2339 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
2340 vmcs_writel(GUEST_LDTR_BASE, 0);
2341 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
2342 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
2343
2344 vmcs_write32(GUEST_SYSENTER_CS, 0);
2345 vmcs_writel(GUEST_SYSENTER_ESP, 0);
2346 vmcs_writel(GUEST_SYSENTER_EIP, 0);
2347
2348 vmcs_writel(GUEST_RFLAGS, 0x02);
2349 if (vmx->vcpu.vcpu_id == 0)
5fdbf976 2350 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 2351 else
5fdbf976
MT		 2352 kvm_rip_write(vcpu, 0);
2353 kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
e00c8cf2 2354
e00c8cf2
AK		 2355 vmcs_writel(GUEST_DR7, 0x400);
2356
2357 vmcs_writel(GUEST_GDTR_BASE, 0);
2358 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
2359
2360 vmcs_writel(GUEST_IDTR_BASE, 0);
2361 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
2362
2363 vmcs_write32(GUEST_ACTIVITY_STATE, 0);
2364 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
2365 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
2366
e00c8cf2
AK		 2367 /* Special registers */
2368 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
2369
2370 setup_msrs(vmx);
2371
6aa8b732
AK		 2372 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
2373
f78e0e2e
SY		 2374 if (cpu_has_vmx_tpr_shadow()) {
2375 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
2376 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
2377 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
ad312c7c 2378 page_to_phys(vmx->vcpu.arch.apic->regs_page));
f78e0e2e
SY		 2379 vmcs_write32(TPR_THRESHOLD, 0);
2380 }
2381
2382 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2383 vmcs_write64(APIC_ACCESS_ADDR,
bfc6d222 2384 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
6aa8b732 2385
2384d2b3
SY		 2386 if (vmx->vpid != 0)
2387 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2388
ad312c7c
ZX		 2389 vmx->vcpu.arch.cr0 = 0x60000010;
2390 vmx_set_cr0(&vmx->vcpu, vmx->vcpu.arch.cr0); /* enter rmode */
8b9cf98c 2391 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 2392 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 2393 vmx_fpu_activate(&vmx->vcpu);
2394 update_exception_bitmap(&vmx->vcpu);
6aa8b732 2395
2384d2b3
SY		 2396 vpid_sync_vcpu_all(vmx);
2397
3200f405 2398 ret = 0;
6aa8b732 2399
a89a8fb9
MG		 2400 /* HACK: Don't enable emulation on guest boot/reset */
2401 vmx->emulation_required = 0;
2402
6aa8b732 2403out:
3200f405 2404 up_read(&vcpu->kvm->slots_lock);
6aa8b732
AK		 2405 return ret;
2406}
2407
3b86cd99
JK		 2408static void enable_irq_window(struct kvm_vcpu *vcpu)
2409{
2410 u32 cpu_based_vm_exec_control;
2411
2412 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2413 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2414 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2415}
2416
2417static void enable_nmi_window(struct kvm_vcpu *vcpu)
2418{
2419 u32 cpu_based_vm_exec_control;
2420
2421 if (!cpu_has_virtual_nmis()) {
2422 enable_irq_window(vcpu);
2423 return;
2424 }
2425
2426 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2427 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
2428 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2429}
2430
85f455f7
ED		 2431static void vmx_inject_irq(struct kvm_vcpu *vcpu, int irq)
2432{
9c8cba37
AK		 2433 struct vcpu_vmx *vmx = to_vmx(vcpu);
2434
2714d1d3
FEL		 2435 KVMTRACE_1D(INJ_VIRQ, vcpu, (u32)irq, handler);
2436
fa89a817 2437 ++vcpu->stat.irq_injections;
ad312c7c 2438 if (vcpu->arch.rmode.active) {
9c8cba37
AK		 2439 vmx->rmode.irq.pending = true;
2440 vmx->rmode.irq.vector = irq;
5fdbf976 2441 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
9c5623e3
AK		 2442 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2443 irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK);
2444 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
5fdbf976 2445 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
85f455f7
ED		 2446 return;
2447 }
2448 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2449 irq | INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
2450}
2451
f08864b4
SY		 2452static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
2453{
66a5a347
JK		 2454 struct vcpu_vmx *vmx = to_vmx(vcpu);
2455
3b86cd99
JK		 2456 if (!cpu_has_virtual_nmis()) {
2457 /*
2458 * Tracking the NMI-blocked state in software is built upon
2459 * finding the next open IRQ window. This, in turn, depends on
2460 * well-behaving guests: They have to keep IRQs disabled at
2461 * least as long as the NMI handler runs. Otherwise we may
2462 * cause NMI nesting, maybe breaking the guest. But as this is
2463 * highly unlikely, we can live with the residual risk.
2464 */
2465 vmx->soft_vnmi_blocked = 1;
2466 vmx->vnmi_blocked_time = 0;
2467 }
2468
487b391d 2469 ++vcpu->stat.nmi_injections;
66a5a347
JK		 2470 if (vcpu->arch.rmode.active) {
2471 vmx->rmode.irq.pending = true;
2472 vmx->rmode.irq.vector = NMI_VECTOR;
2473 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2474 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2475 NMI_VECTOR | INTR_TYPE_SOFT_INTR |
2476 INTR_INFO_VALID_MASK);
2477 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2478 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2479 return;
2480 }
f08864b4
SY		 2481 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2482 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
f08864b4
SY		 2483}
2484
33f089ca
JK		 2485static void vmx_update_window_states(struct kvm_vcpu *vcpu)
2486{
2487 u32 guest_intr = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2488
2489 vcpu->arch.nmi_window_open =
2490 !(guest_intr & (GUEST_INTR_STATE_STI |
2491 GUEST_INTR_STATE_MOV_SS |
2492 GUEST_INTR_STATE_NMI));
3b86cd99
JK		 2493 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
2494 vcpu->arch.nmi_window_open = 0;
33f089ca
JK		 2495
2496 vcpu->arch.interrupt_window_open =
2497 ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2498 !(guest_intr & (GUEST_INTR_STATE_STI |
2499 GUEST_INTR_STATE_MOV_SS)));
2500}
2501
78646121
GN		 2502static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
2503{
2504 vmx_update_window_states(vcpu);
2505 return vcpu->arch.interrupt_window_open;
2506}
2507
cbc94022
IE		 2508static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
2509{
2510 int ret;
2511 struct kvm_userspace_memory_region tss_mem = {
6fe63979 2512 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 2513 .guest_phys_addr = addr,
2514 .memory_size = PAGE_SIZE * 3,
2515 .flags = 0,
2516 };
2517
2518 ret = kvm_set_memory_region(kvm, &tss_mem, 0);
2519 if (ret)
2520 return ret;
bfc6d222 2521 kvm->arch.tss_addr = addr;
cbc94022
IE		 2522 return 0;
2523}
2524
6aa8b732
AK		 2525static int handle_rmode_exception(struct kvm_vcpu *vcpu,
2526 int vec, u32 err_code)
2527{
b3f37707
NK		 2528 /*
2529 * Instruction with address size override prefix opcode 0x67
2530 * Cause the #SS fault with 0 error code in VM86 mode.
2531 */
2532 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
3427318f 2533 if (emulate_instruction(vcpu, NULL, 0, 0, 0) == EMULATE_DONE)
6aa8b732 2534 return 1;
77ab6db0
JK		 2535 /*
2536 * Forward all other exceptions that are valid in real mode.
2537 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
2538 * the required debugging infrastructure rework.
2539 */
2540 switch (vec) {
77ab6db0 2541 case DB_VECTOR:
d0bfb940
JK		 2542 if (vcpu->guest_debug &
2543 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
2544 return 0;
2545 kvm_queue_exception(vcpu, vec);
2546 return 1;
77ab6db0 2547 case BP_VECTOR:
d0bfb940
JK		 2548 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2549 return 0;
2550 /* fall through */
2551 case DE_VECTOR:
77ab6db0
JK		 2552 case OF_VECTOR:
2553 case BR_VECTOR:
2554 case UD_VECTOR:
2555 case DF_VECTOR:
2556 case SS_VECTOR:
2557 case GP_VECTOR:
2558 case MF_VECTOR:
2559 kvm_queue_exception(vcpu, vec);
2560 return 1;
2561 }
6aa8b732
AK		 2562 return 0;
2563}
2564
2565static int handle_exception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2566{
1155f76a 2567 struct vcpu_vmx *vmx = to_vmx(vcpu);
d0bfb940 2568 u32 intr_info, ex_no, error_code;
42dbaa5a 2569 unsigned long cr2, rip, dr6;
6aa8b732
AK		 2570 u32 vect_info;
2571 enum emulation_result er;
2572
1155f76a 2573 vect_info = vmx->idt_vectoring_info;
6aa8b732
AK		 2574 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
2575
2576 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
d77c26fc 2577 !is_page_fault(intr_info))
6aa8b732 2578 printk(KERN_ERR "%s: unexpected, vectoring info 0x%x "
b8688d51 2579 "intr info 0x%x\n", __func__, vect_info, intr_info);
6aa8b732 2580
e4a41889 2581 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 2582 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 2583
2584 if (is_no_device(intr_info)) {
5fd86fcf 2585 vmx_fpu_activate(vcpu);
2ab455cc
AL		 2586 return 1;
2587 }
2588
7aa81cc0 2589 if (is_invalid_opcode(intr_info)) {
571008da 2590 er = emulate_instruction(vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD);
7aa81cc0 2591 if (er != EMULATE_DONE)
7ee5d940 2592 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 2593 return 1;
2594 }
2595
6aa8b732 2596 error_code = 0;
5fdbf976 2597 rip = kvm_rip_read(vcpu);
2e11384c 2598 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732
AK		 2599 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
2600 if (is_page_fault(intr_info)) {
1439442c 2601 /* EPT won't cause page fault directly */
089d034e 2602 if (enable_ept)
1439442c 2603 BUG();
6aa8b732 2604 cr2 = vmcs_readl(EXIT_QUALIFICATION);
2714d1d3
FEL		 2605 KVMTRACE_3D(PAGE_FAULT, vcpu, error_code, (u32)cr2,
2606 (u32)((u64)cr2 >> 32), handler);
f7d9238f 2607 if (vcpu->arch.interrupt.pending || vcpu->arch.exception.pending)
577bdc49 2608 kvm_mmu_unprotect_page_virt(vcpu, cr2);
3067714c 2609 return kvm_mmu_page_fault(vcpu, cr2, error_code);
6aa8b732
AK		 2610 }
2611
ad312c7c 2612 if (vcpu->arch.rmode.active &&
6aa8b732 2613 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
72d6e5a0 2614 error_code)) {
ad312c7c
ZX		 2615 if (vcpu->arch.halt_request) {
2616 vcpu->arch.halt_request = 0;
72d6e5a0
AK		 2617 return kvm_emulate_halt(vcpu);
2618 }
6aa8b732 2619 return 1;
72d6e5a0 2620 }
6aa8b732 2621
d0bfb940 2622 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
42dbaa5a
JK		 2623 switch (ex_no) {
2624 case DB_VECTOR:
2625 dr6 = vmcs_readl(EXIT_QUALIFICATION);
2626 if (!(vcpu->guest_debug &
2627 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
2628 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
2629 kvm_queue_exception(vcpu, DB_VECTOR);
2630 return 1;
2631 }
2632 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
2633 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
2634 /* fall through */
2635 case BP_VECTOR:
6aa8b732 2636 kvm_run->exit_reason = KVM_EXIT_DEBUG;
d0bfb940
JK		 2637 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
2638 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 2639 break;
2640 default:
d0bfb940
JK		 2641 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
2642 kvm_run->ex.exception = ex_no;
2643 kvm_run->ex.error_code = error_code;
42dbaa5a 2644 break;
6aa8b732 2645 }
6aa8b732
AK		 2646 return 0;
2647}
2648
2649static int handle_external_interrupt(struct kvm_vcpu *vcpu,
2650 struct kvm_run *kvm_run)
2651{
1165f5fe 2652 ++vcpu->stat.irq_exits;
2714d1d3 2653 KVMTRACE_1D(INTR, vcpu, vmcs_read32(VM_EXIT_INTR_INFO), handler);
6aa8b732
AK		 2654 return 1;
2655}
2656
988ad74f
AK		 2657static int handle_triple_fault(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2658{
2659 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2660 return 0;
2661}
6aa8b732 2662
6aa8b732
AK		 2663static int handle_io(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2664{
bfdaab09 2665 unsigned long exit_qualification;
34c33d16 2666 int size, in, string;
039576c0 2667 unsigned port;
6aa8b732 2668
1165f5fe 2669 ++vcpu->stat.io_exits;
bfdaab09 2670 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 2671 string = (exit_qualification & 16) != 0;
e70669ab
LV		 2672
2673 if (string) {
3427318f
LV		 2674 if (emulate_instruction(vcpu,
2675 kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
e70669ab
LV		 2676 return 0;
2677 return 1;
2678 }
2679
2680 size = (exit_qualification & 7) + 1;
2681 in = (exit_qualification & 8) != 0;
039576c0 2682 port = exit_qualification >> 16;
e70669ab 2683
e93f36bc 2684 skip_emulated_instruction(vcpu);
3090dd73 2685 return kvm_emulate_pio(vcpu, kvm_run, in, size, port);
6aa8b732
AK		 2686}
2687
102d8325
IM		 2688static void
2689vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2690{
2691 /*
2692 * Patch in the VMCALL instruction:
2693 */
2694 hypercall[0] = 0x0f;
2695 hypercall[1] = 0x01;
2696 hypercall[2] = 0xc1;
102d8325
IM		 2697}
2698
6aa8b732
AK		 2699static int handle_cr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2700{
bfdaab09 2701 unsigned long exit_qualification;
6aa8b732
AK		 2702 int cr;
2703 int reg;
2704
bfdaab09 2705 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 2706 cr = exit_qualification & 15;
2707 reg = (exit_qualification >> 8) & 15;
2708 switch ((exit_qualification >> 4) & 3) {
2709 case 0: /* mov to cr */
5fdbf976
MT		 2710 KVMTRACE_3D(CR_WRITE, vcpu, (u32)cr,
2711 (u32)kvm_register_read(vcpu, reg),
2712 (u32)((u64)kvm_register_read(vcpu, reg) >> 32),
2713 handler);
6aa8b732
AK		 2714 switch (cr) {
2715 case 0:
5fdbf976 2716 kvm_set_cr0(vcpu, kvm_register_read(vcpu, reg));
6aa8b732
AK		 2717 skip_emulated_instruction(vcpu);
2718 return 1;
2719 case 3:
5fdbf976 2720 kvm_set_cr3(vcpu, kvm_register_read(vcpu, reg));
6aa8b732
AK		 2721 skip_emulated_instruction(vcpu);
2722 return 1;
2723 case 4:
5fdbf976 2724 kvm_set_cr4(vcpu, kvm_register_read(vcpu, reg));
6aa8b732
AK		 2725 skip_emulated_instruction(vcpu);
2726 return 1;
0a5fff19
GN		 2727 case 8: {
2728 u8 cr8_prev = kvm_get_cr8(vcpu);
2729 u8 cr8 = kvm_register_read(vcpu, reg);
2730 kvm_set_cr8(vcpu, cr8);
2731 skip_emulated_instruction(vcpu);
2732 if (irqchip_in_kernel(vcpu->kvm))
2733 return 1;
2734 if (cr8_prev <= cr8)
2735 return 1;
2736 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2737 return 0;
2738 }
6aa8b732
AK		 2739 };
2740 break;
25c4c276 2741 case 2: /* clts */
5fd86fcf 2742 vmx_fpu_deactivate(vcpu);
ad312c7c
ZX		 2743 vcpu->arch.cr0 &= ~X86_CR0_TS;
2744 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf 2745 vmx_fpu_activate(vcpu);
2714d1d3 2746 KVMTRACE_0D(CLTS, vcpu, handler);
25c4c276
AL		 2747 skip_emulated_instruction(vcpu);
2748 return 1;
6aa8b732
AK		 2749 case 1: /*mov from cr*/
2750 switch (cr) {
2751 case 3:
5fdbf976 2752 kvm_register_write(vcpu, reg, vcpu->arch.cr3);
2714d1d3 2753 KVMTRACE_3D(CR_READ, vcpu, (u32)cr,
5fdbf976
MT		 2754 (u32)kvm_register_read(vcpu, reg),
2755 (u32)((u64)kvm_register_read(vcpu, reg) >> 32),
2714d1d3 2756 handler);
6aa8b732
AK		 2757 skip_emulated_instruction(vcpu);
2758 return 1;
2759 case 8:
5fdbf976 2760 kvm_register_write(vcpu, reg, kvm_get_cr8(vcpu));
2714d1d3 2761 KVMTRACE_2D(CR_READ, vcpu, (u32)cr,
5fdbf976 2762 (u32)kvm_register_read(vcpu, reg), handler);
6aa8b732
AK		 2763 skip_emulated_instruction(vcpu);
2764 return 1;
2765 }
2766 break;
2767 case 3: /* lmsw */
2d3ad1f4 2768 kvm_lmsw(vcpu, (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f);
6aa8b732
AK		 2769
2770 skip_emulated_instruction(vcpu);
2771 return 1;
2772 default:
2773 break;
2774 }
2775 kvm_run->exit_reason = 0;
f0242478 2776 pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 2777 (int)(exit_qualification >> 4) & 3, cr);
2778 return 0;
2779}
2780
2781static int handle_dr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2782{
bfdaab09 2783 unsigned long exit_qualification;
6aa8b732
AK		 2784 unsigned long val;
2785 int dr, reg;
2786
42dbaa5a
JK		 2787 dr = vmcs_readl(GUEST_DR7);
2788 if (dr & DR7_GD) {
2789 /*
2790 * As the vm-exit takes precedence over the debug trap, we
2791 * need to emulate the latter, either for the host or the
2792 * guest debugging itself.
2793 */
2794 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
2795 kvm_run->debug.arch.dr6 = vcpu->arch.dr6;
2796 kvm_run->debug.arch.dr7 = dr;
2797 kvm_run->debug.arch.pc =
2798 vmcs_readl(GUEST_CS_BASE) +
2799 vmcs_readl(GUEST_RIP);
2800 kvm_run->debug.arch.exception = DB_VECTOR;
2801 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2802 return 0;
2803 } else {
2804 vcpu->arch.dr7 &= ~DR7_GD;
2805 vcpu->arch.dr6 |= DR6_BD;
2806 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
2807 kvm_queue_exception(vcpu, DB_VECTOR);
2808 return 1;
2809 }
2810 }
2811
bfdaab09 2812 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
42dbaa5a
JK		 2813 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
2814 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
2815 if (exit_qualification & TYPE_MOV_FROM_DR) {
6aa8b732 2816 switch (dr) {
42dbaa5a
JK		 2817 case 0 ... 3:
2818 val = vcpu->arch.db[dr];
2819 break;
6aa8b732 2820 case 6:
42dbaa5a 2821 val = vcpu->arch.dr6;
6aa8b732
AK		 2822 break;
2823 case 7:
42dbaa5a 2824 val = vcpu->arch.dr7;
6aa8b732
AK		 2825 break;
2826 default:
2827 val = 0;
2828 }
5fdbf976 2829 kvm_register_write(vcpu, reg, val);
2714d1d3 2830 KVMTRACE_2D(DR_READ, vcpu, (u32)dr, (u32)val, handler);
6aa8b732 2831 } else {
42dbaa5a
JK		 2832 val = vcpu->arch.regs[reg];
2833 switch (dr) {
2834 case 0 ... 3:
2835 vcpu->arch.db[dr] = val;
2836 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
2837 vcpu->arch.eff_db[dr] = val;
2838 break;
2839 case 4 ... 5:
2840 if (vcpu->arch.cr4 & X86_CR4_DE)
2841 kvm_queue_exception(vcpu, UD_VECTOR);
2842 break;
2843 case 6:
2844 if (val & 0xffffffff00000000ULL) {
2845 kvm_queue_exception(vcpu, GP_VECTOR);
2846 break;
2847 }
2848 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
2849 break;
2850 case 7:
2851 if (val & 0xffffffff00000000ULL) {
2852 kvm_queue_exception(vcpu, GP_VECTOR);
2853 break;
2854 }
2855 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
2856 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
2857 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
2858 vcpu->arch.switch_db_regs =
2859 (val & DR7_BP_EN_MASK);
2860 }
2861 break;
2862 }
2863 KVMTRACE_2D(DR_WRITE, vcpu, (u32)dr, (u32)val, handler);
6aa8b732 2864 }
6aa8b732
AK		 2865 skip_emulated_instruction(vcpu);
2866 return 1;
2867}
2868
2869static int handle_cpuid(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2870{
06465c5a
AK		 2871 kvm_emulate_cpuid(vcpu);
2872 return 1;
6aa8b732
AK		 2873}
2874
2875static int handle_rdmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2876{
ad312c7c 2877 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 2878 u64 data;
2879
2880 if (vmx_get_msr(vcpu, ecx, &data)) {
c1a5d4f9 2881 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 2882 return 1;
2883 }
2884
2714d1d3
FEL		 2885 KVMTRACE_3D(MSR_READ, vcpu, ecx, (u32)data, (u32)(data >> 32),
2886 handler);
2887
6aa8b732 2888 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 2889 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
2890 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 2891 skip_emulated_instruction(vcpu);
2892 return 1;
2893}
2894
2895static int handle_wrmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2896{
ad312c7c
ZX		 2897 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
2898 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
2899 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732 2900
2714d1d3
FEL		 2901 KVMTRACE_3D(MSR_WRITE, vcpu, ecx, (u32)data, (u32)(data >> 32),
2902 handler);
2903
6aa8b732 2904 if (vmx_set_msr(vcpu, ecx, data) != 0) {
c1a5d4f9 2905 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 2906 return 1;
2907 }
2908
2909 skip_emulated_instruction(vcpu);
2910 return 1;
2911}
2912
6e5d865c
YS		 2913static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu,
2914 struct kvm_run *kvm_run)
2915{
2916 return 1;
2917}
2918
6aa8b732
AK		 2919static int handle_interrupt_window(struct kvm_vcpu *vcpu,
2920 struct kvm_run *kvm_run)
2921{
85f455f7
ED		 2922 u32 cpu_based_vm_exec_control;
2923
2924 /* clear pending irq */
2925 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2926 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
2927 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3
FEL		 2928
2929 KVMTRACE_0D(PEND_INTR, vcpu, handler);
a26bf12a 2930 ++vcpu->stat.irq_window_exits;
2714d1d3 2931
c1150d8c
DL		 2932 /*
2933 * If the user space waits to inject interrupts, exit as soon as
2934 * possible
2935 */
8061823a
GN		 2936 if (!irqchip_in_kernel(vcpu->kvm) &&
2937 kvm_run->request_interrupt_window &&
2938 !kvm_cpu_has_interrupt(vcpu)) {
c1150d8c 2939 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
c1150d8c
DL		 2940 return 0;
2941 }
6aa8b732
AK		 2942 return 1;
2943}
2944
2945static int handle_halt(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2946{
2947 skip_emulated_instruction(vcpu);
d3bef15f 2948 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 2949}
2950
c21415e8
IM		 2951static int handle_vmcall(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2952{
510043da 2953 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 2954 kvm_emulate_hypercall(vcpu);
2955 return 1;
c21415e8
IM		 2956}
2957
a7052897
MT		 2958static int handle_invlpg(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2959{
f9c617f6 2960 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 2961
2962 kvm_mmu_invlpg(vcpu, exit_qualification);
2963 skip_emulated_instruction(vcpu);
2964 return 1;
2965}
2966
e5edaa01
ED		 2967static int handle_wbinvd(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2968{
2969 skip_emulated_instruction(vcpu);
2970 /* TODO: Add support for VT-d/pass-through device */
2971 return 1;
2972}
2973
f78e0e2e
SY		 2974static int handle_apic_access(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2975{
f9c617f6 2976 unsigned long exit_qualification;
f78e0e2e
SY		 2977 enum emulation_result er;
2978 unsigned long offset;
2979
f9c617f6 2980 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
f78e0e2e
SY		 2981 offset = exit_qualification & 0xffful;
2982
2983 er = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
2984
2985 if (er != EMULATE_DONE) {
2986 printk(KERN_ERR
2987 "Fail to handle apic access vmexit! Offset is 0x%lx\n",
2988 offset);
2989 return -ENOTSUPP;
2990 }
2991 return 1;
2992}
2993
37817f29
IE		 2994static int handle_task_switch(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2995{
60637aac 2996 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29
IE		 2997 unsigned long exit_qualification;
2998 u16 tss_selector;
64a7ec06
GN		 2999 int reason, type, idt_v;
3000
3001 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
3002 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 3003
3004 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3005
3006 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 3007 if (reason == TASK_SWITCH_GATE && idt_v) {
3008 switch (type) {
3009 case INTR_TYPE_NMI_INTR:
3010 vcpu->arch.nmi_injected = false;
3011 if (cpu_has_virtual_nmis())
3012 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3013 GUEST_INTR_STATE_NMI);
3014 break;
3015 case INTR_TYPE_EXT_INTR:
3016 kvm_clear_interrupt_queue(vcpu);
3017 break;
3018 case INTR_TYPE_HARD_EXCEPTION:
3019 case INTR_TYPE_SOFT_EXCEPTION:
3020 kvm_clear_exception_queue(vcpu);
3021 break;
3022 default:
3023 break;
3024 }
60637aac 3025 }
37817f29
IE		 3026 tss_selector = exit_qualification;
3027
64a7ec06
GN		 3028 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
3029 type != INTR_TYPE_EXT_INTR &&
3030 type != INTR_TYPE_NMI_INTR))
3031 skip_emulated_instruction(vcpu);
3032
42dbaa5a
JK		 3033 if (!kvm_task_switch(vcpu, tss_selector, reason))
3034 return 0;
3035
3036 /* clear all local breakpoint enable flags */
3037 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
3038
3039 /*
3040 * TODO: What about debug traps on tss switch?
3041 * Are we supposed to inject them and update dr6?
3042 */
3043
3044 return 1;
37817f29
IE		 3045}
3046
1439442c
SY		 3047static int handle_ept_violation(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3048{
f9c617f6 3049 unsigned long exit_qualification;
1439442c 3050 gpa_t gpa;
1439442c 3051 int gla_validity;
1439442c 3052
f9c617f6 3053 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c
SY		 3054
3055 if (exit_qualification & (1 << 6)) {
3056 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
3057 return -ENOTSUPP;
3058 }
3059
3060 gla_validity = (exit_qualification >> 7) & 0x3;
3061 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
3062 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
3063 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3064 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 3065 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 3066 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
3067 (long unsigned int)exit_qualification);
3068 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
3069 kvm_run->hw.hardware_exit_reason = 0;
3070 return -ENOTSUPP;
3071 }
3072
3073 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
49cd7d22 3074 return kvm_mmu_page_fault(vcpu, gpa & PAGE_MASK, 0);
1439442c
SY		 3075}
3076
f08864b4
SY		 3077static int handle_nmi_window(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3078{
3079 u32 cpu_based_vm_exec_control;
3080
3081 /* clear pending NMI */
3082 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3083 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
3084 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3085 ++vcpu->stat.nmi_window_exits;
3086
3087 return 1;
3088}
3089
ea953ef0
MG		 3090static void handle_invalid_guest_state(struct kvm_vcpu *vcpu,
3091 struct kvm_run *kvm_run)
3092{
8b3079a5
AK		 3093 struct vcpu_vmx *vmx = to_vmx(vcpu);
3094 enum emulation_result err = EMULATE_DONE;
ea953ef0
MG		 3095
3096 preempt_enable();
3097 local_irq_enable();
3098
3099 while (!guest_state_valid(vcpu)) {
3100 err = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
3101
1d5a4d9b
GT		 3102 if (err == EMULATE_DO_MMIO)
3103 break;
3104
3105 if (err != EMULATE_DONE) {
3106 kvm_report_emulation_failure(vcpu, "emulation failure");
3107 return;
ea953ef0
MG		 3108 }
3109
3110 if (signal_pending(current))
3111 break;
3112 if (need_resched())
3113 schedule();
3114 }
3115
3116 local_irq_disable();
3117 preempt_disable();
8b3079a5
AK		 3118
3119 vmx->invalid_state_emulation_result = err;
ea953ef0
MG		 3120}
3121
6aa8b732
AK		 3122/*
3123 * The exit handlers return 1 if the exit was handled fully and guest execution
3124 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
3125 * to be done to userspace and return 0.
3126 */
3127static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu,
3128 struct kvm_run *kvm_run) = {
3129 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
3130 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 3131 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 3132 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 3133 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 3134 [EXIT_REASON_CR_ACCESS] = handle_cr,
3135 [EXIT_REASON_DR_ACCESS] = handle_dr,
3136 [EXIT_REASON_CPUID] = handle_cpuid,
3137 [EXIT_REASON_MSR_READ] = handle_rdmsr,
3138 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
3139 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
3140 [EXIT_REASON_HLT] = handle_halt,
a7052897 3141 [EXIT_REASON_INVLPG] = handle_invlpg,
c21415e8 3142 [EXIT_REASON_VMCALL] = handle_vmcall,
f78e0e2e
SY		 3143 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
3144 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
e5edaa01 3145 [EXIT_REASON_WBINVD] = handle_wbinvd,
37817f29 3146 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
1439442c 3147 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
6aa8b732
AK		 3148};
3149
3150static const int kvm_vmx_max_exit_handlers =
50a3485c 3151 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732
AK		 3152
3153/*
3154 * The guest has exited. See if we can fix it or if we need userspace
3155 * assistance.
3156 */
6062d012 3157static int vmx_handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
6aa8b732 3158{
6aa8b732 3159 u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
29bd8a78 3160 struct vcpu_vmx *vmx = to_vmx(vcpu);
1155f76a 3161 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 3162
5fdbf976
MT		 3163 KVMTRACE_3D(VMEXIT, vcpu, exit_reason, (u32)kvm_rip_read(vcpu),
3164 (u32)((u64)kvm_rip_read(vcpu) >> 32), entryexit);
2714d1d3 3165
1d5a4d9b
GT		 3166 /* If we need to emulate an MMIO from handle_invalid_guest_state
3167 * we just return 0 */
10f32d84
AK		 3168 if (vmx->emulation_required && emulate_invalid_guest_state) {
3169 if (guest_state_valid(vcpu))
3170 vmx->emulation_required = 0;
8b3079a5 3171 return vmx->invalid_state_emulation_result != EMULATE_DO_MMIO;
10f32d84 3172 }
1d5a4d9b 3173
1439442c
SY		 3174 /* Access CR3 don't cause VMExit in paging mode, so we need
3175 * to sync with guest real CR3. */
089d034e 3176 if (enable_ept && is_paging(vcpu)) {
1439442c
SY		 3177 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3178 ept_load_pdptrs(vcpu);
3179 }
3180
29bd8a78
AK		 3181 if (unlikely(vmx->fail)) {
3182 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3183 kvm_run->fail_entry.hardware_entry_failure_reason
3184 = vmcs_read32(VM_INSTRUCTION_ERROR);
3185 return 0;
3186 }
6aa8b732 3187
d77c26fc 3188 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 3189 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac
JK		 3190 exit_reason != EXIT_REASON_EPT_VIOLATION &&
3191 exit_reason != EXIT_REASON_TASK_SWITCH))
3192 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
3193 "(0x%x) and exit reason is 0x%x\n",
3194 __func__, vectoring_info, exit_reason);
3b86cd99
JK		 3195
3196 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) {
3197 if (vcpu->arch.interrupt_window_open) {
3198 vmx->soft_vnmi_blocked = 0;
3199 vcpu->arch.nmi_window_open = 1;
3200 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 3201 vcpu->arch.nmi_pending) {
3b86cd99
JK		 3202 /*
3203 * This CPU don't support us in finding the end of an
3204 * NMI-blocked window if the guest runs with IRQs
3205 * disabled. So we pull the trigger after 1 s of
3206 * futile waiting, but inform the user about this.
3207 */
3208 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
3209 "state on VCPU %d after 1 s timeout\n",
3210 __func__, vcpu->vcpu_id);
3211 vmx->soft_vnmi_blocked = 0;
3212 vmx->vcpu.arch.nmi_window_open = 1;
3213 }
3b86cd99
JK		 3214 }
3215
6aa8b732
AK		 3216 if (exit_reason < kvm_vmx_max_exit_handlers
3217 && kvm_vmx_exit_handlers[exit_reason])
3218 return kvm_vmx_exit_handlers[exit_reason](vcpu, kvm_run);
3219 else {
3220 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
3221 kvm_run->hw.hardware_exit_reason = exit_reason;
3222 }
3223 return 0;
3224}
3225
6e5d865c
YS		 3226static void update_tpr_threshold(struct kvm_vcpu *vcpu)
3227{
3228 int max_irr, tpr;
3229
3230 if (!vm_need_tpr_shadow(vcpu->kvm))
3231 return;
3232
3233 if (!kvm_lapic_enabled(vcpu) ||
3234 ((max_irr = kvm_lapic_find_highest_irr(vcpu)) == -1)) {
3235 vmcs_write32(TPR_THRESHOLD, 0);
3236 return;
3237 }
3238
3239 tpr = (kvm_lapic_get_cr8(vcpu) & 0x0f) << 4;
3240 vmcs_write32(TPR_THRESHOLD, (max_irr > tpr) ? tpr >> 4 : max_irr >> 4);
3241}
3242
cf393f75
AK		 3243static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
3244{
3245 u32 exit_intr_info;
7b4a25cb 3246 u32 idt_vectoring_info = vmx->idt_vectoring_info;
cf393f75
AK		 3247 bool unblock_nmi;
3248 u8 vector;
668f612f
AK		 3249 int type;
3250 bool idtv_info_valid;
cf393f75 3251
7b4a25cb 3252 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
cf393f75
AK		 3253 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3254 if (cpu_has_virtual_nmis()) {
3255 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
3256 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
3257 /*
7b4a25cb 3258 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 3259 * Re-set bit "block by NMI" before VM entry if vmexit caused by
3260 * a guest IRET fault.
7b4a25cb
GN		 3261 * SDM 3: 23.2.2 (September 2008)
3262 * Bit 12 is undefined in any of the following cases:
3263 * If the VM exit sets the valid bit in the IDT-vectoring
3264 * information field.
3265 * If the VM exit is due to a double fault.
cf393f75 3266 */
7b4a25cb
GN		 3267 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
3268 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 3269 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3270 GUEST_INTR_STATE_NMI);
3b86cd99
JK		 3271 } else if (unlikely(vmx->soft_vnmi_blocked))
3272 vmx->vnmi_blocked_time +=
3273 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
668f612f 3274
37b96e98
GN		 3275 vmx->vcpu.arch.nmi_injected = false;
3276 kvm_clear_exception_queue(&vmx->vcpu);
3277 kvm_clear_interrupt_queue(&vmx->vcpu);
3278
3279 if (!idtv_info_valid)
3280 return;
3281
668f612f
AK		 3282 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
3283 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 3284
64a7ec06 3285 switch (type) {
37b96e98
GN		 3286 case INTR_TYPE_NMI_INTR:
3287 vmx->vcpu.arch.nmi_injected = true;
668f612f 3288 /*
7b4a25cb 3289 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 3290 * Clear bit "block by NMI" before VM entry if a NMI
3291 * delivery faulted.
668f612f 3292 */
37b96e98
GN		 3293 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3294 GUEST_INTR_STATE_NMI);
3295 break;
3296 case INTR_TYPE_HARD_EXCEPTION:
3297 case INTR_TYPE_SOFT_EXCEPTION:
35920a35 3298 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
37b96e98
GN		 3299 u32 err = vmcs_read32(IDT_VECTORING_ERROR_CODE);
3300 kvm_queue_exception_e(&vmx->vcpu, vector, err);
35920a35
AK		 3301 } else
3302 kvm_queue_exception(&vmx->vcpu, vector);
37b96e98
GN		 3303 break;
3304 case INTR_TYPE_EXT_INTR:
f7d9238f 3305 kvm_queue_interrupt(&vmx->vcpu, vector);
37b96e98
GN		 3306 break;
3307 default:
3308 break;
f7d9238f 3309 }
cf393f75
AK		 3310}
3311
1f21e79a
GN		 3312static void vmx_intr_inject(struct kvm_vcpu *vcpu)
3313{
3314 /* try to reinject previous events if any */
3315 if (vcpu->arch.nmi_injected) {
3316 vmx_inject_nmi(vcpu);
3317 return;
3318 }
3319
3320 if (vcpu->arch.interrupt.pending) {
3321 vmx_inject_irq(vcpu, vcpu->arch.interrupt.nr);
3322 return;
3323 }
3324
3325 /* try to inject new event if pending */
3326 if (vcpu->arch.nmi_pending) {
3327 if (vcpu->arch.nmi_window_open) {
3328 vcpu->arch.nmi_pending = false;
3329 vcpu->arch.nmi_injected = true;
3330 vmx_inject_nmi(vcpu);
3331 }
3332 } else if (kvm_cpu_has_interrupt(vcpu)) {
3333 if (vcpu->arch.interrupt_window_open) {
3334 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu));
3335 vmx_inject_irq(vcpu, vcpu->arch.interrupt.nr);
3336 }
3337 }
3338}
3339
863e8e65 3340static void vmx_intr_assist(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
85f455f7 3341{
863e8e65
GN		 3342 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
3343 kvm_run->request_interrupt_window;
3344
6e5d865c
YS		 3345 update_tpr_threshold(vcpu);
3346
33f089ca
JK		 3347 vmx_update_window_states(vcpu);
3348
55934c0b
JK		 3349 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
3350 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3351 GUEST_INTR_STATE_STI |
3352 GUEST_INTR_STATE_MOV_SS);
3353
1f21e79a 3354 vmx_intr_inject(vcpu);
863e8e65 3355
1f21e79a 3356 /* enable NMI/IRQ window open exits if needed */
863e8e65
GN		 3357 if (vcpu->arch.nmi_pending)
3358 enable_nmi_window(vcpu);
3359 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
3360 enable_irq_window(vcpu);
85f455f7
ED		 3361}
3362
9c8cba37
AK		 3363/*
3364 * Failure to inject an interrupt should give us the information
3365 * in IDT_VECTORING_INFO_FIELD. However, if the failure occurs
3366 * when fetching the interrupt redirection bitmap in the real-mode
3367 * tss, this doesn't happen. So we do it ourselves.
3368 */
3369static void fixup_rmode_irq(struct vcpu_vmx *vmx)
3370{
3371 vmx->rmode.irq.pending = 0;
5fdbf976 3372 if (kvm_rip_read(&vmx->vcpu) + 1 != vmx->rmode.irq.rip)
9c8cba37 3373 return;
5fdbf976 3374 kvm_rip_write(&vmx->vcpu, vmx->rmode.irq.rip);
9c8cba37
AK		 3375 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
3376 vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK;
3377 vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR;
3378 return;
3379 }
3380 vmx->idt_vectoring_info =
3381 VECTORING_INFO_VALID_MASK
3382 | INTR_TYPE_EXT_INTR
3383 | vmx->rmode.irq.vector;
3384}
3385
c801949d
AK		 3386#ifdef CONFIG_X86_64
3387#define R "r"
3388#define Q "q"
3389#else
3390#define R "e"
3391#define Q "l"
3392#endif
3393
04d2cc77 3394static void vmx_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6aa8b732 3395{
a2fa3e9f 3396 struct vcpu_vmx *vmx = to_vmx(vcpu);
1b6269db 3397 u32 intr_info;
e6adf283 3398
3b86cd99
JK		 3399 /* Record the guest's net vcpu time for enforced NMI injections. */
3400 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
3401 vmx->entry_time = ktime_get();
3402
a89a8fb9
MG		 3403 /* Handle invalid guest state instead of entering VMX */
3404 if (vmx->emulation_required && emulate_invalid_guest_state) {
3405 handle_invalid_guest_state(vcpu, kvm_run);
3406 return;
3407 }
3408
5fdbf976
MT		 3409 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
3410 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
3411 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
3412 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
3413
e6adf283
AK		 3414 /*
3415 * Loading guest fpu may have cleared host cr0.ts
3416 */
3417 vmcs_writel(HOST_CR0, read_cr0());
3418
42dbaa5a
JK		 3419 set_debugreg(vcpu->arch.dr6, 6);
3420
d77c26fc 3421 asm(
6aa8b732 3422 /* Store host registers */
c801949d
AK		 3423 "push %%"R"dx; push %%"R"bp;"
3424 "push %%"R"cx \n\t"
313dbd49
AK		 3425 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
3426 "je 1f \n\t"
3427 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
4ecac3fd 3428 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 3429 "1: \n\t"
6aa8b732 3430 /* Check if vmlaunch of vmresume is needed */
e08aa78a 3431 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 3432 /* Load guest registers. Don't clobber flags. */
c801949d
AK		 3433 "mov %c[cr2](%0), %%"R"ax \n\t"
3434 "mov %%"R"ax, %%cr2 \n\t"
3435 "mov %c[rax](%0), %%"R"ax \n\t"
3436 "mov %c[rbx](%0), %%"R"bx \n\t"
3437 "mov %c[rdx](%0), %%"R"dx \n\t"
3438 "mov %c[rsi](%0), %%"R"si \n\t"
3439 "mov %c[rdi](%0), %%"R"di \n\t"
3440 "mov %c[rbp](%0), %%"R"bp \n\t"
05b3e0c2 3441#ifdef CONFIG_X86_64
e08aa78a
AK		 3442 "mov %c[r8](%0), %%r8 \n\t"
3443 "mov %c[r9](%0), %%r9 \n\t"
3444 "mov %c[r10](%0), %%r10 \n\t"
3445 "mov %c[r11](%0), %%r11 \n\t"
3446 "mov %c[r12](%0), %%r12 \n\t"
3447 "mov %c[r13](%0), %%r13 \n\t"
3448 "mov %c[r14](%0), %%r14 \n\t"
3449 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 3450#endif
c801949d
AK		 3451 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
3452
6aa8b732 3453 /* Enter guest mode */
cd2276a7 3454 "jne .Llaunched \n\t"
4ecac3fd 3455 __ex(ASM_VMX_VMLAUNCH) "\n\t"
cd2276a7 3456 "jmp .Lkvm_vmx_return \n\t"
4ecac3fd 3457 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
cd2276a7 3458 ".Lkvm_vmx_return: "
6aa8b732 3459 /* Save guest registers, load host registers, keep flags */
c801949d
AK		 3460 "xchg %0, (%%"R"sp) \n\t"
3461 "mov %%"R"ax, %c[rax](%0) \n\t"
3462 "mov %%"R"bx, %c[rbx](%0) \n\t"
3463 "push"Q" (%%"R"sp); pop"Q" %c[rcx](%0) \n\t"
3464 "mov %%"R"dx, %c[rdx](%0) \n\t"
3465 "mov %%"R"si, %c[rsi](%0) \n\t"
3466 "mov %%"R"di, %c[rdi](%0) \n\t"
3467 "mov %%"R"bp, %c[rbp](%0) \n\t"
05b3e0c2 3468#ifdef CONFIG_X86_64
e08aa78a
AK		 3469 "mov %%r8, %c[r8](%0) \n\t"
3470 "mov %%r9, %c[r9](%0) \n\t"
3471 "mov %%r10, %c[r10](%0) \n\t"
3472 "mov %%r11, %c[r11](%0) \n\t"
3473 "mov %%r12, %c[r12](%0) \n\t"
3474 "mov %%r13, %c[r13](%0) \n\t"
3475 "mov %%r14, %c[r14](%0) \n\t"
3476 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 3477#endif
c801949d
AK		 3478 "mov %%cr2, %%"R"ax \n\t"
3479 "mov %%"R"ax, %c[cr2](%0) \n\t"
3480
3481 "pop %%"R"bp; pop %%"R"bp; pop %%"R"dx \n\t"
e08aa78a
AK		 3482 "setbe %c[fail](%0) \n\t"
3483 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
3484 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
3485 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 3486 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 3487 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
3488 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
3489 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
3490 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
3491 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
3492 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
3493 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 3494#ifdef CONFIG_X86_64
ad312c7c
ZX		 3495 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
3496 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
3497 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
3498 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
3499 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
3500 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
3501 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
3502 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 3503#endif
ad312c7c 3504 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2))
c2036300 3505 : "cc", "memory"
c801949d 3506 , R"bx", R"di", R"si"
c2036300 3507#ifdef CONFIG_X86_64
c2036300
LV		 3508 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3509#endif
3510 );
6aa8b732 3511
5fdbf976
MT		 3512 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
3513 vcpu->arch.regs_dirty = 0;
3514
42dbaa5a
JK		 3515 get_debugreg(vcpu->arch.dr6, 6);
3516
1155f76a 3517 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
9c8cba37
AK		 3518 if (vmx->rmode.irq.pending)
3519 fixup_rmode_irq(vmx);
1155f76a 3520
33f089ca 3521 vmx_update_window_states(vcpu);
6aa8b732 3522
d77c26fc 3523 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
15ad7146 3524 vmx->launched = 1;
1b6269db
AK		 3525
3526 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3527
3528 /* We need to handle NMIs before interrupts are enabled */
e4a41889 3529 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
f08864b4 3530 (intr_info & INTR_INFO_VALID_MASK)) {
2714d1d3 3531 KVMTRACE_0D(NMI, vcpu, handler);
1b6269db 3532 asm("int $2");
2714d1d3 3533 }
cf393f75
AK		 3534
3535 vmx_complete_interrupts(vmx);
6aa8b732
AK		 3536}
3537
c801949d
AK		 3538#undef R
3539#undef Q
3540
6aa8b732
AK		 3541static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
3542{
a2fa3e9f
GH		 3543 struct vcpu_vmx *vmx = to_vmx(vcpu);
3544
3545 if (vmx->vmcs) {
543e4243 3546 vcpu_clear(vmx);
a2fa3e9f
GH		 3547 free_vmcs(vmx->vmcs);
3548 vmx->vmcs = NULL;
6aa8b732
AK		 3549 }
3550}
3551
3552static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
3553{
fb3f0f51
RR		 3554 struct vcpu_vmx *vmx = to_vmx(vcpu);
3555
2384d2b3
SY		 3556 spin_lock(&vmx_vpid_lock);
3557 if (vmx->vpid != 0)
3558 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3559 spin_unlock(&vmx_vpid_lock);
6aa8b732 3560 vmx_free_vmcs(vcpu);
fb3f0f51
RR		 3561 kfree(vmx->host_msrs);
3562 kfree(vmx->guest_msrs);
3563 kvm_vcpu_uninit(vcpu);
a4770347 3564 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 3565}
3566
fb3f0f51 3567static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 3568{
fb3f0f51 3569 int err;
c16f862d 3570 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 3571 int cpu;
6aa8b732 3572
a2fa3e9f 3573 if (!vmx)
fb3f0f51
RR		 3574 return ERR_PTR(-ENOMEM);
3575
2384d2b3
SY		 3576 allocate_vpid(vmx);
3577
fb3f0f51
RR		 3578 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
3579 if (err)
3580 goto free_vcpu;
965b58a5 3581
a2fa3e9f 3582 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
fb3f0f51
RR		 3583 if (!vmx->guest_msrs) {
3584 err = -ENOMEM;
3585 goto uninit_vcpu;
3586 }
965b58a5 3587
a2fa3e9f
GH		 3588 vmx->host_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
3589 if (!vmx->host_msrs)
fb3f0f51 3590 goto free_guest_msrs;
965b58a5 3591
a2fa3e9f
GH		 3592 vmx->vmcs = alloc_vmcs();
3593 if (!vmx->vmcs)
fb3f0f51 3594 goto free_msrs;
a2fa3e9f
GH		 3595
3596 vmcs_clear(vmx->vmcs);
3597
15ad7146
AK		 3598 cpu = get_cpu();
3599 vmx_vcpu_load(&vmx->vcpu, cpu);
8b9cf98c 3600 err = vmx_vcpu_setup(vmx);
fb3f0f51 3601 vmx_vcpu_put(&vmx->vcpu);
15ad7146 3602 put_cpu();
fb3f0f51
RR		 3603 if (err)
3604 goto free_vmcs;
5e4a0b3c
MT		 3605 if (vm_need_virtualize_apic_accesses(kvm))
3606 if (alloc_apic_access_page(kvm) != 0)
3607 goto free_vmcs;
fb3f0f51 3608
089d034e 3609 if (enable_ept)
b7ebfb05
SY		 3610 if (alloc_identity_pagetable(kvm) != 0)
3611 goto free_vmcs;
3612
fb3f0f51
RR		 3613 return &vmx->vcpu;
3614
3615free_vmcs:
3616 free_vmcs(vmx->vmcs);
3617free_msrs:
3618 kfree(vmx->host_msrs);
3619free_guest_msrs:
3620 kfree(vmx->guest_msrs);
3621uninit_vcpu:
3622 kvm_vcpu_uninit(&vmx->vcpu);
3623free_vcpu:
a4770347 3624 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 3625 return ERR_PTR(err);
6aa8b732
AK		 3626}
3627
002c7f7c
YS		 3628static void __init vmx_check_processor_compat(void *rtn)
3629{
3630 struct vmcs_config vmcs_conf;
3631
3632 *(int *)rtn = 0;
3633 if (setup_vmcs_config(&vmcs_conf) < 0)
3634 *(int *)rtn = -EIO;
3635 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
3636 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
3637 smp_processor_id());
3638 *(int *)rtn = -EIO;
3639 }
3640}
3641
67253af5
SY		 3642static int get_ept_level(void)
3643{
3644 return VMX_EPT_DEFAULT_GAW + 1;
3645}
3646
64d4d521
SY		 3647static int vmx_get_mt_mask_shift(void)
3648{
3649 return VMX_EPT_MT_EPTE_SHIFT;
3650}
3651
cbdd1bea 3652static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 3653 .cpu_has_kvm_support = cpu_has_kvm_support,
3654 .disabled_by_bios = vmx_disabled_by_bios,
3655 .hardware_setup = hardware_setup,
3656 .hardware_unsetup = hardware_unsetup,
002c7f7c 3657 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 3658 .hardware_enable = hardware_enable,
3659 .hardware_disable = hardware_disable,
04547156 3660 .cpu_has_accelerated_tpr = report_flexpriority,
6aa8b732
AK		 3661
3662 .vcpu_create = vmx_create_vcpu,
3663 .vcpu_free = vmx_free_vcpu,
04d2cc77 3664 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 3665
04d2cc77 3666 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 3667 .vcpu_load = vmx_vcpu_load,
3668 .vcpu_put = vmx_vcpu_put,
3669
3670 .set_guest_debug = set_guest_debug,
3671 .get_msr = vmx_get_msr,
3672 .set_msr = vmx_set_msr,
3673 .get_segment_base = vmx_get_segment_base,
3674 .get_segment = vmx_get_segment,
3675 .set_segment = vmx_set_segment,
2e4d2653 3676 .get_cpl = vmx_get_cpl,
6aa8b732 3677 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
25c4c276 3678 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 3679 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 3680 .set_cr3 = vmx_set_cr3,
3681 .set_cr4 = vmx_set_cr4,
6aa8b732 3682 .set_efer = vmx_set_efer,
6aa8b732
AK		 3683 .get_idt = vmx_get_idt,
3684 .set_idt = vmx_set_idt,
3685 .get_gdt = vmx_get_gdt,
3686 .set_gdt = vmx_set_gdt,
5fdbf976 3687 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 3688 .get_rflags = vmx_get_rflags,
3689 .set_rflags = vmx_set_rflags,
3690
3691 .tlb_flush = vmx_flush_tlb,
6aa8b732 3692
6aa8b732 3693 .run = vmx_vcpu_run,
6062d012 3694 .handle_exit = vmx_handle_exit,
6aa8b732 3695 .skip_emulated_instruction = skip_emulated_instruction,
102d8325 3696 .patch_hypercall = vmx_patch_hypercall,
2a8067f1
ED		 3697 .get_irq = vmx_get_irq,
3698 .set_irq = vmx_inject_irq,
298101da 3699 .queue_exception = vmx_queue_exception,
04d2cc77 3700 .inject_pending_irq = vmx_intr_assist,
78646121 3701 .interrupt_allowed = vmx_interrupt_allowed,
cbc94022 3702 .set_tss_addr = vmx_set_tss_addr,
67253af5 3703 .get_tdp_level = get_ept_level,
64d4d521 3704 .get_mt_mask_shift = vmx_get_mt_mask_shift,
6aa8b732
AK		 3705};
3706
3707static int __init vmx_init(void)
3708{
fdef3ad1
HQ		 3709 int r;
3710
3e7c73e9 3711 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 3712 if (!vmx_io_bitmap_a)
3713 return -ENOMEM;
3714
3e7c73e9 3715 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 3716 if (!vmx_io_bitmap_b) {
3717 r = -ENOMEM;
3718 goto out;
3719 }
3720
5897297b
AK		 3721 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
3722 if (!vmx_msr_bitmap_legacy) {
25c5f225
SY		 3723 r = -ENOMEM;
3724 goto out1;
3725 }
3726
5897297b
AK		 3727 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
3728 if (!vmx_msr_bitmap_longmode) {
3729 r = -ENOMEM;
3730 goto out2;
3731 }
3732
fdef3ad1
HQ		 3733 /*
3734 * Allow direct access to the PC debug port (it is often used for I/O
3735 * delays, but the vmexits simply slow things down).
3736 */
3e7c73e9
AK		 3737 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
3738 clear_bit(0x80, vmx_io_bitmap_a);
fdef3ad1 3739
3e7c73e9 3740 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
fdef3ad1 3741
5897297b
AK		 3742 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
3743 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
25c5f225 3744
2384d2b3
SY		 3745 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
3746
cb498ea2 3747 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 3748 if (r)
5897297b 3749 goto out3;
25c5f225 3750
5897297b
AK		 3751 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
3752 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
3753 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
3754 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
3755 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
3756 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
fdef3ad1 3757
089d034e 3758 if (enable_ept) {
1439442c 3759 bypass_guest_pf = 0;
5fdbcb9d 3760 kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK |
2aaf69dc 3761 VMX_EPT_WRITABLE_MASK);
534e38b4 3762 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
64d4d521
SY		 3763 VMX_EPT_EXECUTABLE_MASK,
3764 VMX_EPT_DEFAULT_MT << VMX_EPT_MT_EPTE_SHIFT);
5fdbcb9d
SY		 3765 kvm_enable_tdp();
3766 } else
3767 kvm_disable_tdp();
1439442c 3768
c7addb90
AK		 3769 if (bypass_guest_pf)
3770 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
3771
1439442c
SY		 3772 ept_sync_global();
3773
fdef3ad1
HQ		 3774 return 0;
3775
5897297b
AK		 3776out3:
3777 free_page((unsigned long)vmx_msr_bitmap_longmode);
25c5f225 3778out2:
5897297b 3779 free_page((unsigned long)vmx_msr_bitmap_legacy);
fdef3ad1 3780out1:
3e7c73e9 3781 free_page((unsigned long)vmx_io_bitmap_b);
fdef3ad1 3782out:
3e7c73e9 3783 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 3784 return r;
6aa8b732
AK		 3785}
3786
3787static void __exit vmx_exit(void)
3788{
5897297b
AK		 3789 free_page((unsigned long)vmx_msr_bitmap_legacy);
3790 free_page((unsigned long)vmx_msr_bitmap_longmode);
3e7c73e9
AK		 3791 free_page((unsigned long)vmx_io_bitmap_b);
3792 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 3793
cb498ea2 3794 kvm_exit();
6aa8b732
AK		 3795}
3796
3797module_init(vmx_init)
3798module_exit(vmx_exit)
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