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Commit | Line | Data |
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6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * This module enables machines with Intel VT-x extensions to run virtual | |
5 | * machines without emulation or binary translation. | |
6 | * | |
7 | * Copyright (C) 2006 Qumranet, Inc. | |
9611c187 | 8 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
6aa8b732 AK |
9 | * |
10 | * Authors: | |
11 | * Avi Kivity <avi@qumranet.com> | |
12 | * Yaniv Kamay <yaniv@qumranet.com> | |
13 | * | |
14 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
15 | * the COPYING file in the top-level directory. | |
16 | * | |
17 | */ | |
18 | ||
85f455f7 | 19 | #include "irq.h" |
1d737c8a | 20 | #include "mmu.h" |
00b27a3e | 21 | #include "cpuid.h" |
d62caabb | 22 | #include "lapic.h" |
e495606d | 23 | |
edf88417 | 24 | #include <linux/kvm_host.h> |
6aa8b732 | 25 | #include <linux/module.h> |
9d8f549d | 26 | #include <linux/kernel.h> |
6aa8b732 AK |
27 | #include <linux/mm.h> |
28 | #include <linux/highmem.h> | |
e8edc6e0 | 29 | #include <linux/sched.h> |
67cd6fac | 30 | #include <linux/sched/smt.h> |
c7addb90 | 31 | #include <linux/moduleparam.h> |
e9bda3b3 | 32 | #include <linux/mod_devicetable.h> |
af658dca | 33 | #include <linux/trace_events.h> |
5a0e3ad6 | 34 | #include <linux/slab.h> |
cafd6659 | 35 | #include <linux/tboot.h> |
f4124500 | 36 | #include <linux/hrtimer.h> |
c207aee4 | 37 | #include <linux/frame.h> |
bcaf287c | 38 | #include <linux/nospec.h> |
5fdbf976 | 39 | #include "kvm_cache_regs.h" |
35920a35 | 40 | #include "x86.h" |
e495606d | 41 | |
28b835d6 | 42 | #include <asm/cpu.h> |
6aa8b732 | 43 | #include <asm/io.h> |
3b3be0d1 | 44 | #include <asm/desc.h> |
13673a90 | 45 | #include <asm/vmx.h> |
6210e37b | 46 | #include <asm/virtext.h> |
a0861c02 | 47 | #include <asm/mce.h> |
952f07ec | 48 | #include <asm/fpu/internal.h> |
d7cd9796 | 49 | #include <asm/perf_event.h> |
81908bf4 | 50 | #include <asm/debugreg.h> |
8f536b76 | 51 | #include <asm/kexec.h> |
dab2087d | 52 | #include <asm/apic.h> |
efc64404 | 53 | #include <asm/irq_remapping.h> |
d6e41f11 | 54 | #include <asm/mmu_context.h> |
f471d71b | 55 | #include <asm/microcode.h> |
d7a6a163 | 56 | #include <asm/spec-ctrl.h> |
6aa8b732 | 57 | |
229456fc | 58 | #include "trace.h" |
25462f7f | 59 | #include "pmu.h" |
229456fc | 60 | |
4ecac3fd | 61 | #define __ex(x) __kvm_handle_fault_on_reboot(x) |
5e520e62 AK |
62 | #define __ex_clear(x, reg) \ |
63 | ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg) | |
4ecac3fd | 64 | |
6aa8b732 AK |
65 | MODULE_AUTHOR("Qumranet"); |
66 | MODULE_LICENSE("GPL"); | |
67 | ||
e9bda3b3 JT |
68 | static const struct x86_cpu_id vmx_cpu_id[] = { |
69 | X86_FEATURE_MATCH(X86_FEATURE_VMX), | |
70 | {} | |
71 | }; | |
72 | MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id); | |
73 | ||
476bc001 | 74 | static bool __read_mostly enable_vpid = 1; |
736caefe | 75 | module_param_named(vpid, enable_vpid, bool, 0444); |
2384d2b3 | 76 | |
d02fcf50 PB |
77 | static bool __read_mostly enable_vnmi = 1; |
78 | module_param_named(vnmi, enable_vnmi, bool, S_IRUGO); | |
79 | ||
476bc001 | 80 | static bool __read_mostly flexpriority_enabled = 1; |
736caefe | 81 | module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO); |
4c9fc8ef | 82 | |
476bc001 | 83 | static bool __read_mostly enable_ept = 1; |
736caefe | 84 | module_param_named(ept, enable_ept, bool, S_IRUGO); |
d56f546d | 85 | |
476bc001 | 86 | static bool __read_mostly enable_unrestricted_guest = 1; |
3a624e29 NK |
87 | module_param_named(unrestricted_guest, |
88 | enable_unrestricted_guest, bool, S_IRUGO); | |
89 | ||
83c3a331 XH |
90 | static bool __read_mostly enable_ept_ad_bits = 1; |
91 | module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO); | |
92 | ||
a27685c3 | 93 | static bool __read_mostly emulate_invalid_guest_state = true; |
c1f8bc04 | 94 | module_param(emulate_invalid_guest_state, bool, S_IRUGO); |
04fa4d32 | 95 | |
476bc001 | 96 | static bool __read_mostly fasteoi = 1; |
58fbbf26 KT |
97 | module_param(fasteoi, bool, S_IRUGO); |
98 | ||
5a71785d | 99 | static bool __read_mostly enable_apicv = 1; |
01e439be | 100 | module_param(enable_apicv, bool, S_IRUGO); |
83d4c286 | 101 | |
abc4fc58 AG |
102 | static bool __read_mostly enable_shadow_vmcs = 1; |
103 | module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO); | |
801d3424 NHE |
104 | /* |
105 | * If nested=1, nested virtualization is supported, i.e., guests may use | |
106 | * VMX and be a hypervisor for its own guests. If nested=0, guests may not | |
107 | * use VMX instructions. | |
108 | */ | |
476bc001 | 109 | static bool __read_mostly nested = 0; |
801d3424 NHE |
110 | module_param(nested, bool, S_IRUGO); |
111 | ||
20300099 WL |
112 | static u64 __read_mostly host_xss; |
113 | ||
843e4330 KH |
114 | static bool __read_mostly enable_pml = 1; |
115 | module_param_named(pml, enable_pml, bool, S_IRUGO); | |
116 | ||
4b0be90f PB |
117 | #define MSR_TYPE_R 1 |
118 | #define MSR_TYPE_W 2 | |
119 | #define MSR_TYPE_RW 3 | |
120 | ||
121 | #define MSR_BITMAP_MODE_X2APIC 1 | |
122 | #define MSR_BITMAP_MODE_X2APIC_APICV 2 | |
123 | #define MSR_BITMAP_MODE_LM 4 | |
124 | ||
64903d61 HZ |
125 | #define KVM_VMX_TSC_MULTIPLIER_MAX 0xffffffffffffffffULL |
126 | ||
64672c95 YJ |
127 | /* Guest_tsc -> host_tsc conversion requires 64-bit division. */ |
128 | static int __read_mostly cpu_preemption_timer_multi; | |
129 | static bool __read_mostly enable_preemption_timer = 1; | |
130 | #ifdef CONFIG_X86_64 | |
131 | module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO); | |
132 | #endif | |
133 | ||
5037878e GN |
134 | #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD) |
135 | #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE) | |
cdc0e244 AK |
136 | #define KVM_VM_CR0_ALWAYS_ON \ |
137 | (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE) | |
4c38609a AK |
138 | #define KVM_CR4_GUEST_OWNED_BITS \ |
139 | (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \ | |
fd8cb433 | 140 | | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_TSD) |
4c38609a | 141 | |
cdc0e244 AK |
142 | #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE) |
143 | #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE) | |
144 | ||
78ac8b47 AK |
145 | #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM)) |
146 | ||
f4124500 JK |
147 | #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5 |
148 | ||
16c2aec6 JD |
149 | /* |
150 | * Hyper-V requires all of these, so mark them as supported even though | |
151 | * they are just treated the same as all-context. | |
152 | */ | |
153 | #define VMX_VPID_EXTENT_SUPPORTED_MASK \ | |
154 | (VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT | \ | |
155 | VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT | \ | |
156 | VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT | \ | |
157 | VMX_VPID_EXTENT_SINGLE_NON_GLOBAL_BIT) | |
158 | ||
4b8d54f9 ZE |
159 | /* |
160 | * These 2 parameters are used to config the controls for Pause-Loop Exiting: | |
161 | * ple_gap: upper bound on the amount of time between two successive | |
162 | * executions of PAUSE in a loop. Also indicate if ple enabled. | |
00c25bce | 163 | * According to test, this time is usually smaller than 128 cycles. |
4b8d54f9 ZE |
164 | * ple_window: upper bound on the amount of time a guest is allowed to execute |
165 | * in a PAUSE loop. Tests indicate that most spinlocks are held for | |
166 | * less than 2^12 cycles | |
167 | * Time is measured based on a counter that runs at the same rate as the TSC, | |
168 | * refer SDM volume 3b section 21.6.13 & 22.1.3. | |
169 | */ | |
b4a2d31d RK |
170 | #define KVM_VMX_DEFAULT_PLE_GAP 128 |
171 | #define KVM_VMX_DEFAULT_PLE_WINDOW 4096 | |
172 | #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW 2 | |
173 | #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0 | |
174 | #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX \ | |
175 | INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW | |
176 | ||
4b8d54f9 ZE |
177 | static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP; |
178 | module_param(ple_gap, int, S_IRUGO); | |
179 | ||
180 | static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW; | |
181 | module_param(ple_window, int, S_IRUGO); | |
182 | ||
b4a2d31d RK |
183 | /* Default doubles per-vcpu window every exit. */ |
184 | static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW; | |
185 | module_param(ple_window_grow, int, S_IRUGO); | |
186 | ||
187 | /* Default resets per-vcpu window every exit to ple_window. */ | |
188 | static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK; | |
189 | module_param(ple_window_shrink, int, S_IRUGO); | |
190 | ||
191 | /* Default is to compute the maximum so we can never overflow. */ | |
192 | static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX; | |
193 | static int ple_window_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX; | |
194 | module_param(ple_window_max, int, S_IRUGO); | |
195 | ||
83287ea4 AK |
196 | extern const ulong vmx_return; |
197 | ||
1749555e | 198 | static DEFINE_STATIC_KEY_FALSE(vmx_l1d_should_flush); |
12960b11 | 199 | static DEFINE_STATIC_KEY_FALSE(vmx_l1d_flush_cond); |
eeec2ec1 | 200 | static DEFINE_MUTEX(vmx_l1d_flush_mutex); |
1749555e | 201 | |
2bcd5b01 TG |
202 | /* Storage for pre module init parameter parsing */ |
203 | static enum vmx_l1d_flush_state __read_mostly vmentry_l1d_flush_param = VMENTER_L1D_FLUSH_AUTO; | |
1749555e KRW |
204 | |
205 | static const struct { | |
206 | const char *option; | |
1dd6f98d | 207 | bool for_parse; |
1749555e | 208 | } vmentry_l1d_param[] = { |
1dd6f98d PB |
209 | [VMENTER_L1D_FLUSH_AUTO] = {"auto", true}, |
210 | [VMENTER_L1D_FLUSH_NEVER] = {"never", true}, | |
211 | [VMENTER_L1D_FLUSH_COND] = {"cond", true}, | |
212 | [VMENTER_L1D_FLUSH_ALWAYS] = {"always", true}, | |
213 | [VMENTER_L1D_FLUSH_EPT_DISABLED] = {"EPT disabled", false}, | |
214 | [VMENTER_L1D_FLUSH_NOT_REQUIRED] = {"not required", false}, | |
1749555e KRW |
215 | }; |
216 | ||
2bcd5b01 TG |
217 | #define L1D_CACHE_ORDER 4 |
218 | static void *vmx_l1d_flush_pages; | |
219 | ||
220 | static int vmx_setup_l1d_flush(enum vmx_l1d_flush_state l1tf) | |
1749555e | 221 | { |
2bcd5b01 | 222 | struct page *page; |
55bd6950 | 223 | unsigned int i; |
1749555e | 224 | |
2bcd5b01 TG |
225 | if (!enable_ept) { |
226 | l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_EPT_DISABLED; | |
227 | return 0; | |
228 | } | |
229 | ||
917d427f JH |
230 | if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) { |
231 | u64 msr; | |
232 | ||
233 | rdmsrl(MSR_IA32_ARCH_CAPABILITIES, msr); | |
234 | if (msr & ARCH_CAP_SKIP_VMENTRY_L1DFLUSH) { | |
235 | l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED; | |
236 | return 0; | |
237 | } | |
238 | } | |
364a4311 | 239 | |
24fcb53c JK |
240 | /* If set to auto use the default l1tf mitigation method */ |
241 | if (l1tf == VMENTER_L1D_FLUSH_AUTO) { | |
242 | switch (l1tf_mitigation) { | |
243 | case L1TF_MITIGATION_OFF: | |
244 | l1tf = VMENTER_L1D_FLUSH_NEVER; | |
245 | break; | |
246 | case L1TF_MITIGATION_FLUSH_NOWARN: | |
247 | case L1TF_MITIGATION_FLUSH: | |
248 | case L1TF_MITIGATION_FLUSH_NOSMT: | |
249 | l1tf = VMENTER_L1D_FLUSH_COND; | |
250 | break; | |
251 | case L1TF_MITIGATION_FULL: | |
252 | case L1TF_MITIGATION_FULL_FORCE: | |
253 | l1tf = VMENTER_L1D_FLUSH_ALWAYS; | |
254 | break; | |
255 | } | |
256 | } else if (l1tf_mitigation == L1TF_MITIGATION_FULL_FORCE) { | |
257 | l1tf = VMENTER_L1D_FLUSH_ALWAYS; | |
258 | } | |
259 | ||
2bcd5b01 TG |
260 | if (l1tf != VMENTER_L1D_FLUSH_NEVER && !vmx_l1d_flush_pages && |
261 | !boot_cpu_has(X86_FEATURE_FLUSH_L1D)) { | |
262 | page = alloc_pages(GFP_KERNEL, L1D_CACHE_ORDER); | |
263 | if (!page) | |
264 | return -ENOMEM; | |
265 | vmx_l1d_flush_pages = page_address(page); | |
55bd6950 NS |
266 | |
267 | /* | |
268 | * Initialize each page with a different pattern in | |
269 | * order to protect against KSM in the nested | |
270 | * virtualization case. | |
271 | */ | |
272 | for (i = 0; i < 1u << L1D_CACHE_ORDER; ++i) { | |
273 | memset(vmx_l1d_flush_pages + i * PAGE_SIZE, i + 1, | |
274 | PAGE_SIZE); | |
275 | } | |
1749555e KRW |
276 | } |
277 | ||
2bcd5b01 TG |
278 | l1tf_vmx_mitigation = l1tf; |
279 | ||
522c7bed TG |
280 | if (l1tf != VMENTER_L1D_FLUSH_NEVER) |
281 | static_branch_enable(&vmx_l1d_should_flush); | |
282 | else | |
283 | static_branch_disable(&vmx_l1d_should_flush); | |
ae021965 | 284 | |
12960b11 NS |
285 | if (l1tf == VMENTER_L1D_FLUSH_COND) |
286 | static_branch_enable(&vmx_l1d_flush_cond); | |
522c7bed | 287 | else |
12960b11 | 288 | static_branch_disable(&vmx_l1d_flush_cond); |
2bcd5b01 TG |
289 | return 0; |
290 | } | |
291 | ||
292 | static int vmentry_l1d_flush_parse(const char *s) | |
293 | { | |
294 | unsigned int i; | |
295 | ||
296 | if (s) { | |
297 | for (i = 0; i < ARRAY_SIZE(vmentry_l1d_param); i++) { | |
1dd6f98d PB |
298 | if (vmentry_l1d_param[i].for_parse && |
299 | sysfs_streq(s, vmentry_l1d_param[i].option)) | |
300 | return i; | |
2bcd5b01 TG |
301 | } |
302 | } | |
1749555e KRW |
303 | return -EINVAL; |
304 | } | |
305 | ||
2bcd5b01 TG |
306 | static int vmentry_l1d_flush_set(const char *s, const struct kernel_param *kp) |
307 | { | |
eeec2ec1 | 308 | int l1tf, ret; |
2bcd5b01 | 309 | |
2bcd5b01 TG |
310 | l1tf = vmentry_l1d_flush_parse(s); |
311 | if (l1tf < 0) | |
312 | return l1tf; | |
313 | ||
1dd6f98d PB |
314 | if (!boot_cpu_has(X86_BUG_L1TF)) |
315 | return 0; | |
316 | ||
2bcd5b01 TG |
317 | /* |
318 | * Has vmx_init() run already? If not then this is the pre init | |
319 | * parameter parsing. In that case just store the value and let | |
320 | * vmx_init() do the proper setup after enable_ept has been | |
321 | * established. | |
322 | */ | |
323 | if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO) { | |
324 | vmentry_l1d_flush_param = l1tf; | |
325 | return 0; | |
326 | } | |
327 | ||
eeec2ec1 TG |
328 | mutex_lock(&vmx_l1d_flush_mutex); |
329 | ret = vmx_setup_l1d_flush(l1tf); | |
330 | mutex_unlock(&vmx_l1d_flush_mutex); | |
331 | return ret; | |
2bcd5b01 TG |
332 | } |
333 | ||
1749555e KRW |
334 | static int vmentry_l1d_flush_get(char *s, const struct kernel_param *kp) |
335 | { | |
1dd6f98d PB |
336 | if (WARN_ON_ONCE(l1tf_vmx_mitigation >= ARRAY_SIZE(vmentry_l1d_param))) |
337 | return sprintf(s, "???\n"); | |
338 | ||
2bcd5b01 | 339 | return sprintf(s, "%s\n", vmentry_l1d_param[l1tf_vmx_mitigation].option); |
1749555e KRW |
340 | } |
341 | ||
342 | static const struct kernel_param_ops vmentry_l1d_flush_ops = { | |
343 | .set = vmentry_l1d_flush_set, | |
344 | .get = vmentry_l1d_flush_get, | |
345 | }; | |
522c7bed | 346 | module_param_cb(vmentry_l1d_flush, &vmentry_l1d_flush_ops, NULL, 0644); |
1749555e | 347 | |
8bf00a52 | 348 | #define NR_AUTOLOAD_MSRS 8 |
61d2ef2c | 349 | |
a2fa3e9f GH |
350 | struct vmcs { |
351 | u32 revision_id; | |
352 | u32 abort; | |
353 | char data[0]; | |
354 | }; | |
355 | ||
d462b819 NHE |
356 | /* |
357 | * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also | |
358 | * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs | |
359 | * loaded on this CPU (so we can clear them if the CPU goes down). | |
360 | */ | |
361 | struct loaded_vmcs { | |
362 | struct vmcs *vmcs; | |
355f4fb1 | 363 | struct vmcs *shadow_vmcs; |
d462b819 | 364 | int cpu; |
4c4a6f79 PB |
365 | bool launched; |
366 | bool nmi_known_unmasked; | |
44889942 LP |
367 | unsigned long vmcs_host_cr3; /* May not match real cr3 */ |
368 | unsigned long vmcs_host_cr4; /* May not match real cr4 */ | |
8a1b4392 PB |
369 | /* Support for vnmi-less CPUs */ |
370 | int soft_vnmi_blocked; | |
371 | ktime_t entry_time; | |
372 | s64 vnmi_blocked_time; | |
4b0be90f | 373 | unsigned long *msr_bitmap; |
d462b819 NHE |
374 | struct list_head loaded_vmcss_on_cpu_link; |
375 | }; | |
376 | ||
26bb0981 AK |
377 | struct shared_msr_entry { |
378 | unsigned index; | |
379 | u64 data; | |
d5696725 | 380 | u64 mask; |
26bb0981 AK |
381 | }; |
382 | ||
a9d30f33 NHE |
383 | /* |
384 | * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a | |
385 | * single nested guest (L2), hence the name vmcs12. Any VMX implementation has | |
386 | * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is | |
387 | * stored in guest memory specified by VMPTRLD, but is opaque to the guest, | |
388 | * which must access it using VMREAD/VMWRITE/VMCLEAR instructions. | |
389 | * More than one of these structures may exist, if L1 runs multiple L2 guests. | |
8819227c | 390 | * nested_vmx_run() will use the data here to build the vmcs02: a VMCS for the |
a9d30f33 NHE |
391 | * underlying hardware which will be used to run L2. |
392 | * This structure is packed to ensure that its layout is identical across | |
393 | * machines (necessary for live migration). | |
394 | * If there are changes in this struct, VMCS12_REVISION must be changed. | |
395 | */ | |
22bd0358 | 396 | typedef u64 natural_width; |
a9d30f33 NHE |
397 | struct __packed vmcs12 { |
398 | /* According to the Intel spec, a VMCS region must start with the | |
399 | * following two fields. Then follow implementation-specific data. | |
400 | */ | |
401 | u32 revision_id; | |
402 | u32 abort; | |
22bd0358 | 403 | |
27d6c865 NHE |
404 | u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */ |
405 | u32 padding[7]; /* room for future expansion */ | |
406 | ||
22bd0358 NHE |
407 | u64 io_bitmap_a; |
408 | u64 io_bitmap_b; | |
409 | u64 msr_bitmap; | |
410 | u64 vm_exit_msr_store_addr; | |
411 | u64 vm_exit_msr_load_addr; | |
412 | u64 vm_entry_msr_load_addr; | |
413 | u64 tsc_offset; | |
414 | u64 virtual_apic_page_addr; | |
415 | u64 apic_access_addr; | |
705699a1 | 416 | u64 posted_intr_desc_addr; |
27c42a1b | 417 | u64 vm_function_control; |
22bd0358 | 418 | u64 ept_pointer; |
608406e2 WV |
419 | u64 eoi_exit_bitmap0; |
420 | u64 eoi_exit_bitmap1; | |
421 | u64 eoi_exit_bitmap2; | |
422 | u64 eoi_exit_bitmap3; | |
41ab9372 | 423 | u64 eptp_list_address; |
81dc01f7 | 424 | u64 xss_exit_bitmap; |
22bd0358 NHE |
425 | u64 guest_physical_address; |
426 | u64 vmcs_link_pointer; | |
c5f983f6 | 427 | u64 pml_address; |
22bd0358 NHE |
428 | u64 guest_ia32_debugctl; |
429 | u64 guest_ia32_pat; | |
430 | u64 guest_ia32_efer; | |
431 | u64 guest_ia32_perf_global_ctrl; | |
432 | u64 guest_pdptr0; | |
433 | u64 guest_pdptr1; | |
434 | u64 guest_pdptr2; | |
435 | u64 guest_pdptr3; | |
36be0b9d | 436 | u64 guest_bndcfgs; |
22bd0358 NHE |
437 | u64 host_ia32_pat; |
438 | u64 host_ia32_efer; | |
439 | u64 host_ia32_perf_global_ctrl; | |
440 | u64 padding64[8]; /* room for future expansion */ | |
441 | /* | |
442 | * To allow migration of L1 (complete with its L2 guests) between | |
443 | * machines of different natural widths (32 or 64 bit), we cannot have | |
444 | * unsigned long fields with no explict size. We use u64 (aliased | |
445 | * natural_width) instead. Luckily, x86 is little-endian. | |
446 | */ | |
447 | natural_width cr0_guest_host_mask; | |
448 | natural_width cr4_guest_host_mask; | |
449 | natural_width cr0_read_shadow; | |
450 | natural_width cr4_read_shadow; | |
451 | natural_width cr3_target_value0; | |
452 | natural_width cr3_target_value1; | |
453 | natural_width cr3_target_value2; | |
454 | natural_width cr3_target_value3; | |
455 | natural_width exit_qualification; | |
456 | natural_width guest_linear_address; | |
457 | natural_width guest_cr0; | |
458 | natural_width guest_cr3; | |
459 | natural_width guest_cr4; | |
460 | natural_width guest_es_base; | |
461 | natural_width guest_cs_base; | |
462 | natural_width guest_ss_base; | |
463 | natural_width guest_ds_base; | |
464 | natural_width guest_fs_base; | |
465 | natural_width guest_gs_base; | |
466 | natural_width guest_ldtr_base; | |
467 | natural_width guest_tr_base; | |
468 | natural_width guest_gdtr_base; | |
469 | natural_width guest_idtr_base; | |
470 | natural_width guest_dr7; | |
471 | natural_width guest_rsp; | |
472 | natural_width guest_rip; | |
473 | natural_width guest_rflags; | |
474 | natural_width guest_pending_dbg_exceptions; | |
475 | natural_width guest_sysenter_esp; | |
476 | natural_width guest_sysenter_eip; | |
477 | natural_width host_cr0; | |
478 | natural_width host_cr3; | |
479 | natural_width host_cr4; | |
480 | natural_width host_fs_base; | |
481 | natural_width host_gs_base; | |
482 | natural_width host_tr_base; | |
483 | natural_width host_gdtr_base; | |
484 | natural_width host_idtr_base; | |
485 | natural_width host_ia32_sysenter_esp; | |
486 | natural_width host_ia32_sysenter_eip; | |
487 | natural_width host_rsp; | |
488 | natural_width host_rip; | |
489 | natural_width paddingl[8]; /* room for future expansion */ | |
490 | u32 pin_based_vm_exec_control; | |
491 | u32 cpu_based_vm_exec_control; | |
492 | u32 exception_bitmap; | |
493 | u32 page_fault_error_code_mask; | |
494 | u32 page_fault_error_code_match; | |
495 | u32 cr3_target_count; | |
496 | u32 vm_exit_controls; | |
497 | u32 vm_exit_msr_store_count; | |
498 | u32 vm_exit_msr_load_count; | |
499 | u32 vm_entry_controls; | |
500 | u32 vm_entry_msr_load_count; | |
501 | u32 vm_entry_intr_info_field; | |
502 | u32 vm_entry_exception_error_code; | |
503 | u32 vm_entry_instruction_len; | |
504 | u32 tpr_threshold; | |
505 | u32 secondary_vm_exec_control; | |
506 | u32 vm_instruction_error; | |
507 | u32 vm_exit_reason; | |
508 | u32 vm_exit_intr_info; | |
509 | u32 vm_exit_intr_error_code; | |
510 | u32 idt_vectoring_info_field; | |
511 | u32 idt_vectoring_error_code; | |
512 | u32 vm_exit_instruction_len; | |
513 | u32 vmx_instruction_info; | |
514 | u32 guest_es_limit; | |
515 | u32 guest_cs_limit; | |
516 | u32 guest_ss_limit; | |
517 | u32 guest_ds_limit; | |
518 | u32 guest_fs_limit; | |
519 | u32 guest_gs_limit; | |
520 | u32 guest_ldtr_limit; | |
521 | u32 guest_tr_limit; | |
522 | u32 guest_gdtr_limit; | |
523 | u32 guest_idtr_limit; | |
524 | u32 guest_es_ar_bytes; | |
525 | u32 guest_cs_ar_bytes; | |
526 | u32 guest_ss_ar_bytes; | |
527 | u32 guest_ds_ar_bytes; | |
528 | u32 guest_fs_ar_bytes; | |
529 | u32 guest_gs_ar_bytes; | |
530 | u32 guest_ldtr_ar_bytes; | |
531 | u32 guest_tr_ar_bytes; | |
532 | u32 guest_interruptibility_info; | |
533 | u32 guest_activity_state; | |
534 | u32 guest_sysenter_cs; | |
535 | u32 host_ia32_sysenter_cs; | |
0238ea91 JK |
536 | u32 vmx_preemption_timer_value; |
537 | u32 padding32[7]; /* room for future expansion */ | |
22bd0358 | 538 | u16 virtual_processor_id; |
705699a1 | 539 | u16 posted_intr_nv; |
22bd0358 NHE |
540 | u16 guest_es_selector; |
541 | u16 guest_cs_selector; | |
542 | u16 guest_ss_selector; | |
543 | u16 guest_ds_selector; | |
544 | u16 guest_fs_selector; | |
545 | u16 guest_gs_selector; | |
546 | u16 guest_ldtr_selector; | |
547 | u16 guest_tr_selector; | |
608406e2 | 548 | u16 guest_intr_status; |
c5f983f6 | 549 | u16 guest_pml_index; |
22bd0358 NHE |
550 | u16 host_es_selector; |
551 | u16 host_cs_selector; | |
552 | u16 host_ss_selector; | |
553 | u16 host_ds_selector; | |
554 | u16 host_fs_selector; | |
555 | u16 host_gs_selector; | |
556 | u16 host_tr_selector; | |
a9d30f33 NHE |
557 | }; |
558 | ||
559 | /* | |
560 | * VMCS12_REVISION is an arbitrary id that should be changed if the content or | |
561 | * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and | |
562 | * VMPTRLD verifies that the VMCS region that L1 is loading contains this id. | |
563 | */ | |
564 | #define VMCS12_REVISION 0x11e57ed0 | |
565 | ||
566 | /* | |
567 | * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region | |
568 | * and any VMCS region. Although only sizeof(struct vmcs12) are used by the | |
569 | * current implementation, 4K are reserved to avoid future complications. | |
570 | */ | |
571 | #define VMCS12_SIZE 0x1000 | |
572 | ||
ec378aee NHE |
573 | /* |
574 | * The nested_vmx structure is part of vcpu_vmx, and holds information we need | |
575 | * for correct emulation of VMX (i.e., nested VMX) on this vcpu. | |
576 | */ | |
577 | struct nested_vmx { | |
578 | /* Has the level1 guest done vmxon? */ | |
579 | bool vmxon; | |
3573e22c | 580 | gpa_t vmxon_ptr; |
c5f983f6 | 581 | bool pml_full; |
a9d30f33 NHE |
582 | |
583 | /* The guest-physical address of the current VMCS L1 keeps for L2 */ | |
584 | gpa_t current_vmptr; | |
4f2777bc DM |
585 | /* |
586 | * Cache of the guest's VMCS, existing outside of guest memory. | |
587 | * Loaded from guest memory during VMPTRLD. Flushed to guest | |
8ca44e88 | 588 | * memory during VMCLEAR and VMPTRLD. |
4f2777bc DM |
589 | */ |
590 | struct vmcs12 *cached_vmcs12; | |
012f83cb AG |
591 | /* |
592 | * Indicates if the shadow vmcs must be updated with the | |
593 | * data hold by vmcs12 | |
594 | */ | |
595 | bool sync_shadow_vmcs; | |
ff2f6fe9 | 596 | |
d3f4c0a5 JM |
597 | bool change_vmcs01_virtual_apic_mode; |
598 | ||
644d711a NHE |
599 | /* L2 must run next, and mustn't decide to exit to L1. */ |
600 | bool nested_run_pending; | |
8819227c JM |
601 | |
602 | struct loaded_vmcs vmcs02; | |
603 | ||
fe3ef05c | 604 | /* |
8819227c JM |
605 | * Guest pages referred to in the vmcs02 with host-physical |
606 | * pointers, so we must keep them pinned while L2 runs. | |
fe3ef05c NHE |
607 | */ |
608 | struct page *apic_access_page; | |
a7c0b07d | 609 | struct page *virtual_apic_page; |
705699a1 WV |
610 | struct page *pi_desc_page; |
611 | struct pi_desc *pi_desc; | |
612 | bool pi_pending; | |
613 | u16 posted_intr_nv; | |
f4124500 JK |
614 | |
615 | struct hrtimer preemption_timer; | |
616 | bool preemption_timer_expired; | |
2996fca0 JK |
617 | |
618 | /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */ | |
619 | u64 vmcs01_debugctl; | |
b9c237bb | 620 | |
5c614b35 WL |
621 | u16 vpid02; |
622 | u16 last_vpid; | |
623 | ||
0115f9cb DM |
624 | /* |
625 | * We only store the "true" versions of the VMX capability MSRs. We | |
626 | * generate the "non-true" versions by setting the must-be-1 bits | |
627 | * according to the SDM. | |
628 | */ | |
b9c237bb WV |
629 | u32 nested_vmx_procbased_ctls_low; |
630 | u32 nested_vmx_procbased_ctls_high; | |
b9c237bb WV |
631 | u32 nested_vmx_secondary_ctls_low; |
632 | u32 nested_vmx_secondary_ctls_high; | |
633 | u32 nested_vmx_pinbased_ctls_low; | |
634 | u32 nested_vmx_pinbased_ctls_high; | |
635 | u32 nested_vmx_exit_ctls_low; | |
636 | u32 nested_vmx_exit_ctls_high; | |
b9c237bb WV |
637 | u32 nested_vmx_entry_ctls_low; |
638 | u32 nested_vmx_entry_ctls_high; | |
b9c237bb WV |
639 | u32 nested_vmx_misc_low; |
640 | u32 nested_vmx_misc_high; | |
641 | u32 nested_vmx_ept_caps; | |
99b83ac8 | 642 | u32 nested_vmx_vpid_caps; |
62cc6b9d DM |
643 | u64 nested_vmx_basic; |
644 | u64 nested_vmx_cr0_fixed0; | |
645 | u64 nested_vmx_cr0_fixed1; | |
646 | u64 nested_vmx_cr4_fixed0; | |
647 | u64 nested_vmx_cr4_fixed1; | |
648 | u64 nested_vmx_vmcs_enum; | |
27c42a1b | 649 | u64 nested_vmx_vmfunc_controls; |
72e9cbdb LP |
650 | |
651 | /* SMM related state */ | |
652 | struct { | |
653 | /* in VMX operation on SMM entry? */ | |
654 | bool vmxon; | |
655 | /* in guest mode on SMM entry? */ | |
656 | bool guest_mode; | |
657 | } smm; | |
ec378aee NHE |
658 | }; |
659 | ||
01e439be | 660 | #define POSTED_INTR_ON 0 |
ebbfc765 FW |
661 | #define POSTED_INTR_SN 1 |
662 | ||
01e439be YZ |
663 | /* Posted-Interrupt Descriptor */ |
664 | struct pi_desc { | |
665 | u32 pir[8]; /* Posted interrupt requested */ | |
6ef1522f FW |
666 | union { |
667 | struct { | |
668 | /* bit 256 - Outstanding Notification */ | |
669 | u16 on : 1, | |
670 | /* bit 257 - Suppress Notification */ | |
671 | sn : 1, | |
672 | /* bit 271:258 - Reserved */ | |
673 | rsvd_1 : 14; | |
674 | /* bit 279:272 - Notification Vector */ | |
675 | u8 nv; | |
676 | /* bit 287:280 - Reserved */ | |
677 | u8 rsvd_2; | |
678 | /* bit 319:288 - Notification Destination */ | |
679 | u32 ndst; | |
680 | }; | |
681 | u64 control; | |
682 | }; | |
683 | u32 rsvd[6]; | |
01e439be YZ |
684 | } __aligned(64); |
685 | ||
a20ed54d YZ |
686 | static bool pi_test_and_set_on(struct pi_desc *pi_desc) |
687 | { | |
688 | return test_and_set_bit(POSTED_INTR_ON, | |
689 | (unsigned long *)&pi_desc->control); | |
690 | } | |
691 | ||
692 | static bool pi_test_and_clear_on(struct pi_desc *pi_desc) | |
693 | { | |
694 | return test_and_clear_bit(POSTED_INTR_ON, | |
695 | (unsigned long *)&pi_desc->control); | |
696 | } | |
697 | ||
698 | static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc) | |
699 | { | |
700 | return test_and_set_bit(vector, (unsigned long *)pi_desc->pir); | |
701 | } | |
702 | ||
ebbfc765 FW |
703 | static inline void pi_clear_sn(struct pi_desc *pi_desc) |
704 | { | |
705 | return clear_bit(POSTED_INTR_SN, | |
706 | (unsigned long *)&pi_desc->control); | |
707 | } | |
708 | ||
709 | static inline void pi_set_sn(struct pi_desc *pi_desc) | |
710 | { | |
711 | return set_bit(POSTED_INTR_SN, | |
712 | (unsigned long *)&pi_desc->control); | |
713 | } | |
714 | ||
ad361091 PB |
715 | static inline void pi_clear_on(struct pi_desc *pi_desc) |
716 | { | |
717 | clear_bit(POSTED_INTR_ON, | |
718 | (unsigned long *)&pi_desc->control); | |
719 | } | |
720 | ||
ebbfc765 FW |
721 | static inline int pi_test_on(struct pi_desc *pi_desc) |
722 | { | |
723 | return test_bit(POSTED_INTR_ON, | |
724 | (unsigned long *)&pi_desc->control); | |
725 | } | |
726 | ||
727 | static inline int pi_test_sn(struct pi_desc *pi_desc) | |
728 | { | |
729 | return test_bit(POSTED_INTR_SN, | |
730 | (unsigned long *)&pi_desc->control); | |
731 | } | |
732 | ||
6e3dedb6 KRW |
733 | struct vmx_msrs { |
734 | unsigned int nr; | |
735 | struct vmx_msr_entry val[NR_AUTOLOAD_MSRS]; | |
736 | }; | |
737 | ||
a2fa3e9f | 738 | struct vcpu_vmx { |
fb3f0f51 | 739 | struct kvm_vcpu vcpu; |
313dbd49 | 740 | unsigned long host_rsp; |
29bd8a78 | 741 | u8 fail; |
4b0be90f | 742 | u8 msr_bitmap_mode; |
51aa01d1 | 743 | u32 exit_intr_info; |
1155f76a | 744 | u32 idt_vectoring_info; |
6de12732 | 745 | ulong rflags; |
26bb0981 | 746 | struct shared_msr_entry *guest_msrs; |
a2fa3e9f GH |
747 | int nmsrs; |
748 | int save_nmsrs; | |
a547c6db | 749 | unsigned long host_idt_base; |
a2fa3e9f | 750 | #ifdef CONFIG_X86_64 |
44ea2b17 AK |
751 | u64 msr_host_kernel_gs_base; |
752 | u64 msr_guest_kernel_gs_base; | |
a2fa3e9f | 753 | #endif |
33241bfe | 754 | |
74469996 | 755 | u64 spec_ctrl; |
a6005a79 | 756 | |
2961e876 GN |
757 | u32 vm_entry_controls_shadow; |
758 | u32 vm_exit_controls_shadow; | |
80154d77 PB |
759 | u32 secondary_exec_control; |
760 | ||
d462b819 NHE |
761 | /* |
762 | * loaded_vmcs points to the VMCS currently used in this vcpu. For a | |
763 | * non-nested (L1) guest, it always points to vmcs01. For a nested | |
8a12167a SC |
764 | * guest (L2), it points to a different VMCS. loaded_cpu_state points |
765 | * to the VMCS whose state is loaded into the CPU registers that only | |
766 | * need to be switched when transitioning to/from the kernel; a NULL | |
767 | * value indicates that host state is loaded. | |
d462b819 NHE |
768 | */ |
769 | struct loaded_vmcs vmcs01; | |
770 | struct loaded_vmcs *loaded_vmcs; | |
8a12167a | 771 | struct loaded_vmcs *loaded_cpu_state; |
d462b819 | 772 | bool __launched; /* temporary, used in vmx_vcpu_run */ |
61d2ef2c | 773 | struct msr_autoload { |
6e3dedb6 KRW |
774 | struct vmx_msrs guest; |
775 | struct vmx_msrs host; | |
61d2ef2c | 776 | } msr_autoload; |
8a12167a | 777 | |
a2fa3e9f | 778 | struct { |
a2fa3e9f | 779 | u16 fs_sel, gs_sel, ldt_sel; |
b2da15ac AK |
780 | #ifdef CONFIG_X86_64 |
781 | u16 ds_sel, es_sel; | |
782 | #endif | |
152d3f2f LV |
783 | int gs_ldt_reload_needed; |
784 | int fs_reload_needed; | |
da8999d3 | 785 | u64 msr_host_bndcfgs; |
d77c26fc | 786 | } host_state; |
9c8cba37 | 787 | struct { |
7ffd92c5 | 788 | int vm86_active; |
78ac8b47 | 789 | ulong save_rflags; |
f5f7b2fe AK |
790 | struct kvm_segment segs[8]; |
791 | } rmode; | |
792 | struct { | |
793 | u32 bitmask; /* 4 bits per segment (1 bit per field) */ | |
7ffd92c5 AK |
794 | struct kvm_save_segment { |
795 | u16 selector; | |
796 | unsigned long base; | |
797 | u32 limit; | |
798 | u32 ar; | |
f5f7b2fe | 799 | } seg[8]; |
2fb92db1 | 800 | } segment_cache; |
2384d2b3 | 801 | int vpid; |
04fa4d32 | 802 | bool emulation_required; |
3b86cd99 | 803 | |
a0861c02 | 804 | u32 exit_reason; |
4e47c7a6 | 805 | |
01e439be YZ |
806 | /* Posted interrupt descriptor */ |
807 | struct pi_desc pi_desc; | |
808 | ||
ec378aee NHE |
809 | /* Support for a guest hypervisor (nested VMX) */ |
810 | struct nested_vmx nested; | |
a7653ecd RK |
811 | |
812 | /* Dynamic PLE window. */ | |
813 | int ple_window; | |
814 | bool ple_window_dirty; | |
843e4330 KH |
815 | |
816 | /* Support for PML */ | |
817 | #define PML_ENTITY_NUM 512 | |
818 | struct page *pml_pg; | |
2680d6da | 819 | |
64672c95 YJ |
820 | /* apic deadline value in host tsc */ |
821 | u64 hv_deadline_tsc; | |
822 | ||
2680d6da | 823 | u64 current_tsc_ratio; |
1be0e61c | 824 | |
1be0e61c | 825 | u32 host_pkru; |
3b84080b | 826 | |
37e4c997 HZ |
827 | /* |
828 | * Only bits masked by msr_ia32_feature_control_valid_bits can be set in | |
829 | * msr_ia32_feature_control. FEATURE_CONTROL_LOCKED is always included | |
830 | * in msr_ia32_feature_control_valid_bits. | |
831 | */ | |
3b84080b | 832 | u64 msr_ia32_feature_control; |
37e4c997 | 833 | u64 msr_ia32_feature_control_valid_bits; |
a2fa3e9f GH |
834 | }; |
835 | ||
2fb92db1 AK |
836 | enum segment_cache_field { |
837 | SEG_FIELD_SEL = 0, | |
838 | SEG_FIELD_BASE = 1, | |
839 | SEG_FIELD_LIMIT = 2, | |
840 | SEG_FIELD_AR = 3, | |
841 | ||
842 | SEG_FIELD_NR = 4 | |
843 | }; | |
844 | ||
a2fa3e9f GH |
845 | static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu) |
846 | { | |
fb3f0f51 | 847 | return container_of(vcpu, struct vcpu_vmx, vcpu); |
a2fa3e9f GH |
848 | } |
849 | ||
efc64404 FW |
850 | static struct pi_desc *vcpu_to_pi_desc(struct kvm_vcpu *vcpu) |
851 | { | |
852 | return &(to_vmx(vcpu)->pi_desc); | |
853 | } | |
854 | ||
22bd0358 NHE |
855 | #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x) |
856 | #define FIELD(number, name) [number] = VMCS12_OFFSET(name) | |
857 | #define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \ | |
858 | [number##_HIGH] = VMCS12_OFFSET(name)+4 | |
859 | ||
4607c2d7 | 860 | |
fe2b201b | 861 | static unsigned long shadow_read_only_fields[] = { |
4607c2d7 AG |
862 | /* |
863 | * We do NOT shadow fields that are modified when L0 | |
864 | * traps and emulates any vmx instruction (e.g. VMPTRLD, | |
865 | * VMXON...) executed by L1. | |
866 | * For example, VM_INSTRUCTION_ERROR is read | |
867 | * by L1 if a vmx instruction fails (part of the error path). | |
868 | * Note the code assumes this logic. If for some reason | |
869 | * we start shadowing these fields then we need to | |
870 | * force a shadow sync when L0 emulates vmx instructions | |
871 | * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified | |
872 | * by nested_vmx_failValid) | |
873 | */ | |
874 | VM_EXIT_REASON, | |
875 | VM_EXIT_INTR_INFO, | |
876 | VM_EXIT_INSTRUCTION_LEN, | |
877 | IDT_VECTORING_INFO_FIELD, | |
878 | IDT_VECTORING_ERROR_CODE, | |
879 | VM_EXIT_INTR_ERROR_CODE, | |
880 | EXIT_QUALIFICATION, | |
881 | GUEST_LINEAR_ADDRESS, | |
882 | GUEST_PHYSICAL_ADDRESS | |
883 | }; | |
fe2b201b | 884 | static int max_shadow_read_only_fields = |
4607c2d7 AG |
885 | ARRAY_SIZE(shadow_read_only_fields); |
886 | ||
fe2b201b | 887 | static unsigned long shadow_read_write_fields[] = { |
a7c0b07d | 888 | TPR_THRESHOLD, |
4607c2d7 AG |
889 | GUEST_RIP, |
890 | GUEST_RSP, | |
891 | GUEST_CR0, | |
892 | GUEST_CR3, | |
893 | GUEST_CR4, | |
894 | GUEST_INTERRUPTIBILITY_INFO, | |
895 | GUEST_RFLAGS, | |
896 | GUEST_CS_SELECTOR, | |
897 | GUEST_CS_AR_BYTES, | |
898 | GUEST_CS_LIMIT, | |
899 | GUEST_CS_BASE, | |
900 | GUEST_ES_BASE, | |
36be0b9d | 901 | GUEST_BNDCFGS, |
4607c2d7 AG |
902 | CR0_GUEST_HOST_MASK, |
903 | CR0_READ_SHADOW, | |
904 | CR4_READ_SHADOW, | |
905 | TSC_OFFSET, | |
906 | EXCEPTION_BITMAP, | |
907 | CPU_BASED_VM_EXEC_CONTROL, | |
908 | VM_ENTRY_EXCEPTION_ERROR_CODE, | |
909 | VM_ENTRY_INTR_INFO_FIELD, | |
910 | VM_ENTRY_INSTRUCTION_LEN, | |
911 | VM_ENTRY_EXCEPTION_ERROR_CODE, | |
912 | HOST_FS_BASE, | |
913 | HOST_GS_BASE, | |
914 | HOST_FS_SELECTOR, | |
915 | HOST_GS_SELECTOR | |
916 | }; | |
fe2b201b | 917 | static int max_shadow_read_write_fields = |
4607c2d7 AG |
918 | ARRAY_SIZE(shadow_read_write_fields); |
919 | ||
772e0318 | 920 | static const unsigned short vmcs_field_to_offset_table[] = { |
22bd0358 | 921 | FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id), |
705699a1 | 922 | FIELD(POSTED_INTR_NV, posted_intr_nv), |
22bd0358 NHE |
923 | FIELD(GUEST_ES_SELECTOR, guest_es_selector), |
924 | FIELD(GUEST_CS_SELECTOR, guest_cs_selector), | |
925 | FIELD(GUEST_SS_SELECTOR, guest_ss_selector), | |
926 | FIELD(GUEST_DS_SELECTOR, guest_ds_selector), | |
927 | FIELD(GUEST_FS_SELECTOR, guest_fs_selector), | |
928 | FIELD(GUEST_GS_SELECTOR, guest_gs_selector), | |
929 | FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector), | |
930 | FIELD(GUEST_TR_SELECTOR, guest_tr_selector), | |
608406e2 | 931 | FIELD(GUEST_INTR_STATUS, guest_intr_status), |
c5f983f6 | 932 | FIELD(GUEST_PML_INDEX, guest_pml_index), |
22bd0358 NHE |
933 | FIELD(HOST_ES_SELECTOR, host_es_selector), |
934 | FIELD(HOST_CS_SELECTOR, host_cs_selector), | |
935 | FIELD(HOST_SS_SELECTOR, host_ss_selector), | |
936 | FIELD(HOST_DS_SELECTOR, host_ds_selector), | |
937 | FIELD(HOST_FS_SELECTOR, host_fs_selector), | |
938 | FIELD(HOST_GS_SELECTOR, host_gs_selector), | |
939 | FIELD(HOST_TR_SELECTOR, host_tr_selector), | |
940 | FIELD64(IO_BITMAP_A, io_bitmap_a), | |
941 | FIELD64(IO_BITMAP_B, io_bitmap_b), | |
942 | FIELD64(MSR_BITMAP, msr_bitmap), | |
943 | FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr), | |
944 | FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr), | |
945 | FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr), | |
946 | FIELD64(TSC_OFFSET, tsc_offset), | |
947 | FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr), | |
948 | FIELD64(APIC_ACCESS_ADDR, apic_access_addr), | |
705699a1 | 949 | FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr), |
27c42a1b | 950 | FIELD64(VM_FUNCTION_CONTROL, vm_function_control), |
22bd0358 | 951 | FIELD64(EPT_POINTER, ept_pointer), |
608406e2 WV |
952 | FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0), |
953 | FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1), | |
954 | FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2), | |
955 | FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3), | |
41ab9372 | 956 | FIELD64(EPTP_LIST_ADDRESS, eptp_list_address), |
81dc01f7 | 957 | FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap), |
22bd0358 NHE |
958 | FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address), |
959 | FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer), | |
c5f983f6 | 960 | FIELD64(PML_ADDRESS, pml_address), |
22bd0358 NHE |
961 | FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl), |
962 | FIELD64(GUEST_IA32_PAT, guest_ia32_pat), | |
963 | FIELD64(GUEST_IA32_EFER, guest_ia32_efer), | |
964 | FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl), | |
965 | FIELD64(GUEST_PDPTR0, guest_pdptr0), | |
966 | FIELD64(GUEST_PDPTR1, guest_pdptr1), | |
967 | FIELD64(GUEST_PDPTR2, guest_pdptr2), | |
968 | FIELD64(GUEST_PDPTR3, guest_pdptr3), | |
36be0b9d | 969 | FIELD64(GUEST_BNDCFGS, guest_bndcfgs), |
22bd0358 NHE |
970 | FIELD64(HOST_IA32_PAT, host_ia32_pat), |
971 | FIELD64(HOST_IA32_EFER, host_ia32_efer), | |
972 | FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl), | |
973 | FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control), | |
974 | FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control), | |
975 | FIELD(EXCEPTION_BITMAP, exception_bitmap), | |
976 | FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask), | |
977 | FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match), | |
978 | FIELD(CR3_TARGET_COUNT, cr3_target_count), | |
979 | FIELD(VM_EXIT_CONTROLS, vm_exit_controls), | |
980 | FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count), | |
981 | FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count), | |
982 | FIELD(VM_ENTRY_CONTROLS, vm_entry_controls), | |
983 | FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count), | |
984 | FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field), | |
985 | FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code), | |
986 | FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len), | |
987 | FIELD(TPR_THRESHOLD, tpr_threshold), | |
988 | FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control), | |
989 | FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error), | |
990 | FIELD(VM_EXIT_REASON, vm_exit_reason), | |
991 | FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info), | |
992 | FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code), | |
993 | FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field), | |
994 | FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code), | |
995 | FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len), | |
996 | FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info), | |
997 | FIELD(GUEST_ES_LIMIT, guest_es_limit), | |
998 | FIELD(GUEST_CS_LIMIT, guest_cs_limit), | |
999 | FIELD(GUEST_SS_LIMIT, guest_ss_limit), | |
1000 | FIELD(GUEST_DS_LIMIT, guest_ds_limit), | |
1001 | FIELD(GUEST_FS_LIMIT, guest_fs_limit), | |
1002 | FIELD(GUEST_GS_LIMIT, guest_gs_limit), | |
1003 | FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit), | |
1004 | FIELD(GUEST_TR_LIMIT, guest_tr_limit), | |
1005 | FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit), | |
1006 | FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit), | |
1007 | FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes), | |
1008 | FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes), | |
1009 | FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes), | |
1010 | FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes), | |
1011 | FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes), | |
1012 | FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes), | |
1013 | FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes), | |
1014 | FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes), | |
1015 | FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info), | |
1016 | FIELD(GUEST_ACTIVITY_STATE, guest_activity_state), | |
1017 | FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs), | |
1018 | FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs), | |
0238ea91 | 1019 | FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value), |
22bd0358 NHE |
1020 | FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask), |
1021 | FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask), | |
1022 | FIELD(CR0_READ_SHADOW, cr0_read_shadow), | |
1023 | FIELD(CR4_READ_SHADOW, cr4_read_shadow), | |
1024 | FIELD(CR3_TARGET_VALUE0, cr3_target_value0), | |
1025 | FIELD(CR3_TARGET_VALUE1, cr3_target_value1), | |
1026 | FIELD(CR3_TARGET_VALUE2, cr3_target_value2), | |
1027 | FIELD(CR3_TARGET_VALUE3, cr3_target_value3), | |
1028 | FIELD(EXIT_QUALIFICATION, exit_qualification), | |
1029 | FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address), | |
1030 | FIELD(GUEST_CR0, guest_cr0), | |
1031 | FIELD(GUEST_CR3, guest_cr3), | |
1032 | FIELD(GUEST_CR4, guest_cr4), | |
1033 | FIELD(GUEST_ES_BASE, guest_es_base), | |
1034 | FIELD(GUEST_CS_BASE, guest_cs_base), | |
1035 | FIELD(GUEST_SS_BASE, guest_ss_base), | |
1036 | FIELD(GUEST_DS_BASE, guest_ds_base), | |
1037 | FIELD(GUEST_FS_BASE, guest_fs_base), | |
1038 | FIELD(GUEST_GS_BASE, guest_gs_base), | |
1039 | FIELD(GUEST_LDTR_BASE, guest_ldtr_base), | |
1040 | FIELD(GUEST_TR_BASE, guest_tr_base), | |
1041 | FIELD(GUEST_GDTR_BASE, guest_gdtr_base), | |
1042 | FIELD(GUEST_IDTR_BASE, guest_idtr_base), | |
1043 | FIELD(GUEST_DR7, guest_dr7), | |
1044 | FIELD(GUEST_RSP, guest_rsp), | |
1045 | FIELD(GUEST_RIP, guest_rip), | |
1046 | FIELD(GUEST_RFLAGS, guest_rflags), | |
1047 | FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions), | |
1048 | FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp), | |
1049 | FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip), | |
1050 | FIELD(HOST_CR0, host_cr0), | |
1051 | FIELD(HOST_CR3, host_cr3), | |
1052 | FIELD(HOST_CR4, host_cr4), | |
1053 | FIELD(HOST_FS_BASE, host_fs_base), | |
1054 | FIELD(HOST_GS_BASE, host_gs_base), | |
1055 | FIELD(HOST_TR_BASE, host_tr_base), | |
1056 | FIELD(HOST_GDTR_BASE, host_gdtr_base), | |
1057 | FIELD(HOST_IDTR_BASE, host_idtr_base), | |
1058 | FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp), | |
1059 | FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip), | |
1060 | FIELD(HOST_RSP, host_rsp), | |
1061 | FIELD(HOST_RIP, host_rip), | |
1062 | }; | |
22bd0358 NHE |
1063 | |
1064 | static inline short vmcs_field_to_offset(unsigned long field) | |
1065 | { | |
bcaf287c DW |
1066 | const size_t size = ARRAY_SIZE(vmcs_field_to_offset_table); |
1067 | unsigned short offset; | |
a2ae9df7 | 1068 | |
bcaf287c DW |
1069 | BUILD_BUG_ON(size > SHRT_MAX); |
1070 | if (field >= size) | |
75f139aa AH |
1071 | return -ENOENT; |
1072 | ||
bcaf287c DW |
1073 | field = array_index_nospec(field, size); |
1074 | offset = vmcs_field_to_offset_table[field]; | |
1075 | if (offset == 0) | |
a2ae9df7 | 1076 | return -ENOENT; |
bcaf287c | 1077 | return offset; |
22bd0358 NHE |
1078 | } |
1079 | ||
a9d30f33 NHE |
1080 | static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu) |
1081 | { | |
4f2777bc | 1082 | return to_vmx(vcpu)->nested.cached_vmcs12; |
a9d30f33 NHE |
1083 | } |
1084 | ||
995f00a6 | 1085 | static bool nested_ept_ad_enabled(struct kvm_vcpu *vcpu); |
bfd0a56b | 1086 | static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu); |
995f00a6 | 1087 | static u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa); |
f53cd63c | 1088 | static bool vmx_xsaves_supported(void); |
b246dd5d OW |
1089 | static void vmx_set_segment(struct kvm_vcpu *vcpu, |
1090 | struct kvm_segment *var, int seg); | |
1091 | static void vmx_get_segment(struct kvm_vcpu *vcpu, | |
1092 | struct kvm_segment *var, int seg); | |
d99e4152 GN |
1093 | static bool guest_state_valid(struct kvm_vcpu *vcpu); |
1094 | static u32 vmx_segment_access_rights(struct kvm_segment *var); | |
16f5b903 | 1095 | static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx); |
b96fb439 PB |
1096 | static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu); |
1097 | static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked); | |
1098 | static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12, | |
1099 | u16 error_code); | |
4b0be90f | 1100 | static void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu); |
3861351c | 1101 | static __always_inline void vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, |
33241bfe | 1102 | u32 msr, int type); |
75880a01 | 1103 | |
6aa8b732 AK |
1104 | static DEFINE_PER_CPU(struct vmcs *, vmxarea); |
1105 | static DEFINE_PER_CPU(struct vmcs *, current_vmcs); | |
d462b819 NHE |
1106 | /* |
1107 | * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed | |
1108 | * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it. | |
1109 | */ | |
1110 | static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu); | |
6aa8b732 | 1111 | |
bf9f6ac8 FW |
1112 | /* |
1113 | * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we | |
1114 | * can find which vCPU should be waken up. | |
1115 | */ | |
1116 | static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu); | |
1117 | static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock); | |
1118 | ||
23611332 RK |
1119 | enum { |
1120 | VMX_IO_BITMAP_A, | |
1121 | VMX_IO_BITMAP_B, | |
23611332 RK |
1122 | VMX_VMREAD_BITMAP, |
1123 | VMX_VMWRITE_BITMAP, | |
1124 | VMX_BITMAP_NR | |
1125 | }; | |
1126 | ||
1127 | static unsigned long *vmx_bitmap[VMX_BITMAP_NR]; | |
1128 | ||
1129 | #define vmx_io_bitmap_a (vmx_bitmap[VMX_IO_BITMAP_A]) | |
1130 | #define vmx_io_bitmap_b (vmx_bitmap[VMX_IO_BITMAP_B]) | |
23611332 RK |
1131 | #define vmx_vmread_bitmap (vmx_bitmap[VMX_VMREAD_BITMAP]) |
1132 | #define vmx_vmwrite_bitmap (vmx_bitmap[VMX_VMWRITE_BITMAP]) | |
fdef3ad1 | 1133 | |
110312c8 | 1134 | static bool cpu_has_load_ia32_efer; |
8bf00a52 | 1135 | static bool cpu_has_load_perf_global_ctrl; |
110312c8 | 1136 | |
2384d2b3 SY |
1137 | static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS); |
1138 | static DEFINE_SPINLOCK(vmx_vpid_lock); | |
1139 | ||
1c3d14fe | 1140 | static struct vmcs_config { |
6aa8b732 AK |
1141 | int size; |
1142 | int order; | |
9ac7e3e8 | 1143 | u32 basic_cap; |
6aa8b732 | 1144 | u32 revision_id; |
1c3d14fe YS |
1145 | u32 pin_based_exec_ctrl; |
1146 | u32 cpu_based_exec_ctrl; | |
f78e0e2e | 1147 | u32 cpu_based_2nd_exec_ctrl; |
1c3d14fe YS |
1148 | u32 vmexit_ctrl; |
1149 | u32 vmentry_ctrl; | |
1150 | } vmcs_config; | |
6aa8b732 | 1151 | |
efff9e53 | 1152 | static struct vmx_capability { |
d56f546d SY |
1153 | u32 ept; |
1154 | u32 vpid; | |
1155 | } vmx_capability; | |
1156 | ||
6aa8b732 AK |
1157 | #define VMX_SEGMENT_FIELD(seg) \ |
1158 | [VCPU_SREG_##seg] = { \ | |
1159 | .selector = GUEST_##seg##_SELECTOR, \ | |
1160 | .base = GUEST_##seg##_BASE, \ | |
1161 | .limit = GUEST_##seg##_LIMIT, \ | |
1162 | .ar_bytes = GUEST_##seg##_AR_BYTES, \ | |
1163 | } | |
1164 | ||
772e0318 | 1165 | static const struct kvm_vmx_segment_field { |
6aa8b732 AK |
1166 | unsigned selector; |
1167 | unsigned base; | |
1168 | unsigned limit; | |
1169 | unsigned ar_bytes; | |
1170 | } kvm_vmx_segment_fields[] = { | |
1171 | VMX_SEGMENT_FIELD(CS), | |
1172 | VMX_SEGMENT_FIELD(DS), | |
1173 | VMX_SEGMENT_FIELD(ES), | |
1174 | VMX_SEGMENT_FIELD(FS), | |
1175 | VMX_SEGMENT_FIELD(GS), | |
1176 | VMX_SEGMENT_FIELD(SS), | |
1177 | VMX_SEGMENT_FIELD(TR), | |
1178 | VMX_SEGMENT_FIELD(LDTR), | |
1179 | }; | |
1180 | ||
26bb0981 AK |
1181 | static u64 host_efer; |
1182 | ||
6de4f3ad AK |
1183 | static void ept_save_pdptrs(struct kvm_vcpu *vcpu); |
1184 | ||
4d56c8a7 | 1185 | /* |
8c06585d | 1186 | * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it |
4d56c8a7 AK |
1187 | * away by decrementing the array size. |
1188 | */ | |
6aa8b732 | 1189 | static const u32 vmx_msr_index[] = { |
05b3e0c2 | 1190 | #ifdef CONFIG_X86_64 |
44ea2b17 | 1191 | MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, |
6aa8b732 | 1192 | #endif |
8c06585d | 1193 | MSR_EFER, MSR_TSC_AUX, MSR_STAR, |
6aa8b732 | 1194 | }; |
6aa8b732 | 1195 | |
5bb16016 | 1196 | static inline bool is_exception_n(u32 intr_info, u8 vector) |
6aa8b732 AK |
1197 | { |
1198 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK | | |
1199 | INTR_INFO_VALID_MASK)) == | |
5bb16016 JK |
1200 | (INTR_TYPE_HARD_EXCEPTION | vector | INTR_INFO_VALID_MASK); |
1201 | } | |
1202 | ||
6f05485d JK |
1203 | static inline bool is_debug(u32 intr_info) |
1204 | { | |
1205 | return is_exception_n(intr_info, DB_VECTOR); | |
1206 | } | |
1207 | ||
1208 | static inline bool is_breakpoint(u32 intr_info) | |
1209 | { | |
1210 | return is_exception_n(intr_info, BP_VECTOR); | |
1211 | } | |
1212 | ||
5bb16016 JK |
1213 | static inline bool is_page_fault(u32 intr_info) |
1214 | { | |
1215 | return is_exception_n(intr_info, PF_VECTOR); | |
6aa8b732 AK |
1216 | } |
1217 | ||
31299944 | 1218 | static inline bool is_no_device(u32 intr_info) |
2ab455cc | 1219 | { |
5bb16016 | 1220 | return is_exception_n(intr_info, NM_VECTOR); |
2ab455cc AL |
1221 | } |
1222 | ||
31299944 | 1223 | static inline bool is_invalid_opcode(u32 intr_info) |
7aa81cc0 | 1224 | { |
5bb16016 | 1225 | return is_exception_n(intr_info, UD_VECTOR); |
7aa81cc0 AL |
1226 | } |
1227 | ||
31299944 | 1228 | static inline bool is_external_interrupt(u32 intr_info) |
6aa8b732 AK |
1229 | { |
1230 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK)) | |
1231 | == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK); | |
1232 | } | |
1233 | ||
31299944 | 1234 | static inline bool is_machine_check(u32 intr_info) |
a0861c02 AK |
1235 | { |
1236 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK | | |
1237 | INTR_INFO_VALID_MASK)) == | |
1238 | (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK); | |
1239 | } | |
1240 | ||
3252850d LT |
1241 | /* Undocumented: icebp/int1 */ |
1242 | static inline bool is_icebp(u32 intr_info) | |
1243 | { | |
1244 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK)) | |
1245 | == (INTR_TYPE_PRIV_SW_EXCEPTION | INTR_INFO_VALID_MASK); | |
1246 | } | |
1247 | ||
31299944 | 1248 | static inline bool cpu_has_vmx_msr_bitmap(void) |
25c5f225 | 1249 | { |
04547156 | 1250 | return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS; |
25c5f225 SY |
1251 | } |
1252 | ||
31299944 | 1253 | static inline bool cpu_has_vmx_tpr_shadow(void) |
6e5d865c | 1254 | { |
04547156 | 1255 | return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW; |
6e5d865c YS |
1256 | } |
1257 | ||
35754c98 | 1258 | static inline bool cpu_need_tpr_shadow(struct kvm_vcpu *vcpu) |
6e5d865c | 1259 | { |
35754c98 | 1260 | return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu); |
6e5d865c YS |
1261 | } |
1262 | ||
31299944 | 1263 | static inline bool cpu_has_secondary_exec_ctrls(void) |
f78e0e2e | 1264 | { |
04547156 SY |
1265 | return vmcs_config.cpu_based_exec_ctrl & |
1266 | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS; | |
f78e0e2e SY |
1267 | } |
1268 | ||
774ead3a | 1269 | static inline bool cpu_has_vmx_virtualize_apic_accesses(void) |
f78e0e2e | 1270 | { |
04547156 SY |
1271 | return vmcs_config.cpu_based_2nd_exec_ctrl & |
1272 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; | |
1273 | } | |
1274 | ||
8d14695f YZ |
1275 | static inline bool cpu_has_vmx_virtualize_x2apic_mode(void) |
1276 | { | |
1277 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1278 | SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE; | |
1279 | } | |
1280 | ||
83d4c286 YZ |
1281 | static inline bool cpu_has_vmx_apic_register_virt(void) |
1282 | { | |
1283 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1284 | SECONDARY_EXEC_APIC_REGISTER_VIRT; | |
1285 | } | |
1286 | ||
c7c9c56c YZ |
1287 | static inline bool cpu_has_vmx_virtual_intr_delivery(void) |
1288 | { | |
1289 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1290 | SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY; | |
1291 | } | |
1292 | ||
64672c95 YJ |
1293 | /* |
1294 | * Comment's format: document - errata name - stepping - processor name. | |
1295 | * Refer from | |
1296 | * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp | |
1297 | */ | |
1298 | static u32 vmx_preemption_cpu_tfms[] = { | |
1299 | /* 323344.pdf - BA86 - D0 - Xeon 7500 Series */ | |
1300 | 0x000206E6, | |
1301 | /* 323056.pdf - AAX65 - C2 - Xeon L3406 */ | |
1302 | /* 322814.pdf - AAT59 - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */ | |
1303 | /* 322911.pdf - AAU65 - C2 - i5-600, i3-500 Desktop and Pentium G6950 */ | |
1304 | 0x00020652, | |
1305 | /* 322911.pdf - AAU65 - K0 - i5-600, i3-500 Desktop and Pentium G6950 */ | |
1306 | 0x00020655, | |
1307 | /* 322373.pdf - AAO95 - B1 - Xeon 3400 Series */ | |
1308 | /* 322166.pdf - AAN92 - B1 - i7-800 and i5-700 Desktop */ | |
1309 | /* | |
1310 | * 320767.pdf - AAP86 - B1 - | |
1311 | * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile | |
1312 | */ | |
1313 | 0x000106E5, | |
1314 | /* 321333.pdf - AAM126 - C0 - Xeon 3500 */ | |
1315 | 0x000106A0, | |
1316 | /* 321333.pdf - AAM126 - C1 - Xeon 3500 */ | |
1317 | 0x000106A1, | |
1318 | /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */ | |
1319 | 0x000106A4, | |
1320 | /* 321333.pdf - AAM126 - D0 - Xeon 3500 */ | |
1321 | /* 321324.pdf - AAK139 - D0 - Xeon 5500 */ | |
1322 | /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */ | |
1323 | 0x000106A5, | |
1324 | }; | |
1325 | ||
1326 | static inline bool cpu_has_broken_vmx_preemption_timer(void) | |
1327 | { | |
1328 | u32 eax = cpuid_eax(0x00000001), i; | |
1329 | ||
1330 | /* Clear the reserved bits */ | |
1331 | eax &= ~(0x3U << 14 | 0xfU << 28); | |
03f6a22a | 1332 | for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++) |
64672c95 YJ |
1333 | if (eax == vmx_preemption_cpu_tfms[i]) |
1334 | return true; | |
1335 | ||
1336 | return false; | |
1337 | } | |
1338 | ||
1339 | static inline bool cpu_has_vmx_preemption_timer(void) | |
1340 | { | |
64672c95 YJ |
1341 | return vmcs_config.pin_based_exec_ctrl & |
1342 | PIN_BASED_VMX_PREEMPTION_TIMER; | |
1343 | } | |
1344 | ||
01e439be YZ |
1345 | static inline bool cpu_has_vmx_posted_intr(void) |
1346 | { | |
d6a858d1 PB |
1347 | return IS_ENABLED(CONFIG_X86_LOCAL_APIC) && |
1348 | vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR; | |
01e439be YZ |
1349 | } |
1350 | ||
1351 | static inline bool cpu_has_vmx_apicv(void) | |
1352 | { | |
1353 | return cpu_has_vmx_apic_register_virt() && | |
1354 | cpu_has_vmx_virtual_intr_delivery() && | |
1355 | cpu_has_vmx_posted_intr(); | |
1356 | } | |
1357 | ||
04547156 SY |
1358 | static inline bool cpu_has_vmx_flexpriority(void) |
1359 | { | |
1360 | return cpu_has_vmx_tpr_shadow() && | |
1361 | cpu_has_vmx_virtualize_apic_accesses(); | |
f78e0e2e SY |
1362 | } |
1363 | ||
e799794e MT |
1364 | static inline bool cpu_has_vmx_ept_execute_only(void) |
1365 | { | |
31299944 | 1366 | return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT; |
e799794e MT |
1367 | } |
1368 | ||
e799794e MT |
1369 | static inline bool cpu_has_vmx_ept_2m_page(void) |
1370 | { | |
31299944 | 1371 | return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT; |
e799794e MT |
1372 | } |
1373 | ||
878403b7 SY |
1374 | static inline bool cpu_has_vmx_ept_1g_page(void) |
1375 | { | |
31299944 | 1376 | return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT; |
878403b7 SY |
1377 | } |
1378 | ||
4bc9b982 SY |
1379 | static inline bool cpu_has_vmx_ept_4levels(void) |
1380 | { | |
1381 | return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT; | |
1382 | } | |
1383 | ||
42aa53b4 DH |
1384 | static inline bool cpu_has_vmx_ept_mt_wb(void) |
1385 | { | |
1386 | return vmx_capability.ept & VMX_EPTP_WB_BIT; | |
1387 | } | |
1388 | ||
855feb67 YZ |
1389 | static inline bool cpu_has_vmx_ept_5levels(void) |
1390 | { | |
1391 | return vmx_capability.ept & VMX_EPT_PAGE_WALK_5_BIT; | |
1392 | } | |
1393 | ||
83c3a331 XH |
1394 | static inline bool cpu_has_vmx_ept_ad_bits(void) |
1395 | { | |
1396 | return vmx_capability.ept & VMX_EPT_AD_BIT; | |
1397 | } | |
1398 | ||
31299944 | 1399 | static inline bool cpu_has_vmx_invept_context(void) |
d56f546d | 1400 | { |
31299944 | 1401 | return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT; |
d56f546d SY |
1402 | } |
1403 | ||
31299944 | 1404 | static inline bool cpu_has_vmx_invept_global(void) |
d56f546d | 1405 | { |
31299944 | 1406 | return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT; |
d56f546d SY |
1407 | } |
1408 | ||
518c8aee GJ |
1409 | static inline bool cpu_has_vmx_invvpid_single(void) |
1410 | { | |
1411 | return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT; | |
1412 | } | |
1413 | ||
b9d762fa GJ |
1414 | static inline bool cpu_has_vmx_invvpid_global(void) |
1415 | { | |
1416 | return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT; | |
1417 | } | |
1418 | ||
08d839c4 WL |
1419 | static inline bool cpu_has_vmx_invvpid(void) |
1420 | { | |
1421 | return vmx_capability.vpid & VMX_VPID_INVVPID_BIT; | |
1422 | } | |
1423 | ||
31299944 | 1424 | static inline bool cpu_has_vmx_ept(void) |
d56f546d | 1425 | { |
04547156 SY |
1426 | return vmcs_config.cpu_based_2nd_exec_ctrl & |
1427 | SECONDARY_EXEC_ENABLE_EPT; | |
d56f546d SY |
1428 | } |
1429 | ||
31299944 | 1430 | static inline bool cpu_has_vmx_unrestricted_guest(void) |
3a624e29 NK |
1431 | { |
1432 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1433 | SECONDARY_EXEC_UNRESTRICTED_GUEST; | |
1434 | } | |
1435 | ||
31299944 | 1436 | static inline bool cpu_has_vmx_ple(void) |
4b8d54f9 ZE |
1437 | { |
1438 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1439 | SECONDARY_EXEC_PAUSE_LOOP_EXITING; | |
1440 | } | |
1441 | ||
9ac7e3e8 JD |
1442 | static inline bool cpu_has_vmx_basic_inout(void) |
1443 | { | |
1444 | return (((u64)vmcs_config.basic_cap << 32) & VMX_BASIC_INOUT); | |
1445 | } | |
1446 | ||
35754c98 | 1447 | static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu) |
f78e0e2e | 1448 | { |
35754c98 | 1449 | return flexpriority_enabled && lapic_in_kernel(vcpu); |
f78e0e2e SY |
1450 | } |
1451 | ||
31299944 | 1452 | static inline bool cpu_has_vmx_vpid(void) |
2384d2b3 | 1453 | { |
04547156 SY |
1454 | return vmcs_config.cpu_based_2nd_exec_ctrl & |
1455 | SECONDARY_EXEC_ENABLE_VPID; | |
2384d2b3 SY |
1456 | } |
1457 | ||
31299944 | 1458 | static inline bool cpu_has_vmx_rdtscp(void) |
4e47c7a6 SY |
1459 | { |
1460 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1461 | SECONDARY_EXEC_RDTSCP; | |
1462 | } | |
1463 | ||
ad756a16 MJ |
1464 | static inline bool cpu_has_vmx_invpcid(void) |
1465 | { | |
1466 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1467 | SECONDARY_EXEC_ENABLE_INVPCID; | |
1468 | } | |
1469 | ||
8a1b4392 PB |
1470 | static inline bool cpu_has_virtual_nmis(void) |
1471 | { | |
1472 | return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS; | |
1473 | } | |
1474 | ||
f5f48ee1 SY |
1475 | static inline bool cpu_has_vmx_wbinvd_exit(void) |
1476 | { | |
1477 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1478 | SECONDARY_EXEC_WBINVD_EXITING; | |
1479 | } | |
1480 | ||
abc4fc58 AG |
1481 | static inline bool cpu_has_vmx_shadow_vmcs(void) |
1482 | { | |
1483 | u64 vmx_msr; | |
1484 | rdmsrl(MSR_IA32_VMX_MISC, vmx_msr); | |
1485 | /* check if the cpu supports writing r/o exit information fields */ | |
1486 | if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS)) | |
1487 | return false; | |
1488 | ||
1489 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1490 | SECONDARY_EXEC_SHADOW_VMCS; | |
1491 | } | |
1492 | ||
843e4330 KH |
1493 | static inline bool cpu_has_vmx_pml(void) |
1494 | { | |
1495 | return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML; | |
1496 | } | |
1497 | ||
64903d61 HZ |
1498 | static inline bool cpu_has_vmx_tsc_scaling(void) |
1499 | { | |
1500 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1501 | SECONDARY_EXEC_TSC_SCALING; | |
1502 | } | |
1503 | ||
2a499e49 BD |
1504 | static inline bool cpu_has_vmx_vmfunc(void) |
1505 | { | |
1506 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1507 | SECONDARY_EXEC_ENABLE_VMFUNC; | |
1508 | } | |
1509 | ||
04547156 SY |
1510 | static inline bool report_flexpriority(void) |
1511 | { | |
1512 | return flexpriority_enabled; | |
1513 | } | |
1514 | ||
c7c2c709 JM |
1515 | static inline unsigned nested_cpu_vmx_misc_cr3_count(struct kvm_vcpu *vcpu) |
1516 | { | |
1517 | return vmx_misc_cr3_count(to_vmx(vcpu)->nested.nested_vmx_misc_low); | |
1518 | } | |
1519 | ||
fe3ef05c NHE |
1520 | static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit) |
1521 | { | |
1522 | return vmcs12->cpu_based_vm_exec_control & bit; | |
1523 | } | |
1524 | ||
1525 | static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit) | |
1526 | { | |
1527 | return (vmcs12->cpu_based_vm_exec_control & | |
1528 | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) && | |
1529 | (vmcs12->secondary_vm_exec_control & bit); | |
1530 | } | |
1531 | ||
f4124500 JK |
1532 | static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12) |
1533 | { | |
1534 | return vmcs12->pin_based_vm_exec_control & | |
1535 | PIN_BASED_VMX_PREEMPTION_TIMER; | |
1536 | } | |
1537 | ||
155a97a3 NHE |
1538 | static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12) |
1539 | { | |
1540 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT); | |
1541 | } | |
1542 | ||
81dc01f7 WL |
1543 | static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12) |
1544 | { | |
3db13480 | 1545 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES); |
81dc01f7 WL |
1546 | } |
1547 | ||
c5f983f6 BD |
1548 | static inline bool nested_cpu_has_pml(struct vmcs12 *vmcs12) |
1549 | { | |
1550 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_PML); | |
1551 | } | |
1552 | ||
f2b93280 WV |
1553 | static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12) |
1554 | { | |
1555 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE); | |
1556 | } | |
1557 | ||
5c614b35 WL |
1558 | static inline bool nested_cpu_has_vpid(struct vmcs12 *vmcs12) |
1559 | { | |
1560 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VPID); | |
1561 | } | |
1562 | ||
82f0dd4b WV |
1563 | static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12) |
1564 | { | |
1565 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT); | |
1566 | } | |
1567 | ||
608406e2 WV |
1568 | static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12) |
1569 | { | |
1570 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); | |
1571 | } | |
1572 | ||
705699a1 WV |
1573 | static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12) |
1574 | { | |
1575 | return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR; | |
1576 | } | |
1577 | ||
27c42a1b BD |
1578 | static inline bool nested_cpu_has_vmfunc(struct vmcs12 *vmcs12) |
1579 | { | |
1580 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VMFUNC); | |
1581 | } | |
1582 | ||
41ab9372 BD |
1583 | static inline bool nested_cpu_has_eptp_switching(struct vmcs12 *vmcs12) |
1584 | { | |
1585 | return nested_cpu_has_vmfunc(vmcs12) && | |
1586 | (vmcs12->vm_function_control & | |
1587 | VMX_VMFUNC_EPTP_SWITCHING); | |
1588 | } | |
1589 | ||
ef85b673 | 1590 | static inline bool is_nmi(u32 intr_info) |
644d711a NHE |
1591 | { |
1592 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK)) | |
ef85b673 | 1593 | == (INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK); |
644d711a NHE |
1594 | } |
1595 | ||
533558bc JK |
1596 | static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason, |
1597 | u32 exit_intr_info, | |
1598 | unsigned long exit_qualification); | |
7c177938 NHE |
1599 | static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu, |
1600 | struct vmcs12 *vmcs12, | |
1601 | u32 reason, unsigned long qualification); | |
1602 | ||
8b9cf98c | 1603 | static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr) |
7725f0ba AK |
1604 | { |
1605 | int i; | |
1606 | ||
a2fa3e9f | 1607 | for (i = 0; i < vmx->nmsrs; ++i) |
26bb0981 | 1608 | if (vmx_msr_index[vmx->guest_msrs[i].index] == msr) |
a75beee6 ED |
1609 | return i; |
1610 | return -1; | |
1611 | } | |
1612 | ||
b9d2fecb | 1613 | static inline void __invvpid(unsigned long ext, u16 vpid, gva_t gva) |
2384d2b3 SY |
1614 | { |
1615 | struct { | |
1616 | u64 vpid : 16; | |
1617 | u64 rsvd : 48; | |
1618 | u64 gva; | |
1619 | } operand = { vpid, 0, gva }; | |
1620 | ||
4ecac3fd | 1621 | asm volatile (__ex(ASM_VMX_INVVPID) |
2384d2b3 SY |
1622 | /* CF==1 or ZF==1 --> rc = -1 */ |
1623 | "; ja 1f ; ud2 ; 1:" | |
1624 | : : "a"(&operand), "c"(ext) : "cc", "memory"); | |
1625 | } | |
1626 | ||
b9d2fecb | 1627 | static inline void __invept(unsigned long ext, u64 eptp, gpa_t gpa) |
1439442c SY |
1628 | { |
1629 | struct { | |
1630 | u64 eptp, gpa; | |
1631 | } operand = {eptp, gpa}; | |
1632 | ||
4ecac3fd | 1633 | asm volatile (__ex(ASM_VMX_INVEPT) |
1439442c SY |
1634 | /* CF==1 or ZF==1 --> rc = -1 */ |
1635 | "; ja 1f ; ud2 ; 1:\n" | |
1636 | : : "a" (&operand), "c" (ext) : "cc", "memory"); | |
1637 | } | |
1638 | ||
26bb0981 | 1639 | static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr) |
a75beee6 ED |
1640 | { |
1641 | int i; | |
1642 | ||
8b9cf98c | 1643 | i = __find_msr_index(vmx, msr); |
a75beee6 | 1644 | if (i >= 0) |
a2fa3e9f | 1645 | return &vmx->guest_msrs[i]; |
8b6d44c7 | 1646 | return NULL; |
7725f0ba AK |
1647 | } |
1648 | ||
6aa8b732 AK |
1649 | static void vmcs_clear(struct vmcs *vmcs) |
1650 | { | |
1651 | u64 phys_addr = __pa(vmcs); | |
1652 | u8 error; | |
1653 | ||
4ecac3fd | 1654 | asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0" |
16d8f72f | 1655 | : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr) |
6aa8b732 AK |
1656 | : "cc", "memory"); |
1657 | if (error) | |
1658 | printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n", | |
1659 | vmcs, phys_addr); | |
1660 | } | |
1661 | ||
d462b819 NHE |
1662 | static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs) |
1663 | { | |
1664 | vmcs_clear(loaded_vmcs->vmcs); | |
355f4fb1 JM |
1665 | if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched) |
1666 | vmcs_clear(loaded_vmcs->shadow_vmcs); | |
d462b819 NHE |
1667 | loaded_vmcs->cpu = -1; |
1668 | loaded_vmcs->launched = 0; | |
1669 | } | |
1670 | ||
7725b894 DX |
1671 | static void vmcs_load(struct vmcs *vmcs) |
1672 | { | |
1673 | u64 phys_addr = __pa(vmcs); | |
1674 | u8 error; | |
1675 | ||
1676 | asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0" | |
16d8f72f | 1677 | : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr) |
7725b894 DX |
1678 | : "cc", "memory"); |
1679 | if (error) | |
2844d849 | 1680 | printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n", |
7725b894 DX |
1681 | vmcs, phys_addr); |
1682 | } | |
1683 | ||
2965faa5 | 1684 | #ifdef CONFIG_KEXEC_CORE |
8f536b76 ZY |
1685 | /* |
1686 | * This bitmap is used to indicate whether the vmclear | |
1687 | * operation is enabled on all cpus. All disabled by | |
1688 | * default. | |
1689 | */ | |
1690 | static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE; | |
1691 | ||
1692 | static inline void crash_enable_local_vmclear(int cpu) | |
1693 | { | |
1694 | cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap); | |
1695 | } | |
1696 | ||
1697 | static inline void crash_disable_local_vmclear(int cpu) | |
1698 | { | |
1699 | cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap); | |
1700 | } | |
1701 | ||
1702 | static inline int crash_local_vmclear_enabled(int cpu) | |
1703 | { | |
1704 | return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap); | |
1705 | } | |
1706 | ||
1707 | static void crash_vmclear_local_loaded_vmcss(void) | |
1708 | { | |
1709 | int cpu = raw_smp_processor_id(); | |
1710 | struct loaded_vmcs *v; | |
1711 | ||
1712 | if (!crash_local_vmclear_enabled(cpu)) | |
1713 | return; | |
1714 | ||
1715 | list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu), | |
1716 | loaded_vmcss_on_cpu_link) | |
1717 | vmcs_clear(v->vmcs); | |
1718 | } | |
1719 | #else | |
1720 | static inline void crash_enable_local_vmclear(int cpu) { } | |
1721 | static inline void crash_disable_local_vmclear(int cpu) { } | |
2965faa5 | 1722 | #endif /* CONFIG_KEXEC_CORE */ |
8f536b76 | 1723 | |
d462b819 | 1724 | static void __loaded_vmcs_clear(void *arg) |
6aa8b732 | 1725 | { |
d462b819 | 1726 | struct loaded_vmcs *loaded_vmcs = arg; |
d3b2c338 | 1727 | int cpu = raw_smp_processor_id(); |
6aa8b732 | 1728 | |
d462b819 NHE |
1729 | if (loaded_vmcs->cpu != cpu) |
1730 | return; /* vcpu migration can race with cpu offline */ | |
1731 | if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs) | |
6aa8b732 | 1732 | per_cpu(current_vmcs, cpu) = NULL; |
8f536b76 | 1733 | crash_disable_local_vmclear(cpu); |
d462b819 | 1734 | list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link); |
5a560f8b XG |
1735 | |
1736 | /* | |
1737 | * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link | |
1738 | * is before setting loaded_vmcs->vcpu to -1 which is done in | |
1739 | * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist | |
1740 | * then adds the vmcs into percpu list before it is deleted. | |
1741 | */ | |
1742 | smp_wmb(); | |
1743 | ||
d462b819 | 1744 | loaded_vmcs_init(loaded_vmcs); |
8f536b76 | 1745 | crash_enable_local_vmclear(cpu); |
6aa8b732 AK |
1746 | } |
1747 | ||
d462b819 | 1748 | static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs) |
8d0be2b3 | 1749 | { |
e6c7d321 XG |
1750 | int cpu = loaded_vmcs->cpu; |
1751 | ||
1752 | if (cpu != -1) | |
1753 | smp_call_function_single(cpu, | |
1754 | __loaded_vmcs_clear, loaded_vmcs, 1); | |
8d0be2b3 AK |
1755 | } |
1756 | ||
dd5f5341 | 1757 | static inline void vpid_sync_vcpu_single(int vpid) |
2384d2b3 | 1758 | { |
dd5f5341 | 1759 | if (vpid == 0) |
2384d2b3 SY |
1760 | return; |
1761 | ||
518c8aee | 1762 | if (cpu_has_vmx_invvpid_single()) |
dd5f5341 | 1763 | __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vpid, 0); |
2384d2b3 SY |
1764 | } |
1765 | ||
b9d762fa GJ |
1766 | static inline void vpid_sync_vcpu_global(void) |
1767 | { | |
1768 | if (cpu_has_vmx_invvpid_global()) | |
1769 | __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0); | |
1770 | } | |
1771 | ||
dd5f5341 | 1772 | static inline void vpid_sync_context(int vpid) |
b9d762fa GJ |
1773 | { |
1774 | if (cpu_has_vmx_invvpid_single()) | |
dd5f5341 | 1775 | vpid_sync_vcpu_single(vpid); |
b9d762fa GJ |
1776 | else |
1777 | vpid_sync_vcpu_global(); | |
1778 | } | |
1779 | ||
1439442c SY |
1780 | static inline void ept_sync_global(void) |
1781 | { | |
f5f51586 | 1782 | __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0); |
1439442c SY |
1783 | } |
1784 | ||
1785 | static inline void ept_sync_context(u64 eptp) | |
1786 | { | |
0e1252dc DH |
1787 | if (cpu_has_vmx_invept_context()) |
1788 | __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0); | |
1789 | else | |
1790 | ept_sync_global(); | |
1439442c SY |
1791 | } |
1792 | ||
8a86aea9 PB |
1793 | static __always_inline void vmcs_check16(unsigned long field) |
1794 | { | |
1795 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000, | |
1796 | "16-bit accessor invalid for 64-bit field"); | |
1797 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001, | |
1798 | "16-bit accessor invalid for 64-bit high field"); | |
1799 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000, | |
1800 | "16-bit accessor invalid for 32-bit high field"); | |
1801 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000, | |
1802 | "16-bit accessor invalid for natural width field"); | |
1803 | } | |
1804 | ||
1805 | static __always_inline void vmcs_check32(unsigned long field) | |
1806 | { | |
1807 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0, | |
1808 | "32-bit accessor invalid for 16-bit field"); | |
1809 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000, | |
1810 | "32-bit accessor invalid for natural width field"); | |
1811 | } | |
1812 | ||
1813 | static __always_inline void vmcs_check64(unsigned long field) | |
1814 | { | |
1815 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0, | |
1816 | "64-bit accessor invalid for 16-bit field"); | |
1817 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001, | |
1818 | "64-bit accessor invalid for 64-bit high field"); | |
1819 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000, | |
1820 | "64-bit accessor invalid for 32-bit field"); | |
1821 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000, | |
1822 | "64-bit accessor invalid for natural width field"); | |
1823 | } | |
1824 | ||
1825 | static __always_inline void vmcs_checkl(unsigned long field) | |
1826 | { | |
1827 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0, | |
1828 | "Natural width accessor invalid for 16-bit field"); | |
1829 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000, | |
1830 | "Natural width accessor invalid for 64-bit field"); | |
1831 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001, | |
1832 | "Natural width accessor invalid for 64-bit high field"); | |
1833 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000, | |
1834 | "Natural width accessor invalid for 32-bit field"); | |
1835 | } | |
1836 | ||
1837 | static __always_inline unsigned long __vmcs_readl(unsigned long field) | |
6aa8b732 | 1838 | { |
5e520e62 | 1839 | unsigned long value; |
6aa8b732 | 1840 | |
5e520e62 AK |
1841 | asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0") |
1842 | : "=a"(value) : "d"(field) : "cc"); | |
6aa8b732 AK |
1843 | return value; |
1844 | } | |
1845 | ||
96304217 | 1846 | static __always_inline u16 vmcs_read16(unsigned long field) |
6aa8b732 | 1847 | { |
8a86aea9 PB |
1848 | vmcs_check16(field); |
1849 | return __vmcs_readl(field); | |
6aa8b732 AK |
1850 | } |
1851 | ||
96304217 | 1852 | static __always_inline u32 vmcs_read32(unsigned long field) |
6aa8b732 | 1853 | { |
8a86aea9 PB |
1854 | vmcs_check32(field); |
1855 | return __vmcs_readl(field); | |
6aa8b732 AK |
1856 | } |
1857 | ||
96304217 | 1858 | static __always_inline u64 vmcs_read64(unsigned long field) |
6aa8b732 | 1859 | { |
8a86aea9 | 1860 | vmcs_check64(field); |
05b3e0c2 | 1861 | #ifdef CONFIG_X86_64 |
8a86aea9 | 1862 | return __vmcs_readl(field); |
6aa8b732 | 1863 | #else |
8a86aea9 | 1864 | return __vmcs_readl(field) | ((u64)__vmcs_readl(field+1) << 32); |
6aa8b732 AK |
1865 | #endif |
1866 | } | |
1867 | ||
8a86aea9 PB |
1868 | static __always_inline unsigned long vmcs_readl(unsigned long field) |
1869 | { | |
1870 | vmcs_checkl(field); | |
1871 | return __vmcs_readl(field); | |
1872 | } | |
1873 | ||
e52de1b8 AK |
1874 | static noinline void vmwrite_error(unsigned long field, unsigned long value) |
1875 | { | |
1876 | printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n", | |
1877 | field, value, vmcs_read32(VM_INSTRUCTION_ERROR)); | |
1878 | dump_stack(); | |
1879 | } | |
1880 | ||
8a86aea9 | 1881 | static __always_inline void __vmcs_writel(unsigned long field, unsigned long value) |
6aa8b732 AK |
1882 | { |
1883 | u8 error; | |
1884 | ||
4ecac3fd | 1885 | asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0" |
d77c26fc | 1886 | : "=q"(error) : "a"(value), "d"(field) : "cc"); |
e52de1b8 AK |
1887 | if (unlikely(error)) |
1888 | vmwrite_error(field, value); | |
6aa8b732 AK |
1889 | } |
1890 | ||
8a86aea9 | 1891 | static __always_inline void vmcs_write16(unsigned long field, u16 value) |
6aa8b732 | 1892 | { |
8a86aea9 PB |
1893 | vmcs_check16(field); |
1894 | __vmcs_writel(field, value); | |
6aa8b732 AK |
1895 | } |
1896 | ||
8a86aea9 | 1897 | static __always_inline void vmcs_write32(unsigned long field, u32 value) |
6aa8b732 | 1898 | { |
8a86aea9 PB |
1899 | vmcs_check32(field); |
1900 | __vmcs_writel(field, value); | |
6aa8b732 AK |
1901 | } |
1902 | ||
8a86aea9 | 1903 | static __always_inline void vmcs_write64(unsigned long field, u64 value) |
6aa8b732 | 1904 | { |
8a86aea9 PB |
1905 | vmcs_check64(field); |
1906 | __vmcs_writel(field, value); | |
7682f2d0 | 1907 | #ifndef CONFIG_X86_64 |
6aa8b732 | 1908 | asm volatile (""); |
8a86aea9 | 1909 | __vmcs_writel(field+1, value >> 32); |
6aa8b732 AK |
1910 | #endif |
1911 | } | |
1912 | ||
8a86aea9 | 1913 | static __always_inline void vmcs_writel(unsigned long field, unsigned long value) |
2ab455cc | 1914 | { |
8a86aea9 PB |
1915 | vmcs_checkl(field); |
1916 | __vmcs_writel(field, value); | |
2ab455cc AL |
1917 | } |
1918 | ||
8a86aea9 | 1919 | static __always_inline void vmcs_clear_bits(unsigned long field, u32 mask) |
2ab455cc | 1920 | { |
8a86aea9 PB |
1921 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000, |
1922 | "vmcs_clear_bits does not support 64-bit fields"); | |
1923 | __vmcs_writel(field, __vmcs_readl(field) & ~mask); | |
2ab455cc AL |
1924 | } |
1925 | ||
8a86aea9 | 1926 | static __always_inline void vmcs_set_bits(unsigned long field, u32 mask) |
2ab455cc | 1927 | { |
8a86aea9 PB |
1928 | BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000, |
1929 | "vmcs_set_bits does not support 64-bit fields"); | |
1930 | __vmcs_writel(field, __vmcs_readl(field) | mask); | |
2ab455cc AL |
1931 | } |
1932 | ||
8391ce44 PB |
1933 | static inline void vm_entry_controls_reset_shadow(struct vcpu_vmx *vmx) |
1934 | { | |
1935 | vmx->vm_entry_controls_shadow = vmcs_read32(VM_ENTRY_CONTROLS); | |
1936 | } | |
1937 | ||
2961e876 GN |
1938 | static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val) |
1939 | { | |
1940 | vmcs_write32(VM_ENTRY_CONTROLS, val); | |
1941 | vmx->vm_entry_controls_shadow = val; | |
1942 | } | |
1943 | ||
1944 | static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val) | |
1945 | { | |
1946 | if (vmx->vm_entry_controls_shadow != val) | |
1947 | vm_entry_controls_init(vmx, val); | |
1948 | } | |
1949 | ||
1950 | static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx) | |
1951 | { | |
1952 | return vmx->vm_entry_controls_shadow; | |
1953 | } | |
1954 | ||
1955 | ||
1956 | static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val) | |
1957 | { | |
1958 | vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val); | |
1959 | } | |
1960 | ||
1961 | static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val) | |
1962 | { | |
1963 | vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val); | |
1964 | } | |
1965 | ||
8391ce44 PB |
1966 | static inline void vm_exit_controls_reset_shadow(struct vcpu_vmx *vmx) |
1967 | { | |
1968 | vmx->vm_exit_controls_shadow = vmcs_read32(VM_EXIT_CONTROLS); | |
1969 | } | |
1970 | ||
2961e876 GN |
1971 | static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val) |
1972 | { | |
1973 | vmcs_write32(VM_EXIT_CONTROLS, val); | |
1974 | vmx->vm_exit_controls_shadow = val; | |
1975 | } | |
1976 | ||
1977 | static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val) | |
1978 | { | |
1979 | if (vmx->vm_exit_controls_shadow != val) | |
1980 | vm_exit_controls_init(vmx, val); | |
1981 | } | |
1982 | ||
1983 | static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx) | |
1984 | { | |
1985 | return vmx->vm_exit_controls_shadow; | |
1986 | } | |
1987 | ||
1988 | ||
1989 | static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val) | |
1990 | { | |
1991 | vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val); | |
1992 | } | |
1993 | ||
1994 | static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val) | |
1995 | { | |
1996 | vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val); | |
1997 | } | |
1998 | ||
2fb92db1 AK |
1999 | static void vmx_segment_cache_clear(struct vcpu_vmx *vmx) |
2000 | { | |
2001 | vmx->segment_cache.bitmask = 0; | |
2002 | } | |
2003 | ||
2004 | static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg, | |
2005 | unsigned field) | |
2006 | { | |
2007 | bool ret; | |
2008 | u32 mask = 1 << (seg * SEG_FIELD_NR + field); | |
2009 | ||
2010 | if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) { | |
2011 | vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS); | |
2012 | vmx->segment_cache.bitmask = 0; | |
2013 | } | |
2014 | ret = vmx->segment_cache.bitmask & mask; | |
2015 | vmx->segment_cache.bitmask |= mask; | |
2016 | return ret; | |
2017 | } | |
2018 | ||
2019 | static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg) | |
2020 | { | |
2021 | u16 *p = &vmx->segment_cache.seg[seg].selector; | |
2022 | ||
2023 | if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL)) | |
2024 | *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector); | |
2025 | return *p; | |
2026 | } | |
2027 | ||
2028 | static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg) | |
2029 | { | |
2030 | ulong *p = &vmx->segment_cache.seg[seg].base; | |
2031 | ||
2032 | if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE)) | |
2033 | *p = vmcs_readl(kvm_vmx_segment_fields[seg].base); | |
2034 | return *p; | |
2035 | } | |
2036 | ||
2037 | static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg) | |
2038 | { | |
2039 | u32 *p = &vmx->segment_cache.seg[seg].limit; | |
2040 | ||
2041 | if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT)) | |
2042 | *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit); | |
2043 | return *p; | |
2044 | } | |
2045 | ||
2046 | static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg) | |
2047 | { | |
2048 | u32 *p = &vmx->segment_cache.seg[seg].ar; | |
2049 | ||
2050 | if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR)) | |
2051 | *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes); | |
2052 | return *p; | |
2053 | } | |
2054 | ||
abd3f2d6 AK |
2055 | static void update_exception_bitmap(struct kvm_vcpu *vcpu) |
2056 | { | |
2057 | u32 eb; | |
2058 | ||
bd89525a | 2059 | eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) | |
bd7e5b08 | 2060 | (1u << DB_VECTOR) | (1u << AC_VECTOR); |
fd7373cc JK |
2061 | if ((vcpu->guest_debug & |
2062 | (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) == | |
2063 | (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) | |
2064 | eb |= 1u << BP_VECTOR; | |
7ffd92c5 | 2065 | if (to_vmx(vcpu)->rmode.vm86_active) |
abd3f2d6 | 2066 | eb = ~0; |
089d034e | 2067 | if (enable_ept) |
1439442c | 2068 | eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */ |
36cf24e0 NHE |
2069 | |
2070 | /* When we are running a nested L2 guest and L1 specified for it a | |
2071 | * certain exception bitmap, we must trap the same exceptions and pass | |
2072 | * them to L1. When running L2, we will only handle the exceptions | |
2073 | * specified above if L1 did not want them. | |
2074 | */ | |
2075 | if (is_guest_mode(vcpu)) | |
2076 | eb |= get_vmcs12(vcpu)->exception_bitmap; | |
2077 | ||
abd3f2d6 AK |
2078 | vmcs_write32(EXCEPTION_BITMAP, eb); |
2079 | } | |
2080 | ||
74469996 KA |
2081 | /* |
2082 | * Check if MSR is intercepted for currently loaded MSR bitmap. | |
2083 | */ | |
2084 | static bool msr_write_intercepted(struct kvm_vcpu *vcpu, u32 msr) | |
2085 | { | |
2086 | unsigned long *msr_bitmap; | |
2087 | int f = sizeof(unsigned long); | |
2088 | ||
2089 | if (!cpu_has_vmx_msr_bitmap()) | |
2090 | return true; | |
2091 | ||
2092 | msr_bitmap = to_vmx(vcpu)->loaded_vmcs->msr_bitmap; | |
2093 | ||
2094 | if (msr <= 0x1fff) { | |
2095 | return !!test_bit(msr, msr_bitmap + 0x800 / f); | |
2096 | } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) { | |
2097 | msr &= 0x1fff; | |
2098 | return !!test_bit(msr, msr_bitmap + 0xc00 / f); | |
2099 | } | |
2100 | ||
2101 | return true; | |
2102 | } | |
2103 | ||
33241bfe AR |
2104 | /* |
2105 | * Check if MSR is intercepted for L01 MSR bitmap. | |
2106 | */ | |
2107 | static bool msr_write_intercepted_l01(struct kvm_vcpu *vcpu, u32 msr) | |
2108 | { | |
2109 | unsigned long *msr_bitmap; | |
2110 | int f = sizeof(unsigned long); | |
2111 | ||
2112 | if (!cpu_has_vmx_msr_bitmap()) | |
2113 | return true; | |
2114 | ||
2115 | msr_bitmap = to_vmx(vcpu)->vmcs01.msr_bitmap; | |
2116 | ||
2117 | if (msr <= 0x1fff) { | |
2118 | return !!test_bit(msr, msr_bitmap + 0x800 / f); | |
2119 | } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) { | |
2120 | msr &= 0x1fff; | |
2121 | return !!test_bit(msr, msr_bitmap + 0xc00 / f); | |
2122 | } | |
2123 | ||
2124 | return true; | |
2125 | } | |
2126 | ||
2961e876 GN |
2127 | static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx, |
2128 | unsigned long entry, unsigned long exit) | |
8bf00a52 | 2129 | { |
2961e876 GN |
2130 | vm_entry_controls_clearbit(vmx, entry); |
2131 | vm_exit_controls_clearbit(vmx, exit); | |
8bf00a52 GN |
2132 | } |
2133 | ||
d8066b74 KRW |
2134 | static int find_msr(struct vmx_msrs *m, unsigned int msr) |
2135 | { | |
2136 | unsigned int i; | |
2137 | ||
2138 | for (i = 0; i < m->nr; ++i) { | |
2139 | if (m->val[i].index == msr) | |
2140 | return i; | |
2141 | } | |
2142 | return -ENOENT; | |
2143 | } | |
2144 | ||
61d2ef2c AK |
2145 | static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr) |
2146 | { | |
d8066b74 | 2147 | int i; |
61d2ef2c AK |
2148 | struct msr_autoload *m = &vmx->msr_autoload; |
2149 | ||
8bf00a52 GN |
2150 | switch (msr) { |
2151 | case MSR_EFER: | |
2152 | if (cpu_has_load_ia32_efer) { | |
2961e876 GN |
2153 | clear_atomic_switch_msr_special(vmx, |
2154 | VM_ENTRY_LOAD_IA32_EFER, | |
8bf00a52 GN |
2155 | VM_EXIT_LOAD_IA32_EFER); |
2156 | return; | |
2157 | } | |
2158 | break; | |
2159 | case MSR_CORE_PERF_GLOBAL_CTRL: | |
2160 | if (cpu_has_load_perf_global_ctrl) { | |
2961e876 | 2161 | clear_atomic_switch_msr_special(vmx, |
8bf00a52 GN |
2162 | VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL, |
2163 | VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL); | |
2164 | return; | |
2165 | } | |
2166 | break; | |
110312c8 | 2167 | } |
d8066b74 KRW |
2168 | i = find_msr(&m->guest, msr); |
2169 | if (i < 0) | |
0666648b | 2170 | goto skip_guest; |
6e3dedb6 | 2171 | --m->guest.nr; |
6e3dedb6 | 2172 | m->guest.val[i] = m->guest.val[m->guest.nr]; |
6e3dedb6 | 2173 | vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr); |
0666648b KRW |
2174 | |
2175 | skip_guest: | |
2176 | i = find_msr(&m->host, msr); | |
2177 | if (i < 0) | |
2178 | return; | |
2179 | ||
2180 | --m->host.nr; | |
2181 | m->host.val[i] = m->host.val[m->host.nr]; | |
6e3dedb6 | 2182 | vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr); |
61d2ef2c AK |
2183 | } |
2184 | ||
2961e876 GN |
2185 | static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx, |
2186 | unsigned long entry, unsigned long exit, | |
2187 | unsigned long guest_val_vmcs, unsigned long host_val_vmcs, | |
2188 | u64 guest_val, u64 host_val) | |
8bf00a52 GN |
2189 | { |
2190 | vmcs_write64(guest_val_vmcs, guest_val); | |
2191 | vmcs_write64(host_val_vmcs, host_val); | |
2961e876 GN |
2192 | vm_entry_controls_setbit(vmx, entry); |
2193 | vm_exit_controls_setbit(vmx, exit); | |
8bf00a52 GN |
2194 | } |
2195 | ||
61d2ef2c | 2196 | static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr, |
129ce7ac | 2197 | u64 guest_val, u64 host_val, bool entry_only) |
61d2ef2c | 2198 | { |
129ce7ac | 2199 | int i, j = 0; |
61d2ef2c AK |
2200 | struct msr_autoload *m = &vmx->msr_autoload; |
2201 | ||
8bf00a52 GN |
2202 | switch (msr) { |
2203 | case MSR_EFER: | |
2204 | if (cpu_has_load_ia32_efer) { | |
2961e876 GN |
2205 | add_atomic_switch_msr_special(vmx, |
2206 | VM_ENTRY_LOAD_IA32_EFER, | |
8bf00a52 GN |
2207 | VM_EXIT_LOAD_IA32_EFER, |
2208 | GUEST_IA32_EFER, | |
2209 | HOST_IA32_EFER, | |
2210 | guest_val, host_val); | |
2211 | return; | |
2212 | } | |
2213 | break; | |
2214 | case MSR_CORE_PERF_GLOBAL_CTRL: | |
2215 | if (cpu_has_load_perf_global_ctrl) { | |
2961e876 | 2216 | add_atomic_switch_msr_special(vmx, |
8bf00a52 GN |
2217 | VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL, |
2218 | VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL, | |
2219 | GUEST_IA32_PERF_GLOBAL_CTRL, | |
2220 | HOST_IA32_PERF_GLOBAL_CTRL, | |
2221 | guest_val, host_val); | |
2222 | return; | |
2223 | } | |
2224 | break; | |
7099e2e1 RK |
2225 | case MSR_IA32_PEBS_ENABLE: |
2226 | /* PEBS needs a quiescent period after being disabled (to write | |
2227 | * a record). Disabling PEBS through VMX MSR swapping doesn't | |
2228 | * provide that period, so a CPU could write host's record into | |
2229 | * guest's memory. | |
2230 | */ | |
2231 | wrmsrl(MSR_IA32_PEBS_ENABLE, 0); | |
110312c8 AK |
2232 | } |
2233 | ||
d8066b74 | 2234 | i = find_msr(&m->guest, msr); |
129ce7ac KRW |
2235 | if (!entry_only) |
2236 | j = find_msr(&m->host, msr); | |
2237 | ||
2034b9ef XL |
2238 | if ((i < 0 && m->guest.nr == NR_AUTOLOAD_MSRS) || |
2239 | (j < 0 && m->host.nr == NR_AUTOLOAD_MSRS)) { | |
60266204 | 2240 | printk_once(KERN_WARNING "Not enough msr switch entries. " |
e7fc6f93 GN |
2241 | "Can't add msr %x\n", msr); |
2242 | return; | |
0666648b KRW |
2243 | } |
2244 | if (i < 0) { | |
d8066b74 | 2245 | i = m->guest.nr++; |
6e3dedb6 | 2246 | vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr); |
0666648b | 2247 | } |
129ce7ac KRW |
2248 | m->guest.val[i].index = msr; |
2249 | m->guest.val[i].value = guest_val; | |
2250 | ||
2251 | if (entry_only) | |
2252 | return; | |
2253 | ||
0666648b KRW |
2254 | if (j < 0) { |
2255 | j = m->host.nr++; | |
6e3dedb6 | 2256 | vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr); |
61d2ef2c | 2257 | } |
0666648b KRW |
2258 | m->host.val[j].index = msr; |
2259 | m->host.val[j].value = host_val; | |
61d2ef2c AK |
2260 | } |
2261 | ||
92c0d900 | 2262 | static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset) |
2cc51560 | 2263 | { |
844a5fe2 PB |
2264 | u64 guest_efer = vmx->vcpu.arch.efer; |
2265 | u64 ignore_bits = 0; | |
2266 | ||
6bea1213 PB |
2267 | /* Shadow paging assumes NX to be available. */ |
2268 | if (!enable_ept) | |
2269 | guest_efer |= EFER_NX; | |
3a34a881 | 2270 | |
51c6cf66 | 2271 | /* |
844a5fe2 | 2272 | * LMA and LME handled by hardware; SCE meaningless outside long mode. |
51c6cf66 | 2273 | */ |
844a5fe2 | 2274 | ignore_bits |= EFER_SCE; |
51c6cf66 AK |
2275 | #ifdef CONFIG_X86_64 |
2276 | ignore_bits |= EFER_LMA | EFER_LME; | |
2277 | /* SCE is meaningful only in long mode on Intel */ | |
2278 | if (guest_efer & EFER_LMA) | |
2279 | ignore_bits &= ~(u64)EFER_SCE; | |
2280 | #endif | |
84ad33ef AK |
2281 | |
2282 | clear_atomic_switch_msr(vmx, MSR_EFER); | |
f6577a5f AL |
2283 | |
2284 | /* | |
2285 | * On EPT, we can't emulate NX, so we must switch EFER atomically. | |
2286 | * On CPUs that support "load IA32_EFER", always switch EFER | |
2287 | * atomically, since it's faster than switching it manually. | |
2288 | */ | |
2289 | if (cpu_has_load_ia32_efer || | |
2290 | (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) { | |
84ad33ef AK |
2291 | if (!(guest_efer & EFER_LMA)) |
2292 | guest_efer &= ~EFER_LME; | |
54b98bff AL |
2293 | if (guest_efer != host_efer) |
2294 | add_atomic_switch_msr(vmx, MSR_EFER, | |
129ce7ac | 2295 | guest_efer, host_efer, false); |
84ad33ef | 2296 | return false; |
844a5fe2 PB |
2297 | } else { |
2298 | guest_efer &= ~ignore_bits; | |
2299 | guest_efer |= host_efer & ignore_bits; | |
2300 | ||
2301 | vmx->guest_msrs[efer_offset].data = guest_efer; | |
2302 | vmx->guest_msrs[efer_offset].mask = ~ignore_bits; | |
84ad33ef | 2303 | |
844a5fe2 PB |
2304 | return true; |
2305 | } | |
51c6cf66 AK |
2306 | } |
2307 | ||
e28baead AL |
2308 | #ifdef CONFIG_X86_32 |
2309 | /* | |
2310 | * On 32-bit kernels, VM exits still load the FS and GS bases from the | |
2311 | * VMCS rather than the segment table. KVM uses this helper to figure | |
2312 | * out the current bases to poke them into the VMCS before entry. | |
2313 | */ | |
2d49ec72 GN |
2314 | static unsigned long segment_base(u16 selector) |
2315 | { | |
8c2e41f7 | 2316 | struct desc_struct *table; |
2d49ec72 GN |
2317 | unsigned long v; |
2318 | ||
8c2e41f7 | 2319 | if (!(selector & ~SEGMENT_RPL_MASK)) |
2d49ec72 GN |
2320 | return 0; |
2321 | ||
45fc8757 | 2322 | table = get_current_gdt_ro(); |
2d49ec72 | 2323 | |
8c2e41f7 | 2324 | if ((selector & SEGMENT_TI_MASK) == SEGMENT_LDT) { |
2d49ec72 GN |
2325 | u16 ldt_selector = kvm_read_ldt(); |
2326 | ||
8c2e41f7 | 2327 | if (!(ldt_selector & ~SEGMENT_RPL_MASK)) |
2d49ec72 GN |
2328 | return 0; |
2329 | ||
8c2e41f7 | 2330 | table = (struct desc_struct *)segment_base(ldt_selector); |
2d49ec72 | 2331 | } |
8c2e41f7 | 2332 | v = get_desc_base(&table[selector >> 3]); |
2d49ec72 GN |
2333 | return v; |
2334 | } | |
e28baead | 2335 | #endif |
2d49ec72 | 2336 | |
04d2cc77 | 2337 | static void vmx_save_host_state(struct kvm_vcpu *vcpu) |
33ed6329 | 2338 | { |
04d2cc77 | 2339 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
26bb0981 | 2340 | int i; |
04d2cc77 | 2341 | |
8a12167a | 2342 | if (vmx->loaded_cpu_state) |
33ed6329 AK |
2343 | return; |
2344 | ||
8a12167a SC |
2345 | vmx->loaded_cpu_state = vmx->loaded_vmcs; |
2346 | ||
33ed6329 AK |
2347 | /* |
2348 | * Set host fs and gs selectors. Unfortunately, 22.2.3 does not | |
2349 | * allow segment selectors with cpl > 0 or ti == 1. | |
2350 | */ | |
d6e88aec | 2351 | vmx->host_state.ldt_sel = kvm_read_ldt(); |
152d3f2f | 2352 | vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel; |
9581d442 | 2353 | savesegment(fs, vmx->host_state.fs_sel); |
152d3f2f | 2354 | if (!(vmx->host_state.fs_sel & 7)) { |
a2fa3e9f | 2355 | vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel); |
152d3f2f LV |
2356 | vmx->host_state.fs_reload_needed = 0; |
2357 | } else { | |
33ed6329 | 2358 | vmcs_write16(HOST_FS_SELECTOR, 0); |
152d3f2f | 2359 | vmx->host_state.fs_reload_needed = 1; |
33ed6329 | 2360 | } |
9581d442 | 2361 | savesegment(gs, vmx->host_state.gs_sel); |
a2fa3e9f GH |
2362 | if (!(vmx->host_state.gs_sel & 7)) |
2363 | vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel); | |
33ed6329 AK |
2364 | else { |
2365 | vmcs_write16(HOST_GS_SELECTOR, 0); | |
152d3f2f | 2366 | vmx->host_state.gs_ldt_reload_needed = 1; |
33ed6329 AK |
2367 | } |
2368 | ||
b2da15ac AK |
2369 | #ifdef CONFIG_X86_64 |
2370 | savesegment(ds, vmx->host_state.ds_sel); | |
2371 | savesegment(es, vmx->host_state.es_sel); | |
2372 | #endif | |
2373 | ||
33ed6329 AK |
2374 | #ifdef CONFIG_X86_64 |
2375 | vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE)); | |
2376 | vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE)); | |
2377 | #else | |
a2fa3e9f GH |
2378 | vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel)); |
2379 | vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel)); | |
33ed6329 | 2380 | #endif |
707c0874 AK |
2381 | |
2382 | #ifdef CONFIG_X86_64 | |
c8770e7b AK |
2383 | rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base); |
2384 | if (is_long_mode(&vmx->vcpu)) | |
44ea2b17 | 2385 | wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base); |
707c0874 | 2386 | #endif |
da8999d3 LJ |
2387 | if (boot_cpu_has(X86_FEATURE_MPX)) |
2388 | rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs); | |
26bb0981 AK |
2389 | for (i = 0; i < vmx->save_nmsrs; ++i) |
2390 | kvm_set_shared_msr(vmx->guest_msrs[i].index, | |
d5696725 AK |
2391 | vmx->guest_msrs[i].data, |
2392 | vmx->guest_msrs[i].mask); | |
33ed6329 AK |
2393 | } |
2394 | ||
a9b21b62 | 2395 | static void __vmx_load_host_state(struct vcpu_vmx *vmx) |
33ed6329 | 2396 | { |
8a12167a | 2397 | if (!vmx->loaded_cpu_state) |
33ed6329 AK |
2398 | return; |
2399 | ||
8a12167a SC |
2400 | WARN_ON_ONCE(vmx->loaded_cpu_state != vmx->loaded_vmcs); |
2401 | ||
e1beb1d3 | 2402 | ++vmx->vcpu.stat.host_state_reload; |
8a12167a SC |
2403 | vmx->loaded_cpu_state = NULL; |
2404 | ||
c8770e7b AK |
2405 | #ifdef CONFIG_X86_64 |
2406 | if (is_long_mode(&vmx->vcpu)) | |
2407 | rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base); | |
2408 | #endif | |
152d3f2f | 2409 | if (vmx->host_state.gs_ldt_reload_needed) { |
d6e88aec | 2410 | kvm_load_ldt(vmx->host_state.ldt_sel); |
33ed6329 | 2411 | #ifdef CONFIG_X86_64 |
9581d442 | 2412 | load_gs_index(vmx->host_state.gs_sel); |
9581d442 AK |
2413 | #else |
2414 | loadsegment(gs, vmx->host_state.gs_sel); | |
33ed6329 | 2415 | #endif |
33ed6329 | 2416 | } |
0a77fe4c AK |
2417 | if (vmx->host_state.fs_reload_needed) |
2418 | loadsegment(fs, vmx->host_state.fs_sel); | |
b2da15ac AK |
2419 | #ifdef CONFIG_X86_64 |
2420 | if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) { | |
2421 | loadsegment(ds, vmx->host_state.ds_sel); | |
2422 | loadsegment(es, vmx->host_state.es_sel); | |
2423 | } | |
b2da15ac | 2424 | #endif |
b7ffc44d | 2425 | invalidate_tss_limit(); |
44ea2b17 | 2426 | #ifdef CONFIG_X86_64 |
c8770e7b | 2427 | wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base); |
44ea2b17 | 2428 | #endif |
da8999d3 LJ |
2429 | if (vmx->host_state.msr_host_bndcfgs) |
2430 | wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs); | |
45fc8757 | 2431 | load_fixmap_gdt(raw_smp_processor_id()); |
33ed6329 AK |
2432 | } |
2433 | ||
a9b21b62 AK |
2434 | static void vmx_load_host_state(struct vcpu_vmx *vmx) |
2435 | { | |
2436 | preempt_disable(); | |
2437 | __vmx_load_host_state(vmx); | |
2438 | preempt_enable(); | |
2439 | } | |
2440 | ||
28b835d6 FW |
2441 | static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu) |
2442 | { | |
2443 | struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); | |
2444 | struct pi_desc old, new; | |
2445 | unsigned int dest; | |
2446 | ||
31afb2ea PB |
2447 | /* |
2448 | * In case of hot-plug or hot-unplug, we may have to undo | |
2449 | * vmx_vcpu_pi_put even if there is no assigned device. And we | |
2450 | * always keep PI.NDST up to date for simplicity: it makes the | |
2451 | * code easier, and CPU migration is not a fast path. | |
2452 | */ | |
2453 | if (!pi_test_sn(pi_desc) && vcpu->cpu == cpu) | |
28b835d6 FW |
2454 | return; |
2455 | ||
31afb2ea PB |
2456 | /* |
2457 | * First handle the simple case where no cmpxchg is necessary; just | |
2458 | * allow posting non-urgent interrupts. | |
2459 | * | |
2460 | * If the 'nv' field is POSTED_INTR_WAKEUP_VECTOR, do not change | |
2461 | * PI.NDST: pi_post_block will do it for us and the wakeup_handler | |
2462 | * expects the VCPU to be on the blocked_vcpu_list that matches | |
2463 | * PI.NDST. | |
2464 | */ | |
2465 | if (pi_desc->nv == POSTED_INTR_WAKEUP_VECTOR || | |
2466 | vcpu->cpu == cpu) { | |
2467 | pi_clear_sn(pi_desc); | |
28b835d6 | 2468 | return; |
31afb2ea | 2469 | } |
28b835d6 | 2470 | |
31afb2ea | 2471 | /* The full case. */ |
28b835d6 FW |
2472 | do { |
2473 | old.control = new.control = pi_desc->control; | |
2474 | ||
31afb2ea | 2475 | dest = cpu_physical_id(cpu); |
28b835d6 | 2476 | |
31afb2ea PB |
2477 | if (x2apic_enabled()) |
2478 | new.ndst = dest; | |
2479 | else | |
2480 | new.ndst = (dest << 8) & 0xFF00; | |
28b835d6 | 2481 | |
28b835d6 | 2482 | new.sn = 0; |
c0a1666b PB |
2483 | } while (cmpxchg64(&pi_desc->control, old.control, |
2484 | new.control) != old.control); | |
28b835d6 | 2485 | } |
1be0e61c | 2486 | |
c95ba92a PF |
2487 | static void decache_tsc_multiplier(struct vcpu_vmx *vmx) |
2488 | { | |
2489 | vmx->current_tsc_ratio = vmx->vcpu.arch.tsc_scaling_ratio; | |
2490 | vmcs_write64(TSC_MULTIPLIER, vmx->current_tsc_ratio); | |
2491 | } | |
2492 | ||
6aa8b732 AK |
2493 | /* |
2494 | * Switches to specified vcpu, until a matching vcpu_put(), but assumes | |
2495 | * vcpu mutex is already taken. | |
2496 | */ | |
15ad7146 | 2497 | static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu) |
6aa8b732 | 2498 | { |
a2fa3e9f | 2499 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
b80c76ec | 2500 | bool already_loaded = vmx->loaded_vmcs->cpu == cpu; |
6aa8b732 | 2501 | |
b80c76ec | 2502 | if (!already_loaded) { |
fe0e80be | 2503 | loaded_vmcs_clear(vmx->loaded_vmcs); |
92fe13be | 2504 | local_irq_disable(); |
8f536b76 | 2505 | crash_disable_local_vmclear(cpu); |
5a560f8b XG |
2506 | |
2507 | /* | |
2508 | * Read loaded_vmcs->cpu should be before fetching | |
2509 | * loaded_vmcs->loaded_vmcss_on_cpu_link. | |
2510 | * See the comments in __loaded_vmcs_clear(). | |
2511 | */ | |
2512 | smp_rmb(); | |
2513 | ||
d462b819 NHE |
2514 | list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link, |
2515 | &per_cpu(loaded_vmcss_on_cpu, cpu)); | |
8f536b76 | 2516 | crash_enable_local_vmclear(cpu); |
92fe13be | 2517 | local_irq_enable(); |
b80c76ec JM |
2518 | } |
2519 | ||
2520 | if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) { | |
2521 | per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs; | |
2522 | vmcs_load(vmx->loaded_vmcs->vmcs); | |
33241bfe | 2523 | indirect_branch_prediction_barrier(); |
b80c76ec JM |
2524 | } |
2525 | ||
2526 | if (!already_loaded) { | |
59c58ceb | 2527 | void *gdt = get_current_gdt_ro(); |
b80c76ec JM |
2528 | unsigned long sysenter_esp; |
2529 | ||
2530 | kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); | |
92fe13be | 2531 | |
6aa8b732 AK |
2532 | /* |
2533 | * Linux uses per-cpu TSS and GDT, so set these when switching | |
e0c23063 | 2534 | * processors. See 22.2.4. |
6aa8b732 | 2535 | */ |
e0c23063 | 2536 | vmcs_writel(HOST_TR_BASE, |
72f5e08d | 2537 | (unsigned long)&get_cpu_entry_area(cpu)->tss.x86_tss); |
59c58ceb | 2538 | vmcs_writel(HOST_GDTR_BASE, (unsigned long)gdt); /* 22.2.4 */ |
6aa8b732 | 2539 | |
b7ffc44d AL |
2540 | /* |
2541 | * VM exits change the host TR limit to 0x67 after a VM | |
2542 | * exit. This is okay, since 0x67 covers everything except | |
2543 | * the IO bitmap and have have code to handle the IO bitmap | |
2544 | * being lost after a VM exit. | |
2545 | */ | |
2546 | BUILD_BUG_ON(IO_BITMAP_OFFSET - 1 != 0x67); | |
2547 | ||
6aa8b732 AK |
2548 | rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp); |
2549 | vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */ | |
ff2c3a18 | 2550 | |
d462b819 | 2551 | vmx->loaded_vmcs->cpu = cpu; |
6aa8b732 | 2552 | } |
28b835d6 | 2553 | |
2680d6da OH |
2554 | /* Setup TSC multiplier */ |
2555 | if (kvm_has_tsc_control && | |
c95ba92a PF |
2556 | vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio) |
2557 | decache_tsc_multiplier(vmx); | |
2680d6da | 2558 | |
28b835d6 | 2559 | vmx_vcpu_pi_load(vcpu, cpu); |
1be0e61c | 2560 | vmx->host_pkru = read_pkru(); |
28b835d6 FW |
2561 | } |
2562 | ||
2563 | static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu) | |
2564 | { | |
2565 | struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); | |
2566 | ||
2567 | if (!kvm_arch_has_assigned_device(vcpu->kvm) || | |
a0052191 YZ |
2568 | !irq_remapping_cap(IRQ_POSTING_CAP) || |
2569 | !kvm_vcpu_apicv_active(vcpu)) | |
28b835d6 FW |
2570 | return; |
2571 | ||
2572 | /* Set SN when the vCPU is preempted */ | |
2573 | if (vcpu->preempted) | |
2574 | pi_set_sn(pi_desc); | |
6aa8b732 AK |
2575 | } |
2576 | ||
2577 | static void vmx_vcpu_put(struct kvm_vcpu *vcpu) | |
2578 | { | |
28b835d6 FW |
2579 | vmx_vcpu_pi_put(vcpu); |
2580 | ||
a9b21b62 | 2581 | __vmx_load_host_state(to_vmx(vcpu)); |
6aa8b732 AK |
2582 | } |
2583 | ||
f244deed WL |
2584 | static bool emulation_required(struct kvm_vcpu *vcpu) |
2585 | { | |
2586 | return emulate_invalid_guest_state && !guest_state_valid(vcpu); | |
2587 | } | |
2588 | ||
edcafe3c AK |
2589 | static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu); |
2590 | ||
fe3ef05c NHE |
2591 | /* |
2592 | * Return the cr0 value that a nested guest would read. This is a combination | |
2593 | * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by | |
2594 | * its hypervisor (cr0_read_shadow). | |
2595 | */ | |
2596 | static inline unsigned long nested_read_cr0(struct vmcs12 *fields) | |
2597 | { | |
2598 | return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) | | |
2599 | (fields->cr0_read_shadow & fields->cr0_guest_host_mask); | |
2600 | } | |
2601 | static inline unsigned long nested_read_cr4(struct vmcs12 *fields) | |
2602 | { | |
2603 | return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) | | |
2604 | (fields->cr4_read_shadow & fields->cr4_guest_host_mask); | |
2605 | } | |
2606 | ||
6aa8b732 AK |
2607 | static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu) |
2608 | { | |
78ac8b47 | 2609 | unsigned long rflags, save_rflags; |
345dcaa8 | 2610 | |
6de12732 AK |
2611 | if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) { |
2612 | __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail); | |
2613 | rflags = vmcs_readl(GUEST_RFLAGS); | |
2614 | if (to_vmx(vcpu)->rmode.vm86_active) { | |
2615 | rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS; | |
2616 | save_rflags = to_vmx(vcpu)->rmode.save_rflags; | |
2617 | rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS; | |
2618 | } | |
2619 | to_vmx(vcpu)->rflags = rflags; | |
78ac8b47 | 2620 | } |
6de12732 | 2621 | return to_vmx(vcpu)->rflags; |
6aa8b732 AK |
2622 | } |
2623 | ||
2624 | static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) | |
2625 | { | |
f244deed WL |
2626 | unsigned long old_rflags = vmx_get_rflags(vcpu); |
2627 | ||
6de12732 AK |
2628 | __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail); |
2629 | to_vmx(vcpu)->rflags = rflags; | |
78ac8b47 AK |
2630 | if (to_vmx(vcpu)->rmode.vm86_active) { |
2631 | to_vmx(vcpu)->rmode.save_rflags = rflags; | |
053de044 | 2632 | rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM; |
78ac8b47 | 2633 | } |
6aa8b732 | 2634 | vmcs_writel(GUEST_RFLAGS, rflags); |
f244deed WL |
2635 | |
2636 | if ((old_rflags ^ to_vmx(vcpu)->rflags) & X86_EFLAGS_VM) | |
2637 | to_vmx(vcpu)->emulation_required = emulation_required(vcpu); | |
6aa8b732 AK |
2638 | } |
2639 | ||
37ccdcbe | 2640 | static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu) |
2809f5d2 GC |
2641 | { |
2642 | u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO); | |
2643 | int ret = 0; | |
2644 | ||
2645 | if (interruptibility & GUEST_INTR_STATE_STI) | |
48005f64 | 2646 | ret |= KVM_X86_SHADOW_INT_STI; |
2809f5d2 | 2647 | if (interruptibility & GUEST_INTR_STATE_MOV_SS) |
48005f64 | 2648 | ret |= KVM_X86_SHADOW_INT_MOV_SS; |
2809f5d2 | 2649 | |
37ccdcbe | 2650 | return ret; |
2809f5d2 GC |
2651 | } |
2652 | ||
2653 | static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask) | |
2654 | { | |
2655 | u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO); | |
2656 | u32 interruptibility = interruptibility_old; | |
2657 | ||
2658 | interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS); | |
2659 | ||
48005f64 | 2660 | if (mask & KVM_X86_SHADOW_INT_MOV_SS) |
2809f5d2 | 2661 | interruptibility |= GUEST_INTR_STATE_MOV_SS; |
48005f64 | 2662 | else if (mask & KVM_X86_SHADOW_INT_STI) |
2809f5d2 GC |
2663 | interruptibility |= GUEST_INTR_STATE_STI; |
2664 | ||
2665 | if ((interruptibility != interruptibility_old)) | |
2666 | vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility); | |
2667 | } | |
2668 | ||
6aa8b732 AK |
2669 | static void skip_emulated_instruction(struct kvm_vcpu *vcpu) |
2670 | { | |
2671 | unsigned long rip; | |
6aa8b732 | 2672 | |
5fdbf976 | 2673 | rip = kvm_rip_read(vcpu); |
6aa8b732 | 2674 | rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN); |
5fdbf976 | 2675 | kvm_rip_write(vcpu, rip); |
6aa8b732 | 2676 | |
2809f5d2 GC |
2677 | /* skipping an emulated instruction also counts */ |
2678 | vmx_set_interrupt_shadow(vcpu, 0); | |
6aa8b732 AK |
2679 | } |
2680 | ||
b96fb439 PB |
2681 | static void nested_vmx_inject_exception_vmexit(struct kvm_vcpu *vcpu, |
2682 | unsigned long exit_qual) | |
2683 | { | |
2684 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); | |
2685 | unsigned int nr = vcpu->arch.exception.nr; | |
2686 | u32 intr_info = nr | INTR_INFO_VALID_MASK; | |
2687 | ||
2688 | if (vcpu->arch.exception.has_error_code) { | |
2689 | vmcs12->vm_exit_intr_error_code = vcpu->arch.exception.error_code; | |
2690 | intr_info |= INTR_INFO_DELIVER_CODE_MASK; | |
2691 | } | |
2692 | ||
2693 | if (kvm_exception_is_soft(nr)) | |
2694 | intr_info |= INTR_TYPE_SOFT_EXCEPTION; | |
2695 | else | |
2696 | intr_info |= INTR_TYPE_HARD_EXCEPTION; | |
2697 | ||
2698 | if (!(vmcs12->idt_vectoring_info_field & VECTORING_INFO_VALID_MASK) && | |
2699 | vmx_get_nmi_mask(vcpu)) | |
2700 | intr_info |= INTR_INFO_UNBLOCK_NMI; | |
2701 | ||
2702 | nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI, intr_info, exit_qual); | |
2703 | } | |
2704 | ||
0b6ac343 NHE |
2705 | /* |
2706 | * KVM wants to inject page-faults which it got to the guest. This function | |
2707 | * checks whether in a nested guest, we need to inject them to L1 or L2. | |
0b6ac343 | 2708 | */ |
bfcf83b1 | 2709 | static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned long *exit_qual) |
0b6ac343 NHE |
2710 | { |
2711 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); | |
adfe20fb | 2712 | unsigned int nr = vcpu->arch.exception.nr; |
0b6ac343 | 2713 | |
b96fb439 PB |
2714 | if (nr == PF_VECTOR) { |
2715 | if (vcpu->arch.exception.nested_apf) { | |
bfcf83b1 | 2716 | *exit_qual = vcpu->arch.apf.nested_apf_token; |
b96fb439 PB |
2717 | return 1; |
2718 | } | |
2719 | /* | |
2720 | * FIXME: we must not write CR2 when L1 intercepts an L2 #PF exception. | |
2721 | * The fix is to add the ancillary datum (CR2 or DR6) to structs | |
2722 | * kvm_queued_exception and kvm_vcpu_events, so that CR2 and DR6 | |
2723 | * can be written only when inject_pending_event runs. This should be | |
2724 | * conditional on a new capability---if the capability is disabled, | |
2725 | * kvm_multiple_exception would write the ancillary information to | |
2726 | * CR2 or DR6, for backwards ABI-compatibility. | |
2727 | */ | |
2728 | if (nested_vmx_is_page_fault_vmexit(vmcs12, | |
2729 | vcpu->arch.exception.error_code)) { | |
bfcf83b1 | 2730 | *exit_qual = vcpu->arch.cr2; |
b96fb439 PB |
2731 | return 1; |
2732 | } | |
2733 | } else { | |
b96fb439 | 2734 | if (vmcs12->exception_bitmap & (1u << nr)) { |
a2812bb8 | 2735 | if (nr == DB_VECTOR) { |
bfcf83b1 | 2736 | *exit_qual = vcpu->arch.dr6; |
a2812bb8 JM |
2737 | *exit_qual &= ~(DR6_FIXED_1 | DR6_BT); |
2738 | *exit_qual ^= DR6_RTM; | |
2739 | } else { | |
bfcf83b1 | 2740 | *exit_qual = 0; |
a2812bb8 | 2741 | } |
b96fb439 PB |
2742 | return 1; |
2743 | } | |
adfe20fb WL |
2744 | } |
2745 | ||
b96fb439 | 2746 | return 0; |
0b6ac343 NHE |
2747 | } |
2748 | ||
cfcd20e5 | 2749 | static void vmx_queue_exception(struct kvm_vcpu *vcpu) |
298101da | 2750 | { |
77ab6db0 | 2751 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
cfcd20e5 WL |
2752 | unsigned nr = vcpu->arch.exception.nr; |
2753 | bool has_error_code = vcpu->arch.exception.has_error_code; | |
cfcd20e5 | 2754 | u32 error_code = vcpu->arch.exception.error_code; |
8ab2d2e2 | 2755 | u32 intr_info = nr | INTR_INFO_VALID_MASK; |
77ab6db0 | 2756 | |
8ab2d2e2 | 2757 | if (has_error_code) { |
77ab6db0 | 2758 | vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code); |
8ab2d2e2 JK |
2759 | intr_info |= INTR_INFO_DELIVER_CODE_MASK; |
2760 | } | |
77ab6db0 | 2761 | |
7ffd92c5 | 2762 | if (vmx->rmode.vm86_active) { |
71f9833b SH |
2763 | int inc_eip = 0; |
2764 | if (kvm_exception_is_soft(nr)) | |
2765 | inc_eip = vcpu->arch.event_exit_inst_len; | |
2766 | if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE) | |
a92601bb | 2767 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
77ab6db0 JK |
2768 | return; |
2769 | } | |
2770 | ||
299f0328 SC |
2771 | WARN_ON_ONCE(vmx->emulation_required); |
2772 | ||
66fd3f7f GN |
2773 | if (kvm_exception_is_soft(nr)) { |
2774 | vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, | |
2775 | vmx->vcpu.arch.event_exit_inst_len); | |
8ab2d2e2 JK |
2776 | intr_info |= INTR_TYPE_SOFT_EXCEPTION; |
2777 | } else | |
2778 | intr_info |= INTR_TYPE_HARD_EXCEPTION; | |
2779 | ||
2780 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info); | |
298101da AK |
2781 | } |
2782 | ||
4e47c7a6 SY |
2783 | static bool vmx_rdtscp_supported(void) |
2784 | { | |
2785 | return cpu_has_vmx_rdtscp(); | |
2786 | } | |
2787 | ||
ad756a16 MJ |
2788 | static bool vmx_invpcid_supported(void) |
2789 | { | |
2790 | return cpu_has_vmx_invpcid() && enable_ept; | |
2791 | } | |
2792 | ||
a75beee6 ED |
2793 | /* |
2794 | * Swap MSR entry in host/guest MSR entry array. | |
2795 | */ | |
8b9cf98c | 2796 | static void move_msr_up(struct vcpu_vmx *vmx, int from, int to) |
a75beee6 | 2797 | { |
26bb0981 | 2798 | struct shared_msr_entry tmp; |
a2fa3e9f GH |
2799 | |
2800 | tmp = vmx->guest_msrs[to]; | |
2801 | vmx->guest_msrs[to] = vmx->guest_msrs[from]; | |
2802 | vmx->guest_msrs[from] = tmp; | |
a75beee6 ED |
2803 | } |
2804 | ||
e38aea3e AK |
2805 | /* |
2806 | * Set up the vmcs to automatically save and restore system | |
2807 | * msrs. Don't touch the 64-bit msrs if the guest is in legacy | |
2808 | * mode, as fiddling with msrs is very expensive. | |
2809 | */ | |
8b9cf98c | 2810 | static void setup_msrs(struct vcpu_vmx *vmx) |
e38aea3e | 2811 | { |
26bb0981 | 2812 | int save_nmsrs, index; |
e38aea3e | 2813 | |
a75beee6 ED |
2814 | save_nmsrs = 0; |
2815 | #ifdef CONFIG_X86_64 | |
8b9cf98c | 2816 | if (is_long_mode(&vmx->vcpu)) { |
8b9cf98c | 2817 | index = __find_msr_index(vmx, MSR_SYSCALL_MASK); |
a75beee6 | 2818 | if (index >= 0) |
8b9cf98c RR |
2819 | move_msr_up(vmx, index, save_nmsrs++); |
2820 | index = __find_msr_index(vmx, MSR_LSTAR); | |
a75beee6 | 2821 | if (index >= 0) |
8b9cf98c RR |
2822 | move_msr_up(vmx, index, save_nmsrs++); |
2823 | index = __find_msr_index(vmx, MSR_CSTAR); | |
a75beee6 | 2824 | if (index >= 0) |
8b9cf98c | 2825 | move_msr_up(vmx, index, save_nmsrs++); |
a75beee6 | 2826 | /* |
8c06585d | 2827 | * MSR_STAR is only needed on long mode guests, and only |
a75beee6 ED |
2828 | * if efer.sce is enabled. |
2829 | */ | |
8c06585d | 2830 | index = __find_msr_index(vmx, MSR_STAR); |
f6801dff | 2831 | if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE)) |
8b9cf98c | 2832 | move_msr_up(vmx, index, save_nmsrs++); |
a75beee6 ED |
2833 | } |
2834 | #endif | |
92c0d900 AK |
2835 | index = __find_msr_index(vmx, MSR_EFER); |
2836 | if (index >= 0 && update_transition_efer(vmx, index)) | |
26bb0981 | 2837 | move_msr_up(vmx, index, save_nmsrs++); |
bb4c5f0a JM |
2838 | index = __find_msr_index(vmx, MSR_TSC_AUX); |
2839 | if (index >= 0 && guest_cpuid_has(&vmx->vcpu, X86_FEATURE_RDTSCP)) | |
2840 | move_msr_up(vmx, index, save_nmsrs++); | |
e38aea3e | 2841 | |
26bb0981 | 2842 | vmx->save_nmsrs = save_nmsrs; |
5897297b | 2843 | |
8d14695f | 2844 | if (cpu_has_vmx_msr_bitmap()) |
4b0be90f | 2845 | vmx_update_msr_bitmap(&vmx->vcpu); |
e38aea3e AK |
2846 | } |
2847 | ||
f7f5542f KA |
2848 | static u64 vmx_read_l1_tsc_offset(struct kvm_vcpu *vcpu) |
2849 | { | |
2850 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); | |
2851 | ||
2852 | if (is_guest_mode(vcpu) && | |
2853 | (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)) | |
2854 | return vcpu->arch.tsc_offset - vmcs12->tsc_offset; | |
2855 | ||
2856 | return vcpu->arch.tsc_offset; | |
2857 | } | |
2858 | ||
7cb0f5cc | 2859 | static u64 vmx_write_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 offset) |
6aa8b732 | 2860 | { |
7cb0f5cc | 2861 | u64 active_offset = offset; |
27fc51b2 | 2862 | if (is_guest_mode(vcpu)) { |
7991825b | 2863 | /* |
27fc51b2 NHE |
2864 | * We're here if L1 chose not to trap WRMSR to TSC. According |
2865 | * to the spec, this should set L1's TSC; The offset that L1 | |
2866 | * set for L2 remains unchanged, and still needs to be added | |
2867 | * to the newly set TSC to get L2's TSC. | |
7991825b | 2868 | */ |
7cb0f5cc LS |
2869 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); |
2870 | if (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING)) | |
2871 | active_offset += vmcs12->tsc_offset; | |
27fc51b2 | 2872 | } else { |
489223ed YY |
2873 | trace_kvm_write_tsc_offset(vcpu->vcpu_id, |
2874 | vmcs_read64(TSC_OFFSET), offset); | |
27fc51b2 | 2875 | } |
7cb0f5cc LS |
2876 | |
2877 | vmcs_write64(TSC_OFFSET, active_offset); | |
2878 | return active_offset; | |
6aa8b732 AK |
2879 | } |
2880 | ||
801d3424 NHE |
2881 | /* |
2882 | * nested_vmx_allowed() checks whether a guest should be allowed to use VMX | |
2883 | * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for | |
2884 | * all guests if the "nested" module option is off, and can also be disabled | |
2885 | * for a single guest by disabling its VMX cpuid bit. | |
2886 | */ | |
2887 | static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu) | |
2888 | { | |
d6321d49 | 2889 | return nested && guest_cpuid_has(vcpu, X86_FEATURE_VMX); |
801d3424 NHE |
2890 | } |
2891 | ||
b87a51ae NHE |
2892 | /* |
2893 | * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be | |
2894 | * returned for the various VMX controls MSRs when nested VMX is enabled. | |
2895 | * The same values should also be used to verify that vmcs12 control fields are | |
2896 | * valid during nested entry from L1 to L2. | |
2897 | * Each of these control msrs has a low and high 32-bit half: A low bit is on | |
2898 | * if the corresponding bit in the (32-bit) control field *must* be on, and a | |
2899 | * bit in the high half is on if the corresponding bit in the control field | |
2900 | * may be on. See also vmx_control_verify(). | |
b87a51ae | 2901 | */ |
b9c237bb | 2902 | static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx *vmx) |
b87a51ae NHE |
2903 | { |
2904 | /* | |
2905 | * Note that as a general rule, the high half of the MSRs (bits in | |
2906 | * the control fields which may be 1) should be initialized by the | |
2907 | * intersection of the underlying hardware's MSR (i.e., features which | |
2908 | * can be supported) and the list of features we want to expose - | |
2909 | * because they are known to be properly supported in our code. | |
2910 | * Also, usually, the low half of the MSRs (bits which must be 1) can | |
2911 | * be set to 0, meaning that L1 may turn off any of these bits. The | |
2912 | * reason is that if one of these bits is necessary, it will appear | |
2913 | * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control | |
2914 | * fields of vmcs01 and vmcs02, will turn these bits off - and | |
7313c698 | 2915 | * nested_vmx_exit_reflected() will not pass related exits to L1. |
b87a51ae NHE |
2916 | * These rules have exceptions below. |
2917 | */ | |
2918 | ||
2919 | /* pin-based controls */ | |
eabeaacc | 2920 | rdmsr(MSR_IA32_VMX_PINBASED_CTLS, |
b9c237bb WV |
2921 | vmx->nested.nested_vmx_pinbased_ctls_low, |
2922 | vmx->nested.nested_vmx_pinbased_ctls_high); | |
2923 | vmx->nested.nested_vmx_pinbased_ctls_low |= | |
2924 | PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR; | |
2925 | vmx->nested.nested_vmx_pinbased_ctls_high &= | |
2926 | PIN_BASED_EXT_INTR_MASK | | |
2927 | PIN_BASED_NMI_EXITING | | |
2928 | PIN_BASED_VIRTUAL_NMIS; | |
2929 | vmx->nested.nested_vmx_pinbased_ctls_high |= | |
2930 | PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR | | |
0238ea91 | 2931 | PIN_BASED_VMX_PREEMPTION_TIMER; |
d62caabb | 2932 | if (kvm_vcpu_apicv_active(&vmx->vcpu)) |
705699a1 WV |
2933 | vmx->nested.nested_vmx_pinbased_ctls_high |= |
2934 | PIN_BASED_POSTED_INTR; | |
b87a51ae | 2935 | |
3dbcd8da | 2936 | /* exit controls */ |
c0dfee58 | 2937 | rdmsr(MSR_IA32_VMX_EXIT_CTLS, |
b9c237bb WV |
2938 | vmx->nested.nested_vmx_exit_ctls_low, |
2939 | vmx->nested.nested_vmx_exit_ctls_high); | |
2940 | vmx->nested.nested_vmx_exit_ctls_low = | |
2941 | VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR; | |
e0ba1a6f | 2942 | |
b9c237bb | 2943 | vmx->nested.nested_vmx_exit_ctls_high &= |
b87a51ae | 2944 | #ifdef CONFIG_X86_64 |
c0dfee58 | 2945 | VM_EXIT_HOST_ADDR_SPACE_SIZE | |
b87a51ae | 2946 | #endif |
f4124500 | 2947 | VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT; |
b9c237bb WV |
2948 | vmx->nested.nested_vmx_exit_ctls_high |= |
2949 | VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR | | |
f4124500 | 2950 | VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER | |
e0ba1a6f BD |
2951 | VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT; |
2952 | ||
a87036ad | 2953 | if (kvm_mpx_supported()) |
b9c237bb | 2954 | vmx->nested.nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS; |
b87a51ae | 2955 | |
2996fca0 | 2956 | /* We support free control of debug control saving. */ |
0115f9cb | 2957 | vmx->nested.nested_vmx_exit_ctls_low &= ~VM_EXIT_SAVE_DEBUG_CONTROLS; |
2996fca0 | 2958 | |
b87a51ae NHE |
2959 | /* entry controls */ |
2960 | rdmsr(MSR_IA32_VMX_ENTRY_CTLS, | |
b9c237bb WV |
2961 | vmx->nested.nested_vmx_entry_ctls_low, |
2962 | vmx->nested.nested_vmx_entry_ctls_high); | |
2963 | vmx->nested.nested_vmx_entry_ctls_low = | |
2964 | VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR; | |
2965 | vmx->nested.nested_vmx_entry_ctls_high &= | |
57435349 JK |
2966 | #ifdef CONFIG_X86_64 |
2967 | VM_ENTRY_IA32E_MODE | | |
2968 | #endif | |
2969 | VM_ENTRY_LOAD_IA32_PAT; | |
b9c237bb WV |
2970 | vmx->nested.nested_vmx_entry_ctls_high |= |
2971 | (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER); | |
a87036ad | 2972 | if (kvm_mpx_supported()) |
b9c237bb | 2973 | vmx->nested.nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS; |
57435349 | 2974 | |
2996fca0 | 2975 | /* We support free control of debug control loading. */ |
0115f9cb | 2976 | vmx->nested.nested_vmx_entry_ctls_low &= ~VM_ENTRY_LOAD_DEBUG_CONTROLS; |
2996fca0 | 2977 | |
b87a51ae NHE |
2978 | /* cpu-based controls */ |
2979 | rdmsr(MSR_IA32_VMX_PROCBASED_CTLS, | |
b9c237bb WV |
2980 | vmx->nested.nested_vmx_procbased_ctls_low, |
2981 | vmx->nested.nested_vmx_procbased_ctls_high); | |
2982 | vmx->nested.nested_vmx_procbased_ctls_low = | |
2983 | CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR; | |
2984 | vmx->nested.nested_vmx_procbased_ctls_high &= | |
a294c9bb JK |
2985 | CPU_BASED_VIRTUAL_INTR_PENDING | |
2986 | CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING | | |
b87a51ae NHE |
2987 | CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING | |
2988 | CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING | | |
2989 | CPU_BASED_CR3_STORE_EXITING | | |
2990 | #ifdef CONFIG_X86_64 | |
2991 | CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING | | |
2992 | #endif | |
2993 | CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING | | |
5f3d45e7 MD |
2994 | CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_TRAP_FLAG | |
2995 | CPU_BASED_MONITOR_EXITING | CPU_BASED_RDPMC_EXITING | | |
2996 | CPU_BASED_RDTSC_EXITING | CPU_BASED_PAUSE_EXITING | | |
2997 | CPU_BASED_TPR_SHADOW | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS; | |
b87a51ae NHE |
2998 | /* |
2999 | * We can allow some features even when not supported by the | |
3000 | * hardware. For example, L1 can specify an MSR bitmap - and we | |
3001 | * can use it to avoid exits to L1 - even when L0 runs L2 | |
3002 | * without MSR bitmaps. | |
3003 | */ | |
b9c237bb WV |
3004 | vmx->nested.nested_vmx_procbased_ctls_high |= |
3005 | CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR | | |
560b7ee1 | 3006 | CPU_BASED_USE_MSR_BITMAPS; |
b87a51ae | 3007 | |
3dcdf3ec | 3008 | /* We support free control of CR3 access interception. */ |
0115f9cb | 3009 | vmx->nested.nested_vmx_procbased_ctls_low &= |
3dcdf3ec JK |
3010 | ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING); |
3011 | ||
80154d77 PB |
3012 | /* |
3013 | * secondary cpu-based controls. Do not include those that | |
3014 | * depend on CPUID bits, they are added later by vmx_cpuid_update. | |
3015 | */ | |
b87a51ae | 3016 | rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2, |
b9c237bb WV |
3017 | vmx->nested.nested_vmx_secondary_ctls_low, |
3018 | vmx->nested.nested_vmx_secondary_ctls_high); | |
3019 | vmx->nested.nested_vmx_secondary_ctls_low = 0; | |
3020 | vmx->nested.nested_vmx_secondary_ctls_high &= | |
d6851fbe | 3021 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | |
1b07304c | 3022 | SECONDARY_EXEC_DESC | |
f2b93280 | 3023 | SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | |
82f0dd4b | 3024 | SECONDARY_EXEC_APIC_REGISTER_VIRT | |
608406e2 | 3025 | SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | |
3db13480 | 3026 | SECONDARY_EXEC_WBINVD_EXITING; |
c18911a2 | 3027 | |
afa61f75 NHE |
3028 | if (enable_ept) { |
3029 | /* nested EPT: emulate EPT also to L1 */ | |
b9c237bb | 3030 | vmx->nested.nested_vmx_secondary_ctls_high |= |
0790ec17 | 3031 | SECONDARY_EXEC_ENABLE_EPT; |
b9c237bb | 3032 | vmx->nested.nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT | |
7db74265 | 3033 | VMX_EPTP_WB_BIT | VMX_EPT_INVEPT_BIT; |
02120c45 BD |
3034 | if (cpu_has_vmx_ept_execute_only()) |
3035 | vmx->nested.nested_vmx_ept_caps |= | |
3036 | VMX_EPT_EXECUTE_ONLY_BIT; | |
b9c237bb | 3037 | vmx->nested.nested_vmx_ept_caps &= vmx_capability.ept; |
45e11817 | 3038 | vmx->nested.nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT | |
7db74265 PB |
3039 | VMX_EPT_EXTENT_CONTEXT_BIT | VMX_EPT_2MB_PAGE_BIT | |
3040 | VMX_EPT_1GB_PAGE_BIT; | |
03efce6f BD |
3041 | if (enable_ept_ad_bits) { |
3042 | vmx->nested.nested_vmx_secondary_ctls_high |= | |
3043 | SECONDARY_EXEC_ENABLE_PML; | |
7461fbc4 | 3044 | vmx->nested.nested_vmx_ept_caps |= VMX_EPT_AD_BIT; |
03efce6f | 3045 | } |
1c13bffd | 3046 | } |
afa61f75 | 3047 | |
27c42a1b BD |
3048 | if (cpu_has_vmx_vmfunc()) { |
3049 | vmx->nested.nested_vmx_secondary_ctls_high |= | |
3050 | SECONDARY_EXEC_ENABLE_VMFUNC; | |
41ab9372 BD |
3051 | /* |
3052 | * Advertise EPTP switching unconditionally | |
3053 | * since we emulate it | |
3054 | */ | |
575b3a2c WL |
3055 | if (enable_ept) |
3056 | vmx->nested.nested_vmx_vmfunc_controls = | |
3057 | VMX_VMFUNC_EPTP_SWITCHING; | |
27c42a1b BD |
3058 | } |
3059 | ||
ef697a71 PB |
3060 | /* |
3061 | * Old versions of KVM use the single-context version without | |
3062 | * checking for support, so declare that it is supported even | |
3063 | * though it is treated as global context. The alternative is | |
3064 | * not failing the single-context invvpid, and it is worse. | |
3065 | */ | |
63cb6d5f WL |
3066 | if (enable_vpid) { |
3067 | vmx->nested.nested_vmx_secondary_ctls_high |= | |
3068 | SECONDARY_EXEC_ENABLE_VPID; | |
089d7b6e | 3069 | vmx->nested.nested_vmx_vpid_caps = VMX_VPID_INVVPID_BIT | |
bcdde302 | 3070 | VMX_VPID_EXTENT_SUPPORTED_MASK; |
1c13bffd | 3071 | } |
99b83ac8 | 3072 | |
0790ec17 RK |
3073 | if (enable_unrestricted_guest) |
3074 | vmx->nested.nested_vmx_secondary_ctls_high |= | |
3075 | SECONDARY_EXEC_UNRESTRICTED_GUEST; | |
3076 | ||
c18911a2 | 3077 | /* miscellaneous data */ |
b9c237bb WV |
3078 | rdmsr(MSR_IA32_VMX_MISC, |
3079 | vmx->nested.nested_vmx_misc_low, | |
3080 | vmx->nested.nested_vmx_misc_high); | |
3081 | vmx->nested.nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA; | |
3082 | vmx->nested.nested_vmx_misc_low |= | |
3083 | VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE | | |
f4124500 | 3084 | VMX_MISC_ACTIVITY_HLT; |
b9c237bb | 3085 | vmx->nested.nested_vmx_misc_high = 0; |
62cc6b9d DM |
3086 | |
3087 | /* | |
3088 | * This MSR reports some information about VMX support. We | |
3089 | * should return information about the VMX we emulate for the | |
3090 | * guest, and the VMCS structure we give it - not about the | |
3091 | * VMX support of the underlying hardware. | |
3092 | */ | |
3093 | vmx->nested.nested_vmx_basic = | |
3094 | VMCS12_REVISION | | |
3095 | VMX_BASIC_TRUE_CTLS | | |
3096 | ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) | | |
3097 | (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT); | |
3098 | ||
3099 | if (cpu_has_vmx_basic_inout()) | |
3100 | vmx->nested.nested_vmx_basic |= VMX_BASIC_INOUT; | |
3101 | ||
3102 | /* | |
8322ebbb | 3103 | * These MSRs specify bits which the guest must keep fixed on |
62cc6b9d DM |
3104 | * while L1 is in VMXON mode (in L1's root mode, or running an L2). |
3105 | * We picked the standard core2 setting. | |
3106 | */ | |
3107 | #define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE) | |
3108 | #define VMXON_CR4_ALWAYSON X86_CR4_VMXE | |
3109 | vmx->nested.nested_vmx_cr0_fixed0 = VMXON_CR0_ALWAYSON; | |
62cc6b9d | 3110 | vmx->nested.nested_vmx_cr4_fixed0 = VMXON_CR4_ALWAYSON; |
8322ebbb DM |
3111 | |
3112 | /* These MSRs specify bits which the guest must keep fixed off. */ | |
3113 | rdmsrl(MSR_IA32_VMX_CR0_FIXED1, vmx->nested.nested_vmx_cr0_fixed1); | |
3114 | rdmsrl(MSR_IA32_VMX_CR4_FIXED1, vmx->nested.nested_vmx_cr4_fixed1); | |
62cc6b9d DM |
3115 | |
3116 | /* highest index: VMX_PREEMPTION_TIMER_VALUE */ | |
3117 | vmx->nested.nested_vmx_vmcs_enum = 0x2e; | |
b87a51ae NHE |
3118 | } |
3119 | ||
3899152c DM |
3120 | /* |
3121 | * if fixed0[i] == 1: val[i] must be 1 | |
3122 | * if fixed1[i] == 0: val[i] must be 0 | |
3123 | */ | |
3124 | static inline bool fixed_bits_valid(u64 val, u64 fixed0, u64 fixed1) | |
3125 | { | |
3126 | return ((val & fixed1) | fixed0) == val; | |
b87a51ae NHE |
3127 | } |
3128 | ||
3129 | static inline bool vmx_control_verify(u32 control, u32 low, u32 high) | |
3130 | { | |
3899152c | 3131 | return fixed_bits_valid(control, low, high); |
b87a51ae NHE |
3132 | } |
3133 | ||
3134 | static inline u64 vmx_control_msr(u32 low, u32 high) | |
3135 | { | |
3136 | return low | ((u64)high << 32); | |
3137 | } | |
3138 | ||
62cc6b9d DM |
3139 | static bool is_bitwise_subset(u64 superset, u64 subset, u64 mask) |
3140 | { | |
3141 | superset &= mask; | |
3142 | subset &= mask; | |
3143 | ||
3144 | return (superset | subset) == superset; | |
3145 | } | |
3146 | ||
3147 | static int vmx_restore_vmx_basic(struct vcpu_vmx *vmx, u64 data) | |
3148 | { | |
3149 | const u64 feature_and_reserved = | |
3150 | /* feature (except bit 48; see below) */ | |
3151 | BIT_ULL(49) | BIT_ULL(54) | BIT_ULL(55) | | |
3152 | /* reserved */ | |
3153 | BIT_ULL(31) | GENMASK_ULL(47, 45) | GENMASK_ULL(63, 56); | |
3154 | u64 vmx_basic = vmx->nested.nested_vmx_basic; | |
3155 | ||
3156 | if (!is_bitwise_subset(vmx_basic, data, feature_and_reserved)) | |
3157 | return -EINVAL; | |
3158 | ||
3159 | /* | |
3160 | * KVM does not emulate a version of VMX that constrains physical | |
3161 | * addresses of VMX structures (e.g. VMCS) to 32-bits. | |
3162 | */ | |
3163 | if (data & BIT_ULL(48)) | |
3164 | return -EINVAL; | |
3165 | ||
3166 | if (vmx_basic_vmcs_revision_id(vmx_basic) != | |
3167 | vmx_basic_vmcs_revision_id(data)) | |
3168 | return -EINVAL; | |
3169 | ||
3170 | if (vmx_basic_vmcs_size(vmx_basic) > vmx_basic_vmcs_size(data)) | |
3171 | return -EINVAL; | |
3172 | ||
3173 | vmx->nested.nested_vmx_basic = data; | |
3174 | return 0; | |
3175 | } | |
3176 | ||
3177 | static int | |
3178 | vmx_restore_control_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data) | |
3179 | { | |
3180 | u64 supported; | |
3181 | u32 *lowp, *highp; | |
3182 | ||
3183 | switch (msr_index) { | |
3184 | case MSR_IA32_VMX_TRUE_PINBASED_CTLS: | |
3185 | lowp = &vmx->nested.nested_vmx_pinbased_ctls_low; | |
3186 | highp = &vmx->nested.nested_vmx_pinbased_ctls_high; | |
3187 | break; | |
3188 | case MSR_IA32_VMX_TRUE_PROCBASED_CTLS: | |
3189 | lowp = &vmx->nested.nested_vmx_procbased_ctls_low; | |
3190 | highp = &vmx->nested.nested_vmx_procbased_ctls_high; | |
3191 | break; | |
3192 | case MSR_IA32_VMX_TRUE_EXIT_CTLS: | |
3193 | lowp = &vmx->nested.nested_vmx_exit_ctls_low; | |
3194 | highp = &vmx->nested.nested_vmx_exit_ctls_high; | |
3195 | break; | |
3196 | case MSR_IA32_VMX_TRUE_ENTRY_CTLS: | |
3197 | lowp = &vmx->nested.nested_vmx_entry_ctls_low; | |
3198 | highp = &vmx->nested.nested_vmx_entry_ctls_high; | |
3199 | break; | |
3200 | case MSR_IA32_VMX_PROCBASED_CTLS2: | |
3201 | lowp = &vmx->nested.nested_vmx_secondary_ctls_low; | |
3202 | highp = &vmx->nested.nested_vmx_secondary_ctls_high; | |
3203 | break; | |
3204 | default: | |
3205 | BUG(); | |
3206 | } | |
3207 | ||
3208 | supported = vmx_control_msr(*lowp, *highp); | |
3209 | ||
3210 | /* Check must-be-1 bits are still 1. */ | |
3211 | if (!is_bitwise_subset(data, supported, GENMASK_ULL(31, 0))) | |
3212 | return -EINVAL; | |
3213 | ||
3214 | /* Check must-be-0 bits are still 0. */ | |
3215 | if (!is_bitwise_subset(supported, data, GENMASK_ULL(63, 32))) | |
3216 | return -EINVAL; | |
3217 | ||
3218 | *lowp = data; | |
3219 | *highp = data >> 32; | |
3220 | return 0; | |
3221 | } | |
3222 | ||
3223 | static int vmx_restore_vmx_misc(struct vcpu_vmx *vmx, u64 data) | |
3224 | { | |
3225 | const u64 feature_and_reserved_bits = | |
3226 | /* feature */ | |
3227 | BIT_ULL(5) | GENMASK_ULL(8, 6) | BIT_ULL(14) | BIT_ULL(15) | | |
3228 | BIT_ULL(28) | BIT_ULL(29) | BIT_ULL(30) | | |
3229 | /* reserved */ | |
3230 | GENMASK_ULL(13, 9) | BIT_ULL(31); | |
3231 | u64 vmx_misc; | |
3232 | ||
3233 | vmx_misc = vmx_control_msr(vmx->nested.nested_vmx_misc_low, | |
3234 | vmx->nested.nested_vmx_misc_high); | |
3235 | ||
3236 | if (!is_bitwise_subset(vmx_misc, data, feature_and_reserved_bits)) | |
3237 | return -EINVAL; | |
3238 | ||
3239 | if ((vmx->nested.nested_vmx_pinbased_ctls_high & | |
3240 | PIN_BASED_VMX_PREEMPTION_TIMER) && | |
3241 | vmx_misc_preemption_timer_rate(data) != | |
3242 | vmx_misc_preemption_timer_rate(vmx_misc)) | |
3243 | return -EINVAL; | |
3244 | ||
3245 | if (vmx_misc_cr3_count(data) > vmx_misc_cr3_count(vmx_misc)) | |
3246 | return -EINVAL; | |
3247 | ||
3248 | if (vmx_misc_max_msr(data) > vmx_misc_max_msr(vmx_misc)) | |
3249 | return -EINVAL; | |
3250 | ||
3251 | if (vmx_misc_mseg_revid(data) != vmx_misc_mseg_revid(vmx_misc)) | |
3252 | return -EINVAL; | |
3253 | ||
3254 | vmx->nested.nested_vmx_misc_low = data; | |
3255 | vmx->nested.nested_vmx_misc_high = data >> 32; | |
3256 | return 0; | |
3257 | } | |
3258 | ||
3259 | static int vmx_restore_vmx_ept_vpid_cap(struct vcpu_vmx *vmx, u64 data) | |
3260 | { | |
3261 | u64 vmx_ept_vpid_cap; | |
3262 | ||
3263 | vmx_ept_vpid_cap = vmx_control_msr(vmx->nested.nested_vmx_ept_caps, | |
3264 | vmx->nested.nested_vmx_vpid_caps); | |
3265 | ||
3266 | /* Every bit is either reserved or a feature bit. */ | |
3267 | if (!is_bitwise_subset(vmx_ept_vpid_cap, data, -1ULL)) | |
3268 | return -EINVAL; | |
3269 | ||
3270 | vmx->nested.nested_vmx_ept_caps = data; | |
3271 | vmx->nested.nested_vmx_vpid_caps = data >> 32; | |
3272 | return 0; | |
3273 | } | |
3274 | ||
3275 | static int vmx_restore_fixed0_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data) | |
3276 | { | |
3277 | u64 *msr; | |
3278 | ||
3279 | switch (msr_index) { | |
3280 | case MSR_IA32_VMX_CR0_FIXED0: | |
3281 | msr = &vmx->nested.nested_vmx_cr0_fixed0; | |
3282 | break; | |
3283 | case MSR_IA32_VMX_CR4_FIXED0: | |
3284 | msr = &vmx->nested.nested_vmx_cr4_fixed0; | |
3285 | break; | |
3286 | default: | |
3287 | BUG(); | |
3288 | } | |
3289 | ||
3290 | /* | |
3291 | * 1 bits (which indicates bits which "must-be-1" during VMX operation) | |
3292 | * must be 1 in the restored value. | |
3293 | */ | |
3294 | if (!is_bitwise_subset(data, *msr, -1ULL)) | |
3295 | return -EINVAL; | |
3296 | ||
3297 | *msr = data; | |
3298 | return 0; | |
3299 | } | |
3300 | ||
3301 | /* | |
3302 | * Called when userspace is restoring VMX MSRs. | |
3303 | * | |
3304 | * Returns 0 on success, non-0 otherwise. | |
3305 | */ | |
3306 | static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data) | |
b87a51ae | 3307 | { |
b9c237bb WV |
3308 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
3309 | ||
b87a51ae | 3310 | switch (msr_index) { |
b87a51ae | 3311 | case MSR_IA32_VMX_BASIC: |
62cc6b9d DM |
3312 | return vmx_restore_vmx_basic(vmx, data); |
3313 | case MSR_IA32_VMX_PINBASED_CTLS: | |
3314 | case MSR_IA32_VMX_PROCBASED_CTLS: | |
3315 | case MSR_IA32_VMX_EXIT_CTLS: | |
3316 | case MSR_IA32_VMX_ENTRY_CTLS: | |
b87a51ae | 3317 | /* |
62cc6b9d DM |
3318 | * The "non-true" VMX capability MSRs are generated from the |
3319 | * "true" MSRs, so we do not support restoring them directly. | |
3320 | * | |
3321 | * If userspace wants to emulate VMX_BASIC[55]=0, userspace | |
3322 | * should restore the "true" MSRs with the must-be-1 bits | |
3323 | * set according to the SDM Vol 3. A.2 "RESERVED CONTROLS AND | |
3324 | * DEFAULT SETTINGS". | |
b87a51ae | 3325 | */ |
62cc6b9d DM |
3326 | return -EINVAL; |
3327 | case MSR_IA32_VMX_TRUE_PINBASED_CTLS: | |
3328 | case MSR_IA32_VMX_TRUE_PROCBASED_CTLS: | |
3329 | case MSR_IA32_VMX_TRUE_EXIT_CTLS: | |
3330 | case MSR_IA32_VMX_TRUE_ENTRY_CTLS: | |
3331 | case MSR_IA32_VMX_PROCBASED_CTLS2: | |
3332 | return vmx_restore_control_msr(vmx, msr_index, data); | |
3333 | case MSR_IA32_VMX_MISC: | |
3334 | return vmx_restore_vmx_misc(vmx, data); | |
3335 | case MSR_IA32_VMX_CR0_FIXED0: | |
3336 | case MSR_IA32_VMX_CR4_FIXED0: | |
3337 | return vmx_restore_fixed0_msr(vmx, msr_index, data); | |
3338 | case MSR_IA32_VMX_CR0_FIXED1: | |
3339 | case MSR_IA32_VMX_CR4_FIXED1: | |
3340 | /* | |
3341 | * These MSRs are generated based on the vCPU's CPUID, so we | |
3342 | * do not support restoring them directly. | |
3343 | */ | |
3344 | return -EINVAL; | |
3345 | case MSR_IA32_VMX_EPT_VPID_CAP: | |
3346 | return vmx_restore_vmx_ept_vpid_cap(vmx, data); | |
3347 | case MSR_IA32_VMX_VMCS_ENUM: | |
3348 | vmx->nested.nested_vmx_vmcs_enum = data; | |
3349 | return 0; | |
3350 | default: | |
b87a51ae | 3351 | /* |
62cc6b9d | 3352 | * The rest of the VMX capability MSRs do not support restore. |
b87a51ae | 3353 | */ |
62cc6b9d DM |
3354 | return -EINVAL; |
3355 | } | |
3356 | } | |
3357 | ||
3358 | /* Returns 0 on success, non-0 otherwise. */ | |
3359 | static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata) | |
3360 | { | |
3361 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
3362 | ||
3363 | switch (msr_index) { | |
3364 | case MSR_IA32_VMX_BASIC: | |
3365 | *pdata = vmx->nested.nested_vmx_basic; | |
b87a51ae NHE |
3366 | break; |
3367 | case MSR_IA32_VMX_TRUE_PINBASED_CTLS: | |
3368 | case MSR_IA32_VMX_PINBASED_CTLS: | |
b9c237bb WV |
3369 | *pdata = vmx_control_msr( |
3370 | vmx->nested.nested_vmx_pinbased_ctls_low, | |
3371 | vmx->nested.nested_vmx_pinbased_ctls_high); | |
0115f9cb DM |
3372 | if (msr_index == MSR_IA32_VMX_PINBASED_CTLS) |
3373 | *pdata |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR; | |
b87a51ae NHE |
3374 | break; |
3375 | case MSR_IA32_VMX_TRUE_PROCBASED_CTLS: | |
3376 | case MSR_IA32_VMX_PROCBASED_CTLS: | |
b9c237bb WV |
3377 | *pdata = vmx_control_msr( |
3378 | vmx->nested.nested_vmx_procbased_ctls_low, | |
3379 | vmx->nested.nested_vmx_procbased_ctls_high); | |
0115f9cb DM |
3380 | if (msr_index == MSR_IA32_VMX_PROCBASED_CTLS) |
3381 | *pdata |= CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR; | |
b87a51ae NHE |
3382 | break; |
3383 | case MSR_IA32_VMX_TRUE_EXIT_CTLS: | |
3384 | case MSR_IA32_VMX_EXIT_CTLS: | |
b9c237bb WV |
3385 | *pdata = vmx_control_msr( |
3386 | vmx->nested.nested_vmx_exit_ctls_low, | |
3387 | vmx->nested.nested_vmx_exit_ctls_high); | |
0115f9cb DM |
3388 | if (msr_index == MSR_IA32_VMX_EXIT_CTLS) |
3389 | *pdata |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR; | |
b87a51ae NHE |
3390 | break; |
3391 | case MSR_IA32_VMX_TRUE_ENTRY_CTLS: | |
3392 | case MSR_IA32_VMX_ENTRY_CTLS: | |
b9c237bb WV |
3393 | *pdata = vmx_control_msr( |
3394 | vmx->nested.nested_vmx_entry_ctls_low, | |
3395 | vmx->nested.nested_vmx_entry_ctls_high); | |
0115f9cb DM |
3396 | if (msr_index == MSR_IA32_VMX_ENTRY_CTLS) |
3397 | *pdata |= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR; | |
b87a51ae NHE |
3398 | break; |
3399 | case MSR_IA32_VMX_MISC: | |
b9c237bb WV |
3400 | *pdata = vmx_control_msr( |
3401 | vmx->nested.nested_vmx_misc_low, | |
3402 | vmx->nested.nested_vmx_misc_high); | |
b87a51ae | 3403 | break; |
b87a51ae | 3404 | case MSR_IA32_VMX_CR0_FIXED0: |
62cc6b9d | 3405 | *pdata = vmx->nested.nested_vmx_cr0_fixed0; |
b87a51ae NHE |
3406 | break; |
3407 | case MSR_IA32_VMX_CR0_FIXED1: | |
62cc6b9d | 3408 | *pdata = vmx->nested.nested_vmx_cr0_fixed1; |
b87a51ae NHE |
3409 | break; |
3410 | case MSR_IA32_VMX_CR4_FIXED0: | |
62cc6b9d | 3411 | *pdata = vmx->nested.nested_vmx_cr4_fixed0; |
b87a51ae NHE |
3412 | break; |
3413 | case MSR_IA32_VMX_CR4_FIXED1: | |
62cc6b9d | 3414 | *pdata = vmx->nested.nested_vmx_cr4_fixed1; |
b87a51ae NHE |
3415 | break; |
3416 | case MSR_IA32_VMX_VMCS_ENUM: | |
62cc6b9d | 3417 | *pdata = vmx->nested.nested_vmx_vmcs_enum; |
b87a51ae NHE |
3418 | break; |
3419 | case MSR_IA32_VMX_PROCBASED_CTLS2: | |
b9c237bb WV |
3420 | *pdata = vmx_control_msr( |
3421 | vmx->nested.nested_vmx_secondary_ctls_low, | |
3422 | vmx->nested.nested_vmx_secondary_ctls_high); | |
b87a51ae NHE |
3423 | break; |
3424 | case MSR_IA32_VMX_EPT_VPID_CAP: | |
089d7b6e WL |
3425 | *pdata = vmx->nested.nested_vmx_ept_caps | |
3426 | ((u64)vmx->nested.nested_vmx_vpid_caps << 32); | |
b87a51ae | 3427 | break; |
27c42a1b BD |
3428 | case MSR_IA32_VMX_VMFUNC: |
3429 | *pdata = vmx->nested.nested_vmx_vmfunc_controls; | |
3430 | break; | |
b87a51ae | 3431 | default: |
b87a51ae | 3432 | return 1; |
b3897a49 NHE |
3433 | } |
3434 | ||
b87a51ae NHE |
3435 | return 0; |
3436 | } | |
3437 | ||
37e4c997 HZ |
3438 | static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu, |
3439 | uint64_t val) | |
3440 | { | |
3441 | uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits; | |
3442 | ||
3443 | return !(val & ~valid_bits); | |
3444 | } | |
3445 | ||
ab1bebf8 TL |
3446 | static int vmx_get_msr_feature(struct kvm_msr_entry *msr) |
3447 | { | |
3448 | return 1; | |
3449 | } | |
3450 | ||
6aa8b732 AK |
3451 | /* |
3452 | * Reads an msr value (of 'msr_index') into 'pdata'. | |
3453 | * Returns 0 on success, non-0 otherwise. | |
3454 | * Assumes vcpu_load() was already called. | |
3455 | */ | |
609e36d3 | 3456 | static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
6aa8b732 | 3457 | { |
26bb0981 | 3458 | struct shared_msr_entry *msr; |
6aa8b732 | 3459 | |
609e36d3 | 3460 | switch (msr_info->index) { |
05b3e0c2 | 3461 | #ifdef CONFIG_X86_64 |
6aa8b732 | 3462 | case MSR_FS_BASE: |
609e36d3 | 3463 | msr_info->data = vmcs_readl(GUEST_FS_BASE); |
6aa8b732 AK |
3464 | break; |
3465 | case MSR_GS_BASE: | |
609e36d3 | 3466 | msr_info->data = vmcs_readl(GUEST_GS_BASE); |
6aa8b732 | 3467 | break; |
44ea2b17 AK |
3468 | case MSR_KERNEL_GS_BASE: |
3469 | vmx_load_host_state(to_vmx(vcpu)); | |
609e36d3 | 3470 | msr_info->data = to_vmx(vcpu)->msr_guest_kernel_gs_base; |
44ea2b17 | 3471 | break; |
26bb0981 | 3472 | #endif |
6aa8b732 | 3473 | case MSR_EFER: |
609e36d3 | 3474 | return kvm_get_msr_common(vcpu, msr_info); |
74469996 KA |
3475 | case MSR_IA32_SPEC_CTRL: |
3476 | if (!msr_info->host_initiated && | |
5856293c | 3477 | !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL)) |
74469996 KA |
3478 | return 1; |
3479 | ||
3480 | msr_info->data = to_vmx(vcpu)->spec_ctrl; | |
3481 | break; | |
6aa8b732 | 3482 | case MSR_IA32_SYSENTER_CS: |
609e36d3 | 3483 | msr_info->data = vmcs_read32(GUEST_SYSENTER_CS); |
6aa8b732 AK |
3484 | break; |
3485 | case MSR_IA32_SYSENTER_EIP: | |
609e36d3 | 3486 | msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP); |
6aa8b732 AK |
3487 | break; |
3488 | case MSR_IA32_SYSENTER_ESP: | |
609e36d3 | 3489 | msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP); |
6aa8b732 | 3490 | break; |
0dd376e7 | 3491 | case MSR_IA32_BNDCFGS: |
691bd434 | 3492 | if (!kvm_mpx_supported() || |
d6321d49 RK |
3493 | (!msr_info->host_initiated && |
3494 | !guest_cpuid_has(vcpu, X86_FEATURE_MPX))) | |
93c4adc7 | 3495 | return 1; |
609e36d3 | 3496 | msr_info->data = vmcs_read64(GUEST_BNDCFGS); |
0dd376e7 | 3497 | break; |
c45dcc71 AR |
3498 | case MSR_IA32_MCG_EXT_CTL: |
3499 | if (!msr_info->host_initiated && | |
3500 | !(to_vmx(vcpu)->msr_ia32_feature_control & | |
3501 | FEATURE_CONTROL_LMCE)) | |
cae50139 | 3502 | return 1; |
c45dcc71 AR |
3503 | msr_info->data = vcpu->arch.mcg_ext_ctl; |
3504 | break; | |
cae50139 | 3505 | case MSR_IA32_FEATURE_CONTROL: |
3b84080b | 3506 | msr_info->data = to_vmx(vcpu)->msr_ia32_feature_control; |
cae50139 JK |
3507 | break; |
3508 | case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC: | |
3509 | if (!nested_vmx_allowed(vcpu)) | |
3510 | return 1; | |
609e36d3 | 3511 | return vmx_get_vmx_msr(vcpu, msr_info->index, &msr_info->data); |
20300099 | 3512 | case MSR_IA32_XSS: |
47ee4fb1 WL |
3513 | if (!vmx_xsaves_supported() || |
3514 | (!msr_info->host_initiated && | |
3515 | !(guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && | |
3516 | guest_cpuid_has(vcpu, X86_FEATURE_XSAVES)))) | |
20300099 | 3517 | return 1; |
609e36d3 | 3518 | msr_info->data = vcpu->arch.ia32_xss; |
20300099 | 3519 | break; |
4e47c7a6 | 3520 | case MSR_TSC_AUX: |
d6321d49 RK |
3521 | if (!msr_info->host_initiated && |
3522 | !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP)) | |
4e47c7a6 SY |
3523 | return 1; |
3524 | /* Otherwise falls through */ | |
6aa8b732 | 3525 | default: |
609e36d3 | 3526 | msr = find_msr_entry(to_vmx(vcpu), msr_info->index); |
3bab1f5d | 3527 | if (msr) { |
609e36d3 | 3528 | msr_info->data = msr->data; |
3bab1f5d | 3529 | break; |
6aa8b732 | 3530 | } |
609e36d3 | 3531 | return kvm_get_msr_common(vcpu, msr_info); |
6aa8b732 AK |
3532 | } |
3533 | ||
6aa8b732 AK |
3534 | return 0; |
3535 | } | |
3536 | ||
cae50139 JK |
3537 | static void vmx_leave_nested(struct kvm_vcpu *vcpu); |
3538 | ||
6aa8b732 AK |
3539 | /* |
3540 | * Writes msr value into into the appropriate "register". | |
3541 | * Returns 0 on success, non-0 otherwise. | |
3542 | * Assumes vcpu_load() was already called. | |
3543 | */ | |
8fe8ab46 | 3544 | static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
6aa8b732 | 3545 | { |
a2fa3e9f | 3546 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
26bb0981 | 3547 | struct shared_msr_entry *msr; |
2cc51560 | 3548 | int ret = 0; |
8fe8ab46 WA |
3549 | u32 msr_index = msr_info->index; |
3550 | u64 data = msr_info->data; | |
2cc51560 | 3551 | |
6aa8b732 | 3552 | switch (msr_index) { |
3bab1f5d | 3553 | case MSR_EFER: |
8fe8ab46 | 3554 | ret = kvm_set_msr_common(vcpu, msr_info); |
2cc51560 | 3555 | break; |
16175a79 | 3556 | #ifdef CONFIG_X86_64 |
6aa8b732 | 3557 | case MSR_FS_BASE: |
2fb92db1 | 3558 | vmx_segment_cache_clear(vmx); |
6aa8b732 AK |
3559 | vmcs_writel(GUEST_FS_BASE, data); |
3560 | break; | |
3561 | case MSR_GS_BASE: | |
2fb92db1 | 3562 | vmx_segment_cache_clear(vmx); |
6aa8b732 AK |
3563 | vmcs_writel(GUEST_GS_BASE, data); |
3564 | break; | |
44ea2b17 AK |
3565 | case MSR_KERNEL_GS_BASE: |
3566 | vmx_load_host_state(vmx); | |
3567 | vmx->msr_guest_kernel_gs_base = data; | |
3568 | break; | |
6aa8b732 AK |
3569 | #endif |
3570 | case MSR_IA32_SYSENTER_CS: | |
3571 | vmcs_write32(GUEST_SYSENTER_CS, data); | |
3572 | break; | |
3573 | case MSR_IA32_SYSENTER_EIP: | |
f5b42c33 | 3574 | vmcs_writel(GUEST_SYSENTER_EIP, data); |
6aa8b732 AK |
3575 | break; |
3576 | case MSR_IA32_SYSENTER_ESP: | |
f5b42c33 | 3577 | vmcs_writel(GUEST_SYSENTER_ESP, data); |
6aa8b732 | 3578 | break; |
0dd376e7 | 3579 | case MSR_IA32_BNDCFGS: |
691bd434 | 3580 | if (!kvm_mpx_supported() || |
d6321d49 RK |
3581 | (!msr_info->host_initiated && |
3582 | !guest_cpuid_has(vcpu, X86_FEATURE_MPX))) | |
93c4adc7 | 3583 | return 1; |
fd8cb433 | 3584 | if (is_noncanonical_address(data & PAGE_MASK, vcpu) || |
4531662d | 3585 | (data & MSR_IA32_BNDCFGS_RSVD)) |
93c4adc7 | 3586 | return 1; |
0dd376e7 LJ |
3587 | vmcs_write64(GUEST_BNDCFGS, data); |
3588 | break; | |
74469996 KA |
3589 | case MSR_IA32_SPEC_CTRL: |
3590 | if (!msr_info->host_initiated && | |
5856293c | 3591 | !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL)) |
74469996 KA |
3592 | return 1; |
3593 | ||
3594 | /* The STIBP bit doesn't fault even if it's not advertised */ | |
8fe36c9d | 3595 | if (data & ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | SPEC_CTRL_SSBD)) |
74469996 KA |
3596 | return 1; |
3597 | ||
3598 | vmx->spec_ctrl = data; | |
3599 | ||
3600 | if (!data) | |
3601 | break; | |
3602 | ||
3603 | /* | |
3604 | * For non-nested: | |
3605 | * When it's written (to non-zero) for the first time, pass | |
3606 | * it through. | |
3607 | * | |
3608 | * For nested: | |
3609 | * The handling of the MSR bitmap for L2 guests is done in | |
3610 | * nested_vmx_merge_msr_bitmap. We should not touch the | |
3611 | * vmcs02.msr_bitmap here since it gets completely overwritten | |
3612 | * in the merging. We update the vmcs01 here for L1 as well | |
3613 | * since it will end up touching the MSR anyway now. | |
3614 | */ | |
3615 | vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap, | |
3616 | MSR_IA32_SPEC_CTRL, | |
3617 | MSR_TYPE_RW); | |
3618 | break; | |
33241bfe AR |
3619 | case MSR_IA32_PRED_CMD: |
3620 | if (!msr_info->host_initiated && | |
33241bfe AR |
3621 | !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL)) |
3622 | return 1; | |
3623 | ||
3624 | if (data & ~PRED_CMD_IBPB) | |
3625 | return 1; | |
3626 | ||
3627 | if (!data) | |
3628 | break; | |
3629 | ||
3630 | wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB); | |
3631 | ||
3632 | /* | |
3633 | * For non-nested: | |
3634 | * When it's written (to non-zero) for the first time, pass | |
3635 | * it through. | |
3636 | * | |
3637 | * For nested: | |
3638 | * The handling of the MSR bitmap for L2 guests is done in | |
3639 | * nested_vmx_merge_msr_bitmap. We should not touch the | |
3640 | * vmcs02.msr_bitmap here since it gets completely overwritten | |
3641 | * in the merging. | |
3642 | */ | |
3643 | vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap, MSR_IA32_PRED_CMD, | |
3644 | MSR_TYPE_W); | |
3645 | break; | |
468d472f | 3646 | case MSR_IA32_CR_PAT: |
9a5c34a2 SC |
3647 | if (!kvm_pat_valid(data)) |
3648 | return 1; | |
3649 | ||
468d472f SY |
3650 | if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) { |
3651 | vmcs_write64(GUEST_IA32_PAT, data); | |
3652 | vcpu->arch.pat = data; | |
3653 | break; | |
3654 | } | |
8fe8ab46 | 3655 | ret = kvm_set_msr_common(vcpu, msr_info); |
4e47c7a6 | 3656 | break; |
ba904635 WA |
3657 | case MSR_IA32_TSC_ADJUST: |
3658 | ret = kvm_set_msr_common(vcpu, msr_info); | |
4e47c7a6 | 3659 | break; |
c45dcc71 AR |
3660 | case MSR_IA32_MCG_EXT_CTL: |
3661 | if ((!msr_info->host_initiated && | |
3662 | !(to_vmx(vcpu)->msr_ia32_feature_control & | |
3663 | FEATURE_CONTROL_LMCE)) || | |
3664 | (data & ~MCG_EXT_CTL_LMCE_EN)) | |
3665 | return 1; | |
3666 | vcpu->arch.mcg_ext_ctl = data; | |
3667 | break; | |
cae50139 | 3668 | case MSR_IA32_FEATURE_CONTROL: |
37e4c997 | 3669 | if (!vmx_feature_control_msr_valid(vcpu, data) || |
3b84080b | 3670 | (to_vmx(vcpu)->msr_ia32_feature_control & |
cae50139 JK |
3671 | FEATURE_CONTROL_LOCKED && !msr_info->host_initiated)) |
3672 | return 1; | |
3b84080b | 3673 | vmx->msr_ia32_feature_control = data; |
cae50139 JK |
3674 | if (msr_info->host_initiated && data == 0) |
3675 | vmx_leave_nested(vcpu); | |
3676 | break; | |
3677 | case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC: | |
62cc6b9d DM |
3678 | if (!msr_info->host_initiated) |
3679 | return 1; /* they are read-only */ | |
3680 | if (!nested_vmx_allowed(vcpu)) | |
3681 | return 1; | |
3682 | return vmx_set_vmx_msr(vcpu, msr_index, data); | |
20300099 | 3683 | case MSR_IA32_XSS: |
47ee4fb1 WL |
3684 | if (!vmx_xsaves_supported() || |
3685 | (!msr_info->host_initiated && | |
3686 | !(guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && | |
3687 | guest_cpuid_has(vcpu, X86_FEATURE_XSAVES)))) | |
20300099 WL |
3688 | return 1; |
3689 | /* | |
3690 | * The only supported bit as of Skylake is bit 8, but | |
3691 | * it is not supported on KVM. | |
3692 | */ | |
3693 | if (data != 0) | |
3694 | return 1; | |
3695 | vcpu->arch.ia32_xss = data; | |
3696 | if (vcpu->arch.ia32_xss != host_xss) | |
3697 | add_atomic_switch_msr(vmx, MSR_IA32_XSS, | |
129ce7ac | 3698 | vcpu->arch.ia32_xss, host_xss, false); |
20300099 WL |
3699 | else |
3700 | clear_atomic_switch_msr(vmx, MSR_IA32_XSS); | |
3701 | break; | |
4e47c7a6 | 3702 | case MSR_TSC_AUX: |
d6321d49 RK |
3703 | if (!msr_info->host_initiated && |
3704 | !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP)) | |
4e47c7a6 SY |
3705 | return 1; |
3706 | /* Check reserved bit, higher 32 bits should be zero */ | |
3707 | if ((data >> 32) != 0) | |
3708 | return 1; | |
3709 | /* Otherwise falls through */ | |
6aa8b732 | 3710 | default: |
8b9cf98c | 3711 | msr = find_msr_entry(vmx, msr_index); |
3bab1f5d | 3712 | if (msr) { |
8b3c3104 | 3713 | u64 old_msr_data = msr->data; |
3bab1f5d | 3714 | msr->data = data; |
2225fd56 AK |
3715 | if (msr - vmx->guest_msrs < vmx->save_nmsrs) { |
3716 | preempt_disable(); | |
8b3c3104 AH |
3717 | ret = kvm_set_shared_msr(msr->index, msr->data, |
3718 | msr->mask); | |
2225fd56 | 3719 | preempt_enable(); |
8b3c3104 AH |
3720 | if (ret) |
3721 | msr->data = old_msr_data; | |
2225fd56 | 3722 | } |
3bab1f5d | 3723 | break; |
6aa8b732 | 3724 | } |
8fe8ab46 | 3725 | ret = kvm_set_msr_common(vcpu, msr_info); |
6aa8b732 AK |
3726 | } |
3727 | ||
2cc51560 | 3728 | return ret; |
6aa8b732 AK |
3729 | } |
3730 | ||
5fdbf976 | 3731 | static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg) |
6aa8b732 | 3732 | { |
5fdbf976 MT |
3733 | __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail); |
3734 | switch (reg) { | |
3735 | case VCPU_REGS_RSP: | |
3736 | vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP); | |
3737 | break; | |
3738 | case VCPU_REGS_RIP: | |
3739 | vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP); | |
3740 | break; | |
6de4f3ad AK |
3741 | case VCPU_EXREG_PDPTR: |
3742 | if (enable_ept) | |
3743 | ept_save_pdptrs(vcpu); | |
3744 | break; | |
5fdbf976 MT |
3745 | default: |
3746 | break; | |
3747 | } | |
6aa8b732 AK |
3748 | } |
3749 | ||
6aa8b732 AK |
3750 | static __init int cpu_has_kvm_support(void) |
3751 | { | |
6210e37b | 3752 | return cpu_has_vmx(); |
6aa8b732 AK |
3753 | } |
3754 | ||
3755 | static __init int vmx_disabled_by_bios(void) | |
3756 | { | |
3757 | u64 msr; | |
3758 | ||
3759 | rdmsrl(MSR_IA32_FEATURE_CONTROL, msr); | |
cafd6659 | 3760 | if (msr & FEATURE_CONTROL_LOCKED) { |
23f3e991 | 3761 | /* launched w/ TXT and VMX disabled */ |
cafd6659 SW |
3762 | if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX) |
3763 | && tboot_enabled()) | |
3764 | return 1; | |
23f3e991 | 3765 | /* launched w/o TXT and VMX only enabled w/ TXT */ |
cafd6659 | 3766 | if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX) |
23f3e991 | 3767 | && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX) |
f9335afe SW |
3768 | && !tboot_enabled()) { |
3769 | printk(KERN_WARNING "kvm: disable TXT in the BIOS or " | |
23f3e991 | 3770 | "activate TXT before enabling KVM\n"); |
cafd6659 | 3771 | return 1; |
f9335afe | 3772 | } |
23f3e991 JC |
3773 | /* launched w/o TXT and VMX disabled */ |
3774 | if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX) | |
3775 | && !tboot_enabled()) | |
3776 | return 1; | |
cafd6659 SW |
3777 | } |
3778 | ||
3779 | return 0; | |
6aa8b732 AK |
3780 | } |
3781 | ||
7725b894 DX |
3782 | static void kvm_cpu_vmxon(u64 addr) |
3783 | { | |
fe0e80be | 3784 | cr4_set_bits(X86_CR4_VMXE); |
1c5ac21a AS |
3785 | intel_pt_handle_vmx(1); |
3786 | ||
7725b894 DX |
3787 | asm volatile (ASM_VMX_VMXON_RAX |
3788 | : : "a"(&addr), "m"(addr) | |
3789 | : "memory", "cc"); | |
3790 | } | |
3791 | ||
13a34e06 | 3792 | static int hardware_enable(void) |
6aa8b732 AK |
3793 | { |
3794 | int cpu = raw_smp_processor_id(); | |
3795 | u64 phys_addr = __pa(per_cpu(vmxarea, cpu)); | |
cafd6659 | 3796 | u64 old, test_bits; |
6aa8b732 | 3797 | |
1e02ce4c | 3798 | if (cr4_read_shadow() & X86_CR4_VMXE) |
10474ae8 AG |
3799 | return -EBUSY; |
3800 | ||
d462b819 | 3801 | INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu)); |
bf9f6ac8 FW |
3802 | INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu)); |
3803 | spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu)); | |
8f536b76 ZY |
3804 | |
3805 | /* | |
3806 | * Now we can enable the vmclear operation in kdump | |
3807 | * since the loaded_vmcss_on_cpu list on this cpu | |
3808 | * has been initialized. | |
3809 | * | |
3810 | * Though the cpu is not in VMX operation now, there | |
3811 | * is no problem to enable the vmclear operation | |
3812 | * for the loaded_vmcss_on_cpu list is empty! | |
3813 | */ | |
3814 | crash_enable_local_vmclear(cpu); | |
3815 | ||
6aa8b732 | 3816 | rdmsrl(MSR_IA32_FEATURE_CONTROL, old); |
cafd6659 SW |
3817 | |
3818 | test_bits = FEATURE_CONTROL_LOCKED; | |
3819 | test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX; | |
3820 | if (tboot_enabled()) | |
3821 | test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX; | |
3822 | ||
3823 | if ((old & test_bits) != test_bits) { | |
6aa8b732 | 3824 | /* enable and lock */ |
cafd6659 SW |
3825 | wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits); |
3826 | } | |
fe0e80be | 3827 | kvm_cpu_vmxon(phys_addr); |
fdf288bf DH |
3828 | if (enable_ept) |
3829 | ept_sync_global(); | |
10474ae8 AG |
3830 | |
3831 | return 0; | |
6aa8b732 AK |
3832 | } |
3833 | ||
d462b819 | 3834 | static void vmclear_local_loaded_vmcss(void) |
543e4243 AK |
3835 | { |
3836 | int cpu = raw_smp_processor_id(); | |
d462b819 | 3837 | struct loaded_vmcs *v, *n; |
543e4243 | 3838 | |
d462b819 NHE |
3839 | list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu), |
3840 | loaded_vmcss_on_cpu_link) | |
3841 | __loaded_vmcs_clear(v); | |
543e4243 AK |
3842 | } |
3843 | ||
710ff4a8 EH |
3844 | |
3845 | /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot() | |
3846 | * tricks. | |
3847 | */ | |
3848 | static void kvm_cpu_vmxoff(void) | |
6aa8b732 | 3849 | { |
4ecac3fd | 3850 | asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc"); |
1c5ac21a AS |
3851 | |
3852 | intel_pt_handle_vmx(0); | |
fe0e80be | 3853 | cr4_clear_bits(X86_CR4_VMXE); |
6aa8b732 AK |
3854 | } |
3855 | ||
13a34e06 | 3856 | static void hardware_disable(void) |
710ff4a8 | 3857 | { |
fe0e80be DH |
3858 | vmclear_local_loaded_vmcss(); |
3859 | kvm_cpu_vmxoff(); | |
710ff4a8 EH |
3860 | } |
3861 | ||
1c3d14fe | 3862 | static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt, |
d77c26fc | 3863 | u32 msr, u32 *result) |
1c3d14fe YS |
3864 | { |
3865 | u32 vmx_msr_low, vmx_msr_high; | |
3866 | u32 ctl = ctl_min | ctl_opt; | |
3867 | ||
3868 | rdmsr(msr, vmx_msr_low, vmx_msr_high); | |
3869 | ||
3870 | ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */ | |
3871 | ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */ | |
3872 | ||
3873 | /* Ensure minimum (required) set of control bits are supported. */ | |
3874 | if (ctl_min & ~ctl) | |
002c7f7c | 3875 | return -EIO; |
1c3d14fe YS |
3876 | |
3877 | *result = ctl; | |
3878 | return 0; | |
3879 | } | |
3880 | ||
110312c8 AK |
3881 | static __init bool allow_1_setting(u32 msr, u32 ctl) |
3882 | { | |
3883 | u32 vmx_msr_low, vmx_msr_high; | |
3884 | ||
3885 | rdmsr(msr, vmx_msr_low, vmx_msr_high); | |
3886 | return vmx_msr_high & ctl; | |
3887 | } | |
3888 | ||
002c7f7c | 3889 | static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf) |
6aa8b732 AK |
3890 | { |
3891 | u32 vmx_msr_low, vmx_msr_high; | |
d56f546d | 3892 | u32 min, opt, min2, opt2; |
1c3d14fe YS |
3893 | u32 _pin_based_exec_control = 0; |
3894 | u32 _cpu_based_exec_control = 0; | |
f78e0e2e | 3895 | u32 _cpu_based_2nd_exec_control = 0; |
1c3d14fe YS |
3896 | u32 _vmexit_control = 0; |
3897 | u32 _vmentry_control = 0; | |
3898 | ||
10166744 | 3899 | min = CPU_BASED_HLT_EXITING | |
1c3d14fe YS |
3900 | #ifdef CONFIG_X86_64 |
3901 | CPU_BASED_CR8_LOAD_EXITING | | |
3902 | CPU_BASED_CR8_STORE_EXITING | | |
3903 | #endif | |
d56f546d SY |
3904 | CPU_BASED_CR3_LOAD_EXITING | |
3905 | CPU_BASED_CR3_STORE_EXITING | | |
1c3d14fe YS |
3906 | CPU_BASED_USE_IO_BITMAPS | |
3907 | CPU_BASED_MOV_DR_EXITING | | |
a7052897 | 3908 | CPU_BASED_USE_TSC_OFFSETING | |
fee84b07 AK |
3909 | CPU_BASED_INVLPG_EXITING | |
3910 | CPU_BASED_RDPMC_EXITING; | |
443381a8 | 3911 | |
668fffa3 MT |
3912 | if (!kvm_mwait_in_guest()) |
3913 | min |= CPU_BASED_MWAIT_EXITING | | |
3914 | CPU_BASED_MONITOR_EXITING; | |
3915 | ||
f78e0e2e | 3916 | opt = CPU_BASED_TPR_SHADOW | |
25c5f225 | 3917 | CPU_BASED_USE_MSR_BITMAPS | |
f78e0e2e | 3918 | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS; |
1c3d14fe YS |
3919 | if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS, |
3920 | &_cpu_based_exec_control) < 0) | |
002c7f7c | 3921 | return -EIO; |
6e5d865c YS |
3922 | #ifdef CONFIG_X86_64 |
3923 | if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW)) | |
3924 | _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING & | |
3925 | ~CPU_BASED_CR8_STORE_EXITING; | |
3926 | #endif | |
f78e0e2e | 3927 | if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) { |
d56f546d SY |
3928 | min2 = 0; |
3929 | opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | | |
8d14695f | 3930 | SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | |
2384d2b3 | 3931 | SECONDARY_EXEC_WBINVD_EXITING | |
d56f546d | 3932 | SECONDARY_EXEC_ENABLE_VPID | |
3a624e29 | 3933 | SECONDARY_EXEC_ENABLE_EPT | |
4b8d54f9 | 3934 | SECONDARY_EXEC_UNRESTRICTED_GUEST | |
4e47c7a6 | 3935 | SECONDARY_EXEC_PAUSE_LOOP_EXITING | |
ad756a16 | 3936 | SECONDARY_EXEC_RDTSCP | |
83d4c286 | 3937 | SECONDARY_EXEC_ENABLE_INVPCID | |
c7c9c56c | 3938 | SECONDARY_EXEC_APIC_REGISTER_VIRT | |
abc4fc58 | 3939 | SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | |
20300099 | 3940 | SECONDARY_EXEC_SHADOW_VMCS | |
843e4330 | 3941 | SECONDARY_EXEC_XSAVES | |
736fdf72 DH |
3942 | SECONDARY_EXEC_RDSEED_EXITING | |
3943 | SECONDARY_EXEC_RDRAND_EXITING | | |
8b3e34e4 | 3944 | SECONDARY_EXEC_ENABLE_PML | |
2a499e49 BD |
3945 | SECONDARY_EXEC_TSC_SCALING | |
3946 | SECONDARY_EXEC_ENABLE_VMFUNC; | |
d56f546d SY |
3947 | if (adjust_vmx_controls(min2, opt2, |
3948 | MSR_IA32_VMX_PROCBASED_CTLS2, | |
f78e0e2e SY |
3949 | &_cpu_based_2nd_exec_control) < 0) |
3950 | return -EIO; | |
3951 | } | |
3952 | #ifndef CONFIG_X86_64 | |
3953 | if (!(_cpu_based_2nd_exec_control & | |
3954 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) | |
3955 | _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW; | |
3956 | #endif | |
83d4c286 YZ |
3957 | |
3958 | if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW)) | |
3959 | _cpu_based_2nd_exec_control &= ~( | |
8d14695f | 3960 | SECONDARY_EXEC_APIC_REGISTER_VIRT | |
c7c9c56c YZ |
3961 | SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | |
3962 | SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); | |
83d4c286 | 3963 | |
61f1dd90 WL |
3964 | rdmsr_safe(MSR_IA32_VMX_EPT_VPID_CAP, |
3965 | &vmx_capability.ept, &vmx_capability.vpid); | |
3966 | ||
d56f546d | 3967 | if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) { |
a7052897 MT |
3968 | /* CR3 accesses and invlpg don't need to cause VM Exits when EPT |
3969 | enabled */ | |
5fff7d27 GN |
3970 | _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING | |
3971 | CPU_BASED_CR3_STORE_EXITING | | |
3972 | CPU_BASED_INVLPG_EXITING); | |
61f1dd90 WL |
3973 | } else if (vmx_capability.ept) { |
3974 | vmx_capability.ept = 0; | |
3975 | pr_warn_once("EPT CAP should not exist if not support " | |
3976 | "1-setting enable EPT VM-execution control\n"); | |
3977 | } | |
3978 | if (!(_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_VPID) && | |
3979 | vmx_capability.vpid) { | |
3980 | vmx_capability.vpid = 0; | |
3981 | pr_warn_once("VPID CAP should not exist if not support " | |
3982 | "1-setting enable VPID VM-execution control\n"); | |
d56f546d | 3983 | } |
1c3d14fe | 3984 | |
91fa0f8e | 3985 | min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT; |
1c3d14fe YS |
3986 | #ifdef CONFIG_X86_64 |
3987 | min |= VM_EXIT_HOST_ADDR_SPACE_SIZE; | |
3988 | #endif | |
a547c6db | 3989 | opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT | |
91fa0f8e | 3990 | VM_EXIT_CLEAR_BNDCFGS; |
1c3d14fe YS |
3991 | if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS, |
3992 | &_vmexit_control) < 0) | |
002c7f7c | 3993 | return -EIO; |
1c3d14fe | 3994 | |
8a1b4392 PB |
3995 | min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING; |
3996 | opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR | | |
3997 | PIN_BASED_VMX_PREEMPTION_TIMER; | |
01e439be YZ |
3998 | if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS, |
3999 | &_pin_based_exec_control) < 0) | |
4000 | return -EIO; | |
4001 | ||
1c17c3e6 PB |
4002 | if (cpu_has_broken_vmx_preemption_timer()) |
4003 | _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER; | |
01e439be | 4004 | if (!(_cpu_based_2nd_exec_control & |
91fa0f8e | 4005 | SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)) |
01e439be YZ |
4006 | _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR; |
4007 | ||
c845f9c6 | 4008 | min = VM_ENTRY_LOAD_DEBUG_CONTROLS; |
da8999d3 | 4009 | opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS; |
1c3d14fe YS |
4010 | if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS, |
4011 | &_vmentry_control) < 0) | |
002c7f7c | 4012 | return -EIO; |
6aa8b732 | 4013 | |
c68876fd | 4014 | rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high); |
1c3d14fe YS |
4015 | |
4016 | /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */ | |
4017 | if ((vmx_msr_high & 0x1fff) > PAGE_SIZE) | |
002c7f7c | 4018 | return -EIO; |
1c3d14fe YS |
4019 | |
4020 | #ifdef CONFIG_X86_64 | |
4021 | /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */ | |
4022 | if (vmx_msr_high & (1u<<16)) | |
002c7f7c | 4023 | return -EIO; |
1c3d14fe YS |
4024 | #endif |
4025 | ||
4026 | /* Require Write-Back (WB) memory type for VMCS accesses. */ | |
4027 | if (((vmx_msr_high >> 18) & 15) != 6) | |
002c7f7c | 4028 | return -EIO; |
1c3d14fe | 4029 | |
002c7f7c | 4030 | vmcs_conf->size = vmx_msr_high & 0x1fff; |
16cb0255 | 4031 | vmcs_conf->order = get_order(vmcs_conf->size); |
9ac7e3e8 | 4032 | vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff; |
002c7f7c | 4033 | vmcs_conf->revision_id = vmx_msr_low; |
1c3d14fe | 4034 | |
002c7f7c YS |
4035 | vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control; |
4036 | vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control; | |
f78e0e2e | 4037 | vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control; |
002c7f7c YS |
4038 | vmcs_conf->vmexit_ctrl = _vmexit_control; |
4039 | vmcs_conf->vmentry_ctrl = _vmentry_control; | |
1c3d14fe | 4040 | |
110312c8 AK |
4041 | cpu_has_load_ia32_efer = |
4042 | allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS, | |
4043 | VM_ENTRY_LOAD_IA32_EFER) | |
4044 | && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS, | |
4045 | VM_EXIT_LOAD_IA32_EFER); | |
4046 | ||
8bf00a52 GN |
4047 | cpu_has_load_perf_global_ctrl = |
4048 | allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS, | |
4049 | VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL) | |
4050 | && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS, | |
4051 | VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL); | |
4052 | ||
4053 | /* | |
4054 | * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL | |
bb3541f1 | 4055 | * but due to errata below it can't be used. Workaround is to use |
8bf00a52 GN |
4056 | * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL. |
4057 | * | |
4058 | * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32] | |
4059 | * | |
4060 | * AAK155 (model 26) | |
4061 | * AAP115 (model 30) | |
4062 | * AAT100 (model 37) | |
4063 | * BC86,AAY89,BD102 (model 44) | |
4064 | * BA97 (model 46) | |
4065 | * | |
4066 | */ | |
4067 | if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) { | |
4068 | switch (boot_cpu_data.x86_model) { | |
4069 | case 26: | |
4070 | case 30: | |
4071 | case 37: | |
4072 | case 44: | |
4073 | case 46: | |
4074 | cpu_has_load_perf_global_ctrl = false; | |
4075 | printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL " | |
4076 | "does not work properly. Using workaround\n"); | |
4077 | break; | |
4078 | default: | |
4079 | break; | |
4080 | } | |
4081 | } | |
4082 | ||
782511b0 | 4083 | if (boot_cpu_has(X86_FEATURE_XSAVES)) |
20300099 WL |
4084 | rdmsrl(MSR_IA32_XSS, host_xss); |
4085 | ||
1c3d14fe | 4086 | return 0; |
c68876fd | 4087 | } |
6aa8b732 AK |
4088 | |
4089 | static struct vmcs *alloc_vmcs_cpu(int cpu) | |
4090 | { | |
4091 | int node = cpu_to_node(cpu); | |
4092 | struct page *pages; | |
4093 | struct vmcs *vmcs; | |
4094 | ||
96db800f | 4095 | pages = __alloc_pages_node(node, GFP_KERNEL, vmcs_config.order); |
6aa8b732 AK |
4096 | if (!pages) |
4097 | return NULL; | |
4098 | vmcs = page_address(pages); | |
1c3d14fe YS |
4099 | memset(vmcs, 0, vmcs_config.size); |
4100 | vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */ | |
6aa8b732 AK |
4101 | return vmcs; |
4102 | } | |
4103 | ||
6aa8b732 AK |
4104 | static void free_vmcs(struct vmcs *vmcs) |
4105 | { | |
1c3d14fe | 4106 | free_pages((unsigned long)vmcs, vmcs_config.order); |
6aa8b732 AK |
4107 | } |
4108 | ||
d462b819 NHE |
4109 | /* |
4110 | * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded | |
4111 | */ | |
4112 | static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs) | |
4113 | { | |
4114 | if (!loaded_vmcs->vmcs) | |
4115 | return; | |
4116 | loaded_vmcs_clear(loaded_vmcs); | |
4117 | free_vmcs(loaded_vmcs->vmcs); | |
4118 | loaded_vmcs->vmcs = NULL; | |
4b0be90f PB |
4119 | if (loaded_vmcs->msr_bitmap) |
4120 | free_page((unsigned long)loaded_vmcs->msr_bitmap); | |
355f4fb1 | 4121 | WARN_ON(loaded_vmcs->shadow_vmcs != NULL); |
d462b819 NHE |
4122 | } |
4123 | ||
b6d7026d PB |
4124 | static struct vmcs *alloc_vmcs(void) |
4125 | { | |
4126 | return alloc_vmcs_cpu(raw_smp_processor_id()); | |
4127 | } | |
4128 | ||
4129 | static int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs) | |
4130 | { | |
4131 | loaded_vmcs->vmcs = alloc_vmcs(); | |
4132 | if (!loaded_vmcs->vmcs) | |
4133 | return -ENOMEM; | |
4134 | ||
4135 | loaded_vmcs->shadow_vmcs = NULL; | |
4136 | loaded_vmcs_init(loaded_vmcs); | |
4b0be90f PB |
4137 | |
4138 | if (cpu_has_vmx_msr_bitmap()) { | |
4139 | loaded_vmcs->msr_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL); | |
4140 | if (!loaded_vmcs->msr_bitmap) | |
4141 | goto out_vmcs; | |
4142 | memset(loaded_vmcs->msr_bitmap, 0xff, PAGE_SIZE); | |
4143 | } | |
b6d7026d | 4144 | return 0; |
4b0be90f PB |
4145 | |
4146 | out_vmcs: | |
4147 | free_loaded_vmcs(loaded_vmcs); | |
4148 | return -ENOMEM; | |
b6d7026d PB |
4149 | } |
4150 | ||
39959588 | 4151 | static void free_kvm_area(void) |
6aa8b732 AK |
4152 | { |
4153 | int cpu; | |
4154 | ||
3230bb47 | 4155 | for_each_possible_cpu(cpu) { |
6aa8b732 | 4156 | free_vmcs(per_cpu(vmxarea, cpu)); |
3230bb47 ZA |
4157 | per_cpu(vmxarea, cpu) = NULL; |
4158 | } | |
6aa8b732 AK |
4159 | } |
4160 | ||
85fd514e JM |
4161 | enum vmcs_field_type { |
4162 | VMCS_FIELD_TYPE_U16 = 0, | |
4163 | VMCS_FIELD_TYPE_U64 = 1, | |
4164 | VMCS_FIELD_TYPE_U32 = 2, | |
4165 | VMCS_FIELD_TYPE_NATURAL_WIDTH = 3 | |
4166 | }; | |
4167 | ||
4168 | static inline int vmcs_field_type(unsigned long field) | |
4169 | { | |
4170 | if (0x1 & field) /* the *_HIGH fields are all 32 bit */ | |
4171 | return VMCS_FIELD_TYPE_U32; | |
4172 | return (field >> 13) & 0x3 ; | |
4173 | } | |
4174 | ||
4175 | static inline int vmcs_field_readonly(unsigned long field) | |
4176 | { | |
4177 | return (((field >> 10) & 0x3) == 1); | |
4178 | } | |
4179 | ||
fe2b201b BD |
4180 | static void init_vmcs_shadow_fields(void) |
4181 | { | |
4182 | int i, j; | |
4183 | ||
4184 | /* No checks for read only fields yet */ | |
4185 | ||
4186 | for (i = j = 0; i < max_shadow_read_write_fields; i++) { | |
4187 | switch (shadow_read_write_fields[i]) { | |
4188 | case GUEST_BNDCFGS: | |
a87036ad | 4189 | if (!kvm_mpx_supported()) |
fe2b201b BD |
4190 | continue; |
4191 | break; | |
4192 | default: | |
4193 | break; | |
4194 | } | |
4195 | ||
4196 | if (j < i) | |
4197 | shadow_read_write_fields[j] = | |
4198 | shadow_read_write_fields[i]; | |
4199 | j++; | |
4200 | } | |
4201 | max_shadow_read_write_fields = j; | |
4202 | ||
4203 | /* shadowed fields guest access without vmexit */ | |
4204 | for (i = 0; i < max_shadow_read_write_fields; i++) { | |
85fd514e JM |
4205 | unsigned long field = shadow_read_write_fields[i]; |
4206 | ||
4207 | clear_bit(field, vmx_vmwrite_bitmap); | |
4208 | clear_bit(field, vmx_vmread_bitmap); | |
4209 | if (vmcs_field_type(field) == VMCS_FIELD_TYPE_U64) { | |
4210 | clear_bit(field + 1, vmx_vmwrite_bitmap); | |
4211 | clear_bit(field + 1, vmx_vmread_bitmap); | |
4212 | } | |
4213 | } | |
4214 | for (i = 0; i < max_shadow_read_only_fields; i++) { | |
4215 | unsigned long field = shadow_read_only_fields[i]; | |
4216 | ||
4217 | clear_bit(field, vmx_vmread_bitmap); | |
4218 | if (vmcs_field_type(field) == VMCS_FIELD_TYPE_U64) | |
4219 | clear_bit(field + 1, vmx_vmread_bitmap); | |
fe2b201b | 4220 | } |
fe2b201b BD |
4221 | } |
4222 | ||
6aa8b732 AK |
4223 | static __init int alloc_kvm_area(void) |
4224 | { | |
4225 | int cpu; | |
4226 | ||
3230bb47 | 4227 | for_each_possible_cpu(cpu) { |
6aa8b732 AK |
4228 | struct vmcs *vmcs; |
4229 | ||
4230 | vmcs = alloc_vmcs_cpu(cpu); | |
4231 | if (!vmcs) { | |
4232 | free_kvm_area(); | |
4233 | return -ENOMEM; | |
4234 | } | |
4235 | ||
4236 | per_cpu(vmxarea, cpu) = vmcs; | |
4237 | } | |
4238 | return 0; | |
4239 | } | |
4240 | ||
91b0aa2c | 4241 | static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg, |
d99e4152 | 4242 | struct kvm_segment *save) |
6aa8b732 | 4243 | { |
d99e4152 GN |
4244 | if (!emulate_invalid_guest_state) { |
4245 | /* | |
4246 | * CS and SS RPL should be equal during guest entry according | |
4247 | * to VMX spec, but in reality it is not always so. Since vcpu | |
4248 | * is in the middle of the transition from real mode to | |
4249 | * protected mode it is safe to assume that RPL 0 is a good | |
4250 | * default value. | |
4251 | */ | |
4252 | if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS) | |
b32a9918 NA |
4253 | save->selector &= ~SEGMENT_RPL_MASK; |
4254 | save->dpl = save->selector & SEGMENT_RPL_MASK; | |
d99e4152 | 4255 | save->s = 1; |
6aa8b732 | 4256 | } |
d99e4152 | 4257 | vmx_set_segment(vcpu, save, seg); |
6aa8b732 AK |
4258 | } |
4259 | ||
4260 | static void enter_pmode(struct kvm_vcpu *vcpu) | |
4261 | { | |
4262 | unsigned long flags; | |
a89a8fb9 | 4263 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
6aa8b732 | 4264 | |
d99e4152 GN |
4265 | /* |
4266 | * Update real mode segment cache. It may be not up-to-date if sement | |
4267 | * register was written while vcpu was in a guest mode. | |
4268 | */ | |
4269 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES); | |
4270 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS); | |
4271 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS); | |
4272 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS); | |
4273 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS); | |
4274 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS); | |
4275 | ||
7ffd92c5 | 4276 | vmx->rmode.vm86_active = 0; |
6aa8b732 | 4277 | |
2fb92db1 AK |
4278 | vmx_segment_cache_clear(vmx); |
4279 | ||
f5f7b2fe | 4280 | vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR); |
6aa8b732 AK |
4281 | |
4282 | flags = vmcs_readl(GUEST_RFLAGS); | |
78ac8b47 AK |
4283 | flags &= RMODE_GUEST_OWNED_EFLAGS_BITS; |
4284 | flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS; | |
6aa8b732 AK |
4285 | vmcs_writel(GUEST_RFLAGS, flags); |
4286 | ||
66aee91a RR |
4287 | vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) | |
4288 | (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME)); | |
6aa8b732 AK |
4289 | |
4290 | update_exception_bitmap(vcpu); | |
4291 | ||
91b0aa2c GN |
4292 | fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]); |
4293 | fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]); | |
4294 | fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]); | |
4295 | fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]); | |
4296 | fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]); | |
4297 | fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]); | |
6aa8b732 AK |
4298 | } |
4299 | ||
f5f7b2fe | 4300 | static void fix_rmode_seg(int seg, struct kvm_segment *save) |
6aa8b732 | 4301 | { |
772e0318 | 4302 | const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; |
d99e4152 GN |
4303 | struct kvm_segment var = *save; |
4304 | ||
4305 | var.dpl = 0x3; | |
4306 | if (seg == VCPU_SREG_CS) | |
4307 | var.type = 0x3; | |
4308 | ||
4309 | if (!emulate_invalid_guest_state) { | |
4310 | var.selector = var.base >> 4; | |
4311 | var.base = var.base & 0xffff0; | |
4312 | var.limit = 0xffff; | |
4313 | var.g = 0; | |
4314 | var.db = 0; | |
4315 | var.present = 1; | |
4316 | var.s = 1; | |
4317 | var.l = 0; | |
4318 | var.unusable = 0; | |
4319 | var.type = 0x3; | |
4320 | var.avl = 0; | |
4321 | if (save->base & 0xf) | |
4322 | printk_once(KERN_WARNING "kvm: segment base is not " | |
4323 | "paragraph aligned when entering " | |
4324 | "protected mode (seg=%d)", seg); | |
4325 | } | |
6aa8b732 | 4326 | |
d99e4152 | 4327 | vmcs_write16(sf->selector, var.selector); |
96794e4e | 4328 | vmcs_writel(sf->base, var.base); |
d99e4152 GN |
4329 | vmcs_write32(sf->limit, var.limit); |
4330 | vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var)); | |
6aa8b732 AK |
4331 | } |
4332 | ||
4333 | static void enter_rmode(struct kvm_vcpu *vcpu) | |
4334 | { | |
4335 | unsigned long flags; | |
a89a8fb9 | 4336 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
6aa8b732 | 4337 | |
f5f7b2fe AK |
4338 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR); |
4339 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES); | |
4340 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS); | |
4341 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS); | |
4342 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS); | |
c6ad1153 GN |
4343 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS); |
4344 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS); | |
f5f7b2fe | 4345 | |
7ffd92c5 | 4346 | vmx->rmode.vm86_active = 1; |
6aa8b732 | 4347 | |
776e58ea GN |
4348 | /* |
4349 | * Very old userspace does not call KVM_SET_TSS_ADDR before entering | |
4918c6ca | 4350 | * vcpu. Warn the user that an update is overdue. |
776e58ea | 4351 | */ |
4918c6ca | 4352 | if (!vcpu->kvm->arch.tss_addr) |
776e58ea GN |
4353 | printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be " |
4354 | "called before entering vcpu\n"); | |
776e58ea | 4355 | |
2fb92db1 AK |
4356 | vmx_segment_cache_clear(vmx); |
4357 | ||
4918c6ca | 4358 | vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr); |
6aa8b732 | 4359 | vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1); |
6aa8b732 AK |
4360 | vmcs_write32(GUEST_TR_AR_BYTES, 0x008b); |
4361 | ||
4362 | flags = vmcs_readl(GUEST_RFLAGS); | |
78ac8b47 | 4363 | vmx->rmode.save_rflags = flags; |
6aa8b732 | 4364 | |
053de044 | 4365 | flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM; |
6aa8b732 AK |
4366 | |
4367 | vmcs_writel(GUEST_RFLAGS, flags); | |
66aee91a | 4368 | vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME); |
6aa8b732 AK |
4369 | update_exception_bitmap(vcpu); |
4370 | ||
d99e4152 GN |
4371 | fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]); |
4372 | fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]); | |
4373 | fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]); | |
4374 | fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]); | |
4375 | fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]); | |
4376 | fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]); | |
b246dd5d | 4377 | |
8668a3c4 | 4378 | kvm_mmu_reset_context(vcpu); |
6aa8b732 AK |
4379 | } |
4380 | ||
401d10de AS |
4381 | static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer) |
4382 | { | |
4383 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
26bb0981 AK |
4384 | struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER); |
4385 | ||
4386 | if (!msr) | |
4387 | return; | |
401d10de | 4388 | |
44ea2b17 AK |
4389 | /* |
4390 | * Force kernel_gs_base reloading before EFER changes, as control | |
4391 | * of this msr depends on is_long_mode(). | |
4392 | */ | |
4393 | vmx_load_host_state(to_vmx(vcpu)); | |
f6801dff | 4394 | vcpu->arch.efer = efer; |
401d10de | 4395 | if (efer & EFER_LMA) { |
2961e876 | 4396 | vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE); |
401d10de AS |
4397 | msr->data = efer; |
4398 | } else { | |
2961e876 | 4399 | vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE); |
401d10de AS |
4400 | |
4401 | msr->data = efer & ~EFER_LME; | |
4402 | } | |
4403 | setup_msrs(vmx); | |
4404 | } | |
4405 | ||
05b3e0c2 | 4406 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
4407 | |
4408 | static void enter_lmode(struct kvm_vcpu *vcpu) | |
4409 | { | |
4410 | u32 guest_tr_ar; | |
4411 | ||
2fb92db1 AK |
4412 | vmx_segment_cache_clear(to_vmx(vcpu)); |
4413 | ||
6aa8b732 | 4414 | guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES); |
4d283ec9 | 4415 | if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) { |
bd80158a JK |
4416 | pr_debug_ratelimited("%s: tss fixup for long mode. \n", |
4417 | __func__); | |
6aa8b732 | 4418 | vmcs_write32(GUEST_TR_AR_BYTES, |
4d283ec9 AL |
4419 | (guest_tr_ar & ~VMX_AR_TYPE_MASK) |
4420 | | VMX_AR_TYPE_BUSY_64_TSS); | |
6aa8b732 | 4421 | } |
da38f438 | 4422 | vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA); |
6aa8b732 AK |
4423 | } |
4424 | ||
4425 | static void exit_lmode(struct kvm_vcpu *vcpu) | |
4426 | { | |
2961e876 | 4427 | vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE); |
da38f438 | 4428 | vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA); |
6aa8b732 AK |
4429 | } |
4430 | ||
4431 | #endif | |
4432 | ||
6bf41e55 WL |
4433 | static inline void __vmx_flush_tlb(struct kvm_vcpu *vcpu, int vpid, |
4434 | bool invalidate_gpa) | |
2384d2b3 | 4435 | { |
6bf41e55 | 4436 | if (enable_ept && (invalidate_gpa || !enable_vpid)) { |
dd180b3e XG |
4437 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) |
4438 | return; | |
995f00a6 | 4439 | ept_sync_context(construct_eptp(vcpu, vcpu->arch.mmu.root_hpa)); |
f0b98c02 JM |
4440 | } else { |
4441 | vpid_sync_context(vpid); | |
dd180b3e | 4442 | } |
2384d2b3 SY |
4443 | } |
4444 | ||
6bf41e55 | 4445 | static void vmx_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa) |
dd5f5341 | 4446 | { |
6bf41e55 | 4447 | __vmx_flush_tlb(vcpu, to_vmx(vcpu)->vpid, invalidate_gpa); |
dd5f5341 WL |
4448 | } |
4449 | ||
e8467fda AK |
4450 | static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu) |
4451 | { | |
4452 | ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits; | |
4453 | ||
4454 | vcpu->arch.cr0 &= ~cr0_guest_owned_bits; | |
4455 | vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits; | |
4456 | } | |
4457 | ||
aff48baa AK |
4458 | static void vmx_decache_cr3(struct kvm_vcpu *vcpu) |
4459 | { | |
4460 | if (enable_ept && is_paging(vcpu)) | |
4461 | vcpu->arch.cr3 = vmcs_readl(GUEST_CR3); | |
4462 | __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail); | |
4463 | } | |
4464 | ||
25c4c276 | 4465 | static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu) |
399badf3 | 4466 | { |
fc78f519 AK |
4467 | ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits; |
4468 | ||
4469 | vcpu->arch.cr4 &= ~cr4_guest_owned_bits; | |
4470 | vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits; | |
399badf3 AK |
4471 | } |
4472 | ||
1439442c SY |
4473 | static void ept_load_pdptrs(struct kvm_vcpu *vcpu) |
4474 | { | |
d0d538b9 GN |
4475 | struct kvm_mmu *mmu = vcpu->arch.walk_mmu; |
4476 | ||
6de4f3ad AK |
4477 | if (!test_bit(VCPU_EXREG_PDPTR, |
4478 | (unsigned long *)&vcpu->arch.regs_dirty)) | |
4479 | return; | |
4480 | ||
f68adeae | 4481 | if (is_pae_paging(vcpu)) { |
d0d538b9 GN |
4482 | vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]); |
4483 | vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]); | |
4484 | vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]); | |
4485 | vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]); | |
1439442c SY |
4486 | } |
4487 | } | |
4488 | ||
8f5d549f AK |
4489 | static void ept_save_pdptrs(struct kvm_vcpu *vcpu) |
4490 | { | |
d0d538b9 GN |
4491 | struct kvm_mmu *mmu = vcpu->arch.walk_mmu; |
4492 | ||
f68adeae | 4493 | if (is_pae_paging(vcpu)) { |
d0d538b9 GN |
4494 | mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0); |
4495 | mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1); | |
4496 | mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2); | |
4497 | mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3); | |
8f5d549f | 4498 | } |
6de4f3ad AK |
4499 | |
4500 | __set_bit(VCPU_EXREG_PDPTR, | |
4501 | (unsigned long *)&vcpu->arch.regs_avail); | |
4502 | __set_bit(VCPU_EXREG_PDPTR, | |
4503 | (unsigned long *)&vcpu->arch.regs_dirty); | |
8f5d549f AK |
4504 | } |
4505 | ||
3899152c DM |
4506 | static bool nested_guest_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val) |
4507 | { | |
4508 | u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed0; | |
4509 | u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed1; | |
4510 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); | |
4511 | ||
4512 | if (to_vmx(vcpu)->nested.nested_vmx_secondary_ctls_high & | |
4513 | SECONDARY_EXEC_UNRESTRICTED_GUEST && | |
4514 | nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST)) | |
4515 | fixed0 &= ~(X86_CR0_PE | X86_CR0_PG); | |
4516 | ||
4517 | return fixed_bits_valid(val, fixed0, fixed1); | |
4518 | } | |
4519 | ||
4520 | static bool nested_host_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val) | |
4521 | { | |
4522 | u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed0; | |
4523 | u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed1; | |
4524 | ||
4525 | return fixed_bits_valid(val, fixed0, fixed1); | |
4526 | } | |
4527 | ||
4528 | static bool nested_cr4_valid(struct kvm_vcpu *vcpu, unsigned long val) | |
4529 | { | |
4530 | u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr4_fixed0; | |
4531 | u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr4_fixed1; | |
4532 | ||
4533 | return fixed_bits_valid(val, fixed0, fixed1); | |
4534 | } | |
4535 | ||
4536 | /* No difference in the restrictions on guest and host CR4 in VMX operation. */ | |
4537 | #define nested_guest_cr4_valid nested_cr4_valid | |
4538 | #define nested_host_cr4_valid nested_cr4_valid | |
4539 | ||
5e1746d6 | 4540 | static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4); |
1439442c SY |
4541 | |
4542 | static void ept_update_paging_mode_cr0(unsigned long *hw_cr0, | |
4543 | unsigned long cr0, | |
4544 | struct kvm_vcpu *vcpu) | |
4545 | { | |
5233dd51 MT |
4546 | if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail)) |
4547 | vmx_decache_cr3(vcpu); | |
1439442c SY |
4548 | if (!(cr0 & X86_CR0_PG)) { |
4549 | /* From paging/starting to nonpaging */ | |
4550 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, | |
65267ea1 | 4551 | vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) | |
1439442c SY |
4552 | (CPU_BASED_CR3_LOAD_EXITING | |
4553 | CPU_BASED_CR3_STORE_EXITING)); | |
4554 | vcpu->arch.cr0 = cr0; | |
fc78f519 | 4555 | vmx_set_cr4(vcpu, kvm_read_cr4(vcpu)); |
1439442c SY |
4556 | } else if (!is_paging(vcpu)) { |
4557 | /* From nonpaging to paging */ | |
4558 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, | |
65267ea1 | 4559 | vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) & |
1439442c SY |
4560 | ~(CPU_BASED_CR3_LOAD_EXITING | |
4561 | CPU_BASED_CR3_STORE_EXITING)); | |
4562 | vcpu->arch.cr0 = cr0; | |
fc78f519 | 4563 | vmx_set_cr4(vcpu, kvm_read_cr4(vcpu)); |
1439442c | 4564 | } |
95eb84a7 SY |
4565 | |
4566 | if (!(cr0 & X86_CR0_WP)) | |
4567 | *hw_cr0 &= ~X86_CR0_WP; | |
1439442c SY |
4568 | } |
4569 | ||
6aa8b732 AK |
4570 | static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) |
4571 | { | |
7ffd92c5 | 4572 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
3a624e29 NK |
4573 | unsigned long hw_cr0; |
4574 | ||
5037878e | 4575 | hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK); |
3a624e29 | 4576 | if (enable_unrestricted_guest) |
5037878e | 4577 | hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST; |
218e763f | 4578 | else { |
5037878e | 4579 | hw_cr0 |= KVM_VM_CR0_ALWAYS_ON; |
1439442c | 4580 | |
218e763f GN |
4581 | if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE)) |
4582 | enter_pmode(vcpu); | |
6aa8b732 | 4583 | |
218e763f GN |
4584 | if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE)) |
4585 | enter_rmode(vcpu); | |
4586 | } | |
6aa8b732 | 4587 | |
05b3e0c2 | 4588 | #ifdef CONFIG_X86_64 |
f6801dff | 4589 | if (vcpu->arch.efer & EFER_LME) { |
707d92fa | 4590 | if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) |
6aa8b732 | 4591 | enter_lmode(vcpu); |
707d92fa | 4592 | if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) |
6aa8b732 AK |
4593 | exit_lmode(vcpu); |
4594 | } | |
4595 | #endif | |
4596 | ||
089d034e | 4597 | if (enable_ept) |
1439442c SY |
4598 | ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu); |
4599 | ||
6aa8b732 | 4600 | vmcs_writel(CR0_READ_SHADOW, cr0); |
1439442c | 4601 | vmcs_writel(GUEST_CR0, hw_cr0); |
ad312c7c | 4602 | vcpu->arch.cr0 = cr0; |
14168786 GN |
4603 | |
4604 | /* depends on vcpu->arch.cr0 to be set to a new value */ | |
4605 | vmx->emulation_required = emulation_required(vcpu); | |
6aa8b732 AK |
4606 | } |
4607 | ||
855feb67 YZ |
4608 | static int get_ept_level(struct kvm_vcpu *vcpu) |
4609 | { | |
4610 | if (cpu_has_vmx_ept_5levels() && (cpuid_maxphyaddr(vcpu) > 48)) | |
4611 | return 5; | |
4612 | return 4; | |
4613 | } | |
4614 | ||
995f00a6 | 4615 | static u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa) |
1439442c | 4616 | { |
855feb67 YZ |
4617 | u64 eptp = VMX_EPTP_MT_WB; |
4618 | ||
4619 | eptp |= (get_ept_level(vcpu) == 5) ? VMX_EPTP_PWL_5 : VMX_EPTP_PWL_4; | |
1439442c | 4620 | |
995f00a6 PF |
4621 | if (enable_ept_ad_bits && |
4622 | (!is_guest_mode(vcpu) || nested_ept_ad_enabled(vcpu))) | |
bb97a016 | 4623 | eptp |= VMX_EPTP_AD_ENABLE_BIT; |
1439442c SY |
4624 | eptp |= (root_hpa & PAGE_MASK); |
4625 | ||
4626 | return eptp; | |
4627 | } | |
4628 | ||
6aa8b732 AK |
4629 | static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) |
4630 | { | |
1439442c SY |
4631 | unsigned long guest_cr3; |
4632 | u64 eptp; | |
4633 | ||
4634 | guest_cr3 = cr3; | |
089d034e | 4635 | if (enable_ept) { |
995f00a6 | 4636 | eptp = construct_eptp(vcpu, cr3); |
1439442c | 4637 | vmcs_write64(EPT_POINTER, eptp); |
59ab5a8f JK |
4638 | if (is_paging(vcpu) || is_guest_mode(vcpu)) |
4639 | guest_cr3 = kvm_read_cr3(vcpu); | |
4640 | else | |
4641 | guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr; | |
7c93be44 | 4642 | ept_load_pdptrs(vcpu); |
1439442c SY |
4643 | } |
4644 | ||
6bf41e55 | 4645 | vmx_flush_tlb(vcpu, true); |
1439442c | 4646 | vmcs_writel(GUEST_CR3, guest_cr3); |
6aa8b732 AK |
4647 | } |
4648 | ||
5e1746d6 | 4649 | static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) |
6aa8b732 | 4650 | { |
085e68ee BS |
4651 | /* |
4652 | * Pass through host's Machine Check Enable value to hw_cr4, which | |
4653 | * is in force while we are in guest mode. Do not let guests control | |
4654 | * this bit, even if host CR4.MCE == 0. | |
4655 | */ | |
4656 | unsigned long hw_cr4 = | |
4657 | (cr4_read_shadow() & X86_CR4_MCE) | | |
4658 | (cr4 & ~X86_CR4_MCE) | | |
4659 | (to_vmx(vcpu)->rmode.vm86_active ? | |
4660 | KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON); | |
1439442c | 4661 | |
5e1746d6 NHE |
4662 | if (cr4 & X86_CR4_VMXE) { |
4663 | /* | |
4664 | * To use VMXON (and later other VMX instructions), a guest | |
4665 | * must first be able to turn on cr4.VMXE (see handle_vmon()). | |
4666 | * So basically the check on whether to allow nested VMX | |
4667 | * is here. | |
4668 | */ | |
4669 | if (!nested_vmx_allowed(vcpu)) | |
4670 | return 1; | |
1a0d74e6 | 4671 | } |
3899152c DM |
4672 | |
4673 | if (to_vmx(vcpu)->nested.vmxon && !nested_cr4_valid(vcpu, cr4)) | |
5e1746d6 NHE |
4674 | return 1; |
4675 | ||
ad312c7c | 4676 | vcpu->arch.cr4 = cr4; |
bc23008b AK |
4677 | if (enable_ept) { |
4678 | if (!is_paging(vcpu)) { | |
4679 | hw_cr4 &= ~X86_CR4_PAE; | |
4680 | hw_cr4 |= X86_CR4_PSE; | |
4681 | } else if (!(cr4 & X86_CR4_PAE)) { | |
4682 | hw_cr4 &= ~X86_CR4_PAE; | |
4683 | } | |
4684 | } | |
1439442c | 4685 | |
656ec4a4 RK |
4686 | if (!enable_unrestricted_guest && !is_paging(vcpu)) |
4687 | /* | |
ddba2628 HH |
4688 | * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in |
4689 | * hardware. To emulate this behavior, SMEP/SMAP/PKU needs | |
4690 | * to be manually disabled when guest switches to non-paging | |
4691 | * mode. | |
4692 | * | |
4693 | * If !enable_unrestricted_guest, the CPU is always running | |
4694 | * with CR0.PG=1 and CR4 needs to be modified. | |
4695 | * If enable_unrestricted_guest, the CPU automatically | |
4696 | * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0. | |
656ec4a4 | 4697 | */ |
ddba2628 | 4698 | hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE); |
656ec4a4 | 4699 | |
1439442c SY |
4700 | vmcs_writel(CR4_READ_SHADOW, cr4); |
4701 | vmcs_writel(GUEST_CR4, hw_cr4); | |
5e1746d6 | 4702 | return 0; |
6aa8b732 AK |
4703 | } |
4704 | ||
6aa8b732 AK |
4705 | static void vmx_get_segment(struct kvm_vcpu *vcpu, |
4706 | struct kvm_segment *var, int seg) | |
4707 | { | |
a9179499 | 4708 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
6aa8b732 AK |
4709 | u32 ar; |
4710 | ||
c6ad1153 | 4711 | if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) { |
f5f7b2fe | 4712 | *var = vmx->rmode.segs[seg]; |
a9179499 | 4713 | if (seg == VCPU_SREG_TR |
2fb92db1 | 4714 | || var->selector == vmx_read_guest_seg_selector(vmx, seg)) |
f5f7b2fe | 4715 | return; |
1390a28b AK |
4716 | var->base = vmx_read_guest_seg_base(vmx, seg); |
4717 | var->selector = vmx_read_guest_seg_selector(vmx, seg); | |
4718 | return; | |
a9179499 | 4719 | } |
2fb92db1 AK |
4720 | var->base = vmx_read_guest_seg_base(vmx, seg); |
4721 | var->limit = vmx_read_guest_seg_limit(vmx, seg); | |
4722 | var->selector = vmx_read_guest_seg_selector(vmx, seg); | |
4723 | ar = vmx_read_guest_seg_ar(vmx, seg); | |
03617c18 | 4724 | var->unusable = (ar >> 16) & 1; |
6aa8b732 AK |
4725 | var->type = ar & 15; |
4726 | var->s = (ar >> 4) & 1; | |
4727 | var->dpl = (ar >> 5) & 3; | |
03617c18 GN |
4728 | /* |
4729 | * Some userspaces do not preserve unusable property. Since usable | |
4730 | * segment has to be present according to VMX spec we can use present | |
4731 | * property to amend userspace bug by making unusable segment always | |
4732 | * nonpresent. vmx_segment_access_rights() already marks nonpresent | |
4733 | * segment as unusable. | |
4734 | */ | |
4735 | var->present = !var->unusable; | |
6aa8b732 AK |
4736 | var->avl = (ar >> 12) & 1; |
4737 | var->l = (ar >> 13) & 1; | |
4738 | var->db = (ar >> 14) & 1; | |
4739 | var->g = (ar >> 15) & 1; | |
6aa8b732 AK |
4740 | } |
4741 | ||
a9179499 AK |
4742 | static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg) |
4743 | { | |
a9179499 AK |
4744 | struct kvm_segment s; |
4745 | ||
4746 | if (to_vmx(vcpu)->rmode.vm86_active) { | |
4747 | vmx_get_segment(vcpu, &s, seg); | |
4748 | return s.base; | |
4749 | } | |
2fb92db1 | 4750 | return vmx_read_guest_seg_base(to_vmx(vcpu), seg); |
a9179499 AK |
4751 | } |
4752 | ||
b09408d0 | 4753 | static int vmx_get_cpl(struct kvm_vcpu *vcpu) |
2e4d2653 | 4754 | { |
b09408d0 MT |
4755 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
4756 | ||
ae9fedc7 | 4757 | if (unlikely(vmx->rmode.vm86_active)) |
2e4d2653 | 4758 | return 0; |
ae9fedc7 PB |
4759 | else { |
4760 | int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS); | |
4d283ec9 | 4761 | return VMX_AR_DPL(ar); |
69c73028 | 4762 | } |
69c73028 AK |
4763 | } |
4764 | ||
653e3108 | 4765 | static u32 vmx_segment_access_rights(struct kvm_segment *var) |
6aa8b732 | 4766 | { |
6aa8b732 AK |
4767 | u32 ar; |
4768 | ||
f0495f9b | 4769 | if (var->unusable || !var->present) |
6aa8b732 AK |
4770 | ar = 1 << 16; |
4771 | else { | |
4772 | ar = var->type & 15; | |
4773 | ar |= (var->s & 1) << 4; | |
4774 | ar |= (var->dpl & 3) << 5; | |
4775 | ar |= (var->present & 1) << 7; | |
4776 | ar |= (var->avl & 1) << 12; | |
4777 | ar |= (var->l & 1) << 13; | |
4778 | ar |= (var->db & 1) << 14; | |
4779 | ar |= (var->g & 1) << 15; | |
4780 | } | |
653e3108 AK |
4781 | |
4782 | return ar; | |
4783 | } | |
4784 | ||
4785 | static void vmx_set_segment(struct kvm_vcpu *vcpu, | |
4786 | struct kvm_segment *var, int seg) | |
4787 | { | |
7ffd92c5 | 4788 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
772e0318 | 4789 | const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; |
653e3108 | 4790 | |
2fb92db1 AK |
4791 | vmx_segment_cache_clear(vmx); |
4792 | ||
1ecd50a9 GN |
4793 | if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) { |
4794 | vmx->rmode.segs[seg] = *var; | |
4795 | if (seg == VCPU_SREG_TR) | |
4796 | vmcs_write16(sf->selector, var->selector); | |
4797 | else if (var->s) | |
4798 | fix_rmode_seg(seg, &vmx->rmode.segs[seg]); | |
d99e4152 | 4799 | goto out; |
653e3108 | 4800 | } |
1ecd50a9 | 4801 | |
653e3108 AK |
4802 | vmcs_writel(sf->base, var->base); |
4803 | vmcs_write32(sf->limit, var->limit); | |
4804 | vmcs_write16(sf->selector, var->selector); | |
3a624e29 NK |
4805 | |
4806 | /* | |
4807 | * Fix the "Accessed" bit in AR field of segment registers for older | |
4808 | * qemu binaries. | |
4809 | * IA32 arch specifies that at the time of processor reset the | |
4810 | * "Accessed" bit in the AR field of segment registers is 1. And qemu | |
0fa06071 | 4811 | * is setting it to 0 in the userland code. This causes invalid guest |
3a624e29 NK |
4812 | * state vmexit when "unrestricted guest" mode is turned on. |
4813 | * Fix for this setup issue in cpu_reset is being pushed in the qemu | |
4814 | * tree. Newer qemu binaries with that qemu fix would not need this | |
4815 | * kvm hack. | |
4816 | */ | |
4817 | if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR)) | |
f924d66d | 4818 | var->type |= 0x1; /* Accessed */ |
3a624e29 | 4819 | |
f924d66d | 4820 | vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var)); |
d99e4152 GN |
4821 | |
4822 | out: | |
98eb2f8b | 4823 | vmx->emulation_required = emulation_required(vcpu); |
6aa8b732 AK |
4824 | } |
4825 | ||
6aa8b732 AK |
4826 | static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) |
4827 | { | |
2fb92db1 | 4828 | u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS); |
6aa8b732 AK |
4829 | |
4830 | *db = (ar >> 14) & 1; | |
4831 | *l = (ar >> 13) & 1; | |
4832 | } | |
4833 | ||
89a27f4d | 4834 | static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 4835 | { |
89a27f4d GN |
4836 | dt->size = vmcs_read32(GUEST_IDTR_LIMIT); |
4837 | dt->address = vmcs_readl(GUEST_IDTR_BASE); | |
6aa8b732 AK |
4838 | } |
4839 | ||
89a27f4d | 4840 | static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 4841 | { |
89a27f4d GN |
4842 | vmcs_write32(GUEST_IDTR_LIMIT, dt->size); |
4843 | vmcs_writel(GUEST_IDTR_BASE, dt->address); | |
6aa8b732 AK |
4844 | } |
4845 | ||
89a27f4d | 4846 | static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 4847 | { |
89a27f4d GN |
4848 | dt->size = vmcs_read32(GUEST_GDTR_LIMIT); |
4849 | dt->address = vmcs_readl(GUEST_GDTR_BASE); | |
6aa8b732 AK |
4850 | } |
4851 | ||
89a27f4d | 4852 | static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 4853 | { |
89a27f4d GN |
4854 | vmcs_write32(GUEST_GDTR_LIMIT, dt->size); |
4855 | vmcs_writel(GUEST_GDTR_BASE, dt->address); | |
6aa8b732 AK |
4856 | } |
4857 | ||
648dfaa7 MG |
4858 | static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg) |
4859 | { | |
4860 | struct kvm_segment var; | |
4861 | u32 ar; | |
4862 | ||
4863 | vmx_get_segment(vcpu, &var, seg); | |
07f42f5f | 4864 | var.dpl = 0x3; |
0647f4aa GN |
4865 | if (seg == VCPU_SREG_CS) |
4866 | var.type = 0x3; | |
648dfaa7 MG |
4867 | ar = vmx_segment_access_rights(&var); |
4868 | ||
4869 | if (var.base != (var.selector << 4)) | |
4870 | return false; | |
89efbed0 | 4871 | if (var.limit != 0xffff) |
648dfaa7 | 4872 | return false; |
07f42f5f | 4873 | if (ar != 0xf3) |
648dfaa7 MG |
4874 | return false; |
4875 | ||
4876 | return true; | |
4877 | } | |
4878 | ||
4879 | static bool code_segment_valid(struct kvm_vcpu *vcpu) | |
4880 | { | |
4881 | struct kvm_segment cs; | |
4882 | unsigned int cs_rpl; | |
4883 | ||
4884 | vmx_get_segment(vcpu, &cs, VCPU_SREG_CS); | |
b32a9918 | 4885 | cs_rpl = cs.selector & SEGMENT_RPL_MASK; |
648dfaa7 | 4886 | |
1872a3f4 AK |
4887 | if (cs.unusable) |
4888 | return false; | |
4d283ec9 | 4889 | if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK)) |
648dfaa7 MG |
4890 | return false; |
4891 | if (!cs.s) | |
4892 | return false; | |
4d283ec9 | 4893 | if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) { |
648dfaa7 MG |
4894 | if (cs.dpl > cs_rpl) |
4895 | return false; | |
1872a3f4 | 4896 | } else { |
648dfaa7 MG |
4897 | if (cs.dpl != cs_rpl) |
4898 | return false; | |
4899 | } | |
4900 | if (!cs.present) | |
4901 | return false; | |
4902 | ||
4903 | /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */ | |
4904 | return true; | |
4905 | } | |
4906 | ||
4907 | static bool stack_segment_valid(struct kvm_vcpu *vcpu) | |
4908 | { | |
4909 | struct kvm_segment ss; | |
4910 | unsigned int ss_rpl; | |
4911 | ||
4912 | vmx_get_segment(vcpu, &ss, VCPU_SREG_SS); | |
b32a9918 | 4913 | ss_rpl = ss.selector & SEGMENT_RPL_MASK; |
648dfaa7 | 4914 | |
1872a3f4 AK |
4915 | if (ss.unusable) |
4916 | return true; | |
4917 | if (ss.type != 3 && ss.type != 7) | |
648dfaa7 MG |
4918 | return false; |
4919 | if (!ss.s) | |
4920 | return false; | |
4921 | if (ss.dpl != ss_rpl) /* DPL != RPL */ | |
4922 | return false; | |
4923 | if (!ss.present) | |
4924 | return false; | |
4925 | ||
4926 | return true; | |
4927 | } | |
4928 | ||
4929 | static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg) | |
4930 | { | |
4931 | struct kvm_segment var; | |
4932 | unsigned int rpl; | |
4933 | ||
4934 | vmx_get_segment(vcpu, &var, seg); | |
b32a9918 | 4935 | rpl = var.selector & SEGMENT_RPL_MASK; |
648dfaa7 | 4936 | |
1872a3f4 AK |
4937 | if (var.unusable) |
4938 | return true; | |
648dfaa7 MG |
4939 | if (!var.s) |
4940 | return false; | |
4941 | if (!var.present) | |
4942 | return false; | |
4d283ec9 | 4943 | if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) { |
648dfaa7 MG |
4944 | if (var.dpl < rpl) /* DPL < RPL */ |
4945 | return false; | |
4946 | } | |
4947 | ||
4948 | /* TODO: Add other members to kvm_segment_field to allow checking for other access | |
4949 | * rights flags | |
4950 | */ | |
4951 | return true; | |
4952 | } | |
4953 | ||
4954 | static bool tr_valid(struct kvm_vcpu *vcpu) | |
4955 | { | |
4956 | struct kvm_segment tr; | |
4957 | ||
4958 | vmx_get_segment(vcpu, &tr, VCPU_SREG_TR); | |
4959 | ||
1872a3f4 AK |
4960 | if (tr.unusable) |
4961 | return false; | |
b32a9918 | 4962 | if (tr.selector & SEGMENT_TI_MASK) /* TI = 1 */ |
648dfaa7 | 4963 | return false; |
1872a3f4 | 4964 | if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */ |
648dfaa7 MG |
4965 | return false; |
4966 | if (!tr.present) | |
4967 | return false; | |
4968 | ||
4969 | return true; | |
4970 | } | |
4971 | ||
4972 | static bool ldtr_valid(struct kvm_vcpu *vcpu) | |
4973 | { | |
4974 | struct kvm_segment ldtr; | |
4975 | ||
4976 | vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR); | |
4977 | ||
1872a3f4 AK |
4978 | if (ldtr.unusable) |
4979 | return true; | |
b32a9918 | 4980 | if (ldtr.selector & SEGMENT_TI_MASK) /* TI = 1 */ |
648dfaa7 MG |
4981 | return false; |
4982 | if (ldtr.type != 2) | |
4983 | return false; | |
4984 | if (!ldtr.present) | |
4985 | return false; | |
4986 | ||
4987 | return true; | |
4988 | } | |
4989 | ||
4990 | static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu) | |
4991 | { | |
4992 | struct kvm_segment cs, ss; | |
4993 | ||
4994 | vmx_get_segment(vcpu, &cs, VCPU_SREG_CS); | |
4995 | vmx_get_segment(vcpu, &ss, VCPU_SREG_SS); | |
4996 | ||
b32a9918 NA |
4997 | return ((cs.selector & SEGMENT_RPL_MASK) == |
4998 | (ss.selector & SEGMENT_RPL_MASK)); | |
648dfaa7 MG |
4999 | } |
5000 | ||
e8c9d710 OU |
5001 | static bool nested_vmx_check_io_bitmaps(struct kvm_vcpu *vcpu, |
5002 | unsigned int port, int size); | |
5003 | static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu, | |
5004 | struct vmcs12 *vmcs12) | |
5005 | { | |
5006 | unsigned long exit_qualification; | |
6335e0e8 | 5007 | unsigned short port; |
e8c9d710 OU |
5008 | int size; |
5009 | ||
5010 | if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS)) | |
5011 | return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING); | |
5012 | ||
5013 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
5014 | ||
5015 | port = exit_qualification >> 16; | |
5016 | size = (exit_qualification & 7) + 1; | |
5017 | ||
5018 | return nested_vmx_check_io_bitmaps(vcpu, port, size); | |
5019 | } | |
5020 | ||
648dfaa7 MG |
5021 | /* |
5022 | * Check if guest state is valid. Returns true if valid, false if | |
5023 | * not. | |
5024 | * We assume that registers are always usable | |
5025 | */ | |
5026 | static bool guest_state_valid(struct kvm_vcpu *vcpu) | |
5027 | { | |
c5e97c80 GN |
5028 | if (enable_unrestricted_guest) |
5029 | return true; | |
5030 | ||
648dfaa7 | 5031 | /* real mode guest state checks */ |
f13882d8 | 5032 | if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) { |
648dfaa7 MG |
5033 | if (!rmode_segment_valid(vcpu, VCPU_SREG_CS)) |
5034 | return false; | |
5035 | if (!rmode_segment_valid(vcpu, VCPU_SREG_SS)) | |
5036 | return false; | |
5037 | if (!rmode_segment_valid(vcpu, VCPU_SREG_DS)) | |
5038 | return false; | |
5039 | if (!rmode_segment_valid(vcpu, VCPU_SREG_ES)) | |
5040 | return false; | |
5041 | if (!rmode_segment_valid(vcpu, VCPU_SREG_FS)) | |
5042 | return false; | |
5043 | if (!rmode_segment_valid(vcpu, VCPU_SREG_GS)) | |
5044 | return false; | |
5045 | } else { | |
5046 | /* protected mode guest state checks */ | |
5047 | if (!cs_ss_rpl_check(vcpu)) | |
5048 | return false; | |
5049 | if (!code_segment_valid(vcpu)) | |
5050 | return false; | |
5051 | if (!stack_segment_valid(vcpu)) | |
5052 | return false; | |
5053 | if (!data_segment_valid(vcpu, VCPU_SREG_DS)) | |
5054 | return false; | |
5055 | if (!data_segment_valid(vcpu, VCPU_SREG_ES)) | |
5056 | return false; | |
5057 | if (!data_segment_valid(vcpu, VCPU_SREG_FS)) | |
5058 | return false; | |
5059 | if (!data_segment_valid(vcpu, VCPU_SREG_GS)) | |
5060 | return false; | |
5061 | if (!tr_valid(vcpu)) | |
5062 | return false; | |
5063 | if (!ldtr_valid(vcpu)) | |
5064 | return false; | |
5065 | } | |
5066 | /* TODO: | |
5067 | * - Add checks on RIP | |
5068 | * - Add checks on RFLAGS | |
5069 | */ | |
5070 | ||
5071 | return true; | |
5072 | } | |
5073 | ||
5fa99cbe JM |
5074 | static bool page_address_valid(struct kvm_vcpu *vcpu, gpa_t gpa) |
5075 | { | |
5076 | return PAGE_ALIGNED(gpa) && !(gpa >> cpuid_maxphyaddr(vcpu)); | |
5077 | } | |
5078 | ||
d77c26fc | 5079 | static int init_rmode_tss(struct kvm *kvm) |
6aa8b732 | 5080 | { |
40dcaa9f | 5081 | gfn_t fn; |
195aefde | 5082 | u16 data = 0; |
1f755a82 | 5083 | int idx, r; |
6aa8b732 | 5084 | |
40dcaa9f | 5085 | idx = srcu_read_lock(&kvm->srcu); |
4918c6ca | 5086 | fn = kvm->arch.tss_addr >> PAGE_SHIFT; |
195aefde IE |
5087 | r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE); |
5088 | if (r < 0) | |
10589a46 | 5089 | goto out; |
195aefde | 5090 | data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE; |
464d17c8 SY |
5091 | r = kvm_write_guest_page(kvm, fn++, &data, |
5092 | TSS_IOPB_BASE_OFFSET, sizeof(u16)); | |
195aefde | 5093 | if (r < 0) |
10589a46 | 5094 | goto out; |
195aefde IE |
5095 | r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE); |
5096 | if (r < 0) | |
10589a46 | 5097 | goto out; |
195aefde IE |
5098 | r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE); |
5099 | if (r < 0) | |
10589a46 | 5100 | goto out; |
195aefde | 5101 | data = ~0; |
10589a46 MT |
5102 | r = kvm_write_guest_page(kvm, fn, &data, |
5103 | RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1, | |
5104 | sizeof(u8)); | |
10589a46 | 5105 | out: |
40dcaa9f | 5106 | srcu_read_unlock(&kvm->srcu, idx); |
1f755a82 | 5107 | return r; |
6aa8b732 AK |
5108 | } |
5109 | ||
b7ebfb05 SY |
5110 | static int init_rmode_identity_map(struct kvm *kvm) |
5111 | { | |
f51770ed | 5112 | int i, idx, r = 0; |
ba049e93 | 5113 | kvm_pfn_t identity_map_pfn; |
b7ebfb05 SY |
5114 | u32 tmp; |
5115 | ||
a255d479 TC |
5116 | /* Protect kvm->arch.ept_identity_pagetable_done. */ |
5117 | mutex_lock(&kvm->slots_lock); | |
5118 | ||
f51770ed | 5119 | if (likely(kvm->arch.ept_identity_pagetable_done)) |
a255d479 | 5120 | goto out2; |
a255d479 | 5121 | |
d8a6e365 DH |
5122 | if (!kvm->arch.ept_identity_map_addr) |
5123 | kvm->arch.ept_identity_map_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR; | |
b927a3ce | 5124 | identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT; |
a255d479 | 5125 | |
d8a6e365 DH |
5126 | r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, |
5127 | kvm->arch.ept_identity_map_addr, PAGE_SIZE); | |
f51770ed | 5128 | if (r < 0) |
a255d479 TC |
5129 | goto out2; |
5130 | ||
40dcaa9f | 5131 | idx = srcu_read_lock(&kvm->srcu); |
b7ebfb05 SY |
5132 | r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE); |
5133 | if (r < 0) | |
5134 | goto out; | |
5135 | /* Set up identity-mapping pagetable for EPT in real mode */ | |
5136 | for (i = 0; i < PT32_ENT_PER_PAGE; i++) { | |
5137 | tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER | | |
5138 | _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE); | |
5139 | r = kvm_write_guest_page(kvm, identity_map_pfn, | |
5140 | &tmp, i * sizeof(tmp), sizeof(tmp)); | |
5141 | if (r < 0) | |
5142 | goto out; | |
5143 | } | |
5144 | kvm->arch.ept_identity_pagetable_done = true; | |
f51770ed | 5145 | |
b7ebfb05 | 5146 | out: |
40dcaa9f | 5147 | srcu_read_unlock(&kvm->srcu, idx); |
a255d479 TC |
5148 | |
5149 | out2: | |
5150 | mutex_unlock(&kvm->slots_lock); | |
f51770ed | 5151 | return r; |
b7ebfb05 SY |
5152 | } |
5153 | ||
6aa8b732 AK |
5154 | static void seg_setup(int seg) |
5155 | { | |
772e0318 | 5156 | const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; |
3a624e29 | 5157 | unsigned int ar; |
6aa8b732 AK |
5158 | |
5159 | vmcs_write16(sf->selector, 0); | |
5160 | vmcs_writel(sf->base, 0); | |
5161 | vmcs_write32(sf->limit, 0xffff); | |
d54d07b2 GN |
5162 | ar = 0x93; |
5163 | if (seg == VCPU_SREG_CS) | |
5164 | ar |= 0x08; /* code segment */ | |
3a624e29 NK |
5165 | |
5166 | vmcs_write32(sf->ar_bytes, ar); | |
6aa8b732 AK |
5167 | } |
5168 | ||
f78e0e2e SY |
5169 | static int alloc_apic_access_page(struct kvm *kvm) |
5170 | { | |
4484141a | 5171 | struct page *page; |
f78e0e2e SY |
5172 | int r = 0; |
5173 | ||
79fac95e | 5174 | mutex_lock(&kvm->slots_lock); |
c24ae0dc | 5175 | if (kvm->arch.apic_access_page_done) |
f78e0e2e | 5176 | goto out; |
1d8007bd PB |
5177 | r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, |
5178 | APIC_DEFAULT_PHYS_BASE, PAGE_SIZE); | |
f78e0e2e SY |
5179 | if (r) |
5180 | goto out; | |
72dc67a6 | 5181 | |
73a6d941 | 5182 | page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT); |
4484141a XG |
5183 | if (is_error_page(page)) { |
5184 | r = -EFAULT; | |
5185 | goto out; | |
5186 | } | |
5187 | ||
c24ae0dc TC |
5188 | /* |
5189 | * Do not pin the page in memory, so that memory hot-unplug | |
5190 | * is able to migrate it. | |
5191 | */ | |
5192 | put_page(page); | |
5193 | kvm->arch.apic_access_page_done = true; | |
f78e0e2e | 5194 | out: |
79fac95e | 5195 | mutex_unlock(&kvm->slots_lock); |
f78e0e2e SY |
5196 | return r; |
5197 | } | |
5198 | ||
991e7a0e | 5199 | static int allocate_vpid(void) |
2384d2b3 SY |
5200 | { |
5201 | int vpid; | |
5202 | ||
919818ab | 5203 | if (!enable_vpid) |
991e7a0e | 5204 | return 0; |
2384d2b3 SY |
5205 | spin_lock(&vmx_vpid_lock); |
5206 | vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS); | |
991e7a0e | 5207 | if (vpid < VMX_NR_VPIDS) |
2384d2b3 | 5208 | __set_bit(vpid, vmx_vpid_bitmap); |
991e7a0e WL |
5209 | else |
5210 | vpid = 0; | |
2384d2b3 | 5211 | spin_unlock(&vmx_vpid_lock); |
991e7a0e | 5212 | return vpid; |
2384d2b3 SY |
5213 | } |
5214 | ||
991e7a0e | 5215 | static void free_vpid(int vpid) |
cdbecfc3 | 5216 | { |
991e7a0e | 5217 | if (!enable_vpid || vpid == 0) |
cdbecfc3 LJ |
5218 | return; |
5219 | spin_lock(&vmx_vpid_lock); | |
991e7a0e | 5220 | __clear_bit(vpid, vmx_vpid_bitmap); |
cdbecfc3 LJ |
5221 | spin_unlock(&vmx_vpid_lock); |
5222 | } | |
5223 | ||
3861351c | 5224 | static __always_inline void vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, |
4b0be90f | 5225 | u32 msr, int type) |
25c5f225 | 5226 | { |
3e7c73e9 | 5227 | int f = sizeof(unsigned long); |
25c5f225 SY |
5228 | |
5229 | if (!cpu_has_vmx_msr_bitmap()) | |
5230 | return; | |
5231 | ||
5232 | /* | |
5233 | * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals | |
5234 | * have the write-low and read-high bitmap offsets the wrong way round. | |
5235 | * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff. | |
5236 | */ | |
25c5f225 | 5237 | if (msr <= 0x1fff) { |
8d14695f YZ |
5238 | if (type & MSR_TYPE_R) |
5239 | /* read-low */ | |
5240 | __clear_bit(msr, msr_bitmap + 0x000 / f); | |
5241 | ||
5242 | if (type & MSR_TYPE_W) | |
5243 | /* write-low */ | |
5244 | __clear_bit(msr, msr_bitmap + 0x800 / f); | |
5245 | ||
25c5f225 SY |
5246 | } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) { |
5247 | msr &= 0x1fff; | |
8d14695f YZ |
5248 | if (type & MSR_TYPE_R) |
5249 | /* read-high */ | |
5250 | __clear_bit(msr, msr_bitmap + 0x400 / f); | |
5251 | ||
5252 | if (type & MSR_TYPE_W) | |
5253 | /* write-high */ | |
5254 | __clear_bit(msr, msr_bitmap + 0xc00 / f); | |
5255 | ||
5256 | } | |
5257 | } | |
5258 | ||
3861351c | 5259 | static __always_inline void vmx_enable_intercept_for_msr(unsigned long *msr_bitmap, |
4b0be90f PB |
5260 | u32 msr, int type) |
5261 | { | |
5262 | int f = sizeof(unsigned long); | |
5263 | ||
5264 | if (!cpu_has_vmx_msr_bitmap()) | |
5265 | return; | |
5266 | ||
5267 | /* | |
5268 | * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals | |
5269 | * have the write-low and read-high bitmap offsets the wrong way round. | |
5270 | * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff. | |
5271 | */ | |
5272 | if (msr <= 0x1fff) { | |
5273 | if (type & MSR_TYPE_R) | |
5274 | /* read-low */ | |
5275 | __set_bit(msr, msr_bitmap + 0x000 / f); | |
5276 | ||
5277 | if (type & MSR_TYPE_W) | |
5278 | /* write-low */ | |
5279 | __set_bit(msr, msr_bitmap + 0x800 / f); | |
5280 | ||
5281 | } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) { | |
5282 | msr &= 0x1fff; | |
5283 | if (type & MSR_TYPE_R) | |
5284 | /* read-high */ | |
5285 | __set_bit(msr, msr_bitmap + 0x400 / f); | |
5286 | ||
5287 | if (type & MSR_TYPE_W) | |
5288 | /* write-high */ | |
5289 | __set_bit(msr, msr_bitmap + 0xc00 / f); | |
5290 | ||
5291 | } | |
5292 | } | |
5293 | ||
3861351c | 5294 | static __always_inline void vmx_set_intercept_for_msr(unsigned long *msr_bitmap, |
4b0be90f PB |
5295 | u32 msr, int type, bool value) |
5296 | { | |
5297 | if (value) | |
5298 | vmx_enable_intercept_for_msr(msr_bitmap, msr, type); | |
5299 | else | |
5300 | vmx_disable_intercept_for_msr(msr_bitmap, msr, type); | |
5301 | } | |
5302 | ||
f2b93280 WV |
5303 | /* |
5304 | * If a msr is allowed by L0, we should check whether it is allowed by L1. | |
5305 | * The corresponding bit will be cleared unless both of L0 and L1 allow it. | |
5306 | */ | |
5307 | static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1, | |
5308 | unsigned long *msr_bitmap_nested, | |
5309 | u32 msr, int type) | |
5310 | { | |
5311 | int f = sizeof(unsigned long); | |
5312 | ||
5313 | if (!cpu_has_vmx_msr_bitmap()) { | |
5314 | WARN_ON(1); | |
5315 | return; | |
5316 | } | |
5317 | ||
5318 | /* | |
5319 | * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals | |
5320 | * have the write-low and read-high bitmap offsets the wrong way round. | |
5321 | * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff. | |
5322 | */ | |
5323 | if (msr <= 0x1fff) { | |
5324 | if (type & MSR_TYPE_R && | |
5325 | !test_bit(msr, msr_bitmap_l1 + 0x000 / f)) | |
5326 | /* read-low */ | |
5327 | __clear_bit(msr, msr_bitmap_nested + 0x000 / f); | |
5328 | ||
5329 | if (type & MSR_TYPE_W && | |
5330 | !test_bit(msr, msr_bitmap_l1 + 0x800 / f)) | |
5331 | /* write-low */ | |
5332 | __clear_bit(msr, msr_bitmap_nested + 0x800 / f); | |
5333 | ||
5334 | } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) { | |
5335 | msr &= 0x1fff; | |
5336 | if (type & MSR_TYPE_R && | |
5337 | !test_bit(msr, msr_bitmap_l1 + 0x400 / f)) | |
5338 | /* read-high */ | |
5339 | __clear_bit(msr, msr_bitmap_nested + 0x400 / f); | |
5340 | ||
5341 | if (type & MSR_TYPE_W && | |
5342 | !test_bit(msr, msr_bitmap_l1 + 0xc00 / f)) | |
5343 | /* write-high */ | |
5344 | __clear_bit(msr, msr_bitmap_nested + 0xc00 / f); | |
5345 | ||
5346 | } | |
5347 | } | |
5348 | ||
4b0be90f | 5349 | static u8 vmx_msr_bitmap_mode(struct kvm_vcpu *vcpu) |
5897297b | 5350 | { |
4b0be90f PB |
5351 | u8 mode = 0; |
5352 | ||
5353 | if (cpu_has_secondary_exec_ctrls() && | |
5354 | (vmcs_read32(SECONDARY_VM_EXEC_CONTROL) & | |
5355 | SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) { | |
5356 | mode |= MSR_BITMAP_MODE_X2APIC; | |
5357 | if (enable_apicv && kvm_vcpu_apicv_active(vcpu)) | |
5358 | mode |= MSR_BITMAP_MODE_X2APIC_APICV; | |
5359 | } | |
5360 | ||
5361 | if (is_long_mode(vcpu)) | |
5362 | mode |= MSR_BITMAP_MODE_LM; | |
5363 | ||
5364 | return mode; | |
8d14695f YZ |
5365 | } |
5366 | ||
4b0be90f PB |
5367 | #define X2APIC_MSR(r) (APIC_BASE_MSR + ((r) >> 4)) |
5368 | ||
5369 | static void vmx_update_msr_bitmap_x2apic(unsigned long *msr_bitmap, | |
5370 | u8 mode) | |
8d14695f | 5371 | { |
4b0be90f PB |
5372 | int msr; |
5373 | ||
5374 | for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) { | |
5375 | unsigned word = msr / BITS_PER_LONG; | |
5376 | msr_bitmap[word] = (mode & MSR_BITMAP_MODE_X2APIC_APICV) ? 0 : ~0; | |
5377 | msr_bitmap[word + (0x800 / sizeof(long))] = ~0; | |
5378 | } | |
5379 | ||
5380 | if (mode & MSR_BITMAP_MODE_X2APIC) { | |
5381 | /* | |
5382 | * TPR reads and writes can be virtualized even if virtual interrupt | |
5383 | * delivery is not in use. | |
5384 | */ | |
5385 | vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TASKPRI), MSR_TYPE_RW); | |
5386 | if (mode & MSR_BITMAP_MODE_X2APIC_APICV) { | |
5387 | vmx_enable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TMCCT), MSR_TYPE_R); | |
5388 | vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_EOI), MSR_TYPE_W); | |
5389 | vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_SELF_IPI), MSR_TYPE_W); | |
5390 | } | |
f6e90f9e | 5391 | } |
5897297b AK |
5392 | } |
5393 | ||
4b0be90f PB |
5394 | static void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu) |
5395 | { | |
5396 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
5397 | unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap; | |
5398 | u8 mode = vmx_msr_bitmap_mode(vcpu); | |
5399 | u8 changed = mode ^ vmx->msr_bitmap_mode; | |
5400 | ||
5401 | if (!changed) | |
5402 | return; | |
5403 | ||
5404 | vmx_set_intercept_for_msr(msr_bitmap, MSR_KERNEL_GS_BASE, MSR_TYPE_RW, | |
5405 | !(mode & MSR_BITMAP_MODE_LM)); | |
5406 | ||
5407 | if (changed & (MSR_BITMAP_MODE_X2APIC | MSR_BITMAP_MODE_X2APIC_APICV)) | |
5408 | vmx_update_msr_bitmap_x2apic(msr_bitmap, mode); | |
5409 | ||
5410 | vmx->msr_bitmap_mode = mode; | |
5411 | } | |
5412 | ||
b2a05fef | 5413 | static bool vmx_get_enable_apicv(struct kvm_vcpu *vcpu) |
d50ab6c1 | 5414 | { |
d62caabb | 5415 | return enable_apicv; |
d50ab6c1 PB |
5416 | } |
5417 | ||
c9f04407 DM |
5418 | static void nested_mark_vmcs12_pages_dirty(struct kvm_vcpu *vcpu) |
5419 | { | |
5420 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); | |
5421 | gfn_t gfn; | |
5422 | ||
5423 | /* | |
5424 | * Don't need to mark the APIC access page dirty; it is never | |
5425 | * written to by the CPU during APIC virtualization. | |
5426 | */ | |
5427 | ||
5428 | if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) { | |
5429 | gfn = vmcs12->virtual_apic_page_addr >> PAGE_SHIFT; | |
5430 | kvm_vcpu_mark_page_dirty(vcpu, gfn); | |
5431 | } | |
5432 | ||
5433 | if (nested_cpu_has_posted_intr(vmcs12)) { | |
5434 | gfn = vmcs12->posted_intr_desc_addr >> PAGE_SHIFT; | |
5435 | kvm_vcpu_mark_page_dirty(vcpu, gfn); | |
5436 | } | |
5437 | } | |
5438 | ||
5439 | ||
6342c50a | 5440 | static void vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu) |
705699a1 WV |
5441 | { |
5442 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
5443 | int max_irr; | |
5444 | void *vapic_page; | |
5445 | u16 status; | |
5446 | ||
c9f04407 DM |
5447 | if (!vmx->nested.pi_desc || !vmx->nested.pi_pending) |
5448 | return; | |
705699a1 | 5449 | |
c9f04407 DM |
5450 | vmx->nested.pi_pending = false; |
5451 | if (!pi_test_and_clear_on(vmx->nested.pi_desc)) | |
5452 | return; | |
705699a1 | 5453 | |
c9f04407 DM |
5454 | max_irr = find_last_bit((unsigned long *)vmx->nested.pi_desc->pir, 256); |
5455 | if (max_irr != 256) { | |
705699a1 | 5456 | vapic_page = kmap(vmx->nested.virtual_apic_page); |
705699a1 WV |
5457 | __kvm_apic_update_irr(vmx->nested.pi_desc->pir, vapic_page); |
5458 | kunmap(vmx->nested.virtual_apic_page); | |
5459 | ||
5460 | status = vmcs_read16(GUEST_INTR_STATUS); | |
5461 | if ((u8)max_irr > ((u8)status & 0xff)) { | |
5462 | status &= ~0xff; | |
5463 | status |= (u8)max_irr; | |
5464 | vmcs_write16(GUEST_INTR_STATUS, status); | |
5465 | } | |
5466 | } | |
c9f04407 DM |
5467 | |
5468 | nested_mark_vmcs12_pages_dirty(vcpu); | |
705699a1 WV |
5469 | } |
5470 | ||
06a5524f WV |
5471 | static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu, |
5472 | bool nested) | |
21bc8dc5 RK |
5473 | { |
5474 | #ifdef CONFIG_SMP | |
06a5524f WV |
5475 | int pi_vec = nested ? POSTED_INTR_NESTED_VECTOR : POSTED_INTR_VECTOR; |
5476 | ||
21bc8dc5 | 5477 | if (vcpu->mode == IN_GUEST_MODE) { |
28b835d6 | 5478 | /* |
5753743f HZ |
5479 | * The vector of interrupt to be delivered to vcpu had |
5480 | * been set in PIR before this function. | |
5481 | * | |
5482 | * Following cases will be reached in this block, and | |
5483 | * we always send a notification event in all cases as | |
5484 | * explained below. | |
5485 | * | |
5486 | * Case 1: vcpu keeps in non-root mode. Sending a | |
5487 | * notification event posts the interrupt to vcpu. | |
5488 | * | |
5489 | * Case 2: vcpu exits to root mode and is still | |
5490 | * runnable. PIR will be synced to vIRR before the | |
5491 | * next vcpu entry. Sending a notification event in | |
5492 | * this case has no effect, as vcpu is not in root | |
5493 | * mode. | |
28b835d6 | 5494 | * |
5753743f HZ |
5495 | * Case 3: vcpu exits to root mode and is blocked. |
5496 | * vcpu_block() has already synced PIR to vIRR and | |
5497 | * never blocks vcpu if vIRR is not cleared. Therefore, | |
5498 | * a blocked vcpu here does not wait for any requested | |
5499 | * interrupts in PIR, and sending a notification event | |
5500 | * which has no effect is safe here. | |
28b835d6 | 5501 | */ |
28b835d6 | 5502 | |
06a5524f | 5503 | apic->send_IPI_mask(get_cpu_mask(vcpu->cpu), pi_vec); |
21bc8dc5 RK |
5504 | return true; |
5505 | } | |
5506 | #endif | |
5507 | return false; | |
5508 | } | |
5509 | ||
705699a1 WV |
5510 | static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu, |
5511 | int vector) | |
5512 | { | |
5513 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
5514 | ||
5515 | if (is_guest_mode(vcpu) && | |
5516 | vector == vmx->nested.posted_intr_nv) { | |
705699a1 WV |
5517 | /* |
5518 | * If a posted intr is not recognized by hardware, | |
5519 | * we will accomplish it in the next vmentry. | |
5520 | */ | |
5521 | vmx->nested.pi_pending = true; | |
5522 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
7b616667 LA |
5523 | /* the PIR and ON have been set by L1. */ |
5524 | if (!kvm_vcpu_trigger_posted_interrupt(vcpu, true)) | |
5525 | kvm_vcpu_kick(vcpu); | |
705699a1 WV |
5526 | return 0; |
5527 | } | |
5528 | return -1; | |
5529 | } | |
a20ed54d YZ |
5530 | /* |
5531 | * Send interrupt to vcpu via posted interrupt way. | |
5532 | * 1. If target vcpu is running(non-root mode), send posted interrupt | |
5533 | * notification to vcpu and hardware will sync PIR to vIRR atomically. | |
5534 | * 2. If target vcpu isn't running(root mode), kick it to pick up the | |
5535 | * interrupt from PIR in next vmentry. | |
5536 | */ | |
5537 | static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector) | |
5538 | { | |
5539 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
5540 | int r; | |
5541 | ||
705699a1 WV |
5542 | r = vmx_deliver_nested_posted_interrupt(vcpu, vector); |
5543 | if (!r) | |
5544 | return; | |
5545 | ||
a20ed54d YZ |
5546 | if (pi_test_and_set_pir(vector, &vmx->pi_desc)) |
5547 | return; | |
5548 | ||
b95234c8 PB |
5549 | /* If a previous notification has sent the IPI, nothing to do. */ |
5550 | if (pi_test_and_set_on(&vmx->pi_desc)) | |
5551 | return; | |
5552 | ||
06a5524f | 5553 | if (!kvm_vcpu_trigger_posted_interrupt(vcpu, false)) |
a20ed54d YZ |
5554 | kvm_vcpu_kick(vcpu); |
5555 | } | |
5556 | ||
a3a8ff8e NHE |
5557 | /* |
5558 | * Set up the vmcs's constant host-state fields, i.e., host-state fields that | |
5559 | * will not change in the lifetime of the guest. | |
5560 | * Note that host-state that does change is set elsewhere. E.g., host-state | |
5561 | * that is set differently for each CPU is set in vmx_vcpu_load(), not here. | |
5562 | */ | |
a547c6db | 5563 | static void vmx_set_constant_host_state(struct vcpu_vmx *vmx) |
a3a8ff8e NHE |
5564 | { |
5565 | u32 low32, high32; | |
5566 | unsigned long tmpl; | |
5567 | struct desc_ptr dt; | |
d6e41f11 | 5568 | unsigned long cr0, cr3, cr4; |
a3a8ff8e | 5569 | |
04ac88ab AL |
5570 | cr0 = read_cr0(); |
5571 | WARN_ON(cr0 & X86_CR0_TS); | |
5572 | vmcs_writel(HOST_CR0, cr0); /* 22.2.3 */ | |
d6e41f11 AL |
5573 | |
5574 | /* | |
5575 | * Save the most likely value for this task's CR3 in the VMCS. | |
5576 | * We can't use __get_current_cr3_fast() because we're not atomic. | |
5577 | */ | |
6c690ee1 | 5578 | cr3 = __read_cr3(); |
d6e41f11 | 5579 | vmcs_writel(HOST_CR3, cr3); /* 22.2.3 FIXME: shadow tables */ |
44889942 | 5580 | vmx->loaded_vmcs->vmcs_host_cr3 = cr3; |
a3a8ff8e | 5581 | |
d974baa3 | 5582 | /* Save the most likely value for this task's CR4 in the VMCS. */ |
1e02ce4c | 5583 | cr4 = cr4_read_shadow(); |
d974baa3 | 5584 | vmcs_writel(HOST_CR4, cr4); /* 22.2.3, 22.2.5 */ |
44889942 | 5585 | vmx->loaded_vmcs->vmcs_host_cr4 = cr4; |
d974baa3 | 5586 | |
a3a8ff8e | 5587 | vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */ |
b2da15ac AK |
5588 | #ifdef CONFIG_X86_64 |
5589 | /* | |
5590 | * Load null selectors, so we can avoid reloading them in | |
5591 | * __vmx_load_host_state(), in case userspace uses the null selectors | |
5592 | * too (the expected case). | |
5593 | */ | |
5594 | vmcs_write16(HOST_DS_SELECTOR, 0); | |
5595 | vmcs_write16(HOST_ES_SELECTOR, 0); | |
5596 | #else | |
a3a8ff8e NHE |
5597 | vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */ |
5598 | vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */ | |
b2da15ac | 5599 | #endif |
a3a8ff8e NHE |
5600 | vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */ |
5601 | vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */ | |
5602 | ||
87930019 | 5603 | store_idt(&dt); |
a3a8ff8e | 5604 | vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */ |
a547c6db | 5605 | vmx->host_idt_base = dt.address; |
a3a8ff8e | 5606 | |
83287ea4 | 5607 | vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */ |
a3a8ff8e NHE |
5608 | |
5609 | rdmsr(MSR_IA32_SYSENTER_CS, low32, high32); | |
5610 | vmcs_write32(HOST_IA32_SYSENTER_CS, low32); | |
5611 | rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl); | |
5612 | vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */ | |
5613 | ||
5614 | if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) { | |
5615 | rdmsr(MSR_IA32_CR_PAT, low32, high32); | |
5616 | vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32)); | |
5617 | } | |
5618 | } | |
5619 | ||
bf8179a0 NHE |
5620 | static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx) |
5621 | { | |
5622 | vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS; | |
5623 | if (enable_ept) | |
5624 | vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE; | |
fe3ef05c NHE |
5625 | if (is_guest_mode(&vmx->vcpu)) |
5626 | vmx->vcpu.arch.cr4_guest_owned_bits &= | |
5627 | ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask; | |
bf8179a0 NHE |
5628 | vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits); |
5629 | } | |
5630 | ||
01e439be YZ |
5631 | static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx) |
5632 | { | |
5633 | u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl; | |
5634 | ||
d62caabb | 5635 | if (!kvm_vcpu_apicv_active(&vmx->vcpu)) |
01e439be | 5636 | pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR; |
d02fcf50 PB |
5637 | |
5638 | if (!enable_vnmi) | |
5639 | pin_based_exec_ctrl &= ~PIN_BASED_VIRTUAL_NMIS; | |
5640 | ||
64672c95 YJ |
5641 | /* Enable the preemption timer dynamically */ |
5642 | pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER; | |
01e439be YZ |
5643 | return pin_based_exec_ctrl; |
5644 | } | |
5645 | ||
d62caabb AS |
5646 | static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu) |
5647 | { | |
5648 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
5649 | ||
5650 | vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx)); | |
3ce424e4 RK |
5651 | if (cpu_has_secondary_exec_ctrls()) { |
5652 | if (kvm_vcpu_apicv_active(vcpu)) | |
5653 | vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL, | |
5654 | SECONDARY_EXEC_APIC_REGISTER_VIRT | | |
5655 | SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); | |
5656 | else | |
5657 | vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL, | |
5658 | SECONDARY_EXEC_APIC_REGISTER_VIRT | | |
5659 | SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); | |
5660 | } | |
5661 | ||
5662 | if (cpu_has_vmx_msr_bitmap()) | |
4b0be90f | 5663 | vmx_update_msr_bitmap(vcpu); |
d62caabb AS |
5664 | } |
5665 | ||
bf8179a0 NHE |
5666 | static u32 vmx_exec_control(struct vcpu_vmx *vmx) |
5667 | { | |
5668 | u32 exec_control = vmcs_config.cpu_based_exec_ctrl; | |
d16c293e PB |
5669 | |
5670 | if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT) | |
5671 | exec_control &= ~CPU_BASED_MOV_DR_EXITING; | |
5672 | ||
35754c98 | 5673 | if (!cpu_need_tpr_shadow(&vmx->vcpu)) { |
bf8179a0 NHE |
5674 | exec_control &= ~CPU_BASED_TPR_SHADOW; |
5675 | #ifdef CONFIG_X86_64 | |
5676 | exec_control |= CPU_BASED_CR8_STORE_EXITING | | |
5677 | CPU_BASED_CR8_LOAD_EXITING; | |
5678 | #endif | |
5679 | } | |
5680 | if (!enable_ept) | |
5681 | exec_control |= CPU_BASED_CR3_STORE_EXITING | | |
5682 | CPU_BASED_CR3_LOAD_EXITING | | |
5683 | CPU_BASED_INVLPG_EXITING; | |
5684 | return exec_control; | |
5685 | } | |
5686 | ||
45ec368c | 5687 | static bool vmx_rdrand_supported(void) |
bf8179a0 | 5688 | { |
45ec368c | 5689 | return vmcs_config.cpu_based_2nd_exec_ctrl & |
736fdf72 | 5690 | SECONDARY_EXEC_RDRAND_EXITING; |
45ec368c JM |
5691 | } |
5692 | ||
75f4fc8d JM |
5693 | static bool vmx_rdseed_supported(void) |
5694 | { | |
5695 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
736fdf72 | 5696 | SECONDARY_EXEC_RDSEED_EXITING; |
75f4fc8d JM |
5697 | } |
5698 | ||
80154d77 | 5699 | static void vmx_compute_secondary_exec_control(struct vcpu_vmx *vmx) |
bf8179a0 | 5700 | { |
80154d77 PB |
5701 | struct kvm_vcpu *vcpu = &vmx->vcpu; |
5702 | ||
bf8179a0 | 5703 | u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl; |
80154d77 | 5704 | if (!cpu_need_virtualize_apic_accesses(vcpu)) |
bf8179a0 NHE |
5705 | exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; |
5706 | if (vmx->vpid == 0) | |
5707 | exec_control &= ~SECONDARY_EXEC_ENABLE_VPID; | |
5708 | if (!enable_ept) { | |
5709 | exec_control &= ~SECONDARY_EXEC_ENABLE_EPT; | |
5710 | enable_unrestricted_guest = 0; | |
ad756a16 MJ |
5711 | /* Enable INVPCID for non-ept guests may cause performance regression. */ |
5712 | exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID; | |
bf8179a0 NHE |
5713 | } |
5714 | if (!enable_unrestricted_guest) | |
5715 | exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST; | |
5716 | if (!ple_gap) | |
5717 | exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING; | |
80154d77 | 5718 | if (!kvm_vcpu_apicv_active(vcpu)) |
c7c9c56c YZ |
5719 | exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT | |
5720 | SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); | |
8d14695f | 5721 | exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE; |
abc4fc58 AG |
5722 | /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD |
5723 | (handle_vmptrld). | |
5724 | We can NOT enable shadow_vmcs here because we don't have yet | |
5725 | a current VMCS12 | |
5726 | */ | |
5727 | exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS; | |
a3eaa864 KH |
5728 | |
5729 | if (!enable_pml) | |
5730 | exec_control &= ~SECONDARY_EXEC_ENABLE_PML; | |
843e4330 | 5731 | |
3db13480 PB |
5732 | if (vmx_xsaves_supported()) { |
5733 | /* Exposing XSAVES only when XSAVE is exposed */ | |
5734 | bool xsaves_enabled = | |
5735 | guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && | |
5736 | guest_cpuid_has(vcpu, X86_FEATURE_XSAVES); | |
5737 | ||
5738 | if (!xsaves_enabled) | |
5739 | exec_control &= ~SECONDARY_EXEC_XSAVES; | |
5740 | ||
5741 | if (nested) { | |
5742 | if (xsaves_enabled) | |
5743 | vmx->nested.nested_vmx_secondary_ctls_high |= | |
5744 | SECONDARY_EXEC_XSAVES; | |
5745 | else | |
5746 | vmx->nested.nested_vmx_secondary_ctls_high &= | |
5747 | ~SECONDARY_EXEC_XSAVES; | |
5748 | } | |
5749 | } | |
5750 | ||
80154d77 PB |
5751 | if (vmx_rdtscp_supported()) { |
5752 | bool rdtscp_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP); | |
5753 | if (!rdtscp_enabled) | |
5754 | exec_control &= ~SECONDARY_EXEC_RDTSCP; | |
5755 | ||
5756 | if (nested) { | |
5757 | if (rdtscp_enabled) | |
5758 | vmx->nested.nested_vmx_secondary_ctls_high |= | |
5759 | SECONDARY_EXEC_RDTSCP; | |
5760 | else | |
5761 | vmx->nested.nested_vmx_secondary_ctls_high &= | |
5762 | ~SECONDARY_EXEC_RDTSCP; | |
5763 | } | |
5764 | } | |
5765 | ||
5766 | if (vmx_invpcid_supported()) { | |
5767 | /* Exposing INVPCID only when PCID is exposed */ | |
5768 | bool invpcid_enabled = | |
5769 | guest_cpuid_has(vcpu, X86_FEATURE_INVPCID) && | |
5770 | guest_cpuid_has(vcpu, X86_FEATURE_PCID); | |
5771 | ||
5772 | if (!invpcid_enabled) { | |
5773 | exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID; | |
5774 | guest_cpuid_clear(vcpu, X86_FEATURE_INVPCID); | |
5775 | } | |
5776 | ||
5777 | if (nested) { | |
5778 | if (invpcid_enabled) | |
5779 | vmx->nested.nested_vmx_secondary_ctls_high |= | |
5780 | SECONDARY_EXEC_ENABLE_INVPCID; | |
5781 | else | |
5782 | vmx->nested.nested_vmx_secondary_ctls_high &= | |
5783 | ~SECONDARY_EXEC_ENABLE_INVPCID; | |
5784 | } | |
5785 | } | |
5786 | ||
45ec368c JM |
5787 | if (vmx_rdrand_supported()) { |
5788 | bool rdrand_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDRAND); | |
5789 | if (rdrand_enabled) | |
736fdf72 | 5790 | exec_control &= ~SECONDARY_EXEC_RDRAND_EXITING; |
45ec368c JM |
5791 | |
5792 | if (nested) { | |
5793 | if (rdrand_enabled) | |
5794 | vmx->nested.nested_vmx_secondary_ctls_high |= | |
736fdf72 | 5795 | SECONDARY_EXEC_RDRAND_EXITING; |
45ec368c JM |
5796 | else |
5797 | vmx->nested.nested_vmx_secondary_ctls_high &= | |
736fdf72 | 5798 | ~SECONDARY_EXEC_RDRAND_EXITING; |
45ec368c JM |
5799 | } |
5800 | } | |
5801 | ||
75f4fc8d JM |
5802 | if (vmx_rdseed_supported()) { |
5803 | bool rdseed_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDSEED); | |
5804 | if (rdseed_enabled) | |
736fdf72 | 5805 | exec_control &= ~SECONDARY_EXEC_RDSEED_EXITING; |
75f4fc8d JM |
5806 | |
5807 | if (nested) { | |
5808 | if (rdseed_enabled) | |
5809 | vmx->nested.nested_vmx_secondary_ctls_high |= | |
736fdf72 | 5810 | SECONDARY_EXEC_RDSEED_EXITING; |
75f4fc8d JM |
5811 | else |
5812 | vmx->nested.nested_vmx_secondary_ctls_high &= | |
736fdf72 | 5813 | ~SECONDARY_EXEC_RDSEED_EXITING; |
75f4fc8d JM |
5814 | } |
5815 | } | |
5816 | ||
80154d77 | 5817 | vmx->secondary_exec_control = exec_control; |
bf8179a0 NHE |
5818 | } |
5819 | ||
ce88decf XG |
5820 | static void ept_set_mmio_spte_mask(void) |
5821 | { | |
5822 | /* | |
5823 | * EPT Misconfigurations can be generated if the value of bits 2:0 | |
5824 | * of an EPT paging-structure entry is 110b (write/execute). | |
ce88decf | 5825 | */ |
dcdca5fe PF |
5826 | kvm_mmu_set_mmio_spte_mask(VMX_EPT_RWX_MASK, |
5827 | VMX_EPT_MISCONFIG_WX_VALUE); | |
ce88decf XG |
5828 | } |
5829 | ||
f53cd63c | 5830 | #define VMX_XSS_EXIT_BITMAP 0 |
6aa8b732 AK |
5831 | /* |
5832 | * Sets up the vmcs for emulated real mode. | |
5833 | */ | |
12d79917 | 5834 | static void vmx_vcpu_setup(struct vcpu_vmx *vmx) |
6aa8b732 | 5835 | { |
2e4ce7f5 | 5836 | #ifdef CONFIG_X86_64 |
6aa8b732 | 5837 | unsigned long a; |
2e4ce7f5 | 5838 | #endif |
6aa8b732 | 5839 | int i; |
6aa8b732 | 5840 | |
6aa8b732 | 5841 | /* I/O */ |
3e7c73e9 AK |
5842 | vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a)); |
5843 | vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b)); | |
6aa8b732 | 5844 | |
4607c2d7 AG |
5845 | if (enable_shadow_vmcs) { |
5846 | vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap)); | |
5847 | vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap)); | |
5848 | } | |
25c5f225 | 5849 | if (cpu_has_vmx_msr_bitmap()) |
4b0be90f | 5850 | vmcs_write64(MSR_BITMAP, __pa(vmx->vmcs01.msr_bitmap)); |
25c5f225 | 5851 | |
6aa8b732 AK |
5852 | vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */ |
5853 | ||
6aa8b732 | 5854 | /* Control */ |
01e439be | 5855 | vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx)); |
64672c95 | 5856 | vmx->hv_deadline_tsc = -1; |
6e5d865c | 5857 | |
bf8179a0 | 5858 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx)); |
6aa8b732 | 5859 | |
dfa169bb | 5860 | if (cpu_has_secondary_exec_ctrls()) { |
80154d77 | 5861 | vmx_compute_secondary_exec_control(vmx); |
bf8179a0 | 5862 | vmcs_write32(SECONDARY_VM_EXEC_CONTROL, |
80154d77 | 5863 | vmx->secondary_exec_control); |
dfa169bb | 5864 | } |
f78e0e2e | 5865 | |
d62caabb | 5866 | if (kvm_vcpu_apicv_active(&vmx->vcpu)) { |
c7c9c56c YZ |
5867 | vmcs_write64(EOI_EXIT_BITMAP0, 0); |
5868 | vmcs_write64(EOI_EXIT_BITMAP1, 0); | |
5869 | vmcs_write64(EOI_EXIT_BITMAP2, 0); | |
5870 | vmcs_write64(EOI_EXIT_BITMAP3, 0); | |
5871 | ||
5872 | vmcs_write16(GUEST_INTR_STATUS, 0); | |
01e439be | 5873 | |
0bcf261c | 5874 | vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR); |
01e439be | 5875 | vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc))); |
c7c9c56c YZ |
5876 | } |
5877 | ||
4b8d54f9 ZE |
5878 | if (ple_gap) { |
5879 | vmcs_write32(PLE_GAP, ple_gap); | |
a7653ecd RK |
5880 | vmx->ple_window = ple_window; |
5881 | vmx->ple_window_dirty = true; | |
4b8d54f9 ZE |
5882 | } |
5883 | ||
c3707958 XG |
5884 | vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0); |
5885 | vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0); | |
6aa8b732 AK |
5886 | vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */ |
5887 | ||
9581d442 AK |
5888 | vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */ |
5889 | vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */ | |
a547c6db | 5890 | vmx_set_constant_host_state(vmx); |
05b3e0c2 | 5891 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
5892 | rdmsrl(MSR_FS_BASE, a); |
5893 | vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */ | |
5894 | rdmsrl(MSR_GS_BASE, a); | |
5895 | vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */ | |
5896 | #else | |
5897 | vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */ | |
5898 | vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */ | |
5899 | #endif | |
5900 | ||
2a499e49 BD |
5901 | if (cpu_has_vmx_vmfunc()) |
5902 | vmcs_write64(VM_FUNCTION_CONTROL, 0); | |
5903 | ||
2cc51560 ED |
5904 | vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0); |
5905 | vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0); | |
6e3dedb6 | 5906 | vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host.val)); |
2cc51560 | 5907 | vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0); |
6e3dedb6 | 5908 | vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest.val)); |
6aa8b732 | 5909 | |
74545705 RK |
5910 | if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) |
5911 | vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat); | |
468d472f | 5912 | |
03916db9 | 5913 | for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) { |
6aa8b732 AK |
5914 | u32 index = vmx_msr_index[i]; |
5915 | u32 data_low, data_high; | |
a2fa3e9f | 5916 | int j = vmx->nmsrs; |
6aa8b732 AK |
5917 | |
5918 | if (rdmsr_safe(index, &data_low, &data_high) < 0) | |
5919 | continue; | |
432bd6cb AK |
5920 | if (wrmsr_safe(index, data_low, data_high) < 0) |
5921 | continue; | |
26bb0981 AK |
5922 | vmx->guest_msrs[j].index = i; |
5923 | vmx->guest_msrs[j].data = 0; | |
d5696725 | 5924 | vmx->guest_msrs[j].mask = -1ull; |
a2fa3e9f | 5925 | ++vmx->nmsrs; |
6aa8b732 | 5926 | } |
6aa8b732 | 5927 | |
2961e876 | 5928 | vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl); |
6aa8b732 AK |
5929 | |
5930 | /* 22.2.1, 20.8.1 */ | |
2961e876 | 5931 | vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl); |
1c3d14fe | 5932 | |
bd7e5b08 PB |
5933 | vmx->vcpu.arch.cr0_guest_owned_bits = X86_CR0_TS; |
5934 | vmcs_writel(CR0_GUEST_HOST_MASK, ~X86_CR0_TS); | |
5935 | ||
bf8179a0 | 5936 | set_cr4_guest_host_mask(vmx); |
e00c8cf2 | 5937 | |
f53cd63c WL |
5938 | if (vmx_xsaves_supported()) |
5939 | vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP); | |
5940 | ||
4e59516a PF |
5941 | if (enable_pml) { |
5942 | ASSERT(vmx->pml_pg); | |
5943 | vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg)); | |
5944 | vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1); | |
5945 | } | |
e00c8cf2 AK |
5946 | } |
5947 | ||
d28bc9dd | 5948 | static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event) |
e00c8cf2 AK |
5949 | { |
5950 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
58cb628d | 5951 | struct msr_data apic_base_msr; |
d28bc9dd | 5952 | u64 cr0; |
e00c8cf2 | 5953 | |
7ffd92c5 | 5954 | vmx->rmode.vm86_active = 0; |
74469996 | 5955 | vmx->spec_ctrl = 0; |
e00c8cf2 | 5956 | |
2033c674 | 5957 | vcpu->arch.microcode_version = 0x100000000ULL; |
ad312c7c | 5958 | vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val(); |
d28bc9dd NA |
5959 | kvm_set_cr8(vcpu, 0); |
5960 | ||
5961 | if (!init_event) { | |
5962 | apic_base_msr.data = APIC_DEFAULT_PHYS_BASE | | |
5963 | MSR_IA32_APICBASE_ENABLE; | |
5964 | if (kvm_vcpu_is_reset_bsp(vcpu)) | |
5965 | apic_base_msr.data |= MSR_IA32_APICBASE_BSP; | |
5966 | apic_base_msr.host_initiated = true; | |
5967 | kvm_set_apic_base(vcpu, &apic_base_msr); | |
5968 | } | |
e00c8cf2 | 5969 | |
2fb92db1 AK |
5970 | vmx_segment_cache_clear(vmx); |
5971 | ||
5706be0d | 5972 | seg_setup(VCPU_SREG_CS); |
66450a21 | 5973 | vmcs_write16(GUEST_CS_SELECTOR, 0xf000); |
f3531054 | 5974 | vmcs_writel(GUEST_CS_BASE, 0xffff0000ul); |
e00c8cf2 AK |
5975 | |
5976 | seg_setup(VCPU_SREG_DS); | |
5977 | seg_setup(VCPU_SREG_ES); | |
5978 | seg_setup(VCPU_SREG_FS); | |
5979 | seg_setup(VCPU_SREG_GS); | |
5980 | seg_setup(VCPU_SREG_SS); | |
5981 | ||
5982 | vmcs_write16(GUEST_TR_SELECTOR, 0); | |
5983 | vmcs_writel(GUEST_TR_BASE, 0); | |
5984 | vmcs_write32(GUEST_TR_LIMIT, 0xffff); | |
5985 | vmcs_write32(GUEST_TR_AR_BYTES, 0x008b); | |
5986 | ||
5987 | vmcs_write16(GUEST_LDTR_SELECTOR, 0); | |
5988 | vmcs_writel(GUEST_LDTR_BASE, 0); | |
5989 | vmcs_write32(GUEST_LDTR_LIMIT, 0xffff); | |
5990 | vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082); | |
5991 | ||
d28bc9dd NA |
5992 | if (!init_event) { |
5993 | vmcs_write32(GUEST_SYSENTER_CS, 0); | |
5994 | vmcs_writel(GUEST_SYSENTER_ESP, 0); | |
5995 | vmcs_writel(GUEST_SYSENTER_EIP, 0); | |
5996 | vmcs_write64(GUEST_IA32_DEBUGCTL, 0); | |
5997 | } | |
e00c8cf2 | 5998 | |
c37c2873 | 5999 | kvm_set_rflags(vcpu, X86_EFLAGS_FIXED); |
66450a21 | 6000 | kvm_rip_write(vcpu, 0xfff0); |
e00c8cf2 | 6001 | |
e00c8cf2 AK |
6002 | vmcs_writel(GUEST_GDTR_BASE, 0); |
6003 | vmcs_write32(GUEST_GDTR_LIMIT, 0xffff); | |
6004 | ||
6005 | vmcs_writel(GUEST_IDTR_BASE, 0); | |
6006 | vmcs_write32(GUEST_IDTR_LIMIT, 0xffff); | |
6007 | ||
443381a8 | 6008 | vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE); |
e00c8cf2 | 6009 | vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0); |
f3531054 | 6010 | vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0); |
a554d207 WL |
6011 | if (kvm_mpx_supported()) |
6012 | vmcs_write64(GUEST_BNDCFGS, 0); | |
e00c8cf2 | 6013 | |
e00c8cf2 AK |
6014 | setup_msrs(vmx); |
6015 | ||
6aa8b732 AK |
6016 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */ |
6017 | ||
d28bc9dd | 6018 | if (cpu_has_vmx_tpr_shadow() && !init_event) { |
f78e0e2e | 6019 | vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0); |
35754c98 | 6020 | if (cpu_need_tpr_shadow(vcpu)) |
f78e0e2e | 6021 | vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, |
d28bc9dd | 6022 | __pa(vcpu->arch.apic->regs)); |
f78e0e2e SY |
6023 | vmcs_write32(TPR_THRESHOLD, 0); |
6024 | } | |
6025 | ||
a73896cb | 6026 | kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu); |
6aa8b732 | 6027 | |
2384d2b3 SY |
6028 | if (vmx->vpid != 0) |
6029 | vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid); | |
6030 | ||
d28bc9dd | 6031 | cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET; |
d28bc9dd | 6032 | vmx->vcpu.arch.cr0 = cr0; |
f2463247 | 6033 | vmx_set_cr0(vcpu, cr0); /* enter rmode */ |
d28bc9dd | 6034 | vmx_set_cr4(vcpu, 0); |
5690891b | 6035 | vmx_set_efer(vcpu, 0); |
bd7e5b08 | 6036 | |
d28bc9dd | 6037 | update_exception_bitmap(vcpu); |
6aa8b732 | 6038 | |
dd5f5341 | 6039 | vpid_sync_context(vmx->vpid); |
6aa8b732 AK |
6040 | } |
6041 | ||
b6f1250e NHE |
6042 | /* |
6043 | * In nested virtualization, check if L1 asked to exit on external interrupts. | |
6044 | * For most existing hypervisors, this will always return true. | |
6045 | */ | |
6046 | static bool nested_exit_on_intr(struct kvm_vcpu *vcpu) | |
6047 | { | |
6048 | return get_vmcs12(vcpu)->pin_based_vm_exec_control & | |
6049 | PIN_BASED_EXT_INTR_MASK; | |
6050 | } | |
6051 | ||
77b0f5d6 BD |
6052 | /* |
6053 | * In nested virtualization, check if L1 has set | |
6054 | * VM_EXIT_ACK_INTR_ON_EXIT | |
6055 | */ | |
6056 | static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu) | |
6057 | { | |
6058 | return get_vmcs12(vcpu)->vm_exit_controls & | |
6059 | VM_EXIT_ACK_INTR_ON_EXIT; | |
6060 | } | |
6061 | ||
ea8ceb83 JK |
6062 | static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu) |
6063 | { | |
6064 | return get_vmcs12(vcpu)->pin_based_vm_exec_control & | |
6065 | PIN_BASED_NMI_EXITING; | |
6066 | } | |
6067 | ||
c9a7953f | 6068 | static void enable_irq_window(struct kvm_vcpu *vcpu) |
3b86cd99 | 6069 | { |
47c0152e PB |
6070 | vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL, |
6071 | CPU_BASED_VIRTUAL_INTR_PENDING); | |
3b86cd99 JK |
6072 | } |
6073 | ||
c9a7953f | 6074 | static void enable_nmi_window(struct kvm_vcpu *vcpu) |
3b86cd99 | 6075 | { |
d02fcf50 | 6076 | if (!enable_vnmi || |
8a1b4392 | 6077 | vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) { |
c9a7953f JK |
6078 | enable_irq_window(vcpu); |
6079 | return; | |
6080 | } | |
3b86cd99 | 6081 | |
47c0152e PB |
6082 | vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL, |
6083 | CPU_BASED_VIRTUAL_NMI_PENDING); | |
3b86cd99 JK |
6084 | } |
6085 | ||
66fd3f7f | 6086 | static void vmx_inject_irq(struct kvm_vcpu *vcpu) |
85f455f7 | 6087 | { |
9c8cba37 | 6088 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
66fd3f7f GN |
6089 | uint32_t intr; |
6090 | int irq = vcpu->arch.interrupt.nr; | |
9c8cba37 | 6091 | |
229456fc | 6092 | trace_kvm_inj_virq(irq); |
2714d1d3 | 6093 | |
fa89a817 | 6094 | ++vcpu->stat.irq_injections; |
7ffd92c5 | 6095 | if (vmx->rmode.vm86_active) { |
71f9833b SH |
6096 | int inc_eip = 0; |
6097 | if (vcpu->arch.interrupt.soft) | |
6098 | inc_eip = vcpu->arch.event_exit_inst_len; | |
6099 | if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE) | |
a92601bb | 6100 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
85f455f7 ED |
6101 | return; |
6102 | } | |
66fd3f7f GN |
6103 | intr = irq | INTR_INFO_VALID_MASK; |
6104 | if (vcpu->arch.interrupt.soft) { | |
6105 | intr |= INTR_TYPE_SOFT_INTR; | |
6106 | vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, | |
6107 | vmx->vcpu.arch.event_exit_inst_len); | |
6108 | } else | |
6109 | intr |= INTR_TYPE_EXT_INTR; | |
6110 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr); | |
85f455f7 ED |
6111 | } |
6112 | ||
f08864b4 SY |
6113 | static void vmx_inject_nmi(struct kvm_vcpu *vcpu) |
6114 | { | |
66a5a347 JK |
6115 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
6116 | ||
d02fcf50 | 6117 | if (!enable_vnmi) { |
8a1b4392 PB |
6118 | /* |
6119 | * Tracking the NMI-blocked state in software is built upon | |
6120 | * finding the next open IRQ window. This, in turn, depends on | |
6121 | * well-behaving guests: They have to keep IRQs disabled at | |
6122 | * least as long as the NMI handler runs. Otherwise we may | |
6123 | * cause NMI nesting, maybe breaking the guest. But as this is | |
6124 | * highly unlikely, we can live with the residual risk. | |
6125 | */ | |
6126 | vmx->loaded_vmcs->soft_vnmi_blocked = 1; | |
6127 | vmx->loaded_vmcs->vnmi_blocked_time = 0; | |
6128 | } | |
6129 | ||
4c4a6f79 PB |
6130 | ++vcpu->stat.nmi_injections; |
6131 | vmx->loaded_vmcs->nmi_known_unmasked = false; | |
3b86cd99 | 6132 | |
7ffd92c5 | 6133 | if (vmx->rmode.vm86_active) { |
71f9833b | 6134 | if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE) |
a92601bb | 6135 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
66a5a347 JK |
6136 | return; |
6137 | } | |
c5a6d5f7 | 6138 | |
f08864b4 SY |
6139 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, |
6140 | INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR); | |
f08864b4 SY |
6141 | } |
6142 | ||
3cfc3092 JK |
6143 | static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu) |
6144 | { | |
4c4a6f79 PB |
6145 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
6146 | bool masked; | |
6147 | ||
d02fcf50 | 6148 | if (!enable_vnmi) |
8a1b4392 | 6149 | return vmx->loaded_vmcs->soft_vnmi_blocked; |
4c4a6f79 | 6150 | if (vmx->loaded_vmcs->nmi_known_unmasked) |
9d58b931 | 6151 | return false; |
4c4a6f79 PB |
6152 | masked = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI; |
6153 | vmx->loaded_vmcs->nmi_known_unmasked = !masked; | |
6154 | return masked; | |
3cfc3092 JK |
6155 | } |
6156 | ||
6157 | static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked) | |
6158 | { | |
6159 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
6160 | ||
d02fcf50 | 6161 | if (!enable_vnmi) { |
8a1b4392 PB |
6162 | if (vmx->loaded_vmcs->soft_vnmi_blocked != masked) { |
6163 | vmx->loaded_vmcs->soft_vnmi_blocked = masked; | |
6164 | vmx->loaded_vmcs->vnmi_blocked_time = 0; | |
6165 | } | |
6166 | } else { | |
6167 | vmx->loaded_vmcs->nmi_known_unmasked = !masked; | |
6168 | if (masked) | |
6169 | vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, | |
6170 | GUEST_INTR_STATE_NMI); | |
6171 | else | |
6172 | vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO, | |
6173 | GUEST_INTR_STATE_NMI); | |
6174 | } | |
3cfc3092 JK |
6175 | } |
6176 | ||
2505dc9f JK |
6177 | static int vmx_nmi_allowed(struct kvm_vcpu *vcpu) |
6178 | { | |
b6b8a145 JK |
6179 | if (to_vmx(vcpu)->nested.nested_run_pending) |
6180 | return 0; | |
ea8ceb83 | 6181 | |
d02fcf50 | 6182 | if (!enable_vnmi && |
8a1b4392 PB |
6183 | to_vmx(vcpu)->loaded_vmcs->soft_vnmi_blocked) |
6184 | return 0; | |
6185 | ||
2505dc9f JK |
6186 | return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & |
6187 | (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI | |
6188 | | GUEST_INTR_STATE_NMI)); | |
6189 | } | |
6190 | ||
78646121 GN |
6191 | static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu) |
6192 | { | |
b6b8a145 JK |
6193 | return (!to_vmx(vcpu)->nested.nested_run_pending && |
6194 | vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) && | |
c4282df9 GN |
6195 | !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & |
6196 | (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS)); | |
78646121 GN |
6197 | } |
6198 | ||
cbc94022 IE |
6199 | static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr) |
6200 | { | |
6201 | int ret; | |
cbc94022 | 6202 | |
1d8007bd PB |
6203 | ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr, |
6204 | PAGE_SIZE * 3); | |
cbc94022 IE |
6205 | if (ret) |
6206 | return ret; | |
bfc6d222 | 6207 | kvm->arch.tss_addr = addr; |
1f755a82 | 6208 | return init_rmode_tss(kvm); |
cbc94022 IE |
6209 | } |
6210 | ||
0ca1b4f4 | 6211 | static bool rmode_exception(struct kvm_vcpu *vcpu, int vec) |
6aa8b732 | 6212 | { |
77ab6db0 | 6213 | switch (vec) { |
77ab6db0 | 6214 | case BP_VECTOR: |
c573cd22 JK |
6215 | /* |
6216 | * Update instruction length as we may reinject the exception | |
6217 | * from user space while in guest debugging mode. | |
6218 | */ | |
6219 | to_vmx(vcpu)->vcpu.arch.event_exit_inst_len = | |
6220 | vmcs_read32(VM_EXIT_INSTRUCTION_LEN); | |
d0bfb940 | 6221 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP) |
0ca1b4f4 GN |
6222 | return false; |
6223 | /* fall through */ | |
6224 | case DB_VECTOR: | |
6225 | if (vcpu->guest_debug & | |
6226 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) | |
6227 | return false; | |
d0bfb940 JK |
6228 | /* fall through */ |
6229 | case DE_VECTOR: | |
77ab6db0 JK |
6230 | case OF_VECTOR: |
6231 | case BR_VECTOR: | |
6232 | case UD_VECTOR: | |
6233 | case DF_VECTOR: | |
6234 | case SS_VECTOR: | |
6235 | case GP_VECTOR: | |
6236 | case MF_VECTOR: | |
0ca1b4f4 GN |
6237 | return true; |
6238 | break; | |
77ab6db0 | 6239 | } |
0ca1b4f4 GN |
6240 | return false; |
6241 | } | |
6242 | ||
6243 | static int handle_rmode_exception(struct kvm_vcpu *vcpu, | |
6244 | int vec, u32 err_code) | |
6245 | { | |
6246 | /* | |
6247 | * Instruction with address size override prefix opcode 0x67 | |
6248 | * Cause the #SS fault with 0 error code in VM86 mode. | |
6249 | */ | |
6250 | if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) { | |
6251 | if (emulate_instruction(vcpu, 0) == EMULATE_DONE) { | |
6252 | if (vcpu->arch.halt_request) { | |
6253 | vcpu->arch.halt_request = 0; | |
5cb56059 | 6254 | return kvm_vcpu_halt(vcpu); |
0ca1b4f4 GN |
6255 | } |
6256 | return 1; | |
6257 | } | |
6258 | return 0; | |
6259 | } | |
6260 | ||
6261 | /* | |
6262 | * Forward all other exceptions that are valid in real mode. | |
6263 | * FIXME: Breaks guest debugging in real mode, needs to be fixed with | |
6264 | * the required debugging infrastructure rework. | |
6265 | */ | |
6266 | kvm_queue_exception(vcpu, vec); | |
6267 | return 1; | |
6aa8b732 AK |
6268 | } |
6269 | ||
a0861c02 AK |
6270 | /* |
6271 | * Trigger machine check on the host. We assume all the MSRs are already set up | |
6272 | * by the CPU and that we still run on the same CPU as the MCE occurred on. | |
6273 | * We pass a fake environment to the machine check handler because we want | |
6274 | * the guest to be always treated like user space, no matter what context | |
6275 | * it used internally. | |
6276 | */ | |
6277 | static void kvm_machine_check(void) | |
6278 | { | |
6279 | #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64) | |
6280 | struct pt_regs regs = { | |
6281 | .cs = 3, /* Fake ring 3 no matter what the guest ran on */ | |
6282 | .flags = X86_EFLAGS_IF, | |
6283 | }; | |
6284 | ||
6285 | do_machine_check(®s, 0); | |
6286 | #endif | |
6287 | } | |
6288 | ||
851ba692 | 6289 | static int handle_machine_check(struct kvm_vcpu *vcpu) |
a0861c02 AK |
6290 | { |
6291 | /* already handled by vcpu_run */ | |
6292 | return 1; | |
6293 | } | |
6294 | ||
851ba692 | 6295 | static int handle_exception(struct kvm_vcpu *vcpu) |
6aa8b732 | 6296 | { |
1155f76a | 6297 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
851ba692 | 6298 | struct kvm_run *kvm_run = vcpu->run; |
d0bfb940 | 6299 | u32 intr_info, ex_no, error_code; |
42dbaa5a | 6300 | unsigned long cr2, rip, dr6; |
6aa8b732 AK |
6301 | u32 vect_info; |
6302 | enum emulation_result er; | |
6303 | ||
1155f76a | 6304 | vect_info = vmx->idt_vectoring_info; |
88786475 | 6305 | intr_info = vmx->exit_intr_info; |
6aa8b732 | 6306 | |
a0861c02 | 6307 | if (is_machine_check(intr_info)) |
851ba692 | 6308 | return handle_machine_check(vcpu); |
a0861c02 | 6309 | |
ef85b673 | 6310 | if (is_nmi(intr_info)) |
1b6269db | 6311 | return 1; /* already handled by vmx_vcpu_run() */ |
2ab455cc | 6312 | |
7aa81cc0 | 6313 | if (is_invalid_opcode(intr_info)) { |
51d8b661 | 6314 | er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD); |
61cb57c9 LA |
6315 | if (er == EMULATE_USER_EXIT) |
6316 | return 0; | |
7aa81cc0 | 6317 | if (er != EMULATE_DONE) |
7ee5d940 | 6318 | kvm_queue_exception(vcpu, UD_VECTOR); |
7aa81cc0 AL |
6319 | return 1; |
6320 | } | |
6321 | ||
6aa8b732 | 6322 | error_code = 0; |
2e11384c | 6323 | if (intr_info & INTR_INFO_DELIVER_CODE_MASK) |
6aa8b732 | 6324 | error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE); |
bf4ca23e XG |
6325 | |
6326 | /* | |
6327 | * The #PF with PFEC.RSVD = 1 indicates the guest is accessing | |
6328 | * MMIO, it is better to report an internal error. | |
6329 | * See the comments in vmx_handle_exit. | |
6330 | */ | |
6331 | if ((vect_info & VECTORING_INFO_VALID_MASK) && | |
6332 | !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) { | |
6333 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
6334 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX; | |
80f0e95d | 6335 | vcpu->run->internal.ndata = 3; |
bf4ca23e XG |
6336 | vcpu->run->internal.data[0] = vect_info; |
6337 | vcpu->run->internal.data[1] = intr_info; | |
80f0e95d | 6338 | vcpu->run->internal.data[2] = error_code; |
bf4ca23e XG |
6339 | return 0; |
6340 | } | |
6341 | ||
6aa8b732 AK |
6342 | if (is_page_fault(intr_info)) { |
6343 | cr2 = vmcs_readl(EXIT_QUALIFICATION); | |
1261bfa3 WL |
6344 | /* EPT won't cause page fault directly */ |
6345 | WARN_ON_ONCE(!vcpu->arch.apf.host_apf_reason && enable_ept); | |
d0006530 | 6346 | return kvm_handle_page_fault(vcpu, error_code, cr2, NULL, 0); |
6aa8b732 AK |
6347 | } |
6348 | ||
d0bfb940 | 6349 | ex_no = intr_info & INTR_INFO_VECTOR_MASK; |
0ca1b4f4 GN |
6350 | |
6351 | if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no)) | |
6352 | return handle_rmode_exception(vcpu, ex_no, error_code); | |
6353 | ||
42dbaa5a | 6354 | switch (ex_no) { |
54a20552 EN |
6355 | case AC_VECTOR: |
6356 | kvm_queue_exception_e(vcpu, AC_VECTOR, error_code); | |
6357 | return 1; | |
42dbaa5a JK |
6358 | case DB_VECTOR: |
6359 | dr6 = vmcs_readl(EXIT_QUALIFICATION); | |
6360 | if (!(vcpu->guest_debug & | |
6361 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) { | |
8246bf52 | 6362 | vcpu->arch.dr6 &= ~15; |
6f43ed01 | 6363 | vcpu->arch.dr6 |= dr6 | DR6_RTM; |
3252850d | 6364 | if (is_icebp(intr_info)) |
fd2a445a HD |
6365 | skip_emulated_instruction(vcpu); |
6366 | ||
42dbaa5a JK |
6367 | kvm_queue_exception(vcpu, DB_VECTOR); |
6368 | return 1; | |
6369 | } | |
6370 | kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1; | |
6371 | kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7); | |
6372 | /* fall through */ | |
6373 | case BP_VECTOR: | |
c573cd22 JK |
6374 | /* |
6375 | * Update instruction length as we may reinject #BP from | |
6376 | * user space while in guest debugging mode. Reading it for | |
6377 | * #DB as well causes no harm, it is not used in that case. | |
6378 | */ | |
6379 | vmx->vcpu.arch.event_exit_inst_len = | |
6380 | vmcs_read32(VM_EXIT_INSTRUCTION_LEN); | |
6aa8b732 | 6381 | kvm_run->exit_reason = KVM_EXIT_DEBUG; |
0a434bb2 | 6382 | rip = kvm_rip_read(vcpu); |
d0bfb940 JK |
6383 | kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip; |
6384 | kvm_run->debug.arch.exception = ex_no; | |
42dbaa5a JK |
6385 | break; |
6386 | default: | |
d0bfb940 JK |
6387 | kvm_run->exit_reason = KVM_EXIT_EXCEPTION; |
6388 | kvm_run->ex.exception = ex_no; | |
6389 | kvm_run->ex.error_code = error_code; | |
42dbaa5a | 6390 | break; |
6aa8b732 | 6391 | } |
6aa8b732 AK |
6392 | return 0; |
6393 | } | |
6394 | ||
851ba692 | 6395 | static int handle_external_interrupt(struct kvm_vcpu *vcpu) |
6aa8b732 | 6396 | { |
1165f5fe | 6397 | ++vcpu->stat.irq_exits; |
6aa8b732 AK |
6398 | return 1; |
6399 | } | |
6400 | ||
851ba692 | 6401 | static int handle_triple_fault(struct kvm_vcpu *vcpu) |
988ad74f | 6402 | { |
851ba692 | 6403 | vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN; |
bbeac283 | 6404 | vcpu->mmio_needed = 0; |
988ad74f AK |
6405 | return 0; |
6406 | } | |
6aa8b732 | 6407 | |
851ba692 | 6408 | static int handle_io(struct kvm_vcpu *vcpu) |
6aa8b732 | 6409 | { |
bfdaab09 | 6410 | unsigned long exit_qualification; |
6affcbed | 6411 | int size, in, string, ret; |
039576c0 | 6412 | unsigned port; |
6aa8b732 | 6413 | |
bfdaab09 | 6414 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); |
039576c0 | 6415 | string = (exit_qualification & 16) != 0; |
cf8f70bf | 6416 | in = (exit_qualification & 8) != 0; |
e70669ab | 6417 | |
cf8f70bf | 6418 | ++vcpu->stat.io_exits; |
e70669ab | 6419 | |
cf8f70bf | 6420 | if (string || in) |
51d8b661 | 6421 | return emulate_instruction(vcpu, 0) == EMULATE_DONE; |
e70669ab | 6422 | |
cf8f70bf GN |
6423 | port = exit_qualification >> 16; |
6424 | size = (exit_qualification & 7) + 1; | |
cf8f70bf | 6425 | |
6affcbed KH |
6426 | ret = kvm_skip_emulated_instruction(vcpu); |
6427 | ||
6428 | /* | |
6429 | * TODO: we might be squashing a KVM_GUESTDBG_SINGLESTEP-triggered | |
6430 | * KVM_EXIT_DEBUG here. | |
6431 | */ | |
6432 | return kvm_fast_pio_out(vcpu, size, port) && ret; | |
6aa8b732 AK |
6433 | } |
6434 | ||
102d8325 IM |
6435 | static void |
6436 | vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall) | |
6437 | { | |
6438 | /* | |
6439 | * Patch in the VMCALL instruction: | |
6440 | */ | |
6441 | hypercall[0] = 0x0f; | |
6442 | hypercall[1] = 0x01; | |
6443 | hypercall[2] = 0xc1; | |
102d8325 IM |
6444 | } |
6445 | ||
0fa06071 | 6446 | /* called to set cr0 as appropriate for a mov-to-cr0 exit. */ |
eeadf9e7 NHE |
6447 | static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val) |
6448 | { | |
eeadf9e7 | 6449 | if (is_guest_mode(vcpu)) { |
1a0d74e6 JK |
6450 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); |
6451 | unsigned long orig_val = val; | |
6452 | ||
eeadf9e7 NHE |
6453 | /* |
6454 | * We get here when L2 changed cr0 in a way that did not change | |
6455 | * any of L1's shadowed bits (see nested_vmx_exit_handled_cr), | |
1a0d74e6 JK |
6456 | * but did change L0 shadowed bits. So we first calculate the |
6457 | * effective cr0 value that L1 would like to write into the | |
6458 | * hardware. It consists of the L2-owned bits from the new | |
6459 | * value combined with the L1-owned bits from L1's guest_cr0. | |
eeadf9e7 | 6460 | */ |
1a0d74e6 JK |
6461 | val = (val & ~vmcs12->cr0_guest_host_mask) | |
6462 | (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask); | |
6463 | ||
3899152c | 6464 | if (!nested_guest_cr0_valid(vcpu, val)) |
eeadf9e7 | 6465 | return 1; |
1a0d74e6 JK |
6466 | |
6467 | if (kvm_set_cr0(vcpu, val)) | |
6468 | return 1; | |
6469 | vmcs_writel(CR0_READ_SHADOW, orig_val); | |
eeadf9e7 | 6470 | return 0; |
1a0d74e6 JK |
6471 | } else { |
6472 | if (to_vmx(vcpu)->nested.vmxon && | |
3899152c | 6473 | !nested_host_cr0_valid(vcpu, val)) |
1a0d74e6 | 6474 | return 1; |
3899152c | 6475 | |
eeadf9e7 | 6476 | return kvm_set_cr0(vcpu, val); |
1a0d74e6 | 6477 | } |
eeadf9e7 NHE |
6478 | } |
6479 | ||
6480 | static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val) | |
6481 | { | |
6482 | if (is_guest_mode(vcpu)) { | |
1a0d74e6 JK |
6483 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); |
6484 | unsigned long orig_val = val; | |
6485 | ||
6486 | /* analogously to handle_set_cr0 */ | |
6487 | val = (val & ~vmcs12->cr4_guest_host_mask) | | |
6488 | (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask); | |
6489 | if (kvm_set_cr4(vcpu, val)) | |
eeadf9e7 | 6490 | return 1; |
1a0d74e6 | 6491 | vmcs_writel(CR4_READ_SHADOW, orig_val); |
eeadf9e7 NHE |
6492 | return 0; |
6493 | } else | |
6494 | return kvm_set_cr4(vcpu, val); | |
6495 | } | |
6496 | ||
851ba692 | 6497 | static int handle_cr(struct kvm_vcpu *vcpu) |
6aa8b732 | 6498 | { |
229456fc | 6499 | unsigned long exit_qualification, val; |
6aa8b732 AK |
6500 | int cr; |
6501 | int reg; | |
49a9b07e | 6502 | int err; |
6affcbed | 6503 | int ret; |
6aa8b732 | 6504 | |
bfdaab09 | 6505 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); |
6aa8b732 AK |
6506 | cr = exit_qualification & 15; |
6507 | reg = (exit_qualification >> 8) & 15; | |
6508 | switch ((exit_qualification >> 4) & 3) { | |
6509 | case 0: /* mov to cr */ | |
1e32c079 | 6510 | val = kvm_register_readl(vcpu, reg); |
229456fc | 6511 | trace_kvm_cr_write(cr, val); |
6aa8b732 AK |
6512 | switch (cr) { |
6513 | case 0: | |
eeadf9e7 | 6514 | err = handle_set_cr0(vcpu, val); |
6affcbed | 6515 | return kvm_complete_insn_gp(vcpu, err); |
6aa8b732 | 6516 | case 3: |
2390218b | 6517 | err = kvm_set_cr3(vcpu, val); |
6affcbed | 6518 | return kvm_complete_insn_gp(vcpu, err); |
6aa8b732 | 6519 | case 4: |
eeadf9e7 | 6520 | err = handle_set_cr4(vcpu, val); |
6affcbed | 6521 | return kvm_complete_insn_gp(vcpu, err); |
0a5fff19 GN |
6522 | case 8: { |
6523 | u8 cr8_prev = kvm_get_cr8(vcpu); | |
1e32c079 | 6524 | u8 cr8 = (u8)val; |
eea1cff9 | 6525 | err = kvm_set_cr8(vcpu, cr8); |
6affcbed | 6526 | ret = kvm_complete_insn_gp(vcpu, err); |
35754c98 | 6527 | if (lapic_in_kernel(vcpu)) |
6affcbed | 6528 | return ret; |
0a5fff19 | 6529 | if (cr8_prev <= cr8) |
6affcbed KH |
6530 | return ret; |
6531 | /* | |
6532 | * TODO: we might be squashing a | |
6533 | * KVM_GUESTDBG_SINGLESTEP-triggered | |
6534 | * KVM_EXIT_DEBUG here. | |
6535 | */ | |
851ba692 | 6536 | vcpu->run->exit_reason = KVM_EXIT_SET_TPR; |
0a5fff19 GN |
6537 | return 0; |
6538 | } | |
4b8073e4 | 6539 | } |
6aa8b732 | 6540 | break; |
25c4c276 | 6541 | case 2: /* clts */ |
bd7e5b08 PB |
6542 | WARN_ONCE(1, "Guest should always own CR0.TS"); |
6543 | vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS)); | |
4d4ec087 | 6544 | trace_kvm_cr_write(0, kvm_read_cr0(vcpu)); |
6affcbed | 6545 | return kvm_skip_emulated_instruction(vcpu); |
6aa8b732 AK |
6546 | case 1: /*mov from cr*/ |
6547 | switch (cr) { | |
6548 | case 3: | |
9f8fe504 AK |
6549 | val = kvm_read_cr3(vcpu); |
6550 | kvm_register_write(vcpu, reg, val); | |
6551 | trace_kvm_cr_read(cr, val); | |
6affcbed | 6552 | return kvm_skip_emulated_instruction(vcpu); |
6aa8b732 | 6553 | case 8: |
229456fc MT |
6554 | val = kvm_get_cr8(vcpu); |
6555 | kvm_register_write(vcpu, reg, val); | |
6556 | trace_kvm_cr_read(cr, val); | |
6affcbed | 6557 | return kvm_skip_emulated_instruction(vcpu); |
6aa8b732 AK |
6558 | } |
6559 | break; | |
6560 | case 3: /* lmsw */ | |
a1f83a74 | 6561 | val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f; |
4d4ec087 | 6562 | trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val); |
a1f83a74 | 6563 | kvm_lmsw(vcpu, val); |
6aa8b732 | 6564 | |
6affcbed | 6565 | return kvm_skip_emulated_instruction(vcpu); |
6aa8b732 AK |
6566 | default: |
6567 | break; | |
6568 | } | |
851ba692 | 6569 | vcpu->run->exit_reason = 0; |
a737f256 | 6570 | vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n", |
6aa8b732 AK |
6571 | (int)(exit_qualification >> 4) & 3, cr); |
6572 | return 0; | |
6573 | } | |
6574 | ||
851ba692 | 6575 | static int handle_dr(struct kvm_vcpu *vcpu) |
6aa8b732 | 6576 | { |
bfdaab09 | 6577 | unsigned long exit_qualification; |
16f8a6f9 NA |
6578 | int dr, dr7, reg; |
6579 | ||
6580 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
6581 | dr = exit_qualification & DEBUG_REG_ACCESS_NUM; | |
6582 | ||
6583 | /* First, if DR does not exist, trigger UD */ | |
6584 | if (!kvm_require_dr(vcpu, dr)) | |
6585 | return 1; | |
6aa8b732 | 6586 | |
f2483415 | 6587 | /* Do not handle if the CPL > 0, will trigger GP on re-entry */ |
0a79b009 AK |
6588 | if (!kvm_require_cpl(vcpu, 0)) |
6589 | return 1; | |
16f8a6f9 NA |
6590 | dr7 = vmcs_readl(GUEST_DR7); |
6591 | if (dr7 & DR7_GD) { | |
42dbaa5a JK |
6592 | /* |
6593 | * As the vm-exit takes precedence over the debug trap, we | |
6594 | * need to emulate the latter, either for the host or the | |
6595 | * guest debugging itself. | |
6596 | */ | |
6597 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) { | |
851ba692 | 6598 | vcpu->run->debug.arch.dr6 = vcpu->arch.dr6; |
16f8a6f9 | 6599 | vcpu->run->debug.arch.dr7 = dr7; |
82b32774 | 6600 | vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu); |
851ba692 AK |
6601 | vcpu->run->debug.arch.exception = DB_VECTOR; |
6602 | vcpu->run->exit_reason = KVM_EXIT_DEBUG; | |
42dbaa5a JK |
6603 | return 0; |
6604 | } else { | |
7305eb5d | 6605 | vcpu->arch.dr6 &= ~15; |
6f43ed01 | 6606 | vcpu->arch.dr6 |= DR6_BD | DR6_RTM; |
42dbaa5a JK |
6607 | kvm_queue_exception(vcpu, DB_VECTOR); |
6608 | return 1; | |
6609 | } | |
6610 | } | |
6611 | ||
81908bf4 | 6612 | if (vcpu->guest_debug == 0) { |
8f22372f PB |
6613 | vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL, |
6614 | CPU_BASED_MOV_DR_EXITING); | |
81908bf4 PB |
6615 | |
6616 | /* | |
6617 | * No more DR vmexits; force a reload of the debug registers | |
6618 | * and reenter on this instruction. The next vmexit will | |
6619 | * retrieve the full state of the debug registers. | |
6620 | */ | |
6621 | vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT; | |
6622 | return 1; | |
6623 | } | |
6624 | ||
42dbaa5a JK |
6625 | reg = DEBUG_REG_ACCESS_REG(exit_qualification); |
6626 | if (exit_qualification & TYPE_MOV_FROM_DR) { | |
020df079 | 6627 | unsigned long val; |
4c4d563b JK |
6628 | |
6629 | if (kvm_get_dr(vcpu, dr, &val)) | |
6630 | return 1; | |
6631 | kvm_register_write(vcpu, reg, val); | |
020df079 | 6632 | } else |
5777392e | 6633 | if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg))) |
4c4d563b JK |
6634 | return 1; |
6635 | ||
6affcbed | 6636 | return kvm_skip_emulated_instruction(vcpu); |
6aa8b732 AK |
6637 | } |
6638 | ||
73aaf249 JK |
6639 | static u64 vmx_get_dr6(struct kvm_vcpu *vcpu) |
6640 | { | |
6641 | return vcpu->arch.dr6; | |
6642 | } | |
6643 | ||
6644 | static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val) | |
6645 | { | |
6646 | } | |
6647 | ||
81908bf4 PB |
6648 | static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu) |
6649 | { | |
81908bf4 PB |
6650 | get_debugreg(vcpu->arch.db[0], 0); |
6651 | get_debugreg(vcpu->arch.db[1], 1); | |
6652 | get_debugreg(vcpu->arch.db[2], 2); | |
6653 | get_debugreg(vcpu->arch.db[3], 3); | |
6654 | get_debugreg(vcpu->arch.dr6, 6); | |
6655 | vcpu->arch.dr7 = vmcs_readl(GUEST_DR7); | |
6656 | ||
6657 | vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT; | |
8f22372f | 6658 | vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL, CPU_BASED_MOV_DR_EXITING); |
81908bf4 PB |
6659 | } |
6660 | ||
020df079 GN |
6661 | static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val) |
6662 | { | |
6663 | vmcs_writel(GUEST_DR7, val); | |
6664 | } | |
6665 | ||
851ba692 | 6666 | static int handle_cpuid(struct kvm_vcpu *vcpu) |
6aa8b732 | 6667 | { |
6a908b62 | 6668 | return kvm_emulate_cpuid(vcpu); |
6aa8b732 AK |
6669 | } |
6670 | ||
851ba692 | 6671 | static int handle_rdmsr(struct kvm_vcpu *vcpu) |
6aa8b732 | 6672 | { |
ad312c7c | 6673 | u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX]; |
609e36d3 | 6674 | struct msr_data msr_info; |
6aa8b732 | 6675 | |
609e36d3 PB |
6676 | msr_info.index = ecx; |
6677 | msr_info.host_initiated = false; | |
6678 | if (vmx_get_msr(vcpu, &msr_info)) { | |
59200273 | 6679 | trace_kvm_msr_read_ex(ecx); |
c1a5d4f9 | 6680 | kvm_inject_gp(vcpu, 0); |
6aa8b732 AK |
6681 | return 1; |
6682 | } | |
6683 | ||
609e36d3 | 6684 | trace_kvm_msr_read(ecx, msr_info.data); |
2714d1d3 | 6685 | |
6aa8b732 | 6686 | /* FIXME: handling of bits 32:63 of rax, rdx */ |
609e36d3 PB |
6687 | vcpu->arch.regs[VCPU_REGS_RAX] = msr_info.data & -1u; |
6688 | vcpu->arch.regs[VCPU_REGS_RDX] = (msr_info.data >> 32) & -1u; | |
6affcbed | 6689 | return kvm_skip_emulated_instruction(vcpu); |
6aa8b732 AK |
6690 | } |
6691 | ||
851ba692 | 6692 | static int handle_wrmsr(struct kvm_vcpu *vcpu) |
6aa8b732 | 6693 | { |
8fe8ab46 | 6694 | struct msr_data msr; |
ad312c7c ZX |
6695 | u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX]; |
6696 | u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u) | |
6697 | | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32); | |
6aa8b732 | 6698 | |
8fe8ab46 WA |
6699 | msr.data = data; |
6700 | msr.index = ecx; | |
6701 | msr.host_initiated = false; | |
854e8bb1 | 6702 | if (kvm_set_msr(vcpu, &msr) != 0) { |
59200273 | 6703 | trace_kvm_msr_write_ex(ecx, data); |
c1a5d4f9 | 6704 | kvm_inject_gp(vcpu, 0); |
6aa8b732 AK |
6705 | return 1; |
6706 | } | |
6707 | ||
59200273 | 6708 | trace_kvm_msr_write(ecx, data); |
6affcbed | 6709 | return kvm_skip_emulated_instruction(vcpu); |
6aa8b732 AK |
6710 | } |
6711 | ||
851ba692 | 6712 | static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu) |
6e5d865c | 6713 | { |
eb90f341 | 6714 | kvm_apic_update_ppr(vcpu); |
6e5d865c YS |
6715 | return 1; |
6716 | } | |
6717 | ||
851ba692 | 6718 | static int handle_interrupt_window(struct kvm_vcpu *vcpu) |
6aa8b732 | 6719 | { |
47c0152e PB |
6720 | vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL, |
6721 | CPU_BASED_VIRTUAL_INTR_PENDING); | |
2714d1d3 | 6722 | |
3842d135 AK |
6723 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
6724 | ||
a26bf12a | 6725 | ++vcpu->stat.irq_window_exits; |
6aa8b732 AK |
6726 | return 1; |
6727 | } | |
6728 | ||
851ba692 | 6729 | static int handle_halt(struct kvm_vcpu *vcpu) |
6aa8b732 | 6730 | { |
d3bef15f | 6731 | return kvm_emulate_halt(vcpu); |
6aa8b732 AK |
6732 | } |
6733 | ||
851ba692 | 6734 | static int handle_vmcall(struct kvm_vcpu *vcpu) |
c21415e8 | 6735 | { |
0d9c055e | 6736 | return kvm_emulate_hypercall(vcpu); |
c21415e8 IM |
6737 | } |
6738 | ||
ec25d5e6 GN |
6739 | static int handle_invd(struct kvm_vcpu *vcpu) |
6740 | { | |
51d8b661 | 6741 | return emulate_instruction(vcpu, 0) == EMULATE_DONE; |
ec25d5e6 GN |
6742 | } |
6743 | ||
851ba692 | 6744 | static int handle_invlpg(struct kvm_vcpu *vcpu) |
a7052897 | 6745 | { |
f9c617f6 | 6746 | unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); |
a7052897 MT |
6747 | |
6748 | kvm_mmu_invlpg(vcpu, exit_qualification); | |
6affcbed | 6749 | return kvm_skip_emulated_instruction(vcpu); |
a7052897 MT |
6750 | } |
6751 | ||
fee84b07 AK |
6752 | static int handle_rdpmc(struct kvm_vcpu *vcpu) |
6753 | { | |
6754 | int err; | |
6755 | ||
6756 | err = kvm_rdpmc(vcpu); | |
6affcbed | 6757 | return kvm_complete_insn_gp(vcpu, err); |
fee84b07 AK |
6758 | } |
6759 | ||
851ba692 | 6760 | static int handle_wbinvd(struct kvm_vcpu *vcpu) |
e5edaa01 | 6761 | { |
6affcbed | 6762 | return kvm_emulate_wbinvd(vcpu); |
e5edaa01 ED |
6763 | } |
6764 | ||
2acf923e DC |
6765 | static int handle_xsetbv(struct kvm_vcpu *vcpu) |
6766 | { | |
6767 | u64 new_bv = kvm_read_edx_eax(vcpu); | |
6768 | u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX); | |
6769 | ||
6770 | if (kvm_set_xcr(vcpu, index, new_bv) == 0) | |
6affcbed | 6771 | return kvm_skip_emulated_instruction(vcpu); |
2acf923e DC |
6772 | return 1; |
6773 | } | |
6774 | ||
f53cd63c WL |
6775 | static int handle_xsaves(struct kvm_vcpu *vcpu) |
6776 | { | |
6affcbed | 6777 | kvm_skip_emulated_instruction(vcpu); |
f53cd63c WL |
6778 | WARN(1, "this should never happen\n"); |
6779 | return 1; | |
6780 | } | |
6781 | ||
6782 | static int handle_xrstors(struct kvm_vcpu *vcpu) | |
6783 | { | |
6affcbed | 6784 | kvm_skip_emulated_instruction(vcpu); |
f53cd63c WL |
6785 | WARN(1, "this should never happen\n"); |
6786 | return 1; | |
6787 | } | |
6788 | ||
851ba692 | 6789 | static int handle_apic_access(struct kvm_vcpu *vcpu) |
f78e0e2e | 6790 | { |
58fbbf26 KT |
6791 | if (likely(fasteoi)) { |
6792 | unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
6793 | int access_type, offset; | |
6794 | ||
6795 | access_type = exit_qualification & APIC_ACCESS_TYPE; | |
6796 | offset = exit_qualification & APIC_ACCESS_OFFSET; | |
6797 | /* | |
6798 | * Sane guest uses MOV to write EOI, with written value | |
6799 | * not cared. So make a short-circuit here by avoiding | |
6800 | * heavy instruction emulation. | |
6801 | */ | |
6802 | if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) && | |
6803 | (offset == APIC_EOI)) { | |
6804 | kvm_lapic_set_eoi(vcpu); | |
6affcbed | 6805 | return kvm_skip_emulated_instruction(vcpu); |
58fbbf26 KT |
6806 | } |
6807 | } | |
51d8b661 | 6808 | return emulate_instruction(vcpu, 0) == EMULATE_DONE; |
f78e0e2e SY |
6809 | } |
6810 | ||
c7c9c56c YZ |
6811 | static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu) |
6812 | { | |
6813 | unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
6814 | int vector = exit_qualification & 0xff; | |
6815 | ||
6816 | /* EOI-induced VM exit is trap-like and thus no need to adjust IP */ | |
6817 | kvm_apic_set_eoi_accelerated(vcpu, vector); | |
6818 | return 1; | |
6819 | } | |
6820 | ||
83d4c286 YZ |
6821 | static int handle_apic_write(struct kvm_vcpu *vcpu) |
6822 | { | |
6823 | unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
6824 | u32 offset = exit_qualification & 0xfff; | |
6825 | ||
6826 | /* APIC-write VM exit is trap-like and thus no need to adjust IP */ | |
6827 | kvm_apic_write_nodecode(vcpu, offset); | |
6828 | return 1; | |
6829 | } | |
6830 | ||
851ba692 | 6831 | static int handle_task_switch(struct kvm_vcpu *vcpu) |
37817f29 | 6832 | { |
60637aac | 6833 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
37817f29 | 6834 | unsigned long exit_qualification; |
e269fb21 JK |
6835 | bool has_error_code = false; |
6836 | u32 error_code = 0; | |
37817f29 | 6837 | u16 tss_selector; |
7f3d35fd | 6838 | int reason, type, idt_v, idt_index; |
64a7ec06 GN |
6839 | |
6840 | idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK); | |
7f3d35fd | 6841 | idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK); |
64a7ec06 | 6842 | type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK); |
37817f29 IE |
6843 | |
6844 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
6845 | ||
6846 | reason = (u32)exit_qualification >> 30; | |
64a7ec06 GN |
6847 | if (reason == TASK_SWITCH_GATE && idt_v) { |
6848 | switch (type) { | |
6849 | case INTR_TYPE_NMI_INTR: | |
6850 | vcpu->arch.nmi_injected = false; | |
654f06fc | 6851 | vmx_set_nmi_mask(vcpu, true); |
64a7ec06 GN |
6852 | break; |
6853 | case INTR_TYPE_EXT_INTR: | |
66fd3f7f | 6854 | case INTR_TYPE_SOFT_INTR: |
64a7ec06 GN |
6855 | kvm_clear_interrupt_queue(vcpu); |
6856 | break; | |
6857 | case INTR_TYPE_HARD_EXCEPTION: | |
e269fb21 JK |
6858 | if (vmx->idt_vectoring_info & |
6859 | VECTORING_INFO_DELIVER_CODE_MASK) { | |
6860 | has_error_code = true; | |
6861 | error_code = | |
6862 | vmcs_read32(IDT_VECTORING_ERROR_CODE); | |
6863 | } | |
6864 | /* fall through */ | |
64a7ec06 GN |
6865 | case INTR_TYPE_SOFT_EXCEPTION: |
6866 | kvm_clear_exception_queue(vcpu); | |
6867 | break; | |
6868 | default: | |
6869 | break; | |
6870 | } | |
60637aac | 6871 | } |
37817f29 IE |
6872 | tss_selector = exit_qualification; |
6873 | ||
64a7ec06 GN |
6874 | if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION && |
6875 | type != INTR_TYPE_EXT_INTR && | |
6876 | type != INTR_TYPE_NMI_INTR)) | |
6877 | skip_emulated_instruction(vcpu); | |
6878 | ||
7f3d35fd KW |
6879 | if (kvm_task_switch(vcpu, tss_selector, |
6880 | type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason, | |
6881 | has_error_code, error_code) == EMULATE_FAIL) { | |
acb54517 GN |
6882 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; |
6883 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
6884 | vcpu->run->internal.ndata = 0; | |
42dbaa5a | 6885 | return 0; |
acb54517 | 6886 | } |
42dbaa5a | 6887 | |
42dbaa5a JK |
6888 | /* |
6889 | * TODO: What about debug traps on tss switch? | |
6890 | * Are we supposed to inject them and update dr6? | |
6891 | */ | |
6892 | ||
6893 | return 1; | |
37817f29 IE |
6894 | } |
6895 | ||
851ba692 | 6896 | static int handle_ept_violation(struct kvm_vcpu *vcpu) |
1439442c | 6897 | { |
f9c617f6 | 6898 | unsigned long exit_qualification; |
1439442c | 6899 | gpa_t gpa; |
eebed243 | 6900 | u64 error_code; |
1439442c | 6901 | |
f9c617f6 | 6902 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); |
1439442c | 6903 | |
0be9c7a8 GN |
6904 | /* |
6905 | * EPT violation happened while executing iret from NMI, | |
6906 | * "blocked by NMI" bit has to be set before next VM entry. | |
6907 | * There are errata that may cause this bit to not be set: | |
6908 | * AAK134, BY25. | |
6909 | */ | |
bcd1c294 | 6910 | if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) && |
d02fcf50 | 6911 | enable_vnmi && |
bcd1c294 | 6912 | (exit_qualification & INTR_INFO_UNBLOCK_NMI)) |
0be9c7a8 GN |
6913 | vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI); |
6914 | ||
1439442c | 6915 | gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS); |
229456fc | 6916 | trace_kvm_page_fault(gpa, exit_qualification); |
4f5982a5 | 6917 | |
27959a44 | 6918 | /* Is it a read fault? */ |
ab22a473 | 6919 | error_code = (exit_qualification & EPT_VIOLATION_ACC_READ) |
27959a44 JS |
6920 | ? PFERR_USER_MASK : 0; |
6921 | /* Is it a write fault? */ | |
ab22a473 | 6922 | error_code |= (exit_qualification & EPT_VIOLATION_ACC_WRITE) |
27959a44 JS |
6923 | ? PFERR_WRITE_MASK : 0; |
6924 | /* Is it a fetch fault? */ | |
ab22a473 | 6925 | error_code |= (exit_qualification & EPT_VIOLATION_ACC_INSTR) |
27959a44 JS |
6926 | ? PFERR_FETCH_MASK : 0; |
6927 | /* ept page table entry is present? */ | |
6928 | error_code |= (exit_qualification & | |
6929 | (EPT_VIOLATION_READABLE | EPT_VIOLATION_WRITABLE | | |
6930 | EPT_VIOLATION_EXECUTABLE)) | |
6931 | ? PFERR_PRESENT_MASK : 0; | |
4f5982a5 | 6932 | |
eebed243 PB |
6933 | error_code |= (exit_qualification & 0x100) != 0 ? |
6934 | PFERR_GUEST_FINAL_MASK : PFERR_GUEST_PAGE_MASK; | |
25d92081 | 6935 | |
25d92081 | 6936 | vcpu->arch.exit_qualification = exit_qualification; |
4f5982a5 | 6937 | return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0); |
1439442c SY |
6938 | } |
6939 | ||
851ba692 | 6940 | static int handle_ept_misconfig(struct kvm_vcpu *vcpu) |
68f89400 | 6941 | { |
f735d4af | 6942 | int ret; |
68f89400 MT |
6943 | gpa_t gpa; |
6944 | ||
9034e6e8 PB |
6945 | /* |
6946 | * A nested guest cannot optimize MMIO vmexits, because we have an | |
6947 | * nGPA here instead of the required GPA. | |
6948 | */ | |
68f89400 | 6949 | gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS); |
9034e6e8 PB |
6950 | if (!is_guest_mode(vcpu) && |
6951 | !kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) { | |
931c33b1 | 6952 | trace_kvm_fast_mmio(gpa); |
60165b0a VK |
6953 | /* |
6954 | * Doing kvm_skip_emulated_instruction() depends on undefined | |
6955 | * behavior: Intel's manual doesn't mandate | |
6956 | * VM_EXIT_INSTRUCTION_LEN to be set in VMCS when EPT MISCONFIG | |
6957 | * occurs and while on real hardware it was observed to be set, | |
6958 | * other hypervisors (namely Hyper-V) don't set it, we end up | |
6959 | * advancing IP with some random value. Disable fast mmio when | |
6960 | * running nested and keep it for real hardware in hope that | |
6961 | * VM_EXIT_INSTRUCTION_LEN will always be set correctly. | |
6962 | */ | |
6963 | if (!static_cpu_has(X86_FEATURE_HYPERVISOR)) | |
6964 | return kvm_skip_emulated_instruction(vcpu); | |
6965 | else | |
90a488b3 SC |
6966 | return emulate_instruction(vcpu, EMULTYPE_SKIP) == |
6967 | EMULATE_DONE; | |
68c3b4d1 | 6968 | } |
68f89400 | 6969 | |
e08d26f0 PB |
6970 | ret = kvm_mmu_page_fault(vcpu, gpa, PFERR_RSVD_MASK, NULL, 0); |
6971 | if (ret >= 0) | |
6972 | return ret; | |
ce88decf XG |
6973 | |
6974 | /* It is the real ept misconfig */ | |
f735d4af | 6975 | WARN_ON(1); |
68f89400 | 6976 | |
851ba692 AK |
6977 | vcpu->run->exit_reason = KVM_EXIT_UNKNOWN; |
6978 | vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG; | |
68f89400 MT |
6979 | |
6980 | return 0; | |
6981 | } | |
6982 | ||
851ba692 | 6983 | static int handle_nmi_window(struct kvm_vcpu *vcpu) |
f08864b4 | 6984 | { |
d02fcf50 | 6985 | WARN_ON_ONCE(!enable_vnmi); |
47c0152e PB |
6986 | vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL, |
6987 | CPU_BASED_VIRTUAL_NMI_PENDING); | |
f08864b4 | 6988 | ++vcpu->stat.nmi_window_exits; |
3842d135 | 6989 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
f08864b4 SY |
6990 | |
6991 | return 1; | |
6992 | } | |
6993 | ||
80ced186 | 6994 | static int handle_invalid_guest_state(struct kvm_vcpu *vcpu) |
ea953ef0 | 6995 | { |
8b3079a5 AK |
6996 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
6997 | enum emulation_result err = EMULATE_DONE; | |
80ced186 | 6998 | int ret = 1; |
49e9d557 AK |
6999 | u32 cpu_exec_ctrl; |
7000 | bool intr_window_requested; | |
b8405c18 | 7001 | unsigned count = 130; |
49e9d557 AK |
7002 | |
7003 | cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); | |
7004 | intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING; | |
ea953ef0 | 7005 | |
98eb2f8b | 7006 | while (vmx->emulation_required && count-- != 0) { |
bdea48e3 | 7007 | if (intr_window_requested && vmx_interrupt_allowed(vcpu)) |
49e9d557 AK |
7008 | return handle_interrupt_window(&vmx->vcpu); |
7009 | ||
72875d8a | 7010 | if (kvm_test_request(KVM_REQ_EVENT, vcpu)) |
de87dcdd AK |
7011 | return 1; |
7012 | ||
9b8ae637 | 7013 | err = emulate_instruction(vcpu, 0); |
ea953ef0 | 7014 | |
ac0a48c3 | 7015 | if (err == EMULATE_USER_EXIT) { |
94452b9e | 7016 | ++vcpu->stat.mmio_exits; |
80ced186 MG |
7017 | ret = 0; |
7018 | goto out; | |
7019 | } | |
1d5a4d9b | 7020 | |
299f0328 SC |
7021 | if (err != EMULATE_DONE) |
7022 | goto emulation_error; | |
7023 | ||
7024 | if (vmx->emulation_required && !vmx->rmode.vm86_active && | |
7025 | vcpu->arch.exception.pending) | |
7026 | goto emulation_error; | |
ea953ef0 | 7027 | |
8d76c49e GN |
7028 | if (vcpu->arch.halt_request) { |
7029 | vcpu->arch.halt_request = 0; | |
5cb56059 | 7030 | ret = kvm_vcpu_halt(vcpu); |
8d76c49e GN |
7031 | goto out; |
7032 | } | |
7033 | ||
ea953ef0 | 7034 | if (signal_pending(current)) |
80ced186 | 7035 | goto out; |
ea953ef0 MG |
7036 | if (need_resched()) |
7037 | schedule(); | |
7038 | } | |
7039 | ||
80ced186 MG |
7040 | out: |
7041 | return ret; | |
299f0328 SC |
7042 | |
7043 | emulation_error: | |
7044 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
7045 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
7046 | vcpu->run->internal.ndata = 0; | |
7047 | return 0; | |
ea953ef0 MG |
7048 | } |
7049 | ||
b4a2d31d RK |
7050 | static int __grow_ple_window(int val) |
7051 | { | |
7052 | if (ple_window_grow < 1) | |
7053 | return ple_window; | |
7054 | ||
7055 | val = min(val, ple_window_actual_max); | |
7056 | ||
7057 | if (ple_window_grow < ple_window) | |
7058 | val *= ple_window_grow; | |
7059 | else | |
7060 | val += ple_window_grow; | |
7061 | ||
7062 | return val; | |
7063 | } | |
7064 | ||
7065 | static int __shrink_ple_window(int val, int modifier, int minimum) | |
7066 | { | |
7067 | if (modifier < 1) | |
7068 | return ple_window; | |
7069 | ||
7070 | if (modifier < ple_window) | |
7071 | val /= modifier; | |
7072 | else | |
7073 | val -= modifier; | |
7074 | ||
7075 | return max(val, minimum); | |
7076 | } | |
7077 | ||
7078 | static void grow_ple_window(struct kvm_vcpu *vcpu) | |
7079 | { | |
7080 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
7081 | int old = vmx->ple_window; | |
7082 | ||
7083 | vmx->ple_window = __grow_ple_window(old); | |
7084 | ||
7085 | if (vmx->ple_window != old) | |
7086 | vmx->ple_window_dirty = true; | |
7b46268d RK |
7087 | |
7088 | trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old); | |
b4a2d31d RK |
7089 | } |
7090 | ||
7091 | static void shrink_ple_window(struct kvm_vcpu *vcpu) | |
7092 | { | |
7093 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
7094 | int old = vmx->ple_window; | |
7095 | ||
7096 | vmx->ple_window = __shrink_ple_window(old, | |
7097 | ple_window_shrink, ple_window); | |
7098 | ||
7099 | if (vmx->ple_window != old) | |
7100 | vmx->ple_window_dirty = true; | |
7b46268d RK |
7101 | |
7102 | trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old); | |
b4a2d31d RK |
7103 | } |
7104 | ||
7105 | /* | |
7106 | * ple_window_actual_max is computed to be one grow_ple_window() below | |
7107 | * ple_window_max. (See __grow_ple_window for the reason.) | |
7108 | * This prevents overflows, because ple_window_max is int. | |
7109 | * ple_window_max effectively rounded down to a multiple of ple_window_grow in | |
7110 | * this process. | |
7111 | * ple_window_max is also prevented from setting vmx->ple_window < ple_window. | |
7112 | */ | |
7113 | static void update_ple_window_actual_max(void) | |
7114 | { | |
7115 | ple_window_actual_max = | |
7116 | __shrink_ple_window(max(ple_window_max, ple_window), | |
7117 | ple_window_grow, INT_MIN); | |
7118 | } | |
7119 | ||
bf9f6ac8 FW |
7120 | /* |
7121 | * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR. | |
7122 | */ | |
7123 | static void wakeup_handler(void) | |
7124 | { | |
7125 | struct kvm_vcpu *vcpu; | |
7126 | int cpu = smp_processor_id(); | |
7127 | ||
7128 | spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu)); | |
7129 | list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu), | |
7130 | blocked_vcpu_list) { | |
7131 | struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); | |
7132 | ||
7133 | if (pi_test_on(pi_desc) == 1) | |
7134 | kvm_vcpu_kick(vcpu); | |
7135 | } | |
7136 | spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu)); | |
7137 | } | |
7138 | ||
f160c7b7 JS |
7139 | void vmx_enable_tdp(void) |
7140 | { | |
7141 | kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK, | |
7142 | enable_ept_ad_bits ? VMX_EPT_ACCESS_BIT : 0ull, | |
7143 | enable_ept_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull, | |
7144 | 0ull, VMX_EPT_EXECUTABLE_MASK, | |
7145 | cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK, | |
d0ec49d4 | 7146 | VMX_EPT_RWX_MASK, 0ull); |
f160c7b7 JS |
7147 | |
7148 | ept_set_mmio_spte_mask(); | |
7149 | kvm_enable_tdp(); | |
7150 | } | |
7151 | ||
f2c7648d TC |
7152 | static __init int hardware_setup(void) |
7153 | { | |
4b0be90f | 7154 | int r = -ENOMEM, i; |
34a1cd60 TC |
7155 | |
7156 | rdmsrl_safe(MSR_EFER, &host_efer); | |
7157 | ||
7158 | for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) | |
7159 | kvm_define_shared_msr(i, vmx_msr_index[i]); | |
7160 | ||
23611332 RK |
7161 | for (i = 0; i < VMX_BITMAP_NR; i++) { |
7162 | vmx_bitmap[i] = (unsigned long *)__get_free_page(GFP_KERNEL); | |
7163 | if (!vmx_bitmap[i]) | |
7164 | goto out; | |
7165 | } | |
34a1cd60 | 7166 | |
34a1cd60 TC |
7167 | memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE); |
7168 | memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE); | |
7169 | ||
34a1cd60 | 7170 | memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE); |
34a1cd60 TC |
7171 | |
7172 | memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE); | |
7173 | ||
34a1cd60 TC |
7174 | if (setup_vmcs_config(&vmcs_config) < 0) { |
7175 | r = -EIO; | |
23611332 | 7176 | goto out; |
baa03522 | 7177 | } |
f2c7648d TC |
7178 | |
7179 | if (boot_cpu_has(X86_FEATURE_NX)) | |
7180 | kvm_enable_efer_bits(EFER_NX); | |
7181 | ||
08d839c4 WL |
7182 | if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() || |
7183 | !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global())) | |
f2c7648d | 7184 | enable_vpid = 0; |
08d839c4 | 7185 | |
f2c7648d TC |
7186 | if (!cpu_has_vmx_shadow_vmcs()) |
7187 | enable_shadow_vmcs = 0; | |
7188 | if (enable_shadow_vmcs) | |
7189 | init_vmcs_shadow_fields(); | |
7190 | ||
7191 | if (!cpu_has_vmx_ept() || | |
42aa53b4 | 7192 | !cpu_has_vmx_ept_4levels() || |
f5f51586 | 7193 | !cpu_has_vmx_ept_mt_wb() || |
8ad8182e | 7194 | !cpu_has_vmx_invept_global()) |
f2c7648d | 7195 | enable_ept = 0; |
f2c7648d | 7196 | |
fce6ac4c | 7197 | if (!cpu_has_vmx_ept_ad_bits() || !enable_ept) |
f2c7648d TC |
7198 | enable_ept_ad_bits = 0; |
7199 | ||
8ad8182e | 7200 | if (!cpu_has_vmx_unrestricted_guest() || !enable_ept) |
f2c7648d TC |
7201 | enable_unrestricted_guest = 0; |
7202 | ||
ad15a296 | 7203 | if (!cpu_has_vmx_flexpriority()) |
f2c7648d TC |
7204 | flexpriority_enabled = 0; |
7205 | ||
d02fcf50 PB |
7206 | if (!cpu_has_virtual_nmis()) |
7207 | enable_vnmi = 0; | |
7208 | ||
ad15a296 PB |
7209 | /* |
7210 | * set_apic_access_page_addr() is used to reload apic access | |
7211 | * page upon invalidation. No need to do anything if not | |
7212 | * using the APIC_ACCESS_ADDR VMCS field. | |
7213 | */ | |
7214 | if (!flexpriority_enabled) | |
f2c7648d | 7215 | kvm_x86_ops->set_apic_access_page_addr = NULL; |
f2c7648d TC |
7216 | |
7217 | if (!cpu_has_vmx_tpr_shadow()) | |
7218 | kvm_x86_ops->update_cr8_intercept = NULL; | |
7219 | ||
7220 | if (enable_ept && !cpu_has_vmx_ept_2m_page()) | |
7221 | kvm_disable_largepages(); | |
7222 | ||
0f107682 | 7223 | if (!cpu_has_vmx_ple()) { |
f2c7648d | 7224 | ple_gap = 0; |
0f107682 WL |
7225 | ple_window = 0; |
7226 | ple_window_grow = 0; | |
7227 | ple_window_max = 0; | |
7228 | ple_window_shrink = 0; | |
7229 | } | |
f2c7648d | 7230 | |
76dfafd5 | 7231 | if (!cpu_has_vmx_apicv()) { |
f2c7648d | 7232 | enable_apicv = 0; |
76dfafd5 PB |
7233 | kvm_x86_ops->sync_pir_to_irr = NULL; |
7234 | } | |
f2c7648d | 7235 | |
64903d61 HZ |
7236 | if (cpu_has_vmx_tsc_scaling()) { |
7237 | kvm_has_tsc_control = true; | |
7238 | kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX; | |
7239 | kvm_tsc_scaling_ratio_frac_bits = 48; | |
7240 | } | |
7241 | ||
04bb92e4 WL |
7242 | set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */ |
7243 | ||
f160c7b7 JS |
7244 | if (enable_ept) |
7245 | vmx_enable_tdp(); | |
7246 | else | |
baa03522 TC |
7247 | kvm_disable_tdp(); |
7248 | ||
7249 | update_ple_window_actual_max(); | |
7250 | ||
843e4330 KH |
7251 | /* |
7252 | * Only enable PML when hardware supports PML feature, and both EPT | |
7253 | * and EPT A/D bit features are enabled -- PML depends on them to work. | |
7254 | */ | |
7255 | if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml()) | |
7256 | enable_pml = 0; | |
7257 | ||
7258 | if (!enable_pml) { | |
7259 | kvm_x86_ops->slot_enable_log_dirty = NULL; | |
7260 | kvm_x86_ops->slot_disable_log_dirty = NULL; | |
7261 | kvm_x86_ops->flush_log_dirty = NULL; | |
7262 | kvm_x86_ops->enable_log_dirty_pt_masked = NULL; | |
7263 | } | |
7264 | ||
64672c95 YJ |
7265 | if (cpu_has_vmx_preemption_timer() && enable_preemption_timer) { |
7266 | u64 vmx_msr; | |
7267 | ||
7268 | rdmsrl(MSR_IA32_VMX_MISC, vmx_msr); | |
7269 | cpu_preemption_timer_multi = | |
7270 | vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK; | |
7271 | } else { | |
7272 | kvm_x86_ops->set_hv_timer = NULL; | |
7273 | kvm_x86_ops->cancel_hv_timer = NULL; | |
7274 | } | |
7275 | ||
bf9f6ac8 FW |
7276 | kvm_set_posted_intr_wakeup_handler(wakeup_handler); |
7277 | ||
c45dcc71 AR |
7278 | kvm_mce_cap_supported |= MCG_LMCE_P; |
7279 | ||
2b8d8b33 SC |
7280 | r = alloc_kvm_area(); |
7281 | if (r) | |
7282 | goto out; | |
7283 | return 0; | |
34a1cd60 | 7284 | |
34a1cd60 | 7285 | out: |
23611332 RK |
7286 | for (i = 0; i < VMX_BITMAP_NR; i++) |
7287 | free_page((unsigned long)vmx_bitmap[i]); | |
34a1cd60 | 7288 | |
2b8d8b33 | 7289 | return r; |
f2c7648d TC |
7290 | } |
7291 | ||
7292 | static __exit void hardware_unsetup(void) | |
7293 | { | |
23611332 RK |
7294 | int i; |
7295 | ||
7296 | for (i = 0; i < VMX_BITMAP_NR; i++) | |
7297 | free_page((unsigned long)vmx_bitmap[i]); | |
34a1cd60 | 7298 | |
f2c7648d TC |
7299 | free_kvm_area(); |
7300 | } | |
7301 | ||
4b8d54f9 ZE |
7302 | /* |
7303 | * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE | |
7304 | * exiting, so only get here on cpu with PAUSE-Loop-Exiting. | |
7305 | */ | |
9fb41ba8 | 7306 | static int handle_pause(struct kvm_vcpu *vcpu) |
4b8d54f9 | 7307 | { |
b4a2d31d RK |
7308 | if (ple_gap) |
7309 | grow_ple_window(vcpu); | |
7310 | ||
de63ad4c LM |
7311 | /* |
7312 | * Intel sdm vol3 ch-25.1.3 says: The "PAUSE-loop exiting" | |
7313 | * VM-execution control is ignored if CPL > 0. OTOH, KVM | |
7314 | * never set PAUSE_EXITING and just set PLE if supported, | |
7315 | * so the vcpu must be CPL=0 if it gets a PAUSE exit. | |
7316 | */ | |
7317 | kvm_vcpu_on_spin(vcpu, true); | |
6affcbed | 7318 | return kvm_skip_emulated_instruction(vcpu); |
4b8d54f9 ZE |
7319 | } |
7320 | ||
87c00572 | 7321 | static int handle_nop(struct kvm_vcpu *vcpu) |
59708670 | 7322 | { |
6affcbed | 7323 | return kvm_skip_emulated_instruction(vcpu); |
59708670 SY |
7324 | } |
7325 | ||
87c00572 GS |
7326 | static int handle_mwait(struct kvm_vcpu *vcpu) |
7327 | { | |
7328 | printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n"); | |
7329 | return handle_nop(vcpu); | |
7330 | } | |
7331 | ||
45ec368c JM |
7332 | static int handle_invalid_op(struct kvm_vcpu *vcpu) |
7333 | { | |
7334 | kvm_queue_exception(vcpu, UD_VECTOR); | |
7335 | return 1; | |
7336 | } | |
7337 | ||
5f3d45e7 MD |
7338 | static int handle_monitor_trap(struct kvm_vcpu *vcpu) |
7339 | { | |
7340 | return 1; | |
7341 | } | |
7342 | ||
87c00572 GS |
7343 | static int handle_monitor(struct kvm_vcpu *vcpu) |
7344 | { | |
7345 | printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n"); | |
7346 | return handle_nop(vcpu); | |
7347 | } | |
7348 | ||
0658fbaa ACL |
7349 | /* |
7350 | * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(), | |
7351 | * set the success or error code of an emulated VMX instruction, as specified | |
7352 | * by Vol 2B, VMX Instruction Reference, "Conventions". | |
7353 | */ | |
7354 | static void nested_vmx_succeed(struct kvm_vcpu *vcpu) | |
7355 | { | |
7356 | vmx_set_rflags(vcpu, vmx_get_rflags(vcpu) | |
7357 | & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF | | |
7358 | X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF)); | |
7359 | } | |
7360 | ||
7361 | static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu) | |
7362 | { | |
7363 | vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu) | |
7364 | & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF | | |
7365 | X86_EFLAGS_SF | X86_EFLAGS_OF)) | |
7366 | | X86_EFLAGS_CF); | |
7367 | } | |
7368 | ||
145c28dd | 7369 | static void nested_vmx_failValid(struct kvm_vcpu *vcpu, |
0658fbaa ACL |
7370 | u32 vm_instruction_error) |
7371 | { | |
7372 | if (to_vmx(vcpu)->nested.current_vmptr == -1ull) { | |
7373 | /* | |
7374 | * failValid writes the error number to the current VMCS, which | |
7375 | * can't be done there isn't a current VMCS. | |
7376 | */ | |
7377 | nested_vmx_failInvalid(vcpu); | |
7378 | return; | |
7379 | } | |
7380 | vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu) | |
7381 | & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF | | |
7382 | X86_EFLAGS_SF | X86_EFLAGS_OF)) | |
7383 | | X86_EFLAGS_ZF); | |
7384 | get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error; | |
7385 | /* | |
7386 | * We don't need to force a shadow sync because | |
7387 | * VM_INSTRUCTION_ERROR is not shadowed | |
7388 | */ | |
7389 | } | |
145c28dd | 7390 | |
ff651cb6 WV |
7391 | static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator) |
7392 | { | |
7393 | /* TODO: not to reset guest simply here. */ | |
7394 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); | |
bbe41b95 | 7395 | pr_debug_ratelimited("kvm: nested vmx abort, indicator %d\n", indicator); |
ff651cb6 WV |
7396 | } |
7397 | ||
f4124500 JK |
7398 | static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer) |
7399 | { | |
7400 | struct vcpu_vmx *vmx = | |
7401 | container_of(timer, struct vcpu_vmx, nested.preemption_timer); | |
7402 | ||
7403 | vmx->nested.preemption_timer_expired = true; | |
7404 | kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu); | |
7405 | kvm_vcpu_kick(&vmx->vcpu); | |
7406 | ||
7407 | return HRTIMER_NORESTART; | |
7408 | } | |
7409 | ||
19677e32 BD |
7410 | /* |
7411 | * Decode the memory-address operand of a vmx instruction, as recorded on an | |
7412 | * exit caused by such an instruction (run by a guest hypervisor). | |
7413 | * On success, returns 0. When the operand is invalid, returns 1 and throws | |
7414 | * #UD or #GP. | |
7415 | */ | |
7416 | static int get_vmx_mem_address(struct kvm_vcpu *vcpu, | |
7417 | unsigned long exit_qualification, | |
f9eb4af6 | 7418 | u32 vmx_instruction_info, bool wr, gva_t *ret) |
19677e32 | 7419 | { |
f9eb4af6 EK |
7420 | gva_t off; |
7421 | bool exn; | |
7422 | struct kvm_segment s; | |
7423 | ||
19677e32 BD |
7424 | /* |
7425 | * According to Vol. 3B, "Information for VM Exits Due to Instruction | |
7426 | * Execution", on an exit, vmx_instruction_info holds most of the | |
7427 | * addressing components of the operand. Only the displacement part | |
7428 | * is put in exit_qualification (see 3B, "Basic VM-Exit Information"). | |
7429 | * For how an actual address is calculated from all these components, | |
7430 | * refer to Vol. 1, "Operand Addressing". | |
7431 | */ | |
7432 | int scaling = vmx_instruction_info & 3; | |
7433 | int addr_size = (vmx_instruction_info >> 7) & 7; | |
7434 | bool is_reg = vmx_instruction_info & (1u << 10); | |
7435 | int seg_reg = (vmx_instruction_info >> 15) & 7; | |
7436 | int index_reg = (vmx_instruction_info >> 18) & 0xf; | |
7437 | bool index_is_valid = !(vmx_instruction_info & (1u << 22)); | |
7438 | int base_reg = (vmx_instruction_info >> 23) & 0xf; | |
7439 | bool base_is_valid = !(vmx_instruction_info & (1u << 27)); | |
7440 | ||
7441 | if (is_reg) { | |
7442 | kvm_queue_exception(vcpu, UD_VECTOR); | |
7443 | return 1; | |
7444 | } | |
7445 | ||
7446 | /* Addr = segment_base + offset */ | |
7447 | /* offset = base + [index * scale] + displacement */ | |
f9eb4af6 | 7448 | off = exit_qualification; /* holds the displacement */ |
4f7d4d74 SC |
7449 | if (addr_size == 1) |
7450 | off = (gva_t)sign_extend64(off, 31); | |
7451 | else if (addr_size == 0) | |
7452 | off = (gva_t)sign_extend64(off, 15); | |
19677e32 | 7453 | if (base_is_valid) |
f9eb4af6 | 7454 | off += kvm_register_read(vcpu, base_reg); |
19677e32 | 7455 | if (index_is_valid) |
f9eb4af6 EK |
7456 | off += kvm_register_read(vcpu, index_reg)<<scaling; |
7457 | vmx_get_segment(vcpu, &s, seg_reg); | |
19677e32 | 7458 | |
fedc84f4 SC |
7459 | /* |
7460 | * The effective address, i.e. @off, of a memory operand is truncated | |
7461 | * based on the address size of the instruction. Note that this is | |
7462 | * the *effective address*, i.e. the address prior to accounting for | |
7463 | * the segment's base. | |
7464 | */ | |
19677e32 | 7465 | if (addr_size == 1) /* 32 bit */ |
fedc84f4 SC |
7466 | off &= 0xffffffff; |
7467 | else if (addr_size == 0) /* 16 bit */ | |
7468 | off &= 0xffff; | |
19677e32 | 7469 | |
f9eb4af6 EK |
7470 | /* Checks for #GP/#SS exceptions. */ |
7471 | exn = false; | |
ff30ef40 | 7472 | if (is_long_mode(vcpu)) { |
fedc84f4 SC |
7473 | /* |
7474 | * The virtual/linear address is never truncated in 64-bit | |
7475 | * mode, e.g. a 32-bit address size can yield a 64-bit virtual | |
7476 | * address when using FS/GS with a non-zero base. | |
7477 | */ | |
7478 | *ret = s.base + off; | |
7479 | ||
ff30ef40 QC |
7480 | /* Long mode: #GP(0)/#SS(0) if the memory address is in a |
7481 | * non-canonical form. This is the only check on the memory | |
7482 | * destination for long mode! | |
7483 | */ | |
fd8cb433 | 7484 | exn = is_noncanonical_address(*ret, vcpu); |
ff30ef40 | 7485 | } else if (is_protmode(vcpu)) { |
fedc84f4 SC |
7486 | /* |
7487 | * When not in long mode, the virtual/linear address is | |
7488 | * unconditionally truncated to 32 bits regardless of the | |
7489 | * address size. | |
7490 | */ | |
7491 | *ret = (s.base + off) & 0xffffffff; | |
7492 | ||
f9eb4af6 EK |
7493 | /* Protected mode: apply checks for segment validity in the |
7494 | * following order: | |
7495 | * - segment type check (#GP(0) may be thrown) | |
7496 | * - usability check (#GP(0)/#SS(0)) | |
7497 | * - limit check (#GP(0)/#SS(0)) | |
7498 | */ | |
7499 | if (wr) | |
7500 | /* #GP(0) if the destination operand is located in a | |
7501 | * read-only data segment or any code segment. | |
7502 | */ | |
7503 | exn = ((s.type & 0xa) == 0 || (s.type & 8)); | |
7504 | else | |
7505 | /* #GP(0) if the source operand is located in an | |
7506 | * execute-only code segment | |
7507 | */ | |
7508 | exn = ((s.type & 0xa) == 8); | |
ff30ef40 QC |
7509 | if (exn) { |
7510 | kvm_queue_exception_e(vcpu, GP_VECTOR, 0); | |
7511 | return 1; | |
7512 | } | |
f9eb4af6 EK |
7513 | /* Protected mode: #GP(0)/#SS(0) if the segment is unusable. |
7514 | */ | |
7515 | exn = (s.unusable != 0); | |
05787d1f SC |
7516 | |
7517 | /* | |
7518 | * Protected mode: #GP(0)/#SS(0) if the memory operand is | |
7519 | * outside the segment limit. All CPUs that support VMX ignore | |
7520 | * limit checks for flat segments, i.e. segments with base==0, | |
7521 | * limit==0xffffffff and of type expand-up data or code. | |
f9eb4af6 | 7522 | */ |
05787d1f SC |
7523 | if (!(s.base == 0 && s.limit == 0xffffffff && |
7524 | ((s.type & 8) || !(s.type & 4)))) | |
7525 | exn = exn || (off + sizeof(u64) > s.limit); | |
f9eb4af6 EK |
7526 | } |
7527 | if (exn) { | |
7528 | kvm_queue_exception_e(vcpu, | |
7529 | seg_reg == VCPU_SREG_SS ? | |
7530 | SS_VECTOR : GP_VECTOR, | |
7531 | 0); | |
7532 | return 1; | |
7533 | } | |
7534 | ||
19677e32 BD |
7535 | return 0; |
7536 | } | |
7537 | ||
cbf71279 | 7538 | static int nested_vmx_get_vmptr(struct kvm_vcpu *vcpu, gpa_t *vmpointer) |
3573e22c BD |
7539 | { |
7540 | gva_t gva; | |
3573e22c | 7541 | struct x86_exception e; |
3573e22c BD |
7542 | |
7543 | if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION), | |
f9eb4af6 | 7544 | vmcs_read32(VMX_INSTRUCTION_INFO), false, &gva)) |
3573e22c BD |
7545 | return 1; |
7546 | ||
40d2dba3 | 7547 | if (kvm_read_guest_virt(vcpu, gva, vmpointer, sizeof(*vmpointer), &e)) { |
3573e22c BD |
7548 | kvm_inject_page_fault(vcpu, &e); |
7549 | return 1; | |
7550 | } | |
7551 | ||
3573e22c BD |
7552 | return 0; |
7553 | } | |
7554 | ||
e29acc55 JM |
7555 | static int enter_vmx_operation(struct kvm_vcpu *vcpu) |
7556 | { | |
7557 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
7558 | struct vmcs *shadow_vmcs; | |
b6d7026d | 7559 | int r; |
e29acc55 | 7560 | |
b6d7026d PB |
7561 | r = alloc_loaded_vmcs(&vmx->nested.vmcs02); |
7562 | if (r < 0) | |
8819227c | 7563 | goto out_vmcs02; |
8819227c | 7564 | |
e29acc55 JM |
7565 | vmx->nested.cached_vmcs12 = kmalloc(VMCS12_SIZE, GFP_KERNEL); |
7566 | if (!vmx->nested.cached_vmcs12) | |
7567 | goto out_cached_vmcs12; | |
7568 | ||
7569 | if (enable_shadow_vmcs) { | |
7570 | shadow_vmcs = alloc_vmcs(); | |
7571 | if (!shadow_vmcs) | |
7572 | goto out_shadow_vmcs; | |
7573 | /* mark vmcs as shadow */ | |
7574 | shadow_vmcs->revision_id |= (1u << 31); | |
7575 | /* init shadow vmcs */ | |
7576 | vmcs_clear(shadow_vmcs); | |
7577 | vmx->vmcs01.shadow_vmcs = shadow_vmcs; | |
7578 | } | |
7579 | ||
e29acc55 JM |
7580 | hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC, |
7581 | HRTIMER_MODE_REL_PINNED); | |
7582 | vmx->nested.preemption_timer.function = vmx_preemption_timer_fn; | |
7583 | ||
23f2bb27 RK |
7584 | vmx->nested.vpid02 = allocate_vpid(); |
7585 | ||
e29acc55 JM |
7586 | vmx->nested.vmxon = true; |
7587 | return 0; | |
7588 | ||
7589 | out_shadow_vmcs: | |
7590 | kfree(vmx->nested.cached_vmcs12); | |
7591 | ||
7592 | out_cached_vmcs12: | |
8819227c JM |
7593 | free_loaded_vmcs(&vmx->nested.vmcs02); |
7594 | ||
7595 | out_vmcs02: | |
e29acc55 JM |
7596 | return -ENOMEM; |
7597 | } | |
7598 | ||
ec378aee NHE |
7599 | /* |
7600 | * Emulate the VMXON instruction. | |
7601 | * Currently, we just remember that VMX is active, and do not save or even | |
7602 | * inspect the argument to VMXON (the so-called "VMXON pointer") because we | |
7603 | * do not currently need to store anything in that guest-allocated memory | |
7604 | * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their | |
7605 | * argument is different from the VMXON pointer (which the spec says they do). | |
7606 | */ | |
7607 | static int handle_vmon(struct kvm_vcpu *vcpu) | |
7608 | { | |
e29acc55 | 7609 | int ret; |
cbf71279 RK |
7610 | gpa_t vmptr; |
7611 | struct page *page; | |
ec378aee | 7612 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
b3897a49 NHE |
7613 | const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED |
7614 | | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX; | |
ec378aee | 7615 | |
70f3aac9 JM |
7616 | /* |
7617 | * The Intel VMX Instruction Reference lists a bunch of bits that are | |
7618 | * prerequisite to running VMXON, most notably cr4.VMXE must be set to | |
7619 | * 1 (see vmx_set_cr4() for when we allow the guest to set this). | |
7620 | * Otherwise, we should fail with #UD. But most faulting conditions | |
7621 | * have already been checked by hardware, prior to the VM-exit for | |
7622 | * VMXON. We do test guest cr4.VMXE because processor CR4 always has | |
7623 | * that bit set to 1 in non-root mode. | |
ec378aee | 7624 | */ |
70f3aac9 | 7625 | if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE)) { |
ec378aee NHE |
7626 | kvm_queue_exception(vcpu, UD_VECTOR); |
7627 | return 1; | |
7628 | } | |
7629 | ||
a325262f FW |
7630 | /* CPL=0 must be checked manually. */ |
7631 | if (vmx_get_cpl(vcpu)) { | |
bc9a5a47 | 7632 | kvm_inject_gp(vcpu, 0); |
a325262f FW |
7633 | return 1; |
7634 | } | |
7635 | ||
145c28dd AG |
7636 | if (vmx->nested.vmxon) { |
7637 | nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION); | |
6affcbed | 7638 | return kvm_skip_emulated_instruction(vcpu); |
145c28dd | 7639 | } |
b3897a49 | 7640 | |
3b84080b | 7641 | if ((vmx->msr_ia32_feature_control & VMXON_NEEDED_FEATURES) |
b3897a49 NHE |
7642 | != VMXON_NEEDED_FEATURES) { |
7643 | kvm_inject_gp(vcpu, 0); | |
7644 | return 1; | |
7645 | } | |
7646 | ||
cbf71279 | 7647 | if (nested_vmx_get_vmptr(vcpu, &vmptr)) |
21e7fbe7 | 7648 | return 1; |
cbf71279 RK |
7649 | |
7650 | /* | |
7651 | * SDM 3: 24.11.5 | |
7652 | * The first 4 bytes of VMXON region contain the supported | |
7653 | * VMCS revision identifier | |
7654 | * | |
7655 | * Note - IA32_VMX_BASIC[48] will never be 1 for the nested case; | |
7656 | * which replaces physical address width with 32 | |
7657 | */ | |
7658 | if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu))) { | |
7659 | nested_vmx_failInvalid(vcpu); | |
7660 | return kvm_skip_emulated_instruction(vcpu); | |
7661 | } | |
7662 | ||
5e2f30b7 DH |
7663 | page = kvm_vcpu_gpa_to_page(vcpu, vmptr); |
7664 | if (is_error_page(page)) { | |
cbf71279 RK |
7665 | nested_vmx_failInvalid(vcpu); |
7666 | return kvm_skip_emulated_instruction(vcpu); | |
7667 | } | |
7668 | if (*(u32 *)kmap(page) != VMCS12_REVISION) { | |
7669 | kunmap(page); | |
53a70daf | 7670 | kvm_release_page_clean(page); |
cbf71279 RK |
7671 | nested_vmx_failInvalid(vcpu); |
7672 | return kvm_skip_emulated_instruction(vcpu); | |
7673 | } | |
7674 | kunmap(page); | |
53a70daf | 7675 | kvm_release_page_clean(page); |
cbf71279 RK |
7676 | |
7677 | vmx->nested.vmxon_ptr = vmptr; | |
e29acc55 JM |
7678 | ret = enter_vmx_operation(vcpu); |
7679 | if (ret) | |
7680 | return ret; | |
ec378aee | 7681 | |
a25eb114 | 7682 | nested_vmx_succeed(vcpu); |
6affcbed | 7683 | return kvm_skip_emulated_instruction(vcpu); |
ec378aee NHE |
7684 | } |
7685 | ||
7686 | /* | |
7687 | * Intel's VMX Instruction Reference specifies a common set of prerequisites | |
7688 | * for running VMX instructions (except VMXON, whose prerequisites are | |
7689 | * slightly different). It also specifies what exception to inject otherwise. | |
70f3aac9 JM |
7690 | * Note that many of these exceptions have priority over VM exits, so they |
7691 | * don't have to be checked again here. | |
ec378aee NHE |
7692 | */ |
7693 | static int nested_vmx_check_permission(struct kvm_vcpu *vcpu) | |
7694 | { | |
a325262f | 7695 | if (vmx_get_cpl(vcpu)) { |
bc9a5a47 | 7696 | kvm_inject_gp(vcpu, 0); |
a325262f FW |
7697 | return 0; |
7698 | } | |
7699 | ||
70f3aac9 | 7700 | if (!to_vmx(vcpu)->nested.vmxon) { |
ec378aee NHE |
7701 | kvm_queue_exception(vcpu, UD_VECTOR); |
7702 | return 0; | |
7703 | } | |
ec378aee NHE |
7704 | return 1; |
7705 | } | |
7706 | ||
8ca44e88 DM |
7707 | static void vmx_disable_shadow_vmcs(struct vcpu_vmx *vmx) |
7708 | { | |
7709 | vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL, SECONDARY_EXEC_SHADOW_VMCS); | |
7710 | vmcs_write64(VMCS_LINK_POINTER, -1ull); | |
b2459372 | 7711 | vmx->nested.sync_shadow_vmcs = false; |
8ca44e88 DM |
7712 | } |
7713 | ||
e7953d7f AG |
7714 | static inline void nested_release_vmcs12(struct vcpu_vmx *vmx) |
7715 | { | |
9a2a05b9 PB |
7716 | if (vmx->nested.current_vmptr == -1ull) |
7717 | return; | |
7718 | ||
012f83cb | 7719 | if (enable_shadow_vmcs) { |
9a2a05b9 PB |
7720 | /* copy to memory all shadowed fields in case |
7721 | they were modified */ | |
7722 | copy_shadow_to_vmcs12(vmx); | |
8ca44e88 | 7723 | vmx_disable_shadow_vmcs(vmx); |
012f83cb | 7724 | } |
705699a1 | 7725 | vmx->nested.posted_intr_nv = -1; |
4f2777bc DM |
7726 | |
7727 | /* Flush VMCS12 to guest memory */ | |
9f744c59 PB |
7728 | kvm_vcpu_write_guest_page(&vmx->vcpu, |
7729 | vmx->nested.current_vmptr >> PAGE_SHIFT, | |
7730 | vmx->nested.cached_vmcs12, 0, VMCS12_SIZE); | |
4f2777bc | 7731 | |
9a2a05b9 | 7732 | vmx->nested.current_vmptr = -1ull; |
e7953d7f AG |
7733 | } |
7734 | ||
ec378aee NHE |
7735 | /* |
7736 | * Free whatever needs to be freed from vmx->nested when L1 goes down, or | |
7737 | * just stops using VMX. | |
7738 | */ | |
7739 | static void free_nested(struct vcpu_vmx *vmx) | |
7740 | { | |
b7455825 | 7741 | if (!vmx->nested.vmxon && !vmx->nested.smm.vmxon) |
ec378aee | 7742 | return; |
9a2a05b9 | 7743 | |
fe192085 | 7744 | hrtimer_cancel(&vmx->nested.preemption_timer); |
ec378aee | 7745 | vmx->nested.vmxon = false; |
b7455825 | 7746 | vmx->nested.smm.vmxon = false; |
5c614b35 | 7747 | free_vpid(vmx->nested.vpid02); |
8ca44e88 DM |
7748 | vmx->nested.posted_intr_nv = -1; |
7749 | vmx->nested.current_vmptr = -1ull; | |
355f4fb1 | 7750 | if (enable_shadow_vmcs) { |
8ca44e88 | 7751 | vmx_disable_shadow_vmcs(vmx); |
355f4fb1 JM |
7752 | vmcs_clear(vmx->vmcs01.shadow_vmcs); |
7753 | free_vmcs(vmx->vmcs01.shadow_vmcs); | |
7754 | vmx->vmcs01.shadow_vmcs = NULL; | |
7755 | } | |
4f2777bc | 7756 | kfree(vmx->nested.cached_vmcs12); |
8819227c | 7757 | /* Unpin physical memory we referred to in the vmcs02 */ |
fe3ef05c | 7758 | if (vmx->nested.apic_access_page) { |
53a70daf | 7759 | kvm_release_page_dirty(vmx->nested.apic_access_page); |
48d89b92 | 7760 | vmx->nested.apic_access_page = NULL; |
fe3ef05c | 7761 | } |
a7c0b07d | 7762 | if (vmx->nested.virtual_apic_page) { |
53a70daf | 7763 | kvm_release_page_dirty(vmx->nested.virtual_apic_page); |
48d89b92 | 7764 | vmx->nested.virtual_apic_page = NULL; |
a7c0b07d | 7765 | } |
705699a1 WV |
7766 | if (vmx->nested.pi_desc_page) { |
7767 | kunmap(vmx->nested.pi_desc_page); | |
53a70daf | 7768 | kvm_release_page_dirty(vmx->nested.pi_desc_page); |
705699a1 WV |
7769 | vmx->nested.pi_desc_page = NULL; |
7770 | vmx->nested.pi_desc = NULL; | |
7771 | } | |
ff2f6fe9 | 7772 | |
8819227c | 7773 | free_loaded_vmcs(&vmx->nested.vmcs02); |
ec378aee NHE |
7774 | } |
7775 | ||
7776 | /* Emulate the VMXOFF instruction */ | |
7777 | static int handle_vmoff(struct kvm_vcpu *vcpu) | |
7778 | { | |
7779 | if (!nested_vmx_check_permission(vcpu)) | |
7780 | return 1; | |
7781 | free_nested(to_vmx(vcpu)); | |
a25eb114 | 7782 | nested_vmx_succeed(vcpu); |
6affcbed | 7783 | return kvm_skip_emulated_instruction(vcpu); |
ec378aee NHE |
7784 | } |
7785 | ||
27d6c865 NHE |
7786 | /* Emulate the VMCLEAR instruction */ |
7787 | static int handle_vmclear(struct kvm_vcpu *vcpu) | |
7788 | { | |
7789 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
587d7e72 | 7790 | u32 zero = 0; |
27d6c865 | 7791 | gpa_t vmptr; |
27d6c865 NHE |
7792 | |
7793 | if (!nested_vmx_check_permission(vcpu)) | |
7794 | return 1; | |
7795 | ||
cbf71279 | 7796 | if (nested_vmx_get_vmptr(vcpu, &vmptr)) |
27d6c865 | 7797 | return 1; |
27d6c865 | 7798 | |
cbf71279 RK |
7799 | if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu))) { |
7800 | nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS); | |
7801 | return kvm_skip_emulated_instruction(vcpu); | |
7802 | } | |
7803 | ||
7804 | if (vmptr == vmx->nested.vmxon_ptr) { | |
7805 | nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_VMXON_POINTER); | |
7806 | return kvm_skip_emulated_instruction(vcpu); | |
7807 | } | |
7808 | ||
9a2a05b9 | 7809 | if (vmptr == vmx->nested.current_vmptr) |
e7953d7f | 7810 | nested_release_vmcs12(vmx); |
27d6c865 | 7811 | |
587d7e72 JM |
7812 | kvm_vcpu_write_guest(vcpu, |
7813 | vmptr + offsetof(struct vmcs12, launch_state), | |
7814 | &zero, sizeof(zero)); | |
27d6c865 | 7815 | |
27d6c865 | 7816 | nested_vmx_succeed(vcpu); |
6affcbed | 7817 | return kvm_skip_emulated_instruction(vcpu); |
27d6c865 NHE |
7818 | } |
7819 | ||
cd232ad0 NHE |
7820 | static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch); |
7821 | ||
7822 | /* Emulate the VMLAUNCH instruction */ | |
7823 | static int handle_vmlaunch(struct kvm_vcpu *vcpu) | |
7824 | { | |
7825 | return nested_vmx_run(vcpu, true); | |
7826 | } | |
7827 | ||
7828 | /* Emulate the VMRESUME instruction */ | |
7829 | static int handle_vmresume(struct kvm_vcpu *vcpu) | |
7830 | { | |
7831 | ||
7832 | return nested_vmx_run(vcpu, false); | |
7833 | } | |
7834 | ||
49f705c5 NHE |
7835 | /* |
7836 | * Read a vmcs12 field. Since these can have varying lengths and we return | |
7837 | * one type, we chose the biggest type (u64) and zero-extend the return value | |
7838 | * to that size. Note that the caller, handle_vmread, might need to use only | |
7839 | * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of | |
7840 | * 64-bit fields are to be returned). | |
7841 | */ | |
a2ae9df7 PB |
7842 | static inline int vmcs12_read_any(struct kvm_vcpu *vcpu, |
7843 | unsigned long field, u64 *ret) | |
49f705c5 NHE |
7844 | { |
7845 | short offset = vmcs_field_to_offset(field); | |
7846 | char *p; | |
7847 | ||
7848 | if (offset < 0) | |
a2ae9df7 | 7849 | return offset; |
49f705c5 NHE |
7850 | |
7851 | p = ((char *)(get_vmcs12(vcpu))) + offset; | |
7852 | ||
7853 | switch (vmcs_field_type(field)) { | |
7854 | case VMCS_FIELD_TYPE_NATURAL_WIDTH: | |
7855 | *ret = *((natural_width *)p); | |
a2ae9df7 | 7856 | return 0; |
49f705c5 NHE |
7857 | case VMCS_FIELD_TYPE_U16: |
7858 | *ret = *((u16 *)p); | |
a2ae9df7 | 7859 | return 0; |
49f705c5 NHE |
7860 | case VMCS_FIELD_TYPE_U32: |
7861 | *ret = *((u32 *)p); | |
a2ae9df7 | 7862 | return 0; |
49f705c5 NHE |
7863 | case VMCS_FIELD_TYPE_U64: |
7864 | *ret = *((u64 *)p); | |
a2ae9df7 | 7865 | return 0; |
49f705c5 | 7866 | default: |
a2ae9df7 PB |
7867 | WARN_ON(1); |
7868 | return -ENOENT; | |
49f705c5 NHE |
7869 | } |
7870 | } | |
7871 | ||
20b97fea | 7872 | |
a2ae9df7 PB |
7873 | static inline int vmcs12_write_any(struct kvm_vcpu *vcpu, |
7874 | unsigned long field, u64 field_value){ | |
20b97fea AG |
7875 | short offset = vmcs_field_to_offset(field); |
7876 | char *p = ((char *) get_vmcs12(vcpu)) + offset; | |
7877 | if (offset < 0) | |
a2ae9df7 | 7878 | return offset; |
20b97fea AG |
7879 | |
7880 | switch (vmcs_field_type(field)) { | |
7881 | case VMCS_FIELD_TYPE_U16: | |
7882 | *(u16 *)p = field_value; | |
a2ae9df7 | 7883 | return 0; |
20b97fea AG |
7884 | case VMCS_FIELD_TYPE_U32: |
7885 | *(u32 *)p = field_value; | |
a2ae9df7 | 7886 | return 0; |
20b97fea AG |
7887 | case VMCS_FIELD_TYPE_U64: |
7888 | *(u64 *)p = field_value; | |
a2ae9df7 | 7889 | return 0; |
20b97fea AG |
7890 | case VMCS_FIELD_TYPE_NATURAL_WIDTH: |
7891 | *(natural_width *)p = field_value; | |
a2ae9df7 | 7892 | return 0; |
20b97fea | 7893 | default: |
a2ae9df7 PB |
7894 | WARN_ON(1); |
7895 | return -ENOENT; | |
20b97fea AG |
7896 | } |
7897 | ||
7898 | } | |
7899 | ||
16f5b903 AG |
7900 | static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx) |
7901 | { | |
7902 | int i; | |
7903 | unsigned long field; | |
7904 | u64 field_value; | |
355f4fb1 | 7905 | struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs; |
c2bae893 MK |
7906 | const unsigned long *fields = shadow_read_write_fields; |
7907 | const int num_fields = max_shadow_read_write_fields; | |
16f5b903 | 7908 | |
b2459372 PB |
7909 | if (WARN_ON(!shadow_vmcs)) |
7910 | return; | |
7911 | ||
282da870 JK |
7912 | preempt_disable(); |
7913 | ||
16f5b903 AG |
7914 | vmcs_load(shadow_vmcs); |
7915 | ||
7916 | for (i = 0; i < num_fields; i++) { | |
7917 | field = fields[i]; | |
7918 | switch (vmcs_field_type(field)) { | |
7919 | case VMCS_FIELD_TYPE_U16: | |
7920 | field_value = vmcs_read16(field); | |
7921 | break; | |
7922 | case VMCS_FIELD_TYPE_U32: | |
7923 | field_value = vmcs_read32(field); | |
7924 | break; | |
7925 | case VMCS_FIELD_TYPE_U64: | |
7926 | field_value = vmcs_read64(field); | |
7927 | break; | |
7928 | case VMCS_FIELD_TYPE_NATURAL_WIDTH: | |
7929 | field_value = vmcs_readl(field); | |
7930 | break; | |
a2ae9df7 PB |
7931 | default: |
7932 | WARN_ON(1); | |
7933 | continue; | |
16f5b903 AG |
7934 | } |
7935 | vmcs12_write_any(&vmx->vcpu, field, field_value); | |
7936 | } | |
7937 | ||
7938 | vmcs_clear(shadow_vmcs); | |
7939 | vmcs_load(vmx->loaded_vmcs->vmcs); | |
282da870 JK |
7940 | |
7941 | preempt_enable(); | |
16f5b903 AG |
7942 | } |
7943 | ||
c3114420 AG |
7944 | static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx) |
7945 | { | |
c2bae893 MK |
7946 | const unsigned long *fields[] = { |
7947 | shadow_read_write_fields, | |
7948 | shadow_read_only_fields | |
c3114420 | 7949 | }; |
c2bae893 | 7950 | const int max_fields[] = { |
c3114420 AG |
7951 | max_shadow_read_write_fields, |
7952 | max_shadow_read_only_fields | |
7953 | }; | |
7954 | int i, q; | |
7955 | unsigned long field; | |
7956 | u64 field_value = 0; | |
355f4fb1 | 7957 | struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs; |
c3114420 | 7958 | |
b2459372 PB |
7959 | if (WARN_ON(!shadow_vmcs)) |
7960 | return; | |
7961 | ||
c3114420 AG |
7962 | vmcs_load(shadow_vmcs); |
7963 | ||
c2bae893 | 7964 | for (q = 0; q < ARRAY_SIZE(fields); q++) { |
c3114420 AG |
7965 | for (i = 0; i < max_fields[q]; i++) { |
7966 | field = fields[q][i]; | |
7967 | vmcs12_read_any(&vmx->vcpu, field, &field_value); | |
7968 | ||
7969 | switch (vmcs_field_type(field)) { | |
7970 | case VMCS_FIELD_TYPE_U16: | |
7971 | vmcs_write16(field, (u16)field_value); | |
7972 | break; | |
7973 | case VMCS_FIELD_TYPE_U32: | |
7974 | vmcs_write32(field, (u32)field_value); | |
7975 | break; | |
7976 | case VMCS_FIELD_TYPE_U64: | |
7977 | vmcs_write64(field, (u64)field_value); | |
7978 | break; | |
7979 | case VMCS_FIELD_TYPE_NATURAL_WIDTH: | |
7980 | vmcs_writel(field, (long)field_value); | |
7981 | break; | |
a2ae9df7 PB |
7982 | default: |
7983 | WARN_ON(1); | |
7984 | break; | |
c3114420 AG |
7985 | } |
7986 | } | |
7987 | } | |
7988 | ||
7989 | vmcs_clear(shadow_vmcs); | |
7990 | vmcs_load(vmx->loaded_vmcs->vmcs); | |
7991 | } | |
7992 | ||
49f705c5 NHE |
7993 | /* |
7994 | * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was | |
7995 | * used before) all generate the same failure when it is missing. | |
7996 | */ | |
7997 | static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu) | |
7998 | { | |
7999 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
8000 | if (vmx->nested.current_vmptr == -1ull) { | |
8001 | nested_vmx_failInvalid(vcpu); | |
49f705c5 NHE |
8002 | return 0; |
8003 | } | |
8004 | return 1; | |
8005 | } | |
8006 | ||
8007 | static int handle_vmread(struct kvm_vcpu *vcpu) | |
8008 | { | |
8009 | unsigned long field; | |
8010 | u64 field_value; | |
8011 | unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
8012 | u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO); | |
8013 | gva_t gva = 0; | |
ff2726ac | 8014 | struct x86_exception e; |
49f705c5 | 8015 | |
eb277562 | 8016 | if (!nested_vmx_check_permission(vcpu)) |
49f705c5 NHE |
8017 | return 1; |
8018 | ||
6affcbed KH |
8019 | if (!nested_vmx_check_vmcs12(vcpu)) |
8020 | return kvm_skip_emulated_instruction(vcpu); | |
49f705c5 NHE |
8021 | |
8022 | /* Decode instruction info and find the field to read */ | |
27e6fb5d | 8023 | field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf)); |
49f705c5 | 8024 | /* Read the field, zero-extended to a u64 field_value */ |
a2ae9df7 | 8025 | if (vmcs12_read_any(vcpu, field, &field_value) < 0) { |
49f705c5 | 8026 | nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT); |
6affcbed | 8027 | return kvm_skip_emulated_instruction(vcpu); |
49f705c5 NHE |
8028 | } |
8029 | /* | |
8030 | * Now copy part of this value to register or memory, as requested. | |
8031 | * Note that the number of bits actually copied is 32 or 64 depending | |
8032 | * on the guest's mode (32 or 64 bit), not on the given field's length. | |
8033 | */ | |
8034 | if (vmx_instruction_info & (1u << 10)) { | |
27e6fb5d | 8035 | kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf), |
49f705c5 NHE |
8036 | field_value); |
8037 | } else { | |
8038 | if (get_vmx_mem_address(vcpu, exit_qualification, | |
f9eb4af6 | 8039 | vmx_instruction_info, true, &gva)) |
49f705c5 | 8040 | return 1; |
a325262f | 8041 | /* _system ok, nested_vmx_check_permission has verified cpl=0 */ |
ff2726ac PB |
8042 | if (kvm_write_guest_virt_system(vcpu, gva, &field_value, |
8043 | (is_long_mode(vcpu) ? 8 : 4), | |
b2a0bb4f | 8044 | &e)) { |
ff2726ac | 8045 | kvm_inject_page_fault(vcpu, &e); |
b2a0bb4f ML |
8046 | return 1; |
8047 | } | |
49f705c5 NHE |
8048 | } |
8049 | ||
8050 | nested_vmx_succeed(vcpu); | |
6affcbed | 8051 | return kvm_skip_emulated_instruction(vcpu); |
49f705c5 NHE |
8052 | } |
8053 | ||
8054 | ||
8055 | static int handle_vmwrite(struct kvm_vcpu *vcpu) | |
8056 | { | |
8057 | unsigned long field; | |
8058 | gva_t gva; | |
8059 | unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
8060 | u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO); | |
49f705c5 NHE |
8061 | /* The value to write might be 32 or 64 bits, depending on L1's long |
8062 | * mode, and eventually we need to write that into a field of several | |
8063 | * possible lengths. The code below first zero-extends the value to 64 | |
6a6256f9 | 8064 | * bit (field_value), and then copies only the appropriate number of |
49f705c5 NHE |
8065 | * bits into the vmcs12 field. |
8066 | */ | |
8067 | u64 field_value = 0; | |
8068 | struct x86_exception e; | |
8069 | ||
eb277562 | 8070 | if (!nested_vmx_check_permission(vcpu)) |
49f705c5 NHE |
8071 | return 1; |
8072 | ||
6affcbed KH |
8073 | if (!nested_vmx_check_vmcs12(vcpu)) |
8074 | return kvm_skip_emulated_instruction(vcpu); | |
eb277562 | 8075 | |
49f705c5 | 8076 | if (vmx_instruction_info & (1u << 10)) |
27e6fb5d | 8077 | field_value = kvm_register_readl(vcpu, |
49f705c5 NHE |
8078 | (((vmx_instruction_info) >> 3) & 0xf)); |
8079 | else { | |
8080 | if (get_vmx_mem_address(vcpu, exit_qualification, | |
f9eb4af6 | 8081 | vmx_instruction_info, false, &gva)) |
49f705c5 | 8082 | return 1; |
40d2dba3 PB |
8083 | if (kvm_read_guest_virt(vcpu, gva, &field_value, |
8084 | (is_64_bit_mode(vcpu) ? 8 : 4), &e)) { | |
49f705c5 NHE |
8085 | kvm_inject_page_fault(vcpu, &e); |
8086 | return 1; | |
8087 | } | |
8088 | } | |
8089 | ||
8090 | ||
27e6fb5d | 8091 | field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf)); |
49f705c5 NHE |
8092 | if (vmcs_field_readonly(field)) { |
8093 | nested_vmx_failValid(vcpu, | |
8094 | VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT); | |
6affcbed | 8095 | return kvm_skip_emulated_instruction(vcpu); |
49f705c5 NHE |
8096 | } |
8097 | ||
a2ae9df7 | 8098 | if (vmcs12_write_any(vcpu, field, field_value) < 0) { |
49f705c5 | 8099 | nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT); |
6affcbed | 8100 | return kvm_skip_emulated_instruction(vcpu); |
49f705c5 NHE |
8101 | } |
8102 | ||
8103 | nested_vmx_succeed(vcpu); | |
6affcbed | 8104 | return kvm_skip_emulated_instruction(vcpu); |
49f705c5 NHE |
8105 | } |
8106 | ||
a8bc284e JM |
8107 | static void set_current_vmptr(struct vcpu_vmx *vmx, gpa_t vmptr) |
8108 | { | |
8109 | vmx->nested.current_vmptr = vmptr; | |
8110 | if (enable_shadow_vmcs) { | |
8111 | vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL, | |
8112 | SECONDARY_EXEC_SHADOW_VMCS); | |
8113 | vmcs_write64(VMCS_LINK_POINTER, | |
8114 | __pa(vmx->vmcs01.shadow_vmcs)); | |
8115 | vmx->nested.sync_shadow_vmcs = true; | |
8116 | } | |
8117 | } | |
8118 | ||
63846663 NHE |
8119 | /* Emulate the VMPTRLD instruction */ |
8120 | static int handle_vmptrld(struct kvm_vcpu *vcpu) | |
8121 | { | |
8122 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
63846663 | 8123 | gpa_t vmptr; |
63846663 NHE |
8124 | |
8125 | if (!nested_vmx_check_permission(vcpu)) | |
8126 | return 1; | |
8127 | ||
cbf71279 | 8128 | if (nested_vmx_get_vmptr(vcpu, &vmptr)) |
63846663 | 8129 | return 1; |
63846663 | 8130 | |
cbf71279 RK |
8131 | if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu))) { |
8132 | nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS); | |
8133 | return kvm_skip_emulated_instruction(vcpu); | |
8134 | } | |
8135 | ||
8136 | if (vmptr == vmx->nested.vmxon_ptr) { | |
8137 | nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_VMXON_POINTER); | |
8138 | return kvm_skip_emulated_instruction(vcpu); | |
8139 | } | |
8140 | ||
63846663 NHE |
8141 | if (vmx->nested.current_vmptr != vmptr) { |
8142 | struct vmcs12 *new_vmcs12; | |
8143 | struct page *page; | |
5e2f30b7 DH |
8144 | page = kvm_vcpu_gpa_to_page(vcpu, vmptr); |
8145 | if (is_error_page(page)) { | |
63846663 | 8146 | nested_vmx_failInvalid(vcpu); |
6affcbed | 8147 | return kvm_skip_emulated_instruction(vcpu); |
63846663 NHE |
8148 | } |
8149 | new_vmcs12 = kmap(page); | |
8150 | if (new_vmcs12->revision_id != VMCS12_REVISION) { | |
8151 | kunmap(page); | |
53a70daf | 8152 | kvm_release_page_clean(page); |
63846663 NHE |
8153 | nested_vmx_failValid(vcpu, |
8154 | VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID); | |
6affcbed | 8155 | return kvm_skip_emulated_instruction(vcpu); |
63846663 | 8156 | } |
63846663 | 8157 | |
9a2a05b9 | 8158 | nested_release_vmcs12(vmx); |
4f2777bc DM |
8159 | /* |
8160 | * Load VMCS12 from guest memory since it is not already | |
8161 | * cached. | |
8162 | */ | |
9f744c59 PB |
8163 | memcpy(vmx->nested.cached_vmcs12, new_vmcs12, VMCS12_SIZE); |
8164 | kunmap(page); | |
53a70daf | 8165 | kvm_release_page_clean(page); |
9f744c59 | 8166 | |
a8bc284e | 8167 | set_current_vmptr(vmx, vmptr); |
63846663 NHE |
8168 | } |
8169 | ||
8170 | nested_vmx_succeed(vcpu); | |
6affcbed | 8171 | return kvm_skip_emulated_instruction(vcpu); |
63846663 NHE |
8172 | } |
8173 | ||
6a4d7550 NHE |
8174 | /* Emulate the VMPTRST instruction */ |
8175 | static int handle_vmptrst(struct kvm_vcpu *vcpu) | |
8176 | { | |
30c549fb SC |
8177 | unsigned long exit_qual = vmcs_readl(EXIT_QUALIFICATION); |
8178 | u32 instr_info = vmcs_read32(VMX_INSTRUCTION_INFO); | |
8179 | gpa_t current_vmptr = to_vmx(vcpu)->nested.current_vmptr; | |
6a4d7550 | 8180 | struct x86_exception e; |
30c549fb | 8181 | gva_t gva; |
6a4d7550 NHE |
8182 | |
8183 | if (!nested_vmx_check_permission(vcpu)) | |
8184 | return 1; | |
8185 | ||
30c549fb | 8186 | if (get_vmx_mem_address(vcpu, exit_qual, instr_info, true, &gva)) |
6a4d7550 | 8187 | return 1; |
a325262f | 8188 | /* *_system ok, nested_vmx_check_permission has verified cpl=0 */ |
30c549fb SC |
8189 | if (kvm_write_guest_virt_system(vcpu, gva, (void *)¤t_vmptr, |
8190 | sizeof(gpa_t), &e)) { | |
6a4d7550 NHE |
8191 | kvm_inject_page_fault(vcpu, &e); |
8192 | return 1; | |
8193 | } | |
8194 | nested_vmx_succeed(vcpu); | |
6affcbed | 8195 | return kvm_skip_emulated_instruction(vcpu); |
6a4d7550 NHE |
8196 | } |
8197 | ||
bfd0a56b NHE |
8198 | /* Emulate the INVEPT instruction */ |
8199 | static int handle_invept(struct kvm_vcpu *vcpu) | |
8200 | { | |
b9c237bb | 8201 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
bfd0a56b NHE |
8202 | u32 vmx_instruction_info, types; |
8203 | unsigned long type; | |
8204 | gva_t gva; | |
8205 | struct x86_exception e; | |
8206 | struct { | |
8207 | u64 eptp, gpa; | |
8208 | } operand; | |
bfd0a56b | 8209 | |
b9c237bb WV |
8210 | if (!(vmx->nested.nested_vmx_secondary_ctls_high & |
8211 | SECONDARY_EXEC_ENABLE_EPT) || | |
8212 | !(vmx->nested.nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) { | |
bfd0a56b NHE |
8213 | kvm_queue_exception(vcpu, UD_VECTOR); |
8214 | return 1; | |
8215 | } | |
8216 | ||
8217 | if (!nested_vmx_check_permission(vcpu)) | |
8218 | return 1; | |
8219 | ||
bfd0a56b | 8220 | vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO); |
27e6fb5d | 8221 | type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf); |
bfd0a56b | 8222 | |
b9c237bb | 8223 | types = (vmx->nested.nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6; |
bfd0a56b | 8224 | |
85c856b3 | 8225 | if (type >= 32 || !(types & (1 << type))) { |
bfd0a56b NHE |
8226 | nested_vmx_failValid(vcpu, |
8227 | VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID); | |
6affcbed | 8228 | return kvm_skip_emulated_instruction(vcpu); |
bfd0a56b NHE |
8229 | } |
8230 | ||
8231 | /* According to the Intel VMX instruction reference, the memory | |
8232 | * operand is read even if it isn't needed (e.g., for type==global) | |
8233 | */ | |
8234 | if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION), | |
f9eb4af6 | 8235 | vmx_instruction_info, false, &gva)) |
bfd0a56b | 8236 | return 1; |
40d2dba3 | 8237 | if (kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e)) { |
bfd0a56b NHE |
8238 | kvm_inject_page_fault(vcpu, &e); |
8239 | return 1; | |
8240 | } | |
8241 | ||
8242 | switch (type) { | |
bfd0a56b | 8243 | case VMX_EPT_EXTENT_GLOBAL: |
45e11817 BD |
8244 | /* |
8245 | * TODO: track mappings and invalidate | |
8246 | * single context requests appropriately | |
8247 | */ | |
8248 | case VMX_EPT_EXTENT_CONTEXT: | |
bfd0a56b | 8249 | kvm_mmu_sync_roots(vcpu); |
77c3913b | 8250 | kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); |
bfd0a56b NHE |
8251 | nested_vmx_succeed(vcpu); |
8252 | break; | |
8253 | default: | |
8254 | BUG_ON(1); | |
8255 | break; | |
8256 | } | |
8257 | ||
6affcbed | 8258 | return kvm_skip_emulated_instruction(vcpu); |
bfd0a56b NHE |
8259 | } |
8260 | ||
a642fc30 PM |
8261 | static int handle_invvpid(struct kvm_vcpu *vcpu) |
8262 | { | |
99b83ac8 WL |
8263 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
8264 | u32 vmx_instruction_info; | |
8265 | unsigned long type, types; | |
8266 | gva_t gva; | |
8267 | struct x86_exception e; | |
40352605 JM |
8268 | struct { |
8269 | u64 vpid; | |
8270 | u64 gla; | |
8271 | } operand; | |
99b83ac8 WL |
8272 | |
8273 | if (!(vmx->nested.nested_vmx_secondary_ctls_high & | |
8274 | SECONDARY_EXEC_ENABLE_VPID) || | |
8275 | !(vmx->nested.nested_vmx_vpid_caps & VMX_VPID_INVVPID_BIT)) { | |
8276 | kvm_queue_exception(vcpu, UD_VECTOR); | |
8277 | return 1; | |
8278 | } | |
8279 | ||
8280 | if (!nested_vmx_check_permission(vcpu)) | |
8281 | return 1; | |
8282 | ||
8283 | vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO); | |
8284 | type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf); | |
8285 | ||
bcdde302 JD |
8286 | types = (vmx->nested.nested_vmx_vpid_caps & |
8287 | VMX_VPID_EXTENT_SUPPORTED_MASK) >> 8; | |
99b83ac8 | 8288 | |
85c856b3 | 8289 | if (type >= 32 || !(types & (1 << type))) { |
99b83ac8 WL |
8290 | nested_vmx_failValid(vcpu, |
8291 | VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID); | |
6affcbed | 8292 | return kvm_skip_emulated_instruction(vcpu); |
99b83ac8 WL |
8293 | } |
8294 | ||
8295 | /* according to the intel vmx instruction reference, the memory | |
8296 | * operand is read even if it isn't needed (e.g., for type==global) | |
8297 | */ | |
8298 | if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION), | |
8299 | vmx_instruction_info, false, &gva)) | |
8300 | return 1; | |
40d2dba3 | 8301 | if (kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e)) { |
99b83ac8 WL |
8302 | kvm_inject_page_fault(vcpu, &e); |
8303 | return 1; | |
8304 | } | |
40352605 JM |
8305 | if (operand.vpid >> 16) { |
8306 | nested_vmx_failValid(vcpu, | |
8307 | VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID); | |
8308 | return kvm_skip_emulated_instruction(vcpu); | |
8309 | } | |
99b83ac8 WL |
8310 | |
8311 | switch (type) { | |
bcdde302 | 8312 | case VMX_VPID_EXTENT_INDIVIDUAL_ADDR: |
fd8cb433 | 8313 | if (is_noncanonical_address(operand.gla, vcpu)) { |
40352605 JM |
8314 | nested_vmx_failValid(vcpu, |
8315 | VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID); | |
8316 | return kvm_skip_emulated_instruction(vcpu); | |
8317 | } | |
8318 | /* fall through */ | |
ef697a71 | 8319 | case VMX_VPID_EXTENT_SINGLE_CONTEXT: |
bcdde302 | 8320 | case VMX_VPID_EXTENT_SINGLE_NON_GLOBAL: |
40352605 | 8321 | if (!operand.vpid) { |
bcdde302 JD |
8322 | nested_vmx_failValid(vcpu, |
8323 | VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID); | |
6affcbed | 8324 | return kvm_skip_emulated_instruction(vcpu); |
bcdde302 JD |
8325 | } |
8326 | break; | |
99b83ac8 | 8327 | case VMX_VPID_EXTENT_ALL_CONTEXT: |
99b83ac8 WL |
8328 | break; |
8329 | default: | |
bcdde302 | 8330 | WARN_ON_ONCE(1); |
6affcbed | 8331 | return kvm_skip_emulated_instruction(vcpu); |
99b83ac8 WL |
8332 | } |
8333 | ||
6bf41e55 | 8334 | __vmx_flush_tlb(vcpu, vmx->nested.vpid02, true); |
bcdde302 JD |
8335 | nested_vmx_succeed(vcpu); |
8336 | ||
6affcbed | 8337 | return kvm_skip_emulated_instruction(vcpu); |
a642fc30 PM |
8338 | } |
8339 | ||
843e4330 KH |
8340 | static int handle_pml_full(struct kvm_vcpu *vcpu) |
8341 | { | |
8342 | unsigned long exit_qualification; | |
8343 | ||
8344 | trace_kvm_pml_full(vcpu->vcpu_id); | |
8345 | ||
8346 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
8347 | ||
8348 | /* | |
8349 | * PML buffer FULL happened while executing iret from NMI, | |
8350 | * "blocked by NMI" bit has to be set before next VM entry. | |
8351 | */ | |
8352 | if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) && | |
d02fcf50 | 8353 | enable_vnmi && |
843e4330 KH |
8354 | (exit_qualification & INTR_INFO_UNBLOCK_NMI)) |
8355 | vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, | |
8356 | GUEST_INTR_STATE_NMI); | |
8357 | ||
8358 | /* | |
8359 | * PML buffer already flushed at beginning of VMEXIT. Nothing to do | |
8360 | * here.., and there's no userspace involvement needed for PML. | |
8361 | */ | |
8362 | return 1; | |
8363 | } | |
8364 | ||
64672c95 YJ |
8365 | static int handle_preemption_timer(struct kvm_vcpu *vcpu) |
8366 | { | |
8367 | kvm_lapic_expired_hv_timer(vcpu); | |
8368 | return 1; | |
8369 | } | |
8370 | ||
41ab9372 BD |
8371 | static bool valid_ept_address(struct kvm_vcpu *vcpu, u64 address) |
8372 | { | |
8373 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
41ab9372 BD |
8374 | int maxphyaddr = cpuid_maxphyaddr(vcpu); |
8375 | ||
8376 | /* Check for memory type validity */ | |
bb97a016 DH |
8377 | switch (address & VMX_EPTP_MT_MASK) { |
8378 | case VMX_EPTP_MT_UC: | |
41ab9372 BD |
8379 | if (!(vmx->nested.nested_vmx_ept_caps & VMX_EPTP_UC_BIT)) |
8380 | return false; | |
8381 | break; | |
bb97a016 | 8382 | case VMX_EPTP_MT_WB: |
41ab9372 BD |
8383 | if (!(vmx->nested.nested_vmx_ept_caps & VMX_EPTP_WB_BIT)) |
8384 | return false; | |
8385 | break; | |
8386 | default: | |
8387 | return false; | |
8388 | } | |
8389 | ||
bb97a016 DH |
8390 | /* only 4 levels page-walk length are valid */ |
8391 | if ((address & VMX_EPTP_PWL_MASK) != VMX_EPTP_PWL_4) | |
41ab9372 BD |
8392 | return false; |
8393 | ||
8394 | /* Reserved bits should not be set */ | |
8395 | if (address >> maxphyaddr || ((address >> 7) & 0x1f)) | |
8396 | return false; | |
8397 | ||
8398 | /* AD, if set, should be supported */ | |
bb97a016 | 8399 | if (address & VMX_EPTP_AD_ENABLE_BIT) { |
41ab9372 BD |
8400 | if (!(vmx->nested.nested_vmx_ept_caps & VMX_EPT_AD_BIT)) |
8401 | return false; | |
8402 | } | |
8403 | ||
8404 | return true; | |
8405 | } | |
8406 | ||
8407 | static int nested_vmx_eptp_switching(struct kvm_vcpu *vcpu, | |
8408 | struct vmcs12 *vmcs12) | |
8409 | { | |
8410 | u32 index = vcpu->arch.regs[VCPU_REGS_RCX]; | |
8411 | u64 address; | |
8412 | bool accessed_dirty; | |
8413 | struct kvm_mmu *mmu = vcpu->arch.walk_mmu; | |
8414 | ||
8415 | if (!nested_cpu_has_eptp_switching(vmcs12) || | |
8416 | !nested_cpu_has_ept(vmcs12)) | |
8417 | return 1; | |
8418 | ||
8419 | if (index >= VMFUNC_EPTP_ENTRIES) | |
8420 | return 1; | |
8421 | ||
8422 | ||
8423 | if (kvm_vcpu_read_guest_page(vcpu, vmcs12->eptp_list_address >> PAGE_SHIFT, | |
8424 | &address, index * 8, 8)) | |
8425 | return 1; | |
8426 | ||
bb97a016 | 8427 | accessed_dirty = !!(address & VMX_EPTP_AD_ENABLE_BIT); |
41ab9372 BD |
8428 | |
8429 | /* | |
8430 | * If the (L2) guest does a vmfunc to the currently | |
8431 | * active ept pointer, we don't have to do anything else | |
8432 | */ | |
8433 | if (vmcs12->ept_pointer != address) { | |
8434 | if (!valid_ept_address(vcpu, address)) | |
8435 | return 1; | |
8436 | ||
8437 | kvm_mmu_unload(vcpu); | |
8438 | mmu->ept_ad = accessed_dirty; | |
8439 | mmu->base_role.ad_disabled = !accessed_dirty; | |
8440 | vmcs12->ept_pointer = address; | |
8441 | /* | |
8442 | * TODO: Check what's the correct approach in case | |
8443 | * mmu reload fails. Currently, we just let the next | |
8444 | * reload potentially fail | |
8445 | */ | |
8446 | kvm_mmu_reload(vcpu); | |
8447 | } | |
8448 | ||
8449 | return 0; | |
8450 | } | |
8451 | ||
2a499e49 BD |
8452 | static int handle_vmfunc(struct kvm_vcpu *vcpu) |
8453 | { | |
27c42a1b BD |
8454 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
8455 | struct vmcs12 *vmcs12; | |
8456 | u32 function = vcpu->arch.regs[VCPU_REGS_RAX]; | |
8457 | ||
8458 | /* | |
8459 | * VMFUNC is only supported for nested guests, but we always enable the | |
8460 | * secondary control for simplicity; for non-nested mode, fake that we | |
8461 | * didn't by injecting #UD. | |
8462 | */ | |
8463 | if (!is_guest_mode(vcpu)) { | |
8464 | kvm_queue_exception(vcpu, UD_VECTOR); | |
8465 | return 1; | |
8466 | } | |
8467 | ||
8468 | vmcs12 = get_vmcs12(vcpu); | |
8469 | if ((vmcs12->vm_function_control & (1 << function)) == 0) | |
8470 | goto fail; | |
41ab9372 BD |
8471 | |
8472 | switch (function) { | |
8473 | case 0: | |
8474 | if (nested_vmx_eptp_switching(vcpu, vmcs12)) | |
8475 | goto fail; | |
8476 | break; | |
8477 | default: | |
8478 | goto fail; | |
8479 | } | |
8480 | return kvm_skip_emulated_instruction(vcpu); | |
27c42a1b BD |
8481 | |
8482 | fail: | |
8483 | nested_vmx_vmexit(vcpu, vmx->exit_reason, | |
8484 | vmcs_read32(VM_EXIT_INTR_INFO), | |
8485 | vmcs_readl(EXIT_QUALIFICATION)); | |
2a499e49 BD |
8486 | return 1; |
8487 | } | |
8488 | ||
6aa8b732 AK |
8489 | /* |
8490 | * The exit handlers return 1 if the exit was handled fully and guest execution | |
8491 | * may resume. Otherwise they set the kvm_run parameter to indicate what needs | |
8492 | * to be done to userspace and return 0. | |
8493 | */ | |
772e0318 | 8494 | static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = { |
6aa8b732 AK |
8495 | [EXIT_REASON_EXCEPTION_NMI] = handle_exception, |
8496 | [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt, | |
988ad74f | 8497 | [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault, |
f08864b4 | 8498 | [EXIT_REASON_NMI_WINDOW] = handle_nmi_window, |
6aa8b732 | 8499 | [EXIT_REASON_IO_INSTRUCTION] = handle_io, |
6aa8b732 AK |
8500 | [EXIT_REASON_CR_ACCESS] = handle_cr, |
8501 | [EXIT_REASON_DR_ACCESS] = handle_dr, | |
8502 | [EXIT_REASON_CPUID] = handle_cpuid, | |
8503 | [EXIT_REASON_MSR_READ] = handle_rdmsr, | |
8504 | [EXIT_REASON_MSR_WRITE] = handle_wrmsr, | |
8505 | [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window, | |
8506 | [EXIT_REASON_HLT] = handle_halt, | |
ec25d5e6 | 8507 | [EXIT_REASON_INVD] = handle_invd, |
a7052897 | 8508 | [EXIT_REASON_INVLPG] = handle_invlpg, |
fee84b07 | 8509 | [EXIT_REASON_RDPMC] = handle_rdpmc, |
c21415e8 | 8510 | [EXIT_REASON_VMCALL] = handle_vmcall, |
27d6c865 | 8511 | [EXIT_REASON_VMCLEAR] = handle_vmclear, |
cd232ad0 | 8512 | [EXIT_REASON_VMLAUNCH] = handle_vmlaunch, |
63846663 | 8513 | [EXIT_REASON_VMPTRLD] = handle_vmptrld, |
6a4d7550 | 8514 | [EXIT_REASON_VMPTRST] = handle_vmptrst, |
49f705c5 | 8515 | [EXIT_REASON_VMREAD] = handle_vmread, |
cd232ad0 | 8516 | [EXIT_REASON_VMRESUME] = handle_vmresume, |
49f705c5 | 8517 | [EXIT_REASON_VMWRITE] = handle_vmwrite, |
ec378aee NHE |
8518 | [EXIT_REASON_VMOFF] = handle_vmoff, |
8519 | [EXIT_REASON_VMON] = handle_vmon, | |
f78e0e2e SY |
8520 | [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold, |
8521 | [EXIT_REASON_APIC_ACCESS] = handle_apic_access, | |
83d4c286 | 8522 | [EXIT_REASON_APIC_WRITE] = handle_apic_write, |
c7c9c56c | 8523 | [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced, |
e5edaa01 | 8524 | [EXIT_REASON_WBINVD] = handle_wbinvd, |
2acf923e | 8525 | [EXIT_REASON_XSETBV] = handle_xsetbv, |
37817f29 | 8526 | [EXIT_REASON_TASK_SWITCH] = handle_task_switch, |
a0861c02 | 8527 | [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check, |
68f89400 MT |
8528 | [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation, |
8529 | [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig, | |
4b8d54f9 | 8530 | [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause, |
87c00572 | 8531 | [EXIT_REASON_MWAIT_INSTRUCTION] = handle_mwait, |
5f3d45e7 | 8532 | [EXIT_REASON_MONITOR_TRAP_FLAG] = handle_monitor_trap, |
87c00572 | 8533 | [EXIT_REASON_MONITOR_INSTRUCTION] = handle_monitor, |
bfd0a56b | 8534 | [EXIT_REASON_INVEPT] = handle_invept, |
a642fc30 | 8535 | [EXIT_REASON_INVVPID] = handle_invvpid, |
45ec368c | 8536 | [EXIT_REASON_RDRAND] = handle_invalid_op, |
75f4fc8d | 8537 | [EXIT_REASON_RDSEED] = handle_invalid_op, |
f53cd63c WL |
8538 | [EXIT_REASON_XSAVES] = handle_xsaves, |
8539 | [EXIT_REASON_XRSTORS] = handle_xrstors, | |
843e4330 | 8540 | [EXIT_REASON_PML_FULL] = handle_pml_full, |
2a499e49 | 8541 | [EXIT_REASON_VMFUNC] = handle_vmfunc, |
64672c95 | 8542 | [EXIT_REASON_PREEMPTION_TIMER] = handle_preemption_timer, |
6aa8b732 AK |
8543 | }; |
8544 | ||
8545 | static const int kvm_vmx_max_exit_handlers = | |
50a3485c | 8546 | ARRAY_SIZE(kvm_vmx_exit_handlers); |
6aa8b732 | 8547 | |
e8c9d710 OU |
8548 | /* |
8549 | * Return true if an IO instruction with the specified port and size should cause | |
8550 | * a VM-exit into L1. | |
8551 | */ | |
8552 | bool nested_vmx_check_io_bitmaps(struct kvm_vcpu *vcpu, unsigned int port, | |
8553 | int size) | |
908a7bdd | 8554 | { |
e8c9d710 | 8555 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); |
908a7bdd | 8556 | gpa_t bitmap, last_bitmap; |
908a7bdd JK |
8557 | u8 b; |
8558 | ||
908a7bdd JK |
8559 | last_bitmap = (gpa_t)-1; |
8560 | b = -1; | |
8561 | ||
8562 | while (size > 0) { | |
8563 | if (port < 0x8000) | |
8564 | bitmap = vmcs12->io_bitmap_a; | |
8565 | else if (port < 0x10000) | |
8566 | bitmap = vmcs12->io_bitmap_b; | |
8567 | else | |
1d804d07 | 8568 | return true; |
908a7bdd JK |
8569 | bitmap += (port & 0x7fff) / 8; |
8570 | ||
8571 | if (last_bitmap != bitmap) | |
54bf36aa | 8572 | if (kvm_vcpu_read_guest(vcpu, bitmap, &b, 1)) |
1d804d07 | 8573 | return true; |
908a7bdd | 8574 | if (b & (1 << (port & 7))) |
1d804d07 | 8575 | return true; |
908a7bdd JK |
8576 | |
8577 | port++; | |
8578 | size--; | |
8579 | last_bitmap = bitmap; | |
8580 | } | |
8581 | ||
1d804d07 | 8582 | return false; |
908a7bdd JK |
8583 | } |
8584 | ||
644d711a NHE |
8585 | /* |
8586 | * Return 1 if we should exit from L2 to L1 to handle an MSR access access, | |
8587 | * rather than handle it ourselves in L0. I.e., check whether L1 expressed | |
8588 | * disinterest in the current event (read or write a specific MSR) by using an | |
8589 | * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps. | |
8590 | */ | |
8591 | static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu, | |
8592 | struct vmcs12 *vmcs12, u32 exit_reason) | |
8593 | { | |
8594 | u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX]; | |
8595 | gpa_t bitmap; | |
8596 | ||
cbd29cb6 | 8597 | if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS)) |
1d804d07 | 8598 | return true; |
644d711a NHE |
8599 | |
8600 | /* | |
8601 | * The MSR_BITMAP page is divided into four 1024-byte bitmaps, | |
8602 | * for the four combinations of read/write and low/high MSR numbers. | |
8603 | * First we need to figure out which of the four to use: | |
8604 | */ | |
8605 | bitmap = vmcs12->msr_bitmap; | |
8606 | if (exit_reason == EXIT_REASON_MSR_WRITE) | |
8607 | bitmap += 2048; | |
8608 | if (msr_index >= 0xc0000000) { | |
8609 | msr_index -= 0xc0000000; | |
8610 | bitmap += 1024; | |
8611 | } | |
8612 | ||
8613 | /* Then read the msr_index'th bit from this bitmap: */ | |
8614 | if (msr_index < 1024*8) { | |
8615 | unsigned char b; | |
54bf36aa | 8616 | if (kvm_vcpu_read_guest(vcpu, bitmap + msr_index/8, &b, 1)) |
1d804d07 | 8617 | return true; |
644d711a NHE |
8618 | return 1 & (b >> (msr_index & 7)); |
8619 | } else | |
1d804d07 | 8620 | return true; /* let L1 handle the wrong parameter */ |
644d711a NHE |
8621 | } |
8622 | ||
8623 | /* | |
8624 | * Return 1 if we should exit from L2 to L1 to handle a CR access exit, | |
8625 | * rather than handle it ourselves in L0. I.e., check if L1 wanted to | |
8626 | * intercept (via guest_host_mask etc.) the current event. | |
8627 | */ | |
8628 | static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu, | |
8629 | struct vmcs12 *vmcs12) | |
8630 | { | |
8631 | unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
8632 | int cr = exit_qualification & 15; | |
e1d39b17 JS |
8633 | int reg; |
8634 | unsigned long val; | |
644d711a NHE |
8635 | |
8636 | switch ((exit_qualification >> 4) & 3) { | |
8637 | case 0: /* mov to cr */ | |
e1d39b17 JS |
8638 | reg = (exit_qualification >> 8) & 15; |
8639 | val = kvm_register_readl(vcpu, reg); | |
644d711a NHE |
8640 | switch (cr) { |
8641 | case 0: | |
8642 | if (vmcs12->cr0_guest_host_mask & | |
8643 | (val ^ vmcs12->cr0_read_shadow)) | |
1d804d07 | 8644 | return true; |
644d711a NHE |
8645 | break; |
8646 | case 3: | |
8647 | if ((vmcs12->cr3_target_count >= 1 && | |
8648 | vmcs12->cr3_target_value0 == val) || | |
8649 | (vmcs12->cr3_target_count >= 2 && | |
8650 | vmcs12->cr3_target_value1 == val) || | |
8651 | (vmcs12->cr3_target_count >= 3 && | |
8652 | vmcs12->cr3_target_value2 == val) || | |
8653 | (vmcs12->cr3_target_count >= 4 && | |
8654 | vmcs12->cr3_target_value3 == val)) | |
1d804d07 | 8655 | return false; |
644d711a | 8656 | if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING)) |
1d804d07 | 8657 | return true; |
644d711a NHE |
8658 | break; |
8659 | case 4: | |
8660 | if (vmcs12->cr4_guest_host_mask & | |
8661 | (vmcs12->cr4_read_shadow ^ val)) | |
1d804d07 | 8662 | return true; |
644d711a NHE |
8663 | break; |
8664 | case 8: | |
8665 | if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING)) | |
1d804d07 | 8666 | return true; |
644d711a NHE |
8667 | break; |
8668 | } | |
8669 | break; | |
8670 | case 2: /* clts */ | |
8671 | if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) && | |
8672 | (vmcs12->cr0_read_shadow & X86_CR0_TS)) | |
1d804d07 | 8673 | return true; |
644d711a NHE |
8674 | break; |
8675 | case 1: /* mov from cr */ | |
8676 | switch (cr) { | |
8677 | case 3: | |
8678 | if (vmcs12->cpu_based_vm_exec_control & | |
8679 | CPU_BASED_CR3_STORE_EXITING) | |
1d804d07 | 8680 | return true; |
644d711a NHE |
8681 | break; |
8682 | case 8: | |
8683 | if (vmcs12->cpu_based_vm_exec_control & | |
8684 | CPU_BASED_CR8_STORE_EXITING) | |
1d804d07 | 8685 | return true; |
644d711a NHE |
8686 | break; |
8687 | } | |
8688 | break; | |
8689 | case 3: /* lmsw */ | |
8690 | /* | |
8691 | * lmsw can change bits 1..3 of cr0, and only set bit 0 of | |
8692 | * cr0. Other attempted changes are ignored, with no exit. | |
8693 | */ | |
e1d39b17 | 8694 | val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f; |
644d711a NHE |
8695 | if (vmcs12->cr0_guest_host_mask & 0xe & |
8696 | (val ^ vmcs12->cr0_read_shadow)) | |
1d804d07 | 8697 | return true; |
644d711a NHE |
8698 | if ((vmcs12->cr0_guest_host_mask & 0x1) && |
8699 | !(vmcs12->cr0_read_shadow & 0x1) && | |
8700 | (val & 0x1)) | |
1d804d07 | 8701 | return true; |
644d711a NHE |
8702 | break; |
8703 | } | |
1d804d07 | 8704 | return false; |
644d711a NHE |
8705 | } |
8706 | ||
8707 | /* | |
8708 | * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we | |
8709 | * should handle it ourselves in L0 (and then continue L2). Only call this | |
8710 | * when in is_guest_mode (L2). | |
8711 | */ | |
7313c698 | 8712 | static bool nested_vmx_exit_reflected(struct kvm_vcpu *vcpu, u32 exit_reason) |
644d711a | 8713 | { |
644d711a NHE |
8714 | u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO); |
8715 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
8716 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); | |
8717 | ||
4f350c6d JM |
8718 | if (vmx->nested.nested_run_pending) |
8719 | return false; | |
8720 | ||
8721 | if (unlikely(vmx->fail)) { | |
8722 | pr_info_ratelimited("%s failed vm entry %x\n", __func__, | |
8723 | vmcs_read32(VM_INSTRUCTION_ERROR)); | |
8724 | return true; | |
8725 | } | |
542060ea | 8726 | |
c9f04407 DM |
8727 | /* |
8728 | * The host physical addresses of some pages of guest memory | |
8819227c JM |
8729 | * are loaded into the vmcs02 (e.g. vmcs12's Virtual APIC |
8730 | * Page). The CPU may write to these pages via their host | |
8731 | * physical address while L2 is running, bypassing any | |
8732 | * address-translation-based dirty tracking (e.g. EPT write | |
8733 | * protection). | |
c9f04407 DM |
8734 | * |
8735 | * Mark them dirty on every exit from L2 to prevent them from | |
8736 | * getting out of sync with dirty tracking. | |
8737 | */ | |
8738 | nested_mark_vmcs12_pages_dirty(vcpu); | |
8739 | ||
4f350c6d JM |
8740 | trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason, |
8741 | vmcs_readl(EXIT_QUALIFICATION), | |
8742 | vmx->idt_vectoring_info, | |
8743 | intr_info, | |
8744 | vmcs_read32(VM_EXIT_INTR_ERROR_CODE), | |
8745 | KVM_ISA_VMX); | |
644d711a NHE |
8746 | |
8747 | switch (exit_reason) { | |
8748 | case EXIT_REASON_EXCEPTION_NMI: | |
ef85b673 | 8749 | if (is_nmi(intr_info)) |
1d804d07 | 8750 | return false; |
644d711a | 8751 | else if (is_page_fault(intr_info)) |
52a5c155 | 8752 | return !vmx->vcpu.arch.apf.host_apf_reason && enable_ept; |
e504c909 | 8753 | else if (is_no_device(intr_info) && |
ccf9844e | 8754 | !(vmcs12->guest_cr0 & X86_CR0_TS)) |
1d804d07 | 8755 | return false; |
6f05485d JK |
8756 | else if (is_debug(intr_info) && |
8757 | vcpu->guest_debug & | |
8758 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) | |
8759 | return false; | |
8760 | else if (is_breakpoint(intr_info) && | |
8761 | vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP) | |
8762 | return false; | |
644d711a NHE |
8763 | return vmcs12->exception_bitmap & |
8764 | (1u << (intr_info & INTR_INFO_VECTOR_MASK)); | |
8765 | case EXIT_REASON_EXTERNAL_INTERRUPT: | |
1d804d07 | 8766 | return false; |
644d711a | 8767 | case EXIT_REASON_TRIPLE_FAULT: |
1d804d07 | 8768 | return true; |
644d711a | 8769 | case EXIT_REASON_PENDING_INTERRUPT: |
3b656cf7 | 8770 | return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING); |
644d711a | 8771 | case EXIT_REASON_NMI_WINDOW: |
3b656cf7 | 8772 | return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING); |
644d711a | 8773 | case EXIT_REASON_TASK_SWITCH: |
1d804d07 | 8774 | return true; |
644d711a | 8775 | case EXIT_REASON_CPUID: |
1d804d07 | 8776 | return true; |
644d711a NHE |
8777 | case EXIT_REASON_HLT: |
8778 | return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING); | |
8779 | case EXIT_REASON_INVD: | |
1d804d07 | 8780 | return true; |
644d711a NHE |
8781 | case EXIT_REASON_INVLPG: |
8782 | return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING); | |
8783 | case EXIT_REASON_RDPMC: | |
8784 | return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING); | |
a5f46457 | 8785 | case EXIT_REASON_RDRAND: |
736fdf72 | 8786 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDRAND_EXITING); |
a5f46457 | 8787 | case EXIT_REASON_RDSEED: |
736fdf72 | 8788 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDSEED_EXITING); |
b3a2a907 | 8789 | case EXIT_REASON_RDTSC: case EXIT_REASON_RDTSCP: |
644d711a NHE |
8790 | return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING); |
8791 | case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR: | |
8792 | case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD: | |
8793 | case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD: | |
8794 | case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE: | |
8795 | case EXIT_REASON_VMOFF: case EXIT_REASON_VMON: | |
a642fc30 | 8796 | case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID: |
644d711a NHE |
8797 | /* |
8798 | * VMX instructions trap unconditionally. This allows L1 to | |
8799 | * emulate them for its L2 guest, i.e., allows 3-level nesting! | |
8800 | */ | |
1d804d07 | 8801 | return true; |
644d711a NHE |
8802 | case EXIT_REASON_CR_ACCESS: |
8803 | return nested_vmx_exit_handled_cr(vcpu, vmcs12); | |
8804 | case EXIT_REASON_DR_ACCESS: | |
8805 | return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING); | |
8806 | case EXIT_REASON_IO_INSTRUCTION: | |
908a7bdd | 8807 | return nested_vmx_exit_handled_io(vcpu, vmcs12); |
1b07304c PB |
8808 | case EXIT_REASON_GDTR_IDTR: case EXIT_REASON_LDTR_TR: |
8809 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_DESC); | |
644d711a NHE |
8810 | case EXIT_REASON_MSR_READ: |
8811 | case EXIT_REASON_MSR_WRITE: | |
8812 | return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason); | |
8813 | case EXIT_REASON_INVALID_STATE: | |
1d804d07 | 8814 | return true; |
644d711a NHE |
8815 | case EXIT_REASON_MWAIT_INSTRUCTION: |
8816 | return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING); | |
5f3d45e7 MD |
8817 | case EXIT_REASON_MONITOR_TRAP_FLAG: |
8818 | return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_TRAP_FLAG); | |
644d711a NHE |
8819 | case EXIT_REASON_MONITOR_INSTRUCTION: |
8820 | return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING); | |
8821 | case EXIT_REASON_PAUSE_INSTRUCTION: | |
8822 | return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) || | |
8823 | nested_cpu_has2(vmcs12, | |
8824 | SECONDARY_EXEC_PAUSE_LOOP_EXITING); | |
8825 | case EXIT_REASON_MCE_DURING_VMENTRY: | |
1d804d07 | 8826 | return false; |
644d711a | 8827 | case EXIT_REASON_TPR_BELOW_THRESHOLD: |
a7c0b07d | 8828 | return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW); |
644d711a NHE |
8829 | case EXIT_REASON_APIC_ACCESS: |
8830 | return nested_cpu_has2(vmcs12, | |
8831 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES); | |
82f0dd4b | 8832 | case EXIT_REASON_APIC_WRITE: |
608406e2 WV |
8833 | case EXIT_REASON_EOI_INDUCED: |
8834 | /* apic_write and eoi_induced should exit unconditionally. */ | |
1d804d07 | 8835 | return true; |
644d711a | 8836 | case EXIT_REASON_EPT_VIOLATION: |
2b1be677 NHE |
8837 | /* |
8838 | * L0 always deals with the EPT violation. If nested EPT is | |
8839 | * used, and the nested mmu code discovers that the address is | |
8840 | * missing in the guest EPT table (EPT12), the EPT violation | |
8841 | * will be injected with nested_ept_inject_page_fault() | |
8842 | */ | |
1d804d07 | 8843 | return false; |
644d711a | 8844 | case EXIT_REASON_EPT_MISCONFIG: |
2b1be677 NHE |
8845 | /* |
8846 | * L2 never uses directly L1's EPT, but rather L0's own EPT | |
8847 | * table (shadow on EPT) or a merged EPT table that L0 built | |
8848 | * (EPT on EPT). So any problems with the structure of the | |
8849 | * table is L0's fault. | |
8850 | */ | |
1d804d07 | 8851 | return false; |
90a2db6d PB |
8852 | case EXIT_REASON_INVPCID: |
8853 | return | |
8854 | nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_INVPCID) && | |
8855 | nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING); | |
644d711a NHE |
8856 | case EXIT_REASON_WBINVD: |
8857 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING); | |
8858 | case EXIT_REASON_XSETBV: | |
1d804d07 | 8859 | return true; |
81dc01f7 WL |
8860 | case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS: |
8861 | /* | |
8862 | * This should never happen, since it is not possible to | |
8863 | * set XSS to a non-zero value---neither in L1 nor in L2. | |
8864 | * If if it were, XSS would have to be checked against | |
8865 | * the XSS exit bitmap in vmcs12. | |
8866 | */ | |
8867 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES); | |
55123e3c WL |
8868 | case EXIT_REASON_PREEMPTION_TIMER: |
8869 | return false; | |
ab007cc9 | 8870 | case EXIT_REASON_PML_FULL: |
03efce6f | 8871 | /* We emulate PML support to L1. */ |
ab007cc9 | 8872 | return false; |
2a499e49 BD |
8873 | case EXIT_REASON_VMFUNC: |
8874 | /* VM functions are emulated through L2->L0 vmexits. */ | |
8875 | return false; | |
644d711a | 8876 | default: |
1d804d07 | 8877 | return true; |
644d711a NHE |
8878 | } |
8879 | } | |
8880 | ||
7313c698 PB |
8881 | static int nested_vmx_reflect_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason) |
8882 | { | |
8883 | u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO); | |
8884 | ||
8885 | /* | |
8886 | * At this point, the exit interruption info in exit_intr_info | |
8887 | * is only valid for EXCEPTION_NMI exits. For EXTERNAL_INTERRUPT | |
8888 | * we need to query the in-kernel LAPIC. | |
8889 | */ | |
8890 | WARN_ON(exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT); | |
8891 | if ((exit_intr_info & | |
8892 | (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) == | |
8893 | (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) { | |
8894 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); | |
8895 | vmcs12->vm_exit_intr_error_code = | |
8896 | vmcs_read32(VM_EXIT_INTR_ERROR_CODE); | |
8897 | } | |
8898 | ||
8899 | nested_vmx_vmexit(vcpu, exit_reason, exit_intr_info, | |
8900 | vmcs_readl(EXIT_QUALIFICATION)); | |
8901 | return 1; | |
8902 | } | |
8903 | ||
586f9607 AK |
8904 | static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2) |
8905 | { | |
8906 | *info1 = vmcs_readl(EXIT_QUALIFICATION); | |
8907 | *info2 = vmcs_read32(VM_EXIT_INTR_INFO); | |
8908 | } | |
8909 | ||
a3eaa864 | 8910 | static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx) |
843e4330 | 8911 | { |
a3eaa864 KH |
8912 | if (vmx->pml_pg) { |
8913 | __free_page(vmx->pml_pg); | |
8914 | vmx->pml_pg = NULL; | |
8915 | } | |
843e4330 KH |
8916 | } |
8917 | ||
54bf36aa | 8918 | static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu) |
843e4330 | 8919 | { |
54bf36aa | 8920 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
843e4330 KH |
8921 | u64 *pml_buf; |
8922 | u16 pml_idx; | |
8923 | ||
8924 | pml_idx = vmcs_read16(GUEST_PML_INDEX); | |
8925 | ||
8926 | /* Do nothing if PML buffer is empty */ | |
8927 | if (pml_idx == (PML_ENTITY_NUM - 1)) | |
8928 | return; | |
8929 | ||
8930 | /* PML index always points to next available PML buffer entity */ | |
8931 | if (pml_idx >= PML_ENTITY_NUM) | |
8932 | pml_idx = 0; | |
8933 | else | |
8934 | pml_idx++; | |
8935 | ||
8936 | pml_buf = page_address(vmx->pml_pg); | |
8937 | for (; pml_idx < PML_ENTITY_NUM; pml_idx++) { | |
8938 | u64 gpa; | |
8939 | ||
8940 | gpa = pml_buf[pml_idx]; | |
8941 | WARN_ON(gpa & (PAGE_SIZE - 1)); | |
54bf36aa | 8942 | kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT); |
843e4330 KH |
8943 | } |
8944 | ||
8945 | /* reset PML index */ | |
8946 | vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1); | |
8947 | } | |
8948 | ||
8949 | /* | |
8950 | * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap. | |
8951 | * Called before reporting dirty_bitmap to userspace. | |
8952 | */ | |
8953 | static void kvm_flush_pml_buffers(struct kvm *kvm) | |
8954 | { | |
8955 | int i; | |
8956 | struct kvm_vcpu *vcpu; | |
8957 | /* | |
8958 | * We only need to kick vcpu out of guest mode here, as PML buffer | |
8959 | * is flushed at beginning of all VMEXITs, and it's obvious that only | |
8960 | * vcpus running in guest are possible to have unflushed GPAs in PML | |
8961 | * buffer. | |
8962 | */ | |
8963 | kvm_for_each_vcpu(i, vcpu, kvm) | |
8964 | kvm_vcpu_kick(vcpu); | |
8965 | } | |
8966 | ||
4eb64dce PB |
8967 | static void vmx_dump_sel(char *name, uint32_t sel) |
8968 | { | |
8969 | pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n", | |
96794e4e | 8970 | name, vmcs_read16(sel), |
4eb64dce PB |
8971 | vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR), |
8972 | vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR), | |
8973 | vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR)); | |
8974 | } | |
8975 | ||
8976 | static void vmx_dump_dtsel(char *name, uint32_t limit) | |
8977 | { | |
8978 | pr_err("%s limit=0x%08x, base=0x%016lx\n", | |
8979 | name, vmcs_read32(limit), | |
8980 | vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT)); | |
8981 | } | |
8982 | ||
8983 | static void dump_vmcs(void) | |
8984 | { | |
8985 | u32 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS); | |
8986 | u32 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS); | |
8987 | u32 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); | |
8988 | u32 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL); | |
8989 | u32 secondary_exec_control = 0; | |
8990 | unsigned long cr4 = vmcs_readl(GUEST_CR4); | |
f3531054 | 8991 | u64 efer = vmcs_read64(GUEST_IA32_EFER); |
4eb64dce PB |
8992 | int i, n; |
8993 | ||
8994 | if (cpu_has_secondary_exec_ctrls()) | |
8995 | secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL); | |
8996 | ||
8997 | pr_err("*** Guest State ***\n"); | |
8998 | pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n", | |
8999 | vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW), | |
9000 | vmcs_readl(CR0_GUEST_HOST_MASK)); | |
9001 | pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n", | |
9002 | cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK)); | |
9003 | pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3)); | |
9004 | if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) && | |
9005 | (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA)) | |
9006 | { | |
845c5b40 PB |
9007 | pr_err("PDPTR0 = 0x%016llx PDPTR1 = 0x%016llx\n", |
9008 | vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1)); | |
9009 | pr_err("PDPTR2 = 0x%016llx PDPTR3 = 0x%016llx\n", | |
9010 | vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3)); | |
4eb64dce PB |
9011 | } |
9012 | pr_err("RSP = 0x%016lx RIP = 0x%016lx\n", | |
9013 | vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP)); | |
9014 | pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n", | |
9015 | vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7)); | |
9016 | pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n", | |
9017 | vmcs_readl(GUEST_SYSENTER_ESP), | |
9018 | vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP)); | |
9019 | vmx_dump_sel("CS: ", GUEST_CS_SELECTOR); | |
9020 | vmx_dump_sel("DS: ", GUEST_DS_SELECTOR); | |
9021 | vmx_dump_sel("SS: ", GUEST_SS_SELECTOR); | |
9022 | vmx_dump_sel("ES: ", GUEST_ES_SELECTOR); | |
9023 | vmx_dump_sel("FS: ", GUEST_FS_SELECTOR); | |
9024 | vmx_dump_sel("GS: ", GUEST_GS_SELECTOR); | |
9025 | vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT); | |
9026 | vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR); | |
9027 | vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT); | |
9028 | vmx_dump_sel("TR: ", GUEST_TR_SELECTOR); | |
9029 | if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) || | |
9030 | (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER))) | |
845c5b40 PB |
9031 | pr_err("EFER = 0x%016llx PAT = 0x%016llx\n", |
9032 | efer, vmcs_read64(GUEST_IA32_PAT)); | |
9033 | pr_err("DebugCtl = 0x%016llx DebugExceptions = 0x%016lx\n", | |
9034 | vmcs_read64(GUEST_IA32_DEBUGCTL), | |
4eb64dce PB |
9035 | vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS)); |
9036 | if (vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL) | |
845c5b40 PB |
9037 | pr_err("PerfGlobCtl = 0x%016llx\n", |
9038 | vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL)); | |
4eb64dce | 9039 | if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS) |
845c5b40 | 9040 | pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS)); |
4eb64dce PB |
9041 | pr_err("Interruptibility = %08x ActivityState = %08x\n", |
9042 | vmcs_read32(GUEST_INTERRUPTIBILITY_INFO), | |
9043 | vmcs_read32(GUEST_ACTIVITY_STATE)); | |
9044 | if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) | |
9045 | pr_err("InterruptStatus = %04x\n", | |
9046 | vmcs_read16(GUEST_INTR_STATUS)); | |
9047 | ||
9048 | pr_err("*** Host State ***\n"); | |
9049 | pr_err("RIP = 0x%016lx RSP = 0x%016lx\n", | |
9050 | vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP)); | |
9051 | pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n", | |
9052 | vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR), | |
9053 | vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR), | |
9054 | vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR), | |
9055 | vmcs_read16(HOST_TR_SELECTOR)); | |
9056 | pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n", | |
9057 | vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE), | |
9058 | vmcs_readl(HOST_TR_BASE)); | |
9059 | pr_err("GDTBase=%016lx IDTBase=%016lx\n", | |
9060 | vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE)); | |
9061 | pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n", | |
9062 | vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3), | |
9063 | vmcs_readl(HOST_CR4)); | |
9064 | pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n", | |
9065 | vmcs_readl(HOST_IA32_SYSENTER_ESP), | |
9066 | vmcs_read32(HOST_IA32_SYSENTER_CS), | |
9067 | vmcs_readl(HOST_IA32_SYSENTER_EIP)); | |
9068 | if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER)) | |
845c5b40 PB |
9069 | pr_err("EFER = 0x%016llx PAT = 0x%016llx\n", |
9070 | vmcs_read64(HOST_IA32_EFER), | |
9071 | vmcs_read64(HOST_IA32_PAT)); | |
4eb64dce | 9072 | if (vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL) |
845c5b40 PB |
9073 | pr_err("PerfGlobCtl = 0x%016llx\n", |
9074 | vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL)); | |
4eb64dce PB |
9075 | |
9076 | pr_err("*** Control State ***\n"); | |
9077 | pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n", | |
9078 | pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control); | |
9079 | pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl); | |
9080 | pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n", | |
9081 | vmcs_read32(EXCEPTION_BITMAP), | |
9082 | vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK), | |
9083 | vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH)); | |
9084 | pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n", | |
9085 | vmcs_read32(VM_ENTRY_INTR_INFO_FIELD), | |
9086 | vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE), | |
9087 | vmcs_read32(VM_ENTRY_INSTRUCTION_LEN)); | |
9088 | pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n", | |
9089 | vmcs_read32(VM_EXIT_INTR_INFO), | |
9090 | vmcs_read32(VM_EXIT_INTR_ERROR_CODE), | |
9091 | vmcs_read32(VM_EXIT_INSTRUCTION_LEN)); | |
9092 | pr_err(" reason=%08x qualification=%016lx\n", | |
9093 | vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION)); | |
9094 | pr_err("IDTVectoring: info=%08x errcode=%08x\n", | |
9095 | vmcs_read32(IDT_VECTORING_INFO_FIELD), | |
9096 | vmcs_read32(IDT_VECTORING_ERROR_CODE)); | |
845c5b40 | 9097 | pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET)); |
8cfe9866 | 9098 | if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING) |
845c5b40 PB |
9099 | pr_err("TSC Multiplier = 0x%016llx\n", |
9100 | vmcs_read64(TSC_MULTIPLIER)); | |
4eb64dce PB |
9101 | if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW) |
9102 | pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD)); | |
9103 | if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR) | |
9104 | pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV)); | |
9105 | if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT)) | |
845c5b40 | 9106 | pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER)); |
4eb64dce PB |
9107 | n = vmcs_read32(CR3_TARGET_COUNT); |
9108 | for (i = 0; i + 1 < n; i += 4) | |
9109 | pr_err("CR3 target%u=%016lx target%u=%016lx\n", | |
9110 | i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2), | |
9111 | i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2)); | |
9112 | if (i < n) | |
9113 | pr_err("CR3 target%u=%016lx\n", | |
9114 | i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2)); | |
9115 | if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING) | |
9116 | pr_err("PLE Gap=%08x Window=%08x\n", | |
9117 | vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW)); | |
9118 | if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID) | |
9119 | pr_err("Virtual processor ID = 0x%04x\n", | |
9120 | vmcs_read16(VIRTUAL_PROCESSOR_ID)); | |
9121 | } | |
9122 | ||
6aa8b732 AK |
9123 | /* |
9124 | * The guest has exited. See if we can fix it or if we need userspace | |
9125 | * assistance. | |
9126 | */ | |
851ba692 | 9127 | static int vmx_handle_exit(struct kvm_vcpu *vcpu) |
6aa8b732 | 9128 | { |
29bd8a78 | 9129 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
a0861c02 | 9130 | u32 exit_reason = vmx->exit_reason; |
1155f76a | 9131 | u32 vectoring_info = vmx->idt_vectoring_info; |
29bd8a78 | 9132 | |
8b89fe1f PB |
9133 | trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX); |
9134 | ||
843e4330 KH |
9135 | /* |
9136 | * Flush logged GPAs PML buffer, this will make dirty_bitmap more | |
9137 | * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before | |
9138 | * querying dirty_bitmap, we only need to kick all vcpus out of guest | |
9139 | * mode as if vcpus is in root mode, the PML buffer must has been | |
9140 | * flushed already. | |
9141 | */ | |
9142 | if (enable_pml) | |
54bf36aa | 9143 | vmx_flush_pml_buffer(vcpu); |
843e4330 | 9144 | |
80ced186 | 9145 | /* If guest state is invalid, start emulating */ |
14168786 | 9146 | if (vmx->emulation_required) |
80ced186 | 9147 | return handle_invalid_guest_state(vcpu); |
1d5a4d9b | 9148 | |
7313c698 PB |
9149 | if (is_guest_mode(vcpu) && nested_vmx_exit_reflected(vcpu, exit_reason)) |
9150 | return nested_vmx_reflect_vmexit(vcpu, exit_reason); | |
644d711a | 9151 | |
5120702e | 9152 | if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) { |
4eb64dce | 9153 | dump_vmcs(); |
5120702e MG |
9154 | vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY; |
9155 | vcpu->run->fail_entry.hardware_entry_failure_reason | |
9156 | = exit_reason; | |
9157 | return 0; | |
9158 | } | |
9159 | ||
29bd8a78 | 9160 | if (unlikely(vmx->fail)) { |
851ba692 AK |
9161 | vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY; |
9162 | vcpu->run->fail_entry.hardware_entry_failure_reason | |
29bd8a78 AK |
9163 | = vmcs_read32(VM_INSTRUCTION_ERROR); |
9164 | return 0; | |
9165 | } | |
6aa8b732 | 9166 | |
b9bf6882 XG |
9167 | /* |
9168 | * Note: | |
9169 | * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by | |
9170 | * delivery event since it indicates guest is accessing MMIO. | |
9171 | * The vm-exit can be triggered again after return to guest that | |
9172 | * will cause infinite loop. | |
9173 | */ | |
d77c26fc | 9174 | if ((vectoring_info & VECTORING_INFO_VALID_MASK) && |
1439442c | 9175 | (exit_reason != EXIT_REASON_EXCEPTION_NMI && |
60637aac | 9176 | exit_reason != EXIT_REASON_EPT_VIOLATION && |
b244c9fc | 9177 | exit_reason != EXIT_REASON_PML_FULL && |
b9bf6882 XG |
9178 | exit_reason != EXIT_REASON_TASK_SWITCH)) { |
9179 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
9180 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV; | |
70bcd708 | 9181 | vcpu->run->internal.ndata = 3; |
b9bf6882 XG |
9182 | vcpu->run->internal.data[0] = vectoring_info; |
9183 | vcpu->run->internal.data[1] = exit_reason; | |
70bcd708 PB |
9184 | vcpu->run->internal.data[2] = vcpu->arch.exit_qualification; |
9185 | if (exit_reason == EXIT_REASON_EPT_MISCONFIG) { | |
9186 | vcpu->run->internal.ndata++; | |
9187 | vcpu->run->internal.data[3] = | |
9188 | vmcs_read64(GUEST_PHYSICAL_ADDRESS); | |
9189 | } | |
b9bf6882 XG |
9190 | return 0; |
9191 | } | |
3b86cd99 | 9192 | |
d02fcf50 | 9193 | if (unlikely(!enable_vnmi && |
8a1b4392 PB |
9194 | vmx->loaded_vmcs->soft_vnmi_blocked)) { |
9195 | if (vmx_interrupt_allowed(vcpu)) { | |
9196 | vmx->loaded_vmcs->soft_vnmi_blocked = 0; | |
9197 | } else if (vmx->loaded_vmcs->vnmi_blocked_time > 1000000000LL && | |
9198 | vcpu->arch.nmi_pending) { | |
9199 | /* | |
9200 | * This CPU don't support us in finding the end of an | |
9201 | * NMI-blocked window if the guest runs with IRQs | |
9202 | * disabled. So we pull the trigger after 1 s of | |
9203 | * futile waiting, but inform the user about this. | |
9204 | */ | |
9205 | printk(KERN_WARNING "%s: Breaking out of NMI-blocked " | |
9206 | "state on VCPU %d after 1 s timeout\n", | |
9207 | __func__, vcpu->vcpu_id); | |
9208 | vmx->loaded_vmcs->soft_vnmi_blocked = 0; | |
9209 | } | |
9210 | } | |
9211 | ||
6aa8b732 AK |
9212 | if (exit_reason < kvm_vmx_max_exit_handlers |
9213 | && kvm_vmx_exit_handlers[exit_reason]) | |
851ba692 | 9214 | return kvm_vmx_exit_handlers[exit_reason](vcpu); |
6aa8b732 | 9215 | else { |
6c6c5e03 RK |
9216 | vcpu_unimpl(vcpu, "vmx: unexpected exit reason 0x%x\n", |
9217 | exit_reason); | |
2bc19dc3 MT |
9218 | kvm_queue_exception(vcpu, UD_VECTOR); |
9219 | return 1; | |
6aa8b732 | 9220 | } |
6aa8b732 AK |
9221 | } |
9222 | ||
d665f9fc PB |
9223 | /* |
9224 | * Software based L1D cache flush which is used when microcode providing | |
9225 | * the cache control MSR is not loaded. | |
9226 | * | |
9227 | * The L1D cache is 32 KiB on Nehalem and later microarchitectures, but to | |
9228 | * flush it is required to read in 64 KiB because the replacement algorithm | |
9229 | * is not exactly LRU. This could be sized at runtime via topology | |
9230 | * information but as all relevant affected CPUs have 32KiB L1D cache size | |
9231 | * there is no point in doing so. | |
9232 | */ | |
f0ace387 | 9233 | static void vmx_l1d_flush(struct kvm_vcpu *vcpu) |
d665f9fc PB |
9234 | { |
9235 | int size = PAGE_SIZE << L1D_CACHE_ORDER; | |
f0ace387 PB |
9236 | |
9237 | /* | |
1384247a TG |
9238 | * This code is only executed when the the flush mode is 'cond' or |
9239 | * 'always' | |
f0ace387 | 9240 | */ |
12960b11 | 9241 | if (static_branch_likely(&vmx_l1d_flush_cond)) { |
64947f95 | 9242 | bool flush_l1d; |
bcbe4077 | 9243 | |
07edf60a | 9244 | /* |
64947f95 NS |
9245 | * Clear the per-vcpu flush bit, it gets set again |
9246 | * either from vcpu_run() or from one of the unsafe | |
9247 | * VMEXIT handlers. | |
07edf60a | 9248 | */ |
64947f95 | 9249 | flush_l1d = vcpu->arch.l1tf_flush_l1d; |
ae021965 | 9250 | vcpu->arch.l1tf_flush_l1d = false; |
64947f95 NS |
9251 | |
9252 | /* | |
9253 | * Clear the per-cpu flush bit, it gets set again from | |
9254 | * the interrupt handlers. | |
9255 | */ | |
9256 | flush_l1d |= kvm_get_cpu_l1tf_flush_l1d(); | |
9257 | kvm_clear_cpu_l1tf_flush_l1d(); | |
9258 | ||
bcbe4077 NS |
9259 | if (!flush_l1d) |
9260 | return; | |
07edf60a | 9261 | } |
f0ace387 PB |
9262 | |
9263 | vcpu->stat.l1d_flush++; | |
d665f9fc | 9264 | |
8e494dea PB |
9265 | if (static_cpu_has(X86_FEATURE_FLUSH_L1D)) { |
9266 | wrmsrl(MSR_IA32_FLUSH_CMD, L1D_FLUSH); | |
9267 | return; | |
9268 | } | |
9269 | ||
d665f9fc PB |
9270 | asm volatile( |
9271 | /* First ensure the pages are in the TLB */ | |
9272 | "xorl %%eax, %%eax\n" | |
9273 | ".Lpopulate_tlb:\n\t" | |
55bd6950 | 9274 | "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t" |
d665f9fc PB |
9275 | "addl $4096, %%eax\n\t" |
9276 | "cmpl %%eax, %[size]\n\t" | |
9277 | "jne .Lpopulate_tlb\n\t" | |
9278 | "xorl %%eax, %%eax\n\t" | |
9279 | "cpuid\n\t" | |
9280 | /* Now fill the cache */ | |
9281 | "xorl %%eax, %%eax\n" | |
9282 | ".Lfill_cache:\n" | |
55bd6950 | 9283 | "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t" |
d665f9fc PB |
9284 | "addl $64, %%eax\n\t" |
9285 | "cmpl %%eax, %[size]\n\t" | |
9286 | "jne .Lfill_cache\n\t" | |
9287 | "lfence\n" | |
55bd6950 | 9288 | :: [flush_pages] "r" (vmx_l1d_flush_pages), |
d665f9fc PB |
9289 | [size] "r" (size) |
9290 | : "eax", "ebx", "ecx", "edx"); | |
9291 | } | |
9292 | ||
95ba8273 | 9293 | static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr) |
6e5d865c | 9294 | { |
a7c0b07d WL |
9295 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); |
9296 | ||
9297 | if (is_guest_mode(vcpu) && | |
9298 | nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) | |
9299 | return; | |
9300 | ||
95ba8273 | 9301 | if (irr == -1 || tpr < irr) { |
6e5d865c YS |
9302 | vmcs_write32(TPR_THRESHOLD, 0); |
9303 | return; | |
9304 | } | |
9305 | ||
95ba8273 | 9306 | vmcs_write32(TPR_THRESHOLD, irr); |
6e5d865c YS |
9307 | } |
9308 | ||
d3f4c0a5 | 9309 | static void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu) |
8d14695f YZ |
9310 | { |
9311 | u32 sec_exec_control; | |
9312 | ||
d3f4c0a5 JM |
9313 | if (!lapic_in_kernel(vcpu)) |
9314 | return; | |
9315 | ||
dccbfcf5 RK |
9316 | /* Postpone execution until vmcs01 is the current VMCS. */ |
9317 | if (is_guest_mode(vcpu)) { | |
d3f4c0a5 | 9318 | to_vmx(vcpu)->nested.change_vmcs01_virtual_apic_mode = true; |
dccbfcf5 RK |
9319 | return; |
9320 | } | |
9321 | ||
35754c98 | 9322 | if (!cpu_need_tpr_shadow(vcpu)) |
8d14695f YZ |
9323 | return; |
9324 | ||
9325 | sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL); | |
d3f4c0a5 JM |
9326 | sec_exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | |
9327 | SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE); | |
8d14695f | 9328 | |
d3f4c0a5 JM |
9329 | switch (kvm_get_apic_mode(vcpu)) { |
9330 | case LAPIC_MODE_INVALID: | |
9331 | WARN_ONCE(true, "Invalid local APIC state"); | |
9332 | case LAPIC_MODE_DISABLED: | |
9333 | break; | |
9334 | case LAPIC_MODE_XAPIC: | |
9335 | if (flexpriority_enabled) { | |
9336 | sec_exec_control |= | |
9337 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; | |
9338 | vmx_flush_tlb(vcpu, true); | |
9339 | } | |
9340 | break; | |
9341 | case LAPIC_MODE_X2APIC: | |
9342 | if (cpu_has_vmx_virtualize_x2apic_mode()) | |
9343 | sec_exec_control |= | |
9344 | SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE; | |
9345 | break; | |
8d14695f YZ |
9346 | } |
9347 | vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control); | |
9348 | ||
4b0be90f | 9349 | vmx_update_msr_bitmap(vcpu); |
8d14695f YZ |
9350 | } |
9351 | ||
38b99173 TC |
9352 | static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa) |
9353 | { | |
9354 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
9355 | ||
9356 | /* | |
9357 | * Currently we do not handle the nested case where L2 has an | |
9358 | * APIC access page of its own; that page is still pinned. | |
9359 | * Hence, we skip the case where the VCPU is in guest mode _and_ | |
9360 | * L1 prepared an APIC access page for L2. | |
9361 | * | |
9362 | * For the case where L1 and L2 share the same APIC access page | |
9363 | * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear | |
9364 | * in the vmcs12), this function will only update either the vmcs01 | |
9365 | * or the vmcs02. If the former, the vmcs02 will be updated by | |
9366 | * prepare_vmcs02. If the latter, the vmcs01 will be updated in | |
9367 | * the next L2->L1 exit. | |
9368 | */ | |
9369 | if (!is_guest_mode(vcpu) || | |
4f2777bc | 9370 | !nested_cpu_has2(get_vmcs12(&vmx->vcpu), |
fb6c8198 | 9371 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) { |
38b99173 | 9372 | vmcs_write64(APIC_ACCESS_ADDR, hpa); |
6bf41e55 | 9373 | vmx_flush_tlb(vcpu, true); |
fb6c8198 | 9374 | } |
38b99173 TC |
9375 | } |
9376 | ||
67c9dddc | 9377 | static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr) |
c7c9c56c YZ |
9378 | { |
9379 | u16 status; | |
9380 | u8 old; | |
9381 | ||
67c9dddc PB |
9382 | if (max_isr == -1) |
9383 | max_isr = 0; | |
c7c9c56c YZ |
9384 | |
9385 | status = vmcs_read16(GUEST_INTR_STATUS); | |
9386 | old = status >> 8; | |
67c9dddc | 9387 | if (max_isr != old) { |
c7c9c56c | 9388 | status &= 0xff; |
67c9dddc | 9389 | status |= max_isr << 8; |
c7c9c56c YZ |
9390 | vmcs_write16(GUEST_INTR_STATUS, status); |
9391 | } | |
9392 | } | |
9393 | ||
9394 | static void vmx_set_rvi(int vector) | |
9395 | { | |
9396 | u16 status; | |
9397 | u8 old; | |
9398 | ||
4114c27d WW |
9399 | if (vector == -1) |
9400 | vector = 0; | |
9401 | ||
c7c9c56c YZ |
9402 | status = vmcs_read16(GUEST_INTR_STATUS); |
9403 | old = (u8)status & 0xff; | |
9404 | if ((u8)vector != old) { | |
9405 | status &= ~0xff; | |
9406 | status |= (u8)vector; | |
9407 | vmcs_write16(GUEST_INTR_STATUS, status); | |
9408 | } | |
9409 | } | |
9410 | ||
9411 | static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr) | |
9412 | { | |
4114c27d WW |
9413 | if (!is_guest_mode(vcpu)) { |
9414 | vmx_set_rvi(max_irr); | |
9415 | return; | |
9416 | } | |
9417 | ||
c7c9c56c YZ |
9418 | if (max_irr == -1) |
9419 | return; | |
9420 | ||
963fee16 | 9421 | /* |
4114c27d WW |
9422 | * In guest mode. If a vmexit is needed, vmx_check_nested_events |
9423 | * handles it. | |
963fee16 | 9424 | */ |
4114c27d | 9425 | if (nested_exit_on_intr(vcpu)) |
963fee16 WL |
9426 | return; |
9427 | ||
963fee16 | 9428 | /* |
4114c27d | 9429 | * Else, fall back to pre-APICv interrupt injection since L2 |
963fee16 WL |
9430 | * is run without virtual interrupt delivery. |
9431 | */ | |
9432 | if (!kvm_event_needs_reinjection(vcpu) && | |
9433 | vmx_interrupt_allowed(vcpu)) { | |
9434 | kvm_queue_interrupt(vcpu, max_irr, false); | |
9435 | vmx_inject_irq(vcpu); | |
9436 | } | |
c7c9c56c YZ |
9437 | } |
9438 | ||
76dfafd5 | 9439 | static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu) |
810e6def PB |
9440 | { |
9441 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
76dfafd5 | 9442 | int max_irr; |
810e6def | 9443 | |
76dfafd5 PB |
9444 | WARN_ON(!vcpu->arch.apicv_active); |
9445 | if (pi_test_on(&vmx->pi_desc)) { | |
9446 | pi_clear_on(&vmx->pi_desc); | |
9447 | /* | |
9448 | * IOMMU can write to PIR.ON, so the barrier matters even on UP. | |
9449 | * But on x86 this is just a compiler barrier anyway. | |
9450 | */ | |
9451 | smp_mb__after_atomic(); | |
9452 | max_irr = kvm_apic_update_irr(vcpu, vmx->pi_desc.pir); | |
9453 | } else { | |
9454 | max_irr = kvm_lapic_find_highest_irr(vcpu); | |
9455 | } | |
9456 | vmx_hwapic_irr_update(vcpu, max_irr); | |
9457 | return max_irr; | |
810e6def PB |
9458 | } |
9459 | ||
050ee5a5 WL |
9460 | static bool vmx_dy_apicv_has_pending_interrupt(struct kvm_vcpu *vcpu) |
9461 | { | |
9462 | return pi_test_on(vcpu_to_pi_desc(vcpu)); | |
9463 | } | |
9464 | ||
6308630b | 9465 | static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap) |
c7c9c56c | 9466 | { |
d62caabb | 9467 | if (!kvm_vcpu_apicv_active(vcpu)) |
3d81bc7e YZ |
9468 | return; |
9469 | ||
c7c9c56c YZ |
9470 | vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]); |
9471 | vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]); | |
9472 | vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]); | |
9473 | vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]); | |
9474 | } | |
9475 | ||
967235d3 PB |
9476 | static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu) |
9477 | { | |
9478 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
9479 | ||
9480 | pi_clear_on(&vmx->pi_desc); | |
9481 | memset(vmx->pi_desc.pir, 0, sizeof(vmx->pi_desc.pir)); | |
9482 | } | |
9483 | ||
51aa01d1 | 9484 | static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx) |
cf393f75 | 9485 | { |
7db8a9c1 | 9486 | if (vmx->exit_reason != EXIT_REASON_EXCEPTION_NMI) |
00eba012 AK |
9487 | return; |
9488 | ||
7db8a9c1 | 9489 | vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO); |
a0861c02 | 9490 | |
1261bfa3 | 9491 | /* if exit due to PF check for async PF */ |
7db8a9c1 | 9492 | if (is_page_fault(vmx->exit_intr_info)) |
1261bfa3 WL |
9493 | vmx->vcpu.arch.apf.host_apf_reason = kvm_read_and_reset_pf_reason(); |
9494 | ||
a0861c02 | 9495 | /* Handle machine checks before interrupts are enabled */ |
7db8a9c1 | 9496 | if (is_machine_check(vmx->exit_intr_info)) |
a0861c02 AK |
9497 | kvm_machine_check(); |
9498 | ||
20f65983 | 9499 | /* We need to handle NMIs before interrupts are enabled */ |
7db8a9c1 | 9500 | if (is_nmi(vmx->exit_intr_info)) { |
ff9d07a0 | 9501 | kvm_before_handle_nmi(&vmx->vcpu); |
20f65983 | 9502 | asm("int $2"); |
ff9d07a0 ZY |
9503 | kvm_after_handle_nmi(&vmx->vcpu); |
9504 | } | |
51aa01d1 | 9505 | } |
20f65983 | 9506 | |
a547c6db YZ |
9507 | static void vmx_handle_external_intr(struct kvm_vcpu *vcpu) |
9508 | { | |
9509 | u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO); | |
9510 | ||
a547c6db YZ |
9511 | if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK)) |
9512 | == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) { | |
9513 | unsigned int vector; | |
9514 | unsigned long entry; | |
9515 | gate_desc *desc; | |
9516 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
9517 | #ifdef CONFIG_X86_64 | |
9518 | unsigned long tmp; | |
9519 | #endif | |
9520 | ||
9521 | vector = exit_intr_info & INTR_INFO_VECTOR_MASK; | |
9522 | desc = (gate_desc *)vmx->host_idt_base + vector; | |
64b163fa | 9523 | entry = gate_offset(desc); |
a547c6db YZ |
9524 | asm volatile( |
9525 | #ifdef CONFIG_X86_64 | |
9526 | "mov %%" _ASM_SP ", %[sp]\n\t" | |
9527 | "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t" | |
9528 | "push $%c[ss]\n\t" | |
9529 | "push %[sp]\n\t" | |
9530 | #endif | |
9531 | "pushf\n\t" | |
a547c6db | 9532 | __ASM_SIZE(push) " $%c[cs]\n\t" |
405b60d2 | 9533 | CALL_NOSPEC |
a547c6db YZ |
9534 | : |
9535 | #ifdef CONFIG_X86_64 | |
3f62de5f | 9536 | [sp]"=&r"(tmp), |
a547c6db | 9537 | #endif |
f5caf621 | 9538 | ASM_CALL_CONSTRAINT |
a547c6db | 9539 | : |
405b60d2 | 9540 | THUNK_TARGET(entry), |
a547c6db YZ |
9541 | [ss]"i"(__KERNEL_DS), |
9542 | [cs]"i"(__KERNEL_CS) | |
9543 | ); | |
f2485b3e | 9544 | } |
a547c6db | 9545 | } |
c207aee4 | 9546 | STACK_FRAME_NON_STANDARD(vmx_handle_external_intr); |
a547c6db | 9547 | |
4d5c8a07 | 9548 | static bool vmx_has_emulated_msr(int index) |
6d396b55 | 9549 | { |
4d5c8a07 TL |
9550 | switch (index) { |
9551 | case MSR_IA32_SMBASE: | |
9552 | /* | |
9553 | * We cannot do SMM unless we can run the guest in big | |
9554 | * real mode. | |
9555 | */ | |
9556 | return enable_unrestricted_guest || emulate_invalid_guest_state; | |
9557 | case MSR_AMD64_VIRT_SPEC_CTRL: | |
9558 | /* This is AMD only. */ | |
9559 | return false; | |
9560 | default: | |
9561 | return true; | |
9562 | } | |
6d396b55 PB |
9563 | } |
9564 | ||
da8999d3 LJ |
9565 | static bool vmx_mpx_supported(void) |
9566 | { | |
9567 | return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) && | |
9568 | (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS); | |
9569 | } | |
9570 | ||
55412b2e WL |
9571 | static bool vmx_xsaves_supported(void) |
9572 | { | |
9573 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
9574 | SECONDARY_EXEC_XSAVES; | |
9575 | } | |
9576 | ||
51aa01d1 AK |
9577 | static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx) |
9578 | { | |
c5ca8e57 | 9579 | u32 exit_intr_info; |
51aa01d1 AK |
9580 | bool unblock_nmi; |
9581 | u8 vector; | |
9582 | bool idtv_info_valid; | |
9583 | ||
9584 | idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK; | |
20f65983 | 9585 | |
d02fcf50 | 9586 | if (enable_vnmi) { |
8a1b4392 PB |
9587 | if (vmx->loaded_vmcs->nmi_known_unmasked) |
9588 | return; | |
9589 | /* | |
9590 | * Can't use vmx->exit_intr_info since we're not sure what | |
9591 | * the exit reason is. | |
9592 | */ | |
9593 | exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO); | |
9594 | unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0; | |
9595 | vector = exit_intr_info & INTR_INFO_VECTOR_MASK; | |
9596 | /* | |
9597 | * SDM 3: 27.7.1.2 (September 2008) | |
9598 | * Re-set bit "block by NMI" before VM entry if vmexit caused by | |
9599 | * a guest IRET fault. | |
9600 | * SDM 3: 23.2.2 (September 2008) | |
9601 | * Bit 12 is undefined in any of the following cases: | |
9602 | * If the VM exit sets the valid bit in the IDT-vectoring | |
9603 | * information field. | |
9604 | * If the VM exit is due to a double fault. | |
9605 | */ | |
9606 | if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi && | |
9607 | vector != DF_VECTOR && !idtv_info_valid) | |
9608 | vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, | |
9609 | GUEST_INTR_STATE_NMI); | |
9610 | else | |
9611 | vmx->loaded_vmcs->nmi_known_unmasked = | |
9612 | !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) | |
9613 | & GUEST_INTR_STATE_NMI); | |
9614 | } else if (unlikely(vmx->loaded_vmcs->soft_vnmi_blocked)) | |
9615 | vmx->loaded_vmcs->vnmi_blocked_time += | |
9616 | ktime_to_ns(ktime_sub(ktime_get(), | |
9617 | vmx->loaded_vmcs->entry_time)); | |
51aa01d1 AK |
9618 | } |
9619 | ||
3ab66e8a | 9620 | static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu, |
83422e17 AK |
9621 | u32 idt_vectoring_info, |
9622 | int instr_len_field, | |
9623 | int error_code_field) | |
51aa01d1 | 9624 | { |
51aa01d1 AK |
9625 | u8 vector; |
9626 | int type; | |
9627 | bool idtv_info_valid; | |
9628 | ||
9629 | idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK; | |
668f612f | 9630 | |
3ab66e8a JK |
9631 | vcpu->arch.nmi_injected = false; |
9632 | kvm_clear_exception_queue(vcpu); | |
9633 | kvm_clear_interrupt_queue(vcpu); | |
37b96e98 GN |
9634 | |
9635 | if (!idtv_info_valid) | |
9636 | return; | |
9637 | ||
3ab66e8a | 9638 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
3842d135 | 9639 | |
668f612f AK |
9640 | vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK; |
9641 | type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK; | |
37b96e98 | 9642 | |
64a7ec06 | 9643 | switch (type) { |
37b96e98 | 9644 | case INTR_TYPE_NMI_INTR: |
3ab66e8a | 9645 | vcpu->arch.nmi_injected = true; |
668f612f | 9646 | /* |
7b4a25cb | 9647 | * SDM 3: 27.7.1.2 (September 2008) |
37b96e98 GN |
9648 | * Clear bit "block by NMI" before VM entry if a NMI |
9649 | * delivery faulted. | |
668f612f | 9650 | */ |
3ab66e8a | 9651 | vmx_set_nmi_mask(vcpu, false); |
37b96e98 | 9652 | break; |
37b96e98 | 9653 | case INTR_TYPE_SOFT_EXCEPTION: |
3ab66e8a | 9654 | vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field); |
66fd3f7f GN |
9655 | /* fall through */ |
9656 | case INTR_TYPE_HARD_EXCEPTION: | |
35920a35 | 9657 | if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) { |
83422e17 | 9658 | u32 err = vmcs_read32(error_code_field); |
851eb667 | 9659 | kvm_requeue_exception_e(vcpu, vector, err); |
35920a35 | 9660 | } else |
851eb667 | 9661 | kvm_requeue_exception(vcpu, vector); |
37b96e98 | 9662 | break; |
66fd3f7f | 9663 | case INTR_TYPE_SOFT_INTR: |
3ab66e8a | 9664 | vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field); |
66fd3f7f | 9665 | /* fall through */ |
37b96e98 | 9666 | case INTR_TYPE_EXT_INTR: |
3ab66e8a | 9667 | kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR); |
37b96e98 GN |
9668 | break; |
9669 | default: | |
9670 | break; | |
f7d9238f | 9671 | } |
cf393f75 AK |
9672 | } |
9673 | ||
83422e17 AK |
9674 | static void vmx_complete_interrupts(struct vcpu_vmx *vmx) |
9675 | { | |
3ab66e8a | 9676 | __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info, |
83422e17 AK |
9677 | VM_EXIT_INSTRUCTION_LEN, |
9678 | IDT_VECTORING_ERROR_CODE); | |
9679 | } | |
9680 | ||
b463a6f7 AK |
9681 | static void vmx_cancel_injection(struct kvm_vcpu *vcpu) |
9682 | { | |
3ab66e8a | 9683 | __vmx_complete_interrupts(vcpu, |
b463a6f7 AK |
9684 | vmcs_read32(VM_ENTRY_INTR_INFO_FIELD), |
9685 | VM_ENTRY_INSTRUCTION_LEN, | |
9686 | VM_ENTRY_EXCEPTION_ERROR_CODE); | |
9687 | ||
9688 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); | |
9689 | } | |
9690 | ||
d7cd9796 GN |
9691 | static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx) |
9692 | { | |
9693 | int i, nr_msrs; | |
9694 | struct perf_guest_switch_msr *msrs; | |
9695 | ||
9696 | msrs = perf_guest_get_msrs(&nr_msrs); | |
9697 | ||
9698 | if (!msrs) | |
9699 | return; | |
9700 | ||
9701 | for (i = 0; i < nr_msrs; i++) | |
9702 | if (msrs[i].host == msrs[i].guest) | |
9703 | clear_atomic_switch_msr(vmx, msrs[i].msr); | |
9704 | else | |
9705 | add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest, | |
129ce7ac | 9706 | msrs[i].host, false); |
d7cd9796 GN |
9707 | } |
9708 | ||
33365e7a | 9709 | static void vmx_arm_hv_timer(struct kvm_vcpu *vcpu) |
64672c95 YJ |
9710 | { |
9711 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
9712 | u64 tscl; | |
9713 | u32 delta_tsc; | |
9714 | ||
9715 | if (vmx->hv_deadline_tsc == -1) | |
9716 | return; | |
9717 | ||
9718 | tscl = rdtsc(); | |
9719 | if (vmx->hv_deadline_tsc > tscl) | |
9720 | /* sure to be 32 bit only because checked on set_hv_timer */ | |
9721 | delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >> | |
9722 | cpu_preemption_timer_multi); | |
9723 | else | |
9724 | delta_tsc = 0; | |
9725 | ||
9726 | vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc); | |
9727 | } | |
9728 | ||
a3b5ba49 | 9729 | static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu) |
6aa8b732 | 9730 | { |
a2fa3e9f | 9731 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
d6e41f11 | 9732 | unsigned long debugctlmsr, cr3, cr4; |
104f226b | 9733 | |
8a1b4392 | 9734 | /* Record the guest's net vcpu time for enforced NMI injections. */ |
d02fcf50 | 9735 | if (unlikely(!enable_vnmi && |
8a1b4392 PB |
9736 | vmx->loaded_vmcs->soft_vnmi_blocked)) |
9737 | vmx->loaded_vmcs->entry_time = ktime_get(); | |
9738 | ||
104f226b AK |
9739 | /* Don't enter VMX if guest state is invalid, let the exit handler |
9740 | start emulation until we arrive back to a valid state */ | |
14168786 | 9741 | if (vmx->emulation_required) |
104f226b AK |
9742 | return; |
9743 | ||
a7653ecd RK |
9744 | if (vmx->ple_window_dirty) { |
9745 | vmx->ple_window_dirty = false; | |
9746 | vmcs_write32(PLE_WINDOW, vmx->ple_window); | |
9747 | } | |
9748 | ||
012f83cb AG |
9749 | if (vmx->nested.sync_shadow_vmcs) { |
9750 | copy_vmcs12_to_shadow(vmx); | |
9751 | vmx->nested.sync_shadow_vmcs = false; | |
9752 | } | |
9753 | ||
104f226b AK |
9754 | if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty)) |
9755 | vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]); | |
9756 | if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty)) | |
9757 | vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]); | |
9758 | ||
d6e41f11 | 9759 | cr3 = __get_current_cr3_fast(); |
44889942 | 9760 | if (unlikely(cr3 != vmx->loaded_vmcs->vmcs_host_cr3)) { |
d6e41f11 | 9761 | vmcs_writel(HOST_CR3, cr3); |
44889942 | 9762 | vmx->loaded_vmcs->vmcs_host_cr3 = cr3; |
d6e41f11 AL |
9763 | } |
9764 | ||
1e02ce4c | 9765 | cr4 = cr4_read_shadow(); |
44889942 | 9766 | if (unlikely(cr4 != vmx->loaded_vmcs->vmcs_host_cr4)) { |
d974baa3 | 9767 | vmcs_writel(HOST_CR4, cr4); |
44889942 | 9768 | vmx->loaded_vmcs->vmcs_host_cr4 = cr4; |
d974baa3 AL |
9769 | } |
9770 | ||
104f226b AK |
9771 | /* When single-stepping over STI and MOV SS, we must clear the |
9772 | * corresponding interruptibility bits in the guest state. Otherwise | |
9773 | * vmentry fails as it then expects bit 14 (BS) in pending debug | |
9774 | * exceptions being set, but that's not correct for the guest debugging | |
9775 | * case. */ | |
9776 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) | |
9777 | vmx_set_interrupt_shadow(vcpu, 0); | |
9778 | ||
54bafc23 WC |
9779 | kvm_load_guest_xcr0(vcpu); |
9780 | ||
b9dd21e1 PB |
9781 | if (static_cpu_has(X86_FEATURE_PKU) && |
9782 | kvm_read_cr4_bits(vcpu, X86_CR4_PKE) && | |
9783 | vcpu->arch.pkru != vmx->host_pkru) | |
9784 | __write_pkru(vcpu->arch.pkru); | |
1be0e61c | 9785 | |
d7cd9796 | 9786 | atomic_switch_perf_msrs(vmx); |
2a7921b7 | 9787 | debugctlmsr = get_debugctlmsr(); |
d7cd9796 | 9788 | |
64672c95 YJ |
9789 | vmx_arm_hv_timer(vcpu); |
9790 | ||
74469996 KA |
9791 | /* |
9792 | * If this vCPU has touched SPEC_CTRL, restore the guest's value if | |
9793 | * it's non-zero. Since vmentry is serialising on affected CPUs, there | |
9794 | * is no need to worry about the conditional branch over the wrmsr | |
9795 | * being speculatively taken. | |
9796 | */ | |
692b5d07 | 9797 | x86_spec_ctrl_set_guest(vmx->spec_ctrl, 0); |
74469996 | 9798 | |
d462b819 | 9799 | vmx->__launched = vmx->loaded_vmcs->launched; |
f0ace387 | 9800 | |
c7ed1048 | 9801 | /* L1D Flush includes CPU buffer clear to mitigate MDS */ |
bcbe4077 NS |
9802 | if (static_branch_unlikely(&vmx_l1d_should_flush)) |
9803 | vmx_l1d_flush(vcpu); | |
abf9852b TG |
9804 | else if (static_branch_unlikely(&mds_user_clear)) |
9805 | mds_clear_cpu_buffers(); | |
f0ace387 | 9806 | |
104f226b | 9807 | asm( |
6aa8b732 | 9808 | /* Store host registers */ |
b188c81f AK |
9809 | "push %%" _ASM_DX "; push %%" _ASM_BP ";" |
9810 | "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */ | |
9811 | "push %%" _ASM_CX " \n\t" | |
9812 | "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t" | |
313dbd49 | 9813 | "je 1f \n\t" |
b188c81f | 9814 | "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t" |
4ecac3fd | 9815 | __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t" |
313dbd49 | 9816 | "1: \n\t" |
d3edefc0 | 9817 | /* Reload cr2 if changed */ |
b188c81f AK |
9818 | "mov %c[cr2](%0), %%" _ASM_AX " \n\t" |
9819 | "mov %%cr2, %%" _ASM_DX " \n\t" | |
9820 | "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t" | |
d3edefc0 | 9821 | "je 2f \n\t" |
b188c81f | 9822 | "mov %%" _ASM_AX", %%cr2 \n\t" |
d3edefc0 | 9823 | "2: \n\t" |
6aa8b732 | 9824 | /* Check if vmlaunch of vmresume is needed */ |
61ce5ca0 | 9825 | "cmpb $0, %c[launched](%0) \n\t" |
6aa8b732 | 9826 | /* Load guest registers. Don't clobber flags. */ |
b188c81f AK |
9827 | "mov %c[rax](%0), %%" _ASM_AX " \n\t" |
9828 | "mov %c[rbx](%0), %%" _ASM_BX " \n\t" | |
9829 | "mov %c[rdx](%0), %%" _ASM_DX " \n\t" | |
9830 | "mov %c[rsi](%0), %%" _ASM_SI " \n\t" | |
9831 | "mov %c[rdi](%0), %%" _ASM_DI " \n\t" | |
9832 | "mov %c[rbp](%0), %%" _ASM_BP " \n\t" | |
05b3e0c2 | 9833 | #ifdef CONFIG_X86_64 |
e08aa78a AK |
9834 | "mov %c[r8](%0), %%r8 \n\t" |
9835 | "mov %c[r9](%0), %%r9 \n\t" | |
9836 | "mov %c[r10](%0), %%r10 \n\t" | |
9837 | "mov %c[r11](%0), %%r11 \n\t" | |
9838 | "mov %c[r12](%0), %%r12 \n\t" | |
9839 | "mov %c[r13](%0), %%r13 \n\t" | |
9840 | "mov %c[r14](%0), %%r14 \n\t" | |
9841 | "mov %c[r15](%0), %%r15 \n\t" | |
6aa8b732 | 9842 | #endif |
b188c81f | 9843 | "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */ |
c801949d | 9844 | |
6aa8b732 | 9845 | /* Enter guest mode */ |
83287ea4 | 9846 | "jne 1f \n\t" |
4ecac3fd | 9847 | __ex(ASM_VMX_VMLAUNCH) "\n\t" |
83287ea4 AK |
9848 | "jmp 2f \n\t" |
9849 | "1: " __ex(ASM_VMX_VMRESUME) "\n\t" | |
9850 | "2: " | |
6aa8b732 | 9851 | /* Save guest registers, load host registers, keep flags */ |
b188c81f | 9852 | "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t" |
40712fae | 9853 | "pop %0 \n\t" |
0cb5b306 | 9854 | "setbe %c[fail](%0)\n\t" |
b188c81f AK |
9855 | "mov %%" _ASM_AX ", %c[rax](%0) \n\t" |
9856 | "mov %%" _ASM_BX ", %c[rbx](%0) \n\t" | |
9857 | __ASM_SIZE(pop) " %c[rcx](%0) \n\t" | |
9858 | "mov %%" _ASM_DX ", %c[rdx](%0) \n\t" | |
9859 | "mov %%" _ASM_SI ", %c[rsi](%0) \n\t" | |
9860 | "mov %%" _ASM_DI ", %c[rdi](%0) \n\t" | |
9861 | "mov %%" _ASM_BP ", %c[rbp](%0) \n\t" | |
05b3e0c2 | 9862 | #ifdef CONFIG_X86_64 |
e08aa78a AK |
9863 | "mov %%r8, %c[r8](%0) \n\t" |
9864 | "mov %%r9, %c[r9](%0) \n\t" | |
9865 | "mov %%r10, %c[r10](%0) \n\t" | |
9866 | "mov %%r11, %c[r11](%0) \n\t" | |
9867 | "mov %%r12, %c[r12](%0) \n\t" | |
9868 | "mov %%r13, %c[r13](%0) \n\t" | |
9869 | "mov %%r14, %c[r14](%0) \n\t" | |
9870 | "mov %%r15, %c[r15](%0) \n\t" | |
0cb5b306 JM |
9871 | "xor %%r8d, %%r8d \n\t" |
9872 | "xor %%r9d, %%r9d \n\t" | |
9873 | "xor %%r10d, %%r10d \n\t" | |
9874 | "xor %%r11d, %%r11d \n\t" | |
9875 | "xor %%r12d, %%r12d \n\t" | |
9876 | "xor %%r13d, %%r13d \n\t" | |
9877 | "xor %%r14d, %%r14d \n\t" | |
9878 | "xor %%r15d, %%r15d \n\t" | |
6aa8b732 | 9879 | #endif |
b188c81f AK |
9880 | "mov %%cr2, %%" _ASM_AX " \n\t" |
9881 | "mov %%" _ASM_AX ", %c[cr2](%0) \n\t" | |
c801949d | 9882 | |
0cb5b306 JM |
9883 | "xor %%eax, %%eax \n\t" |
9884 | "xor %%ebx, %%ebx \n\t" | |
9885 | "xor %%esi, %%esi \n\t" | |
9886 | "xor %%edi, %%edi \n\t" | |
b188c81f | 9887 | "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t" |
83287ea4 AK |
9888 | ".pushsection .rodata \n\t" |
9889 | ".global vmx_return \n\t" | |
9890 | "vmx_return: " _ASM_PTR " 2b \n\t" | |
9891 | ".popsection" | |
e08aa78a | 9892 | : : "c"(vmx), "d"((unsigned long)HOST_RSP), |
d462b819 | 9893 | [launched]"i"(offsetof(struct vcpu_vmx, __launched)), |
e08aa78a | 9894 | [fail]"i"(offsetof(struct vcpu_vmx, fail)), |
313dbd49 | 9895 | [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)), |
ad312c7c ZX |
9896 | [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])), |
9897 | [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])), | |
9898 | [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])), | |
9899 | [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])), | |
9900 | [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])), | |
9901 | [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])), | |
9902 | [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])), | |
05b3e0c2 | 9903 | #ifdef CONFIG_X86_64 |
ad312c7c ZX |
9904 | [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])), |
9905 | [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])), | |
9906 | [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])), | |
9907 | [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])), | |
9908 | [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])), | |
9909 | [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])), | |
9910 | [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])), | |
9911 | [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])), | |
6aa8b732 | 9912 | #endif |
40712fae AK |
9913 | [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)), |
9914 | [wordsize]"i"(sizeof(ulong)) | |
c2036300 LV |
9915 | : "cc", "memory" |
9916 | #ifdef CONFIG_X86_64 | |
b188c81f | 9917 | , "rax", "rbx", "rdi", "rsi" |
c2036300 | 9918 | , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" |
b188c81f AK |
9919 | #else |
9920 | , "eax", "ebx", "edi", "esi" | |
c2036300 LV |
9921 | #endif |
9922 | ); | |
6aa8b732 | 9923 | |
74469996 KA |
9924 | /* |
9925 | * We do not use IBRS in the kernel. If this vCPU has used the | |
9926 | * SPEC_CTRL MSR it may have left it on; save the value and | |
9927 | * turn it off. This is much more efficient than blindly adding | |
9928 | * it to the atomic save/restore list. Especially as the former | |
9929 | * (Saving guest MSRs on vmexit) doesn't even exist in KVM. | |
9930 | * | |
9931 | * For non-nested case: | |
9932 | * If the L01 MSR bitmap does not intercept the MSR, then we need to | |
9933 | * save it. | |
9934 | * | |
9935 | * For nested case: | |
9936 | * If the L02 MSR bitmap does not intercept the MSR, then we need to | |
9937 | * save it. | |
9938 | */ | |
481ab71e | 9939 | if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL))) |
f471d71b | 9940 | vmx->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL); |
74469996 | 9941 | |
692b5d07 | 9942 | x86_spec_ctrl_restore_host(vmx->spec_ctrl, 0); |
74469996 | 9943 | |
117cc7a9 DW |
9944 | /* Eliminate branch target predictions from guest mode */ |
9945 | vmexit_fill_RSB(); | |
9946 | ||
2a7921b7 GN |
9947 | /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */ |
9948 | if (debugctlmsr) | |
9949 | update_debugctlmsr(debugctlmsr); | |
9950 | ||
aa67f609 AK |
9951 | #ifndef CONFIG_X86_64 |
9952 | /* | |
9953 | * The sysexit path does not restore ds/es, so we must set them to | |
9954 | * a reasonable value ourselves. | |
9955 | * | |
9956 | * We can't defer this to vmx_load_host_state() since that function | |
9957 | * may be executed in interrupt context, which saves and restore segments | |
9958 | * around it, nullifying its effect. | |
9959 | */ | |
9960 | loadsegment(ds, __USER_DS); | |
9961 | loadsegment(es, __USER_DS); | |
9962 | #endif | |
9963 | ||
6de4f3ad | 9964 | vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP) |
6de12732 | 9965 | | (1 << VCPU_EXREG_RFLAGS) |
aff48baa | 9966 | | (1 << VCPU_EXREG_PDPTR) |
2fb92db1 | 9967 | | (1 << VCPU_EXREG_SEGMENTS) |
aff48baa | 9968 | | (1 << VCPU_EXREG_CR3)); |
5fdbf976 MT |
9969 | vcpu->arch.regs_dirty = 0; |
9970 | ||
1be0e61c XG |
9971 | /* |
9972 | * eager fpu is enabled if PKEY is supported and CR4 is switched | |
9973 | * back on host, so it is safe to read guest PKRU from current | |
9974 | * XSAVE. | |
9975 | */ | |
b9dd21e1 PB |
9976 | if (static_cpu_has(X86_FEATURE_PKU) && |
9977 | kvm_read_cr4_bits(vcpu, X86_CR4_PKE)) { | |
9978 | vcpu->arch.pkru = __read_pkru(); | |
9979 | if (vcpu->arch.pkru != vmx->host_pkru) | |
1be0e61c | 9980 | __write_pkru(vmx->host_pkru); |
1be0e61c XG |
9981 | } |
9982 | ||
e0b890d3 GN |
9983 | /* |
9984 | * the KVM_REQ_EVENT optimization bit is only on for one entry, and if | |
9985 | * we did not inject a still-pending event to L1 now because of | |
9986 | * nested_run_pending, we need to re-enable this bit. | |
9987 | */ | |
9988 | if (vmx->nested.nested_run_pending) | |
9989 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
9990 | ||
54bafc23 WC |
9991 | kvm_put_guest_xcr0(vcpu); |
9992 | ||
e0b890d3 | 9993 | vmx->nested.nested_run_pending = 0; |
b060ca3b JM |
9994 | vmx->idt_vectoring_info = 0; |
9995 | ||
9996 | vmx->exit_reason = vmx->fail ? 0xdead : vmcs_read32(VM_EXIT_REASON); | |
7db8a9c1 SC |
9997 | if ((u16)vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY) |
9998 | kvm_machine_check(); | |
9999 | ||
b060ca3b JM |
10000 | if (vmx->fail || (vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) |
10001 | return; | |
10002 | ||
10003 | vmx->loaded_vmcs->launched = 1; | |
10004 | vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD); | |
e0b890d3 | 10005 | |
51aa01d1 AK |
10006 | vmx_complete_atomic_exit(vmx); |
10007 | vmx_recover_nmi_blocking(vmx); | |
cf393f75 | 10008 | vmx_complete_interrupts(vmx); |
6aa8b732 | 10009 | } |
c207aee4 | 10010 | STACK_FRAME_NON_STANDARD(vmx_vcpu_run); |
6aa8b732 | 10011 | |
1279a6b1 | 10012 | static void vmx_switch_vmcs(struct kvm_vcpu *vcpu, struct loaded_vmcs *vmcs) |
4fa7734c PB |
10013 | { |
10014 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
10015 | int cpu; | |
10016 | ||
1279a6b1 | 10017 | if (vmx->loaded_vmcs == vmcs) |
4fa7734c PB |
10018 | return; |
10019 | ||
10020 | cpu = get_cpu(); | |
4fa7734c | 10021 | vmx_vcpu_put(vcpu); |
8a12167a | 10022 | vmx->loaded_vmcs = vmcs; |
4fa7734c | 10023 | vmx_vcpu_load(vcpu, cpu); |
4fa7734c PB |
10024 | put_cpu(); |
10025 | } | |
10026 | ||
2f1fe811 JM |
10027 | /* |
10028 | * Ensure that the current vmcs of the logical processor is the | |
10029 | * vmcs01 of the vcpu before calling free_nested(). | |
10030 | */ | |
10031 | static void vmx_free_vcpu_nested(struct kvm_vcpu *vcpu) | |
10032 | { | |
10033 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
10034 | int r; | |
10035 | ||
10036 | r = vcpu_load(vcpu); | |
10037 | BUG_ON(r); | |
1279a6b1 | 10038 | vmx_switch_vmcs(vcpu, &vmx->vmcs01); |
2f1fe811 JM |
10039 | free_nested(vmx); |
10040 | vcpu_put(vcpu); | |
10041 | } | |
10042 | ||
6aa8b732 AK |
10043 | static void vmx_free_vcpu(struct kvm_vcpu *vcpu) |
10044 | { | |
fb3f0f51 RR |
10045 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
10046 | ||
843e4330 | 10047 | if (enable_pml) |
a3eaa864 | 10048 | vmx_destroy_pml_buffer(vmx); |
991e7a0e | 10049 | free_vpid(vmx->vpid); |
4fa7734c | 10050 | leave_guest_mode(vcpu); |
2f1fe811 | 10051 | vmx_free_vcpu_nested(vcpu); |
4fa7734c | 10052 | free_loaded_vmcs(vmx->loaded_vmcs); |
fb3f0f51 RR |
10053 | kfree(vmx->guest_msrs); |
10054 | kvm_vcpu_uninit(vcpu); | |
a4770347 | 10055 | kmem_cache_free(kvm_vcpu_cache, vmx); |
6aa8b732 AK |
10056 | } |
10057 | ||
fb3f0f51 | 10058 | static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id) |
6aa8b732 | 10059 | { |
fb3f0f51 | 10060 | int err; |
c16f862d | 10061 | struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL); |
4b0be90f | 10062 | unsigned long *msr_bitmap; |
15ad7146 | 10063 | int cpu; |
6aa8b732 | 10064 | |
a2fa3e9f | 10065 | if (!vmx) |
fb3f0f51 RR |
10066 | return ERR_PTR(-ENOMEM); |
10067 | ||
991e7a0e | 10068 | vmx->vpid = allocate_vpid(); |
2384d2b3 | 10069 | |
fb3f0f51 RR |
10070 | err = kvm_vcpu_init(&vmx->vcpu, kvm, id); |
10071 | if (err) | |
10072 | goto free_vcpu; | |
965b58a5 | 10073 | |
4e59516a PF |
10074 | err = -ENOMEM; |
10075 | ||
10076 | /* | |
10077 | * If PML is turned on, failure on enabling PML just results in failure | |
10078 | * of creating the vcpu, therefore we can simplify PML logic (by | |
10079 | * avoiding dealing with cases, such as enabling PML partially on vcpus | |
10080 | * for the guest, etc. | |
10081 | */ | |
10082 | if (enable_pml) { | |
10083 | vmx->pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO); | |
10084 | if (!vmx->pml_pg) | |
10085 | goto uninit_vcpu; | |
10086 | } | |
10087 | ||
a2fa3e9f | 10088 | vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL); |
03916db9 PB |
10089 | BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0]) |
10090 | > PAGE_SIZE); | |
0123be42 | 10091 | |
4e59516a PF |
10092 | if (!vmx->guest_msrs) |
10093 | goto free_pml; | |
965b58a5 | 10094 | |
b6d7026d PB |
10095 | err = alloc_loaded_vmcs(&vmx->vmcs01); |
10096 | if (err < 0) | |
fb3f0f51 | 10097 | goto free_msrs; |
a2fa3e9f | 10098 | |
4b0be90f PB |
10099 | msr_bitmap = vmx->vmcs01.msr_bitmap; |
10100 | vmx_disable_intercept_for_msr(msr_bitmap, MSR_FS_BASE, MSR_TYPE_RW); | |
10101 | vmx_disable_intercept_for_msr(msr_bitmap, MSR_GS_BASE, MSR_TYPE_RW); | |
10102 | vmx_disable_intercept_for_msr(msr_bitmap, MSR_KERNEL_GS_BASE, MSR_TYPE_RW); | |
10103 | vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_CS, MSR_TYPE_RW); | |
10104 | vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_ESP, MSR_TYPE_RW); | |
10105 | vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_EIP, MSR_TYPE_RW); | |
10106 | vmx->msr_bitmap_mode = 0; | |
10107 | ||
b6d7026d | 10108 | vmx->loaded_vmcs = &vmx->vmcs01; |
15ad7146 AK |
10109 | cpu = get_cpu(); |
10110 | vmx_vcpu_load(&vmx->vcpu, cpu); | |
e48672fa | 10111 | vmx->vcpu.cpu = cpu; |
12d79917 | 10112 | vmx_vcpu_setup(vmx); |
fb3f0f51 | 10113 | vmx_vcpu_put(&vmx->vcpu); |
15ad7146 | 10114 | put_cpu(); |
35754c98 | 10115 | if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) { |
be6d05cf JK |
10116 | err = alloc_apic_access_page(kvm); |
10117 | if (err) | |
5e4a0b3c | 10118 | goto free_vmcs; |
a63cb560 | 10119 | } |
fb3f0f51 | 10120 | |
b927a3ce | 10121 | if (enable_ept) { |
f51770ed TC |
10122 | err = init_rmode_identity_map(kvm); |
10123 | if (err) | |
93ea5388 | 10124 | goto free_vmcs; |
b927a3ce | 10125 | } |
b7ebfb05 | 10126 | |
23f2bb27 | 10127 | if (nested) |
b9c237bb WV |
10128 | nested_vmx_setup_ctls_msrs(vmx); |
10129 | ||
705699a1 | 10130 | vmx->nested.posted_intr_nv = -1; |
a9d30f33 | 10131 | vmx->nested.current_vmptr = -1ull; |
a9d30f33 | 10132 | |
37e4c997 HZ |
10133 | vmx->msr_ia32_feature_control_valid_bits = FEATURE_CONTROL_LOCKED; |
10134 | ||
31afb2ea PB |
10135 | /* |
10136 | * Enforce invariant: pi_desc.nv is always either POSTED_INTR_VECTOR | |
10137 | * or POSTED_INTR_WAKEUP_VECTOR. | |
10138 | */ | |
10139 | vmx->pi_desc.nv = POSTED_INTR_VECTOR; | |
10140 | vmx->pi_desc.sn = 1; | |
10141 | ||
fb3f0f51 RR |
10142 | return &vmx->vcpu; |
10143 | ||
10144 | free_vmcs: | |
5f3fbc34 | 10145 | free_loaded_vmcs(vmx->loaded_vmcs); |
fb3f0f51 | 10146 | free_msrs: |
fb3f0f51 | 10147 | kfree(vmx->guest_msrs); |
4e59516a PF |
10148 | free_pml: |
10149 | vmx_destroy_pml_buffer(vmx); | |
fb3f0f51 RR |
10150 | uninit_vcpu: |
10151 | kvm_vcpu_uninit(&vmx->vcpu); | |
10152 | free_vcpu: | |
991e7a0e | 10153 | free_vpid(vmx->vpid); |
a4770347 | 10154 | kmem_cache_free(kvm_vcpu_cache, vmx); |
fb3f0f51 | 10155 | return ERR_PTR(err); |
6aa8b732 AK |
10156 | } |
10157 | ||
c7ed1048 TH |
10158 | #define L1TF_MSG_SMT "L1TF CPU bug present and SMT on, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n" |
10159 | #define L1TF_MSG_L1D "L1TF CPU bug present and virtualization mitigation disabled, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n" | |
275b72a9 KRW |
10160 | |
10161 | static int vmx_vm_init(struct kvm *kvm) | |
10162 | { | |
24fcb53c JK |
10163 | if (boot_cpu_has(X86_BUG_L1TF) && enable_ept) { |
10164 | switch (l1tf_mitigation) { | |
10165 | case L1TF_MITIGATION_OFF: | |
10166 | case L1TF_MITIGATION_FLUSH_NOWARN: | |
10167 | /* 'I explicitly don't care' is set */ | |
10168 | break; | |
10169 | case L1TF_MITIGATION_FLUSH: | |
10170 | case L1TF_MITIGATION_FLUSH_NOSMT: | |
10171 | case L1TF_MITIGATION_FULL: | |
10172 | /* | |
10173 | * Warn upon starting the first VM in a potentially | |
10174 | * insecure environment. | |
10175 | */ | |
67cd6fac | 10176 | if (sched_smt_active()) |
24fcb53c JK |
10177 | pr_warn_once(L1TF_MSG_SMT); |
10178 | if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER) | |
10179 | pr_warn_once(L1TF_MSG_L1D); | |
10180 | break; | |
10181 | case L1TF_MITIGATION_FULL_FORCE: | |
10182 | /* Flush is enforced */ | |
10183 | break; | |
275b72a9 | 10184 | } |
275b72a9 KRW |
10185 | } |
10186 | return 0; | |
10187 | } | |
10188 | ||
002c7f7c YS |
10189 | static void __init vmx_check_processor_compat(void *rtn) |
10190 | { | |
10191 | struct vmcs_config vmcs_conf; | |
10192 | ||
10193 | *(int *)rtn = 0; | |
10194 | if (setup_vmcs_config(&vmcs_conf) < 0) | |
10195 | *(int *)rtn = -EIO; | |
10196 | if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) { | |
10197 | printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n", | |
10198 | smp_processor_id()); | |
10199 | *(int *)rtn = -EIO; | |
10200 | } | |
10201 | } | |
10202 | ||
4b12f0de | 10203 | static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio) |
64d4d521 | 10204 | { |
b18d5431 XG |
10205 | u8 cache; |
10206 | u64 ipat = 0; | |
4b12f0de | 10207 | |
522c68c4 | 10208 | /* For VT-d and EPT combination |
606decd6 | 10209 | * 1. MMIO: always map as UC |
522c68c4 SY |
10210 | * 2. EPT with VT-d: |
10211 | * a. VT-d without snooping control feature: can't guarantee the | |
606decd6 | 10212 | * result, try to trust guest. |
522c68c4 SY |
10213 | * b. VT-d with snooping control feature: snooping control feature of |
10214 | * VT-d engine can guarantee the cache correctness. Just set it | |
10215 | * to WB to keep consistent with host. So the same as item 3. | |
a19a6d11 | 10216 | * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep |
522c68c4 SY |
10217 | * consistent with host MTRR |
10218 | */ | |
606decd6 PB |
10219 | if (is_mmio) { |
10220 | cache = MTRR_TYPE_UNCACHABLE; | |
10221 | goto exit; | |
10222 | } | |
10223 | ||
10224 | if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) { | |
b18d5431 XG |
10225 | ipat = VMX_EPT_IPAT_BIT; |
10226 | cache = MTRR_TYPE_WRBACK; | |
10227 | goto exit; | |
10228 | } | |
10229 | ||
10230 | if (kvm_read_cr0(vcpu) & X86_CR0_CD) { | |
10231 | ipat = VMX_EPT_IPAT_BIT; | |
0da029ed | 10232 | if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED)) |
fb279950 XG |
10233 | cache = MTRR_TYPE_WRBACK; |
10234 | else | |
10235 | cache = MTRR_TYPE_UNCACHABLE; | |
b18d5431 XG |
10236 | goto exit; |
10237 | } | |
10238 | ||
ff53604b | 10239 | cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn); |
b18d5431 XG |
10240 | |
10241 | exit: | |
10242 | return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat; | |
64d4d521 SY |
10243 | } |
10244 | ||
17cc3935 | 10245 | static int vmx_get_lpage_level(void) |
344f414f | 10246 | { |
878403b7 SY |
10247 | if (enable_ept && !cpu_has_vmx_ept_1g_page()) |
10248 | return PT_DIRECTORY_LEVEL; | |
10249 | else | |
10250 | /* For shadow and EPT supported 1GB page */ | |
10251 | return PT_PDPE_LEVEL; | |
344f414f JR |
10252 | } |
10253 | ||
feda805f XG |
10254 | static void vmcs_set_secondary_exec_control(u32 new_ctl) |
10255 | { | |
10256 | /* | |
10257 | * These bits in the secondary execution controls field | |
10258 | * are dynamic, the others are mostly based on the hypervisor | |
10259 | * architecture and the guest's CPUID. Do not touch the | |
10260 | * dynamic bits. | |
10261 | */ | |
10262 | u32 mask = | |
10263 | SECONDARY_EXEC_SHADOW_VMCS | | |
10264 | SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | | |
10265 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; | |
10266 | ||
10267 | u32 cur_ctl = vmcs_read32(SECONDARY_VM_EXEC_CONTROL); | |
10268 | ||
10269 | vmcs_write32(SECONDARY_VM_EXEC_CONTROL, | |
10270 | (new_ctl & ~mask) | (cur_ctl & mask)); | |
10271 | } | |
10272 | ||
8322ebbb DM |
10273 | /* |
10274 | * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits | |
10275 | * (indicating "allowed-1") if they are supported in the guest's CPUID. | |
10276 | */ | |
10277 | static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu) | |
10278 | { | |
10279 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
10280 | struct kvm_cpuid_entry2 *entry; | |
10281 | ||
10282 | vmx->nested.nested_vmx_cr0_fixed1 = 0xffffffff; | |
10283 | vmx->nested.nested_vmx_cr4_fixed1 = X86_CR4_PCE; | |
10284 | ||
10285 | #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do { \ | |
10286 | if (entry && (entry->_reg & (_cpuid_mask))) \ | |
10287 | vmx->nested.nested_vmx_cr4_fixed1 |= (_cr4_mask); \ | |
10288 | } while (0) | |
10289 | ||
10290 | entry = kvm_find_cpuid_entry(vcpu, 0x1, 0); | |
10291 | cr4_fixed1_update(X86_CR4_VME, edx, bit(X86_FEATURE_VME)); | |
10292 | cr4_fixed1_update(X86_CR4_PVI, edx, bit(X86_FEATURE_VME)); | |
10293 | cr4_fixed1_update(X86_CR4_TSD, edx, bit(X86_FEATURE_TSC)); | |
10294 | cr4_fixed1_update(X86_CR4_DE, edx, bit(X86_FEATURE_DE)); | |
10295 | cr4_fixed1_update(X86_CR4_PSE, edx, bit(X86_FEATURE_PSE)); | |
10296 | cr4_fixed1_update(X86_CR4_PAE, edx, bit(X86_FEATURE_PAE)); | |
10297 | cr4_fixed1_update(X86_CR4_MCE, edx, bit(X86_FEATURE_MCE)); | |
10298 | cr4_fixed1_update(X86_CR4_PGE, edx, bit(X86_FEATURE_PGE)); | |
10299 | cr4_fixed1_update(X86_CR4_OSFXSR, edx, bit(X86_FEATURE_FXSR)); | |
10300 | cr4_fixed1_update(X86_CR4_OSXMMEXCPT, edx, bit(X86_FEATURE_XMM)); | |
10301 | cr4_fixed1_update(X86_CR4_VMXE, ecx, bit(X86_FEATURE_VMX)); | |
10302 | cr4_fixed1_update(X86_CR4_SMXE, ecx, bit(X86_FEATURE_SMX)); | |
10303 | cr4_fixed1_update(X86_CR4_PCIDE, ecx, bit(X86_FEATURE_PCID)); | |
10304 | cr4_fixed1_update(X86_CR4_OSXSAVE, ecx, bit(X86_FEATURE_XSAVE)); | |
10305 | ||
10306 | entry = kvm_find_cpuid_entry(vcpu, 0x7, 0); | |
10307 | cr4_fixed1_update(X86_CR4_FSGSBASE, ebx, bit(X86_FEATURE_FSGSBASE)); | |
10308 | cr4_fixed1_update(X86_CR4_SMEP, ebx, bit(X86_FEATURE_SMEP)); | |
10309 | cr4_fixed1_update(X86_CR4_SMAP, ebx, bit(X86_FEATURE_SMAP)); | |
10310 | cr4_fixed1_update(X86_CR4_PKE, ecx, bit(X86_FEATURE_PKU)); | |
c4ad77e0 | 10311 | cr4_fixed1_update(X86_CR4_UMIP, ecx, bit(X86_FEATURE_UMIP)); |
8322ebbb DM |
10312 | |
10313 | #undef cr4_fixed1_update | |
10314 | } | |
10315 | ||
0e851880 SY |
10316 | static void vmx_cpuid_update(struct kvm_vcpu *vcpu) |
10317 | { | |
4e47c7a6 | 10318 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
4e47c7a6 | 10319 | |
80154d77 PB |
10320 | if (cpu_has_secondary_exec_ctrls()) { |
10321 | vmx_compute_secondary_exec_control(vmx); | |
10322 | vmcs_set_secondary_exec_control(vmx->secondary_exec_control); | |
ad756a16 | 10323 | } |
8b3e34e4 | 10324 | |
37e4c997 HZ |
10325 | if (nested_vmx_allowed(vcpu)) |
10326 | to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |= | |
10327 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX; | |
10328 | else | |
10329 | to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &= | |
10330 | ~FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX; | |
8322ebbb DM |
10331 | |
10332 | if (nested_vmx_allowed(vcpu)) | |
10333 | nested_vmx_cr_fixed1_bits_update(vcpu); | |
0e851880 SY |
10334 | } |
10335 | ||
d4330ef2 JR |
10336 | static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry) |
10337 | { | |
7b8050f5 NHE |
10338 | if (func == 1 && nested) |
10339 | entry->ecx |= bit(X86_FEATURE_VMX); | |
d4330ef2 JR |
10340 | } |
10341 | ||
25d92081 YZ |
10342 | static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu, |
10343 | struct x86_exception *fault) | |
10344 | { | |
533558bc | 10345 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); |
c5f983f6 | 10346 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
533558bc | 10347 | u32 exit_reason; |
c5f983f6 | 10348 | unsigned long exit_qualification = vcpu->arch.exit_qualification; |
25d92081 | 10349 | |
c5f983f6 BD |
10350 | if (vmx->nested.pml_full) { |
10351 | exit_reason = EXIT_REASON_PML_FULL; | |
10352 | vmx->nested.pml_full = false; | |
10353 | exit_qualification &= INTR_INFO_UNBLOCK_NMI; | |
10354 | } else if (fault->error_code & PFERR_RSVD_MASK) | |
533558bc | 10355 | exit_reason = EXIT_REASON_EPT_MISCONFIG; |
25d92081 | 10356 | else |
533558bc | 10357 | exit_reason = EXIT_REASON_EPT_VIOLATION; |
c5f983f6 BD |
10358 | |
10359 | nested_vmx_vmexit(vcpu, exit_reason, 0, exit_qualification); | |
25d92081 YZ |
10360 | vmcs12->guest_physical_address = fault->address; |
10361 | } | |
10362 | ||
995f00a6 PF |
10363 | static bool nested_ept_ad_enabled(struct kvm_vcpu *vcpu) |
10364 | { | |
bb97a016 | 10365 | return nested_ept_get_cr3(vcpu) & VMX_EPTP_AD_ENABLE_BIT; |
995f00a6 PF |
10366 | } |
10367 | ||
155a97a3 NHE |
10368 | /* Callbacks for nested_ept_init_mmu_context: */ |
10369 | ||
10370 | static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu) | |
10371 | { | |
10372 | /* return the page table to be shadowed - in our case, EPT12 */ | |
10373 | return get_vmcs12(vcpu)->ept_pointer; | |
10374 | } | |
10375 | ||
ae1e2d10 | 10376 | static int nested_ept_init_mmu_context(struct kvm_vcpu *vcpu) |
155a97a3 | 10377 | { |
ad896af0 | 10378 | WARN_ON(mmu_is_nested(vcpu)); |
a057e0e2 | 10379 | if (!valid_ept_address(vcpu, nested_ept_get_cr3(vcpu))) |
ae1e2d10 PB |
10380 | return 1; |
10381 | ||
10382 | kvm_mmu_unload(vcpu); | |
ad896af0 | 10383 | kvm_init_shadow_ept_mmu(vcpu, |
b9c237bb | 10384 | to_vmx(vcpu)->nested.nested_vmx_ept_caps & |
ae1e2d10 | 10385 | VMX_EPT_EXECUTE_ONLY_BIT, |
a057e0e2 | 10386 | nested_ept_ad_enabled(vcpu)); |
155a97a3 NHE |
10387 | vcpu->arch.mmu.set_cr3 = vmx_set_cr3; |
10388 | vcpu->arch.mmu.get_cr3 = nested_ept_get_cr3; | |
10389 | vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault; | |
10390 | ||
10391 | vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu; | |
ae1e2d10 | 10392 | return 0; |
155a97a3 NHE |
10393 | } |
10394 | ||
10395 | static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu) | |
10396 | { | |
10397 | vcpu->arch.walk_mmu = &vcpu->arch.mmu; | |
10398 | } | |
10399 | ||
19d5f10b EK |
10400 | static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12, |
10401 | u16 error_code) | |
10402 | { | |
10403 | bool inequality, bit; | |
10404 | ||
10405 | bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0; | |
10406 | inequality = | |
10407 | (error_code & vmcs12->page_fault_error_code_mask) != | |
10408 | vmcs12->page_fault_error_code_match; | |
10409 | return inequality ^ bit; | |
10410 | } | |
10411 | ||
feaf0c7d GN |
10412 | static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu, |
10413 | struct x86_exception *fault) | |
10414 | { | |
10415 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); | |
10416 | ||
10417 | WARN_ON(!is_guest_mode(vcpu)); | |
10418 | ||
305d0ab4 WL |
10419 | if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code) && |
10420 | !to_vmx(vcpu)->nested.nested_run_pending) { | |
b96fb439 PB |
10421 | vmcs12->vm_exit_intr_error_code = fault->error_code; |
10422 | nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI, | |
10423 | PF_VECTOR | INTR_TYPE_HARD_EXCEPTION | | |
10424 | INTR_INFO_DELIVER_CODE_MASK | INTR_INFO_VALID_MASK, | |
10425 | fault->address); | |
7313c698 | 10426 | } else { |
feaf0c7d | 10427 | kvm_inject_page_fault(vcpu, fault); |
7313c698 | 10428 | } |
feaf0c7d GN |
10429 | } |
10430 | ||
6beb7bd5 JM |
10431 | static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu, |
10432 | struct vmcs12 *vmcs12); | |
10433 | ||
10434 | static void nested_get_vmcs12_pages(struct kvm_vcpu *vcpu, | |
a2bcba50 WL |
10435 | struct vmcs12 *vmcs12) |
10436 | { | |
10437 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
5e2f30b7 | 10438 | struct page *page; |
6beb7bd5 | 10439 | u64 hpa; |
a2bcba50 WL |
10440 | |
10441 | if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) { | |
a2bcba50 WL |
10442 | /* |
10443 | * Translate L1 physical address to host physical | |
10444 | * address for vmcs02. Keep the page pinned, so this | |
10445 | * physical address remains valid. We keep a reference | |
10446 | * to it so we can release it later. | |
10447 | */ | |
5e2f30b7 | 10448 | if (vmx->nested.apic_access_page) { /* shouldn't happen */ |
53a70daf | 10449 | kvm_release_page_dirty(vmx->nested.apic_access_page); |
5e2f30b7 DH |
10450 | vmx->nested.apic_access_page = NULL; |
10451 | } | |
10452 | page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->apic_access_addr); | |
6beb7bd5 JM |
10453 | /* |
10454 | * If translation failed, no matter: This feature asks | |
10455 | * to exit when accessing the given address, and if it | |
10456 | * can never be accessed, this feature won't do | |
10457 | * anything anyway. | |
10458 | */ | |
5e2f30b7 DH |
10459 | if (!is_error_page(page)) { |
10460 | vmx->nested.apic_access_page = page; | |
6beb7bd5 JM |
10461 | hpa = page_to_phys(vmx->nested.apic_access_page); |
10462 | vmcs_write64(APIC_ACCESS_ADDR, hpa); | |
10463 | } else { | |
10464 | vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL, | |
10465 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES); | |
10466 | } | |
10467 | } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12)) && | |
10468 | cpu_need_virtualize_apic_accesses(&vmx->vcpu)) { | |
10469 | vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL, | |
10470 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES); | |
10471 | kvm_vcpu_reload_apic_access_page(vcpu); | |
a2bcba50 | 10472 | } |
a7c0b07d WL |
10473 | |
10474 | if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) { | |
5e2f30b7 | 10475 | if (vmx->nested.virtual_apic_page) { /* shouldn't happen */ |
53a70daf | 10476 | kvm_release_page_dirty(vmx->nested.virtual_apic_page); |
5e2f30b7 DH |
10477 | vmx->nested.virtual_apic_page = NULL; |
10478 | } | |
10479 | page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->virtual_apic_page_addr); | |
a7c0b07d WL |
10480 | |
10481 | /* | |
6beb7bd5 JM |
10482 | * If translation failed, VM entry will fail because |
10483 | * prepare_vmcs02 set VIRTUAL_APIC_PAGE_ADDR to -1ull. | |
10484 | * Failing the vm entry is _not_ what the processor | |
10485 | * does but it's basically the only possibility we | |
10486 | * have. We could still enter the guest if CR8 load | |
10487 | * exits are enabled, CR8 store exits are enabled, and | |
10488 | * virtualize APIC access is disabled; in this case | |
10489 | * the processor would never use the TPR shadow and we | |
10490 | * could simply clear the bit from the execution | |
10491 | * control. But such a configuration is useless, so | |
10492 | * let's keep the code simple. | |
a7c0b07d | 10493 | */ |
5e2f30b7 DH |
10494 | if (!is_error_page(page)) { |
10495 | vmx->nested.virtual_apic_page = page; | |
6beb7bd5 JM |
10496 | hpa = page_to_phys(vmx->nested.virtual_apic_page); |
10497 | vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, hpa); | |
10498 | } | |
a7c0b07d WL |
10499 | } |
10500 | ||
705699a1 | 10501 | if (nested_cpu_has_posted_intr(vmcs12)) { |
705699a1 WV |
10502 | if (vmx->nested.pi_desc_page) { /* shouldn't happen */ |
10503 | kunmap(vmx->nested.pi_desc_page); | |
53a70daf | 10504 | kvm_release_page_dirty(vmx->nested.pi_desc_page); |
5e2f30b7 | 10505 | vmx->nested.pi_desc_page = NULL; |
3cf01066 CC |
10506 | vmx->nested.pi_desc = NULL; |
10507 | vmcs_write64(POSTED_INTR_DESC_ADDR, -1ull); | |
705699a1 | 10508 | } |
5e2f30b7 DH |
10509 | page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->posted_intr_desc_addr); |
10510 | if (is_error_page(page)) | |
6beb7bd5 | 10511 | return; |
5e2f30b7 DH |
10512 | vmx->nested.pi_desc_page = page; |
10513 | vmx->nested.pi_desc = kmap(vmx->nested.pi_desc_page); | |
705699a1 WV |
10514 | vmx->nested.pi_desc = |
10515 | (struct pi_desc *)((void *)vmx->nested.pi_desc + | |
10516 | (unsigned long)(vmcs12->posted_intr_desc_addr & | |
10517 | (PAGE_SIZE - 1))); | |
6beb7bd5 JM |
10518 | vmcs_write64(POSTED_INTR_DESC_ADDR, |
10519 | page_to_phys(vmx->nested.pi_desc_page) + | |
10520 | (unsigned long)(vmcs12->posted_intr_desc_addr & | |
10521 | (PAGE_SIZE - 1))); | |
705699a1 | 10522 | } |
6beb7bd5 JM |
10523 | if (cpu_has_vmx_msr_bitmap() && |
10524 | nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS) && | |
10525 | nested_vmx_merge_msr_bitmap(vcpu, vmcs12)) | |
cf40088f KA |
10526 | vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL, |
10527 | CPU_BASED_USE_MSR_BITMAPS); | |
6beb7bd5 JM |
10528 | else |
10529 | vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL, | |
10530 | CPU_BASED_USE_MSR_BITMAPS); | |
a2bcba50 WL |
10531 | } |
10532 | ||
f4124500 JK |
10533 | static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu) |
10534 | { | |
10535 | u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value; | |
10536 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
10537 | ||
10538 | if (vcpu->arch.virtual_tsc_khz == 0) | |
10539 | return; | |
10540 | ||
10541 | /* Make sure short timeouts reliably trigger an immediate vmexit. | |
10542 | * hrtimer_start does not guarantee this. */ | |
10543 | if (preemption_timeout <= 1) { | |
10544 | vmx_preemption_timer_fn(&vmx->nested.preemption_timer); | |
10545 | return; | |
10546 | } | |
10547 | ||
10548 | preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE; | |
10549 | preemption_timeout *= 1000000; | |
10550 | do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz); | |
10551 | hrtimer_start(&vmx->nested.preemption_timer, | |
10552 | ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL); | |
10553 | } | |
10554 | ||
56a20510 JM |
10555 | static int nested_vmx_check_io_bitmap_controls(struct kvm_vcpu *vcpu, |
10556 | struct vmcs12 *vmcs12) | |
10557 | { | |
10558 | if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS)) | |
10559 | return 0; | |
10560 | ||
10561 | if (!page_address_valid(vcpu, vmcs12->io_bitmap_a) || | |
10562 | !page_address_valid(vcpu, vmcs12->io_bitmap_b)) | |
10563 | return -EINVAL; | |
10564 | ||
10565 | return 0; | |
10566 | } | |
10567 | ||
3af18d9c WV |
10568 | static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu, |
10569 | struct vmcs12 *vmcs12) | |
10570 | { | |
3af18d9c WV |
10571 | if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS)) |
10572 | return 0; | |
10573 | ||
5fa99cbe | 10574 | if (!page_address_valid(vcpu, vmcs12->msr_bitmap)) |
3af18d9c WV |
10575 | return -EINVAL; |
10576 | ||
10577 | return 0; | |
10578 | } | |
10579 | ||
712b12d7 JM |
10580 | static int nested_vmx_check_tpr_shadow_controls(struct kvm_vcpu *vcpu, |
10581 | struct vmcs12 *vmcs12) | |
10582 | { | |
10583 | if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) | |
10584 | return 0; | |
10585 | ||
10586 | if (!page_address_valid(vcpu, vmcs12->virtual_apic_page_addr)) | |
10587 | return -EINVAL; | |
10588 | ||
10589 | return 0; | |
10590 | } | |
10591 | ||
3af18d9c WV |
10592 | /* |
10593 | * Merge L0's and L1's MSR bitmap, return false to indicate that | |
10594 | * we do not use the hardware. | |
10595 | */ | |
10596 | static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu, | |
10597 | struct vmcs12 *vmcs12) | |
10598 | { | |
82f0dd4b | 10599 | int msr; |
f2b93280 | 10600 | struct page *page; |
d048c098 | 10601 | unsigned long *msr_bitmap_l1; |
4b0be90f | 10602 | unsigned long *msr_bitmap_l0 = to_vmx(vcpu)->nested.vmcs02.msr_bitmap; |
33241bfe | 10603 | /* |
74469996 | 10604 | * pred_cmd & spec_ctrl are trying to verify two things: |
33241bfe AR |
10605 | * |
10606 | * 1. L0 gave a permission to L1 to actually passthrough the MSR. This | |
10607 | * ensures that we do not accidentally generate an L02 MSR bitmap | |
10608 | * from the L12 MSR bitmap that is too permissive. | |
10609 | * 2. That L1 or L2s have actually used the MSR. This avoids | |
10610 | * unnecessarily merging of the bitmap if the MSR is unused. This | |
10611 | * works properly because we only update the L01 MSR bitmap lazily. | |
10612 | * So even if L0 should pass L1 these MSRs, the L01 bitmap is only | |
10613 | * updated to reflect this when L1 (or its L2s) actually write to | |
10614 | * the MSR. | |
10615 | */ | |
cb9138cc KA |
10616 | bool pred_cmd = !msr_write_intercepted_l01(vcpu, MSR_IA32_PRED_CMD); |
10617 | bool spec_ctrl = !msr_write_intercepted_l01(vcpu, MSR_IA32_SPEC_CTRL); | |
f2b93280 | 10618 | |
33241bfe | 10619 | if (!nested_cpu_has_virt_x2apic_mode(vmcs12) && |
74469996 | 10620 | !pred_cmd && !spec_ctrl) |
f2b93280 WV |
10621 | return false; |
10622 | ||
5e2f30b7 DH |
10623 | page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->msr_bitmap); |
10624 | if (is_error_page(page)) | |
f2b93280 | 10625 | return false; |
d048c098 | 10626 | msr_bitmap_l1 = (unsigned long *)kmap(page); |
f2b93280 | 10627 | |
d048c098 RK |
10628 | memset(msr_bitmap_l0, 0xff, PAGE_SIZE); |
10629 | ||
f2b93280 | 10630 | if (nested_cpu_has_virt_x2apic_mode(vmcs12)) { |
82f0dd4b WV |
10631 | if (nested_cpu_has_apic_reg_virt(vmcs12)) |
10632 | for (msr = 0x800; msr <= 0x8ff; msr++) | |
10633 | nested_vmx_disable_intercept_for_msr( | |
d048c098 | 10634 | msr_bitmap_l1, msr_bitmap_l0, |
82f0dd4b | 10635 | msr, MSR_TYPE_R); |
d048c098 RK |
10636 | |
10637 | nested_vmx_disable_intercept_for_msr( | |
10638 | msr_bitmap_l1, msr_bitmap_l0, | |
f2b93280 WV |
10639 | APIC_BASE_MSR + (APIC_TASKPRI >> 4), |
10640 | MSR_TYPE_R | MSR_TYPE_W); | |
d048c098 | 10641 | |
608406e2 | 10642 | if (nested_cpu_has_vid(vmcs12)) { |
608406e2 | 10643 | nested_vmx_disable_intercept_for_msr( |
d048c098 | 10644 | msr_bitmap_l1, msr_bitmap_l0, |
608406e2 WV |
10645 | APIC_BASE_MSR + (APIC_EOI >> 4), |
10646 | MSR_TYPE_W); | |
10647 | nested_vmx_disable_intercept_for_msr( | |
d048c098 | 10648 | msr_bitmap_l1, msr_bitmap_l0, |
608406e2 WV |
10649 | APIC_BASE_MSR + (APIC_SELF_IPI >> 4), |
10650 | MSR_TYPE_W); | |
10651 | } | |
82f0dd4b | 10652 | } |
33241bfe | 10653 | |
74469996 KA |
10654 | if (spec_ctrl) |
10655 | nested_vmx_disable_intercept_for_msr( | |
10656 | msr_bitmap_l1, msr_bitmap_l0, | |
10657 | MSR_IA32_SPEC_CTRL, | |
10658 | MSR_TYPE_R | MSR_TYPE_W); | |
10659 | ||
33241bfe AR |
10660 | if (pred_cmd) |
10661 | nested_vmx_disable_intercept_for_msr( | |
10662 | msr_bitmap_l1, msr_bitmap_l0, | |
10663 | MSR_IA32_PRED_CMD, | |
10664 | MSR_TYPE_W); | |
10665 | ||
f2b93280 | 10666 | kunmap(page); |
53a70daf | 10667 | kvm_release_page_clean(page); |
f2b93280 WV |
10668 | |
10669 | return true; | |
10670 | } | |
10671 | ||
76a19ac5 KS |
10672 | static int nested_vmx_check_apic_access_controls(struct kvm_vcpu *vcpu, |
10673 | struct vmcs12 *vmcs12) | |
10674 | { | |
10675 | if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) && | |
10676 | !page_address_valid(vcpu, vmcs12->apic_access_addr)) | |
10677 | return -EINVAL; | |
10678 | else | |
10679 | return 0; | |
10680 | } | |
10681 | ||
f2b93280 WV |
10682 | static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu, |
10683 | struct vmcs12 *vmcs12) | |
10684 | { | |
82f0dd4b | 10685 | if (!nested_cpu_has_virt_x2apic_mode(vmcs12) && |
608406e2 | 10686 | !nested_cpu_has_apic_reg_virt(vmcs12) && |
705699a1 WV |
10687 | !nested_cpu_has_vid(vmcs12) && |
10688 | !nested_cpu_has_posted_intr(vmcs12)) | |
f2b93280 WV |
10689 | return 0; |
10690 | ||
10691 | /* | |
10692 | * If virtualize x2apic mode is enabled, | |
10693 | * virtualize apic access must be disabled. | |
10694 | */ | |
82f0dd4b WV |
10695 | if (nested_cpu_has_virt_x2apic_mode(vmcs12) && |
10696 | nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) | |
f2b93280 WV |
10697 | return -EINVAL; |
10698 | ||
608406e2 WV |
10699 | /* |
10700 | * If virtual interrupt delivery is enabled, | |
10701 | * we must exit on external interrupts. | |
10702 | */ | |
10703 | if (nested_cpu_has_vid(vmcs12) && | |
10704 | !nested_exit_on_intr(vcpu)) | |
10705 | return -EINVAL; | |
10706 | ||
705699a1 WV |
10707 | /* |
10708 | * bits 15:8 should be zero in posted_intr_nv, | |
10709 | * the descriptor address has been already checked | |
10710 | * in nested_get_vmcs12_pages. | |
10711 | */ | |
10712 | if (nested_cpu_has_posted_intr(vmcs12) && | |
10713 | (!nested_cpu_has_vid(vmcs12) || | |
10714 | !nested_exit_intr_ack_set(vcpu) || | |
10715 | vmcs12->posted_intr_nv & 0xff00)) | |
10716 | return -EINVAL; | |
10717 | ||
f2b93280 WV |
10718 | /* tpr shadow is needed by all apicv features. */ |
10719 | if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) | |
10720 | return -EINVAL; | |
10721 | ||
10722 | return 0; | |
3af18d9c WV |
10723 | } |
10724 | ||
e9ac033e EK |
10725 | static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu, |
10726 | unsigned long count_field, | |
92d71bc6 | 10727 | unsigned long addr_field) |
ff651cb6 | 10728 | { |
92d71bc6 | 10729 | int maxphyaddr; |
e9ac033e EK |
10730 | u64 count, addr; |
10731 | ||
10732 | if (vmcs12_read_any(vcpu, count_field, &count) || | |
10733 | vmcs12_read_any(vcpu, addr_field, &addr)) { | |
10734 | WARN_ON(1); | |
10735 | return -EINVAL; | |
10736 | } | |
10737 | if (count == 0) | |
10738 | return 0; | |
92d71bc6 | 10739 | maxphyaddr = cpuid_maxphyaddr(vcpu); |
e9ac033e EK |
10740 | if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr || |
10741 | (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) { | |
bbe41b95 | 10742 | pr_debug_ratelimited( |
e9ac033e EK |
10743 | "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)", |
10744 | addr_field, maxphyaddr, count, addr); | |
10745 | return -EINVAL; | |
10746 | } | |
10747 | return 0; | |
10748 | } | |
10749 | ||
10750 | static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu, | |
10751 | struct vmcs12 *vmcs12) | |
10752 | { | |
e9ac033e EK |
10753 | if (vmcs12->vm_exit_msr_load_count == 0 && |
10754 | vmcs12->vm_exit_msr_store_count == 0 && | |
10755 | vmcs12->vm_entry_msr_load_count == 0) | |
10756 | return 0; /* Fast path */ | |
e9ac033e | 10757 | if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT, |
92d71bc6 | 10758 | VM_EXIT_MSR_LOAD_ADDR) || |
e9ac033e | 10759 | nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT, |
92d71bc6 | 10760 | VM_EXIT_MSR_STORE_ADDR) || |
e9ac033e | 10761 | nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT, |
92d71bc6 | 10762 | VM_ENTRY_MSR_LOAD_ADDR)) |
e9ac033e EK |
10763 | return -EINVAL; |
10764 | return 0; | |
10765 | } | |
10766 | ||
c5f983f6 BD |
10767 | static int nested_vmx_check_pml_controls(struct kvm_vcpu *vcpu, |
10768 | struct vmcs12 *vmcs12) | |
10769 | { | |
10770 | u64 address = vmcs12->pml_address; | |
10771 | int maxphyaddr = cpuid_maxphyaddr(vcpu); | |
10772 | ||
10773 | if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_PML)) { | |
10774 | if (!nested_cpu_has_ept(vmcs12) || | |
10775 | !IS_ALIGNED(address, 4096) || | |
10776 | address >> maxphyaddr) | |
10777 | return -EINVAL; | |
10778 | } | |
10779 | ||
10780 | return 0; | |
10781 | } | |
10782 | ||
e9ac033e EK |
10783 | static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu, |
10784 | struct vmx_msr_entry *e) | |
10785 | { | |
10786 | /* x2APIC MSR accesses are not allowed */ | |
8a9781f7 | 10787 | if (vcpu->arch.apic_base & X2APIC_ENABLE && e->index >> 8 == 0x8) |
e9ac033e EK |
10788 | return -EINVAL; |
10789 | if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */ | |
10790 | e->index == MSR_IA32_UCODE_REV) | |
10791 | return -EINVAL; | |
10792 | if (e->reserved != 0) | |
ff651cb6 WV |
10793 | return -EINVAL; |
10794 | return 0; | |
10795 | } | |
10796 | ||
e9ac033e EK |
10797 | static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu, |
10798 | struct vmx_msr_entry *e) | |
ff651cb6 WV |
10799 | { |
10800 | if (e->index == MSR_FS_BASE || | |
10801 | e->index == MSR_GS_BASE || | |
e9ac033e EK |
10802 | e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */ |
10803 | nested_vmx_msr_check_common(vcpu, e)) | |
10804 | return -EINVAL; | |
10805 | return 0; | |
10806 | } | |
10807 | ||
10808 | static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu, | |
10809 | struct vmx_msr_entry *e) | |
10810 | { | |
10811 | if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */ | |
10812 | nested_vmx_msr_check_common(vcpu, e)) | |
ff651cb6 WV |
10813 | return -EINVAL; |
10814 | return 0; | |
10815 | } | |
10816 | ||
10817 | /* | |
10818 | * Load guest's/host's msr at nested entry/exit. | |
10819 | * return 0 for success, entry index for failure. | |
10820 | */ | |
10821 | static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count) | |
10822 | { | |
10823 | u32 i; | |
10824 | struct vmx_msr_entry e; | |
10825 | struct msr_data msr; | |
10826 | ||
10827 | msr.host_initiated = false; | |
10828 | for (i = 0; i < count; i++) { | |
54bf36aa PB |
10829 | if (kvm_vcpu_read_guest(vcpu, gpa + i * sizeof(e), |
10830 | &e, sizeof(e))) { | |
bbe41b95 | 10831 | pr_debug_ratelimited( |
e9ac033e EK |
10832 | "%s cannot read MSR entry (%u, 0x%08llx)\n", |
10833 | __func__, i, gpa + i * sizeof(e)); | |
ff651cb6 | 10834 | goto fail; |
e9ac033e EK |
10835 | } |
10836 | if (nested_vmx_load_msr_check(vcpu, &e)) { | |
bbe41b95 | 10837 | pr_debug_ratelimited( |
e9ac033e EK |
10838 | "%s check failed (%u, 0x%x, 0x%x)\n", |
10839 | __func__, i, e.index, e.reserved); | |
10840 | goto fail; | |
10841 | } | |
ff651cb6 WV |
10842 | msr.index = e.index; |
10843 | msr.data = e.value; | |
e9ac033e | 10844 | if (kvm_set_msr(vcpu, &msr)) { |
bbe41b95 | 10845 | pr_debug_ratelimited( |
e9ac033e EK |
10846 | "%s cannot write MSR (%u, 0x%x, 0x%llx)\n", |
10847 | __func__, i, e.index, e.value); | |
ff651cb6 | 10848 | goto fail; |
e9ac033e | 10849 | } |
ff651cb6 WV |
10850 | } |
10851 | return 0; | |
10852 | fail: | |
10853 | return i + 1; | |
10854 | } | |
10855 | ||
10856 | static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count) | |
10857 | { | |
10858 | u32 i; | |
10859 | struct vmx_msr_entry e; | |
10860 | ||
10861 | for (i = 0; i < count; i++) { | |
609e36d3 | 10862 | struct msr_data msr_info; |
54bf36aa PB |
10863 | if (kvm_vcpu_read_guest(vcpu, |
10864 | gpa + i * sizeof(e), | |
10865 | &e, 2 * sizeof(u32))) { | |
bbe41b95 | 10866 | pr_debug_ratelimited( |
e9ac033e EK |
10867 | "%s cannot read MSR entry (%u, 0x%08llx)\n", |
10868 | __func__, i, gpa + i * sizeof(e)); | |
ff651cb6 | 10869 | return -EINVAL; |
e9ac033e EK |
10870 | } |
10871 | if (nested_vmx_store_msr_check(vcpu, &e)) { | |
bbe41b95 | 10872 | pr_debug_ratelimited( |
e9ac033e EK |
10873 | "%s check failed (%u, 0x%x, 0x%x)\n", |
10874 | __func__, i, e.index, e.reserved); | |
ff651cb6 | 10875 | return -EINVAL; |
e9ac033e | 10876 | } |
609e36d3 PB |
10877 | msr_info.host_initiated = false; |
10878 | msr_info.index = e.index; | |
10879 | if (kvm_get_msr(vcpu, &msr_info)) { | |
bbe41b95 | 10880 | pr_debug_ratelimited( |
e9ac033e EK |
10881 | "%s cannot read MSR (%u, 0x%x)\n", |
10882 | __func__, i, e.index); | |
10883 | return -EINVAL; | |
10884 | } | |
54bf36aa PB |
10885 | if (kvm_vcpu_write_guest(vcpu, |
10886 | gpa + i * sizeof(e) + | |
10887 | offsetof(struct vmx_msr_entry, value), | |
10888 | &msr_info.data, sizeof(msr_info.data))) { | |
bbe41b95 | 10889 | pr_debug_ratelimited( |
e9ac033e | 10890 | "%s cannot write MSR (%u, 0x%x, 0x%llx)\n", |
609e36d3 | 10891 | __func__, i, e.index, msr_info.data); |
e9ac033e EK |
10892 | return -EINVAL; |
10893 | } | |
ff651cb6 WV |
10894 | } |
10895 | return 0; | |
10896 | } | |
10897 | ||
1dc35dac LP |
10898 | static bool nested_cr3_valid(struct kvm_vcpu *vcpu, unsigned long val) |
10899 | { | |
10900 | unsigned long invalid_mask; | |
10901 | ||
10902 | invalid_mask = (~0ULL) << cpuid_maxphyaddr(vcpu); | |
10903 | return (val & invalid_mask) == 0; | |
10904 | } | |
10905 | ||
9ed38ffa LP |
10906 | /* |
10907 | * Load guest's/host's cr3 at nested entry/exit. nested_ept is true if we are | |
10908 | * emulating VM entry into a guest with EPT enabled. | |
10909 | * Returns 0 on success, 1 on failure. Invalid state exit qualification code | |
10910 | * is assigned to entry_failure_code on failure. | |
10911 | */ | |
10912 | static int nested_vmx_load_cr3(struct kvm_vcpu *vcpu, unsigned long cr3, bool nested_ept, | |
ca0bde28 | 10913 | u32 *entry_failure_code) |
9ed38ffa | 10914 | { |
9ed38ffa | 10915 | if (cr3 != kvm_read_cr3(vcpu) || (!nested_ept && pdptrs_changed(vcpu))) { |
1dc35dac | 10916 | if (!nested_cr3_valid(vcpu, cr3)) { |
9ed38ffa LP |
10917 | *entry_failure_code = ENTRY_FAIL_DEFAULT; |
10918 | return 1; | |
10919 | } | |
10920 | ||
10921 | /* | |
10922 | * If PAE paging and EPT are both on, CR3 is not used by the CPU and | |
10923 | * must not be dereferenced. | |
10924 | */ | |
f68adeae | 10925 | if (is_pae_paging(vcpu) && !nested_ept) { |
9ed38ffa LP |
10926 | if (!load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) { |
10927 | *entry_failure_code = ENTRY_FAIL_PDPTE; | |
10928 | return 1; | |
10929 | } | |
10930 | } | |
10931 | ||
10932 | vcpu->arch.cr3 = cr3; | |
10933 | __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail); | |
10934 | } | |
10935 | ||
10936 | kvm_mmu_reset_context(vcpu); | |
10937 | return 0; | |
10938 | } | |
10939 | ||
fe3ef05c NHE |
10940 | /* |
10941 | * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested | |
10942 | * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it | |
b4619660 | 10943 | * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2 |
fe3ef05c NHE |
10944 | * guest in a way that will both be appropriate to L1's requests, and our |
10945 | * needs. In addition to modifying the active vmcs (which is vmcs02), this | |
10946 | * function also has additional necessary side-effects, like setting various | |
10947 | * vcpu->arch fields. | |
ee146c1c LP |
10948 | * Returns 0 on success, 1 on failure. Invalid state exit qualification code |
10949 | * is assigned to entry_failure_code on failure. | |
fe3ef05c | 10950 | */ |
ee146c1c | 10951 | static int prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12, |
ca0bde28 | 10952 | bool from_vmentry, u32 *entry_failure_code) |
fe3ef05c NHE |
10953 | { |
10954 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
03efce6f | 10955 | u32 exec_control, vmcs12_exec_ctrl; |
fe3ef05c NHE |
10956 | |
10957 | vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector); | |
10958 | vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector); | |
10959 | vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector); | |
10960 | vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector); | |
10961 | vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector); | |
10962 | vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector); | |
10963 | vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector); | |
10964 | vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector); | |
10965 | vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit); | |
10966 | vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit); | |
10967 | vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit); | |
10968 | vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit); | |
10969 | vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit); | |
10970 | vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit); | |
10971 | vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit); | |
10972 | vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit); | |
10973 | vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit); | |
10974 | vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit); | |
10975 | vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes); | |
10976 | vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes); | |
10977 | vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes); | |
10978 | vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes); | |
10979 | vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes); | |
10980 | vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes); | |
10981 | vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes); | |
10982 | vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes); | |
10983 | vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base); | |
10984 | vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base); | |
10985 | vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base); | |
10986 | vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base); | |
10987 | vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base); | |
10988 | vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base); | |
10989 | vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base); | |
10990 | vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base); | |
10991 | vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base); | |
10992 | vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base); | |
10993 | ||
cf8b84f4 JM |
10994 | if (from_vmentry && |
10995 | (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS)) { | |
2996fca0 JK |
10996 | kvm_set_dr(vcpu, 7, vmcs12->guest_dr7); |
10997 | vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl); | |
10998 | } else { | |
10999 | kvm_set_dr(vcpu, 7, vcpu->arch.dr7); | |
11000 | vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl); | |
11001 | } | |
cf8b84f4 JM |
11002 | if (from_vmentry) { |
11003 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, | |
11004 | vmcs12->vm_entry_intr_info_field); | |
11005 | vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, | |
11006 | vmcs12->vm_entry_exception_error_code); | |
11007 | vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, | |
11008 | vmcs12->vm_entry_instruction_len); | |
11009 | vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, | |
11010 | vmcs12->guest_interruptibility_info); | |
2d6144e3 WL |
11011 | vmx->loaded_vmcs->nmi_known_unmasked = |
11012 | !(vmcs12->guest_interruptibility_info & GUEST_INTR_STATE_NMI); | |
cf8b84f4 JM |
11013 | } else { |
11014 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); | |
11015 | } | |
fe3ef05c | 11016 | vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs); |
63fbf59f | 11017 | vmx_set_rflags(vcpu, vmcs12->guest_rflags); |
fe3ef05c NHE |
11018 | vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, |
11019 | vmcs12->guest_pending_dbg_exceptions); | |
11020 | vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp); | |
11021 | vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip); | |
11022 | ||
81dc01f7 WL |
11023 | if (nested_cpu_has_xsaves(vmcs12)) |
11024 | vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap); | |
fe3ef05c NHE |
11025 | vmcs_write64(VMCS_LINK_POINTER, -1ull); |
11026 | ||
f4124500 | 11027 | exec_control = vmcs12->pin_based_vm_exec_control; |
9314006d PB |
11028 | |
11029 | /* Preemption timer setting is only taken from vmcs01. */ | |
705699a1 | 11030 | exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER; |
9314006d PB |
11031 | exec_control |= vmcs_config.pin_based_exec_ctrl; |
11032 | if (vmx->hv_deadline_tsc == -1) | |
11033 | exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER; | |
705699a1 | 11034 | |
9314006d | 11035 | /* Posted interrupts setting is only taken from vmcs12. */ |
705699a1 | 11036 | if (nested_cpu_has_posted_intr(vmcs12)) { |
705699a1 WV |
11037 | vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv; |
11038 | vmx->nested.pi_pending = false; | |
06a5524f | 11039 | vmcs_write16(POSTED_INTR_NV, POSTED_INTR_NESTED_VECTOR); |
6beb7bd5 | 11040 | } else { |
705699a1 | 11041 | exec_control &= ~PIN_BASED_POSTED_INTR; |
6beb7bd5 | 11042 | } |
705699a1 | 11043 | |
f4124500 | 11044 | vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control); |
fe3ef05c | 11045 | |
f4124500 JK |
11046 | vmx->nested.preemption_timer_expired = false; |
11047 | if (nested_cpu_has_preemption_timer(vmcs12)) | |
11048 | vmx_start_preemption_timer(vcpu); | |
0238ea91 | 11049 | |
fe3ef05c NHE |
11050 | /* |
11051 | * Whether page-faults are trapped is determined by a combination of | |
11052 | * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF. | |
11053 | * If enable_ept, L0 doesn't care about page faults and we should | |
11054 | * set all of these to L1's desires. However, if !enable_ept, L0 does | |
11055 | * care about (at least some) page faults, and because it is not easy | |
11056 | * (if at all possible?) to merge L0 and L1's desires, we simply ask | |
11057 | * to exit on each and every L2 page fault. This is done by setting | |
11058 | * MASK=MATCH=0 and (see below) EB.PF=1. | |
11059 | * Note that below we don't need special code to set EB.PF beyond the | |
11060 | * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept, | |
11061 | * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when | |
11062 | * !enable_ept, EB.PF is 1, so the "or" will always be 1. | |
fe3ef05c NHE |
11063 | */ |
11064 | vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, | |
11065 | enable_ept ? vmcs12->page_fault_error_code_mask : 0); | |
11066 | vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, | |
11067 | enable_ept ? vmcs12->page_fault_error_code_match : 0); | |
11068 | ||
11069 | if (cpu_has_secondary_exec_ctrls()) { | |
80154d77 | 11070 | exec_control = vmx->secondary_exec_control; |
e2821620 | 11071 | |
fe3ef05c | 11072 | /* Take the following fields only from vmcs12 */ |
696dfd95 | 11073 | exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | |
90a2db6d | 11074 | SECONDARY_EXEC_ENABLE_INVPCID | |
b3a2a907 | 11075 | SECONDARY_EXEC_RDTSCP | |
3db13480 | 11076 | SECONDARY_EXEC_XSAVES | |
696dfd95 | 11077 | SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | |
27c42a1b BD |
11078 | SECONDARY_EXEC_APIC_REGISTER_VIRT | |
11079 | SECONDARY_EXEC_ENABLE_VMFUNC); | |
fe3ef05c | 11080 | if (nested_cpu_has(vmcs12, |
03efce6f BD |
11081 | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS)) { |
11082 | vmcs12_exec_ctrl = vmcs12->secondary_vm_exec_control & | |
11083 | ~SECONDARY_EXEC_ENABLE_PML; | |
11084 | exec_control |= vmcs12_exec_ctrl; | |
11085 | } | |
fe3ef05c | 11086 | |
27c42a1b BD |
11087 | /* All VMFUNCs are currently emulated through L0 vmexits. */ |
11088 | if (exec_control & SECONDARY_EXEC_ENABLE_VMFUNC) | |
11089 | vmcs_write64(VM_FUNCTION_CONTROL, 0); | |
11090 | ||
608406e2 WV |
11091 | if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) { |
11092 | vmcs_write64(EOI_EXIT_BITMAP0, | |
11093 | vmcs12->eoi_exit_bitmap0); | |
11094 | vmcs_write64(EOI_EXIT_BITMAP1, | |
11095 | vmcs12->eoi_exit_bitmap1); | |
11096 | vmcs_write64(EOI_EXIT_BITMAP2, | |
11097 | vmcs12->eoi_exit_bitmap2); | |
11098 | vmcs_write64(EOI_EXIT_BITMAP3, | |
11099 | vmcs12->eoi_exit_bitmap3); | |
11100 | vmcs_write16(GUEST_INTR_STATUS, | |
11101 | vmcs12->guest_intr_status); | |
11102 | } | |
11103 | ||
6beb7bd5 JM |
11104 | /* |
11105 | * Write an illegal value to APIC_ACCESS_ADDR. Later, | |
11106 | * nested_get_vmcs12_pages will either fix it up or | |
11107 | * remove the VM execution control. | |
11108 | */ | |
11109 | if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) | |
11110 | vmcs_write64(APIC_ACCESS_ADDR, -1ull); | |
11111 | ||
fe3ef05c NHE |
11112 | vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control); |
11113 | } | |
11114 | ||
11115 | ||
11116 | /* | |
11117 | * Set host-state according to L0's settings (vmcs12 is irrelevant here) | |
11118 | * Some constant fields are set here by vmx_set_constant_host_state(). | |
11119 | * Other fields are different per CPU, and will be set later when | |
11120 | * vmx_vcpu_load() is called, and when vmx_save_host_state() is called. | |
11121 | */ | |
a547c6db | 11122 | vmx_set_constant_host_state(vmx); |
fe3ef05c | 11123 | |
83bafef1 JM |
11124 | /* |
11125 | * Set the MSR load/store lists to match L0's settings. | |
11126 | */ | |
11127 | vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0); | |
6e3dedb6 KRW |
11128 | vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.host.nr); |
11129 | vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host.val)); | |
11130 | vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.guest.nr); | |
11131 | vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest.val)); | |
83bafef1 | 11132 | |
fe3ef05c NHE |
11133 | /* |
11134 | * HOST_RSP is normally set correctly in vmx_vcpu_run() just before | |
11135 | * entry, but only if the current (host) sp changed from the value | |
11136 | * we wrote last (vmx->host_rsp). This cache is no longer relevant | |
11137 | * if we switch vmcs, and rather than hold a separate cache per vmcs, | |
11138 | * here we just force the write to happen on entry. | |
11139 | */ | |
11140 | vmx->host_rsp = 0; | |
11141 | ||
11142 | exec_control = vmx_exec_control(vmx); /* L0's desires */ | |
11143 | exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING; | |
11144 | exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING; | |
11145 | exec_control &= ~CPU_BASED_TPR_SHADOW; | |
11146 | exec_control |= vmcs12->cpu_based_vm_exec_control; | |
a7c0b07d | 11147 | |
6beb7bd5 JM |
11148 | /* |
11149 | * Write an illegal value to VIRTUAL_APIC_PAGE_ADDR. Later, if | |
11150 | * nested_get_vmcs12_pages can't fix it up, the illegal value | |
11151 | * will result in a VM entry failure. | |
11152 | */ | |
a7c0b07d | 11153 | if (exec_control & CPU_BASED_TPR_SHADOW) { |
6beb7bd5 | 11154 | vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, -1ull); |
a7c0b07d | 11155 | vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold); |
51aa68e7 JM |
11156 | } else { |
11157 | #ifdef CONFIG_X86_64 | |
11158 | exec_control |= CPU_BASED_CR8_LOAD_EXITING | | |
11159 | CPU_BASED_CR8_STORE_EXITING; | |
11160 | #endif | |
a7c0b07d WL |
11161 | } |
11162 | ||
fe3ef05c | 11163 | /* |
3af18d9c | 11164 | * Merging of IO bitmap not currently supported. |
fe3ef05c NHE |
11165 | * Rather, exit every time. |
11166 | */ | |
fe3ef05c NHE |
11167 | exec_control &= ~CPU_BASED_USE_IO_BITMAPS; |
11168 | exec_control |= CPU_BASED_UNCOND_IO_EXITING; | |
11169 | ||
11170 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control); | |
11171 | ||
11172 | /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the | |
11173 | * bitwise-or of what L1 wants to trap for L2, and what we want to | |
11174 | * trap. Note that CR0.TS also needs updating - we do this later. | |
11175 | */ | |
11176 | update_exception_bitmap(vcpu); | |
11177 | vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask; | |
11178 | vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits); | |
11179 | ||
8049d651 NHE |
11180 | /* L2->L1 exit controls are emulated - the hardware exit is to L0 so |
11181 | * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER | |
11182 | * bits are further modified by vmx_set_efer() below. | |
11183 | */ | |
f4124500 | 11184 | vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl); |
8049d651 NHE |
11185 | |
11186 | /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are | |
11187 | * emulated by vmx_set_efer(), below. | |
11188 | */ | |
2961e876 | 11189 | vm_entry_controls_init(vmx, |
8049d651 NHE |
11190 | (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER & |
11191 | ~VM_ENTRY_IA32E_MODE) | | |
fe3ef05c NHE |
11192 | (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE)); |
11193 | ||
cf8b84f4 JM |
11194 | if (from_vmentry && |
11195 | (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)) { | |
fe3ef05c | 11196 | vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat); |
44811c02 | 11197 | vcpu->arch.pat = vmcs12->guest_ia32_pat; |
cf8b84f4 | 11198 | } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) { |
fe3ef05c | 11199 | vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat); |
cf8b84f4 | 11200 | } |
fe3ef05c NHE |
11201 | |
11202 | set_cr4_guest_host_mask(vmx); | |
11203 | ||
cf8b84f4 JM |
11204 | if (from_vmentry && |
11205 | vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS) | |
36be0b9d PB |
11206 | vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs); |
11207 | ||
f7f5542f KA |
11208 | vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset); |
11209 | ||
c95ba92a PF |
11210 | if (kvm_has_tsc_control) |
11211 | decache_tsc_multiplier(vmx); | |
fe3ef05c | 11212 | |
4b0be90f PB |
11213 | if (cpu_has_vmx_msr_bitmap()) |
11214 | vmcs_write64(MSR_BITMAP, __pa(vmx->nested.vmcs02.msr_bitmap)); | |
11215 | ||
fe3ef05c NHE |
11216 | if (enable_vpid) { |
11217 | /* | |
5c614b35 WL |
11218 | * There is no direct mapping between vpid02 and vpid12, the |
11219 | * vpid02 is per-vCPU for L0 and reused while the value of | |
11220 | * vpid12 is changed w/ one invvpid during nested vmentry. | |
11221 | * The vpid12 is allocated by L1 for L2, so it will not | |
11222 | * influence global bitmap(for vpid01 and vpid02 allocation) | |
11223 | * even if spawn a lot of nested vCPUs. | |
fe3ef05c | 11224 | */ |
5c614b35 WL |
11225 | if (nested_cpu_has_vpid(vmcs12) && vmx->nested.vpid02) { |
11226 | vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->nested.vpid02); | |
11227 | if (vmcs12->virtual_processor_id != vmx->nested.last_vpid) { | |
11228 | vmx->nested.last_vpid = vmcs12->virtual_processor_id; | |
6bf41e55 | 11229 | __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02, true); |
5c614b35 WL |
11230 | } |
11231 | } else { | |
11232 | vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid); | |
6bf41e55 | 11233 | vmx_flush_tlb(vcpu, true); |
5c614b35 WL |
11234 | } |
11235 | ||
fe3ef05c NHE |
11236 | } |
11237 | ||
1fb883bb LP |
11238 | if (enable_pml) { |
11239 | /* | |
11240 | * Conceptually we want to copy the PML address and index from | |
11241 | * vmcs01 here, and then back to vmcs01 on nested vmexit. But, | |
11242 | * since we always flush the log on each vmexit, this happens | |
11243 | * to be equivalent to simply resetting the fields in vmcs02. | |
11244 | */ | |
11245 | ASSERT(vmx->pml_pg); | |
11246 | vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg)); | |
11247 | vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1); | |
11248 | } | |
11249 | ||
155a97a3 | 11250 | if (nested_cpu_has_ept(vmcs12)) { |
ae1e2d10 PB |
11251 | if (nested_ept_init_mmu_context(vcpu)) { |
11252 | *entry_failure_code = ENTRY_FAIL_DEFAULT; | |
11253 | return 1; | |
11254 | } | |
fb6c8198 JM |
11255 | } else if (nested_cpu_has2(vmcs12, |
11256 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) { | |
6bf41e55 | 11257 | vmx_flush_tlb(vcpu, true); |
155a97a3 NHE |
11258 | } |
11259 | ||
fe3ef05c | 11260 | /* |
bd7e5b08 PB |
11261 | * This sets GUEST_CR0 to vmcs12->guest_cr0, possibly modifying those |
11262 | * bits which we consider mandatory enabled. | |
fe3ef05c NHE |
11263 | * The CR0_READ_SHADOW is what L2 should have expected to read given |
11264 | * the specifications by L1; It's not enough to take | |
11265 | * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we | |
11266 | * have more bits than L1 expected. | |
11267 | */ | |
11268 | vmx_set_cr0(vcpu, vmcs12->guest_cr0); | |
11269 | vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12)); | |
11270 | ||
11271 | vmx_set_cr4(vcpu, vmcs12->guest_cr4); | |
11272 | vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12)); | |
11273 | ||
cf8b84f4 JM |
11274 | if (from_vmentry && |
11275 | (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)) | |
5a6a9748 DM |
11276 | vcpu->arch.efer = vmcs12->guest_ia32_efer; |
11277 | else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) | |
11278 | vcpu->arch.efer |= (EFER_LMA | EFER_LME); | |
11279 | else | |
11280 | vcpu->arch.efer &= ~(EFER_LMA | EFER_LME); | |
11281 | /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */ | |
11282 | vmx_set_efer(vcpu, vcpu->arch.efer); | |
11283 | ||
9ed38ffa | 11284 | /* Shadow page tables on either EPT or shadow page tables. */ |
7ad658b6 | 11285 | if (nested_vmx_load_cr3(vcpu, vmcs12->guest_cr3, nested_cpu_has_ept(vmcs12), |
9ed38ffa LP |
11286 | entry_failure_code)) |
11287 | return 1; | |
7ca29de2 | 11288 | |
feaf0c7d GN |
11289 | if (!enable_ept) |
11290 | vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested; | |
11291 | ||
3633cfc3 NHE |
11292 | /* |
11293 | * L1 may access the L2's PDPTR, so save them to construct vmcs12 | |
11294 | */ | |
11295 | if (enable_ept) { | |
11296 | vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0); | |
11297 | vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1); | |
11298 | vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2); | |
11299 | vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3); | |
11300 | } | |
11301 | ||
fe3ef05c NHE |
11302 | kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp); |
11303 | kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip); | |
ee146c1c | 11304 | return 0; |
fe3ef05c NHE |
11305 | } |
11306 | ||
ca0bde28 | 11307 | static int check_vmentry_prereqs(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12) |
cd232ad0 | 11308 | { |
cd232ad0 | 11309 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
7c177938 | 11310 | |
6dfacadd | 11311 | if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE && |
ca0bde28 JM |
11312 | vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT) |
11313 | return VMXERR_ENTRY_INVALID_CONTROL_FIELD; | |
26539bd0 | 11314 | |
56a20510 JM |
11315 | if (nested_vmx_check_io_bitmap_controls(vcpu, vmcs12)) |
11316 | return VMXERR_ENTRY_INVALID_CONTROL_FIELD; | |
11317 | ||
ca0bde28 JM |
11318 | if (nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12)) |
11319 | return VMXERR_ENTRY_INVALID_CONTROL_FIELD; | |
7c177938 | 11320 | |
76a19ac5 KS |
11321 | if (nested_vmx_check_apic_access_controls(vcpu, vmcs12)) |
11322 | return VMXERR_ENTRY_INVALID_CONTROL_FIELD; | |
11323 | ||
712b12d7 JM |
11324 | if (nested_vmx_check_tpr_shadow_controls(vcpu, vmcs12)) |
11325 | return VMXERR_ENTRY_INVALID_CONTROL_FIELD; | |
11326 | ||
ca0bde28 JM |
11327 | if (nested_vmx_check_apicv_controls(vcpu, vmcs12)) |
11328 | return VMXERR_ENTRY_INVALID_CONTROL_FIELD; | |
f2b93280 | 11329 | |
ca0bde28 JM |
11330 | if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12)) |
11331 | return VMXERR_ENTRY_INVALID_CONTROL_FIELD; | |
e9ac033e | 11332 | |
c5f983f6 BD |
11333 | if (nested_vmx_check_pml_controls(vcpu, vmcs12)) |
11334 | return VMXERR_ENTRY_INVALID_CONTROL_FIELD; | |
11335 | ||
7c177938 | 11336 | if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control, |
0115f9cb | 11337 | vmx->nested.nested_vmx_procbased_ctls_low, |
b9c237bb | 11338 | vmx->nested.nested_vmx_procbased_ctls_high) || |
2e5b0bd9 JM |
11339 | (nested_cpu_has(vmcs12, CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) && |
11340 | !vmx_control_verify(vmcs12->secondary_vm_exec_control, | |
11341 | vmx->nested.nested_vmx_secondary_ctls_low, | |
11342 | vmx->nested.nested_vmx_secondary_ctls_high)) || | |
7c177938 | 11343 | !vmx_control_verify(vmcs12->pin_based_vm_exec_control, |
b9c237bb WV |
11344 | vmx->nested.nested_vmx_pinbased_ctls_low, |
11345 | vmx->nested.nested_vmx_pinbased_ctls_high) || | |
7c177938 | 11346 | !vmx_control_verify(vmcs12->vm_exit_controls, |
0115f9cb | 11347 | vmx->nested.nested_vmx_exit_ctls_low, |
b9c237bb | 11348 | vmx->nested.nested_vmx_exit_ctls_high) || |
7c177938 | 11349 | !vmx_control_verify(vmcs12->vm_entry_controls, |
0115f9cb | 11350 | vmx->nested.nested_vmx_entry_ctls_low, |
b9c237bb | 11351 | vmx->nested.nested_vmx_entry_ctls_high)) |
ca0bde28 | 11352 | return VMXERR_ENTRY_INVALID_CONTROL_FIELD; |
7c177938 | 11353 | |
41ab9372 BD |
11354 | if (nested_cpu_has_vmfunc(vmcs12)) { |
11355 | if (vmcs12->vm_function_control & | |
11356 | ~vmx->nested.nested_vmx_vmfunc_controls) | |
11357 | return VMXERR_ENTRY_INVALID_CONTROL_FIELD; | |
11358 | ||
11359 | if (nested_cpu_has_eptp_switching(vmcs12)) { | |
11360 | if (!nested_cpu_has_ept(vmcs12) || | |
11361 | !page_address_valid(vcpu, vmcs12->eptp_list_address)) | |
11362 | return VMXERR_ENTRY_INVALID_CONTROL_FIELD; | |
11363 | } | |
11364 | } | |
27c42a1b | 11365 | |
c7c2c709 JM |
11366 | if (vmcs12->cr3_target_count > nested_cpu_vmx_misc_cr3_count(vcpu)) |
11367 | return VMXERR_ENTRY_INVALID_CONTROL_FIELD; | |
11368 | ||
3899152c | 11369 | if (!nested_host_cr0_valid(vcpu, vmcs12->host_cr0) || |
1dc35dac | 11370 | !nested_host_cr4_valid(vcpu, vmcs12->host_cr4) || |
ca0bde28 JM |
11371 | !nested_cr3_valid(vcpu, vmcs12->host_cr3)) |
11372 | return VMXERR_ENTRY_INVALID_HOST_STATE_FIELD; | |
11373 | ||
11374 | return 0; | |
11375 | } | |
11376 | ||
11377 | static int check_vmentry_postreqs(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12, | |
11378 | u32 *exit_qual) | |
11379 | { | |
11380 | bool ia32e; | |
11381 | ||
11382 | *exit_qual = ENTRY_FAIL_DEFAULT; | |
7c177938 | 11383 | |
3899152c | 11384 | if (!nested_guest_cr0_valid(vcpu, vmcs12->guest_cr0) || |
ca0bde28 | 11385 | !nested_guest_cr4_valid(vcpu, vmcs12->guest_cr4)) |
b428018a | 11386 | return 1; |
ca0bde28 JM |
11387 | |
11388 | if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_SHADOW_VMCS) && | |
11389 | vmcs12->vmcs_link_pointer != -1ull) { | |
11390 | *exit_qual = ENTRY_FAIL_VMCS_LINK_PTR; | |
b428018a | 11391 | return 1; |
7c177938 NHE |
11392 | } |
11393 | ||
384bb783 | 11394 | /* |
cb0c8cda | 11395 | * If the load IA32_EFER VM-entry control is 1, the following checks |
384bb783 JK |
11396 | * are performed on the field for the IA32_EFER MSR: |
11397 | * - Bits reserved in the IA32_EFER MSR must be 0. | |
11398 | * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of | |
11399 | * the IA-32e mode guest VM-exit control. It must also be identical | |
11400 | * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to | |
11401 | * CR0.PG) is 1. | |
11402 | */ | |
ca0bde28 JM |
11403 | if (to_vmx(vcpu)->nested.nested_run_pending && |
11404 | (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)) { | |
384bb783 JK |
11405 | ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0; |
11406 | if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) || | |
11407 | ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) || | |
11408 | ((vmcs12->guest_cr0 & X86_CR0_PG) && | |
ca0bde28 | 11409 | ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) |
b428018a | 11410 | return 1; |
384bb783 JK |
11411 | } |
11412 | ||
11413 | /* | |
11414 | * If the load IA32_EFER VM-exit control is 1, bits reserved in the | |
11415 | * IA32_EFER MSR must be 0 in the field for that register. In addition, | |
11416 | * the values of the LMA and LME bits in the field must each be that of | |
11417 | * the host address-space size VM-exit control. | |
11418 | */ | |
11419 | if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) { | |
11420 | ia32e = (vmcs12->vm_exit_controls & | |
11421 | VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0; | |
11422 | if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) || | |
11423 | ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) || | |
ca0bde28 | 11424 | ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) |
b428018a | 11425 | return 1; |
ca0bde28 JM |
11426 | } |
11427 | ||
f1b026a3 WL |
11428 | if ((vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS) && |
11429 | (is_noncanonical_address(vmcs12->guest_bndcfgs & PAGE_MASK, vcpu) || | |
11430 | (vmcs12->guest_bndcfgs & MSR_IA32_BNDCFGS_RSVD))) | |
11431 | return 1; | |
11432 | ||
ca0bde28 JM |
11433 | return 0; |
11434 | } | |
11435 | ||
858e25c0 JM |
11436 | static int enter_vmx_non_root_mode(struct kvm_vcpu *vcpu, bool from_vmentry) |
11437 | { | |
11438 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
11439 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); | |
858e25c0 | 11440 | u32 exit_qual; |
f7f5542f | 11441 | int r; |
858e25c0 | 11442 | |
858e25c0 JM |
11443 | enter_guest_mode(vcpu); |
11444 | ||
11445 | if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS)) | |
11446 | vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL); | |
11447 | ||
8819227c | 11448 | vmx_switch_vmcs(vcpu, &vmx->nested.vmcs02); |
9ee802b1 | 11449 | vmx_segment_cache_clear(vmx); |
858e25c0 | 11450 | |
f7f5542f KA |
11451 | if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING) |
11452 | vcpu->arch.tsc_offset += vmcs12->tsc_offset; | |
11453 | ||
11454 | r = EXIT_REASON_INVALID_STATE; | |
11455 | if (prepare_vmcs02(vcpu, vmcs12, from_vmentry, &exit_qual)) | |
11456 | goto fail; | |
858e25c0 JM |
11457 | |
11458 | nested_get_vmcs12_pages(vcpu, vmcs12); | |
11459 | ||
f7f5542f | 11460 | r = EXIT_REASON_MSR_LOAD_FAIL; |
4fddb9c5 JM |
11461 | exit_qual = nested_vmx_load_msr(vcpu, |
11462 | vmcs12->vm_entry_msr_load_addr, | |
11463 | vmcs12->vm_entry_msr_load_count); | |
11464 | if (exit_qual) | |
f7f5542f | 11465 | goto fail; |
858e25c0 | 11466 | |
858e25c0 JM |
11467 | /* |
11468 | * Note no nested_vmx_succeed or nested_vmx_fail here. At this point | |
11469 | * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet | |
11470 | * returned as far as L1 is concerned. It will only return (and set | |
11471 | * the success flag) when L2 exits (see nested_vmx_vmexit()). | |
11472 | */ | |
11473 | return 0; | |
f7f5542f KA |
11474 | |
11475 | fail: | |
11476 | if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING) | |
11477 | vcpu->arch.tsc_offset -= vmcs12->tsc_offset; | |
11478 | leave_guest_mode(vcpu); | |
11479 | vmx_switch_vmcs(vcpu, &vmx->vmcs01); | |
11480 | nested_vmx_entry_failure(vcpu, vmcs12, r, exit_qual); | |
11481 | return 1; | |
858e25c0 JM |
11482 | } |
11483 | ||
ca0bde28 JM |
11484 | /* |
11485 | * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1 | |
11486 | * for running an L2 nested guest. | |
11487 | */ | |
11488 | static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch) | |
11489 | { | |
11490 | struct vmcs12 *vmcs12; | |
11491 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
b3f1dfb6 | 11492 | u32 interrupt_shadow = vmx_get_interrupt_shadow(vcpu); |
ca0bde28 JM |
11493 | u32 exit_qual; |
11494 | int ret; | |
11495 | ||
11496 | if (!nested_vmx_check_permission(vcpu)) | |
11497 | return 1; | |
11498 | ||
11499 | if (!nested_vmx_check_vmcs12(vcpu)) | |
11500 | goto out; | |
11501 | ||
11502 | vmcs12 = get_vmcs12(vcpu); | |
11503 | ||
11504 | if (enable_shadow_vmcs) | |
11505 | copy_shadow_to_vmcs12(vmx); | |
11506 | ||
11507 | /* | |
11508 | * The nested entry process starts with enforcing various prerequisites | |
11509 | * on vmcs12 as required by the Intel SDM, and act appropriately when | |
11510 | * they fail: As the SDM explains, some conditions should cause the | |
11511 | * instruction to fail, while others will cause the instruction to seem | |
11512 | * to succeed, but return an EXIT_REASON_INVALID_STATE. | |
11513 | * To speed up the normal (success) code path, we should avoid checking | |
11514 | * for misconfigurations which will anyway be caught by the processor | |
11515 | * when using the merged vmcs02. | |
11516 | */ | |
b3f1dfb6 JM |
11517 | if (interrupt_shadow & KVM_X86_SHADOW_INT_MOV_SS) { |
11518 | nested_vmx_failValid(vcpu, | |
11519 | VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS); | |
11520 | goto out; | |
11521 | } | |
11522 | ||
ca0bde28 JM |
11523 | if (vmcs12->launch_state == launch) { |
11524 | nested_vmx_failValid(vcpu, | |
11525 | launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS | |
11526 | : VMXERR_VMRESUME_NONLAUNCHED_VMCS); | |
11527 | goto out; | |
11528 | } | |
11529 | ||
11530 | ret = check_vmentry_prereqs(vcpu, vmcs12); | |
11531 | if (ret) { | |
11532 | nested_vmx_failValid(vcpu, ret); | |
11533 | goto out; | |
11534 | } | |
11535 | ||
11536 | /* | |
11537 | * After this point, the trap flag no longer triggers a singlestep trap | |
11538 | * on the vm entry instructions; don't call kvm_skip_emulated_instruction. | |
11539 | * This is not 100% correct; for performance reasons, we delegate most | |
11540 | * of the checks on host state to the processor. If those fail, | |
11541 | * the singlestep trap is missed. | |
11542 | */ | |
11543 | skip_emulated_instruction(vcpu); | |
11544 | ||
11545 | ret = check_vmentry_postreqs(vcpu, vmcs12, &exit_qual); | |
11546 | if (ret) { | |
11547 | nested_vmx_entry_failure(vcpu, vmcs12, | |
11548 | EXIT_REASON_INVALID_STATE, exit_qual); | |
11549 | return 1; | |
384bb783 JK |
11550 | } |
11551 | ||
7c177938 NHE |
11552 | /* |
11553 | * We're finally done with prerequisite checking, and can start with | |
11554 | * the nested entry. | |
11555 | */ | |
11556 | ||
858e25c0 JM |
11557 | ret = enter_vmx_non_root_mode(vcpu, true); |
11558 | if (ret) | |
11559 | return ret; | |
ff651cb6 | 11560 | |
f0ace387 PB |
11561 | /* Hide L1D cache contents from the nested guest. */ |
11562 | vmx->vcpu.arch.l1tf_flush_l1d = true; | |
11563 | ||
076381c4 CG |
11564 | /* |
11565 | * If we're entering a halted L2 vcpu and the L2 vcpu won't be woken | |
11566 | * by event injection, halt vcpu. | |
11567 | */ | |
11568 | if ((vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT) && | |
11569 | !(vmcs12->vm_entry_intr_info_field & INTR_INFO_VALID_MASK)) | |
5cb56059 | 11570 | return kvm_vcpu_halt(vcpu); |
6dfacadd | 11571 | |
7af40ad3 JK |
11572 | vmx->nested.nested_run_pending = 1; |
11573 | ||
cd232ad0 | 11574 | return 1; |
eb277562 KH |
11575 | |
11576 | out: | |
6affcbed | 11577 | return kvm_skip_emulated_instruction(vcpu); |
cd232ad0 NHE |
11578 | } |
11579 | ||
4704d0be NHE |
11580 | /* |
11581 | * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date | |
11582 | * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK). | |
11583 | * This function returns the new value we should put in vmcs12.guest_cr0. | |
11584 | * It's not enough to just return the vmcs02 GUEST_CR0. Rather, | |
11585 | * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now | |
11586 | * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0 | |
11587 | * didn't trap the bit, because if L1 did, so would L0). | |
11588 | * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have | |
11589 | * been modified by L2, and L1 knows it. So just leave the old value of | |
11590 | * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0 | |
11591 | * isn't relevant, because if L0 traps this bit it can set it to anything. | |
11592 | * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have | |
11593 | * changed these bits, and therefore they need to be updated, but L0 | |
11594 | * didn't necessarily allow them to be changed in GUEST_CR0 - and rather | |
11595 | * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there. | |
11596 | */ | |
11597 | static inline unsigned long | |
11598 | vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12) | |
11599 | { | |
11600 | return | |
11601 | /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) | | |
11602 | /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) | | |
11603 | /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask | | |
11604 | vcpu->arch.cr0_guest_owned_bits)); | |
11605 | } | |
11606 | ||
11607 | static inline unsigned long | |
11608 | vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12) | |
11609 | { | |
11610 | return | |
11611 | /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) | | |
11612 | /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) | | |
11613 | /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask | | |
11614 | vcpu->arch.cr4_guest_owned_bits)); | |
11615 | } | |
11616 | ||
5f3d5799 JK |
11617 | static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu, |
11618 | struct vmcs12 *vmcs12) | |
11619 | { | |
11620 | u32 idt_vectoring; | |
11621 | unsigned int nr; | |
11622 | ||
664f8e26 | 11623 | if (vcpu->arch.exception.injected) { |
5f3d5799 JK |
11624 | nr = vcpu->arch.exception.nr; |
11625 | idt_vectoring = nr | VECTORING_INFO_VALID_MASK; | |
11626 | ||
11627 | if (kvm_exception_is_soft(nr)) { | |
11628 | vmcs12->vm_exit_instruction_len = | |
11629 | vcpu->arch.event_exit_inst_len; | |
11630 | idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION; | |
11631 | } else | |
11632 | idt_vectoring |= INTR_TYPE_HARD_EXCEPTION; | |
11633 | ||
11634 | if (vcpu->arch.exception.has_error_code) { | |
11635 | idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK; | |
11636 | vmcs12->idt_vectoring_error_code = | |
11637 | vcpu->arch.exception.error_code; | |
11638 | } | |
11639 | ||
11640 | vmcs12->idt_vectoring_info_field = idt_vectoring; | |
cd2633c5 | 11641 | } else if (vcpu->arch.nmi_injected) { |
5f3d5799 JK |
11642 | vmcs12->idt_vectoring_info_field = |
11643 | INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR; | |
11644 | } else if (vcpu->arch.interrupt.pending) { | |
11645 | nr = vcpu->arch.interrupt.nr; | |
11646 | idt_vectoring = nr | VECTORING_INFO_VALID_MASK; | |
11647 | ||
11648 | if (vcpu->arch.interrupt.soft) { | |
11649 | idt_vectoring |= INTR_TYPE_SOFT_INTR; | |
11650 | vmcs12->vm_entry_instruction_len = | |
11651 | vcpu->arch.event_exit_inst_len; | |
11652 | } else | |
11653 | idt_vectoring |= INTR_TYPE_EXT_INTR; | |
11654 | ||
11655 | vmcs12->idt_vectoring_info_field = idt_vectoring; | |
11656 | } | |
11657 | } | |
11658 | ||
b6b8a145 JK |
11659 | static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr) |
11660 | { | |
11661 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
bfcf83b1 | 11662 | unsigned long exit_qual; |
917dc606 LA |
11663 | bool block_nested_events = |
11664 | vmx->nested.nested_run_pending || kvm_event_needs_reinjection(vcpu); | |
acc9ab60 | 11665 | |
bfcf83b1 WL |
11666 | if (vcpu->arch.exception.pending && |
11667 | nested_vmx_check_exception(vcpu, &exit_qual)) { | |
917dc606 | 11668 | if (block_nested_events) |
bfcf83b1 WL |
11669 | return -EBUSY; |
11670 | nested_vmx_inject_exception_vmexit(vcpu, exit_qual); | |
bfcf83b1 WL |
11671 | return 0; |
11672 | } | |
11673 | ||
f4124500 JK |
11674 | if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) && |
11675 | vmx->nested.preemption_timer_expired) { | |
917dc606 | 11676 | if (block_nested_events) |
f4124500 JK |
11677 | return -EBUSY; |
11678 | nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0); | |
11679 | return 0; | |
11680 | } | |
11681 | ||
b6b8a145 | 11682 | if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) { |
917dc606 | 11683 | if (block_nested_events) |
b6b8a145 JK |
11684 | return -EBUSY; |
11685 | nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI, | |
11686 | NMI_VECTOR | INTR_TYPE_NMI_INTR | | |
11687 | INTR_INFO_VALID_MASK, 0); | |
11688 | /* | |
11689 | * The NMI-triggered VM exit counts as injection: | |
11690 | * clear this one and block further NMIs. | |
11691 | */ | |
11692 | vcpu->arch.nmi_pending = 0; | |
11693 | vmx_set_nmi_mask(vcpu, true); | |
11694 | return 0; | |
11695 | } | |
11696 | ||
11697 | if ((kvm_cpu_has_interrupt(vcpu) || external_intr) && | |
11698 | nested_exit_on_intr(vcpu)) { | |
917dc606 | 11699 | if (block_nested_events) |
b6b8a145 JK |
11700 | return -EBUSY; |
11701 | nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0); | |
705699a1 | 11702 | return 0; |
b6b8a145 JK |
11703 | } |
11704 | ||
6342c50a DH |
11705 | vmx_complete_nested_posted_interrupt(vcpu); |
11706 | return 0; | |
b6b8a145 JK |
11707 | } |
11708 | ||
f4124500 JK |
11709 | static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu) |
11710 | { | |
11711 | ktime_t remaining = | |
11712 | hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer); | |
11713 | u64 value; | |
11714 | ||
11715 | if (ktime_to_ns(remaining) <= 0) | |
11716 | return 0; | |
11717 | ||
11718 | value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz; | |
11719 | do_div(value, 1000000); | |
11720 | return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE; | |
11721 | } | |
11722 | ||
4704d0be | 11723 | /* |
cf8b84f4 JM |
11724 | * Update the guest state fields of vmcs12 to reflect changes that |
11725 | * occurred while L2 was running. (The "IA-32e mode guest" bit of the | |
11726 | * VM-entry controls is also updated, since this is really a guest | |
11727 | * state bit.) | |
4704d0be | 11728 | */ |
cf8b84f4 | 11729 | static void sync_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12) |
4704d0be | 11730 | { |
4704d0be NHE |
11731 | vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12); |
11732 | vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12); | |
11733 | ||
4704d0be NHE |
11734 | vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP); |
11735 | vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP); | |
11736 | vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS); | |
11737 | ||
11738 | vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR); | |
11739 | vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR); | |
11740 | vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR); | |
11741 | vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR); | |
11742 | vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR); | |
11743 | vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR); | |
11744 | vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR); | |
11745 | vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR); | |
11746 | vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT); | |
11747 | vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT); | |
11748 | vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT); | |
11749 | vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT); | |
11750 | vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT); | |
11751 | vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT); | |
11752 | vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT); | |
11753 | vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT); | |
11754 | vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT); | |
11755 | vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT); | |
11756 | vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES); | |
11757 | vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES); | |
11758 | vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES); | |
11759 | vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES); | |
11760 | vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES); | |
11761 | vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES); | |
11762 | vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES); | |
11763 | vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES); | |
11764 | vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE); | |
11765 | vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE); | |
11766 | vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE); | |
11767 | vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE); | |
11768 | vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE); | |
11769 | vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE); | |
11770 | vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE); | |
11771 | vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE); | |
11772 | vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE); | |
11773 | vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE); | |
11774 | ||
4704d0be NHE |
11775 | vmcs12->guest_interruptibility_info = |
11776 | vmcs_read32(GUEST_INTERRUPTIBILITY_INFO); | |
11777 | vmcs12->guest_pending_dbg_exceptions = | |
11778 | vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS); | |
3edf1e69 JK |
11779 | if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED) |
11780 | vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT; | |
11781 | else | |
11782 | vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE; | |
4704d0be | 11783 | |
f4124500 JK |
11784 | if (nested_cpu_has_preemption_timer(vmcs12)) { |
11785 | if (vmcs12->vm_exit_controls & | |
11786 | VM_EXIT_SAVE_VMX_PREEMPTION_TIMER) | |
11787 | vmcs12->vmx_preemption_timer_value = | |
11788 | vmx_get_preemption_timer_value(vcpu); | |
11789 | hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer); | |
11790 | } | |
7854cbca | 11791 | |
3633cfc3 NHE |
11792 | /* |
11793 | * In some cases (usually, nested EPT), L2 is allowed to change its | |
11794 | * own CR3 without exiting. If it has changed it, we must keep it. | |
11795 | * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined | |
11796 | * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12. | |
11797 | * | |
11798 | * Additionally, restore L2's PDPTR to vmcs12. | |
11799 | */ | |
11800 | if (enable_ept) { | |
f3531054 | 11801 | vmcs12->guest_cr3 = vmcs_readl(GUEST_CR3); |
3633cfc3 NHE |
11802 | vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0); |
11803 | vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1); | |
11804 | vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2); | |
11805 | vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3); | |
11806 | } | |
11807 | ||
d281e13b | 11808 | vmcs12->guest_linear_address = vmcs_readl(GUEST_LINEAR_ADDRESS); |
119a9c01 | 11809 | |
608406e2 WV |
11810 | if (nested_cpu_has_vid(vmcs12)) |
11811 | vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS); | |
11812 | ||
c18911a2 JK |
11813 | vmcs12->vm_entry_controls = |
11814 | (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) | | |
2961e876 | 11815 | (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE); |
c18911a2 | 11816 | |
2996fca0 JK |
11817 | if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) { |
11818 | kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7); | |
11819 | vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL); | |
11820 | } | |
11821 | ||
4704d0be NHE |
11822 | /* TODO: These cannot have changed unless we have MSR bitmaps and |
11823 | * the relevant bit asks not to trap the change */ | |
b8c07d55 | 11824 | if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT) |
4704d0be | 11825 | vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT); |
10ba54a5 JK |
11826 | if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER) |
11827 | vmcs12->guest_ia32_efer = vcpu->arch.efer; | |
4704d0be NHE |
11828 | vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS); |
11829 | vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP); | |
11830 | vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP); | |
a87036ad | 11831 | if (kvm_mpx_supported()) |
36be0b9d | 11832 | vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS); |
cf8b84f4 JM |
11833 | } |
11834 | ||
11835 | /* | |
11836 | * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits | |
11837 | * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12), | |
11838 | * and this function updates it to reflect the changes to the guest state while | |
11839 | * L2 was running (and perhaps made some exits which were handled directly by L0 | |
11840 | * without going back to L1), and to reflect the exit reason. | |
11841 | * Note that we do not have to copy here all VMCS fields, just those that | |
11842 | * could have changed by the L2 guest or the exit - i.e., the guest-state and | |
11843 | * exit-information fields only. Other fields are modified by L1 with VMWRITE, | |
11844 | * which already writes to vmcs12 directly. | |
11845 | */ | |
11846 | static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12, | |
11847 | u32 exit_reason, u32 exit_intr_info, | |
11848 | unsigned long exit_qualification) | |
11849 | { | |
11850 | /* update guest state fields: */ | |
11851 | sync_vmcs12(vcpu, vmcs12); | |
4704d0be NHE |
11852 | |
11853 | /* update exit information fields: */ | |
11854 | ||
533558bc JK |
11855 | vmcs12->vm_exit_reason = exit_reason; |
11856 | vmcs12->exit_qualification = exit_qualification; | |
533558bc | 11857 | vmcs12->vm_exit_intr_info = exit_intr_info; |
7313c698 | 11858 | |
5f3d5799 | 11859 | vmcs12->idt_vectoring_info_field = 0; |
4704d0be NHE |
11860 | vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN); |
11861 | vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO); | |
11862 | ||
5f3d5799 | 11863 | if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) { |
7cdc2d62 JM |
11864 | vmcs12->launch_state = 1; |
11865 | ||
5f3d5799 JK |
11866 | /* vm_entry_intr_info_field is cleared on exit. Emulate this |
11867 | * instead of reading the real value. */ | |
4704d0be | 11868 | vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK; |
5f3d5799 JK |
11869 | |
11870 | /* | |
11871 | * Transfer the event that L0 or L1 may wanted to inject into | |
11872 | * L2 to IDT_VECTORING_INFO_FIELD. | |
11873 | */ | |
11874 | vmcs12_save_pending_event(vcpu, vmcs12); | |
11875 | } | |
11876 | ||
11877 | /* | |
11878 | * Drop what we picked up for L2 via vmx_complete_interrupts. It is | |
11879 | * preserved above and would only end up incorrectly in L1. | |
11880 | */ | |
11881 | vcpu->arch.nmi_injected = false; | |
11882 | kvm_clear_exception_queue(vcpu); | |
11883 | kvm_clear_interrupt_queue(vcpu); | |
4704d0be NHE |
11884 | } |
11885 | ||
11886 | /* | |
11887 | * A part of what we need to when the nested L2 guest exits and we want to | |
11888 | * run its L1 parent, is to reset L1's guest state to the host state specified | |
11889 | * in vmcs12. | |
11890 | * This function is to be called not only on normal nested exit, but also on | |
11891 | * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry | |
11892 | * Failures During or After Loading Guest State"). | |
11893 | * This function should be called when the active VMCS is L1's (vmcs01). | |
11894 | */ | |
733568f9 JK |
11895 | static void load_vmcs12_host_state(struct kvm_vcpu *vcpu, |
11896 | struct vmcs12 *vmcs12) | |
4704d0be | 11897 | { |
21feb4eb | 11898 | struct kvm_segment seg; |
c08567af | 11899 | u32 entry_failure_code; |
21feb4eb | 11900 | |
4704d0be NHE |
11901 | if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) |
11902 | vcpu->arch.efer = vmcs12->host_ia32_efer; | |
d1fa0352 | 11903 | else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE) |
4704d0be NHE |
11904 | vcpu->arch.efer |= (EFER_LMA | EFER_LME); |
11905 | else | |
11906 | vcpu->arch.efer &= ~(EFER_LMA | EFER_LME); | |
11907 | vmx_set_efer(vcpu, vcpu->arch.efer); | |
11908 | ||
11909 | kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp); | |
11910 | kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip); | |
1adfa76a | 11911 | vmx_set_rflags(vcpu, X86_EFLAGS_FIXED); |
4704d0be NHE |
11912 | /* |
11913 | * Note that calling vmx_set_cr0 is important, even if cr0 hasn't | |
bd7e5b08 PB |
11914 | * actually changed, because vmx_set_cr0 refers to efer set above. |
11915 | * | |
11916 | * CR0_GUEST_HOST_MASK is already set in the original vmcs01 | |
11917 | * (KVM doesn't change it); | |
4704d0be | 11918 | */ |
bd7e5b08 | 11919 | vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS; |
9e3e4dbf | 11920 | vmx_set_cr0(vcpu, vmcs12->host_cr0); |
4704d0be | 11921 | |
bd7e5b08 | 11922 | /* Same as above - no reason to call set_cr4_guest_host_mask(). */ |
4704d0be | 11923 | vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK); |
8eb3f87d | 11924 | vmx_set_cr4(vcpu, vmcs12->host_cr4); |
4704d0be | 11925 | |
c08567af SC |
11926 | nested_ept_uninit_mmu_context(vcpu); |
11927 | ||
11928 | /* | |
11929 | * Only PDPTE load can fail as the value of cr3 was checked on entry and | |
11930 | * couldn't have changed. | |
11931 | */ | |
11932 | if (nested_vmx_load_cr3(vcpu, vmcs12->host_cr3, false, &entry_failure_code)) | |
11933 | nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_PDPTE_FAIL); | |
11934 | ||
11935 | if (!enable_ept) | |
11936 | vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault; | |
feaf0c7d | 11937 | |
4704d0be NHE |
11938 | if (enable_vpid) { |
11939 | /* | |
11940 | * Trivially support vpid by letting L2s share their parent | |
11941 | * L1's vpid. TODO: move to a more elaborate solution, giving | |
11942 | * each L2 its own vpid and exposing the vpid feature to L1. | |
11943 | */ | |
6bf41e55 | 11944 | vmx_flush_tlb(vcpu, true); |
4704d0be | 11945 | } |
06a5524f WV |
11946 | /* Restore posted intr vector. */ |
11947 | if (nested_cpu_has_posted_intr(vmcs12)) | |
11948 | vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR); | |
4704d0be NHE |
11949 | |
11950 | vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs); | |
11951 | vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp); | |
11952 | vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip); | |
11953 | vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base); | |
11954 | vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base); | |
21f2d551 LP |
11955 | vmcs_write32(GUEST_IDTR_LIMIT, 0xFFFF); |
11956 | vmcs_write32(GUEST_GDTR_LIMIT, 0xFFFF); | |
4704d0be | 11957 | |
36be0b9d PB |
11958 | /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */ |
11959 | if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS) | |
11960 | vmcs_write64(GUEST_BNDCFGS, 0); | |
11961 | ||
44811c02 | 11962 | if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) { |
4704d0be | 11963 | vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat); |
44811c02 JK |
11964 | vcpu->arch.pat = vmcs12->host_ia32_pat; |
11965 | } | |
4704d0be NHE |
11966 | if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL) |
11967 | vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL, | |
11968 | vmcs12->host_ia32_perf_global_ctrl); | |
503cd0c5 | 11969 | |
21feb4eb ACL |
11970 | /* Set L1 segment info according to Intel SDM |
11971 | 27.5.2 Loading Host Segment and Descriptor-Table Registers */ | |
11972 | seg = (struct kvm_segment) { | |
11973 | .base = 0, | |
11974 | .limit = 0xFFFFFFFF, | |
11975 | .selector = vmcs12->host_cs_selector, | |
11976 | .type = 11, | |
11977 | .present = 1, | |
11978 | .s = 1, | |
11979 | .g = 1 | |
11980 | }; | |
11981 | if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE) | |
11982 | seg.l = 1; | |
11983 | else | |
11984 | seg.db = 1; | |
11985 | vmx_set_segment(vcpu, &seg, VCPU_SREG_CS); | |
11986 | seg = (struct kvm_segment) { | |
11987 | .base = 0, | |
11988 | .limit = 0xFFFFFFFF, | |
11989 | .type = 3, | |
11990 | .present = 1, | |
11991 | .s = 1, | |
11992 | .db = 1, | |
11993 | .g = 1 | |
11994 | }; | |
11995 | seg.selector = vmcs12->host_ds_selector; | |
11996 | vmx_set_segment(vcpu, &seg, VCPU_SREG_DS); | |
11997 | seg.selector = vmcs12->host_es_selector; | |
11998 | vmx_set_segment(vcpu, &seg, VCPU_SREG_ES); | |
11999 | seg.selector = vmcs12->host_ss_selector; | |
12000 | vmx_set_segment(vcpu, &seg, VCPU_SREG_SS); | |
12001 | seg.selector = vmcs12->host_fs_selector; | |
12002 | seg.base = vmcs12->host_fs_base; | |
12003 | vmx_set_segment(vcpu, &seg, VCPU_SREG_FS); | |
12004 | seg.selector = vmcs12->host_gs_selector; | |
12005 | seg.base = vmcs12->host_gs_base; | |
12006 | vmx_set_segment(vcpu, &seg, VCPU_SREG_GS); | |
12007 | seg = (struct kvm_segment) { | |
205befd9 | 12008 | .base = vmcs12->host_tr_base, |
21feb4eb ACL |
12009 | .limit = 0x67, |
12010 | .selector = vmcs12->host_tr_selector, | |
12011 | .type = 11, | |
12012 | .present = 1 | |
12013 | }; | |
12014 | vmx_set_segment(vcpu, &seg, VCPU_SREG_TR); | |
12015 | ||
503cd0c5 JK |
12016 | kvm_set_dr(vcpu, 7, 0x400); |
12017 | vmcs_write64(GUEST_IA32_DEBUGCTL, 0); | |
ff651cb6 | 12018 | |
3af18d9c | 12019 | if (cpu_has_vmx_msr_bitmap()) |
4b0be90f | 12020 | vmx_update_msr_bitmap(vcpu); |
3af18d9c | 12021 | |
ff651cb6 WV |
12022 | if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr, |
12023 | vmcs12->vm_exit_msr_load_count)) | |
12024 | nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL); | |
4704d0be NHE |
12025 | } |
12026 | ||
c08567af SC |
12027 | static inline u64 nested_vmx_get_vmcs01_guest_efer(struct vcpu_vmx *vmx) |
12028 | { | |
12029 | struct shared_msr_entry *efer_msr; | |
12030 | unsigned int i; | |
12031 | ||
12032 | if (vm_entry_controls_get(vmx) & VM_ENTRY_LOAD_IA32_EFER) | |
12033 | return vmcs_read64(GUEST_IA32_EFER); | |
12034 | ||
12035 | if (cpu_has_load_ia32_efer) | |
12036 | return host_efer; | |
12037 | ||
12038 | for (i = 0; i < vmx->msr_autoload.guest.nr; ++i) { | |
12039 | if (vmx->msr_autoload.guest.val[i].index == MSR_EFER) | |
12040 | return vmx->msr_autoload.guest.val[i].value; | |
12041 | } | |
12042 | ||
12043 | efer_msr = find_msr_entry(vmx, MSR_EFER); | |
12044 | if (efer_msr) | |
12045 | return efer_msr->data; | |
12046 | ||
12047 | return host_efer; | |
12048 | } | |
12049 | ||
12050 | static void nested_vmx_restore_host_state(struct kvm_vcpu *vcpu) | |
12051 | { | |
12052 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); | |
12053 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
12054 | struct vmx_msr_entry g, h; | |
12055 | struct msr_data msr; | |
12056 | gpa_t gpa; | |
12057 | u32 i, j; | |
12058 | ||
12059 | vcpu->arch.pat = vmcs_read64(GUEST_IA32_PAT); | |
12060 | ||
12061 | if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS) { | |
12062 | /* | |
12063 | * L1's host DR7 is lost if KVM_GUESTDBG_USE_HW_BP is set | |
12064 | * as vmcs01.GUEST_DR7 contains a userspace defined value | |
12065 | * and vcpu->arch.dr7 is not squirreled away before the | |
12066 | * nested VMENTER (not worth adding a variable in nested_vmx). | |
12067 | */ | |
12068 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) | |
12069 | kvm_set_dr(vcpu, 7, DR7_FIXED_1); | |
12070 | else | |
12071 | WARN_ON(kvm_set_dr(vcpu, 7, vmcs_readl(GUEST_DR7))); | |
12072 | } | |
12073 | ||
12074 | /* | |
12075 | * Note that calling vmx_set_{efer,cr0,cr4} is important as they | |
12076 | * handle a variety of side effects to KVM's software model. | |
12077 | */ | |
12078 | vmx_set_efer(vcpu, nested_vmx_get_vmcs01_guest_efer(vmx)); | |
12079 | ||
12080 | vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS; | |
12081 | vmx_set_cr0(vcpu, vmcs_readl(CR0_READ_SHADOW)); | |
12082 | ||
12083 | vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK); | |
12084 | vmx_set_cr4(vcpu, vmcs_readl(CR4_READ_SHADOW)); | |
12085 | ||
12086 | nested_ept_uninit_mmu_context(vcpu); | |
12087 | vcpu->arch.cr3 = vmcs_readl(GUEST_CR3); | |
12088 | __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail); | |
12089 | ||
12090 | /* | |
12091 | * Use ept_save_pdptrs(vcpu) to load the MMU's cached PDPTRs | |
12092 | * from vmcs01 (if necessary). The PDPTRs are not loaded on | |
12093 | * VMFail, like everything else we just need to ensure our | |
12094 | * software model is up-to-date. | |
12095 | */ | |
12096 | ept_save_pdptrs(vcpu); | |
12097 | ||
12098 | kvm_mmu_reset_context(vcpu); | |
12099 | ||
12100 | if (cpu_has_vmx_msr_bitmap()) | |
12101 | vmx_update_msr_bitmap(vcpu); | |
12102 | ||
12103 | /* | |
12104 | * This nasty bit of open coding is a compromise between blindly | |
12105 | * loading L1's MSRs using the exit load lists (incorrect emulation | |
12106 | * of VMFail), leaving the nested VM's MSRs in the software model | |
12107 | * (incorrect behavior) and snapshotting the modified MSRs (too | |
12108 | * expensive since the lists are unbound by hardware). For each | |
12109 | * MSR that was (prematurely) loaded from the nested VMEntry load | |
12110 | * list, reload it from the exit load list if it exists and differs | |
12111 | * from the guest value. The intent is to stuff host state as | |
12112 | * silently as possible, not to fully process the exit load list. | |
12113 | */ | |
12114 | msr.host_initiated = false; | |
12115 | for (i = 0; i < vmcs12->vm_entry_msr_load_count; i++) { | |
12116 | gpa = vmcs12->vm_entry_msr_load_addr + (i * sizeof(g)); | |
12117 | if (kvm_vcpu_read_guest(vcpu, gpa, &g, sizeof(g))) { | |
12118 | pr_debug_ratelimited( | |
12119 | "%s read MSR index failed (%u, 0x%08llx)\n", | |
12120 | __func__, i, gpa); | |
12121 | goto vmabort; | |
12122 | } | |
12123 | ||
12124 | for (j = 0; j < vmcs12->vm_exit_msr_load_count; j++) { | |
12125 | gpa = vmcs12->vm_exit_msr_load_addr + (j * sizeof(h)); | |
12126 | if (kvm_vcpu_read_guest(vcpu, gpa, &h, sizeof(h))) { | |
12127 | pr_debug_ratelimited( | |
12128 | "%s read MSR failed (%u, 0x%08llx)\n", | |
12129 | __func__, j, gpa); | |
12130 | goto vmabort; | |
12131 | } | |
12132 | if (h.index != g.index) | |
12133 | continue; | |
12134 | if (h.value == g.value) | |
12135 | break; | |
12136 | ||
12137 | if (nested_vmx_load_msr_check(vcpu, &h)) { | |
12138 | pr_debug_ratelimited( | |
12139 | "%s check failed (%u, 0x%x, 0x%x)\n", | |
12140 | __func__, j, h.index, h.reserved); | |
12141 | goto vmabort; | |
12142 | } | |
12143 | ||
12144 | msr.index = h.index; | |
12145 | msr.data = h.value; | |
12146 | if (kvm_set_msr(vcpu, &msr)) { | |
12147 | pr_debug_ratelimited( | |
12148 | "%s WRMSR failed (%u, 0x%x, 0x%llx)\n", | |
12149 | __func__, j, h.index, h.value); | |
12150 | goto vmabort; | |
12151 | } | |
12152 | } | |
12153 | } | |
12154 | ||
12155 | return; | |
12156 | ||
12157 | vmabort: | |
12158 | nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL); | |
12159 | } | |
12160 | ||
4704d0be NHE |
12161 | /* |
12162 | * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1 | |
12163 | * and modify vmcs12 to make it see what it would expect to see there if | |
12164 | * L2 was its real guest. Must only be called when in L2 (is_guest_mode()) | |
12165 | */ | |
533558bc JK |
12166 | static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason, |
12167 | u32 exit_intr_info, | |
12168 | unsigned long exit_qualification) | |
4704d0be NHE |
12169 | { |
12170 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
4704d0be NHE |
12171 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); |
12172 | ||
5f3d5799 JK |
12173 | /* trying to cancel vmlaunch/vmresume is a bug */ |
12174 | WARN_ON_ONCE(vmx->nested.nested_run_pending); | |
12175 | ||
4f350c6d JM |
12176 | /* |
12177 | * The only expected VM-instruction error is "VM entry with | |
12178 | * invalid control field(s)." Anything else indicates a | |
12179 | * problem with L0. | |
12180 | */ | |
12181 | WARN_ON_ONCE(vmx->fail && (vmcs_read32(VM_INSTRUCTION_ERROR) != | |
12182 | VMXERR_ENTRY_INVALID_CONTROL_FIELD)); | |
12183 | ||
4704d0be | 12184 | leave_guest_mode(vcpu); |
4704d0be | 12185 | |
f7f5542f KA |
12186 | if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING) |
12187 | vcpu->arch.tsc_offset -= vmcs12->tsc_offset; | |
12188 | ||
4f350c6d | 12189 | if (likely(!vmx->fail)) { |
72e9cbdb LP |
12190 | if (exit_reason == -1) |
12191 | sync_vmcs12(vcpu, vmcs12); | |
12192 | else | |
12193 | prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info, | |
12194 | exit_qualification); | |
ff651cb6 | 12195 | |
4f350c6d JM |
12196 | if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr, |
12197 | vmcs12->vm_exit_msr_store_count)) | |
12198 | nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL); | |
12199 | } | |
cf3215d9 | 12200 | |
1279a6b1 | 12201 | vmx_switch_vmcs(vcpu, &vmx->vmcs01); |
9ee802b1 GKH |
12202 | vm_entry_controls_reset_shadow(vmx); |
12203 | vm_exit_controls_reset_shadow(vmx); | |
12204 | vmx_segment_cache_clear(vmx); | |
36c3cc42 | 12205 | |
9314006d | 12206 | /* Update any VMCS fields that might have changed while L2 ran */ |
6e3dedb6 KRW |
12207 | vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.host.nr); |
12208 | vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.guest.nr); | |
ea26e4ec | 12209 | vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset); |
9314006d PB |
12210 | if (vmx->hv_deadline_tsc == -1) |
12211 | vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL, | |
12212 | PIN_BASED_VMX_PREEMPTION_TIMER); | |
12213 | else | |
12214 | vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL, | |
12215 | PIN_BASED_VMX_PREEMPTION_TIMER); | |
c95ba92a PF |
12216 | if (kvm_has_tsc_control) |
12217 | decache_tsc_multiplier(vmx); | |
4704d0be | 12218 | |
d3f4c0a5 JM |
12219 | if (vmx->nested.change_vmcs01_virtual_apic_mode) { |
12220 | vmx->nested.change_vmcs01_virtual_apic_mode = false; | |
12221 | vmx_set_virtual_apic_mode(vcpu); | |
fb6c8198 JM |
12222 | } else if (!nested_cpu_has_ept(vmcs12) && |
12223 | nested_cpu_has2(vmcs12, | |
12224 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) { | |
6bf41e55 | 12225 | vmx_flush_tlb(vcpu, true); |
dccbfcf5 | 12226 | } |
4704d0be NHE |
12227 | |
12228 | /* This is needed for same reason as it was needed in prepare_vmcs02 */ | |
12229 | vmx->host_rsp = 0; | |
12230 | ||
12231 | /* Unpin physical memory we referred to in vmcs02 */ | |
12232 | if (vmx->nested.apic_access_page) { | |
53a70daf | 12233 | kvm_release_page_dirty(vmx->nested.apic_access_page); |
48d89b92 | 12234 | vmx->nested.apic_access_page = NULL; |
4704d0be | 12235 | } |
a7c0b07d | 12236 | if (vmx->nested.virtual_apic_page) { |
53a70daf | 12237 | kvm_release_page_dirty(vmx->nested.virtual_apic_page); |
48d89b92 | 12238 | vmx->nested.virtual_apic_page = NULL; |
a7c0b07d | 12239 | } |
705699a1 WV |
12240 | if (vmx->nested.pi_desc_page) { |
12241 | kunmap(vmx->nested.pi_desc_page); | |
53a70daf | 12242 | kvm_release_page_dirty(vmx->nested.pi_desc_page); |
705699a1 WV |
12243 | vmx->nested.pi_desc_page = NULL; |
12244 | vmx->nested.pi_desc = NULL; | |
12245 | } | |
4704d0be | 12246 | |
38b99173 TC |
12247 | /* |
12248 | * We are now running in L2, mmu_notifier will force to reload the | |
12249 | * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1. | |
12250 | */ | |
c83b6d15 | 12251 | kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu); |
38b99173 | 12252 | |
72e9cbdb | 12253 | if (enable_shadow_vmcs && exit_reason != -1) |
012f83cb | 12254 | vmx->nested.sync_shadow_vmcs = true; |
b6b8a145 JK |
12255 | |
12256 | /* in case we halted in L2 */ | |
12257 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; | |
4f350c6d JM |
12258 | |
12259 | if (likely(!vmx->fail)) { | |
12260 | /* | |
12261 | * TODO: SDM says that with acknowledge interrupt on | |
12262 | * exit, bit 31 of the VM-exit interrupt information | |
12263 | * (valid interrupt) is always set to 1 on | |
12264 | * EXIT_REASON_EXTERNAL_INTERRUPT, so we shouldn't | |
12265 | * need kvm_cpu_has_interrupt(). See the commit | |
12266 | * message for details. | |
12267 | */ | |
12268 | if (nested_exit_intr_ack_set(vcpu) && | |
12269 | exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT && | |
12270 | kvm_cpu_has_interrupt(vcpu)) { | |
12271 | int irq = kvm_cpu_get_interrupt(vcpu); | |
12272 | WARN_ON(irq < 0); | |
12273 | vmcs12->vm_exit_intr_info = irq | | |
12274 | INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR; | |
12275 | } | |
12276 | ||
72e9cbdb LP |
12277 | if (exit_reason != -1) |
12278 | trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason, | |
12279 | vmcs12->exit_qualification, | |
12280 | vmcs12->idt_vectoring_info_field, | |
12281 | vmcs12->vm_exit_intr_info, | |
12282 | vmcs12->vm_exit_intr_error_code, | |
12283 | KVM_ISA_VMX); | |
4f350c6d JM |
12284 | |
12285 | load_vmcs12_host_state(vcpu, vmcs12); | |
12286 | ||
12287 | return; | |
12288 | } | |
12289 | ||
12290 | /* | |
12291 | * After an early L2 VM-entry failure, we're now back | |
12292 | * in L1 which thinks it just finished a VMLAUNCH or | |
12293 | * VMRESUME instruction, so we need to set the failure | |
12294 | * flag and the VM-instruction error field of the VMCS | |
12295 | * accordingly. | |
12296 | */ | |
12297 | nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD); | |
5af41573 | 12298 | |
c08567af SC |
12299 | /* |
12300 | * Restore L1's host state to KVM's software model. We're here | |
12301 | * because a consistency check was caught by hardware, which | |
12302 | * means some amount of guest state has been propagated to KVM's | |
12303 | * model and needs to be unwound to the host's state. | |
12304 | */ | |
12305 | nested_vmx_restore_host_state(vcpu); | |
5af41573 | 12306 | |
4f350c6d JM |
12307 | /* |
12308 | * The emulated instruction was already skipped in | |
12309 | * nested_vmx_run, but the updated RIP was never | |
12310 | * written back to the vmcs01. | |
12311 | */ | |
12312 | skip_emulated_instruction(vcpu); | |
12313 | vmx->fail = 0; | |
4704d0be NHE |
12314 | } |
12315 | ||
42124925 JK |
12316 | /* |
12317 | * Forcibly leave nested mode in order to be able to reset the VCPU later on. | |
12318 | */ | |
12319 | static void vmx_leave_nested(struct kvm_vcpu *vcpu) | |
12320 | { | |
2f707d97 WL |
12321 | if (is_guest_mode(vcpu)) { |
12322 | to_vmx(vcpu)->nested.nested_run_pending = 0; | |
533558bc | 12323 | nested_vmx_vmexit(vcpu, -1, 0, 0); |
2f707d97 | 12324 | } |
42124925 JK |
12325 | free_nested(to_vmx(vcpu)); |
12326 | } | |
12327 | ||
7c177938 NHE |
12328 | /* |
12329 | * L1's failure to enter L2 is a subset of a normal exit, as explained in | |
12330 | * 23.7 "VM-entry failures during or after loading guest state" (this also | |
12331 | * lists the acceptable exit-reason and exit-qualification parameters). | |
12332 | * It should only be called before L2 actually succeeded to run, and when | |
12333 | * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss). | |
12334 | */ | |
12335 | static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu, | |
12336 | struct vmcs12 *vmcs12, | |
12337 | u32 reason, unsigned long qualification) | |
12338 | { | |
12339 | load_vmcs12_host_state(vcpu, vmcs12); | |
12340 | vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY; | |
12341 | vmcs12->exit_qualification = qualification; | |
12342 | nested_vmx_succeed(vcpu); | |
012f83cb AG |
12343 | if (enable_shadow_vmcs) |
12344 | to_vmx(vcpu)->nested.sync_shadow_vmcs = true; | |
7c177938 NHE |
12345 | } |
12346 | ||
6335e0e8 OU |
12347 | static int vmx_check_intercept_io(struct kvm_vcpu *vcpu, |
12348 | struct x86_instruction_info *info) | |
12349 | { | |
12350 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); | |
12351 | unsigned short port; | |
12352 | bool intercept; | |
12353 | int size; | |
12354 | ||
12355 | if (info->intercept == x86_intercept_in || | |
12356 | info->intercept == x86_intercept_ins) { | |
12357 | port = info->src_val; | |
12358 | size = info->dst_bytes; | |
12359 | } else { | |
12360 | port = info->dst_val; | |
12361 | size = info->src_bytes; | |
12362 | } | |
12363 | ||
12364 | /* | |
12365 | * If the 'use IO bitmaps' VM-execution control is 0, IO instruction | |
12366 | * VM-exits depend on the 'unconditional IO exiting' VM-execution | |
12367 | * control. | |
12368 | * | |
12369 | * Otherwise, IO instruction VM-exits are controlled by the IO bitmaps. | |
12370 | */ | |
12371 | if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS)) | |
12372 | intercept = nested_cpu_has(vmcs12, | |
12373 | CPU_BASED_UNCOND_IO_EXITING); | |
12374 | else | |
12375 | intercept = nested_vmx_check_io_bitmaps(vcpu, port, size); | |
12376 | ||
12377 | return intercept ? X86EMUL_UNHANDLEABLE : X86EMUL_CONTINUE; | |
12378 | } | |
12379 | ||
8a76d7f2 JR |
12380 | static int vmx_check_intercept(struct kvm_vcpu *vcpu, |
12381 | struct x86_instruction_info *info, | |
12382 | enum x86_intercept_stage stage) | |
12383 | { | |
4b12b681 PB |
12384 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); |
12385 | struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; | |
12386 | ||
6335e0e8 | 12387 | switch (info->intercept) { |
4b12b681 PB |
12388 | /* |
12389 | * RDPID causes #UD if disabled through secondary execution controls. | |
12390 | * Because it is marked as EmulateOnUD, we need to intercept it here. | |
12391 | */ | |
6335e0e8 OU |
12392 | case x86_intercept_rdtscp: |
12393 | if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDTSCP)) { | |
12394 | ctxt->exception.vector = UD_VECTOR; | |
12395 | ctxt->exception.error_code_valid = false; | |
12396 | return X86EMUL_PROPAGATE_FAULT; | |
12397 | } | |
12398 | break; | |
12399 | ||
12400 | case x86_intercept_in: | |
12401 | case x86_intercept_ins: | |
12402 | case x86_intercept_out: | |
12403 | case x86_intercept_outs: | |
12404 | return vmx_check_intercept_io(vcpu, info); | |
4b12b681 PB |
12405 | |
12406 | /* TODO: check more intercepts... */ | |
6335e0e8 OU |
12407 | default: |
12408 | break; | |
12409 | } | |
12410 | ||
7c111381 | 12411 | return X86EMUL_UNHANDLEABLE; |
8a76d7f2 JR |
12412 | } |
12413 | ||
64672c95 YJ |
12414 | #ifdef CONFIG_X86_64 |
12415 | /* (a << shift) / divisor, return 1 if overflow otherwise 0 */ | |
12416 | static inline int u64_shl_div_u64(u64 a, unsigned int shift, | |
12417 | u64 divisor, u64 *result) | |
12418 | { | |
12419 | u64 low = a << shift, high = a >> (64 - shift); | |
12420 | ||
12421 | /* To avoid the overflow on divq */ | |
12422 | if (high >= divisor) | |
12423 | return 1; | |
12424 | ||
12425 | /* Low hold the result, high hold rem which is discarded */ | |
12426 | asm("divq %2\n\t" : "=a" (low), "=d" (high) : | |
12427 | "rm" (divisor), "0" (low), "1" (high)); | |
12428 | *result = low; | |
12429 | ||
12430 | return 0; | |
12431 | } | |
12432 | ||
12433 | static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc) | |
12434 | { | |
12435 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
9175d2e9 PB |
12436 | u64 tscl = rdtsc(); |
12437 | u64 guest_tscl = kvm_read_l1_tsc(vcpu, tscl); | |
12438 | u64 delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl; | |
64672c95 YJ |
12439 | |
12440 | /* Convert to host delta tsc if tsc scaling is enabled */ | |
12441 | if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio && | |
12442 | u64_shl_div_u64(delta_tsc, | |
12443 | kvm_tsc_scaling_ratio_frac_bits, | |
12444 | vcpu->arch.tsc_scaling_ratio, | |
12445 | &delta_tsc)) | |
12446 | return -ERANGE; | |
12447 | ||
12448 | /* | |
12449 | * If the delta tsc can't fit in the 32 bit after the multi shift, | |
12450 | * we can't use the preemption timer. | |
12451 | * It's possible that it fits on later vmentries, but checking | |
12452 | * on every vmentry is costly so we just use an hrtimer. | |
12453 | */ | |
12454 | if (delta_tsc >> (cpu_preemption_timer_multi + 32)) | |
12455 | return -ERANGE; | |
12456 | ||
12457 | vmx->hv_deadline_tsc = tscl + delta_tsc; | |
12458 | vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL, | |
12459 | PIN_BASED_VMX_PREEMPTION_TIMER); | |
c8533544 WL |
12460 | |
12461 | return delta_tsc == 0; | |
64672c95 YJ |
12462 | } |
12463 | ||
12464 | static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu) | |
12465 | { | |
12466 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
12467 | vmx->hv_deadline_tsc = -1; | |
12468 | vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL, | |
12469 | PIN_BASED_VMX_PREEMPTION_TIMER); | |
12470 | } | |
12471 | #endif | |
12472 | ||
48d89b92 | 12473 | static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu) |
ae97a3b8 | 12474 | { |
b4a2d31d RK |
12475 | if (ple_gap) |
12476 | shrink_ple_window(vcpu); | |
ae97a3b8 RK |
12477 | } |
12478 | ||
843e4330 KH |
12479 | static void vmx_slot_enable_log_dirty(struct kvm *kvm, |
12480 | struct kvm_memory_slot *slot) | |
12481 | { | |
12482 | kvm_mmu_slot_leaf_clear_dirty(kvm, slot); | |
12483 | kvm_mmu_slot_largepage_remove_write_access(kvm, slot); | |
12484 | } | |
12485 | ||
12486 | static void vmx_slot_disable_log_dirty(struct kvm *kvm, | |
12487 | struct kvm_memory_slot *slot) | |
12488 | { | |
12489 | kvm_mmu_slot_set_dirty(kvm, slot); | |
12490 | } | |
12491 | ||
12492 | static void vmx_flush_log_dirty(struct kvm *kvm) | |
12493 | { | |
12494 | kvm_flush_pml_buffers(kvm); | |
12495 | } | |
12496 | ||
c5f983f6 BD |
12497 | static int vmx_write_pml_buffer(struct kvm_vcpu *vcpu) |
12498 | { | |
12499 | struct vmcs12 *vmcs12; | |
12500 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
12501 | gpa_t gpa; | |
12502 | struct page *page = NULL; | |
12503 | u64 *pml_address; | |
12504 | ||
12505 | if (is_guest_mode(vcpu)) { | |
12506 | WARN_ON_ONCE(vmx->nested.pml_full); | |
12507 | ||
12508 | /* | |
12509 | * Check if PML is enabled for the nested guest. | |
12510 | * Whether eptp bit 6 is set is already checked | |
12511 | * as part of A/D emulation. | |
12512 | */ | |
12513 | vmcs12 = get_vmcs12(vcpu); | |
12514 | if (!nested_cpu_has_pml(vmcs12)) | |
12515 | return 0; | |
12516 | ||
4769886b | 12517 | if (vmcs12->guest_pml_index >= PML_ENTITY_NUM) { |
c5f983f6 BD |
12518 | vmx->nested.pml_full = true; |
12519 | return 1; | |
12520 | } | |
12521 | ||
12522 | gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS) & ~0xFFFull; | |
12523 | ||
5e2f30b7 DH |
12524 | page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->pml_address); |
12525 | if (is_error_page(page)) | |
c5f983f6 BD |
12526 | return 0; |
12527 | ||
12528 | pml_address = kmap(page); | |
12529 | pml_address[vmcs12->guest_pml_index--] = gpa; | |
12530 | kunmap(page); | |
53a70daf | 12531 | kvm_release_page_clean(page); |
c5f983f6 BD |
12532 | } |
12533 | ||
12534 | return 0; | |
12535 | } | |
12536 | ||
843e4330 KH |
12537 | static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm, |
12538 | struct kvm_memory_slot *memslot, | |
12539 | gfn_t offset, unsigned long mask) | |
12540 | { | |
12541 | kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask); | |
12542 | } | |
12543 | ||
cd39e117 PB |
12544 | static void __pi_post_block(struct kvm_vcpu *vcpu) |
12545 | { | |
12546 | struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); | |
12547 | struct pi_desc old, new; | |
12548 | unsigned int dest; | |
cd39e117 PB |
12549 | |
12550 | do { | |
12551 | old.control = new.control = pi_desc->control; | |
8b306e2f PB |
12552 | WARN(old.nv != POSTED_INTR_WAKEUP_VECTOR, |
12553 | "Wakeup handler not enabled while the VCPU is blocked\n"); | |
cd39e117 PB |
12554 | |
12555 | dest = cpu_physical_id(vcpu->cpu); | |
12556 | ||
12557 | if (x2apic_enabled()) | |
12558 | new.ndst = dest; | |
12559 | else | |
12560 | new.ndst = (dest << 8) & 0xFF00; | |
12561 | ||
cd39e117 PB |
12562 | /* set 'NV' to 'notification vector' */ |
12563 | new.nv = POSTED_INTR_VECTOR; | |
c0a1666b PB |
12564 | } while (cmpxchg64(&pi_desc->control, old.control, |
12565 | new.control) != old.control); | |
cd39e117 | 12566 | |
8b306e2f PB |
12567 | if (!WARN_ON_ONCE(vcpu->pre_pcpu == -1)) { |
12568 | spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu)); | |
cd39e117 | 12569 | list_del(&vcpu->blocked_vcpu_list); |
8b306e2f | 12570 | spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu)); |
cd39e117 PB |
12571 | vcpu->pre_pcpu = -1; |
12572 | } | |
12573 | } | |
12574 | ||
bf9f6ac8 FW |
12575 | /* |
12576 | * This routine does the following things for vCPU which is going | |
12577 | * to be blocked if VT-d PI is enabled. | |
12578 | * - Store the vCPU to the wakeup list, so when interrupts happen | |
12579 | * we can find the right vCPU to wake up. | |
12580 | * - Change the Posted-interrupt descriptor as below: | |
12581 | * 'NDST' <-- vcpu->pre_pcpu | |
12582 | * 'NV' <-- POSTED_INTR_WAKEUP_VECTOR | |
12583 | * - If 'ON' is set during this process, which means at least one | |
12584 | * interrupt is posted for this vCPU, we cannot block it, in | |
12585 | * this case, return 1, otherwise, return 0. | |
12586 | * | |
12587 | */ | |
bc22512b | 12588 | static int pi_pre_block(struct kvm_vcpu *vcpu) |
bf9f6ac8 | 12589 | { |
bf9f6ac8 FW |
12590 | unsigned int dest; |
12591 | struct pi_desc old, new; | |
12592 | struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); | |
12593 | ||
12594 | if (!kvm_arch_has_assigned_device(vcpu->kvm) || | |
a0052191 YZ |
12595 | !irq_remapping_cap(IRQ_POSTING_CAP) || |
12596 | !kvm_vcpu_apicv_active(vcpu)) | |
bf9f6ac8 FW |
12597 | return 0; |
12598 | ||
8b306e2f PB |
12599 | WARN_ON(irqs_disabled()); |
12600 | local_irq_disable(); | |
12601 | if (!WARN_ON_ONCE(vcpu->pre_pcpu != -1)) { | |
12602 | vcpu->pre_pcpu = vcpu->cpu; | |
12603 | spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu)); | |
12604 | list_add_tail(&vcpu->blocked_vcpu_list, | |
12605 | &per_cpu(blocked_vcpu_on_cpu, | |
12606 | vcpu->pre_pcpu)); | |
12607 | spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu)); | |
12608 | } | |
bf9f6ac8 FW |
12609 | |
12610 | do { | |
12611 | old.control = new.control = pi_desc->control; | |
12612 | ||
bf9f6ac8 FW |
12613 | WARN((pi_desc->sn == 1), |
12614 | "Warning: SN field of posted-interrupts " | |
12615 | "is set before blocking\n"); | |
12616 | ||
12617 | /* | |
12618 | * Since vCPU can be preempted during this process, | |
12619 | * vcpu->cpu could be different with pre_pcpu, we | |
12620 | * need to set pre_pcpu as the destination of wakeup | |
12621 | * notification event, then we can find the right vCPU | |
12622 | * to wakeup in wakeup handler if interrupts happen | |
12623 | * when the vCPU is in blocked state. | |
12624 | */ | |
12625 | dest = cpu_physical_id(vcpu->pre_pcpu); | |
12626 | ||
12627 | if (x2apic_enabled()) | |
12628 | new.ndst = dest; | |
12629 | else | |
12630 | new.ndst = (dest << 8) & 0xFF00; | |
12631 | ||
12632 | /* set 'NV' to 'wakeup vector' */ | |
12633 | new.nv = POSTED_INTR_WAKEUP_VECTOR; | |
c0a1666b PB |
12634 | } while (cmpxchg64(&pi_desc->control, old.control, |
12635 | new.control) != old.control); | |
bf9f6ac8 | 12636 | |
8b306e2f PB |
12637 | /* We should not block the vCPU if an interrupt is posted for it. */ |
12638 | if (pi_test_on(pi_desc) == 1) | |
12639 | __pi_post_block(vcpu); | |
12640 | ||
12641 | local_irq_enable(); | |
12642 | return (vcpu->pre_pcpu == -1); | |
bf9f6ac8 FW |
12643 | } |
12644 | ||
bc22512b YJ |
12645 | static int vmx_pre_block(struct kvm_vcpu *vcpu) |
12646 | { | |
12647 | if (pi_pre_block(vcpu)) | |
12648 | return 1; | |
12649 | ||
64672c95 YJ |
12650 | if (kvm_lapic_hv_timer_in_use(vcpu)) |
12651 | kvm_lapic_switch_to_sw_timer(vcpu); | |
12652 | ||
bc22512b YJ |
12653 | return 0; |
12654 | } | |
12655 | ||
12656 | static void pi_post_block(struct kvm_vcpu *vcpu) | |
bf9f6ac8 | 12657 | { |
8b306e2f | 12658 | if (vcpu->pre_pcpu == -1) |
bf9f6ac8 FW |
12659 | return; |
12660 | ||
8b306e2f PB |
12661 | WARN_ON(irqs_disabled()); |
12662 | local_irq_disable(); | |
cd39e117 | 12663 | __pi_post_block(vcpu); |
8b306e2f | 12664 | local_irq_enable(); |
bf9f6ac8 FW |
12665 | } |
12666 | ||
bc22512b YJ |
12667 | static void vmx_post_block(struct kvm_vcpu *vcpu) |
12668 | { | |
64672c95 YJ |
12669 | if (kvm_x86_ops->set_hv_timer) |
12670 | kvm_lapic_switch_to_hv_timer(vcpu); | |
12671 | ||
bc22512b YJ |
12672 | pi_post_block(vcpu); |
12673 | } | |
12674 | ||
efc64404 FW |
12675 | /* |
12676 | * vmx_update_pi_irte - set IRTE for Posted-Interrupts | |
12677 | * | |
12678 | * @kvm: kvm | |
12679 | * @host_irq: host irq of the interrupt | |
12680 | * @guest_irq: gsi of the interrupt | |
12681 | * @set: set or unset PI | |
12682 | * returns 0 on success, < 0 on failure | |
12683 | */ | |
12684 | static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq, | |
12685 | uint32_t guest_irq, bool set) | |
12686 | { | |
12687 | struct kvm_kernel_irq_routing_entry *e; | |
12688 | struct kvm_irq_routing_table *irq_rt; | |
12689 | struct kvm_lapic_irq irq; | |
12690 | struct kvm_vcpu *vcpu; | |
12691 | struct vcpu_data vcpu_info; | |
3a8b0677 | 12692 | int idx, ret = 0; |
efc64404 FW |
12693 | |
12694 | if (!kvm_arch_has_assigned_device(kvm) || | |
a0052191 YZ |
12695 | !irq_remapping_cap(IRQ_POSTING_CAP) || |
12696 | !kvm_vcpu_apicv_active(kvm->vcpus[0])) | |
efc64404 FW |
12697 | return 0; |
12698 | ||
12699 | idx = srcu_read_lock(&kvm->irq_srcu); | |
12700 | irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu); | |
3a8b0677 JS |
12701 | if (guest_irq >= irq_rt->nr_rt_entries || |
12702 | hlist_empty(&irq_rt->map[guest_irq])) { | |
12703 | pr_warn_once("no route for guest_irq %u/%u (broken user space?)\n", | |
12704 | guest_irq, irq_rt->nr_rt_entries); | |
12705 | goto out; | |
12706 | } | |
efc64404 FW |
12707 | |
12708 | hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) { | |
12709 | if (e->type != KVM_IRQ_ROUTING_MSI) | |
12710 | continue; | |
12711 | /* | |
12712 | * VT-d PI cannot support posting multicast/broadcast | |
12713 | * interrupts to a vCPU, we still use interrupt remapping | |
12714 | * for these kind of interrupts. | |
12715 | * | |
12716 | * For lowest-priority interrupts, we only support | |
12717 | * those with single CPU as the destination, e.g. user | |
12718 | * configures the interrupts via /proc/irq or uses | |
12719 | * irqbalance to make the interrupts single-CPU. | |
12720 | * | |
12721 | * We will support full lowest-priority interrupt later. | |
12722 | */ | |
12723 | ||
37131313 | 12724 | kvm_set_msi_irq(kvm, e, &irq); |
23a1c257 FW |
12725 | if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) { |
12726 | /* | |
12727 | * Make sure the IRTE is in remapped mode if | |
12728 | * we don't handle it in posted mode. | |
12729 | */ | |
12730 | ret = irq_set_vcpu_affinity(host_irq, NULL); | |
12731 | if (ret < 0) { | |
12732 | printk(KERN_INFO | |
12733 | "failed to back to remapped mode, irq: %u\n", | |
12734 | host_irq); | |
12735 | goto out; | |
12736 | } | |
12737 | ||
efc64404 | 12738 | continue; |
23a1c257 | 12739 | } |
efc64404 FW |
12740 | |
12741 | vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu)); | |
12742 | vcpu_info.vector = irq.vector; | |
12743 | ||
4edf01c6 | 12744 | trace_kvm_pi_irte_update(host_irq, vcpu->vcpu_id, e->gsi, |
efc64404 FW |
12745 | vcpu_info.vector, vcpu_info.pi_desc_addr, set); |
12746 | ||
12747 | if (set) | |
12748 | ret = irq_set_vcpu_affinity(host_irq, &vcpu_info); | |
dc91f2eb | 12749 | else |
efc64404 | 12750 | ret = irq_set_vcpu_affinity(host_irq, NULL); |
efc64404 FW |
12751 | |
12752 | if (ret < 0) { | |
12753 | printk(KERN_INFO "%s: failed to update PI IRTE\n", | |
12754 | __func__); | |
12755 | goto out; | |
12756 | } | |
12757 | } | |
12758 | ||
12759 | ret = 0; | |
12760 | out: | |
12761 | srcu_read_unlock(&kvm->irq_srcu, idx); | |
12762 | return ret; | |
12763 | } | |
12764 | ||
c45dcc71 AR |
12765 | static void vmx_setup_mce(struct kvm_vcpu *vcpu) |
12766 | { | |
12767 | if (vcpu->arch.mcg_cap & MCG_LMCE_P) | |
12768 | to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |= | |
12769 | FEATURE_CONTROL_LMCE; | |
12770 | else | |
12771 | to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &= | |
12772 | ~FEATURE_CONTROL_LMCE; | |
12773 | } | |
12774 | ||
72d7b374 LP |
12775 | static int vmx_smi_allowed(struct kvm_vcpu *vcpu) |
12776 | { | |
72e9cbdb LP |
12777 | /* we need a nested vmexit to enter SMM, postpone if run is pending */ |
12778 | if (to_vmx(vcpu)->nested.nested_run_pending) | |
12779 | return 0; | |
72d7b374 LP |
12780 | return 1; |
12781 | } | |
12782 | ||
0234bf88 LP |
12783 | static int vmx_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate) |
12784 | { | |
72e9cbdb LP |
12785 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
12786 | ||
12787 | vmx->nested.smm.guest_mode = is_guest_mode(vcpu); | |
12788 | if (vmx->nested.smm.guest_mode) | |
12789 | nested_vmx_vmexit(vcpu, -1, 0, 0); | |
12790 | ||
12791 | vmx->nested.smm.vmxon = vmx->nested.vmxon; | |
12792 | vmx->nested.vmxon = false; | |
0234bf88 LP |
12793 | return 0; |
12794 | } | |
12795 | ||
12796 | static int vmx_pre_leave_smm(struct kvm_vcpu *vcpu, u64 smbase) | |
12797 | { | |
72e9cbdb LP |
12798 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
12799 | int ret; | |
12800 | ||
12801 | if (vmx->nested.smm.vmxon) { | |
12802 | vmx->nested.vmxon = true; | |
12803 | vmx->nested.smm.vmxon = false; | |
12804 | } | |
12805 | ||
12806 | if (vmx->nested.smm.guest_mode) { | |
12807 | vcpu->arch.hflags &= ~HF_SMM_MASK; | |
12808 | ret = enter_vmx_non_root_mode(vcpu, false); | |
12809 | vcpu->arch.hflags |= HF_SMM_MASK; | |
12810 | if (ret) | |
12811 | return ret; | |
12812 | ||
12813 | vmx->nested.smm.guest_mode = false; | |
12814 | } | |
0234bf88 LP |
12815 | return 0; |
12816 | } | |
12817 | ||
cc3d967f LP |
12818 | static int enable_smi_window(struct kvm_vcpu *vcpu) |
12819 | { | |
12820 | return 0; | |
12821 | } | |
12822 | ||
404f6aac | 12823 | static struct kvm_x86_ops vmx_x86_ops __ro_after_init = { |
6aa8b732 AK |
12824 | .cpu_has_kvm_support = cpu_has_kvm_support, |
12825 | .disabled_by_bios = vmx_disabled_by_bios, | |
12826 | .hardware_setup = hardware_setup, | |
12827 | .hardware_unsetup = hardware_unsetup, | |
002c7f7c | 12828 | .check_processor_compatibility = vmx_check_processor_compat, |
6aa8b732 AK |
12829 | .hardware_enable = hardware_enable, |
12830 | .hardware_disable = hardware_disable, | |
04547156 | 12831 | .cpu_has_accelerated_tpr = report_flexpriority, |
4d5c8a07 | 12832 | .has_emulated_msr = vmx_has_emulated_msr, |
6aa8b732 | 12833 | |
275b72a9 KRW |
12834 | .vm_init = vmx_vm_init, |
12835 | ||
6aa8b732 AK |
12836 | .vcpu_create = vmx_create_vcpu, |
12837 | .vcpu_free = vmx_free_vcpu, | |
04d2cc77 | 12838 | .vcpu_reset = vmx_vcpu_reset, |
6aa8b732 | 12839 | |
04d2cc77 | 12840 | .prepare_guest_switch = vmx_save_host_state, |
6aa8b732 AK |
12841 | .vcpu_load = vmx_vcpu_load, |
12842 | .vcpu_put = vmx_vcpu_put, | |
12843 | ||
a96036b8 | 12844 | .update_bp_intercept = update_exception_bitmap, |
ab1bebf8 | 12845 | .get_msr_feature = vmx_get_msr_feature, |
6aa8b732 AK |
12846 | .get_msr = vmx_get_msr, |
12847 | .set_msr = vmx_set_msr, | |
12848 | .get_segment_base = vmx_get_segment_base, | |
12849 | .get_segment = vmx_get_segment, | |
12850 | .set_segment = vmx_set_segment, | |
2e4d2653 | 12851 | .get_cpl = vmx_get_cpl, |
6aa8b732 | 12852 | .get_cs_db_l_bits = vmx_get_cs_db_l_bits, |
e8467fda | 12853 | .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits, |
aff48baa | 12854 | .decache_cr3 = vmx_decache_cr3, |
25c4c276 | 12855 | .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits, |
6aa8b732 | 12856 | .set_cr0 = vmx_set_cr0, |
6aa8b732 AK |
12857 | .set_cr3 = vmx_set_cr3, |
12858 | .set_cr4 = vmx_set_cr4, | |
6aa8b732 | 12859 | .set_efer = vmx_set_efer, |
6aa8b732 AK |
12860 | .get_idt = vmx_get_idt, |
12861 | .set_idt = vmx_set_idt, | |
12862 | .get_gdt = vmx_get_gdt, | |
12863 | .set_gdt = vmx_set_gdt, | |
73aaf249 JK |
12864 | .get_dr6 = vmx_get_dr6, |
12865 | .set_dr6 = vmx_set_dr6, | |
020df079 | 12866 | .set_dr7 = vmx_set_dr7, |
81908bf4 | 12867 | .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs, |
5fdbf976 | 12868 | .cache_reg = vmx_cache_reg, |
6aa8b732 AK |
12869 | .get_rflags = vmx_get_rflags, |
12870 | .set_rflags = vmx_set_rflags, | |
be94f6b7 | 12871 | |
6aa8b732 | 12872 | .tlb_flush = vmx_flush_tlb, |
6aa8b732 | 12873 | |
6aa8b732 | 12874 | .run = vmx_vcpu_run, |
6062d012 | 12875 | .handle_exit = vmx_handle_exit, |
6aa8b732 | 12876 | .skip_emulated_instruction = skip_emulated_instruction, |
2809f5d2 GC |
12877 | .set_interrupt_shadow = vmx_set_interrupt_shadow, |
12878 | .get_interrupt_shadow = vmx_get_interrupt_shadow, | |
102d8325 | 12879 | .patch_hypercall = vmx_patch_hypercall, |
2a8067f1 | 12880 | .set_irq = vmx_inject_irq, |
95ba8273 | 12881 | .set_nmi = vmx_inject_nmi, |
298101da | 12882 | .queue_exception = vmx_queue_exception, |
b463a6f7 | 12883 | .cancel_injection = vmx_cancel_injection, |
78646121 | 12884 | .interrupt_allowed = vmx_interrupt_allowed, |
95ba8273 | 12885 | .nmi_allowed = vmx_nmi_allowed, |
3cfc3092 JK |
12886 | .get_nmi_mask = vmx_get_nmi_mask, |
12887 | .set_nmi_mask = vmx_set_nmi_mask, | |
95ba8273 GN |
12888 | .enable_nmi_window = enable_nmi_window, |
12889 | .enable_irq_window = enable_irq_window, | |
12890 | .update_cr8_intercept = update_cr8_intercept, | |
d3f4c0a5 | 12891 | .set_virtual_apic_mode = vmx_set_virtual_apic_mode, |
38b99173 | 12892 | .set_apic_access_page_addr = vmx_set_apic_access_page_addr, |
d62caabb AS |
12893 | .get_enable_apicv = vmx_get_enable_apicv, |
12894 | .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl, | |
c7c9c56c | 12895 | .load_eoi_exitmap = vmx_load_eoi_exitmap, |
967235d3 | 12896 | .apicv_post_state_restore = vmx_apicv_post_state_restore, |
c7c9c56c YZ |
12897 | .hwapic_irr_update = vmx_hwapic_irr_update, |
12898 | .hwapic_isr_update = vmx_hwapic_isr_update, | |
a20ed54d YZ |
12899 | .sync_pir_to_irr = vmx_sync_pir_to_irr, |
12900 | .deliver_posted_interrupt = vmx_deliver_posted_interrupt, | |
050ee5a5 | 12901 | .dy_apicv_has_pending_interrupt = vmx_dy_apicv_has_pending_interrupt, |
95ba8273 | 12902 | |
cbc94022 | 12903 | .set_tss_addr = vmx_set_tss_addr, |
67253af5 | 12904 | .get_tdp_level = get_ept_level, |
4b12f0de | 12905 | .get_mt_mask = vmx_get_mt_mask, |
229456fc | 12906 | |
586f9607 | 12907 | .get_exit_info = vmx_get_exit_info, |
586f9607 | 12908 | |
17cc3935 | 12909 | .get_lpage_level = vmx_get_lpage_level, |
0e851880 SY |
12910 | |
12911 | .cpuid_update = vmx_cpuid_update, | |
4e47c7a6 SY |
12912 | |
12913 | .rdtscp_supported = vmx_rdtscp_supported, | |
ad756a16 | 12914 | .invpcid_supported = vmx_invpcid_supported, |
d4330ef2 JR |
12915 | |
12916 | .set_supported_cpuid = vmx_set_supported_cpuid, | |
f5f48ee1 SY |
12917 | |
12918 | .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit, | |
99e3e30a | 12919 | |
f7f5542f | 12920 | .read_l1_tsc_offset = vmx_read_l1_tsc_offset, |
7cb0f5cc | 12921 | .write_l1_tsc_offset = vmx_write_l1_tsc_offset, |
1c97f0a0 JR |
12922 | |
12923 | .set_tdp_cr3 = vmx_set_cr3, | |
8a76d7f2 JR |
12924 | |
12925 | .check_intercept = vmx_check_intercept, | |
a547c6db | 12926 | .handle_external_intr = vmx_handle_external_intr, |
da8999d3 | 12927 | .mpx_supported = vmx_mpx_supported, |
55412b2e | 12928 | .xsaves_supported = vmx_xsaves_supported, |
b6b8a145 JK |
12929 | |
12930 | .check_nested_events = vmx_check_nested_events, | |
ae97a3b8 RK |
12931 | |
12932 | .sched_in = vmx_sched_in, | |
843e4330 KH |
12933 | |
12934 | .slot_enable_log_dirty = vmx_slot_enable_log_dirty, | |
12935 | .slot_disable_log_dirty = vmx_slot_disable_log_dirty, | |
12936 | .flush_log_dirty = vmx_flush_log_dirty, | |
12937 | .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked, | |
c5f983f6 | 12938 | .write_log_dirty = vmx_write_pml_buffer, |
25462f7f | 12939 | |
bf9f6ac8 FW |
12940 | .pre_block = vmx_pre_block, |
12941 | .post_block = vmx_post_block, | |
12942 | ||
25462f7f | 12943 | .pmu_ops = &intel_pmu_ops, |
efc64404 FW |
12944 | |
12945 | .update_pi_irte = vmx_update_pi_irte, | |
64672c95 YJ |
12946 | |
12947 | #ifdef CONFIG_X86_64 | |
12948 | .set_hv_timer = vmx_set_hv_timer, | |
12949 | .cancel_hv_timer = vmx_cancel_hv_timer, | |
12950 | #endif | |
c45dcc71 AR |
12951 | |
12952 | .setup_mce = vmx_setup_mce, | |
0234bf88 | 12953 | |
72d7b374 | 12954 | .smi_allowed = vmx_smi_allowed, |
0234bf88 LP |
12955 | .pre_enter_smm = vmx_pre_enter_smm, |
12956 | .pre_leave_smm = vmx_pre_leave_smm, | |
cc3d967f | 12957 | .enable_smi_window = enable_smi_window, |
6aa8b732 AK |
12958 | }; |
12959 | ||
b9cfedcd | 12960 | static void vmx_cleanup_l1d_flush(void) |
d665f9fc PB |
12961 | { |
12962 | if (vmx_l1d_flush_pages) { | |
12963 | free_pages((unsigned long)vmx_l1d_flush_pages, L1D_CACHE_ORDER); | |
12964 | vmx_l1d_flush_pages = NULL; | |
12965 | } | |
b9cfedcd TG |
12966 | /* Restore state so sysfs ignores VMX */ |
12967 | l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO; | |
1749555e KRW |
12968 | } |
12969 | ||
1ead4979 TG |
12970 | static void vmx_exit(void) |
12971 | { | |
12972 | #ifdef CONFIG_KEXEC_CORE | |
12973 | RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL); | |
12974 | synchronize_rcu(); | |
12975 | #endif | |
12976 | ||
12977 | kvm_exit(); | |
12978 | ||
12979 | vmx_cleanup_l1d_flush(); | |
12980 | } | |
12981 | module_exit(vmx_exit) | |
12982 | ||
6aa8b732 AK |
12983 | static int __init vmx_init(void) |
12984 | { | |
1749555e KRW |
12985 | int r; |
12986 | ||
1ead4979 TG |
12987 | r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), |
12988 | __alignof__(struct vcpu_vmx), THIS_MODULE); | |
d665f9fc PB |
12989 | if (r) |
12990 | return r; | |
1749555e | 12991 | |
1ead4979 | 12992 | /* |
2bcd5b01 TG |
12993 | * Must be called after kvm_init() so enable_ept is properly set |
12994 | * up. Hand the parameter mitigation value in which was stored in | |
12995 | * the pre module init parser. If no parameter was given, it will | |
12996 | * contain 'auto' which will be turned into the default 'cond' | |
12997 | * mitigation mode. | |
1ead4979 | 12998 | */ |
2bcd5b01 TG |
12999 | if (boot_cpu_has(X86_BUG_L1TF)) { |
13000 | r = vmx_setup_l1d_flush(vmentry_l1d_flush_param); | |
13001 | if (r) { | |
13002 | vmx_exit(); | |
13003 | return r; | |
13004 | } | |
d665f9fc | 13005 | } |
25c5f225 | 13006 | |
2965faa5 | 13007 | #ifdef CONFIG_KEXEC_CORE |
8f536b76 ZY |
13008 | rcu_assign_pointer(crash_vmclear_loaded_vmcss, |
13009 | crash_vmclear_local_loaded_vmcss); | |
13010 | #endif | |
13011 | ||
fdef3ad1 | 13012 | return 0; |
6aa8b732 | 13013 | } |
6aa8b732 | 13014 | module_init(vmx_init) |