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KVM: x86 emulator: emulate SGDT/SIDT
[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
9611c187 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
00b27a3e 21#include "cpuid.h"
e495606d 22
edf88417 23#include <linux/kvm_host.h>
6aa8b732 24#include <linux/module.h>
9d8f549d 25#include <linux/kernel.h>
6aa8b732
AK		 26#include <linux/mm.h>
27#include <linux/highmem.h>
e8edc6e0 28#include <linux/sched.h>
c7addb90 29#include <linux/moduleparam.h>
e9bda3b3 30#include <linux/mod_devicetable.h>
229456fc 31#include <linux/ftrace_event.h>
5a0e3ad6 32#include <linux/slab.h>
cafd6659 33#include <linux/tboot.h>
5fdbf976 34#include "kvm_cache_regs.h"
35920a35 35#include "x86.h"
e495606d 36
6aa8b732 37#include <asm/io.h>
3b3be0d1 38#include <asm/desc.h>
13673a90 39#include <asm/vmx.h>
6210e37b 40#include <asm/virtext.h>
a0861c02 41#include <asm/mce.h>
2acf923e
DC		 42#include <asm/i387.h>
43#include <asm/xcr.h>
d7cd9796 44#include <asm/perf_event.h>
6aa8b732 45
229456fc
MT		 46#include "trace.h"
47
4ecac3fd 48#define __ex(x) __kvm_handle_fault_on_reboot(x)
5e520e62
AK		 49#define __ex_clear(x, reg) \
50 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
4ecac3fd 51
6aa8b732
AK		 52MODULE_AUTHOR("Qumranet");
53MODULE_LICENSE("GPL");
54
e9bda3b3
JT		 55static const struct x86_cpu_id vmx_cpu_id[] = {
56 X86_FEATURE_MATCH(X86_FEATURE_VMX),
57 {}
58};
59MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
60
476bc001 61static bool __read_mostly enable_vpid = 1;
736caefe 62module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 63
476bc001 64static bool __read_mostly flexpriority_enabled = 1;
736caefe 65module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 66
476bc001 67static bool __read_mostly enable_ept = 1;
736caefe 68module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 69
476bc001 70static bool __read_mostly enable_unrestricted_guest = 1;
3a624e29
NK		 71module_param_named(unrestricted_guest,
72 enable_unrestricted_guest, bool, S_IRUGO);
73
83c3a331
XH		 74static bool __read_mostly enable_ept_ad_bits = 1;
75module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
76
476bc001 77static bool __read_mostly emulate_invalid_guest_state = 0;
c1f8bc04 78module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 79
476bc001 80static bool __read_mostly vmm_exclusive = 1;
b923e62e
DX		 81module_param(vmm_exclusive, bool, S_IRUGO);
82
476bc001 83static bool __read_mostly fasteoi = 1;
58fbbf26
KT		 84module_param(fasteoi, bool, S_IRUGO);
85
801d3424
NHE		 86/*
87 * If nested=1, nested virtualization is supported, i.e., guests may use
88 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
89 * use VMX instructions.
90 */
476bc001 91static bool __read_mostly nested = 0;
801d3424
NHE		 92module_param(nested, bool, S_IRUGO);
93
cdc0e244
AK		 94#define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST \
95 (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
96#define KVM_GUEST_CR0_MASK \
97 (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
98#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST \
81231c69 99 (X86_CR0_WP | X86_CR0_NE)
cdc0e244
AK		 100#define KVM_VM_CR0_ALWAYS_ON \
101 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 102#define KVM_CR4_GUEST_OWNED_BITS \
103 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
104 | X86_CR4_OSXMMEXCPT)
105
cdc0e244
AK		 106#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
107#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
108
78ac8b47
AK		 109#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
110
4b8d54f9
ZE		 111/*
112 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
113 * ple_gap: upper bound on the amount of time between two successive
114 * executions of PAUSE in a loop. Also indicate if ple enabled.
00c25bce 115 * According to test, this time is usually smaller than 128 cycles.
4b8d54f9
ZE		 116 * ple_window: upper bound on the amount of time a guest is allowed to execute
117 * in a PAUSE loop. Tests indicate that most spinlocks are held for
118 * less than 2^12 cycles
119 * Time is measured based on a counter that runs at the same rate as the TSC,
120 * refer SDM volume 3b section 21.6.13 & 22.1.3.
121 */
00c25bce 122#define KVM_VMX_DEFAULT_PLE_GAP 128
4b8d54f9
ZE		 123#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
124static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
125module_param(ple_gap, int, S_IRUGO);
126
127static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
128module_param(ple_window, int, S_IRUGO);
129
8bf00a52 130#define NR_AUTOLOAD_MSRS 8
ff2f6fe9 131#define VMCS02_POOL_SIZE 1
61d2ef2c 132
a2fa3e9f
GH		 133struct vmcs {
134 u32 revision_id;
135 u32 abort;
136 char data[0];
137};
138
d462b819
NHE		 139/*
140 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
141 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
142 * loaded on this CPU (so we can clear them if the CPU goes down).
143 */
144struct loaded_vmcs {
145 struct vmcs *vmcs;
146 int cpu;
147 int launched;
148 struct list_head loaded_vmcss_on_cpu_link;
149};
150
26bb0981
AK		 151struct shared_msr_entry {
152 unsigned index;
153 u64 data;
d5696725 154 u64 mask;
26bb0981
AK		 155};
156
a9d30f33
NHE		 157/*
158 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
159 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
160 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
161 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
162 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
163 * More than one of these structures may exist, if L1 runs multiple L2 guests.
164 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
165 * underlying hardware which will be used to run L2.
166 * This structure is packed to ensure that its layout is identical across
167 * machines (necessary for live migration).
168 * If there are changes in this struct, VMCS12_REVISION must be changed.
169 */
22bd0358 170typedef u64 natural_width;
a9d30f33
NHE		 171struct __packed vmcs12 {
172 /* According to the Intel spec, a VMCS region must start with the
173 * following two fields. Then follow implementation-specific data.
174 */
175 u32 revision_id;
176 u32 abort;
22bd0358 177
27d6c865
NHE		 178 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
179 u32 padding[7]; /* room for future expansion */
180
22bd0358
NHE		 181 u64 io_bitmap_a;
182 u64 io_bitmap_b;
183 u64 msr_bitmap;
184 u64 vm_exit_msr_store_addr;
185 u64 vm_exit_msr_load_addr;
186 u64 vm_entry_msr_load_addr;
187 u64 tsc_offset;
188 u64 virtual_apic_page_addr;
189 u64 apic_access_addr;
190 u64 ept_pointer;
191 u64 guest_physical_address;
192 u64 vmcs_link_pointer;
193 u64 guest_ia32_debugctl;
194 u64 guest_ia32_pat;
195 u64 guest_ia32_efer;
196 u64 guest_ia32_perf_global_ctrl;
197 u64 guest_pdptr0;
198 u64 guest_pdptr1;
199 u64 guest_pdptr2;
200 u64 guest_pdptr3;
201 u64 host_ia32_pat;
202 u64 host_ia32_efer;
203 u64 host_ia32_perf_global_ctrl;
204 u64 padding64[8]; /* room for future expansion */
205 /*
206 * To allow migration of L1 (complete with its L2 guests) between
207 * machines of different natural widths (32 or 64 bit), we cannot have
208 * unsigned long fields with no explict size. We use u64 (aliased
209 * natural_width) instead. Luckily, x86 is little-endian.
210 */
211 natural_width cr0_guest_host_mask;
212 natural_width cr4_guest_host_mask;
213 natural_width cr0_read_shadow;
214 natural_width cr4_read_shadow;
215 natural_width cr3_target_value0;
216 natural_width cr3_target_value1;
217 natural_width cr3_target_value2;
218 natural_width cr3_target_value3;
219 natural_width exit_qualification;
220 natural_width guest_linear_address;
221 natural_width guest_cr0;
222 natural_width guest_cr3;
223 natural_width guest_cr4;
224 natural_width guest_es_base;
225 natural_width guest_cs_base;
226 natural_width guest_ss_base;
227 natural_width guest_ds_base;
228 natural_width guest_fs_base;
229 natural_width guest_gs_base;
230 natural_width guest_ldtr_base;
231 natural_width guest_tr_base;
232 natural_width guest_gdtr_base;
233 natural_width guest_idtr_base;
234 natural_width guest_dr7;
235 natural_width guest_rsp;
236 natural_width guest_rip;
237 natural_width guest_rflags;
238 natural_width guest_pending_dbg_exceptions;
239 natural_width guest_sysenter_esp;
240 natural_width guest_sysenter_eip;
241 natural_width host_cr0;
242 natural_width host_cr3;
243 natural_width host_cr4;
244 natural_width host_fs_base;
245 natural_width host_gs_base;
246 natural_width host_tr_base;
247 natural_width host_gdtr_base;
248 natural_width host_idtr_base;
249 natural_width host_ia32_sysenter_esp;
250 natural_width host_ia32_sysenter_eip;
251 natural_width host_rsp;
252 natural_width host_rip;
253 natural_width paddingl[8]; /* room for future expansion */
254 u32 pin_based_vm_exec_control;
255 u32 cpu_based_vm_exec_control;
256 u32 exception_bitmap;
257 u32 page_fault_error_code_mask;
258 u32 page_fault_error_code_match;
259 u32 cr3_target_count;
260 u32 vm_exit_controls;
261 u32 vm_exit_msr_store_count;
262 u32 vm_exit_msr_load_count;
263 u32 vm_entry_controls;
264 u32 vm_entry_msr_load_count;
265 u32 vm_entry_intr_info_field;
266 u32 vm_entry_exception_error_code;
267 u32 vm_entry_instruction_len;
268 u32 tpr_threshold;
269 u32 secondary_vm_exec_control;
270 u32 vm_instruction_error;
271 u32 vm_exit_reason;
272 u32 vm_exit_intr_info;
273 u32 vm_exit_intr_error_code;
274 u32 idt_vectoring_info_field;
275 u32 idt_vectoring_error_code;
276 u32 vm_exit_instruction_len;
277 u32 vmx_instruction_info;
278 u32 guest_es_limit;
279 u32 guest_cs_limit;
280 u32 guest_ss_limit;
281 u32 guest_ds_limit;
282 u32 guest_fs_limit;
283 u32 guest_gs_limit;
284 u32 guest_ldtr_limit;
285 u32 guest_tr_limit;
286 u32 guest_gdtr_limit;
287 u32 guest_idtr_limit;
288 u32 guest_es_ar_bytes;
289 u32 guest_cs_ar_bytes;
290 u32 guest_ss_ar_bytes;
291 u32 guest_ds_ar_bytes;
292 u32 guest_fs_ar_bytes;
293 u32 guest_gs_ar_bytes;
294 u32 guest_ldtr_ar_bytes;
295 u32 guest_tr_ar_bytes;
296 u32 guest_interruptibility_info;
297 u32 guest_activity_state;
298 u32 guest_sysenter_cs;
299 u32 host_ia32_sysenter_cs;
300 u32 padding32[8]; /* room for future expansion */
301 u16 virtual_processor_id;
302 u16 guest_es_selector;
303 u16 guest_cs_selector;
304 u16 guest_ss_selector;
305 u16 guest_ds_selector;
306 u16 guest_fs_selector;
307 u16 guest_gs_selector;
308 u16 guest_ldtr_selector;
309 u16 guest_tr_selector;
310 u16 host_es_selector;
311 u16 host_cs_selector;
312 u16 host_ss_selector;
313 u16 host_ds_selector;
314 u16 host_fs_selector;
315 u16 host_gs_selector;
316 u16 host_tr_selector;
a9d30f33
NHE		 317};
318
319/*
320 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
321 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
322 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
323 */
324#define VMCS12_REVISION 0x11e57ed0
325
326/*
327 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
328 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
329 * current implementation, 4K are reserved to avoid future complications.
330 */
331#define VMCS12_SIZE 0x1000
332
ff2f6fe9
NHE		 333/* Used to remember the last vmcs02 used for some recently used vmcs12s */
334struct vmcs02_list {
335 struct list_head list;
336 gpa_t vmptr;
337 struct loaded_vmcs vmcs02;
338};
339
ec378aee
NHE		 340/*
341 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
342 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
343 */
344struct nested_vmx {
345 /* Has the level1 guest done vmxon? */
346 bool vmxon;
a9d30f33
NHE		 347
348 /* The guest-physical address of the current VMCS L1 keeps for L2 */
349 gpa_t current_vmptr;
350 /* The host-usable pointer to the above */
351 struct page *current_vmcs12_page;
352 struct vmcs12 *current_vmcs12;
ff2f6fe9
NHE		 353
354 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
355 struct list_head vmcs02_pool;
356 int vmcs02_num;
fe3ef05c 357 u64 vmcs01_tsc_offset;
644d711a
NHE		 358 /* L2 must run next, and mustn't decide to exit to L1. */
359 bool nested_run_pending;
fe3ef05c
NHE		 360 /*
361 * Guest pages referred to in vmcs02 with host-physical pointers, so
362 * we must keep them pinned while L2 runs.
363 */
364 struct page *apic_access_page;
ec378aee
NHE		 365};
366
a2fa3e9f 367struct vcpu_vmx {
fb3f0f51 368 struct kvm_vcpu vcpu;
313dbd49 369 unsigned long host_rsp;
29bd8a78 370 u8 fail;
69c73028 371 u8 cpl;
9d58b931 372 bool nmi_known_unmasked;
51aa01d1 373 u32 exit_intr_info;
1155f76a 374 u32 idt_vectoring_info;
6de12732 375 ulong rflags;
26bb0981 376 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH		 377 int nmsrs;
378 int save_nmsrs;
a2fa3e9f 379#ifdef CONFIG_X86_64
44ea2b17
AK		 380 u64 msr_host_kernel_gs_base;
381 u64 msr_guest_kernel_gs_base;
a2fa3e9f 382#endif
d462b819
NHE		 383 /*
384 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
385 * non-nested (L1) guest, it always points to vmcs01. For a nested
386 * guest (L2), it points to a different VMCS.
387 */
388 struct loaded_vmcs vmcs01;
389 struct loaded_vmcs *loaded_vmcs;
390 bool __launched; /* temporary, used in vmx_vcpu_run */
61d2ef2c
AK		 391 struct msr_autoload {
392 unsigned nr;
393 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
394 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
395 } msr_autoload;
a2fa3e9f
GH		 396 struct {
397 int loaded;
398 u16 fs_sel, gs_sel, ldt_sel;
b2da15ac
AK		 399#ifdef CONFIG_X86_64
400 u16 ds_sel, es_sel;
401#endif
152d3f2f
LV		 402 int gs_ldt_reload_needed;
403 int fs_reload_needed;
d77c26fc 404 } host_state;
9c8cba37 405 struct {
7ffd92c5 406 int vm86_active;
78ac8b47 407 ulong save_rflags;
7ffd92c5
AK		 408 struct kvm_save_segment {
409 u16 selector;
410 unsigned long base;
411 u32 limit;
412 u32 ar;
413 } tr, es, ds, fs, gs;
9c8cba37 414 } rmode;
2fb92db1
AK		 415 struct {
416 u32 bitmask; /* 4 bits per segment (1 bit per field) */
417 struct kvm_save_segment seg[8];
418 } segment_cache;
2384d2b3 419 int vpid;
04fa4d32 420 bool emulation_required;
3b86cd99
JK		 421
422 /* Support for vnmi-less CPUs */
423 int soft_vnmi_blocked;
424 ktime_t entry_time;
425 s64 vnmi_blocked_time;
a0861c02 426 u32 exit_reason;
4e47c7a6
SY		 427
428 bool rdtscp_enabled;
ec378aee
NHE		 429
430 /* Support for a guest hypervisor (nested VMX) */
431 struct nested_vmx nested;
a2fa3e9f
GH		 432};
433
2fb92db1
AK		 434enum segment_cache_field {
435 SEG_FIELD_SEL = 0,
436 SEG_FIELD_BASE = 1,
437 SEG_FIELD_LIMIT = 2,
438 SEG_FIELD_AR = 3,
439
440 SEG_FIELD_NR = 4
441};
442
a2fa3e9f
GH		 443static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
444{
fb3f0f51 445 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 446}
447
22bd0358
NHE		 448#define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
449#define FIELD(number, name) [number] = VMCS12_OFFSET(name)
450#define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
451 [number##_HIGH] = VMCS12_OFFSET(name)+4
452
453static unsigned short vmcs_field_to_offset_table[] = {
454 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
455 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
456 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
457 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
458 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
459 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
460 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
461 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
462 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
463 FIELD(HOST_ES_SELECTOR, host_es_selector),
464 FIELD(HOST_CS_SELECTOR, host_cs_selector),
465 FIELD(HOST_SS_SELECTOR, host_ss_selector),
466 FIELD(HOST_DS_SELECTOR, host_ds_selector),
467 FIELD(HOST_FS_SELECTOR, host_fs_selector),
468 FIELD(HOST_GS_SELECTOR, host_gs_selector),
469 FIELD(HOST_TR_SELECTOR, host_tr_selector),
470 FIELD64(IO_BITMAP_A, io_bitmap_a),
471 FIELD64(IO_BITMAP_B, io_bitmap_b),
472 FIELD64(MSR_BITMAP, msr_bitmap),
473 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
474 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
475 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
476 FIELD64(TSC_OFFSET, tsc_offset),
477 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
478 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
479 FIELD64(EPT_POINTER, ept_pointer),
480 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
481 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
482 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
483 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
484 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
485 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
486 FIELD64(GUEST_PDPTR0, guest_pdptr0),
487 FIELD64(GUEST_PDPTR1, guest_pdptr1),
488 FIELD64(GUEST_PDPTR2, guest_pdptr2),
489 FIELD64(GUEST_PDPTR3, guest_pdptr3),
490 FIELD64(HOST_IA32_PAT, host_ia32_pat),
491 FIELD64(HOST_IA32_EFER, host_ia32_efer),
492 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
493 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
494 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
495 FIELD(EXCEPTION_BITMAP, exception_bitmap),
496 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
497 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
498 FIELD(CR3_TARGET_COUNT, cr3_target_count),
499 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
500 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
501 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
502 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
503 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
504 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
505 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
506 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
507 FIELD(TPR_THRESHOLD, tpr_threshold),
508 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
509 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
510 FIELD(VM_EXIT_REASON, vm_exit_reason),
511 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
512 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
513 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
514 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
515 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
516 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
517 FIELD(GUEST_ES_LIMIT, guest_es_limit),
518 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
519 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
520 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
521 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
522 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
523 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
524 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
525 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
526 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
527 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
528 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
529 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
530 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
531 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
532 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
533 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
534 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
535 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
536 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
537 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
538 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
539 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
540 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
541 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
542 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
543 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
544 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
545 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
546 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
547 FIELD(EXIT_QUALIFICATION, exit_qualification),
548 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
549 FIELD(GUEST_CR0, guest_cr0),
550 FIELD(GUEST_CR3, guest_cr3),
551 FIELD(GUEST_CR4, guest_cr4),
552 FIELD(GUEST_ES_BASE, guest_es_base),
553 FIELD(GUEST_CS_BASE, guest_cs_base),
554 FIELD(GUEST_SS_BASE, guest_ss_base),
555 FIELD(GUEST_DS_BASE, guest_ds_base),
556 FIELD(GUEST_FS_BASE, guest_fs_base),
557 FIELD(GUEST_GS_BASE, guest_gs_base),
558 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
559 FIELD(GUEST_TR_BASE, guest_tr_base),
560 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
561 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
562 FIELD(GUEST_DR7, guest_dr7),
563 FIELD(GUEST_RSP, guest_rsp),
564 FIELD(GUEST_RIP, guest_rip),
565 FIELD(GUEST_RFLAGS, guest_rflags),
566 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
567 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
568 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
569 FIELD(HOST_CR0, host_cr0),
570 FIELD(HOST_CR3, host_cr3),
571 FIELD(HOST_CR4, host_cr4),
572 FIELD(HOST_FS_BASE, host_fs_base),
573 FIELD(HOST_GS_BASE, host_gs_base),
574 FIELD(HOST_TR_BASE, host_tr_base),
575 FIELD(HOST_GDTR_BASE, host_gdtr_base),
576 FIELD(HOST_IDTR_BASE, host_idtr_base),
577 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
578 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
579 FIELD(HOST_RSP, host_rsp),
580 FIELD(HOST_RIP, host_rip),
581};
582static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
583
584static inline short vmcs_field_to_offset(unsigned long field)
585{
586 if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
587 return -1;
588 return vmcs_field_to_offset_table[field];
589}
590
a9d30f33
NHE		 591static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
592{
593 return to_vmx(vcpu)->nested.current_vmcs12;
594}
595
596static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
597{
598 struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
599 if (is_error_page(page)) {
600 kvm_release_page_clean(page);
601 return NULL;
602 }
603 return page;
604}
605
606static void nested_release_page(struct page *page)
607{
608 kvm_release_page_dirty(page);
609}
610
611static void nested_release_page_clean(struct page *page)
612{
613 kvm_release_page_clean(page);
614}
615
4e1096d2 616static u64 construct_eptp(unsigned long root_hpa);
4610c9cc
DX		 617static void kvm_cpu_vmxon(u64 addr);
618static void kvm_cpu_vmxoff(void);
aff48baa 619static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
776e58ea 620static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
b246dd5d
OW		 621static void vmx_set_segment(struct kvm_vcpu *vcpu,
622 struct kvm_segment *var, int seg);
623static void vmx_get_segment(struct kvm_vcpu *vcpu,
624 struct kvm_segment *var, int seg);
75880a01 625
6aa8b732
AK		 626static DEFINE_PER_CPU(struct vmcs *, vmxarea);
627static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
d462b819
NHE		 628/*
629 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
630 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
631 */
632static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
3444d7da 633static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
6aa8b732 634
3e7c73e9
AK		 635static unsigned long *vmx_io_bitmap_a;
636static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 637static unsigned long *vmx_msr_bitmap_legacy;
638static unsigned long *vmx_msr_bitmap_longmode;
fdef3ad1 639
110312c8 640static bool cpu_has_load_ia32_efer;
8bf00a52 641static bool cpu_has_load_perf_global_ctrl;
110312c8 642
2384d2b3
SY		 643static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
644static DEFINE_SPINLOCK(vmx_vpid_lock);
645
1c3d14fe 646static struct vmcs_config {
6aa8b732
AK		 647 int size;
648 int order;
649 u32 revision_id;
1c3d14fe
YS		 650 u32 pin_based_exec_ctrl;
651 u32 cpu_based_exec_ctrl;
f78e0e2e 652 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 653 u32 vmexit_ctrl;
654 u32 vmentry_ctrl;
655} vmcs_config;
6aa8b732 656
efff9e53 657static struct vmx_capability {
d56f546d
SY		 658 u32 ept;
659 u32 vpid;
660} vmx_capability;
661
6aa8b732
AK		 662#define VMX_SEGMENT_FIELD(seg) \
663 [VCPU_SREG_##seg] = { \
664 .selector = GUEST_##seg##_SELECTOR, \
665 .base = GUEST_##seg##_BASE, \
666 .limit = GUEST_##seg##_LIMIT, \
667 .ar_bytes = GUEST_##seg##_AR_BYTES, \
668 }
669
670static struct kvm_vmx_segment_field {
671 unsigned selector;
672 unsigned base;
673 unsigned limit;
674 unsigned ar_bytes;
675} kvm_vmx_segment_fields[] = {
676 VMX_SEGMENT_FIELD(CS),
677 VMX_SEGMENT_FIELD(DS),
678 VMX_SEGMENT_FIELD(ES),
679 VMX_SEGMENT_FIELD(FS),
680 VMX_SEGMENT_FIELD(GS),
681 VMX_SEGMENT_FIELD(SS),
682 VMX_SEGMENT_FIELD(TR),
683 VMX_SEGMENT_FIELD(LDTR),
684};
685
26bb0981
AK		 686static u64 host_efer;
687
6de4f3ad
AK		 688static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
689
4d56c8a7 690/*
8c06585d 691 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
4d56c8a7
AK		 692 * away by decrementing the array size.
693 */
6aa8b732 694static const u32 vmx_msr_index[] = {
05b3e0c2 695#ifdef CONFIG_X86_64
44ea2b17 696 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 697#endif
8c06585d 698 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
6aa8b732 699};
9d8f549d 700#define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
6aa8b732 701
31299944 702static inline bool is_page_fault(u32 intr_info)
6aa8b732
AK		 703{
704 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
705 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 706 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 707}
708
31299944 709static inline bool is_no_device(u32 intr_info)
2ab455cc
AL		 710{
711 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
712 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 713 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 714}
715
31299944 716static inline bool is_invalid_opcode(u32 intr_info)
7aa81cc0
AL		 717{
718 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
719 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 720 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 721}
722
31299944 723static inline bool is_external_interrupt(u32 intr_info)
6aa8b732
AK		 724{
725 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
726 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
727}
728
31299944 729static inline bool is_machine_check(u32 intr_info)
a0861c02
AK		 730{
731 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
732 INTR_INFO_VALID_MASK)) ==
733 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
734}
735
31299944 736static inline bool cpu_has_vmx_msr_bitmap(void)
25c5f225 737{
04547156 738 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 739}
740
31299944 741static inline bool cpu_has_vmx_tpr_shadow(void)
6e5d865c 742{
04547156 743 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 744}
745
31299944 746static inline bool vm_need_tpr_shadow(struct kvm *kvm)
6e5d865c 747{
04547156 748 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
6e5d865c
YS		 749}
750
31299944 751static inline bool cpu_has_secondary_exec_ctrls(void)
f78e0e2e 752{
04547156
SY		 753 return vmcs_config.cpu_based_exec_ctrl &
754 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 755}
756
774ead3a 757static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 758{
04547156
SY		 759 return vmcs_config.cpu_based_2nd_exec_ctrl &
760 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
761}
762
763static inline bool cpu_has_vmx_flexpriority(void)
764{
765 return cpu_has_vmx_tpr_shadow() &&
766 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 767}
768
e799794e
MT		 769static inline bool cpu_has_vmx_ept_execute_only(void)
770{
31299944 771 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
e799794e
MT		 772}
773
774static inline bool cpu_has_vmx_eptp_uncacheable(void)
775{
31299944 776 return vmx_capability.ept & VMX_EPTP_UC_BIT;
e799794e
MT		 777}
778
779static inline bool cpu_has_vmx_eptp_writeback(void)
780{
31299944 781 return vmx_capability.ept & VMX_EPTP_WB_BIT;
e799794e
MT		 782}
783
784static inline bool cpu_has_vmx_ept_2m_page(void)
785{
31299944 786 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
e799794e
MT		 787}
788
878403b7
SY		 789static inline bool cpu_has_vmx_ept_1g_page(void)
790{
31299944 791 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
878403b7
SY		 792}
793
4bc9b982
SY		 794static inline bool cpu_has_vmx_ept_4levels(void)
795{
796 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
797}
798
83c3a331
XH		 799static inline bool cpu_has_vmx_ept_ad_bits(void)
800{
801 return vmx_capability.ept & VMX_EPT_AD_BIT;
802}
803
31299944 804static inline bool cpu_has_vmx_invept_individual_addr(void)
d56f546d 805{
31299944 806 return vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT;
d56f546d
SY		 807}
808
31299944 809static inline bool cpu_has_vmx_invept_context(void)
d56f546d 810{
31299944 811 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
d56f546d
SY		 812}
813
31299944 814static inline bool cpu_has_vmx_invept_global(void)
d56f546d 815{
31299944 816 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
d56f546d
SY		 817}
818
518c8aee
GJ		 819static inline bool cpu_has_vmx_invvpid_single(void)
820{
821 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
822}
823
b9d762fa
GJ		 824static inline bool cpu_has_vmx_invvpid_global(void)
825{
826 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
827}
828
31299944 829static inline bool cpu_has_vmx_ept(void)
d56f546d 830{
04547156
SY		 831 return vmcs_config.cpu_based_2nd_exec_ctrl &
832 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 833}
834
31299944 835static inline bool cpu_has_vmx_unrestricted_guest(void)
3a624e29
NK		 836{
837 return vmcs_config.cpu_based_2nd_exec_ctrl &
838 SECONDARY_EXEC_UNRESTRICTED_GUEST;
839}
840
31299944 841static inline bool cpu_has_vmx_ple(void)
4b8d54f9
ZE		 842{
843 return vmcs_config.cpu_based_2nd_exec_ctrl &
844 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
845}
846
31299944 847static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
f78e0e2e 848{
6d3e435e 849 return flexpriority_enabled && irqchip_in_kernel(kvm);
f78e0e2e
SY		 850}
851
31299944 852static inline bool cpu_has_vmx_vpid(void)
2384d2b3 853{
04547156
SY		 854 return vmcs_config.cpu_based_2nd_exec_ctrl &
855 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 856}
857
31299944 858static inline bool cpu_has_vmx_rdtscp(void)
4e47c7a6
SY		 859{
860 return vmcs_config.cpu_based_2nd_exec_ctrl &
861 SECONDARY_EXEC_RDTSCP;
862}
863
31299944 864static inline bool cpu_has_virtual_nmis(void)
f08864b4
SY		 865{
866 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
867}
868
f5f48ee1
SY		 869static inline bool cpu_has_vmx_wbinvd_exit(void)
870{
871 return vmcs_config.cpu_based_2nd_exec_ctrl &
872 SECONDARY_EXEC_WBINVD_EXITING;
873}
874
04547156
SY		 875static inline bool report_flexpriority(void)
876{
877 return flexpriority_enabled;
878}
879
fe3ef05c
NHE		 880static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
881{
882 return vmcs12->cpu_based_vm_exec_control & bit;
883}
884
885static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
886{
887 return (vmcs12->cpu_based_vm_exec_control &
888 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
889 (vmcs12->secondary_vm_exec_control & bit);
890}
891
644d711a
NHE		 892static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12,
893 struct kvm_vcpu *vcpu)
894{
895 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
896}
897
898static inline bool is_exception(u32 intr_info)
899{
900 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
901 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
902}
903
904static void nested_vmx_vmexit(struct kvm_vcpu *vcpu);
7c177938
NHE		 905static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
906 struct vmcs12 *vmcs12,
907 u32 reason, unsigned long qualification);
908
8b9cf98c 909static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 910{
911 int i;
912
a2fa3e9f 913 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 914 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 915 return i;
916 return -1;
917}
918
2384d2b3
SY		 919static inline void __invvpid(int ext, u16 vpid, gva_t gva)
920{
921 struct {
922 u64 vpid : 16;
923 u64 rsvd : 48;
924 u64 gva;
925 } operand = { vpid, 0, gva };
926
4ecac3fd 927 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 928 /* CF==1 or ZF==1 --> rc = -1 */
929 "; ja 1f ; ud2 ; 1:"
930 : : "a"(&operand), "c"(ext) : "cc", "memory");
931}
932
1439442c
SY		 933static inline void __invept(int ext, u64 eptp, gpa_t gpa)
934{
935 struct {
936 u64 eptp, gpa;
937 } operand = {eptp, gpa};
938
4ecac3fd 939 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 940 /* CF==1 or ZF==1 --> rc = -1 */
941 "; ja 1f ; ud2 ; 1:\n"
942 : : "a" (&operand), "c" (ext) : "cc", "memory");
943}
944
26bb0981 945static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 946{
947 int i;
948
8b9cf98c 949 i = __find_msr_index(vmx, msr);
a75beee6 950 if (i >= 0)
a2fa3e9f 951 return &vmx->guest_msrs[i];
8b6d44c7 952 return NULL;
7725f0ba
AK		 953}
954
6aa8b732
AK		 955static void vmcs_clear(struct vmcs *vmcs)
956{
957 u64 phys_addr = __pa(vmcs);
958 u8 error;
959
4ecac3fd 960 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
16d8f72f 961 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
6aa8b732
AK		 962 : "cc", "memory");
963 if (error)
964 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
965 vmcs, phys_addr);
966}
967
d462b819
NHE		 968static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
969{
970 vmcs_clear(loaded_vmcs->vmcs);
971 loaded_vmcs->cpu = -1;
972 loaded_vmcs->launched = 0;
973}
974
7725b894
DX		 975static void vmcs_load(struct vmcs *vmcs)
976{
977 u64 phys_addr = __pa(vmcs);
978 u8 error;
979
980 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
16d8f72f 981 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
7725b894
DX		 982 : "cc", "memory");
983 if (error)
2844d849 984 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
7725b894
DX		 985 vmcs, phys_addr);
986}
987
d462b819 988static void __loaded_vmcs_clear(void *arg)
6aa8b732 989{
d462b819 990 struct loaded_vmcs *loaded_vmcs = arg;
d3b2c338 991 int cpu = raw_smp_processor_id();
6aa8b732 992
d462b819
NHE		 993 if (loaded_vmcs->cpu != cpu)
994 return; /* vcpu migration can race with cpu offline */
995 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
6aa8b732 996 per_cpu(current_vmcs, cpu) = NULL;
d462b819
NHE		 997 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
998 loaded_vmcs_init(loaded_vmcs);
6aa8b732
AK		 999}
1000
d462b819 1001static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
8d0be2b3 1002{
d462b819
NHE		 1003 if (loaded_vmcs->cpu != -1)
1004 smp_call_function_single(
1005 loaded_vmcs->cpu, __loaded_vmcs_clear, loaded_vmcs, 1);
8d0be2b3
AK		 1006}
1007
1760dd49 1008static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
2384d2b3
SY		 1009{
1010 if (vmx->vpid == 0)
1011 return;
1012
518c8aee
GJ		 1013 if (cpu_has_vmx_invvpid_single())
1014 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
2384d2b3
SY		 1015}
1016
b9d762fa
GJ		 1017static inline void vpid_sync_vcpu_global(void)
1018{
1019 if (cpu_has_vmx_invvpid_global())
1020 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1021}
1022
1023static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1024{
1025 if (cpu_has_vmx_invvpid_single())
1760dd49 1026 vpid_sync_vcpu_single(vmx);
b9d762fa
GJ		 1027 else
1028 vpid_sync_vcpu_global();
1029}
1030
1439442c
SY		 1031static inline void ept_sync_global(void)
1032{
1033 if (cpu_has_vmx_invept_global())
1034 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1035}
1036
1037static inline void ept_sync_context(u64 eptp)
1038{
089d034e 1039 if (enable_ept) {
1439442c
SY		 1040 if (cpu_has_vmx_invept_context())
1041 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1042 else
1043 ept_sync_global();
1044 }
1045}
1046
1047static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
1048{
089d034e 1049 if (enable_ept) {
1439442c
SY		 1050 if (cpu_has_vmx_invept_individual_addr())
1051 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
1052 eptp, gpa);
1053 else
1054 ept_sync_context(eptp);
1055 }
1056}
1057
96304217 1058static __always_inline unsigned long vmcs_readl(unsigned long field)
6aa8b732 1059{
5e520e62 1060 unsigned long value;
6aa8b732 1061
5e520e62
AK		 1062 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1063 : "=a"(value) : "d"(field) : "cc");
6aa8b732
AK		 1064 return value;
1065}
1066
96304217 1067static __always_inline u16 vmcs_read16(unsigned long field)
6aa8b732
AK		 1068{
1069 return vmcs_readl(field);
1070}
1071
96304217 1072static __always_inline u32 vmcs_read32(unsigned long field)
6aa8b732
AK		 1073{
1074 return vmcs_readl(field);
1075}
1076
96304217 1077static __always_inline u64 vmcs_read64(unsigned long field)
6aa8b732 1078{
05b3e0c2 1079#ifdef CONFIG_X86_64
6aa8b732
AK		 1080 return vmcs_readl(field);
1081#else
1082 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1083#endif
1084}
1085
e52de1b8
AK		 1086static noinline void vmwrite_error(unsigned long field, unsigned long value)
1087{
1088 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1089 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1090 dump_stack();
1091}
1092
6aa8b732
AK		 1093static void vmcs_writel(unsigned long field, unsigned long value)
1094{
1095 u8 error;
1096
4ecac3fd 1097 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 1098 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 1099 if (unlikely(error))
1100 vmwrite_error(field, value);
6aa8b732
AK		 1101}
1102
1103static void vmcs_write16(unsigned long field, u16 value)
1104{
1105 vmcs_writel(field, value);
1106}
1107
1108static void vmcs_write32(unsigned long field, u32 value)
1109{
1110 vmcs_writel(field, value);
1111}
1112
1113static void vmcs_write64(unsigned long field, u64 value)
1114{
6aa8b732 1115 vmcs_writel(field, value);
7682f2d0 1116#ifndef CONFIG_X86_64
6aa8b732
AK		 1117 asm volatile ("");
1118 vmcs_writel(field+1, value >> 32);
1119#endif
1120}
1121
2ab455cc
AL		 1122static void vmcs_clear_bits(unsigned long field, u32 mask)
1123{
1124 vmcs_writel(field, vmcs_readl(field) & ~mask);
1125}
1126
1127static void vmcs_set_bits(unsigned long field, u32 mask)
1128{
1129 vmcs_writel(field, vmcs_readl(field) | mask);
1130}
1131
2fb92db1
AK		 1132static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1133{
1134 vmx->segment_cache.bitmask = 0;
1135}
1136
1137static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1138 unsigned field)
1139{
1140 bool ret;
1141 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1142
1143 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1144 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1145 vmx->segment_cache.bitmask = 0;
1146 }
1147 ret = vmx->segment_cache.bitmask & mask;
1148 vmx->segment_cache.bitmask |= mask;
1149 return ret;
1150}
1151
1152static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1153{
1154 u16 *p = &vmx->segment_cache.seg[seg].selector;
1155
1156 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1157 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1158 return *p;
1159}
1160
1161static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1162{
1163 ulong *p = &vmx->segment_cache.seg[seg].base;
1164
1165 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1166 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1167 return *p;
1168}
1169
1170static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1171{
1172 u32 *p = &vmx->segment_cache.seg[seg].limit;
1173
1174 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1175 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1176 return *p;
1177}
1178
1179static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1180{
1181 u32 *p = &vmx->segment_cache.seg[seg].ar;
1182
1183 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1184 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1185 return *p;
1186}
1187
abd3f2d6
AK		 1188static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1189{
1190 u32 eb;
1191
fd7373cc
JK		 1192 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1193 (1u << NM_VECTOR) | (1u << DB_VECTOR);
1194 if ((vcpu->guest_debug &
1195 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1196 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1197 eb |= 1u << BP_VECTOR;
7ffd92c5 1198 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 1199 eb = ~0;
089d034e 1200 if (enable_ept)
1439442c 1201 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
02daab21
AK		 1202 if (vcpu->fpu_active)
1203 eb &= ~(1u << NM_VECTOR);
36cf24e0
NHE		 1204
1205 /* When we are running a nested L2 guest and L1 specified for it a
1206 * certain exception bitmap, we must trap the same exceptions and pass
1207 * them to L1. When running L2, we will only handle the exceptions
1208 * specified above if L1 did not want them.
1209 */
1210 if (is_guest_mode(vcpu))
1211 eb |= get_vmcs12(vcpu)->exception_bitmap;
1212
abd3f2d6
AK		 1213 vmcs_write32(EXCEPTION_BITMAP, eb);
1214}
1215
8bf00a52
GN		 1216static void clear_atomic_switch_msr_special(unsigned long entry,
1217 unsigned long exit)
1218{
1219 vmcs_clear_bits(VM_ENTRY_CONTROLS, entry);
1220 vmcs_clear_bits(VM_EXIT_CONTROLS, exit);
1221}
1222
61d2ef2c
AK		 1223static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1224{
1225 unsigned i;
1226 struct msr_autoload *m = &vmx->msr_autoload;
1227
8bf00a52
GN		 1228 switch (msr) {
1229 case MSR_EFER:
1230 if (cpu_has_load_ia32_efer) {
1231 clear_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1232 VM_EXIT_LOAD_IA32_EFER);
1233 return;
1234 }
1235 break;
1236 case MSR_CORE_PERF_GLOBAL_CTRL:
1237 if (cpu_has_load_perf_global_ctrl) {
1238 clear_atomic_switch_msr_special(
1239 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1240 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1241 return;
1242 }
1243 break;
110312c8
AK		 1244 }
1245
61d2ef2c
AK		 1246 for (i = 0; i < m->nr; ++i)
1247 if (m->guest[i].index == msr)
1248 break;
1249
1250 if (i == m->nr)
1251 return;
1252 --m->nr;
1253 m->guest[i] = m->guest[m->nr];
1254 m->host[i] = m->host[m->nr];
1255 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1256 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1257}
1258
8bf00a52
GN		 1259static void add_atomic_switch_msr_special(unsigned long entry,
1260 unsigned long exit, unsigned long guest_val_vmcs,
1261 unsigned long host_val_vmcs, u64 guest_val, u64 host_val)
1262{
1263 vmcs_write64(guest_val_vmcs, guest_val);
1264 vmcs_write64(host_val_vmcs, host_val);
1265 vmcs_set_bits(VM_ENTRY_CONTROLS, entry);
1266 vmcs_set_bits(VM_EXIT_CONTROLS, exit);
1267}
1268
61d2ef2c
AK		 1269static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1270 u64 guest_val, u64 host_val)
1271{
1272 unsigned i;
1273 struct msr_autoload *m = &vmx->msr_autoload;
1274
8bf00a52
GN		 1275 switch (msr) {
1276 case MSR_EFER:
1277 if (cpu_has_load_ia32_efer) {
1278 add_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1279 VM_EXIT_LOAD_IA32_EFER,
1280 GUEST_IA32_EFER,
1281 HOST_IA32_EFER,
1282 guest_val, host_val);
1283 return;
1284 }
1285 break;
1286 case MSR_CORE_PERF_GLOBAL_CTRL:
1287 if (cpu_has_load_perf_global_ctrl) {
1288 add_atomic_switch_msr_special(
1289 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1290 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1291 GUEST_IA32_PERF_GLOBAL_CTRL,
1292 HOST_IA32_PERF_GLOBAL_CTRL,
1293 guest_val, host_val);
1294 return;
1295 }
1296 break;
110312c8
AK		 1297 }
1298
61d2ef2c
AK		 1299 for (i = 0; i < m->nr; ++i)
1300 if (m->guest[i].index == msr)
1301 break;
1302
e7fc6f93
GN		 1303 if (i == NR_AUTOLOAD_MSRS) {
1304 printk_once(KERN_WARNING"Not enough mst switch entries. "
1305 "Can't add msr %x\n", msr);
1306 return;
1307 } else if (i == m->nr) {
61d2ef2c
AK		 1308 ++m->nr;
1309 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1310 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1311 }
1312
1313 m->guest[i].index = msr;
1314 m->guest[i].value = guest_val;
1315 m->host[i].index = msr;
1316 m->host[i].value = host_val;
1317}
1318
33ed6329
AK		 1319static void reload_tss(void)
1320{
33ed6329
AK		 1321 /*
1322 * VT restores TR but not its size. Useless.
1323 */
d359192f 1324 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
a5f61300 1325 struct desc_struct *descs;
33ed6329 1326
d359192f 1327 descs = (void *)gdt->address;
33ed6329
AK		 1328 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1329 load_TR_desc();
33ed6329
AK		 1330}
1331
92c0d900 1332static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 1333{
3a34a881 1334 u64 guest_efer;
51c6cf66
AK		 1335 u64 ignore_bits;
1336
f6801dff 1337 guest_efer = vmx->vcpu.arch.efer;
3a34a881 1338
51c6cf66
AK		 1339 /*
1340 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
1341 * outside long mode
1342 */
1343 ignore_bits = EFER_NX | EFER_SCE;
1344#ifdef CONFIG_X86_64
1345 ignore_bits |= EFER_LMA | EFER_LME;
1346 /* SCE is meaningful only in long mode on Intel */
1347 if (guest_efer & EFER_LMA)
1348 ignore_bits &= ~(u64)EFER_SCE;
1349#endif
51c6cf66
AK		 1350 guest_efer &= ~ignore_bits;
1351 guest_efer |= host_efer & ignore_bits;
26bb0981 1352 vmx->guest_msrs[efer_offset].data = guest_efer;
d5696725 1353 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef
AK		 1354
1355 clear_atomic_switch_msr(vmx, MSR_EFER);
1356 /* On ept, can't emulate nx, and must switch nx atomically */
1357 if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1358 guest_efer = vmx->vcpu.arch.efer;
1359 if (!(guest_efer & EFER_LMA))
1360 guest_efer &= ~EFER_LME;
1361 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1362 return false;
1363 }
1364
26bb0981 1365 return true;
51c6cf66
AK		 1366}
1367
2d49ec72
GN		 1368static unsigned long segment_base(u16 selector)
1369{
d359192f 1370 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
2d49ec72
GN		 1371 struct desc_struct *d;
1372 unsigned long table_base;
1373 unsigned long v;
1374
1375 if (!(selector & ~3))
1376 return 0;
1377
d359192f 1378 table_base = gdt->address;
2d49ec72
GN		 1379
1380 if (selector & 4) { /* from ldt */
1381 u16 ldt_selector = kvm_read_ldt();
1382
1383 if (!(ldt_selector & ~3))
1384 return 0;
1385
1386 table_base = segment_base(ldt_selector);
1387 }
1388 d = (struct desc_struct *)(table_base + (selector & ~7));
1389 v = get_desc_base(d);
1390#ifdef CONFIG_X86_64
1391 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1392 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1393#endif
1394 return v;
1395}
1396
1397static inline unsigned long kvm_read_tr_base(void)
1398{
1399 u16 tr;
1400 asm("str %0" : "=g"(tr));
1401 return segment_base(tr);
1402}
1403
04d2cc77 1404static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 1405{
04d2cc77 1406 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1407 int i;
04d2cc77 1408
a2fa3e9f 1409 if (vmx->host_state.loaded)
33ed6329
AK		 1410 return;
1411
a2fa3e9f 1412 vmx->host_state.loaded = 1;
33ed6329
AK		 1413 /*
1414 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1415 * allow segment selectors with cpl > 0 or ti == 1.
1416 */
d6e88aec 1417 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 1418 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
9581d442 1419 savesegment(fs, vmx->host_state.fs_sel);
152d3f2f 1420 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 1421 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 1422 vmx->host_state.fs_reload_needed = 0;
1423 } else {
33ed6329 1424 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 1425 vmx->host_state.fs_reload_needed = 1;
33ed6329 1426 }
9581d442 1427 savesegment(gs, vmx->host_state.gs_sel);
a2fa3e9f
GH		 1428 if (!(vmx->host_state.gs_sel & 7))
1429 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 1430 else {
1431 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 1432 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 1433 }
1434
b2da15ac
AK		 1435#ifdef CONFIG_X86_64
1436 savesegment(ds, vmx->host_state.ds_sel);
1437 savesegment(es, vmx->host_state.es_sel);
1438#endif
1439
33ed6329
AK		 1440#ifdef CONFIG_X86_64
1441 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1442 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1443#else
a2fa3e9f
GH		 1444 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1445 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 1446#endif
707c0874
AK		 1447
1448#ifdef CONFIG_X86_64
c8770e7b
AK		 1449 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1450 if (is_long_mode(&vmx->vcpu))
44ea2b17 1451 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
707c0874 1452#endif
26bb0981
AK		 1453 for (i = 0; i < vmx->save_nmsrs; ++i)
1454 kvm_set_shared_msr(vmx->guest_msrs[i].index,
d5696725
AK		 1455 vmx->guest_msrs[i].data,
1456 vmx->guest_msrs[i].mask);
33ed6329
AK		 1457}
1458
a9b21b62 1459static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 1460{
a2fa3e9f 1461 if (!vmx->host_state.loaded)
33ed6329
AK		 1462 return;
1463
e1beb1d3 1464 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 1465 vmx->host_state.loaded = 0;
c8770e7b
AK		 1466#ifdef CONFIG_X86_64
1467 if (is_long_mode(&vmx->vcpu))
1468 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1469#endif
152d3f2f 1470 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 1471 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329 1472#ifdef CONFIG_X86_64
9581d442 1473 load_gs_index(vmx->host_state.gs_sel);
9581d442
AK		 1474#else
1475 loadsegment(gs, vmx->host_state.gs_sel);
33ed6329 1476#endif
33ed6329 1477 }
0a77fe4c
AK		 1478 if (vmx->host_state.fs_reload_needed)
1479 loadsegment(fs, vmx->host_state.fs_sel);
b2da15ac
AK		 1480#ifdef CONFIG_X86_64
1481 if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1482 loadsegment(ds, vmx->host_state.ds_sel);
1483 loadsegment(es, vmx->host_state.es_sel);
1484 }
1485#else
1486 /*
1487 * The sysexit path does not restore ds/es, so we must set them to
1488 * a reasonable value ourselves.
1489 */
1490 loadsegment(ds, __USER_DS);
1491 loadsegment(es, __USER_DS);
1492#endif
152d3f2f 1493 reload_tss();
44ea2b17 1494#ifdef CONFIG_X86_64
c8770e7b 1495 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
44ea2b17 1496#endif
1361b83a 1497 if (user_has_fpu())
1c11e713 1498 clts();
3444d7da 1499 load_gdt(&__get_cpu_var(host_gdt));
33ed6329
AK		 1500}
1501
a9b21b62
AK		 1502static void vmx_load_host_state(struct vcpu_vmx *vmx)
1503{
1504 preempt_disable();
1505 __vmx_load_host_state(vmx);
1506 preempt_enable();
1507}
1508
6aa8b732
AK		 1509/*
1510 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1511 * vcpu mutex is already taken.
1512 */
15ad7146 1513static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 1514{
a2fa3e9f 1515 struct vcpu_vmx *vmx = to_vmx(vcpu);
4610c9cc 1516 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
6aa8b732 1517
4610c9cc
DX		 1518 if (!vmm_exclusive)
1519 kvm_cpu_vmxon(phys_addr);
d462b819
NHE		 1520 else if (vmx->loaded_vmcs->cpu != cpu)
1521 loaded_vmcs_clear(vmx->loaded_vmcs);
6aa8b732 1522
d462b819
NHE		 1523 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1524 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1525 vmcs_load(vmx->loaded_vmcs->vmcs);
6aa8b732
AK		 1526 }
1527
d462b819 1528 if (vmx->loaded_vmcs->cpu != cpu) {
d359192f 1529 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
6aa8b732
AK		 1530 unsigned long sysenter_esp;
1531
a8eeb04a 1532 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
92fe13be 1533 local_irq_disable();
d462b819
NHE		 1534 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1535 &per_cpu(loaded_vmcss_on_cpu, cpu));
92fe13be
DX		 1536 local_irq_enable();
1537
6aa8b732
AK		 1538 /*
1539 * Linux uses per-cpu TSS and GDT, so set these when switching
1540 * processors.
1541 */
d6e88aec 1542 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
d359192f 1543 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
6aa8b732
AK		 1544
1545 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1546 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
d462b819 1547 vmx->loaded_vmcs->cpu = cpu;
6aa8b732 1548 }
6aa8b732
AK		 1549}
1550
1551static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1552{
a9b21b62 1553 __vmx_load_host_state(to_vmx(vcpu));
4610c9cc 1554 if (!vmm_exclusive) {
d462b819
NHE		 1555 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1556 vcpu->cpu = -1;
4610c9cc
DX		 1557 kvm_cpu_vmxoff();
1558 }
6aa8b732
AK		 1559}
1560
5fd86fcf
AK		 1561static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1562{
81231c69
AK		 1563 ulong cr0;
1564
5fd86fcf
AK		 1565 if (vcpu->fpu_active)
1566 return;
1567 vcpu->fpu_active = 1;
81231c69
AK		 1568 cr0 = vmcs_readl(GUEST_CR0);
1569 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1570 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1571 vmcs_writel(GUEST_CR0, cr0);
5fd86fcf 1572 update_exception_bitmap(vcpu);
edcafe3c 1573 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
36cf24e0
NHE		 1574 if (is_guest_mode(vcpu))
1575 vcpu->arch.cr0_guest_owned_bits &=
1576 ~get_vmcs12(vcpu)->cr0_guest_host_mask;
edcafe3c 1577 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
5fd86fcf
AK		 1578}
1579
edcafe3c
AK		 1580static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1581
fe3ef05c
NHE		 1582/*
1583 * Return the cr0 value that a nested guest would read. This is a combination
1584 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1585 * its hypervisor (cr0_read_shadow).
1586 */
1587static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1588{
1589 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1590 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1591}
1592static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1593{
1594 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1595 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1596}
1597
5fd86fcf
AK		 1598static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1599{
36cf24e0
NHE		 1600 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1601 * set this *before* calling this function.
1602 */
edcafe3c 1603 vmx_decache_cr0_guest_bits(vcpu);
81231c69 1604 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
5fd86fcf 1605 update_exception_bitmap(vcpu);
edcafe3c
AK		 1606 vcpu->arch.cr0_guest_owned_bits = 0;
1607 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
36cf24e0
NHE		 1608 if (is_guest_mode(vcpu)) {
1609 /*
1610 * L1's specified read shadow might not contain the TS bit,
1611 * so now that we turned on shadowing of this bit, we need to
1612 * set this bit of the shadow. Like in nested_vmx_run we need
1613 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1614 * up-to-date here because we just decached cr0.TS (and we'll
1615 * only update vmcs12->guest_cr0 on nested exit).
1616 */
1617 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1618 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1619 (vcpu->arch.cr0 & X86_CR0_TS);
1620 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1621 } else
1622 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf
AK		 1623}
1624
6aa8b732
AK		 1625static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1626{
78ac8b47 1627 unsigned long rflags, save_rflags;
345dcaa8 1628
6de12732
AK		 1629 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1630 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1631 rflags = vmcs_readl(GUEST_RFLAGS);
1632 if (to_vmx(vcpu)->rmode.vm86_active) {
1633 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1634 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1635 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1636 }
1637 to_vmx(vcpu)->rflags = rflags;
78ac8b47 1638 }
6de12732 1639 return to_vmx(vcpu)->rflags;
6aa8b732
AK		 1640}
1641
1642static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1643{
6de12732 1644 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
69c73028 1645 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
6de12732 1646 to_vmx(vcpu)->rflags = rflags;
78ac8b47
AK		 1647 if (to_vmx(vcpu)->rmode.vm86_active) {
1648 to_vmx(vcpu)->rmode.save_rflags = rflags;
053de044 1649 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 1650 }
6aa8b732
AK		 1651 vmcs_writel(GUEST_RFLAGS, rflags);
1652}
1653
2809f5d2
GC		 1654static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1655{
1656 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1657 int ret = 0;
1658
1659 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 1660 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 1661 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 1662 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2
GC		 1663
1664 return ret & mask;
1665}
1666
1667static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1668{
1669 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1670 u32 interruptibility = interruptibility_old;
1671
1672 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1673
48005f64 1674 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 1675 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 1676 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC		 1677 interruptibility |= GUEST_INTR_STATE_STI;
1678
1679 if ((interruptibility != interruptibility_old))
1680 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1681}
1682
6aa8b732
AK		 1683static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1684{
1685 unsigned long rip;
6aa8b732 1686
5fdbf976 1687 rip = kvm_rip_read(vcpu);
6aa8b732 1688 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 1689 kvm_rip_write(vcpu, rip);
6aa8b732 1690
2809f5d2
GC		 1691 /* skipping an emulated instruction also counts */
1692 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 1693}
1694
0b6ac343
NHE		 1695/*
1696 * KVM wants to inject page-faults which it got to the guest. This function
1697 * checks whether in a nested guest, we need to inject them to L1 or L2.
1698 * This function assumes it is called with the exit reason in vmcs02 being
1699 * a #PF exception (this is the only case in which KVM injects a #PF when L2
1700 * is running).
1701 */
1702static int nested_pf_handled(struct kvm_vcpu *vcpu)
1703{
1704 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1705
1706 /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
95871901 1707 if (!(vmcs12->exception_bitmap & (1u << PF_VECTOR)))
0b6ac343
NHE		 1708 return 0;
1709
1710 nested_vmx_vmexit(vcpu);
1711 return 1;
1712}
1713
298101da 1714static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 1715 bool has_error_code, u32 error_code,
1716 bool reinject)
298101da 1717{
77ab6db0 1718 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 1719 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 1720
0b6ac343
NHE		 1721 if (nr == PF_VECTOR && is_guest_mode(vcpu) &&
1722 nested_pf_handled(vcpu))
1723 return;
1724
8ab2d2e2 1725 if (has_error_code) {
77ab6db0 1726 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 1727 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1728 }
77ab6db0 1729
7ffd92c5 1730 if (vmx->rmode.vm86_active) {
71f9833b
SH		 1731 int inc_eip = 0;
1732 if (kvm_exception_is_soft(nr))
1733 inc_eip = vcpu->arch.event_exit_inst_len;
1734 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
a92601bb 1735 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
77ab6db0
JK		 1736 return;
1737 }
1738
66fd3f7f
GN		 1739 if (kvm_exception_is_soft(nr)) {
1740 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1741 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 1742 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1743 } else
1744 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1745
1746 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
298101da
AK		 1747}
1748
4e47c7a6
SY		 1749static bool vmx_rdtscp_supported(void)
1750{
1751 return cpu_has_vmx_rdtscp();
1752}
1753
a75beee6
ED		 1754/*
1755 * Swap MSR entry in host/guest MSR entry array.
1756 */
8b9cf98c 1757static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 1758{
26bb0981 1759 struct shared_msr_entry tmp;
a2fa3e9f
GH		 1760
1761 tmp = vmx->guest_msrs[to];
1762 vmx->guest_msrs[to] = vmx->guest_msrs[from];
1763 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 1764}
1765
e38aea3e
AK		 1766/*
1767 * Set up the vmcs to automatically save and restore system
1768 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1769 * mode, as fiddling with msrs is very expensive.
1770 */
8b9cf98c 1771static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 1772{
26bb0981 1773 int save_nmsrs, index;
5897297b 1774 unsigned long *msr_bitmap;
e38aea3e 1775
a75beee6
ED		 1776 save_nmsrs = 0;
1777#ifdef CONFIG_X86_64
8b9cf98c 1778 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 1779 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 1780 if (index >= 0)
8b9cf98c
RR		 1781 move_msr_up(vmx, index, save_nmsrs++);
1782 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 1783 if (index >= 0)
8b9cf98c
RR		 1784 move_msr_up(vmx, index, save_nmsrs++);
1785 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 1786 if (index >= 0)
8b9cf98c 1787 move_msr_up(vmx, index, save_nmsrs++);
4e47c7a6
SY		 1788 index = __find_msr_index(vmx, MSR_TSC_AUX);
1789 if (index >= 0 && vmx->rdtscp_enabled)
1790 move_msr_up(vmx, index, save_nmsrs++);
a75beee6 1791 /*
8c06585d 1792 * MSR_STAR is only needed on long mode guests, and only
a75beee6
ED		 1793 * if efer.sce is enabled.
1794 */
8c06585d 1795 index = __find_msr_index(vmx, MSR_STAR);
f6801dff 1796 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
8b9cf98c 1797 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 1798 }
1799#endif
92c0d900
AK		 1800 index = __find_msr_index(vmx, MSR_EFER);
1801 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 1802 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 1803
26bb0981 1804 vmx->save_nmsrs = save_nmsrs;
5897297b
AK		 1805
1806 if (cpu_has_vmx_msr_bitmap()) {
1807 if (is_long_mode(&vmx->vcpu))
1808 msr_bitmap = vmx_msr_bitmap_longmode;
1809 else
1810 msr_bitmap = vmx_msr_bitmap_legacy;
1811
1812 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1813 }
e38aea3e
AK		 1814}
1815
6aa8b732
AK		 1816/*
1817 * reads and returns guest's timestamp counter "register"
1818 * guest_tsc = host_tsc + tsc_offset -- 21.3
1819 */
1820static u64 guest_read_tsc(void)
1821{
1822 u64 host_tsc, tsc_offset;
1823
1824 rdtscll(host_tsc);
1825 tsc_offset = vmcs_read64(TSC_OFFSET);
1826 return host_tsc + tsc_offset;
1827}
1828
d5c1785d
NHE		 1829/*
1830 * Like guest_read_tsc, but always returns L1's notion of the timestamp
1831 * counter, even if a nested guest (L2) is currently running.
1832 */
1833u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu)
1834{
1835 u64 host_tsc, tsc_offset;
1836
1837 rdtscll(host_tsc);
1838 tsc_offset = is_guest_mode(vcpu) ?
1839 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
1840 vmcs_read64(TSC_OFFSET);
1841 return host_tsc + tsc_offset;
1842}
1843
4051b188 1844/*
cc578287
ZA		 1845 * Engage any workarounds for mis-matched TSC rates. Currently limited to
1846 * software catchup for faster rates on slower CPUs.
4051b188 1847 */
cc578287 1848static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
4051b188 1849{
cc578287
ZA		 1850 if (!scale)
1851 return;
1852
1853 if (user_tsc_khz > tsc_khz) {
1854 vcpu->arch.tsc_catchup = 1;
1855 vcpu->arch.tsc_always_catchup = 1;
1856 } else
1857 WARN(1, "user requested TSC rate below hardware speed\n");
4051b188
JR		 1858}
1859
6aa8b732 1860/*
99e3e30a 1861 * writes 'offset' into guest's timestamp counter offset register
6aa8b732 1862 */
99e3e30a 1863static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
6aa8b732 1864{
27fc51b2 1865 if (is_guest_mode(vcpu)) {
7991825b 1866 /*
27fc51b2
NHE		 1867 * We're here if L1 chose not to trap WRMSR to TSC. According
1868 * to the spec, this should set L1's TSC; The offset that L1
1869 * set for L2 remains unchanged, and still needs to be added
1870 * to the newly set TSC to get L2's TSC.
7991825b 1871 */
27fc51b2
NHE		 1872 struct vmcs12 *vmcs12;
1873 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
1874 /* recalculate vmcs02.TSC_OFFSET: */
1875 vmcs12 = get_vmcs12(vcpu);
1876 vmcs_write64(TSC_OFFSET, offset +
1877 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
1878 vmcs12->tsc_offset : 0));
1879 } else {
1880 vmcs_write64(TSC_OFFSET, offset);
1881 }
6aa8b732
AK		 1882}
1883
f1e2b260 1884static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
e48672fa
ZA		 1885{
1886 u64 offset = vmcs_read64(TSC_OFFSET);
1887 vmcs_write64(TSC_OFFSET, offset + adjustment);
7991825b
NHE		 1888 if (is_guest_mode(vcpu)) {
1889 /* Even when running L2, the adjustment needs to apply to L1 */
1890 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
1891 }
e48672fa
ZA		 1892}
1893
857e4099
JR		 1894static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1895{
1896 return target_tsc - native_read_tsc();
1897}
1898
801d3424
NHE		 1899static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
1900{
1901 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
1902 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
1903}
1904
1905/*
1906 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1907 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
1908 * all guests if the "nested" module option is off, and can also be disabled
1909 * for a single guest by disabling its VMX cpuid bit.
1910 */
1911static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
1912{
1913 return nested && guest_cpuid_has_vmx(vcpu);
1914}
1915
b87a51ae
NHE		 1916/*
1917 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
1918 * returned for the various VMX controls MSRs when nested VMX is enabled.
1919 * The same values should also be used to verify that vmcs12 control fields are
1920 * valid during nested entry from L1 to L2.
1921 * Each of these control msrs has a low and high 32-bit half: A low bit is on
1922 * if the corresponding bit in the (32-bit) control field *must* be on, and a
1923 * bit in the high half is on if the corresponding bit in the control field
1924 * may be on. See also vmx_control_verify().
1925 * TODO: allow these variables to be modified (downgraded) by module options
1926 * or other means.
1927 */
1928static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
1929static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
1930static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
1931static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
1932static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
1933static __init void nested_vmx_setup_ctls_msrs(void)
1934{
1935 /*
1936 * Note that as a general rule, the high half of the MSRs (bits in
1937 * the control fields which may be 1) should be initialized by the
1938 * intersection of the underlying hardware's MSR (i.e., features which
1939 * can be supported) and the list of features we want to expose -
1940 * because they are known to be properly supported in our code.
1941 * Also, usually, the low half of the MSRs (bits which must be 1) can
1942 * be set to 0, meaning that L1 may turn off any of these bits. The
1943 * reason is that if one of these bits is necessary, it will appear
1944 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
1945 * fields of vmcs01 and vmcs02, will turn these bits off - and
1946 * nested_vmx_exit_handled() will not pass related exits to L1.
1947 * These rules have exceptions below.
1948 */
1949
1950 /* pin-based controls */
1951 /*
1952 * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
1953 * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
1954 */
1955 nested_vmx_pinbased_ctls_low = 0x16 ;
1956 nested_vmx_pinbased_ctls_high = 0x16 |
1957 PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING |
1958 PIN_BASED_VIRTUAL_NMIS;
1959
1960 /* exit controls */
1961 nested_vmx_exit_ctls_low = 0;
b6f1250e 1962 /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
b87a51ae
NHE		 1963#ifdef CONFIG_X86_64
1964 nested_vmx_exit_ctls_high = VM_EXIT_HOST_ADDR_SPACE_SIZE;
1965#else
1966 nested_vmx_exit_ctls_high = 0;
1967#endif
1968
1969 /* entry controls */
1970 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
1971 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
1972 nested_vmx_entry_ctls_low = 0;
1973 nested_vmx_entry_ctls_high &=
1974 VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_IA32E_MODE;
1975
1976 /* cpu-based controls */
1977 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
1978 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
1979 nested_vmx_procbased_ctls_low = 0;
1980 nested_vmx_procbased_ctls_high &=
1981 CPU_BASED_VIRTUAL_INTR_PENDING | CPU_BASED_USE_TSC_OFFSETING |
1982 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
1983 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
1984 CPU_BASED_CR3_STORE_EXITING |
1985#ifdef CONFIG_X86_64
1986 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
1987#endif
1988 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
1989 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
fee84b07 1990 CPU_BASED_RDPMC_EXITING |
b87a51ae
NHE		 1991 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1992 /*
1993 * We can allow some features even when not supported by the
1994 * hardware. For example, L1 can specify an MSR bitmap - and we
1995 * can use it to avoid exits to L1 - even when L0 runs L2
1996 * without MSR bitmaps.
1997 */
1998 nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS;
1999
2000 /* secondary cpu-based controls */
2001 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2002 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
2003 nested_vmx_secondary_ctls_low = 0;
2004 nested_vmx_secondary_ctls_high &=
2005 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2006}
2007
2008static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2009{
2010 /*
2011 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2012 */
2013 return ((control & high) | low) == control;
2014}
2015
2016static inline u64 vmx_control_msr(u32 low, u32 high)
2017{
2018 return low | ((u64)high << 32);
2019}
2020
2021/*
2022 * If we allow our guest to use VMX instructions (i.e., nested VMX), we should
2023 * also let it use VMX-specific MSRs.
2024 * vmx_get_vmx_msr() and vmx_set_vmx_msr() return 1 when we handled a
2025 * VMX-specific MSR, or 0 when we haven't (and the caller should handle it
2026 * like all other MSRs).
2027 */
2028static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2029{
2030 if (!nested_vmx_allowed(vcpu) && msr_index >= MSR_IA32_VMX_BASIC &&
2031 msr_index <= MSR_IA32_VMX_TRUE_ENTRY_CTLS) {
2032 /*
2033 * According to the spec, processors which do not support VMX
2034 * should throw a #GP(0) when VMX capability MSRs are read.
2035 */
2036 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
2037 return 1;
2038 }
2039
2040 switch (msr_index) {
2041 case MSR_IA32_FEATURE_CONTROL:
2042 *pdata = 0;
2043 break;
2044 case MSR_IA32_VMX_BASIC:
2045 /*
2046 * This MSR reports some information about VMX support. We
2047 * should return information about the VMX we emulate for the
2048 * guest, and the VMCS structure we give it - not about the
2049 * VMX support of the underlying hardware.
2050 */
2051 *pdata = VMCS12_REVISION |
2052 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2053 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2054 break;
2055 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2056 case MSR_IA32_VMX_PINBASED_CTLS:
2057 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2058 nested_vmx_pinbased_ctls_high);
2059 break;
2060 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2061 case MSR_IA32_VMX_PROCBASED_CTLS:
2062 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2063 nested_vmx_procbased_ctls_high);
2064 break;
2065 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2066 case MSR_IA32_VMX_EXIT_CTLS:
2067 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2068 nested_vmx_exit_ctls_high);
2069 break;
2070 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2071 case MSR_IA32_VMX_ENTRY_CTLS:
2072 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2073 nested_vmx_entry_ctls_high);
2074 break;
2075 case MSR_IA32_VMX_MISC:
2076 *pdata = 0;
2077 break;
2078 /*
2079 * These MSRs specify bits which the guest must keep fixed (on or off)
2080 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2081 * We picked the standard core2 setting.
2082 */
2083#define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2084#define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2085 case MSR_IA32_VMX_CR0_FIXED0:
2086 *pdata = VMXON_CR0_ALWAYSON;
2087 break;
2088 case MSR_IA32_VMX_CR0_FIXED1:
2089 *pdata = -1ULL;
2090 break;
2091 case MSR_IA32_VMX_CR4_FIXED0:
2092 *pdata = VMXON_CR4_ALWAYSON;
2093 break;
2094 case MSR_IA32_VMX_CR4_FIXED1:
2095 *pdata = -1ULL;
2096 break;
2097 case MSR_IA32_VMX_VMCS_ENUM:
2098 *pdata = 0x1f;
2099 break;
2100 case MSR_IA32_VMX_PROCBASED_CTLS2:
2101 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2102 nested_vmx_secondary_ctls_high);
2103 break;
2104 case MSR_IA32_VMX_EPT_VPID_CAP:
2105 /* Currently, no nested ept or nested vpid */
2106 *pdata = 0;
2107 break;
2108 default:
2109 return 0;
2110 }
2111
2112 return 1;
2113}
2114
2115static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
2116{
2117 if (!nested_vmx_allowed(vcpu))
2118 return 0;
2119
2120 if (msr_index == MSR_IA32_FEATURE_CONTROL)
2121 /* TODO: the right thing. */
2122 return 1;
2123 /*
2124 * No need to treat VMX capability MSRs specially: If we don't handle
2125 * them, handle_wrmsr will #GP(0), which is correct (they are readonly)
2126 */
2127 return 0;
2128}
2129
6aa8b732
AK		 2130/*
2131 * Reads an msr value (of 'msr_index') into 'pdata'.
2132 * Returns 0 on success, non-0 otherwise.
2133 * Assumes vcpu_load() was already called.
2134 */
2135static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2136{
2137 u64 data;
26bb0981 2138 struct shared_msr_entry *msr;
6aa8b732
AK		 2139
2140 if (!pdata) {
2141 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2142 return -EINVAL;
2143 }
2144
2145 switch (msr_index) {
05b3e0c2 2146#ifdef CONFIG_X86_64
6aa8b732
AK		 2147 case MSR_FS_BASE:
2148 data = vmcs_readl(GUEST_FS_BASE);
2149 break;
2150 case MSR_GS_BASE:
2151 data = vmcs_readl(GUEST_GS_BASE);
2152 break;
44ea2b17
AK		 2153 case MSR_KERNEL_GS_BASE:
2154 vmx_load_host_state(to_vmx(vcpu));
2155 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2156 break;
26bb0981 2157#endif
6aa8b732 2158 case MSR_EFER:
3bab1f5d 2159 return kvm_get_msr_common(vcpu, msr_index, pdata);
af24a4e4 2160 case MSR_IA32_TSC:
6aa8b732
AK		 2161 data = guest_read_tsc();
2162 break;
2163 case MSR_IA32_SYSENTER_CS:
2164 data = vmcs_read32(GUEST_SYSENTER_CS);
2165 break;
2166 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2167 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 2168 break;
2169 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2170 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 2171 break;
4e47c7a6
SY		 2172 case MSR_TSC_AUX:
2173 if (!to_vmx(vcpu)->rdtscp_enabled)
2174 return 1;
2175 /* Otherwise falls through */
6aa8b732 2176 default:
b87a51ae
NHE		 2177 if (vmx_get_vmx_msr(vcpu, msr_index, pdata))
2178 return 0;
8b9cf98c 2179 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d
AK		 2180 if (msr) {
2181 data = msr->data;
2182 break;
6aa8b732 2183 }
3bab1f5d 2184 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 2185 }
2186
2187 *pdata = data;
2188 return 0;
2189}
2190
2191/*
2192 * Writes msr value into into the appropriate "register".
2193 * Returns 0 on success, non-0 otherwise.
2194 * Assumes vcpu_load() was already called.
2195 */
2196static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
2197{
a2fa3e9f 2198 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 2199 struct shared_msr_entry *msr;
2cc51560
ED		 2200 int ret = 0;
2201
6aa8b732 2202 switch (msr_index) {
3bab1f5d 2203 case MSR_EFER:
2cc51560 2204 ret = kvm_set_msr_common(vcpu, msr_index, data);
2cc51560 2205 break;
16175a79 2206#ifdef CONFIG_X86_64
6aa8b732 2207 case MSR_FS_BASE:
2fb92db1 2208 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2209 vmcs_writel(GUEST_FS_BASE, data);
2210 break;
2211 case MSR_GS_BASE:
2fb92db1 2212 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2213 vmcs_writel(GUEST_GS_BASE, data);
2214 break;
44ea2b17
AK		 2215 case MSR_KERNEL_GS_BASE:
2216 vmx_load_host_state(vmx);
2217 vmx->msr_guest_kernel_gs_base = data;
2218 break;
6aa8b732
AK		 2219#endif
2220 case MSR_IA32_SYSENTER_CS:
2221 vmcs_write32(GUEST_SYSENTER_CS, data);
2222 break;
2223 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2224 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 2225 break;
2226 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2227 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 2228 break;
af24a4e4 2229 case MSR_IA32_TSC:
99e3e30a 2230 kvm_write_tsc(vcpu, data);
6aa8b732 2231 break;
468d472f
SY		 2232 case MSR_IA32_CR_PAT:
2233 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2234 vmcs_write64(GUEST_IA32_PAT, data);
2235 vcpu->arch.pat = data;
2236 break;
2237 }
4e47c7a6
SY		 2238 ret = kvm_set_msr_common(vcpu, msr_index, data);
2239 break;
2240 case MSR_TSC_AUX:
2241 if (!vmx->rdtscp_enabled)
2242 return 1;
2243 /* Check reserved bit, higher 32 bits should be zero */
2244 if ((data >> 32) != 0)
2245 return 1;
2246 /* Otherwise falls through */
6aa8b732 2247 default:
b87a51ae
NHE		 2248 if (vmx_set_vmx_msr(vcpu, msr_index, data))
2249 break;
8b9cf98c 2250 msr = find_msr_entry(vmx, msr_index);
3bab1f5d
AK		 2251 if (msr) {
2252 msr->data = data;
2225fd56
AK		 2253 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2254 preempt_disable();
9ee73970
AK		 2255 kvm_set_shared_msr(msr->index, msr->data,
2256 msr->mask);
2225fd56
AK		 2257 preempt_enable();
2258 }
3bab1f5d 2259 break;
6aa8b732 2260 }
2cc51560 2261 ret = kvm_set_msr_common(vcpu, msr_index, data);
6aa8b732
AK		 2262 }
2263
2cc51560 2264 return ret;
6aa8b732
AK		 2265}
2266
5fdbf976 2267static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 2268{
5fdbf976
MT		 2269 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2270 switch (reg) {
2271 case VCPU_REGS_RSP:
2272 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2273 break;
2274 case VCPU_REGS_RIP:
2275 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2276 break;
6de4f3ad
AK		 2277 case VCPU_EXREG_PDPTR:
2278 if (enable_ept)
2279 ept_save_pdptrs(vcpu);
2280 break;
5fdbf976
MT		 2281 default:
2282 break;
2283 }
6aa8b732
AK		 2284}
2285
355be0b9 2286static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
6aa8b732 2287{
ae675ef0
JK		 2288 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
2289 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
2290 else
2291 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
2292
abd3f2d6 2293 update_exception_bitmap(vcpu);
6aa8b732
AK		 2294}
2295
2296static __init int cpu_has_kvm_support(void)
2297{
6210e37b 2298 return cpu_has_vmx();
6aa8b732
AK		 2299}
2300
2301static __init int vmx_disabled_by_bios(void)
2302{
2303 u64 msr;
2304
2305 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
cafd6659 2306 if (msr & FEATURE_CONTROL_LOCKED) {
23f3e991 2307 /* launched w/ TXT and VMX disabled */
cafd6659
SW		 2308 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2309 && tboot_enabled())
2310 return 1;
23f3e991 2311 /* launched w/o TXT and VMX only enabled w/ TXT */
cafd6659 2312 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
23f3e991 2313 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
f9335afe
SW		 2314 && !tboot_enabled()) {
2315 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
23f3e991 2316 "activate TXT before enabling KVM\n");
cafd6659 2317 return 1;
f9335afe 2318 }
23f3e991
JC		 2319 /* launched w/o TXT and VMX disabled */
2320 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2321 && !tboot_enabled())
2322 return 1;
cafd6659
SW		 2323 }
2324
2325 return 0;
6aa8b732
AK		 2326}
2327
7725b894
DX		 2328static void kvm_cpu_vmxon(u64 addr)
2329{
2330 asm volatile (ASM_VMX_VMXON_RAX
2331 : : "a"(&addr), "m"(addr)
2332 : "memory", "cc");
2333}
2334
10474ae8 2335static int hardware_enable(void *garbage)
6aa8b732
AK		 2336{
2337 int cpu = raw_smp_processor_id();
2338 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
cafd6659 2339 u64 old, test_bits;
6aa8b732 2340
10474ae8
AG		 2341 if (read_cr4() & X86_CR4_VMXE)
2342 return -EBUSY;
2343
d462b819 2344 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
6aa8b732 2345 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
cafd6659
SW		 2346
2347 test_bits = FEATURE_CONTROL_LOCKED;
2348 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2349 if (tboot_enabled())
2350 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2351
2352 if ((old & test_bits) != test_bits) {
6aa8b732 2353 /* enable and lock */
cafd6659
SW		 2354 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2355 }
66aee91a 2356 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
10474ae8 2357
4610c9cc
DX		 2358 if (vmm_exclusive) {
2359 kvm_cpu_vmxon(phys_addr);
2360 ept_sync_global();
2361 }
10474ae8 2362
3444d7da
AK		 2363 store_gdt(&__get_cpu_var(host_gdt));
2364
10474ae8 2365 return 0;
6aa8b732
AK		 2366}
2367
d462b819 2368static void vmclear_local_loaded_vmcss(void)
543e4243
AK		 2369{
2370 int cpu = raw_smp_processor_id();
d462b819 2371 struct loaded_vmcs *v, *n;
543e4243 2372
d462b819
NHE		 2373 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2374 loaded_vmcss_on_cpu_link)
2375 __loaded_vmcs_clear(v);
543e4243
AK		 2376}
2377
710ff4a8
EH		 2378
2379/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2380 * tricks.
2381 */
2382static void kvm_cpu_vmxoff(void)
6aa8b732 2383{
4ecac3fd 2384 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
6aa8b732
AK		 2385}
2386
710ff4a8
EH		 2387static void hardware_disable(void *garbage)
2388{
4610c9cc 2389 if (vmm_exclusive) {
d462b819 2390 vmclear_local_loaded_vmcss();
4610c9cc
DX		 2391 kvm_cpu_vmxoff();
2392 }
7725b894 2393 write_cr4(read_cr4() & ~X86_CR4_VMXE);
710ff4a8
EH		 2394}
2395
1c3d14fe 2396static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 2397 u32 msr, u32 *result)
1c3d14fe
YS		 2398{
2399 u32 vmx_msr_low, vmx_msr_high;
2400 u32 ctl = ctl_min | ctl_opt;
2401
2402 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2403
2404 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2405 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2406
2407 /* Ensure minimum (required) set of control bits are supported. */
2408 if (ctl_min & ~ctl)
002c7f7c 2409 return -EIO;
1c3d14fe
YS		 2410
2411 *result = ctl;
2412 return 0;
2413}
2414
110312c8
AK		 2415static __init bool allow_1_setting(u32 msr, u32 ctl)
2416{
2417 u32 vmx_msr_low, vmx_msr_high;
2418
2419 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2420 return vmx_msr_high & ctl;
2421}
2422
002c7f7c 2423static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 2424{
2425 u32 vmx_msr_low, vmx_msr_high;
d56f546d 2426 u32 min, opt, min2, opt2;
1c3d14fe
YS		 2427 u32 _pin_based_exec_control = 0;
2428 u32 _cpu_based_exec_control = 0;
f78e0e2e 2429 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 2430 u32 _vmexit_control = 0;
2431 u32 _vmentry_control = 0;
2432
2433 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
f08864b4 2434 opt = PIN_BASED_VIRTUAL_NMIS;
1c3d14fe
YS		 2435 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2436 &_pin_based_exec_control) < 0)
002c7f7c 2437 return -EIO;
1c3d14fe 2438
10166744 2439 min = CPU_BASED_HLT_EXITING |
1c3d14fe
YS		 2440#ifdef CONFIG_X86_64
2441 CPU_BASED_CR8_LOAD_EXITING |
2442 CPU_BASED_CR8_STORE_EXITING |
2443#endif
d56f546d
SY		 2444 CPU_BASED_CR3_LOAD_EXITING |
2445 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 2446 CPU_BASED_USE_IO_BITMAPS |
2447 CPU_BASED_MOV_DR_EXITING |
a7052897 2448 CPU_BASED_USE_TSC_OFFSETING |
59708670
SY		 2449 CPU_BASED_MWAIT_EXITING |
2450 CPU_BASED_MONITOR_EXITING |
fee84b07
AK		 2451 CPU_BASED_INVLPG_EXITING |
2452 CPU_BASED_RDPMC_EXITING;
443381a8 2453
f78e0e2e 2454 opt = CPU_BASED_TPR_SHADOW |
25c5f225 2455 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 2456 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 2457 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2458 &_cpu_based_exec_control) < 0)
002c7f7c 2459 return -EIO;
6e5d865c
YS		 2460#ifdef CONFIG_X86_64
2461 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2462 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2463 ~CPU_BASED_CR8_STORE_EXITING;
2464#endif
f78e0e2e 2465 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 2466 min2 = 0;
2467 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2384d2b3 2468 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 2469 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 2470 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 2471 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6
SY		 2472 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
2473 SECONDARY_EXEC_RDTSCP;
d56f546d
SY		 2474 if (adjust_vmx_controls(min2, opt2,
2475 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 2476 &_cpu_based_2nd_exec_control) < 0)
2477 return -EIO;
2478 }
2479#ifndef CONFIG_X86_64
2480 if (!(_cpu_based_2nd_exec_control &
2481 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2482 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2483#endif
d56f546d 2484 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 2485 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2486 enabled */
5fff7d27
GN		 2487 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2488 CPU_BASED_CR3_STORE_EXITING |
2489 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 2490 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2491 vmx_capability.ept, vmx_capability.vpid);
2492 }
1c3d14fe
YS		 2493
2494 min = 0;
2495#ifdef CONFIG_X86_64
2496 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2497#endif
468d472f 2498 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1c3d14fe
YS		 2499 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2500 &_vmexit_control) < 0)
002c7f7c 2501 return -EIO;
1c3d14fe 2502
468d472f
SY		 2503 min = 0;
2504 opt = VM_ENTRY_LOAD_IA32_PAT;
1c3d14fe
YS		 2505 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2506 &_vmentry_control) < 0)
002c7f7c 2507 return -EIO;
6aa8b732 2508
c68876fd 2509 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 2510
2511 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2512 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 2513 return -EIO;
1c3d14fe
YS		 2514
2515#ifdef CONFIG_X86_64
2516 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2517 if (vmx_msr_high & (1u<<16))
002c7f7c 2518 return -EIO;
1c3d14fe
YS		 2519#endif
2520
2521 /* Require Write-Back (WB) memory type for VMCS accesses. */
2522 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 2523 return -EIO;
1c3d14fe 2524
002c7f7c
YS		 2525 vmcs_conf->size = vmx_msr_high & 0x1fff;
2526 vmcs_conf->order = get_order(vmcs_config.size);
2527 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 2528
002c7f7c
YS		 2529 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2530 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 2531 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 2532 vmcs_conf->vmexit_ctrl = _vmexit_control;
2533 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe 2534
110312c8
AK		 2535 cpu_has_load_ia32_efer =
2536 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2537 VM_ENTRY_LOAD_IA32_EFER)
2538 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2539 VM_EXIT_LOAD_IA32_EFER);
2540
8bf00a52
GN		 2541 cpu_has_load_perf_global_ctrl =
2542 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2543 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
2544 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2545 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2546
2547 /*
2548 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2549 * but due to arrata below it can't be used. Workaround is to use
2550 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2551 *
2552 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2553 *
2554 * AAK155 (model 26)
2555 * AAP115 (model 30)
2556 * AAT100 (model 37)
2557 * BC86,AAY89,BD102 (model 44)
2558 * BA97 (model 46)
2559 *
2560 */
2561 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
2562 switch (boot_cpu_data.x86_model) {
2563 case 26:
2564 case 30:
2565 case 37:
2566 case 44:
2567 case 46:
2568 cpu_has_load_perf_global_ctrl = false;
2569 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2570 "does not work properly. Using workaround\n");
2571 break;
2572 default:
2573 break;
2574 }
2575 }
2576
1c3d14fe 2577 return 0;
c68876fd 2578}
6aa8b732
AK		 2579
2580static struct vmcs *alloc_vmcs_cpu(int cpu)
2581{
2582 int node = cpu_to_node(cpu);
2583 struct page *pages;
2584 struct vmcs *vmcs;
2585
6484eb3e 2586 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 2587 if (!pages)
2588 return NULL;
2589 vmcs = page_address(pages);
1c3d14fe
YS		 2590 memset(vmcs, 0, vmcs_config.size);
2591 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 2592 return vmcs;
2593}
2594
2595static struct vmcs *alloc_vmcs(void)
2596{
d3b2c338 2597 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 2598}
2599
2600static void free_vmcs(struct vmcs *vmcs)
2601{
1c3d14fe 2602 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 2603}
2604
d462b819
NHE		 2605/*
2606 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2607 */
2608static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2609{
2610 if (!loaded_vmcs->vmcs)
2611 return;
2612 loaded_vmcs_clear(loaded_vmcs);
2613 free_vmcs(loaded_vmcs->vmcs);
2614 loaded_vmcs->vmcs = NULL;
2615}
2616
39959588 2617static void free_kvm_area(void)
6aa8b732
AK		 2618{
2619 int cpu;
2620
3230bb47 2621 for_each_possible_cpu(cpu) {
6aa8b732 2622 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 2623 per_cpu(vmxarea, cpu) = NULL;
2624 }
6aa8b732
AK		 2625}
2626
6aa8b732
AK		 2627static __init int alloc_kvm_area(void)
2628{
2629 int cpu;
2630
3230bb47 2631 for_each_possible_cpu(cpu) {
6aa8b732
AK		 2632 struct vmcs *vmcs;
2633
2634 vmcs = alloc_vmcs_cpu(cpu);
2635 if (!vmcs) {
2636 free_kvm_area();
2637 return -ENOMEM;
2638 }
2639
2640 per_cpu(vmxarea, cpu) = vmcs;
2641 }
2642 return 0;
2643}
2644
2645static __init int hardware_setup(void)
2646{
002c7f7c
YS		 2647 if (setup_vmcs_config(&vmcs_config) < 0)
2648 return -EIO;
50a37eb4
JR		 2649
2650 if (boot_cpu_has(X86_FEATURE_NX))
2651 kvm_enable_efer_bits(EFER_NX);
2652
93ba03c2
SY		 2653 if (!cpu_has_vmx_vpid())
2654 enable_vpid = 0;
2655
4bc9b982
SY		 2656 if (!cpu_has_vmx_ept() ||
2657 !cpu_has_vmx_ept_4levels()) {
93ba03c2 2658 enable_ept = 0;
3a624e29 2659 enable_unrestricted_guest = 0;
83c3a331 2660 enable_ept_ad_bits = 0;
3a624e29
NK		 2661 }
2662
83c3a331
XH		 2663 if (!cpu_has_vmx_ept_ad_bits())
2664 enable_ept_ad_bits = 0;
2665
3a624e29
NK		 2666 if (!cpu_has_vmx_unrestricted_guest())
2667 enable_unrestricted_guest = 0;
93ba03c2
SY		 2668
2669 if (!cpu_has_vmx_flexpriority())
2670 flexpriority_enabled = 0;
2671
95ba8273
GN		 2672 if (!cpu_has_vmx_tpr_shadow())
2673 kvm_x86_ops->update_cr8_intercept = NULL;
2674
54dee993
MT		 2675 if (enable_ept && !cpu_has_vmx_ept_2m_page())
2676 kvm_disable_largepages();
2677
4b8d54f9
ZE		 2678 if (!cpu_has_vmx_ple())
2679 ple_gap = 0;
2680
b87a51ae
NHE		 2681 if (nested)
2682 nested_vmx_setup_ctls_msrs();
2683
6aa8b732
AK		 2684 return alloc_kvm_area();
2685}
2686
2687static __exit void hardware_unsetup(void)
2688{
2689 free_kvm_area();
2690}
2691
6aa8b732
AK		 2692static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
2693{
2694 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2695
6af11b9e 2696 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
6aa8b732
AK		 2697 vmcs_write16(sf->selector, save->selector);
2698 vmcs_writel(sf->base, save->base);
2699 vmcs_write32(sf->limit, save->limit);
2700 vmcs_write32(sf->ar_bytes, save->ar);
2701 } else {
2702 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
2703 << AR_DPL_SHIFT;
2704 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
2705 }
2706}
2707
2708static void enter_pmode(struct kvm_vcpu *vcpu)
2709{
2710 unsigned long flags;
a89a8fb9 2711 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 2712
a89a8fb9 2713 vmx->emulation_required = 1;
7ffd92c5 2714 vmx->rmode.vm86_active = 0;
6aa8b732 2715
2fb92db1
AK		 2716 vmx_segment_cache_clear(vmx);
2717
d0ba64f9 2718 vmcs_write16(GUEST_TR_SELECTOR, vmx->rmode.tr.selector);
7ffd92c5
AK		 2719 vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
2720 vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
2721 vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
6aa8b732
AK		 2722
2723 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 2724 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2725 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK		 2726 vmcs_writel(GUEST_RFLAGS, flags);
2727
66aee91a
RR		 2728 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
2729 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 2730
2731 update_exception_bitmap(vcpu);
2732
a89a8fb9
MG		 2733 if (emulate_invalid_guest_state)
2734 return;
2735
7ffd92c5
AK		 2736 fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
2737 fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
2738 fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
2739 fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
6aa8b732 2740
2fb92db1
AK		 2741 vmx_segment_cache_clear(vmx);
2742
6aa8b732
AK		 2743 vmcs_write16(GUEST_SS_SELECTOR, 0);
2744 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
2745
2746 vmcs_write16(GUEST_CS_SELECTOR,
2747 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
2748 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
2749}
2750
d77c26fc 2751static gva_t rmode_tss_base(struct kvm *kvm)
6aa8b732 2752{
bfc6d222 2753 if (!kvm->arch.tss_addr) {
bc6678a3 2754 struct kvm_memslots *slots;
28a37544 2755 struct kvm_memory_slot *slot;
bc6678a3
MT		 2756 gfn_t base_gfn;
2757
90d83dc3 2758 slots = kvm_memslots(kvm);
28a37544
XG		 2759 slot = id_to_memslot(slots, 0);
2760 base_gfn = slot->base_gfn + slot->npages - 3;
2761
cbc94022
IE		 2762 return base_gfn << PAGE_SHIFT;
2763 }
bfc6d222 2764 return kvm->arch.tss_addr;
6aa8b732
AK		 2765}
2766
2767static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
2768{
2769 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2770
2771 save->selector = vmcs_read16(sf->selector);
2772 save->base = vmcs_readl(sf->base);
2773 save->limit = vmcs_read32(sf->limit);
2774 save->ar = vmcs_read32(sf->ar_bytes);
15b00f32 2775 vmcs_write16(sf->selector, save->base >> 4);
444e863d 2776 vmcs_write32(sf->base, save->base & 0xffff0);
6aa8b732
AK		 2777 vmcs_write32(sf->limit, 0xffff);
2778 vmcs_write32(sf->ar_bytes, 0xf3);
444e863d
GN		 2779 if (save->base & 0xf)
2780 printk_once(KERN_WARNING "kvm: segment base is not paragraph"
2781 " aligned when entering protected mode (seg=%d)",
2782 seg);
6aa8b732
AK		 2783}
2784
2785static void enter_rmode(struct kvm_vcpu *vcpu)
2786{
2787 unsigned long flags;
a89a8fb9 2788 struct vcpu_vmx *vmx = to_vmx(vcpu);
b246dd5d 2789 struct kvm_segment var;
6aa8b732 2790
3a624e29
NK		 2791 if (enable_unrestricted_guest)
2792 return;
2793
a89a8fb9 2794 vmx->emulation_required = 1;
7ffd92c5 2795 vmx->rmode.vm86_active = 1;
6aa8b732 2796
776e58ea
GN		 2797 /*
2798 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
2799 * vcpu. Call it here with phys address pointing 16M below 4G.
2800 */
2801 if (!vcpu->kvm->arch.tss_addr) {
2802 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
2803 "called before entering vcpu\n");
2804 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
2805 vmx_set_tss_addr(vcpu->kvm, 0xfeffd000);
2806 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
2807 }
2808
2fb92db1
AK		 2809 vmx_segment_cache_clear(vmx);
2810
d0ba64f9 2811 vmx->rmode.tr.selector = vmcs_read16(GUEST_TR_SELECTOR);
7ffd92c5 2812 vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
6aa8b732
AK		 2813 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
2814
7ffd92c5 2815 vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
6aa8b732
AK		 2816 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
2817
7ffd92c5 2818 vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
6aa8b732
AK		 2819 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2820
2821 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 2822 vmx->rmode.save_rflags = flags;
6aa8b732 2823
053de044 2824 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 2825
2826 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 2827 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 2828 update_exception_bitmap(vcpu);
2829
a89a8fb9
MG		 2830 if (emulate_invalid_guest_state)
2831 goto continue_rmode;
2832
b246dd5d
OW		 2833 vmx_get_segment(vcpu, &var, VCPU_SREG_SS);
2834 vmx_set_segment(vcpu, &var, VCPU_SREG_SS);
2835
2836 vmx_get_segment(vcpu, &var, VCPU_SREG_CS);
2837 vmx_set_segment(vcpu, &var, VCPU_SREG_CS);
2838
2839 vmx_get_segment(vcpu, &var, VCPU_SREG_ES);
2840 vmx_set_segment(vcpu, &var, VCPU_SREG_ES);
2841
2842 vmx_get_segment(vcpu, &var, VCPU_SREG_DS);
2843 vmx_set_segment(vcpu, &var, VCPU_SREG_DS);
6aa8b732 2844
b246dd5d
OW		 2845 vmx_get_segment(vcpu, &var, VCPU_SREG_GS);
2846 vmx_set_segment(vcpu, &var, VCPU_SREG_GS);
6aa8b732 2847
b246dd5d
OW		 2848 vmx_get_segment(vcpu, &var, VCPU_SREG_FS);
2849 vmx_set_segment(vcpu, &var, VCPU_SREG_FS);
75880a01 2850
a89a8fb9 2851continue_rmode:
8668a3c4 2852 kvm_mmu_reset_context(vcpu);
6aa8b732
AK		 2853}
2854
401d10de
AS		 2855static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
2856{
2857 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 2858 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
2859
2860 if (!msr)
2861 return;
401d10de 2862
44ea2b17
AK		 2863 /*
2864 * Force kernel_gs_base reloading before EFER changes, as control
2865 * of this msr depends on is_long_mode().
2866 */
2867 vmx_load_host_state(to_vmx(vcpu));
f6801dff 2868 vcpu->arch.efer = efer;
401d10de
AS		 2869 if (efer & EFER_LMA) {
2870 vmcs_write32(VM_ENTRY_CONTROLS,
2871 vmcs_read32(VM_ENTRY_CONTROLS) |
2872 VM_ENTRY_IA32E_MODE);
2873 msr->data = efer;
2874 } else {
2875 vmcs_write32(VM_ENTRY_CONTROLS,
2876 vmcs_read32(VM_ENTRY_CONTROLS) &
2877 ~VM_ENTRY_IA32E_MODE);
2878
2879 msr->data = efer & ~EFER_LME;
2880 }
2881 setup_msrs(vmx);
2882}
2883
05b3e0c2 2884#ifdef CONFIG_X86_64
6aa8b732
AK		 2885
2886static void enter_lmode(struct kvm_vcpu *vcpu)
2887{
2888 u32 guest_tr_ar;
2889
2fb92db1
AK		 2890 vmx_segment_cache_clear(to_vmx(vcpu));
2891
6aa8b732
AK		 2892 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
2893 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
bd80158a
JK		 2894 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
2895 __func__);
6aa8b732
AK		 2896 vmcs_write32(GUEST_TR_AR_BYTES,
2897 (guest_tr_ar & ~AR_TYPE_MASK)
2898 | AR_TYPE_BUSY_64_TSS);
2899 }
da38f438 2900 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
6aa8b732
AK		 2901}
2902
2903static void exit_lmode(struct kvm_vcpu *vcpu)
2904{
6aa8b732
AK		 2905 vmcs_write32(VM_ENTRY_CONTROLS,
2906 vmcs_read32(VM_ENTRY_CONTROLS)
1e4e6e00 2907 & ~VM_ENTRY_IA32E_MODE);
da38f438 2908 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
6aa8b732
AK		 2909}
2910
2911#endif
2912
2384d2b3
SY		 2913static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
2914{
b9d762fa 2915 vpid_sync_context(to_vmx(vcpu));
dd180b3e
XG		 2916 if (enable_ept) {
2917 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2918 return;
4e1096d2 2919 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
dd180b3e 2920 }
2384d2b3
SY		 2921}
2922
e8467fda
AK		 2923static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
2924{
2925 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
2926
2927 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
2928 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
2929}
2930
aff48baa
AK		 2931static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
2932{
2933 if (enable_ept && is_paging(vcpu))
2934 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2935 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
2936}
2937
25c4c276 2938static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 2939{
fc78f519
AK		 2940 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
2941
2942 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
2943 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 2944}
2945
1439442c
SY		 2946static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
2947{
6de4f3ad
AK		 2948 if (!test_bit(VCPU_EXREG_PDPTR,
2949 (unsigned long *)&vcpu->arch.regs_dirty))
2950 return;
2951
1439442c 2952 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
ff03a073
JR		 2953 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
2954 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
2955 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
2956 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
1439442c
SY		 2957 }
2958}
2959
8f5d549f
AK		 2960static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
2961{
2962 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
ff03a073
JR		 2963 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
2964 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
2965 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
2966 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
8f5d549f 2967 }
6de4f3ad
AK		 2968
2969 __set_bit(VCPU_EXREG_PDPTR,
2970 (unsigned long *)&vcpu->arch.regs_avail);
2971 __set_bit(VCPU_EXREG_PDPTR,
2972 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 2973}
2974
5e1746d6 2975static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1439442c
SY		 2976
2977static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
2978 unsigned long cr0,
2979 struct kvm_vcpu *vcpu)
2980{
5233dd51
MT		 2981 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
2982 vmx_decache_cr3(vcpu);
1439442c
SY		 2983 if (!(cr0 & X86_CR0_PG)) {
2984 /* From paging/starting to nonpaging */
2985 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 2986 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 2987 (CPU_BASED_CR3_LOAD_EXITING |
2988 CPU_BASED_CR3_STORE_EXITING));
2989 vcpu->arch.cr0 = cr0;
fc78f519 2990 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 2991 } else if (!is_paging(vcpu)) {
2992 /* From nonpaging to paging */
2993 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 2994 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 2995 ~(CPU_BASED_CR3_LOAD_EXITING |
2996 CPU_BASED_CR3_STORE_EXITING));
2997 vcpu->arch.cr0 = cr0;
fc78f519 2998 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 2999 }
95eb84a7
SY		 3000
3001 if (!(cr0 & X86_CR0_WP))
3002 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 3003}
3004
6aa8b732
AK		 3005static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3006{
7ffd92c5 3007 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 3008 unsigned long hw_cr0;
3009
3010 if (enable_unrestricted_guest)
3011 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
3012 | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
3013 else
3014 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
1439442c 3015
7ffd92c5 3016 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
6aa8b732
AK		 3017 enter_pmode(vcpu);
3018
7ffd92c5 3019 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
6aa8b732
AK		 3020 enter_rmode(vcpu);
3021
05b3e0c2 3022#ifdef CONFIG_X86_64
f6801dff 3023 if (vcpu->arch.efer & EFER_LME) {
707d92fa 3024 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 3025 enter_lmode(vcpu);
707d92fa 3026 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 3027 exit_lmode(vcpu);
3028 }
3029#endif
3030
089d034e 3031 if (enable_ept)
1439442c
SY		 3032 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3033
02daab21 3034 if (!vcpu->fpu_active)
81231c69 3035 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
02daab21 3036
6aa8b732 3037 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 3038 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 3039 vcpu->arch.cr0 = cr0;
69c73028 3040 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
6aa8b732
AK		 3041}
3042
1439442c
SY		 3043static u64 construct_eptp(unsigned long root_hpa)
3044{
3045 u64 eptp;
3046
3047 /* TODO write the value reading from MSR */
3048 eptp = VMX_EPT_DEFAULT_MT |
3049 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
b38f9934
XH		 3050 if (enable_ept_ad_bits)
3051 eptp |= VMX_EPT_AD_ENABLE_BIT;
1439442c
SY		 3052 eptp |= (root_hpa & PAGE_MASK);
3053
3054 return eptp;
3055}
3056
6aa8b732
AK		 3057static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3058{
1439442c
SY		 3059 unsigned long guest_cr3;
3060 u64 eptp;
3061
3062 guest_cr3 = cr3;
089d034e 3063 if (enable_ept) {
1439442c
SY		 3064 eptp = construct_eptp(cr3);
3065 vmcs_write64(EPT_POINTER, eptp);
9f8fe504 3066 guest_cr3 = is_paging(vcpu) ? kvm_read_cr3(vcpu) :
b927a3ce 3067 vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 3068 ept_load_pdptrs(vcpu);
1439442c
SY		 3069 }
3070
2384d2b3 3071 vmx_flush_tlb(vcpu);
1439442c 3072 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK		 3073}
3074
5e1746d6 3075static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
6aa8b732 3076{
7ffd92c5 3077 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1439442c
SY		 3078 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3079
5e1746d6
NHE		 3080 if (cr4 & X86_CR4_VMXE) {
3081 /*
3082 * To use VMXON (and later other VMX instructions), a guest
3083 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3084 * So basically the check on whether to allow nested VMX
3085 * is here.
3086 */
3087 if (!nested_vmx_allowed(vcpu))
3088 return 1;
3089 } else if (to_vmx(vcpu)->nested.vmxon)
3090 return 1;
3091
ad312c7c 3092 vcpu->arch.cr4 = cr4;
bc23008b
AK		 3093 if (enable_ept) {
3094 if (!is_paging(vcpu)) {
3095 hw_cr4 &= ~X86_CR4_PAE;
3096 hw_cr4 |= X86_CR4_PSE;
3097 } else if (!(cr4 & X86_CR4_PAE)) {
3098 hw_cr4 &= ~X86_CR4_PAE;
3099 }
3100 }
1439442c
SY		 3101
3102 vmcs_writel(CR4_READ_SHADOW, cr4);
3103 vmcs_writel(GUEST_CR4, hw_cr4);
5e1746d6 3104 return 0;
6aa8b732
AK		 3105}
3106
6aa8b732
AK		 3107static void vmx_get_segment(struct kvm_vcpu *vcpu,
3108 struct kvm_segment *var, int seg)
3109{
a9179499 3110 struct vcpu_vmx *vmx = to_vmx(vcpu);
a9179499 3111 struct kvm_save_segment *save;
6aa8b732
AK		 3112 u32 ar;
3113
a9179499
AK		 3114 if (vmx->rmode.vm86_active
3115 && (seg == VCPU_SREG_TR || seg == VCPU_SREG_ES
3116 || seg == VCPU_SREG_DS || seg == VCPU_SREG_FS
3117 || seg == VCPU_SREG_GS)
3118 && !emulate_invalid_guest_state) {
3119 switch (seg) {
3120 case VCPU_SREG_TR: save = &vmx->rmode.tr; break;
3121 case VCPU_SREG_ES: save = &vmx->rmode.es; break;
3122 case VCPU_SREG_DS: save = &vmx->rmode.ds; break;
3123 case VCPU_SREG_FS: save = &vmx->rmode.fs; break;
3124 case VCPU_SREG_GS: save = &vmx->rmode.gs; break;
3125 default: BUG();
3126 }
3127 var->selector = save->selector;
3128 var->base = save->base;
3129 var->limit = save->limit;
3130 ar = save->ar;
3131 if (seg == VCPU_SREG_TR
2fb92db1 3132 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
a9179499
AK		 3133 goto use_saved_rmode_seg;
3134 }
2fb92db1
AK		 3135 var->base = vmx_read_guest_seg_base(vmx, seg);
3136 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3137 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3138 ar = vmx_read_guest_seg_ar(vmx, seg);
a9179499 3139use_saved_rmode_seg:
9fd4a3b7 3140 if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
6aa8b732
AK		 3141 ar = 0;
3142 var->type = ar & 15;
3143 var->s = (ar >> 4) & 1;
3144 var->dpl = (ar >> 5) & 3;
3145 var->present = (ar >> 7) & 1;
3146 var->avl = (ar >> 12) & 1;
3147 var->l = (ar >> 13) & 1;
3148 var->db = (ar >> 14) & 1;
3149 var->g = (ar >> 15) & 1;
3150 var->unusable = (ar >> 16) & 1;
3151}
3152
a9179499
AK		 3153static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3154{
a9179499
AK		 3155 struct kvm_segment s;
3156
3157 if (to_vmx(vcpu)->rmode.vm86_active) {
3158 vmx_get_segment(vcpu, &s, seg);
3159 return s.base;
3160 }
2fb92db1 3161 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
a9179499
AK		 3162}
3163
69c73028 3164static int __vmx_get_cpl(struct kvm_vcpu *vcpu)
2e4d2653 3165{
3eeb3288 3166 if (!is_protmode(vcpu))
2e4d2653
IE		 3167 return 0;
3168
f4c63e5d
AK		 3169 if (!is_long_mode(vcpu)
3170 && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
2e4d2653
IE		 3171 return 3;
3172
2fb92db1 3173 return vmx_read_guest_seg_selector(to_vmx(vcpu), VCPU_SREG_CS) & 3;
2e4d2653
IE		 3174}
3175
69c73028
AK		 3176static int vmx_get_cpl(struct kvm_vcpu *vcpu)
3177{
d881e6f6
AK		 3178 struct vcpu_vmx *vmx = to_vmx(vcpu);
3179
3180 /*
3181 * If we enter real mode with cs.sel & 3 != 0, the normal CPL calculations
3182 * fail; use the cache instead.
3183 */
3184 if (unlikely(vmx->emulation_required && emulate_invalid_guest_state)) {
3185 return vmx->cpl;
3186 }
3187
69c73028
AK		 3188 if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
3189 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
d881e6f6 3190 vmx->cpl = __vmx_get_cpl(vcpu);
69c73028 3191 }
d881e6f6
AK		 3192
3193 return vmx->cpl;
69c73028
AK		 3194}
3195
3196
653e3108 3197static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 3198{
6aa8b732
AK		 3199 u32 ar;
3200
f0495f9b 3201 if (var->unusable || !var->present)
6aa8b732
AK		 3202 ar = 1 << 16;
3203 else {
3204 ar = var->type & 15;
3205 ar |= (var->s & 1) << 4;
3206 ar |= (var->dpl & 3) << 5;
3207 ar |= (var->present & 1) << 7;
3208 ar |= (var->avl & 1) << 12;
3209 ar |= (var->l & 1) << 13;
3210 ar |= (var->db & 1) << 14;
3211 ar |= (var->g & 1) << 15;
3212 }
653e3108
AK		 3213
3214 return ar;
3215}
3216
3217static void vmx_set_segment(struct kvm_vcpu *vcpu,
3218 struct kvm_segment *var, int seg)
3219{
7ffd92c5 3220 struct vcpu_vmx *vmx = to_vmx(vcpu);
653e3108
AK		 3221 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3222 u32 ar;
3223
2fb92db1
AK		 3224 vmx_segment_cache_clear(vmx);
3225
7ffd92c5 3226 if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
a8ba6c26 3227 vmcs_write16(sf->selector, var->selector);
7ffd92c5
AK		 3228 vmx->rmode.tr.selector = var->selector;
3229 vmx->rmode.tr.base = var->base;
3230 vmx->rmode.tr.limit = var->limit;
3231 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
653e3108
AK		 3232 return;
3233 }
3234 vmcs_writel(sf->base, var->base);
3235 vmcs_write32(sf->limit, var->limit);
3236 vmcs_write16(sf->selector, var->selector);
7ffd92c5 3237 if (vmx->rmode.vm86_active && var->s) {
653e3108
AK		 3238 /*
3239 * Hack real-mode segments into vm86 compatibility.
3240 */
3241 if (var->base == 0xffff0000 && var->selector == 0xf000)
3242 vmcs_writel(sf->base, 0xf0000);
3243 ar = 0xf3;
3244 } else
3245 ar = vmx_segment_access_rights(var);
3a624e29
NK		 3246
3247 /*
3248 * Fix the "Accessed" bit in AR field of segment registers for older
3249 * qemu binaries.
3250 * IA32 arch specifies that at the time of processor reset the
3251 * "Accessed" bit in the AR field of segment registers is 1. And qemu
3252 * is setting it to 0 in the usedland code. This causes invalid guest
3253 * state vmexit when "unrestricted guest" mode is turned on.
3254 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3255 * tree. Newer qemu binaries with that qemu fix would not need this
3256 * kvm hack.
3257 */
3258 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3259 ar |= 0x1; /* Accessed */
3260
6aa8b732 3261 vmcs_write32(sf->ar_bytes, ar);
69c73028 3262 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
b246dd5d
OW		 3263
3264 /*
3265 * Fix segments for real mode guest in hosts that don't have
3266 * "unrestricted_mode" or it was disabled.
3267 * This is done to allow migration of the guests from hosts with
3268 * unrestricted guest like Westmere to older host that don't have
3269 * unrestricted guest like Nehelem.
3270 */
3271 if (!enable_unrestricted_guest && vmx->rmode.vm86_active) {
3272 switch (seg) {
3273 case VCPU_SREG_CS:
3274 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
3275 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
3276 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
3277 vmcs_writel(GUEST_CS_BASE, 0xf0000);
3278 vmcs_write16(GUEST_CS_SELECTOR,
3279 vmcs_readl(GUEST_CS_BASE) >> 4);
3280 break;
3281 case VCPU_SREG_ES:
3282 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
3283 break;
3284 case VCPU_SREG_DS:
3285 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
3286 break;
3287 case VCPU_SREG_GS:
3288 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
3289 break;
3290 case VCPU_SREG_FS:
3291 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
3292 break;
3293 case VCPU_SREG_SS:
3294 vmcs_write16(GUEST_SS_SELECTOR,
3295 vmcs_readl(GUEST_SS_BASE) >> 4);
3296 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
3297 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
3298 break;
3299 }
3300 }
6aa8b732
AK		 3301}
3302
6aa8b732
AK		 3303static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3304{
2fb92db1 3305 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
6aa8b732
AK		 3306
3307 *db = (ar >> 14) & 1;
3308 *l = (ar >> 13) & 1;
3309}
3310
89a27f4d 3311static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3312{
89a27f4d
GN		 3313 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3314 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK		 3315}
3316
89a27f4d 3317static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3318{
89a27f4d
GN		 3319 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3320 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK		 3321}
3322
89a27f4d 3323static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3324{
89a27f4d
GN		 3325 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3326 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK		 3327}
3328
89a27f4d 3329static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3330{
89a27f4d
GN		 3331 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3332 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK		 3333}
3334
648dfaa7
MG		 3335static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3336{
3337 struct kvm_segment var;
3338 u32 ar;
3339
3340 vmx_get_segment(vcpu, &var, seg);
3341 ar = vmx_segment_access_rights(&var);
3342
3343 if (var.base != (var.selector << 4))
3344 return false;
3345 if (var.limit != 0xffff)
3346 return false;
3347 if (ar != 0xf3)
3348 return false;
3349
3350 return true;
3351}
3352
3353static bool code_segment_valid(struct kvm_vcpu *vcpu)
3354{
3355 struct kvm_segment cs;
3356 unsigned int cs_rpl;
3357
3358 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3359 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3360
1872a3f4
AK		 3361 if (cs.unusable)
3362 return false;
648dfaa7
MG		 3363 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3364 return false;
3365 if (!cs.s)
3366 return false;
1872a3f4 3367 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 3368 if (cs.dpl > cs_rpl)
3369 return false;
1872a3f4 3370 } else {
648dfaa7
MG		 3371 if (cs.dpl != cs_rpl)
3372 return false;
3373 }
3374 if (!cs.present)
3375 return false;
3376
3377 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3378 return true;
3379}
3380
3381static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3382{
3383 struct kvm_segment ss;
3384 unsigned int ss_rpl;
3385
3386 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3387 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3388
1872a3f4
AK		 3389 if (ss.unusable)
3390 return true;
3391 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 3392 return false;
3393 if (!ss.s)
3394 return false;
3395 if (ss.dpl != ss_rpl) /* DPL != RPL */
3396 return false;
3397 if (!ss.present)
3398 return false;
3399
3400 return true;
3401}
3402
3403static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3404{
3405 struct kvm_segment var;
3406 unsigned int rpl;
3407
3408 vmx_get_segment(vcpu, &var, seg);
3409 rpl = var.selector & SELECTOR_RPL_MASK;
3410
1872a3f4
AK		 3411 if (var.unusable)
3412 return true;
648dfaa7
MG		 3413 if (!var.s)
3414 return false;
3415 if (!var.present)
3416 return false;
3417 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3418 if (var.dpl < rpl) /* DPL < RPL */
3419 return false;
3420 }
3421
3422 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3423 * rights flags
3424 */
3425 return true;
3426}
3427
3428static bool tr_valid(struct kvm_vcpu *vcpu)
3429{
3430 struct kvm_segment tr;
3431
3432 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3433
1872a3f4
AK		 3434 if (tr.unusable)
3435 return false;
648dfaa7
MG		 3436 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3437 return false;
1872a3f4 3438 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 3439 return false;
3440 if (!tr.present)
3441 return false;
3442
3443 return true;
3444}
3445
3446static bool ldtr_valid(struct kvm_vcpu *vcpu)
3447{
3448 struct kvm_segment ldtr;
3449
3450 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3451
1872a3f4
AK		 3452 if (ldtr.unusable)
3453 return true;
648dfaa7
MG		 3454 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3455 return false;
3456 if (ldtr.type != 2)
3457 return false;
3458 if (!ldtr.present)
3459 return false;
3460
3461 return true;
3462}
3463
3464static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3465{
3466 struct kvm_segment cs, ss;
3467
3468 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3469 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3470
3471 return ((cs.selector & SELECTOR_RPL_MASK) ==
3472 (ss.selector & SELECTOR_RPL_MASK));
3473}
3474
3475/*
3476 * Check if guest state is valid. Returns true if valid, false if
3477 * not.
3478 * We assume that registers are always usable
3479 */
3480static bool guest_state_valid(struct kvm_vcpu *vcpu)
3481{
3482 /* real mode guest state checks */
3eeb3288 3483 if (!is_protmode(vcpu)) {
648dfaa7
MG		 3484 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3485 return false;
3486 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3487 return false;
3488 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3489 return false;
3490 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3491 return false;
3492 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3493 return false;
3494 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3495 return false;
3496 } else {
3497 /* protected mode guest state checks */
3498 if (!cs_ss_rpl_check(vcpu))
3499 return false;
3500 if (!code_segment_valid(vcpu))
3501 return false;
3502 if (!stack_segment_valid(vcpu))
3503 return false;
3504 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3505 return false;
3506 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3507 return false;
3508 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3509 return false;
3510 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3511 return false;
3512 if (!tr_valid(vcpu))
3513 return false;
3514 if (!ldtr_valid(vcpu))
3515 return false;
3516 }
3517 /* TODO:
3518 * - Add checks on RIP
3519 * - Add checks on RFLAGS
3520 */
3521
3522 return true;
3523}
3524
d77c26fc 3525static int init_rmode_tss(struct kvm *kvm)
6aa8b732 3526{
40dcaa9f 3527 gfn_t fn;
195aefde 3528 u16 data = 0;
40dcaa9f 3529 int r, idx, ret = 0;
6aa8b732 3530
40dcaa9f
XG		 3531 idx = srcu_read_lock(&kvm->srcu);
3532 fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
195aefde
IE		 3533 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3534 if (r < 0)
10589a46 3535 goto out;
195aefde 3536 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 3537 r = kvm_write_guest_page(kvm, fn++, &data,
3538 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 3539 if (r < 0)
10589a46 3540 goto out;
195aefde
IE		 3541 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3542 if (r < 0)
10589a46 3543 goto out;
195aefde
IE		 3544 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3545 if (r < 0)
10589a46 3546 goto out;
195aefde 3547 data = ~0;
10589a46
MT		 3548 r = kvm_write_guest_page(kvm, fn, &data,
3549 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3550 sizeof(u8));
195aefde 3551 if (r < 0)
10589a46
MT		 3552 goto out;
3553
3554 ret = 1;
3555out:
40dcaa9f 3556 srcu_read_unlock(&kvm->srcu, idx);
10589a46 3557 return ret;
6aa8b732
AK		 3558}
3559
b7ebfb05
SY		 3560static int init_rmode_identity_map(struct kvm *kvm)
3561{
40dcaa9f 3562 int i, idx, r, ret;
b7ebfb05
SY		 3563 pfn_t identity_map_pfn;
3564 u32 tmp;
3565
089d034e 3566 if (!enable_ept)
b7ebfb05
SY		 3567 return 1;
3568 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3569 printk(KERN_ERR "EPT: identity-mapping pagetable "
3570 "haven't been allocated!\n");
3571 return 0;
3572 }
3573 if (likely(kvm->arch.ept_identity_pagetable_done))
3574 return 1;
3575 ret = 0;
b927a3ce 3576 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
40dcaa9f 3577 idx = srcu_read_lock(&kvm->srcu);
b7ebfb05
SY		 3578 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3579 if (r < 0)
3580 goto out;
3581 /* Set up identity-mapping pagetable for EPT in real mode */
3582 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3583 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3584 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3585 r = kvm_write_guest_page(kvm, identity_map_pfn,
3586 &tmp, i * sizeof(tmp), sizeof(tmp));
3587 if (r < 0)
3588 goto out;
3589 }
3590 kvm->arch.ept_identity_pagetable_done = true;
3591 ret = 1;
3592out:
40dcaa9f 3593 srcu_read_unlock(&kvm->srcu, idx);
b7ebfb05
SY		 3594 return ret;
3595}
3596
6aa8b732
AK		 3597static void seg_setup(int seg)
3598{
3599 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 3600 unsigned int ar;
6aa8b732
AK		 3601
3602 vmcs_write16(sf->selector, 0);
3603 vmcs_writel(sf->base, 0);
3604 vmcs_write32(sf->limit, 0xffff);
3a624e29
NK		 3605 if (enable_unrestricted_guest) {
3606 ar = 0x93;
3607 if (seg == VCPU_SREG_CS)
3608 ar |= 0x08; /* code segment */
3609 } else
3610 ar = 0xf3;
3611
3612 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 3613}
3614
f78e0e2e
SY		 3615static int alloc_apic_access_page(struct kvm *kvm)
3616{
3617 struct kvm_userspace_memory_region kvm_userspace_mem;
3618 int r = 0;
3619
79fac95e 3620 mutex_lock(&kvm->slots_lock);
bfc6d222 3621 if (kvm->arch.apic_access_page)
f78e0e2e
SY		 3622 goto out;
3623 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3624 kvm_userspace_mem.flags = 0;
3625 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
3626 kvm_userspace_mem.memory_size = PAGE_SIZE;
3627 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
3628 if (r)
3629 goto out;
72dc67a6 3630
bfc6d222 3631 kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
f78e0e2e 3632out:
79fac95e 3633 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY		 3634 return r;
3635}
3636
b7ebfb05
SY		 3637static int alloc_identity_pagetable(struct kvm *kvm)
3638{
3639 struct kvm_userspace_memory_region kvm_userspace_mem;
3640 int r = 0;
3641
79fac95e 3642 mutex_lock(&kvm->slots_lock);
b7ebfb05
SY		 3643 if (kvm->arch.ept_identity_pagetable)
3644 goto out;
3645 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
3646 kvm_userspace_mem.flags = 0;
b927a3ce
SY		 3647 kvm_userspace_mem.guest_phys_addr =
3648 kvm->arch.ept_identity_map_addr;
b7ebfb05
SY		 3649 kvm_userspace_mem.memory_size = PAGE_SIZE;
3650 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
3651 if (r)
3652 goto out;
3653
b7ebfb05 3654 kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
b927a3ce 3655 kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
b7ebfb05 3656out:
79fac95e 3657 mutex_unlock(&kvm->slots_lock);
b7ebfb05
SY		 3658 return r;
3659}
3660
2384d2b3
SY		 3661static void allocate_vpid(struct vcpu_vmx *vmx)
3662{
3663 int vpid;
3664
3665 vmx->vpid = 0;
919818ab 3666 if (!enable_vpid)
2384d2b3
SY		 3667 return;
3668 spin_lock(&vmx_vpid_lock);
3669 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3670 if (vpid < VMX_NR_VPIDS) {
3671 vmx->vpid = vpid;
3672 __set_bit(vpid, vmx_vpid_bitmap);
3673 }
3674 spin_unlock(&vmx_vpid_lock);
3675}
3676
cdbecfc3
LJ		 3677static void free_vpid(struct vcpu_vmx *vmx)
3678{
3679 if (!enable_vpid)
3680 return;
3681 spin_lock(&vmx_vpid_lock);
3682 if (vmx->vpid != 0)
3683 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3684 spin_unlock(&vmx_vpid_lock);
3685}
3686
5897297b 3687static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
25c5f225 3688{
3e7c73e9 3689 int f = sizeof(unsigned long);
25c5f225
SY		 3690
3691 if (!cpu_has_vmx_msr_bitmap())
3692 return;
3693
3694 /*
3695 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3696 * have the write-low and read-high bitmap offsets the wrong way round.
3697 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3698 */
25c5f225 3699 if (msr <= 0x1fff) {
3e7c73e9
AK		 3700 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
3701 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
25c5f225
SY		 3702 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3703 msr &= 0x1fff;
3e7c73e9
AK		 3704 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
3705 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
25c5f225 3706 }
25c5f225
SY		 3707}
3708
5897297b
AK		 3709static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
3710{
3711 if (!longmode_only)
3712 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
3713 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
3714}
3715
a3a8ff8e
NHE		 3716/*
3717 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
3718 * will not change in the lifetime of the guest.
3719 * Note that host-state that does change is set elsewhere. E.g., host-state
3720 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
3721 */
3722static void vmx_set_constant_host_state(void)
3723{
3724 u32 low32, high32;
3725 unsigned long tmpl;
3726 struct desc_ptr dt;
3727
3728 vmcs_writel(HOST_CR0, read_cr0() | X86_CR0_TS); /* 22.2.3 */
3729 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
3730 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
3731
3732 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
b2da15ac
AK		 3733#ifdef CONFIG_X86_64
3734 /*
3735 * Load null selectors, so we can avoid reloading them in
3736 * __vmx_load_host_state(), in case userspace uses the null selectors
3737 * too (the expected case).
3738 */
3739 vmcs_write16(HOST_DS_SELECTOR, 0);
3740 vmcs_write16(HOST_ES_SELECTOR, 0);
3741#else
a3a8ff8e
NHE		 3742 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3743 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
b2da15ac 3744#endif
a3a8ff8e
NHE		 3745 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3746 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
3747
3748 native_store_idt(&dt);
3749 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
3750
3751 asm("mov $.Lkvm_vmx_return, %0" : "=r"(tmpl));
3752 vmcs_writel(HOST_RIP, tmpl); /* 22.2.5 */
3753
3754 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
3755 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
3756 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
3757 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
3758
3759 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
3760 rdmsr(MSR_IA32_CR_PAT, low32, high32);
3761 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
3762 }
3763}
3764
bf8179a0
NHE		 3765static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
3766{
3767 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
3768 if (enable_ept)
3769 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
fe3ef05c
NHE		 3770 if (is_guest_mode(&vmx->vcpu))
3771 vmx->vcpu.arch.cr4_guest_owned_bits &=
3772 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
bf8179a0
NHE		 3773 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
3774}
3775
3776static u32 vmx_exec_control(struct vcpu_vmx *vmx)
3777{
3778 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
3779 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
3780 exec_control &= ~CPU_BASED_TPR_SHADOW;
3781#ifdef CONFIG_X86_64
3782 exec_control |= CPU_BASED_CR8_STORE_EXITING |
3783 CPU_BASED_CR8_LOAD_EXITING;
3784#endif
3785 }
3786 if (!enable_ept)
3787 exec_control |= CPU_BASED_CR3_STORE_EXITING |
3788 CPU_BASED_CR3_LOAD_EXITING |
3789 CPU_BASED_INVLPG_EXITING;
3790 return exec_control;
3791}
3792
3793static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
3794{
3795 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
3796 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
3797 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
3798 if (vmx->vpid == 0)
3799 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
3800 if (!enable_ept) {
3801 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
3802 enable_unrestricted_guest = 0;
3803 }
3804 if (!enable_unrestricted_guest)
3805 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
3806 if (!ple_gap)
3807 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
3808 return exec_control;
3809}
3810
ce88decf
XG		 3811static void ept_set_mmio_spte_mask(void)
3812{
3813 /*
3814 * EPT Misconfigurations can be generated if the value of bits 2:0
3815 * of an EPT paging-structure entry is 110b (write/execute).
3816 * Also, magic bits (0xffull << 49) is set to quickly identify mmio
3817 * spte.
3818 */
3819 kvm_mmu_set_mmio_spte_mask(0xffull << 49 | 0x6ull);
3820}
3821
6aa8b732
AK		 3822/*
3823 * Sets up the vmcs for emulated real mode.
3824 */
8b9cf98c 3825static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 3826{
2e4ce7f5 3827#ifdef CONFIG_X86_64
6aa8b732 3828 unsigned long a;
2e4ce7f5 3829#endif
6aa8b732 3830 int i;
6aa8b732 3831
6aa8b732 3832 /* I/O */
3e7c73e9
AK		 3833 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
3834 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 3835
25c5f225 3836 if (cpu_has_vmx_msr_bitmap())
5897297b 3837 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 3838
6aa8b732
AK		 3839 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
3840
6aa8b732 3841 /* Control */
1c3d14fe
YS		 3842 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
3843 vmcs_config.pin_based_exec_ctrl);
6e5d865c 3844
bf8179a0 3845 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
6aa8b732 3846
83ff3b9d 3847 if (cpu_has_secondary_exec_ctrls()) {
bf8179a0
NHE		 3848 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
3849 vmx_secondary_exec_control(vmx));
83ff3b9d 3850 }
f78e0e2e 3851
4b8d54f9
ZE		 3852 if (ple_gap) {
3853 vmcs_write32(PLE_GAP, ple_gap);
3854 vmcs_write32(PLE_WINDOW, ple_window);
3855 }
3856
c3707958
XG		 3857 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
3858 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
6aa8b732
AK		 3859 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
3860
9581d442
AK		 3861 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
3862 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
a3a8ff8e 3863 vmx_set_constant_host_state();
05b3e0c2 3864#ifdef CONFIG_X86_64
6aa8b732
AK		 3865 rdmsrl(MSR_FS_BASE, a);
3866 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
3867 rdmsrl(MSR_GS_BASE, a);
3868 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
3869#else
3870 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
3871 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
3872#endif
3873
2cc51560
ED		 3874 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
3875 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
61d2ef2c 3876 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2cc51560 3877 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
61d2ef2c 3878 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
6aa8b732 3879
468d472f 3880 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
a3a8ff8e
NHE		 3881 u32 msr_low, msr_high;
3882 u64 host_pat;
468d472f
SY		 3883 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
3884 host_pat = msr_low | ((u64) msr_high << 32);
3885 /* Write the default value follow host pat */
3886 vmcs_write64(GUEST_IA32_PAT, host_pat);
3887 /* Keep arch.pat sync with GUEST_IA32_PAT */
3888 vmx->vcpu.arch.pat = host_pat;
3889 }
3890
6aa8b732
AK		 3891 for (i = 0; i < NR_VMX_MSR; ++i) {
3892 u32 index = vmx_msr_index[i];
3893 u32 data_low, data_high;
a2fa3e9f 3894 int j = vmx->nmsrs;
6aa8b732
AK		 3895
3896 if (rdmsr_safe(index, &data_low, &data_high) < 0)
3897 continue;
432bd6cb
AK		 3898 if (wrmsr_safe(index, data_low, data_high) < 0)
3899 continue;
26bb0981
AK		 3900 vmx->guest_msrs[j].index = i;
3901 vmx->guest_msrs[j].data = 0;
d5696725 3902 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 3903 ++vmx->nmsrs;
6aa8b732 3904 }
6aa8b732 3905
1c3d14fe 3906 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 3907
3908 /* 22.2.1, 20.8.1 */
1c3d14fe
YS		 3909 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
3910
e00c8cf2 3911 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
bf8179a0 3912 set_cr4_guest_host_mask(vmx);
e00c8cf2 3913
99e3e30a 3914 kvm_write_tsc(&vmx->vcpu, 0);
f78e0e2e 3915
e00c8cf2
AK		 3916 return 0;
3917}
3918
3919static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
3920{
3921 struct vcpu_vmx *vmx = to_vmx(vcpu);
3922 u64 msr;
4b9d3a04 3923 int ret;
e00c8cf2 3924
5fdbf976 3925 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
e00c8cf2 3926
7ffd92c5 3927 vmx->rmode.vm86_active = 0;
e00c8cf2 3928
3b86cd99
JK		 3929 vmx->soft_vnmi_blocked = 0;
3930
ad312c7c 3931 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 3932 kvm_set_cr8(&vmx->vcpu, 0);
e00c8cf2 3933 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 3934 if (kvm_vcpu_is_bsp(&vmx->vcpu))
e00c8cf2
AK		 3935 msr |= MSR_IA32_APICBASE_BSP;
3936 kvm_set_apic_base(&vmx->vcpu, msr);
3937
10ab25cd
JK		 3938 ret = fx_init(&vmx->vcpu);
3939 if (ret != 0)
3940 goto out;
e00c8cf2 3941
2fb92db1
AK		 3942 vmx_segment_cache_clear(vmx);
3943
5706be0d 3944 seg_setup(VCPU_SREG_CS);
e00c8cf2
AK		 3945 /*
3946 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
3947 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
3948 */
c5af89b6 3949 if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
e00c8cf2
AK		 3950 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
3951 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
3952 } else {
ad312c7c
ZX		 3953 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
3954 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
e00c8cf2 3955 }
e00c8cf2
AK		 3956
3957 seg_setup(VCPU_SREG_DS);
3958 seg_setup(VCPU_SREG_ES);
3959 seg_setup(VCPU_SREG_FS);
3960 seg_setup(VCPU_SREG_GS);
3961 seg_setup(VCPU_SREG_SS);
3962
3963 vmcs_write16(GUEST_TR_SELECTOR, 0);
3964 vmcs_writel(GUEST_TR_BASE, 0);
3965 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
3966 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3967
3968 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
3969 vmcs_writel(GUEST_LDTR_BASE, 0);
3970 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
3971 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
3972
3973 vmcs_write32(GUEST_SYSENTER_CS, 0);
3974 vmcs_writel(GUEST_SYSENTER_ESP, 0);
3975 vmcs_writel(GUEST_SYSENTER_EIP, 0);
3976
3977 vmcs_writel(GUEST_RFLAGS, 0x02);
c5af89b6 3978 if (kvm_vcpu_is_bsp(&vmx->vcpu))
5fdbf976 3979 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 3980 else
5fdbf976
MT		 3981 kvm_rip_write(vcpu, 0);
3982 kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
e00c8cf2 3983
e00c8cf2
AK		 3984 vmcs_writel(GUEST_DR7, 0x400);
3985
3986 vmcs_writel(GUEST_GDTR_BASE, 0);
3987 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
3988
3989 vmcs_writel(GUEST_IDTR_BASE, 0);
3990 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
3991
443381a8 3992 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
e00c8cf2
AK		 3993 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
3994 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
3995
e00c8cf2
AK		 3996 /* Special registers */
3997 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
3998
3999 setup_msrs(vmx);
4000
6aa8b732
AK		 4001 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
4002
f78e0e2e
SY		 4003 if (cpu_has_vmx_tpr_shadow()) {
4004 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4005 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
4006 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
afc20184 4007 __pa(vmx->vcpu.arch.apic->regs));
f78e0e2e
SY		 4008 vmcs_write32(TPR_THRESHOLD, 0);
4009 }
4010
4011 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4012 vmcs_write64(APIC_ACCESS_ADDR,
bfc6d222 4013 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
6aa8b732 4014
2384d2b3
SY		 4015 if (vmx->vpid != 0)
4016 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4017
fa40052c 4018 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
7a4f5ad0 4019 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
4d4ec087 4020 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
7a4f5ad0 4021 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
8b9cf98c 4022 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 4023 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 4024 vmx_fpu_activate(&vmx->vcpu);
4025 update_exception_bitmap(&vmx->vcpu);
6aa8b732 4026
b9d762fa 4027 vpid_sync_context(vmx);
2384d2b3 4028
3200f405 4029 ret = 0;
6aa8b732 4030
a89a8fb9
MG		 4031 /* HACK: Don't enable emulation on guest boot/reset */
4032 vmx->emulation_required = 0;
4033
6aa8b732
AK		 4034out:
4035 return ret;
4036}
4037
b6f1250e
NHE		 4038/*
4039 * In nested virtualization, check if L1 asked to exit on external interrupts.
4040 * For most existing hypervisors, this will always return true.
4041 */
4042static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4043{
4044 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4045 PIN_BASED_EXT_INTR_MASK;
4046}
4047
3b86cd99
JK		 4048static void enable_irq_window(struct kvm_vcpu *vcpu)
4049{
4050 u32 cpu_based_vm_exec_control;
d6185f20
NHE		 4051 if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) {
4052 /*
4053 * We get here if vmx_interrupt_allowed() said we can't
4054 * inject to L1 now because L2 must run. Ask L2 to exit
4055 * right after entry, so we can inject to L1 more promptly.
b6f1250e 4056 */
d6185f20 4057 kvm_make_request(KVM_REQ_IMMEDIATE_EXIT, vcpu);
b6f1250e 4058 return;
d6185f20 4059 }
3b86cd99
JK		 4060
4061 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4062 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4063 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4064}
4065
4066static void enable_nmi_window(struct kvm_vcpu *vcpu)
4067{
4068 u32 cpu_based_vm_exec_control;
4069
4070 if (!cpu_has_virtual_nmis()) {
4071 enable_irq_window(vcpu);
4072 return;
4073 }
4074
30bd0c4c
AK		 4075 if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4076 enable_irq_window(vcpu);
4077 return;
4078 }
3b86cd99
JK		 4079 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4080 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4081 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4082}
4083
66fd3f7f 4084static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 4085{
9c8cba37 4086 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 4087 uint32_t intr;
4088 int irq = vcpu->arch.interrupt.nr;
9c8cba37 4089
229456fc 4090 trace_kvm_inj_virq(irq);
2714d1d3 4091
fa89a817 4092 ++vcpu->stat.irq_injections;
7ffd92c5 4093 if (vmx->rmode.vm86_active) {
71f9833b
SH		 4094 int inc_eip = 0;
4095 if (vcpu->arch.interrupt.soft)
4096 inc_eip = vcpu->arch.event_exit_inst_len;
4097 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
a92601bb 4098 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
85f455f7
ED		 4099 return;
4100 }
66fd3f7f
GN		 4101 intr = irq | INTR_INFO_VALID_MASK;
4102 if (vcpu->arch.interrupt.soft) {
4103 intr |= INTR_TYPE_SOFT_INTR;
4104 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4105 vmx->vcpu.arch.event_exit_inst_len);
4106 } else
4107 intr |= INTR_TYPE_EXT_INTR;
4108 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
85f455f7
ED		 4109}
4110
f08864b4
SY		 4111static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4112{
66a5a347
JK		 4113 struct vcpu_vmx *vmx = to_vmx(vcpu);
4114
0b6ac343
NHE		 4115 if (is_guest_mode(vcpu))
4116 return;
4117
3b86cd99
JK		 4118 if (!cpu_has_virtual_nmis()) {
4119 /*
4120 * Tracking the NMI-blocked state in software is built upon
4121 * finding the next open IRQ window. This, in turn, depends on
4122 * well-behaving guests: They have to keep IRQs disabled at
4123 * least as long as the NMI handler runs. Otherwise we may
4124 * cause NMI nesting, maybe breaking the guest. But as this is
4125 * highly unlikely, we can live with the residual risk.
4126 */
4127 vmx->soft_vnmi_blocked = 1;
4128 vmx->vnmi_blocked_time = 0;
4129 }
4130
487b391d 4131 ++vcpu->stat.nmi_injections;
9d58b931 4132 vmx->nmi_known_unmasked = false;
7ffd92c5 4133 if (vmx->rmode.vm86_active) {
71f9833b 4134 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
a92601bb 4135 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
66a5a347
JK		 4136 return;
4137 }
f08864b4
SY		 4138 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4139 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
f08864b4
SY		 4140}
4141
c4282df9 4142static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
33f089ca 4143{
3b86cd99 4144 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
c4282df9 4145 return 0;
33f089ca 4146
c4282df9 4147 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
30bd0c4c
AK		 4148 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4149 | GUEST_INTR_STATE_NMI));
33f089ca
JK		 4150}
4151
3cfc3092
JK		 4152static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4153{
4154 if (!cpu_has_virtual_nmis())
4155 return to_vmx(vcpu)->soft_vnmi_blocked;
9d58b931
AK		 4156 if (to_vmx(vcpu)->nmi_known_unmasked)
4157 return false;
c332c83a 4158 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3cfc3092
JK		 4159}
4160
4161static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4162{
4163 struct vcpu_vmx *vmx = to_vmx(vcpu);
4164
4165 if (!cpu_has_virtual_nmis()) {
4166 if (vmx->soft_vnmi_blocked != masked) {
4167 vmx->soft_vnmi_blocked = masked;
4168 vmx->vnmi_blocked_time = 0;
4169 }
4170 } else {
9d58b931 4171 vmx->nmi_known_unmasked = !masked;
3cfc3092
JK		 4172 if (masked)
4173 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4174 GUEST_INTR_STATE_NMI);
4175 else
4176 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4177 GUEST_INTR_STATE_NMI);
4178 }
4179}
4180
78646121
GN		 4181static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4182{
b6f1250e 4183 if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) {
51cfe38e
NHE		 4184 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4185 if (to_vmx(vcpu)->nested.nested_run_pending ||
4186 (vmcs12->idt_vectoring_info_field &
4187 VECTORING_INFO_VALID_MASK))
b6f1250e
NHE		 4188 return 0;
4189 nested_vmx_vmexit(vcpu);
b6f1250e
NHE		 4190 vmcs12->vm_exit_reason = EXIT_REASON_EXTERNAL_INTERRUPT;
4191 vmcs12->vm_exit_intr_info = 0;
4192 /* fall through to normal code, but now in L1, not L2 */
4193 }
4194
c4282df9
GN		 4195 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4196 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4197 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 4198}
4199
cbc94022
IE		 4200static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4201{
4202 int ret;
4203 struct kvm_userspace_memory_region tss_mem = {
6fe63979 4204 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 4205 .guest_phys_addr = addr,
4206 .memory_size = PAGE_SIZE * 3,
4207 .flags = 0,
4208 };
4209
4210 ret = kvm_set_memory_region(kvm, &tss_mem, 0);
4211 if (ret)
4212 return ret;
bfc6d222 4213 kvm->arch.tss_addr = addr;
93ea5388
GN		 4214 if (!init_rmode_tss(kvm))
4215 return -ENOMEM;
4216
cbc94022
IE		 4217 return 0;
4218}
4219
6aa8b732
AK		 4220static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4221 int vec, u32 err_code)
4222{
b3f37707
NK		 4223 /*
4224 * Instruction with address size override prefix opcode 0x67
4225 * Cause the #SS fault with 0 error code in VM86 mode.
4226 */
4227 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
51d8b661 4228 if (emulate_instruction(vcpu, 0) == EMULATE_DONE)
6aa8b732 4229 return 1;
77ab6db0
JK		 4230 /*
4231 * Forward all other exceptions that are valid in real mode.
4232 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4233 * the required debugging infrastructure rework.
4234 */
4235 switch (vec) {
77ab6db0 4236 case DB_VECTOR:
d0bfb940
JK		 4237 if (vcpu->guest_debug &
4238 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4239 return 0;
4240 kvm_queue_exception(vcpu, vec);
4241 return 1;
77ab6db0 4242 case BP_VECTOR:
c573cd22
JK		 4243 /*
4244 * Update instruction length as we may reinject the exception
4245 * from user space while in guest debugging mode.
4246 */
4247 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4248 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940
JK		 4249 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4250 return 0;
4251 /* fall through */
4252 case DE_VECTOR:
77ab6db0
JK		 4253 case OF_VECTOR:
4254 case BR_VECTOR:
4255 case UD_VECTOR:
4256 case DF_VECTOR:
4257 case SS_VECTOR:
4258 case GP_VECTOR:
4259 case MF_VECTOR:
4260 kvm_queue_exception(vcpu, vec);
4261 return 1;
4262 }
6aa8b732
AK		 4263 return 0;
4264}
4265
a0861c02
AK		 4266/*
4267 * Trigger machine check on the host. We assume all the MSRs are already set up
4268 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4269 * We pass a fake environment to the machine check handler because we want
4270 * the guest to be always treated like user space, no matter what context
4271 * it used internally.
4272 */
4273static void kvm_machine_check(void)
4274{
4275#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4276 struct pt_regs regs = {
4277 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4278 .flags = X86_EFLAGS_IF,
4279 };
4280
4281 do_machine_check(&regs, 0);
4282#endif
4283}
4284
851ba692 4285static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK		 4286{
4287 /* already handled by vcpu_run */
4288 return 1;
4289}
4290
851ba692 4291static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 4292{
1155f76a 4293 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 4294 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 4295 u32 intr_info, ex_no, error_code;
42dbaa5a 4296 unsigned long cr2, rip, dr6;
6aa8b732
AK		 4297 u32 vect_info;
4298 enum emulation_result er;
4299
1155f76a 4300 vect_info = vmx->idt_vectoring_info;
88786475 4301 intr_info = vmx->exit_intr_info;
6aa8b732 4302
a0861c02 4303 if (is_machine_check(intr_info))
851ba692 4304 return handle_machine_check(vcpu);
a0861c02 4305
6aa8b732 4306 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
65ac7264
AK		 4307 !is_page_fault(intr_info)) {
4308 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4309 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4310 vcpu->run->internal.ndata = 2;
4311 vcpu->run->internal.data[0] = vect_info;
4312 vcpu->run->internal.data[1] = intr_info;
4313 return 0;
4314 }
6aa8b732 4315
e4a41889 4316 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 4317 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 4318
4319 if (is_no_device(intr_info)) {
5fd86fcf 4320 vmx_fpu_activate(vcpu);
2ab455cc
AL		 4321 return 1;
4322 }
4323
7aa81cc0 4324 if (is_invalid_opcode(intr_info)) {
51d8b661 4325 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
7aa81cc0 4326 if (er != EMULATE_DONE)
7ee5d940 4327 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 4328 return 1;
4329 }
4330
6aa8b732 4331 error_code = 0;
2e11384c 4332 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732
AK		 4333 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
4334 if (is_page_fault(intr_info)) {
1439442c 4335 /* EPT won't cause page fault directly */
cf3ace79 4336 BUG_ON(enable_ept);
6aa8b732 4337 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT		 4338 trace_kvm_page_fault(cr2, error_code);
4339
3298b75c 4340 if (kvm_event_needs_reinjection(vcpu))
577bdc49 4341 kvm_mmu_unprotect_page_virt(vcpu, cr2);
dc25e89e 4342 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
6aa8b732
AK		 4343 }
4344
7ffd92c5 4345 if (vmx->rmode.vm86_active &&
6aa8b732 4346 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
72d6e5a0 4347 error_code)) {
ad312c7c
ZX		 4348 if (vcpu->arch.halt_request) {
4349 vcpu->arch.halt_request = 0;
72d6e5a0
AK		 4350 return kvm_emulate_halt(vcpu);
4351 }
6aa8b732 4352 return 1;
72d6e5a0 4353 }
6aa8b732 4354
d0bfb940 4355 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
42dbaa5a
JK		 4356 switch (ex_no) {
4357 case DB_VECTOR:
4358 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4359 if (!(vcpu->guest_debug &
4360 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4361 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
4362 kvm_queue_exception(vcpu, DB_VECTOR);
4363 return 1;
4364 }
4365 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4366 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4367 /* fall through */
4368 case BP_VECTOR:
c573cd22
JK		 4369 /*
4370 * Update instruction length as we may reinject #BP from
4371 * user space while in guest debugging mode. Reading it for
4372 * #DB as well causes no harm, it is not used in that case.
4373 */
4374 vmx->vcpu.arch.event_exit_inst_len =
4375 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 4376 kvm_run->exit_reason = KVM_EXIT_DEBUG;
0a434bb2 4377 rip = kvm_rip_read(vcpu);
d0bfb940
JK		 4378 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4379 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 4380 break;
4381 default:
d0bfb940
JK		 4382 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4383 kvm_run->ex.exception = ex_no;
4384 kvm_run->ex.error_code = error_code;
42dbaa5a 4385 break;
6aa8b732 4386 }
6aa8b732
AK		 4387 return 0;
4388}
4389
851ba692 4390static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 4391{
1165f5fe 4392 ++vcpu->stat.irq_exits;
6aa8b732
AK		 4393 return 1;
4394}
4395
851ba692 4396static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 4397{
851ba692 4398 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK		 4399 return 0;
4400}
6aa8b732 4401
851ba692 4402static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 4403{
bfdaab09 4404 unsigned long exit_qualification;
34c33d16 4405 int size, in, string;
039576c0 4406 unsigned port;
6aa8b732 4407
bfdaab09 4408 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 4409 string = (exit_qualification & 16) != 0;
cf8f70bf 4410 in = (exit_qualification & 8) != 0;
e70669ab 4411
cf8f70bf 4412 ++vcpu->stat.io_exits;
e70669ab 4413
cf8f70bf 4414 if (string || in)
51d8b661 4415 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
e70669ab 4416
cf8f70bf
GN		 4417 port = exit_qualification >> 16;
4418 size = (exit_qualification & 7) + 1;
e93f36bc 4419 skip_emulated_instruction(vcpu);
cf8f70bf
GN		 4420
4421 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 4422}
4423
102d8325
IM		 4424static void
4425vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4426{
4427 /*
4428 * Patch in the VMCALL instruction:
4429 */
4430 hypercall[0] = 0x0f;
4431 hypercall[1] = 0x01;
4432 hypercall[2] = 0xc1;
102d8325
IM		 4433}
4434
eeadf9e7
NHE		 4435/* called to set cr0 as approriate for a mov-to-cr0 exit. */
4436static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4437{
4438 if (to_vmx(vcpu)->nested.vmxon &&
4439 ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
4440 return 1;
4441
4442 if (is_guest_mode(vcpu)) {
4443 /*
4444 * We get here when L2 changed cr0 in a way that did not change
4445 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4446 * but did change L0 shadowed bits. This can currently happen
4447 * with the TS bit: L0 may want to leave TS on (for lazy fpu
4448 * loading) while pretending to allow the guest to change it.
4449 */
4450 if (kvm_set_cr0(vcpu, (val & vcpu->arch.cr0_guest_owned_bits) |
4451 (vcpu->arch.cr0 & ~vcpu->arch.cr0_guest_owned_bits)))
4452 return 1;
4453 vmcs_writel(CR0_READ_SHADOW, val);
4454 return 0;
4455 } else
4456 return kvm_set_cr0(vcpu, val);
4457}
4458
4459static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4460{
4461 if (is_guest_mode(vcpu)) {
4462 if (kvm_set_cr4(vcpu, (val & vcpu->arch.cr4_guest_owned_bits) |
4463 (vcpu->arch.cr4 & ~vcpu->arch.cr4_guest_owned_bits)))
4464 return 1;
4465 vmcs_writel(CR4_READ_SHADOW, val);
4466 return 0;
4467 } else
4468 return kvm_set_cr4(vcpu, val);
4469}
4470
4471/* called to set cr0 as approriate for clts instruction exit. */
4472static void handle_clts(struct kvm_vcpu *vcpu)
4473{
4474 if (is_guest_mode(vcpu)) {
4475 /*
4476 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
4477 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
4478 * just pretend it's off (also in arch.cr0 for fpu_activate).
4479 */
4480 vmcs_writel(CR0_READ_SHADOW,
4481 vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
4482 vcpu->arch.cr0 &= ~X86_CR0_TS;
4483 } else
4484 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4485}
4486
851ba692 4487static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 4488{
229456fc 4489 unsigned long exit_qualification, val;
6aa8b732
AK		 4490 int cr;
4491 int reg;
49a9b07e 4492 int err;
6aa8b732 4493
bfdaab09 4494 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 4495 cr = exit_qualification & 15;
4496 reg = (exit_qualification >> 8) & 15;
4497 switch ((exit_qualification >> 4) & 3) {
4498 case 0: /* mov to cr */
229456fc
MT		 4499 val = kvm_register_read(vcpu, reg);
4500 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 4501 switch (cr) {
4502 case 0:
eeadf9e7 4503 err = handle_set_cr0(vcpu, val);
db8fcefa 4504 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 4505 return 1;
4506 case 3:
2390218b 4507 err = kvm_set_cr3(vcpu, val);
db8fcefa 4508 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 4509 return 1;
4510 case 4:
eeadf9e7 4511 err = handle_set_cr4(vcpu, val);
db8fcefa 4512 kvm_complete_insn_gp(vcpu, err);
6aa8b732 4513 return 1;
0a5fff19
GN		 4514 case 8: {
4515 u8 cr8_prev = kvm_get_cr8(vcpu);
4516 u8 cr8 = kvm_register_read(vcpu, reg);
eea1cff9 4517 err = kvm_set_cr8(vcpu, cr8);
db8fcefa 4518 kvm_complete_insn_gp(vcpu, err);
0a5fff19
GN		 4519 if (irqchip_in_kernel(vcpu->kvm))
4520 return 1;
4521 if (cr8_prev <= cr8)
4522 return 1;
851ba692 4523 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 4524 return 0;
4525 }
6aa8b732
AK		 4526 };
4527 break;
25c4c276 4528 case 2: /* clts */
eeadf9e7 4529 handle_clts(vcpu);
4d4ec087 4530 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
25c4c276 4531 skip_emulated_instruction(vcpu);
6b52d186 4532 vmx_fpu_activate(vcpu);
25c4c276 4533 return 1;
6aa8b732
AK		 4534 case 1: /*mov from cr*/
4535 switch (cr) {
4536 case 3:
9f8fe504
AK		 4537 val = kvm_read_cr3(vcpu);
4538 kvm_register_write(vcpu, reg, val);
4539 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 4540 skip_emulated_instruction(vcpu);
4541 return 1;
4542 case 8:
229456fc
MT		 4543 val = kvm_get_cr8(vcpu);
4544 kvm_register_write(vcpu, reg, val);
4545 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 4546 skip_emulated_instruction(vcpu);
4547 return 1;
4548 }
4549 break;
4550 case 3: /* lmsw */
a1f83a74 4551 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 4552 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 4553 kvm_lmsw(vcpu, val);
6aa8b732
AK		 4554
4555 skip_emulated_instruction(vcpu);
4556 return 1;
4557 default:
4558 break;
4559 }
851ba692 4560 vcpu->run->exit_reason = 0;
a737f256 4561 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 4562 (int)(exit_qualification >> 4) & 3, cr);
4563 return 0;
4564}
4565
851ba692 4566static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 4567{
bfdaab09 4568 unsigned long exit_qualification;
6aa8b732
AK		 4569 int dr, reg;
4570
f2483415 4571 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK		 4572 if (!kvm_require_cpl(vcpu, 0))
4573 return 1;
42dbaa5a
JK		 4574 dr = vmcs_readl(GUEST_DR7);
4575 if (dr & DR7_GD) {
4576 /*
4577 * As the vm-exit takes precedence over the debug trap, we
4578 * need to emulate the latter, either for the host or the
4579 * guest debugging itself.
4580 */
4581 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692
AK		 4582 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
4583 vcpu->run->debug.arch.dr7 = dr;
4584 vcpu->run->debug.arch.pc =
42dbaa5a
JK		 4585 vmcs_readl(GUEST_CS_BASE) +
4586 vmcs_readl(GUEST_RIP);
851ba692
AK		 4587 vcpu->run->debug.arch.exception = DB_VECTOR;
4588 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 4589 return 0;
4590 } else {
4591 vcpu->arch.dr7 &= ~DR7_GD;
4592 vcpu->arch.dr6 |= DR6_BD;
4593 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
4594 kvm_queue_exception(vcpu, DB_VECTOR);
4595 return 1;
4596 }
4597 }
4598
bfdaab09 4599 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
42dbaa5a
JK		 4600 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
4601 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
4602 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079
GN		 4603 unsigned long val;
4604 if (!kvm_get_dr(vcpu, dr, &val))
4605 kvm_register_write(vcpu, reg, val);
4606 } else
4607 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
6aa8b732
AK		 4608 skip_emulated_instruction(vcpu);
4609 return 1;
4610}
4611
020df079
GN		 4612static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
4613{
4614 vmcs_writel(GUEST_DR7, val);
4615}
4616
851ba692 4617static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 4618{
06465c5a
AK		 4619 kvm_emulate_cpuid(vcpu);
4620 return 1;
6aa8b732
AK		 4621}
4622
851ba692 4623static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 4624{
ad312c7c 4625 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 4626 u64 data;
4627
4628 if (vmx_get_msr(vcpu, ecx, &data)) {
59200273 4629 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 4630 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 4631 return 1;
4632 }
4633
229456fc 4634 trace_kvm_msr_read(ecx, data);
2714d1d3 4635
6aa8b732 4636 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 4637 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
4638 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 4639 skip_emulated_instruction(vcpu);
4640 return 1;
4641}
4642
851ba692 4643static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 4644{
ad312c7c
ZX		 4645 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
4646 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
4647 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732
AK		 4648
4649 if (vmx_set_msr(vcpu, ecx, data) != 0) {
59200273 4650 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 4651 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 4652 return 1;
4653 }
4654
59200273 4655 trace_kvm_msr_write(ecx, data);
6aa8b732
AK		 4656 skip_emulated_instruction(vcpu);
4657 return 1;
4658}
4659
851ba692 4660static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c 4661{
3842d135 4662 kvm_make_request(KVM_REQ_EVENT, vcpu);
6e5d865c
YS		 4663 return 1;
4664}
4665
851ba692 4666static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 4667{
85f455f7
ED		 4668 u32 cpu_based_vm_exec_control;
4669
4670 /* clear pending irq */
4671 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4672 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
4673 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3 4674
3842d135
AK		 4675 kvm_make_request(KVM_REQ_EVENT, vcpu);
4676
a26bf12a 4677 ++vcpu->stat.irq_window_exits;
2714d1d3 4678
c1150d8c
DL		 4679 /*
4680 * If the user space waits to inject interrupts, exit as soon as
4681 * possible
4682 */
8061823a 4683 if (!irqchip_in_kernel(vcpu->kvm) &&
851ba692 4684 vcpu->run->request_interrupt_window &&
8061823a 4685 !kvm_cpu_has_interrupt(vcpu)) {
851ba692 4686 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
c1150d8c
DL		 4687 return 0;
4688 }
6aa8b732
AK		 4689 return 1;
4690}
4691
851ba692 4692static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732
AK		 4693{
4694 skip_emulated_instruction(vcpu);
d3bef15f 4695 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 4696}
4697
851ba692 4698static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 4699{
510043da 4700 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 4701 kvm_emulate_hypercall(vcpu);
4702 return 1;
c21415e8
IM		 4703}
4704
ec25d5e6
GN		 4705static int handle_invd(struct kvm_vcpu *vcpu)
4706{
51d8b661 4707 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
ec25d5e6
GN		 4708}
4709
851ba692 4710static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 4711{
f9c617f6 4712 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 4713
4714 kvm_mmu_invlpg(vcpu, exit_qualification);
4715 skip_emulated_instruction(vcpu);
4716 return 1;
4717}
4718
fee84b07
AK		 4719static int handle_rdpmc(struct kvm_vcpu *vcpu)
4720{
4721 int err;
4722
4723 err = kvm_rdpmc(vcpu);
4724 kvm_complete_insn_gp(vcpu, err);
4725
4726 return 1;
4727}
4728
851ba692 4729static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01
ED		 4730{
4731 skip_emulated_instruction(vcpu);
f5f48ee1 4732 kvm_emulate_wbinvd(vcpu);
e5edaa01
ED		 4733 return 1;
4734}
4735
2acf923e
DC		 4736static int handle_xsetbv(struct kvm_vcpu *vcpu)
4737{
4738 u64 new_bv = kvm_read_edx_eax(vcpu);
4739 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
4740
4741 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
4742 skip_emulated_instruction(vcpu);
4743 return 1;
4744}
4745
851ba692 4746static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 4747{
58fbbf26
KT		 4748 if (likely(fasteoi)) {
4749 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4750 int access_type, offset;
4751
4752 access_type = exit_qualification & APIC_ACCESS_TYPE;
4753 offset = exit_qualification & APIC_ACCESS_OFFSET;
4754 /*
4755 * Sane guest uses MOV to write EOI, with written value
4756 * not cared. So make a short-circuit here by avoiding
4757 * heavy instruction emulation.
4758 */
4759 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
4760 (offset == APIC_EOI)) {
4761 kvm_lapic_set_eoi(vcpu);
4762 skip_emulated_instruction(vcpu);
4763 return 1;
4764 }
4765 }
51d8b661 4766 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
f78e0e2e
SY		 4767}
4768
851ba692 4769static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 4770{
60637aac 4771 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 4772 unsigned long exit_qualification;
e269fb21
JK		 4773 bool has_error_code = false;
4774 u32 error_code = 0;
37817f29 4775 u16 tss_selector;
7f3d35fd 4776 int reason, type, idt_v, idt_index;
64a7ec06
GN		 4777
4778 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
7f3d35fd 4779 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
64a7ec06 4780 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 4781
4782 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4783
4784 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 4785 if (reason == TASK_SWITCH_GATE && idt_v) {
4786 switch (type) {
4787 case INTR_TYPE_NMI_INTR:
4788 vcpu->arch.nmi_injected = false;
654f06fc 4789 vmx_set_nmi_mask(vcpu, true);
64a7ec06
GN		 4790 break;
4791 case INTR_TYPE_EXT_INTR:
66fd3f7f 4792 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 4793 kvm_clear_interrupt_queue(vcpu);
4794 break;
4795 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK		 4796 if (vmx->idt_vectoring_info &
4797 VECTORING_INFO_DELIVER_CODE_MASK) {
4798 has_error_code = true;
4799 error_code =
4800 vmcs_read32(IDT_VECTORING_ERROR_CODE);
4801 }
4802 /* fall through */
64a7ec06
GN		 4803 case INTR_TYPE_SOFT_EXCEPTION:
4804 kvm_clear_exception_queue(vcpu);
4805 break;
4806 default:
4807 break;
4808 }
60637aac 4809 }
37817f29
IE		 4810 tss_selector = exit_qualification;
4811
64a7ec06
GN		 4812 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
4813 type != INTR_TYPE_EXT_INTR &&
4814 type != INTR_TYPE_NMI_INTR))
4815 skip_emulated_instruction(vcpu);
4816
7f3d35fd
KW		 4817 if (kvm_task_switch(vcpu, tss_selector,
4818 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
4819 has_error_code, error_code) == EMULATE_FAIL) {
acb54517
GN		 4820 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4821 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4822 vcpu->run->internal.ndata = 0;
42dbaa5a 4823 return 0;
acb54517 4824 }
42dbaa5a
JK		 4825
4826 /* clear all local breakpoint enable flags */
4827 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
4828
4829 /*
4830 * TODO: What about debug traps on tss switch?
4831 * Are we supposed to inject them and update dr6?
4832 */
4833
4834 return 1;
37817f29
IE		 4835}
4836
851ba692 4837static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 4838{
f9c617f6 4839 unsigned long exit_qualification;
1439442c 4840 gpa_t gpa;
1439442c 4841 int gla_validity;
1439442c 4842
f9c617f6 4843 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c
SY		 4844
4845 if (exit_qualification & (1 << 6)) {
4846 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
7f582ab6 4847 return -EINVAL;
1439442c
SY		 4848 }
4849
4850 gla_validity = (exit_qualification >> 7) & 0x3;
4851 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
4852 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
4853 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
4854 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 4855 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 4856 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
4857 (long unsigned int)exit_qualification);
851ba692
AK		 4858 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4859 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
596ae895 4860 return 0;
1439442c
SY		 4861 }
4862
4863 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 4864 trace_kvm_page_fault(gpa, exit_qualification);
dc25e89e 4865 return kvm_mmu_page_fault(vcpu, gpa, exit_qualification & 0x3, NULL, 0);
1439442c
SY		 4866}
4867
68f89400
MT		 4868static u64 ept_rsvd_mask(u64 spte, int level)
4869{
4870 int i;
4871 u64 mask = 0;
4872
4873 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
4874 mask |= (1ULL << i);
4875
4876 if (level > 2)
4877 /* bits 7:3 reserved */
4878 mask |= 0xf8;
4879 else if (level == 2) {
4880 if (spte & (1ULL << 7))
4881 /* 2MB ref, bits 20:12 reserved */
4882 mask |= 0x1ff000;
4883 else
4884 /* bits 6:3 reserved */
4885 mask |= 0x78;
4886 }
4887
4888 return mask;
4889}
4890
4891static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
4892 int level)
4893{
4894 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
4895
4896 /* 010b (write-only) */
4897 WARN_ON((spte & 0x7) == 0x2);
4898
4899 /* 110b (write/execute) */
4900 WARN_ON((spte & 0x7) == 0x6);
4901
4902 /* 100b (execute-only) and value not supported by logical processor */
4903 if (!cpu_has_vmx_ept_execute_only())
4904 WARN_ON((spte & 0x7) == 0x4);
4905
4906 /* not 000b */
4907 if ((spte & 0x7)) {
4908 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
4909
4910 if (rsvd_bits != 0) {
4911 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
4912 __func__, rsvd_bits);
4913 WARN_ON(1);
4914 }
4915
4916 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
4917 u64 ept_mem_type = (spte & 0x38) >> 3;
4918
4919 if (ept_mem_type == 2 || ept_mem_type == 3 ||
4920 ept_mem_type == 7) {
4921 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
4922 __func__, ept_mem_type);
4923 WARN_ON(1);
4924 }
4925 }
4926 }
4927}
4928
851ba692 4929static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400
MT		 4930{
4931 u64 sptes[4];
ce88decf 4932 int nr_sptes, i, ret;
68f89400
MT		 4933 gpa_t gpa;
4934
4935 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
4936
ce88decf
XG		 4937 ret = handle_mmio_page_fault_common(vcpu, gpa, true);
4938 if (likely(ret == 1))
4939 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
4940 EMULATE_DONE;
4941 if (unlikely(!ret))
4942 return 1;
4943
4944 /* It is the real ept misconfig */
68f89400
MT		 4945 printk(KERN_ERR "EPT: Misconfiguration.\n");
4946 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
4947
4948 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
4949
4950 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
4951 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
4952
851ba692
AK		 4953 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4954 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT		 4955
4956 return 0;
4957}
4958
851ba692 4959static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4
SY		 4960{
4961 u32 cpu_based_vm_exec_control;
4962
4963 /* clear pending NMI */
4964 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4965 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
4966 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4967 ++vcpu->stat.nmi_window_exits;
3842d135 4968 kvm_make_request(KVM_REQ_EVENT, vcpu);
f08864b4
SY		 4969
4970 return 1;
4971}
4972
80ced186 4973static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 4974{
8b3079a5
AK		 4975 struct vcpu_vmx *vmx = to_vmx(vcpu);
4976 enum emulation_result err = EMULATE_DONE;
80ced186 4977 int ret = 1;
49e9d557
AK		 4978 u32 cpu_exec_ctrl;
4979 bool intr_window_requested;
b8405c18 4980 unsigned count = 130;
49e9d557
AK		 4981
4982 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4983 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
ea953ef0 4984
b8405c18 4985 while (!guest_state_valid(vcpu) && count-- != 0) {
49e9d557
AK		 4986 if (intr_window_requested
4987 && (kvm_get_rflags(&vmx->vcpu) & X86_EFLAGS_IF))
4988 return handle_interrupt_window(&vmx->vcpu);
4989
51d8b661 4990 err = emulate_instruction(vcpu, 0);
ea953ef0 4991
80ced186
MG		 4992 if (err == EMULATE_DO_MMIO) {
4993 ret = 0;
4994 goto out;
4995 }
1d5a4d9b 4996
6d77dbfc
GN		 4997 if (err != EMULATE_DONE)
4998 return 0;
ea953ef0
MG		 4999
5000 if (signal_pending(current))
80ced186 5001 goto out;
ea953ef0
MG		 5002 if (need_resched())
5003 schedule();
5004 }
5005
80ced186
MG		 5006 vmx->emulation_required = 0;
5007out:
5008 return ret;
ea953ef0
MG		 5009}
5010
4b8d54f9
ZE		 5011/*
5012 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5013 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5014 */
9fb41ba8 5015static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9
ZE		 5016{
5017 skip_emulated_instruction(vcpu);
5018 kvm_vcpu_on_spin(vcpu);
5019
5020 return 1;
5021}
5022
59708670
SY		 5023static int handle_invalid_op(struct kvm_vcpu *vcpu)
5024{
5025 kvm_queue_exception(vcpu, UD_VECTOR);
5026 return 1;
5027}
5028
ff2f6fe9
NHE		 5029/*
5030 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
5031 * We could reuse a single VMCS for all the L2 guests, but we also want the
5032 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
5033 * allows keeping them loaded on the processor, and in the future will allow
5034 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
5035 * every entry if they never change.
5036 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
5037 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
5038 *
5039 * The following functions allocate and free a vmcs02 in this pool.
5040 */
5041
5042/* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
5043static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
5044{
5045 struct vmcs02_list *item;
5046 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5047 if (item->vmptr == vmx->nested.current_vmptr) {
5048 list_move(&item->list, &vmx->nested.vmcs02_pool);
5049 return &item->vmcs02;
5050 }
5051
5052 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
5053 /* Recycle the least recently used VMCS. */
5054 item = list_entry(vmx->nested.vmcs02_pool.prev,
5055 struct vmcs02_list, list);
5056 item->vmptr = vmx->nested.current_vmptr;
5057 list_move(&item->list, &vmx->nested.vmcs02_pool);
5058 return &item->vmcs02;
5059 }
5060
5061 /* Create a new VMCS */
5062 item = (struct vmcs02_list *)
5063 kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
5064 if (!item)
5065 return NULL;
5066 item->vmcs02.vmcs = alloc_vmcs();
5067 if (!item->vmcs02.vmcs) {
5068 kfree(item);
5069 return NULL;
5070 }
5071 loaded_vmcs_init(&item->vmcs02);
5072 item->vmptr = vmx->nested.current_vmptr;
5073 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
5074 vmx->nested.vmcs02_num++;
5075 return &item->vmcs02;
5076}
5077
5078/* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
5079static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
5080{
5081 struct vmcs02_list *item;
5082 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5083 if (item->vmptr == vmptr) {
5084 free_loaded_vmcs(&item->vmcs02);
5085 list_del(&item->list);
5086 kfree(item);
5087 vmx->nested.vmcs02_num--;
5088 return;
5089 }
5090}
5091
5092/*
5093 * Free all VMCSs saved for this vcpu, except the one pointed by
5094 * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
5095 * currently used, if running L2), and vmcs01 when running L2.
5096 */
5097static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
5098{
5099 struct vmcs02_list *item, *n;
5100 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
5101 if (vmx->loaded_vmcs != &item->vmcs02)
5102 free_loaded_vmcs(&item->vmcs02);
5103 list_del(&item->list);
5104 kfree(item);
5105 }
5106 vmx->nested.vmcs02_num = 0;
5107
5108 if (vmx->loaded_vmcs != &vmx->vmcs01)
5109 free_loaded_vmcs(&vmx->vmcs01);
5110}
5111
ec378aee
NHE		 5112/*
5113 * Emulate the VMXON instruction.
5114 * Currently, we just remember that VMX is active, and do not save or even
5115 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
5116 * do not currently need to store anything in that guest-allocated memory
5117 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
5118 * argument is different from the VMXON pointer (which the spec says they do).
5119 */
5120static int handle_vmon(struct kvm_vcpu *vcpu)
5121{
5122 struct kvm_segment cs;
5123 struct vcpu_vmx *vmx = to_vmx(vcpu);
5124
5125 /* The Intel VMX Instruction Reference lists a bunch of bits that
5126 * are prerequisite to running VMXON, most notably cr4.VMXE must be
5127 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
5128 * Otherwise, we should fail with #UD. We test these now:
5129 */
5130 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
5131 !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
5132 (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
5133 kvm_queue_exception(vcpu, UD_VECTOR);
5134 return 1;
5135 }
5136
5137 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5138 if (is_long_mode(vcpu) && !cs.l) {
5139 kvm_queue_exception(vcpu, UD_VECTOR);
5140 return 1;
5141 }
5142
5143 if (vmx_get_cpl(vcpu)) {
5144 kvm_inject_gp(vcpu, 0);
5145 return 1;
5146 }
5147
ff2f6fe9
NHE		 5148 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
5149 vmx->nested.vmcs02_num = 0;
5150
ec378aee
NHE		 5151 vmx->nested.vmxon = true;
5152
5153 skip_emulated_instruction(vcpu);
5154 return 1;
5155}
5156
5157/*
5158 * Intel's VMX Instruction Reference specifies a common set of prerequisites
5159 * for running VMX instructions (except VMXON, whose prerequisites are
5160 * slightly different). It also specifies what exception to inject otherwise.
5161 */
5162static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
5163{
5164 struct kvm_segment cs;
5165 struct vcpu_vmx *vmx = to_vmx(vcpu);
5166
5167 if (!vmx->nested.vmxon) {
5168 kvm_queue_exception(vcpu, UD_VECTOR);
5169 return 0;
5170 }
5171
5172 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5173 if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
5174 (is_long_mode(vcpu) && !cs.l)) {
5175 kvm_queue_exception(vcpu, UD_VECTOR);
5176 return 0;
5177 }
5178
5179 if (vmx_get_cpl(vcpu)) {
5180 kvm_inject_gp(vcpu, 0);
5181 return 0;
5182 }
5183
5184 return 1;
5185}
5186
5187/*
5188 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
5189 * just stops using VMX.
5190 */
5191static void free_nested(struct vcpu_vmx *vmx)
5192{
5193 if (!vmx->nested.vmxon)
5194 return;
5195 vmx->nested.vmxon = false;
a9d30f33
NHE		 5196 if (vmx->nested.current_vmptr != -1ull) {
5197 kunmap(vmx->nested.current_vmcs12_page);
5198 nested_release_page(vmx->nested.current_vmcs12_page);
5199 vmx->nested.current_vmptr = -1ull;
5200 vmx->nested.current_vmcs12 = NULL;
5201 }
fe3ef05c
NHE		 5202 /* Unpin physical memory we referred to in current vmcs02 */
5203 if (vmx->nested.apic_access_page) {
5204 nested_release_page(vmx->nested.apic_access_page);
5205 vmx->nested.apic_access_page = 0;
5206 }
ff2f6fe9
NHE		 5207
5208 nested_free_all_saved_vmcss(vmx);
ec378aee
NHE		 5209}
5210
5211/* Emulate the VMXOFF instruction */
5212static int handle_vmoff(struct kvm_vcpu *vcpu)
5213{
5214 if (!nested_vmx_check_permission(vcpu))
5215 return 1;
5216 free_nested(to_vmx(vcpu));
5217 skip_emulated_instruction(vcpu);
5218 return 1;
5219}
5220
064aea77
NHE		 5221/*
5222 * Decode the memory-address operand of a vmx instruction, as recorded on an
5223 * exit caused by such an instruction (run by a guest hypervisor).
5224 * On success, returns 0. When the operand is invalid, returns 1 and throws
5225 * #UD or #GP.
5226 */
5227static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
5228 unsigned long exit_qualification,
5229 u32 vmx_instruction_info, gva_t *ret)
5230{
5231 /*
5232 * According to Vol. 3B, "Information for VM Exits Due to Instruction
5233 * Execution", on an exit, vmx_instruction_info holds most of the
5234 * addressing components of the operand. Only the displacement part
5235 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5236 * For how an actual address is calculated from all these components,
5237 * refer to Vol. 1, "Operand Addressing".
5238 */
5239 int scaling = vmx_instruction_info & 3;
5240 int addr_size = (vmx_instruction_info >> 7) & 7;
5241 bool is_reg = vmx_instruction_info & (1u << 10);
5242 int seg_reg = (vmx_instruction_info >> 15) & 7;
5243 int index_reg = (vmx_instruction_info >> 18) & 0xf;
5244 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
5245 int base_reg = (vmx_instruction_info >> 23) & 0xf;
5246 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
5247
5248 if (is_reg) {
5249 kvm_queue_exception(vcpu, UD_VECTOR);
5250 return 1;
5251 }
5252
5253 /* Addr = segment_base + offset */
5254 /* offset = base + [index * scale] + displacement */
5255 *ret = vmx_get_segment_base(vcpu, seg_reg);
5256 if (base_is_valid)
5257 *ret += kvm_register_read(vcpu, base_reg);
5258 if (index_is_valid)
5259 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
5260 *ret += exit_qualification; /* holds the displacement */
5261
5262 if (addr_size == 1) /* 32 bit */
5263 *ret &= 0xffffffff;
5264
5265 /*
5266 * TODO: throw #GP (and return 1) in various cases that the VM*
5267 * instructions require it - e.g., offset beyond segment limit,
5268 * unusable or unreadable/unwritable segment, non-canonical 64-bit
5269 * address, and so on. Currently these are not checked.
5270 */
5271 return 0;
5272}
5273
0140caea
NHE		 5274/*
5275 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5276 * set the success or error code of an emulated VMX instruction, as specified
5277 * by Vol 2B, VMX Instruction Reference, "Conventions".
5278 */
5279static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
5280{
5281 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
5282 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5283 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
5284}
5285
5286static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
5287{
5288 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5289 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
5290 X86_EFLAGS_SF | X86_EFLAGS_OF))
5291 | X86_EFLAGS_CF);
5292}
5293
5294static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
5295 u32 vm_instruction_error)
5296{
5297 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
5298 /*
5299 * failValid writes the error number to the current VMCS, which
5300 * can't be done there isn't a current VMCS.
5301 */
5302 nested_vmx_failInvalid(vcpu);
5303 return;
5304 }
5305 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5306 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5307 X86_EFLAGS_SF | X86_EFLAGS_OF))
5308 | X86_EFLAGS_ZF);
5309 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
5310}
5311
27d6c865
NHE		 5312/* Emulate the VMCLEAR instruction */
5313static int handle_vmclear(struct kvm_vcpu *vcpu)
5314{
5315 struct vcpu_vmx *vmx = to_vmx(vcpu);
5316 gva_t gva;
5317 gpa_t vmptr;
5318 struct vmcs12 *vmcs12;
5319 struct page *page;
5320 struct x86_exception e;
5321
5322 if (!nested_vmx_check_permission(vcpu))
5323 return 1;
5324
5325 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5326 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5327 return 1;
5328
5329 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5330 sizeof(vmptr), &e)) {
5331 kvm_inject_page_fault(vcpu, &e);
5332 return 1;
5333 }
5334
5335 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5336 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
5337 skip_emulated_instruction(vcpu);
5338 return 1;
5339 }
5340
5341 if (vmptr == vmx->nested.current_vmptr) {
5342 kunmap(vmx->nested.current_vmcs12_page);
5343 nested_release_page(vmx->nested.current_vmcs12_page);
5344 vmx->nested.current_vmptr = -1ull;
5345 vmx->nested.current_vmcs12 = NULL;
5346 }
5347
5348 page = nested_get_page(vcpu, vmptr);
5349 if (page == NULL) {
5350 /*
5351 * For accurate processor emulation, VMCLEAR beyond available
5352 * physical memory should do nothing at all. However, it is
5353 * possible that a nested vmx bug, not a guest hypervisor bug,
5354 * resulted in this case, so let's shut down before doing any
5355 * more damage:
5356 */
5357 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5358 return 1;
5359 }
5360 vmcs12 = kmap(page);
5361 vmcs12->launch_state = 0;
5362 kunmap(page);
5363 nested_release_page(page);
5364
5365 nested_free_vmcs02(vmx, vmptr);
5366
5367 skip_emulated_instruction(vcpu);
5368 nested_vmx_succeed(vcpu);
5369 return 1;
5370}
5371
cd232ad0
NHE		 5372static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
5373
5374/* Emulate the VMLAUNCH instruction */
5375static int handle_vmlaunch(struct kvm_vcpu *vcpu)
5376{
5377 return nested_vmx_run(vcpu, true);
5378}
5379
5380/* Emulate the VMRESUME instruction */
5381static int handle_vmresume(struct kvm_vcpu *vcpu)
5382{
5383
5384 return nested_vmx_run(vcpu, false);
5385}
5386
49f705c5
NHE		 5387enum vmcs_field_type {
5388 VMCS_FIELD_TYPE_U16 = 0,
5389 VMCS_FIELD_TYPE_U64 = 1,
5390 VMCS_FIELD_TYPE_U32 = 2,
5391 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
5392};
5393
5394static inline int vmcs_field_type(unsigned long field)
5395{
5396 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
5397 return VMCS_FIELD_TYPE_U32;
5398 return (field >> 13) & 0x3 ;
5399}
5400
5401static inline int vmcs_field_readonly(unsigned long field)
5402{
5403 return (((field >> 10) & 0x3) == 1);
5404}
5405
5406/*
5407 * Read a vmcs12 field. Since these can have varying lengths and we return
5408 * one type, we chose the biggest type (u64) and zero-extend the return value
5409 * to that size. Note that the caller, handle_vmread, might need to use only
5410 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
5411 * 64-bit fields are to be returned).
5412 */
5413static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
5414 unsigned long field, u64 *ret)
5415{
5416 short offset = vmcs_field_to_offset(field);
5417 char *p;
5418
5419 if (offset < 0)
5420 return 0;
5421
5422 p = ((char *)(get_vmcs12(vcpu))) + offset;
5423
5424 switch (vmcs_field_type(field)) {
5425 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5426 *ret = *((natural_width *)p);
5427 return 1;
5428 case VMCS_FIELD_TYPE_U16:
5429 *ret = *((u16 *)p);
5430 return 1;
5431 case VMCS_FIELD_TYPE_U32:
5432 *ret = *((u32 *)p);
5433 return 1;
5434 case VMCS_FIELD_TYPE_U64:
5435 *ret = *((u64 *)p);
5436 return 1;
5437 default:
5438 return 0; /* can never happen. */
5439 }
5440}
5441
5442/*
5443 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
5444 * used before) all generate the same failure when it is missing.
5445 */
5446static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
5447{
5448 struct vcpu_vmx *vmx = to_vmx(vcpu);
5449 if (vmx->nested.current_vmptr == -1ull) {
5450 nested_vmx_failInvalid(vcpu);
5451 skip_emulated_instruction(vcpu);
5452 return 0;
5453 }
5454 return 1;
5455}
5456
5457static int handle_vmread(struct kvm_vcpu *vcpu)
5458{
5459 unsigned long field;
5460 u64 field_value;
5461 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5462 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5463 gva_t gva = 0;
5464
5465 if (!nested_vmx_check_permission(vcpu) ||
5466 !nested_vmx_check_vmcs12(vcpu))
5467 return 1;
5468
5469 /* Decode instruction info and find the field to read */
5470 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5471 /* Read the field, zero-extended to a u64 field_value */
5472 if (!vmcs12_read_any(vcpu, field, &field_value)) {
5473 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5474 skip_emulated_instruction(vcpu);
5475 return 1;
5476 }
5477 /*
5478 * Now copy part of this value to register or memory, as requested.
5479 * Note that the number of bits actually copied is 32 or 64 depending
5480 * on the guest's mode (32 or 64 bit), not on the given field's length.
5481 */
5482 if (vmx_instruction_info & (1u << 10)) {
5483 kvm_register_write(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
5484 field_value);
5485 } else {
5486 if (get_vmx_mem_address(vcpu, exit_qualification,
5487 vmx_instruction_info, &gva))
5488 return 1;
5489 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
5490 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
5491 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
5492 }
5493
5494 nested_vmx_succeed(vcpu);
5495 skip_emulated_instruction(vcpu);
5496 return 1;
5497}
5498
5499
5500static int handle_vmwrite(struct kvm_vcpu *vcpu)
5501{
5502 unsigned long field;
5503 gva_t gva;
5504 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5505 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5506 char *p;
5507 short offset;
5508 /* The value to write might be 32 or 64 bits, depending on L1's long
5509 * mode, and eventually we need to write that into a field of several
5510 * possible lengths. The code below first zero-extends the value to 64
5511 * bit (field_value), and then copies only the approriate number of
5512 * bits into the vmcs12 field.
5513 */
5514 u64 field_value = 0;
5515 struct x86_exception e;
5516
5517 if (!nested_vmx_check_permission(vcpu) ||
5518 !nested_vmx_check_vmcs12(vcpu))
5519 return 1;
5520
5521 if (vmx_instruction_info & (1u << 10))
5522 field_value = kvm_register_read(vcpu,
5523 (((vmx_instruction_info) >> 3) & 0xf));
5524 else {
5525 if (get_vmx_mem_address(vcpu, exit_qualification,
5526 vmx_instruction_info, &gva))
5527 return 1;
5528 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
5529 &field_value, (is_long_mode(vcpu) ? 8 : 4), &e)) {
5530 kvm_inject_page_fault(vcpu, &e);
5531 return 1;
5532 }
5533 }
5534
5535
5536 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5537 if (vmcs_field_readonly(field)) {
5538 nested_vmx_failValid(vcpu,
5539 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
5540 skip_emulated_instruction(vcpu);
5541 return 1;
5542 }
5543
5544 offset = vmcs_field_to_offset(field);
5545 if (offset < 0) {
5546 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5547 skip_emulated_instruction(vcpu);
5548 return 1;
5549 }
5550 p = ((char *) get_vmcs12(vcpu)) + offset;
5551
5552 switch (vmcs_field_type(field)) {
5553 case VMCS_FIELD_TYPE_U16:
5554 *(u16 *)p = field_value;
5555 break;
5556 case VMCS_FIELD_TYPE_U32:
5557 *(u32 *)p = field_value;
5558 break;
5559 case VMCS_FIELD_TYPE_U64:
5560 *(u64 *)p = field_value;
5561 break;
5562 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5563 *(natural_width *)p = field_value;
5564 break;
5565 default:
5566 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5567 skip_emulated_instruction(vcpu);
5568 return 1;
5569 }
5570
5571 nested_vmx_succeed(vcpu);
5572 skip_emulated_instruction(vcpu);
5573 return 1;
5574}
5575
63846663
NHE		 5576/* Emulate the VMPTRLD instruction */
5577static int handle_vmptrld(struct kvm_vcpu *vcpu)
5578{
5579 struct vcpu_vmx *vmx = to_vmx(vcpu);
5580 gva_t gva;
5581 gpa_t vmptr;
5582 struct x86_exception e;
5583
5584 if (!nested_vmx_check_permission(vcpu))
5585 return 1;
5586
5587 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5588 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5589 return 1;
5590
5591 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5592 sizeof(vmptr), &e)) {
5593 kvm_inject_page_fault(vcpu, &e);
5594 return 1;
5595 }
5596
5597 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5598 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
5599 skip_emulated_instruction(vcpu);
5600 return 1;
5601 }
5602
5603 if (vmx->nested.current_vmptr != vmptr) {
5604 struct vmcs12 *new_vmcs12;
5605 struct page *page;
5606 page = nested_get_page(vcpu, vmptr);
5607 if (page == NULL) {
5608 nested_vmx_failInvalid(vcpu);
5609 skip_emulated_instruction(vcpu);
5610 return 1;
5611 }
5612 new_vmcs12 = kmap(page);
5613 if (new_vmcs12->revision_id != VMCS12_REVISION) {
5614 kunmap(page);
5615 nested_release_page_clean(page);
5616 nested_vmx_failValid(vcpu,
5617 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
5618 skip_emulated_instruction(vcpu);
5619 return 1;
5620 }
5621 if (vmx->nested.current_vmptr != -1ull) {
5622 kunmap(vmx->nested.current_vmcs12_page);
5623 nested_release_page(vmx->nested.current_vmcs12_page);
5624 }
5625
5626 vmx->nested.current_vmptr = vmptr;
5627 vmx->nested.current_vmcs12 = new_vmcs12;
5628 vmx->nested.current_vmcs12_page = page;
5629 }
5630
5631 nested_vmx_succeed(vcpu);
5632 skip_emulated_instruction(vcpu);
5633 return 1;
5634}
5635
6a4d7550
NHE		 5636/* Emulate the VMPTRST instruction */
5637static int handle_vmptrst(struct kvm_vcpu *vcpu)
5638{
5639 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5640 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5641 gva_t vmcs_gva;
5642 struct x86_exception e;
5643
5644 if (!nested_vmx_check_permission(vcpu))
5645 return 1;
5646
5647 if (get_vmx_mem_address(vcpu, exit_qualification,
5648 vmx_instruction_info, &vmcs_gva))
5649 return 1;
5650 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
5651 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
5652 (void *)&to_vmx(vcpu)->nested.current_vmptr,
5653 sizeof(u64), &e)) {
5654 kvm_inject_page_fault(vcpu, &e);
5655 return 1;
5656 }
5657 nested_vmx_succeed(vcpu);
5658 skip_emulated_instruction(vcpu);
5659 return 1;
5660}
5661
6aa8b732
AK		 5662/*
5663 * The exit handlers return 1 if the exit was handled fully and guest execution
5664 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
5665 * to be done to userspace and return 0.
5666 */
851ba692 5667static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK		 5668 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
5669 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 5670 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 5671 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 5672 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 5673 [EXIT_REASON_CR_ACCESS] = handle_cr,
5674 [EXIT_REASON_DR_ACCESS] = handle_dr,
5675 [EXIT_REASON_CPUID] = handle_cpuid,
5676 [EXIT_REASON_MSR_READ] = handle_rdmsr,
5677 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
5678 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
5679 [EXIT_REASON_HLT] = handle_halt,
ec25d5e6 5680 [EXIT_REASON_INVD] = handle_invd,
a7052897 5681 [EXIT_REASON_INVLPG] = handle_invlpg,
fee84b07 5682 [EXIT_REASON_RDPMC] = handle_rdpmc,
c21415e8 5683 [EXIT_REASON_VMCALL] = handle_vmcall,
27d6c865 5684 [EXIT_REASON_VMCLEAR] = handle_vmclear,
cd232ad0 5685 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
63846663 5686 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
6a4d7550 5687 [EXIT_REASON_VMPTRST] = handle_vmptrst,
49f705c5 5688 [EXIT_REASON_VMREAD] = handle_vmread,
cd232ad0 5689 [EXIT_REASON_VMRESUME] = handle_vmresume,
49f705c5 5690 [EXIT_REASON_VMWRITE] = handle_vmwrite,
ec378aee
NHE		 5691 [EXIT_REASON_VMOFF] = handle_vmoff,
5692 [EXIT_REASON_VMON] = handle_vmon,
f78e0e2e
SY		 5693 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
5694 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
e5edaa01 5695 [EXIT_REASON_WBINVD] = handle_wbinvd,
2acf923e 5696 [EXIT_REASON_XSETBV] = handle_xsetbv,
37817f29 5697 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 5698 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT		 5699 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
5700 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 5701 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
59708670
SY		 5702 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op,
5703 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op,
6aa8b732
AK		 5704};
5705
5706static const int kvm_vmx_max_exit_handlers =
50a3485c 5707 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732 5708
644d711a
NHE		 5709/*
5710 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
5711 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
5712 * disinterest in the current event (read or write a specific MSR) by using an
5713 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
5714 */
5715static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
5716 struct vmcs12 *vmcs12, u32 exit_reason)
5717{
5718 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
5719 gpa_t bitmap;
5720
5721 if (!nested_cpu_has(get_vmcs12(vcpu), CPU_BASED_USE_MSR_BITMAPS))
5722 return 1;
5723
5724 /*
5725 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
5726 * for the four combinations of read/write and low/high MSR numbers.
5727 * First we need to figure out which of the four to use:
5728 */
5729 bitmap = vmcs12->msr_bitmap;
5730 if (exit_reason == EXIT_REASON_MSR_WRITE)
5731 bitmap += 2048;
5732 if (msr_index >= 0xc0000000) {
5733 msr_index -= 0xc0000000;
5734 bitmap += 1024;
5735 }
5736
5737 /* Then read the msr_index'th bit from this bitmap: */
5738 if (msr_index < 1024*8) {
5739 unsigned char b;
5740 kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1);
5741 return 1 & (b >> (msr_index & 7));
5742 } else
5743 return 1; /* let L1 handle the wrong parameter */
5744}
5745
5746/*
5747 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
5748 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
5749 * intercept (via guest_host_mask etc.) the current event.
5750 */
5751static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
5752 struct vmcs12 *vmcs12)
5753{
5754 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5755 int cr = exit_qualification & 15;
5756 int reg = (exit_qualification >> 8) & 15;
5757 unsigned long val = kvm_register_read(vcpu, reg);
5758
5759 switch ((exit_qualification >> 4) & 3) {
5760 case 0: /* mov to cr */
5761 switch (cr) {
5762 case 0:
5763 if (vmcs12->cr0_guest_host_mask &
5764 (val ^ vmcs12->cr0_read_shadow))
5765 return 1;
5766 break;
5767 case 3:
5768 if ((vmcs12->cr3_target_count >= 1 &&
5769 vmcs12->cr3_target_value0 == val) ||
5770 (vmcs12->cr3_target_count >= 2 &&
5771 vmcs12->cr3_target_value1 == val) ||
5772 (vmcs12->cr3_target_count >= 3 &&
5773 vmcs12->cr3_target_value2 == val) ||
5774 (vmcs12->cr3_target_count >= 4 &&
5775 vmcs12->cr3_target_value3 == val))
5776 return 0;
5777 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
5778 return 1;
5779 break;
5780 case 4:
5781 if (vmcs12->cr4_guest_host_mask &
5782 (vmcs12->cr4_read_shadow ^ val))
5783 return 1;
5784 break;
5785 case 8:
5786 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
5787 return 1;
5788 break;
5789 }
5790 break;
5791 case 2: /* clts */
5792 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
5793 (vmcs12->cr0_read_shadow & X86_CR0_TS))
5794 return 1;
5795 break;
5796 case 1: /* mov from cr */
5797 switch (cr) {
5798 case 3:
5799 if (vmcs12->cpu_based_vm_exec_control &
5800 CPU_BASED_CR3_STORE_EXITING)
5801 return 1;
5802 break;
5803 case 8:
5804 if (vmcs12->cpu_based_vm_exec_control &
5805 CPU_BASED_CR8_STORE_EXITING)
5806 return 1;
5807 break;
5808 }
5809 break;
5810 case 3: /* lmsw */
5811 /*
5812 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
5813 * cr0. Other attempted changes are ignored, with no exit.
5814 */
5815 if (vmcs12->cr0_guest_host_mask & 0xe &
5816 (val ^ vmcs12->cr0_read_shadow))
5817 return 1;
5818 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
5819 !(vmcs12->cr0_read_shadow & 0x1) &&
5820 (val & 0x1))
5821 return 1;
5822 break;
5823 }
5824 return 0;
5825}
5826
5827/*
5828 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
5829 * should handle it ourselves in L0 (and then continue L2). Only call this
5830 * when in is_guest_mode (L2).
5831 */
5832static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
5833{
5834 u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
5835 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
5836 struct vcpu_vmx *vmx = to_vmx(vcpu);
5837 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5838
5839 if (vmx->nested.nested_run_pending)
5840 return 0;
5841
5842 if (unlikely(vmx->fail)) {
bd80158a
JK		 5843 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
5844 vmcs_read32(VM_INSTRUCTION_ERROR));
644d711a
NHE		 5845 return 1;
5846 }
5847
5848 switch (exit_reason) {
5849 case EXIT_REASON_EXCEPTION_NMI:
5850 if (!is_exception(intr_info))
5851 return 0;
5852 else if (is_page_fault(intr_info))
5853 return enable_ept;
5854 return vmcs12->exception_bitmap &
5855 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
5856 case EXIT_REASON_EXTERNAL_INTERRUPT:
5857 return 0;
5858 case EXIT_REASON_TRIPLE_FAULT:
5859 return 1;
5860 case EXIT_REASON_PENDING_INTERRUPT:
5861 case EXIT_REASON_NMI_WINDOW:
5862 /*
5863 * prepare_vmcs02() set the CPU_BASED_VIRTUAL_INTR_PENDING bit
5864 * (aka Interrupt Window Exiting) only when L1 turned it on,
5865 * so if we got a PENDING_INTERRUPT exit, this must be for L1.
5866 * Same for NMI Window Exiting.
5867 */
5868 return 1;
5869 case EXIT_REASON_TASK_SWITCH:
5870 return 1;
5871 case EXIT_REASON_CPUID:
5872 return 1;
5873 case EXIT_REASON_HLT:
5874 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
5875 case EXIT_REASON_INVD:
5876 return 1;
5877 case EXIT_REASON_INVLPG:
5878 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
5879 case EXIT_REASON_RDPMC:
5880 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
5881 case EXIT_REASON_RDTSC:
5882 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
5883 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
5884 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
5885 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
5886 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
5887 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
5888 /*
5889 * VMX instructions trap unconditionally. This allows L1 to
5890 * emulate them for its L2 guest, i.e., allows 3-level nesting!
5891 */
5892 return 1;
5893 case EXIT_REASON_CR_ACCESS:
5894 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
5895 case EXIT_REASON_DR_ACCESS:
5896 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
5897 case EXIT_REASON_IO_INSTRUCTION:
5898 /* TODO: support IO bitmaps */
5899 return 1;
5900 case EXIT_REASON_MSR_READ:
5901 case EXIT_REASON_MSR_WRITE:
5902 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
5903 case EXIT_REASON_INVALID_STATE:
5904 return 1;
5905 case EXIT_REASON_MWAIT_INSTRUCTION:
5906 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
5907 case EXIT_REASON_MONITOR_INSTRUCTION:
5908 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
5909 case EXIT_REASON_PAUSE_INSTRUCTION:
5910 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
5911 nested_cpu_has2(vmcs12,
5912 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
5913 case EXIT_REASON_MCE_DURING_VMENTRY:
5914 return 0;
5915 case EXIT_REASON_TPR_BELOW_THRESHOLD:
5916 return 1;
5917 case EXIT_REASON_APIC_ACCESS:
5918 return nested_cpu_has2(vmcs12,
5919 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
5920 case EXIT_REASON_EPT_VIOLATION:
5921 case EXIT_REASON_EPT_MISCONFIG:
5922 return 0;
5923 case EXIT_REASON_WBINVD:
5924 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
5925 case EXIT_REASON_XSETBV:
5926 return 1;
5927 default:
5928 return 1;
5929 }
5930}
5931
586f9607
AK		 5932static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
5933{
5934 *info1 = vmcs_readl(EXIT_QUALIFICATION);
5935 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
5936}
5937
6aa8b732
AK		 5938/*
5939 * The guest has exited. See if we can fix it or if we need userspace
5940 * assistance.
5941 */
851ba692 5942static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 5943{
29bd8a78 5944 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 5945 u32 exit_reason = vmx->exit_reason;
1155f76a 5946 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 5947
80ced186
MG		 5948 /* If guest state is invalid, start emulating */
5949 if (vmx->emulation_required && emulate_invalid_guest_state)
5950 return handle_invalid_guest_state(vcpu);
1d5a4d9b 5951
b6f1250e
NHE		 5952 /*
5953 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
5954 * we did not inject a still-pending event to L1 now because of
5955 * nested_run_pending, we need to re-enable this bit.
5956 */
5957 if (vmx->nested.nested_run_pending)
5958 kvm_make_request(KVM_REQ_EVENT, vcpu);
5959
509c75ea
NHE		 5960 if (!is_guest_mode(vcpu) && (exit_reason == EXIT_REASON_VMLAUNCH ||
5961 exit_reason == EXIT_REASON_VMRESUME))
644d711a
NHE		 5962 vmx->nested.nested_run_pending = 1;
5963 else
5964 vmx->nested.nested_run_pending = 0;
5965
5966 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
5967 nested_vmx_vmexit(vcpu);
5968 return 1;
5969 }
5970
5120702e
MG		 5971 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
5972 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5973 vcpu->run->fail_entry.hardware_entry_failure_reason
5974 = exit_reason;
5975 return 0;
5976 }
5977
29bd8a78 5978 if (unlikely(vmx->fail)) {
851ba692
AK		 5979 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5980 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK		 5981 = vmcs_read32(VM_INSTRUCTION_ERROR);
5982 return 0;
5983 }
6aa8b732 5984
d77c26fc 5985 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 5986 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac
JK		 5987 exit_reason != EXIT_REASON_EPT_VIOLATION &&
5988 exit_reason != EXIT_REASON_TASK_SWITCH))
5989 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
5990 "(0x%x) and exit reason is 0x%x\n",
5991 __func__, vectoring_info, exit_reason);
3b86cd99 5992
644d711a
NHE		 5993 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
5994 !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
5995 get_vmcs12(vcpu), vcpu)))) {
c4282df9 5996 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 5997 vmx->soft_vnmi_blocked = 0;
3b86cd99 5998 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 5999 vcpu->arch.nmi_pending) {
3b86cd99
JK		 6000 /*
6001 * This CPU don't support us in finding the end of an
6002 * NMI-blocked window if the guest runs with IRQs
6003 * disabled. So we pull the trigger after 1 s of
6004 * futile waiting, but inform the user about this.
6005 */
6006 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
6007 "state on VCPU %d after 1 s timeout\n",
6008 __func__, vcpu->vcpu_id);
6009 vmx->soft_vnmi_blocked = 0;
3b86cd99 6010 }
3b86cd99
JK		 6011 }
6012
6aa8b732
AK		 6013 if (exit_reason < kvm_vmx_max_exit_handlers
6014 && kvm_vmx_exit_handlers[exit_reason])
851ba692 6015 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 6016 else {
851ba692
AK		 6017 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6018 vcpu->run->hw.hardware_exit_reason = exit_reason;
6aa8b732
AK		 6019 }
6020 return 0;
6021}
6022
95ba8273 6023static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 6024{
95ba8273 6025 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 6026 vmcs_write32(TPR_THRESHOLD, 0);
6027 return;
6028 }
6029
95ba8273 6030 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 6031}
6032
51aa01d1 6033static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
cf393f75 6034{
00eba012
AK		 6035 u32 exit_intr_info;
6036
6037 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
6038 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
6039 return;
6040
c5ca8e57 6041 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
00eba012 6042 exit_intr_info = vmx->exit_intr_info;
a0861c02
AK		 6043
6044 /* Handle machine checks before interrupts are enabled */
00eba012 6045 if (is_machine_check(exit_intr_info))
a0861c02
AK		 6046 kvm_machine_check();
6047
20f65983 6048 /* We need to handle NMIs before interrupts are enabled */
00eba012 6049 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
ff9d07a0
ZY		 6050 (exit_intr_info & INTR_INFO_VALID_MASK)) {
6051 kvm_before_handle_nmi(&vmx->vcpu);
20f65983 6052 asm("int $2");
ff9d07a0
ZY		 6053 kvm_after_handle_nmi(&vmx->vcpu);
6054 }
51aa01d1 6055}
20f65983 6056
51aa01d1
AK		 6057static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
6058{
c5ca8e57 6059 u32 exit_intr_info;
51aa01d1
AK		 6060 bool unblock_nmi;
6061 u8 vector;
6062 bool idtv_info_valid;
6063
6064 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
20f65983 6065
cf393f75 6066 if (cpu_has_virtual_nmis()) {
9d58b931
AK		 6067 if (vmx->nmi_known_unmasked)
6068 return;
c5ca8e57
AK		 6069 /*
6070 * Can't use vmx->exit_intr_info since we're not sure what
6071 * the exit reason is.
6072 */
6073 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
cf393f75
AK		 6074 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
6075 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6076 /*
7b4a25cb 6077 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 6078 * Re-set bit "block by NMI" before VM entry if vmexit caused by
6079 * a guest IRET fault.
7b4a25cb
GN		 6080 * SDM 3: 23.2.2 (September 2008)
6081 * Bit 12 is undefined in any of the following cases:
6082 * If the VM exit sets the valid bit in the IDT-vectoring
6083 * information field.
6084 * If the VM exit is due to a double fault.
cf393f75 6085 */
7b4a25cb
GN		 6086 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
6087 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 6088 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
6089 GUEST_INTR_STATE_NMI);
9d58b931
AK		 6090 else
6091 vmx->nmi_known_unmasked =
6092 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
6093 & GUEST_INTR_STATE_NMI);
3b86cd99
JK		 6094 } else if (unlikely(vmx->soft_vnmi_blocked))
6095 vmx->vnmi_blocked_time +=
6096 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
51aa01d1
AK		 6097}
6098
83422e17
AK		 6099static void __vmx_complete_interrupts(struct vcpu_vmx *vmx,
6100 u32 idt_vectoring_info,
6101 int instr_len_field,
6102 int error_code_field)
51aa01d1 6103{
51aa01d1
AK		 6104 u8 vector;
6105 int type;
6106 bool idtv_info_valid;
6107
6108 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
668f612f 6109
37b96e98
GN		 6110 vmx->vcpu.arch.nmi_injected = false;
6111 kvm_clear_exception_queue(&vmx->vcpu);
6112 kvm_clear_interrupt_queue(&vmx->vcpu);
6113
6114 if (!idtv_info_valid)
6115 return;
6116
3842d135
AK		 6117 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6118
668f612f
AK		 6119 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
6120 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 6121
64a7ec06 6122 switch (type) {
37b96e98
GN		 6123 case INTR_TYPE_NMI_INTR:
6124 vmx->vcpu.arch.nmi_injected = true;
668f612f 6125 /*
7b4a25cb 6126 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 6127 * Clear bit "block by NMI" before VM entry if a NMI
6128 * delivery faulted.
668f612f 6129 */
654f06fc 6130 vmx_set_nmi_mask(&vmx->vcpu, false);
37b96e98 6131 break;
37b96e98 6132 case INTR_TYPE_SOFT_EXCEPTION:
66fd3f7f 6133 vmx->vcpu.arch.event_exit_inst_len =
83422e17 6134 vmcs_read32(instr_len_field);
66fd3f7f
GN		 6135 /* fall through */
6136 case INTR_TYPE_HARD_EXCEPTION:
35920a35 6137 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
83422e17 6138 u32 err = vmcs_read32(error_code_field);
37b96e98 6139 kvm_queue_exception_e(&vmx->vcpu, vector, err);
35920a35
AK		 6140 } else
6141 kvm_queue_exception(&vmx->vcpu, vector);
37b96e98 6142 break;
66fd3f7f
GN		 6143 case INTR_TYPE_SOFT_INTR:
6144 vmx->vcpu.arch.event_exit_inst_len =
83422e17 6145 vmcs_read32(instr_len_field);
66fd3f7f 6146 /* fall through */
37b96e98 6147 case INTR_TYPE_EXT_INTR:
66fd3f7f
GN		 6148 kvm_queue_interrupt(&vmx->vcpu, vector,
6149 type == INTR_TYPE_SOFT_INTR);
37b96e98
GN		 6150 break;
6151 default:
6152 break;
f7d9238f 6153 }
cf393f75
AK		 6154}
6155
83422e17
AK		 6156static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
6157{
66c78ae4
NHE		 6158 if (is_guest_mode(&vmx->vcpu))
6159 return;
83422e17
AK		 6160 __vmx_complete_interrupts(vmx, vmx->idt_vectoring_info,
6161 VM_EXIT_INSTRUCTION_LEN,
6162 IDT_VECTORING_ERROR_CODE);
6163}
6164
b463a6f7
AK		 6165static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
6166{
66c78ae4
NHE		 6167 if (is_guest_mode(vcpu))
6168 return;
b463a6f7
AK		 6169 __vmx_complete_interrupts(to_vmx(vcpu),
6170 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
6171 VM_ENTRY_INSTRUCTION_LEN,
6172 VM_ENTRY_EXCEPTION_ERROR_CODE);
6173
6174 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
6175}
6176
d7cd9796
GN		 6177static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
6178{
6179 int i, nr_msrs;
6180 struct perf_guest_switch_msr *msrs;
6181
6182 msrs = perf_guest_get_msrs(&nr_msrs);
6183
6184 if (!msrs)
6185 return;
6186
6187 for (i = 0; i < nr_msrs; i++)
6188 if (msrs[i].host == msrs[i].guest)
6189 clear_atomic_switch_msr(vmx, msrs[i].msr);
6190 else
6191 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
6192 msrs[i].host);
6193}
6194
c801949d
AK		 6195#ifdef CONFIG_X86_64
6196#define R "r"
6197#define Q "q"
6198#else
6199#define R "e"
6200#define Q "l"
6201#endif
6202
a3b5ba49 6203static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 6204{
a2fa3e9f 6205 struct vcpu_vmx *vmx = to_vmx(vcpu);
104f226b 6206
66c78ae4
NHE		 6207 if (is_guest_mode(vcpu) && !vmx->nested.nested_run_pending) {
6208 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6209 if (vmcs12->idt_vectoring_info_field &
6210 VECTORING_INFO_VALID_MASK) {
6211 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
6212 vmcs12->idt_vectoring_info_field);
6213 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
6214 vmcs12->vm_exit_instruction_len);
6215 if (vmcs12->idt_vectoring_info_field &
6216 VECTORING_INFO_DELIVER_CODE_MASK)
6217 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
6218 vmcs12->idt_vectoring_error_code);
6219 }
6220 }
6221
104f226b
AK		 6222 /* Record the guest's net vcpu time for enforced NMI injections. */
6223 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
6224 vmx->entry_time = ktime_get();
6225
6226 /* Don't enter VMX if guest state is invalid, let the exit handler
6227 start emulation until we arrive back to a valid state */
6228 if (vmx->emulation_required && emulate_invalid_guest_state)
6229 return;
6230
6231 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
6232 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
6233 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
6234 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
6235
6236 /* When single-stepping over STI and MOV SS, we must clear the
6237 * corresponding interruptibility bits in the guest state. Otherwise
6238 * vmentry fails as it then expects bit 14 (BS) in pending debug
6239 * exceptions being set, but that's not correct for the guest debugging
6240 * case. */
6241 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6242 vmx_set_interrupt_shadow(vcpu, 0);
6243
d7cd9796
GN		 6244 atomic_switch_perf_msrs(vmx);
6245
d462b819 6246 vmx->__launched = vmx->loaded_vmcs->launched;
104f226b 6247 asm(
6aa8b732 6248 /* Store host registers */
c801949d 6249 "push %%"R"dx; push %%"R"bp;"
40712fae 6250 "push %%"R"cx \n\t" /* placeholder for guest rcx */
c801949d 6251 "push %%"R"cx \n\t"
313dbd49
AK		 6252 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
6253 "je 1f \n\t"
6254 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
4ecac3fd 6255 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 6256 "1: \n\t"
d3edefc0
AK		 6257 /* Reload cr2 if changed */
6258 "mov %c[cr2](%0), %%"R"ax \n\t"
6259 "mov %%cr2, %%"R"dx \n\t"
6260 "cmp %%"R"ax, %%"R"dx \n\t"
6261 "je 2f \n\t"
6262 "mov %%"R"ax, %%cr2 \n\t"
6263 "2: \n\t"
6aa8b732 6264 /* Check if vmlaunch of vmresume is needed */
e08aa78a 6265 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 6266 /* Load guest registers. Don't clobber flags. */
c801949d
AK		 6267 "mov %c[rax](%0), %%"R"ax \n\t"
6268 "mov %c[rbx](%0), %%"R"bx \n\t"
6269 "mov %c[rdx](%0), %%"R"dx \n\t"
6270 "mov %c[rsi](%0), %%"R"si \n\t"
6271 "mov %c[rdi](%0), %%"R"di \n\t"
6272 "mov %c[rbp](%0), %%"R"bp \n\t"
05b3e0c2 6273#ifdef CONFIG_X86_64
e08aa78a
AK		 6274 "mov %c[r8](%0), %%r8 \n\t"
6275 "mov %c[r9](%0), %%r9 \n\t"
6276 "mov %c[r10](%0), %%r10 \n\t"
6277 "mov %c[r11](%0), %%r11 \n\t"
6278 "mov %c[r12](%0), %%r12 \n\t"
6279 "mov %c[r13](%0), %%r13 \n\t"
6280 "mov %c[r14](%0), %%r14 \n\t"
6281 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 6282#endif
c801949d
AK		 6283 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
6284
6aa8b732 6285 /* Enter guest mode */
cd2276a7 6286 "jne .Llaunched \n\t"
4ecac3fd 6287 __ex(ASM_VMX_VMLAUNCH) "\n\t"
cd2276a7 6288 "jmp .Lkvm_vmx_return \n\t"
4ecac3fd 6289 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
cd2276a7 6290 ".Lkvm_vmx_return: "
6aa8b732 6291 /* Save guest registers, load host registers, keep flags */
40712fae
AK		 6292 "mov %0, %c[wordsize](%%"R"sp) \n\t"
6293 "pop %0 \n\t"
c801949d
AK		 6294 "mov %%"R"ax, %c[rax](%0) \n\t"
6295 "mov %%"R"bx, %c[rbx](%0) \n\t"
1c696d0e 6296 "pop"Q" %c[rcx](%0) \n\t"
c801949d
AK		 6297 "mov %%"R"dx, %c[rdx](%0) \n\t"
6298 "mov %%"R"si, %c[rsi](%0) \n\t"
6299 "mov %%"R"di, %c[rdi](%0) \n\t"
6300 "mov %%"R"bp, %c[rbp](%0) \n\t"
05b3e0c2 6301#ifdef CONFIG_X86_64
e08aa78a
AK		 6302 "mov %%r8, %c[r8](%0) \n\t"
6303 "mov %%r9, %c[r9](%0) \n\t"
6304 "mov %%r10, %c[r10](%0) \n\t"
6305 "mov %%r11, %c[r11](%0) \n\t"
6306 "mov %%r12, %c[r12](%0) \n\t"
6307 "mov %%r13, %c[r13](%0) \n\t"
6308 "mov %%r14, %c[r14](%0) \n\t"
6309 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 6310#endif
c801949d
AK		 6311 "mov %%cr2, %%"R"ax \n\t"
6312 "mov %%"R"ax, %c[cr2](%0) \n\t"
6313
1c696d0e 6314 "pop %%"R"bp; pop %%"R"dx \n\t"
e08aa78a
AK		 6315 "setbe %c[fail](%0) \n\t"
6316 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
d462b819 6317 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
e08aa78a 6318 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 6319 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 6320 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
6321 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
6322 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
6323 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
6324 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
6325 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
6326 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 6327#ifdef CONFIG_X86_64
ad312c7c
ZX		 6328 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
6329 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
6330 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
6331 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
6332 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
6333 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
6334 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
6335 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 6336#endif
40712fae
AK		 6337 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
6338 [wordsize]"i"(sizeof(ulong))
c2036300 6339 : "cc", "memory"
07d6f555 6340 , R"ax", R"bx", R"di", R"si"
c2036300 6341#ifdef CONFIG_X86_64
c2036300
LV		 6342 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
6343#endif
6344 );
6aa8b732 6345
6de4f3ad 6346 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6de12732 6347 | (1 << VCPU_EXREG_RFLAGS)
69c73028 6348 | (1 << VCPU_EXREG_CPL)
aff48baa 6349 | (1 << VCPU_EXREG_PDPTR)
2fb92db1 6350 | (1 << VCPU_EXREG_SEGMENTS)
aff48baa 6351 | (1 << VCPU_EXREG_CR3));
5fdbf976
MT		 6352 vcpu->arch.regs_dirty = 0;
6353
1155f76a
AK		 6354 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
6355
66c78ae4
NHE		 6356 if (is_guest_mode(vcpu)) {
6357 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6358 vmcs12->idt_vectoring_info_field = vmx->idt_vectoring_info;
6359 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
6360 vmcs12->idt_vectoring_error_code =
6361 vmcs_read32(IDT_VECTORING_ERROR_CODE);
6362 vmcs12->vm_exit_instruction_len =
6363 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6364 }
6365 }
6366
d462b819 6367 vmx->loaded_vmcs->launched = 1;
1b6269db 6368
51aa01d1 6369 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
1e2b1dd7 6370 trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
51aa01d1
AK		 6371
6372 vmx_complete_atomic_exit(vmx);
6373 vmx_recover_nmi_blocking(vmx);
cf393f75 6374 vmx_complete_interrupts(vmx);
6aa8b732
AK		 6375}
6376
c801949d
AK		 6377#undef R
6378#undef Q
6379
6aa8b732
AK		 6380static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
6381{
fb3f0f51
RR		 6382 struct vcpu_vmx *vmx = to_vmx(vcpu);
6383
cdbecfc3 6384 free_vpid(vmx);
ec378aee 6385 free_nested(vmx);
d462b819 6386 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51
RR		 6387 kfree(vmx->guest_msrs);
6388 kvm_vcpu_uninit(vcpu);
a4770347 6389 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 6390}
6391
fb3f0f51 6392static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 6393{
fb3f0f51 6394 int err;
c16f862d 6395 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 6396 int cpu;
6aa8b732 6397
a2fa3e9f 6398 if (!vmx)
fb3f0f51
RR		 6399 return ERR_PTR(-ENOMEM);
6400
2384d2b3
SY		 6401 allocate_vpid(vmx);
6402
fb3f0f51
RR		 6403 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
6404 if (err)
6405 goto free_vcpu;
965b58a5 6406
a2fa3e9f 6407 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
be6d05cf 6408 err = -ENOMEM;
fb3f0f51 6409 if (!vmx->guest_msrs) {
fb3f0f51
RR		 6410 goto uninit_vcpu;
6411 }
965b58a5 6412
d462b819
NHE		 6413 vmx->loaded_vmcs = &vmx->vmcs01;
6414 vmx->loaded_vmcs->vmcs = alloc_vmcs();
6415 if (!vmx->loaded_vmcs->vmcs)
fb3f0f51 6416 goto free_msrs;
d462b819
NHE		 6417 if (!vmm_exclusive)
6418 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
6419 loaded_vmcs_init(vmx->loaded_vmcs);
6420 if (!vmm_exclusive)
6421 kvm_cpu_vmxoff();
a2fa3e9f 6422
15ad7146
AK		 6423 cpu = get_cpu();
6424 vmx_vcpu_load(&vmx->vcpu, cpu);
e48672fa 6425 vmx->vcpu.cpu = cpu;
8b9cf98c 6426 err = vmx_vcpu_setup(vmx);
fb3f0f51 6427 vmx_vcpu_put(&vmx->vcpu);
15ad7146 6428 put_cpu();
fb3f0f51
RR		 6429 if (err)
6430 goto free_vmcs;
5e4a0b3c 6431 if (vm_need_virtualize_apic_accesses(kvm))
be6d05cf
JK		 6432 err = alloc_apic_access_page(kvm);
6433 if (err)
5e4a0b3c 6434 goto free_vmcs;
fb3f0f51 6435
b927a3ce
SY		 6436 if (enable_ept) {
6437 if (!kvm->arch.ept_identity_map_addr)
6438 kvm->arch.ept_identity_map_addr =
6439 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
93ea5388 6440 err = -ENOMEM;
b7ebfb05
SY		 6441 if (alloc_identity_pagetable(kvm) != 0)
6442 goto free_vmcs;
93ea5388
GN		 6443 if (!init_rmode_identity_map(kvm))
6444 goto free_vmcs;
b927a3ce 6445 }
b7ebfb05 6446
a9d30f33
NHE		 6447 vmx->nested.current_vmptr = -1ull;
6448 vmx->nested.current_vmcs12 = NULL;
6449
fb3f0f51
RR		 6450 return &vmx->vcpu;
6451
6452free_vmcs:
5f3fbc34 6453 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51 6454free_msrs:
fb3f0f51
RR		 6455 kfree(vmx->guest_msrs);
6456uninit_vcpu:
6457 kvm_vcpu_uninit(&vmx->vcpu);
6458free_vcpu:
cdbecfc3 6459 free_vpid(vmx);
a4770347 6460 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 6461 return ERR_PTR(err);
6aa8b732
AK		 6462}
6463
002c7f7c
YS		 6464static void __init vmx_check_processor_compat(void *rtn)
6465{
6466 struct vmcs_config vmcs_conf;
6467
6468 *(int *)rtn = 0;
6469 if (setup_vmcs_config(&vmcs_conf) < 0)
6470 *(int *)rtn = -EIO;
6471 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
6472 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
6473 smp_processor_id());
6474 *(int *)rtn = -EIO;
6475 }
6476}
6477
67253af5
SY		 6478static int get_ept_level(void)
6479{
6480 return VMX_EPT_DEFAULT_GAW + 1;
6481}
6482
4b12f0de 6483static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 6484{
4b12f0de
SY		 6485 u64 ret;
6486
522c68c4
SY		 6487 /* For VT-d and EPT combination
6488 * 1. MMIO: always map as UC
6489 * 2. EPT with VT-d:
6490 * a. VT-d without snooping control feature: can't guarantee the
6491 * result, try to trust guest.
6492 * b. VT-d with snooping control feature: snooping control feature of
6493 * VT-d engine can guarantee the cache correctness. Just set it
6494 * to WB to keep consistent with host. So the same as item 3.
a19a6d11 6495 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
522c68c4
SY		 6496 * consistent with host MTRR
6497 */
4b12f0de
SY		 6498 if (is_mmio)
6499 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
522c68c4
SY		 6500 else if (vcpu->kvm->arch.iommu_domain &&
6501 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
6502 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
6503 VMX_EPT_MT_EPTE_SHIFT;
4b12f0de 6504 else
522c68c4 6505 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
a19a6d11 6506 | VMX_EPT_IPAT_BIT;
4b12f0de
SY		 6507
6508 return ret;
64d4d521
SY		 6509}
6510
17cc3935 6511static int vmx_get_lpage_level(void)
344f414f 6512{
878403b7
SY		 6513 if (enable_ept && !cpu_has_vmx_ept_1g_page())
6514 return PT_DIRECTORY_LEVEL;
6515 else
6516 /* For shadow and EPT supported 1GB page */
6517 return PT_PDPE_LEVEL;
344f414f
JR		 6518}
6519
0e851880
SY		 6520static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
6521{
4e47c7a6
SY		 6522 struct kvm_cpuid_entry2 *best;
6523 struct vcpu_vmx *vmx = to_vmx(vcpu);
6524 u32 exec_control;
6525
6526 vmx->rdtscp_enabled = false;
6527 if (vmx_rdtscp_supported()) {
6528 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6529 if (exec_control & SECONDARY_EXEC_RDTSCP) {
6530 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
6531 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
6532 vmx->rdtscp_enabled = true;
6533 else {
6534 exec_control &= ~SECONDARY_EXEC_RDTSCP;
6535 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6536 exec_control);
6537 }
6538 }
6539 }
0e851880
SY		 6540}
6541
d4330ef2
JR		 6542static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
6543{
7b8050f5
NHE		 6544 if (func == 1 && nested)
6545 entry->ecx |= bit(X86_FEATURE_VMX);
d4330ef2
JR		 6546}
6547
fe3ef05c
NHE		 6548/*
6549 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
6550 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
6551 * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
6552 * guest in a way that will both be appropriate to L1's requests, and our
6553 * needs. In addition to modifying the active vmcs (which is vmcs02), this
6554 * function also has additional necessary side-effects, like setting various
6555 * vcpu->arch fields.
6556 */
6557static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6558{
6559 struct vcpu_vmx *vmx = to_vmx(vcpu);
6560 u32 exec_control;
6561
6562 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
6563 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
6564 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
6565 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
6566 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
6567 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
6568 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
6569 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
6570 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
6571 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
6572 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
6573 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
6574 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
6575 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
6576 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
6577 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
6578 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
6579 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
6580 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
6581 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
6582 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
6583 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
6584 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
6585 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
6586 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
6587 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
6588 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
6589 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
6590 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
6591 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
6592 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
6593 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
6594 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
6595 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
6596 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
6597 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
6598
6599 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
6600 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
6601 vmcs12->vm_entry_intr_info_field);
6602 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
6603 vmcs12->vm_entry_exception_error_code);
6604 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
6605 vmcs12->vm_entry_instruction_len);
6606 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
6607 vmcs12->guest_interruptibility_info);
6608 vmcs_write32(GUEST_ACTIVITY_STATE, vmcs12->guest_activity_state);
6609 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
6610 vmcs_writel(GUEST_DR7, vmcs12->guest_dr7);
6611 vmcs_writel(GUEST_RFLAGS, vmcs12->guest_rflags);
6612 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
6613 vmcs12->guest_pending_dbg_exceptions);
6614 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
6615 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
6616
6617 vmcs_write64(VMCS_LINK_POINTER, -1ull);
6618
6619 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
6620 (vmcs_config.pin_based_exec_ctrl |
6621 vmcs12->pin_based_vm_exec_control));
6622
6623 /*
6624 * Whether page-faults are trapped is determined by a combination of
6625 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
6626 * If enable_ept, L0 doesn't care about page faults and we should
6627 * set all of these to L1's desires. However, if !enable_ept, L0 does
6628 * care about (at least some) page faults, and because it is not easy
6629 * (if at all possible?) to merge L0 and L1's desires, we simply ask
6630 * to exit on each and every L2 page fault. This is done by setting
6631 * MASK=MATCH=0 and (see below) EB.PF=1.
6632 * Note that below we don't need special code to set EB.PF beyond the
6633 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
6634 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
6635 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
6636 *
6637 * A problem with this approach (when !enable_ept) is that L1 may be
6638 * injected with more page faults than it asked for. This could have
6639 * caused problems, but in practice existing hypervisors don't care.
6640 * To fix this, we will need to emulate the PFEC checking (on the L1
6641 * page tables), using walk_addr(), when injecting PFs to L1.
6642 */
6643 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
6644 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
6645 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
6646 enable_ept ? vmcs12->page_fault_error_code_match : 0);
6647
6648 if (cpu_has_secondary_exec_ctrls()) {
6649 u32 exec_control = vmx_secondary_exec_control(vmx);
6650 if (!vmx->rdtscp_enabled)
6651 exec_control &= ~SECONDARY_EXEC_RDTSCP;
6652 /* Take the following fields only from vmcs12 */
6653 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6654 if (nested_cpu_has(vmcs12,
6655 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
6656 exec_control |= vmcs12->secondary_vm_exec_control;
6657
6658 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
6659 /*
6660 * Translate L1 physical address to host physical
6661 * address for vmcs02. Keep the page pinned, so this
6662 * physical address remains valid. We keep a reference
6663 * to it so we can release it later.
6664 */
6665 if (vmx->nested.apic_access_page) /* shouldn't happen */
6666 nested_release_page(vmx->nested.apic_access_page);
6667 vmx->nested.apic_access_page =
6668 nested_get_page(vcpu, vmcs12->apic_access_addr);
6669 /*
6670 * If translation failed, no matter: This feature asks
6671 * to exit when accessing the given address, and if it
6672 * can never be accessed, this feature won't do
6673 * anything anyway.
6674 */
6675 if (!vmx->nested.apic_access_page)
6676 exec_control &=
6677 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6678 else
6679 vmcs_write64(APIC_ACCESS_ADDR,
6680 page_to_phys(vmx->nested.apic_access_page));
6681 }
6682
6683 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6684 }
6685
6686
6687 /*
6688 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
6689 * Some constant fields are set here by vmx_set_constant_host_state().
6690 * Other fields are different per CPU, and will be set later when
6691 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
6692 */
6693 vmx_set_constant_host_state();
6694
6695 /*
6696 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
6697 * entry, but only if the current (host) sp changed from the value
6698 * we wrote last (vmx->host_rsp). This cache is no longer relevant
6699 * if we switch vmcs, and rather than hold a separate cache per vmcs,
6700 * here we just force the write to happen on entry.
6701 */
6702 vmx->host_rsp = 0;
6703
6704 exec_control = vmx_exec_control(vmx); /* L0's desires */
6705 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
6706 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
6707 exec_control &= ~CPU_BASED_TPR_SHADOW;
6708 exec_control |= vmcs12->cpu_based_vm_exec_control;
6709 /*
6710 * Merging of IO and MSR bitmaps not currently supported.
6711 * Rather, exit every time.
6712 */
6713 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
6714 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
6715 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
6716
6717 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
6718
6719 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
6720 * bitwise-or of what L1 wants to trap for L2, and what we want to
6721 * trap. Note that CR0.TS also needs updating - we do this later.
6722 */
6723 update_exception_bitmap(vcpu);
6724 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
6725 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
6726
6727 /* Note: IA32_MODE, LOAD_IA32_EFER are modified by vmx_set_efer below */
6728 vmcs_write32(VM_EXIT_CONTROLS,
6729 vmcs12->vm_exit_controls | vmcs_config.vmexit_ctrl);
6730 vmcs_write32(VM_ENTRY_CONTROLS, vmcs12->vm_entry_controls |
6731 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
6732
6733 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)
6734 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
6735 else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
6736 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
6737
6738
6739 set_cr4_guest_host_mask(vmx);
6740
27fc51b2
NHE		 6741 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
6742 vmcs_write64(TSC_OFFSET,
6743 vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
6744 else
6745 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
fe3ef05c
NHE		 6746
6747 if (enable_vpid) {
6748 /*
6749 * Trivially support vpid by letting L2s share their parent
6750 * L1's vpid. TODO: move to a more elaborate solution, giving
6751 * each L2 its own vpid and exposing the vpid feature to L1.
6752 */
6753 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
6754 vmx_flush_tlb(vcpu);
6755 }
6756
6757 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
6758 vcpu->arch.efer = vmcs12->guest_ia32_efer;
6759 if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
6760 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
6761 else
6762 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
6763 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
6764 vmx_set_efer(vcpu, vcpu->arch.efer);
6765
6766 /*
6767 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
6768 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
6769 * The CR0_READ_SHADOW is what L2 should have expected to read given
6770 * the specifications by L1; It's not enough to take
6771 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
6772 * have more bits than L1 expected.
6773 */
6774 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
6775 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
6776
6777 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
6778 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
6779
6780 /* shadow page tables on either EPT or shadow page tables */
6781 kvm_set_cr3(vcpu, vmcs12->guest_cr3);
6782 kvm_mmu_reset_context(vcpu);
6783
6784 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
6785 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
6786}
6787
cd232ad0
NHE		 6788/*
6789 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
6790 * for running an L2 nested guest.
6791 */
6792static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
6793{
6794 struct vmcs12 *vmcs12;
6795 struct vcpu_vmx *vmx = to_vmx(vcpu);
6796 int cpu;
6797 struct loaded_vmcs *vmcs02;
6798
6799 if (!nested_vmx_check_permission(vcpu) ||
6800 !nested_vmx_check_vmcs12(vcpu))
6801 return 1;
6802
6803 skip_emulated_instruction(vcpu);
6804 vmcs12 = get_vmcs12(vcpu);
6805
7c177938
NHE		 6806 /*
6807 * The nested entry process starts with enforcing various prerequisites
6808 * on vmcs12 as required by the Intel SDM, and act appropriately when
6809 * they fail: As the SDM explains, some conditions should cause the
6810 * instruction to fail, while others will cause the instruction to seem
6811 * to succeed, but return an EXIT_REASON_INVALID_STATE.
6812 * To speed up the normal (success) code path, we should avoid checking
6813 * for misconfigurations which will anyway be caught by the processor
6814 * when using the merged vmcs02.
6815 */
6816 if (vmcs12->launch_state == launch) {
6817 nested_vmx_failValid(vcpu,
6818 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
6819 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
6820 return 1;
6821 }
6822
6823 if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
6824 !IS_ALIGNED(vmcs12->msr_bitmap, PAGE_SIZE)) {
6825 /*TODO: Also verify bits beyond physical address width are 0*/
6826 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6827 return 1;
6828 }
6829
6830 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
6831 !IS_ALIGNED(vmcs12->apic_access_addr, PAGE_SIZE)) {
6832 /*TODO: Also verify bits beyond physical address width are 0*/
6833 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6834 return 1;
6835 }
6836
6837 if (vmcs12->vm_entry_msr_load_count > 0 ||
6838 vmcs12->vm_exit_msr_load_count > 0 ||
6839 vmcs12->vm_exit_msr_store_count > 0) {
bd80158a
JK		 6840 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
6841 __func__);
7c177938
NHE		 6842 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6843 return 1;
6844 }
6845
6846 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
6847 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high) ||
6848 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
6849 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
6850 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
6851 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
6852 !vmx_control_verify(vmcs12->vm_exit_controls,
6853 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high) ||
6854 !vmx_control_verify(vmcs12->vm_entry_controls,
6855 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high))
6856 {
6857 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6858 return 1;
6859 }
6860
6861 if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
6862 ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
6863 nested_vmx_failValid(vcpu,
6864 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
6865 return 1;
6866 }
6867
6868 if (((vmcs12->guest_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
6869 ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
6870 nested_vmx_entry_failure(vcpu, vmcs12,
6871 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
6872 return 1;
6873 }
6874 if (vmcs12->vmcs_link_pointer != -1ull) {
6875 nested_vmx_entry_failure(vcpu, vmcs12,
6876 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
6877 return 1;
6878 }
6879
6880 /*
6881 * We're finally done with prerequisite checking, and can start with
6882 * the nested entry.
6883 */
6884
cd232ad0
NHE		 6885 vmcs02 = nested_get_current_vmcs02(vmx);
6886 if (!vmcs02)
6887 return -ENOMEM;
6888
6889 enter_guest_mode(vcpu);
6890
6891 vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
6892
6893 cpu = get_cpu();
6894 vmx->loaded_vmcs = vmcs02;
6895 vmx_vcpu_put(vcpu);
6896 vmx_vcpu_load(vcpu, cpu);
6897 vcpu->cpu = cpu;
6898 put_cpu();
6899
6900 vmcs12->launch_state = 1;
6901
6902 prepare_vmcs02(vcpu, vmcs12);
6903
6904 /*
6905 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
6906 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
6907 * returned as far as L1 is concerned. It will only return (and set
6908 * the success flag) when L2 exits (see nested_vmx_vmexit()).
6909 */
6910 return 1;
6911}
6912
4704d0be
NHE		 6913/*
6914 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
6915 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
6916 * This function returns the new value we should put in vmcs12.guest_cr0.
6917 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
6918 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
6919 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
6920 * didn't trap the bit, because if L1 did, so would L0).
6921 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
6922 * been modified by L2, and L1 knows it. So just leave the old value of
6923 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
6924 * isn't relevant, because if L0 traps this bit it can set it to anything.
6925 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
6926 * changed these bits, and therefore they need to be updated, but L0
6927 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
6928 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
6929 */
6930static inline unsigned long
6931vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6932{
6933 return
6934 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
6935 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
6936 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
6937 vcpu->arch.cr0_guest_owned_bits));
6938}
6939
6940static inline unsigned long
6941vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6942{
6943 return
6944 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
6945 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
6946 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
6947 vcpu->arch.cr4_guest_owned_bits));
6948}
6949
6950/*
6951 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
6952 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
6953 * and this function updates it to reflect the changes to the guest state while
6954 * L2 was running (and perhaps made some exits which were handled directly by L0
6955 * without going back to L1), and to reflect the exit reason.
6956 * Note that we do not have to copy here all VMCS fields, just those that
6957 * could have changed by the L2 guest or the exit - i.e., the guest-state and
6958 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
6959 * which already writes to vmcs12 directly.
6960 */
6961void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6962{
6963 /* update guest state fields: */
6964 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
6965 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
6966
6967 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
6968 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6969 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
6970 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
6971
6972 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
6973 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
6974 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
6975 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
6976 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
6977 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
6978 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
6979 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
6980 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
6981 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
6982 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
6983 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
6984 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
6985 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
6986 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
6987 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
6988 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
6989 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
6990 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
6991 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
6992 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
6993 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
6994 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
6995 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
6996 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
6997 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
6998 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
6999 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
7000 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
7001 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
7002 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
7003 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
7004 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
7005 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
7006 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
7007 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
7008
7009 vmcs12->guest_activity_state = vmcs_read32(GUEST_ACTIVITY_STATE);
7010 vmcs12->guest_interruptibility_info =
7011 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
7012 vmcs12->guest_pending_dbg_exceptions =
7013 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
7014
7015 /* TODO: These cannot have changed unless we have MSR bitmaps and
7016 * the relevant bit asks not to trap the change */
7017 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
7018 if (vmcs12->vm_entry_controls & VM_EXIT_SAVE_IA32_PAT)
7019 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
7020 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
7021 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
7022 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
7023
7024 /* update exit information fields: */
7025
7026 vmcs12->vm_exit_reason = vmcs_read32(VM_EXIT_REASON);
7027 vmcs12->exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7028
7029 vmcs12->vm_exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7030 vmcs12->vm_exit_intr_error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
7031 vmcs12->idt_vectoring_info_field =
7032 vmcs_read32(IDT_VECTORING_INFO_FIELD);
7033 vmcs12->idt_vectoring_error_code =
7034 vmcs_read32(IDT_VECTORING_ERROR_CODE);
7035 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
7036 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7037
7038 /* clear vm-entry fields which are to be cleared on exit */
7039 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
7040 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
7041}
7042
7043/*
7044 * A part of what we need to when the nested L2 guest exits and we want to
7045 * run its L1 parent, is to reset L1's guest state to the host state specified
7046 * in vmcs12.
7047 * This function is to be called not only on normal nested exit, but also on
7048 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
7049 * Failures During or After Loading Guest State").
7050 * This function should be called when the active VMCS is L1's (vmcs01).
7051 */
7052void load_vmcs12_host_state(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7053{
7054 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
7055 vcpu->arch.efer = vmcs12->host_ia32_efer;
7056 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
7057 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
7058 else
7059 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
7060 vmx_set_efer(vcpu, vcpu->arch.efer);
7061
7062 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
7063 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
7064 /*
7065 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
7066 * actually changed, because it depends on the current state of
7067 * fpu_active (which may have changed).
7068 * Note that vmx_set_cr0 refers to efer set above.
7069 */
7070 kvm_set_cr0(vcpu, vmcs12->host_cr0);
7071 /*
7072 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
7073 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
7074 * but we also need to update cr0_guest_host_mask and exception_bitmap.
7075 */
7076 update_exception_bitmap(vcpu);
7077 vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
7078 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
7079
7080 /*
7081 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
7082 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
7083 */
7084 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
7085 kvm_set_cr4(vcpu, vmcs12->host_cr4);
7086
7087 /* shadow page tables on either EPT or shadow page tables */
7088 kvm_set_cr3(vcpu, vmcs12->host_cr3);
7089 kvm_mmu_reset_context(vcpu);
7090
7091 if (enable_vpid) {
7092 /*
7093 * Trivially support vpid by letting L2s share their parent
7094 * L1's vpid. TODO: move to a more elaborate solution, giving
7095 * each L2 its own vpid and exposing the vpid feature to L1.
7096 */
7097 vmx_flush_tlb(vcpu);
7098 }
7099
7100
7101 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
7102 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
7103 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
7104 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
7105 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
7106 vmcs_writel(GUEST_TR_BASE, vmcs12->host_tr_base);
7107 vmcs_writel(GUEST_GS_BASE, vmcs12->host_gs_base);
7108 vmcs_writel(GUEST_FS_BASE, vmcs12->host_fs_base);
7109 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->host_es_selector);
7110 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->host_cs_selector);
7111 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->host_ss_selector);
7112 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->host_ds_selector);
7113 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->host_fs_selector);
7114 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->host_gs_selector);
7115 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->host_tr_selector);
7116
7117 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT)
7118 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
7119 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
7120 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
7121 vmcs12->host_ia32_perf_global_ctrl);
7122}
7123
7124/*
7125 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
7126 * and modify vmcs12 to make it see what it would expect to see there if
7127 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
7128 */
7129static void nested_vmx_vmexit(struct kvm_vcpu *vcpu)
7130{
7131 struct vcpu_vmx *vmx = to_vmx(vcpu);
7132 int cpu;
7133 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7134
7135 leave_guest_mode(vcpu);
7136 prepare_vmcs12(vcpu, vmcs12);
7137
7138 cpu = get_cpu();
7139 vmx->loaded_vmcs = &vmx->vmcs01;
7140 vmx_vcpu_put(vcpu);
7141 vmx_vcpu_load(vcpu, cpu);
7142 vcpu->cpu = cpu;
7143 put_cpu();
7144
7145 /* if no vmcs02 cache requested, remove the one we used */
7146 if (VMCS02_POOL_SIZE == 0)
7147 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
7148
7149 load_vmcs12_host_state(vcpu, vmcs12);
7150
27fc51b2 7151 /* Update TSC_OFFSET if TSC was changed while L2 ran */
4704d0be
NHE		 7152 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
7153
7154 /* This is needed for same reason as it was needed in prepare_vmcs02 */
7155 vmx->host_rsp = 0;
7156
7157 /* Unpin physical memory we referred to in vmcs02 */
7158 if (vmx->nested.apic_access_page) {
7159 nested_release_page(vmx->nested.apic_access_page);
7160 vmx->nested.apic_access_page = 0;
7161 }
7162
7163 /*
7164 * Exiting from L2 to L1, we're now back to L1 which thinks it just
7165 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
7166 * success or failure flag accordingly.
7167 */
7168 if (unlikely(vmx->fail)) {
7169 vmx->fail = 0;
7170 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
7171 } else
7172 nested_vmx_succeed(vcpu);
7173}
7174
7c177938
NHE		 7175/*
7176 * L1's failure to enter L2 is a subset of a normal exit, as explained in
7177 * 23.7 "VM-entry failures during or after loading guest state" (this also
7178 * lists the acceptable exit-reason and exit-qualification parameters).
7179 * It should only be called before L2 actually succeeded to run, and when
7180 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
7181 */
7182static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
7183 struct vmcs12 *vmcs12,
7184 u32 reason, unsigned long qualification)
7185{
7186 load_vmcs12_host_state(vcpu, vmcs12);
7187 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
7188 vmcs12->exit_qualification = qualification;
7189 nested_vmx_succeed(vcpu);
7190}
7191
8a76d7f2
JR		 7192static int vmx_check_intercept(struct kvm_vcpu *vcpu,
7193 struct x86_instruction_info *info,
7194 enum x86_intercept_stage stage)
7195{
7196 return X86EMUL_CONTINUE;
7197}
7198
cbdd1bea 7199static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 7200 .cpu_has_kvm_support = cpu_has_kvm_support,
7201 .disabled_by_bios = vmx_disabled_by_bios,
7202 .hardware_setup = hardware_setup,
7203 .hardware_unsetup = hardware_unsetup,
002c7f7c 7204 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 7205 .hardware_enable = hardware_enable,
7206 .hardware_disable = hardware_disable,
04547156 7207 .cpu_has_accelerated_tpr = report_flexpriority,
6aa8b732
AK		 7208
7209 .vcpu_create = vmx_create_vcpu,
7210 .vcpu_free = vmx_free_vcpu,
04d2cc77 7211 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 7212
04d2cc77 7213 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 7214 .vcpu_load = vmx_vcpu_load,
7215 .vcpu_put = vmx_vcpu_put,
7216
7217 .set_guest_debug = set_guest_debug,
7218 .get_msr = vmx_get_msr,
7219 .set_msr = vmx_set_msr,
7220 .get_segment_base = vmx_get_segment_base,
7221 .get_segment = vmx_get_segment,
7222 .set_segment = vmx_set_segment,
2e4d2653 7223 .get_cpl = vmx_get_cpl,
6aa8b732 7224 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 7225 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
aff48baa 7226 .decache_cr3 = vmx_decache_cr3,
25c4c276 7227 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 7228 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 7229 .set_cr3 = vmx_set_cr3,
7230 .set_cr4 = vmx_set_cr4,
6aa8b732 7231 .set_efer = vmx_set_efer,
6aa8b732
AK		 7232 .get_idt = vmx_get_idt,
7233 .set_idt = vmx_set_idt,
7234 .get_gdt = vmx_get_gdt,
7235 .set_gdt = vmx_set_gdt,
020df079 7236 .set_dr7 = vmx_set_dr7,
5fdbf976 7237 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 7238 .get_rflags = vmx_get_rflags,
7239 .set_rflags = vmx_set_rflags,
ebcbab4c 7240 .fpu_activate = vmx_fpu_activate,
02daab21 7241 .fpu_deactivate = vmx_fpu_deactivate,
6aa8b732
AK		 7242
7243 .tlb_flush = vmx_flush_tlb,
6aa8b732 7244
6aa8b732 7245 .run = vmx_vcpu_run,
6062d012 7246 .handle_exit = vmx_handle_exit,
6aa8b732 7247 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 7248 .set_interrupt_shadow = vmx_set_interrupt_shadow,
7249 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 7250 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 7251 .set_irq = vmx_inject_irq,
95ba8273 7252 .set_nmi = vmx_inject_nmi,
298101da 7253 .queue_exception = vmx_queue_exception,
b463a6f7 7254 .cancel_injection = vmx_cancel_injection,
78646121 7255 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 7256 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 7257 .get_nmi_mask = vmx_get_nmi_mask,
7258 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 7259 .enable_nmi_window = enable_nmi_window,
7260 .enable_irq_window = enable_irq_window,
7261 .update_cr8_intercept = update_cr8_intercept,
95ba8273 7262
cbc94022 7263 .set_tss_addr = vmx_set_tss_addr,
67253af5 7264 .get_tdp_level = get_ept_level,
4b12f0de 7265 .get_mt_mask = vmx_get_mt_mask,
229456fc 7266
586f9607 7267 .get_exit_info = vmx_get_exit_info,
586f9607 7268
17cc3935 7269 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY		 7270
7271 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY		 7272
7273 .rdtscp_supported = vmx_rdtscp_supported,
d4330ef2
JR		 7274
7275 .set_supported_cpuid = vmx_set_supported_cpuid,
f5f48ee1
SY		 7276
7277 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
99e3e30a 7278
4051b188 7279 .set_tsc_khz = vmx_set_tsc_khz,
99e3e30a 7280 .write_tsc_offset = vmx_write_tsc_offset,
e48672fa 7281 .adjust_tsc_offset = vmx_adjust_tsc_offset,
857e4099 7282 .compute_tsc_offset = vmx_compute_tsc_offset,
d5c1785d 7283 .read_l1_tsc = vmx_read_l1_tsc,
1c97f0a0
JR		 7284
7285 .set_tdp_cr3 = vmx_set_cr3,
8a76d7f2
JR		 7286
7287 .check_intercept = vmx_check_intercept,
6aa8b732
AK		 7288};
7289
7290static int __init vmx_init(void)
7291{
26bb0981
AK		 7292 int r, i;
7293
7294 rdmsrl_safe(MSR_EFER, &host_efer);
7295
7296 for (i = 0; i < NR_VMX_MSR; ++i)
7297 kvm_define_shared_msr(i, vmx_msr_index[i]);
fdef3ad1 7298
3e7c73e9 7299 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 7300 if (!vmx_io_bitmap_a)
7301 return -ENOMEM;
7302
2106a548
GC		 7303 r = -ENOMEM;
7304
3e7c73e9 7305 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 7306 if (!vmx_io_bitmap_b)
fdef3ad1 7307 goto out;
fdef3ad1 7308
5897297b 7309 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 7310 if (!vmx_msr_bitmap_legacy)
25c5f225 7311 goto out1;
2106a548 7312
25c5f225 7313
5897297b 7314 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 7315 if (!vmx_msr_bitmap_longmode)
5897297b 7316 goto out2;
2106a548 7317
5897297b 7318
fdef3ad1
HQ		 7319 /*
7320 * Allow direct access to the PC debug port (it is often used for I/O
7321 * delays, but the vmexits simply slow things down).
7322 */
3e7c73e9
AK		 7323 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
7324 clear_bit(0x80, vmx_io_bitmap_a);
fdef3ad1 7325
3e7c73e9 7326 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
fdef3ad1 7327
5897297b
AK		 7328 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
7329 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
25c5f225 7330
2384d2b3
SY		 7331 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
7332
0ee75bea
AK		 7333 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
7334 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 7335 if (r)
5897297b 7336 goto out3;
25c5f225 7337
5897297b
AK		 7338 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
7339 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
7340 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
7341 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
7342 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
7343 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
fdef3ad1 7344
089d034e 7345 if (enable_ept) {
3f6d8c8a
XH		 7346 kvm_mmu_set_mask_ptes(0ull,
7347 (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
7348 (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
7349 0ull, VMX_EPT_EXECUTABLE_MASK);
ce88decf 7350 ept_set_mmio_spte_mask();
5fdbcb9d
SY		 7351 kvm_enable_tdp();
7352 } else
7353 kvm_disable_tdp();
1439442c 7354
fdef3ad1
HQ		 7355 return 0;
7356
5897297b
AK		 7357out3:
7358 free_page((unsigned long)vmx_msr_bitmap_longmode);
25c5f225 7359out2:
5897297b 7360 free_page((unsigned long)vmx_msr_bitmap_legacy);
fdef3ad1 7361out1:
3e7c73e9 7362 free_page((unsigned long)vmx_io_bitmap_b);
fdef3ad1 7363out:
3e7c73e9 7364 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 7365 return r;
6aa8b732
AK		 7366}
7367
7368static void __exit vmx_exit(void)
7369{
5897297b
AK		 7370 free_page((unsigned long)vmx_msr_bitmap_legacy);
7371 free_page((unsigned long)vmx_msr_bitmap_longmode);
3e7c73e9
AK		 7372 free_page((unsigned long)vmx_io_bitmap_b);
7373 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 7374
cb498ea2 7375 kvm_exit();
6aa8b732
AK		 7376}
7377
7378module_init(vmx_init)
7379module_exit(vmx_exit)
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