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KVM: VMX: Fix incorrect rcu deref in rmode_tss_base()
[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
221d059d 8 * Copyright 2010 Red Hat, Inc. and/or its affilates.
6aa8b732
AK		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
e495606d 21
edf88417 22#include <linux/kvm_host.h>
6aa8b732 23#include <linux/module.h>
9d8f549d 24#include <linux/kernel.h>
6aa8b732
AK		 25#include <linux/mm.h>
26#include <linux/highmem.h>
e8edc6e0 27#include <linux/sched.h>
c7addb90 28#include <linux/moduleparam.h>
229456fc 29#include <linux/ftrace_event.h>
5a0e3ad6 30#include <linux/slab.h>
cafd6659 31#include <linux/tboot.h>
5fdbf976 32#include "kvm_cache_regs.h"
35920a35 33#include "x86.h"
e495606d 34
6aa8b732 35#include <asm/io.h>
3b3be0d1 36#include <asm/desc.h>
13673a90 37#include <asm/vmx.h>
6210e37b 38#include <asm/virtext.h>
a0861c02 39#include <asm/mce.h>
6aa8b732 40
229456fc
MT		 41#include "trace.h"
42
4ecac3fd
AK		 43#define __ex(x) __kvm_handle_fault_on_reboot(x)
44
6aa8b732
AK		 45MODULE_AUTHOR("Qumranet");
46MODULE_LICENSE("GPL");
47
4462d21a 48static int __read_mostly bypass_guest_pf = 1;
c1f8bc04 49module_param(bypass_guest_pf, bool, S_IRUGO);
c7addb90 50
4462d21a 51static int __read_mostly enable_vpid = 1;
736caefe 52module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 53
4462d21a 54static int __read_mostly flexpriority_enabled = 1;
736caefe 55module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 56
4462d21a 57static int __read_mostly enable_ept = 1;
736caefe 58module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 59
3a624e29
NK		 60static int __read_mostly enable_unrestricted_guest = 1;
61module_param_named(unrestricted_guest,
62 enable_unrestricted_guest, bool, S_IRUGO);
63
4462d21a 64static int __read_mostly emulate_invalid_guest_state = 0;
c1f8bc04 65module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 66
b923e62e
DX		 67static int __read_mostly vmm_exclusive = 1;
68module_param(vmm_exclusive, bool, S_IRUGO);
69
cdc0e244
AK		 70#define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST \
71 (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
72#define KVM_GUEST_CR0_MASK \
73 (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
74#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST \
81231c69 75 (X86_CR0_WP | X86_CR0_NE)
cdc0e244
AK		 76#define KVM_VM_CR0_ALWAYS_ON \
77 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 78#define KVM_CR4_GUEST_OWNED_BITS \
79 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
80 | X86_CR4_OSXMMEXCPT)
81
cdc0e244
AK		 82#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
83#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
84
78ac8b47
AK		 85#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
86
4b8d54f9
ZE		 87/*
88 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
89 * ple_gap: upper bound on the amount of time between two successive
90 * executions of PAUSE in a loop. Also indicate if ple enabled.
91 * According to test, this time is usually small than 41 cycles.
92 * ple_window: upper bound on the amount of time a guest is allowed to execute
93 * in a PAUSE loop. Tests indicate that most spinlocks are held for
94 * less than 2^12 cycles
95 * Time is measured based on a counter that runs at the same rate as the TSC,
96 * refer SDM volume 3b section 21.6.13 & 22.1.3.
97 */
98#define KVM_VMX_DEFAULT_PLE_GAP 41
99#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
100static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
101module_param(ple_gap, int, S_IRUGO);
102
103static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
104module_param(ple_window, int, S_IRUGO);
105
61d2ef2c
AK		 106#define NR_AUTOLOAD_MSRS 1
107
a2fa3e9f
GH		 108struct vmcs {
109 u32 revision_id;
110 u32 abort;
111 char data[0];
112};
113
26bb0981
AK		 114struct shared_msr_entry {
115 unsigned index;
116 u64 data;
d5696725 117 u64 mask;
26bb0981
AK		 118};
119
a2fa3e9f 120struct vcpu_vmx {
fb3f0f51 121 struct kvm_vcpu vcpu;
543e4243 122 struct list_head local_vcpus_link;
313dbd49 123 unsigned long host_rsp;
a2fa3e9f 124 int launched;
29bd8a78 125 u8 fail;
1155f76a 126 u32 idt_vectoring_info;
26bb0981 127 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH		 128 int nmsrs;
129 int save_nmsrs;
a2fa3e9f 130#ifdef CONFIG_X86_64
44ea2b17
AK		 131 u64 msr_host_kernel_gs_base;
132 u64 msr_guest_kernel_gs_base;
a2fa3e9f
GH		 133#endif
134 struct vmcs *vmcs;
61d2ef2c
AK		 135 struct msr_autoload {
136 unsigned nr;
137 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
138 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
139 } msr_autoload;
a2fa3e9f
GH		 140 struct {
141 int loaded;
142 u16 fs_sel, gs_sel, ldt_sel;
152d3f2f
LV		 143 int gs_ldt_reload_needed;
144 int fs_reload_needed;
d77c26fc 145 } host_state;
9c8cba37 146 struct {
7ffd92c5 147 int vm86_active;
78ac8b47 148 ulong save_rflags;
7ffd92c5
AK		 149 struct kvm_save_segment {
150 u16 selector;
151 unsigned long base;
152 u32 limit;
153 u32 ar;
154 } tr, es, ds, fs, gs;
9c8cba37
AK		 155 struct {
156 bool pending;
157 u8 vector;
158 unsigned rip;
159 } irq;
160 } rmode;
2384d2b3 161 int vpid;
04fa4d32 162 bool emulation_required;
3b86cd99
JK		 163
164 /* Support for vnmi-less CPUs */
165 int soft_vnmi_blocked;
166 ktime_t entry_time;
167 s64 vnmi_blocked_time;
a0861c02 168 u32 exit_reason;
4e47c7a6
SY		 169
170 bool rdtscp_enabled;
a2fa3e9f
GH		 171};
172
173static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
174{
fb3f0f51 175 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 176}
177
b7ebfb05 178static int init_rmode(struct kvm *kvm);
4e1096d2 179static u64 construct_eptp(unsigned long root_hpa);
4610c9cc
DX		 180static void kvm_cpu_vmxon(u64 addr);
181static void kvm_cpu_vmxoff(void);
75880a01 182
6aa8b732
AK		 183static DEFINE_PER_CPU(struct vmcs *, vmxarea);
184static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
543e4243 185static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu);
6aa8b732 186
3e7c73e9
AK		 187static unsigned long *vmx_io_bitmap_a;
188static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 189static unsigned long *vmx_msr_bitmap_legacy;
190static unsigned long *vmx_msr_bitmap_longmode;
fdef3ad1 191
2384d2b3
SY		 192static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
193static DEFINE_SPINLOCK(vmx_vpid_lock);
194
1c3d14fe 195static struct vmcs_config {
6aa8b732
AK		 196 int size;
197 int order;
198 u32 revision_id;
1c3d14fe
YS		 199 u32 pin_based_exec_ctrl;
200 u32 cpu_based_exec_ctrl;
f78e0e2e 201 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 202 u32 vmexit_ctrl;
203 u32 vmentry_ctrl;
204} vmcs_config;
6aa8b732 205
efff9e53 206static struct vmx_capability {
d56f546d
SY		 207 u32 ept;
208 u32 vpid;
209} vmx_capability;
210
6aa8b732
AK		 211#define VMX_SEGMENT_FIELD(seg) \
212 [VCPU_SREG_##seg] = { \
213 .selector = GUEST_##seg##_SELECTOR, \
214 .base = GUEST_##seg##_BASE, \
215 .limit = GUEST_##seg##_LIMIT, \
216 .ar_bytes = GUEST_##seg##_AR_BYTES, \
217 }
218
219static struct kvm_vmx_segment_field {
220 unsigned selector;
221 unsigned base;
222 unsigned limit;
223 unsigned ar_bytes;
224} kvm_vmx_segment_fields[] = {
225 VMX_SEGMENT_FIELD(CS),
226 VMX_SEGMENT_FIELD(DS),
227 VMX_SEGMENT_FIELD(ES),
228 VMX_SEGMENT_FIELD(FS),
229 VMX_SEGMENT_FIELD(GS),
230 VMX_SEGMENT_FIELD(SS),
231 VMX_SEGMENT_FIELD(TR),
232 VMX_SEGMENT_FIELD(LDTR),
233};
234
26bb0981
AK		 235static u64 host_efer;
236
6de4f3ad
AK		 237static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
238
4d56c8a7
AK		 239/*
240 * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
241 * away by decrementing the array size.
242 */
6aa8b732 243static const u32 vmx_msr_index[] = {
05b3e0c2 244#ifdef CONFIG_X86_64
44ea2b17 245 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 246#endif
4e47c7a6 247 MSR_EFER, MSR_TSC_AUX, MSR_K6_STAR,
6aa8b732 248};
9d8f549d 249#define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
6aa8b732 250
31299944 251static inline bool is_page_fault(u32 intr_info)
6aa8b732
AK		 252{
253 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
254 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 255 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 256}
257
31299944 258static inline bool is_no_device(u32 intr_info)
2ab455cc
AL		 259{
260 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
261 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 262 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 263}
264
31299944 265static inline bool is_invalid_opcode(u32 intr_info)
7aa81cc0
AL		 266{
267 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
268 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 269 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 270}
271
31299944 272static inline bool is_external_interrupt(u32 intr_info)
6aa8b732
AK		 273{
274 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
275 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
276}
277
31299944 278static inline bool is_machine_check(u32 intr_info)
a0861c02
AK		 279{
280 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
281 INTR_INFO_VALID_MASK)) ==
282 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
283}
284
31299944 285static inline bool cpu_has_vmx_msr_bitmap(void)
25c5f225 286{
04547156 287 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 288}
289
31299944 290static inline bool cpu_has_vmx_tpr_shadow(void)
6e5d865c 291{
04547156 292 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 293}
294
31299944 295static inline bool vm_need_tpr_shadow(struct kvm *kvm)
6e5d865c 296{
04547156 297 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
6e5d865c
YS		 298}
299
31299944 300static inline bool cpu_has_secondary_exec_ctrls(void)
f78e0e2e 301{
04547156
SY		 302 return vmcs_config.cpu_based_exec_ctrl &
303 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 304}
305
774ead3a 306static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 307{
04547156
SY		 308 return vmcs_config.cpu_based_2nd_exec_ctrl &
309 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
310}
311
312static inline bool cpu_has_vmx_flexpriority(void)
313{
314 return cpu_has_vmx_tpr_shadow() &&
315 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 316}
317
e799794e
MT		 318static inline bool cpu_has_vmx_ept_execute_only(void)
319{
31299944 320 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
e799794e
MT		 321}
322
323static inline bool cpu_has_vmx_eptp_uncacheable(void)
324{
31299944 325 return vmx_capability.ept & VMX_EPTP_UC_BIT;
e799794e
MT		 326}
327
328static inline bool cpu_has_vmx_eptp_writeback(void)
329{
31299944 330 return vmx_capability.ept & VMX_EPTP_WB_BIT;
e799794e
MT		 331}
332
333static inline bool cpu_has_vmx_ept_2m_page(void)
334{
31299944 335 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
e799794e
MT		 336}
337
878403b7
SY		 338static inline bool cpu_has_vmx_ept_1g_page(void)
339{
31299944 340 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
878403b7
SY		 341}
342
4bc9b982
SY		 343static inline bool cpu_has_vmx_ept_4levels(void)
344{
345 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
346}
347
31299944 348static inline bool cpu_has_vmx_invept_individual_addr(void)
d56f546d 349{
31299944 350 return vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT;
d56f546d
SY		 351}
352
31299944 353static inline bool cpu_has_vmx_invept_context(void)
d56f546d 354{
31299944 355 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
d56f546d
SY		 356}
357
31299944 358static inline bool cpu_has_vmx_invept_global(void)
d56f546d 359{
31299944 360 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
d56f546d
SY		 361}
362
518c8aee
GJ		 363static inline bool cpu_has_vmx_invvpid_single(void)
364{
365 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
366}
367
b9d762fa
GJ		 368static inline bool cpu_has_vmx_invvpid_global(void)
369{
370 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
371}
372
31299944 373static inline bool cpu_has_vmx_ept(void)
d56f546d 374{
04547156
SY		 375 return vmcs_config.cpu_based_2nd_exec_ctrl &
376 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 377}
378
31299944 379static inline bool cpu_has_vmx_unrestricted_guest(void)
3a624e29
NK		 380{
381 return vmcs_config.cpu_based_2nd_exec_ctrl &
382 SECONDARY_EXEC_UNRESTRICTED_GUEST;
383}
384
31299944 385static inline bool cpu_has_vmx_ple(void)
4b8d54f9
ZE		 386{
387 return vmcs_config.cpu_based_2nd_exec_ctrl &
388 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
389}
390
31299944 391static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
f78e0e2e 392{
6d3e435e 393 return flexpriority_enabled && irqchip_in_kernel(kvm);
f78e0e2e
SY		 394}
395
31299944 396static inline bool cpu_has_vmx_vpid(void)
2384d2b3 397{
04547156
SY		 398 return vmcs_config.cpu_based_2nd_exec_ctrl &
399 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 400}
401
31299944 402static inline bool cpu_has_vmx_rdtscp(void)
4e47c7a6
SY		 403{
404 return vmcs_config.cpu_based_2nd_exec_ctrl &
405 SECONDARY_EXEC_RDTSCP;
406}
407
31299944 408static inline bool cpu_has_virtual_nmis(void)
f08864b4
SY		 409{
410 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
411}
412
04547156
SY		 413static inline bool report_flexpriority(void)
414{
415 return flexpriority_enabled;
416}
417
8b9cf98c 418static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 419{
420 int i;
421
a2fa3e9f 422 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 423 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 424 return i;
425 return -1;
426}
427
2384d2b3
SY		 428static inline void __invvpid(int ext, u16 vpid, gva_t gva)
429{
430 struct {
431 u64 vpid : 16;
432 u64 rsvd : 48;
433 u64 gva;
434 } operand = { vpid, 0, gva };
435
4ecac3fd 436 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 437 /* CF==1 or ZF==1 --> rc = -1 */
438 "; ja 1f ; ud2 ; 1:"
439 : : "a"(&operand), "c"(ext) : "cc", "memory");
440}
441
1439442c
SY		 442static inline void __invept(int ext, u64 eptp, gpa_t gpa)
443{
444 struct {
445 u64 eptp, gpa;
446 } operand = {eptp, gpa};
447
4ecac3fd 448 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 449 /* CF==1 or ZF==1 --> rc = -1 */
450 "; ja 1f ; ud2 ; 1:\n"
451 : : "a" (&operand), "c" (ext) : "cc", "memory");
452}
453
26bb0981 454static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 455{
456 int i;
457
8b9cf98c 458 i = __find_msr_index(vmx, msr);
a75beee6 459 if (i >= 0)
a2fa3e9f 460 return &vmx->guest_msrs[i];
8b6d44c7 461 return NULL;
7725f0ba
AK		 462}
463
6aa8b732
AK		 464static void vmcs_clear(struct vmcs *vmcs)
465{
466 u64 phys_addr = __pa(vmcs);
467 u8 error;
468
4ecac3fd 469 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
6aa8b732
AK		 470 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
471 : "cc", "memory");
472 if (error)
473 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
474 vmcs, phys_addr);
475}
476
7725b894
DX		 477static void vmcs_load(struct vmcs *vmcs)
478{
479 u64 phys_addr = __pa(vmcs);
480 u8 error;
481
482 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
483 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
484 : "cc", "memory");
485 if (error)
486 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
487 vmcs, phys_addr);
488}
489
6aa8b732
AK		 490static void __vcpu_clear(void *arg)
491{
8b9cf98c 492 struct vcpu_vmx *vmx = arg;
d3b2c338 493 int cpu = raw_smp_processor_id();
6aa8b732 494
8b9cf98c 495 if (vmx->vcpu.cpu == cpu)
a2fa3e9f
GH		 496 vmcs_clear(vmx->vmcs);
497 if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
6aa8b732 498 per_cpu(current_vmcs, cpu) = NULL;
ad312c7c 499 rdtscll(vmx->vcpu.arch.host_tsc);
543e4243
AK		 500 list_del(&vmx->local_vcpus_link);
501 vmx->vcpu.cpu = -1;
502 vmx->launched = 0;
6aa8b732
AK		 503}
504
8b9cf98c 505static void vcpu_clear(struct vcpu_vmx *vmx)
8d0be2b3 506{
eae5ecb5
AK		 507 if (vmx->vcpu.cpu == -1)
508 return;
8691e5a8 509 smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1);
8d0be2b3
AK		 510}
511
1760dd49 512static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
2384d2b3
SY		 513{
514 if (vmx->vpid == 0)
515 return;
516
518c8aee
GJ		 517 if (cpu_has_vmx_invvpid_single())
518 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
2384d2b3
SY		 519}
520
b9d762fa
GJ		 521static inline void vpid_sync_vcpu_global(void)
522{
523 if (cpu_has_vmx_invvpid_global())
524 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
525}
526
527static inline void vpid_sync_context(struct vcpu_vmx *vmx)
528{
529 if (cpu_has_vmx_invvpid_single())
1760dd49 530 vpid_sync_vcpu_single(vmx);
b9d762fa
GJ		 531 else
532 vpid_sync_vcpu_global();
533}
534
1439442c
SY		 535static inline void ept_sync_global(void)
536{
537 if (cpu_has_vmx_invept_global())
538 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
539}
540
541static inline void ept_sync_context(u64 eptp)
542{
089d034e 543 if (enable_ept) {
1439442c
SY		 544 if (cpu_has_vmx_invept_context())
545 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
546 else
547 ept_sync_global();
548 }
549}
550
551static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
552{
089d034e 553 if (enable_ept) {
1439442c
SY		 554 if (cpu_has_vmx_invept_individual_addr())
555 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
556 eptp, gpa);
557 else
558 ept_sync_context(eptp);
559 }
560}
561
6aa8b732
AK		 562static unsigned long vmcs_readl(unsigned long field)
563{
564 unsigned long value;
565
4ecac3fd 566 asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX)
6aa8b732
AK		 567 : "=a"(value) : "d"(field) : "cc");
568 return value;
569}
570
571static u16 vmcs_read16(unsigned long field)
572{
573 return vmcs_readl(field);
574}
575
576static u32 vmcs_read32(unsigned long field)
577{
578 return vmcs_readl(field);
579}
580
581static u64 vmcs_read64(unsigned long field)
582{
05b3e0c2 583#ifdef CONFIG_X86_64
6aa8b732
AK		 584 return vmcs_readl(field);
585#else
586 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
587#endif
588}
589
e52de1b8
AK		 590static noinline void vmwrite_error(unsigned long field, unsigned long value)
591{
592 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
593 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
594 dump_stack();
595}
596
6aa8b732
AK		 597static void vmcs_writel(unsigned long field, unsigned long value)
598{
599 u8 error;
600
4ecac3fd 601 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 602 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 603 if (unlikely(error))
604 vmwrite_error(field, value);
6aa8b732
AK		 605}
606
607static void vmcs_write16(unsigned long field, u16 value)
608{
609 vmcs_writel(field, value);
610}
611
612static void vmcs_write32(unsigned long field, u32 value)
613{
614 vmcs_writel(field, value);
615}
616
617static void vmcs_write64(unsigned long field, u64 value)
618{
6aa8b732 619 vmcs_writel(field, value);
7682f2d0 620#ifndef CONFIG_X86_64
6aa8b732
AK		 621 asm volatile ("");
622 vmcs_writel(field+1, value >> 32);
623#endif
624}
625
2ab455cc
AL		 626static void vmcs_clear_bits(unsigned long field, u32 mask)
627{
628 vmcs_writel(field, vmcs_readl(field) & ~mask);
629}
630
631static void vmcs_set_bits(unsigned long field, u32 mask)
632{
633 vmcs_writel(field, vmcs_readl(field) | mask);
634}
635
abd3f2d6
AK		 636static void update_exception_bitmap(struct kvm_vcpu *vcpu)
637{
638 u32 eb;
639
fd7373cc
JK		 640 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
641 (1u << NM_VECTOR) | (1u << DB_VECTOR);
642 if ((vcpu->guest_debug &
643 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
644 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
645 eb |= 1u << BP_VECTOR;
7ffd92c5 646 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 647 eb = ~0;
089d034e 648 if (enable_ept)
1439442c 649 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
02daab21
AK		 650 if (vcpu->fpu_active)
651 eb &= ~(1u << NM_VECTOR);
abd3f2d6
AK		 652 vmcs_write32(EXCEPTION_BITMAP, eb);
653}
654
61d2ef2c
AK		 655static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
656{
657 unsigned i;
658 struct msr_autoload *m = &vmx->msr_autoload;
659
660 for (i = 0; i < m->nr; ++i)
661 if (m->guest[i].index == msr)
662 break;
663
664 if (i == m->nr)
665 return;
666 --m->nr;
667 m->guest[i] = m->guest[m->nr];
668 m->host[i] = m->host[m->nr];
669 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
670 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
671}
672
673static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
674 u64 guest_val, u64 host_val)
675{
676 unsigned i;
677 struct msr_autoload *m = &vmx->msr_autoload;
678
679 for (i = 0; i < m->nr; ++i)
680 if (m->guest[i].index == msr)
681 break;
682
683 if (i == m->nr) {
684 ++m->nr;
685 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
686 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
687 }
688
689 m->guest[i].index = msr;
690 m->guest[i].value = guest_val;
691 m->host[i].index = msr;
692 m->host[i].value = host_val;
693}
694
33ed6329
AK		 695static void reload_tss(void)
696{
33ed6329
AK		 697 /*
698 * VT restores TR but not its size. Useless.
699 */
89a27f4d 700 struct desc_ptr gdt;
a5f61300 701 struct desc_struct *descs;
33ed6329 702
d6ab1ed4 703 native_store_gdt(&gdt);
89a27f4d 704 descs = (void *)gdt.address;
33ed6329
AK		 705 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
706 load_TR_desc();
33ed6329
AK		 707}
708
92c0d900 709static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 710{
3a34a881 711 u64 guest_efer;
51c6cf66
AK		 712 u64 ignore_bits;
713
f6801dff 714 guest_efer = vmx->vcpu.arch.efer;
3a34a881 715
51c6cf66
AK		 716 /*
717 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
718 * outside long mode
719 */
720 ignore_bits = EFER_NX | EFER_SCE;
721#ifdef CONFIG_X86_64
722 ignore_bits |= EFER_LMA | EFER_LME;
723 /* SCE is meaningful only in long mode on Intel */
724 if (guest_efer & EFER_LMA)
725 ignore_bits &= ~(u64)EFER_SCE;
726#endif
51c6cf66
AK		 727 guest_efer &= ~ignore_bits;
728 guest_efer |= host_efer & ignore_bits;
26bb0981 729 vmx->guest_msrs[efer_offset].data = guest_efer;
d5696725 730 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef
AK		 731
732 clear_atomic_switch_msr(vmx, MSR_EFER);
733 /* On ept, can't emulate nx, and must switch nx atomically */
734 if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
735 guest_efer = vmx->vcpu.arch.efer;
736 if (!(guest_efer & EFER_LMA))
737 guest_efer &= ~EFER_LME;
738 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
739 return false;
740 }
741
26bb0981 742 return true;
51c6cf66
AK		 743}
744
2d49ec72
GN		 745static unsigned long segment_base(u16 selector)
746{
747 struct desc_ptr gdt;
748 struct desc_struct *d;
749 unsigned long table_base;
750 unsigned long v;
751
752 if (!(selector & ~3))
753 return 0;
754
755 native_store_gdt(&gdt);
756 table_base = gdt.address;
757
758 if (selector & 4) { /* from ldt */
759 u16 ldt_selector = kvm_read_ldt();
760
761 if (!(ldt_selector & ~3))
762 return 0;
763
764 table_base = segment_base(ldt_selector);
765 }
766 d = (struct desc_struct *)(table_base + (selector & ~7));
767 v = get_desc_base(d);
768#ifdef CONFIG_X86_64
769 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
770 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
771#endif
772 return v;
773}
774
775static inline unsigned long kvm_read_tr_base(void)
776{
777 u16 tr;
778 asm("str %0" : "=g"(tr));
779 return segment_base(tr);
780}
781
04d2cc77 782static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 783{
04d2cc77 784 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 785 int i;
04d2cc77 786
a2fa3e9f 787 if (vmx->host_state.loaded)
33ed6329
AK		 788 return;
789
a2fa3e9f 790 vmx->host_state.loaded = 1;
33ed6329
AK		 791 /*
792 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
793 * allow segment selectors with cpl > 0 or ti == 1.
794 */
d6e88aec 795 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 796 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
d6e88aec 797 vmx->host_state.fs_sel = kvm_read_fs();
152d3f2f 798 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 799 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 800 vmx->host_state.fs_reload_needed = 0;
801 } else {
33ed6329 802 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 803 vmx->host_state.fs_reload_needed = 1;
33ed6329 804 }
d6e88aec 805 vmx->host_state.gs_sel = kvm_read_gs();
a2fa3e9f
GH		 806 if (!(vmx->host_state.gs_sel & 7))
807 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 808 else {
809 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 810 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 811 }
812
813#ifdef CONFIG_X86_64
814 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
815 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
816#else
a2fa3e9f
GH		 817 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
818 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 819#endif
707c0874
AK		 820
821#ifdef CONFIG_X86_64
44ea2b17
AK		 822 if (is_long_mode(&vmx->vcpu)) {
823 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
824 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
825 }
707c0874 826#endif
26bb0981
AK		 827 for (i = 0; i < vmx->save_nmsrs; ++i)
828 kvm_set_shared_msr(vmx->guest_msrs[i].index,
d5696725
AK		 829 vmx->guest_msrs[i].data,
830 vmx->guest_msrs[i].mask);
33ed6329
AK		 831}
832
a9b21b62 833static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 834{
15ad7146 835 unsigned long flags;
33ed6329 836
a2fa3e9f 837 if (!vmx->host_state.loaded)
33ed6329
AK		 838 return;
839
e1beb1d3 840 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 841 vmx->host_state.loaded = 0;
152d3f2f 842 if (vmx->host_state.fs_reload_needed)
d6e88aec 843 kvm_load_fs(vmx->host_state.fs_sel);
152d3f2f 844 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 845 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329
AK		 846 /*
847 * If we have to reload gs, we must take care to
848 * preserve our gs base.
849 */
15ad7146 850 local_irq_save(flags);
d6e88aec 851 kvm_load_gs(vmx->host_state.gs_sel);
33ed6329
AK		 852#ifdef CONFIG_X86_64
853 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
854#endif
15ad7146 855 local_irq_restore(flags);
33ed6329 856 }
152d3f2f 857 reload_tss();
44ea2b17
AK		 858#ifdef CONFIG_X86_64
859 if (is_long_mode(&vmx->vcpu)) {
860 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
861 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
862 }
863#endif
1c11e713
AK		 864 if (current_thread_info()->status & TS_USEDFPU)
865 clts();
33ed6329
AK		 866}
867
a9b21b62
AK		 868static void vmx_load_host_state(struct vcpu_vmx *vmx)
869{
870 preempt_disable();
871 __vmx_load_host_state(vmx);
872 preempt_enable();
873}
874
6aa8b732
AK		 875/*
876 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
877 * vcpu mutex is already taken.
878 */
15ad7146 879static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 880{
a2fa3e9f 881 struct vcpu_vmx *vmx = to_vmx(vcpu);
019960ae 882 u64 tsc_this, delta, new_offset;
4610c9cc 883 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
6aa8b732 884
4610c9cc
DX		 885 if (!vmm_exclusive)
886 kvm_cpu_vmxon(phys_addr);
887 else if (vcpu->cpu != cpu)
8b9cf98c 888 vcpu_clear(vmx);
6aa8b732 889
a2fa3e9f 890 if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
a2fa3e9f 891 per_cpu(current_vmcs, cpu) = vmx->vmcs;
7725b894 892 vmcs_load(vmx->vmcs);
6aa8b732
AK		 893 }
894
895 if (vcpu->cpu != cpu) {
89a27f4d 896 struct desc_ptr dt;
6aa8b732
AK		 897 unsigned long sysenter_esp;
898
92fe13be
DX		 899 kvm_migrate_timers(vcpu);
900 set_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests);
901 local_irq_disable();
902 list_add(&vmx->local_vcpus_link,
903 &per_cpu(vcpus_on_cpu, cpu));
904 local_irq_enable();
905
6aa8b732
AK		 906 vcpu->cpu = cpu;
907 /*
908 * Linux uses per-cpu TSS and GDT, so set these when switching
909 * processors.
910 */
d6e88aec 911 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
d6ab1ed4 912 native_store_gdt(&dt);
89a27f4d 913 vmcs_writel(HOST_GDTR_BASE, dt.address); /* 22.2.4 */
6aa8b732
AK		 914
915 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
916 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
7700270e
AK		 917
918 /*
919 * Make sure the time stamp counter is monotonous.
920 */
921 rdtscll(tsc_this);
019960ae
AK		 922 if (tsc_this < vcpu->arch.host_tsc) {
923 delta = vcpu->arch.host_tsc - tsc_this;
924 new_offset = vmcs_read64(TSC_OFFSET) + delta;
925 vmcs_write64(TSC_OFFSET, new_offset);
926 }
6aa8b732 927 }
6aa8b732
AK		 928}
929
930static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
931{
a9b21b62 932 __vmx_load_host_state(to_vmx(vcpu));
4610c9cc 933 if (!vmm_exclusive) {
b923e62e 934 __vcpu_clear(to_vmx(vcpu));
4610c9cc
DX		 935 kvm_cpu_vmxoff();
936 }
6aa8b732
AK		 937}
938
5fd86fcf
AK		 939static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
940{
81231c69
AK		 941 ulong cr0;
942
5fd86fcf
AK		 943 if (vcpu->fpu_active)
944 return;
945 vcpu->fpu_active = 1;
81231c69
AK		 946 cr0 = vmcs_readl(GUEST_CR0);
947 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
948 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
949 vmcs_writel(GUEST_CR0, cr0);
5fd86fcf 950 update_exception_bitmap(vcpu);
edcafe3c
AK		 951 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
952 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
5fd86fcf
AK		 953}
954
edcafe3c
AK		 955static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
956
5fd86fcf
AK		 957static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
958{
edcafe3c 959 vmx_decache_cr0_guest_bits(vcpu);
81231c69 960 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
5fd86fcf 961 update_exception_bitmap(vcpu);
edcafe3c
AK		 962 vcpu->arch.cr0_guest_owned_bits = 0;
963 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
964 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf
AK		 965}
966
6aa8b732
AK		 967static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
968{
78ac8b47 969 unsigned long rflags, save_rflags;
345dcaa8
AK		 970
971 rflags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 972 if (to_vmx(vcpu)->rmode.vm86_active) {
973 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
974 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
975 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
976 }
345dcaa8 977 return rflags;
6aa8b732
AK		 978}
979
980static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
981{
78ac8b47
AK		 982 if (to_vmx(vcpu)->rmode.vm86_active) {
983 to_vmx(vcpu)->rmode.save_rflags = rflags;
053de044 984 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 985 }
6aa8b732
AK		 986 vmcs_writel(GUEST_RFLAGS, rflags);
987}
988
2809f5d2
GC		 989static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
990{
991 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
992 int ret = 0;
993
994 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 995 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 996 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 997 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2
GC		 998
999 return ret & mask;
1000}
1001
1002static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1003{
1004 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1005 u32 interruptibility = interruptibility_old;
1006
1007 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1008
48005f64 1009 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 1010 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 1011 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC		 1012 interruptibility |= GUEST_INTR_STATE_STI;
1013
1014 if ((interruptibility != interruptibility_old))
1015 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1016}
1017
6aa8b732
AK		 1018static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1019{
1020 unsigned long rip;
6aa8b732 1021
5fdbf976 1022 rip = kvm_rip_read(vcpu);
6aa8b732 1023 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 1024 kvm_rip_write(vcpu, rip);
6aa8b732 1025
2809f5d2
GC		 1026 /* skipping an emulated instruction also counts */
1027 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 1028}
1029
298101da 1030static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 1031 bool has_error_code, u32 error_code,
1032 bool reinject)
298101da 1033{
77ab6db0 1034 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 1035 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 1036
8ab2d2e2 1037 if (has_error_code) {
77ab6db0 1038 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 1039 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1040 }
77ab6db0 1041
7ffd92c5 1042 if (vmx->rmode.vm86_active) {
77ab6db0
JK		 1043 vmx->rmode.irq.pending = true;
1044 vmx->rmode.irq.vector = nr;
1045 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
ae0bb3e0
GN		 1046 if (kvm_exception_is_soft(nr))
1047 vmx->rmode.irq.rip +=
1048 vmx->vcpu.arch.event_exit_inst_len;
8ab2d2e2
JK		 1049 intr_info |= INTR_TYPE_SOFT_INTR;
1050 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
77ab6db0
JK		 1051 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
1052 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
1053 return;
1054 }
1055
66fd3f7f
GN		 1056 if (kvm_exception_is_soft(nr)) {
1057 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1058 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 1059 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1060 } else
1061 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1062
1063 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
298101da
AK		 1064}
1065
4e47c7a6
SY		 1066static bool vmx_rdtscp_supported(void)
1067{
1068 return cpu_has_vmx_rdtscp();
1069}
1070
a75beee6
ED		 1071/*
1072 * Swap MSR entry in host/guest MSR entry array.
1073 */
8b9cf98c 1074static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 1075{
26bb0981 1076 struct shared_msr_entry tmp;
a2fa3e9f
GH		 1077
1078 tmp = vmx->guest_msrs[to];
1079 vmx->guest_msrs[to] = vmx->guest_msrs[from];
1080 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 1081}
1082
e38aea3e
AK		 1083/*
1084 * Set up the vmcs to automatically save and restore system
1085 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1086 * mode, as fiddling with msrs is very expensive.
1087 */
8b9cf98c 1088static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 1089{
26bb0981 1090 int save_nmsrs, index;
5897297b 1091 unsigned long *msr_bitmap;
e38aea3e 1092
33f9c505 1093 vmx_load_host_state(vmx);
a75beee6
ED		 1094 save_nmsrs = 0;
1095#ifdef CONFIG_X86_64
8b9cf98c 1096 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 1097 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 1098 if (index >= 0)
8b9cf98c
RR		 1099 move_msr_up(vmx, index, save_nmsrs++);
1100 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 1101 if (index >= 0)
8b9cf98c
RR		 1102 move_msr_up(vmx, index, save_nmsrs++);
1103 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 1104 if (index >= 0)
8b9cf98c 1105 move_msr_up(vmx, index, save_nmsrs++);
4e47c7a6
SY		 1106 index = __find_msr_index(vmx, MSR_TSC_AUX);
1107 if (index >= 0 && vmx->rdtscp_enabled)
1108 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 1109 /*
1110 * MSR_K6_STAR is only needed on long mode guests, and only
1111 * if efer.sce is enabled.
1112 */
8b9cf98c 1113 index = __find_msr_index(vmx, MSR_K6_STAR);
f6801dff 1114 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
8b9cf98c 1115 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 1116 }
1117#endif
92c0d900
AK		 1118 index = __find_msr_index(vmx, MSR_EFER);
1119 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 1120 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 1121
26bb0981 1122 vmx->save_nmsrs = save_nmsrs;
5897297b
AK		 1123
1124 if (cpu_has_vmx_msr_bitmap()) {
1125 if (is_long_mode(&vmx->vcpu))
1126 msr_bitmap = vmx_msr_bitmap_longmode;
1127 else
1128 msr_bitmap = vmx_msr_bitmap_legacy;
1129
1130 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1131 }
e38aea3e
AK		 1132}
1133
6aa8b732
AK		 1134/*
1135 * reads and returns guest's timestamp counter "register"
1136 * guest_tsc = host_tsc + tsc_offset -- 21.3
1137 */
1138static u64 guest_read_tsc(void)
1139{
1140 u64 host_tsc, tsc_offset;
1141
1142 rdtscll(host_tsc);
1143 tsc_offset = vmcs_read64(TSC_OFFSET);
1144 return host_tsc + tsc_offset;
1145}
1146
1147/*
1148 * writes 'guest_tsc' into guest's timestamp counter "register"
1149 * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
1150 */
53f658b3 1151static void guest_write_tsc(u64 guest_tsc, u64 host_tsc)
6aa8b732 1152{
6aa8b732
AK		 1153 vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
1154}
1155
6aa8b732
AK		 1156/*
1157 * Reads an msr value (of 'msr_index') into 'pdata'.
1158 * Returns 0 on success, non-0 otherwise.
1159 * Assumes vcpu_load() was already called.
1160 */
1161static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1162{
1163 u64 data;
26bb0981 1164 struct shared_msr_entry *msr;
6aa8b732
AK		 1165
1166 if (!pdata) {
1167 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
1168 return -EINVAL;
1169 }
1170
1171 switch (msr_index) {
05b3e0c2 1172#ifdef CONFIG_X86_64
6aa8b732
AK		 1173 case MSR_FS_BASE:
1174 data = vmcs_readl(GUEST_FS_BASE);
1175 break;
1176 case MSR_GS_BASE:
1177 data = vmcs_readl(GUEST_GS_BASE);
1178 break;
44ea2b17
AK		 1179 case MSR_KERNEL_GS_BASE:
1180 vmx_load_host_state(to_vmx(vcpu));
1181 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
1182 break;
26bb0981 1183#endif
6aa8b732 1184 case MSR_EFER:
3bab1f5d 1185 return kvm_get_msr_common(vcpu, msr_index, pdata);
af24a4e4 1186 case MSR_IA32_TSC:
6aa8b732
AK		 1187 data = guest_read_tsc();
1188 break;
1189 case MSR_IA32_SYSENTER_CS:
1190 data = vmcs_read32(GUEST_SYSENTER_CS);
1191 break;
1192 case MSR_IA32_SYSENTER_EIP:
f5b42c33 1193 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 1194 break;
1195 case MSR_IA32_SYSENTER_ESP:
f5b42c33 1196 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 1197 break;
4e47c7a6
SY		 1198 case MSR_TSC_AUX:
1199 if (!to_vmx(vcpu)->rdtscp_enabled)
1200 return 1;
1201 /* Otherwise falls through */
6aa8b732 1202 default:
26bb0981 1203 vmx_load_host_state(to_vmx(vcpu));
8b9cf98c 1204 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d 1205 if (msr) {
542423b0 1206 vmx_load_host_state(to_vmx(vcpu));
3bab1f5d
AK		 1207 data = msr->data;
1208 break;
6aa8b732 1209 }
3bab1f5d 1210 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 1211 }
1212
1213 *pdata = data;
1214 return 0;
1215}
1216
1217/*
1218 * Writes msr value into into the appropriate "register".
1219 * Returns 0 on success, non-0 otherwise.
1220 * Assumes vcpu_load() was already called.
1221 */
1222static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
1223{
a2fa3e9f 1224 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1225 struct shared_msr_entry *msr;
53f658b3 1226 u64 host_tsc;
2cc51560
ED		 1227 int ret = 0;
1228
6aa8b732 1229 switch (msr_index) {
3bab1f5d 1230 case MSR_EFER:
a9b21b62 1231 vmx_load_host_state(vmx);
2cc51560 1232 ret = kvm_set_msr_common(vcpu, msr_index, data);
2cc51560 1233 break;
16175a79 1234#ifdef CONFIG_X86_64
6aa8b732
AK		 1235 case MSR_FS_BASE:
1236 vmcs_writel(GUEST_FS_BASE, data);
1237 break;
1238 case MSR_GS_BASE:
1239 vmcs_writel(GUEST_GS_BASE, data);
1240 break;
44ea2b17
AK		 1241 case MSR_KERNEL_GS_BASE:
1242 vmx_load_host_state(vmx);
1243 vmx->msr_guest_kernel_gs_base = data;
1244 break;
6aa8b732
AK		 1245#endif
1246 case MSR_IA32_SYSENTER_CS:
1247 vmcs_write32(GUEST_SYSENTER_CS, data);
1248 break;
1249 case MSR_IA32_SYSENTER_EIP:
f5b42c33 1250 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 1251 break;
1252 case MSR_IA32_SYSENTER_ESP:
f5b42c33 1253 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 1254 break;
af24a4e4 1255 case MSR_IA32_TSC:
53f658b3
MT		 1256 rdtscll(host_tsc);
1257 guest_write_tsc(data, host_tsc);
6aa8b732 1258 break;
468d472f
SY		 1259 case MSR_IA32_CR_PAT:
1260 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
1261 vmcs_write64(GUEST_IA32_PAT, data);
1262 vcpu->arch.pat = data;
1263 break;
1264 }
4e47c7a6
SY		 1265 ret = kvm_set_msr_common(vcpu, msr_index, data);
1266 break;
1267 case MSR_TSC_AUX:
1268 if (!vmx->rdtscp_enabled)
1269 return 1;
1270 /* Check reserved bit, higher 32 bits should be zero */
1271 if ((data >> 32) != 0)
1272 return 1;
1273 /* Otherwise falls through */
6aa8b732 1274 default:
8b9cf98c 1275 msr = find_msr_entry(vmx, msr_index);
3bab1f5d 1276 if (msr) {
542423b0 1277 vmx_load_host_state(vmx);
3bab1f5d
AK		 1278 msr->data = data;
1279 break;
6aa8b732 1280 }
2cc51560 1281 ret = kvm_set_msr_common(vcpu, msr_index, data);
6aa8b732
AK		 1282 }
1283
2cc51560 1284 return ret;
6aa8b732
AK		 1285}
1286
5fdbf976 1287static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 1288{
5fdbf976
MT		 1289 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
1290 switch (reg) {
1291 case VCPU_REGS_RSP:
1292 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
1293 break;
1294 case VCPU_REGS_RIP:
1295 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
1296 break;
6de4f3ad
AK		 1297 case VCPU_EXREG_PDPTR:
1298 if (enable_ept)
1299 ept_save_pdptrs(vcpu);
1300 break;
5fdbf976
MT		 1301 default:
1302 break;
1303 }
6aa8b732
AK		 1304}
1305
355be0b9 1306static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
6aa8b732 1307{
ae675ef0
JK		 1308 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1309 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
1310 else
1311 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
1312
abd3f2d6 1313 update_exception_bitmap(vcpu);
6aa8b732
AK		 1314}
1315
1316static __init int cpu_has_kvm_support(void)
1317{
6210e37b 1318 return cpu_has_vmx();
6aa8b732
AK		 1319}
1320
1321static __init int vmx_disabled_by_bios(void)
1322{
1323 u64 msr;
1324
1325 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
cafd6659
SW		 1326 if (msr & FEATURE_CONTROL_LOCKED) {
1327 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
1328 && tboot_enabled())
1329 return 1;
1330 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
1331 && !tboot_enabled())
1332 return 1;
1333 }
1334
1335 return 0;
62b3ffb8 1336 /* locked but not enabled */
6aa8b732
AK		 1337}
1338
7725b894
DX		 1339static void kvm_cpu_vmxon(u64 addr)
1340{
1341 asm volatile (ASM_VMX_VMXON_RAX
1342 : : "a"(&addr), "m"(addr)
1343 : "memory", "cc");
1344}
1345
10474ae8 1346static int hardware_enable(void *garbage)
6aa8b732
AK		 1347{
1348 int cpu = raw_smp_processor_id();
1349 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
cafd6659 1350 u64 old, test_bits;
6aa8b732 1351
10474ae8
AG		 1352 if (read_cr4() & X86_CR4_VMXE)
1353 return -EBUSY;
1354
543e4243 1355 INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu));
6aa8b732 1356 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
cafd6659
SW		 1357
1358 test_bits = FEATURE_CONTROL_LOCKED;
1359 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
1360 if (tboot_enabled())
1361 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
1362
1363 if ((old & test_bits) != test_bits) {
6aa8b732 1364 /* enable and lock */
cafd6659
SW		 1365 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
1366 }
66aee91a 1367 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
10474ae8 1368
4610c9cc
DX		 1369 if (vmm_exclusive) {
1370 kvm_cpu_vmxon(phys_addr);
1371 ept_sync_global();
1372 }
10474ae8
AG		 1373
1374 return 0;
6aa8b732
AK		 1375}
1376
543e4243
AK		 1377static void vmclear_local_vcpus(void)
1378{
1379 int cpu = raw_smp_processor_id();
1380 struct vcpu_vmx *vmx, *n;
1381
1382 list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu),
1383 local_vcpus_link)
1384 __vcpu_clear(vmx);
1385}
1386
710ff4a8
EH		 1387
1388/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
1389 * tricks.
1390 */
1391static void kvm_cpu_vmxoff(void)
6aa8b732 1392{
4ecac3fd 1393 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
6aa8b732
AK		 1394}
1395
710ff4a8
EH		 1396static void hardware_disable(void *garbage)
1397{
4610c9cc
DX		 1398 if (vmm_exclusive) {
1399 vmclear_local_vcpus();
1400 kvm_cpu_vmxoff();
1401 }
7725b894 1402 write_cr4(read_cr4() & ~X86_CR4_VMXE);
710ff4a8
EH		 1403}
1404
1c3d14fe 1405static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 1406 u32 msr, u32 *result)
1c3d14fe
YS		 1407{
1408 u32 vmx_msr_low, vmx_msr_high;
1409 u32 ctl = ctl_min | ctl_opt;
1410
1411 rdmsr(msr, vmx_msr_low, vmx_msr_high);
1412
1413 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1414 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
1415
1416 /* Ensure minimum (required) set of control bits are supported. */
1417 if (ctl_min & ~ctl)
002c7f7c 1418 return -EIO;
1c3d14fe
YS		 1419
1420 *result = ctl;
1421 return 0;
1422}
1423
002c7f7c 1424static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 1425{
1426 u32 vmx_msr_low, vmx_msr_high;
d56f546d 1427 u32 min, opt, min2, opt2;
1c3d14fe
YS		 1428 u32 _pin_based_exec_control = 0;
1429 u32 _cpu_based_exec_control = 0;
f78e0e2e 1430 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 1431 u32 _vmexit_control = 0;
1432 u32 _vmentry_control = 0;
1433
1434 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
f08864b4 1435 opt = PIN_BASED_VIRTUAL_NMIS;
1c3d14fe
YS		 1436 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1437 &_pin_based_exec_control) < 0)
002c7f7c 1438 return -EIO;
1c3d14fe
YS		 1439
1440 min = CPU_BASED_HLT_EXITING |
1441#ifdef CONFIG_X86_64
1442 CPU_BASED_CR8_LOAD_EXITING |
1443 CPU_BASED_CR8_STORE_EXITING |
1444#endif
d56f546d
SY		 1445 CPU_BASED_CR3_LOAD_EXITING |
1446 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 1447 CPU_BASED_USE_IO_BITMAPS |
1448 CPU_BASED_MOV_DR_EXITING |
a7052897 1449 CPU_BASED_USE_TSC_OFFSETING |
59708670
SY		 1450 CPU_BASED_MWAIT_EXITING |
1451 CPU_BASED_MONITOR_EXITING |
a7052897 1452 CPU_BASED_INVLPG_EXITING;
f78e0e2e 1453 opt = CPU_BASED_TPR_SHADOW |
25c5f225 1454 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 1455 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 1456 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1457 &_cpu_based_exec_control) < 0)
002c7f7c 1458 return -EIO;
6e5d865c
YS		 1459#ifdef CONFIG_X86_64
1460 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1461 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1462 ~CPU_BASED_CR8_STORE_EXITING;
1463#endif
f78e0e2e 1464 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 1465 min2 = 0;
1466 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2384d2b3 1467 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 1468 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 1469 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 1470 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6
SY		 1471 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
1472 SECONDARY_EXEC_RDTSCP;
d56f546d
SY		 1473 if (adjust_vmx_controls(min2, opt2,
1474 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 1475 &_cpu_based_2nd_exec_control) < 0)
1476 return -EIO;
1477 }
1478#ifndef CONFIG_X86_64
1479 if (!(_cpu_based_2nd_exec_control &
1480 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1481 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1482#endif
d56f546d 1483 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 1484 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
1485 enabled */
5fff7d27
GN		 1486 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
1487 CPU_BASED_CR3_STORE_EXITING |
1488 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 1489 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1490 vmx_capability.ept, vmx_capability.vpid);
1491 }
1c3d14fe
YS		 1492
1493 min = 0;
1494#ifdef CONFIG_X86_64
1495 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1496#endif
468d472f 1497 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1c3d14fe
YS		 1498 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1499 &_vmexit_control) < 0)
002c7f7c 1500 return -EIO;
1c3d14fe 1501
468d472f
SY		 1502 min = 0;
1503 opt = VM_ENTRY_LOAD_IA32_PAT;
1c3d14fe
YS		 1504 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1505 &_vmentry_control) < 0)
002c7f7c 1506 return -EIO;
6aa8b732 1507
c68876fd 1508 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 1509
1510 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1511 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 1512 return -EIO;
1c3d14fe
YS		 1513
1514#ifdef CONFIG_X86_64
1515 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1516 if (vmx_msr_high & (1u<<16))
002c7f7c 1517 return -EIO;
1c3d14fe
YS		 1518#endif
1519
1520 /* Require Write-Back (WB) memory type for VMCS accesses. */
1521 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 1522 return -EIO;
1c3d14fe 1523
002c7f7c
YS		 1524 vmcs_conf->size = vmx_msr_high & 0x1fff;
1525 vmcs_conf->order = get_order(vmcs_config.size);
1526 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 1527
002c7f7c
YS		 1528 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1529 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 1530 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 1531 vmcs_conf->vmexit_ctrl = _vmexit_control;
1532 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe
YS		 1533
1534 return 0;
c68876fd 1535}
6aa8b732
AK		 1536
1537static struct vmcs *alloc_vmcs_cpu(int cpu)
1538{
1539 int node = cpu_to_node(cpu);
1540 struct page *pages;
1541 struct vmcs *vmcs;
1542
6484eb3e 1543 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 1544 if (!pages)
1545 return NULL;
1546 vmcs = page_address(pages);
1c3d14fe
YS		 1547 memset(vmcs, 0, vmcs_config.size);
1548 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 1549 return vmcs;
1550}
1551
1552static struct vmcs *alloc_vmcs(void)
1553{
d3b2c338 1554 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 1555}
1556
1557static void free_vmcs(struct vmcs *vmcs)
1558{
1c3d14fe 1559 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 1560}
1561
39959588 1562static void free_kvm_area(void)
6aa8b732
AK		 1563{
1564 int cpu;
1565
3230bb47 1566 for_each_possible_cpu(cpu) {
6aa8b732 1567 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 1568 per_cpu(vmxarea, cpu) = NULL;
1569 }
6aa8b732
AK		 1570}
1571
6aa8b732
AK		 1572static __init int alloc_kvm_area(void)
1573{
1574 int cpu;
1575
3230bb47 1576 for_each_possible_cpu(cpu) {
6aa8b732
AK		 1577 struct vmcs *vmcs;
1578
1579 vmcs = alloc_vmcs_cpu(cpu);
1580 if (!vmcs) {
1581 free_kvm_area();
1582 return -ENOMEM;
1583 }
1584
1585 per_cpu(vmxarea, cpu) = vmcs;
1586 }
1587 return 0;
1588}
1589
1590static __init int hardware_setup(void)
1591{
002c7f7c
YS		 1592 if (setup_vmcs_config(&vmcs_config) < 0)
1593 return -EIO;
50a37eb4
JR		 1594
1595 if (boot_cpu_has(X86_FEATURE_NX))
1596 kvm_enable_efer_bits(EFER_NX);
1597
93ba03c2
SY		 1598 if (!cpu_has_vmx_vpid())
1599 enable_vpid = 0;
1600
4bc9b982
SY		 1601 if (!cpu_has_vmx_ept() ||
1602 !cpu_has_vmx_ept_4levels()) {
93ba03c2 1603 enable_ept = 0;
3a624e29
NK		 1604 enable_unrestricted_guest = 0;
1605 }
1606
1607 if (!cpu_has_vmx_unrestricted_guest())
1608 enable_unrestricted_guest = 0;
93ba03c2
SY		 1609
1610 if (!cpu_has_vmx_flexpriority())
1611 flexpriority_enabled = 0;
1612
95ba8273
GN		 1613 if (!cpu_has_vmx_tpr_shadow())
1614 kvm_x86_ops->update_cr8_intercept = NULL;
1615
54dee993
MT		 1616 if (enable_ept && !cpu_has_vmx_ept_2m_page())
1617 kvm_disable_largepages();
1618
4b8d54f9
ZE		 1619 if (!cpu_has_vmx_ple())
1620 ple_gap = 0;
1621
6aa8b732
AK		 1622 return alloc_kvm_area();
1623}
1624
1625static __exit void hardware_unsetup(void)
1626{
1627 free_kvm_area();
1628}
1629
6aa8b732
AK		 1630static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1631{
1632 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1633
6af11b9e 1634 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
6aa8b732
AK		 1635 vmcs_write16(sf->selector, save->selector);
1636 vmcs_writel(sf->base, save->base);
1637 vmcs_write32(sf->limit, save->limit);
1638 vmcs_write32(sf->ar_bytes, save->ar);
1639 } else {
1640 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1641 << AR_DPL_SHIFT;
1642 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1643 }
1644}
1645
1646static void enter_pmode(struct kvm_vcpu *vcpu)
1647{
1648 unsigned long flags;
a89a8fb9 1649 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 1650
a89a8fb9 1651 vmx->emulation_required = 1;
7ffd92c5 1652 vmx->rmode.vm86_active = 0;
6aa8b732 1653
7ffd92c5
AK		 1654 vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
1655 vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
1656 vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
6aa8b732
AK		 1657
1658 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 1659 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1660 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK		 1661 vmcs_writel(GUEST_RFLAGS, flags);
1662
66aee91a
RR		 1663 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1664 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 1665
1666 update_exception_bitmap(vcpu);
1667
a89a8fb9
MG		 1668 if (emulate_invalid_guest_state)
1669 return;
1670
7ffd92c5
AK		 1671 fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
1672 fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
1673 fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
1674 fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
6aa8b732
AK		 1675
1676 vmcs_write16(GUEST_SS_SELECTOR, 0);
1677 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1678
1679 vmcs_write16(GUEST_CS_SELECTOR,
1680 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1681 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1682}
1683
d77c26fc 1684static gva_t rmode_tss_base(struct kvm *kvm)
6aa8b732 1685{
bfc6d222 1686 if (!kvm->arch.tss_addr) {
bc6678a3
MT		 1687 struct kvm_memslots *slots;
1688 gfn_t base_gfn;
1689
90d83dc3 1690 slots = kvm_memslots(kvm);
f495c6e5 1691 base_gfn = slots->memslots[0].base_gfn +
46a26bf5 1692 kvm->memslots->memslots[0].npages - 3;
cbc94022
IE		 1693 return base_gfn << PAGE_SHIFT;
1694 }
bfc6d222 1695 return kvm->arch.tss_addr;
6aa8b732
AK		 1696}
1697
1698static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1699{
1700 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1701
1702 save->selector = vmcs_read16(sf->selector);
1703 save->base = vmcs_readl(sf->base);
1704 save->limit = vmcs_read32(sf->limit);
1705 save->ar = vmcs_read32(sf->ar_bytes);
15b00f32
JK		 1706 vmcs_write16(sf->selector, save->base >> 4);
1707 vmcs_write32(sf->base, save->base & 0xfffff);
6aa8b732
AK		 1708 vmcs_write32(sf->limit, 0xffff);
1709 vmcs_write32(sf->ar_bytes, 0xf3);
1710}
1711
1712static void enter_rmode(struct kvm_vcpu *vcpu)
1713{
1714 unsigned long flags;
a89a8fb9 1715 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 1716
3a624e29
NK		 1717 if (enable_unrestricted_guest)
1718 return;
1719
a89a8fb9 1720 vmx->emulation_required = 1;
7ffd92c5 1721 vmx->rmode.vm86_active = 1;
6aa8b732 1722
7ffd92c5 1723 vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
6aa8b732
AK		 1724 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1725
7ffd92c5 1726 vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
6aa8b732
AK		 1727 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1728
7ffd92c5 1729 vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
6aa8b732
AK		 1730 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1731
1732 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 1733 vmx->rmode.save_rflags = flags;
6aa8b732 1734
053de044 1735 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 1736
1737 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 1738 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 1739 update_exception_bitmap(vcpu);
1740
a89a8fb9
MG		 1741 if (emulate_invalid_guest_state)
1742 goto continue_rmode;
1743
6aa8b732
AK		 1744 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1745 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1746 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1747
1748 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
abacf8df 1749 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
8cb5b033
AK		 1750 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1751 vmcs_writel(GUEST_CS_BASE, 0xf0000);
6aa8b732
AK		 1752 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1753
7ffd92c5
AK		 1754 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
1755 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
1756 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
1757 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
75880a01 1758
a89a8fb9 1759continue_rmode:
8668a3c4 1760 kvm_mmu_reset_context(vcpu);
b7ebfb05 1761 init_rmode(vcpu->kvm);
6aa8b732
AK		 1762}
1763
401d10de
AS		 1764static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1765{
1766 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 1767 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1768
1769 if (!msr)
1770 return;
401d10de 1771
44ea2b17
AK		 1772 /*
1773 * Force kernel_gs_base reloading before EFER changes, as control
1774 * of this msr depends on is_long_mode().
1775 */
1776 vmx_load_host_state(to_vmx(vcpu));
f6801dff 1777 vcpu->arch.efer = efer;
401d10de
AS		 1778 if (efer & EFER_LMA) {
1779 vmcs_write32(VM_ENTRY_CONTROLS,
1780 vmcs_read32(VM_ENTRY_CONTROLS) |
1781 VM_ENTRY_IA32E_MODE);
1782 msr->data = efer;
1783 } else {
1784 vmcs_write32(VM_ENTRY_CONTROLS,
1785 vmcs_read32(VM_ENTRY_CONTROLS) &
1786 ~VM_ENTRY_IA32E_MODE);
1787
1788 msr->data = efer & ~EFER_LME;
1789 }
1790 setup_msrs(vmx);
1791}
1792
05b3e0c2 1793#ifdef CONFIG_X86_64
6aa8b732
AK		 1794
1795static void enter_lmode(struct kvm_vcpu *vcpu)
1796{
1797 u32 guest_tr_ar;
1798
1799 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1800 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1801 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
b8688d51 1802 __func__);
6aa8b732
AK		 1803 vmcs_write32(GUEST_TR_AR_BYTES,
1804 (guest_tr_ar & ~AR_TYPE_MASK)
1805 | AR_TYPE_BUSY_64_TSS);
1806 }
da38f438 1807 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
6aa8b732
AK		 1808}
1809
1810static void exit_lmode(struct kvm_vcpu *vcpu)
1811{
6aa8b732
AK		 1812 vmcs_write32(VM_ENTRY_CONTROLS,
1813 vmcs_read32(VM_ENTRY_CONTROLS)
1e4e6e00 1814 & ~VM_ENTRY_IA32E_MODE);
da38f438 1815 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
6aa8b732
AK		 1816}
1817
1818#endif
1819
2384d2b3
SY		 1820static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1821{
b9d762fa 1822 vpid_sync_context(to_vmx(vcpu));
089d034e 1823 if (enable_ept)
4e1096d2 1824 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
2384d2b3
SY		 1825}
1826
e8467fda
AK		 1827static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1828{
1829 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
1830
1831 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
1832 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
1833}
1834
25c4c276 1835static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 1836{
fc78f519
AK		 1837 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
1838
1839 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
1840 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 1841}
1842
1439442c
SY		 1843static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
1844{
6de4f3ad
AK		 1845 if (!test_bit(VCPU_EXREG_PDPTR,
1846 (unsigned long *)&vcpu->arch.regs_dirty))
1847 return;
1848
1439442c 1849 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1439442c
SY		 1850 vmcs_write64(GUEST_PDPTR0, vcpu->arch.pdptrs[0]);
1851 vmcs_write64(GUEST_PDPTR1, vcpu->arch.pdptrs[1]);
1852 vmcs_write64(GUEST_PDPTR2, vcpu->arch.pdptrs[2]);
1853 vmcs_write64(GUEST_PDPTR3, vcpu->arch.pdptrs[3]);
1854 }
1855}
1856
8f5d549f
AK		 1857static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
1858{
1859 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1860 vcpu->arch.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
1861 vcpu->arch.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
1862 vcpu->arch.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
1863 vcpu->arch.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
1864 }
6de4f3ad
AK		 1865
1866 __set_bit(VCPU_EXREG_PDPTR,
1867 (unsigned long *)&vcpu->arch.regs_avail);
1868 __set_bit(VCPU_EXREG_PDPTR,
1869 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 1870}
1871
1439442c
SY		 1872static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1873
1874static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
1875 unsigned long cr0,
1876 struct kvm_vcpu *vcpu)
1877{
1878 if (!(cr0 & X86_CR0_PG)) {
1879 /* From paging/starting to nonpaging */
1880 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 1881 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 1882 (CPU_BASED_CR3_LOAD_EXITING |
1883 CPU_BASED_CR3_STORE_EXITING));
1884 vcpu->arch.cr0 = cr0;
fc78f519 1885 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 1886 } else if (!is_paging(vcpu)) {
1887 /* From nonpaging to paging */
1888 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 1889 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 1890 ~(CPU_BASED_CR3_LOAD_EXITING |
1891 CPU_BASED_CR3_STORE_EXITING));
1892 vcpu->arch.cr0 = cr0;
fc78f519 1893 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 1894 }
95eb84a7
SY		 1895
1896 if (!(cr0 & X86_CR0_WP))
1897 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 1898}
1899
6aa8b732
AK		 1900static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1901{
7ffd92c5 1902 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 1903 unsigned long hw_cr0;
1904
1905 if (enable_unrestricted_guest)
1906 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
1907 | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
1908 else
1909 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
1439442c 1910
7ffd92c5 1911 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
6aa8b732
AK		 1912 enter_pmode(vcpu);
1913
7ffd92c5 1914 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
6aa8b732
AK		 1915 enter_rmode(vcpu);
1916
05b3e0c2 1917#ifdef CONFIG_X86_64
f6801dff 1918 if (vcpu->arch.efer & EFER_LME) {
707d92fa 1919 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 1920 enter_lmode(vcpu);
707d92fa 1921 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 1922 exit_lmode(vcpu);
1923 }
1924#endif
1925
089d034e 1926 if (enable_ept)
1439442c
SY		 1927 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
1928
02daab21 1929 if (!vcpu->fpu_active)
81231c69 1930 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
02daab21 1931
6aa8b732 1932 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 1933 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 1934 vcpu->arch.cr0 = cr0;
6aa8b732
AK		 1935}
1936
1439442c
SY		 1937static u64 construct_eptp(unsigned long root_hpa)
1938{
1939 u64 eptp;
1940
1941 /* TODO write the value reading from MSR */
1942 eptp = VMX_EPT_DEFAULT_MT |
1943 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
1944 eptp |= (root_hpa & PAGE_MASK);
1945
1946 return eptp;
1947}
1948
6aa8b732
AK		 1949static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1950{
1439442c
SY		 1951 unsigned long guest_cr3;
1952 u64 eptp;
1953
1954 guest_cr3 = cr3;
089d034e 1955 if (enable_ept) {
1439442c
SY		 1956 eptp = construct_eptp(cr3);
1957 vmcs_write64(EPT_POINTER, eptp);
1439442c 1958 guest_cr3 = is_paging(vcpu) ? vcpu->arch.cr3 :
b927a3ce 1959 vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 1960 ept_load_pdptrs(vcpu);
1439442c
SY		 1961 }
1962
2384d2b3 1963 vmx_flush_tlb(vcpu);
1439442c 1964 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK		 1965}
1966
1967static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1968{
7ffd92c5 1969 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1439442c
SY		 1970 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1971
ad312c7c 1972 vcpu->arch.cr4 = cr4;
bc23008b
AK		 1973 if (enable_ept) {
1974 if (!is_paging(vcpu)) {
1975 hw_cr4 &= ~X86_CR4_PAE;
1976 hw_cr4 |= X86_CR4_PSE;
1977 } else if (!(cr4 & X86_CR4_PAE)) {
1978 hw_cr4 &= ~X86_CR4_PAE;
1979 }
1980 }
1439442c
SY		 1981
1982 vmcs_writel(CR4_READ_SHADOW, cr4);
1983 vmcs_writel(GUEST_CR4, hw_cr4);
6aa8b732
AK		 1984}
1985
6aa8b732
AK		 1986static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1987{
1988 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1989
1990 return vmcs_readl(sf->base);
1991}
1992
1993static void vmx_get_segment(struct kvm_vcpu *vcpu,
1994 struct kvm_segment *var, int seg)
1995{
1996 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1997 u32 ar;
1998
1999 var->base = vmcs_readl(sf->base);
2000 var->limit = vmcs_read32(sf->limit);
2001 var->selector = vmcs_read16(sf->selector);
2002 ar = vmcs_read32(sf->ar_bytes);
9fd4a3b7 2003 if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
6aa8b732
AK		 2004 ar = 0;
2005 var->type = ar & 15;
2006 var->s = (ar >> 4) & 1;
2007 var->dpl = (ar >> 5) & 3;
2008 var->present = (ar >> 7) & 1;
2009 var->avl = (ar >> 12) & 1;
2010 var->l = (ar >> 13) & 1;
2011 var->db = (ar >> 14) & 1;
2012 var->g = (ar >> 15) & 1;
2013 var->unusable = (ar >> 16) & 1;
2014}
2015
2e4d2653
IE		 2016static int vmx_get_cpl(struct kvm_vcpu *vcpu)
2017{
3eeb3288 2018 if (!is_protmode(vcpu))
2e4d2653
IE		 2019 return 0;
2020
2021 if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */
2022 return 3;
2023
eab4b8aa 2024 return vmcs_read16(GUEST_CS_SELECTOR) & 3;
2e4d2653
IE		 2025}
2026
653e3108 2027static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 2028{
6aa8b732
AK		 2029 u32 ar;
2030
653e3108 2031 if (var->unusable)
6aa8b732
AK		 2032 ar = 1 << 16;
2033 else {
2034 ar = var->type & 15;
2035 ar |= (var->s & 1) << 4;
2036 ar |= (var->dpl & 3) << 5;
2037 ar |= (var->present & 1) << 7;
2038 ar |= (var->avl & 1) << 12;
2039 ar |= (var->l & 1) << 13;
2040 ar |= (var->db & 1) << 14;
2041 ar |= (var->g & 1) << 15;
2042 }
f7fbf1fd
UL		 2043 if (ar == 0) /* a 0 value means unusable */
2044 ar = AR_UNUSABLE_MASK;
653e3108
AK		 2045
2046 return ar;
2047}
2048
2049static void vmx_set_segment(struct kvm_vcpu *vcpu,
2050 struct kvm_segment *var, int seg)
2051{
7ffd92c5 2052 struct vcpu_vmx *vmx = to_vmx(vcpu);
653e3108
AK		 2053 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2054 u32 ar;
2055
7ffd92c5
AK		 2056 if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
2057 vmx->rmode.tr.selector = var->selector;
2058 vmx->rmode.tr.base = var->base;
2059 vmx->rmode.tr.limit = var->limit;
2060 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
653e3108
AK		 2061 return;
2062 }
2063 vmcs_writel(sf->base, var->base);
2064 vmcs_write32(sf->limit, var->limit);
2065 vmcs_write16(sf->selector, var->selector);
7ffd92c5 2066 if (vmx->rmode.vm86_active && var->s) {
653e3108
AK		 2067 /*
2068 * Hack real-mode segments into vm86 compatibility.
2069 */
2070 if (var->base == 0xffff0000 && var->selector == 0xf000)
2071 vmcs_writel(sf->base, 0xf0000);
2072 ar = 0xf3;
2073 } else
2074 ar = vmx_segment_access_rights(var);
3a624e29
NK		 2075
2076 /*
2077 * Fix the "Accessed" bit in AR field of segment registers for older
2078 * qemu binaries.
2079 * IA32 arch specifies that at the time of processor reset the
2080 * "Accessed" bit in the AR field of segment registers is 1. And qemu
2081 * is setting it to 0 in the usedland code. This causes invalid guest
2082 * state vmexit when "unrestricted guest" mode is turned on.
2083 * Fix for this setup issue in cpu_reset is being pushed in the qemu
2084 * tree. Newer qemu binaries with that qemu fix would not need this
2085 * kvm hack.
2086 */
2087 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
2088 ar |= 0x1; /* Accessed */
2089
6aa8b732
AK		 2090 vmcs_write32(sf->ar_bytes, ar);
2091}
2092
6aa8b732
AK		 2093static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
2094{
2095 u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
2096
2097 *db = (ar >> 14) & 1;
2098 *l = (ar >> 13) & 1;
2099}
2100
89a27f4d 2101static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 2102{
89a27f4d
GN		 2103 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
2104 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK		 2105}
2106
89a27f4d 2107static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 2108{
89a27f4d
GN		 2109 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
2110 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK		 2111}
2112
89a27f4d 2113static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 2114{
89a27f4d
GN		 2115 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
2116 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK		 2117}
2118
89a27f4d 2119static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 2120{
89a27f4d
GN		 2121 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
2122 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK		 2123}
2124
648dfaa7
MG		 2125static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
2126{
2127 struct kvm_segment var;
2128 u32 ar;
2129
2130 vmx_get_segment(vcpu, &var, seg);
2131 ar = vmx_segment_access_rights(&var);
2132
2133 if (var.base != (var.selector << 4))
2134 return false;
2135 if (var.limit != 0xffff)
2136 return false;
2137 if (ar != 0xf3)
2138 return false;
2139
2140 return true;
2141}
2142
2143static bool code_segment_valid(struct kvm_vcpu *vcpu)
2144{
2145 struct kvm_segment cs;
2146 unsigned int cs_rpl;
2147
2148 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2149 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
2150
1872a3f4
AK		 2151 if (cs.unusable)
2152 return false;
648dfaa7
MG		 2153 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
2154 return false;
2155 if (!cs.s)
2156 return false;
1872a3f4 2157 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 2158 if (cs.dpl > cs_rpl)
2159 return false;
1872a3f4 2160 } else {
648dfaa7
MG		 2161 if (cs.dpl != cs_rpl)
2162 return false;
2163 }
2164 if (!cs.present)
2165 return false;
2166
2167 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
2168 return true;
2169}
2170
2171static bool stack_segment_valid(struct kvm_vcpu *vcpu)
2172{
2173 struct kvm_segment ss;
2174 unsigned int ss_rpl;
2175
2176 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2177 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
2178
1872a3f4
AK		 2179 if (ss.unusable)
2180 return true;
2181 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 2182 return false;
2183 if (!ss.s)
2184 return false;
2185 if (ss.dpl != ss_rpl) /* DPL != RPL */
2186 return false;
2187 if (!ss.present)
2188 return false;
2189
2190 return true;
2191}
2192
2193static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
2194{
2195 struct kvm_segment var;
2196 unsigned int rpl;
2197
2198 vmx_get_segment(vcpu, &var, seg);
2199 rpl = var.selector & SELECTOR_RPL_MASK;
2200
1872a3f4
AK		 2201 if (var.unusable)
2202 return true;
648dfaa7
MG		 2203 if (!var.s)
2204 return false;
2205 if (!var.present)
2206 return false;
2207 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
2208 if (var.dpl < rpl) /* DPL < RPL */
2209 return false;
2210 }
2211
2212 /* TODO: Add other members to kvm_segment_field to allow checking for other access
2213 * rights flags
2214 */
2215 return true;
2216}
2217
2218static bool tr_valid(struct kvm_vcpu *vcpu)
2219{
2220 struct kvm_segment tr;
2221
2222 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
2223
1872a3f4
AK		 2224 if (tr.unusable)
2225 return false;
648dfaa7
MG		 2226 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
2227 return false;
1872a3f4 2228 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 2229 return false;
2230 if (!tr.present)
2231 return false;
2232
2233 return true;
2234}
2235
2236static bool ldtr_valid(struct kvm_vcpu *vcpu)
2237{
2238 struct kvm_segment ldtr;
2239
2240 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
2241
1872a3f4
AK		 2242 if (ldtr.unusable)
2243 return true;
648dfaa7
MG		 2244 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
2245 return false;
2246 if (ldtr.type != 2)
2247 return false;
2248 if (!ldtr.present)
2249 return false;
2250
2251 return true;
2252}
2253
2254static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
2255{
2256 struct kvm_segment cs, ss;
2257
2258 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2259 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2260
2261 return ((cs.selector & SELECTOR_RPL_MASK) ==
2262 (ss.selector & SELECTOR_RPL_MASK));
2263}
2264
2265/*
2266 * Check if guest state is valid. Returns true if valid, false if
2267 * not.
2268 * We assume that registers are always usable
2269 */
2270static bool guest_state_valid(struct kvm_vcpu *vcpu)
2271{
2272 /* real mode guest state checks */
3eeb3288 2273 if (!is_protmode(vcpu)) {
648dfaa7
MG		 2274 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
2275 return false;
2276 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
2277 return false;
2278 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
2279 return false;
2280 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
2281 return false;
2282 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
2283 return false;
2284 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
2285 return false;
2286 } else {
2287 /* protected mode guest state checks */
2288 if (!cs_ss_rpl_check(vcpu))
2289 return false;
2290 if (!code_segment_valid(vcpu))
2291 return false;
2292 if (!stack_segment_valid(vcpu))
2293 return false;
2294 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
2295 return false;
2296 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
2297 return false;
2298 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
2299 return false;
2300 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
2301 return false;
2302 if (!tr_valid(vcpu))
2303 return false;
2304 if (!ldtr_valid(vcpu))
2305 return false;
2306 }
2307 /* TODO:
2308 * - Add checks on RIP
2309 * - Add checks on RFLAGS
2310 */
2311
2312 return true;
2313}
2314
d77c26fc 2315static int init_rmode_tss(struct kvm *kvm)
6aa8b732 2316{
6aa8b732 2317 gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
195aefde 2318 u16 data = 0;
10589a46 2319 int ret = 0;
195aefde 2320 int r;
6aa8b732 2321
195aefde
IE		 2322 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2323 if (r < 0)
10589a46 2324 goto out;
195aefde 2325 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 2326 r = kvm_write_guest_page(kvm, fn++, &data,
2327 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 2328 if (r < 0)
10589a46 2329 goto out;
195aefde
IE		 2330 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
2331 if (r < 0)
10589a46 2332 goto out;
195aefde
IE		 2333 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2334 if (r < 0)
10589a46 2335 goto out;
195aefde 2336 data = ~0;
10589a46
MT		 2337 r = kvm_write_guest_page(kvm, fn, &data,
2338 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
2339 sizeof(u8));
195aefde 2340 if (r < 0)
10589a46
MT		 2341 goto out;
2342
2343 ret = 1;
2344out:
10589a46 2345 return ret;
6aa8b732
AK		 2346}
2347
b7ebfb05
SY		 2348static int init_rmode_identity_map(struct kvm *kvm)
2349{
2350 int i, r, ret;
2351 pfn_t identity_map_pfn;
2352 u32 tmp;
2353
089d034e 2354 if (!enable_ept)
b7ebfb05
SY		 2355 return 1;
2356 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
2357 printk(KERN_ERR "EPT: identity-mapping pagetable "
2358 "haven't been allocated!\n");
2359 return 0;
2360 }
2361 if (likely(kvm->arch.ept_identity_pagetable_done))
2362 return 1;
2363 ret = 0;
b927a3ce 2364 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
b7ebfb05
SY		 2365 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
2366 if (r < 0)
2367 goto out;
2368 /* Set up identity-mapping pagetable for EPT in real mode */
2369 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
2370 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
2371 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
2372 r = kvm_write_guest_page(kvm, identity_map_pfn,
2373 &tmp, i * sizeof(tmp), sizeof(tmp));
2374 if (r < 0)
2375 goto out;
2376 }
2377 kvm->arch.ept_identity_pagetable_done = true;
2378 ret = 1;
2379out:
2380 return ret;
2381}
2382
6aa8b732
AK		 2383static void seg_setup(int seg)
2384{
2385 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 2386 unsigned int ar;
6aa8b732
AK		 2387
2388 vmcs_write16(sf->selector, 0);
2389 vmcs_writel(sf->base, 0);
2390 vmcs_write32(sf->limit, 0xffff);
3a624e29
NK		 2391 if (enable_unrestricted_guest) {
2392 ar = 0x93;
2393 if (seg == VCPU_SREG_CS)
2394 ar |= 0x08; /* code segment */
2395 } else
2396 ar = 0xf3;
2397
2398 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 2399}
2400
f78e0e2e
SY		 2401static int alloc_apic_access_page(struct kvm *kvm)
2402{
2403 struct kvm_userspace_memory_region kvm_userspace_mem;
2404 int r = 0;
2405
79fac95e 2406 mutex_lock(&kvm->slots_lock);
bfc6d222 2407 if (kvm->arch.apic_access_page)
f78e0e2e
SY		 2408 goto out;
2409 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
2410 kvm_userspace_mem.flags = 0;
2411 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
2412 kvm_userspace_mem.memory_size = PAGE_SIZE;
2413 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2414 if (r)
2415 goto out;
72dc67a6 2416
bfc6d222 2417 kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
f78e0e2e 2418out:
79fac95e 2419 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY		 2420 return r;
2421}
2422
b7ebfb05
SY		 2423static int alloc_identity_pagetable(struct kvm *kvm)
2424{
2425 struct kvm_userspace_memory_region kvm_userspace_mem;
2426 int r = 0;
2427
79fac95e 2428 mutex_lock(&kvm->slots_lock);
b7ebfb05
SY		 2429 if (kvm->arch.ept_identity_pagetable)
2430 goto out;
2431 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
2432 kvm_userspace_mem.flags = 0;
b927a3ce
SY		 2433 kvm_userspace_mem.guest_phys_addr =
2434 kvm->arch.ept_identity_map_addr;
b7ebfb05
SY		 2435 kvm_userspace_mem.memory_size = PAGE_SIZE;
2436 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2437 if (r)
2438 goto out;
2439
b7ebfb05 2440 kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
b927a3ce 2441 kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
b7ebfb05 2442out:
79fac95e 2443 mutex_unlock(&kvm->slots_lock);
b7ebfb05
SY		 2444 return r;
2445}
2446
2384d2b3
SY		 2447static void allocate_vpid(struct vcpu_vmx *vmx)
2448{
2449 int vpid;
2450
2451 vmx->vpid = 0;
919818ab 2452 if (!enable_vpid)
2384d2b3
SY		 2453 return;
2454 spin_lock(&vmx_vpid_lock);
2455 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
2456 if (vpid < VMX_NR_VPIDS) {
2457 vmx->vpid = vpid;
2458 __set_bit(vpid, vmx_vpid_bitmap);
2459 }
2460 spin_unlock(&vmx_vpid_lock);
2461}
2462
cdbecfc3
LJ		 2463static void free_vpid(struct vcpu_vmx *vmx)
2464{
2465 if (!enable_vpid)
2466 return;
2467 spin_lock(&vmx_vpid_lock);
2468 if (vmx->vpid != 0)
2469 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
2470 spin_unlock(&vmx_vpid_lock);
2471}
2472
5897297b 2473static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
25c5f225 2474{
3e7c73e9 2475 int f = sizeof(unsigned long);
25c5f225
SY		 2476
2477 if (!cpu_has_vmx_msr_bitmap())
2478 return;
2479
2480 /*
2481 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2482 * have the write-low and read-high bitmap offsets the wrong way round.
2483 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2484 */
25c5f225 2485 if (msr <= 0x1fff) {
3e7c73e9
AK		 2486 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
2487 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
25c5f225
SY		 2488 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2489 msr &= 0x1fff;
3e7c73e9
AK		 2490 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
2491 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
25c5f225 2492 }
25c5f225
SY		 2493}
2494
5897297b
AK		 2495static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
2496{
2497 if (!longmode_only)
2498 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
2499 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
2500}
2501
6aa8b732
AK		 2502/*
2503 * Sets up the vmcs for emulated real mode.
2504 */
8b9cf98c 2505static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 2506{
468d472f 2507 u32 host_sysenter_cs, msr_low, msr_high;
6aa8b732 2508 u32 junk;
53f658b3 2509 u64 host_pat, tsc_this, tsc_base;
6aa8b732 2510 unsigned long a;
89a27f4d 2511 struct desc_ptr dt;
6aa8b732 2512 int i;
cd2276a7 2513 unsigned long kvm_vmx_return;
6e5d865c 2514 u32 exec_control;
6aa8b732 2515
6aa8b732 2516 /* I/O */
3e7c73e9
AK		 2517 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
2518 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 2519
25c5f225 2520 if (cpu_has_vmx_msr_bitmap())
5897297b 2521 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 2522
6aa8b732
AK		 2523 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
2524
6aa8b732 2525 /* Control */
1c3d14fe
YS		 2526 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
2527 vmcs_config.pin_based_exec_ctrl);
6e5d865c
YS		 2528
2529 exec_control = vmcs_config.cpu_based_exec_ctrl;
2530 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
2531 exec_control &= ~CPU_BASED_TPR_SHADOW;
2532#ifdef CONFIG_X86_64
2533 exec_control |= CPU_BASED_CR8_STORE_EXITING |
2534 CPU_BASED_CR8_LOAD_EXITING;
2535#endif
2536 }
089d034e 2537 if (!enable_ept)
d56f546d 2538 exec_control |= CPU_BASED_CR3_STORE_EXITING |
83dbc83a
MT		 2539 CPU_BASED_CR3_LOAD_EXITING |
2540 CPU_BASED_INVLPG_EXITING;
6e5d865c 2541 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
6aa8b732 2542
83ff3b9d
SY		 2543 if (cpu_has_secondary_exec_ctrls()) {
2544 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
2545 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2546 exec_control &=
2547 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2384d2b3
SY		 2548 if (vmx->vpid == 0)
2549 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
046d8710 2550 if (!enable_ept) {
d56f546d 2551 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
046d8710
SY		 2552 enable_unrestricted_guest = 0;
2553 }
3a624e29
NK		 2554 if (!enable_unrestricted_guest)
2555 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4b8d54f9
ZE		 2556 if (!ple_gap)
2557 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
83ff3b9d
SY		 2558 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
2559 }
f78e0e2e 2560
4b8d54f9
ZE		 2561 if (ple_gap) {
2562 vmcs_write32(PLE_GAP, ple_gap);
2563 vmcs_write32(PLE_WINDOW, ple_window);
2564 }
2565
c7addb90
AK		 2566 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
2567 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
6aa8b732
AK		 2568 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
2569
1c11e713 2570 vmcs_writel(HOST_CR0, read_cr0() | X86_CR0_TS); /* 22.2.3 */
6aa8b732
AK		 2571 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
2572 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
2573
2574 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
2575 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2576 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
d6e88aec
AK		 2577 vmcs_write16(HOST_FS_SELECTOR, kvm_read_fs()); /* 22.2.4 */
2578 vmcs_write16(HOST_GS_SELECTOR, kvm_read_gs()); /* 22.2.4 */
6aa8b732 2579 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
05b3e0c2 2580#ifdef CONFIG_X86_64
6aa8b732
AK		 2581 rdmsrl(MSR_FS_BASE, a);
2582 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
2583 rdmsrl(MSR_GS_BASE, a);
2584 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
2585#else
2586 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
2587 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
2588#endif
2589
2590 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
2591
ec68798c 2592 native_store_idt(&dt);
89a27f4d 2593 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
6aa8b732 2594
d77c26fc 2595 asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
cd2276a7 2596 vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2cc51560
ED		 2597 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
2598 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
61d2ef2c 2599 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2cc51560 2600 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
61d2ef2c 2601 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
6aa8b732
AK		 2602
2603 rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
2604 vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
2605 rdmsrl(MSR_IA32_SYSENTER_ESP, a);
2606 vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */
2607 rdmsrl(MSR_IA32_SYSENTER_EIP, a);
2608 vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */
2609
468d472f
SY		 2610 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
2611 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2612 host_pat = msr_low | ((u64) msr_high << 32);
2613 vmcs_write64(HOST_IA32_PAT, host_pat);
2614 }
2615 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2616 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2617 host_pat = msr_low | ((u64) msr_high << 32);
2618 /* Write the default value follow host pat */
2619 vmcs_write64(GUEST_IA32_PAT, host_pat);
2620 /* Keep arch.pat sync with GUEST_IA32_PAT */
2621 vmx->vcpu.arch.pat = host_pat;
2622 }
2623
6aa8b732
AK		 2624 for (i = 0; i < NR_VMX_MSR; ++i) {
2625 u32 index = vmx_msr_index[i];
2626 u32 data_low, data_high;
a2fa3e9f 2627 int j = vmx->nmsrs;
6aa8b732
AK		 2628
2629 if (rdmsr_safe(index, &data_low, &data_high) < 0)
2630 continue;
432bd6cb
AK		 2631 if (wrmsr_safe(index, data_low, data_high) < 0)
2632 continue;
26bb0981
AK		 2633 vmx->guest_msrs[j].index = i;
2634 vmx->guest_msrs[j].data = 0;
d5696725 2635 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 2636 ++vmx->nmsrs;
6aa8b732 2637 }
6aa8b732 2638
1c3d14fe 2639 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 2640
2641 /* 22.2.1, 20.8.1 */
1c3d14fe
YS		 2642 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
2643
e00c8cf2 2644 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
4c38609a 2645 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
ce03e4f2
AK		 2646 if (enable_ept)
2647 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
4c38609a 2648 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
e00c8cf2 2649
53f658b3
MT		 2650 tsc_base = vmx->vcpu.kvm->arch.vm_init_tsc;
2651 rdtscll(tsc_this);
2652 if (tsc_this < vmx->vcpu.kvm->arch.vm_init_tsc)
2653 tsc_base = tsc_this;
2654
2655 guest_write_tsc(0, tsc_base);
f78e0e2e 2656
e00c8cf2
AK		 2657 return 0;
2658}
2659
b7ebfb05
SY		 2660static int init_rmode(struct kvm *kvm)
2661{
4b9d3a04
XG		 2662 int idx, ret = 0;
2663
2664 idx = srcu_read_lock(&kvm->srcu);
b7ebfb05 2665 if (!init_rmode_tss(kvm))
4b9d3a04 2666 goto exit;
b7ebfb05 2667 if (!init_rmode_identity_map(kvm))
4b9d3a04
XG		 2668 goto exit;
2669
2670 ret = 1;
2671exit:
2672 srcu_read_unlock(&kvm->srcu, idx);
2673 return ret;
b7ebfb05
SY		 2674}
2675
e00c8cf2
AK		 2676static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
2677{
2678 struct vcpu_vmx *vmx = to_vmx(vcpu);
2679 u64 msr;
4b9d3a04 2680 int ret;
e00c8cf2 2681
5fdbf976 2682 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
b7ebfb05 2683 if (!init_rmode(vmx->vcpu.kvm)) {
e00c8cf2
AK		 2684 ret = -ENOMEM;
2685 goto out;
2686 }
2687
7ffd92c5 2688 vmx->rmode.vm86_active = 0;
e00c8cf2 2689
3b86cd99
JK		 2690 vmx->soft_vnmi_blocked = 0;
2691
ad312c7c 2692 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 2693 kvm_set_cr8(&vmx->vcpu, 0);
e00c8cf2 2694 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 2695 if (kvm_vcpu_is_bsp(&vmx->vcpu))
e00c8cf2
AK		 2696 msr |= MSR_IA32_APICBASE_BSP;
2697 kvm_set_apic_base(&vmx->vcpu, msr);
2698
10ab25cd
JK		 2699 ret = fx_init(&vmx->vcpu);
2700 if (ret != 0)
2701 goto out;
e00c8cf2 2702
5706be0d 2703 seg_setup(VCPU_SREG_CS);
e00c8cf2
AK		 2704 /*
2705 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2706 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
2707 */
c5af89b6 2708 if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
e00c8cf2
AK		 2709 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2710 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2711 } else {
ad312c7c
ZX		 2712 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2713 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
e00c8cf2 2714 }
e00c8cf2
AK		 2715
2716 seg_setup(VCPU_SREG_DS);
2717 seg_setup(VCPU_SREG_ES);
2718 seg_setup(VCPU_SREG_FS);
2719 seg_setup(VCPU_SREG_GS);
2720 seg_setup(VCPU_SREG_SS);
2721
2722 vmcs_write16(GUEST_TR_SELECTOR, 0);
2723 vmcs_writel(GUEST_TR_BASE, 0);
2724 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
2725 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2726
2727 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
2728 vmcs_writel(GUEST_LDTR_BASE, 0);
2729 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
2730 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
2731
2732 vmcs_write32(GUEST_SYSENTER_CS, 0);
2733 vmcs_writel(GUEST_SYSENTER_ESP, 0);
2734 vmcs_writel(GUEST_SYSENTER_EIP, 0);
2735
2736 vmcs_writel(GUEST_RFLAGS, 0x02);
c5af89b6 2737 if (kvm_vcpu_is_bsp(&vmx->vcpu))
5fdbf976 2738 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 2739 else
5fdbf976
MT		 2740 kvm_rip_write(vcpu, 0);
2741 kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
e00c8cf2 2742
e00c8cf2
AK		 2743 vmcs_writel(GUEST_DR7, 0x400);
2744
2745 vmcs_writel(GUEST_GDTR_BASE, 0);
2746 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
2747
2748 vmcs_writel(GUEST_IDTR_BASE, 0);
2749 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
2750
2751 vmcs_write32(GUEST_ACTIVITY_STATE, 0);
2752 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
2753 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
2754
e00c8cf2
AK		 2755 /* Special registers */
2756 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
2757
2758 setup_msrs(vmx);
2759
6aa8b732
AK		 2760 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
2761
f78e0e2e
SY		 2762 if (cpu_has_vmx_tpr_shadow()) {
2763 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
2764 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
2765 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
ad312c7c 2766 page_to_phys(vmx->vcpu.arch.apic->regs_page));
f78e0e2e
SY		 2767 vmcs_write32(TPR_THRESHOLD, 0);
2768 }
2769
2770 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2771 vmcs_write64(APIC_ACCESS_ADDR,
bfc6d222 2772 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
6aa8b732 2773
2384d2b3
SY		 2774 if (vmx->vpid != 0)
2775 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2776
fa40052c 2777 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4d4ec087 2778 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
8b9cf98c 2779 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 2780 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 2781 vmx_fpu_activate(&vmx->vcpu);
2782 update_exception_bitmap(&vmx->vcpu);
6aa8b732 2783
b9d762fa 2784 vpid_sync_context(vmx);
2384d2b3 2785
3200f405 2786 ret = 0;
6aa8b732 2787
a89a8fb9
MG		 2788 /* HACK: Don't enable emulation on guest boot/reset */
2789 vmx->emulation_required = 0;
2790
6aa8b732
AK		 2791out:
2792 return ret;
2793}
2794
3b86cd99
JK		 2795static void enable_irq_window(struct kvm_vcpu *vcpu)
2796{
2797 u32 cpu_based_vm_exec_control;
2798
2799 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2800 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2801 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2802}
2803
2804static void enable_nmi_window(struct kvm_vcpu *vcpu)
2805{
2806 u32 cpu_based_vm_exec_control;
2807
2808 if (!cpu_has_virtual_nmis()) {
2809 enable_irq_window(vcpu);
2810 return;
2811 }
2812
2813 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2814 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
2815 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2816}
2817
66fd3f7f 2818static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 2819{
9c8cba37 2820 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 2821 uint32_t intr;
2822 int irq = vcpu->arch.interrupt.nr;
9c8cba37 2823
229456fc 2824 trace_kvm_inj_virq(irq);
2714d1d3 2825
fa89a817 2826 ++vcpu->stat.irq_injections;
7ffd92c5 2827 if (vmx->rmode.vm86_active) {
9c8cba37
AK		 2828 vmx->rmode.irq.pending = true;
2829 vmx->rmode.irq.vector = irq;
5fdbf976 2830 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
ae0bb3e0
GN		 2831 if (vcpu->arch.interrupt.soft)
2832 vmx->rmode.irq.rip +=
2833 vmx->vcpu.arch.event_exit_inst_len;
9c5623e3
AK		 2834 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2835 irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK);
2836 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
5fdbf976 2837 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
85f455f7
ED		 2838 return;
2839 }
66fd3f7f
GN		 2840 intr = irq | INTR_INFO_VALID_MASK;
2841 if (vcpu->arch.interrupt.soft) {
2842 intr |= INTR_TYPE_SOFT_INTR;
2843 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2844 vmx->vcpu.arch.event_exit_inst_len);
2845 } else
2846 intr |= INTR_TYPE_EXT_INTR;
2847 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
85f455f7
ED		 2848}
2849
f08864b4
SY		 2850static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
2851{
66a5a347
JK		 2852 struct vcpu_vmx *vmx = to_vmx(vcpu);
2853
3b86cd99
JK		 2854 if (!cpu_has_virtual_nmis()) {
2855 /*
2856 * Tracking the NMI-blocked state in software is built upon
2857 * finding the next open IRQ window. This, in turn, depends on
2858 * well-behaving guests: They have to keep IRQs disabled at
2859 * least as long as the NMI handler runs. Otherwise we may
2860 * cause NMI nesting, maybe breaking the guest. But as this is
2861 * highly unlikely, we can live with the residual risk.
2862 */
2863 vmx->soft_vnmi_blocked = 1;
2864 vmx->vnmi_blocked_time = 0;
2865 }
2866
487b391d 2867 ++vcpu->stat.nmi_injections;
7ffd92c5 2868 if (vmx->rmode.vm86_active) {
66a5a347
JK		 2869 vmx->rmode.irq.pending = true;
2870 vmx->rmode.irq.vector = NMI_VECTOR;
2871 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2872 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2873 NMI_VECTOR | INTR_TYPE_SOFT_INTR |
2874 INTR_INFO_VALID_MASK);
2875 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2876 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2877 return;
2878 }
f08864b4
SY		 2879 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2880 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
f08864b4
SY		 2881}
2882
c4282df9 2883static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
33f089ca 2884{
3b86cd99 2885 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
c4282df9 2886 return 0;
33f089ca 2887
c4282df9 2888 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
f8c5fae1 2889 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_NMI));
33f089ca
JK		 2890}
2891
3cfc3092
JK		 2892static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
2893{
2894 if (!cpu_has_virtual_nmis())
2895 return to_vmx(vcpu)->soft_vnmi_blocked;
c332c83a 2896 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3cfc3092
JK		 2897}
2898
2899static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
2900{
2901 struct vcpu_vmx *vmx = to_vmx(vcpu);
2902
2903 if (!cpu_has_virtual_nmis()) {
2904 if (vmx->soft_vnmi_blocked != masked) {
2905 vmx->soft_vnmi_blocked = masked;
2906 vmx->vnmi_blocked_time = 0;
2907 }
2908 } else {
2909 if (masked)
2910 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
2911 GUEST_INTR_STATE_NMI);
2912 else
2913 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
2914 GUEST_INTR_STATE_NMI);
2915 }
2916}
2917
78646121
GN		 2918static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
2919{
c4282df9
GN		 2920 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2921 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2922 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 2923}
2924
cbc94022
IE		 2925static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
2926{
2927 int ret;
2928 struct kvm_userspace_memory_region tss_mem = {
6fe63979 2929 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 2930 .guest_phys_addr = addr,
2931 .memory_size = PAGE_SIZE * 3,
2932 .flags = 0,
2933 };
2934
2935 ret = kvm_set_memory_region(kvm, &tss_mem, 0);
2936 if (ret)
2937 return ret;
bfc6d222 2938 kvm->arch.tss_addr = addr;
cbc94022
IE		 2939 return 0;
2940}
2941
6aa8b732
AK		 2942static int handle_rmode_exception(struct kvm_vcpu *vcpu,
2943 int vec, u32 err_code)
2944{
b3f37707
NK		 2945 /*
2946 * Instruction with address size override prefix opcode 0x67
2947 * Cause the #SS fault with 0 error code in VM86 mode.
2948 */
2949 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
851ba692 2950 if (emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE)
6aa8b732 2951 return 1;
77ab6db0
JK		 2952 /*
2953 * Forward all other exceptions that are valid in real mode.
2954 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
2955 * the required debugging infrastructure rework.
2956 */
2957 switch (vec) {
77ab6db0 2958 case DB_VECTOR:
d0bfb940
JK		 2959 if (vcpu->guest_debug &
2960 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
2961 return 0;
2962 kvm_queue_exception(vcpu, vec);
2963 return 1;
77ab6db0 2964 case BP_VECTOR:
c573cd22
JK		 2965 /*
2966 * Update instruction length as we may reinject the exception
2967 * from user space while in guest debugging mode.
2968 */
2969 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
2970 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940
JK		 2971 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2972 return 0;
2973 /* fall through */
2974 case DE_VECTOR:
77ab6db0
JK		 2975 case OF_VECTOR:
2976 case BR_VECTOR:
2977 case UD_VECTOR:
2978 case DF_VECTOR:
2979 case SS_VECTOR:
2980 case GP_VECTOR:
2981 case MF_VECTOR:
2982 kvm_queue_exception(vcpu, vec);
2983 return 1;
2984 }
6aa8b732
AK		 2985 return 0;
2986}
2987
a0861c02
AK		 2988/*
2989 * Trigger machine check on the host. We assume all the MSRs are already set up
2990 * by the CPU and that we still run on the same CPU as the MCE occurred on.
2991 * We pass a fake environment to the machine check handler because we want
2992 * the guest to be always treated like user space, no matter what context
2993 * it used internally.
2994 */
2995static void kvm_machine_check(void)
2996{
2997#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
2998 struct pt_regs regs = {
2999 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
3000 .flags = X86_EFLAGS_IF,
3001 };
3002
3003 do_machine_check(&regs, 0);
3004#endif
3005}
3006
851ba692 3007static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK		 3008{
3009 /* already handled by vcpu_run */
3010 return 1;
3011}
3012
851ba692 3013static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 3014{
1155f76a 3015 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 3016 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 3017 u32 intr_info, ex_no, error_code;
42dbaa5a 3018 unsigned long cr2, rip, dr6;
6aa8b732
AK		 3019 u32 vect_info;
3020 enum emulation_result er;
3021
1155f76a 3022 vect_info = vmx->idt_vectoring_info;
6aa8b732
AK		 3023 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3024
a0861c02 3025 if (is_machine_check(intr_info))
851ba692 3026 return handle_machine_check(vcpu);
a0861c02 3027
6aa8b732 3028 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
65ac7264
AK		 3029 !is_page_fault(intr_info)) {
3030 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3031 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
3032 vcpu->run->internal.ndata = 2;
3033 vcpu->run->internal.data[0] = vect_info;
3034 vcpu->run->internal.data[1] = intr_info;
3035 return 0;
3036 }
6aa8b732 3037
e4a41889 3038 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 3039 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 3040
3041 if (is_no_device(intr_info)) {
5fd86fcf 3042 vmx_fpu_activate(vcpu);
2ab455cc
AL		 3043 return 1;
3044 }
3045
7aa81cc0 3046 if (is_invalid_opcode(intr_info)) {
851ba692 3047 er = emulate_instruction(vcpu, 0, 0, EMULTYPE_TRAP_UD);
7aa81cc0 3048 if (er != EMULATE_DONE)
7ee5d940 3049 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 3050 return 1;
3051 }
3052
6aa8b732 3053 error_code = 0;
5fdbf976 3054 rip = kvm_rip_read(vcpu);
2e11384c 3055 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732
AK		 3056 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
3057 if (is_page_fault(intr_info)) {
1439442c 3058 /* EPT won't cause page fault directly */
089d034e 3059 if (enable_ept)
1439442c 3060 BUG();
6aa8b732 3061 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT		 3062 trace_kvm_page_fault(cr2, error_code);
3063
3298b75c 3064 if (kvm_event_needs_reinjection(vcpu))
577bdc49 3065 kvm_mmu_unprotect_page_virt(vcpu, cr2);
3067714c 3066 return kvm_mmu_page_fault(vcpu, cr2, error_code);
6aa8b732
AK		 3067 }
3068
7ffd92c5 3069 if (vmx->rmode.vm86_active &&
6aa8b732 3070 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
72d6e5a0 3071 error_code)) {
ad312c7c
ZX		 3072 if (vcpu->arch.halt_request) {
3073 vcpu->arch.halt_request = 0;
72d6e5a0
AK		 3074 return kvm_emulate_halt(vcpu);
3075 }
6aa8b732 3076 return 1;
72d6e5a0 3077 }
6aa8b732 3078
d0bfb940 3079 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
42dbaa5a
JK		 3080 switch (ex_no) {
3081 case DB_VECTOR:
3082 dr6 = vmcs_readl(EXIT_QUALIFICATION);
3083 if (!(vcpu->guest_debug &
3084 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
3085 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
3086 kvm_queue_exception(vcpu, DB_VECTOR);
3087 return 1;
3088 }
3089 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
3090 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
3091 /* fall through */
3092 case BP_VECTOR:
c573cd22
JK		 3093 /*
3094 * Update instruction length as we may reinject #BP from
3095 * user space while in guest debugging mode. Reading it for
3096 * #DB as well causes no harm, it is not used in that case.
3097 */
3098 vmx->vcpu.arch.event_exit_inst_len =
3099 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 3100 kvm_run->exit_reason = KVM_EXIT_DEBUG;
d0bfb940
JK		 3101 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
3102 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 3103 break;
3104 default:
d0bfb940
JK		 3105 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
3106 kvm_run->ex.exception = ex_no;
3107 kvm_run->ex.error_code = error_code;
42dbaa5a 3108 break;
6aa8b732 3109 }
6aa8b732
AK		 3110 return 0;
3111}
3112
851ba692 3113static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 3114{
1165f5fe 3115 ++vcpu->stat.irq_exits;
6aa8b732
AK		 3116 return 1;
3117}
3118
851ba692 3119static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 3120{
851ba692 3121 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK		 3122 return 0;
3123}
6aa8b732 3124
851ba692 3125static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 3126{
bfdaab09 3127 unsigned long exit_qualification;
34c33d16 3128 int size, in, string;
039576c0 3129 unsigned port;
6aa8b732 3130
bfdaab09 3131 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 3132 string = (exit_qualification & 16) != 0;
cf8f70bf 3133 in = (exit_qualification & 8) != 0;
e70669ab 3134
cf8f70bf 3135 ++vcpu->stat.io_exits;
e70669ab 3136
cf8f70bf 3137 if (string || in)
6d77dbfc 3138 return emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE;
e70669ab 3139
cf8f70bf
GN		 3140 port = exit_qualification >> 16;
3141 size = (exit_qualification & 7) + 1;
e93f36bc 3142 skip_emulated_instruction(vcpu);
cf8f70bf
GN		 3143
3144 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 3145}
3146
102d8325
IM		 3147static void
3148vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3149{
3150 /*
3151 * Patch in the VMCALL instruction:
3152 */
3153 hypercall[0] = 0x0f;
3154 hypercall[1] = 0x01;
3155 hypercall[2] = 0xc1;
102d8325
IM		 3156}
3157
851ba692 3158static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 3159{
229456fc 3160 unsigned long exit_qualification, val;
6aa8b732
AK		 3161 int cr;
3162 int reg;
3163
bfdaab09 3164 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 3165 cr = exit_qualification & 15;
3166 reg = (exit_qualification >> 8) & 15;
3167 switch ((exit_qualification >> 4) & 3) {
3168 case 0: /* mov to cr */
229456fc
MT		 3169 val = kvm_register_read(vcpu, reg);
3170 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 3171 switch (cr) {
3172 case 0:
229456fc 3173 kvm_set_cr0(vcpu, val);
6aa8b732
AK		 3174 skip_emulated_instruction(vcpu);
3175 return 1;
3176 case 3:
229456fc 3177 kvm_set_cr3(vcpu, val);
6aa8b732
AK		 3178 skip_emulated_instruction(vcpu);
3179 return 1;
3180 case 4:
229456fc 3181 kvm_set_cr4(vcpu, val);
6aa8b732
AK		 3182 skip_emulated_instruction(vcpu);
3183 return 1;
0a5fff19
GN		 3184 case 8: {
3185 u8 cr8_prev = kvm_get_cr8(vcpu);
3186 u8 cr8 = kvm_register_read(vcpu, reg);
3187 kvm_set_cr8(vcpu, cr8);
3188 skip_emulated_instruction(vcpu);
3189 if (irqchip_in_kernel(vcpu->kvm))
3190 return 1;
3191 if (cr8_prev <= cr8)
3192 return 1;
851ba692 3193 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 3194 return 0;
3195 }
6aa8b732
AK		 3196 };
3197 break;
25c4c276 3198 case 2: /* clts */
edcafe3c 3199 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4d4ec087 3200 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
25c4c276 3201 skip_emulated_instruction(vcpu);
6b52d186 3202 vmx_fpu_activate(vcpu);
25c4c276 3203 return 1;
6aa8b732
AK		 3204 case 1: /*mov from cr*/
3205 switch (cr) {
3206 case 3:
5fdbf976 3207 kvm_register_write(vcpu, reg, vcpu->arch.cr3);
229456fc 3208 trace_kvm_cr_read(cr, vcpu->arch.cr3);
6aa8b732
AK		 3209 skip_emulated_instruction(vcpu);
3210 return 1;
3211 case 8:
229456fc
MT		 3212 val = kvm_get_cr8(vcpu);
3213 kvm_register_write(vcpu, reg, val);
3214 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 3215 skip_emulated_instruction(vcpu);
3216 return 1;
3217 }
3218 break;
3219 case 3: /* lmsw */
a1f83a74 3220 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 3221 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 3222 kvm_lmsw(vcpu, val);
6aa8b732
AK		 3223
3224 skip_emulated_instruction(vcpu);
3225 return 1;
3226 default:
3227 break;
3228 }
851ba692 3229 vcpu->run->exit_reason = 0;
f0242478 3230 pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 3231 (int)(exit_qualification >> 4) & 3, cr);
3232 return 0;
3233}
3234
851ba692 3235static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 3236{
bfdaab09 3237 unsigned long exit_qualification;
6aa8b732
AK		 3238 int dr, reg;
3239
f2483415 3240 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK		 3241 if (!kvm_require_cpl(vcpu, 0))
3242 return 1;
42dbaa5a
JK		 3243 dr = vmcs_readl(GUEST_DR7);
3244 if (dr & DR7_GD) {
3245 /*
3246 * As the vm-exit takes precedence over the debug trap, we
3247 * need to emulate the latter, either for the host or the
3248 * guest debugging itself.
3249 */
3250 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692
AK		 3251 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
3252 vcpu->run->debug.arch.dr7 = dr;
3253 vcpu->run->debug.arch.pc =
42dbaa5a
JK		 3254 vmcs_readl(GUEST_CS_BASE) +
3255 vmcs_readl(GUEST_RIP);
851ba692
AK		 3256 vcpu->run->debug.arch.exception = DB_VECTOR;
3257 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 3258 return 0;
3259 } else {
3260 vcpu->arch.dr7 &= ~DR7_GD;
3261 vcpu->arch.dr6 |= DR6_BD;
3262 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
3263 kvm_queue_exception(vcpu, DB_VECTOR);
3264 return 1;
3265 }
3266 }
3267
bfdaab09 3268 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
42dbaa5a
JK		 3269 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
3270 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
3271 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079
GN		 3272 unsigned long val;
3273 if (!kvm_get_dr(vcpu, dr, &val))
3274 kvm_register_write(vcpu, reg, val);
3275 } else
3276 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
6aa8b732
AK		 3277 skip_emulated_instruction(vcpu);
3278 return 1;
3279}
3280
020df079
GN		 3281static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
3282{
3283 vmcs_writel(GUEST_DR7, val);
3284}
3285
851ba692 3286static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 3287{
06465c5a
AK		 3288 kvm_emulate_cpuid(vcpu);
3289 return 1;
6aa8b732
AK		 3290}
3291
851ba692 3292static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 3293{
ad312c7c 3294 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 3295 u64 data;
3296
3297 if (vmx_get_msr(vcpu, ecx, &data)) {
59200273 3298 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 3299 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 3300 return 1;
3301 }
3302
229456fc 3303 trace_kvm_msr_read(ecx, data);
2714d1d3 3304
6aa8b732 3305 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 3306 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
3307 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 3308 skip_emulated_instruction(vcpu);
3309 return 1;
3310}
3311
851ba692 3312static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 3313{
ad312c7c
ZX		 3314 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3315 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
3316 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732
AK		 3317
3318 if (vmx_set_msr(vcpu, ecx, data) != 0) {
59200273 3319 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 3320 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 3321 return 1;
3322 }
3323
59200273 3324 trace_kvm_msr_write(ecx, data);
6aa8b732
AK		 3325 skip_emulated_instruction(vcpu);
3326 return 1;
3327}
3328
851ba692 3329static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c
YS		 3330{
3331 return 1;
3332}
3333
851ba692 3334static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 3335{
85f455f7
ED		 3336 u32 cpu_based_vm_exec_control;
3337
3338 /* clear pending irq */
3339 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3340 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
3341 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3 3342
a26bf12a 3343 ++vcpu->stat.irq_window_exits;
2714d1d3 3344
c1150d8c
DL		 3345 /*
3346 * If the user space waits to inject interrupts, exit as soon as
3347 * possible
3348 */
8061823a 3349 if (!irqchip_in_kernel(vcpu->kvm) &&
851ba692 3350 vcpu->run->request_interrupt_window &&
8061823a 3351 !kvm_cpu_has_interrupt(vcpu)) {
851ba692 3352 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
c1150d8c
DL		 3353 return 0;
3354 }
6aa8b732
AK		 3355 return 1;
3356}
3357
851ba692 3358static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732
AK		 3359{
3360 skip_emulated_instruction(vcpu);
d3bef15f 3361 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 3362}
3363
851ba692 3364static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 3365{
510043da 3366 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 3367 kvm_emulate_hypercall(vcpu);
3368 return 1;
c21415e8
IM		 3369}
3370
851ba692 3371static int handle_vmx_insn(struct kvm_vcpu *vcpu)
e3c7cb6a
AK		 3372{
3373 kvm_queue_exception(vcpu, UD_VECTOR);
3374 return 1;
3375}
3376
851ba692 3377static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 3378{
f9c617f6 3379 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 3380
3381 kvm_mmu_invlpg(vcpu, exit_qualification);
3382 skip_emulated_instruction(vcpu);
3383 return 1;
3384}
3385
851ba692 3386static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01
ED		 3387{
3388 skip_emulated_instruction(vcpu);
3389 /* TODO: Add support for VT-d/pass-through device */
3390 return 1;
3391}
3392
851ba692 3393static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 3394{
6d77dbfc 3395 return emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE;
f78e0e2e
SY		 3396}
3397
851ba692 3398static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 3399{
60637aac 3400 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 3401 unsigned long exit_qualification;
e269fb21
JK		 3402 bool has_error_code = false;
3403 u32 error_code = 0;
37817f29 3404 u16 tss_selector;
64a7ec06
GN		 3405 int reason, type, idt_v;
3406
3407 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
3408 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 3409
3410 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3411
3412 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 3413 if (reason == TASK_SWITCH_GATE && idt_v) {
3414 switch (type) {
3415 case INTR_TYPE_NMI_INTR:
3416 vcpu->arch.nmi_injected = false;
3417 if (cpu_has_virtual_nmis())
3418 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3419 GUEST_INTR_STATE_NMI);
3420 break;
3421 case INTR_TYPE_EXT_INTR:
66fd3f7f 3422 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 3423 kvm_clear_interrupt_queue(vcpu);
3424 break;
3425 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK		 3426 if (vmx->idt_vectoring_info &
3427 VECTORING_INFO_DELIVER_CODE_MASK) {
3428 has_error_code = true;
3429 error_code =
3430 vmcs_read32(IDT_VECTORING_ERROR_CODE);
3431 }
3432 /* fall through */
64a7ec06
GN		 3433 case INTR_TYPE_SOFT_EXCEPTION:
3434 kvm_clear_exception_queue(vcpu);
3435 break;
3436 default:
3437 break;
3438 }
60637aac 3439 }
37817f29
IE		 3440 tss_selector = exit_qualification;
3441
64a7ec06
GN		 3442 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
3443 type != INTR_TYPE_EXT_INTR &&
3444 type != INTR_TYPE_NMI_INTR))
3445 skip_emulated_instruction(vcpu);
3446
acb54517
GN		 3447 if (kvm_task_switch(vcpu, tss_selector, reason,
3448 has_error_code, error_code) == EMULATE_FAIL) {
3449 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3450 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
3451 vcpu->run->internal.ndata = 0;
42dbaa5a 3452 return 0;
acb54517 3453 }
42dbaa5a
JK		 3454
3455 /* clear all local breakpoint enable flags */
3456 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
3457
3458 /*
3459 * TODO: What about debug traps on tss switch?
3460 * Are we supposed to inject them and update dr6?
3461 */
3462
3463 return 1;
37817f29
IE		 3464}
3465
851ba692 3466static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 3467{
f9c617f6 3468 unsigned long exit_qualification;
1439442c 3469 gpa_t gpa;
1439442c 3470 int gla_validity;
1439442c 3471
f9c617f6 3472 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c
SY		 3473
3474 if (exit_qualification & (1 << 6)) {
3475 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
7f582ab6 3476 return -EINVAL;
1439442c
SY		 3477 }
3478
3479 gla_validity = (exit_qualification >> 7) & 0x3;
3480 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
3481 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
3482 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3483 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 3484 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 3485 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
3486 (long unsigned int)exit_qualification);
851ba692
AK		 3487 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3488 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
596ae895 3489 return 0;
1439442c
SY		 3490 }
3491
3492 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 3493 trace_kvm_page_fault(gpa, exit_qualification);
49cd7d22 3494 return kvm_mmu_page_fault(vcpu, gpa & PAGE_MASK, 0);
1439442c
SY		 3495}
3496
68f89400
MT		 3497static u64 ept_rsvd_mask(u64 spte, int level)
3498{
3499 int i;
3500 u64 mask = 0;
3501
3502 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
3503 mask |= (1ULL << i);
3504
3505 if (level > 2)
3506 /* bits 7:3 reserved */
3507 mask |= 0xf8;
3508 else if (level == 2) {
3509 if (spte & (1ULL << 7))
3510 /* 2MB ref, bits 20:12 reserved */
3511 mask |= 0x1ff000;
3512 else
3513 /* bits 6:3 reserved */
3514 mask |= 0x78;
3515 }
3516
3517 return mask;
3518}
3519
3520static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
3521 int level)
3522{
3523 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
3524
3525 /* 010b (write-only) */
3526 WARN_ON((spte & 0x7) == 0x2);
3527
3528 /* 110b (write/execute) */
3529 WARN_ON((spte & 0x7) == 0x6);
3530
3531 /* 100b (execute-only) and value not supported by logical processor */
3532 if (!cpu_has_vmx_ept_execute_only())
3533 WARN_ON((spte & 0x7) == 0x4);
3534
3535 /* not 000b */
3536 if ((spte & 0x7)) {
3537 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
3538
3539 if (rsvd_bits != 0) {
3540 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
3541 __func__, rsvd_bits);
3542 WARN_ON(1);
3543 }
3544
3545 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
3546 u64 ept_mem_type = (spte & 0x38) >> 3;
3547
3548 if (ept_mem_type == 2 || ept_mem_type == 3 ||
3549 ept_mem_type == 7) {
3550 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
3551 __func__, ept_mem_type);
3552 WARN_ON(1);
3553 }
3554 }
3555 }
3556}
3557
851ba692 3558static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400
MT		 3559{
3560 u64 sptes[4];
3561 int nr_sptes, i;
3562 gpa_t gpa;
3563
3564 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3565
3566 printk(KERN_ERR "EPT: Misconfiguration.\n");
3567 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
3568
3569 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
3570
3571 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
3572 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
3573
851ba692
AK		 3574 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3575 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT		 3576
3577 return 0;
3578}
3579
851ba692 3580static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4
SY		 3581{
3582 u32 cpu_based_vm_exec_control;
3583
3584 /* clear pending NMI */
3585 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3586 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
3587 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3588 ++vcpu->stat.nmi_window_exits;
3589
3590 return 1;
3591}
3592
80ced186 3593static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 3594{
8b3079a5
AK		 3595 struct vcpu_vmx *vmx = to_vmx(vcpu);
3596 enum emulation_result err = EMULATE_DONE;
80ced186 3597 int ret = 1;
ea953ef0
MG		 3598
3599 while (!guest_state_valid(vcpu)) {
851ba692 3600 err = emulate_instruction(vcpu, 0, 0, 0);
ea953ef0 3601
80ced186
MG		 3602 if (err == EMULATE_DO_MMIO) {
3603 ret = 0;
3604 goto out;
3605 }
1d5a4d9b 3606
6d77dbfc
GN		 3607 if (err != EMULATE_DONE)
3608 return 0;
ea953ef0
MG		 3609
3610 if (signal_pending(current))
80ced186 3611 goto out;
ea953ef0
MG		 3612 if (need_resched())
3613 schedule();
3614 }
3615
80ced186
MG		 3616 vmx->emulation_required = 0;
3617out:
3618 return ret;
ea953ef0
MG		 3619}
3620
4b8d54f9
ZE		 3621/*
3622 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
3623 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
3624 */
9fb41ba8 3625static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9
ZE		 3626{
3627 skip_emulated_instruction(vcpu);
3628 kvm_vcpu_on_spin(vcpu);
3629
3630 return 1;
3631}
3632
59708670
SY		 3633static int handle_invalid_op(struct kvm_vcpu *vcpu)
3634{
3635 kvm_queue_exception(vcpu, UD_VECTOR);
3636 return 1;
3637}
3638
6aa8b732
AK		 3639/*
3640 * The exit handlers return 1 if the exit was handled fully and guest execution
3641 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
3642 * to be done to userspace and return 0.
3643 */
851ba692 3644static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK		 3645 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
3646 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 3647 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 3648 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 3649 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 3650 [EXIT_REASON_CR_ACCESS] = handle_cr,
3651 [EXIT_REASON_DR_ACCESS] = handle_dr,
3652 [EXIT_REASON_CPUID] = handle_cpuid,
3653 [EXIT_REASON_MSR_READ] = handle_rdmsr,
3654 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
3655 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
3656 [EXIT_REASON_HLT] = handle_halt,
a7052897 3657 [EXIT_REASON_INVLPG] = handle_invlpg,
c21415e8 3658 [EXIT_REASON_VMCALL] = handle_vmcall,
e3c7cb6a
AK		 3659 [EXIT_REASON_VMCLEAR] = handle_vmx_insn,
3660 [EXIT_REASON_VMLAUNCH] = handle_vmx_insn,
3661 [EXIT_REASON_VMPTRLD] = handle_vmx_insn,
3662 [EXIT_REASON_VMPTRST] = handle_vmx_insn,
3663 [EXIT_REASON_VMREAD] = handle_vmx_insn,
3664 [EXIT_REASON_VMRESUME] = handle_vmx_insn,
3665 [EXIT_REASON_VMWRITE] = handle_vmx_insn,
3666 [EXIT_REASON_VMOFF] = handle_vmx_insn,
3667 [EXIT_REASON_VMON] = handle_vmx_insn,
f78e0e2e
SY		 3668 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
3669 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
e5edaa01 3670 [EXIT_REASON_WBINVD] = handle_wbinvd,
37817f29 3671 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 3672 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT		 3673 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
3674 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 3675 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
59708670
SY		 3676 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op,
3677 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op,
6aa8b732
AK		 3678};
3679
3680static const int kvm_vmx_max_exit_handlers =
50a3485c 3681 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732
AK		 3682
3683/*
3684 * The guest has exited. See if we can fix it or if we need userspace
3685 * assistance.
3686 */
851ba692 3687static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 3688{
29bd8a78 3689 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 3690 u32 exit_reason = vmx->exit_reason;
1155f76a 3691 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 3692
5bfd8b54 3693 trace_kvm_exit(exit_reason, vcpu);
2714d1d3 3694
80ced186
MG		 3695 /* If guest state is invalid, start emulating */
3696 if (vmx->emulation_required && emulate_invalid_guest_state)
3697 return handle_invalid_guest_state(vcpu);
1d5a4d9b 3698
1439442c
SY		 3699 /* Access CR3 don't cause VMExit in paging mode, so we need
3700 * to sync with guest real CR3. */
6de4f3ad 3701 if (enable_ept && is_paging(vcpu))
1439442c 3702 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
1439442c 3703
5120702e
MG		 3704 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
3705 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3706 vcpu->run->fail_entry.hardware_entry_failure_reason
3707 = exit_reason;
3708 return 0;
3709 }
3710
29bd8a78 3711 if (unlikely(vmx->fail)) {
851ba692
AK		 3712 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3713 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK		 3714 = vmcs_read32(VM_INSTRUCTION_ERROR);
3715 return 0;
3716 }
6aa8b732 3717
d77c26fc 3718 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 3719 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac
JK		 3720 exit_reason != EXIT_REASON_EPT_VIOLATION &&
3721 exit_reason != EXIT_REASON_TASK_SWITCH))
3722 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
3723 "(0x%x) and exit reason is 0x%x\n",
3724 __func__, vectoring_info, exit_reason);
3b86cd99
JK		 3725
3726 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) {
c4282df9 3727 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 3728 vmx->soft_vnmi_blocked = 0;
3b86cd99 3729 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 3730 vcpu->arch.nmi_pending) {
3b86cd99
JK		 3731 /*
3732 * This CPU don't support us in finding the end of an
3733 * NMI-blocked window if the guest runs with IRQs
3734 * disabled. So we pull the trigger after 1 s of
3735 * futile waiting, but inform the user about this.
3736 */
3737 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
3738 "state on VCPU %d after 1 s timeout\n",
3739 __func__, vcpu->vcpu_id);
3740 vmx->soft_vnmi_blocked = 0;
3b86cd99 3741 }
3b86cd99
JK		 3742 }
3743
6aa8b732
AK		 3744 if (exit_reason < kvm_vmx_max_exit_handlers
3745 && kvm_vmx_exit_handlers[exit_reason])
851ba692 3746 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 3747 else {
851ba692
AK		 3748 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3749 vcpu->run->hw.hardware_exit_reason = exit_reason;
6aa8b732
AK		 3750 }
3751 return 0;
3752}
3753
95ba8273 3754static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 3755{
95ba8273 3756 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 3757 vmcs_write32(TPR_THRESHOLD, 0);
3758 return;
3759 }
3760
95ba8273 3761 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 3762}
3763
cf393f75
AK		 3764static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
3765{
3766 u32 exit_intr_info;
7b4a25cb 3767 u32 idt_vectoring_info = vmx->idt_vectoring_info;
cf393f75
AK		 3768 bool unblock_nmi;
3769 u8 vector;
668f612f
AK		 3770 int type;
3771 bool idtv_info_valid;
cf393f75
AK		 3772
3773 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
20f65983 3774
a0861c02
AK		 3775 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
3776
3777 /* Handle machine checks before interrupts are enabled */
3778 if ((vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY)
3779 || (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI
3780 && is_machine_check(exit_intr_info)))
3781 kvm_machine_check();
3782
20f65983
GN		 3783 /* We need to handle NMIs before interrupts are enabled */
3784 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
ff9d07a0
ZY		 3785 (exit_intr_info & INTR_INFO_VALID_MASK)) {
3786 kvm_before_handle_nmi(&vmx->vcpu);
20f65983 3787 asm("int $2");
ff9d07a0
ZY		 3788 kvm_after_handle_nmi(&vmx->vcpu);
3789 }
20f65983
GN		 3790
3791 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
3792
cf393f75
AK		 3793 if (cpu_has_virtual_nmis()) {
3794 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
3795 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
3796 /*
7b4a25cb 3797 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 3798 * Re-set bit "block by NMI" before VM entry if vmexit caused by
3799 * a guest IRET fault.
7b4a25cb
GN		 3800 * SDM 3: 23.2.2 (September 2008)
3801 * Bit 12 is undefined in any of the following cases:
3802 * If the VM exit sets the valid bit in the IDT-vectoring
3803 * information field.
3804 * If the VM exit is due to a double fault.
cf393f75 3805 */
7b4a25cb
GN		 3806 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
3807 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 3808 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3809 GUEST_INTR_STATE_NMI);
3b86cd99
JK		 3810 } else if (unlikely(vmx->soft_vnmi_blocked))
3811 vmx->vnmi_blocked_time +=
3812 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
668f612f 3813
37b96e98
GN		 3814 vmx->vcpu.arch.nmi_injected = false;
3815 kvm_clear_exception_queue(&vmx->vcpu);
3816 kvm_clear_interrupt_queue(&vmx->vcpu);
3817
3818 if (!idtv_info_valid)
3819 return;
3820
668f612f
AK		 3821 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
3822 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 3823
64a7ec06 3824 switch (type) {
37b96e98
GN		 3825 case INTR_TYPE_NMI_INTR:
3826 vmx->vcpu.arch.nmi_injected = true;
668f612f 3827 /*
7b4a25cb 3828 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 3829 * Clear bit "block by NMI" before VM entry if a NMI
3830 * delivery faulted.
668f612f 3831 */
37b96e98
GN		 3832 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3833 GUEST_INTR_STATE_NMI);
3834 break;
37b96e98 3835 case INTR_TYPE_SOFT_EXCEPTION:
66fd3f7f
GN		 3836 vmx->vcpu.arch.event_exit_inst_len =
3837 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3838 /* fall through */
3839 case INTR_TYPE_HARD_EXCEPTION:
35920a35 3840 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
37b96e98
GN		 3841 u32 err = vmcs_read32(IDT_VECTORING_ERROR_CODE);
3842 kvm_queue_exception_e(&vmx->vcpu, vector, err);
35920a35
AK		 3843 } else
3844 kvm_queue_exception(&vmx->vcpu, vector);
37b96e98 3845 break;
66fd3f7f
GN		 3846 case INTR_TYPE_SOFT_INTR:
3847 vmx->vcpu.arch.event_exit_inst_len =
3848 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3849 /* fall through */
37b96e98 3850 case INTR_TYPE_EXT_INTR:
66fd3f7f
GN		 3851 kvm_queue_interrupt(&vmx->vcpu, vector,
3852 type == INTR_TYPE_SOFT_INTR);
37b96e98
GN		 3853 break;
3854 default:
3855 break;
f7d9238f 3856 }
cf393f75
AK		 3857}
3858
9c8cba37
AK		 3859/*
3860 * Failure to inject an interrupt should give us the information
3861 * in IDT_VECTORING_INFO_FIELD. However, if the failure occurs
3862 * when fetching the interrupt redirection bitmap in the real-mode
3863 * tss, this doesn't happen. So we do it ourselves.
3864 */
3865static void fixup_rmode_irq(struct vcpu_vmx *vmx)
3866{
3867 vmx->rmode.irq.pending = 0;
5fdbf976 3868 if (kvm_rip_read(&vmx->vcpu) + 1 != vmx->rmode.irq.rip)
9c8cba37 3869 return;
5fdbf976 3870 kvm_rip_write(&vmx->vcpu, vmx->rmode.irq.rip);
9c8cba37
AK		 3871 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
3872 vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK;
3873 vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR;
3874 return;
3875 }
3876 vmx->idt_vectoring_info =
3877 VECTORING_INFO_VALID_MASK
3878 | INTR_TYPE_EXT_INTR
3879 | vmx->rmode.irq.vector;
3880}
3881
c801949d
AK		 3882#ifdef CONFIG_X86_64
3883#define R "r"
3884#define Q "q"
3885#else
3886#define R "e"
3887#define Q "l"
3888#endif
3889
851ba692 3890static void vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 3891{
a2fa3e9f 3892 struct vcpu_vmx *vmx = to_vmx(vcpu);
e6adf283 3893
3b86cd99
JK		 3894 /* Record the guest's net vcpu time for enforced NMI injections. */
3895 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
3896 vmx->entry_time = ktime_get();
3897
80ced186
MG		 3898 /* Don't enter VMX if guest state is invalid, let the exit handler
3899 start emulation until we arrive back to a valid state */
3900 if (vmx->emulation_required && emulate_invalid_guest_state)
a89a8fb9 3901 return;
a89a8fb9 3902
5fdbf976
MT		 3903 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
3904 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
3905 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
3906 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
3907
787ff736
GN		 3908 /* When single-stepping over STI and MOV SS, we must clear the
3909 * corresponding interruptibility bits in the guest state. Otherwise
3910 * vmentry fails as it then expects bit 14 (BS) in pending debug
3911 * exceptions being set, but that's not correct for the guest debugging
3912 * case. */
3913 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
3914 vmx_set_interrupt_shadow(vcpu, 0);
3915
d77c26fc 3916 asm(
6aa8b732 3917 /* Store host registers */
c801949d
AK		 3918 "push %%"R"dx; push %%"R"bp;"
3919 "push %%"R"cx \n\t"
313dbd49
AK		 3920 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
3921 "je 1f \n\t"
3922 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
4ecac3fd 3923 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 3924 "1: \n\t"
d3edefc0
AK		 3925 /* Reload cr2 if changed */
3926 "mov %c[cr2](%0), %%"R"ax \n\t"
3927 "mov %%cr2, %%"R"dx \n\t"
3928 "cmp %%"R"ax, %%"R"dx \n\t"
3929 "je 2f \n\t"
3930 "mov %%"R"ax, %%cr2 \n\t"
3931 "2: \n\t"
6aa8b732 3932 /* Check if vmlaunch of vmresume is needed */
e08aa78a 3933 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 3934 /* Load guest registers. Don't clobber flags. */
c801949d
AK		 3935 "mov %c[rax](%0), %%"R"ax \n\t"
3936 "mov %c[rbx](%0), %%"R"bx \n\t"
3937 "mov %c[rdx](%0), %%"R"dx \n\t"
3938 "mov %c[rsi](%0), %%"R"si \n\t"
3939 "mov %c[rdi](%0), %%"R"di \n\t"
3940 "mov %c[rbp](%0), %%"R"bp \n\t"
05b3e0c2 3941#ifdef CONFIG_X86_64
e08aa78a
AK		 3942 "mov %c[r8](%0), %%r8 \n\t"
3943 "mov %c[r9](%0), %%r9 \n\t"
3944 "mov %c[r10](%0), %%r10 \n\t"
3945 "mov %c[r11](%0), %%r11 \n\t"
3946 "mov %c[r12](%0), %%r12 \n\t"
3947 "mov %c[r13](%0), %%r13 \n\t"
3948 "mov %c[r14](%0), %%r14 \n\t"
3949 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 3950#endif
c801949d
AK		 3951 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
3952
6aa8b732 3953 /* Enter guest mode */
cd2276a7 3954 "jne .Llaunched \n\t"
4ecac3fd 3955 __ex(ASM_VMX_VMLAUNCH) "\n\t"
cd2276a7 3956 "jmp .Lkvm_vmx_return \n\t"
4ecac3fd 3957 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
cd2276a7 3958 ".Lkvm_vmx_return: "
6aa8b732 3959 /* Save guest registers, load host registers, keep flags */
c801949d
AK		 3960 "xchg %0, (%%"R"sp) \n\t"
3961 "mov %%"R"ax, %c[rax](%0) \n\t"
3962 "mov %%"R"bx, %c[rbx](%0) \n\t"
3963 "push"Q" (%%"R"sp); pop"Q" %c[rcx](%0) \n\t"
3964 "mov %%"R"dx, %c[rdx](%0) \n\t"
3965 "mov %%"R"si, %c[rsi](%0) \n\t"
3966 "mov %%"R"di, %c[rdi](%0) \n\t"
3967 "mov %%"R"bp, %c[rbp](%0) \n\t"
05b3e0c2 3968#ifdef CONFIG_X86_64
e08aa78a
AK		 3969 "mov %%r8, %c[r8](%0) \n\t"
3970 "mov %%r9, %c[r9](%0) \n\t"
3971 "mov %%r10, %c[r10](%0) \n\t"
3972 "mov %%r11, %c[r11](%0) \n\t"
3973 "mov %%r12, %c[r12](%0) \n\t"
3974 "mov %%r13, %c[r13](%0) \n\t"
3975 "mov %%r14, %c[r14](%0) \n\t"
3976 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 3977#endif
c801949d
AK		 3978 "mov %%cr2, %%"R"ax \n\t"
3979 "mov %%"R"ax, %c[cr2](%0) \n\t"
3980
3981 "pop %%"R"bp; pop %%"R"bp; pop %%"R"dx \n\t"
e08aa78a
AK		 3982 "setbe %c[fail](%0) \n\t"
3983 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
3984 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
3985 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 3986 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 3987 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
3988 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
3989 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
3990 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
3991 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
3992 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
3993 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 3994#ifdef CONFIG_X86_64
ad312c7c
ZX		 3995 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
3996 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
3997 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
3998 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
3999 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
4000 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
4001 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
4002 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 4003#endif
ad312c7c 4004 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2))
c2036300 4005 : "cc", "memory"
c801949d 4006 , R"bx", R"di", R"si"
c2036300 4007#ifdef CONFIG_X86_64
c2036300
LV		 4008 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
4009#endif
4010 );
6aa8b732 4011
6de4f3ad
AK		 4012 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
4013 | (1 << VCPU_EXREG_PDPTR));
5fdbf976
MT		 4014 vcpu->arch.regs_dirty = 0;
4015
1155f76a 4016 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
9c8cba37
AK		 4017 if (vmx->rmode.irq.pending)
4018 fixup_rmode_irq(vmx);
1155f76a 4019
d77c26fc 4020 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
15ad7146 4021 vmx->launched = 1;
1b6269db 4022
cf393f75 4023 vmx_complete_interrupts(vmx);
6aa8b732
AK		 4024}
4025
c801949d
AK		 4026#undef R
4027#undef Q
4028
6aa8b732
AK		 4029static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
4030{
a2fa3e9f
GH		 4031 struct vcpu_vmx *vmx = to_vmx(vcpu);
4032
4033 if (vmx->vmcs) {
543e4243 4034 vcpu_clear(vmx);
a2fa3e9f
GH		 4035 free_vmcs(vmx->vmcs);
4036 vmx->vmcs = NULL;
6aa8b732
AK		 4037 }
4038}
4039
4040static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
4041{
fb3f0f51
RR		 4042 struct vcpu_vmx *vmx = to_vmx(vcpu);
4043
cdbecfc3 4044 free_vpid(vmx);
6aa8b732 4045 vmx_free_vmcs(vcpu);
fb3f0f51
RR		 4046 kfree(vmx->guest_msrs);
4047 kvm_vcpu_uninit(vcpu);
a4770347 4048 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 4049}
4050
4610c9cc
DX		 4051static inline void vmcs_init(struct vmcs *vmcs)
4052{
4053 u64 phys_addr = __pa(per_cpu(vmxarea, raw_smp_processor_id()));
4054
4055 if (!vmm_exclusive)
4056 kvm_cpu_vmxon(phys_addr);
4057
4058 vmcs_clear(vmcs);
4059
4060 if (!vmm_exclusive)
4061 kvm_cpu_vmxoff();
4062}
4063
fb3f0f51 4064static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 4065{
fb3f0f51 4066 int err;
c16f862d 4067 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 4068 int cpu;
6aa8b732 4069
a2fa3e9f 4070 if (!vmx)
fb3f0f51
RR		 4071 return ERR_PTR(-ENOMEM);
4072
2384d2b3
SY		 4073 allocate_vpid(vmx);
4074
fb3f0f51
RR		 4075 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
4076 if (err)
4077 goto free_vcpu;
965b58a5 4078
a2fa3e9f 4079 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
fb3f0f51
RR		 4080 if (!vmx->guest_msrs) {
4081 err = -ENOMEM;
4082 goto uninit_vcpu;
4083 }
965b58a5 4084
a2fa3e9f
GH		 4085 vmx->vmcs = alloc_vmcs();
4086 if (!vmx->vmcs)
fb3f0f51 4087 goto free_msrs;
a2fa3e9f 4088
4610c9cc 4089 vmcs_init(vmx->vmcs);
a2fa3e9f 4090
15ad7146
AK		 4091 cpu = get_cpu();
4092 vmx_vcpu_load(&vmx->vcpu, cpu);
8b9cf98c 4093 err = vmx_vcpu_setup(vmx);
fb3f0f51 4094 vmx_vcpu_put(&vmx->vcpu);
15ad7146 4095 put_cpu();
fb3f0f51
RR		 4096 if (err)
4097 goto free_vmcs;
5e4a0b3c
MT		 4098 if (vm_need_virtualize_apic_accesses(kvm))
4099 if (alloc_apic_access_page(kvm) != 0)
4100 goto free_vmcs;
fb3f0f51 4101
b927a3ce
SY		 4102 if (enable_ept) {
4103 if (!kvm->arch.ept_identity_map_addr)
4104 kvm->arch.ept_identity_map_addr =
4105 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
b7ebfb05
SY		 4106 if (alloc_identity_pagetable(kvm) != 0)
4107 goto free_vmcs;
b927a3ce 4108 }
b7ebfb05 4109
fb3f0f51
RR		 4110 return &vmx->vcpu;
4111
4112free_vmcs:
4113 free_vmcs(vmx->vmcs);
4114free_msrs:
fb3f0f51
RR		 4115 kfree(vmx->guest_msrs);
4116uninit_vcpu:
4117 kvm_vcpu_uninit(&vmx->vcpu);
4118free_vcpu:
cdbecfc3 4119 free_vpid(vmx);
a4770347 4120 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 4121 return ERR_PTR(err);
6aa8b732
AK		 4122}
4123
002c7f7c
YS		 4124static void __init vmx_check_processor_compat(void *rtn)
4125{
4126 struct vmcs_config vmcs_conf;
4127
4128 *(int *)rtn = 0;
4129 if (setup_vmcs_config(&vmcs_conf) < 0)
4130 *(int *)rtn = -EIO;
4131 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
4132 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
4133 smp_processor_id());
4134 *(int *)rtn = -EIO;
4135 }
4136}
4137
67253af5
SY		 4138static int get_ept_level(void)
4139{
4140 return VMX_EPT_DEFAULT_GAW + 1;
4141}
4142
4b12f0de 4143static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 4144{
4b12f0de
SY		 4145 u64 ret;
4146
522c68c4
SY		 4147 /* For VT-d and EPT combination
4148 * 1. MMIO: always map as UC
4149 * 2. EPT with VT-d:
4150 * a. VT-d without snooping control feature: can't guarantee the
4151 * result, try to trust guest.
4152 * b. VT-d with snooping control feature: snooping control feature of
4153 * VT-d engine can guarantee the cache correctness. Just set it
4154 * to WB to keep consistent with host. So the same as item 3.
a19a6d11 4155 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
522c68c4
SY		 4156 * consistent with host MTRR
4157 */
4b12f0de
SY		 4158 if (is_mmio)
4159 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
522c68c4
SY		 4160 else if (vcpu->kvm->arch.iommu_domain &&
4161 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
4162 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
4163 VMX_EPT_MT_EPTE_SHIFT;
4b12f0de 4164 else
522c68c4 4165 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
a19a6d11 4166 | VMX_EPT_IPAT_BIT;
4b12f0de
SY		 4167
4168 return ret;
64d4d521
SY		 4169}
4170
f4c9e87c
AK		 4171#define _ER(x) { EXIT_REASON_##x, #x }
4172
229456fc 4173static const struct trace_print_flags vmx_exit_reasons_str[] = {
f4c9e87c
AK		 4174 _ER(EXCEPTION_NMI),
4175 _ER(EXTERNAL_INTERRUPT),
4176 _ER(TRIPLE_FAULT),
4177 _ER(PENDING_INTERRUPT),
4178 _ER(NMI_WINDOW),
4179 _ER(TASK_SWITCH),
4180 _ER(CPUID),
4181 _ER(HLT),
4182 _ER(INVLPG),
4183 _ER(RDPMC),
4184 _ER(RDTSC),
4185 _ER(VMCALL),
4186 _ER(VMCLEAR),
4187 _ER(VMLAUNCH),
4188 _ER(VMPTRLD),
4189 _ER(VMPTRST),
4190 _ER(VMREAD),
4191 _ER(VMRESUME),
4192 _ER(VMWRITE),
4193 _ER(VMOFF),
4194 _ER(VMON),
4195 _ER(CR_ACCESS),
4196 _ER(DR_ACCESS),
4197 _ER(IO_INSTRUCTION),
4198 _ER(MSR_READ),
4199 _ER(MSR_WRITE),
4200 _ER(MWAIT_INSTRUCTION),
4201 _ER(MONITOR_INSTRUCTION),
4202 _ER(PAUSE_INSTRUCTION),
4203 _ER(MCE_DURING_VMENTRY),
4204 _ER(TPR_BELOW_THRESHOLD),
4205 _ER(APIC_ACCESS),
4206 _ER(EPT_VIOLATION),
4207 _ER(EPT_MISCONFIG),
4208 _ER(WBINVD),
229456fc
MT		 4209 { -1, NULL }
4210};
4211
f4c9e87c
AK		 4212#undef _ER
4213
17cc3935 4214static int vmx_get_lpage_level(void)
344f414f 4215{
878403b7
SY		 4216 if (enable_ept && !cpu_has_vmx_ept_1g_page())
4217 return PT_DIRECTORY_LEVEL;
4218 else
4219 /* For shadow and EPT supported 1GB page */
4220 return PT_PDPE_LEVEL;
344f414f
JR		 4221}
4222
4e47c7a6
SY		 4223static inline u32 bit(int bitno)
4224{
4225 return 1 << (bitno & 31);
4226}
4227
0e851880
SY		 4228static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
4229{
4e47c7a6
SY		 4230 struct kvm_cpuid_entry2 *best;
4231 struct vcpu_vmx *vmx = to_vmx(vcpu);
4232 u32 exec_control;
4233
4234 vmx->rdtscp_enabled = false;
4235 if (vmx_rdtscp_supported()) {
4236 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
4237 if (exec_control & SECONDARY_EXEC_RDTSCP) {
4238 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
4239 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
4240 vmx->rdtscp_enabled = true;
4241 else {
4242 exec_control &= ~SECONDARY_EXEC_RDTSCP;
4243 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4244 exec_control);
4245 }
4246 }
4247 }
0e851880
SY		 4248}
4249
d4330ef2
JR		 4250static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
4251{
4252}
4253
cbdd1bea 4254static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 4255 .cpu_has_kvm_support = cpu_has_kvm_support,
4256 .disabled_by_bios = vmx_disabled_by_bios,
4257 .hardware_setup = hardware_setup,
4258 .hardware_unsetup = hardware_unsetup,
002c7f7c 4259 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 4260 .hardware_enable = hardware_enable,
4261 .hardware_disable = hardware_disable,
04547156 4262 .cpu_has_accelerated_tpr = report_flexpriority,
6aa8b732
AK		 4263
4264 .vcpu_create = vmx_create_vcpu,
4265 .vcpu_free = vmx_free_vcpu,
04d2cc77 4266 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 4267
04d2cc77 4268 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 4269 .vcpu_load = vmx_vcpu_load,
4270 .vcpu_put = vmx_vcpu_put,
4271
4272 .set_guest_debug = set_guest_debug,
4273 .get_msr = vmx_get_msr,
4274 .set_msr = vmx_set_msr,
4275 .get_segment_base = vmx_get_segment_base,
4276 .get_segment = vmx_get_segment,
4277 .set_segment = vmx_set_segment,
2e4d2653 4278 .get_cpl = vmx_get_cpl,
6aa8b732 4279 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 4280 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
25c4c276 4281 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 4282 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 4283 .set_cr3 = vmx_set_cr3,
4284 .set_cr4 = vmx_set_cr4,
6aa8b732 4285 .set_efer = vmx_set_efer,
6aa8b732
AK		 4286 .get_idt = vmx_get_idt,
4287 .set_idt = vmx_set_idt,
4288 .get_gdt = vmx_get_gdt,
4289 .set_gdt = vmx_set_gdt,
020df079 4290 .set_dr7 = vmx_set_dr7,
5fdbf976 4291 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 4292 .get_rflags = vmx_get_rflags,
4293 .set_rflags = vmx_set_rflags,
ebcbab4c 4294 .fpu_activate = vmx_fpu_activate,
02daab21 4295 .fpu_deactivate = vmx_fpu_deactivate,
6aa8b732
AK		 4296
4297 .tlb_flush = vmx_flush_tlb,
6aa8b732 4298
6aa8b732 4299 .run = vmx_vcpu_run,
6062d012 4300 .handle_exit = vmx_handle_exit,
6aa8b732 4301 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 4302 .set_interrupt_shadow = vmx_set_interrupt_shadow,
4303 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 4304 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 4305 .set_irq = vmx_inject_irq,
95ba8273 4306 .set_nmi = vmx_inject_nmi,
298101da 4307 .queue_exception = vmx_queue_exception,
78646121 4308 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 4309 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 4310 .get_nmi_mask = vmx_get_nmi_mask,
4311 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 4312 .enable_nmi_window = enable_nmi_window,
4313 .enable_irq_window = enable_irq_window,
4314 .update_cr8_intercept = update_cr8_intercept,
95ba8273 4315
cbc94022 4316 .set_tss_addr = vmx_set_tss_addr,
67253af5 4317 .get_tdp_level = get_ept_level,
4b12f0de 4318 .get_mt_mask = vmx_get_mt_mask,
229456fc
MT		 4319
4320 .exit_reasons_str = vmx_exit_reasons_str,
17cc3935 4321 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY		 4322
4323 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY		 4324
4325 .rdtscp_supported = vmx_rdtscp_supported,
d4330ef2
JR		 4326
4327 .set_supported_cpuid = vmx_set_supported_cpuid,
6aa8b732
AK		 4328};
4329
4330static int __init vmx_init(void)
4331{
26bb0981
AK		 4332 int r, i;
4333
4334 rdmsrl_safe(MSR_EFER, &host_efer);
4335
4336 for (i = 0; i < NR_VMX_MSR; ++i)
4337 kvm_define_shared_msr(i, vmx_msr_index[i]);
fdef3ad1 4338
3e7c73e9 4339 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 4340 if (!vmx_io_bitmap_a)
4341 return -ENOMEM;
4342
3e7c73e9 4343 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 4344 if (!vmx_io_bitmap_b) {
4345 r = -ENOMEM;
4346 goto out;
4347 }
4348
5897297b
AK		 4349 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
4350 if (!vmx_msr_bitmap_legacy) {
25c5f225
SY		 4351 r = -ENOMEM;
4352 goto out1;
4353 }
4354
5897297b
AK		 4355 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
4356 if (!vmx_msr_bitmap_longmode) {
4357 r = -ENOMEM;
4358 goto out2;
4359 }
4360
fdef3ad1
HQ		 4361 /*
4362 * Allow direct access to the PC debug port (it is often used for I/O
4363 * delays, but the vmexits simply slow things down).
4364 */
3e7c73e9
AK		 4365 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
4366 clear_bit(0x80, vmx_io_bitmap_a);
fdef3ad1 4367
3e7c73e9 4368 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
fdef3ad1 4369
5897297b
AK		 4370 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
4371 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
25c5f225 4372
2384d2b3
SY		 4373 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
4374
0ee75bea
AK		 4375 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
4376 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 4377 if (r)
5897297b 4378 goto out3;
25c5f225 4379
5897297b
AK		 4380 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
4381 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
4382 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
4383 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
4384 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
4385 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
fdef3ad1 4386
089d034e 4387 if (enable_ept) {
1439442c 4388 bypass_guest_pf = 0;
5fdbcb9d 4389 kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK |
2aaf69dc 4390 VMX_EPT_WRITABLE_MASK);
534e38b4 4391 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
4b12f0de 4392 VMX_EPT_EXECUTABLE_MASK);
5fdbcb9d
SY		 4393 kvm_enable_tdp();
4394 } else
4395 kvm_disable_tdp();
1439442c 4396
c7addb90
AK		 4397 if (bypass_guest_pf)
4398 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
4399
fdef3ad1
HQ		 4400 return 0;
4401
5897297b
AK		 4402out3:
4403 free_page((unsigned long)vmx_msr_bitmap_longmode);
25c5f225 4404out2:
5897297b 4405 free_page((unsigned long)vmx_msr_bitmap_legacy);
fdef3ad1 4406out1:
3e7c73e9 4407 free_page((unsigned long)vmx_io_bitmap_b);
fdef3ad1 4408out:
3e7c73e9 4409 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 4410 return r;
6aa8b732
AK		 4411}
4412
4413static void __exit vmx_exit(void)
4414{
5897297b
AK		 4415 free_page((unsigned long)vmx_msr_bitmap_legacy);
4416 free_page((unsigned long)vmx_msr_bitmap_longmode);
3e7c73e9
AK		 4417 free_page((unsigned long)vmx_io_bitmap_b);
4418 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 4419
cb498ea2 4420 kvm_exit();
6aa8b732
AK		 4421}
4422
4423module_init(vmx_init)
4424module_exit(vmx_exit)
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