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KVM: x86: use F() macro throughout cpuid.c
[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
9611c187 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
00b27a3e 21#include "cpuid.h"
e495606d 22
edf88417 23#include <linux/kvm_host.h>
6aa8b732 24#include <linux/module.h>
9d8f549d 25#include <linux/kernel.h>
6aa8b732
AK		 26#include <linux/mm.h>
27#include <linux/highmem.h>
e8edc6e0 28#include <linux/sched.h>
c7addb90 29#include <linux/moduleparam.h>
e9bda3b3 30#include <linux/mod_devicetable.h>
229456fc 31#include <linux/ftrace_event.h>
5a0e3ad6 32#include <linux/slab.h>
cafd6659 33#include <linux/tboot.h>
f4124500 34#include <linux/hrtimer.h>
5fdbf976 35#include "kvm_cache_regs.h"
35920a35 36#include "x86.h"
e495606d 37
6aa8b732 38#include <asm/io.h>
3b3be0d1 39#include <asm/desc.h>
13673a90 40#include <asm/vmx.h>
6210e37b 41#include <asm/virtext.h>
a0861c02 42#include <asm/mce.h>
2acf923e
DC		 43#include <asm/i387.h>
44#include <asm/xcr.h>
d7cd9796 45#include <asm/perf_event.h>
81908bf4 46#include <asm/debugreg.h>
8f536b76 47#include <asm/kexec.h>
6aa8b732 48
229456fc
MT		 49#include "trace.h"
50
4ecac3fd 51#define __ex(x) __kvm_handle_fault_on_reboot(x)
5e520e62
AK		 52#define __ex_clear(x, reg) \
53 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
4ecac3fd 54
6aa8b732
AK		 55MODULE_AUTHOR("Qumranet");
56MODULE_LICENSE("GPL");
57
e9bda3b3
JT		 58static const struct x86_cpu_id vmx_cpu_id[] = {
59 X86_FEATURE_MATCH(X86_FEATURE_VMX),
60 {}
61};
62MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
63
476bc001 64static bool __read_mostly enable_vpid = 1;
736caefe 65module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 66
476bc001 67static bool __read_mostly flexpriority_enabled = 1;
736caefe 68module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 69
476bc001 70static bool __read_mostly enable_ept = 1;
736caefe 71module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 72
476bc001 73static bool __read_mostly enable_unrestricted_guest = 1;
3a624e29
NK		 74module_param_named(unrestricted_guest,
75 enable_unrestricted_guest, bool, S_IRUGO);
76
83c3a331
XH		 77static bool __read_mostly enable_ept_ad_bits = 1;
78module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
79
a27685c3 80static bool __read_mostly emulate_invalid_guest_state = true;
c1f8bc04 81module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 82
476bc001 83static bool __read_mostly vmm_exclusive = 1;
b923e62e
DX		 84module_param(vmm_exclusive, bool, S_IRUGO);
85
476bc001 86static bool __read_mostly fasteoi = 1;
58fbbf26
KT		 87module_param(fasteoi, bool, S_IRUGO);
88
5a71785d 89static bool __read_mostly enable_apicv = 1;
01e439be 90module_param(enable_apicv, bool, S_IRUGO);
83d4c286 91
abc4fc58
AG		 92static bool __read_mostly enable_shadow_vmcs = 1;
93module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
801d3424
NHE		 94/*
95 * If nested=1, nested virtualization is supported, i.e., guests may use
96 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
97 * use VMX instructions.
98 */
476bc001 99static bool __read_mostly nested = 0;
801d3424
NHE		 100module_param(nested, bool, S_IRUGO);
101
5037878e
GN		 102#define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
103#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
cdc0e244
AK		 104#define KVM_VM_CR0_ALWAYS_ON \
105 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 106#define KVM_CR4_GUEST_OWNED_BITS \
107 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
52ce3c21 108 | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
4c38609a 109
cdc0e244
AK		 110#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
111#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
112
78ac8b47
AK		 113#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
114
f4124500
JK		 115#define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
116
4b8d54f9
ZE		 117/*
118 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
119 * ple_gap: upper bound on the amount of time between two successive
120 * executions of PAUSE in a loop. Also indicate if ple enabled.
00c25bce 121 * According to test, this time is usually smaller than 128 cycles.
4b8d54f9
ZE		 122 * ple_window: upper bound on the amount of time a guest is allowed to execute
123 * in a PAUSE loop. Tests indicate that most spinlocks are held for
124 * less than 2^12 cycles
125 * Time is measured based on a counter that runs at the same rate as the TSC,
126 * refer SDM volume 3b section 21.6.13 & 22.1.3.
127 */
b4a2d31d
RK		 128#define KVM_VMX_DEFAULT_PLE_GAP 128
129#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
130#define KVM_VMX_DEFAULT_PLE_WINDOW_GROW 2
131#define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
132#define KVM_VMX_DEFAULT_PLE_WINDOW_MAX \
133 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
134
4b8d54f9
ZE		 135static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
136module_param(ple_gap, int, S_IRUGO);
137
138static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
139module_param(ple_window, int, S_IRUGO);
140
b4a2d31d
RK		 141/* Default doubles per-vcpu window every exit. */
142static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW;
143module_param(ple_window_grow, int, S_IRUGO);
144
145/* Default resets per-vcpu window every exit to ple_window. */
146static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK;
147module_param(ple_window_shrink, int, S_IRUGO);
148
149/* Default is to compute the maximum so we can never overflow. */
150static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
151static int ple_window_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
152module_param(ple_window_max, int, S_IRUGO);
153
83287ea4
AK		 154extern const ulong vmx_return;
155
8bf00a52 156#define NR_AUTOLOAD_MSRS 8
ff2f6fe9 157#define VMCS02_POOL_SIZE 1
61d2ef2c 158
a2fa3e9f
GH		 159struct vmcs {
160 u32 revision_id;
161 u32 abort;
162 char data[0];
163};
164
d462b819
NHE		 165/*
166 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
167 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
168 * loaded on this CPU (so we can clear them if the CPU goes down).
169 */
170struct loaded_vmcs {
171 struct vmcs *vmcs;
172 int cpu;
173 int launched;
174 struct list_head loaded_vmcss_on_cpu_link;
175};
176
26bb0981
AK		 177struct shared_msr_entry {
178 unsigned index;
179 u64 data;
d5696725 180 u64 mask;
26bb0981
AK		 181};
182
a9d30f33
NHE		 183/*
184 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
185 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
186 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
187 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
188 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
189 * More than one of these structures may exist, if L1 runs multiple L2 guests.
190 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
191 * underlying hardware which will be used to run L2.
192 * This structure is packed to ensure that its layout is identical across
193 * machines (necessary for live migration).
194 * If there are changes in this struct, VMCS12_REVISION must be changed.
195 */
22bd0358 196typedef u64 natural_width;
a9d30f33
NHE		 197struct __packed vmcs12 {
198 /* According to the Intel spec, a VMCS region must start with the
199 * following two fields. Then follow implementation-specific data.
200 */
201 u32 revision_id;
202 u32 abort;
22bd0358 203
27d6c865
NHE		 204 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
205 u32 padding[7]; /* room for future expansion */
206
22bd0358
NHE		 207 u64 io_bitmap_a;
208 u64 io_bitmap_b;
209 u64 msr_bitmap;
210 u64 vm_exit_msr_store_addr;
211 u64 vm_exit_msr_load_addr;
212 u64 vm_entry_msr_load_addr;
213 u64 tsc_offset;
214 u64 virtual_apic_page_addr;
215 u64 apic_access_addr;
216 u64 ept_pointer;
217 u64 guest_physical_address;
218 u64 vmcs_link_pointer;
219 u64 guest_ia32_debugctl;
220 u64 guest_ia32_pat;
221 u64 guest_ia32_efer;
222 u64 guest_ia32_perf_global_ctrl;
223 u64 guest_pdptr0;
224 u64 guest_pdptr1;
225 u64 guest_pdptr2;
226 u64 guest_pdptr3;
36be0b9d 227 u64 guest_bndcfgs;
22bd0358
NHE		 228 u64 host_ia32_pat;
229 u64 host_ia32_efer;
230 u64 host_ia32_perf_global_ctrl;
231 u64 padding64[8]; /* room for future expansion */
232 /*
233 * To allow migration of L1 (complete with its L2 guests) between
234 * machines of different natural widths (32 or 64 bit), we cannot have
235 * unsigned long fields with no explict size. We use u64 (aliased
236 * natural_width) instead. Luckily, x86 is little-endian.
237 */
238 natural_width cr0_guest_host_mask;
239 natural_width cr4_guest_host_mask;
240 natural_width cr0_read_shadow;
241 natural_width cr4_read_shadow;
242 natural_width cr3_target_value0;
243 natural_width cr3_target_value1;
244 natural_width cr3_target_value2;
245 natural_width cr3_target_value3;
246 natural_width exit_qualification;
247 natural_width guest_linear_address;
248 natural_width guest_cr0;
249 natural_width guest_cr3;
250 natural_width guest_cr4;
251 natural_width guest_es_base;
252 natural_width guest_cs_base;
253 natural_width guest_ss_base;
254 natural_width guest_ds_base;
255 natural_width guest_fs_base;
256 natural_width guest_gs_base;
257 natural_width guest_ldtr_base;
258 natural_width guest_tr_base;
259 natural_width guest_gdtr_base;
260 natural_width guest_idtr_base;
261 natural_width guest_dr7;
262 natural_width guest_rsp;
263 natural_width guest_rip;
264 natural_width guest_rflags;
265 natural_width guest_pending_dbg_exceptions;
266 natural_width guest_sysenter_esp;
267 natural_width guest_sysenter_eip;
268 natural_width host_cr0;
269 natural_width host_cr3;
270 natural_width host_cr4;
271 natural_width host_fs_base;
272 natural_width host_gs_base;
273 natural_width host_tr_base;
274 natural_width host_gdtr_base;
275 natural_width host_idtr_base;
276 natural_width host_ia32_sysenter_esp;
277 natural_width host_ia32_sysenter_eip;
278 natural_width host_rsp;
279 natural_width host_rip;
280 natural_width paddingl[8]; /* room for future expansion */
281 u32 pin_based_vm_exec_control;
282 u32 cpu_based_vm_exec_control;
283 u32 exception_bitmap;
284 u32 page_fault_error_code_mask;
285 u32 page_fault_error_code_match;
286 u32 cr3_target_count;
287 u32 vm_exit_controls;
288 u32 vm_exit_msr_store_count;
289 u32 vm_exit_msr_load_count;
290 u32 vm_entry_controls;
291 u32 vm_entry_msr_load_count;
292 u32 vm_entry_intr_info_field;
293 u32 vm_entry_exception_error_code;
294 u32 vm_entry_instruction_len;
295 u32 tpr_threshold;
296 u32 secondary_vm_exec_control;
297 u32 vm_instruction_error;
298 u32 vm_exit_reason;
299 u32 vm_exit_intr_info;
300 u32 vm_exit_intr_error_code;
301 u32 idt_vectoring_info_field;
302 u32 idt_vectoring_error_code;
303 u32 vm_exit_instruction_len;
304 u32 vmx_instruction_info;
305 u32 guest_es_limit;
306 u32 guest_cs_limit;
307 u32 guest_ss_limit;
308 u32 guest_ds_limit;
309 u32 guest_fs_limit;
310 u32 guest_gs_limit;
311 u32 guest_ldtr_limit;
312 u32 guest_tr_limit;
313 u32 guest_gdtr_limit;
314 u32 guest_idtr_limit;
315 u32 guest_es_ar_bytes;
316 u32 guest_cs_ar_bytes;
317 u32 guest_ss_ar_bytes;
318 u32 guest_ds_ar_bytes;
319 u32 guest_fs_ar_bytes;
320 u32 guest_gs_ar_bytes;
321 u32 guest_ldtr_ar_bytes;
322 u32 guest_tr_ar_bytes;
323 u32 guest_interruptibility_info;
324 u32 guest_activity_state;
325 u32 guest_sysenter_cs;
326 u32 host_ia32_sysenter_cs;
0238ea91
JK		 327 u32 vmx_preemption_timer_value;
328 u32 padding32[7]; /* room for future expansion */
22bd0358
NHE		 329 u16 virtual_processor_id;
330 u16 guest_es_selector;
331 u16 guest_cs_selector;
332 u16 guest_ss_selector;
333 u16 guest_ds_selector;
334 u16 guest_fs_selector;
335 u16 guest_gs_selector;
336 u16 guest_ldtr_selector;
337 u16 guest_tr_selector;
338 u16 host_es_selector;
339 u16 host_cs_selector;
340 u16 host_ss_selector;
341 u16 host_ds_selector;
342 u16 host_fs_selector;
343 u16 host_gs_selector;
344 u16 host_tr_selector;
a9d30f33
NHE		 345};
346
347/*
348 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
349 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
350 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
351 */
352#define VMCS12_REVISION 0x11e57ed0
353
354/*
355 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
356 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
357 * current implementation, 4K are reserved to avoid future complications.
358 */
359#define VMCS12_SIZE 0x1000
360
ff2f6fe9
NHE		 361/* Used to remember the last vmcs02 used for some recently used vmcs12s */
362struct vmcs02_list {
363 struct list_head list;
364 gpa_t vmptr;
365 struct loaded_vmcs vmcs02;
366};
367
ec378aee
NHE		 368/*
369 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
370 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
371 */
372struct nested_vmx {
373 /* Has the level1 guest done vmxon? */
374 bool vmxon;
3573e22c 375 gpa_t vmxon_ptr;
a9d30f33
NHE		 376
377 /* The guest-physical address of the current VMCS L1 keeps for L2 */
378 gpa_t current_vmptr;
379 /* The host-usable pointer to the above */
380 struct page *current_vmcs12_page;
381 struct vmcs12 *current_vmcs12;
8de48833 382 struct vmcs *current_shadow_vmcs;
012f83cb
AG		 383 /*
384 * Indicates if the shadow vmcs must be updated with the
385 * data hold by vmcs12
386 */
387 bool sync_shadow_vmcs;
ff2f6fe9
NHE		 388
389 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
390 struct list_head vmcs02_pool;
391 int vmcs02_num;
fe3ef05c 392 u64 vmcs01_tsc_offset;
644d711a
NHE		 393 /* L2 must run next, and mustn't decide to exit to L1. */
394 bool nested_run_pending;
fe3ef05c
NHE		 395 /*
396 * Guest pages referred to in vmcs02 with host-physical pointers, so
397 * we must keep them pinned while L2 runs.
398 */
399 struct page *apic_access_page;
a7c0b07d 400 struct page *virtual_apic_page;
b3897a49 401 u64 msr_ia32_feature_control;
f4124500
JK		 402
403 struct hrtimer preemption_timer;
404 bool preemption_timer_expired;
2996fca0
JK		 405
406 /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
407 u64 vmcs01_debugctl;
ec378aee
NHE		 408};
409
01e439be
YZ		 410#define POSTED_INTR_ON 0
411/* Posted-Interrupt Descriptor */
412struct pi_desc {
413 u32 pir[8]; /* Posted interrupt requested */
414 u32 control; /* bit 0 of control is outstanding notification bit */
415 u32 rsvd[7];
416} __aligned(64);
417
a20ed54d
YZ		 418static bool pi_test_and_set_on(struct pi_desc *pi_desc)
419{
420 return test_and_set_bit(POSTED_INTR_ON,
421 (unsigned long *)&pi_desc->control);
422}
423
424static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
425{
426 return test_and_clear_bit(POSTED_INTR_ON,
427 (unsigned long *)&pi_desc->control);
428}
429
430static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
431{
432 return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
433}
434
a2fa3e9f 435struct vcpu_vmx {
fb3f0f51 436 struct kvm_vcpu vcpu;
313dbd49 437 unsigned long host_rsp;
29bd8a78 438 u8 fail;
9d58b931 439 bool nmi_known_unmasked;
51aa01d1 440 u32 exit_intr_info;
1155f76a 441 u32 idt_vectoring_info;
6de12732 442 ulong rflags;
26bb0981 443 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH		 444 int nmsrs;
445 int save_nmsrs;
a547c6db 446 unsigned long host_idt_base;
a2fa3e9f 447#ifdef CONFIG_X86_64
44ea2b17
AK		 448 u64 msr_host_kernel_gs_base;
449 u64 msr_guest_kernel_gs_base;
a2fa3e9f 450#endif
2961e876
GN		 451 u32 vm_entry_controls_shadow;
452 u32 vm_exit_controls_shadow;
d462b819
NHE		 453 /*
454 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
455 * non-nested (L1) guest, it always points to vmcs01. For a nested
456 * guest (L2), it points to a different VMCS.
457 */
458 struct loaded_vmcs vmcs01;
459 struct loaded_vmcs *loaded_vmcs;
460 bool __launched; /* temporary, used in vmx_vcpu_run */
61d2ef2c
AK		 461 struct msr_autoload {
462 unsigned nr;
463 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
464 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
465 } msr_autoload;
a2fa3e9f
GH		 466 struct {
467 int loaded;
468 u16 fs_sel, gs_sel, ldt_sel;
b2da15ac
AK		 469#ifdef CONFIG_X86_64
470 u16 ds_sel, es_sel;
471#endif
152d3f2f
LV		 472 int gs_ldt_reload_needed;
473 int fs_reload_needed;
da8999d3 474 u64 msr_host_bndcfgs;
d974baa3 475 unsigned long vmcs_host_cr4; /* May not match real cr4 */
d77c26fc 476 } host_state;
9c8cba37 477 struct {
7ffd92c5 478 int vm86_active;
78ac8b47 479 ulong save_rflags;
f5f7b2fe
AK		 480 struct kvm_segment segs[8];
481 } rmode;
482 struct {
483 u32 bitmask; /* 4 bits per segment (1 bit per field) */
7ffd92c5
AK		 484 struct kvm_save_segment {
485 u16 selector;
486 unsigned long base;
487 u32 limit;
488 u32 ar;
f5f7b2fe 489 } seg[8];
2fb92db1 490 } segment_cache;
2384d2b3 491 int vpid;
04fa4d32 492 bool emulation_required;
3b86cd99
JK		 493
494 /* Support for vnmi-less CPUs */
495 int soft_vnmi_blocked;
496 ktime_t entry_time;
497 s64 vnmi_blocked_time;
a0861c02 498 u32 exit_reason;
4e47c7a6
SY		 499
500 bool rdtscp_enabled;
ec378aee 501
01e439be
YZ		 502 /* Posted interrupt descriptor */
503 struct pi_desc pi_desc;
504
ec378aee
NHE		 505 /* Support for a guest hypervisor (nested VMX) */
506 struct nested_vmx nested;
a7653ecd
RK		 507
508 /* Dynamic PLE window. */
509 int ple_window;
510 bool ple_window_dirty;
a2fa3e9f
GH		 511};
512
2fb92db1
AK		 513enum segment_cache_field {
514 SEG_FIELD_SEL = 0,
515 SEG_FIELD_BASE = 1,
516 SEG_FIELD_LIMIT = 2,
517 SEG_FIELD_AR = 3,
518
519 SEG_FIELD_NR = 4
520};
521
a2fa3e9f
GH		 522static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
523{
fb3f0f51 524 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 525}
526
22bd0358
NHE		 527#define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
528#define FIELD(number, name) [number] = VMCS12_OFFSET(name)
529#define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
530 [number##_HIGH] = VMCS12_OFFSET(name)+4
531
4607c2d7 532
fe2b201b 533static unsigned long shadow_read_only_fields[] = {
4607c2d7
AG		 534 /*
535 * We do NOT shadow fields that are modified when L0
536 * traps and emulates any vmx instruction (e.g. VMPTRLD,
537 * VMXON...) executed by L1.
538 * For example, VM_INSTRUCTION_ERROR is read
539 * by L1 if a vmx instruction fails (part of the error path).
540 * Note the code assumes this logic. If for some reason
541 * we start shadowing these fields then we need to
542 * force a shadow sync when L0 emulates vmx instructions
543 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
544 * by nested_vmx_failValid)
545 */
546 VM_EXIT_REASON,
547 VM_EXIT_INTR_INFO,
548 VM_EXIT_INSTRUCTION_LEN,
549 IDT_VECTORING_INFO_FIELD,
550 IDT_VECTORING_ERROR_CODE,
551 VM_EXIT_INTR_ERROR_CODE,
552 EXIT_QUALIFICATION,
553 GUEST_LINEAR_ADDRESS,
554 GUEST_PHYSICAL_ADDRESS
555};
fe2b201b 556static int max_shadow_read_only_fields =
4607c2d7
AG		 557 ARRAY_SIZE(shadow_read_only_fields);
558
fe2b201b 559static unsigned long shadow_read_write_fields[] = {
a7c0b07d 560 TPR_THRESHOLD,
4607c2d7
AG		 561 GUEST_RIP,
562 GUEST_RSP,
563 GUEST_CR0,
564 GUEST_CR3,
565 GUEST_CR4,
566 GUEST_INTERRUPTIBILITY_INFO,
567 GUEST_RFLAGS,
568 GUEST_CS_SELECTOR,
569 GUEST_CS_AR_BYTES,
570 GUEST_CS_LIMIT,
571 GUEST_CS_BASE,
572 GUEST_ES_BASE,
36be0b9d 573 GUEST_BNDCFGS,
4607c2d7
AG		 574 CR0_GUEST_HOST_MASK,
575 CR0_READ_SHADOW,
576 CR4_READ_SHADOW,
577 TSC_OFFSET,
578 EXCEPTION_BITMAP,
579 CPU_BASED_VM_EXEC_CONTROL,
580 VM_ENTRY_EXCEPTION_ERROR_CODE,
581 VM_ENTRY_INTR_INFO_FIELD,
582 VM_ENTRY_INSTRUCTION_LEN,
583 VM_ENTRY_EXCEPTION_ERROR_CODE,
584 HOST_FS_BASE,
585 HOST_GS_BASE,
586 HOST_FS_SELECTOR,
587 HOST_GS_SELECTOR
588};
fe2b201b 589static int max_shadow_read_write_fields =
4607c2d7
AG		 590 ARRAY_SIZE(shadow_read_write_fields);
591
772e0318 592static const unsigned short vmcs_field_to_offset_table[] = {
22bd0358
NHE		 593 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
594 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
595 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
596 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
597 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
598 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
599 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
600 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
601 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
602 FIELD(HOST_ES_SELECTOR, host_es_selector),
603 FIELD(HOST_CS_SELECTOR, host_cs_selector),
604 FIELD(HOST_SS_SELECTOR, host_ss_selector),
605 FIELD(HOST_DS_SELECTOR, host_ds_selector),
606 FIELD(HOST_FS_SELECTOR, host_fs_selector),
607 FIELD(HOST_GS_SELECTOR, host_gs_selector),
608 FIELD(HOST_TR_SELECTOR, host_tr_selector),
609 FIELD64(IO_BITMAP_A, io_bitmap_a),
610 FIELD64(IO_BITMAP_B, io_bitmap_b),
611 FIELD64(MSR_BITMAP, msr_bitmap),
612 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
613 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
614 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
615 FIELD64(TSC_OFFSET, tsc_offset),
616 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
617 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
618 FIELD64(EPT_POINTER, ept_pointer),
619 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
620 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
621 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
622 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
623 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
624 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
625 FIELD64(GUEST_PDPTR0, guest_pdptr0),
626 FIELD64(GUEST_PDPTR1, guest_pdptr1),
627 FIELD64(GUEST_PDPTR2, guest_pdptr2),
628 FIELD64(GUEST_PDPTR3, guest_pdptr3),
36be0b9d 629 FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
22bd0358
NHE		 630 FIELD64(HOST_IA32_PAT, host_ia32_pat),
631 FIELD64(HOST_IA32_EFER, host_ia32_efer),
632 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
633 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
634 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
635 FIELD(EXCEPTION_BITMAP, exception_bitmap),
636 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
637 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
638 FIELD(CR3_TARGET_COUNT, cr3_target_count),
639 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
640 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
641 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
642 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
643 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
644 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
645 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
646 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
647 FIELD(TPR_THRESHOLD, tpr_threshold),
648 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
649 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
650 FIELD(VM_EXIT_REASON, vm_exit_reason),
651 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
652 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
653 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
654 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
655 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
656 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
657 FIELD(GUEST_ES_LIMIT, guest_es_limit),
658 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
659 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
660 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
661 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
662 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
663 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
664 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
665 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
666 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
667 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
668 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
669 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
670 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
671 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
672 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
673 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
674 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
675 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
676 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
677 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
678 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
0238ea91 679 FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
22bd0358
NHE		 680 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
681 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
682 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
683 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
684 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
685 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
686 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
687 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
688 FIELD(EXIT_QUALIFICATION, exit_qualification),
689 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
690 FIELD(GUEST_CR0, guest_cr0),
691 FIELD(GUEST_CR3, guest_cr3),
692 FIELD(GUEST_CR4, guest_cr4),
693 FIELD(GUEST_ES_BASE, guest_es_base),
694 FIELD(GUEST_CS_BASE, guest_cs_base),
695 FIELD(GUEST_SS_BASE, guest_ss_base),
696 FIELD(GUEST_DS_BASE, guest_ds_base),
697 FIELD(GUEST_FS_BASE, guest_fs_base),
698 FIELD(GUEST_GS_BASE, guest_gs_base),
699 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
700 FIELD(GUEST_TR_BASE, guest_tr_base),
701 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
702 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
703 FIELD(GUEST_DR7, guest_dr7),
704 FIELD(GUEST_RSP, guest_rsp),
705 FIELD(GUEST_RIP, guest_rip),
706 FIELD(GUEST_RFLAGS, guest_rflags),
707 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
708 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
709 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
710 FIELD(HOST_CR0, host_cr0),
711 FIELD(HOST_CR3, host_cr3),
712 FIELD(HOST_CR4, host_cr4),
713 FIELD(HOST_FS_BASE, host_fs_base),
714 FIELD(HOST_GS_BASE, host_gs_base),
715 FIELD(HOST_TR_BASE, host_tr_base),
716 FIELD(HOST_GDTR_BASE, host_gdtr_base),
717 FIELD(HOST_IDTR_BASE, host_idtr_base),
718 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
719 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
720 FIELD(HOST_RSP, host_rsp),
721 FIELD(HOST_RIP, host_rip),
722};
22bd0358
NHE		 723
724static inline short vmcs_field_to_offset(unsigned long field)
725{
a2ae9df7
PB		 726 BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table) > SHRT_MAX);
727
728 if (field >= ARRAY_SIZE(vmcs_field_to_offset_table) ||
729 vmcs_field_to_offset_table[field] == 0)
730 return -ENOENT;
731
22bd0358
NHE		 732 return vmcs_field_to_offset_table[field];
733}
734
a9d30f33
NHE		 735static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
736{
737 return to_vmx(vcpu)->nested.current_vmcs12;
738}
739
740static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
741{
742 struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
32cad84f 743 if (is_error_page(page))
a9d30f33 744 return NULL;
32cad84f 745
a9d30f33
NHE		 746 return page;
747}
748
749static void nested_release_page(struct page *page)
750{
751 kvm_release_page_dirty(page);
752}
753
754static void nested_release_page_clean(struct page *page)
755{
756 kvm_release_page_clean(page);
757}
758
bfd0a56b 759static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
4e1096d2 760static u64 construct_eptp(unsigned long root_hpa);
4610c9cc
DX		 761static void kvm_cpu_vmxon(u64 addr);
762static void kvm_cpu_vmxoff(void);
93c4adc7 763static bool vmx_mpx_supported(void);
776e58ea 764static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
b246dd5d
OW		 765static void vmx_set_segment(struct kvm_vcpu *vcpu,
766 struct kvm_segment *var, int seg);
767static void vmx_get_segment(struct kvm_vcpu *vcpu,
768 struct kvm_segment *var, int seg);
d99e4152
GN		 769static bool guest_state_valid(struct kvm_vcpu *vcpu);
770static u32 vmx_segment_access_rights(struct kvm_segment *var);
a20ed54d 771static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu);
c3114420 772static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
16f5b903 773static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
a255d479 774static int alloc_identity_pagetable(struct kvm *kvm);
75880a01 775
6aa8b732
AK		 776static DEFINE_PER_CPU(struct vmcs *, vmxarea);
777static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
d462b819
NHE		 778/*
779 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
780 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
781 */
782static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
3444d7da 783static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
6aa8b732 784
3e7c73e9
AK		 785static unsigned long *vmx_io_bitmap_a;
786static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 787static unsigned long *vmx_msr_bitmap_legacy;
788static unsigned long *vmx_msr_bitmap_longmode;
8d14695f
YZ		 789static unsigned long *vmx_msr_bitmap_legacy_x2apic;
790static unsigned long *vmx_msr_bitmap_longmode_x2apic;
4607c2d7
AG		 791static unsigned long *vmx_vmread_bitmap;
792static unsigned long *vmx_vmwrite_bitmap;
fdef3ad1 793
110312c8 794static bool cpu_has_load_ia32_efer;
8bf00a52 795static bool cpu_has_load_perf_global_ctrl;
110312c8 796
2384d2b3
SY		 797static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
798static DEFINE_SPINLOCK(vmx_vpid_lock);
799
1c3d14fe 800static struct vmcs_config {
6aa8b732
AK		 801 int size;
802 int order;
803 u32 revision_id;
1c3d14fe
YS		 804 u32 pin_based_exec_ctrl;
805 u32 cpu_based_exec_ctrl;
f78e0e2e 806 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 807 u32 vmexit_ctrl;
808 u32 vmentry_ctrl;
809} vmcs_config;
6aa8b732 810
efff9e53 811static struct vmx_capability {
d56f546d
SY		 812 u32 ept;
813 u32 vpid;
814} vmx_capability;
815
6aa8b732
AK		 816#define VMX_SEGMENT_FIELD(seg) \
817 [VCPU_SREG_##seg] = { \
818 .selector = GUEST_##seg##_SELECTOR, \
819 .base = GUEST_##seg##_BASE, \
820 .limit = GUEST_##seg##_LIMIT, \
821 .ar_bytes = GUEST_##seg##_AR_BYTES, \
822 }
823
772e0318 824static const struct kvm_vmx_segment_field {
6aa8b732
AK		 825 unsigned selector;
826 unsigned base;
827 unsigned limit;
828 unsigned ar_bytes;
829} kvm_vmx_segment_fields[] = {
830 VMX_SEGMENT_FIELD(CS),
831 VMX_SEGMENT_FIELD(DS),
832 VMX_SEGMENT_FIELD(ES),
833 VMX_SEGMENT_FIELD(FS),
834 VMX_SEGMENT_FIELD(GS),
835 VMX_SEGMENT_FIELD(SS),
836 VMX_SEGMENT_FIELD(TR),
837 VMX_SEGMENT_FIELD(LDTR),
838};
839
26bb0981
AK		 840static u64 host_efer;
841
6de4f3ad
AK		 842static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
843
4d56c8a7 844/*
8c06585d 845 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
4d56c8a7
AK		 846 * away by decrementing the array size.
847 */
6aa8b732 848static const u32 vmx_msr_index[] = {
05b3e0c2 849#ifdef CONFIG_X86_64
44ea2b17 850 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 851#endif
8c06585d 852 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
6aa8b732 853};
6aa8b732 854
31299944 855static inline bool is_page_fault(u32 intr_info)
6aa8b732
AK		 856{
857 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
858 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 859 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 860}
861
31299944 862static inline bool is_no_device(u32 intr_info)
2ab455cc
AL		 863{
864 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
865 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 866 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 867}
868
31299944 869static inline bool is_invalid_opcode(u32 intr_info)
7aa81cc0
AL		 870{
871 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
872 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 873 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 874}
875
31299944 876static inline bool is_external_interrupt(u32 intr_info)
6aa8b732
AK		 877{
878 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
879 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
880}
881
31299944 882static inline bool is_machine_check(u32 intr_info)
a0861c02
AK		 883{
884 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
885 INTR_INFO_VALID_MASK)) ==
886 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
887}
888
31299944 889static inline bool cpu_has_vmx_msr_bitmap(void)
25c5f225 890{
04547156 891 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 892}
893
31299944 894static inline bool cpu_has_vmx_tpr_shadow(void)
6e5d865c 895{
04547156 896 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 897}
898
31299944 899static inline bool vm_need_tpr_shadow(struct kvm *kvm)
6e5d865c 900{
04547156 901 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
6e5d865c
YS		 902}
903
31299944 904static inline bool cpu_has_secondary_exec_ctrls(void)
f78e0e2e 905{
04547156
SY		 906 return vmcs_config.cpu_based_exec_ctrl &
907 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 908}
909
774ead3a 910static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 911{
04547156
SY		 912 return vmcs_config.cpu_based_2nd_exec_ctrl &
913 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
914}
915
8d14695f
YZ		 916static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
917{
918 return vmcs_config.cpu_based_2nd_exec_ctrl &
919 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
920}
921
83d4c286
YZ		 922static inline bool cpu_has_vmx_apic_register_virt(void)
923{
924 return vmcs_config.cpu_based_2nd_exec_ctrl &
925 SECONDARY_EXEC_APIC_REGISTER_VIRT;
926}
927
c7c9c56c
YZ		 928static inline bool cpu_has_vmx_virtual_intr_delivery(void)
929{
930 return vmcs_config.cpu_based_2nd_exec_ctrl &
931 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
932}
933
01e439be
YZ		 934static inline bool cpu_has_vmx_posted_intr(void)
935{
936 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
937}
938
939static inline bool cpu_has_vmx_apicv(void)
940{
941 return cpu_has_vmx_apic_register_virt() &&
942 cpu_has_vmx_virtual_intr_delivery() &&
943 cpu_has_vmx_posted_intr();
944}
945
04547156
SY		 946static inline bool cpu_has_vmx_flexpriority(void)
947{
948 return cpu_has_vmx_tpr_shadow() &&
949 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 950}
951
e799794e
MT		 952static inline bool cpu_has_vmx_ept_execute_only(void)
953{
31299944 954 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
e799794e
MT		 955}
956
957static inline bool cpu_has_vmx_eptp_uncacheable(void)
958{
31299944 959 return vmx_capability.ept & VMX_EPTP_UC_BIT;
e799794e
MT		 960}
961
962static inline bool cpu_has_vmx_eptp_writeback(void)
963{
31299944 964 return vmx_capability.ept & VMX_EPTP_WB_BIT;
e799794e
MT		 965}
966
967static inline bool cpu_has_vmx_ept_2m_page(void)
968{
31299944 969 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
e799794e
MT		 970}
971
878403b7
SY		 972static inline bool cpu_has_vmx_ept_1g_page(void)
973{
31299944 974 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
878403b7
SY		 975}
976
4bc9b982
SY		 977static inline bool cpu_has_vmx_ept_4levels(void)
978{
979 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
980}
981
83c3a331
XH		 982static inline bool cpu_has_vmx_ept_ad_bits(void)
983{
984 return vmx_capability.ept & VMX_EPT_AD_BIT;
985}
986
31299944 987static inline bool cpu_has_vmx_invept_context(void)
d56f546d 988{
31299944 989 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
d56f546d
SY		 990}
991
31299944 992static inline bool cpu_has_vmx_invept_global(void)
d56f546d 993{
31299944 994 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
d56f546d
SY		 995}
996
518c8aee
GJ		 997static inline bool cpu_has_vmx_invvpid_single(void)
998{
999 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1000}
1001
b9d762fa
GJ		 1002static inline bool cpu_has_vmx_invvpid_global(void)
1003{
1004 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1005}
1006
31299944 1007static inline bool cpu_has_vmx_ept(void)
d56f546d 1008{
04547156
SY		 1009 return vmcs_config.cpu_based_2nd_exec_ctrl &
1010 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 1011}
1012
31299944 1013static inline bool cpu_has_vmx_unrestricted_guest(void)
3a624e29
NK		 1014{
1015 return vmcs_config.cpu_based_2nd_exec_ctrl &
1016 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1017}
1018
31299944 1019static inline bool cpu_has_vmx_ple(void)
4b8d54f9
ZE		 1020{
1021 return vmcs_config.cpu_based_2nd_exec_ctrl &
1022 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1023}
1024
31299944 1025static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
f78e0e2e 1026{
6d3e435e 1027 return flexpriority_enabled && irqchip_in_kernel(kvm);
f78e0e2e
SY		 1028}
1029
31299944 1030static inline bool cpu_has_vmx_vpid(void)
2384d2b3 1031{
04547156
SY		 1032 return vmcs_config.cpu_based_2nd_exec_ctrl &
1033 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 1034}
1035
31299944 1036static inline bool cpu_has_vmx_rdtscp(void)
4e47c7a6
SY		 1037{
1038 return vmcs_config.cpu_based_2nd_exec_ctrl &
1039 SECONDARY_EXEC_RDTSCP;
1040}
1041
ad756a16
MJ		 1042static inline bool cpu_has_vmx_invpcid(void)
1043{
1044 return vmcs_config.cpu_based_2nd_exec_ctrl &
1045 SECONDARY_EXEC_ENABLE_INVPCID;
1046}
1047
31299944 1048static inline bool cpu_has_virtual_nmis(void)
f08864b4
SY		 1049{
1050 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1051}
1052
f5f48ee1
SY		 1053static inline bool cpu_has_vmx_wbinvd_exit(void)
1054{
1055 return vmcs_config.cpu_based_2nd_exec_ctrl &
1056 SECONDARY_EXEC_WBINVD_EXITING;
1057}
1058
abc4fc58
AG		 1059static inline bool cpu_has_vmx_shadow_vmcs(void)
1060{
1061 u64 vmx_msr;
1062 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1063 /* check if the cpu supports writing r/o exit information fields */
1064 if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1065 return false;
1066
1067 return vmcs_config.cpu_based_2nd_exec_ctrl &
1068 SECONDARY_EXEC_SHADOW_VMCS;
1069}
1070
04547156
SY		 1071static inline bool report_flexpriority(void)
1072{
1073 return flexpriority_enabled;
1074}
1075
fe3ef05c
NHE		 1076static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1077{
1078 return vmcs12->cpu_based_vm_exec_control & bit;
1079}
1080
1081static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1082{
1083 return (vmcs12->cpu_based_vm_exec_control &
1084 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1085 (vmcs12->secondary_vm_exec_control & bit);
1086}
1087
f5c4368f 1088static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
644d711a
NHE		 1089{
1090 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1091}
1092
f4124500
JK		 1093static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1094{
1095 return vmcs12->pin_based_vm_exec_control &
1096 PIN_BASED_VMX_PREEMPTION_TIMER;
1097}
1098
155a97a3
NHE		 1099static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1100{
1101 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1102}
1103
644d711a
NHE		 1104static inline bool is_exception(u32 intr_info)
1105{
1106 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1107 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1108}
1109
533558bc
JK		 1110static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1111 u32 exit_intr_info,
1112 unsigned long exit_qualification);
7c177938
NHE		 1113static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1114 struct vmcs12 *vmcs12,
1115 u32 reason, unsigned long qualification);
1116
8b9cf98c 1117static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 1118{
1119 int i;
1120
a2fa3e9f 1121 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 1122 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 1123 return i;
1124 return -1;
1125}
1126
2384d2b3
SY		 1127static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1128{
1129 struct {
1130 u64 vpid : 16;
1131 u64 rsvd : 48;
1132 u64 gva;
1133 } operand = { vpid, 0, gva };
1134
4ecac3fd 1135 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 1136 /* CF==1 or ZF==1 --> rc = -1 */
1137 "; ja 1f ; ud2 ; 1:"
1138 : : "a"(&operand), "c"(ext) : "cc", "memory");
1139}
1140
1439442c
SY		 1141static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1142{
1143 struct {
1144 u64 eptp, gpa;
1145 } operand = {eptp, gpa};
1146
4ecac3fd 1147 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 1148 /* CF==1 or ZF==1 --> rc = -1 */
1149 "; ja 1f ; ud2 ; 1:\n"
1150 : : "a" (&operand), "c" (ext) : "cc", "memory");
1151}
1152
26bb0981 1153static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 1154{
1155 int i;
1156
8b9cf98c 1157 i = __find_msr_index(vmx, msr);
a75beee6 1158 if (i >= 0)
a2fa3e9f 1159 return &vmx->guest_msrs[i];
8b6d44c7 1160 return NULL;
7725f0ba
AK		 1161}
1162
6aa8b732
AK		 1163static void vmcs_clear(struct vmcs *vmcs)
1164{
1165 u64 phys_addr = __pa(vmcs);
1166 u8 error;
1167
4ecac3fd 1168 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
16d8f72f 1169 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
6aa8b732
AK		 1170 : "cc", "memory");
1171 if (error)
1172 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1173 vmcs, phys_addr);
1174}
1175
d462b819
NHE		 1176static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1177{
1178 vmcs_clear(loaded_vmcs->vmcs);
1179 loaded_vmcs->cpu = -1;
1180 loaded_vmcs->launched = 0;
1181}
1182
7725b894
DX		 1183static void vmcs_load(struct vmcs *vmcs)
1184{
1185 u64 phys_addr = __pa(vmcs);
1186 u8 error;
1187
1188 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
16d8f72f 1189 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
7725b894
DX		 1190 : "cc", "memory");
1191 if (error)
2844d849 1192 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
7725b894
DX		 1193 vmcs, phys_addr);
1194}
1195
8f536b76
ZY		 1196#ifdef CONFIG_KEXEC
1197/*
1198 * This bitmap is used to indicate whether the vmclear
1199 * operation is enabled on all cpus. All disabled by
1200 * default.
1201 */
1202static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1203
1204static inline void crash_enable_local_vmclear(int cpu)
1205{
1206 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1207}
1208
1209static inline void crash_disable_local_vmclear(int cpu)
1210{
1211 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1212}
1213
1214static inline int crash_local_vmclear_enabled(int cpu)
1215{
1216 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1217}
1218
1219static void crash_vmclear_local_loaded_vmcss(void)
1220{
1221 int cpu = raw_smp_processor_id();
1222 struct loaded_vmcs *v;
1223
1224 if (!crash_local_vmclear_enabled(cpu))
1225 return;
1226
1227 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1228 loaded_vmcss_on_cpu_link)
1229 vmcs_clear(v->vmcs);
1230}
1231#else
1232static inline void crash_enable_local_vmclear(int cpu) { }
1233static inline void crash_disable_local_vmclear(int cpu) { }
1234#endif /* CONFIG_KEXEC */
1235
d462b819 1236static void __loaded_vmcs_clear(void *arg)
6aa8b732 1237{
d462b819 1238 struct loaded_vmcs *loaded_vmcs = arg;
d3b2c338 1239 int cpu = raw_smp_processor_id();
6aa8b732 1240
d462b819
NHE		 1241 if (loaded_vmcs->cpu != cpu)
1242 return; /* vcpu migration can race with cpu offline */
1243 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
6aa8b732 1244 per_cpu(current_vmcs, cpu) = NULL;
8f536b76 1245 crash_disable_local_vmclear(cpu);
d462b819 1246 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
5a560f8b
XG		 1247
1248 /*
1249 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1250 * is before setting loaded_vmcs->vcpu to -1 which is done in
1251 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1252 * then adds the vmcs into percpu list before it is deleted.
1253 */
1254 smp_wmb();
1255
d462b819 1256 loaded_vmcs_init(loaded_vmcs);
8f536b76 1257 crash_enable_local_vmclear(cpu);
6aa8b732
AK		 1258}
1259
d462b819 1260static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
8d0be2b3 1261{
e6c7d321
XG		 1262 int cpu = loaded_vmcs->cpu;
1263
1264 if (cpu != -1)
1265 smp_call_function_single(cpu,
1266 __loaded_vmcs_clear, loaded_vmcs, 1);
8d0be2b3
AK		 1267}
1268
1760dd49 1269static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
2384d2b3
SY		 1270{
1271 if (vmx->vpid == 0)
1272 return;
1273
518c8aee
GJ		 1274 if (cpu_has_vmx_invvpid_single())
1275 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
2384d2b3
SY		 1276}
1277
b9d762fa
GJ		 1278static inline void vpid_sync_vcpu_global(void)
1279{
1280 if (cpu_has_vmx_invvpid_global())
1281 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1282}
1283
1284static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1285{
1286 if (cpu_has_vmx_invvpid_single())
1760dd49 1287 vpid_sync_vcpu_single(vmx);
b9d762fa
GJ		 1288 else
1289 vpid_sync_vcpu_global();
1290}
1291
1439442c
SY		 1292static inline void ept_sync_global(void)
1293{
1294 if (cpu_has_vmx_invept_global())
1295 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1296}
1297
1298static inline void ept_sync_context(u64 eptp)
1299{
089d034e 1300 if (enable_ept) {
1439442c
SY		 1301 if (cpu_has_vmx_invept_context())
1302 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1303 else
1304 ept_sync_global();
1305 }
1306}
1307
96304217 1308static __always_inline unsigned long vmcs_readl(unsigned long field)
6aa8b732 1309{
5e520e62 1310 unsigned long value;
6aa8b732 1311
5e520e62
AK		 1312 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1313 : "=a"(value) : "d"(field) : "cc");
6aa8b732
AK		 1314 return value;
1315}
1316
96304217 1317static __always_inline u16 vmcs_read16(unsigned long field)
6aa8b732
AK		 1318{
1319 return vmcs_readl(field);
1320}
1321
96304217 1322static __always_inline u32 vmcs_read32(unsigned long field)
6aa8b732
AK		 1323{
1324 return vmcs_readl(field);
1325}
1326
96304217 1327static __always_inline u64 vmcs_read64(unsigned long field)
6aa8b732 1328{
05b3e0c2 1329#ifdef CONFIG_X86_64
6aa8b732
AK		 1330 return vmcs_readl(field);
1331#else
1332 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1333#endif
1334}
1335
e52de1b8
AK		 1336static noinline void vmwrite_error(unsigned long field, unsigned long value)
1337{
1338 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1339 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1340 dump_stack();
1341}
1342
6aa8b732
AK		 1343static void vmcs_writel(unsigned long field, unsigned long value)
1344{
1345 u8 error;
1346
4ecac3fd 1347 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 1348 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 1349 if (unlikely(error))
1350 vmwrite_error(field, value);
6aa8b732
AK		 1351}
1352
1353static void vmcs_write16(unsigned long field, u16 value)
1354{
1355 vmcs_writel(field, value);
1356}
1357
1358static void vmcs_write32(unsigned long field, u32 value)
1359{
1360 vmcs_writel(field, value);
1361}
1362
1363static void vmcs_write64(unsigned long field, u64 value)
1364{
6aa8b732 1365 vmcs_writel(field, value);
7682f2d0 1366#ifndef CONFIG_X86_64
6aa8b732
AK		 1367 asm volatile ("");
1368 vmcs_writel(field+1, value >> 32);
1369#endif
1370}
1371
2ab455cc
AL		 1372static void vmcs_clear_bits(unsigned long field, u32 mask)
1373{
1374 vmcs_writel(field, vmcs_readl(field) & ~mask);
1375}
1376
1377static void vmcs_set_bits(unsigned long field, u32 mask)
1378{
1379 vmcs_writel(field, vmcs_readl(field) | mask);
1380}
1381
2961e876
GN		 1382static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1383{
1384 vmcs_write32(VM_ENTRY_CONTROLS, val);
1385 vmx->vm_entry_controls_shadow = val;
1386}
1387
1388static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1389{
1390 if (vmx->vm_entry_controls_shadow != val)
1391 vm_entry_controls_init(vmx, val);
1392}
1393
1394static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1395{
1396 return vmx->vm_entry_controls_shadow;
1397}
1398
1399
1400static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1401{
1402 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1403}
1404
1405static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1406{
1407 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1408}
1409
1410static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1411{
1412 vmcs_write32(VM_EXIT_CONTROLS, val);
1413 vmx->vm_exit_controls_shadow = val;
1414}
1415
1416static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1417{
1418 if (vmx->vm_exit_controls_shadow != val)
1419 vm_exit_controls_init(vmx, val);
1420}
1421
1422static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1423{
1424 return vmx->vm_exit_controls_shadow;
1425}
1426
1427
1428static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1429{
1430 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1431}
1432
1433static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1434{
1435 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1436}
1437
2fb92db1
AK		 1438static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1439{
1440 vmx->segment_cache.bitmask = 0;
1441}
1442
1443static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1444 unsigned field)
1445{
1446 bool ret;
1447 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1448
1449 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1450 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1451 vmx->segment_cache.bitmask = 0;
1452 }
1453 ret = vmx->segment_cache.bitmask & mask;
1454 vmx->segment_cache.bitmask |= mask;
1455 return ret;
1456}
1457
1458static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1459{
1460 u16 *p = &vmx->segment_cache.seg[seg].selector;
1461
1462 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1463 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1464 return *p;
1465}
1466
1467static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1468{
1469 ulong *p = &vmx->segment_cache.seg[seg].base;
1470
1471 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1472 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1473 return *p;
1474}
1475
1476static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1477{
1478 u32 *p = &vmx->segment_cache.seg[seg].limit;
1479
1480 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1481 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1482 return *p;
1483}
1484
1485static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1486{
1487 u32 *p = &vmx->segment_cache.seg[seg].ar;
1488
1489 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1490 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1491 return *p;
1492}
1493
abd3f2d6
AK		 1494static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1495{
1496 u32 eb;
1497
fd7373cc
JK		 1498 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1499 (1u << NM_VECTOR) | (1u << DB_VECTOR);
1500 if ((vcpu->guest_debug &
1501 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1502 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1503 eb |= 1u << BP_VECTOR;
7ffd92c5 1504 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 1505 eb = ~0;
089d034e 1506 if (enable_ept)
1439442c 1507 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
02daab21
AK		 1508 if (vcpu->fpu_active)
1509 eb &= ~(1u << NM_VECTOR);
36cf24e0
NHE		 1510
1511 /* When we are running a nested L2 guest and L1 specified for it a
1512 * certain exception bitmap, we must trap the same exceptions and pass
1513 * them to L1. When running L2, we will only handle the exceptions
1514 * specified above if L1 did not want them.
1515 */
1516 if (is_guest_mode(vcpu))
1517 eb |= get_vmcs12(vcpu)->exception_bitmap;
1518
abd3f2d6
AK		 1519 vmcs_write32(EXCEPTION_BITMAP, eb);
1520}
1521
2961e876
GN		 1522static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1523 unsigned long entry, unsigned long exit)
8bf00a52 1524{
2961e876
GN		 1525 vm_entry_controls_clearbit(vmx, entry);
1526 vm_exit_controls_clearbit(vmx, exit);
8bf00a52
GN		 1527}
1528
61d2ef2c
AK		 1529static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1530{
1531 unsigned i;
1532 struct msr_autoload *m = &vmx->msr_autoload;
1533
8bf00a52
GN		 1534 switch (msr) {
1535 case MSR_EFER:
1536 if (cpu_has_load_ia32_efer) {
2961e876
GN		 1537 clear_atomic_switch_msr_special(vmx,
1538 VM_ENTRY_LOAD_IA32_EFER,
8bf00a52
GN		 1539 VM_EXIT_LOAD_IA32_EFER);
1540 return;
1541 }
1542 break;
1543 case MSR_CORE_PERF_GLOBAL_CTRL:
1544 if (cpu_has_load_perf_global_ctrl) {
2961e876 1545 clear_atomic_switch_msr_special(vmx,
8bf00a52
GN		 1546 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1547 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1548 return;
1549 }
1550 break;
110312c8
AK		 1551 }
1552
61d2ef2c
AK		 1553 for (i = 0; i < m->nr; ++i)
1554 if (m->guest[i].index == msr)
1555 break;
1556
1557 if (i == m->nr)
1558 return;
1559 --m->nr;
1560 m->guest[i] = m->guest[m->nr];
1561 m->host[i] = m->host[m->nr];
1562 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1563 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1564}
1565
2961e876
GN		 1566static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1567 unsigned long entry, unsigned long exit,
1568 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1569 u64 guest_val, u64 host_val)
8bf00a52
GN		 1570{
1571 vmcs_write64(guest_val_vmcs, guest_val);
1572 vmcs_write64(host_val_vmcs, host_val);
2961e876
GN		 1573 vm_entry_controls_setbit(vmx, entry);
1574 vm_exit_controls_setbit(vmx, exit);
8bf00a52
GN		 1575}
1576
61d2ef2c
AK		 1577static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1578 u64 guest_val, u64 host_val)
1579{
1580 unsigned i;
1581 struct msr_autoload *m = &vmx->msr_autoload;
1582
8bf00a52
GN		 1583 switch (msr) {
1584 case MSR_EFER:
1585 if (cpu_has_load_ia32_efer) {
2961e876
GN		 1586 add_atomic_switch_msr_special(vmx,
1587 VM_ENTRY_LOAD_IA32_EFER,
8bf00a52
GN		 1588 VM_EXIT_LOAD_IA32_EFER,
1589 GUEST_IA32_EFER,
1590 HOST_IA32_EFER,
1591 guest_val, host_val);
1592 return;
1593 }
1594 break;
1595 case MSR_CORE_PERF_GLOBAL_CTRL:
1596 if (cpu_has_load_perf_global_ctrl) {
2961e876 1597 add_atomic_switch_msr_special(vmx,
8bf00a52
GN		 1598 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1599 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1600 GUEST_IA32_PERF_GLOBAL_CTRL,
1601 HOST_IA32_PERF_GLOBAL_CTRL,
1602 guest_val, host_val);
1603 return;
1604 }
1605 break;
110312c8
AK		 1606 }
1607
61d2ef2c
AK		 1608 for (i = 0; i < m->nr; ++i)
1609 if (m->guest[i].index == msr)
1610 break;
1611
e7fc6f93 1612 if (i == NR_AUTOLOAD_MSRS) {
60266204 1613 printk_once(KERN_WARNING "Not enough msr switch entries. "
e7fc6f93
GN		 1614 "Can't add msr %x\n", msr);
1615 return;
1616 } else if (i == m->nr) {
61d2ef2c
AK		 1617 ++m->nr;
1618 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1619 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1620 }
1621
1622 m->guest[i].index = msr;
1623 m->guest[i].value = guest_val;
1624 m->host[i].index = msr;
1625 m->host[i].value = host_val;
1626}
1627
33ed6329
AK		 1628static void reload_tss(void)
1629{
33ed6329
AK		 1630 /*
1631 * VT restores TR but not its size. Useless.
1632 */
89cbc767 1633 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
a5f61300 1634 struct desc_struct *descs;
33ed6329 1635
d359192f 1636 descs = (void *)gdt->address;
33ed6329
AK		 1637 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1638 load_TR_desc();
33ed6329
AK		 1639}
1640
92c0d900 1641static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 1642{
3a34a881 1643 u64 guest_efer;
51c6cf66
AK		 1644 u64 ignore_bits;
1645
f6801dff 1646 guest_efer = vmx->vcpu.arch.efer;
3a34a881 1647
51c6cf66 1648 /*
0fa06071 1649 * NX is emulated; LMA and LME handled by hardware; SCE meaningless
51c6cf66
AK		 1650 * outside long mode
1651 */
1652 ignore_bits = EFER_NX | EFER_SCE;
1653#ifdef CONFIG_X86_64
1654 ignore_bits |= EFER_LMA | EFER_LME;
1655 /* SCE is meaningful only in long mode on Intel */
1656 if (guest_efer & EFER_LMA)
1657 ignore_bits &= ~(u64)EFER_SCE;
1658#endif
51c6cf66
AK		 1659 guest_efer &= ~ignore_bits;
1660 guest_efer |= host_efer & ignore_bits;
26bb0981 1661 vmx->guest_msrs[efer_offset].data = guest_efer;
d5696725 1662 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef
AK		 1663
1664 clear_atomic_switch_msr(vmx, MSR_EFER);
f6577a5f
AL		 1665
1666 /*
1667 * On EPT, we can't emulate NX, so we must switch EFER atomically.
1668 * On CPUs that support "load IA32_EFER", always switch EFER
1669 * atomically, since it's faster than switching it manually.
1670 */
1671 if (cpu_has_load_ia32_efer ||
1672 (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
84ad33ef
AK		 1673 guest_efer = vmx->vcpu.arch.efer;
1674 if (!(guest_efer & EFER_LMA))
1675 guest_efer &= ~EFER_LME;
54b98bff
AL		 1676 if (guest_efer != host_efer)
1677 add_atomic_switch_msr(vmx, MSR_EFER,
1678 guest_efer, host_efer);
84ad33ef
AK		 1679 return false;
1680 }
1681
26bb0981 1682 return true;
51c6cf66
AK		 1683}
1684
2d49ec72
GN		 1685static unsigned long segment_base(u16 selector)
1686{
89cbc767 1687 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
2d49ec72
GN		 1688 struct desc_struct *d;
1689 unsigned long table_base;
1690 unsigned long v;
1691
1692 if (!(selector & ~3))
1693 return 0;
1694
d359192f 1695 table_base = gdt->address;
2d49ec72
GN		 1696
1697 if (selector & 4) { /* from ldt */
1698 u16 ldt_selector = kvm_read_ldt();
1699
1700 if (!(ldt_selector & ~3))
1701 return 0;
1702
1703 table_base = segment_base(ldt_selector);
1704 }
1705 d = (struct desc_struct *)(table_base + (selector & ~7));
1706 v = get_desc_base(d);
1707#ifdef CONFIG_X86_64
1708 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1709 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1710#endif
1711 return v;
1712}
1713
1714static inline unsigned long kvm_read_tr_base(void)
1715{
1716 u16 tr;
1717 asm("str %0" : "=g"(tr));
1718 return segment_base(tr);
1719}
1720
04d2cc77 1721static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 1722{
04d2cc77 1723 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1724 int i;
04d2cc77 1725
a2fa3e9f 1726 if (vmx->host_state.loaded)
33ed6329
AK		 1727 return;
1728
a2fa3e9f 1729 vmx->host_state.loaded = 1;
33ed6329
AK		 1730 /*
1731 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1732 * allow segment selectors with cpl > 0 or ti == 1.
1733 */
d6e88aec 1734 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 1735 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
9581d442 1736 savesegment(fs, vmx->host_state.fs_sel);
152d3f2f 1737 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 1738 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 1739 vmx->host_state.fs_reload_needed = 0;
1740 } else {
33ed6329 1741 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 1742 vmx->host_state.fs_reload_needed = 1;
33ed6329 1743 }
9581d442 1744 savesegment(gs, vmx->host_state.gs_sel);
a2fa3e9f
GH		 1745 if (!(vmx->host_state.gs_sel & 7))
1746 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 1747 else {
1748 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 1749 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 1750 }
1751
b2da15ac
AK		 1752#ifdef CONFIG_X86_64
1753 savesegment(ds, vmx->host_state.ds_sel);
1754 savesegment(es, vmx->host_state.es_sel);
1755#endif
1756
33ed6329
AK		 1757#ifdef CONFIG_X86_64
1758 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1759 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1760#else
a2fa3e9f
GH		 1761 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1762 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 1763#endif
707c0874
AK		 1764
1765#ifdef CONFIG_X86_64
c8770e7b
AK		 1766 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1767 if (is_long_mode(&vmx->vcpu))
44ea2b17 1768 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
707c0874 1769#endif
da8999d3
LJ		 1770 if (boot_cpu_has(X86_FEATURE_MPX))
1771 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
26bb0981
AK		 1772 for (i = 0; i < vmx->save_nmsrs; ++i)
1773 kvm_set_shared_msr(vmx->guest_msrs[i].index,
d5696725
AK		 1774 vmx->guest_msrs[i].data,
1775 vmx->guest_msrs[i].mask);
33ed6329
AK		 1776}
1777
a9b21b62 1778static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 1779{
a2fa3e9f 1780 if (!vmx->host_state.loaded)
33ed6329
AK		 1781 return;
1782
e1beb1d3 1783 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 1784 vmx->host_state.loaded = 0;
c8770e7b
AK		 1785#ifdef CONFIG_X86_64
1786 if (is_long_mode(&vmx->vcpu))
1787 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1788#endif
152d3f2f 1789 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 1790 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329 1791#ifdef CONFIG_X86_64
9581d442 1792 load_gs_index(vmx->host_state.gs_sel);
9581d442
AK		 1793#else
1794 loadsegment(gs, vmx->host_state.gs_sel);
33ed6329 1795#endif
33ed6329 1796 }
0a77fe4c
AK		 1797 if (vmx->host_state.fs_reload_needed)
1798 loadsegment(fs, vmx->host_state.fs_sel);
b2da15ac
AK		 1799#ifdef CONFIG_X86_64
1800 if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1801 loadsegment(ds, vmx->host_state.ds_sel);
1802 loadsegment(es, vmx->host_state.es_sel);
1803 }
b2da15ac 1804#endif
152d3f2f 1805 reload_tss();
44ea2b17 1806#ifdef CONFIG_X86_64
c8770e7b 1807 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
44ea2b17 1808#endif
da8999d3
LJ		 1809 if (vmx->host_state.msr_host_bndcfgs)
1810 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
b1a74bf8
SS		 1811 /*
1812 * If the FPU is not active (through the host task or
1813 * the guest vcpu), then restore the cr0.TS bit.
1814 */
1815 if (!user_has_fpu() && !vmx->vcpu.guest_fpu_loaded)
1816 stts();
89cbc767 1817 load_gdt(this_cpu_ptr(&host_gdt));
33ed6329
AK		 1818}
1819
a9b21b62
AK		 1820static void vmx_load_host_state(struct vcpu_vmx *vmx)
1821{
1822 preempt_disable();
1823 __vmx_load_host_state(vmx);
1824 preempt_enable();
1825}
1826
6aa8b732
AK		 1827/*
1828 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1829 * vcpu mutex is already taken.
1830 */
15ad7146 1831static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 1832{
a2fa3e9f 1833 struct vcpu_vmx *vmx = to_vmx(vcpu);
4610c9cc 1834 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
6aa8b732 1835
4610c9cc
DX		 1836 if (!vmm_exclusive)
1837 kvm_cpu_vmxon(phys_addr);
d462b819
NHE		 1838 else if (vmx->loaded_vmcs->cpu != cpu)
1839 loaded_vmcs_clear(vmx->loaded_vmcs);
6aa8b732 1840
d462b819
NHE		 1841 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1842 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1843 vmcs_load(vmx->loaded_vmcs->vmcs);
6aa8b732
AK		 1844 }
1845
d462b819 1846 if (vmx->loaded_vmcs->cpu != cpu) {
89cbc767 1847 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
6aa8b732
AK		 1848 unsigned long sysenter_esp;
1849
a8eeb04a 1850 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
92fe13be 1851 local_irq_disable();
8f536b76 1852 crash_disable_local_vmclear(cpu);
5a560f8b
XG		 1853
1854 /*
1855 * Read loaded_vmcs->cpu should be before fetching
1856 * loaded_vmcs->loaded_vmcss_on_cpu_link.
1857 * See the comments in __loaded_vmcs_clear().
1858 */
1859 smp_rmb();
1860
d462b819
NHE		 1861 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1862 &per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76 1863 crash_enable_local_vmclear(cpu);
92fe13be
DX		 1864 local_irq_enable();
1865
6aa8b732
AK		 1866 /*
1867 * Linux uses per-cpu TSS and GDT, so set these when switching
1868 * processors.
1869 */
d6e88aec 1870 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
d359192f 1871 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
6aa8b732
AK		 1872
1873 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1874 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
d462b819 1875 vmx->loaded_vmcs->cpu = cpu;
6aa8b732 1876 }
6aa8b732
AK		 1877}
1878
1879static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1880{
a9b21b62 1881 __vmx_load_host_state(to_vmx(vcpu));
4610c9cc 1882 if (!vmm_exclusive) {
d462b819
NHE		 1883 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1884 vcpu->cpu = -1;
4610c9cc
DX		 1885 kvm_cpu_vmxoff();
1886 }
6aa8b732
AK		 1887}
1888
5fd86fcf
AK		 1889static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1890{
81231c69
AK		 1891 ulong cr0;
1892
5fd86fcf
AK		 1893 if (vcpu->fpu_active)
1894 return;
1895 vcpu->fpu_active = 1;
81231c69
AK		 1896 cr0 = vmcs_readl(GUEST_CR0);
1897 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1898 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1899 vmcs_writel(GUEST_CR0, cr0);
5fd86fcf 1900 update_exception_bitmap(vcpu);
edcafe3c 1901 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
36cf24e0
NHE		 1902 if (is_guest_mode(vcpu))
1903 vcpu->arch.cr0_guest_owned_bits &=
1904 ~get_vmcs12(vcpu)->cr0_guest_host_mask;
edcafe3c 1905 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
5fd86fcf
AK		 1906}
1907
edcafe3c
AK		 1908static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1909
fe3ef05c
NHE		 1910/*
1911 * Return the cr0 value that a nested guest would read. This is a combination
1912 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1913 * its hypervisor (cr0_read_shadow).
1914 */
1915static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1916{
1917 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1918 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1919}
1920static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1921{
1922 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1923 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1924}
1925
5fd86fcf
AK		 1926static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1927{
36cf24e0
NHE		 1928 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1929 * set this *before* calling this function.
1930 */
edcafe3c 1931 vmx_decache_cr0_guest_bits(vcpu);
81231c69 1932 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
5fd86fcf 1933 update_exception_bitmap(vcpu);
edcafe3c
AK		 1934 vcpu->arch.cr0_guest_owned_bits = 0;
1935 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
36cf24e0
NHE		 1936 if (is_guest_mode(vcpu)) {
1937 /*
1938 * L1's specified read shadow might not contain the TS bit,
1939 * so now that we turned on shadowing of this bit, we need to
1940 * set this bit of the shadow. Like in nested_vmx_run we need
1941 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1942 * up-to-date here because we just decached cr0.TS (and we'll
1943 * only update vmcs12->guest_cr0 on nested exit).
1944 */
1945 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1946 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1947 (vcpu->arch.cr0 & X86_CR0_TS);
1948 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1949 } else
1950 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf
AK		 1951}
1952
6aa8b732
AK		 1953static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1954{
78ac8b47 1955 unsigned long rflags, save_rflags;
345dcaa8 1956
6de12732
AK		 1957 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1958 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1959 rflags = vmcs_readl(GUEST_RFLAGS);
1960 if (to_vmx(vcpu)->rmode.vm86_active) {
1961 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1962 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1963 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1964 }
1965 to_vmx(vcpu)->rflags = rflags;
78ac8b47 1966 }
6de12732 1967 return to_vmx(vcpu)->rflags;
6aa8b732
AK		 1968}
1969
1970static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1971{
6de12732
AK		 1972 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1973 to_vmx(vcpu)->rflags = rflags;
78ac8b47
AK		 1974 if (to_vmx(vcpu)->rmode.vm86_active) {
1975 to_vmx(vcpu)->rmode.save_rflags = rflags;
053de044 1976 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 1977 }
6aa8b732
AK		 1978 vmcs_writel(GUEST_RFLAGS, rflags);
1979}
1980
37ccdcbe 1981static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2809f5d2
GC		 1982{
1983 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1984 int ret = 0;
1985
1986 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 1987 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 1988 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 1989 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2 1990
37ccdcbe 1991 return ret;
2809f5d2
GC		 1992}
1993
1994static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1995{
1996 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1997 u32 interruptibility = interruptibility_old;
1998
1999 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
2000
48005f64 2001 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 2002 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 2003 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC		 2004 interruptibility |= GUEST_INTR_STATE_STI;
2005
2006 if ((interruptibility != interruptibility_old))
2007 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
2008}
2009
6aa8b732
AK		 2010static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
2011{
2012 unsigned long rip;
6aa8b732 2013
5fdbf976 2014 rip = kvm_rip_read(vcpu);
6aa8b732 2015 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 2016 kvm_rip_write(vcpu, rip);
6aa8b732 2017
2809f5d2
GC		 2018 /* skipping an emulated instruction also counts */
2019 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 2020}
2021
0b6ac343
NHE		 2022/*
2023 * KVM wants to inject page-faults which it got to the guest. This function
2024 * checks whether in a nested guest, we need to inject them to L1 or L2.
0b6ac343 2025 */
e011c663 2026static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
0b6ac343
NHE		 2027{
2028 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2029
e011c663 2030 if (!(vmcs12->exception_bitmap & (1u << nr)))
0b6ac343
NHE		 2031 return 0;
2032
533558bc
JK		 2033 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
2034 vmcs_read32(VM_EXIT_INTR_INFO),
2035 vmcs_readl(EXIT_QUALIFICATION));
0b6ac343
NHE		 2036 return 1;
2037}
2038
298101da 2039static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 2040 bool has_error_code, u32 error_code,
2041 bool reinject)
298101da 2042{
77ab6db0 2043 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 2044 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 2045
e011c663
GN		 2046 if (!reinject && is_guest_mode(vcpu) &&
2047 nested_vmx_check_exception(vcpu, nr))
0b6ac343
NHE		 2048 return;
2049
8ab2d2e2 2050 if (has_error_code) {
77ab6db0 2051 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 2052 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2053 }
77ab6db0 2054
7ffd92c5 2055 if (vmx->rmode.vm86_active) {
71f9833b
SH		 2056 int inc_eip = 0;
2057 if (kvm_exception_is_soft(nr))
2058 inc_eip = vcpu->arch.event_exit_inst_len;
2059 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
a92601bb 2060 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
77ab6db0
JK		 2061 return;
2062 }
2063
66fd3f7f
GN		 2064 if (kvm_exception_is_soft(nr)) {
2065 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2066 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 2067 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2068 } else
2069 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2070
2071 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
298101da
AK		 2072}
2073
4e47c7a6
SY		 2074static bool vmx_rdtscp_supported(void)
2075{
2076 return cpu_has_vmx_rdtscp();
2077}
2078
ad756a16
MJ		 2079static bool vmx_invpcid_supported(void)
2080{
2081 return cpu_has_vmx_invpcid() && enable_ept;
2082}
2083
a75beee6
ED		 2084/*
2085 * Swap MSR entry in host/guest MSR entry array.
2086 */
8b9cf98c 2087static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 2088{
26bb0981 2089 struct shared_msr_entry tmp;
a2fa3e9f
GH		 2090
2091 tmp = vmx->guest_msrs[to];
2092 vmx->guest_msrs[to] = vmx->guest_msrs[from];
2093 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 2094}
2095
8d14695f
YZ		 2096static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2097{
2098 unsigned long *msr_bitmap;
2099
2100 if (irqchip_in_kernel(vcpu->kvm) && apic_x2apic_mode(vcpu->arch.apic)) {
2101 if (is_long_mode(vcpu))
2102 msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2103 else
2104 msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2105 } else {
2106 if (is_long_mode(vcpu))
2107 msr_bitmap = vmx_msr_bitmap_longmode;
2108 else
2109 msr_bitmap = vmx_msr_bitmap_legacy;
2110 }
2111
2112 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2113}
2114
e38aea3e
AK		 2115/*
2116 * Set up the vmcs to automatically save and restore system
2117 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
2118 * mode, as fiddling with msrs is very expensive.
2119 */
8b9cf98c 2120static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 2121{
26bb0981 2122 int save_nmsrs, index;
e38aea3e 2123
a75beee6
ED		 2124 save_nmsrs = 0;
2125#ifdef CONFIG_X86_64
8b9cf98c 2126 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 2127 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 2128 if (index >= 0)
8b9cf98c
RR		 2129 move_msr_up(vmx, index, save_nmsrs++);
2130 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 2131 if (index >= 0)
8b9cf98c
RR		 2132 move_msr_up(vmx, index, save_nmsrs++);
2133 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 2134 if (index >= 0)
8b9cf98c 2135 move_msr_up(vmx, index, save_nmsrs++);
4e47c7a6
SY		 2136 index = __find_msr_index(vmx, MSR_TSC_AUX);
2137 if (index >= 0 && vmx->rdtscp_enabled)
2138 move_msr_up(vmx, index, save_nmsrs++);
a75beee6 2139 /*
8c06585d 2140 * MSR_STAR is only needed on long mode guests, and only
a75beee6
ED		 2141 * if efer.sce is enabled.
2142 */
8c06585d 2143 index = __find_msr_index(vmx, MSR_STAR);
f6801dff 2144 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
8b9cf98c 2145 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 2146 }
2147#endif
92c0d900
AK		 2148 index = __find_msr_index(vmx, MSR_EFER);
2149 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 2150 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 2151
26bb0981 2152 vmx->save_nmsrs = save_nmsrs;
5897297b 2153
8d14695f
YZ		 2154 if (cpu_has_vmx_msr_bitmap())
2155 vmx_set_msr_bitmap(&vmx->vcpu);
e38aea3e
AK		 2156}
2157
6aa8b732
AK		 2158/*
2159 * reads and returns guest's timestamp counter "register"
2160 * guest_tsc = host_tsc + tsc_offset -- 21.3
2161 */
2162static u64 guest_read_tsc(void)
2163{
2164 u64 host_tsc, tsc_offset;
2165
2166 rdtscll(host_tsc);
2167 tsc_offset = vmcs_read64(TSC_OFFSET);
2168 return host_tsc + tsc_offset;
2169}
2170
d5c1785d
NHE		 2171/*
2172 * Like guest_read_tsc, but always returns L1's notion of the timestamp
2173 * counter, even if a nested guest (L2) is currently running.
2174 */
48d89b92 2175static u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
d5c1785d 2176{
886b470c 2177 u64 tsc_offset;
d5c1785d 2178
d5c1785d
NHE		 2179 tsc_offset = is_guest_mode(vcpu) ?
2180 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2181 vmcs_read64(TSC_OFFSET);
2182 return host_tsc + tsc_offset;
2183}
2184
4051b188 2185/*
cc578287
ZA		 2186 * Engage any workarounds for mis-matched TSC rates. Currently limited to
2187 * software catchup for faster rates on slower CPUs.
4051b188 2188 */
cc578287 2189static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
4051b188 2190{
cc578287
ZA		 2191 if (!scale)
2192 return;
2193
2194 if (user_tsc_khz > tsc_khz) {
2195 vcpu->arch.tsc_catchup = 1;
2196 vcpu->arch.tsc_always_catchup = 1;
2197 } else
2198 WARN(1, "user requested TSC rate below hardware speed\n");
4051b188
JR		 2199}
2200
ba904635
WA		 2201static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2202{
2203 return vmcs_read64(TSC_OFFSET);
2204}
2205
6aa8b732 2206/*
99e3e30a 2207 * writes 'offset' into guest's timestamp counter offset register
6aa8b732 2208 */
99e3e30a 2209static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
6aa8b732 2210{
27fc51b2 2211 if (is_guest_mode(vcpu)) {
7991825b 2212 /*
27fc51b2
NHE		 2213 * We're here if L1 chose not to trap WRMSR to TSC. According
2214 * to the spec, this should set L1's TSC; The offset that L1
2215 * set for L2 remains unchanged, and still needs to be added
2216 * to the newly set TSC to get L2's TSC.
7991825b 2217 */
27fc51b2
NHE		 2218 struct vmcs12 *vmcs12;
2219 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2220 /* recalculate vmcs02.TSC_OFFSET: */
2221 vmcs12 = get_vmcs12(vcpu);
2222 vmcs_write64(TSC_OFFSET, offset +
2223 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2224 vmcs12->tsc_offset : 0));
2225 } else {
489223ed
YY		 2226 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2227 vmcs_read64(TSC_OFFSET), offset);
27fc51b2
NHE		 2228 vmcs_write64(TSC_OFFSET, offset);
2229 }
6aa8b732
AK		 2230}
2231
f1e2b260 2232static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
e48672fa
ZA		 2233{
2234 u64 offset = vmcs_read64(TSC_OFFSET);
489223ed 2235
e48672fa 2236 vmcs_write64(TSC_OFFSET, offset + adjustment);
7991825b
NHE		 2237 if (is_guest_mode(vcpu)) {
2238 /* Even when running L2, the adjustment needs to apply to L1 */
2239 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
489223ed
YY		 2240 } else
2241 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2242 offset + adjustment);
e48672fa
ZA		 2243}
2244
857e4099
JR		 2245static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2246{
2247 return target_tsc - native_read_tsc();
2248}
2249
801d3424
NHE		 2250static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2251{
2252 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2253 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2254}
2255
2256/*
2257 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2258 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2259 * all guests if the "nested" module option is off, and can also be disabled
2260 * for a single guest by disabling its VMX cpuid bit.
2261 */
2262static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2263{
2264 return nested && guest_cpuid_has_vmx(vcpu);
2265}
2266
b87a51ae
NHE		 2267/*
2268 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2269 * returned for the various VMX controls MSRs when nested VMX is enabled.
2270 * The same values should also be used to verify that vmcs12 control fields are
2271 * valid during nested entry from L1 to L2.
2272 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2273 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2274 * bit in the high half is on if the corresponding bit in the control field
2275 * may be on. See also vmx_control_verify().
2276 * TODO: allow these variables to be modified (downgraded) by module options
2277 * or other means.
2278 */
2279static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
3dcdf3ec 2280static u32 nested_vmx_true_procbased_ctls_low;
b87a51ae
NHE		 2281static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
2282static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
2283static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
2996fca0 2284static u32 nested_vmx_true_exit_ctls_low;
b87a51ae 2285static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
2996fca0 2286static u32 nested_vmx_true_entry_ctls_low;
c18911a2 2287static u32 nested_vmx_misc_low, nested_vmx_misc_high;
bfd0a56b 2288static u32 nested_vmx_ept_caps;
b87a51ae
NHE		 2289static __init void nested_vmx_setup_ctls_msrs(void)
2290{
2291 /*
2292 * Note that as a general rule, the high half of the MSRs (bits in
2293 * the control fields which may be 1) should be initialized by the
2294 * intersection of the underlying hardware's MSR (i.e., features which
2295 * can be supported) and the list of features we want to expose -
2296 * because they are known to be properly supported in our code.
2297 * Also, usually, the low half of the MSRs (bits which must be 1) can
2298 * be set to 0, meaning that L1 may turn off any of these bits. The
2299 * reason is that if one of these bits is necessary, it will appear
2300 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2301 * fields of vmcs01 and vmcs02, will turn these bits off - and
2302 * nested_vmx_exit_handled() will not pass related exits to L1.
2303 * These rules have exceptions below.
2304 */
2305
2306 /* pin-based controls */
eabeaacc
JK		 2307 rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2308 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high);
eabeaacc
JK		 2309 nested_vmx_pinbased_ctls_low |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2310 nested_vmx_pinbased_ctls_high &= PIN_BASED_EXT_INTR_MASK |
f4124500
JK		 2311 PIN_BASED_NMI_EXITING | PIN_BASED_VIRTUAL_NMIS;
2312 nested_vmx_pinbased_ctls_high |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
0238ea91 2313 PIN_BASED_VMX_PREEMPTION_TIMER;
b87a51ae 2314
3dbcd8da 2315 /* exit controls */
c0dfee58
ACL		 2316 rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2317 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high);
33fb20c3 2318 nested_vmx_exit_ctls_low = VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
e0ba1a6f 2319
c0dfee58 2320 nested_vmx_exit_ctls_high &=
b87a51ae 2321#ifdef CONFIG_X86_64
c0dfee58 2322 VM_EXIT_HOST_ADDR_SPACE_SIZE |
b87a51ae 2323#endif
f4124500
JK		 2324 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
2325 nested_vmx_exit_ctls_high |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2326 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
e0ba1a6f
BD		 2327 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2328
36be0b9d
PB		 2329 if (vmx_mpx_supported())
2330 nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
b87a51ae 2331
2996fca0
JK		 2332 /* We support free control of debug control saving. */
2333 nested_vmx_true_exit_ctls_low = nested_vmx_exit_ctls_low &
2334 ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2335
b87a51ae
NHE		 2336 /* entry controls */
2337 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2338 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
33fb20c3 2339 nested_vmx_entry_ctls_low = VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae 2340 nested_vmx_entry_ctls_high &=
57435349
JK		 2341#ifdef CONFIG_X86_64
2342 VM_ENTRY_IA32E_MODE |
2343#endif
2344 VM_ENTRY_LOAD_IA32_PAT;
8049d651
NHE		 2345 nested_vmx_entry_ctls_high |= (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR |
2346 VM_ENTRY_LOAD_IA32_EFER);
36be0b9d
PB		 2347 if (vmx_mpx_supported())
2348 nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
57435349 2349
2996fca0
JK		 2350 /* We support free control of debug control loading. */
2351 nested_vmx_true_entry_ctls_low = nested_vmx_entry_ctls_low &
2352 ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
2353
b87a51ae
NHE		 2354 /* cpu-based controls */
2355 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2356 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
560b7ee1 2357 nested_vmx_procbased_ctls_low = CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae 2358 nested_vmx_procbased_ctls_high &=
a294c9bb
JK		 2359 CPU_BASED_VIRTUAL_INTR_PENDING |
2360 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
b87a51ae
NHE		 2361 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2362 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2363 CPU_BASED_CR3_STORE_EXITING |
2364#ifdef CONFIG_X86_64
2365 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2366#endif
2367 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2368 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
dbcb4e79 2369 CPU_BASED_RDPMC_EXITING | CPU_BASED_RDTSC_EXITING |
a7c0b07d 2370 CPU_BASED_PAUSE_EXITING | CPU_BASED_TPR_SHADOW |
b87a51ae
NHE		 2371 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2372 /*
2373 * We can allow some features even when not supported by the
2374 * hardware. For example, L1 can specify an MSR bitmap - and we
2375 * can use it to avoid exits to L1 - even when L0 runs L2
2376 * without MSR bitmaps.
2377 */
560b7ee1
JK		 2378 nested_vmx_procbased_ctls_high |= CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2379 CPU_BASED_USE_MSR_BITMAPS;
b87a51ae 2380
3dcdf3ec
JK		 2381 /* We support free control of CR3 access interception. */
2382 nested_vmx_true_procbased_ctls_low = nested_vmx_procbased_ctls_low &
2383 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
2384
b87a51ae
NHE		 2385 /* secondary cpu-based controls */
2386 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2387 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
2388 nested_vmx_secondary_ctls_low = 0;
2389 nested_vmx_secondary_ctls_high &=
d6851fbe 2390 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
92fbc7b1 2391 SECONDARY_EXEC_UNRESTRICTED_GUEST |
d6851fbe 2392 SECONDARY_EXEC_WBINVD_EXITING;
c18911a2 2393
afa61f75
NHE		 2394 if (enable_ept) {
2395 /* nested EPT: emulate EPT also to L1 */
2396 nested_vmx_secondary_ctls_high |= SECONDARY_EXEC_ENABLE_EPT;
ca72d970 2397 nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
d3134dbf
JK		 2398 VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT |
2399 VMX_EPT_INVEPT_BIT;
afa61f75
NHE		 2400 nested_vmx_ept_caps &= vmx_capability.ept;
2401 /*
4b855078
BD		 2402 * For nested guests, we don't do anything specific
2403 * for single context invalidation. Hence, only advertise
2404 * support for global context invalidation.
afa61f75 2405 */
4b855078 2406 nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT;
afa61f75
NHE		 2407 } else
2408 nested_vmx_ept_caps = 0;
2409
c18911a2
JK		 2410 /* miscellaneous data */
2411 rdmsr(MSR_IA32_VMX_MISC, nested_vmx_misc_low, nested_vmx_misc_high);
f4124500
JK		 2412 nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2413 nested_vmx_misc_low |= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
2414 VMX_MISC_ACTIVITY_HLT;
c18911a2 2415 nested_vmx_misc_high = 0;
b87a51ae
NHE		 2416}
2417
2418static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2419{
2420 /*
2421 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2422 */
2423 return ((control & high) | low) == control;
2424}
2425
2426static inline u64 vmx_control_msr(u32 low, u32 high)
2427{
2428 return low | ((u64)high << 32);
2429}
2430
cae50139 2431/* Returns 0 on success, non-0 otherwise. */
b87a51ae
NHE		 2432static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2433{
b87a51ae 2434 switch (msr_index) {
b87a51ae
NHE		 2435 case MSR_IA32_VMX_BASIC:
2436 /*
2437 * This MSR reports some information about VMX support. We
2438 * should return information about the VMX we emulate for the
2439 * guest, and the VMCS structure we give it - not about the
2440 * VMX support of the underlying hardware.
2441 */
3dbcd8da 2442 *pdata = VMCS12_REVISION | VMX_BASIC_TRUE_CTLS |
b87a51ae
NHE		 2443 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2444 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2445 break;
2446 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2447 case MSR_IA32_VMX_PINBASED_CTLS:
2448 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2449 nested_vmx_pinbased_ctls_high);
2450 break;
2451 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3dcdf3ec
JK		 2452 *pdata = vmx_control_msr(nested_vmx_true_procbased_ctls_low,
2453 nested_vmx_procbased_ctls_high);
2454 break;
b87a51ae
NHE		 2455 case MSR_IA32_VMX_PROCBASED_CTLS:
2456 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2457 nested_vmx_procbased_ctls_high);
2458 break;
2459 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2996fca0
JK		 2460 *pdata = vmx_control_msr(nested_vmx_true_exit_ctls_low,
2461 nested_vmx_exit_ctls_high);
2462 break;
b87a51ae
NHE		 2463 case MSR_IA32_VMX_EXIT_CTLS:
2464 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2465 nested_vmx_exit_ctls_high);
2466 break;
2467 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2996fca0
JK		 2468 *pdata = vmx_control_msr(nested_vmx_true_entry_ctls_low,
2469 nested_vmx_entry_ctls_high);
2470 break;
b87a51ae
NHE		 2471 case MSR_IA32_VMX_ENTRY_CTLS:
2472 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2473 nested_vmx_entry_ctls_high);
2474 break;
2475 case MSR_IA32_VMX_MISC:
c18911a2
JK		 2476 *pdata = vmx_control_msr(nested_vmx_misc_low,
2477 nested_vmx_misc_high);
b87a51ae
NHE		 2478 break;
2479 /*
2480 * These MSRs specify bits which the guest must keep fixed (on or off)
2481 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2482 * We picked the standard core2 setting.
2483 */
2484#define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2485#define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2486 case MSR_IA32_VMX_CR0_FIXED0:
2487 *pdata = VMXON_CR0_ALWAYSON;
2488 break;
2489 case MSR_IA32_VMX_CR0_FIXED1:
2490 *pdata = -1ULL;
2491 break;
2492 case MSR_IA32_VMX_CR4_FIXED0:
2493 *pdata = VMXON_CR4_ALWAYSON;
2494 break;
2495 case MSR_IA32_VMX_CR4_FIXED1:
2496 *pdata = -1ULL;
2497 break;
2498 case MSR_IA32_VMX_VMCS_ENUM:
5381417f 2499 *pdata = 0x2e; /* highest index: VMX_PREEMPTION_TIMER_VALUE */
b87a51ae
NHE		 2500 break;
2501 case MSR_IA32_VMX_PROCBASED_CTLS2:
2502 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2503 nested_vmx_secondary_ctls_high);
2504 break;
2505 case MSR_IA32_VMX_EPT_VPID_CAP:
afa61f75
NHE		 2506 /* Currently, no nested vpid support */
2507 *pdata = nested_vmx_ept_caps;
b87a51ae
NHE		 2508 break;
2509 default:
b87a51ae 2510 return 1;
b3897a49
NHE		 2511 }
2512
b87a51ae
NHE		 2513 return 0;
2514}
2515
6aa8b732
AK		 2516/*
2517 * Reads an msr value (of 'msr_index') into 'pdata'.
2518 * Returns 0 on success, non-0 otherwise.
2519 * Assumes vcpu_load() was already called.
2520 */
2521static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2522{
2523 u64 data;
26bb0981 2524 struct shared_msr_entry *msr;
6aa8b732
AK		 2525
2526 if (!pdata) {
2527 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2528 return -EINVAL;
2529 }
2530
2531 switch (msr_index) {
05b3e0c2 2532#ifdef CONFIG_X86_64
6aa8b732
AK		 2533 case MSR_FS_BASE:
2534 data = vmcs_readl(GUEST_FS_BASE);
2535 break;
2536 case MSR_GS_BASE:
2537 data = vmcs_readl(GUEST_GS_BASE);
2538 break;
44ea2b17
AK		 2539 case MSR_KERNEL_GS_BASE:
2540 vmx_load_host_state(to_vmx(vcpu));
2541 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2542 break;
26bb0981 2543#endif
6aa8b732 2544 case MSR_EFER:
3bab1f5d 2545 return kvm_get_msr_common(vcpu, msr_index, pdata);
af24a4e4 2546 case MSR_IA32_TSC:
6aa8b732
AK		 2547 data = guest_read_tsc();
2548 break;
2549 case MSR_IA32_SYSENTER_CS:
2550 data = vmcs_read32(GUEST_SYSENTER_CS);
2551 break;
2552 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2553 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 2554 break;
2555 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2556 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 2557 break;
0dd376e7 2558 case MSR_IA32_BNDCFGS:
93c4adc7
PB		 2559 if (!vmx_mpx_supported())
2560 return 1;
0dd376e7
LJ		 2561 data = vmcs_read64(GUEST_BNDCFGS);
2562 break;
cae50139
JK		 2563 case MSR_IA32_FEATURE_CONTROL:
2564 if (!nested_vmx_allowed(vcpu))
2565 return 1;
2566 data = to_vmx(vcpu)->nested.msr_ia32_feature_control;
2567 break;
2568 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2569 if (!nested_vmx_allowed(vcpu))
2570 return 1;
2571 return vmx_get_vmx_msr(vcpu, msr_index, pdata);
4e47c7a6
SY		 2572 case MSR_TSC_AUX:
2573 if (!to_vmx(vcpu)->rdtscp_enabled)
2574 return 1;
2575 /* Otherwise falls through */
6aa8b732 2576 default:
8b9cf98c 2577 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d
AK		 2578 if (msr) {
2579 data = msr->data;
2580 break;
6aa8b732 2581 }
3bab1f5d 2582 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 2583 }
2584
2585 *pdata = data;
2586 return 0;
2587}
2588
cae50139
JK		 2589static void vmx_leave_nested(struct kvm_vcpu *vcpu);
2590
6aa8b732
AK		 2591/*
2592 * Writes msr value into into the appropriate "register".
2593 * Returns 0 on success, non-0 otherwise.
2594 * Assumes vcpu_load() was already called.
2595 */
8fe8ab46 2596static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
6aa8b732 2597{
a2fa3e9f 2598 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 2599 struct shared_msr_entry *msr;
2cc51560 2600 int ret = 0;
8fe8ab46
WA		 2601 u32 msr_index = msr_info->index;
2602 u64 data = msr_info->data;
2cc51560 2603
6aa8b732 2604 switch (msr_index) {
3bab1f5d 2605 case MSR_EFER:
8fe8ab46 2606 ret = kvm_set_msr_common(vcpu, msr_info);
2cc51560 2607 break;
16175a79 2608#ifdef CONFIG_X86_64
6aa8b732 2609 case MSR_FS_BASE:
2fb92db1 2610 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2611 vmcs_writel(GUEST_FS_BASE, data);
2612 break;
2613 case MSR_GS_BASE:
2fb92db1 2614 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2615 vmcs_writel(GUEST_GS_BASE, data);
2616 break;
44ea2b17
AK		 2617 case MSR_KERNEL_GS_BASE:
2618 vmx_load_host_state(vmx);
2619 vmx->msr_guest_kernel_gs_base = data;
2620 break;
6aa8b732
AK		 2621#endif
2622 case MSR_IA32_SYSENTER_CS:
2623 vmcs_write32(GUEST_SYSENTER_CS, data);
2624 break;
2625 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2626 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 2627 break;
2628 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2629 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 2630 break;
0dd376e7 2631 case MSR_IA32_BNDCFGS:
93c4adc7
PB		 2632 if (!vmx_mpx_supported())
2633 return 1;
0dd376e7
LJ		 2634 vmcs_write64(GUEST_BNDCFGS, data);
2635 break;
af24a4e4 2636 case MSR_IA32_TSC:
8fe8ab46 2637 kvm_write_tsc(vcpu, msr_info);
6aa8b732 2638 break;
468d472f
SY		 2639 case MSR_IA32_CR_PAT:
2640 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
4566654b
NA		 2641 if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
2642 return 1;
468d472f
SY		 2643 vmcs_write64(GUEST_IA32_PAT, data);
2644 vcpu->arch.pat = data;
2645 break;
2646 }
8fe8ab46 2647 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 2648 break;
ba904635
WA		 2649 case MSR_IA32_TSC_ADJUST:
2650 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 2651 break;
cae50139
JK		 2652 case MSR_IA32_FEATURE_CONTROL:
2653 if (!nested_vmx_allowed(vcpu) ||
2654 (to_vmx(vcpu)->nested.msr_ia32_feature_control &
2655 FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
2656 return 1;
2657 vmx->nested.msr_ia32_feature_control = data;
2658 if (msr_info->host_initiated && data == 0)
2659 vmx_leave_nested(vcpu);
2660 break;
2661 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2662 return 1; /* they are read-only */
4e47c7a6
SY		 2663 case MSR_TSC_AUX:
2664 if (!vmx->rdtscp_enabled)
2665 return 1;
2666 /* Check reserved bit, higher 32 bits should be zero */
2667 if ((data >> 32) != 0)
2668 return 1;
2669 /* Otherwise falls through */
6aa8b732 2670 default:
8b9cf98c 2671 msr = find_msr_entry(vmx, msr_index);
3bab1f5d 2672 if (msr) {
8b3c3104 2673 u64 old_msr_data = msr->data;
3bab1f5d 2674 msr->data = data;
2225fd56
AK		 2675 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2676 preempt_disable();
8b3c3104
AH		 2677 ret = kvm_set_shared_msr(msr->index, msr->data,
2678 msr->mask);
2225fd56 2679 preempt_enable();
8b3c3104
AH		 2680 if (ret)
2681 msr->data = old_msr_data;
2225fd56 2682 }
3bab1f5d 2683 break;
6aa8b732 2684 }
8fe8ab46 2685 ret = kvm_set_msr_common(vcpu, msr_info);
6aa8b732
AK		 2686 }
2687
2cc51560 2688 return ret;
6aa8b732
AK		 2689}
2690
5fdbf976 2691static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 2692{
5fdbf976
MT		 2693 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2694 switch (reg) {
2695 case VCPU_REGS_RSP:
2696 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2697 break;
2698 case VCPU_REGS_RIP:
2699 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2700 break;
6de4f3ad
AK		 2701 case VCPU_EXREG_PDPTR:
2702 if (enable_ept)
2703 ept_save_pdptrs(vcpu);
2704 break;
5fdbf976
MT		 2705 default:
2706 break;
2707 }
6aa8b732
AK		 2708}
2709
6aa8b732
AK		 2710static __init int cpu_has_kvm_support(void)
2711{
6210e37b 2712 return cpu_has_vmx();
6aa8b732
AK		 2713}
2714
2715static __init int vmx_disabled_by_bios(void)
2716{
2717 u64 msr;
2718
2719 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
cafd6659 2720 if (msr & FEATURE_CONTROL_LOCKED) {
23f3e991 2721 /* launched w/ TXT and VMX disabled */
cafd6659
SW		 2722 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2723 && tboot_enabled())
2724 return 1;
23f3e991 2725 /* launched w/o TXT and VMX only enabled w/ TXT */
cafd6659 2726 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
23f3e991 2727 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
f9335afe
SW		 2728 && !tboot_enabled()) {
2729 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
23f3e991 2730 "activate TXT before enabling KVM\n");
cafd6659 2731 return 1;
f9335afe 2732 }
23f3e991
JC		 2733 /* launched w/o TXT and VMX disabled */
2734 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2735 && !tboot_enabled())
2736 return 1;
cafd6659
SW		 2737 }
2738
2739 return 0;
6aa8b732
AK		 2740}
2741
7725b894
DX		 2742static void kvm_cpu_vmxon(u64 addr)
2743{
2744 asm volatile (ASM_VMX_VMXON_RAX
2745 : : "a"(&addr), "m"(addr)
2746 : "memory", "cc");
2747}
2748
13a34e06 2749static int hardware_enable(void)
6aa8b732
AK		 2750{
2751 int cpu = raw_smp_processor_id();
2752 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
cafd6659 2753 u64 old, test_bits;
6aa8b732 2754
10474ae8
AG		 2755 if (read_cr4() & X86_CR4_VMXE)
2756 return -EBUSY;
2757
d462b819 2758 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76
ZY		 2759
2760 /*
2761 * Now we can enable the vmclear operation in kdump
2762 * since the loaded_vmcss_on_cpu list on this cpu
2763 * has been initialized.
2764 *
2765 * Though the cpu is not in VMX operation now, there
2766 * is no problem to enable the vmclear operation
2767 * for the loaded_vmcss_on_cpu list is empty!
2768 */
2769 crash_enable_local_vmclear(cpu);
2770
6aa8b732 2771 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
cafd6659
SW		 2772
2773 test_bits = FEATURE_CONTROL_LOCKED;
2774 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2775 if (tboot_enabled())
2776 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2777
2778 if ((old & test_bits) != test_bits) {
6aa8b732 2779 /* enable and lock */
cafd6659
SW		 2780 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2781 }
66aee91a 2782 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
10474ae8 2783
4610c9cc
DX		 2784 if (vmm_exclusive) {
2785 kvm_cpu_vmxon(phys_addr);
2786 ept_sync_global();
2787 }
10474ae8 2788
89cbc767 2789 native_store_gdt(this_cpu_ptr(&host_gdt));
3444d7da 2790
10474ae8 2791 return 0;
6aa8b732
AK		 2792}
2793
d462b819 2794static void vmclear_local_loaded_vmcss(void)
543e4243
AK		 2795{
2796 int cpu = raw_smp_processor_id();
d462b819 2797 struct loaded_vmcs *v, *n;
543e4243 2798
d462b819
NHE		 2799 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2800 loaded_vmcss_on_cpu_link)
2801 __loaded_vmcs_clear(v);
543e4243
AK		 2802}
2803
710ff4a8
EH		 2804
2805/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2806 * tricks.
2807 */
2808static void kvm_cpu_vmxoff(void)
6aa8b732 2809{
4ecac3fd 2810 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
6aa8b732
AK		 2811}
2812
13a34e06 2813static void hardware_disable(void)
710ff4a8 2814{
4610c9cc 2815 if (vmm_exclusive) {
d462b819 2816 vmclear_local_loaded_vmcss();
4610c9cc
DX		 2817 kvm_cpu_vmxoff();
2818 }
7725b894 2819 write_cr4(read_cr4() & ~X86_CR4_VMXE);
710ff4a8
EH		 2820}
2821
1c3d14fe 2822static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 2823 u32 msr, u32 *result)
1c3d14fe
YS		 2824{
2825 u32 vmx_msr_low, vmx_msr_high;
2826 u32 ctl = ctl_min | ctl_opt;
2827
2828 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2829
2830 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2831 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2832
2833 /* Ensure minimum (required) set of control bits are supported. */
2834 if (ctl_min & ~ctl)
002c7f7c 2835 return -EIO;
1c3d14fe
YS		 2836
2837 *result = ctl;
2838 return 0;
2839}
2840
110312c8
AK		 2841static __init bool allow_1_setting(u32 msr, u32 ctl)
2842{
2843 u32 vmx_msr_low, vmx_msr_high;
2844
2845 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2846 return vmx_msr_high & ctl;
2847}
2848
002c7f7c 2849static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 2850{
2851 u32 vmx_msr_low, vmx_msr_high;
d56f546d 2852 u32 min, opt, min2, opt2;
1c3d14fe
YS		 2853 u32 _pin_based_exec_control = 0;
2854 u32 _cpu_based_exec_control = 0;
f78e0e2e 2855 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 2856 u32 _vmexit_control = 0;
2857 u32 _vmentry_control = 0;
2858
10166744 2859 min = CPU_BASED_HLT_EXITING |
1c3d14fe
YS		 2860#ifdef CONFIG_X86_64
2861 CPU_BASED_CR8_LOAD_EXITING |
2862 CPU_BASED_CR8_STORE_EXITING |
2863#endif
d56f546d
SY		 2864 CPU_BASED_CR3_LOAD_EXITING |
2865 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 2866 CPU_BASED_USE_IO_BITMAPS |
2867 CPU_BASED_MOV_DR_EXITING |
a7052897 2868 CPU_BASED_USE_TSC_OFFSETING |
59708670
SY		 2869 CPU_BASED_MWAIT_EXITING |
2870 CPU_BASED_MONITOR_EXITING |
fee84b07
AK		 2871 CPU_BASED_INVLPG_EXITING |
2872 CPU_BASED_RDPMC_EXITING;
443381a8 2873
f78e0e2e 2874 opt = CPU_BASED_TPR_SHADOW |
25c5f225 2875 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 2876 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 2877 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2878 &_cpu_based_exec_control) < 0)
002c7f7c 2879 return -EIO;
6e5d865c
YS		 2880#ifdef CONFIG_X86_64
2881 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2882 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2883 ~CPU_BASED_CR8_STORE_EXITING;
2884#endif
f78e0e2e 2885 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 2886 min2 = 0;
2887 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
8d14695f 2888 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2384d2b3 2889 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 2890 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 2891 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 2892 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6 2893 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
ad756a16 2894 SECONDARY_EXEC_RDTSCP |
83d4c286 2895 SECONDARY_EXEC_ENABLE_INVPCID |
c7c9c56c 2896 SECONDARY_EXEC_APIC_REGISTER_VIRT |
abc4fc58
AG		 2897 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2898 SECONDARY_EXEC_SHADOW_VMCS;
d56f546d
SY		 2899 if (adjust_vmx_controls(min2, opt2,
2900 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 2901 &_cpu_based_2nd_exec_control) < 0)
2902 return -EIO;
2903 }
2904#ifndef CONFIG_X86_64
2905 if (!(_cpu_based_2nd_exec_control &
2906 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2907 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2908#endif
83d4c286
YZ		 2909
2910 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2911 _cpu_based_2nd_exec_control &= ~(
8d14695f 2912 SECONDARY_EXEC_APIC_REGISTER_VIRT |
c7c9c56c
YZ		 2913 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2914 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
83d4c286 2915
d56f546d 2916 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 2917 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2918 enabled */
5fff7d27
GN		 2919 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2920 CPU_BASED_CR3_STORE_EXITING |
2921 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 2922 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2923 vmx_capability.ept, vmx_capability.vpid);
2924 }
1c3d14fe 2925
81908bf4 2926 min = VM_EXIT_SAVE_DEBUG_CONTROLS;
1c3d14fe
YS		 2927#ifdef CONFIG_X86_64
2928 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2929#endif
a547c6db 2930 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
da8999d3 2931 VM_EXIT_ACK_INTR_ON_EXIT | VM_EXIT_CLEAR_BNDCFGS;
1c3d14fe
YS		 2932 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2933 &_vmexit_control) < 0)
002c7f7c 2934 return -EIO;
1c3d14fe 2935
01e439be
YZ		 2936 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2937 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
2938 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2939 &_pin_based_exec_control) < 0)
2940 return -EIO;
2941
2942 if (!(_cpu_based_2nd_exec_control &
2943 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
2944 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
2945 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
2946
c845f9c6 2947 min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
da8999d3 2948 opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
1c3d14fe
YS		 2949 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2950 &_vmentry_control) < 0)
002c7f7c 2951 return -EIO;
6aa8b732 2952
c68876fd 2953 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 2954
2955 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2956 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 2957 return -EIO;
1c3d14fe
YS		 2958
2959#ifdef CONFIG_X86_64
2960 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2961 if (vmx_msr_high & (1u<<16))
002c7f7c 2962 return -EIO;
1c3d14fe
YS		 2963#endif
2964
2965 /* Require Write-Back (WB) memory type for VMCS accesses. */
2966 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 2967 return -EIO;
1c3d14fe 2968
002c7f7c
YS		 2969 vmcs_conf->size = vmx_msr_high & 0x1fff;
2970 vmcs_conf->order = get_order(vmcs_config.size);
2971 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 2972
002c7f7c
YS		 2973 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2974 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 2975 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 2976 vmcs_conf->vmexit_ctrl = _vmexit_control;
2977 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe 2978
110312c8
AK		 2979 cpu_has_load_ia32_efer =
2980 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2981 VM_ENTRY_LOAD_IA32_EFER)
2982 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2983 VM_EXIT_LOAD_IA32_EFER);
2984
8bf00a52
GN		 2985 cpu_has_load_perf_global_ctrl =
2986 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2987 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
2988 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2989 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2990
2991 /*
2992 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2993 * but due to arrata below it can't be used. Workaround is to use
2994 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2995 *
2996 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2997 *
2998 * AAK155 (model 26)
2999 * AAP115 (model 30)
3000 * AAT100 (model 37)
3001 * BC86,AAY89,BD102 (model 44)
3002 * BA97 (model 46)
3003 *
3004 */
3005 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
3006 switch (boot_cpu_data.x86_model) {
3007 case 26:
3008 case 30:
3009 case 37:
3010 case 44:
3011 case 46:
3012 cpu_has_load_perf_global_ctrl = false;
3013 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3014 "does not work properly. Using workaround\n");
3015 break;
3016 default:
3017 break;
3018 }
3019 }
3020
1c3d14fe 3021 return 0;
c68876fd 3022}
6aa8b732
AK		 3023
3024static struct vmcs *alloc_vmcs_cpu(int cpu)
3025{
3026 int node = cpu_to_node(cpu);
3027 struct page *pages;
3028 struct vmcs *vmcs;
3029
6484eb3e 3030 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 3031 if (!pages)
3032 return NULL;
3033 vmcs = page_address(pages);
1c3d14fe
YS		 3034 memset(vmcs, 0, vmcs_config.size);
3035 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 3036 return vmcs;
3037}
3038
3039static struct vmcs *alloc_vmcs(void)
3040{
d3b2c338 3041 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 3042}
3043
3044static void free_vmcs(struct vmcs *vmcs)
3045{
1c3d14fe 3046 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 3047}
3048
d462b819
NHE		 3049/*
3050 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3051 */
3052static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3053{
3054 if (!loaded_vmcs->vmcs)
3055 return;
3056 loaded_vmcs_clear(loaded_vmcs);
3057 free_vmcs(loaded_vmcs->vmcs);
3058 loaded_vmcs->vmcs = NULL;
3059}
3060
39959588 3061static void free_kvm_area(void)
6aa8b732
AK		 3062{
3063 int cpu;
3064
3230bb47 3065 for_each_possible_cpu(cpu) {
6aa8b732 3066 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 3067 per_cpu(vmxarea, cpu) = NULL;
3068 }
6aa8b732
AK		 3069}
3070
fe2b201b
BD		 3071static void init_vmcs_shadow_fields(void)
3072{
3073 int i, j;
3074
3075 /* No checks for read only fields yet */
3076
3077 for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3078 switch (shadow_read_write_fields[i]) {
3079 case GUEST_BNDCFGS:
3080 if (!vmx_mpx_supported())
3081 continue;
3082 break;
3083 default:
3084 break;
3085 }
3086
3087 if (j < i)
3088 shadow_read_write_fields[j] =
3089 shadow_read_write_fields[i];
3090 j++;
3091 }
3092 max_shadow_read_write_fields = j;
3093
3094 /* shadowed fields guest access without vmexit */
3095 for (i = 0; i < max_shadow_read_write_fields; i++) {
3096 clear_bit(shadow_read_write_fields[i],
3097 vmx_vmwrite_bitmap);
3098 clear_bit(shadow_read_write_fields[i],
3099 vmx_vmread_bitmap);
3100 }
3101 for (i = 0; i < max_shadow_read_only_fields; i++)
3102 clear_bit(shadow_read_only_fields[i],
3103 vmx_vmread_bitmap);
3104}
3105
6aa8b732
AK		 3106static __init int alloc_kvm_area(void)
3107{
3108 int cpu;
3109
3230bb47 3110 for_each_possible_cpu(cpu) {
6aa8b732
AK		 3111 struct vmcs *vmcs;
3112
3113 vmcs = alloc_vmcs_cpu(cpu);
3114 if (!vmcs) {
3115 free_kvm_area();
3116 return -ENOMEM;
3117 }
3118
3119 per_cpu(vmxarea, cpu) = vmcs;
3120 }
3121 return 0;
3122}
3123
14168786
GN		 3124static bool emulation_required(struct kvm_vcpu *vcpu)
3125{
3126 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3127}
3128
91b0aa2c 3129static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
d99e4152 3130 struct kvm_segment *save)
6aa8b732 3131{
d99e4152
GN		 3132 if (!emulate_invalid_guest_state) {
3133 /*
3134 * CS and SS RPL should be equal during guest entry according
3135 * to VMX spec, but in reality it is not always so. Since vcpu
3136 * is in the middle of the transition from real mode to
3137 * protected mode it is safe to assume that RPL 0 is a good
3138 * default value.
3139 */
3140 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3141 save->selector &= ~SELECTOR_RPL_MASK;
3142 save->dpl = save->selector & SELECTOR_RPL_MASK;
3143 save->s = 1;
6aa8b732 3144 }
d99e4152 3145 vmx_set_segment(vcpu, save, seg);
6aa8b732
AK		 3146}
3147
3148static void enter_pmode(struct kvm_vcpu *vcpu)
3149{
3150 unsigned long flags;
a89a8fb9 3151 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3152
d99e4152
GN		 3153 /*
3154 * Update real mode segment cache. It may be not up-to-date if sement
3155 * register was written while vcpu was in a guest mode.
3156 */
3157 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3158 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3159 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3160 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3161 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3162 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3163
7ffd92c5 3164 vmx->rmode.vm86_active = 0;
6aa8b732 3165
2fb92db1
AK		 3166 vmx_segment_cache_clear(vmx);
3167
f5f7b2fe 3168 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
6aa8b732
AK		 3169
3170 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 3171 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3172 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK		 3173 vmcs_writel(GUEST_RFLAGS, flags);
3174
66aee91a
RR		 3175 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3176 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 3177
3178 update_exception_bitmap(vcpu);
3179
91b0aa2c
GN		 3180 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3181 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3182 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3183 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3184 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3185 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
6aa8b732
AK		 3186}
3187
f5f7b2fe 3188static void fix_rmode_seg(int seg, struct kvm_segment *save)
6aa8b732 3189{
772e0318 3190 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
d99e4152
GN		 3191 struct kvm_segment var = *save;
3192
3193 var.dpl = 0x3;
3194 if (seg == VCPU_SREG_CS)
3195 var.type = 0x3;
3196
3197 if (!emulate_invalid_guest_state) {
3198 var.selector = var.base >> 4;
3199 var.base = var.base & 0xffff0;
3200 var.limit = 0xffff;
3201 var.g = 0;
3202 var.db = 0;
3203 var.present = 1;
3204 var.s = 1;
3205 var.l = 0;
3206 var.unusable = 0;
3207 var.type = 0x3;
3208 var.avl = 0;
3209 if (save->base & 0xf)
3210 printk_once(KERN_WARNING "kvm: segment base is not "
3211 "paragraph aligned when entering "
3212 "protected mode (seg=%d)", seg);
3213 }
6aa8b732 3214
d99e4152
GN		 3215 vmcs_write16(sf->selector, var.selector);
3216 vmcs_write32(sf->base, var.base);
3217 vmcs_write32(sf->limit, var.limit);
3218 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
6aa8b732
AK		 3219}
3220
3221static void enter_rmode(struct kvm_vcpu *vcpu)
3222{
3223 unsigned long flags;
a89a8fb9 3224 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3225
f5f7b2fe
AK		 3226 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3227 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3228 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3229 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3230 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
c6ad1153
GN		 3231 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3232 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
f5f7b2fe 3233
7ffd92c5 3234 vmx->rmode.vm86_active = 1;
6aa8b732 3235
776e58ea
GN		 3236 /*
3237 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
4918c6ca 3238 * vcpu. Warn the user that an update is overdue.
776e58ea 3239 */
4918c6ca 3240 if (!vcpu->kvm->arch.tss_addr)
776e58ea
GN		 3241 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3242 "called before entering vcpu\n");
776e58ea 3243
2fb92db1
AK		 3244 vmx_segment_cache_clear(vmx);
3245
4918c6ca 3246 vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
6aa8b732 3247 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
6aa8b732
AK		 3248 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3249
3250 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 3251 vmx->rmode.save_rflags = flags;
6aa8b732 3252
053de044 3253 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 3254
3255 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 3256 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 3257 update_exception_bitmap(vcpu);
3258
d99e4152
GN		 3259 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3260 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3261 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3262 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3263 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3264 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
b246dd5d 3265
8668a3c4 3266 kvm_mmu_reset_context(vcpu);
6aa8b732
AK		 3267}
3268
401d10de
AS		 3269static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3270{
3271 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 3272 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3273
3274 if (!msr)
3275 return;
401d10de 3276
44ea2b17
AK		 3277 /*
3278 * Force kernel_gs_base reloading before EFER changes, as control
3279 * of this msr depends on is_long_mode().
3280 */
3281 vmx_load_host_state(to_vmx(vcpu));
f6801dff 3282 vcpu->arch.efer = efer;
401d10de 3283 if (efer & EFER_LMA) {
2961e876 3284 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
401d10de
AS		 3285 msr->data = efer;
3286 } else {
2961e876 3287 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
401d10de
AS		 3288
3289 msr->data = efer & ~EFER_LME;
3290 }
3291 setup_msrs(vmx);
3292}
3293
05b3e0c2 3294#ifdef CONFIG_X86_64
6aa8b732
AK		 3295
3296static void enter_lmode(struct kvm_vcpu *vcpu)
3297{
3298 u32 guest_tr_ar;
3299
2fb92db1
AK		 3300 vmx_segment_cache_clear(to_vmx(vcpu));
3301
6aa8b732
AK		 3302 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3303 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
bd80158a
JK		 3304 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3305 __func__);
6aa8b732
AK		 3306 vmcs_write32(GUEST_TR_AR_BYTES,
3307 (guest_tr_ar & ~AR_TYPE_MASK)
3308 | AR_TYPE_BUSY_64_TSS);
3309 }
da38f438 3310 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
6aa8b732
AK		 3311}
3312
3313static void exit_lmode(struct kvm_vcpu *vcpu)
3314{
2961e876 3315 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
da38f438 3316 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
6aa8b732
AK		 3317}
3318
3319#endif
3320
2384d2b3
SY		 3321static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3322{
b9d762fa 3323 vpid_sync_context(to_vmx(vcpu));
dd180b3e
XG		 3324 if (enable_ept) {
3325 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3326 return;
4e1096d2 3327 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
dd180b3e 3328 }
2384d2b3
SY		 3329}
3330
e8467fda
AK		 3331static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3332{
3333 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3334
3335 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3336 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3337}
3338
aff48baa
AK		 3339static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3340{
3341 if (enable_ept && is_paging(vcpu))
3342 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3343 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3344}
3345
25c4c276 3346static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 3347{
fc78f519
AK		 3348 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3349
3350 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3351 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 3352}
3353
1439442c
SY		 3354static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3355{
d0d538b9
GN		 3356 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3357
6de4f3ad
AK		 3358 if (!test_bit(VCPU_EXREG_PDPTR,
3359 (unsigned long *)&vcpu->arch.regs_dirty))
3360 return;
3361
1439442c 3362 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
d0d538b9
GN		 3363 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
3364 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
3365 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
3366 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
1439442c
SY		 3367 }
3368}
3369
8f5d549f
AK		 3370static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3371{
d0d538b9
GN		 3372 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3373
8f5d549f 3374 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
d0d538b9
GN		 3375 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3376 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3377 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3378 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
8f5d549f 3379 }
6de4f3ad
AK		 3380
3381 __set_bit(VCPU_EXREG_PDPTR,
3382 (unsigned long *)&vcpu->arch.regs_avail);
3383 __set_bit(VCPU_EXREG_PDPTR,
3384 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 3385}
3386
5e1746d6 3387static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1439442c
SY		 3388
3389static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3390 unsigned long cr0,
3391 struct kvm_vcpu *vcpu)
3392{
5233dd51
MT		 3393 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3394 vmx_decache_cr3(vcpu);
1439442c
SY		 3395 if (!(cr0 & X86_CR0_PG)) {
3396 /* From paging/starting to nonpaging */
3397 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3398 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 3399 (CPU_BASED_CR3_LOAD_EXITING |
3400 CPU_BASED_CR3_STORE_EXITING));
3401 vcpu->arch.cr0 = cr0;
fc78f519 3402 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 3403 } else if (!is_paging(vcpu)) {
3404 /* From nonpaging to paging */
3405 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3406 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 3407 ~(CPU_BASED_CR3_LOAD_EXITING |
3408 CPU_BASED_CR3_STORE_EXITING));
3409 vcpu->arch.cr0 = cr0;
fc78f519 3410 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 3411 }
95eb84a7
SY		 3412
3413 if (!(cr0 & X86_CR0_WP))
3414 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 3415}
3416
6aa8b732
AK		 3417static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3418{
7ffd92c5 3419 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 3420 unsigned long hw_cr0;
3421
5037878e 3422 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3a624e29 3423 if (enable_unrestricted_guest)
5037878e 3424 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
218e763f 3425 else {
5037878e 3426 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
1439442c 3427
218e763f
GN		 3428 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3429 enter_pmode(vcpu);
6aa8b732 3430
218e763f
GN		 3431 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3432 enter_rmode(vcpu);
3433 }
6aa8b732 3434
05b3e0c2 3435#ifdef CONFIG_X86_64
f6801dff 3436 if (vcpu->arch.efer & EFER_LME) {
707d92fa 3437 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 3438 enter_lmode(vcpu);
707d92fa 3439 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 3440 exit_lmode(vcpu);
3441 }
3442#endif
3443
089d034e 3444 if (enable_ept)
1439442c
SY		 3445 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3446
02daab21 3447 if (!vcpu->fpu_active)
81231c69 3448 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
02daab21 3449
6aa8b732 3450 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 3451 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 3452 vcpu->arch.cr0 = cr0;
14168786
GN		 3453
3454 /* depends on vcpu->arch.cr0 to be set to a new value */
3455 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 3456}
3457
1439442c
SY		 3458static u64 construct_eptp(unsigned long root_hpa)
3459{
3460 u64 eptp;
3461
3462 /* TODO write the value reading from MSR */
3463 eptp = VMX_EPT_DEFAULT_MT |
3464 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
b38f9934
XH		 3465 if (enable_ept_ad_bits)
3466 eptp |= VMX_EPT_AD_ENABLE_BIT;
1439442c
SY		 3467 eptp |= (root_hpa & PAGE_MASK);
3468
3469 return eptp;
3470}
3471
6aa8b732
AK		 3472static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3473{
1439442c
SY		 3474 unsigned long guest_cr3;
3475 u64 eptp;
3476
3477 guest_cr3 = cr3;
089d034e 3478 if (enable_ept) {
1439442c
SY		 3479 eptp = construct_eptp(cr3);
3480 vmcs_write64(EPT_POINTER, eptp);
59ab5a8f
JK		 3481 if (is_paging(vcpu) || is_guest_mode(vcpu))
3482 guest_cr3 = kvm_read_cr3(vcpu);
3483 else
3484 guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 3485 ept_load_pdptrs(vcpu);
1439442c
SY		 3486 }
3487
2384d2b3 3488 vmx_flush_tlb(vcpu);
1439442c 3489 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK		 3490}
3491
5e1746d6 3492static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
6aa8b732 3493{
7ffd92c5 3494 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1439442c
SY		 3495 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3496
5e1746d6
NHE		 3497 if (cr4 & X86_CR4_VMXE) {
3498 /*
3499 * To use VMXON (and later other VMX instructions), a guest
3500 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3501 * So basically the check on whether to allow nested VMX
3502 * is here.
3503 */
3504 if (!nested_vmx_allowed(vcpu))
3505 return 1;
1a0d74e6
JK		 3506 }
3507 if (to_vmx(vcpu)->nested.vmxon &&
3508 ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
5e1746d6
NHE		 3509 return 1;
3510
ad312c7c 3511 vcpu->arch.cr4 = cr4;
bc23008b
AK		 3512 if (enable_ept) {
3513 if (!is_paging(vcpu)) {
3514 hw_cr4 &= ~X86_CR4_PAE;
3515 hw_cr4 |= X86_CR4_PSE;
c08800a5 3516 /*
e1e746b3
FW		 3517 * SMEP/SMAP is disabled if CPU is in non-paging mode
3518 * in hardware. However KVM always uses paging mode to
c08800a5 3519 * emulate guest non-paging mode with TDP.
e1e746b3
FW		 3520 * To emulate this behavior, SMEP/SMAP needs to be
3521 * manually disabled when guest switches to non-paging
3522 * mode.
c08800a5 3523 */
e1e746b3 3524 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP);
bc23008b
AK		 3525 } else if (!(cr4 & X86_CR4_PAE)) {
3526 hw_cr4 &= ~X86_CR4_PAE;
3527 }
3528 }
1439442c
SY		 3529
3530 vmcs_writel(CR4_READ_SHADOW, cr4);
3531 vmcs_writel(GUEST_CR4, hw_cr4);
5e1746d6 3532 return 0;
6aa8b732
AK		 3533}
3534
6aa8b732
AK		 3535static void vmx_get_segment(struct kvm_vcpu *vcpu,
3536 struct kvm_segment *var, int seg)
3537{
a9179499 3538 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732
AK		 3539 u32 ar;
3540
c6ad1153 3541 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
f5f7b2fe 3542 *var = vmx->rmode.segs[seg];
a9179499 3543 if (seg == VCPU_SREG_TR
2fb92db1 3544 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
f5f7b2fe 3545 return;
1390a28b
AK		 3546 var->base = vmx_read_guest_seg_base(vmx, seg);
3547 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3548 return;
a9179499 3549 }
2fb92db1
AK		 3550 var->base = vmx_read_guest_seg_base(vmx, seg);
3551 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3552 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3553 ar = vmx_read_guest_seg_ar(vmx, seg);
03617c18 3554 var->unusable = (ar >> 16) & 1;
6aa8b732
AK		 3555 var->type = ar & 15;
3556 var->s = (ar >> 4) & 1;
3557 var->dpl = (ar >> 5) & 3;
03617c18
GN		 3558 /*
3559 * Some userspaces do not preserve unusable property. Since usable
3560 * segment has to be present according to VMX spec we can use present
3561 * property to amend userspace bug by making unusable segment always
3562 * nonpresent. vmx_segment_access_rights() already marks nonpresent
3563 * segment as unusable.
3564 */
3565 var->present = !var->unusable;
6aa8b732
AK		 3566 var->avl = (ar >> 12) & 1;
3567 var->l = (ar >> 13) & 1;
3568 var->db = (ar >> 14) & 1;
3569 var->g = (ar >> 15) & 1;
6aa8b732
AK		 3570}
3571
a9179499
AK		 3572static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3573{
a9179499
AK		 3574 struct kvm_segment s;
3575
3576 if (to_vmx(vcpu)->rmode.vm86_active) {
3577 vmx_get_segment(vcpu, &s, seg);
3578 return s.base;
3579 }
2fb92db1 3580 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
a9179499
AK		 3581}
3582
b09408d0 3583static int vmx_get_cpl(struct kvm_vcpu *vcpu)
2e4d2653 3584{
b09408d0
MT		 3585 struct vcpu_vmx *vmx = to_vmx(vcpu);
3586
ae9fedc7 3587 if (unlikely(vmx->rmode.vm86_active))
2e4d2653 3588 return 0;
ae9fedc7
PB		 3589 else {
3590 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
3591 return AR_DPL(ar);
69c73028 3592 }
69c73028
AK		 3593}
3594
653e3108 3595static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 3596{
6aa8b732
AK		 3597 u32 ar;
3598
f0495f9b 3599 if (var->unusable || !var->present)
6aa8b732
AK		 3600 ar = 1 << 16;
3601 else {
3602 ar = var->type & 15;
3603 ar |= (var->s & 1) << 4;
3604 ar |= (var->dpl & 3) << 5;
3605 ar |= (var->present & 1) << 7;
3606 ar |= (var->avl & 1) << 12;
3607 ar |= (var->l & 1) << 13;
3608 ar |= (var->db & 1) << 14;
3609 ar |= (var->g & 1) << 15;
3610 }
653e3108
AK		 3611
3612 return ar;
3613}
3614
3615static void vmx_set_segment(struct kvm_vcpu *vcpu,
3616 struct kvm_segment *var, int seg)
3617{
7ffd92c5 3618 struct vcpu_vmx *vmx = to_vmx(vcpu);
772e0318 3619 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
653e3108 3620
2fb92db1
AK		 3621 vmx_segment_cache_clear(vmx);
3622
1ecd50a9
GN		 3623 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3624 vmx->rmode.segs[seg] = *var;
3625 if (seg == VCPU_SREG_TR)
3626 vmcs_write16(sf->selector, var->selector);
3627 else if (var->s)
3628 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
d99e4152 3629 goto out;
653e3108 3630 }
1ecd50a9 3631
653e3108
AK		 3632 vmcs_writel(sf->base, var->base);
3633 vmcs_write32(sf->limit, var->limit);
3634 vmcs_write16(sf->selector, var->selector);
3a624e29
NK		 3635
3636 /*
3637 * Fix the "Accessed" bit in AR field of segment registers for older
3638 * qemu binaries.
3639 * IA32 arch specifies that at the time of processor reset the
3640 * "Accessed" bit in the AR field of segment registers is 1. And qemu
0fa06071 3641 * is setting it to 0 in the userland code. This causes invalid guest
3a624e29
NK		 3642 * state vmexit when "unrestricted guest" mode is turned on.
3643 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3644 * tree. Newer qemu binaries with that qemu fix would not need this
3645 * kvm hack.
3646 */
3647 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
f924d66d 3648 var->type |= 0x1; /* Accessed */
3a624e29 3649
f924d66d 3650 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
d99e4152
GN		 3651
3652out:
98eb2f8b 3653 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 3654}
3655
6aa8b732
AK		 3656static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3657{
2fb92db1 3658 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
6aa8b732
AK		 3659
3660 *db = (ar >> 14) & 1;
3661 *l = (ar >> 13) & 1;
3662}
3663
89a27f4d 3664static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3665{
89a27f4d
GN		 3666 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3667 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK		 3668}
3669
89a27f4d 3670static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3671{
89a27f4d
GN		 3672 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3673 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK		 3674}
3675
89a27f4d 3676static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3677{
89a27f4d
GN		 3678 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3679 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK		 3680}
3681
89a27f4d 3682static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3683{
89a27f4d
GN		 3684 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3685 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK		 3686}
3687
648dfaa7
MG		 3688static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3689{
3690 struct kvm_segment var;
3691 u32 ar;
3692
3693 vmx_get_segment(vcpu, &var, seg);
07f42f5f 3694 var.dpl = 0x3;
0647f4aa
GN		 3695 if (seg == VCPU_SREG_CS)
3696 var.type = 0x3;
648dfaa7
MG		 3697 ar = vmx_segment_access_rights(&var);
3698
3699 if (var.base != (var.selector << 4))
3700 return false;
89efbed0 3701 if (var.limit != 0xffff)
648dfaa7 3702 return false;
07f42f5f 3703 if (ar != 0xf3)
648dfaa7
MG		 3704 return false;
3705
3706 return true;
3707}
3708
3709static bool code_segment_valid(struct kvm_vcpu *vcpu)
3710{
3711 struct kvm_segment cs;
3712 unsigned int cs_rpl;
3713
3714 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3715 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3716
1872a3f4
AK		 3717 if (cs.unusable)
3718 return false;
648dfaa7
MG		 3719 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3720 return false;
3721 if (!cs.s)
3722 return false;
1872a3f4 3723 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 3724 if (cs.dpl > cs_rpl)
3725 return false;
1872a3f4 3726 } else {
648dfaa7
MG		 3727 if (cs.dpl != cs_rpl)
3728 return false;
3729 }
3730 if (!cs.present)
3731 return false;
3732
3733 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3734 return true;
3735}
3736
3737static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3738{
3739 struct kvm_segment ss;
3740 unsigned int ss_rpl;
3741
3742 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3743 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3744
1872a3f4
AK		 3745 if (ss.unusable)
3746 return true;
3747 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 3748 return false;
3749 if (!ss.s)
3750 return false;
3751 if (ss.dpl != ss_rpl) /* DPL != RPL */
3752 return false;
3753 if (!ss.present)
3754 return false;
3755
3756 return true;
3757}
3758
3759static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3760{
3761 struct kvm_segment var;
3762 unsigned int rpl;
3763
3764 vmx_get_segment(vcpu, &var, seg);
3765 rpl = var.selector & SELECTOR_RPL_MASK;
3766
1872a3f4
AK		 3767 if (var.unusable)
3768 return true;
648dfaa7
MG		 3769 if (!var.s)
3770 return false;
3771 if (!var.present)
3772 return false;
3773 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3774 if (var.dpl < rpl) /* DPL < RPL */
3775 return false;
3776 }
3777
3778 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3779 * rights flags
3780 */
3781 return true;
3782}
3783
3784static bool tr_valid(struct kvm_vcpu *vcpu)
3785{
3786 struct kvm_segment tr;
3787
3788 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3789
1872a3f4
AK		 3790 if (tr.unusable)
3791 return false;
648dfaa7
MG		 3792 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3793 return false;
1872a3f4 3794 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 3795 return false;
3796 if (!tr.present)
3797 return false;
3798
3799 return true;
3800}
3801
3802static bool ldtr_valid(struct kvm_vcpu *vcpu)
3803{
3804 struct kvm_segment ldtr;
3805
3806 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3807
1872a3f4
AK		 3808 if (ldtr.unusable)
3809 return true;
648dfaa7
MG		 3810 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3811 return false;
3812 if (ldtr.type != 2)
3813 return false;
3814 if (!ldtr.present)
3815 return false;
3816
3817 return true;
3818}
3819
3820static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3821{
3822 struct kvm_segment cs, ss;
3823
3824 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3825 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3826
3827 return ((cs.selector & SELECTOR_RPL_MASK) ==
3828 (ss.selector & SELECTOR_RPL_MASK));
3829}
3830
3831/*
3832 * Check if guest state is valid. Returns true if valid, false if
3833 * not.
3834 * We assume that registers are always usable
3835 */
3836static bool guest_state_valid(struct kvm_vcpu *vcpu)
3837{
c5e97c80
GN		 3838 if (enable_unrestricted_guest)
3839 return true;
3840
648dfaa7 3841 /* real mode guest state checks */
f13882d8 3842 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
648dfaa7
MG		 3843 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3844 return false;
3845 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3846 return false;
3847 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3848 return false;
3849 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3850 return false;
3851 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3852 return false;
3853 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3854 return false;
3855 } else {
3856 /* protected mode guest state checks */
3857 if (!cs_ss_rpl_check(vcpu))
3858 return false;
3859 if (!code_segment_valid(vcpu))
3860 return false;
3861 if (!stack_segment_valid(vcpu))
3862 return false;
3863 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3864 return false;
3865 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3866 return false;
3867 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3868 return false;
3869 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3870 return false;
3871 if (!tr_valid(vcpu))
3872 return false;
3873 if (!ldtr_valid(vcpu))
3874 return false;
3875 }
3876 /* TODO:
3877 * - Add checks on RIP
3878 * - Add checks on RFLAGS
3879 */
3880
3881 return true;
3882}
3883
d77c26fc 3884static int init_rmode_tss(struct kvm *kvm)
6aa8b732 3885{
40dcaa9f 3886 gfn_t fn;
195aefde 3887 u16 data = 0;
1f755a82 3888 int idx, r;
6aa8b732 3889
40dcaa9f 3890 idx = srcu_read_lock(&kvm->srcu);
4918c6ca 3891 fn = kvm->arch.tss_addr >> PAGE_SHIFT;
195aefde
IE		 3892 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3893 if (r < 0)
10589a46 3894 goto out;
195aefde 3895 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 3896 r = kvm_write_guest_page(kvm, fn++, &data,
3897 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 3898 if (r < 0)
10589a46 3899 goto out;
195aefde
IE		 3900 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3901 if (r < 0)
10589a46 3902 goto out;
195aefde
IE		 3903 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3904 if (r < 0)
10589a46 3905 goto out;
195aefde 3906 data = ~0;
10589a46
MT		 3907 r = kvm_write_guest_page(kvm, fn, &data,
3908 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3909 sizeof(u8));
10589a46 3910out:
40dcaa9f 3911 srcu_read_unlock(&kvm->srcu, idx);
1f755a82 3912 return r;
6aa8b732
AK		 3913}
3914
b7ebfb05
SY		 3915static int init_rmode_identity_map(struct kvm *kvm)
3916{
f51770ed 3917 int i, idx, r = 0;
b7ebfb05
SY		 3918 pfn_t identity_map_pfn;
3919 u32 tmp;
3920
089d034e 3921 if (!enable_ept)
f51770ed 3922 return 0;
a255d479
TC		 3923
3924 /* Protect kvm->arch.ept_identity_pagetable_done. */
3925 mutex_lock(&kvm->slots_lock);
3926
f51770ed 3927 if (likely(kvm->arch.ept_identity_pagetable_done))
a255d479 3928 goto out2;
a255d479 3929
b927a3ce 3930 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
a255d479
TC		 3931
3932 r = alloc_identity_pagetable(kvm);
f51770ed 3933 if (r < 0)
a255d479
TC		 3934 goto out2;
3935
40dcaa9f 3936 idx = srcu_read_lock(&kvm->srcu);
b7ebfb05
SY		 3937 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3938 if (r < 0)
3939 goto out;
3940 /* Set up identity-mapping pagetable for EPT in real mode */
3941 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3942 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3943 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3944 r = kvm_write_guest_page(kvm, identity_map_pfn,
3945 &tmp, i * sizeof(tmp), sizeof(tmp));
3946 if (r < 0)
3947 goto out;
3948 }
3949 kvm->arch.ept_identity_pagetable_done = true;
f51770ed 3950
b7ebfb05 3951out:
40dcaa9f 3952 srcu_read_unlock(&kvm->srcu, idx);
a255d479
TC		 3953
3954out2:
3955 mutex_unlock(&kvm->slots_lock);
f51770ed 3956 return r;
b7ebfb05
SY		 3957}
3958
6aa8b732
AK		 3959static void seg_setup(int seg)
3960{
772e0318 3961 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 3962 unsigned int ar;
6aa8b732
AK		 3963
3964 vmcs_write16(sf->selector, 0);
3965 vmcs_writel(sf->base, 0);
3966 vmcs_write32(sf->limit, 0xffff);
d54d07b2
GN		 3967 ar = 0x93;
3968 if (seg == VCPU_SREG_CS)
3969 ar |= 0x08; /* code segment */
3a624e29
NK		 3970
3971 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 3972}
3973
f78e0e2e
SY		 3974static int alloc_apic_access_page(struct kvm *kvm)
3975{
4484141a 3976 struct page *page;
f78e0e2e
SY		 3977 struct kvm_userspace_memory_region kvm_userspace_mem;
3978 int r = 0;
3979
79fac95e 3980 mutex_lock(&kvm->slots_lock);
c24ae0dc 3981 if (kvm->arch.apic_access_page_done)
f78e0e2e
SY		 3982 goto out;
3983 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3984 kvm_userspace_mem.flags = 0;
73a6d941 3985 kvm_userspace_mem.guest_phys_addr = APIC_DEFAULT_PHYS_BASE;
f78e0e2e 3986 kvm_userspace_mem.memory_size = PAGE_SIZE;
47ae31e2 3987 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
f78e0e2e
SY		 3988 if (r)
3989 goto out;
72dc67a6 3990
73a6d941 3991 page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
4484141a
XG		 3992 if (is_error_page(page)) {
3993 r = -EFAULT;
3994 goto out;
3995 }
3996
c24ae0dc
TC		 3997 /*
3998 * Do not pin the page in memory, so that memory hot-unplug
3999 * is able to migrate it.
4000 */
4001 put_page(page);
4002 kvm->arch.apic_access_page_done = true;
f78e0e2e 4003out:
79fac95e 4004 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY		 4005 return r;
4006}
4007
b7ebfb05
SY		 4008static int alloc_identity_pagetable(struct kvm *kvm)
4009{
a255d479
TC		 4010 /* Called with kvm->slots_lock held. */
4011
b7ebfb05
SY		 4012 struct kvm_userspace_memory_region kvm_userspace_mem;
4013 int r = 0;
4014
a255d479
TC		 4015 BUG_ON(kvm->arch.ept_identity_pagetable_done);
4016
b7ebfb05
SY		 4017 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
4018 kvm_userspace_mem.flags = 0;
b927a3ce
SY		 4019 kvm_userspace_mem.guest_phys_addr =
4020 kvm->arch.ept_identity_map_addr;
b7ebfb05 4021 kvm_userspace_mem.memory_size = PAGE_SIZE;
47ae31e2 4022 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
b7ebfb05 4023
b7ebfb05
SY		 4024 return r;
4025}
4026
2384d2b3
SY		 4027static void allocate_vpid(struct vcpu_vmx *vmx)
4028{
4029 int vpid;
4030
4031 vmx->vpid = 0;
919818ab 4032 if (!enable_vpid)
2384d2b3
SY		 4033 return;
4034 spin_lock(&vmx_vpid_lock);
4035 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4036 if (vpid < VMX_NR_VPIDS) {
4037 vmx->vpid = vpid;
4038 __set_bit(vpid, vmx_vpid_bitmap);
4039 }
4040 spin_unlock(&vmx_vpid_lock);
4041}
4042
cdbecfc3
LJ		 4043static void free_vpid(struct vcpu_vmx *vmx)
4044{
4045 if (!enable_vpid)
4046 return;
4047 spin_lock(&vmx_vpid_lock);
4048 if (vmx->vpid != 0)
4049 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
4050 spin_unlock(&vmx_vpid_lock);
4051}
4052
8d14695f
YZ		 4053#define MSR_TYPE_R 1
4054#define MSR_TYPE_W 2
4055static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4056 u32 msr, int type)
25c5f225 4057{
3e7c73e9 4058 int f = sizeof(unsigned long);
25c5f225
SY		 4059
4060 if (!cpu_has_vmx_msr_bitmap())
4061 return;
4062
4063 /*
4064 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4065 * have the write-low and read-high bitmap offsets the wrong way round.
4066 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4067 */
25c5f225 4068 if (msr <= 0x1fff) {
8d14695f
YZ		 4069 if (type & MSR_TYPE_R)
4070 /* read-low */
4071 __clear_bit(msr, msr_bitmap + 0x000 / f);
4072
4073 if (type & MSR_TYPE_W)
4074 /* write-low */
4075 __clear_bit(msr, msr_bitmap + 0x800 / f);
4076
25c5f225
SY		 4077 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4078 msr &= 0x1fff;
8d14695f
YZ		 4079 if (type & MSR_TYPE_R)
4080 /* read-high */
4081 __clear_bit(msr, msr_bitmap + 0x400 / f);
4082
4083 if (type & MSR_TYPE_W)
4084 /* write-high */
4085 __clear_bit(msr, msr_bitmap + 0xc00 / f);
4086
4087 }
4088}
4089
4090static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
4091 u32 msr, int type)
4092{
4093 int f = sizeof(unsigned long);
4094
4095 if (!cpu_has_vmx_msr_bitmap())
4096 return;
4097
4098 /*
4099 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4100 * have the write-low and read-high bitmap offsets the wrong way round.
4101 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4102 */
4103 if (msr <= 0x1fff) {
4104 if (type & MSR_TYPE_R)
4105 /* read-low */
4106 __set_bit(msr, msr_bitmap + 0x000 / f);
4107
4108 if (type & MSR_TYPE_W)
4109 /* write-low */
4110 __set_bit(msr, msr_bitmap + 0x800 / f);
4111
4112 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4113 msr &= 0x1fff;
4114 if (type & MSR_TYPE_R)
4115 /* read-high */
4116 __set_bit(msr, msr_bitmap + 0x400 / f);
4117
4118 if (type & MSR_TYPE_W)
4119 /* write-high */
4120 __set_bit(msr, msr_bitmap + 0xc00 / f);
4121
25c5f225 4122 }
25c5f225
SY		 4123}
4124
5897297b
AK		 4125static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4126{
4127 if (!longmode_only)
8d14695f
YZ		 4128 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4129 msr, MSR_TYPE_R | MSR_TYPE_W);
4130 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4131 msr, MSR_TYPE_R | MSR_TYPE_W);
4132}
4133
4134static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
4135{
4136 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4137 msr, MSR_TYPE_R);
4138 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4139 msr, MSR_TYPE_R);
4140}
4141
4142static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4143{
4144 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4145 msr, MSR_TYPE_R);
4146 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4147 msr, MSR_TYPE_R);
4148}
4149
4150static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4151{
4152 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4153 msr, MSR_TYPE_W);
4154 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4155 msr, MSR_TYPE_W);
5897297b
AK		 4156}
4157
01e439be
YZ		 4158static int vmx_vm_has_apicv(struct kvm *kvm)
4159{
4160 return enable_apicv && irqchip_in_kernel(kvm);
4161}
4162
a20ed54d
YZ		 4163/*
4164 * Send interrupt to vcpu via posted interrupt way.
4165 * 1. If target vcpu is running(non-root mode), send posted interrupt
4166 * notification to vcpu and hardware will sync PIR to vIRR atomically.
4167 * 2. If target vcpu isn't running(root mode), kick it to pick up the
4168 * interrupt from PIR in next vmentry.
4169 */
4170static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4171{
4172 struct vcpu_vmx *vmx = to_vmx(vcpu);
4173 int r;
4174
4175 if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4176 return;
4177
4178 r = pi_test_and_set_on(&vmx->pi_desc);
4179 kvm_make_request(KVM_REQ_EVENT, vcpu);
6ffbbbba 4180#ifdef CONFIG_SMP
a20ed54d
YZ		 4181 if (!r && (vcpu->mode == IN_GUEST_MODE))
4182 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4183 POSTED_INTR_VECTOR);
4184 else
6ffbbbba 4185#endif
a20ed54d
YZ		 4186 kvm_vcpu_kick(vcpu);
4187}
4188
4189static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4190{
4191 struct vcpu_vmx *vmx = to_vmx(vcpu);
4192
4193 if (!pi_test_and_clear_on(&vmx->pi_desc))
4194 return;
4195
4196 kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4197}
4198
4199static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu)
4200{
4201 return;
4202}
4203
a3a8ff8e
NHE		 4204/*
4205 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4206 * will not change in the lifetime of the guest.
4207 * Note that host-state that does change is set elsewhere. E.g., host-state
4208 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4209 */
a547c6db 4210static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
a3a8ff8e
NHE		 4211{
4212 u32 low32, high32;
4213 unsigned long tmpl;
4214 struct desc_ptr dt;
d974baa3 4215 unsigned long cr4;
a3a8ff8e 4216
b1a74bf8 4217 vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS); /* 22.2.3 */
a3a8ff8e
NHE		 4218 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
4219
d974baa3
AL		 4220 /* Save the most likely value for this task's CR4 in the VMCS. */
4221 cr4 = read_cr4();
4222 vmcs_writel(HOST_CR4, cr4); /* 22.2.3, 22.2.5 */
4223 vmx->host_state.vmcs_host_cr4 = cr4;
4224
a3a8ff8e 4225 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
b2da15ac
AK		 4226#ifdef CONFIG_X86_64
4227 /*
4228 * Load null selectors, so we can avoid reloading them in
4229 * __vmx_load_host_state(), in case userspace uses the null selectors
4230 * too (the expected case).
4231 */
4232 vmcs_write16(HOST_DS_SELECTOR, 0);
4233 vmcs_write16(HOST_ES_SELECTOR, 0);
4234#else
a3a8ff8e
NHE		 4235 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4236 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
b2da15ac 4237#endif
a3a8ff8e
NHE		 4238 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4239 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
4240
4241 native_store_idt(&dt);
4242 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
a547c6db 4243 vmx->host_idt_base = dt.address;
a3a8ff8e 4244
83287ea4 4245 vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
a3a8ff8e
NHE		 4246
4247 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4248 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4249 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4250 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
4251
4252 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4253 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4254 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4255 }
4256}
4257
bf8179a0
NHE		 4258static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4259{
4260 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4261 if (enable_ept)
4262 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
fe3ef05c
NHE		 4263 if (is_guest_mode(&vmx->vcpu))
4264 vmx->vcpu.arch.cr4_guest_owned_bits &=
4265 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
bf8179a0
NHE		 4266 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4267}
4268
01e439be
YZ		 4269static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4270{
4271 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4272
4273 if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4274 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4275 return pin_based_exec_ctrl;
4276}
4277
bf8179a0
NHE		 4278static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4279{
4280 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
d16c293e
PB		 4281
4282 if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
4283 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
4284
bf8179a0
NHE		 4285 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
4286 exec_control &= ~CPU_BASED_TPR_SHADOW;
4287#ifdef CONFIG_X86_64
4288 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4289 CPU_BASED_CR8_LOAD_EXITING;
4290#endif
4291 }
4292 if (!enable_ept)
4293 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4294 CPU_BASED_CR3_LOAD_EXITING |
4295 CPU_BASED_INVLPG_EXITING;
4296 return exec_control;
4297}
4298
4299static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4300{
4301 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4302 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4303 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4304 if (vmx->vpid == 0)
4305 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4306 if (!enable_ept) {
4307 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4308 enable_unrestricted_guest = 0;
ad756a16
MJ		 4309 /* Enable INVPCID for non-ept guests may cause performance regression. */
4310 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
bf8179a0
NHE		 4311 }
4312 if (!enable_unrestricted_guest)
4313 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4314 if (!ple_gap)
4315 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
c7c9c56c
YZ		 4316 if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4317 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4318 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
8d14695f 4319 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
abc4fc58
AG		 4320 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4321 (handle_vmptrld).
4322 We can NOT enable shadow_vmcs here because we don't have yet
4323 a current VMCS12
4324 */
4325 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
bf8179a0
NHE		 4326 return exec_control;
4327}
4328
ce88decf
XG		 4329static void ept_set_mmio_spte_mask(void)
4330{
4331 /*
4332 * EPT Misconfigurations can be generated if the value of bits 2:0
4333 * of an EPT paging-structure entry is 110b (write/execute).
885032b9 4334 * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
ce88decf
XG		 4335 * spte.
4336 */
885032b9 4337 kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
ce88decf
XG		 4338}
4339
6aa8b732
AK		 4340/*
4341 * Sets up the vmcs for emulated real mode.
4342 */
8b9cf98c 4343static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 4344{
2e4ce7f5 4345#ifdef CONFIG_X86_64
6aa8b732 4346 unsigned long a;
2e4ce7f5 4347#endif
6aa8b732 4348 int i;
6aa8b732 4349
6aa8b732 4350 /* I/O */
3e7c73e9
AK		 4351 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4352 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 4353
4607c2d7
AG		 4354 if (enable_shadow_vmcs) {
4355 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4356 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4357 }
25c5f225 4358 if (cpu_has_vmx_msr_bitmap())
5897297b 4359 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 4360
6aa8b732
AK		 4361 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4362
6aa8b732 4363 /* Control */
01e439be 4364 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
6e5d865c 4365
bf8179a0 4366 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
6aa8b732 4367
83ff3b9d 4368 if (cpu_has_secondary_exec_ctrls()) {
bf8179a0
NHE		 4369 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4370 vmx_secondary_exec_control(vmx));
83ff3b9d 4371 }
f78e0e2e 4372
01e439be 4373 if (vmx_vm_has_apicv(vmx->vcpu.kvm)) {
c7c9c56c
YZ		 4374 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4375 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4376 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4377 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4378
4379 vmcs_write16(GUEST_INTR_STATUS, 0);
01e439be
YZ		 4380
4381 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4382 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
c7c9c56c
YZ		 4383 }
4384
4b8d54f9
ZE		 4385 if (ple_gap) {
4386 vmcs_write32(PLE_GAP, ple_gap);
a7653ecd
RK		 4387 vmx->ple_window = ple_window;
4388 vmx->ple_window_dirty = true;
4b8d54f9
ZE		 4389 }
4390
c3707958
XG		 4391 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4392 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
6aa8b732
AK		 4393 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
4394
9581d442
AK		 4395 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
4396 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
a547c6db 4397 vmx_set_constant_host_state(vmx);
05b3e0c2 4398#ifdef CONFIG_X86_64
6aa8b732
AK		 4399 rdmsrl(MSR_FS_BASE, a);
4400 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4401 rdmsrl(MSR_GS_BASE, a);
4402 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4403#else
4404 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4405 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4406#endif
4407
2cc51560
ED		 4408 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4409 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
61d2ef2c 4410 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2cc51560 4411 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
61d2ef2c 4412 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
6aa8b732 4413
468d472f 4414 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
a3a8ff8e
NHE		 4415 u32 msr_low, msr_high;
4416 u64 host_pat;
468d472f
SY		 4417 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
4418 host_pat = msr_low | ((u64) msr_high << 32);
4419 /* Write the default value follow host pat */
4420 vmcs_write64(GUEST_IA32_PAT, host_pat);
4421 /* Keep arch.pat sync with GUEST_IA32_PAT */
4422 vmx->vcpu.arch.pat = host_pat;
4423 }
4424
03916db9 4425 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
6aa8b732
AK		 4426 u32 index = vmx_msr_index[i];
4427 u32 data_low, data_high;
a2fa3e9f 4428 int j = vmx->nmsrs;
6aa8b732
AK		 4429
4430 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4431 continue;
432bd6cb
AK		 4432 if (wrmsr_safe(index, data_low, data_high) < 0)
4433 continue;
26bb0981
AK		 4434 vmx->guest_msrs[j].index = i;
4435 vmx->guest_msrs[j].data = 0;
d5696725 4436 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 4437 ++vmx->nmsrs;
6aa8b732 4438 }
6aa8b732 4439
2961e876
GN		 4440
4441 vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 4442
4443 /* 22.2.1, 20.8.1 */
2961e876 4444 vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
1c3d14fe 4445
e00c8cf2 4446 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
bf8179a0 4447 set_cr4_guest_host_mask(vmx);
e00c8cf2
AK		 4448
4449 return 0;
4450}
4451
57f252f2 4452static void vmx_vcpu_reset(struct kvm_vcpu *vcpu)
e00c8cf2
AK		 4453{
4454 struct vcpu_vmx *vmx = to_vmx(vcpu);
58cb628d 4455 struct msr_data apic_base_msr;
e00c8cf2 4456
7ffd92c5 4457 vmx->rmode.vm86_active = 0;
e00c8cf2 4458
3b86cd99
JK		 4459 vmx->soft_vnmi_blocked = 0;
4460
ad312c7c 4461 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 4462 kvm_set_cr8(&vmx->vcpu, 0);
73a6d941 4463 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE | MSR_IA32_APICBASE_ENABLE;
c5af89b6 4464 if (kvm_vcpu_is_bsp(&vmx->vcpu))
58cb628d
JK		 4465 apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4466 apic_base_msr.host_initiated = true;
4467 kvm_set_apic_base(&vmx->vcpu, &apic_base_msr);
e00c8cf2 4468
2fb92db1
AK		 4469 vmx_segment_cache_clear(vmx);
4470
5706be0d 4471 seg_setup(VCPU_SREG_CS);
66450a21 4472 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
04b66839 4473 vmcs_write32(GUEST_CS_BASE, 0xffff0000);
e00c8cf2
AK		 4474
4475 seg_setup(VCPU_SREG_DS);
4476 seg_setup(VCPU_SREG_ES);
4477 seg_setup(VCPU_SREG_FS);
4478 seg_setup(VCPU_SREG_GS);
4479 seg_setup(VCPU_SREG_SS);
4480
4481 vmcs_write16(GUEST_TR_SELECTOR, 0);
4482 vmcs_writel(GUEST_TR_BASE, 0);
4483 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4484 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4485
4486 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4487 vmcs_writel(GUEST_LDTR_BASE, 0);
4488 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4489 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4490
4491 vmcs_write32(GUEST_SYSENTER_CS, 0);
4492 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4493 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4494
4495 vmcs_writel(GUEST_RFLAGS, 0x02);
66450a21 4496 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 4497
e00c8cf2
AK		 4498 vmcs_writel(GUEST_GDTR_BASE, 0);
4499 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4500
4501 vmcs_writel(GUEST_IDTR_BASE, 0);
4502 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4503
443381a8 4504 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
e00c8cf2
AK		 4505 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4506 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4507
e00c8cf2
AK		 4508 /* Special registers */
4509 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4510
4511 setup_msrs(vmx);
4512
6aa8b732
AK		 4513 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
4514
f78e0e2e
SY		 4515 if (cpu_has_vmx_tpr_shadow()) {
4516 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4517 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
4518 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
afc20184 4519 __pa(vmx->vcpu.arch.apic->regs));
f78e0e2e
SY		 4520 vmcs_write32(TPR_THRESHOLD, 0);
4521 }
4522
a73896cb 4523 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
6aa8b732 4524
01e439be
YZ		 4525 if (vmx_vm_has_apicv(vcpu->kvm))
4526 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
4527
2384d2b3
SY		 4528 if (vmx->vpid != 0)
4529 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4530
fa40052c 4531 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4d4ec087 4532 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
8b9cf98c 4533 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 4534 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 4535 vmx_fpu_activate(&vmx->vcpu);
4536 update_exception_bitmap(&vmx->vcpu);
6aa8b732 4537
b9d762fa 4538 vpid_sync_context(vmx);
6aa8b732
AK		 4539}
4540
b6f1250e
NHE		 4541/*
4542 * In nested virtualization, check if L1 asked to exit on external interrupts.
4543 * For most existing hypervisors, this will always return true.
4544 */
4545static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4546{
4547 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4548 PIN_BASED_EXT_INTR_MASK;
4549}
4550
77b0f5d6
BD		 4551/*
4552 * In nested virtualization, check if L1 has set
4553 * VM_EXIT_ACK_INTR_ON_EXIT
4554 */
4555static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
4556{
4557 return get_vmcs12(vcpu)->vm_exit_controls &
4558 VM_EXIT_ACK_INTR_ON_EXIT;
4559}
4560
ea8ceb83
JK		 4561static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
4562{
4563 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4564 PIN_BASED_NMI_EXITING;
4565}
4566
c9a7953f 4567static void enable_irq_window(struct kvm_vcpu *vcpu)
3b86cd99
JK		 4568{
4569 u32 cpu_based_vm_exec_control;
730dca42 4570
3b86cd99
JK		 4571 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4572 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4573 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4574}
4575
c9a7953f 4576static void enable_nmi_window(struct kvm_vcpu *vcpu)
3b86cd99
JK		 4577{
4578 u32 cpu_based_vm_exec_control;
4579
c9a7953f
JK		 4580 if (!cpu_has_virtual_nmis() ||
4581 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4582 enable_irq_window(vcpu);
4583 return;
4584 }
3b86cd99
JK		 4585
4586 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4587 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4588 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4589}
4590
66fd3f7f 4591static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 4592{
9c8cba37 4593 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 4594 uint32_t intr;
4595 int irq = vcpu->arch.interrupt.nr;
9c8cba37 4596
229456fc 4597 trace_kvm_inj_virq(irq);
2714d1d3 4598
fa89a817 4599 ++vcpu->stat.irq_injections;
7ffd92c5 4600 if (vmx->rmode.vm86_active) {
71f9833b
SH		 4601 int inc_eip = 0;
4602 if (vcpu->arch.interrupt.soft)
4603 inc_eip = vcpu->arch.event_exit_inst_len;
4604 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
a92601bb 4605 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
85f455f7
ED		 4606 return;
4607 }
66fd3f7f
GN		 4608 intr = irq | INTR_INFO_VALID_MASK;
4609 if (vcpu->arch.interrupt.soft) {
4610 intr |= INTR_TYPE_SOFT_INTR;
4611 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4612 vmx->vcpu.arch.event_exit_inst_len);
4613 } else
4614 intr |= INTR_TYPE_EXT_INTR;
4615 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
85f455f7
ED		 4616}
4617
f08864b4
SY		 4618static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4619{
66a5a347
JK		 4620 struct vcpu_vmx *vmx = to_vmx(vcpu);
4621
0b6ac343
NHE		 4622 if (is_guest_mode(vcpu))
4623 return;
4624
3b86cd99
JK		 4625 if (!cpu_has_virtual_nmis()) {
4626 /*
4627 * Tracking the NMI-blocked state in software is built upon
4628 * finding the next open IRQ window. This, in turn, depends on
4629 * well-behaving guests: They have to keep IRQs disabled at
4630 * least as long as the NMI handler runs. Otherwise we may
4631 * cause NMI nesting, maybe breaking the guest. But as this is
4632 * highly unlikely, we can live with the residual risk.
4633 */
4634 vmx->soft_vnmi_blocked = 1;
4635 vmx->vnmi_blocked_time = 0;
4636 }
4637
487b391d 4638 ++vcpu->stat.nmi_injections;
9d58b931 4639 vmx->nmi_known_unmasked = false;
7ffd92c5 4640 if (vmx->rmode.vm86_active) {
71f9833b 4641 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
a92601bb 4642 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
66a5a347
JK		 4643 return;
4644 }
f08864b4
SY		 4645 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4646 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
f08864b4
SY		 4647}
4648
3cfc3092
JK		 4649static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4650{
4651 if (!cpu_has_virtual_nmis())
4652 return to_vmx(vcpu)->soft_vnmi_blocked;
9d58b931
AK		 4653 if (to_vmx(vcpu)->nmi_known_unmasked)
4654 return false;
c332c83a 4655 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3cfc3092
JK		 4656}
4657
4658static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4659{
4660 struct vcpu_vmx *vmx = to_vmx(vcpu);
4661
4662 if (!cpu_has_virtual_nmis()) {
4663 if (vmx->soft_vnmi_blocked != masked) {
4664 vmx->soft_vnmi_blocked = masked;
4665 vmx->vnmi_blocked_time = 0;
4666 }
4667 } else {
9d58b931 4668 vmx->nmi_known_unmasked = !masked;
3cfc3092
JK		 4669 if (masked)
4670 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4671 GUEST_INTR_STATE_NMI);
4672 else
4673 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4674 GUEST_INTR_STATE_NMI);
4675 }
4676}
4677
2505dc9f
JK		 4678static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4679{
b6b8a145
JK		 4680 if (to_vmx(vcpu)->nested.nested_run_pending)
4681 return 0;
ea8ceb83 4682
2505dc9f
JK		 4683 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
4684 return 0;
4685
4686 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4687 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4688 | GUEST_INTR_STATE_NMI));
4689}
4690
78646121
GN		 4691static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4692{
b6b8a145
JK		 4693 return (!to_vmx(vcpu)->nested.nested_run_pending &&
4694 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
c4282df9
GN		 4695 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4696 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 4697}
4698
cbc94022
IE		 4699static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4700{
4701 int ret;
4702 struct kvm_userspace_memory_region tss_mem = {
6fe63979 4703 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 4704 .guest_phys_addr = addr,
4705 .memory_size = PAGE_SIZE * 3,
4706 .flags = 0,
4707 };
4708
47ae31e2 4709 ret = kvm_set_memory_region(kvm, &tss_mem);
cbc94022
IE		 4710 if (ret)
4711 return ret;
bfc6d222 4712 kvm->arch.tss_addr = addr;
1f755a82 4713 return init_rmode_tss(kvm);
cbc94022
IE		 4714}
4715
0ca1b4f4 4716static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
6aa8b732 4717{
77ab6db0 4718 switch (vec) {
77ab6db0 4719 case BP_VECTOR:
c573cd22
JK		 4720 /*
4721 * Update instruction length as we may reinject the exception
4722 * from user space while in guest debugging mode.
4723 */
4724 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4725 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940 4726 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
0ca1b4f4
GN		 4727 return false;
4728 /* fall through */
4729 case DB_VECTOR:
4730 if (vcpu->guest_debug &
4731 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4732 return false;
d0bfb940
JK		 4733 /* fall through */
4734 case DE_VECTOR:
77ab6db0
JK		 4735 case OF_VECTOR:
4736 case BR_VECTOR:
4737 case UD_VECTOR:
4738 case DF_VECTOR:
4739 case SS_VECTOR:
4740 case GP_VECTOR:
4741 case MF_VECTOR:
0ca1b4f4
GN		 4742 return true;
4743 break;
77ab6db0 4744 }
0ca1b4f4
GN		 4745 return false;
4746}
4747
4748static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4749 int vec, u32 err_code)
4750{
4751 /*
4752 * Instruction with address size override prefix opcode 0x67
4753 * Cause the #SS fault with 0 error code in VM86 mode.
4754 */
4755 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4756 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
4757 if (vcpu->arch.halt_request) {
4758 vcpu->arch.halt_request = 0;
4759 return kvm_emulate_halt(vcpu);
4760 }
4761 return 1;
4762 }
4763 return 0;
4764 }
4765
4766 /*
4767 * Forward all other exceptions that are valid in real mode.
4768 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4769 * the required debugging infrastructure rework.
4770 */
4771 kvm_queue_exception(vcpu, vec);
4772 return 1;
6aa8b732
AK		 4773}
4774
a0861c02
AK		 4775/*
4776 * Trigger machine check on the host. We assume all the MSRs are already set up
4777 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4778 * We pass a fake environment to the machine check handler because we want
4779 * the guest to be always treated like user space, no matter what context
4780 * it used internally.
4781 */
4782static void kvm_machine_check(void)
4783{
4784#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4785 struct pt_regs regs = {
4786 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4787 .flags = X86_EFLAGS_IF,
4788 };
4789
4790 do_machine_check(&regs, 0);
4791#endif
4792}
4793
851ba692 4794static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK		 4795{
4796 /* already handled by vcpu_run */
4797 return 1;
4798}
4799
851ba692 4800static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 4801{
1155f76a 4802 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 4803 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 4804 u32 intr_info, ex_no, error_code;
42dbaa5a 4805 unsigned long cr2, rip, dr6;
6aa8b732
AK		 4806 u32 vect_info;
4807 enum emulation_result er;
4808
1155f76a 4809 vect_info = vmx->idt_vectoring_info;
88786475 4810 intr_info = vmx->exit_intr_info;
6aa8b732 4811
a0861c02 4812 if (is_machine_check(intr_info))
851ba692 4813 return handle_machine_check(vcpu);
a0861c02 4814
e4a41889 4815 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 4816 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 4817
4818 if (is_no_device(intr_info)) {
5fd86fcf 4819 vmx_fpu_activate(vcpu);
2ab455cc
AL		 4820 return 1;
4821 }
4822
7aa81cc0 4823 if (is_invalid_opcode(intr_info)) {
51d8b661 4824 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
7aa81cc0 4825 if (er != EMULATE_DONE)
7ee5d940 4826 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 4827 return 1;
4828 }
4829
6aa8b732 4830 error_code = 0;
2e11384c 4831 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732 4832 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
bf4ca23e
XG		 4833
4834 /*
4835 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4836 * MMIO, it is better to report an internal error.
4837 * See the comments in vmx_handle_exit.
4838 */
4839 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4840 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4841 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4842 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4843 vcpu->run->internal.ndata = 2;
4844 vcpu->run->internal.data[0] = vect_info;
4845 vcpu->run->internal.data[1] = intr_info;
4846 return 0;
4847 }
4848
6aa8b732 4849 if (is_page_fault(intr_info)) {
1439442c 4850 /* EPT won't cause page fault directly */
cf3ace79 4851 BUG_ON(enable_ept);
6aa8b732 4852 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT		 4853 trace_kvm_page_fault(cr2, error_code);
4854
3298b75c 4855 if (kvm_event_needs_reinjection(vcpu))
577bdc49 4856 kvm_mmu_unprotect_page_virt(vcpu, cr2);
dc25e89e 4857 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
6aa8b732
AK		 4858 }
4859
d0bfb940 4860 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
0ca1b4f4
GN		 4861
4862 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4863 return handle_rmode_exception(vcpu, ex_no, error_code);
4864
42dbaa5a
JK		 4865 switch (ex_no) {
4866 case DB_VECTOR:
4867 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4868 if (!(vcpu->guest_debug &
4869 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
8246bf52 4870 vcpu->arch.dr6 &= ~15;
6f43ed01 4871 vcpu->arch.dr6 |= dr6 | DR6_RTM;
fd2a445a
HD		 4872 if (!(dr6 & ~DR6_RESERVED)) /* icebp */
4873 skip_emulated_instruction(vcpu);
4874
42dbaa5a
JK		 4875 kvm_queue_exception(vcpu, DB_VECTOR);
4876 return 1;
4877 }
4878 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4879 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4880 /* fall through */
4881 case BP_VECTOR:
c573cd22
JK		 4882 /*
4883 * Update instruction length as we may reinject #BP from
4884 * user space while in guest debugging mode. Reading it for
4885 * #DB as well causes no harm, it is not used in that case.
4886 */
4887 vmx->vcpu.arch.event_exit_inst_len =
4888 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 4889 kvm_run->exit_reason = KVM_EXIT_DEBUG;
0a434bb2 4890 rip = kvm_rip_read(vcpu);
d0bfb940
JK		 4891 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4892 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 4893 break;
4894 default:
d0bfb940
JK		 4895 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4896 kvm_run->ex.exception = ex_no;
4897 kvm_run->ex.error_code = error_code;
42dbaa5a 4898 break;
6aa8b732 4899 }
6aa8b732
AK		 4900 return 0;
4901}
4902
851ba692 4903static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 4904{
1165f5fe 4905 ++vcpu->stat.irq_exits;
6aa8b732
AK		 4906 return 1;
4907}
4908
851ba692 4909static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 4910{
851ba692 4911 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK		 4912 return 0;
4913}
6aa8b732 4914
851ba692 4915static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 4916{
bfdaab09 4917 unsigned long exit_qualification;
34c33d16 4918 int size, in, string;
039576c0 4919 unsigned port;
6aa8b732 4920
bfdaab09 4921 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 4922 string = (exit_qualification & 16) != 0;
cf8f70bf 4923 in = (exit_qualification & 8) != 0;
e70669ab 4924
cf8f70bf 4925 ++vcpu->stat.io_exits;
e70669ab 4926
cf8f70bf 4927 if (string || in)
51d8b661 4928 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
e70669ab 4929
cf8f70bf
GN		 4930 port = exit_qualification >> 16;
4931 size = (exit_qualification & 7) + 1;
e93f36bc 4932 skip_emulated_instruction(vcpu);
cf8f70bf
GN		 4933
4934 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 4935}
4936
102d8325
IM		 4937static void
4938vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4939{
4940 /*
4941 * Patch in the VMCALL instruction:
4942 */
4943 hypercall[0] = 0x0f;
4944 hypercall[1] = 0x01;
4945 hypercall[2] = 0xc1;
102d8325
IM		 4946}
4947
92fbc7b1
JK		 4948static bool nested_cr0_valid(struct vmcs12 *vmcs12, unsigned long val)
4949{
4950 unsigned long always_on = VMXON_CR0_ALWAYSON;
4951
4952 if (nested_vmx_secondary_ctls_high &
4953 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
4954 nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
4955 always_on &= ~(X86_CR0_PE | X86_CR0_PG);
4956 return (val & always_on) == always_on;
4957}
4958
0fa06071 4959/* called to set cr0 as appropriate for a mov-to-cr0 exit. */
eeadf9e7
NHE		 4960static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4961{
eeadf9e7 4962 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 4963 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4964 unsigned long orig_val = val;
4965
eeadf9e7
NHE		 4966 /*
4967 * We get here when L2 changed cr0 in a way that did not change
4968 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
1a0d74e6
JK		 4969 * but did change L0 shadowed bits. So we first calculate the
4970 * effective cr0 value that L1 would like to write into the
4971 * hardware. It consists of the L2-owned bits from the new
4972 * value combined with the L1-owned bits from L1's guest_cr0.
eeadf9e7 4973 */
1a0d74e6
JK		 4974 val = (val & ~vmcs12->cr0_guest_host_mask) |
4975 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
4976
92fbc7b1 4977 if (!nested_cr0_valid(vmcs12, val))
eeadf9e7 4978 return 1;
1a0d74e6
JK		 4979
4980 if (kvm_set_cr0(vcpu, val))
4981 return 1;
4982 vmcs_writel(CR0_READ_SHADOW, orig_val);
eeadf9e7 4983 return 0;
1a0d74e6
JK		 4984 } else {
4985 if (to_vmx(vcpu)->nested.vmxon &&
4986 ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
4987 return 1;
eeadf9e7 4988 return kvm_set_cr0(vcpu, val);
1a0d74e6 4989 }
eeadf9e7
NHE		 4990}
4991
4992static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4993{
4994 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 4995 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4996 unsigned long orig_val = val;
4997
4998 /* analogously to handle_set_cr0 */
4999 val = (val & ~vmcs12->cr4_guest_host_mask) |
5000 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
5001 if (kvm_set_cr4(vcpu, val))
eeadf9e7 5002 return 1;
1a0d74e6 5003 vmcs_writel(CR4_READ_SHADOW, orig_val);
eeadf9e7
NHE		 5004 return 0;
5005 } else
5006 return kvm_set_cr4(vcpu, val);
5007}
5008
5009/* called to set cr0 as approriate for clts instruction exit. */
5010static void handle_clts(struct kvm_vcpu *vcpu)
5011{
5012 if (is_guest_mode(vcpu)) {
5013 /*
5014 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
5015 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
5016 * just pretend it's off (also in arch.cr0 for fpu_activate).
5017 */
5018 vmcs_writel(CR0_READ_SHADOW,
5019 vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
5020 vcpu->arch.cr0 &= ~X86_CR0_TS;
5021 } else
5022 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
5023}
5024
851ba692 5025static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 5026{
229456fc 5027 unsigned long exit_qualification, val;
6aa8b732
AK		 5028 int cr;
5029 int reg;
49a9b07e 5030 int err;
6aa8b732 5031
bfdaab09 5032 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 5033 cr = exit_qualification & 15;
5034 reg = (exit_qualification >> 8) & 15;
5035 switch ((exit_qualification >> 4) & 3) {
5036 case 0: /* mov to cr */
1e32c079 5037 val = kvm_register_readl(vcpu, reg);
229456fc 5038 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 5039 switch (cr) {
5040 case 0:
eeadf9e7 5041 err = handle_set_cr0(vcpu, val);
db8fcefa 5042 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 5043 return 1;
5044 case 3:
2390218b 5045 err = kvm_set_cr3(vcpu, val);
db8fcefa 5046 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 5047 return 1;
5048 case 4:
eeadf9e7 5049 err = handle_set_cr4(vcpu, val);
db8fcefa 5050 kvm_complete_insn_gp(vcpu, err);
6aa8b732 5051 return 1;
0a5fff19
GN		 5052 case 8: {
5053 u8 cr8_prev = kvm_get_cr8(vcpu);
1e32c079 5054 u8 cr8 = (u8)val;
eea1cff9 5055 err = kvm_set_cr8(vcpu, cr8);
db8fcefa 5056 kvm_complete_insn_gp(vcpu, err);
0a5fff19
GN		 5057 if (irqchip_in_kernel(vcpu->kvm))
5058 return 1;
5059 if (cr8_prev <= cr8)
5060 return 1;
851ba692 5061 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 5062 return 0;
5063 }
4b8073e4 5064 }
6aa8b732 5065 break;
25c4c276 5066 case 2: /* clts */
eeadf9e7 5067 handle_clts(vcpu);
4d4ec087 5068 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
25c4c276 5069 skip_emulated_instruction(vcpu);
6b52d186 5070 vmx_fpu_activate(vcpu);
25c4c276 5071 return 1;
6aa8b732
AK		 5072 case 1: /*mov from cr*/
5073 switch (cr) {
5074 case 3:
9f8fe504
AK		 5075 val = kvm_read_cr3(vcpu);
5076 kvm_register_write(vcpu, reg, val);
5077 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 5078 skip_emulated_instruction(vcpu);
5079 return 1;
5080 case 8:
229456fc
MT		 5081 val = kvm_get_cr8(vcpu);
5082 kvm_register_write(vcpu, reg, val);
5083 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 5084 skip_emulated_instruction(vcpu);
5085 return 1;
5086 }
5087 break;
5088 case 3: /* lmsw */
a1f83a74 5089 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 5090 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 5091 kvm_lmsw(vcpu, val);
6aa8b732
AK		 5092
5093 skip_emulated_instruction(vcpu);
5094 return 1;
5095 default:
5096 break;
5097 }
851ba692 5098 vcpu->run->exit_reason = 0;
a737f256 5099 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 5100 (int)(exit_qualification >> 4) & 3, cr);
5101 return 0;
5102}
5103
851ba692 5104static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 5105{
bfdaab09 5106 unsigned long exit_qualification;
16f8a6f9
NA		 5107 int dr, dr7, reg;
5108
5109 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5110 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5111
5112 /* First, if DR does not exist, trigger UD */
5113 if (!kvm_require_dr(vcpu, dr))
5114 return 1;
6aa8b732 5115
f2483415 5116 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK		 5117 if (!kvm_require_cpl(vcpu, 0))
5118 return 1;
16f8a6f9
NA		 5119 dr7 = vmcs_readl(GUEST_DR7);
5120 if (dr7 & DR7_GD) {
42dbaa5a
JK		 5121 /*
5122 * As the vm-exit takes precedence over the debug trap, we
5123 * need to emulate the latter, either for the host or the
5124 * guest debugging itself.
5125 */
5126 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692 5127 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
16f8a6f9 5128 vcpu->run->debug.arch.dr7 = dr7;
82b32774 5129 vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
851ba692
AK		 5130 vcpu->run->debug.arch.exception = DB_VECTOR;
5131 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 5132 return 0;
5133 } else {
7305eb5d 5134 vcpu->arch.dr6 &= ~15;
6f43ed01 5135 vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
42dbaa5a
JK		 5136 kvm_queue_exception(vcpu, DB_VECTOR);
5137 return 1;
5138 }
5139 }
5140
81908bf4
PB		 5141 if (vcpu->guest_debug == 0) {
5142 u32 cpu_based_vm_exec_control;
5143
5144 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5145 cpu_based_vm_exec_control &= ~CPU_BASED_MOV_DR_EXITING;
5146 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5147
5148 /*
5149 * No more DR vmexits; force a reload of the debug registers
5150 * and reenter on this instruction. The next vmexit will
5151 * retrieve the full state of the debug registers.
5152 */
5153 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5154 return 1;
5155 }
5156
42dbaa5a
JK		 5157 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5158 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079 5159 unsigned long val;
4c4d563b
JK		 5160
5161 if (kvm_get_dr(vcpu, dr, &val))
5162 return 1;
5163 kvm_register_write(vcpu, reg, val);
020df079 5164 } else
5777392e 5165 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
4c4d563b
JK		 5166 return 1;
5167
6aa8b732
AK		 5168 skip_emulated_instruction(vcpu);
5169 return 1;
5170}
5171
73aaf249
JK		 5172static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
5173{
5174 return vcpu->arch.dr6;
5175}
5176
5177static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
5178{
5179}
5180
81908bf4
PB		 5181static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5182{
5183 u32 cpu_based_vm_exec_control;
5184
5185 get_debugreg(vcpu->arch.db[0], 0);
5186 get_debugreg(vcpu->arch.db[1], 1);
5187 get_debugreg(vcpu->arch.db[2], 2);
5188 get_debugreg(vcpu->arch.db[3], 3);
5189 get_debugreg(vcpu->arch.dr6, 6);
5190 vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5191
5192 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
5193
5194 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5195 cpu_based_vm_exec_control |= CPU_BASED_MOV_DR_EXITING;
5196 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5197}
5198
020df079
GN		 5199static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5200{
5201 vmcs_writel(GUEST_DR7, val);
5202}
5203
851ba692 5204static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 5205{
06465c5a
AK		 5206 kvm_emulate_cpuid(vcpu);
5207 return 1;
6aa8b732
AK		 5208}
5209
851ba692 5210static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 5211{
ad312c7c 5212 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 5213 u64 data;
5214
5215 if (vmx_get_msr(vcpu, ecx, &data)) {
59200273 5216 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 5217 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 5218 return 1;
5219 }
5220
229456fc 5221 trace_kvm_msr_read(ecx, data);
2714d1d3 5222
6aa8b732 5223 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 5224 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
5225 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 5226 skip_emulated_instruction(vcpu);
5227 return 1;
5228}
5229
851ba692 5230static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 5231{
8fe8ab46 5232 struct msr_data msr;
ad312c7c
ZX		 5233 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5234 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5235 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732 5236
8fe8ab46
WA		 5237 msr.data = data;
5238 msr.index = ecx;
5239 msr.host_initiated = false;
854e8bb1 5240 if (kvm_set_msr(vcpu, &msr) != 0) {
59200273 5241 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 5242 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 5243 return 1;
5244 }
5245
59200273 5246 trace_kvm_msr_write(ecx, data);
6aa8b732
AK		 5247 skip_emulated_instruction(vcpu);
5248 return 1;
5249}
5250
851ba692 5251static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c 5252{
3842d135 5253 kvm_make_request(KVM_REQ_EVENT, vcpu);
6e5d865c
YS		 5254 return 1;
5255}
5256
851ba692 5257static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 5258{
85f455f7
ED		 5259 u32 cpu_based_vm_exec_control;
5260
5261 /* clear pending irq */
5262 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5263 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5264 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3 5265
3842d135
AK		 5266 kvm_make_request(KVM_REQ_EVENT, vcpu);
5267
a26bf12a 5268 ++vcpu->stat.irq_window_exits;
2714d1d3 5269
c1150d8c
DL		 5270 /*
5271 * If the user space waits to inject interrupts, exit as soon as
5272 * possible
5273 */
8061823a 5274 if (!irqchip_in_kernel(vcpu->kvm) &&
851ba692 5275 vcpu->run->request_interrupt_window &&
8061823a 5276 !kvm_cpu_has_interrupt(vcpu)) {
851ba692 5277 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
c1150d8c
DL		 5278 return 0;
5279 }
6aa8b732
AK		 5280 return 1;
5281}
5282
851ba692 5283static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732
AK		 5284{
5285 skip_emulated_instruction(vcpu);
d3bef15f 5286 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 5287}
5288
851ba692 5289static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 5290{
510043da 5291 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 5292 kvm_emulate_hypercall(vcpu);
5293 return 1;
c21415e8
IM		 5294}
5295
ec25d5e6
GN		 5296static int handle_invd(struct kvm_vcpu *vcpu)
5297{
51d8b661 5298 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
ec25d5e6
GN		 5299}
5300
851ba692 5301static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 5302{
f9c617f6 5303 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 5304
5305 kvm_mmu_invlpg(vcpu, exit_qualification);
5306 skip_emulated_instruction(vcpu);
5307 return 1;
5308}
5309
fee84b07
AK		 5310static int handle_rdpmc(struct kvm_vcpu *vcpu)
5311{
5312 int err;
5313
5314 err = kvm_rdpmc(vcpu);
5315 kvm_complete_insn_gp(vcpu, err);
5316
5317 return 1;
5318}
5319
851ba692 5320static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01
ED		 5321{
5322 skip_emulated_instruction(vcpu);
f5f48ee1 5323 kvm_emulate_wbinvd(vcpu);
e5edaa01
ED		 5324 return 1;
5325}
5326
2acf923e
DC		 5327static int handle_xsetbv(struct kvm_vcpu *vcpu)
5328{
5329 u64 new_bv = kvm_read_edx_eax(vcpu);
5330 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5331
5332 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5333 skip_emulated_instruction(vcpu);
5334 return 1;
5335}
5336
851ba692 5337static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 5338{
58fbbf26
KT		 5339 if (likely(fasteoi)) {
5340 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5341 int access_type, offset;
5342
5343 access_type = exit_qualification & APIC_ACCESS_TYPE;
5344 offset = exit_qualification & APIC_ACCESS_OFFSET;
5345 /*
5346 * Sane guest uses MOV to write EOI, with written value
5347 * not cared. So make a short-circuit here by avoiding
5348 * heavy instruction emulation.
5349 */
5350 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5351 (offset == APIC_EOI)) {
5352 kvm_lapic_set_eoi(vcpu);
5353 skip_emulated_instruction(vcpu);
5354 return 1;
5355 }
5356 }
51d8b661 5357 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
f78e0e2e
SY		 5358}
5359
c7c9c56c
YZ		 5360static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5361{
5362 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5363 int vector = exit_qualification & 0xff;
5364
5365 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5366 kvm_apic_set_eoi_accelerated(vcpu, vector);
5367 return 1;
5368}
5369
83d4c286
YZ		 5370static int handle_apic_write(struct kvm_vcpu *vcpu)
5371{
5372 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5373 u32 offset = exit_qualification & 0xfff;
5374
5375 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5376 kvm_apic_write_nodecode(vcpu, offset);
5377 return 1;
5378}
5379
851ba692 5380static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 5381{
60637aac 5382 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 5383 unsigned long exit_qualification;
e269fb21
JK		 5384 bool has_error_code = false;
5385 u32 error_code = 0;
37817f29 5386 u16 tss_selector;
7f3d35fd 5387 int reason, type, idt_v, idt_index;
64a7ec06
GN		 5388
5389 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
7f3d35fd 5390 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
64a7ec06 5391 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 5392
5393 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5394
5395 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 5396 if (reason == TASK_SWITCH_GATE && idt_v) {
5397 switch (type) {
5398 case INTR_TYPE_NMI_INTR:
5399 vcpu->arch.nmi_injected = false;
654f06fc 5400 vmx_set_nmi_mask(vcpu, true);
64a7ec06
GN		 5401 break;
5402 case INTR_TYPE_EXT_INTR:
66fd3f7f 5403 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 5404 kvm_clear_interrupt_queue(vcpu);
5405 break;
5406 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK		 5407 if (vmx->idt_vectoring_info &
5408 VECTORING_INFO_DELIVER_CODE_MASK) {
5409 has_error_code = true;
5410 error_code =
5411 vmcs_read32(IDT_VECTORING_ERROR_CODE);
5412 }
5413 /* fall through */
64a7ec06
GN		 5414 case INTR_TYPE_SOFT_EXCEPTION:
5415 kvm_clear_exception_queue(vcpu);
5416 break;
5417 default:
5418 break;
5419 }
60637aac 5420 }
37817f29
IE		 5421 tss_selector = exit_qualification;
5422
64a7ec06
GN		 5423 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5424 type != INTR_TYPE_EXT_INTR &&
5425 type != INTR_TYPE_NMI_INTR))
5426 skip_emulated_instruction(vcpu);
5427
7f3d35fd
KW		 5428 if (kvm_task_switch(vcpu, tss_selector,
5429 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5430 has_error_code, error_code) == EMULATE_FAIL) {
acb54517
GN		 5431 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5432 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5433 vcpu->run->internal.ndata = 0;
42dbaa5a 5434 return 0;
acb54517 5435 }
42dbaa5a
JK		 5436
5437 /* clear all local breakpoint enable flags */
0e8a0996 5438 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~0x155);
42dbaa5a
JK		 5439
5440 /*
5441 * TODO: What about debug traps on tss switch?
5442 * Are we supposed to inject them and update dr6?
5443 */
5444
5445 return 1;
37817f29
IE		 5446}
5447
851ba692 5448static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 5449{
f9c617f6 5450 unsigned long exit_qualification;
1439442c 5451 gpa_t gpa;
4f5982a5 5452 u32 error_code;
1439442c 5453 int gla_validity;
1439442c 5454
f9c617f6 5455 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c 5456
1439442c
SY		 5457 gla_validity = (exit_qualification >> 7) & 0x3;
5458 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5459 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5460 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5461 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 5462 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 5463 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5464 (long unsigned int)exit_qualification);
851ba692
AK		 5465 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5466 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
596ae895 5467 return 0;
1439442c
SY		 5468 }
5469
0be9c7a8
GN		 5470 /*
5471 * EPT violation happened while executing iret from NMI,
5472 * "blocked by NMI" bit has to be set before next VM entry.
5473 * There are errata that may cause this bit to not be set:
5474 * AAK134, BY25.
5475 */
bcd1c294
GN		 5476 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5477 cpu_has_virtual_nmis() &&
5478 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
0be9c7a8
GN		 5479 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5480
1439442c 5481 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 5482 trace_kvm_page_fault(gpa, exit_qualification);
4f5982a5
XG		 5483
5484 /* It is a write fault? */
81ed33e4 5485 error_code = exit_qualification & PFERR_WRITE_MASK;
25d92081 5486 /* It is a fetch fault? */
81ed33e4 5487 error_code |= (exit_qualification << 2) & PFERR_FETCH_MASK;
4f5982a5 5488 /* ept page table is present? */
81ed33e4 5489 error_code |= (exit_qualification >> 3) & PFERR_PRESENT_MASK;
4f5982a5 5490
25d92081
YZ		 5491 vcpu->arch.exit_qualification = exit_qualification;
5492
4f5982a5 5493 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
1439442c
SY		 5494}
5495
68f89400
MT		 5496static u64 ept_rsvd_mask(u64 spte, int level)
5497{
5498 int i;
5499 u64 mask = 0;
5500
5501 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
5502 mask |= (1ULL << i);
5503
a32e8459 5504 if (level == 4)
68f89400
MT		 5505 /* bits 7:3 reserved */
5506 mask |= 0xf8;
a32e8459
WL		 5507 else if (spte & (1ULL << 7))
5508 /*
5509 * 1GB/2MB page, bits 29:12 or 20:12 reserved respectively,
5510 * level == 1 if the hypervisor is using the ignored bit 7.
5511 */
5512 mask |= (PAGE_SIZE << ((level - 1) * 9)) - PAGE_SIZE;
5513 else if (level > 1)
5514 /* bits 6:3 reserved */
5515 mask |= 0x78;
68f89400
MT		 5516
5517 return mask;
5518}
5519
5520static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
5521 int level)
5522{
5523 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
5524
5525 /* 010b (write-only) */
5526 WARN_ON((spte & 0x7) == 0x2);
5527
5528 /* 110b (write/execute) */
5529 WARN_ON((spte & 0x7) == 0x6);
5530
5531 /* 100b (execute-only) and value not supported by logical processor */
5532 if (!cpu_has_vmx_ept_execute_only())
5533 WARN_ON((spte & 0x7) == 0x4);
5534
5535 /* not 000b */
5536 if ((spte & 0x7)) {
5537 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
5538
5539 if (rsvd_bits != 0) {
5540 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
5541 __func__, rsvd_bits);
5542 WARN_ON(1);
5543 }
5544
a32e8459
WL		 5545 /* bits 5:3 are _not_ reserved for large page or leaf page */
5546 if ((rsvd_bits & 0x38) == 0) {
68f89400
MT		 5547 u64 ept_mem_type = (spte & 0x38) >> 3;
5548
5549 if (ept_mem_type == 2 || ept_mem_type == 3 ||
5550 ept_mem_type == 7) {
5551 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
5552 __func__, ept_mem_type);
5553 WARN_ON(1);
5554 }
5555 }
5556 }
5557}
5558
851ba692 5559static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400
MT		 5560{
5561 u64 sptes[4];
ce88decf 5562 int nr_sptes, i, ret;
68f89400
MT		 5563 gpa_t gpa;
5564
5565 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
68c3b4d1
MT		 5566 if (!kvm_io_bus_write(vcpu->kvm, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
5567 skip_emulated_instruction(vcpu);
5568 return 1;
5569 }
68f89400 5570
ce88decf 5571 ret = handle_mmio_page_fault_common(vcpu, gpa, true);
b37fbea6 5572 if (likely(ret == RET_MMIO_PF_EMULATE))
ce88decf
XG		 5573 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5574 EMULATE_DONE;
f8f55942
XG		 5575
5576 if (unlikely(ret == RET_MMIO_PF_INVALID))
5577 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
5578
b37fbea6 5579 if (unlikely(ret == RET_MMIO_PF_RETRY))
ce88decf
XG		 5580 return 1;
5581
5582 /* It is the real ept misconfig */
68f89400
MT		 5583 printk(KERN_ERR "EPT: Misconfiguration.\n");
5584 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
5585
5586 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
5587
5588 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
5589 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
5590
851ba692
AK		 5591 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5592 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT		 5593
5594 return 0;
5595}
5596
851ba692 5597static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4
SY		 5598{
5599 u32 cpu_based_vm_exec_control;
5600
5601 /* clear pending NMI */
5602 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5603 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
5604 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5605 ++vcpu->stat.nmi_window_exits;
3842d135 5606 kvm_make_request(KVM_REQ_EVENT, vcpu);
f08864b4
SY		 5607
5608 return 1;
5609}
5610
80ced186 5611static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 5612{
8b3079a5
AK		 5613 struct vcpu_vmx *vmx = to_vmx(vcpu);
5614 enum emulation_result err = EMULATE_DONE;
80ced186 5615 int ret = 1;
49e9d557
AK		 5616 u32 cpu_exec_ctrl;
5617 bool intr_window_requested;
b8405c18 5618 unsigned count = 130;
49e9d557
AK		 5619
5620 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5621 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
ea953ef0 5622
98eb2f8b 5623 while (vmx->emulation_required && count-- != 0) {
bdea48e3 5624 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
49e9d557
AK		 5625 return handle_interrupt_window(&vmx->vcpu);
5626
de87dcdd
AK		 5627 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5628 return 1;
5629
991eebf9 5630 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
ea953ef0 5631
ac0a48c3 5632 if (err == EMULATE_USER_EXIT) {
94452b9e 5633 ++vcpu->stat.mmio_exits;
80ced186
MG		 5634 ret = 0;
5635 goto out;
5636 }
1d5a4d9b 5637
de5f70e0
AK		 5638 if (err != EMULATE_DONE) {
5639 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5640 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5641 vcpu->run->internal.ndata = 0;
6d77dbfc 5642 return 0;
de5f70e0 5643 }
ea953ef0 5644
8d76c49e
GN		 5645 if (vcpu->arch.halt_request) {
5646 vcpu->arch.halt_request = 0;
5647 ret = kvm_emulate_halt(vcpu);
5648 goto out;
5649 }
5650
ea953ef0 5651 if (signal_pending(current))
80ced186 5652 goto out;
ea953ef0
MG		 5653 if (need_resched())
5654 schedule();
5655 }
5656
80ced186
MG		 5657out:
5658 return ret;
ea953ef0
MG		 5659}
5660
b4a2d31d
RK		 5661static int __grow_ple_window(int val)
5662{
5663 if (ple_window_grow < 1)
5664 return ple_window;
5665
5666 val = min(val, ple_window_actual_max);
5667
5668 if (ple_window_grow < ple_window)
5669 val *= ple_window_grow;
5670 else
5671 val += ple_window_grow;
5672
5673 return val;
5674}
5675
5676static int __shrink_ple_window(int val, int modifier, int minimum)
5677{
5678 if (modifier < 1)
5679 return ple_window;
5680
5681 if (modifier < ple_window)
5682 val /= modifier;
5683 else
5684 val -= modifier;
5685
5686 return max(val, minimum);
5687}
5688
5689static void grow_ple_window(struct kvm_vcpu *vcpu)
5690{
5691 struct vcpu_vmx *vmx = to_vmx(vcpu);
5692 int old = vmx->ple_window;
5693
5694 vmx->ple_window = __grow_ple_window(old);
5695
5696 if (vmx->ple_window != old)
5697 vmx->ple_window_dirty = true;
7b46268d
RK		 5698
5699 trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
b4a2d31d
RK		 5700}
5701
5702static void shrink_ple_window(struct kvm_vcpu *vcpu)
5703{
5704 struct vcpu_vmx *vmx = to_vmx(vcpu);
5705 int old = vmx->ple_window;
5706
5707 vmx->ple_window = __shrink_ple_window(old,
5708 ple_window_shrink, ple_window);
5709
5710 if (vmx->ple_window != old)
5711 vmx->ple_window_dirty = true;
7b46268d
RK		 5712
5713 trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
b4a2d31d
RK		 5714}
5715
5716/*
5717 * ple_window_actual_max is computed to be one grow_ple_window() below
5718 * ple_window_max. (See __grow_ple_window for the reason.)
5719 * This prevents overflows, because ple_window_max is int.
5720 * ple_window_max effectively rounded down to a multiple of ple_window_grow in
5721 * this process.
5722 * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
5723 */
5724static void update_ple_window_actual_max(void)
5725{
5726 ple_window_actual_max =
5727 __shrink_ple_window(max(ple_window_max, ple_window),
5728 ple_window_grow, INT_MIN);
5729}
5730
f2c7648d
TC		 5731static __init int hardware_setup(void)
5732{
34a1cd60
TC		 5733 int r = -ENOMEM, i, msr;
5734
5735 rdmsrl_safe(MSR_EFER, &host_efer);
5736
5737 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
5738 kvm_define_shared_msr(i, vmx_msr_index[i]);
5739
5740 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
5741 if (!vmx_io_bitmap_a)
5742 return r;
5743
5744 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
5745 if (!vmx_io_bitmap_b)
5746 goto out;
5747
5748 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
5749 if (!vmx_msr_bitmap_legacy)
5750 goto out1;
5751
5752 vmx_msr_bitmap_legacy_x2apic =
5753 (unsigned long *)__get_free_page(GFP_KERNEL);
5754 if (!vmx_msr_bitmap_legacy_x2apic)
5755 goto out2;
5756
5757 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
5758 if (!vmx_msr_bitmap_longmode)
5759 goto out3;
5760
5761 vmx_msr_bitmap_longmode_x2apic =
5762 (unsigned long *)__get_free_page(GFP_KERNEL);
5763 if (!vmx_msr_bitmap_longmode_x2apic)
5764 goto out4;
5765 vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
5766 if (!vmx_vmread_bitmap)
5767 goto out5;
5768
5769 vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
5770 if (!vmx_vmwrite_bitmap)
5771 goto out6;
5772
5773 memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
5774 memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
5775
5776 /*
5777 * Allow direct access to the PC debug port (it is often used for I/O
5778 * delays, but the vmexits simply slow things down).
5779 */
5780 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
5781 clear_bit(0x80, vmx_io_bitmap_a);
5782
5783 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
5784
5785 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
5786 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
5787
5788 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
5789 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
5790 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
5791 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
5792 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
5793 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
5794 vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true);
5795
5796 memcpy(vmx_msr_bitmap_legacy_x2apic,
5797 vmx_msr_bitmap_legacy, PAGE_SIZE);
5798 memcpy(vmx_msr_bitmap_longmode_x2apic,
5799 vmx_msr_bitmap_longmode, PAGE_SIZE);
5800
5801 if (enable_apicv) {
5802 for (msr = 0x800; msr <= 0x8ff; msr++)
5803 vmx_disable_intercept_msr_read_x2apic(msr);
5804
5805 /* According SDM, in x2apic mode, the whole id reg is used.
5806 * But in KVM, it only use the highest eight bits. Need to
5807 * intercept it */
5808 vmx_enable_intercept_msr_read_x2apic(0x802);
5809 /* TMCCT */
5810 vmx_enable_intercept_msr_read_x2apic(0x839);
5811 /* TPR */
5812 vmx_disable_intercept_msr_write_x2apic(0x808);
5813 /* EOI */
5814 vmx_disable_intercept_msr_write_x2apic(0x80b);
5815 /* SELF-IPI */
5816 vmx_disable_intercept_msr_write_x2apic(0x83f);
5817 }
5818
5819 if (enable_ept) {
5820 kvm_mmu_set_mask_ptes(0ull,
5821 (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
5822 (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
5823 0ull, VMX_EPT_EXECUTABLE_MASK);
5824 ept_set_mmio_spte_mask();
5825 kvm_enable_tdp();
5826 } else
5827 kvm_disable_tdp();
5828
5829 update_ple_window_actual_max();
5830
5831 if (setup_vmcs_config(&vmcs_config) < 0) {
5832 r = -EIO;
5833 goto out7;
5834 }
f2c7648d
TC		 5835
5836 if (boot_cpu_has(X86_FEATURE_NX))
5837 kvm_enable_efer_bits(EFER_NX);
5838
5839 if (!cpu_has_vmx_vpid())
5840 enable_vpid = 0;
5841 if (!cpu_has_vmx_shadow_vmcs())
5842 enable_shadow_vmcs = 0;
5843 if (enable_shadow_vmcs)
5844 init_vmcs_shadow_fields();
5845
5846 if (!cpu_has_vmx_ept() ||
5847 !cpu_has_vmx_ept_4levels()) {
5848 enable_ept = 0;
5849 enable_unrestricted_guest = 0;
5850 enable_ept_ad_bits = 0;
5851 }
5852
5853 if (!cpu_has_vmx_ept_ad_bits())
5854 enable_ept_ad_bits = 0;
5855
5856 if (!cpu_has_vmx_unrestricted_guest())
5857 enable_unrestricted_guest = 0;
5858
5859 if (!cpu_has_vmx_flexpriority()) {
5860 flexpriority_enabled = 0;
5861
5862 /*
5863 * set_apic_access_page_addr() is used to reload apic access
5864 * page upon invalidation. No need to do anything if the
5865 * processor does not have the APIC_ACCESS_ADDR VMCS field.
5866 */
5867 kvm_x86_ops->set_apic_access_page_addr = NULL;
5868 }
5869
5870 if (!cpu_has_vmx_tpr_shadow())
5871 kvm_x86_ops->update_cr8_intercept = NULL;
5872
5873 if (enable_ept && !cpu_has_vmx_ept_2m_page())
5874 kvm_disable_largepages();
5875
5876 if (!cpu_has_vmx_ple())
5877 ple_gap = 0;
5878
5879 if (!cpu_has_vmx_apicv())
5880 enable_apicv = 0;
5881
5882 if (enable_apicv)
5883 kvm_x86_ops->update_cr8_intercept = NULL;
5884 else {
5885 kvm_x86_ops->hwapic_irr_update = NULL;
5886 kvm_x86_ops->deliver_posted_interrupt = NULL;
5887 kvm_x86_ops->sync_pir_to_irr = vmx_sync_pir_to_irr_dummy;
5888 }
5889
5890 if (nested)
5891 nested_vmx_setup_ctls_msrs();
5892
5893 return alloc_kvm_area();
34a1cd60
TC		 5894
5895out7:
5896 free_page((unsigned long)vmx_vmwrite_bitmap);
5897out6:
5898 free_page((unsigned long)vmx_vmread_bitmap);
5899out5:
5900 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
5901out4:
5902 free_page((unsigned long)vmx_msr_bitmap_longmode);
5903out3:
5904 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
5905out2:
5906 free_page((unsigned long)vmx_msr_bitmap_legacy);
5907out1:
5908 free_page((unsigned long)vmx_io_bitmap_b);
5909out:
5910 free_page((unsigned long)vmx_io_bitmap_a);
5911
5912 return r;
f2c7648d
TC		 5913}
5914
5915static __exit void hardware_unsetup(void)
5916{
34a1cd60
TC		 5917 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
5918 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
5919 free_page((unsigned long)vmx_msr_bitmap_legacy);
5920 free_page((unsigned long)vmx_msr_bitmap_longmode);
5921 free_page((unsigned long)vmx_io_bitmap_b);
5922 free_page((unsigned long)vmx_io_bitmap_a);
5923 free_page((unsigned long)vmx_vmwrite_bitmap);
5924 free_page((unsigned long)vmx_vmread_bitmap);
5925
f2c7648d
TC		 5926 free_kvm_area();
5927}
5928
4b8d54f9
ZE		 5929/*
5930 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5931 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5932 */
9fb41ba8 5933static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9 5934{
b4a2d31d
RK		 5935 if (ple_gap)
5936 grow_ple_window(vcpu);
5937
4b8d54f9
ZE		 5938 skip_emulated_instruction(vcpu);
5939 kvm_vcpu_on_spin(vcpu);
5940
5941 return 1;
5942}
5943
87c00572 5944static int handle_nop(struct kvm_vcpu *vcpu)
59708670 5945{
87c00572 5946 skip_emulated_instruction(vcpu);
59708670
SY		 5947 return 1;
5948}
5949
87c00572
GS		 5950static int handle_mwait(struct kvm_vcpu *vcpu)
5951{
5952 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
5953 return handle_nop(vcpu);
5954}
5955
5956static int handle_monitor(struct kvm_vcpu *vcpu)
5957{
5958 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
5959 return handle_nop(vcpu);
5960}
5961
ff2f6fe9
NHE		 5962/*
5963 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
5964 * We could reuse a single VMCS for all the L2 guests, but we also want the
5965 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
5966 * allows keeping them loaded on the processor, and in the future will allow
5967 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
5968 * every entry if they never change.
5969 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
5970 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
5971 *
5972 * The following functions allocate and free a vmcs02 in this pool.
5973 */
5974
5975/* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
5976static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
5977{
5978 struct vmcs02_list *item;
5979 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5980 if (item->vmptr == vmx->nested.current_vmptr) {
5981 list_move(&item->list, &vmx->nested.vmcs02_pool);
5982 return &item->vmcs02;
5983 }
5984
5985 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
5986 /* Recycle the least recently used VMCS. */
5987 item = list_entry(vmx->nested.vmcs02_pool.prev,
5988 struct vmcs02_list, list);
5989 item->vmptr = vmx->nested.current_vmptr;
5990 list_move(&item->list, &vmx->nested.vmcs02_pool);
5991 return &item->vmcs02;
5992 }
5993
5994 /* Create a new VMCS */
0fa24ce3 5995 item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
ff2f6fe9
NHE		 5996 if (!item)
5997 return NULL;
5998 item->vmcs02.vmcs = alloc_vmcs();
5999 if (!item->vmcs02.vmcs) {
6000 kfree(item);
6001 return NULL;
6002 }
6003 loaded_vmcs_init(&item->vmcs02);
6004 item->vmptr = vmx->nested.current_vmptr;
6005 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
6006 vmx->nested.vmcs02_num++;
6007 return &item->vmcs02;
6008}
6009
6010/* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6011static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
6012{
6013 struct vmcs02_list *item;
6014 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6015 if (item->vmptr == vmptr) {
6016 free_loaded_vmcs(&item->vmcs02);
6017 list_del(&item->list);
6018 kfree(item);
6019 vmx->nested.vmcs02_num--;
6020 return;
6021 }
6022}
6023
6024/*
6025 * Free all VMCSs saved for this vcpu, except the one pointed by
4fa7734c
PB		 6026 * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6027 * must be &vmx->vmcs01.
ff2f6fe9
NHE		 6028 */
6029static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
6030{
6031 struct vmcs02_list *item, *n;
4fa7734c
PB		 6032
6033 WARN_ON(vmx->loaded_vmcs != &vmx->vmcs01);
ff2f6fe9 6034 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
4fa7734c
PB		 6035 /*
6036 * Something will leak if the above WARN triggers. Better than
6037 * a use-after-free.
6038 */
6039 if (vmx->loaded_vmcs == &item->vmcs02)
6040 continue;
6041
6042 free_loaded_vmcs(&item->vmcs02);
ff2f6fe9
NHE		 6043 list_del(&item->list);
6044 kfree(item);
4fa7734c 6045 vmx->nested.vmcs02_num--;
ff2f6fe9 6046 }
ff2f6fe9
NHE		 6047}
6048
0658fbaa
ACL		 6049/*
6050 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6051 * set the success or error code of an emulated VMX instruction, as specified
6052 * by Vol 2B, VMX Instruction Reference, "Conventions".
6053 */
6054static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
6055{
6056 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
6057 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6058 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
6059}
6060
6061static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
6062{
6063 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6064 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
6065 X86_EFLAGS_SF | X86_EFLAGS_OF))
6066 | X86_EFLAGS_CF);
6067}
6068
145c28dd 6069static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
0658fbaa
ACL		 6070 u32 vm_instruction_error)
6071{
6072 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
6073 /*
6074 * failValid writes the error number to the current VMCS, which
6075 * can't be done there isn't a current VMCS.
6076 */
6077 nested_vmx_failInvalid(vcpu);
6078 return;
6079 }
6080 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6081 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6082 X86_EFLAGS_SF | X86_EFLAGS_OF))
6083 | X86_EFLAGS_ZF);
6084 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
6085 /*
6086 * We don't need to force a shadow sync because
6087 * VM_INSTRUCTION_ERROR is not shadowed
6088 */
6089}
145c28dd 6090
f4124500
JK		 6091static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
6092{
6093 struct vcpu_vmx *vmx =
6094 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
6095
6096 vmx->nested.preemption_timer_expired = true;
6097 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6098 kvm_vcpu_kick(&vmx->vcpu);
6099
6100 return HRTIMER_NORESTART;
6101}
6102
19677e32
BD		 6103/*
6104 * Decode the memory-address operand of a vmx instruction, as recorded on an
6105 * exit caused by such an instruction (run by a guest hypervisor).
6106 * On success, returns 0. When the operand is invalid, returns 1 and throws
6107 * #UD or #GP.
6108 */
6109static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
6110 unsigned long exit_qualification,
6111 u32 vmx_instruction_info, gva_t *ret)
6112{
6113 /*
6114 * According to Vol. 3B, "Information for VM Exits Due to Instruction
6115 * Execution", on an exit, vmx_instruction_info holds most of the
6116 * addressing components of the operand. Only the displacement part
6117 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6118 * For how an actual address is calculated from all these components,
6119 * refer to Vol. 1, "Operand Addressing".
6120 */
6121 int scaling = vmx_instruction_info & 3;
6122 int addr_size = (vmx_instruction_info >> 7) & 7;
6123 bool is_reg = vmx_instruction_info & (1u << 10);
6124 int seg_reg = (vmx_instruction_info >> 15) & 7;
6125 int index_reg = (vmx_instruction_info >> 18) & 0xf;
6126 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
6127 int base_reg = (vmx_instruction_info >> 23) & 0xf;
6128 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
6129
6130 if (is_reg) {
6131 kvm_queue_exception(vcpu, UD_VECTOR);
6132 return 1;
6133 }
6134
6135 /* Addr = segment_base + offset */
6136 /* offset = base + [index * scale] + displacement */
6137 *ret = vmx_get_segment_base(vcpu, seg_reg);
6138 if (base_is_valid)
6139 *ret += kvm_register_read(vcpu, base_reg);
6140 if (index_is_valid)
6141 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
6142 *ret += exit_qualification; /* holds the displacement */
6143
6144 if (addr_size == 1) /* 32 bit */
6145 *ret &= 0xffffffff;
6146
6147 /*
6148 * TODO: throw #GP (and return 1) in various cases that the VM*
6149 * instructions require it - e.g., offset beyond segment limit,
6150 * unusable or unreadable/unwritable segment, non-canonical 64-bit
6151 * address, and so on. Currently these are not checked.
6152 */
6153 return 0;
6154}
6155
3573e22c
BD		 6156/*
6157 * This function performs the various checks including
6158 * - if it's 4KB aligned
6159 * - No bits beyond the physical address width are set
6160 * - Returns 0 on success or else 1
4291b588 6161 * (Intel SDM Section 30.3)
3573e22c 6162 */
4291b588
BD		 6163static int nested_vmx_check_vmptr(struct kvm_vcpu *vcpu, int exit_reason,
6164 gpa_t *vmpointer)
3573e22c
BD		 6165{
6166 gva_t gva;
6167 gpa_t vmptr;
6168 struct x86_exception e;
6169 struct page *page;
6170 struct vcpu_vmx *vmx = to_vmx(vcpu);
6171 int maxphyaddr = cpuid_maxphyaddr(vcpu);
6172
6173 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6174 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
6175 return 1;
6176
6177 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6178 sizeof(vmptr), &e)) {
6179 kvm_inject_page_fault(vcpu, &e);
6180 return 1;
6181 }
6182
6183 switch (exit_reason) {
6184 case EXIT_REASON_VMON:
6185 /*
6186 * SDM 3: 24.11.5
6187 * The first 4 bytes of VMXON region contain the supported
6188 * VMCS revision identifier
6189 *
6190 * Note - IA32_VMX_BASIC[48] will never be 1
6191 * for the nested case;
6192 * which replaces physical address width with 32
6193 *
6194 */
bc39c4db 6195 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
3573e22c
BD		 6196 nested_vmx_failInvalid(vcpu);
6197 skip_emulated_instruction(vcpu);
6198 return 1;
6199 }
6200
6201 page = nested_get_page(vcpu, vmptr);
6202 if (page == NULL ||
6203 *(u32 *)kmap(page) != VMCS12_REVISION) {
6204 nested_vmx_failInvalid(vcpu);
6205 kunmap(page);
6206 skip_emulated_instruction(vcpu);
6207 return 1;
6208 }
6209 kunmap(page);
6210 vmx->nested.vmxon_ptr = vmptr;
6211 break;
4291b588 6212 case EXIT_REASON_VMCLEAR:
bc39c4db 6213 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
4291b588
BD		 6214 nested_vmx_failValid(vcpu,
6215 VMXERR_VMCLEAR_INVALID_ADDRESS);
6216 skip_emulated_instruction(vcpu);
6217 return 1;
6218 }
6219
6220 if (vmptr == vmx->nested.vmxon_ptr) {
6221 nested_vmx_failValid(vcpu,
6222 VMXERR_VMCLEAR_VMXON_POINTER);
6223 skip_emulated_instruction(vcpu);
6224 return 1;
6225 }
6226 break;
6227 case EXIT_REASON_VMPTRLD:
bc39c4db 6228 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
4291b588
BD		 6229 nested_vmx_failValid(vcpu,
6230 VMXERR_VMPTRLD_INVALID_ADDRESS);
6231 skip_emulated_instruction(vcpu);
6232 return 1;
6233 }
3573e22c 6234
4291b588
BD		 6235 if (vmptr == vmx->nested.vmxon_ptr) {
6236 nested_vmx_failValid(vcpu,
6237 VMXERR_VMCLEAR_VMXON_POINTER);
6238 skip_emulated_instruction(vcpu);
6239 return 1;
6240 }
6241 break;
3573e22c
BD		 6242 default:
6243 return 1; /* shouldn't happen */
6244 }
6245
4291b588
BD		 6246 if (vmpointer)
6247 *vmpointer = vmptr;
3573e22c
BD		 6248 return 0;
6249}
6250
ec378aee
NHE		 6251/*
6252 * Emulate the VMXON instruction.
6253 * Currently, we just remember that VMX is active, and do not save or even
6254 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
6255 * do not currently need to store anything in that guest-allocated memory
6256 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
6257 * argument is different from the VMXON pointer (which the spec says they do).
6258 */
6259static int handle_vmon(struct kvm_vcpu *vcpu)
6260{
6261 struct kvm_segment cs;
6262 struct vcpu_vmx *vmx = to_vmx(vcpu);
8de48833 6263 struct vmcs *shadow_vmcs;
b3897a49
NHE		 6264 const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
6265 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
ec378aee
NHE		 6266
6267 /* The Intel VMX Instruction Reference lists a bunch of bits that
6268 * are prerequisite to running VMXON, most notably cr4.VMXE must be
6269 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
6270 * Otherwise, we should fail with #UD. We test these now:
6271 */
6272 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
6273 !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
6274 (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
6275 kvm_queue_exception(vcpu, UD_VECTOR);
6276 return 1;
6277 }
6278
6279 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6280 if (is_long_mode(vcpu) && !cs.l) {
6281 kvm_queue_exception(vcpu, UD_VECTOR);
6282 return 1;
6283 }
6284
6285 if (vmx_get_cpl(vcpu)) {
6286 kvm_inject_gp(vcpu, 0);
6287 return 1;
6288 }
3573e22c 6289
4291b588 6290 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMON, NULL))
3573e22c
BD		 6291 return 1;
6292
145c28dd
AG		 6293 if (vmx->nested.vmxon) {
6294 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
6295 skip_emulated_instruction(vcpu);
6296 return 1;
6297 }
b3897a49
NHE		 6298
6299 if ((vmx->nested.msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
6300 != VMXON_NEEDED_FEATURES) {
6301 kvm_inject_gp(vcpu, 0);
6302 return 1;
6303 }
6304
8de48833
AG		 6305 if (enable_shadow_vmcs) {
6306 shadow_vmcs = alloc_vmcs();
6307 if (!shadow_vmcs)
6308 return -ENOMEM;
6309 /* mark vmcs as shadow */
6310 shadow_vmcs->revision_id |= (1u << 31);
6311 /* init shadow vmcs */
6312 vmcs_clear(shadow_vmcs);
6313 vmx->nested.current_shadow_vmcs = shadow_vmcs;
6314 }
ec378aee 6315
ff2f6fe9
NHE		 6316 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
6317 vmx->nested.vmcs02_num = 0;
6318
f4124500
JK		 6319 hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
6320 HRTIMER_MODE_REL);
6321 vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
6322
ec378aee
NHE		 6323 vmx->nested.vmxon = true;
6324
6325 skip_emulated_instruction(vcpu);
a25eb114 6326 nested_vmx_succeed(vcpu);
ec378aee
NHE		 6327 return 1;
6328}
6329
6330/*
6331 * Intel's VMX Instruction Reference specifies a common set of prerequisites
6332 * for running VMX instructions (except VMXON, whose prerequisites are
6333 * slightly different). It also specifies what exception to inject otherwise.
6334 */
6335static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
6336{
6337 struct kvm_segment cs;
6338 struct vcpu_vmx *vmx = to_vmx(vcpu);
6339
6340 if (!vmx->nested.vmxon) {
6341 kvm_queue_exception(vcpu, UD_VECTOR);
6342 return 0;
6343 }
6344
6345 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6346 if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
6347 (is_long_mode(vcpu) && !cs.l)) {
6348 kvm_queue_exception(vcpu, UD_VECTOR);
6349 return 0;
6350 }
6351
6352 if (vmx_get_cpl(vcpu)) {
6353 kvm_inject_gp(vcpu, 0);
6354 return 0;
6355 }
6356
6357 return 1;
6358}
6359
e7953d7f
AG		 6360static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
6361{
8a1b9dd0 6362 u32 exec_control;
9a2a05b9
PB		 6363 if (vmx->nested.current_vmptr == -1ull)
6364 return;
6365
6366 /* current_vmptr and current_vmcs12 are always set/reset together */
6367 if (WARN_ON(vmx->nested.current_vmcs12 == NULL))
6368 return;
6369
012f83cb 6370 if (enable_shadow_vmcs) {
9a2a05b9
PB		 6371 /* copy to memory all shadowed fields in case
6372 they were modified */
6373 copy_shadow_to_vmcs12(vmx);
6374 vmx->nested.sync_shadow_vmcs = false;
6375 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6376 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
6377 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6378 vmcs_write64(VMCS_LINK_POINTER, -1ull);
012f83cb 6379 }
e7953d7f
AG		 6380 kunmap(vmx->nested.current_vmcs12_page);
6381 nested_release_page(vmx->nested.current_vmcs12_page);
9a2a05b9
PB		 6382 vmx->nested.current_vmptr = -1ull;
6383 vmx->nested.current_vmcs12 = NULL;
e7953d7f
AG		 6384}
6385
ec378aee
NHE		 6386/*
6387 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
6388 * just stops using VMX.
6389 */
6390static void free_nested(struct vcpu_vmx *vmx)
6391{
6392 if (!vmx->nested.vmxon)
6393 return;
9a2a05b9 6394
ec378aee 6395 vmx->nested.vmxon = false;
9a2a05b9 6396 nested_release_vmcs12(vmx);
e7953d7f
AG		 6397 if (enable_shadow_vmcs)
6398 free_vmcs(vmx->nested.current_shadow_vmcs);
fe3ef05c
NHE		 6399 /* Unpin physical memory we referred to in current vmcs02 */
6400 if (vmx->nested.apic_access_page) {
6401 nested_release_page(vmx->nested.apic_access_page);
48d89b92 6402 vmx->nested.apic_access_page = NULL;
fe3ef05c 6403 }
a7c0b07d
WL		 6404 if (vmx->nested.virtual_apic_page) {
6405 nested_release_page(vmx->nested.virtual_apic_page);
48d89b92 6406 vmx->nested.virtual_apic_page = NULL;
a7c0b07d 6407 }
ff2f6fe9
NHE		 6408
6409 nested_free_all_saved_vmcss(vmx);
ec378aee
NHE		 6410}
6411
6412/* Emulate the VMXOFF instruction */
6413static int handle_vmoff(struct kvm_vcpu *vcpu)
6414{
6415 if (!nested_vmx_check_permission(vcpu))
6416 return 1;
6417 free_nested(to_vmx(vcpu));
6418 skip_emulated_instruction(vcpu);
a25eb114 6419 nested_vmx_succeed(vcpu);
ec378aee
NHE		 6420 return 1;
6421}
6422
27d6c865
NHE		 6423/* Emulate the VMCLEAR instruction */
6424static int handle_vmclear(struct kvm_vcpu *vcpu)
6425{
6426 struct vcpu_vmx *vmx = to_vmx(vcpu);
27d6c865
NHE		 6427 gpa_t vmptr;
6428 struct vmcs12 *vmcs12;
6429 struct page *page;
27d6c865
NHE		 6430
6431 if (!nested_vmx_check_permission(vcpu))
6432 return 1;
6433
4291b588 6434 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMCLEAR, &vmptr))
27d6c865 6435 return 1;
27d6c865 6436
9a2a05b9 6437 if (vmptr == vmx->nested.current_vmptr)
e7953d7f 6438 nested_release_vmcs12(vmx);
27d6c865
NHE		 6439
6440 page = nested_get_page(vcpu, vmptr);
6441 if (page == NULL) {
6442 /*
6443 * For accurate processor emulation, VMCLEAR beyond available
6444 * physical memory should do nothing at all. However, it is
6445 * possible that a nested vmx bug, not a guest hypervisor bug,
6446 * resulted in this case, so let's shut down before doing any
6447 * more damage:
6448 */
6449 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6450 return 1;
6451 }
6452 vmcs12 = kmap(page);
6453 vmcs12->launch_state = 0;
6454 kunmap(page);
6455 nested_release_page(page);
6456
6457 nested_free_vmcs02(vmx, vmptr);
6458
6459 skip_emulated_instruction(vcpu);
6460 nested_vmx_succeed(vcpu);
6461 return 1;
6462}
6463
cd232ad0
NHE		 6464static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
6465
6466/* Emulate the VMLAUNCH instruction */
6467static int handle_vmlaunch(struct kvm_vcpu *vcpu)
6468{
6469 return nested_vmx_run(vcpu, true);
6470}
6471
6472/* Emulate the VMRESUME instruction */
6473static int handle_vmresume(struct kvm_vcpu *vcpu)
6474{
6475
6476 return nested_vmx_run(vcpu, false);
6477}
6478
49f705c5
NHE		 6479enum vmcs_field_type {
6480 VMCS_FIELD_TYPE_U16 = 0,
6481 VMCS_FIELD_TYPE_U64 = 1,
6482 VMCS_FIELD_TYPE_U32 = 2,
6483 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
6484};
6485
6486static inline int vmcs_field_type(unsigned long field)
6487{
6488 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
6489 return VMCS_FIELD_TYPE_U32;
6490 return (field >> 13) & 0x3 ;
6491}
6492
6493static inline int vmcs_field_readonly(unsigned long field)
6494{
6495 return (((field >> 10) & 0x3) == 1);
6496}
6497
6498/*
6499 * Read a vmcs12 field. Since these can have varying lengths and we return
6500 * one type, we chose the biggest type (u64) and zero-extend the return value
6501 * to that size. Note that the caller, handle_vmread, might need to use only
6502 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
6503 * 64-bit fields are to be returned).
6504 */
a2ae9df7
PB		 6505static inline int vmcs12_read_any(struct kvm_vcpu *vcpu,
6506 unsigned long field, u64 *ret)
49f705c5
NHE		 6507{
6508 short offset = vmcs_field_to_offset(field);
6509 char *p;
6510
6511 if (offset < 0)
a2ae9df7 6512 return offset;
49f705c5
NHE		 6513
6514 p = ((char *)(get_vmcs12(vcpu))) + offset;
6515
6516 switch (vmcs_field_type(field)) {
6517 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6518 *ret = *((natural_width *)p);
a2ae9df7 6519 return 0;
49f705c5
NHE		 6520 case VMCS_FIELD_TYPE_U16:
6521 *ret = *((u16 *)p);
a2ae9df7 6522 return 0;
49f705c5
NHE		 6523 case VMCS_FIELD_TYPE_U32:
6524 *ret = *((u32 *)p);
a2ae9df7 6525 return 0;
49f705c5
NHE		 6526 case VMCS_FIELD_TYPE_U64:
6527 *ret = *((u64 *)p);
a2ae9df7 6528 return 0;
49f705c5 6529 default:
a2ae9df7
PB		 6530 WARN_ON(1);
6531 return -ENOENT;
49f705c5
NHE		 6532 }
6533}
6534
20b97fea 6535
a2ae9df7
PB		 6536static inline int vmcs12_write_any(struct kvm_vcpu *vcpu,
6537 unsigned long field, u64 field_value){
20b97fea
AG		 6538 short offset = vmcs_field_to_offset(field);
6539 char *p = ((char *) get_vmcs12(vcpu)) + offset;
6540 if (offset < 0)
a2ae9df7 6541 return offset;
20b97fea
AG		 6542
6543 switch (vmcs_field_type(field)) {
6544 case VMCS_FIELD_TYPE_U16:
6545 *(u16 *)p = field_value;
a2ae9df7 6546 return 0;
20b97fea
AG		 6547 case VMCS_FIELD_TYPE_U32:
6548 *(u32 *)p = field_value;
a2ae9df7 6549 return 0;
20b97fea
AG		 6550 case VMCS_FIELD_TYPE_U64:
6551 *(u64 *)p = field_value;
a2ae9df7 6552 return 0;
20b97fea
AG		 6553 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6554 *(natural_width *)p = field_value;
a2ae9df7 6555 return 0;
20b97fea 6556 default:
a2ae9df7
PB		 6557 WARN_ON(1);
6558 return -ENOENT;
20b97fea
AG		 6559 }
6560
6561}
6562
16f5b903
AG		 6563static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
6564{
6565 int i;
6566 unsigned long field;
6567 u64 field_value;
6568 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
c2bae893
MK		 6569 const unsigned long *fields = shadow_read_write_fields;
6570 const int num_fields = max_shadow_read_write_fields;
16f5b903 6571
282da870
JK		 6572 preempt_disable();
6573
16f5b903
AG		 6574 vmcs_load(shadow_vmcs);
6575
6576 for (i = 0; i < num_fields; i++) {
6577 field = fields[i];
6578 switch (vmcs_field_type(field)) {
6579 case VMCS_FIELD_TYPE_U16:
6580 field_value = vmcs_read16(field);
6581 break;
6582 case VMCS_FIELD_TYPE_U32:
6583 field_value = vmcs_read32(field);
6584 break;
6585 case VMCS_FIELD_TYPE_U64:
6586 field_value = vmcs_read64(field);
6587 break;
6588 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6589 field_value = vmcs_readl(field);
6590 break;
a2ae9df7
PB		 6591 default:
6592 WARN_ON(1);
6593 continue;
16f5b903
AG		 6594 }
6595 vmcs12_write_any(&vmx->vcpu, field, field_value);
6596 }
6597
6598 vmcs_clear(shadow_vmcs);
6599 vmcs_load(vmx->loaded_vmcs->vmcs);
282da870
JK		 6600
6601 preempt_enable();
16f5b903
AG		 6602}
6603
c3114420
AG		 6604static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
6605{
c2bae893
MK		 6606 const unsigned long *fields[] = {
6607 shadow_read_write_fields,
6608 shadow_read_only_fields
c3114420 6609 };
c2bae893 6610 const int max_fields[] = {
c3114420
AG		 6611 max_shadow_read_write_fields,
6612 max_shadow_read_only_fields
6613 };
6614 int i, q;
6615 unsigned long field;
6616 u64 field_value = 0;
6617 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
6618
6619 vmcs_load(shadow_vmcs);
6620
c2bae893 6621 for (q = 0; q < ARRAY_SIZE(fields); q++) {
c3114420
AG		 6622 for (i = 0; i < max_fields[q]; i++) {
6623 field = fields[q][i];
6624 vmcs12_read_any(&vmx->vcpu, field, &field_value);
6625
6626 switch (vmcs_field_type(field)) {
6627 case VMCS_FIELD_TYPE_U16:
6628 vmcs_write16(field, (u16)field_value);
6629 break;
6630 case VMCS_FIELD_TYPE_U32:
6631 vmcs_write32(field, (u32)field_value);
6632 break;
6633 case VMCS_FIELD_TYPE_U64:
6634 vmcs_write64(field, (u64)field_value);
6635 break;
6636 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6637 vmcs_writel(field, (long)field_value);
6638 break;
a2ae9df7
PB		 6639 default:
6640 WARN_ON(1);
6641 break;
c3114420
AG		 6642 }
6643 }
6644 }
6645
6646 vmcs_clear(shadow_vmcs);
6647 vmcs_load(vmx->loaded_vmcs->vmcs);
6648}
6649
49f705c5
NHE		 6650/*
6651 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
6652 * used before) all generate the same failure when it is missing.
6653 */
6654static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
6655{
6656 struct vcpu_vmx *vmx = to_vmx(vcpu);
6657 if (vmx->nested.current_vmptr == -1ull) {
6658 nested_vmx_failInvalid(vcpu);
6659 skip_emulated_instruction(vcpu);
6660 return 0;
6661 }
6662 return 1;
6663}
6664
6665static int handle_vmread(struct kvm_vcpu *vcpu)
6666{
6667 unsigned long field;
6668 u64 field_value;
6669 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6670 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6671 gva_t gva = 0;
6672
6673 if (!nested_vmx_check_permission(vcpu) ||
6674 !nested_vmx_check_vmcs12(vcpu))
6675 return 1;
6676
6677 /* Decode instruction info and find the field to read */
27e6fb5d 6678 field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
49f705c5 6679 /* Read the field, zero-extended to a u64 field_value */
a2ae9df7 6680 if (vmcs12_read_any(vcpu, field, &field_value) < 0) {
49f705c5
NHE		 6681 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6682 skip_emulated_instruction(vcpu);
6683 return 1;
6684 }
6685 /*
6686 * Now copy part of this value to register or memory, as requested.
6687 * Note that the number of bits actually copied is 32 or 64 depending
6688 * on the guest's mode (32 or 64 bit), not on the given field's length.
6689 */
6690 if (vmx_instruction_info & (1u << 10)) {
27e6fb5d 6691 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
49f705c5
NHE		 6692 field_value);
6693 } else {
6694 if (get_vmx_mem_address(vcpu, exit_qualification,
6695 vmx_instruction_info, &gva))
6696 return 1;
6697 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
6698 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
6699 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
6700 }
6701
6702 nested_vmx_succeed(vcpu);
6703 skip_emulated_instruction(vcpu);
6704 return 1;
6705}
6706
6707
6708static int handle_vmwrite(struct kvm_vcpu *vcpu)
6709{
6710 unsigned long field;
6711 gva_t gva;
6712 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6713 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
49f705c5
NHE		 6714 /* The value to write might be 32 or 64 bits, depending on L1's long
6715 * mode, and eventually we need to write that into a field of several
6716 * possible lengths. The code below first zero-extends the value to 64
6717 * bit (field_value), and then copies only the approriate number of
6718 * bits into the vmcs12 field.
6719 */
6720 u64 field_value = 0;
6721 struct x86_exception e;
6722
6723 if (!nested_vmx_check_permission(vcpu) ||
6724 !nested_vmx_check_vmcs12(vcpu))
6725 return 1;
6726
6727 if (vmx_instruction_info & (1u << 10))
27e6fb5d 6728 field_value = kvm_register_readl(vcpu,
49f705c5
NHE		 6729 (((vmx_instruction_info) >> 3) & 0xf));
6730 else {
6731 if (get_vmx_mem_address(vcpu, exit_qualification,
6732 vmx_instruction_info, &gva))
6733 return 1;
6734 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
27e6fb5d 6735 &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
49f705c5
NHE		 6736 kvm_inject_page_fault(vcpu, &e);
6737 return 1;
6738 }
6739 }
6740
6741
27e6fb5d 6742 field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
49f705c5
NHE		 6743 if (vmcs_field_readonly(field)) {
6744 nested_vmx_failValid(vcpu,
6745 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
6746 skip_emulated_instruction(vcpu);
6747 return 1;
6748 }
6749
a2ae9df7 6750 if (vmcs12_write_any(vcpu, field, field_value) < 0) {
49f705c5
NHE		 6751 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6752 skip_emulated_instruction(vcpu);
6753 return 1;
6754 }
6755
6756 nested_vmx_succeed(vcpu);
6757 skip_emulated_instruction(vcpu);
6758 return 1;
6759}
6760
63846663
NHE		 6761/* Emulate the VMPTRLD instruction */
6762static int handle_vmptrld(struct kvm_vcpu *vcpu)
6763{
6764 struct vcpu_vmx *vmx = to_vmx(vcpu);
63846663 6765 gpa_t vmptr;
8a1b9dd0 6766 u32 exec_control;
63846663
NHE		 6767
6768 if (!nested_vmx_check_permission(vcpu))
6769 return 1;
6770
4291b588 6771 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMPTRLD, &vmptr))
63846663 6772 return 1;
63846663
NHE		 6773
6774 if (vmx->nested.current_vmptr != vmptr) {
6775 struct vmcs12 *new_vmcs12;
6776 struct page *page;
6777 page = nested_get_page(vcpu, vmptr);
6778 if (page == NULL) {
6779 nested_vmx_failInvalid(vcpu);
6780 skip_emulated_instruction(vcpu);
6781 return 1;
6782 }
6783 new_vmcs12 = kmap(page);
6784 if (new_vmcs12->revision_id != VMCS12_REVISION) {
6785 kunmap(page);
6786 nested_release_page_clean(page);
6787 nested_vmx_failValid(vcpu,
6788 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
6789 skip_emulated_instruction(vcpu);
6790 return 1;
6791 }
63846663 6792
9a2a05b9 6793 nested_release_vmcs12(vmx);
63846663
NHE		 6794 vmx->nested.current_vmptr = vmptr;
6795 vmx->nested.current_vmcs12 = new_vmcs12;
6796 vmx->nested.current_vmcs12_page = page;
012f83cb 6797 if (enable_shadow_vmcs) {
8a1b9dd0
AG		 6798 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6799 exec_control |= SECONDARY_EXEC_SHADOW_VMCS;
6800 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6801 vmcs_write64(VMCS_LINK_POINTER,
6802 __pa(vmx->nested.current_shadow_vmcs));
012f83cb
AG		 6803 vmx->nested.sync_shadow_vmcs = true;
6804 }
63846663
NHE		 6805 }
6806
6807 nested_vmx_succeed(vcpu);
6808 skip_emulated_instruction(vcpu);
6809 return 1;
6810}
6811
6a4d7550
NHE		 6812/* Emulate the VMPTRST instruction */
6813static int handle_vmptrst(struct kvm_vcpu *vcpu)
6814{
6815 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6816 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6817 gva_t vmcs_gva;
6818 struct x86_exception e;
6819
6820 if (!nested_vmx_check_permission(vcpu))
6821 return 1;
6822
6823 if (get_vmx_mem_address(vcpu, exit_qualification,
6824 vmx_instruction_info, &vmcs_gva))
6825 return 1;
6826 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
6827 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
6828 (void *)&to_vmx(vcpu)->nested.current_vmptr,
6829 sizeof(u64), &e)) {
6830 kvm_inject_page_fault(vcpu, &e);
6831 return 1;
6832 }
6833 nested_vmx_succeed(vcpu);
6834 skip_emulated_instruction(vcpu);
6835 return 1;
6836}
6837
bfd0a56b
NHE		 6838/* Emulate the INVEPT instruction */
6839static int handle_invept(struct kvm_vcpu *vcpu)
6840{
6841 u32 vmx_instruction_info, types;
6842 unsigned long type;
6843 gva_t gva;
6844 struct x86_exception e;
6845 struct {
6846 u64 eptp, gpa;
6847 } operand;
bfd0a56b
NHE		 6848
6849 if (!(nested_vmx_secondary_ctls_high & SECONDARY_EXEC_ENABLE_EPT) ||
6850 !(nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
6851 kvm_queue_exception(vcpu, UD_VECTOR);
6852 return 1;
6853 }
6854
6855 if (!nested_vmx_check_permission(vcpu))
6856 return 1;
6857
6858 if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
6859 kvm_queue_exception(vcpu, UD_VECTOR);
6860 return 1;
6861 }
6862
6863 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
27e6fb5d 6864 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
bfd0a56b
NHE		 6865
6866 types = (nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
6867
6868 if (!(types & (1UL << type))) {
6869 nested_vmx_failValid(vcpu,
6870 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
6871 return 1;
6872 }
6873
6874 /* According to the Intel VMX instruction reference, the memory
6875 * operand is read even if it isn't needed (e.g., for type==global)
6876 */
6877 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6878 vmx_instruction_info, &gva))
6879 return 1;
6880 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
6881 sizeof(operand), &e)) {
6882 kvm_inject_page_fault(vcpu, &e);
6883 return 1;
6884 }
6885
6886 switch (type) {
bfd0a56b
NHE		 6887 case VMX_EPT_EXTENT_GLOBAL:
6888 kvm_mmu_sync_roots(vcpu);
77c3913b 6889 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
bfd0a56b
NHE		 6890 nested_vmx_succeed(vcpu);
6891 break;
6892 default:
4b855078 6893 /* Trap single context invalidation invept calls */
bfd0a56b
NHE		 6894 BUG_ON(1);
6895 break;
6896 }
6897
6898 skip_emulated_instruction(vcpu);
6899 return 1;
6900}
6901
a642fc30
PM		 6902static int handle_invvpid(struct kvm_vcpu *vcpu)
6903{
6904 kvm_queue_exception(vcpu, UD_VECTOR);
6905 return 1;
6906}
6907
6aa8b732
AK		 6908/*
6909 * The exit handlers return 1 if the exit was handled fully and guest execution
6910 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
6911 * to be done to userspace and return 0.
6912 */
772e0318 6913static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK		 6914 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
6915 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 6916 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 6917 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 6918 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 6919 [EXIT_REASON_CR_ACCESS] = handle_cr,
6920 [EXIT_REASON_DR_ACCESS] = handle_dr,
6921 [EXIT_REASON_CPUID] = handle_cpuid,
6922 [EXIT_REASON_MSR_READ] = handle_rdmsr,
6923 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
6924 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
6925 [EXIT_REASON_HLT] = handle_halt,
ec25d5e6 6926 [EXIT_REASON_INVD] = handle_invd,
a7052897 6927 [EXIT_REASON_INVLPG] = handle_invlpg,
fee84b07 6928 [EXIT_REASON_RDPMC] = handle_rdpmc,
c21415e8 6929 [EXIT_REASON_VMCALL] = handle_vmcall,
27d6c865 6930 [EXIT_REASON_VMCLEAR] = handle_vmclear,
cd232ad0 6931 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
63846663 6932 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
6a4d7550 6933 [EXIT_REASON_VMPTRST] = handle_vmptrst,
49f705c5 6934 [EXIT_REASON_VMREAD] = handle_vmread,
cd232ad0 6935 [EXIT_REASON_VMRESUME] = handle_vmresume,
49f705c5 6936 [EXIT_REASON_VMWRITE] = handle_vmwrite,
ec378aee
NHE		 6937 [EXIT_REASON_VMOFF] = handle_vmoff,
6938 [EXIT_REASON_VMON] = handle_vmon,
f78e0e2e
SY		 6939 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
6940 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
83d4c286 6941 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
c7c9c56c 6942 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
e5edaa01 6943 [EXIT_REASON_WBINVD] = handle_wbinvd,
2acf923e 6944 [EXIT_REASON_XSETBV] = handle_xsetbv,
37817f29 6945 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 6946 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT		 6947 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
6948 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 6949 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
87c00572
GS		 6950 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_mwait,
6951 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_monitor,
bfd0a56b 6952 [EXIT_REASON_INVEPT] = handle_invept,
a642fc30 6953 [EXIT_REASON_INVVPID] = handle_invvpid,
6aa8b732
AK		 6954};
6955
6956static const int kvm_vmx_max_exit_handlers =
50a3485c 6957 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732 6958
908a7bdd
JK		 6959static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
6960 struct vmcs12 *vmcs12)
6961{
6962 unsigned long exit_qualification;
6963 gpa_t bitmap, last_bitmap;
6964 unsigned int port;
6965 int size;
6966 u8 b;
6967
908a7bdd 6968 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
2f0a6397 6969 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
908a7bdd
JK		 6970
6971 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6972
6973 port = exit_qualification >> 16;
6974 size = (exit_qualification & 7) + 1;
6975
6976 last_bitmap = (gpa_t)-1;
6977 b = -1;
6978
6979 while (size > 0) {
6980 if (port < 0x8000)
6981 bitmap = vmcs12->io_bitmap_a;
6982 else if (port < 0x10000)
6983 bitmap = vmcs12->io_bitmap_b;
6984 else
6985 return 1;
6986 bitmap += (port & 0x7fff) / 8;
6987
6988 if (last_bitmap != bitmap)
6989 if (kvm_read_guest(vcpu->kvm, bitmap, &b, 1))
6990 return 1;
6991 if (b & (1 << (port & 7)))
6992 return 1;
6993
6994 port++;
6995 size--;
6996 last_bitmap = bitmap;
6997 }
6998
6999 return 0;
7000}
7001
644d711a
NHE		 7002/*
7003 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
7004 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
7005 * disinterest in the current event (read or write a specific MSR) by using an
7006 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
7007 */
7008static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
7009 struct vmcs12 *vmcs12, u32 exit_reason)
7010{
7011 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
7012 gpa_t bitmap;
7013
cbd29cb6 7014 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
644d711a
NHE		 7015 return 1;
7016
7017 /*
7018 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
7019 * for the four combinations of read/write and low/high MSR numbers.
7020 * First we need to figure out which of the four to use:
7021 */
7022 bitmap = vmcs12->msr_bitmap;
7023 if (exit_reason == EXIT_REASON_MSR_WRITE)
7024 bitmap += 2048;
7025 if (msr_index >= 0xc0000000) {
7026 msr_index -= 0xc0000000;
7027 bitmap += 1024;
7028 }
7029
7030 /* Then read the msr_index'th bit from this bitmap: */
7031 if (msr_index < 1024*8) {
7032 unsigned char b;
bd31a7f5
JK		 7033 if (kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1))
7034 return 1;
644d711a
NHE		 7035 return 1 & (b >> (msr_index & 7));
7036 } else
7037 return 1; /* let L1 handle the wrong parameter */
7038}
7039
7040/*
7041 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
7042 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
7043 * intercept (via guest_host_mask etc.) the current event.
7044 */
7045static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
7046 struct vmcs12 *vmcs12)
7047{
7048 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7049 int cr = exit_qualification & 15;
7050 int reg = (exit_qualification >> 8) & 15;
1e32c079 7051 unsigned long val = kvm_register_readl(vcpu, reg);
644d711a
NHE		 7052
7053 switch ((exit_qualification >> 4) & 3) {
7054 case 0: /* mov to cr */
7055 switch (cr) {
7056 case 0:
7057 if (vmcs12->cr0_guest_host_mask &
7058 (val ^ vmcs12->cr0_read_shadow))
7059 return 1;
7060 break;
7061 case 3:
7062 if ((vmcs12->cr3_target_count >= 1 &&
7063 vmcs12->cr3_target_value0 == val) ||
7064 (vmcs12->cr3_target_count >= 2 &&
7065 vmcs12->cr3_target_value1 == val) ||
7066 (vmcs12->cr3_target_count >= 3 &&
7067 vmcs12->cr3_target_value2 == val) ||
7068 (vmcs12->cr3_target_count >= 4 &&
7069 vmcs12->cr3_target_value3 == val))
7070 return 0;
7071 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
7072 return 1;
7073 break;
7074 case 4:
7075 if (vmcs12->cr4_guest_host_mask &
7076 (vmcs12->cr4_read_shadow ^ val))
7077 return 1;
7078 break;
7079 case 8:
7080 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
7081 return 1;
7082 break;
7083 }
7084 break;
7085 case 2: /* clts */
7086 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
7087 (vmcs12->cr0_read_shadow & X86_CR0_TS))
7088 return 1;
7089 break;
7090 case 1: /* mov from cr */
7091 switch (cr) {
7092 case 3:
7093 if (vmcs12->cpu_based_vm_exec_control &
7094 CPU_BASED_CR3_STORE_EXITING)
7095 return 1;
7096 break;
7097 case 8:
7098 if (vmcs12->cpu_based_vm_exec_control &
7099 CPU_BASED_CR8_STORE_EXITING)
7100 return 1;
7101 break;
7102 }
7103 break;
7104 case 3: /* lmsw */
7105 /*
7106 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
7107 * cr0. Other attempted changes are ignored, with no exit.
7108 */
7109 if (vmcs12->cr0_guest_host_mask & 0xe &
7110 (val ^ vmcs12->cr0_read_shadow))
7111 return 1;
7112 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
7113 !(vmcs12->cr0_read_shadow & 0x1) &&
7114 (val & 0x1))
7115 return 1;
7116 break;
7117 }
7118 return 0;
7119}
7120
7121/*
7122 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
7123 * should handle it ourselves in L0 (and then continue L2). Only call this
7124 * when in is_guest_mode (L2).
7125 */
7126static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
7127{
644d711a
NHE		 7128 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7129 struct vcpu_vmx *vmx = to_vmx(vcpu);
7130 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
957c897e 7131 u32 exit_reason = vmx->exit_reason;
644d711a 7132
542060ea
JK		 7133 trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
7134 vmcs_readl(EXIT_QUALIFICATION),
7135 vmx->idt_vectoring_info,
7136 intr_info,
7137 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
7138 KVM_ISA_VMX);
7139
644d711a
NHE		 7140 if (vmx->nested.nested_run_pending)
7141 return 0;
7142
7143 if (unlikely(vmx->fail)) {
bd80158a
JK		 7144 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
7145 vmcs_read32(VM_INSTRUCTION_ERROR));
644d711a
NHE		 7146 return 1;
7147 }
7148
7149 switch (exit_reason) {
7150 case EXIT_REASON_EXCEPTION_NMI:
7151 if (!is_exception(intr_info))
7152 return 0;
7153 else if (is_page_fault(intr_info))
7154 return enable_ept;
e504c909 7155 else if (is_no_device(intr_info) &&
ccf9844e 7156 !(vmcs12->guest_cr0 & X86_CR0_TS))
e504c909 7157 return 0;
644d711a
NHE		 7158 return vmcs12->exception_bitmap &
7159 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
7160 case EXIT_REASON_EXTERNAL_INTERRUPT:
7161 return 0;
7162 case EXIT_REASON_TRIPLE_FAULT:
7163 return 1;
7164 case EXIT_REASON_PENDING_INTERRUPT:
3b656cf7 7165 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
644d711a 7166 case EXIT_REASON_NMI_WINDOW:
3b656cf7 7167 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
644d711a
NHE		 7168 case EXIT_REASON_TASK_SWITCH:
7169 return 1;
7170 case EXIT_REASON_CPUID:
bc613494
MT		 7171 if (kvm_register_read(vcpu, VCPU_REGS_RAX) == 0xa)
7172 return 0;
644d711a
NHE		 7173 return 1;
7174 case EXIT_REASON_HLT:
7175 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
7176 case EXIT_REASON_INVD:
7177 return 1;
7178 case EXIT_REASON_INVLPG:
7179 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
7180 case EXIT_REASON_RDPMC:
7181 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
7182 case EXIT_REASON_RDTSC:
7183 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
7184 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
7185 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
7186 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
7187 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
7188 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
a642fc30 7189 case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
644d711a
NHE		 7190 /*
7191 * VMX instructions trap unconditionally. This allows L1 to
7192 * emulate them for its L2 guest, i.e., allows 3-level nesting!
7193 */
7194 return 1;
7195 case EXIT_REASON_CR_ACCESS:
7196 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
7197 case EXIT_REASON_DR_ACCESS:
7198 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
7199 case EXIT_REASON_IO_INSTRUCTION:
908a7bdd 7200 return nested_vmx_exit_handled_io(vcpu, vmcs12);
644d711a
NHE		 7201 case EXIT_REASON_MSR_READ:
7202 case EXIT_REASON_MSR_WRITE:
7203 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
7204 case EXIT_REASON_INVALID_STATE:
7205 return 1;
7206 case EXIT_REASON_MWAIT_INSTRUCTION:
7207 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
7208 case EXIT_REASON_MONITOR_INSTRUCTION:
7209 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
7210 case EXIT_REASON_PAUSE_INSTRUCTION:
7211 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
7212 nested_cpu_has2(vmcs12,
7213 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
7214 case EXIT_REASON_MCE_DURING_VMENTRY:
7215 return 0;
7216 case EXIT_REASON_TPR_BELOW_THRESHOLD:
a7c0b07d 7217 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
644d711a
NHE		 7218 case EXIT_REASON_APIC_ACCESS:
7219 return nested_cpu_has2(vmcs12,
7220 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
7221 case EXIT_REASON_EPT_VIOLATION:
2b1be677
NHE		 7222 /*
7223 * L0 always deals with the EPT violation. If nested EPT is
7224 * used, and the nested mmu code discovers that the address is
7225 * missing in the guest EPT table (EPT12), the EPT violation
7226 * will be injected with nested_ept_inject_page_fault()
7227 */
7228 return 0;
644d711a 7229 case EXIT_REASON_EPT_MISCONFIG:
2b1be677
NHE		 7230 /*
7231 * L2 never uses directly L1's EPT, but rather L0's own EPT
7232 * table (shadow on EPT) or a merged EPT table that L0 built
7233 * (EPT on EPT). So any problems with the structure of the
7234 * table is L0's fault.
7235 */
644d711a
NHE		 7236 return 0;
7237 case EXIT_REASON_WBINVD:
7238 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
7239 case EXIT_REASON_XSETBV:
7240 return 1;
7241 default:
7242 return 1;
7243 }
7244}
7245
586f9607
AK		 7246static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
7247{
7248 *info1 = vmcs_readl(EXIT_QUALIFICATION);
7249 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
7250}
7251
6aa8b732
AK		 7252/*
7253 * The guest has exited. See if we can fix it or if we need userspace
7254 * assistance.
7255 */
851ba692 7256static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 7257{
29bd8a78 7258 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 7259 u32 exit_reason = vmx->exit_reason;
1155f76a 7260 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 7261
80ced186 7262 /* If guest state is invalid, start emulating */
14168786 7263 if (vmx->emulation_required)
80ced186 7264 return handle_invalid_guest_state(vcpu);
1d5a4d9b 7265
644d711a 7266 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
533558bc
JK		 7267 nested_vmx_vmexit(vcpu, exit_reason,
7268 vmcs_read32(VM_EXIT_INTR_INFO),
7269 vmcs_readl(EXIT_QUALIFICATION));
644d711a
NHE		 7270 return 1;
7271 }
7272
5120702e
MG		 7273 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
7274 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
7275 vcpu->run->fail_entry.hardware_entry_failure_reason
7276 = exit_reason;
7277 return 0;
7278 }
7279
29bd8a78 7280 if (unlikely(vmx->fail)) {
851ba692
AK		 7281 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
7282 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK		 7283 = vmcs_read32(VM_INSTRUCTION_ERROR);
7284 return 0;
7285 }
6aa8b732 7286
b9bf6882
XG		 7287 /*
7288 * Note:
7289 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
7290 * delivery event since it indicates guest is accessing MMIO.
7291 * The vm-exit can be triggered again after return to guest that
7292 * will cause infinite loop.
7293 */
d77c26fc 7294 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 7295 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac 7296 exit_reason != EXIT_REASON_EPT_VIOLATION &&
b9bf6882
XG		 7297 exit_reason != EXIT_REASON_TASK_SWITCH)) {
7298 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
7299 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
7300 vcpu->run->internal.ndata = 2;
7301 vcpu->run->internal.data[0] = vectoring_info;
7302 vcpu->run->internal.data[1] = exit_reason;
7303 return 0;
7304 }
3b86cd99 7305
644d711a
NHE		 7306 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
7307 !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
f5c4368f 7308 get_vmcs12(vcpu))))) {
c4282df9 7309 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 7310 vmx->soft_vnmi_blocked = 0;
3b86cd99 7311 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 7312 vcpu->arch.nmi_pending) {
3b86cd99
JK		 7313 /*
7314 * This CPU don't support us in finding the end of an
7315 * NMI-blocked window if the guest runs with IRQs
7316 * disabled. So we pull the trigger after 1 s of
7317 * futile waiting, but inform the user about this.
7318 */
7319 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
7320 "state on VCPU %d after 1 s timeout\n",
7321 __func__, vcpu->vcpu_id);
7322 vmx->soft_vnmi_blocked = 0;
3b86cd99 7323 }
3b86cd99
JK		 7324 }
7325
6aa8b732
AK		 7326 if (exit_reason < kvm_vmx_max_exit_handlers
7327 && kvm_vmx_exit_handlers[exit_reason])
851ba692 7328 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 7329 else {
2bc19dc3
MT		 7330 WARN_ONCE(1, "vmx: unexpected exit reason 0x%x\n", exit_reason);
7331 kvm_queue_exception(vcpu, UD_VECTOR);
7332 return 1;
6aa8b732 7333 }
6aa8b732
AK		 7334}
7335
95ba8273 7336static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 7337{
a7c0b07d
WL		 7338 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7339
7340 if (is_guest_mode(vcpu) &&
7341 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
7342 return;
7343
95ba8273 7344 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 7345 vmcs_write32(TPR_THRESHOLD, 0);
7346 return;
7347 }
7348
95ba8273 7349 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 7350}
7351
8d14695f
YZ		 7352static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
7353{
7354 u32 sec_exec_control;
7355
7356 /*
7357 * There is not point to enable virtualize x2apic without enable
7358 * apicv
7359 */
c7c9c56c
YZ		 7360 if (!cpu_has_vmx_virtualize_x2apic_mode() ||
7361 !vmx_vm_has_apicv(vcpu->kvm))
8d14695f
YZ		 7362 return;
7363
7364 if (!vm_need_tpr_shadow(vcpu->kvm))
7365 return;
7366
7367 sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7368
7369 if (set) {
7370 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7371 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
7372 } else {
7373 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
7374 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7375 }
7376 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
7377
7378 vmx_set_msr_bitmap(vcpu);
7379}
7380
38b99173
TC		 7381static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
7382{
7383 struct vcpu_vmx *vmx = to_vmx(vcpu);
7384
7385 /*
7386 * Currently we do not handle the nested case where L2 has an
7387 * APIC access page of its own; that page is still pinned.
7388 * Hence, we skip the case where the VCPU is in guest mode _and_
7389 * L1 prepared an APIC access page for L2.
7390 *
7391 * For the case where L1 and L2 share the same APIC access page
7392 * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
7393 * in the vmcs12), this function will only update either the vmcs01
7394 * or the vmcs02. If the former, the vmcs02 will be updated by
7395 * prepare_vmcs02. If the latter, the vmcs01 will be updated in
7396 * the next L2->L1 exit.
7397 */
7398 if (!is_guest_mode(vcpu) ||
7399 !nested_cpu_has2(vmx->nested.current_vmcs12,
7400 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
7401 vmcs_write64(APIC_ACCESS_ADDR, hpa);
7402}
7403
c7c9c56c
YZ		 7404static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
7405{
7406 u16 status;
7407 u8 old;
7408
7409 if (!vmx_vm_has_apicv(kvm))
7410 return;
7411
7412 if (isr == -1)
7413 isr = 0;
7414
7415 status = vmcs_read16(GUEST_INTR_STATUS);
7416 old = status >> 8;
7417 if (isr != old) {
7418 status &= 0xff;
7419 status |= isr << 8;
7420 vmcs_write16(GUEST_INTR_STATUS, status);
7421 }
7422}
7423
7424static void vmx_set_rvi(int vector)
7425{
7426 u16 status;
7427 u8 old;
7428
4114c27d
WW		 7429 if (vector == -1)
7430 vector = 0;
7431
c7c9c56c
YZ		 7432 status = vmcs_read16(GUEST_INTR_STATUS);
7433 old = (u8)status & 0xff;
7434 if ((u8)vector != old) {
7435 status &= ~0xff;
7436 status |= (u8)vector;
7437 vmcs_write16(GUEST_INTR_STATUS, status);
7438 }
7439}
7440
7441static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
7442{
4114c27d
WW		 7443 if (!is_guest_mode(vcpu)) {
7444 vmx_set_rvi(max_irr);
7445 return;
7446 }
7447
c7c9c56c
YZ		 7448 if (max_irr == -1)
7449 return;
7450
963fee16 7451 /*
4114c27d
WW		 7452 * In guest mode. If a vmexit is needed, vmx_check_nested_events
7453 * handles it.
963fee16 7454 */
4114c27d 7455 if (nested_exit_on_intr(vcpu))
963fee16
WL		 7456 return;
7457
963fee16 7458 /*
4114c27d 7459 * Else, fall back to pre-APICv interrupt injection since L2
963fee16
WL		 7460 * is run without virtual interrupt delivery.
7461 */
7462 if (!kvm_event_needs_reinjection(vcpu) &&
7463 vmx_interrupt_allowed(vcpu)) {
7464 kvm_queue_interrupt(vcpu, max_irr, false);
7465 vmx_inject_irq(vcpu);
7466 }
c7c9c56c
YZ		 7467}
7468
7469static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
7470{
3d81bc7e
YZ		 7471 if (!vmx_vm_has_apicv(vcpu->kvm))
7472 return;
7473
c7c9c56c
YZ		 7474 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
7475 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
7476 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
7477 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
7478}
7479
51aa01d1 7480static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
cf393f75 7481{
00eba012
AK		 7482 u32 exit_intr_info;
7483
7484 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
7485 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
7486 return;
7487
c5ca8e57 7488 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
00eba012 7489 exit_intr_info = vmx->exit_intr_info;
a0861c02
AK		 7490
7491 /* Handle machine checks before interrupts are enabled */
00eba012 7492 if (is_machine_check(exit_intr_info))
a0861c02
AK		 7493 kvm_machine_check();
7494
20f65983 7495 /* We need to handle NMIs before interrupts are enabled */
00eba012 7496 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
ff9d07a0
ZY		 7497 (exit_intr_info & INTR_INFO_VALID_MASK)) {
7498 kvm_before_handle_nmi(&vmx->vcpu);
20f65983 7499 asm("int $2");
ff9d07a0
ZY		 7500 kvm_after_handle_nmi(&vmx->vcpu);
7501 }
51aa01d1 7502}
20f65983 7503
a547c6db
YZ		 7504static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
7505{
7506 u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7507
7508 /*
7509 * If external interrupt exists, IF bit is set in rflags/eflags on the
7510 * interrupt stack frame, and interrupt will be enabled on a return
7511 * from interrupt handler.
7512 */
7513 if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
7514 == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
7515 unsigned int vector;
7516 unsigned long entry;
7517 gate_desc *desc;
7518 struct vcpu_vmx *vmx = to_vmx(vcpu);
7519#ifdef CONFIG_X86_64
7520 unsigned long tmp;
7521#endif
7522
7523 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
7524 desc = (gate_desc *)vmx->host_idt_base + vector;
7525 entry = gate_offset(*desc);
7526 asm volatile(
7527#ifdef CONFIG_X86_64
7528 "mov %%" _ASM_SP ", %[sp]\n\t"
7529 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
7530 "push $%c[ss]\n\t"
7531 "push %[sp]\n\t"
7532#endif
7533 "pushf\n\t"
7534 "orl $0x200, (%%" _ASM_SP ")\n\t"
7535 __ASM_SIZE(push) " $%c[cs]\n\t"
7536 "call *%[entry]\n\t"
7537 :
7538#ifdef CONFIG_X86_64
7539 [sp]"=&r"(tmp)
7540#endif
7541 :
7542 [entry]"r"(entry),
7543 [ss]"i"(__KERNEL_DS),
7544 [cs]"i"(__KERNEL_CS)
7545 );
7546 } else
7547 local_irq_enable();
7548}
7549
da8999d3
LJ		 7550static bool vmx_mpx_supported(void)
7551{
7552 return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
7553 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
7554}
7555
51aa01d1
AK		 7556static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
7557{
c5ca8e57 7558 u32 exit_intr_info;
51aa01d1
AK		 7559 bool unblock_nmi;
7560 u8 vector;
7561 bool idtv_info_valid;
7562
7563 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
20f65983 7564
cf393f75 7565 if (cpu_has_virtual_nmis()) {
9d58b931
AK		 7566 if (vmx->nmi_known_unmasked)
7567 return;
c5ca8e57
AK		 7568 /*
7569 * Can't use vmx->exit_intr_info since we're not sure what
7570 * the exit reason is.
7571 */
7572 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
cf393f75
AK		 7573 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
7574 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
7575 /*
7b4a25cb 7576 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 7577 * Re-set bit "block by NMI" before VM entry if vmexit caused by
7578 * a guest IRET fault.
7b4a25cb
GN		 7579 * SDM 3: 23.2.2 (September 2008)
7580 * Bit 12 is undefined in any of the following cases:
7581 * If the VM exit sets the valid bit in the IDT-vectoring
7582 * information field.
7583 * If the VM exit is due to a double fault.
cf393f75 7584 */
7b4a25cb
GN		 7585 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
7586 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 7587 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7588 GUEST_INTR_STATE_NMI);
9d58b931
AK		 7589 else
7590 vmx->nmi_known_unmasked =
7591 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
7592 & GUEST_INTR_STATE_NMI);
3b86cd99
JK		 7593 } else if (unlikely(vmx->soft_vnmi_blocked))
7594 vmx->vnmi_blocked_time +=
7595 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
51aa01d1
AK		 7596}
7597
3ab66e8a 7598static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
83422e17
AK		 7599 u32 idt_vectoring_info,
7600 int instr_len_field,
7601 int error_code_field)
51aa01d1 7602{
51aa01d1
AK		 7603 u8 vector;
7604 int type;
7605 bool idtv_info_valid;
7606
7607 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
668f612f 7608
3ab66e8a
JK		 7609 vcpu->arch.nmi_injected = false;
7610 kvm_clear_exception_queue(vcpu);
7611 kvm_clear_interrupt_queue(vcpu);
37b96e98
GN		 7612
7613 if (!idtv_info_valid)
7614 return;
7615
3ab66e8a 7616 kvm_make_request(KVM_REQ_EVENT, vcpu);
3842d135 7617
668f612f
AK		 7618 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
7619 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 7620
64a7ec06 7621 switch (type) {
37b96e98 7622 case INTR_TYPE_NMI_INTR:
3ab66e8a 7623 vcpu->arch.nmi_injected = true;
668f612f 7624 /*
7b4a25cb 7625 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 7626 * Clear bit "block by NMI" before VM entry if a NMI
7627 * delivery faulted.
668f612f 7628 */
3ab66e8a 7629 vmx_set_nmi_mask(vcpu, false);
37b96e98 7630 break;
37b96e98 7631 case INTR_TYPE_SOFT_EXCEPTION:
3ab66e8a 7632 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f
GN		 7633 /* fall through */
7634 case INTR_TYPE_HARD_EXCEPTION:
35920a35 7635 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
83422e17 7636 u32 err = vmcs_read32(error_code_field);
851eb667 7637 kvm_requeue_exception_e(vcpu, vector, err);
35920a35 7638 } else
851eb667 7639 kvm_requeue_exception(vcpu, vector);
37b96e98 7640 break;
66fd3f7f 7641 case INTR_TYPE_SOFT_INTR:
3ab66e8a 7642 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f 7643 /* fall through */
37b96e98 7644 case INTR_TYPE_EXT_INTR:
3ab66e8a 7645 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
37b96e98
GN		 7646 break;
7647 default:
7648 break;
f7d9238f 7649 }
cf393f75
AK		 7650}
7651
83422e17
AK		 7652static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
7653{
3ab66e8a 7654 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
83422e17
AK		 7655 VM_EXIT_INSTRUCTION_LEN,
7656 IDT_VECTORING_ERROR_CODE);
7657}
7658
b463a6f7
AK		 7659static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
7660{
3ab66e8a 7661 __vmx_complete_interrupts(vcpu,
b463a6f7
AK		 7662 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
7663 VM_ENTRY_INSTRUCTION_LEN,
7664 VM_ENTRY_EXCEPTION_ERROR_CODE);
7665
7666 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
7667}
7668
d7cd9796
GN		 7669static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
7670{
7671 int i, nr_msrs;
7672 struct perf_guest_switch_msr *msrs;
7673
7674 msrs = perf_guest_get_msrs(&nr_msrs);
7675
7676 if (!msrs)
7677 return;
7678
7679 for (i = 0; i < nr_msrs; i++)
7680 if (msrs[i].host == msrs[i].guest)
7681 clear_atomic_switch_msr(vmx, msrs[i].msr);
7682 else
7683 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
7684 msrs[i].host);
7685}
7686
a3b5ba49 7687static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 7688{
a2fa3e9f 7689 struct vcpu_vmx *vmx = to_vmx(vcpu);
d974baa3 7690 unsigned long debugctlmsr, cr4;
104f226b
AK		 7691
7692 /* Record the guest's net vcpu time for enforced NMI injections. */
7693 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
7694 vmx->entry_time = ktime_get();
7695
7696 /* Don't enter VMX if guest state is invalid, let the exit handler
7697 start emulation until we arrive back to a valid state */
14168786 7698 if (vmx->emulation_required)
104f226b
AK		 7699 return;
7700
a7653ecd
RK		 7701 if (vmx->ple_window_dirty) {
7702 vmx->ple_window_dirty = false;
7703 vmcs_write32(PLE_WINDOW, vmx->ple_window);
7704 }
7705
012f83cb
AG		 7706 if (vmx->nested.sync_shadow_vmcs) {
7707 copy_vmcs12_to_shadow(vmx);
7708 vmx->nested.sync_shadow_vmcs = false;
7709 }
7710
104f226b
AK		 7711 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
7712 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
7713 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
7714 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
7715
d974baa3
AL		 7716 cr4 = read_cr4();
7717 if (unlikely(cr4 != vmx->host_state.vmcs_host_cr4)) {
7718 vmcs_writel(HOST_CR4, cr4);
7719 vmx->host_state.vmcs_host_cr4 = cr4;
7720 }
7721
104f226b
AK		 7722 /* When single-stepping over STI and MOV SS, we must clear the
7723 * corresponding interruptibility bits in the guest state. Otherwise
7724 * vmentry fails as it then expects bit 14 (BS) in pending debug
7725 * exceptions being set, but that's not correct for the guest debugging
7726 * case. */
7727 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7728 vmx_set_interrupt_shadow(vcpu, 0);
7729
d7cd9796 7730 atomic_switch_perf_msrs(vmx);
2a7921b7 7731 debugctlmsr = get_debugctlmsr();
d7cd9796 7732
d462b819 7733 vmx->__launched = vmx->loaded_vmcs->launched;
104f226b 7734 asm(
6aa8b732 7735 /* Store host registers */
b188c81f
AK		 7736 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
7737 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
7738 "push %%" _ASM_CX " \n\t"
7739 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
313dbd49 7740 "je 1f \n\t"
b188c81f 7741 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
4ecac3fd 7742 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 7743 "1: \n\t"
d3edefc0 7744 /* Reload cr2 if changed */
b188c81f
AK		 7745 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
7746 "mov %%cr2, %%" _ASM_DX " \n\t"
7747 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
d3edefc0 7748 "je 2f \n\t"
b188c81f 7749 "mov %%" _ASM_AX", %%cr2 \n\t"
d3edefc0 7750 "2: \n\t"
6aa8b732 7751 /* Check if vmlaunch of vmresume is needed */
e08aa78a 7752 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 7753 /* Load guest registers. Don't clobber flags. */
b188c81f
AK		 7754 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
7755 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
7756 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
7757 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
7758 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
7759 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
05b3e0c2 7760#ifdef CONFIG_X86_64
e08aa78a
AK		 7761 "mov %c[r8](%0), %%r8 \n\t"
7762 "mov %c[r9](%0), %%r9 \n\t"
7763 "mov %c[r10](%0), %%r10 \n\t"
7764 "mov %c[r11](%0), %%r11 \n\t"
7765 "mov %c[r12](%0), %%r12 \n\t"
7766 "mov %c[r13](%0), %%r13 \n\t"
7767 "mov %c[r14](%0), %%r14 \n\t"
7768 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 7769#endif
b188c81f 7770 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
c801949d 7771
6aa8b732 7772 /* Enter guest mode */
83287ea4 7773 "jne 1f \n\t"
4ecac3fd 7774 __ex(ASM_VMX_VMLAUNCH) "\n\t"
83287ea4
AK		 7775 "jmp 2f \n\t"
7776 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
7777 "2: "
6aa8b732 7778 /* Save guest registers, load host registers, keep flags */
b188c81f 7779 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
40712fae 7780 "pop %0 \n\t"
b188c81f
AK		 7781 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
7782 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
7783 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
7784 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
7785 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
7786 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
7787 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
05b3e0c2 7788#ifdef CONFIG_X86_64
e08aa78a
AK		 7789 "mov %%r8, %c[r8](%0) \n\t"
7790 "mov %%r9, %c[r9](%0) \n\t"
7791 "mov %%r10, %c[r10](%0) \n\t"
7792 "mov %%r11, %c[r11](%0) \n\t"
7793 "mov %%r12, %c[r12](%0) \n\t"
7794 "mov %%r13, %c[r13](%0) \n\t"
7795 "mov %%r14, %c[r14](%0) \n\t"
7796 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 7797#endif
b188c81f
AK		 7798 "mov %%cr2, %%" _ASM_AX " \n\t"
7799 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
c801949d 7800
b188c81f 7801 "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t"
e08aa78a 7802 "setbe %c[fail](%0) \n\t"
83287ea4
AK		 7803 ".pushsection .rodata \n\t"
7804 ".global vmx_return \n\t"
7805 "vmx_return: " _ASM_PTR " 2b \n\t"
7806 ".popsection"
e08aa78a 7807 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
d462b819 7808 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
e08aa78a 7809 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 7810 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 7811 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
7812 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
7813 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
7814 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
7815 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
7816 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
7817 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 7818#ifdef CONFIG_X86_64
ad312c7c
ZX		 7819 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
7820 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
7821 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
7822 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
7823 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
7824 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
7825 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
7826 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 7827#endif
40712fae
AK		 7828 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
7829 [wordsize]"i"(sizeof(ulong))
c2036300
LV		 7830 : "cc", "memory"
7831#ifdef CONFIG_X86_64
b188c81f 7832 , "rax", "rbx", "rdi", "rsi"
c2036300 7833 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
b188c81f
AK		 7834#else
7835 , "eax", "ebx", "edi", "esi"
c2036300
LV		 7836#endif
7837 );
6aa8b732 7838
2a7921b7
GN		 7839 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
7840 if (debugctlmsr)
7841 update_debugctlmsr(debugctlmsr);
7842
aa67f609
AK		 7843#ifndef CONFIG_X86_64
7844 /*
7845 * The sysexit path does not restore ds/es, so we must set them to
7846 * a reasonable value ourselves.
7847 *
7848 * We can't defer this to vmx_load_host_state() since that function
7849 * may be executed in interrupt context, which saves and restore segments
7850 * around it, nullifying its effect.
7851 */
7852 loadsegment(ds, __USER_DS);
7853 loadsegment(es, __USER_DS);
7854#endif
7855
6de4f3ad 7856 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6de12732 7857 | (1 << VCPU_EXREG_RFLAGS)
aff48baa 7858 | (1 << VCPU_EXREG_PDPTR)
2fb92db1 7859 | (1 << VCPU_EXREG_SEGMENTS)
aff48baa 7860 | (1 << VCPU_EXREG_CR3));
5fdbf976
MT		 7861 vcpu->arch.regs_dirty = 0;
7862
1155f76a
AK		 7863 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
7864
d462b819 7865 vmx->loaded_vmcs->launched = 1;
1b6269db 7866
51aa01d1 7867 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
1e2b1dd7 7868 trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
51aa01d1 7869
e0b890d3
GN		 7870 /*
7871 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
7872 * we did not inject a still-pending event to L1 now because of
7873 * nested_run_pending, we need to re-enable this bit.
7874 */
7875 if (vmx->nested.nested_run_pending)
7876 kvm_make_request(KVM_REQ_EVENT, vcpu);
7877
7878 vmx->nested.nested_run_pending = 0;
7879
51aa01d1
AK		 7880 vmx_complete_atomic_exit(vmx);
7881 vmx_recover_nmi_blocking(vmx);
cf393f75 7882 vmx_complete_interrupts(vmx);
6aa8b732
AK		 7883}
7884
4fa7734c
PB		 7885static void vmx_load_vmcs01(struct kvm_vcpu *vcpu)
7886{
7887 struct vcpu_vmx *vmx = to_vmx(vcpu);
7888 int cpu;
7889
7890 if (vmx->loaded_vmcs == &vmx->vmcs01)
7891 return;
7892
7893 cpu = get_cpu();
7894 vmx->loaded_vmcs = &vmx->vmcs01;
7895 vmx_vcpu_put(vcpu);
7896 vmx_vcpu_load(vcpu, cpu);
7897 vcpu->cpu = cpu;
7898 put_cpu();
7899}
7900
6aa8b732
AK		 7901static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
7902{
fb3f0f51
RR		 7903 struct vcpu_vmx *vmx = to_vmx(vcpu);
7904
cdbecfc3 7905 free_vpid(vmx);
4fa7734c
PB		 7906 leave_guest_mode(vcpu);
7907 vmx_load_vmcs01(vcpu);
26a865f4 7908 free_nested(vmx);
4fa7734c 7909 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51
RR		 7910 kfree(vmx->guest_msrs);
7911 kvm_vcpu_uninit(vcpu);
a4770347 7912 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 7913}
7914
fb3f0f51 7915static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 7916{
fb3f0f51 7917 int err;
c16f862d 7918 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 7919 int cpu;
6aa8b732 7920
a2fa3e9f 7921 if (!vmx)
fb3f0f51
RR		 7922 return ERR_PTR(-ENOMEM);
7923
2384d2b3
SY		 7924 allocate_vpid(vmx);
7925
fb3f0f51
RR		 7926 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
7927 if (err)
7928 goto free_vcpu;
965b58a5 7929
a2fa3e9f 7930 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
03916db9
PB		 7931 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
7932 > PAGE_SIZE);
0123be42 7933
be6d05cf 7934 err = -ENOMEM;
fb3f0f51 7935 if (!vmx->guest_msrs) {
fb3f0f51
RR		 7936 goto uninit_vcpu;
7937 }
965b58a5 7938
d462b819
NHE		 7939 vmx->loaded_vmcs = &vmx->vmcs01;
7940 vmx->loaded_vmcs->vmcs = alloc_vmcs();
7941 if (!vmx->loaded_vmcs->vmcs)
fb3f0f51 7942 goto free_msrs;
d462b819
NHE		 7943 if (!vmm_exclusive)
7944 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
7945 loaded_vmcs_init(vmx->loaded_vmcs);
7946 if (!vmm_exclusive)
7947 kvm_cpu_vmxoff();
a2fa3e9f 7948
15ad7146
AK		 7949 cpu = get_cpu();
7950 vmx_vcpu_load(&vmx->vcpu, cpu);
e48672fa 7951 vmx->vcpu.cpu = cpu;
8b9cf98c 7952 err = vmx_vcpu_setup(vmx);
fb3f0f51 7953 vmx_vcpu_put(&vmx->vcpu);
15ad7146 7954 put_cpu();
fb3f0f51
RR		 7955 if (err)
7956 goto free_vmcs;
a63cb560 7957 if (vm_need_virtualize_apic_accesses(kvm)) {
be6d05cf
JK		 7958 err = alloc_apic_access_page(kvm);
7959 if (err)
5e4a0b3c 7960 goto free_vmcs;
a63cb560 7961 }
fb3f0f51 7962
b927a3ce
SY		 7963 if (enable_ept) {
7964 if (!kvm->arch.ept_identity_map_addr)
7965 kvm->arch.ept_identity_map_addr =
7966 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
f51770ed
TC		 7967 err = init_rmode_identity_map(kvm);
7968 if (err)
93ea5388 7969 goto free_vmcs;
b927a3ce 7970 }
b7ebfb05 7971
a9d30f33
NHE		 7972 vmx->nested.current_vmptr = -1ull;
7973 vmx->nested.current_vmcs12 = NULL;
7974
fb3f0f51
RR		 7975 return &vmx->vcpu;
7976
7977free_vmcs:
5f3fbc34 7978 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51 7979free_msrs:
fb3f0f51
RR		 7980 kfree(vmx->guest_msrs);
7981uninit_vcpu:
7982 kvm_vcpu_uninit(&vmx->vcpu);
7983free_vcpu:
cdbecfc3 7984 free_vpid(vmx);
a4770347 7985 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 7986 return ERR_PTR(err);
6aa8b732
AK		 7987}
7988
002c7f7c
YS		 7989static void __init vmx_check_processor_compat(void *rtn)
7990{
7991 struct vmcs_config vmcs_conf;
7992
7993 *(int *)rtn = 0;
7994 if (setup_vmcs_config(&vmcs_conf) < 0)
7995 *(int *)rtn = -EIO;
7996 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
7997 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
7998 smp_processor_id());
7999 *(int *)rtn = -EIO;
8000 }
8001}
8002
67253af5
SY		 8003static int get_ept_level(void)
8004{
8005 return VMX_EPT_DEFAULT_GAW + 1;
8006}
8007
4b12f0de 8008static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 8009{
4b12f0de
SY		 8010 u64 ret;
8011
522c68c4
SY		 8012 /* For VT-d and EPT combination
8013 * 1. MMIO: always map as UC
8014 * 2. EPT with VT-d:
8015 * a. VT-d without snooping control feature: can't guarantee the
8016 * result, try to trust guest.
8017 * b. VT-d with snooping control feature: snooping control feature of
8018 * VT-d engine can guarantee the cache correctness. Just set it
8019 * to WB to keep consistent with host. So the same as item 3.
a19a6d11 8020 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
522c68c4
SY		 8021 * consistent with host MTRR
8022 */
4b12f0de
SY		 8023 if (is_mmio)
8024 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
e0f0bbc5 8025 else if (kvm_arch_has_noncoherent_dma(vcpu->kvm))
522c68c4
SY		 8026 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
8027 VMX_EPT_MT_EPTE_SHIFT;
4b12f0de 8028 else
522c68c4 8029 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
a19a6d11 8030 | VMX_EPT_IPAT_BIT;
4b12f0de
SY		 8031
8032 return ret;
64d4d521
SY		 8033}
8034
17cc3935 8035static int vmx_get_lpage_level(void)
344f414f 8036{
878403b7
SY		 8037 if (enable_ept && !cpu_has_vmx_ept_1g_page())
8038 return PT_DIRECTORY_LEVEL;
8039 else
8040 /* For shadow and EPT supported 1GB page */
8041 return PT_PDPE_LEVEL;
344f414f
JR		 8042}
8043
0e851880
SY		 8044static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
8045{
4e47c7a6
SY		 8046 struct kvm_cpuid_entry2 *best;
8047 struct vcpu_vmx *vmx = to_vmx(vcpu);
8048 u32 exec_control;
8049
8050 vmx->rdtscp_enabled = false;
8051 if (vmx_rdtscp_supported()) {
8052 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8053 if (exec_control & SECONDARY_EXEC_RDTSCP) {
8054 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
8055 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
8056 vmx->rdtscp_enabled = true;
8057 else {
8058 exec_control &= ~SECONDARY_EXEC_RDTSCP;
8059 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
8060 exec_control);
8061 }
8062 }
8063 }
ad756a16 8064
ad756a16
MJ		 8065 /* Exposing INVPCID only when PCID is exposed */
8066 best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
8067 if (vmx_invpcid_supported() &&
4f977045 8068 best && (best->ebx & bit(X86_FEATURE_INVPCID)) &&
ad756a16 8069 guest_cpuid_has_pcid(vcpu)) {
29282fde 8070 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
ad756a16
MJ		 8071 exec_control |= SECONDARY_EXEC_ENABLE_INVPCID;
8072 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
8073 exec_control);
8074 } else {
29282fde
TI		 8075 if (cpu_has_secondary_exec_ctrls()) {
8076 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8077 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
8078 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
8079 exec_control);
8080 }
ad756a16 8081 if (best)
4f977045 8082 best->ebx &= ~bit(X86_FEATURE_INVPCID);
ad756a16 8083 }
0e851880
SY		 8084}
8085
d4330ef2
JR		 8086static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
8087{
7b8050f5
NHE		 8088 if (func == 1 && nested)
8089 entry->ecx |= bit(X86_FEATURE_VMX);
d4330ef2
JR		 8090}
8091
25d92081
YZ		 8092static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
8093 struct x86_exception *fault)
8094{
533558bc
JK		 8095 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8096 u32 exit_reason;
25d92081
YZ		 8097
8098 if (fault->error_code & PFERR_RSVD_MASK)
533558bc 8099 exit_reason = EXIT_REASON_EPT_MISCONFIG;
25d92081 8100 else
533558bc
JK		 8101 exit_reason = EXIT_REASON_EPT_VIOLATION;
8102 nested_vmx_vmexit(vcpu, exit_reason, 0, vcpu->arch.exit_qualification);
25d92081
YZ		 8103 vmcs12->guest_physical_address = fault->address;
8104}
8105
155a97a3
NHE		 8106/* Callbacks for nested_ept_init_mmu_context: */
8107
8108static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
8109{
8110 /* return the page table to be shadowed - in our case, EPT12 */
8111 return get_vmcs12(vcpu)->ept_pointer;
8112}
8113
8a3c1a33 8114static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
155a97a3 8115{
8a3c1a33 8116 kvm_init_shadow_ept_mmu(vcpu, &vcpu->arch.mmu,
155a97a3
NHE		 8117 nested_vmx_ept_caps & VMX_EPT_EXECUTE_ONLY_BIT);
8118
8119 vcpu->arch.mmu.set_cr3 = vmx_set_cr3;
8120 vcpu->arch.mmu.get_cr3 = nested_ept_get_cr3;
8121 vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
8122
8123 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
155a97a3
NHE		 8124}
8125
8126static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
8127{
8128 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
8129}
8130
feaf0c7d
GN		 8131static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
8132 struct x86_exception *fault)
8133{
8134 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8135
8136 WARN_ON(!is_guest_mode(vcpu));
8137
8138 /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
8139 if (vmcs12->exception_bitmap & (1u << PF_VECTOR))
533558bc
JK		 8140 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
8141 vmcs_read32(VM_EXIT_INTR_INFO),
8142 vmcs_readl(EXIT_QUALIFICATION));
feaf0c7d
GN		 8143 else
8144 kvm_inject_page_fault(vcpu, fault);
8145}
8146
a2bcba50
WL		 8147static bool nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
8148 struct vmcs12 *vmcs12)
8149{
8150 struct vcpu_vmx *vmx = to_vmx(vcpu);
8151
8152 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
a7c0b07d 8153 /* TODO: Also verify bits beyond physical address width are 0 */
a2bcba50 8154 if (!PAGE_ALIGNED(vmcs12->apic_access_addr))
a2bcba50
WL		 8155 return false;
8156
8157 /*
8158 * Translate L1 physical address to host physical
8159 * address for vmcs02. Keep the page pinned, so this
8160 * physical address remains valid. We keep a reference
8161 * to it so we can release it later.
8162 */
8163 if (vmx->nested.apic_access_page) /* shouldn't happen */
8164 nested_release_page(vmx->nested.apic_access_page);
8165 vmx->nested.apic_access_page =
8166 nested_get_page(vcpu, vmcs12->apic_access_addr);
8167 }
a7c0b07d
WL		 8168
8169 if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
8170 /* TODO: Also verify bits beyond physical address width are 0 */
8171 if (!PAGE_ALIGNED(vmcs12->virtual_apic_page_addr))
8172 return false;
8173
8174 if (vmx->nested.virtual_apic_page) /* shouldn't happen */
8175 nested_release_page(vmx->nested.virtual_apic_page);
8176 vmx->nested.virtual_apic_page =
8177 nested_get_page(vcpu, vmcs12->virtual_apic_page_addr);
8178
8179 /*
8180 * Failing the vm entry is _not_ what the processor does
8181 * but it's basically the only possibility we have.
8182 * We could still enter the guest if CR8 load exits are
8183 * enabled, CR8 store exits are enabled, and virtualize APIC
8184 * access is disabled; in this case the processor would never
8185 * use the TPR shadow and we could simply clear the bit from
8186 * the execution control. But such a configuration is useless,
8187 * so let's keep the code simple.
8188 */
8189 if (!vmx->nested.virtual_apic_page)
8190 return false;
8191 }
8192
a2bcba50
WL		 8193 return true;
8194}
8195
f4124500
JK		 8196static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
8197{
8198 u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
8199 struct vcpu_vmx *vmx = to_vmx(vcpu);
8200
8201 if (vcpu->arch.virtual_tsc_khz == 0)
8202 return;
8203
8204 /* Make sure short timeouts reliably trigger an immediate vmexit.
8205 * hrtimer_start does not guarantee this. */
8206 if (preemption_timeout <= 1) {
8207 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
8208 return;
8209 }
8210
8211 preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
8212 preemption_timeout *= 1000000;
8213 do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
8214 hrtimer_start(&vmx->nested.preemption_timer,
8215 ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
8216}
8217
fe3ef05c
NHE		 8218/*
8219 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
8220 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
b4619660 8221 * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
fe3ef05c
NHE		 8222 * guest in a way that will both be appropriate to L1's requests, and our
8223 * needs. In addition to modifying the active vmcs (which is vmcs02), this
8224 * function also has additional necessary side-effects, like setting various
8225 * vcpu->arch fields.
8226 */
8227static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
8228{
8229 struct vcpu_vmx *vmx = to_vmx(vcpu);
8230 u32 exec_control;
8231
8232 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
8233 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
8234 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
8235 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
8236 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
8237 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
8238 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
8239 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
8240 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
8241 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
8242 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
8243 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
8244 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
8245 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
8246 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
8247 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
8248 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
8249 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
8250 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
8251 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
8252 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
8253 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
8254 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
8255 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
8256 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
8257 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
8258 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
8259 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
8260 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
8261 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
8262 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
8263 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
8264 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
8265 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
8266 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
8267 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
8268
2996fca0
JK		 8269 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS) {
8270 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
8271 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
8272 } else {
8273 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
8274 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
8275 }
fe3ef05c
NHE		 8276 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
8277 vmcs12->vm_entry_intr_info_field);
8278 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
8279 vmcs12->vm_entry_exception_error_code);
8280 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
8281 vmcs12->vm_entry_instruction_len);
8282 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
8283 vmcs12->guest_interruptibility_info);
fe3ef05c 8284 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
63fbf59f 8285 vmx_set_rflags(vcpu, vmcs12->guest_rflags);
fe3ef05c
NHE		 8286 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
8287 vmcs12->guest_pending_dbg_exceptions);
8288 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
8289 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
8290
8291 vmcs_write64(VMCS_LINK_POINTER, -1ull);
8292
f4124500
JK		 8293 exec_control = vmcs12->pin_based_vm_exec_control;
8294 exec_control |= vmcs_config.pin_based_exec_ctrl;
696dfd95
PB		 8295 exec_control &= ~(PIN_BASED_VMX_PREEMPTION_TIMER |
8296 PIN_BASED_POSTED_INTR);
f4124500 8297 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
fe3ef05c 8298
f4124500
JK		 8299 vmx->nested.preemption_timer_expired = false;
8300 if (nested_cpu_has_preemption_timer(vmcs12))
8301 vmx_start_preemption_timer(vcpu);
0238ea91 8302
fe3ef05c
NHE		 8303 /*
8304 * Whether page-faults are trapped is determined by a combination of
8305 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
8306 * If enable_ept, L0 doesn't care about page faults and we should
8307 * set all of these to L1's desires. However, if !enable_ept, L0 does
8308 * care about (at least some) page faults, and because it is not easy
8309 * (if at all possible?) to merge L0 and L1's desires, we simply ask
8310 * to exit on each and every L2 page fault. This is done by setting
8311 * MASK=MATCH=0 and (see below) EB.PF=1.
8312 * Note that below we don't need special code to set EB.PF beyond the
8313 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
8314 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
8315 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
8316 *
8317 * A problem with this approach (when !enable_ept) is that L1 may be
8318 * injected with more page faults than it asked for. This could have
8319 * caused problems, but in practice existing hypervisors don't care.
8320 * To fix this, we will need to emulate the PFEC checking (on the L1
8321 * page tables), using walk_addr(), when injecting PFs to L1.
8322 */
8323 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
8324 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
8325 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
8326 enable_ept ? vmcs12->page_fault_error_code_match : 0);
8327
8328 if (cpu_has_secondary_exec_ctrls()) {
f4124500 8329 exec_control = vmx_secondary_exec_control(vmx);
fe3ef05c
NHE		 8330 if (!vmx->rdtscp_enabled)
8331 exec_control &= ~SECONDARY_EXEC_RDTSCP;
8332 /* Take the following fields only from vmcs12 */
696dfd95
PB		 8333 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
8334 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
8335 SECONDARY_EXEC_APIC_REGISTER_VIRT);
fe3ef05c
NHE		 8336 if (nested_cpu_has(vmcs12,
8337 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
8338 exec_control |= vmcs12->secondary_vm_exec_control;
8339
8340 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
fe3ef05c
NHE		 8341 /*
8342 * If translation failed, no matter: This feature asks
8343 * to exit when accessing the given address, and if it
8344 * can never be accessed, this feature won't do
8345 * anything anyway.
8346 */
8347 if (!vmx->nested.apic_access_page)
8348 exec_control &=
8349 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8350 else
8351 vmcs_write64(APIC_ACCESS_ADDR,
8352 page_to_phys(vmx->nested.apic_access_page));
ca3f257a
JK		 8353 } else if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm)) {
8354 exec_control |=
8355 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
38b99173 8356 kvm_vcpu_reload_apic_access_page(vcpu);
fe3ef05c
NHE		 8357 }
8358
8359 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
8360 }
8361
8362
8363 /*
8364 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
8365 * Some constant fields are set here by vmx_set_constant_host_state().
8366 * Other fields are different per CPU, and will be set later when
8367 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
8368 */
a547c6db 8369 vmx_set_constant_host_state(vmx);
fe3ef05c
NHE		 8370
8371 /*
8372 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
8373 * entry, but only if the current (host) sp changed from the value
8374 * we wrote last (vmx->host_rsp). This cache is no longer relevant
8375 * if we switch vmcs, and rather than hold a separate cache per vmcs,
8376 * here we just force the write to happen on entry.
8377 */
8378 vmx->host_rsp = 0;
8379
8380 exec_control = vmx_exec_control(vmx); /* L0's desires */
8381 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
8382 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
8383 exec_control &= ~CPU_BASED_TPR_SHADOW;
8384 exec_control |= vmcs12->cpu_based_vm_exec_control;
a7c0b07d
WL		 8385
8386 if (exec_control & CPU_BASED_TPR_SHADOW) {
8387 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
8388 page_to_phys(vmx->nested.virtual_apic_page));
8389 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
8390 }
8391
fe3ef05c
NHE		 8392 /*
8393 * Merging of IO and MSR bitmaps not currently supported.
8394 * Rather, exit every time.
8395 */
8396 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
8397 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
8398 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
8399
8400 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
8401
8402 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
8403 * bitwise-or of what L1 wants to trap for L2, and what we want to
8404 * trap. Note that CR0.TS also needs updating - we do this later.
8405 */
8406 update_exception_bitmap(vcpu);
8407 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
8408 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
8409
8049d651
NHE		 8410 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
8411 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
8412 * bits are further modified by vmx_set_efer() below.
8413 */
f4124500 8414 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
8049d651
NHE		 8415
8416 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
8417 * emulated by vmx_set_efer(), below.
8418 */
2961e876 8419 vm_entry_controls_init(vmx,
8049d651
NHE		 8420 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
8421 ~VM_ENTRY_IA32E_MODE) |
fe3ef05c
NHE		 8422 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
8423
44811c02 8424 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) {
fe3ef05c 8425 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
44811c02
JK		 8426 vcpu->arch.pat = vmcs12->guest_ia32_pat;
8427 } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
fe3ef05c
NHE		 8428 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
8429
8430
8431 set_cr4_guest_host_mask(vmx);
8432
36be0b9d
PB		 8433 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
8434 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
8435
27fc51b2
NHE		 8436 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
8437 vmcs_write64(TSC_OFFSET,
8438 vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
8439 else
8440 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
fe3ef05c
NHE		 8441
8442 if (enable_vpid) {
8443 /*
8444 * Trivially support vpid by letting L2s share their parent
8445 * L1's vpid. TODO: move to a more elaborate solution, giving
8446 * each L2 its own vpid and exposing the vpid feature to L1.
8447 */
8448 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
8449 vmx_flush_tlb(vcpu);
8450 }
8451
155a97a3
NHE		 8452 if (nested_cpu_has_ept(vmcs12)) {
8453 kvm_mmu_unload(vcpu);
8454 nested_ept_init_mmu_context(vcpu);
8455 }
8456
fe3ef05c
NHE		 8457 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
8458 vcpu->arch.efer = vmcs12->guest_ia32_efer;
d1fa0352 8459 else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
fe3ef05c
NHE		 8460 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
8461 else
8462 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
8463 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
8464 vmx_set_efer(vcpu, vcpu->arch.efer);
8465
8466 /*
8467 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
8468 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
8469 * The CR0_READ_SHADOW is what L2 should have expected to read given
8470 * the specifications by L1; It's not enough to take
8471 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
8472 * have more bits than L1 expected.
8473 */
8474 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
8475 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
8476
8477 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
8478 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
8479
8480 /* shadow page tables on either EPT or shadow page tables */
8481 kvm_set_cr3(vcpu, vmcs12->guest_cr3);
8482 kvm_mmu_reset_context(vcpu);
8483
feaf0c7d
GN		 8484 if (!enable_ept)
8485 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
8486
3633cfc3
NHE		 8487 /*
8488 * L1 may access the L2's PDPTR, so save them to construct vmcs12
8489 */
8490 if (enable_ept) {
8491 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
8492 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
8493 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
8494 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
8495 }
8496
fe3ef05c
NHE		 8497 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
8498 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
8499}
8500
cd232ad0
NHE		 8501/*
8502 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
8503 * for running an L2 nested guest.
8504 */
8505static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
8506{
8507 struct vmcs12 *vmcs12;
8508 struct vcpu_vmx *vmx = to_vmx(vcpu);
8509 int cpu;
8510 struct loaded_vmcs *vmcs02;
384bb783 8511 bool ia32e;
cd232ad0
NHE		 8512
8513 if (!nested_vmx_check_permission(vcpu) ||
8514 !nested_vmx_check_vmcs12(vcpu))
8515 return 1;
8516
8517 skip_emulated_instruction(vcpu);
8518 vmcs12 = get_vmcs12(vcpu);
8519
012f83cb
AG		 8520 if (enable_shadow_vmcs)
8521 copy_shadow_to_vmcs12(vmx);
8522
7c177938
NHE		 8523 /*
8524 * The nested entry process starts with enforcing various prerequisites
8525 * on vmcs12 as required by the Intel SDM, and act appropriately when
8526 * they fail: As the SDM explains, some conditions should cause the
8527 * instruction to fail, while others will cause the instruction to seem
8528 * to succeed, but return an EXIT_REASON_INVALID_STATE.
8529 * To speed up the normal (success) code path, we should avoid checking
8530 * for misconfigurations which will anyway be caught by the processor
8531 * when using the merged vmcs02.
8532 */
8533 if (vmcs12->launch_state == launch) {
8534 nested_vmx_failValid(vcpu,
8535 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
8536 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
8537 return 1;
8538 }
8539
6dfacadd
JK		 8540 if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
8541 vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT) {
26539bd0
PB		 8542 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8543 return 1;
8544 }
8545
7c177938 8546 if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
bc39c4db 8547 !PAGE_ALIGNED(vmcs12->msr_bitmap)) {
7c177938
NHE		 8548 /*TODO: Also verify bits beyond physical address width are 0*/
8549 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8550 return 1;
8551 }
8552
a2bcba50 8553 if (!nested_get_vmcs12_pages(vcpu, vmcs12)) {
7c177938
NHE		 8554 /*TODO: Also verify bits beyond physical address width are 0*/
8555 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8556 return 1;
8557 }
8558
8559 if (vmcs12->vm_entry_msr_load_count > 0 ||
8560 vmcs12->vm_exit_msr_load_count > 0 ||
8561 vmcs12->vm_exit_msr_store_count > 0) {
bd80158a
JK		 8562 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
8563 __func__);
7c177938
NHE		 8564 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8565 return 1;
8566 }
8567
8568 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
3dcdf3ec
JK		 8569 nested_vmx_true_procbased_ctls_low,
8570 nested_vmx_procbased_ctls_high) ||
7c177938
NHE		 8571 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
8572 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
8573 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
8574 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
8575 !vmx_control_verify(vmcs12->vm_exit_controls,
2996fca0
JK		 8576 nested_vmx_true_exit_ctls_low,
8577 nested_vmx_exit_ctls_high) ||
7c177938 8578 !vmx_control_verify(vmcs12->vm_entry_controls,
2996fca0
JK		 8579 nested_vmx_true_entry_ctls_low,
8580 nested_vmx_entry_ctls_high))
7c177938
NHE		 8581 {
8582 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8583 return 1;
8584 }
8585
8586 if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
8587 ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
8588 nested_vmx_failValid(vcpu,
8589 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
8590 return 1;
8591 }
8592
92fbc7b1 8593 if (!nested_cr0_valid(vmcs12, vmcs12->guest_cr0) ||
7c177938
NHE		 8594 ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
8595 nested_vmx_entry_failure(vcpu, vmcs12,
8596 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
8597 return 1;
8598 }
8599 if (vmcs12->vmcs_link_pointer != -1ull) {
8600 nested_vmx_entry_failure(vcpu, vmcs12,
8601 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
8602 return 1;
8603 }
8604
384bb783 8605 /*
cb0c8cda 8606 * If the load IA32_EFER VM-entry control is 1, the following checks
384bb783
JK		 8607 * are performed on the field for the IA32_EFER MSR:
8608 * - Bits reserved in the IA32_EFER MSR must be 0.
8609 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
8610 * the IA-32e mode guest VM-exit control. It must also be identical
8611 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
8612 * CR0.PG) is 1.
8613 */
8614 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
8615 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
8616 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
8617 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
8618 ((vmcs12->guest_cr0 & X86_CR0_PG) &&
8619 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
8620 nested_vmx_entry_failure(vcpu, vmcs12,
8621 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
8622 return 1;
8623 }
8624 }
8625
8626 /*
8627 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
8628 * IA32_EFER MSR must be 0 in the field for that register. In addition,
8629 * the values of the LMA and LME bits in the field must each be that of
8630 * the host address-space size VM-exit control.
8631 */
8632 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
8633 ia32e = (vmcs12->vm_exit_controls &
8634 VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
8635 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
8636 ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
8637 ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
8638 nested_vmx_entry_failure(vcpu, vmcs12,
8639 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
8640 return 1;
8641 }
8642 }
8643
7c177938
NHE		 8644 /*
8645 * We're finally done with prerequisite checking, and can start with
8646 * the nested entry.
8647 */
8648
cd232ad0
NHE		 8649 vmcs02 = nested_get_current_vmcs02(vmx);
8650 if (!vmcs02)
8651 return -ENOMEM;
8652
8653 enter_guest_mode(vcpu);
8654
8655 vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
8656
2996fca0
JK		 8657 if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
8658 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
8659
cd232ad0
NHE		 8660 cpu = get_cpu();
8661 vmx->loaded_vmcs = vmcs02;
8662 vmx_vcpu_put(vcpu);
8663 vmx_vcpu_load(vcpu, cpu);
8664 vcpu->cpu = cpu;
8665 put_cpu();
8666
36c3cc42
JK		 8667 vmx_segment_cache_clear(vmx);
8668
cd232ad0
NHE		 8669 vmcs12->launch_state = 1;
8670
8671 prepare_vmcs02(vcpu, vmcs12);
8672
6dfacadd
JK		 8673 if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
8674 return kvm_emulate_halt(vcpu);
8675
7af40ad3
JK		 8676 vmx->nested.nested_run_pending = 1;
8677
cd232ad0
NHE		 8678 /*
8679 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
8680 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
8681 * returned as far as L1 is concerned. It will only return (and set
8682 * the success flag) when L2 exits (see nested_vmx_vmexit()).
8683 */
8684 return 1;
8685}
8686
4704d0be
NHE		 8687/*
8688 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
8689 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
8690 * This function returns the new value we should put in vmcs12.guest_cr0.
8691 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
8692 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
8693 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
8694 * didn't trap the bit, because if L1 did, so would L0).
8695 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
8696 * been modified by L2, and L1 knows it. So just leave the old value of
8697 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
8698 * isn't relevant, because if L0 traps this bit it can set it to anything.
8699 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
8700 * changed these bits, and therefore they need to be updated, but L0
8701 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
8702 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
8703 */
8704static inline unsigned long
8705vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
8706{
8707 return
8708 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
8709 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
8710 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
8711 vcpu->arch.cr0_guest_owned_bits));
8712}
8713
8714static inline unsigned long
8715vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
8716{
8717 return
8718 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
8719 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
8720 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
8721 vcpu->arch.cr4_guest_owned_bits));
8722}
8723
5f3d5799
JK		 8724static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
8725 struct vmcs12 *vmcs12)
8726{
8727 u32 idt_vectoring;
8728 unsigned int nr;
8729
851eb667 8730 if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
5f3d5799
JK		 8731 nr = vcpu->arch.exception.nr;
8732 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
8733
8734 if (kvm_exception_is_soft(nr)) {
8735 vmcs12->vm_exit_instruction_len =
8736 vcpu->arch.event_exit_inst_len;
8737 idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
8738 } else
8739 idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
8740
8741 if (vcpu->arch.exception.has_error_code) {
8742 idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
8743 vmcs12->idt_vectoring_error_code =
8744 vcpu->arch.exception.error_code;
8745 }
8746
8747 vmcs12->idt_vectoring_info_field = idt_vectoring;
cd2633c5 8748 } else if (vcpu->arch.nmi_injected) {
5f3d5799
JK		 8749 vmcs12->idt_vectoring_info_field =
8750 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
8751 } else if (vcpu->arch.interrupt.pending) {
8752 nr = vcpu->arch.interrupt.nr;
8753 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
8754
8755 if (vcpu->arch.interrupt.soft) {
8756 idt_vectoring |= INTR_TYPE_SOFT_INTR;
8757 vmcs12->vm_entry_instruction_len =
8758 vcpu->arch.event_exit_inst_len;
8759 } else
8760 idt_vectoring |= INTR_TYPE_EXT_INTR;
8761
8762 vmcs12->idt_vectoring_info_field = idt_vectoring;
8763 }
8764}
8765
b6b8a145
JK		 8766static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
8767{
8768 struct vcpu_vmx *vmx = to_vmx(vcpu);
8769
f4124500
JK		 8770 if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
8771 vmx->nested.preemption_timer_expired) {
8772 if (vmx->nested.nested_run_pending)
8773 return -EBUSY;
8774 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
8775 return 0;
8776 }
8777
b6b8a145 8778 if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
220c5672
JK		 8779 if (vmx->nested.nested_run_pending ||
8780 vcpu->arch.interrupt.pending)
b6b8a145
JK		 8781 return -EBUSY;
8782 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
8783 NMI_VECTOR | INTR_TYPE_NMI_INTR |
8784 INTR_INFO_VALID_MASK, 0);
8785 /*
8786 * The NMI-triggered VM exit counts as injection:
8787 * clear this one and block further NMIs.
8788 */
8789 vcpu->arch.nmi_pending = 0;
8790 vmx_set_nmi_mask(vcpu, true);
8791 return 0;
8792 }
8793
8794 if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
8795 nested_exit_on_intr(vcpu)) {
8796 if (vmx->nested.nested_run_pending)
8797 return -EBUSY;
8798 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
8799 }
8800
8801 return 0;
8802}
8803
f4124500
JK		 8804static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
8805{
8806 ktime_t remaining =
8807 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
8808 u64 value;
8809
8810 if (ktime_to_ns(remaining) <= 0)
8811 return 0;
8812
8813 value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
8814 do_div(value, 1000000);
8815 return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
8816}
8817
4704d0be
NHE		 8818/*
8819 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
8820 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
8821 * and this function updates it to reflect the changes to the guest state while
8822 * L2 was running (and perhaps made some exits which were handled directly by L0
8823 * without going back to L1), and to reflect the exit reason.
8824 * Note that we do not have to copy here all VMCS fields, just those that
8825 * could have changed by the L2 guest or the exit - i.e., the guest-state and
8826 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
8827 * which already writes to vmcs12 directly.
8828 */
533558bc
JK		 8829static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
8830 u32 exit_reason, u32 exit_intr_info,
8831 unsigned long exit_qualification)
4704d0be
NHE		 8832{
8833 /* update guest state fields: */
8834 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
8835 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
8836
4704d0be
NHE		 8837 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
8838 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
8839 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
8840
8841 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
8842 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
8843 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
8844 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
8845 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
8846 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
8847 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
8848 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
8849 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
8850 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
8851 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
8852 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
8853 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
8854 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
8855 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
8856 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
8857 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
8858 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
8859 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
8860 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
8861 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
8862 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
8863 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
8864 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
8865 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
8866 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
8867 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
8868 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
8869 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
8870 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
8871 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
8872 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
8873 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
8874 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
8875 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
8876 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
8877
4704d0be
NHE		 8878 vmcs12->guest_interruptibility_info =
8879 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
8880 vmcs12->guest_pending_dbg_exceptions =
8881 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
3edf1e69
JK		 8882 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
8883 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
8884 else
8885 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
4704d0be 8886
f4124500
JK		 8887 if (nested_cpu_has_preemption_timer(vmcs12)) {
8888 if (vmcs12->vm_exit_controls &
8889 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
8890 vmcs12->vmx_preemption_timer_value =
8891 vmx_get_preemption_timer_value(vcpu);
8892 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
8893 }
7854cbca 8894
3633cfc3
NHE		 8895 /*
8896 * In some cases (usually, nested EPT), L2 is allowed to change its
8897 * own CR3 without exiting. If it has changed it, we must keep it.
8898 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
8899 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
8900 *
8901 * Additionally, restore L2's PDPTR to vmcs12.
8902 */
8903 if (enable_ept) {
8904 vmcs12->guest_cr3 = vmcs_read64(GUEST_CR3);
8905 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
8906 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
8907 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
8908 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
8909 }
8910
c18911a2
JK		 8911 vmcs12->vm_entry_controls =
8912 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
2961e876 8913 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
c18911a2 8914
2996fca0
JK		 8915 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
8916 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
8917 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
8918 }
8919
4704d0be
NHE		 8920 /* TODO: These cannot have changed unless we have MSR bitmaps and
8921 * the relevant bit asks not to trap the change */
b8c07d55 8922 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
4704d0be 8923 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
10ba54a5
JK		 8924 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
8925 vmcs12->guest_ia32_efer = vcpu->arch.efer;
4704d0be
NHE		 8926 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
8927 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
8928 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
36be0b9d
PB		 8929 if (vmx_mpx_supported())
8930 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
4704d0be
NHE		 8931
8932 /* update exit information fields: */
8933
533558bc
JK		 8934 vmcs12->vm_exit_reason = exit_reason;
8935 vmcs12->exit_qualification = exit_qualification;
4704d0be 8936
533558bc 8937 vmcs12->vm_exit_intr_info = exit_intr_info;
c0d1c770
JK		 8938 if ((vmcs12->vm_exit_intr_info &
8939 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
8940 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
8941 vmcs12->vm_exit_intr_error_code =
8942 vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5f3d5799 8943 vmcs12->idt_vectoring_info_field = 0;
4704d0be
NHE		 8944 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
8945 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
8946
5f3d5799
JK		 8947 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
8948 /* vm_entry_intr_info_field is cleared on exit. Emulate this
8949 * instead of reading the real value. */
4704d0be 8950 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
5f3d5799
JK		 8951
8952 /*
8953 * Transfer the event that L0 or L1 may wanted to inject into
8954 * L2 to IDT_VECTORING_INFO_FIELD.
8955 */
8956 vmcs12_save_pending_event(vcpu, vmcs12);
8957 }
8958
8959 /*
8960 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
8961 * preserved above and would only end up incorrectly in L1.
8962 */
8963 vcpu->arch.nmi_injected = false;
8964 kvm_clear_exception_queue(vcpu);
8965 kvm_clear_interrupt_queue(vcpu);
4704d0be
NHE		 8966}
8967
8968/*
8969 * A part of what we need to when the nested L2 guest exits and we want to
8970 * run its L1 parent, is to reset L1's guest state to the host state specified
8971 * in vmcs12.
8972 * This function is to be called not only on normal nested exit, but also on
8973 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
8974 * Failures During or After Loading Guest State").
8975 * This function should be called when the active VMCS is L1's (vmcs01).
8976 */
733568f9
JK		 8977static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
8978 struct vmcs12 *vmcs12)
4704d0be 8979{
21feb4eb
ACL		 8980 struct kvm_segment seg;
8981
4704d0be
NHE		 8982 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
8983 vcpu->arch.efer = vmcs12->host_ia32_efer;
d1fa0352 8984 else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
4704d0be
NHE		 8985 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
8986 else
8987 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
8988 vmx_set_efer(vcpu, vcpu->arch.efer);
8989
8990 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
8991 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
1adfa76a 8992 vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
4704d0be
NHE		 8993 /*
8994 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
8995 * actually changed, because it depends on the current state of
8996 * fpu_active (which may have changed).
8997 * Note that vmx_set_cr0 refers to efer set above.
8998 */
9e3e4dbf 8999 vmx_set_cr0(vcpu, vmcs12->host_cr0);
4704d0be
NHE		 9000 /*
9001 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
9002 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
9003 * but we also need to update cr0_guest_host_mask and exception_bitmap.
9004 */
9005 update_exception_bitmap(vcpu);
9006 vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
9007 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
9008
9009 /*
9010 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
9011 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
9012 */
9013 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
9014 kvm_set_cr4(vcpu, vmcs12->host_cr4);
9015
29bf08f1 9016 nested_ept_uninit_mmu_context(vcpu);
155a97a3 9017
4704d0be
NHE		 9018 kvm_set_cr3(vcpu, vmcs12->host_cr3);
9019 kvm_mmu_reset_context(vcpu);
9020
feaf0c7d
GN		 9021 if (!enable_ept)
9022 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
9023
4704d0be
NHE		 9024 if (enable_vpid) {
9025 /*
9026 * Trivially support vpid by letting L2s share their parent
9027 * L1's vpid. TODO: move to a more elaborate solution, giving
9028 * each L2 its own vpid and exposing the vpid feature to L1.
9029 */
9030 vmx_flush_tlb(vcpu);
9031 }
9032
9033
9034 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
9035 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
9036 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
9037 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
9038 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
4704d0be 9039
36be0b9d
PB		 9040 /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */
9041 if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
9042 vmcs_write64(GUEST_BNDCFGS, 0);
9043
44811c02 9044 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
4704d0be 9045 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
44811c02
JK		 9046 vcpu->arch.pat = vmcs12->host_ia32_pat;
9047 }
4704d0be
NHE		 9048 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
9049 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
9050 vmcs12->host_ia32_perf_global_ctrl);
503cd0c5 9051
21feb4eb
ACL		 9052 /* Set L1 segment info according to Intel SDM
9053 27.5.2 Loading Host Segment and Descriptor-Table Registers */
9054 seg = (struct kvm_segment) {
9055 .base = 0,
9056 .limit = 0xFFFFFFFF,
9057 .selector = vmcs12->host_cs_selector,
9058 .type = 11,
9059 .present = 1,
9060 .s = 1,
9061 .g = 1
9062 };
9063 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
9064 seg.l = 1;
9065 else
9066 seg.db = 1;
9067 vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
9068 seg = (struct kvm_segment) {
9069 .base = 0,
9070 .limit = 0xFFFFFFFF,
9071 .type = 3,
9072 .present = 1,
9073 .s = 1,
9074 .db = 1,
9075 .g = 1
9076 };
9077 seg.selector = vmcs12->host_ds_selector;
9078 vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
9079 seg.selector = vmcs12->host_es_selector;
9080 vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
9081 seg.selector = vmcs12->host_ss_selector;
9082 vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
9083 seg.selector = vmcs12->host_fs_selector;
9084 seg.base = vmcs12->host_fs_base;
9085 vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
9086 seg.selector = vmcs12->host_gs_selector;
9087 seg.base = vmcs12->host_gs_base;
9088 vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
9089 seg = (struct kvm_segment) {
205befd9 9090 .base = vmcs12->host_tr_base,
21feb4eb
ACL		 9091 .limit = 0x67,
9092 .selector = vmcs12->host_tr_selector,
9093 .type = 11,
9094 .present = 1
9095 };
9096 vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
9097
503cd0c5
JK		 9098 kvm_set_dr(vcpu, 7, 0x400);
9099 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4704d0be
NHE		 9100}
9101
9102/*
9103 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
9104 * and modify vmcs12 to make it see what it would expect to see there if
9105 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
9106 */
533558bc
JK		 9107static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
9108 u32 exit_intr_info,
9109 unsigned long exit_qualification)
4704d0be
NHE		 9110{
9111 struct vcpu_vmx *vmx = to_vmx(vcpu);
4704d0be
NHE		 9112 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9113
5f3d5799
JK		 9114 /* trying to cancel vmlaunch/vmresume is a bug */
9115 WARN_ON_ONCE(vmx->nested.nested_run_pending);
9116
4704d0be 9117 leave_guest_mode(vcpu);
533558bc
JK		 9118 prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
9119 exit_qualification);
4704d0be 9120
f3380ca5
WL		 9121 vmx_load_vmcs01(vcpu);
9122
77b0f5d6
BD		 9123 if ((exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
9124 && nested_exit_intr_ack_set(vcpu)) {
9125 int irq = kvm_cpu_get_interrupt(vcpu);
9126 WARN_ON(irq < 0);
9127 vmcs12->vm_exit_intr_info = irq |
9128 INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
9129 }
9130
542060ea
JK		 9131 trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
9132 vmcs12->exit_qualification,
9133 vmcs12->idt_vectoring_info_field,
9134 vmcs12->vm_exit_intr_info,
9135 vmcs12->vm_exit_intr_error_code,
9136 KVM_ISA_VMX);
4704d0be 9137
2961e876
GN		 9138 vm_entry_controls_init(vmx, vmcs_read32(VM_ENTRY_CONTROLS));
9139 vm_exit_controls_init(vmx, vmcs_read32(VM_EXIT_CONTROLS));
36c3cc42
JK		 9140 vmx_segment_cache_clear(vmx);
9141
4704d0be
NHE		 9142 /* if no vmcs02 cache requested, remove the one we used */
9143 if (VMCS02_POOL_SIZE == 0)
9144 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
9145
9146 load_vmcs12_host_state(vcpu, vmcs12);
9147
27fc51b2 9148 /* Update TSC_OFFSET if TSC was changed while L2 ran */
4704d0be
NHE		 9149 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
9150
9151 /* This is needed for same reason as it was needed in prepare_vmcs02 */
9152 vmx->host_rsp = 0;
9153
9154 /* Unpin physical memory we referred to in vmcs02 */
9155 if (vmx->nested.apic_access_page) {
9156 nested_release_page(vmx->nested.apic_access_page);
48d89b92 9157 vmx->nested.apic_access_page = NULL;
4704d0be 9158 }
a7c0b07d
WL		 9159 if (vmx->nested.virtual_apic_page) {
9160 nested_release_page(vmx->nested.virtual_apic_page);
48d89b92 9161 vmx->nested.virtual_apic_page = NULL;
a7c0b07d 9162 }
4704d0be 9163
38b99173
TC		 9164 /*
9165 * We are now running in L2, mmu_notifier will force to reload the
9166 * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
9167 */
9168 kvm_vcpu_reload_apic_access_page(vcpu);
9169
4704d0be
NHE		 9170 /*
9171 * Exiting from L2 to L1, we're now back to L1 which thinks it just
9172 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
9173 * success or failure flag accordingly.
9174 */
9175 if (unlikely(vmx->fail)) {
9176 vmx->fail = 0;
9177 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
9178 } else
9179 nested_vmx_succeed(vcpu);
012f83cb
AG		 9180 if (enable_shadow_vmcs)
9181 vmx->nested.sync_shadow_vmcs = true;
b6b8a145
JK		 9182
9183 /* in case we halted in L2 */
9184 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
4704d0be
NHE		 9185}
9186
42124925
JK		 9187/*
9188 * Forcibly leave nested mode in order to be able to reset the VCPU later on.
9189 */
9190static void vmx_leave_nested(struct kvm_vcpu *vcpu)
9191{
9192 if (is_guest_mode(vcpu))
533558bc 9193 nested_vmx_vmexit(vcpu, -1, 0, 0);
42124925
JK		 9194 free_nested(to_vmx(vcpu));
9195}
9196
7c177938
NHE		 9197/*
9198 * L1's failure to enter L2 is a subset of a normal exit, as explained in
9199 * 23.7 "VM-entry failures during or after loading guest state" (this also
9200 * lists the acceptable exit-reason and exit-qualification parameters).
9201 * It should only be called before L2 actually succeeded to run, and when
9202 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
9203 */
9204static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
9205 struct vmcs12 *vmcs12,
9206 u32 reason, unsigned long qualification)
9207{
9208 load_vmcs12_host_state(vcpu, vmcs12);
9209 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
9210 vmcs12->exit_qualification = qualification;
9211 nested_vmx_succeed(vcpu);
012f83cb
AG		 9212 if (enable_shadow_vmcs)
9213 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
7c177938
NHE		 9214}
9215
8a76d7f2
JR		 9216static int vmx_check_intercept(struct kvm_vcpu *vcpu,
9217 struct x86_instruction_info *info,
9218 enum x86_intercept_stage stage)
9219{
9220 return X86EMUL_CONTINUE;
9221}
9222
48d89b92 9223static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
ae97a3b8 9224{
b4a2d31d
RK		 9225 if (ple_gap)
9226 shrink_ple_window(vcpu);
ae97a3b8
RK		 9227}
9228
cbdd1bea 9229static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 9230 .cpu_has_kvm_support = cpu_has_kvm_support,
9231 .disabled_by_bios = vmx_disabled_by_bios,
9232 .hardware_setup = hardware_setup,
9233 .hardware_unsetup = hardware_unsetup,
002c7f7c 9234 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 9235 .hardware_enable = hardware_enable,
9236 .hardware_disable = hardware_disable,
04547156 9237 .cpu_has_accelerated_tpr = report_flexpriority,
6aa8b732
AK		 9238
9239 .vcpu_create = vmx_create_vcpu,
9240 .vcpu_free = vmx_free_vcpu,
04d2cc77 9241 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 9242
04d2cc77 9243 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 9244 .vcpu_load = vmx_vcpu_load,
9245 .vcpu_put = vmx_vcpu_put,
9246
c8639010 9247 .update_db_bp_intercept = update_exception_bitmap,
6aa8b732
AK		 9248 .get_msr = vmx_get_msr,
9249 .set_msr = vmx_set_msr,
9250 .get_segment_base = vmx_get_segment_base,
9251 .get_segment = vmx_get_segment,
9252 .set_segment = vmx_set_segment,
2e4d2653 9253 .get_cpl = vmx_get_cpl,
6aa8b732 9254 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 9255 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
aff48baa 9256 .decache_cr3 = vmx_decache_cr3,
25c4c276 9257 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 9258 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 9259 .set_cr3 = vmx_set_cr3,
9260 .set_cr4 = vmx_set_cr4,
6aa8b732 9261 .set_efer = vmx_set_efer,
6aa8b732
AK		 9262 .get_idt = vmx_get_idt,
9263 .set_idt = vmx_set_idt,
9264 .get_gdt = vmx_get_gdt,
9265 .set_gdt = vmx_set_gdt,
73aaf249
JK		 9266 .get_dr6 = vmx_get_dr6,
9267 .set_dr6 = vmx_set_dr6,
020df079 9268 .set_dr7 = vmx_set_dr7,
81908bf4 9269 .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
5fdbf976 9270 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 9271 .get_rflags = vmx_get_rflags,
9272 .set_rflags = vmx_set_rflags,
02daab21 9273 .fpu_deactivate = vmx_fpu_deactivate,
6aa8b732
AK		 9274
9275 .tlb_flush = vmx_flush_tlb,
6aa8b732 9276
6aa8b732 9277 .run = vmx_vcpu_run,
6062d012 9278 .handle_exit = vmx_handle_exit,
6aa8b732 9279 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 9280 .set_interrupt_shadow = vmx_set_interrupt_shadow,
9281 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 9282 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 9283 .set_irq = vmx_inject_irq,
95ba8273 9284 .set_nmi = vmx_inject_nmi,
298101da 9285 .queue_exception = vmx_queue_exception,
b463a6f7 9286 .cancel_injection = vmx_cancel_injection,
78646121 9287 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 9288 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 9289 .get_nmi_mask = vmx_get_nmi_mask,
9290 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 9291 .enable_nmi_window = enable_nmi_window,
9292 .enable_irq_window = enable_irq_window,
9293 .update_cr8_intercept = update_cr8_intercept,
8d14695f 9294 .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
38b99173 9295 .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
c7c9c56c
YZ		 9296 .vm_has_apicv = vmx_vm_has_apicv,
9297 .load_eoi_exitmap = vmx_load_eoi_exitmap,
9298 .hwapic_irr_update = vmx_hwapic_irr_update,
9299 .hwapic_isr_update = vmx_hwapic_isr_update,
a20ed54d
YZ		 9300 .sync_pir_to_irr = vmx_sync_pir_to_irr,
9301 .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
95ba8273 9302
cbc94022 9303 .set_tss_addr = vmx_set_tss_addr,
67253af5 9304 .get_tdp_level = get_ept_level,
4b12f0de 9305 .get_mt_mask = vmx_get_mt_mask,
229456fc 9306
586f9607 9307 .get_exit_info = vmx_get_exit_info,
586f9607 9308
17cc3935 9309 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY		 9310
9311 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY		 9312
9313 .rdtscp_supported = vmx_rdtscp_supported,
ad756a16 9314 .invpcid_supported = vmx_invpcid_supported,
d4330ef2
JR		 9315
9316 .set_supported_cpuid = vmx_set_supported_cpuid,
f5f48ee1
SY		 9317
9318 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
99e3e30a 9319
4051b188 9320 .set_tsc_khz = vmx_set_tsc_khz,
ba904635 9321 .read_tsc_offset = vmx_read_tsc_offset,
99e3e30a 9322 .write_tsc_offset = vmx_write_tsc_offset,
e48672fa 9323 .adjust_tsc_offset = vmx_adjust_tsc_offset,
857e4099 9324 .compute_tsc_offset = vmx_compute_tsc_offset,
d5c1785d 9325 .read_l1_tsc = vmx_read_l1_tsc,
1c97f0a0
JR		 9326
9327 .set_tdp_cr3 = vmx_set_cr3,
8a76d7f2
JR		 9328
9329 .check_intercept = vmx_check_intercept,
a547c6db 9330 .handle_external_intr = vmx_handle_external_intr,
da8999d3 9331 .mpx_supported = vmx_mpx_supported,
b6b8a145
JK		 9332
9333 .check_nested_events = vmx_check_nested_events,
ae97a3b8
RK		 9334
9335 .sched_in = vmx_sched_in,
6aa8b732
AK		 9336};
9337
9338static int __init vmx_init(void)
9339{
34a1cd60
TC		 9340 int r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
9341 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 9342 if (r)
34a1cd60 9343 return r;
25c5f225 9344
8f536b76
ZY		 9345#ifdef CONFIG_KEXEC
9346 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
9347 crash_vmclear_local_loaded_vmcss);
9348#endif
9349
fdef3ad1 9350 return 0;
6aa8b732
AK		 9351}
9352
9353static void __exit vmx_exit(void)
9354{
8f536b76 9355#ifdef CONFIG_KEXEC
3b63a43f 9356 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
8f536b76
ZY		 9357 synchronize_rcu();
9358#endif
9359
cb498ea2 9360 kvm_exit();
6aa8b732
AK		 9361}
9362
9363module_init(vmx_init)
9364module_exit(vmx_exit)
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