]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blame - arch/x86/kvm/vmx.c
projects / mirror_ubuntu-bionic-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
KVM: nVMX: introduce nested_get_vmcs12_pages
[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
9611c187 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
00b27a3e 21#include "cpuid.h"
e495606d 22
edf88417 23#include <linux/kvm_host.h>
6aa8b732 24#include <linux/module.h>
9d8f549d 25#include <linux/kernel.h>
6aa8b732
AK		 26#include <linux/mm.h>
27#include <linux/highmem.h>
e8edc6e0 28#include <linux/sched.h>
c7addb90 29#include <linux/moduleparam.h>
e9bda3b3 30#include <linux/mod_devicetable.h>
229456fc 31#include <linux/ftrace_event.h>
5a0e3ad6 32#include <linux/slab.h>
cafd6659 33#include <linux/tboot.h>
f4124500 34#include <linux/hrtimer.h>
5fdbf976 35#include "kvm_cache_regs.h"
35920a35 36#include "x86.h"
e495606d 37
6aa8b732 38#include <asm/io.h>
3b3be0d1 39#include <asm/desc.h>
13673a90 40#include <asm/vmx.h>
6210e37b 41#include <asm/virtext.h>
a0861c02 42#include <asm/mce.h>
2acf923e
DC		 43#include <asm/i387.h>
44#include <asm/xcr.h>
d7cd9796 45#include <asm/perf_event.h>
81908bf4 46#include <asm/debugreg.h>
8f536b76 47#include <asm/kexec.h>
6aa8b732 48
229456fc
MT		 49#include "trace.h"
50
4ecac3fd 51#define __ex(x) __kvm_handle_fault_on_reboot(x)
5e520e62
AK		 52#define __ex_clear(x, reg) \
53 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
4ecac3fd 54
6aa8b732
AK		 55MODULE_AUTHOR("Qumranet");
56MODULE_LICENSE("GPL");
57
e9bda3b3
JT		 58static const struct x86_cpu_id vmx_cpu_id[] = {
59 X86_FEATURE_MATCH(X86_FEATURE_VMX),
60 {}
61};
62MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
63
476bc001 64static bool __read_mostly enable_vpid = 1;
736caefe 65module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 66
476bc001 67static bool __read_mostly flexpriority_enabled = 1;
736caefe 68module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 69
476bc001 70static bool __read_mostly enable_ept = 1;
736caefe 71module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 72
476bc001 73static bool __read_mostly enable_unrestricted_guest = 1;
3a624e29
NK		 74module_param_named(unrestricted_guest,
75 enable_unrestricted_guest, bool, S_IRUGO);
76
83c3a331
XH		 77static bool __read_mostly enable_ept_ad_bits = 1;
78module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
79
a27685c3 80static bool __read_mostly emulate_invalid_guest_state = true;
c1f8bc04 81module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 82
476bc001 83static bool __read_mostly vmm_exclusive = 1;
b923e62e
DX		 84module_param(vmm_exclusive, bool, S_IRUGO);
85
476bc001 86static bool __read_mostly fasteoi = 1;
58fbbf26
KT		 87module_param(fasteoi, bool, S_IRUGO);
88
5a71785d 89static bool __read_mostly enable_apicv = 1;
01e439be 90module_param(enable_apicv, bool, S_IRUGO);
83d4c286 91
abc4fc58
AG		 92static bool __read_mostly enable_shadow_vmcs = 1;
93module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
801d3424
NHE		 94/*
95 * If nested=1, nested virtualization is supported, i.e., guests may use
96 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
97 * use VMX instructions.
98 */
476bc001 99static bool __read_mostly nested = 0;
801d3424
NHE		 100module_param(nested, bool, S_IRUGO);
101
5037878e
GN		 102#define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
103#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
cdc0e244
AK		 104#define KVM_VM_CR0_ALWAYS_ON \
105 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 106#define KVM_CR4_GUEST_OWNED_BITS \
107 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
108 | X86_CR4_OSXMMEXCPT)
109
cdc0e244
AK		 110#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
111#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
112
78ac8b47
AK		 113#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
114
f4124500
JK		 115#define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
116
4b8d54f9
ZE		 117/*
118 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
119 * ple_gap: upper bound on the amount of time between two successive
120 * executions of PAUSE in a loop. Also indicate if ple enabled.
00c25bce 121 * According to test, this time is usually smaller than 128 cycles.
4b8d54f9
ZE		 122 * ple_window: upper bound on the amount of time a guest is allowed to execute
123 * in a PAUSE loop. Tests indicate that most spinlocks are held for
124 * less than 2^12 cycles
125 * Time is measured based on a counter that runs at the same rate as the TSC,
126 * refer SDM volume 3b section 21.6.13 & 22.1.3.
127 */
b4a2d31d
RK		 128#define KVM_VMX_DEFAULT_PLE_GAP 128
129#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
130#define KVM_VMX_DEFAULT_PLE_WINDOW_GROW 2
131#define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
132#define KVM_VMX_DEFAULT_PLE_WINDOW_MAX \
133 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
134
4b8d54f9
ZE		 135static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
136module_param(ple_gap, int, S_IRUGO);
137
138static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
139module_param(ple_window, int, S_IRUGO);
140
b4a2d31d
RK		 141/* Default doubles per-vcpu window every exit. */
142static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW;
143module_param(ple_window_grow, int, S_IRUGO);
144
145/* Default resets per-vcpu window every exit to ple_window. */
146static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK;
147module_param(ple_window_shrink, int, S_IRUGO);
148
149/* Default is to compute the maximum so we can never overflow. */
150static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
151static int ple_window_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
152module_param(ple_window_max, int, S_IRUGO);
153
83287ea4
AK		 154extern const ulong vmx_return;
155
8bf00a52 156#define NR_AUTOLOAD_MSRS 8
ff2f6fe9 157#define VMCS02_POOL_SIZE 1
61d2ef2c 158
a2fa3e9f
GH		 159struct vmcs {
160 u32 revision_id;
161 u32 abort;
162 char data[0];
163};
164
d462b819
NHE		 165/*
166 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
167 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
168 * loaded on this CPU (so we can clear them if the CPU goes down).
169 */
170struct loaded_vmcs {
171 struct vmcs *vmcs;
172 int cpu;
173 int launched;
174 struct list_head loaded_vmcss_on_cpu_link;
175};
176
26bb0981
AK		 177struct shared_msr_entry {
178 unsigned index;
179 u64 data;
d5696725 180 u64 mask;
26bb0981
AK		 181};
182
a9d30f33
NHE		 183/*
184 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
185 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
186 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
187 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
188 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
189 * More than one of these structures may exist, if L1 runs multiple L2 guests.
190 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
191 * underlying hardware which will be used to run L2.
192 * This structure is packed to ensure that its layout is identical across
193 * machines (necessary for live migration).
194 * If there are changes in this struct, VMCS12_REVISION must be changed.
195 */
22bd0358 196typedef u64 natural_width;
a9d30f33
NHE		 197struct __packed vmcs12 {
198 /* According to the Intel spec, a VMCS region must start with the
199 * following two fields. Then follow implementation-specific data.
200 */
201 u32 revision_id;
202 u32 abort;
22bd0358 203
27d6c865
NHE		 204 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
205 u32 padding[7]; /* room for future expansion */
206
22bd0358
NHE		 207 u64 io_bitmap_a;
208 u64 io_bitmap_b;
209 u64 msr_bitmap;
210 u64 vm_exit_msr_store_addr;
211 u64 vm_exit_msr_load_addr;
212 u64 vm_entry_msr_load_addr;
213 u64 tsc_offset;
214 u64 virtual_apic_page_addr;
215 u64 apic_access_addr;
216 u64 ept_pointer;
217 u64 guest_physical_address;
218 u64 vmcs_link_pointer;
219 u64 guest_ia32_debugctl;
220 u64 guest_ia32_pat;
221 u64 guest_ia32_efer;
222 u64 guest_ia32_perf_global_ctrl;
223 u64 guest_pdptr0;
224 u64 guest_pdptr1;
225 u64 guest_pdptr2;
226 u64 guest_pdptr3;
36be0b9d 227 u64 guest_bndcfgs;
22bd0358
NHE		 228 u64 host_ia32_pat;
229 u64 host_ia32_efer;
230 u64 host_ia32_perf_global_ctrl;
231 u64 padding64[8]; /* room for future expansion */
232 /*
233 * To allow migration of L1 (complete with its L2 guests) between
234 * machines of different natural widths (32 or 64 bit), we cannot have
235 * unsigned long fields with no explict size. We use u64 (aliased
236 * natural_width) instead. Luckily, x86 is little-endian.
237 */
238 natural_width cr0_guest_host_mask;
239 natural_width cr4_guest_host_mask;
240 natural_width cr0_read_shadow;
241 natural_width cr4_read_shadow;
242 natural_width cr3_target_value0;
243 natural_width cr3_target_value1;
244 natural_width cr3_target_value2;
245 natural_width cr3_target_value3;
246 natural_width exit_qualification;
247 natural_width guest_linear_address;
248 natural_width guest_cr0;
249 natural_width guest_cr3;
250 natural_width guest_cr4;
251 natural_width guest_es_base;
252 natural_width guest_cs_base;
253 natural_width guest_ss_base;
254 natural_width guest_ds_base;
255 natural_width guest_fs_base;
256 natural_width guest_gs_base;
257 natural_width guest_ldtr_base;
258 natural_width guest_tr_base;
259 natural_width guest_gdtr_base;
260 natural_width guest_idtr_base;
261 natural_width guest_dr7;
262 natural_width guest_rsp;
263 natural_width guest_rip;
264 natural_width guest_rflags;
265 natural_width guest_pending_dbg_exceptions;
266 natural_width guest_sysenter_esp;
267 natural_width guest_sysenter_eip;
268 natural_width host_cr0;
269 natural_width host_cr3;
270 natural_width host_cr4;
271 natural_width host_fs_base;
272 natural_width host_gs_base;
273 natural_width host_tr_base;
274 natural_width host_gdtr_base;
275 natural_width host_idtr_base;
276 natural_width host_ia32_sysenter_esp;
277 natural_width host_ia32_sysenter_eip;
278 natural_width host_rsp;
279 natural_width host_rip;
280 natural_width paddingl[8]; /* room for future expansion */
281 u32 pin_based_vm_exec_control;
282 u32 cpu_based_vm_exec_control;
283 u32 exception_bitmap;
284 u32 page_fault_error_code_mask;
285 u32 page_fault_error_code_match;
286 u32 cr3_target_count;
287 u32 vm_exit_controls;
288 u32 vm_exit_msr_store_count;
289 u32 vm_exit_msr_load_count;
290 u32 vm_entry_controls;
291 u32 vm_entry_msr_load_count;
292 u32 vm_entry_intr_info_field;
293 u32 vm_entry_exception_error_code;
294 u32 vm_entry_instruction_len;
295 u32 tpr_threshold;
296 u32 secondary_vm_exec_control;
297 u32 vm_instruction_error;
298 u32 vm_exit_reason;
299 u32 vm_exit_intr_info;
300 u32 vm_exit_intr_error_code;
301 u32 idt_vectoring_info_field;
302 u32 idt_vectoring_error_code;
303 u32 vm_exit_instruction_len;
304 u32 vmx_instruction_info;
305 u32 guest_es_limit;
306 u32 guest_cs_limit;
307 u32 guest_ss_limit;
308 u32 guest_ds_limit;
309 u32 guest_fs_limit;
310 u32 guest_gs_limit;
311 u32 guest_ldtr_limit;
312 u32 guest_tr_limit;
313 u32 guest_gdtr_limit;
314 u32 guest_idtr_limit;
315 u32 guest_es_ar_bytes;
316 u32 guest_cs_ar_bytes;
317 u32 guest_ss_ar_bytes;
318 u32 guest_ds_ar_bytes;
319 u32 guest_fs_ar_bytes;
320 u32 guest_gs_ar_bytes;
321 u32 guest_ldtr_ar_bytes;
322 u32 guest_tr_ar_bytes;
323 u32 guest_interruptibility_info;
324 u32 guest_activity_state;
325 u32 guest_sysenter_cs;
326 u32 host_ia32_sysenter_cs;
0238ea91
JK		 327 u32 vmx_preemption_timer_value;
328 u32 padding32[7]; /* room for future expansion */
22bd0358
NHE		 329 u16 virtual_processor_id;
330 u16 guest_es_selector;
331 u16 guest_cs_selector;
332 u16 guest_ss_selector;
333 u16 guest_ds_selector;
334 u16 guest_fs_selector;
335 u16 guest_gs_selector;
336 u16 guest_ldtr_selector;
337 u16 guest_tr_selector;
338 u16 host_es_selector;
339 u16 host_cs_selector;
340 u16 host_ss_selector;
341 u16 host_ds_selector;
342 u16 host_fs_selector;
343 u16 host_gs_selector;
344 u16 host_tr_selector;
a9d30f33
NHE		 345};
346
347/*
348 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
349 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
350 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
351 */
352#define VMCS12_REVISION 0x11e57ed0
353
354/*
355 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
356 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
357 * current implementation, 4K are reserved to avoid future complications.
358 */
359#define VMCS12_SIZE 0x1000
360
ff2f6fe9
NHE		 361/* Used to remember the last vmcs02 used for some recently used vmcs12s */
362struct vmcs02_list {
363 struct list_head list;
364 gpa_t vmptr;
365 struct loaded_vmcs vmcs02;
366};
367
ec378aee
NHE		 368/*
369 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
370 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
371 */
372struct nested_vmx {
373 /* Has the level1 guest done vmxon? */
374 bool vmxon;
3573e22c 375 gpa_t vmxon_ptr;
a9d30f33
NHE		 376
377 /* The guest-physical address of the current VMCS L1 keeps for L2 */
378 gpa_t current_vmptr;
379 /* The host-usable pointer to the above */
380 struct page *current_vmcs12_page;
381 struct vmcs12 *current_vmcs12;
8de48833 382 struct vmcs *current_shadow_vmcs;
012f83cb
AG		 383 /*
384 * Indicates if the shadow vmcs must be updated with the
385 * data hold by vmcs12
386 */
387 bool sync_shadow_vmcs;
ff2f6fe9
NHE		 388
389 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
390 struct list_head vmcs02_pool;
391 int vmcs02_num;
fe3ef05c 392 u64 vmcs01_tsc_offset;
644d711a
NHE		 393 /* L2 must run next, and mustn't decide to exit to L1. */
394 bool nested_run_pending;
fe3ef05c
NHE		 395 /*
396 * Guest pages referred to in vmcs02 with host-physical pointers, so
397 * we must keep them pinned while L2 runs.
398 */
399 struct page *apic_access_page;
b3897a49 400 u64 msr_ia32_feature_control;
f4124500
JK		 401
402 struct hrtimer preemption_timer;
403 bool preemption_timer_expired;
2996fca0
JK		 404
405 /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
406 u64 vmcs01_debugctl;
ec378aee
NHE		 407};
408
01e439be
YZ		 409#define POSTED_INTR_ON 0
410/* Posted-Interrupt Descriptor */
411struct pi_desc {
412 u32 pir[8]; /* Posted interrupt requested */
413 u32 control; /* bit 0 of control is outstanding notification bit */
414 u32 rsvd[7];
415} __aligned(64);
416
a20ed54d
YZ		 417static bool pi_test_and_set_on(struct pi_desc *pi_desc)
418{
419 return test_and_set_bit(POSTED_INTR_ON,
420 (unsigned long *)&pi_desc->control);
421}
422
423static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
424{
425 return test_and_clear_bit(POSTED_INTR_ON,
426 (unsigned long *)&pi_desc->control);
427}
428
429static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
430{
431 return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
432}
433
a2fa3e9f 434struct vcpu_vmx {
fb3f0f51 435 struct kvm_vcpu vcpu;
313dbd49 436 unsigned long host_rsp;
29bd8a78 437 u8 fail;
9d58b931 438 bool nmi_known_unmasked;
51aa01d1 439 u32 exit_intr_info;
1155f76a 440 u32 idt_vectoring_info;
6de12732 441 ulong rflags;
26bb0981 442 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH		 443 int nmsrs;
444 int save_nmsrs;
a547c6db 445 unsigned long host_idt_base;
a2fa3e9f 446#ifdef CONFIG_X86_64
44ea2b17
AK		 447 u64 msr_host_kernel_gs_base;
448 u64 msr_guest_kernel_gs_base;
a2fa3e9f 449#endif
2961e876
GN		 450 u32 vm_entry_controls_shadow;
451 u32 vm_exit_controls_shadow;
d462b819
NHE		 452 /*
453 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
454 * non-nested (L1) guest, it always points to vmcs01. For a nested
455 * guest (L2), it points to a different VMCS.
456 */
457 struct loaded_vmcs vmcs01;
458 struct loaded_vmcs *loaded_vmcs;
459 bool __launched; /* temporary, used in vmx_vcpu_run */
61d2ef2c
AK		 460 struct msr_autoload {
461 unsigned nr;
462 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
463 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
464 } msr_autoload;
a2fa3e9f
GH		 465 struct {
466 int loaded;
467 u16 fs_sel, gs_sel, ldt_sel;
b2da15ac
AK		 468#ifdef CONFIG_X86_64
469 u16 ds_sel, es_sel;
470#endif
152d3f2f
LV		 471 int gs_ldt_reload_needed;
472 int fs_reload_needed;
da8999d3 473 u64 msr_host_bndcfgs;
d77c26fc 474 } host_state;
9c8cba37 475 struct {
7ffd92c5 476 int vm86_active;
78ac8b47 477 ulong save_rflags;
f5f7b2fe
AK		 478 struct kvm_segment segs[8];
479 } rmode;
480 struct {
481 u32 bitmask; /* 4 bits per segment (1 bit per field) */
7ffd92c5
AK		 482 struct kvm_save_segment {
483 u16 selector;
484 unsigned long base;
485 u32 limit;
486 u32 ar;
f5f7b2fe 487 } seg[8];
2fb92db1 488 } segment_cache;
2384d2b3 489 int vpid;
04fa4d32 490 bool emulation_required;
3b86cd99
JK		 491
492 /* Support for vnmi-less CPUs */
493 int soft_vnmi_blocked;
494 ktime_t entry_time;
495 s64 vnmi_blocked_time;
a0861c02 496 u32 exit_reason;
4e47c7a6
SY		 497
498 bool rdtscp_enabled;
ec378aee 499
01e439be
YZ		 500 /* Posted interrupt descriptor */
501 struct pi_desc pi_desc;
502
ec378aee
NHE		 503 /* Support for a guest hypervisor (nested VMX) */
504 struct nested_vmx nested;
a7653ecd
RK		 505
506 /* Dynamic PLE window. */
507 int ple_window;
508 bool ple_window_dirty;
a2fa3e9f
GH		 509};
510
2fb92db1
AK		 511enum segment_cache_field {
512 SEG_FIELD_SEL = 0,
513 SEG_FIELD_BASE = 1,
514 SEG_FIELD_LIMIT = 2,
515 SEG_FIELD_AR = 3,
516
517 SEG_FIELD_NR = 4
518};
519
a2fa3e9f
GH		 520static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
521{
fb3f0f51 522 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 523}
524
22bd0358
NHE		 525#define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
526#define FIELD(number, name) [number] = VMCS12_OFFSET(name)
527#define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
528 [number##_HIGH] = VMCS12_OFFSET(name)+4
529
4607c2d7 530
fe2b201b 531static unsigned long shadow_read_only_fields[] = {
4607c2d7
AG		 532 /*
533 * We do NOT shadow fields that are modified when L0
534 * traps and emulates any vmx instruction (e.g. VMPTRLD,
535 * VMXON...) executed by L1.
536 * For example, VM_INSTRUCTION_ERROR is read
537 * by L1 if a vmx instruction fails (part of the error path).
538 * Note the code assumes this logic. If for some reason
539 * we start shadowing these fields then we need to
540 * force a shadow sync when L0 emulates vmx instructions
541 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
542 * by nested_vmx_failValid)
543 */
544 VM_EXIT_REASON,
545 VM_EXIT_INTR_INFO,
546 VM_EXIT_INSTRUCTION_LEN,
547 IDT_VECTORING_INFO_FIELD,
548 IDT_VECTORING_ERROR_CODE,
549 VM_EXIT_INTR_ERROR_CODE,
550 EXIT_QUALIFICATION,
551 GUEST_LINEAR_ADDRESS,
552 GUEST_PHYSICAL_ADDRESS
553};
fe2b201b 554static int max_shadow_read_only_fields =
4607c2d7
AG		 555 ARRAY_SIZE(shadow_read_only_fields);
556
fe2b201b 557static unsigned long shadow_read_write_fields[] = {
4607c2d7
AG		 558 GUEST_RIP,
559 GUEST_RSP,
560 GUEST_CR0,
561 GUEST_CR3,
562 GUEST_CR4,
563 GUEST_INTERRUPTIBILITY_INFO,
564 GUEST_RFLAGS,
565 GUEST_CS_SELECTOR,
566 GUEST_CS_AR_BYTES,
567 GUEST_CS_LIMIT,
568 GUEST_CS_BASE,
569 GUEST_ES_BASE,
36be0b9d 570 GUEST_BNDCFGS,
4607c2d7
AG		 571 CR0_GUEST_HOST_MASK,
572 CR0_READ_SHADOW,
573 CR4_READ_SHADOW,
574 TSC_OFFSET,
575 EXCEPTION_BITMAP,
576 CPU_BASED_VM_EXEC_CONTROL,
577 VM_ENTRY_EXCEPTION_ERROR_CODE,
578 VM_ENTRY_INTR_INFO_FIELD,
579 VM_ENTRY_INSTRUCTION_LEN,
580 VM_ENTRY_EXCEPTION_ERROR_CODE,
581 HOST_FS_BASE,
582 HOST_GS_BASE,
583 HOST_FS_SELECTOR,
584 HOST_GS_SELECTOR
585};
fe2b201b 586static int max_shadow_read_write_fields =
4607c2d7
AG		 587 ARRAY_SIZE(shadow_read_write_fields);
588
772e0318 589static const unsigned short vmcs_field_to_offset_table[] = {
22bd0358
NHE		 590 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
591 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
592 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
593 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
594 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
595 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
596 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
597 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
598 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
599 FIELD(HOST_ES_SELECTOR, host_es_selector),
600 FIELD(HOST_CS_SELECTOR, host_cs_selector),
601 FIELD(HOST_SS_SELECTOR, host_ss_selector),
602 FIELD(HOST_DS_SELECTOR, host_ds_selector),
603 FIELD(HOST_FS_SELECTOR, host_fs_selector),
604 FIELD(HOST_GS_SELECTOR, host_gs_selector),
605 FIELD(HOST_TR_SELECTOR, host_tr_selector),
606 FIELD64(IO_BITMAP_A, io_bitmap_a),
607 FIELD64(IO_BITMAP_B, io_bitmap_b),
608 FIELD64(MSR_BITMAP, msr_bitmap),
609 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
610 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
611 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
612 FIELD64(TSC_OFFSET, tsc_offset),
613 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
614 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
615 FIELD64(EPT_POINTER, ept_pointer),
616 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
617 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
618 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
619 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
620 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
621 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
622 FIELD64(GUEST_PDPTR0, guest_pdptr0),
623 FIELD64(GUEST_PDPTR1, guest_pdptr1),
624 FIELD64(GUEST_PDPTR2, guest_pdptr2),
625 FIELD64(GUEST_PDPTR3, guest_pdptr3),
36be0b9d 626 FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
22bd0358
NHE		 627 FIELD64(HOST_IA32_PAT, host_ia32_pat),
628 FIELD64(HOST_IA32_EFER, host_ia32_efer),
629 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
630 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
631 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
632 FIELD(EXCEPTION_BITMAP, exception_bitmap),
633 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
634 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
635 FIELD(CR3_TARGET_COUNT, cr3_target_count),
636 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
637 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
638 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
639 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
640 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
641 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
642 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
643 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
644 FIELD(TPR_THRESHOLD, tpr_threshold),
645 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
646 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
647 FIELD(VM_EXIT_REASON, vm_exit_reason),
648 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
649 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
650 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
651 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
652 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
653 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
654 FIELD(GUEST_ES_LIMIT, guest_es_limit),
655 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
656 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
657 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
658 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
659 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
660 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
661 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
662 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
663 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
664 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
665 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
666 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
667 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
668 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
669 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
670 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
671 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
672 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
673 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
674 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
675 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
0238ea91 676 FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
22bd0358
NHE		 677 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
678 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
679 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
680 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
681 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
682 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
683 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
684 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
685 FIELD(EXIT_QUALIFICATION, exit_qualification),
686 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
687 FIELD(GUEST_CR0, guest_cr0),
688 FIELD(GUEST_CR3, guest_cr3),
689 FIELD(GUEST_CR4, guest_cr4),
690 FIELD(GUEST_ES_BASE, guest_es_base),
691 FIELD(GUEST_CS_BASE, guest_cs_base),
692 FIELD(GUEST_SS_BASE, guest_ss_base),
693 FIELD(GUEST_DS_BASE, guest_ds_base),
694 FIELD(GUEST_FS_BASE, guest_fs_base),
695 FIELD(GUEST_GS_BASE, guest_gs_base),
696 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
697 FIELD(GUEST_TR_BASE, guest_tr_base),
698 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
699 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
700 FIELD(GUEST_DR7, guest_dr7),
701 FIELD(GUEST_RSP, guest_rsp),
702 FIELD(GUEST_RIP, guest_rip),
703 FIELD(GUEST_RFLAGS, guest_rflags),
704 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
705 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
706 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
707 FIELD(HOST_CR0, host_cr0),
708 FIELD(HOST_CR3, host_cr3),
709 FIELD(HOST_CR4, host_cr4),
710 FIELD(HOST_FS_BASE, host_fs_base),
711 FIELD(HOST_GS_BASE, host_gs_base),
712 FIELD(HOST_TR_BASE, host_tr_base),
713 FIELD(HOST_GDTR_BASE, host_gdtr_base),
714 FIELD(HOST_IDTR_BASE, host_idtr_base),
715 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
716 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
717 FIELD(HOST_RSP, host_rsp),
718 FIELD(HOST_RIP, host_rip),
719};
720static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
721
722static inline short vmcs_field_to_offset(unsigned long field)
723{
724 if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
725 return -1;
726 return vmcs_field_to_offset_table[field];
727}
728
a9d30f33
NHE		 729static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
730{
731 return to_vmx(vcpu)->nested.current_vmcs12;
732}
733
734static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
735{
736 struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
32cad84f 737 if (is_error_page(page))
a9d30f33 738 return NULL;
32cad84f 739
a9d30f33
NHE		 740 return page;
741}
742
743static void nested_release_page(struct page *page)
744{
745 kvm_release_page_dirty(page);
746}
747
748static void nested_release_page_clean(struct page *page)
749{
750 kvm_release_page_clean(page);
751}
752
bfd0a56b 753static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
4e1096d2 754static u64 construct_eptp(unsigned long root_hpa);
4610c9cc
DX		 755static void kvm_cpu_vmxon(u64 addr);
756static void kvm_cpu_vmxoff(void);
93c4adc7 757static bool vmx_mpx_supported(void);
776e58ea 758static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
b246dd5d
OW		 759static void vmx_set_segment(struct kvm_vcpu *vcpu,
760 struct kvm_segment *var, int seg);
761static void vmx_get_segment(struct kvm_vcpu *vcpu,
762 struct kvm_segment *var, int seg);
d99e4152
GN		 763static bool guest_state_valid(struct kvm_vcpu *vcpu);
764static u32 vmx_segment_access_rights(struct kvm_segment *var);
a20ed54d 765static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu);
c3114420 766static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
16f5b903 767static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
75880a01 768
6aa8b732
AK		 769static DEFINE_PER_CPU(struct vmcs *, vmxarea);
770static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
d462b819
NHE		 771/*
772 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
773 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
774 */
775static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
3444d7da 776static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
6aa8b732 777
3e7c73e9
AK		 778static unsigned long *vmx_io_bitmap_a;
779static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 780static unsigned long *vmx_msr_bitmap_legacy;
781static unsigned long *vmx_msr_bitmap_longmode;
8d14695f
YZ		 782static unsigned long *vmx_msr_bitmap_legacy_x2apic;
783static unsigned long *vmx_msr_bitmap_longmode_x2apic;
4607c2d7
AG		 784static unsigned long *vmx_vmread_bitmap;
785static unsigned long *vmx_vmwrite_bitmap;
fdef3ad1 786
110312c8 787static bool cpu_has_load_ia32_efer;
8bf00a52 788static bool cpu_has_load_perf_global_ctrl;
110312c8 789
2384d2b3
SY		 790static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
791static DEFINE_SPINLOCK(vmx_vpid_lock);
792
1c3d14fe 793static struct vmcs_config {
6aa8b732
AK		 794 int size;
795 int order;
796 u32 revision_id;
1c3d14fe
YS		 797 u32 pin_based_exec_ctrl;
798 u32 cpu_based_exec_ctrl;
f78e0e2e 799 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 800 u32 vmexit_ctrl;
801 u32 vmentry_ctrl;
802} vmcs_config;
6aa8b732 803
efff9e53 804static struct vmx_capability {
d56f546d
SY		 805 u32 ept;
806 u32 vpid;
807} vmx_capability;
808
6aa8b732
AK		 809#define VMX_SEGMENT_FIELD(seg) \
810 [VCPU_SREG_##seg] = { \
811 .selector = GUEST_##seg##_SELECTOR, \
812 .base = GUEST_##seg##_BASE, \
813 .limit = GUEST_##seg##_LIMIT, \
814 .ar_bytes = GUEST_##seg##_AR_BYTES, \
815 }
816
772e0318 817static const struct kvm_vmx_segment_field {
6aa8b732
AK		 818 unsigned selector;
819 unsigned base;
820 unsigned limit;
821 unsigned ar_bytes;
822} kvm_vmx_segment_fields[] = {
823 VMX_SEGMENT_FIELD(CS),
824 VMX_SEGMENT_FIELD(DS),
825 VMX_SEGMENT_FIELD(ES),
826 VMX_SEGMENT_FIELD(FS),
827 VMX_SEGMENT_FIELD(GS),
828 VMX_SEGMENT_FIELD(SS),
829 VMX_SEGMENT_FIELD(TR),
830 VMX_SEGMENT_FIELD(LDTR),
831};
832
26bb0981
AK		 833static u64 host_efer;
834
6de4f3ad
AK		 835static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
836
4d56c8a7 837/*
8c06585d 838 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
4d56c8a7
AK		 839 * away by decrementing the array size.
840 */
6aa8b732 841static const u32 vmx_msr_index[] = {
05b3e0c2 842#ifdef CONFIG_X86_64
44ea2b17 843 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 844#endif
8c06585d 845 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
6aa8b732 846};
6aa8b732 847
31299944 848static inline bool is_page_fault(u32 intr_info)
6aa8b732
AK		 849{
850 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
851 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 852 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 853}
854
31299944 855static inline bool is_no_device(u32 intr_info)
2ab455cc
AL		 856{
857 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
858 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 859 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 860}
861
31299944 862static inline bool is_invalid_opcode(u32 intr_info)
7aa81cc0
AL		 863{
864 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
865 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 866 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 867}
868
31299944 869static inline bool is_external_interrupt(u32 intr_info)
6aa8b732
AK		 870{
871 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
872 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
873}
874
31299944 875static inline bool is_machine_check(u32 intr_info)
a0861c02
AK		 876{
877 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
878 INTR_INFO_VALID_MASK)) ==
879 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
880}
881
31299944 882static inline bool cpu_has_vmx_msr_bitmap(void)
25c5f225 883{
04547156 884 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 885}
886
31299944 887static inline bool cpu_has_vmx_tpr_shadow(void)
6e5d865c 888{
04547156 889 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 890}
891
31299944 892static inline bool vm_need_tpr_shadow(struct kvm *kvm)
6e5d865c 893{
04547156 894 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
6e5d865c
YS		 895}
896
31299944 897static inline bool cpu_has_secondary_exec_ctrls(void)
f78e0e2e 898{
04547156
SY		 899 return vmcs_config.cpu_based_exec_ctrl &
900 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 901}
902
774ead3a 903static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 904{
04547156
SY		 905 return vmcs_config.cpu_based_2nd_exec_ctrl &
906 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
907}
908
8d14695f
YZ		 909static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
910{
911 return vmcs_config.cpu_based_2nd_exec_ctrl &
912 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
913}
914
83d4c286
YZ		 915static inline bool cpu_has_vmx_apic_register_virt(void)
916{
917 return vmcs_config.cpu_based_2nd_exec_ctrl &
918 SECONDARY_EXEC_APIC_REGISTER_VIRT;
919}
920
c7c9c56c
YZ		 921static inline bool cpu_has_vmx_virtual_intr_delivery(void)
922{
923 return vmcs_config.cpu_based_2nd_exec_ctrl &
924 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
925}
926
01e439be
YZ		 927static inline bool cpu_has_vmx_posted_intr(void)
928{
929 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
930}
931
932static inline bool cpu_has_vmx_apicv(void)
933{
934 return cpu_has_vmx_apic_register_virt() &&
935 cpu_has_vmx_virtual_intr_delivery() &&
936 cpu_has_vmx_posted_intr();
937}
938
04547156
SY		 939static inline bool cpu_has_vmx_flexpriority(void)
940{
941 return cpu_has_vmx_tpr_shadow() &&
942 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 943}
944
e799794e
MT		 945static inline bool cpu_has_vmx_ept_execute_only(void)
946{
31299944 947 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
e799794e
MT		 948}
949
950static inline bool cpu_has_vmx_eptp_uncacheable(void)
951{
31299944 952 return vmx_capability.ept & VMX_EPTP_UC_BIT;
e799794e
MT		 953}
954
955static inline bool cpu_has_vmx_eptp_writeback(void)
956{
31299944 957 return vmx_capability.ept & VMX_EPTP_WB_BIT;
e799794e
MT		 958}
959
960static inline bool cpu_has_vmx_ept_2m_page(void)
961{
31299944 962 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
e799794e
MT		 963}
964
878403b7
SY		 965static inline bool cpu_has_vmx_ept_1g_page(void)
966{
31299944 967 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
878403b7
SY		 968}
969
4bc9b982
SY		 970static inline bool cpu_has_vmx_ept_4levels(void)
971{
972 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
973}
974
83c3a331
XH		 975static inline bool cpu_has_vmx_ept_ad_bits(void)
976{
977 return vmx_capability.ept & VMX_EPT_AD_BIT;
978}
979
31299944 980static inline bool cpu_has_vmx_invept_context(void)
d56f546d 981{
31299944 982 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
d56f546d
SY		 983}
984
31299944 985static inline bool cpu_has_vmx_invept_global(void)
d56f546d 986{
31299944 987 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
d56f546d
SY		 988}
989
518c8aee
GJ		 990static inline bool cpu_has_vmx_invvpid_single(void)
991{
992 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
993}
994
b9d762fa
GJ		 995static inline bool cpu_has_vmx_invvpid_global(void)
996{
997 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
998}
999
31299944 1000static inline bool cpu_has_vmx_ept(void)
d56f546d 1001{
04547156
SY		 1002 return vmcs_config.cpu_based_2nd_exec_ctrl &
1003 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 1004}
1005
31299944 1006static inline bool cpu_has_vmx_unrestricted_guest(void)
3a624e29
NK		 1007{
1008 return vmcs_config.cpu_based_2nd_exec_ctrl &
1009 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1010}
1011
31299944 1012static inline bool cpu_has_vmx_ple(void)
4b8d54f9
ZE		 1013{
1014 return vmcs_config.cpu_based_2nd_exec_ctrl &
1015 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1016}
1017
31299944 1018static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
f78e0e2e 1019{
6d3e435e 1020 return flexpriority_enabled && irqchip_in_kernel(kvm);
f78e0e2e
SY		 1021}
1022
31299944 1023static inline bool cpu_has_vmx_vpid(void)
2384d2b3 1024{
04547156
SY		 1025 return vmcs_config.cpu_based_2nd_exec_ctrl &
1026 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 1027}
1028
31299944 1029static inline bool cpu_has_vmx_rdtscp(void)
4e47c7a6
SY		 1030{
1031 return vmcs_config.cpu_based_2nd_exec_ctrl &
1032 SECONDARY_EXEC_RDTSCP;
1033}
1034
ad756a16
MJ		 1035static inline bool cpu_has_vmx_invpcid(void)
1036{
1037 return vmcs_config.cpu_based_2nd_exec_ctrl &
1038 SECONDARY_EXEC_ENABLE_INVPCID;
1039}
1040
31299944 1041static inline bool cpu_has_virtual_nmis(void)
f08864b4
SY		 1042{
1043 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1044}
1045
f5f48ee1
SY		 1046static inline bool cpu_has_vmx_wbinvd_exit(void)
1047{
1048 return vmcs_config.cpu_based_2nd_exec_ctrl &
1049 SECONDARY_EXEC_WBINVD_EXITING;
1050}
1051
abc4fc58
AG		 1052static inline bool cpu_has_vmx_shadow_vmcs(void)
1053{
1054 u64 vmx_msr;
1055 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1056 /* check if the cpu supports writing r/o exit information fields */
1057 if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1058 return false;
1059
1060 return vmcs_config.cpu_based_2nd_exec_ctrl &
1061 SECONDARY_EXEC_SHADOW_VMCS;
1062}
1063
04547156
SY		 1064static inline bool report_flexpriority(void)
1065{
1066 return flexpriority_enabled;
1067}
1068
fe3ef05c
NHE		 1069static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1070{
1071 return vmcs12->cpu_based_vm_exec_control & bit;
1072}
1073
1074static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1075{
1076 return (vmcs12->cpu_based_vm_exec_control &
1077 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1078 (vmcs12->secondary_vm_exec_control & bit);
1079}
1080
f5c4368f 1081static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
644d711a
NHE		 1082{
1083 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1084}
1085
f4124500
JK		 1086static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1087{
1088 return vmcs12->pin_based_vm_exec_control &
1089 PIN_BASED_VMX_PREEMPTION_TIMER;
1090}
1091
155a97a3
NHE		 1092static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1093{
1094 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1095}
1096
644d711a
NHE		 1097static inline bool is_exception(u32 intr_info)
1098{
1099 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1100 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1101}
1102
533558bc
JK		 1103static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1104 u32 exit_intr_info,
1105 unsigned long exit_qualification);
7c177938
NHE		 1106static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1107 struct vmcs12 *vmcs12,
1108 u32 reason, unsigned long qualification);
1109
8b9cf98c 1110static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 1111{
1112 int i;
1113
a2fa3e9f 1114 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 1115 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 1116 return i;
1117 return -1;
1118}
1119
2384d2b3
SY		 1120static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1121{
1122 struct {
1123 u64 vpid : 16;
1124 u64 rsvd : 48;
1125 u64 gva;
1126 } operand = { vpid, 0, gva };
1127
4ecac3fd 1128 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 1129 /* CF==1 or ZF==1 --> rc = -1 */
1130 "; ja 1f ; ud2 ; 1:"
1131 : : "a"(&operand), "c"(ext) : "cc", "memory");
1132}
1133
1439442c
SY		 1134static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1135{
1136 struct {
1137 u64 eptp, gpa;
1138 } operand = {eptp, gpa};
1139
4ecac3fd 1140 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 1141 /* CF==1 or ZF==1 --> rc = -1 */
1142 "; ja 1f ; ud2 ; 1:\n"
1143 : : "a" (&operand), "c" (ext) : "cc", "memory");
1144}
1145
26bb0981 1146static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 1147{
1148 int i;
1149
8b9cf98c 1150 i = __find_msr_index(vmx, msr);
a75beee6 1151 if (i >= 0)
a2fa3e9f 1152 return &vmx->guest_msrs[i];
8b6d44c7 1153 return NULL;
7725f0ba
AK		 1154}
1155
6aa8b732
AK		 1156static void vmcs_clear(struct vmcs *vmcs)
1157{
1158 u64 phys_addr = __pa(vmcs);
1159 u8 error;
1160
4ecac3fd 1161 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
16d8f72f 1162 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
6aa8b732
AK		 1163 : "cc", "memory");
1164 if (error)
1165 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1166 vmcs, phys_addr);
1167}
1168
d462b819
NHE		 1169static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1170{
1171 vmcs_clear(loaded_vmcs->vmcs);
1172 loaded_vmcs->cpu = -1;
1173 loaded_vmcs->launched = 0;
1174}
1175
7725b894
DX		 1176static void vmcs_load(struct vmcs *vmcs)
1177{
1178 u64 phys_addr = __pa(vmcs);
1179 u8 error;
1180
1181 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
16d8f72f 1182 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
7725b894
DX		 1183 : "cc", "memory");
1184 if (error)
2844d849 1185 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
7725b894
DX		 1186 vmcs, phys_addr);
1187}
1188
8f536b76
ZY		 1189#ifdef CONFIG_KEXEC
1190/*
1191 * This bitmap is used to indicate whether the vmclear
1192 * operation is enabled on all cpus. All disabled by
1193 * default.
1194 */
1195static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1196
1197static inline void crash_enable_local_vmclear(int cpu)
1198{
1199 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1200}
1201
1202static inline void crash_disable_local_vmclear(int cpu)
1203{
1204 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1205}
1206
1207static inline int crash_local_vmclear_enabled(int cpu)
1208{
1209 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1210}
1211
1212static void crash_vmclear_local_loaded_vmcss(void)
1213{
1214 int cpu = raw_smp_processor_id();
1215 struct loaded_vmcs *v;
1216
1217 if (!crash_local_vmclear_enabled(cpu))
1218 return;
1219
1220 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1221 loaded_vmcss_on_cpu_link)
1222 vmcs_clear(v->vmcs);
1223}
1224#else
1225static inline void crash_enable_local_vmclear(int cpu) { }
1226static inline void crash_disable_local_vmclear(int cpu) { }
1227#endif /* CONFIG_KEXEC */
1228
d462b819 1229static void __loaded_vmcs_clear(void *arg)
6aa8b732 1230{
d462b819 1231 struct loaded_vmcs *loaded_vmcs = arg;
d3b2c338 1232 int cpu = raw_smp_processor_id();
6aa8b732 1233
d462b819
NHE		 1234 if (loaded_vmcs->cpu != cpu)
1235 return; /* vcpu migration can race with cpu offline */
1236 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
6aa8b732 1237 per_cpu(current_vmcs, cpu) = NULL;
8f536b76 1238 crash_disable_local_vmclear(cpu);
d462b819 1239 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
5a560f8b
XG		 1240
1241 /*
1242 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1243 * is before setting loaded_vmcs->vcpu to -1 which is done in
1244 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1245 * then adds the vmcs into percpu list before it is deleted.
1246 */
1247 smp_wmb();
1248
d462b819 1249 loaded_vmcs_init(loaded_vmcs);
8f536b76 1250 crash_enable_local_vmclear(cpu);
6aa8b732
AK		 1251}
1252
d462b819 1253static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
8d0be2b3 1254{
e6c7d321
XG		 1255 int cpu = loaded_vmcs->cpu;
1256
1257 if (cpu != -1)
1258 smp_call_function_single(cpu,
1259 __loaded_vmcs_clear, loaded_vmcs, 1);
8d0be2b3
AK		 1260}
1261
1760dd49 1262static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
2384d2b3
SY		 1263{
1264 if (vmx->vpid == 0)
1265 return;
1266
518c8aee
GJ		 1267 if (cpu_has_vmx_invvpid_single())
1268 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
2384d2b3
SY		 1269}
1270
b9d762fa
GJ		 1271static inline void vpid_sync_vcpu_global(void)
1272{
1273 if (cpu_has_vmx_invvpid_global())
1274 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1275}
1276
1277static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1278{
1279 if (cpu_has_vmx_invvpid_single())
1760dd49 1280 vpid_sync_vcpu_single(vmx);
b9d762fa
GJ		 1281 else
1282 vpid_sync_vcpu_global();
1283}
1284
1439442c
SY		 1285static inline void ept_sync_global(void)
1286{
1287 if (cpu_has_vmx_invept_global())
1288 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1289}
1290
1291static inline void ept_sync_context(u64 eptp)
1292{
089d034e 1293 if (enable_ept) {
1439442c
SY		 1294 if (cpu_has_vmx_invept_context())
1295 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1296 else
1297 ept_sync_global();
1298 }
1299}
1300
96304217 1301static __always_inline unsigned long vmcs_readl(unsigned long field)
6aa8b732 1302{
5e520e62 1303 unsigned long value;
6aa8b732 1304
5e520e62
AK		 1305 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1306 : "=a"(value) : "d"(field) : "cc");
6aa8b732
AK		 1307 return value;
1308}
1309
96304217 1310static __always_inline u16 vmcs_read16(unsigned long field)
6aa8b732
AK		 1311{
1312 return vmcs_readl(field);
1313}
1314
96304217 1315static __always_inline u32 vmcs_read32(unsigned long field)
6aa8b732
AK		 1316{
1317 return vmcs_readl(field);
1318}
1319
96304217 1320static __always_inline u64 vmcs_read64(unsigned long field)
6aa8b732 1321{
05b3e0c2 1322#ifdef CONFIG_X86_64
6aa8b732
AK		 1323 return vmcs_readl(field);
1324#else
1325 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1326#endif
1327}
1328
e52de1b8
AK		 1329static noinline void vmwrite_error(unsigned long field, unsigned long value)
1330{
1331 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1332 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1333 dump_stack();
1334}
1335
6aa8b732
AK		 1336static void vmcs_writel(unsigned long field, unsigned long value)
1337{
1338 u8 error;
1339
4ecac3fd 1340 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 1341 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 1342 if (unlikely(error))
1343 vmwrite_error(field, value);
6aa8b732
AK		 1344}
1345
1346static void vmcs_write16(unsigned long field, u16 value)
1347{
1348 vmcs_writel(field, value);
1349}
1350
1351static void vmcs_write32(unsigned long field, u32 value)
1352{
1353 vmcs_writel(field, value);
1354}
1355
1356static void vmcs_write64(unsigned long field, u64 value)
1357{
6aa8b732 1358 vmcs_writel(field, value);
7682f2d0 1359#ifndef CONFIG_X86_64
6aa8b732
AK		 1360 asm volatile ("");
1361 vmcs_writel(field+1, value >> 32);
1362#endif
1363}
1364
2ab455cc
AL		 1365static void vmcs_clear_bits(unsigned long field, u32 mask)
1366{
1367 vmcs_writel(field, vmcs_readl(field) & ~mask);
1368}
1369
1370static void vmcs_set_bits(unsigned long field, u32 mask)
1371{
1372 vmcs_writel(field, vmcs_readl(field) | mask);
1373}
1374
2961e876
GN		 1375static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1376{
1377 vmcs_write32(VM_ENTRY_CONTROLS, val);
1378 vmx->vm_entry_controls_shadow = val;
1379}
1380
1381static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1382{
1383 if (vmx->vm_entry_controls_shadow != val)
1384 vm_entry_controls_init(vmx, val);
1385}
1386
1387static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1388{
1389 return vmx->vm_entry_controls_shadow;
1390}
1391
1392
1393static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1394{
1395 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1396}
1397
1398static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1399{
1400 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1401}
1402
1403static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1404{
1405 vmcs_write32(VM_EXIT_CONTROLS, val);
1406 vmx->vm_exit_controls_shadow = val;
1407}
1408
1409static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1410{
1411 if (vmx->vm_exit_controls_shadow != val)
1412 vm_exit_controls_init(vmx, val);
1413}
1414
1415static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1416{
1417 return vmx->vm_exit_controls_shadow;
1418}
1419
1420
1421static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1422{
1423 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1424}
1425
1426static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1427{
1428 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1429}
1430
2fb92db1
AK		 1431static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1432{
1433 vmx->segment_cache.bitmask = 0;
1434}
1435
1436static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1437 unsigned field)
1438{
1439 bool ret;
1440 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1441
1442 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1443 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1444 vmx->segment_cache.bitmask = 0;
1445 }
1446 ret = vmx->segment_cache.bitmask & mask;
1447 vmx->segment_cache.bitmask |= mask;
1448 return ret;
1449}
1450
1451static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1452{
1453 u16 *p = &vmx->segment_cache.seg[seg].selector;
1454
1455 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1456 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1457 return *p;
1458}
1459
1460static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1461{
1462 ulong *p = &vmx->segment_cache.seg[seg].base;
1463
1464 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1465 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1466 return *p;
1467}
1468
1469static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1470{
1471 u32 *p = &vmx->segment_cache.seg[seg].limit;
1472
1473 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1474 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1475 return *p;
1476}
1477
1478static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1479{
1480 u32 *p = &vmx->segment_cache.seg[seg].ar;
1481
1482 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1483 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1484 return *p;
1485}
1486
abd3f2d6
AK		 1487static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1488{
1489 u32 eb;
1490
fd7373cc
JK		 1491 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1492 (1u << NM_VECTOR) | (1u << DB_VECTOR);
1493 if ((vcpu->guest_debug &
1494 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1495 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1496 eb |= 1u << BP_VECTOR;
7ffd92c5 1497 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 1498 eb = ~0;
089d034e 1499 if (enable_ept)
1439442c 1500 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
02daab21
AK		 1501 if (vcpu->fpu_active)
1502 eb &= ~(1u << NM_VECTOR);
36cf24e0
NHE		 1503
1504 /* When we are running a nested L2 guest and L1 specified for it a
1505 * certain exception bitmap, we must trap the same exceptions and pass
1506 * them to L1. When running L2, we will only handle the exceptions
1507 * specified above if L1 did not want them.
1508 */
1509 if (is_guest_mode(vcpu))
1510 eb |= get_vmcs12(vcpu)->exception_bitmap;
1511
abd3f2d6
AK		 1512 vmcs_write32(EXCEPTION_BITMAP, eb);
1513}
1514
2961e876
GN		 1515static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1516 unsigned long entry, unsigned long exit)
8bf00a52 1517{
2961e876
GN		 1518 vm_entry_controls_clearbit(vmx, entry);
1519 vm_exit_controls_clearbit(vmx, exit);
8bf00a52
GN		 1520}
1521
61d2ef2c
AK		 1522static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1523{
1524 unsigned i;
1525 struct msr_autoload *m = &vmx->msr_autoload;
1526
8bf00a52
GN		 1527 switch (msr) {
1528 case MSR_EFER:
1529 if (cpu_has_load_ia32_efer) {
2961e876
GN		 1530 clear_atomic_switch_msr_special(vmx,
1531 VM_ENTRY_LOAD_IA32_EFER,
8bf00a52
GN		 1532 VM_EXIT_LOAD_IA32_EFER);
1533 return;
1534 }
1535 break;
1536 case MSR_CORE_PERF_GLOBAL_CTRL:
1537 if (cpu_has_load_perf_global_ctrl) {
2961e876 1538 clear_atomic_switch_msr_special(vmx,
8bf00a52
GN		 1539 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1540 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1541 return;
1542 }
1543 break;
110312c8
AK		 1544 }
1545
61d2ef2c
AK		 1546 for (i = 0; i < m->nr; ++i)
1547 if (m->guest[i].index == msr)
1548 break;
1549
1550 if (i == m->nr)
1551 return;
1552 --m->nr;
1553 m->guest[i] = m->guest[m->nr];
1554 m->host[i] = m->host[m->nr];
1555 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1556 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1557}
1558
2961e876
GN		 1559static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1560 unsigned long entry, unsigned long exit,
1561 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1562 u64 guest_val, u64 host_val)
8bf00a52
GN		 1563{
1564 vmcs_write64(guest_val_vmcs, guest_val);
1565 vmcs_write64(host_val_vmcs, host_val);
2961e876
GN		 1566 vm_entry_controls_setbit(vmx, entry);
1567 vm_exit_controls_setbit(vmx, exit);
8bf00a52
GN		 1568}
1569
61d2ef2c
AK		 1570static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1571 u64 guest_val, u64 host_val)
1572{
1573 unsigned i;
1574 struct msr_autoload *m = &vmx->msr_autoload;
1575
8bf00a52
GN		 1576 switch (msr) {
1577 case MSR_EFER:
1578 if (cpu_has_load_ia32_efer) {
2961e876
GN		 1579 add_atomic_switch_msr_special(vmx,
1580 VM_ENTRY_LOAD_IA32_EFER,
8bf00a52
GN		 1581 VM_EXIT_LOAD_IA32_EFER,
1582 GUEST_IA32_EFER,
1583 HOST_IA32_EFER,
1584 guest_val, host_val);
1585 return;
1586 }
1587 break;
1588 case MSR_CORE_PERF_GLOBAL_CTRL:
1589 if (cpu_has_load_perf_global_ctrl) {
2961e876 1590 add_atomic_switch_msr_special(vmx,
8bf00a52
GN		 1591 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1592 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1593 GUEST_IA32_PERF_GLOBAL_CTRL,
1594 HOST_IA32_PERF_GLOBAL_CTRL,
1595 guest_val, host_val);
1596 return;
1597 }
1598 break;
110312c8
AK		 1599 }
1600
61d2ef2c
AK		 1601 for (i = 0; i < m->nr; ++i)
1602 if (m->guest[i].index == msr)
1603 break;
1604
e7fc6f93 1605 if (i == NR_AUTOLOAD_MSRS) {
60266204 1606 printk_once(KERN_WARNING "Not enough msr switch entries. "
e7fc6f93
GN		 1607 "Can't add msr %x\n", msr);
1608 return;
1609 } else if (i == m->nr) {
61d2ef2c
AK		 1610 ++m->nr;
1611 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1612 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1613 }
1614
1615 m->guest[i].index = msr;
1616 m->guest[i].value = guest_val;
1617 m->host[i].index = msr;
1618 m->host[i].value = host_val;
1619}
1620
33ed6329
AK		 1621static void reload_tss(void)
1622{
33ed6329
AK		 1623 /*
1624 * VT restores TR but not its size. Useless.
1625 */
d359192f 1626 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
a5f61300 1627 struct desc_struct *descs;
33ed6329 1628
d359192f 1629 descs = (void *)gdt->address;
33ed6329
AK		 1630 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1631 load_TR_desc();
33ed6329
AK		 1632}
1633
92c0d900 1634static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 1635{
3a34a881 1636 u64 guest_efer;
51c6cf66
AK		 1637 u64 ignore_bits;
1638
f6801dff 1639 guest_efer = vmx->vcpu.arch.efer;
3a34a881 1640
51c6cf66 1641 /*
0fa06071 1642 * NX is emulated; LMA and LME handled by hardware; SCE meaningless
51c6cf66
AK		 1643 * outside long mode
1644 */
1645 ignore_bits = EFER_NX | EFER_SCE;
1646#ifdef CONFIG_X86_64
1647 ignore_bits |= EFER_LMA | EFER_LME;
1648 /* SCE is meaningful only in long mode on Intel */
1649 if (guest_efer & EFER_LMA)
1650 ignore_bits &= ~(u64)EFER_SCE;
1651#endif
51c6cf66
AK		 1652 guest_efer &= ~ignore_bits;
1653 guest_efer |= host_efer & ignore_bits;
26bb0981 1654 vmx->guest_msrs[efer_offset].data = guest_efer;
d5696725 1655 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef
AK		 1656
1657 clear_atomic_switch_msr(vmx, MSR_EFER);
1658 /* On ept, can't emulate nx, and must switch nx atomically */
1659 if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1660 guest_efer = vmx->vcpu.arch.efer;
1661 if (!(guest_efer & EFER_LMA))
1662 guest_efer &= ~EFER_LME;
1663 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1664 return false;
1665 }
1666
26bb0981 1667 return true;
51c6cf66
AK		 1668}
1669
2d49ec72
GN		 1670static unsigned long segment_base(u16 selector)
1671{
d359192f 1672 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
2d49ec72
GN		 1673 struct desc_struct *d;
1674 unsigned long table_base;
1675 unsigned long v;
1676
1677 if (!(selector & ~3))
1678 return 0;
1679
d359192f 1680 table_base = gdt->address;
2d49ec72
GN		 1681
1682 if (selector & 4) { /* from ldt */
1683 u16 ldt_selector = kvm_read_ldt();
1684
1685 if (!(ldt_selector & ~3))
1686 return 0;
1687
1688 table_base = segment_base(ldt_selector);
1689 }
1690 d = (struct desc_struct *)(table_base + (selector & ~7));
1691 v = get_desc_base(d);
1692#ifdef CONFIG_X86_64
1693 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1694 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1695#endif
1696 return v;
1697}
1698
1699static inline unsigned long kvm_read_tr_base(void)
1700{
1701 u16 tr;
1702 asm("str %0" : "=g"(tr));
1703 return segment_base(tr);
1704}
1705
04d2cc77 1706static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 1707{
04d2cc77 1708 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1709 int i;
04d2cc77 1710
a2fa3e9f 1711 if (vmx->host_state.loaded)
33ed6329
AK		 1712 return;
1713
a2fa3e9f 1714 vmx->host_state.loaded = 1;
33ed6329
AK		 1715 /*
1716 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1717 * allow segment selectors with cpl > 0 or ti == 1.
1718 */
d6e88aec 1719 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 1720 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
9581d442 1721 savesegment(fs, vmx->host_state.fs_sel);
152d3f2f 1722 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 1723 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 1724 vmx->host_state.fs_reload_needed = 0;
1725 } else {
33ed6329 1726 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 1727 vmx->host_state.fs_reload_needed = 1;
33ed6329 1728 }
9581d442 1729 savesegment(gs, vmx->host_state.gs_sel);
a2fa3e9f
GH		 1730 if (!(vmx->host_state.gs_sel & 7))
1731 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 1732 else {
1733 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 1734 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 1735 }
1736
b2da15ac
AK		 1737#ifdef CONFIG_X86_64
1738 savesegment(ds, vmx->host_state.ds_sel);
1739 savesegment(es, vmx->host_state.es_sel);
1740#endif
1741
33ed6329
AK		 1742#ifdef CONFIG_X86_64
1743 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1744 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1745#else
a2fa3e9f
GH		 1746 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1747 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 1748#endif
707c0874
AK		 1749
1750#ifdef CONFIG_X86_64
c8770e7b
AK		 1751 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1752 if (is_long_mode(&vmx->vcpu))
44ea2b17 1753 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
707c0874 1754#endif
da8999d3
LJ		 1755 if (boot_cpu_has(X86_FEATURE_MPX))
1756 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
26bb0981
AK		 1757 for (i = 0; i < vmx->save_nmsrs; ++i)
1758 kvm_set_shared_msr(vmx->guest_msrs[i].index,
d5696725
AK		 1759 vmx->guest_msrs[i].data,
1760 vmx->guest_msrs[i].mask);
33ed6329
AK		 1761}
1762
a9b21b62 1763static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 1764{
a2fa3e9f 1765 if (!vmx->host_state.loaded)
33ed6329
AK		 1766 return;
1767
e1beb1d3 1768 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 1769 vmx->host_state.loaded = 0;
c8770e7b
AK		 1770#ifdef CONFIG_X86_64
1771 if (is_long_mode(&vmx->vcpu))
1772 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1773#endif
152d3f2f 1774 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 1775 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329 1776#ifdef CONFIG_X86_64
9581d442 1777 load_gs_index(vmx->host_state.gs_sel);
9581d442
AK		 1778#else
1779 loadsegment(gs, vmx->host_state.gs_sel);
33ed6329 1780#endif
33ed6329 1781 }
0a77fe4c
AK		 1782 if (vmx->host_state.fs_reload_needed)
1783 loadsegment(fs, vmx->host_state.fs_sel);
b2da15ac
AK		 1784#ifdef CONFIG_X86_64
1785 if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1786 loadsegment(ds, vmx->host_state.ds_sel);
1787 loadsegment(es, vmx->host_state.es_sel);
1788 }
b2da15ac 1789#endif
152d3f2f 1790 reload_tss();
44ea2b17 1791#ifdef CONFIG_X86_64
c8770e7b 1792 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
44ea2b17 1793#endif
da8999d3
LJ		 1794 if (vmx->host_state.msr_host_bndcfgs)
1795 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
b1a74bf8
SS		 1796 /*
1797 * If the FPU is not active (through the host task or
1798 * the guest vcpu), then restore the cr0.TS bit.
1799 */
1800 if (!user_has_fpu() && !vmx->vcpu.guest_fpu_loaded)
1801 stts();
3444d7da 1802 load_gdt(&__get_cpu_var(host_gdt));
33ed6329
AK		 1803}
1804
a9b21b62
AK		 1805static void vmx_load_host_state(struct vcpu_vmx *vmx)
1806{
1807 preempt_disable();
1808 __vmx_load_host_state(vmx);
1809 preempt_enable();
1810}
1811
6aa8b732
AK		 1812/*
1813 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1814 * vcpu mutex is already taken.
1815 */
15ad7146 1816static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 1817{
a2fa3e9f 1818 struct vcpu_vmx *vmx = to_vmx(vcpu);
4610c9cc 1819 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
6aa8b732 1820
4610c9cc
DX		 1821 if (!vmm_exclusive)
1822 kvm_cpu_vmxon(phys_addr);
d462b819
NHE		 1823 else if (vmx->loaded_vmcs->cpu != cpu)
1824 loaded_vmcs_clear(vmx->loaded_vmcs);
6aa8b732 1825
d462b819
NHE		 1826 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1827 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1828 vmcs_load(vmx->loaded_vmcs->vmcs);
6aa8b732
AK		 1829 }
1830
d462b819 1831 if (vmx->loaded_vmcs->cpu != cpu) {
d359192f 1832 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
6aa8b732
AK		 1833 unsigned long sysenter_esp;
1834
a8eeb04a 1835 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
92fe13be 1836 local_irq_disable();
8f536b76 1837 crash_disable_local_vmclear(cpu);
5a560f8b
XG		 1838
1839 /*
1840 * Read loaded_vmcs->cpu should be before fetching
1841 * loaded_vmcs->loaded_vmcss_on_cpu_link.
1842 * See the comments in __loaded_vmcs_clear().
1843 */
1844 smp_rmb();
1845
d462b819
NHE		 1846 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1847 &per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76 1848 crash_enable_local_vmclear(cpu);
92fe13be
DX		 1849 local_irq_enable();
1850
6aa8b732
AK		 1851 /*
1852 * Linux uses per-cpu TSS and GDT, so set these when switching
1853 * processors.
1854 */
d6e88aec 1855 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
d359192f 1856 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
6aa8b732
AK		 1857
1858 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1859 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
d462b819 1860 vmx->loaded_vmcs->cpu = cpu;
6aa8b732 1861 }
6aa8b732
AK		 1862}
1863
1864static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1865{
a9b21b62 1866 __vmx_load_host_state(to_vmx(vcpu));
4610c9cc 1867 if (!vmm_exclusive) {
d462b819
NHE		 1868 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1869 vcpu->cpu = -1;
4610c9cc
DX		 1870 kvm_cpu_vmxoff();
1871 }
6aa8b732
AK		 1872}
1873
5fd86fcf
AK		 1874static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1875{
81231c69
AK		 1876 ulong cr0;
1877
5fd86fcf
AK		 1878 if (vcpu->fpu_active)
1879 return;
1880 vcpu->fpu_active = 1;
81231c69
AK		 1881 cr0 = vmcs_readl(GUEST_CR0);
1882 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1883 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1884 vmcs_writel(GUEST_CR0, cr0);
5fd86fcf 1885 update_exception_bitmap(vcpu);
edcafe3c 1886 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
36cf24e0
NHE		 1887 if (is_guest_mode(vcpu))
1888 vcpu->arch.cr0_guest_owned_bits &=
1889 ~get_vmcs12(vcpu)->cr0_guest_host_mask;
edcafe3c 1890 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
5fd86fcf
AK		 1891}
1892
edcafe3c
AK		 1893static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1894
fe3ef05c
NHE		 1895/*
1896 * Return the cr0 value that a nested guest would read. This is a combination
1897 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1898 * its hypervisor (cr0_read_shadow).
1899 */
1900static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1901{
1902 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1903 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1904}
1905static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1906{
1907 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1908 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1909}
1910
5fd86fcf
AK		 1911static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1912{
36cf24e0
NHE		 1913 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1914 * set this *before* calling this function.
1915 */
edcafe3c 1916 vmx_decache_cr0_guest_bits(vcpu);
81231c69 1917 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
5fd86fcf 1918 update_exception_bitmap(vcpu);
edcafe3c
AK		 1919 vcpu->arch.cr0_guest_owned_bits = 0;
1920 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
36cf24e0
NHE		 1921 if (is_guest_mode(vcpu)) {
1922 /*
1923 * L1's specified read shadow might not contain the TS bit,
1924 * so now that we turned on shadowing of this bit, we need to
1925 * set this bit of the shadow. Like in nested_vmx_run we need
1926 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1927 * up-to-date here because we just decached cr0.TS (and we'll
1928 * only update vmcs12->guest_cr0 on nested exit).
1929 */
1930 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1931 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1932 (vcpu->arch.cr0 & X86_CR0_TS);
1933 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1934 } else
1935 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf
AK		 1936}
1937
6aa8b732
AK		 1938static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1939{
78ac8b47 1940 unsigned long rflags, save_rflags;
345dcaa8 1941
6de12732
AK		 1942 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1943 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1944 rflags = vmcs_readl(GUEST_RFLAGS);
1945 if (to_vmx(vcpu)->rmode.vm86_active) {
1946 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1947 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1948 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1949 }
1950 to_vmx(vcpu)->rflags = rflags;
78ac8b47 1951 }
6de12732 1952 return to_vmx(vcpu)->rflags;
6aa8b732
AK		 1953}
1954
1955static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1956{
6de12732
AK		 1957 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1958 to_vmx(vcpu)->rflags = rflags;
78ac8b47
AK		 1959 if (to_vmx(vcpu)->rmode.vm86_active) {
1960 to_vmx(vcpu)->rmode.save_rflags = rflags;
053de044 1961 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 1962 }
6aa8b732
AK		 1963 vmcs_writel(GUEST_RFLAGS, rflags);
1964}
1965
37ccdcbe 1966static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2809f5d2
GC		 1967{
1968 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1969 int ret = 0;
1970
1971 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 1972 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 1973 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 1974 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2 1975
37ccdcbe 1976 return ret;
2809f5d2
GC		 1977}
1978
1979static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1980{
1981 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1982 u32 interruptibility = interruptibility_old;
1983
1984 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1985
48005f64 1986 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 1987 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 1988 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC		 1989 interruptibility |= GUEST_INTR_STATE_STI;
1990
1991 if ((interruptibility != interruptibility_old))
1992 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1993}
1994
6aa8b732
AK		 1995static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1996{
1997 unsigned long rip;
6aa8b732 1998
5fdbf976 1999 rip = kvm_rip_read(vcpu);
6aa8b732 2000 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 2001 kvm_rip_write(vcpu, rip);
6aa8b732 2002
2809f5d2
GC		 2003 /* skipping an emulated instruction also counts */
2004 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 2005}
2006
0b6ac343
NHE		 2007/*
2008 * KVM wants to inject page-faults which it got to the guest. This function
2009 * checks whether in a nested guest, we need to inject them to L1 or L2.
0b6ac343 2010 */
e011c663 2011static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
0b6ac343
NHE		 2012{
2013 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2014
e011c663 2015 if (!(vmcs12->exception_bitmap & (1u << nr)))
0b6ac343
NHE		 2016 return 0;
2017
533558bc
JK		 2018 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
2019 vmcs_read32(VM_EXIT_INTR_INFO),
2020 vmcs_readl(EXIT_QUALIFICATION));
0b6ac343
NHE		 2021 return 1;
2022}
2023
298101da 2024static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 2025 bool has_error_code, u32 error_code,
2026 bool reinject)
298101da 2027{
77ab6db0 2028 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 2029 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 2030
e011c663
GN		 2031 if (!reinject && is_guest_mode(vcpu) &&
2032 nested_vmx_check_exception(vcpu, nr))
0b6ac343
NHE		 2033 return;
2034
8ab2d2e2 2035 if (has_error_code) {
77ab6db0 2036 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 2037 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2038 }
77ab6db0 2039
7ffd92c5 2040 if (vmx->rmode.vm86_active) {
71f9833b
SH		 2041 int inc_eip = 0;
2042 if (kvm_exception_is_soft(nr))
2043 inc_eip = vcpu->arch.event_exit_inst_len;
2044 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
a92601bb 2045 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
77ab6db0
JK		 2046 return;
2047 }
2048
66fd3f7f
GN		 2049 if (kvm_exception_is_soft(nr)) {
2050 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2051 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 2052 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2053 } else
2054 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2055
2056 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
298101da
AK		 2057}
2058
4e47c7a6
SY		 2059static bool vmx_rdtscp_supported(void)
2060{
2061 return cpu_has_vmx_rdtscp();
2062}
2063
ad756a16
MJ		 2064static bool vmx_invpcid_supported(void)
2065{
2066 return cpu_has_vmx_invpcid() && enable_ept;
2067}
2068
a75beee6
ED		 2069/*
2070 * Swap MSR entry in host/guest MSR entry array.
2071 */
8b9cf98c 2072static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 2073{
26bb0981 2074 struct shared_msr_entry tmp;
a2fa3e9f
GH		 2075
2076 tmp = vmx->guest_msrs[to];
2077 vmx->guest_msrs[to] = vmx->guest_msrs[from];
2078 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 2079}
2080
8d14695f
YZ		 2081static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2082{
2083 unsigned long *msr_bitmap;
2084
2085 if (irqchip_in_kernel(vcpu->kvm) && apic_x2apic_mode(vcpu->arch.apic)) {
2086 if (is_long_mode(vcpu))
2087 msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2088 else
2089 msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2090 } else {
2091 if (is_long_mode(vcpu))
2092 msr_bitmap = vmx_msr_bitmap_longmode;
2093 else
2094 msr_bitmap = vmx_msr_bitmap_legacy;
2095 }
2096
2097 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2098}
2099
e38aea3e
AK		 2100/*
2101 * Set up the vmcs to automatically save and restore system
2102 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
2103 * mode, as fiddling with msrs is very expensive.
2104 */
8b9cf98c 2105static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 2106{
26bb0981 2107 int save_nmsrs, index;
e38aea3e 2108
a75beee6
ED		 2109 save_nmsrs = 0;
2110#ifdef CONFIG_X86_64
8b9cf98c 2111 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 2112 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 2113 if (index >= 0)
8b9cf98c
RR		 2114 move_msr_up(vmx, index, save_nmsrs++);
2115 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 2116 if (index >= 0)
8b9cf98c
RR		 2117 move_msr_up(vmx, index, save_nmsrs++);
2118 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 2119 if (index >= 0)
8b9cf98c 2120 move_msr_up(vmx, index, save_nmsrs++);
4e47c7a6
SY		 2121 index = __find_msr_index(vmx, MSR_TSC_AUX);
2122 if (index >= 0 && vmx->rdtscp_enabled)
2123 move_msr_up(vmx, index, save_nmsrs++);
a75beee6 2124 /*
8c06585d 2125 * MSR_STAR is only needed on long mode guests, and only
a75beee6
ED		 2126 * if efer.sce is enabled.
2127 */
8c06585d 2128 index = __find_msr_index(vmx, MSR_STAR);
f6801dff 2129 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
8b9cf98c 2130 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 2131 }
2132#endif
92c0d900
AK		 2133 index = __find_msr_index(vmx, MSR_EFER);
2134 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 2135 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 2136
26bb0981 2137 vmx->save_nmsrs = save_nmsrs;
5897297b 2138
8d14695f
YZ		 2139 if (cpu_has_vmx_msr_bitmap())
2140 vmx_set_msr_bitmap(&vmx->vcpu);
e38aea3e
AK		 2141}
2142
6aa8b732
AK		 2143/*
2144 * reads and returns guest's timestamp counter "register"
2145 * guest_tsc = host_tsc + tsc_offset -- 21.3
2146 */
2147static u64 guest_read_tsc(void)
2148{
2149 u64 host_tsc, tsc_offset;
2150
2151 rdtscll(host_tsc);
2152 tsc_offset = vmcs_read64(TSC_OFFSET);
2153 return host_tsc + tsc_offset;
2154}
2155
d5c1785d
NHE		 2156/*
2157 * Like guest_read_tsc, but always returns L1's notion of the timestamp
2158 * counter, even if a nested guest (L2) is currently running.
2159 */
886b470c 2160u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
d5c1785d 2161{
886b470c 2162 u64 tsc_offset;
d5c1785d 2163
d5c1785d
NHE		 2164 tsc_offset = is_guest_mode(vcpu) ?
2165 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2166 vmcs_read64(TSC_OFFSET);
2167 return host_tsc + tsc_offset;
2168}
2169
4051b188 2170/*
cc578287
ZA		 2171 * Engage any workarounds for mis-matched TSC rates. Currently limited to
2172 * software catchup for faster rates on slower CPUs.
4051b188 2173 */
cc578287 2174static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
4051b188 2175{
cc578287
ZA		 2176 if (!scale)
2177 return;
2178
2179 if (user_tsc_khz > tsc_khz) {
2180 vcpu->arch.tsc_catchup = 1;
2181 vcpu->arch.tsc_always_catchup = 1;
2182 } else
2183 WARN(1, "user requested TSC rate below hardware speed\n");
4051b188
JR		 2184}
2185
ba904635
WA		 2186static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2187{
2188 return vmcs_read64(TSC_OFFSET);
2189}
2190
6aa8b732 2191/*
99e3e30a 2192 * writes 'offset' into guest's timestamp counter offset register
6aa8b732 2193 */
99e3e30a 2194static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
6aa8b732 2195{
27fc51b2 2196 if (is_guest_mode(vcpu)) {
7991825b 2197 /*
27fc51b2
NHE		 2198 * We're here if L1 chose not to trap WRMSR to TSC. According
2199 * to the spec, this should set L1's TSC; The offset that L1
2200 * set for L2 remains unchanged, and still needs to be added
2201 * to the newly set TSC to get L2's TSC.
7991825b 2202 */
27fc51b2
NHE		 2203 struct vmcs12 *vmcs12;
2204 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2205 /* recalculate vmcs02.TSC_OFFSET: */
2206 vmcs12 = get_vmcs12(vcpu);
2207 vmcs_write64(TSC_OFFSET, offset +
2208 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2209 vmcs12->tsc_offset : 0));
2210 } else {
489223ed
YY		 2211 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2212 vmcs_read64(TSC_OFFSET), offset);
27fc51b2
NHE		 2213 vmcs_write64(TSC_OFFSET, offset);
2214 }
6aa8b732
AK		 2215}
2216
f1e2b260 2217static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
e48672fa
ZA		 2218{
2219 u64 offset = vmcs_read64(TSC_OFFSET);
489223ed 2220
e48672fa 2221 vmcs_write64(TSC_OFFSET, offset + adjustment);
7991825b
NHE		 2222 if (is_guest_mode(vcpu)) {
2223 /* Even when running L2, the adjustment needs to apply to L1 */
2224 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
489223ed
YY		 2225 } else
2226 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2227 offset + adjustment);
e48672fa
ZA		 2228}
2229
857e4099
JR		 2230static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2231{
2232 return target_tsc - native_read_tsc();
2233}
2234
801d3424
NHE		 2235static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2236{
2237 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2238 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2239}
2240
2241/*
2242 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2243 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2244 * all guests if the "nested" module option is off, and can also be disabled
2245 * for a single guest by disabling its VMX cpuid bit.
2246 */
2247static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2248{
2249 return nested && guest_cpuid_has_vmx(vcpu);
2250}
2251
b87a51ae
NHE		 2252/*
2253 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2254 * returned for the various VMX controls MSRs when nested VMX is enabled.
2255 * The same values should also be used to verify that vmcs12 control fields are
2256 * valid during nested entry from L1 to L2.
2257 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2258 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2259 * bit in the high half is on if the corresponding bit in the control field
2260 * may be on. See also vmx_control_verify().
2261 * TODO: allow these variables to be modified (downgraded) by module options
2262 * or other means.
2263 */
2264static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
3dcdf3ec 2265static u32 nested_vmx_true_procbased_ctls_low;
b87a51ae
NHE		 2266static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
2267static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
2268static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
2996fca0 2269static u32 nested_vmx_true_exit_ctls_low;
b87a51ae 2270static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
2996fca0 2271static u32 nested_vmx_true_entry_ctls_low;
c18911a2 2272static u32 nested_vmx_misc_low, nested_vmx_misc_high;
bfd0a56b 2273static u32 nested_vmx_ept_caps;
b87a51ae
NHE		 2274static __init void nested_vmx_setup_ctls_msrs(void)
2275{
2276 /*
2277 * Note that as a general rule, the high half of the MSRs (bits in
2278 * the control fields which may be 1) should be initialized by the
2279 * intersection of the underlying hardware's MSR (i.e., features which
2280 * can be supported) and the list of features we want to expose -
2281 * because they are known to be properly supported in our code.
2282 * Also, usually, the low half of the MSRs (bits which must be 1) can
2283 * be set to 0, meaning that L1 may turn off any of these bits. The
2284 * reason is that if one of these bits is necessary, it will appear
2285 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2286 * fields of vmcs01 and vmcs02, will turn these bits off - and
2287 * nested_vmx_exit_handled() will not pass related exits to L1.
2288 * These rules have exceptions below.
2289 */
2290
2291 /* pin-based controls */
eabeaacc
JK		 2292 rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2293 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high);
eabeaacc
JK		 2294 nested_vmx_pinbased_ctls_low |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2295 nested_vmx_pinbased_ctls_high &= PIN_BASED_EXT_INTR_MASK |
f4124500
JK		 2296 PIN_BASED_NMI_EXITING | PIN_BASED_VIRTUAL_NMIS;
2297 nested_vmx_pinbased_ctls_high |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
0238ea91 2298 PIN_BASED_VMX_PREEMPTION_TIMER;
b87a51ae 2299
3dbcd8da 2300 /* exit controls */
c0dfee58
ACL		 2301 rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2302 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high);
33fb20c3 2303 nested_vmx_exit_ctls_low = VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
e0ba1a6f 2304
c0dfee58 2305 nested_vmx_exit_ctls_high &=
b87a51ae 2306#ifdef CONFIG_X86_64
c0dfee58 2307 VM_EXIT_HOST_ADDR_SPACE_SIZE |
b87a51ae 2308#endif
f4124500
JK		 2309 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
2310 nested_vmx_exit_ctls_high |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2311 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
e0ba1a6f
BD		 2312 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2313
36be0b9d
PB		 2314 if (vmx_mpx_supported())
2315 nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
b87a51ae 2316
2996fca0
JK		 2317 /* We support free control of debug control saving. */
2318 nested_vmx_true_exit_ctls_low = nested_vmx_exit_ctls_low &
2319 ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2320
b87a51ae
NHE		 2321 /* entry controls */
2322 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2323 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
33fb20c3 2324 nested_vmx_entry_ctls_low = VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae 2325 nested_vmx_entry_ctls_high &=
57435349
JK		 2326#ifdef CONFIG_X86_64
2327 VM_ENTRY_IA32E_MODE |
2328#endif
2329 VM_ENTRY_LOAD_IA32_PAT;
8049d651
NHE		 2330 nested_vmx_entry_ctls_high |= (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR |
2331 VM_ENTRY_LOAD_IA32_EFER);
36be0b9d
PB		 2332 if (vmx_mpx_supported())
2333 nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
57435349 2334
2996fca0
JK		 2335 /* We support free control of debug control loading. */
2336 nested_vmx_true_entry_ctls_low = nested_vmx_entry_ctls_low &
2337 ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
2338
b87a51ae
NHE		 2339 /* cpu-based controls */
2340 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2341 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
560b7ee1 2342 nested_vmx_procbased_ctls_low = CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae 2343 nested_vmx_procbased_ctls_high &=
a294c9bb
JK		 2344 CPU_BASED_VIRTUAL_INTR_PENDING |
2345 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
b87a51ae
NHE		 2346 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2347 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2348 CPU_BASED_CR3_STORE_EXITING |
2349#ifdef CONFIG_X86_64
2350 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2351#endif
2352 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2353 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
dbcb4e79 2354 CPU_BASED_RDPMC_EXITING | CPU_BASED_RDTSC_EXITING |
d6851fbe 2355 CPU_BASED_PAUSE_EXITING |
b87a51ae
NHE		 2356 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2357 /*
2358 * We can allow some features even when not supported by the
2359 * hardware. For example, L1 can specify an MSR bitmap - and we
2360 * can use it to avoid exits to L1 - even when L0 runs L2
2361 * without MSR bitmaps.
2362 */
560b7ee1
JK		 2363 nested_vmx_procbased_ctls_high |= CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2364 CPU_BASED_USE_MSR_BITMAPS;
b87a51ae 2365
3dcdf3ec
JK		 2366 /* We support free control of CR3 access interception. */
2367 nested_vmx_true_procbased_ctls_low = nested_vmx_procbased_ctls_low &
2368 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
2369
b87a51ae
NHE		 2370 /* secondary cpu-based controls */
2371 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2372 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
2373 nested_vmx_secondary_ctls_low = 0;
2374 nested_vmx_secondary_ctls_high &=
d6851fbe 2375 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
92fbc7b1 2376 SECONDARY_EXEC_UNRESTRICTED_GUEST |
d6851fbe 2377 SECONDARY_EXEC_WBINVD_EXITING;
c18911a2 2378
afa61f75
NHE		 2379 if (enable_ept) {
2380 /* nested EPT: emulate EPT also to L1 */
2381 nested_vmx_secondary_ctls_high |= SECONDARY_EXEC_ENABLE_EPT;
ca72d970 2382 nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
d3134dbf
JK		 2383 VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT |
2384 VMX_EPT_INVEPT_BIT;
afa61f75
NHE		 2385 nested_vmx_ept_caps &= vmx_capability.ept;
2386 /*
4b855078
BD		 2387 * For nested guests, we don't do anything specific
2388 * for single context invalidation. Hence, only advertise
2389 * support for global context invalidation.
afa61f75 2390 */
4b855078 2391 nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT;
afa61f75
NHE		 2392 } else
2393 nested_vmx_ept_caps = 0;
2394
c18911a2
JK		 2395 /* miscellaneous data */
2396 rdmsr(MSR_IA32_VMX_MISC, nested_vmx_misc_low, nested_vmx_misc_high);
f4124500
JK		 2397 nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2398 nested_vmx_misc_low |= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
2399 VMX_MISC_ACTIVITY_HLT;
c18911a2 2400 nested_vmx_misc_high = 0;
b87a51ae
NHE		 2401}
2402
2403static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2404{
2405 /*
2406 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2407 */
2408 return ((control & high) | low) == control;
2409}
2410
2411static inline u64 vmx_control_msr(u32 low, u32 high)
2412{
2413 return low | ((u64)high << 32);
2414}
2415
cae50139 2416/* Returns 0 on success, non-0 otherwise. */
b87a51ae
NHE		 2417static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2418{
b87a51ae 2419 switch (msr_index) {
b87a51ae
NHE		 2420 case MSR_IA32_VMX_BASIC:
2421 /*
2422 * This MSR reports some information about VMX support. We
2423 * should return information about the VMX we emulate for the
2424 * guest, and the VMCS structure we give it - not about the
2425 * VMX support of the underlying hardware.
2426 */
3dbcd8da 2427 *pdata = VMCS12_REVISION | VMX_BASIC_TRUE_CTLS |
b87a51ae
NHE		 2428 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2429 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2430 break;
2431 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2432 case MSR_IA32_VMX_PINBASED_CTLS:
2433 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2434 nested_vmx_pinbased_ctls_high);
2435 break;
2436 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3dcdf3ec
JK		 2437 *pdata = vmx_control_msr(nested_vmx_true_procbased_ctls_low,
2438 nested_vmx_procbased_ctls_high);
2439 break;
b87a51ae
NHE		 2440 case MSR_IA32_VMX_PROCBASED_CTLS:
2441 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2442 nested_vmx_procbased_ctls_high);
2443 break;
2444 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2996fca0
JK		 2445 *pdata = vmx_control_msr(nested_vmx_true_exit_ctls_low,
2446 nested_vmx_exit_ctls_high);
2447 break;
b87a51ae
NHE		 2448 case MSR_IA32_VMX_EXIT_CTLS:
2449 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2450 nested_vmx_exit_ctls_high);
2451 break;
2452 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2996fca0
JK		 2453 *pdata = vmx_control_msr(nested_vmx_true_entry_ctls_low,
2454 nested_vmx_entry_ctls_high);
2455 break;
b87a51ae
NHE		 2456 case MSR_IA32_VMX_ENTRY_CTLS:
2457 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2458 nested_vmx_entry_ctls_high);
2459 break;
2460 case MSR_IA32_VMX_MISC:
c18911a2
JK		 2461 *pdata = vmx_control_msr(nested_vmx_misc_low,
2462 nested_vmx_misc_high);
b87a51ae
NHE		 2463 break;
2464 /*
2465 * These MSRs specify bits which the guest must keep fixed (on or off)
2466 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2467 * We picked the standard core2 setting.
2468 */
2469#define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2470#define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2471 case MSR_IA32_VMX_CR0_FIXED0:
2472 *pdata = VMXON_CR0_ALWAYSON;
2473 break;
2474 case MSR_IA32_VMX_CR0_FIXED1:
2475 *pdata = -1ULL;
2476 break;
2477 case MSR_IA32_VMX_CR4_FIXED0:
2478 *pdata = VMXON_CR4_ALWAYSON;
2479 break;
2480 case MSR_IA32_VMX_CR4_FIXED1:
2481 *pdata = -1ULL;
2482 break;
2483 case MSR_IA32_VMX_VMCS_ENUM:
5381417f 2484 *pdata = 0x2e; /* highest index: VMX_PREEMPTION_TIMER_VALUE */
b87a51ae
NHE		 2485 break;
2486 case MSR_IA32_VMX_PROCBASED_CTLS2:
2487 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2488 nested_vmx_secondary_ctls_high);
2489 break;
2490 case MSR_IA32_VMX_EPT_VPID_CAP:
afa61f75
NHE		 2491 /* Currently, no nested vpid support */
2492 *pdata = nested_vmx_ept_caps;
b87a51ae
NHE		 2493 break;
2494 default:
b87a51ae 2495 return 1;
b3897a49
NHE		 2496 }
2497
b87a51ae
NHE		 2498 return 0;
2499}
2500
6aa8b732
AK		 2501/*
2502 * Reads an msr value (of 'msr_index') into 'pdata'.
2503 * Returns 0 on success, non-0 otherwise.
2504 * Assumes vcpu_load() was already called.
2505 */
2506static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2507{
2508 u64 data;
26bb0981 2509 struct shared_msr_entry *msr;
6aa8b732
AK		 2510
2511 if (!pdata) {
2512 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2513 return -EINVAL;
2514 }
2515
2516 switch (msr_index) {
05b3e0c2 2517#ifdef CONFIG_X86_64
6aa8b732
AK		 2518 case MSR_FS_BASE:
2519 data = vmcs_readl(GUEST_FS_BASE);
2520 break;
2521 case MSR_GS_BASE:
2522 data = vmcs_readl(GUEST_GS_BASE);
2523 break;
44ea2b17
AK		 2524 case MSR_KERNEL_GS_BASE:
2525 vmx_load_host_state(to_vmx(vcpu));
2526 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2527 break;
26bb0981 2528#endif
6aa8b732 2529 case MSR_EFER:
3bab1f5d 2530 return kvm_get_msr_common(vcpu, msr_index, pdata);
af24a4e4 2531 case MSR_IA32_TSC:
6aa8b732
AK		 2532 data = guest_read_tsc();
2533 break;
2534 case MSR_IA32_SYSENTER_CS:
2535 data = vmcs_read32(GUEST_SYSENTER_CS);
2536 break;
2537 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2538 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 2539 break;
2540 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2541 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 2542 break;
0dd376e7 2543 case MSR_IA32_BNDCFGS:
93c4adc7
PB		 2544 if (!vmx_mpx_supported())
2545 return 1;
0dd376e7
LJ		 2546 data = vmcs_read64(GUEST_BNDCFGS);
2547 break;
cae50139
JK		 2548 case MSR_IA32_FEATURE_CONTROL:
2549 if (!nested_vmx_allowed(vcpu))
2550 return 1;
2551 data = to_vmx(vcpu)->nested.msr_ia32_feature_control;
2552 break;
2553 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2554 if (!nested_vmx_allowed(vcpu))
2555 return 1;
2556 return vmx_get_vmx_msr(vcpu, msr_index, pdata);
4e47c7a6
SY		 2557 case MSR_TSC_AUX:
2558 if (!to_vmx(vcpu)->rdtscp_enabled)
2559 return 1;
2560 /* Otherwise falls through */
6aa8b732 2561 default:
8b9cf98c 2562 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d
AK		 2563 if (msr) {
2564 data = msr->data;
2565 break;
6aa8b732 2566 }
3bab1f5d 2567 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 2568 }
2569
2570 *pdata = data;
2571 return 0;
2572}
2573
cae50139
JK		 2574static void vmx_leave_nested(struct kvm_vcpu *vcpu);
2575
6aa8b732
AK		 2576/*
2577 * Writes msr value into into the appropriate "register".
2578 * Returns 0 on success, non-0 otherwise.
2579 * Assumes vcpu_load() was already called.
2580 */
8fe8ab46 2581static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
6aa8b732 2582{
a2fa3e9f 2583 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 2584 struct shared_msr_entry *msr;
2cc51560 2585 int ret = 0;
8fe8ab46
WA		 2586 u32 msr_index = msr_info->index;
2587 u64 data = msr_info->data;
2cc51560 2588
6aa8b732 2589 switch (msr_index) {
3bab1f5d 2590 case MSR_EFER:
8fe8ab46 2591 ret = kvm_set_msr_common(vcpu, msr_info);
2cc51560 2592 break;
16175a79 2593#ifdef CONFIG_X86_64
6aa8b732 2594 case MSR_FS_BASE:
2fb92db1 2595 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2596 vmcs_writel(GUEST_FS_BASE, data);
2597 break;
2598 case MSR_GS_BASE:
2fb92db1 2599 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2600 vmcs_writel(GUEST_GS_BASE, data);
2601 break;
44ea2b17
AK		 2602 case MSR_KERNEL_GS_BASE:
2603 vmx_load_host_state(vmx);
2604 vmx->msr_guest_kernel_gs_base = data;
2605 break;
6aa8b732
AK		 2606#endif
2607 case MSR_IA32_SYSENTER_CS:
2608 vmcs_write32(GUEST_SYSENTER_CS, data);
2609 break;
2610 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2611 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 2612 break;
2613 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2614 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 2615 break;
0dd376e7 2616 case MSR_IA32_BNDCFGS:
93c4adc7
PB		 2617 if (!vmx_mpx_supported())
2618 return 1;
0dd376e7
LJ		 2619 vmcs_write64(GUEST_BNDCFGS, data);
2620 break;
af24a4e4 2621 case MSR_IA32_TSC:
8fe8ab46 2622 kvm_write_tsc(vcpu, msr_info);
6aa8b732 2623 break;
468d472f
SY		 2624 case MSR_IA32_CR_PAT:
2625 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2626 vmcs_write64(GUEST_IA32_PAT, data);
2627 vcpu->arch.pat = data;
2628 break;
2629 }
8fe8ab46 2630 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 2631 break;
ba904635
WA		 2632 case MSR_IA32_TSC_ADJUST:
2633 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 2634 break;
cae50139
JK		 2635 case MSR_IA32_FEATURE_CONTROL:
2636 if (!nested_vmx_allowed(vcpu) ||
2637 (to_vmx(vcpu)->nested.msr_ia32_feature_control &
2638 FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
2639 return 1;
2640 vmx->nested.msr_ia32_feature_control = data;
2641 if (msr_info->host_initiated && data == 0)
2642 vmx_leave_nested(vcpu);
2643 break;
2644 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2645 return 1; /* they are read-only */
4e47c7a6
SY		 2646 case MSR_TSC_AUX:
2647 if (!vmx->rdtscp_enabled)
2648 return 1;
2649 /* Check reserved bit, higher 32 bits should be zero */
2650 if ((data >> 32) != 0)
2651 return 1;
2652 /* Otherwise falls through */
6aa8b732 2653 default:
8b9cf98c 2654 msr = find_msr_entry(vmx, msr_index);
3bab1f5d
AK		 2655 if (msr) {
2656 msr->data = data;
2225fd56
AK		 2657 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2658 preempt_disable();
9ee73970
AK		 2659 kvm_set_shared_msr(msr->index, msr->data,
2660 msr->mask);
2225fd56
AK		 2661 preempt_enable();
2662 }
3bab1f5d 2663 break;
6aa8b732 2664 }
8fe8ab46 2665 ret = kvm_set_msr_common(vcpu, msr_info);
6aa8b732
AK		 2666 }
2667
2cc51560 2668 return ret;
6aa8b732
AK		 2669}
2670
5fdbf976 2671static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 2672{
5fdbf976
MT		 2673 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2674 switch (reg) {
2675 case VCPU_REGS_RSP:
2676 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2677 break;
2678 case VCPU_REGS_RIP:
2679 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2680 break;
6de4f3ad
AK		 2681 case VCPU_EXREG_PDPTR:
2682 if (enable_ept)
2683 ept_save_pdptrs(vcpu);
2684 break;
5fdbf976
MT		 2685 default:
2686 break;
2687 }
6aa8b732
AK		 2688}
2689
6aa8b732
AK		 2690static __init int cpu_has_kvm_support(void)
2691{
6210e37b 2692 return cpu_has_vmx();
6aa8b732
AK		 2693}
2694
2695static __init int vmx_disabled_by_bios(void)
2696{
2697 u64 msr;
2698
2699 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
cafd6659 2700 if (msr & FEATURE_CONTROL_LOCKED) {
23f3e991 2701 /* launched w/ TXT and VMX disabled */
cafd6659
SW		 2702 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2703 && tboot_enabled())
2704 return 1;
23f3e991 2705 /* launched w/o TXT and VMX only enabled w/ TXT */
cafd6659 2706 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
23f3e991 2707 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
f9335afe
SW		 2708 && !tboot_enabled()) {
2709 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
23f3e991 2710 "activate TXT before enabling KVM\n");
cafd6659 2711 return 1;
f9335afe 2712 }
23f3e991
JC		 2713 /* launched w/o TXT and VMX disabled */
2714 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2715 && !tboot_enabled())
2716 return 1;
cafd6659
SW		 2717 }
2718
2719 return 0;
6aa8b732
AK		 2720}
2721
7725b894
DX		 2722static void kvm_cpu_vmxon(u64 addr)
2723{
2724 asm volatile (ASM_VMX_VMXON_RAX
2725 : : "a"(&addr), "m"(addr)
2726 : "memory", "cc");
2727}
2728
10474ae8 2729static int hardware_enable(void *garbage)
6aa8b732
AK		 2730{
2731 int cpu = raw_smp_processor_id();
2732 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
cafd6659 2733 u64 old, test_bits;
6aa8b732 2734
10474ae8
AG		 2735 if (read_cr4() & X86_CR4_VMXE)
2736 return -EBUSY;
2737
d462b819 2738 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76
ZY		 2739
2740 /*
2741 * Now we can enable the vmclear operation in kdump
2742 * since the loaded_vmcss_on_cpu list on this cpu
2743 * has been initialized.
2744 *
2745 * Though the cpu is not in VMX operation now, there
2746 * is no problem to enable the vmclear operation
2747 * for the loaded_vmcss_on_cpu list is empty!
2748 */
2749 crash_enable_local_vmclear(cpu);
2750
6aa8b732 2751 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
cafd6659
SW		 2752
2753 test_bits = FEATURE_CONTROL_LOCKED;
2754 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2755 if (tboot_enabled())
2756 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2757
2758 if ((old & test_bits) != test_bits) {
6aa8b732 2759 /* enable and lock */
cafd6659
SW		 2760 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2761 }
66aee91a 2762 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
10474ae8 2763
4610c9cc
DX		 2764 if (vmm_exclusive) {
2765 kvm_cpu_vmxon(phys_addr);
2766 ept_sync_global();
2767 }
10474ae8 2768
357d1226 2769 native_store_gdt(&__get_cpu_var(host_gdt));
3444d7da 2770
10474ae8 2771 return 0;
6aa8b732
AK		 2772}
2773
d462b819 2774static void vmclear_local_loaded_vmcss(void)
543e4243
AK		 2775{
2776 int cpu = raw_smp_processor_id();
d462b819 2777 struct loaded_vmcs *v, *n;
543e4243 2778
d462b819
NHE		 2779 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2780 loaded_vmcss_on_cpu_link)
2781 __loaded_vmcs_clear(v);
543e4243
AK		 2782}
2783
710ff4a8
EH		 2784
2785/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2786 * tricks.
2787 */
2788static void kvm_cpu_vmxoff(void)
6aa8b732 2789{
4ecac3fd 2790 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
6aa8b732
AK		 2791}
2792
710ff4a8
EH		 2793static void hardware_disable(void *garbage)
2794{
4610c9cc 2795 if (vmm_exclusive) {
d462b819 2796 vmclear_local_loaded_vmcss();
4610c9cc
DX		 2797 kvm_cpu_vmxoff();
2798 }
7725b894 2799 write_cr4(read_cr4() & ~X86_CR4_VMXE);
710ff4a8
EH		 2800}
2801
1c3d14fe 2802static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 2803 u32 msr, u32 *result)
1c3d14fe
YS		 2804{
2805 u32 vmx_msr_low, vmx_msr_high;
2806 u32 ctl = ctl_min | ctl_opt;
2807
2808 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2809
2810 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2811 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2812
2813 /* Ensure minimum (required) set of control bits are supported. */
2814 if (ctl_min & ~ctl)
002c7f7c 2815 return -EIO;
1c3d14fe
YS		 2816
2817 *result = ctl;
2818 return 0;
2819}
2820
110312c8
AK		 2821static __init bool allow_1_setting(u32 msr, u32 ctl)
2822{
2823 u32 vmx_msr_low, vmx_msr_high;
2824
2825 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2826 return vmx_msr_high & ctl;
2827}
2828
002c7f7c 2829static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 2830{
2831 u32 vmx_msr_low, vmx_msr_high;
d56f546d 2832 u32 min, opt, min2, opt2;
1c3d14fe
YS		 2833 u32 _pin_based_exec_control = 0;
2834 u32 _cpu_based_exec_control = 0;
f78e0e2e 2835 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 2836 u32 _vmexit_control = 0;
2837 u32 _vmentry_control = 0;
2838
10166744 2839 min = CPU_BASED_HLT_EXITING |
1c3d14fe
YS		 2840#ifdef CONFIG_X86_64
2841 CPU_BASED_CR8_LOAD_EXITING |
2842 CPU_BASED_CR8_STORE_EXITING |
2843#endif
d56f546d
SY		 2844 CPU_BASED_CR3_LOAD_EXITING |
2845 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 2846 CPU_BASED_USE_IO_BITMAPS |
2847 CPU_BASED_MOV_DR_EXITING |
a7052897 2848 CPU_BASED_USE_TSC_OFFSETING |
59708670
SY		 2849 CPU_BASED_MWAIT_EXITING |
2850 CPU_BASED_MONITOR_EXITING |
fee84b07
AK		 2851 CPU_BASED_INVLPG_EXITING |
2852 CPU_BASED_RDPMC_EXITING;
443381a8 2853
f78e0e2e 2854 opt = CPU_BASED_TPR_SHADOW |
25c5f225 2855 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 2856 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 2857 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2858 &_cpu_based_exec_control) < 0)
002c7f7c 2859 return -EIO;
6e5d865c
YS		 2860#ifdef CONFIG_X86_64
2861 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2862 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2863 ~CPU_BASED_CR8_STORE_EXITING;
2864#endif
f78e0e2e 2865 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 2866 min2 = 0;
2867 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
8d14695f 2868 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2384d2b3 2869 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 2870 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 2871 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 2872 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6 2873 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
ad756a16 2874 SECONDARY_EXEC_RDTSCP |
83d4c286 2875 SECONDARY_EXEC_ENABLE_INVPCID |
c7c9c56c 2876 SECONDARY_EXEC_APIC_REGISTER_VIRT |
abc4fc58
AG		 2877 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2878 SECONDARY_EXEC_SHADOW_VMCS;
d56f546d
SY		 2879 if (adjust_vmx_controls(min2, opt2,
2880 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 2881 &_cpu_based_2nd_exec_control) < 0)
2882 return -EIO;
2883 }
2884#ifndef CONFIG_X86_64
2885 if (!(_cpu_based_2nd_exec_control &
2886 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2887 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2888#endif
83d4c286
YZ		 2889
2890 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2891 _cpu_based_2nd_exec_control &= ~(
8d14695f 2892 SECONDARY_EXEC_APIC_REGISTER_VIRT |
c7c9c56c
YZ		 2893 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2894 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
83d4c286 2895
d56f546d 2896 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 2897 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2898 enabled */
5fff7d27
GN		 2899 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2900 CPU_BASED_CR3_STORE_EXITING |
2901 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 2902 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2903 vmx_capability.ept, vmx_capability.vpid);
2904 }
1c3d14fe 2905
81908bf4 2906 min = VM_EXIT_SAVE_DEBUG_CONTROLS;
1c3d14fe
YS		 2907#ifdef CONFIG_X86_64
2908 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2909#endif
a547c6db 2910 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
da8999d3 2911 VM_EXIT_ACK_INTR_ON_EXIT | VM_EXIT_CLEAR_BNDCFGS;
1c3d14fe
YS		 2912 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2913 &_vmexit_control) < 0)
002c7f7c 2914 return -EIO;
1c3d14fe 2915
01e439be
YZ		 2916 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2917 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
2918 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2919 &_pin_based_exec_control) < 0)
2920 return -EIO;
2921
2922 if (!(_cpu_based_2nd_exec_control &
2923 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
2924 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
2925 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
2926
c845f9c6 2927 min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
da8999d3 2928 opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
1c3d14fe
YS		 2929 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2930 &_vmentry_control) < 0)
002c7f7c 2931 return -EIO;
6aa8b732 2932
c68876fd 2933 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 2934
2935 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2936 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 2937 return -EIO;
1c3d14fe
YS		 2938
2939#ifdef CONFIG_X86_64
2940 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2941 if (vmx_msr_high & (1u<<16))
002c7f7c 2942 return -EIO;
1c3d14fe
YS		 2943#endif
2944
2945 /* Require Write-Back (WB) memory type for VMCS accesses. */
2946 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 2947 return -EIO;
1c3d14fe 2948
002c7f7c
YS		 2949 vmcs_conf->size = vmx_msr_high & 0x1fff;
2950 vmcs_conf->order = get_order(vmcs_config.size);
2951 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 2952
002c7f7c
YS		 2953 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2954 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 2955 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 2956 vmcs_conf->vmexit_ctrl = _vmexit_control;
2957 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe 2958
110312c8
AK		 2959 cpu_has_load_ia32_efer =
2960 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2961 VM_ENTRY_LOAD_IA32_EFER)
2962 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2963 VM_EXIT_LOAD_IA32_EFER);
2964
8bf00a52
GN		 2965 cpu_has_load_perf_global_ctrl =
2966 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2967 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
2968 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2969 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2970
2971 /*
2972 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2973 * but due to arrata below it can't be used. Workaround is to use
2974 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2975 *
2976 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2977 *
2978 * AAK155 (model 26)
2979 * AAP115 (model 30)
2980 * AAT100 (model 37)
2981 * BC86,AAY89,BD102 (model 44)
2982 * BA97 (model 46)
2983 *
2984 */
2985 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
2986 switch (boot_cpu_data.x86_model) {
2987 case 26:
2988 case 30:
2989 case 37:
2990 case 44:
2991 case 46:
2992 cpu_has_load_perf_global_ctrl = false;
2993 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2994 "does not work properly. Using workaround\n");
2995 break;
2996 default:
2997 break;
2998 }
2999 }
3000
1c3d14fe 3001 return 0;
c68876fd 3002}
6aa8b732
AK		 3003
3004static struct vmcs *alloc_vmcs_cpu(int cpu)
3005{
3006 int node = cpu_to_node(cpu);
3007 struct page *pages;
3008 struct vmcs *vmcs;
3009
6484eb3e 3010 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 3011 if (!pages)
3012 return NULL;
3013 vmcs = page_address(pages);
1c3d14fe
YS		 3014 memset(vmcs, 0, vmcs_config.size);
3015 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 3016 return vmcs;
3017}
3018
3019static struct vmcs *alloc_vmcs(void)
3020{
d3b2c338 3021 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 3022}
3023
3024static void free_vmcs(struct vmcs *vmcs)
3025{
1c3d14fe 3026 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 3027}
3028
d462b819
NHE		 3029/*
3030 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3031 */
3032static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3033{
3034 if (!loaded_vmcs->vmcs)
3035 return;
3036 loaded_vmcs_clear(loaded_vmcs);
3037 free_vmcs(loaded_vmcs->vmcs);
3038 loaded_vmcs->vmcs = NULL;
3039}
3040
39959588 3041static void free_kvm_area(void)
6aa8b732
AK		 3042{
3043 int cpu;
3044
3230bb47 3045 for_each_possible_cpu(cpu) {
6aa8b732 3046 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 3047 per_cpu(vmxarea, cpu) = NULL;
3048 }
6aa8b732
AK		 3049}
3050
fe2b201b
BD		 3051static void init_vmcs_shadow_fields(void)
3052{
3053 int i, j;
3054
3055 /* No checks for read only fields yet */
3056
3057 for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3058 switch (shadow_read_write_fields[i]) {
3059 case GUEST_BNDCFGS:
3060 if (!vmx_mpx_supported())
3061 continue;
3062 break;
3063 default:
3064 break;
3065 }
3066
3067 if (j < i)
3068 shadow_read_write_fields[j] =
3069 shadow_read_write_fields[i];
3070 j++;
3071 }
3072 max_shadow_read_write_fields = j;
3073
3074 /* shadowed fields guest access without vmexit */
3075 for (i = 0; i < max_shadow_read_write_fields; i++) {
3076 clear_bit(shadow_read_write_fields[i],
3077 vmx_vmwrite_bitmap);
3078 clear_bit(shadow_read_write_fields[i],
3079 vmx_vmread_bitmap);
3080 }
3081 for (i = 0; i < max_shadow_read_only_fields; i++)
3082 clear_bit(shadow_read_only_fields[i],
3083 vmx_vmread_bitmap);
3084}
3085
6aa8b732
AK		 3086static __init int alloc_kvm_area(void)
3087{
3088 int cpu;
3089
3230bb47 3090 for_each_possible_cpu(cpu) {
6aa8b732
AK		 3091 struct vmcs *vmcs;
3092
3093 vmcs = alloc_vmcs_cpu(cpu);
3094 if (!vmcs) {
3095 free_kvm_area();
3096 return -ENOMEM;
3097 }
3098
3099 per_cpu(vmxarea, cpu) = vmcs;
3100 }
3101 return 0;
3102}
3103
3104static __init int hardware_setup(void)
3105{
002c7f7c
YS		 3106 if (setup_vmcs_config(&vmcs_config) < 0)
3107 return -EIO;
50a37eb4
JR		 3108
3109 if (boot_cpu_has(X86_FEATURE_NX))
3110 kvm_enable_efer_bits(EFER_NX);
3111
93ba03c2
SY		 3112 if (!cpu_has_vmx_vpid())
3113 enable_vpid = 0;
abc4fc58
AG		 3114 if (!cpu_has_vmx_shadow_vmcs())
3115 enable_shadow_vmcs = 0;
fe2b201b
BD		 3116 if (enable_shadow_vmcs)
3117 init_vmcs_shadow_fields();
93ba03c2 3118
4bc9b982
SY		 3119 if (!cpu_has_vmx_ept() ||
3120 !cpu_has_vmx_ept_4levels()) {
93ba03c2 3121 enable_ept = 0;
3a624e29 3122 enable_unrestricted_guest = 0;
83c3a331 3123 enable_ept_ad_bits = 0;
3a624e29
NK		 3124 }
3125
83c3a331
XH		 3126 if (!cpu_has_vmx_ept_ad_bits())
3127 enable_ept_ad_bits = 0;
3128
3a624e29
NK		 3129 if (!cpu_has_vmx_unrestricted_guest())
3130 enable_unrestricted_guest = 0;
93ba03c2
SY		 3131
3132 if (!cpu_has_vmx_flexpriority())
3133 flexpriority_enabled = 0;
3134
95ba8273
GN		 3135 if (!cpu_has_vmx_tpr_shadow())
3136 kvm_x86_ops->update_cr8_intercept = NULL;
3137
54dee993
MT		 3138 if (enable_ept && !cpu_has_vmx_ept_2m_page())
3139 kvm_disable_largepages();
3140
4b8d54f9
ZE		 3141 if (!cpu_has_vmx_ple())
3142 ple_gap = 0;
3143
01e439be
YZ		 3144 if (!cpu_has_vmx_apicv())
3145 enable_apicv = 0;
c7c9c56c 3146
01e439be 3147 if (enable_apicv)
c7c9c56c 3148 kvm_x86_ops->update_cr8_intercept = NULL;
a20ed54d 3149 else {
c7c9c56c 3150 kvm_x86_ops->hwapic_irr_update = NULL;
a20ed54d
YZ		 3151 kvm_x86_ops->deliver_posted_interrupt = NULL;
3152 kvm_x86_ops->sync_pir_to_irr = vmx_sync_pir_to_irr_dummy;
3153 }
83d4c286 3154
b87a51ae
NHE		 3155 if (nested)
3156 nested_vmx_setup_ctls_msrs();
3157
6aa8b732
AK		 3158 return alloc_kvm_area();
3159}
3160
3161static __exit void hardware_unsetup(void)
3162{
3163 free_kvm_area();
3164}
3165
14168786
GN		 3166static bool emulation_required(struct kvm_vcpu *vcpu)
3167{
3168 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3169}
3170
91b0aa2c 3171static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
d99e4152 3172 struct kvm_segment *save)
6aa8b732 3173{
d99e4152
GN		 3174 if (!emulate_invalid_guest_state) {
3175 /*
3176 * CS and SS RPL should be equal during guest entry according
3177 * to VMX spec, but in reality it is not always so. Since vcpu
3178 * is in the middle of the transition from real mode to
3179 * protected mode it is safe to assume that RPL 0 is a good
3180 * default value.
3181 */
3182 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3183 save->selector &= ~SELECTOR_RPL_MASK;
3184 save->dpl = save->selector & SELECTOR_RPL_MASK;
3185 save->s = 1;
6aa8b732 3186 }
d99e4152 3187 vmx_set_segment(vcpu, save, seg);
6aa8b732
AK		 3188}
3189
3190static void enter_pmode(struct kvm_vcpu *vcpu)
3191{
3192 unsigned long flags;
a89a8fb9 3193 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3194
d99e4152
GN		 3195 /*
3196 * Update real mode segment cache. It may be not up-to-date if sement
3197 * register was written while vcpu was in a guest mode.
3198 */
3199 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3200 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3201 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3202 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3203 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3204 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3205
7ffd92c5 3206 vmx->rmode.vm86_active = 0;
6aa8b732 3207
2fb92db1
AK		 3208 vmx_segment_cache_clear(vmx);
3209
f5f7b2fe 3210 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
6aa8b732
AK		 3211
3212 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 3213 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3214 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK		 3215 vmcs_writel(GUEST_RFLAGS, flags);
3216
66aee91a
RR		 3217 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3218 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 3219
3220 update_exception_bitmap(vcpu);
3221
91b0aa2c
GN		 3222 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3223 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3224 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3225 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3226 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3227 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
6aa8b732
AK		 3228}
3229
f5f7b2fe 3230static void fix_rmode_seg(int seg, struct kvm_segment *save)
6aa8b732 3231{
772e0318 3232 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
d99e4152
GN		 3233 struct kvm_segment var = *save;
3234
3235 var.dpl = 0x3;
3236 if (seg == VCPU_SREG_CS)
3237 var.type = 0x3;
3238
3239 if (!emulate_invalid_guest_state) {
3240 var.selector = var.base >> 4;
3241 var.base = var.base & 0xffff0;
3242 var.limit = 0xffff;
3243 var.g = 0;
3244 var.db = 0;
3245 var.present = 1;
3246 var.s = 1;
3247 var.l = 0;
3248 var.unusable = 0;
3249 var.type = 0x3;
3250 var.avl = 0;
3251 if (save->base & 0xf)
3252 printk_once(KERN_WARNING "kvm: segment base is not "
3253 "paragraph aligned when entering "
3254 "protected mode (seg=%d)", seg);
3255 }
6aa8b732 3256
d99e4152
GN		 3257 vmcs_write16(sf->selector, var.selector);
3258 vmcs_write32(sf->base, var.base);
3259 vmcs_write32(sf->limit, var.limit);
3260 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
6aa8b732
AK		 3261}
3262
3263static void enter_rmode(struct kvm_vcpu *vcpu)
3264{
3265 unsigned long flags;
a89a8fb9 3266 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3267
f5f7b2fe
AK		 3268 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3269 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3270 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3271 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3272 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
c6ad1153
GN		 3273 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3274 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
f5f7b2fe 3275
7ffd92c5 3276 vmx->rmode.vm86_active = 1;
6aa8b732 3277
776e58ea
GN		 3278 /*
3279 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
4918c6ca 3280 * vcpu. Warn the user that an update is overdue.
776e58ea 3281 */
4918c6ca 3282 if (!vcpu->kvm->arch.tss_addr)
776e58ea
GN		 3283 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3284 "called before entering vcpu\n");
776e58ea 3285
2fb92db1
AK		 3286 vmx_segment_cache_clear(vmx);
3287
4918c6ca 3288 vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
6aa8b732 3289 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
6aa8b732
AK		 3290 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3291
3292 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 3293 vmx->rmode.save_rflags = flags;
6aa8b732 3294
053de044 3295 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 3296
3297 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 3298 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 3299 update_exception_bitmap(vcpu);
3300
d99e4152
GN		 3301 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3302 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3303 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3304 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3305 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3306 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
b246dd5d 3307
8668a3c4 3308 kvm_mmu_reset_context(vcpu);
6aa8b732
AK		 3309}
3310
401d10de
AS		 3311static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3312{
3313 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 3314 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3315
3316 if (!msr)
3317 return;
401d10de 3318
44ea2b17
AK		 3319 /*
3320 * Force kernel_gs_base reloading before EFER changes, as control
3321 * of this msr depends on is_long_mode().
3322 */
3323 vmx_load_host_state(to_vmx(vcpu));
f6801dff 3324 vcpu->arch.efer = efer;
401d10de 3325 if (efer & EFER_LMA) {
2961e876 3326 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
401d10de
AS		 3327 msr->data = efer;
3328 } else {
2961e876 3329 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
401d10de
AS		 3330
3331 msr->data = efer & ~EFER_LME;
3332 }
3333 setup_msrs(vmx);
3334}
3335
05b3e0c2 3336#ifdef CONFIG_X86_64
6aa8b732
AK		 3337
3338static void enter_lmode(struct kvm_vcpu *vcpu)
3339{
3340 u32 guest_tr_ar;
3341
2fb92db1
AK		 3342 vmx_segment_cache_clear(to_vmx(vcpu));
3343
6aa8b732
AK		 3344 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3345 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
bd80158a
JK		 3346 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3347 __func__);
6aa8b732
AK		 3348 vmcs_write32(GUEST_TR_AR_BYTES,
3349 (guest_tr_ar & ~AR_TYPE_MASK)
3350 | AR_TYPE_BUSY_64_TSS);
3351 }
da38f438 3352 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
6aa8b732
AK		 3353}
3354
3355static void exit_lmode(struct kvm_vcpu *vcpu)
3356{
2961e876 3357 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
da38f438 3358 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
6aa8b732
AK		 3359}
3360
3361#endif
3362
2384d2b3
SY		 3363static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3364{
b9d762fa 3365 vpid_sync_context(to_vmx(vcpu));
dd180b3e
XG		 3366 if (enable_ept) {
3367 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3368 return;
4e1096d2 3369 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
dd180b3e 3370 }
2384d2b3
SY		 3371}
3372
e8467fda
AK		 3373static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3374{
3375 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3376
3377 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3378 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3379}
3380
aff48baa
AK		 3381static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3382{
3383 if (enable_ept && is_paging(vcpu))
3384 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3385 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3386}
3387
25c4c276 3388static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 3389{
fc78f519
AK		 3390 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3391
3392 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3393 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 3394}
3395
1439442c
SY		 3396static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3397{
d0d538b9
GN		 3398 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3399
6de4f3ad
AK		 3400 if (!test_bit(VCPU_EXREG_PDPTR,
3401 (unsigned long *)&vcpu->arch.regs_dirty))
3402 return;
3403
1439442c 3404 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
d0d538b9
GN		 3405 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
3406 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
3407 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
3408 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
1439442c
SY		 3409 }
3410}
3411
8f5d549f
AK		 3412static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3413{
d0d538b9
GN		 3414 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3415
8f5d549f 3416 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
d0d538b9
GN		 3417 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3418 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3419 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3420 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
8f5d549f 3421 }
6de4f3ad
AK		 3422
3423 __set_bit(VCPU_EXREG_PDPTR,
3424 (unsigned long *)&vcpu->arch.regs_avail);
3425 __set_bit(VCPU_EXREG_PDPTR,
3426 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 3427}
3428
5e1746d6 3429static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1439442c
SY		 3430
3431static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3432 unsigned long cr0,
3433 struct kvm_vcpu *vcpu)
3434{
5233dd51
MT		 3435 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3436 vmx_decache_cr3(vcpu);
1439442c
SY		 3437 if (!(cr0 & X86_CR0_PG)) {
3438 /* From paging/starting to nonpaging */
3439 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3440 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 3441 (CPU_BASED_CR3_LOAD_EXITING |
3442 CPU_BASED_CR3_STORE_EXITING));
3443 vcpu->arch.cr0 = cr0;
fc78f519 3444 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 3445 } else if (!is_paging(vcpu)) {
3446 /* From nonpaging to paging */
3447 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3448 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 3449 ~(CPU_BASED_CR3_LOAD_EXITING |
3450 CPU_BASED_CR3_STORE_EXITING));
3451 vcpu->arch.cr0 = cr0;
fc78f519 3452 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 3453 }
95eb84a7
SY		 3454
3455 if (!(cr0 & X86_CR0_WP))
3456 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 3457}
3458
6aa8b732
AK		 3459static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3460{
7ffd92c5 3461 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 3462 unsigned long hw_cr0;
3463
5037878e 3464 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3a624e29 3465 if (enable_unrestricted_guest)
5037878e 3466 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
218e763f 3467 else {
5037878e 3468 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
1439442c 3469
218e763f
GN		 3470 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3471 enter_pmode(vcpu);
6aa8b732 3472
218e763f
GN		 3473 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3474 enter_rmode(vcpu);
3475 }
6aa8b732 3476
05b3e0c2 3477#ifdef CONFIG_X86_64
f6801dff 3478 if (vcpu->arch.efer & EFER_LME) {
707d92fa 3479 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 3480 enter_lmode(vcpu);
707d92fa 3481 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 3482 exit_lmode(vcpu);
3483 }
3484#endif
3485
089d034e 3486 if (enable_ept)
1439442c
SY		 3487 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3488
02daab21 3489 if (!vcpu->fpu_active)
81231c69 3490 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
02daab21 3491
6aa8b732 3492 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 3493 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 3494 vcpu->arch.cr0 = cr0;
14168786
GN		 3495
3496 /* depends on vcpu->arch.cr0 to be set to a new value */
3497 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 3498}
3499
1439442c
SY		 3500static u64 construct_eptp(unsigned long root_hpa)
3501{
3502 u64 eptp;
3503
3504 /* TODO write the value reading from MSR */
3505 eptp = VMX_EPT_DEFAULT_MT |
3506 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
b38f9934
XH		 3507 if (enable_ept_ad_bits)
3508 eptp |= VMX_EPT_AD_ENABLE_BIT;
1439442c
SY		 3509 eptp |= (root_hpa & PAGE_MASK);
3510
3511 return eptp;
3512}
3513
6aa8b732
AK		 3514static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3515{
1439442c
SY		 3516 unsigned long guest_cr3;
3517 u64 eptp;
3518
3519 guest_cr3 = cr3;
089d034e 3520 if (enable_ept) {
1439442c
SY		 3521 eptp = construct_eptp(cr3);
3522 vmcs_write64(EPT_POINTER, eptp);
59ab5a8f
JK		 3523 if (is_paging(vcpu) || is_guest_mode(vcpu))
3524 guest_cr3 = kvm_read_cr3(vcpu);
3525 else
3526 guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 3527 ept_load_pdptrs(vcpu);
1439442c
SY		 3528 }
3529
2384d2b3 3530 vmx_flush_tlb(vcpu);
1439442c 3531 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK		 3532}
3533
5e1746d6 3534static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
6aa8b732 3535{
7ffd92c5 3536 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1439442c
SY		 3537 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3538
5e1746d6
NHE		 3539 if (cr4 & X86_CR4_VMXE) {
3540 /*
3541 * To use VMXON (and later other VMX instructions), a guest
3542 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3543 * So basically the check on whether to allow nested VMX
3544 * is here.
3545 */
3546 if (!nested_vmx_allowed(vcpu))
3547 return 1;
1a0d74e6
JK		 3548 }
3549 if (to_vmx(vcpu)->nested.vmxon &&
3550 ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
5e1746d6
NHE		 3551 return 1;
3552
ad312c7c 3553 vcpu->arch.cr4 = cr4;
bc23008b
AK		 3554 if (enable_ept) {
3555 if (!is_paging(vcpu)) {
3556 hw_cr4 &= ~X86_CR4_PAE;
3557 hw_cr4 |= X86_CR4_PSE;
c08800a5 3558 /*
e1e746b3
FW		 3559 * SMEP/SMAP is disabled if CPU is in non-paging mode
3560 * in hardware. However KVM always uses paging mode to
c08800a5 3561 * emulate guest non-paging mode with TDP.
e1e746b3
FW		 3562 * To emulate this behavior, SMEP/SMAP needs to be
3563 * manually disabled when guest switches to non-paging
3564 * mode.
c08800a5 3565 */
e1e746b3 3566 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP);
bc23008b
AK		 3567 } else if (!(cr4 & X86_CR4_PAE)) {
3568 hw_cr4 &= ~X86_CR4_PAE;
3569 }
3570 }
1439442c
SY		 3571
3572 vmcs_writel(CR4_READ_SHADOW, cr4);
3573 vmcs_writel(GUEST_CR4, hw_cr4);
5e1746d6 3574 return 0;
6aa8b732
AK		 3575}
3576
6aa8b732
AK		 3577static void vmx_get_segment(struct kvm_vcpu *vcpu,
3578 struct kvm_segment *var, int seg)
3579{
a9179499 3580 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732
AK		 3581 u32 ar;
3582
c6ad1153 3583 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
f5f7b2fe 3584 *var = vmx->rmode.segs[seg];
a9179499 3585 if (seg == VCPU_SREG_TR
2fb92db1 3586 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
f5f7b2fe 3587 return;
1390a28b
AK		 3588 var->base = vmx_read_guest_seg_base(vmx, seg);
3589 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3590 return;
a9179499 3591 }
2fb92db1
AK		 3592 var->base = vmx_read_guest_seg_base(vmx, seg);
3593 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3594 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3595 ar = vmx_read_guest_seg_ar(vmx, seg);
03617c18 3596 var->unusable = (ar >> 16) & 1;
6aa8b732
AK		 3597 var->type = ar & 15;
3598 var->s = (ar >> 4) & 1;
3599 var->dpl = (ar >> 5) & 3;
03617c18
GN		 3600 /*
3601 * Some userspaces do not preserve unusable property. Since usable
3602 * segment has to be present according to VMX spec we can use present
3603 * property to amend userspace bug by making unusable segment always
3604 * nonpresent. vmx_segment_access_rights() already marks nonpresent
3605 * segment as unusable.
3606 */
3607 var->present = !var->unusable;
6aa8b732
AK		 3608 var->avl = (ar >> 12) & 1;
3609 var->l = (ar >> 13) & 1;
3610 var->db = (ar >> 14) & 1;
3611 var->g = (ar >> 15) & 1;
6aa8b732
AK		 3612}
3613
a9179499
AK		 3614static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3615{
a9179499
AK		 3616 struct kvm_segment s;
3617
3618 if (to_vmx(vcpu)->rmode.vm86_active) {
3619 vmx_get_segment(vcpu, &s, seg);
3620 return s.base;
3621 }
2fb92db1 3622 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
a9179499
AK		 3623}
3624
b09408d0 3625static int vmx_get_cpl(struct kvm_vcpu *vcpu)
2e4d2653 3626{
b09408d0
MT		 3627 struct vcpu_vmx *vmx = to_vmx(vcpu);
3628
ae9fedc7 3629 if (unlikely(vmx->rmode.vm86_active))
2e4d2653 3630 return 0;
ae9fedc7
PB		 3631 else {
3632 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
3633 return AR_DPL(ar);
69c73028 3634 }
69c73028
AK		 3635}
3636
653e3108 3637static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 3638{
6aa8b732
AK		 3639 u32 ar;
3640
f0495f9b 3641 if (var->unusable || !var->present)
6aa8b732
AK		 3642 ar = 1 << 16;
3643 else {
3644 ar = var->type & 15;
3645 ar |= (var->s & 1) << 4;
3646 ar |= (var->dpl & 3) << 5;
3647 ar |= (var->present & 1) << 7;
3648 ar |= (var->avl & 1) << 12;
3649 ar |= (var->l & 1) << 13;
3650 ar |= (var->db & 1) << 14;
3651 ar |= (var->g & 1) << 15;
3652 }
653e3108
AK		 3653
3654 return ar;
3655}
3656
3657static void vmx_set_segment(struct kvm_vcpu *vcpu,
3658 struct kvm_segment *var, int seg)
3659{
7ffd92c5 3660 struct vcpu_vmx *vmx = to_vmx(vcpu);
772e0318 3661 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
653e3108 3662
2fb92db1
AK		 3663 vmx_segment_cache_clear(vmx);
3664
1ecd50a9
GN		 3665 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3666 vmx->rmode.segs[seg] = *var;
3667 if (seg == VCPU_SREG_TR)
3668 vmcs_write16(sf->selector, var->selector);
3669 else if (var->s)
3670 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
d99e4152 3671 goto out;
653e3108 3672 }
1ecd50a9 3673
653e3108
AK		 3674 vmcs_writel(sf->base, var->base);
3675 vmcs_write32(sf->limit, var->limit);
3676 vmcs_write16(sf->selector, var->selector);
3a624e29
NK		 3677
3678 /*
3679 * Fix the "Accessed" bit in AR field of segment registers for older
3680 * qemu binaries.
3681 * IA32 arch specifies that at the time of processor reset the
3682 * "Accessed" bit in the AR field of segment registers is 1. And qemu
0fa06071 3683 * is setting it to 0 in the userland code. This causes invalid guest
3a624e29
NK		 3684 * state vmexit when "unrestricted guest" mode is turned on.
3685 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3686 * tree. Newer qemu binaries with that qemu fix would not need this
3687 * kvm hack.
3688 */
3689 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
f924d66d 3690 var->type |= 0x1; /* Accessed */
3a624e29 3691
f924d66d 3692 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
d99e4152
GN		 3693
3694out:
98eb2f8b 3695 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 3696}
3697
6aa8b732
AK		 3698static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3699{
2fb92db1 3700 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
6aa8b732
AK		 3701
3702 *db = (ar >> 14) & 1;
3703 *l = (ar >> 13) & 1;
3704}
3705
89a27f4d 3706static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3707{
89a27f4d
GN		 3708 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3709 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK		 3710}
3711
89a27f4d 3712static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3713{
89a27f4d
GN		 3714 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3715 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK		 3716}
3717
89a27f4d 3718static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3719{
89a27f4d
GN		 3720 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3721 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK		 3722}
3723
89a27f4d 3724static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3725{
89a27f4d
GN		 3726 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3727 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK		 3728}
3729
648dfaa7
MG		 3730static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3731{
3732 struct kvm_segment var;
3733 u32 ar;
3734
3735 vmx_get_segment(vcpu, &var, seg);
07f42f5f 3736 var.dpl = 0x3;
0647f4aa
GN		 3737 if (seg == VCPU_SREG_CS)
3738 var.type = 0x3;
648dfaa7
MG		 3739 ar = vmx_segment_access_rights(&var);
3740
3741 if (var.base != (var.selector << 4))
3742 return false;
89efbed0 3743 if (var.limit != 0xffff)
648dfaa7 3744 return false;
07f42f5f 3745 if (ar != 0xf3)
648dfaa7
MG		 3746 return false;
3747
3748 return true;
3749}
3750
3751static bool code_segment_valid(struct kvm_vcpu *vcpu)
3752{
3753 struct kvm_segment cs;
3754 unsigned int cs_rpl;
3755
3756 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3757 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3758
1872a3f4
AK		 3759 if (cs.unusable)
3760 return false;
648dfaa7
MG		 3761 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3762 return false;
3763 if (!cs.s)
3764 return false;
1872a3f4 3765 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 3766 if (cs.dpl > cs_rpl)
3767 return false;
1872a3f4 3768 } else {
648dfaa7
MG		 3769 if (cs.dpl != cs_rpl)
3770 return false;
3771 }
3772 if (!cs.present)
3773 return false;
3774
3775 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3776 return true;
3777}
3778
3779static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3780{
3781 struct kvm_segment ss;
3782 unsigned int ss_rpl;
3783
3784 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3785 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3786
1872a3f4
AK		 3787 if (ss.unusable)
3788 return true;
3789 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 3790 return false;
3791 if (!ss.s)
3792 return false;
3793 if (ss.dpl != ss_rpl) /* DPL != RPL */
3794 return false;
3795 if (!ss.present)
3796 return false;
3797
3798 return true;
3799}
3800
3801static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3802{
3803 struct kvm_segment var;
3804 unsigned int rpl;
3805
3806 vmx_get_segment(vcpu, &var, seg);
3807 rpl = var.selector & SELECTOR_RPL_MASK;
3808
1872a3f4
AK		 3809 if (var.unusable)
3810 return true;
648dfaa7
MG		 3811 if (!var.s)
3812 return false;
3813 if (!var.present)
3814 return false;
3815 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3816 if (var.dpl < rpl) /* DPL < RPL */
3817 return false;
3818 }
3819
3820 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3821 * rights flags
3822 */
3823 return true;
3824}
3825
3826static bool tr_valid(struct kvm_vcpu *vcpu)
3827{
3828 struct kvm_segment tr;
3829
3830 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3831
1872a3f4
AK		 3832 if (tr.unusable)
3833 return false;
648dfaa7
MG		 3834 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3835 return false;
1872a3f4 3836 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 3837 return false;
3838 if (!tr.present)
3839 return false;
3840
3841 return true;
3842}
3843
3844static bool ldtr_valid(struct kvm_vcpu *vcpu)
3845{
3846 struct kvm_segment ldtr;
3847
3848 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3849
1872a3f4
AK		 3850 if (ldtr.unusable)
3851 return true;
648dfaa7
MG		 3852 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3853 return false;
3854 if (ldtr.type != 2)
3855 return false;
3856 if (!ldtr.present)
3857 return false;
3858
3859 return true;
3860}
3861
3862static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3863{
3864 struct kvm_segment cs, ss;
3865
3866 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3867 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3868
3869 return ((cs.selector & SELECTOR_RPL_MASK) ==
3870 (ss.selector & SELECTOR_RPL_MASK));
3871}
3872
3873/*
3874 * Check if guest state is valid. Returns true if valid, false if
3875 * not.
3876 * We assume that registers are always usable
3877 */
3878static bool guest_state_valid(struct kvm_vcpu *vcpu)
3879{
c5e97c80
GN		 3880 if (enable_unrestricted_guest)
3881 return true;
3882
648dfaa7 3883 /* real mode guest state checks */
f13882d8 3884 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
648dfaa7
MG		 3885 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3886 return false;
3887 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3888 return false;
3889 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3890 return false;
3891 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3892 return false;
3893 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3894 return false;
3895 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3896 return false;
3897 } else {
3898 /* protected mode guest state checks */
3899 if (!cs_ss_rpl_check(vcpu))
3900 return false;
3901 if (!code_segment_valid(vcpu))
3902 return false;
3903 if (!stack_segment_valid(vcpu))
3904 return false;
3905 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3906 return false;
3907 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3908 return false;
3909 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3910 return false;
3911 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3912 return false;
3913 if (!tr_valid(vcpu))
3914 return false;
3915 if (!ldtr_valid(vcpu))
3916 return false;
3917 }
3918 /* TODO:
3919 * - Add checks on RIP
3920 * - Add checks on RFLAGS
3921 */
3922
3923 return true;
3924}
3925
d77c26fc 3926static int init_rmode_tss(struct kvm *kvm)
6aa8b732 3927{
40dcaa9f 3928 gfn_t fn;
195aefde 3929 u16 data = 0;
40dcaa9f 3930 int r, idx, ret = 0;
6aa8b732 3931
40dcaa9f 3932 idx = srcu_read_lock(&kvm->srcu);
4918c6ca 3933 fn = kvm->arch.tss_addr >> PAGE_SHIFT;
195aefde
IE		 3934 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3935 if (r < 0)
10589a46 3936 goto out;
195aefde 3937 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 3938 r = kvm_write_guest_page(kvm, fn++, &data,
3939 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 3940 if (r < 0)
10589a46 3941 goto out;
195aefde
IE		 3942 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3943 if (r < 0)
10589a46 3944 goto out;
195aefde
IE		 3945 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3946 if (r < 0)
10589a46 3947 goto out;
195aefde 3948 data = ~0;
10589a46
MT		 3949 r = kvm_write_guest_page(kvm, fn, &data,
3950 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3951 sizeof(u8));
195aefde 3952 if (r < 0)
10589a46
MT		 3953 goto out;
3954
3955 ret = 1;
3956out:
40dcaa9f 3957 srcu_read_unlock(&kvm->srcu, idx);
10589a46 3958 return ret;
6aa8b732
AK		 3959}
3960
b7ebfb05
SY		 3961static int init_rmode_identity_map(struct kvm *kvm)
3962{
40dcaa9f 3963 int i, idx, r, ret;
b7ebfb05
SY		 3964 pfn_t identity_map_pfn;
3965 u32 tmp;
3966
089d034e 3967 if (!enable_ept)
b7ebfb05
SY		 3968 return 1;
3969 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3970 printk(KERN_ERR "EPT: identity-mapping pagetable "
3971 "haven't been allocated!\n");
3972 return 0;
3973 }
3974 if (likely(kvm->arch.ept_identity_pagetable_done))
3975 return 1;
3976 ret = 0;
b927a3ce 3977 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
40dcaa9f 3978 idx = srcu_read_lock(&kvm->srcu);
b7ebfb05
SY		 3979 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3980 if (r < 0)
3981 goto out;
3982 /* Set up identity-mapping pagetable for EPT in real mode */
3983 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3984 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3985 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3986 r = kvm_write_guest_page(kvm, identity_map_pfn,
3987 &tmp, i * sizeof(tmp), sizeof(tmp));
3988 if (r < 0)
3989 goto out;
3990 }
3991 kvm->arch.ept_identity_pagetable_done = true;
3992 ret = 1;
3993out:
40dcaa9f 3994 srcu_read_unlock(&kvm->srcu, idx);
b7ebfb05
SY		 3995 return ret;
3996}
3997
6aa8b732
AK		 3998static void seg_setup(int seg)
3999{
772e0318 4000 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 4001 unsigned int ar;
6aa8b732
AK		 4002
4003 vmcs_write16(sf->selector, 0);
4004 vmcs_writel(sf->base, 0);
4005 vmcs_write32(sf->limit, 0xffff);
d54d07b2
GN		 4006 ar = 0x93;
4007 if (seg == VCPU_SREG_CS)
4008 ar |= 0x08; /* code segment */
3a624e29
NK		 4009
4010 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 4011}
4012
f78e0e2e
SY		 4013static int alloc_apic_access_page(struct kvm *kvm)
4014{
4484141a 4015 struct page *page;
f78e0e2e
SY		 4016 struct kvm_userspace_memory_region kvm_userspace_mem;
4017 int r = 0;
4018
79fac95e 4019 mutex_lock(&kvm->slots_lock);
bfc6d222 4020 if (kvm->arch.apic_access_page)
f78e0e2e
SY		 4021 goto out;
4022 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
4023 kvm_userspace_mem.flags = 0;
4024 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
4025 kvm_userspace_mem.memory_size = PAGE_SIZE;
47ae31e2 4026 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
f78e0e2e
SY		 4027 if (r)
4028 goto out;
72dc67a6 4029
4484141a
XG		 4030 page = gfn_to_page(kvm, 0xfee00);
4031 if (is_error_page(page)) {
4032 r = -EFAULT;
4033 goto out;
4034 }
4035
4036 kvm->arch.apic_access_page = page;
f78e0e2e 4037out:
79fac95e 4038 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY		 4039 return r;
4040}
4041
b7ebfb05
SY		 4042static int alloc_identity_pagetable(struct kvm *kvm)
4043{
4484141a 4044 struct page *page;
b7ebfb05
SY		 4045 struct kvm_userspace_memory_region kvm_userspace_mem;
4046 int r = 0;
4047
79fac95e 4048 mutex_lock(&kvm->slots_lock);
b7ebfb05
SY		 4049 if (kvm->arch.ept_identity_pagetable)
4050 goto out;
4051 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
4052 kvm_userspace_mem.flags = 0;
b927a3ce
SY		 4053 kvm_userspace_mem.guest_phys_addr =
4054 kvm->arch.ept_identity_map_addr;
b7ebfb05 4055 kvm_userspace_mem.memory_size = PAGE_SIZE;
47ae31e2 4056 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
b7ebfb05
SY		 4057 if (r)
4058 goto out;
4059
4484141a
XG		 4060 page = gfn_to_page(kvm, kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
4061 if (is_error_page(page)) {
4062 r = -EFAULT;
4063 goto out;
4064 }
4065
4066 kvm->arch.ept_identity_pagetable = page;
b7ebfb05 4067out:
79fac95e 4068 mutex_unlock(&kvm->slots_lock);
b7ebfb05
SY		 4069 return r;
4070}
4071
2384d2b3
SY		 4072static void allocate_vpid(struct vcpu_vmx *vmx)
4073{
4074 int vpid;
4075
4076 vmx->vpid = 0;
919818ab 4077 if (!enable_vpid)
2384d2b3
SY		 4078 return;
4079 spin_lock(&vmx_vpid_lock);
4080 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4081 if (vpid < VMX_NR_VPIDS) {
4082 vmx->vpid = vpid;
4083 __set_bit(vpid, vmx_vpid_bitmap);
4084 }
4085 spin_unlock(&vmx_vpid_lock);
4086}
4087
cdbecfc3
LJ		 4088static void free_vpid(struct vcpu_vmx *vmx)
4089{
4090 if (!enable_vpid)
4091 return;
4092 spin_lock(&vmx_vpid_lock);
4093 if (vmx->vpid != 0)
4094 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
4095 spin_unlock(&vmx_vpid_lock);
4096}
4097
8d14695f
YZ		 4098#define MSR_TYPE_R 1
4099#define MSR_TYPE_W 2
4100static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4101 u32 msr, int type)
25c5f225 4102{
3e7c73e9 4103 int f = sizeof(unsigned long);
25c5f225
SY		 4104
4105 if (!cpu_has_vmx_msr_bitmap())
4106 return;
4107
4108 /*
4109 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4110 * have the write-low and read-high bitmap offsets the wrong way round.
4111 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4112 */
25c5f225 4113 if (msr <= 0x1fff) {
8d14695f
YZ		 4114 if (type & MSR_TYPE_R)
4115 /* read-low */
4116 __clear_bit(msr, msr_bitmap + 0x000 / f);
4117
4118 if (type & MSR_TYPE_W)
4119 /* write-low */
4120 __clear_bit(msr, msr_bitmap + 0x800 / f);
4121
25c5f225
SY		 4122 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4123 msr &= 0x1fff;
8d14695f
YZ		 4124 if (type & MSR_TYPE_R)
4125 /* read-high */
4126 __clear_bit(msr, msr_bitmap + 0x400 / f);
4127
4128 if (type & MSR_TYPE_W)
4129 /* write-high */
4130 __clear_bit(msr, msr_bitmap + 0xc00 / f);
4131
4132 }
4133}
4134
4135static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
4136 u32 msr, int type)
4137{
4138 int f = sizeof(unsigned long);
4139
4140 if (!cpu_has_vmx_msr_bitmap())
4141 return;
4142
4143 /*
4144 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4145 * have the write-low and read-high bitmap offsets the wrong way round.
4146 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4147 */
4148 if (msr <= 0x1fff) {
4149 if (type & MSR_TYPE_R)
4150 /* read-low */
4151 __set_bit(msr, msr_bitmap + 0x000 / f);
4152
4153 if (type & MSR_TYPE_W)
4154 /* write-low */
4155 __set_bit(msr, msr_bitmap + 0x800 / f);
4156
4157 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4158 msr &= 0x1fff;
4159 if (type & MSR_TYPE_R)
4160 /* read-high */
4161 __set_bit(msr, msr_bitmap + 0x400 / f);
4162
4163 if (type & MSR_TYPE_W)
4164 /* write-high */
4165 __set_bit(msr, msr_bitmap + 0xc00 / f);
4166
25c5f225 4167 }
25c5f225
SY		 4168}
4169
5897297b
AK		 4170static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4171{
4172 if (!longmode_only)
8d14695f
YZ		 4173 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4174 msr, MSR_TYPE_R | MSR_TYPE_W);
4175 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4176 msr, MSR_TYPE_R | MSR_TYPE_W);
4177}
4178
4179static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
4180{
4181 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4182 msr, MSR_TYPE_R);
4183 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4184 msr, MSR_TYPE_R);
4185}
4186
4187static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4188{
4189 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4190 msr, MSR_TYPE_R);
4191 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4192 msr, MSR_TYPE_R);
4193}
4194
4195static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4196{
4197 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4198 msr, MSR_TYPE_W);
4199 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4200 msr, MSR_TYPE_W);
5897297b
AK		 4201}
4202
01e439be
YZ		 4203static int vmx_vm_has_apicv(struct kvm *kvm)
4204{
4205 return enable_apicv && irqchip_in_kernel(kvm);
4206}
4207
a20ed54d
YZ		 4208/*
4209 * Send interrupt to vcpu via posted interrupt way.
4210 * 1. If target vcpu is running(non-root mode), send posted interrupt
4211 * notification to vcpu and hardware will sync PIR to vIRR atomically.
4212 * 2. If target vcpu isn't running(root mode), kick it to pick up the
4213 * interrupt from PIR in next vmentry.
4214 */
4215static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4216{
4217 struct vcpu_vmx *vmx = to_vmx(vcpu);
4218 int r;
4219
4220 if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4221 return;
4222
4223 r = pi_test_and_set_on(&vmx->pi_desc);
4224 kvm_make_request(KVM_REQ_EVENT, vcpu);
6ffbbbba 4225#ifdef CONFIG_SMP
a20ed54d
YZ		 4226 if (!r && (vcpu->mode == IN_GUEST_MODE))
4227 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4228 POSTED_INTR_VECTOR);
4229 else
6ffbbbba 4230#endif
a20ed54d
YZ		 4231 kvm_vcpu_kick(vcpu);
4232}
4233
4234static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4235{
4236 struct vcpu_vmx *vmx = to_vmx(vcpu);
4237
4238 if (!pi_test_and_clear_on(&vmx->pi_desc))
4239 return;
4240
4241 kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4242}
4243
4244static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu)
4245{
4246 return;
4247}
4248
a3a8ff8e
NHE		 4249/*
4250 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4251 * will not change in the lifetime of the guest.
4252 * Note that host-state that does change is set elsewhere. E.g., host-state
4253 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4254 */
a547c6db 4255static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
a3a8ff8e
NHE		 4256{
4257 u32 low32, high32;
4258 unsigned long tmpl;
4259 struct desc_ptr dt;
4260
b1a74bf8 4261 vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS); /* 22.2.3 */
a3a8ff8e
NHE		 4262 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
4263 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
4264
4265 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
b2da15ac
AK		 4266#ifdef CONFIG_X86_64
4267 /*
4268 * Load null selectors, so we can avoid reloading them in
4269 * __vmx_load_host_state(), in case userspace uses the null selectors
4270 * too (the expected case).
4271 */
4272 vmcs_write16(HOST_DS_SELECTOR, 0);
4273 vmcs_write16(HOST_ES_SELECTOR, 0);
4274#else
a3a8ff8e
NHE		 4275 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4276 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
b2da15ac 4277#endif
a3a8ff8e
NHE		 4278 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4279 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
4280
4281 native_store_idt(&dt);
4282 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
a547c6db 4283 vmx->host_idt_base = dt.address;
a3a8ff8e 4284
83287ea4 4285 vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
a3a8ff8e
NHE		 4286
4287 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4288 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4289 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4290 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
4291
4292 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4293 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4294 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4295 }
4296}
4297
bf8179a0
NHE		 4298static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4299{
4300 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4301 if (enable_ept)
4302 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
fe3ef05c
NHE		 4303 if (is_guest_mode(&vmx->vcpu))
4304 vmx->vcpu.arch.cr4_guest_owned_bits &=
4305 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
bf8179a0
NHE		 4306 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4307}
4308
01e439be
YZ		 4309static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4310{
4311 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4312
4313 if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4314 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4315 return pin_based_exec_ctrl;
4316}
4317
bf8179a0
NHE		 4318static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4319{
4320 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
d16c293e
PB		 4321
4322 if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
4323 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
4324
bf8179a0
NHE		 4325 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
4326 exec_control &= ~CPU_BASED_TPR_SHADOW;
4327#ifdef CONFIG_X86_64
4328 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4329 CPU_BASED_CR8_LOAD_EXITING;
4330#endif
4331 }
4332 if (!enable_ept)
4333 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4334 CPU_BASED_CR3_LOAD_EXITING |
4335 CPU_BASED_INVLPG_EXITING;
4336 return exec_control;
4337}
4338
4339static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4340{
4341 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4342 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4343 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4344 if (vmx->vpid == 0)
4345 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4346 if (!enable_ept) {
4347 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4348 enable_unrestricted_guest = 0;
ad756a16
MJ		 4349 /* Enable INVPCID for non-ept guests may cause performance regression. */
4350 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
bf8179a0
NHE		 4351 }
4352 if (!enable_unrestricted_guest)
4353 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4354 if (!ple_gap)
4355 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
c7c9c56c
YZ		 4356 if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4357 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4358 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
8d14695f 4359 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
abc4fc58
AG		 4360 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4361 (handle_vmptrld).
4362 We can NOT enable shadow_vmcs here because we don't have yet
4363 a current VMCS12
4364 */
4365 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
bf8179a0
NHE		 4366 return exec_control;
4367}
4368
ce88decf
XG		 4369static void ept_set_mmio_spte_mask(void)
4370{
4371 /*
4372 * EPT Misconfigurations can be generated if the value of bits 2:0
4373 * of an EPT paging-structure entry is 110b (write/execute).
885032b9 4374 * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
ce88decf
XG		 4375 * spte.
4376 */
885032b9 4377 kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
ce88decf
XG		 4378}
4379
6aa8b732
AK		 4380/*
4381 * Sets up the vmcs for emulated real mode.
4382 */
8b9cf98c 4383static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 4384{
2e4ce7f5 4385#ifdef CONFIG_X86_64
6aa8b732 4386 unsigned long a;
2e4ce7f5 4387#endif
6aa8b732 4388 int i;
6aa8b732 4389
6aa8b732 4390 /* I/O */
3e7c73e9
AK		 4391 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4392 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 4393
4607c2d7
AG		 4394 if (enable_shadow_vmcs) {
4395 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4396 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4397 }
25c5f225 4398 if (cpu_has_vmx_msr_bitmap())
5897297b 4399 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 4400
6aa8b732
AK		 4401 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4402
6aa8b732 4403 /* Control */
01e439be 4404 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
6e5d865c 4405
bf8179a0 4406 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
6aa8b732 4407
83ff3b9d 4408 if (cpu_has_secondary_exec_ctrls()) {
bf8179a0
NHE		 4409 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4410 vmx_secondary_exec_control(vmx));
83ff3b9d 4411 }
f78e0e2e 4412
01e439be 4413 if (vmx_vm_has_apicv(vmx->vcpu.kvm)) {
c7c9c56c
YZ		 4414 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4415 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4416 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4417 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4418
4419 vmcs_write16(GUEST_INTR_STATUS, 0);
01e439be
YZ		 4420
4421 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4422 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
c7c9c56c
YZ		 4423 }
4424
4b8d54f9
ZE		 4425 if (ple_gap) {
4426 vmcs_write32(PLE_GAP, ple_gap);
a7653ecd
RK		 4427 vmx->ple_window = ple_window;
4428 vmx->ple_window_dirty = true;
4b8d54f9
ZE		 4429 }
4430
c3707958
XG		 4431 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4432 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
6aa8b732
AK		 4433 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
4434
9581d442
AK		 4435 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
4436 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
a547c6db 4437 vmx_set_constant_host_state(vmx);
05b3e0c2 4438#ifdef CONFIG_X86_64
6aa8b732
AK		 4439 rdmsrl(MSR_FS_BASE, a);
4440 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4441 rdmsrl(MSR_GS_BASE, a);
4442 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4443#else
4444 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4445 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4446#endif
4447
2cc51560
ED		 4448 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4449 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
61d2ef2c 4450 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2cc51560 4451 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
61d2ef2c 4452 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
6aa8b732 4453
468d472f 4454 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
a3a8ff8e
NHE		 4455 u32 msr_low, msr_high;
4456 u64 host_pat;
468d472f
SY		 4457 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
4458 host_pat = msr_low | ((u64) msr_high << 32);
4459 /* Write the default value follow host pat */
4460 vmcs_write64(GUEST_IA32_PAT, host_pat);
4461 /* Keep arch.pat sync with GUEST_IA32_PAT */
4462 vmx->vcpu.arch.pat = host_pat;
4463 }
4464
03916db9 4465 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
6aa8b732
AK		 4466 u32 index = vmx_msr_index[i];
4467 u32 data_low, data_high;
a2fa3e9f 4468 int j = vmx->nmsrs;
6aa8b732
AK		 4469
4470 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4471 continue;
432bd6cb
AK		 4472 if (wrmsr_safe(index, data_low, data_high) < 0)
4473 continue;
26bb0981
AK		 4474 vmx->guest_msrs[j].index = i;
4475 vmx->guest_msrs[j].data = 0;
d5696725 4476 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 4477 ++vmx->nmsrs;
6aa8b732 4478 }
6aa8b732 4479
2961e876
GN		 4480
4481 vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 4482
4483 /* 22.2.1, 20.8.1 */
2961e876 4484 vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
1c3d14fe 4485
e00c8cf2 4486 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
bf8179a0 4487 set_cr4_guest_host_mask(vmx);
e00c8cf2
AK		 4488
4489 return 0;
4490}
4491
57f252f2 4492static void vmx_vcpu_reset(struct kvm_vcpu *vcpu)
e00c8cf2
AK		 4493{
4494 struct vcpu_vmx *vmx = to_vmx(vcpu);
58cb628d 4495 struct msr_data apic_base_msr;
e00c8cf2 4496
7ffd92c5 4497 vmx->rmode.vm86_active = 0;
e00c8cf2 4498
3b86cd99
JK		 4499 vmx->soft_vnmi_blocked = 0;
4500
ad312c7c 4501 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 4502 kvm_set_cr8(&vmx->vcpu, 0);
58cb628d 4503 apic_base_msr.data = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 4504 if (kvm_vcpu_is_bsp(&vmx->vcpu))
58cb628d
JK		 4505 apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4506 apic_base_msr.host_initiated = true;
4507 kvm_set_apic_base(&vmx->vcpu, &apic_base_msr);
e00c8cf2 4508
2fb92db1
AK		 4509 vmx_segment_cache_clear(vmx);
4510
5706be0d 4511 seg_setup(VCPU_SREG_CS);
66450a21 4512 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
04b66839 4513 vmcs_write32(GUEST_CS_BASE, 0xffff0000);
e00c8cf2
AK		 4514
4515 seg_setup(VCPU_SREG_DS);
4516 seg_setup(VCPU_SREG_ES);
4517 seg_setup(VCPU_SREG_FS);
4518 seg_setup(VCPU_SREG_GS);
4519 seg_setup(VCPU_SREG_SS);
4520
4521 vmcs_write16(GUEST_TR_SELECTOR, 0);
4522 vmcs_writel(GUEST_TR_BASE, 0);
4523 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4524 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4525
4526 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4527 vmcs_writel(GUEST_LDTR_BASE, 0);
4528 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4529 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4530
4531 vmcs_write32(GUEST_SYSENTER_CS, 0);
4532 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4533 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4534
4535 vmcs_writel(GUEST_RFLAGS, 0x02);
66450a21 4536 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 4537
e00c8cf2
AK		 4538 vmcs_writel(GUEST_GDTR_BASE, 0);
4539 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4540
4541 vmcs_writel(GUEST_IDTR_BASE, 0);
4542 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4543
443381a8 4544 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
e00c8cf2
AK		 4545 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4546 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4547
e00c8cf2
AK		 4548 /* Special registers */
4549 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4550
4551 setup_msrs(vmx);
4552
6aa8b732
AK		 4553 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
4554
f78e0e2e
SY		 4555 if (cpu_has_vmx_tpr_shadow()) {
4556 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4557 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
4558 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
afc20184 4559 __pa(vmx->vcpu.arch.apic->regs));
f78e0e2e
SY		 4560 vmcs_write32(TPR_THRESHOLD, 0);
4561 }
4562
4563 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4564 vmcs_write64(APIC_ACCESS_ADDR,
bfc6d222 4565 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
6aa8b732 4566
01e439be
YZ		 4567 if (vmx_vm_has_apicv(vcpu->kvm))
4568 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
4569
2384d2b3
SY		 4570 if (vmx->vpid != 0)
4571 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4572
fa40052c 4573 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4d4ec087 4574 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
8b9cf98c 4575 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 4576 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 4577 vmx_fpu_activate(&vmx->vcpu);
4578 update_exception_bitmap(&vmx->vcpu);
6aa8b732 4579
b9d762fa 4580 vpid_sync_context(vmx);
6aa8b732
AK		 4581}
4582
b6f1250e
NHE		 4583/*
4584 * In nested virtualization, check if L1 asked to exit on external interrupts.
4585 * For most existing hypervisors, this will always return true.
4586 */
4587static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4588{
4589 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4590 PIN_BASED_EXT_INTR_MASK;
4591}
4592
77b0f5d6
BD		 4593/*
4594 * In nested virtualization, check if L1 has set
4595 * VM_EXIT_ACK_INTR_ON_EXIT
4596 */
4597static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
4598{
4599 return get_vmcs12(vcpu)->vm_exit_controls &
4600 VM_EXIT_ACK_INTR_ON_EXIT;
4601}
4602
ea8ceb83
JK		 4603static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
4604{
4605 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4606 PIN_BASED_NMI_EXITING;
4607}
4608
c9a7953f 4609static void enable_irq_window(struct kvm_vcpu *vcpu)
3b86cd99
JK		 4610{
4611 u32 cpu_based_vm_exec_control;
730dca42 4612
3b86cd99
JK		 4613 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4614 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4615 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4616}
4617
c9a7953f 4618static void enable_nmi_window(struct kvm_vcpu *vcpu)
3b86cd99
JK		 4619{
4620 u32 cpu_based_vm_exec_control;
4621
c9a7953f
JK		 4622 if (!cpu_has_virtual_nmis() ||
4623 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4624 enable_irq_window(vcpu);
4625 return;
4626 }
3b86cd99
JK		 4627
4628 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4629 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4630 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4631}
4632
66fd3f7f 4633static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 4634{
9c8cba37 4635 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 4636 uint32_t intr;
4637 int irq = vcpu->arch.interrupt.nr;
9c8cba37 4638
229456fc 4639 trace_kvm_inj_virq(irq);
2714d1d3 4640
fa89a817 4641 ++vcpu->stat.irq_injections;
7ffd92c5 4642 if (vmx->rmode.vm86_active) {
71f9833b
SH		 4643 int inc_eip = 0;
4644 if (vcpu->arch.interrupt.soft)
4645 inc_eip = vcpu->arch.event_exit_inst_len;
4646 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
a92601bb 4647 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
85f455f7
ED		 4648 return;
4649 }
66fd3f7f
GN		 4650 intr = irq | INTR_INFO_VALID_MASK;
4651 if (vcpu->arch.interrupt.soft) {
4652 intr |= INTR_TYPE_SOFT_INTR;
4653 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4654 vmx->vcpu.arch.event_exit_inst_len);
4655 } else
4656 intr |= INTR_TYPE_EXT_INTR;
4657 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
85f455f7
ED		 4658}
4659
f08864b4
SY		 4660static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4661{
66a5a347
JK		 4662 struct vcpu_vmx *vmx = to_vmx(vcpu);
4663
0b6ac343
NHE		 4664 if (is_guest_mode(vcpu))
4665 return;
4666
3b86cd99
JK		 4667 if (!cpu_has_virtual_nmis()) {
4668 /*
4669 * Tracking the NMI-blocked state in software is built upon
4670 * finding the next open IRQ window. This, in turn, depends on
4671 * well-behaving guests: They have to keep IRQs disabled at
4672 * least as long as the NMI handler runs. Otherwise we may
4673 * cause NMI nesting, maybe breaking the guest. But as this is
4674 * highly unlikely, we can live with the residual risk.
4675 */
4676 vmx->soft_vnmi_blocked = 1;
4677 vmx->vnmi_blocked_time = 0;
4678 }
4679
487b391d 4680 ++vcpu->stat.nmi_injections;
9d58b931 4681 vmx->nmi_known_unmasked = false;
7ffd92c5 4682 if (vmx->rmode.vm86_active) {
71f9833b 4683 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
a92601bb 4684 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
66a5a347
JK		 4685 return;
4686 }
f08864b4
SY		 4687 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4688 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
f08864b4
SY		 4689}
4690
3cfc3092
JK		 4691static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4692{
4693 if (!cpu_has_virtual_nmis())
4694 return to_vmx(vcpu)->soft_vnmi_blocked;
9d58b931
AK		 4695 if (to_vmx(vcpu)->nmi_known_unmasked)
4696 return false;
c332c83a 4697 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3cfc3092
JK		 4698}
4699
4700static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4701{
4702 struct vcpu_vmx *vmx = to_vmx(vcpu);
4703
4704 if (!cpu_has_virtual_nmis()) {
4705 if (vmx->soft_vnmi_blocked != masked) {
4706 vmx->soft_vnmi_blocked = masked;
4707 vmx->vnmi_blocked_time = 0;
4708 }
4709 } else {
9d58b931 4710 vmx->nmi_known_unmasked = !masked;
3cfc3092
JK		 4711 if (masked)
4712 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4713 GUEST_INTR_STATE_NMI);
4714 else
4715 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4716 GUEST_INTR_STATE_NMI);
4717 }
4718}
4719
2505dc9f
JK		 4720static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4721{
b6b8a145
JK		 4722 if (to_vmx(vcpu)->nested.nested_run_pending)
4723 return 0;
ea8ceb83 4724
2505dc9f
JK		 4725 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
4726 return 0;
4727
4728 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4729 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4730 | GUEST_INTR_STATE_NMI));
4731}
4732
78646121
GN		 4733static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4734{
b6b8a145
JK		 4735 return (!to_vmx(vcpu)->nested.nested_run_pending &&
4736 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
c4282df9
GN		 4737 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4738 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 4739}
4740
cbc94022
IE		 4741static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4742{
4743 int ret;
4744 struct kvm_userspace_memory_region tss_mem = {
6fe63979 4745 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 4746 .guest_phys_addr = addr,
4747 .memory_size = PAGE_SIZE * 3,
4748 .flags = 0,
4749 };
4750
47ae31e2 4751 ret = kvm_set_memory_region(kvm, &tss_mem);
cbc94022
IE		 4752 if (ret)
4753 return ret;
bfc6d222 4754 kvm->arch.tss_addr = addr;
93ea5388
GN		 4755 if (!init_rmode_tss(kvm))
4756 return -ENOMEM;
4757
cbc94022
IE		 4758 return 0;
4759}
4760
0ca1b4f4 4761static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
6aa8b732 4762{
77ab6db0 4763 switch (vec) {
77ab6db0 4764 case BP_VECTOR:
c573cd22
JK		 4765 /*
4766 * Update instruction length as we may reinject the exception
4767 * from user space while in guest debugging mode.
4768 */
4769 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4770 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940 4771 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
0ca1b4f4
GN		 4772 return false;
4773 /* fall through */
4774 case DB_VECTOR:
4775 if (vcpu->guest_debug &
4776 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4777 return false;
d0bfb940
JK		 4778 /* fall through */
4779 case DE_VECTOR:
77ab6db0
JK		 4780 case OF_VECTOR:
4781 case BR_VECTOR:
4782 case UD_VECTOR:
4783 case DF_VECTOR:
4784 case SS_VECTOR:
4785 case GP_VECTOR:
4786 case MF_VECTOR:
0ca1b4f4
GN		 4787 return true;
4788 break;
77ab6db0 4789 }
0ca1b4f4
GN		 4790 return false;
4791}
4792
4793static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4794 int vec, u32 err_code)
4795{
4796 /*
4797 * Instruction with address size override prefix opcode 0x67
4798 * Cause the #SS fault with 0 error code in VM86 mode.
4799 */
4800 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4801 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
4802 if (vcpu->arch.halt_request) {
4803 vcpu->arch.halt_request = 0;
4804 return kvm_emulate_halt(vcpu);
4805 }
4806 return 1;
4807 }
4808 return 0;
4809 }
4810
4811 /*
4812 * Forward all other exceptions that are valid in real mode.
4813 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4814 * the required debugging infrastructure rework.
4815 */
4816 kvm_queue_exception(vcpu, vec);
4817 return 1;
6aa8b732
AK		 4818}
4819
a0861c02
AK		 4820/*
4821 * Trigger machine check on the host. We assume all the MSRs are already set up
4822 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4823 * We pass a fake environment to the machine check handler because we want
4824 * the guest to be always treated like user space, no matter what context
4825 * it used internally.
4826 */
4827static void kvm_machine_check(void)
4828{
4829#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4830 struct pt_regs regs = {
4831 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4832 .flags = X86_EFLAGS_IF,
4833 };
4834
4835 do_machine_check(&regs, 0);
4836#endif
4837}
4838
851ba692 4839static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK		 4840{
4841 /* already handled by vcpu_run */
4842 return 1;
4843}
4844
851ba692 4845static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 4846{
1155f76a 4847 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 4848 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 4849 u32 intr_info, ex_no, error_code;
42dbaa5a 4850 unsigned long cr2, rip, dr6;
6aa8b732
AK		 4851 u32 vect_info;
4852 enum emulation_result er;
4853
1155f76a 4854 vect_info = vmx->idt_vectoring_info;
88786475 4855 intr_info = vmx->exit_intr_info;
6aa8b732 4856
a0861c02 4857 if (is_machine_check(intr_info))
851ba692 4858 return handle_machine_check(vcpu);
a0861c02 4859
e4a41889 4860 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 4861 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 4862
4863 if (is_no_device(intr_info)) {
5fd86fcf 4864 vmx_fpu_activate(vcpu);
2ab455cc
AL		 4865 return 1;
4866 }
4867
7aa81cc0 4868 if (is_invalid_opcode(intr_info)) {
51d8b661 4869 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
7aa81cc0 4870 if (er != EMULATE_DONE)
7ee5d940 4871 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 4872 return 1;
4873 }
4874
6aa8b732 4875 error_code = 0;
2e11384c 4876 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732 4877 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
bf4ca23e
XG		 4878
4879 /*
4880 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4881 * MMIO, it is better to report an internal error.
4882 * See the comments in vmx_handle_exit.
4883 */
4884 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4885 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4886 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4887 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4888 vcpu->run->internal.ndata = 2;
4889 vcpu->run->internal.data[0] = vect_info;
4890 vcpu->run->internal.data[1] = intr_info;
4891 return 0;
4892 }
4893
6aa8b732 4894 if (is_page_fault(intr_info)) {
1439442c 4895 /* EPT won't cause page fault directly */
cf3ace79 4896 BUG_ON(enable_ept);
6aa8b732 4897 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT		 4898 trace_kvm_page_fault(cr2, error_code);
4899
3298b75c 4900 if (kvm_event_needs_reinjection(vcpu))
577bdc49 4901 kvm_mmu_unprotect_page_virt(vcpu, cr2);
dc25e89e 4902 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
6aa8b732
AK		 4903 }
4904
d0bfb940 4905 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
0ca1b4f4
GN		 4906
4907 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4908 return handle_rmode_exception(vcpu, ex_no, error_code);
4909
42dbaa5a
JK		 4910 switch (ex_no) {
4911 case DB_VECTOR:
4912 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4913 if (!(vcpu->guest_debug &
4914 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
8246bf52 4915 vcpu->arch.dr6 &= ~15;
6f43ed01 4916 vcpu->arch.dr6 |= dr6 | DR6_RTM;
fd2a445a
HD		 4917 if (!(dr6 & ~DR6_RESERVED)) /* icebp */
4918 skip_emulated_instruction(vcpu);
4919
42dbaa5a
JK		 4920 kvm_queue_exception(vcpu, DB_VECTOR);
4921 return 1;
4922 }
4923 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4924 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4925 /* fall through */
4926 case BP_VECTOR:
c573cd22
JK		 4927 /*
4928 * Update instruction length as we may reinject #BP from
4929 * user space while in guest debugging mode. Reading it for
4930 * #DB as well causes no harm, it is not used in that case.
4931 */
4932 vmx->vcpu.arch.event_exit_inst_len =
4933 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 4934 kvm_run->exit_reason = KVM_EXIT_DEBUG;
0a434bb2 4935 rip = kvm_rip_read(vcpu);
d0bfb940
JK		 4936 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4937 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 4938 break;
4939 default:
d0bfb940
JK		 4940 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4941 kvm_run->ex.exception = ex_no;
4942 kvm_run->ex.error_code = error_code;
42dbaa5a 4943 break;
6aa8b732 4944 }
6aa8b732
AK		 4945 return 0;
4946}
4947
851ba692 4948static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 4949{
1165f5fe 4950 ++vcpu->stat.irq_exits;
6aa8b732
AK		 4951 return 1;
4952}
4953
851ba692 4954static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 4955{
851ba692 4956 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK		 4957 return 0;
4958}
6aa8b732 4959
851ba692 4960static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 4961{
bfdaab09 4962 unsigned long exit_qualification;
34c33d16 4963 int size, in, string;
039576c0 4964 unsigned port;
6aa8b732 4965
bfdaab09 4966 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 4967 string = (exit_qualification & 16) != 0;
cf8f70bf 4968 in = (exit_qualification & 8) != 0;
e70669ab 4969
cf8f70bf 4970 ++vcpu->stat.io_exits;
e70669ab 4971
cf8f70bf 4972 if (string || in)
51d8b661 4973 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
e70669ab 4974
cf8f70bf
GN		 4975 port = exit_qualification >> 16;
4976 size = (exit_qualification & 7) + 1;
e93f36bc 4977 skip_emulated_instruction(vcpu);
cf8f70bf
GN		 4978
4979 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 4980}
4981
102d8325
IM		 4982static void
4983vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4984{
4985 /*
4986 * Patch in the VMCALL instruction:
4987 */
4988 hypercall[0] = 0x0f;
4989 hypercall[1] = 0x01;
4990 hypercall[2] = 0xc1;
102d8325
IM		 4991}
4992
92fbc7b1
JK		 4993static bool nested_cr0_valid(struct vmcs12 *vmcs12, unsigned long val)
4994{
4995 unsigned long always_on = VMXON_CR0_ALWAYSON;
4996
4997 if (nested_vmx_secondary_ctls_high &
4998 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
4999 nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
5000 always_on &= ~(X86_CR0_PE | X86_CR0_PG);
5001 return (val & always_on) == always_on;
5002}
5003
0fa06071 5004/* called to set cr0 as appropriate for a mov-to-cr0 exit. */
eeadf9e7
NHE		 5005static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
5006{
eeadf9e7 5007 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 5008 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5009 unsigned long orig_val = val;
5010
eeadf9e7
NHE		 5011 /*
5012 * We get here when L2 changed cr0 in a way that did not change
5013 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
1a0d74e6
JK		 5014 * but did change L0 shadowed bits. So we first calculate the
5015 * effective cr0 value that L1 would like to write into the
5016 * hardware. It consists of the L2-owned bits from the new
5017 * value combined with the L1-owned bits from L1's guest_cr0.
eeadf9e7 5018 */
1a0d74e6
JK		 5019 val = (val & ~vmcs12->cr0_guest_host_mask) |
5020 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
5021
92fbc7b1 5022 if (!nested_cr0_valid(vmcs12, val))
eeadf9e7 5023 return 1;
1a0d74e6
JK		 5024
5025 if (kvm_set_cr0(vcpu, val))
5026 return 1;
5027 vmcs_writel(CR0_READ_SHADOW, orig_val);
eeadf9e7 5028 return 0;
1a0d74e6
JK		 5029 } else {
5030 if (to_vmx(vcpu)->nested.vmxon &&
5031 ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
5032 return 1;
eeadf9e7 5033 return kvm_set_cr0(vcpu, val);
1a0d74e6 5034 }
eeadf9e7
NHE		 5035}
5036
5037static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
5038{
5039 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 5040 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5041 unsigned long orig_val = val;
5042
5043 /* analogously to handle_set_cr0 */
5044 val = (val & ~vmcs12->cr4_guest_host_mask) |
5045 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
5046 if (kvm_set_cr4(vcpu, val))
eeadf9e7 5047 return 1;
1a0d74e6 5048 vmcs_writel(CR4_READ_SHADOW, orig_val);
eeadf9e7
NHE		 5049 return 0;
5050 } else
5051 return kvm_set_cr4(vcpu, val);
5052}
5053
5054/* called to set cr0 as approriate for clts instruction exit. */
5055static void handle_clts(struct kvm_vcpu *vcpu)
5056{
5057 if (is_guest_mode(vcpu)) {
5058 /*
5059 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
5060 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
5061 * just pretend it's off (also in arch.cr0 for fpu_activate).
5062 */
5063 vmcs_writel(CR0_READ_SHADOW,
5064 vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
5065 vcpu->arch.cr0 &= ~X86_CR0_TS;
5066 } else
5067 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
5068}
5069
851ba692 5070static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 5071{
229456fc 5072 unsigned long exit_qualification, val;
6aa8b732
AK		 5073 int cr;
5074 int reg;
49a9b07e 5075 int err;
6aa8b732 5076
bfdaab09 5077 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 5078 cr = exit_qualification & 15;
5079 reg = (exit_qualification >> 8) & 15;
5080 switch ((exit_qualification >> 4) & 3) {
5081 case 0: /* mov to cr */
1e32c079 5082 val = kvm_register_readl(vcpu, reg);
229456fc 5083 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 5084 switch (cr) {
5085 case 0:
eeadf9e7 5086 err = handle_set_cr0(vcpu, val);
db8fcefa 5087 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 5088 return 1;
5089 case 3:
2390218b 5090 err = kvm_set_cr3(vcpu, val);
db8fcefa 5091 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 5092 return 1;
5093 case 4:
eeadf9e7 5094 err = handle_set_cr4(vcpu, val);
db8fcefa 5095 kvm_complete_insn_gp(vcpu, err);
6aa8b732 5096 return 1;
0a5fff19
GN		 5097 case 8: {
5098 u8 cr8_prev = kvm_get_cr8(vcpu);
1e32c079 5099 u8 cr8 = (u8)val;
eea1cff9 5100 err = kvm_set_cr8(vcpu, cr8);
db8fcefa 5101 kvm_complete_insn_gp(vcpu, err);
0a5fff19
GN		 5102 if (irqchip_in_kernel(vcpu->kvm))
5103 return 1;
5104 if (cr8_prev <= cr8)
5105 return 1;
851ba692 5106 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 5107 return 0;
5108 }
4b8073e4 5109 }
6aa8b732 5110 break;
25c4c276 5111 case 2: /* clts */
eeadf9e7 5112 handle_clts(vcpu);
4d4ec087 5113 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
25c4c276 5114 skip_emulated_instruction(vcpu);
6b52d186 5115 vmx_fpu_activate(vcpu);
25c4c276 5116 return 1;
6aa8b732
AK		 5117 case 1: /*mov from cr*/
5118 switch (cr) {
5119 case 3:
9f8fe504
AK		 5120 val = kvm_read_cr3(vcpu);
5121 kvm_register_write(vcpu, reg, val);
5122 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 5123 skip_emulated_instruction(vcpu);
5124 return 1;
5125 case 8:
229456fc
MT		 5126 val = kvm_get_cr8(vcpu);
5127 kvm_register_write(vcpu, reg, val);
5128 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 5129 skip_emulated_instruction(vcpu);
5130 return 1;
5131 }
5132 break;
5133 case 3: /* lmsw */
a1f83a74 5134 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 5135 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 5136 kvm_lmsw(vcpu, val);
6aa8b732
AK		 5137
5138 skip_emulated_instruction(vcpu);
5139 return 1;
5140 default:
5141 break;
5142 }
851ba692 5143 vcpu->run->exit_reason = 0;
a737f256 5144 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 5145 (int)(exit_qualification >> 4) & 3, cr);
5146 return 0;
5147}
5148
851ba692 5149static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 5150{
bfdaab09 5151 unsigned long exit_qualification;
6aa8b732
AK		 5152 int dr, reg;
5153
f2483415 5154 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK		 5155 if (!kvm_require_cpl(vcpu, 0))
5156 return 1;
42dbaa5a
JK		 5157 dr = vmcs_readl(GUEST_DR7);
5158 if (dr & DR7_GD) {
5159 /*
5160 * As the vm-exit takes precedence over the debug trap, we
5161 * need to emulate the latter, either for the host or the
5162 * guest debugging itself.
5163 */
5164 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692
AK		 5165 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
5166 vcpu->run->debug.arch.dr7 = dr;
5167 vcpu->run->debug.arch.pc =
42dbaa5a
JK		 5168 vmcs_readl(GUEST_CS_BASE) +
5169 vmcs_readl(GUEST_RIP);
851ba692
AK		 5170 vcpu->run->debug.arch.exception = DB_VECTOR;
5171 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 5172 return 0;
5173 } else {
5174 vcpu->arch.dr7 &= ~DR7_GD;
6f43ed01 5175 vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
42dbaa5a
JK		 5176 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
5177 kvm_queue_exception(vcpu, DB_VECTOR);
5178 return 1;
5179 }
5180 }
5181
81908bf4
PB		 5182 if (vcpu->guest_debug == 0) {
5183 u32 cpu_based_vm_exec_control;
5184
5185 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5186 cpu_based_vm_exec_control &= ~CPU_BASED_MOV_DR_EXITING;
5187 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5188
5189 /*
5190 * No more DR vmexits; force a reload of the debug registers
5191 * and reenter on this instruction. The next vmexit will
5192 * retrieve the full state of the debug registers.
5193 */
5194 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5195 return 1;
5196 }
5197
bfdaab09 5198 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
42dbaa5a
JK		 5199 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5200 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5201 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079 5202 unsigned long val;
4c4d563b
JK		 5203
5204 if (kvm_get_dr(vcpu, dr, &val))
5205 return 1;
5206 kvm_register_write(vcpu, reg, val);
020df079 5207 } else
5777392e 5208 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
4c4d563b
JK		 5209 return 1;
5210
6aa8b732
AK		 5211 skip_emulated_instruction(vcpu);
5212 return 1;
5213}
5214
73aaf249
JK		 5215static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
5216{
5217 return vcpu->arch.dr6;
5218}
5219
5220static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
5221{
5222}
5223
81908bf4
PB		 5224static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5225{
5226 u32 cpu_based_vm_exec_control;
5227
5228 get_debugreg(vcpu->arch.db[0], 0);
5229 get_debugreg(vcpu->arch.db[1], 1);
5230 get_debugreg(vcpu->arch.db[2], 2);
5231 get_debugreg(vcpu->arch.db[3], 3);
5232 get_debugreg(vcpu->arch.dr6, 6);
5233 vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5234
5235 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
5236
5237 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5238 cpu_based_vm_exec_control |= CPU_BASED_MOV_DR_EXITING;
5239 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5240}
5241
020df079
GN		 5242static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5243{
5244 vmcs_writel(GUEST_DR7, val);
5245}
5246
851ba692 5247static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 5248{
06465c5a
AK		 5249 kvm_emulate_cpuid(vcpu);
5250 return 1;
6aa8b732
AK		 5251}
5252
851ba692 5253static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 5254{
ad312c7c 5255 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 5256 u64 data;
5257
5258 if (vmx_get_msr(vcpu, ecx, &data)) {
59200273 5259 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 5260 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 5261 return 1;
5262 }
5263
229456fc 5264 trace_kvm_msr_read(ecx, data);
2714d1d3 5265
6aa8b732 5266 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 5267 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
5268 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 5269 skip_emulated_instruction(vcpu);
5270 return 1;
5271}
5272
851ba692 5273static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 5274{
8fe8ab46 5275 struct msr_data msr;
ad312c7c
ZX		 5276 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5277 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5278 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732 5279
8fe8ab46
WA		 5280 msr.data = data;
5281 msr.index = ecx;
5282 msr.host_initiated = false;
5283 if (vmx_set_msr(vcpu, &msr) != 0) {
59200273 5284 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 5285 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 5286 return 1;
5287 }
5288
59200273 5289 trace_kvm_msr_write(ecx, data);
6aa8b732
AK		 5290 skip_emulated_instruction(vcpu);
5291 return 1;
5292}
5293
851ba692 5294static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c 5295{
3842d135 5296 kvm_make_request(KVM_REQ_EVENT, vcpu);
6e5d865c
YS		 5297 return 1;
5298}
5299
851ba692 5300static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 5301{
85f455f7
ED		 5302 u32 cpu_based_vm_exec_control;
5303
5304 /* clear pending irq */
5305 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5306 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5307 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3 5308
3842d135
AK		 5309 kvm_make_request(KVM_REQ_EVENT, vcpu);
5310
a26bf12a 5311 ++vcpu->stat.irq_window_exits;
2714d1d3 5312
c1150d8c
DL		 5313 /*
5314 * If the user space waits to inject interrupts, exit as soon as
5315 * possible
5316 */
8061823a 5317 if (!irqchip_in_kernel(vcpu->kvm) &&
851ba692 5318 vcpu->run->request_interrupt_window &&
8061823a 5319 !kvm_cpu_has_interrupt(vcpu)) {
851ba692 5320 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
c1150d8c
DL		 5321 return 0;
5322 }
6aa8b732
AK		 5323 return 1;
5324}
5325
851ba692 5326static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732
AK		 5327{
5328 skip_emulated_instruction(vcpu);
d3bef15f 5329 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 5330}
5331
851ba692 5332static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 5333{
510043da 5334 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 5335 kvm_emulate_hypercall(vcpu);
5336 return 1;
c21415e8
IM		 5337}
5338
ec25d5e6
GN		 5339static int handle_invd(struct kvm_vcpu *vcpu)
5340{
51d8b661 5341 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
ec25d5e6
GN		 5342}
5343
851ba692 5344static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 5345{
f9c617f6 5346 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 5347
5348 kvm_mmu_invlpg(vcpu, exit_qualification);
5349 skip_emulated_instruction(vcpu);
5350 return 1;
5351}
5352
fee84b07
AK		 5353static int handle_rdpmc(struct kvm_vcpu *vcpu)
5354{
5355 int err;
5356
5357 err = kvm_rdpmc(vcpu);
5358 kvm_complete_insn_gp(vcpu, err);
5359
5360 return 1;
5361}
5362
851ba692 5363static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01
ED		 5364{
5365 skip_emulated_instruction(vcpu);
f5f48ee1 5366 kvm_emulate_wbinvd(vcpu);
e5edaa01
ED		 5367 return 1;
5368}
5369
2acf923e
DC		 5370static int handle_xsetbv(struct kvm_vcpu *vcpu)
5371{
5372 u64 new_bv = kvm_read_edx_eax(vcpu);
5373 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5374
5375 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5376 skip_emulated_instruction(vcpu);
5377 return 1;
5378}
5379
851ba692 5380static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 5381{
58fbbf26
KT		 5382 if (likely(fasteoi)) {
5383 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5384 int access_type, offset;
5385
5386 access_type = exit_qualification & APIC_ACCESS_TYPE;
5387 offset = exit_qualification & APIC_ACCESS_OFFSET;
5388 /*
5389 * Sane guest uses MOV to write EOI, with written value
5390 * not cared. So make a short-circuit here by avoiding
5391 * heavy instruction emulation.
5392 */
5393 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5394 (offset == APIC_EOI)) {
5395 kvm_lapic_set_eoi(vcpu);
5396 skip_emulated_instruction(vcpu);
5397 return 1;
5398 }
5399 }
51d8b661 5400 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
f78e0e2e
SY		 5401}
5402
c7c9c56c
YZ		 5403static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5404{
5405 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5406 int vector = exit_qualification & 0xff;
5407
5408 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5409 kvm_apic_set_eoi_accelerated(vcpu, vector);
5410 return 1;
5411}
5412
83d4c286
YZ		 5413static int handle_apic_write(struct kvm_vcpu *vcpu)
5414{
5415 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5416 u32 offset = exit_qualification & 0xfff;
5417
5418 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5419 kvm_apic_write_nodecode(vcpu, offset);
5420 return 1;
5421}
5422
851ba692 5423static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 5424{
60637aac 5425 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 5426 unsigned long exit_qualification;
e269fb21
JK		 5427 bool has_error_code = false;
5428 u32 error_code = 0;
37817f29 5429 u16 tss_selector;
7f3d35fd 5430 int reason, type, idt_v, idt_index;
64a7ec06
GN		 5431
5432 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
7f3d35fd 5433 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
64a7ec06 5434 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 5435
5436 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5437
5438 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 5439 if (reason == TASK_SWITCH_GATE && idt_v) {
5440 switch (type) {
5441 case INTR_TYPE_NMI_INTR:
5442 vcpu->arch.nmi_injected = false;
654f06fc 5443 vmx_set_nmi_mask(vcpu, true);
64a7ec06
GN		 5444 break;
5445 case INTR_TYPE_EXT_INTR:
66fd3f7f 5446 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 5447 kvm_clear_interrupt_queue(vcpu);
5448 break;
5449 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK		 5450 if (vmx->idt_vectoring_info &
5451 VECTORING_INFO_DELIVER_CODE_MASK) {
5452 has_error_code = true;
5453 error_code =
5454 vmcs_read32(IDT_VECTORING_ERROR_CODE);
5455 }
5456 /* fall through */
64a7ec06
GN		 5457 case INTR_TYPE_SOFT_EXCEPTION:
5458 kvm_clear_exception_queue(vcpu);
5459 break;
5460 default:
5461 break;
5462 }
60637aac 5463 }
37817f29
IE		 5464 tss_selector = exit_qualification;
5465
64a7ec06
GN		 5466 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5467 type != INTR_TYPE_EXT_INTR &&
5468 type != INTR_TYPE_NMI_INTR))
5469 skip_emulated_instruction(vcpu);
5470
7f3d35fd
KW		 5471 if (kvm_task_switch(vcpu, tss_selector,
5472 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5473 has_error_code, error_code) == EMULATE_FAIL) {
acb54517
GN		 5474 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5475 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5476 vcpu->run->internal.ndata = 0;
42dbaa5a 5477 return 0;
acb54517 5478 }
42dbaa5a
JK		 5479
5480 /* clear all local breakpoint enable flags */
1f854112 5481 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~0x55);
42dbaa5a
JK		 5482
5483 /*
5484 * TODO: What about debug traps on tss switch?
5485 * Are we supposed to inject them and update dr6?
5486 */
5487
5488 return 1;
37817f29
IE		 5489}
5490
851ba692 5491static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 5492{
f9c617f6 5493 unsigned long exit_qualification;
1439442c 5494 gpa_t gpa;
4f5982a5 5495 u32 error_code;
1439442c 5496 int gla_validity;
1439442c 5497
f9c617f6 5498 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c 5499
1439442c
SY		 5500 gla_validity = (exit_qualification >> 7) & 0x3;
5501 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5502 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5503 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5504 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 5505 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 5506 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5507 (long unsigned int)exit_qualification);
851ba692
AK		 5508 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5509 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
596ae895 5510 return 0;
1439442c
SY		 5511 }
5512
0be9c7a8
GN		 5513 /*
5514 * EPT violation happened while executing iret from NMI,
5515 * "blocked by NMI" bit has to be set before next VM entry.
5516 * There are errata that may cause this bit to not be set:
5517 * AAK134, BY25.
5518 */
bcd1c294
GN		 5519 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5520 cpu_has_virtual_nmis() &&
5521 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
0be9c7a8
GN		 5522 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5523
1439442c 5524 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 5525 trace_kvm_page_fault(gpa, exit_qualification);
4f5982a5
XG		 5526
5527 /* It is a write fault? */
5528 error_code = exit_qualification & (1U << 1);
25d92081
YZ		 5529 /* It is a fetch fault? */
5530 error_code |= (exit_qualification & (1U << 2)) << 2;
4f5982a5
XG		 5531 /* ept page table is present? */
5532 error_code |= (exit_qualification >> 3) & 0x1;
5533
25d92081
YZ		 5534 vcpu->arch.exit_qualification = exit_qualification;
5535
4f5982a5 5536 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
1439442c
SY		 5537}
5538
68f89400
MT		 5539static u64 ept_rsvd_mask(u64 spte, int level)
5540{
5541 int i;
5542 u64 mask = 0;
5543
5544 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
5545 mask |= (1ULL << i);
5546
a32e8459 5547 if (level == 4)
68f89400
MT		 5548 /* bits 7:3 reserved */
5549 mask |= 0xf8;
a32e8459
WL		 5550 else if (spte & (1ULL << 7))
5551 /*
5552 * 1GB/2MB page, bits 29:12 or 20:12 reserved respectively,
5553 * level == 1 if the hypervisor is using the ignored bit 7.
5554 */
5555 mask |= (PAGE_SIZE << ((level - 1) * 9)) - PAGE_SIZE;
5556 else if (level > 1)
5557 /* bits 6:3 reserved */
5558 mask |= 0x78;
68f89400
MT		 5559
5560 return mask;
5561}
5562
5563static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
5564 int level)
5565{
5566 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
5567
5568 /* 010b (write-only) */
5569 WARN_ON((spte & 0x7) == 0x2);
5570
5571 /* 110b (write/execute) */
5572 WARN_ON((spte & 0x7) == 0x6);
5573
5574 /* 100b (execute-only) and value not supported by logical processor */
5575 if (!cpu_has_vmx_ept_execute_only())
5576 WARN_ON((spte & 0x7) == 0x4);
5577
5578 /* not 000b */
5579 if ((spte & 0x7)) {
5580 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
5581
5582 if (rsvd_bits != 0) {
5583 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
5584 __func__, rsvd_bits);
5585 WARN_ON(1);
5586 }
5587
a32e8459
WL		 5588 /* bits 5:3 are _not_ reserved for large page or leaf page */
5589 if ((rsvd_bits & 0x38) == 0) {
68f89400
MT		 5590 u64 ept_mem_type = (spte & 0x38) >> 3;
5591
5592 if (ept_mem_type == 2 || ept_mem_type == 3 ||
5593 ept_mem_type == 7) {
5594 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
5595 __func__, ept_mem_type);
5596 WARN_ON(1);
5597 }
5598 }
5599 }
5600}
5601
851ba692 5602static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400
MT		 5603{
5604 u64 sptes[4];
ce88decf 5605 int nr_sptes, i, ret;
68f89400
MT		 5606 gpa_t gpa;
5607
5608 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
68c3b4d1
MT		 5609 if (!kvm_io_bus_write(vcpu->kvm, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
5610 skip_emulated_instruction(vcpu);
5611 return 1;
5612 }
68f89400 5613
ce88decf 5614 ret = handle_mmio_page_fault_common(vcpu, gpa, true);
b37fbea6 5615 if (likely(ret == RET_MMIO_PF_EMULATE))
ce88decf
XG		 5616 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5617 EMULATE_DONE;
f8f55942
XG		 5618
5619 if (unlikely(ret == RET_MMIO_PF_INVALID))
5620 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
5621
b37fbea6 5622 if (unlikely(ret == RET_MMIO_PF_RETRY))
ce88decf
XG		 5623 return 1;
5624
5625 /* It is the real ept misconfig */
68f89400
MT		 5626 printk(KERN_ERR "EPT: Misconfiguration.\n");
5627 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
5628
5629 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
5630
5631 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
5632 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
5633
851ba692
AK		 5634 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5635 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT		 5636
5637 return 0;
5638}
5639
851ba692 5640static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4
SY		 5641{
5642 u32 cpu_based_vm_exec_control;
5643
5644 /* clear pending NMI */
5645 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5646 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
5647 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5648 ++vcpu->stat.nmi_window_exits;
3842d135 5649 kvm_make_request(KVM_REQ_EVENT, vcpu);
f08864b4
SY		 5650
5651 return 1;
5652}
5653
80ced186 5654static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 5655{
8b3079a5
AK		 5656 struct vcpu_vmx *vmx = to_vmx(vcpu);
5657 enum emulation_result err = EMULATE_DONE;
80ced186 5658 int ret = 1;
49e9d557
AK		 5659 u32 cpu_exec_ctrl;
5660 bool intr_window_requested;
b8405c18 5661 unsigned count = 130;
49e9d557
AK		 5662
5663 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5664 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
ea953ef0 5665
98eb2f8b 5666 while (vmx->emulation_required && count-- != 0) {
bdea48e3 5667 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
49e9d557
AK		 5668 return handle_interrupt_window(&vmx->vcpu);
5669
de87dcdd
AK		 5670 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5671 return 1;
5672
991eebf9 5673 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
ea953ef0 5674
ac0a48c3 5675 if (err == EMULATE_USER_EXIT) {
94452b9e 5676 ++vcpu->stat.mmio_exits;
80ced186
MG		 5677 ret = 0;
5678 goto out;
5679 }
1d5a4d9b 5680
de5f70e0
AK		 5681 if (err != EMULATE_DONE) {
5682 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5683 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5684 vcpu->run->internal.ndata = 0;
6d77dbfc 5685 return 0;
de5f70e0 5686 }
ea953ef0 5687
8d76c49e
GN		 5688 if (vcpu->arch.halt_request) {
5689 vcpu->arch.halt_request = 0;
5690 ret = kvm_emulate_halt(vcpu);
5691 goto out;
5692 }
5693
ea953ef0 5694 if (signal_pending(current))
80ced186 5695 goto out;
ea953ef0
MG		 5696 if (need_resched())
5697 schedule();
5698 }
5699
80ced186
MG		 5700out:
5701 return ret;
ea953ef0
MG		 5702}
5703
b4a2d31d
RK		 5704static int __grow_ple_window(int val)
5705{
5706 if (ple_window_grow < 1)
5707 return ple_window;
5708
5709 val = min(val, ple_window_actual_max);
5710
5711 if (ple_window_grow < ple_window)
5712 val *= ple_window_grow;
5713 else
5714 val += ple_window_grow;
5715
5716 return val;
5717}
5718
5719static int __shrink_ple_window(int val, int modifier, int minimum)
5720{
5721 if (modifier < 1)
5722 return ple_window;
5723
5724 if (modifier < ple_window)
5725 val /= modifier;
5726 else
5727 val -= modifier;
5728
5729 return max(val, minimum);
5730}
5731
5732static void grow_ple_window(struct kvm_vcpu *vcpu)
5733{
5734 struct vcpu_vmx *vmx = to_vmx(vcpu);
5735 int old = vmx->ple_window;
5736
5737 vmx->ple_window = __grow_ple_window(old);
5738
5739 if (vmx->ple_window != old)
5740 vmx->ple_window_dirty = true;
7b46268d
RK		 5741
5742 trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
b4a2d31d
RK		 5743}
5744
5745static void shrink_ple_window(struct kvm_vcpu *vcpu)
5746{
5747 struct vcpu_vmx *vmx = to_vmx(vcpu);
5748 int old = vmx->ple_window;
5749
5750 vmx->ple_window = __shrink_ple_window(old,
5751 ple_window_shrink, ple_window);
5752
5753 if (vmx->ple_window != old)
5754 vmx->ple_window_dirty = true;
7b46268d
RK		 5755
5756 trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
b4a2d31d
RK		 5757}
5758
5759/*
5760 * ple_window_actual_max is computed to be one grow_ple_window() below
5761 * ple_window_max. (See __grow_ple_window for the reason.)
5762 * This prevents overflows, because ple_window_max is int.
5763 * ple_window_max effectively rounded down to a multiple of ple_window_grow in
5764 * this process.
5765 * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
5766 */
5767static void update_ple_window_actual_max(void)
5768{
5769 ple_window_actual_max =
5770 __shrink_ple_window(max(ple_window_max, ple_window),
5771 ple_window_grow, INT_MIN);
5772}
5773
4b8d54f9
ZE		 5774/*
5775 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5776 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5777 */
9fb41ba8 5778static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9 5779{
b4a2d31d
RK		 5780 if (ple_gap)
5781 grow_ple_window(vcpu);
5782
4b8d54f9
ZE		 5783 skip_emulated_instruction(vcpu);
5784 kvm_vcpu_on_spin(vcpu);
5785
5786 return 1;
5787}
5788
87c00572 5789static int handle_nop(struct kvm_vcpu *vcpu)
59708670 5790{
87c00572 5791 skip_emulated_instruction(vcpu);
59708670
SY		 5792 return 1;
5793}
5794
87c00572
GS		 5795static int handle_mwait(struct kvm_vcpu *vcpu)
5796{
5797 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
5798 return handle_nop(vcpu);
5799}
5800
5801static int handle_monitor(struct kvm_vcpu *vcpu)
5802{
5803 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
5804 return handle_nop(vcpu);
5805}
5806
ff2f6fe9
NHE		 5807/*
5808 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
5809 * We could reuse a single VMCS for all the L2 guests, but we also want the
5810 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
5811 * allows keeping them loaded on the processor, and in the future will allow
5812 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
5813 * every entry if they never change.
5814 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
5815 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
5816 *
5817 * The following functions allocate and free a vmcs02 in this pool.
5818 */
5819
5820/* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
5821static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
5822{
5823 struct vmcs02_list *item;
5824 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5825 if (item->vmptr == vmx->nested.current_vmptr) {
5826 list_move(&item->list, &vmx->nested.vmcs02_pool);
5827 return &item->vmcs02;
5828 }
5829
5830 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
5831 /* Recycle the least recently used VMCS. */
5832 item = list_entry(vmx->nested.vmcs02_pool.prev,
5833 struct vmcs02_list, list);
5834 item->vmptr = vmx->nested.current_vmptr;
5835 list_move(&item->list, &vmx->nested.vmcs02_pool);
5836 return &item->vmcs02;
5837 }
5838
5839 /* Create a new VMCS */
0fa24ce3 5840 item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
ff2f6fe9
NHE		 5841 if (!item)
5842 return NULL;
5843 item->vmcs02.vmcs = alloc_vmcs();
5844 if (!item->vmcs02.vmcs) {
5845 kfree(item);
5846 return NULL;
5847 }
5848 loaded_vmcs_init(&item->vmcs02);
5849 item->vmptr = vmx->nested.current_vmptr;
5850 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
5851 vmx->nested.vmcs02_num++;
5852 return &item->vmcs02;
5853}
5854
5855/* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
5856static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
5857{
5858 struct vmcs02_list *item;
5859 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5860 if (item->vmptr == vmptr) {
5861 free_loaded_vmcs(&item->vmcs02);
5862 list_del(&item->list);
5863 kfree(item);
5864 vmx->nested.vmcs02_num--;
5865 return;
5866 }
5867}
5868
5869/*
5870 * Free all VMCSs saved for this vcpu, except the one pointed by
4fa7734c
PB		 5871 * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
5872 * must be &vmx->vmcs01.
ff2f6fe9
NHE		 5873 */
5874static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
5875{
5876 struct vmcs02_list *item, *n;
4fa7734c
PB		 5877
5878 WARN_ON(vmx->loaded_vmcs != &vmx->vmcs01);
ff2f6fe9 5879 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
4fa7734c
PB		 5880 /*
5881 * Something will leak if the above WARN triggers. Better than
5882 * a use-after-free.
5883 */
5884 if (vmx->loaded_vmcs == &item->vmcs02)
5885 continue;
5886
5887 free_loaded_vmcs(&item->vmcs02);
ff2f6fe9
NHE		 5888 list_del(&item->list);
5889 kfree(item);
4fa7734c 5890 vmx->nested.vmcs02_num--;
ff2f6fe9 5891 }
ff2f6fe9
NHE		 5892}
5893
0658fbaa
ACL		 5894/*
5895 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5896 * set the success or error code of an emulated VMX instruction, as specified
5897 * by Vol 2B, VMX Instruction Reference, "Conventions".
5898 */
5899static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
5900{
5901 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
5902 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5903 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
5904}
5905
5906static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
5907{
5908 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5909 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
5910 X86_EFLAGS_SF | X86_EFLAGS_OF))
5911 | X86_EFLAGS_CF);
5912}
5913
145c28dd 5914static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
0658fbaa
ACL		 5915 u32 vm_instruction_error)
5916{
5917 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
5918 /*
5919 * failValid writes the error number to the current VMCS, which
5920 * can't be done there isn't a current VMCS.
5921 */
5922 nested_vmx_failInvalid(vcpu);
5923 return;
5924 }
5925 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5926 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5927 X86_EFLAGS_SF | X86_EFLAGS_OF))
5928 | X86_EFLAGS_ZF);
5929 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
5930 /*
5931 * We don't need to force a shadow sync because
5932 * VM_INSTRUCTION_ERROR is not shadowed
5933 */
5934}
145c28dd 5935
f4124500
JK		 5936static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
5937{
5938 struct vcpu_vmx *vmx =
5939 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
5940
5941 vmx->nested.preemption_timer_expired = true;
5942 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
5943 kvm_vcpu_kick(&vmx->vcpu);
5944
5945 return HRTIMER_NORESTART;
5946}
5947
19677e32
BD		 5948/*
5949 * Decode the memory-address operand of a vmx instruction, as recorded on an
5950 * exit caused by such an instruction (run by a guest hypervisor).
5951 * On success, returns 0. When the operand is invalid, returns 1 and throws
5952 * #UD or #GP.
5953 */
5954static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
5955 unsigned long exit_qualification,
5956 u32 vmx_instruction_info, gva_t *ret)
5957{
5958 /*
5959 * According to Vol. 3B, "Information for VM Exits Due to Instruction
5960 * Execution", on an exit, vmx_instruction_info holds most of the
5961 * addressing components of the operand. Only the displacement part
5962 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5963 * For how an actual address is calculated from all these components,
5964 * refer to Vol. 1, "Operand Addressing".
5965 */
5966 int scaling = vmx_instruction_info & 3;
5967 int addr_size = (vmx_instruction_info >> 7) & 7;
5968 bool is_reg = vmx_instruction_info & (1u << 10);
5969 int seg_reg = (vmx_instruction_info >> 15) & 7;
5970 int index_reg = (vmx_instruction_info >> 18) & 0xf;
5971 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
5972 int base_reg = (vmx_instruction_info >> 23) & 0xf;
5973 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
5974
5975 if (is_reg) {
5976 kvm_queue_exception(vcpu, UD_VECTOR);
5977 return 1;
5978 }
5979
5980 /* Addr = segment_base + offset */
5981 /* offset = base + [index * scale] + displacement */
5982 *ret = vmx_get_segment_base(vcpu, seg_reg);
5983 if (base_is_valid)
5984 *ret += kvm_register_read(vcpu, base_reg);
5985 if (index_is_valid)
5986 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
5987 *ret += exit_qualification; /* holds the displacement */
5988
5989 if (addr_size == 1) /* 32 bit */
5990 *ret &= 0xffffffff;
5991
5992 /*
5993 * TODO: throw #GP (and return 1) in various cases that the VM*
5994 * instructions require it - e.g., offset beyond segment limit,
5995 * unusable or unreadable/unwritable segment, non-canonical 64-bit
5996 * address, and so on. Currently these are not checked.
5997 */
5998 return 0;
5999}
6000
3573e22c
BD		 6001/*
6002 * This function performs the various checks including
6003 * - if it's 4KB aligned
6004 * - No bits beyond the physical address width are set
6005 * - Returns 0 on success or else 1
4291b588 6006 * (Intel SDM Section 30.3)
3573e22c 6007 */
4291b588
BD		 6008static int nested_vmx_check_vmptr(struct kvm_vcpu *vcpu, int exit_reason,
6009 gpa_t *vmpointer)
3573e22c
BD		 6010{
6011 gva_t gva;
6012 gpa_t vmptr;
6013 struct x86_exception e;
6014 struct page *page;
6015 struct vcpu_vmx *vmx = to_vmx(vcpu);
6016 int maxphyaddr = cpuid_maxphyaddr(vcpu);
6017
6018 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6019 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
6020 return 1;
6021
6022 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6023 sizeof(vmptr), &e)) {
6024 kvm_inject_page_fault(vcpu, &e);
6025 return 1;
6026 }
6027
6028 switch (exit_reason) {
6029 case EXIT_REASON_VMON:
6030 /*
6031 * SDM 3: 24.11.5
6032 * The first 4 bytes of VMXON region contain the supported
6033 * VMCS revision identifier
6034 *
6035 * Note - IA32_VMX_BASIC[48] will never be 1
6036 * for the nested case;
6037 * which replaces physical address width with 32
6038 *
6039 */
bc39c4db 6040 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
3573e22c
BD		 6041 nested_vmx_failInvalid(vcpu);
6042 skip_emulated_instruction(vcpu);
6043 return 1;
6044 }
6045
6046 page = nested_get_page(vcpu, vmptr);
6047 if (page == NULL ||
6048 *(u32 *)kmap(page) != VMCS12_REVISION) {
6049 nested_vmx_failInvalid(vcpu);
6050 kunmap(page);
6051 skip_emulated_instruction(vcpu);
6052 return 1;
6053 }
6054 kunmap(page);
6055 vmx->nested.vmxon_ptr = vmptr;
6056 break;
4291b588 6057 case EXIT_REASON_VMCLEAR:
bc39c4db 6058 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
4291b588
BD		 6059 nested_vmx_failValid(vcpu,
6060 VMXERR_VMCLEAR_INVALID_ADDRESS);
6061 skip_emulated_instruction(vcpu);
6062 return 1;
6063 }
6064
6065 if (vmptr == vmx->nested.vmxon_ptr) {
6066 nested_vmx_failValid(vcpu,
6067 VMXERR_VMCLEAR_VMXON_POINTER);
6068 skip_emulated_instruction(vcpu);
6069 return 1;
6070 }
6071 break;
6072 case EXIT_REASON_VMPTRLD:
bc39c4db 6073 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
4291b588
BD		 6074 nested_vmx_failValid(vcpu,
6075 VMXERR_VMPTRLD_INVALID_ADDRESS);
6076 skip_emulated_instruction(vcpu);
6077 return 1;
6078 }
3573e22c 6079
4291b588
BD		 6080 if (vmptr == vmx->nested.vmxon_ptr) {
6081 nested_vmx_failValid(vcpu,
6082 VMXERR_VMCLEAR_VMXON_POINTER);
6083 skip_emulated_instruction(vcpu);
6084 return 1;
6085 }
6086 break;
3573e22c
BD		 6087 default:
6088 return 1; /* shouldn't happen */
6089 }
6090
4291b588
BD		 6091 if (vmpointer)
6092 *vmpointer = vmptr;
3573e22c
BD		 6093 return 0;
6094}
6095
ec378aee
NHE		 6096/*
6097 * Emulate the VMXON instruction.
6098 * Currently, we just remember that VMX is active, and do not save or even
6099 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
6100 * do not currently need to store anything in that guest-allocated memory
6101 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
6102 * argument is different from the VMXON pointer (which the spec says they do).
6103 */
6104static int handle_vmon(struct kvm_vcpu *vcpu)
6105{
6106 struct kvm_segment cs;
6107 struct vcpu_vmx *vmx = to_vmx(vcpu);
8de48833 6108 struct vmcs *shadow_vmcs;
b3897a49
NHE		 6109 const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
6110 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
ec378aee
NHE		 6111
6112 /* The Intel VMX Instruction Reference lists a bunch of bits that
6113 * are prerequisite to running VMXON, most notably cr4.VMXE must be
6114 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
6115 * Otherwise, we should fail with #UD. We test these now:
6116 */
6117 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
6118 !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
6119 (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
6120 kvm_queue_exception(vcpu, UD_VECTOR);
6121 return 1;
6122 }
6123
6124 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6125 if (is_long_mode(vcpu) && !cs.l) {
6126 kvm_queue_exception(vcpu, UD_VECTOR);
6127 return 1;
6128 }
6129
6130 if (vmx_get_cpl(vcpu)) {
6131 kvm_inject_gp(vcpu, 0);
6132 return 1;
6133 }
3573e22c 6134
4291b588 6135 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMON, NULL))
3573e22c
BD		 6136 return 1;
6137
145c28dd
AG		 6138 if (vmx->nested.vmxon) {
6139 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
6140 skip_emulated_instruction(vcpu);
6141 return 1;
6142 }
b3897a49
NHE		 6143
6144 if ((vmx->nested.msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
6145 != VMXON_NEEDED_FEATURES) {
6146 kvm_inject_gp(vcpu, 0);
6147 return 1;
6148 }
6149
8de48833
AG		 6150 if (enable_shadow_vmcs) {
6151 shadow_vmcs = alloc_vmcs();
6152 if (!shadow_vmcs)
6153 return -ENOMEM;
6154 /* mark vmcs as shadow */
6155 shadow_vmcs->revision_id |= (1u << 31);
6156 /* init shadow vmcs */
6157 vmcs_clear(shadow_vmcs);
6158 vmx->nested.current_shadow_vmcs = shadow_vmcs;
6159 }
ec378aee 6160
ff2f6fe9
NHE		 6161 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
6162 vmx->nested.vmcs02_num = 0;
6163
f4124500
JK		 6164 hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
6165 HRTIMER_MODE_REL);
6166 vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
6167
ec378aee
NHE		 6168 vmx->nested.vmxon = true;
6169
6170 skip_emulated_instruction(vcpu);
a25eb114 6171 nested_vmx_succeed(vcpu);
ec378aee
NHE		 6172 return 1;
6173}
6174
6175/*
6176 * Intel's VMX Instruction Reference specifies a common set of prerequisites
6177 * for running VMX instructions (except VMXON, whose prerequisites are
6178 * slightly different). It also specifies what exception to inject otherwise.
6179 */
6180static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
6181{
6182 struct kvm_segment cs;
6183 struct vcpu_vmx *vmx = to_vmx(vcpu);
6184
6185 if (!vmx->nested.vmxon) {
6186 kvm_queue_exception(vcpu, UD_VECTOR);
6187 return 0;
6188 }
6189
6190 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6191 if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
6192 (is_long_mode(vcpu) && !cs.l)) {
6193 kvm_queue_exception(vcpu, UD_VECTOR);
6194 return 0;
6195 }
6196
6197 if (vmx_get_cpl(vcpu)) {
6198 kvm_inject_gp(vcpu, 0);
6199 return 0;
6200 }
6201
6202 return 1;
6203}
6204
e7953d7f
AG		 6205static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
6206{
8a1b9dd0 6207 u32 exec_control;
9a2a05b9
PB		 6208 if (vmx->nested.current_vmptr == -1ull)
6209 return;
6210
6211 /* current_vmptr and current_vmcs12 are always set/reset together */
6212 if (WARN_ON(vmx->nested.current_vmcs12 == NULL))
6213 return;
6214
012f83cb 6215 if (enable_shadow_vmcs) {
9a2a05b9
PB		 6216 /* copy to memory all shadowed fields in case
6217 they were modified */
6218 copy_shadow_to_vmcs12(vmx);
6219 vmx->nested.sync_shadow_vmcs = false;
6220 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6221 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
6222 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6223 vmcs_write64(VMCS_LINK_POINTER, -1ull);
012f83cb 6224 }
e7953d7f
AG		 6225 kunmap(vmx->nested.current_vmcs12_page);
6226 nested_release_page(vmx->nested.current_vmcs12_page);
9a2a05b9
PB		 6227 vmx->nested.current_vmptr = -1ull;
6228 vmx->nested.current_vmcs12 = NULL;
e7953d7f
AG		 6229}
6230
ec378aee
NHE		 6231/*
6232 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
6233 * just stops using VMX.
6234 */
6235static void free_nested(struct vcpu_vmx *vmx)
6236{
6237 if (!vmx->nested.vmxon)
6238 return;
9a2a05b9 6239
ec378aee 6240 vmx->nested.vmxon = false;
9a2a05b9 6241 nested_release_vmcs12(vmx);
e7953d7f
AG		 6242 if (enable_shadow_vmcs)
6243 free_vmcs(vmx->nested.current_shadow_vmcs);
fe3ef05c
NHE		 6244 /* Unpin physical memory we referred to in current vmcs02 */
6245 if (vmx->nested.apic_access_page) {
6246 nested_release_page(vmx->nested.apic_access_page);
6247 vmx->nested.apic_access_page = 0;
6248 }
ff2f6fe9
NHE		 6249
6250 nested_free_all_saved_vmcss(vmx);
ec378aee
NHE		 6251}
6252
6253/* Emulate the VMXOFF instruction */
6254static int handle_vmoff(struct kvm_vcpu *vcpu)
6255{
6256 if (!nested_vmx_check_permission(vcpu))
6257 return 1;
6258 free_nested(to_vmx(vcpu));
6259 skip_emulated_instruction(vcpu);
a25eb114 6260 nested_vmx_succeed(vcpu);
ec378aee
NHE		 6261 return 1;
6262}
6263
27d6c865
NHE		 6264/* Emulate the VMCLEAR instruction */
6265static int handle_vmclear(struct kvm_vcpu *vcpu)
6266{
6267 struct vcpu_vmx *vmx = to_vmx(vcpu);
27d6c865
NHE		 6268 gpa_t vmptr;
6269 struct vmcs12 *vmcs12;
6270 struct page *page;
27d6c865
NHE		 6271
6272 if (!nested_vmx_check_permission(vcpu))
6273 return 1;
6274
4291b588 6275 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMCLEAR, &vmptr))
27d6c865 6276 return 1;
27d6c865 6277
9a2a05b9 6278 if (vmptr == vmx->nested.current_vmptr)
e7953d7f 6279 nested_release_vmcs12(vmx);
27d6c865
NHE		 6280
6281 page = nested_get_page(vcpu, vmptr);
6282 if (page == NULL) {
6283 /*
6284 * For accurate processor emulation, VMCLEAR beyond available
6285 * physical memory should do nothing at all. However, it is
6286 * possible that a nested vmx bug, not a guest hypervisor bug,
6287 * resulted in this case, so let's shut down before doing any
6288 * more damage:
6289 */
6290 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6291 return 1;
6292 }
6293 vmcs12 = kmap(page);
6294 vmcs12->launch_state = 0;
6295 kunmap(page);
6296 nested_release_page(page);
6297
6298 nested_free_vmcs02(vmx, vmptr);
6299
6300 skip_emulated_instruction(vcpu);
6301 nested_vmx_succeed(vcpu);
6302 return 1;
6303}
6304
cd232ad0
NHE		 6305static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
6306
6307/* Emulate the VMLAUNCH instruction */
6308static int handle_vmlaunch(struct kvm_vcpu *vcpu)
6309{
6310 return nested_vmx_run(vcpu, true);
6311}
6312
6313/* Emulate the VMRESUME instruction */
6314static int handle_vmresume(struct kvm_vcpu *vcpu)
6315{
6316
6317 return nested_vmx_run(vcpu, false);
6318}
6319
49f705c5
NHE		 6320enum vmcs_field_type {
6321 VMCS_FIELD_TYPE_U16 = 0,
6322 VMCS_FIELD_TYPE_U64 = 1,
6323 VMCS_FIELD_TYPE_U32 = 2,
6324 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
6325};
6326
6327static inline int vmcs_field_type(unsigned long field)
6328{
6329 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
6330 return VMCS_FIELD_TYPE_U32;
6331 return (field >> 13) & 0x3 ;
6332}
6333
6334static inline int vmcs_field_readonly(unsigned long field)
6335{
6336 return (((field >> 10) & 0x3) == 1);
6337}
6338
6339/*
6340 * Read a vmcs12 field. Since these can have varying lengths and we return
6341 * one type, we chose the biggest type (u64) and zero-extend the return value
6342 * to that size. Note that the caller, handle_vmread, might need to use only
6343 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
6344 * 64-bit fields are to be returned).
6345 */
6346static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
6347 unsigned long field, u64 *ret)
6348{
6349 short offset = vmcs_field_to_offset(field);
6350 char *p;
6351
6352 if (offset < 0)
6353 return 0;
6354
6355 p = ((char *)(get_vmcs12(vcpu))) + offset;
6356
6357 switch (vmcs_field_type(field)) {
6358 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6359 *ret = *((natural_width *)p);
6360 return 1;
6361 case VMCS_FIELD_TYPE_U16:
6362 *ret = *((u16 *)p);
6363 return 1;
6364 case VMCS_FIELD_TYPE_U32:
6365 *ret = *((u32 *)p);
6366 return 1;
6367 case VMCS_FIELD_TYPE_U64:
6368 *ret = *((u64 *)p);
6369 return 1;
6370 default:
6371 return 0; /* can never happen. */
6372 }
6373}
6374
20b97fea
AG		 6375
6376static inline bool vmcs12_write_any(struct kvm_vcpu *vcpu,
6377 unsigned long field, u64 field_value){
6378 short offset = vmcs_field_to_offset(field);
6379 char *p = ((char *) get_vmcs12(vcpu)) + offset;
6380 if (offset < 0)
6381 return false;
6382
6383 switch (vmcs_field_type(field)) {
6384 case VMCS_FIELD_TYPE_U16:
6385 *(u16 *)p = field_value;
6386 return true;
6387 case VMCS_FIELD_TYPE_U32:
6388 *(u32 *)p = field_value;
6389 return true;
6390 case VMCS_FIELD_TYPE_U64:
6391 *(u64 *)p = field_value;
6392 return true;
6393 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6394 *(natural_width *)p = field_value;
6395 return true;
6396 default:
6397 return false; /* can never happen. */
6398 }
6399
6400}
6401
16f5b903
AG		 6402static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
6403{
6404 int i;
6405 unsigned long field;
6406 u64 field_value;
6407 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
c2bae893
MK		 6408 const unsigned long *fields = shadow_read_write_fields;
6409 const int num_fields = max_shadow_read_write_fields;
16f5b903
AG		 6410
6411 vmcs_load(shadow_vmcs);
6412
6413 for (i = 0; i < num_fields; i++) {
6414 field = fields[i];
6415 switch (vmcs_field_type(field)) {
6416 case VMCS_FIELD_TYPE_U16:
6417 field_value = vmcs_read16(field);
6418 break;
6419 case VMCS_FIELD_TYPE_U32:
6420 field_value = vmcs_read32(field);
6421 break;
6422 case VMCS_FIELD_TYPE_U64:
6423 field_value = vmcs_read64(field);
6424 break;
6425 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6426 field_value = vmcs_readl(field);
6427 break;
6428 }
6429 vmcs12_write_any(&vmx->vcpu, field, field_value);
6430 }
6431
6432 vmcs_clear(shadow_vmcs);
6433 vmcs_load(vmx->loaded_vmcs->vmcs);
6434}
6435
c3114420
AG		 6436static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
6437{
c2bae893
MK		 6438 const unsigned long *fields[] = {
6439 shadow_read_write_fields,
6440 shadow_read_only_fields
c3114420 6441 };
c2bae893 6442 const int max_fields[] = {
c3114420
AG		 6443 max_shadow_read_write_fields,
6444 max_shadow_read_only_fields
6445 };
6446 int i, q;
6447 unsigned long field;
6448 u64 field_value = 0;
6449 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
6450
6451 vmcs_load(shadow_vmcs);
6452
c2bae893 6453 for (q = 0; q < ARRAY_SIZE(fields); q++) {
c3114420
AG		 6454 for (i = 0; i < max_fields[q]; i++) {
6455 field = fields[q][i];
6456 vmcs12_read_any(&vmx->vcpu, field, &field_value);
6457
6458 switch (vmcs_field_type(field)) {
6459 case VMCS_FIELD_TYPE_U16:
6460 vmcs_write16(field, (u16)field_value);
6461 break;
6462 case VMCS_FIELD_TYPE_U32:
6463 vmcs_write32(field, (u32)field_value);
6464 break;
6465 case VMCS_FIELD_TYPE_U64:
6466 vmcs_write64(field, (u64)field_value);
6467 break;
6468 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6469 vmcs_writel(field, (long)field_value);
6470 break;
6471 }
6472 }
6473 }
6474
6475 vmcs_clear(shadow_vmcs);
6476 vmcs_load(vmx->loaded_vmcs->vmcs);
6477}
6478
49f705c5
NHE		 6479/*
6480 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
6481 * used before) all generate the same failure when it is missing.
6482 */
6483static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
6484{
6485 struct vcpu_vmx *vmx = to_vmx(vcpu);
6486 if (vmx->nested.current_vmptr == -1ull) {
6487 nested_vmx_failInvalid(vcpu);
6488 skip_emulated_instruction(vcpu);
6489 return 0;
6490 }
6491 return 1;
6492}
6493
6494static int handle_vmread(struct kvm_vcpu *vcpu)
6495{
6496 unsigned long field;
6497 u64 field_value;
6498 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6499 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6500 gva_t gva = 0;
6501
6502 if (!nested_vmx_check_permission(vcpu) ||
6503 !nested_vmx_check_vmcs12(vcpu))
6504 return 1;
6505
6506 /* Decode instruction info and find the field to read */
27e6fb5d 6507 field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
49f705c5
NHE		 6508 /* Read the field, zero-extended to a u64 field_value */
6509 if (!vmcs12_read_any(vcpu, field, &field_value)) {
6510 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6511 skip_emulated_instruction(vcpu);
6512 return 1;
6513 }
6514 /*
6515 * Now copy part of this value to register or memory, as requested.
6516 * Note that the number of bits actually copied is 32 or 64 depending
6517 * on the guest's mode (32 or 64 bit), not on the given field's length.
6518 */
6519 if (vmx_instruction_info & (1u << 10)) {
27e6fb5d 6520 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
49f705c5
NHE		 6521 field_value);
6522 } else {
6523 if (get_vmx_mem_address(vcpu, exit_qualification,
6524 vmx_instruction_info, &gva))
6525 return 1;
6526 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
6527 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
6528 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
6529 }
6530
6531 nested_vmx_succeed(vcpu);
6532 skip_emulated_instruction(vcpu);
6533 return 1;
6534}
6535
6536
6537static int handle_vmwrite(struct kvm_vcpu *vcpu)
6538{
6539 unsigned long field;
6540 gva_t gva;
6541 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6542 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
49f705c5
NHE		 6543 /* The value to write might be 32 or 64 bits, depending on L1's long
6544 * mode, and eventually we need to write that into a field of several
6545 * possible lengths. The code below first zero-extends the value to 64
6546 * bit (field_value), and then copies only the approriate number of
6547 * bits into the vmcs12 field.
6548 */
6549 u64 field_value = 0;
6550 struct x86_exception e;
6551
6552 if (!nested_vmx_check_permission(vcpu) ||
6553 !nested_vmx_check_vmcs12(vcpu))
6554 return 1;
6555
6556 if (vmx_instruction_info & (1u << 10))
27e6fb5d 6557 field_value = kvm_register_readl(vcpu,
49f705c5
NHE		 6558 (((vmx_instruction_info) >> 3) & 0xf));
6559 else {
6560 if (get_vmx_mem_address(vcpu, exit_qualification,
6561 vmx_instruction_info, &gva))
6562 return 1;
6563 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
27e6fb5d 6564 &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
49f705c5
NHE		 6565 kvm_inject_page_fault(vcpu, &e);
6566 return 1;
6567 }
6568 }
6569
6570
27e6fb5d 6571 field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
49f705c5
NHE		 6572 if (vmcs_field_readonly(field)) {
6573 nested_vmx_failValid(vcpu,
6574 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
6575 skip_emulated_instruction(vcpu);
6576 return 1;
6577 }
6578
20b97fea 6579 if (!vmcs12_write_any(vcpu, field, field_value)) {
49f705c5
NHE		 6580 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6581 skip_emulated_instruction(vcpu);
6582 return 1;
6583 }
6584
6585 nested_vmx_succeed(vcpu);
6586 skip_emulated_instruction(vcpu);
6587 return 1;
6588}
6589
63846663
NHE		 6590/* Emulate the VMPTRLD instruction */
6591static int handle_vmptrld(struct kvm_vcpu *vcpu)
6592{
6593 struct vcpu_vmx *vmx = to_vmx(vcpu);
63846663 6594 gpa_t vmptr;
8a1b9dd0 6595 u32 exec_control;
63846663
NHE		 6596
6597 if (!nested_vmx_check_permission(vcpu))
6598 return 1;
6599
4291b588 6600 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMPTRLD, &vmptr))
63846663 6601 return 1;
63846663
NHE		 6602
6603 if (vmx->nested.current_vmptr != vmptr) {
6604 struct vmcs12 *new_vmcs12;
6605 struct page *page;
6606 page = nested_get_page(vcpu, vmptr);
6607 if (page == NULL) {
6608 nested_vmx_failInvalid(vcpu);
6609 skip_emulated_instruction(vcpu);
6610 return 1;
6611 }
6612 new_vmcs12 = kmap(page);
6613 if (new_vmcs12->revision_id != VMCS12_REVISION) {
6614 kunmap(page);
6615 nested_release_page_clean(page);
6616 nested_vmx_failValid(vcpu,
6617 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
6618 skip_emulated_instruction(vcpu);
6619 return 1;
6620 }
63846663 6621
9a2a05b9 6622 nested_release_vmcs12(vmx);
63846663
NHE		 6623 vmx->nested.current_vmptr = vmptr;
6624 vmx->nested.current_vmcs12 = new_vmcs12;
6625 vmx->nested.current_vmcs12_page = page;
012f83cb 6626 if (enable_shadow_vmcs) {
8a1b9dd0
AG		 6627 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6628 exec_control |= SECONDARY_EXEC_SHADOW_VMCS;
6629 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6630 vmcs_write64(VMCS_LINK_POINTER,
6631 __pa(vmx->nested.current_shadow_vmcs));
012f83cb
AG		 6632 vmx->nested.sync_shadow_vmcs = true;
6633 }
63846663
NHE		 6634 }
6635
6636 nested_vmx_succeed(vcpu);
6637 skip_emulated_instruction(vcpu);
6638 return 1;
6639}
6640
6a4d7550
NHE		 6641/* Emulate the VMPTRST instruction */
6642static int handle_vmptrst(struct kvm_vcpu *vcpu)
6643{
6644 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6645 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6646 gva_t vmcs_gva;
6647 struct x86_exception e;
6648
6649 if (!nested_vmx_check_permission(vcpu))
6650 return 1;
6651
6652 if (get_vmx_mem_address(vcpu, exit_qualification,
6653 vmx_instruction_info, &vmcs_gva))
6654 return 1;
6655 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
6656 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
6657 (void *)&to_vmx(vcpu)->nested.current_vmptr,
6658 sizeof(u64), &e)) {
6659 kvm_inject_page_fault(vcpu, &e);
6660 return 1;
6661 }
6662 nested_vmx_succeed(vcpu);
6663 skip_emulated_instruction(vcpu);
6664 return 1;
6665}
6666
bfd0a56b
NHE		 6667/* Emulate the INVEPT instruction */
6668static int handle_invept(struct kvm_vcpu *vcpu)
6669{
6670 u32 vmx_instruction_info, types;
6671 unsigned long type;
6672 gva_t gva;
6673 struct x86_exception e;
6674 struct {
6675 u64 eptp, gpa;
6676 } operand;
bfd0a56b
NHE		 6677
6678 if (!(nested_vmx_secondary_ctls_high & SECONDARY_EXEC_ENABLE_EPT) ||
6679 !(nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
6680 kvm_queue_exception(vcpu, UD_VECTOR);
6681 return 1;
6682 }
6683
6684 if (!nested_vmx_check_permission(vcpu))
6685 return 1;
6686
6687 if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
6688 kvm_queue_exception(vcpu, UD_VECTOR);
6689 return 1;
6690 }
6691
6692 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
27e6fb5d 6693 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
bfd0a56b
NHE		 6694
6695 types = (nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
6696
6697 if (!(types & (1UL << type))) {
6698 nested_vmx_failValid(vcpu,
6699 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
6700 return 1;
6701 }
6702
6703 /* According to the Intel VMX instruction reference, the memory
6704 * operand is read even if it isn't needed (e.g., for type==global)
6705 */
6706 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6707 vmx_instruction_info, &gva))
6708 return 1;
6709 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
6710 sizeof(operand), &e)) {
6711 kvm_inject_page_fault(vcpu, &e);
6712 return 1;
6713 }
6714
6715 switch (type) {
bfd0a56b
NHE		 6716 case VMX_EPT_EXTENT_GLOBAL:
6717 kvm_mmu_sync_roots(vcpu);
6718 kvm_mmu_flush_tlb(vcpu);
6719 nested_vmx_succeed(vcpu);
6720 break;
6721 default:
4b855078 6722 /* Trap single context invalidation invept calls */
bfd0a56b
NHE		 6723 BUG_ON(1);
6724 break;
6725 }
6726
6727 skip_emulated_instruction(vcpu);
6728 return 1;
6729}
6730
6aa8b732
AK		 6731/*
6732 * The exit handlers return 1 if the exit was handled fully and guest execution
6733 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
6734 * to be done to userspace and return 0.
6735 */
772e0318 6736static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK		 6737 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
6738 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 6739 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 6740 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 6741 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 6742 [EXIT_REASON_CR_ACCESS] = handle_cr,
6743 [EXIT_REASON_DR_ACCESS] = handle_dr,
6744 [EXIT_REASON_CPUID] = handle_cpuid,
6745 [EXIT_REASON_MSR_READ] = handle_rdmsr,
6746 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
6747 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
6748 [EXIT_REASON_HLT] = handle_halt,
ec25d5e6 6749 [EXIT_REASON_INVD] = handle_invd,
a7052897 6750 [EXIT_REASON_INVLPG] = handle_invlpg,
fee84b07 6751 [EXIT_REASON_RDPMC] = handle_rdpmc,
c21415e8 6752 [EXIT_REASON_VMCALL] = handle_vmcall,
27d6c865 6753 [EXIT_REASON_VMCLEAR] = handle_vmclear,
cd232ad0 6754 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
63846663 6755 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
6a4d7550 6756 [EXIT_REASON_VMPTRST] = handle_vmptrst,
49f705c5 6757 [EXIT_REASON_VMREAD] = handle_vmread,
cd232ad0 6758 [EXIT_REASON_VMRESUME] = handle_vmresume,
49f705c5 6759 [EXIT_REASON_VMWRITE] = handle_vmwrite,
ec378aee
NHE		 6760 [EXIT_REASON_VMOFF] = handle_vmoff,
6761 [EXIT_REASON_VMON] = handle_vmon,
f78e0e2e
SY		 6762 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
6763 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
83d4c286 6764 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
c7c9c56c 6765 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
e5edaa01 6766 [EXIT_REASON_WBINVD] = handle_wbinvd,
2acf923e 6767 [EXIT_REASON_XSETBV] = handle_xsetbv,
37817f29 6768 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 6769 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT		 6770 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
6771 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 6772 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
87c00572
GS		 6773 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_mwait,
6774 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_monitor,
bfd0a56b 6775 [EXIT_REASON_INVEPT] = handle_invept,
6aa8b732
AK		 6776};
6777
6778static const int kvm_vmx_max_exit_handlers =
50a3485c 6779 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732 6780
908a7bdd
JK		 6781static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
6782 struct vmcs12 *vmcs12)
6783{
6784 unsigned long exit_qualification;
6785 gpa_t bitmap, last_bitmap;
6786 unsigned int port;
6787 int size;
6788 u8 b;
6789
908a7bdd 6790 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
2f0a6397 6791 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
908a7bdd
JK		 6792
6793 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6794
6795 port = exit_qualification >> 16;
6796 size = (exit_qualification & 7) + 1;
6797
6798 last_bitmap = (gpa_t)-1;
6799 b = -1;
6800
6801 while (size > 0) {
6802 if (port < 0x8000)
6803 bitmap = vmcs12->io_bitmap_a;
6804 else if (port < 0x10000)
6805 bitmap = vmcs12->io_bitmap_b;
6806 else
6807 return 1;
6808 bitmap += (port & 0x7fff) / 8;
6809
6810 if (last_bitmap != bitmap)
6811 if (kvm_read_guest(vcpu->kvm, bitmap, &b, 1))
6812 return 1;
6813 if (b & (1 << (port & 7)))
6814 return 1;
6815
6816 port++;
6817 size--;
6818 last_bitmap = bitmap;
6819 }
6820
6821 return 0;
6822}
6823
644d711a
NHE		 6824/*
6825 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
6826 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
6827 * disinterest in the current event (read or write a specific MSR) by using an
6828 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
6829 */
6830static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
6831 struct vmcs12 *vmcs12, u32 exit_reason)
6832{
6833 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
6834 gpa_t bitmap;
6835
cbd29cb6 6836 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
644d711a
NHE		 6837 return 1;
6838
6839 /*
6840 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
6841 * for the four combinations of read/write and low/high MSR numbers.
6842 * First we need to figure out which of the four to use:
6843 */
6844 bitmap = vmcs12->msr_bitmap;
6845 if (exit_reason == EXIT_REASON_MSR_WRITE)
6846 bitmap += 2048;
6847 if (msr_index >= 0xc0000000) {
6848 msr_index -= 0xc0000000;
6849 bitmap += 1024;
6850 }
6851
6852 /* Then read the msr_index'th bit from this bitmap: */
6853 if (msr_index < 1024*8) {
6854 unsigned char b;
bd31a7f5
JK		 6855 if (kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1))
6856 return 1;
644d711a
NHE		 6857 return 1 & (b >> (msr_index & 7));
6858 } else
6859 return 1; /* let L1 handle the wrong parameter */
6860}
6861
6862/*
6863 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
6864 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
6865 * intercept (via guest_host_mask etc.) the current event.
6866 */
6867static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
6868 struct vmcs12 *vmcs12)
6869{
6870 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6871 int cr = exit_qualification & 15;
6872 int reg = (exit_qualification >> 8) & 15;
1e32c079 6873 unsigned long val = kvm_register_readl(vcpu, reg);
644d711a
NHE		 6874
6875 switch ((exit_qualification >> 4) & 3) {
6876 case 0: /* mov to cr */
6877 switch (cr) {
6878 case 0:
6879 if (vmcs12->cr0_guest_host_mask &
6880 (val ^ vmcs12->cr0_read_shadow))
6881 return 1;
6882 break;
6883 case 3:
6884 if ((vmcs12->cr3_target_count >= 1 &&
6885 vmcs12->cr3_target_value0 == val) ||
6886 (vmcs12->cr3_target_count >= 2 &&
6887 vmcs12->cr3_target_value1 == val) ||
6888 (vmcs12->cr3_target_count >= 3 &&
6889 vmcs12->cr3_target_value2 == val) ||
6890 (vmcs12->cr3_target_count >= 4 &&
6891 vmcs12->cr3_target_value3 == val))
6892 return 0;
6893 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
6894 return 1;
6895 break;
6896 case 4:
6897 if (vmcs12->cr4_guest_host_mask &
6898 (vmcs12->cr4_read_shadow ^ val))
6899 return 1;
6900 break;
6901 case 8:
6902 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
6903 return 1;
6904 break;
6905 }
6906 break;
6907 case 2: /* clts */
6908 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
6909 (vmcs12->cr0_read_shadow & X86_CR0_TS))
6910 return 1;
6911 break;
6912 case 1: /* mov from cr */
6913 switch (cr) {
6914 case 3:
6915 if (vmcs12->cpu_based_vm_exec_control &
6916 CPU_BASED_CR3_STORE_EXITING)
6917 return 1;
6918 break;
6919 case 8:
6920 if (vmcs12->cpu_based_vm_exec_control &
6921 CPU_BASED_CR8_STORE_EXITING)
6922 return 1;
6923 break;
6924 }
6925 break;
6926 case 3: /* lmsw */
6927 /*
6928 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
6929 * cr0. Other attempted changes are ignored, with no exit.
6930 */
6931 if (vmcs12->cr0_guest_host_mask & 0xe &
6932 (val ^ vmcs12->cr0_read_shadow))
6933 return 1;
6934 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
6935 !(vmcs12->cr0_read_shadow & 0x1) &&
6936 (val & 0x1))
6937 return 1;
6938 break;
6939 }
6940 return 0;
6941}
6942
6943/*
6944 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
6945 * should handle it ourselves in L0 (and then continue L2). Only call this
6946 * when in is_guest_mode (L2).
6947 */
6948static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
6949{
644d711a
NHE		 6950 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6951 struct vcpu_vmx *vmx = to_vmx(vcpu);
6952 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
957c897e 6953 u32 exit_reason = vmx->exit_reason;
644d711a 6954
542060ea
JK		 6955 trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
6956 vmcs_readl(EXIT_QUALIFICATION),
6957 vmx->idt_vectoring_info,
6958 intr_info,
6959 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
6960 KVM_ISA_VMX);
6961
644d711a
NHE		 6962 if (vmx->nested.nested_run_pending)
6963 return 0;
6964
6965 if (unlikely(vmx->fail)) {
bd80158a
JK		 6966 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
6967 vmcs_read32(VM_INSTRUCTION_ERROR));
644d711a
NHE		 6968 return 1;
6969 }
6970
6971 switch (exit_reason) {
6972 case EXIT_REASON_EXCEPTION_NMI:
6973 if (!is_exception(intr_info))
6974 return 0;
6975 else if (is_page_fault(intr_info))
6976 return enable_ept;
e504c909 6977 else if (is_no_device(intr_info) &&
ccf9844e 6978 !(vmcs12->guest_cr0 & X86_CR0_TS))
e504c909 6979 return 0;
644d711a
NHE		 6980 return vmcs12->exception_bitmap &
6981 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
6982 case EXIT_REASON_EXTERNAL_INTERRUPT:
6983 return 0;
6984 case EXIT_REASON_TRIPLE_FAULT:
6985 return 1;
6986 case EXIT_REASON_PENDING_INTERRUPT:
3b656cf7 6987 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
644d711a 6988 case EXIT_REASON_NMI_WINDOW:
3b656cf7 6989 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
644d711a
NHE		 6990 case EXIT_REASON_TASK_SWITCH:
6991 return 1;
6992 case EXIT_REASON_CPUID:
6993 return 1;
6994 case EXIT_REASON_HLT:
6995 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
6996 case EXIT_REASON_INVD:
6997 return 1;
6998 case EXIT_REASON_INVLPG:
6999 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
7000 case EXIT_REASON_RDPMC:
7001 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
7002 case EXIT_REASON_RDTSC:
7003 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
7004 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
7005 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
7006 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
7007 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
7008 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
bfd0a56b 7009 case EXIT_REASON_INVEPT:
644d711a
NHE		 7010 /*
7011 * VMX instructions trap unconditionally. This allows L1 to
7012 * emulate them for its L2 guest, i.e., allows 3-level nesting!
7013 */
7014 return 1;
7015 case EXIT_REASON_CR_ACCESS:
7016 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
7017 case EXIT_REASON_DR_ACCESS:
7018 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
7019 case EXIT_REASON_IO_INSTRUCTION:
908a7bdd 7020 return nested_vmx_exit_handled_io(vcpu, vmcs12);
644d711a
NHE		 7021 case EXIT_REASON_MSR_READ:
7022 case EXIT_REASON_MSR_WRITE:
7023 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
7024 case EXIT_REASON_INVALID_STATE:
7025 return 1;
7026 case EXIT_REASON_MWAIT_INSTRUCTION:
7027 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
7028 case EXIT_REASON_MONITOR_INSTRUCTION:
7029 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
7030 case EXIT_REASON_PAUSE_INSTRUCTION:
7031 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
7032 nested_cpu_has2(vmcs12,
7033 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
7034 case EXIT_REASON_MCE_DURING_VMENTRY:
7035 return 0;
7036 case EXIT_REASON_TPR_BELOW_THRESHOLD:
7037 return 1;
7038 case EXIT_REASON_APIC_ACCESS:
7039 return nested_cpu_has2(vmcs12,
7040 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
7041 case EXIT_REASON_EPT_VIOLATION:
2b1be677
NHE		 7042 /*
7043 * L0 always deals with the EPT violation. If nested EPT is
7044 * used, and the nested mmu code discovers that the address is
7045 * missing in the guest EPT table (EPT12), the EPT violation
7046 * will be injected with nested_ept_inject_page_fault()
7047 */
7048 return 0;
644d711a 7049 case EXIT_REASON_EPT_MISCONFIG:
2b1be677
NHE		 7050 /*
7051 * L2 never uses directly L1's EPT, but rather L0's own EPT
7052 * table (shadow on EPT) or a merged EPT table that L0 built
7053 * (EPT on EPT). So any problems with the structure of the
7054 * table is L0's fault.
7055 */
644d711a
NHE		 7056 return 0;
7057 case EXIT_REASON_WBINVD:
7058 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
7059 case EXIT_REASON_XSETBV:
7060 return 1;
7061 default:
7062 return 1;
7063 }
7064}
7065
586f9607
AK		 7066static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
7067{
7068 *info1 = vmcs_readl(EXIT_QUALIFICATION);
7069 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
7070}
7071
6aa8b732
AK		 7072/*
7073 * The guest has exited. See if we can fix it or if we need userspace
7074 * assistance.
7075 */
851ba692 7076static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 7077{
29bd8a78 7078 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 7079 u32 exit_reason = vmx->exit_reason;
1155f76a 7080 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 7081
80ced186 7082 /* If guest state is invalid, start emulating */
14168786 7083 if (vmx->emulation_required)
80ced186 7084 return handle_invalid_guest_state(vcpu);
1d5a4d9b 7085
644d711a 7086 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
533558bc
JK		 7087 nested_vmx_vmexit(vcpu, exit_reason,
7088 vmcs_read32(VM_EXIT_INTR_INFO),
7089 vmcs_readl(EXIT_QUALIFICATION));
644d711a
NHE		 7090 return 1;
7091 }
7092
5120702e
MG		 7093 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
7094 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
7095 vcpu->run->fail_entry.hardware_entry_failure_reason
7096 = exit_reason;
7097 return 0;
7098 }
7099
29bd8a78 7100 if (unlikely(vmx->fail)) {
851ba692
AK		 7101 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
7102 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK		 7103 = vmcs_read32(VM_INSTRUCTION_ERROR);
7104 return 0;
7105 }
6aa8b732 7106
b9bf6882
XG		 7107 /*
7108 * Note:
7109 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
7110 * delivery event since it indicates guest is accessing MMIO.
7111 * The vm-exit can be triggered again after return to guest that
7112 * will cause infinite loop.
7113 */
d77c26fc 7114 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 7115 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac 7116 exit_reason != EXIT_REASON_EPT_VIOLATION &&
b9bf6882
XG		 7117 exit_reason != EXIT_REASON_TASK_SWITCH)) {
7118 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
7119 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
7120 vcpu->run->internal.ndata = 2;
7121 vcpu->run->internal.data[0] = vectoring_info;
7122 vcpu->run->internal.data[1] = exit_reason;
7123 return 0;
7124 }
3b86cd99 7125
644d711a
NHE		 7126 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
7127 !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
f5c4368f 7128 get_vmcs12(vcpu))))) {
c4282df9 7129 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 7130 vmx->soft_vnmi_blocked = 0;
3b86cd99 7131 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 7132 vcpu->arch.nmi_pending) {
3b86cd99
JK		 7133 /*
7134 * This CPU don't support us in finding the end of an
7135 * NMI-blocked window if the guest runs with IRQs
7136 * disabled. So we pull the trigger after 1 s of
7137 * futile waiting, but inform the user about this.
7138 */
7139 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
7140 "state on VCPU %d after 1 s timeout\n",
7141 __func__, vcpu->vcpu_id);
7142 vmx->soft_vnmi_blocked = 0;
3b86cd99 7143 }
3b86cd99
JK		 7144 }
7145
6aa8b732
AK		 7146 if (exit_reason < kvm_vmx_max_exit_handlers
7147 && kvm_vmx_exit_handlers[exit_reason])
851ba692 7148 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 7149 else {
851ba692
AK		 7150 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
7151 vcpu->run->hw.hardware_exit_reason = exit_reason;
6aa8b732
AK		 7152 }
7153 return 0;
7154}
7155
95ba8273 7156static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 7157{
95ba8273 7158 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 7159 vmcs_write32(TPR_THRESHOLD, 0);
7160 return;
7161 }
7162
95ba8273 7163 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 7164}
7165
8d14695f
YZ		 7166static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
7167{
7168 u32 sec_exec_control;
7169
7170 /*
7171 * There is not point to enable virtualize x2apic without enable
7172 * apicv
7173 */
c7c9c56c
YZ		 7174 if (!cpu_has_vmx_virtualize_x2apic_mode() ||
7175 !vmx_vm_has_apicv(vcpu->kvm))
8d14695f
YZ		 7176 return;
7177
7178 if (!vm_need_tpr_shadow(vcpu->kvm))
7179 return;
7180
7181 sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7182
7183 if (set) {
7184 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7185 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
7186 } else {
7187 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
7188 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7189 }
7190 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
7191
7192 vmx_set_msr_bitmap(vcpu);
7193}
7194
c7c9c56c
YZ		 7195static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
7196{
7197 u16 status;
7198 u8 old;
7199
7200 if (!vmx_vm_has_apicv(kvm))
7201 return;
7202
7203 if (isr == -1)
7204 isr = 0;
7205
7206 status = vmcs_read16(GUEST_INTR_STATUS);
7207 old = status >> 8;
7208 if (isr != old) {
7209 status &= 0xff;
7210 status |= isr << 8;
7211 vmcs_write16(GUEST_INTR_STATUS, status);
7212 }
7213}
7214
7215static void vmx_set_rvi(int vector)
7216{
7217 u16 status;
7218 u8 old;
7219
7220 status = vmcs_read16(GUEST_INTR_STATUS);
7221 old = (u8)status & 0xff;
7222 if ((u8)vector != old) {
7223 status &= ~0xff;
7224 status |= (u8)vector;
7225 vmcs_write16(GUEST_INTR_STATUS, status);
7226 }
7227}
7228
7229static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
7230{
7231 if (max_irr == -1)
7232 return;
7233
963fee16
WL		 7234 /*
7235 * If a vmexit is needed, vmx_check_nested_events handles it.
7236 */
7237 if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu))
7238 return;
7239
7240 if (!is_guest_mode(vcpu)) {
7241 vmx_set_rvi(max_irr);
7242 return;
7243 }
7244
7245 /*
7246 * Fall back to pre-APICv interrupt injection since L2
7247 * is run without virtual interrupt delivery.
7248 */
7249 if (!kvm_event_needs_reinjection(vcpu) &&
7250 vmx_interrupt_allowed(vcpu)) {
7251 kvm_queue_interrupt(vcpu, max_irr, false);
7252 vmx_inject_irq(vcpu);
7253 }
c7c9c56c
YZ		 7254}
7255
7256static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
7257{
3d81bc7e
YZ		 7258 if (!vmx_vm_has_apicv(vcpu->kvm))
7259 return;
7260
c7c9c56c
YZ		 7261 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
7262 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
7263 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
7264 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
7265}
7266
51aa01d1 7267static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
cf393f75 7268{
00eba012
AK		 7269 u32 exit_intr_info;
7270
7271 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
7272 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
7273 return;
7274
c5ca8e57 7275 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
00eba012 7276 exit_intr_info = vmx->exit_intr_info;
a0861c02
AK		 7277
7278 /* Handle machine checks before interrupts are enabled */
00eba012 7279 if (is_machine_check(exit_intr_info))
a0861c02
AK		 7280 kvm_machine_check();
7281
20f65983 7282 /* We need to handle NMIs before interrupts are enabled */
00eba012 7283 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
ff9d07a0
ZY		 7284 (exit_intr_info & INTR_INFO_VALID_MASK)) {
7285 kvm_before_handle_nmi(&vmx->vcpu);
20f65983 7286 asm("int $2");
ff9d07a0
ZY		 7287 kvm_after_handle_nmi(&vmx->vcpu);
7288 }
51aa01d1 7289}
20f65983 7290
a547c6db
YZ		 7291static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
7292{
7293 u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7294
7295 /*
7296 * If external interrupt exists, IF bit is set in rflags/eflags on the
7297 * interrupt stack frame, and interrupt will be enabled on a return
7298 * from interrupt handler.
7299 */
7300 if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
7301 == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
7302 unsigned int vector;
7303 unsigned long entry;
7304 gate_desc *desc;
7305 struct vcpu_vmx *vmx = to_vmx(vcpu);
7306#ifdef CONFIG_X86_64
7307 unsigned long tmp;
7308#endif
7309
7310 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
7311 desc = (gate_desc *)vmx->host_idt_base + vector;
7312 entry = gate_offset(*desc);
7313 asm volatile(
7314#ifdef CONFIG_X86_64
7315 "mov %%" _ASM_SP ", %[sp]\n\t"
7316 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
7317 "push $%c[ss]\n\t"
7318 "push %[sp]\n\t"
7319#endif
7320 "pushf\n\t"
7321 "orl $0x200, (%%" _ASM_SP ")\n\t"
7322 __ASM_SIZE(push) " $%c[cs]\n\t"
7323 "call *%[entry]\n\t"
7324 :
7325#ifdef CONFIG_X86_64
7326 [sp]"=&r"(tmp)
7327#endif
7328 :
7329 [entry]"r"(entry),
7330 [ss]"i"(__KERNEL_DS),
7331 [cs]"i"(__KERNEL_CS)
7332 );
7333 } else
7334 local_irq_enable();
7335}
7336
da8999d3
LJ		 7337static bool vmx_mpx_supported(void)
7338{
7339 return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
7340 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
7341}
7342
51aa01d1
AK		 7343static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
7344{
c5ca8e57 7345 u32 exit_intr_info;
51aa01d1
AK		 7346 bool unblock_nmi;
7347 u8 vector;
7348 bool idtv_info_valid;
7349
7350 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
20f65983 7351
cf393f75 7352 if (cpu_has_virtual_nmis()) {
9d58b931
AK		 7353 if (vmx->nmi_known_unmasked)
7354 return;
c5ca8e57
AK		 7355 /*
7356 * Can't use vmx->exit_intr_info since we're not sure what
7357 * the exit reason is.
7358 */
7359 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
cf393f75
AK		 7360 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
7361 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
7362 /*
7b4a25cb 7363 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 7364 * Re-set bit "block by NMI" before VM entry if vmexit caused by
7365 * a guest IRET fault.
7b4a25cb
GN		 7366 * SDM 3: 23.2.2 (September 2008)
7367 * Bit 12 is undefined in any of the following cases:
7368 * If the VM exit sets the valid bit in the IDT-vectoring
7369 * information field.
7370 * If the VM exit is due to a double fault.
cf393f75 7371 */
7b4a25cb
GN		 7372 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
7373 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 7374 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7375 GUEST_INTR_STATE_NMI);
9d58b931
AK		 7376 else
7377 vmx->nmi_known_unmasked =
7378 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
7379 & GUEST_INTR_STATE_NMI);
3b86cd99
JK		 7380 } else if (unlikely(vmx->soft_vnmi_blocked))
7381 vmx->vnmi_blocked_time +=
7382 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
51aa01d1
AK		 7383}
7384
3ab66e8a 7385static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
83422e17
AK		 7386 u32 idt_vectoring_info,
7387 int instr_len_field,
7388 int error_code_field)
51aa01d1 7389{
51aa01d1
AK		 7390 u8 vector;
7391 int type;
7392 bool idtv_info_valid;
7393
7394 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
668f612f 7395
3ab66e8a
JK		 7396 vcpu->arch.nmi_injected = false;
7397 kvm_clear_exception_queue(vcpu);
7398 kvm_clear_interrupt_queue(vcpu);
37b96e98
GN		 7399
7400 if (!idtv_info_valid)
7401 return;
7402
3ab66e8a 7403 kvm_make_request(KVM_REQ_EVENT, vcpu);
3842d135 7404
668f612f
AK		 7405 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
7406 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 7407
64a7ec06 7408 switch (type) {
37b96e98 7409 case INTR_TYPE_NMI_INTR:
3ab66e8a 7410 vcpu->arch.nmi_injected = true;
668f612f 7411 /*
7b4a25cb 7412 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 7413 * Clear bit "block by NMI" before VM entry if a NMI
7414 * delivery faulted.
668f612f 7415 */
3ab66e8a 7416 vmx_set_nmi_mask(vcpu, false);
37b96e98 7417 break;
37b96e98 7418 case INTR_TYPE_SOFT_EXCEPTION:
3ab66e8a 7419 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f
GN		 7420 /* fall through */
7421 case INTR_TYPE_HARD_EXCEPTION:
35920a35 7422 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
83422e17 7423 u32 err = vmcs_read32(error_code_field);
851eb667 7424 kvm_requeue_exception_e(vcpu, vector, err);
35920a35 7425 } else
851eb667 7426 kvm_requeue_exception(vcpu, vector);
37b96e98 7427 break;
66fd3f7f 7428 case INTR_TYPE_SOFT_INTR:
3ab66e8a 7429 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f 7430 /* fall through */
37b96e98 7431 case INTR_TYPE_EXT_INTR:
3ab66e8a 7432 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
37b96e98
GN		 7433 break;
7434 default:
7435 break;
f7d9238f 7436 }
cf393f75
AK		 7437}
7438
83422e17
AK		 7439static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
7440{
3ab66e8a 7441 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
83422e17
AK		 7442 VM_EXIT_INSTRUCTION_LEN,
7443 IDT_VECTORING_ERROR_CODE);
7444}
7445
b463a6f7
AK		 7446static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
7447{
3ab66e8a 7448 __vmx_complete_interrupts(vcpu,
b463a6f7
AK		 7449 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
7450 VM_ENTRY_INSTRUCTION_LEN,
7451 VM_ENTRY_EXCEPTION_ERROR_CODE);
7452
7453 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
7454}
7455
d7cd9796
GN		 7456static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
7457{
7458 int i, nr_msrs;
7459 struct perf_guest_switch_msr *msrs;
7460
7461 msrs = perf_guest_get_msrs(&nr_msrs);
7462
7463 if (!msrs)
7464 return;
7465
7466 for (i = 0; i < nr_msrs; i++)
7467 if (msrs[i].host == msrs[i].guest)
7468 clear_atomic_switch_msr(vmx, msrs[i].msr);
7469 else
7470 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
7471 msrs[i].host);
7472}
7473
a3b5ba49 7474static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 7475{
a2fa3e9f 7476 struct vcpu_vmx *vmx = to_vmx(vcpu);
2a7921b7 7477 unsigned long debugctlmsr;
104f226b
AK		 7478
7479 /* Record the guest's net vcpu time for enforced NMI injections. */
7480 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
7481 vmx->entry_time = ktime_get();
7482
7483 /* Don't enter VMX if guest state is invalid, let the exit handler
7484 start emulation until we arrive back to a valid state */
14168786 7485 if (vmx->emulation_required)
104f226b
AK		 7486 return;
7487
a7653ecd
RK		 7488 if (vmx->ple_window_dirty) {
7489 vmx->ple_window_dirty = false;
7490 vmcs_write32(PLE_WINDOW, vmx->ple_window);
7491 }
7492
012f83cb
AG		 7493 if (vmx->nested.sync_shadow_vmcs) {
7494 copy_vmcs12_to_shadow(vmx);
7495 vmx->nested.sync_shadow_vmcs = false;
7496 }
7497
104f226b
AK		 7498 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
7499 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
7500 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
7501 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
7502
7503 /* When single-stepping over STI and MOV SS, we must clear the
7504 * corresponding interruptibility bits in the guest state. Otherwise
7505 * vmentry fails as it then expects bit 14 (BS) in pending debug
7506 * exceptions being set, but that's not correct for the guest debugging
7507 * case. */
7508 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7509 vmx_set_interrupt_shadow(vcpu, 0);
7510
d7cd9796 7511 atomic_switch_perf_msrs(vmx);
2a7921b7 7512 debugctlmsr = get_debugctlmsr();
d7cd9796 7513
d462b819 7514 vmx->__launched = vmx->loaded_vmcs->launched;
104f226b 7515 asm(
6aa8b732 7516 /* Store host registers */
b188c81f
AK		 7517 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
7518 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
7519 "push %%" _ASM_CX " \n\t"
7520 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
313dbd49 7521 "je 1f \n\t"
b188c81f 7522 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
4ecac3fd 7523 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 7524 "1: \n\t"
d3edefc0 7525 /* Reload cr2 if changed */
b188c81f
AK		 7526 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
7527 "mov %%cr2, %%" _ASM_DX " \n\t"
7528 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
d3edefc0 7529 "je 2f \n\t"
b188c81f 7530 "mov %%" _ASM_AX", %%cr2 \n\t"
d3edefc0 7531 "2: \n\t"
6aa8b732 7532 /* Check if vmlaunch of vmresume is needed */
e08aa78a 7533 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 7534 /* Load guest registers. Don't clobber flags. */
b188c81f
AK		 7535 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
7536 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
7537 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
7538 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
7539 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
7540 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
05b3e0c2 7541#ifdef CONFIG_X86_64
e08aa78a
AK		 7542 "mov %c[r8](%0), %%r8 \n\t"
7543 "mov %c[r9](%0), %%r9 \n\t"
7544 "mov %c[r10](%0), %%r10 \n\t"
7545 "mov %c[r11](%0), %%r11 \n\t"
7546 "mov %c[r12](%0), %%r12 \n\t"
7547 "mov %c[r13](%0), %%r13 \n\t"
7548 "mov %c[r14](%0), %%r14 \n\t"
7549 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 7550#endif
b188c81f 7551 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
c801949d 7552
6aa8b732 7553 /* Enter guest mode */
83287ea4 7554 "jne 1f \n\t"
4ecac3fd 7555 __ex(ASM_VMX_VMLAUNCH) "\n\t"
83287ea4
AK		 7556 "jmp 2f \n\t"
7557 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
7558 "2: "
6aa8b732 7559 /* Save guest registers, load host registers, keep flags */
b188c81f 7560 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
40712fae 7561 "pop %0 \n\t"
b188c81f
AK		 7562 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
7563 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
7564 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
7565 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
7566 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
7567 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
7568 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
05b3e0c2 7569#ifdef CONFIG_X86_64
e08aa78a
AK		 7570 "mov %%r8, %c[r8](%0) \n\t"
7571 "mov %%r9, %c[r9](%0) \n\t"
7572 "mov %%r10, %c[r10](%0) \n\t"
7573 "mov %%r11, %c[r11](%0) \n\t"
7574 "mov %%r12, %c[r12](%0) \n\t"
7575 "mov %%r13, %c[r13](%0) \n\t"
7576 "mov %%r14, %c[r14](%0) \n\t"
7577 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 7578#endif
b188c81f
AK		 7579 "mov %%cr2, %%" _ASM_AX " \n\t"
7580 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
c801949d 7581
b188c81f 7582 "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t"
e08aa78a 7583 "setbe %c[fail](%0) \n\t"
83287ea4
AK		 7584 ".pushsection .rodata \n\t"
7585 ".global vmx_return \n\t"
7586 "vmx_return: " _ASM_PTR " 2b \n\t"
7587 ".popsection"
e08aa78a 7588 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
d462b819 7589 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
e08aa78a 7590 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 7591 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 7592 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
7593 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
7594 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
7595 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
7596 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
7597 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
7598 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 7599#ifdef CONFIG_X86_64
ad312c7c
ZX		 7600 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
7601 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
7602 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
7603 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
7604 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
7605 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
7606 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
7607 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 7608#endif
40712fae
AK		 7609 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
7610 [wordsize]"i"(sizeof(ulong))
c2036300
LV		 7611 : "cc", "memory"
7612#ifdef CONFIG_X86_64
b188c81f 7613 , "rax", "rbx", "rdi", "rsi"
c2036300 7614 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
b188c81f
AK		 7615#else
7616 , "eax", "ebx", "edi", "esi"
c2036300
LV		 7617#endif
7618 );
6aa8b732 7619
2a7921b7
GN		 7620 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
7621 if (debugctlmsr)
7622 update_debugctlmsr(debugctlmsr);
7623
aa67f609
AK		 7624#ifndef CONFIG_X86_64
7625 /*
7626 * The sysexit path does not restore ds/es, so we must set them to
7627 * a reasonable value ourselves.
7628 *
7629 * We can't defer this to vmx_load_host_state() since that function
7630 * may be executed in interrupt context, which saves and restore segments
7631 * around it, nullifying its effect.
7632 */
7633 loadsegment(ds, __USER_DS);
7634 loadsegment(es, __USER_DS);
7635#endif
7636
6de4f3ad 7637 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6de12732 7638 | (1 << VCPU_EXREG_RFLAGS)
aff48baa 7639 | (1 << VCPU_EXREG_PDPTR)
2fb92db1 7640 | (1 << VCPU_EXREG_SEGMENTS)
aff48baa 7641 | (1 << VCPU_EXREG_CR3));
5fdbf976
MT		 7642 vcpu->arch.regs_dirty = 0;
7643
1155f76a
AK		 7644 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
7645
d462b819 7646 vmx->loaded_vmcs->launched = 1;
1b6269db 7647
51aa01d1 7648 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
1e2b1dd7 7649 trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
51aa01d1 7650
e0b890d3
GN		 7651 /*
7652 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
7653 * we did not inject a still-pending event to L1 now because of
7654 * nested_run_pending, we need to re-enable this bit.
7655 */
7656 if (vmx->nested.nested_run_pending)
7657 kvm_make_request(KVM_REQ_EVENT, vcpu);
7658
7659 vmx->nested.nested_run_pending = 0;
7660
51aa01d1
AK		 7661 vmx_complete_atomic_exit(vmx);
7662 vmx_recover_nmi_blocking(vmx);
cf393f75 7663 vmx_complete_interrupts(vmx);
6aa8b732
AK		 7664}
7665
4fa7734c
PB		 7666static void vmx_load_vmcs01(struct kvm_vcpu *vcpu)
7667{
7668 struct vcpu_vmx *vmx = to_vmx(vcpu);
7669 int cpu;
7670
7671 if (vmx->loaded_vmcs == &vmx->vmcs01)
7672 return;
7673
7674 cpu = get_cpu();
7675 vmx->loaded_vmcs = &vmx->vmcs01;
7676 vmx_vcpu_put(vcpu);
7677 vmx_vcpu_load(vcpu, cpu);
7678 vcpu->cpu = cpu;
7679 put_cpu();
7680}
7681
6aa8b732
AK		 7682static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
7683{
fb3f0f51
RR		 7684 struct vcpu_vmx *vmx = to_vmx(vcpu);
7685
cdbecfc3 7686 free_vpid(vmx);
4fa7734c
PB		 7687 leave_guest_mode(vcpu);
7688 vmx_load_vmcs01(vcpu);
26a865f4 7689 free_nested(vmx);
4fa7734c 7690 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51
RR		 7691 kfree(vmx->guest_msrs);
7692 kvm_vcpu_uninit(vcpu);
a4770347 7693 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 7694}
7695
fb3f0f51 7696static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 7697{
fb3f0f51 7698 int err;
c16f862d 7699 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 7700 int cpu;
6aa8b732 7701
a2fa3e9f 7702 if (!vmx)
fb3f0f51
RR		 7703 return ERR_PTR(-ENOMEM);
7704
2384d2b3
SY		 7705 allocate_vpid(vmx);
7706
fb3f0f51
RR		 7707 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
7708 if (err)
7709 goto free_vcpu;
965b58a5 7710
a2fa3e9f 7711 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
03916db9
PB		 7712 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
7713 > PAGE_SIZE);
0123be42 7714
be6d05cf 7715 err = -ENOMEM;
fb3f0f51 7716 if (!vmx->guest_msrs) {
fb3f0f51
RR		 7717 goto uninit_vcpu;
7718 }
965b58a5 7719
d462b819
NHE		 7720 vmx->loaded_vmcs = &vmx->vmcs01;
7721 vmx->loaded_vmcs->vmcs = alloc_vmcs();
7722 if (!vmx->loaded_vmcs->vmcs)
fb3f0f51 7723 goto free_msrs;
d462b819
NHE		 7724 if (!vmm_exclusive)
7725 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
7726 loaded_vmcs_init(vmx->loaded_vmcs);
7727 if (!vmm_exclusive)
7728 kvm_cpu_vmxoff();
a2fa3e9f 7729
15ad7146
AK		 7730 cpu = get_cpu();
7731 vmx_vcpu_load(&vmx->vcpu, cpu);
e48672fa 7732 vmx->vcpu.cpu = cpu;
8b9cf98c 7733 err = vmx_vcpu_setup(vmx);
fb3f0f51 7734 vmx_vcpu_put(&vmx->vcpu);
15ad7146 7735 put_cpu();
fb3f0f51
RR		 7736 if (err)
7737 goto free_vmcs;
a63cb560 7738 if (vm_need_virtualize_apic_accesses(kvm)) {
be6d05cf
JK		 7739 err = alloc_apic_access_page(kvm);
7740 if (err)
5e4a0b3c 7741 goto free_vmcs;
a63cb560 7742 }
fb3f0f51 7743
b927a3ce
SY		 7744 if (enable_ept) {
7745 if (!kvm->arch.ept_identity_map_addr)
7746 kvm->arch.ept_identity_map_addr =
7747 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
93ea5388 7748 err = -ENOMEM;
b7ebfb05
SY		 7749 if (alloc_identity_pagetable(kvm) != 0)
7750 goto free_vmcs;
93ea5388
GN		 7751 if (!init_rmode_identity_map(kvm))
7752 goto free_vmcs;
b927a3ce 7753 }
b7ebfb05 7754
a9d30f33
NHE		 7755 vmx->nested.current_vmptr = -1ull;
7756 vmx->nested.current_vmcs12 = NULL;
7757
fb3f0f51
RR		 7758 return &vmx->vcpu;
7759
7760free_vmcs:
5f3fbc34 7761 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51 7762free_msrs:
fb3f0f51
RR		 7763 kfree(vmx->guest_msrs);
7764uninit_vcpu:
7765 kvm_vcpu_uninit(&vmx->vcpu);
7766free_vcpu:
cdbecfc3 7767 free_vpid(vmx);
a4770347 7768 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 7769 return ERR_PTR(err);
6aa8b732
AK		 7770}
7771
002c7f7c
YS		 7772static void __init vmx_check_processor_compat(void *rtn)
7773{
7774 struct vmcs_config vmcs_conf;
7775
7776 *(int *)rtn = 0;
7777 if (setup_vmcs_config(&vmcs_conf) < 0)
7778 *(int *)rtn = -EIO;
7779 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
7780 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
7781 smp_processor_id());
7782 *(int *)rtn = -EIO;
7783 }
7784}
7785
67253af5
SY		 7786static int get_ept_level(void)
7787{
7788 return VMX_EPT_DEFAULT_GAW + 1;
7789}
7790
4b12f0de 7791static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 7792{
4b12f0de
SY		 7793 u64 ret;
7794
522c68c4
SY		 7795 /* For VT-d and EPT combination
7796 * 1. MMIO: always map as UC
7797 * 2. EPT with VT-d:
7798 * a. VT-d without snooping control feature: can't guarantee the
7799 * result, try to trust guest.
7800 * b. VT-d with snooping control feature: snooping control feature of
7801 * VT-d engine can guarantee the cache correctness. Just set it
7802 * to WB to keep consistent with host. So the same as item 3.
a19a6d11 7803 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
522c68c4
SY		 7804 * consistent with host MTRR
7805 */
4b12f0de
SY		 7806 if (is_mmio)
7807 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
e0f0bbc5 7808 else if (kvm_arch_has_noncoherent_dma(vcpu->kvm))
522c68c4
SY		 7809 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
7810 VMX_EPT_MT_EPTE_SHIFT;
4b12f0de 7811 else
522c68c4 7812 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
a19a6d11 7813 | VMX_EPT_IPAT_BIT;
4b12f0de
SY		 7814
7815 return ret;
64d4d521
SY		 7816}
7817
17cc3935 7818static int vmx_get_lpage_level(void)
344f414f 7819{
878403b7
SY		 7820 if (enable_ept && !cpu_has_vmx_ept_1g_page())
7821 return PT_DIRECTORY_LEVEL;
7822 else
7823 /* For shadow and EPT supported 1GB page */
7824 return PT_PDPE_LEVEL;
344f414f
JR		 7825}
7826
0e851880
SY		 7827static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
7828{
4e47c7a6
SY		 7829 struct kvm_cpuid_entry2 *best;
7830 struct vcpu_vmx *vmx = to_vmx(vcpu);
7831 u32 exec_control;
7832
7833 vmx->rdtscp_enabled = false;
7834 if (vmx_rdtscp_supported()) {
7835 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7836 if (exec_control & SECONDARY_EXEC_RDTSCP) {
7837 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
7838 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
7839 vmx->rdtscp_enabled = true;
7840 else {
7841 exec_control &= ~SECONDARY_EXEC_RDTSCP;
7842 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7843 exec_control);
7844 }
7845 }
7846 }
ad756a16 7847
ad756a16
MJ		 7848 /* Exposing INVPCID only when PCID is exposed */
7849 best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
7850 if (vmx_invpcid_supported() &&
4f977045 7851 best && (best->ebx & bit(X86_FEATURE_INVPCID)) &&
ad756a16 7852 guest_cpuid_has_pcid(vcpu)) {
29282fde 7853 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
ad756a16
MJ		 7854 exec_control |= SECONDARY_EXEC_ENABLE_INVPCID;
7855 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7856 exec_control);
7857 } else {
29282fde
TI		 7858 if (cpu_has_secondary_exec_ctrls()) {
7859 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7860 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
7861 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7862 exec_control);
7863 }
ad756a16 7864 if (best)
4f977045 7865 best->ebx &= ~bit(X86_FEATURE_INVPCID);
ad756a16 7866 }
0e851880
SY		 7867}
7868
d4330ef2
JR		 7869static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
7870{
7b8050f5
NHE		 7871 if (func == 1 && nested)
7872 entry->ecx |= bit(X86_FEATURE_VMX);
d4330ef2
JR		 7873}
7874
25d92081
YZ		 7875static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
7876 struct x86_exception *fault)
7877{
533558bc
JK		 7878 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7879 u32 exit_reason;
25d92081
YZ		 7880
7881 if (fault->error_code & PFERR_RSVD_MASK)
533558bc 7882 exit_reason = EXIT_REASON_EPT_MISCONFIG;
25d92081 7883 else
533558bc
JK		 7884 exit_reason = EXIT_REASON_EPT_VIOLATION;
7885 nested_vmx_vmexit(vcpu, exit_reason, 0, vcpu->arch.exit_qualification);
25d92081
YZ		 7886 vmcs12->guest_physical_address = fault->address;
7887}
7888
155a97a3
NHE		 7889/* Callbacks for nested_ept_init_mmu_context: */
7890
7891static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
7892{
7893 /* return the page table to be shadowed - in our case, EPT12 */
7894 return get_vmcs12(vcpu)->ept_pointer;
7895}
7896
8a3c1a33 7897static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
155a97a3 7898{
8a3c1a33 7899 kvm_init_shadow_ept_mmu(vcpu, &vcpu->arch.mmu,
155a97a3
NHE		 7900 nested_vmx_ept_caps & VMX_EPT_EXECUTE_ONLY_BIT);
7901
7902 vcpu->arch.mmu.set_cr3 = vmx_set_cr3;
7903 vcpu->arch.mmu.get_cr3 = nested_ept_get_cr3;
7904 vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
7905
7906 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
155a97a3
NHE		 7907}
7908
7909static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
7910{
7911 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
7912}
7913
feaf0c7d
GN		 7914static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
7915 struct x86_exception *fault)
7916{
7917 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7918
7919 WARN_ON(!is_guest_mode(vcpu));
7920
7921 /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
7922 if (vmcs12->exception_bitmap & (1u << PF_VECTOR))
533558bc
JK		 7923 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
7924 vmcs_read32(VM_EXIT_INTR_INFO),
7925 vmcs_readl(EXIT_QUALIFICATION));
feaf0c7d
GN		 7926 else
7927 kvm_inject_page_fault(vcpu, fault);
7928}
7929
a2bcba50
WL		 7930static bool nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
7931 struct vmcs12 *vmcs12)
7932{
7933 struct vcpu_vmx *vmx = to_vmx(vcpu);
7934
7935 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
7936 if (!PAGE_ALIGNED(vmcs12->apic_access_addr))
7937 /*TODO: Also verify bits beyond physical address width are 0*/
7938 return false;
7939
7940 /*
7941 * Translate L1 physical address to host physical
7942 * address for vmcs02. Keep the page pinned, so this
7943 * physical address remains valid. We keep a reference
7944 * to it so we can release it later.
7945 */
7946 if (vmx->nested.apic_access_page) /* shouldn't happen */
7947 nested_release_page(vmx->nested.apic_access_page);
7948 vmx->nested.apic_access_page =
7949 nested_get_page(vcpu, vmcs12->apic_access_addr);
7950 }
7951 return true;
7952}
7953
f4124500
JK		 7954static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
7955{
7956 u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
7957 struct vcpu_vmx *vmx = to_vmx(vcpu);
7958
7959 if (vcpu->arch.virtual_tsc_khz == 0)
7960 return;
7961
7962 /* Make sure short timeouts reliably trigger an immediate vmexit.
7963 * hrtimer_start does not guarantee this. */
7964 if (preemption_timeout <= 1) {
7965 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
7966 return;
7967 }
7968
7969 preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
7970 preemption_timeout *= 1000000;
7971 do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
7972 hrtimer_start(&vmx->nested.preemption_timer,
7973 ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
7974}
7975
fe3ef05c
NHE		 7976/*
7977 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
7978 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
7979 * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
7980 * guest in a way that will both be appropriate to L1's requests, and our
7981 * needs. In addition to modifying the active vmcs (which is vmcs02), this
7982 * function also has additional necessary side-effects, like setting various
7983 * vcpu->arch fields.
7984 */
7985static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7986{
7987 struct vcpu_vmx *vmx = to_vmx(vcpu);
7988 u32 exec_control;
7989
7990 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
7991 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
7992 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
7993 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
7994 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
7995 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
7996 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
7997 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
7998 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
7999 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
8000 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
8001 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
8002 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
8003 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
8004 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
8005 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
8006 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
8007 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
8008 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
8009 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
8010 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
8011 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
8012 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
8013 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
8014 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
8015 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
8016 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
8017 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
8018 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
8019 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
8020 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
8021 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
8022 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
8023 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
8024 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
8025 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
8026
2996fca0
JK		 8027 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS) {
8028 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
8029 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
8030 } else {
8031 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
8032 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
8033 }
fe3ef05c
NHE		 8034 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
8035 vmcs12->vm_entry_intr_info_field);
8036 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
8037 vmcs12->vm_entry_exception_error_code);
8038 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
8039 vmcs12->vm_entry_instruction_len);
8040 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
8041 vmcs12->guest_interruptibility_info);
fe3ef05c 8042 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
63fbf59f 8043 vmx_set_rflags(vcpu, vmcs12->guest_rflags);
fe3ef05c
NHE		 8044 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
8045 vmcs12->guest_pending_dbg_exceptions);
8046 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
8047 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
8048
8049 vmcs_write64(VMCS_LINK_POINTER, -1ull);
8050
f4124500
JK		 8051 exec_control = vmcs12->pin_based_vm_exec_control;
8052 exec_control |= vmcs_config.pin_based_exec_ctrl;
696dfd95
PB		 8053 exec_control &= ~(PIN_BASED_VMX_PREEMPTION_TIMER |
8054 PIN_BASED_POSTED_INTR);
f4124500 8055 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
fe3ef05c 8056
f4124500
JK		 8057 vmx->nested.preemption_timer_expired = false;
8058 if (nested_cpu_has_preemption_timer(vmcs12))
8059 vmx_start_preemption_timer(vcpu);
0238ea91 8060
fe3ef05c
NHE		 8061 /*
8062 * Whether page-faults are trapped is determined by a combination of
8063 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
8064 * If enable_ept, L0 doesn't care about page faults and we should
8065 * set all of these to L1's desires. However, if !enable_ept, L0 does
8066 * care about (at least some) page faults, and because it is not easy
8067 * (if at all possible?) to merge L0 and L1's desires, we simply ask
8068 * to exit on each and every L2 page fault. This is done by setting
8069 * MASK=MATCH=0 and (see below) EB.PF=1.
8070 * Note that below we don't need special code to set EB.PF beyond the
8071 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
8072 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
8073 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
8074 *
8075 * A problem with this approach (when !enable_ept) is that L1 may be
8076 * injected with more page faults than it asked for. This could have
8077 * caused problems, but in practice existing hypervisors don't care.
8078 * To fix this, we will need to emulate the PFEC checking (on the L1
8079 * page tables), using walk_addr(), when injecting PFs to L1.
8080 */
8081 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
8082 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
8083 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
8084 enable_ept ? vmcs12->page_fault_error_code_match : 0);
8085
8086 if (cpu_has_secondary_exec_ctrls()) {
f4124500 8087 exec_control = vmx_secondary_exec_control(vmx);
fe3ef05c
NHE		 8088 if (!vmx->rdtscp_enabled)
8089 exec_control &= ~SECONDARY_EXEC_RDTSCP;
8090 /* Take the following fields only from vmcs12 */
696dfd95
PB		 8091 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
8092 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
8093 SECONDARY_EXEC_APIC_REGISTER_VIRT);
fe3ef05c
NHE		 8094 if (nested_cpu_has(vmcs12,
8095 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
8096 exec_control |= vmcs12->secondary_vm_exec_control;
8097
8098 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
fe3ef05c
NHE		 8099 /*
8100 * If translation failed, no matter: This feature asks
8101 * to exit when accessing the given address, and if it
8102 * can never be accessed, this feature won't do
8103 * anything anyway.
8104 */
8105 if (!vmx->nested.apic_access_page)
8106 exec_control &=
8107 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8108 else
8109 vmcs_write64(APIC_ACCESS_ADDR,
8110 page_to_phys(vmx->nested.apic_access_page));
ca3f257a
JK		 8111 } else if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm)) {
8112 exec_control |=
8113 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8114 vmcs_write64(APIC_ACCESS_ADDR,
8115 page_to_phys(vcpu->kvm->arch.apic_access_page));
fe3ef05c
NHE		 8116 }
8117
8118 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
8119 }
8120
8121
8122 /*
8123 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
8124 * Some constant fields are set here by vmx_set_constant_host_state().
8125 * Other fields are different per CPU, and will be set later when
8126 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
8127 */
a547c6db 8128 vmx_set_constant_host_state(vmx);
fe3ef05c
NHE		 8129
8130 /*
8131 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
8132 * entry, but only if the current (host) sp changed from the value
8133 * we wrote last (vmx->host_rsp). This cache is no longer relevant
8134 * if we switch vmcs, and rather than hold a separate cache per vmcs,
8135 * here we just force the write to happen on entry.
8136 */
8137 vmx->host_rsp = 0;
8138
8139 exec_control = vmx_exec_control(vmx); /* L0's desires */
8140 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
8141 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
8142 exec_control &= ~CPU_BASED_TPR_SHADOW;
8143 exec_control |= vmcs12->cpu_based_vm_exec_control;
8144 /*
8145 * Merging of IO and MSR bitmaps not currently supported.
8146 * Rather, exit every time.
8147 */
8148 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
8149 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
8150 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
8151
8152 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
8153
8154 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
8155 * bitwise-or of what L1 wants to trap for L2, and what we want to
8156 * trap. Note that CR0.TS also needs updating - we do this later.
8157 */
8158 update_exception_bitmap(vcpu);
8159 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
8160 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
8161
8049d651
NHE		 8162 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
8163 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
8164 * bits are further modified by vmx_set_efer() below.
8165 */
f4124500 8166 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
8049d651
NHE		 8167
8168 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
8169 * emulated by vmx_set_efer(), below.
8170 */
2961e876 8171 vm_entry_controls_init(vmx,
8049d651
NHE		 8172 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
8173 ~VM_ENTRY_IA32E_MODE) |
fe3ef05c
NHE		 8174 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
8175
44811c02 8176 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) {
fe3ef05c 8177 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
44811c02
JK		 8178 vcpu->arch.pat = vmcs12->guest_ia32_pat;
8179 } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
fe3ef05c
NHE		 8180 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
8181
8182
8183 set_cr4_guest_host_mask(vmx);
8184
36be0b9d
PB		 8185 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
8186 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
8187
27fc51b2
NHE		 8188 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
8189 vmcs_write64(TSC_OFFSET,
8190 vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
8191 else
8192 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
fe3ef05c
NHE		 8193
8194 if (enable_vpid) {
8195 /*
8196 * Trivially support vpid by letting L2s share their parent
8197 * L1's vpid. TODO: move to a more elaborate solution, giving
8198 * each L2 its own vpid and exposing the vpid feature to L1.
8199 */
8200 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
8201 vmx_flush_tlb(vcpu);
8202 }
8203
155a97a3
NHE		 8204 if (nested_cpu_has_ept(vmcs12)) {
8205 kvm_mmu_unload(vcpu);
8206 nested_ept_init_mmu_context(vcpu);
8207 }
8208
fe3ef05c
NHE		 8209 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
8210 vcpu->arch.efer = vmcs12->guest_ia32_efer;
d1fa0352 8211 else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
fe3ef05c
NHE		 8212 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
8213 else
8214 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
8215 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
8216 vmx_set_efer(vcpu, vcpu->arch.efer);
8217
8218 /*
8219 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
8220 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
8221 * The CR0_READ_SHADOW is what L2 should have expected to read given
8222 * the specifications by L1; It's not enough to take
8223 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
8224 * have more bits than L1 expected.
8225 */
8226 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
8227 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
8228
8229 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
8230 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
8231
8232 /* shadow page tables on either EPT or shadow page tables */
8233 kvm_set_cr3(vcpu, vmcs12->guest_cr3);
8234 kvm_mmu_reset_context(vcpu);
8235
feaf0c7d
GN		 8236 if (!enable_ept)
8237 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
8238
3633cfc3
NHE		 8239 /*
8240 * L1 may access the L2's PDPTR, so save them to construct vmcs12
8241 */
8242 if (enable_ept) {
8243 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
8244 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
8245 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
8246 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
8247 }
8248
fe3ef05c
NHE		 8249 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
8250 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
8251}
8252
cd232ad0
NHE		 8253/*
8254 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
8255 * for running an L2 nested guest.
8256 */
8257static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
8258{
8259 struct vmcs12 *vmcs12;
8260 struct vcpu_vmx *vmx = to_vmx(vcpu);
8261 int cpu;
8262 struct loaded_vmcs *vmcs02;
384bb783 8263 bool ia32e;
cd232ad0
NHE		 8264
8265 if (!nested_vmx_check_permission(vcpu) ||
8266 !nested_vmx_check_vmcs12(vcpu))
8267 return 1;
8268
8269 skip_emulated_instruction(vcpu);
8270 vmcs12 = get_vmcs12(vcpu);
8271
012f83cb
AG		 8272 if (enable_shadow_vmcs)
8273 copy_shadow_to_vmcs12(vmx);
8274
7c177938
NHE		 8275 /*
8276 * The nested entry process starts with enforcing various prerequisites
8277 * on vmcs12 as required by the Intel SDM, and act appropriately when
8278 * they fail: As the SDM explains, some conditions should cause the
8279 * instruction to fail, while others will cause the instruction to seem
8280 * to succeed, but return an EXIT_REASON_INVALID_STATE.
8281 * To speed up the normal (success) code path, we should avoid checking
8282 * for misconfigurations which will anyway be caught by the processor
8283 * when using the merged vmcs02.
8284 */
8285 if (vmcs12->launch_state == launch) {
8286 nested_vmx_failValid(vcpu,
8287 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
8288 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
8289 return 1;
8290 }
8291
6dfacadd
JK		 8292 if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
8293 vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT) {
26539bd0
PB		 8294 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8295 return 1;
8296 }
8297
7c177938 8298 if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
bc39c4db 8299 !PAGE_ALIGNED(vmcs12->msr_bitmap)) {
7c177938
NHE		 8300 /*TODO: Also verify bits beyond physical address width are 0*/
8301 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8302 return 1;
8303 }
8304
a2bcba50 8305 if (!nested_get_vmcs12_pages(vcpu, vmcs12)) {
7c177938
NHE		 8306 /*TODO: Also verify bits beyond physical address width are 0*/
8307 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8308 return 1;
8309 }
8310
8311 if (vmcs12->vm_entry_msr_load_count > 0 ||
8312 vmcs12->vm_exit_msr_load_count > 0 ||
8313 vmcs12->vm_exit_msr_store_count > 0) {
bd80158a
JK		 8314 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
8315 __func__);
7c177938
NHE		 8316 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8317 return 1;
8318 }
8319
8320 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
3dcdf3ec
JK		 8321 nested_vmx_true_procbased_ctls_low,
8322 nested_vmx_procbased_ctls_high) ||
7c177938
NHE		 8323 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
8324 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
8325 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
8326 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
8327 !vmx_control_verify(vmcs12->vm_exit_controls,
2996fca0
JK		 8328 nested_vmx_true_exit_ctls_low,
8329 nested_vmx_exit_ctls_high) ||
7c177938 8330 !vmx_control_verify(vmcs12->vm_entry_controls,
2996fca0
JK		 8331 nested_vmx_true_entry_ctls_low,
8332 nested_vmx_entry_ctls_high))
7c177938
NHE		 8333 {
8334 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8335 return 1;
8336 }
8337
8338 if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
8339 ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
8340 nested_vmx_failValid(vcpu,
8341 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
8342 return 1;
8343 }
8344
92fbc7b1 8345 if (!nested_cr0_valid(vmcs12, vmcs12->guest_cr0) ||
7c177938
NHE		 8346 ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
8347 nested_vmx_entry_failure(vcpu, vmcs12,
8348 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
8349 return 1;
8350 }
8351 if (vmcs12->vmcs_link_pointer != -1ull) {
8352 nested_vmx_entry_failure(vcpu, vmcs12,
8353 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
8354 return 1;
8355 }
8356
384bb783 8357 /*
cb0c8cda 8358 * If the load IA32_EFER VM-entry control is 1, the following checks
384bb783
JK		 8359 * are performed on the field for the IA32_EFER MSR:
8360 * - Bits reserved in the IA32_EFER MSR must be 0.
8361 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
8362 * the IA-32e mode guest VM-exit control. It must also be identical
8363 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
8364 * CR0.PG) is 1.
8365 */
8366 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
8367 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
8368 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
8369 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
8370 ((vmcs12->guest_cr0 & X86_CR0_PG) &&
8371 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
8372 nested_vmx_entry_failure(vcpu, vmcs12,
8373 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
8374 return 1;
8375 }
8376 }
8377
8378 /*
8379 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
8380 * IA32_EFER MSR must be 0 in the field for that register. In addition,
8381 * the values of the LMA and LME bits in the field must each be that of
8382 * the host address-space size VM-exit control.
8383 */
8384 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
8385 ia32e = (vmcs12->vm_exit_controls &
8386 VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
8387 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
8388 ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
8389 ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
8390 nested_vmx_entry_failure(vcpu, vmcs12,
8391 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
8392 return 1;
8393 }
8394 }
8395
7c177938
NHE		 8396 /*
8397 * We're finally done with prerequisite checking, and can start with
8398 * the nested entry.
8399 */
8400
cd232ad0
NHE		 8401 vmcs02 = nested_get_current_vmcs02(vmx);
8402 if (!vmcs02)
8403 return -ENOMEM;
8404
8405 enter_guest_mode(vcpu);
8406
8407 vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
8408
2996fca0
JK		 8409 if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
8410 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
8411
cd232ad0
NHE		 8412 cpu = get_cpu();
8413 vmx->loaded_vmcs = vmcs02;
8414 vmx_vcpu_put(vcpu);
8415 vmx_vcpu_load(vcpu, cpu);
8416 vcpu->cpu = cpu;
8417 put_cpu();
8418
36c3cc42
JK		 8419 vmx_segment_cache_clear(vmx);
8420
cd232ad0
NHE		 8421 vmcs12->launch_state = 1;
8422
8423 prepare_vmcs02(vcpu, vmcs12);
8424
6dfacadd
JK		 8425 if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
8426 return kvm_emulate_halt(vcpu);
8427
7af40ad3
JK		 8428 vmx->nested.nested_run_pending = 1;
8429
cd232ad0
NHE		 8430 /*
8431 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
8432 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
8433 * returned as far as L1 is concerned. It will only return (and set
8434 * the success flag) when L2 exits (see nested_vmx_vmexit()).
8435 */
8436 return 1;
8437}
8438
4704d0be
NHE		 8439/*
8440 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
8441 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
8442 * This function returns the new value we should put in vmcs12.guest_cr0.
8443 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
8444 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
8445 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
8446 * didn't trap the bit, because if L1 did, so would L0).
8447 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
8448 * been modified by L2, and L1 knows it. So just leave the old value of
8449 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
8450 * isn't relevant, because if L0 traps this bit it can set it to anything.
8451 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
8452 * changed these bits, and therefore they need to be updated, but L0
8453 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
8454 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
8455 */
8456static inline unsigned long
8457vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
8458{
8459 return
8460 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
8461 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
8462 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
8463 vcpu->arch.cr0_guest_owned_bits));
8464}
8465
8466static inline unsigned long
8467vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
8468{
8469 return
8470 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
8471 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
8472 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
8473 vcpu->arch.cr4_guest_owned_bits));
8474}
8475
5f3d5799
JK		 8476static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
8477 struct vmcs12 *vmcs12)
8478{
8479 u32 idt_vectoring;
8480 unsigned int nr;
8481
851eb667 8482 if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
5f3d5799
JK		 8483 nr = vcpu->arch.exception.nr;
8484 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
8485
8486 if (kvm_exception_is_soft(nr)) {
8487 vmcs12->vm_exit_instruction_len =
8488 vcpu->arch.event_exit_inst_len;
8489 idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
8490 } else
8491 idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
8492
8493 if (vcpu->arch.exception.has_error_code) {
8494 idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
8495 vmcs12->idt_vectoring_error_code =
8496 vcpu->arch.exception.error_code;
8497 }
8498
8499 vmcs12->idt_vectoring_info_field = idt_vectoring;
cd2633c5 8500 } else if (vcpu->arch.nmi_injected) {
5f3d5799
JK		 8501 vmcs12->idt_vectoring_info_field =
8502 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
8503 } else if (vcpu->arch.interrupt.pending) {
8504 nr = vcpu->arch.interrupt.nr;
8505 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
8506
8507 if (vcpu->arch.interrupt.soft) {
8508 idt_vectoring |= INTR_TYPE_SOFT_INTR;
8509 vmcs12->vm_entry_instruction_len =
8510 vcpu->arch.event_exit_inst_len;
8511 } else
8512 idt_vectoring |= INTR_TYPE_EXT_INTR;
8513
8514 vmcs12->idt_vectoring_info_field = idt_vectoring;
8515 }
8516}
8517
b6b8a145
JK		 8518static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
8519{
8520 struct vcpu_vmx *vmx = to_vmx(vcpu);
8521
f4124500
JK		 8522 if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
8523 vmx->nested.preemption_timer_expired) {
8524 if (vmx->nested.nested_run_pending)
8525 return -EBUSY;
8526 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
8527 return 0;
8528 }
8529
b6b8a145 8530 if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
220c5672
JK		 8531 if (vmx->nested.nested_run_pending ||
8532 vcpu->arch.interrupt.pending)
b6b8a145
JK		 8533 return -EBUSY;
8534 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
8535 NMI_VECTOR | INTR_TYPE_NMI_INTR |
8536 INTR_INFO_VALID_MASK, 0);
8537 /*
8538 * The NMI-triggered VM exit counts as injection:
8539 * clear this one and block further NMIs.
8540 */
8541 vcpu->arch.nmi_pending = 0;
8542 vmx_set_nmi_mask(vcpu, true);
8543 return 0;
8544 }
8545
8546 if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
8547 nested_exit_on_intr(vcpu)) {
8548 if (vmx->nested.nested_run_pending)
8549 return -EBUSY;
8550 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
8551 }
8552
8553 return 0;
8554}
8555
f4124500
JK		 8556static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
8557{
8558 ktime_t remaining =
8559 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
8560 u64 value;
8561
8562 if (ktime_to_ns(remaining) <= 0)
8563 return 0;
8564
8565 value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
8566 do_div(value, 1000000);
8567 return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
8568}
8569
4704d0be
NHE		 8570/*
8571 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
8572 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
8573 * and this function updates it to reflect the changes to the guest state while
8574 * L2 was running (and perhaps made some exits which were handled directly by L0
8575 * without going back to L1), and to reflect the exit reason.
8576 * Note that we do not have to copy here all VMCS fields, just those that
8577 * could have changed by the L2 guest or the exit - i.e., the guest-state and
8578 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
8579 * which already writes to vmcs12 directly.
8580 */
533558bc
JK		 8581static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
8582 u32 exit_reason, u32 exit_intr_info,
8583 unsigned long exit_qualification)
4704d0be
NHE		 8584{
8585 /* update guest state fields: */
8586 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
8587 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
8588
4704d0be
NHE		 8589 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
8590 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
8591 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
8592
8593 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
8594 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
8595 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
8596 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
8597 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
8598 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
8599 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
8600 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
8601 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
8602 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
8603 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
8604 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
8605 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
8606 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
8607 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
8608 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
8609 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
8610 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
8611 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
8612 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
8613 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
8614 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
8615 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
8616 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
8617 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
8618 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
8619 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
8620 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
8621 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
8622 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
8623 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
8624 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
8625 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
8626 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
8627 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
8628 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
8629
4704d0be
NHE		 8630 vmcs12->guest_interruptibility_info =
8631 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
8632 vmcs12->guest_pending_dbg_exceptions =
8633 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
3edf1e69
JK		 8634 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
8635 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
8636 else
8637 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
4704d0be 8638
f4124500
JK		 8639 if (nested_cpu_has_preemption_timer(vmcs12)) {
8640 if (vmcs12->vm_exit_controls &
8641 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
8642 vmcs12->vmx_preemption_timer_value =
8643 vmx_get_preemption_timer_value(vcpu);
8644 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
8645 }
7854cbca 8646
3633cfc3
NHE		 8647 /*
8648 * In some cases (usually, nested EPT), L2 is allowed to change its
8649 * own CR3 without exiting. If it has changed it, we must keep it.
8650 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
8651 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
8652 *
8653 * Additionally, restore L2's PDPTR to vmcs12.
8654 */
8655 if (enable_ept) {
8656 vmcs12->guest_cr3 = vmcs_read64(GUEST_CR3);
8657 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
8658 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
8659 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
8660 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
8661 }
8662
c18911a2
JK		 8663 vmcs12->vm_entry_controls =
8664 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
2961e876 8665 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
c18911a2 8666
2996fca0
JK		 8667 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
8668 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
8669 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
8670 }
8671
4704d0be
NHE		 8672 /* TODO: These cannot have changed unless we have MSR bitmaps and
8673 * the relevant bit asks not to trap the change */
b8c07d55 8674 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
4704d0be 8675 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
10ba54a5
JK		 8676 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
8677 vmcs12->guest_ia32_efer = vcpu->arch.efer;
4704d0be
NHE		 8678 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
8679 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
8680 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
36be0b9d
PB		 8681 if (vmx_mpx_supported())
8682 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
4704d0be
NHE		 8683
8684 /* update exit information fields: */
8685
533558bc
JK		 8686 vmcs12->vm_exit_reason = exit_reason;
8687 vmcs12->exit_qualification = exit_qualification;
4704d0be 8688
533558bc 8689 vmcs12->vm_exit_intr_info = exit_intr_info;
c0d1c770
JK		 8690 if ((vmcs12->vm_exit_intr_info &
8691 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
8692 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
8693 vmcs12->vm_exit_intr_error_code =
8694 vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5f3d5799 8695 vmcs12->idt_vectoring_info_field = 0;
4704d0be
NHE		 8696 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
8697 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
8698
5f3d5799
JK		 8699 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
8700 /* vm_entry_intr_info_field is cleared on exit. Emulate this
8701 * instead of reading the real value. */
4704d0be 8702 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
5f3d5799
JK		 8703
8704 /*
8705 * Transfer the event that L0 or L1 may wanted to inject into
8706 * L2 to IDT_VECTORING_INFO_FIELD.
8707 */
8708 vmcs12_save_pending_event(vcpu, vmcs12);
8709 }
8710
8711 /*
8712 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
8713 * preserved above and would only end up incorrectly in L1.
8714 */
8715 vcpu->arch.nmi_injected = false;
8716 kvm_clear_exception_queue(vcpu);
8717 kvm_clear_interrupt_queue(vcpu);
4704d0be
NHE		 8718}
8719
8720/*
8721 * A part of what we need to when the nested L2 guest exits and we want to
8722 * run its L1 parent, is to reset L1's guest state to the host state specified
8723 * in vmcs12.
8724 * This function is to be called not only on normal nested exit, but also on
8725 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
8726 * Failures During or After Loading Guest State").
8727 * This function should be called when the active VMCS is L1's (vmcs01).
8728 */
733568f9
JK		 8729static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
8730 struct vmcs12 *vmcs12)
4704d0be 8731{
21feb4eb
ACL		 8732 struct kvm_segment seg;
8733
4704d0be
NHE		 8734 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
8735 vcpu->arch.efer = vmcs12->host_ia32_efer;
d1fa0352 8736 else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
4704d0be
NHE		 8737 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
8738 else
8739 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
8740 vmx_set_efer(vcpu, vcpu->arch.efer);
8741
8742 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
8743 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
1adfa76a 8744 vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
4704d0be
NHE		 8745 /*
8746 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
8747 * actually changed, because it depends on the current state of
8748 * fpu_active (which may have changed).
8749 * Note that vmx_set_cr0 refers to efer set above.
8750 */
9e3e4dbf 8751 vmx_set_cr0(vcpu, vmcs12->host_cr0);
4704d0be
NHE		 8752 /*
8753 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
8754 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
8755 * but we also need to update cr0_guest_host_mask and exception_bitmap.
8756 */
8757 update_exception_bitmap(vcpu);
8758 vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
8759 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
8760
8761 /*
8762 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
8763 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
8764 */
8765 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
8766 kvm_set_cr4(vcpu, vmcs12->host_cr4);
8767
29bf08f1 8768 nested_ept_uninit_mmu_context(vcpu);
155a97a3 8769
4704d0be
NHE		 8770 kvm_set_cr3(vcpu, vmcs12->host_cr3);
8771 kvm_mmu_reset_context(vcpu);
8772
feaf0c7d
GN		 8773 if (!enable_ept)
8774 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
8775
4704d0be
NHE		 8776 if (enable_vpid) {
8777 /*
8778 * Trivially support vpid by letting L2s share their parent
8779 * L1's vpid. TODO: move to a more elaborate solution, giving
8780 * each L2 its own vpid and exposing the vpid feature to L1.
8781 */
8782 vmx_flush_tlb(vcpu);
8783 }
8784
8785
8786 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
8787 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
8788 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
8789 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
8790 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
4704d0be 8791
36be0b9d
PB		 8792 /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */
8793 if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
8794 vmcs_write64(GUEST_BNDCFGS, 0);
8795
44811c02 8796 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
4704d0be 8797 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
44811c02
JK		 8798 vcpu->arch.pat = vmcs12->host_ia32_pat;
8799 }
4704d0be
NHE		 8800 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
8801 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
8802 vmcs12->host_ia32_perf_global_ctrl);
503cd0c5 8803
21feb4eb
ACL		 8804 /* Set L1 segment info according to Intel SDM
8805 27.5.2 Loading Host Segment and Descriptor-Table Registers */
8806 seg = (struct kvm_segment) {
8807 .base = 0,
8808 .limit = 0xFFFFFFFF,
8809 .selector = vmcs12->host_cs_selector,
8810 .type = 11,
8811 .present = 1,
8812 .s = 1,
8813 .g = 1
8814 };
8815 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
8816 seg.l = 1;
8817 else
8818 seg.db = 1;
8819 vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
8820 seg = (struct kvm_segment) {
8821 .base = 0,
8822 .limit = 0xFFFFFFFF,
8823 .type = 3,
8824 .present = 1,
8825 .s = 1,
8826 .db = 1,
8827 .g = 1
8828 };
8829 seg.selector = vmcs12->host_ds_selector;
8830 vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
8831 seg.selector = vmcs12->host_es_selector;
8832 vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
8833 seg.selector = vmcs12->host_ss_selector;
8834 vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
8835 seg.selector = vmcs12->host_fs_selector;
8836 seg.base = vmcs12->host_fs_base;
8837 vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
8838 seg.selector = vmcs12->host_gs_selector;
8839 seg.base = vmcs12->host_gs_base;
8840 vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
8841 seg = (struct kvm_segment) {
205befd9 8842 .base = vmcs12->host_tr_base,
21feb4eb
ACL		 8843 .limit = 0x67,
8844 .selector = vmcs12->host_tr_selector,
8845 .type = 11,
8846 .present = 1
8847 };
8848 vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
8849
503cd0c5
JK		 8850 kvm_set_dr(vcpu, 7, 0x400);
8851 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4704d0be
NHE		 8852}
8853
8854/*
8855 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
8856 * and modify vmcs12 to make it see what it would expect to see there if
8857 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
8858 */
533558bc
JK		 8859static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
8860 u32 exit_intr_info,
8861 unsigned long exit_qualification)
4704d0be
NHE		 8862{
8863 struct vcpu_vmx *vmx = to_vmx(vcpu);
4704d0be
NHE		 8864 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8865
5f3d5799
JK		 8866 /* trying to cancel vmlaunch/vmresume is a bug */
8867 WARN_ON_ONCE(vmx->nested.nested_run_pending);
8868
4704d0be 8869 leave_guest_mode(vcpu);
533558bc
JK		 8870 prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
8871 exit_qualification);
4704d0be 8872
f3380ca5
WL		 8873 vmx_load_vmcs01(vcpu);
8874
77b0f5d6
BD		 8875 if ((exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
8876 && nested_exit_intr_ack_set(vcpu)) {
8877 int irq = kvm_cpu_get_interrupt(vcpu);
8878 WARN_ON(irq < 0);
8879 vmcs12->vm_exit_intr_info = irq |
8880 INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
8881 }
8882
542060ea
JK		 8883 trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
8884 vmcs12->exit_qualification,
8885 vmcs12->idt_vectoring_info_field,
8886 vmcs12->vm_exit_intr_info,
8887 vmcs12->vm_exit_intr_error_code,
8888 KVM_ISA_VMX);
4704d0be 8889
2961e876
GN		 8890 vm_entry_controls_init(vmx, vmcs_read32(VM_ENTRY_CONTROLS));
8891 vm_exit_controls_init(vmx, vmcs_read32(VM_EXIT_CONTROLS));
36c3cc42
JK		 8892 vmx_segment_cache_clear(vmx);
8893
4704d0be
NHE		 8894 /* if no vmcs02 cache requested, remove the one we used */
8895 if (VMCS02_POOL_SIZE == 0)
8896 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
8897
8898 load_vmcs12_host_state(vcpu, vmcs12);
8899
27fc51b2 8900 /* Update TSC_OFFSET if TSC was changed while L2 ran */
4704d0be
NHE		 8901 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
8902
8903 /* This is needed for same reason as it was needed in prepare_vmcs02 */
8904 vmx->host_rsp = 0;
8905
8906 /* Unpin physical memory we referred to in vmcs02 */
8907 if (vmx->nested.apic_access_page) {
8908 nested_release_page(vmx->nested.apic_access_page);
8909 vmx->nested.apic_access_page = 0;
8910 }
8911
8912 /*
8913 * Exiting from L2 to L1, we're now back to L1 which thinks it just
8914 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
8915 * success or failure flag accordingly.
8916 */
8917 if (unlikely(vmx->fail)) {
8918 vmx->fail = 0;
8919 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
8920 } else
8921 nested_vmx_succeed(vcpu);
012f83cb
AG		 8922 if (enable_shadow_vmcs)
8923 vmx->nested.sync_shadow_vmcs = true;
b6b8a145
JK		 8924
8925 /* in case we halted in L2 */
8926 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
4704d0be
NHE		 8927}
8928
42124925
JK		 8929/*
8930 * Forcibly leave nested mode in order to be able to reset the VCPU later on.
8931 */
8932static void vmx_leave_nested(struct kvm_vcpu *vcpu)
8933{
8934 if (is_guest_mode(vcpu))
533558bc 8935 nested_vmx_vmexit(vcpu, -1, 0, 0);
42124925
JK		 8936 free_nested(to_vmx(vcpu));
8937}
8938
7c177938
NHE		 8939/*
8940 * L1's failure to enter L2 is a subset of a normal exit, as explained in
8941 * 23.7 "VM-entry failures during or after loading guest state" (this also
8942 * lists the acceptable exit-reason and exit-qualification parameters).
8943 * It should only be called before L2 actually succeeded to run, and when
8944 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
8945 */
8946static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
8947 struct vmcs12 *vmcs12,
8948 u32 reason, unsigned long qualification)
8949{
8950 load_vmcs12_host_state(vcpu, vmcs12);
8951 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
8952 vmcs12->exit_qualification = qualification;
8953 nested_vmx_succeed(vcpu);
012f83cb
AG		 8954 if (enable_shadow_vmcs)
8955 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
7c177938
NHE		 8956}
8957
8a76d7f2
JR		 8958static int vmx_check_intercept(struct kvm_vcpu *vcpu,
8959 struct x86_instruction_info *info,
8960 enum x86_intercept_stage stage)
8961{
8962 return X86EMUL_CONTINUE;
8963}
8964
ae97a3b8
RK		 8965void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
8966{
b4a2d31d
RK		 8967 if (ple_gap)
8968 shrink_ple_window(vcpu);
ae97a3b8
RK		 8969}
8970
cbdd1bea 8971static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 8972 .cpu_has_kvm_support = cpu_has_kvm_support,
8973 .disabled_by_bios = vmx_disabled_by_bios,
8974 .hardware_setup = hardware_setup,
8975 .hardware_unsetup = hardware_unsetup,
002c7f7c 8976 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 8977 .hardware_enable = hardware_enable,
8978 .hardware_disable = hardware_disable,
04547156 8979 .cpu_has_accelerated_tpr = report_flexpriority,
6aa8b732
AK		 8980
8981 .vcpu_create = vmx_create_vcpu,
8982 .vcpu_free = vmx_free_vcpu,
04d2cc77 8983 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 8984
04d2cc77 8985 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 8986 .vcpu_load = vmx_vcpu_load,
8987 .vcpu_put = vmx_vcpu_put,
8988
c8639010 8989 .update_db_bp_intercept = update_exception_bitmap,
6aa8b732
AK		 8990 .get_msr = vmx_get_msr,
8991 .set_msr = vmx_set_msr,
8992 .get_segment_base = vmx_get_segment_base,
8993 .get_segment = vmx_get_segment,
8994 .set_segment = vmx_set_segment,
2e4d2653 8995 .get_cpl = vmx_get_cpl,
6aa8b732 8996 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 8997 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
aff48baa 8998 .decache_cr3 = vmx_decache_cr3,
25c4c276 8999 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 9000 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 9001 .set_cr3 = vmx_set_cr3,
9002 .set_cr4 = vmx_set_cr4,
6aa8b732 9003 .set_efer = vmx_set_efer,
6aa8b732
AK		 9004 .get_idt = vmx_get_idt,
9005 .set_idt = vmx_set_idt,
9006 .get_gdt = vmx_get_gdt,
9007 .set_gdt = vmx_set_gdt,
73aaf249
JK		 9008 .get_dr6 = vmx_get_dr6,
9009 .set_dr6 = vmx_set_dr6,
020df079 9010 .set_dr7 = vmx_set_dr7,
81908bf4 9011 .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
5fdbf976 9012 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 9013 .get_rflags = vmx_get_rflags,
9014 .set_rflags = vmx_set_rflags,
02daab21 9015 .fpu_deactivate = vmx_fpu_deactivate,
6aa8b732
AK		 9016
9017 .tlb_flush = vmx_flush_tlb,
6aa8b732 9018
6aa8b732 9019 .run = vmx_vcpu_run,
6062d012 9020 .handle_exit = vmx_handle_exit,
6aa8b732 9021 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 9022 .set_interrupt_shadow = vmx_set_interrupt_shadow,
9023 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 9024 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 9025 .set_irq = vmx_inject_irq,
95ba8273 9026 .set_nmi = vmx_inject_nmi,
298101da 9027 .queue_exception = vmx_queue_exception,
b463a6f7 9028 .cancel_injection = vmx_cancel_injection,
78646121 9029 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 9030 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 9031 .get_nmi_mask = vmx_get_nmi_mask,
9032 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 9033 .enable_nmi_window = enable_nmi_window,
9034 .enable_irq_window = enable_irq_window,
9035 .update_cr8_intercept = update_cr8_intercept,
8d14695f 9036 .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
c7c9c56c
YZ		 9037 .vm_has_apicv = vmx_vm_has_apicv,
9038 .load_eoi_exitmap = vmx_load_eoi_exitmap,
9039 .hwapic_irr_update = vmx_hwapic_irr_update,
9040 .hwapic_isr_update = vmx_hwapic_isr_update,
a20ed54d
YZ		 9041 .sync_pir_to_irr = vmx_sync_pir_to_irr,
9042 .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
95ba8273 9043
cbc94022 9044 .set_tss_addr = vmx_set_tss_addr,
67253af5 9045 .get_tdp_level = get_ept_level,
4b12f0de 9046 .get_mt_mask = vmx_get_mt_mask,
229456fc 9047
586f9607 9048 .get_exit_info = vmx_get_exit_info,
586f9607 9049
17cc3935 9050 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY		 9051
9052 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY		 9053
9054 .rdtscp_supported = vmx_rdtscp_supported,
ad756a16 9055 .invpcid_supported = vmx_invpcid_supported,
d4330ef2
JR		 9056
9057 .set_supported_cpuid = vmx_set_supported_cpuid,
f5f48ee1
SY		 9058
9059 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
99e3e30a 9060
4051b188 9061 .set_tsc_khz = vmx_set_tsc_khz,
ba904635 9062 .read_tsc_offset = vmx_read_tsc_offset,
99e3e30a 9063 .write_tsc_offset = vmx_write_tsc_offset,
e48672fa 9064 .adjust_tsc_offset = vmx_adjust_tsc_offset,
857e4099 9065 .compute_tsc_offset = vmx_compute_tsc_offset,
d5c1785d 9066 .read_l1_tsc = vmx_read_l1_tsc,
1c97f0a0
JR		 9067
9068 .set_tdp_cr3 = vmx_set_cr3,
8a76d7f2
JR		 9069
9070 .check_intercept = vmx_check_intercept,
a547c6db 9071 .handle_external_intr = vmx_handle_external_intr,
da8999d3 9072 .mpx_supported = vmx_mpx_supported,
b6b8a145
JK		 9073
9074 .check_nested_events = vmx_check_nested_events,
ae97a3b8
RK		 9075
9076 .sched_in = vmx_sched_in,
6aa8b732
AK		 9077};
9078
9079static int __init vmx_init(void)
9080{
8d14695f 9081 int r, i, msr;
26bb0981
AK		 9082
9083 rdmsrl_safe(MSR_EFER, &host_efer);
9084
03916db9 9085 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
26bb0981 9086 kvm_define_shared_msr(i, vmx_msr_index[i]);
fdef3ad1 9087
3e7c73e9 9088 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 9089 if (!vmx_io_bitmap_a)
9090 return -ENOMEM;
9091
2106a548
GC		 9092 r = -ENOMEM;
9093
3e7c73e9 9094 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 9095 if (!vmx_io_bitmap_b)
fdef3ad1 9096 goto out;
fdef3ad1 9097
5897297b 9098 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 9099 if (!vmx_msr_bitmap_legacy)
25c5f225 9100 goto out1;
2106a548 9101
8d14695f
YZ		 9102 vmx_msr_bitmap_legacy_x2apic =
9103 (unsigned long *)__get_free_page(GFP_KERNEL);
9104 if (!vmx_msr_bitmap_legacy_x2apic)
9105 goto out2;
25c5f225 9106
5897297b 9107 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 9108 if (!vmx_msr_bitmap_longmode)
8d14695f 9109 goto out3;
2106a548 9110
8d14695f
YZ		 9111 vmx_msr_bitmap_longmode_x2apic =
9112 (unsigned long *)__get_free_page(GFP_KERNEL);
9113 if (!vmx_msr_bitmap_longmode_x2apic)
9114 goto out4;
4607c2d7
AG		 9115 vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
9116 if (!vmx_vmread_bitmap)
9117 goto out5;
9118
9119 vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
9120 if (!vmx_vmwrite_bitmap)
9121 goto out6;
9122
9123 memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
9124 memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
5897297b 9125
fdef3ad1
HQ		 9126 /*
9127 * Allow direct access to the PC debug port (it is often used for I/O
9128 * delays, but the vmexits simply slow things down).
9129 */
3e7c73e9
AK		 9130 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
9131 clear_bit(0x80, vmx_io_bitmap_a);
fdef3ad1 9132
3e7c73e9 9133 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
fdef3ad1 9134
5897297b
AK		 9135 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
9136 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
25c5f225 9137
2384d2b3
SY		 9138 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
9139
0ee75bea
AK		 9140 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
9141 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 9142 if (r)
4607c2d7 9143 goto out7;
25c5f225 9144
8f536b76
ZY		 9145#ifdef CONFIG_KEXEC
9146 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
9147 crash_vmclear_local_loaded_vmcss);
9148#endif
9149
5897297b
AK		 9150 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
9151 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
9152 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
9153 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
9154 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
9155 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
da8999d3
LJ		 9156 vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true);
9157
8d14695f
YZ		 9158 memcpy(vmx_msr_bitmap_legacy_x2apic,
9159 vmx_msr_bitmap_legacy, PAGE_SIZE);
9160 memcpy(vmx_msr_bitmap_longmode_x2apic,
9161 vmx_msr_bitmap_longmode, PAGE_SIZE);
9162
01e439be 9163 if (enable_apicv) {
8d14695f
YZ		 9164 for (msr = 0x800; msr <= 0x8ff; msr++)
9165 vmx_disable_intercept_msr_read_x2apic(msr);
9166
9167 /* According SDM, in x2apic mode, the whole id reg is used.
9168 * But in KVM, it only use the highest eight bits. Need to
9169 * intercept it */
9170 vmx_enable_intercept_msr_read_x2apic(0x802);
9171 /* TMCCT */
9172 vmx_enable_intercept_msr_read_x2apic(0x839);
9173 /* TPR */
9174 vmx_disable_intercept_msr_write_x2apic(0x808);
c7c9c56c
YZ		 9175 /* EOI */
9176 vmx_disable_intercept_msr_write_x2apic(0x80b);
9177 /* SELF-IPI */
9178 vmx_disable_intercept_msr_write_x2apic(0x83f);
8d14695f 9179 }
fdef3ad1 9180
089d034e 9181 if (enable_ept) {
3f6d8c8a
XH		 9182 kvm_mmu_set_mask_ptes(0ull,
9183 (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
9184 (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
9185 0ull, VMX_EPT_EXECUTABLE_MASK);
ce88decf 9186 ept_set_mmio_spte_mask();
5fdbcb9d
SY		 9187 kvm_enable_tdp();
9188 } else
9189 kvm_disable_tdp();
1439442c 9190
b4a2d31d
RK		 9191 update_ple_window_actual_max();
9192
fdef3ad1
HQ		 9193 return 0;
9194
4607c2d7
AG		 9195out7:
9196 free_page((unsigned long)vmx_vmwrite_bitmap);
9197out6:
9198 free_page((unsigned long)vmx_vmread_bitmap);
458f212e
YZ		 9199out5:
9200 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
8d14695f 9201out4:
5897297b 9202 free_page((unsigned long)vmx_msr_bitmap_longmode);
8d14695f
YZ		 9203out3:
9204 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
25c5f225 9205out2:
5897297b 9206 free_page((unsigned long)vmx_msr_bitmap_legacy);
fdef3ad1 9207out1:
3e7c73e9 9208 free_page((unsigned long)vmx_io_bitmap_b);
fdef3ad1 9209out:
3e7c73e9 9210 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 9211 return r;
6aa8b732
AK		 9212}
9213
9214static void __exit vmx_exit(void)
9215{
8d14695f
YZ		 9216 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
9217 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
5897297b
AK		 9218 free_page((unsigned long)vmx_msr_bitmap_legacy);
9219 free_page((unsigned long)vmx_msr_bitmap_longmode);
3e7c73e9
AK		 9220 free_page((unsigned long)vmx_io_bitmap_b);
9221 free_page((unsigned long)vmx_io_bitmap_a);
4607c2d7
AG		 9222 free_page((unsigned long)vmx_vmwrite_bitmap);
9223 free_page((unsigned long)vmx_vmread_bitmap);
fdef3ad1 9224
8f536b76 9225#ifdef CONFIG_KEXEC
3b63a43f 9226 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
8f536b76
ZY		 9227 synchronize_rcu();
9228#endif
9229
cb498ea2 9230 kvm_exit();
6aa8b732
AK		 9231}
9232
9233module_init(vmx_init)
9234module_exit(vmx_exit)
ubuntu-bionic-kernel mirror