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KVM: x86: remove unused variable from walk_addr_generic()
[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
9611c187 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
00b27a3e 21#include "cpuid.h"
e495606d 22
edf88417 23#include <linux/kvm_host.h>
6aa8b732 24#include <linux/module.h>
9d8f549d 25#include <linux/kernel.h>
6aa8b732
AK		 26#include <linux/mm.h>
27#include <linux/highmem.h>
e8edc6e0 28#include <linux/sched.h>
c7addb90 29#include <linux/moduleparam.h>
e9bda3b3 30#include <linux/mod_devicetable.h>
229456fc 31#include <linux/ftrace_event.h>
5a0e3ad6 32#include <linux/slab.h>
cafd6659 33#include <linux/tboot.h>
5fdbf976 34#include "kvm_cache_regs.h"
35920a35 35#include "x86.h"
e495606d 36
6aa8b732 37#include <asm/io.h>
3b3be0d1 38#include <asm/desc.h>
13673a90 39#include <asm/vmx.h>
6210e37b 40#include <asm/virtext.h>
a0861c02 41#include <asm/mce.h>
2acf923e
DC		 42#include <asm/i387.h>
43#include <asm/xcr.h>
d7cd9796 44#include <asm/perf_event.h>
8f536b76 45#include <asm/kexec.h>
6aa8b732 46
229456fc
MT		 47#include "trace.h"
48
4ecac3fd 49#define __ex(x) __kvm_handle_fault_on_reboot(x)
5e520e62
AK		 50#define __ex_clear(x, reg) \
51 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
4ecac3fd 52
6aa8b732
AK		 53MODULE_AUTHOR("Qumranet");
54MODULE_LICENSE("GPL");
55
e9bda3b3
JT		 56static const struct x86_cpu_id vmx_cpu_id[] = {
57 X86_FEATURE_MATCH(X86_FEATURE_VMX),
58 {}
59};
60MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
61
476bc001 62static bool __read_mostly enable_vpid = 1;
736caefe 63module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 64
476bc001 65static bool __read_mostly flexpriority_enabled = 1;
736caefe 66module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 67
476bc001 68static bool __read_mostly enable_ept = 1;
736caefe 69module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 70
476bc001 71static bool __read_mostly enable_unrestricted_guest = 1;
3a624e29
NK		 72module_param_named(unrestricted_guest,
73 enable_unrestricted_guest, bool, S_IRUGO);
74
83c3a331
XH		 75static bool __read_mostly enable_ept_ad_bits = 1;
76module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
77
a27685c3 78static bool __read_mostly emulate_invalid_guest_state = true;
c1f8bc04 79module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 80
476bc001 81static bool __read_mostly vmm_exclusive = 1;
b923e62e
DX		 82module_param(vmm_exclusive, bool, S_IRUGO);
83
476bc001 84static bool __read_mostly fasteoi = 1;
58fbbf26
KT		 85module_param(fasteoi, bool, S_IRUGO);
86
801d3424
NHE		 87/*
88 * If nested=1, nested virtualization is supported, i.e., guests may use
89 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
90 * use VMX instructions.
91 */
476bc001 92static bool __read_mostly nested = 0;
801d3424
NHE		 93module_param(nested, bool, S_IRUGO);
94
cdc0e244
AK		 95#define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST \
96 (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
97#define KVM_GUEST_CR0_MASK \
98 (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
99#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST \
81231c69 100 (X86_CR0_WP | X86_CR0_NE)
cdc0e244
AK		 101#define KVM_VM_CR0_ALWAYS_ON \
102 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 103#define KVM_CR4_GUEST_OWNED_BITS \
104 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
105 | X86_CR4_OSXMMEXCPT)
106
cdc0e244
AK		 107#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
108#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
109
78ac8b47
AK		 110#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
111
4b8d54f9
ZE		 112/*
113 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
114 * ple_gap: upper bound on the amount of time between two successive
115 * executions of PAUSE in a loop. Also indicate if ple enabled.
00c25bce 116 * According to test, this time is usually smaller than 128 cycles.
4b8d54f9
ZE		 117 * ple_window: upper bound on the amount of time a guest is allowed to execute
118 * in a PAUSE loop. Tests indicate that most spinlocks are held for
119 * less than 2^12 cycles
120 * Time is measured based on a counter that runs at the same rate as the TSC,
121 * refer SDM volume 3b section 21.6.13 & 22.1.3.
122 */
00c25bce 123#define KVM_VMX_DEFAULT_PLE_GAP 128
4b8d54f9
ZE		 124#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
125static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
126module_param(ple_gap, int, S_IRUGO);
127
128static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
129module_param(ple_window, int, S_IRUGO);
130
83287ea4
AK		 131extern const ulong vmx_return;
132
8bf00a52 133#define NR_AUTOLOAD_MSRS 8
ff2f6fe9 134#define VMCS02_POOL_SIZE 1
61d2ef2c 135
a2fa3e9f
GH		 136struct vmcs {
137 u32 revision_id;
138 u32 abort;
139 char data[0];
140};
141
d462b819
NHE		 142/*
143 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
144 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
145 * loaded on this CPU (so we can clear them if the CPU goes down).
146 */
147struct loaded_vmcs {
148 struct vmcs *vmcs;
149 int cpu;
150 int launched;
151 struct list_head loaded_vmcss_on_cpu_link;
152};
153
26bb0981
AK		 154struct shared_msr_entry {
155 unsigned index;
156 u64 data;
d5696725 157 u64 mask;
26bb0981
AK		 158};
159
a9d30f33
NHE		 160/*
161 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
162 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
163 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
164 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
165 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
166 * More than one of these structures may exist, if L1 runs multiple L2 guests.
167 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
168 * underlying hardware which will be used to run L2.
169 * This structure is packed to ensure that its layout is identical across
170 * machines (necessary for live migration).
171 * If there are changes in this struct, VMCS12_REVISION must be changed.
172 */
22bd0358 173typedef u64 natural_width;
a9d30f33
NHE		 174struct __packed vmcs12 {
175 /* According to the Intel spec, a VMCS region must start with the
176 * following two fields. Then follow implementation-specific data.
177 */
178 u32 revision_id;
179 u32 abort;
22bd0358 180
27d6c865
NHE		 181 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
182 u32 padding[7]; /* room for future expansion */
183
22bd0358
NHE		 184 u64 io_bitmap_a;
185 u64 io_bitmap_b;
186 u64 msr_bitmap;
187 u64 vm_exit_msr_store_addr;
188 u64 vm_exit_msr_load_addr;
189 u64 vm_entry_msr_load_addr;
190 u64 tsc_offset;
191 u64 virtual_apic_page_addr;
192 u64 apic_access_addr;
193 u64 ept_pointer;
194 u64 guest_physical_address;
195 u64 vmcs_link_pointer;
196 u64 guest_ia32_debugctl;
197 u64 guest_ia32_pat;
198 u64 guest_ia32_efer;
199 u64 guest_ia32_perf_global_ctrl;
200 u64 guest_pdptr0;
201 u64 guest_pdptr1;
202 u64 guest_pdptr2;
203 u64 guest_pdptr3;
204 u64 host_ia32_pat;
205 u64 host_ia32_efer;
206 u64 host_ia32_perf_global_ctrl;
207 u64 padding64[8]; /* room for future expansion */
208 /*
209 * To allow migration of L1 (complete with its L2 guests) between
210 * machines of different natural widths (32 or 64 bit), we cannot have
211 * unsigned long fields with no explict size. We use u64 (aliased
212 * natural_width) instead. Luckily, x86 is little-endian.
213 */
214 natural_width cr0_guest_host_mask;
215 natural_width cr4_guest_host_mask;
216 natural_width cr0_read_shadow;
217 natural_width cr4_read_shadow;
218 natural_width cr3_target_value0;
219 natural_width cr3_target_value1;
220 natural_width cr3_target_value2;
221 natural_width cr3_target_value3;
222 natural_width exit_qualification;
223 natural_width guest_linear_address;
224 natural_width guest_cr0;
225 natural_width guest_cr3;
226 natural_width guest_cr4;
227 natural_width guest_es_base;
228 natural_width guest_cs_base;
229 natural_width guest_ss_base;
230 natural_width guest_ds_base;
231 natural_width guest_fs_base;
232 natural_width guest_gs_base;
233 natural_width guest_ldtr_base;
234 natural_width guest_tr_base;
235 natural_width guest_gdtr_base;
236 natural_width guest_idtr_base;
237 natural_width guest_dr7;
238 natural_width guest_rsp;
239 natural_width guest_rip;
240 natural_width guest_rflags;
241 natural_width guest_pending_dbg_exceptions;
242 natural_width guest_sysenter_esp;
243 natural_width guest_sysenter_eip;
244 natural_width host_cr0;
245 natural_width host_cr3;
246 natural_width host_cr4;
247 natural_width host_fs_base;
248 natural_width host_gs_base;
249 natural_width host_tr_base;
250 natural_width host_gdtr_base;
251 natural_width host_idtr_base;
252 natural_width host_ia32_sysenter_esp;
253 natural_width host_ia32_sysenter_eip;
254 natural_width host_rsp;
255 natural_width host_rip;
256 natural_width paddingl[8]; /* room for future expansion */
257 u32 pin_based_vm_exec_control;
258 u32 cpu_based_vm_exec_control;
259 u32 exception_bitmap;
260 u32 page_fault_error_code_mask;
261 u32 page_fault_error_code_match;
262 u32 cr3_target_count;
263 u32 vm_exit_controls;
264 u32 vm_exit_msr_store_count;
265 u32 vm_exit_msr_load_count;
266 u32 vm_entry_controls;
267 u32 vm_entry_msr_load_count;
268 u32 vm_entry_intr_info_field;
269 u32 vm_entry_exception_error_code;
270 u32 vm_entry_instruction_len;
271 u32 tpr_threshold;
272 u32 secondary_vm_exec_control;
273 u32 vm_instruction_error;
274 u32 vm_exit_reason;
275 u32 vm_exit_intr_info;
276 u32 vm_exit_intr_error_code;
277 u32 idt_vectoring_info_field;
278 u32 idt_vectoring_error_code;
279 u32 vm_exit_instruction_len;
280 u32 vmx_instruction_info;
281 u32 guest_es_limit;
282 u32 guest_cs_limit;
283 u32 guest_ss_limit;
284 u32 guest_ds_limit;
285 u32 guest_fs_limit;
286 u32 guest_gs_limit;
287 u32 guest_ldtr_limit;
288 u32 guest_tr_limit;
289 u32 guest_gdtr_limit;
290 u32 guest_idtr_limit;
291 u32 guest_es_ar_bytes;
292 u32 guest_cs_ar_bytes;
293 u32 guest_ss_ar_bytes;
294 u32 guest_ds_ar_bytes;
295 u32 guest_fs_ar_bytes;
296 u32 guest_gs_ar_bytes;
297 u32 guest_ldtr_ar_bytes;
298 u32 guest_tr_ar_bytes;
299 u32 guest_interruptibility_info;
300 u32 guest_activity_state;
301 u32 guest_sysenter_cs;
302 u32 host_ia32_sysenter_cs;
303 u32 padding32[8]; /* room for future expansion */
304 u16 virtual_processor_id;
305 u16 guest_es_selector;
306 u16 guest_cs_selector;
307 u16 guest_ss_selector;
308 u16 guest_ds_selector;
309 u16 guest_fs_selector;
310 u16 guest_gs_selector;
311 u16 guest_ldtr_selector;
312 u16 guest_tr_selector;
313 u16 host_es_selector;
314 u16 host_cs_selector;
315 u16 host_ss_selector;
316 u16 host_ds_selector;
317 u16 host_fs_selector;
318 u16 host_gs_selector;
319 u16 host_tr_selector;
a9d30f33
NHE		 320};
321
322/*
323 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
324 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
325 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
326 */
327#define VMCS12_REVISION 0x11e57ed0
328
329/*
330 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
331 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
332 * current implementation, 4K are reserved to avoid future complications.
333 */
334#define VMCS12_SIZE 0x1000
335
ff2f6fe9
NHE		 336/* Used to remember the last vmcs02 used for some recently used vmcs12s */
337struct vmcs02_list {
338 struct list_head list;
339 gpa_t vmptr;
340 struct loaded_vmcs vmcs02;
341};
342
ec378aee
NHE		 343/*
344 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
345 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
346 */
347struct nested_vmx {
348 /* Has the level1 guest done vmxon? */
349 bool vmxon;
a9d30f33
NHE		 350
351 /* The guest-physical address of the current VMCS L1 keeps for L2 */
352 gpa_t current_vmptr;
353 /* The host-usable pointer to the above */
354 struct page *current_vmcs12_page;
355 struct vmcs12 *current_vmcs12;
ff2f6fe9
NHE		 356
357 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
358 struct list_head vmcs02_pool;
359 int vmcs02_num;
fe3ef05c 360 u64 vmcs01_tsc_offset;
644d711a
NHE		 361 /* L2 must run next, and mustn't decide to exit to L1. */
362 bool nested_run_pending;
fe3ef05c
NHE		 363 /*
364 * Guest pages referred to in vmcs02 with host-physical pointers, so
365 * we must keep them pinned while L2 runs.
366 */
367 struct page *apic_access_page;
ec378aee
NHE		 368};
369
a2fa3e9f 370struct vcpu_vmx {
fb3f0f51 371 struct kvm_vcpu vcpu;
313dbd49 372 unsigned long host_rsp;
29bd8a78 373 u8 fail;
69c73028 374 u8 cpl;
9d58b931 375 bool nmi_known_unmasked;
51aa01d1 376 u32 exit_intr_info;
1155f76a 377 u32 idt_vectoring_info;
6de12732 378 ulong rflags;
26bb0981 379 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH		 380 int nmsrs;
381 int save_nmsrs;
a2fa3e9f 382#ifdef CONFIG_X86_64
44ea2b17
AK		 383 u64 msr_host_kernel_gs_base;
384 u64 msr_guest_kernel_gs_base;
a2fa3e9f 385#endif
d462b819
NHE		 386 /*
387 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
388 * non-nested (L1) guest, it always points to vmcs01. For a nested
389 * guest (L2), it points to a different VMCS.
390 */
391 struct loaded_vmcs vmcs01;
392 struct loaded_vmcs *loaded_vmcs;
393 bool __launched; /* temporary, used in vmx_vcpu_run */
61d2ef2c
AK		 394 struct msr_autoload {
395 unsigned nr;
396 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
397 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
398 } msr_autoload;
a2fa3e9f
GH		 399 struct {
400 int loaded;
401 u16 fs_sel, gs_sel, ldt_sel;
b2da15ac
AK		 402#ifdef CONFIG_X86_64
403 u16 ds_sel, es_sel;
404#endif
152d3f2f
LV		 405 int gs_ldt_reload_needed;
406 int fs_reload_needed;
d77c26fc 407 } host_state;
9c8cba37 408 struct {
7ffd92c5 409 int vm86_active;
78ac8b47 410 ulong save_rflags;
f5f7b2fe
AK		 411 struct kvm_segment segs[8];
412 } rmode;
413 struct {
414 u32 bitmask; /* 4 bits per segment (1 bit per field) */
7ffd92c5
AK		 415 struct kvm_save_segment {
416 u16 selector;
417 unsigned long base;
418 u32 limit;
419 u32 ar;
f5f7b2fe 420 } seg[8];
2fb92db1 421 } segment_cache;
2384d2b3 422 int vpid;
04fa4d32 423 bool emulation_required;
3b86cd99
JK		 424
425 /* Support for vnmi-less CPUs */
426 int soft_vnmi_blocked;
427 ktime_t entry_time;
428 s64 vnmi_blocked_time;
a0861c02 429 u32 exit_reason;
4e47c7a6
SY		 430
431 bool rdtscp_enabled;
ec378aee
NHE		 432
433 /* Support for a guest hypervisor (nested VMX) */
434 struct nested_vmx nested;
a2fa3e9f
GH		 435};
436
2fb92db1
AK		 437enum segment_cache_field {
438 SEG_FIELD_SEL = 0,
439 SEG_FIELD_BASE = 1,
440 SEG_FIELD_LIMIT = 2,
441 SEG_FIELD_AR = 3,
442
443 SEG_FIELD_NR = 4
444};
445
a2fa3e9f
GH		 446static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
447{
fb3f0f51 448 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 449}
450
22bd0358
NHE		 451#define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
452#define FIELD(number, name) [number] = VMCS12_OFFSET(name)
453#define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
454 [number##_HIGH] = VMCS12_OFFSET(name)+4
455
772e0318 456static const unsigned short vmcs_field_to_offset_table[] = {
22bd0358
NHE		 457 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
458 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
459 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
460 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
461 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
462 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
463 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
464 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
465 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
466 FIELD(HOST_ES_SELECTOR, host_es_selector),
467 FIELD(HOST_CS_SELECTOR, host_cs_selector),
468 FIELD(HOST_SS_SELECTOR, host_ss_selector),
469 FIELD(HOST_DS_SELECTOR, host_ds_selector),
470 FIELD(HOST_FS_SELECTOR, host_fs_selector),
471 FIELD(HOST_GS_SELECTOR, host_gs_selector),
472 FIELD(HOST_TR_SELECTOR, host_tr_selector),
473 FIELD64(IO_BITMAP_A, io_bitmap_a),
474 FIELD64(IO_BITMAP_B, io_bitmap_b),
475 FIELD64(MSR_BITMAP, msr_bitmap),
476 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
477 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
478 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
479 FIELD64(TSC_OFFSET, tsc_offset),
480 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
481 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
482 FIELD64(EPT_POINTER, ept_pointer),
483 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
484 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
485 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
486 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
487 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
488 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
489 FIELD64(GUEST_PDPTR0, guest_pdptr0),
490 FIELD64(GUEST_PDPTR1, guest_pdptr1),
491 FIELD64(GUEST_PDPTR2, guest_pdptr2),
492 FIELD64(GUEST_PDPTR3, guest_pdptr3),
493 FIELD64(HOST_IA32_PAT, host_ia32_pat),
494 FIELD64(HOST_IA32_EFER, host_ia32_efer),
495 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
496 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
497 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
498 FIELD(EXCEPTION_BITMAP, exception_bitmap),
499 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
500 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
501 FIELD(CR3_TARGET_COUNT, cr3_target_count),
502 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
503 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
504 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
505 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
506 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
507 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
508 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
509 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
510 FIELD(TPR_THRESHOLD, tpr_threshold),
511 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
512 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
513 FIELD(VM_EXIT_REASON, vm_exit_reason),
514 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
515 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
516 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
517 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
518 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
519 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
520 FIELD(GUEST_ES_LIMIT, guest_es_limit),
521 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
522 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
523 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
524 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
525 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
526 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
527 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
528 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
529 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
530 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
531 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
532 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
533 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
534 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
535 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
536 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
537 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
538 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
539 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
540 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
541 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
542 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
543 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
544 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
545 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
546 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
547 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
548 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
549 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
550 FIELD(EXIT_QUALIFICATION, exit_qualification),
551 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
552 FIELD(GUEST_CR0, guest_cr0),
553 FIELD(GUEST_CR3, guest_cr3),
554 FIELD(GUEST_CR4, guest_cr4),
555 FIELD(GUEST_ES_BASE, guest_es_base),
556 FIELD(GUEST_CS_BASE, guest_cs_base),
557 FIELD(GUEST_SS_BASE, guest_ss_base),
558 FIELD(GUEST_DS_BASE, guest_ds_base),
559 FIELD(GUEST_FS_BASE, guest_fs_base),
560 FIELD(GUEST_GS_BASE, guest_gs_base),
561 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
562 FIELD(GUEST_TR_BASE, guest_tr_base),
563 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
564 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
565 FIELD(GUEST_DR7, guest_dr7),
566 FIELD(GUEST_RSP, guest_rsp),
567 FIELD(GUEST_RIP, guest_rip),
568 FIELD(GUEST_RFLAGS, guest_rflags),
569 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
570 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
571 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
572 FIELD(HOST_CR0, host_cr0),
573 FIELD(HOST_CR3, host_cr3),
574 FIELD(HOST_CR4, host_cr4),
575 FIELD(HOST_FS_BASE, host_fs_base),
576 FIELD(HOST_GS_BASE, host_gs_base),
577 FIELD(HOST_TR_BASE, host_tr_base),
578 FIELD(HOST_GDTR_BASE, host_gdtr_base),
579 FIELD(HOST_IDTR_BASE, host_idtr_base),
580 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
581 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
582 FIELD(HOST_RSP, host_rsp),
583 FIELD(HOST_RIP, host_rip),
584};
585static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
586
587static inline short vmcs_field_to_offset(unsigned long field)
588{
589 if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
590 return -1;
591 return vmcs_field_to_offset_table[field];
592}
593
a9d30f33
NHE		 594static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
595{
596 return to_vmx(vcpu)->nested.current_vmcs12;
597}
598
599static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
600{
601 struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
32cad84f 602 if (is_error_page(page))
a9d30f33 603 return NULL;
32cad84f 604
a9d30f33
NHE		 605 return page;
606}
607
608static void nested_release_page(struct page *page)
609{
610 kvm_release_page_dirty(page);
611}
612
613static void nested_release_page_clean(struct page *page)
614{
615 kvm_release_page_clean(page);
616}
617
4e1096d2 618static u64 construct_eptp(unsigned long root_hpa);
4610c9cc
DX		 619static void kvm_cpu_vmxon(u64 addr);
620static void kvm_cpu_vmxoff(void);
aff48baa 621static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
776e58ea 622static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
b246dd5d
OW		 623static void vmx_set_segment(struct kvm_vcpu *vcpu,
624 struct kvm_segment *var, int seg);
625static void vmx_get_segment(struct kvm_vcpu *vcpu,
626 struct kvm_segment *var, int seg);
d99e4152
GN		 627static bool guest_state_valid(struct kvm_vcpu *vcpu);
628static u32 vmx_segment_access_rights(struct kvm_segment *var);
75880a01 629
6aa8b732
AK		 630static DEFINE_PER_CPU(struct vmcs *, vmxarea);
631static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
d462b819
NHE		 632/*
633 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
634 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
635 */
636static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
3444d7da 637static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
6aa8b732 638
3e7c73e9
AK		 639static unsigned long *vmx_io_bitmap_a;
640static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 641static unsigned long *vmx_msr_bitmap_legacy;
642static unsigned long *vmx_msr_bitmap_longmode;
fdef3ad1 643
110312c8 644static bool cpu_has_load_ia32_efer;
8bf00a52 645static bool cpu_has_load_perf_global_ctrl;
110312c8 646
2384d2b3
SY		 647static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
648static DEFINE_SPINLOCK(vmx_vpid_lock);
649
1c3d14fe 650static struct vmcs_config {
6aa8b732
AK		 651 int size;
652 int order;
653 u32 revision_id;
1c3d14fe
YS		 654 u32 pin_based_exec_ctrl;
655 u32 cpu_based_exec_ctrl;
f78e0e2e 656 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 657 u32 vmexit_ctrl;
658 u32 vmentry_ctrl;
659} vmcs_config;
6aa8b732 660
efff9e53 661static struct vmx_capability {
d56f546d
SY		 662 u32 ept;
663 u32 vpid;
664} vmx_capability;
665
6aa8b732
AK		 666#define VMX_SEGMENT_FIELD(seg) \
667 [VCPU_SREG_##seg] = { \
668 .selector = GUEST_##seg##_SELECTOR, \
669 .base = GUEST_##seg##_BASE, \
670 .limit = GUEST_##seg##_LIMIT, \
671 .ar_bytes = GUEST_##seg##_AR_BYTES, \
672 }
673
772e0318 674static const struct kvm_vmx_segment_field {
6aa8b732
AK		 675 unsigned selector;
676 unsigned base;
677 unsigned limit;
678 unsigned ar_bytes;
679} kvm_vmx_segment_fields[] = {
680 VMX_SEGMENT_FIELD(CS),
681 VMX_SEGMENT_FIELD(DS),
682 VMX_SEGMENT_FIELD(ES),
683 VMX_SEGMENT_FIELD(FS),
684 VMX_SEGMENT_FIELD(GS),
685 VMX_SEGMENT_FIELD(SS),
686 VMX_SEGMENT_FIELD(TR),
687 VMX_SEGMENT_FIELD(LDTR),
688};
689
26bb0981
AK		 690static u64 host_efer;
691
6de4f3ad
AK		 692static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
693
4d56c8a7 694/*
8c06585d 695 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
4d56c8a7
AK		 696 * away by decrementing the array size.
697 */
6aa8b732 698static const u32 vmx_msr_index[] = {
05b3e0c2 699#ifdef CONFIG_X86_64
44ea2b17 700 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 701#endif
8c06585d 702 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
6aa8b732 703};
9d8f549d 704#define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
6aa8b732 705
31299944 706static inline bool is_page_fault(u32 intr_info)
6aa8b732
AK		 707{
708 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
709 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 710 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 711}
712
31299944 713static inline bool is_no_device(u32 intr_info)
2ab455cc
AL		 714{
715 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
716 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 717 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 718}
719
31299944 720static inline bool is_invalid_opcode(u32 intr_info)
7aa81cc0
AL		 721{
722 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
723 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 724 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 725}
726
31299944 727static inline bool is_external_interrupt(u32 intr_info)
6aa8b732
AK		 728{
729 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
730 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
731}
732
31299944 733static inline bool is_machine_check(u32 intr_info)
a0861c02
AK		 734{
735 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
736 INTR_INFO_VALID_MASK)) ==
737 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
738}
739
31299944 740static inline bool cpu_has_vmx_msr_bitmap(void)
25c5f225 741{
04547156 742 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 743}
744
31299944 745static inline bool cpu_has_vmx_tpr_shadow(void)
6e5d865c 746{
04547156 747 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 748}
749
31299944 750static inline bool vm_need_tpr_shadow(struct kvm *kvm)
6e5d865c 751{
04547156 752 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
6e5d865c
YS		 753}
754
31299944 755static inline bool cpu_has_secondary_exec_ctrls(void)
f78e0e2e 756{
04547156
SY		 757 return vmcs_config.cpu_based_exec_ctrl &
758 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 759}
760
774ead3a 761static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 762{
04547156
SY		 763 return vmcs_config.cpu_based_2nd_exec_ctrl &
764 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
765}
766
767static inline bool cpu_has_vmx_flexpriority(void)
768{
769 return cpu_has_vmx_tpr_shadow() &&
770 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 771}
772
e799794e
MT		 773static inline bool cpu_has_vmx_ept_execute_only(void)
774{
31299944 775 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
e799794e
MT		 776}
777
778static inline bool cpu_has_vmx_eptp_uncacheable(void)
779{
31299944 780 return vmx_capability.ept & VMX_EPTP_UC_BIT;
e799794e
MT		 781}
782
783static inline bool cpu_has_vmx_eptp_writeback(void)
784{
31299944 785 return vmx_capability.ept & VMX_EPTP_WB_BIT;
e799794e
MT		 786}
787
788static inline bool cpu_has_vmx_ept_2m_page(void)
789{
31299944 790 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
e799794e
MT		 791}
792
878403b7
SY		 793static inline bool cpu_has_vmx_ept_1g_page(void)
794{
31299944 795 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
878403b7
SY		 796}
797
4bc9b982
SY		 798static inline bool cpu_has_vmx_ept_4levels(void)
799{
800 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
801}
802
83c3a331
XH		 803static inline bool cpu_has_vmx_ept_ad_bits(void)
804{
805 return vmx_capability.ept & VMX_EPT_AD_BIT;
806}
807
31299944 808static inline bool cpu_has_vmx_invept_context(void)
d56f546d 809{
31299944 810 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
d56f546d
SY		 811}
812
31299944 813static inline bool cpu_has_vmx_invept_global(void)
d56f546d 814{
31299944 815 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
d56f546d
SY		 816}
817
518c8aee
GJ		 818static inline bool cpu_has_vmx_invvpid_single(void)
819{
820 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
821}
822
b9d762fa
GJ		 823static inline bool cpu_has_vmx_invvpid_global(void)
824{
825 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
826}
827
31299944 828static inline bool cpu_has_vmx_ept(void)
d56f546d 829{
04547156
SY		 830 return vmcs_config.cpu_based_2nd_exec_ctrl &
831 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 832}
833
31299944 834static inline bool cpu_has_vmx_unrestricted_guest(void)
3a624e29
NK		 835{
836 return vmcs_config.cpu_based_2nd_exec_ctrl &
837 SECONDARY_EXEC_UNRESTRICTED_GUEST;
838}
839
31299944 840static inline bool cpu_has_vmx_ple(void)
4b8d54f9
ZE		 841{
842 return vmcs_config.cpu_based_2nd_exec_ctrl &
843 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
844}
845
31299944 846static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
f78e0e2e 847{
6d3e435e 848 return flexpriority_enabled && irqchip_in_kernel(kvm);
f78e0e2e
SY		 849}
850
31299944 851static inline bool cpu_has_vmx_vpid(void)
2384d2b3 852{
04547156
SY		 853 return vmcs_config.cpu_based_2nd_exec_ctrl &
854 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 855}
856
31299944 857static inline bool cpu_has_vmx_rdtscp(void)
4e47c7a6
SY		 858{
859 return vmcs_config.cpu_based_2nd_exec_ctrl &
860 SECONDARY_EXEC_RDTSCP;
861}
862
ad756a16
MJ		 863static inline bool cpu_has_vmx_invpcid(void)
864{
865 return vmcs_config.cpu_based_2nd_exec_ctrl &
866 SECONDARY_EXEC_ENABLE_INVPCID;
867}
868
31299944 869static inline bool cpu_has_virtual_nmis(void)
f08864b4
SY		 870{
871 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
872}
873
f5f48ee1
SY		 874static inline bool cpu_has_vmx_wbinvd_exit(void)
875{
876 return vmcs_config.cpu_based_2nd_exec_ctrl &
877 SECONDARY_EXEC_WBINVD_EXITING;
878}
879
04547156
SY		 880static inline bool report_flexpriority(void)
881{
882 return flexpriority_enabled;
883}
884
fe3ef05c
NHE		 885static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
886{
887 return vmcs12->cpu_based_vm_exec_control & bit;
888}
889
890static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
891{
892 return (vmcs12->cpu_based_vm_exec_control &
893 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
894 (vmcs12->secondary_vm_exec_control & bit);
895}
896
644d711a
NHE		 897static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12,
898 struct kvm_vcpu *vcpu)
899{
900 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
901}
902
903static inline bool is_exception(u32 intr_info)
904{
905 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
906 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
907}
908
909static void nested_vmx_vmexit(struct kvm_vcpu *vcpu);
7c177938
NHE		 910static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
911 struct vmcs12 *vmcs12,
912 u32 reason, unsigned long qualification);
913
8b9cf98c 914static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 915{
916 int i;
917
a2fa3e9f 918 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 919 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 920 return i;
921 return -1;
922}
923
2384d2b3
SY		 924static inline void __invvpid(int ext, u16 vpid, gva_t gva)
925{
926 struct {
927 u64 vpid : 16;
928 u64 rsvd : 48;
929 u64 gva;
930 } operand = { vpid, 0, gva };
931
4ecac3fd 932 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 933 /* CF==1 or ZF==1 --> rc = -1 */
934 "; ja 1f ; ud2 ; 1:"
935 : : "a"(&operand), "c"(ext) : "cc", "memory");
936}
937
1439442c
SY		 938static inline void __invept(int ext, u64 eptp, gpa_t gpa)
939{
940 struct {
941 u64 eptp, gpa;
942 } operand = {eptp, gpa};
943
4ecac3fd 944 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 945 /* CF==1 or ZF==1 --> rc = -1 */
946 "; ja 1f ; ud2 ; 1:\n"
947 : : "a" (&operand), "c" (ext) : "cc", "memory");
948}
949
26bb0981 950static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 951{
952 int i;
953
8b9cf98c 954 i = __find_msr_index(vmx, msr);
a75beee6 955 if (i >= 0)
a2fa3e9f 956 return &vmx->guest_msrs[i];
8b6d44c7 957 return NULL;
7725f0ba
AK		 958}
959
6aa8b732
AK		 960static void vmcs_clear(struct vmcs *vmcs)
961{
962 u64 phys_addr = __pa(vmcs);
963 u8 error;
964
4ecac3fd 965 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
16d8f72f 966 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
6aa8b732
AK		 967 : "cc", "memory");
968 if (error)
969 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
970 vmcs, phys_addr);
971}
972
d462b819
NHE		 973static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
974{
975 vmcs_clear(loaded_vmcs->vmcs);
976 loaded_vmcs->cpu = -1;
977 loaded_vmcs->launched = 0;
978}
979
7725b894
DX		 980static void vmcs_load(struct vmcs *vmcs)
981{
982 u64 phys_addr = __pa(vmcs);
983 u8 error;
984
985 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
16d8f72f 986 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
7725b894
DX		 987 : "cc", "memory");
988 if (error)
2844d849 989 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
7725b894
DX		 990 vmcs, phys_addr);
991}
992
8f536b76
ZY		 993#ifdef CONFIG_KEXEC
994/*
995 * This bitmap is used to indicate whether the vmclear
996 * operation is enabled on all cpus. All disabled by
997 * default.
998 */
999static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1000
1001static inline void crash_enable_local_vmclear(int cpu)
1002{
1003 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1004}
1005
1006static inline void crash_disable_local_vmclear(int cpu)
1007{
1008 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1009}
1010
1011static inline int crash_local_vmclear_enabled(int cpu)
1012{
1013 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1014}
1015
1016static void crash_vmclear_local_loaded_vmcss(void)
1017{
1018 int cpu = raw_smp_processor_id();
1019 struct loaded_vmcs *v;
1020
1021 if (!crash_local_vmclear_enabled(cpu))
1022 return;
1023
1024 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1025 loaded_vmcss_on_cpu_link)
1026 vmcs_clear(v->vmcs);
1027}
1028#else
1029static inline void crash_enable_local_vmclear(int cpu) { }
1030static inline void crash_disable_local_vmclear(int cpu) { }
1031#endif /* CONFIG_KEXEC */
1032
d462b819 1033static void __loaded_vmcs_clear(void *arg)
6aa8b732 1034{
d462b819 1035 struct loaded_vmcs *loaded_vmcs = arg;
d3b2c338 1036 int cpu = raw_smp_processor_id();
6aa8b732 1037
d462b819
NHE		 1038 if (loaded_vmcs->cpu != cpu)
1039 return; /* vcpu migration can race with cpu offline */
1040 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
6aa8b732 1041 per_cpu(current_vmcs, cpu) = NULL;
8f536b76 1042 crash_disable_local_vmclear(cpu);
d462b819 1043 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
5a560f8b
XG		 1044
1045 /*
1046 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1047 * is before setting loaded_vmcs->vcpu to -1 which is done in
1048 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1049 * then adds the vmcs into percpu list before it is deleted.
1050 */
1051 smp_wmb();
1052
d462b819 1053 loaded_vmcs_init(loaded_vmcs);
8f536b76 1054 crash_enable_local_vmclear(cpu);
6aa8b732
AK		 1055}
1056
d462b819 1057static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
8d0be2b3 1058{
e6c7d321
XG		 1059 int cpu = loaded_vmcs->cpu;
1060
1061 if (cpu != -1)
1062 smp_call_function_single(cpu,
1063 __loaded_vmcs_clear, loaded_vmcs, 1);
8d0be2b3
AK		 1064}
1065
1760dd49 1066static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
2384d2b3
SY		 1067{
1068 if (vmx->vpid == 0)
1069 return;
1070
518c8aee
GJ		 1071 if (cpu_has_vmx_invvpid_single())
1072 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
2384d2b3
SY		 1073}
1074
b9d762fa
GJ		 1075static inline void vpid_sync_vcpu_global(void)
1076{
1077 if (cpu_has_vmx_invvpid_global())
1078 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1079}
1080
1081static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1082{
1083 if (cpu_has_vmx_invvpid_single())
1760dd49 1084 vpid_sync_vcpu_single(vmx);
b9d762fa
GJ		 1085 else
1086 vpid_sync_vcpu_global();
1087}
1088
1439442c
SY		 1089static inline void ept_sync_global(void)
1090{
1091 if (cpu_has_vmx_invept_global())
1092 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1093}
1094
1095static inline void ept_sync_context(u64 eptp)
1096{
089d034e 1097 if (enable_ept) {
1439442c
SY		 1098 if (cpu_has_vmx_invept_context())
1099 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1100 else
1101 ept_sync_global();
1102 }
1103}
1104
96304217 1105static __always_inline unsigned long vmcs_readl(unsigned long field)
6aa8b732 1106{
5e520e62 1107 unsigned long value;
6aa8b732 1108
5e520e62
AK		 1109 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1110 : "=a"(value) : "d"(field) : "cc");
6aa8b732
AK		 1111 return value;
1112}
1113
96304217 1114static __always_inline u16 vmcs_read16(unsigned long field)
6aa8b732
AK		 1115{
1116 return vmcs_readl(field);
1117}
1118
96304217 1119static __always_inline u32 vmcs_read32(unsigned long field)
6aa8b732
AK		 1120{
1121 return vmcs_readl(field);
1122}
1123
96304217 1124static __always_inline u64 vmcs_read64(unsigned long field)
6aa8b732 1125{
05b3e0c2 1126#ifdef CONFIG_X86_64
6aa8b732
AK		 1127 return vmcs_readl(field);
1128#else
1129 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1130#endif
1131}
1132
e52de1b8
AK		 1133static noinline void vmwrite_error(unsigned long field, unsigned long value)
1134{
1135 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1136 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1137 dump_stack();
1138}
1139
6aa8b732
AK		 1140static void vmcs_writel(unsigned long field, unsigned long value)
1141{
1142 u8 error;
1143
4ecac3fd 1144 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 1145 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 1146 if (unlikely(error))
1147 vmwrite_error(field, value);
6aa8b732
AK		 1148}
1149
1150static void vmcs_write16(unsigned long field, u16 value)
1151{
1152 vmcs_writel(field, value);
1153}
1154
1155static void vmcs_write32(unsigned long field, u32 value)
1156{
1157 vmcs_writel(field, value);
1158}
1159
1160static void vmcs_write64(unsigned long field, u64 value)
1161{
6aa8b732 1162 vmcs_writel(field, value);
7682f2d0 1163#ifndef CONFIG_X86_64
6aa8b732
AK		 1164 asm volatile ("");
1165 vmcs_writel(field+1, value >> 32);
1166#endif
1167}
1168
2ab455cc
AL		 1169static void vmcs_clear_bits(unsigned long field, u32 mask)
1170{
1171 vmcs_writel(field, vmcs_readl(field) & ~mask);
1172}
1173
1174static void vmcs_set_bits(unsigned long field, u32 mask)
1175{
1176 vmcs_writel(field, vmcs_readl(field) | mask);
1177}
1178
2fb92db1
AK		 1179static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1180{
1181 vmx->segment_cache.bitmask = 0;
1182}
1183
1184static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1185 unsigned field)
1186{
1187 bool ret;
1188 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1189
1190 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1191 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1192 vmx->segment_cache.bitmask = 0;
1193 }
1194 ret = vmx->segment_cache.bitmask & mask;
1195 vmx->segment_cache.bitmask |= mask;
1196 return ret;
1197}
1198
1199static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1200{
1201 u16 *p = &vmx->segment_cache.seg[seg].selector;
1202
1203 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1204 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1205 return *p;
1206}
1207
1208static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1209{
1210 ulong *p = &vmx->segment_cache.seg[seg].base;
1211
1212 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1213 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1214 return *p;
1215}
1216
1217static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1218{
1219 u32 *p = &vmx->segment_cache.seg[seg].limit;
1220
1221 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1222 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1223 return *p;
1224}
1225
1226static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1227{
1228 u32 *p = &vmx->segment_cache.seg[seg].ar;
1229
1230 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1231 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1232 return *p;
1233}
1234
abd3f2d6
AK		 1235static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1236{
1237 u32 eb;
1238
fd7373cc
JK		 1239 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1240 (1u << NM_VECTOR) | (1u << DB_VECTOR);
1241 if ((vcpu->guest_debug &
1242 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1243 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1244 eb |= 1u << BP_VECTOR;
7ffd92c5 1245 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 1246 eb = ~0;
089d034e 1247 if (enable_ept)
1439442c 1248 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
02daab21
AK		 1249 if (vcpu->fpu_active)
1250 eb &= ~(1u << NM_VECTOR);
36cf24e0
NHE		 1251
1252 /* When we are running a nested L2 guest and L1 specified for it a
1253 * certain exception bitmap, we must trap the same exceptions and pass
1254 * them to L1. When running L2, we will only handle the exceptions
1255 * specified above if L1 did not want them.
1256 */
1257 if (is_guest_mode(vcpu))
1258 eb |= get_vmcs12(vcpu)->exception_bitmap;
1259
abd3f2d6
AK		 1260 vmcs_write32(EXCEPTION_BITMAP, eb);
1261}
1262
8bf00a52
GN		 1263static void clear_atomic_switch_msr_special(unsigned long entry,
1264 unsigned long exit)
1265{
1266 vmcs_clear_bits(VM_ENTRY_CONTROLS, entry);
1267 vmcs_clear_bits(VM_EXIT_CONTROLS, exit);
1268}
1269
61d2ef2c
AK		 1270static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1271{
1272 unsigned i;
1273 struct msr_autoload *m = &vmx->msr_autoload;
1274
8bf00a52
GN		 1275 switch (msr) {
1276 case MSR_EFER:
1277 if (cpu_has_load_ia32_efer) {
1278 clear_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1279 VM_EXIT_LOAD_IA32_EFER);
1280 return;
1281 }
1282 break;
1283 case MSR_CORE_PERF_GLOBAL_CTRL:
1284 if (cpu_has_load_perf_global_ctrl) {
1285 clear_atomic_switch_msr_special(
1286 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1287 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1288 return;
1289 }
1290 break;
110312c8
AK		 1291 }
1292
61d2ef2c
AK		 1293 for (i = 0; i < m->nr; ++i)
1294 if (m->guest[i].index == msr)
1295 break;
1296
1297 if (i == m->nr)
1298 return;
1299 --m->nr;
1300 m->guest[i] = m->guest[m->nr];
1301 m->host[i] = m->host[m->nr];
1302 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1303 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1304}
1305
8bf00a52
GN		 1306static void add_atomic_switch_msr_special(unsigned long entry,
1307 unsigned long exit, unsigned long guest_val_vmcs,
1308 unsigned long host_val_vmcs, u64 guest_val, u64 host_val)
1309{
1310 vmcs_write64(guest_val_vmcs, guest_val);
1311 vmcs_write64(host_val_vmcs, host_val);
1312 vmcs_set_bits(VM_ENTRY_CONTROLS, entry);
1313 vmcs_set_bits(VM_EXIT_CONTROLS, exit);
1314}
1315
61d2ef2c
AK		 1316static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1317 u64 guest_val, u64 host_val)
1318{
1319 unsigned i;
1320 struct msr_autoload *m = &vmx->msr_autoload;
1321
8bf00a52
GN		 1322 switch (msr) {
1323 case MSR_EFER:
1324 if (cpu_has_load_ia32_efer) {
1325 add_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1326 VM_EXIT_LOAD_IA32_EFER,
1327 GUEST_IA32_EFER,
1328 HOST_IA32_EFER,
1329 guest_val, host_val);
1330 return;
1331 }
1332 break;
1333 case MSR_CORE_PERF_GLOBAL_CTRL:
1334 if (cpu_has_load_perf_global_ctrl) {
1335 add_atomic_switch_msr_special(
1336 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1337 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1338 GUEST_IA32_PERF_GLOBAL_CTRL,
1339 HOST_IA32_PERF_GLOBAL_CTRL,
1340 guest_val, host_val);
1341 return;
1342 }
1343 break;
110312c8
AK		 1344 }
1345
61d2ef2c
AK		 1346 for (i = 0; i < m->nr; ++i)
1347 if (m->guest[i].index == msr)
1348 break;
1349
e7fc6f93
GN		 1350 if (i == NR_AUTOLOAD_MSRS) {
1351 printk_once(KERN_WARNING"Not enough mst switch entries. "
1352 "Can't add msr %x\n", msr);
1353 return;
1354 } else if (i == m->nr) {
61d2ef2c
AK		 1355 ++m->nr;
1356 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1357 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1358 }
1359
1360 m->guest[i].index = msr;
1361 m->guest[i].value = guest_val;
1362 m->host[i].index = msr;
1363 m->host[i].value = host_val;
1364}
1365
33ed6329
AK		 1366static void reload_tss(void)
1367{
33ed6329
AK		 1368 /*
1369 * VT restores TR but not its size. Useless.
1370 */
d359192f 1371 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
a5f61300 1372 struct desc_struct *descs;
33ed6329 1373
d359192f 1374 descs = (void *)gdt->address;
33ed6329
AK		 1375 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1376 load_TR_desc();
33ed6329
AK		 1377}
1378
92c0d900 1379static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 1380{
3a34a881 1381 u64 guest_efer;
51c6cf66
AK		 1382 u64 ignore_bits;
1383
f6801dff 1384 guest_efer = vmx->vcpu.arch.efer;
3a34a881 1385
51c6cf66 1386 /*
0fa06071 1387 * NX is emulated; LMA and LME handled by hardware; SCE meaningless
51c6cf66
AK		 1388 * outside long mode
1389 */
1390 ignore_bits = EFER_NX | EFER_SCE;
1391#ifdef CONFIG_X86_64
1392 ignore_bits |= EFER_LMA | EFER_LME;
1393 /* SCE is meaningful only in long mode on Intel */
1394 if (guest_efer & EFER_LMA)
1395 ignore_bits &= ~(u64)EFER_SCE;
1396#endif
51c6cf66
AK		 1397 guest_efer &= ~ignore_bits;
1398 guest_efer |= host_efer & ignore_bits;
26bb0981 1399 vmx->guest_msrs[efer_offset].data = guest_efer;
d5696725 1400 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef
AK		 1401
1402 clear_atomic_switch_msr(vmx, MSR_EFER);
1403 /* On ept, can't emulate nx, and must switch nx atomically */
1404 if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1405 guest_efer = vmx->vcpu.arch.efer;
1406 if (!(guest_efer & EFER_LMA))
1407 guest_efer &= ~EFER_LME;
1408 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1409 return false;
1410 }
1411
26bb0981 1412 return true;
51c6cf66
AK		 1413}
1414
2d49ec72
GN		 1415static unsigned long segment_base(u16 selector)
1416{
d359192f 1417 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
2d49ec72
GN		 1418 struct desc_struct *d;
1419 unsigned long table_base;
1420 unsigned long v;
1421
1422 if (!(selector & ~3))
1423 return 0;
1424
d359192f 1425 table_base = gdt->address;
2d49ec72
GN		 1426
1427 if (selector & 4) { /* from ldt */
1428 u16 ldt_selector = kvm_read_ldt();
1429
1430 if (!(ldt_selector & ~3))
1431 return 0;
1432
1433 table_base = segment_base(ldt_selector);
1434 }
1435 d = (struct desc_struct *)(table_base + (selector & ~7));
1436 v = get_desc_base(d);
1437#ifdef CONFIG_X86_64
1438 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1439 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1440#endif
1441 return v;
1442}
1443
1444static inline unsigned long kvm_read_tr_base(void)
1445{
1446 u16 tr;
1447 asm("str %0" : "=g"(tr));
1448 return segment_base(tr);
1449}
1450
04d2cc77 1451static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 1452{
04d2cc77 1453 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1454 int i;
04d2cc77 1455
a2fa3e9f 1456 if (vmx->host_state.loaded)
33ed6329
AK		 1457 return;
1458
a2fa3e9f 1459 vmx->host_state.loaded = 1;
33ed6329
AK		 1460 /*
1461 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1462 * allow segment selectors with cpl > 0 or ti == 1.
1463 */
d6e88aec 1464 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 1465 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
9581d442 1466 savesegment(fs, vmx->host_state.fs_sel);
152d3f2f 1467 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 1468 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 1469 vmx->host_state.fs_reload_needed = 0;
1470 } else {
33ed6329 1471 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 1472 vmx->host_state.fs_reload_needed = 1;
33ed6329 1473 }
9581d442 1474 savesegment(gs, vmx->host_state.gs_sel);
a2fa3e9f
GH		 1475 if (!(vmx->host_state.gs_sel & 7))
1476 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 1477 else {
1478 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 1479 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 1480 }
1481
b2da15ac
AK		 1482#ifdef CONFIG_X86_64
1483 savesegment(ds, vmx->host_state.ds_sel);
1484 savesegment(es, vmx->host_state.es_sel);
1485#endif
1486
33ed6329
AK		 1487#ifdef CONFIG_X86_64
1488 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1489 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1490#else
a2fa3e9f
GH		 1491 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1492 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 1493#endif
707c0874
AK		 1494
1495#ifdef CONFIG_X86_64
c8770e7b
AK		 1496 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1497 if (is_long_mode(&vmx->vcpu))
44ea2b17 1498 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
707c0874 1499#endif
26bb0981
AK		 1500 for (i = 0; i < vmx->save_nmsrs; ++i)
1501 kvm_set_shared_msr(vmx->guest_msrs[i].index,
d5696725
AK		 1502 vmx->guest_msrs[i].data,
1503 vmx->guest_msrs[i].mask);
33ed6329
AK		 1504}
1505
a9b21b62 1506static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 1507{
a2fa3e9f 1508 if (!vmx->host_state.loaded)
33ed6329
AK		 1509 return;
1510
e1beb1d3 1511 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 1512 vmx->host_state.loaded = 0;
c8770e7b
AK		 1513#ifdef CONFIG_X86_64
1514 if (is_long_mode(&vmx->vcpu))
1515 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1516#endif
152d3f2f 1517 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 1518 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329 1519#ifdef CONFIG_X86_64
9581d442 1520 load_gs_index(vmx->host_state.gs_sel);
9581d442
AK		 1521#else
1522 loadsegment(gs, vmx->host_state.gs_sel);
33ed6329 1523#endif
33ed6329 1524 }
0a77fe4c
AK		 1525 if (vmx->host_state.fs_reload_needed)
1526 loadsegment(fs, vmx->host_state.fs_sel);
b2da15ac
AK		 1527#ifdef CONFIG_X86_64
1528 if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1529 loadsegment(ds, vmx->host_state.ds_sel);
1530 loadsegment(es, vmx->host_state.es_sel);
1531 }
b2da15ac 1532#endif
152d3f2f 1533 reload_tss();
44ea2b17 1534#ifdef CONFIG_X86_64
c8770e7b 1535 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
44ea2b17 1536#endif
b1a74bf8
SS		 1537 /*
1538 * If the FPU is not active (through the host task or
1539 * the guest vcpu), then restore the cr0.TS bit.
1540 */
1541 if (!user_has_fpu() && !vmx->vcpu.guest_fpu_loaded)
1542 stts();
3444d7da 1543 load_gdt(&__get_cpu_var(host_gdt));
33ed6329
AK		 1544}
1545
a9b21b62
AK		 1546static void vmx_load_host_state(struct vcpu_vmx *vmx)
1547{
1548 preempt_disable();
1549 __vmx_load_host_state(vmx);
1550 preempt_enable();
1551}
1552
6aa8b732
AK		 1553/*
1554 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1555 * vcpu mutex is already taken.
1556 */
15ad7146 1557static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 1558{
a2fa3e9f 1559 struct vcpu_vmx *vmx = to_vmx(vcpu);
4610c9cc 1560 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
6aa8b732 1561
4610c9cc
DX		 1562 if (!vmm_exclusive)
1563 kvm_cpu_vmxon(phys_addr);
d462b819
NHE		 1564 else if (vmx->loaded_vmcs->cpu != cpu)
1565 loaded_vmcs_clear(vmx->loaded_vmcs);
6aa8b732 1566
d462b819
NHE		 1567 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1568 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1569 vmcs_load(vmx->loaded_vmcs->vmcs);
6aa8b732
AK		 1570 }
1571
d462b819 1572 if (vmx->loaded_vmcs->cpu != cpu) {
d359192f 1573 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
6aa8b732
AK		 1574 unsigned long sysenter_esp;
1575
a8eeb04a 1576 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
92fe13be 1577 local_irq_disable();
8f536b76 1578 crash_disable_local_vmclear(cpu);
5a560f8b
XG		 1579
1580 /*
1581 * Read loaded_vmcs->cpu should be before fetching
1582 * loaded_vmcs->loaded_vmcss_on_cpu_link.
1583 * See the comments in __loaded_vmcs_clear().
1584 */
1585 smp_rmb();
1586
d462b819
NHE		 1587 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1588 &per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76 1589 crash_enable_local_vmclear(cpu);
92fe13be
DX		 1590 local_irq_enable();
1591
6aa8b732
AK		 1592 /*
1593 * Linux uses per-cpu TSS and GDT, so set these when switching
1594 * processors.
1595 */
d6e88aec 1596 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
d359192f 1597 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
6aa8b732
AK		 1598
1599 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1600 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
d462b819 1601 vmx->loaded_vmcs->cpu = cpu;
6aa8b732 1602 }
6aa8b732
AK		 1603}
1604
1605static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1606{
a9b21b62 1607 __vmx_load_host_state(to_vmx(vcpu));
4610c9cc 1608 if (!vmm_exclusive) {
d462b819
NHE		 1609 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1610 vcpu->cpu = -1;
4610c9cc
DX		 1611 kvm_cpu_vmxoff();
1612 }
6aa8b732
AK		 1613}
1614
5fd86fcf
AK		 1615static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1616{
81231c69
AK		 1617 ulong cr0;
1618
5fd86fcf
AK		 1619 if (vcpu->fpu_active)
1620 return;
1621 vcpu->fpu_active = 1;
81231c69
AK		 1622 cr0 = vmcs_readl(GUEST_CR0);
1623 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1624 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1625 vmcs_writel(GUEST_CR0, cr0);
5fd86fcf 1626 update_exception_bitmap(vcpu);
edcafe3c 1627 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
36cf24e0
NHE		 1628 if (is_guest_mode(vcpu))
1629 vcpu->arch.cr0_guest_owned_bits &=
1630 ~get_vmcs12(vcpu)->cr0_guest_host_mask;
edcafe3c 1631 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
5fd86fcf
AK		 1632}
1633
edcafe3c
AK		 1634static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1635
fe3ef05c
NHE		 1636/*
1637 * Return the cr0 value that a nested guest would read. This is a combination
1638 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1639 * its hypervisor (cr0_read_shadow).
1640 */
1641static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1642{
1643 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1644 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1645}
1646static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1647{
1648 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1649 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1650}
1651
5fd86fcf
AK		 1652static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1653{
36cf24e0
NHE		 1654 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1655 * set this *before* calling this function.
1656 */
edcafe3c 1657 vmx_decache_cr0_guest_bits(vcpu);
81231c69 1658 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
5fd86fcf 1659 update_exception_bitmap(vcpu);
edcafe3c
AK		 1660 vcpu->arch.cr0_guest_owned_bits = 0;
1661 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
36cf24e0
NHE		 1662 if (is_guest_mode(vcpu)) {
1663 /*
1664 * L1's specified read shadow might not contain the TS bit,
1665 * so now that we turned on shadowing of this bit, we need to
1666 * set this bit of the shadow. Like in nested_vmx_run we need
1667 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1668 * up-to-date here because we just decached cr0.TS (and we'll
1669 * only update vmcs12->guest_cr0 on nested exit).
1670 */
1671 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1672 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1673 (vcpu->arch.cr0 & X86_CR0_TS);
1674 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1675 } else
1676 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf
AK		 1677}
1678
6aa8b732
AK		 1679static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1680{
78ac8b47 1681 unsigned long rflags, save_rflags;
345dcaa8 1682
6de12732
AK		 1683 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1684 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1685 rflags = vmcs_readl(GUEST_RFLAGS);
1686 if (to_vmx(vcpu)->rmode.vm86_active) {
1687 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1688 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1689 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1690 }
1691 to_vmx(vcpu)->rflags = rflags;
78ac8b47 1692 }
6de12732 1693 return to_vmx(vcpu)->rflags;
6aa8b732
AK		 1694}
1695
1696static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1697{
6de12732 1698 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
69c73028 1699 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
6de12732 1700 to_vmx(vcpu)->rflags = rflags;
78ac8b47
AK		 1701 if (to_vmx(vcpu)->rmode.vm86_active) {
1702 to_vmx(vcpu)->rmode.save_rflags = rflags;
053de044 1703 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 1704 }
6aa8b732
AK		 1705 vmcs_writel(GUEST_RFLAGS, rflags);
1706}
1707
2809f5d2
GC		 1708static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1709{
1710 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1711 int ret = 0;
1712
1713 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 1714 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 1715 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 1716 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2
GC		 1717
1718 return ret & mask;
1719}
1720
1721static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1722{
1723 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1724 u32 interruptibility = interruptibility_old;
1725
1726 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1727
48005f64 1728 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 1729 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 1730 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC		 1731 interruptibility |= GUEST_INTR_STATE_STI;
1732
1733 if ((interruptibility != interruptibility_old))
1734 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1735}
1736
6aa8b732
AK		 1737static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1738{
1739 unsigned long rip;
6aa8b732 1740
5fdbf976 1741 rip = kvm_rip_read(vcpu);
6aa8b732 1742 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 1743 kvm_rip_write(vcpu, rip);
6aa8b732 1744
2809f5d2
GC		 1745 /* skipping an emulated instruction also counts */
1746 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 1747}
1748
0b6ac343
NHE		 1749/*
1750 * KVM wants to inject page-faults which it got to the guest. This function
1751 * checks whether in a nested guest, we need to inject them to L1 or L2.
1752 * This function assumes it is called with the exit reason in vmcs02 being
1753 * a #PF exception (this is the only case in which KVM injects a #PF when L2
1754 * is running).
1755 */
1756static int nested_pf_handled(struct kvm_vcpu *vcpu)
1757{
1758 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1759
1760 /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
95871901 1761 if (!(vmcs12->exception_bitmap & (1u << PF_VECTOR)))
0b6ac343
NHE		 1762 return 0;
1763
1764 nested_vmx_vmexit(vcpu);
1765 return 1;
1766}
1767
298101da 1768static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 1769 bool has_error_code, u32 error_code,
1770 bool reinject)
298101da 1771{
77ab6db0 1772 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 1773 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 1774
0b6ac343
NHE		 1775 if (nr == PF_VECTOR && is_guest_mode(vcpu) &&
1776 nested_pf_handled(vcpu))
1777 return;
1778
8ab2d2e2 1779 if (has_error_code) {
77ab6db0 1780 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 1781 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1782 }
77ab6db0 1783
7ffd92c5 1784 if (vmx->rmode.vm86_active) {
71f9833b
SH		 1785 int inc_eip = 0;
1786 if (kvm_exception_is_soft(nr))
1787 inc_eip = vcpu->arch.event_exit_inst_len;
1788 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
a92601bb 1789 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
77ab6db0
JK		 1790 return;
1791 }
1792
66fd3f7f
GN		 1793 if (kvm_exception_is_soft(nr)) {
1794 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1795 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 1796 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1797 } else
1798 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1799
1800 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
298101da
AK		 1801}
1802
4e47c7a6
SY		 1803static bool vmx_rdtscp_supported(void)
1804{
1805 return cpu_has_vmx_rdtscp();
1806}
1807
ad756a16
MJ		 1808static bool vmx_invpcid_supported(void)
1809{
1810 return cpu_has_vmx_invpcid() && enable_ept;
1811}
1812
a75beee6
ED		 1813/*
1814 * Swap MSR entry in host/guest MSR entry array.
1815 */
8b9cf98c 1816static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 1817{
26bb0981 1818 struct shared_msr_entry tmp;
a2fa3e9f
GH		 1819
1820 tmp = vmx->guest_msrs[to];
1821 vmx->guest_msrs[to] = vmx->guest_msrs[from];
1822 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 1823}
1824
e38aea3e
AK		 1825/*
1826 * Set up the vmcs to automatically save and restore system
1827 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1828 * mode, as fiddling with msrs is very expensive.
1829 */
8b9cf98c 1830static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 1831{
26bb0981 1832 int save_nmsrs, index;
5897297b 1833 unsigned long *msr_bitmap;
e38aea3e 1834
a75beee6
ED		 1835 save_nmsrs = 0;
1836#ifdef CONFIG_X86_64
8b9cf98c 1837 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 1838 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 1839 if (index >= 0)
8b9cf98c
RR		 1840 move_msr_up(vmx, index, save_nmsrs++);
1841 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 1842 if (index >= 0)
8b9cf98c
RR		 1843 move_msr_up(vmx, index, save_nmsrs++);
1844 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 1845 if (index >= 0)
8b9cf98c 1846 move_msr_up(vmx, index, save_nmsrs++);
4e47c7a6
SY		 1847 index = __find_msr_index(vmx, MSR_TSC_AUX);
1848 if (index >= 0 && vmx->rdtscp_enabled)
1849 move_msr_up(vmx, index, save_nmsrs++);
a75beee6 1850 /*
8c06585d 1851 * MSR_STAR is only needed on long mode guests, and only
a75beee6
ED		 1852 * if efer.sce is enabled.
1853 */
8c06585d 1854 index = __find_msr_index(vmx, MSR_STAR);
f6801dff 1855 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
8b9cf98c 1856 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 1857 }
1858#endif
92c0d900
AK		 1859 index = __find_msr_index(vmx, MSR_EFER);
1860 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 1861 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 1862
26bb0981 1863 vmx->save_nmsrs = save_nmsrs;
5897297b
AK		 1864
1865 if (cpu_has_vmx_msr_bitmap()) {
1866 if (is_long_mode(&vmx->vcpu))
1867 msr_bitmap = vmx_msr_bitmap_longmode;
1868 else
1869 msr_bitmap = vmx_msr_bitmap_legacy;
1870
1871 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1872 }
e38aea3e
AK		 1873}
1874
6aa8b732
AK		 1875/*
1876 * reads and returns guest's timestamp counter "register"
1877 * guest_tsc = host_tsc + tsc_offset -- 21.3
1878 */
1879static u64 guest_read_tsc(void)
1880{
1881 u64 host_tsc, tsc_offset;
1882
1883 rdtscll(host_tsc);
1884 tsc_offset = vmcs_read64(TSC_OFFSET);
1885 return host_tsc + tsc_offset;
1886}
1887
d5c1785d
NHE		 1888/*
1889 * Like guest_read_tsc, but always returns L1's notion of the timestamp
1890 * counter, even if a nested guest (L2) is currently running.
1891 */
886b470c 1892u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
d5c1785d 1893{
886b470c 1894 u64 tsc_offset;
d5c1785d 1895
d5c1785d
NHE		 1896 tsc_offset = is_guest_mode(vcpu) ?
1897 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
1898 vmcs_read64(TSC_OFFSET);
1899 return host_tsc + tsc_offset;
1900}
1901
4051b188 1902/*
cc578287
ZA		 1903 * Engage any workarounds for mis-matched TSC rates. Currently limited to
1904 * software catchup for faster rates on slower CPUs.
4051b188 1905 */
cc578287 1906static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
4051b188 1907{
cc578287
ZA		 1908 if (!scale)
1909 return;
1910
1911 if (user_tsc_khz > tsc_khz) {
1912 vcpu->arch.tsc_catchup = 1;
1913 vcpu->arch.tsc_always_catchup = 1;
1914 } else
1915 WARN(1, "user requested TSC rate below hardware speed\n");
4051b188
JR		 1916}
1917
ba904635
WA		 1918static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
1919{
1920 return vmcs_read64(TSC_OFFSET);
1921}
1922
6aa8b732 1923/*
99e3e30a 1924 * writes 'offset' into guest's timestamp counter offset register
6aa8b732 1925 */
99e3e30a 1926static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
6aa8b732 1927{
27fc51b2 1928 if (is_guest_mode(vcpu)) {
7991825b 1929 /*
27fc51b2
NHE		 1930 * We're here if L1 chose not to trap WRMSR to TSC. According
1931 * to the spec, this should set L1's TSC; The offset that L1
1932 * set for L2 remains unchanged, and still needs to be added
1933 * to the newly set TSC to get L2's TSC.
7991825b 1934 */
27fc51b2
NHE		 1935 struct vmcs12 *vmcs12;
1936 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
1937 /* recalculate vmcs02.TSC_OFFSET: */
1938 vmcs12 = get_vmcs12(vcpu);
1939 vmcs_write64(TSC_OFFSET, offset +
1940 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
1941 vmcs12->tsc_offset : 0));
1942 } else {
1943 vmcs_write64(TSC_OFFSET, offset);
1944 }
6aa8b732
AK		 1945}
1946
f1e2b260 1947static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
e48672fa
ZA		 1948{
1949 u64 offset = vmcs_read64(TSC_OFFSET);
1950 vmcs_write64(TSC_OFFSET, offset + adjustment);
7991825b
NHE		 1951 if (is_guest_mode(vcpu)) {
1952 /* Even when running L2, the adjustment needs to apply to L1 */
1953 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
1954 }
e48672fa
ZA		 1955}
1956
857e4099
JR		 1957static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1958{
1959 return target_tsc - native_read_tsc();
1960}
1961
801d3424
NHE		 1962static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
1963{
1964 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
1965 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
1966}
1967
1968/*
1969 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1970 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
1971 * all guests if the "nested" module option is off, and can also be disabled
1972 * for a single guest by disabling its VMX cpuid bit.
1973 */
1974static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
1975{
1976 return nested && guest_cpuid_has_vmx(vcpu);
1977}
1978
b87a51ae
NHE		 1979/*
1980 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
1981 * returned for the various VMX controls MSRs when nested VMX is enabled.
1982 * The same values should also be used to verify that vmcs12 control fields are
1983 * valid during nested entry from L1 to L2.
1984 * Each of these control msrs has a low and high 32-bit half: A low bit is on
1985 * if the corresponding bit in the (32-bit) control field *must* be on, and a
1986 * bit in the high half is on if the corresponding bit in the control field
1987 * may be on. See also vmx_control_verify().
1988 * TODO: allow these variables to be modified (downgraded) by module options
1989 * or other means.
1990 */
1991static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
1992static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
1993static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
1994static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
1995static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
1996static __init void nested_vmx_setup_ctls_msrs(void)
1997{
1998 /*
1999 * Note that as a general rule, the high half of the MSRs (bits in
2000 * the control fields which may be 1) should be initialized by the
2001 * intersection of the underlying hardware's MSR (i.e., features which
2002 * can be supported) and the list of features we want to expose -
2003 * because they are known to be properly supported in our code.
2004 * Also, usually, the low half of the MSRs (bits which must be 1) can
2005 * be set to 0, meaning that L1 may turn off any of these bits. The
2006 * reason is that if one of these bits is necessary, it will appear
2007 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2008 * fields of vmcs01 and vmcs02, will turn these bits off - and
2009 * nested_vmx_exit_handled() will not pass related exits to L1.
2010 * These rules have exceptions below.
2011 */
2012
2013 /* pin-based controls */
2014 /*
2015 * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
2016 * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
2017 */
2018 nested_vmx_pinbased_ctls_low = 0x16 ;
2019 nested_vmx_pinbased_ctls_high = 0x16 |
2020 PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING |
2021 PIN_BASED_VIRTUAL_NMIS;
2022
2023 /* exit controls */
2024 nested_vmx_exit_ctls_low = 0;
b6f1250e 2025 /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
b87a51ae
NHE		 2026#ifdef CONFIG_X86_64
2027 nested_vmx_exit_ctls_high = VM_EXIT_HOST_ADDR_SPACE_SIZE;
2028#else
2029 nested_vmx_exit_ctls_high = 0;
2030#endif
2031
2032 /* entry controls */
2033 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2034 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
2035 nested_vmx_entry_ctls_low = 0;
2036 nested_vmx_entry_ctls_high &=
2037 VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_IA32E_MODE;
2038
2039 /* cpu-based controls */
2040 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2041 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
2042 nested_vmx_procbased_ctls_low = 0;
2043 nested_vmx_procbased_ctls_high &=
2044 CPU_BASED_VIRTUAL_INTR_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2045 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2046 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2047 CPU_BASED_CR3_STORE_EXITING |
2048#ifdef CONFIG_X86_64
2049 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2050#endif
2051 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2052 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
dbcb4e79 2053 CPU_BASED_RDPMC_EXITING | CPU_BASED_RDTSC_EXITING |
b87a51ae
NHE		 2054 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2055 /*
2056 * We can allow some features even when not supported by the
2057 * hardware. For example, L1 can specify an MSR bitmap - and we
2058 * can use it to avoid exits to L1 - even when L0 runs L2
2059 * without MSR bitmaps.
2060 */
2061 nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS;
2062
2063 /* secondary cpu-based controls */
2064 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2065 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
2066 nested_vmx_secondary_ctls_low = 0;
2067 nested_vmx_secondary_ctls_high &=
2068 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2069}
2070
2071static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2072{
2073 /*
2074 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2075 */
2076 return ((control & high) | low) == control;
2077}
2078
2079static inline u64 vmx_control_msr(u32 low, u32 high)
2080{
2081 return low | ((u64)high << 32);
2082}
2083
2084/*
2085 * If we allow our guest to use VMX instructions (i.e., nested VMX), we should
2086 * also let it use VMX-specific MSRs.
2087 * vmx_get_vmx_msr() and vmx_set_vmx_msr() return 1 when we handled a
2088 * VMX-specific MSR, or 0 when we haven't (and the caller should handle it
2089 * like all other MSRs).
2090 */
2091static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2092{
2093 if (!nested_vmx_allowed(vcpu) && msr_index >= MSR_IA32_VMX_BASIC &&
2094 msr_index <= MSR_IA32_VMX_TRUE_ENTRY_CTLS) {
2095 /*
2096 * According to the spec, processors which do not support VMX
2097 * should throw a #GP(0) when VMX capability MSRs are read.
2098 */
2099 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
2100 return 1;
2101 }
2102
2103 switch (msr_index) {
2104 case MSR_IA32_FEATURE_CONTROL:
2105 *pdata = 0;
2106 break;
2107 case MSR_IA32_VMX_BASIC:
2108 /*
2109 * This MSR reports some information about VMX support. We
2110 * should return information about the VMX we emulate for the
2111 * guest, and the VMCS structure we give it - not about the
2112 * VMX support of the underlying hardware.
2113 */
2114 *pdata = VMCS12_REVISION |
2115 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2116 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2117 break;
2118 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2119 case MSR_IA32_VMX_PINBASED_CTLS:
2120 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2121 nested_vmx_pinbased_ctls_high);
2122 break;
2123 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2124 case MSR_IA32_VMX_PROCBASED_CTLS:
2125 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2126 nested_vmx_procbased_ctls_high);
2127 break;
2128 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2129 case MSR_IA32_VMX_EXIT_CTLS:
2130 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2131 nested_vmx_exit_ctls_high);
2132 break;
2133 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2134 case MSR_IA32_VMX_ENTRY_CTLS:
2135 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2136 nested_vmx_entry_ctls_high);
2137 break;
2138 case MSR_IA32_VMX_MISC:
2139 *pdata = 0;
2140 break;
2141 /*
2142 * These MSRs specify bits which the guest must keep fixed (on or off)
2143 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2144 * We picked the standard core2 setting.
2145 */
2146#define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2147#define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2148 case MSR_IA32_VMX_CR0_FIXED0:
2149 *pdata = VMXON_CR0_ALWAYSON;
2150 break;
2151 case MSR_IA32_VMX_CR0_FIXED1:
2152 *pdata = -1ULL;
2153 break;
2154 case MSR_IA32_VMX_CR4_FIXED0:
2155 *pdata = VMXON_CR4_ALWAYSON;
2156 break;
2157 case MSR_IA32_VMX_CR4_FIXED1:
2158 *pdata = -1ULL;
2159 break;
2160 case MSR_IA32_VMX_VMCS_ENUM:
2161 *pdata = 0x1f;
2162 break;
2163 case MSR_IA32_VMX_PROCBASED_CTLS2:
2164 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2165 nested_vmx_secondary_ctls_high);
2166 break;
2167 case MSR_IA32_VMX_EPT_VPID_CAP:
2168 /* Currently, no nested ept or nested vpid */
2169 *pdata = 0;
2170 break;
2171 default:
2172 return 0;
2173 }
2174
2175 return 1;
2176}
2177
2178static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
2179{
2180 if (!nested_vmx_allowed(vcpu))
2181 return 0;
2182
2183 if (msr_index == MSR_IA32_FEATURE_CONTROL)
2184 /* TODO: the right thing. */
2185 return 1;
2186 /*
2187 * No need to treat VMX capability MSRs specially: If we don't handle
2188 * them, handle_wrmsr will #GP(0), which is correct (they are readonly)
2189 */
2190 return 0;
2191}
2192
6aa8b732
AK		 2193/*
2194 * Reads an msr value (of 'msr_index') into 'pdata'.
2195 * Returns 0 on success, non-0 otherwise.
2196 * Assumes vcpu_load() was already called.
2197 */
2198static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2199{
2200 u64 data;
26bb0981 2201 struct shared_msr_entry *msr;
6aa8b732
AK		 2202
2203 if (!pdata) {
2204 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2205 return -EINVAL;
2206 }
2207
2208 switch (msr_index) {
05b3e0c2 2209#ifdef CONFIG_X86_64
6aa8b732
AK		 2210 case MSR_FS_BASE:
2211 data = vmcs_readl(GUEST_FS_BASE);
2212 break;
2213 case MSR_GS_BASE:
2214 data = vmcs_readl(GUEST_GS_BASE);
2215 break;
44ea2b17
AK		 2216 case MSR_KERNEL_GS_BASE:
2217 vmx_load_host_state(to_vmx(vcpu));
2218 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2219 break;
26bb0981 2220#endif
6aa8b732 2221 case MSR_EFER:
3bab1f5d 2222 return kvm_get_msr_common(vcpu, msr_index, pdata);
af24a4e4 2223 case MSR_IA32_TSC:
6aa8b732
AK		 2224 data = guest_read_tsc();
2225 break;
2226 case MSR_IA32_SYSENTER_CS:
2227 data = vmcs_read32(GUEST_SYSENTER_CS);
2228 break;
2229 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2230 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 2231 break;
2232 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2233 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 2234 break;
4e47c7a6
SY		 2235 case MSR_TSC_AUX:
2236 if (!to_vmx(vcpu)->rdtscp_enabled)
2237 return 1;
2238 /* Otherwise falls through */
6aa8b732 2239 default:
b87a51ae
NHE		 2240 if (vmx_get_vmx_msr(vcpu, msr_index, pdata))
2241 return 0;
8b9cf98c 2242 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d
AK		 2243 if (msr) {
2244 data = msr->data;
2245 break;
6aa8b732 2246 }
3bab1f5d 2247 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 2248 }
2249
2250 *pdata = data;
2251 return 0;
2252}
2253
2254/*
2255 * Writes msr value into into the appropriate "register".
2256 * Returns 0 on success, non-0 otherwise.
2257 * Assumes vcpu_load() was already called.
2258 */
8fe8ab46 2259static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
6aa8b732 2260{
a2fa3e9f 2261 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 2262 struct shared_msr_entry *msr;
2cc51560 2263 int ret = 0;
8fe8ab46
WA		 2264 u32 msr_index = msr_info->index;
2265 u64 data = msr_info->data;
2cc51560 2266
6aa8b732 2267 switch (msr_index) {
3bab1f5d 2268 case MSR_EFER:
8fe8ab46 2269 ret = kvm_set_msr_common(vcpu, msr_info);
2cc51560 2270 break;
16175a79 2271#ifdef CONFIG_X86_64
6aa8b732 2272 case MSR_FS_BASE:
2fb92db1 2273 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2274 vmcs_writel(GUEST_FS_BASE, data);
2275 break;
2276 case MSR_GS_BASE:
2fb92db1 2277 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2278 vmcs_writel(GUEST_GS_BASE, data);
2279 break;
44ea2b17
AK		 2280 case MSR_KERNEL_GS_BASE:
2281 vmx_load_host_state(vmx);
2282 vmx->msr_guest_kernel_gs_base = data;
2283 break;
6aa8b732
AK		 2284#endif
2285 case MSR_IA32_SYSENTER_CS:
2286 vmcs_write32(GUEST_SYSENTER_CS, data);
2287 break;
2288 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2289 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 2290 break;
2291 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2292 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 2293 break;
af24a4e4 2294 case MSR_IA32_TSC:
8fe8ab46 2295 kvm_write_tsc(vcpu, msr_info);
6aa8b732 2296 break;
468d472f
SY		 2297 case MSR_IA32_CR_PAT:
2298 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2299 vmcs_write64(GUEST_IA32_PAT, data);
2300 vcpu->arch.pat = data;
2301 break;
2302 }
8fe8ab46 2303 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 2304 break;
ba904635
WA		 2305 case MSR_IA32_TSC_ADJUST:
2306 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6
SY		 2307 break;
2308 case MSR_TSC_AUX:
2309 if (!vmx->rdtscp_enabled)
2310 return 1;
2311 /* Check reserved bit, higher 32 bits should be zero */
2312 if ((data >> 32) != 0)
2313 return 1;
2314 /* Otherwise falls through */
6aa8b732 2315 default:
b87a51ae
NHE		 2316 if (vmx_set_vmx_msr(vcpu, msr_index, data))
2317 break;
8b9cf98c 2318 msr = find_msr_entry(vmx, msr_index);
3bab1f5d
AK		 2319 if (msr) {
2320 msr->data = data;
2225fd56
AK		 2321 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2322 preempt_disable();
9ee73970
AK		 2323 kvm_set_shared_msr(msr->index, msr->data,
2324 msr->mask);
2225fd56
AK		 2325 preempt_enable();
2326 }
3bab1f5d 2327 break;
6aa8b732 2328 }
8fe8ab46 2329 ret = kvm_set_msr_common(vcpu, msr_info);
6aa8b732
AK		 2330 }
2331
2cc51560 2332 return ret;
6aa8b732
AK		 2333}
2334
5fdbf976 2335static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 2336{
5fdbf976
MT		 2337 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2338 switch (reg) {
2339 case VCPU_REGS_RSP:
2340 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2341 break;
2342 case VCPU_REGS_RIP:
2343 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2344 break;
6de4f3ad
AK		 2345 case VCPU_EXREG_PDPTR:
2346 if (enable_ept)
2347 ept_save_pdptrs(vcpu);
2348 break;
5fdbf976
MT		 2349 default:
2350 break;
2351 }
6aa8b732
AK		 2352}
2353
6aa8b732
AK		 2354static __init int cpu_has_kvm_support(void)
2355{
6210e37b 2356 return cpu_has_vmx();
6aa8b732
AK		 2357}
2358
2359static __init int vmx_disabled_by_bios(void)
2360{
2361 u64 msr;
2362
2363 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
cafd6659 2364 if (msr & FEATURE_CONTROL_LOCKED) {
23f3e991 2365 /* launched w/ TXT and VMX disabled */
cafd6659
SW		 2366 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2367 && tboot_enabled())
2368 return 1;
23f3e991 2369 /* launched w/o TXT and VMX only enabled w/ TXT */
cafd6659 2370 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
23f3e991 2371 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
f9335afe
SW		 2372 && !tboot_enabled()) {
2373 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
23f3e991 2374 "activate TXT before enabling KVM\n");
cafd6659 2375 return 1;
f9335afe 2376 }
23f3e991
JC		 2377 /* launched w/o TXT and VMX disabled */
2378 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2379 && !tboot_enabled())
2380 return 1;
cafd6659
SW		 2381 }
2382
2383 return 0;
6aa8b732
AK		 2384}
2385
7725b894
DX		 2386static void kvm_cpu_vmxon(u64 addr)
2387{
2388 asm volatile (ASM_VMX_VMXON_RAX
2389 : : "a"(&addr), "m"(addr)
2390 : "memory", "cc");
2391}
2392
10474ae8 2393static int hardware_enable(void *garbage)
6aa8b732
AK		 2394{
2395 int cpu = raw_smp_processor_id();
2396 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
cafd6659 2397 u64 old, test_bits;
6aa8b732 2398
10474ae8
AG		 2399 if (read_cr4() & X86_CR4_VMXE)
2400 return -EBUSY;
2401
d462b819 2402 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76
ZY		 2403
2404 /*
2405 * Now we can enable the vmclear operation in kdump
2406 * since the loaded_vmcss_on_cpu list on this cpu
2407 * has been initialized.
2408 *
2409 * Though the cpu is not in VMX operation now, there
2410 * is no problem to enable the vmclear operation
2411 * for the loaded_vmcss_on_cpu list is empty!
2412 */
2413 crash_enable_local_vmclear(cpu);
2414
6aa8b732 2415 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
cafd6659
SW		 2416
2417 test_bits = FEATURE_CONTROL_LOCKED;
2418 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2419 if (tboot_enabled())
2420 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2421
2422 if ((old & test_bits) != test_bits) {
6aa8b732 2423 /* enable and lock */
cafd6659
SW		 2424 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2425 }
66aee91a 2426 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
10474ae8 2427
4610c9cc
DX		 2428 if (vmm_exclusive) {
2429 kvm_cpu_vmxon(phys_addr);
2430 ept_sync_global();
2431 }
10474ae8 2432
3444d7da
AK		 2433 store_gdt(&__get_cpu_var(host_gdt));
2434
10474ae8 2435 return 0;
6aa8b732
AK		 2436}
2437
d462b819 2438static void vmclear_local_loaded_vmcss(void)
543e4243
AK		 2439{
2440 int cpu = raw_smp_processor_id();
d462b819 2441 struct loaded_vmcs *v, *n;
543e4243 2442
d462b819
NHE		 2443 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2444 loaded_vmcss_on_cpu_link)
2445 __loaded_vmcs_clear(v);
543e4243
AK		 2446}
2447
710ff4a8
EH		 2448
2449/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2450 * tricks.
2451 */
2452static void kvm_cpu_vmxoff(void)
6aa8b732 2453{
4ecac3fd 2454 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
6aa8b732
AK		 2455}
2456
710ff4a8
EH		 2457static void hardware_disable(void *garbage)
2458{
4610c9cc 2459 if (vmm_exclusive) {
d462b819 2460 vmclear_local_loaded_vmcss();
4610c9cc
DX		 2461 kvm_cpu_vmxoff();
2462 }
7725b894 2463 write_cr4(read_cr4() & ~X86_CR4_VMXE);
710ff4a8
EH		 2464}
2465
1c3d14fe 2466static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 2467 u32 msr, u32 *result)
1c3d14fe
YS		 2468{
2469 u32 vmx_msr_low, vmx_msr_high;
2470 u32 ctl = ctl_min | ctl_opt;
2471
2472 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2473
2474 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2475 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2476
2477 /* Ensure minimum (required) set of control bits are supported. */
2478 if (ctl_min & ~ctl)
002c7f7c 2479 return -EIO;
1c3d14fe
YS		 2480
2481 *result = ctl;
2482 return 0;
2483}
2484
110312c8
AK		 2485static __init bool allow_1_setting(u32 msr, u32 ctl)
2486{
2487 u32 vmx_msr_low, vmx_msr_high;
2488
2489 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2490 return vmx_msr_high & ctl;
2491}
2492
002c7f7c 2493static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 2494{
2495 u32 vmx_msr_low, vmx_msr_high;
d56f546d 2496 u32 min, opt, min2, opt2;
1c3d14fe
YS		 2497 u32 _pin_based_exec_control = 0;
2498 u32 _cpu_based_exec_control = 0;
f78e0e2e 2499 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 2500 u32 _vmexit_control = 0;
2501 u32 _vmentry_control = 0;
2502
2503 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
f08864b4 2504 opt = PIN_BASED_VIRTUAL_NMIS;
1c3d14fe
YS		 2505 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2506 &_pin_based_exec_control) < 0)
002c7f7c 2507 return -EIO;
1c3d14fe 2508
10166744 2509 min = CPU_BASED_HLT_EXITING |
1c3d14fe
YS		 2510#ifdef CONFIG_X86_64
2511 CPU_BASED_CR8_LOAD_EXITING |
2512 CPU_BASED_CR8_STORE_EXITING |
2513#endif
d56f546d
SY		 2514 CPU_BASED_CR3_LOAD_EXITING |
2515 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 2516 CPU_BASED_USE_IO_BITMAPS |
2517 CPU_BASED_MOV_DR_EXITING |
a7052897 2518 CPU_BASED_USE_TSC_OFFSETING |
59708670
SY		 2519 CPU_BASED_MWAIT_EXITING |
2520 CPU_BASED_MONITOR_EXITING |
fee84b07
AK		 2521 CPU_BASED_INVLPG_EXITING |
2522 CPU_BASED_RDPMC_EXITING;
443381a8 2523
f78e0e2e 2524 opt = CPU_BASED_TPR_SHADOW |
25c5f225 2525 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 2526 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 2527 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2528 &_cpu_based_exec_control) < 0)
002c7f7c 2529 return -EIO;
6e5d865c
YS		 2530#ifdef CONFIG_X86_64
2531 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2532 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2533 ~CPU_BASED_CR8_STORE_EXITING;
2534#endif
f78e0e2e 2535 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 2536 min2 = 0;
2537 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2384d2b3 2538 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 2539 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 2540 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 2541 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6 2542 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
ad756a16
MJ		 2543 SECONDARY_EXEC_RDTSCP |
2544 SECONDARY_EXEC_ENABLE_INVPCID;
d56f546d
SY		 2545 if (adjust_vmx_controls(min2, opt2,
2546 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 2547 &_cpu_based_2nd_exec_control) < 0)
2548 return -EIO;
2549 }
2550#ifndef CONFIG_X86_64
2551 if (!(_cpu_based_2nd_exec_control &
2552 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2553 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2554#endif
d56f546d 2555 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 2556 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2557 enabled */
5fff7d27
GN		 2558 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2559 CPU_BASED_CR3_STORE_EXITING |
2560 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 2561 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2562 vmx_capability.ept, vmx_capability.vpid);
2563 }
1c3d14fe
YS		 2564
2565 min = 0;
2566#ifdef CONFIG_X86_64
2567 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2568#endif
468d472f 2569 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1c3d14fe
YS		 2570 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2571 &_vmexit_control) < 0)
002c7f7c 2572 return -EIO;
1c3d14fe 2573
468d472f
SY		 2574 min = 0;
2575 opt = VM_ENTRY_LOAD_IA32_PAT;
1c3d14fe
YS		 2576 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2577 &_vmentry_control) < 0)
002c7f7c 2578 return -EIO;
6aa8b732 2579
c68876fd 2580 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 2581
2582 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2583 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 2584 return -EIO;
1c3d14fe
YS		 2585
2586#ifdef CONFIG_X86_64
2587 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2588 if (vmx_msr_high & (1u<<16))
002c7f7c 2589 return -EIO;
1c3d14fe
YS		 2590#endif
2591
2592 /* Require Write-Back (WB) memory type for VMCS accesses. */
2593 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 2594 return -EIO;
1c3d14fe 2595
002c7f7c
YS		 2596 vmcs_conf->size = vmx_msr_high & 0x1fff;
2597 vmcs_conf->order = get_order(vmcs_config.size);
2598 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 2599
002c7f7c
YS		 2600 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2601 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 2602 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 2603 vmcs_conf->vmexit_ctrl = _vmexit_control;
2604 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe 2605
110312c8
AK		 2606 cpu_has_load_ia32_efer =
2607 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2608 VM_ENTRY_LOAD_IA32_EFER)
2609 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2610 VM_EXIT_LOAD_IA32_EFER);
2611
8bf00a52
GN		 2612 cpu_has_load_perf_global_ctrl =
2613 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2614 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
2615 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2616 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2617
2618 /*
2619 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2620 * but due to arrata below it can't be used. Workaround is to use
2621 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2622 *
2623 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2624 *
2625 * AAK155 (model 26)
2626 * AAP115 (model 30)
2627 * AAT100 (model 37)
2628 * BC86,AAY89,BD102 (model 44)
2629 * BA97 (model 46)
2630 *
2631 */
2632 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
2633 switch (boot_cpu_data.x86_model) {
2634 case 26:
2635 case 30:
2636 case 37:
2637 case 44:
2638 case 46:
2639 cpu_has_load_perf_global_ctrl = false;
2640 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2641 "does not work properly. Using workaround\n");
2642 break;
2643 default:
2644 break;
2645 }
2646 }
2647
1c3d14fe 2648 return 0;
c68876fd 2649}
6aa8b732
AK		 2650
2651static struct vmcs *alloc_vmcs_cpu(int cpu)
2652{
2653 int node = cpu_to_node(cpu);
2654 struct page *pages;
2655 struct vmcs *vmcs;
2656
6484eb3e 2657 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 2658 if (!pages)
2659 return NULL;
2660 vmcs = page_address(pages);
1c3d14fe
YS		 2661 memset(vmcs, 0, vmcs_config.size);
2662 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 2663 return vmcs;
2664}
2665
2666static struct vmcs *alloc_vmcs(void)
2667{
d3b2c338 2668 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 2669}
2670
2671static void free_vmcs(struct vmcs *vmcs)
2672{
1c3d14fe 2673 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 2674}
2675
d462b819
NHE		 2676/*
2677 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2678 */
2679static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2680{
2681 if (!loaded_vmcs->vmcs)
2682 return;
2683 loaded_vmcs_clear(loaded_vmcs);
2684 free_vmcs(loaded_vmcs->vmcs);
2685 loaded_vmcs->vmcs = NULL;
2686}
2687
39959588 2688static void free_kvm_area(void)
6aa8b732
AK		 2689{
2690 int cpu;
2691
3230bb47 2692 for_each_possible_cpu(cpu) {
6aa8b732 2693 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 2694 per_cpu(vmxarea, cpu) = NULL;
2695 }
6aa8b732
AK		 2696}
2697
6aa8b732
AK		 2698static __init int alloc_kvm_area(void)
2699{
2700 int cpu;
2701
3230bb47 2702 for_each_possible_cpu(cpu) {
6aa8b732
AK		 2703 struct vmcs *vmcs;
2704
2705 vmcs = alloc_vmcs_cpu(cpu);
2706 if (!vmcs) {
2707 free_kvm_area();
2708 return -ENOMEM;
2709 }
2710
2711 per_cpu(vmxarea, cpu) = vmcs;
2712 }
2713 return 0;
2714}
2715
2716static __init int hardware_setup(void)
2717{
002c7f7c
YS		 2718 if (setup_vmcs_config(&vmcs_config) < 0)
2719 return -EIO;
50a37eb4
JR		 2720
2721 if (boot_cpu_has(X86_FEATURE_NX))
2722 kvm_enable_efer_bits(EFER_NX);
2723
93ba03c2
SY		 2724 if (!cpu_has_vmx_vpid())
2725 enable_vpid = 0;
2726
4bc9b982
SY		 2727 if (!cpu_has_vmx_ept() ||
2728 !cpu_has_vmx_ept_4levels()) {
93ba03c2 2729 enable_ept = 0;
3a624e29 2730 enable_unrestricted_guest = 0;
83c3a331 2731 enable_ept_ad_bits = 0;
3a624e29
NK		 2732 }
2733
83c3a331
XH		 2734 if (!cpu_has_vmx_ept_ad_bits())
2735 enable_ept_ad_bits = 0;
2736
3a624e29
NK		 2737 if (!cpu_has_vmx_unrestricted_guest())
2738 enable_unrestricted_guest = 0;
93ba03c2
SY		 2739
2740 if (!cpu_has_vmx_flexpriority())
2741 flexpriority_enabled = 0;
2742
95ba8273
GN		 2743 if (!cpu_has_vmx_tpr_shadow())
2744 kvm_x86_ops->update_cr8_intercept = NULL;
2745
54dee993
MT		 2746 if (enable_ept && !cpu_has_vmx_ept_2m_page())
2747 kvm_disable_largepages();
2748
4b8d54f9
ZE		 2749 if (!cpu_has_vmx_ple())
2750 ple_gap = 0;
2751
b87a51ae
NHE		 2752 if (nested)
2753 nested_vmx_setup_ctls_msrs();
2754
6aa8b732
AK		 2755 return alloc_kvm_area();
2756}
2757
2758static __exit void hardware_unsetup(void)
2759{
2760 free_kvm_area();
2761}
2762
d99e4152
GN		 2763static void fix_pmode_dataseg(struct kvm_vcpu *vcpu, int seg,
2764 struct kvm_segment *save)
6aa8b732 2765{
d99e4152
GN		 2766 if (!emulate_invalid_guest_state) {
2767 /*
2768 * CS and SS RPL should be equal during guest entry according
2769 * to VMX spec, but in reality it is not always so. Since vcpu
2770 * is in the middle of the transition from real mode to
2771 * protected mode it is safe to assume that RPL 0 is a good
2772 * default value.
2773 */
2774 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
2775 save->selector &= ~SELECTOR_RPL_MASK;
2776 save->dpl = save->selector & SELECTOR_RPL_MASK;
2777 save->s = 1;
6aa8b732 2778 }
d99e4152 2779 vmx_set_segment(vcpu, save, seg);
6aa8b732
AK		 2780}
2781
2782static void enter_pmode(struct kvm_vcpu *vcpu)
2783{
2784 unsigned long flags;
a89a8fb9 2785 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 2786
d99e4152
GN		 2787 /*
2788 * Update real mode segment cache. It may be not up-to-date if sement
2789 * register was written while vcpu was in a guest mode.
2790 */
2791 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2792 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2793 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2794 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
2795 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
2796 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
2797
a89a8fb9 2798 vmx->emulation_required = 1;
7ffd92c5 2799 vmx->rmode.vm86_active = 0;
6aa8b732 2800
2fb92db1
AK		 2801 vmx_segment_cache_clear(vmx);
2802
f5f7b2fe 2803 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
6aa8b732
AK		 2804
2805 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 2806 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2807 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK		 2808 vmcs_writel(GUEST_RFLAGS, flags);
2809
66aee91a
RR		 2810 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
2811 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 2812
2813 update_exception_bitmap(vcpu);
2814
d99e4152
GN		 2815 fix_pmode_dataseg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
2816 fix_pmode_dataseg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
f5f7b2fe
AK		 2817 fix_pmode_dataseg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2818 fix_pmode_dataseg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2819 fix_pmode_dataseg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
2820 fix_pmode_dataseg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
6aa8b732
AK		 2821}
2822
d77c26fc 2823static gva_t rmode_tss_base(struct kvm *kvm)
6aa8b732 2824{
bfc6d222 2825 if (!kvm->arch.tss_addr) {
bc6678a3 2826 struct kvm_memslots *slots;
28a37544 2827 struct kvm_memory_slot *slot;
bc6678a3
MT		 2828 gfn_t base_gfn;
2829
90d83dc3 2830 slots = kvm_memslots(kvm);
28a37544
XG		 2831 slot = id_to_memslot(slots, 0);
2832 base_gfn = slot->base_gfn + slot->npages - 3;
2833
cbc94022
IE		 2834 return base_gfn << PAGE_SHIFT;
2835 }
bfc6d222 2836 return kvm->arch.tss_addr;
6aa8b732
AK		 2837}
2838
f5f7b2fe 2839static void fix_rmode_seg(int seg, struct kvm_segment *save)
6aa8b732 2840{
772e0318 2841 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
d99e4152
GN		 2842 struct kvm_segment var = *save;
2843
2844 var.dpl = 0x3;
2845 if (seg == VCPU_SREG_CS)
2846 var.type = 0x3;
2847
2848 if (!emulate_invalid_guest_state) {
2849 var.selector = var.base >> 4;
2850 var.base = var.base & 0xffff0;
2851 var.limit = 0xffff;
2852 var.g = 0;
2853 var.db = 0;
2854 var.present = 1;
2855 var.s = 1;
2856 var.l = 0;
2857 var.unusable = 0;
2858 var.type = 0x3;
2859 var.avl = 0;
2860 if (save->base & 0xf)
2861 printk_once(KERN_WARNING "kvm: segment base is not "
2862 "paragraph aligned when entering "
2863 "protected mode (seg=%d)", seg);
2864 }
6aa8b732 2865
d99e4152
GN		 2866 vmcs_write16(sf->selector, var.selector);
2867 vmcs_write32(sf->base, var.base);
2868 vmcs_write32(sf->limit, var.limit);
2869 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
6aa8b732
AK		 2870}
2871
2872static void enter_rmode(struct kvm_vcpu *vcpu)
2873{
2874 unsigned long flags;
a89a8fb9 2875 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 2876
3a624e29
NK		 2877 if (enable_unrestricted_guest)
2878 return;
2879
f5f7b2fe
AK		 2880 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
2881 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2882 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2883 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2884 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
c6ad1153
GN		 2885 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
2886 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
f5f7b2fe 2887
a89a8fb9 2888 vmx->emulation_required = 1;
7ffd92c5 2889 vmx->rmode.vm86_active = 1;
6aa8b732 2890
776e58ea
GN		 2891 /*
2892 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
2893 * vcpu. Call it here with phys address pointing 16M below 4G.
2894 */
2895 if (!vcpu->kvm->arch.tss_addr) {
2896 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
2897 "called before entering vcpu\n");
2898 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
2899 vmx_set_tss_addr(vcpu->kvm, 0xfeffd000);
2900 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
2901 }
2902
2fb92db1
AK		 2903 vmx_segment_cache_clear(vmx);
2904
6aa8b732 2905 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
6aa8b732 2906 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
6aa8b732
AK		 2907 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2908
2909 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 2910 vmx->rmode.save_rflags = flags;
6aa8b732 2911
053de044 2912 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 2913
2914 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 2915 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 2916 update_exception_bitmap(vcpu);
2917
d99e4152
GN		 2918 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
2919 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
2920 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2921 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2922 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
2923 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
b246dd5d 2924
8668a3c4 2925 kvm_mmu_reset_context(vcpu);
6aa8b732
AK		 2926}
2927
401d10de
AS		 2928static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
2929{
2930 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 2931 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
2932
2933 if (!msr)
2934 return;
401d10de 2935
44ea2b17
AK		 2936 /*
2937 * Force kernel_gs_base reloading before EFER changes, as control
2938 * of this msr depends on is_long_mode().
2939 */
2940 vmx_load_host_state(to_vmx(vcpu));
f6801dff 2941 vcpu->arch.efer = efer;
401d10de
AS		 2942 if (efer & EFER_LMA) {
2943 vmcs_write32(VM_ENTRY_CONTROLS,
2944 vmcs_read32(VM_ENTRY_CONTROLS) |
2945 VM_ENTRY_IA32E_MODE);
2946 msr->data = efer;
2947 } else {
2948 vmcs_write32(VM_ENTRY_CONTROLS,
2949 vmcs_read32(VM_ENTRY_CONTROLS) &
2950 ~VM_ENTRY_IA32E_MODE);
2951
2952 msr->data = efer & ~EFER_LME;
2953 }
2954 setup_msrs(vmx);
2955}
2956
05b3e0c2 2957#ifdef CONFIG_X86_64
6aa8b732
AK		 2958
2959static void enter_lmode(struct kvm_vcpu *vcpu)
2960{
2961 u32 guest_tr_ar;
2962
2fb92db1
AK		 2963 vmx_segment_cache_clear(to_vmx(vcpu));
2964
6aa8b732
AK		 2965 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
2966 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
bd80158a
JK		 2967 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
2968 __func__);
6aa8b732
AK		 2969 vmcs_write32(GUEST_TR_AR_BYTES,
2970 (guest_tr_ar & ~AR_TYPE_MASK)
2971 | AR_TYPE_BUSY_64_TSS);
2972 }
da38f438 2973 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
6aa8b732
AK		 2974}
2975
2976static void exit_lmode(struct kvm_vcpu *vcpu)
2977{
6aa8b732
AK		 2978 vmcs_write32(VM_ENTRY_CONTROLS,
2979 vmcs_read32(VM_ENTRY_CONTROLS)
1e4e6e00 2980 & ~VM_ENTRY_IA32E_MODE);
da38f438 2981 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
6aa8b732
AK		 2982}
2983
2984#endif
2985
2384d2b3
SY		 2986static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
2987{
b9d762fa 2988 vpid_sync_context(to_vmx(vcpu));
dd180b3e
XG		 2989 if (enable_ept) {
2990 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2991 return;
4e1096d2 2992 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
dd180b3e 2993 }
2384d2b3
SY		 2994}
2995
e8467fda
AK		 2996static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
2997{
2998 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
2999
3000 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3001 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3002}
3003
aff48baa
AK		 3004static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3005{
3006 if (enable_ept && is_paging(vcpu))
3007 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3008 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3009}
3010
25c4c276 3011static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 3012{
fc78f519
AK		 3013 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3014
3015 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3016 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 3017}
3018
1439442c
SY		 3019static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3020{
6de4f3ad
AK		 3021 if (!test_bit(VCPU_EXREG_PDPTR,
3022 (unsigned long *)&vcpu->arch.regs_dirty))
3023 return;
3024
1439442c 3025 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
ff03a073
JR		 3026 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
3027 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
3028 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
3029 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
1439442c
SY		 3030 }
3031}
3032
8f5d549f
AK		 3033static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3034{
3035 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
ff03a073
JR		 3036 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3037 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3038 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3039 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
8f5d549f 3040 }
6de4f3ad
AK		 3041
3042 __set_bit(VCPU_EXREG_PDPTR,
3043 (unsigned long *)&vcpu->arch.regs_avail);
3044 __set_bit(VCPU_EXREG_PDPTR,
3045 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 3046}
3047
5e1746d6 3048static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1439442c
SY		 3049
3050static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3051 unsigned long cr0,
3052 struct kvm_vcpu *vcpu)
3053{
5233dd51
MT		 3054 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3055 vmx_decache_cr3(vcpu);
1439442c
SY		 3056 if (!(cr0 & X86_CR0_PG)) {
3057 /* From paging/starting to nonpaging */
3058 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3059 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 3060 (CPU_BASED_CR3_LOAD_EXITING |
3061 CPU_BASED_CR3_STORE_EXITING));
3062 vcpu->arch.cr0 = cr0;
fc78f519 3063 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 3064 } else if (!is_paging(vcpu)) {
3065 /* From nonpaging to paging */
3066 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3067 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 3068 ~(CPU_BASED_CR3_LOAD_EXITING |
3069 CPU_BASED_CR3_STORE_EXITING));
3070 vcpu->arch.cr0 = cr0;
fc78f519 3071 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 3072 }
95eb84a7
SY		 3073
3074 if (!(cr0 & X86_CR0_WP))
3075 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 3076}
3077
6aa8b732
AK		 3078static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3079{
7ffd92c5 3080 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 3081 unsigned long hw_cr0;
3082
3083 if (enable_unrestricted_guest)
3084 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
3085 | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
3086 else
3087 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
1439442c 3088
7ffd92c5 3089 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
6aa8b732
AK		 3090 enter_pmode(vcpu);
3091
7ffd92c5 3092 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
6aa8b732
AK		 3093 enter_rmode(vcpu);
3094
05b3e0c2 3095#ifdef CONFIG_X86_64
f6801dff 3096 if (vcpu->arch.efer & EFER_LME) {
707d92fa 3097 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 3098 enter_lmode(vcpu);
707d92fa 3099 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 3100 exit_lmode(vcpu);
3101 }
3102#endif
3103
089d034e 3104 if (enable_ept)
1439442c
SY		 3105 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3106
02daab21 3107 if (!vcpu->fpu_active)
81231c69 3108 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
02daab21 3109
6aa8b732 3110 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 3111 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 3112 vcpu->arch.cr0 = cr0;
69c73028 3113 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
6aa8b732
AK		 3114}
3115
1439442c
SY		 3116static u64 construct_eptp(unsigned long root_hpa)
3117{
3118 u64 eptp;
3119
3120 /* TODO write the value reading from MSR */
3121 eptp = VMX_EPT_DEFAULT_MT |
3122 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
b38f9934
XH		 3123 if (enable_ept_ad_bits)
3124 eptp |= VMX_EPT_AD_ENABLE_BIT;
1439442c
SY		 3125 eptp |= (root_hpa & PAGE_MASK);
3126
3127 return eptp;
3128}
3129
6aa8b732
AK		 3130static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3131{
1439442c
SY		 3132 unsigned long guest_cr3;
3133 u64 eptp;
3134
3135 guest_cr3 = cr3;
089d034e 3136 if (enable_ept) {
1439442c
SY		 3137 eptp = construct_eptp(cr3);
3138 vmcs_write64(EPT_POINTER, eptp);
9f8fe504 3139 guest_cr3 = is_paging(vcpu) ? kvm_read_cr3(vcpu) :
b927a3ce 3140 vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 3141 ept_load_pdptrs(vcpu);
1439442c
SY		 3142 }
3143
2384d2b3 3144 vmx_flush_tlb(vcpu);
1439442c 3145 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK		 3146}
3147
5e1746d6 3148static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
6aa8b732 3149{
7ffd92c5 3150 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1439442c
SY		 3151 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3152
5e1746d6
NHE		 3153 if (cr4 & X86_CR4_VMXE) {
3154 /*
3155 * To use VMXON (and later other VMX instructions), a guest
3156 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3157 * So basically the check on whether to allow nested VMX
3158 * is here.
3159 */
3160 if (!nested_vmx_allowed(vcpu))
3161 return 1;
3162 } else if (to_vmx(vcpu)->nested.vmxon)
3163 return 1;
3164
ad312c7c 3165 vcpu->arch.cr4 = cr4;
bc23008b
AK		 3166 if (enable_ept) {
3167 if (!is_paging(vcpu)) {
3168 hw_cr4 &= ~X86_CR4_PAE;
3169 hw_cr4 |= X86_CR4_PSE;
3170 } else if (!(cr4 & X86_CR4_PAE)) {
3171 hw_cr4 &= ~X86_CR4_PAE;
3172 }
3173 }
1439442c
SY		 3174
3175 vmcs_writel(CR4_READ_SHADOW, cr4);
3176 vmcs_writel(GUEST_CR4, hw_cr4);
5e1746d6 3177 return 0;
6aa8b732
AK		 3178}
3179
6aa8b732
AK		 3180static void vmx_get_segment(struct kvm_vcpu *vcpu,
3181 struct kvm_segment *var, int seg)
3182{
a9179499 3183 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732
AK		 3184 u32 ar;
3185
c6ad1153 3186 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
f5f7b2fe 3187 *var = vmx->rmode.segs[seg];
a9179499 3188 if (seg == VCPU_SREG_TR
2fb92db1 3189 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
f5f7b2fe 3190 return;
1390a28b
AK		 3191 var->base = vmx_read_guest_seg_base(vmx, seg);
3192 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3193 return;
a9179499 3194 }
2fb92db1
AK		 3195 var->base = vmx_read_guest_seg_base(vmx, seg);
3196 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3197 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3198 ar = vmx_read_guest_seg_ar(vmx, seg);
9fd4a3b7 3199 if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
6aa8b732
AK		 3200 ar = 0;
3201 var->type = ar & 15;
3202 var->s = (ar >> 4) & 1;
3203 var->dpl = (ar >> 5) & 3;
3204 var->present = (ar >> 7) & 1;
3205 var->avl = (ar >> 12) & 1;
3206 var->l = (ar >> 13) & 1;
3207 var->db = (ar >> 14) & 1;
3208 var->g = (ar >> 15) & 1;
3209 var->unusable = (ar >> 16) & 1;
3210}
3211
a9179499
AK		 3212static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3213{
a9179499
AK		 3214 struct kvm_segment s;
3215
3216 if (to_vmx(vcpu)->rmode.vm86_active) {
3217 vmx_get_segment(vcpu, &s, seg);
3218 return s.base;
3219 }
2fb92db1 3220 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
a9179499
AK		 3221}
3222
69c73028 3223static int __vmx_get_cpl(struct kvm_vcpu *vcpu)
2e4d2653 3224{
3eeb3288 3225 if (!is_protmode(vcpu))
2e4d2653
IE		 3226 return 0;
3227
f4c63e5d
AK		 3228 if (!is_long_mode(vcpu)
3229 && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
2e4d2653
IE		 3230 return 3;
3231
2fb92db1 3232 return vmx_read_guest_seg_selector(to_vmx(vcpu), VCPU_SREG_CS) & 3;
2e4d2653
IE		 3233}
3234
69c73028
AK		 3235static int vmx_get_cpl(struct kvm_vcpu *vcpu)
3236{
d881e6f6
AK		 3237 struct vcpu_vmx *vmx = to_vmx(vcpu);
3238
3239 /*
3240 * If we enter real mode with cs.sel & 3 != 0, the normal CPL calculations
3241 * fail; use the cache instead.
3242 */
3243 if (unlikely(vmx->emulation_required && emulate_invalid_guest_state)) {
3244 return vmx->cpl;
3245 }
3246
69c73028
AK		 3247 if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
3248 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
d881e6f6 3249 vmx->cpl = __vmx_get_cpl(vcpu);
69c73028 3250 }
d881e6f6
AK		 3251
3252 return vmx->cpl;
69c73028
AK		 3253}
3254
3255
653e3108 3256static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 3257{
6aa8b732
AK		 3258 u32 ar;
3259
f0495f9b 3260 if (var->unusable || !var->present)
6aa8b732
AK		 3261 ar = 1 << 16;
3262 else {
3263 ar = var->type & 15;
3264 ar |= (var->s & 1) << 4;
3265 ar |= (var->dpl & 3) << 5;
3266 ar |= (var->present & 1) << 7;
3267 ar |= (var->avl & 1) << 12;
3268 ar |= (var->l & 1) << 13;
3269 ar |= (var->db & 1) << 14;
3270 ar |= (var->g & 1) << 15;
3271 }
653e3108
AK		 3272
3273 return ar;
3274}
3275
3276static void vmx_set_segment(struct kvm_vcpu *vcpu,
3277 struct kvm_segment *var, int seg)
3278{
7ffd92c5 3279 struct vcpu_vmx *vmx = to_vmx(vcpu);
772e0318 3280 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
653e3108 3281
2fb92db1 3282 vmx_segment_cache_clear(vmx);
1ecd50a9 3283 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
2fb92db1 3284
1ecd50a9
GN		 3285 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3286 vmx->rmode.segs[seg] = *var;
3287 if (seg == VCPU_SREG_TR)
3288 vmcs_write16(sf->selector, var->selector);
3289 else if (var->s)
3290 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
d99e4152 3291 goto out;
653e3108 3292 }
1ecd50a9 3293
653e3108
AK		 3294 vmcs_writel(sf->base, var->base);
3295 vmcs_write32(sf->limit, var->limit);
3296 vmcs_write16(sf->selector, var->selector);
3a624e29
NK		 3297
3298 /*
3299 * Fix the "Accessed" bit in AR field of segment registers for older
3300 * qemu binaries.
3301 * IA32 arch specifies that at the time of processor reset the
3302 * "Accessed" bit in the AR field of segment registers is 1. And qemu
0fa06071 3303 * is setting it to 0 in the userland code. This causes invalid guest
3a624e29
NK		 3304 * state vmexit when "unrestricted guest" mode is turned on.
3305 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3306 * tree. Newer qemu binaries with that qemu fix would not need this
3307 * kvm hack.
3308 */
3309 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
f924d66d 3310 var->type |= 0x1; /* Accessed */
3a624e29 3311
f924d66d 3312 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
d99e4152
GN		 3313
3314out:
3315 if (!vmx->emulation_required)
3316 vmx->emulation_required = !guest_state_valid(vcpu);
6aa8b732
AK		 3317}
3318
6aa8b732
AK		 3319static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3320{
2fb92db1 3321 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
6aa8b732
AK		 3322
3323 *db = (ar >> 14) & 1;
3324 *l = (ar >> 13) & 1;
3325}
3326
89a27f4d 3327static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3328{
89a27f4d
GN		 3329 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3330 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK		 3331}
3332
89a27f4d 3333static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3334{
89a27f4d
GN		 3335 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3336 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK		 3337}
3338
89a27f4d 3339static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3340{
89a27f4d
GN		 3341 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3342 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK		 3343}
3344
89a27f4d 3345static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3346{
89a27f4d
GN		 3347 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3348 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK		 3349}
3350
648dfaa7
MG		 3351static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3352{
3353 struct kvm_segment var;
3354 u32 ar;
3355
3356 vmx_get_segment(vcpu, &var, seg);
07f42f5f 3357 var.dpl = 0x3;
0647f4aa
GN		 3358 if (seg == VCPU_SREG_CS)
3359 var.type = 0x3;
648dfaa7
MG		 3360 ar = vmx_segment_access_rights(&var);
3361
3362 if (var.base != (var.selector << 4))
3363 return false;
89efbed0 3364 if (var.limit != 0xffff)
648dfaa7 3365 return false;
07f42f5f 3366 if (ar != 0xf3)
648dfaa7
MG		 3367 return false;
3368
3369 return true;
3370}
3371
3372static bool code_segment_valid(struct kvm_vcpu *vcpu)
3373{
3374 struct kvm_segment cs;
3375 unsigned int cs_rpl;
3376
3377 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3378 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3379
1872a3f4
AK		 3380 if (cs.unusable)
3381 return false;
648dfaa7
MG		 3382 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3383 return false;
3384 if (!cs.s)
3385 return false;
1872a3f4 3386 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 3387 if (cs.dpl > cs_rpl)
3388 return false;
1872a3f4 3389 } else {
648dfaa7
MG		 3390 if (cs.dpl != cs_rpl)
3391 return false;
3392 }
3393 if (!cs.present)
3394 return false;
3395
3396 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3397 return true;
3398}
3399
3400static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3401{
3402 struct kvm_segment ss;
3403 unsigned int ss_rpl;
3404
3405 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3406 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3407
1872a3f4
AK		 3408 if (ss.unusable)
3409 return true;
3410 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 3411 return false;
3412 if (!ss.s)
3413 return false;
3414 if (ss.dpl != ss_rpl) /* DPL != RPL */
3415 return false;
3416 if (!ss.present)
3417 return false;
3418
3419 return true;
3420}
3421
3422static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3423{
3424 struct kvm_segment var;
3425 unsigned int rpl;
3426
3427 vmx_get_segment(vcpu, &var, seg);
3428 rpl = var.selector & SELECTOR_RPL_MASK;
3429
1872a3f4
AK		 3430 if (var.unusable)
3431 return true;
648dfaa7
MG		 3432 if (!var.s)
3433 return false;
3434 if (!var.present)
3435 return false;
3436 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3437 if (var.dpl < rpl) /* DPL < RPL */
3438 return false;
3439 }
3440
3441 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3442 * rights flags
3443 */
3444 return true;
3445}
3446
3447static bool tr_valid(struct kvm_vcpu *vcpu)
3448{
3449 struct kvm_segment tr;
3450
3451 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3452
1872a3f4
AK		 3453 if (tr.unusable)
3454 return false;
648dfaa7
MG		 3455 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3456 return false;
1872a3f4 3457 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 3458 return false;
3459 if (!tr.present)
3460 return false;
3461
3462 return true;
3463}
3464
3465static bool ldtr_valid(struct kvm_vcpu *vcpu)
3466{
3467 struct kvm_segment ldtr;
3468
3469 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3470
1872a3f4
AK		 3471 if (ldtr.unusable)
3472 return true;
648dfaa7
MG		 3473 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3474 return false;
3475 if (ldtr.type != 2)
3476 return false;
3477 if (!ldtr.present)
3478 return false;
3479
3480 return true;
3481}
3482
3483static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3484{
3485 struct kvm_segment cs, ss;
3486
3487 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3488 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3489
3490 return ((cs.selector & SELECTOR_RPL_MASK) ==
3491 (ss.selector & SELECTOR_RPL_MASK));
3492}
3493
3494/*
3495 * Check if guest state is valid. Returns true if valid, false if
3496 * not.
3497 * We assume that registers are always usable
3498 */
3499static bool guest_state_valid(struct kvm_vcpu *vcpu)
3500{
3501 /* real mode guest state checks */
3eeb3288 3502 if (!is_protmode(vcpu)) {
648dfaa7
MG		 3503 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3504 return false;
3505 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3506 return false;
3507 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3508 return false;
3509 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3510 return false;
3511 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3512 return false;
3513 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3514 return false;
3515 } else {
3516 /* protected mode guest state checks */
3517 if (!cs_ss_rpl_check(vcpu))
3518 return false;
3519 if (!code_segment_valid(vcpu))
3520 return false;
3521 if (!stack_segment_valid(vcpu))
3522 return false;
3523 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3524 return false;
3525 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3526 return false;
3527 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3528 return false;
3529 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3530 return false;
3531 if (!tr_valid(vcpu))
3532 return false;
3533 if (!ldtr_valid(vcpu))
3534 return false;
3535 }
3536 /* TODO:
3537 * - Add checks on RIP
3538 * - Add checks on RFLAGS
3539 */
3540
3541 return true;
3542}
3543
d77c26fc 3544static int init_rmode_tss(struct kvm *kvm)
6aa8b732 3545{
40dcaa9f 3546 gfn_t fn;
195aefde 3547 u16 data = 0;
40dcaa9f 3548 int r, idx, ret = 0;
6aa8b732 3549
40dcaa9f
XG		 3550 idx = srcu_read_lock(&kvm->srcu);
3551 fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
195aefde
IE		 3552 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3553 if (r < 0)
10589a46 3554 goto out;
195aefde 3555 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 3556 r = kvm_write_guest_page(kvm, fn++, &data,
3557 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 3558 if (r < 0)
10589a46 3559 goto out;
195aefde
IE		 3560 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3561 if (r < 0)
10589a46 3562 goto out;
195aefde
IE		 3563 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3564 if (r < 0)
10589a46 3565 goto out;
195aefde 3566 data = ~0;
10589a46
MT		 3567 r = kvm_write_guest_page(kvm, fn, &data,
3568 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3569 sizeof(u8));
195aefde 3570 if (r < 0)
10589a46
MT		 3571 goto out;
3572
3573 ret = 1;
3574out:
40dcaa9f 3575 srcu_read_unlock(&kvm->srcu, idx);
10589a46 3576 return ret;
6aa8b732
AK		 3577}
3578
b7ebfb05
SY		 3579static int init_rmode_identity_map(struct kvm *kvm)
3580{
40dcaa9f 3581 int i, idx, r, ret;
b7ebfb05
SY		 3582 pfn_t identity_map_pfn;
3583 u32 tmp;
3584
089d034e 3585 if (!enable_ept)
b7ebfb05
SY		 3586 return 1;
3587 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3588 printk(KERN_ERR "EPT: identity-mapping pagetable "
3589 "haven't been allocated!\n");
3590 return 0;
3591 }
3592 if (likely(kvm->arch.ept_identity_pagetable_done))
3593 return 1;
3594 ret = 0;
b927a3ce 3595 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
40dcaa9f 3596 idx = srcu_read_lock(&kvm->srcu);
b7ebfb05
SY		 3597 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3598 if (r < 0)
3599 goto out;
3600 /* Set up identity-mapping pagetable for EPT in real mode */
3601 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3602 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3603 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3604 r = kvm_write_guest_page(kvm, identity_map_pfn,
3605 &tmp, i * sizeof(tmp), sizeof(tmp));
3606 if (r < 0)
3607 goto out;
3608 }
3609 kvm->arch.ept_identity_pagetable_done = true;
3610 ret = 1;
3611out:
40dcaa9f 3612 srcu_read_unlock(&kvm->srcu, idx);
b7ebfb05
SY		 3613 return ret;
3614}
3615
6aa8b732
AK		 3616static void seg_setup(int seg)
3617{
772e0318 3618 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 3619 unsigned int ar;
6aa8b732
AK		 3620
3621 vmcs_write16(sf->selector, 0);
3622 vmcs_writel(sf->base, 0);
3623 vmcs_write32(sf->limit, 0xffff);
d54d07b2
GN		 3624 ar = 0x93;
3625 if (seg == VCPU_SREG_CS)
3626 ar |= 0x08; /* code segment */
3a624e29
NK		 3627
3628 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 3629}
3630
f78e0e2e
SY		 3631static int alloc_apic_access_page(struct kvm *kvm)
3632{
4484141a 3633 struct page *page;
f78e0e2e
SY		 3634 struct kvm_userspace_memory_region kvm_userspace_mem;
3635 int r = 0;
3636
79fac95e 3637 mutex_lock(&kvm->slots_lock);
bfc6d222 3638 if (kvm->arch.apic_access_page)
f78e0e2e
SY		 3639 goto out;
3640 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3641 kvm_userspace_mem.flags = 0;
3642 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
3643 kvm_userspace_mem.memory_size = PAGE_SIZE;
f82a8cfe 3644 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, false);
f78e0e2e
SY		 3645 if (r)
3646 goto out;
72dc67a6 3647
4484141a
XG		 3648 page = gfn_to_page(kvm, 0xfee00);
3649 if (is_error_page(page)) {
3650 r = -EFAULT;
3651 goto out;
3652 }
3653
3654 kvm->arch.apic_access_page = page;
f78e0e2e 3655out:
79fac95e 3656 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY		 3657 return r;
3658}
3659
b7ebfb05
SY		 3660static int alloc_identity_pagetable(struct kvm *kvm)
3661{
4484141a 3662 struct page *page;
b7ebfb05
SY		 3663 struct kvm_userspace_memory_region kvm_userspace_mem;
3664 int r = 0;
3665
79fac95e 3666 mutex_lock(&kvm->slots_lock);
b7ebfb05
SY		 3667 if (kvm->arch.ept_identity_pagetable)
3668 goto out;
3669 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
3670 kvm_userspace_mem.flags = 0;
b927a3ce
SY		 3671 kvm_userspace_mem.guest_phys_addr =
3672 kvm->arch.ept_identity_map_addr;
b7ebfb05 3673 kvm_userspace_mem.memory_size = PAGE_SIZE;
f82a8cfe 3674 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, false);
b7ebfb05
SY		 3675 if (r)
3676 goto out;
3677
4484141a
XG		 3678 page = gfn_to_page(kvm, kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
3679 if (is_error_page(page)) {
3680 r = -EFAULT;
3681 goto out;
3682 }
3683
3684 kvm->arch.ept_identity_pagetable = page;
b7ebfb05 3685out:
79fac95e 3686 mutex_unlock(&kvm->slots_lock);
b7ebfb05
SY		 3687 return r;
3688}
3689
2384d2b3
SY		 3690static void allocate_vpid(struct vcpu_vmx *vmx)
3691{
3692 int vpid;
3693
3694 vmx->vpid = 0;
919818ab 3695 if (!enable_vpid)
2384d2b3
SY		 3696 return;
3697 spin_lock(&vmx_vpid_lock);
3698 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3699 if (vpid < VMX_NR_VPIDS) {
3700 vmx->vpid = vpid;
3701 __set_bit(vpid, vmx_vpid_bitmap);
3702 }
3703 spin_unlock(&vmx_vpid_lock);
3704}
3705
cdbecfc3
LJ		 3706static void free_vpid(struct vcpu_vmx *vmx)
3707{
3708 if (!enable_vpid)
3709 return;
3710 spin_lock(&vmx_vpid_lock);
3711 if (vmx->vpid != 0)
3712 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3713 spin_unlock(&vmx_vpid_lock);
3714}
3715
5897297b 3716static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
25c5f225 3717{
3e7c73e9 3718 int f = sizeof(unsigned long);
25c5f225
SY		 3719
3720 if (!cpu_has_vmx_msr_bitmap())
3721 return;
3722
3723 /*
3724 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3725 * have the write-low and read-high bitmap offsets the wrong way round.
3726 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3727 */
25c5f225 3728 if (msr <= 0x1fff) {
3e7c73e9
AK		 3729 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
3730 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
25c5f225
SY		 3731 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3732 msr &= 0x1fff;
3e7c73e9
AK		 3733 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
3734 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
25c5f225 3735 }
25c5f225
SY		 3736}
3737
5897297b
AK		 3738static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
3739{
3740 if (!longmode_only)
3741 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
3742 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
3743}
3744
a3a8ff8e
NHE		 3745/*
3746 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
3747 * will not change in the lifetime of the guest.
3748 * Note that host-state that does change is set elsewhere. E.g., host-state
3749 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
3750 */
3751static void vmx_set_constant_host_state(void)
3752{
3753 u32 low32, high32;
3754 unsigned long tmpl;
3755 struct desc_ptr dt;
3756
b1a74bf8 3757 vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS); /* 22.2.3 */
a3a8ff8e
NHE		 3758 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
3759 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
3760
3761 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
b2da15ac
AK		 3762#ifdef CONFIG_X86_64
3763 /*
3764 * Load null selectors, so we can avoid reloading them in
3765 * __vmx_load_host_state(), in case userspace uses the null selectors
3766 * too (the expected case).
3767 */
3768 vmcs_write16(HOST_DS_SELECTOR, 0);
3769 vmcs_write16(HOST_ES_SELECTOR, 0);
3770#else
a3a8ff8e
NHE		 3771 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3772 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
b2da15ac 3773#endif
a3a8ff8e
NHE		 3774 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3775 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
3776
3777 native_store_idt(&dt);
3778 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
3779
83287ea4 3780 vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
a3a8ff8e
NHE		 3781
3782 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
3783 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
3784 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
3785 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
3786
3787 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
3788 rdmsr(MSR_IA32_CR_PAT, low32, high32);
3789 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
3790 }
3791}
3792
bf8179a0
NHE		 3793static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
3794{
3795 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
3796 if (enable_ept)
3797 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
fe3ef05c
NHE		 3798 if (is_guest_mode(&vmx->vcpu))
3799 vmx->vcpu.arch.cr4_guest_owned_bits &=
3800 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
bf8179a0
NHE		 3801 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
3802}
3803
3804static u32 vmx_exec_control(struct vcpu_vmx *vmx)
3805{
3806 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
3807 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
3808 exec_control &= ~CPU_BASED_TPR_SHADOW;
3809#ifdef CONFIG_X86_64
3810 exec_control |= CPU_BASED_CR8_STORE_EXITING |
3811 CPU_BASED_CR8_LOAD_EXITING;
3812#endif
3813 }
3814 if (!enable_ept)
3815 exec_control |= CPU_BASED_CR3_STORE_EXITING |
3816 CPU_BASED_CR3_LOAD_EXITING |
3817 CPU_BASED_INVLPG_EXITING;
3818 return exec_control;
3819}
3820
3821static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
3822{
3823 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
3824 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
3825 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
3826 if (vmx->vpid == 0)
3827 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
3828 if (!enable_ept) {
3829 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
3830 enable_unrestricted_guest = 0;
ad756a16
MJ		 3831 /* Enable INVPCID for non-ept guests may cause performance regression. */
3832 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
bf8179a0
NHE		 3833 }
3834 if (!enable_unrestricted_guest)
3835 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
3836 if (!ple_gap)
3837 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
3838 return exec_control;
3839}
3840
ce88decf
XG		 3841static void ept_set_mmio_spte_mask(void)
3842{
3843 /*
3844 * EPT Misconfigurations can be generated if the value of bits 2:0
3845 * of an EPT paging-structure entry is 110b (write/execute).
3846 * Also, magic bits (0xffull << 49) is set to quickly identify mmio
3847 * spte.
3848 */
3849 kvm_mmu_set_mmio_spte_mask(0xffull << 49 | 0x6ull);
3850}
3851
6aa8b732
AK		 3852/*
3853 * Sets up the vmcs for emulated real mode.
3854 */
8b9cf98c 3855static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 3856{
2e4ce7f5 3857#ifdef CONFIG_X86_64
6aa8b732 3858 unsigned long a;
2e4ce7f5 3859#endif
6aa8b732 3860 int i;
6aa8b732 3861
6aa8b732 3862 /* I/O */
3e7c73e9
AK		 3863 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
3864 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 3865
25c5f225 3866 if (cpu_has_vmx_msr_bitmap())
5897297b 3867 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 3868
6aa8b732
AK		 3869 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
3870
6aa8b732 3871 /* Control */
1c3d14fe
YS		 3872 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
3873 vmcs_config.pin_based_exec_ctrl);
6e5d865c 3874
bf8179a0 3875 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
6aa8b732 3876
83ff3b9d 3877 if (cpu_has_secondary_exec_ctrls()) {
bf8179a0
NHE		 3878 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
3879 vmx_secondary_exec_control(vmx));
83ff3b9d 3880 }
f78e0e2e 3881
4b8d54f9
ZE		 3882 if (ple_gap) {
3883 vmcs_write32(PLE_GAP, ple_gap);
3884 vmcs_write32(PLE_WINDOW, ple_window);
3885 }
3886
c3707958
XG		 3887 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
3888 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
6aa8b732
AK		 3889 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
3890
9581d442
AK		 3891 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
3892 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
a3a8ff8e 3893 vmx_set_constant_host_state();
05b3e0c2 3894#ifdef CONFIG_X86_64
6aa8b732
AK		 3895 rdmsrl(MSR_FS_BASE, a);
3896 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
3897 rdmsrl(MSR_GS_BASE, a);
3898 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
3899#else
3900 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
3901 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
3902#endif
3903
2cc51560
ED		 3904 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
3905 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
61d2ef2c 3906 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2cc51560 3907 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
61d2ef2c 3908 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
6aa8b732 3909
468d472f 3910 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
a3a8ff8e
NHE		 3911 u32 msr_low, msr_high;
3912 u64 host_pat;
468d472f
SY		 3913 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
3914 host_pat = msr_low | ((u64) msr_high << 32);
3915 /* Write the default value follow host pat */
3916 vmcs_write64(GUEST_IA32_PAT, host_pat);
3917 /* Keep arch.pat sync with GUEST_IA32_PAT */
3918 vmx->vcpu.arch.pat = host_pat;
3919 }
3920
6aa8b732
AK		 3921 for (i = 0; i < NR_VMX_MSR; ++i) {
3922 u32 index = vmx_msr_index[i];
3923 u32 data_low, data_high;
a2fa3e9f 3924 int j = vmx->nmsrs;
6aa8b732
AK		 3925
3926 if (rdmsr_safe(index, &data_low, &data_high) < 0)
3927 continue;
432bd6cb
AK		 3928 if (wrmsr_safe(index, data_low, data_high) < 0)
3929 continue;
26bb0981
AK		 3930 vmx->guest_msrs[j].index = i;
3931 vmx->guest_msrs[j].data = 0;
d5696725 3932 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 3933 ++vmx->nmsrs;
6aa8b732 3934 }
6aa8b732 3935
1c3d14fe 3936 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 3937
3938 /* 22.2.1, 20.8.1 */
1c3d14fe
YS		 3939 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
3940
e00c8cf2 3941 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
bf8179a0 3942 set_cr4_guest_host_mask(vmx);
e00c8cf2
AK		 3943
3944 return 0;
3945}
3946
3947static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
3948{
3949 struct vcpu_vmx *vmx = to_vmx(vcpu);
3950 u64 msr;
4b9d3a04 3951 int ret;
e00c8cf2 3952
7ffd92c5 3953 vmx->rmode.vm86_active = 0;
e00c8cf2 3954
3b86cd99
JK		 3955 vmx->soft_vnmi_blocked = 0;
3956
ad312c7c 3957 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 3958 kvm_set_cr8(&vmx->vcpu, 0);
e00c8cf2 3959 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 3960 if (kvm_vcpu_is_bsp(&vmx->vcpu))
e00c8cf2
AK		 3961 msr |= MSR_IA32_APICBASE_BSP;
3962 kvm_set_apic_base(&vmx->vcpu, msr);
3963
2fb92db1
AK		 3964 vmx_segment_cache_clear(vmx);
3965
5706be0d 3966 seg_setup(VCPU_SREG_CS);
d54d07b2 3967 if (kvm_vcpu_is_bsp(&vmx->vcpu))
e00c8cf2 3968 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
d54d07b2 3969 else {
ad312c7c
ZX		 3970 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
3971 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
e00c8cf2 3972 }
e00c8cf2
AK		 3973
3974 seg_setup(VCPU_SREG_DS);
3975 seg_setup(VCPU_SREG_ES);
3976 seg_setup(VCPU_SREG_FS);
3977 seg_setup(VCPU_SREG_GS);
3978 seg_setup(VCPU_SREG_SS);
3979
3980 vmcs_write16(GUEST_TR_SELECTOR, 0);
3981 vmcs_writel(GUEST_TR_BASE, 0);
3982 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
3983 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3984
3985 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
3986 vmcs_writel(GUEST_LDTR_BASE, 0);
3987 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
3988 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
3989
3990 vmcs_write32(GUEST_SYSENTER_CS, 0);
3991 vmcs_writel(GUEST_SYSENTER_ESP, 0);
3992 vmcs_writel(GUEST_SYSENTER_EIP, 0);
3993
3994 vmcs_writel(GUEST_RFLAGS, 0x02);
c5af89b6 3995 if (kvm_vcpu_is_bsp(&vmx->vcpu))
5fdbf976 3996 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 3997 else
5fdbf976 3998 kvm_rip_write(vcpu, 0);
e00c8cf2 3999
e00c8cf2
AK		 4000 vmcs_writel(GUEST_GDTR_BASE, 0);
4001 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4002
4003 vmcs_writel(GUEST_IDTR_BASE, 0);
4004 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4005
443381a8 4006 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
e00c8cf2
AK		 4007 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4008 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4009
e00c8cf2
AK		 4010 /* Special registers */
4011 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4012
4013 setup_msrs(vmx);
4014
6aa8b732
AK		 4015 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
4016
f78e0e2e
SY		 4017 if (cpu_has_vmx_tpr_shadow()) {
4018 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4019 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
4020 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
afc20184 4021 __pa(vmx->vcpu.arch.apic->regs));
f78e0e2e
SY		 4022 vmcs_write32(TPR_THRESHOLD, 0);
4023 }
4024
4025 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4026 vmcs_write64(APIC_ACCESS_ADDR,
bfc6d222 4027 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
6aa8b732 4028
2384d2b3
SY		 4029 if (vmx->vpid != 0)
4030 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4031
fa40052c 4032 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
7a4f5ad0 4033 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
4d4ec087 4034 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
7a4f5ad0 4035 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
8b9cf98c 4036 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 4037 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 4038 vmx_fpu_activate(&vmx->vcpu);
4039 update_exception_bitmap(&vmx->vcpu);
6aa8b732 4040
b9d762fa 4041 vpid_sync_context(vmx);
2384d2b3 4042
3200f405 4043 ret = 0;
6aa8b732 4044
a89a8fb9
MG		 4045 /* HACK: Don't enable emulation on guest boot/reset */
4046 vmx->emulation_required = 0;
4047
6aa8b732
AK		 4048 return ret;
4049}
4050
b6f1250e
NHE		 4051/*
4052 * In nested virtualization, check if L1 asked to exit on external interrupts.
4053 * For most existing hypervisors, this will always return true.
4054 */
4055static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4056{
4057 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4058 PIN_BASED_EXT_INTR_MASK;
4059}
4060
3b86cd99
JK		 4061static void enable_irq_window(struct kvm_vcpu *vcpu)
4062{
4063 u32 cpu_based_vm_exec_control;
d6185f20
NHE		 4064 if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) {
4065 /*
4066 * We get here if vmx_interrupt_allowed() said we can't
4067 * inject to L1 now because L2 must run. Ask L2 to exit
4068 * right after entry, so we can inject to L1 more promptly.
b6f1250e 4069 */
d6185f20 4070 kvm_make_request(KVM_REQ_IMMEDIATE_EXIT, vcpu);
b6f1250e 4071 return;
d6185f20 4072 }
3b86cd99
JK		 4073
4074 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4075 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4076 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4077}
4078
4079static void enable_nmi_window(struct kvm_vcpu *vcpu)
4080{
4081 u32 cpu_based_vm_exec_control;
4082
4083 if (!cpu_has_virtual_nmis()) {
4084 enable_irq_window(vcpu);
4085 return;
4086 }
4087
30bd0c4c
AK		 4088 if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4089 enable_irq_window(vcpu);
4090 return;
4091 }
3b86cd99
JK		 4092 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4093 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4094 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4095}
4096
66fd3f7f 4097static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 4098{
9c8cba37 4099 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 4100 uint32_t intr;
4101 int irq = vcpu->arch.interrupt.nr;
9c8cba37 4102
229456fc 4103 trace_kvm_inj_virq(irq);
2714d1d3 4104
fa89a817 4105 ++vcpu->stat.irq_injections;
7ffd92c5 4106 if (vmx->rmode.vm86_active) {
71f9833b
SH		 4107 int inc_eip = 0;
4108 if (vcpu->arch.interrupt.soft)
4109 inc_eip = vcpu->arch.event_exit_inst_len;
4110 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
a92601bb 4111 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
85f455f7
ED		 4112 return;
4113 }
66fd3f7f
GN		 4114 intr = irq | INTR_INFO_VALID_MASK;
4115 if (vcpu->arch.interrupt.soft) {
4116 intr |= INTR_TYPE_SOFT_INTR;
4117 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4118 vmx->vcpu.arch.event_exit_inst_len);
4119 } else
4120 intr |= INTR_TYPE_EXT_INTR;
4121 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
85f455f7
ED		 4122}
4123
f08864b4
SY		 4124static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4125{
66a5a347
JK		 4126 struct vcpu_vmx *vmx = to_vmx(vcpu);
4127
0b6ac343
NHE		 4128 if (is_guest_mode(vcpu))
4129 return;
4130
3b86cd99
JK		 4131 if (!cpu_has_virtual_nmis()) {
4132 /*
4133 * Tracking the NMI-blocked state in software is built upon
4134 * finding the next open IRQ window. This, in turn, depends on
4135 * well-behaving guests: They have to keep IRQs disabled at
4136 * least as long as the NMI handler runs. Otherwise we may
4137 * cause NMI nesting, maybe breaking the guest. But as this is
4138 * highly unlikely, we can live with the residual risk.
4139 */
4140 vmx->soft_vnmi_blocked = 1;
4141 vmx->vnmi_blocked_time = 0;
4142 }
4143
487b391d 4144 ++vcpu->stat.nmi_injections;
9d58b931 4145 vmx->nmi_known_unmasked = false;
7ffd92c5 4146 if (vmx->rmode.vm86_active) {
71f9833b 4147 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
a92601bb 4148 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
66a5a347
JK		 4149 return;
4150 }
f08864b4
SY		 4151 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4152 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
f08864b4
SY		 4153}
4154
c4282df9 4155static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
33f089ca 4156{
3b86cd99 4157 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
c4282df9 4158 return 0;
33f089ca 4159
c4282df9 4160 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
30bd0c4c
AK		 4161 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4162 | GUEST_INTR_STATE_NMI));
33f089ca
JK		 4163}
4164
3cfc3092
JK		 4165static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4166{
4167 if (!cpu_has_virtual_nmis())
4168 return to_vmx(vcpu)->soft_vnmi_blocked;
9d58b931
AK		 4169 if (to_vmx(vcpu)->nmi_known_unmasked)
4170 return false;
c332c83a 4171 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3cfc3092
JK		 4172}
4173
4174static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4175{
4176 struct vcpu_vmx *vmx = to_vmx(vcpu);
4177
4178 if (!cpu_has_virtual_nmis()) {
4179 if (vmx->soft_vnmi_blocked != masked) {
4180 vmx->soft_vnmi_blocked = masked;
4181 vmx->vnmi_blocked_time = 0;
4182 }
4183 } else {
9d58b931 4184 vmx->nmi_known_unmasked = !masked;
3cfc3092
JK		 4185 if (masked)
4186 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4187 GUEST_INTR_STATE_NMI);
4188 else
4189 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4190 GUEST_INTR_STATE_NMI);
4191 }
4192}
4193
78646121
GN		 4194static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4195{
b6f1250e 4196 if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) {
51cfe38e
NHE		 4197 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4198 if (to_vmx(vcpu)->nested.nested_run_pending ||
4199 (vmcs12->idt_vectoring_info_field &
4200 VECTORING_INFO_VALID_MASK))
b6f1250e
NHE		 4201 return 0;
4202 nested_vmx_vmexit(vcpu);
b6f1250e
NHE		 4203 vmcs12->vm_exit_reason = EXIT_REASON_EXTERNAL_INTERRUPT;
4204 vmcs12->vm_exit_intr_info = 0;
4205 /* fall through to normal code, but now in L1, not L2 */
4206 }
4207
c4282df9
GN		 4208 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4209 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4210 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 4211}
4212
cbc94022
IE		 4213static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4214{
4215 int ret;
4216 struct kvm_userspace_memory_region tss_mem = {
6fe63979 4217 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 4218 .guest_phys_addr = addr,
4219 .memory_size = PAGE_SIZE * 3,
4220 .flags = 0,
4221 };
4222
f82a8cfe 4223 ret = kvm_set_memory_region(kvm, &tss_mem, false);
cbc94022
IE		 4224 if (ret)
4225 return ret;
bfc6d222 4226 kvm->arch.tss_addr = addr;
93ea5388
GN		 4227 if (!init_rmode_tss(kvm))
4228 return -ENOMEM;
4229
cbc94022
IE		 4230 return 0;
4231}
4232
0ca1b4f4 4233static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
6aa8b732 4234{
77ab6db0 4235 switch (vec) {
77ab6db0 4236 case BP_VECTOR:
c573cd22
JK		 4237 /*
4238 * Update instruction length as we may reinject the exception
4239 * from user space while in guest debugging mode.
4240 */
4241 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4242 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940 4243 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
0ca1b4f4
GN		 4244 return false;
4245 /* fall through */
4246 case DB_VECTOR:
4247 if (vcpu->guest_debug &
4248 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4249 return false;
d0bfb940
JK		 4250 /* fall through */
4251 case DE_VECTOR:
77ab6db0
JK		 4252 case OF_VECTOR:
4253 case BR_VECTOR:
4254 case UD_VECTOR:
4255 case DF_VECTOR:
4256 case SS_VECTOR:
4257 case GP_VECTOR:
4258 case MF_VECTOR:
0ca1b4f4
GN		 4259 return true;
4260 break;
77ab6db0 4261 }
0ca1b4f4
GN		 4262 return false;
4263}
4264
4265static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4266 int vec, u32 err_code)
4267{
4268 /*
4269 * Instruction with address size override prefix opcode 0x67
4270 * Cause the #SS fault with 0 error code in VM86 mode.
4271 */
4272 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4273 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
4274 if (vcpu->arch.halt_request) {
4275 vcpu->arch.halt_request = 0;
4276 return kvm_emulate_halt(vcpu);
4277 }
4278 return 1;
4279 }
4280 return 0;
4281 }
4282
4283 /*
4284 * Forward all other exceptions that are valid in real mode.
4285 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4286 * the required debugging infrastructure rework.
4287 */
4288 kvm_queue_exception(vcpu, vec);
4289 return 1;
6aa8b732
AK		 4290}
4291
a0861c02
AK		 4292/*
4293 * Trigger machine check on the host. We assume all the MSRs are already set up
4294 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4295 * We pass a fake environment to the machine check handler because we want
4296 * the guest to be always treated like user space, no matter what context
4297 * it used internally.
4298 */
4299static void kvm_machine_check(void)
4300{
4301#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4302 struct pt_regs regs = {
4303 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4304 .flags = X86_EFLAGS_IF,
4305 };
4306
4307 do_machine_check(&regs, 0);
4308#endif
4309}
4310
851ba692 4311static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK		 4312{
4313 /* already handled by vcpu_run */
4314 return 1;
4315}
4316
851ba692 4317static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 4318{
1155f76a 4319 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 4320 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 4321 u32 intr_info, ex_no, error_code;
42dbaa5a 4322 unsigned long cr2, rip, dr6;
6aa8b732
AK		 4323 u32 vect_info;
4324 enum emulation_result er;
4325
1155f76a 4326 vect_info = vmx->idt_vectoring_info;
88786475 4327 intr_info = vmx->exit_intr_info;
6aa8b732 4328
a0861c02 4329 if (is_machine_check(intr_info))
851ba692 4330 return handle_machine_check(vcpu);
a0861c02 4331
e4a41889 4332 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 4333 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 4334
4335 if (is_no_device(intr_info)) {
5fd86fcf 4336 vmx_fpu_activate(vcpu);
2ab455cc
AL		 4337 return 1;
4338 }
4339
7aa81cc0 4340 if (is_invalid_opcode(intr_info)) {
51d8b661 4341 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
7aa81cc0 4342 if (er != EMULATE_DONE)
7ee5d940 4343 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 4344 return 1;
4345 }
4346
6aa8b732 4347 error_code = 0;
2e11384c 4348 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732 4349 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
bf4ca23e
XG		 4350
4351 /*
4352 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4353 * MMIO, it is better to report an internal error.
4354 * See the comments in vmx_handle_exit.
4355 */
4356 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4357 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4358 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4359 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4360 vcpu->run->internal.ndata = 2;
4361 vcpu->run->internal.data[0] = vect_info;
4362 vcpu->run->internal.data[1] = intr_info;
4363 return 0;
4364 }
4365
6aa8b732 4366 if (is_page_fault(intr_info)) {
1439442c 4367 /* EPT won't cause page fault directly */
cf3ace79 4368 BUG_ON(enable_ept);
6aa8b732 4369 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT		 4370 trace_kvm_page_fault(cr2, error_code);
4371
3298b75c 4372 if (kvm_event_needs_reinjection(vcpu))
577bdc49 4373 kvm_mmu_unprotect_page_virt(vcpu, cr2);
dc25e89e 4374 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
6aa8b732
AK		 4375 }
4376
d0bfb940 4377 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
0ca1b4f4
GN		 4378
4379 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4380 return handle_rmode_exception(vcpu, ex_no, error_code);
4381
42dbaa5a
JK		 4382 switch (ex_no) {
4383 case DB_VECTOR:
4384 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4385 if (!(vcpu->guest_debug &
4386 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4387 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
4388 kvm_queue_exception(vcpu, DB_VECTOR);
4389 return 1;
4390 }
4391 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4392 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4393 /* fall through */
4394 case BP_VECTOR:
c573cd22
JK		 4395 /*
4396 * Update instruction length as we may reinject #BP from
4397 * user space while in guest debugging mode. Reading it for
4398 * #DB as well causes no harm, it is not used in that case.
4399 */
4400 vmx->vcpu.arch.event_exit_inst_len =
4401 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 4402 kvm_run->exit_reason = KVM_EXIT_DEBUG;
0a434bb2 4403 rip = kvm_rip_read(vcpu);
d0bfb940
JK		 4404 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4405 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 4406 break;
4407 default:
d0bfb940
JK		 4408 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4409 kvm_run->ex.exception = ex_no;
4410 kvm_run->ex.error_code = error_code;
42dbaa5a 4411 break;
6aa8b732 4412 }
6aa8b732
AK		 4413 return 0;
4414}
4415
851ba692 4416static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 4417{
1165f5fe 4418 ++vcpu->stat.irq_exits;
6aa8b732
AK		 4419 return 1;
4420}
4421
851ba692 4422static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 4423{
851ba692 4424 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK		 4425 return 0;
4426}
6aa8b732 4427
851ba692 4428static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 4429{
bfdaab09 4430 unsigned long exit_qualification;
34c33d16 4431 int size, in, string;
039576c0 4432 unsigned port;
6aa8b732 4433
bfdaab09 4434 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 4435 string = (exit_qualification & 16) != 0;
cf8f70bf 4436 in = (exit_qualification & 8) != 0;
e70669ab 4437
cf8f70bf 4438 ++vcpu->stat.io_exits;
e70669ab 4439
cf8f70bf 4440 if (string || in)
51d8b661 4441 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
e70669ab 4442
cf8f70bf
GN		 4443 port = exit_qualification >> 16;
4444 size = (exit_qualification & 7) + 1;
e93f36bc 4445 skip_emulated_instruction(vcpu);
cf8f70bf
GN		 4446
4447 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 4448}
4449
102d8325
IM		 4450static void
4451vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4452{
4453 /*
4454 * Patch in the VMCALL instruction:
4455 */
4456 hypercall[0] = 0x0f;
4457 hypercall[1] = 0x01;
4458 hypercall[2] = 0xc1;
102d8325
IM		 4459}
4460
0fa06071 4461/* called to set cr0 as appropriate for a mov-to-cr0 exit. */
eeadf9e7
NHE		 4462static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4463{
4464 if (to_vmx(vcpu)->nested.vmxon &&
4465 ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
4466 return 1;
4467
4468 if (is_guest_mode(vcpu)) {
4469 /*
4470 * We get here when L2 changed cr0 in a way that did not change
4471 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4472 * but did change L0 shadowed bits. This can currently happen
4473 * with the TS bit: L0 may want to leave TS on (for lazy fpu
4474 * loading) while pretending to allow the guest to change it.
4475 */
4476 if (kvm_set_cr0(vcpu, (val & vcpu->arch.cr0_guest_owned_bits) |
4477 (vcpu->arch.cr0 & ~vcpu->arch.cr0_guest_owned_bits)))
4478 return 1;
4479 vmcs_writel(CR0_READ_SHADOW, val);
4480 return 0;
4481 } else
4482 return kvm_set_cr0(vcpu, val);
4483}
4484
4485static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4486{
4487 if (is_guest_mode(vcpu)) {
4488 if (kvm_set_cr4(vcpu, (val & vcpu->arch.cr4_guest_owned_bits) |
4489 (vcpu->arch.cr4 & ~vcpu->arch.cr4_guest_owned_bits)))
4490 return 1;
4491 vmcs_writel(CR4_READ_SHADOW, val);
4492 return 0;
4493 } else
4494 return kvm_set_cr4(vcpu, val);
4495}
4496
4497/* called to set cr0 as approriate for clts instruction exit. */
4498static void handle_clts(struct kvm_vcpu *vcpu)
4499{
4500 if (is_guest_mode(vcpu)) {
4501 /*
4502 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
4503 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
4504 * just pretend it's off (also in arch.cr0 for fpu_activate).
4505 */
4506 vmcs_writel(CR0_READ_SHADOW,
4507 vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
4508 vcpu->arch.cr0 &= ~X86_CR0_TS;
4509 } else
4510 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4511}
4512
851ba692 4513static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 4514{
229456fc 4515 unsigned long exit_qualification, val;
6aa8b732
AK		 4516 int cr;
4517 int reg;
49a9b07e 4518 int err;
6aa8b732 4519
bfdaab09 4520 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 4521 cr = exit_qualification & 15;
4522 reg = (exit_qualification >> 8) & 15;
4523 switch ((exit_qualification >> 4) & 3) {
4524 case 0: /* mov to cr */
229456fc
MT		 4525 val = kvm_register_read(vcpu, reg);
4526 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 4527 switch (cr) {
4528 case 0:
eeadf9e7 4529 err = handle_set_cr0(vcpu, val);
db8fcefa 4530 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 4531 return 1;
4532 case 3:
2390218b 4533 err = kvm_set_cr3(vcpu, val);
db8fcefa 4534 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 4535 return 1;
4536 case 4:
eeadf9e7 4537 err = handle_set_cr4(vcpu, val);
db8fcefa 4538 kvm_complete_insn_gp(vcpu, err);
6aa8b732 4539 return 1;
0a5fff19
GN		 4540 case 8: {
4541 u8 cr8_prev = kvm_get_cr8(vcpu);
4542 u8 cr8 = kvm_register_read(vcpu, reg);
eea1cff9 4543 err = kvm_set_cr8(vcpu, cr8);
db8fcefa 4544 kvm_complete_insn_gp(vcpu, err);
0a5fff19
GN		 4545 if (irqchip_in_kernel(vcpu->kvm))
4546 return 1;
4547 if (cr8_prev <= cr8)
4548 return 1;
851ba692 4549 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 4550 return 0;
4551 }
4b8073e4 4552 }
6aa8b732 4553 break;
25c4c276 4554 case 2: /* clts */
eeadf9e7 4555 handle_clts(vcpu);
4d4ec087 4556 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
25c4c276 4557 skip_emulated_instruction(vcpu);
6b52d186 4558 vmx_fpu_activate(vcpu);
25c4c276 4559 return 1;
6aa8b732
AK		 4560 case 1: /*mov from cr*/
4561 switch (cr) {
4562 case 3:
9f8fe504
AK		 4563 val = kvm_read_cr3(vcpu);
4564 kvm_register_write(vcpu, reg, val);
4565 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 4566 skip_emulated_instruction(vcpu);
4567 return 1;
4568 case 8:
229456fc
MT		 4569 val = kvm_get_cr8(vcpu);
4570 kvm_register_write(vcpu, reg, val);
4571 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 4572 skip_emulated_instruction(vcpu);
4573 return 1;
4574 }
4575 break;
4576 case 3: /* lmsw */
a1f83a74 4577 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 4578 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 4579 kvm_lmsw(vcpu, val);
6aa8b732
AK		 4580
4581 skip_emulated_instruction(vcpu);
4582 return 1;
4583 default:
4584 break;
4585 }
851ba692 4586 vcpu->run->exit_reason = 0;
a737f256 4587 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 4588 (int)(exit_qualification >> 4) & 3, cr);
4589 return 0;
4590}
4591
851ba692 4592static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 4593{
bfdaab09 4594 unsigned long exit_qualification;
6aa8b732
AK		 4595 int dr, reg;
4596
f2483415 4597 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK		 4598 if (!kvm_require_cpl(vcpu, 0))
4599 return 1;
42dbaa5a
JK		 4600 dr = vmcs_readl(GUEST_DR7);
4601 if (dr & DR7_GD) {
4602 /*
4603 * As the vm-exit takes precedence over the debug trap, we
4604 * need to emulate the latter, either for the host or the
4605 * guest debugging itself.
4606 */
4607 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692
AK		 4608 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
4609 vcpu->run->debug.arch.dr7 = dr;
4610 vcpu->run->debug.arch.pc =
42dbaa5a
JK		 4611 vmcs_readl(GUEST_CS_BASE) +
4612 vmcs_readl(GUEST_RIP);
851ba692
AK		 4613 vcpu->run->debug.arch.exception = DB_VECTOR;
4614 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 4615 return 0;
4616 } else {
4617 vcpu->arch.dr7 &= ~DR7_GD;
4618 vcpu->arch.dr6 |= DR6_BD;
4619 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
4620 kvm_queue_exception(vcpu, DB_VECTOR);
4621 return 1;
4622 }
4623 }
4624
bfdaab09 4625 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
42dbaa5a
JK		 4626 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
4627 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
4628 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079
GN		 4629 unsigned long val;
4630 if (!kvm_get_dr(vcpu, dr, &val))
4631 kvm_register_write(vcpu, reg, val);
4632 } else
4633 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
6aa8b732
AK		 4634 skip_emulated_instruction(vcpu);
4635 return 1;
4636}
4637
020df079
GN		 4638static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
4639{
4640 vmcs_writel(GUEST_DR7, val);
4641}
4642
851ba692 4643static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 4644{
06465c5a
AK		 4645 kvm_emulate_cpuid(vcpu);
4646 return 1;
6aa8b732
AK		 4647}
4648
851ba692 4649static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 4650{
ad312c7c 4651 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 4652 u64 data;
4653
4654 if (vmx_get_msr(vcpu, ecx, &data)) {
59200273 4655 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 4656 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 4657 return 1;
4658 }
4659
229456fc 4660 trace_kvm_msr_read(ecx, data);
2714d1d3 4661
6aa8b732 4662 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 4663 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
4664 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 4665 skip_emulated_instruction(vcpu);
4666 return 1;
4667}
4668
851ba692 4669static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 4670{
8fe8ab46 4671 struct msr_data msr;
ad312c7c
ZX		 4672 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
4673 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
4674 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732 4675
8fe8ab46
WA		 4676 msr.data = data;
4677 msr.index = ecx;
4678 msr.host_initiated = false;
4679 if (vmx_set_msr(vcpu, &msr) != 0) {
59200273 4680 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 4681 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 4682 return 1;
4683 }
4684
59200273 4685 trace_kvm_msr_write(ecx, data);
6aa8b732
AK		 4686 skip_emulated_instruction(vcpu);
4687 return 1;
4688}
4689
851ba692 4690static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c 4691{
3842d135 4692 kvm_make_request(KVM_REQ_EVENT, vcpu);
6e5d865c
YS		 4693 return 1;
4694}
4695
851ba692 4696static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 4697{
85f455f7
ED		 4698 u32 cpu_based_vm_exec_control;
4699
4700 /* clear pending irq */
4701 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4702 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
4703 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3 4704
3842d135
AK		 4705 kvm_make_request(KVM_REQ_EVENT, vcpu);
4706
a26bf12a 4707 ++vcpu->stat.irq_window_exits;
2714d1d3 4708
c1150d8c
DL		 4709 /*
4710 * If the user space waits to inject interrupts, exit as soon as
4711 * possible
4712 */
8061823a 4713 if (!irqchip_in_kernel(vcpu->kvm) &&
851ba692 4714 vcpu->run->request_interrupt_window &&
8061823a 4715 !kvm_cpu_has_interrupt(vcpu)) {
851ba692 4716 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
c1150d8c
DL		 4717 return 0;
4718 }
6aa8b732
AK		 4719 return 1;
4720}
4721
851ba692 4722static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732
AK		 4723{
4724 skip_emulated_instruction(vcpu);
d3bef15f 4725 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 4726}
4727
851ba692 4728static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 4729{
510043da 4730 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 4731 kvm_emulate_hypercall(vcpu);
4732 return 1;
c21415e8
IM		 4733}
4734
ec25d5e6
GN		 4735static int handle_invd(struct kvm_vcpu *vcpu)
4736{
51d8b661 4737 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
ec25d5e6
GN		 4738}
4739
851ba692 4740static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 4741{
f9c617f6 4742 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 4743
4744 kvm_mmu_invlpg(vcpu, exit_qualification);
4745 skip_emulated_instruction(vcpu);
4746 return 1;
4747}
4748
fee84b07
AK		 4749static int handle_rdpmc(struct kvm_vcpu *vcpu)
4750{
4751 int err;
4752
4753 err = kvm_rdpmc(vcpu);
4754 kvm_complete_insn_gp(vcpu, err);
4755
4756 return 1;
4757}
4758
851ba692 4759static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01
ED		 4760{
4761 skip_emulated_instruction(vcpu);
f5f48ee1 4762 kvm_emulate_wbinvd(vcpu);
e5edaa01
ED		 4763 return 1;
4764}
4765
2acf923e
DC		 4766static int handle_xsetbv(struct kvm_vcpu *vcpu)
4767{
4768 u64 new_bv = kvm_read_edx_eax(vcpu);
4769 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
4770
4771 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
4772 skip_emulated_instruction(vcpu);
4773 return 1;
4774}
4775
851ba692 4776static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 4777{
58fbbf26
KT		 4778 if (likely(fasteoi)) {
4779 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4780 int access_type, offset;
4781
4782 access_type = exit_qualification & APIC_ACCESS_TYPE;
4783 offset = exit_qualification & APIC_ACCESS_OFFSET;
4784 /*
4785 * Sane guest uses MOV to write EOI, with written value
4786 * not cared. So make a short-circuit here by avoiding
4787 * heavy instruction emulation.
4788 */
4789 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
4790 (offset == APIC_EOI)) {
4791 kvm_lapic_set_eoi(vcpu);
4792 skip_emulated_instruction(vcpu);
4793 return 1;
4794 }
4795 }
51d8b661 4796 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
f78e0e2e
SY		 4797}
4798
851ba692 4799static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 4800{
60637aac 4801 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 4802 unsigned long exit_qualification;
e269fb21
JK		 4803 bool has_error_code = false;
4804 u32 error_code = 0;
37817f29 4805 u16 tss_selector;
7f3d35fd 4806 int reason, type, idt_v, idt_index;
64a7ec06
GN		 4807
4808 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
7f3d35fd 4809 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
64a7ec06 4810 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 4811
4812 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4813
4814 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 4815 if (reason == TASK_SWITCH_GATE && idt_v) {
4816 switch (type) {
4817 case INTR_TYPE_NMI_INTR:
4818 vcpu->arch.nmi_injected = false;
654f06fc 4819 vmx_set_nmi_mask(vcpu, true);
64a7ec06
GN		 4820 break;
4821 case INTR_TYPE_EXT_INTR:
66fd3f7f 4822 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 4823 kvm_clear_interrupt_queue(vcpu);
4824 break;
4825 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK		 4826 if (vmx->idt_vectoring_info &
4827 VECTORING_INFO_DELIVER_CODE_MASK) {
4828 has_error_code = true;
4829 error_code =
4830 vmcs_read32(IDT_VECTORING_ERROR_CODE);
4831 }
4832 /* fall through */
64a7ec06
GN		 4833 case INTR_TYPE_SOFT_EXCEPTION:
4834 kvm_clear_exception_queue(vcpu);
4835 break;
4836 default:
4837 break;
4838 }
60637aac 4839 }
37817f29
IE		 4840 tss_selector = exit_qualification;
4841
64a7ec06
GN		 4842 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
4843 type != INTR_TYPE_EXT_INTR &&
4844 type != INTR_TYPE_NMI_INTR))
4845 skip_emulated_instruction(vcpu);
4846
7f3d35fd
KW		 4847 if (kvm_task_switch(vcpu, tss_selector,
4848 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
4849 has_error_code, error_code) == EMULATE_FAIL) {
acb54517
GN		 4850 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4851 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4852 vcpu->run->internal.ndata = 0;
42dbaa5a 4853 return 0;
acb54517 4854 }
42dbaa5a
JK		 4855
4856 /* clear all local breakpoint enable flags */
4857 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
4858
4859 /*
4860 * TODO: What about debug traps on tss switch?
4861 * Are we supposed to inject them and update dr6?
4862 */
4863
4864 return 1;
37817f29
IE		 4865}
4866
851ba692 4867static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 4868{
f9c617f6 4869 unsigned long exit_qualification;
1439442c 4870 gpa_t gpa;
4f5982a5 4871 u32 error_code;
1439442c 4872 int gla_validity;
1439442c 4873
f9c617f6 4874 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c 4875
1439442c
SY		 4876 gla_validity = (exit_qualification >> 7) & 0x3;
4877 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
4878 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
4879 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
4880 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 4881 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 4882 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
4883 (long unsigned int)exit_qualification);
851ba692
AK		 4884 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4885 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
596ae895 4886 return 0;
1439442c
SY		 4887 }
4888
4889 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 4890 trace_kvm_page_fault(gpa, exit_qualification);
4f5982a5
XG		 4891
4892 /* It is a write fault? */
4893 error_code = exit_qualification & (1U << 1);
4894 /* ept page table is present? */
4895 error_code |= (exit_qualification >> 3) & 0x1;
4896
4897 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
1439442c
SY		 4898}
4899
68f89400
MT		 4900static u64 ept_rsvd_mask(u64 spte, int level)
4901{
4902 int i;
4903 u64 mask = 0;
4904
4905 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
4906 mask |= (1ULL << i);
4907
4908 if (level > 2)
4909 /* bits 7:3 reserved */
4910 mask |= 0xf8;
4911 else if (level == 2) {
4912 if (spte & (1ULL << 7))
4913 /* 2MB ref, bits 20:12 reserved */
4914 mask |= 0x1ff000;
4915 else
4916 /* bits 6:3 reserved */
4917 mask |= 0x78;
4918 }
4919
4920 return mask;
4921}
4922
4923static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
4924 int level)
4925{
4926 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
4927
4928 /* 010b (write-only) */
4929 WARN_ON((spte & 0x7) == 0x2);
4930
4931 /* 110b (write/execute) */
4932 WARN_ON((spte & 0x7) == 0x6);
4933
4934 /* 100b (execute-only) and value not supported by logical processor */
4935 if (!cpu_has_vmx_ept_execute_only())
4936 WARN_ON((spte & 0x7) == 0x4);
4937
4938 /* not 000b */
4939 if ((spte & 0x7)) {
4940 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
4941
4942 if (rsvd_bits != 0) {
4943 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
4944 __func__, rsvd_bits);
4945 WARN_ON(1);
4946 }
4947
4948 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
4949 u64 ept_mem_type = (spte & 0x38) >> 3;
4950
4951 if (ept_mem_type == 2 || ept_mem_type == 3 ||
4952 ept_mem_type == 7) {
4953 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
4954 __func__, ept_mem_type);
4955 WARN_ON(1);
4956 }
4957 }
4958 }
4959}
4960
851ba692 4961static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400
MT		 4962{
4963 u64 sptes[4];
ce88decf 4964 int nr_sptes, i, ret;
68f89400
MT		 4965 gpa_t gpa;
4966
4967 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
4968
ce88decf
XG		 4969 ret = handle_mmio_page_fault_common(vcpu, gpa, true);
4970 if (likely(ret == 1))
4971 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
4972 EMULATE_DONE;
4973 if (unlikely(!ret))
4974 return 1;
4975
4976 /* It is the real ept misconfig */
68f89400
MT		 4977 printk(KERN_ERR "EPT: Misconfiguration.\n");
4978 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
4979
4980 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
4981
4982 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
4983 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
4984
851ba692
AK		 4985 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4986 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT		 4987
4988 return 0;
4989}
4990
851ba692 4991static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4
SY		 4992{
4993 u32 cpu_based_vm_exec_control;
4994
4995 /* clear pending NMI */
4996 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4997 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
4998 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4999 ++vcpu->stat.nmi_window_exits;
3842d135 5000 kvm_make_request(KVM_REQ_EVENT, vcpu);
f08864b4
SY		 5001
5002 return 1;
5003}
5004
80ced186 5005static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 5006{
8b3079a5
AK		 5007 struct vcpu_vmx *vmx = to_vmx(vcpu);
5008 enum emulation_result err = EMULATE_DONE;
80ced186 5009 int ret = 1;
49e9d557
AK		 5010 u32 cpu_exec_ctrl;
5011 bool intr_window_requested;
b8405c18 5012 unsigned count = 130;
49e9d557
AK		 5013
5014 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5015 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
ea953ef0 5016
b8405c18 5017 while (!guest_state_valid(vcpu) && count-- != 0) {
bdea48e3 5018 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
49e9d557
AK		 5019 return handle_interrupt_window(&vmx->vcpu);
5020
de87dcdd
AK		 5021 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5022 return 1;
5023
51d8b661 5024 err = emulate_instruction(vcpu, 0);
ea953ef0 5025
80ced186
MG		 5026 if (err == EMULATE_DO_MMIO) {
5027 ret = 0;
5028 goto out;
5029 }
1d5a4d9b 5030
de5f70e0
AK		 5031 if (err != EMULATE_DONE) {
5032 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5033 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5034 vcpu->run->internal.ndata = 0;
6d77dbfc 5035 return 0;
de5f70e0 5036 }
ea953ef0
MG		 5037
5038 if (signal_pending(current))
80ced186 5039 goto out;
ea953ef0
MG		 5040 if (need_resched())
5041 schedule();
5042 }
5043
7c068e45 5044 vmx->emulation_required = !guest_state_valid(vcpu);
80ced186
MG		 5045out:
5046 return ret;
ea953ef0
MG		 5047}
5048
4b8d54f9
ZE		 5049/*
5050 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5051 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5052 */
9fb41ba8 5053static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9
ZE		 5054{
5055 skip_emulated_instruction(vcpu);
5056 kvm_vcpu_on_spin(vcpu);
5057
5058 return 1;
5059}
5060
59708670
SY		 5061static int handle_invalid_op(struct kvm_vcpu *vcpu)
5062{
5063 kvm_queue_exception(vcpu, UD_VECTOR);
5064 return 1;
5065}
5066
ff2f6fe9
NHE		 5067/*
5068 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
5069 * We could reuse a single VMCS for all the L2 guests, but we also want the
5070 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
5071 * allows keeping them loaded on the processor, and in the future will allow
5072 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
5073 * every entry if they never change.
5074 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
5075 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
5076 *
5077 * The following functions allocate and free a vmcs02 in this pool.
5078 */
5079
5080/* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
5081static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
5082{
5083 struct vmcs02_list *item;
5084 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5085 if (item->vmptr == vmx->nested.current_vmptr) {
5086 list_move(&item->list, &vmx->nested.vmcs02_pool);
5087 return &item->vmcs02;
5088 }
5089
5090 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
5091 /* Recycle the least recently used VMCS. */
5092 item = list_entry(vmx->nested.vmcs02_pool.prev,
5093 struct vmcs02_list, list);
5094 item->vmptr = vmx->nested.current_vmptr;
5095 list_move(&item->list, &vmx->nested.vmcs02_pool);
5096 return &item->vmcs02;
5097 }
5098
5099 /* Create a new VMCS */
5100 item = (struct vmcs02_list *)
5101 kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
5102 if (!item)
5103 return NULL;
5104 item->vmcs02.vmcs = alloc_vmcs();
5105 if (!item->vmcs02.vmcs) {
5106 kfree(item);
5107 return NULL;
5108 }
5109 loaded_vmcs_init(&item->vmcs02);
5110 item->vmptr = vmx->nested.current_vmptr;
5111 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
5112 vmx->nested.vmcs02_num++;
5113 return &item->vmcs02;
5114}
5115
5116/* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
5117static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
5118{
5119 struct vmcs02_list *item;
5120 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5121 if (item->vmptr == vmptr) {
5122 free_loaded_vmcs(&item->vmcs02);
5123 list_del(&item->list);
5124 kfree(item);
5125 vmx->nested.vmcs02_num--;
5126 return;
5127 }
5128}
5129
5130/*
5131 * Free all VMCSs saved for this vcpu, except the one pointed by
5132 * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
5133 * currently used, if running L2), and vmcs01 when running L2.
5134 */
5135static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
5136{
5137 struct vmcs02_list *item, *n;
5138 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
5139 if (vmx->loaded_vmcs != &item->vmcs02)
5140 free_loaded_vmcs(&item->vmcs02);
5141 list_del(&item->list);
5142 kfree(item);
5143 }
5144 vmx->nested.vmcs02_num = 0;
5145
5146 if (vmx->loaded_vmcs != &vmx->vmcs01)
5147 free_loaded_vmcs(&vmx->vmcs01);
5148}
5149
ec378aee
NHE		 5150/*
5151 * Emulate the VMXON instruction.
5152 * Currently, we just remember that VMX is active, and do not save or even
5153 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
5154 * do not currently need to store anything in that guest-allocated memory
5155 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
5156 * argument is different from the VMXON pointer (which the spec says they do).
5157 */
5158static int handle_vmon(struct kvm_vcpu *vcpu)
5159{
5160 struct kvm_segment cs;
5161 struct vcpu_vmx *vmx = to_vmx(vcpu);
5162
5163 /* The Intel VMX Instruction Reference lists a bunch of bits that
5164 * are prerequisite to running VMXON, most notably cr4.VMXE must be
5165 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
5166 * Otherwise, we should fail with #UD. We test these now:
5167 */
5168 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
5169 !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
5170 (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
5171 kvm_queue_exception(vcpu, UD_VECTOR);
5172 return 1;
5173 }
5174
5175 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5176 if (is_long_mode(vcpu) && !cs.l) {
5177 kvm_queue_exception(vcpu, UD_VECTOR);
5178 return 1;
5179 }
5180
5181 if (vmx_get_cpl(vcpu)) {
5182 kvm_inject_gp(vcpu, 0);
5183 return 1;
5184 }
5185
ff2f6fe9
NHE		 5186 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
5187 vmx->nested.vmcs02_num = 0;
5188
ec378aee
NHE		 5189 vmx->nested.vmxon = true;
5190
5191 skip_emulated_instruction(vcpu);
5192 return 1;
5193}
5194
5195/*
5196 * Intel's VMX Instruction Reference specifies a common set of prerequisites
5197 * for running VMX instructions (except VMXON, whose prerequisites are
5198 * slightly different). It also specifies what exception to inject otherwise.
5199 */
5200static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
5201{
5202 struct kvm_segment cs;
5203 struct vcpu_vmx *vmx = to_vmx(vcpu);
5204
5205 if (!vmx->nested.vmxon) {
5206 kvm_queue_exception(vcpu, UD_VECTOR);
5207 return 0;
5208 }
5209
5210 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5211 if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
5212 (is_long_mode(vcpu) && !cs.l)) {
5213 kvm_queue_exception(vcpu, UD_VECTOR);
5214 return 0;
5215 }
5216
5217 if (vmx_get_cpl(vcpu)) {
5218 kvm_inject_gp(vcpu, 0);
5219 return 0;
5220 }
5221
5222 return 1;
5223}
5224
5225/*
5226 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
5227 * just stops using VMX.
5228 */
5229static void free_nested(struct vcpu_vmx *vmx)
5230{
5231 if (!vmx->nested.vmxon)
5232 return;
5233 vmx->nested.vmxon = false;
a9d30f33
NHE		 5234 if (vmx->nested.current_vmptr != -1ull) {
5235 kunmap(vmx->nested.current_vmcs12_page);
5236 nested_release_page(vmx->nested.current_vmcs12_page);
5237 vmx->nested.current_vmptr = -1ull;
5238 vmx->nested.current_vmcs12 = NULL;
5239 }
fe3ef05c
NHE		 5240 /* Unpin physical memory we referred to in current vmcs02 */
5241 if (vmx->nested.apic_access_page) {
5242 nested_release_page(vmx->nested.apic_access_page);
5243 vmx->nested.apic_access_page = 0;
5244 }
ff2f6fe9
NHE		 5245
5246 nested_free_all_saved_vmcss(vmx);
ec378aee
NHE		 5247}
5248
5249/* Emulate the VMXOFF instruction */
5250static int handle_vmoff(struct kvm_vcpu *vcpu)
5251{
5252 if (!nested_vmx_check_permission(vcpu))
5253 return 1;
5254 free_nested(to_vmx(vcpu));
5255 skip_emulated_instruction(vcpu);
5256 return 1;
5257}
5258
064aea77
NHE		 5259/*
5260 * Decode the memory-address operand of a vmx instruction, as recorded on an
5261 * exit caused by such an instruction (run by a guest hypervisor).
5262 * On success, returns 0. When the operand is invalid, returns 1 and throws
5263 * #UD or #GP.
5264 */
5265static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
5266 unsigned long exit_qualification,
5267 u32 vmx_instruction_info, gva_t *ret)
5268{
5269 /*
5270 * According to Vol. 3B, "Information for VM Exits Due to Instruction
5271 * Execution", on an exit, vmx_instruction_info holds most of the
5272 * addressing components of the operand. Only the displacement part
5273 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5274 * For how an actual address is calculated from all these components,
5275 * refer to Vol. 1, "Operand Addressing".
5276 */
5277 int scaling = vmx_instruction_info & 3;
5278 int addr_size = (vmx_instruction_info >> 7) & 7;
5279 bool is_reg = vmx_instruction_info & (1u << 10);
5280 int seg_reg = (vmx_instruction_info >> 15) & 7;
5281 int index_reg = (vmx_instruction_info >> 18) & 0xf;
5282 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
5283 int base_reg = (vmx_instruction_info >> 23) & 0xf;
5284 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
5285
5286 if (is_reg) {
5287 kvm_queue_exception(vcpu, UD_VECTOR);
5288 return 1;
5289 }
5290
5291 /* Addr = segment_base + offset */
5292 /* offset = base + [index * scale] + displacement */
5293 *ret = vmx_get_segment_base(vcpu, seg_reg);
5294 if (base_is_valid)
5295 *ret += kvm_register_read(vcpu, base_reg);
5296 if (index_is_valid)
5297 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
5298 *ret += exit_qualification; /* holds the displacement */
5299
5300 if (addr_size == 1) /* 32 bit */
5301 *ret &= 0xffffffff;
5302
5303 /*
5304 * TODO: throw #GP (and return 1) in various cases that the VM*
5305 * instructions require it - e.g., offset beyond segment limit,
5306 * unusable or unreadable/unwritable segment, non-canonical 64-bit
5307 * address, and so on. Currently these are not checked.
5308 */
5309 return 0;
5310}
5311
0140caea
NHE		 5312/*
5313 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5314 * set the success or error code of an emulated VMX instruction, as specified
5315 * by Vol 2B, VMX Instruction Reference, "Conventions".
5316 */
5317static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
5318{
5319 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
5320 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5321 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
5322}
5323
5324static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
5325{
5326 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5327 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
5328 X86_EFLAGS_SF | X86_EFLAGS_OF))
5329 | X86_EFLAGS_CF);
5330}
5331
5332static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
5333 u32 vm_instruction_error)
5334{
5335 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
5336 /*
5337 * failValid writes the error number to the current VMCS, which
5338 * can't be done there isn't a current VMCS.
5339 */
5340 nested_vmx_failInvalid(vcpu);
5341 return;
5342 }
5343 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5344 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5345 X86_EFLAGS_SF | X86_EFLAGS_OF))
5346 | X86_EFLAGS_ZF);
5347 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
5348}
5349
27d6c865
NHE		 5350/* Emulate the VMCLEAR instruction */
5351static int handle_vmclear(struct kvm_vcpu *vcpu)
5352{
5353 struct vcpu_vmx *vmx = to_vmx(vcpu);
5354 gva_t gva;
5355 gpa_t vmptr;
5356 struct vmcs12 *vmcs12;
5357 struct page *page;
5358 struct x86_exception e;
5359
5360 if (!nested_vmx_check_permission(vcpu))
5361 return 1;
5362
5363 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5364 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5365 return 1;
5366
5367 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5368 sizeof(vmptr), &e)) {
5369 kvm_inject_page_fault(vcpu, &e);
5370 return 1;
5371 }
5372
5373 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5374 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
5375 skip_emulated_instruction(vcpu);
5376 return 1;
5377 }
5378
5379 if (vmptr == vmx->nested.current_vmptr) {
5380 kunmap(vmx->nested.current_vmcs12_page);
5381 nested_release_page(vmx->nested.current_vmcs12_page);
5382 vmx->nested.current_vmptr = -1ull;
5383 vmx->nested.current_vmcs12 = NULL;
5384 }
5385
5386 page = nested_get_page(vcpu, vmptr);
5387 if (page == NULL) {
5388 /*
5389 * For accurate processor emulation, VMCLEAR beyond available
5390 * physical memory should do nothing at all. However, it is
5391 * possible that a nested vmx bug, not a guest hypervisor bug,
5392 * resulted in this case, so let's shut down before doing any
5393 * more damage:
5394 */
5395 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5396 return 1;
5397 }
5398 vmcs12 = kmap(page);
5399 vmcs12->launch_state = 0;
5400 kunmap(page);
5401 nested_release_page(page);
5402
5403 nested_free_vmcs02(vmx, vmptr);
5404
5405 skip_emulated_instruction(vcpu);
5406 nested_vmx_succeed(vcpu);
5407 return 1;
5408}
5409
cd232ad0
NHE		 5410static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
5411
5412/* Emulate the VMLAUNCH instruction */
5413static int handle_vmlaunch(struct kvm_vcpu *vcpu)
5414{
5415 return nested_vmx_run(vcpu, true);
5416}
5417
5418/* Emulate the VMRESUME instruction */
5419static int handle_vmresume(struct kvm_vcpu *vcpu)
5420{
5421
5422 return nested_vmx_run(vcpu, false);
5423}
5424
49f705c5
NHE		 5425enum vmcs_field_type {
5426 VMCS_FIELD_TYPE_U16 = 0,
5427 VMCS_FIELD_TYPE_U64 = 1,
5428 VMCS_FIELD_TYPE_U32 = 2,
5429 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
5430};
5431
5432static inline int vmcs_field_type(unsigned long field)
5433{
5434 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
5435 return VMCS_FIELD_TYPE_U32;
5436 return (field >> 13) & 0x3 ;
5437}
5438
5439static inline int vmcs_field_readonly(unsigned long field)
5440{
5441 return (((field >> 10) & 0x3) == 1);
5442}
5443
5444/*
5445 * Read a vmcs12 field. Since these can have varying lengths and we return
5446 * one type, we chose the biggest type (u64) and zero-extend the return value
5447 * to that size. Note that the caller, handle_vmread, might need to use only
5448 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
5449 * 64-bit fields are to be returned).
5450 */
5451static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
5452 unsigned long field, u64 *ret)
5453{
5454 short offset = vmcs_field_to_offset(field);
5455 char *p;
5456
5457 if (offset < 0)
5458 return 0;
5459
5460 p = ((char *)(get_vmcs12(vcpu))) + offset;
5461
5462 switch (vmcs_field_type(field)) {
5463 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5464 *ret = *((natural_width *)p);
5465 return 1;
5466 case VMCS_FIELD_TYPE_U16:
5467 *ret = *((u16 *)p);
5468 return 1;
5469 case VMCS_FIELD_TYPE_U32:
5470 *ret = *((u32 *)p);
5471 return 1;
5472 case VMCS_FIELD_TYPE_U64:
5473 *ret = *((u64 *)p);
5474 return 1;
5475 default:
5476 return 0; /* can never happen. */
5477 }
5478}
5479
5480/*
5481 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
5482 * used before) all generate the same failure when it is missing.
5483 */
5484static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
5485{
5486 struct vcpu_vmx *vmx = to_vmx(vcpu);
5487 if (vmx->nested.current_vmptr == -1ull) {
5488 nested_vmx_failInvalid(vcpu);
5489 skip_emulated_instruction(vcpu);
5490 return 0;
5491 }
5492 return 1;
5493}
5494
5495static int handle_vmread(struct kvm_vcpu *vcpu)
5496{
5497 unsigned long field;
5498 u64 field_value;
5499 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5500 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5501 gva_t gva = 0;
5502
5503 if (!nested_vmx_check_permission(vcpu) ||
5504 !nested_vmx_check_vmcs12(vcpu))
5505 return 1;
5506
5507 /* Decode instruction info and find the field to read */
5508 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5509 /* Read the field, zero-extended to a u64 field_value */
5510 if (!vmcs12_read_any(vcpu, field, &field_value)) {
5511 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5512 skip_emulated_instruction(vcpu);
5513 return 1;
5514 }
5515 /*
5516 * Now copy part of this value to register or memory, as requested.
5517 * Note that the number of bits actually copied is 32 or 64 depending
5518 * on the guest's mode (32 or 64 bit), not on the given field's length.
5519 */
5520 if (vmx_instruction_info & (1u << 10)) {
5521 kvm_register_write(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
5522 field_value);
5523 } else {
5524 if (get_vmx_mem_address(vcpu, exit_qualification,
5525 vmx_instruction_info, &gva))
5526 return 1;
5527 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
5528 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
5529 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
5530 }
5531
5532 nested_vmx_succeed(vcpu);
5533 skip_emulated_instruction(vcpu);
5534 return 1;
5535}
5536
5537
5538static int handle_vmwrite(struct kvm_vcpu *vcpu)
5539{
5540 unsigned long field;
5541 gva_t gva;
5542 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5543 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5544 char *p;
5545 short offset;
5546 /* The value to write might be 32 or 64 bits, depending on L1's long
5547 * mode, and eventually we need to write that into a field of several
5548 * possible lengths. The code below first zero-extends the value to 64
5549 * bit (field_value), and then copies only the approriate number of
5550 * bits into the vmcs12 field.
5551 */
5552 u64 field_value = 0;
5553 struct x86_exception e;
5554
5555 if (!nested_vmx_check_permission(vcpu) ||
5556 !nested_vmx_check_vmcs12(vcpu))
5557 return 1;
5558
5559 if (vmx_instruction_info & (1u << 10))
5560 field_value = kvm_register_read(vcpu,
5561 (((vmx_instruction_info) >> 3) & 0xf));
5562 else {
5563 if (get_vmx_mem_address(vcpu, exit_qualification,
5564 vmx_instruction_info, &gva))
5565 return 1;
5566 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
5567 &field_value, (is_long_mode(vcpu) ? 8 : 4), &e)) {
5568 kvm_inject_page_fault(vcpu, &e);
5569 return 1;
5570 }
5571 }
5572
5573
5574 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5575 if (vmcs_field_readonly(field)) {
5576 nested_vmx_failValid(vcpu,
5577 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
5578 skip_emulated_instruction(vcpu);
5579 return 1;
5580 }
5581
5582 offset = vmcs_field_to_offset(field);
5583 if (offset < 0) {
5584 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5585 skip_emulated_instruction(vcpu);
5586 return 1;
5587 }
5588 p = ((char *) get_vmcs12(vcpu)) + offset;
5589
5590 switch (vmcs_field_type(field)) {
5591 case VMCS_FIELD_TYPE_U16:
5592 *(u16 *)p = field_value;
5593 break;
5594 case VMCS_FIELD_TYPE_U32:
5595 *(u32 *)p = field_value;
5596 break;
5597 case VMCS_FIELD_TYPE_U64:
5598 *(u64 *)p = field_value;
5599 break;
5600 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5601 *(natural_width *)p = field_value;
5602 break;
5603 default:
5604 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5605 skip_emulated_instruction(vcpu);
5606 return 1;
5607 }
5608
5609 nested_vmx_succeed(vcpu);
5610 skip_emulated_instruction(vcpu);
5611 return 1;
5612}
5613
63846663
NHE		 5614/* Emulate the VMPTRLD instruction */
5615static int handle_vmptrld(struct kvm_vcpu *vcpu)
5616{
5617 struct vcpu_vmx *vmx = to_vmx(vcpu);
5618 gva_t gva;
5619 gpa_t vmptr;
5620 struct x86_exception e;
5621
5622 if (!nested_vmx_check_permission(vcpu))
5623 return 1;
5624
5625 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5626 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5627 return 1;
5628
5629 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5630 sizeof(vmptr), &e)) {
5631 kvm_inject_page_fault(vcpu, &e);
5632 return 1;
5633 }
5634
5635 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5636 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
5637 skip_emulated_instruction(vcpu);
5638 return 1;
5639 }
5640
5641 if (vmx->nested.current_vmptr != vmptr) {
5642 struct vmcs12 *new_vmcs12;
5643 struct page *page;
5644 page = nested_get_page(vcpu, vmptr);
5645 if (page == NULL) {
5646 nested_vmx_failInvalid(vcpu);
5647 skip_emulated_instruction(vcpu);
5648 return 1;
5649 }
5650 new_vmcs12 = kmap(page);
5651 if (new_vmcs12->revision_id != VMCS12_REVISION) {
5652 kunmap(page);
5653 nested_release_page_clean(page);
5654 nested_vmx_failValid(vcpu,
5655 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
5656 skip_emulated_instruction(vcpu);
5657 return 1;
5658 }
5659 if (vmx->nested.current_vmptr != -1ull) {
5660 kunmap(vmx->nested.current_vmcs12_page);
5661 nested_release_page(vmx->nested.current_vmcs12_page);
5662 }
5663
5664 vmx->nested.current_vmptr = vmptr;
5665 vmx->nested.current_vmcs12 = new_vmcs12;
5666 vmx->nested.current_vmcs12_page = page;
5667 }
5668
5669 nested_vmx_succeed(vcpu);
5670 skip_emulated_instruction(vcpu);
5671 return 1;
5672}
5673
6a4d7550
NHE		 5674/* Emulate the VMPTRST instruction */
5675static int handle_vmptrst(struct kvm_vcpu *vcpu)
5676{
5677 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5678 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5679 gva_t vmcs_gva;
5680 struct x86_exception e;
5681
5682 if (!nested_vmx_check_permission(vcpu))
5683 return 1;
5684
5685 if (get_vmx_mem_address(vcpu, exit_qualification,
5686 vmx_instruction_info, &vmcs_gva))
5687 return 1;
5688 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
5689 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
5690 (void *)&to_vmx(vcpu)->nested.current_vmptr,
5691 sizeof(u64), &e)) {
5692 kvm_inject_page_fault(vcpu, &e);
5693 return 1;
5694 }
5695 nested_vmx_succeed(vcpu);
5696 skip_emulated_instruction(vcpu);
5697 return 1;
5698}
5699
6aa8b732
AK		 5700/*
5701 * The exit handlers return 1 if the exit was handled fully and guest execution
5702 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
5703 * to be done to userspace and return 0.
5704 */
772e0318 5705static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK		 5706 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
5707 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 5708 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 5709 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 5710 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 5711 [EXIT_REASON_CR_ACCESS] = handle_cr,
5712 [EXIT_REASON_DR_ACCESS] = handle_dr,
5713 [EXIT_REASON_CPUID] = handle_cpuid,
5714 [EXIT_REASON_MSR_READ] = handle_rdmsr,
5715 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
5716 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
5717 [EXIT_REASON_HLT] = handle_halt,
ec25d5e6 5718 [EXIT_REASON_INVD] = handle_invd,
a7052897 5719 [EXIT_REASON_INVLPG] = handle_invlpg,
fee84b07 5720 [EXIT_REASON_RDPMC] = handle_rdpmc,
c21415e8 5721 [EXIT_REASON_VMCALL] = handle_vmcall,
27d6c865 5722 [EXIT_REASON_VMCLEAR] = handle_vmclear,
cd232ad0 5723 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
63846663 5724 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
6a4d7550 5725 [EXIT_REASON_VMPTRST] = handle_vmptrst,
49f705c5 5726 [EXIT_REASON_VMREAD] = handle_vmread,
cd232ad0 5727 [EXIT_REASON_VMRESUME] = handle_vmresume,
49f705c5 5728 [EXIT_REASON_VMWRITE] = handle_vmwrite,
ec378aee
NHE		 5729 [EXIT_REASON_VMOFF] = handle_vmoff,
5730 [EXIT_REASON_VMON] = handle_vmon,
f78e0e2e
SY		 5731 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
5732 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
e5edaa01 5733 [EXIT_REASON_WBINVD] = handle_wbinvd,
2acf923e 5734 [EXIT_REASON_XSETBV] = handle_xsetbv,
37817f29 5735 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 5736 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT		 5737 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
5738 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 5739 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
59708670
SY		 5740 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op,
5741 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op,
6aa8b732
AK		 5742};
5743
5744static const int kvm_vmx_max_exit_handlers =
50a3485c 5745 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732 5746
644d711a
NHE		 5747/*
5748 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
5749 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
5750 * disinterest in the current event (read or write a specific MSR) by using an
5751 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
5752 */
5753static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
5754 struct vmcs12 *vmcs12, u32 exit_reason)
5755{
5756 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
5757 gpa_t bitmap;
5758
5759 if (!nested_cpu_has(get_vmcs12(vcpu), CPU_BASED_USE_MSR_BITMAPS))
5760 return 1;
5761
5762 /*
5763 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
5764 * for the four combinations of read/write and low/high MSR numbers.
5765 * First we need to figure out which of the four to use:
5766 */
5767 bitmap = vmcs12->msr_bitmap;
5768 if (exit_reason == EXIT_REASON_MSR_WRITE)
5769 bitmap += 2048;
5770 if (msr_index >= 0xc0000000) {
5771 msr_index -= 0xc0000000;
5772 bitmap += 1024;
5773 }
5774
5775 /* Then read the msr_index'th bit from this bitmap: */
5776 if (msr_index < 1024*8) {
5777 unsigned char b;
5778 kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1);
5779 return 1 & (b >> (msr_index & 7));
5780 } else
5781 return 1; /* let L1 handle the wrong parameter */
5782}
5783
5784/*
5785 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
5786 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
5787 * intercept (via guest_host_mask etc.) the current event.
5788 */
5789static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
5790 struct vmcs12 *vmcs12)
5791{
5792 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5793 int cr = exit_qualification & 15;
5794 int reg = (exit_qualification >> 8) & 15;
5795 unsigned long val = kvm_register_read(vcpu, reg);
5796
5797 switch ((exit_qualification >> 4) & 3) {
5798 case 0: /* mov to cr */
5799 switch (cr) {
5800 case 0:
5801 if (vmcs12->cr0_guest_host_mask &
5802 (val ^ vmcs12->cr0_read_shadow))
5803 return 1;
5804 break;
5805 case 3:
5806 if ((vmcs12->cr3_target_count >= 1 &&
5807 vmcs12->cr3_target_value0 == val) ||
5808 (vmcs12->cr3_target_count >= 2 &&
5809 vmcs12->cr3_target_value1 == val) ||
5810 (vmcs12->cr3_target_count >= 3 &&
5811 vmcs12->cr3_target_value2 == val) ||
5812 (vmcs12->cr3_target_count >= 4 &&
5813 vmcs12->cr3_target_value3 == val))
5814 return 0;
5815 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
5816 return 1;
5817 break;
5818 case 4:
5819 if (vmcs12->cr4_guest_host_mask &
5820 (vmcs12->cr4_read_shadow ^ val))
5821 return 1;
5822 break;
5823 case 8:
5824 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
5825 return 1;
5826 break;
5827 }
5828 break;
5829 case 2: /* clts */
5830 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
5831 (vmcs12->cr0_read_shadow & X86_CR0_TS))
5832 return 1;
5833 break;
5834 case 1: /* mov from cr */
5835 switch (cr) {
5836 case 3:
5837 if (vmcs12->cpu_based_vm_exec_control &
5838 CPU_BASED_CR3_STORE_EXITING)
5839 return 1;
5840 break;
5841 case 8:
5842 if (vmcs12->cpu_based_vm_exec_control &
5843 CPU_BASED_CR8_STORE_EXITING)
5844 return 1;
5845 break;
5846 }
5847 break;
5848 case 3: /* lmsw */
5849 /*
5850 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
5851 * cr0. Other attempted changes are ignored, with no exit.
5852 */
5853 if (vmcs12->cr0_guest_host_mask & 0xe &
5854 (val ^ vmcs12->cr0_read_shadow))
5855 return 1;
5856 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
5857 !(vmcs12->cr0_read_shadow & 0x1) &&
5858 (val & 0x1))
5859 return 1;
5860 break;
5861 }
5862 return 0;
5863}
5864
5865/*
5866 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
5867 * should handle it ourselves in L0 (and then continue L2). Only call this
5868 * when in is_guest_mode (L2).
5869 */
5870static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
5871{
5872 u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
5873 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
5874 struct vcpu_vmx *vmx = to_vmx(vcpu);
5875 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5876
5877 if (vmx->nested.nested_run_pending)
5878 return 0;
5879
5880 if (unlikely(vmx->fail)) {
bd80158a
JK		 5881 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
5882 vmcs_read32(VM_INSTRUCTION_ERROR));
644d711a
NHE		 5883 return 1;
5884 }
5885
5886 switch (exit_reason) {
5887 case EXIT_REASON_EXCEPTION_NMI:
5888 if (!is_exception(intr_info))
5889 return 0;
5890 else if (is_page_fault(intr_info))
5891 return enable_ept;
5892 return vmcs12->exception_bitmap &
5893 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
5894 case EXIT_REASON_EXTERNAL_INTERRUPT:
5895 return 0;
5896 case EXIT_REASON_TRIPLE_FAULT:
5897 return 1;
5898 case EXIT_REASON_PENDING_INTERRUPT:
5899 case EXIT_REASON_NMI_WINDOW:
5900 /*
5901 * prepare_vmcs02() set the CPU_BASED_VIRTUAL_INTR_PENDING bit
5902 * (aka Interrupt Window Exiting) only when L1 turned it on,
5903 * so if we got a PENDING_INTERRUPT exit, this must be for L1.
5904 * Same for NMI Window Exiting.
5905 */
5906 return 1;
5907 case EXIT_REASON_TASK_SWITCH:
5908 return 1;
5909 case EXIT_REASON_CPUID:
5910 return 1;
5911 case EXIT_REASON_HLT:
5912 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
5913 case EXIT_REASON_INVD:
5914 return 1;
5915 case EXIT_REASON_INVLPG:
5916 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
5917 case EXIT_REASON_RDPMC:
5918 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
5919 case EXIT_REASON_RDTSC:
5920 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
5921 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
5922 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
5923 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
5924 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
5925 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
5926 /*
5927 * VMX instructions trap unconditionally. This allows L1 to
5928 * emulate them for its L2 guest, i.e., allows 3-level nesting!
5929 */
5930 return 1;
5931 case EXIT_REASON_CR_ACCESS:
5932 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
5933 case EXIT_REASON_DR_ACCESS:
5934 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
5935 case EXIT_REASON_IO_INSTRUCTION:
5936 /* TODO: support IO bitmaps */
5937 return 1;
5938 case EXIT_REASON_MSR_READ:
5939 case EXIT_REASON_MSR_WRITE:
5940 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
5941 case EXIT_REASON_INVALID_STATE:
5942 return 1;
5943 case EXIT_REASON_MWAIT_INSTRUCTION:
5944 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
5945 case EXIT_REASON_MONITOR_INSTRUCTION:
5946 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
5947 case EXIT_REASON_PAUSE_INSTRUCTION:
5948 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
5949 nested_cpu_has2(vmcs12,
5950 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
5951 case EXIT_REASON_MCE_DURING_VMENTRY:
5952 return 0;
5953 case EXIT_REASON_TPR_BELOW_THRESHOLD:
5954 return 1;
5955 case EXIT_REASON_APIC_ACCESS:
5956 return nested_cpu_has2(vmcs12,
5957 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
5958 case EXIT_REASON_EPT_VIOLATION:
5959 case EXIT_REASON_EPT_MISCONFIG:
5960 return 0;
5961 case EXIT_REASON_WBINVD:
5962 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
5963 case EXIT_REASON_XSETBV:
5964 return 1;
5965 default:
5966 return 1;
5967 }
5968}
5969
586f9607
AK		 5970static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
5971{
5972 *info1 = vmcs_readl(EXIT_QUALIFICATION);
5973 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
5974}
5975
6aa8b732
AK		 5976/*
5977 * The guest has exited. See if we can fix it or if we need userspace
5978 * assistance.
5979 */
851ba692 5980static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 5981{
29bd8a78 5982 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 5983 u32 exit_reason = vmx->exit_reason;
1155f76a 5984 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 5985
80ced186
MG		 5986 /* If guest state is invalid, start emulating */
5987 if (vmx->emulation_required && emulate_invalid_guest_state)
5988 return handle_invalid_guest_state(vcpu);
1d5a4d9b 5989
b6f1250e
NHE		 5990 /*
5991 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
5992 * we did not inject a still-pending event to L1 now because of
5993 * nested_run_pending, we need to re-enable this bit.
5994 */
5995 if (vmx->nested.nested_run_pending)
5996 kvm_make_request(KVM_REQ_EVENT, vcpu);
5997
509c75ea
NHE		 5998 if (!is_guest_mode(vcpu) && (exit_reason == EXIT_REASON_VMLAUNCH ||
5999 exit_reason == EXIT_REASON_VMRESUME))
644d711a
NHE		 6000 vmx->nested.nested_run_pending = 1;
6001 else
6002 vmx->nested.nested_run_pending = 0;
6003
6004 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
6005 nested_vmx_vmexit(vcpu);
6006 return 1;
6007 }
6008
5120702e
MG		 6009 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
6010 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6011 vcpu->run->fail_entry.hardware_entry_failure_reason
6012 = exit_reason;
6013 return 0;
6014 }
6015
29bd8a78 6016 if (unlikely(vmx->fail)) {
851ba692
AK		 6017 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6018 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK		 6019 = vmcs_read32(VM_INSTRUCTION_ERROR);
6020 return 0;
6021 }
6aa8b732 6022
b9bf6882
XG		 6023 /*
6024 * Note:
6025 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
6026 * delivery event since it indicates guest is accessing MMIO.
6027 * The vm-exit can be triggered again after return to guest that
6028 * will cause infinite loop.
6029 */
d77c26fc 6030 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 6031 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac 6032 exit_reason != EXIT_REASON_EPT_VIOLATION &&
b9bf6882
XG		 6033 exit_reason != EXIT_REASON_TASK_SWITCH)) {
6034 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6035 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
6036 vcpu->run->internal.ndata = 2;
6037 vcpu->run->internal.data[0] = vectoring_info;
6038 vcpu->run->internal.data[1] = exit_reason;
6039 return 0;
6040 }
3b86cd99 6041
644d711a
NHE		 6042 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
6043 !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
6044 get_vmcs12(vcpu), vcpu)))) {
c4282df9 6045 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 6046 vmx->soft_vnmi_blocked = 0;
3b86cd99 6047 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 6048 vcpu->arch.nmi_pending) {
3b86cd99
JK		 6049 /*
6050 * This CPU don't support us in finding the end of an
6051 * NMI-blocked window if the guest runs with IRQs
6052 * disabled. So we pull the trigger after 1 s of
6053 * futile waiting, but inform the user about this.
6054 */
6055 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
6056 "state on VCPU %d after 1 s timeout\n",
6057 __func__, vcpu->vcpu_id);
6058 vmx->soft_vnmi_blocked = 0;
3b86cd99 6059 }
3b86cd99
JK		 6060 }
6061
6aa8b732
AK		 6062 if (exit_reason < kvm_vmx_max_exit_handlers
6063 && kvm_vmx_exit_handlers[exit_reason])
851ba692 6064 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 6065 else {
851ba692
AK		 6066 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6067 vcpu->run->hw.hardware_exit_reason = exit_reason;
6aa8b732
AK		 6068 }
6069 return 0;
6070}
6071
95ba8273 6072static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 6073{
95ba8273 6074 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 6075 vmcs_write32(TPR_THRESHOLD, 0);
6076 return;
6077 }
6078
95ba8273 6079 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 6080}
6081
51aa01d1 6082static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
cf393f75 6083{
00eba012
AK		 6084 u32 exit_intr_info;
6085
6086 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
6087 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
6088 return;
6089
c5ca8e57 6090 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
00eba012 6091 exit_intr_info = vmx->exit_intr_info;
a0861c02
AK		 6092
6093 /* Handle machine checks before interrupts are enabled */
00eba012 6094 if (is_machine_check(exit_intr_info))
a0861c02
AK		 6095 kvm_machine_check();
6096
20f65983 6097 /* We need to handle NMIs before interrupts are enabled */
00eba012 6098 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
ff9d07a0
ZY		 6099 (exit_intr_info & INTR_INFO_VALID_MASK)) {
6100 kvm_before_handle_nmi(&vmx->vcpu);
20f65983 6101 asm("int $2");
ff9d07a0
ZY		 6102 kvm_after_handle_nmi(&vmx->vcpu);
6103 }
51aa01d1 6104}
20f65983 6105
51aa01d1
AK		 6106static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
6107{
c5ca8e57 6108 u32 exit_intr_info;
51aa01d1
AK		 6109 bool unblock_nmi;
6110 u8 vector;
6111 bool idtv_info_valid;
6112
6113 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
20f65983 6114
cf393f75 6115 if (cpu_has_virtual_nmis()) {
9d58b931
AK		 6116 if (vmx->nmi_known_unmasked)
6117 return;
c5ca8e57
AK		 6118 /*
6119 * Can't use vmx->exit_intr_info since we're not sure what
6120 * the exit reason is.
6121 */
6122 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
cf393f75
AK		 6123 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
6124 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6125 /*
7b4a25cb 6126 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 6127 * Re-set bit "block by NMI" before VM entry if vmexit caused by
6128 * a guest IRET fault.
7b4a25cb
GN		 6129 * SDM 3: 23.2.2 (September 2008)
6130 * Bit 12 is undefined in any of the following cases:
6131 * If the VM exit sets the valid bit in the IDT-vectoring
6132 * information field.
6133 * If the VM exit is due to a double fault.
cf393f75 6134 */
7b4a25cb
GN		 6135 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
6136 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 6137 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
6138 GUEST_INTR_STATE_NMI);
9d58b931
AK		 6139 else
6140 vmx->nmi_known_unmasked =
6141 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
6142 & GUEST_INTR_STATE_NMI);
3b86cd99
JK		 6143 } else if (unlikely(vmx->soft_vnmi_blocked))
6144 vmx->vnmi_blocked_time +=
6145 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
51aa01d1
AK		 6146}
6147
83422e17
AK		 6148static void __vmx_complete_interrupts(struct vcpu_vmx *vmx,
6149 u32 idt_vectoring_info,
6150 int instr_len_field,
6151 int error_code_field)
51aa01d1 6152{
51aa01d1
AK		 6153 u8 vector;
6154 int type;
6155 bool idtv_info_valid;
6156
6157 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
668f612f 6158
37b96e98
GN		 6159 vmx->vcpu.arch.nmi_injected = false;
6160 kvm_clear_exception_queue(&vmx->vcpu);
6161 kvm_clear_interrupt_queue(&vmx->vcpu);
6162
6163 if (!idtv_info_valid)
6164 return;
6165
3842d135
AK		 6166 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6167
668f612f
AK		 6168 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
6169 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 6170
64a7ec06 6171 switch (type) {
37b96e98
GN		 6172 case INTR_TYPE_NMI_INTR:
6173 vmx->vcpu.arch.nmi_injected = true;
668f612f 6174 /*
7b4a25cb 6175 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 6176 * Clear bit "block by NMI" before VM entry if a NMI
6177 * delivery faulted.
668f612f 6178 */
654f06fc 6179 vmx_set_nmi_mask(&vmx->vcpu, false);
37b96e98 6180 break;
37b96e98 6181 case INTR_TYPE_SOFT_EXCEPTION:
66fd3f7f 6182 vmx->vcpu.arch.event_exit_inst_len =
83422e17 6183 vmcs_read32(instr_len_field);
66fd3f7f
GN		 6184 /* fall through */
6185 case INTR_TYPE_HARD_EXCEPTION:
35920a35 6186 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
83422e17 6187 u32 err = vmcs_read32(error_code_field);
37b96e98 6188 kvm_queue_exception_e(&vmx->vcpu, vector, err);
35920a35
AK		 6189 } else
6190 kvm_queue_exception(&vmx->vcpu, vector);
37b96e98 6191 break;
66fd3f7f
GN		 6192 case INTR_TYPE_SOFT_INTR:
6193 vmx->vcpu.arch.event_exit_inst_len =
83422e17 6194 vmcs_read32(instr_len_field);
66fd3f7f 6195 /* fall through */
37b96e98 6196 case INTR_TYPE_EXT_INTR:
66fd3f7f
GN		 6197 kvm_queue_interrupt(&vmx->vcpu, vector,
6198 type == INTR_TYPE_SOFT_INTR);
37b96e98
GN		 6199 break;
6200 default:
6201 break;
f7d9238f 6202 }
cf393f75
AK		 6203}
6204
83422e17
AK		 6205static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
6206{
66c78ae4
NHE		 6207 if (is_guest_mode(&vmx->vcpu))
6208 return;
83422e17
AK		 6209 __vmx_complete_interrupts(vmx, vmx->idt_vectoring_info,
6210 VM_EXIT_INSTRUCTION_LEN,
6211 IDT_VECTORING_ERROR_CODE);
6212}
6213
b463a6f7
AK		 6214static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
6215{
66c78ae4
NHE		 6216 if (is_guest_mode(vcpu))
6217 return;
b463a6f7
AK		 6218 __vmx_complete_interrupts(to_vmx(vcpu),
6219 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
6220 VM_ENTRY_INSTRUCTION_LEN,
6221 VM_ENTRY_EXCEPTION_ERROR_CODE);
6222
6223 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
6224}
6225
d7cd9796
GN		 6226static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
6227{
6228 int i, nr_msrs;
6229 struct perf_guest_switch_msr *msrs;
6230
6231 msrs = perf_guest_get_msrs(&nr_msrs);
6232
6233 if (!msrs)
6234 return;
6235
6236 for (i = 0; i < nr_msrs; i++)
6237 if (msrs[i].host == msrs[i].guest)
6238 clear_atomic_switch_msr(vmx, msrs[i].msr);
6239 else
6240 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
6241 msrs[i].host);
6242}
6243
a3b5ba49 6244static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 6245{
a2fa3e9f 6246 struct vcpu_vmx *vmx = to_vmx(vcpu);
2a7921b7 6247 unsigned long debugctlmsr;
104f226b 6248
66c78ae4
NHE		 6249 if (is_guest_mode(vcpu) && !vmx->nested.nested_run_pending) {
6250 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6251 if (vmcs12->idt_vectoring_info_field &
6252 VECTORING_INFO_VALID_MASK) {
6253 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
6254 vmcs12->idt_vectoring_info_field);
6255 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
6256 vmcs12->vm_exit_instruction_len);
6257 if (vmcs12->idt_vectoring_info_field &
6258 VECTORING_INFO_DELIVER_CODE_MASK)
6259 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
6260 vmcs12->idt_vectoring_error_code);
6261 }
6262 }
6263
104f226b
AK		 6264 /* Record the guest's net vcpu time for enforced NMI injections. */
6265 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
6266 vmx->entry_time = ktime_get();
6267
6268 /* Don't enter VMX if guest state is invalid, let the exit handler
6269 start emulation until we arrive back to a valid state */
6270 if (vmx->emulation_required && emulate_invalid_guest_state)
6271 return;
6272
6273 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
6274 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
6275 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
6276 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
6277
6278 /* When single-stepping over STI and MOV SS, we must clear the
6279 * corresponding interruptibility bits in the guest state. Otherwise
6280 * vmentry fails as it then expects bit 14 (BS) in pending debug
6281 * exceptions being set, but that's not correct for the guest debugging
6282 * case. */
6283 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6284 vmx_set_interrupt_shadow(vcpu, 0);
6285
d7cd9796 6286 atomic_switch_perf_msrs(vmx);
2a7921b7 6287 debugctlmsr = get_debugctlmsr();
d7cd9796 6288
d462b819 6289 vmx->__launched = vmx->loaded_vmcs->launched;
104f226b 6290 asm(
6aa8b732 6291 /* Store host registers */
b188c81f
AK		 6292 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
6293 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
6294 "push %%" _ASM_CX " \n\t"
6295 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
313dbd49 6296 "je 1f \n\t"
b188c81f 6297 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
4ecac3fd 6298 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 6299 "1: \n\t"
d3edefc0 6300 /* Reload cr2 if changed */
b188c81f
AK		 6301 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
6302 "mov %%cr2, %%" _ASM_DX " \n\t"
6303 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
d3edefc0 6304 "je 2f \n\t"
b188c81f 6305 "mov %%" _ASM_AX", %%cr2 \n\t"
d3edefc0 6306 "2: \n\t"
6aa8b732 6307 /* Check if vmlaunch of vmresume is needed */
e08aa78a 6308 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 6309 /* Load guest registers. Don't clobber flags. */
b188c81f
AK		 6310 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
6311 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
6312 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
6313 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
6314 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
6315 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
05b3e0c2 6316#ifdef CONFIG_X86_64
e08aa78a
AK		 6317 "mov %c[r8](%0), %%r8 \n\t"
6318 "mov %c[r9](%0), %%r9 \n\t"
6319 "mov %c[r10](%0), %%r10 \n\t"
6320 "mov %c[r11](%0), %%r11 \n\t"
6321 "mov %c[r12](%0), %%r12 \n\t"
6322 "mov %c[r13](%0), %%r13 \n\t"
6323 "mov %c[r14](%0), %%r14 \n\t"
6324 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 6325#endif
b188c81f 6326 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
c801949d 6327
6aa8b732 6328 /* Enter guest mode */
83287ea4 6329 "jne 1f \n\t"
4ecac3fd 6330 __ex(ASM_VMX_VMLAUNCH) "\n\t"
83287ea4
AK		 6331 "jmp 2f \n\t"
6332 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
6333 "2: "
6aa8b732 6334 /* Save guest registers, load host registers, keep flags */
b188c81f 6335 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
40712fae 6336 "pop %0 \n\t"
b188c81f
AK		 6337 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
6338 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
6339 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
6340 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
6341 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
6342 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
6343 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
05b3e0c2 6344#ifdef CONFIG_X86_64
e08aa78a
AK		 6345 "mov %%r8, %c[r8](%0) \n\t"
6346 "mov %%r9, %c[r9](%0) \n\t"
6347 "mov %%r10, %c[r10](%0) \n\t"
6348 "mov %%r11, %c[r11](%0) \n\t"
6349 "mov %%r12, %c[r12](%0) \n\t"
6350 "mov %%r13, %c[r13](%0) \n\t"
6351 "mov %%r14, %c[r14](%0) \n\t"
6352 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 6353#endif
b188c81f
AK		 6354 "mov %%cr2, %%" _ASM_AX " \n\t"
6355 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
c801949d 6356
b188c81f 6357 "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t"
e08aa78a 6358 "setbe %c[fail](%0) \n\t"
83287ea4
AK		 6359 ".pushsection .rodata \n\t"
6360 ".global vmx_return \n\t"
6361 "vmx_return: " _ASM_PTR " 2b \n\t"
6362 ".popsection"
e08aa78a 6363 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
d462b819 6364 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
e08aa78a 6365 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 6366 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 6367 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
6368 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
6369 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
6370 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
6371 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
6372 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
6373 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 6374#ifdef CONFIG_X86_64
ad312c7c
ZX		 6375 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
6376 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
6377 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
6378 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
6379 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
6380 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
6381 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
6382 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 6383#endif
40712fae
AK		 6384 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
6385 [wordsize]"i"(sizeof(ulong))
c2036300
LV		 6386 : "cc", "memory"
6387#ifdef CONFIG_X86_64
b188c81f 6388 , "rax", "rbx", "rdi", "rsi"
c2036300 6389 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
b188c81f
AK		 6390#else
6391 , "eax", "ebx", "edi", "esi"
c2036300
LV		 6392#endif
6393 );
6aa8b732 6394
2a7921b7
GN		 6395 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
6396 if (debugctlmsr)
6397 update_debugctlmsr(debugctlmsr);
6398
aa67f609
AK		 6399#ifndef CONFIG_X86_64
6400 /*
6401 * The sysexit path does not restore ds/es, so we must set them to
6402 * a reasonable value ourselves.
6403 *
6404 * We can't defer this to vmx_load_host_state() since that function
6405 * may be executed in interrupt context, which saves and restore segments
6406 * around it, nullifying its effect.
6407 */
6408 loadsegment(ds, __USER_DS);
6409 loadsegment(es, __USER_DS);
6410#endif
6411
6de4f3ad 6412 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6de12732 6413 | (1 << VCPU_EXREG_RFLAGS)
69c73028 6414 | (1 << VCPU_EXREG_CPL)
aff48baa 6415 | (1 << VCPU_EXREG_PDPTR)
2fb92db1 6416 | (1 << VCPU_EXREG_SEGMENTS)
aff48baa 6417 | (1 << VCPU_EXREG_CR3));
5fdbf976
MT		 6418 vcpu->arch.regs_dirty = 0;
6419
1155f76a
AK		 6420 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
6421
66c78ae4
NHE		 6422 if (is_guest_mode(vcpu)) {
6423 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6424 vmcs12->idt_vectoring_info_field = vmx->idt_vectoring_info;
6425 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
6426 vmcs12->idt_vectoring_error_code =
6427 vmcs_read32(IDT_VECTORING_ERROR_CODE);
6428 vmcs12->vm_exit_instruction_len =
6429 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6430 }
6431 }
6432
d462b819 6433 vmx->loaded_vmcs->launched = 1;
1b6269db 6434
51aa01d1 6435 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
1e2b1dd7 6436 trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
51aa01d1
AK		 6437
6438 vmx_complete_atomic_exit(vmx);
6439 vmx_recover_nmi_blocking(vmx);
cf393f75 6440 vmx_complete_interrupts(vmx);
6aa8b732
AK		 6441}
6442
6aa8b732
AK		 6443static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
6444{
fb3f0f51
RR		 6445 struct vcpu_vmx *vmx = to_vmx(vcpu);
6446
cdbecfc3 6447 free_vpid(vmx);
ec378aee 6448 free_nested(vmx);
d462b819 6449 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51
RR		 6450 kfree(vmx->guest_msrs);
6451 kvm_vcpu_uninit(vcpu);
a4770347 6452 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 6453}
6454
fb3f0f51 6455static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 6456{
fb3f0f51 6457 int err;
c16f862d 6458 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 6459 int cpu;
6aa8b732 6460
a2fa3e9f 6461 if (!vmx)
fb3f0f51
RR		 6462 return ERR_PTR(-ENOMEM);
6463
2384d2b3
SY		 6464 allocate_vpid(vmx);
6465
fb3f0f51
RR		 6466 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
6467 if (err)
6468 goto free_vcpu;
965b58a5 6469
a2fa3e9f 6470 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
be6d05cf 6471 err = -ENOMEM;
fb3f0f51 6472 if (!vmx->guest_msrs) {
fb3f0f51
RR		 6473 goto uninit_vcpu;
6474 }
965b58a5 6475
d462b819
NHE		 6476 vmx->loaded_vmcs = &vmx->vmcs01;
6477 vmx->loaded_vmcs->vmcs = alloc_vmcs();
6478 if (!vmx->loaded_vmcs->vmcs)
fb3f0f51 6479 goto free_msrs;
d462b819
NHE		 6480 if (!vmm_exclusive)
6481 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
6482 loaded_vmcs_init(vmx->loaded_vmcs);
6483 if (!vmm_exclusive)
6484 kvm_cpu_vmxoff();
a2fa3e9f 6485
15ad7146
AK		 6486 cpu = get_cpu();
6487 vmx_vcpu_load(&vmx->vcpu, cpu);
e48672fa 6488 vmx->vcpu.cpu = cpu;
8b9cf98c 6489 err = vmx_vcpu_setup(vmx);
fb3f0f51 6490 vmx_vcpu_put(&vmx->vcpu);
15ad7146 6491 put_cpu();
fb3f0f51
RR		 6492 if (err)
6493 goto free_vmcs;
5e4a0b3c 6494 if (vm_need_virtualize_apic_accesses(kvm))
be6d05cf
JK		 6495 err = alloc_apic_access_page(kvm);
6496 if (err)
5e4a0b3c 6497 goto free_vmcs;
fb3f0f51 6498
b927a3ce
SY		 6499 if (enable_ept) {
6500 if (!kvm->arch.ept_identity_map_addr)
6501 kvm->arch.ept_identity_map_addr =
6502 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
93ea5388 6503 err = -ENOMEM;
b7ebfb05
SY		 6504 if (alloc_identity_pagetable(kvm) != 0)
6505 goto free_vmcs;
93ea5388
GN		 6506 if (!init_rmode_identity_map(kvm))
6507 goto free_vmcs;
b927a3ce 6508 }
b7ebfb05 6509
a9d30f33
NHE		 6510 vmx->nested.current_vmptr = -1ull;
6511 vmx->nested.current_vmcs12 = NULL;
6512
fb3f0f51
RR		 6513 return &vmx->vcpu;
6514
6515free_vmcs:
5f3fbc34 6516 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51 6517free_msrs:
fb3f0f51
RR		 6518 kfree(vmx->guest_msrs);
6519uninit_vcpu:
6520 kvm_vcpu_uninit(&vmx->vcpu);
6521free_vcpu:
cdbecfc3 6522 free_vpid(vmx);
a4770347 6523 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 6524 return ERR_PTR(err);
6aa8b732
AK		 6525}
6526
002c7f7c
YS		 6527static void __init vmx_check_processor_compat(void *rtn)
6528{
6529 struct vmcs_config vmcs_conf;
6530
6531 *(int *)rtn = 0;
6532 if (setup_vmcs_config(&vmcs_conf) < 0)
6533 *(int *)rtn = -EIO;
6534 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
6535 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
6536 smp_processor_id());
6537 *(int *)rtn = -EIO;
6538 }
6539}
6540
67253af5
SY		 6541static int get_ept_level(void)
6542{
6543 return VMX_EPT_DEFAULT_GAW + 1;
6544}
6545
4b12f0de 6546static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 6547{
4b12f0de
SY		 6548 u64 ret;
6549
522c68c4
SY		 6550 /* For VT-d and EPT combination
6551 * 1. MMIO: always map as UC
6552 * 2. EPT with VT-d:
6553 * a. VT-d without snooping control feature: can't guarantee the
6554 * result, try to trust guest.
6555 * b. VT-d with snooping control feature: snooping control feature of
6556 * VT-d engine can guarantee the cache correctness. Just set it
6557 * to WB to keep consistent with host. So the same as item 3.
a19a6d11 6558 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
522c68c4
SY		 6559 * consistent with host MTRR
6560 */
4b12f0de
SY		 6561 if (is_mmio)
6562 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
522c68c4
SY		 6563 else if (vcpu->kvm->arch.iommu_domain &&
6564 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
6565 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
6566 VMX_EPT_MT_EPTE_SHIFT;
4b12f0de 6567 else
522c68c4 6568 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
a19a6d11 6569 | VMX_EPT_IPAT_BIT;
4b12f0de
SY		 6570
6571 return ret;
64d4d521
SY		 6572}
6573
17cc3935 6574static int vmx_get_lpage_level(void)
344f414f 6575{
878403b7
SY		 6576 if (enable_ept && !cpu_has_vmx_ept_1g_page())
6577 return PT_DIRECTORY_LEVEL;
6578 else
6579 /* For shadow and EPT supported 1GB page */
6580 return PT_PDPE_LEVEL;
344f414f
JR		 6581}
6582
0e851880
SY		 6583static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
6584{
4e47c7a6
SY		 6585 struct kvm_cpuid_entry2 *best;
6586 struct vcpu_vmx *vmx = to_vmx(vcpu);
6587 u32 exec_control;
6588
6589 vmx->rdtscp_enabled = false;
6590 if (vmx_rdtscp_supported()) {
6591 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6592 if (exec_control & SECONDARY_EXEC_RDTSCP) {
6593 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
6594 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
6595 vmx->rdtscp_enabled = true;
6596 else {
6597 exec_control &= ~SECONDARY_EXEC_RDTSCP;
6598 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6599 exec_control);
6600 }
6601 }
6602 }
ad756a16 6603
ad756a16
MJ		 6604 /* Exposing INVPCID only when PCID is exposed */
6605 best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
6606 if (vmx_invpcid_supported() &&
4f977045 6607 best && (best->ebx & bit(X86_FEATURE_INVPCID)) &&
ad756a16 6608 guest_cpuid_has_pcid(vcpu)) {
29282fde 6609 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
ad756a16
MJ		 6610 exec_control |= SECONDARY_EXEC_ENABLE_INVPCID;
6611 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6612 exec_control);
6613 } else {
29282fde
TI		 6614 if (cpu_has_secondary_exec_ctrls()) {
6615 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6616 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
6617 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6618 exec_control);
6619 }
ad756a16 6620 if (best)
4f977045 6621 best->ebx &= ~bit(X86_FEATURE_INVPCID);
ad756a16 6622 }
0e851880
SY		 6623}
6624
d4330ef2
JR		 6625static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
6626{
7b8050f5
NHE		 6627 if (func == 1 && nested)
6628 entry->ecx |= bit(X86_FEATURE_VMX);
d4330ef2
JR		 6629}
6630
fe3ef05c
NHE		 6631/*
6632 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
6633 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
6634 * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
6635 * guest in a way that will both be appropriate to L1's requests, and our
6636 * needs. In addition to modifying the active vmcs (which is vmcs02), this
6637 * function also has additional necessary side-effects, like setting various
6638 * vcpu->arch fields.
6639 */
6640static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6641{
6642 struct vcpu_vmx *vmx = to_vmx(vcpu);
6643 u32 exec_control;
6644
6645 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
6646 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
6647 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
6648 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
6649 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
6650 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
6651 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
6652 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
6653 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
6654 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
6655 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
6656 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
6657 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
6658 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
6659 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
6660 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
6661 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
6662 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
6663 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
6664 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
6665 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
6666 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
6667 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
6668 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
6669 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
6670 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
6671 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
6672 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
6673 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
6674 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
6675 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
6676 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
6677 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
6678 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
6679 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
6680 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
6681
6682 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
6683 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
6684 vmcs12->vm_entry_intr_info_field);
6685 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
6686 vmcs12->vm_entry_exception_error_code);
6687 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
6688 vmcs12->vm_entry_instruction_len);
6689 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
6690 vmcs12->guest_interruptibility_info);
6691 vmcs_write32(GUEST_ACTIVITY_STATE, vmcs12->guest_activity_state);
6692 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
6693 vmcs_writel(GUEST_DR7, vmcs12->guest_dr7);
6694 vmcs_writel(GUEST_RFLAGS, vmcs12->guest_rflags);
6695 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
6696 vmcs12->guest_pending_dbg_exceptions);
6697 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
6698 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
6699
6700 vmcs_write64(VMCS_LINK_POINTER, -1ull);
6701
6702 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
6703 (vmcs_config.pin_based_exec_ctrl |
6704 vmcs12->pin_based_vm_exec_control));
6705
6706 /*
6707 * Whether page-faults are trapped is determined by a combination of
6708 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
6709 * If enable_ept, L0 doesn't care about page faults and we should
6710 * set all of these to L1's desires. However, if !enable_ept, L0 does
6711 * care about (at least some) page faults, and because it is not easy
6712 * (if at all possible?) to merge L0 and L1's desires, we simply ask
6713 * to exit on each and every L2 page fault. This is done by setting
6714 * MASK=MATCH=0 and (see below) EB.PF=1.
6715 * Note that below we don't need special code to set EB.PF beyond the
6716 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
6717 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
6718 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
6719 *
6720 * A problem with this approach (when !enable_ept) is that L1 may be
6721 * injected with more page faults than it asked for. This could have
6722 * caused problems, but in practice existing hypervisors don't care.
6723 * To fix this, we will need to emulate the PFEC checking (on the L1
6724 * page tables), using walk_addr(), when injecting PFs to L1.
6725 */
6726 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
6727 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
6728 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
6729 enable_ept ? vmcs12->page_fault_error_code_match : 0);
6730
6731 if (cpu_has_secondary_exec_ctrls()) {
6732 u32 exec_control = vmx_secondary_exec_control(vmx);
6733 if (!vmx->rdtscp_enabled)
6734 exec_control &= ~SECONDARY_EXEC_RDTSCP;
6735 /* Take the following fields only from vmcs12 */
6736 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6737 if (nested_cpu_has(vmcs12,
6738 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
6739 exec_control |= vmcs12->secondary_vm_exec_control;
6740
6741 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
6742 /*
6743 * Translate L1 physical address to host physical
6744 * address for vmcs02. Keep the page pinned, so this
6745 * physical address remains valid. We keep a reference
6746 * to it so we can release it later.
6747 */
6748 if (vmx->nested.apic_access_page) /* shouldn't happen */
6749 nested_release_page(vmx->nested.apic_access_page);
6750 vmx->nested.apic_access_page =
6751 nested_get_page(vcpu, vmcs12->apic_access_addr);
6752 /*
6753 * If translation failed, no matter: This feature asks
6754 * to exit when accessing the given address, and if it
6755 * can never be accessed, this feature won't do
6756 * anything anyway.
6757 */
6758 if (!vmx->nested.apic_access_page)
6759 exec_control &=
6760 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6761 else
6762 vmcs_write64(APIC_ACCESS_ADDR,
6763 page_to_phys(vmx->nested.apic_access_page));
6764 }
6765
6766 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6767 }
6768
6769
6770 /*
6771 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
6772 * Some constant fields are set here by vmx_set_constant_host_state().
6773 * Other fields are different per CPU, and will be set later when
6774 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
6775 */
6776 vmx_set_constant_host_state();
6777
6778 /*
6779 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
6780 * entry, but only if the current (host) sp changed from the value
6781 * we wrote last (vmx->host_rsp). This cache is no longer relevant
6782 * if we switch vmcs, and rather than hold a separate cache per vmcs,
6783 * here we just force the write to happen on entry.
6784 */
6785 vmx->host_rsp = 0;
6786
6787 exec_control = vmx_exec_control(vmx); /* L0's desires */
6788 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
6789 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
6790 exec_control &= ~CPU_BASED_TPR_SHADOW;
6791 exec_control |= vmcs12->cpu_based_vm_exec_control;
6792 /*
6793 * Merging of IO and MSR bitmaps not currently supported.
6794 * Rather, exit every time.
6795 */
6796 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
6797 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
6798 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
6799
6800 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
6801
6802 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
6803 * bitwise-or of what L1 wants to trap for L2, and what we want to
6804 * trap. Note that CR0.TS also needs updating - we do this later.
6805 */
6806 update_exception_bitmap(vcpu);
6807 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
6808 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
6809
6810 /* Note: IA32_MODE, LOAD_IA32_EFER are modified by vmx_set_efer below */
6811 vmcs_write32(VM_EXIT_CONTROLS,
6812 vmcs12->vm_exit_controls | vmcs_config.vmexit_ctrl);
6813 vmcs_write32(VM_ENTRY_CONTROLS, vmcs12->vm_entry_controls |
6814 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
6815
6816 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)
6817 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
6818 else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
6819 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
6820
6821
6822 set_cr4_guest_host_mask(vmx);
6823
27fc51b2
NHE		 6824 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
6825 vmcs_write64(TSC_OFFSET,
6826 vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
6827 else
6828 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
fe3ef05c
NHE		 6829
6830 if (enable_vpid) {
6831 /*
6832 * Trivially support vpid by letting L2s share their parent
6833 * L1's vpid. TODO: move to a more elaborate solution, giving
6834 * each L2 its own vpid and exposing the vpid feature to L1.
6835 */
6836 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
6837 vmx_flush_tlb(vcpu);
6838 }
6839
6840 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
6841 vcpu->arch.efer = vmcs12->guest_ia32_efer;
6842 if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
6843 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
6844 else
6845 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
6846 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
6847 vmx_set_efer(vcpu, vcpu->arch.efer);
6848
6849 /*
6850 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
6851 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
6852 * The CR0_READ_SHADOW is what L2 should have expected to read given
6853 * the specifications by L1; It's not enough to take
6854 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
6855 * have more bits than L1 expected.
6856 */
6857 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
6858 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
6859
6860 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
6861 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
6862
6863 /* shadow page tables on either EPT or shadow page tables */
6864 kvm_set_cr3(vcpu, vmcs12->guest_cr3);
6865 kvm_mmu_reset_context(vcpu);
6866
6867 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
6868 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
6869}
6870
cd232ad0
NHE		 6871/*
6872 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
6873 * for running an L2 nested guest.
6874 */
6875static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
6876{
6877 struct vmcs12 *vmcs12;
6878 struct vcpu_vmx *vmx = to_vmx(vcpu);
6879 int cpu;
6880 struct loaded_vmcs *vmcs02;
6881
6882 if (!nested_vmx_check_permission(vcpu) ||
6883 !nested_vmx_check_vmcs12(vcpu))
6884 return 1;
6885
6886 skip_emulated_instruction(vcpu);
6887 vmcs12 = get_vmcs12(vcpu);
6888
7c177938
NHE		 6889 /*
6890 * The nested entry process starts with enforcing various prerequisites
6891 * on vmcs12 as required by the Intel SDM, and act appropriately when
6892 * they fail: As the SDM explains, some conditions should cause the
6893 * instruction to fail, while others will cause the instruction to seem
6894 * to succeed, but return an EXIT_REASON_INVALID_STATE.
6895 * To speed up the normal (success) code path, we should avoid checking
6896 * for misconfigurations which will anyway be caught by the processor
6897 * when using the merged vmcs02.
6898 */
6899 if (vmcs12->launch_state == launch) {
6900 nested_vmx_failValid(vcpu,
6901 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
6902 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
6903 return 1;
6904 }
6905
6906 if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
6907 !IS_ALIGNED(vmcs12->msr_bitmap, PAGE_SIZE)) {
6908 /*TODO: Also verify bits beyond physical address width are 0*/
6909 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6910 return 1;
6911 }
6912
6913 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
6914 !IS_ALIGNED(vmcs12->apic_access_addr, PAGE_SIZE)) {
6915 /*TODO: Also verify bits beyond physical address width are 0*/
6916 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6917 return 1;
6918 }
6919
6920 if (vmcs12->vm_entry_msr_load_count > 0 ||
6921 vmcs12->vm_exit_msr_load_count > 0 ||
6922 vmcs12->vm_exit_msr_store_count > 0) {
bd80158a
JK		 6923 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
6924 __func__);
7c177938
NHE		 6925 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6926 return 1;
6927 }
6928
6929 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
6930 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high) ||
6931 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
6932 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
6933 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
6934 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
6935 !vmx_control_verify(vmcs12->vm_exit_controls,
6936 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high) ||
6937 !vmx_control_verify(vmcs12->vm_entry_controls,
6938 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high))
6939 {
6940 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6941 return 1;
6942 }
6943
6944 if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
6945 ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
6946 nested_vmx_failValid(vcpu,
6947 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
6948 return 1;
6949 }
6950
6951 if (((vmcs12->guest_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
6952 ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
6953 nested_vmx_entry_failure(vcpu, vmcs12,
6954 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
6955 return 1;
6956 }
6957 if (vmcs12->vmcs_link_pointer != -1ull) {
6958 nested_vmx_entry_failure(vcpu, vmcs12,
6959 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
6960 return 1;
6961 }
6962
6963 /*
6964 * We're finally done with prerequisite checking, and can start with
6965 * the nested entry.
6966 */
6967
cd232ad0
NHE		 6968 vmcs02 = nested_get_current_vmcs02(vmx);
6969 if (!vmcs02)
6970 return -ENOMEM;
6971
6972 enter_guest_mode(vcpu);
6973
6974 vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
6975
6976 cpu = get_cpu();
6977 vmx->loaded_vmcs = vmcs02;
6978 vmx_vcpu_put(vcpu);
6979 vmx_vcpu_load(vcpu, cpu);
6980 vcpu->cpu = cpu;
6981 put_cpu();
6982
6983 vmcs12->launch_state = 1;
6984
6985 prepare_vmcs02(vcpu, vmcs12);
6986
6987 /*
6988 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
6989 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
6990 * returned as far as L1 is concerned. It will only return (and set
6991 * the success flag) when L2 exits (see nested_vmx_vmexit()).
6992 */
6993 return 1;
6994}
6995
4704d0be
NHE		 6996/*
6997 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
6998 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
6999 * This function returns the new value we should put in vmcs12.guest_cr0.
7000 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
7001 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
7002 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
7003 * didn't trap the bit, because if L1 did, so would L0).
7004 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
7005 * been modified by L2, and L1 knows it. So just leave the old value of
7006 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
7007 * isn't relevant, because if L0 traps this bit it can set it to anything.
7008 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
7009 * changed these bits, and therefore they need to be updated, but L0
7010 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
7011 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
7012 */
7013static inline unsigned long
7014vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7015{
7016 return
7017 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
7018 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
7019 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
7020 vcpu->arch.cr0_guest_owned_bits));
7021}
7022
7023static inline unsigned long
7024vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7025{
7026 return
7027 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
7028 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
7029 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
7030 vcpu->arch.cr4_guest_owned_bits));
7031}
7032
7033/*
7034 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
7035 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
7036 * and this function updates it to reflect the changes to the guest state while
7037 * L2 was running (and perhaps made some exits which were handled directly by L0
7038 * without going back to L1), and to reflect the exit reason.
7039 * Note that we do not have to copy here all VMCS fields, just those that
7040 * could have changed by the L2 guest or the exit - i.e., the guest-state and
7041 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
7042 * which already writes to vmcs12 directly.
7043 */
7044void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7045{
7046 /* update guest state fields: */
7047 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
7048 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
7049
7050 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
7051 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
7052 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
7053 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
7054
7055 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
7056 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
7057 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
7058 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
7059 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
7060 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
7061 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
7062 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
7063 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
7064 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
7065 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
7066 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
7067 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
7068 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
7069 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
7070 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
7071 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
7072 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
7073 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
7074 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
7075 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
7076 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
7077 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
7078 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
7079 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
7080 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
7081 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
7082 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
7083 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
7084 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
7085 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
7086 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
7087 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
7088 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
7089 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
7090 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
7091
7092 vmcs12->guest_activity_state = vmcs_read32(GUEST_ACTIVITY_STATE);
7093 vmcs12->guest_interruptibility_info =
7094 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
7095 vmcs12->guest_pending_dbg_exceptions =
7096 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
7097
7098 /* TODO: These cannot have changed unless we have MSR bitmaps and
7099 * the relevant bit asks not to trap the change */
7100 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
7101 if (vmcs12->vm_entry_controls & VM_EXIT_SAVE_IA32_PAT)
7102 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
7103 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
7104 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
7105 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
7106
7107 /* update exit information fields: */
7108
7109 vmcs12->vm_exit_reason = vmcs_read32(VM_EXIT_REASON);
7110 vmcs12->exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7111
7112 vmcs12->vm_exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7113 vmcs12->vm_exit_intr_error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
7114 vmcs12->idt_vectoring_info_field =
7115 vmcs_read32(IDT_VECTORING_INFO_FIELD);
7116 vmcs12->idt_vectoring_error_code =
7117 vmcs_read32(IDT_VECTORING_ERROR_CODE);
7118 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
7119 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7120
7121 /* clear vm-entry fields which are to be cleared on exit */
7122 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
7123 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
7124}
7125
7126/*
7127 * A part of what we need to when the nested L2 guest exits and we want to
7128 * run its L1 parent, is to reset L1's guest state to the host state specified
7129 * in vmcs12.
7130 * This function is to be called not only on normal nested exit, but also on
7131 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
7132 * Failures During or After Loading Guest State").
7133 * This function should be called when the active VMCS is L1's (vmcs01).
7134 */
7135void load_vmcs12_host_state(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7136{
7137 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
7138 vcpu->arch.efer = vmcs12->host_ia32_efer;
7139 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
7140 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
7141 else
7142 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
7143 vmx_set_efer(vcpu, vcpu->arch.efer);
7144
7145 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
7146 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
7147 /*
7148 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
7149 * actually changed, because it depends on the current state of
7150 * fpu_active (which may have changed).
7151 * Note that vmx_set_cr0 refers to efer set above.
7152 */
7153 kvm_set_cr0(vcpu, vmcs12->host_cr0);
7154 /*
7155 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
7156 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
7157 * but we also need to update cr0_guest_host_mask and exception_bitmap.
7158 */
7159 update_exception_bitmap(vcpu);
7160 vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
7161 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
7162
7163 /*
7164 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
7165 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
7166 */
7167 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
7168 kvm_set_cr4(vcpu, vmcs12->host_cr4);
7169
7170 /* shadow page tables on either EPT or shadow page tables */
7171 kvm_set_cr3(vcpu, vmcs12->host_cr3);
7172 kvm_mmu_reset_context(vcpu);
7173
7174 if (enable_vpid) {
7175 /*
7176 * Trivially support vpid by letting L2s share their parent
7177 * L1's vpid. TODO: move to a more elaborate solution, giving
7178 * each L2 its own vpid and exposing the vpid feature to L1.
7179 */
7180 vmx_flush_tlb(vcpu);
7181 }
7182
7183
7184 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
7185 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
7186 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
7187 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
7188 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
7189 vmcs_writel(GUEST_TR_BASE, vmcs12->host_tr_base);
7190 vmcs_writel(GUEST_GS_BASE, vmcs12->host_gs_base);
7191 vmcs_writel(GUEST_FS_BASE, vmcs12->host_fs_base);
7192 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->host_es_selector);
7193 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->host_cs_selector);
7194 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->host_ss_selector);
7195 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->host_ds_selector);
7196 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->host_fs_selector);
7197 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->host_gs_selector);
7198 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->host_tr_selector);
7199
7200 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT)
7201 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
7202 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
7203 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
7204 vmcs12->host_ia32_perf_global_ctrl);
7205}
7206
7207/*
7208 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
7209 * and modify vmcs12 to make it see what it would expect to see there if
7210 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
7211 */
7212static void nested_vmx_vmexit(struct kvm_vcpu *vcpu)
7213{
7214 struct vcpu_vmx *vmx = to_vmx(vcpu);
7215 int cpu;
7216 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7217
7218 leave_guest_mode(vcpu);
7219 prepare_vmcs12(vcpu, vmcs12);
7220
7221 cpu = get_cpu();
7222 vmx->loaded_vmcs = &vmx->vmcs01;
7223 vmx_vcpu_put(vcpu);
7224 vmx_vcpu_load(vcpu, cpu);
7225 vcpu->cpu = cpu;
7226 put_cpu();
7227
7228 /* if no vmcs02 cache requested, remove the one we used */
7229 if (VMCS02_POOL_SIZE == 0)
7230 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
7231
7232 load_vmcs12_host_state(vcpu, vmcs12);
7233
27fc51b2 7234 /* Update TSC_OFFSET if TSC was changed while L2 ran */
4704d0be
NHE		 7235 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
7236
7237 /* This is needed for same reason as it was needed in prepare_vmcs02 */
7238 vmx->host_rsp = 0;
7239
7240 /* Unpin physical memory we referred to in vmcs02 */
7241 if (vmx->nested.apic_access_page) {
7242 nested_release_page(vmx->nested.apic_access_page);
7243 vmx->nested.apic_access_page = 0;
7244 }
7245
7246 /*
7247 * Exiting from L2 to L1, we're now back to L1 which thinks it just
7248 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
7249 * success or failure flag accordingly.
7250 */
7251 if (unlikely(vmx->fail)) {
7252 vmx->fail = 0;
7253 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
7254 } else
7255 nested_vmx_succeed(vcpu);
7256}
7257
7c177938
NHE		 7258/*
7259 * L1's failure to enter L2 is a subset of a normal exit, as explained in
7260 * 23.7 "VM-entry failures during or after loading guest state" (this also
7261 * lists the acceptable exit-reason and exit-qualification parameters).
7262 * It should only be called before L2 actually succeeded to run, and when
7263 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
7264 */
7265static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
7266 struct vmcs12 *vmcs12,
7267 u32 reason, unsigned long qualification)
7268{
7269 load_vmcs12_host_state(vcpu, vmcs12);
7270 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
7271 vmcs12->exit_qualification = qualification;
7272 nested_vmx_succeed(vcpu);
7273}
7274
8a76d7f2
JR		 7275static int vmx_check_intercept(struct kvm_vcpu *vcpu,
7276 struct x86_instruction_info *info,
7277 enum x86_intercept_stage stage)
7278{
7279 return X86EMUL_CONTINUE;
7280}
7281
cbdd1bea 7282static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 7283 .cpu_has_kvm_support = cpu_has_kvm_support,
7284 .disabled_by_bios = vmx_disabled_by_bios,
7285 .hardware_setup = hardware_setup,
7286 .hardware_unsetup = hardware_unsetup,
002c7f7c 7287 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 7288 .hardware_enable = hardware_enable,
7289 .hardware_disable = hardware_disable,
04547156 7290 .cpu_has_accelerated_tpr = report_flexpriority,
6aa8b732
AK		 7291
7292 .vcpu_create = vmx_create_vcpu,
7293 .vcpu_free = vmx_free_vcpu,
04d2cc77 7294 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 7295
04d2cc77 7296 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 7297 .vcpu_load = vmx_vcpu_load,
7298 .vcpu_put = vmx_vcpu_put,
7299
c8639010 7300 .update_db_bp_intercept = update_exception_bitmap,
6aa8b732
AK		 7301 .get_msr = vmx_get_msr,
7302 .set_msr = vmx_set_msr,
7303 .get_segment_base = vmx_get_segment_base,
7304 .get_segment = vmx_get_segment,
7305 .set_segment = vmx_set_segment,
2e4d2653 7306 .get_cpl = vmx_get_cpl,
6aa8b732 7307 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 7308 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
aff48baa 7309 .decache_cr3 = vmx_decache_cr3,
25c4c276 7310 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 7311 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 7312 .set_cr3 = vmx_set_cr3,
7313 .set_cr4 = vmx_set_cr4,
6aa8b732 7314 .set_efer = vmx_set_efer,
6aa8b732
AK		 7315 .get_idt = vmx_get_idt,
7316 .set_idt = vmx_set_idt,
7317 .get_gdt = vmx_get_gdt,
7318 .set_gdt = vmx_set_gdt,
020df079 7319 .set_dr7 = vmx_set_dr7,
5fdbf976 7320 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 7321 .get_rflags = vmx_get_rflags,
7322 .set_rflags = vmx_set_rflags,
ebcbab4c 7323 .fpu_activate = vmx_fpu_activate,
02daab21 7324 .fpu_deactivate = vmx_fpu_deactivate,
6aa8b732
AK		 7325
7326 .tlb_flush = vmx_flush_tlb,
6aa8b732 7327
6aa8b732 7328 .run = vmx_vcpu_run,
6062d012 7329 .handle_exit = vmx_handle_exit,
6aa8b732 7330 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 7331 .set_interrupt_shadow = vmx_set_interrupt_shadow,
7332 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 7333 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 7334 .set_irq = vmx_inject_irq,
95ba8273 7335 .set_nmi = vmx_inject_nmi,
298101da 7336 .queue_exception = vmx_queue_exception,
b463a6f7 7337 .cancel_injection = vmx_cancel_injection,
78646121 7338 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 7339 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 7340 .get_nmi_mask = vmx_get_nmi_mask,
7341 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 7342 .enable_nmi_window = enable_nmi_window,
7343 .enable_irq_window = enable_irq_window,
7344 .update_cr8_intercept = update_cr8_intercept,
95ba8273 7345
cbc94022 7346 .set_tss_addr = vmx_set_tss_addr,
67253af5 7347 .get_tdp_level = get_ept_level,
4b12f0de 7348 .get_mt_mask = vmx_get_mt_mask,
229456fc 7349
586f9607 7350 .get_exit_info = vmx_get_exit_info,
586f9607 7351
17cc3935 7352 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY		 7353
7354 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY		 7355
7356 .rdtscp_supported = vmx_rdtscp_supported,
ad756a16 7357 .invpcid_supported = vmx_invpcid_supported,
d4330ef2
JR		 7358
7359 .set_supported_cpuid = vmx_set_supported_cpuid,
f5f48ee1
SY		 7360
7361 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
99e3e30a 7362
4051b188 7363 .set_tsc_khz = vmx_set_tsc_khz,
ba904635 7364 .read_tsc_offset = vmx_read_tsc_offset,
99e3e30a 7365 .write_tsc_offset = vmx_write_tsc_offset,
e48672fa 7366 .adjust_tsc_offset = vmx_adjust_tsc_offset,
857e4099 7367 .compute_tsc_offset = vmx_compute_tsc_offset,
d5c1785d 7368 .read_l1_tsc = vmx_read_l1_tsc,
1c97f0a0
JR		 7369
7370 .set_tdp_cr3 = vmx_set_cr3,
8a76d7f2
JR		 7371
7372 .check_intercept = vmx_check_intercept,
6aa8b732
AK		 7373};
7374
7375static int __init vmx_init(void)
7376{
26bb0981
AK		 7377 int r, i;
7378
7379 rdmsrl_safe(MSR_EFER, &host_efer);
7380
7381 for (i = 0; i < NR_VMX_MSR; ++i)
7382 kvm_define_shared_msr(i, vmx_msr_index[i]);
fdef3ad1 7383
3e7c73e9 7384 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 7385 if (!vmx_io_bitmap_a)
7386 return -ENOMEM;
7387
2106a548
GC		 7388 r = -ENOMEM;
7389
3e7c73e9 7390 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 7391 if (!vmx_io_bitmap_b)
fdef3ad1 7392 goto out;
fdef3ad1 7393
5897297b 7394 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 7395 if (!vmx_msr_bitmap_legacy)
25c5f225 7396 goto out1;
2106a548 7397
25c5f225 7398
5897297b 7399 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 7400 if (!vmx_msr_bitmap_longmode)
5897297b 7401 goto out2;
2106a548 7402
5897297b 7403
fdef3ad1
HQ		 7404 /*
7405 * Allow direct access to the PC debug port (it is often used for I/O
7406 * delays, but the vmexits simply slow things down).
7407 */
3e7c73e9
AK		 7408 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
7409 clear_bit(0x80, vmx_io_bitmap_a);
fdef3ad1 7410
3e7c73e9 7411 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
fdef3ad1 7412
5897297b
AK		 7413 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
7414 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
25c5f225 7415
2384d2b3
SY		 7416 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
7417
0ee75bea
AK		 7418 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
7419 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 7420 if (r)
5897297b 7421 goto out3;
25c5f225 7422
8f536b76
ZY		 7423#ifdef CONFIG_KEXEC
7424 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
7425 crash_vmclear_local_loaded_vmcss);
7426#endif
7427
5897297b
AK		 7428 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
7429 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
7430 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
7431 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
7432 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
7433 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
fdef3ad1 7434
089d034e 7435 if (enable_ept) {
3f6d8c8a
XH		 7436 kvm_mmu_set_mask_ptes(0ull,
7437 (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
7438 (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
7439 0ull, VMX_EPT_EXECUTABLE_MASK);
ce88decf 7440 ept_set_mmio_spte_mask();
5fdbcb9d
SY		 7441 kvm_enable_tdp();
7442 } else
7443 kvm_disable_tdp();
1439442c 7444
fdef3ad1
HQ		 7445 return 0;
7446
5897297b
AK		 7447out3:
7448 free_page((unsigned long)vmx_msr_bitmap_longmode);
25c5f225 7449out2:
5897297b 7450 free_page((unsigned long)vmx_msr_bitmap_legacy);
fdef3ad1 7451out1:
3e7c73e9 7452 free_page((unsigned long)vmx_io_bitmap_b);
fdef3ad1 7453out:
3e7c73e9 7454 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 7455 return r;
6aa8b732
AK		 7456}
7457
7458static void __exit vmx_exit(void)
7459{
5897297b
AK		 7460 free_page((unsigned long)vmx_msr_bitmap_legacy);
7461 free_page((unsigned long)vmx_msr_bitmap_longmode);
3e7c73e9
AK		 7462 free_page((unsigned long)vmx_io_bitmap_b);
7463 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 7464
8f536b76
ZY		 7465#ifdef CONFIG_KEXEC
7466 rcu_assign_pointer(crash_vmclear_loaded_vmcss, NULL);
7467 synchronize_rcu();
7468#endif
7469
cb498ea2 7470 kvm_exit();
6aa8b732
AK		 7471}
7472
7473module_init(vmx_init)
7474module_exit(vmx_exit)
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