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KVM: ia64: Fix the build errors due to lack of macros related to MSI.
[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
8 *
9 * Authors:
10 * Avi Kivity <avi@qumranet.com>
11 * Yaniv Kamay <yaniv@qumranet.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
15 *
16 */
17
85f455f7 18#include "irq.h"
1d737c8a 19#include "mmu.h"
e495606d 20
edf88417 21#include <linux/kvm_host.h>
6aa8b732 22#include <linux/module.h>
9d8f549d 23#include <linux/kernel.h>
6aa8b732
AK		 24#include <linux/mm.h>
25#include <linux/highmem.h>
e8edc6e0 26#include <linux/sched.h>
c7addb90 27#include <linux/moduleparam.h>
5fdbf976 28#include "kvm_cache_regs.h"
35920a35 29#include "x86.h"
e495606d 30
6aa8b732 31#include <asm/io.h>
3b3be0d1 32#include <asm/desc.h>
13673a90 33#include <asm/vmx.h>
6210e37b 34#include <asm/virtext.h>
6aa8b732 35
4ecac3fd
AK		 36#define __ex(x) __kvm_handle_fault_on_reboot(x)
37
6aa8b732
AK		 38MODULE_AUTHOR("Qumranet");
39MODULE_LICENSE("GPL");
40
c7addb90
AK		 41static int bypass_guest_pf = 1;
42module_param(bypass_guest_pf, bool, 0);
43
2384d2b3
SY		 44static int enable_vpid = 1;
45module_param(enable_vpid, bool, 0);
46
4c9fc8ef
AK		 47static int flexpriority_enabled = 1;
48module_param(flexpriority_enabled, bool, 0);
49
1439442c 50static int enable_ept = 1;
d56f546d
SY		 51module_param(enable_ept, bool, 0);
52
04fa4d32
MG		 53static int emulate_invalid_guest_state = 0;
54module_param(emulate_invalid_guest_state, bool, 0);
55
a2fa3e9f
GH		 56struct vmcs {
57 u32 revision_id;
58 u32 abort;
59 char data[0];
60};
61
62struct vcpu_vmx {
fb3f0f51 63 struct kvm_vcpu vcpu;
543e4243 64 struct list_head local_vcpus_link;
313dbd49 65 unsigned long host_rsp;
a2fa3e9f 66 int launched;
29bd8a78 67 u8 fail;
1155f76a 68 u32 idt_vectoring_info;
a2fa3e9f
GH		 69 struct kvm_msr_entry *guest_msrs;
70 struct kvm_msr_entry *host_msrs;
71 int nmsrs;
72 int save_nmsrs;
73 int msr_offset_efer;
74#ifdef CONFIG_X86_64
75 int msr_offset_kernel_gs_base;
76#endif
77 struct vmcs *vmcs;
78 struct {
79 int loaded;
80 u16 fs_sel, gs_sel, ldt_sel;
152d3f2f
LV		 81 int gs_ldt_reload_needed;
82 int fs_reload_needed;
51c6cf66 83 int guest_efer_loaded;
d77c26fc 84 } host_state;
9c8cba37
AK		 85 struct {
86 struct {
87 bool pending;
88 u8 vector;
89 unsigned rip;
90 } irq;
91 } rmode;
2384d2b3 92 int vpid;
04fa4d32 93 bool emulation_required;
8b3079a5 94 enum emulation_result invalid_state_emulation_result;
3b86cd99
JK		 95
96 /* Support for vnmi-less CPUs */
97 int soft_vnmi_blocked;
98 ktime_t entry_time;
99 s64 vnmi_blocked_time;
a2fa3e9f
GH		 100};
101
102static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
103{
fb3f0f51 104 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 105}
106
b7ebfb05 107static int init_rmode(struct kvm *kvm);
4e1096d2 108static u64 construct_eptp(unsigned long root_hpa);
75880a01 109
6aa8b732
AK		 110static DEFINE_PER_CPU(struct vmcs *, vmxarea);
111static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
543e4243 112static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu);
6aa8b732 113
fdef3ad1
HQ		 114static struct page *vmx_io_bitmap_a;
115static struct page *vmx_io_bitmap_b;
25c5f225 116static struct page *vmx_msr_bitmap;
fdef3ad1 117
2384d2b3
SY		 118static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
119static DEFINE_SPINLOCK(vmx_vpid_lock);
120
1c3d14fe 121static struct vmcs_config {
6aa8b732
AK		 122 int size;
123 int order;
124 u32 revision_id;
1c3d14fe
YS		 125 u32 pin_based_exec_ctrl;
126 u32 cpu_based_exec_ctrl;
f78e0e2e 127 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 128 u32 vmexit_ctrl;
129 u32 vmentry_ctrl;
130} vmcs_config;
6aa8b732 131
efff9e53 132static struct vmx_capability {
d56f546d
SY		 133 u32 ept;
134 u32 vpid;
135} vmx_capability;
136
6aa8b732
AK		 137#define VMX_SEGMENT_FIELD(seg) \
138 [VCPU_SREG_##seg] = { \
139 .selector = GUEST_##seg##_SELECTOR, \
140 .base = GUEST_##seg##_BASE, \
141 .limit = GUEST_##seg##_LIMIT, \
142 .ar_bytes = GUEST_##seg##_AR_BYTES, \
143 }
144
145static struct kvm_vmx_segment_field {
146 unsigned selector;
147 unsigned base;
148 unsigned limit;
149 unsigned ar_bytes;
150} kvm_vmx_segment_fields[] = {
151 VMX_SEGMENT_FIELD(CS),
152 VMX_SEGMENT_FIELD(DS),
153 VMX_SEGMENT_FIELD(ES),
154 VMX_SEGMENT_FIELD(FS),
155 VMX_SEGMENT_FIELD(GS),
156 VMX_SEGMENT_FIELD(SS),
157 VMX_SEGMENT_FIELD(TR),
158 VMX_SEGMENT_FIELD(LDTR),
159};
160
4d56c8a7
AK		 161/*
162 * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
163 * away by decrementing the array size.
164 */
6aa8b732 165static const u32 vmx_msr_index[] = {
05b3e0c2 166#ifdef CONFIG_X86_64
6aa8b732
AK		 167 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, MSR_KERNEL_GS_BASE,
168#endif
169 MSR_EFER, MSR_K6_STAR,
170};
9d8f549d 171#define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
6aa8b732 172
a2fa3e9f
GH		 173static void load_msrs(struct kvm_msr_entry *e, int n)
174{
175 int i;
176
177 for (i = 0; i < n; ++i)
178 wrmsrl(e[i].index, e[i].data);
179}
180
181static void save_msrs(struct kvm_msr_entry *e, int n)
182{
183 int i;
184
185 for (i = 0; i < n; ++i)
186 rdmsrl(e[i].index, e[i].data);
187}
188
6aa8b732
AK		 189static inline int is_page_fault(u32 intr_info)
190{
191 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
192 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 193 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 194}
195
2ab455cc
AL		 196static inline int is_no_device(u32 intr_info)
197{
198 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
199 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 200 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 201}
202
7aa81cc0
AL		 203static inline int is_invalid_opcode(u32 intr_info)
204{
205 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
206 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 207 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 208}
209
6aa8b732
AK		 210static inline int is_external_interrupt(u32 intr_info)
211{
212 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
213 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
214}
215
25c5f225
SY		 216static inline int cpu_has_vmx_msr_bitmap(void)
217{
218 return (vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS);
219}
220
6e5d865c
YS		 221static inline int cpu_has_vmx_tpr_shadow(void)
222{
223 return (vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW);
224}
225
226static inline int vm_need_tpr_shadow(struct kvm *kvm)
227{
228 return ((cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm)));
229}
230
f78e0e2e
SY		 231static inline int cpu_has_secondary_exec_ctrls(void)
232{
233 return (vmcs_config.cpu_based_exec_ctrl &
234 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS);
235}
236
774ead3a 237static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 238{
4c9fc8ef
AK		 239 return flexpriority_enabled
240 && (vmcs_config.cpu_based_2nd_exec_ctrl &
241 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
f78e0e2e
SY		 242}
243
d56f546d
SY		 244static inline int cpu_has_vmx_invept_individual_addr(void)
245{
246 return (!!(vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT));
247}
248
249static inline int cpu_has_vmx_invept_context(void)
250{
251 return (!!(vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT));
252}
253
254static inline int cpu_has_vmx_invept_global(void)
255{
256 return (!!(vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT));
257}
258
259static inline int cpu_has_vmx_ept(void)
260{
261 return (vmcs_config.cpu_based_2nd_exec_ctrl &
262 SECONDARY_EXEC_ENABLE_EPT);
263}
264
265static inline int vm_need_ept(void)
266{
267 return (cpu_has_vmx_ept() && enable_ept);
268}
269
f78e0e2e
SY		 270static inline int vm_need_virtualize_apic_accesses(struct kvm *kvm)
271{
272 return ((cpu_has_vmx_virtualize_apic_accesses()) &&
273 (irqchip_in_kernel(kvm)));
274}
275
2384d2b3
SY		 276static inline int cpu_has_vmx_vpid(void)
277{
278 return (vmcs_config.cpu_based_2nd_exec_ctrl &
279 SECONDARY_EXEC_ENABLE_VPID);
280}
281
f08864b4
SY		 282static inline int cpu_has_virtual_nmis(void)
283{
284 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
285}
286
8b9cf98c 287static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 288{
289 int i;
290
a2fa3e9f
GH		 291 for (i = 0; i < vmx->nmsrs; ++i)
292 if (vmx->guest_msrs[i].index == msr)
a75beee6
ED		 293 return i;
294 return -1;
295}
296
2384d2b3
SY		 297static inline void __invvpid(int ext, u16 vpid, gva_t gva)
298{
299 struct {
300 u64 vpid : 16;
301 u64 rsvd : 48;
302 u64 gva;
303 } operand = { vpid, 0, gva };
304
4ecac3fd 305 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 306 /* CF==1 or ZF==1 --> rc = -1 */
307 "; ja 1f ; ud2 ; 1:"
308 : : "a"(&operand), "c"(ext) : "cc", "memory");
309}
310
1439442c
SY		 311static inline void __invept(int ext, u64 eptp, gpa_t gpa)
312{
313 struct {
314 u64 eptp, gpa;
315 } operand = {eptp, gpa};
316
4ecac3fd 317 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 318 /* CF==1 or ZF==1 --> rc = -1 */
319 "; ja 1f ; ud2 ; 1:\n"
320 : : "a" (&operand), "c" (ext) : "cc", "memory");
321}
322
8b9cf98c 323static struct kvm_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 324{
325 int i;
326
8b9cf98c 327 i = __find_msr_index(vmx, msr);
a75beee6 328 if (i >= 0)
a2fa3e9f 329 return &vmx->guest_msrs[i];
8b6d44c7 330 return NULL;
7725f0ba
AK		 331}
332
6aa8b732
AK		 333static void vmcs_clear(struct vmcs *vmcs)
334{
335 u64 phys_addr = __pa(vmcs);
336 u8 error;
337
4ecac3fd 338 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
6aa8b732
AK		 339 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
340 : "cc", "memory");
341 if (error)
342 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
343 vmcs, phys_addr);
344}
345
346static void __vcpu_clear(void *arg)
347{
8b9cf98c 348 struct vcpu_vmx *vmx = arg;
d3b2c338 349 int cpu = raw_smp_processor_id();
6aa8b732 350
8b9cf98c 351 if (vmx->vcpu.cpu == cpu)
a2fa3e9f
GH		 352 vmcs_clear(vmx->vmcs);
353 if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
6aa8b732 354 per_cpu(current_vmcs, cpu) = NULL;
ad312c7c 355 rdtscll(vmx->vcpu.arch.host_tsc);
543e4243
AK		 356 list_del(&vmx->local_vcpus_link);
357 vmx->vcpu.cpu = -1;
358 vmx->launched = 0;
6aa8b732
AK		 359}
360
8b9cf98c 361static void vcpu_clear(struct vcpu_vmx *vmx)
8d0be2b3 362{
eae5ecb5
AK		 363 if (vmx->vcpu.cpu == -1)
364 return;
8691e5a8 365 smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1);
8d0be2b3
AK		 366}
367
2384d2b3
SY		 368static inline void vpid_sync_vcpu_all(struct vcpu_vmx *vmx)
369{
370 if (vmx->vpid == 0)
371 return;
372
373 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
374}
375
1439442c
SY		 376static inline void ept_sync_global(void)
377{
378 if (cpu_has_vmx_invept_global())
379 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
380}
381
382static inline void ept_sync_context(u64 eptp)
383{
384 if (vm_need_ept()) {
385 if (cpu_has_vmx_invept_context())
386 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
387 else
388 ept_sync_global();
389 }
390}
391
392static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
393{
394 if (vm_need_ept()) {
395 if (cpu_has_vmx_invept_individual_addr())
396 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
397 eptp, gpa);
398 else
399 ept_sync_context(eptp);
400 }
401}
402
6aa8b732
AK		 403static unsigned long vmcs_readl(unsigned long field)
404{
405 unsigned long value;
406
4ecac3fd 407 asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX)
6aa8b732
AK		 408 : "=a"(value) : "d"(field) : "cc");
409 return value;
410}
411
412static u16 vmcs_read16(unsigned long field)
413{
414 return vmcs_readl(field);
415}
416
417static u32 vmcs_read32(unsigned long field)
418{
419 return vmcs_readl(field);
420}
421
422static u64 vmcs_read64(unsigned long field)
423{
05b3e0c2 424#ifdef CONFIG_X86_64
6aa8b732
AK		 425 return vmcs_readl(field);
426#else
427 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
428#endif
429}
430
e52de1b8
AK		 431static noinline void vmwrite_error(unsigned long field, unsigned long value)
432{
433 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
434 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
435 dump_stack();
436}
437
6aa8b732
AK		 438static void vmcs_writel(unsigned long field, unsigned long value)
439{
440 u8 error;
441
4ecac3fd 442 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 443 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 444 if (unlikely(error))
445 vmwrite_error(field, value);
6aa8b732
AK		 446}
447
448static void vmcs_write16(unsigned long field, u16 value)
449{
450 vmcs_writel(field, value);
451}
452
453static void vmcs_write32(unsigned long field, u32 value)
454{
455 vmcs_writel(field, value);
456}
457
458static void vmcs_write64(unsigned long field, u64 value)
459{
6aa8b732 460 vmcs_writel(field, value);
7682f2d0 461#ifndef CONFIG_X86_64
6aa8b732
AK		 462 asm volatile ("");
463 vmcs_writel(field+1, value >> 32);
464#endif
465}
466
2ab455cc
AL		 467static void vmcs_clear_bits(unsigned long field, u32 mask)
468{
469 vmcs_writel(field, vmcs_readl(field) & ~mask);
470}
471
472static void vmcs_set_bits(unsigned long field, u32 mask)
473{
474 vmcs_writel(field, vmcs_readl(field) | mask);
475}
476
abd3f2d6
AK		 477static void update_exception_bitmap(struct kvm_vcpu *vcpu)
478{
479 u32 eb;
480
7aa81cc0 481 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR);
abd3f2d6
AK		 482 if (!vcpu->fpu_active)
483 eb |= 1u << NM_VECTOR;
d0bfb940
JK		 484 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
485 if (vcpu->guest_debug &
486 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
487 eb |= 1u << DB_VECTOR;
488 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
489 eb |= 1u << BP_VECTOR;
490 }
ad312c7c 491 if (vcpu->arch.rmode.active)
abd3f2d6 492 eb = ~0;
1439442c
SY		 493 if (vm_need_ept())
494 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
abd3f2d6
AK		 495 vmcs_write32(EXCEPTION_BITMAP, eb);
496}
497
33ed6329
AK		 498static void reload_tss(void)
499{
33ed6329
AK		 500 /*
501 * VT restores TR but not its size. Useless.
502 */
503 struct descriptor_table gdt;
a5f61300 504 struct desc_struct *descs;
33ed6329 505
d6e88aec 506 kvm_get_gdt(&gdt);
33ed6329
AK		 507 descs = (void *)gdt.base;
508 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
509 load_TR_desc();
33ed6329
AK		 510}
511
8b9cf98c 512static void load_transition_efer(struct vcpu_vmx *vmx)
2cc51560 513{
a2fa3e9f 514 int efer_offset = vmx->msr_offset_efer;
51c6cf66
AK		 515 u64 host_efer = vmx->host_msrs[efer_offset].data;
516 u64 guest_efer = vmx->guest_msrs[efer_offset].data;
517 u64 ignore_bits;
518
519 if (efer_offset < 0)
520 return;
521 /*
522 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
523 * outside long mode
524 */
525 ignore_bits = EFER_NX | EFER_SCE;
526#ifdef CONFIG_X86_64
527 ignore_bits |= EFER_LMA | EFER_LME;
528 /* SCE is meaningful only in long mode on Intel */
529 if (guest_efer & EFER_LMA)
530 ignore_bits &= ~(u64)EFER_SCE;
531#endif
532 if ((guest_efer & ~ignore_bits) == (host_efer & ~ignore_bits))
533 return;
2cc51560 534
51c6cf66
AK		 535 vmx->host_state.guest_efer_loaded = 1;
536 guest_efer &= ~ignore_bits;
537 guest_efer |= host_efer & ignore_bits;
538 wrmsrl(MSR_EFER, guest_efer);
8b9cf98c 539 vmx->vcpu.stat.efer_reload++;
2cc51560
ED		 540}
541
51c6cf66
AK		 542static void reload_host_efer(struct vcpu_vmx *vmx)
543{
544 if (vmx->host_state.guest_efer_loaded) {
545 vmx->host_state.guest_efer_loaded = 0;
546 load_msrs(vmx->host_msrs + vmx->msr_offset_efer, 1);
547 }
548}
549
04d2cc77 550static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 551{
04d2cc77
AK		 552 struct vcpu_vmx *vmx = to_vmx(vcpu);
553
a2fa3e9f 554 if (vmx->host_state.loaded)
33ed6329
AK		 555 return;
556
a2fa3e9f 557 vmx->host_state.loaded = 1;
33ed6329
AK		 558 /*
559 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
560 * allow segment selectors with cpl > 0 or ti == 1.
561 */
d6e88aec 562 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 563 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
d6e88aec 564 vmx->host_state.fs_sel = kvm_read_fs();
152d3f2f 565 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 566 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 567 vmx->host_state.fs_reload_needed = 0;
568 } else {
33ed6329 569 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 570 vmx->host_state.fs_reload_needed = 1;
33ed6329 571 }
d6e88aec 572 vmx->host_state.gs_sel = kvm_read_gs();
a2fa3e9f
GH		 573 if (!(vmx->host_state.gs_sel & 7))
574 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 575 else {
576 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 577 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 578 }
579
580#ifdef CONFIG_X86_64
581 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
582 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
583#else
a2fa3e9f
GH		 584 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
585 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 586#endif
707c0874
AK		 587
588#ifdef CONFIG_X86_64
d77c26fc 589 if (is_long_mode(&vmx->vcpu))
a2fa3e9f
GH		 590 save_msrs(vmx->host_msrs +
591 vmx->msr_offset_kernel_gs_base, 1);
d77c26fc 592
707c0874 593#endif
a2fa3e9f 594 load_msrs(vmx->guest_msrs, vmx->save_nmsrs);
51c6cf66 595 load_transition_efer(vmx);
33ed6329
AK		 596}
597
a9b21b62 598static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 599{
15ad7146 600 unsigned long flags;
33ed6329 601
a2fa3e9f 602 if (!vmx->host_state.loaded)
33ed6329
AK		 603 return;
604
e1beb1d3 605 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 606 vmx->host_state.loaded = 0;
152d3f2f 607 if (vmx->host_state.fs_reload_needed)
d6e88aec 608 kvm_load_fs(vmx->host_state.fs_sel);
152d3f2f 609 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 610 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329
AK		 611 /*
612 * If we have to reload gs, we must take care to
613 * preserve our gs base.
614 */
15ad7146 615 local_irq_save(flags);
d6e88aec 616 kvm_load_gs(vmx->host_state.gs_sel);
33ed6329
AK		 617#ifdef CONFIG_X86_64
618 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
619#endif
15ad7146 620 local_irq_restore(flags);
33ed6329 621 }
152d3f2f 622 reload_tss();
a2fa3e9f
GH		 623 save_msrs(vmx->guest_msrs, vmx->save_nmsrs);
624 load_msrs(vmx->host_msrs, vmx->save_nmsrs);
51c6cf66 625 reload_host_efer(vmx);
33ed6329
AK		 626}
627
a9b21b62
AK		 628static void vmx_load_host_state(struct vcpu_vmx *vmx)
629{
630 preempt_disable();
631 __vmx_load_host_state(vmx);
632 preempt_enable();
633}
634
6aa8b732
AK		 635/*
636 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
637 * vcpu mutex is already taken.
638 */
15ad7146 639static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 640{
a2fa3e9f
GH		 641 struct vcpu_vmx *vmx = to_vmx(vcpu);
642 u64 phys_addr = __pa(vmx->vmcs);
019960ae 643 u64 tsc_this, delta, new_offset;
6aa8b732 644
a3d7f85f 645 if (vcpu->cpu != cpu) {
8b9cf98c 646 vcpu_clear(vmx);
2f599714 647 kvm_migrate_timers(vcpu);
2384d2b3 648 vpid_sync_vcpu_all(vmx);
543e4243
AK		 649 local_irq_disable();
650 list_add(&vmx->local_vcpus_link,
651 &per_cpu(vcpus_on_cpu, cpu));
652 local_irq_enable();
a3d7f85f 653 }
6aa8b732 654
a2fa3e9f 655 if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
6aa8b732
AK		 656 u8 error;
657
a2fa3e9f 658 per_cpu(current_vmcs, cpu) = vmx->vmcs;
4ecac3fd 659 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
6aa8b732
AK		 660 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
661 : "cc");
662 if (error)
663 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
a2fa3e9f 664 vmx->vmcs, phys_addr);
6aa8b732
AK		 665 }
666
667 if (vcpu->cpu != cpu) {
668 struct descriptor_table dt;
669 unsigned long sysenter_esp;
670
671 vcpu->cpu = cpu;
672 /*
673 * Linux uses per-cpu TSS and GDT, so set these when switching
674 * processors.
675 */
d6e88aec
AK		 676 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
677 kvm_get_gdt(&dt);
6aa8b732
AK		 678 vmcs_writel(HOST_GDTR_BASE, dt.base); /* 22.2.4 */
679
680 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
681 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
7700270e
AK		 682
683 /*
684 * Make sure the time stamp counter is monotonous.
685 */
686 rdtscll(tsc_this);
019960ae
AK		 687 if (tsc_this < vcpu->arch.host_tsc) {
688 delta = vcpu->arch.host_tsc - tsc_this;
689 new_offset = vmcs_read64(TSC_OFFSET) + delta;
690 vmcs_write64(TSC_OFFSET, new_offset);
691 }
6aa8b732 692 }
6aa8b732
AK		 693}
694
695static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
696{
a9b21b62 697 __vmx_load_host_state(to_vmx(vcpu));
6aa8b732
AK		 698}
699
5fd86fcf
AK		 700static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
701{
702 if (vcpu->fpu_active)
703 return;
704 vcpu->fpu_active = 1;
707d92fa 705 vmcs_clear_bits(GUEST_CR0, X86_CR0_TS);
ad312c7c 706 if (vcpu->arch.cr0 & X86_CR0_TS)
707d92fa 707 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
5fd86fcf
AK		 708 update_exception_bitmap(vcpu);
709}
710
711static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
712{
713 if (!vcpu->fpu_active)
714 return;
715 vcpu->fpu_active = 0;
707d92fa 716 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
5fd86fcf
AK		 717 update_exception_bitmap(vcpu);
718}
719
6aa8b732
AK		 720static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
721{
722 return vmcs_readl(GUEST_RFLAGS);
723}
724
725static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
726{
ad312c7c 727 if (vcpu->arch.rmode.active)
053de044 728 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 729 vmcs_writel(GUEST_RFLAGS, rflags);
730}
731
732static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
733{
734 unsigned long rip;
735 u32 interruptibility;
736
5fdbf976 737 rip = kvm_rip_read(vcpu);
6aa8b732 738 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 739 kvm_rip_write(vcpu, rip);
6aa8b732
AK		 740
741 /*
742 * We emulated an instruction, so temporary interrupt blocking
743 * should be removed, if set.
744 */
745 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
746 if (interruptibility & 3)
747 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
748 interruptibility & ~3);
ad312c7c 749 vcpu->arch.interrupt_window_open = 1;
6aa8b732
AK		 750}
751
298101da
AK		 752static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
753 bool has_error_code, u32 error_code)
754{
77ab6db0 755 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 756 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 757
8ab2d2e2 758 if (has_error_code) {
77ab6db0 759 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 760 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
761 }
77ab6db0
JK		 762
763 if (vcpu->arch.rmode.active) {
764 vmx->rmode.irq.pending = true;
765 vmx->rmode.irq.vector = nr;
766 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
8ab2d2e2 767 if (nr == BP_VECTOR || nr == OF_VECTOR)
77ab6db0 768 vmx->rmode.irq.rip++;
8ab2d2e2
JK		 769 intr_info |= INTR_TYPE_SOFT_INTR;
770 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
77ab6db0
JK		 771 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
772 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
773 return;
774 }
775
8ab2d2e2
JK		 776 if (nr == BP_VECTOR || nr == OF_VECTOR) {
777 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
778 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
779 } else
780 intr_info |= INTR_TYPE_HARD_EXCEPTION;
781
782 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
298101da
AK		 783}
784
785static bool vmx_exception_injected(struct kvm_vcpu *vcpu)
786{
35920a35 787 return false;
298101da
AK		 788}
789
a75beee6
ED		 790/*
791 * Swap MSR entry in host/guest MSR entry array.
792 */
54e11fa1 793#ifdef CONFIG_X86_64
8b9cf98c 794static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 795{
a2fa3e9f
GH		 796 struct kvm_msr_entry tmp;
797
798 tmp = vmx->guest_msrs[to];
799 vmx->guest_msrs[to] = vmx->guest_msrs[from];
800 vmx->guest_msrs[from] = tmp;
801 tmp = vmx->host_msrs[to];
802 vmx->host_msrs[to] = vmx->host_msrs[from];
803 vmx->host_msrs[from] = tmp;
a75beee6 804}
54e11fa1 805#endif
a75beee6 806
e38aea3e
AK		 807/*
808 * Set up the vmcs to automatically save and restore system
809 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
810 * mode, as fiddling with msrs is very expensive.
811 */
8b9cf98c 812static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 813{
2cc51560 814 int save_nmsrs;
e38aea3e 815
33f9c505 816 vmx_load_host_state(vmx);
a75beee6
ED		 817 save_nmsrs = 0;
818#ifdef CONFIG_X86_64
8b9cf98c 819 if (is_long_mode(&vmx->vcpu)) {
2cc51560
ED		 820 int index;
821
8b9cf98c 822 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 823 if (index >= 0)
8b9cf98c
RR		 824 move_msr_up(vmx, index, save_nmsrs++);
825 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 826 if (index >= 0)
8b9cf98c
RR		 827 move_msr_up(vmx, index, save_nmsrs++);
828 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 829 if (index >= 0)
8b9cf98c
RR		 830 move_msr_up(vmx, index, save_nmsrs++);
831 index = __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
a75beee6 832 if (index >= 0)
8b9cf98c 833 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 834 /*
835 * MSR_K6_STAR is only needed on long mode guests, and only
836 * if efer.sce is enabled.
837 */
8b9cf98c 838 index = __find_msr_index(vmx, MSR_K6_STAR);
ad312c7c 839 if ((index >= 0) && (vmx->vcpu.arch.shadow_efer & EFER_SCE))
8b9cf98c 840 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 841 }
842#endif
a2fa3e9f 843 vmx->save_nmsrs = save_nmsrs;
e38aea3e 844
4d56c8a7 845#ifdef CONFIG_X86_64
a2fa3e9f 846 vmx->msr_offset_kernel_gs_base =
8b9cf98c 847 __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
4d56c8a7 848#endif
8b9cf98c 849 vmx->msr_offset_efer = __find_msr_index(vmx, MSR_EFER);
e38aea3e
AK		 850}
851
6aa8b732
AK		 852/*
853 * reads and returns guest's timestamp counter "register"
854 * guest_tsc = host_tsc + tsc_offset -- 21.3
855 */
856static u64 guest_read_tsc(void)
857{
858 u64 host_tsc, tsc_offset;
859
860 rdtscll(host_tsc);
861 tsc_offset = vmcs_read64(TSC_OFFSET);
862 return host_tsc + tsc_offset;
863}
864
865/*
866 * writes 'guest_tsc' into guest's timestamp counter "register"
867 * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
868 */
53f658b3 869static void guest_write_tsc(u64 guest_tsc, u64 host_tsc)
6aa8b732 870{
6aa8b732
AK		 871 vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
872}
873
6aa8b732
AK		 874/*
875 * Reads an msr value (of 'msr_index') into 'pdata'.
876 * Returns 0 on success, non-0 otherwise.
877 * Assumes vcpu_load() was already called.
878 */
879static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
880{
881 u64 data;
a2fa3e9f 882 struct kvm_msr_entry *msr;
6aa8b732
AK		 883
884 if (!pdata) {
885 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
886 return -EINVAL;
887 }
888
889 switch (msr_index) {
05b3e0c2 890#ifdef CONFIG_X86_64
6aa8b732
AK		 891 case MSR_FS_BASE:
892 data = vmcs_readl(GUEST_FS_BASE);
893 break;
894 case MSR_GS_BASE:
895 data = vmcs_readl(GUEST_GS_BASE);
896 break;
897 case MSR_EFER:
3bab1f5d 898 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 899#endif
900 case MSR_IA32_TIME_STAMP_COUNTER:
901 data = guest_read_tsc();
902 break;
903 case MSR_IA32_SYSENTER_CS:
904 data = vmcs_read32(GUEST_SYSENTER_CS);
905 break;
906 case MSR_IA32_SYSENTER_EIP:
f5b42c33 907 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 908 break;
909 case MSR_IA32_SYSENTER_ESP:
f5b42c33 910 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 911 break;
6aa8b732 912 default:
516a1a7e 913 vmx_load_host_state(to_vmx(vcpu));
8b9cf98c 914 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d
AK		 915 if (msr) {
916 data = msr->data;
917 break;
6aa8b732 918 }
3bab1f5d 919 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 920 }
921
922 *pdata = data;
923 return 0;
924}
925
926/*
927 * Writes msr value into into the appropriate "register".
928 * Returns 0 on success, non-0 otherwise.
929 * Assumes vcpu_load() was already called.
930 */
931static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
932{
a2fa3e9f
GH		 933 struct vcpu_vmx *vmx = to_vmx(vcpu);
934 struct kvm_msr_entry *msr;
53f658b3 935 u64 host_tsc;
2cc51560
ED		 936 int ret = 0;
937
6aa8b732 938 switch (msr_index) {
05b3e0c2 939#ifdef CONFIG_X86_64
3bab1f5d 940 case MSR_EFER:
a9b21b62 941 vmx_load_host_state(vmx);
2cc51560 942 ret = kvm_set_msr_common(vcpu, msr_index, data);
2cc51560 943 break;
6aa8b732
AK		 944 case MSR_FS_BASE:
945 vmcs_writel(GUEST_FS_BASE, data);
946 break;
947 case MSR_GS_BASE:
948 vmcs_writel(GUEST_GS_BASE, data);
949 break;
950#endif
951 case MSR_IA32_SYSENTER_CS:
952 vmcs_write32(GUEST_SYSENTER_CS, data);
953 break;
954 case MSR_IA32_SYSENTER_EIP:
f5b42c33 955 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 956 break;
957 case MSR_IA32_SYSENTER_ESP:
f5b42c33 958 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 959 break;
d27d4aca 960 case MSR_IA32_TIME_STAMP_COUNTER:
53f658b3
MT		 961 rdtscll(host_tsc);
962 guest_write_tsc(data, host_tsc);
efa67e0d
CL		 963 break;
964 case MSR_P6_PERFCTR0:
965 case MSR_P6_PERFCTR1:
966 case MSR_P6_EVNTSEL0:
967 case MSR_P6_EVNTSEL1:
968 /*
969 * Just discard all writes to the performance counters; this
970 * should keep both older linux and windows 64-bit guests
971 * happy
972 */
973 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: 0x%x data 0x%llx\n", msr_index, data);
974
6aa8b732 975 break;
468d472f
SY		 976 case MSR_IA32_CR_PAT:
977 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
978 vmcs_write64(GUEST_IA32_PAT, data);
979 vcpu->arch.pat = data;
980 break;
981 }
982 /* Otherwise falls through to kvm_set_msr_common */
6aa8b732 983 default:
a9b21b62 984 vmx_load_host_state(vmx);
8b9cf98c 985 msr = find_msr_entry(vmx, msr_index);
3bab1f5d
AK		 986 if (msr) {
987 msr->data = data;
988 break;
6aa8b732 989 }
2cc51560 990 ret = kvm_set_msr_common(vcpu, msr_index, data);
6aa8b732
AK		 991 }
992
2cc51560 993 return ret;
6aa8b732
AK		 994}
995
5fdbf976 996static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 997{
5fdbf976
MT		 998 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
999 switch (reg) {
1000 case VCPU_REGS_RSP:
1001 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
1002 break;
1003 case VCPU_REGS_RIP:
1004 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
1005 break;
1006 default:
1007 break;
1008 }
6aa8b732
AK		 1009}
1010
d0bfb940 1011static int set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
6aa8b732 1012{
d0bfb940
JK		 1013 int old_debug = vcpu->guest_debug;
1014 unsigned long flags;
6aa8b732 1015
d0bfb940
JK		 1016 vcpu->guest_debug = dbg->control;
1017 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
1018 vcpu->guest_debug = 0;
6aa8b732 1019
ae675ef0
JK		 1020 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1021 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
1022 else
1023 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
1024
d0bfb940
JK		 1025 flags = vmcs_readl(GUEST_RFLAGS);
1026 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
1027 flags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
1028 else if (old_debug & KVM_GUESTDBG_SINGLESTEP)
6aa8b732 1029 flags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
d0bfb940 1030 vmcs_writel(GUEST_RFLAGS, flags);
6aa8b732 1031
abd3f2d6 1032 update_exception_bitmap(vcpu);
6aa8b732
AK		 1033
1034 return 0;
1035}
1036
2a8067f1
ED		 1037static int vmx_get_irq(struct kvm_vcpu *vcpu)
1038{
f7d9238f
AK		 1039 if (!vcpu->arch.interrupt.pending)
1040 return -1;
1041 return vcpu->arch.interrupt.nr;
2a8067f1
ED		 1042}
1043
6aa8b732
AK		 1044static __init int cpu_has_kvm_support(void)
1045{
6210e37b 1046 return cpu_has_vmx();
6aa8b732
AK		 1047}
1048
1049static __init int vmx_disabled_by_bios(void)
1050{
1051 u64 msr;
1052
1053 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
9ea542fa
SY		 1054 return (msr & (FEATURE_CONTROL_LOCKED |
1055 FEATURE_CONTROL_VMXON_ENABLED))
1056 == FEATURE_CONTROL_LOCKED;
62b3ffb8 1057 /* locked but not enabled */
6aa8b732
AK		 1058}
1059
774c47f1 1060static void hardware_enable(void *garbage)
6aa8b732
AK		 1061{
1062 int cpu = raw_smp_processor_id();
1063 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1064 u64 old;
1065
543e4243 1066 INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu));
6aa8b732 1067 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
9ea542fa
SY		 1068 if ((old & (FEATURE_CONTROL_LOCKED |
1069 FEATURE_CONTROL_VMXON_ENABLED))
1070 != (FEATURE_CONTROL_LOCKED |
1071 FEATURE_CONTROL_VMXON_ENABLED))
6aa8b732 1072 /* enable and lock */
62b3ffb8 1073 wrmsrl(MSR_IA32_FEATURE_CONTROL, old |
9ea542fa
SY		 1074 FEATURE_CONTROL_LOCKED |
1075 FEATURE_CONTROL_VMXON_ENABLED);
66aee91a 1076 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
4ecac3fd
AK		 1077 asm volatile (ASM_VMX_VMXON_RAX
1078 : : "a"(&phys_addr), "m"(phys_addr)
6aa8b732
AK		 1079 : "memory", "cc");
1080}
1081
543e4243
AK		 1082static void vmclear_local_vcpus(void)
1083{
1084 int cpu = raw_smp_processor_id();
1085 struct vcpu_vmx *vmx, *n;
1086
1087 list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu),
1088 local_vcpus_link)
1089 __vcpu_clear(vmx);
1090}
1091
710ff4a8
EH		 1092
1093/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
1094 * tricks.
1095 */
1096static void kvm_cpu_vmxoff(void)
6aa8b732 1097{
4ecac3fd 1098 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
e693d71b 1099 write_cr4(read_cr4() & ~X86_CR4_VMXE);
6aa8b732
AK		 1100}
1101
710ff4a8
EH		 1102static void hardware_disable(void *garbage)
1103{
1104 vmclear_local_vcpus();
1105 kvm_cpu_vmxoff();
1106}
1107
1c3d14fe 1108static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 1109 u32 msr, u32 *result)
1c3d14fe
YS		 1110{
1111 u32 vmx_msr_low, vmx_msr_high;
1112 u32 ctl = ctl_min | ctl_opt;
1113
1114 rdmsr(msr, vmx_msr_low, vmx_msr_high);
1115
1116 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1117 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
1118
1119 /* Ensure minimum (required) set of control bits are supported. */
1120 if (ctl_min & ~ctl)
002c7f7c 1121 return -EIO;
1c3d14fe
YS		 1122
1123 *result = ctl;
1124 return 0;
1125}
1126
002c7f7c 1127static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 1128{
1129 u32 vmx_msr_low, vmx_msr_high;
d56f546d 1130 u32 min, opt, min2, opt2;
1c3d14fe
YS		 1131 u32 _pin_based_exec_control = 0;
1132 u32 _cpu_based_exec_control = 0;
f78e0e2e 1133 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 1134 u32 _vmexit_control = 0;
1135 u32 _vmentry_control = 0;
1136
1137 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
f08864b4 1138 opt = PIN_BASED_VIRTUAL_NMIS;
1c3d14fe
YS		 1139 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1140 &_pin_based_exec_control) < 0)
002c7f7c 1141 return -EIO;
1c3d14fe
YS		 1142
1143 min = CPU_BASED_HLT_EXITING |
1144#ifdef CONFIG_X86_64
1145 CPU_BASED_CR8_LOAD_EXITING |
1146 CPU_BASED_CR8_STORE_EXITING |
1147#endif
d56f546d
SY		 1148 CPU_BASED_CR3_LOAD_EXITING |
1149 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 1150 CPU_BASED_USE_IO_BITMAPS |
1151 CPU_BASED_MOV_DR_EXITING |
a7052897
MT		 1152 CPU_BASED_USE_TSC_OFFSETING |
1153 CPU_BASED_INVLPG_EXITING;
f78e0e2e 1154 opt = CPU_BASED_TPR_SHADOW |
25c5f225 1155 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 1156 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 1157 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1158 &_cpu_based_exec_control) < 0)
002c7f7c 1159 return -EIO;
6e5d865c
YS		 1160#ifdef CONFIG_X86_64
1161 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1162 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1163 ~CPU_BASED_CR8_STORE_EXITING;
1164#endif
f78e0e2e 1165 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 1166 min2 = 0;
1167 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2384d2b3 1168 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d
SY		 1169 SECONDARY_EXEC_ENABLE_VPID |
1170 SECONDARY_EXEC_ENABLE_EPT;
1171 if (adjust_vmx_controls(min2, opt2,
1172 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 1173 &_cpu_based_2nd_exec_control) < 0)
1174 return -EIO;
1175 }
1176#ifndef CONFIG_X86_64
1177 if (!(_cpu_based_2nd_exec_control &
1178 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1179 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1180#endif
d56f546d 1181 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 1182 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
1183 enabled */
d56f546d 1184 min &= ~(CPU_BASED_CR3_LOAD_EXITING |
a7052897
MT		 1185 CPU_BASED_CR3_STORE_EXITING |
1186 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 1187 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1188 &_cpu_based_exec_control) < 0)
1189 return -EIO;
1190 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1191 vmx_capability.ept, vmx_capability.vpid);
1192 }
1c3d14fe
YS		 1193
1194 min = 0;
1195#ifdef CONFIG_X86_64
1196 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1197#endif
468d472f 1198 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1c3d14fe
YS		 1199 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1200 &_vmexit_control) < 0)
002c7f7c 1201 return -EIO;
1c3d14fe 1202
468d472f
SY		 1203 min = 0;
1204 opt = VM_ENTRY_LOAD_IA32_PAT;
1c3d14fe
YS		 1205 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1206 &_vmentry_control) < 0)
002c7f7c 1207 return -EIO;
6aa8b732 1208
c68876fd 1209 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 1210
1211 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1212 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 1213 return -EIO;
1c3d14fe
YS		 1214
1215#ifdef CONFIG_X86_64
1216 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1217 if (vmx_msr_high & (1u<<16))
002c7f7c 1218 return -EIO;
1c3d14fe
YS		 1219#endif
1220
1221 /* Require Write-Back (WB) memory type for VMCS accesses. */
1222 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 1223 return -EIO;
1c3d14fe 1224
002c7f7c
YS		 1225 vmcs_conf->size = vmx_msr_high & 0x1fff;
1226 vmcs_conf->order = get_order(vmcs_config.size);
1227 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 1228
002c7f7c
YS		 1229 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1230 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 1231 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 1232 vmcs_conf->vmexit_ctrl = _vmexit_control;
1233 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe
YS		 1234
1235 return 0;
c68876fd 1236}
6aa8b732
AK		 1237
1238static struct vmcs *alloc_vmcs_cpu(int cpu)
1239{
1240 int node = cpu_to_node(cpu);
1241 struct page *pages;
1242 struct vmcs *vmcs;
1243
1c3d14fe 1244 pages = alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 1245 if (!pages)
1246 return NULL;
1247 vmcs = page_address(pages);
1c3d14fe
YS		 1248 memset(vmcs, 0, vmcs_config.size);
1249 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 1250 return vmcs;
1251}
1252
1253static struct vmcs *alloc_vmcs(void)
1254{
d3b2c338 1255 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 1256}
1257
1258static void free_vmcs(struct vmcs *vmcs)
1259{
1c3d14fe 1260 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 1261}
1262
39959588 1263static void free_kvm_area(void)
6aa8b732
AK		 1264{
1265 int cpu;
1266
1267 for_each_online_cpu(cpu)
1268 free_vmcs(per_cpu(vmxarea, cpu));
1269}
1270
6aa8b732
AK		 1271static __init int alloc_kvm_area(void)
1272{
1273 int cpu;
1274
1275 for_each_online_cpu(cpu) {
1276 struct vmcs *vmcs;
1277
1278 vmcs = alloc_vmcs_cpu(cpu);
1279 if (!vmcs) {
1280 free_kvm_area();
1281 return -ENOMEM;
1282 }
1283
1284 per_cpu(vmxarea, cpu) = vmcs;
1285 }
1286 return 0;
1287}
1288
1289static __init int hardware_setup(void)
1290{
002c7f7c
YS		 1291 if (setup_vmcs_config(&vmcs_config) < 0)
1292 return -EIO;
50a37eb4
JR		 1293
1294 if (boot_cpu_has(X86_FEATURE_NX))
1295 kvm_enable_efer_bits(EFER_NX);
1296
6aa8b732
AK		 1297 return alloc_kvm_area();
1298}
1299
1300static __exit void hardware_unsetup(void)
1301{
1302 free_kvm_area();
1303}
1304
6aa8b732
AK		 1305static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1306{
1307 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1308
6af11b9e 1309 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
6aa8b732
AK		 1310 vmcs_write16(sf->selector, save->selector);
1311 vmcs_writel(sf->base, save->base);
1312 vmcs_write32(sf->limit, save->limit);
1313 vmcs_write32(sf->ar_bytes, save->ar);
1314 } else {
1315 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1316 << AR_DPL_SHIFT;
1317 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1318 }
1319}
1320
1321static void enter_pmode(struct kvm_vcpu *vcpu)
1322{
1323 unsigned long flags;
a89a8fb9 1324 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 1325
a89a8fb9 1326 vmx->emulation_required = 1;
ad312c7c 1327 vcpu->arch.rmode.active = 0;
6aa8b732 1328
ad312c7c
ZX		 1329 vmcs_writel(GUEST_TR_BASE, vcpu->arch.rmode.tr.base);
1330 vmcs_write32(GUEST_TR_LIMIT, vcpu->arch.rmode.tr.limit);
1331 vmcs_write32(GUEST_TR_AR_BYTES, vcpu->arch.rmode.tr.ar);
6aa8b732
AK		 1332
1333 flags = vmcs_readl(GUEST_RFLAGS);
053de044 1334 flags &= ~(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
ad312c7c 1335 flags |= (vcpu->arch.rmode.save_iopl << IOPL_SHIFT);
6aa8b732
AK		 1336 vmcs_writel(GUEST_RFLAGS, flags);
1337
66aee91a
RR		 1338 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1339 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 1340
1341 update_exception_bitmap(vcpu);
1342
a89a8fb9
MG		 1343 if (emulate_invalid_guest_state)
1344 return;
1345
ad312c7c
ZX		 1346 fix_pmode_dataseg(VCPU_SREG_ES, &vcpu->arch.rmode.es);
1347 fix_pmode_dataseg(VCPU_SREG_DS, &vcpu->arch.rmode.ds);
1348 fix_pmode_dataseg(VCPU_SREG_GS, &vcpu->arch.rmode.gs);
1349 fix_pmode_dataseg(VCPU_SREG_FS, &vcpu->arch.rmode.fs);
6aa8b732
AK		 1350
1351 vmcs_write16(GUEST_SS_SELECTOR, 0);
1352 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1353
1354 vmcs_write16(GUEST_CS_SELECTOR,
1355 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1356 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1357}
1358
d77c26fc 1359static gva_t rmode_tss_base(struct kvm *kvm)
6aa8b732 1360{
bfc6d222 1361 if (!kvm->arch.tss_addr) {
cbc94022
IE		 1362 gfn_t base_gfn = kvm->memslots[0].base_gfn +
1363 kvm->memslots[0].npages - 3;
1364 return base_gfn << PAGE_SHIFT;
1365 }
bfc6d222 1366 return kvm->arch.tss_addr;
6aa8b732
AK		 1367}
1368
1369static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1370{
1371 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1372
1373 save->selector = vmcs_read16(sf->selector);
1374 save->base = vmcs_readl(sf->base);
1375 save->limit = vmcs_read32(sf->limit);
1376 save->ar = vmcs_read32(sf->ar_bytes);
15b00f32
JK		 1377 vmcs_write16(sf->selector, save->base >> 4);
1378 vmcs_write32(sf->base, save->base & 0xfffff);
6aa8b732
AK		 1379 vmcs_write32(sf->limit, 0xffff);
1380 vmcs_write32(sf->ar_bytes, 0xf3);
1381}
1382
1383static void enter_rmode(struct kvm_vcpu *vcpu)
1384{
1385 unsigned long flags;
a89a8fb9 1386 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 1387
a89a8fb9 1388 vmx->emulation_required = 1;
ad312c7c 1389 vcpu->arch.rmode.active = 1;
6aa8b732 1390
ad312c7c 1391 vcpu->arch.rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
6aa8b732
AK		 1392 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1393
ad312c7c 1394 vcpu->arch.rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
6aa8b732
AK		 1395 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1396
ad312c7c 1397 vcpu->arch.rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
6aa8b732
AK		 1398 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1399
1400 flags = vmcs_readl(GUEST_RFLAGS);
ad312c7c
ZX		 1401 vcpu->arch.rmode.save_iopl
1402 = (flags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
6aa8b732 1403
053de044 1404 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 1405
1406 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 1407 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 1408 update_exception_bitmap(vcpu);
1409
a89a8fb9
MG		 1410 if (emulate_invalid_guest_state)
1411 goto continue_rmode;
1412
6aa8b732
AK		 1413 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1414 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1415 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1416
1417 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
abacf8df 1418 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
8cb5b033
AK		 1419 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1420 vmcs_writel(GUEST_CS_BASE, 0xf0000);
6aa8b732
AK		 1421 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1422
ad312c7c
ZX		 1423 fix_rmode_seg(VCPU_SREG_ES, &vcpu->arch.rmode.es);
1424 fix_rmode_seg(VCPU_SREG_DS, &vcpu->arch.rmode.ds);
1425 fix_rmode_seg(VCPU_SREG_GS, &vcpu->arch.rmode.gs);
1426 fix_rmode_seg(VCPU_SREG_FS, &vcpu->arch.rmode.fs);
75880a01 1427
a89a8fb9 1428continue_rmode:
8668a3c4 1429 kvm_mmu_reset_context(vcpu);
b7ebfb05 1430 init_rmode(vcpu->kvm);
6aa8b732
AK		 1431}
1432
05b3e0c2 1433#ifdef CONFIG_X86_64
6aa8b732
AK		 1434
1435static void enter_lmode(struct kvm_vcpu *vcpu)
1436{
1437 u32 guest_tr_ar;
1438
1439 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1440 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1441 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
b8688d51 1442 __func__);
6aa8b732
AK		 1443 vmcs_write32(GUEST_TR_AR_BYTES,
1444 (guest_tr_ar & ~AR_TYPE_MASK)
1445 | AR_TYPE_BUSY_64_TSS);
1446 }
1447
ad312c7c 1448 vcpu->arch.shadow_efer |= EFER_LMA;
6aa8b732 1449
8b9cf98c 1450 find_msr_entry(to_vmx(vcpu), MSR_EFER)->data |= EFER_LMA | EFER_LME;
6aa8b732
AK		 1451 vmcs_write32(VM_ENTRY_CONTROLS,
1452 vmcs_read32(VM_ENTRY_CONTROLS)
1e4e6e00 1453 | VM_ENTRY_IA32E_MODE);
6aa8b732
AK		 1454}
1455
1456static void exit_lmode(struct kvm_vcpu *vcpu)
1457{
ad312c7c 1458 vcpu->arch.shadow_efer &= ~EFER_LMA;
6aa8b732
AK		 1459
1460 vmcs_write32(VM_ENTRY_CONTROLS,
1461 vmcs_read32(VM_ENTRY_CONTROLS)
1e4e6e00 1462 & ~VM_ENTRY_IA32E_MODE);
6aa8b732
AK		 1463}
1464
1465#endif
1466
2384d2b3
SY		 1467static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1468{
1469 vpid_sync_vcpu_all(to_vmx(vcpu));
4e1096d2
SY		 1470 if (vm_need_ept())
1471 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
2384d2b3
SY		 1472}
1473
25c4c276 1474static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 1475{
ad312c7c
ZX		 1476 vcpu->arch.cr4 &= KVM_GUEST_CR4_MASK;
1477 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & ~KVM_GUEST_CR4_MASK;
399badf3
AK		 1478}
1479
1439442c
SY		 1480static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
1481{
1482 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1483 if (!load_pdptrs(vcpu, vcpu->arch.cr3)) {
1484 printk(KERN_ERR "EPT: Fail to load pdptrs!\n");
1485 return;
1486 }
1487 vmcs_write64(GUEST_PDPTR0, vcpu->arch.pdptrs[0]);
1488 vmcs_write64(GUEST_PDPTR1, vcpu->arch.pdptrs[1]);
1489 vmcs_write64(GUEST_PDPTR2, vcpu->arch.pdptrs[2]);
1490 vmcs_write64(GUEST_PDPTR3, vcpu->arch.pdptrs[3]);
1491 }
1492}
1493
1494static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1495
1496static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
1497 unsigned long cr0,
1498 struct kvm_vcpu *vcpu)
1499{
1500 if (!(cr0 & X86_CR0_PG)) {
1501 /* From paging/starting to nonpaging */
1502 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 1503 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 1504 (CPU_BASED_CR3_LOAD_EXITING |
1505 CPU_BASED_CR3_STORE_EXITING));
1506 vcpu->arch.cr0 = cr0;
1507 vmx_set_cr4(vcpu, vcpu->arch.cr4);
1508 *hw_cr0 |= X86_CR0_PE | X86_CR0_PG;
1509 *hw_cr0 &= ~X86_CR0_WP;
1510 } else if (!is_paging(vcpu)) {
1511 /* From nonpaging to paging */
1512 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 1513 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 1514 ~(CPU_BASED_CR3_LOAD_EXITING |
1515 CPU_BASED_CR3_STORE_EXITING));
1516 vcpu->arch.cr0 = cr0;
1517 vmx_set_cr4(vcpu, vcpu->arch.cr4);
1518 if (!(vcpu->arch.cr0 & X86_CR0_WP))
1519 *hw_cr0 &= ~X86_CR0_WP;
1520 }
1521}
1522
1523static void ept_update_paging_mode_cr4(unsigned long *hw_cr4,
1524 struct kvm_vcpu *vcpu)
1525{
1526 if (!is_paging(vcpu)) {
1527 *hw_cr4 &= ~X86_CR4_PAE;
1528 *hw_cr4 |= X86_CR4_PSE;
1529 } else if (!(vcpu->arch.cr4 & X86_CR4_PAE))
1530 *hw_cr4 &= ~X86_CR4_PAE;
1531}
1532
6aa8b732
AK		 1533static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1534{
1439442c
SY		 1535 unsigned long hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) |
1536 KVM_VM_CR0_ALWAYS_ON;
1537
5fd86fcf
AK		 1538 vmx_fpu_deactivate(vcpu);
1539
ad312c7c 1540 if (vcpu->arch.rmode.active && (cr0 & X86_CR0_PE))
6aa8b732
AK		 1541 enter_pmode(vcpu);
1542
ad312c7c 1543 if (!vcpu->arch.rmode.active && !(cr0 & X86_CR0_PE))
6aa8b732
AK		 1544 enter_rmode(vcpu);
1545
05b3e0c2 1546#ifdef CONFIG_X86_64
ad312c7c 1547 if (vcpu->arch.shadow_efer & EFER_LME) {
707d92fa 1548 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 1549 enter_lmode(vcpu);
707d92fa 1550 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 1551 exit_lmode(vcpu);
1552 }
1553#endif
1554
1439442c
SY		 1555 if (vm_need_ept())
1556 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
1557
6aa8b732 1558 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 1559 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 1560 vcpu->arch.cr0 = cr0;
5fd86fcf 1561
707d92fa 1562 if (!(cr0 & X86_CR0_TS) || !(cr0 & X86_CR0_PE))
5fd86fcf 1563 vmx_fpu_activate(vcpu);
6aa8b732
AK		 1564}
1565
1439442c
SY		 1566static u64 construct_eptp(unsigned long root_hpa)
1567{
1568 u64 eptp;
1569
1570 /* TODO write the value reading from MSR */
1571 eptp = VMX_EPT_DEFAULT_MT |
1572 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
1573 eptp |= (root_hpa & PAGE_MASK);
1574
1575 return eptp;
1576}
1577
6aa8b732
AK		 1578static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1579{
1439442c
SY		 1580 unsigned long guest_cr3;
1581 u64 eptp;
1582
1583 guest_cr3 = cr3;
1584 if (vm_need_ept()) {
1585 eptp = construct_eptp(cr3);
1586 vmcs_write64(EPT_POINTER, eptp);
1587 ept_sync_context(eptp);
1588 ept_load_pdptrs(vcpu);
1589 guest_cr3 = is_paging(vcpu) ? vcpu->arch.cr3 :
1590 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
1591 }
1592
2384d2b3 1593 vmx_flush_tlb(vcpu);
1439442c 1594 vmcs_writel(GUEST_CR3, guest_cr3);
ad312c7c 1595 if (vcpu->arch.cr0 & X86_CR0_PE)
5fd86fcf 1596 vmx_fpu_deactivate(vcpu);
6aa8b732
AK		 1597}
1598
1599static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1600{
1439442c
SY		 1601 unsigned long hw_cr4 = cr4 | (vcpu->arch.rmode.active ?
1602 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1603
ad312c7c 1604 vcpu->arch.cr4 = cr4;
1439442c
SY		 1605 if (vm_need_ept())
1606 ept_update_paging_mode_cr4(&hw_cr4, vcpu);
1607
1608 vmcs_writel(CR4_READ_SHADOW, cr4);
1609 vmcs_writel(GUEST_CR4, hw_cr4);
6aa8b732
AK		 1610}
1611
6aa8b732
AK		 1612static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1613{
8b9cf98c
RR		 1614 struct vcpu_vmx *vmx = to_vmx(vcpu);
1615 struct kvm_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
6aa8b732 1616
ad312c7c 1617 vcpu->arch.shadow_efer = efer;
9f62e19a
JR		 1618 if (!msr)
1619 return;
6aa8b732
AK		 1620 if (efer & EFER_LMA) {
1621 vmcs_write32(VM_ENTRY_CONTROLS,
1622 vmcs_read32(VM_ENTRY_CONTROLS) |
1e4e6e00 1623 VM_ENTRY_IA32E_MODE);
6aa8b732
AK		 1624 msr->data = efer;
1625
1626 } else {
1627 vmcs_write32(VM_ENTRY_CONTROLS,
1628 vmcs_read32(VM_ENTRY_CONTROLS) &
1e4e6e00 1629 ~VM_ENTRY_IA32E_MODE);
6aa8b732
AK		 1630
1631 msr->data = efer & ~EFER_LME;
1632 }
8b9cf98c 1633 setup_msrs(vmx);
6aa8b732
AK		 1634}
1635
6aa8b732
AK		 1636static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1637{
1638 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1639
1640 return vmcs_readl(sf->base);
1641}
1642
1643static void vmx_get_segment(struct kvm_vcpu *vcpu,
1644 struct kvm_segment *var, int seg)
1645{
1646 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1647 u32 ar;
1648
1649 var->base = vmcs_readl(sf->base);
1650 var->limit = vmcs_read32(sf->limit);
1651 var->selector = vmcs_read16(sf->selector);
1652 ar = vmcs_read32(sf->ar_bytes);
9fd4a3b7 1653 if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
6aa8b732
AK		 1654 ar = 0;
1655 var->type = ar & 15;
1656 var->s = (ar >> 4) & 1;
1657 var->dpl = (ar >> 5) & 3;
1658 var->present = (ar >> 7) & 1;
1659 var->avl = (ar >> 12) & 1;
1660 var->l = (ar >> 13) & 1;
1661 var->db = (ar >> 14) & 1;
1662 var->g = (ar >> 15) & 1;
1663 var->unusable = (ar >> 16) & 1;
1664}
1665
2e4d2653
IE		 1666static int vmx_get_cpl(struct kvm_vcpu *vcpu)
1667{
1668 struct kvm_segment kvm_seg;
1669
1670 if (!(vcpu->arch.cr0 & X86_CR0_PE)) /* if real mode */
1671 return 0;
1672
1673 if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */
1674 return 3;
1675
1676 vmx_get_segment(vcpu, &kvm_seg, VCPU_SREG_CS);
1677 return kvm_seg.selector & 3;
1678}
1679
653e3108 1680static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 1681{
6aa8b732
AK		 1682 u32 ar;
1683
653e3108 1684 if (var->unusable)
6aa8b732
AK		 1685 ar = 1 << 16;
1686 else {
1687 ar = var->type & 15;
1688 ar |= (var->s & 1) << 4;
1689 ar |= (var->dpl & 3) << 5;
1690 ar |= (var->present & 1) << 7;
1691 ar |= (var->avl & 1) << 12;
1692 ar |= (var->l & 1) << 13;
1693 ar |= (var->db & 1) << 14;
1694 ar |= (var->g & 1) << 15;
1695 }
f7fbf1fd
UL		 1696 if (ar == 0) /* a 0 value means unusable */
1697 ar = AR_UNUSABLE_MASK;
653e3108
AK		 1698
1699 return ar;
1700}
1701
1702static void vmx_set_segment(struct kvm_vcpu *vcpu,
1703 struct kvm_segment *var, int seg)
1704{
1705 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1706 u32 ar;
1707
ad312c7c
ZX		 1708 if (vcpu->arch.rmode.active && seg == VCPU_SREG_TR) {
1709 vcpu->arch.rmode.tr.selector = var->selector;
1710 vcpu->arch.rmode.tr.base = var->base;
1711 vcpu->arch.rmode.tr.limit = var->limit;
1712 vcpu->arch.rmode.tr.ar = vmx_segment_access_rights(var);
653e3108
AK		 1713 return;
1714 }
1715 vmcs_writel(sf->base, var->base);
1716 vmcs_write32(sf->limit, var->limit);
1717 vmcs_write16(sf->selector, var->selector);
ad312c7c 1718 if (vcpu->arch.rmode.active && var->s) {
653e3108
AK		 1719 /*
1720 * Hack real-mode segments into vm86 compatibility.
1721 */
1722 if (var->base == 0xffff0000 && var->selector == 0xf000)
1723 vmcs_writel(sf->base, 0xf0000);
1724 ar = 0xf3;
1725 } else
1726 ar = vmx_segment_access_rights(var);
6aa8b732
AK		 1727 vmcs_write32(sf->ar_bytes, ar);
1728}
1729
6aa8b732
AK		 1730static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
1731{
1732 u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
1733
1734 *db = (ar >> 14) & 1;
1735 *l = (ar >> 13) & 1;
1736}
1737
1738static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1739{
1740 dt->limit = vmcs_read32(GUEST_IDTR_LIMIT);
1741 dt->base = vmcs_readl(GUEST_IDTR_BASE);
1742}
1743
1744static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1745{
1746 vmcs_write32(GUEST_IDTR_LIMIT, dt->limit);
1747 vmcs_writel(GUEST_IDTR_BASE, dt->base);
1748}
1749
1750static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1751{
1752 dt->limit = vmcs_read32(GUEST_GDTR_LIMIT);
1753 dt->base = vmcs_readl(GUEST_GDTR_BASE);
1754}
1755
1756static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1757{
1758 vmcs_write32(GUEST_GDTR_LIMIT, dt->limit);
1759 vmcs_writel(GUEST_GDTR_BASE, dt->base);
1760}
1761
648dfaa7
MG		 1762static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
1763{
1764 struct kvm_segment var;
1765 u32 ar;
1766
1767 vmx_get_segment(vcpu, &var, seg);
1768 ar = vmx_segment_access_rights(&var);
1769
1770 if (var.base != (var.selector << 4))
1771 return false;
1772 if (var.limit != 0xffff)
1773 return false;
1774 if (ar != 0xf3)
1775 return false;
1776
1777 return true;
1778}
1779
1780static bool code_segment_valid(struct kvm_vcpu *vcpu)
1781{
1782 struct kvm_segment cs;
1783 unsigned int cs_rpl;
1784
1785 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
1786 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
1787
1872a3f4
AK		 1788 if (cs.unusable)
1789 return false;
648dfaa7
MG		 1790 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
1791 return false;
1792 if (!cs.s)
1793 return false;
1872a3f4 1794 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 1795 if (cs.dpl > cs_rpl)
1796 return false;
1872a3f4 1797 } else {
648dfaa7
MG		 1798 if (cs.dpl != cs_rpl)
1799 return false;
1800 }
1801 if (!cs.present)
1802 return false;
1803
1804 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
1805 return true;
1806}
1807
1808static bool stack_segment_valid(struct kvm_vcpu *vcpu)
1809{
1810 struct kvm_segment ss;
1811 unsigned int ss_rpl;
1812
1813 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
1814 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
1815
1872a3f4
AK		 1816 if (ss.unusable)
1817 return true;
1818 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 1819 return false;
1820 if (!ss.s)
1821 return false;
1822 if (ss.dpl != ss_rpl) /* DPL != RPL */
1823 return false;
1824 if (!ss.present)
1825 return false;
1826
1827 return true;
1828}
1829
1830static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
1831{
1832 struct kvm_segment var;
1833 unsigned int rpl;
1834
1835 vmx_get_segment(vcpu, &var, seg);
1836 rpl = var.selector & SELECTOR_RPL_MASK;
1837
1872a3f4
AK		 1838 if (var.unusable)
1839 return true;
648dfaa7
MG		 1840 if (!var.s)
1841 return false;
1842 if (!var.present)
1843 return false;
1844 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
1845 if (var.dpl < rpl) /* DPL < RPL */
1846 return false;
1847 }
1848
1849 /* TODO: Add other members to kvm_segment_field to allow checking for other access
1850 * rights flags
1851 */
1852 return true;
1853}
1854
1855static bool tr_valid(struct kvm_vcpu *vcpu)
1856{
1857 struct kvm_segment tr;
1858
1859 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
1860
1872a3f4
AK		 1861 if (tr.unusable)
1862 return false;
648dfaa7
MG		 1863 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
1864 return false;
1872a3f4 1865 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 1866 return false;
1867 if (!tr.present)
1868 return false;
1869
1870 return true;
1871}
1872
1873static bool ldtr_valid(struct kvm_vcpu *vcpu)
1874{
1875 struct kvm_segment ldtr;
1876
1877 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
1878
1872a3f4
AK		 1879 if (ldtr.unusable)
1880 return true;
648dfaa7
MG		 1881 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
1882 return false;
1883 if (ldtr.type != 2)
1884 return false;
1885 if (!ldtr.present)
1886 return false;
1887
1888 return true;
1889}
1890
1891static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
1892{
1893 struct kvm_segment cs, ss;
1894
1895 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
1896 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
1897
1898 return ((cs.selector & SELECTOR_RPL_MASK) ==
1899 (ss.selector & SELECTOR_RPL_MASK));
1900}
1901
1902/*
1903 * Check if guest state is valid. Returns true if valid, false if
1904 * not.
1905 * We assume that registers are always usable
1906 */
1907static bool guest_state_valid(struct kvm_vcpu *vcpu)
1908{
1909 /* real mode guest state checks */
1910 if (!(vcpu->arch.cr0 & X86_CR0_PE)) {
1911 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
1912 return false;
1913 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
1914 return false;
1915 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
1916 return false;
1917 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
1918 return false;
1919 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
1920 return false;
1921 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
1922 return false;
1923 } else {
1924 /* protected mode guest state checks */
1925 if (!cs_ss_rpl_check(vcpu))
1926 return false;
1927 if (!code_segment_valid(vcpu))
1928 return false;
1929 if (!stack_segment_valid(vcpu))
1930 return false;
1931 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
1932 return false;
1933 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
1934 return false;
1935 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
1936 return false;
1937 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
1938 return false;
1939 if (!tr_valid(vcpu))
1940 return false;
1941 if (!ldtr_valid(vcpu))
1942 return false;
1943 }
1944 /* TODO:
1945 * - Add checks on RIP
1946 * - Add checks on RFLAGS
1947 */
1948
1949 return true;
1950}
1951
d77c26fc 1952static int init_rmode_tss(struct kvm *kvm)
6aa8b732 1953{
6aa8b732 1954 gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
195aefde 1955 u16 data = 0;
10589a46 1956 int ret = 0;
195aefde 1957 int r;
6aa8b732 1958
195aefde
IE		 1959 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
1960 if (r < 0)
10589a46 1961 goto out;
195aefde 1962 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 1963 r = kvm_write_guest_page(kvm, fn++, &data,
1964 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 1965 if (r < 0)
10589a46 1966 goto out;
195aefde
IE		 1967 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
1968 if (r < 0)
10589a46 1969 goto out;
195aefde
IE		 1970 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
1971 if (r < 0)
10589a46 1972 goto out;
195aefde 1973 data = ~0;
10589a46
MT		 1974 r = kvm_write_guest_page(kvm, fn, &data,
1975 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
1976 sizeof(u8));
195aefde 1977 if (r < 0)
10589a46
MT		 1978 goto out;
1979
1980 ret = 1;
1981out:
10589a46 1982 return ret;
6aa8b732
AK		 1983}
1984
b7ebfb05
SY		 1985static int init_rmode_identity_map(struct kvm *kvm)
1986{
1987 int i, r, ret;
1988 pfn_t identity_map_pfn;
1989 u32 tmp;
1990
1991 if (!vm_need_ept())
1992 return 1;
1993 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
1994 printk(KERN_ERR "EPT: identity-mapping pagetable "
1995 "haven't been allocated!\n");
1996 return 0;
1997 }
1998 if (likely(kvm->arch.ept_identity_pagetable_done))
1999 return 1;
2000 ret = 0;
2001 identity_map_pfn = VMX_EPT_IDENTITY_PAGETABLE_ADDR >> PAGE_SHIFT;
2002 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
2003 if (r < 0)
2004 goto out;
2005 /* Set up identity-mapping pagetable for EPT in real mode */
2006 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
2007 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
2008 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
2009 r = kvm_write_guest_page(kvm, identity_map_pfn,
2010 &tmp, i * sizeof(tmp), sizeof(tmp));
2011 if (r < 0)
2012 goto out;
2013 }
2014 kvm->arch.ept_identity_pagetable_done = true;
2015 ret = 1;
2016out:
2017 return ret;
2018}
2019
6aa8b732
AK		 2020static void seg_setup(int seg)
2021{
2022 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2023
2024 vmcs_write16(sf->selector, 0);
2025 vmcs_writel(sf->base, 0);
2026 vmcs_write32(sf->limit, 0xffff);
a16b20da 2027 vmcs_write32(sf->ar_bytes, 0xf3);
6aa8b732
AK		 2028}
2029
f78e0e2e
SY		 2030static int alloc_apic_access_page(struct kvm *kvm)
2031{
2032 struct kvm_userspace_memory_region kvm_userspace_mem;
2033 int r = 0;
2034
72dc67a6 2035 down_write(&kvm->slots_lock);
bfc6d222 2036 if (kvm->arch.apic_access_page)
f78e0e2e
SY		 2037 goto out;
2038 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
2039 kvm_userspace_mem.flags = 0;
2040 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
2041 kvm_userspace_mem.memory_size = PAGE_SIZE;
2042 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2043 if (r)
2044 goto out;
72dc67a6 2045
bfc6d222 2046 kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
f78e0e2e 2047out:
72dc67a6 2048 up_write(&kvm->slots_lock);
f78e0e2e
SY		 2049 return r;
2050}
2051
b7ebfb05
SY		 2052static int alloc_identity_pagetable(struct kvm *kvm)
2053{
2054 struct kvm_userspace_memory_region kvm_userspace_mem;
2055 int r = 0;
2056
2057 down_write(&kvm->slots_lock);
2058 if (kvm->arch.ept_identity_pagetable)
2059 goto out;
2060 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
2061 kvm_userspace_mem.flags = 0;
2062 kvm_userspace_mem.guest_phys_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR;
2063 kvm_userspace_mem.memory_size = PAGE_SIZE;
2064 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2065 if (r)
2066 goto out;
2067
b7ebfb05
SY		 2068 kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
2069 VMX_EPT_IDENTITY_PAGETABLE_ADDR >> PAGE_SHIFT);
b7ebfb05
SY		 2070out:
2071 up_write(&kvm->slots_lock);
2072 return r;
2073}
2074
2384d2b3
SY		 2075static void allocate_vpid(struct vcpu_vmx *vmx)
2076{
2077 int vpid;
2078
2079 vmx->vpid = 0;
2080 if (!enable_vpid || !cpu_has_vmx_vpid())
2081 return;
2082 spin_lock(&vmx_vpid_lock);
2083 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
2084 if (vpid < VMX_NR_VPIDS) {
2085 vmx->vpid = vpid;
2086 __set_bit(vpid, vmx_vpid_bitmap);
2087 }
2088 spin_unlock(&vmx_vpid_lock);
2089}
2090
8b2cf73c 2091static void vmx_disable_intercept_for_msr(struct page *msr_bitmap, u32 msr)
25c5f225
SY		 2092{
2093 void *va;
2094
2095 if (!cpu_has_vmx_msr_bitmap())
2096 return;
2097
2098 /*
2099 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2100 * have the write-low and read-high bitmap offsets the wrong way round.
2101 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2102 */
2103 va = kmap(msr_bitmap);
2104 if (msr <= 0x1fff) {
2105 __clear_bit(msr, va + 0x000); /* read-low */
2106 __clear_bit(msr, va + 0x800); /* write-low */
2107 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2108 msr &= 0x1fff;
2109 __clear_bit(msr, va + 0x400); /* read-high */
2110 __clear_bit(msr, va + 0xc00); /* write-high */
2111 }
2112 kunmap(msr_bitmap);
2113}
2114
6aa8b732
AK		 2115/*
2116 * Sets up the vmcs for emulated real mode.
2117 */
8b9cf98c 2118static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 2119{
468d472f 2120 u32 host_sysenter_cs, msr_low, msr_high;
6aa8b732 2121 u32 junk;
53f658b3 2122 u64 host_pat, tsc_this, tsc_base;
6aa8b732
AK		 2123 unsigned long a;
2124 struct descriptor_table dt;
2125 int i;
cd2276a7 2126 unsigned long kvm_vmx_return;
6e5d865c 2127 u32 exec_control;
6aa8b732 2128
6aa8b732 2129 /* I/O */
fdef3ad1
HQ		 2130 vmcs_write64(IO_BITMAP_A, page_to_phys(vmx_io_bitmap_a));
2131 vmcs_write64(IO_BITMAP_B, page_to_phys(vmx_io_bitmap_b));
6aa8b732 2132
25c5f225
SY		 2133 if (cpu_has_vmx_msr_bitmap())
2134 vmcs_write64(MSR_BITMAP, page_to_phys(vmx_msr_bitmap));
2135
6aa8b732
AK		 2136 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
2137
6aa8b732 2138 /* Control */
1c3d14fe
YS		 2139 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
2140 vmcs_config.pin_based_exec_ctrl);
6e5d865c
YS		 2141
2142 exec_control = vmcs_config.cpu_based_exec_ctrl;
2143 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
2144 exec_control &= ~CPU_BASED_TPR_SHADOW;
2145#ifdef CONFIG_X86_64
2146 exec_control |= CPU_BASED_CR8_STORE_EXITING |
2147 CPU_BASED_CR8_LOAD_EXITING;
2148#endif
2149 }
d56f546d
SY		 2150 if (!vm_need_ept())
2151 exec_control |= CPU_BASED_CR3_STORE_EXITING |
83dbc83a
MT		 2152 CPU_BASED_CR3_LOAD_EXITING |
2153 CPU_BASED_INVLPG_EXITING;
6e5d865c 2154 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
6aa8b732 2155
83ff3b9d
SY		 2156 if (cpu_has_secondary_exec_ctrls()) {
2157 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
2158 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2159 exec_control &=
2160 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2384d2b3
SY		 2161 if (vmx->vpid == 0)
2162 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
d56f546d
SY		 2163 if (!vm_need_ept())
2164 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
83ff3b9d
SY		 2165 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
2166 }
f78e0e2e 2167
c7addb90
AK		 2168 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
2169 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
6aa8b732
AK		 2170 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
2171
2172 vmcs_writel(HOST_CR0, read_cr0()); /* 22.2.3 */
2173 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
2174 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
2175
2176 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
2177 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2178 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
d6e88aec
AK		 2179 vmcs_write16(HOST_FS_SELECTOR, kvm_read_fs()); /* 22.2.4 */
2180 vmcs_write16(HOST_GS_SELECTOR, kvm_read_gs()); /* 22.2.4 */
6aa8b732 2181 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
05b3e0c2 2182#ifdef CONFIG_X86_64
6aa8b732
AK		 2183 rdmsrl(MSR_FS_BASE, a);
2184 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
2185 rdmsrl(MSR_GS_BASE, a);
2186 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
2187#else
2188 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
2189 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
2190#endif
2191
2192 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
2193
d6e88aec 2194 kvm_get_idt(&dt);
6aa8b732
AK		 2195 vmcs_writel(HOST_IDTR_BASE, dt.base); /* 22.2.4 */
2196
d77c26fc 2197 asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
cd2276a7 2198 vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2cc51560
ED		 2199 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
2200 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
2201 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
6aa8b732
AK		 2202
2203 rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
2204 vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
2205 rdmsrl(MSR_IA32_SYSENTER_ESP, a);
2206 vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */
2207 rdmsrl(MSR_IA32_SYSENTER_EIP, a);
2208 vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */
2209
468d472f
SY		 2210 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
2211 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2212 host_pat = msr_low | ((u64) msr_high << 32);
2213 vmcs_write64(HOST_IA32_PAT, host_pat);
2214 }
2215 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2216 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2217 host_pat = msr_low | ((u64) msr_high << 32);
2218 /* Write the default value follow host pat */
2219 vmcs_write64(GUEST_IA32_PAT, host_pat);
2220 /* Keep arch.pat sync with GUEST_IA32_PAT */
2221 vmx->vcpu.arch.pat = host_pat;
2222 }
2223
6aa8b732
AK		 2224 for (i = 0; i < NR_VMX_MSR; ++i) {
2225 u32 index = vmx_msr_index[i];
2226 u32 data_low, data_high;
2227 u64 data;
a2fa3e9f 2228 int j = vmx->nmsrs;
6aa8b732
AK		 2229
2230 if (rdmsr_safe(index, &data_low, &data_high) < 0)
2231 continue;
432bd6cb
AK		 2232 if (wrmsr_safe(index, data_low, data_high) < 0)
2233 continue;
6aa8b732 2234 data = data_low | ((u64)data_high << 32);
a2fa3e9f
GH		 2235 vmx->host_msrs[j].index = index;
2236 vmx->host_msrs[j].reserved = 0;
2237 vmx->host_msrs[j].data = data;
2238 vmx->guest_msrs[j] = vmx->host_msrs[j];
2239 ++vmx->nmsrs;
6aa8b732 2240 }
6aa8b732 2241
1c3d14fe 2242 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 2243
2244 /* 22.2.1, 20.8.1 */
1c3d14fe
YS		 2245 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
2246
e00c8cf2
AK		 2247 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
2248 vmcs_writel(CR4_GUEST_HOST_MASK, KVM_GUEST_CR4_MASK);
2249
53f658b3
MT		 2250 tsc_base = vmx->vcpu.kvm->arch.vm_init_tsc;
2251 rdtscll(tsc_this);
2252 if (tsc_this < vmx->vcpu.kvm->arch.vm_init_tsc)
2253 tsc_base = tsc_this;
2254
2255 guest_write_tsc(0, tsc_base);
f78e0e2e 2256
e00c8cf2
AK		 2257 return 0;
2258}
2259
b7ebfb05
SY		 2260static int init_rmode(struct kvm *kvm)
2261{
2262 if (!init_rmode_tss(kvm))
2263 return 0;
2264 if (!init_rmode_identity_map(kvm))
2265 return 0;
2266 return 1;
2267}
2268
e00c8cf2
AK		 2269static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
2270{
2271 struct vcpu_vmx *vmx = to_vmx(vcpu);
2272 u64 msr;
2273 int ret;
2274
5fdbf976 2275 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
3200f405 2276 down_read(&vcpu->kvm->slots_lock);
b7ebfb05 2277 if (!init_rmode(vmx->vcpu.kvm)) {
e00c8cf2
AK		 2278 ret = -ENOMEM;
2279 goto out;
2280 }
2281
ad312c7c 2282 vmx->vcpu.arch.rmode.active = 0;
e00c8cf2 2283
3b86cd99
JK		 2284 vmx->soft_vnmi_blocked = 0;
2285
ad312c7c 2286 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 2287 kvm_set_cr8(&vmx->vcpu, 0);
e00c8cf2
AK		 2288 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
2289 if (vmx->vcpu.vcpu_id == 0)
2290 msr |= MSR_IA32_APICBASE_BSP;
2291 kvm_set_apic_base(&vmx->vcpu, msr);
2292
2293 fx_init(&vmx->vcpu);
2294
5706be0d 2295 seg_setup(VCPU_SREG_CS);
e00c8cf2
AK		 2296 /*
2297 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2298 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
2299 */
2300 if (vmx->vcpu.vcpu_id == 0) {
2301 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2302 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2303 } else {
ad312c7c
ZX		 2304 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2305 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
e00c8cf2 2306 }
e00c8cf2
AK		 2307
2308 seg_setup(VCPU_SREG_DS);
2309 seg_setup(VCPU_SREG_ES);
2310 seg_setup(VCPU_SREG_FS);
2311 seg_setup(VCPU_SREG_GS);
2312 seg_setup(VCPU_SREG_SS);
2313
2314 vmcs_write16(GUEST_TR_SELECTOR, 0);
2315 vmcs_writel(GUEST_TR_BASE, 0);
2316 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
2317 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2318
2319 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
2320 vmcs_writel(GUEST_LDTR_BASE, 0);
2321 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
2322 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
2323
2324 vmcs_write32(GUEST_SYSENTER_CS, 0);
2325 vmcs_writel(GUEST_SYSENTER_ESP, 0);
2326 vmcs_writel(GUEST_SYSENTER_EIP, 0);
2327
2328 vmcs_writel(GUEST_RFLAGS, 0x02);
2329 if (vmx->vcpu.vcpu_id == 0)
5fdbf976 2330 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 2331 else
5fdbf976
MT		 2332 kvm_rip_write(vcpu, 0);
2333 kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
e00c8cf2 2334
e00c8cf2
AK		 2335 vmcs_writel(GUEST_DR7, 0x400);
2336
2337 vmcs_writel(GUEST_GDTR_BASE, 0);
2338 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
2339
2340 vmcs_writel(GUEST_IDTR_BASE, 0);
2341 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
2342
2343 vmcs_write32(GUEST_ACTIVITY_STATE, 0);
2344 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
2345 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
2346
e00c8cf2
AK		 2347 /* Special registers */
2348 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
2349
2350 setup_msrs(vmx);
2351
6aa8b732
AK		 2352 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
2353
f78e0e2e
SY		 2354 if (cpu_has_vmx_tpr_shadow()) {
2355 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
2356 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
2357 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
ad312c7c 2358 page_to_phys(vmx->vcpu.arch.apic->regs_page));
f78e0e2e
SY		 2359 vmcs_write32(TPR_THRESHOLD, 0);
2360 }
2361
2362 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2363 vmcs_write64(APIC_ACCESS_ADDR,
bfc6d222 2364 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
6aa8b732 2365
2384d2b3
SY		 2366 if (vmx->vpid != 0)
2367 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2368
ad312c7c
ZX		 2369 vmx->vcpu.arch.cr0 = 0x60000010;
2370 vmx_set_cr0(&vmx->vcpu, vmx->vcpu.arch.cr0); /* enter rmode */
8b9cf98c 2371 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 2372 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 2373 vmx_fpu_activate(&vmx->vcpu);
2374 update_exception_bitmap(&vmx->vcpu);
6aa8b732 2375
2384d2b3
SY		 2376 vpid_sync_vcpu_all(vmx);
2377
3200f405 2378 ret = 0;
6aa8b732 2379
a89a8fb9
MG		 2380 /* HACK: Don't enable emulation on guest boot/reset */
2381 vmx->emulation_required = 0;
2382
6aa8b732 2383out:
3200f405 2384 up_read(&vcpu->kvm->slots_lock);
6aa8b732
AK		 2385 return ret;
2386}
2387
3b86cd99
JK		 2388static void enable_irq_window(struct kvm_vcpu *vcpu)
2389{
2390 u32 cpu_based_vm_exec_control;
2391
2392 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2393 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2394 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2395}
2396
2397static void enable_nmi_window(struct kvm_vcpu *vcpu)
2398{
2399 u32 cpu_based_vm_exec_control;
2400
2401 if (!cpu_has_virtual_nmis()) {
2402 enable_irq_window(vcpu);
2403 return;
2404 }
2405
2406 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2407 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
2408 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2409}
2410
85f455f7
ED		 2411static void vmx_inject_irq(struct kvm_vcpu *vcpu, int irq)
2412{
9c8cba37
AK		 2413 struct vcpu_vmx *vmx = to_vmx(vcpu);
2414
2714d1d3
FEL		 2415 KVMTRACE_1D(INJ_VIRQ, vcpu, (u32)irq, handler);
2416
fa89a817 2417 ++vcpu->stat.irq_injections;
ad312c7c 2418 if (vcpu->arch.rmode.active) {
9c8cba37
AK		 2419 vmx->rmode.irq.pending = true;
2420 vmx->rmode.irq.vector = irq;
5fdbf976 2421 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
9c5623e3
AK		 2422 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2423 irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK);
2424 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
5fdbf976 2425 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
85f455f7
ED		 2426 return;
2427 }
2428 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2429 irq | INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
2430}
2431
f08864b4
SY		 2432static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
2433{
66a5a347
JK		 2434 struct vcpu_vmx *vmx = to_vmx(vcpu);
2435
3b86cd99
JK		 2436 if (!cpu_has_virtual_nmis()) {
2437 /*
2438 * Tracking the NMI-blocked state in software is built upon
2439 * finding the next open IRQ window. This, in turn, depends on
2440 * well-behaving guests: They have to keep IRQs disabled at
2441 * least as long as the NMI handler runs. Otherwise we may
2442 * cause NMI nesting, maybe breaking the guest. But as this is
2443 * highly unlikely, we can live with the residual risk.
2444 */
2445 vmx->soft_vnmi_blocked = 1;
2446 vmx->vnmi_blocked_time = 0;
2447 }
2448
487b391d 2449 ++vcpu->stat.nmi_injections;
66a5a347
JK		 2450 if (vcpu->arch.rmode.active) {
2451 vmx->rmode.irq.pending = true;
2452 vmx->rmode.irq.vector = NMI_VECTOR;
2453 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2454 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2455 NMI_VECTOR | INTR_TYPE_SOFT_INTR |
2456 INTR_INFO_VALID_MASK);
2457 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2458 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2459 return;
2460 }
f08864b4
SY		 2461 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2462 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
f08864b4
SY		 2463}
2464
33f089ca
JK		 2465static void vmx_update_window_states(struct kvm_vcpu *vcpu)
2466{
2467 u32 guest_intr = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2468
2469 vcpu->arch.nmi_window_open =
2470 !(guest_intr & (GUEST_INTR_STATE_STI |
2471 GUEST_INTR_STATE_MOV_SS |
2472 GUEST_INTR_STATE_NMI));
3b86cd99
JK		 2473 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
2474 vcpu->arch.nmi_window_open = 0;
33f089ca
JK		 2475
2476 vcpu->arch.interrupt_window_open =
2477 ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2478 !(guest_intr & (GUEST_INTR_STATE_STI |
2479 GUEST_INTR_STATE_MOV_SS)));
2480}
2481
6aa8b732
AK		 2482static void kvm_do_inject_irq(struct kvm_vcpu *vcpu)
2483{
ad312c7c
ZX		 2484 int word_index = __ffs(vcpu->arch.irq_summary);
2485 int bit_index = __ffs(vcpu->arch.irq_pending[word_index]);
6aa8b732
AK		 2486 int irq = word_index * BITS_PER_LONG + bit_index;
2487
ad312c7c
ZX		 2488 clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]);
2489 if (!vcpu->arch.irq_pending[word_index])
2490 clear_bit(word_index, &vcpu->arch.irq_summary);
ecfc79c7 2491 kvm_queue_interrupt(vcpu, irq);
6aa8b732
AK		 2492}
2493
f460ee43
JK		 2494static void do_interrupt_requests(struct kvm_vcpu *vcpu,
2495 struct kvm_run *kvm_run)
2496{
2497 vmx_update_window_states(vcpu);
2498
55934c0b
JK		 2499 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
2500 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
2501 GUEST_INTR_STATE_STI |
2502 GUEST_INTR_STATE_MOV_SS);
2503
3b86cd99 2504 if (vcpu->arch.nmi_pending && !vcpu->arch.nmi_injected) {
264ff01d
JK		 2505 if (vcpu->arch.interrupt.pending) {
2506 enable_nmi_window(vcpu);
2507 } else if (vcpu->arch.nmi_window_open) {
3b86cd99
JK		 2508 vcpu->arch.nmi_pending = false;
2509 vcpu->arch.nmi_injected = true;
2510 } else {
2511 enable_nmi_window(vcpu);
487b391d
JK		 2512 return;
2513 }
3b86cd99
JK		 2514 }
2515 if (vcpu->arch.nmi_injected) {
2516 vmx_inject_nmi(vcpu);
4531220b 2517 if (vcpu->arch.nmi_pending)
487b391d 2518 enable_nmi_window(vcpu);
3b86cd99
JK		 2519 else if (vcpu->arch.irq_summary
2520 || kvm_run->request_interrupt_window)
2521 enable_irq_window(vcpu);
2522 return;
487b391d
JK		 2523 }
2524
f460ee43
JK		 2525 if (vcpu->arch.interrupt_window_open) {
2526 if (vcpu->arch.irq_summary && !vcpu->arch.interrupt.pending)
2527 kvm_do_inject_irq(vcpu);
2528
2529 if (vcpu->arch.interrupt.pending)
2530 vmx_inject_irq(vcpu, vcpu->arch.interrupt.nr);
2531 }
ad312c7c
ZX		 2532 if (!vcpu->arch.interrupt_window_open &&
2533 (vcpu->arch.irq_summary || kvm_run->request_interrupt_window))
f460ee43 2534 enable_irq_window(vcpu);
6aa8b732
AK		 2535}
2536
cbc94022
IE		 2537static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
2538{
2539 int ret;
2540 struct kvm_userspace_memory_region tss_mem = {
6fe63979 2541 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 2542 .guest_phys_addr = addr,
2543 .memory_size = PAGE_SIZE * 3,
2544 .flags = 0,
2545 };
2546
2547 ret = kvm_set_memory_region(kvm, &tss_mem, 0);
2548 if (ret)
2549 return ret;
bfc6d222 2550 kvm->arch.tss_addr = addr;
cbc94022
IE		 2551 return 0;
2552}
2553
6aa8b732
AK		 2554static int handle_rmode_exception(struct kvm_vcpu *vcpu,
2555 int vec, u32 err_code)
2556{
b3f37707
NK		 2557 /*
2558 * Instruction with address size override prefix opcode 0x67
2559 * Cause the #SS fault with 0 error code in VM86 mode.
2560 */
2561 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
3427318f 2562 if (emulate_instruction(vcpu, NULL, 0, 0, 0) == EMULATE_DONE)
6aa8b732 2563 return 1;
77ab6db0
JK		 2564 /*
2565 * Forward all other exceptions that are valid in real mode.
2566 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
2567 * the required debugging infrastructure rework.
2568 */
2569 switch (vec) {
77ab6db0 2570 case DB_VECTOR:
d0bfb940
JK		 2571 if (vcpu->guest_debug &
2572 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
2573 return 0;
2574 kvm_queue_exception(vcpu, vec);
2575 return 1;
77ab6db0 2576 case BP_VECTOR:
d0bfb940
JK		 2577 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2578 return 0;
2579 /* fall through */
2580 case DE_VECTOR:
77ab6db0
JK		 2581 case OF_VECTOR:
2582 case BR_VECTOR:
2583 case UD_VECTOR:
2584 case DF_VECTOR:
2585 case SS_VECTOR:
2586 case GP_VECTOR:
2587 case MF_VECTOR:
2588 kvm_queue_exception(vcpu, vec);
2589 return 1;
2590 }
6aa8b732
AK		 2591 return 0;
2592}
2593
2594static int handle_exception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2595{
1155f76a 2596 struct vcpu_vmx *vmx = to_vmx(vcpu);
d0bfb940 2597 u32 intr_info, ex_no, error_code;
42dbaa5a 2598 unsigned long cr2, rip, dr6;
6aa8b732
AK		 2599 u32 vect_info;
2600 enum emulation_result er;
2601
1155f76a 2602 vect_info = vmx->idt_vectoring_info;
6aa8b732
AK		 2603 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
2604
2605 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
d77c26fc 2606 !is_page_fault(intr_info))
6aa8b732 2607 printk(KERN_ERR "%s: unexpected, vectoring info 0x%x "
b8688d51 2608 "intr info 0x%x\n", __func__, vect_info, intr_info);
6aa8b732 2609
85f455f7 2610 if (!irqchip_in_kernel(vcpu->kvm) && is_external_interrupt(vect_info)) {
6aa8b732 2611 int irq = vect_info & VECTORING_INFO_VECTOR_MASK;
ad312c7c
ZX		 2612 set_bit(irq, vcpu->arch.irq_pending);
2613 set_bit(irq / BITS_PER_LONG, &vcpu->arch.irq_summary);
6aa8b732
AK		 2614 }
2615
e4a41889 2616 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 2617 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 2618
2619 if (is_no_device(intr_info)) {
5fd86fcf 2620 vmx_fpu_activate(vcpu);
2ab455cc
AL		 2621 return 1;
2622 }
2623
7aa81cc0 2624 if (is_invalid_opcode(intr_info)) {
571008da 2625 er = emulate_instruction(vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD);
7aa81cc0 2626 if (er != EMULATE_DONE)
7ee5d940 2627 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 2628 return 1;
2629 }
2630
6aa8b732 2631 error_code = 0;
5fdbf976 2632 rip = kvm_rip_read(vcpu);
2e11384c 2633 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732
AK		 2634 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
2635 if (is_page_fault(intr_info)) {
1439442c
SY		 2636 /* EPT won't cause page fault directly */
2637 if (vm_need_ept())
2638 BUG();
6aa8b732 2639 cr2 = vmcs_readl(EXIT_QUALIFICATION);
2714d1d3
FEL		 2640 KVMTRACE_3D(PAGE_FAULT, vcpu, error_code, (u32)cr2,
2641 (u32)((u64)cr2 >> 32), handler);
f7d9238f 2642 if (vcpu->arch.interrupt.pending || vcpu->arch.exception.pending)
577bdc49 2643 kvm_mmu_unprotect_page_virt(vcpu, cr2);
3067714c 2644 return kvm_mmu_page_fault(vcpu, cr2, error_code);
6aa8b732
AK		 2645 }
2646
ad312c7c 2647 if (vcpu->arch.rmode.active &&
6aa8b732 2648 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
72d6e5a0 2649 error_code)) {
ad312c7c
ZX		 2650 if (vcpu->arch.halt_request) {
2651 vcpu->arch.halt_request = 0;
72d6e5a0
AK		 2652 return kvm_emulate_halt(vcpu);
2653 }
6aa8b732 2654 return 1;
72d6e5a0 2655 }
6aa8b732 2656
d0bfb940 2657 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
42dbaa5a
JK		 2658 switch (ex_no) {
2659 case DB_VECTOR:
2660 dr6 = vmcs_readl(EXIT_QUALIFICATION);
2661 if (!(vcpu->guest_debug &
2662 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
2663 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
2664 kvm_queue_exception(vcpu, DB_VECTOR);
2665 return 1;
2666 }
2667 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
2668 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
2669 /* fall through */
2670 case BP_VECTOR:
6aa8b732 2671 kvm_run->exit_reason = KVM_EXIT_DEBUG;
d0bfb940
JK		 2672 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
2673 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 2674 break;
2675 default:
d0bfb940
JK		 2676 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
2677 kvm_run->ex.exception = ex_no;
2678 kvm_run->ex.error_code = error_code;
42dbaa5a 2679 break;
6aa8b732 2680 }
6aa8b732
AK		 2681 return 0;
2682}
2683
2684static int handle_external_interrupt(struct kvm_vcpu *vcpu,
2685 struct kvm_run *kvm_run)
2686{
1165f5fe 2687 ++vcpu->stat.irq_exits;
2714d1d3 2688 KVMTRACE_1D(INTR, vcpu, vmcs_read32(VM_EXIT_INTR_INFO), handler);
6aa8b732
AK		 2689 return 1;
2690}
2691
988ad74f
AK		 2692static int handle_triple_fault(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2693{
2694 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2695 return 0;
2696}
6aa8b732 2697
6aa8b732
AK		 2698static int handle_io(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2699{
bfdaab09 2700 unsigned long exit_qualification;
34c33d16 2701 int size, in, string;
039576c0 2702 unsigned port;
6aa8b732 2703
1165f5fe 2704 ++vcpu->stat.io_exits;
bfdaab09 2705 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 2706 string = (exit_qualification & 16) != 0;
e70669ab
LV		 2707
2708 if (string) {
3427318f
LV		 2709 if (emulate_instruction(vcpu,
2710 kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
e70669ab
LV		 2711 return 0;
2712 return 1;
2713 }
2714
2715 size = (exit_qualification & 7) + 1;
2716 in = (exit_qualification & 8) != 0;
039576c0 2717 port = exit_qualification >> 16;
e70669ab 2718
e93f36bc 2719 skip_emulated_instruction(vcpu);
3090dd73 2720 return kvm_emulate_pio(vcpu, kvm_run, in, size, port);
6aa8b732
AK		 2721}
2722
102d8325
IM		 2723static void
2724vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2725{
2726 /*
2727 * Patch in the VMCALL instruction:
2728 */
2729 hypercall[0] = 0x0f;
2730 hypercall[1] = 0x01;
2731 hypercall[2] = 0xc1;
102d8325
IM		 2732}
2733
6aa8b732
AK		 2734static int handle_cr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2735{
bfdaab09 2736 unsigned long exit_qualification;
6aa8b732
AK		 2737 int cr;
2738 int reg;
2739
bfdaab09 2740 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 2741 cr = exit_qualification & 15;
2742 reg = (exit_qualification >> 8) & 15;
2743 switch ((exit_qualification >> 4) & 3) {
2744 case 0: /* mov to cr */
5fdbf976
MT		 2745 KVMTRACE_3D(CR_WRITE, vcpu, (u32)cr,
2746 (u32)kvm_register_read(vcpu, reg),
2747 (u32)((u64)kvm_register_read(vcpu, reg) >> 32),
2748 handler);
6aa8b732
AK		 2749 switch (cr) {
2750 case 0:
5fdbf976 2751 kvm_set_cr0(vcpu, kvm_register_read(vcpu, reg));
6aa8b732
AK		 2752 skip_emulated_instruction(vcpu);
2753 return 1;
2754 case 3:
5fdbf976 2755 kvm_set_cr3(vcpu, kvm_register_read(vcpu, reg));
6aa8b732
AK		 2756 skip_emulated_instruction(vcpu);
2757 return 1;
2758 case 4:
5fdbf976 2759 kvm_set_cr4(vcpu, kvm_register_read(vcpu, reg));
6aa8b732
AK		 2760 skip_emulated_instruction(vcpu);
2761 return 1;
2762 case 8:
5fdbf976 2763 kvm_set_cr8(vcpu, kvm_register_read(vcpu, reg));
6aa8b732 2764 skip_emulated_instruction(vcpu);
e5314067
AK		 2765 if (irqchip_in_kernel(vcpu->kvm))
2766 return 1;
253abdee
YS		 2767 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2768 return 0;
6aa8b732
AK		 2769 };
2770 break;
25c4c276 2771 case 2: /* clts */
5fd86fcf 2772 vmx_fpu_deactivate(vcpu);
ad312c7c
ZX		 2773 vcpu->arch.cr0 &= ~X86_CR0_TS;
2774 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf 2775 vmx_fpu_activate(vcpu);
2714d1d3 2776 KVMTRACE_0D(CLTS, vcpu, handler);
25c4c276
AL		 2777 skip_emulated_instruction(vcpu);
2778 return 1;
6aa8b732
AK		 2779 case 1: /*mov from cr*/
2780 switch (cr) {
2781 case 3:
5fdbf976 2782 kvm_register_write(vcpu, reg, vcpu->arch.cr3);
2714d1d3 2783 KVMTRACE_3D(CR_READ, vcpu, (u32)cr,
5fdbf976
MT		 2784 (u32)kvm_register_read(vcpu, reg),
2785 (u32)((u64)kvm_register_read(vcpu, reg) >> 32),
2714d1d3 2786 handler);
6aa8b732
AK		 2787 skip_emulated_instruction(vcpu);
2788 return 1;
2789 case 8:
5fdbf976 2790 kvm_register_write(vcpu, reg, kvm_get_cr8(vcpu));
2714d1d3 2791 KVMTRACE_2D(CR_READ, vcpu, (u32)cr,
5fdbf976 2792 (u32)kvm_register_read(vcpu, reg), handler);
6aa8b732
AK		 2793 skip_emulated_instruction(vcpu);
2794 return 1;
2795 }
2796 break;
2797 case 3: /* lmsw */
2d3ad1f4 2798 kvm_lmsw(vcpu, (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f);
6aa8b732
AK		 2799
2800 skip_emulated_instruction(vcpu);
2801 return 1;
2802 default:
2803 break;
2804 }
2805 kvm_run->exit_reason = 0;
f0242478 2806 pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 2807 (int)(exit_qualification >> 4) & 3, cr);
2808 return 0;
2809}
2810
2811static int handle_dr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2812{
bfdaab09 2813 unsigned long exit_qualification;
6aa8b732
AK		 2814 unsigned long val;
2815 int dr, reg;
2816
42dbaa5a
JK		 2817 dr = vmcs_readl(GUEST_DR7);
2818 if (dr & DR7_GD) {
2819 /*
2820 * As the vm-exit takes precedence over the debug trap, we
2821 * need to emulate the latter, either for the host or the
2822 * guest debugging itself.
2823 */
2824 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
2825 kvm_run->debug.arch.dr6 = vcpu->arch.dr6;
2826 kvm_run->debug.arch.dr7 = dr;
2827 kvm_run->debug.arch.pc =
2828 vmcs_readl(GUEST_CS_BASE) +
2829 vmcs_readl(GUEST_RIP);
2830 kvm_run->debug.arch.exception = DB_VECTOR;
2831 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2832 return 0;
2833 } else {
2834 vcpu->arch.dr7 &= ~DR7_GD;
2835 vcpu->arch.dr6 |= DR6_BD;
2836 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
2837 kvm_queue_exception(vcpu, DB_VECTOR);
2838 return 1;
2839 }
2840 }
2841
bfdaab09 2842 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
42dbaa5a
JK		 2843 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
2844 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
2845 if (exit_qualification & TYPE_MOV_FROM_DR) {
6aa8b732 2846 switch (dr) {
42dbaa5a
JK		 2847 case 0 ... 3:
2848 val = vcpu->arch.db[dr];
2849 break;
6aa8b732 2850 case 6:
42dbaa5a 2851 val = vcpu->arch.dr6;
6aa8b732
AK		 2852 break;
2853 case 7:
42dbaa5a 2854 val = vcpu->arch.dr7;
6aa8b732
AK		 2855 break;
2856 default:
2857 val = 0;
2858 }
5fdbf976 2859 kvm_register_write(vcpu, reg, val);
2714d1d3 2860 KVMTRACE_2D(DR_READ, vcpu, (u32)dr, (u32)val, handler);
6aa8b732 2861 } else {
42dbaa5a
JK		 2862 val = vcpu->arch.regs[reg];
2863 switch (dr) {
2864 case 0 ... 3:
2865 vcpu->arch.db[dr] = val;
2866 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
2867 vcpu->arch.eff_db[dr] = val;
2868 break;
2869 case 4 ... 5:
2870 if (vcpu->arch.cr4 & X86_CR4_DE)
2871 kvm_queue_exception(vcpu, UD_VECTOR);
2872 break;
2873 case 6:
2874 if (val & 0xffffffff00000000ULL) {
2875 kvm_queue_exception(vcpu, GP_VECTOR);
2876 break;
2877 }
2878 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
2879 break;
2880 case 7:
2881 if (val & 0xffffffff00000000ULL) {
2882 kvm_queue_exception(vcpu, GP_VECTOR);
2883 break;
2884 }
2885 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
2886 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
2887 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
2888 vcpu->arch.switch_db_regs =
2889 (val & DR7_BP_EN_MASK);
2890 }
2891 break;
2892 }
2893 KVMTRACE_2D(DR_WRITE, vcpu, (u32)dr, (u32)val, handler);
6aa8b732 2894 }
6aa8b732
AK		 2895 skip_emulated_instruction(vcpu);
2896 return 1;
2897}
2898
2899static int handle_cpuid(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2900{
06465c5a
AK		 2901 kvm_emulate_cpuid(vcpu);
2902 return 1;
6aa8b732
AK		 2903}
2904
2905static int handle_rdmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2906{
ad312c7c 2907 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 2908 u64 data;
2909
2910 if (vmx_get_msr(vcpu, ecx, &data)) {
c1a5d4f9 2911 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 2912 return 1;
2913 }
2914
2714d1d3
FEL		 2915 KVMTRACE_3D(MSR_READ, vcpu, ecx, (u32)data, (u32)(data >> 32),
2916 handler);
2917
6aa8b732 2918 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 2919 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
2920 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 2921 skip_emulated_instruction(vcpu);
2922 return 1;
2923}
2924
2925static int handle_wrmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2926{
ad312c7c
ZX		 2927 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
2928 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
2929 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732 2930
2714d1d3
FEL		 2931 KVMTRACE_3D(MSR_WRITE, vcpu, ecx, (u32)data, (u32)(data >> 32),
2932 handler);
2933
6aa8b732 2934 if (vmx_set_msr(vcpu, ecx, data) != 0) {
c1a5d4f9 2935 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 2936 return 1;
2937 }
2938
2939 skip_emulated_instruction(vcpu);
2940 return 1;
2941}
2942
6e5d865c
YS		 2943static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu,
2944 struct kvm_run *kvm_run)
2945{
2946 return 1;
2947}
2948
6aa8b732
AK		 2949static int handle_interrupt_window(struct kvm_vcpu *vcpu,
2950 struct kvm_run *kvm_run)
2951{
85f455f7
ED		 2952 u32 cpu_based_vm_exec_control;
2953
2954 /* clear pending irq */
2955 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2956 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
2957 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3
FEL		 2958
2959 KVMTRACE_0D(PEND_INTR, vcpu, handler);
a26bf12a 2960 ++vcpu->stat.irq_window_exits;
2714d1d3 2961
c1150d8c
DL		 2962 /*
2963 * If the user space waits to inject interrupts, exit as soon as
2964 * possible
2965 */
2966 if (kvm_run->request_interrupt_window &&
ad312c7c 2967 !vcpu->arch.irq_summary) {
c1150d8c 2968 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
c1150d8c
DL		 2969 return 0;
2970 }
6aa8b732
AK		 2971 return 1;
2972}
2973
2974static int handle_halt(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2975{
2976 skip_emulated_instruction(vcpu);
d3bef15f 2977 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 2978}
2979
c21415e8
IM		 2980static int handle_vmcall(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2981{
510043da 2982 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 2983 kvm_emulate_hypercall(vcpu);
2984 return 1;
c21415e8
IM		 2985}
2986
a7052897
MT		 2987static int handle_invlpg(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2988{
2989 u64 exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
2990
2991 kvm_mmu_invlpg(vcpu, exit_qualification);
2992 skip_emulated_instruction(vcpu);
2993 return 1;
2994}
2995
e5edaa01
ED		 2996static int handle_wbinvd(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2997{
2998 skip_emulated_instruction(vcpu);
2999 /* TODO: Add support for VT-d/pass-through device */
3000 return 1;
3001}
3002
f78e0e2e
SY		 3003static int handle_apic_access(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3004{
3005 u64 exit_qualification;
3006 enum emulation_result er;
3007 unsigned long offset;
3008
3009 exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
3010 offset = exit_qualification & 0xffful;
3011
3012 er = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
3013
3014 if (er != EMULATE_DONE) {
3015 printk(KERN_ERR
3016 "Fail to handle apic access vmexit! Offset is 0x%lx\n",
3017 offset);
3018 return -ENOTSUPP;
3019 }
3020 return 1;
3021}
3022
37817f29
IE		 3023static int handle_task_switch(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3024{
60637aac 3025 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29
IE		 3026 unsigned long exit_qualification;
3027 u16 tss_selector;
3028 int reason;
3029
3030 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3031
3032 reason = (u32)exit_qualification >> 30;
60637aac
JK		 3033 if (reason == TASK_SWITCH_GATE && vmx->vcpu.arch.nmi_injected &&
3034 (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
3035 (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK)
3036 == INTR_TYPE_NMI_INTR) {
3037 vcpu->arch.nmi_injected = false;
3038 if (cpu_has_virtual_nmis())
3039 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3040 GUEST_INTR_STATE_NMI);
3041 }
37817f29
IE		 3042 tss_selector = exit_qualification;
3043
42dbaa5a
JK		 3044 if (!kvm_task_switch(vcpu, tss_selector, reason))
3045 return 0;
3046
3047 /* clear all local breakpoint enable flags */
3048 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
3049
3050 /*
3051 * TODO: What about debug traps on tss switch?
3052 * Are we supposed to inject them and update dr6?
3053 */
3054
3055 return 1;
37817f29
IE		 3056}
3057
1439442c
SY		 3058static int handle_ept_violation(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3059{
3060 u64 exit_qualification;
1439442c 3061 gpa_t gpa;
1439442c 3062 int gla_validity;
1439442c
SY		 3063
3064 exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
3065
3066 if (exit_qualification & (1 << 6)) {
3067 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
3068 return -ENOTSUPP;
3069 }
3070
3071 gla_validity = (exit_qualification >> 7) & 0x3;
3072 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
3073 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
3074 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3075 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
3076 (long unsigned int)vmcs_read64(GUEST_LINEAR_ADDRESS));
3077 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
3078 (long unsigned int)exit_qualification);
3079 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
3080 kvm_run->hw.hardware_exit_reason = 0;
3081 return -ENOTSUPP;
3082 }
3083
3084 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
49cd7d22 3085 return kvm_mmu_page_fault(vcpu, gpa & PAGE_MASK, 0);
1439442c
SY		 3086}
3087
f08864b4
SY		 3088static int handle_nmi_window(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3089{
3090 u32 cpu_based_vm_exec_control;
3091
3092 /* clear pending NMI */
3093 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3094 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
3095 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3096 ++vcpu->stat.nmi_window_exits;
3097
3098 return 1;
3099}
3100
ea953ef0
MG		 3101static void handle_invalid_guest_state(struct kvm_vcpu *vcpu,
3102 struct kvm_run *kvm_run)
3103{
8b3079a5
AK		 3104 struct vcpu_vmx *vmx = to_vmx(vcpu);
3105 enum emulation_result err = EMULATE_DONE;
ea953ef0
MG		 3106
3107 preempt_enable();
3108 local_irq_enable();
3109
3110 while (!guest_state_valid(vcpu)) {
3111 err = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
3112
1d5a4d9b
GT		 3113 if (err == EMULATE_DO_MMIO)
3114 break;
3115
3116 if (err != EMULATE_DONE) {
3117 kvm_report_emulation_failure(vcpu, "emulation failure");
3118 return;
ea953ef0
MG		 3119 }
3120
3121 if (signal_pending(current))
3122 break;
3123 if (need_resched())
3124 schedule();
3125 }
3126
3127 local_irq_disable();
3128 preempt_disable();
8b3079a5
AK		 3129
3130 vmx->invalid_state_emulation_result = err;
ea953ef0
MG		 3131}
3132
6aa8b732
AK		 3133/*
3134 * The exit handlers return 1 if the exit was handled fully and guest execution
3135 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
3136 * to be done to userspace and return 0.
3137 */
3138static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu,
3139 struct kvm_run *kvm_run) = {
3140 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
3141 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 3142 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 3143 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 3144 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 3145 [EXIT_REASON_CR_ACCESS] = handle_cr,
3146 [EXIT_REASON_DR_ACCESS] = handle_dr,
3147 [EXIT_REASON_CPUID] = handle_cpuid,
3148 [EXIT_REASON_MSR_READ] = handle_rdmsr,
3149 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
3150 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
3151 [EXIT_REASON_HLT] = handle_halt,
a7052897 3152 [EXIT_REASON_INVLPG] = handle_invlpg,
c21415e8 3153 [EXIT_REASON_VMCALL] = handle_vmcall,
f78e0e2e
SY		 3154 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
3155 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
e5edaa01 3156 [EXIT_REASON_WBINVD] = handle_wbinvd,
37817f29 3157 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
1439442c 3158 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
6aa8b732
AK		 3159};
3160
3161static const int kvm_vmx_max_exit_handlers =
50a3485c 3162 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732
AK		 3163
3164/*
3165 * The guest has exited. See if we can fix it or if we need userspace
3166 * assistance.
3167 */
3168static int kvm_handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
3169{
6aa8b732 3170 u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
29bd8a78 3171 struct vcpu_vmx *vmx = to_vmx(vcpu);
1155f76a 3172 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 3173
5fdbf976
MT		 3174 KVMTRACE_3D(VMEXIT, vcpu, exit_reason, (u32)kvm_rip_read(vcpu),
3175 (u32)((u64)kvm_rip_read(vcpu) >> 32), entryexit);
2714d1d3 3176
1d5a4d9b
GT		 3177 /* If we need to emulate an MMIO from handle_invalid_guest_state
3178 * we just return 0 */
10f32d84
AK		 3179 if (vmx->emulation_required && emulate_invalid_guest_state) {
3180 if (guest_state_valid(vcpu))
3181 vmx->emulation_required = 0;
8b3079a5 3182 return vmx->invalid_state_emulation_result != EMULATE_DO_MMIO;
10f32d84 3183 }
1d5a4d9b 3184
1439442c
SY		 3185 /* Access CR3 don't cause VMExit in paging mode, so we need
3186 * to sync with guest real CR3. */
3187 if (vm_need_ept() && is_paging(vcpu)) {
3188 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3189 ept_load_pdptrs(vcpu);
3190 }
3191
29bd8a78
AK		 3192 if (unlikely(vmx->fail)) {
3193 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3194 kvm_run->fail_entry.hardware_entry_failure_reason
3195 = vmcs_read32(VM_INSTRUCTION_ERROR);
3196 return 0;
3197 }
6aa8b732 3198
d77c26fc 3199 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 3200 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac
JK		 3201 exit_reason != EXIT_REASON_EPT_VIOLATION &&
3202 exit_reason != EXIT_REASON_TASK_SWITCH))
3203 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
3204 "(0x%x) and exit reason is 0x%x\n",
3205 __func__, vectoring_info, exit_reason);
3b86cd99
JK		 3206
3207 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) {
3208 if (vcpu->arch.interrupt_window_open) {
3209 vmx->soft_vnmi_blocked = 0;
3210 vcpu->arch.nmi_window_open = 1;
3211 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 3212 vcpu->arch.nmi_pending) {
3b86cd99
JK		 3213 /*
3214 * This CPU don't support us in finding the end of an
3215 * NMI-blocked window if the guest runs with IRQs
3216 * disabled. So we pull the trigger after 1 s of
3217 * futile waiting, but inform the user about this.
3218 */
3219 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
3220 "state on VCPU %d after 1 s timeout\n",
3221 __func__, vcpu->vcpu_id);
3222 vmx->soft_vnmi_blocked = 0;
3223 vmx->vcpu.arch.nmi_window_open = 1;
3224 }
3b86cd99
JK		 3225 }
3226
6aa8b732
AK		 3227 if (exit_reason < kvm_vmx_max_exit_handlers
3228 && kvm_vmx_exit_handlers[exit_reason])
3229 return kvm_vmx_exit_handlers[exit_reason](vcpu, kvm_run);
3230 else {
3231 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
3232 kvm_run->hw.hardware_exit_reason = exit_reason;
3233 }
3234 return 0;
3235}
3236
6e5d865c
YS		 3237static void update_tpr_threshold(struct kvm_vcpu *vcpu)
3238{
3239 int max_irr, tpr;
3240
3241 if (!vm_need_tpr_shadow(vcpu->kvm))
3242 return;
3243
3244 if (!kvm_lapic_enabled(vcpu) ||
3245 ((max_irr = kvm_lapic_find_highest_irr(vcpu)) == -1)) {
3246 vmcs_write32(TPR_THRESHOLD, 0);
3247 return;
3248 }
3249
3250 tpr = (kvm_lapic_get_cr8(vcpu) & 0x0f) << 4;
3251 vmcs_write32(TPR_THRESHOLD, (max_irr > tpr) ? tpr >> 4 : max_irr >> 4);
3252}
3253
cf393f75
AK		 3254static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
3255{
3256 u32 exit_intr_info;
668f612f 3257 u32 idt_vectoring_info;
cf393f75
AK		 3258 bool unblock_nmi;
3259 u8 vector;
668f612f
AK		 3260 int type;
3261 bool idtv_info_valid;
35920a35 3262 u32 error;
cf393f75
AK		 3263
3264 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3265 if (cpu_has_virtual_nmis()) {
3266 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
3267 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
3268 /*
3269 * SDM 3: 25.7.1.2
3270 * Re-set bit "block by NMI" before VM entry if vmexit caused by
3271 * a guest IRET fault.
3272 */
3273 if (unblock_nmi && vector != DF_VECTOR)
3274 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3275 GUEST_INTR_STATE_NMI);
3b86cd99
JK		 3276 } else if (unlikely(vmx->soft_vnmi_blocked))
3277 vmx->vnmi_blocked_time +=
3278 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
668f612f
AK		 3279
3280 idt_vectoring_info = vmx->idt_vectoring_info;
3281 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
3282 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
3283 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
3284 if (vmx->vcpu.arch.nmi_injected) {
3285 /*
3286 * SDM 3: 25.7.1.2
3287 * Clear bit "block by NMI" before VM entry if a NMI delivery
3288 * faulted.
3289 */
3290 if (idtv_info_valid && type == INTR_TYPE_NMI_INTR)
3291 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3292 GUEST_INTR_STATE_NMI);
3293 else
3294 vmx->vcpu.arch.nmi_injected = false;
3295 }
35920a35 3296 kvm_clear_exception_queue(&vmx->vcpu);
8ab2d2e2
JK		 3297 if (idtv_info_valid && (type == INTR_TYPE_HARD_EXCEPTION ||
3298 type == INTR_TYPE_SOFT_EXCEPTION)) {
35920a35
AK		 3299 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
3300 error = vmcs_read32(IDT_VECTORING_ERROR_CODE);
3301 kvm_queue_exception_e(&vmx->vcpu, vector, error);
3302 } else
3303 kvm_queue_exception(&vmx->vcpu, vector);
3304 vmx->idt_vectoring_info = 0;
3305 }
f7d9238f
AK		 3306 kvm_clear_interrupt_queue(&vmx->vcpu);
3307 if (idtv_info_valid && type == INTR_TYPE_EXT_INTR) {
3308 kvm_queue_interrupt(&vmx->vcpu, vector);
3309 vmx->idt_vectoring_info = 0;
3310 }
cf393f75
AK		 3311}
3312
85f455f7
ED		 3313static void vmx_intr_assist(struct kvm_vcpu *vcpu)
3314{
6e5d865c
YS		 3315 update_tpr_threshold(vcpu);
3316
33f089ca
JK		 3317 vmx_update_window_states(vcpu);
3318
55934c0b
JK		 3319 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
3320 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3321 GUEST_INTR_STATE_STI |
3322 GUEST_INTR_STATE_MOV_SS);
3323
3b86cd99
JK		 3324 if (vcpu->arch.nmi_pending && !vcpu->arch.nmi_injected) {
3325 if (vcpu->arch.interrupt.pending) {
3326 enable_nmi_window(vcpu);
3327 } else if (vcpu->arch.nmi_window_open) {
3328 vcpu->arch.nmi_pending = false;
3329 vcpu->arch.nmi_injected = true;
3330 } else {
3331 enable_nmi_window(vcpu);
f08864b4
SY		 3332 return;
3333 }
f08864b4 3334 }
3b86cd99
JK		 3335 if (vcpu->arch.nmi_injected) {
3336 vmx_inject_nmi(vcpu);
3337 if (vcpu->arch.nmi_pending)
3338 enable_nmi_window(vcpu);
3339 else if (kvm_cpu_has_interrupt(vcpu))
3340 enable_irq_window(vcpu);
3341 return;
3342 }
f7d9238f 3343 if (!vcpu->arch.interrupt.pending && kvm_cpu_has_interrupt(vcpu)) {
33f089ca 3344 if (vcpu->arch.interrupt_window_open)
f7d9238f
AK		 3345 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu));
3346 else
3347 enable_irq_window(vcpu);
3348 }
3349 if (vcpu->arch.interrupt.pending) {
3350 vmx_inject_irq(vcpu, vcpu->arch.interrupt.nr);
df203ec9
AK		 3351 if (kvm_cpu_has_interrupt(vcpu))
3352 enable_irq_window(vcpu);
f7d9238f 3353 }
85f455f7
ED		 3354}
3355
9c8cba37
AK		 3356/*
3357 * Failure to inject an interrupt should give us the information
3358 * in IDT_VECTORING_INFO_FIELD. However, if the failure occurs
3359 * when fetching the interrupt redirection bitmap in the real-mode
3360 * tss, this doesn't happen. So we do it ourselves.
3361 */
3362static void fixup_rmode_irq(struct vcpu_vmx *vmx)
3363{
3364 vmx->rmode.irq.pending = 0;
5fdbf976 3365 if (kvm_rip_read(&vmx->vcpu) + 1 != vmx->rmode.irq.rip)
9c8cba37 3366 return;
5fdbf976 3367 kvm_rip_write(&vmx->vcpu, vmx->rmode.irq.rip);
9c8cba37
AK		 3368 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
3369 vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK;
3370 vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR;
3371 return;
3372 }
3373 vmx->idt_vectoring_info =
3374 VECTORING_INFO_VALID_MASK
3375 | INTR_TYPE_EXT_INTR
3376 | vmx->rmode.irq.vector;
3377}
3378
c801949d
AK		 3379#ifdef CONFIG_X86_64
3380#define R "r"
3381#define Q "q"
3382#else
3383#define R "e"
3384#define Q "l"
3385#endif
3386
04d2cc77 3387static void vmx_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6aa8b732 3388{
a2fa3e9f 3389 struct vcpu_vmx *vmx = to_vmx(vcpu);
1b6269db 3390 u32 intr_info;
e6adf283 3391
3b86cd99
JK		 3392 /* Record the guest's net vcpu time for enforced NMI injections. */
3393 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
3394 vmx->entry_time = ktime_get();
3395
a89a8fb9
MG		 3396 /* Handle invalid guest state instead of entering VMX */
3397 if (vmx->emulation_required && emulate_invalid_guest_state) {
3398 handle_invalid_guest_state(vcpu, kvm_run);
3399 return;
3400 }
3401
5fdbf976
MT		 3402 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
3403 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
3404 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
3405 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
3406
e6adf283
AK		 3407 /*
3408 * Loading guest fpu may have cleared host cr0.ts
3409 */
3410 vmcs_writel(HOST_CR0, read_cr0());
3411
42dbaa5a
JK		 3412 set_debugreg(vcpu->arch.dr6, 6);
3413
d77c26fc 3414 asm(
6aa8b732 3415 /* Store host registers */
c801949d
AK		 3416 "push %%"R"dx; push %%"R"bp;"
3417 "push %%"R"cx \n\t"
313dbd49
AK		 3418 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
3419 "je 1f \n\t"
3420 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
4ecac3fd 3421 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 3422 "1: \n\t"
6aa8b732 3423 /* Check if vmlaunch of vmresume is needed */
e08aa78a 3424 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 3425 /* Load guest registers. Don't clobber flags. */
c801949d
AK		 3426 "mov %c[cr2](%0), %%"R"ax \n\t"
3427 "mov %%"R"ax, %%cr2 \n\t"
3428 "mov %c[rax](%0), %%"R"ax \n\t"
3429 "mov %c[rbx](%0), %%"R"bx \n\t"
3430 "mov %c[rdx](%0), %%"R"dx \n\t"
3431 "mov %c[rsi](%0), %%"R"si \n\t"
3432 "mov %c[rdi](%0), %%"R"di \n\t"
3433 "mov %c[rbp](%0), %%"R"bp \n\t"
05b3e0c2 3434#ifdef CONFIG_X86_64
e08aa78a
AK		 3435 "mov %c[r8](%0), %%r8 \n\t"
3436 "mov %c[r9](%0), %%r9 \n\t"
3437 "mov %c[r10](%0), %%r10 \n\t"
3438 "mov %c[r11](%0), %%r11 \n\t"
3439 "mov %c[r12](%0), %%r12 \n\t"
3440 "mov %c[r13](%0), %%r13 \n\t"
3441 "mov %c[r14](%0), %%r14 \n\t"
3442 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 3443#endif
c801949d
AK		 3444 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
3445
6aa8b732 3446 /* Enter guest mode */
cd2276a7 3447 "jne .Llaunched \n\t"
4ecac3fd 3448 __ex(ASM_VMX_VMLAUNCH) "\n\t"
cd2276a7 3449 "jmp .Lkvm_vmx_return \n\t"
4ecac3fd 3450 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
cd2276a7 3451 ".Lkvm_vmx_return: "
6aa8b732 3452 /* Save guest registers, load host registers, keep flags */
c801949d
AK		 3453 "xchg %0, (%%"R"sp) \n\t"
3454 "mov %%"R"ax, %c[rax](%0) \n\t"
3455 "mov %%"R"bx, %c[rbx](%0) \n\t"
3456 "push"Q" (%%"R"sp); pop"Q" %c[rcx](%0) \n\t"
3457 "mov %%"R"dx, %c[rdx](%0) \n\t"
3458 "mov %%"R"si, %c[rsi](%0) \n\t"
3459 "mov %%"R"di, %c[rdi](%0) \n\t"
3460 "mov %%"R"bp, %c[rbp](%0) \n\t"
05b3e0c2 3461#ifdef CONFIG_X86_64
e08aa78a
AK		 3462 "mov %%r8, %c[r8](%0) \n\t"
3463 "mov %%r9, %c[r9](%0) \n\t"
3464 "mov %%r10, %c[r10](%0) \n\t"
3465 "mov %%r11, %c[r11](%0) \n\t"
3466 "mov %%r12, %c[r12](%0) \n\t"
3467 "mov %%r13, %c[r13](%0) \n\t"
3468 "mov %%r14, %c[r14](%0) \n\t"
3469 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 3470#endif
c801949d
AK		 3471 "mov %%cr2, %%"R"ax \n\t"
3472 "mov %%"R"ax, %c[cr2](%0) \n\t"
3473
3474 "pop %%"R"bp; pop %%"R"bp; pop %%"R"dx \n\t"
e08aa78a
AK		 3475 "setbe %c[fail](%0) \n\t"
3476 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
3477 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
3478 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 3479 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 3480 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
3481 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
3482 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
3483 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
3484 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
3485 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
3486 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 3487#ifdef CONFIG_X86_64
ad312c7c
ZX		 3488 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
3489 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
3490 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
3491 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
3492 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
3493 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
3494 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
3495 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 3496#endif
ad312c7c 3497 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2))
c2036300 3498 : "cc", "memory"
c801949d 3499 , R"bx", R"di", R"si"
c2036300 3500#ifdef CONFIG_X86_64
c2036300
LV		 3501 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3502#endif
3503 );
6aa8b732 3504
5fdbf976
MT		 3505 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
3506 vcpu->arch.regs_dirty = 0;
3507
42dbaa5a
JK		 3508 get_debugreg(vcpu->arch.dr6, 6);
3509
1155f76a 3510 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
9c8cba37
AK		 3511 if (vmx->rmode.irq.pending)
3512 fixup_rmode_irq(vmx);
1155f76a 3513
33f089ca 3514 vmx_update_window_states(vcpu);
6aa8b732 3515
d77c26fc 3516 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
15ad7146 3517 vmx->launched = 1;
1b6269db
AK		 3518
3519 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3520
3521 /* We need to handle NMIs before interrupts are enabled */
e4a41889 3522 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
f08864b4 3523 (intr_info & INTR_INFO_VALID_MASK)) {
2714d1d3 3524 KVMTRACE_0D(NMI, vcpu, handler);
1b6269db 3525 asm("int $2");
2714d1d3 3526 }
cf393f75
AK		 3527
3528 vmx_complete_interrupts(vmx);
6aa8b732
AK		 3529}
3530
c801949d
AK		 3531#undef R
3532#undef Q
3533
6aa8b732
AK		 3534static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
3535{
a2fa3e9f
GH		 3536 struct vcpu_vmx *vmx = to_vmx(vcpu);
3537
3538 if (vmx->vmcs) {
543e4243 3539 vcpu_clear(vmx);
a2fa3e9f
GH		 3540 free_vmcs(vmx->vmcs);
3541 vmx->vmcs = NULL;
6aa8b732
AK		 3542 }
3543}
3544
3545static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
3546{
fb3f0f51
RR		 3547 struct vcpu_vmx *vmx = to_vmx(vcpu);
3548
2384d2b3
SY		 3549 spin_lock(&vmx_vpid_lock);
3550 if (vmx->vpid != 0)
3551 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3552 spin_unlock(&vmx_vpid_lock);
6aa8b732 3553 vmx_free_vmcs(vcpu);
fb3f0f51
RR		 3554 kfree(vmx->host_msrs);
3555 kfree(vmx->guest_msrs);
3556 kvm_vcpu_uninit(vcpu);
a4770347 3557 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 3558}
3559
fb3f0f51 3560static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 3561{
fb3f0f51 3562 int err;
c16f862d 3563 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 3564 int cpu;
6aa8b732 3565
a2fa3e9f 3566 if (!vmx)
fb3f0f51
RR		 3567 return ERR_PTR(-ENOMEM);
3568
2384d2b3
SY		 3569 allocate_vpid(vmx);
3570
fb3f0f51
RR		 3571 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
3572 if (err)
3573 goto free_vcpu;
965b58a5 3574
a2fa3e9f 3575 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
fb3f0f51
RR		 3576 if (!vmx->guest_msrs) {
3577 err = -ENOMEM;
3578 goto uninit_vcpu;
3579 }
965b58a5 3580
a2fa3e9f
GH		 3581 vmx->host_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
3582 if (!vmx->host_msrs)
fb3f0f51 3583 goto free_guest_msrs;
965b58a5 3584
a2fa3e9f
GH		 3585 vmx->vmcs = alloc_vmcs();
3586 if (!vmx->vmcs)
fb3f0f51 3587 goto free_msrs;
a2fa3e9f
GH		 3588
3589 vmcs_clear(vmx->vmcs);
3590
15ad7146
AK		 3591 cpu = get_cpu();
3592 vmx_vcpu_load(&vmx->vcpu, cpu);
8b9cf98c 3593 err = vmx_vcpu_setup(vmx);
fb3f0f51 3594 vmx_vcpu_put(&vmx->vcpu);
15ad7146 3595 put_cpu();
fb3f0f51
RR		 3596 if (err)
3597 goto free_vmcs;
5e4a0b3c
MT		 3598 if (vm_need_virtualize_apic_accesses(kvm))
3599 if (alloc_apic_access_page(kvm) != 0)
3600 goto free_vmcs;
fb3f0f51 3601
b7ebfb05
SY		 3602 if (vm_need_ept())
3603 if (alloc_identity_pagetable(kvm) != 0)
3604 goto free_vmcs;
3605
fb3f0f51
RR		 3606 return &vmx->vcpu;
3607
3608free_vmcs:
3609 free_vmcs(vmx->vmcs);
3610free_msrs:
3611 kfree(vmx->host_msrs);
3612free_guest_msrs:
3613 kfree(vmx->guest_msrs);
3614uninit_vcpu:
3615 kvm_vcpu_uninit(&vmx->vcpu);
3616free_vcpu:
a4770347 3617 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 3618 return ERR_PTR(err);
6aa8b732
AK		 3619}
3620
002c7f7c
YS		 3621static void __init vmx_check_processor_compat(void *rtn)
3622{
3623 struct vmcs_config vmcs_conf;
3624
3625 *(int *)rtn = 0;
3626 if (setup_vmcs_config(&vmcs_conf) < 0)
3627 *(int *)rtn = -EIO;
3628 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
3629 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
3630 smp_processor_id());
3631 *(int *)rtn = -EIO;
3632 }
3633}
3634
67253af5
SY		 3635static int get_ept_level(void)
3636{
3637 return VMX_EPT_DEFAULT_GAW + 1;
3638}
3639
64d4d521
SY		 3640static int vmx_get_mt_mask_shift(void)
3641{
3642 return VMX_EPT_MT_EPTE_SHIFT;
3643}
3644
cbdd1bea 3645static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 3646 .cpu_has_kvm_support = cpu_has_kvm_support,
3647 .disabled_by_bios = vmx_disabled_by_bios,
3648 .hardware_setup = hardware_setup,
3649 .hardware_unsetup = hardware_unsetup,
002c7f7c 3650 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 3651 .hardware_enable = hardware_enable,
3652 .hardware_disable = hardware_disable,
774ead3a 3653 .cpu_has_accelerated_tpr = cpu_has_vmx_virtualize_apic_accesses,
6aa8b732
AK		 3654
3655 .vcpu_create = vmx_create_vcpu,
3656 .vcpu_free = vmx_free_vcpu,
04d2cc77 3657 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 3658
04d2cc77 3659 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 3660 .vcpu_load = vmx_vcpu_load,
3661 .vcpu_put = vmx_vcpu_put,
3662
3663 .set_guest_debug = set_guest_debug,
3664 .get_msr = vmx_get_msr,
3665 .set_msr = vmx_set_msr,
3666 .get_segment_base = vmx_get_segment_base,
3667 .get_segment = vmx_get_segment,
3668 .set_segment = vmx_set_segment,
2e4d2653 3669 .get_cpl = vmx_get_cpl,
6aa8b732 3670 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
25c4c276 3671 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 3672 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 3673 .set_cr3 = vmx_set_cr3,
3674 .set_cr4 = vmx_set_cr4,
6aa8b732 3675 .set_efer = vmx_set_efer,
6aa8b732
AK		 3676 .get_idt = vmx_get_idt,
3677 .set_idt = vmx_set_idt,
3678 .get_gdt = vmx_get_gdt,
3679 .set_gdt = vmx_set_gdt,
5fdbf976 3680 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 3681 .get_rflags = vmx_get_rflags,
3682 .set_rflags = vmx_set_rflags,
3683
3684 .tlb_flush = vmx_flush_tlb,
6aa8b732 3685
6aa8b732 3686 .run = vmx_vcpu_run,
04d2cc77 3687 .handle_exit = kvm_handle_exit,
6aa8b732 3688 .skip_emulated_instruction = skip_emulated_instruction,
102d8325 3689 .patch_hypercall = vmx_patch_hypercall,
2a8067f1
ED		 3690 .get_irq = vmx_get_irq,
3691 .set_irq = vmx_inject_irq,
298101da
AK		 3692 .queue_exception = vmx_queue_exception,
3693 .exception_injected = vmx_exception_injected,
04d2cc77
AK		 3694 .inject_pending_irq = vmx_intr_assist,
3695 .inject_pending_vectors = do_interrupt_requests,
cbc94022
IE		 3696
3697 .set_tss_addr = vmx_set_tss_addr,
67253af5 3698 .get_tdp_level = get_ept_level,
64d4d521 3699 .get_mt_mask_shift = vmx_get_mt_mask_shift,
6aa8b732
AK		 3700};
3701
3702static int __init vmx_init(void)
3703{
25c5f225 3704 void *va;
fdef3ad1
HQ		 3705 int r;
3706
3707 vmx_io_bitmap_a = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
3708 if (!vmx_io_bitmap_a)
3709 return -ENOMEM;
3710
3711 vmx_io_bitmap_b = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
3712 if (!vmx_io_bitmap_b) {
3713 r = -ENOMEM;
3714 goto out;
3715 }
3716
25c5f225
SY		 3717 vmx_msr_bitmap = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
3718 if (!vmx_msr_bitmap) {
3719 r = -ENOMEM;
3720 goto out1;
3721 }
3722
fdef3ad1
HQ		 3723 /*
3724 * Allow direct access to the PC debug port (it is often used for I/O
3725 * delays, but the vmexits simply slow things down).
3726 */
25c5f225
SY		 3727 va = kmap(vmx_io_bitmap_a);
3728 memset(va, 0xff, PAGE_SIZE);
3729 clear_bit(0x80, va);
cd0536d7 3730 kunmap(vmx_io_bitmap_a);
fdef3ad1 3731
25c5f225
SY		 3732 va = kmap(vmx_io_bitmap_b);
3733 memset(va, 0xff, PAGE_SIZE);
cd0536d7 3734 kunmap(vmx_io_bitmap_b);
fdef3ad1 3735
25c5f225
SY		 3736 va = kmap(vmx_msr_bitmap);
3737 memset(va, 0xff, PAGE_SIZE);
3738 kunmap(vmx_msr_bitmap);
3739
2384d2b3
SY		 3740 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
3741
cb498ea2 3742 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 3743 if (r)
25c5f225
SY		 3744 goto out2;
3745
3746 vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_FS_BASE);
3747 vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_GS_BASE);
3748 vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_IA32_SYSENTER_CS);
3749 vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_IA32_SYSENTER_ESP);
3750 vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_IA32_SYSENTER_EIP);
fdef3ad1 3751
5fdbcb9d 3752 if (vm_need_ept()) {
1439442c 3753 bypass_guest_pf = 0;
5fdbcb9d 3754 kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK |
2aaf69dc 3755 VMX_EPT_WRITABLE_MASK);
534e38b4 3756 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
64d4d521
SY		 3757 VMX_EPT_EXECUTABLE_MASK,
3758 VMX_EPT_DEFAULT_MT << VMX_EPT_MT_EPTE_SHIFT);
5fdbcb9d
SY		 3759 kvm_enable_tdp();
3760 } else
3761 kvm_disable_tdp();
1439442c 3762
c7addb90
AK		 3763 if (bypass_guest_pf)
3764 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
3765
1439442c
SY		 3766 ept_sync_global();
3767
fdef3ad1
HQ		 3768 return 0;
3769
25c5f225
SY		 3770out2:
3771 __free_page(vmx_msr_bitmap);
fdef3ad1
HQ		 3772out1:
3773 __free_page(vmx_io_bitmap_b);
3774out:
3775 __free_page(vmx_io_bitmap_a);
3776 return r;
6aa8b732
AK		 3777}
3778
3779static void __exit vmx_exit(void)
3780{
25c5f225 3781 __free_page(vmx_msr_bitmap);
fdef3ad1
HQ		 3782 __free_page(vmx_io_bitmap_b);
3783 __free_page(vmx_io_bitmap_a);
3784
cb498ea2 3785 kvm_exit();
6aa8b732
AK		 3786}
3787
3788module_init(vmx_init)
3789module_exit(vmx_exit)
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