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KVM: Fix msr trace
[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
8 *
9 * Authors:
10 * Avi Kivity <avi@qumranet.com>
11 * Yaniv Kamay <yaniv@qumranet.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
15 *
16 */
17
85f455f7 18#include "irq.h"
1d737c8a 19#include "mmu.h"
e495606d 20
edf88417 21#include <linux/kvm_host.h>
6aa8b732 22#include <linux/module.h>
9d8f549d 23#include <linux/kernel.h>
6aa8b732
AK		 24#include <linux/mm.h>
25#include <linux/highmem.h>
e8edc6e0 26#include <linux/sched.h>
c7addb90 27#include <linux/moduleparam.h>
229456fc 28#include <linux/ftrace_event.h>
5fdbf976 29#include "kvm_cache_regs.h"
35920a35 30#include "x86.h"
e495606d 31
6aa8b732 32#include <asm/io.h>
3b3be0d1 33#include <asm/desc.h>
13673a90 34#include <asm/vmx.h>
6210e37b 35#include <asm/virtext.h>
a0861c02 36#include <asm/mce.h>
6aa8b732 37
229456fc
MT		 38#include "trace.h"
39
4ecac3fd
AK		 40#define __ex(x) __kvm_handle_fault_on_reboot(x)
41
6aa8b732
AK		 42MODULE_AUTHOR("Qumranet");
43MODULE_LICENSE("GPL");
44
4462d21a 45static int __read_mostly bypass_guest_pf = 1;
c1f8bc04 46module_param(bypass_guest_pf, bool, S_IRUGO);
c7addb90 47
4462d21a 48static int __read_mostly enable_vpid = 1;
736caefe 49module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 50
4462d21a 51static int __read_mostly flexpriority_enabled = 1;
736caefe 52module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 53
4462d21a 54static int __read_mostly enable_ept = 1;
736caefe 55module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 56
3a624e29
NK		 57static int __read_mostly enable_unrestricted_guest = 1;
58module_param_named(unrestricted_guest,
59 enable_unrestricted_guest, bool, S_IRUGO);
60
4462d21a 61static int __read_mostly emulate_invalid_guest_state = 0;
c1f8bc04 62module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 63
cdc0e244
AK		 64#define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST \
65 (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
66#define KVM_GUEST_CR0_MASK \
67 (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
68#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST \
81231c69 69 (X86_CR0_WP | X86_CR0_NE)
cdc0e244
AK		 70#define KVM_VM_CR0_ALWAYS_ON \
71 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 72#define KVM_CR4_GUEST_OWNED_BITS \
73 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
74 | X86_CR4_OSXMMEXCPT)
75
cdc0e244
AK		 76#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
77#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
78
4b8d54f9
ZE		 79/*
80 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
81 * ple_gap: upper bound on the amount of time between two successive
82 * executions of PAUSE in a loop. Also indicate if ple enabled.
83 * According to test, this time is usually small than 41 cycles.
84 * ple_window: upper bound on the amount of time a guest is allowed to execute
85 * in a PAUSE loop. Tests indicate that most spinlocks are held for
86 * less than 2^12 cycles
87 * Time is measured based on a counter that runs at the same rate as the TSC,
88 * refer SDM volume 3b section 21.6.13 & 22.1.3.
89 */
90#define KVM_VMX_DEFAULT_PLE_GAP 41
91#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
92static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
93module_param(ple_gap, int, S_IRUGO);
94
95static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
96module_param(ple_window, int, S_IRUGO);
97
a2fa3e9f
GH		 98struct vmcs {
99 u32 revision_id;
100 u32 abort;
101 char data[0];
102};
103
26bb0981
AK		 104struct shared_msr_entry {
105 unsigned index;
106 u64 data;
d5696725 107 u64 mask;
26bb0981
AK		 108};
109
a2fa3e9f 110struct vcpu_vmx {
fb3f0f51 111 struct kvm_vcpu vcpu;
543e4243 112 struct list_head local_vcpus_link;
313dbd49 113 unsigned long host_rsp;
a2fa3e9f 114 int launched;
29bd8a78 115 u8 fail;
1155f76a 116 u32 idt_vectoring_info;
26bb0981 117 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH		 118 int nmsrs;
119 int save_nmsrs;
a2fa3e9f 120#ifdef CONFIG_X86_64
44ea2b17
AK		 121 u64 msr_host_kernel_gs_base;
122 u64 msr_guest_kernel_gs_base;
a2fa3e9f
GH		 123#endif
124 struct vmcs *vmcs;
125 struct {
126 int loaded;
127 u16 fs_sel, gs_sel, ldt_sel;
152d3f2f
LV		 128 int gs_ldt_reload_needed;
129 int fs_reload_needed;
d77c26fc 130 } host_state;
9c8cba37 131 struct {
7ffd92c5
AK		 132 int vm86_active;
133 u8 save_iopl;
134 struct kvm_save_segment {
135 u16 selector;
136 unsigned long base;
137 u32 limit;
138 u32 ar;
139 } tr, es, ds, fs, gs;
9c8cba37
AK		 140 struct {
141 bool pending;
142 u8 vector;
143 unsigned rip;
144 } irq;
145 } rmode;
2384d2b3 146 int vpid;
04fa4d32 147 bool emulation_required;
3b86cd99
JK		 148
149 /* Support for vnmi-less CPUs */
150 int soft_vnmi_blocked;
151 ktime_t entry_time;
152 s64 vnmi_blocked_time;
a0861c02 153 u32 exit_reason;
4e47c7a6
SY		 154
155 bool rdtscp_enabled;
a2fa3e9f
GH		 156};
157
158static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
159{
fb3f0f51 160 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 161}
162
b7ebfb05 163static int init_rmode(struct kvm *kvm);
4e1096d2 164static u64 construct_eptp(unsigned long root_hpa);
75880a01 165
6aa8b732
AK		 166static DEFINE_PER_CPU(struct vmcs *, vmxarea);
167static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
543e4243 168static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu);
6aa8b732 169
3e7c73e9
AK		 170static unsigned long *vmx_io_bitmap_a;
171static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 172static unsigned long *vmx_msr_bitmap_legacy;
173static unsigned long *vmx_msr_bitmap_longmode;
fdef3ad1 174
2384d2b3
SY		 175static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
176static DEFINE_SPINLOCK(vmx_vpid_lock);
177
1c3d14fe 178static struct vmcs_config {
6aa8b732
AK		 179 int size;
180 int order;
181 u32 revision_id;
1c3d14fe
YS		 182 u32 pin_based_exec_ctrl;
183 u32 cpu_based_exec_ctrl;
f78e0e2e 184 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 185 u32 vmexit_ctrl;
186 u32 vmentry_ctrl;
187} vmcs_config;
6aa8b732 188
efff9e53 189static struct vmx_capability {
d56f546d
SY		 190 u32 ept;
191 u32 vpid;
192} vmx_capability;
193
6aa8b732
AK		 194#define VMX_SEGMENT_FIELD(seg) \
195 [VCPU_SREG_##seg] = { \
196 .selector = GUEST_##seg##_SELECTOR, \
197 .base = GUEST_##seg##_BASE, \
198 .limit = GUEST_##seg##_LIMIT, \
199 .ar_bytes = GUEST_##seg##_AR_BYTES, \
200 }
201
202static struct kvm_vmx_segment_field {
203 unsigned selector;
204 unsigned base;
205 unsigned limit;
206 unsigned ar_bytes;
207} kvm_vmx_segment_fields[] = {
208 VMX_SEGMENT_FIELD(CS),
209 VMX_SEGMENT_FIELD(DS),
210 VMX_SEGMENT_FIELD(ES),
211 VMX_SEGMENT_FIELD(FS),
212 VMX_SEGMENT_FIELD(GS),
213 VMX_SEGMENT_FIELD(SS),
214 VMX_SEGMENT_FIELD(TR),
215 VMX_SEGMENT_FIELD(LDTR),
216};
217
26bb0981
AK		 218static u64 host_efer;
219
6de4f3ad
AK		 220static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
221
4d56c8a7
AK		 222/*
223 * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
224 * away by decrementing the array size.
225 */
6aa8b732 226static const u32 vmx_msr_index[] = {
05b3e0c2 227#ifdef CONFIG_X86_64
44ea2b17 228 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 229#endif
4e47c7a6 230 MSR_EFER, MSR_TSC_AUX, MSR_K6_STAR,
6aa8b732 231};
9d8f549d 232#define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
6aa8b732 233
6aa8b732
AK		 234static inline int is_page_fault(u32 intr_info)
235{
236 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
237 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 238 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 239}
240
2ab455cc
AL		 241static inline int is_no_device(u32 intr_info)
242{
243 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
244 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 245 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 246}
247
7aa81cc0
AL		 248static inline int is_invalid_opcode(u32 intr_info)
249{
250 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
251 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 252 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 253}
254
6aa8b732
AK		 255static inline int is_external_interrupt(u32 intr_info)
256{
257 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
258 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
259}
260
a0861c02
AK		 261static inline int is_machine_check(u32 intr_info)
262{
263 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
264 INTR_INFO_VALID_MASK)) ==
265 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
266}
267
25c5f225
SY		 268static inline int cpu_has_vmx_msr_bitmap(void)
269{
04547156 270 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 271}
272
6e5d865c
YS		 273static inline int cpu_has_vmx_tpr_shadow(void)
274{
04547156 275 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 276}
277
278static inline int vm_need_tpr_shadow(struct kvm *kvm)
279{
04547156 280 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
6e5d865c
YS		 281}
282
f78e0e2e
SY		 283static inline int cpu_has_secondary_exec_ctrls(void)
284{
04547156
SY		 285 return vmcs_config.cpu_based_exec_ctrl &
286 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 287}
288
774ead3a 289static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 290{
04547156
SY		 291 return vmcs_config.cpu_based_2nd_exec_ctrl &
292 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
293}
294
295static inline bool cpu_has_vmx_flexpriority(void)
296{
297 return cpu_has_vmx_tpr_shadow() &&
298 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 299}
300
e799794e
MT		 301static inline bool cpu_has_vmx_ept_execute_only(void)
302{
303 return !!(vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT);
304}
305
306static inline bool cpu_has_vmx_eptp_uncacheable(void)
307{
308 return !!(vmx_capability.ept & VMX_EPTP_UC_BIT);
309}
310
311static inline bool cpu_has_vmx_eptp_writeback(void)
312{
313 return !!(vmx_capability.ept & VMX_EPTP_WB_BIT);
314}
315
316static inline bool cpu_has_vmx_ept_2m_page(void)
317{
318 return !!(vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT);
319}
320
878403b7
SY		 321static inline bool cpu_has_vmx_ept_1g_page(void)
322{
323 return !!(vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT);
324}
325
d56f546d
SY		 326static inline int cpu_has_vmx_invept_individual_addr(void)
327{
04547156 328 return !!(vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT);
d56f546d
SY		 329}
330
331static inline int cpu_has_vmx_invept_context(void)
332{
04547156 333 return !!(vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT);
d56f546d
SY		 334}
335
336static inline int cpu_has_vmx_invept_global(void)
337{
04547156 338 return !!(vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT);
d56f546d
SY		 339}
340
341static inline int cpu_has_vmx_ept(void)
342{
04547156
SY		 343 return vmcs_config.cpu_based_2nd_exec_ctrl &
344 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 345}
346
3a624e29
NK		 347static inline int cpu_has_vmx_unrestricted_guest(void)
348{
349 return vmcs_config.cpu_based_2nd_exec_ctrl &
350 SECONDARY_EXEC_UNRESTRICTED_GUEST;
351}
352
4b8d54f9
ZE		 353static inline int cpu_has_vmx_ple(void)
354{
355 return vmcs_config.cpu_based_2nd_exec_ctrl &
356 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
357}
358
f78e0e2e
SY		 359static inline int vm_need_virtualize_apic_accesses(struct kvm *kvm)
360{
04547156
SY		 361 return flexpriority_enabled &&
362 (cpu_has_vmx_virtualize_apic_accesses()) &&
363 (irqchip_in_kernel(kvm));
f78e0e2e
SY		 364}
365
2384d2b3
SY		 366static inline int cpu_has_vmx_vpid(void)
367{
04547156
SY		 368 return vmcs_config.cpu_based_2nd_exec_ctrl &
369 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 370}
371
4e47c7a6
SY		 372static inline int cpu_has_vmx_rdtscp(void)
373{
374 return vmcs_config.cpu_based_2nd_exec_ctrl &
375 SECONDARY_EXEC_RDTSCP;
376}
377
f08864b4
SY		 378static inline int cpu_has_virtual_nmis(void)
379{
380 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
381}
382
04547156
SY		 383static inline bool report_flexpriority(void)
384{
385 return flexpriority_enabled;
386}
387
8b9cf98c 388static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 389{
390 int i;
391
a2fa3e9f 392 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 393 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 394 return i;
395 return -1;
396}
397
2384d2b3
SY		 398static inline void __invvpid(int ext, u16 vpid, gva_t gva)
399{
400 struct {
401 u64 vpid : 16;
402 u64 rsvd : 48;
403 u64 gva;
404 } operand = { vpid, 0, gva };
405
4ecac3fd 406 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 407 /* CF==1 or ZF==1 --> rc = -1 */
408 "; ja 1f ; ud2 ; 1:"
409 : : "a"(&operand), "c"(ext) : "cc", "memory");
410}
411
1439442c
SY		 412static inline void __invept(int ext, u64 eptp, gpa_t gpa)
413{
414 struct {
415 u64 eptp, gpa;
416 } operand = {eptp, gpa};
417
4ecac3fd 418 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 419 /* CF==1 or ZF==1 --> rc = -1 */
420 "; ja 1f ; ud2 ; 1:\n"
421 : : "a" (&operand), "c" (ext) : "cc", "memory");
422}
423
26bb0981 424static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 425{
426 int i;
427
8b9cf98c 428 i = __find_msr_index(vmx, msr);
a75beee6 429 if (i >= 0)
a2fa3e9f 430 return &vmx->guest_msrs[i];
8b6d44c7 431 return NULL;
7725f0ba
AK		 432}
433
6aa8b732
AK		 434static void vmcs_clear(struct vmcs *vmcs)
435{
436 u64 phys_addr = __pa(vmcs);
437 u8 error;
438
4ecac3fd 439 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
6aa8b732
AK		 440 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
441 : "cc", "memory");
442 if (error)
443 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
444 vmcs, phys_addr);
445}
446
447static void __vcpu_clear(void *arg)
448{
8b9cf98c 449 struct vcpu_vmx *vmx = arg;
d3b2c338 450 int cpu = raw_smp_processor_id();
6aa8b732 451
8b9cf98c 452 if (vmx->vcpu.cpu == cpu)
a2fa3e9f
GH		 453 vmcs_clear(vmx->vmcs);
454 if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
6aa8b732 455 per_cpu(current_vmcs, cpu) = NULL;
ad312c7c 456 rdtscll(vmx->vcpu.arch.host_tsc);
543e4243
AK		 457 list_del(&vmx->local_vcpus_link);
458 vmx->vcpu.cpu = -1;
459 vmx->launched = 0;
6aa8b732
AK		 460}
461
8b9cf98c 462static void vcpu_clear(struct vcpu_vmx *vmx)
8d0be2b3 463{
eae5ecb5
AK		 464 if (vmx->vcpu.cpu == -1)
465 return;
8691e5a8 466 smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1);
8d0be2b3
AK		 467}
468
2384d2b3
SY		 469static inline void vpid_sync_vcpu_all(struct vcpu_vmx *vmx)
470{
471 if (vmx->vpid == 0)
472 return;
473
474 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
475}
476
1439442c
SY		 477static inline void ept_sync_global(void)
478{
479 if (cpu_has_vmx_invept_global())
480 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
481}
482
483static inline void ept_sync_context(u64 eptp)
484{
089d034e 485 if (enable_ept) {
1439442c
SY		 486 if (cpu_has_vmx_invept_context())
487 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
488 else
489 ept_sync_global();
490 }
491}
492
493static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
494{
089d034e 495 if (enable_ept) {
1439442c
SY		 496 if (cpu_has_vmx_invept_individual_addr())
497 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
498 eptp, gpa);
499 else
500 ept_sync_context(eptp);
501 }
502}
503
6aa8b732
AK		 504static unsigned long vmcs_readl(unsigned long field)
505{
506 unsigned long value;
507
4ecac3fd 508 asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX)
6aa8b732
AK		 509 : "=a"(value) : "d"(field) : "cc");
510 return value;
511}
512
513static u16 vmcs_read16(unsigned long field)
514{
515 return vmcs_readl(field);
516}
517
518static u32 vmcs_read32(unsigned long field)
519{
520 return vmcs_readl(field);
521}
522
523static u64 vmcs_read64(unsigned long field)
524{
05b3e0c2 525#ifdef CONFIG_X86_64
6aa8b732
AK		 526 return vmcs_readl(field);
527#else
528 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
529#endif
530}
531
e52de1b8
AK		 532static noinline void vmwrite_error(unsigned long field, unsigned long value)
533{
534 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
535 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
536 dump_stack();
537}
538
6aa8b732
AK		 539static void vmcs_writel(unsigned long field, unsigned long value)
540{
541 u8 error;
542
4ecac3fd 543 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 544 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 545 if (unlikely(error))
546 vmwrite_error(field, value);
6aa8b732
AK		 547}
548
549static void vmcs_write16(unsigned long field, u16 value)
550{
551 vmcs_writel(field, value);
552}
553
554static void vmcs_write32(unsigned long field, u32 value)
555{
556 vmcs_writel(field, value);
557}
558
559static void vmcs_write64(unsigned long field, u64 value)
560{
6aa8b732 561 vmcs_writel(field, value);
7682f2d0 562#ifndef CONFIG_X86_64
6aa8b732
AK		 563 asm volatile ("");
564 vmcs_writel(field+1, value >> 32);
565#endif
566}
567
2ab455cc
AL		 568static void vmcs_clear_bits(unsigned long field, u32 mask)
569{
570 vmcs_writel(field, vmcs_readl(field) & ~mask);
571}
572
573static void vmcs_set_bits(unsigned long field, u32 mask)
574{
575 vmcs_writel(field, vmcs_readl(field) | mask);
576}
577
abd3f2d6
AK		 578static void update_exception_bitmap(struct kvm_vcpu *vcpu)
579{
580 u32 eb;
581
fd7373cc
JK		 582 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
583 (1u << NM_VECTOR) | (1u << DB_VECTOR);
584 if ((vcpu->guest_debug &
585 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
586 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
587 eb |= 1u << BP_VECTOR;
7ffd92c5 588 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 589 eb = ~0;
089d034e 590 if (enable_ept)
1439442c 591 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
02daab21
AK		 592 if (vcpu->fpu_active)
593 eb &= ~(1u << NM_VECTOR);
abd3f2d6
AK		 594 vmcs_write32(EXCEPTION_BITMAP, eb);
595}
596
33ed6329
AK		 597static void reload_tss(void)
598{
33ed6329
AK		 599 /*
600 * VT restores TR but not its size. Useless.
601 */
602 struct descriptor_table gdt;
a5f61300 603 struct desc_struct *descs;
33ed6329 604
d6e88aec 605 kvm_get_gdt(&gdt);
33ed6329
AK		 606 descs = (void *)gdt.base;
607 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
608 load_TR_desc();
33ed6329
AK		 609}
610
92c0d900 611static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 612{
3a34a881 613 u64 guest_efer;
51c6cf66
AK		 614 u64 ignore_bits;
615
f6801dff 616 guest_efer = vmx->vcpu.arch.efer;
3a34a881 617
51c6cf66
AK		 618 /*
619 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
620 * outside long mode
621 */
622 ignore_bits = EFER_NX | EFER_SCE;
623#ifdef CONFIG_X86_64
624 ignore_bits |= EFER_LMA | EFER_LME;
625 /* SCE is meaningful only in long mode on Intel */
626 if (guest_efer & EFER_LMA)
627 ignore_bits &= ~(u64)EFER_SCE;
628#endif
51c6cf66
AK		 629 guest_efer &= ~ignore_bits;
630 guest_efer |= host_efer & ignore_bits;
26bb0981 631 vmx->guest_msrs[efer_offset].data = guest_efer;
d5696725 632 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
26bb0981 633 return true;
51c6cf66
AK		 634}
635
04d2cc77 636static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 637{
04d2cc77 638 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 639 int i;
04d2cc77 640
a2fa3e9f 641 if (vmx->host_state.loaded)
33ed6329
AK		 642 return;
643
a2fa3e9f 644 vmx->host_state.loaded = 1;
33ed6329
AK		 645 /*
646 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
647 * allow segment selectors with cpl > 0 or ti == 1.
648 */
d6e88aec 649 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 650 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
d6e88aec 651 vmx->host_state.fs_sel = kvm_read_fs();
152d3f2f 652 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 653 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 654 vmx->host_state.fs_reload_needed = 0;
655 } else {
33ed6329 656 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 657 vmx->host_state.fs_reload_needed = 1;
33ed6329 658 }
d6e88aec 659 vmx->host_state.gs_sel = kvm_read_gs();
a2fa3e9f
GH		 660 if (!(vmx->host_state.gs_sel & 7))
661 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 662 else {
663 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 664 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 665 }
666
667#ifdef CONFIG_X86_64
668 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
669 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
670#else
a2fa3e9f
GH		 671 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
672 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 673#endif
707c0874
AK		 674
675#ifdef CONFIG_X86_64
44ea2b17
AK		 676 if (is_long_mode(&vmx->vcpu)) {
677 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
678 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
679 }
707c0874 680#endif
26bb0981
AK		 681 for (i = 0; i < vmx->save_nmsrs; ++i)
682 kvm_set_shared_msr(vmx->guest_msrs[i].index,
d5696725
AK		 683 vmx->guest_msrs[i].data,
684 vmx->guest_msrs[i].mask);
33ed6329
AK		 685}
686
a9b21b62 687static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 688{
15ad7146 689 unsigned long flags;
33ed6329 690
a2fa3e9f 691 if (!vmx->host_state.loaded)
33ed6329
AK		 692 return;
693
e1beb1d3 694 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 695 vmx->host_state.loaded = 0;
152d3f2f 696 if (vmx->host_state.fs_reload_needed)
d6e88aec 697 kvm_load_fs(vmx->host_state.fs_sel);
152d3f2f 698 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 699 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329
AK		 700 /*
701 * If we have to reload gs, we must take care to
702 * preserve our gs base.
703 */
15ad7146 704 local_irq_save(flags);
d6e88aec 705 kvm_load_gs(vmx->host_state.gs_sel);
33ed6329
AK		 706#ifdef CONFIG_X86_64
707 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
708#endif
15ad7146 709 local_irq_restore(flags);
33ed6329 710 }
152d3f2f 711 reload_tss();
44ea2b17
AK		 712#ifdef CONFIG_X86_64
713 if (is_long_mode(&vmx->vcpu)) {
714 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
715 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
716 }
717#endif
33ed6329
AK		 718}
719
a9b21b62
AK		 720static void vmx_load_host_state(struct vcpu_vmx *vmx)
721{
722 preempt_disable();
723 __vmx_load_host_state(vmx);
724 preempt_enable();
725}
726
6aa8b732
AK		 727/*
728 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
729 * vcpu mutex is already taken.
730 */
15ad7146 731static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 732{
a2fa3e9f
GH		 733 struct vcpu_vmx *vmx = to_vmx(vcpu);
734 u64 phys_addr = __pa(vmx->vmcs);
019960ae 735 u64 tsc_this, delta, new_offset;
6aa8b732 736
a3d7f85f 737 if (vcpu->cpu != cpu) {
8b9cf98c 738 vcpu_clear(vmx);
2f599714 739 kvm_migrate_timers(vcpu);
eb5109e3 740 set_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests);
543e4243
AK		 741 local_irq_disable();
742 list_add(&vmx->local_vcpus_link,
743 &per_cpu(vcpus_on_cpu, cpu));
744 local_irq_enable();
a3d7f85f 745 }
6aa8b732 746
a2fa3e9f 747 if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
6aa8b732
AK		 748 u8 error;
749
a2fa3e9f 750 per_cpu(current_vmcs, cpu) = vmx->vmcs;
4ecac3fd 751 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
6aa8b732
AK		 752 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
753 : "cc");
754 if (error)
755 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
a2fa3e9f 756 vmx->vmcs, phys_addr);
6aa8b732
AK		 757 }
758
759 if (vcpu->cpu != cpu) {
760 struct descriptor_table dt;
761 unsigned long sysenter_esp;
762
763 vcpu->cpu = cpu;
764 /*
765 * Linux uses per-cpu TSS and GDT, so set these when switching
766 * processors.
767 */
d6e88aec
AK		 768 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
769 kvm_get_gdt(&dt);
6aa8b732
AK		 770 vmcs_writel(HOST_GDTR_BASE, dt.base); /* 22.2.4 */
771
772 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
773 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
7700270e
AK		 774
775 /*
776 * Make sure the time stamp counter is monotonous.
777 */
778 rdtscll(tsc_this);
019960ae
AK		 779 if (tsc_this < vcpu->arch.host_tsc) {
780 delta = vcpu->arch.host_tsc - tsc_this;
781 new_offset = vmcs_read64(TSC_OFFSET) + delta;
782 vmcs_write64(TSC_OFFSET, new_offset);
783 }
6aa8b732 784 }
6aa8b732
AK		 785}
786
787static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
788{
a9b21b62 789 __vmx_load_host_state(to_vmx(vcpu));
6aa8b732
AK		 790}
791
5fd86fcf
AK		 792static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
793{
81231c69
AK		 794 ulong cr0;
795
5fd86fcf
AK		 796 if (vcpu->fpu_active)
797 return;
798 vcpu->fpu_active = 1;
81231c69
AK		 799 cr0 = vmcs_readl(GUEST_CR0);
800 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
801 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
802 vmcs_writel(GUEST_CR0, cr0);
5fd86fcf 803 update_exception_bitmap(vcpu);
edcafe3c
AK		 804 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
805 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
5fd86fcf
AK		 806}
807
edcafe3c
AK		 808static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
809
5fd86fcf
AK		 810static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
811{
edcafe3c 812 vmx_decache_cr0_guest_bits(vcpu);
81231c69 813 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
5fd86fcf 814 update_exception_bitmap(vcpu);
edcafe3c
AK		 815 vcpu->arch.cr0_guest_owned_bits = 0;
816 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
817 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf
AK		 818}
819
6aa8b732
AK		 820static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
821{
345dcaa8
AK		 822 unsigned long rflags;
823
824 rflags = vmcs_readl(GUEST_RFLAGS);
825 if (to_vmx(vcpu)->rmode.vm86_active)
826 rflags &= ~(unsigned long)(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
827 return rflags;
6aa8b732
AK		 828}
829
830static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
831{
7ffd92c5 832 if (to_vmx(vcpu)->rmode.vm86_active)
053de044 833 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 834 vmcs_writel(GUEST_RFLAGS, rflags);
835}
836
2809f5d2
GC		 837static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
838{
839 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
840 int ret = 0;
841
842 if (interruptibility & GUEST_INTR_STATE_STI)
843 ret |= X86_SHADOW_INT_STI;
844 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
845 ret |= X86_SHADOW_INT_MOV_SS;
846
847 return ret & mask;
848}
849
850static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
851{
852 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
853 u32 interruptibility = interruptibility_old;
854
855 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
856
857 if (mask & X86_SHADOW_INT_MOV_SS)
858 interruptibility |= GUEST_INTR_STATE_MOV_SS;
859 if (mask & X86_SHADOW_INT_STI)
860 interruptibility |= GUEST_INTR_STATE_STI;
861
862 if ((interruptibility != interruptibility_old))
863 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
864}
865
6aa8b732
AK		 866static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
867{
868 unsigned long rip;
6aa8b732 869
5fdbf976 870 rip = kvm_rip_read(vcpu);
6aa8b732 871 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 872 kvm_rip_write(vcpu, rip);
6aa8b732 873
2809f5d2
GC		 874 /* skipping an emulated instruction also counts */
875 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 876}
877
298101da
AK		 878static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
879 bool has_error_code, u32 error_code)
880{
77ab6db0 881 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 882 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 883
8ab2d2e2 884 if (has_error_code) {
77ab6db0 885 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 886 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
887 }
77ab6db0 888
7ffd92c5 889 if (vmx->rmode.vm86_active) {
77ab6db0
JK		 890 vmx->rmode.irq.pending = true;
891 vmx->rmode.irq.vector = nr;
892 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
ae0bb3e0
GN		 893 if (kvm_exception_is_soft(nr))
894 vmx->rmode.irq.rip +=
895 vmx->vcpu.arch.event_exit_inst_len;
8ab2d2e2
JK		 896 intr_info |= INTR_TYPE_SOFT_INTR;
897 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
77ab6db0
JK		 898 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
899 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
900 return;
901 }
902
66fd3f7f
GN		 903 if (kvm_exception_is_soft(nr)) {
904 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
905 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 906 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
907 } else
908 intr_info |= INTR_TYPE_HARD_EXCEPTION;
909
910 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
298101da
AK		 911}
912
4e47c7a6
SY		 913static bool vmx_rdtscp_supported(void)
914{
915 return cpu_has_vmx_rdtscp();
916}
917
a75beee6
ED		 918/*
919 * Swap MSR entry in host/guest MSR entry array.
920 */
8b9cf98c 921static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 922{
26bb0981 923 struct shared_msr_entry tmp;
a2fa3e9f
GH		 924
925 tmp = vmx->guest_msrs[to];
926 vmx->guest_msrs[to] = vmx->guest_msrs[from];
927 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 928}
929
e38aea3e
AK		 930/*
931 * Set up the vmcs to automatically save and restore system
932 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
933 * mode, as fiddling with msrs is very expensive.
934 */
8b9cf98c 935static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 936{
26bb0981 937 int save_nmsrs, index;
5897297b 938 unsigned long *msr_bitmap;
e38aea3e 939
33f9c505 940 vmx_load_host_state(vmx);
a75beee6
ED		 941 save_nmsrs = 0;
942#ifdef CONFIG_X86_64
8b9cf98c 943 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 944 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 945 if (index >= 0)
8b9cf98c
RR		 946 move_msr_up(vmx, index, save_nmsrs++);
947 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 948 if (index >= 0)
8b9cf98c
RR		 949 move_msr_up(vmx, index, save_nmsrs++);
950 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 951 if (index >= 0)
8b9cf98c 952 move_msr_up(vmx, index, save_nmsrs++);
4e47c7a6
SY		 953 index = __find_msr_index(vmx, MSR_TSC_AUX);
954 if (index >= 0 && vmx->rdtscp_enabled)
955 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 956 /*
957 * MSR_K6_STAR is only needed on long mode guests, and only
958 * if efer.sce is enabled.
959 */
8b9cf98c 960 index = __find_msr_index(vmx, MSR_K6_STAR);
f6801dff 961 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
8b9cf98c 962 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 963 }
964#endif
92c0d900
AK		 965 index = __find_msr_index(vmx, MSR_EFER);
966 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 967 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 968
26bb0981 969 vmx->save_nmsrs = save_nmsrs;
5897297b
AK		 970
971 if (cpu_has_vmx_msr_bitmap()) {
972 if (is_long_mode(&vmx->vcpu))
973 msr_bitmap = vmx_msr_bitmap_longmode;
974 else
975 msr_bitmap = vmx_msr_bitmap_legacy;
976
977 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
978 }
e38aea3e
AK		 979}
980
6aa8b732
AK		 981/*
982 * reads and returns guest's timestamp counter "register"
983 * guest_tsc = host_tsc + tsc_offset -- 21.3
984 */
985static u64 guest_read_tsc(void)
986{
987 u64 host_tsc, tsc_offset;
988
989 rdtscll(host_tsc);
990 tsc_offset = vmcs_read64(TSC_OFFSET);
991 return host_tsc + tsc_offset;
992}
993
994/*
995 * writes 'guest_tsc' into guest's timestamp counter "register"
996 * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
997 */
53f658b3 998static void guest_write_tsc(u64 guest_tsc, u64 host_tsc)
6aa8b732 999{
6aa8b732
AK		 1000 vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
1001}
1002
6aa8b732
AK		 1003/*
1004 * Reads an msr value (of 'msr_index') into 'pdata'.
1005 * Returns 0 on success, non-0 otherwise.
1006 * Assumes vcpu_load() was already called.
1007 */
1008static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1009{
1010 u64 data;
26bb0981 1011 struct shared_msr_entry *msr;
6aa8b732
AK		 1012
1013 if (!pdata) {
1014 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
1015 return -EINVAL;
1016 }
1017
1018 switch (msr_index) {
05b3e0c2 1019#ifdef CONFIG_X86_64
6aa8b732
AK		 1020 case MSR_FS_BASE:
1021 data = vmcs_readl(GUEST_FS_BASE);
1022 break;
1023 case MSR_GS_BASE:
1024 data = vmcs_readl(GUEST_GS_BASE);
1025 break;
44ea2b17
AK		 1026 case MSR_KERNEL_GS_BASE:
1027 vmx_load_host_state(to_vmx(vcpu));
1028 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
1029 break;
26bb0981 1030#endif
6aa8b732 1031 case MSR_EFER:
3bab1f5d 1032 return kvm_get_msr_common(vcpu, msr_index, pdata);
af24a4e4 1033 case MSR_IA32_TSC:
6aa8b732
AK		 1034 data = guest_read_tsc();
1035 break;
1036 case MSR_IA32_SYSENTER_CS:
1037 data = vmcs_read32(GUEST_SYSENTER_CS);
1038 break;
1039 case MSR_IA32_SYSENTER_EIP:
f5b42c33 1040 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 1041 break;
1042 case MSR_IA32_SYSENTER_ESP:
f5b42c33 1043 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 1044 break;
4e47c7a6
SY		 1045 case MSR_TSC_AUX:
1046 if (!to_vmx(vcpu)->rdtscp_enabled)
1047 return 1;
1048 /* Otherwise falls through */
6aa8b732 1049 default:
26bb0981 1050 vmx_load_host_state(to_vmx(vcpu));
8b9cf98c 1051 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d 1052 if (msr) {
542423b0 1053 vmx_load_host_state(to_vmx(vcpu));
3bab1f5d
AK		 1054 data = msr->data;
1055 break;
6aa8b732 1056 }
3bab1f5d 1057 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 1058 }
1059
1060 *pdata = data;
1061 return 0;
1062}
1063
1064/*
1065 * Writes msr value into into the appropriate "register".
1066 * Returns 0 on success, non-0 otherwise.
1067 * Assumes vcpu_load() was already called.
1068 */
1069static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
1070{
a2fa3e9f 1071 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1072 struct shared_msr_entry *msr;
53f658b3 1073 u64 host_tsc;
2cc51560
ED		 1074 int ret = 0;
1075
6aa8b732 1076 switch (msr_index) {
3bab1f5d 1077 case MSR_EFER:
a9b21b62 1078 vmx_load_host_state(vmx);
2cc51560 1079 ret = kvm_set_msr_common(vcpu, msr_index, data);
2cc51560 1080 break;
16175a79 1081#ifdef CONFIG_X86_64
6aa8b732
AK		 1082 case MSR_FS_BASE:
1083 vmcs_writel(GUEST_FS_BASE, data);
1084 break;
1085 case MSR_GS_BASE:
1086 vmcs_writel(GUEST_GS_BASE, data);
1087 break;
44ea2b17
AK		 1088 case MSR_KERNEL_GS_BASE:
1089 vmx_load_host_state(vmx);
1090 vmx->msr_guest_kernel_gs_base = data;
1091 break;
6aa8b732
AK		 1092#endif
1093 case MSR_IA32_SYSENTER_CS:
1094 vmcs_write32(GUEST_SYSENTER_CS, data);
1095 break;
1096 case MSR_IA32_SYSENTER_EIP:
f5b42c33 1097 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 1098 break;
1099 case MSR_IA32_SYSENTER_ESP:
f5b42c33 1100 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 1101 break;
af24a4e4 1102 case MSR_IA32_TSC:
53f658b3
MT		 1103 rdtscll(host_tsc);
1104 guest_write_tsc(data, host_tsc);
6aa8b732 1105 break;
468d472f
SY		 1106 case MSR_IA32_CR_PAT:
1107 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
1108 vmcs_write64(GUEST_IA32_PAT, data);
1109 vcpu->arch.pat = data;
1110 break;
1111 }
4e47c7a6
SY		 1112 ret = kvm_set_msr_common(vcpu, msr_index, data);
1113 break;
1114 case MSR_TSC_AUX:
1115 if (!vmx->rdtscp_enabled)
1116 return 1;
1117 /* Check reserved bit, higher 32 bits should be zero */
1118 if ((data >> 32) != 0)
1119 return 1;
1120 /* Otherwise falls through */
6aa8b732 1121 default:
8b9cf98c 1122 msr = find_msr_entry(vmx, msr_index);
3bab1f5d 1123 if (msr) {
542423b0 1124 vmx_load_host_state(vmx);
3bab1f5d
AK		 1125 msr->data = data;
1126 break;
6aa8b732 1127 }
2cc51560 1128 ret = kvm_set_msr_common(vcpu, msr_index, data);
6aa8b732
AK		 1129 }
1130
2cc51560 1131 return ret;
6aa8b732
AK		 1132}
1133
5fdbf976 1134static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 1135{
5fdbf976
MT		 1136 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
1137 switch (reg) {
1138 case VCPU_REGS_RSP:
1139 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
1140 break;
1141 case VCPU_REGS_RIP:
1142 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
1143 break;
6de4f3ad
AK		 1144 case VCPU_EXREG_PDPTR:
1145 if (enable_ept)
1146 ept_save_pdptrs(vcpu);
1147 break;
5fdbf976
MT		 1148 default:
1149 break;
1150 }
6aa8b732
AK		 1151}
1152
355be0b9 1153static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
6aa8b732 1154{
ae675ef0
JK		 1155 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1156 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
1157 else
1158 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
1159
abd3f2d6 1160 update_exception_bitmap(vcpu);
6aa8b732
AK		 1161}
1162
1163static __init int cpu_has_kvm_support(void)
1164{
6210e37b 1165 return cpu_has_vmx();
6aa8b732
AK		 1166}
1167
1168static __init int vmx_disabled_by_bios(void)
1169{
1170 u64 msr;
1171
1172 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
9ea542fa
SY		 1173 return (msr & (FEATURE_CONTROL_LOCKED |
1174 FEATURE_CONTROL_VMXON_ENABLED))
1175 == FEATURE_CONTROL_LOCKED;
62b3ffb8 1176 /* locked but not enabled */
6aa8b732
AK		 1177}
1178
10474ae8 1179static int hardware_enable(void *garbage)
6aa8b732
AK		 1180{
1181 int cpu = raw_smp_processor_id();
1182 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1183 u64 old;
1184
10474ae8
AG		 1185 if (read_cr4() & X86_CR4_VMXE)
1186 return -EBUSY;
1187
543e4243 1188 INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu));
6aa8b732 1189 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
9ea542fa
SY		 1190 if ((old & (FEATURE_CONTROL_LOCKED |
1191 FEATURE_CONTROL_VMXON_ENABLED))
1192 != (FEATURE_CONTROL_LOCKED |
1193 FEATURE_CONTROL_VMXON_ENABLED))
6aa8b732 1194 /* enable and lock */
62b3ffb8 1195 wrmsrl(MSR_IA32_FEATURE_CONTROL, old |
9ea542fa
SY		 1196 FEATURE_CONTROL_LOCKED |
1197 FEATURE_CONTROL_VMXON_ENABLED);
66aee91a 1198 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
4ecac3fd
AK		 1199 asm volatile (ASM_VMX_VMXON_RAX
1200 : : "a"(&phys_addr), "m"(phys_addr)
6aa8b732 1201 : "memory", "cc");
10474ae8
AG		 1202
1203 ept_sync_global();
1204
1205 return 0;
6aa8b732
AK		 1206}
1207
543e4243
AK		 1208static void vmclear_local_vcpus(void)
1209{
1210 int cpu = raw_smp_processor_id();
1211 struct vcpu_vmx *vmx, *n;
1212
1213 list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu),
1214 local_vcpus_link)
1215 __vcpu_clear(vmx);
1216}
1217
710ff4a8
EH		 1218
1219/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
1220 * tricks.
1221 */
1222static void kvm_cpu_vmxoff(void)
6aa8b732 1223{
4ecac3fd 1224 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
e693d71b 1225 write_cr4(read_cr4() & ~X86_CR4_VMXE);
6aa8b732
AK		 1226}
1227
710ff4a8
EH		 1228static void hardware_disable(void *garbage)
1229{
1230 vmclear_local_vcpus();
1231 kvm_cpu_vmxoff();
1232}
1233
1c3d14fe 1234static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 1235 u32 msr, u32 *result)
1c3d14fe
YS		 1236{
1237 u32 vmx_msr_low, vmx_msr_high;
1238 u32 ctl = ctl_min | ctl_opt;
1239
1240 rdmsr(msr, vmx_msr_low, vmx_msr_high);
1241
1242 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1243 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
1244
1245 /* Ensure minimum (required) set of control bits are supported. */
1246 if (ctl_min & ~ctl)
002c7f7c 1247 return -EIO;
1c3d14fe
YS		 1248
1249 *result = ctl;
1250 return 0;
1251}
1252
002c7f7c 1253static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 1254{
1255 u32 vmx_msr_low, vmx_msr_high;
d56f546d 1256 u32 min, opt, min2, opt2;
1c3d14fe
YS		 1257 u32 _pin_based_exec_control = 0;
1258 u32 _cpu_based_exec_control = 0;
f78e0e2e 1259 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 1260 u32 _vmexit_control = 0;
1261 u32 _vmentry_control = 0;
1262
1263 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
f08864b4 1264 opt = PIN_BASED_VIRTUAL_NMIS;
1c3d14fe
YS		 1265 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1266 &_pin_based_exec_control) < 0)
002c7f7c 1267 return -EIO;
1c3d14fe
YS		 1268
1269 min = CPU_BASED_HLT_EXITING |
1270#ifdef CONFIG_X86_64
1271 CPU_BASED_CR8_LOAD_EXITING |
1272 CPU_BASED_CR8_STORE_EXITING |
1273#endif
d56f546d
SY		 1274 CPU_BASED_CR3_LOAD_EXITING |
1275 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 1276 CPU_BASED_USE_IO_BITMAPS |
1277 CPU_BASED_MOV_DR_EXITING |
a7052897 1278 CPU_BASED_USE_TSC_OFFSETING |
59708670
SY		 1279 CPU_BASED_MWAIT_EXITING |
1280 CPU_BASED_MONITOR_EXITING |
a7052897 1281 CPU_BASED_INVLPG_EXITING;
f78e0e2e 1282 opt = CPU_BASED_TPR_SHADOW |
25c5f225 1283 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 1284 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 1285 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1286 &_cpu_based_exec_control) < 0)
002c7f7c 1287 return -EIO;
6e5d865c
YS		 1288#ifdef CONFIG_X86_64
1289 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1290 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1291 ~CPU_BASED_CR8_STORE_EXITING;
1292#endif
f78e0e2e 1293 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 1294 min2 = 0;
1295 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2384d2b3 1296 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 1297 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 1298 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 1299 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6
SY		 1300 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
1301 SECONDARY_EXEC_RDTSCP;
d56f546d
SY		 1302 if (adjust_vmx_controls(min2, opt2,
1303 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 1304 &_cpu_based_2nd_exec_control) < 0)
1305 return -EIO;
1306 }
1307#ifndef CONFIG_X86_64
1308 if (!(_cpu_based_2nd_exec_control &
1309 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1310 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1311#endif
d56f546d 1312 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 1313 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
1314 enabled */
5fff7d27
GN		 1315 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
1316 CPU_BASED_CR3_STORE_EXITING |
1317 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 1318 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1319 vmx_capability.ept, vmx_capability.vpid);
1320 }
1c3d14fe
YS		 1321
1322 min = 0;
1323#ifdef CONFIG_X86_64
1324 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1325#endif
468d472f 1326 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1c3d14fe
YS		 1327 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1328 &_vmexit_control) < 0)
002c7f7c 1329 return -EIO;
1c3d14fe 1330
468d472f
SY		 1331 min = 0;
1332 opt = VM_ENTRY_LOAD_IA32_PAT;
1c3d14fe
YS		 1333 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1334 &_vmentry_control) < 0)
002c7f7c 1335 return -EIO;
6aa8b732 1336
c68876fd 1337 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 1338
1339 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1340 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 1341 return -EIO;
1c3d14fe
YS		 1342
1343#ifdef CONFIG_X86_64
1344 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1345 if (vmx_msr_high & (1u<<16))
002c7f7c 1346 return -EIO;
1c3d14fe
YS		 1347#endif
1348
1349 /* Require Write-Back (WB) memory type for VMCS accesses. */
1350 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 1351 return -EIO;
1c3d14fe 1352
002c7f7c
YS		 1353 vmcs_conf->size = vmx_msr_high & 0x1fff;
1354 vmcs_conf->order = get_order(vmcs_config.size);
1355 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 1356
002c7f7c
YS		 1357 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1358 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 1359 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 1360 vmcs_conf->vmexit_ctrl = _vmexit_control;
1361 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe
YS		 1362
1363 return 0;
c68876fd 1364}
6aa8b732
AK		 1365
1366static struct vmcs *alloc_vmcs_cpu(int cpu)
1367{
1368 int node = cpu_to_node(cpu);
1369 struct page *pages;
1370 struct vmcs *vmcs;
1371
6484eb3e 1372 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 1373 if (!pages)
1374 return NULL;
1375 vmcs = page_address(pages);
1c3d14fe
YS		 1376 memset(vmcs, 0, vmcs_config.size);
1377 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 1378 return vmcs;
1379}
1380
1381static struct vmcs *alloc_vmcs(void)
1382{
d3b2c338 1383 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 1384}
1385
1386static void free_vmcs(struct vmcs *vmcs)
1387{
1c3d14fe 1388 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 1389}
1390
39959588 1391static void free_kvm_area(void)
6aa8b732
AK		 1392{
1393 int cpu;
1394
3230bb47 1395 for_each_possible_cpu(cpu) {
6aa8b732 1396 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 1397 per_cpu(vmxarea, cpu) = NULL;
1398 }
6aa8b732
AK		 1399}
1400
6aa8b732
AK		 1401static __init int alloc_kvm_area(void)
1402{
1403 int cpu;
1404
3230bb47 1405 for_each_possible_cpu(cpu) {
6aa8b732
AK		 1406 struct vmcs *vmcs;
1407
1408 vmcs = alloc_vmcs_cpu(cpu);
1409 if (!vmcs) {
1410 free_kvm_area();
1411 return -ENOMEM;
1412 }
1413
1414 per_cpu(vmxarea, cpu) = vmcs;
1415 }
1416 return 0;
1417}
1418
1419static __init int hardware_setup(void)
1420{
002c7f7c
YS		 1421 if (setup_vmcs_config(&vmcs_config) < 0)
1422 return -EIO;
50a37eb4
JR		 1423
1424 if (boot_cpu_has(X86_FEATURE_NX))
1425 kvm_enable_efer_bits(EFER_NX);
1426
93ba03c2
SY		 1427 if (!cpu_has_vmx_vpid())
1428 enable_vpid = 0;
1429
3a624e29 1430 if (!cpu_has_vmx_ept()) {
93ba03c2 1431 enable_ept = 0;
3a624e29
NK		 1432 enable_unrestricted_guest = 0;
1433 }
1434
1435 if (!cpu_has_vmx_unrestricted_guest())
1436 enable_unrestricted_guest = 0;
93ba03c2
SY		 1437
1438 if (!cpu_has_vmx_flexpriority())
1439 flexpriority_enabled = 0;
1440
95ba8273
GN		 1441 if (!cpu_has_vmx_tpr_shadow())
1442 kvm_x86_ops->update_cr8_intercept = NULL;
1443
54dee993
MT		 1444 if (enable_ept && !cpu_has_vmx_ept_2m_page())
1445 kvm_disable_largepages();
1446
4b8d54f9
ZE		 1447 if (!cpu_has_vmx_ple())
1448 ple_gap = 0;
1449
6aa8b732
AK		 1450 return alloc_kvm_area();
1451}
1452
1453static __exit void hardware_unsetup(void)
1454{
1455 free_kvm_area();
1456}
1457
6aa8b732
AK		 1458static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1459{
1460 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1461
6af11b9e 1462 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
6aa8b732
AK		 1463 vmcs_write16(sf->selector, save->selector);
1464 vmcs_writel(sf->base, save->base);
1465 vmcs_write32(sf->limit, save->limit);
1466 vmcs_write32(sf->ar_bytes, save->ar);
1467 } else {
1468 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1469 << AR_DPL_SHIFT;
1470 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1471 }
1472}
1473
1474static void enter_pmode(struct kvm_vcpu *vcpu)
1475{
1476 unsigned long flags;
a89a8fb9 1477 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 1478
a89a8fb9 1479 vmx->emulation_required = 1;
7ffd92c5 1480 vmx->rmode.vm86_active = 0;
6aa8b732 1481
7ffd92c5
AK		 1482 vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
1483 vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
1484 vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
6aa8b732
AK		 1485
1486 flags = vmcs_readl(GUEST_RFLAGS);
053de044 1487 flags &= ~(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
7ffd92c5 1488 flags |= (vmx->rmode.save_iopl << IOPL_SHIFT);
6aa8b732
AK		 1489 vmcs_writel(GUEST_RFLAGS, flags);
1490
66aee91a
RR		 1491 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1492 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 1493
1494 update_exception_bitmap(vcpu);
1495
a89a8fb9
MG		 1496 if (emulate_invalid_guest_state)
1497 return;
1498
7ffd92c5
AK		 1499 fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
1500 fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
1501 fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
1502 fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
6aa8b732
AK		 1503
1504 vmcs_write16(GUEST_SS_SELECTOR, 0);
1505 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1506
1507 vmcs_write16(GUEST_CS_SELECTOR,
1508 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1509 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1510}
1511
d77c26fc 1512static gva_t rmode_tss_base(struct kvm *kvm)
6aa8b732 1513{
bfc6d222 1514 if (!kvm->arch.tss_addr) {
bc6678a3
MT		 1515 struct kvm_memslots *slots;
1516 gfn_t base_gfn;
1517
1518 slots = rcu_dereference(kvm->memslots);
1519 base_gfn = kvm->memslots->memslots[0].base_gfn +
46a26bf5 1520 kvm->memslots->memslots[0].npages - 3;
cbc94022
IE		 1521 return base_gfn << PAGE_SHIFT;
1522 }
bfc6d222 1523 return kvm->arch.tss_addr;
6aa8b732
AK		 1524}
1525
1526static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1527{
1528 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1529
1530 save->selector = vmcs_read16(sf->selector);
1531 save->base = vmcs_readl(sf->base);
1532 save->limit = vmcs_read32(sf->limit);
1533 save->ar = vmcs_read32(sf->ar_bytes);
15b00f32
JK		 1534 vmcs_write16(sf->selector, save->base >> 4);
1535 vmcs_write32(sf->base, save->base & 0xfffff);
6aa8b732
AK		 1536 vmcs_write32(sf->limit, 0xffff);
1537 vmcs_write32(sf->ar_bytes, 0xf3);
1538}
1539
1540static void enter_rmode(struct kvm_vcpu *vcpu)
1541{
1542 unsigned long flags;
a89a8fb9 1543 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 1544
3a624e29
NK		 1545 if (enable_unrestricted_guest)
1546 return;
1547
a89a8fb9 1548 vmx->emulation_required = 1;
7ffd92c5 1549 vmx->rmode.vm86_active = 1;
6aa8b732 1550
7ffd92c5 1551 vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
6aa8b732
AK		 1552 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1553
7ffd92c5 1554 vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
6aa8b732
AK		 1555 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1556
7ffd92c5 1557 vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
6aa8b732
AK		 1558 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1559
1560 flags = vmcs_readl(GUEST_RFLAGS);
7ffd92c5 1561 vmx->rmode.save_iopl
ad312c7c 1562 = (flags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
6aa8b732 1563
053de044 1564 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 1565
1566 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 1567 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 1568 update_exception_bitmap(vcpu);
1569
a89a8fb9
MG		 1570 if (emulate_invalid_guest_state)
1571 goto continue_rmode;
1572
6aa8b732
AK		 1573 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1574 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1575 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1576
1577 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
abacf8df 1578 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
8cb5b033
AK		 1579 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1580 vmcs_writel(GUEST_CS_BASE, 0xf0000);
6aa8b732
AK		 1581 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1582
7ffd92c5
AK		 1583 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
1584 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
1585 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
1586 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
75880a01 1587
a89a8fb9 1588continue_rmode:
8668a3c4 1589 kvm_mmu_reset_context(vcpu);
b7ebfb05 1590 init_rmode(vcpu->kvm);
6aa8b732
AK		 1591}
1592
401d10de
AS		 1593static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1594{
1595 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 1596 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1597
1598 if (!msr)
1599 return;
401d10de 1600
44ea2b17
AK		 1601 /*
1602 * Force kernel_gs_base reloading before EFER changes, as control
1603 * of this msr depends on is_long_mode().
1604 */
1605 vmx_load_host_state(to_vmx(vcpu));
f6801dff 1606 vcpu->arch.efer = efer;
401d10de
AS		 1607 if (!msr)
1608 return;
1609 if (efer & EFER_LMA) {
1610 vmcs_write32(VM_ENTRY_CONTROLS,
1611 vmcs_read32(VM_ENTRY_CONTROLS) |
1612 VM_ENTRY_IA32E_MODE);
1613 msr->data = efer;
1614 } else {
1615 vmcs_write32(VM_ENTRY_CONTROLS,
1616 vmcs_read32(VM_ENTRY_CONTROLS) &
1617 ~VM_ENTRY_IA32E_MODE);
1618
1619 msr->data = efer & ~EFER_LME;
1620 }
1621 setup_msrs(vmx);
1622}
1623
05b3e0c2 1624#ifdef CONFIG_X86_64
6aa8b732
AK		 1625
1626static void enter_lmode(struct kvm_vcpu *vcpu)
1627{
1628 u32 guest_tr_ar;
1629
1630 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1631 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1632 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
b8688d51 1633 __func__);
6aa8b732
AK		 1634 vmcs_write32(GUEST_TR_AR_BYTES,
1635 (guest_tr_ar & ~AR_TYPE_MASK)
1636 | AR_TYPE_BUSY_64_TSS);
1637 }
f6801dff
AK		 1638 vcpu->arch.efer |= EFER_LMA;
1639 vmx_set_efer(vcpu, vcpu->arch.efer);
6aa8b732
AK		 1640}
1641
1642static void exit_lmode(struct kvm_vcpu *vcpu)
1643{
f6801dff 1644 vcpu->arch.efer &= ~EFER_LMA;
6aa8b732
AK		 1645
1646 vmcs_write32(VM_ENTRY_CONTROLS,
1647 vmcs_read32(VM_ENTRY_CONTROLS)
1e4e6e00 1648 & ~VM_ENTRY_IA32E_MODE);
6aa8b732
AK		 1649}
1650
1651#endif
1652
2384d2b3
SY		 1653static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1654{
1655 vpid_sync_vcpu_all(to_vmx(vcpu));
089d034e 1656 if (enable_ept)
4e1096d2 1657 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
2384d2b3
SY		 1658}
1659
e8467fda
AK		 1660static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1661{
1662 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
1663
1664 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
1665 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
1666}
1667
25c4c276 1668static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 1669{
fc78f519
AK		 1670 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
1671
1672 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
1673 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 1674}
1675
1439442c
SY		 1676static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
1677{
6de4f3ad
AK		 1678 if (!test_bit(VCPU_EXREG_PDPTR,
1679 (unsigned long *)&vcpu->arch.regs_dirty))
1680 return;
1681
1439442c 1682 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1439442c
SY		 1683 vmcs_write64(GUEST_PDPTR0, vcpu->arch.pdptrs[0]);
1684 vmcs_write64(GUEST_PDPTR1, vcpu->arch.pdptrs[1]);
1685 vmcs_write64(GUEST_PDPTR2, vcpu->arch.pdptrs[2]);
1686 vmcs_write64(GUEST_PDPTR3, vcpu->arch.pdptrs[3]);
1687 }
1688}
1689
8f5d549f
AK		 1690static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
1691{
1692 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1693 vcpu->arch.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
1694 vcpu->arch.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
1695 vcpu->arch.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
1696 vcpu->arch.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
1697 }
6de4f3ad
AK		 1698
1699 __set_bit(VCPU_EXREG_PDPTR,
1700 (unsigned long *)&vcpu->arch.regs_avail);
1701 __set_bit(VCPU_EXREG_PDPTR,
1702 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 1703}
1704
1439442c
SY		 1705static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1706
1707static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
1708 unsigned long cr0,
1709 struct kvm_vcpu *vcpu)
1710{
1711 if (!(cr0 & X86_CR0_PG)) {
1712 /* From paging/starting to nonpaging */
1713 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 1714 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 1715 (CPU_BASED_CR3_LOAD_EXITING |
1716 CPU_BASED_CR3_STORE_EXITING));
1717 vcpu->arch.cr0 = cr0;
fc78f519 1718 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 1719 } else if (!is_paging(vcpu)) {
1720 /* From nonpaging to paging */
1721 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 1722 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 1723 ~(CPU_BASED_CR3_LOAD_EXITING |
1724 CPU_BASED_CR3_STORE_EXITING));
1725 vcpu->arch.cr0 = cr0;
fc78f519 1726 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 1727 }
95eb84a7
SY		 1728
1729 if (!(cr0 & X86_CR0_WP))
1730 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 1731}
1732
6aa8b732
AK		 1733static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1734{
7ffd92c5 1735 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 1736 unsigned long hw_cr0;
1737
1738 if (enable_unrestricted_guest)
1739 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
1740 | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
1741 else
1742 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
1439442c 1743
7ffd92c5 1744 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
6aa8b732
AK		 1745 enter_pmode(vcpu);
1746
7ffd92c5 1747 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
6aa8b732
AK		 1748 enter_rmode(vcpu);
1749
05b3e0c2 1750#ifdef CONFIG_X86_64
f6801dff 1751 if (vcpu->arch.efer & EFER_LME) {
707d92fa 1752 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 1753 enter_lmode(vcpu);
707d92fa 1754 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 1755 exit_lmode(vcpu);
1756 }
1757#endif
1758
089d034e 1759 if (enable_ept)
1439442c
SY		 1760 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
1761
02daab21 1762 if (!vcpu->fpu_active)
81231c69 1763 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
02daab21 1764
6aa8b732 1765 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 1766 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 1767 vcpu->arch.cr0 = cr0;
6aa8b732
AK		 1768}
1769
1439442c
SY		 1770static u64 construct_eptp(unsigned long root_hpa)
1771{
1772 u64 eptp;
1773
1774 /* TODO write the value reading from MSR */
1775 eptp = VMX_EPT_DEFAULT_MT |
1776 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
1777 eptp |= (root_hpa & PAGE_MASK);
1778
1779 return eptp;
1780}
1781
6aa8b732
AK		 1782static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1783{
1439442c
SY		 1784 unsigned long guest_cr3;
1785 u64 eptp;
1786
1787 guest_cr3 = cr3;
089d034e 1788 if (enable_ept) {
1439442c
SY		 1789 eptp = construct_eptp(cr3);
1790 vmcs_write64(EPT_POINTER, eptp);
1439442c 1791 guest_cr3 = is_paging(vcpu) ? vcpu->arch.cr3 :
b927a3ce 1792 vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 1793 ept_load_pdptrs(vcpu);
1439442c
SY		 1794 }
1795
2384d2b3 1796 vmx_flush_tlb(vcpu);
1439442c 1797 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK		 1798}
1799
1800static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1801{
7ffd92c5 1802 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1439442c
SY		 1803 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1804
ad312c7c 1805 vcpu->arch.cr4 = cr4;
bc23008b
AK		 1806 if (enable_ept) {
1807 if (!is_paging(vcpu)) {
1808 hw_cr4 &= ~X86_CR4_PAE;
1809 hw_cr4 |= X86_CR4_PSE;
1810 } else if (!(cr4 & X86_CR4_PAE)) {
1811 hw_cr4 &= ~X86_CR4_PAE;
1812 }
1813 }
1439442c
SY		 1814
1815 vmcs_writel(CR4_READ_SHADOW, cr4);
1816 vmcs_writel(GUEST_CR4, hw_cr4);
6aa8b732
AK		 1817}
1818
6aa8b732
AK		 1819static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1820{
1821 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1822
1823 return vmcs_readl(sf->base);
1824}
1825
1826static void vmx_get_segment(struct kvm_vcpu *vcpu,
1827 struct kvm_segment *var, int seg)
1828{
1829 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1830 u32 ar;
1831
1832 var->base = vmcs_readl(sf->base);
1833 var->limit = vmcs_read32(sf->limit);
1834 var->selector = vmcs_read16(sf->selector);
1835 ar = vmcs_read32(sf->ar_bytes);
9fd4a3b7 1836 if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
6aa8b732
AK		 1837 ar = 0;
1838 var->type = ar & 15;
1839 var->s = (ar >> 4) & 1;
1840 var->dpl = (ar >> 5) & 3;
1841 var->present = (ar >> 7) & 1;
1842 var->avl = (ar >> 12) & 1;
1843 var->l = (ar >> 13) & 1;
1844 var->db = (ar >> 14) & 1;
1845 var->g = (ar >> 15) & 1;
1846 var->unusable = (ar >> 16) & 1;
1847}
1848
2e4d2653
IE		 1849static int vmx_get_cpl(struct kvm_vcpu *vcpu)
1850{
3eeb3288 1851 if (!is_protmode(vcpu))
2e4d2653
IE		 1852 return 0;
1853
1854 if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */
1855 return 3;
1856
eab4b8aa 1857 return vmcs_read16(GUEST_CS_SELECTOR) & 3;
2e4d2653
IE		 1858}
1859
653e3108 1860static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 1861{
6aa8b732
AK		 1862 u32 ar;
1863
653e3108 1864 if (var->unusable)
6aa8b732
AK		 1865 ar = 1 << 16;
1866 else {
1867 ar = var->type & 15;
1868 ar |= (var->s & 1) << 4;
1869 ar |= (var->dpl & 3) << 5;
1870 ar |= (var->present & 1) << 7;
1871 ar |= (var->avl & 1) << 12;
1872 ar |= (var->l & 1) << 13;
1873 ar |= (var->db & 1) << 14;
1874 ar |= (var->g & 1) << 15;
1875 }
f7fbf1fd
UL		 1876 if (ar == 0) /* a 0 value means unusable */
1877 ar = AR_UNUSABLE_MASK;
653e3108
AK		 1878
1879 return ar;
1880}
1881
1882static void vmx_set_segment(struct kvm_vcpu *vcpu,
1883 struct kvm_segment *var, int seg)
1884{
7ffd92c5 1885 struct vcpu_vmx *vmx = to_vmx(vcpu);
653e3108
AK		 1886 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1887 u32 ar;
1888
7ffd92c5
AK		 1889 if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
1890 vmx->rmode.tr.selector = var->selector;
1891 vmx->rmode.tr.base = var->base;
1892 vmx->rmode.tr.limit = var->limit;
1893 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
653e3108
AK		 1894 return;
1895 }
1896 vmcs_writel(sf->base, var->base);
1897 vmcs_write32(sf->limit, var->limit);
1898 vmcs_write16(sf->selector, var->selector);
7ffd92c5 1899 if (vmx->rmode.vm86_active && var->s) {
653e3108
AK		 1900 /*
1901 * Hack real-mode segments into vm86 compatibility.
1902 */
1903 if (var->base == 0xffff0000 && var->selector == 0xf000)
1904 vmcs_writel(sf->base, 0xf0000);
1905 ar = 0xf3;
1906 } else
1907 ar = vmx_segment_access_rights(var);
3a624e29
NK		 1908
1909 /*
1910 * Fix the "Accessed" bit in AR field of segment registers for older
1911 * qemu binaries.
1912 * IA32 arch specifies that at the time of processor reset the
1913 * "Accessed" bit in the AR field of segment registers is 1. And qemu
1914 * is setting it to 0 in the usedland code. This causes invalid guest
1915 * state vmexit when "unrestricted guest" mode is turned on.
1916 * Fix for this setup issue in cpu_reset is being pushed in the qemu
1917 * tree. Newer qemu binaries with that qemu fix would not need this
1918 * kvm hack.
1919 */
1920 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
1921 ar |= 0x1; /* Accessed */
1922
6aa8b732
AK		 1923 vmcs_write32(sf->ar_bytes, ar);
1924}
1925
6aa8b732
AK		 1926static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
1927{
1928 u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
1929
1930 *db = (ar >> 14) & 1;
1931 *l = (ar >> 13) & 1;
1932}
1933
1934static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1935{
1936 dt->limit = vmcs_read32(GUEST_IDTR_LIMIT);
1937 dt->base = vmcs_readl(GUEST_IDTR_BASE);
1938}
1939
1940static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1941{
1942 vmcs_write32(GUEST_IDTR_LIMIT, dt->limit);
1943 vmcs_writel(GUEST_IDTR_BASE, dt->base);
1944}
1945
1946static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1947{
1948 dt->limit = vmcs_read32(GUEST_GDTR_LIMIT);
1949 dt->base = vmcs_readl(GUEST_GDTR_BASE);
1950}
1951
1952static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1953{
1954 vmcs_write32(GUEST_GDTR_LIMIT, dt->limit);
1955 vmcs_writel(GUEST_GDTR_BASE, dt->base);
1956}
1957
648dfaa7
MG		 1958static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
1959{
1960 struct kvm_segment var;
1961 u32 ar;
1962
1963 vmx_get_segment(vcpu, &var, seg);
1964 ar = vmx_segment_access_rights(&var);
1965
1966 if (var.base != (var.selector << 4))
1967 return false;
1968 if (var.limit != 0xffff)
1969 return false;
1970 if (ar != 0xf3)
1971 return false;
1972
1973 return true;
1974}
1975
1976static bool code_segment_valid(struct kvm_vcpu *vcpu)
1977{
1978 struct kvm_segment cs;
1979 unsigned int cs_rpl;
1980
1981 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
1982 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
1983
1872a3f4
AK		 1984 if (cs.unusable)
1985 return false;
648dfaa7
MG		 1986 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
1987 return false;
1988 if (!cs.s)
1989 return false;
1872a3f4 1990 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 1991 if (cs.dpl > cs_rpl)
1992 return false;
1872a3f4 1993 } else {
648dfaa7
MG		 1994 if (cs.dpl != cs_rpl)
1995 return false;
1996 }
1997 if (!cs.present)
1998 return false;
1999
2000 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
2001 return true;
2002}
2003
2004static bool stack_segment_valid(struct kvm_vcpu *vcpu)
2005{
2006 struct kvm_segment ss;
2007 unsigned int ss_rpl;
2008
2009 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2010 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
2011
1872a3f4
AK		 2012 if (ss.unusable)
2013 return true;
2014 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 2015 return false;
2016 if (!ss.s)
2017 return false;
2018 if (ss.dpl != ss_rpl) /* DPL != RPL */
2019 return false;
2020 if (!ss.present)
2021 return false;
2022
2023 return true;
2024}
2025
2026static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
2027{
2028 struct kvm_segment var;
2029 unsigned int rpl;
2030
2031 vmx_get_segment(vcpu, &var, seg);
2032 rpl = var.selector & SELECTOR_RPL_MASK;
2033
1872a3f4
AK		 2034 if (var.unusable)
2035 return true;
648dfaa7
MG		 2036 if (!var.s)
2037 return false;
2038 if (!var.present)
2039 return false;
2040 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
2041 if (var.dpl < rpl) /* DPL < RPL */
2042 return false;
2043 }
2044
2045 /* TODO: Add other members to kvm_segment_field to allow checking for other access
2046 * rights flags
2047 */
2048 return true;
2049}
2050
2051static bool tr_valid(struct kvm_vcpu *vcpu)
2052{
2053 struct kvm_segment tr;
2054
2055 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
2056
1872a3f4
AK		 2057 if (tr.unusable)
2058 return false;
648dfaa7
MG		 2059 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
2060 return false;
1872a3f4 2061 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 2062 return false;
2063 if (!tr.present)
2064 return false;
2065
2066 return true;
2067}
2068
2069static bool ldtr_valid(struct kvm_vcpu *vcpu)
2070{
2071 struct kvm_segment ldtr;
2072
2073 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
2074
1872a3f4
AK		 2075 if (ldtr.unusable)
2076 return true;
648dfaa7
MG		 2077 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
2078 return false;
2079 if (ldtr.type != 2)
2080 return false;
2081 if (!ldtr.present)
2082 return false;
2083
2084 return true;
2085}
2086
2087static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
2088{
2089 struct kvm_segment cs, ss;
2090
2091 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2092 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2093
2094 return ((cs.selector & SELECTOR_RPL_MASK) ==
2095 (ss.selector & SELECTOR_RPL_MASK));
2096}
2097
2098/*
2099 * Check if guest state is valid. Returns true if valid, false if
2100 * not.
2101 * We assume that registers are always usable
2102 */
2103static bool guest_state_valid(struct kvm_vcpu *vcpu)
2104{
2105 /* real mode guest state checks */
3eeb3288 2106 if (!is_protmode(vcpu)) {
648dfaa7
MG		 2107 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
2108 return false;
2109 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
2110 return false;
2111 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
2112 return false;
2113 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
2114 return false;
2115 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
2116 return false;
2117 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
2118 return false;
2119 } else {
2120 /* protected mode guest state checks */
2121 if (!cs_ss_rpl_check(vcpu))
2122 return false;
2123 if (!code_segment_valid(vcpu))
2124 return false;
2125 if (!stack_segment_valid(vcpu))
2126 return false;
2127 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
2128 return false;
2129 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
2130 return false;
2131 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
2132 return false;
2133 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
2134 return false;
2135 if (!tr_valid(vcpu))
2136 return false;
2137 if (!ldtr_valid(vcpu))
2138 return false;
2139 }
2140 /* TODO:
2141 * - Add checks on RIP
2142 * - Add checks on RFLAGS
2143 */
2144
2145 return true;
2146}
2147
d77c26fc 2148static int init_rmode_tss(struct kvm *kvm)
6aa8b732 2149{
6aa8b732 2150 gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
195aefde 2151 u16 data = 0;
10589a46 2152 int ret = 0;
195aefde 2153 int r;
6aa8b732 2154
195aefde
IE		 2155 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2156 if (r < 0)
10589a46 2157 goto out;
195aefde 2158 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 2159 r = kvm_write_guest_page(kvm, fn++, &data,
2160 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 2161 if (r < 0)
10589a46 2162 goto out;
195aefde
IE		 2163 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
2164 if (r < 0)
10589a46 2165 goto out;
195aefde
IE		 2166 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2167 if (r < 0)
10589a46 2168 goto out;
195aefde 2169 data = ~0;
10589a46
MT		 2170 r = kvm_write_guest_page(kvm, fn, &data,
2171 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
2172 sizeof(u8));
195aefde 2173 if (r < 0)
10589a46
MT		 2174 goto out;
2175
2176 ret = 1;
2177out:
10589a46 2178 return ret;
6aa8b732
AK		 2179}
2180
b7ebfb05
SY		 2181static int init_rmode_identity_map(struct kvm *kvm)
2182{
2183 int i, r, ret;
2184 pfn_t identity_map_pfn;
2185 u32 tmp;
2186
089d034e 2187 if (!enable_ept)
b7ebfb05
SY		 2188 return 1;
2189 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
2190 printk(KERN_ERR "EPT: identity-mapping pagetable "
2191 "haven't been allocated!\n");
2192 return 0;
2193 }
2194 if (likely(kvm->arch.ept_identity_pagetable_done))
2195 return 1;
2196 ret = 0;
b927a3ce 2197 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
b7ebfb05
SY		 2198 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
2199 if (r < 0)
2200 goto out;
2201 /* Set up identity-mapping pagetable for EPT in real mode */
2202 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
2203 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
2204 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
2205 r = kvm_write_guest_page(kvm, identity_map_pfn,
2206 &tmp, i * sizeof(tmp), sizeof(tmp));
2207 if (r < 0)
2208 goto out;
2209 }
2210 kvm->arch.ept_identity_pagetable_done = true;
2211 ret = 1;
2212out:
2213 return ret;
2214}
2215
6aa8b732
AK		 2216static void seg_setup(int seg)
2217{
2218 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 2219 unsigned int ar;
6aa8b732
AK		 2220
2221 vmcs_write16(sf->selector, 0);
2222 vmcs_writel(sf->base, 0);
2223 vmcs_write32(sf->limit, 0xffff);
3a624e29
NK		 2224 if (enable_unrestricted_guest) {
2225 ar = 0x93;
2226 if (seg == VCPU_SREG_CS)
2227 ar |= 0x08; /* code segment */
2228 } else
2229 ar = 0xf3;
2230
2231 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 2232}
2233
f78e0e2e
SY		 2234static int alloc_apic_access_page(struct kvm *kvm)
2235{
2236 struct kvm_userspace_memory_region kvm_userspace_mem;
2237 int r = 0;
2238
79fac95e 2239 mutex_lock(&kvm->slots_lock);
bfc6d222 2240 if (kvm->arch.apic_access_page)
f78e0e2e
SY		 2241 goto out;
2242 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
2243 kvm_userspace_mem.flags = 0;
2244 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
2245 kvm_userspace_mem.memory_size = PAGE_SIZE;
2246 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2247 if (r)
2248 goto out;
72dc67a6 2249
bfc6d222 2250 kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
f78e0e2e 2251out:
79fac95e 2252 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY		 2253 return r;
2254}
2255
b7ebfb05
SY		 2256static int alloc_identity_pagetable(struct kvm *kvm)
2257{
2258 struct kvm_userspace_memory_region kvm_userspace_mem;
2259 int r = 0;
2260
79fac95e 2261 mutex_lock(&kvm->slots_lock);
b7ebfb05
SY		 2262 if (kvm->arch.ept_identity_pagetable)
2263 goto out;
2264 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
2265 kvm_userspace_mem.flags = 0;
b927a3ce
SY		 2266 kvm_userspace_mem.guest_phys_addr =
2267 kvm->arch.ept_identity_map_addr;
b7ebfb05
SY		 2268 kvm_userspace_mem.memory_size = PAGE_SIZE;
2269 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2270 if (r)
2271 goto out;
2272
b7ebfb05 2273 kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
b927a3ce 2274 kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
b7ebfb05 2275out:
79fac95e 2276 mutex_unlock(&kvm->slots_lock);
b7ebfb05
SY		 2277 return r;
2278}
2279
2384d2b3
SY		 2280static void allocate_vpid(struct vcpu_vmx *vmx)
2281{
2282 int vpid;
2283
2284 vmx->vpid = 0;
919818ab 2285 if (!enable_vpid)
2384d2b3
SY		 2286 return;
2287 spin_lock(&vmx_vpid_lock);
2288 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
2289 if (vpid < VMX_NR_VPIDS) {
2290 vmx->vpid = vpid;
2291 __set_bit(vpid, vmx_vpid_bitmap);
2292 }
2293 spin_unlock(&vmx_vpid_lock);
2294}
2295
5897297b 2296static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
25c5f225 2297{
3e7c73e9 2298 int f = sizeof(unsigned long);
25c5f225
SY		 2299
2300 if (!cpu_has_vmx_msr_bitmap())
2301 return;
2302
2303 /*
2304 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2305 * have the write-low and read-high bitmap offsets the wrong way round.
2306 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2307 */
25c5f225 2308 if (msr <= 0x1fff) {
3e7c73e9
AK		 2309 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
2310 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
25c5f225
SY		 2311 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2312 msr &= 0x1fff;
3e7c73e9
AK		 2313 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
2314 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
25c5f225 2315 }
25c5f225
SY		 2316}
2317
5897297b
AK		 2318static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
2319{
2320 if (!longmode_only)
2321 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
2322 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
2323}
2324
6aa8b732
AK		 2325/*
2326 * Sets up the vmcs for emulated real mode.
2327 */
8b9cf98c 2328static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 2329{
468d472f 2330 u32 host_sysenter_cs, msr_low, msr_high;
6aa8b732 2331 u32 junk;
53f658b3 2332 u64 host_pat, tsc_this, tsc_base;
6aa8b732
AK		 2333 unsigned long a;
2334 struct descriptor_table dt;
2335 int i;
cd2276a7 2336 unsigned long kvm_vmx_return;
6e5d865c 2337 u32 exec_control;
6aa8b732 2338
6aa8b732 2339 /* I/O */
3e7c73e9
AK		 2340 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
2341 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 2342
25c5f225 2343 if (cpu_has_vmx_msr_bitmap())
5897297b 2344 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 2345
6aa8b732
AK		 2346 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
2347
6aa8b732 2348 /* Control */
1c3d14fe
YS		 2349 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
2350 vmcs_config.pin_based_exec_ctrl);
6e5d865c
YS		 2351
2352 exec_control = vmcs_config.cpu_based_exec_ctrl;
2353 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
2354 exec_control &= ~CPU_BASED_TPR_SHADOW;
2355#ifdef CONFIG_X86_64
2356 exec_control |= CPU_BASED_CR8_STORE_EXITING |
2357 CPU_BASED_CR8_LOAD_EXITING;
2358#endif
2359 }
089d034e 2360 if (!enable_ept)
d56f546d 2361 exec_control |= CPU_BASED_CR3_STORE_EXITING |
83dbc83a
MT		 2362 CPU_BASED_CR3_LOAD_EXITING |
2363 CPU_BASED_INVLPG_EXITING;
6e5d865c 2364 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
6aa8b732 2365
83ff3b9d
SY		 2366 if (cpu_has_secondary_exec_ctrls()) {
2367 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
2368 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2369 exec_control &=
2370 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2384d2b3
SY		 2371 if (vmx->vpid == 0)
2372 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
046d8710 2373 if (!enable_ept) {
d56f546d 2374 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
046d8710
SY		 2375 enable_unrestricted_guest = 0;
2376 }
3a624e29
NK		 2377 if (!enable_unrestricted_guest)
2378 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4b8d54f9
ZE		 2379 if (!ple_gap)
2380 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
83ff3b9d
SY		 2381 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
2382 }
f78e0e2e 2383
4b8d54f9
ZE		 2384 if (ple_gap) {
2385 vmcs_write32(PLE_GAP, ple_gap);
2386 vmcs_write32(PLE_WINDOW, ple_window);
2387 }
2388
c7addb90
AK		 2389 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
2390 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
6aa8b732
AK		 2391 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
2392
2393 vmcs_writel(HOST_CR0, read_cr0()); /* 22.2.3 */
2394 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
2395 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
2396
2397 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
2398 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2399 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
d6e88aec
AK		 2400 vmcs_write16(HOST_FS_SELECTOR, kvm_read_fs()); /* 22.2.4 */
2401 vmcs_write16(HOST_GS_SELECTOR, kvm_read_gs()); /* 22.2.4 */
6aa8b732 2402 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
05b3e0c2 2403#ifdef CONFIG_X86_64
6aa8b732
AK		 2404 rdmsrl(MSR_FS_BASE, a);
2405 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
2406 rdmsrl(MSR_GS_BASE, a);
2407 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
2408#else
2409 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
2410 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
2411#endif
2412
2413 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
2414
d6e88aec 2415 kvm_get_idt(&dt);
6aa8b732
AK		 2416 vmcs_writel(HOST_IDTR_BASE, dt.base); /* 22.2.4 */
2417
d77c26fc 2418 asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
cd2276a7 2419 vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2cc51560
ED		 2420 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
2421 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
2422 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
6aa8b732
AK		 2423
2424 rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
2425 vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
2426 rdmsrl(MSR_IA32_SYSENTER_ESP, a);
2427 vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */
2428 rdmsrl(MSR_IA32_SYSENTER_EIP, a);
2429 vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */
2430
468d472f
SY		 2431 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
2432 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2433 host_pat = msr_low | ((u64) msr_high << 32);
2434 vmcs_write64(HOST_IA32_PAT, host_pat);
2435 }
2436 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2437 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2438 host_pat = msr_low | ((u64) msr_high << 32);
2439 /* Write the default value follow host pat */
2440 vmcs_write64(GUEST_IA32_PAT, host_pat);
2441 /* Keep arch.pat sync with GUEST_IA32_PAT */
2442 vmx->vcpu.arch.pat = host_pat;
2443 }
2444
6aa8b732
AK		 2445 for (i = 0; i < NR_VMX_MSR; ++i) {
2446 u32 index = vmx_msr_index[i];
2447 u32 data_low, data_high;
a2fa3e9f 2448 int j = vmx->nmsrs;
6aa8b732
AK		 2449
2450 if (rdmsr_safe(index, &data_low, &data_high) < 0)
2451 continue;
432bd6cb
AK		 2452 if (wrmsr_safe(index, data_low, data_high) < 0)
2453 continue;
26bb0981
AK		 2454 vmx->guest_msrs[j].index = i;
2455 vmx->guest_msrs[j].data = 0;
d5696725 2456 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 2457 ++vmx->nmsrs;
6aa8b732 2458 }
6aa8b732 2459
1c3d14fe 2460 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 2461
2462 /* 22.2.1, 20.8.1 */
1c3d14fe
YS		 2463 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
2464
e00c8cf2 2465 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
4c38609a 2466 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
ce03e4f2
AK		 2467 if (enable_ept)
2468 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
4c38609a 2469 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
e00c8cf2 2470
53f658b3
MT		 2471 tsc_base = vmx->vcpu.kvm->arch.vm_init_tsc;
2472 rdtscll(tsc_this);
2473 if (tsc_this < vmx->vcpu.kvm->arch.vm_init_tsc)
2474 tsc_base = tsc_this;
2475
2476 guest_write_tsc(0, tsc_base);
f78e0e2e 2477
e00c8cf2
AK		 2478 return 0;
2479}
2480
b7ebfb05
SY		 2481static int init_rmode(struct kvm *kvm)
2482{
2483 if (!init_rmode_tss(kvm))
2484 return 0;
2485 if (!init_rmode_identity_map(kvm))
2486 return 0;
2487 return 1;
2488}
2489
e00c8cf2
AK		 2490static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
2491{
2492 struct vcpu_vmx *vmx = to_vmx(vcpu);
2493 u64 msr;
f656ce01 2494 int ret, idx;
e00c8cf2 2495
5fdbf976 2496 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
f656ce01 2497 idx = srcu_read_lock(&vcpu->kvm->srcu);
b7ebfb05 2498 if (!init_rmode(vmx->vcpu.kvm)) {
e00c8cf2
AK		 2499 ret = -ENOMEM;
2500 goto out;
2501 }
2502
7ffd92c5 2503 vmx->rmode.vm86_active = 0;
e00c8cf2 2504
3b86cd99
JK		 2505 vmx->soft_vnmi_blocked = 0;
2506
ad312c7c 2507 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 2508 kvm_set_cr8(&vmx->vcpu, 0);
e00c8cf2 2509 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 2510 if (kvm_vcpu_is_bsp(&vmx->vcpu))
e00c8cf2
AK		 2511 msr |= MSR_IA32_APICBASE_BSP;
2512 kvm_set_apic_base(&vmx->vcpu, msr);
2513
2514 fx_init(&vmx->vcpu);
2515
5706be0d 2516 seg_setup(VCPU_SREG_CS);
e00c8cf2
AK		 2517 /*
2518 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2519 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
2520 */
c5af89b6 2521 if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
e00c8cf2
AK		 2522 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2523 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2524 } else {
ad312c7c
ZX		 2525 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2526 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
e00c8cf2 2527 }
e00c8cf2
AK		 2528
2529 seg_setup(VCPU_SREG_DS);
2530 seg_setup(VCPU_SREG_ES);
2531 seg_setup(VCPU_SREG_FS);
2532 seg_setup(VCPU_SREG_GS);
2533 seg_setup(VCPU_SREG_SS);
2534
2535 vmcs_write16(GUEST_TR_SELECTOR, 0);
2536 vmcs_writel(GUEST_TR_BASE, 0);
2537 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
2538 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2539
2540 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
2541 vmcs_writel(GUEST_LDTR_BASE, 0);
2542 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
2543 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
2544
2545 vmcs_write32(GUEST_SYSENTER_CS, 0);
2546 vmcs_writel(GUEST_SYSENTER_ESP, 0);
2547 vmcs_writel(GUEST_SYSENTER_EIP, 0);
2548
2549 vmcs_writel(GUEST_RFLAGS, 0x02);
c5af89b6 2550 if (kvm_vcpu_is_bsp(&vmx->vcpu))
5fdbf976 2551 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 2552 else
5fdbf976
MT		 2553 kvm_rip_write(vcpu, 0);
2554 kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
e00c8cf2 2555
e00c8cf2
AK		 2556 vmcs_writel(GUEST_DR7, 0x400);
2557
2558 vmcs_writel(GUEST_GDTR_BASE, 0);
2559 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
2560
2561 vmcs_writel(GUEST_IDTR_BASE, 0);
2562 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
2563
2564 vmcs_write32(GUEST_ACTIVITY_STATE, 0);
2565 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
2566 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
2567
e00c8cf2
AK		 2568 /* Special registers */
2569 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
2570
2571 setup_msrs(vmx);
2572
6aa8b732
AK		 2573 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
2574
f78e0e2e
SY		 2575 if (cpu_has_vmx_tpr_shadow()) {
2576 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
2577 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
2578 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
ad312c7c 2579 page_to_phys(vmx->vcpu.arch.apic->regs_page));
f78e0e2e
SY		 2580 vmcs_write32(TPR_THRESHOLD, 0);
2581 }
2582
2583 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2584 vmcs_write64(APIC_ACCESS_ADDR,
bfc6d222 2585 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
6aa8b732 2586
2384d2b3
SY		 2587 if (vmx->vpid != 0)
2588 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2589
fa40052c 2590 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4d4ec087 2591 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
8b9cf98c 2592 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 2593 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 2594 vmx_fpu_activate(&vmx->vcpu);
2595 update_exception_bitmap(&vmx->vcpu);
6aa8b732 2596
2384d2b3
SY		 2597 vpid_sync_vcpu_all(vmx);
2598
3200f405 2599 ret = 0;
6aa8b732 2600
a89a8fb9
MG		 2601 /* HACK: Don't enable emulation on guest boot/reset */
2602 vmx->emulation_required = 0;
2603
6aa8b732 2604out:
f656ce01 2605 srcu_read_unlock(&vcpu->kvm->srcu, idx);
6aa8b732
AK		 2606 return ret;
2607}
2608
3b86cd99
JK		 2609static void enable_irq_window(struct kvm_vcpu *vcpu)
2610{
2611 u32 cpu_based_vm_exec_control;
2612
2613 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2614 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2615 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2616}
2617
2618static void enable_nmi_window(struct kvm_vcpu *vcpu)
2619{
2620 u32 cpu_based_vm_exec_control;
2621
2622 if (!cpu_has_virtual_nmis()) {
2623 enable_irq_window(vcpu);
2624 return;
2625 }
2626
2627 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2628 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
2629 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2630}
2631
66fd3f7f 2632static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 2633{
9c8cba37 2634 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 2635 uint32_t intr;
2636 int irq = vcpu->arch.interrupt.nr;
9c8cba37 2637
229456fc 2638 trace_kvm_inj_virq(irq);
2714d1d3 2639
fa89a817 2640 ++vcpu->stat.irq_injections;
7ffd92c5 2641 if (vmx->rmode.vm86_active) {
9c8cba37
AK		 2642 vmx->rmode.irq.pending = true;
2643 vmx->rmode.irq.vector = irq;
5fdbf976 2644 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
ae0bb3e0
GN		 2645 if (vcpu->arch.interrupt.soft)
2646 vmx->rmode.irq.rip +=
2647 vmx->vcpu.arch.event_exit_inst_len;
9c5623e3
AK		 2648 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2649 irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK);
2650 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
5fdbf976 2651 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
85f455f7
ED		 2652 return;
2653 }
66fd3f7f
GN		 2654 intr = irq | INTR_INFO_VALID_MASK;
2655 if (vcpu->arch.interrupt.soft) {
2656 intr |= INTR_TYPE_SOFT_INTR;
2657 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2658 vmx->vcpu.arch.event_exit_inst_len);
2659 } else
2660 intr |= INTR_TYPE_EXT_INTR;
2661 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
85f455f7
ED		 2662}
2663
f08864b4
SY		 2664static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
2665{
66a5a347
JK		 2666 struct vcpu_vmx *vmx = to_vmx(vcpu);
2667
3b86cd99
JK		 2668 if (!cpu_has_virtual_nmis()) {
2669 /*
2670 * Tracking the NMI-blocked state in software is built upon
2671 * finding the next open IRQ window. This, in turn, depends on
2672 * well-behaving guests: They have to keep IRQs disabled at
2673 * least as long as the NMI handler runs. Otherwise we may
2674 * cause NMI nesting, maybe breaking the guest. But as this is
2675 * highly unlikely, we can live with the residual risk.
2676 */
2677 vmx->soft_vnmi_blocked = 1;
2678 vmx->vnmi_blocked_time = 0;
2679 }
2680
487b391d 2681 ++vcpu->stat.nmi_injections;
7ffd92c5 2682 if (vmx->rmode.vm86_active) {
66a5a347
JK		 2683 vmx->rmode.irq.pending = true;
2684 vmx->rmode.irq.vector = NMI_VECTOR;
2685 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2686 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2687 NMI_VECTOR | INTR_TYPE_SOFT_INTR |
2688 INTR_INFO_VALID_MASK);
2689 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2690 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2691 return;
2692 }
f08864b4
SY		 2693 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2694 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
f08864b4
SY		 2695}
2696
c4282df9 2697static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
33f089ca 2698{
3b86cd99 2699 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
c4282df9 2700 return 0;
33f089ca 2701
c4282df9
GN		 2702 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2703 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS |
2704 GUEST_INTR_STATE_NMI));
33f089ca
JK		 2705}
2706
3cfc3092
JK		 2707static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
2708{
2709 if (!cpu_has_virtual_nmis())
2710 return to_vmx(vcpu)->soft_vnmi_blocked;
2711 else
2712 return !!(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2713 GUEST_INTR_STATE_NMI);
2714}
2715
2716static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
2717{
2718 struct vcpu_vmx *vmx = to_vmx(vcpu);
2719
2720 if (!cpu_has_virtual_nmis()) {
2721 if (vmx->soft_vnmi_blocked != masked) {
2722 vmx->soft_vnmi_blocked = masked;
2723 vmx->vnmi_blocked_time = 0;
2724 }
2725 } else {
2726 if (masked)
2727 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
2728 GUEST_INTR_STATE_NMI);
2729 else
2730 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
2731 GUEST_INTR_STATE_NMI);
2732 }
2733}
2734
78646121
GN		 2735static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
2736{
c4282df9
GN		 2737 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2738 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2739 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 2740}
2741
cbc94022
IE		 2742static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
2743{
2744 int ret;
2745 struct kvm_userspace_memory_region tss_mem = {
6fe63979 2746 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 2747 .guest_phys_addr = addr,
2748 .memory_size = PAGE_SIZE * 3,
2749 .flags = 0,
2750 };
2751
2752 ret = kvm_set_memory_region(kvm, &tss_mem, 0);
2753 if (ret)
2754 return ret;
bfc6d222 2755 kvm->arch.tss_addr = addr;
cbc94022
IE		 2756 return 0;
2757}
2758
6aa8b732
AK		 2759static int handle_rmode_exception(struct kvm_vcpu *vcpu,
2760 int vec, u32 err_code)
2761{
b3f37707
NK		 2762 /*
2763 * Instruction with address size override prefix opcode 0x67
2764 * Cause the #SS fault with 0 error code in VM86 mode.
2765 */
2766 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
851ba692 2767 if (emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE)
6aa8b732 2768 return 1;
77ab6db0
JK		 2769 /*
2770 * Forward all other exceptions that are valid in real mode.
2771 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
2772 * the required debugging infrastructure rework.
2773 */
2774 switch (vec) {
77ab6db0 2775 case DB_VECTOR:
d0bfb940
JK		 2776 if (vcpu->guest_debug &
2777 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
2778 return 0;
2779 kvm_queue_exception(vcpu, vec);
2780 return 1;
77ab6db0 2781 case BP_VECTOR:
d0bfb940
JK		 2782 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2783 return 0;
2784 /* fall through */
2785 case DE_VECTOR:
77ab6db0
JK		 2786 case OF_VECTOR:
2787 case BR_VECTOR:
2788 case UD_VECTOR:
2789 case DF_VECTOR:
2790 case SS_VECTOR:
2791 case GP_VECTOR:
2792 case MF_VECTOR:
2793 kvm_queue_exception(vcpu, vec);
2794 return 1;
2795 }
6aa8b732
AK		 2796 return 0;
2797}
2798
a0861c02
AK		 2799/*
2800 * Trigger machine check on the host. We assume all the MSRs are already set up
2801 * by the CPU and that we still run on the same CPU as the MCE occurred on.
2802 * We pass a fake environment to the machine check handler because we want
2803 * the guest to be always treated like user space, no matter what context
2804 * it used internally.
2805 */
2806static void kvm_machine_check(void)
2807{
2808#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
2809 struct pt_regs regs = {
2810 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
2811 .flags = X86_EFLAGS_IF,
2812 };
2813
2814 do_machine_check(&regs, 0);
2815#endif
2816}
2817
851ba692 2818static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK		 2819{
2820 /* already handled by vcpu_run */
2821 return 1;
2822}
2823
851ba692 2824static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 2825{
1155f76a 2826 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 2827 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 2828 u32 intr_info, ex_no, error_code;
42dbaa5a 2829 unsigned long cr2, rip, dr6;
6aa8b732
AK		 2830 u32 vect_info;
2831 enum emulation_result er;
2832
1155f76a 2833 vect_info = vmx->idt_vectoring_info;
6aa8b732
AK		 2834 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
2835
a0861c02 2836 if (is_machine_check(intr_info))
851ba692 2837 return handle_machine_check(vcpu);
a0861c02 2838
6aa8b732 2839 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
65ac7264
AK		 2840 !is_page_fault(intr_info)) {
2841 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2842 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
2843 vcpu->run->internal.ndata = 2;
2844 vcpu->run->internal.data[0] = vect_info;
2845 vcpu->run->internal.data[1] = intr_info;
2846 return 0;
2847 }
6aa8b732 2848
e4a41889 2849 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 2850 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 2851
2852 if (is_no_device(intr_info)) {
5fd86fcf 2853 vmx_fpu_activate(vcpu);
2ab455cc
AL		 2854 return 1;
2855 }
2856
7aa81cc0 2857 if (is_invalid_opcode(intr_info)) {
851ba692 2858 er = emulate_instruction(vcpu, 0, 0, EMULTYPE_TRAP_UD);
7aa81cc0 2859 if (er != EMULATE_DONE)
7ee5d940 2860 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 2861 return 1;
2862 }
2863
6aa8b732 2864 error_code = 0;
5fdbf976 2865 rip = kvm_rip_read(vcpu);
2e11384c 2866 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732
AK		 2867 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
2868 if (is_page_fault(intr_info)) {
1439442c 2869 /* EPT won't cause page fault directly */
089d034e 2870 if (enable_ept)
1439442c 2871 BUG();
6aa8b732 2872 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT		 2873 trace_kvm_page_fault(cr2, error_code);
2874
3298b75c 2875 if (kvm_event_needs_reinjection(vcpu))
577bdc49 2876 kvm_mmu_unprotect_page_virt(vcpu, cr2);
3067714c 2877 return kvm_mmu_page_fault(vcpu, cr2, error_code);
6aa8b732
AK		 2878 }
2879
7ffd92c5 2880 if (vmx->rmode.vm86_active &&
6aa8b732 2881 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
72d6e5a0 2882 error_code)) {
ad312c7c
ZX		 2883 if (vcpu->arch.halt_request) {
2884 vcpu->arch.halt_request = 0;
72d6e5a0
AK		 2885 return kvm_emulate_halt(vcpu);
2886 }
6aa8b732 2887 return 1;
72d6e5a0 2888 }
6aa8b732 2889
d0bfb940 2890 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
42dbaa5a
JK		 2891 switch (ex_no) {
2892 case DB_VECTOR:
2893 dr6 = vmcs_readl(EXIT_QUALIFICATION);
2894 if (!(vcpu->guest_debug &
2895 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
2896 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
2897 kvm_queue_exception(vcpu, DB_VECTOR);
2898 return 1;
2899 }
2900 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
2901 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
2902 /* fall through */
2903 case BP_VECTOR:
6aa8b732 2904 kvm_run->exit_reason = KVM_EXIT_DEBUG;
d0bfb940
JK		 2905 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
2906 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 2907 break;
2908 default:
d0bfb940
JK		 2909 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
2910 kvm_run->ex.exception = ex_no;
2911 kvm_run->ex.error_code = error_code;
42dbaa5a 2912 break;
6aa8b732 2913 }
6aa8b732
AK		 2914 return 0;
2915}
2916
851ba692 2917static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 2918{
1165f5fe 2919 ++vcpu->stat.irq_exits;
6aa8b732
AK		 2920 return 1;
2921}
2922
851ba692 2923static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 2924{
851ba692 2925 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK		 2926 return 0;
2927}
6aa8b732 2928
851ba692 2929static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 2930{
bfdaab09 2931 unsigned long exit_qualification;
34c33d16 2932 int size, in, string;
039576c0 2933 unsigned port;
6aa8b732 2934
1165f5fe 2935 ++vcpu->stat.io_exits;
bfdaab09 2936 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 2937 string = (exit_qualification & 16) != 0;
e70669ab
LV		 2938
2939 if (string) {
851ba692 2940 if (emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DO_MMIO)
e70669ab
LV		 2941 return 0;
2942 return 1;
2943 }
2944
2945 size = (exit_qualification & 7) + 1;
2946 in = (exit_qualification & 8) != 0;
039576c0 2947 port = exit_qualification >> 16;
e70669ab 2948
e93f36bc 2949 skip_emulated_instruction(vcpu);
851ba692 2950 return kvm_emulate_pio(vcpu, in, size, port);
6aa8b732
AK		 2951}
2952
102d8325
IM		 2953static void
2954vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2955{
2956 /*
2957 * Patch in the VMCALL instruction:
2958 */
2959 hypercall[0] = 0x0f;
2960 hypercall[1] = 0x01;
2961 hypercall[2] = 0xc1;
102d8325
IM		 2962}
2963
851ba692 2964static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 2965{
229456fc 2966 unsigned long exit_qualification, val;
6aa8b732
AK		 2967 int cr;
2968 int reg;
2969
bfdaab09 2970 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 2971 cr = exit_qualification & 15;
2972 reg = (exit_qualification >> 8) & 15;
2973 switch ((exit_qualification >> 4) & 3) {
2974 case 0: /* mov to cr */
229456fc
MT		 2975 val = kvm_register_read(vcpu, reg);
2976 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 2977 switch (cr) {
2978 case 0:
229456fc 2979 kvm_set_cr0(vcpu, val);
6aa8b732
AK		 2980 skip_emulated_instruction(vcpu);
2981 return 1;
2982 case 3:
229456fc 2983 kvm_set_cr3(vcpu, val);
6aa8b732
AK		 2984 skip_emulated_instruction(vcpu);
2985 return 1;
2986 case 4:
229456fc 2987 kvm_set_cr4(vcpu, val);
6aa8b732
AK		 2988 skip_emulated_instruction(vcpu);
2989 return 1;
0a5fff19
GN		 2990 case 8: {
2991 u8 cr8_prev = kvm_get_cr8(vcpu);
2992 u8 cr8 = kvm_register_read(vcpu, reg);
2993 kvm_set_cr8(vcpu, cr8);
2994 skip_emulated_instruction(vcpu);
2995 if (irqchip_in_kernel(vcpu->kvm))
2996 return 1;
2997 if (cr8_prev <= cr8)
2998 return 1;
851ba692 2999 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 3000 return 0;
3001 }
6aa8b732
AK		 3002 };
3003 break;
25c4c276 3004 case 2: /* clts */
edcafe3c 3005 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4d4ec087 3006 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
25c4c276 3007 skip_emulated_instruction(vcpu);
6b52d186 3008 vmx_fpu_activate(vcpu);
25c4c276 3009 return 1;
6aa8b732
AK		 3010 case 1: /*mov from cr*/
3011 switch (cr) {
3012 case 3:
5fdbf976 3013 kvm_register_write(vcpu, reg, vcpu->arch.cr3);
229456fc 3014 trace_kvm_cr_read(cr, vcpu->arch.cr3);
6aa8b732
AK		 3015 skip_emulated_instruction(vcpu);
3016 return 1;
3017 case 8:
229456fc
MT		 3018 val = kvm_get_cr8(vcpu);
3019 kvm_register_write(vcpu, reg, val);
3020 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 3021 skip_emulated_instruction(vcpu);
3022 return 1;
3023 }
3024 break;
3025 case 3: /* lmsw */
a1f83a74 3026 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 3027 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 3028 kvm_lmsw(vcpu, val);
6aa8b732
AK		 3029
3030 skip_emulated_instruction(vcpu);
3031 return 1;
3032 default:
3033 break;
3034 }
851ba692 3035 vcpu->run->exit_reason = 0;
f0242478 3036 pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 3037 (int)(exit_qualification >> 4) & 3, cr);
3038 return 0;
3039}
3040
138ac8d8
JK		 3041static int check_dr_alias(struct kvm_vcpu *vcpu)
3042{
3043 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE)) {
3044 kvm_queue_exception(vcpu, UD_VECTOR);
3045 return -1;
3046 }
3047 return 0;
3048}
3049
851ba692 3050static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 3051{
bfdaab09 3052 unsigned long exit_qualification;
6aa8b732
AK		 3053 unsigned long val;
3054 int dr, reg;
3055
f2483415 3056 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK		 3057 if (!kvm_require_cpl(vcpu, 0))
3058 return 1;
42dbaa5a
JK		 3059 dr = vmcs_readl(GUEST_DR7);
3060 if (dr & DR7_GD) {
3061 /*
3062 * As the vm-exit takes precedence over the debug trap, we
3063 * need to emulate the latter, either for the host or the
3064 * guest debugging itself.
3065 */
3066 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692
AK		 3067 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
3068 vcpu->run->debug.arch.dr7 = dr;
3069 vcpu->run->debug.arch.pc =
42dbaa5a
JK		 3070 vmcs_readl(GUEST_CS_BASE) +
3071 vmcs_readl(GUEST_RIP);
851ba692
AK		 3072 vcpu->run->debug.arch.exception = DB_VECTOR;
3073 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 3074 return 0;
3075 } else {
3076 vcpu->arch.dr7 &= ~DR7_GD;
3077 vcpu->arch.dr6 |= DR6_BD;
3078 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
3079 kvm_queue_exception(vcpu, DB_VECTOR);
3080 return 1;
3081 }
3082 }
3083
bfdaab09 3084 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
42dbaa5a
JK		 3085 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
3086 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
3087 if (exit_qualification & TYPE_MOV_FROM_DR) {
6aa8b732 3088 switch (dr) {
42dbaa5a
JK		 3089 case 0 ... 3:
3090 val = vcpu->arch.db[dr];
3091 break;
138ac8d8
JK		 3092 case 4:
3093 if (check_dr_alias(vcpu) < 0)
3094 return 1;
3095 /* fall through */
6aa8b732 3096 case 6:
42dbaa5a 3097 val = vcpu->arch.dr6;
6aa8b732 3098 break;
138ac8d8
JK		 3099 case 5:
3100 if (check_dr_alias(vcpu) < 0)
3101 return 1;
3102 /* fall through */
3103 default: /* 7 */
42dbaa5a 3104 val = vcpu->arch.dr7;
6aa8b732 3105 break;
6aa8b732 3106 }
5fdbf976 3107 kvm_register_write(vcpu, reg, val);
6aa8b732 3108 } else {
42dbaa5a
JK		 3109 val = vcpu->arch.regs[reg];
3110 switch (dr) {
3111 case 0 ... 3:
3112 vcpu->arch.db[dr] = val;
3113 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
3114 vcpu->arch.eff_db[dr] = val;
3115 break;
138ac8d8
JK		 3116 case 4:
3117 if (check_dr_alias(vcpu) < 0)
f2483415 3118 return 1;
138ac8d8 3119 /* fall through */
42dbaa5a
JK		 3120 case 6:
3121 if (val & 0xffffffff00000000ULL) {
f2483415
JK		 3122 kvm_inject_gp(vcpu, 0);
3123 return 1;
42dbaa5a
JK		 3124 }
3125 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
3126 break;
138ac8d8
JK		 3127 case 5:
3128 if (check_dr_alias(vcpu) < 0)
3129 return 1;
3130 /* fall through */
3131 default: /* 7 */
42dbaa5a 3132 if (val & 0xffffffff00000000ULL) {
f2483415
JK		 3133 kvm_inject_gp(vcpu, 0);
3134 return 1;
42dbaa5a
JK		 3135 }
3136 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
3137 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
3138 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
3139 vcpu->arch.switch_db_regs =
3140 (val & DR7_BP_EN_MASK);
3141 }
3142 break;
3143 }
6aa8b732 3144 }
6aa8b732
AK		 3145 skip_emulated_instruction(vcpu);
3146 return 1;
3147}
3148
851ba692 3149static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 3150{
06465c5a
AK		 3151 kvm_emulate_cpuid(vcpu);
3152 return 1;
6aa8b732
AK		 3153}
3154
851ba692 3155static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 3156{
ad312c7c 3157 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 3158 u64 data;
3159
3160 if (vmx_get_msr(vcpu, ecx, &data)) {
c1a5d4f9 3161 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 3162 return 1;
3163 }
3164
229456fc 3165 trace_kvm_msr_read(ecx, data);
2714d1d3 3166
6aa8b732 3167 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 3168 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
3169 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 3170 skip_emulated_instruction(vcpu);
3171 return 1;
3172}
3173
851ba692 3174static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 3175{
ad312c7c
ZX		 3176 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3177 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
3178 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732 3179
229456fc 3180 trace_kvm_msr_write(ecx, data);
2714d1d3 3181
6aa8b732 3182 if (vmx_set_msr(vcpu, ecx, data) != 0) {
c1a5d4f9 3183 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 3184 return 1;
3185 }
3186
3187 skip_emulated_instruction(vcpu);
3188 return 1;
3189}
3190
851ba692 3191static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c
YS		 3192{
3193 return 1;
3194}
3195
851ba692 3196static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 3197{
85f455f7
ED		 3198 u32 cpu_based_vm_exec_control;
3199
3200 /* clear pending irq */
3201 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3202 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
3203 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3 3204
a26bf12a 3205 ++vcpu->stat.irq_window_exits;
2714d1d3 3206
c1150d8c
DL		 3207 /*
3208 * If the user space waits to inject interrupts, exit as soon as
3209 * possible
3210 */
8061823a 3211 if (!irqchip_in_kernel(vcpu->kvm) &&
851ba692 3212 vcpu->run->request_interrupt_window &&
8061823a 3213 !kvm_cpu_has_interrupt(vcpu)) {
851ba692 3214 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
c1150d8c
DL		 3215 return 0;
3216 }
6aa8b732
AK		 3217 return 1;
3218}
3219
851ba692 3220static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732
AK		 3221{
3222 skip_emulated_instruction(vcpu);
d3bef15f 3223 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 3224}
3225
851ba692 3226static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 3227{
510043da 3228 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 3229 kvm_emulate_hypercall(vcpu);
3230 return 1;
c21415e8
IM		 3231}
3232
851ba692 3233static int handle_vmx_insn(struct kvm_vcpu *vcpu)
e3c7cb6a
AK		 3234{
3235 kvm_queue_exception(vcpu, UD_VECTOR);
3236 return 1;
3237}
3238
851ba692 3239static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 3240{
f9c617f6 3241 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 3242
3243 kvm_mmu_invlpg(vcpu, exit_qualification);
3244 skip_emulated_instruction(vcpu);
3245 return 1;
3246}
3247
851ba692 3248static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01
ED		 3249{
3250 skip_emulated_instruction(vcpu);
3251 /* TODO: Add support for VT-d/pass-through device */
3252 return 1;
3253}
3254
851ba692 3255static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 3256{
f9c617f6 3257 unsigned long exit_qualification;
f78e0e2e
SY		 3258 enum emulation_result er;
3259 unsigned long offset;
3260
f9c617f6 3261 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
f78e0e2e
SY		 3262 offset = exit_qualification & 0xffful;
3263
851ba692 3264 er = emulate_instruction(vcpu, 0, 0, 0);
f78e0e2e
SY		 3265
3266 if (er != EMULATE_DONE) {
3267 printk(KERN_ERR
3268 "Fail to handle apic access vmexit! Offset is 0x%lx\n",
3269 offset);
7f582ab6 3270 return -ENOEXEC;
f78e0e2e
SY		 3271 }
3272 return 1;
3273}
3274
851ba692 3275static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 3276{
60637aac 3277 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29
IE		 3278 unsigned long exit_qualification;
3279 u16 tss_selector;
64a7ec06
GN		 3280 int reason, type, idt_v;
3281
3282 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
3283 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 3284
3285 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3286
3287 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 3288 if (reason == TASK_SWITCH_GATE && idt_v) {
3289 switch (type) {
3290 case INTR_TYPE_NMI_INTR:
3291 vcpu->arch.nmi_injected = false;
3292 if (cpu_has_virtual_nmis())
3293 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3294 GUEST_INTR_STATE_NMI);
3295 break;
3296 case INTR_TYPE_EXT_INTR:
66fd3f7f 3297 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 3298 kvm_clear_interrupt_queue(vcpu);
3299 break;
3300 case INTR_TYPE_HARD_EXCEPTION:
3301 case INTR_TYPE_SOFT_EXCEPTION:
3302 kvm_clear_exception_queue(vcpu);
3303 break;
3304 default:
3305 break;
3306 }
60637aac 3307 }
37817f29
IE		 3308 tss_selector = exit_qualification;
3309
64a7ec06
GN		 3310 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
3311 type != INTR_TYPE_EXT_INTR &&
3312 type != INTR_TYPE_NMI_INTR))
3313 skip_emulated_instruction(vcpu);
3314
42dbaa5a
JK		 3315 if (!kvm_task_switch(vcpu, tss_selector, reason))
3316 return 0;
3317
3318 /* clear all local breakpoint enable flags */
3319 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
3320
3321 /*
3322 * TODO: What about debug traps on tss switch?
3323 * Are we supposed to inject them and update dr6?
3324 */
3325
3326 return 1;
37817f29
IE		 3327}
3328
851ba692 3329static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 3330{
f9c617f6 3331 unsigned long exit_qualification;
1439442c 3332 gpa_t gpa;
1439442c 3333 int gla_validity;
1439442c 3334
f9c617f6 3335 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c
SY		 3336
3337 if (exit_qualification & (1 << 6)) {
3338 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
7f582ab6 3339 return -EINVAL;
1439442c
SY		 3340 }
3341
3342 gla_validity = (exit_qualification >> 7) & 0x3;
3343 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
3344 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
3345 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3346 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 3347 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 3348 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
3349 (long unsigned int)exit_qualification);
851ba692
AK		 3350 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3351 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
596ae895 3352 return 0;
1439442c
SY		 3353 }
3354
3355 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 3356 trace_kvm_page_fault(gpa, exit_qualification);
49cd7d22 3357 return kvm_mmu_page_fault(vcpu, gpa & PAGE_MASK, 0);
1439442c
SY		 3358}
3359
68f89400
MT		 3360static u64 ept_rsvd_mask(u64 spte, int level)
3361{
3362 int i;
3363 u64 mask = 0;
3364
3365 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
3366 mask |= (1ULL << i);
3367
3368 if (level > 2)
3369 /* bits 7:3 reserved */
3370 mask |= 0xf8;
3371 else if (level == 2) {
3372 if (spte & (1ULL << 7))
3373 /* 2MB ref, bits 20:12 reserved */
3374 mask |= 0x1ff000;
3375 else
3376 /* bits 6:3 reserved */
3377 mask |= 0x78;
3378 }
3379
3380 return mask;
3381}
3382
3383static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
3384 int level)
3385{
3386 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
3387
3388 /* 010b (write-only) */
3389 WARN_ON((spte & 0x7) == 0x2);
3390
3391 /* 110b (write/execute) */
3392 WARN_ON((spte & 0x7) == 0x6);
3393
3394 /* 100b (execute-only) and value not supported by logical processor */
3395 if (!cpu_has_vmx_ept_execute_only())
3396 WARN_ON((spte & 0x7) == 0x4);
3397
3398 /* not 000b */
3399 if ((spte & 0x7)) {
3400 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
3401
3402 if (rsvd_bits != 0) {
3403 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
3404 __func__, rsvd_bits);
3405 WARN_ON(1);
3406 }
3407
3408 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
3409 u64 ept_mem_type = (spte & 0x38) >> 3;
3410
3411 if (ept_mem_type == 2 || ept_mem_type == 3 ||
3412 ept_mem_type == 7) {
3413 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
3414 __func__, ept_mem_type);
3415 WARN_ON(1);
3416 }
3417 }
3418 }
3419}
3420
851ba692 3421static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400
MT		 3422{
3423 u64 sptes[4];
3424 int nr_sptes, i;
3425 gpa_t gpa;
3426
3427 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3428
3429 printk(KERN_ERR "EPT: Misconfiguration.\n");
3430 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
3431
3432 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
3433
3434 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
3435 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
3436
851ba692
AK		 3437 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3438 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT		 3439
3440 return 0;
3441}
3442
851ba692 3443static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4
SY		 3444{
3445 u32 cpu_based_vm_exec_control;
3446
3447 /* clear pending NMI */
3448 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3449 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
3450 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3451 ++vcpu->stat.nmi_window_exits;
3452
3453 return 1;
3454}
3455
80ced186 3456static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 3457{
8b3079a5
AK		 3458 struct vcpu_vmx *vmx = to_vmx(vcpu);
3459 enum emulation_result err = EMULATE_DONE;
80ced186 3460 int ret = 1;
ea953ef0
MG		 3461
3462 while (!guest_state_valid(vcpu)) {
851ba692 3463 err = emulate_instruction(vcpu, 0, 0, 0);
ea953ef0 3464
80ced186
MG		 3465 if (err == EMULATE_DO_MMIO) {
3466 ret = 0;
3467 goto out;
3468 }
1d5a4d9b
GT		 3469
3470 if (err != EMULATE_DONE) {
80ced186
MG		 3471 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3472 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
a9c7399d 3473 vcpu->run->internal.ndata = 0;
80ced186
MG		 3474 ret = 0;
3475 goto out;
ea953ef0
MG		 3476 }
3477
3478 if (signal_pending(current))
80ced186 3479 goto out;
ea953ef0
MG		 3480 if (need_resched())
3481 schedule();
3482 }
3483
80ced186
MG		 3484 vmx->emulation_required = 0;
3485out:
3486 return ret;
ea953ef0
MG		 3487}
3488
4b8d54f9
ZE		 3489/*
3490 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
3491 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
3492 */
9fb41ba8 3493static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9
ZE		 3494{
3495 skip_emulated_instruction(vcpu);
3496 kvm_vcpu_on_spin(vcpu);
3497
3498 return 1;
3499}
3500
59708670
SY		 3501static int handle_invalid_op(struct kvm_vcpu *vcpu)
3502{
3503 kvm_queue_exception(vcpu, UD_VECTOR);
3504 return 1;
3505}
3506
6aa8b732
AK		 3507/*
3508 * The exit handlers return 1 if the exit was handled fully and guest execution
3509 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
3510 * to be done to userspace and return 0.
3511 */
851ba692 3512static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK		 3513 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
3514 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 3515 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 3516 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 3517 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 3518 [EXIT_REASON_CR_ACCESS] = handle_cr,
3519 [EXIT_REASON_DR_ACCESS] = handle_dr,
3520 [EXIT_REASON_CPUID] = handle_cpuid,
3521 [EXIT_REASON_MSR_READ] = handle_rdmsr,
3522 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
3523 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
3524 [EXIT_REASON_HLT] = handle_halt,
a7052897 3525 [EXIT_REASON_INVLPG] = handle_invlpg,
c21415e8 3526 [EXIT_REASON_VMCALL] = handle_vmcall,
e3c7cb6a
AK		 3527 [EXIT_REASON_VMCLEAR] = handle_vmx_insn,
3528 [EXIT_REASON_VMLAUNCH] = handle_vmx_insn,
3529 [EXIT_REASON_VMPTRLD] = handle_vmx_insn,
3530 [EXIT_REASON_VMPTRST] = handle_vmx_insn,
3531 [EXIT_REASON_VMREAD] = handle_vmx_insn,
3532 [EXIT_REASON_VMRESUME] = handle_vmx_insn,
3533 [EXIT_REASON_VMWRITE] = handle_vmx_insn,
3534 [EXIT_REASON_VMOFF] = handle_vmx_insn,
3535 [EXIT_REASON_VMON] = handle_vmx_insn,
f78e0e2e
SY		 3536 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
3537 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
e5edaa01 3538 [EXIT_REASON_WBINVD] = handle_wbinvd,
37817f29 3539 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 3540 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT		 3541 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
3542 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 3543 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
59708670
SY		 3544 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op,
3545 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op,
6aa8b732
AK		 3546};
3547
3548static const int kvm_vmx_max_exit_handlers =
50a3485c 3549 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732
AK		 3550
3551/*
3552 * The guest has exited. See if we can fix it or if we need userspace
3553 * assistance.
3554 */
851ba692 3555static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 3556{
29bd8a78 3557 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 3558 u32 exit_reason = vmx->exit_reason;
1155f76a 3559 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 3560
229456fc 3561 trace_kvm_exit(exit_reason, kvm_rip_read(vcpu));
2714d1d3 3562
80ced186
MG		 3563 /* If guest state is invalid, start emulating */
3564 if (vmx->emulation_required && emulate_invalid_guest_state)
3565 return handle_invalid_guest_state(vcpu);
1d5a4d9b 3566
1439442c
SY		 3567 /* Access CR3 don't cause VMExit in paging mode, so we need
3568 * to sync with guest real CR3. */
6de4f3ad 3569 if (enable_ept && is_paging(vcpu))
1439442c 3570 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
1439442c 3571
29bd8a78 3572 if (unlikely(vmx->fail)) {
851ba692
AK		 3573 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3574 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK		 3575 = vmcs_read32(VM_INSTRUCTION_ERROR);
3576 return 0;
3577 }
6aa8b732 3578
d77c26fc 3579 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 3580 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac
JK		 3581 exit_reason != EXIT_REASON_EPT_VIOLATION &&
3582 exit_reason != EXIT_REASON_TASK_SWITCH))
3583 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
3584 "(0x%x) and exit reason is 0x%x\n",
3585 __func__, vectoring_info, exit_reason);
3b86cd99
JK		 3586
3587 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) {
c4282df9 3588 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 3589 vmx->soft_vnmi_blocked = 0;
3b86cd99 3590 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 3591 vcpu->arch.nmi_pending) {
3b86cd99
JK		 3592 /*
3593 * This CPU don't support us in finding the end of an
3594 * NMI-blocked window if the guest runs with IRQs
3595 * disabled. So we pull the trigger after 1 s of
3596 * futile waiting, but inform the user about this.
3597 */
3598 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
3599 "state on VCPU %d after 1 s timeout\n",
3600 __func__, vcpu->vcpu_id);
3601 vmx->soft_vnmi_blocked = 0;
3b86cd99 3602 }
3b86cd99
JK		 3603 }
3604
6aa8b732
AK		 3605 if (exit_reason < kvm_vmx_max_exit_handlers
3606 && kvm_vmx_exit_handlers[exit_reason])
851ba692 3607 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 3608 else {
851ba692
AK		 3609 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3610 vcpu->run->hw.hardware_exit_reason = exit_reason;
6aa8b732
AK		 3611 }
3612 return 0;
3613}
3614
95ba8273 3615static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 3616{
95ba8273 3617 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 3618 vmcs_write32(TPR_THRESHOLD, 0);
3619 return;
3620 }
3621
95ba8273 3622 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 3623}
3624
cf393f75
AK		 3625static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
3626{
3627 u32 exit_intr_info;
7b4a25cb 3628 u32 idt_vectoring_info = vmx->idt_vectoring_info;
cf393f75
AK		 3629 bool unblock_nmi;
3630 u8 vector;
668f612f
AK		 3631 int type;
3632 bool idtv_info_valid;
cf393f75
AK		 3633
3634 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
20f65983 3635
a0861c02
AK		 3636 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
3637
3638 /* Handle machine checks before interrupts are enabled */
3639 if ((vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY)
3640 || (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI
3641 && is_machine_check(exit_intr_info)))
3642 kvm_machine_check();
3643
20f65983
GN		 3644 /* We need to handle NMIs before interrupts are enabled */
3645 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
229456fc 3646 (exit_intr_info & INTR_INFO_VALID_MASK))
20f65983 3647 asm("int $2");
20f65983
GN		 3648
3649 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
3650
cf393f75
AK		 3651 if (cpu_has_virtual_nmis()) {
3652 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
3653 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
3654 /*
7b4a25cb 3655 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 3656 * Re-set bit "block by NMI" before VM entry if vmexit caused by
3657 * a guest IRET fault.
7b4a25cb
GN		 3658 * SDM 3: 23.2.2 (September 2008)
3659 * Bit 12 is undefined in any of the following cases:
3660 * If the VM exit sets the valid bit in the IDT-vectoring
3661 * information field.
3662 * If the VM exit is due to a double fault.
cf393f75 3663 */
7b4a25cb
GN		 3664 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
3665 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 3666 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3667 GUEST_INTR_STATE_NMI);
3b86cd99
JK		 3668 } else if (unlikely(vmx->soft_vnmi_blocked))
3669 vmx->vnmi_blocked_time +=
3670 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
668f612f 3671
37b96e98
GN		 3672 vmx->vcpu.arch.nmi_injected = false;
3673 kvm_clear_exception_queue(&vmx->vcpu);
3674 kvm_clear_interrupt_queue(&vmx->vcpu);
3675
3676 if (!idtv_info_valid)
3677 return;
3678
668f612f
AK		 3679 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
3680 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 3681
64a7ec06 3682 switch (type) {
37b96e98
GN		 3683 case INTR_TYPE_NMI_INTR:
3684 vmx->vcpu.arch.nmi_injected = true;
668f612f 3685 /*
7b4a25cb 3686 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 3687 * Clear bit "block by NMI" before VM entry if a NMI
3688 * delivery faulted.
668f612f 3689 */
37b96e98
GN		 3690 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3691 GUEST_INTR_STATE_NMI);
3692 break;
37b96e98 3693 case INTR_TYPE_SOFT_EXCEPTION:
66fd3f7f
GN		 3694 vmx->vcpu.arch.event_exit_inst_len =
3695 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3696 /* fall through */
3697 case INTR_TYPE_HARD_EXCEPTION:
35920a35 3698 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
37b96e98
GN		 3699 u32 err = vmcs_read32(IDT_VECTORING_ERROR_CODE);
3700 kvm_queue_exception_e(&vmx->vcpu, vector, err);
35920a35
AK		 3701 } else
3702 kvm_queue_exception(&vmx->vcpu, vector);
37b96e98 3703 break;
66fd3f7f
GN		 3704 case INTR_TYPE_SOFT_INTR:
3705 vmx->vcpu.arch.event_exit_inst_len =
3706 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3707 /* fall through */
37b96e98 3708 case INTR_TYPE_EXT_INTR:
66fd3f7f
GN		 3709 kvm_queue_interrupt(&vmx->vcpu, vector,
3710 type == INTR_TYPE_SOFT_INTR);
37b96e98
GN		 3711 break;
3712 default:
3713 break;
f7d9238f 3714 }
cf393f75
AK		 3715}
3716
9c8cba37
AK		 3717/*
3718 * Failure to inject an interrupt should give us the information
3719 * in IDT_VECTORING_INFO_FIELD. However, if the failure occurs
3720 * when fetching the interrupt redirection bitmap in the real-mode
3721 * tss, this doesn't happen. So we do it ourselves.
3722 */
3723static void fixup_rmode_irq(struct vcpu_vmx *vmx)
3724{
3725 vmx->rmode.irq.pending = 0;
5fdbf976 3726 if (kvm_rip_read(&vmx->vcpu) + 1 != vmx->rmode.irq.rip)
9c8cba37 3727 return;
5fdbf976 3728 kvm_rip_write(&vmx->vcpu, vmx->rmode.irq.rip);
9c8cba37
AK		 3729 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
3730 vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK;
3731 vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR;
3732 return;
3733 }
3734 vmx->idt_vectoring_info =
3735 VECTORING_INFO_VALID_MASK
3736 | INTR_TYPE_EXT_INTR
3737 | vmx->rmode.irq.vector;
3738}
3739
c801949d
AK		 3740#ifdef CONFIG_X86_64
3741#define R "r"
3742#define Q "q"
3743#else
3744#define R "e"
3745#define Q "l"
3746#endif
3747
851ba692 3748static void vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 3749{
a2fa3e9f 3750 struct vcpu_vmx *vmx = to_vmx(vcpu);
e6adf283 3751
3b86cd99
JK		 3752 /* Record the guest's net vcpu time for enforced NMI injections. */
3753 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
3754 vmx->entry_time = ktime_get();
3755
80ced186
MG		 3756 /* Don't enter VMX if guest state is invalid, let the exit handler
3757 start emulation until we arrive back to a valid state */
3758 if (vmx->emulation_required && emulate_invalid_guest_state)
a89a8fb9 3759 return;
a89a8fb9 3760
5fdbf976
MT		 3761 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
3762 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
3763 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
3764 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
3765
787ff736
GN		 3766 /* When single-stepping over STI and MOV SS, we must clear the
3767 * corresponding interruptibility bits in the guest state. Otherwise
3768 * vmentry fails as it then expects bit 14 (BS) in pending debug
3769 * exceptions being set, but that's not correct for the guest debugging
3770 * case. */
3771 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
3772 vmx_set_interrupt_shadow(vcpu, 0);
3773
e6adf283
AK		 3774 /*
3775 * Loading guest fpu may have cleared host cr0.ts
3776 */
3777 vmcs_writel(HOST_CR0, read_cr0());
3778
d77c26fc 3779 asm(
6aa8b732 3780 /* Store host registers */
c801949d
AK		 3781 "push %%"R"dx; push %%"R"bp;"
3782 "push %%"R"cx \n\t"
313dbd49
AK		 3783 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
3784 "je 1f \n\t"
3785 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
4ecac3fd 3786 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 3787 "1: \n\t"
d3edefc0
AK		 3788 /* Reload cr2 if changed */
3789 "mov %c[cr2](%0), %%"R"ax \n\t"
3790 "mov %%cr2, %%"R"dx \n\t"
3791 "cmp %%"R"ax, %%"R"dx \n\t"
3792 "je 2f \n\t"
3793 "mov %%"R"ax, %%cr2 \n\t"
3794 "2: \n\t"
6aa8b732 3795 /* Check if vmlaunch of vmresume is needed */
e08aa78a 3796 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 3797 /* Load guest registers. Don't clobber flags. */
c801949d
AK		 3798 "mov %c[rax](%0), %%"R"ax \n\t"
3799 "mov %c[rbx](%0), %%"R"bx \n\t"
3800 "mov %c[rdx](%0), %%"R"dx \n\t"
3801 "mov %c[rsi](%0), %%"R"si \n\t"
3802 "mov %c[rdi](%0), %%"R"di \n\t"
3803 "mov %c[rbp](%0), %%"R"bp \n\t"
05b3e0c2 3804#ifdef CONFIG_X86_64
e08aa78a
AK		 3805 "mov %c[r8](%0), %%r8 \n\t"
3806 "mov %c[r9](%0), %%r9 \n\t"
3807 "mov %c[r10](%0), %%r10 \n\t"
3808 "mov %c[r11](%0), %%r11 \n\t"
3809 "mov %c[r12](%0), %%r12 \n\t"
3810 "mov %c[r13](%0), %%r13 \n\t"
3811 "mov %c[r14](%0), %%r14 \n\t"
3812 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 3813#endif
c801949d
AK		 3814 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
3815
6aa8b732 3816 /* Enter guest mode */
cd2276a7 3817 "jne .Llaunched \n\t"
4ecac3fd 3818 __ex(ASM_VMX_VMLAUNCH) "\n\t"
cd2276a7 3819 "jmp .Lkvm_vmx_return \n\t"
4ecac3fd 3820 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
cd2276a7 3821 ".Lkvm_vmx_return: "
6aa8b732 3822 /* Save guest registers, load host registers, keep flags */
c801949d
AK		 3823 "xchg %0, (%%"R"sp) \n\t"
3824 "mov %%"R"ax, %c[rax](%0) \n\t"
3825 "mov %%"R"bx, %c[rbx](%0) \n\t"
3826 "push"Q" (%%"R"sp); pop"Q" %c[rcx](%0) \n\t"
3827 "mov %%"R"dx, %c[rdx](%0) \n\t"
3828 "mov %%"R"si, %c[rsi](%0) \n\t"
3829 "mov %%"R"di, %c[rdi](%0) \n\t"
3830 "mov %%"R"bp, %c[rbp](%0) \n\t"
05b3e0c2 3831#ifdef CONFIG_X86_64
e08aa78a
AK		 3832 "mov %%r8, %c[r8](%0) \n\t"
3833 "mov %%r9, %c[r9](%0) \n\t"
3834 "mov %%r10, %c[r10](%0) \n\t"
3835 "mov %%r11, %c[r11](%0) \n\t"
3836 "mov %%r12, %c[r12](%0) \n\t"
3837 "mov %%r13, %c[r13](%0) \n\t"
3838 "mov %%r14, %c[r14](%0) \n\t"
3839 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 3840#endif
c801949d
AK		 3841 "mov %%cr2, %%"R"ax \n\t"
3842 "mov %%"R"ax, %c[cr2](%0) \n\t"
3843
3844 "pop %%"R"bp; pop %%"R"bp; pop %%"R"dx \n\t"
e08aa78a
AK		 3845 "setbe %c[fail](%0) \n\t"
3846 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
3847 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
3848 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 3849 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 3850 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
3851 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
3852 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
3853 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
3854 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
3855 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
3856 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 3857#ifdef CONFIG_X86_64
ad312c7c
ZX		 3858 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
3859 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
3860 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
3861 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
3862 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
3863 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
3864 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
3865 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 3866#endif
ad312c7c 3867 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2))
c2036300 3868 : "cc", "memory"
c801949d 3869 , R"bx", R"di", R"si"
c2036300 3870#ifdef CONFIG_X86_64
c2036300
LV		 3871 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3872#endif
3873 );
6aa8b732 3874
6de4f3ad
AK		 3875 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
3876 | (1 << VCPU_EXREG_PDPTR));
5fdbf976
MT		 3877 vcpu->arch.regs_dirty = 0;
3878
1155f76a 3879 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
9c8cba37
AK		 3880 if (vmx->rmode.irq.pending)
3881 fixup_rmode_irq(vmx);
1155f76a 3882
d77c26fc 3883 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
15ad7146 3884 vmx->launched = 1;
1b6269db 3885
cf393f75 3886 vmx_complete_interrupts(vmx);
6aa8b732
AK		 3887}
3888
c801949d
AK		 3889#undef R
3890#undef Q
3891
6aa8b732
AK		 3892static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
3893{
a2fa3e9f
GH		 3894 struct vcpu_vmx *vmx = to_vmx(vcpu);
3895
3896 if (vmx->vmcs) {
543e4243 3897 vcpu_clear(vmx);
a2fa3e9f
GH		 3898 free_vmcs(vmx->vmcs);
3899 vmx->vmcs = NULL;
6aa8b732
AK		 3900 }
3901}
3902
3903static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
3904{
fb3f0f51
RR		 3905 struct vcpu_vmx *vmx = to_vmx(vcpu);
3906
2384d2b3
SY		 3907 spin_lock(&vmx_vpid_lock);
3908 if (vmx->vpid != 0)
3909 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3910 spin_unlock(&vmx_vpid_lock);
6aa8b732 3911 vmx_free_vmcs(vcpu);
fb3f0f51
RR		 3912 kfree(vmx->guest_msrs);
3913 kvm_vcpu_uninit(vcpu);
a4770347 3914 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 3915}
3916
fb3f0f51 3917static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 3918{
fb3f0f51 3919 int err;
c16f862d 3920 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 3921 int cpu;
6aa8b732 3922
a2fa3e9f 3923 if (!vmx)
fb3f0f51
RR		 3924 return ERR_PTR(-ENOMEM);
3925
2384d2b3
SY		 3926 allocate_vpid(vmx);
3927
fb3f0f51
RR		 3928 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
3929 if (err)
3930 goto free_vcpu;
965b58a5 3931
a2fa3e9f 3932 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
fb3f0f51
RR		 3933 if (!vmx->guest_msrs) {
3934 err = -ENOMEM;
3935 goto uninit_vcpu;
3936 }
965b58a5 3937
a2fa3e9f
GH		 3938 vmx->vmcs = alloc_vmcs();
3939 if (!vmx->vmcs)
fb3f0f51 3940 goto free_msrs;
a2fa3e9f
GH		 3941
3942 vmcs_clear(vmx->vmcs);
3943
15ad7146
AK		 3944 cpu = get_cpu();
3945 vmx_vcpu_load(&vmx->vcpu, cpu);
8b9cf98c 3946 err = vmx_vcpu_setup(vmx);
fb3f0f51 3947 vmx_vcpu_put(&vmx->vcpu);
15ad7146 3948 put_cpu();
fb3f0f51
RR		 3949 if (err)
3950 goto free_vmcs;
5e4a0b3c
MT		 3951 if (vm_need_virtualize_apic_accesses(kvm))
3952 if (alloc_apic_access_page(kvm) != 0)
3953 goto free_vmcs;
fb3f0f51 3954
b927a3ce
SY		 3955 if (enable_ept) {
3956 if (!kvm->arch.ept_identity_map_addr)
3957 kvm->arch.ept_identity_map_addr =
3958 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
b7ebfb05
SY		 3959 if (alloc_identity_pagetable(kvm) != 0)
3960 goto free_vmcs;
b927a3ce 3961 }
b7ebfb05 3962
fb3f0f51
RR		 3963 return &vmx->vcpu;
3964
3965free_vmcs:
3966 free_vmcs(vmx->vmcs);
3967free_msrs:
fb3f0f51
RR		 3968 kfree(vmx->guest_msrs);
3969uninit_vcpu:
3970 kvm_vcpu_uninit(&vmx->vcpu);
3971free_vcpu:
a4770347 3972 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 3973 return ERR_PTR(err);
6aa8b732
AK		 3974}
3975
002c7f7c
YS		 3976static void __init vmx_check_processor_compat(void *rtn)
3977{
3978 struct vmcs_config vmcs_conf;
3979
3980 *(int *)rtn = 0;
3981 if (setup_vmcs_config(&vmcs_conf) < 0)
3982 *(int *)rtn = -EIO;
3983 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
3984 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
3985 smp_processor_id());
3986 *(int *)rtn = -EIO;
3987 }
3988}
3989
67253af5
SY		 3990static int get_ept_level(void)
3991{
3992 return VMX_EPT_DEFAULT_GAW + 1;
3993}
3994
4b12f0de 3995static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 3996{
4b12f0de
SY		 3997 u64 ret;
3998
522c68c4
SY		 3999 /* For VT-d and EPT combination
4000 * 1. MMIO: always map as UC
4001 * 2. EPT with VT-d:
4002 * a. VT-d without snooping control feature: can't guarantee the
4003 * result, try to trust guest.
4004 * b. VT-d with snooping control feature: snooping control feature of
4005 * VT-d engine can guarantee the cache correctness. Just set it
4006 * to WB to keep consistent with host. So the same as item 3.
4007 * 3. EPT without VT-d: always map as WB and set IGMT=1 to keep
4008 * consistent with host MTRR
4009 */
4b12f0de
SY		 4010 if (is_mmio)
4011 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
522c68c4
SY		 4012 else if (vcpu->kvm->arch.iommu_domain &&
4013 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
4014 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
4015 VMX_EPT_MT_EPTE_SHIFT;
4b12f0de 4016 else
522c68c4
SY		 4017 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
4018 | VMX_EPT_IGMT_BIT;
4b12f0de
SY		 4019
4020 return ret;
64d4d521
SY		 4021}
4022
f4c9e87c
AK		 4023#define _ER(x) { EXIT_REASON_##x, #x }
4024
229456fc 4025static const struct trace_print_flags vmx_exit_reasons_str[] = {
f4c9e87c
AK		 4026 _ER(EXCEPTION_NMI),
4027 _ER(EXTERNAL_INTERRUPT),
4028 _ER(TRIPLE_FAULT),
4029 _ER(PENDING_INTERRUPT),
4030 _ER(NMI_WINDOW),
4031 _ER(TASK_SWITCH),
4032 _ER(CPUID),
4033 _ER(HLT),
4034 _ER(INVLPG),
4035 _ER(RDPMC),
4036 _ER(RDTSC),
4037 _ER(VMCALL),
4038 _ER(VMCLEAR),
4039 _ER(VMLAUNCH),
4040 _ER(VMPTRLD),
4041 _ER(VMPTRST),
4042 _ER(VMREAD),
4043 _ER(VMRESUME),
4044 _ER(VMWRITE),
4045 _ER(VMOFF),
4046 _ER(VMON),
4047 _ER(CR_ACCESS),
4048 _ER(DR_ACCESS),
4049 _ER(IO_INSTRUCTION),
4050 _ER(MSR_READ),
4051 _ER(MSR_WRITE),
4052 _ER(MWAIT_INSTRUCTION),
4053 _ER(MONITOR_INSTRUCTION),
4054 _ER(PAUSE_INSTRUCTION),
4055 _ER(MCE_DURING_VMENTRY),
4056 _ER(TPR_BELOW_THRESHOLD),
4057 _ER(APIC_ACCESS),
4058 _ER(EPT_VIOLATION),
4059 _ER(EPT_MISCONFIG),
4060 _ER(WBINVD),
229456fc
MT		 4061 { -1, NULL }
4062};
4063
f4c9e87c
AK		 4064#undef _ER
4065
17cc3935 4066static int vmx_get_lpage_level(void)
344f414f 4067{
878403b7
SY		 4068 if (enable_ept && !cpu_has_vmx_ept_1g_page())
4069 return PT_DIRECTORY_LEVEL;
4070 else
4071 /* For shadow and EPT supported 1GB page */
4072 return PT_PDPE_LEVEL;
344f414f
JR		 4073}
4074
4e47c7a6
SY		 4075static inline u32 bit(int bitno)
4076{
4077 return 1 << (bitno & 31);
4078}
4079
0e851880
SY		 4080static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
4081{
4e47c7a6
SY		 4082 struct kvm_cpuid_entry2 *best;
4083 struct vcpu_vmx *vmx = to_vmx(vcpu);
4084 u32 exec_control;
4085
4086 vmx->rdtscp_enabled = false;
4087 if (vmx_rdtscp_supported()) {
4088 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
4089 if (exec_control & SECONDARY_EXEC_RDTSCP) {
4090 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
4091 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
4092 vmx->rdtscp_enabled = true;
4093 else {
4094 exec_control &= ~SECONDARY_EXEC_RDTSCP;
4095 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4096 exec_control);
4097 }
4098 }
4099 }
0e851880
SY		 4100}
4101
cbdd1bea 4102static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 4103 .cpu_has_kvm_support = cpu_has_kvm_support,
4104 .disabled_by_bios = vmx_disabled_by_bios,
4105 .hardware_setup = hardware_setup,
4106 .hardware_unsetup = hardware_unsetup,
002c7f7c 4107 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 4108 .hardware_enable = hardware_enable,
4109 .hardware_disable = hardware_disable,
04547156 4110 .cpu_has_accelerated_tpr = report_flexpriority,
6aa8b732
AK		 4111
4112 .vcpu_create = vmx_create_vcpu,
4113 .vcpu_free = vmx_free_vcpu,
04d2cc77 4114 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 4115
04d2cc77 4116 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 4117 .vcpu_load = vmx_vcpu_load,
4118 .vcpu_put = vmx_vcpu_put,
4119
4120 .set_guest_debug = set_guest_debug,
4121 .get_msr = vmx_get_msr,
4122 .set_msr = vmx_set_msr,
4123 .get_segment_base = vmx_get_segment_base,
4124 .get_segment = vmx_get_segment,
4125 .set_segment = vmx_set_segment,
2e4d2653 4126 .get_cpl = vmx_get_cpl,
6aa8b732 4127 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 4128 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
25c4c276 4129 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 4130 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 4131 .set_cr3 = vmx_set_cr3,
4132 .set_cr4 = vmx_set_cr4,
6aa8b732 4133 .set_efer = vmx_set_efer,
6aa8b732
AK		 4134 .get_idt = vmx_get_idt,
4135 .set_idt = vmx_set_idt,
4136 .get_gdt = vmx_get_gdt,
4137 .set_gdt = vmx_set_gdt,
5fdbf976 4138 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 4139 .get_rflags = vmx_get_rflags,
4140 .set_rflags = vmx_set_rflags,
02daab21 4141 .fpu_deactivate = vmx_fpu_deactivate,
6aa8b732
AK		 4142
4143 .tlb_flush = vmx_flush_tlb,
6aa8b732 4144
6aa8b732 4145 .run = vmx_vcpu_run,
6062d012 4146 .handle_exit = vmx_handle_exit,
6aa8b732 4147 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 4148 .set_interrupt_shadow = vmx_set_interrupt_shadow,
4149 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 4150 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 4151 .set_irq = vmx_inject_irq,
95ba8273 4152 .set_nmi = vmx_inject_nmi,
298101da 4153 .queue_exception = vmx_queue_exception,
78646121 4154 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 4155 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 4156 .get_nmi_mask = vmx_get_nmi_mask,
4157 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 4158 .enable_nmi_window = enable_nmi_window,
4159 .enable_irq_window = enable_irq_window,
4160 .update_cr8_intercept = update_cr8_intercept,
95ba8273 4161
cbc94022 4162 .set_tss_addr = vmx_set_tss_addr,
67253af5 4163 .get_tdp_level = get_ept_level,
4b12f0de 4164 .get_mt_mask = vmx_get_mt_mask,
229456fc
MT		 4165
4166 .exit_reasons_str = vmx_exit_reasons_str,
17cc3935 4167 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY		 4168
4169 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY		 4170
4171 .rdtscp_supported = vmx_rdtscp_supported,
6aa8b732
AK		 4172};
4173
4174static int __init vmx_init(void)
4175{
26bb0981
AK		 4176 int r, i;
4177
4178 rdmsrl_safe(MSR_EFER, &host_efer);
4179
4180 for (i = 0; i < NR_VMX_MSR; ++i)
4181 kvm_define_shared_msr(i, vmx_msr_index[i]);
fdef3ad1 4182
3e7c73e9 4183 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 4184 if (!vmx_io_bitmap_a)
4185 return -ENOMEM;
4186
3e7c73e9 4187 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 4188 if (!vmx_io_bitmap_b) {
4189 r = -ENOMEM;
4190 goto out;
4191 }
4192
5897297b
AK		 4193 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
4194 if (!vmx_msr_bitmap_legacy) {
25c5f225
SY		 4195 r = -ENOMEM;
4196 goto out1;
4197 }
4198
5897297b
AK		 4199 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
4200 if (!vmx_msr_bitmap_longmode) {
4201 r = -ENOMEM;
4202 goto out2;
4203 }
4204
fdef3ad1
HQ		 4205 /*
4206 * Allow direct access to the PC debug port (it is often used for I/O
4207 * delays, but the vmexits simply slow things down).
4208 */
3e7c73e9
AK		 4209 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
4210 clear_bit(0x80, vmx_io_bitmap_a);
fdef3ad1 4211
3e7c73e9 4212 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
fdef3ad1 4213
5897297b
AK		 4214 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
4215 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
25c5f225 4216
2384d2b3
SY		 4217 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
4218
cb498ea2 4219 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 4220 if (r)
5897297b 4221 goto out3;
25c5f225 4222
5897297b
AK		 4223 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
4224 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
4225 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
4226 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
4227 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
4228 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
fdef3ad1 4229
089d034e 4230 if (enable_ept) {
1439442c 4231 bypass_guest_pf = 0;
5fdbcb9d 4232 kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK |
2aaf69dc 4233 VMX_EPT_WRITABLE_MASK);
534e38b4 4234 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
4b12f0de 4235 VMX_EPT_EXECUTABLE_MASK);
5fdbcb9d
SY		 4236 kvm_enable_tdp();
4237 } else
4238 kvm_disable_tdp();
1439442c 4239
c7addb90
AK		 4240 if (bypass_guest_pf)
4241 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
4242
fdef3ad1
HQ		 4243 return 0;
4244
5897297b
AK		 4245out3:
4246 free_page((unsigned long)vmx_msr_bitmap_longmode);
25c5f225 4247out2:
5897297b 4248 free_page((unsigned long)vmx_msr_bitmap_legacy);
fdef3ad1 4249out1:
3e7c73e9 4250 free_page((unsigned long)vmx_io_bitmap_b);
fdef3ad1 4251out:
3e7c73e9 4252 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 4253 return r;
6aa8b732
AK		 4254}
4255
4256static void __exit vmx_exit(void)
4257{
5897297b
AK		 4258 free_page((unsigned long)vmx_msr_bitmap_legacy);
4259 free_page((unsigned long)vmx_msr_bitmap_longmode);
3e7c73e9
AK		 4260 free_page((unsigned long)vmx_io_bitmap_b);
4261 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 4262
cb498ea2 4263 kvm_exit();
6aa8b732
AK		 4264}
4265
4266module_init(vmx_init)
4267module_exit(vmx_exit)
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