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KVM: s390: Fix prefix register checking in arch/s390/kvm/sigp.c
[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
8 *
9 * Authors:
10 * Avi Kivity <avi@qumranet.com>
11 * Yaniv Kamay <yaniv@qumranet.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
15 *
16 */
17
85f455f7 18#include "irq.h"
1d737c8a 19#include "mmu.h"
e495606d 20
edf88417 21#include <linux/kvm_host.h>
6aa8b732 22#include <linux/module.h>
9d8f549d 23#include <linux/kernel.h>
6aa8b732
AK		 24#include <linux/mm.h>
25#include <linux/highmem.h>
e8edc6e0 26#include <linux/sched.h>
c7addb90 27#include <linux/moduleparam.h>
229456fc 28#include <linux/ftrace_event.h>
5fdbf976 29#include "kvm_cache_regs.h"
35920a35 30#include "x86.h"
e495606d 31
6aa8b732 32#include <asm/io.h>
3b3be0d1 33#include <asm/desc.h>
13673a90 34#include <asm/vmx.h>
6210e37b 35#include <asm/virtext.h>
a0861c02 36#include <asm/mce.h>
6aa8b732 37
229456fc
MT		 38#include "trace.h"
39
4ecac3fd
AK		 40#define __ex(x) __kvm_handle_fault_on_reboot(x)
41
6aa8b732
AK		 42MODULE_AUTHOR("Qumranet");
43MODULE_LICENSE("GPL");
44
4462d21a 45static int __read_mostly bypass_guest_pf = 1;
c1f8bc04 46module_param(bypass_guest_pf, bool, S_IRUGO);
c7addb90 47
4462d21a 48static int __read_mostly enable_vpid = 1;
736caefe 49module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 50
4462d21a 51static int __read_mostly flexpriority_enabled = 1;
736caefe 52module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 53
4462d21a 54static int __read_mostly enable_ept = 1;
736caefe 55module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 56
3a624e29
NK		 57static int __read_mostly enable_unrestricted_guest = 1;
58module_param_named(unrestricted_guest,
59 enable_unrestricted_guest, bool, S_IRUGO);
60
4462d21a 61static int __read_mostly emulate_invalid_guest_state = 0;
c1f8bc04 62module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 63
4b8d54f9
ZE		 64/*
65 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
66 * ple_gap: upper bound on the amount of time between two successive
67 * executions of PAUSE in a loop. Also indicate if ple enabled.
68 * According to test, this time is usually small than 41 cycles.
69 * ple_window: upper bound on the amount of time a guest is allowed to execute
70 * in a PAUSE loop. Tests indicate that most spinlocks are held for
71 * less than 2^12 cycles
72 * Time is measured based on a counter that runs at the same rate as the TSC,
73 * refer SDM volume 3b section 21.6.13 & 22.1.3.
74 */
75#define KVM_VMX_DEFAULT_PLE_GAP 41
76#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
77static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
78module_param(ple_gap, int, S_IRUGO);
79
80static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
81module_param(ple_window, int, S_IRUGO);
82
a2fa3e9f
GH		 83struct vmcs {
84 u32 revision_id;
85 u32 abort;
86 char data[0];
87};
88
26bb0981
AK		 89struct shared_msr_entry {
90 unsigned index;
91 u64 data;
92};
93
a2fa3e9f 94struct vcpu_vmx {
fb3f0f51 95 struct kvm_vcpu vcpu;
543e4243 96 struct list_head local_vcpus_link;
313dbd49 97 unsigned long host_rsp;
a2fa3e9f 98 int launched;
29bd8a78 99 u8 fail;
1155f76a 100 u32 idt_vectoring_info;
26bb0981 101 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH		 102 int nmsrs;
103 int save_nmsrs;
a2fa3e9f 104#ifdef CONFIG_X86_64
44ea2b17
AK		 105 u64 msr_host_kernel_gs_base;
106 u64 msr_guest_kernel_gs_base;
a2fa3e9f
GH		 107#endif
108 struct vmcs *vmcs;
109 struct {
110 int loaded;
111 u16 fs_sel, gs_sel, ldt_sel;
152d3f2f
LV		 112 int gs_ldt_reload_needed;
113 int fs_reload_needed;
d77c26fc 114 } host_state;
9c8cba37 115 struct {
7ffd92c5
AK		 116 int vm86_active;
117 u8 save_iopl;
118 struct kvm_save_segment {
119 u16 selector;
120 unsigned long base;
121 u32 limit;
122 u32 ar;
123 } tr, es, ds, fs, gs;
9c8cba37
AK		 124 struct {
125 bool pending;
126 u8 vector;
127 unsigned rip;
128 } irq;
129 } rmode;
2384d2b3 130 int vpid;
04fa4d32 131 bool emulation_required;
3b86cd99
JK		 132
133 /* Support for vnmi-less CPUs */
134 int soft_vnmi_blocked;
135 ktime_t entry_time;
136 s64 vnmi_blocked_time;
a0861c02 137 u32 exit_reason;
a2fa3e9f
GH		 138};
139
140static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
141{
fb3f0f51 142 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 143}
144
b7ebfb05 145static int init_rmode(struct kvm *kvm);
4e1096d2 146static u64 construct_eptp(unsigned long root_hpa);
75880a01 147
6aa8b732
AK		 148static DEFINE_PER_CPU(struct vmcs *, vmxarea);
149static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
543e4243 150static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu);
6aa8b732 151
3e7c73e9
AK		 152static unsigned long *vmx_io_bitmap_a;
153static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 154static unsigned long *vmx_msr_bitmap_legacy;
155static unsigned long *vmx_msr_bitmap_longmode;
fdef3ad1 156
2384d2b3
SY		 157static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
158static DEFINE_SPINLOCK(vmx_vpid_lock);
159
1c3d14fe 160static struct vmcs_config {
6aa8b732
AK		 161 int size;
162 int order;
163 u32 revision_id;
1c3d14fe
YS		 164 u32 pin_based_exec_ctrl;
165 u32 cpu_based_exec_ctrl;
f78e0e2e 166 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 167 u32 vmexit_ctrl;
168 u32 vmentry_ctrl;
169} vmcs_config;
6aa8b732 170
efff9e53 171static struct vmx_capability {
d56f546d
SY		 172 u32 ept;
173 u32 vpid;
174} vmx_capability;
175
6aa8b732
AK		 176#define VMX_SEGMENT_FIELD(seg) \
177 [VCPU_SREG_##seg] = { \
178 .selector = GUEST_##seg##_SELECTOR, \
179 .base = GUEST_##seg##_BASE, \
180 .limit = GUEST_##seg##_LIMIT, \
181 .ar_bytes = GUEST_##seg##_AR_BYTES, \
182 }
183
184static struct kvm_vmx_segment_field {
185 unsigned selector;
186 unsigned base;
187 unsigned limit;
188 unsigned ar_bytes;
189} kvm_vmx_segment_fields[] = {
190 VMX_SEGMENT_FIELD(CS),
191 VMX_SEGMENT_FIELD(DS),
192 VMX_SEGMENT_FIELD(ES),
193 VMX_SEGMENT_FIELD(FS),
194 VMX_SEGMENT_FIELD(GS),
195 VMX_SEGMENT_FIELD(SS),
196 VMX_SEGMENT_FIELD(TR),
197 VMX_SEGMENT_FIELD(LDTR),
198};
199
26bb0981
AK		 200static u64 host_efer;
201
6de4f3ad
AK		 202static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
203
4d56c8a7
AK		 204/*
205 * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
206 * away by decrementing the array size.
207 */
6aa8b732 208static const u32 vmx_msr_index[] = {
05b3e0c2 209#ifdef CONFIG_X86_64
44ea2b17 210 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732
AK		 211#endif
212 MSR_EFER, MSR_K6_STAR,
213};
9d8f549d 214#define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
6aa8b732 215
6aa8b732
AK		 216static inline int is_page_fault(u32 intr_info)
217{
218 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
219 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 220 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 221}
222
2ab455cc
AL		 223static inline int is_no_device(u32 intr_info)
224{
225 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
226 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 227 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 228}
229
7aa81cc0
AL		 230static inline int is_invalid_opcode(u32 intr_info)
231{
232 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
233 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 234 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 235}
236
6aa8b732
AK		 237static inline int is_external_interrupt(u32 intr_info)
238{
239 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
240 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
241}
242
a0861c02
AK		 243static inline int is_machine_check(u32 intr_info)
244{
245 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
246 INTR_INFO_VALID_MASK)) ==
247 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
248}
249
25c5f225
SY		 250static inline int cpu_has_vmx_msr_bitmap(void)
251{
04547156 252 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 253}
254
6e5d865c
YS		 255static inline int cpu_has_vmx_tpr_shadow(void)
256{
04547156 257 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 258}
259
260static inline int vm_need_tpr_shadow(struct kvm *kvm)
261{
04547156 262 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
6e5d865c
YS		 263}
264
f78e0e2e
SY		 265static inline int cpu_has_secondary_exec_ctrls(void)
266{
04547156
SY		 267 return vmcs_config.cpu_based_exec_ctrl &
268 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 269}
270
774ead3a 271static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 272{
04547156
SY		 273 return vmcs_config.cpu_based_2nd_exec_ctrl &
274 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
275}
276
277static inline bool cpu_has_vmx_flexpriority(void)
278{
279 return cpu_has_vmx_tpr_shadow() &&
280 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 281}
282
e799794e
MT		 283static inline bool cpu_has_vmx_ept_execute_only(void)
284{
285 return !!(vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT);
286}
287
288static inline bool cpu_has_vmx_eptp_uncacheable(void)
289{
290 return !!(vmx_capability.ept & VMX_EPTP_UC_BIT);
291}
292
293static inline bool cpu_has_vmx_eptp_writeback(void)
294{
295 return !!(vmx_capability.ept & VMX_EPTP_WB_BIT);
296}
297
298static inline bool cpu_has_vmx_ept_2m_page(void)
299{
300 return !!(vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT);
301}
302
d56f546d
SY		 303static inline int cpu_has_vmx_invept_individual_addr(void)
304{
04547156 305 return !!(vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT);
d56f546d
SY		 306}
307
308static inline int cpu_has_vmx_invept_context(void)
309{
04547156 310 return !!(vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT);
d56f546d
SY		 311}
312
313static inline int cpu_has_vmx_invept_global(void)
314{
04547156 315 return !!(vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT);
d56f546d
SY		 316}
317
318static inline int cpu_has_vmx_ept(void)
319{
04547156
SY		 320 return vmcs_config.cpu_based_2nd_exec_ctrl &
321 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 322}
323
3a624e29
NK		 324static inline int cpu_has_vmx_unrestricted_guest(void)
325{
326 return vmcs_config.cpu_based_2nd_exec_ctrl &
327 SECONDARY_EXEC_UNRESTRICTED_GUEST;
328}
329
4b8d54f9
ZE		 330static inline int cpu_has_vmx_ple(void)
331{
332 return vmcs_config.cpu_based_2nd_exec_ctrl &
333 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
334}
335
f78e0e2e
SY		 336static inline int vm_need_virtualize_apic_accesses(struct kvm *kvm)
337{
04547156
SY		 338 return flexpriority_enabled &&
339 (cpu_has_vmx_virtualize_apic_accesses()) &&
340 (irqchip_in_kernel(kvm));
f78e0e2e
SY		 341}
342
2384d2b3
SY		 343static inline int cpu_has_vmx_vpid(void)
344{
04547156
SY		 345 return vmcs_config.cpu_based_2nd_exec_ctrl &
346 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 347}
348
f08864b4
SY		 349static inline int cpu_has_virtual_nmis(void)
350{
351 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
352}
353
04547156
SY		 354static inline bool report_flexpriority(void)
355{
356 return flexpriority_enabled;
357}
358
8b9cf98c 359static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 360{
361 int i;
362
a2fa3e9f 363 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 364 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 365 return i;
366 return -1;
367}
368
2384d2b3
SY		 369static inline void __invvpid(int ext, u16 vpid, gva_t gva)
370{
371 struct {
372 u64 vpid : 16;
373 u64 rsvd : 48;
374 u64 gva;
375 } operand = { vpid, 0, gva };
376
4ecac3fd 377 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 378 /* CF==1 or ZF==1 --> rc = -1 */
379 "; ja 1f ; ud2 ; 1:"
380 : : "a"(&operand), "c"(ext) : "cc", "memory");
381}
382
1439442c
SY		 383static inline void __invept(int ext, u64 eptp, gpa_t gpa)
384{
385 struct {
386 u64 eptp, gpa;
387 } operand = {eptp, gpa};
388
4ecac3fd 389 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 390 /* CF==1 or ZF==1 --> rc = -1 */
391 "; ja 1f ; ud2 ; 1:\n"
392 : : "a" (&operand), "c" (ext) : "cc", "memory");
393}
394
26bb0981 395static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 396{
397 int i;
398
8b9cf98c 399 i = __find_msr_index(vmx, msr);
a75beee6 400 if (i >= 0)
a2fa3e9f 401 return &vmx->guest_msrs[i];
8b6d44c7 402 return NULL;
7725f0ba
AK		 403}
404
6aa8b732
AK		 405static void vmcs_clear(struct vmcs *vmcs)
406{
407 u64 phys_addr = __pa(vmcs);
408 u8 error;
409
4ecac3fd 410 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
6aa8b732
AK		 411 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
412 : "cc", "memory");
413 if (error)
414 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
415 vmcs, phys_addr);
416}
417
418static void __vcpu_clear(void *arg)
419{
8b9cf98c 420 struct vcpu_vmx *vmx = arg;
d3b2c338 421 int cpu = raw_smp_processor_id();
6aa8b732 422
8b9cf98c 423 if (vmx->vcpu.cpu == cpu)
a2fa3e9f
GH		 424 vmcs_clear(vmx->vmcs);
425 if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
6aa8b732 426 per_cpu(current_vmcs, cpu) = NULL;
ad312c7c 427 rdtscll(vmx->vcpu.arch.host_tsc);
543e4243
AK		 428 list_del(&vmx->local_vcpus_link);
429 vmx->vcpu.cpu = -1;
430 vmx->launched = 0;
6aa8b732
AK		 431}
432
8b9cf98c 433static void vcpu_clear(struct vcpu_vmx *vmx)
8d0be2b3 434{
eae5ecb5
AK		 435 if (vmx->vcpu.cpu == -1)
436 return;
8691e5a8 437 smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1);
8d0be2b3
AK		 438}
439
2384d2b3
SY		 440static inline void vpid_sync_vcpu_all(struct vcpu_vmx *vmx)
441{
442 if (vmx->vpid == 0)
443 return;
444
445 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
446}
447
1439442c
SY		 448static inline void ept_sync_global(void)
449{
450 if (cpu_has_vmx_invept_global())
451 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
452}
453
454static inline void ept_sync_context(u64 eptp)
455{
089d034e 456 if (enable_ept) {
1439442c
SY		 457 if (cpu_has_vmx_invept_context())
458 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
459 else
460 ept_sync_global();
461 }
462}
463
464static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
465{
089d034e 466 if (enable_ept) {
1439442c
SY		 467 if (cpu_has_vmx_invept_individual_addr())
468 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
469 eptp, gpa);
470 else
471 ept_sync_context(eptp);
472 }
473}
474
6aa8b732
AK		 475static unsigned long vmcs_readl(unsigned long field)
476{
477 unsigned long value;
478
4ecac3fd 479 asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX)
6aa8b732
AK		 480 : "=a"(value) : "d"(field) : "cc");
481 return value;
482}
483
484static u16 vmcs_read16(unsigned long field)
485{
486 return vmcs_readl(field);
487}
488
489static u32 vmcs_read32(unsigned long field)
490{
491 return vmcs_readl(field);
492}
493
494static u64 vmcs_read64(unsigned long field)
495{
05b3e0c2 496#ifdef CONFIG_X86_64
6aa8b732
AK		 497 return vmcs_readl(field);
498#else
499 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
500#endif
501}
502
e52de1b8
AK		 503static noinline void vmwrite_error(unsigned long field, unsigned long value)
504{
505 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
506 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
507 dump_stack();
508}
509
6aa8b732
AK		 510static void vmcs_writel(unsigned long field, unsigned long value)
511{
512 u8 error;
513
4ecac3fd 514 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 515 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 516 if (unlikely(error))
517 vmwrite_error(field, value);
6aa8b732
AK		 518}
519
520static void vmcs_write16(unsigned long field, u16 value)
521{
522 vmcs_writel(field, value);
523}
524
525static void vmcs_write32(unsigned long field, u32 value)
526{
527 vmcs_writel(field, value);
528}
529
530static void vmcs_write64(unsigned long field, u64 value)
531{
6aa8b732 532 vmcs_writel(field, value);
7682f2d0 533#ifndef CONFIG_X86_64
6aa8b732
AK		 534 asm volatile ("");
535 vmcs_writel(field+1, value >> 32);
536#endif
537}
538
2ab455cc
AL		 539static void vmcs_clear_bits(unsigned long field, u32 mask)
540{
541 vmcs_writel(field, vmcs_readl(field) & ~mask);
542}
543
544static void vmcs_set_bits(unsigned long field, u32 mask)
545{
546 vmcs_writel(field, vmcs_readl(field) | mask);
547}
548
abd3f2d6
AK		 549static void update_exception_bitmap(struct kvm_vcpu *vcpu)
550{
551 u32 eb;
552
a0861c02 553 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR);
abd3f2d6
AK		 554 if (!vcpu->fpu_active)
555 eb |= 1u << NM_VECTOR;
e8a48342
AK		 556 /*
557 * Unconditionally intercept #DB so we can maintain dr6 without
558 * reading it every exit.
559 */
560 eb |= 1u << DB_VECTOR;
d0bfb940 561 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
d0bfb940
JK		 562 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
563 eb |= 1u << BP_VECTOR;
564 }
7ffd92c5 565 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 566 eb = ~0;
089d034e 567 if (enable_ept)
1439442c 568 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
abd3f2d6
AK		 569 vmcs_write32(EXCEPTION_BITMAP, eb);
570}
571
33ed6329
AK		 572static void reload_tss(void)
573{
33ed6329
AK		 574 /*
575 * VT restores TR but not its size. Useless.
576 */
577 struct descriptor_table gdt;
a5f61300 578 struct desc_struct *descs;
33ed6329 579
d6e88aec 580 kvm_get_gdt(&gdt);
33ed6329
AK		 581 descs = (void *)gdt.base;
582 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
583 load_TR_desc();
33ed6329
AK		 584}
585
92c0d900 586static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 587{
3a34a881 588 u64 guest_efer;
51c6cf66
AK		 589 u64 ignore_bits;
590
26bb0981 591 guest_efer = vmx->vcpu.arch.shadow_efer;
3a34a881 592
51c6cf66
AK		 593 /*
594 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
595 * outside long mode
596 */
597 ignore_bits = EFER_NX | EFER_SCE;
598#ifdef CONFIG_X86_64
599 ignore_bits |= EFER_LMA | EFER_LME;
600 /* SCE is meaningful only in long mode on Intel */
601 if (guest_efer & EFER_LMA)
602 ignore_bits &= ~(u64)EFER_SCE;
603#endif
604 if ((guest_efer & ~ignore_bits) == (host_efer & ~ignore_bits))
26bb0981 605 return false;
2cc51560 606
51c6cf66
AK		 607 guest_efer &= ~ignore_bits;
608 guest_efer |= host_efer & ignore_bits;
26bb0981
AK		 609 vmx->guest_msrs[efer_offset].data = guest_efer;
610 return true;
51c6cf66
AK		 611}
612
04d2cc77 613static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 614{
04d2cc77 615 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 616 int i;
04d2cc77 617
a2fa3e9f 618 if (vmx->host_state.loaded)
33ed6329
AK		 619 return;
620
a2fa3e9f 621 vmx->host_state.loaded = 1;
33ed6329
AK		 622 /*
623 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
624 * allow segment selectors with cpl > 0 or ti == 1.
625 */
d6e88aec 626 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 627 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
d6e88aec 628 vmx->host_state.fs_sel = kvm_read_fs();
152d3f2f 629 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 630 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 631 vmx->host_state.fs_reload_needed = 0;
632 } else {
33ed6329 633 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 634 vmx->host_state.fs_reload_needed = 1;
33ed6329 635 }
d6e88aec 636 vmx->host_state.gs_sel = kvm_read_gs();
a2fa3e9f
GH		 637 if (!(vmx->host_state.gs_sel & 7))
638 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 639 else {
640 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 641 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 642 }
643
644#ifdef CONFIG_X86_64
645 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
646 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
647#else
a2fa3e9f
GH		 648 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
649 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 650#endif
707c0874
AK		 651
652#ifdef CONFIG_X86_64
44ea2b17
AK		 653 if (is_long_mode(&vmx->vcpu)) {
654 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
655 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
656 }
707c0874 657#endif
26bb0981
AK		 658 for (i = 0; i < vmx->save_nmsrs; ++i)
659 kvm_set_shared_msr(vmx->guest_msrs[i].index,
660 vmx->guest_msrs[i].data);
33ed6329
AK		 661}
662
a9b21b62 663static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 664{
15ad7146 665 unsigned long flags;
33ed6329 666
a2fa3e9f 667 if (!vmx->host_state.loaded)
33ed6329
AK		 668 return;
669
e1beb1d3 670 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 671 vmx->host_state.loaded = 0;
152d3f2f 672 if (vmx->host_state.fs_reload_needed)
d6e88aec 673 kvm_load_fs(vmx->host_state.fs_sel);
152d3f2f 674 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 675 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329
AK		 676 /*
677 * If we have to reload gs, we must take care to
678 * preserve our gs base.
679 */
15ad7146 680 local_irq_save(flags);
d6e88aec 681 kvm_load_gs(vmx->host_state.gs_sel);
33ed6329
AK		 682#ifdef CONFIG_X86_64
683 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
684#endif
15ad7146 685 local_irq_restore(flags);
33ed6329 686 }
152d3f2f 687 reload_tss();
44ea2b17
AK		 688#ifdef CONFIG_X86_64
689 if (is_long_mode(&vmx->vcpu)) {
690 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
691 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
692 }
693#endif
33ed6329
AK		 694}
695
a9b21b62
AK		 696static void vmx_load_host_state(struct vcpu_vmx *vmx)
697{
698 preempt_disable();
699 __vmx_load_host_state(vmx);
700 preempt_enable();
701}
702
6aa8b732
AK		 703/*
704 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
705 * vcpu mutex is already taken.
706 */
15ad7146 707static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 708{
a2fa3e9f
GH		 709 struct vcpu_vmx *vmx = to_vmx(vcpu);
710 u64 phys_addr = __pa(vmx->vmcs);
019960ae 711 u64 tsc_this, delta, new_offset;
6aa8b732 712
a3d7f85f 713 if (vcpu->cpu != cpu) {
8b9cf98c 714 vcpu_clear(vmx);
2f599714 715 kvm_migrate_timers(vcpu);
eb5109e3 716 set_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests);
543e4243
AK		 717 local_irq_disable();
718 list_add(&vmx->local_vcpus_link,
719 &per_cpu(vcpus_on_cpu, cpu));
720 local_irq_enable();
a3d7f85f 721 }
6aa8b732 722
a2fa3e9f 723 if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
6aa8b732
AK		 724 u8 error;
725
a2fa3e9f 726 per_cpu(current_vmcs, cpu) = vmx->vmcs;
4ecac3fd 727 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
6aa8b732
AK		 728 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
729 : "cc");
730 if (error)
731 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
a2fa3e9f 732 vmx->vmcs, phys_addr);
6aa8b732
AK		 733 }
734
735 if (vcpu->cpu != cpu) {
736 struct descriptor_table dt;
737 unsigned long sysenter_esp;
738
739 vcpu->cpu = cpu;
740 /*
741 * Linux uses per-cpu TSS and GDT, so set these when switching
742 * processors.
743 */
d6e88aec
AK		 744 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
745 kvm_get_gdt(&dt);
6aa8b732
AK		 746 vmcs_writel(HOST_GDTR_BASE, dt.base); /* 22.2.4 */
747
748 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
749 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
7700270e
AK		 750
751 /*
752 * Make sure the time stamp counter is monotonous.
753 */
754 rdtscll(tsc_this);
019960ae
AK		 755 if (tsc_this < vcpu->arch.host_tsc) {
756 delta = vcpu->arch.host_tsc - tsc_this;
757 new_offset = vmcs_read64(TSC_OFFSET) + delta;
758 vmcs_write64(TSC_OFFSET, new_offset);
759 }
6aa8b732 760 }
6aa8b732
AK		 761}
762
763static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
764{
a9b21b62 765 __vmx_load_host_state(to_vmx(vcpu));
6aa8b732
AK		 766}
767
5fd86fcf
AK		 768static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
769{
770 if (vcpu->fpu_active)
771 return;
772 vcpu->fpu_active = 1;
707d92fa 773 vmcs_clear_bits(GUEST_CR0, X86_CR0_TS);
ad312c7c 774 if (vcpu->arch.cr0 & X86_CR0_TS)
707d92fa 775 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
5fd86fcf
AK		 776 update_exception_bitmap(vcpu);
777}
778
779static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
780{
781 if (!vcpu->fpu_active)
782 return;
783 vcpu->fpu_active = 0;
707d92fa 784 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
5fd86fcf
AK		 785 update_exception_bitmap(vcpu);
786}
787
6aa8b732
AK		 788static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
789{
345dcaa8
AK		 790 unsigned long rflags;
791
792 rflags = vmcs_readl(GUEST_RFLAGS);
793 if (to_vmx(vcpu)->rmode.vm86_active)
794 rflags &= ~(unsigned long)(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
795 return rflags;
6aa8b732
AK		 796}
797
798static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
799{
7ffd92c5 800 if (to_vmx(vcpu)->rmode.vm86_active)
053de044 801 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 802 vmcs_writel(GUEST_RFLAGS, rflags);
803}
804
2809f5d2
GC		 805static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
806{
807 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
808 int ret = 0;
809
810 if (interruptibility & GUEST_INTR_STATE_STI)
811 ret |= X86_SHADOW_INT_STI;
812 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
813 ret |= X86_SHADOW_INT_MOV_SS;
814
815 return ret & mask;
816}
817
818static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
819{
820 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
821 u32 interruptibility = interruptibility_old;
822
823 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
824
825 if (mask & X86_SHADOW_INT_MOV_SS)
826 interruptibility |= GUEST_INTR_STATE_MOV_SS;
827 if (mask & X86_SHADOW_INT_STI)
828 interruptibility |= GUEST_INTR_STATE_STI;
829
830 if ((interruptibility != interruptibility_old))
831 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
832}
833
6aa8b732
AK		 834static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
835{
836 unsigned long rip;
6aa8b732 837
5fdbf976 838 rip = kvm_rip_read(vcpu);
6aa8b732 839 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 840 kvm_rip_write(vcpu, rip);
6aa8b732 841
2809f5d2
GC		 842 /* skipping an emulated instruction also counts */
843 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 844}
845
298101da
AK		 846static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
847 bool has_error_code, u32 error_code)
848{
77ab6db0 849 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 850 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 851
8ab2d2e2 852 if (has_error_code) {
77ab6db0 853 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 854 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
855 }
77ab6db0 856
7ffd92c5 857 if (vmx->rmode.vm86_active) {
77ab6db0
JK		 858 vmx->rmode.irq.pending = true;
859 vmx->rmode.irq.vector = nr;
860 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
ae0bb3e0
GN		 861 if (kvm_exception_is_soft(nr))
862 vmx->rmode.irq.rip +=
863 vmx->vcpu.arch.event_exit_inst_len;
8ab2d2e2
JK		 864 intr_info |= INTR_TYPE_SOFT_INTR;
865 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
77ab6db0
JK		 866 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
867 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
868 return;
869 }
870
66fd3f7f
GN		 871 if (kvm_exception_is_soft(nr)) {
872 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
873 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 874 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
875 } else
876 intr_info |= INTR_TYPE_HARD_EXCEPTION;
877
878 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
298101da
AK		 879}
880
a75beee6
ED		 881/*
882 * Swap MSR entry in host/guest MSR entry array.
883 */
8b9cf98c 884static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 885{
26bb0981 886 struct shared_msr_entry tmp;
a2fa3e9f
GH		 887
888 tmp = vmx->guest_msrs[to];
889 vmx->guest_msrs[to] = vmx->guest_msrs[from];
890 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 891}
892
e38aea3e
AK		 893/*
894 * Set up the vmcs to automatically save and restore system
895 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
896 * mode, as fiddling with msrs is very expensive.
897 */
8b9cf98c 898static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 899{
26bb0981 900 int save_nmsrs, index;
5897297b 901 unsigned long *msr_bitmap;
e38aea3e 902
33f9c505 903 vmx_load_host_state(vmx);
a75beee6
ED		 904 save_nmsrs = 0;
905#ifdef CONFIG_X86_64
8b9cf98c 906 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 907 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 908 if (index >= 0)
8b9cf98c
RR		 909 move_msr_up(vmx, index, save_nmsrs++);
910 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 911 if (index >= 0)
8b9cf98c
RR		 912 move_msr_up(vmx, index, save_nmsrs++);
913 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 914 if (index >= 0)
8b9cf98c 915 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 916 /*
917 * MSR_K6_STAR is only needed on long mode guests, and only
918 * if efer.sce is enabled.
919 */
8b9cf98c 920 index = __find_msr_index(vmx, MSR_K6_STAR);
ad312c7c 921 if ((index >= 0) && (vmx->vcpu.arch.shadow_efer & EFER_SCE))
8b9cf98c 922 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 923 }
924#endif
92c0d900
AK		 925 index = __find_msr_index(vmx, MSR_EFER);
926 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 927 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 928
26bb0981 929 vmx->save_nmsrs = save_nmsrs;
5897297b
AK		 930
931 if (cpu_has_vmx_msr_bitmap()) {
932 if (is_long_mode(&vmx->vcpu))
933 msr_bitmap = vmx_msr_bitmap_longmode;
934 else
935 msr_bitmap = vmx_msr_bitmap_legacy;
936
937 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
938 }
e38aea3e
AK		 939}
940
6aa8b732
AK		 941/*
942 * reads and returns guest's timestamp counter "register"
943 * guest_tsc = host_tsc + tsc_offset -- 21.3
944 */
945static u64 guest_read_tsc(void)
946{
947 u64 host_tsc, tsc_offset;
948
949 rdtscll(host_tsc);
950 tsc_offset = vmcs_read64(TSC_OFFSET);
951 return host_tsc + tsc_offset;
952}
953
954/*
955 * writes 'guest_tsc' into guest's timestamp counter "register"
956 * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
957 */
53f658b3 958static void guest_write_tsc(u64 guest_tsc, u64 host_tsc)
6aa8b732 959{
6aa8b732
AK		 960 vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
961}
962
6aa8b732
AK		 963/*
964 * Reads an msr value (of 'msr_index') into 'pdata'.
965 * Returns 0 on success, non-0 otherwise.
966 * Assumes vcpu_load() was already called.
967 */
968static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
969{
970 u64 data;
26bb0981 971 struct shared_msr_entry *msr;
6aa8b732
AK		 972
973 if (!pdata) {
974 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
975 return -EINVAL;
976 }
977
978 switch (msr_index) {
05b3e0c2 979#ifdef CONFIG_X86_64
6aa8b732
AK		 980 case MSR_FS_BASE:
981 data = vmcs_readl(GUEST_FS_BASE);
982 break;
983 case MSR_GS_BASE:
984 data = vmcs_readl(GUEST_GS_BASE);
985 break;
44ea2b17
AK		 986 case MSR_KERNEL_GS_BASE:
987 vmx_load_host_state(to_vmx(vcpu));
988 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
989 break;
26bb0981 990#endif
6aa8b732 991 case MSR_EFER:
3bab1f5d 992 return kvm_get_msr_common(vcpu, msr_index, pdata);
af24a4e4 993 case MSR_IA32_TSC:
6aa8b732
AK		 994 data = guest_read_tsc();
995 break;
996 case MSR_IA32_SYSENTER_CS:
997 data = vmcs_read32(GUEST_SYSENTER_CS);
998 break;
999 case MSR_IA32_SYSENTER_EIP:
f5b42c33 1000 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 1001 break;
1002 case MSR_IA32_SYSENTER_ESP:
f5b42c33 1003 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 1004 break;
6aa8b732 1005 default:
26bb0981 1006 vmx_load_host_state(to_vmx(vcpu));
8b9cf98c 1007 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d 1008 if (msr) {
542423b0 1009 vmx_load_host_state(to_vmx(vcpu));
3bab1f5d
AK		 1010 data = msr->data;
1011 break;
6aa8b732 1012 }
3bab1f5d 1013 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 1014 }
1015
1016 *pdata = data;
1017 return 0;
1018}
1019
1020/*
1021 * Writes msr value into into the appropriate "register".
1022 * Returns 0 on success, non-0 otherwise.
1023 * Assumes vcpu_load() was already called.
1024 */
1025static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
1026{
a2fa3e9f 1027 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1028 struct shared_msr_entry *msr;
53f658b3 1029 u64 host_tsc;
2cc51560
ED		 1030 int ret = 0;
1031
6aa8b732 1032 switch (msr_index) {
3bab1f5d 1033 case MSR_EFER:
a9b21b62 1034 vmx_load_host_state(vmx);
2cc51560 1035 ret = kvm_set_msr_common(vcpu, msr_index, data);
2cc51560 1036 break;
16175a79 1037#ifdef CONFIG_X86_64
6aa8b732
AK		 1038 case MSR_FS_BASE:
1039 vmcs_writel(GUEST_FS_BASE, data);
1040 break;
1041 case MSR_GS_BASE:
1042 vmcs_writel(GUEST_GS_BASE, data);
1043 break;
44ea2b17
AK		 1044 case MSR_KERNEL_GS_BASE:
1045 vmx_load_host_state(vmx);
1046 vmx->msr_guest_kernel_gs_base = data;
1047 break;
6aa8b732
AK		 1048#endif
1049 case MSR_IA32_SYSENTER_CS:
1050 vmcs_write32(GUEST_SYSENTER_CS, data);
1051 break;
1052 case MSR_IA32_SYSENTER_EIP:
f5b42c33 1053 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 1054 break;
1055 case MSR_IA32_SYSENTER_ESP:
f5b42c33 1056 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 1057 break;
af24a4e4 1058 case MSR_IA32_TSC:
53f658b3
MT		 1059 rdtscll(host_tsc);
1060 guest_write_tsc(data, host_tsc);
6aa8b732 1061 break;
468d472f
SY		 1062 case MSR_IA32_CR_PAT:
1063 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
1064 vmcs_write64(GUEST_IA32_PAT, data);
1065 vcpu->arch.pat = data;
1066 break;
1067 }
1068 /* Otherwise falls through to kvm_set_msr_common */
6aa8b732 1069 default:
8b9cf98c 1070 msr = find_msr_entry(vmx, msr_index);
3bab1f5d 1071 if (msr) {
542423b0 1072 vmx_load_host_state(vmx);
3bab1f5d
AK		 1073 msr->data = data;
1074 break;
6aa8b732 1075 }
2cc51560 1076 ret = kvm_set_msr_common(vcpu, msr_index, data);
6aa8b732
AK		 1077 }
1078
2cc51560 1079 return ret;
6aa8b732
AK		 1080}
1081
5fdbf976 1082static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 1083{
5fdbf976
MT		 1084 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
1085 switch (reg) {
1086 case VCPU_REGS_RSP:
1087 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
1088 break;
1089 case VCPU_REGS_RIP:
1090 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
1091 break;
6de4f3ad
AK		 1092 case VCPU_EXREG_PDPTR:
1093 if (enable_ept)
1094 ept_save_pdptrs(vcpu);
1095 break;
5fdbf976
MT		 1096 default:
1097 break;
1098 }
6aa8b732
AK		 1099}
1100
355be0b9 1101static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
6aa8b732 1102{
ae675ef0
JK		 1103 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1104 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
1105 else
1106 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
1107
abd3f2d6 1108 update_exception_bitmap(vcpu);
6aa8b732
AK		 1109}
1110
1111static __init int cpu_has_kvm_support(void)
1112{
6210e37b 1113 return cpu_has_vmx();
6aa8b732
AK		 1114}
1115
1116static __init int vmx_disabled_by_bios(void)
1117{
1118 u64 msr;
1119
1120 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
9ea542fa
SY		 1121 return (msr & (FEATURE_CONTROL_LOCKED |
1122 FEATURE_CONTROL_VMXON_ENABLED))
1123 == FEATURE_CONTROL_LOCKED;
62b3ffb8 1124 /* locked but not enabled */
6aa8b732
AK		 1125}
1126
10474ae8 1127static int hardware_enable(void *garbage)
6aa8b732
AK		 1128{
1129 int cpu = raw_smp_processor_id();
1130 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1131 u64 old;
1132
10474ae8
AG		 1133 if (read_cr4() & X86_CR4_VMXE)
1134 return -EBUSY;
1135
543e4243 1136 INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu));
6aa8b732 1137 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
9ea542fa
SY		 1138 if ((old & (FEATURE_CONTROL_LOCKED |
1139 FEATURE_CONTROL_VMXON_ENABLED))
1140 != (FEATURE_CONTROL_LOCKED |
1141 FEATURE_CONTROL_VMXON_ENABLED))
6aa8b732 1142 /* enable and lock */
62b3ffb8 1143 wrmsrl(MSR_IA32_FEATURE_CONTROL, old |
9ea542fa
SY		 1144 FEATURE_CONTROL_LOCKED |
1145 FEATURE_CONTROL_VMXON_ENABLED);
66aee91a 1146 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
4ecac3fd
AK		 1147 asm volatile (ASM_VMX_VMXON_RAX
1148 : : "a"(&phys_addr), "m"(phys_addr)
6aa8b732 1149 : "memory", "cc");
10474ae8
AG		 1150
1151 ept_sync_global();
1152
1153 return 0;
6aa8b732
AK		 1154}
1155
543e4243
AK		 1156static void vmclear_local_vcpus(void)
1157{
1158 int cpu = raw_smp_processor_id();
1159 struct vcpu_vmx *vmx, *n;
1160
1161 list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu),
1162 local_vcpus_link)
1163 __vcpu_clear(vmx);
1164}
1165
710ff4a8
EH		 1166
1167/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
1168 * tricks.
1169 */
1170static void kvm_cpu_vmxoff(void)
6aa8b732 1171{
4ecac3fd 1172 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
e693d71b 1173 write_cr4(read_cr4() & ~X86_CR4_VMXE);
6aa8b732
AK		 1174}
1175
710ff4a8
EH		 1176static void hardware_disable(void *garbage)
1177{
1178 vmclear_local_vcpus();
1179 kvm_cpu_vmxoff();
1180}
1181
1c3d14fe 1182static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 1183 u32 msr, u32 *result)
1c3d14fe
YS		 1184{
1185 u32 vmx_msr_low, vmx_msr_high;
1186 u32 ctl = ctl_min | ctl_opt;
1187
1188 rdmsr(msr, vmx_msr_low, vmx_msr_high);
1189
1190 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1191 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
1192
1193 /* Ensure minimum (required) set of control bits are supported. */
1194 if (ctl_min & ~ctl)
002c7f7c 1195 return -EIO;
1c3d14fe
YS		 1196
1197 *result = ctl;
1198 return 0;
1199}
1200
002c7f7c 1201static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 1202{
1203 u32 vmx_msr_low, vmx_msr_high;
d56f546d 1204 u32 min, opt, min2, opt2;
1c3d14fe
YS		 1205 u32 _pin_based_exec_control = 0;
1206 u32 _cpu_based_exec_control = 0;
f78e0e2e 1207 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 1208 u32 _vmexit_control = 0;
1209 u32 _vmentry_control = 0;
1210
1211 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
f08864b4 1212 opt = PIN_BASED_VIRTUAL_NMIS;
1c3d14fe
YS		 1213 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1214 &_pin_based_exec_control) < 0)
002c7f7c 1215 return -EIO;
1c3d14fe
YS		 1216
1217 min = CPU_BASED_HLT_EXITING |
1218#ifdef CONFIG_X86_64
1219 CPU_BASED_CR8_LOAD_EXITING |
1220 CPU_BASED_CR8_STORE_EXITING |
1221#endif
d56f546d
SY		 1222 CPU_BASED_CR3_LOAD_EXITING |
1223 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 1224 CPU_BASED_USE_IO_BITMAPS |
1225 CPU_BASED_MOV_DR_EXITING |
a7052897
MT		 1226 CPU_BASED_USE_TSC_OFFSETING |
1227 CPU_BASED_INVLPG_EXITING;
f78e0e2e 1228 opt = CPU_BASED_TPR_SHADOW |
25c5f225 1229 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 1230 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 1231 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1232 &_cpu_based_exec_control) < 0)
002c7f7c 1233 return -EIO;
6e5d865c
YS		 1234#ifdef CONFIG_X86_64
1235 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1236 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1237 ~CPU_BASED_CR8_STORE_EXITING;
1238#endif
f78e0e2e 1239 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 1240 min2 = 0;
1241 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2384d2b3 1242 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 1243 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 1244 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9
ZE		 1245 SECONDARY_EXEC_UNRESTRICTED_GUEST |
1246 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
d56f546d
SY		 1247 if (adjust_vmx_controls(min2, opt2,
1248 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 1249 &_cpu_based_2nd_exec_control) < 0)
1250 return -EIO;
1251 }
1252#ifndef CONFIG_X86_64
1253 if (!(_cpu_based_2nd_exec_control &
1254 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1255 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1256#endif
d56f546d 1257 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 1258 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
1259 enabled */
5fff7d27
GN		 1260 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
1261 CPU_BASED_CR3_STORE_EXITING |
1262 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 1263 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1264 vmx_capability.ept, vmx_capability.vpid);
1265 }
1c3d14fe
YS		 1266
1267 min = 0;
1268#ifdef CONFIG_X86_64
1269 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1270#endif
468d472f 1271 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1c3d14fe
YS		 1272 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1273 &_vmexit_control) < 0)
002c7f7c 1274 return -EIO;
1c3d14fe 1275
468d472f
SY		 1276 min = 0;
1277 opt = VM_ENTRY_LOAD_IA32_PAT;
1c3d14fe
YS		 1278 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1279 &_vmentry_control) < 0)
002c7f7c 1280 return -EIO;
6aa8b732 1281
c68876fd 1282 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 1283
1284 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1285 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 1286 return -EIO;
1c3d14fe
YS		 1287
1288#ifdef CONFIG_X86_64
1289 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1290 if (vmx_msr_high & (1u<<16))
002c7f7c 1291 return -EIO;
1c3d14fe
YS		 1292#endif
1293
1294 /* Require Write-Back (WB) memory type for VMCS accesses. */
1295 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 1296 return -EIO;
1c3d14fe 1297
002c7f7c
YS		 1298 vmcs_conf->size = vmx_msr_high & 0x1fff;
1299 vmcs_conf->order = get_order(vmcs_config.size);
1300 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 1301
002c7f7c
YS		 1302 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1303 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 1304 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 1305 vmcs_conf->vmexit_ctrl = _vmexit_control;
1306 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe
YS		 1307
1308 return 0;
c68876fd 1309}
6aa8b732
AK		 1310
1311static struct vmcs *alloc_vmcs_cpu(int cpu)
1312{
1313 int node = cpu_to_node(cpu);
1314 struct page *pages;
1315 struct vmcs *vmcs;
1316
6484eb3e 1317 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 1318 if (!pages)
1319 return NULL;
1320 vmcs = page_address(pages);
1c3d14fe
YS		 1321 memset(vmcs, 0, vmcs_config.size);
1322 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 1323 return vmcs;
1324}
1325
1326static struct vmcs *alloc_vmcs(void)
1327{
d3b2c338 1328 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 1329}
1330
1331static void free_vmcs(struct vmcs *vmcs)
1332{
1c3d14fe 1333 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 1334}
1335
39959588 1336static void free_kvm_area(void)
6aa8b732
AK		 1337{
1338 int cpu;
1339
3230bb47 1340 for_each_possible_cpu(cpu) {
6aa8b732 1341 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 1342 per_cpu(vmxarea, cpu) = NULL;
1343 }
6aa8b732
AK		 1344}
1345
6aa8b732
AK		 1346static __init int alloc_kvm_area(void)
1347{
1348 int cpu;
1349
3230bb47 1350 for_each_possible_cpu(cpu) {
6aa8b732
AK		 1351 struct vmcs *vmcs;
1352
1353 vmcs = alloc_vmcs_cpu(cpu);
1354 if (!vmcs) {
1355 free_kvm_area();
1356 return -ENOMEM;
1357 }
1358
1359 per_cpu(vmxarea, cpu) = vmcs;
1360 }
1361 return 0;
1362}
1363
1364static __init int hardware_setup(void)
1365{
002c7f7c
YS		 1366 if (setup_vmcs_config(&vmcs_config) < 0)
1367 return -EIO;
50a37eb4
JR		 1368
1369 if (boot_cpu_has(X86_FEATURE_NX))
1370 kvm_enable_efer_bits(EFER_NX);
1371
93ba03c2
SY		 1372 if (!cpu_has_vmx_vpid())
1373 enable_vpid = 0;
1374
3a624e29 1375 if (!cpu_has_vmx_ept()) {
93ba03c2 1376 enable_ept = 0;
3a624e29
NK		 1377 enable_unrestricted_guest = 0;
1378 }
1379
1380 if (!cpu_has_vmx_unrestricted_guest())
1381 enable_unrestricted_guest = 0;
93ba03c2
SY		 1382
1383 if (!cpu_has_vmx_flexpriority())
1384 flexpriority_enabled = 0;
1385
95ba8273
GN		 1386 if (!cpu_has_vmx_tpr_shadow())
1387 kvm_x86_ops->update_cr8_intercept = NULL;
1388
54dee993
MT		 1389 if (enable_ept && !cpu_has_vmx_ept_2m_page())
1390 kvm_disable_largepages();
1391
4b8d54f9
ZE		 1392 if (!cpu_has_vmx_ple())
1393 ple_gap = 0;
1394
6aa8b732
AK		 1395 return alloc_kvm_area();
1396}
1397
1398static __exit void hardware_unsetup(void)
1399{
1400 free_kvm_area();
1401}
1402
6aa8b732
AK		 1403static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1404{
1405 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1406
6af11b9e 1407 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
6aa8b732
AK		 1408 vmcs_write16(sf->selector, save->selector);
1409 vmcs_writel(sf->base, save->base);
1410 vmcs_write32(sf->limit, save->limit);
1411 vmcs_write32(sf->ar_bytes, save->ar);
1412 } else {
1413 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1414 << AR_DPL_SHIFT;
1415 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1416 }
1417}
1418
1419static void enter_pmode(struct kvm_vcpu *vcpu)
1420{
1421 unsigned long flags;
a89a8fb9 1422 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 1423
a89a8fb9 1424 vmx->emulation_required = 1;
7ffd92c5 1425 vmx->rmode.vm86_active = 0;
6aa8b732 1426
7ffd92c5
AK		 1427 vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
1428 vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
1429 vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
6aa8b732
AK		 1430
1431 flags = vmcs_readl(GUEST_RFLAGS);
053de044 1432 flags &= ~(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
7ffd92c5 1433 flags |= (vmx->rmode.save_iopl << IOPL_SHIFT);
6aa8b732
AK		 1434 vmcs_writel(GUEST_RFLAGS, flags);
1435
66aee91a
RR		 1436 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1437 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 1438
1439 update_exception_bitmap(vcpu);
1440
a89a8fb9
MG		 1441 if (emulate_invalid_guest_state)
1442 return;
1443
7ffd92c5
AK		 1444 fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
1445 fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
1446 fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
1447 fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
6aa8b732
AK		 1448
1449 vmcs_write16(GUEST_SS_SELECTOR, 0);
1450 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1451
1452 vmcs_write16(GUEST_CS_SELECTOR,
1453 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1454 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1455}
1456
d77c26fc 1457static gva_t rmode_tss_base(struct kvm *kvm)
6aa8b732 1458{
bfc6d222 1459 if (!kvm->arch.tss_addr) {
cbc94022
IE		 1460 gfn_t base_gfn = kvm->memslots[0].base_gfn +
1461 kvm->memslots[0].npages - 3;
1462 return base_gfn << PAGE_SHIFT;
1463 }
bfc6d222 1464 return kvm->arch.tss_addr;
6aa8b732
AK		 1465}
1466
1467static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1468{
1469 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1470
1471 save->selector = vmcs_read16(sf->selector);
1472 save->base = vmcs_readl(sf->base);
1473 save->limit = vmcs_read32(sf->limit);
1474 save->ar = vmcs_read32(sf->ar_bytes);
15b00f32
JK		 1475 vmcs_write16(sf->selector, save->base >> 4);
1476 vmcs_write32(sf->base, save->base & 0xfffff);
6aa8b732
AK		 1477 vmcs_write32(sf->limit, 0xffff);
1478 vmcs_write32(sf->ar_bytes, 0xf3);
1479}
1480
1481static void enter_rmode(struct kvm_vcpu *vcpu)
1482{
1483 unsigned long flags;
a89a8fb9 1484 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 1485
3a624e29
NK		 1486 if (enable_unrestricted_guest)
1487 return;
1488
a89a8fb9 1489 vmx->emulation_required = 1;
7ffd92c5 1490 vmx->rmode.vm86_active = 1;
6aa8b732 1491
7ffd92c5 1492 vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
6aa8b732
AK		 1493 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1494
7ffd92c5 1495 vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
6aa8b732
AK		 1496 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1497
7ffd92c5 1498 vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
6aa8b732
AK		 1499 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1500
1501 flags = vmcs_readl(GUEST_RFLAGS);
7ffd92c5 1502 vmx->rmode.save_iopl
ad312c7c 1503 = (flags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
6aa8b732 1504
053de044 1505 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 1506
1507 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 1508 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 1509 update_exception_bitmap(vcpu);
1510
a89a8fb9
MG		 1511 if (emulate_invalid_guest_state)
1512 goto continue_rmode;
1513
6aa8b732
AK		 1514 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1515 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1516 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1517
1518 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
abacf8df 1519 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
8cb5b033
AK		 1520 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1521 vmcs_writel(GUEST_CS_BASE, 0xf0000);
6aa8b732
AK		 1522 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1523
7ffd92c5
AK		 1524 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
1525 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
1526 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
1527 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
75880a01 1528
a89a8fb9 1529continue_rmode:
8668a3c4 1530 kvm_mmu_reset_context(vcpu);
b7ebfb05 1531 init_rmode(vcpu->kvm);
6aa8b732
AK		 1532}
1533
401d10de
AS		 1534static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1535{
1536 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 1537 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1538
1539 if (!msr)
1540 return;
401d10de 1541
44ea2b17
AK		 1542 /*
1543 * Force kernel_gs_base reloading before EFER changes, as control
1544 * of this msr depends on is_long_mode().
1545 */
1546 vmx_load_host_state(to_vmx(vcpu));
401d10de
AS		 1547 vcpu->arch.shadow_efer = efer;
1548 if (!msr)
1549 return;
1550 if (efer & EFER_LMA) {
1551 vmcs_write32(VM_ENTRY_CONTROLS,
1552 vmcs_read32(VM_ENTRY_CONTROLS) |
1553 VM_ENTRY_IA32E_MODE);
1554 msr->data = efer;
1555 } else {
1556 vmcs_write32(VM_ENTRY_CONTROLS,
1557 vmcs_read32(VM_ENTRY_CONTROLS) &
1558 ~VM_ENTRY_IA32E_MODE);
1559
1560 msr->data = efer & ~EFER_LME;
1561 }
1562 setup_msrs(vmx);
1563}
1564
05b3e0c2 1565#ifdef CONFIG_X86_64
6aa8b732
AK		 1566
1567static void enter_lmode(struct kvm_vcpu *vcpu)
1568{
1569 u32 guest_tr_ar;
1570
1571 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1572 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1573 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
b8688d51 1574 __func__);
6aa8b732
AK		 1575 vmcs_write32(GUEST_TR_AR_BYTES,
1576 (guest_tr_ar & ~AR_TYPE_MASK)
1577 | AR_TYPE_BUSY_64_TSS);
1578 }
ad312c7c 1579 vcpu->arch.shadow_efer |= EFER_LMA;
401d10de 1580 vmx_set_efer(vcpu, vcpu->arch.shadow_efer);
6aa8b732
AK		 1581}
1582
1583static void exit_lmode(struct kvm_vcpu *vcpu)
1584{
ad312c7c 1585 vcpu->arch.shadow_efer &= ~EFER_LMA;
6aa8b732
AK		 1586
1587 vmcs_write32(VM_ENTRY_CONTROLS,
1588 vmcs_read32(VM_ENTRY_CONTROLS)
1e4e6e00 1589 & ~VM_ENTRY_IA32E_MODE);
6aa8b732
AK		 1590}
1591
1592#endif
1593
2384d2b3
SY		 1594static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1595{
1596 vpid_sync_vcpu_all(to_vmx(vcpu));
089d034e 1597 if (enable_ept)
4e1096d2 1598 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
2384d2b3
SY		 1599}
1600
25c4c276 1601static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 1602{
ad312c7c
ZX		 1603 vcpu->arch.cr4 &= KVM_GUEST_CR4_MASK;
1604 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & ~KVM_GUEST_CR4_MASK;
399badf3
AK		 1605}
1606
1439442c
SY		 1607static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
1608{
6de4f3ad
AK		 1609 if (!test_bit(VCPU_EXREG_PDPTR,
1610 (unsigned long *)&vcpu->arch.regs_dirty))
1611 return;
1612
1439442c 1613 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1439442c
SY		 1614 vmcs_write64(GUEST_PDPTR0, vcpu->arch.pdptrs[0]);
1615 vmcs_write64(GUEST_PDPTR1, vcpu->arch.pdptrs[1]);
1616 vmcs_write64(GUEST_PDPTR2, vcpu->arch.pdptrs[2]);
1617 vmcs_write64(GUEST_PDPTR3, vcpu->arch.pdptrs[3]);
1618 }
1619}
1620
8f5d549f
AK		 1621static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
1622{
1623 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1624 vcpu->arch.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
1625 vcpu->arch.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
1626 vcpu->arch.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
1627 vcpu->arch.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
1628 }
6de4f3ad
AK		 1629
1630 __set_bit(VCPU_EXREG_PDPTR,
1631 (unsigned long *)&vcpu->arch.regs_avail);
1632 __set_bit(VCPU_EXREG_PDPTR,
1633 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 1634}
1635
1439442c
SY		 1636static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1637
1638static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
1639 unsigned long cr0,
1640 struct kvm_vcpu *vcpu)
1641{
1642 if (!(cr0 & X86_CR0_PG)) {
1643 /* From paging/starting to nonpaging */
1644 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 1645 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 1646 (CPU_BASED_CR3_LOAD_EXITING |
1647 CPU_BASED_CR3_STORE_EXITING));
1648 vcpu->arch.cr0 = cr0;
1649 vmx_set_cr4(vcpu, vcpu->arch.cr4);
1439442c
SY		 1650 } else if (!is_paging(vcpu)) {
1651 /* From nonpaging to paging */
1652 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 1653 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 1654 ~(CPU_BASED_CR3_LOAD_EXITING |
1655 CPU_BASED_CR3_STORE_EXITING));
1656 vcpu->arch.cr0 = cr0;
1657 vmx_set_cr4(vcpu, vcpu->arch.cr4);
1439442c 1658 }
95eb84a7
SY		 1659
1660 if (!(cr0 & X86_CR0_WP))
1661 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 1662}
1663
1664static void ept_update_paging_mode_cr4(unsigned long *hw_cr4,
1665 struct kvm_vcpu *vcpu)
1666{
1667 if (!is_paging(vcpu)) {
1668 *hw_cr4 &= ~X86_CR4_PAE;
1669 *hw_cr4 |= X86_CR4_PSE;
1670 } else if (!(vcpu->arch.cr4 & X86_CR4_PAE))
1671 *hw_cr4 &= ~X86_CR4_PAE;
1672}
1673
6aa8b732
AK		 1674static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1675{
7ffd92c5 1676 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 1677 unsigned long hw_cr0;
1678
1679 if (enable_unrestricted_guest)
1680 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
1681 | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
1682 else
1683 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
1439442c 1684
5fd86fcf
AK		 1685 vmx_fpu_deactivate(vcpu);
1686
7ffd92c5 1687 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
6aa8b732
AK		 1688 enter_pmode(vcpu);
1689
7ffd92c5 1690 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
6aa8b732
AK		 1691 enter_rmode(vcpu);
1692
05b3e0c2 1693#ifdef CONFIG_X86_64
ad312c7c 1694 if (vcpu->arch.shadow_efer & EFER_LME) {
707d92fa 1695 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 1696 enter_lmode(vcpu);
707d92fa 1697 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 1698 exit_lmode(vcpu);
1699 }
1700#endif
1701
089d034e 1702 if (enable_ept)
1439442c
SY		 1703 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
1704
6aa8b732 1705 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 1706 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 1707 vcpu->arch.cr0 = cr0;
5fd86fcf 1708
707d92fa 1709 if (!(cr0 & X86_CR0_TS) || !(cr0 & X86_CR0_PE))
5fd86fcf 1710 vmx_fpu_activate(vcpu);
6aa8b732
AK		 1711}
1712
1439442c
SY		 1713static u64 construct_eptp(unsigned long root_hpa)
1714{
1715 u64 eptp;
1716
1717 /* TODO write the value reading from MSR */
1718 eptp = VMX_EPT_DEFAULT_MT |
1719 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
1720 eptp |= (root_hpa & PAGE_MASK);
1721
1722 return eptp;
1723}
1724
6aa8b732
AK		 1725static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1726{
1439442c
SY		 1727 unsigned long guest_cr3;
1728 u64 eptp;
1729
1730 guest_cr3 = cr3;
089d034e 1731 if (enable_ept) {
1439442c
SY		 1732 eptp = construct_eptp(cr3);
1733 vmcs_write64(EPT_POINTER, eptp);
1439442c 1734 guest_cr3 = is_paging(vcpu) ? vcpu->arch.cr3 :
b927a3ce 1735 vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 1736 ept_load_pdptrs(vcpu);
1439442c
SY		 1737 }
1738
2384d2b3 1739 vmx_flush_tlb(vcpu);
1439442c 1740 vmcs_writel(GUEST_CR3, guest_cr3);
ad312c7c 1741 if (vcpu->arch.cr0 & X86_CR0_PE)
5fd86fcf 1742 vmx_fpu_deactivate(vcpu);
6aa8b732
AK		 1743}
1744
1745static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1746{
7ffd92c5 1747 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1439442c
SY		 1748 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1749
ad312c7c 1750 vcpu->arch.cr4 = cr4;
089d034e 1751 if (enable_ept)
1439442c
SY		 1752 ept_update_paging_mode_cr4(&hw_cr4, vcpu);
1753
1754 vmcs_writel(CR4_READ_SHADOW, cr4);
1755 vmcs_writel(GUEST_CR4, hw_cr4);
6aa8b732
AK		 1756}
1757
6aa8b732
AK		 1758static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1759{
1760 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1761
1762 return vmcs_readl(sf->base);
1763}
1764
1765static void vmx_get_segment(struct kvm_vcpu *vcpu,
1766 struct kvm_segment *var, int seg)
1767{
1768 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1769 u32 ar;
1770
1771 var->base = vmcs_readl(sf->base);
1772 var->limit = vmcs_read32(sf->limit);
1773 var->selector = vmcs_read16(sf->selector);
1774 ar = vmcs_read32(sf->ar_bytes);
9fd4a3b7 1775 if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
6aa8b732
AK		 1776 ar = 0;
1777 var->type = ar & 15;
1778 var->s = (ar >> 4) & 1;
1779 var->dpl = (ar >> 5) & 3;
1780 var->present = (ar >> 7) & 1;
1781 var->avl = (ar >> 12) & 1;
1782 var->l = (ar >> 13) & 1;
1783 var->db = (ar >> 14) & 1;
1784 var->g = (ar >> 15) & 1;
1785 var->unusable = (ar >> 16) & 1;
1786}
1787
2e4d2653
IE		 1788static int vmx_get_cpl(struct kvm_vcpu *vcpu)
1789{
2e4d2653
IE		 1790 if (!(vcpu->arch.cr0 & X86_CR0_PE)) /* if real mode */
1791 return 0;
1792
1793 if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */
1794 return 3;
1795
eab4b8aa 1796 return vmcs_read16(GUEST_CS_SELECTOR) & 3;
2e4d2653
IE		 1797}
1798
653e3108 1799static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 1800{
6aa8b732
AK		 1801 u32 ar;
1802
653e3108 1803 if (var->unusable)
6aa8b732
AK		 1804 ar = 1 << 16;
1805 else {
1806 ar = var->type & 15;
1807 ar |= (var->s & 1) << 4;
1808 ar |= (var->dpl & 3) << 5;
1809 ar |= (var->present & 1) << 7;
1810 ar |= (var->avl & 1) << 12;
1811 ar |= (var->l & 1) << 13;
1812 ar |= (var->db & 1) << 14;
1813 ar |= (var->g & 1) << 15;
1814 }
f7fbf1fd
UL		 1815 if (ar == 0) /* a 0 value means unusable */
1816 ar = AR_UNUSABLE_MASK;
653e3108
AK		 1817
1818 return ar;
1819}
1820
1821static void vmx_set_segment(struct kvm_vcpu *vcpu,
1822 struct kvm_segment *var, int seg)
1823{
7ffd92c5 1824 struct vcpu_vmx *vmx = to_vmx(vcpu);
653e3108
AK		 1825 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1826 u32 ar;
1827
7ffd92c5
AK		 1828 if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
1829 vmx->rmode.tr.selector = var->selector;
1830 vmx->rmode.tr.base = var->base;
1831 vmx->rmode.tr.limit = var->limit;
1832 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
653e3108
AK		 1833 return;
1834 }
1835 vmcs_writel(sf->base, var->base);
1836 vmcs_write32(sf->limit, var->limit);
1837 vmcs_write16(sf->selector, var->selector);
7ffd92c5 1838 if (vmx->rmode.vm86_active && var->s) {
653e3108
AK		 1839 /*
1840 * Hack real-mode segments into vm86 compatibility.
1841 */
1842 if (var->base == 0xffff0000 && var->selector == 0xf000)
1843 vmcs_writel(sf->base, 0xf0000);
1844 ar = 0xf3;
1845 } else
1846 ar = vmx_segment_access_rights(var);
3a624e29
NK		 1847
1848 /*
1849 * Fix the "Accessed" bit in AR field of segment registers for older
1850 * qemu binaries.
1851 * IA32 arch specifies that at the time of processor reset the
1852 * "Accessed" bit in the AR field of segment registers is 1. And qemu
1853 * is setting it to 0 in the usedland code. This causes invalid guest
1854 * state vmexit when "unrestricted guest" mode is turned on.
1855 * Fix for this setup issue in cpu_reset is being pushed in the qemu
1856 * tree. Newer qemu binaries with that qemu fix would not need this
1857 * kvm hack.
1858 */
1859 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
1860 ar |= 0x1; /* Accessed */
1861
6aa8b732
AK		 1862 vmcs_write32(sf->ar_bytes, ar);
1863}
1864
6aa8b732
AK		 1865static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
1866{
1867 u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
1868
1869 *db = (ar >> 14) & 1;
1870 *l = (ar >> 13) & 1;
1871}
1872
1873static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1874{
1875 dt->limit = vmcs_read32(GUEST_IDTR_LIMIT);
1876 dt->base = vmcs_readl(GUEST_IDTR_BASE);
1877}
1878
1879static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1880{
1881 vmcs_write32(GUEST_IDTR_LIMIT, dt->limit);
1882 vmcs_writel(GUEST_IDTR_BASE, dt->base);
1883}
1884
1885static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1886{
1887 dt->limit = vmcs_read32(GUEST_GDTR_LIMIT);
1888 dt->base = vmcs_readl(GUEST_GDTR_BASE);
1889}
1890
1891static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1892{
1893 vmcs_write32(GUEST_GDTR_LIMIT, dt->limit);
1894 vmcs_writel(GUEST_GDTR_BASE, dt->base);
1895}
1896
648dfaa7
MG		 1897static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
1898{
1899 struct kvm_segment var;
1900 u32 ar;
1901
1902 vmx_get_segment(vcpu, &var, seg);
1903 ar = vmx_segment_access_rights(&var);
1904
1905 if (var.base != (var.selector << 4))
1906 return false;
1907 if (var.limit != 0xffff)
1908 return false;
1909 if (ar != 0xf3)
1910 return false;
1911
1912 return true;
1913}
1914
1915static bool code_segment_valid(struct kvm_vcpu *vcpu)
1916{
1917 struct kvm_segment cs;
1918 unsigned int cs_rpl;
1919
1920 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
1921 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
1922
1872a3f4
AK		 1923 if (cs.unusable)
1924 return false;
648dfaa7
MG		 1925 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
1926 return false;
1927 if (!cs.s)
1928 return false;
1872a3f4 1929 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 1930 if (cs.dpl > cs_rpl)
1931 return false;
1872a3f4 1932 } else {
648dfaa7
MG		 1933 if (cs.dpl != cs_rpl)
1934 return false;
1935 }
1936 if (!cs.present)
1937 return false;
1938
1939 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
1940 return true;
1941}
1942
1943static bool stack_segment_valid(struct kvm_vcpu *vcpu)
1944{
1945 struct kvm_segment ss;
1946 unsigned int ss_rpl;
1947
1948 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
1949 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
1950
1872a3f4
AK		 1951 if (ss.unusable)
1952 return true;
1953 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 1954 return false;
1955 if (!ss.s)
1956 return false;
1957 if (ss.dpl != ss_rpl) /* DPL != RPL */
1958 return false;
1959 if (!ss.present)
1960 return false;
1961
1962 return true;
1963}
1964
1965static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
1966{
1967 struct kvm_segment var;
1968 unsigned int rpl;
1969
1970 vmx_get_segment(vcpu, &var, seg);
1971 rpl = var.selector & SELECTOR_RPL_MASK;
1972
1872a3f4
AK		 1973 if (var.unusable)
1974 return true;
648dfaa7
MG		 1975 if (!var.s)
1976 return false;
1977 if (!var.present)
1978 return false;
1979 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
1980 if (var.dpl < rpl) /* DPL < RPL */
1981 return false;
1982 }
1983
1984 /* TODO: Add other members to kvm_segment_field to allow checking for other access
1985 * rights flags
1986 */
1987 return true;
1988}
1989
1990static bool tr_valid(struct kvm_vcpu *vcpu)
1991{
1992 struct kvm_segment tr;
1993
1994 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
1995
1872a3f4
AK		 1996 if (tr.unusable)
1997 return false;
648dfaa7
MG		 1998 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
1999 return false;
1872a3f4 2000 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 2001 return false;
2002 if (!tr.present)
2003 return false;
2004
2005 return true;
2006}
2007
2008static bool ldtr_valid(struct kvm_vcpu *vcpu)
2009{
2010 struct kvm_segment ldtr;
2011
2012 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
2013
1872a3f4
AK		 2014 if (ldtr.unusable)
2015 return true;
648dfaa7
MG		 2016 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
2017 return false;
2018 if (ldtr.type != 2)
2019 return false;
2020 if (!ldtr.present)
2021 return false;
2022
2023 return true;
2024}
2025
2026static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
2027{
2028 struct kvm_segment cs, ss;
2029
2030 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2031 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2032
2033 return ((cs.selector & SELECTOR_RPL_MASK) ==
2034 (ss.selector & SELECTOR_RPL_MASK));
2035}
2036
2037/*
2038 * Check if guest state is valid. Returns true if valid, false if
2039 * not.
2040 * We assume that registers are always usable
2041 */
2042static bool guest_state_valid(struct kvm_vcpu *vcpu)
2043{
2044 /* real mode guest state checks */
2045 if (!(vcpu->arch.cr0 & X86_CR0_PE)) {
2046 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
2047 return false;
2048 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
2049 return false;
2050 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
2051 return false;
2052 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
2053 return false;
2054 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
2055 return false;
2056 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
2057 return false;
2058 } else {
2059 /* protected mode guest state checks */
2060 if (!cs_ss_rpl_check(vcpu))
2061 return false;
2062 if (!code_segment_valid(vcpu))
2063 return false;
2064 if (!stack_segment_valid(vcpu))
2065 return false;
2066 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
2067 return false;
2068 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
2069 return false;
2070 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
2071 return false;
2072 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
2073 return false;
2074 if (!tr_valid(vcpu))
2075 return false;
2076 if (!ldtr_valid(vcpu))
2077 return false;
2078 }
2079 /* TODO:
2080 * - Add checks on RIP
2081 * - Add checks on RFLAGS
2082 */
2083
2084 return true;
2085}
2086
d77c26fc 2087static int init_rmode_tss(struct kvm *kvm)
6aa8b732 2088{
6aa8b732 2089 gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
195aefde 2090 u16 data = 0;
10589a46 2091 int ret = 0;
195aefde 2092 int r;
6aa8b732 2093
195aefde
IE		 2094 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2095 if (r < 0)
10589a46 2096 goto out;
195aefde 2097 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 2098 r = kvm_write_guest_page(kvm, fn++, &data,
2099 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 2100 if (r < 0)
10589a46 2101 goto out;
195aefde
IE		 2102 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
2103 if (r < 0)
10589a46 2104 goto out;
195aefde
IE		 2105 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2106 if (r < 0)
10589a46 2107 goto out;
195aefde 2108 data = ~0;
10589a46
MT		 2109 r = kvm_write_guest_page(kvm, fn, &data,
2110 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
2111 sizeof(u8));
195aefde 2112 if (r < 0)
10589a46
MT		 2113 goto out;
2114
2115 ret = 1;
2116out:
10589a46 2117 return ret;
6aa8b732
AK		 2118}
2119
b7ebfb05
SY		 2120static int init_rmode_identity_map(struct kvm *kvm)
2121{
2122 int i, r, ret;
2123 pfn_t identity_map_pfn;
2124 u32 tmp;
2125
089d034e 2126 if (!enable_ept)
b7ebfb05
SY		 2127 return 1;
2128 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
2129 printk(KERN_ERR "EPT: identity-mapping pagetable "
2130 "haven't been allocated!\n");
2131 return 0;
2132 }
2133 if (likely(kvm->arch.ept_identity_pagetable_done))
2134 return 1;
2135 ret = 0;
b927a3ce 2136 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
b7ebfb05
SY		 2137 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
2138 if (r < 0)
2139 goto out;
2140 /* Set up identity-mapping pagetable for EPT in real mode */
2141 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
2142 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
2143 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
2144 r = kvm_write_guest_page(kvm, identity_map_pfn,
2145 &tmp, i * sizeof(tmp), sizeof(tmp));
2146 if (r < 0)
2147 goto out;
2148 }
2149 kvm->arch.ept_identity_pagetable_done = true;
2150 ret = 1;
2151out:
2152 return ret;
2153}
2154
6aa8b732
AK		 2155static void seg_setup(int seg)
2156{
2157 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 2158 unsigned int ar;
6aa8b732
AK		 2159
2160 vmcs_write16(sf->selector, 0);
2161 vmcs_writel(sf->base, 0);
2162 vmcs_write32(sf->limit, 0xffff);
3a624e29
NK		 2163 if (enable_unrestricted_guest) {
2164 ar = 0x93;
2165 if (seg == VCPU_SREG_CS)
2166 ar |= 0x08; /* code segment */
2167 } else
2168 ar = 0xf3;
2169
2170 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 2171}
2172
f78e0e2e
SY		 2173static int alloc_apic_access_page(struct kvm *kvm)
2174{
2175 struct kvm_userspace_memory_region kvm_userspace_mem;
2176 int r = 0;
2177
72dc67a6 2178 down_write(&kvm->slots_lock);
bfc6d222 2179 if (kvm->arch.apic_access_page)
f78e0e2e
SY		 2180 goto out;
2181 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
2182 kvm_userspace_mem.flags = 0;
2183 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
2184 kvm_userspace_mem.memory_size = PAGE_SIZE;
2185 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2186 if (r)
2187 goto out;
72dc67a6 2188
bfc6d222 2189 kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
f78e0e2e 2190out:
72dc67a6 2191 up_write(&kvm->slots_lock);
f78e0e2e
SY		 2192 return r;
2193}
2194
b7ebfb05
SY		 2195static int alloc_identity_pagetable(struct kvm *kvm)
2196{
2197 struct kvm_userspace_memory_region kvm_userspace_mem;
2198 int r = 0;
2199
2200 down_write(&kvm->slots_lock);
2201 if (kvm->arch.ept_identity_pagetable)
2202 goto out;
2203 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
2204 kvm_userspace_mem.flags = 0;
b927a3ce
SY		 2205 kvm_userspace_mem.guest_phys_addr =
2206 kvm->arch.ept_identity_map_addr;
b7ebfb05
SY		 2207 kvm_userspace_mem.memory_size = PAGE_SIZE;
2208 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2209 if (r)
2210 goto out;
2211
b7ebfb05 2212 kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
b927a3ce 2213 kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
b7ebfb05
SY		 2214out:
2215 up_write(&kvm->slots_lock);
2216 return r;
2217}
2218
2384d2b3
SY		 2219static void allocate_vpid(struct vcpu_vmx *vmx)
2220{
2221 int vpid;
2222
2223 vmx->vpid = 0;
919818ab 2224 if (!enable_vpid)
2384d2b3
SY		 2225 return;
2226 spin_lock(&vmx_vpid_lock);
2227 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
2228 if (vpid < VMX_NR_VPIDS) {
2229 vmx->vpid = vpid;
2230 __set_bit(vpid, vmx_vpid_bitmap);
2231 }
2232 spin_unlock(&vmx_vpid_lock);
2233}
2234
5897297b 2235static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
25c5f225 2236{
3e7c73e9 2237 int f = sizeof(unsigned long);
25c5f225
SY		 2238
2239 if (!cpu_has_vmx_msr_bitmap())
2240 return;
2241
2242 /*
2243 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2244 * have the write-low and read-high bitmap offsets the wrong way round.
2245 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2246 */
25c5f225 2247 if (msr <= 0x1fff) {
3e7c73e9
AK		 2248 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
2249 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
25c5f225
SY		 2250 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2251 msr &= 0x1fff;
3e7c73e9
AK		 2252 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
2253 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
25c5f225 2254 }
25c5f225
SY		 2255}
2256
5897297b
AK		 2257static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
2258{
2259 if (!longmode_only)
2260 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
2261 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
2262}
2263
6aa8b732
AK		 2264/*
2265 * Sets up the vmcs for emulated real mode.
2266 */
8b9cf98c 2267static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 2268{
468d472f 2269 u32 host_sysenter_cs, msr_low, msr_high;
6aa8b732 2270 u32 junk;
53f658b3 2271 u64 host_pat, tsc_this, tsc_base;
6aa8b732
AK		 2272 unsigned long a;
2273 struct descriptor_table dt;
2274 int i;
cd2276a7 2275 unsigned long kvm_vmx_return;
6e5d865c 2276 u32 exec_control;
6aa8b732 2277
6aa8b732 2278 /* I/O */
3e7c73e9
AK		 2279 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
2280 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 2281
25c5f225 2282 if (cpu_has_vmx_msr_bitmap())
5897297b 2283 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 2284
6aa8b732
AK		 2285 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
2286
6aa8b732 2287 /* Control */
1c3d14fe
YS		 2288 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
2289 vmcs_config.pin_based_exec_ctrl);
6e5d865c
YS		 2290
2291 exec_control = vmcs_config.cpu_based_exec_ctrl;
2292 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
2293 exec_control &= ~CPU_BASED_TPR_SHADOW;
2294#ifdef CONFIG_X86_64
2295 exec_control |= CPU_BASED_CR8_STORE_EXITING |
2296 CPU_BASED_CR8_LOAD_EXITING;
2297#endif
2298 }
089d034e 2299 if (!enable_ept)
d56f546d 2300 exec_control |= CPU_BASED_CR3_STORE_EXITING |
83dbc83a
MT		 2301 CPU_BASED_CR3_LOAD_EXITING |
2302 CPU_BASED_INVLPG_EXITING;
6e5d865c 2303 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
6aa8b732 2304
83ff3b9d
SY		 2305 if (cpu_has_secondary_exec_ctrls()) {
2306 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
2307 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2308 exec_control &=
2309 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2384d2b3
SY		 2310 if (vmx->vpid == 0)
2311 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
046d8710 2312 if (!enable_ept) {
d56f546d 2313 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
046d8710
SY		 2314 enable_unrestricted_guest = 0;
2315 }
3a624e29
NK		 2316 if (!enable_unrestricted_guest)
2317 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4b8d54f9
ZE		 2318 if (!ple_gap)
2319 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
83ff3b9d
SY		 2320 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
2321 }
f78e0e2e 2322
4b8d54f9
ZE		 2323 if (ple_gap) {
2324 vmcs_write32(PLE_GAP, ple_gap);
2325 vmcs_write32(PLE_WINDOW, ple_window);
2326 }
2327
c7addb90
AK		 2328 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
2329 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
6aa8b732
AK		 2330 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
2331
2332 vmcs_writel(HOST_CR0, read_cr0()); /* 22.2.3 */
2333 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
2334 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
2335
2336 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
2337 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2338 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
d6e88aec
AK		 2339 vmcs_write16(HOST_FS_SELECTOR, kvm_read_fs()); /* 22.2.4 */
2340 vmcs_write16(HOST_GS_SELECTOR, kvm_read_gs()); /* 22.2.4 */
6aa8b732 2341 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
05b3e0c2 2342#ifdef CONFIG_X86_64
6aa8b732
AK		 2343 rdmsrl(MSR_FS_BASE, a);
2344 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
2345 rdmsrl(MSR_GS_BASE, a);
2346 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
2347#else
2348 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
2349 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
2350#endif
2351
2352 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
2353
d6e88aec 2354 kvm_get_idt(&dt);
6aa8b732
AK		 2355 vmcs_writel(HOST_IDTR_BASE, dt.base); /* 22.2.4 */
2356
d77c26fc 2357 asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
cd2276a7 2358 vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2cc51560
ED		 2359 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
2360 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
2361 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
6aa8b732
AK		 2362
2363 rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
2364 vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
2365 rdmsrl(MSR_IA32_SYSENTER_ESP, a);
2366 vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */
2367 rdmsrl(MSR_IA32_SYSENTER_EIP, a);
2368 vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */
2369
468d472f
SY		 2370 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
2371 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2372 host_pat = msr_low | ((u64) msr_high << 32);
2373 vmcs_write64(HOST_IA32_PAT, host_pat);
2374 }
2375 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2376 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2377 host_pat = msr_low | ((u64) msr_high << 32);
2378 /* Write the default value follow host pat */
2379 vmcs_write64(GUEST_IA32_PAT, host_pat);
2380 /* Keep arch.pat sync with GUEST_IA32_PAT */
2381 vmx->vcpu.arch.pat = host_pat;
2382 }
2383
6aa8b732
AK		 2384 for (i = 0; i < NR_VMX_MSR; ++i) {
2385 u32 index = vmx_msr_index[i];
2386 u32 data_low, data_high;
2387 u64 data;
a2fa3e9f 2388 int j = vmx->nmsrs;
6aa8b732
AK		 2389
2390 if (rdmsr_safe(index, &data_low, &data_high) < 0)
2391 continue;
432bd6cb
AK		 2392 if (wrmsr_safe(index, data_low, data_high) < 0)
2393 continue;
6aa8b732 2394 data = data_low | ((u64)data_high << 32);
26bb0981
AK		 2395 vmx->guest_msrs[j].index = i;
2396 vmx->guest_msrs[j].data = 0;
a2fa3e9f 2397 ++vmx->nmsrs;
6aa8b732 2398 }
6aa8b732 2399
1c3d14fe 2400 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 2401
2402 /* 22.2.1, 20.8.1 */
1c3d14fe
YS		 2403 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
2404
e00c8cf2
AK		 2405 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
2406 vmcs_writel(CR4_GUEST_HOST_MASK, KVM_GUEST_CR4_MASK);
2407
53f658b3
MT		 2408 tsc_base = vmx->vcpu.kvm->arch.vm_init_tsc;
2409 rdtscll(tsc_this);
2410 if (tsc_this < vmx->vcpu.kvm->arch.vm_init_tsc)
2411 tsc_base = tsc_this;
2412
2413 guest_write_tsc(0, tsc_base);
f78e0e2e 2414
e00c8cf2
AK		 2415 return 0;
2416}
2417
b7ebfb05
SY		 2418static int init_rmode(struct kvm *kvm)
2419{
2420 if (!init_rmode_tss(kvm))
2421 return 0;
2422 if (!init_rmode_identity_map(kvm))
2423 return 0;
2424 return 1;
2425}
2426
e00c8cf2
AK		 2427static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
2428{
2429 struct vcpu_vmx *vmx = to_vmx(vcpu);
2430 u64 msr;
2431 int ret;
2432
5fdbf976 2433 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
3200f405 2434 down_read(&vcpu->kvm->slots_lock);
b7ebfb05 2435 if (!init_rmode(vmx->vcpu.kvm)) {
e00c8cf2
AK		 2436 ret = -ENOMEM;
2437 goto out;
2438 }
2439
7ffd92c5 2440 vmx->rmode.vm86_active = 0;
e00c8cf2 2441
3b86cd99
JK		 2442 vmx->soft_vnmi_blocked = 0;
2443
ad312c7c 2444 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 2445 kvm_set_cr8(&vmx->vcpu, 0);
e00c8cf2 2446 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 2447 if (kvm_vcpu_is_bsp(&vmx->vcpu))
e00c8cf2
AK		 2448 msr |= MSR_IA32_APICBASE_BSP;
2449 kvm_set_apic_base(&vmx->vcpu, msr);
2450
2451 fx_init(&vmx->vcpu);
2452
5706be0d 2453 seg_setup(VCPU_SREG_CS);
e00c8cf2
AK		 2454 /*
2455 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2456 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
2457 */
c5af89b6 2458 if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
e00c8cf2
AK		 2459 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2460 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2461 } else {
ad312c7c
ZX		 2462 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2463 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
e00c8cf2 2464 }
e00c8cf2
AK		 2465
2466 seg_setup(VCPU_SREG_DS);
2467 seg_setup(VCPU_SREG_ES);
2468 seg_setup(VCPU_SREG_FS);
2469 seg_setup(VCPU_SREG_GS);
2470 seg_setup(VCPU_SREG_SS);
2471
2472 vmcs_write16(GUEST_TR_SELECTOR, 0);
2473 vmcs_writel(GUEST_TR_BASE, 0);
2474 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
2475 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2476
2477 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
2478 vmcs_writel(GUEST_LDTR_BASE, 0);
2479 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
2480 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
2481
2482 vmcs_write32(GUEST_SYSENTER_CS, 0);
2483 vmcs_writel(GUEST_SYSENTER_ESP, 0);
2484 vmcs_writel(GUEST_SYSENTER_EIP, 0);
2485
2486 vmcs_writel(GUEST_RFLAGS, 0x02);
c5af89b6 2487 if (kvm_vcpu_is_bsp(&vmx->vcpu))
5fdbf976 2488 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 2489 else
5fdbf976
MT		 2490 kvm_rip_write(vcpu, 0);
2491 kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
e00c8cf2 2492
e00c8cf2
AK		 2493 vmcs_writel(GUEST_DR7, 0x400);
2494
2495 vmcs_writel(GUEST_GDTR_BASE, 0);
2496 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
2497
2498 vmcs_writel(GUEST_IDTR_BASE, 0);
2499 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
2500
2501 vmcs_write32(GUEST_ACTIVITY_STATE, 0);
2502 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
2503 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
2504
e00c8cf2
AK		 2505 /* Special registers */
2506 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
2507
2508 setup_msrs(vmx);
2509
6aa8b732
AK		 2510 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
2511
f78e0e2e
SY		 2512 if (cpu_has_vmx_tpr_shadow()) {
2513 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
2514 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
2515 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
ad312c7c 2516 page_to_phys(vmx->vcpu.arch.apic->regs_page));
f78e0e2e
SY		 2517 vmcs_write32(TPR_THRESHOLD, 0);
2518 }
2519
2520 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2521 vmcs_write64(APIC_ACCESS_ADDR,
bfc6d222 2522 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
6aa8b732 2523
2384d2b3
SY		 2524 if (vmx->vpid != 0)
2525 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2526
fa40052c 2527 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
ad312c7c 2528 vmx_set_cr0(&vmx->vcpu, vmx->vcpu.arch.cr0); /* enter rmode */
8b9cf98c 2529 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 2530 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 2531 vmx_fpu_activate(&vmx->vcpu);
2532 update_exception_bitmap(&vmx->vcpu);
6aa8b732 2533
2384d2b3
SY		 2534 vpid_sync_vcpu_all(vmx);
2535
3200f405 2536 ret = 0;
6aa8b732 2537
a89a8fb9
MG		 2538 /* HACK: Don't enable emulation on guest boot/reset */
2539 vmx->emulation_required = 0;
2540
6aa8b732 2541out:
3200f405 2542 up_read(&vcpu->kvm->slots_lock);
6aa8b732
AK		 2543 return ret;
2544}
2545
3b86cd99
JK		 2546static void enable_irq_window(struct kvm_vcpu *vcpu)
2547{
2548 u32 cpu_based_vm_exec_control;
2549
2550 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2551 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2552 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2553}
2554
2555static void enable_nmi_window(struct kvm_vcpu *vcpu)
2556{
2557 u32 cpu_based_vm_exec_control;
2558
2559 if (!cpu_has_virtual_nmis()) {
2560 enable_irq_window(vcpu);
2561 return;
2562 }
2563
2564 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2565 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
2566 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2567}
2568
66fd3f7f 2569static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 2570{
9c8cba37 2571 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 2572 uint32_t intr;
2573 int irq = vcpu->arch.interrupt.nr;
9c8cba37 2574
229456fc 2575 trace_kvm_inj_virq(irq);
2714d1d3 2576
fa89a817 2577 ++vcpu->stat.irq_injections;
7ffd92c5 2578 if (vmx->rmode.vm86_active) {
9c8cba37
AK		 2579 vmx->rmode.irq.pending = true;
2580 vmx->rmode.irq.vector = irq;
5fdbf976 2581 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
ae0bb3e0
GN		 2582 if (vcpu->arch.interrupt.soft)
2583 vmx->rmode.irq.rip +=
2584 vmx->vcpu.arch.event_exit_inst_len;
9c5623e3
AK		 2585 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2586 irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK);
2587 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
5fdbf976 2588 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
85f455f7
ED		 2589 return;
2590 }
66fd3f7f
GN		 2591 intr = irq | INTR_INFO_VALID_MASK;
2592 if (vcpu->arch.interrupt.soft) {
2593 intr |= INTR_TYPE_SOFT_INTR;
2594 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2595 vmx->vcpu.arch.event_exit_inst_len);
2596 } else
2597 intr |= INTR_TYPE_EXT_INTR;
2598 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
85f455f7
ED		 2599}
2600
f08864b4
SY		 2601static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
2602{
66a5a347
JK		 2603 struct vcpu_vmx *vmx = to_vmx(vcpu);
2604
3b86cd99
JK		 2605 if (!cpu_has_virtual_nmis()) {
2606 /*
2607 * Tracking the NMI-blocked state in software is built upon
2608 * finding the next open IRQ window. This, in turn, depends on
2609 * well-behaving guests: They have to keep IRQs disabled at
2610 * least as long as the NMI handler runs. Otherwise we may
2611 * cause NMI nesting, maybe breaking the guest. But as this is
2612 * highly unlikely, we can live with the residual risk.
2613 */
2614 vmx->soft_vnmi_blocked = 1;
2615 vmx->vnmi_blocked_time = 0;
2616 }
2617
487b391d 2618 ++vcpu->stat.nmi_injections;
7ffd92c5 2619 if (vmx->rmode.vm86_active) {
66a5a347
JK		 2620 vmx->rmode.irq.pending = true;
2621 vmx->rmode.irq.vector = NMI_VECTOR;
2622 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2623 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2624 NMI_VECTOR | INTR_TYPE_SOFT_INTR |
2625 INTR_INFO_VALID_MASK);
2626 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2627 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2628 return;
2629 }
f08864b4
SY		 2630 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2631 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
f08864b4
SY		 2632}
2633
c4282df9 2634static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
33f089ca 2635{
3b86cd99 2636 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
c4282df9 2637 return 0;
33f089ca 2638
c4282df9
GN		 2639 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2640 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS |
2641 GUEST_INTR_STATE_NMI));
33f089ca
JK		 2642}
2643
3cfc3092
JK		 2644static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
2645{
2646 if (!cpu_has_virtual_nmis())
2647 return to_vmx(vcpu)->soft_vnmi_blocked;
2648 else
2649 return !!(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2650 GUEST_INTR_STATE_NMI);
2651}
2652
2653static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
2654{
2655 struct vcpu_vmx *vmx = to_vmx(vcpu);
2656
2657 if (!cpu_has_virtual_nmis()) {
2658 if (vmx->soft_vnmi_blocked != masked) {
2659 vmx->soft_vnmi_blocked = masked;
2660 vmx->vnmi_blocked_time = 0;
2661 }
2662 } else {
2663 if (masked)
2664 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
2665 GUEST_INTR_STATE_NMI);
2666 else
2667 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
2668 GUEST_INTR_STATE_NMI);
2669 }
2670}
2671
78646121
GN		 2672static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
2673{
c4282df9
GN		 2674 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2675 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2676 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 2677}
2678
cbc94022
IE		 2679static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
2680{
2681 int ret;
2682 struct kvm_userspace_memory_region tss_mem = {
6fe63979 2683 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 2684 .guest_phys_addr = addr,
2685 .memory_size = PAGE_SIZE * 3,
2686 .flags = 0,
2687 };
2688
2689 ret = kvm_set_memory_region(kvm, &tss_mem, 0);
2690 if (ret)
2691 return ret;
bfc6d222 2692 kvm->arch.tss_addr = addr;
cbc94022
IE		 2693 return 0;
2694}
2695
6aa8b732
AK		 2696static int handle_rmode_exception(struct kvm_vcpu *vcpu,
2697 int vec, u32 err_code)
2698{
b3f37707
NK		 2699 /*
2700 * Instruction with address size override prefix opcode 0x67
2701 * Cause the #SS fault with 0 error code in VM86 mode.
2702 */
2703 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
851ba692 2704 if (emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE)
6aa8b732 2705 return 1;
77ab6db0
JK		 2706 /*
2707 * Forward all other exceptions that are valid in real mode.
2708 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
2709 * the required debugging infrastructure rework.
2710 */
2711 switch (vec) {
77ab6db0 2712 case DB_VECTOR:
d0bfb940
JK		 2713 if (vcpu->guest_debug &
2714 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
2715 return 0;
2716 kvm_queue_exception(vcpu, vec);
2717 return 1;
77ab6db0 2718 case BP_VECTOR:
d0bfb940
JK		 2719 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2720 return 0;
2721 /* fall through */
2722 case DE_VECTOR:
77ab6db0
JK		 2723 case OF_VECTOR:
2724 case BR_VECTOR:
2725 case UD_VECTOR:
2726 case DF_VECTOR:
2727 case SS_VECTOR:
2728 case GP_VECTOR:
2729 case MF_VECTOR:
2730 kvm_queue_exception(vcpu, vec);
2731 return 1;
2732 }
6aa8b732
AK		 2733 return 0;
2734}
2735
a0861c02
AK		 2736/*
2737 * Trigger machine check on the host. We assume all the MSRs are already set up
2738 * by the CPU and that we still run on the same CPU as the MCE occurred on.
2739 * We pass a fake environment to the machine check handler because we want
2740 * the guest to be always treated like user space, no matter what context
2741 * it used internally.
2742 */
2743static void kvm_machine_check(void)
2744{
2745#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
2746 struct pt_regs regs = {
2747 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
2748 .flags = X86_EFLAGS_IF,
2749 };
2750
2751 do_machine_check(&regs, 0);
2752#endif
2753}
2754
851ba692 2755static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK		 2756{
2757 /* already handled by vcpu_run */
2758 return 1;
2759}
2760
851ba692 2761static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 2762{
1155f76a 2763 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 2764 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 2765 u32 intr_info, ex_no, error_code;
42dbaa5a 2766 unsigned long cr2, rip, dr6;
6aa8b732
AK		 2767 u32 vect_info;
2768 enum emulation_result er;
2769
1155f76a 2770 vect_info = vmx->idt_vectoring_info;
6aa8b732
AK		 2771 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
2772
a0861c02 2773 if (is_machine_check(intr_info))
851ba692 2774 return handle_machine_check(vcpu);
a0861c02 2775
6aa8b732 2776 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
65ac7264
AK		 2777 !is_page_fault(intr_info)) {
2778 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2779 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
2780 vcpu->run->internal.ndata = 2;
2781 vcpu->run->internal.data[0] = vect_info;
2782 vcpu->run->internal.data[1] = intr_info;
2783 return 0;
2784 }
6aa8b732 2785
e4a41889 2786 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 2787 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 2788
2789 if (is_no_device(intr_info)) {
5fd86fcf 2790 vmx_fpu_activate(vcpu);
2ab455cc
AL		 2791 return 1;
2792 }
2793
7aa81cc0 2794 if (is_invalid_opcode(intr_info)) {
851ba692 2795 er = emulate_instruction(vcpu, 0, 0, EMULTYPE_TRAP_UD);
7aa81cc0 2796 if (er != EMULATE_DONE)
7ee5d940 2797 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 2798 return 1;
2799 }
2800
6aa8b732 2801 error_code = 0;
5fdbf976 2802 rip = kvm_rip_read(vcpu);
2e11384c 2803 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732
AK		 2804 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
2805 if (is_page_fault(intr_info)) {
1439442c 2806 /* EPT won't cause page fault directly */
089d034e 2807 if (enable_ept)
1439442c 2808 BUG();
6aa8b732 2809 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT		 2810 trace_kvm_page_fault(cr2, error_code);
2811
3298b75c 2812 if (kvm_event_needs_reinjection(vcpu))
577bdc49 2813 kvm_mmu_unprotect_page_virt(vcpu, cr2);
3067714c 2814 return kvm_mmu_page_fault(vcpu, cr2, error_code);
6aa8b732
AK		 2815 }
2816
7ffd92c5 2817 if (vmx->rmode.vm86_active &&
6aa8b732 2818 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
72d6e5a0 2819 error_code)) {
ad312c7c
ZX		 2820 if (vcpu->arch.halt_request) {
2821 vcpu->arch.halt_request = 0;
72d6e5a0
AK		 2822 return kvm_emulate_halt(vcpu);
2823 }
6aa8b732 2824 return 1;
72d6e5a0 2825 }
6aa8b732 2826
d0bfb940 2827 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
42dbaa5a
JK		 2828 switch (ex_no) {
2829 case DB_VECTOR:
2830 dr6 = vmcs_readl(EXIT_QUALIFICATION);
2831 if (!(vcpu->guest_debug &
2832 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
2833 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
2834 kvm_queue_exception(vcpu, DB_VECTOR);
2835 return 1;
2836 }
2837 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
2838 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
2839 /* fall through */
2840 case BP_VECTOR:
6aa8b732 2841 kvm_run->exit_reason = KVM_EXIT_DEBUG;
d0bfb940
JK		 2842 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
2843 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 2844 break;
2845 default:
d0bfb940
JK		 2846 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
2847 kvm_run->ex.exception = ex_no;
2848 kvm_run->ex.error_code = error_code;
42dbaa5a 2849 break;
6aa8b732 2850 }
6aa8b732
AK		 2851 return 0;
2852}
2853
851ba692 2854static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 2855{
1165f5fe 2856 ++vcpu->stat.irq_exits;
6aa8b732
AK		 2857 return 1;
2858}
2859
851ba692 2860static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 2861{
851ba692 2862 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK		 2863 return 0;
2864}
6aa8b732 2865
851ba692 2866static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 2867{
bfdaab09 2868 unsigned long exit_qualification;
34c33d16 2869 int size, in, string;
039576c0 2870 unsigned port;
6aa8b732 2871
1165f5fe 2872 ++vcpu->stat.io_exits;
bfdaab09 2873 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 2874 string = (exit_qualification & 16) != 0;
e70669ab
LV		 2875
2876 if (string) {
851ba692 2877 if (emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DO_MMIO)
e70669ab
LV		 2878 return 0;
2879 return 1;
2880 }
2881
2882 size = (exit_qualification & 7) + 1;
2883 in = (exit_qualification & 8) != 0;
039576c0 2884 port = exit_qualification >> 16;
e70669ab 2885
e93f36bc 2886 skip_emulated_instruction(vcpu);
851ba692 2887 return kvm_emulate_pio(vcpu, in, size, port);
6aa8b732
AK		 2888}
2889
102d8325
IM		 2890static void
2891vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2892{
2893 /*
2894 * Patch in the VMCALL instruction:
2895 */
2896 hypercall[0] = 0x0f;
2897 hypercall[1] = 0x01;
2898 hypercall[2] = 0xc1;
102d8325
IM		 2899}
2900
851ba692 2901static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 2902{
229456fc 2903 unsigned long exit_qualification, val;
6aa8b732
AK		 2904 int cr;
2905 int reg;
2906
bfdaab09 2907 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 2908 cr = exit_qualification & 15;
2909 reg = (exit_qualification >> 8) & 15;
2910 switch ((exit_qualification >> 4) & 3) {
2911 case 0: /* mov to cr */
229456fc
MT		 2912 val = kvm_register_read(vcpu, reg);
2913 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 2914 switch (cr) {
2915 case 0:
229456fc 2916 kvm_set_cr0(vcpu, val);
6aa8b732
AK		 2917 skip_emulated_instruction(vcpu);
2918 return 1;
2919 case 3:
229456fc 2920 kvm_set_cr3(vcpu, val);
6aa8b732
AK		 2921 skip_emulated_instruction(vcpu);
2922 return 1;
2923 case 4:
229456fc 2924 kvm_set_cr4(vcpu, val);
6aa8b732
AK		 2925 skip_emulated_instruction(vcpu);
2926 return 1;
0a5fff19
GN		 2927 case 8: {
2928 u8 cr8_prev = kvm_get_cr8(vcpu);
2929 u8 cr8 = kvm_register_read(vcpu, reg);
2930 kvm_set_cr8(vcpu, cr8);
2931 skip_emulated_instruction(vcpu);
2932 if (irqchip_in_kernel(vcpu->kvm))
2933 return 1;
2934 if (cr8_prev <= cr8)
2935 return 1;
851ba692 2936 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 2937 return 0;
2938 }
6aa8b732
AK		 2939 };
2940 break;
25c4c276 2941 case 2: /* clts */
5fd86fcf 2942 vmx_fpu_deactivate(vcpu);
ad312c7c
ZX		 2943 vcpu->arch.cr0 &= ~X86_CR0_TS;
2944 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf 2945 vmx_fpu_activate(vcpu);
25c4c276
AL		 2946 skip_emulated_instruction(vcpu);
2947 return 1;
6aa8b732
AK		 2948 case 1: /*mov from cr*/
2949 switch (cr) {
2950 case 3:
5fdbf976 2951 kvm_register_write(vcpu, reg, vcpu->arch.cr3);
229456fc 2952 trace_kvm_cr_read(cr, vcpu->arch.cr3);
6aa8b732
AK		 2953 skip_emulated_instruction(vcpu);
2954 return 1;
2955 case 8:
229456fc
MT		 2956 val = kvm_get_cr8(vcpu);
2957 kvm_register_write(vcpu, reg, val);
2958 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 2959 skip_emulated_instruction(vcpu);
2960 return 1;
2961 }
2962 break;
2963 case 3: /* lmsw */
2d3ad1f4 2964 kvm_lmsw(vcpu, (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f);
6aa8b732
AK		 2965
2966 skip_emulated_instruction(vcpu);
2967 return 1;
2968 default:
2969 break;
2970 }
851ba692 2971 vcpu->run->exit_reason = 0;
f0242478 2972 pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 2973 (int)(exit_qualification >> 4) & 3, cr);
2974 return 0;
2975}
2976
851ba692 2977static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 2978{
bfdaab09 2979 unsigned long exit_qualification;
6aa8b732
AK		 2980 unsigned long val;
2981 int dr, reg;
2982
0a79b009
AK		 2983 if (!kvm_require_cpl(vcpu, 0))
2984 return 1;
42dbaa5a
JK		 2985 dr = vmcs_readl(GUEST_DR7);
2986 if (dr & DR7_GD) {
2987 /*
2988 * As the vm-exit takes precedence over the debug trap, we
2989 * need to emulate the latter, either for the host or the
2990 * guest debugging itself.
2991 */
2992 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692
AK		 2993 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
2994 vcpu->run->debug.arch.dr7 = dr;
2995 vcpu->run->debug.arch.pc =
42dbaa5a
JK		 2996 vmcs_readl(GUEST_CS_BASE) +
2997 vmcs_readl(GUEST_RIP);
851ba692
AK		 2998 vcpu->run->debug.arch.exception = DB_VECTOR;
2999 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 3000 return 0;
3001 } else {
3002 vcpu->arch.dr7 &= ~DR7_GD;
3003 vcpu->arch.dr6 |= DR6_BD;
3004 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
3005 kvm_queue_exception(vcpu, DB_VECTOR);
3006 return 1;
3007 }
3008 }
3009
bfdaab09 3010 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
42dbaa5a
JK		 3011 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
3012 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
3013 if (exit_qualification & TYPE_MOV_FROM_DR) {
6aa8b732 3014 switch (dr) {
42dbaa5a
JK		 3015 case 0 ... 3:
3016 val = vcpu->arch.db[dr];
3017 break;
6aa8b732 3018 case 6:
42dbaa5a 3019 val = vcpu->arch.dr6;
6aa8b732
AK		 3020 break;
3021 case 7:
42dbaa5a 3022 val = vcpu->arch.dr7;
6aa8b732
AK		 3023 break;
3024 default:
3025 val = 0;
3026 }
5fdbf976 3027 kvm_register_write(vcpu, reg, val);
6aa8b732 3028 } else {
42dbaa5a
JK		 3029 val = vcpu->arch.regs[reg];
3030 switch (dr) {
3031 case 0 ... 3:
3032 vcpu->arch.db[dr] = val;
3033 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
3034 vcpu->arch.eff_db[dr] = val;
3035 break;
3036 case 4 ... 5:
3037 if (vcpu->arch.cr4 & X86_CR4_DE)
3038 kvm_queue_exception(vcpu, UD_VECTOR);
3039 break;
3040 case 6:
3041 if (val & 0xffffffff00000000ULL) {
3042 kvm_queue_exception(vcpu, GP_VECTOR);
3043 break;
3044 }
3045 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
3046 break;
3047 case 7:
3048 if (val & 0xffffffff00000000ULL) {
3049 kvm_queue_exception(vcpu, GP_VECTOR);
3050 break;
3051 }
3052 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
3053 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
3054 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
3055 vcpu->arch.switch_db_regs =
3056 (val & DR7_BP_EN_MASK);
3057 }
3058 break;
3059 }
6aa8b732 3060 }
6aa8b732
AK		 3061 skip_emulated_instruction(vcpu);
3062 return 1;
3063}
3064
851ba692 3065static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 3066{
06465c5a
AK		 3067 kvm_emulate_cpuid(vcpu);
3068 return 1;
6aa8b732
AK		 3069}
3070
851ba692 3071static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 3072{
ad312c7c 3073 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 3074 u64 data;
3075
3076 if (vmx_get_msr(vcpu, ecx, &data)) {
c1a5d4f9 3077 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 3078 return 1;
3079 }
3080
229456fc 3081 trace_kvm_msr_read(ecx, data);
2714d1d3 3082
6aa8b732 3083 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 3084 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
3085 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 3086 skip_emulated_instruction(vcpu);
3087 return 1;
3088}
3089
851ba692 3090static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 3091{
ad312c7c
ZX		 3092 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3093 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
3094 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732 3095
229456fc 3096 trace_kvm_msr_write(ecx, data);
2714d1d3 3097
6aa8b732 3098 if (vmx_set_msr(vcpu, ecx, data) != 0) {
c1a5d4f9 3099 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 3100 return 1;
3101 }
3102
3103 skip_emulated_instruction(vcpu);
3104 return 1;
3105}
3106
851ba692 3107static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c
YS		 3108{
3109 return 1;
3110}
3111
851ba692 3112static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 3113{
85f455f7
ED		 3114 u32 cpu_based_vm_exec_control;
3115
3116 /* clear pending irq */
3117 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3118 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
3119 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3 3120
a26bf12a 3121 ++vcpu->stat.irq_window_exits;
2714d1d3 3122
c1150d8c
DL		 3123 /*
3124 * If the user space waits to inject interrupts, exit as soon as
3125 * possible
3126 */
8061823a 3127 if (!irqchip_in_kernel(vcpu->kvm) &&
851ba692 3128 vcpu->run->request_interrupt_window &&
8061823a 3129 !kvm_cpu_has_interrupt(vcpu)) {
851ba692 3130 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
c1150d8c
DL		 3131 return 0;
3132 }
6aa8b732
AK		 3133 return 1;
3134}
3135
851ba692 3136static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732
AK		 3137{
3138 skip_emulated_instruction(vcpu);
d3bef15f 3139 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 3140}
3141
851ba692 3142static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 3143{
510043da 3144 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 3145 kvm_emulate_hypercall(vcpu);
3146 return 1;
c21415e8
IM		 3147}
3148
851ba692 3149static int handle_vmx_insn(struct kvm_vcpu *vcpu)
e3c7cb6a
AK		 3150{
3151 kvm_queue_exception(vcpu, UD_VECTOR);
3152 return 1;
3153}
3154
851ba692 3155static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 3156{
f9c617f6 3157 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 3158
3159 kvm_mmu_invlpg(vcpu, exit_qualification);
3160 skip_emulated_instruction(vcpu);
3161 return 1;
3162}
3163
851ba692 3164static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01
ED		 3165{
3166 skip_emulated_instruction(vcpu);
3167 /* TODO: Add support for VT-d/pass-through device */
3168 return 1;
3169}
3170
851ba692 3171static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 3172{
f9c617f6 3173 unsigned long exit_qualification;
f78e0e2e
SY		 3174 enum emulation_result er;
3175 unsigned long offset;
3176
f9c617f6 3177 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
f78e0e2e
SY		 3178 offset = exit_qualification & 0xffful;
3179
851ba692 3180 er = emulate_instruction(vcpu, 0, 0, 0);
f78e0e2e
SY		 3181
3182 if (er != EMULATE_DONE) {
3183 printk(KERN_ERR
3184 "Fail to handle apic access vmexit! Offset is 0x%lx\n",
3185 offset);
7f582ab6 3186 return -ENOEXEC;
f78e0e2e
SY		 3187 }
3188 return 1;
3189}
3190
851ba692 3191static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 3192{
60637aac 3193 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29
IE		 3194 unsigned long exit_qualification;
3195 u16 tss_selector;
64a7ec06
GN		 3196 int reason, type, idt_v;
3197
3198 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
3199 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 3200
3201 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3202
3203 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 3204 if (reason == TASK_SWITCH_GATE && idt_v) {
3205 switch (type) {
3206 case INTR_TYPE_NMI_INTR:
3207 vcpu->arch.nmi_injected = false;
3208 if (cpu_has_virtual_nmis())
3209 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3210 GUEST_INTR_STATE_NMI);
3211 break;
3212 case INTR_TYPE_EXT_INTR:
66fd3f7f 3213 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 3214 kvm_clear_interrupt_queue(vcpu);
3215 break;
3216 case INTR_TYPE_HARD_EXCEPTION:
3217 case INTR_TYPE_SOFT_EXCEPTION:
3218 kvm_clear_exception_queue(vcpu);
3219 break;
3220 default:
3221 break;
3222 }
60637aac 3223 }
37817f29
IE		 3224 tss_selector = exit_qualification;
3225
64a7ec06
GN		 3226 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
3227 type != INTR_TYPE_EXT_INTR &&
3228 type != INTR_TYPE_NMI_INTR))
3229 skip_emulated_instruction(vcpu);
3230
42dbaa5a
JK		 3231 if (!kvm_task_switch(vcpu, tss_selector, reason))
3232 return 0;
3233
3234 /* clear all local breakpoint enable flags */
3235 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
3236
3237 /*
3238 * TODO: What about debug traps on tss switch?
3239 * Are we supposed to inject them and update dr6?
3240 */
3241
3242 return 1;
37817f29
IE		 3243}
3244
851ba692 3245static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 3246{
f9c617f6 3247 unsigned long exit_qualification;
1439442c 3248 gpa_t gpa;
1439442c 3249 int gla_validity;
1439442c 3250
f9c617f6 3251 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c
SY		 3252
3253 if (exit_qualification & (1 << 6)) {
3254 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
7f582ab6 3255 return -EINVAL;
1439442c
SY		 3256 }
3257
3258 gla_validity = (exit_qualification >> 7) & 0x3;
3259 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
3260 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
3261 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3262 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 3263 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 3264 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
3265 (long unsigned int)exit_qualification);
851ba692
AK		 3266 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3267 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
596ae895 3268 return 0;
1439442c
SY		 3269 }
3270
3271 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 3272 trace_kvm_page_fault(gpa, exit_qualification);
49cd7d22 3273 return kvm_mmu_page_fault(vcpu, gpa & PAGE_MASK, 0);
1439442c
SY		 3274}
3275
68f89400
MT		 3276static u64 ept_rsvd_mask(u64 spte, int level)
3277{
3278 int i;
3279 u64 mask = 0;
3280
3281 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
3282 mask |= (1ULL << i);
3283
3284 if (level > 2)
3285 /* bits 7:3 reserved */
3286 mask |= 0xf8;
3287 else if (level == 2) {
3288 if (spte & (1ULL << 7))
3289 /* 2MB ref, bits 20:12 reserved */
3290 mask |= 0x1ff000;
3291 else
3292 /* bits 6:3 reserved */
3293 mask |= 0x78;
3294 }
3295
3296 return mask;
3297}
3298
3299static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
3300 int level)
3301{
3302 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
3303
3304 /* 010b (write-only) */
3305 WARN_ON((spte & 0x7) == 0x2);
3306
3307 /* 110b (write/execute) */
3308 WARN_ON((spte & 0x7) == 0x6);
3309
3310 /* 100b (execute-only) and value not supported by logical processor */
3311 if (!cpu_has_vmx_ept_execute_only())
3312 WARN_ON((spte & 0x7) == 0x4);
3313
3314 /* not 000b */
3315 if ((spte & 0x7)) {
3316 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
3317
3318 if (rsvd_bits != 0) {
3319 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
3320 __func__, rsvd_bits);
3321 WARN_ON(1);
3322 }
3323
3324 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
3325 u64 ept_mem_type = (spte & 0x38) >> 3;
3326
3327 if (ept_mem_type == 2 || ept_mem_type == 3 ||
3328 ept_mem_type == 7) {
3329 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
3330 __func__, ept_mem_type);
3331 WARN_ON(1);
3332 }
3333 }
3334 }
3335}
3336
851ba692 3337static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400
MT		 3338{
3339 u64 sptes[4];
3340 int nr_sptes, i;
3341 gpa_t gpa;
3342
3343 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3344
3345 printk(KERN_ERR "EPT: Misconfiguration.\n");
3346 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
3347
3348 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
3349
3350 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
3351 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
3352
851ba692
AK		 3353 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3354 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT		 3355
3356 return 0;
3357}
3358
851ba692 3359static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4
SY		 3360{
3361 u32 cpu_based_vm_exec_control;
3362
3363 /* clear pending NMI */
3364 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3365 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
3366 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3367 ++vcpu->stat.nmi_window_exits;
3368
3369 return 1;
3370}
3371
80ced186 3372static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 3373{
8b3079a5
AK		 3374 struct vcpu_vmx *vmx = to_vmx(vcpu);
3375 enum emulation_result err = EMULATE_DONE;
80ced186 3376 int ret = 1;
ea953ef0
MG		 3377
3378 while (!guest_state_valid(vcpu)) {
851ba692 3379 err = emulate_instruction(vcpu, 0, 0, 0);
ea953ef0 3380
80ced186
MG		 3381 if (err == EMULATE_DO_MMIO) {
3382 ret = 0;
3383 goto out;
3384 }
1d5a4d9b
GT		 3385
3386 if (err != EMULATE_DONE) {
3387 kvm_report_emulation_failure(vcpu, "emulation failure");
80ced186
MG		 3388 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3389 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
a9c7399d 3390 vcpu->run->internal.ndata = 0;
80ced186
MG		 3391 ret = 0;
3392 goto out;
ea953ef0
MG		 3393 }
3394
3395 if (signal_pending(current))
80ced186 3396 goto out;
ea953ef0
MG		 3397 if (need_resched())
3398 schedule();
3399 }
3400
80ced186
MG		 3401 vmx->emulation_required = 0;
3402out:
3403 return ret;
ea953ef0
MG		 3404}
3405
4b8d54f9
ZE		 3406/*
3407 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
3408 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
3409 */
9fb41ba8 3410static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9
ZE		 3411{
3412 skip_emulated_instruction(vcpu);
3413 kvm_vcpu_on_spin(vcpu);
3414
3415 return 1;
3416}
3417
6aa8b732
AK		 3418/*
3419 * The exit handlers return 1 if the exit was handled fully and guest execution
3420 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
3421 * to be done to userspace and return 0.
3422 */
851ba692 3423static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK		 3424 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
3425 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 3426 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 3427 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 3428 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 3429 [EXIT_REASON_CR_ACCESS] = handle_cr,
3430 [EXIT_REASON_DR_ACCESS] = handle_dr,
3431 [EXIT_REASON_CPUID] = handle_cpuid,
3432 [EXIT_REASON_MSR_READ] = handle_rdmsr,
3433 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
3434 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
3435 [EXIT_REASON_HLT] = handle_halt,
a7052897 3436 [EXIT_REASON_INVLPG] = handle_invlpg,
c21415e8 3437 [EXIT_REASON_VMCALL] = handle_vmcall,
e3c7cb6a
AK		 3438 [EXIT_REASON_VMCLEAR] = handle_vmx_insn,
3439 [EXIT_REASON_VMLAUNCH] = handle_vmx_insn,
3440 [EXIT_REASON_VMPTRLD] = handle_vmx_insn,
3441 [EXIT_REASON_VMPTRST] = handle_vmx_insn,
3442 [EXIT_REASON_VMREAD] = handle_vmx_insn,
3443 [EXIT_REASON_VMRESUME] = handle_vmx_insn,
3444 [EXIT_REASON_VMWRITE] = handle_vmx_insn,
3445 [EXIT_REASON_VMOFF] = handle_vmx_insn,
3446 [EXIT_REASON_VMON] = handle_vmx_insn,
f78e0e2e
SY		 3447 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
3448 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
e5edaa01 3449 [EXIT_REASON_WBINVD] = handle_wbinvd,
37817f29 3450 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 3451 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT		 3452 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
3453 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 3454 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
6aa8b732
AK		 3455};
3456
3457static const int kvm_vmx_max_exit_handlers =
50a3485c 3458 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732
AK		 3459
3460/*
3461 * The guest has exited. See if we can fix it or if we need userspace
3462 * assistance.
3463 */
851ba692 3464static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 3465{
29bd8a78 3466 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 3467 u32 exit_reason = vmx->exit_reason;
1155f76a 3468 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 3469
229456fc 3470 trace_kvm_exit(exit_reason, kvm_rip_read(vcpu));
2714d1d3 3471
80ced186
MG		 3472 /* If guest state is invalid, start emulating */
3473 if (vmx->emulation_required && emulate_invalid_guest_state)
3474 return handle_invalid_guest_state(vcpu);
1d5a4d9b 3475
1439442c
SY		 3476 /* Access CR3 don't cause VMExit in paging mode, so we need
3477 * to sync with guest real CR3. */
6de4f3ad 3478 if (enable_ept && is_paging(vcpu))
1439442c 3479 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
1439442c 3480
29bd8a78 3481 if (unlikely(vmx->fail)) {
851ba692
AK		 3482 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3483 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK		 3484 = vmcs_read32(VM_INSTRUCTION_ERROR);
3485 return 0;
3486 }
6aa8b732 3487
d77c26fc 3488 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 3489 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac
JK		 3490 exit_reason != EXIT_REASON_EPT_VIOLATION &&
3491 exit_reason != EXIT_REASON_TASK_SWITCH))
3492 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
3493 "(0x%x) and exit reason is 0x%x\n",
3494 __func__, vectoring_info, exit_reason);
3b86cd99
JK		 3495
3496 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) {
c4282df9 3497 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 3498 vmx->soft_vnmi_blocked = 0;
3b86cd99 3499 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 3500 vcpu->arch.nmi_pending) {
3b86cd99
JK		 3501 /*
3502 * This CPU don't support us in finding the end of an
3503 * NMI-blocked window if the guest runs with IRQs
3504 * disabled. So we pull the trigger after 1 s of
3505 * futile waiting, but inform the user about this.
3506 */
3507 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
3508 "state on VCPU %d after 1 s timeout\n",
3509 __func__, vcpu->vcpu_id);
3510 vmx->soft_vnmi_blocked = 0;
3b86cd99 3511 }
3b86cd99
JK		 3512 }
3513
6aa8b732
AK		 3514 if (exit_reason < kvm_vmx_max_exit_handlers
3515 && kvm_vmx_exit_handlers[exit_reason])
851ba692 3516 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 3517 else {
851ba692
AK		 3518 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3519 vcpu->run->hw.hardware_exit_reason = exit_reason;
6aa8b732
AK		 3520 }
3521 return 0;
3522}
3523
95ba8273 3524static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 3525{
95ba8273 3526 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 3527 vmcs_write32(TPR_THRESHOLD, 0);
3528 return;
3529 }
3530
95ba8273 3531 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 3532}
3533
cf393f75
AK		 3534static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
3535{
3536 u32 exit_intr_info;
7b4a25cb 3537 u32 idt_vectoring_info = vmx->idt_vectoring_info;
cf393f75
AK		 3538 bool unblock_nmi;
3539 u8 vector;
668f612f
AK		 3540 int type;
3541 bool idtv_info_valid;
cf393f75
AK		 3542
3543 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
20f65983 3544
a0861c02
AK		 3545 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
3546
3547 /* Handle machine checks before interrupts are enabled */
3548 if ((vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY)
3549 || (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI
3550 && is_machine_check(exit_intr_info)))
3551 kvm_machine_check();
3552
20f65983
GN		 3553 /* We need to handle NMIs before interrupts are enabled */
3554 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
229456fc 3555 (exit_intr_info & INTR_INFO_VALID_MASK))
20f65983 3556 asm("int $2");
20f65983
GN		 3557
3558 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
3559
cf393f75
AK		 3560 if (cpu_has_virtual_nmis()) {
3561 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
3562 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
3563 /*
7b4a25cb 3564 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 3565 * Re-set bit "block by NMI" before VM entry if vmexit caused by
3566 * a guest IRET fault.
7b4a25cb
GN		 3567 * SDM 3: 23.2.2 (September 2008)
3568 * Bit 12 is undefined in any of the following cases:
3569 * If the VM exit sets the valid bit in the IDT-vectoring
3570 * information field.
3571 * If the VM exit is due to a double fault.
cf393f75 3572 */
7b4a25cb
GN		 3573 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
3574 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 3575 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3576 GUEST_INTR_STATE_NMI);
3b86cd99
JK		 3577 } else if (unlikely(vmx->soft_vnmi_blocked))
3578 vmx->vnmi_blocked_time +=
3579 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
668f612f 3580
37b96e98
GN		 3581 vmx->vcpu.arch.nmi_injected = false;
3582 kvm_clear_exception_queue(&vmx->vcpu);
3583 kvm_clear_interrupt_queue(&vmx->vcpu);
3584
3585 if (!idtv_info_valid)
3586 return;
3587
668f612f
AK		 3588 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
3589 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 3590
64a7ec06 3591 switch (type) {
37b96e98
GN		 3592 case INTR_TYPE_NMI_INTR:
3593 vmx->vcpu.arch.nmi_injected = true;
668f612f 3594 /*
7b4a25cb 3595 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 3596 * Clear bit "block by NMI" before VM entry if a NMI
3597 * delivery faulted.
668f612f 3598 */
37b96e98
GN		 3599 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3600 GUEST_INTR_STATE_NMI);
3601 break;
37b96e98 3602 case INTR_TYPE_SOFT_EXCEPTION:
66fd3f7f
GN		 3603 vmx->vcpu.arch.event_exit_inst_len =
3604 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3605 /* fall through */
3606 case INTR_TYPE_HARD_EXCEPTION:
35920a35 3607 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
37b96e98
GN		 3608 u32 err = vmcs_read32(IDT_VECTORING_ERROR_CODE);
3609 kvm_queue_exception_e(&vmx->vcpu, vector, err);
35920a35
AK		 3610 } else
3611 kvm_queue_exception(&vmx->vcpu, vector);
37b96e98 3612 break;
66fd3f7f
GN		 3613 case INTR_TYPE_SOFT_INTR:
3614 vmx->vcpu.arch.event_exit_inst_len =
3615 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3616 /* fall through */
37b96e98 3617 case INTR_TYPE_EXT_INTR:
66fd3f7f
GN		 3618 kvm_queue_interrupt(&vmx->vcpu, vector,
3619 type == INTR_TYPE_SOFT_INTR);
37b96e98
GN		 3620 break;
3621 default:
3622 break;
f7d9238f 3623 }
cf393f75
AK		 3624}
3625
9c8cba37
AK		 3626/*
3627 * Failure to inject an interrupt should give us the information
3628 * in IDT_VECTORING_INFO_FIELD. However, if the failure occurs
3629 * when fetching the interrupt redirection bitmap in the real-mode
3630 * tss, this doesn't happen. So we do it ourselves.
3631 */
3632static void fixup_rmode_irq(struct vcpu_vmx *vmx)
3633{
3634 vmx->rmode.irq.pending = 0;
5fdbf976 3635 if (kvm_rip_read(&vmx->vcpu) + 1 != vmx->rmode.irq.rip)
9c8cba37 3636 return;
5fdbf976 3637 kvm_rip_write(&vmx->vcpu, vmx->rmode.irq.rip);
9c8cba37
AK		 3638 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
3639 vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK;
3640 vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR;
3641 return;
3642 }
3643 vmx->idt_vectoring_info =
3644 VECTORING_INFO_VALID_MASK
3645 | INTR_TYPE_EXT_INTR
3646 | vmx->rmode.irq.vector;
3647}
3648
c801949d
AK		 3649#ifdef CONFIG_X86_64
3650#define R "r"
3651#define Q "q"
3652#else
3653#define R "e"
3654#define Q "l"
3655#endif
3656
851ba692 3657static void vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 3658{
a2fa3e9f 3659 struct vcpu_vmx *vmx = to_vmx(vcpu);
e6adf283 3660
3b86cd99
JK		 3661 /* Record the guest's net vcpu time for enforced NMI injections. */
3662 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
3663 vmx->entry_time = ktime_get();
3664
80ced186
MG		 3665 /* Don't enter VMX if guest state is invalid, let the exit handler
3666 start emulation until we arrive back to a valid state */
3667 if (vmx->emulation_required && emulate_invalid_guest_state)
a89a8fb9 3668 return;
a89a8fb9 3669
5fdbf976
MT		 3670 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
3671 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
3672 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
3673 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
3674
787ff736
GN		 3675 /* When single-stepping over STI and MOV SS, we must clear the
3676 * corresponding interruptibility bits in the guest state. Otherwise
3677 * vmentry fails as it then expects bit 14 (BS) in pending debug
3678 * exceptions being set, but that's not correct for the guest debugging
3679 * case. */
3680 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
3681 vmx_set_interrupt_shadow(vcpu, 0);
3682
e6adf283
AK		 3683 /*
3684 * Loading guest fpu may have cleared host cr0.ts
3685 */
3686 vmcs_writel(HOST_CR0, read_cr0());
3687
e8a48342
AK		 3688 if (vcpu->arch.switch_db_regs)
3689 set_debugreg(vcpu->arch.dr6, 6);
42dbaa5a 3690
d77c26fc 3691 asm(
6aa8b732 3692 /* Store host registers */
c801949d
AK		 3693 "push %%"R"dx; push %%"R"bp;"
3694 "push %%"R"cx \n\t"
313dbd49
AK		 3695 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
3696 "je 1f \n\t"
3697 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
4ecac3fd 3698 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 3699 "1: \n\t"
d3edefc0
AK		 3700 /* Reload cr2 if changed */
3701 "mov %c[cr2](%0), %%"R"ax \n\t"
3702 "mov %%cr2, %%"R"dx \n\t"
3703 "cmp %%"R"ax, %%"R"dx \n\t"
3704 "je 2f \n\t"
3705 "mov %%"R"ax, %%cr2 \n\t"
3706 "2: \n\t"
6aa8b732 3707 /* Check if vmlaunch of vmresume is needed */
e08aa78a 3708 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 3709 /* Load guest registers. Don't clobber flags. */
c801949d
AK		 3710 "mov %c[rax](%0), %%"R"ax \n\t"
3711 "mov %c[rbx](%0), %%"R"bx \n\t"
3712 "mov %c[rdx](%0), %%"R"dx \n\t"
3713 "mov %c[rsi](%0), %%"R"si \n\t"
3714 "mov %c[rdi](%0), %%"R"di \n\t"
3715 "mov %c[rbp](%0), %%"R"bp \n\t"
05b3e0c2 3716#ifdef CONFIG_X86_64
e08aa78a
AK		 3717 "mov %c[r8](%0), %%r8 \n\t"
3718 "mov %c[r9](%0), %%r9 \n\t"
3719 "mov %c[r10](%0), %%r10 \n\t"
3720 "mov %c[r11](%0), %%r11 \n\t"
3721 "mov %c[r12](%0), %%r12 \n\t"
3722 "mov %c[r13](%0), %%r13 \n\t"
3723 "mov %c[r14](%0), %%r14 \n\t"
3724 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 3725#endif
c801949d
AK		 3726 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
3727
6aa8b732 3728 /* Enter guest mode */
cd2276a7 3729 "jne .Llaunched \n\t"
4ecac3fd 3730 __ex(ASM_VMX_VMLAUNCH) "\n\t"
cd2276a7 3731 "jmp .Lkvm_vmx_return \n\t"
4ecac3fd 3732 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
cd2276a7 3733 ".Lkvm_vmx_return: "
6aa8b732 3734 /* Save guest registers, load host registers, keep flags */
c801949d
AK		 3735 "xchg %0, (%%"R"sp) \n\t"
3736 "mov %%"R"ax, %c[rax](%0) \n\t"
3737 "mov %%"R"bx, %c[rbx](%0) \n\t"
3738 "push"Q" (%%"R"sp); pop"Q" %c[rcx](%0) \n\t"
3739 "mov %%"R"dx, %c[rdx](%0) \n\t"
3740 "mov %%"R"si, %c[rsi](%0) \n\t"
3741 "mov %%"R"di, %c[rdi](%0) \n\t"
3742 "mov %%"R"bp, %c[rbp](%0) \n\t"
05b3e0c2 3743#ifdef CONFIG_X86_64
e08aa78a
AK		 3744 "mov %%r8, %c[r8](%0) \n\t"
3745 "mov %%r9, %c[r9](%0) \n\t"
3746 "mov %%r10, %c[r10](%0) \n\t"
3747 "mov %%r11, %c[r11](%0) \n\t"
3748 "mov %%r12, %c[r12](%0) \n\t"
3749 "mov %%r13, %c[r13](%0) \n\t"
3750 "mov %%r14, %c[r14](%0) \n\t"
3751 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 3752#endif
c801949d
AK		 3753 "mov %%cr2, %%"R"ax \n\t"
3754 "mov %%"R"ax, %c[cr2](%0) \n\t"
3755
3756 "pop %%"R"bp; pop %%"R"bp; pop %%"R"dx \n\t"
e08aa78a
AK		 3757 "setbe %c[fail](%0) \n\t"
3758 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
3759 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
3760 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 3761 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 3762 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
3763 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
3764 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
3765 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
3766 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
3767 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
3768 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 3769#ifdef CONFIG_X86_64
ad312c7c
ZX		 3770 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
3771 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
3772 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
3773 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
3774 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
3775 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
3776 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
3777 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 3778#endif
ad312c7c 3779 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2))
c2036300 3780 : "cc", "memory"
c801949d 3781 , R"bx", R"di", R"si"
c2036300 3782#ifdef CONFIG_X86_64
c2036300
LV		 3783 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3784#endif
3785 );
6aa8b732 3786
6de4f3ad
AK		 3787 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
3788 | (1 << VCPU_EXREG_PDPTR));
5fdbf976
MT		 3789 vcpu->arch.regs_dirty = 0;
3790
e8a48342
AK		 3791 if (vcpu->arch.switch_db_regs)
3792 get_debugreg(vcpu->arch.dr6, 6);
42dbaa5a 3793
1155f76a 3794 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
9c8cba37
AK		 3795 if (vmx->rmode.irq.pending)
3796 fixup_rmode_irq(vmx);
1155f76a 3797
d77c26fc 3798 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
15ad7146 3799 vmx->launched = 1;
1b6269db 3800
cf393f75 3801 vmx_complete_interrupts(vmx);
6aa8b732
AK		 3802}
3803
c801949d
AK		 3804#undef R
3805#undef Q
3806
6aa8b732
AK		 3807static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
3808{
a2fa3e9f
GH		 3809 struct vcpu_vmx *vmx = to_vmx(vcpu);
3810
3811 if (vmx->vmcs) {
543e4243 3812 vcpu_clear(vmx);
a2fa3e9f
GH		 3813 free_vmcs(vmx->vmcs);
3814 vmx->vmcs = NULL;
6aa8b732
AK		 3815 }
3816}
3817
3818static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
3819{
fb3f0f51
RR		 3820 struct vcpu_vmx *vmx = to_vmx(vcpu);
3821
2384d2b3
SY		 3822 spin_lock(&vmx_vpid_lock);
3823 if (vmx->vpid != 0)
3824 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3825 spin_unlock(&vmx_vpid_lock);
6aa8b732 3826 vmx_free_vmcs(vcpu);
fb3f0f51
RR		 3827 kfree(vmx->guest_msrs);
3828 kvm_vcpu_uninit(vcpu);
a4770347 3829 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 3830}
3831
fb3f0f51 3832static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 3833{
fb3f0f51 3834 int err;
c16f862d 3835 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 3836 int cpu;
6aa8b732 3837
a2fa3e9f 3838 if (!vmx)
fb3f0f51
RR		 3839 return ERR_PTR(-ENOMEM);
3840
2384d2b3
SY		 3841 allocate_vpid(vmx);
3842
fb3f0f51
RR		 3843 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
3844 if (err)
3845 goto free_vcpu;
965b58a5 3846
a2fa3e9f 3847 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
fb3f0f51
RR		 3848 if (!vmx->guest_msrs) {
3849 err = -ENOMEM;
3850 goto uninit_vcpu;
3851 }
965b58a5 3852
a2fa3e9f
GH		 3853 vmx->vmcs = alloc_vmcs();
3854 if (!vmx->vmcs)
fb3f0f51 3855 goto free_msrs;
a2fa3e9f
GH		 3856
3857 vmcs_clear(vmx->vmcs);
3858
15ad7146
AK		 3859 cpu = get_cpu();
3860 vmx_vcpu_load(&vmx->vcpu, cpu);
8b9cf98c 3861 err = vmx_vcpu_setup(vmx);
fb3f0f51 3862 vmx_vcpu_put(&vmx->vcpu);
15ad7146 3863 put_cpu();
fb3f0f51
RR		 3864 if (err)
3865 goto free_vmcs;
5e4a0b3c
MT		 3866 if (vm_need_virtualize_apic_accesses(kvm))
3867 if (alloc_apic_access_page(kvm) != 0)
3868 goto free_vmcs;
fb3f0f51 3869
b927a3ce
SY		 3870 if (enable_ept) {
3871 if (!kvm->arch.ept_identity_map_addr)
3872 kvm->arch.ept_identity_map_addr =
3873 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
b7ebfb05
SY		 3874 if (alloc_identity_pagetable(kvm) != 0)
3875 goto free_vmcs;
b927a3ce 3876 }
b7ebfb05 3877
fb3f0f51
RR		 3878 return &vmx->vcpu;
3879
3880free_vmcs:
3881 free_vmcs(vmx->vmcs);
3882free_msrs:
fb3f0f51
RR		 3883 kfree(vmx->guest_msrs);
3884uninit_vcpu:
3885 kvm_vcpu_uninit(&vmx->vcpu);
3886free_vcpu:
a4770347 3887 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 3888 return ERR_PTR(err);
6aa8b732
AK		 3889}
3890
002c7f7c
YS		 3891static void __init vmx_check_processor_compat(void *rtn)
3892{
3893 struct vmcs_config vmcs_conf;
3894
3895 *(int *)rtn = 0;
3896 if (setup_vmcs_config(&vmcs_conf) < 0)
3897 *(int *)rtn = -EIO;
3898 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
3899 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
3900 smp_processor_id());
3901 *(int *)rtn = -EIO;
3902 }
3903}
3904
67253af5
SY		 3905static int get_ept_level(void)
3906{
3907 return VMX_EPT_DEFAULT_GAW + 1;
3908}
3909
4b12f0de 3910static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 3911{
4b12f0de
SY		 3912 u64 ret;
3913
522c68c4
SY		 3914 /* For VT-d and EPT combination
3915 * 1. MMIO: always map as UC
3916 * 2. EPT with VT-d:
3917 * a. VT-d without snooping control feature: can't guarantee the
3918 * result, try to trust guest.
3919 * b. VT-d with snooping control feature: snooping control feature of
3920 * VT-d engine can guarantee the cache correctness. Just set it
3921 * to WB to keep consistent with host. So the same as item 3.
3922 * 3. EPT without VT-d: always map as WB and set IGMT=1 to keep
3923 * consistent with host MTRR
3924 */
4b12f0de
SY		 3925 if (is_mmio)
3926 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
522c68c4
SY		 3927 else if (vcpu->kvm->arch.iommu_domain &&
3928 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
3929 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
3930 VMX_EPT_MT_EPTE_SHIFT;
4b12f0de 3931 else
522c68c4
SY		 3932 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
3933 | VMX_EPT_IGMT_BIT;
4b12f0de
SY		 3934
3935 return ret;
64d4d521
SY		 3936}
3937
229456fc
MT		 3938static const struct trace_print_flags vmx_exit_reasons_str[] = {
3939 { EXIT_REASON_EXCEPTION_NMI, "exception" },
3940 { EXIT_REASON_EXTERNAL_INTERRUPT, "ext_irq" },
3941 { EXIT_REASON_TRIPLE_FAULT, "triple_fault" },
3942 { EXIT_REASON_NMI_WINDOW, "nmi_window" },
3943 { EXIT_REASON_IO_INSTRUCTION, "io_instruction" },
3944 { EXIT_REASON_CR_ACCESS, "cr_access" },
3945 { EXIT_REASON_DR_ACCESS, "dr_access" },
3946 { EXIT_REASON_CPUID, "cpuid" },
3947 { EXIT_REASON_MSR_READ, "rdmsr" },
3948 { EXIT_REASON_MSR_WRITE, "wrmsr" },
3949 { EXIT_REASON_PENDING_INTERRUPT, "interrupt_window" },
3950 { EXIT_REASON_HLT, "halt" },
3951 { EXIT_REASON_INVLPG, "invlpg" },
3952 { EXIT_REASON_VMCALL, "hypercall" },
3953 { EXIT_REASON_TPR_BELOW_THRESHOLD, "tpr_below_thres" },
3954 { EXIT_REASON_APIC_ACCESS, "apic_access" },
3955 { EXIT_REASON_WBINVD, "wbinvd" },
3956 { EXIT_REASON_TASK_SWITCH, "task_switch" },
3957 { EXIT_REASON_EPT_VIOLATION, "ept_violation" },
3958 { -1, NULL }
3959};
3960
344f414f
JR		 3961static bool vmx_gb_page_enable(void)
3962{
3963 return false;
3964}
3965
cbdd1bea 3966static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 3967 .cpu_has_kvm_support = cpu_has_kvm_support,
3968 .disabled_by_bios = vmx_disabled_by_bios,
3969 .hardware_setup = hardware_setup,
3970 .hardware_unsetup = hardware_unsetup,
002c7f7c 3971 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 3972 .hardware_enable = hardware_enable,
3973 .hardware_disable = hardware_disable,
04547156 3974 .cpu_has_accelerated_tpr = report_flexpriority,
6aa8b732
AK		 3975
3976 .vcpu_create = vmx_create_vcpu,
3977 .vcpu_free = vmx_free_vcpu,
04d2cc77 3978 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 3979
04d2cc77 3980 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 3981 .vcpu_load = vmx_vcpu_load,
3982 .vcpu_put = vmx_vcpu_put,
3983
3984 .set_guest_debug = set_guest_debug,
3985 .get_msr = vmx_get_msr,
3986 .set_msr = vmx_set_msr,
3987 .get_segment_base = vmx_get_segment_base,
3988 .get_segment = vmx_get_segment,
3989 .set_segment = vmx_set_segment,
2e4d2653 3990 .get_cpl = vmx_get_cpl,
6aa8b732 3991 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
25c4c276 3992 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 3993 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 3994 .set_cr3 = vmx_set_cr3,
3995 .set_cr4 = vmx_set_cr4,
6aa8b732 3996 .set_efer = vmx_set_efer,
6aa8b732
AK		 3997 .get_idt = vmx_get_idt,
3998 .set_idt = vmx_set_idt,
3999 .get_gdt = vmx_get_gdt,
4000 .set_gdt = vmx_set_gdt,
5fdbf976 4001 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 4002 .get_rflags = vmx_get_rflags,
4003 .set_rflags = vmx_set_rflags,
4004
4005 .tlb_flush = vmx_flush_tlb,
6aa8b732 4006
6aa8b732 4007 .run = vmx_vcpu_run,
6062d012 4008 .handle_exit = vmx_handle_exit,
6aa8b732 4009 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 4010 .set_interrupt_shadow = vmx_set_interrupt_shadow,
4011 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 4012 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 4013 .set_irq = vmx_inject_irq,
95ba8273 4014 .set_nmi = vmx_inject_nmi,
298101da 4015 .queue_exception = vmx_queue_exception,
78646121 4016 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 4017 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 4018 .get_nmi_mask = vmx_get_nmi_mask,
4019 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 4020 .enable_nmi_window = enable_nmi_window,
4021 .enable_irq_window = enable_irq_window,
4022 .update_cr8_intercept = update_cr8_intercept,
95ba8273 4023
cbc94022 4024 .set_tss_addr = vmx_set_tss_addr,
67253af5 4025 .get_tdp_level = get_ept_level,
4b12f0de 4026 .get_mt_mask = vmx_get_mt_mask,
229456fc
MT		 4027
4028 .exit_reasons_str = vmx_exit_reasons_str,
344f414f 4029 .gb_page_enable = vmx_gb_page_enable,
6aa8b732
AK		 4030};
4031
4032static int __init vmx_init(void)
4033{
26bb0981
AK		 4034 int r, i;
4035
4036 rdmsrl_safe(MSR_EFER, &host_efer);
4037
4038 for (i = 0; i < NR_VMX_MSR; ++i)
4039 kvm_define_shared_msr(i, vmx_msr_index[i]);
fdef3ad1 4040
3e7c73e9 4041 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 4042 if (!vmx_io_bitmap_a)
4043 return -ENOMEM;
4044
3e7c73e9 4045 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 4046 if (!vmx_io_bitmap_b) {
4047 r = -ENOMEM;
4048 goto out;
4049 }
4050
5897297b
AK		 4051 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
4052 if (!vmx_msr_bitmap_legacy) {
25c5f225
SY		 4053 r = -ENOMEM;
4054 goto out1;
4055 }
4056
5897297b
AK		 4057 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
4058 if (!vmx_msr_bitmap_longmode) {
4059 r = -ENOMEM;
4060 goto out2;
4061 }
4062
fdef3ad1
HQ		 4063 /*
4064 * Allow direct access to the PC debug port (it is often used for I/O
4065 * delays, but the vmexits simply slow things down).
4066 */
3e7c73e9
AK		 4067 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
4068 clear_bit(0x80, vmx_io_bitmap_a);
fdef3ad1 4069
3e7c73e9 4070 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
fdef3ad1 4071
5897297b
AK		 4072 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
4073 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
25c5f225 4074
2384d2b3
SY		 4075 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
4076
cb498ea2 4077 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 4078 if (r)
5897297b 4079 goto out3;
25c5f225 4080
5897297b
AK		 4081 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
4082 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
4083 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
4084 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
4085 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
4086 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
fdef3ad1 4087
089d034e 4088 if (enable_ept) {
1439442c 4089 bypass_guest_pf = 0;
5fdbcb9d 4090 kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK |
2aaf69dc 4091 VMX_EPT_WRITABLE_MASK);
534e38b4 4092 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
4b12f0de 4093 VMX_EPT_EXECUTABLE_MASK);
5fdbcb9d
SY		 4094 kvm_enable_tdp();
4095 } else
4096 kvm_disable_tdp();
1439442c 4097
c7addb90
AK		 4098 if (bypass_guest_pf)
4099 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
4100
fdef3ad1
HQ		 4101 return 0;
4102
5897297b
AK		 4103out3:
4104 free_page((unsigned long)vmx_msr_bitmap_longmode);
25c5f225 4105out2:
5897297b 4106 free_page((unsigned long)vmx_msr_bitmap_legacy);
fdef3ad1 4107out1:
3e7c73e9 4108 free_page((unsigned long)vmx_io_bitmap_b);
fdef3ad1 4109out:
3e7c73e9 4110 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 4111 return r;
6aa8b732
AK		 4112}
4113
4114static void __exit vmx_exit(void)
4115{
5897297b
AK		 4116 free_page((unsigned long)vmx_msr_bitmap_legacy);
4117 free_page((unsigned long)vmx_msr_bitmap_longmode);
3e7c73e9
AK		 4118 free_page((unsigned long)vmx_io_bitmap_b);
4119 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 4120
cb498ea2 4121 kvm_exit();
6aa8b732
AK		 4122}
4123
4124module_init(vmx_init)
4125module_exit(vmx_exit)
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