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KVM: x86: Do not return soft events in vcpu_events
[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
043405e1
CO		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 13 * Amit Shah <amit.shah@qumranet.com>
14 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 */
20
edf88417 21#include <linux/kvm_host.h>
313a3dc7 22#include "irq.h"
1d737c8a 23#include "mmu.h"
7837699f 24#include "i8254.h"
37817f29 25#include "tss.h"
5fdbf976 26#include "kvm_cache_regs.h"
26eef70c 27#include "x86.h"
313a3dc7 28
18068523 29#include <linux/clocksource.h>
4d5c5d0f 30#include <linux/interrupt.h>
313a3dc7
CO		 31#include <linux/kvm.h>
32#include <linux/fs.h>
33#include <linux/vmalloc.h>
5fb76f9b 34#include <linux/module.h>
0de10343 35#include <linux/mman.h>
2bacc55c 36#include <linux/highmem.h>
19de40a8 37#include <linux/iommu.h>
62c476c7 38#include <linux/intel-iommu.h>
c8076604 39#include <linux/cpufreq.h>
18863bdd 40#include <linux/user-return-notifier.h>
a983fb23 41#include <linux/srcu.h>
5a0e3ad6 42#include <linux/slab.h>
aec51dc4
AK		 43#include <trace/events/kvm.h>
44#undef TRACE_INCLUDE_FILE
229456fc
MT		 45#define CREATE_TRACE_POINTS
46#include "trace.h"
043405e1 47
24f1e32c 48#include <asm/debugreg.h>
043405e1 49#include <asm/uaccess.h>
d825ed0a 50#include <asm/msr.h>
a5f61300 51#include <asm/desc.h>
0bed3b56 52#include <asm/mtrr.h>
890ca9ae 53#include <asm/mce.h>
043405e1 54
313a3dc7 55#define MAX_IO_MSRS 256
a03490ed
CO		 56#define CR0_RESERVED_BITS \
57 (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \
58 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \
59 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG))
60#define CR4_RESERVED_BITS \
61 (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\
62 | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \
63 | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR \
64 | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE))
65
66#define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
890ca9ae
HY		 67
68#define KVM_MAX_MCE_BANKS 32
69#define KVM_MCE_CAP_SUPPORTED MCG_CTL_P
70
50a37eb4
JR		 71/* EFER defaults:
72 * - enable syscall per default because its emulated by KVM
73 * - enable LME and LMA per default on 64 bit KVM
74 */
75#ifdef CONFIG_X86_64
76static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffafeULL;
77#else
78static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffffeULL;
79#endif
313a3dc7 80
ba1389b7
AK		 81#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
82#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 83
cb142eb7 84static void update_cr8_intercept(struct kvm_vcpu *vcpu);
674eea0f
AK		 85static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
86 struct kvm_cpuid_entry2 __user *entries);
87
97896d04 88struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 89EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 90
ed85c068
AP		 91int ignore_msrs = 0;
92module_param_named(ignore_msrs, ignore_msrs, bool, S_IRUGO | S_IWUSR);
93
18863bdd
AK		 94#define KVM_NR_SHARED_MSRS 16
95
96struct kvm_shared_msrs_global {
97 int nr;
2bf78fa7 98 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 99};
100
101struct kvm_shared_msrs {
102 struct user_return_notifier urn;
103 bool registered;
2bf78fa7
SY		 104 struct kvm_shared_msr_values {
105 u64 host;
106 u64 curr;
107 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 108};
109
110static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
111static DEFINE_PER_CPU(struct kvm_shared_msrs, shared_msrs);
112
417bc304 113struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 114 { "pf_fixed", VCPU_STAT(pf_fixed) },
115 { "pf_guest", VCPU_STAT(pf_guest) },
116 { "tlb_flush", VCPU_STAT(tlb_flush) },
117 { "invlpg", VCPU_STAT(invlpg) },
118 { "exits", VCPU_STAT(exits) },
119 { "io_exits", VCPU_STAT(io_exits) },
120 { "mmio_exits", VCPU_STAT(mmio_exits) },
121 { "signal_exits", VCPU_STAT(signal_exits) },
122 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 123 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 124 { "halt_exits", VCPU_STAT(halt_exits) },
125 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 126 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 127 { "request_irq", VCPU_STAT(request_irq_exits) },
128 { "irq_exits", VCPU_STAT(irq_exits) },
129 { "host_state_reload", VCPU_STAT(host_state_reload) },
130 { "efer_reload", VCPU_STAT(efer_reload) },
131 { "fpu_reload", VCPU_STAT(fpu_reload) },
132 { "insn_emulation", VCPU_STAT(insn_emulation) },
133 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 134 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 135 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 136 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
137 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
138 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
139 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
140 { "mmu_flooded", VM_STAT(mmu_flooded) },
141 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 142 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 143 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 144 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 145 { "largepages", VM_STAT(lpages) },
417bc304
HB		 146 { NULL }
147};
148
18863bdd
AK		 149static void kvm_on_user_return(struct user_return_notifier *urn)
150{
151 unsigned slot;
18863bdd
AK		 152 struct kvm_shared_msrs *locals
153 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 154 struct kvm_shared_msr_values *values;
18863bdd
AK		 155
156 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 157 values = &locals->values[slot];
158 if (values->host != values->curr) {
159 wrmsrl(shared_msrs_global.msrs[slot], values->host);
160 values->curr = values->host;
18863bdd
AK		 161 }
162 }
163 locals->registered = false;
164 user_return_notifier_unregister(urn);
165}
166
2bf78fa7 167static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 168{
2bf78fa7 169 struct kvm_shared_msrs *smsr;
18863bdd
AK		 170 u64 value;
171
2bf78fa7
SY		 172 smsr = &__get_cpu_var(shared_msrs);
173 /* only read, and nobody should modify it at this time,
174 * so don't need lock */
175 if (slot >= shared_msrs_global.nr) {
176 printk(KERN_ERR "kvm: invalid MSR slot!");
177 return;
178 }
179 rdmsrl_safe(msr, &value);
180 smsr->values[slot].host = value;
181 smsr->values[slot].curr = value;
182}
183
184void kvm_define_shared_msr(unsigned slot, u32 msr)
185{
18863bdd
AK		 186 if (slot >= shared_msrs_global.nr)
187 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 188 shared_msrs_global.msrs[slot] = msr;
189 /* we need ensured the shared_msr_global have been updated */
190 smp_wmb();
18863bdd
AK		 191}
192EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
193
194static void kvm_shared_msr_cpu_online(void)
195{
196 unsigned i;
18863bdd
AK		 197
198 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 199 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 200}
201
d5696725 202void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd
AK		 203{
204 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
205
2bf78fa7 206 if (((value ^ smsr->values[slot].curr) & mask) == 0)
18863bdd 207 return;
2bf78fa7
SY		 208 smsr->values[slot].curr = value;
209 wrmsrl(shared_msrs_global.msrs[slot], value);
18863bdd
AK		 210 if (!smsr->registered) {
211 smsr->urn.on_user_return = kvm_on_user_return;
212 user_return_notifier_register(&smsr->urn);
213 smsr->registered = true;
214 }
215}
216EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
217
3548bab5
AK		 218static void drop_user_return_notifiers(void *ignore)
219{
220 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
221
222 if (smsr->registered)
223 kvm_on_user_return(&smsr->urn);
224}
225
5fb76f9b
CO		 226unsigned long segment_base(u16 selector)
227{
89a27f4d 228 struct desc_ptr gdt;
a5f61300 229 struct desc_struct *d;
5fb76f9b
CO		 230 unsigned long table_base;
231 unsigned long v;
232
233 if (selector == 0)
234 return 0;
235
b792c344 236 kvm_get_gdt(&gdt);
89a27f4d 237 table_base = gdt.address;
5fb76f9b
CO		 238
239 if (selector & 4) { /* from ldt */
b792c344 240 u16 ldt_selector = kvm_read_ldt();
5fb76f9b 241
5fb76f9b
CO		 242 table_base = segment_base(ldt_selector);
243 }
a5f61300 244 d = (struct desc_struct *)(table_base + (selector & ~7));
46a359e7 245 v = get_desc_base(d);
5fb76f9b 246#ifdef CONFIG_X86_64
a5f61300
AK		 247 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
248 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
5fb76f9b
CO		 249#endif
250 return v;
251}
252EXPORT_SYMBOL_GPL(segment_base);
253
6866b83e
CO		 254u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
255{
256 if (irqchip_in_kernel(vcpu->kvm))
ad312c7c 257 return vcpu->arch.apic_base;
6866b83e 258 else
ad312c7c 259 return vcpu->arch.apic_base;
6866b83e
CO		 260}
261EXPORT_SYMBOL_GPL(kvm_get_apic_base);
262
263void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
264{
265 /* TODO: reserve bits check */
266 if (irqchip_in_kernel(vcpu->kvm))
267 kvm_lapic_set_base(vcpu, data);
268 else
ad312c7c 269 vcpu->arch.apic_base = data;
6866b83e
CO		 270}
271EXPORT_SYMBOL_GPL(kvm_set_apic_base);
272
3fd28fce
ED		 273#define EXCPT_BENIGN 0
274#define EXCPT_CONTRIBUTORY 1
275#define EXCPT_PF 2
276
277static int exception_class(int vector)
278{
279 switch (vector) {
280 case PF_VECTOR:
281 return EXCPT_PF;
282 case DE_VECTOR:
283 case TS_VECTOR:
284 case NP_VECTOR:
285 case SS_VECTOR:
286 case GP_VECTOR:
287 return EXCPT_CONTRIBUTORY;
288 default:
289 break;
290 }
291 return EXCPT_BENIGN;
292}
293
294static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
295 unsigned nr, bool has_error, u32 error_code)
296{
297 u32 prev_nr;
298 int class1, class2;
299
300 if (!vcpu->arch.exception.pending) {
301 queue:
302 vcpu->arch.exception.pending = true;
303 vcpu->arch.exception.has_error_code = has_error;
304 vcpu->arch.exception.nr = nr;
305 vcpu->arch.exception.error_code = error_code;
306 return;
307 }
308
309 /* to check exception */
310 prev_nr = vcpu->arch.exception.nr;
311 if (prev_nr == DF_VECTOR) {
312 /* triple fault -> shutdown */
313 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
314 return;
315 }
316 class1 = exception_class(prev_nr);
317 class2 = exception_class(nr);
318 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
319 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
320 /* generate double fault per SDM Table 5-5 */
321 vcpu->arch.exception.pending = true;
322 vcpu->arch.exception.has_error_code = true;
323 vcpu->arch.exception.nr = DF_VECTOR;
324 vcpu->arch.exception.error_code = 0;
325 } else
326 /* replace previous exception with a new one in a hope
327 that instruction re-execution will regenerate lost
328 exception */
329 goto queue;
330}
331
298101da
AK		 332void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
333{
3fd28fce 334 kvm_multiple_exception(vcpu, nr, false, 0);
298101da
AK		 335}
336EXPORT_SYMBOL_GPL(kvm_queue_exception);
337
c3c91fee
AK		 338void kvm_inject_page_fault(struct kvm_vcpu *vcpu, unsigned long addr,
339 u32 error_code)
340{
341 ++vcpu->stat.pf_guest;
ad312c7c 342 vcpu->arch.cr2 = addr;
c3c91fee
AK		 343 kvm_queue_exception_e(vcpu, PF_VECTOR, error_code);
344}
345
3419ffc8
SY		 346void kvm_inject_nmi(struct kvm_vcpu *vcpu)
347{
348 vcpu->arch.nmi_pending = 1;
349}
350EXPORT_SYMBOL_GPL(kvm_inject_nmi);
351
298101da
AK		 352void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
353{
3fd28fce 354 kvm_multiple_exception(vcpu, nr, true, error_code);
298101da
AK		 355}
356EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
357
0a79b009
AK		 358/*
359 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
360 * a #GP and return false.
361 */
362bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 363{
0a79b009
AK		 364 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
365 return true;
366 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
367 return false;
298101da 368}
0a79b009 369EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 370
a03490ed
CO		 371/*
372 * Load the pae pdptrs. Return true is they are all valid.
373 */
374int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3)
375{
376 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
377 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
378 int i;
379 int ret;
ad312c7c 380 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
a03490ed 381
a03490ed
CO		 382 ret = kvm_read_guest_page(vcpu->kvm, pdpt_gfn, pdpte,
383 offset * sizeof(u64), sizeof(pdpte));
384 if (ret < 0) {
385 ret = 0;
386 goto out;
387 }
388 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 389 if (is_present_gpte(pdpte[i]) &&
20c466b5 390 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 391 ret = 0;
392 goto out;
393 }
394 }
395 ret = 1;
396
ad312c7c 397 memcpy(vcpu->arch.pdptrs, pdpte, sizeof(vcpu->arch.pdptrs));
6de4f3ad
AK		 398 __set_bit(VCPU_EXREG_PDPTR,
399 (unsigned long *)&vcpu->arch.regs_avail);
400 __set_bit(VCPU_EXREG_PDPTR,
401 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 402out:
a03490ed
CO		 403
404 return ret;
405}
cc4b6871 406EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 407
d835dfec
AK		 408static bool pdptrs_changed(struct kvm_vcpu *vcpu)
409{
ad312c7c 410 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
d835dfec
AK		 411 bool changed = true;
412 int r;
413
414 if (is_long_mode(vcpu) || !is_pae(vcpu))
415 return false;
416
6de4f3ad
AK		 417 if (!test_bit(VCPU_EXREG_PDPTR,
418 (unsigned long *)&vcpu->arch.regs_avail))
419 return true;
420
ad312c7c 421 r = kvm_read_guest(vcpu->kvm, vcpu->arch.cr3 & ~31u, pdpte, sizeof(pdpte));
d835dfec
AK		 422 if (r < 0)
423 goto out;
ad312c7c 424 changed = memcmp(pdpte, vcpu->arch.pdptrs, sizeof(pdpte)) != 0;
d835dfec 425out:
d835dfec
AK		 426
427 return changed;
428}
429
2d3ad1f4 430void kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 431{
f9a48e6a
AK		 432 cr0 |= X86_CR0_ET;
433
ab344828
GN		 434#ifdef CONFIG_X86_64
435 if (cr0 & 0xffffffff00000000UL) {
c1a5d4f9 436 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 437 return;
438 }
ab344828
GN		 439#endif
440
441 cr0 &= ~CR0_RESERVED_BITS;
a03490ed
CO		 442
443 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) {
c1a5d4f9 444 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 445 return;
446 }
447
448 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) {
c1a5d4f9 449 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 450 return;
451 }
452
453 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
454#ifdef CONFIG_X86_64
f6801dff 455 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 456 int cs_db, cs_l;
457
458 if (!is_pae(vcpu)) {
c1a5d4f9 459 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 460 return;
461 }
462 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
463 if (cs_l) {
c1a5d4f9 464 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 465 return;
466
467 }
468 } else
469#endif
ad312c7c 470 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
c1a5d4f9 471 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 472 return;
473 }
474
475 }
476
477 kvm_x86_ops->set_cr0(vcpu, cr0);
ad312c7c 478 vcpu->arch.cr0 = cr0;
a03490ed 479
a03490ed 480 kvm_mmu_reset_context(vcpu);
a03490ed
CO		 481 return;
482}
2d3ad1f4 483EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 484
2d3ad1f4 485void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 486{
4d4ec087 487 kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0ful) | (msw & 0x0f));
a03490ed 488}
2d3ad1f4 489EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 490
2d3ad1f4 491void kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 492{
fc78f519 493 unsigned long old_cr4 = kvm_read_cr4(vcpu);
a2edf57f
AK		 494 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE;
495
a03490ed 496 if (cr4 & CR4_RESERVED_BITS) {
c1a5d4f9 497 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 498 return;
499 }
500
501 if (is_long_mode(vcpu)) {
502 if (!(cr4 & X86_CR4_PAE)) {
c1a5d4f9 503 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 504 return;
505 }
a2edf57f
AK		 506 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
507 && ((cr4 ^ old_cr4) & pdptr_bits)
ad312c7c 508 && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
c1a5d4f9 509 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 510 return;
511 }
512
513 if (cr4 & X86_CR4_VMXE) {
c1a5d4f9 514 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 515 return;
516 }
517 kvm_x86_ops->set_cr4(vcpu, cr4);
ad312c7c 518 vcpu->arch.cr4 = cr4;
5a41accd 519 vcpu->arch.mmu.base_role.cr4_pge = (cr4 & X86_CR4_PGE) && !tdp_enabled;
a03490ed 520 kvm_mmu_reset_context(vcpu);
a03490ed 521}
2d3ad1f4 522EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 523
2d3ad1f4 524void kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 525{
ad312c7c 526 if (cr3 == vcpu->arch.cr3 && !pdptrs_changed(vcpu)) {
0ba73cda 527 kvm_mmu_sync_roots(vcpu);
d835dfec
AK		 528 kvm_mmu_flush_tlb(vcpu);
529 return;
530 }
531
a03490ed
CO		 532 if (is_long_mode(vcpu)) {
533 if (cr3 & CR3_L_MODE_RESERVED_BITS) {
c1a5d4f9 534 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 535 return;
536 }
537 } else {
538 if (is_pae(vcpu)) {
539 if (cr3 & CR3_PAE_RESERVED_BITS) {
c1a5d4f9 540 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 541 return;
542 }
543 if (is_paging(vcpu) && !load_pdptrs(vcpu, cr3)) {
c1a5d4f9 544 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 545 return;
546 }
547 }
548 /*
549 * We don't check reserved bits in nonpae mode, because
550 * this isn't enforced, and VMware depends on this.
551 */
552 }
553
a03490ed
CO		 554 /*
555 * Does the new cr3 value map to physical memory? (Note, we
556 * catch an invalid cr3 even in real-mode, because it would
557 * cause trouble later on when we turn on paging anyway.)
558 *
559 * A real CPU would silently accept an invalid cr3 and would
560 * attempt to use it - with largely undefined (and often hard
561 * to debug) behavior on the guest side.
562 */
563 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
c1a5d4f9 564 kvm_inject_gp(vcpu, 0);
a03490ed 565 else {
ad312c7c
ZX		 566 vcpu->arch.cr3 = cr3;
567 vcpu->arch.mmu.new_cr3(vcpu);
a03490ed 568 }
a03490ed 569}
2d3ad1f4 570EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 571
2d3ad1f4 572void kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed
CO		 573{
574 if (cr8 & CR8_RESERVED_BITS) {
c1a5d4f9 575 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 576 return;
577 }
578 if (irqchip_in_kernel(vcpu->kvm))
579 kvm_lapic_set_tpr(vcpu, cr8);
580 else
ad312c7c 581 vcpu->arch.cr8 = cr8;
a03490ed 582}
2d3ad1f4 583EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 584
2d3ad1f4 585unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 586{
587 if (irqchip_in_kernel(vcpu->kvm))
588 return kvm_lapic_get_cr8(vcpu);
589 else
ad312c7c 590 return vcpu->arch.cr8;
a03490ed 591}
2d3ad1f4 592EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 593
d8017474
AG		 594static inline u32 bit(int bitno)
595{
596 return 1 << (bitno & 31);
597}
598
043405e1
CO		 599/*
600 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
601 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
602 *
603 * This list is modified at module load time to reflect the
e3267cbb
GC		 604 * capabilities of the host cpu. This capabilities test skips MSRs that are
605 * kvm-specific. Those are put in the beginning of the list.
043405e1 606 */
e3267cbb 607
10388a07 608#define KVM_SAVE_MSRS_BEGIN 5
043405e1 609static u32 msrs_to_save[] = {
e3267cbb 610 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
55cd8e5a 611 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
10388a07 612 HV_X64_MSR_APIC_ASSIST_PAGE,
043405e1
CO		 613 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
614 MSR_K6_STAR,
615#ifdef CONFIG_X86_64
616 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
617#endif
e3267cbb 618 MSR_IA32_TSC, MSR_IA32_PERF_STATUS, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
043405e1
CO		 619};
620
621static unsigned num_msrs_to_save;
622
623static u32 emulated_msrs[] = {
624 MSR_IA32_MISC_ENABLE,
625};
626
15c4a640
CO		 627static void set_efer(struct kvm_vcpu *vcpu, u64 efer)
628{
f2b4b7dd 629 if (efer & efer_reserved_bits) {
c1a5d4f9 630 kvm_inject_gp(vcpu, 0);
15c4a640
CO		 631 return;
632 }
633
634 if (is_paging(vcpu)
f6801dff 635 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME)) {
c1a5d4f9 636 kvm_inject_gp(vcpu, 0);
15c4a640
CO		 637 return;
638 }
639
1b2fd70c
AG		 640 if (efer & EFER_FFXSR) {
641 struct kvm_cpuid_entry2 *feat;
642
643 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
644 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT))) {
1b2fd70c
AG		 645 kvm_inject_gp(vcpu, 0);
646 return;
647 }
648 }
649
d8017474
AG		 650 if (efer & EFER_SVME) {
651 struct kvm_cpuid_entry2 *feat;
652
653 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
654 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM))) {
d8017474
AG		 655 kvm_inject_gp(vcpu, 0);
656 return;
657 }
658 }
659
15c4a640
CO		 660 kvm_x86_ops->set_efer(vcpu, efer);
661
662 efer &= ~EFER_LMA;
f6801dff 663 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 664
f6801dff 665 vcpu->arch.efer = efer;
9645bb56
AK		 666
667 vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
668 kvm_mmu_reset_context(vcpu);
15c4a640
CO		 669}
670
f2b4b7dd
JR		 671void kvm_enable_efer_bits(u64 mask)
672{
673 efer_reserved_bits &= ~mask;
674}
675EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
676
677
15c4a640
CO		 678/*
679 * Writes msr value into into the appropriate "register".
680 * Returns 0 on success, non-0 otherwise.
681 * Assumes vcpu_load() was already called.
682 */
683int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
684{
685 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
686}
687
313a3dc7
CO		 688/*
689 * Adapt set_msr() to msr_io()'s calling convention
690 */
691static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
692{
693 return kvm_set_msr(vcpu, index, *data);
694}
695
18068523
GOC		 696static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
697{
698 static int version;
50d0a0f9 699 struct pvclock_wall_clock wc;
923de3cf 700 struct timespec boot;
18068523
GOC		 701
702 if (!wall_clock)
703 return;
704
705 version++;
706
18068523
GOC		 707 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
708
50d0a0f9
GH		 709 /*
710 * The guest calculates current wall clock time by adding
711 * system time (updated by kvm_write_guest_time below) to the
712 * wall clock specified here. guest system time equals host
713 * system time for us, thus we must fill in host boot time here.
714 */
923de3cf 715 getboottime(&boot);
50d0a0f9
GH		 716
717 wc.sec = boot.tv_sec;
718 wc.nsec = boot.tv_nsec;
719 wc.version = version;
18068523
GOC		 720
721 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
722
723 version++;
724 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 725}
726
50d0a0f9
GH		 727static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
728{
729 uint32_t quotient, remainder;
730
731 /* Don't try to replace with do_div(), this one calculates
732 * "(dividend << 32) / divisor" */
733 __asm__ ( "divl %4"
734 : "=a" (quotient), "=d" (remainder)
735 : "0" (0), "1" (dividend), "r" (divisor) );
736 return quotient;
737}
738
739static void kvm_set_time_scale(uint32_t tsc_khz, struct pvclock_vcpu_time_info *hv_clock)
740{
741 uint64_t nsecs = 1000000000LL;
742 int32_t shift = 0;
743 uint64_t tps64;
744 uint32_t tps32;
745
746 tps64 = tsc_khz * 1000LL;
747 while (tps64 > nsecs*2) {
748 tps64 >>= 1;
749 shift--;
750 }
751
752 tps32 = (uint32_t)tps64;
753 while (tps32 <= (uint32_t)nsecs) {
754 tps32 <<= 1;
755 shift++;
756 }
757
758 hv_clock->tsc_shift = shift;
759 hv_clock->tsc_to_system_mul = div_frac(nsecs, tps32);
760
761 pr_debug("%s: tsc_khz %u, tsc_shift %d, tsc_mul %u\n",
80a914dc 762 __func__, tsc_khz, hv_clock->tsc_shift,
50d0a0f9
GH		 763 hv_clock->tsc_to_system_mul);
764}
765
c8076604
GH		 766static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
767
18068523
GOC		 768static void kvm_write_guest_time(struct kvm_vcpu *v)
769{
770 struct timespec ts;
771 unsigned long flags;
772 struct kvm_vcpu_arch *vcpu = &v->arch;
773 void *shared_kaddr;
463656c0 774 unsigned long this_tsc_khz;
18068523
GOC		 775
776 if ((!vcpu->time_page))
777 return;
778
463656c0
AK		 779 this_tsc_khz = get_cpu_var(cpu_tsc_khz);
780 if (unlikely(vcpu->hv_clock_tsc_khz != this_tsc_khz)) {
781 kvm_set_time_scale(this_tsc_khz, &vcpu->hv_clock);
782 vcpu->hv_clock_tsc_khz = this_tsc_khz;
50d0a0f9 783 }
463656c0 784 put_cpu_var(cpu_tsc_khz);
50d0a0f9 785
18068523
GOC		 786 /* Keep irq disabled to prevent changes to the clock */
787 local_irq_save(flags);
af24a4e4 788 kvm_get_msr(v, MSR_IA32_TSC, &vcpu->hv_clock.tsc_timestamp);
18068523 789 ktime_get_ts(&ts);
923de3cf 790 monotonic_to_bootbased(&ts);
18068523
GOC		 791 local_irq_restore(flags);
792
793 /* With all the info we got, fill in the values */
794
795 vcpu->hv_clock.system_time = ts.tv_nsec +
afbcf7ab
GC		 796 (NSEC_PER_SEC * (u64)ts.tv_sec) + v->kvm->arch.kvmclock_offset;
797
18068523
GOC		 798 /*
799 * The interface expects us to write an even number signaling that the
800 * update is finished. Since the guest won't see the intermediate
50d0a0f9 801 * state, we just increase by 2 at the end.
18068523 802 */
50d0a0f9 803 vcpu->hv_clock.version += 2;
18068523
GOC		 804
805 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
806
807 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
50d0a0f9 808 sizeof(vcpu->hv_clock));
18068523
GOC		 809
810 kunmap_atomic(shared_kaddr, KM_USER0);
811
812 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
813}
814
c8076604
GH		 815static int kvm_request_guest_time_update(struct kvm_vcpu *v)
816{
817 struct kvm_vcpu_arch *vcpu = &v->arch;
818
819 if (!vcpu->time_page)
820 return 0;
821 set_bit(KVM_REQ_KVMCLOCK_UPDATE, &v->requests);
822 return 1;
823}
824
9ba075a6
AK		 825static bool msr_mtrr_valid(unsigned msr)
826{
827 switch (msr) {
828 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
829 case MSR_MTRRfix64K_00000:
830 case MSR_MTRRfix16K_80000:
831 case MSR_MTRRfix16K_A0000:
832 case MSR_MTRRfix4K_C0000:
833 case MSR_MTRRfix4K_C8000:
834 case MSR_MTRRfix4K_D0000:
835 case MSR_MTRRfix4K_D8000:
836 case MSR_MTRRfix4K_E0000:
837 case MSR_MTRRfix4K_E8000:
838 case MSR_MTRRfix4K_F0000:
839 case MSR_MTRRfix4K_F8000:
840 case MSR_MTRRdefType:
841 case MSR_IA32_CR_PAT:
842 return true;
843 case 0x2f8:
844 return true;
845 }
846 return false;
847}
848
d6289b93
MT		 849static bool valid_pat_type(unsigned t)
850{
851 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
852}
853
854static bool valid_mtrr_type(unsigned t)
855{
856 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
857}
858
859static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
860{
861 int i;
862
863 if (!msr_mtrr_valid(msr))
864 return false;
865
866 if (msr == MSR_IA32_CR_PAT) {
867 for (i = 0; i < 8; i++)
868 if (!valid_pat_type((data >> (i * 8)) & 0xff))
869 return false;
870 return true;
871 } else if (msr == MSR_MTRRdefType) {
872 if (data & ~0xcff)
873 return false;
874 return valid_mtrr_type(data & 0xff);
875 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
876 for (i = 0; i < 8 ; i++)
877 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
878 return false;
879 return true;
880 }
881
882 /* variable MTRRs */
883 return valid_mtrr_type(data & 0xff);
884}
885
9ba075a6
AK		 886static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
887{
0bed3b56
SY		 888 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
889
d6289b93 890 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 891 return 1;
892
0bed3b56
SY		 893 if (msr == MSR_MTRRdefType) {
894 vcpu->arch.mtrr_state.def_type = data;
895 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
896 } else if (msr == MSR_MTRRfix64K_00000)
897 p[0] = data;
898 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
899 p[1 + msr - MSR_MTRRfix16K_80000] = data;
900 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
901 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
902 else if (msr == MSR_IA32_CR_PAT)
903 vcpu->arch.pat = data;
904 else { /* Variable MTRRs */
905 int idx, is_mtrr_mask;
906 u64 *pt;
907
908 idx = (msr - 0x200) / 2;
909 is_mtrr_mask = msr - 0x200 - 2 * idx;
910 if (!is_mtrr_mask)
911 pt =
912 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
913 else
914 pt =
915 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
916 *pt = data;
917 }
918
919 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 920 return 0;
921}
15c4a640 922
890ca9ae 923static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 924{
890ca9ae
HY		 925 u64 mcg_cap = vcpu->arch.mcg_cap;
926 unsigned bank_num = mcg_cap & 0xff;
927
15c4a640 928 switch (msr) {
15c4a640 929 case MSR_IA32_MCG_STATUS:
890ca9ae 930 vcpu->arch.mcg_status = data;
15c4a640 931 break;
c7ac679c 932 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 933 if (!(mcg_cap & MCG_CTL_P))
934 return 1;
935 if (data != 0 && data != ~(u64)0)
936 return -1;
937 vcpu->arch.mcg_ctl = data;
938 break;
939 default:
940 if (msr >= MSR_IA32_MC0_CTL &&
941 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
942 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 943 /* only 0 or all 1s can be written to IA32_MCi_CTL
944 * some Linux kernels though clear bit 10 in bank 4 to
945 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
946 * this to avoid an uncatched #GP in the guest
947 */
890ca9ae 948 if ((offset & 0x3) == 0 &&
114be429 949 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 950 return -1;
951 vcpu->arch.mce_banks[offset] = data;
952 break;
953 }
954 return 1;
955 }
956 return 0;
957}
958
ffde22ac
ES		 959static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
960{
961 struct kvm *kvm = vcpu->kvm;
962 int lm = is_long_mode(vcpu);
963 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
964 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
965 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
966 : kvm->arch.xen_hvm_config.blob_size_32;
967 u32 page_num = data & ~PAGE_MASK;
968 u64 page_addr = data & PAGE_MASK;
969 u8 *page;
970 int r;
971
972 r = -E2BIG;
973 if (page_num >= blob_size)
974 goto out;
975 r = -ENOMEM;
976 page = kzalloc(PAGE_SIZE, GFP_KERNEL);
977 if (!page)
978 goto out;
979 r = -EFAULT;
980 if (copy_from_user(page, blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE))
981 goto out_free;
982 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
983 goto out_free;
984 r = 0;
985out_free:
986 kfree(page);
987out:
988 return r;
989}
990
55cd8e5a
GN		 991static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
992{
993 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
994}
995
996static bool kvm_hv_msr_partition_wide(u32 msr)
997{
998 bool r = false;
999 switch (msr) {
1000 case HV_X64_MSR_GUEST_OS_ID:
1001 case HV_X64_MSR_HYPERCALL:
1002 r = true;
1003 break;
1004 }
1005
1006 return r;
1007}
1008
1009static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1010{
1011 struct kvm *kvm = vcpu->kvm;
1012
1013 switch (msr) {
1014 case HV_X64_MSR_GUEST_OS_ID:
1015 kvm->arch.hv_guest_os_id = data;
1016 /* setting guest os id to zero disables hypercall page */
1017 if (!kvm->arch.hv_guest_os_id)
1018 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1019 break;
1020 case HV_X64_MSR_HYPERCALL: {
1021 u64 gfn;
1022 unsigned long addr;
1023 u8 instructions[4];
1024
1025 /* if guest os id is not set hypercall should remain disabled */
1026 if (!kvm->arch.hv_guest_os_id)
1027 break;
1028 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1029 kvm->arch.hv_hypercall = data;
1030 break;
1031 }
1032 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1033 addr = gfn_to_hva(kvm, gfn);
1034 if (kvm_is_error_hva(addr))
1035 return 1;
1036 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1037 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
1038 if (copy_to_user((void __user *)addr, instructions, 4))
1039 return 1;
1040 kvm->arch.hv_hypercall = data;
1041 break;
1042 }
1043 default:
1044 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1045 "data 0x%llx\n", msr, data);
1046 return 1;
1047 }
1048 return 0;
1049}
1050
1051static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1052{
10388a07
GN		 1053 switch (msr) {
1054 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1055 unsigned long addr;
55cd8e5a 1056
10388a07
GN		 1057 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1058 vcpu->arch.hv_vapic = data;
1059 break;
1060 }
1061 addr = gfn_to_hva(vcpu->kvm, data >>
1062 HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1063 if (kvm_is_error_hva(addr))
1064 return 1;
1065 if (clear_user((void __user *)addr, PAGE_SIZE))
1066 return 1;
1067 vcpu->arch.hv_vapic = data;
1068 break;
1069 }
1070 case HV_X64_MSR_EOI:
1071 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1072 case HV_X64_MSR_ICR:
1073 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1074 case HV_X64_MSR_TPR:
1075 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1076 default:
1077 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1078 "data 0x%llx\n", msr, data);
1079 return 1;
1080 }
1081
1082 return 0;
55cd8e5a
GN		 1083}
1084
15c4a640
CO		 1085int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1086{
1087 switch (msr) {
15c4a640
CO		 1088 case MSR_EFER:
1089 set_efer(vcpu, data);
1090 break;
8f1589d9
AP		 1091 case MSR_K7_HWCR:
1092 data &= ~(u64)0x40; /* ignore flush filter disable */
1093 if (data != 0) {
1094 pr_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1095 data);
1096 return 1;
1097 }
15c4a640 1098 break;
f7c6d140
AP		 1099 case MSR_FAM10H_MMIO_CONF_BASE:
1100 if (data != 0) {
1101 pr_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1102 "0x%llx\n", data);
1103 return 1;
1104 }
15c4a640 1105 break;
c323c0e5 1106 case MSR_AMD64_NB_CFG:
c7ac679c 1107 break;
b5e2fec0
AG		 1108 case MSR_IA32_DEBUGCTLMSR:
1109 if (!data) {
1110 /* We support the non-activated case already */
1111 break;
1112 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1113 /* Values other than LBR and BTF are vendor-specific,
1114 thus reserved and should throw a #GP */
1115 return 1;
1116 }
1117 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1118 __func__, data);
1119 break;
15c4a640
CO		 1120 case MSR_IA32_UCODE_REV:
1121 case MSR_IA32_UCODE_WRITE:
61a6bd67 1122 case MSR_VM_HSAVE_PA:
6098ca93 1123 case MSR_AMD64_PATCH_LOADER:
15c4a640 1124 break;
9ba075a6
AK		 1125 case 0x200 ... 0x2ff:
1126 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 1127 case MSR_IA32_APICBASE:
1128 kvm_set_apic_base(vcpu, data);
1129 break;
0105d1a5
GN		 1130 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1131 return kvm_x2apic_msr_write(vcpu, msr, data);
15c4a640 1132 case MSR_IA32_MISC_ENABLE:
ad312c7c 1133 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 1134 break;
18068523
GOC		 1135 case MSR_KVM_WALL_CLOCK:
1136 vcpu->kvm->arch.wall_clock = data;
1137 kvm_write_wall_clock(vcpu->kvm, data);
1138 break;
1139 case MSR_KVM_SYSTEM_TIME: {
1140 if (vcpu->arch.time_page) {
1141 kvm_release_page_dirty(vcpu->arch.time_page);
1142 vcpu->arch.time_page = NULL;
1143 }
1144
1145 vcpu->arch.time = data;
1146
1147 /* we verify if the enable bit is set... */
1148 if (!(data & 1))
1149 break;
1150
1151 /* ...but clean it before doing the actual write */
1152 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
1153
18068523
GOC		 1154 vcpu->arch.time_page =
1155 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
18068523
GOC		 1156
1157 if (is_error_page(vcpu->arch.time_page)) {
1158 kvm_release_page_clean(vcpu->arch.time_page);
1159 vcpu->arch.time_page = NULL;
1160 }
1161
c8076604 1162 kvm_request_guest_time_update(vcpu);
18068523
GOC		 1163 break;
1164 }
890ca9ae
HY		 1165 case MSR_IA32_MCG_CTL:
1166 case MSR_IA32_MCG_STATUS:
1167 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1168 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 1169
1170 /* Performance counters are not protected by a CPUID bit,
1171 * so we should check all of them in the generic path for the sake of
1172 * cross vendor migration.
1173 * Writing a zero into the event select MSRs disables them,
1174 * which we perfectly emulate ;-). Any other value should be at least
1175 * reported, some guests depend on them.
1176 */
1177 case MSR_P6_EVNTSEL0:
1178 case MSR_P6_EVNTSEL1:
1179 case MSR_K7_EVNTSEL0:
1180 case MSR_K7_EVNTSEL1:
1181 case MSR_K7_EVNTSEL2:
1182 case MSR_K7_EVNTSEL3:
1183 if (data != 0)
1184 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1185 "0x%x data 0x%llx\n", msr, data);
1186 break;
1187 /* at least RHEL 4 unconditionally writes to the perfctr registers,
1188 * so we ignore writes to make it happy.
1189 */
1190 case MSR_P6_PERFCTR0:
1191 case MSR_P6_PERFCTR1:
1192 case MSR_K7_PERFCTR0:
1193 case MSR_K7_PERFCTR1:
1194 case MSR_K7_PERFCTR2:
1195 case MSR_K7_PERFCTR3:
1196 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1197 "0x%x data 0x%llx\n", msr, data);
1198 break;
55cd8e5a
GN		 1199 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1200 if (kvm_hv_msr_partition_wide(msr)) {
1201 int r;
1202 mutex_lock(&vcpu->kvm->lock);
1203 r = set_msr_hyperv_pw(vcpu, msr, data);
1204 mutex_unlock(&vcpu->kvm->lock);
1205 return r;
1206 } else
1207 return set_msr_hyperv(vcpu, msr, data);
1208 break;
15c4a640 1209 default:
ffde22ac
ES		 1210 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
1211 return xen_hvm_config(vcpu, data);
ed85c068
AP		 1212 if (!ignore_msrs) {
1213 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
1214 msr, data);
1215 return 1;
1216 } else {
1217 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
1218 msr, data);
1219 break;
1220 }
15c4a640
CO		 1221 }
1222 return 0;
1223}
1224EXPORT_SYMBOL_GPL(kvm_set_msr_common);
1225
1226
1227/*
1228 * Reads an msr value (of 'msr_index') into 'pdata'.
1229 * Returns 0 on success, non-0 otherwise.
1230 * Assumes vcpu_load() was already called.
1231 */
1232int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1233{
1234 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
1235}
1236
9ba075a6
AK		 1237static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1238{
0bed3b56
SY		 1239 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1240
9ba075a6
AK		 1241 if (!msr_mtrr_valid(msr))
1242 return 1;
1243
0bed3b56
SY		 1244 if (msr == MSR_MTRRdefType)
1245 *pdata = vcpu->arch.mtrr_state.def_type +
1246 (vcpu->arch.mtrr_state.enabled << 10);
1247 else if (msr == MSR_MTRRfix64K_00000)
1248 *pdata = p[0];
1249 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1250 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
1251 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1252 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
1253 else if (msr == MSR_IA32_CR_PAT)
1254 *pdata = vcpu->arch.pat;
1255 else { /* Variable MTRRs */
1256 int idx, is_mtrr_mask;
1257 u64 *pt;
1258
1259 idx = (msr - 0x200) / 2;
1260 is_mtrr_mask = msr - 0x200 - 2 * idx;
1261 if (!is_mtrr_mask)
1262 pt =
1263 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1264 else
1265 pt =
1266 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1267 *pdata = *pt;
1268 }
1269
9ba075a6
AK		 1270 return 0;
1271}
1272
890ca9ae 1273static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 1274{
1275 u64 data;
890ca9ae
HY		 1276 u64 mcg_cap = vcpu->arch.mcg_cap;
1277 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 1278
1279 switch (msr) {
15c4a640
CO		 1280 case MSR_IA32_P5_MC_ADDR:
1281 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 1282 data = 0;
1283 break;
15c4a640 1284 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 1285 data = vcpu->arch.mcg_cap;
1286 break;
c7ac679c 1287 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1288 if (!(mcg_cap & MCG_CTL_P))
1289 return 1;
1290 data = vcpu->arch.mcg_ctl;
1291 break;
1292 case MSR_IA32_MCG_STATUS:
1293 data = vcpu->arch.mcg_status;
1294 break;
1295 default:
1296 if (msr >= MSR_IA32_MC0_CTL &&
1297 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1298 u32 offset = msr - MSR_IA32_MC0_CTL;
1299 data = vcpu->arch.mce_banks[offset];
1300 break;
1301 }
1302 return 1;
1303 }
1304 *pdata = data;
1305 return 0;
1306}
1307
55cd8e5a
GN		 1308static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1309{
1310 u64 data = 0;
1311 struct kvm *kvm = vcpu->kvm;
1312
1313 switch (msr) {
1314 case HV_X64_MSR_GUEST_OS_ID:
1315 data = kvm->arch.hv_guest_os_id;
1316 break;
1317 case HV_X64_MSR_HYPERCALL:
1318 data = kvm->arch.hv_hypercall;
1319 break;
1320 default:
1321 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1322 return 1;
1323 }
1324
1325 *pdata = data;
1326 return 0;
1327}
1328
1329static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1330{
1331 u64 data = 0;
1332
1333 switch (msr) {
1334 case HV_X64_MSR_VP_INDEX: {
1335 int r;
1336 struct kvm_vcpu *v;
1337 kvm_for_each_vcpu(r, v, vcpu->kvm)
1338 if (v == vcpu)
1339 data = r;
1340 break;
1341 }
10388a07
GN		 1342 case HV_X64_MSR_EOI:
1343 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
1344 case HV_X64_MSR_ICR:
1345 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
1346 case HV_X64_MSR_TPR:
1347 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
55cd8e5a
GN		 1348 default:
1349 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1350 return 1;
1351 }
1352 *pdata = data;
1353 return 0;
1354}
1355
890ca9ae
HY		 1356int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1357{
1358 u64 data;
1359
1360 switch (msr) {
890ca9ae 1361 case MSR_IA32_PLATFORM_ID:
15c4a640 1362 case MSR_IA32_UCODE_REV:
15c4a640 1363 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 1364 case MSR_IA32_DEBUGCTLMSR:
1365 case MSR_IA32_LASTBRANCHFROMIP:
1366 case MSR_IA32_LASTBRANCHTOIP:
1367 case MSR_IA32_LASTINTFROMIP:
1368 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 1369 case MSR_K8_SYSCFG:
1370 case MSR_K7_HWCR:
61a6bd67 1371 case MSR_VM_HSAVE_PA:
1f3ee616
AS		 1372 case MSR_P6_PERFCTR0:
1373 case MSR_P6_PERFCTR1:
7fe29e0f
AS		 1374 case MSR_P6_EVNTSEL0:
1375 case MSR_P6_EVNTSEL1:
9e699624 1376 case MSR_K7_EVNTSEL0:
1f3ee616 1377 case MSR_K7_PERFCTR0:
1fdbd48c 1378 case MSR_K8_INT_PENDING_MSG:
c323c0e5 1379 case MSR_AMD64_NB_CFG:
f7c6d140 1380 case MSR_FAM10H_MMIO_CONF_BASE:
15c4a640
CO		 1381 data = 0;
1382 break;
9ba075a6
AK		 1383 case MSR_MTRRcap:
1384 data = 0x500 | KVM_NR_VAR_MTRR;
1385 break;
1386 case 0x200 ... 0x2ff:
1387 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 1388 case 0xcd: /* fsb frequency */
1389 data = 3;
1390 break;
1391 case MSR_IA32_APICBASE:
1392 data = kvm_get_apic_base(vcpu);
1393 break;
0105d1a5
GN		 1394 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1395 return kvm_x2apic_msr_read(vcpu, msr, pdata);
1396 break;
15c4a640 1397 case MSR_IA32_MISC_ENABLE:
ad312c7c 1398 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 1399 break;
847f0ad8
AG		 1400 case MSR_IA32_PERF_STATUS:
1401 /* TSC increment by tick */
1402 data = 1000ULL;
1403 /* CPU multiplier */
1404 data |= (((uint64_t)4ULL) << 40);
1405 break;
15c4a640 1406 case MSR_EFER:
f6801dff 1407 data = vcpu->arch.efer;
15c4a640 1408 break;
18068523
GOC		 1409 case MSR_KVM_WALL_CLOCK:
1410 data = vcpu->kvm->arch.wall_clock;
1411 break;
1412 case MSR_KVM_SYSTEM_TIME:
1413 data = vcpu->arch.time;
1414 break;
890ca9ae
HY		 1415 case MSR_IA32_P5_MC_ADDR:
1416 case MSR_IA32_P5_MC_TYPE:
1417 case MSR_IA32_MCG_CAP:
1418 case MSR_IA32_MCG_CTL:
1419 case MSR_IA32_MCG_STATUS:
1420 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1421 return get_msr_mce(vcpu, msr, pdata);
55cd8e5a
GN		 1422 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1423 if (kvm_hv_msr_partition_wide(msr)) {
1424 int r;
1425 mutex_lock(&vcpu->kvm->lock);
1426 r = get_msr_hyperv_pw(vcpu, msr, pdata);
1427 mutex_unlock(&vcpu->kvm->lock);
1428 return r;
1429 } else
1430 return get_msr_hyperv(vcpu, msr, pdata);
1431 break;
15c4a640 1432 default:
ed85c068
AP		 1433 if (!ignore_msrs) {
1434 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
1435 return 1;
1436 } else {
1437 pr_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
1438 data = 0;
1439 }
1440 break;
15c4a640
CO		 1441 }
1442 *pdata = data;
1443 return 0;
1444}
1445EXPORT_SYMBOL_GPL(kvm_get_msr_common);
1446
313a3dc7
CO		 1447/*
1448 * Read or write a bunch of msrs. All parameters are kernel addresses.
1449 *
1450 * @return number of msrs set successfully.
1451 */
1452static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
1453 struct kvm_msr_entry *entries,
1454 int (*do_msr)(struct kvm_vcpu *vcpu,
1455 unsigned index, u64 *data))
1456{
f656ce01 1457 int i, idx;
313a3dc7
CO		 1458
1459 vcpu_load(vcpu);
1460
f656ce01 1461 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 1462 for (i = 0; i < msrs->nmsrs; ++i)
1463 if (do_msr(vcpu, entries[i].index, &entries[i].data))
1464 break;
f656ce01 1465 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7
CO		 1466
1467 vcpu_put(vcpu);
1468
1469 return i;
1470}
1471
1472/*
1473 * Read or write a bunch of msrs. Parameters are user addresses.
1474 *
1475 * @return number of msrs set successfully.
1476 */
1477static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
1478 int (*do_msr)(struct kvm_vcpu *vcpu,
1479 unsigned index, u64 *data),
1480 int writeback)
1481{
1482 struct kvm_msrs msrs;
1483 struct kvm_msr_entry *entries;
1484 int r, n;
1485 unsigned size;
1486
1487 r = -EFAULT;
1488 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
1489 goto out;
1490
1491 r = -E2BIG;
1492 if (msrs.nmsrs >= MAX_IO_MSRS)
1493 goto out;
1494
1495 r = -ENOMEM;
1496 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
1497 entries = vmalloc(size);
1498 if (!entries)
1499 goto out;
1500
1501 r = -EFAULT;
1502 if (copy_from_user(entries, user_msrs->entries, size))
1503 goto out_free;
1504
1505 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
1506 if (r < 0)
1507 goto out_free;
1508
1509 r = -EFAULT;
1510 if (writeback && copy_to_user(user_msrs->entries, entries, size))
1511 goto out_free;
1512
1513 r = n;
1514
1515out_free:
1516 vfree(entries);
1517out:
1518 return r;
1519}
1520
018d00d2
ZX		 1521int kvm_dev_ioctl_check_extension(long ext)
1522{
1523 int r;
1524
1525 switch (ext) {
1526 case KVM_CAP_IRQCHIP:
1527 case KVM_CAP_HLT:
1528 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 1529 case KVM_CAP_SET_TSS_ADDR:
07716717 1530 case KVM_CAP_EXT_CPUID:
c8076604 1531 case KVM_CAP_CLOCKSOURCE:
7837699f 1532 case KVM_CAP_PIT:
a28e4f5a 1533 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 1534 case KVM_CAP_MP_STATE:
ed848624 1535 case KVM_CAP_SYNC_MMU:
52d939a0 1536 case KVM_CAP_REINJECT_CONTROL:
4925663a 1537 case KVM_CAP_IRQ_INJECT_STATUS:
e56d532f 1538 case KVM_CAP_ASSIGN_DEV_IRQ:
721eecbf 1539 case KVM_CAP_IRQFD:
d34e6b17 1540 case KVM_CAP_IOEVENTFD:
c5ff41ce 1541 case KVM_CAP_PIT2:
e9f42757 1542 case KVM_CAP_PIT_STATE2:
b927a3ce 1543 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 1544 case KVM_CAP_XEN_HVM:
afbcf7ab 1545 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 1546 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 1547 case KVM_CAP_HYPERV:
10388a07 1548 case KVM_CAP_HYPERV_VAPIC:
c25bc163 1549 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 1550 case KVM_CAP_PCI_SEGMENT:
d2be1651 1551 case KVM_CAP_X86_ROBUST_SINGLESTEP:
018d00d2
ZX		 1552 r = 1;
1553 break;
542472b5
LV		 1554 case KVM_CAP_COALESCED_MMIO:
1555 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
1556 break;
774ead3a
AK		 1557 case KVM_CAP_VAPIC:
1558 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
1559 break;
f725230a
AK		 1560 case KVM_CAP_NR_VCPUS:
1561 r = KVM_MAX_VCPUS;
1562 break;
a988b910
AK		 1563 case KVM_CAP_NR_MEMSLOTS:
1564 r = KVM_MEMORY_SLOTS;
1565 break;
a68a6a72
MT		 1566 case KVM_CAP_PV_MMU: /* obsolete */
1567 r = 0;
2f333bcb 1568 break;
62c476c7 1569 case KVM_CAP_IOMMU:
19de40a8 1570 r = iommu_found();
62c476c7 1571 break;
890ca9ae
HY		 1572 case KVM_CAP_MCE:
1573 r = KVM_MAX_MCE_BANKS;
1574 break;
018d00d2
ZX		 1575 default:
1576 r = 0;
1577 break;
1578 }
1579 return r;
1580
1581}
1582
043405e1
CO		 1583long kvm_arch_dev_ioctl(struct file *filp,
1584 unsigned int ioctl, unsigned long arg)
1585{
1586 void __user *argp = (void __user *)arg;
1587 long r;
1588
1589 switch (ioctl) {
1590 case KVM_GET_MSR_INDEX_LIST: {
1591 struct kvm_msr_list __user *user_msr_list = argp;
1592 struct kvm_msr_list msr_list;
1593 unsigned n;
1594
1595 r = -EFAULT;
1596 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
1597 goto out;
1598 n = msr_list.nmsrs;
1599 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
1600 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
1601 goto out;
1602 r = -E2BIG;
e125e7b6 1603 if (n < msr_list.nmsrs)
043405e1
CO		 1604 goto out;
1605 r = -EFAULT;
1606 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
1607 num_msrs_to_save * sizeof(u32)))
1608 goto out;
e125e7b6 1609 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 1610 &emulated_msrs,
1611 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
1612 goto out;
1613 r = 0;
1614 break;
1615 }
674eea0f
AK		 1616 case KVM_GET_SUPPORTED_CPUID: {
1617 struct kvm_cpuid2 __user *cpuid_arg = argp;
1618 struct kvm_cpuid2 cpuid;
1619
1620 r = -EFAULT;
1621 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1622 goto out;
1623 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
19355475 1624 cpuid_arg->entries);
674eea0f
AK		 1625 if (r)
1626 goto out;
1627
1628 r = -EFAULT;
1629 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
1630 goto out;
1631 r = 0;
1632 break;
1633 }
890ca9ae
HY		 1634 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
1635 u64 mce_cap;
1636
1637 mce_cap = KVM_MCE_CAP_SUPPORTED;
1638 r = -EFAULT;
1639 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
1640 goto out;
1641 r = 0;
1642 break;
1643 }
043405e1
CO		 1644 default:
1645 r = -EINVAL;
1646 }
1647out:
1648 return r;
1649}
1650
313a3dc7
CO		 1651void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1652{
1653 kvm_x86_ops->vcpu_load(vcpu, cpu);
6b7d7e76
ZA		 1654 if (unlikely(per_cpu(cpu_tsc_khz, cpu) == 0)) {
1655 unsigned long khz = cpufreq_quick_get(cpu);
1656 if (!khz)
1657 khz = tsc_khz;
1658 per_cpu(cpu_tsc_khz, cpu) = khz;
1659 }
c8076604 1660 kvm_request_guest_time_update(vcpu);
313a3dc7
CO		 1661}
1662
1663void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
1664{
9327fd11 1665 kvm_put_guest_fpu(vcpu);
02daab21 1666 kvm_x86_ops->vcpu_put(vcpu);
313a3dc7
CO		 1667}
1668
07716717 1669static int is_efer_nx(void)
313a3dc7 1670{
e286e86e 1671 unsigned long long efer = 0;
313a3dc7 1672
e286e86e 1673 rdmsrl_safe(MSR_EFER, &efer);
07716717
DK		 1674 return efer & EFER_NX;
1675}
1676
1677static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
1678{
1679 int i;
1680 struct kvm_cpuid_entry2 *e, *entry;
1681
313a3dc7 1682 entry = NULL;
ad312c7c
ZX		 1683 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
1684 e = &vcpu->arch.cpuid_entries[i];
313a3dc7
CO		 1685 if (e->function == 0x80000001) {
1686 entry = e;
1687 break;
1688 }
1689 }
07716717 1690 if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) {
313a3dc7
CO		 1691 entry->edx &= ~(1 << 20);
1692 printk(KERN_INFO "kvm: guest NX capability removed\n");
1693 }
1694}
1695
07716717 1696/* when an old userspace process fills a new kernel module */
313a3dc7
CO		 1697static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
1698 struct kvm_cpuid *cpuid,
1699 struct kvm_cpuid_entry __user *entries)
07716717
DK		 1700{
1701 int r, i;
1702 struct kvm_cpuid_entry *cpuid_entries;
1703
1704 r = -E2BIG;
1705 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1706 goto out;
1707 r = -ENOMEM;
1708 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent);
1709 if (!cpuid_entries)
1710 goto out;
1711 r = -EFAULT;
1712 if (copy_from_user(cpuid_entries, entries,
1713 cpuid->nent * sizeof(struct kvm_cpuid_entry)))
1714 goto out_free;
1715 for (i = 0; i < cpuid->nent; i++) {
ad312c7c
ZX		 1716 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
1717 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
1718 vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx;
1719 vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx;
1720 vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx;
1721 vcpu->arch.cpuid_entries[i].index = 0;
1722 vcpu->arch.cpuid_entries[i].flags = 0;
1723 vcpu->arch.cpuid_entries[i].padding[0] = 0;
1724 vcpu->arch.cpuid_entries[i].padding[1] = 0;
1725 vcpu->arch.cpuid_entries[i].padding[2] = 0;
1726 }
1727 vcpu->arch.cpuid_nent = cpuid->nent;
07716717
DK		 1728 cpuid_fix_nx_cap(vcpu);
1729 r = 0;
fc61b800 1730 kvm_apic_set_version(vcpu);
0e851880 1731 kvm_x86_ops->cpuid_update(vcpu);
07716717
DK		 1732
1733out_free:
1734 vfree(cpuid_entries);
1735out:
1736 return r;
1737}
1738
1739static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 1740 struct kvm_cpuid2 *cpuid,
1741 struct kvm_cpuid_entry2 __user *entries)
313a3dc7
CO		 1742{
1743 int r;
1744
1745 r = -E2BIG;
1746 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1747 goto out;
1748 r = -EFAULT;
ad312c7c 1749 if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
07716717 1750 cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
313a3dc7 1751 goto out;
ad312c7c 1752 vcpu->arch.cpuid_nent = cpuid->nent;
fc61b800 1753 kvm_apic_set_version(vcpu);
0e851880 1754 kvm_x86_ops->cpuid_update(vcpu);
313a3dc7
CO		 1755 return 0;
1756
1757out:
1758 return r;
1759}
1760
07716717 1761static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 1762 struct kvm_cpuid2 *cpuid,
1763 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 1764{
1765 int r;
1766
1767 r = -E2BIG;
ad312c7c 1768 if (cpuid->nent < vcpu->arch.cpuid_nent)
07716717
DK		 1769 goto out;
1770 r = -EFAULT;
ad312c7c 1771 if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
19355475 1772 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 1773 goto out;
1774 return 0;
1775
1776out:
ad312c7c 1777 cpuid->nent = vcpu->arch.cpuid_nent;
07716717
DK		 1778 return r;
1779}
1780
07716717 1781static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function,
19355475 1782 u32 index)
07716717
DK		 1783{
1784 entry->function = function;
1785 entry->index = index;
1786 cpuid_count(entry->function, entry->index,
19355475 1787 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
07716717
DK		 1788 entry->flags = 0;
1789}
1790
7faa4ee1
AK		 1791#define F(x) bit(X86_FEATURE_##x)
1792
07716717
DK		 1793static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
1794 u32 index, int *nent, int maxnent)
1795{
7faa4ee1 1796 unsigned f_nx = is_efer_nx() ? F(NX) : 0;
07716717 1797#ifdef CONFIG_X86_64
17cc3935
SY		 1798 unsigned f_gbpages = (kvm_x86_ops->get_lpage_level() == PT_PDPE_LEVEL)
1799 ? F(GBPAGES) : 0;
7faa4ee1
AK		 1800 unsigned f_lm = F(LM);
1801#else
17cc3935 1802 unsigned f_gbpages = 0;
7faa4ee1 1803 unsigned f_lm = 0;
07716717 1804#endif
4e47c7a6 1805 unsigned f_rdtscp = kvm_x86_ops->rdtscp_supported() ? F(RDTSCP) : 0;
7faa4ee1
AK		 1806
1807 /* cpuid 1.edx */
1808 const u32 kvm_supported_word0_x86_features =
1809 F(FPU) | F(VME) | F(DE) | F(PSE) |
1810 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
1811 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) |
1812 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
1813 F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLSH) |
1814 0 /* Reserved, DS, ACPI */ | F(MMX) |
1815 F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) |
1816 0 /* HTT, TM, Reserved, PBE */;
1817 /* cpuid 0x80000001.edx */
1818 const u32 kvm_supported_word1_x86_features =
1819 F(FPU) | F(VME) | F(DE) | F(PSE) |
1820 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
1821 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) |
1822 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
1823 F(PAT) | F(PSE36) | 0 /* Reserved */ |
1824 f_nx | 0 /* Reserved */ | F(MMXEXT) | F(MMX) |
4e47c7a6 1825 F(FXSR) | F(FXSR_OPT) | f_gbpages | f_rdtscp |
7faa4ee1
AK		 1826 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW);
1827 /* cpuid 1.ecx */
1828 const u32 kvm_supported_word4_x86_features =
d149c731
AK		 1829 F(XMM3) | 0 /* Reserved, DTES64, MONITOR */ |
1830 0 /* DS-CPL, VMX, SMX, EST */ |
1831 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ |
1832 0 /* Reserved */ | F(CX16) | 0 /* xTPR Update, PDCM */ |
1833 0 /* Reserved, DCA */ | F(XMM4_1) |
0105d1a5 1834 F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) |
d149c731 1835 0 /* Reserved, XSAVE, OSXSAVE */;
7faa4ee1 1836 /* cpuid 0x80000001.ecx */
07716717 1837 const u32 kvm_supported_word6_x86_features =
7faa4ee1
AK		 1838 F(LAHF_LM) | F(CMP_LEGACY) | F(SVM) | 0 /* ExtApicSpace */ |
1839 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) |
1840 F(3DNOWPREFETCH) | 0 /* OSVW */ | 0 /* IBS */ | F(SSE5) |
1841 0 /* SKINIT */ | 0 /* WDT */;
07716717 1842
19355475 1843 /* all calls to cpuid_count() should be made on the same cpu */
07716717
DK		 1844 get_cpu();
1845 do_cpuid_1_ent(entry, function, index);
1846 ++*nent;
1847
1848 switch (function) {
1849 case 0:
1850 entry->eax = min(entry->eax, (u32)0xb);
1851 break;
1852 case 1:
1853 entry->edx &= kvm_supported_word0_x86_features;
7faa4ee1 1854 entry->ecx &= kvm_supported_word4_x86_features;
0d1de2d9
GN		 1855 /* we support x2apic emulation even if host does not support
1856 * it since we emulate x2apic in software */
1857 entry->ecx |= F(X2APIC);
07716717
DK		 1858 break;
1859 /* function 2 entries are STATEFUL. That is, repeated cpuid commands
1860 * may return different values. This forces us to get_cpu() before
1861 * issuing the first command, and also to emulate this annoying behavior
1862 * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */
1863 case 2: {
1864 int t, times = entry->eax & 0xff;
1865
1866 entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
0fdf8e59 1867 entry->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
07716717
DK		 1868 for (t = 1; t < times && *nent < maxnent; ++t) {
1869 do_cpuid_1_ent(&entry[t], function, 0);
1870 entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
1871 ++*nent;
1872 }
1873 break;
1874 }
1875 /* function 4 and 0xb have additional index. */
1876 case 4: {
14af3f3c 1877 int i, cache_type;
07716717
DK		 1878
1879 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1880 /* read more entries until cache_type is zero */
14af3f3c
HH		 1881 for (i = 1; *nent < maxnent; ++i) {
1882 cache_type = entry[i - 1].eax & 0x1f;
07716717
DK		 1883 if (!cache_type)
1884 break;
14af3f3c
HH		 1885 do_cpuid_1_ent(&entry[i], function, i);
1886 entry[i].flags |=
07716717
DK		 1887 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1888 ++*nent;
1889 }
1890 break;
1891 }
1892 case 0xb: {
14af3f3c 1893 int i, level_type;
07716717
DK		 1894
1895 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1896 /* read more entries until level_type is zero */
14af3f3c 1897 for (i = 1; *nent < maxnent; ++i) {
0853d2c1 1898 level_type = entry[i - 1].ecx & 0xff00;
07716717
DK		 1899 if (!level_type)
1900 break;
14af3f3c
HH		 1901 do_cpuid_1_ent(&entry[i], function, i);
1902 entry[i].flags |=
07716717
DK		 1903 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1904 ++*nent;
1905 }
1906 break;
1907 }
1908 case 0x80000000:
1909 entry->eax = min(entry->eax, 0x8000001a);
1910 break;
1911 case 0x80000001:
1912 entry->edx &= kvm_supported_word1_x86_features;
1913 entry->ecx &= kvm_supported_word6_x86_features;
1914 break;
1915 }
1916 put_cpu();
1917}
1918
7faa4ee1
AK		 1919#undef F
1920
674eea0f 1921static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
19355475 1922 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 1923{
1924 struct kvm_cpuid_entry2 *cpuid_entries;
1925 int limit, nent = 0, r = -E2BIG;
1926 u32 func;
1927
1928 if (cpuid->nent < 1)
1929 goto out;
6a544355
AK		 1930 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1931 cpuid->nent = KVM_MAX_CPUID_ENTRIES;
07716717
DK		 1932 r = -ENOMEM;
1933 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent);
1934 if (!cpuid_entries)
1935 goto out;
1936
1937 do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent);
1938 limit = cpuid_entries[0].eax;
1939 for (func = 1; func <= limit && nent < cpuid->nent; ++func)
1940 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 1941 &nent, cpuid->nent);
07716717
DK		 1942 r = -E2BIG;
1943 if (nent >= cpuid->nent)
1944 goto out_free;
1945
1946 do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent);
1947 limit = cpuid_entries[nent - 1].eax;
1948 for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func)
1949 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 1950 &nent, cpuid->nent);
cb007648
MM		 1951 r = -E2BIG;
1952 if (nent >= cpuid->nent)
1953 goto out_free;
1954
07716717
DK		 1955 r = -EFAULT;
1956 if (copy_to_user(entries, cpuid_entries,
19355475 1957 nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 1958 goto out_free;
1959 cpuid->nent = nent;
1960 r = 0;
1961
1962out_free:
1963 vfree(cpuid_entries);
1964out:
1965 return r;
1966}
1967
313a3dc7
CO		 1968static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
1969 struct kvm_lapic_state *s)
1970{
1971 vcpu_load(vcpu);
ad312c7c 1972 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 1973 vcpu_put(vcpu);
1974
1975 return 0;
1976}
1977
1978static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
1979 struct kvm_lapic_state *s)
1980{
1981 vcpu_load(vcpu);
ad312c7c 1982 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
313a3dc7 1983 kvm_apic_post_state_restore(vcpu);
cb142eb7 1984 update_cr8_intercept(vcpu);
313a3dc7
CO		 1985 vcpu_put(vcpu);
1986
1987 return 0;
1988}
1989
f77bc6a4
ZX		 1990static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
1991 struct kvm_interrupt *irq)
1992{
1993 if (irq->irq < 0 || irq->irq >= 256)
1994 return -EINVAL;
1995 if (irqchip_in_kernel(vcpu->kvm))
1996 return -ENXIO;
1997 vcpu_load(vcpu);
1998
66fd3f7f 1999 kvm_queue_interrupt(vcpu, irq->irq, false);
f77bc6a4
ZX		 2000
2001 vcpu_put(vcpu);
2002
2003 return 0;
2004}
2005
c4abb7c9
JK		 2006static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2007{
2008 vcpu_load(vcpu);
2009 kvm_inject_nmi(vcpu);
2010 vcpu_put(vcpu);
2011
2012 return 0;
2013}
2014
b209749f
AK		 2015static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2016 struct kvm_tpr_access_ctl *tac)
2017{
2018 if (tac->flags)
2019 return -EINVAL;
2020 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2021 return 0;
2022}
2023
890ca9ae
HY		 2024static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2025 u64 mcg_cap)
2026{
2027 int r;
2028 unsigned bank_num = mcg_cap & 0xff, bank;
2029
2030 r = -EINVAL;
a9e38c3e 2031 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2032 goto out;
2033 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2034 goto out;
2035 r = 0;
2036 vcpu->arch.mcg_cap = mcg_cap;
2037 /* Init IA32_MCG_CTL to all 1s */
2038 if (mcg_cap & MCG_CTL_P)
2039 vcpu->arch.mcg_ctl = ~(u64)0;
2040 /* Init IA32_MCi_CTL to all 1s */
2041 for (bank = 0; bank < bank_num; bank++)
2042 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2043out:
2044 return r;
2045}
2046
2047static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2048 struct kvm_x86_mce *mce)
2049{
2050 u64 mcg_cap = vcpu->arch.mcg_cap;
2051 unsigned bank_num = mcg_cap & 0xff;
2052 u64 *banks = vcpu->arch.mce_banks;
2053
2054 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2055 return -EINVAL;
2056 /*
2057 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2058 * reporting is disabled
2059 */
2060 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2061 vcpu->arch.mcg_ctl != ~(u64)0)
2062 return 0;
2063 banks += 4 * mce->bank;
2064 /*
2065 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2066 * reporting is disabled for the bank
2067 */
2068 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2069 return 0;
2070 if (mce->status & MCI_STATUS_UC) {
2071 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2072 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
890ca9ae
HY		 2073 printk(KERN_DEBUG "kvm: set_mce: "
2074 "injects mce exception while "
2075 "previous one is in progress!\n");
2076 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
2077 return 0;
2078 }
2079 if (banks[1] & MCI_STATUS_VAL)
2080 mce->status |= MCI_STATUS_OVER;
2081 banks[2] = mce->addr;
2082 banks[3] = mce->misc;
2083 vcpu->arch.mcg_status = mce->mcg_status;
2084 banks[1] = mce->status;
2085 kvm_queue_exception(vcpu, MC_VECTOR);
2086 } else if (!(banks[1] & MCI_STATUS_VAL)
2087 || !(banks[1] & MCI_STATUS_UC)) {
2088 if (banks[1] & MCI_STATUS_VAL)
2089 mce->status |= MCI_STATUS_OVER;
2090 banks[2] = mce->addr;
2091 banks[3] = mce->misc;
2092 banks[1] = mce->status;
2093 } else
2094 banks[1] |= MCI_STATUS_OVER;
2095 return 0;
2096}
2097
3cfc3092
JK		 2098static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2099 struct kvm_vcpu_events *events)
2100{
2101 vcpu_load(vcpu);
2102
03b82a30
JK		 2103 events->exception.injected =
2104 vcpu->arch.exception.pending &&
2105 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2106 events->exception.nr = vcpu->arch.exception.nr;
2107 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
2108 events->exception.error_code = vcpu->arch.exception.error_code;
2109
03b82a30
JK		 2110 events->interrupt.injected =
2111 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2112 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2113 events->interrupt.soft = 0;
3cfc3092
JK		 2114
2115 events->nmi.injected = vcpu->arch.nmi_injected;
2116 events->nmi.pending = vcpu->arch.nmi_pending;
2117 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
2118
2119 events->sipi_vector = vcpu->arch.sipi_vector;
2120
dab4b911
JK		 2121 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
2122 | KVM_VCPUEVENT_VALID_SIPI_VECTOR);
3cfc3092
JK		 2123
2124 vcpu_put(vcpu);
2125}
2126
2127static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2128 struct kvm_vcpu_events *events)
2129{
dab4b911
JK		 2130 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
2131 | KVM_VCPUEVENT_VALID_SIPI_VECTOR))
3cfc3092
JK		 2132 return -EINVAL;
2133
2134 vcpu_load(vcpu);
2135
2136 vcpu->arch.exception.pending = events->exception.injected;
2137 vcpu->arch.exception.nr = events->exception.nr;
2138 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2139 vcpu->arch.exception.error_code = events->exception.error_code;
2140
2141 vcpu->arch.interrupt.pending = events->interrupt.injected;
2142 vcpu->arch.interrupt.nr = events->interrupt.nr;
2143 vcpu->arch.interrupt.soft = events->interrupt.soft;
2144 if (vcpu->arch.interrupt.pending && irqchip_in_kernel(vcpu->kvm))
2145 kvm_pic_clear_isr_ack(vcpu->kvm);
2146
2147 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2148 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2149 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2150 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2151
dab4b911
JK		 2152 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR)
2153 vcpu->arch.sipi_vector = events->sipi_vector;
3cfc3092
JK		 2154
2155 vcpu_put(vcpu);
2156
2157 return 0;
2158}
2159
313a3dc7
CO		 2160long kvm_arch_vcpu_ioctl(struct file *filp,
2161 unsigned int ioctl, unsigned long arg)
2162{
2163 struct kvm_vcpu *vcpu = filp->private_data;
2164 void __user *argp = (void __user *)arg;
2165 int r;
b772ff36 2166 struct kvm_lapic_state *lapic = NULL;
313a3dc7
CO		 2167
2168 switch (ioctl) {
2169 case KVM_GET_LAPIC: {
2204ae3c
MT		 2170 r = -EINVAL;
2171 if (!vcpu->arch.apic)
2172 goto out;
b772ff36 2173 lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 2174
b772ff36
DH		 2175 r = -ENOMEM;
2176 if (!lapic)
2177 goto out;
2178 r = kvm_vcpu_ioctl_get_lapic(vcpu, lapic);
313a3dc7
CO		 2179 if (r)
2180 goto out;
2181 r = -EFAULT;
b772ff36 2182 if (copy_to_user(argp, lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 2183 goto out;
2184 r = 0;
2185 break;
2186 }
2187 case KVM_SET_LAPIC: {
2204ae3c
MT		 2188 r = -EINVAL;
2189 if (!vcpu->arch.apic)
2190 goto out;
b772ff36
DH		 2191 lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
2192 r = -ENOMEM;
2193 if (!lapic)
2194 goto out;
313a3dc7 2195 r = -EFAULT;
b772ff36 2196 if (copy_from_user(lapic, argp, sizeof(struct kvm_lapic_state)))
313a3dc7 2197 goto out;
b772ff36 2198 r = kvm_vcpu_ioctl_set_lapic(vcpu, lapic);
313a3dc7
CO		 2199 if (r)
2200 goto out;
2201 r = 0;
2202 break;
2203 }
f77bc6a4
ZX		 2204 case KVM_INTERRUPT: {
2205 struct kvm_interrupt irq;
2206
2207 r = -EFAULT;
2208 if (copy_from_user(&irq, argp, sizeof irq))
2209 goto out;
2210 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
2211 if (r)
2212 goto out;
2213 r = 0;
2214 break;
2215 }
c4abb7c9
JK		 2216 case KVM_NMI: {
2217 r = kvm_vcpu_ioctl_nmi(vcpu);
2218 if (r)
2219 goto out;
2220 r = 0;
2221 break;
2222 }
313a3dc7
CO		 2223 case KVM_SET_CPUID: {
2224 struct kvm_cpuid __user *cpuid_arg = argp;
2225 struct kvm_cpuid cpuid;
2226
2227 r = -EFAULT;
2228 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2229 goto out;
2230 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
2231 if (r)
2232 goto out;
2233 break;
2234 }
07716717
DK		 2235 case KVM_SET_CPUID2: {
2236 struct kvm_cpuid2 __user *cpuid_arg = argp;
2237 struct kvm_cpuid2 cpuid;
2238
2239 r = -EFAULT;
2240 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2241 goto out;
2242 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 2243 cpuid_arg->entries);
07716717
DK		 2244 if (r)
2245 goto out;
2246 break;
2247 }
2248 case KVM_GET_CPUID2: {
2249 struct kvm_cpuid2 __user *cpuid_arg = argp;
2250 struct kvm_cpuid2 cpuid;
2251
2252 r = -EFAULT;
2253 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2254 goto out;
2255 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 2256 cpuid_arg->entries);
07716717
DK		 2257 if (r)
2258 goto out;
2259 r = -EFAULT;
2260 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2261 goto out;
2262 r = 0;
2263 break;
2264 }
313a3dc7
CO		 2265 case KVM_GET_MSRS:
2266 r = msr_io(vcpu, argp, kvm_get_msr, 1);
2267 break;
2268 case KVM_SET_MSRS:
2269 r = msr_io(vcpu, argp, do_set_msr, 0);
2270 break;
b209749f
AK		 2271 case KVM_TPR_ACCESS_REPORTING: {
2272 struct kvm_tpr_access_ctl tac;
2273
2274 r = -EFAULT;
2275 if (copy_from_user(&tac, argp, sizeof tac))
2276 goto out;
2277 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
2278 if (r)
2279 goto out;
2280 r = -EFAULT;
2281 if (copy_to_user(argp, &tac, sizeof tac))
2282 goto out;
2283 r = 0;
2284 break;
2285 };
b93463aa
AK		 2286 case KVM_SET_VAPIC_ADDR: {
2287 struct kvm_vapic_addr va;
2288
2289 r = -EINVAL;
2290 if (!irqchip_in_kernel(vcpu->kvm))
2291 goto out;
2292 r = -EFAULT;
2293 if (copy_from_user(&va, argp, sizeof va))
2294 goto out;
2295 r = 0;
2296 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
2297 break;
2298 }
890ca9ae
HY		 2299 case KVM_X86_SETUP_MCE: {
2300 u64 mcg_cap;
2301
2302 r = -EFAULT;
2303 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
2304 goto out;
2305 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
2306 break;
2307 }
2308 case KVM_X86_SET_MCE: {
2309 struct kvm_x86_mce mce;
2310
2311 r = -EFAULT;
2312 if (copy_from_user(&mce, argp, sizeof mce))
2313 goto out;
2314 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
2315 break;
2316 }
3cfc3092
JK		 2317 case KVM_GET_VCPU_EVENTS: {
2318 struct kvm_vcpu_events events;
2319
2320 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
2321
2322 r = -EFAULT;
2323 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
2324 break;
2325 r = 0;
2326 break;
2327 }
2328 case KVM_SET_VCPU_EVENTS: {
2329 struct kvm_vcpu_events events;
2330
2331 r = -EFAULT;
2332 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
2333 break;
2334
2335 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
2336 break;
2337 }
313a3dc7
CO		 2338 default:
2339 r = -EINVAL;
2340 }
2341out:
7a6ce84c 2342 kfree(lapic);
313a3dc7
CO		 2343 return r;
2344}
2345
1fe779f8
CO		 2346static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
2347{
2348 int ret;
2349
2350 if (addr > (unsigned int)(-3 * PAGE_SIZE))
2351 return -1;
2352 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
2353 return ret;
2354}
2355
b927a3ce
SY		 2356static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
2357 u64 ident_addr)
2358{
2359 kvm->arch.ept_identity_map_addr = ident_addr;
2360 return 0;
2361}
2362
1fe779f8
CO		 2363static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
2364 u32 kvm_nr_mmu_pages)
2365{
2366 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
2367 return -EINVAL;
2368
79fac95e 2369 mutex_lock(&kvm->slots_lock);
7c8a83b7 2370 spin_lock(&kvm->mmu_lock);
1fe779f8
CO		 2371
2372 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 2373 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 2374
7c8a83b7 2375 spin_unlock(&kvm->mmu_lock);
79fac95e 2376 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 2377 return 0;
2378}
2379
2380static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
2381{
f05e70ac 2382 return kvm->arch.n_alloc_mmu_pages;
1fe779f8
CO		 2383}
2384
a983fb23
MT		 2385gfn_t unalias_gfn_instantiation(struct kvm *kvm, gfn_t gfn)
2386{
2387 int i;
2388 struct kvm_mem_alias *alias;
2389 struct kvm_mem_aliases *aliases;
2390
2391 aliases = rcu_dereference(kvm->arch.aliases);
2392
2393 for (i = 0; i < aliases->naliases; ++i) {
2394 alias = &aliases->aliases[i];
2395 if (alias->flags & KVM_ALIAS_INVALID)
2396 continue;
2397 if (gfn >= alias->base_gfn
2398 && gfn < alias->base_gfn + alias->npages)
2399 return alias->target_gfn + gfn - alias->base_gfn;
2400 }
2401 return gfn;
2402}
2403
e9f85cde
ZX		 2404gfn_t unalias_gfn(struct kvm *kvm, gfn_t gfn)
2405{
2406 int i;
2407 struct kvm_mem_alias *alias;
a983fb23
MT		 2408 struct kvm_mem_aliases *aliases;
2409
2410 aliases = rcu_dereference(kvm->arch.aliases);
e9f85cde 2411
fef9cce0
MT		 2412 for (i = 0; i < aliases->naliases; ++i) {
2413 alias = &aliases->aliases[i];
e9f85cde
ZX		 2414 if (gfn >= alias->base_gfn
2415 && gfn < alias->base_gfn + alias->npages)
2416 return alias->target_gfn + gfn - alias->base_gfn;
2417 }
2418 return gfn;
2419}
2420
1fe779f8
CO		 2421/*
2422 * Set a new alias region. Aliases map a portion of physical memory into
2423 * another portion. This is useful for memory windows, for example the PC
2424 * VGA region.
2425 */
2426static int kvm_vm_ioctl_set_memory_alias(struct kvm *kvm,
2427 struct kvm_memory_alias *alias)
2428{
2429 int r, n;
2430 struct kvm_mem_alias *p;
a983fb23 2431 struct kvm_mem_aliases *aliases, *old_aliases;
1fe779f8
CO		 2432
2433 r = -EINVAL;
2434 /* General sanity checks */
2435 if (alias->memory_size & (PAGE_SIZE - 1))
2436 goto out;
2437 if (alias->guest_phys_addr & (PAGE_SIZE - 1))
2438 goto out;
2439 if (alias->slot >= KVM_ALIAS_SLOTS)
2440 goto out;
2441 if (alias->guest_phys_addr + alias->memory_size
2442 < alias->guest_phys_addr)
2443 goto out;
2444 if (alias->target_phys_addr + alias->memory_size
2445 < alias->target_phys_addr)
2446 goto out;
2447
a983fb23
MT		 2448 r = -ENOMEM;
2449 aliases = kzalloc(sizeof(struct kvm_mem_aliases), GFP_KERNEL);
2450 if (!aliases)
2451 goto out;
2452
79fac95e 2453 mutex_lock(&kvm->slots_lock);
1fe779f8 2454
a983fb23
MT		 2455 /* invalidate any gfn reference in case of deletion/shrinking */
2456 memcpy(aliases, kvm->arch.aliases, sizeof(struct kvm_mem_aliases));
2457 aliases->aliases[alias->slot].flags |= KVM_ALIAS_INVALID;
2458 old_aliases = kvm->arch.aliases;
2459 rcu_assign_pointer(kvm->arch.aliases, aliases);
2460 synchronize_srcu_expedited(&kvm->srcu);
2461 kvm_mmu_zap_all(kvm);
2462 kfree(old_aliases);
2463
2464 r = -ENOMEM;
2465 aliases = kzalloc(sizeof(struct kvm_mem_aliases), GFP_KERNEL);
2466 if (!aliases)
2467 goto out_unlock;
2468
2469 memcpy(aliases, kvm->arch.aliases, sizeof(struct kvm_mem_aliases));
fef9cce0
MT		 2470
2471 p = &aliases->aliases[alias->slot];
1fe779f8
CO		 2472 p->base_gfn = alias->guest_phys_addr >> PAGE_SHIFT;
2473 p->npages = alias->memory_size >> PAGE_SHIFT;
2474 p->target_gfn = alias->target_phys_addr >> PAGE_SHIFT;
a983fb23 2475 p->flags &= ~(KVM_ALIAS_INVALID);
1fe779f8
CO		 2476
2477 for (n = KVM_ALIAS_SLOTS; n > 0; --n)
fef9cce0 2478 if (aliases->aliases[n - 1].npages)
1fe779f8 2479 break;
fef9cce0 2480 aliases->naliases = n;
1fe779f8 2481
a983fb23
MT		 2482 old_aliases = kvm->arch.aliases;
2483 rcu_assign_pointer(kvm->arch.aliases, aliases);
2484 synchronize_srcu_expedited(&kvm->srcu);
2485 kfree(old_aliases);
2486 r = 0;
1fe779f8 2487
a983fb23 2488out_unlock:
79fac95e 2489 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 2490out:
2491 return r;
2492}
2493
2494static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2495{
2496 int r;
2497
2498 r = 0;
2499 switch (chip->chip_id) {
2500 case KVM_IRQCHIP_PIC_MASTER:
2501 memcpy(&chip->chip.pic,
2502 &pic_irqchip(kvm)->pics[0],
2503 sizeof(struct kvm_pic_state));
2504 break;
2505 case KVM_IRQCHIP_PIC_SLAVE:
2506 memcpy(&chip->chip.pic,
2507 &pic_irqchip(kvm)->pics[1],
2508 sizeof(struct kvm_pic_state));
2509 break;
2510 case KVM_IRQCHIP_IOAPIC:
eba0226b 2511 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 2512 break;
2513 default:
2514 r = -EINVAL;
2515 break;
2516 }
2517 return r;
2518}
2519
2520static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2521{
2522 int r;
2523
2524 r = 0;
2525 switch (chip->chip_id) {
2526 case KVM_IRQCHIP_PIC_MASTER:
fa8273e9 2527 raw_spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2528 memcpy(&pic_irqchip(kvm)->pics[0],
2529 &chip->chip.pic,
2530 sizeof(struct kvm_pic_state));
fa8273e9 2531 raw_spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2532 break;
2533 case KVM_IRQCHIP_PIC_SLAVE:
fa8273e9 2534 raw_spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2535 memcpy(&pic_irqchip(kvm)->pics[1],
2536 &chip->chip.pic,
2537 sizeof(struct kvm_pic_state));
fa8273e9 2538 raw_spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2539 break;
2540 case KVM_IRQCHIP_IOAPIC:
eba0226b 2541 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 2542 break;
2543 default:
2544 r = -EINVAL;
2545 break;
2546 }
2547 kvm_pic_update_irq(pic_irqchip(kvm));
2548 return r;
2549}
2550
e0f63cb9
SY		 2551static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2552{
2553 int r = 0;
2554
894a9c55 2555 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 2556 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 2557 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 2558 return r;
2559}
2560
2561static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2562{
2563 int r = 0;
2564
894a9c55 2565 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 2566 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 2567 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
2568 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2569 return r;
2570}
2571
2572static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
2573{
2574 int r = 0;
2575
2576 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2577 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
2578 sizeof(ps->channels));
2579 ps->flags = kvm->arch.vpit->pit_state.flags;
2580 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2581 return r;
2582}
2583
2584static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
2585{
2586 int r = 0, start = 0;
2587 u32 prev_legacy, cur_legacy;
2588 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2589 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
2590 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
2591 if (!prev_legacy && cur_legacy)
2592 start = 1;
2593 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
2594 sizeof(kvm->arch.vpit->pit_state.channels));
2595 kvm->arch.vpit->pit_state.flags = ps->flags;
2596 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 2597 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 2598 return r;
2599}
2600
52d939a0
MT		 2601static int kvm_vm_ioctl_reinject(struct kvm *kvm,
2602 struct kvm_reinject_control *control)
2603{
2604 if (!kvm->arch.vpit)
2605 return -ENXIO;
894a9c55 2606 mutex_lock(&kvm->arch.vpit->pit_state.lock);
52d939a0 2607 kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject;
894a9c55 2608 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 2609 return 0;
2610}
2611
5bb064dc
ZX		 2612/*
2613 * Get (and clear) the dirty memory log for a memory slot.
2614 */
2615int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
2616 struct kvm_dirty_log *log)
2617{
87bf6e7d 2618 int r, i;
5bb064dc 2619 struct kvm_memory_slot *memslot;
87bf6e7d 2620 unsigned long n;
b050b015
MT		 2621 unsigned long is_dirty = 0;
2622 unsigned long *dirty_bitmap = NULL;
5bb064dc 2623
79fac95e 2624 mutex_lock(&kvm->slots_lock);
5bb064dc 2625
b050b015
MT		 2626 r = -EINVAL;
2627 if (log->slot >= KVM_MEMORY_SLOTS)
2628 goto out;
2629
2630 memslot = &kvm->memslots->memslots[log->slot];
2631 r = -ENOENT;
2632 if (!memslot->dirty_bitmap)
2633 goto out;
2634
87bf6e7d 2635 n = kvm_dirty_bitmap_bytes(memslot);
b050b015
MT		 2636
2637 r = -ENOMEM;
2638 dirty_bitmap = vmalloc(n);
2639 if (!dirty_bitmap)
5bb064dc 2640 goto out;
b050b015
MT		 2641 memset(dirty_bitmap, 0, n);
2642
2643 for (i = 0; !is_dirty && i < n/sizeof(long); i++)
2644 is_dirty = memslot->dirty_bitmap[i];
5bb064dc
ZX		 2645
2646 /* If nothing is dirty, don't bother messing with page tables. */
2647 if (is_dirty) {
b050b015
MT		 2648 struct kvm_memslots *slots, *old_slots;
2649
7c8a83b7 2650 spin_lock(&kvm->mmu_lock);
5bb064dc 2651 kvm_mmu_slot_remove_write_access(kvm, log->slot);
7c8a83b7 2652 spin_unlock(&kvm->mmu_lock);
b050b015
MT		 2653
2654 slots = kzalloc(sizeof(struct kvm_memslots), GFP_KERNEL);
2655 if (!slots)
2656 goto out_free;
2657
2658 memcpy(slots, kvm->memslots, sizeof(struct kvm_memslots));
2659 slots->memslots[log->slot].dirty_bitmap = dirty_bitmap;
2660
2661 old_slots = kvm->memslots;
2662 rcu_assign_pointer(kvm->memslots, slots);
2663 synchronize_srcu_expedited(&kvm->srcu);
2664 dirty_bitmap = old_slots->memslots[log->slot].dirty_bitmap;
2665 kfree(old_slots);
5bb064dc 2666 }
b050b015 2667
5bb064dc 2668 r = 0;
b050b015
MT		 2669 if (copy_to_user(log->dirty_bitmap, dirty_bitmap, n))
2670 r = -EFAULT;
2671out_free:
2672 vfree(dirty_bitmap);
5bb064dc 2673out:
79fac95e 2674 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 2675 return r;
2676}
2677
1fe779f8
CO		 2678long kvm_arch_vm_ioctl(struct file *filp,
2679 unsigned int ioctl, unsigned long arg)
2680{
2681 struct kvm *kvm = filp->private_data;
2682 void __user *argp = (void __user *)arg;
367e1319 2683 int r = -ENOTTY;
f0d66275
DH		 2684 /*
2685 * This union makes it completely explicit to gcc-3.x
2686 * that these two variables' stack usage should be
2687 * combined, not added together.
2688 */
2689 union {
2690 struct kvm_pit_state ps;
e9f42757 2691 struct kvm_pit_state2 ps2;
f0d66275 2692 struct kvm_memory_alias alias;
c5ff41ce 2693 struct kvm_pit_config pit_config;
f0d66275 2694 } u;
1fe779f8
CO		 2695
2696 switch (ioctl) {
2697 case KVM_SET_TSS_ADDR:
2698 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
2699 if (r < 0)
2700 goto out;
2701 break;
b927a3ce
SY		 2702 case KVM_SET_IDENTITY_MAP_ADDR: {
2703 u64 ident_addr;
2704
2705 r = -EFAULT;
2706 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
2707 goto out;
2708 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
2709 if (r < 0)
2710 goto out;
2711 break;
2712 }
1fe779f8
CO		 2713 case KVM_SET_MEMORY_REGION: {
2714 struct kvm_memory_region kvm_mem;
2715 struct kvm_userspace_memory_region kvm_userspace_mem;
2716
2717 r = -EFAULT;
2718 if (copy_from_user(&kvm_mem, argp, sizeof kvm_mem))
2719 goto out;
2720 kvm_userspace_mem.slot = kvm_mem.slot;
2721 kvm_userspace_mem.flags = kvm_mem.flags;
2722 kvm_userspace_mem.guest_phys_addr = kvm_mem.guest_phys_addr;
2723 kvm_userspace_mem.memory_size = kvm_mem.memory_size;
2724 r = kvm_vm_ioctl_set_memory_region(kvm, &kvm_userspace_mem, 0);
2725 if (r)
2726 goto out;
2727 break;
2728 }
2729 case KVM_SET_NR_MMU_PAGES:
2730 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
2731 if (r)
2732 goto out;
2733 break;
2734 case KVM_GET_NR_MMU_PAGES:
2735 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
2736 break;
f0d66275 2737 case KVM_SET_MEMORY_ALIAS:
1fe779f8 2738 r = -EFAULT;
f0d66275 2739 if (copy_from_user(&u.alias, argp, sizeof(struct kvm_memory_alias)))
1fe779f8 2740 goto out;
f0d66275 2741 r = kvm_vm_ioctl_set_memory_alias(kvm, &u.alias);
1fe779f8
CO		 2742 if (r)
2743 goto out;
2744 break;
3ddea128
MT		 2745 case KVM_CREATE_IRQCHIP: {
2746 struct kvm_pic *vpic;
2747
2748 mutex_lock(&kvm->lock);
2749 r = -EEXIST;
2750 if (kvm->arch.vpic)
2751 goto create_irqchip_unlock;
1fe779f8 2752 r = -ENOMEM;
3ddea128
MT		 2753 vpic = kvm_create_pic(kvm);
2754 if (vpic) {
1fe779f8
CO		 2755 r = kvm_ioapic_init(kvm);
2756 if (r) {
72bb2fcd
WY		 2757 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
2758 &vpic->dev);
3ddea128
MT		 2759 kfree(vpic);
2760 goto create_irqchip_unlock;
1fe779f8
CO		 2761 }
2762 } else
3ddea128
MT		 2763 goto create_irqchip_unlock;
2764 smp_wmb();
2765 kvm->arch.vpic = vpic;
2766 smp_wmb();
399ec807
AK		 2767 r = kvm_setup_default_irq_routing(kvm);
2768 if (r) {
3ddea128 2769 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 2770 kvm_ioapic_destroy(kvm);
2771 kvm_destroy_pic(kvm);
3ddea128 2772 mutex_unlock(&kvm->irq_lock);
399ec807 2773 }
3ddea128
MT		 2774 create_irqchip_unlock:
2775 mutex_unlock(&kvm->lock);
1fe779f8 2776 break;
3ddea128 2777 }
7837699f 2778 case KVM_CREATE_PIT:
c5ff41ce
JK		 2779 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
2780 goto create_pit;
2781 case KVM_CREATE_PIT2:
2782 r = -EFAULT;
2783 if (copy_from_user(&u.pit_config, argp,
2784 sizeof(struct kvm_pit_config)))
2785 goto out;
2786 create_pit:
79fac95e 2787 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 2788 r = -EEXIST;
2789 if (kvm->arch.vpit)
2790 goto create_pit_unlock;
7837699f 2791 r = -ENOMEM;
c5ff41ce 2792 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 2793 if (kvm->arch.vpit)
2794 r = 0;
269e05e4 2795 create_pit_unlock:
79fac95e 2796 mutex_unlock(&kvm->slots_lock);
7837699f 2797 break;
4925663a 2798 case KVM_IRQ_LINE_STATUS:
1fe779f8
CO		 2799 case KVM_IRQ_LINE: {
2800 struct kvm_irq_level irq_event;
2801
2802 r = -EFAULT;
2803 if (copy_from_user(&irq_event, argp, sizeof irq_event))
2804 goto out;
2805 if (irqchip_in_kernel(kvm)) {
4925663a 2806 __s32 status;
4925663a
GN		 2807 status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
2808 irq_event.irq, irq_event.level);
4925663a
GN		 2809 if (ioctl == KVM_IRQ_LINE_STATUS) {
2810 irq_event.status = status;
2811 if (copy_to_user(argp, &irq_event,
2812 sizeof irq_event))
2813 goto out;
2814 }
1fe779f8
CO		 2815 r = 0;
2816 }
2817 break;
2818 }
2819 case KVM_GET_IRQCHIP: {
2820 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 2821 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 2822
f0d66275
DH		 2823 r = -ENOMEM;
2824 if (!chip)
1fe779f8 2825 goto out;
f0d66275
DH		 2826 r = -EFAULT;
2827 if (copy_from_user(chip, argp, sizeof *chip))
2828 goto get_irqchip_out;
1fe779f8
CO		 2829 r = -ENXIO;
2830 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 2831 goto get_irqchip_out;
2832 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 2833 if (r)
f0d66275 2834 goto get_irqchip_out;
1fe779f8 2835 r = -EFAULT;
f0d66275
DH		 2836 if (copy_to_user(argp, chip, sizeof *chip))
2837 goto get_irqchip_out;
1fe779f8 2838 r = 0;
f0d66275
DH		 2839 get_irqchip_out:
2840 kfree(chip);
2841 if (r)
2842 goto out;
1fe779f8
CO		 2843 break;
2844 }
2845 case KVM_SET_IRQCHIP: {
2846 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 2847 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 2848
f0d66275
DH		 2849 r = -ENOMEM;
2850 if (!chip)
1fe779f8 2851 goto out;
f0d66275
DH		 2852 r = -EFAULT;
2853 if (copy_from_user(chip, argp, sizeof *chip))
2854 goto set_irqchip_out;
1fe779f8
CO		 2855 r = -ENXIO;
2856 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 2857 goto set_irqchip_out;
2858 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 2859 if (r)
f0d66275 2860 goto set_irqchip_out;
1fe779f8 2861 r = 0;
f0d66275
DH		 2862 set_irqchip_out:
2863 kfree(chip);
2864 if (r)
2865 goto out;
1fe779f8
CO		 2866 break;
2867 }
e0f63cb9 2868 case KVM_GET_PIT: {
e0f63cb9 2869 r = -EFAULT;
f0d66275 2870 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 2871 goto out;
2872 r = -ENXIO;
2873 if (!kvm->arch.vpit)
2874 goto out;
f0d66275 2875 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 2876 if (r)
2877 goto out;
2878 r = -EFAULT;
f0d66275 2879 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 2880 goto out;
2881 r = 0;
2882 break;
2883 }
2884 case KVM_SET_PIT: {
e0f63cb9 2885 r = -EFAULT;
f0d66275 2886 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 2887 goto out;
2888 r = -ENXIO;
2889 if (!kvm->arch.vpit)
2890 goto out;
f0d66275 2891 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 2892 if (r)
2893 goto out;
2894 r = 0;
2895 break;
2896 }
e9f42757
BK		 2897 case KVM_GET_PIT2: {
2898 r = -ENXIO;
2899 if (!kvm->arch.vpit)
2900 goto out;
2901 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
2902 if (r)
2903 goto out;
2904 r = -EFAULT;
2905 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
2906 goto out;
2907 r = 0;
2908 break;
2909 }
2910 case KVM_SET_PIT2: {
2911 r = -EFAULT;
2912 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
2913 goto out;
2914 r = -ENXIO;
2915 if (!kvm->arch.vpit)
2916 goto out;
2917 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
2918 if (r)
2919 goto out;
2920 r = 0;
2921 break;
2922 }
52d939a0
MT		 2923 case KVM_REINJECT_CONTROL: {
2924 struct kvm_reinject_control control;
2925 r = -EFAULT;
2926 if (copy_from_user(&control, argp, sizeof(control)))
2927 goto out;
2928 r = kvm_vm_ioctl_reinject(kvm, &control);
2929 if (r)
2930 goto out;
2931 r = 0;
2932 break;
2933 }
ffde22ac
ES		 2934 case KVM_XEN_HVM_CONFIG: {
2935 r = -EFAULT;
2936 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
2937 sizeof(struct kvm_xen_hvm_config)))
2938 goto out;
2939 r = -EINVAL;
2940 if (kvm->arch.xen_hvm_config.flags)
2941 goto out;
2942 r = 0;
2943 break;
2944 }
afbcf7ab
GC		 2945 case KVM_SET_CLOCK: {
2946 struct timespec now;
2947 struct kvm_clock_data user_ns;
2948 u64 now_ns;
2949 s64 delta;
2950
2951 r = -EFAULT;
2952 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
2953 goto out;
2954
2955 r = -EINVAL;
2956 if (user_ns.flags)
2957 goto out;
2958
2959 r = 0;
2960 ktime_get_ts(&now);
2961 now_ns = timespec_to_ns(&now);
2962 delta = user_ns.clock - now_ns;
2963 kvm->arch.kvmclock_offset = delta;
2964 break;
2965 }
2966 case KVM_GET_CLOCK: {
2967 struct timespec now;
2968 struct kvm_clock_data user_ns;
2969 u64 now_ns;
2970
2971 ktime_get_ts(&now);
2972 now_ns = timespec_to_ns(&now);
2973 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
2974 user_ns.flags = 0;
2975
2976 r = -EFAULT;
2977 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
2978 goto out;
2979 r = 0;
2980 break;
2981 }
2982
1fe779f8
CO		 2983 default:
2984 ;
2985 }
2986out:
2987 return r;
2988}
2989
a16b043c 2990static void kvm_init_msr_list(void)
043405e1
CO		 2991{
2992 u32 dummy[2];
2993 unsigned i, j;
2994
e3267cbb
GC		 2995 /* skip the first msrs in the list. KVM-specific */
2996 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 2997 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
2998 continue;
2999 if (j < i)
3000 msrs_to_save[j] = msrs_to_save[i];
3001 j++;
3002 }
3003 num_msrs_to_save = j;
3004}
3005
bda9020e
MT		 3006static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3007 const void *v)
bbd9b64e 3008{
bda9020e
MT		 3009 if (vcpu->arch.apic &&
3010 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, len, v))
3011 return 0;
bbd9b64e 3012
e93f8a0f 3013 return kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, len, v);
bbd9b64e
CO		 3014}
3015
bda9020e 3016static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 3017{
bda9020e
MT		 3018 if (vcpu->arch.apic &&
3019 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, len, v))
3020 return 0;
bbd9b64e 3021
e93f8a0f 3022 return kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, len, v);
bbd9b64e
CO		 3023}
3024
1871c602
GN		 3025gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3026{
3027 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3028 return vcpu->arch.mmu.gva_to_gpa(vcpu, gva, access, error);
3029}
3030
3031 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3032{
3033 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3034 access |= PFERR_FETCH_MASK;
3035 return vcpu->arch.mmu.gva_to_gpa(vcpu, gva, access, error);
3036}
3037
3038gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3039{
3040 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3041 access |= PFERR_WRITE_MASK;
3042 return vcpu->arch.mmu.gva_to_gpa(vcpu, gva, access, error);
3043}
3044
3045/* uses this to access any guest's mapped memory without checking CPL */
3046gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3047{
3048 return vcpu->arch.mmu.gva_to_gpa(vcpu, gva, 0, error);
3049}
3050
3051static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3052 struct kvm_vcpu *vcpu, u32 access,
3053 u32 *error)
bbd9b64e
CO		 3054{
3055 void *data = val;
10589a46 3056 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 3057
3058 while (bytes) {
1871c602 3059 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr, access, error);
bbd9b64e 3060 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 3061 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 3062 int ret;
3063
10589a46
MT		 3064 if (gpa == UNMAPPED_GVA) {
3065 r = X86EMUL_PROPAGATE_FAULT;
3066 goto out;
3067 }
77c2002e 3068 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46
MT		 3069 if (ret < 0) {
3070 r = X86EMUL_UNHANDLEABLE;
3071 goto out;
3072 }
bbd9b64e 3073
77c2002e
IE		 3074 bytes -= toread;
3075 data += toread;
3076 addr += toread;
bbd9b64e 3077 }
10589a46 3078out:
10589a46 3079 return r;
bbd9b64e 3080}
77c2002e 3081
1871c602
GN		 3082/* used for instruction fetching */
3083static int kvm_fetch_guest_virt(gva_t addr, void *val, unsigned int bytes,
3084 struct kvm_vcpu *vcpu, u32 *error)
3085{
3086 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3087 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
3088 access | PFERR_FETCH_MASK, error);
3089}
3090
3091static int kvm_read_guest_virt(gva_t addr, void *val, unsigned int bytes,
3092 struct kvm_vcpu *vcpu, u32 *error)
3093{
3094 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3095 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
3096 error);
3097}
3098
3099static int kvm_read_guest_virt_system(gva_t addr, void *val, unsigned int bytes,
3100 struct kvm_vcpu *vcpu, u32 *error)
3101{
3102 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, error);
3103}
3104
cded19f3 3105static int kvm_write_guest_virt(gva_t addr, void *val, unsigned int bytes,
1871c602 3106 struct kvm_vcpu *vcpu, u32 *error)
77c2002e
IE		 3107{
3108 void *data = val;
3109 int r = X86EMUL_CONTINUE;
3110
3111 while (bytes) {
1871c602 3112 gpa_t gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, error);
77c2002e
IE		 3113 unsigned offset = addr & (PAGE_SIZE-1);
3114 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
3115 int ret;
3116
3117 if (gpa == UNMAPPED_GVA) {
3118 r = X86EMUL_PROPAGATE_FAULT;
3119 goto out;
3120 }
3121 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
3122 if (ret < 0) {
3123 r = X86EMUL_UNHANDLEABLE;
3124 goto out;
3125 }
3126
3127 bytes -= towrite;
3128 data += towrite;
3129 addr += towrite;
3130 }
3131out:
3132 return r;
3133}
3134
bbd9b64e 3135
bbd9b64e
CO		 3136static int emulator_read_emulated(unsigned long addr,
3137 void *val,
3138 unsigned int bytes,
3139 struct kvm_vcpu *vcpu)
3140{
bbd9b64e 3141 gpa_t gpa;
1871c602 3142 u32 error_code;
bbd9b64e
CO		 3143
3144 if (vcpu->mmio_read_completed) {
3145 memcpy(val, vcpu->mmio_data, bytes);
aec51dc4
AK		 3146 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
3147 vcpu->mmio_phys_addr, *(u64 *)val);
bbd9b64e
CO		 3148 vcpu->mmio_read_completed = 0;
3149 return X86EMUL_CONTINUE;
3150 }
3151
1871c602
GN		 3152 gpa = kvm_mmu_gva_to_gpa_read(vcpu, addr, &error_code);
3153
3154 if (gpa == UNMAPPED_GVA) {
3155 kvm_inject_page_fault(vcpu, addr, error_code);
3156 return X86EMUL_PROPAGATE_FAULT;
3157 }
bbd9b64e
CO		 3158
3159 /* For APIC access vmexit */
3160 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3161 goto mmio;
3162
1871c602 3163 if (kvm_read_guest_virt(addr, val, bytes, vcpu, NULL)
77c2002e 3164 == X86EMUL_CONTINUE)
bbd9b64e 3165 return X86EMUL_CONTINUE;
bbd9b64e
CO		 3166
3167mmio:
3168 /*
3169 * Is this MMIO handled locally?
3170 */
aec51dc4
AK		 3171 if (!vcpu_mmio_read(vcpu, gpa, bytes, val)) {
3172 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 3173 return X86EMUL_CONTINUE;
3174 }
aec51dc4
AK		 3175
3176 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
bbd9b64e
CO		 3177
3178 vcpu->mmio_needed = 1;
3179 vcpu->mmio_phys_addr = gpa;
3180 vcpu->mmio_size = bytes;
3181 vcpu->mmio_is_write = 0;
3182
3183 return X86EMUL_UNHANDLEABLE;
3184}
3185
3200f405 3186int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
9f811285 3187 const void *val, int bytes)
bbd9b64e
CO		 3188{
3189 int ret;
3190
3191 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 3192 if (ret < 0)
bbd9b64e 3193 return 0;
ad218f85 3194 kvm_mmu_pte_write(vcpu, gpa, val, bytes, 1);
bbd9b64e
CO		 3195 return 1;
3196}
3197
3198static int emulator_write_emulated_onepage(unsigned long addr,
3199 const void *val,
3200 unsigned int bytes,
3201 struct kvm_vcpu *vcpu)
3202{
10589a46 3203 gpa_t gpa;
1871c602 3204 u32 error_code;
10589a46 3205
1871c602 3206 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, &error_code);
bbd9b64e
CO		 3207
3208 if (gpa == UNMAPPED_GVA) {
1871c602 3209 kvm_inject_page_fault(vcpu, addr, error_code);
bbd9b64e
CO		 3210 return X86EMUL_PROPAGATE_FAULT;
3211 }
3212
3213 /* For APIC access vmexit */
3214 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3215 goto mmio;
3216
3217 if (emulator_write_phys(vcpu, gpa, val, bytes))
3218 return X86EMUL_CONTINUE;
3219
3220mmio:
aec51dc4 3221 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 3222 /*
3223 * Is this MMIO handled locally?
3224 */
bda9020e 3225 if (!vcpu_mmio_write(vcpu, gpa, bytes, val))
bbd9b64e 3226 return X86EMUL_CONTINUE;
bbd9b64e
CO		 3227
3228 vcpu->mmio_needed = 1;
3229 vcpu->mmio_phys_addr = gpa;
3230 vcpu->mmio_size = bytes;
3231 vcpu->mmio_is_write = 1;
3232 memcpy(vcpu->mmio_data, val, bytes);
3233
3234 return X86EMUL_CONTINUE;
3235}
3236
3237int emulator_write_emulated(unsigned long addr,
3238 const void *val,
3239 unsigned int bytes,
3240 struct kvm_vcpu *vcpu)
3241{
3242 /* Crossing a page boundary? */
3243 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
3244 int rc, now;
3245
3246 now = -addr & ~PAGE_MASK;
3247 rc = emulator_write_emulated_onepage(addr, val, now, vcpu);
3248 if (rc != X86EMUL_CONTINUE)
3249 return rc;
3250 addr += now;
3251 val += now;
3252 bytes -= now;
3253 }
3254 return emulator_write_emulated_onepage(addr, val, bytes, vcpu);
3255}
3256EXPORT_SYMBOL_GPL(emulator_write_emulated);
3257
3258static int emulator_cmpxchg_emulated(unsigned long addr,
3259 const void *old,
3260 const void *new,
3261 unsigned int bytes,
3262 struct kvm_vcpu *vcpu)
3263{
9f51e24e 3264 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c
MT		 3265#ifndef CONFIG_X86_64
3266 /* guests cmpxchg8b have to be emulated atomically */
3267 if (bytes == 8) {
10589a46 3268 gpa_t gpa;
2bacc55c 3269 struct page *page;
c0b49b0d 3270 char *kaddr;
2bacc55c
MT		 3271 u64 val;
3272
1871c602 3273 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
10589a46 3274
2bacc55c
MT		 3275 if (gpa == UNMAPPED_GVA ||
3276 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3277 goto emul_write;
3278
3279 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
3280 goto emul_write;
3281
3282 val = *(u64 *)new;
72dc67a6 3283
2bacc55c 3284 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
72dc67a6 3285
c0b49b0d
AM		 3286 kaddr = kmap_atomic(page, KM_USER0);
3287 set_64bit((u64 *)(kaddr + offset_in_page(gpa)), val);
3288 kunmap_atomic(kaddr, KM_USER0);
2bacc55c
MT		 3289 kvm_release_page_dirty(page);
3290 }
3200f405 3291emul_write:
2bacc55c
MT		 3292#endif
3293
bbd9b64e
CO		 3294 return emulator_write_emulated(addr, new, bytes, vcpu);
3295}
3296
3297static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
3298{
3299 return kvm_x86_ops->get_segment_base(vcpu, seg);
3300}
3301
3302int emulate_invlpg(struct kvm_vcpu *vcpu, gva_t address)
3303{
a7052897 3304 kvm_mmu_invlpg(vcpu, address);
bbd9b64e
CO		 3305 return X86EMUL_CONTINUE;
3306}
3307
3308int emulate_clts(struct kvm_vcpu *vcpu)
3309{
4d4ec087 3310 kvm_x86_ops->set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
6b52d186 3311 kvm_x86_ops->fpu_activate(vcpu);
bbd9b64e
CO		 3312 return X86EMUL_CONTINUE;
3313}
3314
3315int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
3316{
c76de350 3317 return kvm_x86_ops->get_dr(ctxt->vcpu, dr, dest);
bbd9b64e
CO		 3318}
3319
3320int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
3321{
3322 unsigned long mask = (ctxt->mode == X86EMUL_MODE_PROT64) ? ~0ULL : ~0U;
bbd9b64e 3323
c76de350 3324 return kvm_x86_ops->set_dr(ctxt->vcpu, dr, value & mask);
bbd9b64e
CO		 3325}
3326
3327void kvm_report_emulation_failure(struct kvm_vcpu *vcpu, const char *context)
3328{
bbd9b64e 3329 u8 opcodes[4];
5fdbf976 3330 unsigned long rip = kvm_rip_read(vcpu);
bbd9b64e
CO		 3331 unsigned long rip_linear;
3332
f76c710d 3333 if (!printk_ratelimit())
bbd9b64e
CO		 3334 return;
3335
25be4608
GC		 3336 rip_linear = rip + get_segment_base(vcpu, VCPU_SREG_CS);
3337
1871c602 3338 kvm_read_guest_virt(rip_linear, (void *)opcodes, 4, vcpu, NULL);
bbd9b64e
CO		 3339
3340 printk(KERN_ERR "emulation failed (%s) rip %lx %02x %02x %02x %02x\n",
3341 context, rip, opcodes[0], opcodes[1], opcodes[2], opcodes[3]);
bbd9b64e
CO		 3342}
3343EXPORT_SYMBOL_GPL(kvm_report_emulation_failure);
3344
14af3f3c 3345static struct x86_emulate_ops emulate_ops = {
1871c602
GN		 3346 .read_std = kvm_read_guest_virt_system,
3347 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 3348 .read_emulated = emulator_read_emulated,
3349 .write_emulated = emulator_write_emulated,
3350 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3351};
3352
5fdbf976
MT		 3353static void cache_all_regs(struct kvm_vcpu *vcpu)
3354{
3355 kvm_register_read(vcpu, VCPU_REGS_RAX);
3356 kvm_register_read(vcpu, VCPU_REGS_RSP);
3357 kvm_register_read(vcpu, VCPU_REGS_RIP);
3358 vcpu->arch.regs_dirty = ~0;
3359}
3360
bbd9b64e 3361int emulate_instruction(struct kvm_vcpu *vcpu,
bbd9b64e
CO		 3362 unsigned long cr2,
3363 u16 error_code,
571008da 3364 int emulation_type)
bbd9b64e 3365{
310b5d30 3366 int r, shadow_mask;
571008da 3367 struct decode_cache *c;
851ba692 3368 struct kvm_run *run = vcpu->run;
bbd9b64e 3369
26eef70c 3370 kvm_clear_exception_queue(vcpu);
ad312c7c 3371 vcpu->arch.mmio_fault_cr2 = cr2;
5fdbf976 3372 /*
56e82318 3373 * TODO: fix emulate.c to use guest_read/write_register
5fdbf976
MT		 3374 * instead of direct ->regs accesses, can save hundred cycles
3375 * on Intel for instructions that don't read/change RSP, for
3376 * for example.
3377 */
3378 cache_all_regs(vcpu);
bbd9b64e
CO		 3379
3380 vcpu->mmio_is_write = 0;
ad312c7c 3381 vcpu->arch.pio.string = 0;
bbd9b64e 3382
571008da 3383 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
bbd9b64e
CO		 3384 int cs_db, cs_l;
3385 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
3386
ad312c7c 3387 vcpu->arch.emulate_ctxt.vcpu = vcpu;
91586a3b 3388 vcpu->arch.emulate_ctxt.eflags = kvm_get_rflags(vcpu);
ad312c7c 3389 vcpu->arch.emulate_ctxt.mode =
a0044755 3390 (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
ad312c7c 3391 (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM)
a0044755 3392 ? X86EMUL_MODE_VM86 : cs_l
bbd9b64e
CO		 3393 ? X86EMUL_MODE_PROT64 : cs_db
3394 ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
3395
ad312c7c 3396 r = x86_decode_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
571008da 3397
0cb5762e
AP		 3398 /* Only allow emulation of specific instructions on #UD
3399 * (namely VMMCALL, sysenter, sysexit, syscall)*/
571008da 3400 c = &vcpu->arch.emulate_ctxt.decode;
0cb5762e
AP		 3401 if (emulation_type & EMULTYPE_TRAP_UD) {
3402 if (!c->twobyte)
3403 return EMULATE_FAIL;
3404 switch (c->b) {
3405 case 0x01: /* VMMCALL */
3406 if (c->modrm_mod != 3 || c->modrm_rm != 1)
3407 return EMULATE_FAIL;
3408 break;
3409 case 0x34: /* sysenter */
3410 case 0x35: /* sysexit */
3411 if (c->modrm_mod != 0 || c->modrm_rm != 0)
3412 return EMULATE_FAIL;
3413 break;
3414 case 0x05: /* syscall */
3415 if (c->modrm_mod != 0 || c->modrm_rm != 0)
3416 return EMULATE_FAIL;
3417 break;
3418 default:
3419 return EMULATE_FAIL;
3420 }
3421
3422 if (!(c->modrm_reg == 0 || c->modrm_reg == 3))
3423 return EMULATE_FAIL;
3424 }
571008da 3425
f2b5756b 3426 ++vcpu->stat.insn_emulation;
bbd9b64e 3427 if (r) {
f2b5756b 3428 ++vcpu->stat.insn_emulation_fail;
bbd9b64e
CO		 3429 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
3430 return EMULATE_DONE;
3431 return EMULATE_FAIL;
3432 }
3433 }
3434
ba8afb6b
GN		 3435 if (emulation_type & EMULTYPE_SKIP) {
3436 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.decode.eip);
3437 return EMULATE_DONE;
3438 }
3439
ad312c7c 3440 r = x86_emulate_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
310b5d30
GC		 3441 shadow_mask = vcpu->arch.emulate_ctxt.interruptibility;
3442
3443 if (r == 0)
3444 kvm_x86_ops->set_interrupt_shadow(vcpu, shadow_mask);
bbd9b64e 3445
ad312c7c 3446 if (vcpu->arch.pio.string)
bbd9b64e
CO		 3447 return EMULATE_DO_MMIO;
3448
112592da 3449 if (r || vcpu->mmio_is_write) {
bbd9b64e
CO		 3450 run->exit_reason = KVM_EXIT_MMIO;
3451 run->mmio.phys_addr = vcpu->mmio_phys_addr;
3452 memcpy(run->mmio.data, vcpu->mmio_data, 8);
3453 run->mmio.len = vcpu->mmio_size;
3454 run->mmio.is_write = vcpu->mmio_is_write;
3455 }
3456
3457 if (r) {
3458 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
3459 return EMULATE_DONE;
3460 if (!vcpu->mmio_needed) {
3461 kvm_report_emulation_failure(vcpu, "mmio");
3462 return EMULATE_FAIL;
3463 }
3464 return EMULATE_DO_MMIO;
3465 }
3466
91586a3b 3467 kvm_set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
bbd9b64e
CO		 3468
3469 if (vcpu->mmio_is_write) {
3470 vcpu->mmio_needed = 0;
3471 return EMULATE_DO_MMIO;
3472 }
3473
3474 return EMULATE_DONE;
3475}
3476EXPORT_SYMBOL_GPL(emulate_instruction);
3477
de7d789a
CO		 3478static int pio_copy_data(struct kvm_vcpu *vcpu)
3479{
ad312c7c 3480 void *p = vcpu->arch.pio_data;
0f346074 3481 gva_t q = vcpu->arch.pio.guest_gva;
de7d789a 3482 unsigned bytes;
0f346074 3483 int ret;
1871c602 3484 u32 error_code;
de7d789a 3485
ad312c7c
ZX		 3486 bytes = vcpu->arch.pio.size * vcpu->arch.pio.cur_count;
3487 if (vcpu->arch.pio.in)
1871c602 3488 ret = kvm_write_guest_virt(q, p, bytes, vcpu, &error_code);
de7d789a 3489 else
1871c602
GN		 3490 ret = kvm_read_guest_virt(q, p, bytes, vcpu, &error_code);
3491
3492 if (ret == X86EMUL_PROPAGATE_FAULT)
3493 kvm_inject_page_fault(vcpu, q, error_code);
3494
0f346074 3495 return ret;
de7d789a
CO		 3496}
3497
3498int complete_pio(struct kvm_vcpu *vcpu)
3499{
ad312c7c 3500 struct kvm_pio_request *io = &vcpu->arch.pio;
de7d789a
CO		 3501 long delta;
3502 int r;
5fdbf976 3503 unsigned long val;
de7d789a
CO		 3504
3505 if (!io->string) {
5fdbf976
MT		 3506 if (io->in) {
3507 val = kvm_register_read(vcpu, VCPU_REGS_RAX);
3508 memcpy(&val, vcpu->arch.pio_data, io->size);
3509 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
3510 }
de7d789a
CO		 3511 } else {
3512 if (io->in) {
3513 r = pio_copy_data(vcpu);
5fdbf976 3514 if (r)
1871c602 3515 goto out;
de7d789a
CO		 3516 }
3517
3518 delta = 1;
3519 if (io->rep) {
3520 delta *= io->cur_count;
3521 /*
3522 * The size of the register should really depend on
3523 * current address size.
3524 */
5fdbf976
MT		 3525 val = kvm_register_read(vcpu, VCPU_REGS_RCX);
3526 val -= delta;
3527 kvm_register_write(vcpu, VCPU_REGS_RCX, val);
de7d789a
CO		 3528 }
3529 if (io->down)
3530 delta = -delta;
3531 delta *= io->size;
5fdbf976
MT		 3532 if (io->in) {
3533 val = kvm_register_read(vcpu, VCPU_REGS_RDI);
3534 val += delta;
3535 kvm_register_write(vcpu, VCPU_REGS_RDI, val);
3536 } else {
3537 val = kvm_register_read(vcpu, VCPU_REGS_RSI);
3538 val += delta;
3539 kvm_register_write(vcpu, VCPU_REGS_RSI, val);
3540 }
de7d789a 3541 }
1871c602 3542out:
de7d789a
CO		 3543 io->count -= io->cur_count;
3544 io->cur_count = 0;
3545
3546 return 0;
3547}
3548
bda9020e 3549static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
de7d789a
CO		 3550{
3551 /* TODO: String I/O for in kernel device */
bda9020e 3552 int r;
de7d789a 3553
ad312c7c 3554 if (vcpu->arch.pio.in)
e93f8a0f 3555 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
bda9020e 3556 vcpu->arch.pio.size, pd);
de7d789a 3557 else
e93f8a0f
MT		 3558 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
3559 vcpu->arch.pio.port, vcpu->arch.pio.size,
3560 pd);
bda9020e 3561 return r;
de7d789a
CO		 3562}
3563
bda9020e 3564static int pio_string_write(struct kvm_vcpu *vcpu)
de7d789a 3565{
ad312c7c
ZX		 3566 struct kvm_pio_request *io = &vcpu->arch.pio;
3567 void *pd = vcpu->arch.pio_data;
bda9020e 3568 int i, r = 0;
de7d789a 3569
de7d789a 3570 for (i = 0; i < io->cur_count; i++) {
e93f8a0f 3571 if (kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
bda9020e
MT		 3572 io->port, io->size, pd)) {
3573 r = -EOPNOTSUPP;
3574 break;
3575 }
de7d789a
CO		 3576 pd += io->size;
3577 }
bda9020e 3578 return r;
de7d789a
CO		 3579}
3580
851ba692 3581int kvm_emulate_pio(struct kvm_vcpu *vcpu, int in, int size, unsigned port)
de7d789a 3582{
5fdbf976 3583 unsigned long val;
de7d789a 3584
f850e2e6
GN		 3585 trace_kvm_pio(!in, port, size, 1);
3586
de7d789a
CO		 3587 vcpu->run->exit_reason = KVM_EXIT_IO;
3588 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
ad312c7c 3589 vcpu->run->io.size = vcpu->arch.pio.size = size;
de7d789a 3590 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
ad312c7c
ZX		 3591 vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = 1;
3592 vcpu->run->io.port = vcpu->arch.pio.port = port;
3593 vcpu->arch.pio.in = in;
3594 vcpu->arch.pio.string = 0;
3595 vcpu->arch.pio.down = 0;
ad312c7c 3596 vcpu->arch.pio.rep = 0;
de7d789a 3597
1976d2d2
TY		 3598 if (!vcpu->arch.pio.in) {
3599 val = kvm_register_read(vcpu, VCPU_REGS_RAX);
3600 memcpy(vcpu->arch.pio_data, &val, 4);
3601 }
de7d789a 3602
bda9020e 3603 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
de7d789a
CO		 3604 complete_pio(vcpu);
3605 return 1;
3606 }
3607 return 0;
3608}
3609EXPORT_SYMBOL_GPL(kvm_emulate_pio);
3610
851ba692 3611int kvm_emulate_pio_string(struct kvm_vcpu *vcpu, int in,
de7d789a
CO		 3612 int size, unsigned long count, int down,
3613 gva_t address, int rep, unsigned port)
3614{
3615 unsigned now, in_page;
0f346074 3616 int ret = 0;
de7d789a 3617
f850e2e6
GN		 3618 trace_kvm_pio(!in, port, size, count);
3619
de7d789a
CO		 3620 vcpu->run->exit_reason = KVM_EXIT_IO;
3621 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
ad312c7c 3622 vcpu->run->io.size = vcpu->arch.pio.size = size;
de7d789a 3623 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
ad312c7c
ZX		 3624 vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = count;
3625 vcpu->run->io.port = vcpu->arch.pio.port = port;
3626 vcpu->arch.pio.in = in;
3627 vcpu->arch.pio.string = 1;
3628 vcpu->arch.pio.down = down;
ad312c7c 3629 vcpu->arch.pio.rep = rep;
de7d789a
CO		 3630
3631 if (!count) {
3632 kvm_x86_ops->skip_emulated_instruction(vcpu);
3633 return 1;
3634 }
3635
3636 if (!down)
3637 in_page = PAGE_SIZE - offset_in_page(address);
3638 else
3639 in_page = offset_in_page(address) + size;
3640 now = min(count, (unsigned long)in_page / size);
0f346074 3641 if (!now)
de7d789a 3642 now = 1;
de7d789a
CO		 3643 if (down) {
3644 /*
3645 * String I/O in reverse. Yuck. Kill the guest, fix later.
3646 */
3647 pr_unimpl(vcpu, "guest string pio down\n");
c1a5d4f9 3648 kvm_inject_gp(vcpu, 0);
de7d789a
CO		 3649 return 1;
3650 }
3651 vcpu->run->io.count = now;
ad312c7c 3652 vcpu->arch.pio.cur_count = now;
de7d789a 3653
ad312c7c 3654 if (vcpu->arch.pio.cur_count == vcpu->arch.pio.count)
de7d789a
CO		 3655 kvm_x86_ops->skip_emulated_instruction(vcpu);
3656
0f346074 3657 vcpu->arch.pio.guest_gva = address;
de7d789a 3658
ad312c7c 3659 if (!vcpu->arch.pio.in) {
de7d789a
CO		 3660 /* string PIO write */
3661 ret = pio_copy_data(vcpu);
1871c602 3662 if (ret == X86EMUL_PROPAGATE_FAULT)
0f346074 3663 return 1;
bda9020e 3664 if (ret == 0 && !pio_string_write(vcpu)) {
de7d789a 3665 complete_pio(vcpu);
ad312c7c 3666 if (vcpu->arch.pio.count == 0)
de7d789a
CO		 3667 ret = 1;
3668 }
bda9020e
MT		 3669 }
3670 /* no string PIO read support yet */
de7d789a
CO		 3671
3672 return ret;
3673}
3674EXPORT_SYMBOL_GPL(kvm_emulate_pio_string);
3675
c8076604
GH		 3676static void bounce_off(void *info)
3677{
3678 /* nothing */
3679}
3680
c8076604
GH		 3681static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
3682 void *data)
3683{
3684 struct cpufreq_freqs *freq = data;
3685 struct kvm *kvm;
3686 struct kvm_vcpu *vcpu;
3687 int i, send_ipi = 0;
3688
c8076604
GH		 3689 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
3690 return 0;
3691 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
3692 return 0;
0cca7907 3693 per_cpu(cpu_tsc_khz, freq->cpu) = freq->new;
c8076604
GH		 3694
3695 spin_lock(&kvm_lock);
3696 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 3697 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 3698 if (vcpu->cpu != freq->cpu)
3699 continue;
3700 if (!kvm_request_guest_time_update(vcpu))
3701 continue;
3702 if (vcpu->cpu != smp_processor_id())
3703 send_ipi++;
3704 }
3705 }
3706 spin_unlock(&kvm_lock);
3707
3708 if (freq->old < freq->new && send_ipi) {
3709 /*
3710 * We upscale the frequency. Must make the guest
3711 * doesn't see old kvmclock values while running with
3712 * the new frequency, otherwise we risk the guest sees
3713 * time go backwards.
3714 *
3715 * In case we update the frequency for another cpu
3716 * (which might be in guest context) send an interrupt
3717 * to kick the cpu out of guest context. Next time
3718 * guest context is entered kvmclock will be updated,
3719 * so the guest will not see stale values.
3720 */
3721 smp_call_function_single(freq->cpu, bounce_off, NULL, 1);
3722 }
3723 return 0;
3724}
3725
3726static struct notifier_block kvmclock_cpufreq_notifier_block = {
3727 .notifier_call = kvmclock_cpufreq_notifier
3728};
3729
b820cc0c
ZA		 3730static void kvm_timer_init(void)
3731{
3732 int cpu;
3733
b820cc0c 3734 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
b820cc0c
ZA		 3735 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
3736 CPUFREQ_TRANSITION_NOTIFIER);
6b7d7e76
ZA		 3737 for_each_online_cpu(cpu) {
3738 unsigned long khz = cpufreq_get(cpu);
3739 if (!khz)
3740 khz = tsc_khz;
3741 per_cpu(cpu_tsc_khz, cpu) = khz;
3742 }
0cca7907
ZA		 3743 } else {
3744 for_each_possible_cpu(cpu)
3745 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
b820cc0c
ZA		 3746 }
3747}
3748
f8c16bba 3749int kvm_arch_init(void *opaque)
043405e1 3750{
b820cc0c 3751 int r;
f8c16bba
ZX		 3752 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
3753
f8c16bba
ZX		 3754 if (kvm_x86_ops) {
3755 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 3756 r = -EEXIST;
3757 goto out;
f8c16bba
ZX		 3758 }
3759
3760 if (!ops->cpu_has_kvm_support()) {
3761 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 3762 r = -EOPNOTSUPP;
3763 goto out;
f8c16bba
ZX		 3764 }
3765 if (ops->disabled_by_bios()) {
3766 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 3767 r = -EOPNOTSUPP;
3768 goto out;
f8c16bba
ZX		 3769 }
3770
97db56ce
AK		 3771 r = kvm_mmu_module_init();
3772 if (r)
3773 goto out;
3774
3775 kvm_init_msr_list();
3776
f8c16bba 3777 kvm_x86_ops = ops;
56c6d28a 3778 kvm_mmu_set_nonpresent_ptes(0ull, 0ull);
7b52345e
SY		 3779 kvm_mmu_set_base_ptes(PT_PRESENT_MASK);
3780 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 3781 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 3782
b820cc0c 3783 kvm_timer_init();
c8076604 3784
f8c16bba 3785 return 0;
56c6d28a
ZX		 3786
3787out:
56c6d28a 3788 return r;
043405e1 3789}
8776e519 3790
f8c16bba
ZX		 3791void kvm_arch_exit(void)
3792{
888d256e
JK		 3793 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
3794 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
3795 CPUFREQ_TRANSITION_NOTIFIER);
f8c16bba 3796 kvm_x86_ops = NULL;
56c6d28a
ZX		 3797 kvm_mmu_module_exit();
3798}
f8c16bba 3799
8776e519
HB		 3800int kvm_emulate_halt(struct kvm_vcpu *vcpu)
3801{
3802 ++vcpu->stat.halt_exits;
3803 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 3804 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 3805 return 1;
3806 } else {
3807 vcpu->run->exit_reason = KVM_EXIT_HLT;
3808 return 0;
3809 }
3810}
3811EXPORT_SYMBOL_GPL(kvm_emulate_halt);
3812
2f333bcb
MT		 3813static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0,
3814 unsigned long a1)
3815{
3816 if (is_long_mode(vcpu))
3817 return a0;
3818 else
3819 return a0 | ((gpa_t)a1 << 32);
3820}
3821
55cd8e5a
GN		 3822int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
3823{
3824 u64 param, ingpa, outgpa, ret;
3825 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
3826 bool fast, longmode;
3827 int cs_db, cs_l;
3828
3829 /*
3830 * hypercall generates UD from non zero cpl and real mode
3831 * per HYPER-V spec
3832 */
3eeb3288 3833 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 3834 kvm_queue_exception(vcpu, UD_VECTOR);
3835 return 0;
3836 }
3837
3838 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
3839 longmode = is_long_mode(vcpu) && cs_l == 1;
3840
3841 if (!longmode) {
ccd46936
GN		 3842 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
3843 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
3844 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
3845 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
3846 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
3847 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 3848 }
3849#ifdef CONFIG_X86_64
3850 else {
3851 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
3852 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
3853 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
3854 }
3855#endif
3856
3857 code = param & 0xffff;
3858 fast = (param >> 16) & 0x1;
3859 rep_cnt = (param >> 32) & 0xfff;
3860 rep_idx = (param >> 48) & 0xfff;
3861
3862 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
3863
c25bc163
GN		 3864 switch (code) {
3865 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
3866 kvm_vcpu_on_spin(vcpu);
3867 break;
3868 default:
3869 res = HV_STATUS_INVALID_HYPERCALL_CODE;
3870 break;
3871 }
55cd8e5a
GN		 3872
3873 ret = res | (((u64)rep_done & 0xfff) << 32);
3874 if (longmode) {
3875 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
3876 } else {
3877 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
3878 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
3879 }
3880
3881 return 1;
3882}
3883
8776e519
HB		 3884int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
3885{
3886 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 3887 int r = 1;
8776e519 3888
55cd8e5a
GN		 3889 if (kvm_hv_hypercall_enabled(vcpu->kvm))
3890 return kvm_hv_hypercall(vcpu);
3891
5fdbf976
MT		 3892 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
3893 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
3894 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
3895 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
3896 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 3897
229456fc 3898 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 3899
8776e519
HB		 3900 if (!is_long_mode(vcpu)) {
3901 nr &= 0xFFFFFFFF;
3902 a0 &= 0xFFFFFFFF;
3903 a1 &= 0xFFFFFFFF;
3904 a2 &= 0xFFFFFFFF;
3905 a3 &= 0xFFFFFFFF;
3906 }
3907
07708c4a
JK		 3908 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
3909 ret = -KVM_EPERM;
3910 goto out;
3911 }
3912
8776e519 3913 switch (nr) {
b93463aa
AK		 3914 case KVM_HC_VAPIC_POLL_IRQ:
3915 ret = 0;
3916 break;
2f333bcb
MT		 3917 case KVM_HC_MMU_OP:
3918 r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret);
3919 break;
8776e519
HB		 3920 default:
3921 ret = -KVM_ENOSYS;
3922 break;
3923 }
07708c4a 3924out:
5fdbf976 3925 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 3926 ++vcpu->stat.hypercalls;
2f333bcb 3927 return r;
8776e519
HB		 3928}
3929EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
3930
3931int kvm_fix_hypercall(struct kvm_vcpu *vcpu)
3932{
3933 char instruction[3];
5fdbf976 3934 unsigned long rip = kvm_rip_read(vcpu);
8776e519 3935
8776e519
HB		 3936 /*
3937 * Blow out the MMU to ensure that no other VCPU has an active mapping
3938 * to ensure that the updated hypercall appears atomically across all
3939 * VCPUs.
3940 */
3941 kvm_mmu_zap_all(vcpu->kvm);
3942
8776e519 3943 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 3944
7edcface 3945 return emulator_write_emulated(rip, instruction, 3, vcpu);
8776e519
HB		 3946}
3947
3948static u64 mk_cr_64(u64 curr_cr, u32 new_val)
3949{
3950 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
3951}
3952
3953void realmode_lgdt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
3954{
89a27f4d 3955 struct desc_ptr dt = { limit, base };
8776e519
HB		 3956
3957 kvm_x86_ops->set_gdt(vcpu, &dt);
3958}
3959
3960void realmode_lidt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
3961{
89a27f4d 3962 struct desc_ptr dt = { limit, base };
8776e519
HB		 3963
3964 kvm_x86_ops->set_idt(vcpu, &dt);
3965}
3966
3967void realmode_lmsw(struct kvm_vcpu *vcpu, unsigned long msw,
3968 unsigned long *rflags)
3969{
2d3ad1f4 3970 kvm_lmsw(vcpu, msw);
91586a3b 3971 *rflags = kvm_get_rflags(vcpu);
8776e519
HB		 3972}
3973
3974unsigned long realmode_get_cr(struct kvm_vcpu *vcpu, int cr)
3975{
54e445ca
JR		 3976 unsigned long value;
3977
8776e519
HB		 3978 switch (cr) {
3979 case 0:
4d4ec087 3980 value = kvm_read_cr0(vcpu);
54e445ca 3981 break;
8776e519 3982 case 2:
54e445ca
JR		 3983 value = vcpu->arch.cr2;
3984 break;
8776e519 3985 case 3:
54e445ca
JR		 3986 value = vcpu->arch.cr3;
3987 break;
8776e519 3988 case 4:
fc78f519 3989 value = kvm_read_cr4(vcpu);
54e445ca 3990 break;
152ff9be 3991 case 8:
54e445ca
JR		 3992 value = kvm_get_cr8(vcpu);
3993 break;
8776e519 3994 default:
b8688d51 3995 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
8776e519
HB		 3996 return 0;
3997 }
54e445ca
JR		 3998
3999 return value;
8776e519
HB		 4000}
4001
4002void realmode_set_cr(struct kvm_vcpu *vcpu, int cr, unsigned long val,
4003 unsigned long *rflags)
4004{
4005 switch (cr) {
4006 case 0:
4d4ec087 4007 kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
91586a3b 4008 *rflags = kvm_get_rflags(vcpu);
8776e519
HB		 4009 break;
4010 case 2:
ad312c7c 4011 vcpu->arch.cr2 = val;
8776e519
HB		 4012 break;
4013 case 3:
2d3ad1f4 4014 kvm_set_cr3(vcpu, val);
8776e519
HB		 4015 break;
4016 case 4:
fc78f519 4017 kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
8776e519 4018 break;
152ff9be 4019 case 8:
2d3ad1f4 4020 kvm_set_cr8(vcpu, val & 0xfUL);
152ff9be 4021 break;
8776e519 4022 default:
b8688d51 4023 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
8776e519
HB		 4024 }
4025}
4026
07716717
DK		 4027static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)
4028{
ad312c7c
ZX		 4029 struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];
4030 int j, nent = vcpu->arch.cpuid_nent;
07716717
DK		 4031
4032 e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;
4033 /* when no next entry is found, the current entry[i] is reselected */
0fdf8e59 4034 for (j = i + 1; ; j = (j + 1) % nent) {
ad312c7c 4035 struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j];
07716717
DK		 4036 if (ej->function == e->function) {
4037 ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
4038 return j;
4039 }
4040 }
4041 return 0; /* silence gcc, even though control never reaches here */
4042}
4043
4044/* find an entry with matching function, matching index (if needed), and that
4045 * should be read next (if it's stateful) */
4046static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e,
4047 u32 function, u32 index)
4048{
4049 if (e->function != function)
4050 return 0;
4051 if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index)
4052 return 0;
4053 if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) &&
19355475 4054 !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT))
07716717
DK		 4055 return 0;
4056 return 1;
4057}
4058
d8017474
AG		 4059struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
4060 u32 function, u32 index)
8776e519
HB		 4061{
4062 int i;
d8017474 4063 struct kvm_cpuid_entry2 *best = NULL;
8776e519 4064
ad312c7c 4065 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
d8017474
AG		 4066 struct kvm_cpuid_entry2 *e;
4067
ad312c7c 4068 e = &vcpu->arch.cpuid_entries[i];
07716717
DK		 4069 if (is_matching_cpuid_entry(e, function, index)) {
4070 if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC)
4071 move_to_next_stateful_cpuid_entry(vcpu, i);
8776e519
HB		 4072 best = e;
4073 break;
4074 }
4075 /*
4076 * Both basic or both extended?
4077 */
4078 if (((e->function ^ function) & 0x80000000) == 0)
4079 if (!best || e->function > best->function)
4080 best = e;
4081 }
d8017474
AG		 4082 return best;
4083}
0e851880 4084EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry);
d8017474 4085
82725b20
DE		 4086int cpuid_maxphyaddr(struct kvm_vcpu *vcpu)
4087{
4088 struct kvm_cpuid_entry2 *best;
4089
4090 best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0);
4091 if (best)
4092 return best->eax & 0xff;
4093 return 36;
4094}
4095
d8017474
AG		 4096void kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
4097{
4098 u32 function, index;
4099 struct kvm_cpuid_entry2 *best;
4100
4101 function = kvm_register_read(vcpu, VCPU_REGS_RAX);
4102 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
4103 kvm_register_write(vcpu, VCPU_REGS_RAX, 0);
4104 kvm_register_write(vcpu, VCPU_REGS_RBX, 0);
4105 kvm_register_write(vcpu, VCPU_REGS_RCX, 0);
4106 kvm_register_write(vcpu, VCPU_REGS_RDX, 0);
4107 best = kvm_find_cpuid_entry(vcpu, function, index);
8776e519 4108 if (best) {
5fdbf976
MT		 4109 kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax);
4110 kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx);
4111 kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx);
4112 kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx);
8776e519 4113 }
8776e519 4114 kvm_x86_ops->skip_emulated_instruction(vcpu);
229456fc
MT		 4115 trace_kvm_cpuid(function,
4116 kvm_register_read(vcpu, VCPU_REGS_RAX),
4117 kvm_register_read(vcpu, VCPU_REGS_RBX),
4118 kvm_register_read(vcpu, VCPU_REGS_RCX),
4119 kvm_register_read(vcpu, VCPU_REGS_RDX));
8776e519
HB		 4120}
4121EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
d0752060 4122
b6c7a5dc
HB		 4123/*
4124 * Check if userspace requested an interrupt window, and that the
4125 * interrupt window is open.
4126 *
4127 * No need to exit to userspace if we already have an interrupt queued.
4128 */
851ba692 4129static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 4130{
8061823a 4131 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 4132 vcpu->run->request_interrupt_window &&
5df56646 4133 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 4134}
4135
851ba692 4136static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 4137{
851ba692
AK		 4138 struct kvm_run *kvm_run = vcpu->run;
4139
91586a3b 4140 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 4141 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 4142 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 4143 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 4144 kvm_run->ready_for_interrupt_injection = 1;
4531220b 4145 else
b6c7a5dc 4146 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 4147 kvm_arch_interrupt_allowed(vcpu) &&
4148 !kvm_cpu_has_interrupt(vcpu) &&
4149 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 4150}
4151
b93463aa
AK		 4152static void vapic_enter(struct kvm_vcpu *vcpu)
4153{
4154 struct kvm_lapic *apic = vcpu->arch.apic;
4155 struct page *page;
4156
4157 if (!apic || !apic->vapic_addr)
4158 return;
4159
4160 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
72dc67a6
IE		 4161
4162 vcpu->arch.apic->vapic_page = page;
b93463aa
AK		 4163}
4164
4165static void vapic_exit(struct kvm_vcpu *vcpu)
4166{
4167 struct kvm_lapic *apic = vcpu->arch.apic;
f656ce01 4168 int idx;
b93463aa
AK		 4169
4170 if (!apic || !apic->vapic_addr)
4171 return;
4172
f656ce01 4173 idx = srcu_read_lock(&vcpu->kvm->srcu);
b93463aa
AK		 4174 kvm_release_page_dirty(apic->vapic_page);
4175 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f656ce01 4176 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 4177}
4178
95ba8273
GN		 4179static void update_cr8_intercept(struct kvm_vcpu *vcpu)
4180{
4181 int max_irr, tpr;
4182
4183 if (!kvm_x86_ops->update_cr8_intercept)
4184 return;
4185
88c808fd
AK		 4186 if (!vcpu->arch.apic)
4187 return;
4188
8db3baa2
GN		 4189 if (!vcpu->arch.apic->vapic_addr)
4190 max_irr = kvm_lapic_find_highest_irr(vcpu);
4191 else
4192 max_irr = -1;
95ba8273
GN		 4193
4194 if (max_irr != -1)
4195 max_irr >>= 4;
4196
4197 tpr = kvm_lapic_get_cr8(vcpu);
4198
4199 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
4200}
4201
851ba692 4202static void inject_pending_event(struct kvm_vcpu *vcpu)
95ba8273
GN		 4203{
4204 /* try to reinject previous events if any */
b59bb7bd
GN		 4205 if (vcpu->arch.exception.pending) {
4206 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
4207 vcpu->arch.exception.has_error_code,
4208 vcpu->arch.exception.error_code);
4209 return;
4210 }
4211
95ba8273
GN		 4212 if (vcpu->arch.nmi_injected) {
4213 kvm_x86_ops->set_nmi(vcpu);
4214 return;
4215 }
4216
4217 if (vcpu->arch.interrupt.pending) {
66fd3f7f 4218 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 4219 return;
4220 }
4221
4222 /* try to inject new event if pending */
4223 if (vcpu->arch.nmi_pending) {
4224 if (kvm_x86_ops->nmi_allowed(vcpu)) {
4225 vcpu->arch.nmi_pending = false;
4226 vcpu->arch.nmi_injected = true;
4227 kvm_x86_ops->set_nmi(vcpu);
4228 }
4229 } else if (kvm_cpu_has_interrupt(vcpu)) {
4230 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 4231 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
4232 false);
4233 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 4234 }
4235 }
4236}
4237
851ba692 4238static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 4239{
4240 int r;
6a8b1d13 4241 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 4242 vcpu->run->request_interrupt_window;
b6c7a5dc 4243
2e53d63a
MT		 4244 if (vcpu->requests)
4245 if (test_and_clear_bit(KVM_REQ_MMU_RELOAD, &vcpu->requests))
4246 kvm_mmu_unload(vcpu);
4247
b6c7a5dc
HB		 4248 r = kvm_mmu_reload(vcpu);
4249 if (unlikely(r))
4250 goto out;
4251
2f52d58c
AK		 4252 if (vcpu->requests) {
4253 if (test_and_clear_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests))
2f599714 4254 __kvm_migrate_timers(vcpu);
c8076604
GH		 4255 if (test_and_clear_bit(KVM_REQ_KVMCLOCK_UPDATE, &vcpu->requests))
4256 kvm_write_guest_time(vcpu);
4731d4c7
MT		 4257 if (test_and_clear_bit(KVM_REQ_MMU_SYNC, &vcpu->requests))
4258 kvm_mmu_sync_roots(vcpu);
d4acf7e7
MT		 4259 if (test_and_clear_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests))
4260 kvm_x86_ops->tlb_flush(vcpu);
b93463aa
AK		 4261 if (test_and_clear_bit(KVM_REQ_REPORT_TPR_ACCESS,
4262 &vcpu->requests)) {
851ba692 4263 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 4264 r = 0;
4265 goto out;
4266 }
71c4dfaf 4267 if (test_and_clear_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests)) {
851ba692 4268 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 4269 r = 0;
4270 goto out;
4271 }
02daab21
AK		 4272 if (test_and_clear_bit(KVM_REQ_DEACTIVATE_FPU, &vcpu->requests)) {
4273 vcpu->fpu_active = 0;
4274 kvm_x86_ops->fpu_deactivate(vcpu);
4275 }
2f52d58c 4276 }
b93463aa 4277
b6c7a5dc
HB		 4278 preempt_disable();
4279
4280 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 4281 if (vcpu->fpu_active)
4282 kvm_load_guest_fpu(vcpu);
b6c7a5dc
HB		 4283
4284 local_irq_disable();
4285
32f88400
MT		 4286 clear_bit(KVM_REQ_KICK, &vcpu->requests);
4287 smp_mb__after_clear_bit();
4288
d7690175 4289 if (vcpu->requests || need_resched() || signal_pending(current)) {
c7f0f24b 4290 set_bit(KVM_REQ_KICK, &vcpu->requests);
6c142801
AK		 4291 local_irq_enable();
4292 preempt_enable();
4293 r = 1;
4294 goto out;
4295 }
4296
851ba692 4297 inject_pending_event(vcpu);
b6c7a5dc 4298
6a8b1d13
GN		 4299 /* enable NMI/IRQ window open exits if needed */
4300 if (vcpu->arch.nmi_pending)
4301 kvm_x86_ops->enable_nmi_window(vcpu);
4302 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
4303 kvm_x86_ops->enable_irq_window(vcpu);
4304
95ba8273 4305 if (kvm_lapic_enabled(vcpu)) {
8db3baa2
GN		 4306 update_cr8_intercept(vcpu);
4307 kvm_lapic_sync_to_vapic(vcpu);
95ba8273 4308 }
b93463aa 4309
f656ce01 4310 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
3200f405 4311
b6c7a5dc
HB		 4312 kvm_guest_enter();
4313
42dbaa5a 4314 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 4315 set_debugreg(0, 7);
4316 set_debugreg(vcpu->arch.eff_db[0], 0);
4317 set_debugreg(vcpu->arch.eff_db[1], 1);
4318 set_debugreg(vcpu->arch.eff_db[2], 2);
4319 set_debugreg(vcpu->arch.eff_db[3], 3);
4320 }
b6c7a5dc 4321
229456fc 4322 trace_kvm_entry(vcpu->vcpu_id);
851ba692 4323 kvm_x86_ops->run(vcpu);
b6c7a5dc 4324
24f1e32c
FW		 4325 /*
4326 * If the guest has used debug registers, at least dr7
4327 * will be disabled while returning to the host.
4328 * If we don't have active breakpoints in the host, we don't
4329 * care about the messed up debug address registers. But if
4330 * we have some of them active, restore the old state.
4331 */
59d8eb53 4332 if (hw_breakpoint_active())
24f1e32c 4333 hw_breakpoint_restore();
42dbaa5a 4334
32f88400 4335 set_bit(KVM_REQ_KICK, &vcpu->requests);
b6c7a5dc
HB		 4336 local_irq_enable();
4337
4338 ++vcpu->stat.exits;
4339
4340 /*
4341 * We must have an instruction between local_irq_enable() and
4342 * kvm_guest_exit(), so the timer interrupt isn't delayed by
4343 * the interrupt shadow. The stat.exits increment will do nicely.
4344 * But we need to prevent reordering, hence this barrier():
4345 */
4346 barrier();
4347
4348 kvm_guest_exit();
4349
4350 preempt_enable();
4351
f656ce01 4352 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 4353
b6c7a5dc
HB		 4354 /*
4355 * Profile KVM exit RIPs:
4356 */
4357 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 4358 unsigned long rip = kvm_rip_read(vcpu);
4359 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 4360 }
4361
298101da 4362
b93463aa
AK		 4363 kvm_lapic_sync_from_vapic(vcpu);
4364
851ba692 4365 r = kvm_x86_ops->handle_exit(vcpu);
d7690175
MT		 4366out:
4367 return r;
4368}
b6c7a5dc 4369
09cec754 4370
851ba692 4371static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 4372{
4373 int r;
f656ce01 4374 struct kvm *kvm = vcpu->kvm;
d7690175
MT		 4375
4376 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
1b10bf31
JK		 4377 pr_debug("vcpu %d received sipi with vector # %x\n",
4378 vcpu->vcpu_id, vcpu->arch.sipi_vector);
d7690175 4379 kvm_lapic_reset(vcpu);
5f179287 4380 r = kvm_arch_vcpu_reset(vcpu);
d7690175
MT		 4381 if (r)
4382 return r;
4383 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 4384 }
4385
f656ce01 4386 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175
MT		 4387 vapic_enter(vcpu);
4388
4389 r = 1;
4390 while (r > 0) {
af2152f5 4391 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE)
851ba692 4392 r = vcpu_enter_guest(vcpu);
d7690175 4393 else {
f656ce01 4394 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 4395 kvm_vcpu_block(vcpu);
f656ce01 4396 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 4397 if (test_and_clear_bit(KVM_REQ_UNHALT, &vcpu->requests))
09cec754
GN		 4398 {
4399 switch(vcpu->arch.mp_state) {
4400 case KVM_MP_STATE_HALTED:
d7690175 4401 vcpu->arch.mp_state =
09cec754
GN		 4402 KVM_MP_STATE_RUNNABLE;
4403 case KVM_MP_STATE_RUNNABLE:
4404 break;
4405 case KVM_MP_STATE_SIPI_RECEIVED:
4406 default:
4407 r = -EINTR;
4408 break;
4409 }
4410 }
d7690175
MT		 4411 }
4412
09cec754
GN		 4413 if (r <= 0)
4414 break;
4415
4416 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
4417 if (kvm_cpu_has_pending_timer(vcpu))
4418 kvm_inject_pending_timer_irqs(vcpu);
4419
851ba692 4420 if (dm_request_for_irq_injection(vcpu)) {
09cec754 4421 r = -EINTR;
851ba692 4422 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 4423 ++vcpu->stat.request_irq_exits;
4424 }
4425 if (signal_pending(current)) {
4426 r = -EINTR;
851ba692 4427 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 4428 ++vcpu->stat.signal_exits;
4429 }
4430 if (need_resched()) {
f656ce01 4431 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
09cec754 4432 kvm_resched(vcpu);
f656ce01 4433 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 4434 }
b6c7a5dc
HB		 4435 }
4436
f656ce01 4437 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
851ba692 4438 post_kvm_run_save(vcpu);
b6c7a5dc 4439
b93463aa
AK		 4440 vapic_exit(vcpu);
4441
b6c7a5dc
HB		 4442 return r;
4443}
4444
4445int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
4446{
4447 int r;
4448 sigset_t sigsaved;
4449
4450 vcpu_load(vcpu);
4451
ac9f6dc0
AK		 4452 if (vcpu->sigset_active)
4453 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
4454
a4535290 4455 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 4456 kvm_vcpu_block(vcpu);
d7690175 4457 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 4458 r = -EAGAIN;
4459 goto out;
b6c7a5dc
HB		 4460 }
4461
b6c7a5dc
HB		 4462 /* re-sync apic's tpr */
4463 if (!irqchip_in_kernel(vcpu->kvm))
2d3ad1f4 4464 kvm_set_cr8(vcpu, kvm_run->cr8);
b6c7a5dc 4465
ad312c7c 4466 if (vcpu->arch.pio.cur_count) {
7567cae1 4467 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
b6c7a5dc 4468 r = complete_pio(vcpu);
7567cae1 4469 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 4470 if (r)
4471 goto out;
4472 }
b6c7a5dc
HB		 4473 if (vcpu->mmio_needed) {
4474 memcpy(vcpu->mmio_data, kvm_run->mmio.data, 8);
4475 vcpu->mmio_read_completed = 1;
4476 vcpu->mmio_needed = 0;
3200f405 4477
f656ce01 4478 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
851ba692 4479 r = emulate_instruction(vcpu, vcpu->arch.mmio_fault_cr2, 0,
571008da 4480 EMULTYPE_NO_DECODE);
f656ce01 4481 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 4482 if (r == EMULATE_DO_MMIO) {
4483 /*
4484 * Read-modify-write. Back to userspace.
4485 */
4486 r = 0;
4487 goto out;
4488 }
4489 }
5fdbf976
MT		 4490 if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL)
4491 kvm_register_write(vcpu, VCPU_REGS_RAX,
4492 kvm_run->hypercall.ret);
b6c7a5dc 4493
851ba692 4494 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 4495
4496out:
4497 if (vcpu->sigset_active)
4498 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
4499
4500 vcpu_put(vcpu);
4501 return r;
4502}
4503
4504int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
4505{
4506 vcpu_load(vcpu);
4507
5fdbf976
MT		 4508 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
4509 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
4510 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
4511 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
4512 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
4513 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
4514 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
4515 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 4516#ifdef CONFIG_X86_64
5fdbf976
MT		 4517 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
4518 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
4519 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
4520 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
4521 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
4522 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
4523 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
4524 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 4525#endif
4526
5fdbf976 4527 regs->rip = kvm_rip_read(vcpu);
91586a3b 4528 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc
HB		 4529
4530 vcpu_put(vcpu);
4531
4532 return 0;
4533}
4534
4535int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
4536{
4537 vcpu_load(vcpu);
4538
5fdbf976
MT		 4539 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
4540 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
4541 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
4542 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
4543 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
4544 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
4545 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
4546 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 4547#ifdef CONFIG_X86_64
5fdbf976
MT		 4548 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
4549 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
4550 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
4551 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
4552 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
4553 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
4554 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
4555 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 4556#endif
4557
5fdbf976 4558 kvm_rip_write(vcpu, regs->rip);
91586a3b 4559 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 4560
b4f14abd
JK		 4561 vcpu->arch.exception.pending = false;
4562
b6c7a5dc
HB		 4563 vcpu_put(vcpu);
4564
4565 return 0;
4566}
4567
3e6e0aab
GT		 4568void kvm_get_segment(struct kvm_vcpu *vcpu,
4569 struct kvm_segment *var, int seg)
b6c7a5dc 4570{
14af3f3c 4571 kvm_x86_ops->get_segment(vcpu, var, seg);
b6c7a5dc
HB		 4572}
4573
4574void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
4575{
4576 struct kvm_segment cs;
4577
3e6e0aab 4578 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 4579 *db = cs.db;
4580 *l = cs.l;
4581}
4582EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
4583
4584int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
4585 struct kvm_sregs *sregs)
4586{
89a27f4d 4587 struct desc_ptr dt;
b6c7a5dc
HB		 4588
4589 vcpu_load(vcpu);
4590
3e6e0aab
GT		 4591 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
4592 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
4593 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
4594 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
4595 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
4596 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 4597
3e6e0aab
GT		 4598 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
4599 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 4600
4601 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 4602 sregs->idt.limit = dt.size;
4603 sregs->idt.base = dt.address;
b6c7a5dc 4604 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 4605 sregs->gdt.limit = dt.size;
4606 sregs->gdt.base = dt.address;
b6c7a5dc 4607
4d4ec087 4608 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c
ZX		 4609 sregs->cr2 = vcpu->arch.cr2;
4610 sregs->cr3 = vcpu->arch.cr3;
fc78f519 4611 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 4612 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 4613 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 4614 sregs->apic_base = kvm_get_apic_base(vcpu);
4615
923c61bb 4616 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 4617
36752c9b 4618 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 4619 set_bit(vcpu->arch.interrupt.nr,
4620 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 4621
b6c7a5dc
HB		 4622 vcpu_put(vcpu);
4623
4624 return 0;
4625}
4626
62d9f0db
MT		 4627int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
4628 struct kvm_mp_state *mp_state)
4629{
4630 vcpu_load(vcpu);
4631 mp_state->mp_state = vcpu->arch.mp_state;
4632 vcpu_put(vcpu);
4633 return 0;
4634}
4635
4636int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
4637 struct kvm_mp_state *mp_state)
4638{
4639 vcpu_load(vcpu);
4640 vcpu->arch.mp_state = mp_state->mp_state;
4641 vcpu_put(vcpu);
4642 return 0;
4643}
4644
3e6e0aab 4645static void kvm_set_segment(struct kvm_vcpu *vcpu,
b6c7a5dc
HB		 4646 struct kvm_segment *var, int seg)
4647{
14af3f3c 4648 kvm_x86_ops->set_segment(vcpu, var, seg);
b6c7a5dc
HB		 4649}
4650
37817f29
IE		 4651static void seg_desct_to_kvm_desct(struct desc_struct *seg_desc, u16 selector,
4652 struct kvm_segment *kvm_desct)
4653{
46a359e7
AM		 4654 kvm_desct->base = get_desc_base(seg_desc);
4655 kvm_desct->limit = get_desc_limit(seg_desc);
c93cd3a5
MT		 4656 if (seg_desc->g) {
4657 kvm_desct->limit <<= 12;
4658 kvm_desct->limit |= 0xfff;
4659 }
37817f29
IE		 4660 kvm_desct->selector = selector;
4661 kvm_desct->type = seg_desc->type;
4662 kvm_desct->present = seg_desc->p;
4663 kvm_desct->dpl = seg_desc->dpl;
4664 kvm_desct->db = seg_desc->d;
4665 kvm_desct->s = seg_desc->s;
4666 kvm_desct->l = seg_desc->l;
4667 kvm_desct->g = seg_desc->g;
4668 kvm_desct->avl = seg_desc->avl;
4669 if (!selector)
4670 kvm_desct->unusable = 1;
4671 else
4672 kvm_desct->unusable = 0;
4673 kvm_desct->padding = 0;
4674}
4675
b8222ad2
AS		 4676static void get_segment_descriptor_dtable(struct kvm_vcpu *vcpu,
4677 u16 selector,
89a27f4d 4678 struct desc_ptr *dtable)
37817f29
IE		 4679{
4680 if (selector & 1 << 2) {
4681 struct kvm_segment kvm_seg;
4682
3e6e0aab 4683 kvm_get_segment(vcpu, &kvm_seg, VCPU_SREG_LDTR);
37817f29
IE		 4684
4685 if (kvm_seg.unusable)
89a27f4d 4686 dtable->size = 0;
37817f29 4687 else
89a27f4d
GN		 4688 dtable->size = kvm_seg.limit;
4689 dtable->address = kvm_seg.base;
37817f29
IE		 4690 }
4691 else
4692 kvm_x86_ops->get_gdt(vcpu, dtable);
4693}
4694
4695/* allowed just for 8 bytes segments */
4696static int load_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
4697 struct desc_struct *seg_desc)
4698{
89a27f4d 4699 struct desc_ptr dtable;
37817f29 4700 u16 index = selector >> 3;
6f550484
TY		 4701 int ret;
4702 u32 err;
4703 gva_t addr;
37817f29 4704
b8222ad2 4705 get_segment_descriptor_dtable(vcpu, selector, &dtable);
37817f29 4706
89a27f4d 4707 if (dtable.size < index * 8 + 7) {
37817f29 4708 kvm_queue_exception_e(vcpu, GP_VECTOR, selector & 0xfffc);
c125c607 4709 return X86EMUL_PROPAGATE_FAULT;
37817f29 4710 }
6f550484
TY		 4711 addr = dtable.base + index * 8;
4712 ret = kvm_read_guest_virt_system(addr, seg_desc, sizeof(*seg_desc),
4713 vcpu, &err);
4714 if (ret == X86EMUL_PROPAGATE_FAULT)
4715 kvm_inject_page_fault(vcpu, addr, err);
4716
4717 return ret;
37817f29
IE		 4718}
4719
4720/* allowed just for 8 bytes segments */
4721static int save_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
4722 struct desc_struct *seg_desc)
4723{
89a27f4d 4724 struct desc_ptr dtable;
37817f29
IE		 4725 u16 index = selector >> 3;
4726
b8222ad2 4727 get_segment_descriptor_dtable(vcpu, selector, &dtable);
37817f29 4728
89a27f4d 4729 if (dtable.size < index * 8 + 7)
37817f29 4730 return 1;
89a27f4d 4731 return kvm_write_guest_virt(dtable.address + index*8, seg_desc, sizeof(*seg_desc), vcpu, NULL);
1871c602
GN		 4732}
4733
4734static gpa_t get_tss_base_addr_write(struct kvm_vcpu *vcpu,
4735 struct desc_struct *seg_desc)
4736{
4737 u32 base_addr = get_desc_base(seg_desc);
4738
4739 return kvm_mmu_gva_to_gpa_write(vcpu, base_addr, NULL);
37817f29
IE		 4740}
4741
1871c602 4742static gpa_t get_tss_base_addr_read(struct kvm_vcpu *vcpu,
37817f29
IE		 4743 struct desc_struct *seg_desc)
4744{
46a359e7 4745 u32 base_addr = get_desc_base(seg_desc);
37817f29 4746
1871c602 4747 return kvm_mmu_gva_to_gpa_read(vcpu, base_addr, NULL);
37817f29
IE		 4748}
4749
37817f29
IE		 4750static u16 get_segment_selector(struct kvm_vcpu *vcpu, int seg)
4751{
4752 struct kvm_segment kvm_seg;
4753
3e6e0aab 4754 kvm_get_segment(vcpu, &kvm_seg, seg);
37817f29
IE		 4755 return kvm_seg.selector;
4756}
4757
2259e3a7 4758static int kvm_load_realmode_segment(struct kvm_vcpu *vcpu, u16 selector, int seg)
f4bbd9aa
AK		 4759{
4760 struct kvm_segment segvar = {
4761 .base = selector << 4,
4762 .limit = 0xffff,
4763 .selector = selector,
4764 .type = 3,
4765 .present = 1,
4766 .dpl = 3,
4767 .db = 0,
4768 .s = 1,
4769 .l = 0,
4770 .g = 0,
4771 .avl = 0,
4772 .unusable = 0,
4773 };
4774 kvm_x86_ops->set_segment(vcpu, &segvar, seg);
c697518a 4775 return X86EMUL_CONTINUE;
f4bbd9aa
AK		 4776}
4777
c0c7c04b
AL		 4778static int is_vm86_segment(struct kvm_vcpu *vcpu, int seg)
4779{
4780 return (seg != VCPU_SREG_LDTR) &&
4781 (seg != VCPU_SREG_TR) &&
91586a3b 4782 (kvm_get_rflags(vcpu) & X86_EFLAGS_VM);
c0c7c04b
AL		 4783}
4784
c697518a 4785int kvm_load_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector, int seg)
37817f29
IE		 4786{
4787 struct kvm_segment kvm_seg;
e01c2426 4788 struct desc_struct seg_desc;
c697518a
GN		 4789 u8 dpl, rpl, cpl;
4790 unsigned err_vec = GP_VECTOR;
4791 u32 err_code = 0;
4792 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
4793 int ret;
37817f29 4794
3eeb3288 4795 if (is_vm86_segment(vcpu, seg) || !is_protmode(vcpu))
f4bbd9aa 4796 return kvm_load_realmode_segment(vcpu, selector, seg);
e01c2426 4797
c697518a
GN		 4798 /* NULL selector is not valid for TR, CS and SS */
4799 if ((seg == VCPU_SREG_CS || seg == VCPU_SREG_SS || seg == VCPU_SREG_TR)
4800 && null_selector)
4801 goto exception;
4802
4803 /* TR should be in GDT only */
4804 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
4805 goto exception;
4806
4807 ret = load_guest_segment_descriptor(vcpu, selector, &seg_desc);
4808 if (ret)
4809 return ret;
4810
e01c2426 4811 seg_desct_to_kvm_desct(&seg_desc, selector, &kvm_seg);
cb84b55f 4812
c697518a
GN		 4813 if (null_selector) { /* for NULL selector skip all following checks */
4814 kvm_seg.unusable = 1;
4815 goto load;
4816 }
37817f29 4817
c697518a
GN		 4818 err_code = selector & 0xfffc;
4819 err_vec = GP_VECTOR;
37817f29 4820
c697518a
GN		 4821 /* can't load system descriptor into segment selecor */
4822 if (seg <= VCPU_SREG_GS && !kvm_seg.s)
4823 goto exception;
4824
4825 if (!kvm_seg.present) {
4826 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
4827 goto exception;
4828 }
4829
4830 rpl = selector & 3;
4831 dpl = kvm_seg.dpl;
4832 cpl = kvm_x86_ops->get_cpl(vcpu);
4833
4834 switch (seg) {
4835 case VCPU_SREG_SS:
4836 /*
4837 * segment is not a writable data segment or segment
4838 * selector's RPL != CPL or segment selector's RPL != CPL
4839 */
4840 if (rpl != cpl || (kvm_seg.type & 0xa) != 0x2 || dpl != cpl)
4841 goto exception;
4842 break;
4843 case VCPU_SREG_CS:
4844 if (!(kvm_seg.type & 8))
4845 goto exception;
4846
4847 if (kvm_seg.type & 4) {
4848 /* conforming */
4849 if (dpl > cpl)
4850 goto exception;
4851 } else {
4852 /* nonconforming */
4853 if (rpl > cpl || dpl != cpl)
4854 goto exception;
4855 }
4856 /* CS(RPL) <- CPL */
4857 selector = (selector & 0xfffc) | cpl;
4858 break;
4859 case VCPU_SREG_TR:
4860 if (kvm_seg.s || (kvm_seg.type != 1 && kvm_seg.type != 9))
4861 goto exception;
4862 break;
4863 case VCPU_SREG_LDTR:
4864 if (kvm_seg.s || kvm_seg.type != 2)
4865 goto exception;
4866 break;
4867 default: /* DS, ES, FS, or GS */
4868 /*
4869 * segment is not a data or readable code segment or
4870 * ((segment is a data or nonconforming code segment)
4871 * and (both RPL and CPL > DPL))
4872 */
4873 if ((kvm_seg.type & 0xa) == 0x8 ||
4874 (((kvm_seg.type & 0xc) != 0xc) && (rpl > dpl && cpl > dpl)))
4875 goto exception;
4876 break;
4877 }
4878
4879 if (!kvm_seg.unusable && kvm_seg.s) {
e01c2426 4880 /* mark segment as accessed */
c697518a 4881 kvm_seg.type |= 1;
e01c2426
GN		 4882 seg_desc.type |= 1;
4883 save_guest_segment_descriptor(vcpu, selector, &seg_desc);
4884 }
c697518a
GN		 4885load:
4886 kvm_set_segment(vcpu, &kvm_seg, seg);
4887 return X86EMUL_CONTINUE;
4888exception:
4889 kvm_queue_exception_e(vcpu, err_vec, err_code);
4890 return X86EMUL_PROPAGATE_FAULT;
37817f29
IE		 4891}
4892
4893static void save_state_to_tss32(struct kvm_vcpu *vcpu,
4894 struct tss_segment_32 *tss)
4895{
4896 tss->cr3 = vcpu->arch.cr3;
5fdbf976 4897 tss->eip = kvm_rip_read(vcpu);
91586a3b 4898 tss->eflags = kvm_get_rflags(vcpu);
5fdbf976
MT		 4899 tss->eax = kvm_register_read(vcpu, VCPU_REGS_RAX);
4900 tss->ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
4901 tss->edx = kvm_register_read(vcpu, VCPU_REGS_RDX);
4902 tss->ebx = kvm_register_read(vcpu, VCPU_REGS_RBX);
4903 tss->esp = kvm_register_read(vcpu, VCPU_REGS_RSP);
4904 tss->ebp = kvm_register_read(vcpu, VCPU_REGS_RBP);
4905 tss->esi = kvm_register_read(vcpu, VCPU_REGS_RSI);
4906 tss->edi = kvm_register_read(vcpu, VCPU_REGS_RDI);
37817f29
IE		 4907 tss->es = get_segment_selector(vcpu, VCPU_SREG_ES);
4908 tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS);
4909 tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS);
4910 tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS);
4911 tss->fs = get_segment_selector(vcpu, VCPU_SREG_FS);
4912 tss->gs = get_segment_selector(vcpu, VCPU_SREG_GS);
4913 tss->ldt_selector = get_segment_selector(vcpu, VCPU_SREG_LDTR);
37817f29
IE		 4914}
4915
c697518a
GN		 4916static void kvm_load_segment_selector(struct kvm_vcpu *vcpu, u16 sel, int seg)
4917{
4918 struct kvm_segment kvm_seg;
4919 kvm_get_segment(vcpu, &kvm_seg, seg);
4920 kvm_seg.selector = sel;
4921 kvm_set_segment(vcpu, &kvm_seg, seg);
4922}
4923
37817f29
IE		 4924static int load_state_from_tss32(struct kvm_vcpu *vcpu,
4925 struct tss_segment_32 *tss)
4926{
4927 kvm_set_cr3(vcpu, tss->cr3);
4928
5fdbf976 4929 kvm_rip_write(vcpu, tss->eip);
91586a3b 4930 kvm_set_rflags(vcpu, tss->eflags | 2);
37817f29 4931
5fdbf976
MT		 4932 kvm_register_write(vcpu, VCPU_REGS_RAX, tss->eax);
4933 kvm_register_write(vcpu, VCPU_REGS_RCX, tss->ecx);
4934 kvm_register_write(vcpu, VCPU_REGS_RDX, tss->edx);
4935 kvm_register_write(vcpu, VCPU_REGS_RBX, tss->ebx);
4936 kvm_register_write(vcpu, VCPU_REGS_RSP, tss->esp);
4937 kvm_register_write(vcpu, VCPU_REGS_RBP, tss->ebp);
4938 kvm_register_write(vcpu, VCPU_REGS_RSI, tss->esi);
4939 kvm_register_write(vcpu, VCPU_REGS_RDI, tss->edi);
37817f29 4940
c697518a
GN		 4941 /*
4942 * SDM says that segment selectors are loaded before segment
4943 * descriptors
4944 */
4945 kvm_load_segment_selector(vcpu, tss->ldt_selector, VCPU_SREG_LDTR);
4946 kvm_load_segment_selector(vcpu, tss->es, VCPU_SREG_ES);
4947 kvm_load_segment_selector(vcpu, tss->cs, VCPU_SREG_CS);
4948 kvm_load_segment_selector(vcpu, tss->ss, VCPU_SREG_SS);
4949 kvm_load_segment_selector(vcpu, tss->ds, VCPU_SREG_DS);
4950 kvm_load_segment_selector(vcpu, tss->fs, VCPU_SREG_FS);
4951 kvm_load_segment_selector(vcpu, tss->gs, VCPU_SREG_GS);
4952
4953 /*
4954 * Now load segment descriptors. If fault happenes at this stage
4955 * it is handled in a context of new task
4956 */
4957 if (kvm_load_segment_descriptor(vcpu, tss->ldt_selector, VCPU_SREG_LDTR))
37817f29
IE		 4958 return 1;
4959
c697518a 4960 if (kvm_load_segment_descriptor(vcpu, tss->es, VCPU_SREG_ES))
37817f29
IE		 4961 return 1;
4962
c697518a 4963 if (kvm_load_segment_descriptor(vcpu, tss->cs, VCPU_SREG_CS))
37817f29
IE		 4964 return 1;
4965
c697518a 4966 if (kvm_load_segment_descriptor(vcpu, tss->ss, VCPU_SREG_SS))
37817f29
IE		 4967 return 1;
4968
c697518a 4969 if (kvm_load_segment_descriptor(vcpu, tss->ds, VCPU_SREG_DS))
37817f29
IE		 4970 return 1;
4971
c697518a 4972 if (kvm_load_segment_descriptor(vcpu, tss->fs, VCPU_SREG_FS))
37817f29
IE		 4973 return 1;
4974
c697518a 4975 if (kvm_load_segment_descriptor(vcpu, tss->gs, VCPU_SREG_GS))
37817f29
IE		 4976 return 1;
4977 return 0;
4978}
4979
4980static void save_state_to_tss16(struct kvm_vcpu *vcpu,
4981 struct tss_segment_16 *tss)
4982{
5fdbf976 4983 tss->ip = kvm_rip_read(vcpu);
91586a3b 4984 tss->flag = kvm_get_rflags(vcpu);
5fdbf976
MT		 4985 tss->ax = kvm_register_read(vcpu, VCPU_REGS_RAX);
4986 tss->cx = kvm_register_read(vcpu, VCPU_REGS_RCX);
4987 tss->dx = kvm_register_read(vcpu, VCPU_REGS_RDX);
4988 tss->bx = kvm_register_read(vcpu, VCPU_REGS_RBX);
4989 tss->sp = kvm_register_read(vcpu, VCPU_REGS_RSP);
4990 tss->bp = kvm_register_read(vcpu, VCPU_REGS_RBP);
4991 tss->si = kvm_register_read(vcpu, VCPU_REGS_RSI);
4992 tss->di = kvm_register_read(vcpu, VCPU_REGS_RDI);
37817f29
IE		 4993
4994 tss->es = get_segment_selector(vcpu, VCPU_SREG_ES);
4995 tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS);
4996 tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS);
4997 tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS);
4998 tss->ldt = get_segment_selector(vcpu, VCPU_SREG_LDTR);
37817f29
IE		 4999}
5000
5001static int load_state_from_tss16(struct kvm_vcpu *vcpu,
5002 struct tss_segment_16 *tss)
5003{
5fdbf976 5004 kvm_rip_write(vcpu, tss->ip);
91586a3b 5005 kvm_set_rflags(vcpu, tss->flag | 2);
5fdbf976
MT		 5006 kvm_register_write(vcpu, VCPU_REGS_RAX, tss->ax);
5007 kvm_register_write(vcpu, VCPU_REGS_RCX, tss->cx);
5008 kvm_register_write(vcpu, VCPU_REGS_RDX, tss->dx);
5009 kvm_register_write(vcpu, VCPU_REGS_RBX, tss->bx);
5010 kvm_register_write(vcpu, VCPU_REGS_RSP, tss->sp);
5011 kvm_register_write(vcpu, VCPU_REGS_RBP, tss->bp);
5012 kvm_register_write(vcpu, VCPU_REGS_RSI, tss->si);
5013 kvm_register_write(vcpu, VCPU_REGS_RDI, tss->di);
37817f29 5014
c697518a
GN		 5015 /*
5016 * SDM says that segment selectors are loaded before segment
5017 * descriptors
5018 */
5019 kvm_load_segment_selector(vcpu, tss->ldt, VCPU_SREG_LDTR);
5020 kvm_load_segment_selector(vcpu, tss->es, VCPU_SREG_ES);
5021 kvm_load_segment_selector(vcpu, tss->cs, VCPU_SREG_CS);
5022 kvm_load_segment_selector(vcpu, tss->ss, VCPU_SREG_SS);
5023 kvm_load_segment_selector(vcpu, tss->ds, VCPU_SREG_DS);
5024
5025 /*
5026 * Now load segment descriptors. If fault happenes at this stage
5027 * it is handled in a context of new task
5028 */
5029 if (kvm_load_segment_descriptor(vcpu, tss->ldt, VCPU_SREG_LDTR))
37817f29
IE		 5030 return 1;
5031
c697518a 5032 if (kvm_load_segment_descriptor(vcpu, tss->es, VCPU_SREG_ES))
37817f29
IE		 5033 return 1;
5034
c697518a 5035 if (kvm_load_segment_descriptor(vcpu, tss->cs, VCPU_SREG_CS))
37817f29
IE		 5036 return 1;
5037
c697518a 5038 if (kvm_load_segment_descriptor(vcpu, tss->ss, VCPU_SREG_SS))
37817f29
IE		 5039 return 1;
5040
c697518a 5041 if (kvm_load_segment_descriptor(vcpu, tss->ds, VCPU_SREG_DS))
37817f29
IE		 5042 return 1;
5043 return 0;
5044}
5045
8b2cf73c 5046static int kvm_task_switch_16(struct kvm_vcpu *vcpu, u16 tss_selector,
b237ac37
GN		 5047 u16 old_tss_sel, u32 old_tss_base,
5048 struct desc_struct *nseg_desc)
37817f29
IE		 5049{
5050 struct tss_segment_16 tss_segment_16;
5051 int ret = 0;
5052
34198bf8
MT		 5053 if (kvm_read_guest(vcpu->kvm, old_tss_base, &tss_segment_16,
5054 sizeof tss_segment_16))
37817f29
IE		 5055 goto out;
5056
5057 save_state_to_tss16(vcpu, &tss_segment_16);
37817f29 5058
34198bf8
MT		 5059 if (kvm_write_guest(vcpu->kvm, old_tss_base, &tss_segment_16,
5060 sizeof tss_segment_16))
37817f29 5061 goto out;
34198bf8 5062
1871c602 5063 if (kvm_read_guest(vcpu->kvm, get_tss_base_addr_read(vcpu, nseg_desc),
34198bf8
MT		 5064 &tss_segment_16, sizeof tss_segment_16))
5065 goto out;
5066
b237ac37
GN		 5067 if (old_tss_sel != 0xffff) {
5068 tss_segment_16.prev_task_link = old_tss_sel;
5069
5070 if (kvm_write_guest(vcpu->kvm,
1871c602 5071 get_tss_base_addr_write(vcpu, nseg_desc),
b237ac37
GN		 5072 &tss_segment_16.prev_task_link,
5073 sizeof tss_segment_16.prev_task_link))
5074 goto out;
5075 }
5076
37817f29
IE		 5077 if (load_state_from_tss16(vcpu, &tss_segment_16))
5078 goto out;
5079
5080 ret = 1;
5081out:
5082 return ret;
5083}
5084
8b2cf73c 5085static int kvm_task_switch_32(struct kvm_vcpu *vcpu, u16 tss_selector,
b237ac37 5086 u16 old_tss_sel, u32 old_tss_base,
37817f29
IE		 5087 struct desc_struct *nseg_desc)
5088{
5089 struct tss_segment_32 tss_segment_32;
5090 int ret = 0;
5091
34198bf8
MT		 5092 if (kvm_read_guest(vcpu->kvm, old_tss_base, &tss_segment_32,
5093 sizeof tss_segment_32))
37817f29
IE		 5094 goto out;
5095
5096 save_state_to_tss32(vcpu, &tss_segment_32);
37817f29 5097
34198bf8
MT		 5098 if (kvm_write_guest(vcpu->kvm, old_tss_base, &tss_segment_32,
5099 sizeof tss_segment_32))
5100 goto out;
5101
1871c602 5102 if (kvm_read_guest(vcpu->kvm, get_tss_base_addr_read(vcpu, nseg_desc),
34198bf8 5103 &tss_segment_32, sizeof tss_segment_32))
37817f29 5104 goto out;
34198bf8 5105
b237ac37
GN		 5106 if (old_tss_sel != 0xffff) {
5107 tss_segment_32.prev_task_link = old_tss_sel;
5108
5109 if (kvm_write_guest(vcpu->kvm,
1871c602 5110 get_tss_base_addr_write(vcpu, nseg_desc),
b237ac37
GN		 5111 &tss_segment_32.prev_task_link,
5112 sizeof tss_segment_32.prev_task_link))
5113 goto out;
5114 }
5115
37817f29
IE		 5116 if (load_state_from_tss32(vcpu, &tss_segment_32))
5117 goto out;
5118
5119 ret = 1;
5120out:
5121 return ret;
5122}
5123
5124int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason)
5125{
5126 struct kvm_segment tr_seg;
5127 struct desc_struct cseg_desc;
5128 struct desc_struct nseg_desc;
5129 int ret = 0;
34198bf8
MT		 5130 u32 old_tss_base = get_segment_base(vcpu, VCPU_SREG_TR);
5131 u16 old_tss_sel = get_segment_selector(vcpu, VCPU_SREG_TR);
e8861cfe 5132 u32 desc_limit;
37817f29 5133
1871c602 5134 old_tss_base = kvm_mmu_gva_to_gpa_write(vcpu, old_tss_base, NULL);
37817f29 5135
34198bf8
MT		 5136 /* FIXME: Handle errors. Failure to read either TSS or their
5137 * descriptors should generate a pagefault.
5138 */
37817f29
IE		 5139 if (load_guest_segment_descriptor(vcpu, tss_selector, &nseg_desc))
5140 goto out;
5141
34198bf8 5142 if (load_guest_segment_descriptor(vcpu, old_tss_sel, &cseg_desc))
37817f29
IE		 5143 goto out;
5144
37817f29
IE		 5145 if (reason != TASK_SWITCH_IRET) {
5146 int cpl;
5147
5148 cpl = kvm_x86_ops->get_cpl(vcpu);
5149 if ((tss_selector & 3) > nseg_desc.dpl || cpl > nseg_desc.dpl) {
5150 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
5151 return 1;
5152 }
5153 }
5154
e8861cfe
JK		 5155 desc_limit = get_desc_limit(&nseg_desc);
5156 if (!nseg_desc.p ||
5157 ((desc_limit < 0x67 && (nseg_desc.type & 8)) ||
5158 desc_limit < 0x2b)) {
37817f29
IE		 5159 kvm_queue_exception_e(vcpu, TS_VECTOR, tss_selector & 0xfffc);
5160 return 1;
5161 }
5162
5163 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
3fe913e7 5164 cseg_desc.type &= ~(1 << 1); //clear the B flag
34198bf8 5165 save_guest_segment_descriptor(vcpu, old_tss_sel, &cseg_desc);
37817f29
IE		 5166 }
5167
5168 if (reason == TASK_SWITCH_IRET) {
91586a3b
JK		 5169 u32 eflags = kvm_get_rflags(vcpu);
5170 kvm_set_rflags(vcpu, eflags & ~X86_EFLAGS_NT);
37817f29
IE		 5171 }
5172
b237ac37
GN		 5173 /* set back link to prev task only if NT bit is set in eflags
5174 note that old_tss_sel is not used afetr this point */
5175 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
5176 old_tss_sel = 0xffff;
5177
37817f29 5178 if (nseg_desc.type & 8)
b237ac37
GN		 5179 ret = kvm_task_switch_32(vcpu, tss_selector, old_tss_sel,
5180 old_tss_base, &nseg_desc);
37817f29 5181 else
b237ac37
GN		 5182 ret = kvm_task_switch_16(vcpu, tss_selector, old_tss_sel,
5183 old_tss_base, &nseg_desc);
37817f29
IE		 5184
5185 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE) {
91586a3b
JK		 5186 u32 eflags = kvm_get_rflags(vcpu);
5187 kvm_set_rflags(vcpu, eflags | X86_EFLAGS_NT);
37817f29
IE		 5188 }
5189
5190 if (reason != TASK_SWITCH_IRET) {
3fe913e7 5191 nseg_desc.type |= (1 << 1);
37817f29
IE		 5192 save_guest_segment_descriptor(vcpu, tss_selector,
5193 &nseg_desc);
5194 }
5195
4d4ec087 5196 kvm_x86_ops->set_cr0(vcpu, kvm_read_cr0(vcpu) | X86_CR0_TS);
37817f29
IE		 5197 seg_desct_to_kvm_desct(&nseg_desc, tss_selector, &tr_seg);
5198 tr_seg.type = 11;
3e6e0aab 5199 kvm_set_segment(vcpu, &tr_seg, VCPU_SREG_TR);
37817f29 5200out:
37817f29
IE		 5201 return ret;
5202}
5203EXPORT_SYMBOL_GPL(kvm_task_switch);
5204
b6c7a5dc
HB		 5205int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
5206 struct kvm_sregs *sregs)
5207{
5208 int mmu_reset_needed = 0;
923c61bb 5209 int pending_vec, max_bits;
89a27f4d 5210 struct desc_ptr dt;
b6c7a5dc
HB		 5211
5212 vcpu_load(vcpu);
5213
89a27f4d
GN		 5214 dt.size = sregs->idt.limit;
5215 dt.address = sregs->idt.base;
b6c7a5dc 5216 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 5217 dt.size = sregs->gdt.limit;
5218 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 5219 kvm_x86_ops->set_gdt(vcpu, &dt);
5220
ad312c7c
ZX		 5221 vcpu->arch.cr2 = sregs->cr2;
5222 mmu_reset_needed |= vcpu->arch.cr3 != sregs->cr3;
dc7e795e 5223 vcpu->arch.cr3 = sregs->cr3;
b6c7a5dc 5224
2d3ad1f4 5225 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 5226
f6801dff 5227 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 5228 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 5229 kvm_set_apic_base(vcpu, sregs->apic_base);
5230
4d4ec087 5231 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 5232 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 5233 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 5234
fc78f519 5235 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 5236 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
7c93be44 5237 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
ad312c7c 5238 load_pdptrs(vcpu, vcpu->arch.cr3);
7c93be44
MT		 5239 mmu_reset_needed = 1;
5240 }
b6c7a5dc
HB		 5241
5242 if (mmu_reset_needed)
5243 kvm_mmu_reset_context(vcpu);
5244
923c61bb
GN		 5245 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
5246 pending_vec = find_first_bit(
5247 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
5248 if (pending_vec < max_bits) {
66fd3f7f 5249 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb
GN		 5250 pr_debug("Set back pending irq %d\n", pending_vec);
5251 if (irqchip_in_kernel(vcpu->kvm))
5252 kvm_pic_clear_isr_ack(vcpu->kvm);
b6c7a5dc
HB		 5253 }
5254
3e6e0aab
GT		 5255 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5256 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5257 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5258 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5259 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5260 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 5261
3e6e0aab
GT		 5262 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5263 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 5264
5f0269f5
ME		 5265 update_cr8_intercept(vcpu);
5266
9c3e4aab 5267 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 5268 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 5269 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 5270 !is_protmode(vcpu))
9c3e4aab
MT		 5271 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
5272
b6c7a5dc
HB		 5273 vcpu_put(vcpu);
5274
5275 return 0;
5276}
5277
d0bfb940
JK		 5278int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
5279 struct kvm_guest_debug *dbg)
b6c7a5dc 5280{
355be0b9 5281 unsigned long rflags;
ae675ef0 5282 int i, r;
b6c7a5dc
HB		 5283
5284 vcpu_load(vcpu);
5285
4f926bf2
JK		 5286 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
5287 r = -EBUSY;
5288 if (vcpu->arch.exception.pending)
5289 goto unlock_out;
5290 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
5291 kvm_queue_exception(vcpu, DB_VECTOR);
5292 else
5293 kvm_queue_exception(vcpu, BP_VECTOR);
5294 }
5295
91586a3b
JK		 5296 /*
5297 * Read rflags as long as potentially injected trace flags are still
5298 * filtered out.
5299 */
5300 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 5301
5302 vcpu->guest_debug = dbg->control;
5303 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
5304 vcpu->guest_debug = 0;
5305
5306 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 5307 for (i = 0; i < KVM_NR_DB_REGS; ++i)
5308 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
5309 vcpu->arch.switch_db_regs =
5310 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
5311 } else {
5312 for (i = 0; i < KVM_NR_DB_REGS; i++)
5313 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
5314 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
5315 }
5316
94fe45da
JK		 5317 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
5318 vcpu->arch.singlestep_cs =
5319 get_segment_selector(vcpu, VCPU_SREG_CS);
5320 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu);
5321 }
5322
91586a3b
JK		 5323 /*
5324 * Trigger an rflags update that will inject or remove the trace
5325 * flags.
5326 */
5327 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 5328
355be0b9 5329 kvm_x86_ops->set_guest_debug(vcpu, dbg);
b6c7a5dc 5330
4f926bf2 5331 r = 0;
d0bfb940 5332
4f926bf2 5333unlock_out:
b6c7a5dc
HB		 5334 vcpu_put(vcpu);
5335
5336 return r;
5337}
5338
d0752060
HB		 5339/*
5340 * fxsave fpu state. Taken from x86_64/processor.h. To be killed when
5341 * we have asm/x86/processor.h
5342 */
5343struct fxsave {
5344 u16 cwd;
5345 u16 swd;
5346 u16 twd;
5347 u16 fop;
5348 u64 rip;
5349 u64 rdp;
5350 u32 mxcsr;
5351 u32 mxcsr_mask;
5352 u32 st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
5353#ifdef CONFIG_X86_64
5354 u32 xmm_space[64]; /* 16*16 bytes for each XMM-reg = 256 bytes */
5355#else
5356 u32 xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */
5357#endif
5358};
5359
8b006791
ZX		 5360/*
5361 * Translate a guest virtual address to a guest physical address.
5362 */
5363int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
5364 struct kvm_translation *tr)
5365{
5366 unsigned long vaddr = tr->linear_address;
5367 gpa_t gpa;
f656ce01 5368 int idx;
8b006791
ZX		 5369
5370 vcpu_load(vcpu);
f656ce01 5371 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 5372 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 5373 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 5374 tr->physical_address = gpa;
5375 tr->valid = gpa != UNMAPPED_GVA;
5376 tr->writeable = 1;
5377 tr->usermode = 0;
8b006791
ZX		 5378 vcpu_put(vcpu);
5379
5380 return 0;
5381}
5382
d0752060
HB		 5383int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5384{
ad312c7c 5385 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060
HB		 5386
5387 vcpu_load(vcpu);
5388
5389 memcpy(fpu->fpr, fxsave->st_space, 128);
5390 fpu->fcw = fxsave->cwd;
5391 fpu->fsw = fxsave->swd;
5392 fpu->ftwx = fxsave->twd;
5393 fpu->last_opcode = fxsave->fop;
5394 fpu->last_ip = fxsave->rip;
5395 fpu->last_dp = fxsave->rdp;
5396 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
5397
5398 vcpu_put(vcpu);
5399
5400 return 0;
5401}
5402
5403int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5404{
ad312c7c 5405 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060
HB		 5406
5407 vcpu_load(vcpu);
5408
5409 memcpy(fxsave->st_space, fpu->fpr, 128);
5410 fxsave->cwd = fpu->fcw;
5411 fxsave->swd = fpu->fsw;
5412 fxsave->twd = fpu->ftwx;
5413 fxsave->fop = fpu->last_opcode;
5414 fxsave->rip = fpu->last_ip;
5415 fxsave->rdp = fpu->last_dp;
5416 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
5417
5418 vcpu_put(vcpu);
5419
5420 return 0;
5421}
5422
5423void fx_init(struct kvm_vcpu *vcpu)
5424{
5425 unsigned after_mxcsr_mask;
5426
bc1a34f1
AA		 5427 /*
5428 * Touch the fpu the first time in non atomic context as if
5429 * this is the first fpu instruction the exception handler
5430 * will fire before the instruction returns and it'll have to
5431 * allocate ram with GFP_KERNEL.
5432 */
5433 if (!used_math())
d6e88aec 5434 kvm_fx_save(&vcpu->arch.host_fx_image);
bc1a34f1 5435
d0752060
HB		 5436 /* Initialize guest FPU by resetting ours and saving into guest's */
5437 preempt_disable();
d6e88aec
AK		 5438 kvm_fx_save(&vcpu->arch.host_fx_image);
5439 kvm_fx_finit();
5440 kvm_fx_save(&vcpu->arch.guest_fx_image);
5441 kvm_fx_restore(&vcpu->arch.host_fx_image);
d0752060
HB		 5442 preempt_enable();
5443
ad312c7c 5444 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 5445 after_mxcsr_mask = offsetof(struct i387_fxsave_struct, st_space);
ad312c7c
ZX		 5446 vcpu->arch.guest_fx_image.mxcsr = 0x1f80;
5447 memset((void *)&vcpu->arch.guest_fx_image + after_mxcsr_mask,
d0752060
HB		 5448 0, sizeof(struct i387_fxsave_struct) - after_mxcsr_mask);
5449}
5450EXPORT_SYMBOL_GPL(fx_init);
5451
5452void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
5453{
2608d7a1 5454 if (vcpu->guest_fpu_loaded)
d0752060
HB		 5455 return;
5456
5457 vcpu->guest_fpu_loaded = 1;
d6e88aec
AK		 5458 kvm_fx_save(&vcpu->arch.host_fx_image);
5459 kvm_fx_restore(&vcpu->arch.guest_fx_image);
0c04851c 5460 trace_kvm_fpu(1);
d0752060 5461}
d0752060
HB		 5462
5463void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
5464{
5465 if (!vcpu->guest_fpu_loaded)
5466 return;
5467
5468 vcpu->guest_fpu_loaded = 0;
d6e88aec
AK		 5469 kvm_fx_save(&vcpu->arch.guest_fx_image);
5470 kvm_fx_restore(&vcpu->arch.host_fx_image);
f096ed85 5471 ++vcpu->stat.fpu_reload;
02daab21 5472 set_bit(KVM_REQ_DEACTIVATE_FPU, &vcpu->requests);
0c04851c 5473 trace_kvm_fpu(0);
d0752060 5474}
e9b11c17
ZX		 5475
5476void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
5477{
7f1ea208
JR		 5478 if (vcpu->arch.time_page) {
5479 kvm_release_page_dirty(vcpu->arch.time_page);
5480 vcpu->arch.time_page = NULL;
5481 }
5482
e9b11c17
ZX		 5483 kvm_x86_ops->vcpu_free(vcpu);
5484}
5485
5486struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
5487 unsigned int id)
5488{
26e5215f
AK		 5489 return kvm_x86_ops->vcpu_create(kvm, id);
5490}
e9b11c17 5491
26e5215f
AK		 5492int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
5493{
5494 int r;
e9b11c17
ZX		 5495
5496 /* We do fxsave: this must be aligned. */
ad312c7c 5497 BUG_ON((unsigned long)&vcpu->arch.host_fx_image & 0xF);
e9b11c17 5498
0bed3b56 5499 vcpu->arch.mtrr_state.have_fixed = 1;
e9b11c17
ZX		 5500 vcpu_load(vcpu);
5501 r = kvm_arch_vcpu_reset(vcpu);
5502 if (r == 0)
5503 r = kvm_mmu_setup(vcpu);
5504 vcpu_put(vcpu);
5505 if (r < 0)
5506 goto free_vcpu;
5507
26e5215f 5508 return 0;
e9b11c17
ZX		 5509free_vcpu:
5510 kvm_x86_ops->vcpu_free(vcpu);
26e5215f 5511 return r;
e9b11c17
ZX		 5512}
5513
d40ccc62 5514void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17
ZX		 5515{
5516 vcpu_load(vcpu);
5517 kvm_mmu_unload(vcpu);
5518 vcpu_put(vcpu);
5519
5520 kvm_x86_ops->vcpu_free(vcpu);
5521}
5522
5523int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
5524{
448fa4a9
JK		 5525 vcpu->arch.nmi_pending = false;
5526 vcpu->arch.nmi_injected = false;
5527
42dbaa5a
JK		 5528 vcpu->arch.switch_db_regs = 0;
5529 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
5530 vcpu->arch.dr6 = DR6_FIXED_1;
5531 vcpu->arch.dr7 = DR7_FIXED_1;
5532
e9b11c17
ZX		 5533 return kvm_x86_ops->vcpu_reset(vcpu);
5534}
5535
10474ae8 5536int kvm_arch_hardware_enable(void *garbage)
e9b11c17 5537{
0cca7907
ZA		 5538 /*
5539 * Since this may be called from a hotplug notifcation,
5540 * we can't get the CPU frequency directly.
5541 */
5542 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
5543 int cpu = raw_smp_processor_id();
5544 per_cpu(cpu_tsc_khz, cpu) = 0;
5545 }
18863bdd
AK		 5546
5547 kvm_shared_msr_cpu_online();
5548
10474ae8 5549 return kvm_x86_ops->hardware_enable(garbage);
e9b11c17
ZX		 5550}
5551
5552void kvm_arch_hardware_disable(void *garbage)
5553{
5554 kvm_x86_ops->hardware_disable(garbage);
3548bab5 5555 drop_user_return_notifiers(garbage);
e9b11c17
ZX		 5556}
5557
5558int kvm_arch_hardware_setup(void)
5559{
5560 return kvm_x86_ops->hardware_setup();
5561}
5562
5563void kvm_arch_hardware_unsetup(void)
5564{
5565 kvm_x86_ops->hardware_unsetup();
5566}
5567
5568void kvm_arch_check_processor_compat(void *rtn)
5569{
5570 kvm_x86_ops->check_processor_compatibility(rtn);
5571}
5572
5573int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
5574{
5575 struct page *page;
5576 struct kvm *kvm;
5577 int r;
5578
5579 BUG_ON(vcpu->kvm == NULL);
5580 kvm = vcpu->kvm;
5581
ad312c7c 5582 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
c5af89b6 5583 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 5584 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 5585 else
a4535290 5586 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 5587
5588 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
5589 if (!page) {
5590 r = -ENOMEM;
5591 goto fail;
5592 }
ad312c7c 5593 vcpu->arch.pio_data = page_address(page);
e9b11c17
ZX		 5594
5595 r = kvm_mmu_create(vcpu);
5596 if (r < 0)
5597 goto fail_free_pio_data;
5598
5599 if (irqchip_in_kernel(kvm)) {
5600 r = kvm_create_lapic(vcpu);
5601 if (r < 0)
5602 goto fail_mmu_destroy;
5603 }
5604
890ca9ae
HY		 5605 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
5606 GFP_KERNEL);
5607 if (!vcpu->arch.mce_banks) {
5608 r = -ENOMEM;
443c39bc 5609 goto fail_free_lapic;
890ca9ae
HY		 5610 }
5611 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
5612
e9b11c17 5613 return 0;
443c39bc
WY		 5614fail_free_lapic:
5615 kvm_free_lapic(vcpu);
e9b11c17
ZX		 5616fail_mmu_destroy:
5617 kvm_mmu_destroy(vcpu);
5618fail_free_pio_data:
ad312c7c 5619 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 5620fail:
5621 return r;
5622}
5623
5624void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
5625{
f656ce01
MT		 5626 int idx;
5627
36cb93fd 5628 kfree(vcpu->arch.mce_banks);
e9b11c17 5629 kvm_free_lapic(vcpu);
f656ce01 5630 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 5631 kvm_mmu_destroy(vcpu);
f656ce01 5632 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 5633 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17 5634}
d19a9cd2
ZX		 5635
5636struct kvm *kvm_arch_create_vm(void)
5637{
5638 struct kvm *kvm = kzalloc(sizeof(struct kvm), GFP_KERNEL);
5639
5640 if (!kvm)
5641 return ERR_PTR(-ENOMEM);
5642
fef9cce0
MT		 5643 kvm->arch.aliases = kzalloc(sizeof(struct kvm_mem_aliases), GFP_KERNEL);
5644 if (!kvm->arch.aliases) {
5645 kfree(kvm);
5646 return ERR_PTR(-ENOMEM);
5647 }
5648
f05e70ac 5649 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4d5c5d0f 5650 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2 5651
5550af4d
SY		 5652 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
5653 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
5654
53f658b3
MT		 5655 rdtscll(kvm->arch.vm_init_tsc);
5656
d19a9cd2
ZX		 5657 return kvm;
5658}
5659
5660static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
5661{
5662 vcpu_load(vcpu);
5663 kvm_mmu_unload(vcpu);
5664 vcpu_put(vcpu);
5665}
5666
5667static void kvm_free_vcpus(struct kvm *kvm)
5668{
5669 unsigned int i;
988a2cae 5670 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 5671
5672 /*
5673 * Unpin any mmu pages first.
5674 */
988a2cae
GN		 5675 kvm_for_each_vcpu(i, vcpu, kvm)
5676 kvm_unload_vcpu_mmu(vcpu);
5677 kvm_for_each_vcpu(i, vcpu, kvm)
5678 kvm_arch_vcpu_free(vcpu);
5679
5680 mutex_lock(&kvm->lock);
5681 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
5682 kvm->vcpus[i] = NULL;
d19a9cd2 5683
988a2cae
GN		 5684 atomic_set(&kvm->online_vcpus, 0);
5685 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 5686}
5687
ad8ba2cd
SY		 5688void kvm_arch_sync_events(struct kvm *kvm)
5689{
ba4cef31 5690 kvm_free_all_assigned_devices(kvm);
ad8ba2cd
SY		 5691}
5692
d19a9cd2
ZX		 5693void kvm_arch_destroy_vm(struct kvm *kvm)
5694{
6eb55818 5695 kvm_iommu_unmap_guest(kvm);
7837699f 5696 kvm_free_pit(kvm);
d7deeeb0
ZX		 5697 kfree(kvm->arch.vpic);
5698 kfree(kvm->arch.vioapic);
d19a9cd2
ZX		 5699 kvm_free_vcpus(kvm);
5700 kvm_free_physmem(kvm);
3d45830c
AK		 5701 if (kvm->arch.apic_access_page)
5702 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 5703 if (kvm->arch.ept_identity_pagetable)
5704 put_page(kvm->arch.ept_identity_pagetable);
64749204 5705 cleanup_srcu_struct(&kvm->srcu);
fef9cce0 5706 kfree(kvm->arch.aliases);
d19a9cd2
ZX		 5707 kfree(kvm);
5708}
0de10343 5709
f7784b8e
MT		 5710int kvm_arch_prepare_memory_region(struct kvm *kvm,
5711 struct kvm_memory_slot *memslot,
0de10343 5712 struct kvm_memory_slot old,
f7784b8e 5713 struct kvm_userspace_memory_region *mem,
0de10343
ZX		 5714 int user_alloc)
5715{
f7784b8e 5716 int npages = memslot->npages;
0de10343
ZX		 5717
5718 /*To keep backward compatibility with older userspace,
5719 *x86 needs to hanlde !user_alloc case.
5720 */
5721 if (!user_alloc) {
5722 if (npages && !old.rmap) {
604b38ac
AA		 5723 unsigned long userspace_addr;
5724
72dc67a6 5725 down_write(&current->mm->mmap_sem);
604b38ac
AA		 5726 userspace_addr = do_mmap(NULL, 0,
5727 npages * PAGE_SIZE,
5728 PROT_READ | PROT_WRITE,
acee3c04 5729 MAP_PRIVATE | MAP_ANONYMOUS,
604b38ac 5730 0);
72dc67a6 5731 up_write(&current->mm->mmap_sem);
0de10343 5732
604b38ac
AA		 5733 if (IS_ERR((void *)userspace_addr))
5734 return PTR_ERR((void *)userspace_addr);
5735
604b38ac 5736 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 5737 }
5738 }
5739
f7784b8e
MT		 5740
5741 return 0;
5742}
5743
5744void kvm_arch_commit_memory_region(struct kvm *kvm,
5745 struct kvm_userspace_memory_region *mem,
5746 struct kvm_memory_slot old,
5747 int user_alloc)
5748{
5749
5750 int npages = mem->memory_size >> PAGE_SHIFT;
5751
5752 if (!user_alloc && !old.user_alloc && old.rmap && !npages) {
5753 int ret;
5754
5755 down_write(&current->mm->mmap_sem);
5756 ret = do_munmap(current->mm, old.userspace_addr,
5757 old.npages * PAGE_SIZE);
5758 up_write(&current->mm->mmap_sem);
5759 if (ret < 0)
5760 printk(KERN_WARNING
5761 "kvm_vm_ioctl_set_memory_region: "
5762 "failed to munmap memory\n");
5763 }
5764
7c8a83b7 5765 spin_lock(&kvm->mmu_lock);
f05e70ac 5766 if (!kvm->arch.n_requested_mmu_pages) {
0de10343
ZX		 5767 unsigned int nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
5768 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
5769 }
5770
5771 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
7c8a83b7 5772 spin_unlock(&kvm->mmu_lock);
0de10343 5773}
1d737c8a 5774
34d4cb8f
MT		 5775void kvm_arch_flush_shadow(struct kvm *kvm)
5776{
5777 kvm_mmu_zap_all(kvm);
8986ecc0 5778 kvm_reload_remote_mmus(kvm);
34d4cb8f
MT		 5779}
5780
1d737c8a
ZX		 5781int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
5782{
a4535290 5783 return vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE
a1b37100
GN		 5784 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
5785 || vcpu->arch.nmi_pending ||
5786 (kvm_arch_interrupt_allowed(vcpu) &&
5787 kvm_cpu_has_interrupt(vcpu));
1d737c8a 5788}
5736199a 5789
5736199a
ZX		 5790void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
5791{
32f88400
MT		 5792 int me;
5793 int cpu = vcpu->cpu;
5736199a
ZX		 5794
5795 if (waitqueue_active(&vcpu->wq)) {
5796 wake_up_interruptible(&vcpu->wq);
5797 ++vcpu->stat.halt_wakeup;
5798 }
32f88400
MT		 5799
5800 me = get_cpu();
5801 if (cpu != me && (unsigned)cpu < nr_cpu_ids && cpu_online(cpu))
5802 if (!test_and_set_bit(KVM_REQ_KICK, &vcpu->requests))
5803 smp_send_reschedule(cpu);
e9571ed5 5804 put_cpu();
5736199a 5805}
78646121
GN		 5806
5807int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
5808{
5809 return kvm_x86_ops->interrupt_allowed(vcpu);
5810}
229456fc 5811
94fe45da
JK		 5812unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
5813{
5814 unsigned long rflags;
5815
5816 rflags = kvm_x86_ops->get_rflags(vcpu);
5817 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
5818 rflags &= ~(unsigned long)(X86_EFLAGS_TF | X86_EFLAGS_RF);
5819 return rflags;
5820}
5821EXPORT_SYMBOL_GPL(kvm_get_rflags);
5822
5823void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
5824{
5825 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
5826 vcpu->arch.singlestep_cs ==
5827 get_segment_selector(vcpu, VCPU_SREG_CS) &&
5828 vcpu->arch.singlestep_rip == kvm_rip_read(vcpu))
5829 rflags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
5830 kvm_x86_ops->set_rflags(vcpu, rflags);
5831}
5832EXPORT_SYMBOL_GPL(kvm_set_rflags);
5833
229456fc
MT		 5834EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
5835EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
5836EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
5837EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
5838EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 5839EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 5840EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 5841EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 5842EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 5843EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 5844EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
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