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KVM: Device assignment permission checks
[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
313a3dc7 29
18068523 30#include <linux/clocksource.h>
4d5c5d0f 31#include <linux/interrupt.h>
313a3dc7
CO		 32#include <linux/kvm.h>
33#include <linux/fs.h>
34#include <linux/vmalloc.h>
5fb76f9b 35#include <linux/module.h>
0de10343 36#include <linux/mman.h>
2bacc55c 37#include <linux/highmem.h>
19de40a8 38#include <linux/iommu.h>
62c476c7 39#include <linux/intel-iommu.h>
c8076604 40#include <linux/cpufreq.h>
18863bdd 41#include <linux/user-return-notifier.h>
a983fb23 42#include <linux/srcu.h>
5a0e3ad6 43#include <linux/slab.h>
ff9d07a0 44#include <linux/perf_event.h>
7bee342a 45#include <linux/uaccess.h>
af585b92 46#include <linux/hash.h>
a1b60c1c 47#include <linux/pci.h>
aec51dc4 48#include <trace/events/kvm.h>
2ed152af 49
229456fc
MT		 50#define CREATE_TRACE_POINTS
51#include "trace.h"
043405e1 52
24f1e32c 53#include <asm/debugreg.h>
d825ed0a 54#include <asm/msr.h>
a5f61300 55#include <asm/desc.h>
0bed3b56 56#include <asm/mtrr.h>
890ca9ae 57#include <asm/mce.h>
7cf30855 58#include <asm/i387.h>
98918833 59#include <asm/xcr.h>
1d5f066e 60#include <asm/pvclock.h>
217fc9cf 61#include <asm/div64.h>
043405e1 62
313a3dc7 63#define MAX_IO_MSRS 256
890ca9ae 64#define KVM_MAX_MCE_BANKS 32
5854dbca 65#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 66
0f65dd70
AK		 67#define emul_to_vcpu(ctxt) \
68 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
69
50a37eb4
JR		 70/* EFER defaults:
71 * - enable syscall per default because its emulated by KVM
72 * - enable LME and LMA per default on 64 bit KVM
73 */
74#ifdef CONFIG_X86_64
1260edbe
LJ		 75static
76u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 77#else
1260edbe 78static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 79#endif
313a3dc7 80
ba1389b7
AK		 81#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
82#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 83
cb142eb7 84static void update_cr8_intercept(struct kvm_vcpu *vcpu);
674eea0f
AK		 85static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
86 struct kvm_cpuid_entry2 __user *entries);
7460fb4a 87static void process_nmi(struct kvm_vcpu *vcpu);
674eea0f 88
97896d04 89struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 90EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 91
ed85c068
AP		 92int ignore_msrs = 0;
93module_param_named(ignore_msrs, ignore_msrs, bool, S_IRUGO | S_IWUSR);
94
92a1f12d
JR		 95bool kvm_has_tsc_control;
96EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
97u32 kvm_max_guest_tsc_khz;
98EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
99
18863bdd
AK		 100#define KVM_NR_SHARED_MSRS 16
101
102struct kvm_shared_msrs_global {
103 int nr;
2bf78fa7 104 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 105};
106
107struct kvm_shared_msrs {
108 struct user_return_notifier urn;
109 bool registered;
2bf78fa7
SY		 110 struct kvm_shared_msr_values {
111 u64 host;
112 u64 curr;
113 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 114};
115
116static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
117static DEFINE_PER_CPU(struct kvm_shared_msrs, shared_msrs);
118
417bc304 119struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 120 { "pf_fixed", VCPU_STAT(pf_fixed) },
121 { "pf_guest", VCPU_STAT(pf_guest) },
122 { "tlb_flush", VCPU_STAT(tlb_flush) },
123 { "invlpg", VCPU_STAT(invlpg) },
124 { "exits", VCPU_STAT(exits) },
125 { "io_exits", VCPU_STAT(io_exits) },
126 { "mmio_exits", VCPU_STAT(mmio_exits) },
127 { "signal_exits", VCPU_STAT(signal_exits) },
128 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 129 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 130 { "halt_exits", VCPU_STAT(halt_exits) },
131 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 132 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 133 { "request_irq", VCPU_STAT(request_irq_exits) },
134 { "irq_exits", VCPU_STAT(irq_exits) },
135 { "host_state_reload", VCPU_STAT(host_state_reload) },
136 { "efer_reload", VCPU_STAT(efer_reload) },
137 { "fpu_reload", VCPU_STAT(fpu_reload) },
138 { "insn_emulation", VCPU_STAT(insn_emulation) },
139 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 140 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 141 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 142 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
143 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
144 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
145 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
146 { "mmu_flooded", VM_STAT(mmu_flooded) },
147 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 148 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 149 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 150 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 151 { "largepages", VM_STAT(lpages) },
417bc304
HB		 152 { NULL }
153};
154
2acf923e
DC		 155u64 __read_mostly host_xcr0;
156
d6aa1000
AK		 157int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
158
af585b92
GN		 159static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
160{
161 int i;
162 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
163 vcpu->arch.apf.gfns[i] = ~0;
164}
165
18863bdd
AK		 166static void kvm_on_user_return(struct user_return_notifier *urn)
167{
168 unsigned slot;
18863bdd
AK		 169 struct kvm_shared_msrs *locals
170 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 171 struct kvm_shared_msr_values *values;
18863bdd
AK		 172
173 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 174 values = &locals->values[slot];
175 if (values->host != values->curr) {
176 wrmsrl(shared_msrs_global.msrs[slot], values->host);
177 values->curr = values->host;
18863bdd
AK		 178 }
179 }
180 locals->registered = false;
181 user_return_notifier_unregister(urn);
182}
183
2bf78fa7 184static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 185{
2bf78fa7 186 struct kvm_shared_msrs *smsr;
18863bdd
AK		 187 u64 value;
188
2bf78fa7
SY		 189 smsr = &__get_cpu_var(shared_msrs);
190 /* only read, and nobody should modify it at this time,
191 * so don't need lock */
192 if (slot >= shared_msrs_global.nr) {
193 printk(KERN_ERR "kvm: invalid MSR slot!");
194 return;
195 }
196 rdmsrl_safe(msr, &value);
197 smsr->values[slot].host = value;
198 smsr->values[slot].curr = value;
199}
200
201void kvm_define_shared_msr(unsigned slot, u32 msr)
202{
18863bdd
AK		 203 if (slot >= shared_msrs_global.nr)
204 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 205 shared_msrs_global.msrs[slot] = msr;
206 /* we need ensured the shared_msr_global have been updated */
207 smp_wmb();
18863bdd
AK		 208}
209EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
210
211static void kvm_shared_msr_cpu_online(void)
212{
213 unsigned i;
18863bdd
AK		 214
215 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 216 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 217}
218
d5696725 219void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd
AK		 220{
221 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
222
2bf78fa7 223 if (((value ^ smsr->values[slot].curr) & mask) == 0)
18863bdd 224 return;
2bf78fa7
SY		 225 smsr->values[slot].curr = value;
226 wrmsrl(shared_msrs_global.msrs[slot], value);
18863bdd
AK		 227 if (!smsr->registered) {
228 smsr->urn.on_user_return = kvm_on_user_return;
229 user_return_notifier_register(&smsr->urn);
230 smsr->registered = true;
231 }
232}
233EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
234
3548bab5
AK		 235static void drop_user_return_notifiers(void *ignore)
236{
237 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
238
239 if (smsr->registered)
240 kvm_on_user_return(&smsr->urn);
241}
242
6866b83e
CO		 243u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
244{
245 if (irqchip_in_kernel(vcpu->kvm))
ad312c7c 246 return vcpu->arch.apic_base;
6866b83e 247 else
ad312c7c 248 return vcpu->arch.apic_base;
6866b83e
CO		 249}
250EXPORT_SYMBOL_GPL(kvm_get_apic_base);
251
252void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
253{
254 /* TODO: reserve bits check */
255 if (irqchip_in_kernel(vcpu->kvm))
256 kvm_lapic_set_base(vcpu, data);
257 else
ad312c7c 258 vcpu->arch.apic_base = data;
6866b83e
CO		 259}
260EXPORT_SYMBOL_GPL(kvm_set_apic_base);
261
3fd28fce
ED		 262#define EXCPT_BENIGN 0
263#define EXCPT_CONTRIBUTORY 1
264#define EXCPT_PF 2
265
266static int exception_class(int vector)
267{
268 switch (vector) {
269 case PF_VECTOR:
270 return EXCPT_PF;
271 case DE_VECTOR:
272 case TS_VECTOR:
273 case NP_VECTOR:
274 case SS_VECTOR:
275 case GP_VECTOR:
276 return EXCPT_CONTRIBUTORY;
277 default:
278 break;
279 }
280 return EXCPT_BENIGN;
281}
282
283static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 284 unsigned nr, bool has_error, u32 error_code,
285 bool reinject)
3fd28fce
ED		 286{
287 u32 prev_nr;
288 int class1, class2;
289
3842d135
AK		 290 kvm_make_request(KVM_REQ_EVENT, vcpu);
291
3fd28fce
ED		 292 if (!vcpu->arch.exception.pending) {
293 queue:
294 vcpu->arch.exception.pending = true;
295 vcpu->arch.exception.has_error_code = has_error;
296 vcpu->arch.exception.nr = nr;
297 vcpu->arch.exception.error_code = error_code;
3f0fd292 298 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 299 return;
300 }
301
302 /* to check exception */
303 prev_nr = vcpu->arch.exception.nr;
304 if (prev_nr == DF_VECTOR) {
305 /* triple fault -> shutdown */
a8eeb04a 306 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 307 return;
308 }
309 class1 = exception_class(prev_nr);
310 class2 = exception_class(nr);
311 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
312 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
313 /* generate double fault per SDM Table 5-5 */
314 vcpu->arch.exception.pending = true;
315 vcpu->arch.exception.has_error_code = true;
316 vcpu->arch.exception.nr = DF_VECTOR;
317 vcpu->arch.exception.error_code = 0;
318 } else
319 /* replace previous exception with a new one in a hope
320 that instruction re-execution will regenerate lost
321 exception */
322 goto queue;
323}
324
298101da
AK		 325void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
326{
ce7ddec4 327 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 328}
329EXPORT_SYMBOL_GPL(kvm_queue_exception);
330
ce7ddec4
JR		 331void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
332{
333 kvm_multiple_exception(vcpu, nr, false, 0, true);
334}
335EXPORT_SYMBOL_GPL(kvm_requeue_exception);
336
db8fcefa 337void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 338{
db8fcefa
AP		 339 if (err)
340 kvm_inject_gp(vcpu, 0);
341 else
342 kvm_x86_ops->skip_emulated_instruction(vcpu);
343}
344EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 345
6389ee94 346void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 347{
348 ++vcpu->stat.pf_guest;
6389ee94
AK		 349 vcpu->arch.cr2 = fault->address;
350 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 351}
27d6c865 352EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 353
6389ee94 354void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 355{
6389ee94
AK		 356 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
357 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 358 else
6389ee94 359 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
d4f8cf66
JR		 360}
361
3419ffc8
SY		 362void kvm_inject_nmi(struct kvm_vcpu *vcpu)
363{
7460fb4a
AK		 364 atomic_inc(&vcpu->arch.nmi_queued);
365 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 366}
367EXPORT_SYMBOL_GPL(kvm_inject_nmi);
368
298101da
AK		 369void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
370{
ce7ddec4 371 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 372}
373EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
374
ce7ddec4
JR		 375void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
376{
377 kvm_multiple_exception(vcpu, nr, true, error_code, true);
378}
379EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
380
0a79b009
AK		 381/*
382 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
383 * a #GP and return false.
384 */
385bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 386{
0a79b009
AK		 387 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
388 return true;
389 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
390 return false;
298101da 391}
0a79b009 392EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 393
ec92fe44
JR		 394/*
395 * This function will be used to read from the physical memory of the currently
396 * running guest. The difference to kvm_read_guest_page is that this function
397 * can read from guest physical or from the guest's guest physical memory.
398 */
399int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
400 gfn_t ngfn, void *data, int offset, int len,
401 u32 access)
402{
403 gfn_t real_gfn;
404 gpa_t ngpa;
405
406 ngpa = gfn_to_gpa(ngfn);
407 real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
408 if (real_gfn == UNMAPPED_GVA)
409 return -EFAULT;
410
411 real_gfn = gpa_to_gfn(real_gfn);
412
413 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
414}
415EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
416
3d06b8bf
JR		 417int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
418 void *data, int offset, int len, u32 access)
419{
420 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
421 data, offset, len, access);
422}
423
a03490ed
CO		 424/*
425 * Load the pae pdptrs. Return true is they are all valid.
426 */
ff03a073 427int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 428{
429 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
430 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
431 int i;
432 int ret;
ff03a073 433 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 434
ff03a073
JR		 435 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
436 offset * sizeof(u64), sizeof(pdpte),
437 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 438 if (ret < 0) {
439 ret = 0;
440 goto out;
441 }
442 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 443 if (is_present_gpte(pdpte[i]) &&
20c466b5 444 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 445 ret = 0;
446 goto out;
447 }
448 }
449 ret = 1;
450
ff03a073 451 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 452 __set_bit(VCPU_EXREG_PDPTR,
453 (unsigned long *)&vcpu->arch.regs_avail);
454 __set_bit(VCPU_EXREG_PDPTR,
455 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 456out:
a03490ed
CO		 457
458 return ret;
459}
cc4b6871 460EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 461
d835dfec
AK		 462static bool pdptrs_changed(struct kvm_vcpu *vcpu)
463{
ff03a073 464 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 465 bool changed = true;
3d06b8bf
JR		 466 int offset;
467 gfn_t gfn;
d835dfec
AK		 468 int r;
469
470 if (is_long_mode(vcpu) || !is_pae(vcpu))
471 return false;
472
6de4f3ad
AK		 473 if (!test_bit(VCPU_EXREG_PDPTR,
474 (unsigned long *)&vcpu->arch.regs_avail))
475 return true;
476
9f8fe504
AK		 477 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
478 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 479 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
480 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 481 if (r < 0)
482 goto out;
ff03a073 483 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 484out:
d835dfec
AK		 485
486 return changed;
487}
488
49a9b07e 489int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 490{
aad82703
SY		 491 unsigned long old_cr0 = kvm_read_cr0(vcpu);
492 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
493 X86_CR0_CD | X86_CR0_NW;
494
f9a48e6a
AK		 495 cr0 |= X86_CR0_ET;
496
ab344828 497#ifdef CONFIG_X86_64
0f12244f
GN		 498 if (cr0 & 0xffffffff00000000UL)
499 return 1;
ab344828
GN		 500#endif
501
502 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 503
0f12244f
GN		 504 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
505 return 1;
a03490ed 506
0f12244f
GN		 507 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
508 return 1;
a03490ed
CO		 509
510 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
511#ifdef CONFIG_X86_64
f6801dff 512 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 513 int cs_db, cs_l;
514
0f12244f
GN		 515 if (!is_pae(vcpu))
516 return 1;
a03490ed 517 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 518 if (cs_l)
519 return 1;
a03490ed
CO		 520 } else
521#endif
ff03a073 522 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 523 kvm_read_cr3(vcpu)))
0f12244f 524 return 1;
a03490ed
CO		 525 }
526
527 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 528
d170c419 529 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 530 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 531 kvm_async_pf_hash_reset(vcpu);
532 }
e5f3f027 533
aad82703
SY		 534 if ((cr0 ^ old_cr0) & update_bits)
535 kvm_mmu_reset_context(vcpu);
0f12244f
GN		 536 return 0;
537}
2d3ad1f4 538EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 539
2d3ad1f4 540void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 541{
49a9b07e 542 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 543}
2d3ad1f4 544EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 545
2acf923e
DC		 546int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
547{
548 u64 xcr0;
549
550 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
551 if (index != XCR_XFEATURE_ENABLED_MASK)
552 return 1;
553 xcr0 = xcr;
554 if (kvm_x86_ops->get_cpl(vcpu) != 0)
555 return 1;
556 if (!(xcr0 & XSTATE_FP))
557 return 1;
558 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
559 return 1;
560 if (xcr0 & ~host_xcr0)
561 return 1;
562 vcpu->arch.xcr0 = xcr0;
563 vcpu->guest_xcr0_loaded = 0;
564 return 0;
565}
566
567int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
568{
569 if (__kvm_set_xcr(vcpu, index, xcr)) {
570 kvm_inject_gp(vcpu, 0);
571 return 1;
572 }
573 return 0;
574}
575EXPORT_SYMBOL_GPL(kvm_set_xcr);
576
577static bool guest_cpuid_has_xsave(struct kvm_vcpu *vcpu)
578{
579 struct kvm_cpuid_entry2 *best;
580
581 best = kvm_find_cpuid_entry(vcpu, 1, 0);
582 return best && (best->ecx & bit(X86_FEATURE_XSAVE));
583}
584
c68b734f
YW		 585static bool guest_cpuid_has_smep(struct kvm_vcpu *vcpu)
586{
587 struct kvm_cpuid_entry2 *best;
588
589 best = kvm_find_cpuid_entry(vcpu, 7, 0);
590 return best && (best->ebx & bit(X86_FEATURE_SMEP));
591}
592
74dc2b4f
YW		 593static bool guest_cpuid_has_fsgsbase(struct kvm_vcpu *vcpu)
594{
595 struct kvm_cpuid_entry2 *best;
596
597 best = kvm_find_cpuid_entry(vcpu, 7, 0);
598 return best && (best->ebx & bit(X86_FEATURE_FSGSBASE));
599}
600
2acf923e
DC		 601static void update_cpuid(struct kvm_vcpu *vcpu)
602{
603 struct kvm_cpuid_entry2 *best;
a3e06bbe
LJ		 604 struct kvm_lapic *apic = vcpu->arch.apic;
605 u32 timer_mode_mask;
2acf923e
DC		 606
607 best = kvm_find_cpuid_entry(vcpu, 1, 0);
608 if (!best)
609 return;
610
611 /* Update OSXSAVE bit */
612 if (cpu_has_xsave && best->function == 0x1) {
613 best->ecx &= ~(bit(X86_FEATURE_OSXSAVE));
614 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE))
615 best->ecx |= bit(X86_FEATURE_OSXSAVE);
616 }
a3e06bbe
LJ		 617
618 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
619 best->function == 0x1) {
620 best->ecx |= bit(X86_FEATURE_TSC_DEADLINE_TIMER);
621 timer_mode_mask = 3 << 17;
622 } else
623 timer_mode_mask = 1 << 17;
624
625 if (apic)
626 apic->lapic_timer.timer_mode_mask = timer_mode_mask;
2acf923e
DC		 627}
628
a83b29c6 629int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 630{
fc78f519 631 unsigned long old_cr4 = kvm_read_cr4(vcpu);
c68b734f
YW		 632 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE |
633 X86_CR4_PAE | X86_CR4_SMEP;
0f12244f
GN		 634 if (cr4 & CR4_RESERVED_BITS)
635 return 1;
a03490ed 636
2acf923e
DC		 637 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
638 return 1;
639
c68b734f
YW		 640 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
641 return 1;
642
74dc2b4f
YW		 643 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_RDWRGSFS))
644 return 1;
645
a03490ed 646 if (is_long_mode(vcpu)) {
0f12244f
GN		 647 if (!(cr4 & X86_CR4_PAE))
648 return 1;
a2edf57f
AK		 649 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
650 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 651 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
652 kvm_read_cr3(vcpu)))
0f12244f
GN		 653 return 1;
654
5e1746d6 655 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 656 return 1;
a03490ed 657
aad82703
SY		 658 if ((cr4 ^ old_cr4) & pdptr_bits)
659 kvm_mmu_reset_context(vcpu);
0f12244f 660
2acf923e
DC		 661 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
662 update_cpuid(vcpu);
663
0f12244f
GN		 664 return 0;
665}
2d3ad1f4 666EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 667
2390218b 668int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 669{
9f8fe504 670 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 671 kvm_mmu_sync_roots(vcpu);
d835dfec 672 kvm_mmu_flush_tlb(vcpu);
0f12244f 673 return 0;
d835dfec
AK		 674 }
675
a03490ed 676 if (is_long_mode(vcpu)) {
0f12244f
GN		 677 if (cr3 & CR3_L_MODE_RESERVED_BITS)
678 return 1;
a03490ed
CO		 679 } else {
680 if (is_pae(vcpu)) {
0f12244f
GN		 681 if (cr3 & CR3_PAE_RESERVED_BITS)
682 return 1;
ff03a073
JR		 683 if (is_paging(vcpu) &&
684 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
0f12244f 685 return 1;
a03490ed
CO		 686 }
687 /*
688 * We don't check reserved bits in nonpae mode, because
689 * this isn't enforced, and VMware depends on this.
690 */
691 }
692
a03490ed
CO		 693 /*
694 * Does the new cr3 value map to physical memory? (Note, we
695 * catch an invalid cr3 even in real-mode, because it would
696 * cause trouble later on when we turn on paging anyway.)
697 *
698 * A real CPU would silently accept an invalid cr3 and would
699 * attempt to use it - with largely undefined (and often hard
700 * to debug) behavior on the guest side.
701 */
702 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
0f12244f
GN		 703 return 1;
704 vcpu->arch.cr3 = cr3;
aff48baa 705 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
0f12244f
GN		 706 vcpu->arch.mmu.new_cr3(vcpu);
707 return 0;
708}
2d3ad1f4 709EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 710
eea1cff9 711int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 712{
0f12244f
GN		 713 if (cr8 & CR8_RESERVED_BITS)
714 return 1;
a03490ed
CO		 715 if (irqchip_in_kernel(vcpu->kvm))
716 kvm_lapic_set_tpr(vcpu, cr8);
717 else
ad312c7c 718 vcpu->arch.cr8 = cr8;
0f12244f
GN		 719 return 0;
720}
2d3ad1f4 721EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 722
2d3ad1f4 723unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 724{
725 if (irqchip_in_kernel(vcpu->kvm))
726 return kvm_lapic_get_cr8(vcpu);
727 else
ad312c7c 728 return vcpu->arch.cr8;
a03490ed 729}
2d3ad1f4 730EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 731
338dbc97 732static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 733{
734 switch (dr) {
735 case 0 ... 3:
736 vcpu->arch.db[dr] = val;
737 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
738 vcpu->arch.eff_db[dr] = val;
739 break;
740 case 4:
338dbc97
GN		 741 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
742 return 1; /* #UD */
020df079
GN		 743 /* fall through */
744 case 6:
338dbc97
GN		 745 if (val & 0xffffffff00000000ULL)
746 return -1; /* #GP */
020df079
GN		 747 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
748 break;
749 case 5:
338dbc97
GN		 750 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
751 return 1; /* #UD */
020df079
GN		 752 /* fall through */
753 default: /* 7 */
338dbc97
GN		 754 if (val & 0xffffffff00000000ULL)
755 return -1; /* #GP */
020df079
GN		 756 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
757 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
758 kvm_x86_ops->set_dr7(vcpu, vcpu->arch.dr7);
759 vcpu->arch.switch_db_regs = (val & DR7_BP_EN_MASK);
760 }
761 break;
762 }
763
764 return 0;
765}
338dbc97
GN		 766
767int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
768{
769 int res;
770
771 res = __kvm_set_dr(vcpu, dr, val);
772 if (res > 0)
773 kvm_queue_exception(vcpu, UD_VECTOR);
774 else if (res < 0)
775 kvm_inject_gp(vcpu, 0);
776
777 return res;
778}
020df079
GN		 779EXPORT_SYMBOL_GPL(kvm_set_dr);
780
338dbc97 781static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 782{
783 switch (dr) {
784 case 0 ... 3:
785 *val = vcpu->arch.db[dr];
786 break;
787 case 4:
338dbc97 788 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 789 return 1;
020df079
GN		 790 /* fall through */
791 case 6:
792 *val = vcpu->arch.dr6;
793 break;
794 case 5:
338dbc97 795 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 796 return 1;
020df079
GN		 797 /* fall through */
798 default: /* 7 */
799 *val = vcpu->arch.dr7;
800 break;
801 }
802
803 return 0;
804}
338dbc97
GN		 805
806int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
807{
808 if (_kvm_get_dr(vcpu, dr, val)) {
809 kvm_queue_exception(vcpu, UD_VECTOR);
810 return 1;
811 }
812 return 0;
813}
020df079
GN		 814EXPORT_SYMBOL_GPL(kvm_get_dr);
815
043405e1
CO		 816/*
817 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
818 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
819 *
820 * This list is modified at module load time to reflect the
e3267cbb
GC		 821 * capabilities of the host cpu. This capabilities test skips MSRs that are
822 * kvm-specific. Those are put in the beginning of the list.
043405e1 823 */
e3267cbb 824
c9aaa895 825#define KVM_SAVE_MSRS_BEGIN 9
043405e1 826static u32 msrs_to_save[] = {
e3267cbb 827 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
11c6bffa 828 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
55cd8e5a 829 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
c9aaa895 830 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
043405e1 831 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 832 MSR_STAR,
043405e1
CO		 833#ifdef CONFIG_X86_64
834 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
835#endif
e90aa41e 836 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
043405e1
CO		 837};
838
839static unsigned num_msrs_to_save;
840
841static u32 emulated_msrs[] = {
a3e06bbe 842 MSR_IA32_TSCDEADLINE,
043405e1 843 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 844 MSR_IA32_MCG_STATUS,
845 MSR_IA32_MCG_CTL,
043405e1
CO		 846};
847
b69e8cae 848static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 849{
aad82703
SY		 850 u64 old_efer = vcpu->arch.efer;
851
b69e8cae
RJ		 852 if (efer & efer_reserved_bits)
853 return 1;
15c4a640
CO		 854
855 if (is_paging(vcpu)
b69e8cae
RJ		 856 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
857 return 1;
15c4a640 858
1b2fd70c
AG		 859 if (efer & EFER_FFXSR) {
860 struct kvm_cpuid_entry2 *feat;
861
862 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 863 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
864 return 1;
1b2fd70c
AG		 865 }
866
d8017474
AG		 867 if (efer & EFER_SVME) {
868 struct kvm_cpuid_entry2 *feat;
869
870 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 871 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
872 return 1;
d8017474
AG		 873 }
874
15c4a640 875 efer &= ~EFER_LMA;
f6801dff 876 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 877
a3d204e2
SY		 878 kvm_x86_ops->set_efer(vcpu, efer);
879
9645bb56 880 vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
b69e8cae 881
aad82703
SY		 882 /* Update reserved bits */
883 if ((efer ^ old_efer) & EFER_NX)
884 kvm_mmu_reset_context(vcpu);
885
b69e8cae 886 return 0;
15c4a640
CO		 887}
888
f2b4b7dd
JR		 889void kvm_enable_efer_bits(u64 mask)
890{
891 efer_reserved_bits &= ~mask;
892}
893EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
894
895
15c4a640
CO		 896/*
897 * Writes msr value into into the appropriate "register".
898 * Returns 0 on success, non-0 otherwise.
899 * Assumes vcpu_load() was already called.
900 */
901int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
902{
903 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
904}
905
313a3dc7
CO		 906/*
907 * Adapt set_msr() to msr_io()'s calling convention
908 */
909static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
910{
911 return kvm_set_msr(vcpu, index, *data);
912}
913
18068523
GOC		 914static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
915{
9ed3c444
AK		 916 int version;
917 int r;
50d0a0f9 918 struct pvclock_wall_clock wc;
923de3cf 919 struct timespec boot;
18068523
GOC		 920
921 if (!wall_clock)
922 return;
923
9ed3c444
AK		 924 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
925 if (r)
926 return;
927
928 if (version & 1)
929 ++version; /* first time write, random junk */
930
931 ++version;
18068523 932
18068523
GOC		 933 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
934
50d0a0f9
GH		 935 /*
936 * The guest calculates current wall clock time by adding
34c238a1 937 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 938 * wall clock specified here. guest system time equals host
939 * system time for us, thus we must fill in host boot time here.
940 */
923de3cf 941 getboottime(&boot);
50d0a0f9
GH		 942
943 wc.sec = boot.tv_sec;
944 wc.nsec = boot.tv_nsec;
945 wc.version = version;
18068523
GOC		 946
947 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
948
949 version++;
950 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 951}
952
50d0a0f9
GH		 953static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
954{
955 uint32_t quotient, remainder;
956
957 /* Don't try to replace with do_div(), this one calculates
958 * "(dividend << 32) / divisor" */
959 __asm__ ( "divl %4"
960 : "=a" (quotient), "=d" (remainder)
961 : "0" (0), "1" (dividend), "r" (divisor) );
962 return quotient;
963}
964
5f4e3f88
ZA		 965static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
966 s8 *pshift, u32 *pmultiplier)
50d0a0f9 967{
5f4e3f88 968 uint64_t scaled64;
50d0a0f9
GH		 969 int32_t shift = 0;
970 uint64_t tps64;
971 uint32_t tps32;
972
5f4e3f88
ZA		 973 tps64 = base_khz * 1000LL;
974 scaled64 = scaled_khz * 1000LL;
50933623 975 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 976 tps64 >>= 1;
977 shift--;
978 }
979
980 tps32 = (uint32_t)tps64;
50933623
JK		 981 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
982 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 983 scaled64 >>= 1;
984 else
985 tps32 <<= 1;
50d0a0f9
GH		 986 shift++;
987 }
988
5f4e3f88
ZA		 989 *pshift = shift;
990 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 991
5f4e3f88
ZA		 992 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
993 __func__, base_khz, scaled_khz, shift, *pmultiplier);
50d0a0f9
GH		 994}
995
759379dd
ZA		 996static inline u64 get_kernel_ns(void)
997{
998 struct timespec ts;
999
1000 WARN_ON(preemptible());
1001 ktime_get_ts(&ts);
1002 monotonic_to_bootbased(&ts);
1003 return timespec_to_ns(&ts);
50d0a0f9
GH		 1004}
1005
c8076604 1006static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
c285545f 1007unsigned long max_tsc_khz;
c8076604 1008
8cfdc000
ZA		 1009static inline int kvm_tsc_changes_freq(void)
1010{
1011 int cpu = get_cpu();
1012 int ret = !boot_cpu_has(X86_FEATURE_CONSTANT_TSC) &&
1013 cpufreq_quick_get(cpu) != 0;
1014 put_cpu();
1015 return ret;
1016}
1017
a3e06bbe 1018u64 vcpu_tsc_khz(struct kvm_vcpu *vcpu)
1e993611
JR		 1019{
1020 if (vcpu->arch.virtual_tsc_khz)
1021 return vcpu->arch.virtual_tsc_khz;
1022 else
1023 return __this_cpu_read(cpu_tsc_khz);
1024}
1025
857e4099 1026static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
759379dd 1027{
217fc9cf
AK		 1028 u64 ret;
1029
759379dd
ZA		 1030 WARN_ON(preemptible());
1031 if (kvm_tsc_changes_freq())
1032 printk_once(KERN_WARNING
1033 "kvm: unreliable cycle conversion on adjustable rate TSC\n");
857e4099 1034 ret = nsec * vcpu_tsc_khz(vcpu);
217fc9cf
AK		 1035 do_div(ret, USEC_PER_SEC);
1036 return ret;
759379dd
ZA		 1037}
1038
1e993611 1039static void kvm_init_tsc_catchup(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
c285545f
ZA		 1040{
1041 /* Compute a scale to convert nanoseconds in TSC cycles */
1042 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
1e993611
JR		 1043 &vcpu->arch.tsc_catchup_shift,
1044 &vcpu->arch.tsc_catchup_mult);
c285545f
ZA		 1045}
1046
1047static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1048{
1049 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.last_tsc_nsec,
1e993611
JR		 1050 vcpu->arch.tsc_catchup_mult,
1051 vcpu->arch.tsc_catchup_shift);
c285545f
ZA		 1052 tsc += vcpu->arch.last_tsc_write;
1053 return tsc;
1054}
1055
99e3e30a
ZA		 1056void kvm_write_tsc(struct kvm_vcpu *vcpu, u64 data)
1057{
1058 struct kvm *kvm = vcpu->kvm;
f38e098f 1059 u64 offset, ns, elapsed;
99e3e30a 1060 unsigned long flags;
46543ba4 1061 s64 sdiff;
99e3e30a 1062
038f8c11 1063 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
857e4099 1064 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1065 ns = get_kernel_ns();
f38e098f 1066 elapsed = ns - kvm->arch.last_tsc_nsec;
46543ba4
ZA		 1067 sdiff = data - kvm->arch.last_tsc_write;
1068 if (sdiff < 0)
1069 sdiff = -sdiff;
f38e098f
ZA		 1070
1071 /*
46543ba4 1072 * Special case: close write to TSC within 5 seconds of
f38e098f 1073 * another CPU is interpreted as an attempt to synchronize
0d2eb44f 1074 * The 5 seconds is to accommodate host load / swapping as
46543ba4 1075 * well as any reset of TSC during the boot process.
f38e098f
ZA		 1076 *
1077 * In that case, for a reliable TSC, we can match TSC offsets,
46543ba4 1078 * or make a best guest using elapsed value.
f38e098f 1079 */
857e4099 1080 if (sdiff < nsec_to_cycles(vcpu, 5ULL * NSEC_PER_SEC) &&
46543ba4 1081 elapsed < 5ULL * NSEC_PER_SEC) {
f38e098f
ZA		 1082 if (!check_tsc_unstable()) {
1083 offset = kvm->arch.last_tsc_offset;
1084 pr_debug("kvm: matched tsc offset for %llu\n", data);
1085 } else {
857e4099 1086 u64 delta = nsec_to_cycles(vcpu, elapsed);
759379dd
ZA		 1087 offset += delta;
1088 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f
ZA		 1089 }
1090 ns = kvm->arch.last_tsc_nsec;
1091 }
1092 kvm->arch.last_tsc_nsec = ns;
1093 kvm->arch.last_tsc_write = data;
1094 kvm->arch.last_tsc_offset = offset;
99e3e30a 1095 kvm_x86_ops->write_tsc_offset(vcpu, offset);
038f8c11 1096 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
99e3e30a
ZA		 1097
1098 /* Reset of TSC must disable overshoot protection below */
1099 vcpu->arch.hv_clock.tsc_timestamp = 0;
c285545f
ZA		 1100 vcpu->arch.last_tsc_write = data;
1101 vcpu->arch.last_tsc_nsec = ns;
99e3e30a
ZA		 1102}
1103EXPORT_SYMBOL_GPL(kvm_write_tsc);
1104
34c238a1 1105static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1106{
18068523
GOC		 1107 unsigned long flags;
1108 struct kvm_vcpu_arch *vcpu = &v->arch;
1109 void *shared_kaddr;
463656c0 1110 unsigned long this_tsc_khz;
1d5f066e
ZA		 1111 s64 kernel_ns, max_kernel_ns;
1112 u64 tsc_timestamp;
18068523 1113
18068523
GOC		 1114 /* Keep irq disabled to prevent changes to the clock */
1115 local_irq_save(flags);
d5c1785d 1116 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v);
759379dd 1117 kernel_ns = get_kernel_ns();
1e993611 1118 this_tsc_khz = vcpu_tsc_khz(v);
8cfdc000 1119 if (unlikely(this_tsc_khz == 0)) {
c285545f 1120 local_irq_restore(flags);
34c238a1 1121 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
8cfdc000
ZA		 1122 return 1;
1123 }
18068523 1124
c285545f
ZA		 1125 /*
1126 * We may have to catch up the TSC to match elapsed wall clock
1127 * time for two reasons, even if kvmclock is used.
1128 * 1) CPU could have been running below the maximum TSC rate
1129 * 2) Broken TSC compensation resets the base at each VCPU
1130 * entry to avoid unknown leaps of TSC even when running
1131 * again on the same CPU. This may cause apparent elapsed
1132 * time to disappear, and the guest to stand still or run
1133 * very slowly.
1134 */
1135 if (vcpu->tsc_catchup) {
1136 u64 tsc = compute_guest_tsc(v, kernel_ns);
1137 if (tsc > tsc_timestamp) {
1138 kvm_x86_ops->adjust_tsc_offset(v, tsc - tsc_timestamp);
1139 tsc_timestamp = tsc;
1140 }
50d0a0f9
GH		 1141 }
1142
18068523
GOC		 1143 local_irq_restore(flags);
1144
c285545f
ZA		 1145 if (!vcpu->time_page)
1146 return 0;
18068523 1147
1d5f066e
ZA		 1148 /*
1149 * Time as measured by the TSC may go backwards when resetting the base
1150 * tsc_timestamp. The reason for this is that the TSC resolution is
1151 * higher than the resolution of the other clock scales. Thus, many
1152 * possible measurments of the TSC correspond to one measurement of any
1153 * other clock, and so a spread of values is possible. This is not a
1154 * problem for the computation of the nanosecond clock; with TSC rates
1155 * around 1GHZ, there can only be a few cycles which correspond to one
1156 * nanosecond value, and any path through this code will inevitably
1157 * take longer than that. However, with the kernel_ns value itself,
1158 * the precision may be much lower, down to HZ granularity. If the
1159 * first sampling of TSC against kernel_ns ends in the low part of the
1160 * range, and the second in the high end of the range, we can get:
1161 *
1162 * (TSC - offset_low) * S + kns_old > (TSC - offset_high) * S + kns_new
1163 *
1164 * As the sampling errors potentially range in the thousands of cycles,
1165 * it is possible such a time value has already been observed by the
1166 * guest. To protect against this, we must compute the system time as
1167 * observed by the guest and ensure the new system time is greater.
1168 */
1169 max_kernel_ns = 0;
1170 if (vcpu->hv_clock.tsc_timestamp && vcpu->last_guest_tsc) {
1171 max_kernel_ns = vcpu->last_guest_tsc -
1172 vcpu->hv_clock.tsc_timestamp;
1173 max_kernel_ns = pvclock_scale_delta(max_kernel_ns,
1174 vcpu->hv_clock.tsc_to_system_mul,
1175 vcpu->hv_clock.tsc_shift);
1176 max_kernel_ns += vcpu->last_kernel_ns;
1177 }
afbcf7ab 1178
e48672fa 1179 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
5f4e3f88
ZA		 1180 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1181 &vcpu->hv_clock.tsc_shift,
1182 &vcpu->hv_clock.tsc_to_system_mul);
e48672fa 1183 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1184 }
1185
1d5f066e
ZA		 1186 if (max_kernel_ns > kernel_ns)
1187 kernel_ns = max_kernel_ns;
1188
8cfdc000 1189 /* With all the info we got, fill in the values */
1d5f066e 1190 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1191 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1d5f066e 1192 vcpu->last_kernel_ns = kernel_ns;
28e4639a 1193 vcpu->last_guest_tsc = tsc_timestamp;
371bcf64
GC		 1194 vcpu->hv_clock.flags = 0;
1195
18068523
GOC		 1196 /*
1197 * The interface expects us to write an even number signaling that the
1198 * update is finished. Since the guest won't see the intermediate
50d0a0f9 1199 * state, we just increase by 2 at the end.
18068523 1200 */
50d0a0f9 1201 vcpu->hv_clock.version += 2;
18068523
GOC		 1202
1203 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
1204
1205 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
50d0a0f9 1206 sizeof(vcpu->hv_clock));
18068523
GOC		 1207
1208 kunmap_atomic(shared_kaddr, KM_USER0);
1209
1210 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
8cfdc000 1211 return 0;
c8076604
GH		 1212}
1213
9ba075a6
AK		 1214static bool msr_mtrr_valid(unsigned msr)
1215{
1216 switch (msr) {
1217 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1218 case MSR_MTRRfix64K_00000:
1219 case MSR_MTRRfix16K_80000:
1220 case MSR_MTRRfix16K_A0000:
1221 case MSR_MTRRfix4K_C0000:
1222 case MSR_MTRRfix4K_C8000:
1223 case MSR_MTRRfix4K_D0000:
1224 case MSR_MTRRfix4K_D8000:
1225 case MSR_MTRRfix4K_E0000:
1226 case MSR_MTRRfix4K_E8000:
1227 case MSR_MTRRfix4K_F0000:
1228 case MSR_MTRRfix4K_F8000:
1229 case MSR_MTRRdefType:
1230 case MSR_IA32_CR_PAT:
1231 return true;
1232 case 0x2f8:
1233 return true;
1234 }
1235 return false;
1236}
1237
d6289b93
MT		 1238static bool valid_pat_type(unsigned t)
1239{
1240 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1241}
1242
1243static bool valid_mtrr_type(unsigned t)
1244{
1245 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1246}
1247
1248static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1249{
1250 int i;
1251
1252 if (!msr_mtrr_valid(msr))
1253 return false;
1254
1255 if (msr == MSR_IA32_CR_PAT) {
1256 for (i = 0; i < 8; i++)
1257 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1258 return false;
1259 return true;
1260 } else if (msr == MSR_MTRRdefType) {
1261 if (data & ~0xcff)
1262 return false;
1263 return valid_mtrr_type(data & 0xff);
1264 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1265 for (i = 0; i < 8 ; i++)
1266 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1267 return false;
1268 return true;
1269 }
1270
1271 /* variable MTRRs */
1272 return valid_mtrr_type(data & 0xff);
1273}
1274
9ba075a6
AK		 1275static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1276{
0bed3b56
SY		 1277 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1278
d6289b93 1279 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 1280 return 1;
1281
0bed3b56
SY		 1282 if (msr == MSR_MTRRdefType) {
1283 vcpu->arch.mtrr_state.def_type = data;
1284 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1285 } else if (msr == MSR_MTRRfix64K_00000)
1286 p[0] = data;
1287 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1288 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1289 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1290 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1291 else if (msr == MSR_IA32_CR_PAT)
1292 vcpu->arch.pat = data;
1293 else { /* Variable MTRRs */
1294 int idx, is_mtrr_mask;
1295 u64 *pt;
1296
1297 idx = (msr - 0x200) / 2;
1298 is_mtrr_mask = msr - 0x200 - 2 * idx;
1299 if (!is_mtrr_mask)
1300 pt =
1301 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1302 else
1303 pt =
1304 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1305 *pt = data;
1306 }
1307
1308 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 1309 return 0;
1310}
15c4a640 1311
890ca9ae 1312static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1313{
890ca9ae
HY		 1314 u64 mcg_cap = vcpu->arch.mcg_cap;
1315 unsigned bank_num = mcg_cap & 0xff;
1316
15c4a640 1317 switch (msr) {
15c4a640 1318 case MSR_IA32_MCG_STATUS:
890ca9ae 1319 vcpu->arch.mcg_status = data;
15c4a640 1320 break;
c7ac679c 1321 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1322 if (!(mcg_cap & MCG_CTL_P))
1323 return 1;
1324 if (data != 0 && data != ~(u64)0)
1325 return -1;
1326 vcpu->arch.mcg_ctl = data;
1327 break;
1328 default:
1329 if (msr >= MSR_IA32_MC0_CTL &&
1330 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1331 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1332 /* only 0 or all 1s can be written to IA32_MCi_CTL
1333 * some Linux kernels though clear bit 10 in bank 4 to
1334 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1335 * this to avoid an uncatched #GP in the guest
1336 */
890ca9ae 1337 if ((offset & 0x3) == 0 &&
114be429 1338 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1339 return -1;
1340 vcpu->arch.mce_banks[offset] = data;
1341 break;
1342 }
1343 return 1;
1344 }
1345 return 0;
1346}
1347
ffde22ac
ES		 1348static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1349{
1350 struct kvm *kvm = vcpu->kvm;
1351 int lm = is_long_mode(vcpu);
1352 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1353 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1354 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1355 : kvm->arch.xen_hvm_config.blob_size_32;
1356 u32 page_num = data & ~PAGE_MASK;
1357 u64 page_addr = data & PAGE_MASK;
1358 u8 *page;
1359 int r;
1360
1361 r = -E2BIG;
1362 if (page_num >= blob_size)
1363 goto out;
1364 r = -ENOMEM;
1365 page = kzalloc(PAGE_SIZE, GFP_KERNEL);
1366 if (!page)
1367 goto out;
1368 r = -EFAULT;
1369 if (copy_from_user(page, blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE))
1370 goto out_free;
1371 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1372 goto out_free;
1373 r = 0;
1374out_free:
1375 kfree(page);
1376out:
1377 return r;
1378}
1379
55cd8e5a
GN		 1380static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1381{
1382 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1383}
1384
1385static bool kvm_hv_msr_partition_wide(u32 msr)
1386{
1387 bool r = false;
1388 switch (msr) {
1389 case HV_X64_MSR_GUEST_OS_ID:
1390 case HV_X64_MSR_HYPERCALL:
1391 r = true;
1392 break;
1393 }
1394
1395 return r;
1396}
1397
1398static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1399{
1400 struct kvm *kvm = vcpu->kvm;
1401
1402 switch (msr) {
1403 case HV_X64_MSR_GUEST_OS_ID:
1404 kvm->arch.hv_guest_os_id = data;
1405 /* setting guest os id to zero disables hypercall page */
1406 if (!kvm->arch.hv_guest_os_id)
1407 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1408 break;
1409 case HV_X64_MSR_HYPERCALL: {
1410 u64 gfn;
1411 unsigned long addr;
1412 u8 instructions[4];
1413
1414 /* if guest os id is not set hypercall should remain disabled */
1415 if (!kvm->arch.hv_guest_os_id)
1416 break;
1417 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1418 kvm->arch.hv_hypercall = data;
1419 break;
1420 }
1421 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1422 addr = gfn_to_hva(kvm, gfn);
1423 if (kvm_is_error_hva(addr))
1424 return 1;
1425 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1426 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
8b0cedff 1427 if (__copy_to_user((void __user *)addr, instructions, 4))
55cd8e5a
GN		 1428 return 1;
1429 kvm->arch.hv_hypercall = data;
1430 break;
1431 }
1432 default:
1433 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1434 "data 0x%llx\n", msr, data);
1435 return 1;
1436 }
1437 return 0;
1438}
1439
1440static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1441{
10388a07
GN		 1442 switch (msr) {
1443 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1444 unsigned long addr;
55cd8e5a 1445
10388a07
GN		 1446 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1447 vcpu->arch.hv_vapic = data;
1448 break;
1449 }
1450 addr = gfn_to_hva(vcpu->kvm, data >>
1451 HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1452 if (kvm_is_error_hva(addr))
1453 return 1;
8b0cedff 1454 if (__clear_user((void __user *)addr, PAGE_SIZE))
10388a07
GN		 1455 return 1;
1456 vcpu->arch.hv_vapic = data;
1457 break;
1458 }
1459 case HV_X64_MSR_EOI:
1460 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1461 case HV_X64_MSR_ICR:
1462 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1463 case HV_X64_MSR_TPR:
1464 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1465 default:
1466 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1467 "data 0x%llx\n", msr, data);
1468 return 1;
1469 }
1470
1471 return 0;
55cd8e5a
GN		 1472}
1473
344d9588
GN		 1474static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1475{
1476 gpa_t gpa = data & ~0x3f;
1477
6adba527
GN		 1478 /* Bits 2:5 are resrved, Should be zero */
1479 if (data & 0x3c)
344d9588
GN		 1480 return 1;
1481
1482 vcpu->arch.apf.msr_val = data;
1483
1484 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1485 kvm_clear_async_pf_completion_queue(vcpu);
1486 kvm_async_pf_hash_reset(vcpu);
1487 return 0;
1488 }
1489
1490 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa))
1491 return 1;
1492
6adba527 1493 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 1494 kvm_async_pf_wakeup_all(vcpu);
1495 return 0;
1496}
1497
12f9a48f
GC		 1498static void kvmclock_reset(struct kvm_vcpu *vcpu)
1499{
1500 if (vcpu->arch.time_page) {
1501 kvm_release_page_dirty(vcpu->arch.time_page);
1502 vcpu->arch.time_page = NULL;
1503 }
1504}
1505
c9aaa895
GC		 1506static void accumulate_steal_time(struct kvm_vcpu *vcpu)
1507{
1508 u64 delta;
1509
1510 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1511 return;
1512
1513 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
1514 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1515 vcpu->arch.st.accum_steal = delta;
1516}
1517
1518static void record_steal_time(struct kvm_vcpu *vcpu)
1519{
1520 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1521 return;
1522
1523 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1524 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
1525 return;
1526
1527 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
1528 vcpu->arch.st.steal.version += 2;
1529 vcpu->arch.st.accum_steal = 0;
1530
1531 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1532 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
1533}
1534
15c4a640
CO		 1535int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1536{
1537 switch (msr) {
15c4a640 1538 case MSR_EFER:
b69e8cae 1539 return set_efer(vcpu, data);
8f1589d9
AP		 1540 case MSR_K7_HWCR:
1541 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 1542 data &= ~(u64)0x100; /* ignore ignne emulation enable */
8f1589d9
AP		 1543 if (data != 0) {
1544 pr_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1545 data);
1546 return 1;
1547 }
15c4a640 1548 break;
f7c6d140
AP		 1549 case MSR_FAM10H_MMIO_CONF_BASE:
1550 if (data != 0) {
1551 pr_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1552 "0x%llx\n", data);
1553 return 1;
1554 }
15c4a640 1555 break;
c323c0e5 1556 case MSR_AMD64_NB_CFG:
c7ac679c 1557 break;
b5e2fec0
AG		 1558 case MSR_IA32_DEBUGCTLMSR:
1559 if (!data) {
1560 /* We support the non-activated case already */
1561 break;
1562 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1563 /* Values other than LBR and BTF are vendor-specific,
1564 thus reserved and should throw a #GP */
1565 return 1;
1566 }
1567 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1568 __func__, data);
1569 break;
15c4a640
CO		 1570 case MSR_IA32_UCODE_REV:
1571 case MSR_IA32_UCODE_WRITE:
61a6bd67 1572 case MSR_VM_HSAVE_PA:
6098ca93 1573 case MSR_AMD64_PATCH_LOADER:
15c4a640 1574 break;
9ba075a6
AK		 1575 case 0x200 ... 0x2ff:
1576 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 1577 case MSR_IA32_APICBASE:
1578 kvm_set_apic_base(vcpu, data);
1579 break;
0105d1a5
GN		 1580 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1581 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 1582 case MSR_IA32_TSCDEADLINE:
1583 kvm_set_lapic_tscdeadline_msr(vcpu, data);
1584 break;
15c4a640 1585 case MSR_IA32_MISC_ENABLE:
ad312c7c 1586 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 1587 break;
11c6bffa 1588 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1589 case MSR_KVM_WALL_CLOCK:
1590 vcpu->kvm->arch.wall_clock = data;
1591 kvm_write_wall_clock(vcpu->kvm, data);
1592 break;
11c6bffa 1593 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 1594 case MSR_KVM_SYSTEM_TIME: {
12f9a48f 1595 kvmclock_reset(vcpu);
18068523
GOC		 1596
1597 vcpu->arch.time = data;
c285545f 1598 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
18068523
GOC		 1599
1600 /* we verify if the enable bit is set... */
1601 if (!(data & 1))
1602 break;
1603
1604 /* ...but clean it before doing the actual write */
1605 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
1606
18068523
GOC		 1607 vcpu->arch.time_page =
1608 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
18068523
GOC		 1609
1610 if (is_error_page(vcpu->arch.time_page)) {
1611 kvm_release_page_clean(vcpu->arch.time_page);
1612 vcpu->arch.time_page = NULL;
1613 }
18068523
GOC		 1614 break;
1615 }
344d9588
GN		 1616 case MSR_KVM_ASYNC_PF_EN:
1617 if (kvm_pv_enable_async_pf(vcpu, data))
1618 return 1;
1619 break;
c9aaa895
GC		 1620 case MSR_KVM_STEAL_TIME:
1621
1622 if (unlikely(!sched_info_on()))
1623 return 1;
1624
1625 if (data & KVM_STEAL_RESERVED_MASK)
1626 return 1;
1627
1628 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
1629 data & KVM_STEAL_VALID_BITS))
1630 return 1;
1631
1632 vcpu->arch.st.msr_val = data;
1633
1634 if (!(data & KVM_MSR_ENABLED))
1635 break;
1636
1637 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1638
1639 preempt_disable();
1640 accumulate_steal_time(vcpu);
1641 preempt_enable();
1642
1643 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
1644
1645 break;
1646
890ca9ae
HY		 1647 case MSR_IA32_MCG_CTL:
1648 case MSR_IA32_MCG_STATUS:
1649 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1650 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 1651
1652 /* Performance counters are not protected by a CPUID bit,
1653 * so we should check all of them in the generic path for the sake of
1654 * cross vendor migration.
1655 * Writing a zero into the event select MSRs disables them,
1656 * which we perfectly emulate ;-). Any other value should be at least
1657 * reported, some guests depend on them.
1658 */
1659 case MSR_P6_EVNTSEL0:
1660 case MSR_P6_EVNTSEL1:
1661 case MSR_K7_EVNTSEL0:
1662 case MSR_K7_EVNTSEL1:
1663 case MSR_K7_EVNTSEL2:
1664 case MSR_K7_EVNTSEL3:
1665 if (data != 0)
1666 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1667 "0x%x data 0x%llx\n", msr, data);
1668 break;
1669 /* at least RHEL 4 unconditionally writes to the perfctr registers,
1670 * so we ignore writes to make it happy.
1671 */
1672 case MSR_P6_PERFCTR0:
1673 case MSR_P6_PERFCTR1:
1674 case MSR_K7_PERFCTR0:
1675 case MSR_K7_PERFCTR1:
1676 case MSR_K7_PERFCTR2:
1677 case MSR_K7_PERFCTR3:
1678 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1679 "0x%x data 0x%llx\n", msr, data);
1680 break;
84e0cefa
JS		 1681 case MSR_K7_CLK_CTL:
1682 /*
1683 * Ignore all writes to this no longer documented MSR.
1684 * Writes are only relevant for old K7 processors,
1685 * all pre-dating SVM, but a recommended workaround from
1686 * AMD for these chips. It is possible to speicify the
1687 * affected processor models on the command line, hence
1688 * the need to ignore the workaround.
1689 */
1690 break;
55cd8e5a
GN		 1691 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1692 if (kvm_hv_msr_partition_wide(msr)) {
1693 int r;
1694 mutex_lock(&vcpu->kvm->lock);
1695 r = set_msr_hyperv_pw(vcpu, msr, data);
1696 mutex_unlock(&vcpu->kvm->lock);
1697 return r;
1698 } else
1699 return set_msr_hyperv(vcpu, msr, data);
1700 break;
91c9c3ed 1701 case MSR_IA32_BBL_CR_CTL3:
1702 /* Drop writes to this legacy MSR -- see rdmsr
1703 * counterpart for further detail.
1704 */
1705 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
1706 break;
15c4a640 1707 default:
ffde22ac
ES		 1708 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
1709 return xen_hvm_config(vcpu, data);
ed85c068
AP		 1710 if (!ignore_msrs) {
1711 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
1712 msr, data);
1713 return 1;
1714 } else {
1715 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
1716 msr, data);
1717 break;
1718 }
15c4a640
CO		 1719 }
1720 return 0;
1721}
1722EXPORT_SYMBOL_GPL(kvm_set_msr_common);
1723
1724
1725/*
1726 * Reads an msr value (of 'msr_index') into 'pdata'.
1727 * Returns 0 on success, non-0 otherwise.
1728 * Assumes vcpu_load() was already called.
1729 */
1730int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1731{
1732 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
1733}
1734
9ba075a6
AK		 1735static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1736{
0bed3b56
SY		 1737 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1738
9ba075a6
AK		 1739 if (!msr_mtrr_valid(msr))
1740 return 1;
1741
0bed3b56
SY		 1742 if (msr == MSR_MTRRdefType)
1743 *pdata = vcpu->arch.mtrr_state.def_type +
1744 (vcpu->arch.mtrr_state.enabled << 10);
1745 else if (msr == MSR_MTRRfix64K_00000)
1746 *pdata = p[0];
1747 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1748 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
1749 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1750 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
1751 else if (msr == MSR_IA32_CR_PAT)
1752 *pdata = vcpu->arch.pat;
1753 else { /* Variable MTRRs */
1754 int idx, is_mtrr_mask;
1755 u64 *pt;
1756
1757 idx = (msr - 0x200) / 2;
1758 is_mtrr_mask = msr - 0x200 - 2 * idx;
1759 if (!is_mtrr_mask)
1760 pt =
1761 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1762 else
1763 pt =
1764 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1765 *pdata = *pt;
1766 }
1767
9ba075a6
AK		 1768 return 0;
1769}
1770
890ca9ae 1771static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 1772{
1773 u64 data;
890ca9ae
HY		 1774 u64 mcg_cap = vcpu->arch.mcg_cap;
1775 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 1776
1777 switch (msr) {
15c4a640
CO		 1778 case MSR_IA32_P5_MC_ADDR:
1779 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 1780 data = 0;
1781 break;
15c4a640 1782 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 1783 data = vcpu->arch.mcg_cap;
1784 break;
c7ac679c 1785 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1786 if (!(mcg_cap & MCG_CTL_P))
1787 return 1;
1788 data = vcpu->arch.mcg_ctl;
1789 break;
1790 case MSR_IA32_MCG_STATUS:
1791 data = vcpu->arch.mcg_status;
1792 break;
1793 default:
1794 if (msr >= MSR_IA32_MC0_CTL &&
1795 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1796 u32 offset = msr - MSR_IA32_MC0_CTL;
1797 data = vcpu->arch.mce_banks[offset];
1798 break;
1799 }
1800 return 1;
1801 }
1802 *pdata = data;
1803 return 0;
1804}
1805
55cd8e5a
GN		 1806static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1807{
1808 u64 data = 0;
1809 struct kvm *kvm = vcpu->kvm;
1810
1811 switch (msr) {
1812 case HV_X64_MSR_GUEST_OS_ID:
1813 data = kvm->arch.hv_guest_os_id;
1814 break;
1815 case HV_X64_MSR_HYPERCALL:
1816 data = kvm->arch.hv_hypercall;
1817 break;
1818 default:
1819 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1820 return 1;
1821 }
1822
1823 *pdata = data;
1824 return 0;
1825}
1826
1827static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1828{
1829 u64 data = 0;
1830
1831 switch (msr) {
1832 case HV_X64_MSR_VP_INDEX: {
1833 int r;
1834 struct kvm_vcpu *v;
1835 kvm_for_each_vcpu(r, v, vcpu->kvm)
1836 if (v == vcpu)
1837 data = r;
1838 break;
1839 }
10388a07
GN		 1840 case HV_X64_MSR_EOI:
1841 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
1842 case HV_X64_MSR_ICR:
1843 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
1844 case HV_X64_MSR_TPR:
1845 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
14fa67ee 1846 case HV_X64_MSR_APIC_ASSIST_PAGE:
d1613ad5
MW		 1847 data = vcpu->arch.hv_vapic;
1848 break;
55cd8e5a
GN		 1849 default:
1850 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1851 return 1;
1852 }
1853 *pdata = data;
1854 return 0;
1855}
1856
890ca9ae
HY		 1857int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1858{
1859 u64 data;
1860
1861 switch (msr) {
890ca9ae 1862 case MSR_IA32_PLATFORM_ID:
15c4a640 1863 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 1864 case MSR_IA32_DEBUGCTLMSR:
1865 case MSR_IA32_LASTBRANCHFROMIP:
1866 case MSR_IA32_LASTBRANCHTOIP:
1867 case MSR_IA32_LASTINTFROMIP:
1868 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 1869 case MSR_K8_SYSCFG:
1870 case MSR_K7_HWCR:
61a6bd67 1871 case MSR_VM_HSAVE_PA:
1f3ee616
AS		 1872 case MSR_P6_PERFCTR0:
1873 case MSR_P6_PERFCTR1:
7fe29e0f
AS		 1874 case MSR_P6_EVNTSEL0:
1875 case MSR_P6_EVNTSEL1:
9e699624 1876 case MSR_K7_EVNTSEL0:
1f3ee616 1877 case MSR_K7_PERFCTR0:
1fdbd48c 1878 case MSR_K8_INT_PENDING_MSG:
c323c0e5 1879 case MSR_AMD64_NB_CFG:
f7c6d140 1880 case MSR_FAM10H_MMIO_CONF_BASE:
15c4a640
CO		 1881 data = 0;
1882 break;
742bc670
MT		 1883 case MSR_IA32_UCODE_REV:
1884 data = 0x100000000ULL;
1885 break;
9ba075a6
AK		 1886 case MSR_MTRRcap:
1887 data = 0x500 | KVM_NR_VAR_MTRR;
1888 break;
1889 case 0x200 ... 0x2ff:
1890 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 1891 case 0xcd: /* fsb frequency */
1892 data = 3;
1893 break;
7b914098
JS		 1894 /*
1895 * MSR_EBC_FREQUENCY_ID
1896 * Conservative value valid for even the basic CPU models.
1897 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
1898 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
1899 * and 266MHz for model 3, or 4. Set Core Clock
1900 * Frequency to System Bus Frequency Ratio to 1 (bits
1901 * 31:24) even though these are only valid for CPU
1902 * models > 2, however guests may end up dividing or
1903 * multiplying by zero otherwise.
1904 */
1905 case MSR_EBC_FREQUENCY_ID:
1906 data = 1 << 24;
1907 break;
15c4a640
CO		 1908 case MSR_IA32_APICBASE:
1909 data = kvm_get_apic_base(vcpu);
1910 break;
0105d1a5
GN		 1911 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1912 return kvm_x2apic_msr_read(vcpu, msr, pdata);
1913 break;
a3e06bbe
LJ		 1914 case MSR_IA32_TSCDEADLINE:
1915 data = kvm_get_lapic_tscdeadline_msr(vcpu);
1916 break;
15c4a640 1917 case MSR_IA32_MISC_ENABLE:
ad312c7c 1918 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 1919 break;
847f0ad8
AG		 1920 case MSR_IA32_PERF_STATUS:
1921 /* TSC increment by tick */
1922 data = 1000ULL;
1923 /* CPU multiplier */
1924 data |= (((uint64_t)4ULL) << 40);
1925 break;
15c4a640 1926 case MSR_EFER:
f6801dff 1927 data = vcpu->arch.efer;
15c4a640 1928 break;
18068523 1929 case MSR_KVM_WALL_CLOCK:
11c6bffa 1930 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1931 data = vcpu->kvm->arch.wall_clock;
1932 break;
1933 case MSR_KVM_SYSTEM_TIME:
11c6bffa 1934 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 1935 data = vcpu->arch.time;
1936 break;
344d9588
GN		 1937 case MSR_KVM_ASYNC_PF_EN:
1938 data = vcpu->arch.apf.msr_val;
1939 break;
c9aaa895
GC		 1940 case MSR_KVM_STEAL_TIME:
1941 data = vcpu->arch.st.msr_val;
1942 break;
890ca9ae
HY		 1943 case MSR_IA32_P5_MC_ADDR:
1944 case MSR_IA32_P5_MC_TYPE:
1945 case MSR_IA32_MCG_CAP:
1946 case MSR_IA32_MCG_CTL:
1947 case MSR_IA32_MCG_STATUS:
1948 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1949 return get_msr_mce(vcpu, msr, pdata);
84e0cefa
JS		 1950 case MSR_K7_CLK_CTL:
1951 /*
1952 * Provide expected ramp-up count for K7. All other
1953 * are set to zero, indicating minimum divisors for
1954 * every field.
1955 *
1956 * This prevents guest kernels on AMD host with CPU
1957 * type 6, model 8 and higher from exploding due to
1958 * the rdmsr failing.
1959 */
1960 data = 0x20000000;
1961 break;
55cd8e5a
GN		 1962 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1963 if (kvm_hv_msr_partition_wide(msr)) {
1964 int r;
1965 mutex_lock(&vcpu->kvm->lock);
1966 r = get_msr_hyperv_pw(vcpu, msr, pdata);
1967 mutex_unlock(&vcpu->kvm->lock);
1968 return r;
1969 } else
1970 return get_msr_hyperv(vcpu, msr, pdata);
1971 break;
91c9c3ed 1972 case MSR_IA32_BBL_CR_CTL3:
1973 /* This legacy MSR exists but isn't fully documented in current
1974 * silicon. It is however accessed by winxp in very narrow
1975 * scenarios where it sets bit #19, itself documented as
1976 * a "reserved" bit. Best effort attempt to source coherent
1977 * read data here should the balance of the register be
1978 * interpreted by the guest:
1979 *
1980 * L2 cache control register 3: 64GB range, 256KB size,
1981 * enabled, latency 0x1, configured
1982 */
1983 data = 0xbe702111;
1984 break;
15c4a640 1985 default:
ed85c068
AP		 1986 if (!ignore_msrs) {
1987 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
1988 return 1;
1989 } else {
1990 pr_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
1991 data = 0;
1992 }
1993 break;
15c4a640
CO		 1994 }
1995 *pdata = data;
1996 return 0;
1997}
1998EXPORT_SYMBOL_GPL(kvm_get_msr_common);
1999
313a3dc7
CO		 2000/*
2001 * Read or write a bunch of msrs. All parameters are kernel addresses.
2002 *
2003 * @return number of msrs set successfully.
2004 */
2005static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2006 struct kvm_msr_entry *entries,
2007 int (*do_msr)(struct kvm_vcpu *vcpu,
2008 unsigned index, u64 *data))
2009{
f656ce01 2010 int i, idx;
313a3dc7 2011
f656ce01 2012 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2013 for (i = 0; i < msrs->nmsrs; ++i)
2014 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2015 break;
f656ce01 2016 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2017
313a3dc7
CO		 2018 return i;
2019}
2020
2021/*
2022 * Read or write a bunch of msrs. Parameters are user addresses.
2023 *
2024 * @return number of msrs set successfully.
2025 */
2026static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2027 int (*do_msr)(struct kvm_vcpu *vcpu,
2028 unsigned index, u64 *data),
2029 int writeback)
2030{
2031 struct kvm_msrs msrs;
2032 struct kvm_msr_entry *entries;
2033 int r, n;
2034 unsigned size;
2035
2036 r = -EFAULT;
2037 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2038 goto out;
2039
2040 r = -E2BIG;
2041 if (msrs.nmsrs >= MAX_IO_MSRS)
2042 goto out;
2043
2044 r = -ENOMEM;
2045 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
7a73c028 2046 entries = kmalloc(size, GFP_KERNEL);
313a3dc7
CO		 2047 if (!entries)
2048 goto out;
2049
2050 r = -EFAULT;
2051 if (copy_from_user(entries, user_msrs->entries, size))
2052 goto out_free;
2053
2054 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2055 if (r < 0)
2056 goto out_free;
2057
2058 r = -EFAULT;
2059 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2060 goto out_free;
2061
2062 r = n;
2063
2064out_free:
7a73c028 2065 kfree(entries);
313a3dc7
CO		 2066out:
2067 return r;
2068}
2069
018d00d2
ZX		 2070int kvm_dev_ioctl_check_extension(long ext)
2071{
2072 int r;
2073
2074 switch (ext) {
2075 case KVM_CAP_IRQCHIP:
2076 case KVM_CAP_HLT:
2077 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2078 case KVM_CAP_SET_TSS_ADDR:
07716717 2079 case KVM_CAP_EXT_CPUID:
c8076604 2080 case KVM_CAP_CLOCKSOURCE:
7837699f 2081 case KVM_CAP_PIT:
a28e4f5a 2082 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2083 case KVM_CAP_MP_STATE:
ed848624 2084 case KVM_CAP_SYNC_MMU:
a355c85c 2085 case KVM_CAP_USER_NMI:
52d939a0 2086 case KVM_CAP_REINJECT_CONTROL:
4925663a 2087 case KVM_CAP_IRQ_INJECT_STATUS:
e56d532f 2088 case KVM_CAP_ASSIGN_DEV_IRQ:
721eecbf 2089 case KVM_CAP_IRQFD:
d34e6b17 2090 case KVM_CAP_IOEVENTFD:
c5ff41ce 2091 case KVM_CAP_PIT2:
e9f42757 2092 case KVM_CAP_PIT_STATE2:
b927a3ce 2093 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2094 case KVM_CAP_XEN_HVM:
afbcf7ab 2095 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 2096 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2097 case KVM_CAP_HYPERV:
10388a07 2098 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2099 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 2100 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2101 case KVM_CAP_DEBUGREGS:
d2be1651 2102 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2103 case KVM_CAP_XSAVE:
344d9588 2104 case KVM_CAP_ASYNC_PF:
92a1f12d 2105 case KVM_CAP_GET_TSC_KHZ:
018d00d2
ZX		 2106 r = 1;
2107 break;
542472b5
LV		 2108 case KVM_CAP_COALESCED_MMIO:
2109 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2110 break;
774ead3a
AK		 2111 case KVM_CAP_VAPIC:
2112 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2113 break;
f725230a 2114 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2115 r = KVM_SOFT_MAX_VCPUS;
2116 break;
2117 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2118 r = KVM_MAX_VCPUS;
2119 break;
a988b910
AK		 2120 case KVM_CAP_NR_MEMSLOTS:
2121 r = KVM_MEMORY_SLOTS;
2122 break;
a68a6a72
MT		 2123 case KVM_CAP_PV_MMU: /* obsolete */
2124 r = 0;
2f333bcb 2125 break;
62c476c7 2126 case KVM_CAP_IOMMU:
a1b60c1c 2127 r = iommu_present(&pci_bus_type);
62c476c7 2128 break;
890ca9ae
HY		 2129 case KVM_CAP_MCE:
2130 r = KVM_MAX_MCE_BANKS;
2131 break;
2d5b5a66
SY		 2132 case KVM_CAP_XCRS:
2133 r = cpu_has_xsave;
2134 break;
92a1f12d
JR		 2135 case KVM_CAP_TSC_CONTROL:
2136 r = kvm_has_tsc_control;
2137 break;
018d00d2
ZX		 2138 default:
2139 r = 0;
2140 break;
2141 }
2142 return r;
2143
2144}
2145
043405e1
CO		 2146long kvm_arch_dev_ioctl(struct file *filp,
2147 unsigned int ioctl, unsigned long arg)
2148{
2149 void __user *argp = (void __user *)arg;
2150 long r;
2151
2152 switch (ioctl) {
2153 case KVM_GET_MSR_INDEX_LIST: {
2154 struct kvm_msr_list __user *user_msr_list = argp;
2155 struct kvm_msr_list msr_list;
2156 unsigned n;
2157
2158 r = -EFAULT;
2159 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2160 goto out;
2161 n = msr_list.nmsrs;
2162 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2163 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2164 goto out;
2165 r = -E2BIG;
e125e7b6 2166 if (n < msr_list.nmsrs)
043405e1
CO		 2167 goto out;
2168 r = -EFAULT;
2169 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2170 num_msrs_to_save * sizeof(u32)))
2171 goto out;
e125e7b6 2172 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 2173 &emulated_msrs,
2174 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2175 goto out;
2176 r = 0;
2177 break;
2178 }
674eea0f
AK		 2179 case KVM_GET_SUPPORTED_CPUID: {
2180 struct kvm_cpuid2 __user *cpuid_arg = argp;
2181 struct kvm_cpuid2 cpuid;
2182
2183 r = -EFAULT;
2184 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2185 goto out;
2186 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
19355475 2187 cpuid_arg->entries);
674eea0f
AK		 2188 if (r)
2189 goto out;
2190
2191 r = -EFAULT;
2192 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2193 goto out;
2194 r = 0;
2195 break;
2196 }
890ca9ae
HY		 2197 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2198 u64 mce_cap;
2199
2200 mce_cap = KVM_MCE_CAP_SUPPORTED;
2201 r = -EFAULT;
2202 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2203 goto out;
2204 r = 0;
2205 break;
2206 }
043405e1
CO		 2207 default:
2208 r = -EINVAL;
2209 }
2210out:
2211 return r;
2212}
2213
f5f48ee1
SY		 2214static void wbinvd_ipi(void *garbage)
2215{
2216 wbinvd();
2217}
2218
2219static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2220{
2221 return vcpu->kvm->arch.iommu_domain &&
2222 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY);
2223}
2224
313a3dc7
CO		 2225void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2226{
f5f48ee1
SY		 2227 /* Address WBINVD may be executed by guest */
2228 if (need_emulate_wbinvd(vcpu)) {
2229 if (kvm_x86_ops->has_wbinvd_exit())
2230 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2231 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2232 smp_call_function_single(vcpu->cpu,
2233 wbinvd_ipi, NULL, 1);
2234 }
2235
313a3dc7 2236 kvm_x86_ops->vcpu_load(vcpu, cpu);
48434c20 2237 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
e48672fa 2238 /* Make sure TSC doesn't go backwards */
8f6055cb
JR		 2239 s64 tsc_delta;
2240 u64 tsc;
2241
d5c1785d 2242 tsc = kvm_x86_ops->read_l1_tsc(vcpu);
8f6055cb
JR		 2243 tsc_delta = !vcpu->arch.last_guest_tsc ? 0 :
2244 tsc - vcpu->arch.last_guest_tsc;
2245
e48672fa
ZA		 2246 if (tsc_delta < 0)
2247 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 2248 if (check_tsc_unstable()) {
e48672fa 2249 kvm_x86_ops->adjust_tsc_offset(vcpu, -tsc_delta);
c285545f 2250 vcpu->arch.tsc_catchup = 1;
c285545f 2251 }
1aa8ceef 2252 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c285545f
ZA		 2253 if (vcpu->cpu != cpu)
2254 kvm_migrate_timers(vcpu);
e48672fa 2255 vcpu->cpu = cpu;
6b7d7e76 2256 }
c9aaa895
GC		 2257
2258 accumulate_steal_time(vcpu);
2259 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2260}
2261
2262void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2263{
02daab21 2264 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2265 kvm_put_guest_fpu(vcpu);
d5c1785d 2266 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu);
313a3dc7
CO		 2267}
2268
07716717 2269static int is_efer_nx(void)
313a3dc7 2270{
e286e86e 2271 unsigned long long efer = 0;
313a3dc7 2272
e286e86e 2273 rdmsrl_safe(MSR_EFER, &efer);
07716717
DK		 2274 return efer & EFER_NX;
2275}
2276
2277static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
2278{
2279 int i;
2280 struct kvm_cpuid_entry2 *e, *entry;
2281
313a3dc7 2282 entry = NULL;
ad312c7c
ZX		 2283 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
2284 e = &vcpu->arch.cpuid_entries[i];
313a3dc7
CO		 2285 if (e->function == 0x80000001) {
2286 entry = e;
2287 break;
2288 }
2289 }
07716717 2290 if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) {
313a3dc7
CO		 2291 entry->edx &= ~(1 << 20);
2292 printk(KERN_INFO "kvm: guest NX capability removed\n");
2293 }
2294}
2295
07716717 2296/* when an old userspace process fills a new kernel module */
313a3dc7
CO		 2297static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
2298 struct kvm_cpuid *cpuid,
2299 struct kvm_cpuid_entry __user *entries)
07716717
DK		 2300{
2301 int r, i;
2302 struct kvm_cpuid_entry *cpuid_entries;
2303
2304 r = -E2BIG;
2305 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2306 goto out;
2307 r = -ENOMEM;
2308 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent);
2309 if (!cpuid_entries)
2310 goto out;
2311 r = -EFAULT;
2312 if (copy_from_user(cpuid_entries, entries,
2313 cpuid->nent * sizeof(struct kvm_cpuid_entry)))
2314 goto out_free;
2315 for (i = 0; i < cpuid->nent; i++) {
ad312c7c
ZX		 2316 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
2317 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
2318 vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx;
2319 vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx;
2320 vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx;
2321 vcpu->arch.cpuid_entries[i].index = 0;
2322 vcpu->arch.cpuid_entries[i].flags = 0;
2323 vcpu->arch.cpuid_entries[i].padding[0] = 0;
2324 vcpu->arch.cpuid_entries[i].padding[1] = 0;
2325 vcpu->arch.cpuid_entries[i].padding[2] = 0;
2326 }
2327 vcpu->arch.cpuid_nent = cpuid->nent;
07716717
DK		 2328 cpuid_fix_nx_cap(vcpu);
2329 r = 0;
fc61b800 2330 kvm_apic_set_version(vcpu);
0e851880 2331 kvm_x86_ops->cpuid_update(vcpu);
2acf923e 2332 update_cpuid(vcpu);
07716717
DK		 2333
2334out_free:
2335 vfree(cpuid_entries);
2336out:
2337 return r;
2338}
2339
2340static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 2341 struct kvm_cpuid2 *cpuid,
2342 struct kvm_cpuid_entry2 __user *entries)
313a3dc7
CO		 2343{
2344 int r;
2345
2346 r = -E2BIG;
2347 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2348 goto out;
2349 r = -EFAULT;
ad312c7c 2350 if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
07716717 2351 cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
313a3dc7 2352 goto out;
ad312c7c 2353 vcpu->arch.cpuid_nent = cpuid->nent;
fc61b800 2354 kvm_apic_set_version(vcpu);
0e851880 2355 kvm_x86_ops->cpuid_update(vcpu);
2acf923e 2356 update_cpuid(vcpu);
313a3dc7
CO		 2357 return 0;
2358
2359out:
2360 return r;
2361}
2362
07716717 2363static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 2364 struct kvm_cpuid2 *cpuid,
2365 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 2366{
2367 int r;
2368
2369 r = -E2BIG;
ad312c7c 2370 if (cpuid->nent < vcpu->arch.cpuid_nent)
07716717
DK		 2371 goto out;
2372 r = -EFAULT;
ad312c7c 2373 if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
19355475 2374 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 2375 goto out;
2376 return 0;
2377
2378out:
ad312c7c 2379 cpuid->nent = vcpu->arch.cpuid_nent;
07716717
DK		 2380 return r;
2381}
2382
945ee35e
AK		 2383static void cpuid_mask(u32 *word, int wordnum)
2384{
2385 *word &= boot_cpu_data.x86_capability[wordnum];
2386}
2387
07716717 2388static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function,
19355475 2389 u32 index)
07716717
DK		 2390{
2391 entry->function = function;
2392 entry->index = index;
2393 cpuid_count(entry->function, entry->index,
19355475 2394 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
07716717
DK		 2395 entry->flags = 0;
2396}
2397
24c82e57
AK		 2398static bool supported_xcr0_bit(unsigned bit)
2399{
2400 u64 mask = ((u64)1 << bit);
2401
2402 return mask & (XSTATE_FP | XSTATE_SSE | XSTATE_YMM) & host_xcr0;
2403}
2404
7faa4ee1
AK		 2405#define F(x) bit(X86_FEATURE_##x)
2406
07716717
DK		 2407static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
2408 u32 index, int *nent, int maxnent)
2409{
7faa4ee1 2410 unsigned f_nx = is_efer_nx() ? F(NX) : 0;
07716717 2411#ifdef CONFIG_X86_64
17cc3935
SY		 2412 unsigned f_gbpages = (kvm_x86_ops->get_lpage_level() == PT_PDPE_LEVEL)
2413 ? F(GBPAGES) : 0;
7faa4ee1
AK		 2414 unsigned f_lm = F(LM);
2415#else
17cc3935 2416 unsigned f_gbpages = 0;
7faa4ee1 2417 unsigned f_lm = 0;
07716717 2418#endif
4e47c7a6 2419 unsigned f_rdtscp = kvm_x86_ops->rdtscp_supported() ? F(RDTSCP) : 0;
7faa4ee1
AK		 2420
2421 /* cpuid 1.edx */
2422 const u32 kvm_supported_word0_x86_features =
2423 F(FPU) | F(VME) | F(DE) | F(PSE) |
2424 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
2425 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) |
2426 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
2427 F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLSH) |
2428 0 /* Reserved, DS, ACPI */ | F(MMX) |
2429 F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) |
2430 0 /* HTT, TM, Reserved, PBE */;
2431 /* cpuid 0x80000001.edx */
2432 const u32 kvm_supported_word1_x86_features =
2433 F(FPU) | F(VME) | F(DE) | F(PSE) |
2434 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
2435 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) |
2436 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
2437 F(PAT) | F(PSE36) | 0 /* Reserved */ |
2438 f_nx | 0 /* Reserved */ | F(MMXEXT) | F(MMX) |
4e47c7a6 2439 F(FXSR) | F(FXSR_OPT) | f_gbpages | f_rdtscp |
7faa4ee1
AK		 2440 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW);
2441 /* cpuid 1.ecx */
2442 const u32 kvm_supported_word4_x86_features =
6c3f6041 2443 F(XMM3) | F(PCLMULQDQ) | 0 /* DTES64, MONITOR */ |
d149c731
AK		 2444 0 /* DS-CPL, VMX, SMX, EST */ |
2445 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ |
2446 0 /* Reserved */ | F(CX16) | 0 /* xTPR Update, PDCM */ |
2447 0 /* Reserved, DCA */ | F(XMM4_1) |
0105d1a5 2448 F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) |
6d886fd0 2449 0 /* Reserved*/ | F(AES) | F(XSAVE) | 0 /* OSXSAVE */ | F(AVX) |
4a00efdf 2450 F(F16C) | F(RDRAND);
7faa4ee1 2451 /* cpuid 0x80000001.ecx */
07716717 2452 const u32 kvm_supported_word6_x86_features =
4c62a2dc 2453 F(LAHF_LM) | F(CMP_LEGACY) | 0 /*SVM*/ | 0 /* ExtApicSpace */ |
7faa4ee1 2454 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) |
7ef8aa72 2455 F(3DNOWPREFETCH) | 0 /* OSVW */ | 0 /* IBS */ | F(XOP) |
6d886fd0 2456 0 /* SKINIT, WDT, LWP */ | F(FMA4) | F(TBM);
07716717 2457
4429d5dc
B		 2458 /* cpuid 0xC0000001.edx */
2459 const u32 kvm_supported_word5_x86_features =
2460 F(XSTORE) | F(XSTORE_EN) | F(XCRYPT) | F(XCRYPT_EN) |
2461 F(ACE2) | F(ACE2_EN) | F(PHE) | F(PHE_EN) |
2462 F(PMM) | F(PMM_EN);
2463
611c120f
YW		 2464 /* cpuid 7.0.ebx */
2465 const u32 kvm_supported_word9_x86_features =
a01c8f9b 2466 F(SMEP) | F(FSGSBASE) | F(ERMS);
611c120f 2467
19355475 2468 /* all calls to cpuid_count() should be made on the same cpu */
07716717
DK		 2469 get_cpu();
2470 do_cpuid_1_ent(entry, function, index);
2471 ++*nent;
2472
2473 switch (function) {
2474 case 0:
2acf923e 2475 entry->eax = min(entry->eax, (u32)0xd);
07716717
DK		 2476 break;
2477 case 1:
2478 entry->edx &= kvm_supported_word0_x86_features;
945ee35e 2479 cpuid_mask(&entry->edx, 0);
7faa4ee1 2480 entry->ecx &= kvm_supported_word4_x86_features;
945ee35e 2481 cpuid_mask(&entry->ecx, 4);
0d1de2d9
GN		 2482 /* we support x2apic emulation even if host does not support
2483 * it since we emulate x2apic in software */
2484 entry->ecx |= F(X2APIC);
07716717
DK		 2485 break;
2486 /* function 2 entries are STATEFUL. That is, repeated cpuid commands
2487 * may return different values. This forces us to get_cpu() before
2488 * issuing the first command, and also to emulate this annoying behavior
2489 * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */
2490 case 2: {
2491 int t, times = entry->eax & 0xff;
2492
2493 entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
0fdf8e59 2494 entry->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
07716717
DK		 2495 for (t = 1; t < times && *nent < maxnent; ++t) {
2496 do_cpuid_1_ent(&entry[t], function, 0);
2497 entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
2498 ++*nent;
2499 }
2500 break;
2501 }
611c120f 2502 /* function 4 has additional index. */
07716717 2503 case 4: {
14af3f3c 2504 int i, cache_type;
07716717
DK		 2505
2506 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2507 /* read more entries until cache_type is zero */
14af3f3c
HH		 2508 for (i = 1; *nent < maxnent; ++i) {
2509 cache_type = entry[i - 1].eax & 0x1f;
07716717
DK		 2510 if (!cache_type)
2511 break;
14af3f3c
HH		 2512 do_cpuid_1_ent(&entry[i], function, i);
2513 entry[i].flags |=
07716717
DK		 2514 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2515 ++*nent;
2516 }
2517 break;
2518 }
611c120f
YW		 2519 case 7: {
2520 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2521 /* Mask ebx against host capbability word 9 */
2522 if (index == 0) {
2523 entry->ebx &= kvm_supported_word9_x86_features;
2524 cpuid_mask(&entry->ebx, 9);
2525 } else
2526 entry->ebx = 0;
2527 entry->eax = 0;
2528 entry->ecx = 0;
2529 entry->edx = 0;
2530 break;
2531 }
24c82e57
AK		 2532 case 9:
2533 break;
611c120f 2534 /* function 0xb has additional index. */
07716717 2535 case 0xb: {
14af3f3c 2536 int i, level_type;
07716717
DK		 2537
2538 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2539 /* read more entries until level_type is zero */
14af3f3c 2540 for (i = 1; *nent < maxnent; ++i) {
0853d2c1 2541 level_type = entry[i - 1].ecx & 0xff00;
07716717
DK		 2542 if (!level_type)
2543 break;
14af3f3c
HH		 2544 do_cpuid_1_ent(&entry[i], function, i);
2545 entry[i].flags |=
07716717
DK		 2546 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2547 ++*nent;
2548 }
2549 break;
2550 }
2acf923e 2551 case 0xd: {
02668b06 2552 int idx, i;
2acf923e
DC		 2553
2554 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
02668b06
AP		 2555 for (idx = 1, i = 1; *nent < maxnent && idx < 64; ++idx) {
2556 do_cpuid_1_ent(&entry[i], function, idx);
2557 if (entry[i].eax == 0 || !supported_xcr0_bit(idx))
20800bc9 2558 continue;
2acf923e
DC		 2559 entry[i].flags |=
2560 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2561 ++*nent;
02668b06 2562 ++i;
2acf923e
DC		 2563 }
2564 break;
2565 }
84478c82
GC		 2566 case KVM_CPUID_SIGNATURE: {
2567 char signature[12] = "KVMKVMKVM\0\0";
2568 u32 *sigptr = (u32 *)signature;
2569 entry->eax = 0;
2570 entry->ebx = sigptr[0];
2571 entry->ecx = sigptr[1];
2572 entry->edx = sigptr[2];
2573 break;
2574 }
2575 case KVM_CPUID_FEATURES:
2576 entry->eax = (1 << KVM_FEATURE_CLOCKSOURCE) |
2577 (1 << KVM_FEATURE_NOP_IO_DELAY) |
371bcf64 2578 (1 << KVM_FEATURE_CLOCKSOURCE2) |
32918924 2579 (1 << KVM_FEATURE_ASYNC_PF) |
371bcf64 2580 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT);
c9aaa895
GC		 2581
2582 if (sched_info_on())
2583 entry->eax |= (1 << KVM_FEATURE_STEAL_TIME);
2584
84478c82
GC		 2585 entry->ebx = 0;
2586 entry->ecx = 0;
2587 entry->edx = 0;
2588 break;
07716717
DK		 2589 case 0x80000000:
2590 entry->eax = min(entry->eax, 0x8000001a);
2591 break;
2592 case 0x80000001:
2593 entry->edx &= kvm_supported_word1_x86_features;
945ee35e 2594 cpuid_mask(&entry->edx, 1);
07716717 2595 entry->ecx &= kvm_supported_word6_x86_features;
945ee35e 2596 cpuid_mask(&entry->ecx, 6);
07716717 2597 break;
24c82e57
AK		 2598 case 0x80000008: {
2599 unsigned g_phys_as = (entry->eax >> 16) & 0xff;
2600 unsigned virt_as = max((entry->eax >> 8) & 0xff, 48U);
2601 unsigned phys_as = entry->eax & 0xff;
2602
2603 if (!g_phys_as)
2604 g_phys_as = phys_as;
2605 entry->eax = g_phys_as | (virt_as << 8);
2606 entry->ebx = entry->edx = 0;
2607 break;
2608 }
2609 case 0x80000019:
2610 entry->ecx = entry->edx = 0;
2611 break;
2612 case 0x8000001a:
2613 break;
2614 case 0x8000001d:
2615 break;
4429d5dc
B		 2616 /*Add support for Centaur's CPUID instruction*/
2617 case 0xC0000000:
2618 /*Just support up to 0xC0000004 now*/
2619 entry->eax = min(entry->eax, 0xC0000004);
2620 break;
2621 case 0xC0000001:
2622 entry->edx &= kvm_supported_word5_x86_features;
2623 cpuid_mask(&entry->edx, 5);
2624 break;
24c82e57
AK		 2625 case 3: /* Processor serial number */
2626 case 5: /* MONITOR/MWAIT */
2627 case 6: /* Thermal management */
2628 case 0xA: /* Architectural Performance Monitoring */
2629 case 0x80000007: /* Advanced power management */
4429d5dc
B		 2630 case 0xC0000002:
2631 case 0xC0000003:
2632 case 0xC0000004:
24c82e57
AK		 2633 default:
2634 entry->eax = entry->ebx = entry->ecx = entry->edx = 0;
4429d5dc 2635 break;
07716717 2636 }
d4330ef2
JR		 2637
2638 kvm_x86_ops->set_supported_cpuid(function, entry);
2639
07716717
DK		 2640 put_cpu();
2641}
2642
7faa4ee1
AK		 2643#undef F
2644
674eea0f 2645static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
19355475 2646 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 2647{
2648 struct kvm_cpuid_entry2 *cpuid_entries;
2649 int limit, nent = 0, r = -E2BIG;
2650 u32 func;
2651
2652 if (cpuid->nent < 1)
2653 goto out;
6a544355
AK		 2654 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2655 cpuid->nent = KVM_MAX_CPUID_ENTRIES;
07716717
DK		 2656 r = -ENOMEM;
2657 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent);
2658 if (!cpuid_entries)
2659 goto out;
2660
2661 do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent);
2662 limit = cpuid_entries[0].eax;
2663 for (func = 1; func <= limit && nent < cpuid->nent; ++func)
2664 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 2665 &nent, cpuid->nent);
07716717
DK		 2666 r = -E2BIG;
2667 if (nent >= cpuid->nent)
2668 goto out_free;
2669
2670 do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent);
2671 limit = cpuid_entries[nent - 1].eax;
2672 for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func)
2673 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 2674 &nent, cpuid->nent);
84478c82
GC		 2675
2676
2677
2678 r = -E2BIG;
2679 if (nent >= cpuid->nent)
2680 goto out_free;
2681
4429d5dc
B		 2682 /* Add support for Centaur's CPUID instruction. */
2683 if (boot_cpu_data.x86_vendor == X86_VENDOR_CENTAUR) {
2684 do_cpuid_ent(&cpuid_entries[nent], 0xC0000000, 0,
2685 &nent, cpuid->nent);
2686
2687 r = -E2BIG;
2688 if (nent >= cpuid->nent)
2689 goto out_free;
2690
2691 limit = cpuid_entries[nent - 1].eax;
2692 for (func = 0xC0000001;
2693 func <= limit && nent < cpuid->nent; ++func)
2694 do_cpuid_ent(&cpuid_entries[nent], func, 0,
2695 &nent, cpuid->nent);
2696
2697 r = -E2BIG;
2698 if (nent >= cpuid->nent)
2699 goto out_free;
2700 }
2701
84478c82
GC		 2702 do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_SIGNATURE, 0, &nent,
2703 cpuid->nent);
2704
2705 r = -E2BIG;
2706 if (nent >= cpuid->nent)
2707 goto out_free;
2708
2709 do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_FEATURES, 0, &nent,
2710 cpuid->nent);
2711
cb007648
MM		 2712 r = -E2BIG;
2713 if (nent >= cpuid->nent)
2714 goto out_free;
2715
07716717
DK		 2716 r = -EFAULT;
2717 if (copy_to_user(entries, cpuid_entries,
19355475 2718 nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 2719 goto out_free;
2720 cpuid->nent = nent;
2721 r = 0;
2722
2723out_free:
2724 vfree(cpuid_entries);
2725out:
2726 return r;
2727}
2728
313a3dc7
CO		 2729static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2730 struct kvm_lapic_state *s)
2731{
ad312c7c 2732 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2733
2734 return 0;
2735}
2736
2737static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2738 struct kvm_lapic_state *s)
2739{
ad312c7c 2740 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
313a3dc7 2741 kvm_apic_post_state_restore(vcpu);
cb142eb7 2742 update_cr8_intercept(vcpu);
313a3dc7
CO		 2743
2744 return 0;
2745}
2746
f77bc6a4
ZX		 2747static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2748 struct kvm_interrupt *irq)
2749{
2750 if (irq->irq < 0 || irq->irq >= 256)
2751 return -EINVAL;
2752 if (irqchip_in_kernel(vcpu->kvm))
2753 return -ENXIO;
f77bc6a4 2754
66fd3f7f 2755 kvm_queue_interrupt(vcpu, irq->irq, false);
3842d135 2756 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4 2757
f77bc6a4
ZX		 2758 return 0;
2759}
2760
c4abb7c9
JK		 2761static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2762{
c4abb7c9 2763 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2764
2765 return 0;
2766}
2767
b209749f
AK		 2768static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2769 struct kvm_tpr_access_ctl *tac)
2770{
2771 if (tac->flags)
2772 return -EINVAL;
2773 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2774 return 0;
2775}
2776
890ca9ae
HY		 2777static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2778 u64 mcg_cap)
2779{
2780 int r;
2781 unsigned bank_num = mcg_cap & 0xff, bank;
2782
2783 r = -EINVAL;
a9e38c3e 2784 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2785 goto out;
2786 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2787 goto out;
2788 r = 0;
2789 vcpu->arch.mcg_cap = mcg_cap;
2790 /* Init IA32_MCG_CTL to all 1s */
2791 if (mcg_cap & MCG_CTL_P)
2792 vcpu->arch.mcg_ctl = ~(u64)0;
2793 /* Init IA32_MCi_CTL to all 1s */
2794 for (bank = 0; bank < bank_num; bank++)
2795 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2796out:
2797 return r;
2798}
2799
2800static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2801 struct kvm_x86_mce *mce)
2802{
2803 u64 mcg_cap = vcpu->arch.mcg_cap;
2804 unsigned bank_num = mcg_cap & 0xff;
2805 u64 *banks = vcpu->arch.mce_banks;
2806
2807 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2808 return -EINVAL;
2809 /*
2810 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2811 * reporting is disabled
2812 */
2813 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2814 vcpu->arch.mcg_ctl != ~(u64)0)
2815 return 0;
2816 banks += 4 * mce->bank;
2817 /*
2818 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2819 * reporting is disabled for the bank
2820 */
2821 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2822 return 0;
2823 if (mce->status & MCI_STATUS_UC) {
2824 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2825 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 2826 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2827 return 0;
2828 }
2829 if (banks[1] & MCI_STATUS_VAL)
2830 mce->status |= MCI_STATUS_OVER;
2831 banks[2] = mce->addr;
2832 banks[3] = mce->misc;
2833 vcpu->arch.mcg_status = mce->mcg_status;
2834 banks[1] = mce->status;
2835 kvm_queue_exception(vcpu, MC_VECTOR);
2836 } else if (!(banks[1] & MCI_STATUS_VAL)
2837 || !(banks[1] & MCI_STATUS_UC)) {
2838 if (banks[1] & MCI_STATUS_VAL)
2839 mce->status |= MCI_STATUS_OVER;
2840 banks[2] = mce->addr;
2841 banks[3] = mce->misc;
2842 banks[1] = mce->status;
2843 } else
2844 banks[1] |= MCI_STATUS_OVER;
2845 return 0;
2846}
2847
3cfc3092
JK		 2848static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2849 struct kvm_vcpu_events *events)
2850{
7460fb4a 2851 process_nmi(vcpu);
03b82a30
JK		 2852 events->exception.injected =
2853 vcpu->arch.exception.pending &&
2854 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2855 events->exception.nr = vcpu->arch.exception.nr;
2856 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 2857 events->exception.pad = 0;
3cfc3092
JK		 2858 events->exception.error_code = vcpu->arch.exception.error_code;
2859
03b82a30
JK		 2860 events->interrupt.injected =
2861 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2862 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2863 events->interrupt.soft = 0;
48005f64
JK		 2864 events->interrupt.shadow =
2865 kvm_x86_ops->get_interrupt_shadow(vcpu,
2866 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
3cfc3092
JK		 2867
2868 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 2869 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 2870 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 2871 events->nmi.pad = 0;
3cfc3092
JK		 2872
2873 events->sipi_vector = vcpu->arch.sipi_vector;
2874
dab4b911 2875 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2876 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2877 | KVM_VCPUEVENT_VALID_SHADOW);
97e69aa6 2878 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 2879}
2880
2881static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2882 struct kvm_vcpu_events *events)
2883{
dab4b911 2884 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2885 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2886 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 2887 return -EINVAL;
2888
7460fb4a 2889 process_nmi(vcpu);
3cfc3092
JK		 2890 vcpu->arch.exception.pending = events->exception.injected;
2891 vcpu->arch.exception.nr = events->exception.nr;
2892 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2893 vcpu->arch.exception.error_code = events->exception.error_code;
2894
2895 vcpu->arch.interrupt.pending = events->interrupt.injected;
2896 vcpu->arch.interrupt.nr = events->interrupt.nr;
2897 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 2898 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2899 kvm_x86_ops->set_interrupt_shadow(vcpu,
2900 events->interrupt.shadow);
3cfc3092
JK		 2901
2902 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2903 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2904 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2905 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2906
dab4b911
JK		 2907 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR)
2908 vcpu->arch.sipi_vector = events->sipi_vector;
3cfc3092 2909
3842d135
AK		 2910 kvm_make_request(KVM_REQ_EVENT, vcpu);
2911
3cfc3092
JK		 2912 return 0;
2913}
2914
a1efbe77
JK		 2915static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2916 struct kvm_debugregs *dbgregs)
2917{
a1efbe77
JK		 2918 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2919 dbgregs->dr6 = vcpu->arch.dr6;
2920 dbgregs->dr7 = vcpu->arch.dr7;
2921 dbgregs->flags = 0;
97e69aa6 2922 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 2923}
2924
2925static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2926 struct kvm_debugregs *dbgregs)
2927{
2928 if (dbgregs->flags)
2929 return -EINVAL;
2930
a1efbe77
JK		 2931 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2932 vcpu->arch.dr6 = dbgregs->dr6;
2933 vcpu->arch.dr7 = dbgregs->dr7;
2934
a1efbe77
JK		 2935 return 0;
2936}
2937
2d5b5a66
SY		 2938static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
2939 struct kvm_xsave *guest_xsave)
2940{
2941 if (cpu_has_xsave)
2942 memcpy(guest_xsave->region,
2943 &vcpu->arch.guest_fpu.state->xsave,
f45755b8 2944 xstate_size);
2d5b5a66
SY		 2945 else {
2946 memcpy(guest_xsave->region,
2947 &vcpu->arch.guest_fpu.state->fxsave,
2948 sizeof(struct i387_fxsave_struct));
2949 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
2950 XSTATE_FPSSE;
2951 }
2952}
2953
2954static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
2955 struct kvm_xsave *guest_xsave)
2956{
2957 u64 xstate_bv =
2958 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
2959
2960 if (cpu_has_xsave)
2961 memcpy(&vcpu->arch.guest_fpu.state->xsave,
f45755b8 2962 guest_xsave->region, xstate_size);
2d5b5a66
SY		 2963 else {
2964 if (xstate_bv & ~XSTATE_FPSSE)
2965 return -EINVAL;
2966 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
2967 guest_xsave->region, sizeof(struct i387_fxsave_struct));
2968 }
2969 return 0;
2970}
2971
2972static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
2973 struct kvm_xcrs *guest_xcrs)
2974{
2975 if (!cpu_has_xsave) {
2976 guest_xcrs->nr_xcrs = 0;
2977 return;
2978 }
2979
2980 guest_xcrs->nr_xcrs = 1;
2981 guest_xcrs->flags = 0;
2982 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
2983 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
2984}
2985
2986static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
2987 struct kvm_xcrs *guest_xcrs)
2988{
2989 int i, r = 0;
2990
2991 if (!cpu_has_xsave)
2992 return -EINVAL;
2993
2994 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
2995 return -EINVAL;
2996
2997 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
2998 /* Only support XCR0 currently */
2999 if (guest_xcrs->xcrs[0].xcr == XCR_XFEATURE_ENABLED_MASK) {
3000 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
3001 guest_xcrs->xcrs[0].value);
3002 break;
3003 }
3004 if (r)
3005 r = -EINVAL;
3006 return r;
3007}
3008
313a3dc7
CO		 3009long kvm_arch_vcpu_ioctl(struct file *filp,
3010 unsigned int ioctl, unsigned long arg)
3011{
3012 struct kvm_vcpu *vcpu = filp->private_data;
3013 void __user *argp = (void __user *)arg;
3014 int r;
d1ac91d8
AK		 3015 union {
3016 struct kvm_lapic_state *lapic;
3017 struct kvm_xsave *xsave;
3018 struct kvm_xcrs *xcrs;
3019 void *buffer;
3020 } u;
3021
3022 u.buffer = NULL;
313a3dc7
CO		 3023 switch (ioctl) {
3024 case KVM_GET_LAPIC: {
2204ae3c
MT		 3025 r = -EINVAL;
3026 if (!vcpu->arch.apic)
3027 goto out;
d1ac91d8 3028 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3029
b772ff36 3030 r = -ENOMEM;
d1ac91d8 3031 if (!u.lapic)
b772ff36 3032 goto out;
d1ac91d8 3033 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3034 if (r)
3035 goto out;
3036 r = -EFAULT;
d1ac91d8 3037 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3038 goto out;
3039 r = 0;
3040 break;
3041 }
3042 case KVM_SET_LAPIC: {
2204ae3c
MT		 3043 r = -EINVAL;
3044 if (!vcpu->arch.apic)
3045 goto out;
d1ac91d8 3046 u.lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
b772ff36 3047 r = -ENOMEM;
d1ac91d8 3048 if (!u.lapic)
b772ff36 3049 goto out;
313a3dc7 3050 r = -EFAULT;
d1ac91d8 3051 if (copy_from_user(u.lapic, argp, sizeof(struct kvm_lapic_state)))
313a3dc7 3052 goto out;
d1ac91d8 3053 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3054 if (r)
3055 goto out;
3056 r = 0;
3057 break;
3058 }
f77bc6a4
ZX		 3059 case KVM_INTERRUPT: {
3060 struct kvm_interrupt irq;
3061
3062 r = -EFAULT;
3063 if (copy_from_user(&irq, argp, sizeof irq))
3064 goto out;
3065 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
3066 if (r)
3067 goto out;
3068 r = 0;
3069 break;
3070 }
c4abb7c9
JK		 3071 case KVM_NMI: {
3072 r = kvm_vcpu_ioctl_nmi(vcpu);
3073 if (r)
3074 goto out;
3075 r = 0;
3076 break;
3077 }
313a3dc7
CO		 3078 case KVM_SET_CPUID: {
3079 struct kvm_cpuid __user *cpuid_arg = argp;
3080 struct kvm_cpuid cpuid;
3081
3082 r = -EFAULT;
3083 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3084 goto out;
3085 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
3086 if (r)
3087 goto out;
3088 break;
3089 }
07716717
DK		 3090 case KVM_SET_CPUID2: {
3091 struct kvm_cpuid2 __user *cpuid_arg = argp;
3092 struct kvm_cpuid2 cpuid;
3093
3094 r = -EFAULT;
3095 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3096 goto out;
3097 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3098 cpuid_arg->entries);
07716717
DK		 3099 if (r)
3100 goto out;
3101 break;
3102 }
3103 case KVM_GET_CPUID2: {
3104 struct kvm_cpuid2 __user *cpuid_arg = argp;
3105 struct kvm_cpuid2 cpuid;
3106
3107 r = -EFAULT;
3108 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3109 goto out;
3110 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3111 cpuid_arg->entries);
07716717
DK		 3112 if (r)
3113 goto out;
3114 r = -EFAULT;
3115 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3116 goto out;
3117 r = 0;
3118 break;
3119 }
313a3dc7
CO		 3120 case KVM_GET_MSRS:
3121 r = msr_io(vcpu, argp, kvm_get_msr, 1);
3122 break;
3123 case KVM_SET_MSRS:
3124 r = msr_io(vcpu, argp, do_set_msr, 0);
3125 break;
b209749f
AK		 3126 case KVM_TPR_ACCESS_REPORTING: {
3127 struct kvm_tpr_access_ctl tac;
3128
3129 r = -EFAULT;
3130 if (copy_from_user(&tac, argp, sizeof tac))
3131 goto out;
3132 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3133 if (r)
3134 goto out;
3135 r = -EFAULT;
3136 if (copy_to_user(argp, &tac, sizeof tac))
3137 goto out;
3138 r = 0;
3139 break;
3140 };
b93463aa
AK		 3141 case KVM_SET_VAPIC_ADDR: {
3142 struct kvm_vapic_addr va;
3143
3144 r = -EINVAL;
3145 if (!irqchip_in_kernel(vcpu->kvm))
3146 goto out;
3147 r = -EFAULT;
3148 if (copy_from_user(&va, argp, sizeof va))
3149 goto out;
3150 r = 0;
3151 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
3152 break;
3153 }
890ca9ae
HY		 3154 case KVM_X86_SETUP_MCE: {
3155 u64 mcg_cap;
3156
3157 r = -EFAULT;
3158 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3159 goto out;
3160 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3161 break;
3162 }
3163 case KVM_X86_SET_MCE: {
3164 struct kvm_x86_mce mce;
3165
3166 r = -EFAULT;
3167 if (copy_from_user(&mce, argp, sizeof mce))
3168 goto out;
3169 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3170 break;
3171 }
3cfc3092
JK		 3172 case KVM_GET_VCPU_EVENTS: {
3173 struct kvm_vcpu_events events;
3174
3175 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3176
3177 r = -EFAULT;
3178 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3179 break;
3180 r = 0;
3181 break;
3182 }
3183 case KVM_SET_VCPU_EVENTS: {
3184 struct kvm_vcpu_events events;
3185
3186 r = -EFAULT;
3187 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3188 break;
3189
3190 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3191 break;
3192 }
a1efbe77
JK		 3193 case KVM_GET_DEBUGREGS: {
3194 struct kvm_debugregs dbgregs;
3195
3196 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3197
3198 r = -EFAULT;
3199 if (copy_to_user(argp, &dbgregs,
3200 sizeof(struct kvm_debugregs)))
3201 break;
3202 r = 0;
3203 break;
3204 }
3205 case KVM_SET_DEBUGREGS: {
3206 struct kvm_debugregs dbgregs;
3207
3208 r = -EFAULT;
3209 if (copy_from_user(&dbgregs, argp,
3210 sizeof(struct kvm_debugregs)))
3211 break;
3212
3213 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3214 break;
3215 }
2d5b5a66 3216 case KVM_GET_XSAVE: {
d1ac91d8 3217 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3218 r = -ENOMEM;
d1ac91d8 3219 if (!u.xsave)
2d5b5a66
SY		 3220 break;
3221
d1ac91d8 3222 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3223
3224 r = -EFAULT;
d1ac91d8 3225 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3226 break;
3227 r = 0;
3228 break;
3229 }
3230 case KVM_SET_XSAVE: {
d1ac91d8 3231 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3232 r = -ENOMEM;
d1ac91d8 3233 if (!u.xsave)
2d5b5a66
SY		 3234 break;
3235
3236 r = -EFAULT;
d1ac91d8 3237 if (copy_from_user(u.xsave, argp, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3238 break;
3239
d1ac91d8 3240 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3241 break;
3242 }
3243 case KVM_GET_XCRS: {
d1ac91d8 3244 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3245 r = -ENOMEM;
d1ac91d8 3246 if (!u.xcrs)
2d5b5a66
SY		 3247 break;
3248
d1ac91d8 3249 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3250
3251 r = -EFAULT;
d1ac91d8 3252 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3253 sizeof(struct kvm_xcrs)))
3254 break;
3255 r = 0;
3256 break;
3257 }
3258 case KVM_SET_XCRS: {
d1ac91d8 3259 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3260 r = -ENOMEM;
d1ac91d8 3261 if (!u.xcrs)
2d5b5a66
SY		 3262 break;
3263
3264 r = -EFAULT;
d1ac91d8 3265 if (copy_from_user(u.xcrs, argp,
2d5b5a66
SY		 3266 sizeof(struct kvm_xcrs)))
3267 break;
3268
d1ac91d8 3269 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3270 break;
3271 }
92a1f12d
JR		 3272 case KVM_SET_TSC_KHZ: {
3273 u32 user_tsc_khz;
3274
3275 r = -EINVAL;
3276 if (!kvm_has_tsc_control)
3277 break;
3278
3279 user_tsc_khz = (u32)arg;
3280
3281 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3282 goto out;
3283
3284 kvm_x86_ops->set_tsc_khz(vcpu, user_tsc_khz);
3285
3286 r = 0;
3287 goto out;
3288 }
3289 case KVM_GET_TSC_KHZ: {
3290 r = -EIO;
3291 if (check_tsc_unstable())
3292 goto out;
3293
3294 r = vcpu_tsc_khz(vcpu);
3295
3296 goto out;
3297 }
313a3dc7
CO		 3298 default:
3299 r = -EINVAL;
3300 }
3301out:
d1ac91d8 3302 kfree(u.buffer);
313a3dc7
CO		 3303 return r;
3304}
3305
1fe779f8
CO		 3306static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3307{
3308 int ret;
3309
3310 if (addr > (unsigned int)(-3 * PAGE_SIZE))
3311 return -1;
3312 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3313 return ret;
3314}
3315
b927a3ce
SY		 3316static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3317 u64 ident_addr)
3318{
3319 kvm->arch.ept_identity_map_addr = ident_addr;
3320 return 0;
3321}
3322
1fe779f8
CO		 3323static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3324 u32 kvm_nr_mmu_pages)
3325{
3326 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3327 return -EINVAL;
3328
79fac95e 3329 mutex_lock(&kvm->slots_lock);
7c8a83b7 3330 spin_lock(&kvm->mmu_lock);
1fe779f8
CO		 3331
3332 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3333 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3334
7c8a83b7 3335 spin_unlock(&kvm->mmu_lock);
79fac95e 3336 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3337 return 0;
3338}
3339
3340static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3341{
39de71ec 3342 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3343}
3344
1fe779f8
CO		 3345static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3346{
3347 int r;
3348
3349 r = 0;
3350 switch (chip->chip_id) {
3351 case KVM_IRQCHIP_PIC_MASTER:
3352 memcpy(&chip->chip.pic,
3353 &pic_irqchip(kvm)->pics[0],
3354 sizeof(struct kvm_pic_state));
3355 break;
3356 case KVM_IRQCHIP_PIC_SLAVE:
3357 memcpy(&chip->chip.pic,
3358 &pic_irqchip(kvm)->pics[1],
3359 sizeof(struct kvm_pic_state));
3360 break;
3361 case KVM_IRQCHIP_IOAPIC:
eba0226b 3362 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3363 break;
3364 default:
3365 r = -EINVAL;
3366 break;
3367 }
3368 return r;
3369}
3370
3371static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3372{
3373 int r;
3374
3375 r = 0;
3376 switch (chip->chip_id) {
3377 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3378 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3379 memcpy(&pic_irqchip(kvm)->pics[0],
3380 &chip->chip.pic,
3381 sizeof(struct kvm_pic_state));
f4f51050 3382 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3383 break;
3384 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3385 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3386 memcpy(&pic_irqchip(kvm)->pics[1],
3387 &chip->chip.pic,
3388 sizeof(struct kvm_pic_state));
f4f51050 3389 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3390 break;
3391 case KVM_IRQCHIP_IOAPIC:
eba0226b 3392 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3393 break;
3394 default:
3395 r = -EINVAL;
3396 break;
3397 }
3398 kvm_pic_update_irq(pic_irqchip(kvm));
3399 return r;
3400}
3401
e0f63cb9
SY		 3402static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3403{
3404 int r = 0;
3405
894a9c55 3406 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3407 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 3408 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3409 return r;
3410}
3411
3412static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3413{
3414 int r = 0;
3415
894a9c55 3416 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3417 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 3418 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3419 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3420 return r;
3421}
3422
3423static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3424{
3425 int r = 0;
3426
3427 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3428 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3429 sizeof(ps->channels));
3430 ps->flags = kvm->arch.vpit->pit_state.flags;
3431 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3432 memset(&ps->reserved, 0, sizeof(ps->reserved));
e9f42757
BK		 3433 return r;
3434}
3435
3436static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3437{
3438 int r = 0, start = 0;
3439 u32 prev_legacy, cur_legacy;
3440 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3441 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3442 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3443 if (!prev_legacy && cur_legacy)
3444 start = 1;
3445 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3446 sizeof(kvm->arch.vpit->pit_state.channels));
3447 kvm->arch.vpit->pit_state.flags = ps->flags;
3448 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 3449 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3450 return r;
3451}
3452
52d939a0
MT		 3453static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3454 struct kvm_reinject_control *control)
3455{
3456 if (!kvm->arch.vpit)
3457 return -ENXIO;
894a9c55 3458 mutex_lock(&kvm->arch.vpit->pit_state.lock);
52d939a0 3459 kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject;
894a9c55 3460 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3461 return 0;
3462}
3463
5bb064dc
ZX		 3464/*
3465 * Get (and clear) the dirty memory log for a memory slot.
3466 */
3467int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
3468 struct kvm_dirty_log *log)
3469{
87bf6e7d 3470 int r, i;
5bb064dc 3471 struct kvm_memory_slot *memslot;
87bf6e7d 3472 unsigned long n;
b050b015 3473 unsigned long is_dirty = 0;
5bb064dc 3474
79fac95e 3475 mutex_lock(&kvm->slots_lock);
5bb064dc 3476
b050b015
MT		 3477 r = -EINVAL;
3478 if (log->slot >= KVM_MEMORY_SLOTS)
3479 goto out;
3480
3481 memslot = &kvm->memslots->memslots[log->slot];
3482 r = -ENOENT;
3483 if (!memslot->dirty_bitmap)
3484 goto out;
3485
87bf6e7d 3486 n = kvm_dirty_bitmap_bytes(memslot);
b050b015 3487
b050b015
MT		 3488 for (i = 0; !is_dirty && i < n/sizeof(long); i++)
3489 is_dirty = memslot->dirty_bitmap[i];
5bb064dc
ZX		 3490
3491 /* If nothing is dirty, don't bother messing with page tables. */
3492 if (is_dirty) {
b050b015 3493 struct kvm_memslots *slots, *old_slots;
914ebccd 3494 unsigned long *dirty_bitmap;
b050b015 3495
515a0127
TY		 3496 dirty_bitmap = memslot->dirty_bitmap_head;
3497 if (memslot->dirty_bitmap == dirty_bitmap)
3498 dirty_bitmap += n / sizeof(long);
914ebccd 3499 memset(dirty_bitmap, 0, n);
b050b015 3500
914ebccd
TY		 3501 r = -ENOMEM;
3502 slots = kzalloc(sizeof(struct kvm_memslots), GFP_KERNEL);
515a0127 3503 if (!slots)
914ebccd 3504 goto out;
b050b015
MT		 3505 memcpy(slots, kvm->memslots, sizeof(struct kvm_memslots));
3506 slots->memslots[log->slot].dirty_bitmap = dirty_bitmap;
49c7754c 3507 slots->generation++;
b050b015
MT		 3508
3509 old_slots = kvm->memslots;
3510 rcu_assign_pointer(kvm->memslots, slots);
3511 synchronize_srcu_expedited(&kvm->srcu);
3512 dirty_bitmap = old_slots->memslots[log->slot].dirty_bitmap;
3513 kfree(old_slots);
914ebccd 3514
edde99ce
MT		 3515 spin_lock(&kvm->mmu_lock);
3516 kvm_mmu_slot_remove_write_access(kvm, log->slot);
3517 spin_unlock(&kvm->mmu_lock);
3518
914ebccd 3519 r = -EFAULT;
515a0127 3520 if (copy_to_user(log->dirty_bitmap, dirty_bitmap, n))
914ebccd 3521 goto out;
914ebccd
TY		 3522 } else {
3523 r = -EFAULT;
3524 if (clear_user(log->dirty_bitmap, n))
3525 goto out;
5bb064dc 3526 }
b050b015 3527
5bb064dc
ZX		 3528 r = 0;
3529out:
79fac95e 3530 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3531 return r;
3532}
3533
1fe779f8
CO		 3534long kvm_arch_vm_ioctl(struct file *filp,
3535 unsigned int ioctl, unsigned long arg)
3536{
3537 struct kvm *kvm = filp->private_data;
3538 void __user *argp = (void __user *)arg;
367e1319 3539 int r = -ENOTTY;
f0d66275
DH		 3540 /*
3541 * This union makes it completely explicit to gcc-3.x
3542 * that these two variables' stack usage should be
3543 * combined, not added together.
3544 */
3545 union {
3546 struct kvm_pit_state ps;
e9f42757 3547 struct kvm_pit_state2 ps2;
c5ff41ce 3548 struct kvm_pit_config pit_config;
f0d66275 3549 } u;
1fe779f8
CO		 3550
3551 switch (ioctl) {
3552 case KVM_SET_TSS_ADDR:
3553 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
3554 if (r < 0)
3555 goto out;
3556 break;
b927a3ce
SY		 3557 case KVM_SET_IDENTITY_MAP_ADDR: {
3558 u64 ident_addr;
3559
3560 r = -EFAULT;
3561 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3562 goto out;
3563 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
3564 if (r < 0)
3565 goto out;
3566 break;
3567 }
1fe779f8
CO		 3568 case KVM_SET_NR_MMU_PAGES:
3569 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
3570 if (r)
3571 goto out;
3572 break;
3573 case KVM_GET_NR_MMU_PAGES:
3574 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3575 break;
3ddea128
MT		 3576 case KVM_CREATE_IRQCHIP: {
3577 struct kvm_pic *vpic;
3578
3579 mutex_lock(&kvm->lock);
3580 r = -EEXIST;
3581 if (kvm->arch.vpic)
3582 goto create_irqchip_unlock;
1fe779f8 3583 r = -ENOMEM;
3ddea128
MT		 3584 vpic = kvm_create_pic(kvm);
3585 if (vpic) {
1fe779f8
CO		 3586 r = kvm_ioapic_init(kvm);
3587 if (r) {
175504cd 3588 mutex_lock(&kvm->slots_lock);
72bb2fcd 3589 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
743eeb0b
SL		 3590 &vpic->dev_master);
3591 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3592 &vpic->dev_slave);
3593 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3594 &vpic->dev_eclr);
175504cd 3595 mutex_unlock(&kvm->slots_lock);
3ddea128
MT		 3596 kfree(vpic);
3597 goto create_irqchip_unlock;
1fe779f8
CO		 3598 }
3599 } else
3ddea128
MT		 3600 goto create_irqchip_unlock;
3601 smp_wmb();
3602 kvm->arch.vpic = vpic;
3603 smp_wmb();
399ec807
AK		 3604 r = kvm_setup_default_irq_routing(kvm);
3605 if (r) {
175504cd 3606 mutex_lock(&kvm->slots_lock);
3ddea128 3607 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 3608 kvm_ioapic_destroy(kvm);
3609 kvm_destroy_pic(kvm);
3ddea128 3610 mutex_unlock(&kvm->irq_lock);
175504cd 3611 mutex_unlock(&kvm->slots_lock);
399ec807 3612 }
3ddea128
MT		 3613 create_irqchip_unlock:
3614 mutex_unlock(&kvm->lock);
1fe779f8 3615 break;
3ddea128 3616 }
7837699f 3617 case KVM_CREATE_PIT:
c5ff41ce
JK		 3618 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3619 goto create_pit;
3620 case KVM_CREATE_PIT2:
3621 r = -EFAULT;
3622 if (copy_from_user(&u.pit_config, argp,
3623 sizeof(struct kvm_pit_config)))
3624 goto out;
3625 create_pit:
79fac95e 3626 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3627 r = -EEXIST;
3628 if (kvm->arch.vpit)
3629 goto create_pit_unlock;
7837699f 3630 r = -ENOMEM;
c5ff41ce 3631 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3632 if (kvm->arch.vpit)
3633 r = 0;
269e05e4 3634 create_pit_unlock:
79fac95e 3635 mutex_unlock(&kvm->slots_lock);
7837699f 3636 break;
4925663a 3637 case KVM_IRQ_LINE_STATUS:
1fe779f8
CO		 3638 case KVM_IRQ_LINE: {
3639 struct kvm_irq_level irq_event;
3640
3641 r = -EFAULT;
3642 if (copy_from_user(&irq_event, argp, sizeof irq_event))
3643 goto out;
160d2f6c 3644 r = -ENXIO;
1fe779f8 3645 if (irqchip_in_kernel(kvm)) {
4925663a 3646 __s32 status;
4925663a
GN		 3647 status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3648 irq_event.irq, irq_event.level);
4925663a 3649 if (ioctl == KVM_IRQ_LINE_STATUS) {
160d2f6c 3650 r = -EFAULT;
4925663a
GN		 3651 irq_event.status = status;
3652 if (copy_to_user(argp, &irq_event,
3653 sizeof irq_event))
3654 goto out;
3655 }
1fe779f8
CO		 3656 r = 0;
3657 }
3658 break;
3659 }
3660 case KVM_GET_IRQCHIP: {
3661 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 3662 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 3663
f0d66275
DH		 3664 r = -ENOMEM;
3665 if (!chip)
1fe779f8 3666 goto out;
f0d66275
DH		 3667 r = -EFAULT;
3668 if (copy_from_user(chip, argp, sizeof *chip))
3669 goto get_irqchip_out;
1fe779f8
CO		 3670 r = -ENXIO;
3671 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3672 goto get_irqchip_out;
3673 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3674 if (r)
f0d66275 3675 goto get_irqchip_out;
1fe779f8 3676 r = -EFAULT;
f0d66275
DH		 3677 if (copy_to_user(argp, chip, sizeof *chip))
3678 goto get_irqchip_out;
1fe779f8 3679 r = 0;
f0d66275
DH		 3680 get_irqchip_out:
3681 kfree(chip);
3682 if (r)
3683 goto out;
1fe779f8
CO		 3684 break;
3685 }
3686 case KVM_SET_IRQCHIP: {
3687 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 3688 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 3689
f0d66275
DH		 3690 r = -ENOMEM;
3691 if (!chip)
1fe779f8 3692 goto out;
f0d66275
DH		 3693 r = -EFAULT;
3694 if (copy_from_user(chip, argp, sizeof *chip))
3695 goto set_irqchip_out;
1fe779f8
CO		 3696 r = -ENXIO;
3697 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3698 goto set_irqchip_out;
3699 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3700 if (r)
f0d66275 3701 goto set_irqchip_out;
1fe779f8 3702 r = 0;
f0d66275
DH		 3703 set_irqchip_out:
3704 kfree(chip);
3705 if (r)
3706 goto out;
1fe779f8
CO		 3707 break;
3708 }
e0f63cb9 3709 case KVM_GET_PIT: {
e0f63cb9 3710 r = -EFAULT;
f0d66275 3711 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3712 goto out;
3713 r = -ENXIO;
3714 if (!kvm->arch.vpit)
3715 goto out;
f0d66275 3716 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3717 if (r)
3718 goto out;
3719 r = -EFAULT;
f0d66275 3720 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3721 goto out;
3722 r = 0;
3723 break;
3724 }
3725 case KVM_SET_PIT: {
e0f63cb9 3726 r = -EFAULT;
f0d66275 3727 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3728 goto out;
3729 r = -ENXIO;
3730 if (!kvm->arch.vpit)
3731 goto out;
f0d66275 3732 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3733 if (r)
3734 goto out;
3735 r = 0;
3736 break;
3737 }
e9f42757
BK		 3738 case KVM_GET_PIT2: {
3739 r = -ENXIO;
3740 if (!kvm->arch.vpit)
3741 goto out;
3742 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3743 if (r)
3744 goto out;
3745 r = -EFAULT;
3746 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3747 goto out;
3748 r = 0;
3749 break;
3750 }
3751 case KVM_SET_PIT2: {
3752 r = -EFAULT;
3753 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3754 goto out;
3755 r = -ENXIO;
3756 if (!kvm->arch.vpit)
3757 goto out;
3758 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
3759 if (r)
3760 goto out;
3761 r = 0;
3762 break;
3763 }
52d939a0
MT		 3764 case KVM_REINJECT_CONTROL: {
3765 struct kvm_reinject_control control;
3766 r = -EFAULT;
3767 if (copy_from_user(&control, argp, sizeof(control)))
3768 goto out;
3769 r = kvm_vm_ioctl_reinject(kvm, &control);
3770 if (r)
3771 goto out;
3772 r = 0;
3773 break;
3774 }
ffde22ac
ES		 3775 case KVM_XEN_HVM_CONFIG: {
3776 r = -EFAULT;
3777 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3778 sizeof(struct kvm_xen_hvm_config)))
3779 goto out;
3780 r = -EINVAL;
3781 if (kvm->arch.xen_hvm_config.flags)
3782 goto out;
3783 r = 0;
3784 break;
3785 }
afbcf7ab 3786 case KVM_SET_CLOCK: {
afbcf7ab
GC		 3787 struct kvm_clock_data user_ns;
3788 u64 now_ns;
3789 s64 delta;
3790
3791 r = -EFAULT;
3792 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3793 goto out;
3794
3795 r = -EINVAL;
3796 if (user_ns.flags)
3797 goto out;
3798
3799 r = 0;
395c6b0a 3800 local_irq_disable();
759379dd 3801 now_ns = get_kernel_ns();
afbcf7ab 3802 delta = user_ns.clock - now_ns;
395c6b0a 3803 local_irq_enable();
afbcf7ab
GC		 3804 kvm->arch.kvmclock_offset = delta;
3805 break;
3806 }
3807 case KVM_GET_CLOCK: {
afbcf7ab
GC		 3808 struct kvm_clock_data user_ns;
3809 u64 now_ns;
3810
395c6b0a 3811 local_irq_disable();
759379dd 3812 now_ns = get_kernel_ns();
afbcf7ab 3813 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 3814 local_irq_enable();
afbcf7ab 3815 user_ns.flags = 0;
97e69aa6 3816 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 3817
3818 r = -EFAULT;
3819 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3820 goto out;
3821 r = 0;
3822 break;
3823 }
3824
1fe779f8
CO		 3825 default:
3826 ;
3827 }
3828out:
3829 return r;
3830}
3831
a16b043c 3832static void kvm_init_msr_list(void)
043405e1
CO		 3833{
3834 u32 dummy[2];
3835 unsigned i, j;
3836
e3267cbb
GC		 3837 /* skip the first msrs in the list. KVM-specific */
3838 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3839 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3840 continue;
3841 if (j < i)
3842 msrs_to_save[j] = msrs_to_save[i];
3843 j++;
3844 }
3845 num_msrs_to_save = j;
3846}
3847
bda9020e
MT		 3848static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3849 const void *v)
bbd9b64e 3850{
70252a10
AK		 3851 int handled = 0;
3852 int n;
3853
3854 do {
3855 n = min(len, 8);
3856 if (!(vcpu->arch.apic &&
3857 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v))
3858 && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3859 break;
3860 handled += n;
3861 addr += n;
3862 len -= n;
3863 v += n;
3864 } while (len);
bbd9b64e 3865
70252a10 3866 return handled;
bbd9b64e
CO		 3867}
3868
bda9020e 3869static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 3870{
70252a10
AK		 3871 int handled = 0;
3872 int n;
3873
3874 do {
3875 n = min(len, 8);
3876 if (!(vcpu->arch.apic &&
3877 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v))
3878 && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3879 break;
3880 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
3881 handled += n;
3882 addr += n;
3883 len -= n;
3884 v += n;
3885 } while (len);
bbd9b64e 3886
70252a10 3887 return handled;
bbd9b64e
CO		 3888}
3889
2dafc6c2
GN		 3890static void kvm_set_segment(struct kvm_vcpu *vcpu,
3891 struct kvm_segment *var, int seg)
3892{
3893 kvm_x86_ops->set_segment(vcpu, var, seg);
3894}
3895
3896void kvm_get_segment(struct kvm_vcpu *vcpu,
3897 struct kvm_segment *var, int seg)
3898{
3899 kvm_x86_ops->get_segment(vcpu, var, seg);
3900}
3901
c30a358d
JR		 3902static gpa_t translate_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
3903{
3904 return gpa;
3905}
3906
02f59dc9
JR		 3907static gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
3908{
3909 gpa_t t_gpa;
ab9ae313 3910 struct x86_exception exception;
02f59dc9
JR		 3911
3912 BUG_ON(!mmu_is_nested(vcpu));
3913
3914 /* NPT walks are always user-walks */
3915 access |= PFERR_USER_MASK;
ab9ae313 3916 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &exception);
02f59dc9
JR		 3917
3918 return t_gpa;
3919}
3920
ab9ae313
AK		 3921gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
3922 struct x86_exception *exception)
1871c602
GN		 3923{
3924 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 3925 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3926}
3927
ab9ae313
AK		 3928 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
3929 struct x86_exception *exception)
1871c602
GN		 3930{
3931 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3932 access |= PFERR_FETCH_MASK;
ab9ae313 3933 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3934}
3935
ab9ae313
AK		 3936gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
3937 struct x86_exception *exception)
1871c602
GN		 3938{
3939 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3940 access |= PFERR_WRITE_MASK;
ab9ae313 3941 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3942}
3943
3944/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 3945gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
3946 struct x86_exception *exception)
1871c602 3947{
ab9ae313 3948 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 3949}
3950
3951static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3952 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 3953 struct x86_exception *exception)
bbd9b64e
CO		 3954{
3955 void *data = val;
10589a46 3956 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 3957
3958 while (bytes) {
14dfe855 3959 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 3960 exception);
bbd9b64e 3961 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 3962 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 3963 int ret;
3964
bcc55cba 3965 if (gpa == UNMAPPED_GVA)
ab9ae313 3966 return X86EMUL_PROPAGATE_FAULT;
77c2002e 3967 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46 3968 if (ret < 0) {
c3cd7ffa 3969 r = X86EMUL_IO_NEEDED;
10589a46
MT		 3970 goto out;
3971 }
bbd9b64e 3972
77c2002e
IE		 3973 bytes -= toread;
3974 data += toread;
3975 addr += toread;
bbd9b64e 3976 }
10589a46 3977out:
10589a46 3978 return r;
bbd9b64e 3979}
77c2002e 3980
1871c602 3981/* used for instruction fetching */
0f65dd70
AK		 3982static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
3983 gva_t addr, void *val, unsigned int bytes,
bcc55cba 3984 struct x86_exception *exception)
1871c602 3985{
0f65dd70 3986 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 3987 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 3988
1871c602 3989 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
bcc55cba
AK		 3990 access | PFERR_FETCH_MASK,
3991 exception);
1871c602
GN		 3992}
3993
064aea77 3994int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 3995 gva_t addr, void *val, unsigned int bytes,
bcc55cba 3996 struct x86_exception *exception)
1871c602 3997{
0f65dd70 3998 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 3999 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4000
1871c602 4001 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4002 exception);
1871c602 4003}
064aea77 4004EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4005
0f65dd70
AK		 4006static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4007 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4008 struct x86_exception *exception)
1871c602 4009{
0f65dd70 4010 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4011 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4012}
4013
6a4d7550 4014int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4015 gva_t addr, void *val,
2dafc6c2 4016 unsigned int bytes,
bcc55cba 4017 struct x86_exception *exception)
77c2002e 4018{
0f65dd70 4019 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4020 void *data = val;
4021 int r = X86EMUL_CONTINUE;
4022
4023 while (bytes) {
14dfe855
JR		 4024 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4025 PFERR_WRITE_MASK,
ab9ae313 4026 exception);
77c2002e
IE		 4027 unsigned offset = addr & (PAGE_SIZE-1);
4028 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4029 int ret;
4030
bcc55cba 4031 if (gpa == UNMAPPED_GVA)
ab9ae313 4032 return X86EMUL_PROPAGATE_FAULT;
77c2002e
IE		 4033 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
4034 if (ret < 0) {
c3cd7ffa 4035 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4036 goto out;
4037 }
4038
4039 bytes -= towrite;
4040 data += towrite;
4041 addr += towrite;
4042 }
4043out:
4044 return r;
4045}
6a4d7550 4046EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4047
af7cc7d1
XG		 4048static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4049 gpa_t *gpa, struct x86_exception *exception,
4050 bool write)
4051{
4052 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4053
bebb106a
XG		 4054 if (vcpu_match_mmio_gva(vcpu, gva) &&
4055 check_write_user_access(vcpu, write, access,
4056 vcpu->arch.access)) {
4057 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4058 (gva & (PAGE_SIZE - 1));
4f022648 4059 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4060 return 1;
4061 }
4062
af7cc7d1
XG		 4063 if (write)
4064 access |= PFERR_WRITE_MASK;
4065
4066 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4067
4068 if (*gpa == UNMAPPED_GVA)
4069 return -1;
4070
4071 /* For APIC access vmexit */
4072 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4073 return 1;
4074
4f022648
XG		 4075 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4076 trace_vcpu_match_mmio(gva, *gpa, write, true);
bebb106a 4077 return 1;
4f022648 4078 }
bebb106a 4079
af7cc7d1
XG		 4080 return 0;
4081}
4082
3200f405 4083int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4084 const void *val, int bytes)
bbd9b64e
CO		 4085{
4086 int ret;
4087
4088 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 4089 if (ret < 0)
bbd9b64e 4090 return 0;
ad218f85 4091 kvm_mmu_pte_write(vcpu, gpa, val, bytes, 1);
bbd9b64e
CO		 4092 return 1;
4093}
4094
77d197b2
XG		 4095struct read_write_emulator_ops {
4096 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4097 int bytes);
4098 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4099 void *val, int bytes);
4100 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4101 int bytes, void *val);
4102 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4103 void *val, int bytes);
4104 bool write;
4105};
4106
4107static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4108{
4109 if (vcpu->mmio_read_completed) {
4110 memcpy(val, vcpu->mmio_data, bytes);
4111 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
4112 vcpu->mmio_phys_addr, *(u64 *)val);
4113 vcpu->mmio_read_completed = 0;
4114 return 1;
4115 }
4116
4117 return 0;
4118}
4119
4120static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4121 void *val, int bytes)
4122{
4123 return !kvm_read_guest(vcpu->kvm, gpa, val, bytes);
4124}
4125
4126static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4127 void *val, int bytes)
4128{
4129 return emulator_write_phys(vcpu, gpa, val, bytes);
4130}
4131
4132static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4133{
4134 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4135 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4136}
4137
4138static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4139 void *val, int bytes)
4140{
4141 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4142 return X86EMUL_IO_NEEDED;
4143}
4144
4145static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4146 void *val, int bytes)
4147{
4148 memcpy(vcpu->mmio_data, val, bytes);
4149 memcpy(vcpu->run->mmio.data, vcpu->mmio_data, 8);
4150 return X86EMUL_CONTINUE;
4151}
4152
4153static struct read_write_emulator_ops read_emultor = {
4154 .read_write_prepare = read_prepare,
4155 .read_write_emulate = read_emulate,
4156 .read_write_mmio = vcpu_mmio_read,
4157 .read_write_exit_mmio = read_exit_mmio,
4158};
4159
4160static struct read_write_emulator_ops write_emultor = {
4161 .read_write_emulate = write_emulate,
4162 .read_write_mmio = write_mmio,
4163 .read_write_exit_mmio = write_exit_mmio,
4164 .write = true,
4165};
4166
22388a3c
XG		 4167static int emulator_read_write_onepage(unsigned long addr, void *val,
4168 unsigned int bytes,
4169 struct x86_exception *exception,
4170 struct kvm_vcpu *vcpu,
4171 struct read_write_emulator_ops *ops)
bbd9b64e 4172{
af7cc7d1
XG		 4173 gpa_t gpa;
4174 int handled, ret;
22388a3c
XG		 4175 bool write = ops->write;
4176
4177 if (ops->read_write_prepare &&
4178 ops->read_write_prepare(vcpu, val, bytes))
4179 return X86EMUL_CONTINUE;
10589a46 4180
22388a3c 4181 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 4182
af7cc7d1 4183 if (ret < 0)
bbd9b64e 4184 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 4185
4186 /* For APIC access vmexit */
af7cc7d1 4187 if (ret)
bbd9b64e
CO		 4188 goto mmio;
4189
22388a3c 4190 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4191 return X86EMUL_CONTINUE;
4192
4193mmio:
4194 /*
4195 * Is this MMIO handled locally?
4196 */
22388a3c 4197 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4198 if (handled == bytes)
bbd9b64e 4199 return X86EMUL_CONTINUE;
bbd9b64e 4200
70252a10
AK		 4201 gpa += handled;
4202 bytes -= handled;
4203 val += handled;
4204
bbd9b64e 4205 vcpu->mmio_needed = 1;
411c35b7
GN		 4206 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4207 vcpu->run->mmio.phys_addr = vcpu->mmio_phys_addr = gpa;
cef4dea0
AK		 4208 vcpu->mmio_size = bytes;
4209 vcpu->run->mmio.len = min(vcpu->mmio_size, 8);
22388a3c 4210 vcpu->run->mmio.is_write = vcpu->mmio_is_write = write;
cef4dea0 4211 vcpu->mmio_index = 0;
bbd9b64e 4212
22388a3c 4213 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4214}
4215
22388a3c
XG		 4216int emulator_read_write(struct x86_emulate_ctxt *ctxt, unsigned long addr,
4217 void *val, unsigned int bytes,
4218 struct x86_exception *exception,
4219 struct read_write_emulator_ops *ops)
bbd9b64e 4220{
0f65dd70
AK		 4221 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4222
bbd9b64e
CO		 4223 /* Crossing a page boundary? */
4224 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
4225 int rc, now;
4226
4227 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4228 rc = emulator_read_write_onepage(addr, val, now, exception,
4229 vcpu, ops);
4230
bbd9b64e
CO		 4231 if (rc != X86EMUL_CONTINUE)
4232 return rc;
4233 addr += now;
4234 val += now;
4235 bytes -= now;
4236 }
22388a3c
XG		 4237
4238 return emulator_read_write_onepage(addr, val, bytes, exception,
4239 vcpu, ops);
4240}
4241
4242static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4243 unsigned long addr,
4244 void *val,
4245 unsigned int bytes,
4246 struct x86_exception *exception)
4247{
4248 return emulator_read_write(ctxt, addr, val, bytes,
4249 exception, &read_emultor);
4250}
4251
4252int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
4253 unsigned long addr,
4254 const void *val,
4255 unsigned int bytes,
4256 struct x86_exception *exception)
4257{
4258 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4259 exception, &write_emultor);
bbd9b64e 4260}
bbd9b64e 4261
daea3e73
AK		 4262#define CMPXCHG_TYPE(t, ptr, old, new) \
4263 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4264
4265#ifdef CONFIG_X86_64
4266# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4267#else
4268# define CMPXCHG64(ptr, old, new) \
9749a6c0 4269 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4270#endif
4271
0f65dd70
AK		 4272static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4273 unsigned long addr,
bbd9b64e
CO		 4274 const void *old,
4275 const void *new,
4276 unsigned int bytes,
0f65dd70 4277 struct x86_exception *exception)
bbd9b64e 4278{
0f65dd70 4279 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4280 gpa_t gpa;
4281 struct page *page;
4282 char *kaddr;
4283 bool exchanged;
2bacc55c 4284
daea3e73
AK		 4285 /* guests cmpxchg8b have to be emulated atomically */
4286 if (bytes > 8 || (bytes & (bytes - 1)))
4287 goto emul_write;
10589a46 4288
daea3e73 4289 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4290
daea3e73
AK		 4291 if (gpa == UNMAPPED_GVA ||
4292 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4293 goto emul_write;
2bacc55c 4294
daea3e73
AK		 4295 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4296 goto emul_write;
72dc67a6 4297
daea3e73 4298 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
c19b8bd6
WY		 4299 if (is_error_page(page)) {
4300 kvm_release_page_clean(page);
4301 goto emul_write;
4302 }
72dc67a6 4303
daea3e73
AK		 4304 kaddr = kmap_atomic(page, KM_USER0);
4305 kaddr += offset_in_page(gpa);
4306 switch (bytes) {
4307 case 1:
4308 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4309 break;
4310 case 2:
4311 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4312 break;
4313 case 4:
4314 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4315 break;
4316 case 8:
4317 exchanged = CMPXCHG64(kaddr, old, new);
4318 break;
4319 default:
4320 BUG();
2bacc55c 4321 }
daea3e73
AK		 4322 kunmap_atomic(kaddr, KM_USER0);
4323 kvm_release_page_dirty(page);
4324
4325 if (!exchanged)
4326 return X86EMUL_CMPXCHG_FAILED;
4327
8f6abd06
GN		 4328 kvm_mmu_pte_write(vcpu, gpa, new, bytes, 1);
4329
4330 return X86EMUL_CONTINUE;
4a5f48f6 4331
3200f405 4332emul_write:
daea3e73 4333 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4334
0f65dd70 4335 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4336}
4337
cf8f70bf
GN		 4338static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4339{
4340 /* TODO: String I/O for in kernel device */
4341 int r;
4342
4343 if (vcpu->arch.pio.in)
4344 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
4345 vcpu->arch.pio.size, pd);
4346 else
4347 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
4348 vcpu->arch.pio.port, vcpu->arch.pio.size,
4349 pd);
4350 return r;
4351}
4352
4353
ca1d4a9e
AK		 4354static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4355 int size, unsigned short port, void *val,
4356 unsigned int count)
cf8f70bf 4357{
ca1d4a9e
AK		 4358 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4359
7972995b 4360 if (vcpu->arch.pio.count)
cf8f70bf
GN		 4361 goto data_avail;
4362
61cfab2e 4363 trace_kvm_pio(0, port, size, count);
cf8f70bf
GN		 4364
4365 vcpu->arch.pio.port = port;
4366 vcpu->arch.pio.in = 1;
7972995b 4367 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4368 vcpu->arch.pio.size = size;
4369
4370 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
4371 data_avail:
4372 memcpy(val, vcpu->arch.pio_data, size * count);
7972995b 4373 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4374 return 1;
4375 }
4376
4377 vcpu->run->exit_reason = KVM_EXIT_IO;
4378 vcpu->run->io.direction = KVM_EXIT_IO_IN;
4379 vcpu->run->io.size = size;
4380 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4381 vcpu->run->io.count = count;
4382 vcpu->run->io.port = port;
4383
4384 return 0;
4385}
4386
ca1d4a9e
AK		 4387static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4388 int size, unsigned short port,
4389 const void *val, unsigned int count)
cf8f70bf 4390{
ca1d4a9e
AK		 4391 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4392
61cfab2e 4393 trace_kvm_pio(1, port, size, count);
cf8f70bf
GN		 4394
4395 vcpu->arch.pio.port = port;
4396 vcpu->arch.pio.in = 0;
7972995b 4397 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4398 vcpu->arch.pio.size = size;
4399
4400 memcpy(vcpu->arch.pio_data, val, size * count);
4401
4402 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4403 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4404 return 1;
4405 }
4406
4407 vcpu->run->exit_reason = KVM_EXIT_IO;
4408 vcpu->run->io.direction = KVM_EXIT_IO_OUT;
4409 vcpu->run->io.size = size;
4410 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4411 vcpu->run->io.count = count;
4412 vcpu->run->io.port = port;
4413
4414 return 0;
4415}
4416
bbd9b64e
CO		 4417static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4418{
4419 return kvm_x86_ops->get_segment_base(vcpu, seg);
4420}
4421
3cb16fe7 4422static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4423{
3cb16fe7 4424 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4425}
4426
f5f48ee1
SY		 4427int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4428{
4429 if (!need_emulate_wbinvd(vcpu))
4430 return X86EMUL_CONTINUE;
4431
4432 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4433 int cpu = get_cpu();
4434
4435 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4436 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4437 wbinvd_ipi, NULL, 1);
2eec7343 4438 put_cpu();
f5f48ee1 4439 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4440 } else
4441 wbinvd();
f5f48ee1
SY		 4442 return X86EMUL_CONTINUE;
4443}
4444EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4445
bcaf5cc5
AK		 4446static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4447{
4448 kvm_emulate_wbinvd(emul_to_vcpu(ctxt));
4449}
4450
717746e3 4451int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
bbd9b64e 4452{
717746e3 4453 return _kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4454}
4455
717746e3 4456int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
bbd9b64e 4457{
338dbc97 4458
717746e3 4459 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4460}
4461
52a46617 4462static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4463{
52a46617 4464 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4465}
4466
717746e3 4467static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4468{
717746e3 4469 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4470 unsigned long value;
4471
4472 switch (cr) {
4473 case 0:
4474 value = kvm_read_cr0(vcpu);
4475 break;
4476 case 2:
4477 value = vcpu->arch.cr2;
4478 break;
4479 case 3:
9f8fe504 4480 value = kvm_read_cr3(vcpu);
52a46617
GN		 4481 break;
4482 case 4:
4483 value = kvm_read_cr4(vcpu);
4484 break;
4485 case 8:
4486 value = kvm_get_cr8(vcpu);
4487 break;
4488 default:
4489 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
4490 return 0;
4491 }
4492
4493 return value;
4494}
4495
717746e3 4496static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4497{
717746e3 4498 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4499 int res = 0;
4500
52a46617
GN		 4501 switch (cr) {
4502 case 0:
49a9b07e 4503 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4504 break;
4505 case 2:
4506 vcpu->arch.cr2 = val;
4507 break;
4508 case 3:
2390218b 4509 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4510 break;
4511 case 4:
a83b29c6 4512 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4513 break;
4514 case 8:
eea1cff9 4515 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4516 break;
4517 default:
4518 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
0f12244f 4519 res = -1;
52a46617 4520 }
0f12244f
GN		 4521
4522 return res;
52a46617
GN		 4523}
4524
717746e3 4525static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 4526{
717746e3 4527 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 4528}
4529
4bff1e86 4530static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 4531{
4bff1e86 4532 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 4533}
4534
4bff1e86 4535static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 4536{
4bff1e86 4537 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 4538}
4539
1ac9d0cf
AK		 4540static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4541{
4542 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4543}
4544
4545static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4546{
4547 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4548}
4549
4bff1e86
AK		 4550static unsigned long emulator_get_cached_segment_base(
4551 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 4552{
4bff1e86 4553 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 4554}
4555
1aa36616
AK		 4556static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4557 struct desc_struct *desc, u32 *base3,
4558 int seg)
2dafc6c2
GN		 4559{
4560 struct kvm_segment var;
4561
4bff1e86 4562 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 4563 *selector = var.selector;
2dafc6c2
GN		 4564
4565 if (var.unusable)
4566 return false;
4567
4568 if (var.g)
4569 var.limit >>= 12;
4570 set_desc_limit(desc, var.limit);
4571 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 4572#ifdef CONFIG_X86_64
4573 if (base3)
4574 *base3 = var.base >> 32;
4575#endif
2dafc6c2
GN		 4576 desc->type = var.type;
4577 desc->s = var.s;
4578 desc->dpl = var.dpl;
4579 desc->p = var.present;
4580 desc->avl = var.avl;
4581 desc->l = var.l;
4582 desc->d = var.db;
4583 desc->g = var.g;
4584
4585 return true;
4586}
4587
1aa36616
AK		 4588static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4589 struct desc_struct *desc, u32 base3,
4590 int seg)
2dafc6c2 4591{
4bff1e86 4592 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 4593 struct kvm_segment var;
4594
1aa36616 4595 var.selector = selector;
2dafc6c2 4596 var.base = get_desc_base(desc);
5601d05b
GN		 4597#ifdef CONFIG_X86_64
4598 var.base |= ((u64)base3) << 32;
4599#endif
2dafc6c2
GN		 4600 var.limit = get_desc_limit(desc);
4601 if (desc->g)
4602 var.limit = (var.limit << 12) | 0xfff;
4603 var.type = desc->type;
4604 var.present = desc->p;
4605 var.dpl = desc->dpl;
4606 var.db = desc->d;
4607 var.s = desc->s;
4608 var.l = desc->l;
4609 var.g = desc->g;
4610 var.avl = desc->avl;
4611 var.present = desc->p;
4612 var.unusable = !var.present;
4613 var.padding = 0;
4614
4615 kvm_set_segment(vcpu, &var, seg);
4616 return;
4617}
4618
717746e3
AK		 4619static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4620 u32 msr_index, u64 *pdata)
4621{
4622 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
4623}
4624
4625static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4626 u32 msr_index, u64 data)
4627{
4628 return kvm_set_msr(emul_to_vcpu(ctxt), msr_index, data);
4629}
4630
6c3287f7
AK		 4631static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4632{
4633 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4634}
4635
5037f6f3
AK		 4636static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4637{
4638 preempt_disable();
5197b808 4639 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 4640 /*
4641 * CR0.TS may reference the host fpu state, not the guest fpu state,
4642 * so it may be clear at this point.
4643 */
4644 clts();
4645}
4646
4647static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4648{
4649 preempt_enable();
4650}
4651
2953538e 4652static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 4653 struct x86_instruction_info *info,
c4f035c6
AK		 4654 enum x86_intercept_stage stage)
4655{
2953538e 4656 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 4657}
4658
14af3f3c 4659static struct x86_emulate_ops emulate_ops = {
1871c602 4660 .read_std = kvm_read_guest_virt_system,
2dafc6c2 4661 .write_std = kvm_write_guest_virt_system,
1871c602 4662 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 4663 .read_emulated = emulator_read_emulated,
4664 .write_emulated = emulator_write_emulated,
4665 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 4666 .invlpg = emulator_invlpg,
cf8f70bf
GN		 4667 .pio_in_emulated = emulator_pio_in_emulated,
4668 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 4669 .get_segment = emulator_get_segment,
4670 .set_segment = emulator_set_segment,
5951c442 4671 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 4672 .get_gdt = emulator_get_gdt,
160ce1f1 4673 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 4674 .set_gdt = emulator_set_gdt,
4675 .set_idt = emulator_set_idt,
52a46617
GN		 4676 .get_cr = emulator_get_cr,
4677 .set_cr = emulator_set_cr,
9c537244 4678 .cpl = emulator_get_cpl,
35aa5375
GN		 4679 .get_dr = emulator_get_dr,
4680 .set_dr = emulator_set_dr,
717746e3
AK		 4681 .set_msr = emulator_set_msr,
4682 .get_msr = emulator_get_msr,
6c3287f7 4683 .halt = emulator_halt,
bcaf5cc5 4684 .wbinvd = emulator_wbinvd,
d6aa1000 4685 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 4686 .get_fpu = emulator_get_fpu,
4687 .put_fpu = emulator_put_fpu,
c4f035c6 4688 .intercept = emulator_intercept,
bbd9b64e
CO		 4689};
4690
5fdbf976
MT		 4691static void cache_all_regs(struct kvm_vcpu *vcpu)
4692{
4693 kvm_register_read(vcpu, VCPU_REGS_RAX);
4694 kvm_register_read(vcpu, VCPU_REGS_RSP);
4695 kvm_register_read(vcpu, VCPU_REGS_RIP);
4696 vcpu->arch.regs_dirty = ~0;
4697}
4698
95cb2295
GN		 4699static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4700{
4701 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
4702 /*
4703 * an sti; sti; sequence only disable interrupts for the first
4704 * instruction. So, if the last instruction, be it emulated or
4705 * not, left the system with the INT_STI flag enabled, it
4706 * means that the last instruction is an sti. We should not
4707 * leave the flag on in this case. The same goes for mov ss
4708 */
4709 if (!(int_shadow & mask))
4710 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4711}
4712
54b8486f
GN		 4713static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4714{
4715 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 4716 if (ctxt->exception.vector == PF_VECTOR)
6389ee94 4717 kvm_propagate_fault(vcpu, &ctxt->exception);
da9cb575
AK		 4718 else if (ctxt->exception.error_code_valid)
4719 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4720 ctxt->exception.error_code);
54b8486f 4721 else
da9cb575 4722 kvm_queue_exception(vcpu, ctxt->exception.vector);
54b8486f
GN		 4723}
4724
9dac77fa 4725static void init_decode_cache(struct x86_emulate_ctxt *ctxt,
b5c9ff73
TY		 4726 const unsigned long *regs)
4727{
9dac77fa
AK		 4728 memset(&ctxt->twobyte, 0,
4729 (void *)&ctxt->regs - (void *)&ctxt->twobyte);
4730 memcpy(ctxt->regs, regs, sizeof(ctxt->regs));
b5c9ff73 4731
9dac77fa
AK		 4732 ctxt->fetch.start = 0;
4733 ctxt->fetch.end = 0;
4734 ctxt->io_read.pos = 0;
4735 ctxt->io_read.end = 0;
4736 ctxt->mem_read.pos = 0;
4737 ctxt->mem_read.end = 0;
b5c9ff73
TY		 4738}
4739
8ec4722d
MG		 4740static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4741{
adf52235 4742 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 4743 int cs_db, cs_l;
4744
2aab2c5b
GN		 4745 /*
4746 * TODO: fix emulate.c to use guest_read/write_register
4747 * instead of direct ->regs accesses, can save hundred cycles
4748 * on Intel for instructions that don't read/change RSP, for
4749 * for example.
4750 */
8ec4722d
MG		 4751 cache_all_regs(vcpu);
4752
4753 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4754
adf52235
TY		 4755 ctxt->eflags = kvm_get_rflags(vcpu);
4756 ctxt->eip = kvm_rip_read(vcpu);
4757 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4758 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
4759 cs_l ? X86EMUL_MODE_PROT64 :
4760 cs_db ? X86EMUL_MODE_PROT32 :
4761 X86EMUL_MODE_PROT16;
4762 ctxt->guest_mode = is_guest_mode(vcpu);
4763
9dac77fa 4764 init_decode_cache(ctxt, vcpu->arch.regs);
7ae441ea 4765 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 4766}
4767
71f9833b 4768int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 4769{
9d74191a 4770 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 4771 int ret;
4772
4773 init_emulate_ctxt(vcpu);
4774
9dac77fa
AK		 4775 ctxt->op_bytes = 2;
4776 ctxt->ad_bytes = 2;
4777 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 4778 ret = emulate_int_real(ctxt, irq);
63995653
MG		 4779
4780 if (ret != X86EMUL_CONTINUE)
4781 return EMULATE_FAIL;
4782
9dac77fa
AK		 4783 ctxt->eip = ctxt->_eip;
4784 memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs);
9d74191a
TY		 4785 kvm_rip_write(vcpu, ctxt->eip);
4786 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 4787
4788 if (irq == NMI_VECTOR)
7460fb4a 4789 vcpu->arch.nmi_pending = 0;
63995653
MG		 4790 else
4791 vcpu->arch.interrupt.pending = false;
4792
4793 return EMULATE_DONE;
4794}
4795EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4796
6d77dbfc
GN		 4797static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4798{
fc3a9157
JR		 4799 int r = EMULATE_DONE;
4800
6d77dbfc
GN		 4801 ++vcpu->stat.insn_emulation_fail;
4802 trace_kvm_emulate_insn_failed(vcpu);
fc3a9157
JR		 4803 if (!is_guest_mode(vcpu)) {
4804 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4805 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4806 vcpu->run->internal.ndata = 0;
4807 r = EMULATE_FAIL;
4808 }
6d77dbfc 4809 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 4810
4811 return r;
6d77dbfc
GN		 4812}
4813
a6f177ef
GN		 4814static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t gva)
4815{
4816 gpa_t gpa;
4817
68be0803
GN		 4818 if (tdp_enabled)
4819 return false;
4820
a6f177ef
GN		 4821 /*
4822 * if emulation was due to access to shadowed page table
4823 * and it failed try to unshadow page and re-entetr the
4824 * guest to let CPU execute the instruction.
4825 */
4826 if (kvm_mmu_unprotect_page_virt(vcpu, gva))
4827 return true;
4828
4829 gpa = kvm_mmu_gva_to_gpa_system(vcpu, gva, NULL);
4830
4831 if (gpa == UNMAPPED_GVA)
4832 return true; /* let cpu generate fault */
4833
4834 if (!kvm_is_error_hva(gfn_to_hva(vcpu->kvm, gpa >> PAGE_SHIFT)))
4835 return true;
4836
4837 return false;
4838}
4839
51d8b661
AP		 4840int x86_emulate_instruction(struct kvm_vcpu *vcpu,
4841 unsigned long cr2,
dc25e89e
AP		 4842 int emulation_type,
4843 void *insn,
4844 int insn_len)
bbd9b64e 4845{
95cb2295 4846 int r;
9d74191a 4847 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 4848 bool writeback = true;
bbd9b64e 4849
26eef70c 4850 kvm_clear_exception_queue(vcpu);
8d7d8102 4851
571008da 4852 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 4853 init_emulate_ctxt(vcpu);
9d74191a
TY		 4854 ctxt->interruptibility = 0;
4855 ctxt->have_exception = false;
4856 ctxt->perm_ok = false;
bbd9b64e 4857
9d74191a 4858 ctxt->only_vendor_specific_insn
4005996e
AK		 4859 = emulation_type & EMULTYPE_TRAP_UD;
4860
9d74191a 4861 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 4862
e46479f8 4863 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 4864 ++vcpu->stat.insn_emulation;
1d2887e2 4865 if (r != EMULATION_OK) {
4005996e
AK		 4866 if (emulation_type & EMULTYPE_TRAP_UD)
4867 return EMULATE_FAIL;
a6f177ef 4868 if (reexecute_instruction(vcpu, cr2))
bbd9b64e 4869 return EMULATE_DONE;
6d77dbfc
GN		 4870 if (emulation_type & EMULTYPE_SKIP)
4871 return EMULATE_FAIL;
4872 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4873 }
4874 }
4875
ba8afb6b 4876 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 4877 kvm_rip_write(vcpu, ctxt->_eip);
ba8afb6b
GN		 4878 return EMULATE_DONE;
4879 }
4880
7ae441ea 4881 /* this is needed for vmware backdoor interface to work since it
4d2179e1 4882 changes registers values during IO operation */
7ae441ea
GN		 4883 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
4884 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
9dac77fa 4885 memcpy(ctxt->regs, vcpu->arch.regs, sizeof ctxt->regs);
7ae441ea 4886 }
4d2179e1 4887
5cd21917 4888restart:
9d74191a 4889 r = x86_emulate_insn(ctxt);
bbd9b64e 4890
775fde86
JR		 4891 if (r == EMULATION_INTERCEPTED)
4892 return EMULATE_DONE;
4893
d2ddd1c4 4894 if (r == EMULATION_FAILED) {
a6f177ef 4895 if (reexecute_instruction(vcpu, cr2))
c3cd7ffa
GN		 4896 return EMULATE_DONE;
4897
6d77dbfc 4898 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4899 }
4900
9d74191a 4901 if (ctxt->have_exception) {
54b8486f 4902 inject_emulated_exception(vcpu);
d2ddd1c4
GN		 4903 r = EMULATE_DONE;
4904 } else if (vcpu->arch.pio.count) {
3457e419
GN		 4905 if (!vcpu->arch.pio.in)
4906 vcpu->arch.pio.count = 0;
7ae441ea
GN		 4907 else
4908 writeback = false;
e85d28f8 4909 r = EMULATE_DO_MMIO;
7ae441ea
GN		 4910 } else if (vcpu->mmio_needed) {
4911 if (!vcpu->mmio_is_write)
4912 writeback = false;
e85d28f8 4913 r = EMULATE_DO_MMIO;
7ae441ea 4914 } else if (r == EMULATION_RESTART)
5cd21917 4915 goto restart;
d2ddd1c4
GN		 4916 else
4917 r = EMULATE_DONE;
f850e2e6 4918
7ae441ea 4919 if (writeback) {
9d74191a
TY		 4920 toggle_interruptibility(vcpu, ctxt->interruptibility);
4921 kvm_set_rflags(vcpu, ctxt->eflags);
7ae441ea 4922 kvm_make_request(KVM_REQ_EVENT, vcpu);
9dac77fa 4923 memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs);
7ae441ea 4924 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 4925 kvm_rip_write(vcpu, ctxt->eip);
7ae441ea
GN		 4926 } else
4927 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 4928
4929 return r;
de7d789a 4930}
51d8b661 4931EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 4932
cf8f70bf 4933int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 4934{
cf8f70bf 4935 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 4936 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
4937 size, port, &val, 1);
cf8f70bf 4938 /* do not return to emulator after return from userspace */
7972995b 4939 vcpu->arch.pio.count = 0;
de7d789a
CO		 4940 return ret;
4941}
cf8f70bf 4942EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 4943
8cfdc000
ZA		 4944static void tsc_bad(void *info)
4945{
0a3aee0d 4946 __this_cpu_write(cpu_tsc_khz, 0);
8cfdc000
ZA		 4947}
4948
4949static void tsc_khz_changed(void *data)
c8076604 4950{
8cfdc000
ZA		 4951 struct cpufreq_freqs *freq = data;
4952 unsigned long khz = 0;
4953
4954 if (data)
4955 khz = freq->new;
4956 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4957 khz = cpufreq_quick_get(raw_smp_processor_id());
4958 if (!khz)
4959 khz = tsc_khz;
0a3aee0d 4960 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 4961}
4962
c8076604
GH		 4963static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
4964 void *data)
4965{
4966 struct cpufreq_freqs *freq = data;
4967 struct kvm *kvm;
4968 struct kvm_vcpu *vcpu;
4969 int i, send_ipi = 0;
4970
8cfdc000
ZA		 4971 /*
4972 * We allow guests to temporarily run on slowing clocks,
4973 * provided we notify them after, or to run on accelerating
4974 * clocks, provided we notify them before. Thus time never
4975 * goes backwards.
4976 *
4977 * However, we have a problem. We can't atomically update
4978 * the frequency of a given CPU from this function; it is
4979 * merely a notifier, which can be called from any CPU.
4980 * Changing the TSC frequency at arbitrary points in time
4981 * requires a recomputation of local variables related to
4982 * the TSC for each VCPU. We must flag these local variables
4983 * to be updated and be sure the update takes place with the
4984 * new frequency before any guests proceed.
4985 *
4986 * Unfortunately, the combination of hotplug CPU and frequency
4987 * change creates an intractable locking scenario; the order
4988 * of when these callouts happen is undefined with respect to
4989 * CPU hotplug, and they can race with each other. As such,
4990 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
4991 * undefined; you can actually have a CPU frequency change take
4992 * place in between the computation of X and the setting of the
4993 * variable. To protect against this problem, all updates of
4994 * the per_cpu tsc_khz variable are done in an interrupt
4995 * protected IPI, and all callers wishing to update the value
4996 * must wait for a synchronous IPI to complete (which is trivial
4997 * if the caller is on the CPU already). This establishes the
4998 * necessary total order on variable updates.
4999 *
5000 * Note that because a guest time update may take place
5001 * anytime after the setting of the VCPU's request bit, the
5002 * correct TSC value must be set before the request. However,
5003 * to ensure the update actually makes it to any guest which
5004 * starts running in hardware virtualization between the set
5005 * and the acquisition of the spinlock, we must also ping the
5006 * CPU after setting the request bit.
5007 *
5008 */
5009
c8076604
GH		 5010 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5011 return 0;
5012 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5013 return 0;
8cfdc000
ZA		 5014
5015 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 5016
e935b837 5017 raw_spin_lock(&kvm_lock);
c8076604 5018 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 5019 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 5020 if (vcpu->cpu != freq->cpu)
5021 continue;
c285545f 5022 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 5023 if (vcpu->cpu != smp_processor_id())
8cfdc000 5024 send_ipi = 1;
c8076604
GH		 5025 }
5026 }
e935b837 5027 raw_spin_unlock(&kvm_lock);
c8076604
GH		 5028
5029 if (freq->old < freq->new && send_ipi) {
5030 /*
5031 * We upscale the frequency. Must make the guest
5032 * doesn't see old kvmclock values while running with
5033 * the new frequency, otherwise we risk the guest sees
5034 * time go backwards.
5035 *
5036 * In case we update the frequency for another cpu
5037 * (which might be in guest context) send an interrupt
5038 * to kick the cpu out of guest context. Next time
5039 * guest context is entered kvmclock will be updated,
5040 * so the guest will not see stale values.
5041 */
8cfdc000 5042 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 5043 }
5044 return 0;
5045}
5046
5047static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 5048 .notifier_call = kvmclock_cpufreq_notifier
5049};
5050
5051static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5052 unsigned long action, void *hcpu)
5053{
5054 unsigned int cpu = (unsigned long)hcpu;
5055
5056 switch (action) {
5057 case CPU_ONLINE:
5058 case CPU_DOWN_FAILED:
5059 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5060 break;
5061 case CPU_DOWN_PREPARE:
5062 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5063 break;
5064 }
5065 return NOTIFY_OK;
5066}
5067
5068static struct notifier_block kvmclock_cpu_notifier_block = {
5069 .notifier_call = kvmclock_cpu_notifier,
5070 .priority = -INT_MAX
c8076604
GH		 5071};
5072
b820cc0c
ZA		 5073static void kvm_timer_init(void)
5074{
5075 int cpu;
5076
c285545f 5077 max_tsc_khz = tsc_khz;
8cfdc000 5078 register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
b820cc0c 5079 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 5080#ifdef CONFIG_CPU_FREQ
5081 struct cpufreq_policy policy;
5082 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 5083 cpu = get_cpu();
5084 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 5085 if (policy.cpuinfo.max_freq)
5086 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 5087 put_cpu();
c285545f 5088#endif
b820cc0c
ZA		 5089 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5090 CPUFREQ_TRANSITION_NOTIFIER);
5091 }
c285545f 5092 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 5093 for_each_online_cpu(cpu)
5094 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
b820cc0c
ZA		 5095}
5096
ff9d07a0
ZY		 5097static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5098
5099static int kvm_is_in_guest(void)
5100{
5101 return percpu_read(current_vcpu) != NULL;
5102}
5103
5104static int kvm_is_user_mode(void)
5105{
5106 int user_mode = 3;
dcf46b94 5107
ff9d07a0
ZY		 5108 if (percpu_read(current_vcpu))
5109 user_mode = kvm_x86_ops->get_cpl(percpu_read(current_vcpu));
dcf46b94 5110
ff9d07a0
ZY		 5111 return user_mode != 0;
5112}
5113
5114static unsigned long kvm_get_guest_ip(void)
5115{
5116 unsigned long ip = 0;
dcf46b94 5117
ff9d07a0
ZY		 5118 if (percpu_read(current_vcpu))
5119 ip = kvm_rip_read(percpu_read(current_vcpu));
dcf46b94 5120
ff9d07a0
ZY		 5121 return ip;
5122}
5123
5124static struct perf_guest_info_callbacks kvm_guest_cbs = {
5125 .is_in_guest = kvm_is_in_guest,
5126 .is_user_mode = kvm_is_user_mode,
5127 .get_guest_ip = kvm_get_guest_ip,
5128};
5129
5130void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5131{
5132 percpu_write(current_vcpu, vcpu);
5133}
5134EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5135
5136void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5137{
5138 percpu_write(current_vcpu, NULL);
5139}
5140EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5141
ce88decf
XG		 5142static void kvm_set_mmio_spte_mask(void)
5143{
5144 u64 mask;
5145 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5146
5147 /*
5148 * Set the reserved bits and the present bit of an paging-structure
5149 * entry to generate page fault with PFER.RSV = 1.
5150 */
5151 mask = ((1ull << (62 - maxphyaddr + 1)) - 1) << maxphyaddr;
5152 mask |= 1ull;
5153
5154#ifdef CONFIG_X86_64
5155 /*
5156 * If reserved bit is not supported, clear the present bit to disable
5157 * mmio page fault.
5158 */
5159 if (maxphyaddr == 52)
5160 mask &= ~1ull;
5161#endif
5162
5163 kvm_mmu_set_mmio_spte_mask(mask);
5164}
5165
f8c16bba 5166int kvm_arch_init(void *opaque)
043405e1 5167{
b820cc0c 5168 int r;
f8c16bba
ZX		 5169 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
5170
f8c16bba
ZX		 5171 if (kvm_x86_ops) {
5172 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 5173 r = -EEXIST;
5174 goto out;
f8c16bba
ZX		 5175 }
5176
5177 if (!ops->cpu_has_kvm_support()) {
5178 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 5179 r = -EOPNOTSUPP;
5180 goto out;
f8c16bba
ZX		 5181 }
5182 if (ops->disabled_by_bios()) {
5183 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 5184 r = -EOPNOTSUPP;
5185 goto out;
f8c16bba
ZX		 5186 }
5187
97db56ce
AK		 5188 r = kvm_mmu_module_init();
5189 if (r)
5190 goto out;
5191
ce88decf 5192 kvm_set_mmio_spte_mask();
97db56ce
AK		 5193 kvm_init_msr_list();
5194
f8c16bba 5195 kvm_x86_ops = ops;
7b52345e 5196 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 5197 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 5198
b820cc0c 5199 kvm_timer_init();
c8076604 5200
ff9d07a0
ZY		 5201 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5202
2acf923e
DC		 5203 if (cpu_has_xsave)
5204 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5205
f8c16bba 5206 return 0;
56c6d28a
ZX		 5207
5208out:
56c6d28a 5209 return r;
043405e1 5210}
8776e519 5211
f8c16bba
ZX		 5212void kvm_arch_exit(void)
5213{
ff9d07a0
ZY		 5214 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5215
888d256e
JK		 5216 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5217 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5218 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 5219 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
f8c16bba 5220 kvm_x86_ops = NULL;
56c6d28a
ZX		 5221 kvm_mmu_module_exit();
5222}
f8c16bba 5223
8776e519
HB		 5224int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5225{
5226 ++vcpu->stat.halt_exits;
5227 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 5228 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 5229 return 1;
5230 } else {
5231 vcpu->run->exit_reason = KVM_EXIT_HLT;
5232 return 0;
5233 }
5234}
5235EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5236
2f333bcb
MT		 5237static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0,
5238 unsigned long a1)
5239{
5240 if (is_long_mode(vcpu))
5241 return a0;
5242 else
5243 return a0 | ((gpa_t)a1 << 32);
5244}
5245
55cd8e5a
GN		 5246int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
5247{
5248 u64 param, ingpa, outgpa, ret;
5249 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
5250 bool fast, longmode;
5251 int cs_db, cs_l;
5252
5253 /*
5254 * hypercall generates UD from non zero cpl and real mode
5255 * per HYPER-V spec
5256 */
3eeb3288 5257 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 5258 kvm_queue_exception(vcpu, UD_VECTOR);
5259 return 0;
5260 }
5261
5262 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5263 longmode = is_long_mode(vcpu) && cs_l == 1;
5264
5265 if (!longmode) {
ccd46936
GN		 5266 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
5267 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
5268 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
5269 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
5270 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
5271 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 5272 }
5273#ifdef CONFIG_X86_64
5274 else {
5275 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
5276 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
5277 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
5278 }
5279#endif
5280
5281 code = param & 0xffff;
5282 fast = (param >> 16) & 0x1;
5283 rep_cnt = (param >> 32) & 0xfff;
5284 rep_idx = (param >> 48) & 0xfff;
5285
5286 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
5287
c25bc163
GN		 5288 switch (code) {
5289 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
5290 kvm_vcpu_on_spin(vcpu);
5291 break;
5292 default:
5293 res = HV_STATUS_INVALID_HYPERCALL_CODE;
5294 break;
5295 }
55cd8e5a
GN		 5296
5297 ret = res | (((u64)rep_done & 0xfff) << 32);
5298 if (longmode) {
5299 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5300 } else {
5301 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
5302 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
5303 }
5304
5305 return 1;
5306}
5307
8776e519
HB		 5308int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5309{
5310 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 5311 int r = 1;
8776e519 5312
55cd8e5a
GN		 5313 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5314 return kvm_hv_hypercall(vcpu);
5315
5fdbf976
MT		 5316 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5317 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5318 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5319 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5320 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 5321
229456fc 5322 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 5323
8776e519
HB		 5324 if (!is_long_mode(vcpu)) {
5325 nr &= 0xFFFFFFFF;
5326 a0 &= 0xFFFFFFFF;
5327 a1 &= 0xFFFFFFFF;
5328 a2 &= 0xFFFFFFFF;
5329 a3 &= 0xFFFFFFFF;
5330 }
5331
07708c4a
JK		 5332 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5333 ret = -KVM_EPERM;
5334 goto out;
5335 }
5336
8776e519 5337 switch (nr) {
b93463aa
AK		 5338 case KVM_HC_VAPIC_POLL_IRQ:
5339 ret = 0;
5340 break;
2f333bcb
MT		 5341 case KVM_HC_MMU_OP:
5342 r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret);
5343 break;
8776e519
HB		 5344 default:
5345 ret = -KVM_ENOSYS;
5346 break;
5347 }
07708c4a 5348out:
5fdbf976 5349 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 5350 ++vcpu->stat.hypercalls;
2f333bcb 5351 return r;
8776e519
HB		 5352}
5353EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5354
d6aa1000 5355int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 5356{
d6aa1000 5357 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 5358 char instruction[3];
5fdbf976 5359 unsigned long rip = kvm_rip_read(vcpu);
8776e519 5360
8776e519
HB		 5361 /*
5362 * Blow out the MMU to ensure that no other VCPU has an active mapping
5363 * to ensure that the updated hypercall appears atomically across all
5364 * VCPUs.
5365 */
5366 kvm_mmu_zap_all(vcpu->kvm);
5367
8776e519 5368 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 5369
9d74191a 5370 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
8776e519
HB		 5371}
5372
07716717
DK		 5373static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)
5374{
ad312c7c
ZX		 5375 struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];
5376 int j, nent = vcpu->arch.cpuid_nent;
07716717
DK		 5377
5378 e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;
5379 /* when no next entry is found, the current entry[i] is reselected */
0fdf8e59 5380 for (j = i + 1; ; j = (j + 1) % nent) {
ad312c7c 5381 struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j];
07716717
DK		 5382 if (ej->function == e->function) {
5383 ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
5384 return j;
5385 }
5386 }
5387 return 0; /* silence gcc, even though control never reaches here */
5388}
5389
5390/* find an entry with matching function, matching index (if needed), and that
5391 * should be read next (if it's stateful) */
5392static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e,
5393 u32 function, u32 index)
5394{
5395 if (e->function != function)
5396 return 0;
5397 if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index)
5398 return 0;
5399 if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) &&
19355475 5400 !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT))
07716717
DK		 5401 return 0;
5402 return 1;
5403}
5404
d8017474
AG		 5405struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
5406 u32 function, u32 index)
8776e519
HB		 5407{
5408 int i;
d8017474 5409 struct kvm_cpuid_entry2 *best = NULL;
8776e519 5410
ad312c7c 5411 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
d8017474
AG		 5412 struct kvm_cpuid_entry2 *e;
5413
ad312c7c 5414 e = &vcpu->arch.cpuid_entries[i];
07716717
DK		 5415 if (is_matching_cpuid_entry(e, function, index)) {
5416 if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC)
5417 move_to_next_stateful_cpuid_entry(vcpu, i);
8776e519
HB		 5418 best = e;
5419 break;
5420 }
8776e519 5421 }
d8017474
AG		 5422 return best;
5423}
0e851880 5424EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry);
d8017474 5425
82725b20
DE		 5426int cpuid_maxphyaddr(struct kvm_vcpu *vcpu)
5427{
5428 struct kvm_cpuid_entry2 *best;
5429
f7a71197
AK		 5430 best = kvm_find_cpuid_entry(vcpu, 0x80000000, 0);
5431 if (!best || best->eax < 0x80000008)
5432 goto not_found;
82725b20
DE		 5433 best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0);
5434 if (best)
5435 return best->eax & 0xff;
f7a71197 5436not_found:
82725b20
DE		 5437 return 36;
5438}
5439
bd22f5cf
AP		 5440/*
5441 * If no match is found, check whether we exceed the vCPU's limit
5442 * and return the content of the highest valid _standard_ leaf instead.
5443 * This is to satisfy the CPUID specification.
5444 */
5445static struct kvm_cpuid_entry2* check_cpuid_limit(struct kvm_vcpu *vcpu,
5446 u32 function, u32 index)
5447{
5448 struct kvm_cpuid_entry2 *maxlevel;
5449
5450 maxlevel = kvm_find_cpuid_entry(vcpu, function & 0x80000000, 0);
5451 if (!maxlevel || maxlevel->eax >= function)
5452 return NULL;
5453 if (function & 0x80000000) {
5454 maxlevel = kvm_find_cpuid_entry(vcpu, 0, 0);
5455 if (!maxlevel)
5456 return NULL;
5457 }
5458 return kvm_find_cpuid_entry(vcpu, maxlevel->eax, index);
5459}
5460
d8017474
AG		 5461void kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
5462{
5463 u32 function, index;
5464 struct kvm_cpuid_entry2 *best;
5465
5466 function = kvm_register_read(vcpu, VCPU_REGS_RAX);
5467 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5468 kvm_register_write(vcpu, VCPU_REGS_RAX, 0);
5469 kvm_register_write(vcpu, VCPU_REGS_RBX, 0);
5470 kvm_register_write(vcpu, VCPU_REGS_RCX, 0);
5471 kvm_register_write(vcpu, VCPU_REGS_RDX, 0);
5472 best = kvm_find_cpuid_entry(vcpu, function, index);
bd22f5cf
AP		 5473
5474 if (!best)
5475 best = check_cpuid_limit(vcpu, function, index);
5476
8776e519 5477 if (best) {
5fdbf976
MT		 5478 kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax);
5479 kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx);
5480 kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx);
5481 kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx);
8776e519 5482 }
8776e519 5483 kvm_x86_ops->skip_emulated_instruction(vcpu);
229456fc
MT		 5484 trace_kvm_cpuid(function,
5485 kvm_register_read(vcpu, VCPU_REGS_RAX),
5486 kvm_register_read(vcpu, VCPU_REGS_RBX),
5487 kvm_register_read(vcpu, VCPU_REGS_RCX),
5488 kvm_register_read(vcpu, VCPU_REGS_RDX));
8776e519
HB		 5489}
5490EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
d0752060 5491
b6c7a5dc
HB		 5492/*
5493 * Check if userspace requested an interrupt window, and that the
5494 * interrupt window is open.
5495 *
5496 * No need to exit to userspace if we already have an interrupt queued.
5497 */
851ba692 5498static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 5499{
8061823a 5500 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 5501 vcpu->run->request_interrupt_window &&
5df56646 5502 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 5503}
5504
851ba692 5505static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 5506{
851ba692
AK		 5507 struct kvm_run *kvm_run = vcpu->run;
5508
91586a3b 5509 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 5510 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 5511 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 5512 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 5513 kvm_run->ready_for_interrupt_injection = 1;
4531220b 5514 else
b6c7a5dc 5515 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 5516 kvm_arch_interrupt_allowed(vcpu) &&
5517 !kvm_cpu_has_interrupt(vcpu) &&
5518 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 5519}
5520
b93463aa
AK		 5521static void vapic_enter(struct kvm_vcpu *vcpu)
5522{
5523 struct kvm_lapic *apic = vcpu->arch.apic;
5524 struct page *page;
5525
5526 if (!apic || !apic->vapic_addr)
5527 return;
5528
5529 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
72dc67a6
IE		 5530
5531 vcpu->arch.apic->vapic_page = page;
b93463aa
AK		 5532}
5533
5534static void vapic_exit(struct kvm_vcpu *vcpu)
5535{
5536 struct kvm_lapic *apic = vcpu->arch.apic;
f656ce01 5537 int idx;
b93463aa
AK		 5538
5539 if (!apic || !apic->vapic_addr)
5540 return;
5541
f656ce01 5542 idx = srcu_read_lock(&vcpu->kvm->srcu);
b93463aa
AK		 5543 kvm_release_page_dirty(apic->vapic_page);
5544 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f656ce01 5545 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 5546}
5547
95ba8273
GN		 5548static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5549{
5550 int max_irr, tpr;
5551
5552 if (!kvm_x86_ops->update_cr8_intercept)
5553 return;
5554
88c808fd
AK		 5555 if (!vcpu->arch.apic)
5556 return;
5557
8db3baa2
GN		 5558 if (!vcpu->arch.apic->vapic_addr)
5559 max_irr = kvm_lapic_find_highest_irr(vcpu);
5560 else
5561 max_irr = -1;
95ba8273
GN		 5562
5563 if (max_irr != -1)
5564 max_irr >>= 4;
5565
5566 tpr = kvm_lapic_get_cr8(vcpu);
5567
5568 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5569}
5570
851ba692 5571static void inject_pending_event(struct kvm_vcpu *vcpu)
95ba8273
GN		 5572{
5573 /* try to reinject previous events if any */
b59bb7bd 5574 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 5575 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5576 vcpu->arch.exception.has_error_code,
5577 vcpu->arch.exception.error_code);
b59bb7bd
GN		 5578 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5579 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 5580 vcpu->arch.exception.error_code,
5581 vcpu->arch.exception.reinject);
b59bb7bd
GN		 5582 return;
5583 }
5584
95ba8273
GN		 5585 if (vcpu->arch.nmi_injected) {
5586 kvm_x86_ops->set_nmi(vcpu);
5587 return;
5588 }
5589
5590 if (vcpu->arch.interrupt.pending) {
66fd3f7f 5591 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5592 return;
5593 }
5594
5595 /* try to inject new event if pending */
5596 if (vcpu->arch.nmi_pending) {
5597 if (kvm_x86_ops->nmi_allowed(vcpu)) {
7460fb4a 5598 --vcpu->arch.nmi_pending;
95ba8273
GN		 5599 vcpu->arch.nmi_injected = true;
5600 kvm_x86_ops->set_nmi(vcpu);
5601 }
5602 } else if (kvm_cpu_has_interrupt(vcpu)) {
5603 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 5604 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5605 false);
5606 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5607 }
5608 }
5609}
5610
2acf923e
DC		 5611static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
5612{
5613 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
5614 !vcpu->guest_xcr0_loaded) {
5615 /* kvm_set_xcr() also depends on this */
5616 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
5617 vcpu->guest_xcr0_loaded = 1;
5618 }
5619}
5620
5621static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
5622{
5623 if (vcpu->guest_xcr0_loaded) {
5624 if (vcpu->arch.xcr0 != host_xcr0)
5625 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
5626 vcpu->guest_xcr0_loaded = 0;
5627 }
5628}
5629
7460fb4a
AK		 5630static void process_nmi(struct kvm_vcpu *vcpu)
5631{
5632 unsigned limit = 2;
5633
5634 /*
5635 * x86 is limited to one NMI running, and one NMI pending after it.
5636 * If an NMI is already in progress, limit further NMIs to just one.
5637 * Otherwise, allow two (and we'll inject the first one immediately).
5638 */
5639 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
5640 limit = 1;
5641
5642 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
5643 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
5644 kvm_make_request(KVM_REQ_EVENT, vcpu);
5645}
5646
851ba692 5647static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 5648{
5649 int r;
6a8b1d13 5650 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 5651 vcpu->run->request_interrupt_window;
b6c7a5dc 5652
3e007509 5653 if (vcpu->requests) {
a8eeb04a 5654 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 5655 kvm_mmu_unload(vcpu);
a8eeb04a 5656 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 5657 __kvm_migrate_timers(vcpu);
34c238a1
ZA		 5658 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
5659 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 5660 if (unlikely(r))
5661 goto out;
5662 }
a8eeb04a 5663 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 5664 kvm_mmu_sync_roots(vcpu);
a8eeb04a 5665 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
d4acf7e7 5666 kvm_x86_ops->tlb_flush(vcpu);
a8eeb04a 5667 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 5668 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 5669 r = 0;
5670 goto out;
5671 }
a8eeb04a 5672 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 5673 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 5674 r = 0;
5675 goto out;
5676 }
a8eeb04a 5677 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 5678 vcpu->fpu_active = 0;
5679 kvm_x86_ops->fpu_deactivate(vcpu);
5680 }
af585b92
GN		 5681 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
5682 /* Page is swapped out. Do synthetic halt */
5683 vcpu->arch.apf.halted = true;
5684 r = 1;
5685 goto out;
5686 }
c9aaa895
GC		 5687 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
5688 record_steal_time(vcpu);
7460fb4a
AK		 5689 if (kvm_check_request(KVM_REQ_NMI, vcpu))
5690 process_nmi(vcpu);
c9aaa895 5691
2f52d58c 5692 }
b93463aa 5693
3e007509
AK		 5694 r = kvm_mmu_reload(vcpu);
5695 if (unlikely(r))
5696 goto out;
5697
b463a6f7
AK		 5698 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
5699 inject_pending_event(vcpu);
5700
5701 /* enable NMI/IRQ window open exits if needed */
7460fb4a 5702 if (vcpu->arch.nmi_pending)
b463a6f7
AK		 5703 kvm_x86_ops->enable_nmi_window(vcpu);
5704 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
5705 kvm_x86_ops->enable_irq_window(vcpu);
5706
5707 if (kvm_lapic_enabled(vcpu)) {
5708 update_cr8_intercept(vcpu);
5709 kvm_lapic_sync_to_vapic(vcpu);
5710 }
5711 }
5712
b6c7a5dc
HB		 5713 preempt_disable();
5714
5715 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 5716 if (vcpu->fpu_active)
5717 kvm_load_guest_fpu(vcpu);
2acf923e 5718 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 5719
6b7e2d09
XG		 5720 vcpu->mode = IN_GUEST_MODE;
5721
5722 /* We should set ->mode before check ->requests,
5723 * see the comment in make_all_cpus_request.
5724 */
5725 smp_mb();
b6c7a5dc 5726
d94e1dc9 5727 local_irq_disable();
32f88400 5728
6b7e2d09 5729 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 5730 || need_resched() || signal_pending(current)) {
6b7e2d09 5731 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 5732 smp_wmb();
6c142801
AK		 5733 local_irq_enable();
5734 preempt_enable();
b463a6f7 5735 kvm_x86_ops->cancel_injection(vcpu);
6c142801
AK		 5736 r = 1;
5737 goto out;
5738 }
5739
f656ce01 5740 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
3200f405 5741
b6c7a5dc
HB		 5742 kvm_guest_enter();
5743
42dbaa5a 5744 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 5745 set_debugreg(0, 7);
5746 set_debugreg(vcpu->arch.eff_db[0], 0);
5747 set_debugreg(vcpu->arch.eff_db[1], 1);
5748 set_debugreg(vcpu->arch.eff_db[2], 2);
5749 set_debugreg(vcpu->arch.eff_db[3], 3);
5750 }
b6c7a5dc 5751
229456fc 5752 trace_kvm_entry(vcpu->vcpu_id);
851ba692 5753 kvm_x86_ops->run(vcpu);
b6c7a5dc 5754
24f1e32c
FW		 5755 /*
5756 * If the guest has used debug registers, at least dr7
5757 * will be disabled while returning to the host.
5758 * If we don't have active breakpoints in the host, we don't
5759 * care about the messed up debug address registers. But if
5760 * we have some of them active, restore the old state.
5761 */
59d8eb53 5762 if (hw_breakpoint_active())
24f1e32c 5763 hw_breakpoint_restore();
42dbaa5a 5764
d5c1785d 5765 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu);
1d5f066e 5766
6b7e2d09 5767 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 5768 smp_wmb();
b6c7a5dc
HB		 5769 local_irq_enable();
5770
5771 ++vcpu->stat.exits;
5772
5773 /*
5774 * We must have an instruction between local_irq_enable() and
5775 * kvm_guest_exit(), so the timer interrupt isn't delayed by
5776 * the interrupt shadow. The stat.exits increment will do nicely.
5777 * But we need to prevent reordering, hence this barrier():
5778 */
5779 barrier();
5780
5781 kvm_guest_exit();
5782
5783 preempt_enable();
5784
f656ce01 5785 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 5786
b6c7a5dc
HB		 5787 /*
5788 * Profile KVM exit RIPs:
5789 */
5790 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 5791 unsigned long rip = kvm_rip_read(vcpu);
5792 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 5793 }
5794
298101da 5795
b93463aa
AK		 5796 kvm_lapic_sync_from_vapic(vcpu);
5797
851ba692 5798 r = kvm_x86_ops->handle_exit(vcpu);
d7690175
MT		 5799out:
5800 return r;
5801}
b6c7a5dc 5802
09cec754 5803
851ba692 5804static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 5805{
5806 int r;
f656ce01 5807 struct kvm *kvm = vcpu->kvm;
d7690175
MT		 5808
5809 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
1b10bf31
JK		 5810 pr_debug("vcpu %d received sipi with vector # %x\n",
5811 vcpu->vcpu_id, vcpu->arch.sipi_vector);
d7690175 5812 kvm_lapic_reset(vcpu);
5f179287 5813 r = kvm_arch_vcpu_reset(vcpu);
d7690175
MT		 5814 if (r)
5815 return r;
5816 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 5817 }
5818
f656ce01 5819 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175
MT		 5820 vapic_enter(vcpu);
5821
5822 r = 1;
5823 while (r > 0) {
af585b92
GN		 5824 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
5825 !vcpu->arch.apf.halted)
851ba692 5826 r = vcpu_enter_guest(vcpu);
d7690175 5827 else {
f656ce01 5828 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 5829 kvm_vcpu_block(vcpu);
f656ce01 5830 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
a8eeb04a 5831 if (kvm_check_request(KVM_REQ_UNHALT, vcpu))
09cec754
GN		 5832 {
5833 switch(vcpu->arch.mp_state) {
5834 case KVM_MP_STATE_HALTED:
d7690175 5835 vcpu->arch.mp_state =
09cec754
GN		 5836 KVM_MP_STATE_RUNNABLE;
5837 case KVM_MP_STATE_RUNNABLE:
af585b92 5838 vcpu->arch.apf.halted = false;
09cec754
GN		 5839 break;
5840 case KVM_MP_STATE_SIPI_RECEIVED:
5841 default:
5842 r = -EINTR;
5843 break;
5844 }
5845 }
d7690175
MT		 5846 }
5847
09cec754
GN		 5848 if (r <= 0)
5849 break;
5850
5851 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
5852 if (kvm_cpu_has_pending_timer(vcpu))
5853 kvm_inject_pending_timer_irqs(vcpu);
5854
851ba692 5855 if (dm_request_for_irq_injection(vcpu)) {
09cec754 5856 r = -EINTR;
851ba692 5857 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5858 ++vcpu->stat.request_irq_exits;
5859 }
af585b92
GN		 5860
5861 kvm_check_async_pf_completion(vcpu);
5862
09cec754
GN		 5863 if (signal_pending(current)) {
5864 r = -EINTR;
851ba692 5865 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5866 ++vcpu->stat.signal_exits;
5867 }
5868 if (need_resched()) {
f656ce01 5869 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
09cec754 5870 kvm_resched(vcpu);
f656ce01 5871 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 5872 }
b6c7a5dc
HB		 5873 }
5874
f656ce01 5875 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc 5876
b93463aa
AK		 5877 vapic_exit(vcpu);
5878
b6c7a5dc
HB		 5879 return r;
5880}
5881
5287f194
AK		 5882static int complete_mmio(struct kvm_vcpu *vcpu)
5883{
5884 struct kvm_run *run = vcpu->run;
5885 int r;
5886
5887 if (!(vcpu->arch.pio.count || vcpu->mmio_needed))
5888 return 1;
5889
5890 if (vcpu->mmio_needed) {
5287f194 5891 vcpu->mmio_needed = 0;
cef4dea0 5892 if (!vcpu->mmio_is_write)
0004c7c2
GN		 5893 memcpy(vcpu->mmio_data + vcpu->mmio_index,
5894 run->mmio.data, 8);
cef4dea0
AK		 5895 vcpu->mmio_index += 8;
5896 if (vcpu->mmio_index < vcpu->mmio_size) {
5897 run->exit_reason = KVM_EXIT_MMIO;
5898 run->mmio.phys_addr = vcpu->mmio_phys_addr + vcpu->mmio_index;
5899 memcpy(run->mmio.data, vcpu->mmio_data + vcpu->mmio_index, 8);
5900 run->mmio.len = min(vcpu->mmio_size - vcpu->mmio_index, 8);
5901 run->mmio.is_write = vcpu->mmio_is_write;
5902 vcpu->mmio_needed = 1;
5903 return 0;
5904 }
5905 if (vcpu->mmio_is_write)
5906 return 1;
5907 vcpu->mmio_read_completed = 1;
5287f194
AK		 5908 }
5909 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5910 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
5911 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
5912 if (r != EMULATE_DONE)
5913 return 0;
5914 return 1;
5915}
5916
b6c7a5dc
HB		 5917int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
5918{
5919 int r;
5920 sigset_t sigsaved;
5921
e5c30142
AK		 5922 if (!tsk_used_math(current) && init_fpu(current))
5923 return -ENOMEM;
5924
ac9f6dc0
AK		 5925 if (vcpu->sigset_active)
5926 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
5927
a4535290 5928 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 5929 kvm_vcpu_block(vcpu);
d7690175 5930 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 5931 r = -EAGAIN;
5932 goto out;
b6c7a5dc
HB		 5933 }
5934
b6c7a5dc 5935 /* re-sync apic's tpr */
eea1cff9
AP		 5936 if (!irqchip_in_kernel(vcpu->kvm)) {
5937 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
5938 r = -EINVAL;
5939 goto out;
5940 }
5941 }
b6c7a5dc 5942
5287f194
AK		 5943 r = complete_mmio(vcpu);
5944 if (r <= 0)
5945 goto out;
5946
5fdbf976
MT		 5947 if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL)
5948 kvm_register_write(vcpu, VCPU_REGS_RAX,
5949 kvm_run->hypercall.ret);
b6c7a5dc 5950
851ba692 5951 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 5952
5953out:
f1d86e46 5954 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 5955 if (vcpu->sigset_active)
5956 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
5957
b6c7a5dc
HB		 5958 return r;
5959}
5960
5961int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5962{
7ae441ea
GN		 5963 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
5964 /*
5965 * We are here if userspace calls get_regs() in the middle of
5966 * instruction emulation. Registers state needs to be copied
5967 * back from emulation context to vcpu. Usrapace shouldn't do
5968 * that usually, but some bad designed PV devices (vmware
5969 * backdoor interface) need this to work
5970 */
9dac77fa
AK		 5971 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5972 memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs);
7ae441ea
GN		 5973 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5974 }
5fdbf976
MT		 5975 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
5976 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
5977 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
5978 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
5979 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
5980 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
5981 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
5982 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 5983#ifdef CONFIG_X86_64
5fdbf976
MT		 5984 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
5985 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
5986 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
5987 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
5988 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
5989 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
5990 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
5991 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 5992#endif
5993
5fdbf976 5994 regs->rip = kvm_rip_read(vcpu);
91586a3b 5995 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 5996
b6c7a5dc
HB		 5997 return 0;
5998}
5999
6000int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6001{
7ae441ea
GN		 6002 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6003 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6004
5fdbf976
MT		 6005 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6006 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6007 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6008 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6009 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6010 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6011 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6012 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 6013#ifdef CONFIG_X86_64
5fdbf976
MT		 6014 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6015 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6016 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6017 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6018 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6019 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6020 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6021 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 6022#endif
6023
5fdbf976 6024 kvm_rip_write(vcpu, regs->rip);
91586a3b 6025 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 6026
b4f14abd
JK		 6027 vcpu->arch.exception.pending = false;
6028
3842d135
AK		 6029 kvm_make_request(KVM_REQ_EVENT, vcpu);
6030
b6c7a5dc
HB		 6031 return 0;
6032}
6033
b6c7a5dc
HB		 6034void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6035{
6036 struct kvm_segment cs;
6037
3e6e0aab 6038 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 6039 *db = cs.db;
6040 *l = cs.l;
6041}
6042EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
6043
6044int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
6045 struct kvm_sregs *sregs)
6046{
89a27f4d 6047 struct desc_ptr dt;
b6c7a5dc 6048
3e6e0aab
GT		 6049 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6050 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6051 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6052 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6053 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6054 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6055
3e6e0aab
GT		 6056 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6057 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 6058
6059 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 6060 sregs->idt.limit = dt.size;
6061 sregs->idt.base = dt.address;
b6c7a5dc 6062 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 6063 sregs->gdt.limit = dt.size;
6064 sregs->gdt.base = dt.address;
b6c7a5dc 6065
4d4ec087 6066 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 6067 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 6068 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 6069 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 6070 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 6071 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 6072 sregs->apic_base = kvm_get_apic_base(vcpu);
6073
923c61bb 6074 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 6075
36752c9b 6076 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 6077 set_bit(vcpu->arch.interrupt.nr,
6078 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 6079
b6c7a5dc
HB		 6080 return 0;
6081}
6082
62d9f0db
MT		 6083int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
6084 struct kvm_mp_state *mp_state)
6085{
62d9f0db 6086 mp_state->mp_state = vcpu->arch.mp_state;
62d9f0db
MT		 6087 return 0;
6088}
6089
6090int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
6091 struct kvm_mp_state *mp_state)
6092{
62d9f0db 6093 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 6094 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 6095 return 0;
6096}
6097
e269fb21
JK		 6098int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason,
6099 bool has_error_code, u32 error_code)
b6c7a5dc 6100{
9d74191a 6101 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 6102 int ret;
e01c2426 6103
8ec4722d 6104 init_emulate_ctxt(vcpu);
c697518a 6105
9d74191a
TY		 6106 ret = emulator_task_switch(ctxt, tss_selector, reason,
6107 has_error_code, error_code);
c697518a 6108
c697518a 6109 if (ret)
19d04437 6110 return EMULATE_FAIL;
37817f29 6111
9dac77fa 6112 memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs);
9d74191a
TY		 6113 kvm_rip_write(vcpu, ctxt->eip);
6114 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 6115 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 6116 return EMULATE_DONE;
37817f29
IE		 6117}
6118EXPORT_SYMBOL_GPL(kvm_task_switch);
6119
b6c7a5dc
HB		 6120int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
6121 struct kvm_sregs *sregs)
6122{
6123 int mmu_reset_needed = 0;
63f42e02 6124 int pending_vec, max_bits, idx;
89a27f4d 6125 struct desc_ptr dt;
b6c7a5dc 6126
89a27f4d
GN		 6127 dt.size = sregs->idt.limit;
6128 dt.address = sregs->idt.base;
b6c7a5dc 6129 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 6130 dt.size = sregs->gdt.limit;
6131 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 6132 kvm_x86_ops->set_gdt(vcpu, &dt);
6133
ad312c7c 6134 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 6135 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 6136 vcpu->arch.cr3 = sregs->cr3;
aff48baa 6137 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 6138
2d3ad1f4 6139 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 6140
f6801dff 6141 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 6142 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 6143 kvm_set_apic_base(vcpu, sregs->apic_base);
6144
4d4ec087 6145 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 6146 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 6147 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 6148
fc78f519 6149 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 6150 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3ea3aa8c
SY		 6151 if (sregs->cr4 & X86_CR4_OSXSAVE)
6152 update_cpuid(vcpu);
63f42e02
XG		 6153
6154 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 6155 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 6156 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 6157 mmu_reset_needed = 1;
6158 }
63f42e02 6159 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 6160
6161 if (mmu_reset_needed)
6162 kvm_mmu_reset_context(vcpu);
6163
923c61bb
GN		 6164 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
6165 pending_vec = find_first_bit(
6166 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
6167 if (pending_vec < max_bits) {
66fd3f7f 6168 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 6169 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 6170 }
6171
3e6e0aab
GT		 6172 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6173 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6174 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6175 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6176 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6177 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6178
3e6e0aab
GT		 6179 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6180 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 6181
5f0269f5
ME		 6182 update_cr8_intercept(vcpu);
6183
9c3e4aab 6184 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 6185 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 6186 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 6187 !is_protmode(vcpu))
9c3e4aab
MT		 6188 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6189
3842d135
AK		 6190 kvm_make_request(KVM_REQ_EVENT, vcpu);
6191
b6c7a5dc
HB		 6192 return 0;
6193}
6194
d0bfb940
JK		 6195int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
6196 struct kvm_guest_debug *dbg)
b6c7a5dc 6197{
355be0b9 6198 unsigned long rflags;
ae675ef0 6199 int i, r;
b6c7a5dc 6200
4f926bf2
JK		 6201 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
6202 r = -EBUSY;
6203 if (vcpu->arch.exception.pending)
2122ff5e 6204 goto out;
4f926bf2
JK		 6205 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
6206 kvm_queue_exception(vcpu, DB_VECTOR);
6207 else
6208 kvm_queue_exception(vcpu, BP_VECTOR);
6209 }
6210
91586a3b
JK		 6211 /*
6212 * Read rflags as long as potentially injected trace flags are still
6213 * filtered out.
6214 */
6215 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 6216
6217 vcpu->guest_debug = dbg->control;
6218 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
6219 vcpu->guest_debug = 0;
6220
6221 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 6222 for (i = 0; i < KVM_NR_DB_REGS; ++i)
6223 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
6224 vcpu->arch.switch_db_regs =
6225 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
6226 } else {
6227 for (i = 0; i < KVM_NR_DB_REGS; i++)
6228 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
6229 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
6230 }
6231
f92653ee
JK		 6232 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6233 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
6234 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 6235
91586a3b
JK		 6236 /*
6237 * Trigger an rflags update that will inject or remove the trace
6238 * flags.
6239 */
6240 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 6241
355be0b9 6242 kvm_x86_ops->set_guest_debug(vcpu, dbg);
b6c7a5dc 6243
4f926bf2 6244 r = 0;
d0bfb940 6245
2122ff5e 6246out:
b6c7a5dc
HB		 6247
6248 return r;
6249}
6250
8b006791
ZX		 6251/*
6252 * Translate a guest virtual address to a guest physical address.
6253 */
6254int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
6255 struct kvm_translation *tr)
6256{
6257 unsigned long vaddr = tr->linear_address;
6258 gpa_t gpa;
f656ce01 6259 int idx;
8b006791 6260
f656ce01 6261 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 6262 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 6263 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 6264 tr->physical_address = gpa;
6265 tr->valid = gpa != UNMAPPED_GVA;
6266 tr->writeable = 1;
6267 tr->usermode = 0;
8b006791
ZX		 6268
6269 return 0;
6270}
6271
d0752060
HB		 6272int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6273{
98918833
SY		 6274 struct i387_fxsave_struct *fxsave =
6275 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 6276
d0752060
HB		 6277 memcpy(fpu->fpr, fxsave->st_space, 128);
6278 fpu->fcw = fxsave->cwd;
6279 fpu->fsw = fxsave->swd;
6280 fpu->ftwx = fxsave->twd;
6281 fpu->last_opcode = fxsave->fop;
6282 fpu->last_ip = fxsave->rip;
6283 fpu->last_dp = fxsave->rdp;
6284 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
6285
d0752060
HB		 6286 return 0;
6287}
6288
6289int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6290{
98918833
SY		 6291 struct i387_fxsave_struct *fxsave =
6292 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 6293
d0752060
HB		 6294 memcpy(fxsave->st_space, fpu->fpr, 128);
6295 fxsave->cwd = fpu->fcw;
6296 fxsave->swd = fpu->fsw;
6297 fxsave->twd = fpu->ftwx;
6298 fxsave->fop = fpu->last_opcode;
6299 fxsave->rip = fpu->last_ip;
6300 fxsave->rdp = fpu->last_dp;
6301 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
6302
d0752060
HB		 6303 return 0;
6304}
6305
10ab25cd 6306int fx_init(struct kvm_vcpu *vcpu)
d0752060 6307{
10ab25cd
JK		 6308 int err;
6309
6310 err = fpu_alloc(&vcpu->arch.guest_fpu);
6311 if (err)
6312 return err;
6313
98918833 6314 fpu_finit(&vcpu->arch.guest_fpu);
d0752060 6315
2acf923e
DC		 6316 /*
6317 * Ensure guest xcr0 is valid for loading
6318 */
6319 vcpu->arch.xcr0 = XSTATE_FP;
6320
ad312c7c 6321 vcpu->arch.cr0 |= X86_CR0_ET;
10ab25cd
JK		 6322
6323 return 0;
d0752060
HB		 6324}
6325EXPORT_SYMBOL_GPL(fx_init);
6326
98918833
SY		 6327static void fx_free(struct kvm_vcpu *vcpu)
6328{
6329 fpu_free(&vcpu->arch.guest_fpu);
6330}
6331
d0752060
HB		 6332void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
6333{
2608d7a1 6334 if (vcpu->guest_fpu_loaded)
d0752060
HB		 6335 return;
6336
2acf923e
DC		 6337 /*
6338 * Restore all possible states in the guest,
6339 * and assume host would use all available bits.
6340 * Guest xcr0 would be loaded later.
6341 */
6342 kvm_put_guest_xcr0(vcpu);
d0752060 6343 vcpu->guest_fpu_loaded = 1;
7cf30855 6344 unlazy_fpu(current);
98918833 6345 fpu_restore_checking(&vcpu->arch.guest_fpu);
0c04851c 6346 trace_kvm_fpu(1);
d0752060 6347}
d0752060
HB		 6348
6349void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
6350{
2acf923e
DC		 6351 kvm_put_guest_xcr0(vcpu);
6352
d0752060
HB		 6353 if (!vcpu->guest_fpu_loaded)
6354 return;
6355
6356 vcpu->guest_fpu_loaded = 0;
98918833 6357 fpu_save_init(&vcpu->arch.guest_fpu);
f096ed85 6358 ++vcpu->stat.fpu_reload;
a8eeb04a 6359 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
0c04851c 6360 trace_kvm_fpu(0);
d0752060 6361}
e9b11c17
ZX		 6362
6363void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
6364{
12f9a48f 6365 kvmclock_reset(vcpu);
7f1ea208 6366
f5f48ee1 6367 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
98918833 6368 fx_free(vcpu);
e9b11c17
ZX		 6369 kvm_x86_ops->vcpu_free(vcpu);
6370}
6371
6372struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
6373 unsigned int id)
6374{
6755bae8
ZA		 6375 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6376 printk_once(KERN_WARNING
6377 "kvm: SMP vm created on host with unstable TSC; "
6378 "guest TSC will not be reliable\n");
26e5215f
AK		 6379 return kvm_x86_ops->vcpu_create(kvm, id);
6380}
e9b11c17 6381
26e5215f
AK		 6382int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
6383{
6384 int r;
e9b11c17 6385
0bed3b56 6386 vcpu->arch.mtrr_state.have_fixed = 1;
e9b11c17
ZX		 6387 vcpu_load(vcpu);
6388 r = kvm_arch_vcpu_reset(vcpu);
6389 if (r == 0)
6390 r = kvm_mmu_setup(vcpu);
6391 vcpu_put(vcpu);
e9b11c17 6392
26e5215f 6393 return r;
e9b11c17
ZX		 6394}
6395
d40ccc62 6396void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 6397{
344d9588
GN		 6398 vcpu->arch.apf.msr_val = 0;
6399
e9b11c17
ZX		 6400 vcpu_load(vcpu);
6401 kvm_mmu_unload(vcpu);
6402 vcpu_put(vcpu);
6403
98918833 6404 fx_free(vcpu);
e9b11c17
ZX		 6405 kvm_x86_ops->vcpu_free(vcpu);
6406}
6407
6408int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
6409{
7460fb4a
AK		 6410 atomic_set(&vcpu->arch.nmi_queued, 0);
6411 vcpu->arch.nmi_pending = 0;
448fa4a9
JK		 6412 vcpu->arch.nmi_injected = false;
6413
42dbaa5a
JK		 6414 vcpu->arch.switch_db_regs = 0;
6415 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
6416 vcpu->arch.dr6 = DR6_FIXED_1;
6417 vcpu->arch.dr7 = DR7_FIXED_1;
6418
3842d135 6419 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 6420 vcpu->arch.apf.msr_val = 0;
c9aaa895 6421 vcpu->arch.st.msr_val = 0;
3842d135 6422
12f9a48f
GC		 6423 kvmclock_reset(vcpu);
6424
af585b92
GN		 6425 kvm_clear_async_pf_completion_queue(vcpu);
6426 kvm_async_pf_hash_reset(vcpu);
6427 vcpu->arch.apf.halted = false;
3842d135 6428
e9b11c17
ZX		 6429 return kvm_x86_ops->vcpu_reset(vcpu);
6430}
6431
10474ae8 6432int kvm_arch_hardware_enable(void *garbage)
e9b11c17 6433{
ca84d1a2
ZA		 6434 struct kvm *kvm;
6435 struct kvm_vcpu *vcpu;
6436 int i;
18863bdd
AK		 6437
6438 kvm_shared_msr_cpu_online();
ca84d1a2
ZA		 6439 list_for_each_entry(kvm, &vm_list, vm_list)
6440 kvm_for_each_vcpu(i, vcpu, kvm)
6441 if (vcpu->cpu == smp_processor_id())
c285545f 6442 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
10474ae8 6443 return kvm_x86_ops->hardware_enable(garbage);
e9b11c17
ZX		 6444}
6445
6446void kvm_arch_hardware_disable(void *garbage)
6447{
6448 kvm_x86_ops->hardware_disable(garbage);
3548bab5 6449 drop_user_return_notifiers(garbage);
e9b11c17
ZX		 6450}
6451
6452int kvm_arch_hardware_setup(void)
6453{
6454 return kvm_x86_ops->hardware_setup();
6455}
6456
6457void kvm_arch_hardware_unsetup(void)
6458{
6459 kvm_x86_ops->hardware_unsetup();
6460}
6461
6462void kvm_arch_check_processor_compat(void *rtn)
6463{
6464 kvm_x86_ops->check_processor_compatibility(rtn);
6465}
6466
6467int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
6468{
6469 struct page *page;
6470 struct kvm *kvm;
6471 int r;
6472
6473 BUG_ON(vcpu->kvm == NULL);
6474 kvm = vcpu->kvm;
6475
9aabc88f 6476 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
14dfe855 6477 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
ad312c7c 6478 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
c30a358d 6479 vcpu->arch.mmu.translate_gpa = translate_gpa;
02f59dc9 6480 vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa;
c5af89b6 6481 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 6482 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 6483 else
a4535290 6484 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 6485
6486 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
6487 if (!page) {
6488 r = -ENOMEM;
6489 goto fail;
6490 }
ad312c7c 6491 vcpu->arch.pio_data = page_address(page);
e9b11c17 6492
1e993611 6493 kvm_init_tsc_catchup(vcpu, max_tsc_khz);
c285545f 6494
e9b11c17
ZX		 6495 r = kvm_mmu_create(vcpu);
6496 if (r < 0)
6497 goto fail_free_pio_data;
6498
6499 if (irqchip_in_kernel(kvm)) {
6500 r = kvm_create_lapic(vcpu);
6501 if (r < 0)
6502 goto fail_mmu_destroy;
6503 }
6504
890ca9ae
HY		 6505 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
6506 GFP_KERNEL);
6507 if (!vcpu->arch.mce_banks) {
6508 r = -ENOMEM;
443c39bc 6509 goto fail_free_lapic;
890ca9ae
HY		 6510 }
6511 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
6512
f5f48ee1
SY		 6513 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL))
6514 goto fail_free_mce_banks;
6515
af585b92
GN		 6516 kvm_async_pf_hash_reset(vcpu);
6517
e9b11c17 6518 return 0;
f5f48ee1
SY		 6519fail_free_mce_banks:
6520 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 6521fail_free_lapic:
6522 kvm_free_lapic(vcpu);
e9b11c17
ZX		 6523fail_mmu_destroy:
6524 kvm_mmu_destroy(vcpu);
6525fail_free_pio_data:
ad312c7c 6526 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 6527fail:
6528 return r;
6529}
6530
6531void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
6532{
f656ce01
MT		 6533 int idx;
6534
36cb93fd 6535 kfree(vcpu->arch.mce_banks);
e9b11c17 6536 kvm_free_lapic(vcpu);
f656ce01 6537 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 6538 kvm_mmu_destroy(vcpu);
f656ce01 6539 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 6540 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17 6541}
d19a9cd2 6542
d89f5eff 6543int kvm_arch_init_vm(struct kvm *kvm)
d19a9cd2 6544{
f05e70ac 6545 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4d5c5d0f 6546 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2 6547
5550af4d
SY		 6548 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
6549 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
6550
038f8c11 6551 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
53f658b3 6552
d89f5eff 6553 return 0;
d19a9cd2
ZX		 6554}
6555
6556static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
6557{
6558 vcpu_load(vcpu);
6559 kvm_mmu_unload(vcpu);
6560 vcpu_put(vcpu);
6561}
6562
6563static void kvm_free_vcpus(struct kvm *kvm)
6564{
6565 unsigned int i;
988a2cae 6566 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 6567
6568 /*
6569 * Unpin any mmu pages first.
6570 */
af585b92
GN		 6571 kvm_for_each_vcpu(i, vcpu, kvm) {
6572 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 6573 kvm_unload_vcpu_mmu(vcpu);
af585b92 6574 }
988a2cae
GN		 6575 kvm_for_each_vcpu(i, vcpu, kvm)
6576 kvm_arch_vcpu_free(vcpu);
6577
6578 mutex_lock(&kvm->lock);
6579 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
6580 kvm->vcpus[i] = NULL;
d19a9cd2 6581
988a2cae
GN		 6582 atomic_set(&kvm->online_vcpus, 0);
6583 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 6584}
6585
ad8ba2cd
SY		 6586void kvm_arch_sync_events(struct kvm *kvm)
6587{
ba4cef31 6588 kvm_free_all_assigned_devices(kvm);
aea924f6 6589 kvm_free_pit(kvm);
ad8ba2cd
SY		 6590}
6591
d19a9cd2
ZX		 6592void kvm_arch_destroy_vm(struct kvm *kvm)
6593{
6eb55818 6594 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 6595 kfree(kvm->arch.vpic);
6596 kfree(kvm->arch.vioapic);
d19a9cd2 6597 kvm_free_vcpus(kvm);
3d45830c
AK		 6598 if (kvm->arch.apic_access_page)
6599 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 6600 if (kvm->arch.ept_identity_pagetable)
6601 put_page(kvm->arch.ept_identity_pagetable);
d19a9cd2 6602}
0de10343 6603
f7784b8e
MT		 6604int kvm_arch_prepare_memory_region(struct kvm *kvm,
6605 struct kvm_memory_slot *memslot,
0de10343 6606 struct kvm_memory_slot old,
f7784b8e 6607 struct kvm_userspace_memory_region *mem,
0de10343
ZX		 6608 int user_alloc)
6609{
f7784b8e 6610 int npages = memslot->npages;
7ac77099
AK		 6611 int map_flags = MAP_PRIVATE | MAP_ANONYMOUS;
6612
6613 /* Prevent internal slot pages from being moved by fork()/COW. */
6614 if (memslot->id >= KVM_MEMORY_SLOTS)
6615 map_flags = MAP_SHARED | MAP_ANONYMOUS;
0de10343
ZX		 6616
6617 /*To keep backward compatibility with older userspace,
6618 *x86 needs to hanlde !user_alloc case.
6619 */
6620 if (!user_alloc) {
6621 if (npages && !old.rmap) {
604b38ac
AA		 6622 unsigned long userspace_addr;
6623
72dc67a6 6624 down_write(&current->mm->mmap_sem);
604b38ac
AA		 6625 userspace_addr = do_mmap(NULL, 0,
6626 npages * PAGE_SIZE,
6627 PROT_READ | PROT_WRITE,
7ac77099 6628 map_flags,
604b38ac 6629 0);
72dc67a6 6630 up_write(&current->mm->mmap_sem);
0de10343 6631
604b38ac
AA		 6632 if (IS_ERR((void *)userspace_addr))
6633 return PTR_ERR((void *)userspace_addr);
6634
604b38ac 6635 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 6636 }
6637 }
6638
f7784b8e
MT		 6639
6640 return 0;
6641}
6642
6643void kvm_arch_commit_memory_region(struct kvm *kvm,
6644 struct kvm_userspace_memory_region *mem,
6645 struct kvm_memory_slot old,
6646 int user_alloc)
6647{
6648
48c0e4e9 6649 int nr_mmu_pages = 0, npages = mem->memory_size >> PAGE_SHIFT;
f7784b8e
MT		 6650
6651 if (!user_alloc && !old.user_alloc && old.rmap && !npages) {
6652 int ret;
6653
6654 down_write(&current->mm->mmap_sem);
6655 ret = do_munmap(current->mm, old.userspace_addr,
6656 old.npages * PAGE_SIZE);
6657 up_write(&current->mm->mmap_sem);
6658 if (ret < 0)
6659 printk(KERN_WARNING
6660 "kvm_vm_ioctl_set_memory_region: "
6661 "failed to munmap memory\n");
6662 }
6663
48c0e4e9
XG		 6664 if (!kvm->arch.n_requested_mmu_pages)
6665 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
6666
7c8a83b7 6667 spin_lock(&kvm->mmu_lock);
48c0e4e9 6668 if (nr_mmu_pages)
0de10343 6669 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
0de10343 6670 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
7c8a83b7 6671 spin_unlock(&kvm->mmu_lock);
0de10343 6672}
1d737c8a 6673
34d4cb8f
MT		 6674void kvm_arch_flush_shadow(struct kvm *kvm)
6675{
6676 kvm_mmu_zap_all(kvm);
8986ecc0 6677 kvm_reload_remote_mmus(kvm);
34d4cb8f
MT		 6678}
6679
1d737c8a
ZX		 6680int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
6681{
af585b92
GN		 6682 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6683 !vcpu->arch.apf.halted)
6684 || !list_empty_careful(&vcpu->async_pf.done)
a1b37100 6685 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
7460fb4a 6686 || atomic_read(&vcpu->arch.nmi_queued) ||
a1b37100
GN		 6687 (kvm_arch_interrupt_allowed(vcpu) &&
6688 kvm_cpu_has_interrupt(vcpu));
1d737c8a 6689}
5736199a 6690
5736199a
ZX		 6691void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
6692{
32f88400
MT		 6693 int me;
6694 int cpu = vcpu->cpu;
5736199a
ZX		 6695
6696 if (waitqueue_active(&vcpu->wq)) {
6697 wake_up_interruptible(&vcpu->wq);
6698 ++vcpu->stat.halt_wakeup;
6699 }
32f88400
MT		 6700
6701 me = get_cpu();
6702 if (cpu != me && (unsigned)cpu < nr_cpu_ids && cpu_online(cpu))
6b7e2d09 6703 if (kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE)
32f88400 6704 smp_send_reschedule(cpu);
e9571ed5 6705 put_cpu();
5736199a 6706}
78646121
GN		 6707
6708int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
6709{
6710 return kvm_x86_ops->interrupt_allowed(vcpu);
6711}
229456fc 6712
f92653ee
JK		 6713bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
6714{
6715 unsigned long current_rip = kvm_rip_read(vcpu) +
6716 get_segment_base(vcpu, VCPU_SREG_CS);
6717
6718 return current_rip == linear_rip;
6719}
6720EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
6721
94fe45da
JK		 6722unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
6723{
6724 unsigned long rflags;
6725
6726 rflags = kvm_x86_ops->get_rflags(vcpu);
6727 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 6728 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 6729 return rflags;
6730}
6731EXPORT_SYMBOL_GPL(kvm_get_rflags);
6732
6733void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
6734{
6735 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 6736 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 6737 rflags |= X86_EFLAGS_TF;
94fe45da 6738 kvm_x86_ops->set_rflags(vcpu, rflags);
3842d135 6739 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 6740}
6741EXPORT_SYMBOL_GPL(kvm_set_rflags);
6742
56028d08
GN		 6743void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
6744{
6745 int r;
6746
fb67e14f 6747 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
c4806acd 6748 is_error_page(work->page))
56028d08
GN		 6749 return;
6750
6751 r = kvm_mmu_reload(vcpu);
6752 if (unlikely(r))
6753 return;
6754
fb67e14f
XG		 6755 if (!vcpu->arch.mmu.direct_map &&
6756 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
6757 return;
6758
56028d08
GN		 6759 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
6760}
6761
af585b92
GN		 6762static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
6763{
6764 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
6765}
6766
6767static inline u32 kvm_async_pf_next_probe(u32 key)
6768{
6769 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
6770}
6771
6772static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6773{
6774 u32 key = kvm_async_pf_hash_fn(gfn);
6775
6776 while (vcpu->arch.apf.gfns[key] != ~0)
6777 key = kvm_async_pf_next_probe(key);
6778
6779 vcpu->arch.apf.gfns[key] = gfn;
6780}
6781
6782static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
6783{
6784 int i;
6785 u32 key = kvm_async_pf_hash_fn(gfn);
6786
6787 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 6788 (vcpu->arch.apf.gfns[key] != gfn &&
6789 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 6790 key = kvm_async_pf_next_probe(key);
6791
6792 return key;
6793}
6794
6795bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6796{
6797 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
6798}
6799
6800static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6801{
6802 u32 i, j, k;
6803
6804 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
6805 while (true) {
6806 vcpu->arch.apf.gfns[i] = ~0;
6807 do {
6808 j = kvm_async_pf_next_probe(j);
6809 if (vcpu->arch.apf.gfns[j] == ~0)
6810 return;
6811 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
6812 /*
6813 * k lies cyclically in ]i,j]
6814 * | i.k.j |
6815 * |....j i.k.| or |.k..j i...|
6816 */
6817 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
6818 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
6819 i = j;
6820 }
6821}
6822
7c90705b
GN		 6823static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
6824{
6825
6826 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
6827 sizeof(val));
6828}
6829
af585b92
GN		 6830void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
6831 struct kvm_async_pf *work)
6832{
6389ee94
AK		 6833 struct x86_exception fault;
6834
7c90705b 6835 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 6836 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 6837
6838 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 6839 (vcpu->arch.apf.send_user_only &&
6840 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 6841 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
6842 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 6843 fault.vector = PF_VECTOR;
6844 fault.error_code_valid = true;
6845 fault.error_code = 0;
6846 fault.nested_page_fault = false;
6847 fault.address = work->arch.token;
6848 kvm_inject_page_fault(vcpu, &fault);
7c90705b 6849 }
af585b92
GN		 6850}
6851
6852void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
6853 struct kvm_async_pf *work)
6854{
6389ee94
AK		 6855 struct x86_exception fault;
6856
7c90705b
GN		 6857 trace_kvm_async_pf_ready(work->arch.token, work->gva);
6858 if (is_error_page(work->page))
6859 work->arch.token = ~0; /* broadcast wakeup */
6860 else
6861 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
6862
6863 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
6864 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 6865 fault.vector = PF_VECTOR;
6866 fault.error_code_valid = true;
6867 fault.error_code = 0;
6868 fault.nested_page_fault = false;
6869 fault.address = work->arch.token;
6870 kvm_inject_page_fault(vcpu, &fault);
7c90705b 6871 }
e6d53e3b 6872 vcpu->arch.apf.halted = false;
7c90705b
GN		 6873}
6874
6875bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
6876{
6877 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
6878 return true;
6879 else
6880 return !kvm_event_needs_reinjection(vcpu) &&
6881 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 6882}
6883
229456fc
MT		 6884EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
6885EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
6886EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
6887EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
6888EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 6889EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 6890EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 6891EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 6892EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 6893EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 6894EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 6895EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
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