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KVM: nVMX: Implement VMPTRLD
[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
313a3dc7 29
18068523 30#include <linux/clocksource.h>
4d5c5d0f 31#include <linux/interrupt.h>
313a3dc7
CO		 32#include <linux/kvm.h>
33#include <linux/fs.h>
34#include <linux/vmalloc.h>
5fb76f9b 35#include <linux/module.h>
0de10343 36#include <linux/mman.h>
2bacc55c 37#include <linux/highmem.h>
19de40a8 38#include <linux/iommu.h>
62c476c7 39#include <linux/intel-iommu.h>
c8076604 40#include <linux/cpufreq.h>
18863bdd 41#include <linux/user-return-notifier.h>
a983fb23 42#include <linux/srcu.h>
5a0e3ad6 43#include <linux/slab.h>
ff9d07a0 44#include <linux/perf_event.h>
7bee342a 45#include <linux/uaccess.h>
af585b92 46#include <linux/hash.h>
aec51dc4 47#include <trace/events/kvm.h>
2ed152af 48
229456fc
MT		 49#define CREATE_TRACE_POINTS
50#include "trace.h"
043405e1 51
24f1e32c 52#include <asm/debugreg.h>
d825ed0a 53#include <asm/msr.h>
a5f61300 54#include <asm/desc.h>
0bed3b56 55#include <asm/mtrr.h>
890ca9ae 56#include <asm/mce.h>
7cf30855 57#include <asm/i387.h>
98918833 58#include <asm/xcr.h>
1d5f066e 59#include <asm/pvclock.h>
217fc9cf 60#include <asm/div64.h>
043405e1 61
313a3dc7 62#define MAX_IO_MSRS 256
890ca9ae 63#define KVM_MAX_MCE_BANKS 32
5854dbca 64#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 65
0f65dd70
AK		 66#define emul_to_vcpu(ctxt) \
67 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
68
50a37eb4
JR		 69/* EFER defaults:
70 * - enable syscall per default because its emulated by KVM
71 * - enable LME and LMA per default on 64 bit KVM
72 */
73#ifdef CONFIG_X86_64
1260edbe
LJ		 74static
75u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 76#else
1260edbe 77static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 78#endif
313a3dc7 79
ba1389b7
AK		 80#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
81#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 82
cb142eb7 83static void update_cr8_intercept(struct kvm_vcpu *vcpu);
674eea0f
AK		 84static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
85 struct kvm_cpuid_entry2 __user *entries);
86
97896d04 87struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 88EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 89
ed85c068
AP		 90int ignore_msrs = 0;
91module_param_named(ignore_msrs, ignore_msrs, bool, S_IRUGO | S_IWUSR);
92
92a1f12d
JR		 93bool kvm_has_tsc_control;
94EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
95u32 kvm_max_guest_tsc_khz;
96EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
97
18863bdd
AK		 98#define KVM_NR_SHARED_MSRS 16
99
100struct kvm_shared_msrs_global {
101 int nr;
2bf78fa7 102 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 103};
104
105struct kvm_shared_msrs {
106 struct user_return_notifier urn;
107 bool registered;
2bf78fa7
SY		 108 struct kvm_shared_msr_values {
109 u64 host;
110 u64 curr;
111 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 112};
113
114static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
115static DEFINE_PER_CPU(struct kvm_shared_msrs, shared_msrs);
116
417bc304 117struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 118 { "pf_fixed", VCPU_STAT(pf_fixed) },
119 { "pf_guest", VCPU_STAT(pf_guest) },
120 { "tlb_flush", VCPU_STAT(tlb_flush) },
121 { "invlpg", VCPU_STAT(invlpg) },
122 { "exits", VCPU_STAT(exits) },
123 { "io_exits", VCPU_STAT(io_exits) },
124 { "mmio_exits", VCPU_STAT(mmio_exits) },
125 { "signal_exits", VCPU_STAT(signal_exits) },
126 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 127 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 128 { "halt_exits", VCPU_STAT(halt_exits) },
129 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 130 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 131 { "request_irq", VCPU_STAT(request_irq_exits) },
132 { "irq_exits", VCPU_STAT(irq_exits) },
133 { "host_state_reload", VCPU_STAT(host_state_reload) },
134 { "efer_reload", VCPU_STAT(efer_reload) },
135 { "fpu_reload", VCPU_STAT(fpu_reload) },
136 { "insn_emulation", VCPU_STAT(insn_emulation) },
137 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 138 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 139 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 140 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
141 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
142 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
143 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
144 { "mmu_flooded", VM_STAT(mmu_flooded) },
145 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 146 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 147 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 148 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 149 { "largepages", VM_STAT(lpages) },
417bc304
HB		 150 { NULL }
151};
152
2acf923e
DC		 153u64 __read_mostly host_xcr0;
154
d6aa1000
AK		 155int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
156
af585b92
GN		 157static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
158{
159 int i;
160 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
161 vcpu->arch.apf.gfns[i] = ~0;
162}
163
18863bdd
AK		 164static void kvm_on_user_return(struct user_return_notifier *urn)
165{
166 unsigned slot;
18863bdd
AK		 167 struct kvm_shared_msrs *locals
168 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 169 struct kvm_shared_msr_values *values;
18863bdd
AK		 170
171 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 172 values = &locals->values[slot];
173 if (values->host != values->curr) {
174 wrmsrl(shared_msrs_global.msrs[slot], values->host);
175 values->curr = values->host;
18863bdd
AK		 176 }
177 }
178 locals->registered = false;
179 user_return_notifier_unregister(urn);
180}
181
2bf78fa7 182static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 183{
2bf78fa7 184 struct kvm_shared_msrs *smsr;
18863bdd
AK		 185 u64 value;
186
2bf78fa7
SY		 187 smsr = &__get_cpu_var(shared_msrs);
188 /* only read, and nobody should modify it at this time,
189 * so don't need lock */
190 if (slot >= shared_msrs_global.nr) {
191 printk(KERN_ERR "kvm: invalid MSR slot!");
192 return;
193 }
194 rdmsrl_safe(msr, &value);
195 smsr->values[slot].host = value;
196 smsr->values[slot].curr = value;
197}
198
199void kvm_define_shared_msr(unsigned slot, u32 msr)
200{
18863bdd
AK		 201 if (slot >= shared_msrs_global.nr)
202 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 203 shared_msrs_global.msrs[slot] = msr;
204 /* we need ensured the shared_msr_global have been updated */
205 smp_wmb();
18863bdd
AK		 206}
207EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
208
209static void kvm_shared_msr_cpu_online(void)
210{
211 unsigned i;
18863bdd
AK		 212
213 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 214 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 215}
216
d5696725 217void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd
AK		 218{
219 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
220
2bf78fa7 221 if (((value ^ smsr->values[slot].curr) & mask) == 0)
18863bdd 222 return;
2bf78fa7
SY		 223 smsr->values[slot].curr = value;
224 wrmsrl(shared_msrs_global.msrs[slot], value);
18863bdd
AK		 225 if (!smsr->registered) {
226 smsr->urn.on_user_return = kvm_on_user_return;
227 user_return_notifier_register(&smsr->urn);
228 smsr->registered = true;
229 }
230}
231EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
232
3548bab5
AK		 233static void drop_user_return_notifiers(void *ignore)
234{
235 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
236
237 if (smsr->registered)
238 kvm_on_user_return(&smsr->urn);
239}
240
6866b83e
CO		 241u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
242{
243 if (irqchip_in_kernel(vcpu->kvm))
ad312c7c 244 return vcpu->arch.apic_base;
6866b83e 245 else
ad312c7c 246 return vcpu->arch.apic_base;
6866b83e
CO		 247}
248EXPORT_SYMBOL_GPL(kvm_get_apic_base);
249
250void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
251{
252 /* TODO: reserve bits check */
253 if (irqchip_in_kernel(vcpu->kvm))
254 kvm_lapic_set_base(vcpu, data);
255 else
ad312c7c 256 vcpu->arch.apic_base = data;
6866b83e
CO		 257}
258EXPORT_SYMBOL_GPL(kvm_set_apic_base);
259
3fd28fce
ED		 260#define EXCPT_BENIGN 0
261#define EXCPT_CONTRIBUTORY 1
262#define EXCPT_PF 2
263
264static int exception_class(int vector)
265{
266 switch (vector) {
267 case PF_VECTOR:
268 return EXCPT_PF;
269 case DE_VECTOR:
270 case TS_VECTOR:
271 case NP_VECTOR:
272 case SS_VECTOR:
273 case GP_VECTOR:
274 return EXCPT_CONTRIBUTORY;
275 default:
276 break;
277 }
278 return EXCPT_BENIGN;
279}
280
281static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 282 unsigned nr, bool has_error, u32 error_code,
283 bool reinject)
3fd28fce
ED		 284{
285 u32 prev_nr;
286 int class1, class2;
287
3842d135
AK		 288 kvm_make_request(KVM_REQ_EVENT, vcpu);
289
3fd28fce
ED		 290 if (!vcpu->arch.exception.pending) {
291 queue:
292 vcpu->arch.exception.pending = true;
293 vcpu->arch.exception.has_error_code = has_error;
294 vcpu->arch.exception.nr = nr;
295 vcpu->arch.exception.error_code = error_code;
3f0fd292 296 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 297 return;
298 }
299
300 /* to check exception */
301 prev_nr = vcpu->arch.exception.nr;
302 if (prev_nr == DF_VECTOR) {
303 /* triple fault -> shutdown */
a8eeb04a 304 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 305 return;
306 }
307 class1 = exception_class(prev_nr);
308 class2 = exception_class(nr);
309 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
310 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
311 /* generate double fault per SDM Table 5-5 */
312 vcpu->arch.exception.pending = true;
313 vcpu->arch.exception.has_error_code = true;
314 vcpu->arch.exception.nr = DF_VECTOR;
315 vcpu->arch.exception.error_code = 0;
316 } else
317 /* replace previous exception with a new one in a hope
318 that instruction re-execution will regenerate lost
319 exception */
320 goto queue;
321}
322
298101da
AK		 323void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
324{
ce7ddec4 325 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 326}
327EXPORT_SYMBOL_GPL(kvm_queue_exception);
328
ce7ddec4
JR		 329void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
330{
331 kvm_multiple_exception(vcpu, nr, false, 0, true);
332}
333EXPORT_SYMBOL_GPL(kvm_requeue_exception);
334
db8fcefa 335void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 336{
db8fcefa
AP		 337 if (err)
338 kvm_inject_gp(vcpu, 0);
339 else
340 kvm_x86_ops->skip_emulated_instruction(vcpu);
341}
342EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 343
6389ee94 344void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 345{
346 ++vcpu->stat.pf_guest;
6389ee94
AK		 347 vcpu->arch.cr2 = fault->address;
348 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 349}
27d6c865 350EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 351
6389ee94 352void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 353{
6389ee94
AK		 354 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
355 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 356 else
6389ee94 357 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
d4f8cf66
JR		 358}
359
3419ffc8
SY		 360void kvm_inject_nmi(struct kvm_vcpu *vcpu)
361{
3842d135 362 kvm_make_request(KVM_REQ_EVENT, vcpu);
c761e586 363 vcpu->arch.nmi_pending = 1;
3419ffc8
SY		 364}
365EXPORT_SYMBOL_GPL(kvm_inject_nmi);
366
298101da
AK		 367void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
368{
ce7ddec4 369 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 370}
371EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
372
ce7ddec4
JR		 373void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
374{
375 kvm_multiple_exception(vcpu, nr, true, error_code, true);
376}
377EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
378
0a79b009
AK		 379/*
380 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
381 * a #GP and return false.
382 */
383bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 384{
0a79b009
AK		 385 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
386 return true;
387 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
388 return false;
298101da 389}
0a79b009 390EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 391
ec92fe44
JR		 392/*
393 * This function will be used to read from the physical memory of the currently
394 * running guest. The difference to kvm_read_guest_page is that this function
395 * can read from guest physical or from the guest's guest physical memory.
396 */
397int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
398 gfn_t ngfn, void *data, int offset, int len,
399 u32 access)
400{
401 gfn_t real_gfn;
402 gpa_t ngpa;
403
404 ngpa = gfn_to_gpa(ngfn);
405 real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
406 if (real_gfn == UNMAPPED_GVA)
407 return -EFAULT;
408
409 real_gfn = gpa_to_gfn(real_gfn);
410
411 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
412}
413EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
414
3d06b8bf
JR		 415int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
416 void *data, int offset, int len, u32 access)
417{
418 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
419 data, offset, len, access);
420}
421
a03490ed
CO		 422/*
423 * Load the pae pdptrs. Return true is they are all valid.
424 */
ff03a073 425int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 426{
427 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
428 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
429 int i;
430 int ret;
ff03a073 431 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 432
ff03a073
JR		 433 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
434 offset * sizeof(u64), sizeof(pdpte),
435 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 436 if (ret < 0) {
437 ret = 0;
438 goto out;
439 }
440 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 441 if (is_present_gpte(pdpte[i]) &&
20c466b5 442 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 443 ret = 0;
444 goto out;
445 }
446 }
447 ret = 1;
448
ff03a073 449 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 450 __set_bit(VCPU_EXREG_PDPTR,
451 (unsigned long *)&vcpu->arch.regs_avail);
452 __set_bit(VCPU_EXREG_PDPTR,
453 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 454out:
a03490ed
CO		 455
456 return ret;
457}
cc4b6871 458EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 459
d835dfec
AK		 460static bool pdptrs_changed(struct kvm_vcpu *vcpu)
461{
ff03a073 462 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 463 bool changed = true;
3d06b8bf
JR		 464 int offset;
465 gfn_t gfn;
d835dfec
AK		 466 int r;
467
468 if (is_long_mode(vcpu) || !is_pae(vcpu))
469 return false;
470
6de4f3ad
AK		 471 if (!test_bit(VCPU_EXREG_PDPTR,
472 (unsigned long *)&vcpu->arch.regs_avail))
473 return true;
474
9f8fe504
AK		 475 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
476 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 477 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
478 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 479 if (r < 0)
480 goto out;
ff03a073 481 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 482out:
d835dfec
AK		 483
484 return changed;
485}
486
49a9b07e 487int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 488{
aad82703
SY		 489 unsigned long old_cr0 = kvm_read_cr0(vcpu);
490 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
491 X86_CR0_CD | X86_CR0_NW;
492
f9a48e6a
AK		 493 cr0 |= X86_CR0_ET;
494
ab344828 495#ifdef CONFIG_X86_64
0f12244f
GN		 496 if (cr0 & 0xffffffff00000000UL)
497 return 1;
ab344828
GN		 498#endif
499
500 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 501
0f12244f
GN		 502 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
503 return 1;
a03490ed 504
0f12244f
GN		 505 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
506 return 1;
a03490ed
CO		 507
508 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
509#ifdef CONFIG_X86_64
f6801dff 510 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 511 int cs_db, cs_l;
512
0f12244f
GN		 513 if (!is_pae(vcpu))
514 return 1;
a03490ed 515 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 516 if (cs_l)
517 return 1;
a03490ed
CO		 518 } else
519#endif
ff03a073 520 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 521 kvm_read_cr3(vcpu)))
0f12244f 522 return 1;
a03490ed
CO		 523 }
524
525 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 526
d170c419 527 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 528 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 529 kvm_async_pf_hash_reset(vcpu);
530 }
e5f3f027 531
aad82703
SY		 532 if ((cr0 ^ old_cr0) & update_bits)
533 kvm_mmu_reset_context(vcpu);
0f12244f
GN		 534 return 0;
535}
2d3ad1f4 536EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 537
2d3ad1f4 538void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 539{
49a9b07e 540 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 541}
2d3ad1f4 542EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 543
2acf923e
DC		 544int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
545{
546 u64 xcr0;
547
548 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
549 if (index != XCR_XFEATURE_ENABLED_MASK)
550 return 1;
551 xcr0 = xcr;
552 if (kvm_x86_ops->get_cpl(vcpu) != 0)
553 return 1;
554 if (!(xcr0 & XSTATE_FP))
555 return 1;
556 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
557 return 1;
558 if (xcr0 & ~host_xcr0)
559 return 1;
560 vcpu->arch.xcr0 = xcr0;
561 vcpu->guest_xcr0_loaded = 0;
562 return 0;
563}
564
565int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
566{
567 if (__kvm_set_xcr(vcpu, index, xcr)) {
568 kvm_inject_gp(vcpu, 0);
569 return 1;
570 }
571 return 0;
572}
573EXPORT_SYMBOL_GPL(kvm_set_xcr);
574
575static bool guest_cpuid_has_xsave(struct kvm_vcpu *vcpu)
576{
577 struct kvm_cpuid_entry2 *best;
578
579 best = kvm_find_cpuid_entry(vcpu, 1, 0);
580 return best && (best->ecx & bit(X86_FEATURE_XSAVE));
581}
582
583static void update_cpuid(struct kvm_vcpu *vcpu)
584{
585 struct kvm_cpuid_entry2 *best;
586
587 best = kvm_find_cpuid_entry(vcpu, 1, 0);
588 if (!best)
589 return;
590
591 /* Update OSXSAVE bit */
592 if (cpu_has_xsave && best->function == 0x1) {
593 best->ecx &= ~(bit(X86_FEATURE_OSXSAVE));
594 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE))
595 best->ecx |= bit(X86_FEATURE_OSXSAVE);
596 }
597}
598
a83b29c6 599int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 600{
fc78f519 601 unsigned long old_cr4 = kvm_read_cr4(vcpu);
a2edf57f
AK		 602 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE;
603
0f12244f
GN		 604 if (cr4 & CR4_RESERVED_BITS)
605 return 1;
a03490ed 606
2acf923e
DC		 607 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
608 return 1;
609
a03490ed 610 if (is_long_mode(vcpu)) {
0f12244f
GN		 611 if (!(cr4 & X86_CR4_PAE))
612 return 1;
a2edf57f
AK		 613 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
614 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 615 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
616 kvm_read_cr3(vcpu)))
0f12244f
GN		 617 return 1;
618
5e1746d6 619 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 620 return 1;
a03490ed 621
aad82703
SY		 622 if ((cr4 ^ old_cr4) & pdptr_bits)
623 kvm_mmu_reset_context(vcpu);
0f12244f 624
2acf923e
DC		 625 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
626 update_cpuid(vcpu);
627
0f12244f
GN		 628 return 0;
629}
2d3ad1f4 630EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 631
2390218b 632int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 633{
9f8fe504 634 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 635 kvm_mmu_sync_roots(vcpu);
d835dfec 636 kvm_mmu_flush_tlb(vcpu);
0f12244f 637 return 0;
d835dfec
AK		 638 }
639
a03490ed 640 if (is_long_mode(vcpu)) {
0f12244f
GN		 641 if (cr3 & CR3_L_MODE_RESERVED_BITS)
642 return 1;
a03490ed
CO		 643 } else {
644 if (is_pae(vcpu)) {
0f12244f
GN		 645 if (cr3 & CR3_PAE_RESERVED_BITS)
646 return 1;
ff03a073
JR		 647 if (is_paging(vcpu) &&
648 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
0f12244f 649 return 1;
a03490ed
CO		 650 }
651 /*
652 * We don't check reserved bits in nonpae mode, because
653 * this isn't enforced, and VMware depends on this.
654 */
655 }
656
a03490ed
CO		 657 /*
658 * Does the new cr3 value map to physical memory? (Note, we
659 * catch an invalid cr3 even in real-mode, because it would
660 * cause trouble later on when we turn on paging anyway.)
661 *
662 * A real CPU would silently accept an invalid cr3 and would
663 * attempt to use it - with largely undefined (and often hard
664 * to debug) behavior on the guest side.
665 */
666 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
0f12244f
GN		 667 return 1;
668 vcpu->arch.cr3 = cr3;
aff48baa 669 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
0f12244f
GN		 670 vcpu->arch.mmu.new_cr3(vcpu);
671 return 0;
672}
2d3ad1f4 673EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 674
eea1cff9 675int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 676{
0f12244f
GN		 677 if (cr8 & CR8_RESERVED_BITS)
678 return 1;
a03490ed
CO		 679 if (irqchip_in_kernel(vcpu->kvm))
680 kvm_lapic_set_tpr(vcpu, cr8);
681 else
ad312c7c 682 vcpu->arch.cr8 = cr8;
0f12244f
GN		 683 return 0;
684}
2d3ad1f4 685EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 686
2d3ad1f4 687unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 688{
689 if (irqchip_in_kernel(vcpu->kvm))
690 return kvm_lapic_get_cr8(vcpu);
691 else
ad312c7c 692 return vcpu->arch.cr8;
a03490ed 693}
2d3ad1f4 694EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 695
338dbc97 696static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 697{
698 switch (dr) {
699 case 0 ... 3:
700 vcpu->arch.db[dr] = val;
701 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
702 vcpu->arch.eff_db[dr] = val;
703 break;
704 case 4:
338dbc97
GN		 705 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
706 return 1; /* #UD */
020df079
GN		 707 /* fall through */
708 case 6:
338dbc97
GN		 709 if (val & 0xffffffff00000000ULL)
710 return -1; /* #GP */
020df079
GN		 711 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
712 break;
713 case 5:
338dbc97
GN		 714 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
715 return 1; /* #UD */
020df079
GN		 716 /* fall through */
717 default: /* 7 */
338dbc97
GN		 718 if (val & 0xffffffff00000000ULL)
719 return -1; /* #GP */
020df079
GN		 720 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
721 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
722 kvm_x86_ops->set_dr7(vcpu, vcpu->arch.dr7);
723 vcpu->arch.switch_db_regs = (val & DR7_BP_EN_MASK);
724 }
725 break;
726 }
727
728 return 0;
729}
338dbc97
GN		 730
731int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
732{
733 int res;
734
735 res = __kvm_set_dr(vcpu, dr, val);
736 if (res > 0)
737 kvm_queue_exception(vcpu, UD_VECTOR);
738 else if (res < 0)
739 kvm_inject_gp(vcpu, 0);
740
741 return res;
742}
020df079
GN		 743EXPORT_SYMBOL_GPL(kvm_set_dr);
744
338dbc97 745static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 746{
747 switch (dr) {
748 case 0 ... 3:
749 *val = vcpu->arch.db[dr];
750 break;
751 case 4:
338dbc97 752 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 753 return 1;
020df079
GN		 754 /* fall through */
755 case 6:
756 *val = vcpu->arch.dr6;
757 break;
758 case 5:
338dbc97 759 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 760 return 1;
020df079
GN		 761 /* fall through */
762 default: /* 7 */
763 *val = vcpu->arch.dr7;
764 break;
765 }
766
767 return 0;
768}
338dbc97
GN		 769
770int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
771{
772 if (_kvm_get_dr(vcpu, dr, val)) {
773 kvm_queue_exception(vcpu, UD_VECTOR);
774 return 1;
775 }
776 return 0;
777}
020df079
GN		 778EXPORT_SYMBOL_GPL(kvm_get_dr);
779
043405e1
CO		 780/*
781 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
782 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
783 *
784 * This list is modified at module load time to reflect the
e3267cbb
GC		 785 * capabilities of the host cpu. This capabilities test skips MSRs that are
786 * kvm-specific. Those are put in the beginning of the list.
043405e1 787 */
e3267cbb 788
344d9588 789#define KVM_SAVE_MSRS_BEGIN 8
043405e1 790static u32 msrs_to_save[] = {
e3267cbb 791 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
11c6bffa 792 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
55cd8e5a 793 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
344d9588 794 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN,
043405e1 795 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 796 MSR_STAR,
043405e1
CO		 797#ifdef CONFIG_X86_64
798 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
799#endif
e90aa41e 800 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
043405e1
CO		 801};
802
803static unsigned num_msrs_to_save;
804
805static u32 emulated_msrs[] = {
806 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 807 MSR_IA32_MCG_STATUS,
808 MSR_IA32_MCG_CTL,
043405e1
CO		 809};
810
b69e8cae 811static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 812{
aad82703
SY		 813 u64 old_efer = vcpu->arch.efer;
814
b69e8cae
RJ		 815 if (efer & efer_reserved_bits)
816 return 1;
15c4a640
CO		 817
818 if (is_paging(vcpu)
b69e8cae
RJ		 819 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
820 return 1;
15c4a640 821
1b2fd70c
AG		 822 if (efer & EFER_FFXSR) {
823 struct kvm_cpuid_entry2 *feat;
824
825 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 826 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
827 return 1;
1b2fd70c
AG		 828 }
829
d8017474
AG		 830 if (efer & EFER_SVME) {
831 struct kvm_cpuid_entry2 *feat;
832
833 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 834 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
835 return 1;
d8017474
AG		 836 }
837
15c4a640 838 efer &= ~EFER_LMA;
f6801dff 839 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 840
a3d204e2
SY		 841 kvm_x86_ops->set_efer(vcpu, efer);
842
9645bb56 843 vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
b69e8cae 844
aad82703
SY		 845 /* Update reserved bits */
846 if ((efer ^ old_efer) & EFER_NX)
847 kvm_mmu_reset_context(vcpu);
848
b69e8cae 849 return 0;
15c4a640
CO		 850}
851
f2b4b7dd
JR		 852void kvm_enable_efer_bits(u64 mask)
853{
854 efer_reserved_bits &= ~mask;
855}
856EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
857
858
15c4a640
CO		 859/*
860 * Writes msr value into into the appropriate "register".
861 * Returns 0 on success, non-0 otherwise.
862 * Assumes vcpu_load() was already called.
863 */
864int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
865{
866 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
867}
868
313a3dc7
CO		 869/*
870 * Adapt set_msr() to msr_io()'s calling convention
871 */
872static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
873{
874 return kvm_set_msr(vcpu, index, *data);
875}
876
18068523
GOC		 877static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
878{
9ed3c444
AK		 879 int version;
880 int r;
50d0a0f9 881 struct pvclock_wall_clock wc;
923de3cf 882 struct timespec boot;
18068523
GOC		 883
884 if (!wall_clock)
885 return;
886
9ed3c444
AK		 887 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
888 if (r)
889 return;
890
891 if (version & 1)
892 ++version; /* first time write, random junk */
893
894 ++version;
18068523 895
18068523
GOC		 896 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
897
50d0a0f9
GH		 898 /*
899 * The guest calculates current wall clock time by adding
34c238a1 900 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 901 * wall clock specified here. guest system time equals host
902 * system time for us, thus we must fill in host boot time here.
903 */
923de3cf 904 getboottime(&boot);
50d0a0f9
GH		 905
906 wc.sec = boot.tv_sec;
907 wc.nsec = boot.tv_nsec;
908 wc.version = version;
18068523
GOC		 909
910 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
911
912 version++;
913 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 914}
915
50d0a0f9
GH		 916static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
917{
918 uint32_t quotient, remainder;
919
920 /* Don't try to replace with do_div(), this one calculates
921 * "(dividend << 32) / divisor" */
922 __asm__ ( "divl %4"
923 : "=a" (quotient), "=d" (remainder)
924 : "0" (0), "1" (dividend), "r" (divisor) );
925 return quotient;
926}
927
5f4e3f88
ZA		 928static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
929 s8 *pshift, u32 *pmultiplier)
50d0a0f9 930{
5f4e3f88 931 uint64_t scaled64;
50d0a0f9
GH		 932 int32_t shift = 0;
933 uint64_t tps64;
934 uint32_t tps32;
935
5f4e3f88
ZA		 936 tps64 = base_khz * 1000LL;
937 scaled64 = scaled_khz * 1000LL;
50933623 938 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 939 tps64 >>= 1;
940 shift--;
941 }
942
943 tps32 = (uint32_t)tps64;
50933623
JK		 944 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
945 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 946 scaled64 >>= 1;
947 else
948 tps32 <<= 1;
50d0a0f9
GH		 949 shift++;
950 }
951
5f4e3f88
ZA		 952 *pshift = shift;
953 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 954
5f4e3f88
ZA		 955 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
956 __func__, base_khz, scaled_khz, shift, *pmultiplier);
50d0a0f9
GH		 957}
958
759379dd
ZA		 959static inline u64 get_kernel_ns(void)
960{
961 struct timespec ts;
962
963 WARN_ON(preemptible());
964 ktime_get_ts(&ts);
965 monotonic_to_bootbased(&ts);
966 return timespec_to_ns(&ts);
50d0a0f9
GH		 967}
968
c8076604 969static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
c285545f 970unsigned long max_tsc_khz;
c8076604 971
8cfdc000
ZA		 972static inline int kvm_tsc_changes_freq(void)
973{
974 int cpu = get_cpu();
975 int ret = !boot_cpu_has(X86_FEATURE_CONSTANT_TSC) &&
976 cpufreq_quick_get(cpu) != 0;
977 put_cpu();
978 return ret;
979}
980
1e993611
JR		 981static u64 vcpu_tsc_khz(struct kvm_vcpu *vcpu)
982{
983 if (vcpu->arch.virtual_tsc_khz)
984 return vcpu->arch.virtual_tsc_khz;
985 else
986 return __this_cpu_read(cpu_tsc_khz);
987}
988
857e4099 989static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
759379dd 990{
217fc9cf
AK		 991 u64 ret;
992
759379dd
ZA		 993 WARN_ON(preemptible());
994 if (kvm_tsc_changes_freq())
995 printk_once(KERN_WARNING
996 "kvm: unreliable cycle conversion on adjustable rate TSC\n");
857e4099 997 ret = nsec * vcpu_tsc_khz(vcpu);
217fc9cf
AK		 998 do_div(ret, USEC_PER_SEC);
999 return ret;
759379dd
ZA		 1000}
1001
1e993611 1002static void kvm_init_tsc_catchup(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
c285545f
ZA		 1003{
1004 /* Compute a scale to convert nanoseconds in TSC cycles */
1005 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
1e993611
JR		 1006 &vcpu->arch.tsc_catchup_shift,
1007 &vcpu->arch.tsc_catchup_mult);
c285545f
ZA		 1008}
1009
1010static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1011{
1012 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.last_tsc_nsec,
1e993611
JR		 1013 vcpu->arch.tsc_catchup_mult,
1014 vcpu->arch.tsc_catchup_shift);
c285545f
ZA		 1015 tsc += vcpu->arch.last_tsc_write;
1016 return tsc;
1017}
1018
99e3e30a
ZA		 1019void kvm_write_tsc(struct kvm_vcpu *vcpu, u64 data)
1020{
1021 struct kvm *kvm = vcpu->kvm;
f38e098f 1022 u64 offset, ns, elapsed;
99e3e30a 1023 unsigned long flags;
46543ba4 1024 s64 sdiff;
99e3e30a 1025
038f8c11 1026 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
857e4099 1027 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1028 ns = get_kernel_ns();
f38e098f 1029 elapsed = ns - kvm->arch.last_tsc_nsec;
46543ba4
ZA		 1030 sdiff = data - kvm->arch.last_tsc_write;
1031 if (sdiff < 0)
1032 sdiff = -sdiff;
f38e098f
ZA		 1033
1034 /*
46543ba4 1035 * Special case: close write to TSC within 5 seconds of
f38e098f 1036 * another CPU is interpreted as an attempt to synchronize
0d2eb44f 1037 * The 5 seconds is to accommodate host load / swapping as
46543ba4 1038 * well as any reset of TSC during the boot process.
f38e098f
ZA		 1039 *
1040 * In that case, for a reliable TSC, we can match TSC offsets,
46543ba4 1041 * or make a best guest using elapsed value.
f38e098f 1042 */
857e4099 1043 if (sdiff < nsec_to_cycles(vcpu, 5ULL * NSEC_PER_SEC) &&
46543ba4 1044 elapsed < 5ULL * NSEC_PER_SEC) {
f38e098f
ZA		 1045 if (!check_tsc_unstable()) {
1046 offset = kvm->arch.last_tsc_offset;
1047 pr_debug("kvm: matched tsc offset for %llu\n", data);
1048 } else {
857e4099 1049 u64 delta = nsec_to_cycles(vcpu, elapsed);
759379dd
ZA		 1050 offset += delta;
1051 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f
ZA		 1052 }
1053 ns = kvm->arch.last_tsc_nsec;
1054 }
1055 kvm->arch.last_tsc_nsec = ns;
1056 kvm->arch.last_tsc_write = data;
1057 kvm->arch.last_tsc_offset = offset;
99e3e30a 1058 kvm_x86_ops->write_tsc_offset(vcpu, offset);
038f8c11 1059 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
99e3e30a
ZA		 1060
1061 /* Reset of TSC must disable overshoot protection below */
1062 vcpu->arch.hv_clock.tsc_timestamp = 0;
c285545f
ZA		 1063 vcpu->arch.last_tsc_write = data;
1064 vcpu->arch.last_tsc_nsec = ns;
99e3e30a
ZA		 1065}
1066EXPORT_SYMBOL_GPL(kvm_write_tsc);
1067
34c238a1 1068static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1069{
18068523
GOC		 1070 unsigned long flags;
1071 struct kvm_vcpu_arch *vcpu = &v->arch;
1072 void *shared_kaddr;
463656c0 1073 unsigned long this_tsc_khz;
1d5f066e
ZA		 1074 s64 kernel_ns, max_kernel_ns;
1075 u64 tsc_timestamp;
18068523 1076
18068523
GOC		 1077 /* Keep irq disabled to prevent changes to the clock */
1078 local_irq_save(flags);
1d5f066e 1079 kvm_get_msr(v, MSR_IA32_TSC, &tsc_timestamp);
759379dd 1080 kernel_ns = get_kernel_ns();
1e993611 1081 this_tsc_khz = vcpu_tsc_khz(v);
8cfdc000 1082 if (unlikely(this_tsc_khz == 0)) {
c285545f 1083 local_irq_restore(flags);
34c238a1 1084 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
8cfdc000
ZA		 1085 return 1;
1086 }
18068523 1087
c285545f
ZA		 1088 /*
1089 * We may have to catch up the TSC to match elapsed wall clock
1090 * time for two reasons, even if kvmclock is used.
1091 * 1) CPU could have been running below the maximum TSC rate
1092 * 2) Broken TSC compensation resets the base at each VCPU
1093 * entry to avoid unknown leaps of TSC even when running
1094 * again on the same CPU. This may cause apparent elapsed
1095 * time to disappear, and the guest to stand still or run
1096 * very slowly.
1097 */
1098 if (vcpu->tsc_catchup) {
1099 u64 tsc = compute_guest_tsc(v, kernel_ns);
1100 if (tsc > tsc_timestamp) {
1101 kvm_x86_ops->adjust_tsc_offset(v, tsc - tsc_timestamp);
1102 tsc_timestamp = tsc;
1103 }
50d0a0f9
GH		 1104 }
1105
18068523
GOC		 1106 local_irq_restore(flags);
1107
c285545f
ZA		 1108 if (!vcpu->time_page)
1109 return 0;
18068523 1110
1d5f066e
ZA		 1111 /*
1112 * Time as measured by the TSC may go backwards when resetting the base
1113 * tsc_timestamp. The reason for this is that the TSC resolution is
1114 * higher than the resolution of the other clock scales. Thus, many
1115 * possible measurments of the TSC correspond to one measurement of any
1116 * other clock, and so a spread of values is possible. This is not a
1117 * problem for the computation of the nanosecond clock; with TSC rates
1118 * around 1GHZ, there can only be a few cycles which correspond to one
1119 * nanosecond value, and any path through this code will inevitably
1120 * take longer than that. However, with the kernel_ns value itself,
1121 * the precision may be much lower, down to HZ granularity. If the
1122 * first sampling of TSC against kernel_ns ends in the low part of the
1123 * range, and the second in the high end of the range, we can get:
1124 *
1125 * (TSC - offset_low) * S + kns_old > (TSC - offset_high) * S + kns_new
1126 *
1127 * As the sampling errors potentially range in the thousands of cycles,
1128 * it is possible such a time value has already been observed by the
1129 * guest. To protect against this, we must compute the system time as
1130 * observed by the guest and ensure the new system time is greater.
1131 */
1132 max_kernel_ns = 0;
1133 if (vcpu->hv_clock.tsc_timestamp && vcpu->last_guest_tsc) {
1134 max_kernel_ns = vcpu->last_guest_tsc -
1135 vcpu->hv_clock.tsc_timestamp;
1136 max_kernel_ns = pvclock_scale_delta(max_kernel_ns,
1137 vcpu->hv_clock.tsc_to_system_mul,
1138 vcpu->hv_clock.tsc_shift);
1139 max_kernel_ns += vcpu->last_kernel_ns;
1140 }
afbcf7ab 1141
e48672fa 1142 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
5f4e3f88
ZA		 1143 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1144 &vcpu->hv_clock.tsc_shift,
1145 &vcpu->hv_clock.tsc_to_system_mul);
e48672fa 1146 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1147 }
1148
1d5f066e
ZA		 1149 if (max_kernel_ns > kernel_ns)
1150 kernel_ns = max_kernel_ns;
1151
8cfdc000 1152 /* With all the info we got, fill in the values */
1d5f066e 1153 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1154 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1d5f066e 1155 vcpu->last_kernel_ns = kernel_ns;
28e4639a 1156 vcpu->last_guest_tsc = tsc_timestamp;
371bcf64
GC		 1157 vcpu->hv_clock.flags = 0;
1158
18068523
GOC		 1159 /*
1160 * The interface expects us to write an even number signaling that the
1161 * update is finished. Since the guest won't see the intermediate
50d0a0f9 1162 * state, we just increase by 2 at the end.
18068523 1163 */
50d0a0f9 1164 vcpu->hv_clock.version += 2;
18068523
GOC		 1165
1166 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
1167
1168 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
50d0a0f9 1169 sizeof(vcpu->hv_clock));
18068523
GOC		 1170
1171 kunmap_atomic(shared_kaddr, KM_USER0);
1172
1173 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
8cfdc000 1174 return 0;
c8076604
GH		 1175}
1176
9ba075a6
AK		 1177static bool msr_mtrr_valid(unsigned msr)
1178{
1179 switch (msr) {
1180 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1181 case MSR_MTRRfix64K_00000:
1182 case MSR_MTRRfix16K_80000:
1183 case MSR_MTRRfix16K_A0000:
1184 case MSR_MTRRfix4K_C0000:
1185 case MSR_MTRRfix4K_C8000:
1186 case MSR_MTRRfix4K_D0000:
1187 case MSR_MTRRfix4K_D8000:
1188 case MSR_MTRRfix4K_E0000:
1189 case MSR_MTRRfix4K_E8000:
1190 case MSR_MTRRfix4K_F0000:
1191 case MSR_MTRRfix4K_F8000:
1192 case MSR_MTRRdefType:
1193 case MSR_IA32_CR_PAT:
1194 return true;
1195 case 0x2f8:
1196 return true;
1197 }
1198 return false;
1199}
1200
d6289b93
MT		 1201static bool valid_pat_type(unsigned t)
1202{
1203 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1204}
1205
1206static bool valid_mtrr_type(unsigned t)
1207{
1208 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1209}
1210
1211static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1212{
1213 int i;
1214
1215 if (!msr_mtrr_valid(msr))
1216 return false;
1217
1218 if (msr == MSR_IA32_CR_PAT) {
1219 for (i = 0; i < 8; i++)
1220 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1221 return false;
1222 return true;
1223 } else if (msr == MSR_MTRRdefType) {
1224 if (data & ~0xcff)
1225 return false;
1226 return valid_mtrr_type(data & 0xff);
1227 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1228 for (i = 0; i < 8 ; i++)
1229 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1230 return false;
1231 return true;
1232 }
1233
1234 /* variable MTRRs */
1235 return valid_mtrr_type(data & 0xff);
1236}
1237
9ba075a6
AK		 1238static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1239{
0bed3b56
SY		 1240 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1241
d6289b93 1242 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 1243 return 1;
1244
0bed3b56
SY		 1245 if (msr == MSR_MTRRdefType) {
1246 vcpu->arch.mtrr_state.def_type = data;
1247 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1248 } else if (msr == MSR_MTRRfix64K_00000)
1249 p[0] = data;
1250 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1251 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1252 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1253 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1254 else if (msr == MSR_IA32_CR_PAT)
1255 vcpu->arch.pat = data;
1256 else { /* Variable MTRRs */
1257 int idx, is_mtrr_mask;
1258 u64 *pt;
1259
1260 idx = (msr - 0x200) / 2;
1261 is_mtrr_mask = msr - 0x200 - 2 * idx;
1262 if (!is_mtrr_mask)
1263 pt =
1264 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1265 else
1266 pt =
1267 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1268 *pt = data;
1269 }
1270
1271 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 1272 return 0;
1273}
15c4a640 1274
890ca9ae 1275static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1276{
890ca9ae
HY		 1277 u64 mcg_cap = vcpu->arch.mcg_cap;
1278 unsigned bank_num = mcg_cap & 0xff;
1279
15c4a640 1280 switch (msr) {
15c4a640 1281 case MSR_IA32_MCG_STATUS:
890ca9ae 1282 vcpu->arch.mcg_status = data;
15c4a640 1283 break;
c7ac679c 1284 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1285 if (!(mcg_cap & MCG_CTL_P))
1286 return 1;
1287 if (data != 0 && data != ~(u64)0)
1288 return -1;
1289 vcpu->arch.mcg_ctl = data;
1290 break;
1291 default:
1292 if (msr >= MSR_IA32_MC0_CTL &&
1293 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1294 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1295 /* only 0 or all 1s can be written to IA32_MCi_CTL
1296 * some Linux kernels though clear bit 10 in bank 4 to
1297 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1298 * this to avoid an uncatched #GP in the guest
1299 */
890ca9ae 1300 if ((offset & 0x3) == 0 &&
114be429 1301 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1302 return -1;
1303 vcpu->arch.mce_banks[offset] = data;
1304 break;
1305 }
1306 return 1;
1307 }
1308 return 0;
1309}
1310
ffde22ac
ES		 1311static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1312{
1313 struct kvm *kvm = vcpu->kvm;
1314 int lm = is_long_mode(vcpu);
1315 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1316 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1317 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1318 : kvm->arch.xen_hvm_config.blob_size_32;
1319 u32 page_num = data & ~PAGE_MASK;
1320 u64 page_addr = data & PAGE_MASK;
1321 u8 *page;
1322 int r;
1323
1324 r = -E2BIG;
1325 if (page_num >= blob_size)
1326 goto out;
1327 r = -ENOMEM;
1328 page = kzalloc(PAGE_SIZE, GFP_KERNEL);
1329 if (!page)
1330 goto out;
1331 r = -EFAULT;
1332 if (copy_from_user(page, blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE))
1333 goto out_free;
1334 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1335 goto out_free;
1336 r = 0;
1337out_free:
1338 kfree(page);
1339out:
1340 return r;
1341}
1342
55cd8e5a
GN		 1343static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1344{
1345 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1346}
1347
1348static bool kvm_hv_msr_partition_wide(u32 msr)
1349{
1350 bool r = false;
1351 switch (msr) {
1352 case HV_X64_MSR_GUEST_OS_ID:
1353 case HV_X64_MSR_HYPERCALL:
1354 r = true;
1355 break;
1356 }
1357
1358 return r;
1359}
1360
1361static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1362{
1363 struct kvm *kvm = vcpu->kvm;
1364
1365 switch (msr) {
1366 case HV_X64_MSR_GUEST_OS_ID:
1367 kvm->arch.hv_guest_os_id = data;
1368 /* setting guest os id to zero disables hypercall page */
1369 if (!kvm->arch.hv_guest_os_id)
1370 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1371 break;
1372 case HV_X64_MSR_HYPERCALL: {
1373 u64 gfn;
1374 unsigned long addr;
1375 u8 instructions[4];
1376
1377 /* if guest os id is not set hypercall should remain disabled */
1378 if (!kvm->arch.hv_guest_os_id)
1379 break;
1380 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1381 kvm->arch.hv_hypercall = data;
1382 break;
1383 }
1384 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1385 addr = gfn_to_hva(kvm, gfn);
1386 if (kvm_is_error_hva(addr))
1387 return 1;
1388 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1389 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
8b0cedff 1390 if (__copy_to_user((void __user *)addr, instructions, 4))
55cd8e5a
GN		 1391 return 1;
1392 kvm->arch.hv_hypercall = data;
1393 break;
1394 }
1395 default:
1396 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1397 "data 0x%llx\n", msr, data);
1398 return 1;
1399 }
1400 return 0;
1401}
1402
1403static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1404{
10388a07
GN		 1405 switch (msr) {
1406 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1407 unsigned long addr;
55cd8e5a 1408
10388a07
GN		 1409 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1410 vcpu->arch.hv_vapic = data;
1411 break;
1412 }
1413 addr = gfn_to_hva(vcpu->kvm, data >>
1414 HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1415 if (kvm_is_error_hva(addr))
1416 return 1;
8b0cedff 1417 if (__clear_user((void __user *)addr, PAGE_SIZE))
10388a07
GN		 1418 return 1;
1419 vcpu->arch.hv_vapic = data;
1420 break;
1421 }
1422 case HV_X64_MSR_EOI:
1423 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1424 case HV_X64_MSR_ICR:
1425 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1426 case HV_X64_MSR_TPR:
1427 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1428 default:
1429 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1430 "data 0x%llx\n", msr, data);
1431 return 1;
1432 }
1433
1434 return 0;
55cd8e5a
GN		 1435}
1436
344d9588
GN		 1437static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1438{
1439 gpa_t gpa = data & ~0x3f;
1440
6adba527
GN		 1441 /* Bits 2:5 are resrved, Should be zero */
1442 if (data & 0x3c)
344d9588
GN		 1443 return 1;
1444
1445 vcpu->arch.apf.msr_val = data;
1446
1447 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1448 kvm_clear_async_pf_completion_queue(vcpu);
1449 kvm_async_pf_hash_reset(vcpu);
1450 return 0;
1451 }
1452
1453 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa))
1454 return 1;
1455
6adba527 1456 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 1457 kvm_async_pf_wakeup_all(vcpu);
1458 return 0;
1459}
1460
12f9a48f
GC		 1461static void kvmclock_reset(struct kvm_vcpu *vcpu)
1462{
1463 if (vcpu->arch.time_page) {
1464 kvm_release_page_dirty(vcpu->arch.time_page);
1465 vcpu->arch.time_page = NULL;
1466 }
1467}
1468
15c4a640
CO		 1469int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1470{
1471 switch (msr) {
15c4a640 1472 case MSR_EFER:
b69e8cae 1473 return set_efer(vcpu, data);
8f1589d9
AP		 1474 case MSR_K7_HWCR:
1475 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 1476 data &= ~(u64)0x100; /* ignore ignne emulation enable */
8f1589d9
AP		 1477 if (data != 0) {
1478 pr_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1479 data);
1480 return 1;
1481 }
15c4a640 1482 break;
f7c6d140
AP		 1483 case MSR_FAM10H_MMIO_CONF_BASE:
1484 if (data != 0) {
1485 pr_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1486 "0x%llx\n", data);
1487 return 1;
1488 }
15c4a640 1489 break;
c323c0e5 1490 case MSR_AMD64_NB_CFG:
c7ac679c 1491 break;
b5e2fec0
AG		 1492 case MSR_IA32_DEBUGCTLMSR:
1493 if (!data) {
1494 /* We support the non-activated case already */
1495 break;
1496 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1497 /* Values other than LBR and BTF are vendor-specific,
1498 thus reserved and should throw a #GP */
1499 return 1;
1500 }
1501 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1502 __func__, data);
1503 break;
15c4a640
CO		 1504 case MSR_IA32_UCODE_REV:
1505 case MSR_IA32_UCODE_WRITE:
61a6bd67 1506 case MSR_VM_HSAVE_PA:
6098ca93 1507 case MSR_AMD64_PATCH_LOADER:
15c4a640 1508 break;
9ba075a6
AK		 1509 case 0x200 ... 0x2ff:
1510 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 1511 case MSR_IA32_APICBASE:
1512 kvm_set_apic_base(vcpu, data);
1513 break;
0105d1a5
GN		 1514 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1515 return kvm_x2apic_msr_write(vcpu, msr, data);
15c4a640 1516 case MSR_IA32_MISC_ENABLE:
ad312c7c 1517 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 1518 break;
11c6bffa 1519 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1520 case MSR_KVM_WALL_CLOCK:
1521 vcpu->kvm->arch.wall_clock = data;
1522 kvm_write_wall_clock(vcpu->kvm, data);
1523 break;
11c6bffa 1524 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 1525 case MSR_KVM_SYSTEM_TIME: {
12f9a48f 1526 kvmclock_reset(vcpu);
18068523
GOC		 1527
1528 vcpu->arch.time = data;
c285545f 1529 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
18068523
GOC		 1530
1531 /* we verify if the enable bit is set... */
1532 if (!(data & 1))
1533 break;
1534
1535 /* ...but clean it before doing the actual write */
1536 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
1537
18068523
GOC		 1538 vcpu->arch.time_page =
1539 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
18068523
GOC		 1540
1541 if (is_error_page(vcpu->arch.time_page)) {
1542 kvm_release_page_clean(vcpu->arch.time_page);
1543 vcpu->arch.time_page = NULL;
1544 }
18068523
GOC		 1545 break;
1546 }
344d9588
GN		 1547 case MSR_KVM_ASYNC_PF_EN:
1548 if (kvm_pv_enable_async_pf(vcpu, data))
1549 return 1;
1550 break;
890ca9ae
HY		 1551 case MSR_IA32_MCG_CTL:
1552 case MSR_IA32_MCG_STATUS:
1553 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1554 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 1555
1556 /* Performance counters are not protected by a CPUID bit,
1557 * so we should check all of them in the generic path for the sake of
1558 * cross vendor migration.
1559 * Writing a zero into the event select MSRs disables them,
1560 * which we perfectly emulate ;-). Any other value should be at least
1561 * reported, some guests depend on them.
1562 */
1563 case MSR_P6_EVNTSEL0:
1564 case MSR_P6_EVNTSEL1:
1565 case MSR_K7_EVNTSEL0:
1566 case MSR_K7_EVNTSEL1:
1567 case MSR_K7_EVNTSEL2:
1568 case MSR_K7_EVNTSEL3:
1569 if (data != 0)
1570 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1571 "0x%x data 0x%llx\n", msr, data);
1572 break;
1573 /* at least RHEL 4 unconditionally writes to the perfctr registers,
1574 * so we ignore writes to make it happy.
1575 */
1576 case MSR_P6_PERFCTR0:
1577 case MSR_P6_PERFCTR1:
1578 case MSR_K7_PERFCTR0:
1579 case MSR_K7_PERFCTR1:
1580 case MSR_K7_PERFCTR2:
1581 case MSR_K7_PERFCTR3:
1582 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1583 "0x%x data 0x%llx\n", msr, data);
1584 break;
84e0cefa
JS		 1585 case MSR_K7_CLK_CTL:
1586 /*
1587 * Ignore all writes to this no longer documented MSR.
1588 * Writes are only relevant for old K7 processors,
1589 * all pre-dating SVM, but a recommended workaround from
1590 * AMD for these chips. It is possible to speicify the
1591 * affected processor models on the command line, hence
1592 * the need to ignore the workaround.
1593 */
1594 break;
55cd8e5a
GN		 1595 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1596 if (kvm_hv_msr_partition_wide(msr)) {
1597 int r;
1598 mutex_lock(&vcpu->kvm->lock);
1599 r = set_msr_hyperv_pw(vcpu, msr, data);
1600 mutex_unlock(&vcpu->kvm->lock);
1601 return r;
1602 } else
1603 return set_msr_hyperv(vcpu, msr, data);
1604 break;
91c9c3ed 1605 case MSR_IA32_BBL_CR_CTL3:
1606 /* Drop writes to this legacy MSR -- see rdmsr
1607 * counterpart for further detail.
1608 */
1609 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
1610 break;
15c4a640 1611 default:
ffde22ac
ES		 1612 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
1613 return xen_hvm_config(vcpu, data);
ed85c068
AP		 1614 if (!ignore_msrs) {
1615 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
1616 msr, data);
1617 return 1;
1618 } else {
1619 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
1620 msr, data);
1621 break;
1622 }
15c4a640
CO		 1623 }
1624 return 0;
1625}
1626EXPORT_SYMBOL_GPL(kvm_set_msr_common);
1627
1628
1629/*
1630 * Reads an msr value (of 'msr_index') into 'pdata'.
1631 * Returns 0 on success, non-0 otherwise.
1632 * Assumes vcpu_load() was already called.
1633 */
1634int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1635{
1636 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
1637}
1638
9ba075a6
AK		 1639static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1640{
0bed3b56
SY		 1641 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1642
9ba075a6
AK		 1643 if (!msr_mtrr_valid(msr))
1644 return 1;
1645
0bed3b56
SY		 1646 if (msr == MSR_MTRRdefType)
1647 *pdata = vcpu->arch.mtrr_state.def_type +
1648 (vcpu->arch.mtrr_state.enabled << 10);
1649 else if (msr == MSR_MTRRfix64K_00000)
1650 *pdata = p[0];
1651 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1652 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
1653 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1654 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
1655 else if (msr == MSR_IA32_CR_PAT)
1656 *pdata = vcpu->arch.pat;
1657 else { /* Variable MTRRs */
1658 int idx, is_mtrr_mask;
1659 u64 *pt;
1660
1661 idx = (msr - 0x200) / 2;
1662 is_mtrr_mask = msr - 0x200 - 2 * idx;
1663 if (!is_mtrr_mask)
1664 pt =
1665 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1666 else
1667 pt =
1668 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1669 *pdata = *pt;
1670 }
1671
9ba075a6
AK		 1672 return 0;
1673}
1674
890ca9ae 1675static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 1676{
1677 u64 data;
890ca9ae
HY		 1678 u64 mcg_cap = vcpu->arch.mcg_cap;
1679 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 1680
1681 switch (msr) {
15c4a640
CO		 1682 case MSR_IA32_P5_MC_ADDR:
1683 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 1684 data = 0;
1685 break;
15c4a640 1686 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 1687 data = vcpu->arch.mcg_cap;
1688 break;
c7ac679c 1689 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1690 if (!(mcg_cap & MCG_CTL_P))
1691 return 1;
1692 data = vcpu->arch.mcg_ctl;
1693 break;
1694 case MSR_IA32_MCG_STATUS:
1695 data = vcpu->arch.mcg_status;
1696 break;
1697 default:
1698 if (msr >= MSR_IA32_MC0_CTL &&
1699 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1700 u32 offset = msr - MSR_IA32_MC0_CTL;
1701 data = vcpu->arch.mce_banks[offset];
1702 break;
1703 }
1704 return 1;
1705 }
1706 *pdata = data;
1707 return 0;
1708}
1709
55cd8e5a
GN		 1710static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1711{
1712 u64 data = 0;
1713 struct kvm *kvm = vcpu->kvm;
1714
1715 switch (msr) {
1716 case HV_X64_MSR_GUEST_OS_ID:
1717 data = kvm->arch.hv_guest_os_id;
1718 break;
1719 case HV_X64_MSR_HYPERCALL:
1720 data = kvm->arch.hv_hypercall;
1721 break;
1722 default:
1723 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1724 return 1;
1725 }
1726
1727 *pdata = data;
1728 return 0;
1729}
1730
1731static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1732{
1733 u64 data = 0;
1734
1735 switch (msr) {
1736 case HV_X64_MSR_VP_INDEX: {
1737 int r;
1738 struct kvm_vcpu *v;
1739 kvm_for_each_vcpu(r, v, vcpu->kvm)
1740 if (v == vcpu)
1741 data = r;
1742 break;
1743 }
10388a07
GN		 1744 case HV_X64_MSR_EOI:
1745 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
1746 case HV_X64_MSR_ICR:
1747 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
1748 case HV_X64_MSR_TPR:
1749 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
55cd8e5a
GN		 1750 default:
1751 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1752 return 1;
1753 }
1754 *pdata = data;
1755 return 0;
1756}
1757
890ca9ae
HY		 1758int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1759{
1760 u64 data;
1761
1762 switch (msr) {
890ca9ae 1763 case MSR_IA32_PLATFORM_ID:
15c4a640 1764 case MSR_IA32_UCODE_REV:
15c4a640 1765 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 1766 case MSR_IA32_DEBUGCTLMSR:
1767 case MSR_IA32_LASTBRANCHFROMIP:
1768 case MSR_IA32_LASTBRANCHTOIP:
1769 case MSR_IA32_LASTINTFROMIP:
1770 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 1771 case MSR_K8_SYSCFG:
1772 case MSR_K7_HWCR:
61a6bd67 1773 case MSR_VM_HSAVE_PA:
1f3ee616
AS		 1774 case MSR_P6_PERFCTR0:
1775 case MSR_P6_PERFCTR1:
7fe29e0f
AS		 1776 case MSR_P6_EVNTSEL0:
1777 case MSR_P6_EVNTSEL1:
9e699624 1778 case MSR_K7_EVNTSEL0:
1f3ee616 1779 case MSR_K7_PERFCTR0:
1fdbd48c 1780 case MSR_K8_INT_PENDING_MSG:
c323c0e5 1781 case MSR_AMD64_NB_CFG:
f7c6d140 1782 case MSR_FAM10H_MMIO_CONF_BASE:
15c4a640
CO		 1783 data = 0;
1784 break;
9ba075a6
AK		 1785 case MSR_MTRRcap:
1786 data = 0x500 | KVM_NR_VAR_MTRR;
1787 break;
1788 case 0x200 ... 0x2ff:
1789 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 1790 case 0xcd: /* fsb frequency */
1791 data = 3;
1792 break;
7b914098
JS		 1793 /*
1794 * MSR_EBC_FREQUENCY_ID
1795 * Conservative value valid for even the basic CPU models.
1796 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
1797 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
1798 * and 266MHz for model 3, or 4. Set Core Clock
1799 * Frequency to System Bus Frequency Ratio to 1 (bits
1800 * 31:24) even though these are only valid for CPU
1801 * models > 2, however guests may end up dividing or
1802 * multiplying by zero otherwise.
1803 */
1804 case MSR_EBC_FREQUENCY_ID:
1805 data = 1 << 24;
1806 break;
15c4a640
CO		 1807 case MSR_IA32_APICBASE:
1808 data = kvm_get_apic_base(vcpu);
1809 break;
0105d1a5
GN		 1810 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1811 return kvm_x2apic_msr_read(vcpu, msr, pdata);
1812 break;
15c4a640 1813 case MSR_IA32_MISC_ENABLE:
ad312c7c 1814 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 1815 break;
847f0ad8
AG		 1816 case MSR_IA32_PERF_STATUS:
1817 /* TSC increment by tick */
1818 data = 1000ULL;
1819 /* CPU multiplier */
1820 data |= (((uint64_t)4ULL) << 40);
1821 break;
15c4a640 1822 case MSR_EFER:
f6801dff 1823 data = vcpu->arch.efer;
15c4a640 1824 break;
18068523 1825 case MSR_KVM_WALL_CLOCK:
11c6bffa 1826 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1827 data = vcpu->kvm->arch.wall_clock;
1828 break;
1829 case MSR_KVM_SYSTEM_TIME:
11c6bffa 1830 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 1831 data = vcpu->arch.time;
1832 break;
344d9588
GN		 1833 case MSR_KVM_ASYNC_PF_EN:
1834 data = vcpu->arch.apf.msr_val;
1835 break;
890ca9ae
HY		 1836 case MSR_IA32_P5_MC_ADDR:
1837 case MSR_IA32_P5_MC_TYPE:
1838 case MSR_IA32_MCG_CAP:
1839 case MSR_IA32_MCG_CTL:
1840 case MSR_IA32_MCG_STATUS:
1841 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1842 return get_msr_mce(vcpu, msr, pdata);
84e0cefa
JS		 1843 case MSR_K7_CLK_CTL:
1844 /*
1845 * Provide expected ramp-up count for K7. All other
1846 * are set to zero, indicating minimum divisors for
1847 * every field.
1848 *
1849 * This prevents guest kernels on AMD host with CPU
1850 * type 6, model 8 and higher from exploding due to
1851 * the rdmsr failing.
1852 */
1853 data = 0x20000000;
1854 break;
55cd8e5a
GN		 1855 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1856 if (kvm_hv_msr_partition_wide(msr)) {
1857 int r;
1858 mutex_lock(&vcpu->kvm->lock);
1859 r = get_msr_hyperv_pw(vcpu, msr, pdata);
1860 mutex_unlock(&vcpu->kvm->lock);
1861 return r;
1862 } else
1863 return get_msr_hyperv(vcpu, msr, pdata);
1864 break;
91c9c3ed 1865 case MSR_IA32_BBL_CR_CTL3:
1866 /* This legacy MSR exists but isn't fully documented in current
1867 * silicon. It is however accessed by winxp in very narrow
1868 * scenarios where it sets bit #19, itself documented as
1869 * a "reserved" bit. Best effort attempt to source coherent
1870 * read data here should the balance of the register be
1871 * interpreted by the guest:
1872 *
1873 * L2 cache control register 3: 64GB range, 256KB size,
1874 * enabled, latency 0x1, configured
1875 */
1876 data = 0xbe702111;
1877 break;
15c4a640 1878 default:
ed85c068
AP		 1879 if (!ignore_msrs) {
1880 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
1881 return 1;
1882 } else {
1883 pr_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
1884 data = 0;
1885 }
1886 break;
15c4a640
CO		 1887 }
1888 *pdata = data;
1889 return 0;
1890}
1891EXPORT_SYMBOL_GPL(kvm_get_msr_common);
1892
313a3dc7
CO		 1893/*
1894 * Read or write a bunch of msrs. All parameters are kernel addresses.
1895 *
1896 * @return number of msrs set successfully.
1897 */
1898static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
1899 struct kvm_msr_entry *entries,
1900 int (*do_msr)(struct kvm_vcpu *vcpu,
1901 unsigned index, u64 *data))
1902{
f656ce01 1903 int i, idx;
313a3dc7 1904
f656ce01 1905 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 1906 for (i = 0; i < msrs->nmsrs; ++i)
1907 if (do_msr(vcpu, entries[i].index, &entries[i].data))
1908 break;
f656ce01 1909 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 1910
313a3dc7
CO		 1911 return i;
1912}
1913
1914/*
1915 * Read or write a bunch of msrs. Parameters are user addresses.
1916 *
1917 * @return number of msrs set successfully.
1918 */
1919static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
1920 int (*do_msr)(struct kvm_vcpu *vcpu,
1921 unsigned index, u64 *data),
1922 int writeback)
1923{
1924 struct kvm_msrs msrs;
1925 struct kvm_msr_entry *entries;
1926 int r, n;
1927 unsigned size;
1928
1929 r = -EFAULT;
1930 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
1931 goto out;
1932
1933 r = -E2BIG;
1934 if (msrs.nmsrs >= MAX_IO_MSRS)
1935 goto out;
1936
1937 r = -ENOMEM;
1938 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
7a73c028 1939 entries = kmalloc(size, GFP_KERNEL);
313a3dc7
CO		 1940 if (!entries)
1941 goto out;
1942
1943 r = -EFAULT;
1944 if (copy_from_user(entries, user_msrs->entries, size))
1945 goto out_free;
1946
1947 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
1948 if (r < 0)
1949 goto out_free;
1950
1951 r = -EFAULT;
1952 if (writeback && copy_to_user(user_msrs->entries, entries, size))
1953 goto out_free;
1954
1955 r = n;
1956
1957out_free:
7a73c028 1958 kfree(entries);
313a3dc7
CO		 1959out:
1960 return r;
1961}
1962
018d00d2
ZX		 1963int kvm_dev_ioctl_check_extension(long ext)
1964{
1965 int r;
1966
1967 switch (ext) {
1968 case KVM_CAP_IRQCHIP:
1969 case KVM_CAP_HLT:
1970 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 1971 case KVM_CAP_SET_TSS_ADDR:
07716717 1972 case KVM_CAP_EXT_CPUID:
c8076604 1973 case KVM_CAP_CLOCKSOURCE:
7837699f 1974 case KVM_CAP_PIT:
a28e4f5a 1975 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 1976 case KVM_CAP_MP_STATE:
ed848624 1977 case KVM_CAP_SYNC_MMU:
a355c85c 1978 case KVM_CAP_USER_NMI:
52d939a0 1979 case KVM_CAP_REINJECT_CONTROL:
4925663a 1980 case KVM_CAP_IRQ_INJECT_STATUS:
e56d532f 1981 case KVM_CAP_ASSIGN_DEV_IRQ:
721eecbf 1982 case KVM_CAP_IRQFD:
d34e6b17 1983 case KVM_CAP_IOEVENTFD:
c5ff41ce 1984 case KVM_CAP_PIT2:
e9f42757 1985 case KVM_CAP_PIT_STATE2:
b927a3ce 1986 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 1987 case KVM_CAP_XEN_HVM:
afbcf7ab 1988 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 1989 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 1990 case KVM_CAP_HYPERV:
10388a07 1991 case KVM_CAP_HYPERV_VAPIC:
c25bc163 1992 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 1993 case KVM_CAP_PCI_SEGMENT:
a1efbe77 1994 case KVM_CAP_DEBUGREGS:
d2be1651 1995 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 1996 case KVM_CAP_XSAVE:
344d9588 1997 case KVM_CAP_ASYNC_PF:
92a1f12d 1998 case KVM_CAP_GET_TSC_KHZ:
018d00d2
ZX		 1999 r = 1;
2000 break;
542472b5
LV		 2001 case KVM_CAP_COALESCED_MMIO:
2002 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2003 break;
774ead3a
AK		 2004 case KVM_CAP_VAPIC:
2005 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2006 break;
f725230a
AK		 2007 case KVM_CAP_NR_VCPUS:
2008 r = KVM_MAX_VCPUS;
2009 break;
a988b910
AK		 2010 case KVM_CAP_NR_MEMSLOTS:
2011 r = KVM_MEMORY_SLOTS;
2012 break;
a68a6a72
MT		 2013 case KVM_CAP_PV_MMU: /* obsolete */
2014 r = 0;
2f333bcb 2015 break;
62c476c7 2016 case KVM_CAP_IOMMU:
19de40a8 2017 r = iommu_found();
62c476c7 2018 break;
890ca9ae
HY		 2019 case KVM_CAP_MCE:
2020 r = KVM_MAX_MCE_BANKS;
2021 break;
2d5b5a66
SY		 2022 case KVM_CAP_XCRS:
2023 r = cpu_has_xsave;
2024 break;
92a1f12d
JR		 2025 case KVM_CAP_TSC_CONTROL:
2026 r = kvm_has_tsc_control;
2027 break;
018d00d2
ZX		 2028 default:
2029 r = 0;
2030 break;
2031 }
2032 return r;
2033
2034}
2035
043405e1
CO		 2036long kvm_arch_dev_ioctl(struct file *filp,
2037 unsigned int ioctl, unsigned long arg)
2038{
2039 void __user *argp = (void __user *)arg;
2040 long r;
2041
2042 switch (ioctl) {
2043 case KVM_GET_MSR_INDEX_LIST: {
2044 struct kvm_msr_list __user *user_msr_list = argp;
2045 struct kvm_msr_list msr_list;
2046 unsigned n;
2047
2048 r = -EFAULT;
2049 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2050 goto out;
2051 n = msr_list.nmsrs;
2052 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2053 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2054 goto out;
2055 r = -E2BIG;
e125e7b6 2056 if (n < msr_list.nmsrs)
043405e1
CO		 2057 goto out;
2058 r = -EFAULT;
2059 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2060 num_msrs_to_save * sizeof(u32)))
2061 goto out;
e125e7b6 2062 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 2063 &emulated_msrs,
2064 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2065 goto out;
2066 r = 0;
2067 break;
2068 }
674eea0f
AK		 2069 case KVM_GET_SUPPORTED_CPUID: {
2070 struct kvm_cpuid2 __user *cpuid_arg = argp;
2071 struct kvm_cpuid2 cpuid;
2072
2073 r = -EFAULT;
2074 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2075 goto out;
2076 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
19355475 2077 cpuid_arg->entries);
674eea0f
AK		 2078 if (r)
2079 goto out;
2080
2081 r = -EFAULT;
2082 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2083 goto out;
2084 r = 0;
2085 break;
2086 }
890ca9ae
HY		 2087 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2088 u64 mce_cap;
2089
2090 mce_cap = KVM_MCE_CAP_SUPPORTED;
2091 r = -EFAULT;
2092 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2093 goto out;
2094 r = 0;
2095 break;
2096 }
043405e1
CO		 2097 default:
2098 r = -EINVAL;
2099 }
2100out:
2101 return r;
2102}
2103
f5f48ee1
SY		 2104static void wbinvd_ipi(void *garbage)
2105{
2106 wbinvd();
2107}
2108
2109static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2110{
2111 return vcpu->kvm->arch.iommu_domain &&
2112 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY);
2113}
2114
313a3dc7
CO		 2115void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2116{
f5f48ee1
SY		 2117 /* Address WBINVD may be executed by guest */
2118 if (need_emulate_wbinvd(vcpu)) {
2119 if (kvm_x86_ops->has_wbinvd_exit())
2120 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2121 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2122 smp_call_function_single(vcpu->cpu,
2123 wbinvd_ipi, NULL, 1);
2124 }
2125
313a3dc7 2126 kvm_x86_ops->vcpu_load(vcpu, cpu);
48434c20 2127 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
e48672fa 2128 /* Make sure TSC doesn't go backwards */
8f6055cb
JR		 2129 s64 tsc_delta;
2130 u64 tsc;
2131
2132 kvm_get_msr(vcpu, MSR_IA32_TSC, &tsc);
2133 tsc_delta = !vcpu->arch.last_guest_tsc ? 0 :
2134 tsc - vcpu->arch.last_guest_tsc;
2135
e48672fa
ZA		 2136 if (tsc_delta < 0)
2137 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 2138 if (check_tsc_unstable()) {
e48672fa 2139 kvm_x86_ops->adjust_tsc_offset(vcpu, -tsc_delta);
c285545f 2140 vcpu->arch.tsc_catchup = 1;
c285545f 2141 }
1aa8ceef 2142 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c285545f
ZA		 2143 if (vcpu->cpu != cpu)
2144 kvm_migrate_timers(vcpu);
e48672fa 2145 vcpu->cpu = cpu;
6b7d7e76 2146 }
313a3dc7
CO		 2147}
2148
2149void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2150{
02daab21 2151 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2152 kvm_put_guest_fpu(vcpu);
7c4c0f4f 2153 kvm_get_msr(vcpu, MSR_IA32_TSC, &vcpu->arch.last_guest_tsc);
313a3dc7
CO		 2154}
2155
07716717 2156static int is_efer_nx(void)
313a3dc7 2157{
e286e86e 2158 unsigned long long efer = 0;
313a3dc7 2159
e286e86e 2160 rdmsrl_safe(MSR_EFER, &efer);
07716717
DK		 2161 return efer & EFER_NX;
2162}
2163
2164static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
2165{
2166 int i;
2167 struct kvm_cpuid_entry2 *e, *entry;
2168
313a3dc7 2169 entry = NULL;
ad312c7c
ZX		 2170 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
2171 e = &vcpu->arch.cpuid_entries[i];
313a3dc7
CO		 2172 if (e->function == 0x80000001) {
2173 entry = e;
2174 break;
2175 }
2176 }
07716717 2177 if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) {
313a3dc7
CO		 2178 entry->edx &= ~(1 << 20);
2179 printk(KERN_INFO "kvm: guest NX capability removed\n");
2180 }
2181}
2182
07716717 2183/* when an old userspace process fills a new kernel module */
313a3dc7
CO		 2184static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
2185 struct kvm_cpuid *cpuid,
2186 struct kvm_cpuid_entry __user *entries)
07716717
DK		 2187{
2188 int r, i;
2189 struct kvm_cpuid_entry *cpuid_entries;
2190
2191 r = -E2BIG;
2192 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2193 goto out;
2194 r = -ENOMEM;
2195 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent);
2196 if (!cpuid_entries)
2197 goto out;
2198 r = -EFAULT;
2199 if (copy_from_user(cpuid_entries, entries,
2200 cpuid->nent * sizeof(struct kvm_cpuid_entry)))
2201 goto out_free;
2202 for (i = 0; i < cpuid->nent; i++) {
ad312c7c
ZX		 2203 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
2204 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
2205 vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx;
2206 vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx;
2207 vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx;
2208 vcpu->arch.cpuid_entries[i].index = 0;
2209 vcpu->arch.cpuid_entries[i].flags = 0;
2210 vcpu->arch.cpuid_entries[i].padding[0] = 0;
2211 vcpu->arch.cpuid_entries[i].padding[1] = 0;
2212 vcpu->arch.cpuid_entries[i].padding[2] = 0;
2213 }
2214 vcpu->arch.cpuid_nent = cpuid->nent;
07716717
DK		 2215 cpuid_fix_nx_cap(vcpu);
2216 r = 0;
fc61b800 2217 kvm_apic_set_version(vcpu);
0e851880 2218 kvm_x86_ops->cpuid_update(vcpu);
2acf923e 2219 update_cpuid(vcpu);
07716717
DK		 2220
2221out_free:
2222 vfree(cpuid_entries);
2223out:
2224 return r;
2225}
2226
2227static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 2228 struct kvm_cpuid2 *cpuid,
2229 struct kvm_cpuid_entry2 __user *entries)
313a3dc7
CO		 2230{
2231 int r;
2232
2233 r = -E2BIG;
2234 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2235 goto out;
2236 r = -EFAULT;
ad312c7c 2237 if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
07716717 2238 cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
313a3dc7 2239 goto out;
ad312c7c 2240 vcpu->arch.cpuid_nent = cpuid->nent;
fc61b800 2241 kvm_apic_set_version(vcpu);
0e851880 2242 kvm_x86_ops->cpuid_update(vcpu);
2acf923e 2243 update_cpuid(vcpu);
313a3dc7
CO		 2244 return 0;
2245
2246out:
2247 return r;
2248}
2249
07716717 2250static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 2251 struct kvm_cpuid2 *cpuid,
2252 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 2253{
2254 int r;
2255
2256 r = -E2BIG;
ad312c7c 2257 if (cpuid->nent < vcpu->arch.cpuid_nent)
07716717
DK		 2258 goto out;
2259 r = -EFAULT;
ad312c7c 2260 if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
19355475 2261 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 2262 goto out;
2263 return 0;
2264
2265out:
ad312c7c 2266 cpuid->nent = vcpu->arch.cpuid_nent;
07716717
DK		 2267 return r;
2268}
2269
945ee35e
AK		 2270static void cpuid_mask(u32 *word, int wordnum)
2271{
2272 *word &= boot_cpu_data.x86_capability[wordnum];
2273}
2274
07716717 2275static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function,
19355475 2276 u32 index)
07716717
DK		 2277{
2278 entry->function = function;
2279 entry->index = index;
2280 cpuid_count(entry->function, entry->index,
19355475 2281 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
07716717
DK		 2282 entry->flags = 0;
2283}
2284
24c82e57
AK		 2285static bool supported_xcr0_bit(unsigned bit)
2286{
2287 u64 mask = ((u64)1 << bit);
2288
2289 return mask & (XSTATE_FP | XSTATE_SSE | XSTATE_YMM) & host_xcr0;
2290}
2291
7faa4ee1
AK		 2292#define F(x) bit(X86_FEATURE_##x)
2293
07716717
DK		 2294static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
2295 u32 index, int *nent, int maxnent)
2296{
7faa4ee1 2297 unsigned f_nx = is_efer_nx() ? F(NX) : 0;
07716717 2298#ifdef CONFIG_X86_64
17cc3935
SY		 2299 unsigned f_gbpages = (kvm_x86_ops->get_lpage_level() == PT_PDPE_LEVEL)
2300 ? F(GBPAGES) : 0;
7faa4ee1
AK		 2301 unsigned f_lm = F(LM);
2302#else
17cc3935 2303 unsigned f_gbpages = 0;
7faa4ee1 2304 unsigned f_lm = 0;
07716717 2305#endif
4e47c7a6 2306 unsigned f_rdtscp = kvm_x86_ops->rdtscp_supported() ? F(RDTSCP) : 0;
7faa4ee1
AK		 2307
2308 /* cpuid 1.edx */
2309 const u32 kvm_supported_word0_x86_features =
2310 F(FPU) | F(VME) | F(DE) | F(PSE) |
2311 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
2312 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) |
2313 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
2314 F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLSH) |
2315 0 /* Reserved, DS, ACPI */ | F(MMX) |
2316 F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) |
2317 0 /* HTT, TM, Reserved, PBE */;
2318 /* cpuid 0x80000001.edx */
2319 const u32 kvm_supported_word1_x86_features =
2320 F(FPU) | F(VME) | F(DE) | F(PSE) |
2321 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
2322 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) |
2323 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
2324 F(PAT) | F(PSE36) | 0 /* Reserved */ |
2325 f_nx | 0 /* Reserved */ | F(MMXEXT) | F(MMX) |
4e47c7a6 2326 F(FXSR) | F(FXSR_OPT) | f_gbpages | f_rdtscp |
7faa4ee1
AK		 2327 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW);
2328 /* cpuid 1.ecx */
2329 const u32 kvm_supported_word4_x86_features =
6c3f6041 2330 F(XMM3) | F(PCLMULQDQ) | 0 /* DTES64, MONITOR */ |
d149c731
AK		 2331 0 /* DS-CPL, VMX, SMX, EST */ |
2332 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ |
2333 0 /* Reserved */ | F(CX16) | 0 /* xTPR Update, PDCM */ |
2334 0 /* Reserved, DCA */ | F(XMM4_1) |
0105d1a5 2335 F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) |
6d886fd0
AP		 2336 0 /* Reserved*/ | F(AES) | F(XSAVE) | 0 /* OSXSAVE */ | F(AVX) |
2337 F(F16C);
7faa4ee1 2338 /* cpuid 0x80000001.ecx */
07716717 2339 const u32 kvm_supported_word6_x86_features =
4c62a2dc 2340 F(LAHF_LM) | F(CMP_LEGACY) | 0 /*SVM*/ | 0 /* ExtApicSpace */ |
7faa4ee1 2341 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) |
7ef8aa72 2342 F(3DNOWPREFETCH) | 0 /* OSVW */ | 0 /* IBS */ | F(XOP) |
6d886fd0 2343 0 /* SKINIT, WDT, LWP */ | F(FMA4) | F(TBM);
07716717 2344
4429d5dc
B		 2345 /* cpuid 0xC0000001.edx */
2346 const u32 kvm_supported_word5_x86_features =
2347 F(XSTORE) | F(XSTORE_EN) | F(XCRYPT) | F(XCRYPT_EN) |
2348 F(ACE2) | F(ACE2_EN) | F(PHE) | F(PHE_EN) |
2349 F(PMM) | F(PMM_EN);
2350
19355475 2351 /* all calls to cpuid_count() should be made on the same cpu */
07716717
DK		 2352 get_cpu();
2353 do_cpuid_1_ent(entry, function, index);
2354 ++*nent;
2355
2356 switch (function) {
2357 case 0:
2acf923e 2358 entry->eax = min(entry->eax, (u32)0xd);
07716717
DK		 2359 break;
2360 case 1:
2361 entry->edx &= kvm_supported_word0_x86_features;
945ee35e 2362 cpuid_mask(&entry->edx, 0);
7faa4ee1 2363 entry->ecx &= kvm_supported_word4_x86_features;
945ee35e 2364 cpuid_mask(&entry->ecx, 4);
0d1de2d9
GN		 2365 /* we support x2apic emulation even if host does not support
2366 * it since we emulate x2apic in software */
2367 entry->ecx |= F(X2APIC);
07716717
DK		 2368 break;
2369 /* function 2 entries are STATEFUL. That is, repeated cpuid commands
2370 * may return different values. This forces us to get_cpu() before
2371 * issuing the first command, and also to emulate this annoying behavior
2372 * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */
2373 case 2: {
2374 int t, times = entry->eax & 0xff;
2375
2376 entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
0fdf8e59 2377 entry->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
07716717
DK		 2378 for (t = 1; t < times && *nent < maxnent; ++t) {
2379 do_cpuid_1_ent(&entry[t], function, 0);
2380 entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
2381 ++*nent;
2382 }
2383 break;
2384 }
2385 /* function 4 and 0xb have additional index. */
2386 case 4: {
14af3f3c 2387 int i, cache_type;
07716717
DK		 2388
2389 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2390 /* read more entries until cache_type is zero */
14af3f3c
HH		 2391 for (i = 1; *nent < maxnent; ++i) {
2392 cache_type = entry[i - 1].eax & 0x1f;
07716717
DK		 2393 if (!cache_type)
2394 break;
14af3f3c
HH		 2395 do_cpuid_1_ent(&entry[i], function, i);
2396 entry[i].flags |=
07716717
DK		 2397 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2398 ++*nent;
2399 }
2400 break;
2401 }
24c82e57
AK		 2402 case 9:
2403 break;
07716717 2404 case 0xb: {
14af3f3c 2405 int i, level_type;
07716717
DK		 2406
2407 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2408 /* read more entries until level_type is zero */
14af3f3c 2409 for (i = 1; *nent < maxnent; ++i) {
0853d2c1 2410 level_type = entry[i - 1].ecx & 0xff00;
07716717
DK		 2411 if (!level_type)
2412 break;
14af3f3c
HH		 2413 do_cpuid_1_ent(&entry[i], function, i);
2414 entry[i].flags |=
07716717
DK		 2415 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2416 ++*nent;
2417 }
2418 break;
2419 }
2acf923e
DC		 2420 case 0xd: {
2421 int i;
2422
2423 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
20800bc9 2424 for (i = 1; *nent < maxnent && i < 64; ++i) {
24c82e57 2425 if (entry[i].eax == 0 || !supported_xcr0_bit(i))
20800bc9 2426 continue;
2acf923e
DC		 2427 do_cpuid_1_ent(&entry[i], function, i);
2428 entry[i].flags |=
2429 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2430 ++*nent;
2431 }
2432 break;
2433 }
84478c82
GC		 2434 case KVM_CPUID_SIGNATURE: {
2435 char signature[12] = "KVMKVMKVM\0\0";
2436 u32 *sigptr = (u32 *)signature;
2437 entry->eax = 0;
2438 entry->ebx = sigptr[0];
2439 entry->ecx = sigptr[1];
2440 entry->edx = sigptr[2];
2441 break;
2442 }
2443 case KVM_CPUID_FEATURES:
2444 entry->eax = (1 << KVM_FEATURE_CLOCKSOURCE) |
2445 (1 << KVM_FEATURE_NOP_IO_DELAY) |
371bcf64 2446 (1 << KVM_FEATURE_CLOCKSOURCE2) |
32918924 2447 (1 << KVM_FEATURE_ASYNC_PF) |
371bcf64 2448 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT);
84478c82
GC		 2449 entry->ebx = 0;
2450 entry->ecx = 0;
2451 entry->edx = 0;
2452 break;
07716717
DK		 2453 case 0x80000000:
2454 entry->eax = min(entry->eax, 0x8000001a);
2455 break;
2456 case 0x80000001:
2457 entry->edx &= kvm_supported_word1_x86_features;
945ee35e 2458 cpuid_mask(&entry->edx, 1);
07716717 2459 entry->ecx &= kvm_supported_word6_x86_features;
945ee35e 2460 cpuid_mask(&entry->ecx, 6);
07716717 2461 break;
24c82e57
AK		 2462 case 0x80000008: {
2463 unsigned g_phys_as = (entry->eax >> 16) & 0xff;
2464 unsigned virt_as = max((entry->eax >> 8) & 0xff, 48U);
2465 unsigned phys_as = entry->eax & 0xff;
2466
2467 if (!g_phys_as)
2468 g_phys_as = phys_as;
2469 entry->eax = g_phys_as | (virt_as << 8);
2470 entry->ebx = entry->edx = 0;
2471 break;
2472 }
2473 case 0x80000019:
2474 entry->ecx = entry->edx = 0;
2475 break;
2476 case 0x8000001a:
2477 break;
2478 case 0x8000001d:
2479 break;
4429d5dc
B		 2480 /*Add support for Centaur's CPUID instruction*/
2481 case 0xC0000000:
2482 /*Just support up to 0xC0000004 now*/
2483 entry->eax = min(entry->eax, 0xC0000004);
2484 break;
2485 case 0xC0000001:
2486 entry->edx &= kvm_supported_word5_x86_features;
2487 cpuid_mask(&entry->edx, 5);
2488 break;
24c82e57
AK		 2489 case 3: /* Processor serial number */
2490 case 5: /* MONITOR/MWAIT */
2491 case 6: /* Thermal management */
2492 case 0xA: /* Architectural Performance Monitoring */
2493 case 0x80000007: /* Advanced power management */
4429d5dc
B		 2494 case 0xC0000002:
2495 case 0xC0000003:
2496 case 0xC0000004:
24c82e57
AK		 2497 default:
2498 entry->eax = entry->ebx = entry->ecx = entry->edx = 0;
4429d5dc 2499 break;
07716717 2500 }
d4330ef2
JR		 2501
2502 kvm_x86_ops->set_supported_cpuid(function, entry);
2503
07716717
DK		 2504 put_cpu();
2505}
2506
7faa4ee1
AK		 2507#undef F
2508
674eea0f 2509static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
19355475 2510 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 2511{
2512 struct kvm_cpuid_entry2 *cpuid_entries;
2513 int limit, nent = 0, r = -E2BIG;
2514 u32 func;
2515
2516 if (cpuid->nent < 1)
2517 goto out;
6a544355
AK		 2518 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2519 cpuid->nent = KVM_MAX_CPUID_ENTRIES;
07716717
DK		 2520 r = -ENOMEM;
2521 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent);
2522 if (!cpuid_entries)
2523 goto out;
2524
2525 do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent);
2526 limit = cpuid_entries[0].eax;
2527 for (func = 1; func <= limit && nent < cpuid->nent; ++func)
2528 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 2529 &nent, cpuid->nent);
07716717
DK		 2530 r = -E2BIG;
2531 if (nent >= cpuid->nent)
2532 goto out_free;
2533
2534 do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent);
2535 limit = cpuid_entries[nent - 1].eax;
2536 for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func)
2537 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 2538 &nent, cpuid->nent);
84478c82
GC		 2539
2540
2541
2542 r = -E2BIG;
2543 if (nent >= cpuid->nent)
2544 goto out_free;
2545
4429d5dc
B		 2546 /* Add support for Centaur's CPUID instruction. */
2547 if (boot_cpu_data.x86_vendor == X86_VENDOR_CENTAUR) {
2548 do_cpuid_ent(&cpuid_entries[nent], 0xC0000000, 0,
2549 &nent, cpuid->nent);
2550
2551 r = -E2BIG;
2552 if (nent >= cpuid->nent)
2553 goto out_free;
2554
2555 limit = cpuid_entries[nent - 1].eax;
2556 for (func = 0xC0000001;
2557 func <= limit && nent < cpuid->nent; ++func)
2558 do_cpuid_ent(&cpuid_entries[nent], func, 0,
2559 &nent, cpuid->nent);
2560
2561 r = -E2BIG;
2562 if (nent >= cpuid->nent)
2563 goto out_free;
2564 }
2565
84478c82
GC		 2566 do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_SIGNATURE, 0, &nent,
2567 cpuid->nent);
2568
2569 r = -E2BIG;
2570 if (nent >= cpuid->nent)
2571 goto out_free;
2572
2573 do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_FEATURES, 0, &nent,
2574 cpuid->nent);
2575
cb007648
MM		 2576 r = -E2BIG;
2577 if (nent >= cpuid->nent)
2578 goto out_free;
2579
07716717
DK		 2580 r = -EFAULT;
2581 if (copy_to_user(entries, cpuid_entries,
19355475 2582 nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 2583 goto out_free;
2584 cpuid->nent = nent;
2585 r = 0;
2586
2587out_free:
2588 vfree(cpuid_entries);
2589out:
2590 return r;
2591}
2592
313a3dc7
CO		 2593static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2594 struct kvm_lapic_state *s)
2595{
ad312c7c 2596 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2597
2598 return 0;
2599}
2600
2601static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2602 struct kvm_lapic_state *s)
2603{
ad312c7c 2604 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
313a3dc7 2605 kvm_apic_post_state_restore(vcpu);
cb142eb7 2606 update_cr8_intercept(vcpu);
313a3dc7
CO		 2607
2608 return 0;
2609}
2610
f77bc6a4
ZX		 2611static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2612 struct kvm_interrupt *irq)
2613{
2614 if (irq->irq < 0 || irq->irq >= 256)
2615 return -EINVAL;
2616 if (irqchip_in_kernel(vcpu->kvm))
2617 return -ENXIO;
f77bc6a4 2618
66fd3f7f 2619 kvm_queue_interrupt(vcpu, irq->irq, false);
3842d135 2620 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4 2621
f77bc6a4
ZX		 2622 return 0;
2623}
2624
c4abb7c9
JK		 2625static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2626{
c4abb7c9 2627 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2628
2629 return 0;
2630}
2631
b209749f
AK		 2632static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2633 struct kvm_tpr_access_ctl *tac)
2634{
2635 if (tac->flags)
2636 return -EINVAL;
2637 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2638 return 0;
2639}
2640
890ca9ae
HY		 2641static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2642 u64 mcg_cap)
2643{
2644 int r;
2645 unsigned bank_num = mcg_cap & 0xff, bank;
2646
2647 r = -EINVAL;
a9e38c3e 2648 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2649 goto out;
2650 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2651 goto out;
2652 r = 0;
2653 vcpu->arch.mcg_cap = mcg_cap;
2654 /* Init IA32_MCG_CTL to all 1s */
2655 if (mcg_cap & MCG_CTL_P)
2656 vcpu->arch.mcg_ctl = ~(u64)0;
2657 /* Init IA32_MCi_CTL to all 1s */
2658 for (bank = 0; bank < bank_num; bank++)
2659 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2660out:
2661 return r;
2662}
2663
2664static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2665 struct kvm_x86_mce *mce)
2666{
2667 u64 mcg_cap = vcpu->arch.mcg_cap;
2668 unsigned bank_num = mcg_cap & 0xff;
2669 u64 *banks = vcpu->arch.mce_banks;
2670
2671 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2672 return -EINVAL;
2673 /*
2674 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2675 * reporting is disabled
2676 */
2677 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2678 vcpu->arch.mcg_ctl != ~(u64)0)
2679 return 0;
2680 banks += 4 * mce->bank;
2681 /*
2682 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2683 * reporting is disabled for the bank
2684 */
2685 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2686 return 0;
2687 if (mce->status & MCI_STATUS_UC) {
2688 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2689 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 2690 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2691 return 0;
2692 }
2693 if (banks[1] & MCI_STATUS_VAL)
2694 mce->status |= MCI_STATUS_OVER;
2695 banks[2] = mce->addr;
2696 banks[3] = mce->misc;
2697 vcpu->arch.mcg_status = mce->mcg_status;
2698 banks[1] = mce->status;
2699 kvm_queue_exception(vcpu, MC_VECTOR);
2700 } else if (!(banks[1] & MCI_STATUS_VAL)
2701 || !(banks[1] & MCI_STATUS_UC)) {
2702 if (banks[1] & MCI_STATUS_VAL)
2703 mce->status |= MCI_STATUS_OVER;
2704 banks[2] = mce->addr;
2705 banks[3] = mce->misc;
2706 banks[1] = mce->status;
2707 } else
2708 banks[1] |= MCI_STATUS_OVER;
2709 return 0;
2710}
2711
3cfc3092
JK		 2712static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2713 struct kvm_vcpu_events *events)
2714{
03b82a30
JK		 2715 events->exception.injected =
2716 vcpu->arch.exception.pending &&
2717 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2718 events->exception.nr = vcpu->arch.exception.nr;
2719 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 2720 events->exception.pad = 0;
3cfc3092
JK		 2721 events->exception.error_code = vcpu->arch.exception.error_code;
2722
03b82a30
JK		 2723 events->interrupt.injected =
2724 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2725 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2726 events->interrupt.soft = 0;
48005f64
JK		 2727 events->interrupt.shadow =
2728 kvm_x86_ops->get_interrupt_shadow(vcpu,
2729 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
3cfc3092
JK		 2730
2731 events->nmi.injected = vcpu->arch.nmi_injected;
2732 events->nmi.pending = vcpu->arch.nmi_pending;
2733 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 2734 events->nmi.pad = 0;
3cfc3092
JK		 2735
2736 events->sipi_vector = vcpu->arch.sipi_vector;
2737
dab4b911 2738 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2739 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2740 | KVM_VCPUEVENT_VALID_SHADOW);
97e69aa6 2741 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 2742}
2743
2744static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2745 struct kvm_vcpu_events *events)
2746{
dab4b911 2747 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2748 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2749 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 2750 return -EINVAL;
2751
3cfc3092
JK		 2752 vcpu->arch.exception.pending = events->exception.injected;
2753 vcpu->arch.exception.nr = events->exception.nr;
2754 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2755 vcpu->arch.exception.error_code = events->exception.error_code;
2756
2757 vcpu->arch.interrupt.pending = events->interrupt.injected;
2758 vcpu->arch.interrupt.nr = events->interrupt.nr;
2759 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 2760 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2761 kvm_x86_ops->set_interrupt_shadow(vcpu,
2762 events->interrupt.shadow);
3cfc3092
JK		 2763
2764 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2765 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2766 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2767 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2768
dab4b911
JK		 2769 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR)
2770 vcpu->arch.sipi_vector = events->sipi_vector;
3cfc3092 2771
3842d135
AK		 2772 kvm_make_request(KVM_REQ_EVENT, vcpu);
2773
3cfc3092
JK		 2774 return 0;
2775}
2776
a1efbe77
JK		 2777static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2778 struct kvm_debugregs *dbgregs)
2779{
a1efbe77
JK		 2780 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2781 dbgregs->dr6 = vcpu->arch.dr6;
2782 dbgregs->dr7 = vcpu->arch.dr7;
2783 dbgregs->flags = 0;
97e69aa6 2784 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 2785}
2786
2787static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2788 struct kvm_debugregs *dbgregs)
2789{
2790 if (dbgregs->flags)
2791 return -EINVAL;
2792
a1efbe77
JK		 2793 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2794 vcpu->arch.dr6 = dbgregs->dr6;
2795 vcpu->arch.dr7 = dbgregs->dr7;
2796
a1efbe77
JK		 2797 return 0;
2798}
2799
2d5b5a66
SY		 2800static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
2801 struct kvm_xsave *guest_xsave)
2802{
2803 if (cpu_has_xsave)
2804 memcpy(guest_xsave->region,
2805 &vcpu->arch.guest_fpu.state->xsave,
f45755b8 2806 xstate_size);
2d5b5a66
SY		 2807 else {
2808 memcpy(guest_xsave->region,
2809 &vcpu->arch.guest_fpu.state->fxsave,
2810 sizeof(struct i387_fxsave_struct));
2811 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
2812 XSTATE_FPSSE;
2813 }
2814}
2815
2816static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
2817 struct kvm_xsave *guest_xsave)
2818{
2819 u64 xstate_bv =
2820 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
2821
2822 if (cpu_has_xsave)
2823 memcpy(&vcpu->arch.guest_fpu.state->xsave,
f45755b8 2824 guest_xsave->region, xstate_size);
2d5b5a66
SY		 2825 else {
2826 if (xstate_bv & ~XSTATE_FPSSE)
2827 return -EINVAL;
2828 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
2829 guest_xsave->region, sizeof(struct i387_fxsave_struct));
2830 }
2831 return 0;
2832}
2833
2834static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
2835 struct kvm_xcrs *guest_xcrs)
2836{
2837 if (!cpu_has_xsave) {
2838 guest_xcrs->nr_xcrs = 0;
2839 return;
2840 }
2841
2842 guest_xcrs->nr_xcrs = 1;
2843 guest_xcrs->flags = 0;
2844 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
2845 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
2846}
2847
2848static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
2849 struct kvm_xcrs *guest_xcrs)
2850{
2851 int i, r = 0;
2852
2853 if (!cpu_has_xsave)
2854 return -EINVAL;
2855
2856 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
2857 return -EINVAL;
2858
2859 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
2860 /* Only support XCR0 currently */
2861 if (guest_xcrs->xcrs[0].xcr == XCR_XFEATURE_ENABLED_MASK) {
2862 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
2863 guest_xcrs->xcrs[0].value);
2864 break;
2865 }
2866 if (r)
2867 r = -EINVAL;
2868 return r;
2869}
2870
313a3dc7
CO		 2871long kvm_arch_vcpu_ioctl(struct file *filp,
2872 unsigned int ioctl, unsigned long arg)
2873{
2874 struct kvm_vcpu *vcpu = filp->private_data;
2875 void __user *argp = (void __user *)arg;
2876 int r;
d1ac91d8
AK		 2877 union {
2878 struct kvm_lapic_state *lapic;
2879 struct kvm_xsave *xsave;
2880 struct kvm_xcrs *xcrs;
2881 void *buffer;
2882 } u;
2883
2884 u.buffer = NULL;
313a3dc7
CO		 2885 switch (ioctl) {
2886 case KVM_GET_LAPIC: {
2204ae3c
MT		 2887 r = -EINVAL;
2888 if (!vcpu->arch.apic)
2889 goto out;
d1ac91d8 2890 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 2891
b772ff36 2892 r = -ENOMEM;
d1ac91d8 2893 if (!u.lapic)
b772ff36 2894 goto out;
d1ac91d8 2895 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 2896 if (r)
2897 goto out;
2898 r = -EFAULT;
d1ac91d8 2899 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 2900 goto out;
2901 r = 0;
2902 break;
2903 }
2904 case KVM_SET_LAPIC: {
2204ae3c
MT		 2905 r = -EINVAL;
2906 if (!vcpu->arch.apic)
2907 goto out;
d1ac91d8 2908 u.lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
b772ff36 2909 r = -ENOMEM;
d1ac91d8 2910 if (!u.lapic)
b772ff36 2911 goto out;
313a3dc7 2912 r = -EFAULT;
d1ac91d8 2913 if (copy_from_user(u.lapic, argp, sizeof(struct kvm_lapic_state)))
313a3dc7 2914 goto out;
d1ac91d8 2915 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 2916 if (r)
2917 goto out;
2918 r = 0;
2919 break;
2920 }
f77bc6a4
ZX		 2921 case KVM_INTERRUPT: {
2922 struct kvm_interrupt irq;
2923
2924 r = -EFAULT;
2925 if (copy_from_user(&irq, argp, sizeof irq))
2926 goto out;
2927 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
2928 if (r)
2929 goto out;
2930 r = 0;
2931 break;
2932 }
c4abb7c9
JK		 2933 case KVM_NMI: {
2934 r = kvm_vcpu_ioctl_nmi(vcpu);
2935 if (r)
2936 goto out;
2937 r = 0;
2938 break;
2939 }
313a3dc7
CO		 2940 case KVM_SET_CPUID: {
2941 struct kvm_cpuid __user *cpuid_arg = argp;
2942 struct kvm_cpuid cpuid;
2943
2944 r = -EFAULT;
2945 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2946 goto out;
2947 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
2948 if (r)
2949 goto out;
2950 break;
2951 }
07716717
DK		 2952 case KVM_SET_CPUID2: {
2953 struct kvm_cpuid2 __user *cpuid_arg = argp;
2954 struct kvm_cpuid2 cpuid;
2955
2956 r = -EFAULT;
2957 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2958 goto out;
2959 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 2960 cpuid_arg->entries);
07716717
DK		 2961 if (r)
2962 goto out;
2963 break;
2964 }
2965 case KVM_GET_CPUID2: {
2966 struct kvm_cpuid2 __user *cpuid_arg = argp;
2967 struct kvm_cpuid2 cpuid;
2968
2969 r = -EFAULT;
2970 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2971 goto out;
2972 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 2973 cpuid_arg->entries);
07716717
DK		 2974 if (r)
2975 goto out;
2976 r = -EFAULT;
2977 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2978 goto out;
2979 r = 0;
2980 break;
2981 }
313a3dc7
CO		 2982 case KVM_GET_MSRS:
2983 r = msr_io(vcpu, argp, kvm_get_msr, 1);
2984 break;
2985 case KVM_SET_MSRS:
2986 r = msr_io(vcpu, argp, do_set_msr, 0);
2987 break;
b209749f
AK		 2988 case KVM_TPR_ACCESS_REPORTING: {
2989 struct kvm_tpr_access_ctl tac;
2990
2991 r = -EFAULT;
2992 if (copy_from_user(&tac, argp, sizeof tac))
2993 goto out;
2994 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
2995 if (r)
2996 goto out;
2997 r = -EFAULT;
2998 if (copy_to_user(argp, &tac, sizeof tac))
2999 goto out;
3000 r = 0;
3001 break;
3002 };
b93463aa
AK		 3003 case KVM_SET_VAPIC_ADDR: {
3004 struct kvm_vapic_addr va;
3005
3006 r = -EINVAL;
3007 if (!irqchip_in_kernel(vcpu->kvm))
3008 goto out;
3009 r = -EFAULT;
3010 if (copy_from_user(&va, argp, sizeof va))
3011 goto out;
3012 r = 0;
3013 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
3014 break;
3015 }
890ca9ae
HY		 3016 case KVM_X86_SETUP_MCE: {
3017 u64 mcg_cap;
3018
3019 r = -EFAULT;
3020 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3021 goto out;
3022 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3023 break;
3024 }
3025 case KVM_X86_SET_MCE: {
3026 struct kvm_x86_mce mce;
3027
3028 r = -EFAULT;
3029 if (copy_from_user(&mce, argp, sizeof mce))
3030 goto out;
3031 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3032 break;
3033 }
3cfc3092
JK		 3034 case KVM_GET_VCPU_EVENTS: {
3035 struct kvm_vcpu_events events;
3036
3037 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3038
3039 r = -EFAULT;
3040 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3041 break;
3042 r = 0;
3043 break;
3044 }
3045 case KVM_SET_VCPU_EVENTS: {
3046 struct kvm_vcpu_events events;
3047
3048 r = -EFAULT;
3049 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3050 break;
3051
3052 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3053 break;
3054 }
a1efbe77
JK		 3055 case KVM_GET_DEBUGREGS: {
3056 struct kvm_debugregs dbgregs;
3057
3058 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3059
3060 r = -EFAULT;
3061 if (copy_to_user(argp, &dbgregs,
3062 sizeof(struct kvm_debugregs)))
3063 break;
3064 r = 0;
3065 break;
3066 }
3067 case KVM_SET_DEBUGREGS: {
3068 struct kvm_debugregs dbgregs;
3069
3070 r = -EFAULT;
3071 if (copy_from_user(&dbgregs, argp,
3072 sizeof(struct kvm_debugregs)))
3073 break;
3074
3075 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3076 break;
3077 }
2d5b5a66 3078 case KVM_GET_XSAVE: {
d1ac91d8 3079 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3080 r = -ENOMEM;
d1ac91d8 3081 if (!u.xsave)
2d5b5a66
SY		 3082 break;
3083
d1ac91d8 3084 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3085
3086 r = -EFAULT;
d1ac91d8 3087 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3088 break;
3089 r = 0;
3090 break;
3091 }
3092 case KVM_SET_XSAVE: {
d1ac91d8 3093 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3094 r = -ENOMEM;
d1ac91d8 3095 if (!u.xsave)
2d5b5a66
SY		 3096 break;
3097
3098 r = -EFAULT;
d1ac91d8 3099 if (copy_from_user(u.xsave, argp, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3100 break;
3101
d1ac91d8 3102 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3103 break;
3104 }
3105 case KVM_GET_XCRS: {
d1ac91d8 3106 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3107 r = -ENOMEM;
d1ac91d8 3108 if (!u.xcrs)
2d5b5a66
SY		 3109 break;
3110
d1ac91d8 3111 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3112
3113 r = -EFAULT;
d1ac91d8 3114 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3115 sizeof(struct kvm_xcrs)))
3116 break;
3117 r = 0;
3118 break;
3119 }
3120 case KVM_SET_XCRS: {
d1ac91d8 3121 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3122 r = -ENOMEM;
d1ac91d8 3123 if (!u.xcrs)
2d5b5a66
SY		 3124 break;
3125
3126 r = -EFAULT;
d1ac91d8 3127 if (copy_from_user(u.xcrs, argp,
2d5b5a66
SY		 3128 sizeof(struct kvm_xcrs)))
3129 break;
3130
d1ac91d8 3131 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3132 break;
3133 }
92a1f12d
JR		 3134 case KVM_SET_TSC_KHZ: {
3135 u32 user_tsc_khz;
3136
3137 r = -EINVAL;
3138 if (!kvm_has_tsc_control)
3139 break;
3140
3141 user_tsc_khz = (u32)arg;
3142
3143 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3144 goto out;
3145
3146 kvm_x86_ops->set_tsc_khz(vcpu, user_tsc_khz);
3147
3148 r = 0;
3149 goto out;
3150 }
3151 case KVM_GET_TSC_KHZ: {
3152 r = -EIO;
3153 if (check_tsc_unstable())
3154 goto out;
3155
3156 r = vcpu_tsc_khz(vcpu);
3157
3158 goto out;
3159 }
313a3dc7
CO		 3160 default:
3161 r = -EINVAL;
3162 }
3163out:
d1ac91d8 3164 kfree(u.buffer);
313a3dc7
CO		 3165 return r;
3166}
3167
1fe779f8
CO		 3168static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3169{
3170 int ret;
3171
3172 if (addr > (unsigned int)(-3 * PAGE_SIZE))
3173 return -1;
3174 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3175 return ret;
3176}
3177
b927a3ce
SY		 3178static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3179 u64 ident_addr)
3180{
3181 kvm->arch.ept_identity_map_addr = ident_addr;
3182 return 0;
3183}
3184
1fe779f8
CO		 3185static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3186 u32 kvm_nr_mmu_pages)
3187{
3188 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3189 return -EINVAL;
3190
79fac95e 3191 mutex_lock(&kvm->slots_lock);
7c8a83b7 3192 spin_lock(&kvm->mmu_lock);
1fe779f8
CO		 3193
3194 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3195 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3196
7c8a83b7 3197 spin_unlock(&kvm->mmu_lock);
79fac95e 3198 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3199 return 0;
3200}
3201
3202static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3203{
39de71ec 3204 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3205}
3206
1fe779f8
CO		 3207static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3208{
3209 int r;
3210
3211 r = 0;
3212 switch (chip->chip_id) {
3213 case KVM_IRQCHIP_PIC_MASTER:
3214 memcpy(&chip->chip.pic,
3215 &pic_irqchip(kvm)->pics[0],
3216 sizeof(struct kvm_pic_state));
3217 break;
3218 case KVM_IRQCHIP_PIC_SLAVE:
3219 memcpy(&chip->chip.pic,
3220 &pic_irqchip(kvm)->pics[1],
3221 sizeof(struct kvm_pic_state));
3222 break;
3223 case KVM_IRQCHIP_IOAPIC:
eba0226b 3224 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3225 break;
3226 default:
3227 r = -EINVAL;
3228 break;
3229 }
3230 return r;
3231}
3232
3233static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3234{
3235 int r;
3236
3237 r = 0;
3238 switch (chip->chip_id) {
3239 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3240 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3241 memcpy(&pic_irqchip(kvm)->pics[0],
3242 &chip->chip.pic,
3243 sizeof(struct kvm_pic_state));
f4f51050 3244 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3245 break;
3246 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3247 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3248 memcpy(&pic_irqchip(kvm)->pics[1],
3249 &chip->chip.pic,
3250 sizeof(struct kvm_pic_state));
f4f51050 3251 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3252 break;
3253 case KVM_IRQCHIP_IOAPIC:
eba0226b 3254 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3255 break;
3256 default:
3257 r = -EINVAL;
3258 break;
3259 }
3260 kvm_pic_update_irq(pic_irqchip(kvm));
3261 return r;
3262}
3263
e0f63cb9
SY		 3264static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3265{
3266 int r = 0;
3267
894a9c55 3268 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3269 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 3270 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3271 return r;
3272}
3273
3274static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3275{
3276 int r = 0;
3277
894a9c55 3278 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3279 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 3280 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3281 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3282 return r;
3283}
3284
3285static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3286{
3287 int r = 0;
3288
3289 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3290 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3291 sizeof(ps->channels));
3292 ps->flags = kvm->arch.vpit->pit_state.flags;
3293 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3294 memset(&ps->reserved, 0, sizeof(ps->reserved));
e9f42757
BK		 3295 return r;
3296}
3297
3298static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3299{
3300 int r = 0, start = 0;
3301 u32 prev_legacy, cur_legacy;
3302 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3303 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3304 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3305 if (!prev_legacy && cur_legacy)
3306 start = 1;
3307 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3308 sizeof(kvm->arch.vpit->pit_state.channels));
3309 kvm->arch.vpit->pit_state.flags = ps->flags;
3310 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 3311 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3312 return r;
3313}
3314
52d939a0
MT		 3315static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3316 struct kvm_reinject_control *control)
3317{
3318 if (!kvm->arch.vpit)
3319 return -ENXIO;
894a9c55 3320 mutex_lock(&kvm->arch.vpit->pit_state.lock);
52d939a0 3321 kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject;
894a9c55 3322 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3323 return 0;
3324}
3325
5bb064dc
ZX		 3326/*
3327 * Get (and clear) the dirty memory log for a memory slot.
3328 */
3329int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
3330 struct kvm_dirty_log *log)
3331{
87bf6e7d 3332 int r, i;
5bb064dc 3333 struct kvm_memory_slot *memslot;
87bf6e7d 3334 unsigned long n;
b050b015 3335 unsigned long is_dirty = 0;
5bb064dc 3336
79fac95e 3337 mutex_lock(&kvm->slots_lock);
5bb064dc 3338
b050b015
MT		 3339 r = -EINVAL;
3340 if (log->slot >= KVM_MEMORY_SLOTS)
3341 goto out;
3342
3343 memslot = &kvm->memslots->memslots[log->slot];
3344 r = -ENOENT;
3345 if (!memslot->dirty_bitmap)
3346 goto out;
3347
87bf6e7d 3348 n = kvm_dirty_bitmap_bytes(memslot);
b050b015 3349
b050b015
MT		 3350 for (i = 0; !is_dirty && i < n/sizeof(long); i++)
3351 is_dirty = memslot->dirty_bitmap[i];
5bb064dc
ZX		 3352
3353 /* If nothing is dirty, don't bother messing with page tables. */
3354 if (is_dirty) {
b050b015 3355 struct kvm_memslots *slots, *old_slots;
914ebccd 3356 unsigned long *dirty_bitmap;
b050b015 3357
515a0127
TY		 3358 dirty_bitmap = memslot->dirty_bitmap_head;
3359 if (memslot->dirty_bitmap == dirty_bitmap)
3360 dirty_bitmap += n / sizeof(long);
914ebccd 3361 memset(dirty_bitmap, 0, n);
b050b015 3362
914ebccd
TY		 3363 r = -ENOMEM;
3364 slots = kzalloc(sizeof(struct kvm_memslots), GFP_KERNEL);
515a0127 3365 if (!slots)
914ebccd 3366 goto out;
b050b015
MT		 3367 memcpy(slots, kvm->memslots, sizeof(struct kvm_memslots));
3368 slots->memslots[log->slot].dirty_bitmap = dirty_bitmap;
49c7754c 3369 slots->generation++;
b050b015
MT		 3370
3371 old_slots = kvm->memslots;
3372 rcu_assign_pointer(kvm->memslots, slots);
3373 synchronize_srcu_expedited(&kvm->srcu);
3374 dirty_bitmap = old_slots->memslots[log->slot].dirty_bitmap;
3375 kfree(old_slots);
914ebccd 3376
edde99ce
MT		 3377 spin_lock(&kvm->mmu_lock);
3378 kvm_mmu_slot_remove_write_access(kvm, log->slot);
3379 spin_unlock(&kvm->mmu_lock);
3380
914ebccd 3381 r = -EFAULT;
515a0127 3382 if (copy_to_user(log->dirty_bitmap, dirty_bitmap, n))
914ebccd 3383 goto out;
914ebccd
TY		 3384 } else {
3385 r = -EFAULT;
3386 if (clear_user(log->dirty_bitmap, n))
3387 goto out;
5bb064dc 3388 }
b050b015 3389
5bb064dc
ZX		 3390 r = 0;
3391out:
79fac95e 3392 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3393 return r;
3394}
3395
1fe779f8
CO		 3396long kvm_arch_vm_ioctl(struct file *filp,
3397 unsigned int ioctl, unsigned long arg)
3398{
3399 struct kvm *kvm = filp->private_data;
3400 void __user *argp = (void __user *)arg;
367e1319 3401 int r = -ENOTTY;
f0d66275
DH		 3402 /*
3403 * This union makes it completely explicit to gcc-3.x
3404 * that these two variables' stack usage should be
3405 * combined, not added together.
3406 */
3407 union {
3408 struct kvm_pit_state ps;
e9f42757 3409 struct kvm_pit_state2 ps2;
c5ff41ce 3410 struct kvm_pit_config pit_config;
f0d66275 3411 } u;
1fe779f8
CO		 3412
3413 switch (ioctl) {
3414 case KVM_SET_TSS_ADDR:
3415 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
3416 if (r < 0)
3417 goto out;
3418 break;
b927a3ce
SY		 3419 case KVM_SET_IDENTITY_MAP_ADDR: {
3420 u64 ident_addr;
3421
3422 r = -EFAULT;
3423 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3424 goto out;
3425 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
3426 if (r < 0)
3427 goto out;
3428 break;
3429 }
1fe779f8
CO		 3430 case KVM_SET_NR_MMU_PAGES:
3431 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
3432 if (r)
3433 goto out;
3434 break;
3435 case KVM_GET_NR_MMU_PAGES:
3436 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3437 break;
3ddea128
MT		 3438 case KVM_CREATE_IRQCHIP: {
3439 struct kvm_pic *vpic;
3440
3441 mutex_lock(&kvm->lock);
3442 r = -EEXIST;
3443 if (kvm->arch.vpic)
3444 goto create_irqchip_unlock;
1fe779f8 3445 r = -ENOMEM;
3ddea128
MT		 3446 vpic = kvm_create_pic(kvm);
3447 if (vpic) {
1fe779f8
CO		 3448 r = kvm_ioapic_init(kvm);
3449 if (r) {
175504cd 3450 mutex_lock(&kvm->slots_lock);
72bb2fcd
WY		 3451 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3452 &vpic->dev);
175504cd 3453 mutex_unlock(&kvm->slots_lock);
3ddea128
MT		 3454 kfree(vpic);
3455 goto create_irqchip_unlock;
1fe779f8
CO		 3456 }
3457 } else
3ddea128
MT		 3458 goto create_irqchip_unlock;
3459 smp_wmb();
3460 kvm->arch.vpic = vpic;
3461 smp_wmb();
399ec807
AK		 3462 r = kvm_setup_default_irq_routing(kvm);
3463 if (r) {
175504cd 3464 mutex_lock(&kvm->slots_lock);
3ddea128 3465 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 3466 kvm_ioapic_destroy(kvm);
3467 kvm_destroy_pic(kvm);
3ddea128 3468 mutex_unlock(&kvm->irq_lock);
175504cd 3469 mutex_unlock(&kvm->slots_lock);
399ec807 3470 }
3ddea128
MT		 3471 create_irqchip_unlock:
3472 mutex_unlock(&kvm->lock);
1fe779f8 3473 break;
3ddea128 3474 }
7837699f 3475 case KVM_CREATE_PIT:
c5ff41ce
JK		 3476 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3477 goto create_pit;
3478 case KVM_CREATE_PIT2:
3479 r = -EFAULT;
3480 if (copy_from_user(&u.pit_config, argp,
3481 sizeof(struct kvm_pit_config)))
3482 goto out;
3483 create_pit:
79fac95e 3484 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3485 r = -EEXIST;
3486 if (kvm->arch.vpit)
3487 goto create_pit_unlock;
7837699f 3488 r = -ENOMEM;
c5ff41ce 3489 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3490 if (kvm->arch.vpit)
3491 r = 0;
269e05e4 3492 create_pit_unlock:
79fac95e 3493 mutex_unlock(&kvm->slots_lock);
7837699f 3494 break;
4925663a 3495 case KVM_IRQ_LINE_STATUS:
1fe779f8
CO		 3496 case KVM_IRQ_LINE: {
3497 struct kvm_irq_level irq_event;
3498
3499 r = -EFAULT;
3500 if (copy_from_user(&irq_event, argp, sizeof irq_event))
3501 goto out;
160d2f6c 3502 r = -ENXIO;
1fe779f8 3503 if (irqchip_in_kernel(kvm)) {
4925663a 3504 __s32 status;
4925663a
GN		 3505 status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3506 irq_event.irq, irq_event.level);
4925663a 3507 if (ioctl == KVM_IRQ_LINE_STATUS) {
160d2f6c 3508 r = -EFAULT;
4925663a
GN		 3509 irq_event.status = status;
3510 if (copy_to_user(argp, &irq_event,
3511 sizeof irq_event))
3512 goto out;
3513 }
1fe779f8
CO		 3514 r = 0;
3515 }
3516 break;
3517 }
3518 case KVM_GET_IRQCHIP: {
3519 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 3520 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 3521
f0d66275
DH		 3522 r = -ENOMEM;
3523 if (!chip)
1fe779f8 3524 goto out;
f0d66275
DH		 3525 r = -EFAULT;
3526 if (copy_from_user(chip, argp, sizeof *chip))
3527 goto get_irqchip_out;
1fe779f8
CO		 3528 r = -ENXIO;
3529 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3530 goto get_irqchip_out;
3531 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3532 if (r)
f0d66275 3533 goto get_irqchip_out;
1fe779f8 3534 r = -EFAULT;
f0d66275
DH		 3535 if (copy_to_user(argp, chip, sizeof *chip))
3536 goto get_irqchip_out;
1fe779f8 3537 r = 0;
f0d66275
DH		 3538 get_irqchip_out:
3539 kfree(chip);
3540 if (r)
3541 goto out;
1fe779f8
CO		 3542 break;
3543 }
3544 case KVM_SET_IRQCHIP: {
3545 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 3546 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 3547
f0d66275
DH		 3548 r = -ENOMEM;
3549 if (!chip)
1fe779f8 3550 goto out;
f0d66275
DH		 3551 r = -EFAULT;
3552 if (copy_from_user(chip, argp, sizeof *chip))
3553 goto set_irqchip_out;
1fe779f8
CO		 3554 r = -ENXIO;
3555 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3556 goto set_irqchip_out;
3557 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3558 if (r)
f0d66275 3559 goto set_irqchip_out;
1fe779f8 3560 r = 0;
f0d66275
DH		 3561 set_irqchip_out:
3562 kfree(chip);
3563 if (r)
3564 goto out;
1fe779f8
CO		 3565 break;
3566 }
e0f63cb9 3567 case KVM_GET_PIT: {
e0f63cb9 3568 r = -EFAULT;
f0d66275 3569 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3570 goto out;
3571 r = -ENXIO;
3572 if (!kvm->arch.vpit)
3573 goto out;
f0d66275 3574 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3575 if (r)
3576 goto out;
3577 r = -EFAULT;
f0d66275 3578 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3579 goto out;
3580 r = 0;
3581 break;
3582 }
3583 case KVM_SET_PIT: {
e0f63cb9 3584 r = -EFAULT;
f0d66275 3585 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3586 goto out;
3587 r = -ENXIO;
3588 if (!kvm->arch.vpit)
3589 goto out;
f0d66275 3590 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3591 if (r)
3592 goto out;
3593 r = 0;
3594 break;
3595 }
e9f42757
BK		 3596 case KVM_GET_PIT2: {
3597 r = -ENXIO;
3598 if (!kvm->arch.vpit)
3599 goto out;
3600 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3601 if (r)
3602 goto out;
3603 r = -EFAULT;
3604 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3605 goto out;
3606 r = 0;
3607 break;
3608 }
3609 case KVM_SET_PIT2: {
3610 r = -EFAULT;
3611 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3612 goto out;
3613 r = -ENXIO;
3614 if (!kvm->arch.vpit)
3615 goto out;
3616 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
3617 if (r)
3618 goto out;
3619 r = 0;
3620 break;
3621 }
52d939a0
MT		 3622 case KVM_REINJECT_CONTROL: {
3623 struct kvm_reinject_control control;
3624 r = -EFAULT;
3625 if (copy_from_user(&control, argp, sizeof(control)))
3626 goto out;
3627 r = kvm_vm_ioctl_reinject(kvm, &control);
3628 if (r)
3629 goto out;
3630 r = 0;
3631 break;
3632 }
ffde22ac
ES		 3633 case KVM_XEN_HVM_CONFIG: {
3634 r = -EFAULT;
3635 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3636 sizeof(struct kvm_xen_hvm_config)))
3637 goto out;
3638 r = -EINVAL;
3639 if (kvm->arch.xen_hvm_config.flags)
3640 goto out;
3641 r = 0;
3642 break;
3643 }
afbcf7ab 3644 case KVM_SET_CLOCK: {
afbcf7ab
GC		 3645 struct kvm_clock_data user_ns;
3646 u64 now_ns;
3647 s64 delta;
3648
3649 r = -EFAULT;
3650 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3651 goto out;
3652
3653 r = -EINVAL;
3654 if (user_ns.flags)
3655 goto out;
3656
3657 r = 0;
395c6b0a 3658 local_irq_disable();
759379dd 3659 now_ns = get_kernel_ns();
afbcf7ab 3660 delta = user_ns.clock - now_ns;
395c6b0a 3661 local_irq_enable();
afbcf7ab
GC		 3662 kvm->arch.kvmclock_offset = delta;
3663 break;
3664 }
3665 case KVM_GET_CLOCK: {
afbcf7ab
GC		 3666 struct kvm_clock_data user_ns;
3667 u64 now_ns;
3668
395c6b0a 3669 local_irq_disable();
759379dd 3670 now_ns = get_kernel_ns();
afbcf7ab 3671 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 3672 local_irq_enable();
afbcf7ab 3673 user_ns.flags = 0;
97e69aa6 3674 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 3675
3676 r = -EFAULT;
3677 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3678 goto out;
3679 r = 0;
3680 break;
3681 }
3682
1fe779f8
CO		 3683 default:
3684 ;
3685 }
3686out:
3687 return r;
3688}
3689
a16b043c 3690static void kvm_init_msr_list(void)
043405e1
CO		 3691{
3692 u32 dummy[2];
3693 unsigned i, j;
3694
e3267cbb
GC		 3695 /* skip the first msrs in the list. KVM-specific */
3696 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3697 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3698 continue;
3699 if (j < i)
3700 msrs_to_save[j] = msrs_to_save[i];
3701 j++;
3702 }
3703 num_msrs_to_save = j;
3704}
3705
bda9020e
MT		 3706static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3707 const void *v)
bbd9b64e 3708{
70252a10
AK		 3709 int handled = 0;
3710 int n;
3711
3712 do {
3713 n = min(len, 8);
3714 if (!(vcpu->arch.apic &&
3715 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v))
3716 && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3717 break;
3718 handled += n;
3719 addr += n;
3720 len -= n;
3721 v += n;
3722 } while (len);
bbd9b64e 3723
70252a10 3724 return handled;
bbd9b64e
CO		 3725}
3726
bda9020e 3727static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 3728{
70252a10
AK		 3729 int handled = 0;
3730 int n;
3731
3732 do {
3733 n = min(len, 8);
3734 if (!(vcpu->arch.apic &&
3735 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v))
3736 && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3737 break;
3738 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
3739 handled += n;
3740 addr += n;
3741 len -= n;
3742 v += n;
3743 } while (len);
bbd9b64e 3744
70252a10 3745 return handled;
bbd9b64e
CO		 3746}
3747
2dafc6c2
GN		 3748static void kvm_set_segment(struct kvm_vcpu *vcpu,
3749 struct kvm_segment *var, int seg)
3750{
3751 kvm_x86_ops->set_segment(vcpu, var, seg);
3752}
3753
3754void kvm_get_segment(struct kvm_vcpu *vcpu,
3755 struct kvm_segment *var, int seg)
3756{
3757 kvm_x86_ops->get_segment(vcpu, var, seg);
3758}
3759
c30a358d
JR		 3760static gpa_t translate_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
3761{
3762 return gpa;
3763}
3764
02f59dc9
JR		 3765static gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
3766{
3767 gpa_t t_gpa;
ab9ae313 3768 struct x86_exception exception;
02f59dc9
JR		 3769
3770 BUG_ON(!mmu_is_nested(vcpu));
3771
3772 /* NPT walks are always user-walks */
3773 access |= PFERR_USER_MASK;
ab9ae313 3774 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &exception);
02f59dc9
JR		 3775
3776 return t_gpa;
3777}
3778
ab9ae313
AK		 3779gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
3780 struct x86_exception *exception)
1871c602
GN		 3781{
3782 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 3783 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3784}
3785
ab9ae313
AK		 3786 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
3787 struct x86_exception *exception)
1871c602
GN		 3788{
3789 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3790 access |= PFERR_FETCH_MASK;
ab9ae313 3791 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3792}
3793
ab9ae313
AK		 3794gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
3795 struct x86_exception *exception)
1871c602
GN		 3796{
3797 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3798 access |= PFERR_WRITE_MASK;
ab9ae313 3799 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3800}
3801
3802/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 3803gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
3804 struct x86_exception *exception)
1871c602 3805{
ab9ae313 3806 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 3807}
3808
3809static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3810 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 3811 struct x86_exception *exception)
bbd9b64e
CO		 3812{
3813 void *data = val;
10589a46 3814 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 3815
3816 while (bytes) {
14dfe855 3817 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 3818 exception);
bbd9b64e 3819 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 3820 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 3821 int ret;
3822
bcc55cba 3823 if (gpa == UNMAPPED_GVA)
ab9ae313 3824 return X86EMUL_PROPAGATE_FAULT;
77c2002e 3825 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46 3826 if (ret < 0) {
c3cd7ffa 3827 r = X86EMUL_IO_NEEDED;
10589a46
MT		 3828 goto out;
3829 }
bbd9b64e 3830
77c2002e
IE		 3831 bytes -= toread;
3832 data += toread;
3833 addr += toread;
bbd9b64e 3834 }
10589a46 3835out:
10589a46 3836 return r;
bbd9b64e 3837}
77c2002e 3838
1871c602 3839/* used for instruction fetching */
0f65dd70
AK		 3840static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
3841 gva_t addr, void *val, unsigned int bytes,
bcc55cba 3842 struct x86_exception *exception)
1871c602 3843{
0f65dd70 3844 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 3845 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 3846
1871c602 3847 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
bcc55cba
AK		 3848 access | PFERR_FETCH_MASK,
3849 exception);
1871c602
GN		 3850}
3851
064aea77 3852int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 3853 gva_t addr, void *val, unsigned int bytes,
bcc55cba 3854 struct x86_exception *exception)
1871c602 3855{
0f65dd70 3856 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 3857 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 3858
1871c602 3859 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 3860 exception);
1871c602 3861}
064aea77 3862EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 3863
0f65dd70
AK		 3864static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
3865 gva_t addr, void *val, unsigned int bytes,
bcc55cba 3866 struct x86_exception *exception)
1871c602 3867{
0f65dd70 3868 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 3869 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 3870}
3871
0f65dd70
AK		 3872static int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
3873 gva_t addr, void *val,
2dafc6c2 3874 unsigned int bytes,
bcc55cba 3875 struct x86_exception *exception)
77c2002e 3876{
0f65dd70 3877 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 3878 void *data = val;
3879 int r = X86EMUL_CONTINUE;
3880
3881 while (bytes) {
14dfe855
JR		 3882 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
3883 PFERR_WRITE_MASK,
ab9ae313 3884 exception);
77c2002e
IE		 3885 unsigned offset = addr & (PAGE_SIZE-1);
3886 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
3887 int ret;
3888
bcc55cba 3889 if (gpa == UNMAPPED_GVA)
ab9ae313 3890 return X86EMUL_PROPAGATE_FAULT;
77c2002e
IE		 3891 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
3892 if (ret < 0) {
c3cd7ffa 3893 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 3894 goto out;
3895 }
3896
3897 bytes -= towrite;
3898 data += towrite;
3899 addr += towrite;
3900 }
3901out:
3902 return r;
3903}
3904
0f65dd70
AK		 3905static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
3906 unsigned long addr,
bbd9b64e
CO		 3907 void *val,
3908 unsigned int bytes,
0f65dd70 3909 struct x86_exception *exception)
bbd9b64e 3910{
0f65dd70 3911 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bbd9b64e 3912 gpa_t gpa;
70252a10 3913 int handled;
bbd9b64e
CO		 3914
3915 if (vcpu->mmio_read_completed) {
3916 memcpy(val, vcpu->mmio_data, bytes);
aec51dc4
AK		 3917 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
3918 vcpu->mmio_phys_addr, *(u64 *)val);
bbd9b64e
CO		 3919 vcpu->mmio_read_completed = 0;
3920 return X86EMUL_CONTINUE;
3921 }
3922
ab9ae313 3923 gpa = kvm_mmu_gva_to_gpa_read(vcpu, addr, exception);
1871c602 3924
8fe681e9 3925 if (gpa == UNMAPPED_GVA)
1871c602 3926 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 3927
3928 /* For APIC access vmexit */
3929 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3930 goto mmio;
3931
0f65dd70 3932 if (kvm_read_guest_virt(ctxt, addr, val, bytes, exception)
bcc55cba 3933 == X86EMUL_CONTINUE)
bbd9b64e 3934 return X86EMUL_CONTINUE;
bbd9b64e
CO		 3935
3936mmio:
3937 /*
3938 * Is this MMIO handled locally?
3939 */
70252a10
AK		 3940 handled = vcpu_mmio_read(vcpu, gpa, bytes, val);
3941
3942 if (handled == bytes)
bbd9b64e 3943 return X86EMUL_CONTINUE;
70252a10
AK		 3944
3945 gpa += handled;
3946 bytes -= handled;
3947 val += handled;
aec51dc4
AK		 3948
3949 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
bbd9b64e
CO		 3950
3951 vcpu->mmio_needed = 1;
411c35b7
GN		 3952 vcpu->run->exit_reason = KVM_EXIT_MMIO;
3953 vcpu->run->mmio.phys_addr = vcpu->mmio_phys_addr = gpa;
cef4dea0
AK		 3954 vcpu->mmio_size = bytes;
3955 vcpu->run->mmio.len = min(vcpu->mmio_size, 8);
411c35b7 3956 vcpu->run->mmio.is_write = vcpu->mmio_is_write = 0;
cef4dea0 3957 vcpu->mmio_index = 0;
bbd9b64e 3958
c3cd7ffa 3959 return X86EMUL_IO_NEEDED;
bbd9b64e
CO		 3960}
3961
3200f405 3962int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 3963 const void *val, int bytes)
bbd9b64e
CO		 3964{
3965 int ret;
3966
3967 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 3968 if (ret < 0)
bbd9b64e 3969 return 0;
ad218f85 3970 kvm_mmu_pte_write(vcpu, gpa, val, bytes, 1);
bbd9b64e
CO		 3971 return 1;
3972}
3973
3974static int emulator_write_emulated_onepage(unsigned long addr,
3975 const void *val,
3976 unsigned int bytes,
bcc55cba 3977 struct x86_exception *exception,
bbd9b64e
CO		 3978 struct kvm_vcpu *vcpu)
3979{
10589a46 3980 gpa_t gpa;
70252a10 3981 int handled;
10589a46 3982
ab9ae313 3983 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, exception);
bbd9b64e 3984
8fe681e9 3985 if (gpa == UNMAPPED_GVA)
bbd9b64e 3986 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 3987
3988 /* For APIC access vmexit */
3989 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3990 goto mmio;
3991
3992 if (emulator_write_phys(vcpu, gpa, val, bytes))
3993 return X86EMUL_CONTINUE;
3994
3995mmio:
aec51dc4 3996 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 3997 /*
3998 * Is this MMIO handled locally?
3999 */
70252a10
AK		 4000 handled = vcpu_mmio_write(vcpu, gpa, bytes, val);
4001 if (handled == bytes)
bbd9b64e 4002 return X86EMUL_CONTINUE;
bbd9b64e 4003
70252a10
AK		 4004 gpa += handled;
4005 bytes -= handled;
4006 val += handled;
4007
bbd9b64e 4008 vcpu->mmio_needed = 1;
cef4dea0 4009 memcpy(vcpu->mmio_data, val, bytes);
411c35b7
GN		 4010 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4011 vcpu->run->mmio.phys_addr = vcpu->mmio_phys_addr = gpa;
cef4dea0
AK		 4012 vcpu->mmio_size = bytes;
4013 vcpu->run->mmio.len = min(vcpu->mmio_size, 8);
411c35b7 4014 vcpu->run->mmio.is_write = vcpu->mmio_is_write = 1;
cef4dea0
AK		 4015 memcpy(vcpu->run->mmio.data, vcpu->mmio_data, 8);
4016 vcpu->mmio_index = 0;
bbd9b64e
CO		 4017
4018 return X86EMUL_CONTINUE;
4019}
4020
0f65dd70
AK		 4021int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
4022 unsigned long addr,
8f6abd06
GN		 4023 const void *val,
4024 unsigned int bytes,
0f65dd70 4025 struct x86_exception *exception)
bbd9b64e 4026{
0f65dd70
AK		 4027 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4028
bbd9b64e
CO		 4029 /* Crossing a page boundary? */
4030 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
4031 int rc, now;
4032
4033 now = -addr & ~PAGE_MASK;
bcc55cba 4034 rc = emulator_write_emulated_onepage(addr, val, now, exception,
8fe681e9 4035 vcpu);
bbd9b64e
CO		 4036 if (rc != X86EMUL_CONTINUE)
4037 return rc;
4038 addr += now;
4039 val += now;
4040 bytes -= now;
4041 }
bcc55cba 4042 return emulator_write_emulated_onepage(addr, val, bytes, exception,
8fe681e9 4043 vcpu);
bbd9b64e 4044}
bbd9b64e 4045
daea3e73
AK		 4046#define CMPXCHG_TYPE(t, ptr, old, new) \
4047 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4048
4049#ifdef CONFIG_X86_64
4050# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4051#else
4052# define CMPXCHG64(ptr, old, new) \
9749a6c0 4053 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4054#endif
4055
0f65dd70
AK		 4056static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4057 unsigned long addr,
bbd9b64e
CO		 4058 const void *old,
4059 const void *new,
4060 unsigned int bytes,
0f65dd70 4061 struct x86_exception *exception)
bbd9b64e 4062{
0f65dd70 4063 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4064 gpa_t gpa;
4065 struct page *page;
4066 char *kaddr;
4067 bool exchanged;
2bacc55c 4068
daea3e73
AK		 4069 /* guests cmpxchg8b have to be emulated atomically */
4070 if (bytes > 8 || (bytes & (bytes - 1)))
4071 goto emul_write;
10589a46 4072
daea3e73 4073 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4074
daea3e73
AK		 4075 if (gpa == UNMAPPED_GVA ||
4076 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4077 goto emul_write;
2bacc55c 4078
daea3e73
AK		 4079 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4080 goto emul_write;
72dc67a6 4081
daea3e73 4082 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
c19b8bd6
WY		 4083 if (is_error_page(page)) {
4084 kvm_release_page_clean(page);
4085 goto emul_write;
4086 }
72dc67a6 4087
daea3e73
AK		 4088 kaddr = kmap_atomic(page, KM_USER0);
4089 kaddr += offset_in_page(gpa);
4090 switch (bytes) {
4091 case 1:
4092 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4093 break;
4094 case 2:
4095 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4096 break;
4097 case 4:
4098 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4099 break;
4100 case 8:
4101 exchanged = CMPXCHG64(kaddr, old, new);
4102 break;
4103 default:
4104 BUG();
2bacc55c 4105 }
daea3e73
AK		 4106 kunmap_atomic(kaddr, KM_USER0);
4107 kvm_release_page_dirty(page);
4108
4109 if (!exchanged)
4110 return X86EMUL_CMPXCHG_FAILED;
4111
8f6abd06
GN		 4112 kvm_mmu_pte_write(vcpu, gpa, new, bytes, 1);
4113
4114 return X86EMUL_CONTINUE;
4a5f48f6 4115
3200f405 4116emul_write:
daea3e73 4117 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4118
0f65dd70 4119 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4120}
4121
cf8f70bf
GN		 4122static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4123{
4124 /* TODO: String I/O for in kernel device */
4125 int r;
4126
4127 if (vcpu->arch.pio.in)
4128 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
4129 vcpu->arch.pio.size, pd);
4130 else
4131 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
4132 vcpu->arch.pio.port, vcpu->arch.pio.size,
4133 pd);
4134 return r;
4135}
4136
4137
ca1d4a9e
AK		 4138static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4139 int size, unsigned short port, void *val,
4140 unsigned int count)
cf8f70bf 4141{
ca1d4a9e
AK		 4142 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4143
7972995b 4144 if (vcpu->arch.pio.count)
cf8f70bf
GN		 4145 goto data_avail;
4146
61cfab2e 4147 trace_kvm_pio(0, port, size, count);
cf8f70bf
GN		 4148
4149 vcpu->arch.pio.port = port;
4150 vcpu->arch.pio.in = 1;
7972995b 4151 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4152 vcpu->arch.pio.size = size;
4153
4154 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
4155 data_avail:
4156 memcpy(val, vcpu->arch.pio_data, size * count);
7972995b 4157 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4158 return 1;
4159 }
4160
4161 vcpu->run->exit_reason = KVM_EXIT_IO;
4162 vcpu->run->io.direction = KVM_EXIT_IO_IN;
4163 vcpu->run->io.size = size;
4164 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4165 vcpu->run->io.count = count;
4166 vcpu->run->io.port = port;
4167
4168 return 0;
4169}
4170
ca1d4a9e
AK		 4171static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4172 int size, unsigned short port,
4173 const void *val, unsigned int count)
cf8f70bf 4174{
ca1d4a9e
AK		 4175 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4176
61cfab2e 4177 trace_kvm_pio(1, port, size, count);
cf8f70bf
GN		 4178
4179 vcpu->arch.pio.port = port;
4180 vcpu->arch.pio.in = 0;
7972995b 4181 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4182 vcpu->arch.pio.size = size;
4183
4184 memcpy(vcpu->arch.pio_data, val, size * count);
4185
4186 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4187 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4188 return 1;
4189 }
4190
4191 vcpu->run->exit_reason = KVM_EXIT_IO;
4192 vcpu->run->io.direction = KVM_EXIT_IO_OUT;
4193 vcpu->run->io.size = size;
4194 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4195 vcpu->run->io.count = count;
4196 vcpu->run->io.port = port;
4197
4198 return 0;
4199}
4200
bbd9b64e
CO		 4201static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4202{
4203 return kvm_x86_ops->get_segment_base(vcpu, seg);
4204}
4205
3cb16fe7 4206static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4207{
3cb16fe7 4208 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4209}
4210
f5f48ee1
SY		 4211int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4212{
4213 if (!need_emulate_wbinvd(vcpu))
4214 return X86EMUL_CONTINUE;
4215
4216 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4217 int cpu = get_cpu();
4218
4219 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4220 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4221 wbinvd_ipi, NULL, 1);
2eec7343 4222 put_cpu();
f5f48ee1 4223 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4224 } else
4225 wbinvd();
f5f48ee1
SY		 4226 return X86EMUL_CONTINUE;
4227}
4228EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4229
bcaf5cc5
AK		 4230static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4231{
4232 kvm_emulate_wbinvd(emul_to_vcpu(ctxt));
4233}
4234
717746e3 4235int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
bbd9b64e 4236{
717746e3 4237 return _kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4238}
4239
717746e3 4240int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
bbd9b64e 4241{
338dbc97 4242
717746e3 4243 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4244}
4245
52a46617 4246static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4247{
52a46617 4248 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4249}
4250
717746e3 4251static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4252{
717746e3 4253 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4254 unsigned long value;
4255
4256 switch (cr) {
4257 case 0:
4258 value = kvm_read_cr0(vcpu);
4259 break;
4260 case 2:
4261 value = vcpu->arch.cr2;
4262 break;
4263 case 3:
9f8fe504 4264 value = kvm_read_cr3(vcpu);
52a46617
GN		 4265 break;
4266 case 4:
4267 value = kvm_read_cr4(vcpu);
4268 break;
4269 case 8:
4270 value = kvm_get_cr8(vcpu);
4271 break;
4272 default:
4273 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
4274 return 0;
4275 }
4276
4277 return value;
4278}
4279
717746e3 4280static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4281{
717746e3 4282 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4283 int res = 0;
4284
52a46617
GN		 4285 switch (cr) {
4286 case 0:
49a9b07e 4287 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4288 break;
4289 case 2:
4290 vcpu->arch.cr2 = val;
4291 break;
4292 case 3:
2390218b 4293 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4294 break;
4295 case 4:
a83b29c6 4296 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4297 break;
4298 case 8:
eea1cff9 4299 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4300 break;
4301 default:
4302 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
0f12244f 4303 res = -1;
52a46617 4304 }
0f12244f
GN		 4305
4306 return res;
52a46617
GN		 4307}
4308
717746e3 4309static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 4310{
717746e3 4311 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 4312}
4313
4bff1e86 4314static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 4315{
4bff1e86 4316 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 4317}
4318
4bff1e86 4319static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 4320{
4bff1e86 4321 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 4322}
4323
1ac9d0cf
AK		 4324static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4325{
4326 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4327}
4328
4329static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4330{
4331 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4332}
4333
4bff1e86
AK		 4334static unsigned long emulator_get_cached_segment_base(
4335 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 4336{
4bff1e86 4337 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 4338}
4339
1aa36616
AK		 4340static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4341 struct desc_struct *desc, u32 *base3,
4342 int seg)
2dafc6c2
GN		 4343{
4344 struct kvm_segment var;
4345
4bff1e86 4346 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 4347 *selector = var.selector;
2dafc6c2
GN		 4348
4349 if (var.unusable)
4350 return false;
4351
4352 if (var.g)
4353 var.limit >>= 12;
4354 set_desc_limit(desc, var.limit);
4355 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 4356#ifdef CONFIG_X86_64
4357 if (base3)
4358 *base3 = var.base >> 32;
4359#endif
2dafc6c2
GN		 4360 desc->type = var.type;
4361 desc->s = var.s;
4362 desc->dpl = var.dpl;
4363 desc->p = var.present;
4364 desc->avl = var.avl;
4365 desc->l = var.l;
4366 desc->d = var.db;
4367 desc->g = var.g;
4368
4369 return true;
4370}
4371
1aa36616
AK		 4372static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4373 struct desc_struct *desc, u32 base3,
4374 int seg)
2dafc6c2 4375{
4bff1e86 4376 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 4377 struct kvm_segment var;
4378
1aa36616 4379 var.selector = selector;
2dafc6c2 4380 var.base = get_desc_base(desc);
5601d05b
GN		 4381#ifdef CONFIG_X86_64
4382 var.base |= ((u64)base3) << 32;
4383#endif
2dafc6c2
GN		 4384 var.limit = get_desc_limit(desc);
4385 if (desc->g)
4386 var.limit = (var.limit << 12) | 0xfff;
4387 var.type = desc->type;
4388 var.present = desc->p;
4389 var.dpl = desc->dpl;
4390 var.db = desc->d;
4391 var.s = desc->s;
4392 var.l = desc->l;
4393 var.g = desc->g;
4394 var.avl = desc->avl;
4395 var.present = desc->p;
4396 var.unusable = !var.present;
4397 var.padding = 0;
4398
4399 kvm_set_segment(vcpu, &var, seg);
4400 return;
4401}
4402
717746e3
AK		 4403static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4404 u32 msr_index, u64 *pdata)
4405{
4406 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
4407}
4408
4409static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4410 u32 msr_index, u64 data)
4411{
4412 return kvm_set_msr(emul_to_vcpu(ctxt), msr_index, data);
4413}
4414
6c3287f7
AK		 4415static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4416{
4417 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4418}
4419
5037f6f3
AK		 4420static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4421{
4422 preempt_disable();
5197b808 4423 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 4424 /*
4425 * CR0.TS may reference the host fpu state, not the guest fpu state,
4426 * so it may be clear at this point.
4427 */
4428 clts();
4429}
4430
4431static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4432{
4433 preempt_enable();
4434}
4435
2953538e 4436static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 4437 struct x86_instruction_info *info,
c4f035c6
AK		 4438 enum x86_intercept_stage stage)
4439{
2953538e 4440 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 4441}
4442
14af3f3c 4443static struct x86_emulate_ops emulate_ops = {
1871c602 4444 .read_std = kvm_read_guest_virt_system,
2dafc6c2 4445 .write_std = kvm_write_guest_virt_system,
1871c602 4446 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 4447 .read_emulated = emulator_read_emulated,
4448 .write_emulated = emulator_write_emulated,
4449 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 4450 .invlpg = emulator_invlpg,
cf8f70bf
GN		 4451 .pio_in_emulated = emulator_pio_in_emulated,
4452 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 4453 .get_segment = emulator_get_segment,
4454 .set_segment = emulator_set_segment,
5951c442 4455 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 4456 .get_gdt = emulator_get_gdt,
160ce1f1 4457 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 4458 .set_gdt = emulator_set_gdt,
4459 .set_idt = emulator_set_idt,
52a46617
GN		 4460 .get_cr = emulator_get_cr,
4461 .set_cr = emulator_set_cr,
9c537244 4462 .cpl = emulator_get_cpl,
35aa5375
GN		 4463 .get_dr = emulator_get_dr,
4464 .set_dr = emulator_set_dr,
717746e3
AK		 4465 .set_msr = emulator_set_msr,
4466 .get_msr = emulator_get_msr,
6c3287f7 4467 .halt = emulator_halt,
bcaf5cc5 4468 .wbinvd = emulator_wbinvd,
d6aa1000 4469 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 4470 .get_fpu = emulator_get_fpu,
4471 .put_fpu = emulator_put_fpu,
c4f035c6 4472 .intercept = emulator_intercept,
bbd9b64e
CO		 4473};
4474
5fdbf976
MT		 4475static void cache_all_regs(struct kvm_vcpu *vcpu)
4476{
4477 kvm_register_read(vcpu, VCPU_REGS_RAX);
4478 kvm_register_read(vcpu, VCPU_REGS_RSP);
4479 kvm_register_read(vcpu, VCPU_REGS_RIP);
4480 vcpu->arch.regs_dirty = ~0;
4481}
4482
95cb2295
GN		 4483static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4484{
4485 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
4486 /*
4487 * an sti; sti; sequence only disable interrupts for the first
4488 * instruction. So, if the last instruction, be it emulated or
4489 * not, left the system with the INT_STI flag enabled, it
4490 * means that the last instruction is an sti. We should not
4491 * leave the flag on in this case. The same goes for mov ss
4492 */
4493 if (!(int_shadow & mask))
4494 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4495}
4496
54b8486f
GN		 4497static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4498{
4499 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 4500 if (ctxt->exception.vector == PF_VECTOR)
6389ee94 4501 kvm_propagate_fault(vcpu, &ctxt->exception);
da9cb575
AK		 4502 else if (ctxt->exception.error_code_valid)
4503 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4504 ctxt->exception.error_code);
54b8486f 4505 else
da9cb575 4506 kvm_queue_exception(vcpu, ctxt->exception.vector);
54b8486f
GN		 4507}
4508
b5c9ff73
TY		 4509static void init_decode_cache(struct decode_cache *c,
4510 const unsigned long *regs)
4511{
4512 memset(c, 0, offsetof(struct decode_cache, regs));
4513 memcpy(c->regs, regs, sizeof(c->regs));
4514
4515 c->fetch.start = 0;
4516 c->fetch.end = 0;
4517 c->io_read.pos = 0;
4518 c->io_read.end = 0;
4519 c->mem_read.pos = 0;
4520 c->mem_read.end = 0;
4521}
4522
8ec4722d
MG		 4523static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4524{
adf52235
TY		 4525 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4526 struct decode_cache *c = &ctxt->decode;
8ec4722d
MG		 4527 int cs_db, cs_l;
4528
2aab2c5b
GN		 4529 /*
4530 * TODO: fix emulate.c to use guest_read/write_register
4531 * instead of direct ->regs accesses, can save hundred cycles
4532 * on Intel for instructions that don't read/change RSP, for
4533 * for example.
4534 */
8ec4722d
MG		 4535 cache_all_regs(vcpu);
4536
4537 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4538
adf52235
TY		 4539 ctxt->eflags = kvm_get_rflags(vcpu);
4540 ctxt->eip = kvm_rip_read(vcpu);
4541 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4542 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
4543 cs_l ? X86EMUL_MODE_PROT64 :
4544 cs_db ? X86EMUL_MODE_PROT32 :
4545 X86EMUL_MODE_PROT16;
4546 ctxt->guest_mode = is_guest_mode(vcpu);
4547
b5c9ff73 4548 init_decode_cache(c, vcpu->arch.regs);
7ae441ea 4549 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 4550}
4551
71f9833b 4552int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653
MG		 4553{
4554 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
4555 int ret;
4556
4557 init_emulate_ctxt(vcpu);
4558
4559 vcpu->arch.emulate_ctxt.decode.op_bytes = 2;
4560 vcpu->arch.emulate_ctxt.decode.ad_bytes = 2;
71f9833b
SH		 4561 vcpu->arch.emulate_ctxt.decode.eip = vcpu->arch.emulate_ctxt.eip +
4562 inc_eip;
7b105ca2 4563 ret = emulate_int_real(&vcpu->arch.emulate_ctxt, irq);
63995653
MG		 4564
4565 if (ret != X86EMUL_CONTINUE)
4566 return EMULATE_FAIL;
4567
4568 vcpu->arch.emulate_ctxt.eip = c->eip;
4569 memcpy(vcpu->arch.regs, c->regs, sizeof c->regs);
4570 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.eip);
f6e78475 4571 kvm_set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
63995653
MG		 4572
4573 if (irq == NMI_VECTOR)
4574 vcpu->arch.nmi_pending = false;
4575 else
4576 vcpu->arch.interrupt.pending = false;
4577
4578 return EMULATE_DONE;
4579}
4580EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4581
6d77dbfc
GN		 4582static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4583{
fc3a9157
JR		 4584 int r = EMULATE_DONE;
4585
6d77dbfc
GN		 4586 ++vcpu->stat.insn_emulation_fail;
4587 trace_kvm_emulate_insn_failed(vcpu);
fc3a9157
JR		 4588 if (!is_guest_mode(vcpu)) {
4589 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4590 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4591 vcpu->run->internal.ndata = 0;
4592 r = EMULATE_FAIL;
4593 }
6d77dbfc 4594 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 4595
4596 return r;
6d77dbfc
GN		 4597}
4598
a6f177ef
GN		 4599static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t gva)
4600{
4601 gpa_t gpa;
4602
68be0803
GN		 4603 if (tdp_enabled)
4604 return false;
4605
a6f177ef
GN		 4606 /*
4607 * if emulation was due to access to shadowed page table
4608 * and it failed try to unshadow page and re-entetr the
4609 * guest to let CPU execute the instruction.
4610 */
4611 if (kvm_mmu_unprotect_page_virt(vcpu, gva))
4612 return true;
4613
4614 gpa = kvm_mmu_gva_to_gpa_system(vcpu, gva, NULL);
4615
4616 if (gpa == UNMAPPED_GVA)
4617 return true; /* let cpu generate fault */
4618
4619 if (!kvm_is_error_hva(gfn_to_hva(vcpu->kvm, gpa >> PAGE_SHIFT)))
4620 return true;
4621
4622 return false;
4623}
4624
51d8b661
AP		 4625int x86_emulate_instruction(struct kvm_vcpu *vcpu,
4626 unsigned long cr2,
dc25e89e
AP		 4627 int emulation_type,
4628 void *insn,
4629 int insn_len)
bbd9b64e 4630{
95cb2295 4631 int r;
4d2179e1 4632 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
7ae441ea 4633 bool writeback = true;
bbd9b64e 4634
26eef70c 4635 kvm_clear_exception_queue(vcpu);
8d7d8102 4636
571008da 4637 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 4638 init_emulate_ctxt(vcpu);
95cb2295 4639 vcpu->arch.emulate_ctxt.interruptibility = 0;
da9cb575 4640 vcpu->arch.emulate_ctxt.have_exception = false;
4fc40f07 4641 vcpu->arch.emulate_ctxt.perm_ok = false;
bbd9b64e 4642
4005996e
AK		 4643 vcpu->arch.emulate_ctxt.only_vendor_specific_insn
4644 = emulation_type & EMULTYPE_TRAP_UD;
4645
dc25e89e 4646 r = x86_decode_insn(&vcpu->arch.emulate_ctxt, insn, insn_len);
bbd9b64e 4647
e46479f8 4648 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 4649 ++vcpu->stat.insn_emulation;
bbd9b64e 4650 if (r) {
4005996e
AK		 4651 if (emulation_type & EMULTYPE_TRAP_UD)
4652 return EMULATE_FAIL;
a6f177ef 4653 if (reexecute_instruction(vcpu, cr2))
bbd9b64e 4654 return EMULATE_DONE;
6d77dbfc
GN		 4655 if (emulation_type & EMULTYPE_SKIP)
4656 return EMULATE_FAIL;
4657 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4658 }
4659 }
4660
ba8afb6b
GN		 4661 if (emulation_type & EMULTYPE_SKIP) {
4662 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.decode.eip);
4663 return EMULATE_DONE;
4664 }
4665
7ae441ea 4666 /* this is needed for vmware backdoor interface to work since it
4d2179e1 4667 changes registers values during IO operation */
7ae441ea
GN		 4668 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
4669 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
4670 memcpy(c->regs, vcpu->arch.regs, sizeof c->regs);
4671 }
4d2179e1 4672
5cd21917 4673restart:
9aabc88f 4674 r = x86_emulate_insn(&vcpu->arch.emulate_ctxt);
bbd9b64e 4675
775fde86
JR		 4676 if (r == EMULATION_INTERCEPTED)
4677 return EMULATE_DONE;
4678
d2ddd1c4 4679 if (r == EMULATION_FAILED) {
a6f177ef 4680 if (reexecute_instruction(vcpu, cr2))
c3cd7ffa
GN		 4681 return EMULATE_DONE;
4682
6d77dbfc 4683 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4684 }
4685
da9cb575 4686 if (vcpu->arch.emulate_ctxt.have_exception) {
54b8486f 4687 inject_emulated_exception(vcpu);
d2ddd1c4
GN		 4688 r = EMULATE_DONE;
4689 } else if (vcpu->arch.pio.count) {
3457e419
GN		 4690 if (!vcpu->arch.pio.in)
4691 vcpu->arch.pio.count = 0;
7ae441ea
GN		 4692 else
4693 writeback = false;
e85d28f8 4694 r = EMULATE_DO_MMIO;
7ae441ea
GN		 4695 } else if (vcpu->mmio_needed) {
4696 if (!vcpu->mmio_is_write)
4697 writeback = false;
e85d28f8 4698 r = EMULATE_DO_MMIO;
7ae441ea 4699 } else if (r == EMULATION_RESTART)
5cd21917 4700 goto restart;
d2ddd1c4
GN		 4701 else
4702 r = EMULATE_DONE;
f850e2e6 4703
7ae441ea
GN		 4704 if (writeback) {
4705 toggle_interruptibility(vcpu,
4706 vcpu->arch.emulate_ctxt.interruptibility);
4707 kvm_set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
4708 kvm_make_request(KVM_REQ_EVENT, vcpu);
4709 memcpy(vcpu->arch.regs, c->regs, sizeof c->regs);
4710 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
4711 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.eip);
4712 } else
4713 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 4714
4715 return r;
de7d789a 4716}
51d8b661 4717EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 4718
cf8f70bf 4719int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 4720{
cf8f70bf 4721 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 4722 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
4723 size, port, &val, 1);
cf8f70bf 4724 /* do not return to emulator after return from userspace */
7972995b 4725 vcpu->arch.pio.count = 0;
de7d789a
CO		 4726 return ret;
4727}
cf8f70bf 4728EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 4729
8cfdc000
ZA		 4730static void tsc_bad(void *info)
4731{
0a3aee0d 4732 __this_cpu_write(cpu_tsc_khz, 0);
8cfdc000
ZA		 4733}
4734
4735static void tsc_khz_changed(void *data)
c8076604 4736{
8cfdc000
ZA		 4737 struct cpufreq_freqs *freq = data;
4738 unsigned long khz = 0;
4739
4740 if (data)
4741 khz = freq->new;
4742 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4743 khz = cpufreq_quick_get(raw_smp_processor_id());
4744 if (!khz)
4745 khz = tsc_khz;
0a3aee0d 4746 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 4747}
4748
c8076604
GH		 4749static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
4750 void *data)
4751{
4752 struct cpufreq_freqs *freq = data;
4753 struct kvm *kvm;
4754 struct kvm_vcpu *vcpu;
4755 int i, send_ipi = 0;
4756
8cfdc000
ZA		 4757 /*
4758 * We allow guests to temporarily run on slowing clocks,
4759 * provided we notify them after, or to run on accelerating
4760 * clocks, provided we notify them before. Thus time never
4761 * goes backwards.
4762 *
4763 * However, we have a problem. We can't atomically update
4764 * the frequency of a given CPU from this function; it is
4765 * merely a notifier, which can be called from any CPU.
4766 * Changing the TSC frequency at arbitrary points in time
4767 * requires a recomputation of local variables related to
4768 * the TSC for each VCPU. We must flag these local variables
4769 * to be updated and be sure the update takes place with the
4770 * new frequency before any guests proceed.
4771 *
4772 * Unfortunately, the combination of hotplug CPU and frequency
4773 * change creates an intractable locking scenario; the order
4774 * of when these callouts happen is undefined with respect to
4775 * CPU hotplug, and they can race with each other. As such,
4776 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
4777 * undefined; you can actually have a CPU frequency change take
4778 * place in between the computation of X and the setting of the
4779 * variable. To protect against this problem, all updates of
4780 * the per_cpu tsc_khz variable are done in an interrupt
4781 * protected IPI, and all callers wishing to update the value
4782 * must wait for a synchronous IPI to complete (which is trivial
4783 * if the caller is on the CPU already). This establishes the
4784 * necessary total order on variable updates.
4785 *
4786 * Note that because a guest time update may take place
4787 * anytime after the setting of the VCPU's request bit, the
4788 * correct TSC value must be set before the request. However,
4789 * to ensure the update actually makes it to any guest which
4790 * starts running in hardware virtualization between the set
4791 * and the acquisition of the spinlock, we must also ping the
4792 * CPU after setting the request bit.
4793 *
4794 */
4795
c8076604
GH		 4796 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
4797 return 0;
4798 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
4799 return 0;
8cfdc000
ZA		 4800
4801 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 4802
e935b837 4803 raw_spin_lock(&kvm_lock);
c8076604 4804 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 4805 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 4806 if (vcpu->cpu != freq->cpu)
4807 continue;
c285545f 4808 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 4809 if (vcpu->cpu != smp_processor_id())
8cfdc000 4810 send_ipi = 1;
c8076604
GH		 4811 }
4812 }
e935b837 4813 raw_spin_unlock(&kvm_lock);
c8076604
GH		 4814
4815 if (freq->old < freq->new && send_ipi) {
4816 /*
4817 * We upscale the frequency. Must make the guest
4818 * doesn't see old kvmclock values while running with
4819 * the new frequency, otherwise we risk the guest sees
4820 * time go backwards.
4821 *
4822 * In case we update the frequency for another cpu
4823 * (which might be in guest context) send an interrupt
4824 * to kick the cpu out of guest context. Next time
4825 * guest context is entered kvmclock will be updated,
4826 * so the guest will not see stale values.
4827 */
8cfdc000 4828 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 4829 }
4830 return 0;
4831}
4832
4833static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 4834 .notifier_call = kvmclock_cpufreq_notifier
4835};
4836
4837static int kvmclock_cpu_notifier(struct notifier_block *nfb,
4838 unsigned long action, void *hcpu)
4839{
4840 unsigned int cpu = (unsigned long)hcpu;
4841
4842 switch (action) {
4843 case CPU_ONLINE:
4844 case CPU_DOWN_FAILED:
4845 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
4846 break;
4847 case CPU_DOWN_PREPARE:
4848 smp_call_function_single(cpu, tsc_bad, NULL, 1);
4849 break;
4850 }
4851 return NOTIFY_OK;
4852}
4853
4854static struct notifier_block kvmclock_cpu_notifier_block = {
4855 .notifier_call = kvmclock_cpu_notifier,
4856 .priority = -INT_MAX
c8076604
GH		 4857};
4858
b820cc0c
ZA		 4859static void kvm_timer_init(void)
4860{
4861 int cpu;
4862
c285545f 4863 max_tsc_khz = tsc_khz;
8cfdc000 4864 register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
b820cc0c 4865 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 4866#ifdef CONFIG_CPU_FREQ
4867 struct cpufreq_policy policy;
4868 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 4869 cpu = get_cpu();
4870 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 4871 if (policy.cpuinfo.max_freq)
4872 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 4873 put_cpu();
c285545f 4874#endif
b820cc0c
ZA		 4875 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
4876 CPUFREQ_TRANSITION_NOTIFIER);
4877 }
c285545f 4878 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 4879 for_each_online_cpu(cpu)
4880 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
b820cc0c
ZA		 4881}
4882
ff9d07a0
ZY		 4883static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
4884
4885static int kvm_is_in_guest(void)
4886{
4887 return percpu_read(current_vcpu) != NULL;
4888}
4889
4890static int kvm_is_user_mode(void)
4891{
4892 int user_mode = 3;
dcf46b94 4893
ff9d07a0
ZY		 4894 if (percpu_read(current_vcpu))
4895 user_mode = kvm_x86_ops->get_cpl(percpu_read(current_vcpu));
dcf46b94 4896
ff9d07a0
ZY		 4897 return user_mode != 0;
4898}
4899
4900static unsigned long kvm_get_guest_ip(void)
4901{
4902 unsigned long ip = 0;
dcf46b94 4903
ff9d07a0
ZY		 4904 if (percpu_read(current_vcpu))
4905 ip = kvm_rip_read(percpu_read(current_vcpu));
dcf46b94 4906
ff9d07a0
ZY		 4907 return ip;
4908}
4909
4910static struct perf_guest_info_callbacks kvm_guest_cbs = {
4911 .is_in_guest = kvm_is_in_guest,
4912 .is_user_mode = kvm_is_user_mode,
4913 .get_guest_ip = kvm_get_guest_ip,
4914};
4915
4916void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
4917{
4918 percpu_write(current_vcpu, vcpu);
4919}
4920EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
4921
4922void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
4923{
4924 percpu_write(current_vcpu, NULL);
4925}
4926EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
4927
f8c16bba 4928int kvm_arch_init(void *opaque)
043405e1 4929{
b820cc0c 4930 int r;
f8c16bba
ZX		 4931 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
4932
f8c16bba
ZX		 4933 if (kvm_x86_ops) {
4934 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 4935 r = -EEXIST;
4936 goto out;
f8c16bba
ZX		 4937 }
4938
4939 if (!ops->cpu_has_kvm_support()) {
4940 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 4941 r = -EOPNOTSUPP;
4942 goto out;
f8c16bba
ZX		 4943 }
4944 if (ops->disabled_by_bios()) {
4945 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 4946 r = -EOPNOTSUPP;
4947 goto out;
f8c16bba
ZX		 4948 }
4949
97db56ce
AK		 4950 r = kvm_mmu_module_init();
4951 if (r)
4952 goto out;
4953
4954 kvm_init_msr_list();
4955
f8c16bba 4956 kvm_x86_ops = ops;
56c6d28a 4957 kvm_mmu_set_nonpresent_ptes(0ull, 0ull);
7b52345e 4958 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 4959 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 4960
b820cc0c 4961 kvm_timer_init();
c8076604 4962
ff9d07a0
ZY		 4963 perf_register_guest_info_callbacks(&kvm_guest_cbs);
4964
2acf923e
DC		 4965 if (cpu_has_xsave)
4966 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
4967
f8c16bba 4968 return 0;
56c6d28a
ZX		 4969
4970out:
56c6d28a 4971 return r;
043405e1 4972}
8776e519 4973
f8c16bba
ZX		 4974void kvm_arch_exit(void)
4975{
ff9d07a0
ZY		 4976 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
4977
888d256e
JK		 4978 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4979 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
4980 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 4981 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
f8c16bba 4982 kvm_x86_ops = NULL;
56c6d28a
ZX		 4983 kvm_mmu_module_exit();
4984}
f8c16bba 4985
8776e519
HB		 4986int kvm_emulate_halt(struct kvm_vcpu *vcpu)
4987{
4988 ++vcpu->stat.halt_exits;
4989 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 4990 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 4991 return 1;
4992 } else {
4993 vcpu->run->exit_reason = KVM_EXIT_HLT;
4994 return 0;
4995 }
4996}
4997EXPORT_SYMBOL_GPL(kvm_emulate_halt);
4998
2f333bcb
MT		 4999static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0,
5000 unsigned long a1)
5001{
5002 if (is_long_mode(vcpu))
5003 return a0;
5004 else
5005 return a0 | ((gpa_t)a1 << 32);
5006}
5007
55cd8e5a
GN		 5008int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
5009{
5010 u64 param, ingpa, outgpa, ret;
5011 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
5012 bool fast, longmode;
5013 int cs_db, cs_l;
5014
5015 /*
5016 * hypercall generates UD from non zero cpl and real mode
5017 * per HYPER-V spec
5018 */
3eeb3288 5019 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 5020 kvm_queue_exception(vcpu, UD_VECTOR);
5021 return 0;
5022 }
5023
5024 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5025 longmode = is_long_mode(vcpu) && cs_l == 1;
5026
5027 if (!longmode) {
ccd46936
GN		 5028 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
5029 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
5030 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
5031 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
5032 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
5033 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 5034 }
5035#ifdef CONFIG_X86_64
5036 else {
5037 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
5038 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
5039 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
5040 }
5041#endif
5042
5043 code = param & 0xffff;
5044 fast = (param >> 16) & 0x1;
5045 rep_cnt = (param >> 32) & 0xfff;
5046 rep_idx = (param >> 48) & 0xfff;
5047
5048 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
5049
c25bc163
GN		 5050 switch (code) {
5051 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
5052 kvm_vcpu_on_spin(vcpu);
5053 break;
5054 default:
5055 res = HV_STATUS_INVALID_HYPERCALL_CODE;
5056 break;
5057 }
55cd8e5a
GN		 5058
5059 ret = res | (((u64)rep_done & 0xfff) << 32);
5060 if (longmode) {
5061 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5062 } else {
5063 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
5064 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
5065 }
5066
5067 return 1;
5068}
5069
8776e519
HB		 5070int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5071{
5072 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 5073 int r = 1;
8776e519 5074
55cd8e5a
GN		 5075 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5076 return kvm_hv_hypercall(vcpu);
5077
5fdbf976
MT		 5078 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5079 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5080 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5081 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5082 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 5083
229456fc 5084 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 5085
8776e519
HB		 5086 if (!is_long_mode(vcpu)) {
5087 nr &= 0xFFFFFFFF;
5088 a0 &= 0xFFFFFFFF;
5089 a1 &= 0xFFFFFFFF;
5090 a2 &= 0xFFFFFFFF;
5091 a3 &= 0xFFFFFFFF;
5092 }
5093
07708c4a
JK		 5094 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5095 ret = -KVM_EPERM;
5096 goto out;
5097 }
5098
8776e519 5099 switch (nr) {
b93463aa
AK		 5100 case KVM_HC_VAPIC_POLL_IRQ:
5101 ret = 0;
5102 break;
2f333bcb
MT		 5103 case KVM_HC_MMU_OP:
5104 r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret);
5105 break;
8776e519
HB		 5106 default:
5107 ret = -KVM_ENOSYS;
5108 break;
5109 }
07708c4a 5110out:
5fdbf976 5111 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 5112 ++vcpu->stat.hypercalls;
2f333bcb 5113 return r;
8776e519
HB		 5114}
5115EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5116
d6aa1000 5117int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 5118{
d6aa1000 5119 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 5120 char instruction[3];
5fdbf976 5121 unsigned long rip = kvm_rip_read(vcpu);
8776e519 5122
8776e519
HB		 5123 /*
5124 * Blow out the MMU to ensure that no other VCPU has an active mapping
5125 * to ensure that the updated hypercall appears atomically across all
5126 * VCPUs.
5127 */
5128 kvm_mmu_zap_all(vcpu->kvm);
5129
8776e519 5130 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 5131
0f65dd70
AK		 5132 return emulator_write_emulated(&vcpu->arch.emulate_ctxt,
5133 rip, instruction, 3, NULL);
8776e519
HB		 5134}
5135
07716717
DK		 5136static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)
5137{
ad312c7c
ZX		 5138 struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];
5139 int j, nent = vcpu->arch.cpuid_nent;
07716717
DK		 5140
5141 e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;
5142 /* when no next entry is found, the current entry[i] is reselected */
0fdf8e59 5143 for (j = i + 1; ; j = (j + 1) % nent) {
ad312c7c 5144 struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j];
07716717
DK		 5145 if (ej->function == e->function) {
5146 ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
5147 return j;
5148 }
5149 }
5150 return 0; /* silence gcc, even though control never reaches here */
5151}
5152
5153/* find an entry with matching function, matching index (if needed), and that
5154 * should be read next (if it's stateful) */
5155static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e,
5156 u32 function, u32 index)
5157{
5158 if (e->function != function)
5159 return 0;
5160 if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index)
5161 return 0;
5162 if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) &&
19355475 5163 !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT))
07716717
DK		 5164 return 0;
5165 return 1;
5166}
5167
d8017474
AG		 5168struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
5169 u32 function, u32 index)
8776e519
HB		 5170{
5171 int i;
d8017474 5172 struct kvm_cpuid_entry2 *best = NULL;
8776e519 5173
ad312c7c 5174 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
d8017474
AG		 5175 struct kvm_cpuid_entry2 *e;
5176
ad312c7c 5177 e = &vcpu->arch.cpuid_entries[i];
07716717
DK		 5178 if (is_matching_cpuid_entry(e, function, index)) {
5179 if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC)
5180 move_to_next_stateful_cpuid_entry(vcpu, i);
8776e519
HB		 5181 best = e;
5182 break;
5183 }
8776e519 5184 }
d8017474
AG		 5185 return best;
5186}
0e851880 5187EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry);
d8017474 5188
82725b20
DE		 5189int cpuid_maxphyaddr(struct kvm_vcpu *vcpu)
5190{
5191 struct kvm_cpuid_entry2 *best;
5192
f7a71197
AK		 5193 best = kvm_find_cpuid_entry(vcpu, 0x80000000, 0);
5194 if (!best || best->eax < 0x80000008)
5195 goto not_found;
82725b20
DE		 5196 best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0);
5197 if (best)
5198 return best->eax & 0xff;
f7a71197 5199not_found:
82725b20
DE		 5200 return 36;
5201}
5202
bd22f5cf
AP		 5203/*
5204 * If no match is found, check whether we exceed the vCPU's limit
5205 * and return the content of the highest valid _standard_ leaf instead.
5206 * This is to satisfy the CPUID specification.
5207 */
5208static struct kvm_cpuid_entry2* check_cpuid_limit(struct kvm_vcpu *vcpu,
5209 u32 function, u32 index)
5210{
5211 struct kvm_cpuid_entry2 *maxlevel;
5212
5213 maxlevel = kvm_find_cpuid_entry(vcpu, function & 0x80000000, 0);
5214 if (!maxlevel || maxlevel->eax >= function)
5215 return NULL;
5216 if (function & 0x80000000) {
5217 maxlevel = kvm_find_cpuid_entry(vcpu, 0, 0);
5218 if (!maxlevel)
5219 return NULL;
5220 }
5221 return kvm_find_cpuid_entry(vcpu, maxlevel->eax, index);
5222}
5223
d8017474
AG		 5224void kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
5225{
5226 u32 function, index;
5227 struct kvm_cpuid_entry2 *best;
5228
5229 function = kvm_register_read(vcpu, VCPU_REGS_RAX);
5230 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5231 kvm_register_write(vcpu, VCPU_REGS_RAX, 0);
5232 kvm_register_write(vcpu, VCPU_REGS_RBX, 0);
5233 kvm_register_write(vcpu, VCPU_REGS_RCX, 0);
5234 kvm_register_write(vcpu, VCPU_REGS_RDX, 0);
5235 best = kvm_find_cpuid_entry(vcpu, function, index);
bd22f5cf
AP		 5236
5237 if (!best)
5238 best = check_cpuid_limit(vcpu, function, index);
5239
8776e519 5240 if (best) {
5fdbf976
MT		 5241 kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax);
5242 kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx);
5243 kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx);
5244 kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx);
8776e519 5245 }
8776e519 5246 kvm_x86_ops->skip_emulated_instruction(vcpu);
229456fc
MT		 5247 trace_kvm_cpuid(function,
5248 kvm_register_read(vcpu, VCPU_REGS_RAX),
5249 kvm_register_read(vcpu, VCPU_REGS_RBX),
5250 kvm_register_read(vcpu, VCPU_REGS_RCX),
5251 kvm_register_read(vcpu, VCPU_REGS_RDX));
8776e519
HB		 5252}
5253EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
d0752060 5254
b6c7a5dc
HB		 5255/*
5256 * Check if userspace requested an interrupt window, and that the
5257 * interrupt window is open.
5258 *
5259 * No need to exit to userspace if we already have an interrupt queued.
5260 */
851ba692 5261static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 5262{
8061823a 5263 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 5264 vcpu->run->request_interrupt_window &&
5df56646 5265 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 5266}
5267
851ba692 5268static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 5269{
851ba692
AK		 5270 struct kvm_run *kvm_run = vcpu->run;
5271
91586a3b 5272 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 5273 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 5274 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 5275 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 5276 kvm_run->ready_for_interrupt_injection = 1;
4531220b 5277 else
b6c7a5dc 5278 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 5279 kvm_arch_interrupt_allowed(vcpu) &&
5280 !kvm_cpu_has_interrupt(vcpu) &&
5281 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 5282}
5283
b93463aa
AK		 5284static void vapic_enter(struct kvm_vcpu *vcpu)
5285{
5286 struct kvm_lapic *apic = vcpu->arch.apic;
5287 struct page *page;
5288
5289 if (!apic || !apic->vapic_addr)
5290 return;
5291
5292 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
72dc67a6
IE		 5293
5294 vcpu->arch.apic->vapic_page = page;
b93463aa
AK		 5295}
5296
5297static void vapic_exit(struct kvm_vcpu *vcpu)
5298{
5299 struct kvm_lapic *apic = vcpu->arch.apic;
f656ce01 5300 int idx;
b93463aa
AK		 5301
5302 if (!apic || !apic->vapic_addr)
5303 return;
5304
f656ce01 5305 idx = srcu_read_lock(&vcpu->kvm->srcu);
b93463aa
AK		 5306 kvm_release_page_dirty(apic->vapic_page);
5307 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f656ce01 5308 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 5309}
5310
95ba8273
GN		 5311static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5312{
5313 int max_irr, tpr;
5314
5315 if (!kvm_x86_ops->update_cr8_intercept)
5316 return;
5317
88c808fd
AK		 5318 if (!vcpu->arch.apic)
5319 return;
5320
8db3baa2
GN		 5321 if (!vcpu->arch.apic->vapic_addr)
5322 max_irr = kvm_lapic_find_highest_irr(vcpu);
5323 else
5324 max_irr = -1;
95ba8273
GN		 5325
5326 if (max_irr != -1)
5327 max_irr >>= 4;
5328
5329 tpr = kvm_lapic_get_cr8(vcpu);
5330
5331 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5332}
5333
851ba692 5334static void inject_pending_event(struct kvm_vcpu *vcpu)
95ba8273
GN		 5335{
5336 /* try to reinject previous events if any */
b59bb7bd 5337 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 5338 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5339 vcpu->arch.exception.has_error_code,
5340 vcpu->arch.exception.error_code);
b59bb7bd
GN		 5341 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5342 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 5343 vcpu->arch.exception.error_code,
5344 vcpu->arch.exception.reinject);
b59bb7bd
GN		 5345 return;
5346 }
5347
95ba8273
GN		 5348 if (vcpu->arch.nmi_injected) {
5349 kvm_x86_ops->set_nmi(vcpu);
5350 return;
5351 }
5352
5353 if (vcpu->arch.interrupt.pending) {
66fd3f7f 5354 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5355 return;
5356 }
5357
5358 /* try to inject new event if pending */
5359 if (vcpu->arch.nmi_pending) {
5360 if (kvm_x86_ops->nmi_allowed(vcpu)) {
5361 vcpu->arch.nmi_pending = false;
5362 vcpu->arch.nmi_injected = true;
5363 kvm_x86_ops->set_nmi(vcpu);
5364 }
5365 } else if (kvm_cpu_has_interrupt(vcpu)) {
5366 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 5367 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5368 false);
5369 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5370 }
5371 }
5372}
5373
2acf923e
DC		 5374static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
5375{
5376 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
5377 !vcpu->guest_xcr0_loaded) {
5378 /* kvm_set_xcr() also depends on this */
5379 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
5380 vcpu->guest_xcr0_loaded = 1;
5381 }
5382}
5383
5384static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
5385{
5386 if (vcpu->guest_xcr0_loaded) {
5387 if (vcpu->arch.xcr0 != host_xcr0)
5388 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
5389 vcpu->guest_xcr0_loaded = 0;
5390 }
5391}
5392
851ba692 5393static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 5394{
5395 int r;
1499e54a 5396 bool nmi_pending;
6a8b1d13 5397 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 5398 vcpu->run->request_interrupt_window;
b6c7a5dc 5399
3e007509 5400 if (vcpu->requests) {
a8eeb04a 5401 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 5402 kvm_mmu_unload(vcpu);
a8eeb04a 5403 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 5404 __kvm_migrate_timers(vcpu);
34c238a1
ZA		 5405 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
5406 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 5407 if (unlikely(r))
5408 goto out;
5409 }
a8eeb04a 5410 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 5411 kvm_mmu_sync_roots(vcpu);
a8eeb04a 5412 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
d4acf7e7 5413 kvm_x86_ops->tlb_flush(vcpu);
a8eeb04a 5414 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 5415 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 5416 r = 0;
5417 goto out;
5418 }
a8eeb04a 5419 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 5420 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 5421 r = 0;
5422 goto out;
5423 }
a8eeb04a 5424 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 5425 vcpu->fpu_active = 0;
5426 kvm_x86_ops->fpu_deactivate(vcpu);
5427 }
af585b92
GN		 5428 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
5429 /* Page is swapped out. Do synthetic halt */
5430 vcpu->arch.apf.halted = true;
5431 r = 1;
5432 goto out;
5433 }
2f52d58c 5434 }
b93463aa 5435
3e007509
AK		 5436 r = kvm_mmu_reload(vcpu);
5437 if (unlikely(r))
5438 goto out;
5439
1499e54a
GN		 5440 /*
5441 * An NMI can be injected between local nmi_pending read and
5442 * vcpu->arch.nmi_pending read inside inject_pending_event().
5443 * But in that case, KVM_REQ_EVENT will be set, which makes
5444 * the race described above benign.
5445 */
5446 nmi_pending = ACCESS_ONCE(vcpu->arch.nmi_pending);
5447
b463a6f7
AK		 5448 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
5449 inject_pending_event(vcpu);
5450
5451 /* enable NMI/IRQ window open exits if needed */
1499e54a 5452 if (nmi_pending)
b463a6f7
AK		 5453 kvm_x86_ops->enable_nmi_window(vcpu);
5454 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
5455 kvm_x86_ops->enable_irq_window(vcpu);
5456
5457 if (kvm_lapic_enabled(vcpu)) {
5458 update_cr8_intercept(vcpu);
5459 kvm_lapic_sync_to_vapic(vcpu);
5460 }
5461 }
5462
b6c7a5dc
HB		 5463 preempt_disable();
5464
5465 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 5466 if (vcpu->fpu_active)
5467 kvm_load_guest_fpu(vcpu);
2acf923e 5468 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 5469
6b7e2d09
XG		 5470 vcpu->mode = IN_GUEST_MODE;
5471
5472 /* We should set ->mode before check ->requests,
5473 * see the comment in make_all_cpus_request.
5474 */
5475 smp_mb();
b6c7a5dc 5476
d94e1dc9 5477 local_irq_disable();
32f88400 5478
6b7e2d09 5479 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 5480 || need_resched() || signal_pending(current)) {
6b7e2d09 5481 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 5482 smp_wmb();
6c142801
AK		 5483 local_irq_enable();
5484 preempt_enable();
b463a6f7 5485 kvm_x86_ops->cancel_injection(vcpu);
6c142801
AK		 5486 r = 1;
5487 goto out;
5488 }
5489
f656ce01 5490 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
3200f405 5491
b6c7a5dc
HB		 5492 kvm_guest_enter();
5493
42dbaa5a 5494 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 5495 set_debugreg(0, 7);
5496 set_debugreg(vcpu->arch.eff_db[0], 0);
5497 set_debugreg(vcpu->arch.eff_db[1], 1);
5498 set_debugreg(vcpu->arch.eff_db[2], 2);
5499 set_debugreg(vcpu->arch.eff_db[3], 3);
5500 }
b6c7a5dc 5501
229456fc 5502 trace_kvm_entry(vcpu->vcpu_id);
851ba692 5503 kvm_x86_ops->run(vcpu);
b6c7a5dc 5504
24f1e32c
FW		 5505 /*
5506 * If the guest has used debug registers, at least dr7
5507 * will be disabled while returning to the host.
5508 * If we don't have active breakpoints in the host, we don't
5509 * care about the messed up debug address registers. But if
5510 * we have some of them active, restore the old state.
5511 */
59d8eb53 5512 if (hw_breakpoint_active())
24f1e32c 5513 hw_breakpoint_restore();
42dbaa5a 5514
1d5f066e
ZA		 5515 kvm_get_msr(vcpu, MSR_IA32_TSC, &vcpu->arch.last_guest_tsc);
5516
6b7e2d09 5517 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 5518 smp_wmb();
b6c7a5dc
HB		 5519 local_irq_enable();
5520
5521 ++vcpu->stat.exits;
5522
5523 /*
5524 * We must have an instruction between local_irq_enable() and
5525 * kvm_guest_exit(), so the timer interrupt isn't delayed by
5526 * the interrupt shadow. The stat.exits increment will do nicely.
5527 * But we need to prevent reordering, hence this barrier():
5528 */
5529 barrier();
5530
5531 kvm_guest_exit();
5532
5533 preempt_enable();
5534
f656ce01 5535 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 5536
b6c7a5dc
HB		 5537 /*
5538 * Profile KVM exit RIPs:
5539 */
5540 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 5541 unsigned long rip = kvm_rip_read(vcpu);
5542 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 5543 }
5544
298101da 5545
b93463aa
AK		 5546 kvm_lapic_sync_from_vapic(vcpu);
5547
851ba692 5548 r = kvm_x86_ops->handle_exit(vcpu);
d7690175
MT		 5549out:
5550 return r;
5551}
b6c7a5dc 5552
09cec754 5553
851ba692 5554static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 5555{
5556 int r;
f656ce01 5557 struct kvm *kvm = vcpu->kvm;
d7690175
MT		 5558
5559 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
1b10bf31
JK		 5560 pr_debug("vcpu %d received sipi with vector # %x\n",
5561 vcpu->vcpu_id, vcpu->arch.sipi_vector);
d7690175 5562 kvm_lapic_reset(vcpu);
5f179287 5563 r = kvm_arch_vcpu_reset(vcpu);
d7690175
MT		 5564 if (r)
5565 return r;
5566 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 5567 }
5568
f656ce01 5569 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175
MT		 5570 vapic_enter(vcpu);
5571
5572 r = 1;
5573 while (r > 0) {
af585b92
GN		 5574 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
5575 !vcpu->arch.apf.halted)
851ba692 5576 r = vcpu_enter_guest(vcpu);
d7690175 5577 else {
f656ce01 5578 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 5579 kvm_vcpu_block(vcpu);
f656ce01 5580 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
a8eeb04a 5581 if (kvm_check_request(KVM_REQ_UNHALT, vcpu))
09cec754
GN		 5582 {
5583 switch(vcpu->arch.mp_state) {
5584 case KVM_MP_STATE_HALTED:
d7690175 5585 vcpu->arch.mp_state =
09cec754
GN		 5586 KVM_MP_STATE_RUNNABLE;
5587 case KVM_MP_STATE_RUNNABLE:
af585b92 5588 vcpu->arch.apf.halted = false;
09cec754
GN		 5589 break;
5590 case KVM_MP_STATE_SIPI_RECEIVED:
5591 default:
5592 r = -EINTR;
5593 break;
5594 }
5595 }
d7690175
MT		 5596 }
5597
09cec754
GN		 5598 if (r <= 0)
5599 break;
5600
5601 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
5602 if (kvm_cpu_has_pending_timer(vcpu))
5603 kvm_inject_pending_timer_irqs(vcpu);
5604
851ba692 5605 if (dm_request_for_irq_injection(vcpu)) {
09cec754 5606 r = -EINTR;
851ba692 5607 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5608 ++vcpu->stat.request_irq_exits;
5609 }
af585b92
GN		 5610
5611 kvm_check_async_pf_completion(vcpu);
5612
09cec754
GN		 5613 if (signal_pending(current)) {
5614 r = -EINTR;
851ba692 5615 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5616 ++vcpu->stat.signal_exits;
5617 }
5618 if (need_resched()) {
f656ce01 5619 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
09cec754 5620 kvm_resched(vcpu);
f656ce01 5621 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 5622 }
b6c7a5dc
HB		 5623 }
5624
f656ce01 5625 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc 5626
b93463aa
AK		 5627 vapic_exit(vcpu);
5628
b6c7a5dc
HB		 5629 return r;
5630}
5631
5287f194
AK		 5632static int complete_mmio(struct kvm_vcpu *vcpu)
5633{
5634 struct kvm_run *run = vcpu->run;
5635 int r;
5636
5637 if (!(vcpu->arch.pio.count || vcpu->mmio_needed))
5638 return 1;
5639
5640 if (vcpu->mmio_needed) {
5287f194 5641 vcpu->mmio_needed = 0;
cef4dea0 5642 if (!vcpu->mmio_is_write)
0004c7c2
GN		 5643 memcpy(vcpu->mmio_data + vcpu->mmio_index,
5644 run->mmio.data, 8);
cef4dea0
AK		 5645 vcpu->mmio_index += 8;
5646 if (vcpu->mmio_index < vcpu->mmio_size) {
5647 run->exit_reason = KVM_EXIT_MMIO;
5648 run->mmio.phys_addr = vcpu->mmio_phys_addr + vcpu->mmio_index;
5649 memcpy(run->mmio.data, vcpu->mmio_data + vcpu->mmio_index, 8);
5650 run->mmio.len = min(vcpu->mmio_size - vcpu->mmio_index, 8);
5651 run->mmio.is_write = vcpu->mmio_is_write;
5652 vcpu->mmio_needed = 1;
5653 return 0;
5654 }
5655 if (vcpu->mmio_is_write)
5656 return 1;
5657 vcpu->mmio_read_completed = 1;
5287f194
AK		 5658 }
5659 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5660 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
5661 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
5662 if (r != EMULATE_DONE)
5663 return 0;
5664 return 1;
5665}
5666
b6c7a5dc
HB		 5667int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
5668{
5669 int r;
5670 sigset_t sigsaved;
5671
e5c30142
AK		 5672 if (!tsk_used_math(current) && init_fpu(current))
5673 return -ENOMEM;
5674
ac9f6dc0
AK		 5675 if (vcpu->sigset_active)
5676 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
5677
a4535290 5678 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 5679 kvm_vcpu_block(vcpu);
d7690175 5680 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 5681 r = -EAGAIN;
5682 goto out;
b6c7a5dc
HB		 5683 }
5684
b6c7a5dc 5685 /* re-sync apic's tpr */
eea1cff9
AP		 5686 if (!irqchip_in_kernel(vcpu->kvm)) {
5687 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
5688 r = -EINVAL;
5689 goto out;
5690 }
5691 }
b6c7a5dc 5692
5287f194
AK		 5693 r = complete_mmio(vcpu);
5694 if (r <= 0)
5695 goto out;
5696
5fdbf976
MT		 5697 if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL)
5698 kvm_register_write(vcpu, VCPU_REGS_RAX,
5699 kvm_run->hypercall.ret);
b6c7a5dc 5700
851ba692 5701 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 5702
5703out:
f1d86e46 5704 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 5705 if (vcpu->sigset_active)
5706 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
5707
b6c7a5dc
HB		 5708 return r;
5709}
5710
5711int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5712{
7ae441ea
GN		 5713 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
5714 /*
5715 * We are here if userspace calls get_regs() in the middle of
5716 * instruction emulation. Registers state needs to be copied
5717 * back from emulation context to vcpu. Usrapace shouldn't do
5718 * that usually, but some bad designed PV devices (vmware
5719 * backdoor interface) need this to work
5720 */
5721 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
5722 memcpy(vcpu->arch.regs, c->regs, sizeof c->regs);
5723 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5724 }
5fdbf976
MT		 5725 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
5726 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
5727 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
5728 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
5729 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
5730 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
5731 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
5732 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 5733#ifdef CONFIG_X86_64
5fdbf976
MT		 5734 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
5735 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
5736 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
5737 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
5738 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
5739 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
5740 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
5741 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 5742#endif
5743
5fdbf976 5744 regs->rip = kvm_rip_read(vcpu);
91586a3b 5745 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 5746
b6c7a5dc
HB		 5747 return 0;
5748}
5749
5750int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5751{
7ae441ea
GN		 5752 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
5753 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5754
5fdbf976
MT		 5755 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
5756 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
5757 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
5758 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
5759 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
5760 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
5761 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
5762 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 5763#ifdef CONFIG_X86_64
5fdbf976
MT		 5764 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
5765 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
5766 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
5767 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
5768 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
5769 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
5770 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
5771 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 5772#endif
5773
5fdbf976 5774 kvm_rip_write(vcpu, regs->rip);
91586a3b 5775 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 5776
b4f14abd
JK		 5777 vcpu->arch.exception.pending = false;
5778
3842d135
AK		 5779 kvm_make_request(KVM_REQ_EVENT, vcpu);
5780
b6c7a5dc
HB		 5781 return 0;
5782}
5783
b6c7a5dc
HB		 5784void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
5785{
5786 struct kvm_segment cs;
5787
3e6e0aab 5788 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 5789 *db = cs.db;
5790 *l = cs.l;
5791}
5792EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
5793
5794int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
5795 struct kvm_sregs *sregs)
5796{
89a27f4d 5797 struct desc_ptr dt;
b6c7a5dc 5798
3e6e0aab
GT		 5799 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5800 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5801 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5802 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5803 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5804 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 5805
3e6e0aab
GT		 5806 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5807 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 5808
5809 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 5810 sregs->idt.limit = dt.size;
5811 sregs->idt.base = dt.address;
b6c7a5dc 5812 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 5813 sregs->gdt.limit = dt.size;
5814 sregs->gdt.base = dt.address;
b6c7a5dc 5815
4d4ec087 5816 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 5817 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 5818 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 5819 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 5820 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 5821 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 5822 sregs->apic_base = kvm_get_apic_base(vcpu);
5823
923c61bb 5824 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 5825
36752c9b 5826 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 5827 set_bit(vcpu->arch.interrupt.nr,
5828 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 5829
b6c7a5dc
HB		 5830 return 0;
5831}
5832
62d9f0db
MT		 5833int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
5834 struct kvm_mp_state *mp_state)
5835{
62d9f0db 5836 mp_state->mp_state = vcpu->arch.mp_state;
62d9f0db
MT		 5837 return 0;
5838}
5839
5840int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
5841 struct kvm_mp_state *mp_state)
5842{
62d9f0db 5843 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 5844 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 5845 return 0;
5846}
5847
e269fb21
JK		 5848int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason,
5849 bool has_error_code, u32 error_code)
b6c7a5dc 5850{
4d2179e1 5851 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
8ec4722d 5852 int ret;
e01c2426 5853
8ec4722d 5854 init_emulate_ctxt(vcpu);
c697518a 5855
9aabc88f 5856 ret = emulator_task_switch(&vcpu->arch.emulate_ctxt,
e269fb21
JK		 5857 tss_selector, reason, has_error_code,
5858 error_code);
c697518a 5859
c697518a 5860 if (ret)
19d04437 5861 return EMULATE_FAIL;
37817f29 5862
4d2179e1 5863 memcpy(vcpu->arch.regs, c->regs, sizeof c->regs);
95c55886 5864 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.eip);
f6e78475 5865 kvm_set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
3842d135 5866 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 5867 return EMULATE_DONE;
37817f29
IE		 5868}
5869EXPORT_SYMBOL_GPL(kvm_task_switch);
5870
b6c7a5dc
HB		 5871int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
5872 struct kvm_sregs *sregs)
5873{
5874 int mmu_reset_needed = 0;
63f42e02 5875 int pending_vec, max_bits, idx;
89a27f4d 5876 struct desc_ptr dt;
b6c7a5dc 5877
89a27f4d
GN		 5878 dt.size = sregs->idt.limit;
5879 dt.address = sregs->idt.base;
b6c7a5dc 5880 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 5881 dt.size = sregs->gdt.limit;
5882 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 5883 kvm_x86_ops->set_gdt(vcpu, &dt);
5884
ad312c7c 5885 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 5886 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 5887 vcpu->arch.cr3 = sregs->cr3;
aff48baa 5888 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 5889
2d3ad1f4 5890 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 5891
f6801dff 5892 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 5893 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 5894 kvm_set_apic_base(vcpu, sregs->apic_base);
5895
4d4ec087 5896 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 5897 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 5898 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 5899
fc78f519 5900 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 5901 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3ea3aa8c
SY		 5902 if (sregs->cr4 & X86_CR4_OSXSAVE)
5903 update_cpuid(vcpu);
63f42e02
XG		 5904
5905 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 5906 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 5907 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 5908 mmu_reset_needed = 1;
5909 }
63f42e02 5910 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 5911
5912 if (mmu_reset_needed)
5913 kvm_mmu_reset_context(vcpu);
5914
923c61bb
GN		 5915 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
5916 pending_vec = find_first_bit(
5917 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
5918 if (pending_vec < max_bits) {
66fd3f7f 5919 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 5920 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 5921 }
5922
3e6e0aab
GT		 5923 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5924 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5925 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5926 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5927 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5928 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 5929
3e6e0aab
GT		 5930 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5931 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 5932
5f0269f5
ME		 5933 update_cr8_intercept(vcpu);
5934
9c3e4aab 5935 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 5936 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 5937 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 5938 !is_protmode(vcpu))
9c3e4aab
MT		 5939 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
5940
3842d135
AK		 5941 kvm_make_request(KVM_REQ_EVENT, vcpu);
5942
b6c7a5dc
HB		 5943 return 0;
5944}
5945
d0bfb940
JK		 5946int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
5947 struct kvm_guest_debug *dbg)
b6c7a5dc 5948{
355be0b9 5949 unsigned long rflags;
ae675ef0 5950 int i, r;
b6c7a5dc 5951
4f926bf2
JK		 5952 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
5953 r = -EBUSY;
5954 if (vcpu->arch.exception.pending)
2122ff5e 5955 goto out;
4f926bf2
JK		 5956 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
5957 kvm_queue_exception(vcpu, DB_VECTOR);
5958 else
5959 kvm_queue_exception(vcpu, BP_VECTOR);
5960 }
5961
91586a3b
JK		 5962 /*
5963 * Read rflags as long as potentially injected trace flags are still
5964 * filtered out.
5965 */
5966 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 5967
5968 vcpu->guest_debug = dbg->control;
5969 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
5970 vcpu->guest_debug = 0;
5971
5972 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 5973 for (i = 0; i < KVM_NR_DB_REGS; ++i)
5974 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
5975 vcpu->arch.switch_db_regs =
5976 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
5977 } else {
5978 for (i = 0; i < KVM_NR_DB_REGS; i++)
5979 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
5980 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
5981 }
5982
f92653ee
JK		 5983 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
5984 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
5985 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 5986
91586a3b
JK		 5987 /*
5988 * Trigger an rflags update that will inject or remove the trace
5989 * flags.
5990 */
5991 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 5992
355be0b9 5993 kvm_x86_ops->set_guest_debug(vcpu, dbg);
b6c7a5dc 5994
4f926bf2 5995 r = 0;
d0bfb940 5996
2122ff5e 5997out:
b6c7a5dc
HB		 5998
5999 return r;
6000}
6001
8b006791
ZX		 6002/*
6003 * Translate a guest virtual address to a guest physical address.
6004 */
6005int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
6006 struct kvm_translation *tr)
6007{
6008 unsigned long vaddr = tr->linear_address;
6009 gpa_t gpa;
f656ce01 6010 int idx;
8b006791 6011
f656ce01 6012 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 6013 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 6014 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 6015 tr->physical_address = gpa;
6016 tr->valid = gpa != UNMAPPED_GVA;
6017 tr->writeable = 1;
6018 tr->usermode = 0;
8b006791
ZX		 6019
6020 return 0;
6021}
6022
d0752060
HB		 6023int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6024{
98918833
SY		 6025 struct i387_fxsave_struct *fxsave =
6026 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 6027
d0752060
HB		 6028 memcpy(fpu->fpr, fxsave->st_space, 128);
6029 fpu->fcw = fxsave->cwd;
6030 fpu->fsw = fxsave->swd;
6031 fpu->ftwx = fxsave->twd;
6032 fpu->last_opcode = fxsave->fop;
6033 fpu->last_ip = fxsave->rip;
6034 fpu->last_dp = fxsave->rdp;
6035 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
6036
d0752060
HB		 6037 return 0;
6038}
6039
6040int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6041{
98918833
SY		 6042 struct i387_fxsave_struct *fxsave =
6043 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 6044
d0752060
HB		 6045 memcpy(fxsave->st_space, fpu->fpr, 128);
6046 fxsave->cwd = fpu->fcw;
6047 fxsave->swd = fpu->fsw;
6048 fxsave->twd = fpu->ftwx;
6049 fxsave->fop = fpu->last_opcode;
6050 fxsave->rip = fpu->last_ip;
6051 fxsave->rdp = fpu->last_dp;
6052 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
6053
d0752060
HB		 6054 return 0;
6055}
6056
10ab25cd 6057int fx_init(struct kvm_vcpu *vcpu)
d0752060 6058{
10ab25cd
JK		 6059 int err;
6060
6061 err = fpu_alloc(&vcpu->arch.guest_fpu);
6062 if (err)
6063 return err;
6064
98918833 6065 fpu_finit(&vcpu->arch.guest_fpu);
d0752060 6066
2acf923e
DC		 6067 /*
6068 * Ensure guest xcr0 is valid for loading
6069 */
6070 vcpu->arch.xcr0 = XSTATE_FP;
6071
ad312c7c 6072 vcpu->arch.cr0 |= X86_CR0_ET;
10ab25cd
JK		 6073
6074 return 0;
d0752060
HB		 6075}
6076EXPORT_SYMBOL_GPL(fx_init);
6077
98918833
SY		 6078static void fx_free(struct kvm_vcpu *vcpu)
6079{
6080 fpu_free(&vcpu->arch.guest_fpu);
6081}
6082
d0752060
HB		 6083void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
6084{
2608d7a1 6085 if (vcpu->guest_fpu_loaded)
d0752060
HB		 6086 return;
6087
2acf923e
DC		 6088 /*
6089 * Restore all possible states in the guest,
6090 * and assume host would use all available bits.
6091 * Guest xcr0 would be loaded later.
6092 */
6093 kvm_put_guest_xcr0(vcpu);
d0752060 6094 vcpu->guest_fpu_loaded = 1;
7cf30855 6095 unlazy_fpu(current);
98918833 6096 fpu_restore_checking(&vcpu->arch.guest_fpu);
0c04851c 6097 trace_kvm_fpu(1);
d0752060 6098}
d0752060
HB		 6099
6100void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
6101{
2acf923e
DC		 6102 kvm_put_guest_xcr0(vcpu);
6103
d0752060
HB		 6104 if (!vcpu->guest_fpu_loaded)
6105 return;
6106
6107 vcpu->guest_fpu_loaded = 0;
98918833 6108 fpu_save_init(&vcpu->arch.guest_fpu);
f096ed85 6109 ++vcpu->stat.fpu_reload;
a8eeb04a 6110 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
0c04851c 6111 trace_kvm_fpu(0);
d0752060 6112}
e9b11c17
ZX		 6113
6114void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
6115{
12f9a48f 6116 kvmclock_reset(vcpu);
7f1ea208 6117
f5f48ee1 6118 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
98918833 6119 fx_free(vcpu);
e9b11c17
ZX		 6120 kvm_x86_ops->vcpu_free(vcpu);
6121}
6122
6123struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
6124 unsigned int id)
6125{
6755bae8
ZA		 6126 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6127 printk_once(KERN_WARNING
6128 "kvm: SMP vm created on host with unstable TSC; "
6129 "guest TSC will not be reliable\n");
26e5215f
AK		 6130 return kvm_x86_ops->vcpu_create(kvm, id);
6131}
e9b11c17 6132
26e5215f
AK		 6133int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
6134{
6135 int r;
e9b11c17 6136
0bed3b56 6137 vcpu->arch.mtrr_state.have_fixed = 1;
e9b11c17
ZX		 6138 vcpu_load(vcpu);
6139 r = kvm_arch_vcpu_reset(vcpu);
6140 if (r == 0)
6141 r = kvm_mmu_setup(vcpu);
6142 vcpu_put(vcpu);
e9b11c17 6143
26e5215f 6144 return r;
e9b11c17
ZX		 6145}
6146
d40ccc62 6147void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 6148{
344d9588
GN		 6149 vcpu->arch.apf.msr_val = 0;
6150
e9b11c17
ZX		 6151 vcpu_load(vcpu);
6152 kvm_mmu_unload(vcpu);
6153 vcpu_put(vcpu);
6154
98918833 6155 fx_free(vcpu);
e9b11c17
ZX		 6156 kvm_x86_ops->vcpu_free(vcpu);
6157}
6158
6159int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
6160{
448fa4a9
JK		 6161 vcpu->arch.nmi_pending = false;
6162 vcpu->arch.nmi_injected = false;
6163
42dbaa5a
JK		 6164 vcpu->arch.switch_db_regs = 0;
6165 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
6166 vcpu->arch.dr6 = DR6_FIXED_1;
6167 vcpu->arch.dr7 = DR7_FIXED_1;
6168
3842d135 6169 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 6170 vcpu->arch.apf.msr_val = 0;
3842d135 6171
12f9a48f
GC		 6172 kvmclock_reset(vcpu);
6173
af585b92
GN		 6174 kvm_clear_async_pf_completion_queue(vcpu);
6175 kvm_async_pf_hash_reset(vcpu);
6176 vcpu->arch.apf.halted = false;
3842d135 6177
e9b11c17
ZX		 6178 return kvm_x86_ops->vcpu_reset(vcpu);
6179}
6180
10474ae8 6181int kvm_arch_hardware_enable(void *garbage)
e9b11c17 6182{
ca84d1a2
ZA		 6183 struct kvm *kvm;
6184 struct kvm_vcpu *vcpu;
6185 int i;
18863bdd
AK		 6186
6187 kvm_shared_msr_cpu_online();
ca84d1a2
ZA		 6188 list_for_each_entry(kvm, &vm_list, vm_list)
6189 kvm_for_each_vcpu(i, vcpu, kvm)
6190 if (vcpu->cpu == smp_processor_id())
c285545f 6191 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
10474ae8 6192 return kvm_x86_ops->hardware_enable(garbage);
e9b11c17
ZX		 6193}
6194
6195void kvm_arch_hardware_disable(void *garbage)
6196{
6197 kvm_x86_ops->hardware_disable(garbage);
3548bab5 6198 drop_user_return_notifiers(garbage);
e9b11c17
ZX		 6199}
6200
6201int kvm_arch_hardware_setup(void)
6202{
6203 return kvm_x86_ops->hardware_setup();
6204}
6205
6206void kvm_arch_hardware_unsetup(void)
6207{
6208 kvm_x86_ops->hardware_unsetup();
6209}
6210
6211void kvm_arch_check_processor_compat(void *rtn)
6212{
6213 kvm_x86_ops->check_processor_compatibility(rtn);
6214}
6215
6216int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
6217{
6218 struct page *page;
6219 struct kvm *kvm;
6220 int r;
6221
6222 BUG_ON(vcpu->kvm == NULL);
6223 kvm = vcpu->kvm;
6224
9aabc88f 6225 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
14dfe855 6226 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
ad312c7c 6227 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
c30a358d 6228 vcpu->arch.mmu.translate_gpa = translate_gpa;
02f59dc9 6229 vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa;
c5af89b6 6230 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 6231 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 6232 else
a4535290 6233 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 6234
6235 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
6236 if (!page) {
6237 r = -ENOMEM;
6238 goto fail;
6239 }
ad312c7c 6240 vcpu->arch.pio_data = page_address(page);
e9b11c17 6241
1e993611 6242 kvm_init_tsc_catchup(vcpu, max_tsc_khz);
c285545f 6243
e9b11c17
ZX		 6244 r = kvm_mmu_create(vcpu);
6245 if (r < 0)
6246 goto fail_free_pio_data;
6247
6248 if (irqchip_in_kernel(kvm)) {
6249 r = kvm_create_lapic(vcpu);
6250 if (r < 0)
6251 goto fail_mmu_destroy;
6252 }
6253
890ca9ae
HY		 6254 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
6255 GFP_KERNEL);
6256 if (!vcpu->arch.mce_banks) {
6257 r = -ENOMEM;
443c39bc 6258 goto fail_free_lapic;
890ca9ae
HY		 6259 }
6260 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
6261
f5f48ee1
SY		 6262 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL))
6263 goto fail_free_mce_banks;
6264
af585b92
GN		 6265 kvm_async_pf_hash_reset(vcpu);
6266
e9b11c17 6267 return 0;
f5f48ee1
SY		 6268fail_free_mce_banks:
6269 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 6270fail_free_lapic:
6271 kvm_free_lapic(vcpu);
e9b11c17
ZX		 6272fail_mmu_destroy:
6273 kvm_mmu_destroy(vcpu);
6274fail_free_pio_data:
ad312c7c 6275 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 6276fail:
6277 return r;
6278}
6279
6280void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
6281{
f656ce01
MT		 6282 int idx;
6283
36cb93fd 6284 kfree(vcpu->arch.mce_banks);
e9b11c17 6285 kvm_free_lapic(vcpu);
f656ce01 6286 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 6287 kvm_mmu_destroy(vcpu);
f656ce01 6288 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 6289 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17 6290}
d19a9cd2 6291
d89f5eff 6292int kvm_arch_init_vm(struct kvm *kvm)
d19a9cd2 6293{
f05e70ac 6294 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4d5c5d0f 6295 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2 6296
5550af4d
SY		 6297 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
6298 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
6299
038f8c11 6300 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
53f658b3 6301
d89f5eff 6302 return 0;
d19a9cd2
ZX		 6303}
6304
6305static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
6306{
6307 vcpu_load(vcpu);
6308 kvm_mmu_unload(vcpu);
6309 vcpu_put(vcpu);
6310}
6311
6312static void kvm_free_vcpus(struct kvm *kvm)
6313{
6314 unsigned int i;
988a2cae 6315 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 6316
6317 /*
6318 * Unpin any mmu pages first.
6319 */
af585b92
GN		 6320 kvm_for_each_vcpu(i, vcpu, kvm) {
6321 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 6322 kvm_unload_vcpu_mmu(vcpu);
af585b92 6323 }
988a2cae
GN		 6324 kvm_for_each_vcpu(i, vcpu, kvm)
6325 kvm_arch_vcpu_free(vcpu);
6326
6327 mutex_lock(&kvm->lock);
6328 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
6329 kvm->vcpus[i] = NULL;
d19a9cd2 6330
988a2cae
GN		 6331 atomic_set(&kvm->online_vcpus, 0);
6332 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 6333}
6334
ad8ba2cd
SY		 6335void kvm_arch_sync_events(struct kvm *kvm)
6336{
ba4cef31 6337 kvm_free_all_assigned_devices(kvm);
aea924f6 6338 kvm_free_pit(kvm);
ad8ba2cd
SY		 6339}
6340
d19a9cd2
ZX		 6341void kvm_arch_destroy_vm(struct kvm *kvm)
6342{
6eb55818 6343 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 6344 kfree(kvm->arch.vpic);
6345 kfree(kvm->arch.vioapic);
d19a9cd2 6346 kvm_free_vcpus(kvm);
3d45830c
AK		 6347 if (kvm->arch.apic_access_page)
6348 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 6349 if (kvm->arch.ept_identity_pagetable)
6350 put_page(kvm->arch.ept_identity_pagetable);
d19a9cd2 6351}
0de10343 6352
f7784b8e
MT		 6353int kvm_arch_prepare_memory_region(struct kvm *kvm,
6354 struct kvm_memory_slot *memslot,
0de10343 6355 struct kvm_memory_slot old,
f7784b8e 6356 struct kvm_userspace_memory_region *mem,
0de10343
ZX		 6357 int user_alloc)
6358{
f7784b8e 6359 int npages = memslot->npages;
7ac77099
AK		 6360 int map_flags = MAP_PRIVATE | MAP_ANONYMOUS;
6361
6362 /* Prevent internal slot pages from being moved by fork()/COW. */
6363 if (memslot->id >= KVM_MEMORY_SLOTS)
6364 map_flags = MAP_SHARED | MAP_ANONYMOUS;
0de10343
ZX		 6365
6366 /*To keep backward compatibility with older userspace,
6367 *x86 needs to hanlde !user_alloc case.
6368 */
6369 if (!user_alloc) {
6370 if (npages && !old.rmap) {
604b38ac
AA		 6371 unsigned long userspace_addr;
6372
72dc67a6 6373 down_write(&current->mm->mmap_sem);
604b38ac
AA		 6374 userspace_addr = do_mmap(NULL, 0,
6375 npages * PAGE_SIZE,
6376 PROT_READ | PROT_WRITE,
7ac77099 6377 map_flags,
604b38ac 6378 0);
72dc67a6 6379 up_write(&current->mm->mmap_sem);
0de10343 6380
604b38ac
AA		 6381 if (IS_ERR((void *)userspace_addr))
6382 return PTR_ERR((void *)userspace_addr);
6383
604b38ac 6384 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 6385 }
6386 }
6387
f7784b8e
MT		 6388
6389 return 0;
6390}
6391
6392void kvm_arch_commit_memory_region(struct kvm *kvm,
6393 struct kvm_userspace_memory_region *mem,
6394 struct kvm_memory_slot old,
6395 int user_alloc)
6396{
6397
48c0e4e9 6398 int nr_mmu_pages = 0, npages = mem->memory_size >> PAGE_SHIFT;
f7784b8e
MT		 6399
6400 if (!user_alloc && !old.user_alloc && old.rmap && !npages) {
6401 int ret;
6402
6403 down_write(&current->mm->mmap_sem);
6404 ret = do_munmap(current->mm, old.userspace_addr,
6405 old.npages * PAGE_SIZE);
6406 up_write(&current->mm->mmap_sem);
6407 if (ret < 0)
6408 printk(KERN_WARNING
6409 "kvm_vm_ioctl_set_memory_region: "
6410 "failed to munmap memory\n");
6411 }
6412
48c0e4e9
XG		 6413 if (!kvm->arch.n_requested_mmu_pages)
6414 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
6415
7c8a83b7 6416 spin_lock(&kvm->mmu_lock);
48c0e4e9 6417 if (nr_mmu_pages)
0de10343 6418 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
0de10343 6419 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
7c8a83b7 6420 spin_unlock(&kvm->mmu_lock);
0de10343 6421}
1d737c8a 6422
34d4cb8f
MT		 6423void kvm_arch_flush_shadow(struct kvm *kvm)
6424{
6425 kvm_mmu_zap_all(kvm);
8986ecc0 6426 kvm_reload_remote_mmus(kvm);
34d4cb8f
MT		 6427}
6428
1d737c8a
ZX		 6429int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
6430{
af585b92
GN		 6431 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6432 !vcpu->arch.apf.halted)
6433 || !list_empty_careful(&vcpu->async_pf.done)
a1b37100
GN		 6434 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
6435 || vcpu->arch.nmi_pending ||
6436 (kvm_arch_interrupt_allowed(vcpu) &&
6437 kvm_cpu_has_interrupt(vcpu));
1d737c8a 6438}
5736199a 6439
5736199a
ZX		 6440void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
6441{
32f88400
MT		 6442 int me;
6443 int cpu = vcpu->cpu;
5736199a
ZX		 6444
6445 if (waitqueue_active(&vcpu->wq)) {
6446 wake_up_interruptible(&vcpu->wq);
6447 ++vcpu->stat.halt_wakeup;
6448 }
32f88400
MT		 6449
6450 me = get_cpu();
6451 if (cpu != me && (unsigned)cpu < nr_cpu_ids && cpu_online(cpu))
6b7e2d09 6452 if (kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE)
32f88400 6453 smp_send_reschedule(cpu);
e9571ed5 6454 put_cpu();
5736199a 6455}
78646121
GN		 6456
6457int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
6458{
6459 return kvm_x86_ops->interrupt_allowed(vcpu);
6460}
229456fc 6461
f92653ee
JK		 6462bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
6463{
6464 unsigned long current_rip = kvm_rip_read(vcpu) +
6465 get_segment_base(vcpu, VCPU_SREG_CS);
6466
6467 return current_rip == linear_rip;
6468}
6469EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
6470
94fe45da
JK		 6471unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
6472{
6473 unsigned long rflags;
6474
6475 rflags = kvm_x86_ops->get_rflags(vcpu);
6476 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 6477 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 6478 return rflags;
6479}
6480EXPORT_SYMBOL_GPL(kvm_get_rflags);
6481
6482void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
6483{
6484 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 6485 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 6486 rflags |= X86_EFLAGS_TF;
94fe45da 6487 kvm_x86_ops->set_rflags(vcpu, rflags);
3842d135 6488 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 6489}
6490EXPORT_SYMBOL_GPL(kvm_set_rflags);
6491
56028d08
GN		 6492void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
6493{
6494 int r;
6495
fb67e14f 6496 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
c4806acd 6497 is_error_page(work->page))
56028d08
GN		 6498 return;
6499
6500 r = kvm_mmu_reload(vcpu);
6501 if (unlikely(r))
6502 return;
6503
fb67e14f
XG		 6504 if (!vcpu->arch.mmu.direct_map &&
6505 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
6506 return;
6507
56028d08
GN		 6508 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
6509}
6510
af585b92
GN		 6511static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
6512{
6513 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
6514}
6515
6516static inline u32 kvm_async_pf_next_probe(u32 key)
6517{
6518 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
6519}
6520
6521static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6522{
6523 u32 key = kvm_async_pf_hash_fn(gfn);
6524
6525 while (vcpu->arch.apf.gfns[key] != ~0)
6526 key = kvm_async_pf_next_probe(key);
6527
6528 vcpu->arch.apf.gfns[key] = gfn;
6529}
6530
6531static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
6532{
6533 int i;
6534 u32 key = kvm_async_pf_hash_fn(gfn);
6535
6536 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 6537 (vcpu->arch.apf.gfns[key] != gfn &&
6538 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 6539 key = kvm_async_pf_next_probe(key);
6540
6541 return key;
6542}
6543
6544bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6545{
6546 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
6547}
6548
6549static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6550{
6551 u32 i, j, k;
6552
6553 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
6554 while (true) {
6555 vcpu->arch.apf.gfns[i] = ~0;
6556 do {
6557 j = kvm_async_pf_next_probe(j);
6558 if (vcpu->arch.apf.gfns[j] == ~0)
6559 return;
6560 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
6561 /*
6562 * k lies cyclically in ]i,j]
6563 * | i.k.j |
6564 * |....j i.k.| or |.k..j i...|
6565 */
6566 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
6567 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
6568 i = j;
6569 }
6570}
6571
7c90705b
GN		 6572static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
6573{
6574
6575 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
6576 sizeof(val));
6577}
6578
af585b92
GN		 6579void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
6580 struct kvm_async_pf *work)
6581{
6389ee94
AK		 6582 struct x86_exception fault;
6583
7c90705b 6584 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 6585 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 6586
6587 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 6588 (vcpu->arch.apf.send_user_only &&
6589 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 6590 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
6591 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 6592 fault.vector = PF_VECTOR;
6593 fault.error_code_valid = true;
6594 fault.error_code = 0;
6595 fault.nested_page_fault = false;
6596 fault.address = work->arch.token;
6597 kvm_inject_page_fault(vcpu, &fault);
7c90705b 6598 }
af585b92
GN		 6599}
6600
6601void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
6602 struct kvm_async_pf *work)
6603{
6389ee94
AK		 6604 struct x86_exception fault;
6605
7c90705b
GN		 6606 trace_kvm_async_pf_ready(work->arch.token, work->gva);
6607 if (is_error_page(work->page))
6608 work->arch.token = ~0; /* broadcast wakeup */
6609 else
6610 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
6611
6612 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
6613 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 6614 fault.vector = PF_VECTOR;
6615 fault.error_code_valid = true;
6616 fault.error_code = 0;
6617 fault.nested_page_fault = false;
6618 fault.address = work->arch.token;
6619 kvm_inject_page_fault(vcpu, &fault);
7c90705b 6620 }
e6d53e3b 6621 vcpu->arch.apf.halted = false;
7c90705b
GN		 6622}
6623
6624bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
6625{
6626 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
6627 return true;
6628 else
6629 return !kvm_event_needs_reinjection(vcpu) &&
6630 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 6631}
6632
229456fc
MT		 6633EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
6634EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
6635EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
6636EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
6637EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 6638EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 6639EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 6640EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 6641EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 6642EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 6643EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 6644EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
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