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KVM: VMX: Parameterize vmx_complete_interrupts() for both exit and entry
[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
221d059d 9 * Copyright 2010 Red Hat, Inc. and/or its affilates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
313a3dc7 29
18068523 30#include <linux/clocksource.h>
4d5c5d0f 31#include <linux/interrupt.h>
313a3dc7
CO		 32#include <linux/kvm.h>
33#include <linux/fs.h>
34#include <linux/vmalloc.h>
5fb76f9b 35#include <linux/module.h>
0de10343 36#include <linux/mman.h>
2bacc55c 37#include <linux/highmem.h>
19de40a8 38#include <linux/iommu.h>
62c476c7 39#include <linux/intel-iommu.h>
c8076604 40#include <linux/cpufreq.h>
18863bdd 41#include <linux/user-return-notifier.h>
a983fb23 42#include <linux/srcu.h>
5a0e3ad6 43#include <linux/slab.h>
ff9d07a0 44#include <linux/perf_event.h>
7bee342a 45#include <linux/uaccess.h>
aec51dc4 46#include <trace/events/kvm.h>
2ed152af 47
229456fc
MT		 48#define CREATE_TRACE_POINTS
49#include "trace.h"
043405e1 50
24f1e32c 51#include <asm/debugreg.h>
d825ed0a 52#include <asm/msr.h>
a5f61300 53#include <asm/desc.h>
0bed3b56 54#include <asm/mtrr.h>
890ca9ae 55#include <asm/mce.h>
7cf30855 56#include <asm/i387.h>
98918833 57#include <asm/xcr.h>
1d5f066e 58#include <asm/pvclock.h>
217fc9cf 59#include <asm/div64.h>
043405e1 60
313a3dc7 61#define MAX_IO_MSRS 256
a03490ed
CO		 62#define CR0_RESERVED_BITS \
63 (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \
64 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \
65 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG))
66#define CR4_RESERVED_BITS \
67 (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\
68 | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \
69 | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR \
2acf923e 70 | X86_CR4_OSXSAVE \
a03490ed
CO		 71 | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE))
72
73#define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
890ca9ae
HY		 74
75#define KVM_MAX_MCE_BANKS 32
76#define KVM_MCE_CAP_SUPPORTED MCG_CTL_P
77
50a37eb4
JR		 78/* EFER defaults:
79 * - enable syscall per default because its emulated by KVM
80 * - enable LME and LMA per default on 64 bit KVM
81 */
82#ifdef CONFIG_X86_64
83static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffafeULL;
84#else
85static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffffeULL;
86#endif
313a3dc7 87
ba1389b7
AK		 88#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
89#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 90
cb142eb7 91static void update_cr8_intercept(struct kvm_vcpu *vcpu);
674eea0f
AK		 92static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
93 struct kvm_cpuid_entry2 __user *entries);
94
97896d04 95struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 96EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 97
ed85c068
AP		 98int ignore_msrs = 0;
99module_param_named(ignore_msrs, ignore_msrs, bool, S_IRUGO | S_IWUSR);
100
18863bdd
AK		 101#define KVM_NR_SHARED_MSRS 16
102
103struct kvm_shared_msrs_global {
104 int nr;
2bf78fa7 105 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 106};
107
108struct kvm_shared_msrs {
109 struct user_return_notifier urn;
110 bool registered;
2bf78fa7
SY		 111 struct kvm_shared_msr_values {
112 u64 host;
113 u64 curr;
114 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 115};
116
117static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
118static DEFINE_PER_CPU(struct kvm_shared_msrs, shared_msrs);
119
417bc304 120struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 121 { "pf_fixed", VCPU_STAT(pf_fixed) },
122 { "pf_guest", VCPU_STAT(pf_guest) },
123 { "tlb_flush", VCPU_STAT(tlb_flush) },
124 { "invlpg", VCPU_STAT(invlpg) },
125 { "exits", VCPU_STAT(exits) },
126 { "io_exits", VCPU_STAT(io_exits) },
127 { "mmio_exits", VCPU_STAT(mmio_exits) },
128 { "signal_exits", VCPU_STAT(signal_exits) },
129 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 130 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 131 { "halt_exits", VCPU_STAT(halt_exits) },
132 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 133 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 134 { "request_irq", VCPU_STAT(request_irq_exits) },
135 { "irq_exits", VCPU_STAT(irq_exits) },
136 { "host_state_reload", VCPU_STAT(host_state_reload) },
137 { "efer_reload", VCPU_STAT(efer_reload) },
138 { "fpu_reload", VCPU_STAT(fpu_reload) },
139 { "insn_emulation", VCPU_STAT(insn_emulation) },
140 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 141 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 142 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 143 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
144 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
145 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
146 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
147 { "mmu_flooded", VM_STAT(mmu_flooded) },
148 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 149 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 150 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 151 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 152 { "largepages", VM_STAT(lpages) },
417bc304
HB		 153 { NULL }
154};
155
2acf923e
DC		 156u64 __read_mostly host_xcr0;
157
158static inline u32 bit(int bitno)
159{
160 return 1 << (bitno & 31);
161}
162
18863bdd
AK		 163static void kvm_on_user_return(struct user_return_notifier *urn)
164{
165 unsigned slot;
18863bdd
AK		 166 struct kvm_shared_msrs *locals
167 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 168 struct kvm_shared_msr_values *values;
18863bdd
AK		 169
170 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 171 values = &locals->values[slot];
172 if (values->host != values->curr) {
173 wrmsrl(shared_msrs_global.msrs[slot], values->host);
174 values->curr = values->host;
18863bdd
AK		 175 }
176 }
177 locals->registered = false;
178 user_return_notifier_unregister(urn);
179}
180
2bf78fa7 181static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 182{
2bf78fa7 183 struct kvm_shared_msrs *smsr;
18863bdd
AK		 184 u64 value;
185
2bf78fa7
SY		 186 smsr = &__get_cpu_var(shared_msrs);
187 /* only read, and nobody should modify it at this time,
188 * so don't need lock */
189 if (slot >= shared_msrs_global.nr) {
190 printk(KERN_ERR "kvm: invalid MSR slot!");
191 return;
192 }
193 rdmsrl_safe(msr, &value);
194 smsr->values[slot].host = value;
195 smsr->values[slot].curr = value;
196}
197
198void kvm_define_shared_msr(unsigned slot, u32 msr)
199{
18863bdd
AK		 200 if (slot >= shared_msrs_global.nr)
201 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 202 shared_msrs_global.msrs[slot] = msr;
203 /* we need ensured the shared_msr_global have been updated */
204 smp_wmb();
18863bdd
AK		 205}
206EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
207
208static void kvm_shared_msr_cpu_online(void)
209{
210 unsigned i;
18863bdd
AK		 211
212 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 213 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 214}
215
d5696725 216void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd
AK		 217{
218 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
219
2bf78fa7 220 if (((value ^ smsr->values[slot].curr) & mask) == 0)
18863bdd 221 return;
2bf78fa7
SY		 222 smsr->values[slot].curr = value;
223 wrmsrl(shared_msrs_global.msrs[slot], value);
18863bdd
AK		 224 if (!smsr->registered) {
225 smsr->urn.on_user_return = kvm_on_user_return;
226 user_return_notifier_register(&smsr->urn);
227 smsr->registered = true;
228 }
229}
230EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
231
3548bab5
AK		 232static void drop_user_return_notifiers(void *ignore)
233{
234 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
235
236 if (smsr->registered)
237 kvm_on_user_return(&smsr->urn);
238}
239
6866b83e
CO		 240u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
241{
242 if (irqchip_in_kernel(vcpu->kvm))
ad312c7c 243 return vcpu->arch.apic_base;
6866b83e 244 else
ad312c7c 245 return vcpu->arch.apic_base;
6866b83e
CO		 246}
247EXPORT_SYMBOL_GPL(kvm_get_apic_base);
248
249void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
250{
251 /* TODO: reserve bits check */
252 if (irqchip_in_kernel(vcpu->kvm))
253 kvm_lapic_set_base(vcpu, data);
254 else
ad312c7c 255 vcpu->arch.apic_base = data;
6866b83e
CO		 256}
257EXPORT_SYMBOL_GPL(kvm_set_apic_base);
258
3fd28fce
ED		 259#define EXCPT_BENIGN 0
260#define EXCPT_CONTRIBUTORY 1
261#define EXCPT_PF 2
262
263static int exception_class(int vector)
264{
265 switch (vector) {
266 case PF_VECTOR:
267 return EXCPT_PF;
268 case DE_VECTOR:
269 case TS_VECTOR:
270 case NP_VECTOR:
271 case SS_VECTOR:
272 case GP_VECTOR:
273 return EXCPT_CONTRIBUTORY;
274 default:
275 break;
276 }
277 return EXCPT_BENIGN;
278}
279
280static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 281 unsigned nr, bool has_error, u32 error_code,
282 bool reinject)
3fd28fce
ED		 283{
284 u32 prev_nr;
285 int class1, class2;
286
3842d135
AK		 287 kvm_make_request(KVM_REQ_EVENT, vcpu);
288
3fd28fce
ED		 289 if (!vcpu->arch.exception.pending) {
290 queue:
291 vcpu->arch.exception.pending = true;
292 vcpu->arch.exception.has_error_code = has_error;
293 vcpu->arch.exception.nr = nr;
294 vcpu->arch.exception.error_code = error_code;
3f0fd292 295 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 296 return;
297 }
298
299 /* to check exception */
300 prev_nr = vcpu->arch.exception.nr;
301 if (prev_nr == DF_VECTOR) {
302 /* triple fault -> shutdown */
a8eeb04a 303 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 304 return;
305 }
306 class1 = exception_class(prev_nr);
307 class2 = exception_class(nr);
308 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
309 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
310 /* generate double fault per SDM Table 5-5 */
311 vcpu->arch.exception.pending = true;
312 vcpu->arch.exception.has_error_code = true;
313 vcpu->arch.exception.nr = DF_VECTOR;
314 vcpu->arch.exception.error_code = 0;
315 } else
316 /* replace previous exception with a new one in a hope
317 that instruction re-execution will regenerate lost
318 exception */
319 goto queue;
320}
321
298101da
AK		 322void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
323{
ce7ddec4 324 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 325}
326EXPORT_SYMBOL_GPL(kvm_queue_exception);
327
ce7ddec4
JR		 328void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
329{
330 kvm_multiple_exception(vcpu, nr, false, 0, true);
331}
332EXPORT_SYMBOL_GPL(kvm_requeue_exception);
333
8df25a32 334void kvm_inject_page_fault(struct kvm_vcpu *vcpu)
c3c91fee 335{
8df25a32
JR		 336 unsigned error_code = vcpu->arch.fault.error_code;
337
c3c91fee 338 ++vcpu->stat.pf_guest;
8df25a32 339 vcpu->arch.cr2 = vcpu->arch.fault.address;
c3c91fee
AK		 340 kvm_queue_exception_e(vcpu, PF_VECTOR, error_code);
341}
342
d4f8cf66
JR		 343void kvm_propagate_fault(struct kvm_vcpu *vcpu)
344{
345 u32 nested, error;
346
347 error = vcpu->arch.fault.error_code;
348 nested = error & PFERR_NESTED_MASK;
349 error = error & ~PFERR_NESTED_MASK;
350
351 vcpu->arch.fault.error_code = error;
352
353 if (mmu_is_nested(vcpu) && !nested)
354 vcpu->arch.nested_mmu.inject_page_fault(vcpu);
355 else
356 vcpu->arch.mmu.inject_page_fault(vcpu);
357}
358
3419ffc8
SY		 359void kvm_inject_nmi(struct kvm_vcpu *vcpu)
360{
3842d135 361 kvm_make_request(KVM_REQ_EVENT, vcpu);
3419ffc8
SY		 362 vcpu->arch.nmi_pending = 1;
363}
364EXPORT_SYMBOL_GPL(kvm_inject_nmi);
365
298101da
AK		 366void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
367{
ce7ddec4 368 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 369}
370EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
371
ce7ddec4
JR		 372void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
373{
374 kvm_multiple_exception(vcpu, nr, true, error_code, true);
375}
376EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
377
0a79b009
AK		 378/*
379 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
380 * a #GP and return false.
381 */
382bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 383{
0a79b009
AK		 384 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
385 return true;
386 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
387 return false;
298101da 388}
0a79b009 389EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 390
ec92fe44
JR		 391/*
392 * This function will be used to read from the physical memory of the currently
393 * running guest. The difference to kvm_read_guest_page is that this function
394 * can read from guest physical or from the guest's guest physical memory.
395 */
396int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
397 gfn_t ngfn, void *data, int offset, int len,
398 u32 access)
399{
400 gfn_t real_gfn;
401 gpa_t ngpa;
402
403 ngpa = gfn_to_gpa(ngfn);
404 real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
405 if (real_gfn == UNMAPPED_GVA)
406 return -EFAULT;
407
408 real_gfn = gpa_to_gfn(real_gfn);
409
410 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
411}
412EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
413
3d06b8bf
JR		 414int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
415 void *data, int offset, int len, u32 access)
416{
417 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
418 data, offset, len, access);
419}
420
a03490ed
CO		 421/*
422 * Load the pae pdptrs. Return true is they are all valid.
423 */
ff03a073 424int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 425{
426 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
427 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
428 int i;
429 int ret;
ff03a073 430 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 431
ff03a073
JR		 432 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
433 offset * sizeof(u64), sizeof(pdpte),
434 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 435 if (ret < 0) {
436 ret = 0;
437 goto out;
438 }
439 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 440 if (is_present_gpte(pdpte[i]) &&
20c466b5 441 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 442 ret = 0;
443 goto out;
444 }
445 }
446 ret = 1;
447
ff03a073 448 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 449 __set_bit(VCPU_EXREG_PDPTR,
450 (unsigned long *)&vcpu->arch.regs_avail);
451 __set_bit(VCPU_EXREG_PDPTR,
452 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 453out:
a03490ed
CO		 454
455 return ret;
456}
cc4b6871 457EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 458
d835dfec
AK		 459static bool pdptrs_changed(struct kvm_vcpu *vcpu)
460{
ff03a073 461 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 462 bool changed = true;
3d06b8bf
JR		 463 int offset;
464 gfn_t gfn;
d835dfec
AK		 465 int r;
466
467 if (is_long_mode(vcpu) || !is_pae(vcpu))
468 return false;
469
6de4f3ad
AK		 470 if (!test_bit(VCPU_EXREG_PDPTR,
471 (unsigned long *)&vcpu->arch.regs_avail))
472 return true;
473
3d06b8bf
JR		 474 gfn = (vcpu->arch.cr3 & ~31u) >> PAGE_SHIFT;
475 offset = (vcpu->arch.cr3 & ~31u) & (PAGE_SIZE - 1);
476 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
477 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 478 if (r < 0)
479 goto out;
ff03a073 480 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 481out:
d835dfec
AK		 482
483 return changed;
484}
485
49a9b07e 486int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 487{
aad82703
SY		 488 unsigned long old_cr0 = kvm_read_cr0(vcpu);
489 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
490 X86_CR0_CD | X86_CR0_NW;
491
f9a48e6a
AK		 492 cr0 |= X86_CR0_ET;
493
ab344828 494#ifdef CONFIG_X86_64
0f12244f
GN		 495 if (cr0 & 0xffffffff00000000UL)
496 return 1;
ab344828
GN		 497#endif
498
499 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 500
0f12244f
GN		 501 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
502 return 1;
a03490ed 503
0f12244f
GN		 504 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
505 return 1;
a03490ed
CO		 506
507 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
508#ifdef CONFIG_X86_64
f6801dff 509 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 510 int cs_db, cs_l;
511
0f12244f
GN		 512 if (!is_pae(vcpu))
513 return 1;
a03490ed 514 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 515 if (cs_l)
516 return 1;
a03490ed
CO		 517 } else
518#endif
ff03a073
JR		 519 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
520 vcpu->arch.cr3))
0f12244f 521 return 1;
a03490ed
CO		 522 }
523
524 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 525
aad82703
SY		 526 if ((cr0 ^ old_cr0) & update_bits)
527 kvm_mmu_reset_context(vcpu);
0f12244f
GN		 528 return 0;
529}
2d3ad1f4 530EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 531
2d3ad1f4 532void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 533{
49a9b07e 534 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 535}
2d3ad1f4 536EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 537
2acf923e
DC		 538int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
539{
540 u64 xcr0;
541
542 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
543 if (index != XCR_XFEATURE_ENABLED_MASK)
544 return 1;
545 xcr0 = xcr;
546 if (kvm_x86_ops->get_cpl(vcpu) != 0)
547 return 1;
548 if (!(xcr0 & XSTATE_FP))
549 return 1;
550 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
551 return 1;
552 if (xcr0 & ~host_xcr0)
553 return 1;
554 vcpu->arch.xcr0 = xcr0;
555 vcpu->guest_xcr0_loaded = 0;
556 return 0;
557}
558
559int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
560{
561 if (__kvm_set_xcr(vcpu, index, xcr)) {
562 kvm_inject_gp(vcpu, 0);
563 return 1;
564 }
565 return 0;
566}
567EXPORT_SYMBOL_GPL(kvm_set_xcr);
568
569static bool guest_cpuid_has_xsave(struct kvm_vcpu *vcpu)
570{
571 struct kvm_cpuid_entry2 *best;
572
573 best = kvm_find_cpuid_entry(vcpu, 1, 0);
574 return best && (best->ecx & bit(X86_FEATURE_XSAVE));
575}
576
577static void update_cpuid(struct kvm_vcpu *vcpu)
578{
579 struct kvm_cpuid_entry2 *best;
580
581 best = kvm_find_cpuid_entry(vcpu, 1, 0);
582 if (!best)
583 return;
584
585 /* Update OSXSAVE bit */
586 if (cpu_has_xsave && best->function == 0x1) {
587 best->ecx &= ~(bit(X86_FEATURE_OSXSAVE));
588 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE))
589 best->ecx |= bit(X86_FEATURE_OSXSAVE);
590 }
591}
592
a83b29c6 593int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 594{
fc78f519 595 unsigned long old_cr4 = kvm_read_cr4(vcpu);
a2edf57f
AK		 596 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE;
597
0f12244f
GN		 598 if (cr4 & CR4_RESERVED_BITS)
599 return 1;
a03490ed 600
2acf923e
DC		 601 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
602 return 1;
603
a03490ed 604 if (is_long_mode(vcpu)) {
0f12244f
GN		 605 if (!(cr4 & X86_CR4_PAE))
606 return 1;
a2edf57f
AK		 607 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
608 && ((cr4 ^ old_cr4) & pdptr_bits)
ff03a073 609 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, vcpu->arch.cr3))
0f12244f
GN		 610 return 1;
611
612 if (cr4 & X86_CR4_VMXE)
613 return 1;
a03490ed 614
a03490ed 615 kvm_x86_ops->set_cr4(vcpu, cr4);
62ad0755 616
aad82703
SY		 617 if ((cr4 ^ old_cr4) & pdptr_bits)
618 kvm_mmu_reset_context(vcpu);
0f12244f 619
2acf923e
DC		 620 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
621 update_cpuid(vcpu);
622
0f12244f
GN		 623 return 0;
624}
2d3ad1f4 625EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 626
2390218b 627int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 628{
ad312c7c 629 if (cr3 == vcpu->arch.cr3 && !pdptrs_changed(vcpu)) {
0ba73cda 630 kvm_mmu_sync_roots(vcpu);
d835dfec 631 kvm_mmu_flush_tlb(vcpu);
0f12244f 632 return 0;
d835dfec
AK		 633 }
634
a03490ed 635 if (is_long_mode(vcpu)) {
0f12244f
GN		 636 if (cr3 & CR3_L_MODE_RESERVED_BITS)
637 return 1;
a03490ed
CO		 638 } else {
639 if (is_pae(vcpu)) {
0f12244f
GN		 640 if (cr3 & CR3_PAE_RESERVED_BITS)
641 return 1;
ff03a073
JR		 642 if (is_paging(vcpu) &&
643 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
0f12244f 644 return 1;
a03490ed
CO		 645 }
646 /*
647 * We don't check reserved bits in nonpae mode, because
648 * this isn't enforced, and VMware depends on this.
649 */
650 }
651
a03490ed
CO		 652 /*
653 * Does the new cr3 value map to physical memory? (Note, we
654 * catch an invalid cr3 even in real-mode, because it would
655 * cause trouble later on when we turn on paging anyway.)
656 *
657 * A real CPU would silently accept an invalid cr3 and would
658 * attempt to use it - with largely undefined (and often hard
659 * to debug) behavior on the guest side.
660 */
661 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
0f12244f
GN		 662 return 1;
663 vcpu->arch.cr3 = cr3;
664 vcpu->arch.mmu.new_cr3(vcpu);
665 return 0;
666}
2d3ad1f4 667EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 668
0f12244f 669int __kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 670{
0f12244f
GN		 671 if (cr8 & CR8_RESERVED_BITS)
672 return 1;
a03490ed
CO		 673 if (irqchip_in_kernel(vcpu->kvm))
674 kvm_lapic_set_tpr(vcpu, cr8);
675 else
ad312c7c 676 vcpu->arch.cr8 = cr8;
0f12244f
GN		 677 return 0;
678}
679
680void kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
681{
682 if (__kvm_set_cr8(vcpu, cr8))
683 kvm_inject_gp(vcpu, 0);
a03490ed 684}
2d3ad1f4 685EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 686
2d3ad1f4 687unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 688{
689 if (irqchip_in_kernel(vcpu->kvm))
690 return kvm_lapic_get_cr8(vcpu);
691 else
ad312c7c 692 return vcpu->arch.cr8;
a03490ed 693}
2d3ad1f4 694EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 695
338dbc97 696static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 697{
698 switch (dr) {
699 case 0 ... 3:
700 vcpu->arch.db[dr] = val;
701 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
702 vcpu->arch.eff_db[dr] = val;
703 break;
704 case 4:
338dbc97
GN		 705 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
706 return 1; /* #UD */
020df079
GN		 707 /* fall through */
708 case 6:
338dbc97
GN		 709 if (val & 0xffffffff00000000ULL)
710 return -1; /* #GP */
020df079
GN		 711 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
712 break;
713 case 5:
338dbc97
GN		 714 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
715 return 1; /* #UD */
020df079
GN		 716 /* fall through */
717 default: /* 7 */
338dbc97
GN		 718 if (val & 0xffffffff00000000ULL)
719 return -1; /* #GP */
020df079
GN		 720 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
721 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
722 kvm_x86_ops->set_dr7(vcpu, vcpu->arch.dr7);
723 vcpu->arch.switch_db_regs = (val & DR7_BP_EN_MASK);
724 }
725 break;
726 }
727
728 return 0;
729}
338dbc97
GN		 730
731int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
732{
733 int res;
734
735 res = __kvm_set_dr(vcpu, dr, val);
736 if (res > 0)
737 kvm_queue_exception(vcpu, UD_VECTOR);
738 else if (res < 0)
739 kvm_inject_gp(vcpu, 0);
740
741 return res;
742}
020df079
GN		 743EXPORT_SYMBOL_GPL(kvm_set_dr);
744
338dbc97 745static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 746{
747 switch (dr) {
748 case 0 ... 3:
749 *val = vcpu->arch.db[dr];
750 break;
751 case 4:
338dbc97 752 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 753 return 1;
020df079
GN		 754 /* fall through */
755 case 6:
756 *val = vcpu->arch.dr6;
757 break;
758 case 5:
338dbc97 759 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 760 return 1;
020df079
GN		 761 /* fall through */
762 default: /* 7 */
763 *val = vcpu->arch.dr7;
764 break;
765 }
766
767 return 0;
768}
338dbc97
GN		 769
770int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
771{
772 if (_kvm_get_dr(vcpu, dr, val)) {
773 kvm_queue_exception(vcpu, UD_VECTOR);
774 return 1;
775 }
776 return 0;
777}
020df079
GN		 778EXPORT_SYMBOL_GPL(kvm_get_dr);
779
043405e1
CO		 780/*
781 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
782 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
783 *
784 * This list is modified at module load time to reflect the
e3267cbb
GC		 785 * capabilities of the host cpu. This capabilities test skips MSRs that are
786 * kvm-specific. Those are put in the beginning of the list.
043405e1 787 */
e3267cbb 788
11c6bffa 789#define KVM_SAVE_MSRS_BEGIN 7
043405e1 790static u32 msrs_to_save[] = {
e3267cbb 791 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
11c6bffa 792 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
55cd8e5a 793 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
10388a07 794 HV_X64_MSR_APIC_ASSIST_PAGE,
043405e1 795 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 796 MSR_STAR,
043405e1
CO		 797#ifdef CONFIG_X86_64
798 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
799#endif
e90aa41e 800 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
043405e1
CO		 801};
802
803static unsigned num_msrs_to_save;
804
805static u32 emulated_msrs[] = {
806 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 807 MSR_IA32_MCG_STATUS,
808 MSR_IA32_MCG_CTL,
043405e1
CO		 809};
810
b69e8cae 811static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 812{
aad82703
SY		 813 u64 old_efer = vcpu->arch.efer;
814
b69e8cae
RJ		 815 if (efer & efer_reserved_bits)
816 return 1;
15c4a640
CO		 817
818 if (is_paging(vcpu)
b69e8cae
RJ		 819 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
820 return 1;
15c4a640 821
1b2fd70c
AG		 822 if (efer & EFER_FFXSR) {
823 struct kvm_cpuid_entry2 *feat;
824
825 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 826 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
827 return 1;
1b2fd70c
AG		 828 }
829
d8017474
AG		 830 if (efer & EFER_SVME) {
831 struct kvm_cpuid_entry2 *feat;
832
833 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 834 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
835 return 1;
d8017474
AG		 836 }
837
15c4a640 838 efer &= ~EFER_LMA;
f6801dff 839 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 840
a3d204e2
SY		 841 kvm_x86_ops->set_efer(vcpu, efer);
842
9645bb56
AK		 843 vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
844 kvm_mmu_reset_context(vcpu);
b69e8cae 845
aad82703
SY		 846 /* Update reserved bits */
847 if ((efer ^ old_efer) & EFER_NX)
848 kvm_mmu_reset_context(vcpu);
849
b69e8cae 850 return 0;
15c4a640
CO		 851}
852
f2b4b7dd
JR		 853void kvm_enable_efer_bits(u64 mask)
854{
855 efer_reserved_bits &= ~mask;
856}
857EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
858
859
15c4a640
CO		 860/*
861 * Writes msr value into into the appropriate "register".
862 * Returns 0 on success, non-0 otherwise.
863 * Assumes vcpu_load() was already called.
864 */
865int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
866{
867 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
868}
869
313a3dc7
CO		 870/*
871 * Adapt set_msr() to msr_io()'s calling convention
872 */
873static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
874{
875 return kvm_set_msr(vcpu, index, *data);
876}
877
18068523
GOC		 878static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
879{
9ed3c444
AK		 880 int version;
881 int r;
50d0a0f9 882 struct pvclock_wall_clock wc;
923de3cf 883 struct timespec boot;
18068523
GOC		 884
885 if (!wall_clock)
886 return;
887
9ed3c444
AK		 888 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
889 if (r)
890 return;
891
892 if (version & 1)
893 ++version; /* first time write, random junk */
894
895 ++version;
18068523 896
18068523
GOC		 897 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
898
50d0a0f9
GH		 899 /*
900 * The guest calculates current wall clock time by adding
901 * system time (updated by kvm_write_guest_time below) to the
902 * wall clock specified here. guest system time equals host
903 * system time for us, thus we must fill in host boot time here.
904 */
923de3cf 905 getboottime(&boot);
50d0a0f9
GH		 906
907 wc.sec = boot.tv_sec;
908 wc.nsec = boot.tv_nsec;
909 wc.version = version;
18068523
GOC		 910
911 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
912
913 version++;
914 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 915}
916
50d0a0f9
GH		 917static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
918{
919 uint32_t quotient, remainder;
920
921 /* Don't try to replace with do_div(), this one calculates
922 * "(dividend << 32) / divisor" */
923 __asm__ ( "divl %4"
924 : "=a" (quotient), "=d" (remainder)
925 : "0" (0), "1" (dividend), "r" (divisor) );
926 return quotient;
927}
928
929static void kvm_set_time_scale(uint32_t tsc_khz, struct pvclock_vcpu_time_info *hv_clock)
930{
931 uint64_t nsecs = 1000000000LL;
932 int32_t shift = 0;
933 uint64_t tps64;
934 uint32_t tps32;
935
936 tps64 = tsc_khz * 1000LL;
937 while (tps64 > nsecs*2) {
938 tps64 >>= 1;
939 shift--;
940 }
941
942 tps32 = (uint32_t)tps64;
943 while (tps32 <= (uint32_t)nsecs) {
944 tps32 <<= 1;
945 shift++;
946 }
947
948 hv_clock->tsc_shift = shift;
949 hv_clock->tsc_to_system_mul = div_frac(nsecs, tps32);
950
951 pr_debug("%s: tsc_khz %u, tsc_shift %d, tsc_mul %u\n",
80a914dc 952 __func__, tsc_khz, hv_clock->tsc_shift,
50d0a0f9
GH		 953 hv_clock->tsc_to_system_mul);
954}
955
759379dd
ZA		 956static inline u64 get_kernel_ns(void)
957{
958 struct timespec ts;
959
960 WARN_ON(preemptible());
961 ktime_get_ts(&ts);
962 monotonic_to_bootbased(&ts);
963 return timespec_to_ns(&ts);
964}
965
c8076604
GH		 966static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
967
8cfdc000
ZA		 968static inline int kvm_tsc_changes_freq(void)
969{
970 int cpu = get_cpu();
971 int ret = !boot_cpu_has(X86_FEATURE_CONSTANT_TSC) &&
972 cpufreq_quick_get(cpu) != 0;
973 put_cpu();
974 return ret;
975}
976
759379dd
ZA		 977static inline u64 nsec_to_cycles(u64 nsec)
978{
217fc9cf
AK		 979 u64 ret;
980
759379dd
ZA		 981 WARN_ON(preemptible());
982 if (kvm_tsc_changes_freq())
983 printk_once(KERN_WARNING
984 "kvm: unreliable cycle conversion on adjustable rate TSC\n");
217fc9cf
AK		 985 ret = nsec * __get_cpu_var(cpu_tsc_khz);
986 do_div(ret, USEC_PER_SEC);
987 return ret;
759379dd
ZA		 988}
989
99e3e30a
ZA		 990void kvm_write_tsc(struct kvm_vcpu *vcpu, u64 data)
991{
992 struct kvm *kvm = vcpu->kvm;
f38e098f 993 u64 offset, ns, elapsed;
99e3e30a 994 unsigned long flags;
46543ba4 995 s64 sdiff;
99e3e30a
ZA		 996
997 spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
998 offset = data - native_read_tsc();
759379dd 999 ns = get_kernel_ns();
f38e098f 1000 elapsed = ns - kvm->arch.last_tsc_nsec;
46543ba4
ZA		 1001 sdiff = data - kvm->arch.last_tsc_write;
1002 if (sdiff < 0)
1003 sdiff = -sdiff;
f38e098f
ZA		 1004
1005 /*
46543ba4 1006 * Special case: close write to TSC within 5 seconds of
f38e098f 1007 * another CPU is interpreted as an attempt to synchronize
46543ba4
ZA		 1008 * The 5 seconds is to accomodate host load / swapping as
1009 * well as any reset of TSC during the boot process.
f38e098f
ZA		 1010 *
1011 * In that case, for a reliable TSC, we can match TSC offsets,
46543ba4 1012 * or make a best guest using elapsed value.
f38e098f 1013 */
46543ba4
ZA		 1014 if (sdiff < nsec_to_cycles(5ULL * NSEC_PER_SEC) &&
1015 elapsed < 5ULL * NSEC_PER_SEC) {
f38e098f
ZA		 1016 if (!check_tsc_unstable()) {
1017 offset = kvm->arch.last_tsc_offset;
1018 pr_debug("kvm: matched tsc offset for %llu\n", data);
1019 } else {
759379dd
ZA		 1020 u64 delta = nsec_to_cycles(elapsed);
1021 offset += delta;
1022 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f
ZA		 1023 }
1024 ns = kvm->arch.last_tsc_nsec;
1025 }
1026 kvm->arch.last_tsc_nsec = ns;
1027 kvm->arch.last_tsc_write = data;
1028 kvm->arch.last_tsc_offset = offset;
99e3e30a
ZA		 1029 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1030 spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
1031
1032 /* Reset of TSC must disable overshoot protection below */
1033 vcpu->arch.hv_clock.tsc_timestamp = 0;
1034}
1035EXPORT_SYMBOL_GPL(kvm_write_tsc);
1036
8cfdc000 1037static int kvm_write_guest_time(struct kvm_vcpu *v)
18068523 1038{
18068523
GOC		 1039 unsigned long flags;
1040 struct kvm_vcpu_arch *vcpu = &v->arch;
1041 void *shared_kaddr;
463656c0 1042 unsigned long this_tsc_khz;
1d5f066e
ZA		 1043 s64 kernel_ns, max_kernel_ns;
1044 u64 tsc_timestamp;
18068523
GOC		 1045
1046 if ((!vcpu->time_page))
8cfdc000 1047 return 0;
50d0a0f9 1048
18068523
GOC		 1049 /* Keep irq disabled to prevent changes to the clock */
1050 local_irq_save(flags);
1d5f066e 1051 kvm_get_msr(v, MSR_IA32_TSC, &tsc_timestamp);
759379dd 1052 kernel_ns = get_kernel_ns();
8cfdc000 1053 this_tsc_khz = __get_cpu_var(cpu_tsc_khz);
18068523
GOC		 1054 local_irq_restore(flags);
1055
8cfdc000
ZA		 1056 if (unlikely(this_tsc_khz == 0)) {
1057 kvm_make_request(KVM_REQ_KVMCLOCK_UPDATE, v);
1058 return 1;
1059 }
18068523 1060
1d5f066e
ZA		 1061 /*
1062 * Time as measured by the TSC may go backwards when resetting the base
1063 * tsc_timestamp. The reason for this is that the TSC resolution is
1064 * higher than the resolution of the other clock scales. Thus, many
1065 * possible measurments of the TSC correspond to one measurement of any
1066 * other clock, and so a spread of values is possible. This is not a
1067 * problem for the computation of the nanosecond clock; with TSC rates
1068 * around 1GHZ, there can only be a few cycles which correspond to one
1069 * nanosecond value, and any path through this code will inevitably
1070 * take longer than that. However, with the kernel_ns value itself,
1071 * the precision may be much lower, down to HZ granularity. If the
1072 * first sampling of TSC against kernel_ns ends in the low part of the
1073 * range, and the second in the high end of the range, we can get:
1074 *
1075 * (TSC - offset_low) * S + kns_old > (TSC - offset_high) * S + kns_new
1076 *
1077 * As the sampling errors potentially range in the thousands of cycles,
1078 * it is possible such a time value has already been observed by the
1079 * guest. To protect against this, we must compute the system time as
1080 * observed by the guest and ensure the new system time is greater.
1081 */
1082 max_kernel_ns = 0;
1083 if (vcpu->hv_clock.tsc_timestamp && vcpu->last_guest_tsc) {
1084 max_kernel_ns = vcpu->last_guest_tsc -
1085 vcpu->hv_clock.tsc_timestamp;
1086 max_kernel_ns = pvclock_scale_delta(max_kernel_ns,
1087 vcpu->hv_clock.tsc_to_system_mul,
1088 vcpu->hv_clock.tsc_shift);
1089 max_kernel_ns += vcpu->last_kernel_ns;
1090 }
1091
e48672fa 1092 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
8cfdc000 1093 kvm_set_time_scale(this_tsc_khz, &vcpu->hv_clock);
e48672fa 1094 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1095 }
1096
1d5f066e
ZA		 1097 if (max_kernel_ns > kernel_ns)
1098 kernel_ns = max_kernel_ns;
1099
8cfdc000 1100 /* With all the info we got, fill in the values */
1d5f066e 1101 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1102 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1d5f066e 1103 vcpu->last_kernel_ns = kernel_ns;
371bcf64
GC		 1104 vcpu->hv_clock.flags = 0;
1105
18068523
GOC		 1106 /*
1107 * The interface expects us to write an even number signaling that the
1108 * update is finished. Since the guest won't see the intermediate
50d0a0f9 1109 * state, we just increase by 2 at the end.
18068523 1110 */
50d0a0f9 1111 vcpu->hv_clock.version += 2;
18068523
GOC		 1112
1113 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
1114
1115 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
50d0a0f9 1116 sizeof(vcpu->hv_clock));
18068523
GOC		 1117
1118 kunmap_atomic(shared_kaddr, KM_USER0);
1119
1120 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
8cfdc000 1121 return 0;
18068523
GOC		 1122}
1123
c8076604
GH		 1124static int kvm_request_guest_time_update(struct kvm_vcpu *v)
1125{
1126 struct kvm_vcpu_arch *vcpu = &v->arch;
1127
1128 if (!vcpu->time_page)
1129 return 0;
a8eeb04a 1130 kvm_make_request(KVM_REQ_KVMCLOCK_UPDATE, v);
c8076604
GH		 1131 return 1;
1132}
1133
9ba075a6
AK		 1134static bool msr_mtrr_valid(unsigned msr)
1135{
1136 switch (msr) {
1137 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1138 case MSR_MTRRfix64K_00000:
1139 case MSR_MTRRfix16K_80000:
1140 case MSR_MTRRfix16K_A0000:
1141 case MSR_MTRRfix4K_C0000:
1142 case MSR_MTRRfix4K_C8000:
1143 case MSR_MTRRfix4K_D0000:
1144 case MSR_MTRRfix4K_D8000:
1145 case MSR_MTRRfix4K_E0000:
1146 case MSR_MTRRfix4K_E8000:
1147 case MSR_MTRRfix4K_F0000:
1148 case MSR_MTRRfix4K_F8000:
1149 case MSR_MTRRdefType:
1150 case MSR_IA32_CR_PAT:
1151 return true;
1152 case 0x2f8:
1153 return true;
1154 }
1155 return false;
1156}
1157
d6289b93
MT		 1158static bool valid_pat_type(unsigned t)
1159{
1160 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1161}
1162
1163static bool valid_mtrr_type(unsigned t)
1164{
1165 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1166}
1167
1168static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1169{
1170 int i;
1171
1172 if (!msr_mtrr_valid(msr))
1173 return false;
1174
1175 if (msr == MSR_IA32_CR_PAT) {
1176 for (i = 0; i < 8; i++)
1177 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1178 return false;
1179 return true;
1180 } else if (msr == MSR_MTRRdefType) {
1181 if (data & ~0xcff)
1182 return false;
1183 return valid_mtrr_type(data & 0xff);
1184 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1185 for (i = 0; i < 8 ; i++)
1186 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1187 return false;
1188 return true;
1189 }
1190
1191 /* variable MTRRs */
1192 return valid_mtrr_type(data & 0xff);
1193}
1194
9ba075a6
AK		 1195static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1196{
0bed3b56
SY		 1197 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1198
d6289b93 1199 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 1200 return 1;
1201
0bed3b56
SY		 1202 if (msr == MSR_MTRRdefType) {
1203 vcpu->arch.mtrr_state.def_type = data;
1204 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1205 } else if (msr == MSR_MTRRfix64K_00000)
1206 p[0] = data;
1207 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1208 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1209 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1210 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1211 else if (msr == MSR_IA32_CR_PAT)
1212 vcpu->arch.pat = data;
1213 else { /* Variable MTRRs */
1214 int idx, is_mtrr_mask;
1215 u64 *pt;
1216
1217 idx = (msr - 0x200) / 2;
1218 is_mtrr_mask = msr - 0x200 - 2 * idx;
1219 if (!is_mtrr_mask)
1220 pt =
1221 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1222 else
1223 pt =
1224 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1225 *pt = data;
1226 }
1227
1228 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 1229 return 0;
1230}
15c4a640 1231
890ca9ae 1232static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1233{
890ca9ae
HY		 1234 u64 mcg_cap = vcpu->arch.mcg_cap;
1235 unsigned bank_num = mcg_cap & 0xff;
1236
15c4a640 1237 switch (msr) {
15c4a640 1238 case MSR_IA32_MCG_STATUS:
890ca9ae 1239 vcpu->arch.mcg_status = data;
15c4a640 1240 break;
c7ac679c 1241 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1242 if (!(mcg_cap & MCG_CTL_P))
1243 return 1;
1244 if (data != 0 && data != ~(u64)0)
1245 return -1;
1246 vcpu->arch.mcg_ctl = data;
1247 break;
1248 default:
1249 if (msr >= MSR_IA32_MC0_CTL &&
1250 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1251 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1252 /* only 0 or all 1s can be written to IA32_MCi_CTL
1253 * some Linux kernels though clear bit 10 in bank 4 to
1254 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1255 * this to avoid an uncatched #GP in the guest
1256 */
890ca9ae 1257 if ((offset & 0x3) == 0 &&
114be429 1258 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1259 return -1;
1260 vcpu->arch.mce_banks[offset] = data;
1261 break;
1262 }
1263 return 1;
1264 }
1265 return 0;
1266}
1267
ffde22ac
ES		 1268static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1269{
1270 struct kvm *kvm = vcpu->kvm;
1271 int lm = is_long_mode(vcpu);
1272 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1273 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1274 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1275 : kvm->arch.xen_hvm_config.blob_size_32;
1276 u32 page_num = data & ~PAGE_MASK;
1277 u64 page_addr = data & PAGE_MASK;
1278 u8 *page;
1279 int r;
1280
1281 r = -E2BIG;
1282 if (page_num >= blob_size)
1283 goto out;
1284 r = -ENOMEM;
1285 page = kzalloc(PAGE_SIZE, GFP_KERNEL);
1286 if (!page)
1287 goto out;
1288 r = -EFAULT;
1289 if (copy_from_user(page, blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE))
1290 goto out_free;
1291 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1292 goto out_free;
1293 r = 0;
1294out_free:
1295 kfree(page);
1296out:
1297 return r;
1298}
1299
55cd8e5a
GN		 1300static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1301{
1302 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1303}
1304
1305static bool kvm_hv_msr_partition_wide(u32 msr)
1306{
1307 bool r = false;
1308 switch (msr) {
1309 case HV_X64_MSR_GUEST_OS_ID:
1310 case HV_X64_MSR_HYPERCALL:
1311 r = true;
1312 break;
1313 }
1314
1315 return r;
1316}
1317
1318static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1319{
1320 struct kvm *kvm = vcpu->kvm;
1321
1322 switch (msr) {
1323 case HV_X64_MSR_GUEST_OS_ID:
1324 kvm->arch.hv_guest_os_id = data;
1325 /* setting guest os id to zero disables hypercall page */
1326 if (!kvm->arch.hv_guest_os_id)
1327 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1328 break;
1329 case HV_X64_MSR_HYPERCALL: {
1330 u64 gfn;
1331 unsigned long addr;
1332 u8 instructions[4];
1333
1334 /* if guest os id is not set hypercall should remain disabled */
1335 if (!kvm->arch.hv_guest_os_id)
1336 break;
1337 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1338 kvm->arch.hv_hypercall = data;
1339 break;
1340 }
1341 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1342 addr = gfn_to_hva(kvm, gfn);
1343 if (kvm_is_error_hva(addr))
1344 return 1;
1345 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1346 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
1347 if (copy_to_user((void __user *)addr, instructions, 4))
1348 return 1;
1349 kvm->arch.hv_hypercall = data;
1350 break;
1351 }
1352 default:
1353 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1354 "data 0x%llx\n", msr, data);
1355 return 1;
1356 }
1357 return 0;
1358}
1359
1360static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1361{
10388a07
GN		 1362 switch (msr) {
1363 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1364 unsigned long addr;
55cd8e5a 1365
10388a07
GN		 1366 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1367 vcpu->arch.hv_vapic = data;
1368 break;
1369 }
1370 addr = gfn_to_hva(vcpu->kvm, data >>
1371 HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1372 if (kvm_is_error_hva(addr))
1373 return 1;
1374 if (clear_user((void __user *)addr, PAGE_SIZE))
1375 return 1;
1376 vcpu->arch.hv_vapic = data;
1377 break;
1378 }
1379 case HV_X64_MSR_EOI:
1380 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1381 case HV_X64_MSR_ICR:
1382 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1383 case HV_X64_MSR_TPR:
1384 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1385 default:
1386 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1387 "data 0x%llx\n", msr, data);
1388 return 1;
1389 }
1390
1391 return 0;
55cd8e5a
GN		 1392}
1393
15c4a640
CO		 1394int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1395{
1396 switch (msr) {
15c4a640 1397 case MSR_EFER:
b69e8cae 1398 return set_efer(vcpu, data);
8f1589d9
AP		 1399 case MSR_K7_HWCR:
1400 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 1401 data &= ~(u64)0x100; /* ignore ignne emulation enable */
8f1589d9
AP		 1402 if (data != 0) {
1403 pr_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1404 data);
1405 return 1;
1406 }
15c4a640 1407 break;
f7c6d140
AP		 1408 case MSR_FAM10H_MMIO_CONF_BASE:
1409 if (data != 0) {
1410 pr_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1411 "0x%llx\n", data);
1412 return 1;
1413 }
15c4a640 1414 break;
c323c0e5 1415 case MSR_AMD64_NB_CFG:
c7ac679c 1416 break;
b5e2fec0
AG		 1417 case MSR_IA32_DEBUGCTLMSR:
1418 if (!data) {
1419 /* We support the non-activated case already */
1420 break;
1421 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1422 /* Values other than LBR and BTF are vendor-specific,
1423 thus reserved and should throw a #GP */
1424 return 1;
1425 }
1426 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1427 __func__, data);
1428 break;
15c4a640
CO		 1429 case MSR_IA32_UCODE_REV:
1430 case MSR_IA32_UCODE_WRITE:
61a6bd67 1431 case MSR_VM_HSAVE_PA:
6098ca93 1432 case MSR_AMD64_PATCH_LOADER:
15c4a640 1433 break;
9ba075a6
AK		 1434 case 0x200 ... 0x2ff:
1435 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 1436 case MSR_IA32_APICBASE:
1437 kvm_set_apic_base(vcpu, data);
1438 break;
0105d1a5
GN		 1439 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1440 return kvm_x2apic_msr_write(vcpu, msr, data);
15c4a640 1441 case MSR_IA32_MISC_ENABLE:
ad312c7c 1442 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 1443 break;
11c6bffa 1444 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1445 case MSR_KVM_WALL_CLOCK:
1446 vcpu->kvm->arch.wall_clock = data;
1447 kvm_write_wall_clock(vcpu->kvm, data);
1448 break;
11c6bffa 1449 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 1450 case MSR_KVM_SYSTEM_TIME: {
1451 if (vcpu->arch.time_page) {
1452 kvm_release_page_dirty(vcpu->arch.time_page);
1453 vcpu->arch.time_page = NULL;
1454 }
1455
1456 vcpu->arch.time = data;
1457
1458 /* we verify if the enable bit is set... */
1459 if (!(data & 1))
1460 break;
1461
1462 /* ...but clean it before doing the actual write */
1463 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
1464
18068523
GOC		 1465 vcpu->arch.time_page =
1466 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
18068523
GOC		 1467
1468 if (is_error_page(vcpu->arch.time_page)) {
1469 kvm_release_page_clean(vcpu->arch.time_page);
1470 vcpu->arch.time_page = NULL;
1471 }
1472
c8076604 1473 kvm_request_guest_time_update(vcpu);
18068523
GOC		 1474 break;
1475 }
890ca9ae
HY		 1476 case MSR_IA32_MCG_CTL:
1477 case MSR_IA32_MCG_STATUS:
1478 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1479 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 1480
1481 /* Performance counters are not protected by a CPUID bit,
1482 * so we should check all of them in the generic path for the sake of
1483 * cross vendor migration.
1484 * Writing a zero into the event select MSRs disables them,
1485 * which we perfectly emulate ;-). Any other value should be at least
1486 * reported, some guests depend on them.
1487 */
1488 case MSR_P6_EVNTSEL0:
1489 case MSR_P6_EVNTSEL1:
1490 case MSR_K7_EVNTSEL0:
1491 case MSR_K7_EVNTSEL1:
1492 case MSR_K7_EVNTSEL2:
1493 case MSR_K7_EVNTSEL3:
1494 if (data != 0)
1495 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1496 "0x%x data 0x%llx\n", msr, data);
1497 break;
1498 /* at least RHEL 4 unconditionally writes to the perfctr registers,
1499 * so we ignore writes to make it happy.
1500 */
1501 case MSR_P6_PERFCTR0:
1502 case MSR_P6_PERFCTR1:
1503 case MSR_K7_PERFCTR0:
1504 case MSR_K7_PERFCTR1:
1505 case MSR_K7_PERFCTR2:
1506 case MSR_K7_PERFCTR3:
1507 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1508 "0x%x data 0x%llx\n", msr, data);
1509 break;
84e0cefa
JS		 1510 case MSR_K7_CLK_CTL:
1511 /*
1512 * Ignore all writes to this no longer documented MSR.
1513 * Writes are only relevant for old K7 processors,
1514 * all pre-dating SVM, but a recommended workaround from
1515 * AMD for these chips. It is possible to speicify the
1516 * affected processor models on the command line, hence
1517 * the need to ignore the workaround.
1518 */
1519 break;
55cd8e5a
GN		 1520 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1521 if (kvm_hv_msr_partition_wide(msr)) {
1522 int r;
1523 mutex_lock(&vcpu->kvm->lock);
1524 r = set_msr_hyperv_pw(vcpu, msr, data);
1525 mutex_unlock(&vcpu->kvm->lock);
1526 return r;
1527 } else
1528 return set_msr_hyperv(vcpu, msr, data);
1529 break;
15c4a640 1530 default:
ffde22ac
ES		 1531 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
1532 return xen_hvm_config(vcpu, data);
ed85c068
AP		 1533 if (!ignore_msrs) {
1534 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
1535 msr, data);
1536 return 1;
1537 } else {
1538 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
1539 msr, data);
1540 break;
1541 }
15c4a640
CO		 1542 }
1543 return 0;
1544}
1545EXPORT_SYMBOL_GPL(kvm_set_msr_common);
1546
1547
1548/*
1549 * Reads an msr value (of 'msr_index') into 'pdata'.
1550 * Returns 0 on success, non-0 otherwise.
1551 * Assumes vcpu_load() was already called.
1552 */
1553int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1554{
1555 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
1556}
1557
9ba075a6
AK		 1558static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1559{
0bed3b56
SY		 1560 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1561
9ba075a6
AK		 1562 if (!msr_mtrr_valid(msr))
1563 return 1;
1564
0bed3b56
SY		 1565 if (msr == MSR_MTRRdefType)
1566 *pdata = vcpu->arch.mtrr_state.def_type +
1567 (vcpu->arch.mtrr_state.enabled << 10);
1568 else if (msr == MSR_MTRRfix64K_00000)
1569 *pdata = p[0];
1570 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1571 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
1572 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1573 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
1574 else if (msr == MSR_IA32_CR_PAT)
1575 *pdata = vcpu->arch.pat;
1576 else { /* Variable MTRRs */
1577 int idx, is_mtrr_mask;
1578 u64 *pt;
1579
1580 idx = (msr - 0x200) / 2;
1581 is_mtrr_mask = msr - 0x200 - 2 * idx;
1582 if (!is_mtrr_mask)
1583 pt =
1584 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1585 else
1586 pt =
1587 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1588 *pdata = *pt;
1589 }
1590
9ba075a6
AK		 1591 return 0;
1592}
1593
890ca9ae 1594static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 1595{
1596 u64 data;
890ca9ae
HY		 1597 u64 mcg_cap = vcpu->arch.mcg_cap;
1598 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 1599
1600 switch (msr) {
15c4a640
CO		 1601 case MSR_IA32_P5_MC_ADDR:
1602 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 1603 data = 0;
1604 break;
15c4a640 1605 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 1606 data = vcpu->arch.mcg_cap;
1607 break;
c7ac679c 1608 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1609 if (!(mcg_cap & MCG_CTL_P))
1610 return 1;
1611 data = vcpu->arch.mcg_ctl;
1612 break;
1613 case MSR_IA32_MCG_STATUS:
1614 data = vcpu->arch.mcg_status;
1615 break;
1616 default:
1617 if (msr >= MSR_IA32_MC0_CTL &&
1618 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1619 u32 offset = msr - MSR_IA32_MC0_CTL;
1620 data = vcpu->arch.mce_banks[offset];
1621 break;
1622 }
1623 return 1;
1624 }
1625 *pdata = data;
1626 return 0;
1627}
1628
55cd8e5a
GN		 1629static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1630{
1631 u64 data = 0;
1632 struct kvm *kvm = vcpu->kvm;
1633
1634 switch (msr) {
1635 case HV_X64_MSR_GUEST_OS_ID:
1636 data = kvm->arch.hv_guest_os_id;
1637 break;
1638 case HV_X64_MSR_HYPERCALL:
1639 data = kvm->arch.hv_hypercall;
1640 break;
1641 default:
1642 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1643 return 1;
1644 }
1645
1646 *pdata = data;
1647 return 0;
1648}
1649
1650static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1651{
1652 u64 data = 0;
1653
1654 switch (msr) {
1655 case HV_X64_MSR_VP_INDEX: {
1656 int r;
1657 struct kvm_vcpu *v;
1658 kvm_for_each_vcpu(r, v, vcpu->kvm)
1659 if (v == vcpu)
1660 data = r;
1661 break;
1662 }
10388a07
GN		 1663 case HV_X64_MSR_EOI:
1664 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
1665 case HV_X64_MSR_ICR:
1666 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
1667 case HV_X64_MSR_TPR:
1668 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
55cd8e5a
GN		 1669 default:
1670 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1671 return 1;
1672 }
1673 *pdata = data;
1674 return 0;
1675}
1676
890ca9ae
HY		 1677int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1678{
1679 u64 data;
1680
1681 switch (msr) {
890ca9ae 1682 case MSR_IA32_PLATFORM_ID:
15c4a640 1683 case MSR_IA32_UCODE_REV:
15c4a640 1684 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 1685 case MSR_IA32_DEBUGCTLMSR:
1686 case MSR_IA32_LASTBRANCHFROMIP:
1687 case MSR_IA32_LASTBRANCHTOIP:
1688 case MSR_IA32_LASTINTFROMIP:
1689 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 1690 case MSR_K8_SYSCFG:
1691 case MSR_K7_HWCR:
61a6bd67 1692 case MSR_VM_HSAVE_PA:
1f3ee616
AS		 1693 case MSR_P6_PERFCTR0:
1694 case MSR_P6_PERFCTR1:
7fe29e0f
AS		 1695 case MSR_P6_EVNTSEL0:
1696 case MSR_P6_EVNTSEL1:
9e699624 1697 case MSR_K7_EVNTSEL0:
1f3ee616 1698 case MSR_K7_PERFCTR0:
1fdbd48c 1699 case MSR_K8_INT_PENDING_MSG:
c323c0e5 1700 case MSR_AMD64_NB_CFG:
f7c6d140 1701 case MSR_FAM10H_MMIO_CONF_BASE:
15c4a640
CO		 1702 data = 0;
1703 break;
9ba075a6
AK		 1704 case MSR_MTRRcap:
1705 data = 0x500 | KVM_NR_VAR_MTRR;
1706 break;
1707 case 0x200 ... 0x2ff:
1708 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 1709 case 0xcd: /* fsb frequency */
1710 data = 3;
1711 break;
7b914098
JS		 1712 /*
1713 * MSR_EBC_FREQUENCY_ID
1714 * Conservative value valid for even the basic CPU models.
1715 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
1716 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
1717 * and 266MHz for model 3, or 4. Set Core Clock
1718 * Frequency to System Bus Frequency Ratio to 1 (bits
1719 * 31:24) even though these are only valid for CPU
1720 * models > 2, however guests may end up dividing or
1721 * multiplying by zero otherwise.
1722 */
1723 case MSR_EBC_FREQUENCY_ID:
1724 data = 1 << 24;
1725 break;
15c4a640
CO		 1726 case MSR_IA32_APICBASE:
1727 data = kvm_get_apic_base(vcpu);
1728 break;
0105d1a5
GN		 1729 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1730 return kvm_x2apic_msr_read(vcpu, msr, pdata);
1731 break;
15c4a640 1732 case MSR_IA32_MISC_ENABLE:
ad312c7c 1733 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 1734 break;
847f0ad8
AG		 1735 case MSR_IA32_PERF_STATUS:
1736 /* TSC increment by tick */
1737 data = 1000ULL;
1738 /* CPU multiplier */
1739 data |= (((uint64_t)4ULL) << 40);
1740 break;
15c4a640 1741 case MSR_EFER:
f6801dff 1742 data = vcpu->arch.efer;
15c4a640 1743 break;
18068523 1744 case MSR_KVM_WALL_CLOCK:
11c6bffa 1745 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1746 data = vcpu->kvm->arch.wall_clock;
1747 break;
1748 case MSR_KVM_SYSTEM_TIME:
11c6bffa 1749 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 1750 data = vcpu->arch.time;
1751 break;
890ca9ae
HY		 1752 case MSR_IA32_P5_MC_ADDR:
1753 case MSR_IA32_P5_MC_TYPE:
1754 case MSR_IA32_MCG_CAP:
1755 case MSR_IA32_MCG_CTL:
1756 case MSR_IA32_MCG_STATUS:
1757 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1758 return get_msr_mce(vcpu, msr, pdata);
84e0cefa
JS		 1759 case MSR_K7_CLK_CTL:
1760 /*
1761 * Provide expected ramp-up count for K7. All other
1762 * are set to zero, indicating minimum divisors for
1763 * every field.
1764 *
1765 * This prevents guest kernels on AMD host with CPU
1766 * type 6, model 8 and higher from exploding due to
1767 * the rdmsr failing.
1768 */
1769 data = 0x20000000;
1770 break;
55cd8e5a
GN		 1771 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1772 if (kvm_hv_msr_partition_wide(msr)) {
1773 int r;
1774 mutex_lock(&vcpu->kvm->lock);
1775 r = get_msr_hyperv_pw(vcpu, msr, pdata);
1776 mutex_unlock(&vcpu->kvm->lock);
1777 return r;
1778 } else
1779 return get_msr_hyperv(vcpu, msr, pdata);
1780 break;
15c4a640 1781 default:
ed85c068
AP		 1782 if (!ignore_msrs) {
1783 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
1784 return 1;
1785 } else {
1786 pr_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
1787 data = 0;
1788 }
1789 break;
15c4a640
CO		 1790 }
1791 *pdata = data;
1792 return 0;
1793}
1794EXPORT_SYMBOL_GPL(kvm_get_msr_common);
1795
313a3dc7
CO		 1796/*
1797 * Read or write a bunch of msrs. All parameters are kernel addresses.
1798 *
1799 * @return number of msrs set successfully.
1800 */
1801static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
1802 struct kvm_msr_entry *entries,
1803 int (*do_msr)(struct kvm_vcpu *vcpu,
1804 unsigned index, u64 *data))
1805{
f656ce01 1806 int i, idx;
313a3dc7 1807
f656ce01 1808 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 1809 for (i = 0; i < msrs->nmsrs; ++i)
1810 if (do_msr(vcpu, entries[i].index, &entries[i].data))
1811 break;
f656ce01 1812 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 1813
313a3dc7
CO		 1814 return i;
1815}
1816
1817/*
1818 * Read or write a bunch of msrs. Parameters are user addresses.
1819 *
1820 * @return number of msrs set successfully.
1821 */
1822static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
1823 int (*do_msr)(struct kvm_vcpu *vcpu,
1824 unsigned index, u64 *data),
1825 int writeback)
1826{
1827 struct kvm_msrs msrs;
1828 struct kvm_msr_entry *entries;
1829 int r, n;
1830 unsigned size;
1831
1832 r = -EFAULT;
1833 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
1834 goto out;
1835
1836 r = -E2BIG;
1837 if (msrs.nmsrs >= MAX_IO_MSRS)
1838 goto out;
1839
1840 r = -ENOMEM;
1841 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
7a73c028 1842 entries = kmalloc(size, GFP_KERNEL);
313a3dc7
CO		 1843 if (!entries)
1844 goto out;
1845
1846 r = -EFAULT;
1847 if (copy_from_user(entries, user_msrs->entries, size))
1848 goto out_free;
1849
1850 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
1851 if (r < 0)
1852 goto out_free;
1853
1854 r = -EFAULT;
1855 if (writeback && copy_to_user(user_msrs->entries, entries, size))
1856 goto out_free;
1857
1858 r = n;
1859
1860out_free:
7a73c028 1861 kfree(entries);
313a3dc7
CO		 1862out:
1863 return r;
1864}
1865
018d00d2
ZX		 1866int kvm_dev_ioctl_check_extension(long ext)
1867{
1868 int r;
1869
1870 switch (ext) {
1871 case KVM_CAP_IRQCHIP:
1872 case KVM_CAP_HLT:
1873 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 1874 case KVM_CAP_SET_TSS_ADDR:
07716717 1875 case KVM_CAP_EXT_CPUID:
c8076604 1876 case KVM_CAP_CLOCKSOURCE:
7837699f 1877 case KVM_CAP_PIT:
a28e4f5a 1878 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 1879 case KVM_CAP_MP_STATE:
ed848624 1880 case KVM_CAP_SYNC_MMU:
52d939a0 1881 case KVM_CAP_REINJECT_CONTROL:
4925663a 1882 case KVM_CAP_IRQ_INJECT_STATUS:
e56d532f 1883 case KVM_CAP_ASSIGN_DEV_IRQ:
721eecbf 1884 case KVM_CAP_IRQFD:
d34e6b17 1885 case KVM_CAP_IOEVENTFD:
c5ff41ce 1886 case KVM_CAP_PIT2:
e9f42757 1887 case KVM_CAP_PIT_STATE2:
b927a3ce 1888 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 1889 case KVM_CAP_XEN_HVM:
afbcf7ab 1890 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 1891 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 1892 case KVM_CAP_HYPERV:
10388a07 1893 case KVM_CAP_HYPERV_VAPIC:
c25bc163 1894 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 1895 case KVM_CAP_PCI_SEGMENT:
a1efbe77 1896 case KVM_CAP_DEBUGREGS:
d2be1651 1897 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 1898 case KVM_CAP_XSAVE:
018d00d2
ZX		 1899 r = 1;
1900 break;
542472b5
LV		 1901 case KVM_CAP_COALESCED_MMIO:
1902 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
1903 break;
774ead3a
AK		 1904 case KVM_CAP_VAPIC:
1905 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
1906 break;
f725230a
AK		 1907 case KVM_CAP_NR_VCPUS:
1908 r = KVM_MAX_VCPUS;
1909 break;
a988b910
AK		 1910 case KVM_CAP_NR_MEMSLOTS:
1911 r = KVM_MEMORY_SLOTS;
1912 break;
a68a6a72
MT		 1913 case KVM_CAP_PV_MMU: /* obsolete */
1914 r = 0;
2f333bcb 1915 break;
62c476c7 1916 case KVM_CAP_IOMMU:
19de40a8 1917 r = iommu_found();
62c476c7 1918 break;
890ca9ae
HY		 1919 case KVM_CAP_MCE:
1920 r = KVM_MAX_MCE_BANKS;
1921 break;
2d5b5a66
SY		 1922 case KVM_CAP_XCRS:
1923 r = cpu_has_xsave;
1924 break;
018d00d2
ZX		 1925 default:
1926 r = 0;
1927 break;
1928 }
1929 return r;
1930
1931}
1932
043405e1
CO		 1933long kvm_arch_dev_ioctl(struct file *filp,
1934 unsigned int ioctl, unsigned long arg)
1935{
1936 void __user *argp = (void __user *)arg;
1937 long r;
1938
1939 switch (ioctl) {
1940 case KVM_GET_MSR_INDEX_LIST: {
1941 struct kvm_msr_list __user *user_msr_list = argp;
1942 struct kvm_msr_list msr_list;
1943 unsigned n;
1944
1945 r = -EFAULT;
1946 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
1947 goto out;
1948 n = msr_list.nmsrs;
1949 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
1950 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
1951 goto out;
1952 r = -E2BIG;
e125e7b6 1953 if (n < msr_list.nmsrs)
043405e1
CO		 1954 goto out;
1955 r = -EFAULT;
1956 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
1957 num_msrs_to_save * sizeof(u32)))
1958 goto out;
e125e7b6 1959 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 1960 &emulated_msrs,
1961 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
1962 goto out;
1963 r = 0;
1964 break;
1965 }
674eea0f
AK		 1966 case KVM_GET_SUPPORTED_CPUID: {
1967 struct kvm_cpuid2 __user *cpuid_arg = argp;
1968 struct kvm_cpuid2 cpuid;
1969
1970 r = -EFAULT;
1971 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1972 goto out;
1973 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
19355475 1974 cpuid_arg->entries);
674eea0f
AK		 1975 if (r)
1976 goto out;
1977
1978 r = -EFAULT;
1979 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
1980 goto out;
1981 r = 0;
1982 break;
1983 }
890ca9ae
HY		 1984 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
1985 u64 mce_cap;
1986
1987 mce_cap = KVM_MCE_CAP_SUPPORTED;
1988 r = -EFAULT;
1989 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
1990 goto out;
1991 r = 0;
1992 break;
1993 }
043405e1
CO		 1994 default:
1995 r = -EINVAL;
1996 }
1997out:
1998 return r;
1999}
2000
f5f48ee1
SY		 2001static void wbinvd_ipi(void *garbage)
2002{
2003 wbinvd();
2004}
2005
2006static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2007{
2008 return vcpu->kvm->arch.iommu_domain &&
2009 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY);
2010}
2011
313a3dc7
CO		 2012void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2013{
f5f48ee1
SY		 2014 /* Address WBINVD may be executed by guest */
2015 if (need_emulate_wbinvd(vcpu)) {
2016 if (kvm_x86_ops->has_wbinvd_exit())
2017 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2018 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2019 smp_call_function_single(vcpu->cpu,
2020 wbinvd_ipi, NULL, 1);
2021 }
2022
313a3dc7 2023 kvm_x86_ops->vcpu_load(vcpu, cpu);
48434c20 2024 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
e48672fa
ZA		 2025 /* Make sure TSC doesn't go backwards */
2026 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2027 native_read_tsc() - vcpu->arch.last_host_tsc;
2028 if (tsc_delta < 0)
2029 mark_tsc_unstable("KVM discovered backwards TSC");
2030 if (check_tsc_unstable())
2031 kvm_x86_ops->adjust_tsc_offset(vcpu, -tsc_delta);
2032 kvm_migrate_timers(vcpu);
2033 vcpu->cpu = cpu;
2034 }
313a3dc7
CO		 2035}
2036
2037void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2038{
02daab21 2039 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2040 kvm_put_guest_fpu(vcpu);
e48672fa 2041 vcpu->arch.last_host_tsc = native_read_tsc();
313a3dc7
CO		 2042}
2043
07716717 2044static int is_efer_nx(void)
313a3dc7 2045{
e286e86e 2046 unsigned long long efer = 0;
313a3dc7 2047
e286e86e 2048 rdmsrl_safe(MSR_EFER, &efer);
07716717
DK		 2049 return efer & EFER_NX;
2050}
2051
2052static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
2053{
2054 int i;
2055 struct kvm_cpuid_entry2 *e, *entry;
2056
313a3dc7 2057 entry = NULL;
ad312c7c
ZX		 2058 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
2059 e = &vcpu->arch.cpuid_entries[i];
313a3dc7
CO		 2060 if (e->function == 0x80000001) {
2061 entry = e;
2062 break;
2063 }
2064 }
07716717 2065 if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) {
313a3dc7
CO		 2066 entry->edx &= ~(1 << 20);
2067 printk(KERN_INFO "kvm: guest NX capability removed\n");
2068 }
2069}
2070
07716717 2071/* when an old userspace process fills a new kernel module */
313a3dc7
CO		 2072static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
2073 struct kvm_cpuid *cpuid,
2074 struct kvm_cpuid_entry __user *entries)
07716717
DK		 2075{
2076 int r, i;
2077 struct kvm_cpuid_entry *cpuid_entries;
2078
2079 r = -E2BIG;
2080 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2081 goto out;
2082 r = -ENOMEM;
2083 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent);
2084 if (!cpuid_entries)
2085 goto out;
2086 r = -EFAULT;
2087 if (copy_from_user(cpuid_entries, entries,
2088 cpuid->nent * sizeof(struct kvm_cpuid_entry)))
2089 goto out_free;
2090 for (i = 0; i < cpuid->nent; i++) {
ad312c7c
ZX		 2091 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
2092 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
2093 vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx;
2094 vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx;
2095 vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx;
2096 vcpu->arch.cpuid_entries[i].index = 0;
2097 vcpu->arch.cpuid_entries[i].flags = 0;
2098 vcpu->arch.cpuid_entries[i].padding[0] = 0;
2099 vcpu->arch.cpuid_entries[i].padding[1] = 0;
2100 vcpu->arch.cpuid_entries[i].padding[2] = 0;
2101 }
2102 vcpu->arch.cpuid_nent = cpuid->nent;
07716717
DK		 2103 cpuid_fix_nx_cap(vcpu);
2104 r = 0;
fc61b800 2105 kvm_apic_set_version(vcpu);
0e851880 2106 kvm_x86_ops->cpuid_update(vcpu);
2acf923e 2107 update_cpuid(vcpu);
07716717
DK		 2108
2109out_free:
2110 vfree(cpuid_entries);
2111out:
2112 return r;
2113}
2114
2115static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 2116 struct kvm_cpuid2 *cpuid,
2117 struct kvm_cpuid_entry2 __user *entries)
313a3dc7
CO		 2118{
2119 int r;
2120
2121 r = -E2BIG;
2122 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2123 goto out;
2124 r = -EFAULT;
ad312c7c 2125 if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
07716717 2126 cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
313a3dc7 2127 goto out;
ad312c7c 2128 vcpu->arch.cpuid_nent = cpuid->nent;
fc61b800 2129 kvm_apic_set_version(vcpu);
0e851880 2130 kvm_x86_ops->cpuid_update(vcpu);
2acf923e 2131 update_cpuid(vcpu);
313a3dc7
CO		 2132 return 0;
2133
2134out:
2135 return r;
2136}
2137
07716717 2138static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 2139 struct kvm_cpuid2 *cpuid,
2140 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 2141{
2142 int r;
2143
2144 r = -E2BIG;
ad312c7c 2145 if (cpuid->nent < vcpu->arch.cpuid_nent)
07716717
DK		 2146 goto out;
2147 r = -EFAULT;
ad312c7c 2148 if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
19355475 2149 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 2150 goto out;
2151 return 0;
2152
2153out:
ad312c7c 2154 cpuid->nent = vcpu->arch.cpuid_nent;
07716717
DK		 2155 return r;
2156}
2157
07716717 2158static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function,
19355475 2159 u32 index)
07716717
DK		 2160{
2161 entry->function = function;
2162 entry->index = index;
2163 cpuid_count(entry->function, entry->index,
19355475 2164 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
07716717
DK		 2165 entry->flags = 0;
2166}
2167
7faa4ee1
AK		 2168#define F(x) bit(X86_FEATURE_##x)
2169
07716717
DK		 2170static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
2171 u32 index, int *nent, int maxnent)
2172{
7faa4ee1 2173 unsigned f_nx = is_efer_nx() ? F(NX) : 0;
07716717 2174#ifdef CONFIG_X86_64
17cc3935
SY		 2175 unsigned f_gbpages = (kvm_x86_ops->get_lpage_level() == PT_PDPE_LEVEL)
2176 ? F(GBPAGES) : 0;
7faa4ee1
AK		 2177 unsigned f_lm = F(LM);
2178#else
17cc3935 2179 unsigned f_gbpages = 0;
7faa4ee1 2180 unsigned f_lm = 0;
07716717 2181#endif
4e47c7a6 2182 unsigned f_rdtscp = kvm_x86_ops->rdtscp_supported() ? F(RDTSCP) : 0;
7faa4ee1
AK		 2183
2184 /* cpuid 1.edx */
2185 const u32 kvm_supported_word0_x86_features =
2186 F(FPU) | F(VME) | F(DE) | F(PSE) |
2187 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
2188 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) |
2189 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
2190 F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLSH) |
2191 0 /* Reserved, DS, ACPI */ | F(MMX) |
2192 F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) |
2193 0 /* HTT, TM, Reserved, PBE */;
2194 /* cpuid 0x80000001.edx */
2195 const u32 kvm_supported_word1_x86_features =
2196 F(FPU) | F(VME) | F(DE) | F(PSE) |
2197 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
2198 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) |
2199 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
2200 F(PAT) | F(PSE36) | 0 /* Reserved */ |
2201 f_nx | 0 /* Reserved */ | F(MMXEXT) | F(MMX) |
4e47c7a6 2202 F(FXSR) | F(FXSR_OPT) | f_gbpages | f_rdtscp |
7faa4ee1
AK		 2203 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW);
2204 /* cpuid 1.ecx */
2205 const u32 kvm_supported_word4_x86_features =
6c3f6041 2206 F(XMM3) | F(PCLMULQDQ) | 0 /* DTES64, MONITOR */ |
d149c731
AK		 2207 0 /* DS-CPL, VMX, SMX, EST */ |
2208 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ |
2209 0 /* Reserved */ | F(CX16) | 0 /* xTPR Update, PDCM */ |
2210 0 /* Reserved, DCA */ | F(XMM4_1) |
0105d1a5 2211 F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) |
6c3f6041 2212 0 /* Reserved, AES */ | F(XSAVE) | 0 /* OSXSAVE */ | F(AVX);
7faa4ee1 2213 /* cpuid 0x80000001.ecx */
07716717 2214 const u32 kvm_supported_word6_x86_features =
4c62a2dc 2215 F(LAHF_LM) | F(CMP_LEGACY) | 0 /*SVM*/ | 0 /* ExtApicSpace */ |
7faa4ee1
AK		 2216 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) |
2217 F(3DNOWPREFETCH) | 0 /* OSVW */ | 0 /* IBS */ | F(SSE5) |
2218 0 /* SKINIT */ | 0 /* WDT */;
07716717 2219
19355475 2220 /* all calls to cpuid_count() should be made on the same cpu */
07716717
DK		 2221 get_cpu();
2222 do_cpuid_1_ent(entry, function, index);
2223 ++*nent;
2224
2225 switch (function) {
2226 case 0:
2acf923e 2227 entry->eax = min(entry->eax, (u32)0xd);
07716717
DK		 2228 break;
2229 case 1:
2230 entry->edx &= kvm_supported_word0_x86_features;
7faa4ee1 2231 entry->ecx &= kvm_supported_word4_x86_features;
0d1de2d9
GN		 2232 /* we support x2apic emulation even if host does not support
2233 * it since we emulate x2apic in software */
2234 entry->ecx |= F(X2APIC);
07716717
DK		 2235 break;
2236 /* function 2 entries are STATEFUL. That is, repeated cpuid commands
2237 * may return different values. This forces us to get_cpu() before
2238 * issuing the first command, and also to emulate this annoying behavior
2239 * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */
2240 case 2: {
2241 int t, times = entry->eax & 0xff;
2242
2243 entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
0fdf8e59 2244 entry->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
07716717
DK		 2245 for (t = 1; t < times && *nent < maxnent; ++t) {
2246 do_cpuid_1_ent(&entry[t], function, 0);
2247 entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
2248 ++*nent;
2249 }
2250 break;
2251 }
2252 /* function 4 and 0xb have additional index. */
2253 case 4: {
14af3f3c 2254 int i, cache_type;
07716717
DK		 2255
2256 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2257 /* read more entries until cache_type is zero */
14af3f3c
HH		 2258 for (i = 1; *nent < maxnent; ++i) {
2259 cache_type = entry[i - 1].eax & 0x1f;
07716717
DK		 2260 if (!cache_type)
2261 break;
14af3f3c
HH		 2262 do_cpuid_1_ent(&entry[i], function, i);
2263 entry[i].flags |=
07716717
DK		 2264 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2265 ++*nent;
2266 }
2267 break;
2268 }
2269 case 0xb: {
14af3f3c 2270 int i, level_type;
07716717
DK		 2271
2272 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2273 /* read more entries until level_type is zero */
14af3f3c 2274 for (i = 1; *nent < maxnent; ++i) {
0853d2c1 2275 level_type = entry[i - 1].ecx & 0xff00;
07716717
DK		 2276 if (!level_type)
2277 break;
14af3f3c
HH		 2278 do_cpuid_1_ent(&entry[i], function, i);
2279 entry[i].flags |=
07716717
DK		 2280 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2281 ++*nent;
2282 }
2283 break;
2284 }
2acf923e
DC		 2285 case 0xd: {
2286 int i;
2287
2288 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2289 for (i = 1; *nent < maxnent; ++i) {
2290 if (entry[i - 1].eax == 0 && i != 2)
2291 break;
2292 do_cpuid_1_ent(&entry[i], function, i);
2293 entry[i].flags |=
2294 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2295 ++*nent;
2296 }
2297 break;
2298 }
84478c82
GC		 2299 case KVM_CPUID_SIGNATURE: {
2300 char signature[12] = "KVMKVMKVM\0\0";
2301 u32 *sigptr = (u32 *)signature;
2302 entry->eax = 0;
2303 entry->ebx = sigptr[0];
2304 entry->ecx = sigptr[1];
2305 entry->edx = sigptr[2];
2306 break;
2307 }
2308 case KVM_CPUID_FEATURES:
2309 entry->eax = (1 << KVM_FEATURE_CLOCKSOURCE) |
2310 (1 << KVM_FEATURE_NOP_IO_DELAY) |
371bcf64
GC		 2311 (1 << KVM_FEATURE_CLOCKSOURCE2) |
2312 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT);
84478c82
GC		 2313 entry->ebx = 0;
2314 entry->ecx = 0;
2315 entry->edx = 0;
2316 break;
07716717
DK		 2317 case 0x80000000:
2318 entry->eax = min(entry->eax, 0x8000001a);
2319 break;
2320 case 0x80000001:
2321 entry->edx &= kvm_supported_word1_x86_features;
2322 entry->ecx &= kvm_supported_word6_x86_features;
2323 break;
2324 }
d4330ef2
JR		 2325
2326 kvm_x86_ops->set_supported_cpuid(function, entry);
2327
07716717
DK		 2328 put_cpu();
2329}
2330
7faa4ee1
AK		 2331#undef F
2332
674eea0f 2333static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
19355475 2334 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 2335{
2336 struct kvm_cpuid_entry2 *cpuid_entries;
2337 int limit, nent = 0, r = -E2BIG;
2338 u32 func;
2339
2340 if (cpuid->nent < 1)
2341 goto out;
6a544355
AK		 2342 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2343 cpuid->nent = KVM_MAX_CPUID_ENTRIES;
07716717
DK		 2344 r = -ENOMEM;
2345 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent);
2346 if (!cpuid_entries)
2347 goto out;
2348
2349 do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent);
2350 limit = cpuid_entries[0].eax;
2351 for (func = 1; func <= limit && nent < cpuid->nent; ++func)
2352 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 2353 &nent, cpuid->nent);
07716717
DK		 2354 r = -E2BIG;
2355 if (nent >= cpuid->nent)
2356 goto out_free;
2357
2358 do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent);
2359 limit = cpuid_entries[nent - 1].eax;
2360 for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func)
2361 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 2362 &nent, cpuid->nent);
84478c82
GC		 2363
2364
2365
2366 r = -E2BIG;
2367 if (nent >= cpuid->nent)
2368 goto out_free;
2369
2370 do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_SIGNATURE, 0, &nent,
2371 cpuid->nent);
2372
2373 r = -E2BIG;
2374 if (nent >= cpuid->nent)
2375 goto out_free;
2376
2377 do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_FEATURES, 0, &nent,
2378 cpuid->nent);
2379
cb007648
MM		 2380 r = -E2BIG;
2381 if (nent >= cpuid->nent)
2382 goto out_free;
2383
07716717
DK		 2384 r = -EFAULT;
2385 if (copy_to_user(entries, cpuid_entries,
19355475 2386 nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 2387 goto out_free;
2388 cpuid->nent = nent;
2389 r = 0;
2390
2391out_free:
2392 vfree(cpuid_entries);
2393out:
2394 return r;
2395}
2396
313a3dc7
CO		 2397static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2398 struct kvm_lapic_state *s)
2399{
ad312c7c 2400 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2401
2402 return 0;
2403}
2404
2405static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2406 struct kvm_lapic_state *s)
2407{
ad312c7c 2408 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
313a3dc7 2409 kvm_apic_post_state_restore(vcpu);
cb142eb7 2410 update_cr8_intercept(vcpu);
313a3dc7
CO		 2411
2412 return 0;
2413}
2414
f77bc6a4
ZX		 2415static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2416 struct kvm_interrupt *irq)
2417{
2418 if (irq->irq < 0 || irq->irq >= 256)
2419 return -EINVAL;
2420 if (irqchip_in_kernel(vcpu->kvm))
2421 return -ENXIO;
f77bc6a4 2422
66fd3f7f 2423 kvm_queue_interrupt(vcpu, irq->irq, false);
3842d135 2424 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4 2425
f77bc6a4
ZX		 2426 return 0;
2427}
2428
c4abb7c9
JK		 2429static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2430{
c4abb7c9 2431 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2432
2433 return 0;
2434}
2435
b209749f
AK		 2436static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2437 struct kvm_tpr_access_ctl *tac)
2438{
2439 if (tac->flags)
2440 return -EINVAL;
2441 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2442 return 0;
2443}
2444
890ca9ae
HY		 2445static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2446 u64 mcg_cap)
2447{
2448 int r;
2449 unsigned bank_num = mcg_cap & 0xff, bank;
2450
2451 r = -EINVAL;
a9e38c3e 2452 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2453 goto out;
2454 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2455 goto out;
2456 r = 0;
2457 vcpu->arch.mcg_cap = mcg_cap;
2458 /* Init IA32_MCG_CTL to all 1s */
2459 if (mcg_cap & MCG_CTL_P)
2460 vcpu->arch.mcg_ctl = ~(u64)0;
2461 /* Init IA32_MCi_CTL to all 1s */
2462 for (bank = 0; bank < bank_num; bank++)
2463 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2464out:
2465 return r;
2466}
2467
2468static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2469 struct kvm_x86_mce *mce)
2470{
2471 u64 mcg_cap = vcpu->arch.mcg_cap;
2472 unsigned bank_num = mcg_cap & 0xff;
2473 u64 *banks = vcpu->arch.mce_banks;
2474
2475 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2476 return -EINVAL;
2477 /*
2478 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2479 * reporting is disabled
2480 */
2481 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2482 vcpu->arch.mcg_ctl != ~(u64)0)
2483 return 0;
2484 banks += 4 * mce->bank;
2485 /*
2486 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2487 * reporting is disabled for the bank
2488 */
2489 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2490 return 0;
2491 if (mce->status & MCI_STATUS_UC) {
2492 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2493 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
890ca9ae
HY		 2494 printk(KERN_DEBUG "kvm: set_mce: "
2495 "injects mce exception while "
2496 "previous one is in progress!\n");
a8eeb04a 2497 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2498 return 0;
2499 }
2500 if (banks[1] & MCI_STATUS_VAL)
2501 mce->status |= MCI_STATUS_OVER;
2502 banks[2] = mce->addr;
2503 banks[3] = mce->misc;
2504 vcpu->arch.mcg_status = mce->mcg_status;
2505 banks[1] = mce->status;
2506 kvm_queue_exception(vcpu, MC_VECTOR);
2507 } else if (!(banks[1] & MCI_STATUS_VAL)
2508 || !(banks[1] & MCI_STATUS_UC)) {
2509 if (banks[1] & MCI_STATUS_VAL)
2510 mce->status |= MCI_STATUS_OVER;
2511 banks[2] = mce->addr;
2512 banks[3] = mce->misc;
2513 banks[1] = mce->status;
2514 } else
2515 banks[1] |= MCI_STATUS_OVER;
2516 return 0;
2517}
2518
3cfc3092
JK		 2519static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2520 struct kvm_vcpu_events *events)
2521{
03b82a30
JK		 2522 events->exception.injected =
2523 vcpu->arch.exception.pending &&
2524 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2525 events->exception.nr = vcpu->arch.exception.nr;
2526 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
2527 events->exception.error_code = vcpu->arch.exception.error_code;
2528
03b82a30
JK		 2529 events->interrupt.injected =
2530 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2531 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2532 events->interrupt.soft = 0;
48005f64
JK		 2533 events->interrupt.shadow =
2534 kvm_x86_ops->get_interrupt_shadow(vcpu,
2535 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
3cfc3092
JK		 2536
2537 events->nmi.injected = vcpu->arch.nmi_injected;
2538 events->nmi.pending = vcpu->arch.nmi_pending;
2539 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
2540
2541 events->sipi_vector = vcpu->arch.sipi_vector;
2542
dab4b911 2543 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2544 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2545 | KVM_VCPUEVENT_VALID_SHADOW);
3cfc3092
JK		 2546}
2547
2548static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2549 struct kvm_vcpu_events *events)
2550{
dab4b911 2551 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2552 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2553 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 2554 return -EINVAL;
2555
3cfc3092
JK		 2556 vcpu->arch.exception.pending = events->exception.injected;
2557 vcpu->arch.exception.nr = events->exception.nr;
2558 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2559 vcpu->arch.exception.error_code = events->exception.error_code;
2560
2561 vcpu->arch.interrupt.pending = events->interrupt.injected;
2562 vcpu->arch.interrupt.nr = events->interrupt.nr;
2563 vcpu->arch.interrupt.soft = events->interrupt.soft;
2564 if (vcpu->arch.interrupt.pending && irqchip_in_kernel(vcpu->kvm))
2565 kvm_pic_clear_isr_ack(vcpu->kvm);
48005f64
JK		 2566 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2567 kvm_x86_ops->set_interrupt_shadow(vcpu,
2568 events->interrupt.shadow);
3cfc3092
JK		 2569
2570 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2571 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2572 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2573 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2574
dab4b911
JK		 2575 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR)
2576 vcpu->arch.sipi_vector = events->sipi_vector;
3cfc3092 2577
3842d135
AK		 2578 kvm_make_request(KVM_REQ_EVENT, vcpu);
2579
3cfc3092
JK		 2580 return 0;
2581}
2582
a1efbe77
JK		 2583static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2584 struct kvm_debugregs *dbgregs)
2585{
a1efbe77
JK		 2586 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2587 dbgregs->dr6 = vcpu->arch.dr6;
2588 dbgregs->dr7 = vcpu->arch.dr7;
2589 dbgregs->flags = 0;
a1efbe77
JK		 2590}
2591
2592static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2593 struct kvm_debugregs *dbgregs)
2594{
2595 if (dbgregs->flags)
2596 return -EINVAL;
2597
a1efbe77
JK		 2598 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2599 vcpu->arch.dr6 = dbgregs->dr6;
2600 vcpu->arch.dr7 = dbgregs->dr7;
2601
a1efbe77
JK		 2602 return 0;
2603}
2604
2d5b5a66
SY		 2605static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
2606 struct kvm_xsave *guest_xsave)
2607{
2608 if (cpu_has_xsave)
2609 memcpy(guest_xsave->region,
2610 &vcpu->arch.guest_fpu.state->xsave,
f45755b8 2611 xstate_size);
2d5b5a66
SY		 2612 else {
2613 memcpy(guest_xsave->region,
2614 &vcpu->arch.guest_fpu.state->fxsave,
2615 sizeof(struct i387_fxsave_struct));
2616 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
2617 XSTATE_FPSSE;
2618 }
2619}
2620
2621static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
2622 struct kvm_xsave *guest_xsave)
2623{
2624 u64 xstate_bv =
2625 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
2626
2627 if (cpu_has_xsave)
2628 memcpy(&vcpu->arch.guest_fpu.state->xsave,
f45755b8 2629 guest_xsave->region, xstate_size);
2d5b5a66
SY		 2630 else {
2631 if (xstate_bv & ~XSTATE_FPSSE)
2632 return -EINVAL;
2633 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
2634 guest_xsave->region, sizeof(struct i387_fxsave_struct));
2635 }
2636 return 0;
2637}
2638
2639static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
2640 struct kvm_xcrs *guest_xcrs)
2641{
2642 if (!cpu_has_xsave) {
2643 guest_xcrs->nr_xcrs = 0;
2644 return;
2645 }
2646
2647 guest_xcrs->nr_xcrs = 1;
2648 guest_xcrs->flags = 0;
2649 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
2650 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
2651}
2652
2653static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
2654 struct kvm_xcrs *guest_xcrs)
2655{
2656 int i, r = 0;
2657
2658 if (!cpu_has_xsave)
2659 return -EINVAL;
2660
2661 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
2662 return -EINVAL;
2663
2664 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
2665 /* Only support XCR0 currently */
2666 if (guest_xcrs->xcrs[0].xcr == XCR_XFEATURE_ENABLED_MASK) {
2667 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
2668 guest_xcrs->xcrs[0].value);
2669 break;
2670 }
2671 if (r)
2672 r = -EINVAL;
2673 return r;
2674}
2675
313a3dc7
CO		 2676long kvm_arch_vcpu_ioctl(struct file *filp,
2677 unsigned int ioctl, unsigned long arg)
2678{
2679 struct kvm_vcpu *vcpu = filp->private_data;
2680 void __user *argp = (void __user *)arg;
2681 int r;
d1ac91d8
AK		 2682 union {
2683 struct kvm_lapic_state *lapic;
2684 struct kvm_xsave *xsave;
2685 struct kvm_xcrs *xcrs;
2686 void *buffer;
2687 } u;
2688
2689 u.buffer = NULL;
313a3dc7
CO		 2690 switch (ioctl) {
2691 case KVM_GET_LAPIC: {
2204ae3c
MT		 2692 r = -EINVAL;
2693 if (!vcpu->arch.apic)
2694 goto out;
d1ac91d8 2695 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 2696
b772ff36 2697 r = -ENOMEM;
d1ac91d8 2698 if (!u.lapic)
b772ff36 2699 goto out;
d1ac91d8 2700 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 2701 if (r)
2702 goto out;
2703 r = -EFAULT;
d1ac91d8 2704 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 2705 goto out;
2706 r = 0;
2707 break;
2708 }
2709 case KVM_SET_LAPIC: {
2204ae3c
MT		 2710 r = -EINVAL;
2711 if (!vcpu->arch.apic)
2712 goto out;
d1ac91d8 2713 u.lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
b772ff36 2714 r = -ENOMEM;
d1ac91d8 2715 if (!u.lapic)
b772ff36 2716 goto out;
313a3dc7 2717 r = -EFAULT;
d1ac91d8 2718 if (copy_from_user(u.lapic, argp, sizeof(struct kvm_lapic_state)))
313a3dc7 2719 goto out;
d1ac91d8 2720 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 2721 if (r)
2722 goto out;
2723 r = 0;
2724 break;
2725 }
f77bc6a4
ZX		 2726 case KVM_INTERRUPT: {
2727 struct kvm_interrupt irq;
2728
2729 r = -EFAULT;
2730 if (copy_from_user(&irq, argp, sizeof irq))
2731 goto out;
2732 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
2733 if (r)
2734 goto out;
2735 r = 0;
2736 break;
2737 }
c4abb7c9
JK		 2738 case KVM_NMI: {
2739 r = kvm_vcpu_ioctl_nmi(vcpu);
2740 if (r)
2741 goto out;
2742 r = 0;
2743 break;
2744 }
313a3dc7
CO		 2745 case KVM_SET_CPUID: {
2746 struct kvm_cpuid __user *cpuid_arg = argp;
2747 struct kvm_cpuid cpuid;
2748
2749 r = -EFAULT;
2750 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2751 goto out;
2752 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
2753 if (r)
2754 goto out;
2755 break;
2756 }
07716717
DK		 2757 case KVM_SET_CPUID2: {
2758 struct kvm_cpuid2 __user *cpuid_arg = argp;
2759 struct kvm_cpuid2 cpuid;
2760
2761 r = -EFAULT;
2762 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2763 goto out;
2764 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 2765 cpuid_arg->entries);
07716717
DK		 2766 if (r)
2767 goto out;
2768 break;
2769 }
2770 case KVM_GET_CPUID2: {
2771 struct kvm_cpuid2 __user *cpuid_arg = argp;
2772 struct kvm_cpuid2 cpuid;
2773
2774 r = -EFAULT;
2775 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2776 goto out;
2777 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 2778 cpuid_arg->entries);
07716717
DK		 2779 if (r)
2780 goto out;
2781 r = -EFAULT;
2782 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2783 goto out;
2784 r = 0;
2785 break;
2786 }
313a3dc7
CO		 2787 case KVM_GET_MSRS:
2788 r = msr_io(vcpu, argp, kvm_get_msr, 1);
2789 break;
2790 case KVM_SET_MSRS:
2791 r = msr_io(vcpu, argp, do_set_msr, 0);
2792 break;
b209749f
AK		 2793 case KVM_TPR_ACCESS_REPORTING: {
2794 struct kvm_tpr_access_ctl tac;
2795
2796 r = -EFAULT;
2797 if (copy_from_user(&tac, argp, sizeof tac))
2798 goto out;
2799 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
2800 if (r)
2801 goto out;
2802 r = -EFAULT;
2803 if (copy_to_user(argp, &tac, sizeof tac))
2804 goto out;
2805 r = 0;
2806 break;
2807 };
b93463aa
AK		 2808 case KVM_SET_VAPIC_ADDR: {
2809 struct kvm_vapic_addr va;
2810
2811 r = -EINVAL;
2812 if (!irqchip_in_kernel(vcpu->kvm))
2813 goto out;
2814 r = -EFAULT;
2815 if (copy_from_user(&va, argp, sizeof va))
2816 goto out;
2817 r = 0;
2818 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
2819 break;
2820 }
890ca9ae
HY		 2821 case KVM_X86_SETUP_MCE: {
2822 u64 mcg_cap;
2823
2824 r = -EFAULT;
2825 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
2826 goto out;
2827 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
2828 break;
2829 }
2830 case KVM_X86_SET_MCE: {
2831 struct kvm_x86_mce mce;
2832
2833 r = -EFAULT;
2834 if (copy_from_user(&mce, argp, sizeof mce))
2835 goto out;
2836 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
2837 break;
2838 }
3cfc3092
JK		 2839 case KVM_GET_VCPU_EVENTS: {
2840 struct kvm_vcpu_events events;
2841
2842 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
2843
2844 r = -EFAULT;
2845 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
2846 break;
2847 r = 0;
2848 break;
2849 }
2850 case KVM_SET_VCPU_EVENTS: {
2851 struct kvm_vcpu_events events;
2852
2853 r = -EFAULT;
2854 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
2855 break;
2856
2857 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
2858 break;
2859 }
a1efbe77
JK		 2860 case KVM_GET_DEBUGREGS: {
2861 struct kvm_debugregs dbgregs;
2862
2863 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
2864
2865 r = -EFAULT;
2866 if (copy_to_user(argp, &dbgregs,
2867 sizeof(struct kvm_debugregs)))
2868 break;
2869 r = 0;
2870 break;
2871 }
2872 case KVM_SET_DEBUGREGS: {
2873 struct kvm_debugregs dbgregs;
2874
2875 r = -EFAULT;
2876 if (copy_from_user(&dbgregs, argp,
2877 sizeof(struct kvm_debugregs)))
2878 break;
2879
2880 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
2881 break;
2882 }
2d5b5a66 2883 case KVM_GET_XSAVE: {
d1ac91d8 2884 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 2885 r = -ENOMEM;
d1ac91d8 2886 if (!u.xsave)
2d5b5a66
SY		 2887 break;
2888
d1ac91d8 2889 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 2890
2891 r = -EFAULT;
d1ac91d8 2892 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 2893 break;
2894 r = 0;
2895 break;
2896 }
2897 case KVM_SET_XSAVE: {
d1ac91d8 2898 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 2899 r = -ENOMEM;
d1ac91d8 2900 if (!u.xsave)
2d5b5a66
SY		 2901 break;
2902
2903 r = -EFAULT;
d1ac91d8 2904 if (copy_from_user(u.xsave, argp, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 2905 break;
2906
d1ac91d8 2907 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 2908 break;
2909 }
2910 case KVM_GET_XCRS: {
d1ac91d8 2911 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 2912 r = -ENOMEM;
d1ac91d8 2913 if (!u.xcrs)
2d5b5a66
SY		 2914 break;
2915
d1ac91d8 2916 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 2917
2918 r = -EFAULT;
d1ac91d8 2919 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 2920 sizeof(struct kvm_xcrs)))
2921 break;
2922 r = 0;
2923 break;
2924 }
2925 case KVM_SET_XCRS: {
d1ac91d8 2926 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 2927 r = -ENOMEM;
d1ac91d8 2928 if (!u.xcrs)
2d5b5a66
SY		 2929 break;
2930
2931 r = -EFAULT;
d1ac91d8 2932 if (copy_from_user(u.xcrs, argp,
2d5b5a66
SY		 2933 sizeof(struct kvm_xcrs)))
2934 break;
2935
d1ac91d8 2936 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 2937 break;
2938 }
313a3dc7
CO		 2939 default:
2940 r = -EINVAL;
2941 }
2942out:
d1ac91d8 2943 kfree(u.buffer);
313a3dc7
CO		 2944 return r;
2945}
2946
1fe779f8
CO		 2947static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
2948{
2949 int ret;
2950
2951 if (addr > (unsigned int)(-3 * PAGE_SIZE))
2952 return -1;
2953 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
2954 return ret;
2955}
2956
b927a3ce
SY		 2957static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
2958 u64 ident_addr)
2959{
2960 kvm->arch.ept_identity_map_addr = ident_addr;
2961 return 0;
2962}
2963
1fe779f8
CO		 2964static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
2965 u32 kvm_nr_mmu_pages)
2966{
2967 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
2968 return -EINVAL;
2969
79fac95e 2970 mutex_lock(&kvm->slots_lock);
7c8a83b7 2971 spin_lock(&kvm->mmu_lock);
1fe779f8
CO		 2972
2973 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 2974 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 2975
7c8a83b7 2976 spin_unlock(&kvm->mmu_lock);
79fac95e 2977 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 2978 return 0;
2979}
2980
2981static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
2982{
39de71ec 2983 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 2984}
2985
1fe779f8
CO		 2986static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2987{
2988 int r;
2989
2990 r = 0;
2991 switch (chip->chip_id) {
2992 case KVM_IRQCHIP_PIC_MASTER:
2993 memcpy(&chip->chip.pic,
2994 &pic_irqchip(kvm)->pics[0],
2995 sizeof(struct kvm_pic_state));
2996 break;
2997 case KVM_IRQCHIP_PIC_SLAVE:
2998 memcpy(&chip->chip.pic,
2999 &pic_irqchip(kvm)->pics[1],
3000 sizeof(struct kvm_pic_state));
3001 break;
3002 case KVM_IRQCHIP_IOAPIC:
eba0226b 3003 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3004 break;
3005 default:
3006 r = -EINVAL;
3007 break;
3008 }
3009 return r;
3010}
3011
3012static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3013{
3014 int r;
3015
3016 r = 0;
3017 switch (chip->chip_id) {
3018 case KVM_IRQCHIP_PIC_MASTER:
fa8273e9 3019 raw_spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3020 memcpy(&pic_irqchip(kvm)->pics[0],
3021 &chip->chip.pic,
3022 sizeof(struct kvm_pic_state));
fa8273e9 3023 raw_spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3024 break;
3025 case KVM_IRQCHIP_PIC_SLAVE:
fa8273e9 3026 raw_spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3027 memcpy(&pic_irqchip(kvm)->pics[1],
3028 &chip->chip.pic,
3029 sizeof(struct kvm_pic_state));
fa8273e9 3030 raw_spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3031 break;
3032 case KVM_IRQCHIP_IOAPIC:
eba0226b 3033 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3034 break;
3035 default:
3036 r = -EINVAL;
3037 break;
3038 }
3039 kvm_pic_update_irq(pic_irqchip(kvm));
3040 return r;
3041}
3042
e0f63cb9
SY		 3043static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3044{
3045 int r = 0;
3046
894a9c55 3047 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3048 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 3049 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3050 return r;
3051}
3052
3053static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3054{
3055 int r = 0;
3056
894a9c55 3057 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3058 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 3059 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3060 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3061 return r;
3062}
3063
3064static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3065{
3066 int r = 0;
3067
3068 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3069 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3070 sizeof(ps->channels));
3071 ps->flags = kvm->arch.vpit->pit_state.flags;
3072 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3073 return r;
3074}
3075
3076static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3077{
3078 int r = 0, start = 0;
3079 u32 prev_legacy, cur_legacy;
3080 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3081 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3082 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3083 if (!prev_legacy && cur_legacy)
3084 start = 1;
3085 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3086 sizeof(kvm->arch.vpit->pit_state.channels));
3087 kvm->arch.vpit->pit_state.flags = ps->flags;
3088 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 3089 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3090 return r;
3091}
3092
52d939a0
MT		 3093static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3094 struct kvm_reinject_control *control)
3095{
3096 if (!kvm->arch.vpit)
3097 return -ENXIO;
894a9c55 3098 mutex_lock(&kvm->arch.vpit->pit_state.lock);
52d939a0 3099 kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject;
894a9c55 3100 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3101 return 0;
3102}
3103
5bb064dc
ZX		 3104/*
3105 * Get (and clear) the dirty memory log for a memory slot.
3106 */
3107int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
3108 struct kvm_dirty_log *log)
3109{
87bf6e7d 3110 int r, i;
5bb064dc 3111 struct kvm_memory_slot *memslot;
87bf6e7d 3112 unsigned long n;
b050b015 3113 unsigned long is_dirty = 0;
5bb064dc 3114
79fac95e 3115 mutex_lock(&kvm->slots_lock);
5bb064dc 3116
b050b015
MT		 3117 r = -EINVAL;
3118 if (log->slot >= KVM_MEMORY_SLOTS)
3119 goto out;
3120
3121 memslot = &kvm->memslots->memslots[log->slot];
3122 r = -ENOENT;
3123 if (!memslot->dirty_bitmap)
3124 goto out;
3125
87bf6e7d 3126 n = kvm_dirty_bitmap_bytes(memslot);
b050b015 3127
b050b015
MT		 3128 for (i = 0; !is_dirty && i < n/sizeof(long); i++)
3129 is_dirty = memslot->dirty_bitmap[i];
5bb064dc
ZX		 3130
3131 /* If nothing is dirty, don't bother messing with page tables. */
3132 if (is_dirty) {
b050b015 3133 struct kvm_memslots *slots, *old_slots;
914ebccd 3134 unsigned long *dirty_bitmap;
b050b015 3135
7c8a83b7 3136 spin_lock(&kvm->mmu_lock);
5bb064dc 3137 kvm_mmu_slot_remove_write_access(kvm, log->slot);
7c8a83b7 3138 spin_unlock(&kvm->mmu_lock);
b050b015 3139
914ebccd
TY		 3140 r = -ENOMEM;
3141 dirty_bitmap = vmalloc(n);
3142 if (!dirty_bitmap)
3143 goto out;
3144 memset(dirty_bitmap, 0, n);
b050b015 3145
914ebccd
TY		 3146 r = -ENOMEM;
3147 slots = kzalloc(sizeof(struct kvm_memslots), GFP_KERNEL);
3148 if (!slots) {
3149 vfree(dirty_bitmap);
3150 goto out;
3151 }
b050b015
MT		 3152 memcpy(slots, kvm->memslots, sizeof(struct kvm_memslots));
3153 slots->memslots[log->slot].dirty_bitmap = dirty_bitmap;
3154
3155 old_slots = kvm->memslots;
3156 rcu_assign_pointer(kvm->memslots, slots);
3157 synchronize_srcu_expedited(&kvm->srcu);
3158 dirty_bitmap = old_slots->memslots[log->slot].dirty_bitmap;
3159 kfree(old_slots);
914ebccd
TY		 3160
3161 r = -EFAULT;
3162 if (copy_to_user(log->dirty_bitmap, dirty_bitmap, n)) {
3163 vfree(dirty_bitmap);
3164 goto out;
3165 }
3166 vfree(dirty_bitmap);
3167 } else {
3168 r = -EFAULT;
3169 if (clear_user(log->dirty_bitmap, n))
3170 goto out;
5bb064dc 3171 }
b050b015 3172
5bb064dc
ZX		 3173 r = 0;
3174out:
79fac95e 3175 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3176 return r;
3177}
3178
1fe779f8
CO		 3179long kvm_arch_vm_ioctl(struct file *filp,
3180 unsigned int ioctl, unsigned long arg)
3181{
3182 struct kvm *kvm = filp->private_data;
3183 void __user *argp = (void __user *)arg;
367e1319 3184 int r = -ENOTTY;
f0d66275
DH		 3185 /*
3186 * This union makes it completely explicit to gcc-3.x
3187 * that these two variables' stack usage should be
3188 * combined, not added together.
3189 */
3190 union {
3191 struct kvm_pit_state ps;
e9f42757 3192 struct kvm_pit_state2 ps2;
c5ff41ce 3193 struct kvm_pit_config pit_config;
f0d66275 3194 } u;
1fe779f8
CO		 3195
3196 switch (ioctl) {
3197 case KVM_SET_TSS_ADDR:
3198 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
3199 if (r < 0)
3200 goto out;
3201 break;
b927a3ce
SY		 3202 case KVM_SET_IDENTITY_MAP_ADDR: {
3203 u64 ident_addr;
3204
3205 r = -EFAULT;
3206 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3207 goto out;
3208 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
3209 if (r < 0)
3210 goto out;
3211 break;
3212 }
1fe779f8
CO		 3213 case KVM_SET_NR_MMU_PAGES:
3214 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
3215 if (r)
3216 goto out;
3217 break;
3218 case KVM_GET_NR_MMU_PAGES:
3219 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3220 break;
3ddea128
MT		 3221 case KVM_CREATE_IRQCHIP: {
3222 struct kvm_pic *vpic;
3223
3224 mutex_lock(&kvm->lock);
3225 r = -EEXIST;
3226 if (kvm->arch.vpic)
3227 goto create_irqchip_unlock;
1fe779f8 3228 r = -ENOMEM;
3ddea128
MT		 3229 vpic = kvm_create_pic(kvm);
3230 if (vpic) {
1fe779f8
CO		 3231 r = kvm_ioapic_init(kvm);
3232 if (r) {
72bb2fcd
WY		 3233 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3234 &vpic->dev);
3ddea128
MT		 3235 kfree(vpic);
3236 goto create_irqchip_unlock;
1fe779f8
CO		 3237 }
3238 } else
3ddea128
MT		 3239 goto create_irqchip_unlock;
3240 smp_wmb();
3241 kvm->arch.vpic = vpic;
3242 smp_wmb();
399ec807
AK		 3243 r = kvm_setup_default_irq_routing(kvm);
3244 if (r) {
3ddea128 3245 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 3246 kvm_ioapic_destroy(kvm);
3247 kvm_destroy_pic(kvm);
3ddea128 3248 mutex_unlock(&kvm->irq_lock);
399ec807 3249 }
3ddea128
MT		 3250 create_irqchip_unlock:
3251 mutex_unlock(&kvm->lock);
1fe779f8 3252 break;
3ddea128 3253 }
7837699f 3254 case KVM_CREATE_PIT:
c5ff41ce
JK		 3255 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3256 goto create_pit;
3257 case KVM_CREATE_PIT2:
3258 r = -EFAULT;
3259 if (copy_from_user(&u.pit_config, argp,
3260 sizeof(struct kvm_pit_config)))
3261 goto out;
3262 create_pit:
79fac95e 3263 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3264 r = -EEXIST;
3265 if (kvm->arch.vpit)
3266 goto create_pit_unlock;
7837699f 3267 r = -ENOMEM;
c5ff41ce 3268 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3269 if (kvm->arch.vpit)
3270 r = 0;
269e05e4 3271 create_pit_unlock:
79fac95e 3272 mutex_unlock(&kvm->slots_lock);
7837699f 3273 break;
4925663a 3274 case KVM_IRQ_LINE_STATUS:
1fe779f8
CO		 3275 case KVM_IRQ_LINE: {
3276 struct kvm_irq_level irq_event;
3277
3278 r = -EFAULT;
3279 if (copy_from_user(&irq_event, argp, sizeof irq_event))
3280 goto out;
160d2f6c 3281 r = -ENXIO;
1fe779f8 3282 if (irqchip_in_kernel(kvm)) {
4925663a 3283 __s32 status;
4925663a
GN		 3284 status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3285 irq_event.irq, irq_event.level);
4925663a 3286 if (ioctl == KVM_IRQ_LINE_STATUS) {
160d2f6c 3287 r = -EFAULT;
4925663a
GN		 3288 irq_event.status = status;
3289 if (copy_to_user(argp, &irq_event,
3290 sizeof irq_event))
3291 goto out;
3292 }
1fe779f8
CO		 3293 r = 0;
3294 }
3295 break;
3296 }
3297 case KVM_GET_IRQCHIP: {
3298 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 3299 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 3300
f0d66275
DH		 3301 r = -ENOMEM;
3302 if (!chip)
1fe779f8 3303 goto out;
f0d66275
DH		 3304 r = -EFAULT;
3305 if (copy_from_user(chip, argp, sizeof *chip))
3306 goto get_irqchip_out;
1fe779f8
CO		 3307 r = -ENXIO;
3308 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3309 goto get_irqchip_out;
3310 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3311 if (r)
f0d66275 3312 goto get_irqchip_out;
1fe779f8 3313 r = -EFAULT;
f0d66275
DH		 3314 if (copy_to_user(argp, chip, sizeof *chip))
3315 goto get_irqchip_out;
1fe779f8 3316 r = 0;
f0d66275
DH		 3317 get_irqchip_out:
3318 kfree(chip);
3319 if (r)
3320 goto out;
1fe779f8
CO		 3321 break;
3322 }
3323 case KVM_SET_IRQCHIP: {
3324 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 3325 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 3326
f0d66275
DH		 3327 r = -ENOMEM;
3328 if (!chip)
1fe779f8 3329 goto out;
f0d66275
DH		 3330 r = -EFAULT;
3331 if (copy_from_user(chip, argp, sizeof *chip))
3332 goto set_irqchip_out;
1fe779f8
CO		 3333 r = -ENXIO;
3334 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3335 goto set_irqchip_out;
3336 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3337 if (r)
f0d66275 3338 goto set_irqchip_out;
1fe779f8 3339 r = 0;
f0d66275
DH		 3340 set_irqchip_out:
3341 kfree(chip);
3342 if (r)
3343 goto out;
1fe779f8
CO		 3344 break;
3345 }
e0f63cb9 3346 case KVM_GET_PIT: {
e0f63cb9 3347 r = -EFAULT;
f0d66275 3348 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3349 goto out;
3350 r = -ENXIO;
3351 if (!kvm->arch.vpit)
3352 goto out;
f0d66275 3353 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3354 if (r)
3355 goto out;
3356 r = -EFAULT;
f0d66275 3357 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3358 goto out;
3359 r = 0;
3360 break;
3361 }
3362 case KVM_SET_PIT: {
e0f63cb9 3363 r = -EFAULT;
f0d66275 3364 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3365 goto out;
3366 r = -ENXIO;
3367 if (!kvm->arch.vpit)
3368 goto out;
f0d66275 3369 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3370 if (r)
3371 goto out;
3372 r = 0;
3373 break;
3374 }
e9f42757
BK		 3375 case KVM_GET_PIT2: {
3376 r = -ENXIO;
3377 if (!kvm->arch.vpit)
3378 goto out;
3379 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3380 if (r)
3381 goto out;
3382 r = -EFAULT;
3383 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3384 goto out;
3385 r = 0;
3386 break;
3387 }
3388 case KVM_SET_PIT2: {
3389 r = -EFAULT;
3390 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3391 goto out;
3392 r = -ENXIO;
3393 if (!kvm->arch.vpit)
3394 goto out;
3395 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
3396 if (r)
3397 goto out;
3398 r = 0;
3399 break;
3400 }
52d939a0
MT		 3401 case KVM_REINJECT_CONTROL: {
3402 struct kvm_reinject_control control;
3403 r = -EFAULT;
3404 if (copy_from_user(&control, argp, sizeof(control)))
3405 goto out;
3406 r = kvm_vm_ioctl_reinject(kvm, &control);
3407 if (r)
3408 goto out;
3409 r = 0;
3410 break;
3411 }
ffde22ac
ES		 3412 case KVM_XEN_HVM_CONFIG: {
3413 r = -EFAULT;
3414 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3415 sizeof(struct kvm_xen_hvm_config)))
3416 goto out;
3417 r = -EINVAL;
3418 if (kvm->arch.xen_hvm_config.flags)
3419 goto out;
3420 r = 0;
3421 break;
3422 }
afbcf7ab 3423 case KVM_SET_CLOCK: {
afbcf7ab
GC		 3424 struct kvm_clock_data user_ns;
3425 u64 now_ns;
3426 s64 delta;
3427
3428 r = -EFAULT;
3429 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3430 goto out;
3431
3432 r = -EINVAL;
3433 if (user_ns.flags)
3434 goto out;
3435
3436 r = 0;
759379dd 3437 now_ns = get_kernel_ns();
afbcf7ab
GC		 3438 delta = user_ns.clock - now_ns;
3439 kvm->arch.kvmclock_offset = delta;
3440 break;
3441 }
3442 case KVM_GET_CLOCK: {
afbcf7ab
GC		 3443 struct kvm_clock_data user_ns;
3444 u64 now_ns;
3445
759379dd 3446 now_ns = get_kernel_ns();
afbcf7ab
GC		 3447 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
3448 user_ns.flags = 0;
3449
3450 r = -EFAULT;
3451 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3452 goto out;
3453 r = 0;
3454 break;
3455 }
3456
1fe779f8
CO		 3457 default:
3458 ;
3459 }
3460out:
3461 return r;
3462}
3463
a16b043c 3464static void kvm_init_msr_list(void)
043405e1
CO		 3465{
3466 u32 dummy[2];
3467 unsigned i, j;
3468
e3267cbb
GC		 3469 /* skip the first msrs in the list. KVM-specific */
3470 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3471 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3472 continue;
3473 if (j < i)
3474 msrs_to_save[j] = msrs_to_save[i];
3475 j++;
3476 }
3477 num_msrs_to_save = j;
3478}
3479
bda9020e
MT		 3480static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3481 const void *v)
bbd9b64e 3482{
bda9020e
MT		 3483 if (vcpu->arch.apic &&
3484 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, len, v))
3485 return 0;
bbd9b64e 3486
e93f8a0f 3487 return kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, len, v);
bbd9b64e
CO		 3488}
3489
bda9020e 3490static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 3491{
bda9020e
MT		 3492 if (vcpu->arch.apic &&
3493 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, len, v))
3494 return 0;
bbd9b64e 3495
e93f8a0f 3496 return kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, len, v);
bbd9b64e
CO		 3497}
3498
2dafc6c2
GN		 3499static void kvm_set_segment(struct kvm_vcpu *vcpu,
3500 struct kvm_segment *var, int seg)
3501{
3502 kvm_x86_ops->set_segment(vcpu, var, seg);
3503}
3504
3505void kvm_get_segment(struct kvm_vcpu *vcpu,
3506 struct kvm_segment *var, int seg)
3507{
3508 kvm_x86_ops->get_segment(vcpu, var, seg);
3509}
3510
c30a358d
JR		 3511static gpa_t translate_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
3512{
3513 return gpa;
3514}
3515
02f59dc9
JR		 3516static gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
3517{
3518 gpa_t t_gpa;
3519 u32 error;
3520
3521 BUG_ON(!mmu_is_nested(vcpu));
3522
3523 /* NPT walks are always user-walks */
3524 access |= PFERR_USER_MASK;
3525 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &error);
3526 if (t_gpa == UNMAPPED_GVA)
3527 vcpu->arch.fault.error_code |= PFERR_NESTED_MASK;
3528
3529 return t_gpa;
3530}
3531
1871c602
GN		 3532gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3533{
3534 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
14dfe855 3535 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, error);
1871c602
GN		 3536}
3537
3538 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3539{
3540 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3541 access |= PFERR_FETCH_MASK;
14dfe855 3542 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, error);
1871c602
GN		 3543}
3544
3545gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3546{
3547 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3548 access |= PFERR_WRITE_MASK;
14dfe855 3549 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, error);
1871c602
GN		 3550}
3551
3552/* uses this to access any guest's mapped memory without checking CPL */
3553gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3554{
14dfe855 3555 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, error);
1871c602
GN		 3556}
3557
3558static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3559 struct kvm_vcpu *vcpu, u32 access,
3560 u32 *error)
bbd9b64e
CO		 3561{
3562 void *data = val;
10589a46 3563 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 3564
3565 while (bytes) {
14dfe855
JR		 3566 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
3567 error);
bbd9b64e 3568 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 3569 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 3570 int ret;
3571
10589a46
MT		 3572 if (gpa == UNMAPPED_GVA) {
3573 r = X86EMUL_PROPAGATE_FAULT;
3574 goto out;
3575 }
77c2002e 3576 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46 3577 if (ret < 0) {
c3cd7ffa 3578 r = X86EMUL_IO_NEEDED;
10589a46
MT		 3579 goto out;
3580 }
bbd9b64e 3581
77c2002e
IE		 3582 bytes -= toread;
3583 data += toread;
3584 addr += toread;
bbd9b64e 3585 }
10589a46 3586out:
10589a46 3587 return r;
bbd9b64e 3588}
77c2002e 3589
1871c602
GN		 3590/* used for instruction fetching */
3591static int kvm_fetch_guest_virt(gva_t addr, void *val, unsigned int bytes,
3592 struct kvm_vcpu *vcpu, u32 *error)
3593{
3594 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3595 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
3596 access | PFERR_FETCH_MASK, error);
3597}
3598
3599static int kvm_read_guest_virt(gva_t addr, void *val, unsigned int bytes,
3600 struct kvm_vcpu *vcpu, u32 *error)
3601{
3602 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3603 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
3604 error);
3605}
3606
3607static int kvm_read_guest_virt_system(gva_t addr, void *val, unsigned int bytes,
3608 struct kvm_vcpu *vcpu, u32 *error)
3609{
3610 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, error);
3611}
3612
7972995b 3613static int kvm_write_guest_virt_system(gva_t addr, void *val,
2dafc6c2 3614 unsigned int bytes,
7972995b 3615 struct kvm_vcpu *vcpu,
2dafc6c2 3616 u32 *error)
77c2002e
IE		 3617{
3618 void *data = val;
3619 int r = X86EMUL_CONTINUE;
3620
3621 while (bytes) {
14dfe855
JR		 3622 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
3623 PFERR_WRITE_MASK,
3624 error);
77c2002e
IE		 3625 unsigned offset = addr & (PAGE_SIZE-1);
3626 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
3627 int ret;
3628
3629 if (gpa == UNMAPPED_GVA) {
3630 r = X86EMUL_PROPAGATE_FAULT;
3631 goto out;
3632 }
3633 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
3634 if (ret < 0) {
c3cd7ffa 3635 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 3636 goto out;
3637 }
3638
3639 bytes -= towrite;
3640 data += towrite;
3641 addr += towrite;
3642 }
3643out:
3644 return r;
3645}
3646
bbd9b64e
CO		 3647static int emulator_read_emulated(unsigned long addr,
3648 void *val,
3649 unsigned int bytes,
8fe681e9 3650 unsigned int *error_code,
bbd9b64e
CO		 3651 struct kvm_vcpu *vcpu)
3652{
bbd9b64e
CO		 3653 gpa_t gpa;
3654
3655 if (vcpu->mmio_read_completed) {
3656 memcpy(val, vcpu->mmio_data, bytes);
aec51dc4
AK		 3657 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
3658 vcpu->mmio_phys_addr, *(u64 *)val);
bbd9b64e
CO		 3659 vcpu->mmio_read_completed = 0;
3660 return X86EMUL_CONTINUE;
3661 }
3662
8fe681e9 3663 gpa = kvm_mmu_gva_to_gpa_read(vcpu, addr, error_code);
1871c602 3664
8fe681e9 3665 if (gpa == UNMAPPED_GVA)
1871c602 3666 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 3667
3668 /* For APIC access vmexit */
3669 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3670 goto mmio;
3671
1871c602 3672 if (kvm_read_guest_virt(addr, val, bytes, vcpu, NULL)
77c2002e 3673 == X86EMUL_CONTINUE)
bbd9b64e 3674 return X86EMUL_CONTINUE;
bbd9b64e
CO		 3675
3676mmio:
3677 /*
3678 * Is this MMIO handled locally?
3679 */
aec51dc4
AK		 3680 if (!vcpu_mmio_read(vcpu, gpa, bytes, val)) {
3681 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 3682 return X86EMUL_CONTINUE;
3683 }
aec51dc4
AK		 3684
3685 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
bbd9b64e
CO		 3686
3687 vcpu->mmio_needed = 1;
411c35b7
GN		 3688 vcpu->run->exit_reason = KVM_EXIT_MMIO;
3689 vcpu->run->mmio.phys_addr = vcpu->mmio_phys_addr = gpa;
3690 vcpu->run->mmio.len = vcpu->mmio_size = bytes;
3691 vcpu->run->mmio.is_write = vcpu->mmio_is_write = 0;
bbd9b64e 3692
c3cd7ffa 3693 return X86EMUL_IO_NEEDED;
bbd9b64e
CO		 3694}
3695
3200f405 3696int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
9f811285 3697 const void *val, int bytes)
bbd9b64e
CO		 3698{
3699 int ret;
3700
3701 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 3702 if (ret < 0)
bbd9b64e 3703 return 0;
ad218f85 3704 kvm_mmu_pte_write(vcpu, gpa, val, bytes, 1);
bbd9b64e
CO		 3705 return 1;
3706}
3707
3708static int emulator_write_emulated_onepage(unsigned long addr,
3709 const void *val,
3710 unsigned int bytes,
8fe681e9 3711 unsigned int *error_code,
bbd9b64e
CO		 3712 struct kvm_vcpu *vcpu)
3713{
10589a46
MT		 3714 gpa_t gpa;
3715
8fe681e9 3716 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, error_code);
bbd9b64e 3717
8fe681e9 3718 if (gpa == UNMAPPED_GVA)
bbd9b64e 3719 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 3720
3721 /* For APIC access vmexit */
3722 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3723 goto mmio;
3724
3725 if (emulator_write_phys(vcpu, gpa, val, bytes))
3726 return X86EMUL_CONTINUE;
3727
3728mmio:
aec51dc4 3729 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 3730 /*
3731 * Is this MMIO handled locally?
3732 */
bda9020e 3733 if (!vcpu_mmio_write(vcpu, gpa, bytes, val))
bbd9b64e 3734 return X86EMUL_CONTINUE;
bbd9b64e
CO		 3735
3736 vcpu->mmio_needed = 1;
411c35b7
GN		 3737 vcpu->run->exit_reason = KVM_EXIT_MMIO;
3738 vcpu->run->mmio.phys_addr = vcpu->mmio_phys_addr = gpa;
3739 vcpu->run->mmio.len = vcpu->mmio_size = bytes;
3740 vcpu->run->mmio.is_write = vcpu->mmio_is_write = 1;
3741 memcpy(vcpu->run->mmio.data, val, bytes);
bbd9b64e
CO		 3742
3743 return X86EMUL_CONTINUE;
3744}
3745
3746int emulator_write_emulated(unsigned long addr,
8f6abd06
GN		 3747 const void *val,
3748 unsigned int bytes,
8fe681e9 3749 unsigned int *error_code,
8f6abd06 3750 struct kvm_vcpu *vcpu)
bbd9b64e
CO		 3751{
3752 /* Crossing a page boundary? */
3753 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
3754 int rc, now;
3755
3756 now = -addr & ~PAGE_MASK;
8fe681e9
GN		 3757 rc = emulator_write_emulated_onepage(addr, val, now, error_code,
3758 vcpu);
bbd9b64e
CO		 3759 if (rc != X86EMUL_CONTINUE)
3760 return rc;
3761 addr += now;
3762 val += now;
3763 bytes -= now;
3764 }
8fe681e9
GN		 3765 return emulator_write_emulated_onepage(addr, val, bytes, error_code,
3766 vcpu);
bbd9b64e 3767}
bbd9b64e 3768
daea3e73
AK		 3769#define CMPXCHG_TYPE(t, ptr, old, new) \
3770 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
3771
3772#ifdef CONFIG_X86_64
3773# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
3774#else
3775# define CMPXCHG64(ptr, old, new) \
9749a6c0 3776 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 3777#endif
3778
bbd9b64e
CO		 3779static int emulator_cmpxchg_emulated(unsigned long addr,
3780 const void *old,
3781 const void *new,
3782 unsigned int bytes,
8fe681e9 3783 unsigned int *error_code,
bbd9b64e
CO		 3784 struct kvm_vcpu *vcpu)
3785{
daea3e73
AK		 3786 gpa_t gpa;
3787 struct page *page;
3788 char *kaddr;
3789 bool exchanged;
2bacc55c 3790
daea3e73
AK		 3791 /* guests cmpxchg8b have to be emulated atomically */
3792 if (bytes > 8 || (bytes & (bytes - 1)))
3793 goto emul_write;
10589a46 3794
daea3e73 3795 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 3796
daea3e73
AK		 3797 if (gpa == UNMAPPED_GVA ||
3798 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3799 goto emul_write;
2bacc55c 3800
daea3e73
AK		 3801 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
3802 goto emul_write;
72dc67a6 3803
daea3e73 3804 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
c19b8bd6
WY		 3805 if (is_error_page(page)) {
3806 kvm_release_page_clean(page);
3807 goto emul_write;
3808 }
72dc67a6 3809
daea3e73
AK		 3810 kaddr = kmap_atomic(page, KM_USER0);
3811 kaddr += offset_in_page(gpa);
3812 switch (bytes) {
3813 case 1:
3814 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
3815 break;
3816 case 2:
3817 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
3818 break;
3819 case 4:
3820 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
3821 break;
3822 case 8:
3823 exchanged = CMPXCHG64(kaddr, old, new);
3824 break;
3825 default:
3826 BUG();
2bacc55c 3827 }
daea3e73
AK		 3828 kunmap_atomic(kaddr, KM_USER0);
3829 kvm_release_page_dirty(page);
3830
3831 if (!exchanged)
3832 return X86EMUL_CMPXCHG_FAILED;
3833
8f6abd06
GN		 3834 kvm_mmu_pte_write(vcpu, gpa, new, bytes, 1);
3835
3836 return X86EMUL_CONTINUE;
4a5f48f6 3837
3200f405 3838emul_write:
daea3e73 3839 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 3840
8fe681e9 3841 return emulator_write_emulated(addr, new, bytes, error_code, vcpu);
bbd9b64e
CO		 3842}
3843
cf8f70bf
GN		 3844static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
3845{
3846 /* TODO: String I/O for in kernel device */
3847 int r;
3848
3849 if (vcpu->arch.pio.in)
3850 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
3851 vcpu->arch.pio.size, pd);
3852 else
3853 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
3854 vcpu->arch.pio.port, vcpu->arch.pio.size,
3855 pd);
3856 return r;
3857}
3858
3859
3860static int emulator_pio_in_emulated(int size, unsigned short port, void *val,
3861 unsigned int count, struct kvm_vcpu *vcpu)
3862{
7972995b 3863 if (vcpu->arch.pio.count)
cf8f70bf
GN		 3864 goto data_avail;
3865
c41a15dd 3866 trace_kvm_pio(0, port, size, 1);
cf8f70bf
GN		 3867
3868 vcpu->arch.pio.port = port;
3869 vcpu->arch.pio.in = 1;
7972995b 3870 vcpu->arch.pio.count = count;
cf8f70bf
GN		 3871 vcpu->arch.pio.size = size;
3872
3873 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
3874 data_avail:
3875 memcpy(val, vcpu->arch.pio_data, size * count);
7972995b 3876 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 3877 return 1;
3878 }
3879
3880 vcpu->run->exit_reason = KVM_EXIT_IO;
3881 vcpu->run->io.direction = KVM_EXIT_IO_IN;
3882 vcpu->run->io.size = size;
3883 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
3884 vcpu->run->io.count = count;
3885 vcpu->run->io.port = port;
3886
3887 return 0;
3888}
3889
3890static int emulator_pio_out_emulated(int size, unsigned short port,
3891 const void *val, unsigned int count,
3892 struct kvm_vcpu *vcpu)
3893{
c41a15dd 3894 trace_kvm_pio(1, port, size, 1);
cf8f70bf
GN		 3895
3896 vcpu->arch.pio.port = port;
3897 vcpu->arch.pio.in = 0;
7972995b 3898 vcpu->arch.pio.count = count;
cf8f70bf
GN		 3899 vcpu->arch.pio.size = size;
3900
3901 memcpy(vcpu->arch.pio_data, val, size * count);
3902
3903 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 3904 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 3905 return 1;
3906 }
3907
3908 vcpu->run->exit_reason = KVM_EXIT_IO;
3909 vcpu->run->io.direction = KVM_EXIT_IO_OUT;
3910 vcpu->run->io.size = size;
3911 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
3912 vcpu->run->io.count = count;
3913 vcpu->run->io.port = port;
3914
3915 return 0;
3916}
3917
bbd9b64e
CO		 3918static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
3919{
3920 return kvm_x86_ops->get_segment_base(vcpu, seg);
3921}
3922
3923int emulate_invlpg(struct kvm_vcpu *vcpu, gva_t address)
3924{
a7052897 3925 kvm_mmu_invlpg(vcpu, address);
bbd9b64e
CO		 3926 return X86EMUL_CONTINUE;
3927}
3928
f5f48ee1
SY		 3929int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
3930{
3931 if (!need_emulate_wbinvd(vcpu))
3932 return X86EMUL_CONTINUE;
3933
3934 if (kvm_x86_ops->has_wbinvd_exit()) {
3935 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
3936 wbinvd_ipi, NULL, 1);
3937 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
3938 }
3939 wbinvd();
3940 return X86EMUL_CONTINUE;
3941}
3942EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
3943
bbd9b64e
CO		 3944int emulate_clts(struct kvm_vcpu *vcpu)
3945{
4d4ec087 3946 kvm_x86_ops->set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
6b52d186 3947 kvm_x86_ops->fpu_activate(vcpu);
bbd9b64e
CO		 3948 return X86EMUL_CONTINUE;
3949}
3950
35aa5375 3951int emulator_get_dr(int dr, unsigned long *dest, struct kvm_vcpu *vcpu)
bbd9b64e 3952{
338dbc97 3953 return _kvm_get_dr(vcpu, dr, dest);
bbd9b64e
CO		 3954}
3955
35aa5375 3956int emulator_set_dr(int dr, unsigned long value, struct kvm_vcpu *vcpu)
bbd9b64e 3957{
338dbc97
GN		 3958
3959 return __kvm_set_dr(vcpu, dr, value);
bbd9b64e
CO		 3960}
3961
52a46617 3962static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 3963{
52a46617 3964 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 3965}
3966
52a46617 3967static unsigned long emulator_get_cr(int cr, struct kvm_vcpu *vcpu)
bbd9b64e 3968{
52a46617
GN		 3969 unsigned long value;
3970
3971 switch (cr) {
3972 case 0:
3973 value = kvm_read_cr0(vcpu);
3974 break;
3975 case 2:
3976 value = vcpu->arch.cr2;
3977 break;
3978 case 3:
3979 value = vcpu->arch.cr3;
3980 break;
3981 case 4:
3982 value = kvm_read_cr4(vcpu);
3983 break;
3984 case 8:
3985 value = kvm_get_cr8(vcpu);
3986 break;
3987 default:
3988 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
3989 return 0;
3990 }
3991
3992 return value;
3993}
3994
0f12244f 3995static int emulator_set_cr(int cr, unsigned long val, struct kvm_vcpu *vcpu)
52a46617 3996{
0f12244f
GN		 3997 int res = 0;
3998
52a46617
GN		 3999 switch (cr) {
4000 case 0:
49a9b07e 4001 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4002 break;
4003 case 2:
4004 vcpu->arch.cr2 = val;
4005 break;
4006 case 3:
2390218b 4007 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4008 break;
4009 case 4:
a83b29c6 4010 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4011 break;
4012 case 8:
0f12244f 4013 res = __kvm_set_cr8(vcpu, val & 0xfUL);
52a46617
GN		 4014 break;
4015 default:
4016 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
0f12244f 4017 res = -1;
52a46617 4018 }
0f12244f
GN		 4019
4020 return res;
52a46617
GN		 4021}
4022
9c537244
GN		 4023static int emulator_get_cpl(struct kvm_vcpu *vcpu)
4024{
4025 return kvm_x86_ops->get_cpl(vcpu);
4026}
4027
2dafc6c2
GN		 4028static void emulator_get_gdt(struct desc_ptr *dt, struct kvm_vcpu *vcpu)
4029{
4030 kvm_x86_ops->get_gdt(vcpu, dt);
4031}
4032
160ce1f1
MG		 4033static void emulator_get_idt(struct desc_ptr *dt, struct kvm_vcpu *vcpu)
4034{
4035 kvm_x86_ops->get_idt(vcpu, dt);
4036}
4037
5951c442
GN		 4038static unsigned long emulator_get_cached_segment_base(int seg,
4039 struct kvm_vcpu *vcpu)
4040{
4041 return get_segment_base(vcpu, seg);
4042}
4043
2dafc6c2
GN		 4044static bool emulator_get_cached_descriptor(struct desc_struct *desc, int seg,
4045 struct kvm_vcpu *vcpu)
4046{
4047 struct kvm_segment var;
4048
4049 kvm_get_segment(vcpu, &var, seg);
4050
4051 if (var.unusable)
4052 return false;
4053
4054 if (var.g)
4055 var.limit >>= 12;
4056 set_desc_limit(desc, var.limit);
4057 set_desc_base(desc, (unsigned long)var.base);
4058 desc->type = var.type;
4059 desc->s = var.s;
4060 desc->dpl = var.dpl;
4061 desc->p = var.present;
4062 desc->avl = var.avl;
4063 desc->l = var.l;
4064 desc->d = var.db;
4065 desc->g = var.g;
4066
4067 return true;
4068}
4069
4070static void emulator_set_cached_descriptor(struct desc_struct *desc, int seg,
4071 struct kvm_vcpu *vcpu)
4072{
4073 struct kvm_segment var;
4074
4075 /* needed to preserve selector */
4076 kvm_get_segment(vcpu, &var, seg);
4077
4078 var.base = get_desc_base(desc);
4079 var.limit = get_desc_limit(desc);
4080 if (desc->g)
4081 var.limit = (var.limit << 12) | 0xfff;
4082 var.type = desc->type;
4083 var.present = desc->p;
4084 var.dpl = desc->dpl;
4085 var.db = desc->d;
4086 var.s = desc->s;
4087 var.l = desc->l;
4088 var.g = desc->g;
4089 var.avl = desc->avl;
4090 var.present = desc->p;
4091 var.unusable = !var.present;
4092 var.padding = 0;
4093
4094 kvm_set_segment(vcpu, &var, seg);
4095 return;
4096}
4097
4098static u16 emulator_get_segment_selector(int seg, struct kvm_vcpu *vcpu)
4099{
4100 struct kvm_segment kvm_seg;
4101
4102 kvm_get_segment(vcpu, &kvm_seg, seg);
4103 return kvm_seg.selector;
4104}
4105
4106static void emulator_set_segment_selector(u16 sel, int seg,
4107 struct kvm_vcpu *vcpu)
4108{
4109 struct kvm_segment kvm_seg;
4110
4111 kvm_get_segment(vcpu, &kvm_seg, seg);
4112 kvm_seg.selector = sel;
4113 kvm_set_segment(vcpu, &kvm_seg, seg);
4114}
4115
14af3f3c 4116static struct x86_emulate_ops emulate_ops = {
1871c602 4117 .read_std = kvm_read_guest_virt_system,
2dafc6c2 4118 .write_std = kvm_write_guest_virt_system,
1871c602 4119 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 4120 .read_emulated = emulator_read_emulated,
4121 .write_emulated = emulator_write_emulated,
4122 .cmpxchg_emulated = emulator_cmpxchg_emulated,
cf8f70bf
GN		 4123 .pio_in_emulated = emulator_pio_in_emulated,
4124 .pio_out_emulated = emulator_pio_out_emulated,
2dafc6c2
GN		 4125 .get_cached_descriptor = emulator_get_cached_descriptor,
4126 .set_cached_descriptor = emulator_set_cached_descriptor,
4127 .get_segment_selector = emulator_get_segment_selector,
4128 .set_segment_selector = emulator_set_segment_selector,
5951c442 4129 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 4130 .get_gdt = emulator_get_gdt,
160ce1f1 4131 .get_idt = emulator_get_idt,
52a46617
GN		 4132 .get_cr = emulator_get_cr,
4133 .set_cr = emulator_set_cr,
9c537244 4134 .cpl = emulator_get_cpl,
35aa5375
GN		 4135 .get_dr = emulator_get_dr,
4136 .set_dr = emulator_set_dr,
3fb1b5db
GN		 4137 .set_msr = kvm_set_msr,
4138 .get_msr = kvm_get_msr,
bbd9b64e
CO		 4139};
4140
5fdbf976
MT		 4141static void cache_all_regs(struct kvm_vcpu *vcpu)
4142{
4143 kvm_register_read(vcpu, VCPU_REGS_RAX);
4144 kvm_register_read(vcpu, VCPU_REGS_RSP);
4145 kvm_register_read(vcpu, VCPU_REGS_RIP);
4146 vcpu->arch.regs_dirty = ~0;
4147}
4148
95cb2295
GN		 4149static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4150{
4151 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
4152 /*
4153 * an sti; sti; sequence only disable interrupts for the first
4154 * instruction. So, if the last instruction, be it emulated or
4155 * not, left the system with the INT_STI flag enabled, it
4156 * means that the last instruction is an sti. We should not
4157 * leave the flag on in this case. The same goes for mov ss
4158 */
4159 if (!(int_shadow & mask))
4160 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4161}
4162
54b8486f
GN		 4163static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4164{
4165 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4166 if (ctxt->exception == PF_VECTOR)
d4f8cf66 4167 kvm_propagate_fault(vcpu);
54b8486f
GN		 4168 else if (ctxt->error_code_valid)
4169 kvm_queue_exception_e(vcpu, ctxt->exception, ctxt->error_code);
4170 else
4171 kvm_queue_exception(vcpu, ctxt->exception);
4172}
4173
8ec4722d
MG		 4174static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4175{
4176 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
4177 int cs_db, cs_l;
4178
4179 cache_all_regs(vcpu);
4180
4181 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4182
4183 vcpu->arch.emulate_ctxt.vcpu = vcpu;
4184 vcpu->arch.emulate_ctxt.eflags = kvm_x86_ops->get_rflags(vcpu);
4185 vcpu->arch.emulate_ctxt.eip = kvm_rip_read(vcpu);
4186 vcpu->arch.emulate_ctxt.mode =
4187 (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4188 (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM)
4189 ? X86EMUL_MODE_VM86 : cs_l
4190 ? X86EMUL_MODE_PROT64 : cs_db
4191 ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
4192 memset(c, 0, sizeof(struct decode_cache));
4193 memcpy(c->regs, vcpu->arch.regs, sizeof c->regs);
4194}
4195
6d77dbfc
GN		 4196static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4197{
6d77dbfc
GN		 4198 ++vcpu->stat.insn_emulation_fail;
4199 trace_kvm_emulate_insn_failed(vcpu);
4200 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4201 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4202 vcpu->run->internal.ndata = 0;
4203 kvm_queue_exception(vcpu, UD_VECTOR);
4204 return EMULATE_FAIL;
4205}
4206
a6f177ef
GN		 4207static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t gva)
4208{
4209 gpa_t gpa;
4210
68be0803
GN		 4211 if (tdp_enabled)
4212 return false;
4213
a6f177ef
GN		 4214 /*
4215 * if emulation was due to access to shadowed page table
4216 * and it failed try to unshadow page and re-entetr the
4217 * guest to let CPU execute the instruction.
4218 */
4219 if (kvm_mmu_unprotect_page_virt(vcpu, gva))
4220 return true;
4221
4222 gpa = kvm_mmu_gva_to_gpa_system(vcpu, gva, NULL);
4223
4224 if (gpa == UNMAPPED_GVA)
4225 return true; /* let cpu generate fault */
4226
4227 if (!kvm_is_error_hva(gfn_to_hva(vcpu->kvm, gpa >> PAGE_SHIFT)))
4228 return true;
4229
4230 return false;
4231}
4232
bbd9b64e 4233int emulate_instruction(struct kvm_vcpu *vcpu,
bbd9b64e
CO		 4234 unsigned long cr2,
4235 u16 error_code,
571008da 4236 int emulation_type)
bbd9b64e 4237{
95cb2295 4238 int r;
4d2179e1 4239 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
bbd9b64e 4240
26eef70c 4241 kvm_clear_exception_queue(vcpu);
ad312c7c 4242 vcpu->arch.mmio_fault_cr2 = cr2;
5fdbf976 4243 /*
56e82318 4244 * TODO: fix emulate.c to use guest_read/write_register
5fdbf976
MT		 4245 * instead of direct ->regs accesses, can save hundred cycles
4246 * on Intel for instructions that don't read/change RSP, for
4247 * for example.
4248 */
4249 cache_all_regs(vcpu);
bbd9b64e 4250
571008da 4251 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 4252 init_emulate_ctxt(vcpu);
95cb2295 4253 vcpu->arch.emulate_ctxt.interruptibility = 0;
54b8486f 4254 vcpu->arch.emulate_ctxt.exception = -1;
4fc40f07 4255 vcpu->arch.emulate_ctxt.perm_ok = false;
bbd9b64e 4256
9aabc88f 4257 r = x86_decode_insn(&vcpu->arch.emulate_ctxt);
d47f00a6
JR		 4258 if (r == X86EMUL_PROPAGATE_FAULT)
4259 goto done;
4260
e46479f8 4261 trace_kvm_emulate_insn_start(vcpu);
571008da 4262
0cb5762e
AP		 4263 /* Only allow emulation of specific instructions on #UD
4264 * (namely VMMCALL, sysenter, sysexit, syscall)*/
0cb5762e
AP		 4265 if (emulation_type & EMULTYPE_TRAP_UD) {
4266 if (!c->twobyte)
4267 return EMULATE_FAIL;
4268 switch (c->b) {
4269 case 0x01: /* VMMCALL */
4270 if (c->modrm_mod != 3 || c->modrm_rm != 1)
4271 return EMULATE_FAIL;
4272 break;
4273 case 0x34: /* sysenter */
4274 case 0x35: /* sysexit */
4275 if (c->modrm_mod != 0 || c->modrm_rm != 0)
4276 return EMULATE_FAIL;
4277 break;
4278 case 0x05: /* syscall */
4279 if (c->modrm_mod != 0 || c->modrm_rm != 0)
4280 return EMULATE_FAIL;
4281 break;
4282 default:
4283 return EMULATE_FAIL;
4284 }
4285
4286 if (!(c->modrm_reg == 0 || c->modrm_reg == 3))
4287 return EMULATE_FAIL;
4288 }
571008da 4289
f2b5756b 4290 ++vcpu->stat.insn_emulation;
bbd9b64e 4291 if (r) {
a6f177ef 4292 if (reexecute_instruction(vcpu, cr2))
bbd9b64e 4293 return EMULATE_DONE;
6d77dbfc
GN		 4294 if (emulation_type & EMULTYPE_SKIP)
4295 return EMULATE_FAIL;
4296 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4297 }
4298 }
4299
ba8afb6b
GN		 4300 if (emulation_type & EMULTYPE_SKIP) {
4301 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.decode.eip);
4302 return EMULATE_DONE;
4303 }
4304
4d2179e1
GN		 4305 /* this is needed for vmware backdor interface to work since it
4306 changes registers values during IO operation */
4307 memcpy(c->regs, vcpu->arch.regs, sizeof c->regs);
4308
5cd21917 4309restart:
9aabc88f 4310 r = x86_emulate_insn(&vcpu->arch.emulate_ctxt);
bbd9b64e 4311
d2ddd1c4 4312 if (r == EMULATION_FAILED) {
a6f177ef 4313 if (reexecute_instruction(vcpu, cr2))
c3cd7ffa
GN		 4314 return EMULATE_DONE;
4315
6d77dbfc 4316 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4317 }
4318
d47f00a6 4319done:
d2ddd1c4 4320 if (vcpu->arch.emulate_ctxt.exception >= 0) {
54b8486f 4321 inject_emulated_exception(vcpu);
d2ddd1c4
GN		 4322 r = EMULATE_DONE;
4323 } else if (vcpu->arch.pio.count) {
3457e419
GN		 4324 if (!vcpu->arch.pio.in)
4325 vcpu->arch.pio.count = 0;
e85d28f8
GN		 4326 r = EMULATE_DO_MMIO;
4327 } else if (vcpu->mmio_needed) {
3457e419
GN		 4328 if (vcpu->mmio_is_write)
4329 vcpu->mmio_needed = 0;
e85d28f8 4330 r = EMULATE_DO_MMIO;
d2ddd1c4 4331 } else if (r == EMULATION_RESTART)
5cd21917 4332 goto restart;
d2ddd1c4
GN		 4333 else
4334 r = EMULATE_DONE;
f850e2e6 4335
e85d28f8
GN		 4336 toggle_interruptibility(vcpu, vcpu->arch.emulate_ctxt.interruptibility);
4337 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
3842d135 4338 kvm_make_request(KVM_REQ_EVENT, vcpu);
e85d28f8
GN		 4339 memcpy(vcpu->arch.regs, c->regs, sizeof c->regs);
4340 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.eip);
4341
4342 return r;
de7d789a 4343}
bbd9b64e 4344EXPORT_SYMBOL_GPL(emulate_instruction);
de7d789a 4345
cf8f70bf 4346int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 4347{
cf8f70bf
GN		 4348 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
4349 int ret = emulator_pio_out_emulated(size, port, &val, 1, vcpu);
4350 /* do not return to emulator after return from userspace */
7972995b 4351 vcpu->arch.pio.count = 0;
de7d789a
CO		 4352 return ret;
4353}
cf8f70bf 4354EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 4355
8cfdc000
ZA		 4356static void tsc_bad(void *info)
4357{
4358 __get_cpu_var(cpu_tsc_khz) = 0;
4359}
4360
4361static void tsc_khz_changed(void *data)
c8076604 4362{
8cfdc000
ZA		 4363 struct cpufreq_freqs *freq = data;
4364 unsigned long khz = 0;
4365
4366 if (data)
4367 khz = freq->new;
4368 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4369 khz = cpufreq_quick_get(raw_smp_processor_id());
4370 if (!khz)
4371 khz = tsc_khz;
4372 __get_cpu_var(cpu_tsc_khz) = khz;
c8076604
GH		 4373}
4374
c8076604
GH		 4375static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
4376 void *data)
4377{
4378 struct cpufreq_freqs *freq = data;
4379 struct kvm *kvm;
4380 struct kvm_vcpu *vcpu;
4381 int i, send_ipi = 0;
4382
8cfdc000
ZA		 4383 /*
4384 * We allow guests to temporarily run on slowing clocks,
4385 * provided we notify them after, or to run on accelerating
4386 * clocks, provided we notify them before. Thus time never
4387 * goes backwards.
4388 *
4389 * However, we have a problem. We can't atomically update
4390 * the frequency of a given CPU from this function; it is
4391 * merely a notifier, which can be called from any CPU.
4392 * Changing the TSC frequency at arbitrary points in time
4393 * requires a recomputation of local variables related to
4394 * the TSC for each VCPU. We must flag these local variables
4395 * to be updated and be sure the update takes place with the
4396 * new frequency before any guests proceed.
4397 *
4398 * Unfortunately, the combination of hotplug CPU and frequency
4399 * change creates an intractable locking scenario; the order
4400 * of when these callouts happen is undefined with respect to
4401 * CPU hotplug, and they can race with each other. As such,
4402 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
4403 * undefined; you can actually have a CPU frequency change take
4404 * place in between the computation of X and the setting of the
4405 * variable. To protect against this problem, all updates of
4406 * the per_cpu tsc_khz variable are done in an interrupt
4407 * protected IPI, and all callers wishing to update the value
4408 * must wait for a synchronous IPI to complete (which is trivial
4409 * if the caller is on the CPU already). This establishes the
4410 * necessary total order on variable updates.
4411 *
4412 * Note that because a guest time update may take place
4413 * anytime after the setting of the VCPU's request bit, the
4414 * correct TSC value must be set before the request. However,
4415 * to ensure the update actually makes it to any guest which
4416 * starts running in hardware virtualization between the set
4417 * and the acquisition of the spinlock, we must also ping the
4418 * CPU after setting the request bit.
4419 *
4420 */
4421
c8076604
GH		 4422 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
4423 return 0;
4424 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
4425 return 0;
8cfdc000
ZA		 4426
4427 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 4428
4429 spin_lock(&kvm_lock);
4430 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 4431 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 4432 if (vcpu->cpu != freq->cpu)
4433 continue;
4434 if (!kvm_request_guest_time_update(vcpu))
4435 continue;
4436 if (vcpu->cpu != smp_processor_id())
8cfdc000 4437 send_ipi = 1;
c8076604
GH		 4438 }
4439 }
4440 spin_unlock(&kvm_lock);
4441
4442 if (freq->old < freq->new && send_ipi) {
4443 /*
4444 * We upscale the frequency. Must make the guest
4445 * doesn't see old kvmclock values while running with
4446 * the new frequency, otherwise we risk the guest sees
4447 * time go backwards.
4448 *
4449 * In case we update the frequency for another cpu
4450 * (which might be in guest context) send an interrupt
4451 * to kick the cpu out of guest context. Next time
4452 * guest context is entered kvmclock will be updated,
4453 * so the guest will not see stale values.
4454 */
8cfdc000 4455 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 4456 }
4457 return 0;
4458}
4459
4460static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 4461 .notifier_call = kvmclock_cpufreq_notifier
4462};
4463
4464static int kvmclock_cpu_notifier(struct notifier_block *nfb,
4465 unsigned long action, void *hcpu)
4466{
4467 unsigned int cpu = (unsigned long)hcpu;
4468
4469 switch (action) {
4470 case CPU_ONLINE:
4471 case CPU_DOWN_FAILED:
4472 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
4473 break;
4474 case CPU_DOWN_PREPARE:
4475 smp_call_function_single(cpu, tsc_bad, NULL, 1);
4476 break;
4477 }
4478 return NOTIFY_OK;
4479}
4480
4481static struct notifier_block kvmclock_cpu_notifier_block = {
4482 .notifier_call = kvmclock_cpu_notifier,
4483 .priority = -INT_MAX
c8076604
GH		 4484};
4485
b820cc0c
ZA		 4486static void kvm_timer_init(void)
4487{
4488 int cpu;
4489
8cfdc000 4490 register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
b820cc0c 4491 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
b820cc0c
ZA		 4492 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
4493 CPUFREQ_TRANSITION_NOTIFIER);
4494 }
8cfdc000
ZA		 4495 for_each_online_cpu(cpu)
4496 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
b820cc0c
ZA		 4497}
4498
ff9d07a0
ZY		 4499static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
4500
4501static int kvm_is_in_guest(void)
4502{
4503 return percpu_read(current_vcpu) != NULL;
4504}
4505
4506static int kvm_is_user_mode(void)
4507{
4508 int user_mode = 3;
dcf46b94 4509
ff9d07a0
ZY		 4510 if (percpu_read(current_vcpu))
4511 user_mode = kvm_x86_ops->get_cpl(percpu_read(current_vcpu));
dcf46b94 4512
ff9d07a0
ZY		 4513 return user_mode != 0;
4514}
4515
4516static unsigned long kvm_get_guest_ip(void)
4517{
4518 unsigned long ip = 0;
dcf46b94 4519
ff9d07a0
ZY		 4520 if (percpu_read(current_vcpu))
4521 ip = kvm_rip_read(percpu_read(current_vcpu));
dcf46b94 4522
ff9d07a0
ZY		 4523 return ip;
4524}
4525
4526static struct perf_guest_info_callbacks kvm_guest_cbs = {
4527 .is_in_guest = kvm_is_in_guest,
4528 .is_user_mode = kvm_is_user_mode,
4529 .get_guest_ip = kvm_get_guest_ip,
4530};
4531
4532void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
4533{
4534 percpu_write(current_vcpu, vcpu);
4535}
4536EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
4537
4538void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
4539{
4540 percpu_write(current_vcpu, NULL);
4541}
4542EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
4543
f8c16bba 4544int kvm_arch_init(void *opaque)
043405e1 4545{
b820cc0c 4546 int r;
f8c16bba
ZX		 4547 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
4548
f8c16bba
ZX		 4549 if (kvm_x86_ops) {
4550 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 4551 r = -EEXIST;
4552 goto out;
f8c16bba
ZX		 4553 }
4554
4555 if (!ops->cpu_has_kvm_support()) {
4556 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 4557 r = -EOPNOTSUPP;
4558 goto out;
f8c16bba
ZX		 4559 }
4560 if (ops->disabled_by_bios()) {
4561 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 4562 r = -EOPNOTSUPP;
4563 goto out;
f8c16bba
ZX		 4564 }
4565
97db56ce
AK		 4566 r = kvm_mmu_module_init();
4567 if (r)
4568 goto out;
4569
4570 kvm_init_msr_list();
4571
f8c16bba 4572 kvm_x86_ops = ops;
56c6d28a 4573 kvm_mmu_set_nonpresent_ptes(0ull, 0ull);
7b52345e
SY		 4574 kvm_mmu_set_base_ptes(PT_PRESENT_MASK);
4575 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 4576 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 4577
b820cc0c 4578 kvm_timer_init();
c8076604 4579
ff9d07a0
ZY		 4580 perf_register_guest_info_callbacks(&kvm_guest_cbs);
4581
2acf923e
DC		 4582 if (cpu_has_xsave)
4583 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
4584
f8c16bba 4585 return 0;
56c6d28a
ZX		 4586
4587out:
56c6d28a 4588 return r;
043405e1 4589}
8776e519 4590
f8c16bba
ZX		 4591void kvm_arch_exit(void)
4592{
ff9d07a0
ZY		 4593 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
4594
888d256e
JK		 4595 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4596 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
4597 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 4598 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
f8c16bba 4599 kvm_x86_ops = NULL;
56c6d28a
ZX		 4600 kvm_mmu_module_exit();
4601}
f8c16bba 4602
8776e519
HB		 4603int kvm_emulate_halt(struct kvm_vcpu *vcpu)
4604{
4605 ++vcpu->stat.halt_exits;
4606 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 4607 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 4608 return 1;
4609 } else {
4610 vcpu->run->exit_reason = KVM_EXIT_HLT;
4611 return 0;
4612 }
4613}
4614EXPORT_SYMBOL_GPL(kvm_emulate_halt);
4615
2f333bcb
MT		 4616static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0,
4617 unsigned long a1)
4618{
4619 if (is_long_mode(vcpu))
4620 return a0;
4621 else
4622 return a0 | ((gpa_t)a1 << 32);
4623}
4624
55cd8e5a
GN		 4625int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
4626{
4627 u64 param, ingpa, outgpa, ret;
4628 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
4629 bool fast, longmode;
4630 int cs_db, cs_l;
4631
4632 /*
4633 * hypercall generates UD from non zero cpl and real mode
4634 * per HYPER-V spec
4635 */
3eeb3288 4636 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 4637 kvm_queue_exception(vcpu, UD_VECTOR);
4638 return 0;
4639 }
4640
4641 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4642 longmode = is_long_mode(vcpu) && cs_l == 1;
4643
4644 if (!longmode) {
ccd46936
GN		 4645 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
4646 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
4647 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
4648 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
4649 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
4650 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 4651 }
4652#ifdef CONFIG_X86_64
4653 else {
4654 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
4655 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
4656 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
4657 }
4658#endif
4659
4660 code = param & 0xffff;
4661 fast = (param >> 16) & 0x1;
4662 rep_cnt = (param >> 32) & 0xfff;
4663 rep_idx = (param >> 48) & 0xfff;
4664
4665 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
4666
c25bc163
GN		 4667 switch (code) {
4668 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
4669 kvm_vcpu_on_spin(vcpu);
4670 break;
4671 default:
4672 res = HV_STATUS_INVALID_HYPERCALL_CODE;
4673 break;
4674 }
55cd8e5a
GN		 4675
4676 ret = res | (((u64)rep_done & 0xfff) << 32);
4677 if (longmode) {
4678 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
4679 } else {
4680 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
4681 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
4682 }
4683
4684 return 1;
4685}
4686
8776e519
HB		 4687int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
4688{
4689 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 4690 int r = 1;
8776e519 4691
55cd8e5a
GN		 4692 if (kvm_hv_hypercall_enabled(vcpu->kvm))
4693 return kvm_hv_hypercall(vcpu);
4694
5fdbf976
MT		 4695 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
4696 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
4697 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
4698 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
4699 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 4700
229456fc 4701 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 4702
8776e519
HB		 4703 if (!is_long_mode(vcpu)) {
4704 nr &= 0xFFFFFFFF;
4705 a0 &= 0xFFFFFFFF;
4706 a1 &= 0xFFFFFFFF;
4707 a2 &= 0xFFFFFFFF;
4708 a3 &= 0xFFFFFFFF;
4709 }
4710
07708c4a
JK		 4711 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
4712 ret = -KVM_EPERM;
4713 goto out;
4714 }
4715
8776e519 4716 switch (nr) {
b93463aa
AK		 4717 case KVM_HC_VAPIC_POLL_IRQ:
4718 ret = 0;
4719 break;
2f333bcb
MT		 4720 case KVM_HC_MMU_OP:
4721 r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret);
4722 break;
8776e519
HB		 4723 default:
4724 ret = -KVM_ENOSYS;
4725 break;
4726 }
07708c4a 4727out:
5fdbf976 4728 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 4729 ++vcpu->stat.hypercalls;
2f333bcb 4730 return r;
8776e519
HB		 4731}
4732EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
4733
4734int kvm_fix_hypercall(struct kvm_vcpu *vcpu)
4735{
4736 char instruction[3];
5fdbf976 4737 unsigned long rip = kvm_rip_read(vcpu);
8776e519 4738
8776e519
HB		 4739 /*
4740 * Blow out the MMU to ensure that no other VCPU has an active mapping
4741 * to ensure that the updated hypercall appears atomically across all
4742 * VCPUs.
4743 */
4744 kvm_mmu_zap_all(vcpu->kvm);
4745
8776e519 4746 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 4747
8fe681e9 4748 return emulator_write_emulated(rip, instruction, 3, NULL, vcpu);
8776e519
HB		 4749}
4750
8776e519
HB		 4751void realmode_lgdt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
4752{
89a27f4d 4753 struct desc_ptr dt = { limit, base };
8776e519
HB		 4754
4755 kvm_x86_ops->set_gdt(vcpu, &dt);
4756}
4757
4758void realmode_lidt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
4759{
89a27f4d 4760 struct desc_ptr dt = { limit, base };
8776e519
HB		 4761
4762 kvm_x86_ops->set_idt(vcpu, &dt);
4763}
4764
07716717
DK		 4765static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)
4766{
ad312c7c
ZX		 4767 struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];
4768 int j, nent = vcpu->arch.cpuid_nent;
07716717
DK		 4769
4770 e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;
4771 /* when no next entry is found, the current entry[i] is reselected */
0fdf8e59 4772 for (j = i + 1; ; j = (j + 1) % nent) {
ad312c7c 4773 struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j];
07716717
DK		 4774 if (ej->function == e->function) {
4775 ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
4776 return j;
4777 }
4778 }
4779 return 0; /* silence gcc, even though control never reaches here */
4780}
4781
4782/* find an entry with matching function, matching index (if needed), and that
4783 * should be read next (if it's stateful) */
4784static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e,
4785 u32 function, u32 index)
4786{
4787 if (e->function != function)
4788 return 0;
4789 if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index)
4790 return 0;
4791 if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) &&
19355475 4792 !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT))
07716717
DK		 4793 return 0;
4794 return 1;
4795}
4796
d8017474
AG		 4797struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
4798 u32 function, u32 index)
8776e519
HB		 4799{
4800 int i;
d8017474 4801 struct kvm_cpuid_entry2 *best = NULL;
8776e519 4802
ad312c7c 4803 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
d8017474
AG		 4804 struct kvm_cpuid_entry2 *e;
4805
ad312c7c 4806 e = &vcpu->arch.cpuid_entries[i];
07716717
DK		 4807 if (is_matching_cpuid_entry(e, function, index)) {
4808 if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC)
4809 move_to_next_stateful_cpuid_entry(vcpu, i);
8776e519
HB		 4810 best = e;
4811 break;
4812 }
4813 /*
4814 * Both basic or both extended?
4815 */
4816 if (((e->function ^ function) & 0x80000000) == 0)
4817 if (!best || e->function > best->function)
4818 best = e;
4819 }
d8017474
AG		 4820 return best;
4821}
0e851880 4822EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry);
d8017474 4823
82725b20
DE		 4824int cpuid_maxphyaddr(struct kvm_vcpu *vcpu)
4825{
4826 struct kvm_cpuid_entry2 *best;
4827
f7a71197
AK		 4828 best = kvm_find_cpuid_entry(vcpu, 0x80000000, 0);
4829 if (!best || best->eax < 0x80000008)
4830 goto not_found;
82725b20
DE		 4831 best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0);
4832 if (best)
4833 return best->eax & 0xff;
f7a71197 4834not_found:
82725b20
DE		 4835 return 36;
4836}
4837
d8017474
AG		 4838void kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
4839{
4840 u32 function, index;
4841 struct kvm_cpuid_entry2 *best;
4842
4843 function = kvm_register_read(vcpu, VCPU_REGS_RAX);
4844 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
4845 kvm_register_write(vcpu, VCPU_REGS_RAX, 0);
4846 kvm_register_write(vcpu, VCPU_REGS_RBX, 0);
4847 kvm_register_write(vcpu, VCPU_REGS_RCX, 0);
4848 kvm_register_write(vcpu, VCPU_REGS_RDX, 0);
4849 best = kvm_find_cpuid_entry(vcpu, function, index);
8776e519 4850 if (best) {
5fdbf976
MT		 4851 kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax);
4852 kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx);
4853 kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx);
4854 kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx);
8776e519 4855 }
8776e519 4856 kvm_x86_ops->skip_emulated_instruction(vcpu);
229456fc
MT		 4857 trace_kvm_cpuid(function,
4858 kvm_register_read(vcpu, VCPU_REGS_RAX),
4859 kvm_register_read(vcpu, VCPU_REGS_RBX),
4860 kvm_register_read(vcpu, VCPU_REGS_RCX),
4861 kvm_register_read(vcpu, VCPU_REGS_RDX));
8776e519
HB		 4862}
4863EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
d0752060 4864
b6c7a5dc
HB		 4865/*
4866 * Check if userspace requested an interrupt window, and that the
4867 * interrupt window is open.
4868 *
4869 * No need to exit to userspace if we already have an interrupt queued.
4870 */
851ba692 4871static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 4872{
8061823a 4873 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 4874 vcpu->run->request_interrupt_window &&
5df56646 4875 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 4876}
4877
851ba692 4878static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 4879{
851ba692
AK		 4880 struct kvm_run *kvm_run = vcpu->run;
4881
91586a3b 4882 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 4883 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 4884 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 4885 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 4886 kvm_run->ready_for_interrupt_injection = 1;
4531220b 4887 else
b6c7a5dc 4888 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 4889 kvm_arch_interrupt_allowed(vcpu) &&
4890 !kvm_cpu_has_interrupt(vcpu) &&
4891 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 4892}
4893
b93463aa
AK		 4894static void vapic_enter(struct kvm_vcpu *vcpu)
4895{
4896 struct kvm_lapic *apic = vcpu->arch.apic;
4897 struct page *page;
4898
4899 if (!apic || !apic->vapic_addr)
4900 return;
4901
4902 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
72dc67a6
IE		 4903
4904 vcpu->arch.apic->vapic_page = page;
b93463aa
AK		 4905}
4906
4907static void vapic_exit(struct kvm_vcpu *vcpu)
4908{
4909 struct kvm_lapic *apic = vcpu->arch.apic;
f656ce01 4910 int idx;
b93463aa
AK		 4911
4912 if (!apic || !apic->vapic_addr)
4913 return;
4914
f656ce01 4915 idx = srcu_read_lock(&vcpu->kvm->srcu);
b93463aa
AK		 4916 kvm_release_page_dirty(apic->vapic_page);
4917 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f656ce01 4918 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 4919}
4920
95ba8273
GN		 4921static void update_cr8_intercept(struct kvm_vcpu *vcpu)
4922{
4923 int max_irr, tpr;
4924
4925 if (!kvm_x86_ops->update_cr8_intercept)
4926 return;
4927
88c808fd
AK		 4928 if (!vcpu->arch.apic)
4929 return;
4930
8db3baa2
GN		 4931 if (!vcpu->arch.apic->vapic_addr)
4932 max_irr = kvm_lapic_find_highest_irr(vcpu);
4933 else
4934 max_irr = -1;
95ba8273
GN		 4935
4936 if (max_irr != -1)
4937 max_irr >>= 4;
4938
4939 tpr = kvm_lapic_get_cr8(vcpu);
4940
4941 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
4942}
4943
851ba692 4944static void inject_pending_event(struct kvm_vcpu *vcpu)
95ba8273
GN		 4945{
4946 /* try to reinject previous events if any */
b59bb7bd 4947 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 4948 trace_kvm_inj_exception(vcpu->arch.exception.nr,
4949 vcpu->arch.exception.has_error_code,
4950 vcpu->arch.exception.error_code);
b59bb7bd
GN		 4951 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
4952 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 4953 vcpu->arch.exception.error_code,
4954 vcpu->arch.exception.reinject);
b59bb7bd
GN		 4955 return;
4956 }
4957
95ba8273
GN		 4958 if (vcpu->arch.nmi_injected) {
4959 kvm_x86_ops->set_nmi(vcpu);
4960 return;
4961 }
4962
4963 if (vcpu->arch.interrupt.pending) {
66fd3f7f 4964 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 4965 return;
4966 }
4967
4968 /* try to inject new event if pending */
4969 if (vcpu->arch.nmi_pending) {
4970 if (kvm_x86_ops->nmi_allowed(vcpu)) {
4971 vcpu->arch.nmi_pending = false;
4972 vcpu->arch.nmi_injected = true;
4973 kvm_x86_ops->set_nmi(vcpu);
4974 }
4975 } else if (kvm_cpu_has_interrupt(vcpu)) {
4976 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 4977 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
4978 false);
4979 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 4980 }
4981 }
4982}
4983
2acf923e
DC		 4984static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
4985{
4986 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
4987 !vcpu->guest_xcr0_loaded) {
4988 /* kvm_set_xcr() also depends on this */
4989 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
4990 vcpu->guest_xcr0_loaded = 1;
4991 }
4992}
4993
4994static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
4995{
4996 if (vcpu->guest_xcr0_loaded) {
4997 if (vcpu->arch.xcr0 != host_xcr0)
4998 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
4999 vcpu->guest_xcr0_loaded = 0;
5000 }
5001}
5002
851ba692 5003static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 5004{
5005 int r;
6a8b1d13 5006 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 5007 vcpu->run->request_interrupt_window;
3842d135 5008 bool req_event;
b6c7a5dc 5009
3e007509 5010 if (vcpu->requests) {
a8eeb04a 5011 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 5012 kvm_mmu_unload(vcpu);
a8eeb04a 5013 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 5014 __kvm_migrate_timers(vcpu);
8cfdc000
ZA		 5015 if (kvm_check_request(KVM_REQ_KVMCLOCK_UPDATE, vcpu)) {
5016 r = kvm_write_guest_time(vcpu);
5017 if (unlikely(r))
5018 goto out;
5019 }
a8eeb04a 5020 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 5021 kvm_mmu_sync_roots(vcpu);
a8eeb04a 5022 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
d4acf7e7 5023 kvm_x86_ops->tlb_flush(vcpu);
a8eeb04a 5024 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 5025 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 5026 r = 0;
5027 goto out;
5028 }
a8eeb04a 5029 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 5030 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 5031 r = 0;
5032 goto out;
5033 }
a8eeb04a 5034 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 5035 vcpu->fpu_active = 0;
5036 kvm_x86_ops->fpu_deactivate(vcpu);
5037 }
2f52d58c 5038 }
b93463aa 5039
3e007509
AK		 5040 r = kvm_mmu_reload(vcpu);
5041 if (unlikely(r))
5042 goto out;
5043
b6c7a5dc
HB		 5044 preempt_disable();
5045
5046 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 5047 if (vcpu->fpu_active)
5048 kvm_load_guest_fpu(vcpu);
2acf923e 5049 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 5050
d94e1dc9
AK		 5051 atomic_set(&vcpu->guest_mode, 1);
5052 smp_wmb();
b6c7a5dc 5053
d94e1dc9 5054 local_irq_disable();
32f88400 5055
3842d135
AK		 5056 req_event = kvm_check_request(KVM_REQ_EVENT, vcpu);
5057
d94e1dc9
AK		 5058 if (!atomic_read(&vcpu->guest_mode) || vcpu->requests
5059 || need_resched() || signal_pending(current)) {
3842d135
AK		 5060 if (req_event)
5061 kvm_make_request(KVM_REQ_EVENT, vcpu);
d94e1dc9
AK		 5062 atomic_set(&vcpu->guest_mode, 0);
5063 smp_wmb();
6c142801
AK		 5064 local_irq_enable();
5065 preempt_enable();
5066 r = 1;
5067 goto out;
5068 }
5069
3842d135
AK		 5070 if (req_event || req_int_win) {
5071 inject_pending_event(vcpu);
b6c7a5dc 5072
3842d135
AK		 5073 /* enable NMI/IRQ window open exits if needed */
5074 if (vcpu->arch.nmi_pending)
5075 kvm_x86_ops->enable_nmi_window(vcpu);
5076 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
5077 kvm_x86_ops->enable_irq_window(vcpu);
6a8b1d13 5078
3842d135
AK		 5079 if (kvm_lapic_enabled(vcpu)) {
5080 update_cr8_intercept(vcpu);
5081 kvm_lapic_sync_to_vapic(vcpu);
5082 }
95ba8273 5083 }
b93463aa 5084
f656ce01 5085 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
3200f405 5086
b6c7a5dc
HB		 5087 kvm_guest_enter();
5088
42dbaa5a 5089 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 5090 set_debugreg(0, 7);
5091 set_debugreg(vcpu->arch.eff_db[0], 0);
5092 set_debugreg(vcpu->arch.eff_db[1], 1);
5093 set_debugreg(vcpu->arch.eff_db[2], 2);
5094 set_debugreg(vcpu->arch.eff_db[3], 3);
5095 }
b6c7a5dc 5096
229456fc 5097 trace_kvm_entry(vcpu->vcpu_id);
851ba692 5098 kvm_x86_ops->run(vcpu);
b6c7a5dc 5099
24f1e32c
FW		 5100 /*
5101 * If the guest has used debug registers, at least dr7
5102 * will be disabled while returning to the host.
5103 * If we don't have active breakpoints in the host, we don't
5104 * care about the messed up debug address registers. But if
5105 * we have some of them active, restore the old state.
5106 */
59d8eb53 5107 if (hw_breakpoint_active())
24f1e32c 5108 hw_breakpoint_restore();
42dbaa5a 5109
1d5f066e
ZA		 5110 kvm_get_msr(vcpu, MSR_IA32_TSC, &vcpu->arch.last_guest_tsc);
5111
d94e1dc9
AK		 5112 atomic_set(&vcpu->guest_mode, 0);
5113 smp_wmb();
b6c7a5dc
HB		 5114 local_irq_enable();
5115
5116 ++vcpu->stat.exits;
5117
5118 /*
5119 * We must have an instruction between local_irq_enable() and
5120 * kvm_guest_exit(), so the timer interrupt isn't delayed by
5121 * the interrupt shadow. The stat.exits increment will do nicely.
5122 * But we need to prevent reordering, hence this barrier():
5123 */
5124 barrier();
5125
5126 kvm_guest_exit();
5127
5128 preempt_enable();
5129
f656ce01 5130 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 5131
b6c7a5dc
HB		 5132 /*
5133 * Profile KVM exit RIPs:
5134 */
5135 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 5136 unsigned long rip = kvm_rip_read(vcpu);
5137 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 5138 }
5139
298101da 5140
b93463aa
AK		 5141 kvm_lapic_sync_from_vapic(vcpu);
5142
851ba692 5143 r = kvm_x86_ops->handle_exit(vcpu);
d7690175
MT		 5144out:
5145 return r;
5146}
b6c7a5dc 5147
09cec754 5148
851ba692 5149static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 5150{
5151 int r;
f656ce01 5152 struct kvm *kvm = vcpu->kvm;
d7690175
MT		 5153
5154 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
1b10bf31
JK		 5155 pr_debug("vcpu %d received sipi with vector # %x\n",
5156 vcpu->vcpu_id, vcpu->arch.sipi_vector);
d7690175 5157 kvm_lapic_reset(vcpu);
5f179287 5158 r = kvm_arch_vcpu_reset(vcpu);
d7690175
MT		 5159 if (r)
5160 return r;
5161 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 5162 }
5163
f656ce01 5164 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175
MT		 5165 vapic_enter(vcpu);
5166
5167 r = 1;
5168 while (r > 0) {
af2152f5 5169 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE)
851ba692 5170 r = vcpu_enter_guest(vcpu);
d7690175 5171 else {
f656ce01 5172 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 5173 kvm_vcpu_block(vcpu);
f656ce01 5174 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
a8eeb04a 5175 if (kvm_check_request(KVM_REQ_UNHALT, vcpu))
09cec754
GN		 5176 {
5177 switch(vcpu->arch.mp_state) {
5178 case KVM_MP_STATE_HALTED:
d7690175 5179 vcpu->arch.mp_state =
09cec754
GN		 5180 KVM_MP_STATE_RUNNABLE;
5181 case KVM_MP_STATE_RUNNABLE:
5182 break;
5183 case KVM_MP_STATE_SIPI_RECEIVED:
5184 default:
5185 r = -EINTR;
5186 break;
5187 }
5188 }
d7690175
MT		 5189 }
5190
09cec754
GN		 5191 if (r <= 0)
5192 break;
5193
5194 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
5195 if (kvm_cpu_has_pending_timer(vcpu))
5196 kvm_inject_pending_timer_irqs(vcpu);
5197
851ba692 5198 if (dm_request_for_irq_injection(vcpu)) {
09cec754 5199 r = -EINTR;
851ba692 5200 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5201 ++vcpu->stat.request_irq_exits;
5202 }
5203 if (signal_pending(current)) {
5204 r = -EINTR;
851ba692 5205 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5206 ++vcpu->stat.signal_exits;
5207 }
5208 if (need_resched()) {
f656ce01 5209 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
09cec754 5210 kvm_resched(vcpu);
f656ce01 5211 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 5212 }
b6c7a5dc
HB		 5213 }
5214
f656ce01 5215 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc 5216
b93463aa
AK		 5217 vapic_exit(vcpu);
5218
b6c7a5dc
HB		 5219 return r;
5220}
5221
5222int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
5223{
5224 int r;
5225 sigset_t sigsaved;
5226
ac9f6dc0
AK		 5227 if (vcpu->sigset_active)
5228 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
5229
a4535290 5230 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 5231 kvm_vcpu_block(vcpu);
d7690175 5232 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 5233 r = -EAGAIN;
5234 goto out;
b6c7a5dc
HB		 5235 }
5236
b6c7a5dc
HB		 5237 /* re-sync apic's tpr */
5238 if (!irqchip_in_kernel(vcpu->kvm))
2d3ad1f4 5239 kvm_set_cr8(vcpu, kvm_run->cr8);
b6c7a5dc 5240
d2ddd1c4 5241 if (vcpu->arch.pio.count || vcpu->mmio_needed) {
92bf9748
GN		 5242 if (vcpu->mmio_needed) {
5243 memcpy(vcpu->mmio_data, kvm_run->mmio.data, 8);
5244 vcpu->mmio_read_completed = 1;
5245 vcpu->mmio_needed = 0;
b6c7a5dc 5246 }
f656ce01 5247 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5cd21917 5248 r = emulate_instruction(vcpu, 0, 0, EMULTYPE_NO_DECODE);
f656ce01 5249 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6d77dbfc 5250 if (r != EMULATE_DONE) {
b6c7a5dc
HB		 5251 r = 0;
5252 goto out;
5253 }
5254 }
5fdbf976
MT		 5255 if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL)
5256 kvm_register_write(vcpu, VCPU_REGS_RAX,
5257 kvm_run->hypercall.ret);
b6c7a5dc 5258
851ba692 5259 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 5260
5261out:
f1d86e46 5262 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 5263 if (vcpu->sigset_active)
5264 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
5265
b6c7a5dc
HB		 5266 return r;
5267}
5268
5269int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5270{
5fdbf976
MT		 5271 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
5272 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
5273 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
5274 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
5275 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
5276 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
5277 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
5278 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 5279#ifdef CONFIG_X86_64
5fdbf976
MT		 5280 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
5281 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
5282 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
5283 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
5284 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
5285 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
5286 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
5287 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 5288#endif
5289
5fdbf976 5290 regs->rip = kvm_rip_read(vcpu);
91586a3b 5291 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 5292
b6c7a5dc
HB		 5293 return 0;
5294}
5295
5296int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5297{
5fdbf976
MT		 5298 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
5299 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
5300 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
5301 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
5302 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
5303 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
5304 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
5305 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 5306#ifdef CONFIG_X86_64
5fdbf976
MT		 5307 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
5308 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
5309 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
5310 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
5311 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
5312 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
5313 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
5314 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 5315#endif
5316
5fdbf976 5317 kvm_rip_write(vcpu, regs->rip);
91586a3b 5318 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 5319
b4f14abd
JK		 5320 vcpu->arch.exception.pending = false;
5321
3842d135
AK		 5322 kvm_make_request(KVM_REQ_EVENT, vcpu);
5323
b6c7a5dc
HB		 5324 return 0;
5325}
5326
b6c7a5dc
HB		 5327void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
5328{
5329 struct kvm_segment cs;
5330
3e6e0aab 5331 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 5332 *db = cs.db;
5333 *l = cs.l;
5334}
5335EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
5336
5337int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
5338 struct kvm_sregs *sregs)
5339{
89a27f4d 5340 struct desc_ptr dt;
b6c7a5dc 5341
3e6e0aab
GT		 5342 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5343 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5344 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5345 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5346 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5347 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 5348
3e6e0aab
GT		 5349 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5350 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 5351
5352 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 5353 sregs->idt.limit = dt.size;
5354 sregs->idt.base = dt.address;
b6c7a5dc 5355 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 5356 sregs->gdt.limit = dt.size;
5357 sregs->gdt.base = dt.address;
b6c7a5dc 5358
4d4ec087 5359 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c
ZX		 5360 sregs->cr2 = vcpu->arch.cr2;
5361 sregs->cr3 = vcpu->arch.cr3;
fc78f519 5362 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 5363 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 5364 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 5365 sregs->apic_base = kvm_get_apic_base(vcpu);
5366
923c61bb 5367 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 5368
36752c9b 5369 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 5370 set_bit(vcpu->arch.interrupt.nr,
5371 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 5372
b6c7a5dc
HB		 5373 return 0;
5374}
5375
62d9f0db
MT		 5376int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
5377 struct kvm_mp_state *mp_state)
5378{
62d9f0db 5379 mp_state->mp_state = vcpu->arch.mp_state;
62d9f0db
MT		 5380 return 0;
5381}
5382
5383int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
5384 struct kvm_mp_state *mp_state)
5385{
62d9f0db 5386 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 5387 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 5388 return 0;
5389}
5390
e269fb21
JK		 5391int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason,
5392 bool has_error_code, u32 error_code)
b6c7a5dc 5393{
4d2179e1 5394 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
8ec4722d 5395 int ret;
e01c2426 5396
8ec4722d 5397 init_emulate_ctxt(vcpu);
c697518a 5398
9aabc88f 5399 ret = emulator_task_switch(&vcpu->arch.emulate_ctxt,
e269fb21
JK		 5400 tss_selector, reason, has_error_code,
5401 error_code);
c697518a 5402
c697518a 5403 if (ret)
19d04437 5404 return EMULATE_FAIL;
37817f29 5405
4d2179e1 5406 memcpy(vcpu->arch.regs, c->regs, sizeof c->regs);
95c55886 5407 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.eip);
19d04437 5408 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
3842d135 5409 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 5410 return EMULATE_DONE;
37817f29
IE		 5411}
5412EXPORT_SYMBOL_GPL(kvm_task_switch);
5413
b6c7a5dc
HB		 5414int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
5415 struct kvm_sregs *sregs)
5416{
5417 int mmu_reset_needed = 0;
923c61bb 5418 int pending_vec, max_bits;
89a27f4d 5419 struct desc_ptr dt;
b6c7a5dc 5420
89a27f4d
GN		 5421 dt.size = sregs->idt.limit;
5422 dt.address = sregs->idt.base;
b6c7a5dc 5423 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 5424 dt.size = sregs->gdt.limit;
5425 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 5426 kvm_x86_ops->set_gdt(vcpu, &dt);
5427
ad312c7c
ZX		 5428 vcpu->arch.cr2 = sregs->cr2;
5429 mmu_reset_needed |= vcpu->arch.cr3 != sregs->cr3;
dc7e795e 5430 vcpu->arch.cr3 = sregs->cr3;
b6c7a5dc 5431
2d3ad1f4 5432 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 5433
f6801dff 5434 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 5435 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 5436 kvm_set_apic_base(vcpu, sregs->apic_base);
5437
4d4ec087 5438 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 5439 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 5440 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 5441
fc78f519 5442 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 5443 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
7c93be44 5444 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
ff03a073 5445 load_pdptrs(vcpu, vcpu->arch.walk_mmu, vcpu->arch.cr3);
7c93be44
MT		 5446 mmu_reset_needed = 1;
5447 }
b6c7a5dc
HB		 5448
5449 if (mmu_reset_needed)
5450 kvm_mmu_reset_context(vcpu);
5451
923c61bb
GN		 5452 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
5453 pending_vec = find_first_bit(
5454 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
5455 if (pending_vec < max_bits) {
66fd3f7f 5456 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb
GN		 5457 pr_debug("Set back pending irq %d\n", pending_vec);
5458 if (irqchip_in_kernel(vcpu->kvm))
5459 kvm_pic_clear_isr_ack(vcpu->kvm);
b6c7a5dc
HB		 5460 }
5461
3e6e0aab
GT		 5462 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5463 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5464 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5465 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5466 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5467 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 5468
3e6e0aab
GT		 5469 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5470 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 5471
5f0269f5
ME		 5472 update_cr8_intercept(vcpu);
5473
9c3e4aab 5474 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 5475 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 5476 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 5477 !is_protmode(vcpu))
9c3e4aab
MT		 5478 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
5479
3842d135
AK		 5480 kvm_make_request(KVM_REQ_EVENT, vcpu);
5481
b6c7a5dc
HB		 5482 return 0;
5483}
5484
d0bfb940
JK		 5485int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
5486 struct kvm_guest_debug *dbg)
b6c7a5dc 5487{
355be0b9 5488 unsigned long rflags;
ae675ef0 5489 int i, r;
b6c7a5dc 5490
4f926bf2
JK		 5491 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
5492 r = -EBUSY;
5493 if (vcpu->arch.exception.pending)
2122ff5e 5494 goto out;
4f926bf2
JK		 5495 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
5496 kvm_queue_exception(vcpu, DB_VECTOR);
5497 else
5498 kvm_queue_exception(vcpu, BP_VECTOR);
5499 }
5500
91586a3b
JK		 5501 /*
5502 * Read rflags as long as potentially injected trace flags are still
5503 * filtered out.
5504 */
5505 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 5506
5507 vcpu->guest_debug = dbg->control;
5508 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
5509 vcpu->guest_debug = 0;
5510
5511 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 5512 for (i = 0; i < KVM_NR_DB_REGS; ++i)
5513 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
5514 vcpu->arch.switch_db_regs =
5515 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
5516 } else {
5517 for (i = 0; i < KVM_NR_DB_REGS; i++)
5518 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
5519 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
5520 }
5521
f92653ee
JK		 5522 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
5523 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
5524 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 5525
91586a3b
JK		 5526 /*
5527 * Trigger an rflags update that will inject or remove the trace
5528 * flags.
5529 */
5530 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 5531
355be0b9 5532 kvm_x86_ops->set_guest_debug(vcpu, dbg);
b6c7a5dc 5533
4f926bf2 5534 r = 0;
d0bfb940 5535
2122ff5e 5536out:
b6c7a5dc
HB		 5537
5538 return r;
5539}
5540
8b006791
ZX		 5541/*
5542 * Translate a guest virtual address to a guest physical address.
5543 */
5544int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
5545 struct kvm_translation *tr)
5546{
5547 unsigned long vaddr = tr->linear_address;
5548 gpa_t gpa;
f656ce01 5549 int idx;
8b006791 5550
f656ce01 5551 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 5552 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 5553 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 5554 tr->physical_address = gpa;
5555 tr->valid = gpa != UNMAPPED_GVA;
5556 tr->writeable = 1;
5557 tr->usermode = 0;
8b006791
ZX		 5558
5559 return 0;
5560}
5561
d0752060
HB		 5562int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5563{
98918833
SY		 5564 struct i387_fxsave_struct *fxsave =
5565 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 5566
d0752060
HB		 5567 memcpy(fpu->fpr, fxsave->st_space, 128);
5568 fpu->fcw = fxsave->cwd;
5569 fpu->fsw = fxsave->swd;
5570 fpu->ftwx = fxsave->twd;
5571 fpu->last_opcode = fxsave->fop;
5572 fpu->last_ip = fxsave->rip;
5573 fpu->last_dp = fxsave->rdp;
5574 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
5575
d0752060
HB		 5576 return 0;
5577}
5578
5579int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5580{
98918833
SY		 5581 struct i387_fxsave_struct *fxsave =
5582 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 5583
d0752060
HB		 5584 memcpy(fxsave->st_space, fpu->fpr, 128);
5585 fxsave->cwd = fpu->fcw;
5586 fxsave->swd = fpu->fsw;
5587 fxsave->twd = fpu->ftwx;
5588 fxsave->fop = fpu->last_opcode;
5589 fxsave->rip = fpu->last_ip;
5590 fxsave->rdp = fpu->last_dp;
5591 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
5592
d0752060
HB		 5593 return 0;
5594}
5595
10ab25cd 5596int fx_init(struct kvm_vcpu *vcpu)
d0752060 5597{
10ab25cd
JK		 5598 int err;
5599
5600 err = fpu_alloc(&vcpu->arch.guest_fpu);
5601 if (err)
5602 return err;
5603
98918833 5604 fpu_finit(&vcpu->arch.guest_fpu);
d0752060 5605
2acf923e
DC		 5606 /*
5607 * Ensure guest xcr0 is valid for loading
5608 */
5609 vcpu->arch.xcr0 = XSTATE_FP;
5610
ad312c7c 5611 vcpu->arch.cr0 |= X86_CR0_ET;
10ab25cd
JK		 5612
5613 return 0;
d0752060
HB		 5614}
5615EXPORT_SYMBOL_GPL(fx_init);
5616
98918833
SY		 5617static void fx_free(struct kvm_vcpu *vcpu)
5618{
5619 fpu_free(&vcpu->arch.guest_fpu);
5620}
5621
d0752060
HB		 5622void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
5623{
2608d7a1 5624 if (vcpu->guest_fpu_loaded)
d0752060
HB		 5625 return;
5626
2acf923e
DC		 5627 /*
5628 * Restore all possible states in the guest,
5629 * and assume host would use all available bits.
5630 * Guest xcr0 would be loaded later.
5631 */
5632 kvm_put_guest_xcr0(vcpu);
d0752060 5633 vcpu->guest_fpu_loaded = 1;
7cf30855 5634 unlazy_fpu(current);
98918833 5635 fpu_restore_checking(&vcpu->arch.guest_fpu);
0c04851c 5636 trace_kvm_fpu(1);
d0752060 5637}
d0752060
HB		 5638
5639void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
5640{
2acf923e
DC		 5641 kvm_put_guest_xcr0(vcpu);
5642
d0752060
HB		 5643 if (!vcpu->guest_fpu_loaded)
5644 return;
5645
5646 vcpu->guest_fpu_loaded = 0;
98918833 5647 fpu_save_init(&vcpu->arch.guest_fpu);
f096ed85 5648 ++vcpu->stat.fpu_reload;
a8eeb04a 5649 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
0c04851c 5650 trace_kvm_fpu(0);
d0752060 5651}
e9b11c17
ZX		 5652
5653void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
5654{
7f1ea208
JR		 5655 if (vcpu->arch.time_page) {
5656 kvm_release_page_dirty(vcpu->arch.time_page);
5657 vcpu->arch.time_page = NULL;
5658 }
5659
f5f48ee1 5660 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
98918833 5661 fx_free(vcpu);
e9b11c17
ZX		 5662 kvm_x86_ops->vcpu_free(vcpu);
5663}
5664
5665struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
5666 unsigned int id)
5667{
6755bae8
ZA		 5668 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
5669 printk_once(KERN_WARNING
5670 "kvm: SMP vm created on host with unstable TSC; "
5671 "guest TSC will not be reliable\n");
26e5215f
AK		 5672 return kvm_x86_ops->vcpu_create(kvm, id);
5673}
e9b11c17 5674
26e5215f
AK		 5675int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
5676{
5677 int r;
e9b11c17 5678
0bed3b56 5679 vcpu->arch.mtrr_state.have_fixed = 1;
e9b11c17
ZX		 5680 vcpu_load(vcpu);
5681 r = kvm_arch_vcpu_reset(vcpu);
5682 if (r == 0)
5683 r = kvm_mmu_setup(vcpu);
5684 vcpu_put(vcpu);
5685 if (r < 0)
5686 goto free_vcpu;
5687
26e5215f 5688 return 0;
e9b11c17
ZX		 5689free_vcpu:
5690 kvm_x86_ops->vcpu_free(vcpu);
26e5215f 5691 return r;
e9b11c17
ZX		 5692}
5693
d40ccc62 5694void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17
ZX		 5695{
5696 vcpu_load(vcpu);
5697 kvm_mmu_unload(vcpu);
5698 vcpu_put(vcpu);
5699
98918833 5700 fx_free(vcpu);
e9b11c17
ZX		 5701 kvm_x86_ops->vcpu_free(vcpu);
5702}
5703
5704int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
5705{
448fa4a9
JK		 5706 vcpu->arch.nmi_pending = false;
5707 vcpu->arch.nmi_injected = false;
5708
42dbaa5a
JK		 5709 vcpu->arch.switch_db_regs = 0;
5710 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
5711 vcpu->arch.dr6 = DR6_FIXED_1;
5712 vcpu->arch.dr7 = DR7_FIXED_1;
5713
3842d135
AK		 5714 kvm_make_request(KVM_REQ_EVENT, vcpu);
5715
e9b11c17
ZX		 5716 return kvm_x86_ops->vcpu_reset(vcpu);
5717}
5718
10474ae8 5719int kvm_arch_hardware_enable(void *garbage)
e9b11c17 5720{
ca84d1a2
ZA		 5721 struct kvm *kvm;
5722 struct kvm_vcpu *vcpu;
5723 int i;
5724
18863bdd 5725 kvm_shared_msr_cpu_online();
ca84d1a2
ZA		 5726 list_for_each_entry(kvm, &vm_list, vm_list)
5727 kvm_for_each_vcpu(i, vcpu, kvm)
5728 if (vcpu->cpu == smp_processor_id())
5729 kvm_request_guest_time_update(vcpu);
10474ae8 5730 return kvm_x86_ops->hardware_enable(garbage);
e9b11c17
ZX		 5731}
5732
5733void kvm_arch_hardware_disable(void *garbage)
5734{
5735 kvm_x86_ops->hardware_disable(garbage);
3548bab5 5736 drop_user_return_notifiers(garbage);
e9b11c17
ZX		 5737}
5738
5739int kvm_arch_hardware_setup(void)
5740{
5741 return kvm_x86_ops->hardware_setup();
5742}
5743
5744void kvm_arch_hardware_unsetup(void)
5745{
5746 kvm_x86_ops->hardware_unsetup();
5747}
5748
5749void kvm_arch_check_processor_compat(void *rtn)
5750{
5751 kvm_x86_ops->check_processor_compatibility(rtn);
5752}
5753
5754int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
5755{
5756 struct page *page;
5757 struct kvm *kvm;
5758 int r;
5759
5760 BUG_ON(vcpu->kvm == NULL);
5761 kvm = vcpu->kvm;
5762
9aabc88f 5763 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
14dfe855 5764 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
ad312c7c 5765 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
c30a358d 5766 vcpu->arch.mmu.translate_gpa = translate_gpa;
02f59dc9 5767 vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa;
c5af89b6 5768 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 5769 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 5770 else
a4535290 5771 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 5772
5773 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
5774 if (!page) {
5775 r = -ENOMEM;
5776 goto fail;
5777 }
ad312c7c 5778 vcpu->arch.pio_data = page_address(page);
e9b11c17
ZX		 5779
5780 r = kvm_mmu_create(vcpu);
5781 if (r < 0)
5782 goto fail_free_pio_data;
5783
5784 if (irqchip_in_kernel(kvm)) {
5785 r = kvm_create_lapic(vcpu);
5786 if (r < 0)
5787 goto fail_mmu_destroy;
5788 }
5789
890ca9ae
HY		 5790 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
5791 GFP_KERNEL);
5792 if (!vcpu->arch.mce_banks) {
5793 r = -ENOMEM;
443c39bc 5794 goto fail_free_lapic;
890ca9ae
HY		 5795 }
5796 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
5797
f5f48ee1
SY		 5798 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL))
5799 goto fail_free_mce_banks;
5800
e9b11c17 5801 return 0;
f5f48ee1
SY		 5802fail_free_mce_banks:
5803 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 5804fail_free_lapic:
5805 kvm_free_lapic(vcpu);
e9b11c17
ZX		 5806fail_mmu_destroy:
5807 kvm_mmu_destroy(vcpu);
5808fail_free_pio_data:
ad312c7c 5809 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 5810fail:
5811 return r;
5812}
5813
5814void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
5815{
f656ce01
MT		 5816 int idx;
5817
36cb93fd 5818 kfree(vcpu->arch.mce_banks);
e9b11c17 5819 kvm_free_lapic(vcpu);
f656ce01 5820 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 5821 kvm_mmu_destroy(vcpu);
f656ce01 5822 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 5823 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17 5824}
d19a9cd2
ZX		 5825
5826struct kvm *kvm_arch_create_vm(void)
5827{
5828 struct kvm *kvm = kzalloc(sizeof(struct kvm), GFP_KERNEL);
5829
5830 if (!kvm)
5831 return ERR_PTR(-ENOMEM);
5832
f05e70ac 5833 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4d5c5d0f 5834 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2 5835
5550af4d
SY		 5836 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
5837 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
5838
99e3e30a
ZA		 5839 spin_lock_init(&kvm->arch.tsc_write_lock);
5840
d19a9cd2
ZX		 5841 return kvm;
5842}
5843
5844static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
5845{
5846 vcpu_load(vcpu);
5847 kvm_mmu_unload(vcpu);
5848 vcpu_put(vcpu);
5849}
5850
5851static void kvm_free_vcpus(struct kvm *kvm)
5852{
5853 unsigned int i;
988a2cae 5854 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 5855
5856 /*
5857 * Unpin any mmu pages first.
5858 */
988a2cae
GN		 5859 kvm_for_each_vcpu(i, vcpu, kvm)
5860 kvm_unload_vcpu_mmu(vcpu);
5861 kvm_for_each_vcpu(i, vcpu, kvm)
5862 kvm_arch_vcpu_free(vcpu);
5863
5864 mutex_lock(&kvm->lock);
5865 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
5866 kvm->vcpus[i] = NULL;
d19a9cd2 5867
988a2cae
GN		 5868 atomic_set(&kvm->online_vcpus, 0);
5869 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 5870}
5871
ad8ba2cd
SY		 5872void kvm_arch_sync_events(struct kvm *kvm)
5873{
ba4cef31 5874 kvm_free_all_assigned_devices(kvm);
aea924f6 5875 kvm_free_pit(kvm);
ad8ba2cd
SY		 5876}
5877
d19a9cd2
ZX		 5878void kvm_arch_destroy_vm(struct kvm *kvm)
5879{
6eb55818 5880 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 5881 kfree(kvm->arch.vpic);
5882 kfree(kvm->arch.vioapic);
d19a9cd2
ZX		 5883 kvm_free_vcpus(kvm);
5884 kvm_free_physmem(kvm);
3d45830c
AK		 5885 if (kvm->arch.apic_access_page)
5886 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 5887 if (kvm->arch.ept_identity_pagetable)
5888 put_page(kvm->arch.ept_identity_pagetable);
64749204 5889 cleanup_srcu_struct(&kvm->srcu);
d19a9cd2
ZX		 5890 kfree(kvm);
5891}
0de10343 5892
f7784b8e
MT		 5893int kvm_arch_prepare_memory_region(struct kvm *kvm,
5894 struct kvm_memory_slot *memslot,
0de10343 5895 struct kvm_memory_slot old,
f7784b8e 5896 struct kvm_userspace_memory_region *mem,
0de10343
ZX		 5897 int user_alloc)
5898{
f7784b8e 5899 int npages = memslot->npages;
7ac77099
AK		 5900 int map_flags = MAP_PRIVATE | MAP_ANONYMOUS;
5901
5902 /* Prevent internal slot pages from being moved by fork()/COW. */
5903 if (memslot->id >= KVM_MEMORY_SLOTS)
5904 map_flags = MAP_SHARED | MAP_ANONYMOUS;
0de10343
ZX		 5905
5906 /*To keep backward compatibility with older userspace,
5907 *x86 needs to hanlde !user_alloc case.
5908 */
5909 if (!user_alloc) {
5910 if (npages && !old.rmap) {
604b38ac
AA		 5911 unsigned long userspace_addr;
5912
72dc67a6 5913 down_write(&current->mm->mmap_sem);
604b38ac
AA		 5914 userspace_addr = do_mmap(NULL, 0,
5915 npages * PAGE_SIZE,
5916 PROT_READ | PROT_WRITE,
7ac77099 5917 map_flags,
604b38ac 5918 0);
72dc67a6 5919 up_write(&current->mm->mmap_sem);
0de10343 5920
604b38ac
AA		 5921 if (IS_ERR((void *)userspace_addr))
5922 return PTR_ERR((void *)userspace_addr);
5923
604b38ac 5924 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 5925 }
5926 }
5927
f7784b8e
MT		 5928
5929 return 0;
5930}
5931
5932void kvm_arch_commit_memory_region(struct kvm *kvm,
5933 struct kvm_userspace_memory_region *mem,
5934 struct kvm_memory_slot old,
5935 int user_alloc)
5936{
5937
5938 int npages = mem->memory_size >> PAGE_SHIFT;
5939
5940 if (!user_alloc && !old.user_alloc && old.rmap && !npages) {
5941 int ret;
5942
5943 down_write(&current->mm->mmap_sem);
5944 ret = do_munmap(current->mm, old.userspace_addr,
5945 old.npages * PAGE_SIZE);
5946 up_write(&current->mm->mmap_sem);
5947 if (ret < 0)
5948 printk(KERN_WARNING
5949 "kvm_vm_ioctl_set_memory_region: "
5950 "failed to munmap memory\n");
5951 }
5952
7c8a83b7 5953 spin_lock(&kvm->mmu_lock);
f05e70ac 5954 if (!kvm->arch.n_requested_mmu_pages) {
0de10343
ZX		 5955 unsigned int nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
5956 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
5957 }
5958
5959 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
7c8a83b7 5960 spin_unlock(&kvm->mmu_lock);
0de10343 5961}
1d737c8a 5962
34d4cb8f
MT		 5963void kvm_arch_flush_shadow(struct kvm *kvm)
5964{
5965 kvm_mmu_zap_all(kvm);
8986ecc0 5966 kvm_reload_remote_mmus(kvm);
34d4cb8f
MT		 5967}
5968
1d737c8a
ZX		 5969int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
5970{
a4535290 5971 return vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE
a1b37100
GN		 5972 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
5973 || vcpu->arch.nmi_pending ||
5974 (kvm_arch_interrupt_allowed(vcpu) &&
5975 kvm_cpu_has_interrupt(vcpu));
1d737c8a 5976}
5736199a 5977
5736199a
ZX		 5978void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
5979{
32f88400
MT		 5980 int me;
5981 int cpu = vcpu->cpu;
5736199a
ZX		 5982
5983 if (waitqueue_active(&vcpu->wq)) {
5984 wake_up_interruptible(&vcpu->wq);
5985 ++vcpu->stat.halt_wakeup;
5986 }
32f88400
MT		 5987
5988 me = get_cpu();
5989 if (cpu != me && (unsigned)cpu < nr_cpu_ids && cpu_online(cpu))
d94e1dc9 5990 if (atomic_xchg(&vcpu->guest_mode, 0))
32f88400 5991 smp_send_reschedule(cpu);
e9571ed5 5992 put_cpu();
5736199a 5993}
78646121
GN		 5994
5995int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
5996{
5997 return kvm_x86_ops->interrupt_allowed(vcpu);
5998}
229456fc 5999
f92653ee
JK		 6000bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
6001{
6002 unsigned long current_rip = kvm_rip_read(vcpu) +
6003 get_segment_base(vcpu, VCPU_SREG_CS);
6004
6005 return current_rip == linear_rip;
6006}
6007EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
6008
94fe45da
JK		 6009unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
6010{
6011 unsigned long rflags;
6012
6013 rflags = kvm_x86_ops->get_rflags(vcpu);
6014 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 6015 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 6016 return rflags;
6017}
6018EXPORT_SYMBOL_GPL(kvm_get_rflags);
6019
6020void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
6021{
6022 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 6023 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 6024 rflags |= X86_EFLAGS_TF;
94fe45da 6025 kvm_x86_ops->set_rflags(vcpu, rflags);
3842d135 6026 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 6027}
6028EXPORT_SYMBOL_GPL(kvm_set_rflags);
6029
229456fc
MT		 6030EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
6031EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
6032EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
6033EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
6034EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 6035EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 6036EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 6037EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 6038EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 6039EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 6040EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 6041EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
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