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KVM: remove realmode_lmsw function.
[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
043405e1
CO		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 13 * Amit Shah <amit.shah@qumranet.com>
14 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 */
20
edf88417 21#include <linux/kvm_host.h>
313a3dc7 22#include "irq.h"
1d737c8a 23#include "mmu.h"
7837699f 24#include "i8254.h"
37817f29 25#include "tss.h"
5fdbf976 26#include "kvm_cache_regs.h"
26eef70c 27#include "x86.h"
313a3dc7 28
18068523 29#include <linux/clocksource.h>
4d5c5d0f 30#include <linux/interrupt.h>
313a3dc7
CO		 31#include <linux/kvm.h>
32#include <linux/fs.h>
33#include <linux/vmalloc.h>
5fb76f9b 34#include <linux/module.h>
0de10343 35#include <linux/mman.h>
2bacc55c 36#include <linux/highmem.h>
19de40a8 37#include <linux/iommu.h>
62c476c7 38#include <linux/intel-iommu.h>
c8076604 39#include <linux/cpufreq.h>
18863bdd 40#include <linux/user-return-notifier.h>
a983fb23 41#include <linux/srcu.h>
5a0e3ad6 42#include <linux/slab.h>
aec51dc4 43#include <trace/events/kvm.h>
2ed152af 44
229456fc
MT		 45#define CREATE_TRACE_POINTS
46#include "trace.h"
043405e1 47
24f1e32c 48#include <asm/debugreg.h>
043405e1 49#include <asm/uaccess.h>
d825ed0a 50#include <asm/msr.h>
a5f61300 51#include <asm/desc.h>
0bed3b56 52#include <asm/mtrr.h>
890ca9ae 53#include <asm/mce.h>
043405e1 54
313a3dc7 55#define MAX_IO_MSRS 256
a03490ed
CO		 56#define CR0_RESERVED_BITS \
57 (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \
58 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \
59 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG))
60#define CR4_RESERVED_BITS \
61 (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\
62 | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \
63 | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR \
64 | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE))
65
66#define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
890ca9ae
HY		 67
68#define KVM_MAX_MCE_BANKS 32
69#define KVM_MCE_CAP_SUPPORTED MCG_CTL_P
70
50a37eb4
JR		 71/* EFER defaults:
72 * - enable syscall per default because its emulated by KVM
73 * - enable LME and LMA per default on 64 bit KVM
74 */
75#ifdef CONFIG_X86_64
76static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffafeULL;
77#else
78static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffffeULL;
79#endif
313a3dc7 80
ba1389b7
AK		 81#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
82#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 83
cb142eb7 84static void update_cr8_intercept(struct kvm_vcpu *vcpu);
674eea0f
AK		 85static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
86 struct kvm_cpuid_entry2 __user *entries);
87
97896d04 88struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 89EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 90
ed85c068
AP		 91int ignore_msrs = 0;
92module_param_named(ignore_msrs, ignore_msrs, bool, S_IRUGO | S_IWUSR);
93
18863bdd
AK		 94#define KVM_NR_SHARED_MSRS 16
95
96struct kvm_shared_msrs_global {
97 int nr;
2bf78fa7 98 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 99};
100
101struct kvm_shared_msrs {
102 struct user_return_notifier urn;
103 bool registered;
2bf78fa7
SY		 104 struct kvm_shared_msr_values {
105 u64 host;
106 u64 curr;
107 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 108};
109
110static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
111static DEFINE_PER_CPU(struct kvm_shared_msrs, shared_msrs);
112
417bc304 113struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 114 { "pf_fixed", VCPU_STAT(pf_fixed) },
115 { "pf_guest", VCPU_STAT(pf_guest) },
116 { "tlb_flush", VCPU_STAT(tlb_flush) },
117 { "invlpg", VCPU_STAT(invlpg) },
118 { "exits", VCPU_STAT(exits) },
119 { "io_exits", VCPU_STAT(io_exits) },
120 { "mmio_exits", VCPU_STAT(mmio_exits) },
121 { "signal_exits", VCPU_STAT(signal_exits) },
122 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 123 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 124 { "halt_exits", VCPU_STAT(halt_exits) },
125 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 126 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 127 { "request_irq", VCPU_STAT(request_irq_exits) },
128 { "irq_exits", VCPU_STAT(irq_exits) },
129 { "host_state_reload", VCPU_STAT(host_state_reload) },
130 { "efer_reload", VCPU_STAT(efer_reload) },
131 { "fpu_reload", VCPU_STAT(fpu_reload) },
132 { "insn_emulation", VCPU_STAT(insn_emulation) },
133 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 134 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 135 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 136 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
137 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
138 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
139 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
140 { "mmu_flooded", VM_STAT(mmu_flooded) },
141 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 142 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 143 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 144 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 145 { "largepages", VM_STAT(lpages) },
417bc304
HB		 146 { NULL }
147};
148
18863bdd
AK		 149static void kvm_on_user_return(struct user_return_notifier *urn)
150{
151 unsigned slot;
18863bdd
AK		 152 struct kvm_shared_msrs *locals
153 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 154 struct kvm_shared_msr_values *values;
18863bdd
AK		 155
156 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 157 values = &locals->values[slot];
158 if (values->host != values->curr) {
159 wrmsrl(shared_msrs_global.msrs[slot], values->host);
160 values->curr = values->host;
18863bdd
AK		 161 }
162 }
163 locals->registered = false;
164 user_return_notifier_unregister(urn);
165}
166
2bf78fa7 167static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 168{
2bf78fa7 169 struct kvm_shared_msrs *smsr;
18863bdd
AK		 170 u64 value;
171
2bf78fa7
SY		 172 smsr = &__get_cpu_var(shared_msrs);
173 /* only read, and nobody should modify it at this time,
174 * so don't need lock */
175 if (slot >= shared_msrs_global.nr) {
176 printk(KERN_ERR "kvm: invalid MSR slot!");
177 return;
178 }
179 rdmsrl_safe(msr, &value);
180 smsr->values[slot].host = value;
181 smsr->values[slot].curr = value;
182}
183
184void kvm_define_shared_msr(unsigned slot, u32 msr)
185{
18863bdd
AK		 186 if (slot >= shared_msrs_global.nr)
187 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 188 shared_msrs_global.msrs[slot] = msr;
189 /* we need ensured the shared_msr_global have been updated */
190 smp_wmb();
18863bdd
AK		 191}
192EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
193
194static void kvm_shared_msr_cpu_online(void)
195{
196 unsigned i;
18863bdd
AK		 197
198 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 199 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 200}
201
d5696725 202void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd
AK		 203{
204 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
205
2bf78fa7 206 if (((value ^ smsr->values[slot].curr) & mask) == 0)
18863bdd 207 return;
2bf78fa7
SY		 208 smsr->values[slot].curr = value;
209 wrmsrl(shared_msrs_global.msrs[slot], value);
18863bdd
AK		 210 if (!smsr->registered) {
211 smsr->urn.on_user_return = kvm_on_user_return;
212 user_return_notifier_register(&smsr->urn);
213 smsr->registered = true;
214 }
215}
216EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
217
3548bab5
AK		 218static void drop_user_return_notifiers(void *ignore)
219{
220 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
221
222 if (smsr->registered)
223 kvm_on_user_return(&smsr->urn);
224}
225
6866b83e
CO		 226u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
227{
228 if (irqchip_in_kernel(vcpu->kvm))
ad312c7c 229 return vcpu->arch.apic_base;
6866b83e 230 else
ad312c7c 231 return vcpu->arch.apic_base;
6866b83e
CO		 232}
233EXPORT_SYMBOL_GPL(kvm_get_apic_base);
234
235void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
236{
237 /* TODO: reserve bits check */
238 if (irqchip_in_kernel(vcpu->kvm))
239 kvm_lapic_set_base(vcpu, data);
240 else
ad312c7c 241 vcpu->arch.apic_base = data;
6866b83e
CO		 242}
243EXPORT_SYMBOL_GPL(kvm_set_apic_base);
244
3fd28fce
ED		 245#define EXCPT_BENIGN 0
246#define EXCPT_CONTRIBUTORY 1
247#define EXCPT_PF 2
248
249static int exception_class(int vector)
250{
251 switch (vector) {
252 case PF_VECTOR:
253 return EXCPT_PF;
254 case DE_VECTOR:
255 case TS_VECTOR:
256 case NP_VECTOR:
257 case SS_VECTOR:
258 case GP_VECTOR:
259 return EXCPT_CONTRIBUTORY;
260 default:
261 break;
262 }
263 return EXCPT_BENIGN;
264}
265
266static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
267 unsigned nr, bool has_error, u32 error_code)
268{
269 u32 prev_nr;
270 int class1, class2;
271
272 if (!vcpu->arch.exception.pending) {
273 queue:
274 vcpu->arch.exception.pending = true;
275 vcpu->arch.exception.has_error_code = has_error;
276 vcpu->arch.exception.nr = nr;
277 vcpu->arch.exception.error_code = error_code;
278 return;
279 }
280
281 /* to check exception */
282 prev_nr = vcpu->arch.exception.nr;
283 if (prev_nr == DF_VECTOR) {
284 /* triple fault -> shutdown */
285 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
286 return;
287 }
288 class1 = exception_class(prev_nr);
289 class2 = exception_class(nr);
290 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
291 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
292 /* generate double fault per SDM Table 5-5 */
293 vcpu->arch.exception.pending = true;
294 vcpu->arch.exception.has_error_code = true;
295 vcpu->arch.exception.nr = DF_VECTOR;
296 vcpu->arch.exception.error_code = 0;
297 } else
298 /* replace previous exception with a new one in a hope
299 that instruction re-execution will regenerate lost
300 exception */
301 goto queue;
302}
303
298101da
AK		 304void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
305{
3fd28fce 306 kvm_multiple_exception(vcpu, nr, false, 0);
298101da
AK		 307}
308EXPORT_SYMBOL_GPL(kvm_queue_exception);
309
c3c91fee
AK		 310void kvm_inject_page_fault(struct kvm_vcpu *vcpu, unsigned long addr,
311 u32 error_code)
312{
313 ++vcpu->stat.pf_guest;
ad312c7c 314 vcpu->arch.cr2 = addr;
c3c91fee
AK		 315 kvm_queue_exception_e(vcpu, PF_VECTOR, error_code);
316}
317
3419ffc8
SY		 318void kvm_inject_nmi(struct kvm_vcpu *vcpu)
319{
320 vcpu->arch.nmi_pending = 1;
321}
322EXPORT_SYMBOL_GPL(kvm_inject_nmi);
323
298101da
AK		 324void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
325{
3fd28fce 326 kvm_multiple_exception(vcpu, nr, true, error_code);
298101da
AK		 327}
328EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
329
0a79b009
AK		 330/*
331 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
332 * a #GP and return false.
333 */
334bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 335{
0a79b009
AK		 336 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
337 return true;
338 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
339 return false;
298101da 340}
0a79b009 341EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 342
a03490ed
CO		 343/*
344 * Load the pae pdptrs. Return true is they are all valid.
345 */
346int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3)
347{
348 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
349 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
350 int i;
351 int ret;
ad312c7c 352 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
a03490ed 353
a03490ed
CO		 354 ret = kvm_read_guest_page(vcpu->kvm, pdpt_gfn, pdpte,
355 offset * sizeof(u64), sizeof(pdpte));
356 if (ret < 0) {
357 ret = 0;
358 goto out;
359 }
360 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 361 if (is_present_gpte(pdpte[i]) &&
20c466b5 362 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 363 ret = 0;
364 goto out;
365 }
366 }
367 ret = 1;
368
ad312c7c 369 memcpy(vcpu->arch.pdptrs, pdpte, sizeof(vcpu->arch.pdptrs));
6de4f3ad
AK		 370 __set_bit(VCPU_EXREG_PDPTR,
371 (unsigned long *)&vcpu->arch.regs_avail);
372 __set_bit(VCPU_EXREG_PDPTR,
373 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 374out:
a03490ed
CO		 375
376 return ret;
377}
cc4b6871 378EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 379
d835dfec
AK		 380static bool pdptrs_changed(struct kvm_vcpu *vcpu)
381{
ad312c7c 382 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
d835dfec
AK		 383 bool changed = true;
384 int r;
385
386 if (is_long_mode(vcpu) || !is_pae(vcpu))
387 return false;
388
6de4f3ad
AK		 389 if (!test_bit(VCPU_EXREG_PDPTR,
390 (unsigned long *)&vcpu->arch.regs_avail))
391 return true;
392
ad312c7c 393 r = kvm_read_guest(vcpu->kvm, vcpu->arch.cr3 & ~31u, pdpte, sizeof(pdpte));
d835dfec
AK		 394 if (r < 0)
395 goto out;
ad312c7c 396 changed = memcmp(pdpte, vcpu->arch.pdptrs, sizeof(pdpte)) != 0;
d835dfec 397out:
d835dfec
AK		 398
399 return changed;
400}
401
2d3ad1f4 402void kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 403{
f9a48e6a
AK		 404 cr0 |= X86_CR0_ET;
405
ab344828
GN		 406#ifdef CONFIG_X86_64
407 if (cr0 & 0xffffffff00000000UL) {
c1a5d4f9 408 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 409 return;
410 }
ab344828
GN		 411#endif
412
413 cr0 &= ~CR0_RESERVED_BITS;
a03490ed
CO		 414
415 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) {
c1a5d4f9 416 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 417 return;
418 }
419
420 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) {
c1a5d4f9 421 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 422 return;
423 }
424
425 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
426#ifdef CONFIG_X86_64
f6801dff 427 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 428 int cs_db, cs_l;
429
430 if (!is_pae(vcpu)) {
c1a5d4f9 431 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 432 return;
433 }
434 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
435 if (cs_l) {
c1a5d4f9 436 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 437 return;
438
439 }
440 } else
441#endif
ad312c7c 442 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
c1a5d4f9 443 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 444 return;
445 }
446
447 }
448
449 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 450
a03490ed 451 kvm_mmu_reset_context(vcpu);
a03490ed
CO		 452 return;
453}
2d3ad1f4 454EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 455
2d3ad1f4 456void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 457{
4d4ec087 458 kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0ful) | (msw & 0x0f));
a03490ed 459}
2d3ad1f4 460EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 461
2d3ad1f4 462void kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 463{
fc78f519 464 unsigned long old_cr4 = kvm_read_cr4(vcpu);
a2edf57f
AK		 465 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE;
466
a03490ed 467 if (cr4 & CR4_RESERVED_BITS) {
c1a5d4f9 468 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 469 return;
470 }
471
472 if (is_long_mode(vcpu)) {
473 if (!(cr4 & X86_CR4_PAE)) {
c1a5d4f9 474 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 475 return;
476 }
a2edf57f
AK		 477 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
478 && ((cr4 ^ old_cr4) & pdptr_bits)
ad312c7c 479 && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
c1a5d4f9 480 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 481 return;
482 }
483
484 if (cr4 & X86_CR4_VMXE) {
c1a5d4f9 485 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 486 return;
487 }
488 kvm_x86_ops->set_cr4(vcpu, cr4);
ad312c7c 489 vcpu->arch.cr4 = cr4;
5a41accd 490 vcpu->arch.mmu.base_role.cr4_pge = (cr4 & X86_CR4_PGE) && !tdp_enabled;
a03490ed 491 kvm_mmu_reset_context(vcpu);
a03490ed 492}
2d3ad1f4 493EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 494
2d3ad1f4 495void kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 496{
ad312c7c 497 if (cr3 == vcpu->arch.cr3 && !pdptrs_changed(vcpu)) {
0ba73cda 498 kvm_mmu_sync_roots(vcpu);
d835dfec
AK		 499 kvm_mmu_flush_tlb(vcpu);
500 return;
501 }
502
a03490ed
CO		 503 if (is_long_mode(vcpu)) {
504 if (cr3 & CR3_L_MODE_RESERVED_BITS) {
c1a5d4f9 505 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 506 return;
507 }
508 } else {
509 if (is_pae(vcpu)) {
510 if (cr3 & CR3_PAE_RESERVED_BITS) {
c1a5d4f9 511 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 512 return;
513 }
514 if (is_paging(vcpu) && !load_pdptrs(vcpu, cr3)) {
c1a5d4f9 515 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 516 return;
517 }
518 }
519 /*
520 * We don't check reserved bits in nonpae mode, because
521 * this isn't enforced, and VMware depends on this.
522 */
523 }
524
a03490ed
CO		 525 /*
526 * Does the new cr3 value map to physical memory? (Note, we
527 * catch an invalid cr3 even in real-mode, because it would
528 * cause trouble later on when we turn on paging anyway.)
529 *
530 * A real CPU would silently accept an invalid cr3 and would
531 * attempt to use it - with largely undefined (and often hard
532 * to debug) behavior on the guest side.
533 */
534 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
c1a5d4f9 535 kvm_inject_gp(vcpu, 0);
a03490ed 536 else {
ad312c7c
ZX		 537 vcpu->arch.cr3 = cr3;
538 vcpu->arch.mmu.new_cr3(vcpu);
a03490ed 539 }
a03490ed 540}
2d3ad1f4 541EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 542
2d3ad1f4 543void kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed
CO		 544{
545 if (cr8 & CR8_RESERVED_BITS) {
c1a5d4f9 546 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 547 return;
548 }
549 if (irqchip_in_kernel(vcpu->kvm))
550 kvm_lapic_set_tpr(vcpu, cr8);
551 else
ad312c7c 552 vcpu->arch.cr8 = cr8;
a03490ed 553}
2d3ad1f4 554EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 555
2d3ad1f4 556unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 557{
558 if (irqchip_in_kernel(vcpu->kvm))
559 return kvm_lapic_get_cr8(vcpu);
560 else
ad312c7c 561 return vcpu->arch.cr8;
a03490ed 562}
2d3ad1f4 563EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 564
d8017474
AG		 565static inline u32 bit(int bitno)
566{
567 return 1 << (bitno & 31);
568}
569
043405e1
CO		 570/*
571 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
572 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
573 *
574 * This list is modified at module load time to reflect the
e3267cbb
GC		 575 * capabilities of the host cpu. This capabilities test skips MSRs that are
576 * kvm-specific. Those are put in the beginning of the list.
043405e1 577 */
e3267cbb 578
10388a07 579#define KVM_SAVE_MSRS_BEGIN 5
043405e1 580static u32 msrs_to_save[] = {
e3267cbb 581 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
55cd8e5a 582 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
10388a07 583 HV_X64_MSR_APIC_ASSIST_PAGE,
043405e1
CO		 584 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
585 MSR_K6_STAR,
586#ifdef CONFIG_X86_64
587 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
588#endif
e3267cbb 589 MSR_IA32_TSC, MSR_IA32_PERF_STATUS, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
043405e1
CO		 590};
591
592static unsigned num_msrs_to_save;
593
594static u32 emulated_msrs[] = {
595 MSR_IA32_MISC_ENABLE,
596};
597
15c4a640
CO		 598static void set_efer(struct kvm_vcpu *vcpu, u64 efer)
599{
f2b4b7dd 600 if (efer & efer_reserved_bits) {
c1a5d4f9 601 kvm_inject_gp(vcpu, 0);
15c4a640
CO		 602 return;
603 }
604
605 if (is_paging(vcpu)
f6801dff 606 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME)) {
c1a5d4f9 607 kvm_inject_gp(vcpu, 0);
15c4a640
CO		 608 return;
609 }
610
1b2fd70c
AG		 611 if (efer & EFER_FFXSR) {
612 struct kvm_cpuid_entry2 *feat;
613
614 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
615 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT))) {
1b2fd70c
AG		 616 kvm_inject_gp(vcpu, 0);
617 return;
618 }
619 }
620
d8017474
AG		 621 if (efer & EFER_SVME) {
622 struct kvm_cpuid_entry2 *feat;
623
624 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
625 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM))) {
d8017474
AG		 626 kvm_inject_gp(vcpu, 0);
627 return;
628 }
629 }
630
15c4a640
CO		 631 kvm_x86_ops->set_efer(vcpu, efer);
632
633 efer &= ~EFER_LMA;
f6801dff 634 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 635
f6801dff 636 vcpu->arch.efer = efer;
9645bb56
AK		 637
638 vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
639 kvm_mmu_reset_context(vcpu);
15c4a640
CO		 640}
641
f2b4b7dd
JR		 642void kvm_enable_efer_bits(u64 mask)
643{
644 efer_reserved_bits &= ~mask;
645}
646EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
647
648
15c4a640
CO		 649/*
650 * Writes msr value into into the appropriate "register".
651 * Returns 0 on success, non-0 otherwise.
652 * Assumes vcpu_load() was already called.
653 */
654int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
655{
656 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
657}
658
313a3dc7
CO		 659/*
660 * Adapt set_msr() to msr_io()'s calling convention
661 */
662static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
663{
664 return kvm_set_msr(vcpu, index, *data);
665}
666
18068523
GOC		 667static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
668{
669 static int version;
50d0a0f9 670 struct pvclock_wall_clock wc;
923de3cf 671 struct timespec boot;
18068523
GOC		 672
673 if (!wall_clock)
674 return;
675
676 version++;
677
18068523
GOC		 678 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
679
50d0a0f9
GH		 680 /*
681 * The guest calculates current wall clock time by adding
682 * system time (updated by kvm_write_guest_time below) to the
683 * wall clock specified here. guest system time equals host
684 * system time for us, thus we must fill in host boot time here.
685 */
923de3cf 686 getboottime(&boot);
50d0a0f9
GH		 687
688 wc.sec = boot.tv_sec;
689 wc.nsec = boot.tv_nsec;
690 wc.version = version;
18068523
GOC		 691
692 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
693
694 version++;
695 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 696}
697
50d0a0f9
GH		 698static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
699{
700 uint32_t quotient, remainder;
701
702 /* Don't try to replace with do_div(), this one calculates
703 * "(dividend << 32) / divisor" */
704 __asm__ ( "divl %4"
705 : "=a" (quotient), "=d" (remainder)
706 : "0" (0), "1" (dividend), "r" (divisor) );
707 return quotient;
708}
709
710static void kvm_set_time_scale(uint32_t tsc_khz, struct pvclock_vcpu_time_info *hv_clock)
711{
712 uint64_t nsecs = 1000000000LL;
713 int32_t shift = 0;
714 uint64_t tps64;
715 uint32_t tps32;
716
717 tps64 = tsc_khz * 1000LL;
718 while (tps64 > nsecs*2) {
719 tps64 >>= 1;
720 shift--;
721 }
722
723 tps32 = (uint32_t)tps64;
724 while (tps32 <= (uint32_t)nsecs) {
725 tps32 <<= 1;
726 shift++;
727 }
728
729 hv_clock->tsc_shift = shift;
730 hv_clock->tsc_to_system_mul = div_frac(nsecs, tps32);
731
732 pr_debug("%s: tsc_khz %u, tsc_shift %d, tsc_mul %u\n",
80a914dc 733 __func__, tsc_khz, hv_clock->tsc_shift,
50d0a0f9
GH		 734 hv_clock->tsc_to_system_mul);
735}
736
c8076604
GH		 737static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
738
18068523
GOC		 739static void kvm_write_guest_time(struct kvm_vcpu *v)
740{
741 struct timespec ts;
742 unsigned long flags;
743 struct kvm_vcpu_arch *vcpu = &v->arch;
744 void *shared_kaddr;
463656c0 745 unsigned long this_tsc_khz;
18068523
GOC		 746
747 if ((!vcpu->time_page))
748 return;
749
463656c0
AK		 750 this_tsc_khz = get_cpu_var(cpu_tsc_khz);
751 if (unlikely(vcpu->hv_clock_tsc_khz != this_tsc_khz)) {
752 kvm_set_time_scale(this_tsc_khz, &vcpu->hv_clock);
753 vcpu->hv_clock_tsc_khz = this_tsc_khz;
50d0a0f9 754 }
463656c0 755 put_cpu_var(cpu_tsc_khz);
50d0a0f9 756
18068523
GOC		 757 /* Keep irq disabled to prevent changes to the clock */
758 local_irq_save(flags);
af24a4e4 759 kvm_get_msr(v, MSR_IA32_TSC, &vcpu->hv_clock.tsc_timestamp);
18068523 760 ktime_get_ts(&ts);
923de3cf 761 monotonic_to_bootbased(&ts);
18068523
GOC		 762 local_irq_restore(flags);
763
764 /* With all the info we got, fill in the values */
765
766 vcpu->hv_clock.system_time = ts.tv_nsec +
afbcf7ab
GC		 767 (NSEC_PER_SEC * (u64)ts.tv_sec) + v->kvm->arch.kvmclock_offset;
768
18068523
GOC		 769 /*
770 * The interface expects us to write an even number signaling that the
771 * update is finished. Since the guest won't see the intermediate
50d0a0f9 772 * state, we just increase by 2 at the end.
18068523 773 */
50d0a0f9 774 vcpu->hv_clock.version += 2;
18068523
GOC		 775
776 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
777
778 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
50d0a0f9 779 sizeof(vcpu->hv_clock));
18068523
GOC		 780
781 kunmap_atomic(shared_kaddr, KM_USER0);
782
783 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
784}
785
c8076604
GH		 786static int kvm_request_guest_time_update(struct kvm_vcpu *v)
787{
788 struct kvm_vcpu_arch *vcpu = &v->arch;
789
790 if (!vcpu->time_page)
791 return 0;
792 set_bit(KVM_REQ_KVMCLOCK_UPDATE, &v->requests);
793 return 1;
794}
795
9ba075a6
AK		 796static bool msr_mtrr_valid(unsigned msr)
797{
798 switch (msr) {
799 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
800 case MSR_MTRRfix64K_00000:
801 case MSR_MTRRfix16K_80000:
802 case MSR_MTRRfix16K_A0000:
803 case MSR_MTRRfix4K_C0000:
804 case MSR_MTRRfix4K_C8000:
805 case MSR_MTRRfix4K_D0000:
806 case MSR_MTRRfix4K_D8000:
807 case MSR_MTRRfix4K_E0000:
808 case MSR_MTRRfix4K_E8000:
809 case MSR_MTRRfix4K_F0000:
810 case MSR_MTRRfix4K_F8000:
811 case MSR_MTRRdefType:
812 case MSR_IA32_CR_PAT:
813 return true;
814 case 0x2f8:
815 return true;
816 }
817 return false;
818}
819
d6289b93
MT		 820static bool valid_pat_type(unsigned t)
821{
822 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
823}
824
825static bool valid_mtrr_type(unsigned t)
826{
827 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
828}
829
830static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
831{
832 int i;
833
834 if (!msr_mtrr_valid(msr))
835 return false;
836
837 if (msr == MSR_IA32_CR_PAT) {
838 for (i = 0; i < 8; i++)
839 if (!valid_pat_type((data >> (i * 8)) & 0xff))
840 return false;
841 return true;
842 } else if (msr == MSR_MTRRdefType) {
843 if (data & ~0xcff)
844 return false;
845 return valid_mtrr_type(data & 0xff);
846 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
847 for (i = 0; i < 8 ; i++)
848 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
849 return false;
850 return true;
851 }
852
853 /* variable MTRRs */
854 return valid_mtrr_type(data & 0xff);
855}
856
9ba075a6
AK		 857static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
858{
0bed3b56
SY		 859 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
860
d6289b93 861 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 862 return 1;
863
0bed3b56
SY		 864 if (msr == MSR_MTRRdefType) {
865 vcpu->arch.mtrr_state.def_type = data;
866 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
867 } else if (msr == MSR_MTRRfix64K_00000)
868 p[0] = data;
869 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
870 p[1 + msr - MSR_MTRRfix16K_80000] = data;
871 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
872 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
873 else if (msr == MSR_IA32_CR_PAT)
874 vcpu->arch.pat = data;
875 else { /* Variable MTRRs */
876 int idx, is_mtrr_mask;
877 u64 *pt;
878
879 idx = (msr - 0x200) / 2;
880 is_mtrr_mask = msr - 0x200 - 2 * idx;
881 if (!is_mtrr_mask)
882 pt =
883 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
884 else
885 pt =
886 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
887 *pt = data;
888 }
889
890 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 891 return 0;
892}
15c4a640 893
890ca9ae 894static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 895{
890ca9ae
HY		 896 u64 mcg_cap = vcpu->arch.mcg_cap;
897 unsigned bank_num = mcg_cap & 0xff;
898
15c4a640 899 switch (msr) {
15c4a640 900 case MSR_IA32_MCG_STATUS:
890ca9ae 901 vcpu->arch.mcg_status = data;
15c4a640 902 break;
c7ac679c 903 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 904 if (!(mcg_cap & MCG_CTL_P))
905 return 1;
906 if (data != 0 && data != ~(u64)0)
907 return -1;
908 vcpu->arch.mcg_ctl = data;
909 break;
910 default:
911 if (msr >= MSR_IA32_MC0_CTL &&
912 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
913 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 914 /* only 0 or all 1s can be written to IA32_MCi_CTL
915 * some Linux kernels though clear bit 10 in bank 4 to
916 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
917 * this to avoid an uncatched #GP in the guest
918 */
890ca9ae 919 if ((offset & 0x3) == 0 &&
114be429 920 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 921 return -1;
922 vcpu->arch.mce_banks[offset] = data;
923 break;
924 }
925 return 1;
926 }
927 return 0;
928}
929
ffde22ac
ES		 930static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
931{
932 struct kvm *kvm = vcpu->kvm;
933 int lm = is_long_mode(vcpu);
934 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
935 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
936 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
937 : kvm->arch.xen_hvm_config.blob_size_32;
938 u32 page_num = data & ~PAGE_MASK;
939 u64 page_addr = data & PAGE_MASK;
940 u8 *page;
941 int r;
942
943 r = -E2BIG;
944 if (page_num >= blob_size)
945 goto out;
946 r = -ENOMEM;
947 page = kzalloc(PAGE_SIZE, GFP_KERNEL);
948 if (!page)
949 goto out;
950 r = -EFAULT;
951 if (copy_from_user(page, blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE))
952 goto out_free;
953 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
954 goto out_free;
955 r = 0;
956out_free:
957 kfree(page);
958out:
959 return r;
960}
961
55cd8e5a
GN		 962static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
963{
964 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
965}
966
967static bool kvm_hv_msr_partition_wide(u32 msr)
968{
969 bool r = false;
970 switch (msr) {
971 case HV_X64_MSR_GUEST_OS_ID:
972 case HV_X64_MSR_HYPERCALL:
973 r = true;
974 break;
975 }
976
977 return r;
978}
979
980static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
981{
982 struct kvm *kvm = vcpu->kvm;
983
984 switch (msr) {
985 case HV_X64_MSR_GUEST_OS_ID:
986 kvm->arch.hv_guest_os_id = data;
987 /* setting guest os id to zero disables hypercall page */
988 if (!kvm->arch.hv_guest_os_id)
989 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
990 break;
991 case HV_X64_MSR_HYPERCALL: {
992 u64 gfn;
993 unsigned long addr;
994 u8 instructions[4];
995
996 /* if guest os id is not set hypercall should remain disabled */
997 if (!kvm->arch.hv_guest_os_id)
998 break;
999 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1000 kvm->arch.hv_hypercall = data;
1001 break;
1002 }
1003 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1004 addr = gfn_to_hva(kvm, gfn);
1005 if (kvm_is_error_hva(addr))
1006 return 1;
1007 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1008 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
1009 if (copy_to_user((void __user *)addr, instructions, 4))
1010 return 1;
1011 kvm->arch.hv_hypercall = data;
1012 break;
1013 }
1014 default:
1015 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1016 "data 0x%llx\n", msr, data);
1017 return 1;
1018 }
1019 return 0;
1020}
1021
1022static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1023{
10388a07
GN		 1024 switch (msr) {
1025 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1026 unsigned long addr;
55cd8e5a 1027
10388a07
GN		 1028 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1029 vcpu->arch.hv_vapic = data;
1030 break;
1031 }
1032 addr = gfn_to_hva(vcpu->kvm, data >>
1033 HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1034 if (kvm_is_error_hva(addr))
1035 return 1;
1036 if (clear_user((void __user *)addr, PAGE_SIZE))
1037 return 1;
1038 vcpu->arch.hv_vapic = data;
1039 break;
1040 }
1041 case HV_X64_MSR_EOI:
1042 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1043 case HV_X64_MSR_ICR:
1044 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1045 case HV_X64_MSR_TPR:
1046 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1047 default:
1048 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1049 "data 0x%llx\n", msr, data);
1050 return 1;
1051 }
1052
1053 return 0;
55cd8e5a
GN		 1054}
1055
15c4a640
CO		 1056int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1057{
1058 switch (msr) {
15c4a640
CO		 1059 case MSR_EFER:
1060 set_efer(vcpu, data);
1061 break;
8f1589d9
AP		 1062 case MSR_K7_HWCR:
1063 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 1064 data &= ~(u64)0x100; /* ignore ignne emulation enable */
8f1589d9
AP		 1065 if (data != 0) {
1066 pr_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1067 data);
1068 return 1;
1069 }
15c4a640 1070 break;
f7c6d140
AP		 1071 case MSR_FAM10H_MMIO_CONF_BASE:
1072 if (data != 0) {
1073 pr_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1074 "0x%llx\n", data);
1075 return 1;
1076 }
15c4a640 1077 break;
c323c0e5 1078 case MSR_AMD64_NB_CFG:
c7ac679c 1079 break;
b5e2fec0
AG		 1080 case MSR_IA32_DEBUGCTLMSR:
1081 if (!data) {
1082 /* We support the non-activated case already */
1083 break;
1084 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1085 /* Values other than LBR and BTF are vendor-specific,
1086 thus reserved and should throw a #GP */
1087 return 1;
1088 }
1089 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1090 __func__, data);
1091 break;
15c4a640
CO		 1092 case MSR_IA32_UCODE_REV:
1093 case MSR_IA32_UCODE_WRITE:
61a6bd67 1094 case MSR_VM_HSAVE_PA:
6098ca93 1095 case MSR_AMD64_PATCH_LOADER:
15c4a640 1096 break;
9ba075a6
AK		 1097 case 0x200 ... 0x2ff:
1098 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 1099 case MSR_IA32_APICBASE:
1100 kvm_set_apic_base(vcpu, data);
1101 break;
0105d1a5
GN		 1102 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1103 return kvm_x2apic_msr_write(vcpu, msr, data);
15c4a640 1104 case MSR_IA32_MISC_ENABLE:
ad312c7c 1105 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 1106 break;
18068523
GOC		 1107 case MSR_KVM_WALL_CLOCK:
1108 vcpu->kvm->arch.wall_clock = data;
1109 kvm_write_wall_clock(vcpu->kvm, data);
1110 break;
1111 case MSR_KVM_SYSTEM_TIME: {
1112 if (vcpu->arch.time_page) {
1113 kvm_release_page_dirty(vcpu->arch.time_page);
1114 vcpu->arch.time_page = NULL;
1115 }
1116
1117 vcpu->arch.time = data;
1118
1119 /* we verify if the enable bit is set... */
1120 if (!(data & 1))
1121 break;
1122
1123 /* ...but clean it before doing the actual write */
1124 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
1125
18068523
GOC		 1126 vcpu->arch.time_page =
1127 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
18068523
GOC		 1128
1129 if (is_error_page(vcpu->arch.time_page)) {
1130 kvm_release_page_clean(vcpu->arch.time_page);
1131 vcpu->arch.time_page = NULL;
1132 }
1133
c8076604 1134 kvm_request_guest_time_update(vcpu);
18068523
GOC		 1135 break;
1136 }
890ca9ae
HY		 1137 case MSR_IA32_MCG_CTL:
1138 case MSR_IA32_MCG_STATUS:
1139 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1140 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 1141
1142 /* Performance counters are not protected by a CPUID bit,
1143 * so we should check all of them in the generic path for the sake of
1144 * cross vendor migration.
1145 * Writing a zero into the event select MSRs disables them,
1146 * which we perfectly emulate ;-). Any other value should be at least
1147 * reported, some guests depend on them.
1148 */
1149 case MSR_P6_EVNTSEL0:
1150 case MSR_P6_EVNTSEL1:
1151 case MSR_K7_EVNTSEL0:
1152 case MSR_K7_EVNTSEL1:
1153 case MSR_K7_EVNTSEL2:
1154 case MSR_K7_EVNTSEL3:
1155 if (data != 0)
1156 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1157 "0x%x data 0x%llx\n", msr, data);
1158 break;
1159 /* at least RHEL 4 unconditionally writes to the perfctr registers,
1160 * so we ignore writes to make it happy.
1161 */
1162 case MSR_P6_PERFCTR0:
1163 case MSR_P6_PERFCTR1:
1164 case MSR_K7_PERFCTR0:
1165 case MSR_K7_PERFCTR1:
1166 case MSR_K7_PERFCTR2:
1167 case MSR_K7_PERFCTR3:
1168 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1169 "0x%x data 0x%llx\n", msr, data);
1170 break;
55cd8e5a
GN		 1171 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1172 if (kvm_hv_msr_partition_wide(msr)) {
1173 int r;
1174 mutex_lock(&vcpu->kvm->lock);
1175 r = set_msr_hyperv_pw(vcpu, msr, data);
1176 mutex_unlock(&vcpu->kvm->lock);
1177 return r;
1178 } else
1179 return set_msr_hyperv(vcpu, msr, data);
1180 break;
15c4a640 1181 default:
ffde22ac
ES		 1182 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
1183 return xen_hvm_config(vcpu, data);
ed85c068
AP		 1184 if (!ignore_msrs) {
1185 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
1186 msr, data);
1187 return 1;
1188 } else {
1189 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
1190 msr, data);
1191 break;
1192 }
15c4a640
CO		 1193 }
1194 return 0;
1195}
1196EXPORT_SYMBOL_GPL(kvm_set_msr_common);
1197
1198
1199/*
1200 * Reads an msr value (of 'msr_index') into 'pdata'.
1201 * Returns 0 on success, non-0 otherwise.
1202 * Assumes vcpu_load() was already called.
1203 */
1204int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1205{
1206 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
1207}
1208
9ba075a6
AK		 1209static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1210{
0bed3b56
SY		 1211 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1212
9ba075a6
AK		 1213 if (!msr_mtrr_valid(msr))
1214 return 1;
1215
0bed3b56
SY		 1216 if (msr == MSR_MTRRdefType)
1217 *pdata = vcpu->arch.mtrr_state.def_type +
1218 (vcpu->arch.mtrr_state.enabled << 10);
1219 else if (msr == MSR_MTRRfix64K_00000)
1220 *pdata = p[0];
1221 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1222 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
1223 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1224 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
1225 else if (msr == MSR_IA32_CR_PAT)
1226 *pdata = vcpu->arch.pat;
1227 else { /* Variable MTRRs */
1228 int idx, is_mtrr_mask;
1229 u64 *pt;
1230
1231 idx = (msr - 0x200) / 2;
1232 is_mtrr_mask = msr - 0x200 - 2 * idx;
1233 if (!is_mtrr_mask)
1234 pt =
1235 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1236 else
1237 pt =
1238 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1239 *pdata = *pt;
1240 }
1241
9ba075a6
AK		 1242 return 0;
1243}
1244
890ca9ae 1245static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 1246{
1247 u64 data;
890ca9ae
HY		 1248 u64 mcg_cap = vcpu->arch.mcg_cap;
1249 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 1250
1251 switch (msr) {
15c4a640
CO		 1252 case MSR_IA32_P5_MC_ADDR:
1253 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 1254 data = 0;
1255 break;
15c4a640 1256 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 1257 data = vcpu->arch.mcg_cap;
1258 break;
c7ac679c 1259 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1260 if (!(mcg_cap & MCG_CTL_P))
1261 return 1;
1262 data = vcpu->arch.mcg_ctl;
1263 break;
1264 case MSR_IA32_MCG_STATUS:
1265 data = vcpu->arch.mcg_status;
1266 break;
1267 default:
1268 if (msr >= MSR_IA32_MC0_CTL &&
1269 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1270 u32 offset = msr - MSR_IA32_MC0_CTL;
1271 data = vcpu->arch.mce_banks[offset];
1272 break;
1273 }
1274 return 1;
1275 }
1276 *pdata = data;
1277 return 0;
1278}
1279
55cd8e5a
GN		 1280static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1281{
1282 u64 data = 0;
1283 struct kvm *kvm = vcpu->kvm;
1284
1285 switch (msr) {
1286 case HV_X64_MSR_GUEST_OS_ID:
1287 data = kvm->arch.hv_guest_os_id;
1288 break;
1289 case HV_X64_MSR_HYPERCALL:
1290 data = kvm->arch.hv_hypercall;
1291 break;
1292 default:
1293 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1294 return 1;
1295 }
1296
1297 *pdata = data;
1298 return 0;
1299}
1300
1301static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1302{
1303 u64 data = 0;
1304
1305 switch (msr) {
1306 case HV_X64_MSR_VP_INDEX: {
1307 int r;
1308 struct kvm_vcpu *v;
1309 kvm_for_each_vcpu(r, v, vcpu->kvm)
1310 if (v == vcpu)
1311 data = r;
1312 break;
1313 }
10388a07
GN		 1314 case HV_X64_MSR_EOI:
1315 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
1316 case HV_X64_MSR_ICR:
1317 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
1318 case HV_X64_MSR_TPR:
1319 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
55cd8e5a
GN		 1320 default:
1321 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1322 return 1;
1323 }
1324 *pdata = data;
1325 return 0;
1326}
1327
890ca9ae
HY		 1328int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1329{
1330 u64 data;
1331
1332 switch (msr) {
890ca9ae 1333 case MSR_IA32_PLATFORM_ID:
15c4a640 1334 case MSR_IA32_UCODE_REV:
15c4a640 1335 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 1336 case MSR_IA32_DEBUGCTLMSR:
1337 case MSR_IA32_LASTBRANCHFROMIP:
1338 case MSR_IA32_LASTBRANCHTOIP:
1339 case MSR_IA32_LASTINTFROMIP:
1340 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 1341 case MSR_K8_SYSCFG:
1342 case MSR_K7_HWCR:
61a6bd67 1343 case MSR_VM_HSAVE_PA:
1f3ee616
AS		 1344 case MSR_P6_PERFCTR0:
1345 case MSR_P6_PERFCTR1:
7fe29e0f
AS		 1346 case MSR_P6_EVNTSEL0:
1347 case MSR_P6_EVNTSEL1:
9e699624 1348 case MSR_K7_EVNTSEL0:
1f3ee616 1349 case MSR_K7_PERFCTR0:
1fdbd48c 1350 case MSR_K8_INT_PENDING_MSG:
c323c0e5 1351 case MSR_AMD64_NB_CFG:
f7c6d140 1352 case MSR_FAM10H_MMIO_CONF_BASE:
15c4a640
CO		 1353 data = 0;
1354 break;
9ba075a6
AK		 1355 case MSR_MTRRcap:
1356 data = 0x500 | KVM_NR_VAR_MTRR;
1357 break;
1358 case 0x200 ... 0x2ff:
1359 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 1360 case 0xcd: /* fsb frequency */
1361 data = 3;
1362 break;
1363 case MSR_IA32_APICBASE:
1364 data = kvm_get_apic_base(vcpu);
1365 break;
0105d1a5
GN		 1366 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1367 return kvm_x2apic_msr_read(vcpu, msr, pdata);
1368 break;
15c4a640 1369 case MSR_IA32_MISC_ENABLE:
ad312c7c 1370 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 1371 break;
847f0ad8
AG		 1372 case MSR_IA32_PERF_STATUS:
1373 /* TSC increment by tick */
1374 data = 1000ULL;
1375 /* CPU multiplier */
1376 data |= (((uint64_t)4ULL) << 40);
1377 break;
15c4a640 1378 case MSR_EFER:
f6801dff 1379 data = vcpu->arch.efer;
15c4a640 1380 break;
18068523
GOC		 1381 case MSR_KVM_WALL_CLOCK:
1382 data = vcpu->kvm->arch.wall_clock;
1383 break;
1384 case MSR_KVM_SYSTEM_TIME:
1385 data = vcpu->arch.time;
1386 break;
890ca9ae
HY		 1387 case MSR_IA32_P5_MC_ADDR:
1388 case MSR_IA32_P5_MC_TYPE:
1389 case MSR_IA32_MCG_CAP:
1390 case MSR_IA32_MCG_CTL:
1391 case MSR_IA32_MCG_STATUS:
1392 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1393 return get_msr_mce(vcpu, msr, pdata);
55cd8e5a
GN		 1394 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1395 if (kvm_hv_msr_partition_wide(msr)) {
1396 int r;
1397 mutex_lock(&vcpu->kvm->lock);
1398 r = get_msr_hyperv_pw(vcpu, msr, pdata);
1399 mutex_unlock(&vcpu->kvm->lock);
1400 return r;
1401 } else
1402 return get_msr_hyperv(vcpu, msr, pdata);
1403 break;
15c4a640 1404 default:
ed85c068
AP		 1405 if (!ignore_msrs) {
1406 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
1407 return 1;
1408 } else {
1409 pr_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
1410 data = 0;
1411 }
1412 break;
15c4a640
CO		 1413 }
1414 *pdata = data;
1415 return 0;
1416}
1417EXPORT_SYMBOL_GPL(kvm_get_msr_common);
1418
313a3dc7
CO		 1419/*
1420 * Read or write a bunch of msrs. All parameters are kernel addresses.
1421 *
1422 * @return number of msrs set successfully.
1423 */
1424static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
1425 struct kvm_msr_entry *entries,
1426 int (*do_msr)(struct kvm_vcpu *vcpu,
1427 unsigned index, u64 *data))
1428{
f656ce01 1429 int i, idx;
313a3dc7
CO		 1430
1431 vcpu_load(vcpu);
1432
f656ce01 1433 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 1434 for (i = 0; i < msrs->nmsrs; ++i)
1435 if (do_msr(vcpu, entries[i].index, &entries[i].data))
1436 break;
f656ce01 1437 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7
CO		 1438
1439 vcpu_put(vcpu);
1440
1441 return i;
1442}
1443
1444/*
1445 * Read or write a bunch of msrs. Parameters are user addresses.
1446 *
1447 * @return number of msrs set successfully.
1448 */
1449static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
1450 int (*do_msr)(struct kvm_vcpu *vcpu,
1451 unsigned index, u64 *data),
1452 int writeback)
1453{
1454 struct kvm_msrs msrs;
1455 struct kvm_msr_entry *entries;
1456 int r, n;
1457 unsigned size;
1458
1459 r = -EFAULT;
1460 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
1461 goto out;
1462
1463 r = -E2BIG;
1464 if (msrs.nmsrs >= MAX_IO_MSRS)
1465 goto out;
1466
1467 r = -ENOMEM;
1468 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
1469 entries = vmalloc(size);
1470 if (!entries)
1471 goto out;
1472
1473 r = -EFAULT;
1474 if (copy_from_user(entries, user_msrs->entries, size))
1475 goto out_free;
1476
1477 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
1478 if (r < 0)
1479 goto out_free;
1480
1481 r = -EFAULT;
1482 if (writeback && copy_to_user(user_msrs->entries, entries, size))
1483 goto out_free;
1484
1485 r = n;
1486
1487out_free:
1488 vfree(entries);
1489out:
1490 return r;
1491}
1492
018d00d2
ZX		 1493int kvm_dev_ioctl_check_extension(long ext)
1494{
1495 int r;
1496
1497 switch (ext) {
1498 case KVM_CAP_IRQCHIP:
1499 case KVM_CAP_HLT:
1500 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 1501 case KVM_CAP_SET_TSS_ADDR:
07716717 1502 case KVM_CAP_EXT_CPUID:
c8076604 1503 case KVM_CAP_CLOCKSOURCE:
7837699f 1504 case KVM_CAP_PIT:
a28e4f5a 1505 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 1506 case KVM_CAP_MP_STATE:
ed848624 1507 case KVM_CAP_SYNC_MMU:
52d939a0 1508 case KVM_CAP_REINJECT_CONTROL:
4925663a 1509 case KVM_CAP_IRQ_INJECT_STATUS:
e56d532f 1510 case KVM_CAP_ASSIGN_DEV_IRQ:
721eecbf 1511 case KVM_CAP_IRQFD:
d34e6b17 1512 case KVM_CAP_IOEVENTFD:
c5ff41ce 1513 case KVM_CAP_PIT2:
e9f42757 1514 case KVM_CAP_PIT_STATE2:
b927a3ce 1515 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 1516 case KVM_CAP_XEN_HVM:
afbcf7ab 1517 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 1518 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 1519 case KVM_CAP_HYPERV:
10388a07 1520 case KVM_CAP_HYPERV_VAPIC:
c25bc163 1521 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 1522 case KVM_CAP_PCI_SEGMENT:
a1efbe77 1523 case KVM_CAP_DEBUGREGS:
d2be1651 1524 case KVM_CAP_X86_ROBUST_SINGLESTEP:
018d00d2
ZX		 1525 r = 1;
1526 break;
542472b5
LV		 1527 case KVM_CAP_COALESCED_MMIO:
1528 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
1529 break;
774ead3a
AK		 1530 case KVM_CAP_VAPIC:
1531 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
1532 break;
f725230a
AK		 1533 case KVM_CAP_NR_VCPUS:
1534 r = KVM_MAX_VCPUS;
1535 break;
a988b910
AK		 1536 case KVM_CAP_NR_MEMSLOTS:
1537 r = KVM_MEMORY_SLOTS;
1538 break;
a68a6a72
MT		 1539 case KVM_CAP_PV_MMU: /* obsolete */
1540 r = 0;
2f333bcb 1541 break;
62c476c7 1542 case KVM_CAP_IOMMU:
19de40a8 1543 r = iommu_found();
62c476c7 1544 break;
890ca9ae
HY		 1545 case KVM_CAP_MCE:
1546 r = KVM_MAX_MCE_BANKS;
1547 break;
018d00d2
ZX		 1548 default:
1549 r = 0;
1550 break;
1551 }
1552 return r;
1553
1554}
1555
043405e1
CO		 1556long kvm_arch_dev_ioctl(struct file *filp,
1557 unsigned int ioctl, unsigned long arg)
1558{
1559 void __user *argp = (void __user *)arg;
1560 long r;
1561
1562 switch (ioctl) {
1563 case KVM_GET_MSR_INDEX_LIST: {
1564 struct kvm_msr_list __user *user_msr_list = argp;
1565 struct kvm_msr_list msr_list;
1566 unsigned n;
1567
1568 r = -EFAULT;
1569 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
1570 goto out;
1571 n = msr_list.nmsrs;
1572 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
1573 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
1574 goto out;
1575 r = -E2BIG;
e125e7b6 1576 if (n < msr_list.nmsrs)
043405e1
CO		 1577 goto out;
1578 r = -EFAULT;
1579 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
1580 num_msrs_to_save * sizeof(u32)))
1581 goto out;
e125e7b6 1582 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 1583 &emulated_msrs,
1584 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
1585 goto out;
1586 r = 0;
1587 break;
1588 }
674eea0f
AK		 1589 case KVM_GET_SUPPORTED_CPUID: {
1590 struct kvm_cpuid2 __user *cpuid_arg = argp;
1591 struct kvm_cpuid2 cpuid;
1592
1593 r = -EFAULT;
1594 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1595 goto out;
1596 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
19355475 1597 cpuid_arg->entries);
674eea0f
AK		 1598 if (r)
1599 goto out;
1600
1601 r = -EFAULT;
1602 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
1603 goto out;
1604 r = 0;
1605 break;
1606 }
890ca9ae
HY		 1607 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
1608 u64 mce_cap;
1609
1610 mce_cap = KVM_MCE_CAP_SUPPORTED;
1611 r = -EFAULT;
1612 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
1613 goto out;
1614 r = 0;
1615 break;
1616 }
043405e1
CO		 1617 default:
1618 r = -EINVAL;
1619 }
1620out:
1621 return r;
1622}
1623
313a3dc7
CO		 1624void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1625{
1626 kvm_x86_ops->vcpu_load(vcpu, cpu);
6b7d7e76
ZA		 1627 if (unlikely(per_cpu(cpu_tsc_khz, cpu) == 0)) {
1628 unsigned long khz = cpufreq_quick_get(cpu);
1629 if (!khz)
1630 khz = tsc_khz;
1631 per_cpu(cpu_tsc_khz, cpu) = khz;
1632 }
c8076604 1633 kvm_request_guest_time_update(vcpu);
313a3dc7
CO		 1634}
1635
1636void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
1637{
9327fd11 1638 kvm_put_guest_fpu(vcpu);
02daab21 1639 kvm_x86_ops->vcpu_put(vcpu);
313a3dc7
CO		 1640}
1641
07716717 1642static int is_efer_nx(void)
313a3dc7 1643{
e286e86e 1644 unsigned long long efer = 0;
313a3dc7 1645
e286e86e 1646 rdmsrl_safe(MSR_EFER, &efer);
07716717
DK		 1647 return efer & EFER_NX;
1648}
1649
1650static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
1651{
1652 int i;
1653 struct kvm_cpuid_entry2 *e, *entry;
1654
313a3dc7 1655 entry = NULL;
ad312c7c
ZX		 1656 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
1657 e = &vcpu->arch.cpuid_entries[i];
313a3dc7
CO		 1658 if (e->function == 0x80000001) {
1659 entry = e;
1660 break;
1661 }
1662 }
07716717 1663 if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) {
313a3dc7
CO		 1664 entry->edx &= ~(1 << 20);
1665 printk(KERN_INFO "kvm: guest NX capability removed\n");
1666 }
1667}
1668
07716717 1669/* when an old userspace process fills a new kernel module */
313a3dc7
CO		 1670static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
1671 struct kvm_cpuid *cpuid,
1672 struct kvm_cpuid_entry __user *entries)
07716717
DK		 1673{
1674 int r, i;
1675 struct kvm_cpuid_entry *cpuid_entries;
1676
1677 r = -E2BIG;
1678 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1679 goto out;
1680 r = -ENOMEM;
1681 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent);
1682 if (!cpuid_entries)
1683 goto out;
1684 r = -EFAULT;
1685 if (copy_from_user(cpuid_entries, entries,
1686 cpuid->nent * sizeof(struct kvm_cpuid_entry)))
1687 goto out_free;
1688 for (i = 0; i < cpuid->nent; i++) {
ad312c7c
ZX		 1689 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
1690 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
1691 vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx;
1692 vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx;
1693 vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx;
1694 vcpu->arch.cpuid_entries[i].index = 0;
1695 vcpu->arch.cpuid_entries[i].flags = 0;
1696 vcpu->arch.cpuid_entries[i].padding[0] = 0;
1697 vcpu->arch.cpuid_entries[i].padding[1] = 0;
1698 vcpu->arch.cpuid_entries[i].padding[2] = 0;
1699 }
1700 vcpu->arch.cpuid_nent = cpuid->nent;
07716717
DK		 1701 cpuid_fix_nx_cap(vcpu);
1702 r = 0;
fc61b800 1703 kvm_apic_set_version(vcpu);
0e851880 1704 kvm_x86_ops->cpuid_update(vcpu);
07716717
DK		 1705
1706out_free:
1707 vfree(cpuid_entries);
1708out:
1709 return r;
1710}
1711
1712static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 1713 struct kvm_cpuid2 *cpuid,
1714 struct kvm_cpuid_entry2 __user *entries)
313a3dc7
CO		 1715{
1716 int r;
1717
1718 r = -E2BIG;
1719 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1720 goto out;
1721 r = -EFAULT;
ad312c7c 1722 if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
07716717 1723 cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
313a3dc7 1724 goto out;
ad312c7c 1725 vcpu->arch.cpuid_nent = cpuid->nent;
fc61b800 1726 kvm_apic_set_version(vcpu);
0e851880 1727 kvm_x86_ops->cpuid_update(vcpu);
313a3dc7
CO		 1728 return 0;
1729
1730out:
1731 return r;
1732}
1733
07716717 1734static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 1735 struct kvm_cpuid2 *cpuid,
1736 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 1737{
1738 int r;
1739
1740 r = -E2BIG;
ad312c7c 1741 if (cpuid->nent < vcpu->arch.cpuid_nent)
07716717
DK		 1742 goto out;
1743 r = -EFAULT;
ad312c7c 1744 if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
19355475 1745 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 1746 goto out;
1747 return 0;
1748
1749out:
ad312c7c 1750 cpuid->nent = vcpu->arch.cpuid_nent;
07716717
DK		 1751 return r;
1752}
1753
07716717 1754static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function,
19355475 1755 u32 index)
07716717
DK		 1756{
1757 entry->function = function;
1758 entry->index = index;
1759 cpuid_count(entry->function, entry->index,
19355475 1760 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
07716717
DK		 1761 entry->flags = 0;
1762}
1763
7faa4ee1
AK		 1764#define F(x) bit(X86_FEATURE_##x)
1765
07716717
DK		 1766static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
1767 u32 index, int *nent, int maxnent)
1768{
7faa4ee1 1769 unsigned f_nx = is_efer_nx() ? F(NX) : 0;
07716717 1770#ifdef CONFIG_X86_64
17cc3935
SY		 1771 unsigned f_gbpages = (kvm_x86_ops->get_lpage_level() == PT_PDPE_LEVEL)
1772 ? F(GBPAGES) : 0;
7faa4ee1
AK		 1773 unsigned f_lm = F(LM);
1774#else
17cc3935 1775 unsigned f_gbpages = 0;
7faa4ee1 1776 unsigned f_lm = 0;
07716717 1777#endif
4e47c7a6 1778 unsigned f_rdtscp = kvm_x86_ops->rdtscp_supported() ? F(RDTSCP) : 0;
7faa4ee1
AK		 1779
1780 /* cpuid 1.edx */
1781 const u32 kvm_supported_word0_x86_features =
1782 F(FPU) | F(VME) | F(DE) | F(PSE) |
1783 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
1784 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) |
1785 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
1786 F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLSH) |
1787 0 /* Reserved, DS, ACPI */ | F(MMX) |
1788 F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) |
1789 0 /* HTT, TM, Reserved, PBE */;
1790 /* cpuid 0x80000001.edx */
1791 const u32 kvm_supported_word1_x86_features =
1792 F(FPU) | F(VME) | F(DE) | F(PSE) |
1793 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
1794 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) |
1795 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
1796 F(PAT) | F(PSE36) | 0 /* Reserved */ |
1797 f_nx | 0 /* Reserved */ | F(MMXEXT) | F(MMX) |
4e47c7a6 1798 F(FXSR) | F(FXSR_OPT) | f_gbpages | f_rdtscp |
7faa4ee1
AK		 1799 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW);
1800 /* cpuid 1.ecx */
1801 const u32 kvm_supported_word4_x86_features =
d149c731
AK		 1802 F(XMM3) | 0 /* Reserved, DTES64, MONITOR */ |
1803 0 /* DS-CPL, VMX, SMX, EST */ |
1804 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ |
1805 0 /* Reserved */ | F(CX16) | 0 /* xTPR Update, PDCM */ |
1806 0 /* Reserved, DCA */ | F(XMM4_1) |
0105d1a5 1807 F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) |
d149c731 1808 0 /* Reserved, XSAVE, OSXSAVE */;
7faa4ee1 1809 /* cpuid 0x80000001.ecx */
07716717 1810 const u32 kvm_supported_word6_x86_features =
7faa4ee1
AK		 1811 F(LAHF_LM) | F(CMP_LEGACY) | F(SVM) | 0 /* ExtApicSpace */ |
1812 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) |
1813 F(3DNOWPREFETCH) | 0 /* OSVW */ | 0 /* IBS */ | F(SSE5) |
1814 0 /* SKINIT */ | 0 /* WDT */;
07716717 1815
19355475 1816 /* all calls to cpuid_count() should be made on the same cpu */
07716717
DK		 1817 get_cpu();
1818 do_cpuid_1_ent(entry, function, index);
1819 ++*nent;
1820
1821 switch (function) {
1822 case 0:
1823 entry->eax = min(entry->eax, (u32)0xb);
1824 break;
1825 case 1:
1826 entry->edx &= kvm_supported_word0_x86_features;
7faa4ee1 1827 entry->ecx &= kvm_supported_word4_x86_features;
0d1de2d9
GN		 1828 /* we support x2apic emulation even if host does not support
1829 * it since we emulate x2apic in software */
1830 entry->ecx |= F(X2APIC);
07716717
DK		 1831 break;
1832 /* function 2 entries are STATEFUL. That is, repeated cpuid commands
1833 * may return different values. This forces us to get_cpu() before
1834 * issuing the first command, and also to emulate this annoying behavior
1835 * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */
1836 case 2: {
1837 int t, times = entry->eax & 0xff;
1838
1839 entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
0fdf8e59 1840 entry->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
07716717
DK		 1841 for (t = 1; t < times && *nent < maxnent; ++t) {
1842 do_cpuid_1_ent(&entry[t], function, 0);
1843 entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
1844 ++*nent;
1845 }
1846 break;
1847 }
1848 /* function 4 and 0xb have additional index. */
1849 case 4: {
14af3f3c 1850 int i, cache_type;
07716717
DK		 1851
1852 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1853 /* read more entries until cache_type is zero */
14af3f3c
HH		 1854 for (i = 1; *nent < maxnent; ++i) {
1855 cache_type = entry[i - 1].eax & 0x1f;
07716717
DK		 1856 if (!cache_type)
1857 break;
14af3f3c
HH		 1858 do_cpuid_1_ent(&entry[i], function, i);
1859 entry[i].flags |=
07716717
DK		 1860 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1861 ++*nent;
1862 }
1863 break;
1864 }
1865 case 0xb: {
14af3f3c 1866 int i, level_type;
07716717
DK		 1867
1868 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1869 /* read more entries until level_type is zero */
14af3f3c 1870 for (i = 1; *nent < maxnent; ++i) {
0853d2c1 1871 level_type = entry[i - 1].ecx & 0xff00;
07716717
DK		 1872 if (!level_type)
1873 break;
14af3f3c
HH		 1874 do_cpuid_1_ent(&entry[i], function, i);
1875 entry[i].flags |=
07716717
DK		 1876 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1877 ++*nent;
1878 }
1879 break;
1880 }
1881 case 0x80000000:
1882 entry->eax = min(entry->eax, 0x8000001a);
1883 break;
1884 case 0x80000001:
1885 entry->edx &= kvm_supported_word1_x86_features;
1886 entry->ecx &= kvm_supported_word6_x86_features;
1887 break;
1888 }
1889 put_cpu();
1890}
1891
7faa4ee1
AK		 1892#undef F
1893
674eea0f 1894static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
19355475 1895 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 1896{
1897 struct kvm_cpuid_entry2 *cpuid_entries;
1898 int limit, nent = 0, r = -E2BIG;
1899 u32 func;
1900
1901 if (cpuid->nent < 1)
1902 goto out;
6a544355
AK		 1903 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1904 cpuid->nent = KVM_MAX_CPUID_ENTRIES;
07716717
DK		 1905 r = -ENOMEM;
1906 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent);
1907 if (!cpuid_entries)
1908 goto out;
1909
1910 do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent);
1911 limit = cpuid_entries[0].eax;
1912 for (func = 1; func <= limit && nent < cpuid->nent; ++func)
1913 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 1914 &nent, cpuid->nent);
07716717
DK		 1915 r = -E2BIG;
1916 if (nent >= cpuid->nent)
1917 goto out_free;
1918
1919 do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent);
1920 limit = cpuid_entries[nent - 1].eax;
1921 for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func)
1922 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 1923 &nent, cpuid->nent);
cb007648
MM		 1924 r = -E2BIG;
1925 if (nent >= cpuid->nent)
1926 goto out_free;
1927
07716717
DK		 1928 r = -EFAULT;
1929 if (copy_to_user(entries, cpuid_entries,
19355475 1930 nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 1931 goto out_free;
1932 cpuid->nent = nent;
1933 r = 0;
1934
1935out_free:
1936 vfree(cpuid_entries);
1937out:
1938 return r;
1939}
1940
313a3dc7
CO		 1941static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
1942 struct kvm_lapic_state *s)
1943{
1944 vcpu_load(vcpu);
ad312c7c 1945 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 1946 vcpu_put(vcpu);
1947
1948 return 0;
1949}
1950
1951static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
1952 struct kvm_lapic_state *s)
1953{
1954 vcpu_load(vcpu);
ad312c7c 1955 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
313a3dc7 1956 kvm_apic_post_state_restore(vcpu);
cb142eb7 1957 update_cr8_intercept(vcpu);
313a3dc7
CO		 1958 vcpu_put(vcpu);
1959
1960 return 0;
1961}
1962
f77bc6a4
ZX		 1963static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
1964 struct kvm_interrupt *irq)
1965{
1966 if (irq->irq < 0 || irq->irq >= 256)
1967 return -EINVAL;
1968 if (irqchip_in_kernel(vcpu->kvm))
1969 return -ENXIO;
1970 vcpu_load(vcpu);
1971
66fd3f7f 1972 kvm_queue_interrupt(vcpu, irq->irq, false);
f77bc6a4
ZX		 1973
1974 vcpu_put(vcpu);
1975
1976 return 0;
1977}
1978
c4abb7c9
JK		 1979static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
1980{
1981 vcpu_load(vcpu);
1982 kvm_inject_nmi(vcpu);
1983 vcpu_put(vcpu);
1984
1985 return 0;
1986}
1987
b209749f
AK		 1988static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
1989 struct kvm_tpr_access_ctl *tac)
1990{
1991 if (tac->flags)
1992 return -EINVAL;
1993 vcpu->arch.tpr_access_reporting = !!tac->enabled;
1994 return 0;
1995}
1996
890ca9ae
HY		 1997static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
1998 u64 mcg_cap)
1999{
2000 int r;
2001 unsigned bank_num = mcg_cap & 0xff, bank;
2002
2003 r = -EINVAL;
a9e38c3e 2004 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2005 goto out;
2006 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2007 goto out;
2008 r = 0;
2009 vcpu->arch.mcg_cap = mcg_cap;
2010 /* Init IA32_MCG_CTL to all 1s */
2011 if (mcg_cap & MCG_CTL_P)
2012 vcpu->arch.mcg_ctl = ~(u64)0;
2013 /* Init IA32_MCi_CTL to all 1s */
2014 for (bank = 0; bank < bank_num; bank++)
2015 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2016out:
2017 return r;
2018}
2019
2020static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2021 struct kvm_x86_mce *mce)
2022{
2023 u64 mcg_cap = vcpu->arch.mcg_cap;
2024 unsigned bank_num = mcg_cap & 0xff;
2025 u64 *banks = vcpu->arch.mce_banks;
2026
2027 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2028 return -EINVAL;
2029 /*
2030 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2031 * reporting is disabled
2032 */
2033 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2034 vcpu->arch.mcg_ctl != ~(u64)0)
2035 return 0;
2036 banks += 4 * mce->bank;
2037 /*
2038 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2039 * reporting is disabled for the bank
2040 */
2041 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2042 return 0;
2043 if (mce->status & MCI_STATUS_UC) {
2044 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2045 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
890ca9ae
HY		 2046 printk(KERN_DEBUG "kvm: set_mce: "
2047 "injects mce exception while "
2048 "previous one is in progress!\n");
2049 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
2050 return 0;
2051 }
2052 if (banks[1] & MCI_STATUS_VAL)
2053 mce->status |= MCI_STATUS_OVER;
2054 banks[2] = mce->addr;
2055 banks[3] = mce->misc;
2056 vcpu->arch.mcg_status = mce->mcg_status;
2057 banks[1] = mce->status;
2058 kvm_queue_exception(vcpu, MC_VECTOR);
2059 } else if (!(banks[1] & MCI_STATUS_VAL)
2060 || !(banks[1] & MCI_STATUS_UC)) {
2061 if (banks[1] & MCI_STATUS_VAL)
2062 mce->status |= MCI_STATUS_OVER;
2063 banks[2] = mce->addr;
2064 banks[3] = mce->misc;
2065 banks[1] = mce->status;
2066 } else
2067 banks[1] |= MCI_STATUS_OVER;
2068 return 0;
2069}
2070
3cfc3092
JK		 2071static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2072 struct kvm_vcpu_events *events)
2073{
2074 vcpu_load(vcpu);
2075
03b82a30
JK		 2076 events->exception.injected =
2077 vcpu->arch.exception.pending &&
2078 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2079 events->exception.nr = vcpu->arch.exception.nr;
2080 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
2081 events->exception.error_code = vcpu->arch.exception.error_code;
2082
03b82a30
JK		 2083 events->interrupt.injected =
2084 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2085 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2086 events->interrupt.soft = 0;
48005f64
JK		 2087 events->interrupt.shadow =
2088 kvm_x86_ops->get_interrupt_shadow(vcpu,
2089 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
3cfc3092
JK		 2090
2091 events->nmi.injected = vcpu->arch.nmi_injected;
2092 events->nmi.pending = vcpu->arch.nmi_pending;
2093 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
2094
2095 events->sipi_vector = vcpu->arch.sipi_vector;
2096
dab4b911 2097 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2098 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2099 | KVM_VCPUEVENT_VALID_SHADOW);
3cfc3092
JK		 2100
2101 vcpu_put(vcpu);
2102}
2103
2104static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2105 struct kvm_vcpu_events *events)
2106{
dab4b911 2107 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2108 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2109 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 2110 return -EINVAL;
2111
2112 vcpu_load(vcpu);
2113
2114 vcpu->arch.exception.pending = events->exception.injected;
2115 vcpu->arch.exception.nr = events->exception.nr;
2116 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2117 vcpu->arch.exception.error_code = events->exception.error_code;
2118
2119 vcpu->arch.interrupt.pending = events->interrupt.injected;
2120 vcpu->arch.interrupt.nr = events->interrupt.nr;
2121 vcpu->arch.interrupt.soft = events->interrupt.soft;
2122 if (vcpu->arch.interrupt.pending && irqchip_in_kernel(vcpu->kvm))
2123 kvm_pic_clear_isr_ack(vcpu->kvm);
48005f64
JK		 2124 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2125 kvm_x86_ops->set_interrupt_shadow(vcpu,
2126 events->interrupt.shadow);
3cfc3092
JK		 2127
2128 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2129 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2130 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2131 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2132
dab4b911
JK		 2133 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR)
2134 vcpu->arch.sipi_vector = events->sipi_vector;
3cfc3092
JK		 2135
2136 vcpu_put(vcpu);
2137
2138 return 0;
2139}
2140
a1efbe77
JK		 2141static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2142 struct kvm_debugregs *dbgregs)
2143{
2144 vcpu_load(vcpu);
2145
2146 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2147 dbgregs->dr6 = vcpu->arch.dr6;
2148 dbgregs->dr7 = vcpu->arch.dr7;
2149 dbgregs->flags = 0;
2150
2151 vcpu_put(vcpu);
2152}
2153
2154static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2155 struct kvm_debugregs *dbgregs)
2156{
2157 if (dbgregs->flags)
2158 return -EINVAL;
2159
2160 vcpu_load(vcpu);
2161
2162 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2163 vcpu->arch.dr6 = dbgregs->dr6;
2164 vcpu->arch.dr7 = dbgregs->dr7;
2165
2166 vcpu_put(vcpu);
2167
2168 return 0;
2169}
2170
313a3dc7
CO		 2171long kvm_arch_vcpu_ioctl(struct file *filp,
2172 unsigned int ioctl, unsigned long arg)
2173{
2174 struct kvm_vcpu *vcpu = filp->private_data;
2175 void __user *argp = (void __user *)arg;
2176 int r;
b772ff36 2177 struct kvm_lapic_state *lapic = NULL;
313a3dc7
CO		 2178
2179 switch (ioctl) {
2180 case KVM_GET_LAPIC: {
2204ae3c
MT		 2181 r = -EINVAL;
2182 if (!vcpu->arch.apic)
2183 goto out;
b772ff36 2184 lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 2185
b772ff36
DH		 2186 r = -ENOMEM;
2187 if (!lapic)
2188 goto out;
2189 r = kvm_vcpu_ioctl_get_lapic(vcpu, lapic);
313a3dc7
CO		 2190 if (r)
2191 goto out;
2192 r = -EFAULT;
b772ff36 2193 if (copy_to_user(argp, lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 2194 goto out;
2195 r = 0;
2196 break;
2197 }
2198 case KVM_SET_LAPIC: {
2204ae3c
MT		 2199 r = -EINVAL;
2200 if (!vcpu->arch.apic)
2201 goto out;
b772ff36
DH		 2202 lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
2203 r = -ENOMEM;
2204 if (!lapic)
2205 goto out;
313a3dc7 2206 r = -EFAULT;
b772ff36 2207 if (copy_from_user(lapic, argp, sizeof(struct kvm_lapic_state)))
313a3dc7 2208 goto out;
b772ff36 2209 r = kvm_vcpu_ioctl_set_lapic(vcpu, lapic);
313a3dc7
CO		 2210 if (r)
2211 goto out;
2212 r = 0;
2213 break;
2214 }
f77bc6a4
ZX		 2215 case KVM_INTERRUPT: {
2216 struct kvm_interrupt irq;
2217
2218 r = -EFAULT;
2219 if (copy_from_user(&irq, argp, sizeof irq))
2220 goto out;
2221 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
2222 if (r)
2223 goto out;
2224 r = 0;
2225 break;
2226 }
c4abb7c9
JK		 2227 case KVM_NMI: {
2228 r = kvm_vcpu_ioctl_nmi(vcpu);
2229 if (r)
2230 goto out;
2231 r = 0;
2232 break;
2233 }
313a3dc7
CO		 2234 case KVM_SET_CPUID: {
2235 struct kvm_cpuid __user *cpuid_arg = argp;
2236 struct kvm_cpuid cpuid;
2237
2238 r = -EFAULT;
2239 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2240 goto out;
2241 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
2242 if (r)
2243 goto out;
2244 break;
2245 }
07716717
DK		 2246 case KVM_SET_CPUID2: {
2247 struct kvm_cpuid2 __user *cpuid_arg = argp;
2248 struct kvm_cpuid2 cpuid;
2249
2250 r = -EFAULT;
2251 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2252 goto out;
2253 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 2254 cpuid_arg->entries);
07716717
DK		 2255 if (r)
2256 goto out;
2257 break;
2258 }
2259 case KVM_GET_CPUID2: {
2260 struct kvm_cpuid2 __user *cpuid_arg = argp;
2261 struct kvm_cpuid2 cpuid;
2262
2263 r = -EFAULT;
2264 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2265 goto out;
2266 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 2267 cpuid_arg->entries);
07716717
DK		 2268 if (r)
2269 goto out;
2270 r = -EFAULT;
2271 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2272 goto out;
2273 r = 0;
2274 break;
2275 }
313a3dc7
CO		 2276 case KVM_GET_MSRS:
2277 r = msr_io(vcpu, argp, kvm_get_msr, 1);
2278 break;
2279 case KVM_SET_MSRS:
2280 r = msr_io(vcpu, argp, do_set_msr, 0);
2281 break;
b209749f
AK		 2282 case KVM_TPR_ACCESS_REPORTING: {
2283 struct kvm_tpr_access_ctl tac;
2284
2285 r = -EFAULT;
2286 if (copy_from_user(&tac, argp, sizeof tac))
2287 goto out;
2288 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
2289 if (r)
2290 goto out;
2291 r = -EFAULT;
2292 if (copy_to_user(argp, &tac, sizeof tac))
2293 goto out;
2294 r = 0;
2295 break;
2296 };
b93463aa
AK		 2297 case KVM_SET_VAPIC_ADDR: {
2298 struct kvm_vapic_addr va;
2299
2300 r = -EINVAL;
2301 if (!irqchip_in_kernel(vcpu->kvm))
2302 goto out;
2303 r = -EFAULT;
2304 if (copy_from_user(&va, argp, sizeof va))
2305 goto out;
2306 r = 0;
2307 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
2308 break;
2309 }
890ca9ae
HY		 2310 case KVM_X86_SETUP_MCE: {
2311 u64 mcg_cap;
2312
2313 r = -EFAULT;
2314 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
2315 goto out;
2316 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
2317 break;
2318 }
2319 case KVM_X86_SET_MCE: {
2320 struct kvm_x86_mce mce;
2321
2322 r = -EFAULT;
2323 if (copy_from_user(&mce, argp, sizeof mce))
2324 goto out;
2325 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
2326 break;
2327 }
3cfc3092
JK		 2328 case KVM_GET_VCPU_EVENTS: {
2329 struct kvm_vcpu_events events;
2330
2331 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
2332
2333 r = -EFAULT;
2334 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
2335 break;
2336 r = 0;
2337 break;
2338 }
2339 case KVM_SET_VCPU_EVENTS: {
2340 struct kvm_vcpu_events events;
2341
2342 r = -EFAULT;
2343 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
2344 break;
2345
2346 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
2347 break;
2348 }
a1efbe77
JK		 2349 case KVM_GET_DEBUGREGS: {
2350 struct kvm_debugregs dbgregs;
2351
2352 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
2353
2354 r = -EFAULT;
2355 if (copy_to_user(argp, &dbgregs,
2356 sizeof(struct kvm_debugregs)))
2357 break;
2358 r = 0;
2359 break;
2360 }
2361 case KVM_SET_DEBUGREGS: {
2362 struct kvm_debugregs dbgregs;
2363
2364 r = -EFAULT;
2365 if (copy_from_user(&dbgregs, argp,
2366 sizeof(struct kvm_debugregs)))
2367 break;
2368
2369 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
2370 break;
2371 }
313a3dc7
CO		 2372 default:
2373 r = -EINVAL;
2374 }
2375out:
7a6ce84c 2376 kfree(lapic);
313a3dc7
CO		 2377 return r;
2378}
2379
1fe779f8
CO		 2380static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
2381{
2382 int ret;
2383
2384 if (addr > (unsigned int)(-3 * PAGE_SIZE))
2385 return -1;
2386 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
2387 return ret;
2388}
2389
b927a3ce
SY		 2390static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
2391 u64 ident_addr)
2392{
2393 kvm->arch.ept_identity_map_addr = ident_addr;
2394 return 0;
2395}
2396
1fe779f8
CO		 2397static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
2398 u32 kvm_nr_mmu_pages)
2399{
2400 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
2401 return -EINVAL;
2402
79fac95e 2403 mutex_lock(&kvm->slots_lock);
7c8a83b7 2404 spin_lock(&kvm->mmu_lock);
1fe779f8
CO		 2405
2406 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 2407 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 2408
7c8a83b7 2409 spin_unlock(&kvm->mmu_lock);
79fac95e 2410 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 2411 return 0;
2412}
2413
2414static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
2415{
f05e70ac 2416 return kvm->arch.n_alloc_mmu_pages;
1fe779f8
CO		 2417}
2418
a983fb23
MT		 2419gfn_t unalias_gfn_instantiation(struct kvm *kvm, gfn_t gfn)
2420{
2421 int i;
2422 struct kvm_mem_alias *alias;
2423 struct kvm_mem_aliases *aliases;
2424
2425 aliases = rcu_dereference(kvm->arch.aliases);
2426
2427 for (i = 0; i < aliases->naliases; ++i) {
2428 alias = &aliases->aliases[i];
2429 if (alias->flags & KVM_ALIAS_INVALID)
2430 continue;
2431 if (gfn >= alias->base_gfn
2432 && gfn < alias->base_gfn + alias->npages)
2433 return alias->target_gfn + gfn - alias->base_gfn;
2434 }
2435 return gfn;
2436}
2437
e9f85cde
ZX		 2438gfn_t unalias_gfn(struct kvm *kvm, gfn_t gfn)
2439{
2440 int i;
2441 struct kvm_mem_alias *alias;
a983fb23
MT		 2442 struct kvm_mem_aliases *aliases;
2443
2444 aliases = rcu_dereference(kvm->arch.aliases);
e9f85cde 2445
fef9cce0
MT		 2446 for (i = 0; i < aliases->naliases; ++i) {
2447 alias = &aliases->aliases[i];
e9f85cde
ZX		 2448 if (gfn >= alias->base_gfn
2449 && gfn < alias->base_gfn + alias->npages)
2450 return alias->target_gfn + gfn - alias->base_gfn;
2451 }
2452 return gfn;
2453}
2454
1fe779f8
CO		 2455/*
2456 * Set a new alias region. Aliases map a portion of physical memory into
2457 * another portion. This is useful for memory windows, for example the PC
2458 * VGA region.
2459 */
2460static int kvm_vm_ioctl_set_memory_alias(struct kvm *kvm,
2461 struct kvm_memory_alias *alias)
2462{
2463 int r, n;
2464 struct kvm_mem_alias *p;
a983fb23 2465 struct kvm_mem_aliases *aliases, *old_aliases;
1fe779f8
CO		 2466
2467 r = -EINVAL;
2468 /* General sanity checks */
2469 if (alias->memory_size & (PAGE_SIZE - 1))
2470 goto out;
2471 if (alias->guest_phys_addr & (PAGE_SIZE - 1))
2472 goto out;
2473 if (alias->slot >= KVM_ALIAS_SLOTS)
2474 goto out;
2475 if (alias->guest_phys_addr + alias->memory_size
2476 < alias->guest_phys_addr)
2477 goto out;
2478 if (alias->target_phys_addr + alias->memory_size
2479 < alias->target_phys_addr)
2480 goto out;
2481
a983fb23
MT		 2482 r = -ENOMEM;
2483 aliases = kzalloc(sizeof(struct kvm_mem_aliases), GFP_KERNEL);
2484 if (!aliases)
2485 goto out;
2486
79fac95e 2487 mutex_lock(&kvm->slots_lock);
1fe779f8 2488
a983fb23
MT		 2489 /* invalidate any gfn reference in case of deletion/shrinking */
2490 memcpy(aliases, kvm->arch.aliases, sizeof(struct kvm_mem_aliases));
2491 aliases->aliases[alias->slot].flags |= KVM_ALIAS_INVALID;
2492 old_aliases = kvm->arch.aliases;
2493 rcu_assign_pointer(kvm->arch.aliases, aliases);
2494 synchronize_srcu_expedited(&kvm->srcu);
2495 kvm_mmu_zap_all(kvm);
2496 kfree(old_aliases);
2497
2498 r = -ENOMEM;
2499 aliases = kzalloc(sizeof(struct kvm_mem_aliases), GFP_KERNEL);
2500 if (!aliases)
2501 goto out_unlock;
2502
2503 memcpy(aliases, kvm->arch.aliases, sizeof(struct kvm_mem_aliases));
fef9cce0
MT		 2504
2505 p = &aliases->aliases[alias->slot];
1fe779f8
CO		 2506 p->base_gfn = alias->guest_phys_addr >> PAGE_SHIFT;
2507 p->npages = alias->memory_size >> PAGE_SHIFT;
2508 p->target_gfn = alias->target_phys_addr >> PAGE_SHIFT;
a983fb23 2509 p->flags &= ~(KVM_ALIAS_INVALID);
1fe779f8
CO		 2510
2511 for (n = KVM_ALIAS_SLOTS; n > 0; --n)
fef9cce0 2512 if (aliases->aliases[n - 1].npages)
1fe779f8 2513 break;
fef9cce0 2514 aliases->naliases = n;
1fe779f8 2515
a983fb23
MT		 2516 old_aliases = kvm->arch.aliases;
2517 rcu_assign_pointer(kvm->arch.aliases, aliases);
2518 synchronize_srcu_expedited(&kvm->srcu);
2519 kfree(old_aliases);
2520 r = 0;
1fe779f8 2521
a983fb23 2522out_unlock:
79fac95e 2523 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 2524out:
2525 return r;
2526}
2527
2528static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2529{
2530 int r;
2531
2532 r = 0;
2533 switch (chip->chip_id) {
2534 case KVM_IRQCHIP_PIC_MASTER:
2535 memcpy(&chip->chip.pic,
2536 &pic_irqchip(kvm)->pics[0],
2537 sizeof(struct kvm_pic_state));
2538 break;
2539 case KVM_IRQCHIP_PIC_SLAVE:
2540 memcpy(&chip->chip.pic,
2541 &pic_irqchip(kvm)->pics[1],
2542 sizeof(struct kvm_pic_state));
2543 break;
2544 case KVM_IRQCHIP_IOAPIC:
eba0226b 2545 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 2546 break;
2547 default:
2548 r = -EINVAL;
2549 break;
2550 }
2551 return r;
2552}
2553
2554static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2555{
2556 int r;
2557
2558 r = 0;
2559 switch (chip->chip_id) {
2560 case KVM_IRQCHIP_PIC_MASTER:
fa8273e9 2561 raw_spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2562 memcpy(&pic_irqchip(kvm)->pics[0],
2563 &chip->chip.pic,
2564 sizeof(struct kvm_pic_state));
fa8273e9 2565 raw_spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2566 break;
2567 case KVM_IRQCHIP_PIC_SLAVE:
fa8273e9 2568 raw_spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2569 memcpy(&pic_irqchip(kvm)->pics[1],
2570 &chip->chip.pic,
2571 sizeof(struct kvm_pic_state));
fa8273e9 2572 raw_spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2573 break;
2574 case KVM_IRQCHIP_IOAPIC:
eba0226b 2575 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 2576 break;
2577 default:
2578 r = -EINVAL;
2579 break;
2580 }
2581 kvm_pic_update_irq(pic_irqchip(kvm));
2582 return r;
2583}
2584
e0f63cb9
SY		 2585static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2586{
2587 int r = 0;
2588
894a9c55 2589 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 2590 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 2591 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 2592 return r;
2593}
2594
2595static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2596{
2597 int r = 0;
2598
894a9c55 2599 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 2600 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 2601 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
2602 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2603 return r;
2604}
2605
2606static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
2607{
2608 int r = 0;
2609
2610 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2611 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
2612 sizeof(ps->channels));
2613 ps->flags = kvm->arch.vpit->pit_state.flags;
2614 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2615 return r;
2616}
2617
2618static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
2619{
2620 int r = 0, start = 0;
2621 u32 prev_legacy, cur_legacy;
2622 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2623 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
2624 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
2625 if (!prev_legacy && cur_legacy)
2626 start = 1;
2627 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
2628 sizeof(kvm->arch.vpit->pit_state.channels));
2629 kvm->arch.vpit->pit_state.flags = ps->flags;
2630 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 2631 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 2632 return r;
2633}
2634
52d939a0
MT		 2635static int kvm_vm_ioctl_reinject(struct kvm *kvm,
2636 struct kvm_reinject_control *control)
2637{
2638 if (!kvm->arch.vpit)
2639 return -ENXIO;
894a9c55 2640 mutex_lock(&kvm->arch.vpit->pit_state.lock);
52d939a0 2641 kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject;
894a9c55 2642 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 2643 return 0;
2644}
2645
5bb064dc
ZX		 2646/*
2647 * Get (and clear) the dirty memory log for a memory slot.
2648 */
2649int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
2650 struct kvm_dirty_log *log)
2651{
87bf6e7d 2652 int r, i;
5bb064dc 2653 struct kvm_memory_slot *memslot;
87bf6e7d 2654 unsigned long n;
b050b015
MT		 2655 unsigned long is_dirty = 0;
2656 unsigned long *dirty_bitmap = NULL;
5bb064dc 2657
79fac95e 2658 mutex_lock(&kvm->slots_lock);
5bb064dc 2659
b050b015
MT		 2660 r = -EINVAL;
2661 if (log->slot >= KVM_MEMORY_SLOTS)
2662 goto out;
2663
2664 memslot = &kvm->memslots->memslots[log->slot];
2665 r = -ENOENT;
2666 if (!memslot->dirty_bitmap)
2667 goto out;
2668
87bf6e7d 2669 n = kvm_dirty_bitmap_bytes(memslot);
b050b015
MT		 2670
2671 r = -ENOMEM;
2672 dirty_bitmap = vmalloc(n);
2673 if (!dirty_bitmap)
5bb064dc 2674 goto out;
b050b015
MT		 2675 memset(dirty_bitmap, 0, n);
2676
2677 for (i = 0; !is_dirty && i < n/sizeof(long); i++)
2678 is_dirty = memslot->dirty_bitmap[i];
5bb064dc
ZX		 2679
2680 /* If nothing is dirty, don't bother messing with page tables. */
2681 if (is_dirty) {
b050b015
MT		 2682 struct kvm_memslots *slots, *old_slots;
2683
7c8a83b7 2684 spin_lock(&kvm->mmu_lock);
5bb064dc 2685 kvm_mmu_slot_remove_write_access(kvm, log->slot);
7c8a83b7 2686 spin_unlock(&kvm->mmu_lock);
b050b015
MT		 2687
2688 slots = kzalloc(sizeof(struct kvm_memslots), GFP_KERNEL);
2689 if (!slots)
2690 goto out_free;
2691
2692 memcpy(slots, kvm->memslots, sizeof(struct kvm_memslots));
2693 slots->memslots[log->slot].dirty_bitmap = dirty_bitmap;
2694
2695 old_slots = kvm->memslots;
2696 rcu_assign_pointer(kvm->memslots, slots);
2697 synchronize_srcu_expedited(&kvm->srcu);
2698 dirty_bitmap = old_slots->memslots[log->slot].dirty_bitmap;
2699 kfree(old_slots);
5bb064dc 2700 }
b050b015 2701
5bb064dc 2702 r = 0;
b050b015
MT		 2703 if (copy_to_user(log->dirty_bitmap, dirty_bitmap, n))
2704 r = -EFAULT;
2705out_free:
2706 vfree(dirty_bitmap);
5bb064dc 2707out:
79fac95e 2708 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 2709 return r;
2710}
2711
1fe779f8
CO		 2712long kvm_arch_vm_ioctl(struct file *filp,
2713 unsigned int ioctl, unsigned long arg)
2714{
2715 struct kvm *kvm = filp->private_data;
2716 void __user *argp = (void __user *)arg;
367e1319 2717 int r = -ENOTTY;
f0d66275
DH		 2718 /*
2719 * This union makes it completely explicit to gcc-3.x
2720 * that these two variables' stack usage should be
2721 * combined, not added together.
2722 */
2723 union {
2724 struct kvm_pit_state ps;
e9f42757 2725 struct kvm_pit_state2 ps2;
f0d66275 2726 struct kvm_memory_alias alias;
c5ff41ce 2727 struct kvm_pit_config pit_config;
f0d66275 2728 } u;
1fe779f8
CO		 2729
2730 switch (ioctl) {
2731 case KVM_SET_TSS_ADDR:
2732 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
2733 if (r < 0)
2734 goto out;
2735 break;
b927a3ce
SY		 2736 case KVM_SET_IDENTITY_MAP_ADDR: {
2737 u64 ident_addr;
2738
2739 r = -EFAULT;
2740 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
2741 goto out;
2742 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
2743 if (r < 0)
2744 goto out;
2745 break;
2746 }
1fe779f8
CO		 2747 case KVM_SET_MEMORY_REGION: {
2748 struct kvm_memory_region kvm_mem;
2749 struct kvm_userspace_memory_region kvm_userspace_mem;
2750
2751 r = -EFAULT;
2752 if (copy_from_user(&kvm_mem, argp, sizeof kvm_mem))
2753 goto out;
2754 kvm_userspace_mem.slot = kvm_mem.slot;
2755 kvm_userspace_mem.flags = kvm_mem.flags;
2756 kvm_userspace_mem.guest_phys_addr = kvm_mem.guest_phys_addr;
2757 kvm_userspace_mem.memory_size = kvm_mem.memory_size;
2758 r = kvm_vm_ioctl_set_memory_region(kvm, &kvm_userspace_mem, 0);
2759 if (r)
2760 goto out;
2761 break;
2762 }
2763 case KVM_SET_NR_MMU_PAGES:
2764 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
2765 if (r)
2766 goto out;
2767 break;
2768 case KVM_GET_NR_MMU_PAGES:
2769 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
2770 break;
f0d66275 2771 case KVM_SET_MEMORY_ALIAS:
1fe779f8 2772 r = -EFAULT;
f0d66275 2773 if (copy_from_user(&u.alias, argp, sizeof(struct kvm_memory_alias)))
1fe779f8 2774 goto out;
f0d66275 2775 r = kvm_vm_ioctl_set_memory_alias(kvm, &u.alias);
1fe779f8
CO		 2776 if (r)
2777 goto out;
2778 break;
3ddea128
MT		 2779 case KVM_CREATE_IRQCHIP: {
2780 struct kvm_pic *vpic;
2781
2782 mutex_lock(&kvm->lock);
2783 r = -EEXIST;
2784 if (kvm->arch.vpic)
2785 goto create_irqchip_unlock;
1fe779f8 2786 r = -ENOMEM;
3ddea128
MT		 2787 vpic = kvm_create_pic(kvm);
2788 if (vpic) {
1fe779f8
CO		 2789 r = kvm_ioapic_init(kvm);
2790 if (r) {
72bb2fcd
WY		 2791 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
2792 &vpic->dev);
3ddea128
MT		 2793 kfree(vpic);
2794 goto create_irqchip_unlock;
1fe779f8
CO		 2795 }
2796 } else
3ddea128
MT		 2797 goto create_irqchip_unlock;
2798 smp_wmb();
2799 kvm->arch.vpic = vpic;
2800 smp_wmb();
399ec807
AK		 2801 r = kvm_setup_default_irq_routing(kvm);
2802 if (r) {
3ddea128 2803 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 2804 kvm_ioapic_destroy(kvm);
2805 kvm_destroy_pic(kvm);
3ddea128 2806 mutex_unlock(&kvm->irq_lock);
399ec807 2807 }
3ddea128
MT		 2808 create_irqchip_unlock:
2809 mutex_unlock(&kvm->lock);
1fe779f8 2810 break;
3ddea128 2811 }
7837699f 2812 case KVM_CREATE_PIT:
c5ff41ce
JK		 2813 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
2814 goto create_pit;
2815 case KVM_CREATE_PIT2:
2816 r = -EFAULT;
2817 if (copy_from_user(&u.pit_config, argp,
2818 sizeof(struct kvm_pit_config)))
2819 goto out;
2820 create_pit:
79fac95e 2821 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 2822 r = -EEXIST;
2823 if (kvm->arch.vpit)
2824 goto create_pit_unlock;
7837699f 2825 r = -ENOMEM;
c5ff41ce 2826 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 2827 if (kvm->arch.vpit)
2828 r = 0;
269e05e4 2829 create_pit_unlock:
79fac95e 2830 mutex_unlock(&kvm->slots_lock);
7837699f 2831 break;
4925663a 2832 case KVM_IRQ_LINE_STATUS:
1fe779f8
CO		 2833 case KVM_IRQ_LINE: {
2834 struct kvm_irq_level irq_event;
2835
2836 r = -EFAULT;
2837 if (copy_from_user(&irq_event, argp, sizeof irq_event))
2838 goto out;
160d2f6c 2839 r = -ENXIO;
1fe779f8 2840 if (irqchip_in_kernel(kvm)) {
4925663a 2841 __s32 status;
4925663a
GN		 2842 status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
2843 irq_event.irq, irq_event.level);
4925663a 2844 if (ioctl == KVM_IRQ_LINE_STATUS) {
160d2f6c 2845 r = -EFAULT;
4925663a
GN		 2846 irq_event.status = status;
2847 if (copy_to_user(argp, &irq_event,
2848 sizeof irq_event))
2849 goto out;
2850 }
1fe779f8
CO		 2851 r = 0;
2852 }
2853 break;
2854 }
2855 case KVM_GET_IRQCHIP: {
2856 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 2857 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 2858
f0d66275
DH		 2859 r = -ENOMEM;
2860 if (!chip)
1fe779f8 2861 goto out;
f0d66275
DH		 2862 r = -EFAULT;
2863 if (copy_from_user(chip, argp, sizeof *chip))
2864 goto get_irqchip_out;
1fe779f8
CO		 2865 r = -ENXIO;
2866 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 2867 goto get_irqchip_out;
2868 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 2869 if (r)
f0d66275 2870 goto get_irqchip_out;
1fe779f8 2871 r = -EFAULT;
f0d66275
DH		 2872 if (copy_to_user(argp, chip, sizeof *chip))
2873 goto get_irqchip_out;
1fe779f8 2874 r = 0;
f0d66275
DH		 2875 get_irqchip_out:
2876 kfree(chip);
2877 if (r)
2878 goto out;
1fe779f8
CO		 2879 break;
2880 }
2881 case KVM_SET_IRQCHIP: {
2882 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 2883 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 2884
f0d66275
DH		 2885 r = -ENOMEM;
2886 if (!chip)
1fe779f8 2887 goto out;
f0d66275
DH		 2888 r = -EFAULT;
2889 if (copy_from_user(chip, argp, sizeof *chip))
2890 goto set_irqchip_out;
1fe779f8
CO		 2891 r = -ENXIO;
2892 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 2893 goto set_irqchip_out;
2894 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 2895 if (r)
f0d66275 2896 goto set_irqchip_out;
1fe779f8 2897 r = 0;
f0d66275
DH		 2898 set_irqchip_out:
2899 kfree(chip);
2900 if (r)
2901 goto out;
1fe779f8
CO		 2902 break;
2903 }
e0f63cb9 2904 case KVM_GET_PIT: {
e0f63cb9 2905 r = -EFAULT;
f0d66275 2906 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 2907 goto out;
2908 r = -ENXIO;
2909 if (!kvm->arch.vpit)
2910 goto out;
f0d66275 2911 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 2912 if (r)
2913 goto out;
2914 r = -EFAULT;
f0d66275 2915 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 2916 goto out;
2917 r = 0;
2918 break;
2919 }
2920 case KVM_SET_PIT: {
e0f63cb9 2921 r = -EFAULT;
f0d66275 2922 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 2923 goto out;
2924 r = -ENXIO;
2925 if (!kvm->arch.vpit)
2926 goto out;
f0d66275 2927 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 2928 if (r)
2929 goto out;
2930 r = 0;
2931 break;
2932 }
e9f42757
BK		 2933 case KVM_GET_PIT2: {
2934 r = -ENXIO;
2935 if (!kvm->arch.vpit)
2936 goto out;
2937 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
2938 if (r)
2939 goto out;
2940 r = -EFAULT;
2941 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
2942 goto out;
2943 r = 0;
2944 break;
2945 }
2946 case KVM_SET_PIT2: {
2947 r = -EFAULT;
2948 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
2949 goto out;
2950 r = -ENXIO;
2951 if (!kvm->arch.vpit)
2952 goto out;
2953 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
2954 if (r)
2955 goto out;
2956 r = 0;
2957 break;
2958 }
52d939a0
MT		 2959 case KVM_REINJECT_CONTROL: {
2960 struct kvm_reinject_control control;
2961 r = -EFAULT;
2962 if (copy_from_user(&control, argp, sizeof(control)))
2963 goto out;
2964 r = kvm_vm_ioctl_reinject(kvm, &control);
2965 if (r)
2966 goto out;
2967 r = 0;
2968 break;
2969 }
ffde22ac
ES		 2970 case KVM_XEN_HVM_CONFIG: {
2971 r = -EFAULT;
2972 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
2973 sizeof(struct kvm_xen_hvm_config)))
2974 goto out;
2975 r = -EINVAL;
2976 if (kvm->arch.xen_hvm_config.flags)
2977 goto out;
2978 r = 0;
2979 break;
2980 }
afbcf7ab
GC		 2981 case KVM_SET_CLOCK: {
2982 struct timespec now;
2983 struct kvm_clock_data user_ns;
2984 u64 now_ns;
2985 s64 delta;
2986
2987 r = -EFAULT;
2988 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
2989 goto out;
2990
2991 r = -EINVAL;
2992 if (user_ns.flags)
2993 goto out;
2994
2995 r = 0;
2996 ktime_get_ts(&now);
2997 now_ns = timespec_to_ns(&now);
2998 delta = user_ns.clock - now_ns;
2999 kvm->arch.kvmclock_offset = delta;
3000 break;
3001 }
3002 case KVM_GET_CLOCK: {
3003 struct timespec now;
3004 struct kvm_clock_data user_ns;
3005 u64 now_ns;
3006
3007 ktime_get_ts(&now);
3008 now_ns = timespec_to_ns(&now);
3009 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
3010 user_ns.flags = 0;
3011
3012 r = -EFAULT;
3013 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3014 goto out;
3015 r = 0;
3016 break;
3017 }
3018
1fe779f8
CO		 3019 default:
3020 ;
3021 }
3022out:
3023 return r;
3024}
3025
a16b043c 3026static void kvm_init_msr_list(void)
043405e1
CO		 3027{
3028 u32 dummy[2];
3029 unsigned i, j;
3030
e3267cbb
GC		 3031 /* skip the first msrs in the list. KVM-specific */
3032 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3033 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3034 continue;
3035 if (j < i)
3036 msrs_to_save[j] = msrs_to_save[i];
3037 j++;
3038 }
3039 num_msrs_to_save = j;
3040}
3041
bda9020e
MT		 3042static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3043 const void *v)
bbd9b64e 3044{
bda9020e
MT		 3045 if (vcpu->arch.apic &&
3046 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, len, v))
3047 return 0;
bbd9b64e 3048
e93f8a0f 3049 return kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, len, v);
bbd9b64e
CO		 3050}
3051
bda9020e 3052static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 3053{
bda9020e
MT		 3054 if (vcpu->arch.apic &&
3055 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, len, v))
3056 return 0;
bbd9b64e 3057
e93f8a0f 3058 return kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, len, v);
bbd9b64e
CO		 3059}
3060
1871c602
GN		 3061gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3062{
3063 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3064 return vcpu->arch.mmu.gva_to_gpa(vcpu, gva, access, error);
3065}
3066
3067 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3068{
3069 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3070 access |= PFERR_FETCH_MASK;
3071 return vcpu->arch.mmu.gva_to_gpa(vcpu, gva, access, error);
3072}
3073
3074gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3075{
3076 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3077 access |= PFERR_WRITE_MASK;
3078 return vcpu->arch.mmu.gva_to_gpa(vcpu, gva, access, error);
3079}
3080
3081/* uses this to access any guest's mapped memory without checking CPL */
3082gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3083{
3084 return vcpu->arch.mmu.gva_to_gpa(vcpu, gva, 0, error);
3085}
3086
3087static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3088 struct kvm_vcpu *vcpu, u32 access,
3089 u32 *error)
bbd9b64e
CO		 3090{
3091 void *data = val;
10589a46 3092 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 3093
3094 while (bytes) {
1871c602 3095 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr, access, error);
bbd9b64e 3096 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 3097 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 3098 int ret;
3099
10589a46
MT		 3100 if (gpa == UNMAPPED_GVA) {
3101 r = X86EMUL_PROPAGATE_FAULT;
3102 goto out;
3103 }
77c2002e 3104 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46
MT		 3105 if (ret < 0) {
3106 r = X86EMUL_UNHANDLEABLE;
3107 goto out;
3108 }
bbd9b64e 3109
77c2002e
IE		 3110 bytes -= toread;
3111 data += toread;
3112 addr += toread;
bbd9b64e 3113 }
10589a46 3114out:
10589a46 3115 return r;
bbd9b64e 3116}
77c2002e 3117
1871c602
GN		 3118/* used for instruction fetching */
3119static int kvm_fetch_guest_virt(gva_t addr, void *val, unsigned int bytes,
3120 struct kvm_vcpu *vcpu, u32 *error)
3121{
3122 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3123 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
3124 access | PFERR_FETCH_MASK, error);
3125}
3126
3127static int kvm_read_guest_virt(gva_t addr, void *val, unsigned int bytes,
3128 struct kvm_vcpu *vcpu, u32 *error)
3129{
3130 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3131 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
3132 error);
3133}
3134
3135static int kvm_read_guest_virt_system(gva_t addr, void *val, unsigned int bytes,
3136 struct kvm_vcpu *vcpu, u32 *error)
3137{
3138 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, error);
3139}
3140
cded19f3 3141static int kvm_write_guest_virt(gva_t addr, void *val, unsigned int bytes,
1871c602 3142 struct kvm_vcpu *vcpu, u32 *error)
77c2002e
IE		 3143{
3144 void *data = val;
3145 int r = X86EMUL_CONTINUE;
3146
3147 while (bytes) {
1871c602 3148 gpa_t gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, error);
77c2002e
IE		 3149 unsigned offset = addr & (PAGE_SIZE-1);
3150 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
3151 int ret;
3152
3153 if (gpa == UNMAPPED_GVA) {
3154 r = X86EMUL_PROPAGATE_FAULT;
3155 goto out;
3156 }
3157 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
3158 if (ret < 0) {
3159 r = X86EMUL_UNHANDLEABLE;
3160 goto out;
3161 }
3162
3163 bytes -= towrite;
3164 data += towrite;
3165 addr += towrite;
3166 }
3167out:
3168 return r;
3169}
3170
bbd9b64e 3171
bbd9b64e
CO		 3172static int emulator_read_emulated(unsigned long addr,
3173 void *val,
3174 unsigned int bytes,
3175 struct kvm_vcpu *vcpu)
3176{
bbd9b64e 3177 gpa_t gpa;
1871c602 3178 u32 error_code;
bbd9b64e
CO		 3179
3180 if (vcpu->mmio_read_completed) {
3181 memcpy(val, vcpu->mmio_data, bytes);
aec51dc4
AK		 3182 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
3183 vcpu->mmio_phys_addr, *(u64 *)val);
bbd9b64e
CO		 3184 vcpu->mmio_read_completed = 0;
3185 return X86EMUL_CONTINUE;
3186 }
3187
1871c602
GN		 3188 gpa = kvm_mmu_gva_to_gpa_read(vcpu, addr, &error_code);
3189
3190 if (gpa == UNMAPPED_GVA) {
3191 kvm_inject_page_fault(vcpu, addr, error_code);
3192 return X86EMUL_PROPAGATE_FAULT;
3193 }
bbd9b64e
CO		 3194
3195 /* For APIC access vmexit */
3196 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3197 goto mmio;
3198
1871c602 3199 if (kvm_read_guest_virt(addr, val, bytes, vcpu, NULL)
77c2002e 3200 == X86EMUL_CONTINUE)
bbd9b64e 3201 return X86EMUL_CONTINUE;
bbd9b64e
CO		 3202
3203mmio:
3204 /*
3205 * Is this MMIO handled locally?
3206 */
aec51dc4
AK		 3207 if (!vcpu_mmio_read(vcpu, gpa, bytes, val)) {
3208 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 3209 return X86EMUL_CONTINUE;
3210 }
aec51dc4
AK		 3211
3212 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
bbd9b64e
CO		 3213
3214 vcpu->mmio_needed = 1;
3215 vcpu->mmio_phys_addr = gpa;
3216 vcpu->mmio_size = bytes;
3217 vcpu->mmio_is_write = 0;
3218
3219 return X86EMUL_UNHANDLEABLE;
3220}
3221
3200f405 3222int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
9f811285 3223 const void *val, int bytes)
bbd9b64e
CO		 3224{
3225 int ret;
3226
3227 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 3228 if (ret < 0)
bbd9b64e 3229 return 0;
ad218f85 3230 kvm_mmu_pte_write(vcpu, gpa, val, bytes, 1);
bbd9b64e
CO		 3231 return 1;
3232}
3233
3234static int emulator_write_emulated_onepage(unsigned long addr,
3235 const void *val,
3236 unsigned int bytes,
4a5f48f6
AK		 3237 struct kvm_vcpu *vcpu,
3238 bool mmu_only)
bbd9b64e 3239{
10589a46 3240 gpa_t gpa;
1871c602 3241 u32 error_code;
10589a46 3242
1871c602 3243 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, &error_code);
bbd9b64e
CO		 3244
3245 if (gpa == UNMAPPED_GVA) {
1871c602 3246 kvm_inject_page_fault(vcpu, addr, error_code);
bbd9b64e
CO		 3247 return X86EMUL_PROPAGATE_FAULT;
3248 }
3249
3250 /* For APIC access vmexit */
3251 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3252 goto mmio;
3253
4a5f48f6
AK		 3254 if (mmu_only) {
3255 kvm_mmu_pte_write(vcpu, gpa, val, bytes, 1);
3256 return X86EMUL_CONTINUE;
3257 }
bbd9b64e
CO		 3258 if (emulator_write_phys(vcpu, gpa, val, bytes))
3259 return X86EMUL_CONTINUE;
3260
3261mmio:
aec51dc4 3262 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 3263 /*
3264 * Is this MMIO handled locally?
3265 */
bda9020e 3266 if (!vcpu_mmio_write(vcpu, gpa, bytes, val))
bbd9b64e 3267 return X86EMUL_CONTINUE;
bbd9b64e
CO		 3268
3269 vcpu->mmio_needed = 1;
3270 vcpu->mmio_phys_addr = gpa;
3271 vcpu->mmio_size = bytes;
3272 vcpu->mmio_is_write = 1;
3273 memcpy(vcpu->mmio_data, val, bytes);
3274
3275 return X86EMUL_CONTINUE;
3276}
3277
4a5f48f6 3278int __emulator_write_emulated(unsigned long addr,
bbd9b64e
CO		 3279 const void *val,
3280 unsigned int bytes,
4a5f48f6
AK		 3281 struct kvm_vcpu *vcpu,
3282 bool mmu_only)
bbd9b64e
CO		 3283{
3284 /* Crossing a page boundary? */
3285 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
3286 int rc, now;
3287
3288 now = -addr & ~PAGE_MASK;
4a5f48f6
AK		 3289 rc = emulator_write_emulated_onepage(addr, val, now, vcpu,
3290 mmu_only);
bbd9b64e
CO		 3291 if (rc != X86EMUL_CONTINUE)
3292 return rc;
3293 addr += now;
3294 val += now;
3295 bytes -= now;
3296 }
4a5f48f6
AK		 3297 return emulator_write_emulated_onepage(addr, val, bytes, vcpu,
3298 mmu_only);
3299}
3300
3301int emulator_write_emulated(unsigned long addr,
3302 const void *val,
3303 unsigned int bytes,
3304 struct kvm_vcpu *vcpu)
3305{
3306 return __emulator_write_emulated(addr, val, bytes, vcpu, false);
bbd9b64e
CO		 3307}
3308EXPORT_SYMBOL_GPL(emulator_write_emulated);
3309
daea3e73
AK		 3310#define CMPXCHG_TYPE(t, ptr, old, new) \
3311 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
3312
3313#ifdef CONFIG_X86_64
3314# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
3315#else
3316# define CMPXCHG64(ptr, old, new) \
3317 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u *)(new)) == *(u64 *)(old))
3318#endif
3319
bbd9b64e
CO		 3320static int emulator_cmpxchg_emulated(unsigned long addr,
3321 const void *old,
3322 const void *new,
3323 unsigned int bytes,
3324 struct kvm_vcpu *vcpu)
3325{
daea3e73
AK		 3326 gpa_t gpa;
3327 struct page *page;
3328 char *kaddr;
3329 bool exchanged;
2bacc55c 3330
daea3e73
AK		 3331 /* guests cmpxchg8b have to be emulated atomically */
3332 if (bytes > 8 || (bytes & (bytes - 1)))
3333 goto emul_write;
10589a46 3334
daea3e73 3335 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 3336
daea3e73
AK		 3337 if (gpa == UNMAPPED_GVA ||
3338 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3339 goto emul_write;
2bacc55c 3340
daea3e73
AK		 3341 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
3342 goto emul_write;
72dc67a6 3343
daea3e73 3344 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
72dc67a6 3345
daea3e73
AK		 3346 kaddr = kmap_atomic(page, KM_USER0);
3347 kaddr += offset_in_page(gpa);
3348 switch (bytes) {
3349 case 1:
3350 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
3351 break;
3352 case 2:
3353 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
3354 break;
3355 case 4:
3356 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
3357 break;
3358 case 8:
3359 exchanged = CMPXCHG64(kaddr, old, new);
3360 break;
3361 default:
3362 BUG();
2bacc55c 3363 }
daea3e73
AK		 3364 kunmap_atomic(kaddr, KM_USER0);
3365 kvm_release_page_dirty(page);
3366
3367 if (!exchanged)
3368 return X86EMUL_CMPXCHG_FAILED;
3369
4a5f48f6
AK		 3370 return __emulator_write_emulated(addr, new, bytes, vcpu, true);
3371
3200f405 3372emul_write:
daea3e73 3373 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 3374
bbd9b64e
CO		 3375 return emulator_write_emulated(addr, new, bytes, vcpu);
3376}
3377
3378static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
3379{
3380 return kvm_x86_ops->get_segment_base(vcpu, seg);
3381}
3382
3383int emulate_invlpg(struct kvm_vcpu *vcpu, gva_t address)
3384{
a7052897 3385 kvm_mmu_invlpg(vcpu, address);
bbd9b64e
CO		 3386 return X86EMUL_CONTINUE;
3387}
3388
3389int emulate_clts(struct kvm_vcpu *vcpu)
3390{
4d4ec087 3391 kvm_x86_ops->set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
6b52d186 3392 kvm_x86_ops->fpu_activate(vcpu);
bbd9b64e
CO		 3393 return X86EMUL_CONTINUE;
3394}
3395
3396int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
3397{
c76de350 3398 return kvm_x86_ops->get_dr(ctxt->vcpu, dr, dest);
bbd9b64e
CO		 3399}
3400
3401int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
3402{
3403 unsigned long mask = (ctxt->mode == X86EMUL_MODE_PROT64) ? ~0ULL : ~0U;
bbd9b64e 3404
c76de350 3405 return kvm_x86_ops->set_dr(ctxt->vcpu, dr, value & mask);
bbd9b64e
CO		 3406}
3407
3408void kvm_report_emulation_failure(struct kvm_vcpu *vcpu, const char *context)
3409{
bbd9b64e 3410 u8 opcodes[4];
5fdbf976 3411 unsigned long rip = kvm_rip_read(vcpu);
bbd9b64e
CO		 3412 unsigned long rip_linear;
3413
f76c710d 3414 if (!printk_ratelimit())
bbd9b64e
CO		 3415 return;
3416
25be4608
GC		 3417 rip_linear = rip + get_segment_base(vcpu, VCPU_SREG_CS);
3418
1871c602 3419 kvm_read_guest_virt(rip_linear, (void *)opcodes, 4, vcpu, NULL);
bbd9b64e
CO		 3420
3421 printk(KERN_ERR "emulation failed (%s) rip %lx %02x %02x %02x %02x\n",
3422 context, rip, opcodes[0], opcodes[1], opcodes[2], opcodes[3]);
bbd9b64e
CO		 3423}
3424EXPORT_SYMBOL_GPL(kvm_report_emulation_failure);
3425
52a46617
GN		 3426static u64 mk_cr_64(u64 curr_cr, u32 new_val)
3427{
3428 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
3429}
3430
3431static unsigned long emulator_get_cr(int cr, struct kvm_vcpu *vcpu)
3432{
3433 unsigned long value;
3434
3435 switch (cr) {
3436 case 0:
3437 value = kvm_read_cr0(vcpu);
3438 break;
3439 case 2:
3440 value = vcpu->arch.cr2;
3441 break;
3442 case 3:
3443 value = vcpu->arch.cr3;
3444 break;
3445 case 4:
3446 value = kvm_read_cr4(vcpu);
3447 break;
3448 case 8:
3449 value = kvm_get_cr8(vcpu);
3450 break;
3451 default:
3452 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
3453 return 0;
3454 }
3455
3456 return value;
3457}
3458
3459static void emulator_set_cr(int cr, unsigned long val, struct kvm_vcpu *vcpu)
3460{
3461 switch (cr) {
3462 case 0:
3463 kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
3464 break;
3465 case 2:
3466 vcpu->arch.cr2 = val;
3467 break;
3468 case 3:
3469 kvm_set_cr3(vcpu, val);
3470 break;
3471 case 4:
3472 kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
3473 break;
3474 case 8:
3475 kvm_set_cr8(vcpu, val & 0xfUL);
3476 break;
3477 default:
3478 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
3479 }
3480}
3481
14af3f3c 3482static struct x86_emulate_ops emulate_ops = {
1871c602
GN		 3483 .read_std = kvm_read_guest_virt_system,
3484 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 3485 .read_emulated = emulator_read_emulated,
3486 .write_emulated = emulator_write_emulated,
3487 .cmpxchg_emulated = emulator_cmpxchg_emulated,
52a46617
GN		 3488 .get_cr = emulator_get_cr,
3489 .set_cr = emulator_set_cr,
bbd9b64e
CO		 3490};
3491
5fdbf976
MT		 3492static void cache_all_regs(struct kvm_vcpu *vcpu)
3493{
3494 kvm_register_read(vcpu, VCPU_REGS_RAX);
3495 kvm_register_read(vcpu, VCPU_REGS_RSP);
3496 kvm_register_read(vcpu, VCPU_REGS_RIP);
3497 vcpu->arch.regs_dirty = ~0;
3498}
3499
bbd9b64e 3500int emulate_instruction(struct kvm_vcpu *vcpu,
bbd9b64e
CO		 3501 unsigned long cr2,
3502 u16 error_code,
571008da 3503 int emulation_type)
bbd9b64e 3504{
310b5d30 3505 int r, shadow_mask;
571008da 3506 struct decode_cache *c;
851ba692 3507 struct kvm_run *run = vcpu->run;
bbd9b64e 3508
26eef70c 3509 kvm_clear_exception_queue(vcpu);
ad312c7c 3510 vcpu->arch.mmio_fault_cr2 = cr2;
5fdbf976 3511 /*
56e82318 3512 * TODO: fix emulate.c to use guest_read/write_register
5fdbf976
MT		 3513 * instead of direct ->regs accesses, can save hundred cycles
3514 * on Intel for instructions that don't read/change RSP, for
3515 * for example.
3516 */
3517 cache_all_regs(vcpu);
bbd9b64e
CO		 3518
3519 vcpu->mmio_is_write = 0;
ad312c7c 3520 vcpu->arch.pio.string = 0;
bbd9b64e 3521
571008da 3522 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
bbd9b64e
CO		 3523 int cs_db, cs_l;
3524 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
3525
ad312c7c 3526 vcpu->arch.emulate_ctxt.vcpu = vcpu;
83bf0002 3527 vcpu->arch.emulate_ctxt.eflags = kvm_x86_ops->get_rflags(vcpu);
ad312c7c 3528 vcpu->arch.emulate_ctxt.mode =
a0044755 3529 (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
ad312c7c 3530 (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM)
a0044755 3531 ? X86EMUL_MODE_VM86 : cs_l
bbd9b64e
CO		 3532 ? X86EMUL_MODE_PROT64 : cs_db
3533 ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
3534
ad312c7c 3535 r = x86_decode_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
571008da 3536
0cb5762e
AP		 3537 /* Only allow emulation of specific instructions on #UD
3538 * (namely VMMCALL, sysenter, sysexit, syscall)*/
571008da 3539 c = &vcpu->arch.emulate_ctxt.decode;
0cb5762e
AP		 3540 if (emulation_type & EMULTYPE_TRAP_UD) {
3541 if (!c->twobyte)
3542 return EMULATE_FAIL;
3543 switch (c->b) {
3544 case 0x01: /* VMMCALL */
3545 if (c->modrm_mod != 3 || c->modrm_rm != 1)
3546 return EMULATE_FAIL;
3547 break;
3548 case 0x34: /* sysenter */
3549 case 0x35: /* sysexit */
3550 if (c->modrm_mod != 0 || c->modrm_rm != 0)
3551 return EMULATE_FAIL;
3552 break;
3553 case 0x05: /* syscall */
3554 if (c->modrm_mod != 0 || c->modrm_rm != 0)
3555 return EMULATE_FAIL;
3556 break;
3557 default:
3558 return EMULATE_FAIL;
3559 }
3560
3561 if (!(c->modrm_reg == 0 || c->modrm_reg == 3))
3562 return EMULATE_FAIL;
3563 }
571008da 3564
f2b5756b 3565 ++vcpu->stat.insn_emulation;
bbd9b64e 3566 if (r) {
f2b5756b 3567 ++vcpu->stat.insn_emulation_fail;
bbd9b64e
CO		 3568 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
3569 return EMULATE_DONE;
3570 return EMULATE_FAIL;
3571 }
3572 }
3573
ba8afb6b
GN		 3574 if (emulation_type & EMULTYPE_SKIP) {
3575 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.decode.eip);
3576 return EMULATE_DONE;
3577 }
3578
ad312c7c 3579 r = x86_emulate_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
310b5d30
GC		 3580 shadow_mask = vcpu->arch.emulate_ctxt.interruptibility;
3581
3582 if (r == 0)
3583 kvm_x86_ops->set_interrupt_shadow(vcpu, shadow_mask);
bbd9b64e 3584
ad312c7c 3585 if (vcpu->arch.pio.string)
bbd9b64e
CO		 3586 return EMULATE_DO_MMIO;
3587
112592da 3588 if (r || vcpu->mmio_is_write) {
bbd9b64e
CO		 3589 run->exit_reason = KVM_EXIT_MMIO;
3590 run->mmio.phys_addr = vcpu->mmio_phys_addr;
3591 memcpy(run->mmio.data, vcpu->mmio_data, 8);
3592 run->mmio.len = vcpu->mmio_size;
3593 run->mmio.is_write = vcpu->mmio_is_write;
3594 }
3595
3596 if (r) {
3597 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
3598 return EMULATE_DONE;
3599 if (!vcpu->mmio_needed) {
3600 kvm_report_emulation_failure(vcpu, "mmio");
3601 return EMULATE_FAIL;
3602 }
3603 return EMULATE_DO_MMIO;
3604 }
3605
83bf0002 3606 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
bbd9b64e
CO		 3607
3608 if (vcpu->mmio_is_write) {
3609 vcpu->mmio_needed = 0;
3610 return EMULATE_DO_MMIO;
3611 }
3612
3613 return EMULATE_DONE;
3614}
3615EXPORT_SYMBOL_GPL(emulate_instruction);
3616
de7d789a
CO		 3617static int pio_copy_data(struct kvm_vcpu *vcpu)
3618{
ad312c7c 3619 void *p = vcpu->arch.pio_data;
0f346074 3620 gva_t q = vcpu->arch.pio.guest_gva;
de7d789a 3621 unsigned bytes;
0f346074 3622 int ret;
1871c602 3623 u32 error_code;
de7d789a 3624
ad312c7c
ZX		 3625 bytes = vcpu->arch.pio.size * vcpu->arch.pio.cur_count;
3626 if (vcpu->arch.pio.in)
1871c602 3627 ret = kvm_write_guest_virt(q, p, bytes, vcpu, &error_code);
de7d789a 3628 else
1871c602
GN		 3629 ret = kvm_read_guest_virt(q, p, bytes, vcpu, &error_code);
3630
3631 if (ret == X86EMUL_PROPAGATE_FAULT)
3632 kvm_inject_page_fault(vcpu, q, error_code);
3633
0f346074 3634 return ret;
de7d789a
CO		 3635}
3636
3637int complete_pio(struct kvm_vcpu *vcpu)
3638{
ad312c7c 3639 struct kvm_pio_request *io = &vcpu->arch.pio;
de7d789a
CO		 3640 long delta;
3641 int r;
5fdbf976 3642 unsigned long val;
de7d789a
CO		 3643
3644 if (!io->string) {
5fdbf976
MT		 3645 if (io->in) {
3646 val = kvm_register_read(vcpu, VCPU_REGS_RAX);
3647 memcpy(&val, vcpu->arch.pio_data, io->size);
3648 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
3649 }
de7d789a
CO		 3650 } else {
3651 if (io->in) {
3652 r = pio_copy_data(vcpu);
5fdbf976 3653 if (r)
1871c602 3654 goto out;
de7d789a
CO		 3655 }
3656
3657 delta = 1;
3658 if (io->rep) {
3659 delta *= io->cur_count;
3660 /*
3661 * The size of the register should really depend on
3662 * current address size.
3663 */
5fdbf976
MT		 3664 val = kvm_register_read(vcpu, VCPU_REGS_RCX);
3665 val -= delta;
3666 kvm_register_write(vcpu, VCPU_REGS_RCX, val);
de7d789a
CO		 3667 }
3668 if (io->down)
3669 delta = -delta;
3670 delta *= io->size;
5fdbf976
MT		 3671 if (io->in) {
3672 val = kvm_register_read(vcpu, VCPU_REGS_RDI);
3673 val += delta;
3674 kvm_register_write(vcpu, VCPU_REGS_RDI, val);
3675 } else {
3676 val = kvm_register_read(vcpu, VCPU_REGS_RSI);
3677 val += delta;
3678 kvm_register_write(vcpu, VCPU_REGS_RSI, val);
3679 }
de7d789a 3680 }
1871c602 3681out:
de7d789a
CO		 3682 io->count -= io->cur_count;
3683 io->cur_count = 0;
3684
3685 return 0;
3686}
3687
bda9020e 3688static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
de7d789a
CO		 3689{
3690 /* TODO: String I/O for in kernel device */
bda9020e 3691 int r;
de7d789a 3692
ad312c7c 3693 if (vcpu->arch.pio.in)
e93f8a0f 3694 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
bda9020e 3695 vcpu->arch.pio.size, pd);
de7d789a 3696 else
e93f8a0f
MT		 3697 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
3698 vcpu->arch.pio.port, vcpu->arch.pio.size,
3699 pd);
bda9020e 3700 return r;
de7d789a
CO		 3701}
3702
bda9020e 3703static int pio_string_write(struct kvm_vcpu *vcpu)
de7d789a 3704{
ad312c7c
ZX		 3705 struct kvm_pio_request *io = &vcpu->arch.pio;
3706 void *pd = vcpu->arch.pio_data;
bda9020e 3707 int i, r = 0;
de7d789a 3708
de7d789a 3709 for (i = 0; i < io->cur_count; i++) {
e93f8a0f 3710 if (kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
bda9020e
MT		 3711 io->port, io->size, pd)) {
3712 r = -EOPNOTSUPP;
3713 break;
3714 }
de7d789a
CO		 3715 pd += io->size;
3716 }
bda9020e 3717 return r;
de7d789a
CO		 3718}
3719
851ba692 3720int kvm_emulate_pio(struct kvm_vcpu *vcpu, int in, int size, unsigned port)
de7d789a 3721{
5fdbf976 3722 unsigned long val;
de7d789a 3723
f850e2e6
GN		 3724 trace_kvm_pio(!in, port, size, 1);
3725
de7d789a
CO		 3726 vcpu->run->exit_reason = KVM_EXIT_IO;
3727 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
ad312c7c 3728 vcpu->run->io.size = vcpu->arch.pio.size = size;
de7d789a 3729 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
ad312c7c
ZX		 3730 vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = 1;
3731 vcpu->run->io.port = vcpu->arch.pio.port = port;
3732 vcpu->arch.pio.in = in;
3733 vcpu->arch.pio.string = 0;
3734 vcpu->arch.pio.down = 0;
ad312c7c 3735 vcpu->arch.pio.rep = 0;
de7d789a 3736
1976d2d2
TY		 3737 if (!vcpu->arch.pio.in) {
3738 val = kvm_register_read(vcpu, VCPU_REGS_RAX);
3739 memcpy(vcpu->arch.pio_data, &val, 4);
3740 }
de7d789a 3741
bda9020e 3742 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
de7d789a
CO		 3743 complete_pio(vcpu);
3744 return 1;
3745 }
3746 return 0;
3747}
3748EXPORT_SYMBOL_GPL(kvm_emulate_pio);
3749
851ba692 3750int kvm_emulate_pio_string(struct kvm_vcpu *vcpu, int in,
de7d789a
CO		 3751 int size, unsigned long count, int down,
3752 gva_t address, int rep, unsigned port)
3753{
3754 unsigned now, in_page;
0f346074 3755 int ret = 0;
de7d789a 3756
f850e2e6
GN		 3757 trace_kvm_pio(!in, port, size, count);
3758
de7d789a
CO		 3759 vcpu->run->exit_reason = KVM_EXIT_IO;
3760 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
ad312c7c 3761 vcpu->run->io.size = vcpu->arch.pio.size = size;
de7d789a 3762 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
ad312c7c
ZX		 3763 vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = count;
3764 vcpu->run->io.port = vcpu->arch.pio.port = port;
3765 vcpu->arch.pio.in = in;
3766 vcpu->arch.pio.string = 1;
3767 vcpu->arch.pio.down = down;
ad312c7c 3768 vcpu->arch.pio.rep = rep;
de7d789a
CO		 3769
3770 if (!count) {
3771 kvm_x86_ops->skip_emulated_instruction(vcpu);
3772 return 1;
3773 }
3774
3775 if (!down)
3776 in_page = PAGE_SIZE - offset_in_page(address);
3777 else
3778 in_page = offset_in_page(address) + size;
3779 now = min(count, (unsigned long)in_page / size);
0f346074 3780 if (!now)
de7d789a 3781 now = 1;
de7d789a
CO		 3782 if (down) {
3783 /*
3784 * String I/O in reverse. Yuck. Kill the guest, fix later.
3785 */
3786 pr_unimpl(vcpu, "guest string pio down\n");
c1a5d4f9 3787 kvm_inject_gp(vcpu, 0);
de7d789a
CO		 3788 return 1;
3789 }
3790 vcpu->run->io.count = now;
ad312c7c 3791 vcpu->arch.pio.cur_count = now;
de7d789a 3792
ad312c7c 3793 if (vcpu->arch.pio.cur_count == vcpu->arch.pio.count)
de7d789a
CO		 3794 kvm_x86_ops->skip_emulated_instruction(vcpu);
3795
0f346074 3796 vcpu->arch.pio.guest_gva = address;
de7d789a 3797
ad312c7c 3798 if (!vcpu->arch.pio.in) {
de7d789a
CO		 3799 /* string PIO write */
3800 ret = pio_copy_data(vcpu);
1871c602 3801 if (ret == X86EMUL_PROPAGATE_FAULT)
0f346074 3802 return 1;
bda9020e 3803 if (ret == 0 && !pio_string_write(vcpu)) {
de7d789a 3804 complete_pio(vcpu);
ad312c7c 3805 if (vcpu->arch.pio.count == 0)
de7d789a
CO		 3806 ret = 1;
3807 }
bda9020e
MT		 3808 }
3809 /* no string PIO read support yet */
de7d789a
CO		 3810
3811 return ret;
3812}
3813EXPORT_SYMBOL_GPL(kvm_emulate_pio_string);
3814
c8076604
GH		 3815static void bounce_off(void *info)
3816{
3817 /* nothing */
3818}
3819
c8076604
GH		 3820static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
3821 void *data)
3822{
3823 struct cpufreq_freqs *freq = data;
3824 struct kvm *kvm;
3825 struct kvm_vcpu *vcpu;
3826 int i, send_ipi = 0;
3827
c8076604
GH		 3828 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
3829 return 0;
3830 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
3831 return 0;
0cca7907 3832 per_cpu(cpu_tsc_khz, freq->cpu) = freq->new;
c8076604
GH		 3833
3834 spin_lock(&kvm_lock);
3835 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 3836 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 3837 if (vcpu->cpu != freq->cpu)
3838 continue;
3839 if (!kvm_request_guest_time_update(vcpu))
3840 continue;
3841 if (vcpu->cpu != smp_processor_id())
3842 send_ipi++;
3843 }
3844 }
3845 spin_unlock(&kvm_lock);
3846
3847 if (freq->old < freq->new && send_ipi) {
3848 /*
3849 * We upscale the frequency. Must make the guest
3850 * doesn't see old kvmclock values while running with
3851 * the new frequency, otherwise we risk the guest sees
3852 * time go backwards.
3853 *
3854 * In case we update the frequency for another cpu
3855 * (which might be in guest context) send an interrupt
3856 * to kick the cpu out of guest context. Next time
3857 * guest context is entered kvmclock will be updated,
3858 * so the guest will not see stale values.
3859 */
3860 smp_call_function_single(freq->cpu, bounce_off, NULL, 1);
3861 }
3862 return 0;
3863}
3864
3865static struct notifier_block kvmclock_cpufreq_notifier_block = {
3866 .notifier_call = kvmclock_cpufreq_notifier
3867};
3868
b820cc0c
ZA		 3869static void kvm_timer_init(void)
3870{
3871 int cpu;
3872
b820cc0c 3873 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
b820cc0c
ZA		 3874 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
3875 CPUFREQ_TRANSITION_NOTIFIER);
6b7d7e76
ZA		 3876 for_each_online_cpu(cpu) {
3877 unsigned long khz = cpufreq_get(cpu);
3878 if (!khz)
3879 khz = tsc_khz;
3880 per_cpu(cpu_tsc_khz, cpu) = khz;
3881 }
0cca7907
ZA		 3882 } else {
3883 for_each_possible_cpu(cpu)
3884 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
b820cc0c
ZA		 3885 }
3886}
3887
f8c16bba 3888int kvm_arch_init(void *opaque)
043405e1 3889{
b820cc0c 3890 int r;
f8c16bba
ZX		 3891 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
3892
f8c16bba
ZX		 3893 if (kvm_x86_ops) {
3894 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 3895 r = -EEXIST;
3896 goto out;
f8c16bba
ZX		 3897 }
3898
3899 if (!ops->cpu_has_kvm_support()) {
3900 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 3901 r = -EOPNOTSUPP;
3902 goto out;
f8c16bba
ZX		 3903 }
3904 if (ops->disabled_by_bios()) {
3905 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 3906 r = -EOPNOTSUPP;
3907 goto out;
f8c16bba
ZX		 3908 }
3909
97db56ce
AK		 3910 r = kvm_mmu_module_init();
3911 if (r)
3912 goto out;
3913
3914 kvm_init_msr_list();
3915
f8c16bba 3916 kvm_x86_ops = ops;
56c6d28a 3917 kvm_mmu_set_nonpresent_ptes(0ull, 0ull);
7b52345e
SY		 3918 kvm_mmu_set_base_ptes(PT_PRESENT_MASK);
3919 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 3920 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 3921
b820cc0c 3922 kvm_timer_init();
c8076604 3923
f8c16bba 3924 return 0;
56c6d28a
ZX		 3925
3926out:
56c6d28a 3927 return r;
043405e1 3928}
8776e519 3929
f8c16bba
ZX		 3930void kvm_arch_exit(void)
3931{
888d256e
JK		 3932 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
3933 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
3934 CPUFREQ_TRANSITION_NOTIFIER);
f8c16bba 3935 kvm_x86_ops = NULL;
56c6d28a
ZX		 3936 kvm_mmu_module_exit();
3937}
f8c16bba 3938
8776e519
HB		 3939int kvm_emulate_halt(struct kvm_vcpu *vcpu)
3940{
3941 ++vcpu->stat.halt_exits;
3942 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 3943 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 3944 return 1;
3945 } else {
3946 vcpu->run->exit_reason = KVM_EXIT_HLT;
3947 return 0;
3948 }
3949}
3950EXPORT_SYMBOL_GPL(kvm_emulate_halt);
3951
2f333bcb
MT		 3952static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0,
3953 unsigned long a1)
3954{
3955 if (is_long_mode(vcpu))
3956 return a0;
3957 else
3958 return a0 | ((gpa_t)a1 << 32);
3959}
3960
55cd8e5a
GN		 3961int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
3962{
3963 u64 param, ingpa, outgpa, ret;
3964 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
3965 bool fast, longmode;
3966 int cs_db, cs_l;
3967
3968 /*
3969 * hypercall generates UD from non zero cpl and real mode
3970 * per HYPER-V spec
3971 */
3eeb3288 3972 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 3973 kvm_queue_exception(vcpu, UD_VECTOR);
3974 return 0;
3975 }
3976
3977 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
3978 longmode = is_long_mode(vcpu) && cs_l == 1;
3979
3980 if (!longmode) {
ccd46936
GN		 3981 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
3982 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
3983 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
3984 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
3985 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
3986 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 3987 }
3988#ifdef CONFIG_X86_64
3989 else {
3990 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
3991 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
3992 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
3993 }
3994#endif
3995
3996 code = param & 0xffff;
3997 fast = (param >> 16) & 0x1;
3998 rep_cnt = (param >> 32) & 0xfff;
3999 rep_idx = (param >> 48) & 0xfff;
4000
4001 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
4002
c25bc163
GN		 4003 switch (code) {
4004 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
4005 kvm_vcpu_on_spin(vcpu);
4006 break;
4007 default:
4008 res = HV_STATUS_INVALID_HYPERCALL_CODE;
4009 break;
4010 }
55cd8e5a
GN		 4011
4012 ret = res | (((u64)rep_done & 0xfff) << 32);
4013 if (longmode) {
4014 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
4015 } else {
4016 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
4017 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
4018 }
4019
4020 return 1;
4021}
4022
8776e519
HB		 4023int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
4024{
4025 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 4026 int r = 1;
8776e519 4027
55cd8e5a
GN		 4028 if (kvm_hv_hypercall_enabled(vcpu->kvm))
4029 return kvm_hv_hypercall(vcpu);
4030
5fdbf976
MT		 4031 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
4032 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
4033 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
4034 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
4035 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 4036
229456fc 4037 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 4038
8776e519
HB		 4039 if (!is_long_mode(vcpu)) {
4040 nr &= 0xFFFFFFFF;
4041 a0 &= 0xFFFFFFFF;
4042 a1 &= 0xFFFFFFFF;
4043 a2 &= 0xFFFFFFFF;
4044 a3 &= 0xFFFFFFFF;
4045 }
4046
07708c4a
JK		 4047 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
4048 ret = -KVM_EPERM;
4049 goto out;
4050 }
4051
8776e519 4052 switch (nr) {
b93463aa
AK		 4053 case KVM_HC_VAPIC_POLL_IRQ:
4054 ret = 0;
4055 break;
2f333bcb
MT		 4056 case KVM_HC_MMU_OP:
4057 r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret);
4058 break;
8776e519
HB		 4059 default:
4060 ret = -KVM_ENOSYS;
4061 break;
4062 }
07708c4a 4063out:
5fdbf976 4064 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 4065 ++vcpu->stat.hypercalls;
2f333bcb 4066 return r;
8776e519
HB		 4067}
4068EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
4069
4070int kvm_fix_hypercall(struct kvm_vcpu *vcpu)
4071{
4072 char instruction[3];
5fdbf976 4073 unsigned long rip = kvm_rip_read(vcpu);
8776e519 4074
8776e519
HB		 4075 /*
4076 * Blow out the MMU to ensure that no other VCPU has an active mapping
4077 * to ensure that the updated hypercall appears atomically across all
4078 * VCPUs.
4079 */
4080 kvm_mmu_zap_all(vcpu->kvm);
4081
8776e519 4082 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 4083
4a5f48f6 4084 return __emulator_write_emulated(rip, instruction, 3, vcpu, false);
8776e519
HB		 4085}
4086
8776e519
HB		 4087void realmode_lgdt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
4088{
89a27f4d 4089 struct desc_ptr dt = { limit, base };
8776e519
HB		 4090
4091 kvm_x86_ops->set_gdt(vcpu, &dt);
4092}
4093
4094void realmode_lidt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
4095{
89a27f4d 4096 struct desc_ptr dt = { limit, base };
8776e519
HB		 4097
4098 kvm_x86_ops->set_idt(vcpu, &dt);
4099}
4100
07716717
DK		 4101static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)
4102{
ad312c7c
ZX		 4103 struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];
4104 int j, nent = vcpu->arch.cpuid_nent;
07716717
DK		 4105
4106 e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;
4107 /* when no next entry is found, the current entry[i] is reselected */
0fdf8e59 4108 for (j = i + 1; ; j = (j + 1) % nent) {
ad312c7c 4109 struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j];
07716717
DK		 4110 if (ej->function == e->function) {
4111 ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
4112 return j;
4113 }
4114 }
4115 return 0; /* silence gcc, even though control never reaches here */
4116}
4117
4118/* find an entry with matching function, matching index (if needed), and that
4119 * should be read next (if it's stateful) */
4120static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e,
4121 u32 function, u32 index)
4122{
4123 if (e->function != function)
4124 return 0;
4125 if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index)
4126 return 0;
4127 if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) &&
19355475 4128 !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT))
07716717
DK		 4129 return 0;
4130 return 1;
4131}
4132
d8017474
AG		 4133struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
4134 u32 function, u32 index)
8776e519
HB		 4135{
4136 int i;
d8017474 4137 struct kvm_cpuid_entry2 *best = NULL;
8776e519 4138
ad312c7c 4139 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
d8017474
AG		 4140 struct kvm_cpuid_entry2 *e;
4141
ad312c7c 4142 e = &vcpu->arch.cpuid_entries[i];
07716717
DK		 4143 if (is_matching_cpuid_entry(e, function, index)) {
4144 if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC)
4145 move_to_next_stateful_cpuid_entry(vcpu, i);
8776e519
HB		 4146 best = e;
4147 break;
4148 }
4149 /*
4150 * Both basic or both extended?
4151 */
4152 if (((e->function ^ function) & 0x80000000) == 0)
4153 if (!best || e->function > best->function)
4154 best = e;
4155 }
d8017474
AG		 4156 return best;
4157}
0e851880 4158EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry);
d8017474 4159
82725b20
DE		 4160int cpuid_maxphyaddr(struct kvm_vcpu *vcpu)
4161{
4162 struct kvm_cpuid_entry2 *best;
4163
4164 best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0);
4165 if (best)
4166 return best->eax & 0xff;
4167 return 36;
4168}
4169
d8017474
AG		 4170void kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
4171{
4172 u32 function, index;
4173 struct kvm_cpuid_entry2 *best;
4174
4175 function = kvm_register_read(vcpu, VCPU_REGS_RAX);
4176 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
4177 kvm_register_write(vcpu, VCPU_REGS_RAX, 0);
4178 kvm_register_write(vcpu, VCPU_REGS_RBX, 0);
4179 kvm_register_write(vcpu, VCPU_REGS_RCX, 0);
4180 kvm_register_write(vcpu, VCPU_REGS_RDX, 0);
4181 best = kvm_find_cpuid_entry(vcpu, function, index);
8776e519 4182 if (best) {
5fdbf976
MT		 4183 kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax);
4184 kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx);
4185 kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx);
4186 kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx);
8776e519 4187 }
8776e519 4188 kvm_x86_ops->skip_emulated_instruction(vcpu);
229456fc
MT		 4189 trace_kvm_cpuid(function,
4190 kvm_register_read(vcpu, VCPU_REGS_RAX),
4191 kvm_register_read(vcpu, VCPU_REGS_RBX),
4192 kvm_register_read(vcpu, VCPU_REGS_RCX),
4193 kvm_register_read(vcpu, VCPU_REGS_RDX));
8776e519
HB		 4194}
4195EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
d0752060 4196
b6c7a5dc
HB		 4197/*
4198 * Check if userspace requested an interrupt window, and that the
4199 * interrupt window is open.
4200 *
4201 * No need to exit to userspace if we already have an interrupt queued.
4202 */
851ba692 4203static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 4204{
8061823a 4205 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 4206 vcpu->run->request_interrupt_window &&
5df56646 4207 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 4208}
4209
851ba692 4210static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 4211{
851ba692
AK		 4212 struct kvm_run *kvm_run = vcpu->run;
4213
91586a3b 4214 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 4215 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 4216 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 4217 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 4218 kvm_run->ready_for_interrupt_injection = 1;
4531220b 4219 else
b6c7a5dc 4220 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 4221 kvm_arch_interrupt_allowed(vcpu) &&
4222 !kvm_cpu_has_interrupt(vcpu) &&
4223 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 4224}
4225
b93463aa
AK		 4226static void vapic_enter(struct kvm_vcpu *vcpu)
4227{
4228 struct kvm_lapic *apic = vcpu->arch.apic;
4229 struct page *page;
4230
4231 if (!apic || !apic->vapic_addr)
4232 return;
4233
4234 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
72dc67a6
IE		 4235
4236 vcpu->arch.apic->vapic_page = page;
b93463aa
AK		 4237}
4238
4239static void vapic_exit(struct kvm_vcpu *vcpu)
4240{
4241 struct kvm_lapic *apic = vcpu->arch.apic;
f656ce01 4242 int idx;
b93463aa
AK		 4243
4244 if (!apic || !apic->vapic_addr)
4245 return;
4246
f656ce01 4247 idx = srcu_read_lock(&vcpu->kvm->srcu);
b93463aa
AK		 4248 kvm_release_page_dirty(apic->vapic_page);
4249 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f656ce01 4250 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 4251}
4252
95ba8273
GN		 4253static void update_cr8_intercept(struct kvm_vcpu *vcpu)
4254{
4255 int max_irr, tpr;
4256
4257 if (!kvm_x86_ops->update_cr8_intercept)
4258 return;
4259
88c808fd
AK		 4260 if (!vcpu->arch.apic)
4261 return;
4262
8db3baa2
GN		 4263 if (!vcpu->arch.apic->vapic_addr)
4264 max_irr = kvm_lapic_find_highest_irr(vcpu);
4265 else
4266 max_irr = -1;
95ba8273
GN		 4267
4268 if (max_irr != -1)
4269 max_irr >>= 4;
4270
4271 tpr = kvm_lapic_get_cr8(vcpu);
4272
4273 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
4274}
4275
851ba692 4276static void inject_pending_event(struct kvm_vcpu *vcpu)
95ba8273
GN		 4277{
4278 /* try to reinject previous events if any */
b59bb7bd 4279 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 4280 trace_kvm_inj_exception(vcpu->arch.exception.nr,
4281 vcpu->arch.exception.has_error_code,
4282 vcpu->arch.exception.error_code);
b59bb7bd
GN		 4283 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
4284 vcpu->arch.exception.has_error_code,
4285 vcpu->arch.exception.error_code);
4286 return;
4287 }
4288
95ba8273
GN		 4289 if (vcpu->arch.nmi_injected) {
4290 kvm_x86_ops->set_nmi(vcpu);
4291 return;
4292 }
4293
4294 if (vcpu->arch.interrupt.pending) {
66fd3f7f 4295 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 4296 return;
4297 }
4298
4299 /* try to inject new event if pending */
4300 if (vcpu->arch.nmi_pending) {
4301 if (kvm_x86_ops->nmi_allowed(vcpu)) {
4302 vcpu->arch.nmi_pending = false;
4303 vcpu->arch.nmi_injected = true;
4304 kvm_x86_ops->set_nmi(vcpu);
4305 }
4306 } else if (kvm_cpu_has_interrupt(vcpu)) {
4307 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 4308 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
4309 false);
4310 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 4311 }
4312 }
4313}
4314
851ba692 4315static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 4316{
4317 int r;
6a8b1d13 4318 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 4319 vcpu->run->request_interrupt_window;
b6c7a5dc 4320
2e53d63a
MT		 4321 if (vcpu->requests)
4322 if (test_and_clear_bit(KVM_REQ_MMU_RELOAD, &vcpu->requests))
4323 kvm_mmu_unload(vcpu);
4324
b6c7a5dc
HB		 4325 r = kvm_mmu_reload(vcpu);
4326 if (unlikely(r))
4327 goto out;
4328
2f52d58c
AK		 4329 if (vcpu->requests) {
4330 if (test_and_clear_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests))
2f599714 4331 __kvm_migrate_timers(vcpu);
c8076604
GH		 4332 if (test_and_clear_bit(KVM_REQ_KVMCLOCK_UPDATE, &vcpu->requests))
4333 kvm_write_guest_time(vcpu);
4731d4c7
MT		 4334 if (test_and_clear_bit(KVM_REQ_MMU_SYNC, &vcpu->requests))
4335 kvm_mmu_sync_roots(vcpu);
d4acf7e7
MT		 4336 if (test_and_clear_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests))
4337 kvm_x86_ops->tlb_flush(vcpu);
b93463aa
AK		 4338 if (test_and_clear_bit(KVM_REQ_REPORT_TPR_ACCESS,
4339 &vcpu->requests)) {
851ba692 4340 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 4341 r = 0;
4342 goto out;
4343 }
71c4dfaf 4344 if (test_and_clear_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests)) {
851ba692 4345 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 4346 r = 0;
4347 goto out;
4348 }
02daab21
AK		 4349 if (test_and_clear_bit(KVM_REQ_DEACTIVATE_FPU, &vcpu->requests)) {
4350 vcpu->fpu_active = 0;
4351 kvm_x86_ops->fpu_deactivate(vcpu);
4352 }
2f52d58c 4353 }
b93463aa 4354
b6c7a5dc
HB		 4355 preempt_disable();
4356
4357 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 4358 if (vcpu->fpu_active)
4359 kvm_load_guest_fpu(vcpu);
b6c7a5dc
HB		 4360
4361 local_irq_disable();
4362
32f88400
MT		 4363 clear_bit(KVM_REQ_KICK, &vcpu->requests);
4364 smp_mb__after_clear_bit();
4365
d7690175 4366 if (vcpu->requests || need_resched() || signal_pending(current)) {
c7f0f24b 4367 set_bit(KVM_REQ_KICK, &vcpu->requests);
6c142801
AK		 4368 local_irq_enable();
4369 preempt_enable();
4370 r = 1;
4371 goto out;
4372 }
4373
851ba692 4374 inject_pending_event(vcpu);
b6c7a5dc 4375
6a8b1d13
GN		 4376 /* enable NMI/IRQ window open exits if needed */
4377 if (vcpu->arch.nmi_pending)
4378 kvm_x86_ops->enable_nmi_window(vcpu);
4379 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
4380 kvm_x86_ops->enable_irq_window(vcpu);
4381
95ba8273 4382 if (kvm_lapic_enabled(vcpu)) {
8db3baa2
GN		 4383 update_cr8_intercept(vcpu);
4384 kvm_lapic_sync_to_vapic(vcpu);
95ba8273 4385 }
b93463aa 4386
f656ce01 4387 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
3200f405 4388
b6c7a5dc
HB		 4389 kvm_guest_enter();
4390
42dbaa5a 4391 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 4392 set_debugreg(0, 7);
4393 set_debugreg(vcpu->arch.eff_db[0], 0);
4394 set_debugreg(vcpu->arch.eff_db[1], 1);
4395 set_debugreg(vcpu->arch.eff_db[2], 2);
4396 set_debugreg(vcpu->arch.eff_db[3], 3);
4397 }
b6c7a5dc 4398
229456fc 4399 trace_kvm_entry(vcpu->vcpu_id);
851ba692 4400 kvm_x86_ops->run(vcpu);
b6c7a5dc 4401
24f1e32c
FW		 4402 /*
4403 * If the guest has used debug registers, at least dr7
4404 * will be disabled while returning to the host.
4405 * If we don't have active breakpoints in the host, we don't
4406 * care about the messed up debug address registers. But if
4407 * we have some of them active, restore the old state.
4408 */
59d8eb53 4409 if (hw_breakpoint_active())
24f1e32c 4410 hw_breakpoint_restore();
42dbaa5a 4411
32f88400 4412 set_bit(KVM_REQ_KICK, &vcpu->requests);
b6c7a5dc
HB		 4413 local_irq_enable();
4414
4415 ++vcpu->stat.exits;
4416
4417 /*
4418 * We must have an instruction between local_irq_enable() and
4419 * kvm_guest_exit(), so the timer interrupt isn't delayed by
4420 * the interrupt shadow. The stat.exits increment will do nicely.
4421 * But we need to prevent reordering, hence this barrier():
4422 */
4423 barrier();
4424
4425 kvm_guest_exit();
4426
4427 preempt_enable();
4428
f656ce01 4429 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 4430
b6c7a5dc
HB		 4431 /*
4432 * Profile KVM exit RIPs:
4433 */
4434 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 4435 unsigned long rip = kvm_rip_read(vcpu);
4436 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 4437 }
4438
298101da 4439
b93463aa
AK		 4440 kvm_lapic_sync_from_vapic(vcpu);
4441
851ba692 4442 r = kvm_x86_ops->handle_exit(vcpu);
d7690175
MT		 4443out:
4444 return r;
4445}
b6c7a5dc 4446
09cec754 4447
851ba692 4448static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 4449{
4450 int r;
f656ce01 4451 struct kvm *kvm = vcpu->kvm;
d7690175
MT		 4452
4453 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
1b10bf31
JK		 4454 pr_debug("vcpu %d received sipi with vector # %x\n",
4455 vcpu->vcpu_id, vcpu->arch.sipi_vector);
d7690175 4456 kvm_lapic_reset(vcpu);
5f179287 4457 r = kvm_arch_vcpu_reset(vcpu);
d7690175
MT		 4458 if (r)
4459 return r;
4460 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 4461 }
4462
f656ce01 4463 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175
MT		 4464 vapic_enter(vcpu);
4465
4466 r = 1;
4467 while (r > 0) {
af2152f5 4468 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE)
851ba692 4469 r = vcpu_enter_guest(vcpu);
d7690175 4470 else {
f656ce01 4471 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 4472 kvm_vcpu_block(vcpu);
f656ce01 4473 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 4474 if (test_and_clear_bit(KVM_REQ_UNHALT, &vcpu->requests))
09cec754
GN		 4475 {
4476 switch(vcpu->arch.mp_state) {
4477 case KVM_MP_STATE_HALTED:
d7690175 4478 vcpu->arch.mp_state =
09cec754
GN		 4479 KVM_MP_STATE_RUNNABLE;
4480 case KVM_MP_STATE_RUNNABLE:
4481 break;
4482 case KVM_MP_STATE_SIPI_RECEIVED:
4483 default:
4484 r = -EINTR;
4485 break;
4486 }
4487 }
d7690175
MT		 4488 }
4489
09cec754
GN		 4490 if (r <= 0)
4491 break;
4492
4493 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
4494 if (kvm_cpu_has_pending_timer(vcpu))
4495 kvm_inject_pending_timer_irqs(vcpu);
4496
851ba692 4497 if (dm_request_for_irq_injection(vcpu)) {
09cec754 4498 r = -EINTR;
851ba692 4499 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 4500 ++vcpu->stat.request_irq_exits;
4501 }
4502 if (signal_pending(current)) {
4503 r = -EINTR;
851ba692 4504 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 4505 ++vcpu->stat.signal_exits;
4506 }
4507 if (need_resched()) {
f656ce01 4508 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
09cec754 4509 kvm_resched(vcpu);
f656ce01 4510 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 4511 }
b6c7a5dc
HB		 4512 }
4513
f656ce01 4514 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
851ba692 4515 post_kvm_run_save(vcpu);
b6c7a5dc 4516
b93463aa
AK		 4517 vapic_exit(vcpu);
4518
b6c7a5dc
HB		 4519 return r;
4520}
4521
4522int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
4523{
4524 int r;
4525 sigset_t sigsaved;
4526
4527 vcpu_load(vcpu);
4528
ac9f6dc0
AK		 4529 if (vcpu->sigset_active)
4530 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
4531
a4535290 4532 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 4533 kvm_vcpu_block(vcpu);
d7690175 4534 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 4535 r = -EAGAIN;
4536 goto out;
b6c7a5dc
HB		 4537 }
4538
b6c7a5dc
HB		 4539 /* re-sync apic's tpr */
4540 if (!irqchip_in_kernel(vcpu->kvm))
2d3ad1f4 4541 kvm_set_cr8(vcpu, kvm_run->cr8);
b6c7a5dc 4542
ad312c7c 4543 if (vcpu->arch.pio.cur_count) {
7567cae1 4544 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
b6c7a5dc 4545 r = complete_pio(vcpu);
7567cae1 4546 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 4547 if (r)
4548 goto out;
4549 }
b6c7a5dc
HB		 4550 if (vcpu->mmio_needed) {
4551 memcpy(vcpu->mmio_data, kvm_run->mmio.data, 8);
4552 vcpu->mmio_read_completed = 1;
4553 vcpu->mmio_needed = 0;
3200f405 4554
f656ce01 4555 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
851ba692 4556 r = emulate_instruction(vcpu, vcpu->arch.mmio_fault_cr2, 0,
571008da 4557 EMULTYPE_NO_DECODE);
f656ce01 4558 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 4559 if (r == EMULATE_DO_MMIO) {
4560 /*
4561 * Read-modify-write. Back to userspace.
4562 */
4563 r = 0;
4564 goto out;
4565 }
4566 }
5fdbf976
MT		 4567 if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL)
4568 kvm_register_write(vcpu, VCPU_REGS_RAX,
4569 kvm_run->hypercall.ret);
b6c7a5dc 4570
851ba692 4571 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 4572
4573out:
4574 if (vcpu->sigset_active)
4575 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
4576
4577 vcpu_put(vcpu);
4578 return r;
4579}
4580
4581int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
4582{
4583 vcpu_load(vcpu);
4584
5fdbf976
MT		 4585 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
4586 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
4587 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
4588 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
4589 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
4590 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
4591 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
4592 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 4593#ifdef CONFIG_X86_64
5fdbf976
MT		 4594 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
4595 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
4596 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
4597 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
4598 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
4599 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
4600 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
4601 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 4602#endif
4603
5fdbf976 4604 regs->rip = kvm_rip_read(vcpu);
91586a3b 4605 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc
HB		 4606
4607 vcpu_put(vcpu);
4608
4609 return 0;
4610}
4611
4612int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
4613{
4614 vcpu_load(vcpu);
4615
5fdbf976
MT		 4616 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
4617 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
4618 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
4619 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
4620 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
4621 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
4622 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
4623 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 4624#ifdef CONFIG_X86_64
5fdbf976
MT		 4625 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
4626 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
4627 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
4628 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
4629 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
4630 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
4631 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
4632 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 4633#endif
4634
5fdbf976 4635 kvm_rip_write(vcpu, regs->rip);
91586a3b 4636 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 4637
b4f14abd
JK		 4638 vcpu->arch.exception.pending = false;
4639
b6c7a5dc
HB		 4640 vcpu_put(vcpu);
4641
4642 return 0;
4643}
4644
3e6e0aab
GT		 4645void kvm_get_segment(struct kvm_vcpu *vcpu,
4646 struct kvm_segment *var, int seg)
b6c7a5dc 4647{
14af3f3c 4648 kvm_x86_ops->get_segment(vcpu, var, seg);
b6c7a5dc
HB		 4649}
4650
4651void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
4652{
4653 struct kvm_segment cs;
4654
3e6e0aab 4655 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 4656 *db = cs.db;
4657 *l = cs.l;
4658}
4659EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
4660
4661int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
4662 struct kvm_sregs *sregs)
4663{
89a27f4d 4664 struct desc_ptr dt;
b6c7a5dc
HB		 4665
4666 vcpu_load(vcpu);
4667
3e6e0aab
GT		 4668 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
4669 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
4670 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
4671 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
4672 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
4673 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 4674
3e6e0aab
GT		 4675 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
4676 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 4677
4678 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 4679 sregs->idt.limit = dt.size;
4680 sregs->idt.base = dt.address;
b6c7a5dc 4681 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 4682 sregs->gdt.limit = dt.size;
4683 sregs->gdt.base = dt.address;
b6c7a5dc 4684
4d4ec087 4685 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c
ZX		 4686 sregs->cr2 = vcpu->arch.cr2;
4687 sregs->cr3 = vcpu->arch.cr3;
fc78f519 4688 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 4689 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 4690 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 4691 sregs->apic_base = kvm_get_apic_base(vcpu);
4692
923c61bb 4693 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 4694
36752c9b 4695 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 4696 set_bit(vcpu->arch.interrupt.nr,
4697 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 4698
b6c7a5dc
HB		 4699 vcpu_put(vcpu);
4700
4701 return 0;
4702}
4703
62d9f0db
MT		 4704int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
4705 struct kvm_mp_state *mp_state)
4706{
4707 vcpu_load(vcpu);
4708 mp_state->mp_state = vcpu->arch.mp_state;
4709 vcpu_put(vcpu);
4710 return 0;
4711}
4712
4713int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
4714 struct kvm_mp_state *mp_state)
4715{
4716 vcpu_load(vcpu);
4717 vcpu->arch.mp_state = mp_state->mp_state;
4718 vcpu_put(vcpu);
4719 return 0;
4720}
4721
3e6e0aab 4722static void kvm_set_segment(struct kvm_vcpu *vcpu,
b6c7a5dc
HB		 4723 struct kvm_segment *var, int seg)
4724{
14af3f3c 4725 kvm_x86_ops->set_segment(vcpu, var, seg);
b6c7a5dc
HB		 4726}
4727
37817f29
IE		 4728static void seg_desct_to_kvm_desct(struct desc_struct *seg_desc, u16 selector,
4729 struct kvm_segment *kvm_desct)
4730{
46a359e7
AM		 4731 kvm_desct->base = get_desc_base(seg_desc);
4732 kvm_desct->limit = get_desc_limit(seg_desc);
c93cd3a5
MT		 4733 if (seg_desc->g) {
4734 kvm_desct->limit <<= 12;
4735 kvm_desct->limit |= 0xfff;
4736 }
37817f29
IE		 4737 kvm_desct->selector = selector;
4738 kvm_desct->type = seg_desc->type;
4739 kvm_desct->present = seg_desc->p;
4740 kvm_desct->dpl = seg_desc->dpl;
4741 kvm_desct->db = seg_desc->d;
4742 kvm_desct->s = seg_desc->s;
4743 kvm_desct->l = seg_desc->l;
4744 kvm_desct->g = seg_desc->g;
4745 kvm_desct->avl = seg_desc->avl;
4746 if (!selector)
4747 kvm_desct->unusable = 1;
4748 else
4749 kvm_desct->unusable = 0;
4750 kvm_desct->padding = 0;
4751}
4752
b8222ad2
AS		 4753static void get_segment_descriptor_dtable(struct kvm_vcpu *vcpu,
4754 u16 selector,
89a27f4d 4755 struct desc_ptr *dtable)
37817f29
IE		 4756{
4757 if (selector & 1 << 2) {
4758 struct kvm_segment kvm_seg;
4759
3e6e0aab 4760 kvm_get_segment(vcpu, &kvm_seg, VCPU_SREG_LDTR);
37817f29
IE		 4761
4762 if (kvm_seg.unusable)
89a27f4d 4763 dtable->size = 0;
37817f29 4764 else
89a27f4d
GN		 4765 dtable->size = kvm_seg.limit;
4766 dtable->address = kvm_seg.base;
37817f29
IE		 4767 }
4768 else
4769 kvm_x86_ops->get_gdt(vcpu, dtable);
4770}
4771
4772/* allowed just for 8 bytes segments */
4773static int load_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
4774 struct desc_struct *seg_desc)
4775{
89a27f4d 4776 struct desc_ptr dtable;
37817f29 4777 u16 index = selector >> 3;
6f550484
TY		 4778 int ret;
4779 u32 err;
4780 gva_t addr;
37817f29 4781
b8222ad2 4782 get_segment_descriptor_dtable(vcpu, selector, &dtable);
37817f29 4783
89a27f4d 4784 if (dtable.size < index * 8 + 7) {
37817f29 4785 kvm_queue_exception_e(vcpu, GP_VECTOR, selector & 0xfffc);
c125c607 4786 return X86EMUL_PROPAGATE_FAULT;
37817f29 4787 }
6f550484
TY		 4788 addr = dtable.base + index * 8;
4789 ret = kvm_read_guest_virt_system(addr, seg_desc, sizeof(*seg_desc),
4790 vcpu, &err);
4791 if (ret == X86EMUL_PROPAGATE_FAULT)
4792 kvm_inject_page_fault(vcpu, addr, err);
4793
4794 return ret;
37817f29
IE		 4795}
4796
4797/* allowed just for 8 bytes segments */
4798static int save_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
4799 struct desc_struct *seg_desc)
4800{
89a27f4d 4801 struct desc_ptr dtable;
37817f29
IE		 4802 u16 index = selector >> 3;
4803
b8222ad2 4804 get_segment_descriptor_dtable(vcpu, selector, &dtable);
37817f29 4805
89a27f4d 4806 if (dtable.size < index * 8 + 7)
37817f29 4807 return 1;
89a27f4d 4808 return kvm_write_guest_virt(dtable.address + index*8, seg_desc, sizeof(*seg_desc), vcpu, NULL);
1871c602
GN		 4809}
4810
4811static gpa_t get_tss_base_addr_write(struct kvm_vcpu *vcpu,
4812 struct desc_struct *seg_desc)
4813{
4814 u32 base_addr = get_desc_base(seg_desc);
4815
4816 return kvm_mmu_gva_to_gpa_write(vcpu, base_addr, NULL);
37817f29
IE		 4817}
4818
1871c602 4819static gpa_t get_tss_base_addr_read(struct kvm_vcpu *vcpu,
37817f29
IE		 4820 struct desc_struct *seg_desc)
4821{
46a359e7 4822 u32 base_addr = get_desc_base(seg_desc);
37817f29 4823
1871c602 4824 return kvm_mmu_gva_to_gpa_read(vcpu, base_addr, NULL);
37817f29
IE		 4825}
4826
37817f29
IE		 4827static u16 get_segment_selector(struct kvm_vcpu *vcpu, int seg)
4828{
4829 struct kvm_segment kvm_seg;
4830
3e6e0aab 4831 kvm_get_segment(vcpu, &kvm_seg, seg);
37817f29
IE		 4832 return kvm_seg.selector;
4833}
4834
2259e3a7 4835static int kvm_load_realmode_segment(struct kvm_vcpu *vcpu, u16 selector, int seg)
f4bbd9aa
AK		 4836{
4837 struct kvm_segment segvar = {
4838 .base = selector << 4,
4839 .limit = 0xffff,
4840 .selector = selector,
4841 .type = 3,
4842 .present = 1,
4843 .dpl = 3,
4844 .db = 0,
4845 .s = 1,
4846 .l = 0,
4847 .g = 0,
4848 .avl = 0,
4849 .unusable = 0,
4850 };
4851 kvm_x86_ops->set_segment(vcpu, &segvar, seg);
c697518a 4852 return X86EMUL_CONTINUE;
f4bbd9aa
AK		 4853}
4854
c0c7c04b
AL		 4855static int is_vm86_segment(struct kvm_vcpu *vcpu, int seg)
4856{
4857 return (seg != VCPU_SREG_LDTR) &&
4858 (seg != VCPU_SREG_TR) &&
91586a3b 4859 (kvm_get_rflags(vcpu) & X86_EFLAGS_VM);
c0c7c04b
AL		 4860}
4861
c697518a 4862int kvm_load_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector, int seg)
37817f29
IE		 4863{
4864 struct kvm_segment kvm_seg;
e01c2426 4865 struct desc_struct seg_desc;
c697518a
GN		 4866 u8 dpl, rpl, cpl;
4867 unsigned err_vec = GP_VECTOR;
4868 u32 err_code = 0;
4869 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
4870 int ret;
37817f29 4871
3eeb3288 4872 if (is_vm86_segment(vcpu, seg) || !is_protmode(vcpu))
f4bbd9aa 4873 return kvm_load_realmode_segment(vcpu, selector, seg);
e01c2426 4874
c697518a
GN		 4875 /* NULL selector is not valid for TR, CS and SS */
4876 if ((seg == VCPU_SREG_CS || seg == VCPU_SREG_SS || seg == VCPU_SREG_TR)
4877 && null_selector)
4878 goto exception;
4879
4880 /* TR should be in GDT only */
4881 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
4882 goto exception;
4883
4884 ret = load_guest_segment_descriptor(vcpu, selector, &seg_desc);
4885 if (ret)
4886 return ret;
4887
e01c2426 4888 seg_desct_to_kvm_desct(&seg_desc, selector, &kvm_seg);
cb84b55f 4889
c697518a
GN		 4890 if (null_selector) { /* for NULL selector skip all following checks */
4891 kvm_seg.unusable = 1;
4892 goto load;
4893 }
37817f29 4894
c697518a
GN		 4895 err_code = selector & 0xfffc;
4896 err_vec = GP_VECTOR;
37817f29 4897
c697518a
GN		 4898 /* can't load system descriptor into segment selecor */
4899 if (seg <= VCPU_SREG_GS && !kvm_seg.s)
4900 goto exception;
4901
4902 if (!kvm_seg.present) {
4903 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
4904 goto exception;
4905 }
4906
4907 rpl = selector & 3;
4908 dpl = kvm_seg.dpl;
4909 cpl = kvm_x86_ops->get_cpl(vcpu);
4910
4911 switch (seg) {
4912 case VCPU_SREG_SS:
4913 /*
4914 * segment is not a writable data segment or segment
4915 * selector's RPL != CPL or segment selector's RPL != CPL
4916 */
4917 if (rpl != cpl || (kvm_seg.type & 0xa) != 0x2 || dpl != cpl)
4918 goto exception;
4919 break;
4920 case VCPU_SREG_CS:
4921 if (!(kvm_seg.type & 8))
4922 goto exception;
4923
4924 if (kvm_seg.type & 4) {
4925 /* conforming */
4926 if (dpl > cpl)
4927 goto exception;
4928 } else {
4929 /* nonconforming */
4930 if (rpl > cpl || dpl != cpl)
4931 goto exception;
4932 }
4933 /* CS(RPL) <- CPL */
4934 selector = (selector & 0xfffc) | cpl;
4935 break;
4936 case VCPU_SREG_TR:
4937 if (kvm_seg.s || (kvm_seg.type != 1 && kvm_seg.type != 9))
4938 goto exception;
4939 break;
4940 case VCPU_SREG_LDTR:
4941 if (kvm_seg.s || kvm_seg.type != 2)
4942 goto exception;
4943 break;
4944 default: /* DS, ES, FS, or GS */
4945 /*
4946 * segment is not a data or readable code segment or
4947 * ((segment is a data or nonconforming code segment)
4948 * and (both RPL and CPL > DPL))
4949 */
4950 if ((kvm_seg.type & 0xa) == 0x8 ||
4951 (((kvm_seg.type & 0xc) != 0xc) && (rpl > dpl && cpl > dpl)))
4952 goto exception;
4953 break;
4954 }
4955
4956 if (!kvm_seg.unusable && kvm_seg.s) {
e01c2426 4957 /* mark segment as accessed */
c697518a 4958 kvm_seg.type |= 1;
e01c2426
GN		 4959 seg_desc.type |= 1;
4960 save_guest_segment_descriptor(vcpu, selector, &seg_desc);
4961 }
c697518a
GN		 4962load:
4963 kvm_set_segment(vcpu, &kvm_seg, seg);
4964 return X86EMUL_CONTINUE;
4965exception:
4966 kvm_queue_exception_e(vcpu, err_vec, err_code);
4967 return X86EMUL_PROPAGATE_FAULT;
37817f29
IE		 4968}
4969
4970static void save_state_to_tss32(struct kvm_vcpu *vcpu,
4971 struct tss_segment_32 *tss)
4972{
4973 tss->cr3 = vcpu->arch.cr3;
5fdbf976 4974 tss->eip = kvm_rip_read(vcpu);
91586a3b 4975 tss->eflags = kvm_get_rflags(vcpu);
5fdbf976
MT		 4976 tss->eax = kvm_register_read(vcpu, VCPU_REGS_RAX);
4977 tss->ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
4978 tss->edx = kvm_register_read(vcpu, VCPU_REGS_RDX);
4979 tss->ebx = kvm_register_read(vcpu, VCPU_REGS_RBX);
4980 tss->esp = kvm_register_read(vcpu, VCPU_REGS_RSP);
4981 tss->ebp = kvm_register_read(vcpu, VCPU_REGS_RBP);
4982 tss->esi = kvm_register_read(vcpu, VCPU_REGS_RSI);
4983 tss->edi = kvm_register_read(vcpu, VCPU_REGS_RDI);
37817f29
IE		 4984 tss->es = get_segment_selector(vcpu, VCPU_SREG_ES);
4985 tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS);
4986 tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS);
4987 tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS);
4988 tss->fs = get_segment_selector(vcpu, VCPU_SREG_FS);
4989 tss->gs = get_segment_selector(vcpu, VCPU_SREG_GS);
4990 tss->ldt_selector = get_segment_selector(vcpu, VCPU_SREG_LDTR);
37817f29
IE		 4991}
4992
c697518a
GN		 4993static void kvm_load_segment_selector(struct kvm_vcpu *vcpu, u16 sel, int seg)
4994{
4995 struct kvm_segment kvm_seg;
4996 kvm_get_segment(vcpu, &kvm_seg, seg);
4997 kvm_seg.selector = sel;
4998 kvm_set_segment(vcpu, &kvm_seg, seg);
4999}
5000
37817f29
IE		 5001static int load_state_from_tss32(struct kvm_vcpu *vcpu,
5002 struct tss_segment_32 *tss)
5003{
5004 kvm_set_cr3(vcpu, tss->cr3);
5005
5fdbf976 5006 kvm_rip_write(vcpu, tss->eip);
91586a3b 5007 kvm_set_rflags(vcpu, tss->eflags | 2);
37817f29 5008
5fdbf976
MT		 5009 kvm_register_write(vcpu, VCPU_REGS_RAX, tss->eax);
5010 kvm_register_write(vcpu, VCPU_REGS_RCX, tss->ecx);
5011 kvm_register_write(vcpu, VCPU_REGS_RDX, tss->edx);
5012 kvm_register_write(vcpu, VCPU_REGS_RBX, tss->ebx);
5013 kvm_register_write(vcpu, VCPU_REGS_RSP, tss->esp);
5014 kvm_register_write(vcpu, VCPU_REGS_RBP, tss->ebp);
5015 kvm_register_write(vcpu, VCPU_REGS_RSI, tss->esi);
5016 kvm_register_write(vcpu, VCPU_REGS_RDI, tss->edi);
37817f29 5017
c697518a
GN		 5018 /*
5019 * SDM says that segment selectors are loaded before segment
5020 * descriptors
5021 */
5022 kvm_load_segment_selector(vcpu, tss->ldt_selector, VCPU_SREG_LDTR);
5023 kvm_load_segment_selector(vcpu, tss->es, VCPU_SREG_ES);
5024 kvm_load_segment_selector(vcpu, tss->cs, VCPU_SREG_CS);
5025 kvm_load_segment_selector(vcpu, tss->ss, VCPU_SREG_SS);
5026 kvm_load_segment_selector(vcpu, tss->ds, VCPU_SREG_DS);
5027 kvm_load_segment_selector(vcpu, tss->fs, VCPU_SREG_FS);
5028 kvm_load_segment_selector(vcpu, tss->gs, VCPU_SREG_GS);
5029
5030 /*
5031 * Now load segment descriptors. If fault happenes at this stage
5032 * it is handled in a context of new task
5033 */
5034 if (kvm_load_segment_descriptor(vcpu, tss->ldt_selector, VCPU_SREG_LDTR))
37817f29
IE		 5035 return 1;
5036
c697518a 5037 if (kvm_load_segment_descriptor(vcpu, tss->es, VCPU_SREG_ES))
37817f29
IE		 5038 return 1;
5039
c697518a 5040 if (kvm_load_segment_descriptor(vcpu, tss->cs, VCPU_SREG_CS))
37817f29
IE		 5041 return 1;
5042
c697518a 5043 if (kvm_load_segment_descriptor(vcpu, tss->ss, VCPU_SREG_SS))
37817f29
IE		 5044 return 1;
5045
c697518a 5046 if (kvm_load_segment_descriptor(vcpu, tss->ds, VCPU_SREG_DS))
37817f29
IE		 5047 return 1;
5048
c697518a 5049 if (kvm_load_segment_descriptor(vcpu, tss->fs, VCPU_SREG_FS))
37817f29
IE		 5050 return 1;
5051
c697518a 5052 if (kvm_load_segment_descriptor(vcpu, tss->gs, VCPU_SREG_GS))
37817f29
IE		 5053 return 1;
5054 return 0;
5055}
5056
5057static void save_state_to_tss16(struct kvm_vcpu *vcpu,
5058 struct tss_segment_16 *tss)
5059{
5fdbf976 5060 tss->ip = kvm_rip_read(vcpu);
91586a3b 5061 tss->flag = kvm_get_rflags(vcpu);
5fdbf976
MT		 5062 tss->ax = kvm_register_read(vcpu, VCPU_REGS_RAX);
5063 tss->cx = kvm_register_read(vcpu, VCPU_REGS_RCX);
5064 tss->dx = kvm_register_read(vcpu, VCPU_REGS_RDX);
5065 tss->bx = kvm_register_read(vcpu, VCPU_REGS_RBX);
5066 tss->sp = kvm_register_read(vcpu, VCPU_REGS_RSP);
5067 tss->bp = kvm_register_read(vcpu, VCPU_REGS_RBP);
5068 tss->si = kvm_register_read(vcpu, VCPU_REGS_RSI);
5069 tss->di = kvm_register_read(vcpu, VCPU_REGS_RDI);
37817f29
IE		 5070
5071 tss->es = get_segment_selector(vcpu, VCPU_SREG_ES);
5072 tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS);
5073 tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS);
5074 tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS);
5075 tss->ldt = get_segment_selector(vcpu, VCPU_SREG_LDTR);
37817f29
IE		 5076}
5077
5078static int load_state_from_tss16(struct kvm_vcpu *vcpu,
5079 struct tss_segment_16 *tss)
5080{
5fdbf976 5081 kvm_rip_write(vcpu, tss->ip);
91586a3b 5082 kvm_set_rflags(vcpu, tss->flag | 2);
5fdbf976
MT		 5083 kvm_register_write(vcpu, VCPU_REGS_RAX, tss->ax);
5084 kvm_register_write(vcpu, VCPU_REGS_RCX, tss->cx);
5085 kvm_register_write(vcpu, VCPU_REGS_RDX, tss->dx);
5086 kvm_register_write(vcpu, VCPU_REGS_RBX, tss->bx);
5087 kvm_register_write(vcpu, VCPU_REGS_RSP, tss->sp);
5088 kvm_register_write(vcpu, VCPU_REGS_RBP, tss->bp);
5089 kvm_register_write(vcpu, VCPU_REGS_RSI, tss->si);
5090 kvm_register_write(vcpu, VCPU_REGS_RDI, tss->di);
37817f29 5091
c697518a
GN		 5092 /*
5093 * SDM says that segment selectors are loaded before segment
5094 * descriptors
5095 */
5096 kvm_load_segment_selector(vcpu, tss->ldt, VCPU_SREG_LDTR);
5097 kvm_load_segment_selector(vcpu, tss->es, VCPU_SREG_ES);
5098 kvm_load_segment_selector(vcpu, tss->cs, VCPU_SREG_CS);
5099 kvm_load_segment_selector(vcpu, tss->ss, VCPU_SREG_SS);
5100 kvm_load_segment_selector(vcpu, tss->ds, VCPU_SREG_DS);
5101
5102 /*
5103 * Now load segment descriptors. If fault happenes at this stage
5104 * it is handled in a context of new task
5105 */
5106 if (kvm_load_segment_descriptor(vcpu, tss->ldt, VCPU_SREG_LDTR))
37817f29
IE		 5107 return 1;
5108
c697518a 5109 if (kvm_load_segment_descriptor(vcpu, tss->es, VCPU_SREG_ES))
37817f29
IE		 5110 return 1;
5111
c697518a 5112 if (kvm_load_segment_descriptor(vcpu, tss->cs, VCPU_SREG_CS))
37817f29
IE		 5113 return 1;
5114
c697518a 5115 if (kvm_load_segment_descriptor(vcpu, tss->ss, VCPU_SREG_SS))
37817f29
IE		 5116 return 1;
5117
c697518a 5118 if (kvm_load_segment_descriptor(vcpu, tss->ds, VCPU_SREG_DS))
37817f29
IE		 5119 return 1;
5120 return 0;
5121}
5122
8b2cf73c 5123static int kvm_task_switch_16(struct kvm_vcpu *vcpu, u16 tss_selector,
b237ac37
GN		 5124 u16 old_tss_sel, u32 old_tss_base,
5125 struct desc_struct *nseg_desc)
37817f29
IE		 5126{
5127 struct tss_segment_16 tss_segment_16;
5128 int ret = 0;
5129
34198bf8
MT		 5130 if (kvm_read_guest(vcpu->kvm, old_tss_base, &tss_segment_16,
5131 sizeof tss_segment_16))
37817f29
IE		 5132 goto out;
5133
5134 save_state_to_tss16(vcpu, &tss_segment_16);
37817f29 5135
34198bf8
MT		 5136 if (kvm_write_guest(vcpu->kvm, old_tss_base, &tss_segment_16,
5137 sizeof tss_segment_16))
37817f29 5138 goto out;
34198bf8 5139
1871c602 5140 if (kvm_read_guest(vcpu->kvm, get_tss_base_addr_read(vcpu, nseg_desc),
34198bf8
MT		 5141 &tss_segment_16, sizeof tss_segment_16))
5142 goto out;
5143
b237ac37
GN		 5144 if (old_tss_sel != 0xffff) {
5145 tss_segment_16.prev_task_link = old_tss_sel;
5146
5147 if (kvm_write_guest(vcpu->kvm,
1871c602 5148 get_tss_base_addr_write(vcpu, nseg_desc),
b237ac37
GN		 5149 &tss_segment_16.prev_task_link,
5150 sizeof tss_segment_16.prev_task_link))
5151 goto out;
5152 }
5153
37817f29
IE		 5154 if (load_state_from_tss16(vcpu, &tss_segment_16))
5155 goto out;
5156
5157 ret = 1;
5158out:
5159 return ret;
5160}
5161
8b2cf73c 5162static int kvm_task_switch_32(struct kvm_vcpu *vcpu, u16 tss_selector,
b237ac37 5163 u16 old_tss_sel, u32 old_tss_base,
37817f29
IE		 5164 struct desc_struct *nseg_desc)
5165{
5166 struct tss_segment_32 tss_segment_32;
5167 int ret = 0;
5168
34198bf8
MT		 5169 if (kvm_read_guest(vcpu->kvm, old_tss_base, &tss_segment_32,
5170 sizeof tss_segment_32))
37817f29
IE		 5171 goto out;
5172
5173 save_state_to_tss32(vcpu, &tss_segment_32);
37817f29 5174
34198bf8
MT		 5175 if (kvm_write_guest(vcpu->kvm, old_tss_base, &tss_segment_32,
5176 sizeof tss_segment_32))
5177 goto out;
5178
1871c602 5179 if (kvm_read_guest(vcpu->kvm, get_tss_base_addr_read(vcpu, nseg_desc),
34198bf8 5180 &tss_segment_32, sizeof tss_segment_32))
37817f29 5181 goto out;
34198bf8 5182
b237ac37
GN		 5183 if (old_tss_sel != 0xffff) {
5184 tss_segment_32.prev_task_link = old_tss_sel;
5185
5186 if (kvm_write_guest(vcpu->kvm,
1871c602 5187 get_tss_base_addr_write(vcpu, nseg_desc),
b237ac37
GN		 5188 &tss_segment_32.prev_task_link,
5189 sizeof tss_segment_32.prev_task_link))
5190 goto out;
5191 }
5192
37817f29
IE		 5193 if (load_state_from_tss32(vcpu, &tss_segment_32))
5194 goto out;
5195
5196 ret = 1;
5197out:
5198 return ret;
5199}
5200
5201int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason)
5202{
5203 struct kvm_segment tr_seg;
5204 struct desc_struct cseg_desc;
5205 struct desc_struct nseg_desc;
5206 int ret = 0;
34198bf8
MT		 5207 u32 old_tss_base = get_segment_base(vcpu, VCPU_SREG_TR);
5208 u16 old_tss_sel = get_segment_selector(vcpu, VCPU_SREG_TR);
e8861cfe 5209 u32 desc_limit;
37817f29 5210
1871c602 5211 old_tss_base = kvm_mmu_gva_to_gpa_write(vcpu, old_tss_base, NULL);
37817f29 5212
34198bf8
MT		 5213 /* FIXME: Handle errors. Failure to read either TSS or their
5214 * descriptors should generate a pagefault.
5215 */
37817f29
IE		 5216 if (load_guest_segment_descriptor(vcpu, tss_selector, &nseg_desc))
5217 goto out;
5218
34198bf8 5219 if (load_guest_segment_descriptor(vcpu, old_tss_sel, &cseg_desc))
37817f29
IE		 5220 goto out;
5221
37817f29
IE		 5222 if (reason != TASK_SWITCH_IRET) {
5223 int cpl;
5224
5225 cpl = kvm_x86_ops->get_cpl(vcpu);
5226 if ((tss_selector & 3) > nseg_desc.dpl || cpl > nseg_desc.dpl) {
5227 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
5228 return 1;
5229 }
5230 }
5231
e8861cfe
JK		 5232 desc_limit = get_desc_limit(&nseg_desc);
5233 if (!nseg_desc.p ||
5234 ((desc_limit < 0x67 && (nseg_desc.type & 8)) ||
5235 desc_limit < 0x2b)) {
37817f29
IE		 5236 kvm_queue_exception_e(vcpu, TS_VECTOR, tss_selector & 0xfffc);
5237 return 1;
5238 }
5239
5240 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
3fe913e7 5241 cseg_desc.type &= ~(1 << 1); //clear the B flag
34198bf8 5242 save_guest_segment_descriptor(vcpu, old_tss_sel, &cseg_desc);
37817f29
IE		 5243 }
5244
5245 if (reason == TASK_SWITCH_IRET) {
91586a3b
JK		 5246 u32 eflags = kvm_get_rflags(vcpu);
5247 kvm_set_rflags(vcpu, eflags & ~X86_EFLAGS_NT);
37817f29
IE		 5248 }
5249
b237ac37
GN		 5250 /* set back link to prev task only if NT bit is set in eflags
5251 note that old_tss_sel is not used afetr this point */
5252 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
5253 old_tss_sel = 0xffff;
5254
37817f29 5255 if (nseg_desc.type & 8)
b237ac37
GN		 5256 ret = kvm_task_switch_32(vcpu, tss_selector, old_tss_sel,
5257 old_tss_base, &nseg_desc);
37817f29 5258 else
b237ac37
GN		 5259 ret = kvm_task_switch_16(vcpu, tss_selector, old_tss_sel,
5260 old_tss_base, &nseg_desc);
37817f29
IE		 5261
5262 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE) {
91586a3b
JK		 5263 u32 eflags = kvm_get_rflags(vcpu);
5264 kvm_set_rflags(vcpu, eflags | X86_EFLAGS_NT);
37817f29
IE		 5265 }
5266
5267 if (reason != TASK_SWITCH_IRET) {
3fe913e7 5268 nseg_desc.type |= (1 << 1);
37817f29
IE		 5269 save_guest_segment_descriptor(vcpu, tss_selector,
5270 &nseg_desc);
5271 }
5272
4d4ec087 5273 kvm_x86_ops->set_cr0(vcpu, kvm_read_cr0(vcpu) | X86_CR0_TS);
37817f29
IE		 5274 seg_desct_to_kvm_desct(&nseg_desc, tss_selector, &tr_seg);
5275 tr_seg.type = 11;
3e6e0aab 5276 kvm_set_segment(vcpu, &tr_seg, VCPU_SREG_TR);
37817f29 5277out:
37817f29
IE		 5278 return ret;
5279}
5280EXPORT_SYMBOL_GPL(kvm_task_switch);
5281
b6c7a5dc
HB		 5282int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
5283 struct kvm_sregs *sregs)
5284{
5285 int mmu_reset_needed = 0;
923c61bb 5286 int pending_vec, max_bits;
89a27f4d 5287 struct desc_ptr dt;
b6c7a5dc
HB		 5288
5289 vcpu_load(vcpu);
5290
89a27f4d
GN		 5291 dt.size = sregs->idt.limit;
5292 dt.address = sregs->idt.base;
b6c7a5dc 5293 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 5294 dt.size = sregs->gdt.limit;
5295 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 5296 kvm_x86_ops->set_gdt(vcpu, &dt);
5297
ad312c7c
ZX		 5298 vcpu->arch.cr2 = sregs->cr2;
5299 mmu_reset_needed |= vcpu->arch.cr3 != sregs->cr3;
dc7e795e 5300 vcpu->arch.cr3 = sregs->cr3;
b6c7a5dc 5301
2d3ad1f4 5302 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 5303
f6801dff 5304 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 5305 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 5306 kvm_set_apic_base(vcpu, sregs->apic_base);
5307
4d4ec087 5308 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 5309 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 5310 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 5311
fc78f519 5312 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 5313 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
7c93be44 5314 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
ad312c7c 5315 load_pdptrs(vcpu, vcpu->arch.cr3);
7c93be44
MT		 5316 mmu_reset_needed = 1;
5317 }
b6c7a5dc
HB		 5318
5319 if (mmu_reset_needed)
5320 kvm_mmu_reset_context(vcpu);
5321
923c61bb
GN		 5322 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
5323 pending_vec = find_first_bit(
5324 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
5325 if (pending_vec < max_bits) {
66fd3f7f 5326 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb
GN		 5327 pr_debug("Set back pending irq %d\n", pending_vec);
5328 if (irqchip_in_kernel(vcpu->kvm))
5329 kvm_pic_clear_isr_ack(vcpu->kvm);
b6c7a5dc
HB		 5330 }
5331
3e6e0aab
GT		 5332 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5333 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5334 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5335 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5336 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5337 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 5338
3e6e0aab
GT		 5339 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5340 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 5341
5f0269f5
ME		 5342 update_cr8_intercept(vcpu);
5343
9c3e4aab 5344 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 5345 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 5346 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 5347 !is_protmode(vcpu))
9c3e4aab
MT		 5348 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
5349
b6c7a5dc
HB		 5350 vcpu_put(vcpu);
5351
5352 return 0;
5353}
5354
d0bfb940
JK		 5355int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
5356 struct kvm_guest_debug *dbg)
b6c7a5dc 5357{
355be0b9 5358 unsigned long rflags;
ae675ef0 5359 int i, r;
b6c7a5dc
HB		 5360
5361 vcpu_load(vcpu);
5362
4f926bf2
JK		 5363 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
5364 r = -EBUSY;
5365 if (vcpu->arch.exception.pending)
5366 goto unlock_out;
5367 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
5368 kvm_queue_exception(vcpu, DB_VECTOR);
5369 else
5370 kvm_queue_exception(vcpu, BP_VECTOR);
5371 }
5372
91586a3b
JK		 5373 /*
5374 * Read rflags as long as potentially injected trace flags are still
5375 * filtered out.
5376 */
5377 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 5378
5379 vcpu->guest_debug = dbg->control;
5380 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
5381 vcpu->guest_debug = 0;
5382
5383 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 5384 for (i = 0; i < KVM_NR_DB_REGS; ++i)
5385 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
5386 vcpu->arch.switch_db_regs =
5387 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
5388 } else {
5389 for (i = 0; i < KVM_NR_DB_REGS; i++)
5390 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
5391 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
5392 }
5393
f92653ee
JK		 5394 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
5395 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
5396 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 5397
91586a3b
JK		 5398 /*
5399 * Trigger an rflags update that will inject or remove the trace
5400 * flags.
5401 */
5402 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 5403
355be0b9 5404 kvm_x86_ops->set_guest_debug(vcpu, dbg);
b6c7a5dc 5405
4f926bf2 5406 r = 0;
d0bfb940 5407
4f926bf2 5408unlock_out:
b6c7a5dc
HB		 5409 vcpu_put(vcpu);
5410
5411 return r;
5412}
5413
d0752060
HB		 5414/*
5415 * fxsave fpu state. Taken from x86_64/processor.h. To be killed when
5416 * we have asm/x86/processor.h
5417 */
5418struct fxsave {
5419 u16 cwd;
5420 u16 swd;
5421 u16 twd;
5422 u16 fop;
5423 u64 rip;
5424 u64 rdp;
5425 u32 mxcsr;
5426 u32 mxcsr_mask;
5427 u32 st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
5428#ifdef CONFIG_X86_64
5429 u32 xmm_space[64]; /* 16*16 bytes for each XMM-reg = 256 bytes */
5430#else
5431 u32 xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */
5432#endif
5433};
5434
8b006791
ZX		 5435/*
5436 * Translate a guest virtual address to a guest physical address.
5437 */
5438int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
5439 struct kvm_translation *tr)
5440{
5441 unsigned long vaddr = tr->linear_address;
5442 gpa_t gpa;
f656ce01 5443 int idx;
8b006791
ZX		 5444
5445 vcpu_load(vcpu);
f656ce01 5446 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 5447 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 5448 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 5449 tr->physical_address = gpa;
5450 tr->valid = gpa != UNMAPPED_GVA;
5451 tr->writeable = 1;
5452 tr->usermode = 0;
8b006791
ZX		 5453 vcpu_put(vcpu);
5454
5455 return 0;
5456}
5457
d0752060
HB		 5458int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5459{
ad312c7c 5460 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060
HB		 5461
5462 vcpu_load(vcpu);
5463
5464 memcpy(fpu->fpr, fxsave->st_space, 128);
5465 fpu->fcw = fxsave->cwd;
5466 fpu->fsw = fxsave->swd;
5467 fpu->ftwx = fxsave->twd;
5468 fpu->last_opcode = fxsave->fop;
5469 fpu->last_ip = fxsave->rip;
5470 fpu->last_dp = fxsave->rdp;
5471 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
5472
5473 vcpu_put(vcpu);
5474
5475 return 0;
5476}
5477
5478int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5479{
ad312c7c 5480 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060
HB		 5481
5482 vcpu_load(vcpu);
5483
5484 memcpy(fxsave->st_space, fpu->fpr, 128);
5485 fxsave->cwd = fpu->fcw;
5486 fxsave->swd = fpu->fsw;
5487 fxsave->twd = fpu->ftwx;
5488 fxsave->fop = fpu->last_opcode;
5489 fxsave->rip = fpu->last_ip;
5490 fxsave->rdp = fpu->last_dp;
5491 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
5492
5493 vcpu_put(vcpu);
5494
5495 return 0;
5496}
5497
5498void fx_init(struct kvm_vcpu *vcpu)
5499{
5500 unsigned after_mxcsr_mask;
5501
bc1a34f1
AA		 5502 /*
5503 * Touch the fpu the first time in non atomic context as if
5504 * this is the first fpu instruction the exception handler
5505 * will fire before the instruction returns and it'll have to
5506 * allocate ram with GFP_KERNEL.
5507 */
5508 if (!used_math())
d6e88aec 5509 kvm_fx_save(&vcpu->arch.host_fx_image);
bc1a34f1 5510
d0752060
HB		 5511 /* Initialize guest FPU by resetting ours and saving into guest's */
5512 preempt_disable();
d6e88aec
AK		 5513 kvm_fx_save(&vcpu->arch.host_fx_image);
5514 kvm_fx_finit();
5515 kvm_fx_save(&vcpu->arch.guest_fx_image);
5516 kvm_fx_restore(&vcpu->arch.host_fx_image);
d0752060
HB		 5517 preempt_enable();
5518
ad312c7c 5519 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 5520 after_mxcsr_mask = offsetof(struct i387_fxsave_struct, st_space);
ad312c7c
ZX		 5521 vcpu->arch.guest_fx_image.mxcsr = 0x1f80;
5522 memset((void *)&vcpu->arch.guest_fx_image + after_mxcsr_mask,
d0752060
HB		 5523 0, sizeof(struct i387_fxsave_struct) - after_mxcsr_mask);
5524}
5525EXPORT_SYMBOL_GPL(fx_init);
5526
5527void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
5528{
2608d7a1 5529 if (vcpu->guest_fpu_loaded)
d0752060
HB		 5530 return;
5531
5532 vcpu->guest_fpu_loaded = 1;
d6e88aec
AK		 5533 kvm_fx_save(&vcpu->arch.host_fx_image);
5534 kvm_fx_restore(&vcpu->arch.guest_fx_image);
0c04851c 5535 trace_kvm_fpu(1);
d0752060 5536}
d0752060
HB		 5537
5538void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
5539{
5540 if (!vcpu->guest_fpu_loaded)
5541 return;
5542
5543 vcpu->guest_fpu_loaded = 0;
d6e88aec
AK		 5544 kvm_fx_save(&vcpu->arch.guest_fx_image);
5545 kvm_fx_restore(&vcpu->arch.host_fx_image);
f096ed85 5546 ++vcpu->stat.fpu_reload;
02daab21 5547 set_bit(KVM_REQ_DEACTIVATE_FPU, &vcpu->requests);
0c04851c 5548 trace_kvm_fpu(0);
d0752060 5549}
e9b11c17
ZX		 5550
5551void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
5552{
7f1ea208
JR		 5553 if (vcpu->arch.time_page) {
5554 kvm_release_page_dirty(vcpu->arch.time_page);
5555 vcpu->arch.time_page = NULL;
5556 }
5557
e9b11c17
ZX		 5558 kvm_x86_ops->vcpu_free(vcpu);
5559}
5560
5561struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
5562 unsigned int id)
5563{
26e5215f
AK		 5564 return kvm_x86_ops->vcpu_create(kvm, id);
5565}
e9b11c17 5566
26e5215f
AK		 5567int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
5568{
5569 int r;
e9b11c17
ZX		 5570
5571 /* We do fxsave: this must be aligned. */
ad312c7c 5572 BUG_ON((unsigned long)&vcpu->arch.host_fx_image & 0xF);
e9b11c17 5573
0bed3b56 5574 vcpu->arch.mtrr_state.have_fixed = 1;
e9b11c17
ZX		 5575 vcpu_load(vcpu);
5576 r = kvm_arch_vcpu_reset(vcpu);
5577 if (r == 0)
5578 r = kvm_mmu_setup(vcpu);
5579 vcpu_put(vcpu);
5580 if (r < 0)
5581 goto free_vcpu;
5582
26e5215f 5583 return 0;
e9b11c17
ZX		 5584free_vcpu:
5585 kvm_x86_ops->vcpu_free(vcpu);
26e5215f 5586 return r;
e9b11c17
ZX		 5587}
5588
d40ccc62 5589void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17
ZX		 5590{
5591 vcpu_load(vcpu);
5592 kvm_mmu_unload(vcpu);
5593 vcpu_put(vcpu);
5594
5595 kvm_x86_ops->vcpu_free(vcpu);
5596}
5597
5598int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
5599{
448fa4a9
JK		 5600 vcpu->arch.nmi_pending = false;
5601 vcpu->arch.nmi_injected = false;
5602
42dbaa5a
JK		 5603 vcpu->arch.switch_db_regs = 0;
5604 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
5605 vcpu->arch.dr6 = DR6_FIXED_1;
5606 vcpu->arch.dr7 = DR7_FIXED_1;
5607
e9b11c17
ZX		 5608 return kvm_x86_ops->vcpu_reset(vcpu);
5609}
5610
10474ae8 5611int kvm_arch_hardware_enable(void *garbage)
e9b11c17 5612{
0cca7907
ZA		 5613 /*
5614 * Since this may be called from a hotplug notifcation,
5615 * we can't get the CPU frequency directly.
5616 */
5617 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
5618 int cpu = raw_smp_processor_id();
5619 per_cpu(cpu_tsc_khz, cpu) = 0;
5620 }
18863bdd
AK		 5621
5622 kvm_shared_msr_cpu_online();
5623
10474ae8 5624 return kvm_x86_ops->hardware_enable(garbage);
e9b11c17
ZX		 5625}
5626
5627void kvm_arch_hardware_disable(void *garbage)
5628{
5629 kvm_x86_ops->hardware_disable(garbage);
3548bab5 5630 drop_user_return_notifiers(garbage);
e9b11c17
ZX		 5631}
5632
5633int kvm_arch_hardware_setup(void)
5634{
5635 return kvm_x86_ops->hardware_setup();
5636}
5637
5638void kvm_arch_hardware_unsetup(void)
5639{
5640 kvm_x86_ops->hardware_unsetup();
5641}
5642
5643void kvm_arch_check_processor_compat(void *rtn)
5644{
5645 kvm_x86_ops->check_processor_compatibility(rtn);
5646}
5647
5648int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
5649{
5650 struct page *page;
5651 struct kvm *kvm;
5652 int r;
5653
5654 BUG_ON(vcpu->kvm == NULL);
5655 kvm = vcpu->kvm;
5656
ad312c7c 5657 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
c5af89b6 5658 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 5659 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 5660 else
a4535290 5661 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 5662
5663 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
5664 if (!page) {
5665 r = -ENOMEM;
5666 goto fail;
5667 }
ad312c7c 5668 vcpu->arch.pio_data = page_address(page);
e9b11c17
ZX		 5669
5670 r = kvm_mmu_create(vcpu);
5671 if (r < 0)
5672 goto fail_free_pio_data;
5673
5674 if (irqchip_in_kernel(kvm)) {
5675 r = kvm_create_lapic(vcpu);
5676 if (r < 0)
5677 goto fail_mmu_destroy;
5678 }
5679
890ca9ae
HY		 5680 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
5681 GFP_KERNEL);
5682 if (!vcpu->arch.mce_banks) {
5683 r = -ENOMEM;
443c39bc 5684 goto fail_free_lapic;
890ca9ae
HY		 5685 }
5686 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
5687
e9b11c17 5688 return 0;
443c39bc
WY		 5689fail_free_lapic:
5690 kvm_free_lapic(vcpu);
e9b11c17
ZX		 5691fail_mmu_destroy:
5692 kvm_mmu_destroy(vcpu);
5693fail_free_pio_data:
ad312c7c 5694 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 5695fail:
5696 return r;
5697}
5698
5699void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
5700{
f656ce01
MT		 5701 int idx;
5702
36cb93fd 5703 kfree(vcpu->arch.mce_banks);
e9b11c17 5704 kvm_free_lapic(vcpu);
f656ce01 5705 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 5706 kvm_mmu_destroy(vcpu);
f656ce01 5707 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 5708 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17 5709}
d19a9cd2
ZX		 5710
5711struct kvm *kvm_arch_create_vm(void)
5712{
5713 struct kvm *kvm = kzalloc(sizeof(struct kvm), GFP_KERNEL);
5714
5715 if (!kvm)
5716 return ERR_PTR(-ENOMEM);
5717
fef9cce0
MT		 5718 kvm->arch.aliases = kzalloc(sizeof(struct kvm_mem_aliases), GFP_KERNEL);
5719 if (!kvm->arch.aliases) {
5720 kfree(kvm);
5721 return ERR_PTR(-ENOMEM);
5722 }
5723
f05e70ac 5724 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4d5c5d0f 5725 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2 5726
5550af4d
SY		 5727 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
5728 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
5729
53f658b3
MT		 5730 rdtscll(kvm->arch.vm_init_tsc);
5731
d19a9cd2
ZX		 5732 return kvm;
5733}
5734
5735static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
5736{
5737 vcpu_load(vcpu);
5738 kvm_mmu_unload(vcpu);
5739 vcpu_put(vcpu);
5740}
5741
5742static void kvm_free_vcpus(struct kvm *kvm)
5743{
5744 unsigned int i;
988a2cae 5745 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 5746
5747 /*
5748 * Unpin any mmu pages first.
5749 */
988a2cae
GN		 5750 kvm_for_each_vcpu(i, vcpu, kvm)
5751 kvm_unload_vcpu_mmu(vcpu);
5752 kvm_for_each_vcpu(i, vcpu, kvm)
5753 kvm_arch_vcpu_free(vcpu);
5754
5755 mutex_lock(&kvm->lock);
5756 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
5757 kvm->vcpus[i] = NULL;
d19a9cd2 5758
988a2cae
GN		 5759 atomic_set(&kvm->online_vcpus, 0);
5760 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 5761}
5762
ad8ba2cd
SY		 5763void kvm_arch_sync_events(struct kvm *kvm)
5764{
ba4cef31 5765 kvm_free_all_assigned_devices(kvm);
ad8ba2cd
SY		 5766}
5767
d19a9cd2
ZX		 5768void kvm_arch_destroy_vm(struct kvm *kvm)
5769{
6eb55818 5770 kvm_iommu_unmap_guest(kvm);
7837699f 5771 kvm_free_pit(kvm);
d7deeeb0
ZX		 5772 kfree(kvm->arch.vpic);
5773 kfree(kvm->arch.vioapic);
d19a9cd2
ZX		 5774 kvm_free_vcpus(kvm);
5775 kvm_free_physmem(kvm);
3d45830c
AK		 5776 if (kvm->arch.apic_access_page)
5777 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 5778 if (kvm->arch.ept_identity_pagetable)
5779 put_page(kvm->arch.ept_identity_pagetable);
64749204 5780 cleanup_srcu_struct(&kvm->srcu);
fef9cce0 5781 kfree(kvm->arch.aliases);
d19a9cd2
ZX		 5782 kfree(kvm);
5783}
0de10343 5784
f7784b8e
MT		 5785int kvm_arch_prepare_memory_region(struct kvm *kvm,
5786 struct kvm_memory_slot *memslot,
0de10343 5787 struct kvm_memory_slot old,
f7784b8e 5788 struct kvm_userspace_memory_region *mem,
0de10343
ZX		 5789 int user_alloc)
5790{
f7784b8e 5791 int npages = memslot->npages;
0de10343
ZX		 5792
5793 /*To keep backward compatibility with older userspace,
5794 *x86 needs to hanlde !user_alloc case.
5795 */
5796 if (!user_alloc) {
5797 if (npages && !old.rmap) {
604b38ac
AA		 5798 unsigned long userspace_addr;
5799
72dc67a6 5800 down_write(&current->mm->mmap_sem);
604b38ac
AA		 5801 userspace_addr = do_mmap(NULL, 0,
5802 npages * PAGE_SIZE,
5803 PROT_READ | PROT_WRITE,
acee3c04 5804 MAP_PRIVATE | MAP_ANONYMOUS,
604b38ac 5805 0);
72dc67a6 5806 up_write(&current->mm->mmap_sem);
0de10343 5807
604b38ac
AA		 5808 if (IS_ERR((void *)userspace_addr))
5809 return PTR_ERR((void *)userspace_addr);
5810
604b38ac 5811 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 5812 }
5813 }
5814
f7784b8e
MT		 5815
5816 return 0;
5817}
5818
5819void kvm_arch_commit_memory_region(struct kvm *kvm,
5820 struct kvm_userspace_memory_region *mem,
5821 struct kvm_memory_slot old,
5822 int user_alloc)
5823{
5824
5825 int npages = mem->memory_size >> PAGE_SHIFT;
5826
5827 if (!user_alloc && !old.user_alloc && old.rmap && !npages) {
5828 int ret;
5829
5830 down_write(&current->mm->mmap_sem);
5831 ret = do_munmap(current->mm, old.userspace_addr,
5832 old.npages * PAGE_SIZE);
5833 up_write(&current->mm->mmap_sem);
5834 if (ret < 0)
5835 printk(KERN_WARNING
5836 "kvm_vm_ioctl_set_memory_region: "
5837 "failed to munmap memory\n");
5838 }
5839
7c8a83b7 5840 spin_lock(&kvm->mmu_lock);
f05e70ac 5841 if (!kvm->arch.n_requested_mmu_pages) {
0de10343
ZX		 5842 unsigned int nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
5843 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
5844 }
5845
5846 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
7c8a83b7 5847 spin_unlock(&kvm->mmu_lock);
0de10343 5848}
1d737c8a 5849
34d4cb8f
MT		 5850void kvm_arch_flush_shadow(struct kvm *kvm)
5851{
5852 kvm_mmu_zap_all(kvm);
8986ecc0 5853 kvm_reload_remote_mmus(kvm);
34d4cb8f
MT		 5854}
5855
1d737c8a
ZX		 5856int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
5857{
a4535290 5858 return vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE
a1b37100
GN		 5859 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
5860 || vcpu->arch.nmi_pending ||
5861 (kvm_arch_interrupt_allowed(vcpu) &&
5862 kvm_cpu_has_interrupt(vcpu));
1d737c8a 5863}
5736199a 5864
5736199a
ZX		 5865void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
5866{
32f88400
MT		 5867 int me;
5868 int cpu = vcpu->cpu;
5736199a
ZX		 5869
5870 if (waitqueue_active(&vcpu->wq)) {
5871 wake_up_interruptible(&vcpu->wq);
5872 ++vcpu->stat.halt_wakeup;
5873 }
32f88400
MT		 5874
5875 me = get_cpu();
5876 if (cpu != me && (unsigned)cpu < nr_cpu_ids && cpu_online(cpu))
5877 if (!test_and_set_bit(KVM_REQ_KICK, &vcpu->requests))
5878 smp_send_reschedule(cpu);
e9571ed5 5879 put_cpu();
5736199a 5880}
78646121
GN		 5881
5882int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
5883{
5884 return kvm_x86_ops->interrupt_allowed(vcpu);
5885}
229456fc 5886
f92653ee
JK		 5887bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
5888{
5889 unsigned long current_rip = kvm_rip_read(vcpu) +
5890 get_segment_base(vcpu, VCPU_SREG_CS);
5891
5892 return current_rip == linear_rip;
5893}
5894EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
5895
94fe45da
JK		 5896unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
5897{
5898 unsigned long rflags;
5899
5900 rflags = kvm_x86_ops->get_rflags(vcpu);
5901 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 5902 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 5903 return rflags;
5904}
5905EXPORT_SYMBOL_GPL(kvm_get_rflags);
5906
5907void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
5908{
5909 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 5910 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 5911 rflags |= X86_EFLAGS_TF;
94fe45da
JK		 5912 kvm_x86_ops->set_rflags(vcpu, rflags);
5913}
5914EXPORT_SYMBOL_GPL(kvm_set_rflags);
5915
229456fc
MT		 5916EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
5917EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
5918EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
5919EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
5920EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 5921EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 5922EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 5923EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 5924EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 5925EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 5926EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 5927EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
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