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KVM: introduce wrapper functions for creating/destroying dirty bitmaps
[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
313a3dc7 29
18068523 30#include <linux/clocksource.h>
4d5c5d0f 31#include <linux/interrupt.h>
313a3dc7
CO		 32#include <linux/kvm.h>
33#include <linux/fs.h>
34#include <linux/vmalloc.h>
5fb76f9b 35#include <linux/module.h>
0de10343 36#include <linux/mman.h>
2bacc55c 37#include <linux/highmem.h>
19de40a8 38#include <linux/iommu.h>
62c476c7 39#include <linux/intel-iommu.h>
c8076604 40#include <linux/cpufreq.h>
18863bdd 41#include <linux/user-return-notifier.h>
a983fb23 42#include <linux/srcu.h>
5a0e3ad6 43#include <linux/slab.h>
ff9d07a0 44#include <linux/perf_event.h>
7bee342a 45#include <linux/uaccess.h>
af585b92 46#include <linux/hash.h>
aec51dc4 47#include <trace/events/kvm.h>
2ed152af 48
229456fc
MT		 49#define CREATE_TRACE_POINTS
50#include "trace.h"
043405e1 51
24f1e32c 52#include <asm/debugreg.h>
d825ed0a 53#include <asm/msr.h>
a5f61300 54#include <asm/desc.h>
0bed3b56 55#include <asm/mtrr.h>
890ca9ae 56#include <asm/mce.h>
7cf30855 57#include <asm/i387.h>
98918833 58#include <asm/xcr.h>
1d5f066e 59#include <asm/pvclock.h>
217fc9cf 60#include <asm/div64.h>
043405e1 61
313a3dc7 62#define MAX_IO_MSRS 256
a03490ed
CO		 63#define CR0_RESERVED_BITS \
64 (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \
65 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \
66 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG))
67#define CR4_RESERVED_BITS \
68 (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\
69 | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \
70 | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR \
2acf923e 71 | X86_CR4_OSXSAVE \
a03490ed
CO		 72 | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE))
73
74#define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
890ca9ae
HY		 75
76#define KVM_MAX_MCE_BANKS 32
5854dbca 77#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 78
50a37eb4
JR		 79/* EFER defaults:
80 * - enable syscall per default because its emulated by KVM
81 * - enable LME and LMA per default on 64 bit KVM
82 */
83#ifdef CONFIG_X86_64
84static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffafeULL;
85#else
86static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffffeULL;
87#endif
313a3dc7 88
ba1389b7
AK		 89#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
90#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 91
cb142eb7 92static void update_cr8_intercept(struct kvm_vcpu *vcpu);
674eea0f
AK		 93static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
94 struct kvm_cpuid_entry2 __user *entries);
95
97896d04 96struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 97EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 98
ed85c068
AP		 99int ignore_msrs = 0;
100module_param_named(ignore_msrs, ignore_msrs, bool, S_IRUGO | S_IWUSR);
101
18863bdd
AK		 102#define KVM_NR_SHARED_MSRS 16
103
104struct kvm_shared_msrs_global {
105 int nr;
2bf78fa7 106 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 107};
108
109struct kvm_shared_msrs {
110 struct user_return_notifier urn;
111 bool registered;
2bf78fa7
SY		 112 struct kvm_shared_msr_values {
113 u64 host;
114 u64 curr;
115 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 116};
117
118static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
119static DEFINE_PER_CPU(struct kvm_shared_msrs, shared_msrs);
120
417bc304 121struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 122 { "pf_fixed", VCPU_STAT(pf_fixed) },
123 { "pf_guest", VCPU_STAT(pf_guest) },
124 { "tlb_flush", VCPU_STAT(tlb_flush) },
125 { "invlpg", VCPU_STAT(invlpg) },
126 { "exits", VCPU_STAT(exits) },
127 { "io_exits", VCPU_STAT(io_exits) },
128 { "mmio_exits", VCPU_STAT(mmio_exits) },
129 { "signal_exits", VCPU_STAT(signal_exits) },
130 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 131 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 132 { "halt_exits", VCPU_STAT(halt_exits) },
133 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 134 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 135 { "request_irq", VCPU_STAT(request_irq_exits) },
136 { "irq_exits", VCPU_STAT(irq_exits) },
137 { "host_state_reload", VCPU_STAT(host_state_reload) },
138 { "efer_reload", VCPU_STAT(efer_reload) },
139 { "fpu_reload", VCPU_STAT(fpu_reload) },
140 { "insn_emulation", VCPU_STAT(insn_emulation) },
141 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 142 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 143 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 144 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
145 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
146 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
147 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
148 { "mmu_flooded", VM_STAT(mmu_flooded) },
149 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 150 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 151 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 152 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 153 { "largepages", VM_STAT(lpages) },
417bc304
HB		 154 { NULL }
155};
156
2acf923e
DC		 157u64 __read_mostly host_xcr0;
158
af585b92
GN		 159static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
160{
161 int i;
162 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
163 vcpu->arch.apf.gfns[i] = ~0;
164}
165
18863bdd
AK		 166static void kvm_on_user_return(struct user_return_notifier *urn)
167{
168 unsigned slot;
18863bdd
AK		 169 struct kvm_shared_msrs *locals
170 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 171 struct kvm_shared_msr_values *values;
18863bdd
AK		 172
173 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 174 values = &locals->values[slot];
175 if (values->host != values->curr) {
176 wrmsrl(shared_msrs_global.msrs[slot], values->host);
177 values->curr = values->host;
18863bdd
AK		 178 }
179 }
180 locals->registered = false;
181 user_return_notifier_unregister(urn);
182}
183
2bf78fa7 184static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 185{
2bf78fa7 186 struct kvm_shared_msrs *smsr;
18863bdd
AK		 187 u64 value;
188
2bf78fa7
SY		 189 smsr = &__get_cpu_var(shared_msrs);
190 /* only read, and nobody should modify it at this time,
191 * so don't need lock */
192 if (slot >= shared_msrs_global.nr) {
193 printk(KERN_ERR "kvm: invalid MSR slot!");
194 return;
195 }
196 rdmsrl_safe(msr, &value);
197 smsr->values[slot].host = value;
198 smsr->values[slot].curr = value;
199}
200
201void kvm_define_shared_msr(unsigned slot, u32 msr)
202{
18863bdd
AK		 203 if (slot >= shared_msrs_global.nr)
204 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 205 shared_msrs_global.msrs[slot] = msr;
206 /* we need ensured the shared_msr_global have been updated */
207 smp_wmb();
18863bdd
AK		 208}
209EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
210
211static void kvm_shared_msr_cpu_online(void)
212{
213 unsigned i;
18863bdd
AK		 214
215 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 216 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 217}
218
d5696725 219void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd
AK		 220{
221 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
222
2bf78fa7 223 if (((value ^ smsr->values[slot].curr) & mask) == 0)
18863bdd 224 return;
2bf78fa7
SY		 225 smsr->values[slot].curr = value;
226 wrmsrl(shared_msrs_global.msrs[slot], value);
18863bdd
AK		 227 if (!smsr->registered) {
228 smsr->urn.on_user_return = kvm_on_user_return;
229 user_return_notifier_register(&smsr->urn);
230 smsr->registered = true;
231 }
232}
233EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
234
3548bab5
AK		 235static void drop_user_return_notifiers(void *ignore)
236{
237 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
238
239 if (smsr->registered)
240 kvm_on_user_return(&smsr->urn);
241}
242
6866b83e
CO		 243u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
244{
245 if (irqchip_in_kernel(vcpu->kvm))
ad312c7c 246 return vcpu->arch.apic_base;
6866b83e 247 else
ad312c7c 248 return vcpu->arch.apic_base;
6866b83e
CO		 249}
250EXPORT_SYMBOL_GPL(kvm_get_apic_base);
251
252void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
253{
254 /* TODO: reserve bits check */
255 if (irqchip_in_kernel(vcpu->kvm))
256 kvm_lapic_set_base(vcpu, data);
257 else
ad312c7c 258 vcpu->arch.apic_base = data;
6866b83e
CO		 259}
260EXPORT_SYMBOL_GPL(kvm_set_apic_base);
261
3fd28fce
ED		 262#define EXCPT_BENIGN 0
263#define EXCPT_CONTRIBUTORY 1
264#define EXCPT_PF 2
265
266static int exception_class(int vector)
267{
268 switch (vector) {
269 case PF_VECTOR:
270 return EXCPT_PF;
271 case DE_VECTOR:
272 case TS_VECTOR:
273 case NP_VECTOR:
274 case SS_VECTOR:
275 case GP_VECTOR:
276 return EXCPT_CONTRIBUTORY;
277 default:
278 break;
279 }
280 return EXCPT_BENIGN;
281}
282
283static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 284 unsigned nr, bool has_error, u32 error_code,
285 bool reinject)
3fd28fce
ED		 286{
287 u32 prev_nr;
288 int class1, class2;
289
3842d135
AK		 290 kvm_make_request(KVM_REQ_EVENT, vcpu);
291
3fd28fce
ED		 292 if (!vcpu->arch.exception.pending) {
293 queue:
294 vcpu->arch.exception.pending = true;
295 vcpu->arch.exception.has_error_code = has_error;
296 vcpu->arch.exception.nr = nr;
297 vcpu->arch.exception.error_code = error_code;
3f0fd292 298 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 299 return;
300 }
301
302 /* to check exception */
303 prev_nr = vcpu->arch.exception.nr;
304 if (prev_nr == DF_VECTOR) {
305 /* triple fault -> shutdown */
a8eeb04a 306 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 307 return;
308 }
309 class1 = exception_class(prev_nr);
310 class2 = exception_class(nr);
311 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
312 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
313 /* generate double fault per SDM Table 5-5 */
314 vcpu->arch.exception.pending = true;
315 vcpu->arch.exception.has_error_code = true;
316 vcpu->arch.exception.nr = DF_VECTOR;
317 vcpu->arch.exception.error_code = 0;
318 } else
319 /* replace previous exception with a new one in a hope
320 that instruction re-execution will regenerate lost
321 exception */
322 goto queue;
323}
324
298101da
AK		 325void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
326{
ce7ddec4 327 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 328}
329EXPORT_SYMBOL_GPL(kvm_queue_exception);
330
ce7ddec4
JR		 331void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
332{
333 kvm_multiple_exception(vcpu, nr, false, 0, true);
334}
335EXPORT_SYMBOL_GPL(kvm_requeue_exception);
336
8df25a32 337void kvm_inject_page_fault(struct kvm_vcpu *vcpu)
c3c91fee 338{
8df25a32
JR		 339 unsigned error_code = vcpu->arch.fault.error_code;
340
c3c91fee 341 ++vcpu->stat.pf_guest;
8df25a32 342 vcpu->arch.cr2 = vcpu->arch.fault.address;
c3c91fee
AK		 343 kvm_queue_exception_e(vcpu, PF_VECTOR, error_code);
344}
345
d4f8cf66
JR		 346void kvm_propagate_fault(struct kvm_vcpu *vcpu)
347{
0959ffac 348 if (mmu_is_nested(vcpu) && !vcpu->arch.fault.nested)
d4f8cf66
JR		 349 vcpu->arch.nested_mmu.inject_page_fault(vcpu);
350 else
351 vcpu->arch.mmu.inject_page_fault(vcpu);
0959ffac
JR		 352
353 vcpu->arch.fault.nested = false;
d4f8cf66
JR		 354}
355
3419ffc8
SY		 356void kvm_inject_nmi(struct kvm_vcpu *vcpu)
357{
3842d135 358 kvm_make_request(KVM_REQ_EVENT, vcpu);
3419ffc8
SY		 359 vcpu->arch.nmi_pending = 1;
360}
361EXPORT_SYMBOL_GPL(kvm_inject_nmi);
362
298101da
AK		 363void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
364{
ce7ddec4 365 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 366}
367EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
368
ce7ddec4
JR		 369void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
370{
371 kvm_multiple_exception(vcpu, nr, true, error_code, true);
372}
373EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
374
0a79b009
AK		 375/*
376 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
377 * a #GP and return false.
378 */
379bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 380{
0a79b009
AK		 381 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
382 return true;
383 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
384 return false;
298101da 385}
0a79b009 386EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 387
ec92fe44
JR		 388/*
389 * This function will be used to read from the physical memory of the currently
390 * running guest. The difference to kvm_read_guest_page is that this function
391 * can read from guest physical or from the guest's guest physical memory.
392 */
393int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
394 gfn_t ngfn, void *data, int offset, int len,
395 u32 access)
396{
397 gfn_t real_gfn;
398 gpa_t ngpa;
399
400 ngpa = gfn_to_gpa(ngfn);
401 real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
402 if (real_gfn == UNMAPPED_GVA)
403 return -EFAULT;
404
405 real_gfn = gpa_to_gfn(real_gfn);
406
407 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
408}
409EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
410
3d06b8bf
JR		 411int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
412 void *data, int offset, int len, u32 access)
413{
414 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
415 data, offset, len, access);
416}
417
a03490ed
CO		 418/*
419 * Load the pae pdptrs. Return true is they are all valid.
420 */
ff03a073 421int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 422{
423 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
424 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
425 int i;
426 int ret;
ff03a073 427 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 428
ff03a073
JR		 429 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
430 offset * sizeof(u64), sizeof(pdpte),
431 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 432 if (ret < 0) {
433 ret = 0;
434 goto out;
435 }
436 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 437 if (is_present_gpte(pdpte[i]) &&
20c466b5 438 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 439 ret = 0;
440 goto out;
441 }
442 }
443 ret = 1;
444
ff03a073 445 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 446 __set_bit(VCPU_EXREG_PDPTR,
447 (unsigned long *)&vcpu->arch.regs_avail);
448 __set_bit(VCPU_EXREG_PDPTR,
449 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 450out:
a03490ed
CO		 451
452 return ret;
453}
cc4b6871 454EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 455
d835dfec
AK		 456static bool pdptrs_changed(struct kvm_vcpu *vcpu)
457{
ff03a073 458 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 459 bool changed = true;
3d06b8bf
JR		 460 int offset;
461 gfn_t gfn;
d835dfec
AK		 462 int r;
463
464 if (is_long_mode(vcpu) || !is_pae(vcpu))
465 return false;
466
6de4f3ad
AK		 467 if (!test_bit(VCPU_EXREG_PDPTR,
468 (unsigned long *)&vcpu->arch.regs_avail))
469 return true;
470
3d06b8bf
JR		 471 gfn = (vcpu->arch.cr3 & ~31u) >> PAGE_SHIFT;
472 offset = (vcpu->arch.cr3 & ~31u) & (PAGE_SIZE - 1);
473 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
474 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 475 if (r < 0)
476 goto out;
ff03a073 477 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 478out:
d835dfec
AK		 479
480 return changed;
481}
482
49a9b07e 483int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 484{
aad82703
SY		 485 unsigned long old_cr0 = kvm_read_cr0(vcpu);
486 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
487 X86_CR0_CD | X86_CR0_NW;
488
f9a48e6a
AK		 489 cr0 |= X86_CR0_ET;
490
ab344828 491#ifdef CONFIG_X86_64
0f12244f
GN		 492 if (cr0 & 0xffffffff00000000UL)
493 return 1;
ab344828
GN		 494#endif
495
496 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 497
0f12244f
GN		 498 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
499 return 1;
a03490ed 500
0f12244f
GN		 501 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
502 return 1;
a03490ed
CO		 503
504 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
505#ifdef CONFIG_X86_64
f6801dff 506 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 507 int cs_db, cs_l;
508
0f12244f
GN		 509 if (!is_pae(vcpu))
510 return 1;
a03490ed 511 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 512 if (cs_l)
513 return 1;
a03490ed
CO		 514 } else
515#endif
ff03a073
JR		 516 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
517 vcpu->arch.cr3))
0f12244f 518 return 1;
a03490ed
CO		 519 }
520
521 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 522
aad82703
SY		 523 if ((cr0 ^ old_cr0) & update_bits)
524 kvm_mmu_reset_context(vcpu);
0f12244f
GN		 525 return 0;
526}
2d3ad1f4 527EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 528
2d3ad1f4 529void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 530{
49a9b07e 531 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 532}
2d3ad1f4 533EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 534
2acf923e
DC		 535int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
536{
537 u64 xcr0;
538
539 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
540 if (index != XCR_XFEATURE_ENABLED_MASK)
541 return 1;
542 xcr0 = xcr;
543 if (kvm_x86_ops->get_cpl(vcpu) != 0)
544 return 1;
545 if (!(xcr0 & XSTATE_FP))
546 return 1;
547 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
548 return 1;
549 if (xcr0 & ~host_xcr0)
550 return 1;
551 vcpu->arch.xcr0 = xcr0;
552 vcpu->guest_xcr0_loaded = 0;
553 return 0;
554}
555
556int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
557{
558 if (__kvm_set_xcr(vcpu, index, xcr)) {
559 kvm_inject_gp(vcpu, 0);
560 return 1;
561 }
562 return 0;
563}
564EXPORT_SYMBOL_GPL(kvm_set_xcr);
565
566static bool guest_cpuid_has_xsave(struct kvm_vcpu *vcpu)
567{
568 struct kvm_cpuid_entry2 *best;
569
570 best = kvm_find_cpuid_entry(vcpu, 1, 0);
571 return best && (best->ecx & bit(X86_FEATURE_XSAVE));
572}
573
574static void update_cpuid(struct kvm_vcpu *vcpu)
575{
576 struct kvm_cpuid_entry2 *best;
577
578 best = kvm_find_cpuid_entry(vcpu, 1, 0);
579 if (!best)
580 return;
581
582 /* Update OSXSAVE bit */
583 if (cpu_has_xsave && best->function == 0x1) {
584 best->ecx &= ~(bit(X86_FEATURE_OSXSAVE));
585 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE))
586 best->ecx |= bit(X86_FEATURE_OSXSAVE);
587 }
588}
589
a83b29c6 590int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 591{
fc78f519 592 unsigned long old_cr4 = kvm_read_cr4(vcpu);
a2edf57f
AK		 593 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE;
594
0f12244f
GN		 595 if (cr4 & CR4_RESERVED_BITS)
596 return 1;
a03490ed 597
2acf923e
DC		 598 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
599 return 1;
600
a03490ed 601 if (is_long_mode(vcpu)) {
0f12244f
GN		 602 if (!(cr4 & X86_CR4_PAE))
603 return 1;
a2edf57f
AK		 604 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
605 && ((cr4 ^ old_cr4) & pdptr_bits)
ff03a073 606 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, vcpu->arch.cr3))
0f12244f
GN		 607 return 1;
608
609 if (cr4 & X86_CR4_VMXE)
610 return 1;
a03490ed 611
a03490ed 612 kvm_x86_ops->set_cr4(vcpu, cr4);
62ad0755 613
aad82703
SY		 614 if ((cr4 ^ old_cr4) & pdptr_bits)
615 kvm_mmu_reset_context(vcpu);
0f12244f 616
2acf923e
DC		 617 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
618 update_cpuid(vcpu);
619
0f12244f
GN		 620 return 0;
621}
2d3ad1f4 622EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 623
2390218b 624int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 625{
ad312c7c 626 if (cr3 == vcpu->arch.cr3 && !pdptrs_changed(vcpu)) {
0ba73cda 627 kvm_mmu_sync_roots(vcpu);
d835dfec 628 kvm_mmu_flush_tlb(vcpu);
0f12244f 629 return 0;
d835dfec
AK		 630 }
631
a03490ed 632 if (is_long_mode(vcpu)) {
0f12244f
GN		 633 if (cr3 & CR3_L_MODE_RESERVED_BITS)
634 return 1;
a03490ed
CO		 635 } else {
636 if (is_pae(vcpu)) {
0f12244f
GN		 637 if (cr3 & CR3_PAE_RESERVED_BITS)
638 return 1;
ff03a073
JR		 639 if (is_paging(vcpu) &&
640 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
0f12244f 641 return 1;
a03490ed
CO		 642 }
643 /*
644 * We don't check reserved bits in nonpae mode, because
645 * this isn't enforced, and VMware depends on this.
646 */
647 }
648
a03490ed
CO		 649 /*
650 * Does the new cr3 value map to physical memory? (Note, we
651 * catch an invalid cr3 even in real-mode, because it would
652 * cause trouble later on when we turn on paging anyway.)
653 *
654 * A real CPU would silently accept an invalid cr3 and would
655 * attempt to use it - with largely undefined (and often hard
656 * to debug) behavior on the guest side.
657 */
658 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
0f12244f
GN		 659 return 1;
660 vcpu->arch.cr3 = cr3;
661 vcpu->arch.mmu.new_cr3(vcpu);
662 return 0;
663}
2d3ad1f4 664EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 665
0f12244f 666int __kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 667{
0f12244f
GN		 668 if (cr8 & CR8_RESERVED_BITS)
669 return 1;
a03490ed
CO		 670 if (irqchip_in_kernel(vcpu->kvm))
671 kvm_lapic_set_tpr(vcpu, cr8);
672 else
ad312c7c 673 vcpu->arch.cr8 = cr8;
0f12244f
GN		 674 return 0;
675}
676
677void kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
678{
679 if (__kvm_set_cr8(vcpu, cr8))
680 kvm_inject_gp(vcpu, 0);
a03490ed 681}
2d3ad1f4 682EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 683
2d3ad1f4 684unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 685{
686 if (irqchip_in_kernel(vcpu->kvm))
687 return kvm_lapic_get_cr8(vcpu);
688 else
ad312c7c 689 return vcpu->arch.cr8;
a03490ed 690}
2d3ad1f4 691EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 692
338dbc97 693static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 694{
695 switch (dr) {
696 case 0 ... 3:
697 vcpu->arch.db[dr] = val;
698 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
699 vcpu->arch.eff_db[dr] = val;
700 break;
701 case 4:
338dbc97
GN		 702 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
703 return 1; /* #UD */
020df079
GN		 704 /* fall through */
705 case 6:
338dbc97
GN		 706 if (val & 0xffffffff00000000ULL)
707 return -1; /* #GP */
020df079
GN		 708 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
709 break;
710 case 5:
338dbc97
GN		 711 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
712 return 1; /* #UD */
020df079
GN		 713 /* fall through */
714 default: /* 7 */
338dbc97
GN		 715 if (val & 0xffffffff00000000ULL)
716 return -1; /* #GP */
020df079
GN		 717 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
718 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
719 kvm_x86_ops->set_dr7(vcpu, vcpu->arch.dr7);
720 vcpu->arch.switch_db_regs = (val & DR7_BP_EN_MASK);
721 }
722 break;
723 }
724
725 return 0;
726}
338dbc97
GN		 727
728int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
729{
730 int res;
731
732 res = __kvm_set_dr(vcpu, dr, val);
733 if (res > 0)
734 kvm_queue_exception(vcpu, UD_VECTOR);
735 else if (res < 0)
736 kvm_inject_gp(vcpu, 0);
737
738 return res;
739}
020df079
GN		 740EXPORT_SYMBOL_GPL(kvm_set_dr);
741
338dbc97 742static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 743{
744 switch (dr) {
745 case 0 ... 3:
746 *val = vcpu->arch.db[dr];
747 break;
748 case 4:
338dbc97 749 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 750 return 1;
020df079
GN		 751 /* fall through */
752 case 6:
753 *val = vcpu->arch.dr6;
754 break;
755 case 5:
338dbc97 756 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 757 return 1;
020df079
GN		 758 /* fall through */
759 default: /* 7 */
760 *val = vcpu->arch.dr7;
761 break;
762 }
763
764 return 0;
765}
338dbc97
GN		 766
767int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
768{
769 if (_kvm_get_dr(vcpu, dr, val)) {
770 kvm_queue_exception(vcpu, UD_VECTOR);
771 return 1;
772 }
773 return 0;
774}
020df079
GN		 775EXPORT_SYMBOL_GPL(kvm_get_dr);
776
043405e1
CO		 777/*
778 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
779 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
780 *
781 * This list is modified at module load time to reflect the
e3267cbb
GC		 782 * capabilities of the host cpu. This capabilities test skips MSRs that are
783 * kvm-specific. Those are put in the beginning of the list.
043405e1 784 */
e3267cbb 785
344d9588 786#define KVM_SAVE_MSRS_BEGIN 8
043405e1 787static u32 msrs_to_save[] = {
e3267cbb 788 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
11c6bffa 789 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
55cd8e5a 790 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
344d9588 791 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN,
043405e1 792 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 793 MSR_STAR,
043405e1
CO		 794#ifdef CONFIG_X86_64
795 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
796#endif
e90aa41e 797 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
043405e1
CO		 798};
799
800static unsigned num_msrs_to_save;
801
802static u32 emulated_msrs[] = {
803 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 804 MSR_IA32_MCG_STATUS,
805 MSR_IA32_MCG_CTL,
043405e1
CO		 806};
807
b69e8cae 808static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 809{
aad82703
SY		 810 u64 old_efer = vcpu->arch.efer;
811
b69e8cae
RJ		 812 if (efer & efer_reserved_bits)
813 return 1;
15c4a640
CO		 814
815 if (is_paging(vcpu)
b69e8cae
RJ		 816 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
817 return 1;
15c4a640 818
1b2fd70c
AG		 819 if (efer & EFER_FFXSR) {
820 struct kvm_cpuid_entry2 *feat;
821
822 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 823 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
824 return 1;
1b2fd70c
AG		 825 }
826
d8017474
AG		 827 if (efer & EFER_SVME) {
828 struct kvm_cpuid_entry2 *feat;
829
830 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 831 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
832 return 1;
d8017474
AG		 833 }
834
15c4a640 835 efer &= ~EFER_LMA;
f6801dff 836 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 837
a3d204e2
SY		 838 kvm_x86_ops->set_efer(vcpu, efer);
839
9645bb56 840 vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
b69e8cae 841
aad82703
SY		 842 /* Update reserved bits */
843 if ((efer ^ old_efer) & EFER_NX)
844 kvm_mmu_reset_context(vcpu);
845
b69e8cae 846 return 0;
15c4a640
CO		 847}
848
f2b4b7dd
JR		 849void kvm_enable_efer_bits(u64 mask)
850{
851 efer_reserved_bits &= ~mask;
852}
853EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
854
855
15c4a640
CO		 856/*
857 * Writes msr value into into the appropriate "register".
858 * Returns 0 on success, non-0 otherwise.
859 * Assumes vcpu_load() was already called.
860 */
861int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
862{
863 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
864}
865
313a3dc7
CO		 866/*
867 * Adapt set_msr() to msr_io()'s calling convention
868 */
869static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
870{
871 return kvm_set_msr(vcpu, index, *data);
872}
873
18068523
GOC		 874static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
875{
9ed3c444
AK		 876 int version;
877 int r;
50d0a0f9 878 struct pvclock_wall_clock wc;
923de3cf 879 struct timespec boot;
18068523
GOC		 880
881 if (!wall_clock)
882 return;
883
9ed3c444
AK		 884 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
885 if (r)
886 return;
887
888 if (version & 1)
889 ++version; /* first time write, random junk */
890
891 ++version;
18068523 892
18068523
GOC		 893 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
894
50d0a0f9
GH		 895 /*
896 * The guest calculates current wall clock time by adding
34c238a1 897 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 898 * wall clock specified here. guest system time equals host
899 * system time for us, thus we must fill in host boot time here.
900 */
923de3cf 901 getboottime(&boot);
50d0a0f9
GH		 902
903 wc.sec = boot.tv_sec;
904 wc.nsec = boot.tv_nsec;
905 wc.version = version;
18068523
GOC		 906
907 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
908
909 version++;
910 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 911}
912
50d0a0f9
GH		 913static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
914{
915 uint32_t quotient, remainder;
916
917 /* Don't try to replace with do_div(), this one calculates
918 * "(dividend << 32) / divisor" */
919 __asm__ ( "divl %4"
920 : "=a" (quotient), "=d" (remainder)
921 : "0" (0), "1" (dividend), "r" (divisor) );
922 return quotient;
923}
924
5f4e3f88
ZA		 925static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
926 s8 *pshift, u32 *pmultiplier)
50d0a0f9 927{
5f4e3f88 928 uint64_t scaled64;
50d0a0f9
GH		 929 int32_t shift = 0;
930 uint64_t tps64;
931 uint32_t tps32;
932
5f4e3f88
ZA		 933 tps64 = base_khz * 1000LL;
934 scaled64 = scaled_khz * 1000LL;
50933623 935 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 936 tps64 >>= 1;
937 shift--;
938 }
939
940 tps32 = (uint32_t)tps64;
50933623
JK		 941 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
942 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 943 scaled64 >>= 1;
944 else
945 tps32 <<= 1;
50d0a0f9
GH		 946 shift++;
947 }
948
5f4e3f88
ZA		 949 *pshift = shift;
950 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 951
5f4e3f88
ZA		 952 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
953 __func__, base_khz, scaled_khz, shift, *pmultiplier);
50d0a0f9
GH		 954}
955
759379dd
ZA		 956static inline u64 get_kernel_ns(void)
957{
958 struct timespec ts;
959
960 WARN_ON(preemptible());
961 ktime_get_ts(&ts);
962 monotonic_to_bootbased(&ts);
963 return timespec_to_ns(&ts);
50d0a0f9
GH		 964}
965
c8076604 966static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
c285545f 967unsigned long max_tsc_khz;
c8076604 968
8cfdc000
ZA		 969static inline int kvm_tsc_changes_freq(void)
970{
971 int cpu = get_cpu();
972 int ret = !boot_cpu_has(X86_FEATURE_CONSTANT_TSC) &&
973 cpufreq_quick_get(cpu) != 0;
974 put_cpu();
975 return ret;
976}
977
759379dd
ZA		 978static inline u64 nsec_to_cycles(u64 nsec)
979{
217fc9cf
AK		 980 u64 ret;
981
759379dd
ZA		 982 WARN_ON(preemptible());
983 if (kvm_tsc_changes_freq())
984 printk_once(KERN_WARNING
985 "kvm: unreliable cycle conversion on adjustable rate TSC\n");
217fc9cf
AK		 986 ret = nsec * __get_cpu_var(cpu_tsc_khz);
987 do_div(ret, USEC_PER_SEC);
988 return ret;
759379dd
ZA		 989}
990
c285545f
ZA		 991static void kvm_arch_set_tsc_khz(struct kvm *kvm, u32 this_tsc_khz)
992{
993 /* Compute a scale to convert nanoseconds in TSC cycles */
994 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
995 &kvm->arch.virtual_tsc_shift,
996 &kvm->arch.virtual_tsc_mult);
997 kvm->arch.virtual_tsc_khz = this_tsc_khz;
998}
999
1000static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1001{
1002 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.last_tsc_nsec,
1003 vcpu->kvm->arch.virtual_tsc_mult,
1004 vcpu->kvm->arch.virtual_tsc_shift);
1005 tsc += vcpu->arch.last_tsc_write;
1006 return tsc;
1007}
1008
99e3e30a
ZA		 1009void kvm_write_tsc(struct kvm_vcpu *vcpu, u64 data)
1010{
1011 struct kvm *kvm = vcpu->kvm;
f38e098f 1012 u64 offset, ns, elapsed;
99e3e30a 1013 unsigned long flags;
46543ba4 1014 s64 sdiff;
99e3e30a
ZA		 1015
1016 spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
1017 offset = data - native_read_tsc();
759379dd 1018 ns = get_kernel_ns();
f38e098f 1019 elapsed = ns - kvm->arch.last_tsc_nsec;
46543ba4
ZA		 1020 sdiff = data - kvm->arch.last_tsc_write;
1021 if (sdiff < 0)
1022 sdiff = -sdiff;
f38e098f
ZA		 1023
1024 /*
46543ba4 1025 * Special case: close write to TSC within 5 seconds of
f38e098f 1026 * another CPU is interpreted as an attempt to synchronize
46543ba4
ZA		 1027 * The 5 seconds is to accomodate host load / swapping as
1028 * well as any reset of TSC during the boot process.
f38e098f
ZA		 1029 *
1030 * In that case, for a reliable TSC, we can match TSC offsets,
46543ba4 1031 * or make a best guest using elapsed value.
f38e098f 1032 */
46543ba4
ZA		 1033 if (sdiff < nsec_to_cycles(5ULL * NSEC_PER_SEC) &&
1034 elapsed < 5ULL * NSEC_PER_SEC) {
f38e098f
ZA		 1035 if (!check_tsc_unstable()) {
1036 offset = kvm->arch.last_tsc_offset;
1037 pr_debug("kvm: matched tsc offset for %llu\n", data);
1038 } else {
759379dd
ZA		 1039 u64 delta = nsec_to_cycles(elapsed);
1040 offset += delta;
1041 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f
ZA		 1042 }
1043 ns = kvm->arch.last_tsc_nsec;
1044 }
1045 kvm->arch.last_tsc_nsec = ns;
1046 kvm->arch.last_tsc_write = data;
1047 kvm->arch.last_tsc_offset = offset;
99e3e30a
ZA		 1048 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1049 spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
1050
1051 /* Reset of TSC must disable overshoot protection below */
1052 vcpu->arch.hv_clock.tsc_timestamp = 0;
c285545f
ZA		 1053 vcpu->arch.last_tsc_write = data;
1054 vcpu->arch.last_tsc_nsec = ns;
99e3e30a
ZA		 1055}
1056EXPORT_SYMBOL_GPL(kvm_write_tsc);
1057
34c238a1 1058static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1059{
18068523
GOC		 1060 unsigned long flags;
1061 struct kvm_vcpu_arch *vcpu = &v->arch;
1062 void *shared_kaddr;
463656c0 1063 unsigned long this_tsc_khz;
1d5f066e
ZA		 1064 s64 kernel_ns, max_kernel_ns;
1065 u64 tsc_timestamp;
18068523 1066
18068523
GOC		 1067 /* Keep irq disabled to prevent changes to the clock */
1068 local_irq_save(flags);
1d5f066e 1069 kvm_get_msr(v, MSR_IA32_TSC, &tsc_timestamp);
759379dd 1070 kernel_ns = get_kernel_ns();
8cfdc000 1071 this_tsc_khz = __get_cpu_var(cpu_tsc_khz);
18068523 1072
8cfdc000 1073 if (unlikely(this_tsc_khz == 0)) {
c285545f 1074 local_irq_restore(flags);
34c238a1 1075 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
8cfdc000
ZA		 1076 return 1;
1077 }
18068523 1078
c285545f
ZA		 1079 /*
1080 * We may have to catch up the TSC to match elapsed wall clock
1081 * time for two reasons, even if kvmclock is used.
1082 * 1) CPU could have been running below the maximum TSC rate
1083 * 2) Broken TSC compensation resets the base at each VCPU
1084 * entry to avoid unknown leaps of TSC even when running
1085 * again on the same CPU. This may cause apparent elapsed
1086 * time to disappear, and the guest to stand still or run
1087 * very slowly.
1088 */
1089 if (vcpu->tsc_catchup) {
1090 u64 tsc = compute_guest_tsc(v, kernel_ns);
1091 if (tsc > tsc_timestamp) {
1092 kvm_x86_ops->adjust_tsc_offset(v, tsc - tsc_timestamp);
1093 tsc_timestamp = tsc;
1094 }
50d0a0f9
GH		 1095 }
1096
18068523
GOC		 1097 local_irq_restore(flags);
1098
c285545f
ZA		 1099 if (!vcpu->time_page)
1100 return 0;
18068523 1101
1d5f066e
ZA		 1102 /*
1103 * Time as measured by the TSC may go backwards when resetting the base
1104 * tsc_timestamp. The reason for this is that the TSC resolution is
1105 * higher than the resolution of the other clock scales. Thus, many
1106 * possible measurments of the TSC correspond to one measurement of any
1107 * other clock, and so a spread of values is possible. This is not a
1108 * problem for the computation of the nanosecond clock; with TSC rates
1109 * around 1GHZ, there can only be a few cycles which correspond to one
1110 * nanosecond value, and any path through this code will inevitably
1111 * take longer than that. However, with the kernel_ns value itself,
1112 * the precision may be much lower, down to HZ granularity. If the
1113 * first sampling of TSC against kernel_ns ends in the low part of the
1114 * range, and the second in the high end of the range, we can get:
1115 *
1116 * (TSC - offset_low) * S + kns_old > (TSC - offset_high) * S + kns_new
1117 *
1118 * As the sampling errors potentially range in the thousands of cycles,
1119 * it is possible such a time value has already been observed by the
1120 * guest. To protect against this, we must compute the system time as
1121 * observed by the guest and ensure the new system time is greater.
1122 */
1123 max_kernel_ns = 0;
1124 if (vcpu->hv_clock.tsc_timestamp && vcpu->last_guest_tsc) {
1125 max_kernel_ns = vcpu->last_guest_tsc -
1126 vcpu->hv_clock.tsc_timestamp;
1127 max_kernel_ns = pvclock_scale_delta(max_kernel_ns,
1128 vcpu->hv_clock.tsc_to_system_mul,
1129 vcpu->hv_clock.tsc_shift);
1130 max_kernel_ns += vcpu->last_kernel_ns;
1131 }
afbcf7ab 1132
e48672fa 1133 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
5f4e3f88
ZA		 1134 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1135 &vcpu->hv_clock.tsc_shift,
1136 &vcpu->hv_clock.tsc_to_system_mul);
e48672fa 1137 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1138 }
1139
1d5f066e
ZA		 1140 if (max_kernel_ns > kernel_ns)
1141 kernel_ns = max_kernel_ns;
1142
8cfdc000 1143 /* With all the info we got, fill in the values */
1d5f066e 1144 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1145 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1d5f066e 1146 vcpu->last_kernel_ns = kernel_ns;
28e4639a 1147 vcpu->last_guest_tsc = tsc_timestamp;
371bcf64
GC		 1148 vcpu->hv_clock.flags = 0;
1149
18068523
GOC		 1150 /*
1151 * The interface expects us to write an even number signaling that the
1152 * update is finished. Since the guest won't see the intermediate
50d0a0f9 1153 * state, we just increase by 2 at the end.
18068523 1154 */
50d0a0f9 1155 vcpu->hv_clock.version += 2;
18068523
GOC		 1156
1157 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
1158
1159 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
50d0a0f9 1160 sizeof(vcpu->hv_clock));
18068523
GOC		 1161
1162 kunmap_atomic(shared_kaddr, KM_USER0);
1163
1164 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
8cfdc000 1165 return 0;
c8076604
GH		 1166}
1167
9ba075a6
AK		 1168static bool msr_mtrr_valid(unsigned msr)
1169{
1170 switch (msr) {
1171 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1172 case MSR_MTRRfix64K_00000:
1173 case MSR_MTRRfix16K_80000:
1174 case MSR_MTRRfix16K_A0000:
1175 case MSR_MTRRfix4K_C0000:
1176 case MSR_MTRRfix4K_C8000:
1177 case MSR_MTRRfix4K_D0000:
1178 case MSR_MTRRfix4K_D8000:
1179 case MSR_MTRRfix4K_E0000:
1180 case MSR_MTRRfix4K_E8000:
1181 case MSR_MTRRfix4K_F0000:
1182 case MSR_MTRRfix4K_F8000:
1183 case MSR_MTRRdefType:
1184 case MSR_IA32_CR_PAT:
1185 return true;
1186 case 0x2f8:
1187 return true;
1188 }
1189 return false;
1190}
1191
d6289b93
MT		 1192static bool valid_pat_type(unsigned t)
1193{
1194 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1195}
1196
1197static bool valid_mtrr_type(unsigned t)
1198{
1199 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1200}
1201
1202static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1203{
1204 int i;
1205
1206 if (!msr_mtrr_valid(msr))
1207 return false;
1208
1209 if (msr == MSR_IA32_CR_PAT) {
1210 for (i = 0; i < 8; i++)
1211 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1212 return false;
1213 return true;
1214 } else if (msr == MSR_MTRRdefType) {
1215 if (data & ~0xcff)
1216 return false;
1217 return valid_mtrr_type(data & 0xff);
1218 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1219 for (i = 0; i < 8 ; i++)
1220 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1221 return false;
1222 return true;
1223 }
1224
1225 /* variable MTRRs */
1226 return valid_mtrr_type(data & 0xff);
1227}
1228
9ba075a6
AK		 1229static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1230{
0bed3b56
SY		 1231 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1232
d6289b93 1233 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 1234 return 1;
1235
0bed3b56
SY		 1236 if (msr == MSR_MTRRdefType) {
1237 vcpu->arch.mtrr_state.def_type = data;
1238 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1239 } else if (msr == MSR_MTRRfix64K_00000)
1240 p[0] = data;
1241 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1242 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1243 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1244 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1245 else if (msr == MSR_IA32_CR_PAT)
1246 vcpu->arch.pat = data;
1247 else { /* Variable MTRRs */
1248 int idx, is_mtrr_mask;
1249 u64 *pt;
1250
1251 idx = (msr - 0x200) / 2;
1252 is_mtrr_mask = msr - 0x200 - 2 * idx;
1253 if (!is_mtrr_mask)
1254 pt =
1255 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1256 else
1257 pt =
1258 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1259 *pt = data;
1260 }
1261
1262 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 1263 return 0;
1264}
15c4a640 1265
890ca9ae 1266static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1267{
890ca9ae
HY		 1268 u64 mcg_cap = vcpu->arch.mcg_cap;
1269 unsigned bank_num = mcg_cap & 0xff;
1270
15c4a640 1271 switch (msr) {
15c4a640 1272 case MSR_IA32_MCG_STATUS:
890ca9ae 1273 vcpu->arch.mcg_status = data;
15c4a640 1274 break;
c7ac679c 1275 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1276 if (!(mcg_cap & MCG_CTL_P))
1277 return 1;
1278 if (data != 0 && data != ~(u64)0)
1279 return -1;
1280 vcpu->arch.mcg_ctl = data;
1281 break;
1282 default:
1283 if (msr >= MSR_IA32_MC0_CTL &&
1284 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1285 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1286 /* only 0 or all 1s can be written to IA32_MCi_CTL
1287 * some Linux kernels though clear bit 10 in bank 4 to
1288 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1289 * this to avoid an uncatched #GP in the guest
1290 */
890ca9ae 1291 if ((offset & 0x3) == 0 &&
114be429 1292 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1293 return -1;
1294 vcpu->arch.mce_banks[offset] = data;
1295 break;
1296 }
1297 return 1;
1298 }
1299 return 0;
1300}
1301
ffde22ac
ES		 1302static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1303{
1304 struct kvm *kvm = vcpu->kvm;
1305 int lm = is_long_mode(vcpu);
1306 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1307 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1308 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1309 : kvm->arch.xen_hvm_config.blob_size_32;
1310 u32 page_num = data & ~PAGE_MASK;
1311 u64 page_addr = data & PAGE_MASK;
1312 u8 *page;
1313 int r;
1314
1315 r = -E2BIG;
1316 if (page_num >= blob_size)
1317 goto out;
1318 r = -ENOMEM;
1319 page = kzalloc(PAGE_SIZE, GFP_KERNEL);
1320 if (!page)
1321 goto out;
1322 r = -EFAULT;
1323 if (copy_from_user(page, blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE))
1324 goto out_free;
1325 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1326 goto out_free;
1327 r = 0;
1328out_free:
1329 kfree(page);
1330out:
1331 return r;
1332}
1333
55cd8e5a
GN		 1334static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1335{
1336 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1337}
1338
1339static bool kvm_hv_msr_partition_wide(u32 msr)
1340{
1341 bool r = false;
1342 switch (msr) {
1343 case HV_X64_MSR_GUEST_OS_ID:
1344 case HV_X64_MSR_HYPERCALL:
1345 r = true;
1346 break;
1347 }
1348
1349 return r;
1350}
1351
1352static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1353{
1354 struct kvm *kvm = vcpu->kvm;
1355
1356 switch (msr) {
1357 case HV_X64_MSR_GUEST_OS_ID:
1358 kvm->arch.hv_guest_os_id = data;
1359 /* setting guest os id to zero disables hypercall page */
1360 if (!kvm->arch.hv_guest_os_id)
1361 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1362 break;
1363 case HV_X64_MSR_HYPERCALL: {
1364 u64 gfn;
1365 unsigned long addr;
1366 u8 instructions[4];
1367
1368 /* if guest os id is not set hypercall should remain disabled */
1369 if (!kvm->arch.hv_guest_os_id)
1370 break;
1371 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1372 kvm->arch.hv_hypercall = data;
1373 break;
1374 }
1375 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1376 addr = gfn_to_hva(kvm, gfn);
1377 if (kvm_is_error_hva(addr))
1378 return 1;
1379 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1380 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
1381 if (copy_to_user((void __user *)addr, instructions, 4))
1382 return 1;
1383 kvm->arch.hv_hypercall = data;
1384 break;
1385 }
1386 default:
1387 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1388 "data 0x%llx\n", msr, data);
1389 return 1;
1390 }
1391 return 0;
1392}
1393
1394static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1395{
10388a07
GN		 1396 switch (msr) {
1397 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1398 unsigned long addr;
55cd8e5a 1399
10388a07
GN		 1400 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1401 vcpu->arch.hv_vapic = data;
1402 break;
1403 }
1404 addr = gfn_to_hva(vcpu->kvm, data >>
1405 HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1406 if (kvm_is_error_hva(addr))
1407 return 1;
1408 if (clear_user((void __user *)addr, PAGE_SIZE))
1409 return 1;
1410 vcpu->arch.hv_vapic = data;
1411 break;
1412 }
1413 case HV_X64_MSR_EOI:
1414 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1415 case HV_X64_MSR_ICR:
1416 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1417 case HV_X64_MSR_TPR:
1418 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1419 default:
1420 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1421 "data 0x%llx\n", msr, data);
1422 return 1;
1423 }
1424
1425 return 0;
55cd8e5a
GN		 1426}
1427
344d9588
GN		 1428static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1429{
1430 gpa_t gpa = data & ~0x3f;
1431
6adba527
GN		 1432 /* Bits 2:5 are resrved, Should be zero */
1433 if (data & 0x3c)
344d9588
GN		 1434 return 1;
1435
1436 vcpu->arch.apf.msr_val = data;
1437
1438 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1439 kvm_clear_async_pf_completion_queue(vcpu);
1440 kvm_async_pf_hash_reset(vcpu);
1441 return 0;
1442 }
1443
1444 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa))
1445 return 1;
1446
6adba527 1447 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 1448 kvm_async_pf_wakeup_all(vcpu);
1449 return 0;
1450}
1451
15c4a640
CO		 1452int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1453{
1454 switch (msr) {
15c4a640 1455 case MSR_EFER:
b69e8cae 1456 return set_efer(vcpu, data);
8f1589d9
AP		 1457 case MSR_K7_HWCR:
1458 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 1459 data &= ~(u64)0x100; /* ignore ignne emulation enable */
8f1589d9
AP		 1460 if (data != 0) {
1461 pr_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1462 data);
1463 return 1;
1464 }
15c4a640 1465 break;
f7c6d140
AP		 1466 case MSR_FAM10H_MMIO_CONF_BASE:
1467 if (data != 0) {
1468 pr_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1469 "0x%llx\n", data);
1470 return 1;
1471 }
15c4a640 1472 break;
c323c0e5 1473 case MSR_AMD64_NB_CFG:
c7ac679c 1474 break;
b5e2fec0
AG		 1475 case MSR_IA32_DEBUGCTLMSR:
1476 if (!data) {
1477 /* We support the non-activated case already */
1478 break;
1479 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1480 /* Values other than LBR and BTF are vendor-specific,
1481 thus reserved and should throw a #GP */
1482 return 1;
1483 }
1484 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1485 __func__, data);
1486 break;
15c4a640
CO		 1487 case MSR_IA32_UCODE_REV:
1488 case MSR_IA32_UCODE_WRITE:
61a6bd67 1489 case MSR_VM_HSAVE_PA:
6098ca93 1490 case MSR_AMD64_PATCH_LOADER:
15c4a640 1491 break;
9ba075a6
AK		 1492 case 0x200 ... 0x2ff:
1493 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 1494 case MSR_IA32_APICBASE:
1495 kvm_set_apic_base(vcpu, data);
1496 break;
0105d1a5
GN		 1497 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1498 return kvm_x2apic_msr_write(vcpu, msr, data);
15c4a640 1499 case MSR_IA32_MISC_ENABLE:
ad312c7c 1500 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 1501 break;
11c6bffa 1502 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1503 case MSR_KVM_WALL_CLOCK:
1504 vcpu->kvm->arch.wall_clock = data;
1505 kvm_write_wall_clock(vcpu->kvm, data);
1506 break;
11c6bffa 1507 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 1508 case MSR_KVM_SYSTEM_TIME: {
1509 if (vcpu->arch.time_page) {
1510 kvm_release_page_dirty(vcpu->arch.time_page);
1511 vcpu->arch.time_page = NULL;
1512 }
1513
1514 vcpu->arch.time = data;
c285545f 1515 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
18068523
GOC		 1516
1517 /* we verify if the enable bit is set... */
1518 if (!(data & 1))
1519 break;
1520
1521 /* ...but clean it before doing the actual write */
1522 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
1523
18068523
GOC		 1524 vcpu->arch.time_page =
1525 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
18068523
GOC		 1526
1527 if (is_error_page(vcpu->arch.time_page)) {
1528 kvm_release_page_clean(vcpu->arch.time_page);
1529 vcpu->arch.time_page = NULL;
1530 }
18068523
GOC		 1531 break;
1532 }
344d9588
GN		 1533 case MSR_KVM_ASYNC_PF_EN:
1534 if (kvm_pv_enable_async_pf(vcpu, data))
1535 return 1;
1536 break;
890ca9ae
HY		 1537 case MSR_IA32_MCG_CTL:
1538 case MSR_IA32_MCG_STATUS:
1539 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1540 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 1541
1542 /* Performance counters are not protected by a CPUID bit,
1543 * so we should check all of them in the generic path for the sake of
1544 * cross vendor migration.
1545 * Writing a zero into the event select MSRs disables them,
1546 * which we perfectly emulate ;-). Any other value should be at least
1547 * reported, some guests depend on them.
1548 */
1549 case MSR_P6_EVNTSEL0:
1550 case MSR_P6_EVNTSEL1:
1551 case MSR_K7_EVNTSEL0:
1552 case MSR_K7_EVNTSEL1:
1553 case MSR_K7_EVNTSEL2:
1554 case MSR_K7_EVNTSEL3:
1555 if (data != 0)
1556 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1557 "0x%x data 0x%llx\n", msr, data);
1558 break;
1559 /* at least RHEL 4 unconditionally writes to the perfctr registers,
1560 * so we ignore writes to make it happy.
1561 */
1562 case MSR_P6_PERFCTR0:
1563 case MSR_P6_PERFCTR1:
1564 case MSR_K7_PERFCTR0:
1565 case MSR_K7_PERFCTR1:
1566 case MSR_K7_PERFCTR2:
1567 case MSR_K7_PERFCTR3:
1568 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1569 "0x%x data 0x%llx\n", msr, data);
1570 break;
84e0cefa
JS		 1571 case MSR_K7_CLK_CTL:
1572 /*
1573 * Ignore all writes to this no longer documented MSR.
1574 * Writes are only relevant for old K7 processors,
1575 * all pre-dating SVM, but a recommended workaround from
1576 * AMD for these chips. It is possible to speicify the
1577 * affected processor models on the command line, hence
1578 * the need to ignore the workaround.
1579 */
1580 break;
55cd8e5a
GN		 1581 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1582 if (kvm_hv_msr_partition_wide(msr)) {
1583 int r;
1584 mutex_lock(&vcpu->kvm->lock);
1585 r = set_msr_hyperv_pw(vcpu, msr, data);
1586 mutex_unlock(&vcpu->kvm->lock);
1587 return r;
1588 } else
1589 return set_msr_hyperv(vcpu, msr, data);
1590 break;
15c4a640 1591 default:
ffde22ac
ES		 1592 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
1593 return xen_hvm_config(vcpu, data);
ed85c068
AP		 1594 if (!ignore_msrs) {
1595 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
1596 msr, data);
1597 return 1;
1598 } else {
1599 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
1600 msr, data);
1601 break;
1602 }
15c4a640
CO		 1603 }
1604 return 0;
1605}
1606EXPORT_SYMBOL_GPL(kvm_set_msr_common);
1607
1608
1609/*
1610 * Reads an msr value (of 'msr_index') into 'pdata'.
1611 * Returns 0 on success, non-0 otherwise.
1612 * Assumes vcpu_load() was already called.
1613 */
1614int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1615{
1616 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
1617}
1618
9ba075a6
AK		 1619static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1620{
0bed3b56
SY		 1621 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1622
9ba075a6
AK		 1623 if (!msr_mtrr_valid(msr))
1624 return 1;
1625
0bed3b56
SY		 1626 if (msr == MSR_MTRRdefType)
1627 *pdata = vcpu->arch.mtrr_state.def_type +
1628 (vcpu->arch.mtrr_state.enabled << 10);
1629 else if (msr == MSR_MTRRfix64K_00000)
1630 *pdata = p[0];
1631 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1632 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
1633 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1634 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
1635 else if (msr == MSR_IA32_CR_PAT)
1636 *pdata = vcpu->arch.pat;
1637 else { /* Variable MTRRs */
1638 int idx, is_mtrr_mask;
1639 u64 *pt;
1640
1641 idx = (msr - 0x200) / 2;
1642 is_mtrr_mask = msr - 0x200 - 2 * idx;
1643 if (!is_mtrr_mask)
1644 pt =
1645 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1646 else
1647 pt =
1648 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1649 *pdata = *pt;
1650 }
1651
9ba075a6
AK		 1652 return 0;
1653}
1654
890ca9ae 1655static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 1656{
1657 u64 data;
890ca9ae
HY		 1658 u64 mcg_cap = vcpu->arch.mcg_cap;
1659 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 1660
1661 switch (msr) {
15c4a640
CO		 1662 case MSR_IA32_P5_MC_ADDR:
1663 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 1664 data = 0;
1665 break;
15c4a640 1666 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 1667 data = vcpu->arch.mcg_cap;
1668 break;
c7ac679c 1669 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1670 if (!(mcg_cap & MCG_CTL_P))
1671 return 1;
1672 data = vcpu->arch.mcg_ctl;
1673 break;
1674 case MSR_IA32_MCG_STATUS:
1675 data = vcpu->arch.mcg_status;
1676 break;
1677 default:
1678 if (msr >= MSR_IA32_MC0_CTL &&
1679 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1680 u32 offset = msr - MSR_IA32_MC0_CTL;
1681 data = vcpu->arch.mce_banks[offset];
1682 break;
1683 }
1684 return 1;
1685 }
1686 *pdata = data;
1687 return 0;
1688}
1689
55cd8e5a
GN		 1690static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1691{
1692 u64 data = 0;
1693 struct kvm *kvm = vcpu->kvm;
1694
1695 switch (msr) {
1696 case HV_X64_MSR_GUEST_OS_ID:
1697 data = kvm->arch.hv_guest_os_id;
1698 break;
1699 case HV_X64_MSR_HYPERCALL:
1700 data = kvm->arch.hv_hypercall;
1701 break;
1702 default:
1703 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1704 return 1;
1705 }
1706
1707 *pdata = data;
1708 return 0;
1709}
1710
1711static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1712{
1713 u64 data = 0;
1714
1715 switch (msr) {
1716 case HV_X64_MSR_VP_INDEX: {
1717 int r;
1718 struct kvm_vcpu *v;
1719 kvm_for_each_vcpu(r, v, vcpu->kvm)
1720 if (v == vcpu)
1721 data = r;
1722 break;
1723 }
10388a07
GN		 1724 case HV_X64_MSR_EOI:
1725 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
1726 case HV_X64_MSR_ICR:
1727 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
1728 case HV_X64_MSR_TPR:
1729 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
55cd8e5a
GN		 1730 default:
1731 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1732 return 1;
1733 }
1734 *pdata = data;
1735 return 0;
1736}
1737
890ca9ae
HY		 1738int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1739{
1740 u64 data;
1741
1742 switch (msr) {
890ca9ae 1743 case MSR_IA32_PLATFORM_ID:
15c4a640 1744 case MSR_IA32_UCODE_REV:
15c4a640 1745 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 1746 case MSR_IA32_DEBUGCTLMSR:
1747 case MSR_IA32_LASTBRANCHFROMIP:
1748 case MSR_IA32_LASTBRANCHTOIP:
1749 case MSR_IA32_LASTINTFROMIP:
1750 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 1751 case MSR_K8_SYSCFG:
1752 case MSR_K7_HWCR:
61a6bd67 1753 case MSR_VM_HSAVE_PA:
1f3ee616
AS		 1754 case MSR_P6_PERFCTR0:
1755 case MSR_P6_PERFCTR1:
7fe29e0f
AS		 1756 case MSR_P6_EVNTSEL0:
1757 case MSR_P6_EVNTSEL1:
9e699624 1758 case MSR_K7_EVNTSEL0:
1f3ee616 1759 case MSR_K7_PERFCTR0:
1fdbd48c 1760 case MSR_K8_INT_PENDING_MSG:
c323c0e5 1761 case MSR_AMD64_NB_CFG:
f7c6d140 1762 case MSR_FAM10H_MMIO_CONF_BASE:
15c4a640
CO		 1763 data = 0;
1764 break;
9ba075a6
AK		 1765 case MSR_MTRRcap:
1766 data = 0x500 | KVM_NR_VAR_MTRR;
1767 break;
1768 case 0x200 ... 0x2ff:
1769 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 1770 case 0xcd: /* fsb frequency */
1771 data = 3;
1772 break;
7b914098
JS		 1773 /*
1774 * MSR_EBC_FREQUENCY_ID
1775 * Conservative value valid for even the basic CPU models.
1776 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
1777 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
1778 * and 266MHz for model 3, or 4. Set Core Clock
1779 * Frequency to System Bus Frequency Ratio to 1 (bits
1780 * 31:24) even though these are only valid for CPU
1781 * models > 2, however guests may end up dividing or
1782 * multiplying by zero otherwise.
1783 */
1784 case MSR_EBC_FREQUENCY_ID:
1785 data = 1 << 24;
1786 break;
15c4a640
CO		 1787 case MSR_IA32_APICBASE:
1788 data = kvm_get_apic_base(vcpu);
1789 break;
0105d1a5
GN		 1790 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1791 return kvm_x2apic_msr_read(vcpu, msr, pdata);
1792 break;
15c4a640 1793 case MSR_IA32_MISC_ENABLE:
ad312c7c 1794 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 1795 break;
847f0ad8
AG		 1796 case MSR_IA32_PERF_STATUS:
1797 /* TSC increment by tick */
1798 data = 1000ULL;
1799 /* CPU multiplier */
1800 data |= (((uint64_t)4ULL) << 40);
1801 break;
15c4a640 1802 case MSR_EFER:
f6801dff 1803 data = vcpu->arch.efer;
15c4a640 1804 break;
18068523 1805 case MSR_KVM_WALL_CLOCK:
11c6bffa 1806 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1807 data = vcpu->kvm->arch.wall_clock;
1808 break;
1809 case MSR_KVM_SYSTEM_TIME:
11c6bffa 1810 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 1811 data = vcpu->arch.time;
1812 break;
344d9588
GN		 1813 case MSR_KVM_ASYNC_PF_EN:
1814 data = vcpu->arch.apf.msr_val;
1815 break;
890ca9ae
HY		 1816 case MSR_IA32_P5_MC_ADDR:
1817 case MSR_IA32_P5_MC_TYPE:
1818 case MSR_IA32_MCG_CAP:
1819 case MSR_IA32_MCG_CTL:
1820 case MSR_IA32_MCG_STATUS:
1821 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1822 return get_msr_mce(vcpu, msr, pdata);
84e0cefa
JS		 1823 case MSR_K7_CLK_CTL:
1824 /*
1825 * Provide expected ramp-up count for K7. All other
1826 * are set to zero, indicating minimum divisors for
1827 * every field.
1828 *
1829 * This prevents guest kernels on AMD host with CPU
1830 * type 6, model 8 and higher from exploding due to
1831 * the rdmsr failing.
1832 */
1833 data = 0x20000000;
1834 break;
55cd8e5a
GN		 1835 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1836 if (kvm_hv_msr_partition_wide(msr)) {
1837 int r;
1838 mutex_lock(&vcpu->kvm->lock);
1839 r = get_msr_hyperv_pw(vcpu, msr, pdata);
1840 mutex_unlock(&vcpu->kvm->lock);
1841 return r;
1842 } else
1843 return get_msr_hyperv(vcpu, msr, pdata);
1844 break;
15c4a640 1845 default:
ed85c068
AP		 1846 if (!ignore_msrs) {
1847 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
1848 return 1;
1849 } else {
1850 pr_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
1851 data = 0;
1852 }
1853 break;
15c4a640
CO		 1854 }
1855 *pdata = data;
1856 return 0;
1857}
1858EXPORT_SYMBOL_GPL(kvm_get_msr_common);
1859
313a3dc7
CO		 1860/*
1861 * Read or write a bunch of msrs. All parameters are kernel addresses.
1862 *
1863 * @return number of msrs set successfully.
1864 */
1865static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
1866 struct kvm_msr_entry *entries,
1867 int (*do_msr)(struct kvm_vcpu *vcpu,
1868 unsigned index, u64 *data))
1869{
f656ce01 1870 int i, idx;
313a3dc7 1871
f656ce01 1872 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 1873 for (i = 0; i < msrs->nmsrs; ++i)
1874 if (do_msr(vcpu, entries[i].index, &entries[i].data))
1875 break;
f656ce01 1876 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 1877
313a3dc7
CO		 1878 return i;
1879}
1880
1881/*
1882 * Read or write a bunch of msrs. Parameters are user addresses.
1883 *
1884 * @return number of msrs set successfully.
1885 */
1886static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
1887 int (*do_msr)(struct kvm_vcpu *vcpu,
1888 unsigned index, u64 *data),
1889 int writeback)
1890{
1891 struct kvm_msrs msrs;
1892 struct kvm_msr_entry *entries;
1893 int r, n;
1894 unsigned size;
1895
1896 r = -EFAULT;
1897 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
1898 goto out;
1899
1900 r = -E2BIG;
1901 if (msrs.nmsrs >= MAX_IO_MSRS)
1902 goto out;
1903
1904 r = -ENOMEM;
1905 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
7a73c028 1906 entries = kmalloc(size, GFP_KERNEL);
313a3dc7
CO		 1907 if (!entries)
1908 goto out;
1909
1910 r = -EFAULT;
1911 if (copy_from_user(entries, user_msrs->entries, size))
1912 goto out_free;
1913
1914 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
1915 if (r < 0)
1916 goto out_free;
1917
1918 r = -EFAULT;
1919 if (writeback && copy_to_user(user_msrs->entries, entries, size))
1920 goto out_free;
1921
1922 r = n;
1923
1924out_free:
7a73c028 1925 kfree(entries);
313a3dc7
CO		 1926out:
1927 return r;
1928}
1929
018d00d2
ZX		 1930int kvm_dev_ioctl_check_extension(long ext)
1931{
1932 int r;
1933
1934 switch (ext) {
1935 case KVM_CAP_IRQCHIP:
1936 case KVM_CAP_HLT:
1937 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 1938 case KVM_CAP_SET_TSS_ADDR:
07716717 1939 case KVM_CAP_EXT_CPUID:
c8076604 1940 case KVM_CAP_CLOCKSOURCE:
7837699f 1941 case KVM_CAP_PIT:
a28e4f5a 1942 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 1943 case KVM_CAP_MP_STATE:
ed848624 1944 case KVM_CAP_SYNC_MMU:
52d939a0 1945 case KVM_CAP_REINJECT_CONTROL:
4925663a 1946 case KVM_CAP_IRQ_INJECT_STATUS:
e56d532f 1947 case KVM_CAP_ASSIGN_DEV_IRQ:
721eecbf 1948 case KVM_CAP_IRQFD:
d34e6b17 1949 case KVM_CAP_IOEVENTFD:
c5ff41ce 1950 case KVM_CAP_PIT2:
e9f42757 1951 case KVM_CAP_PIT_STATE2:
b927a3ce 1952 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 1953 case KVM_CAP_XEN_HVM:
afbcf7ab 1954 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 1955 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 1956 case KVM_CAP_HYPERV:
10388a07 1957 case KVM_CAP_HYPERV_VAPIC:
c25bc163 1958 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 1959 case KVM_CAP_PCI_SEGMENT:
a1efbe77 1960 case KVM_CAP_DEBUGREGS:
d2be1651 1961 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 1962 case KVM_CAP_XSAVE:
344d9588 1963 case KVM_CAP_ASYNC_PF:
018d00d2
ZX		 1964 r = 1;
1965 break;
542472b5
LV		 1966 case KVM_CAP_COALESCED_MMIO:
1967 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
1968 break;
774ead3a
AK		 1969 case KVM_CAP_VAPIC:
1970 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
1971 break;
f725230a
AK		 1972 case KVM_CAP_NR_VCPUS:
1973 r = KVM_MAX_VCPUS;
1974 break;
a988b910
AK		 1975 case KVM_CAP_NR_MEMSLOTS:
1976 r = KVM_MEMORY_SLOTS;
1977 break;
a68a6a72
MT		 1978 case KVM_CAP_PV_MMU: /* obsolete */
1979 r = 0;
2f333bcb 1980 break;
62c476c7 1981 case KVM_CAP_IOMMU:
19de40a8 1982 r = iommu_found();
62c476c7 1983 break;
890ca9ae
HY		 1984 case KVM_CAP_MCE:
1985 r = KVM_MAX_MCE_BANKS;
1986 break;
2d5b5a66
SY		 1987 case KVM_CAP_XCRS:
1988 r = cpu_has_xsave;
1989 break;
018d00d2
ZX		 1990 default:
1991 r = 0;
1992 break;
1993 }
1994 return r;
1995
1996}
1997
043405e1
CO		 1998long kvm_arch_dev_ioctl(struct file *filp,
1999 unsigned int ioctl, unsigned long arg)
2000{
2001 void __user *argp = (void __user *)arg;
2002 long r;
2003
2004 switch (ioctl) {
2005 case KVM_GET_MSR_INDEX_LIST: {
2006 struct kvm_msr_list __user *user_msr_list = argp;
2007 struct kvm_msr_list msr_list;
2008 unsigned n;
2009
2010 r = -EFAULT;
2011 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2012 goto out;
2013 n = msr_list.nmsrs;
2014 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2015 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2016 goto out;
2017 r = -E2BIG;
e125e7b6 2018 if (n < msr_list.nmsrs)
043405e1
CO		 2019 goto out;
2020 r = -EFAULT;
2021 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2022 num_msrs_to_save * sizeof(u32)))
2023 goto out;
e125e7b6 2024 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 2025 &emulated_msrs,
2026 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2027 goto out;
2028 r = 0;
2029 break;
2030 }
674eea0f
AK		 2031 case KVM_GET_SUPPORTED_CPUID: {
2032 struct kvm_cpuid2 __user *cpuid_arg = argp;
2033 struct kvm_cpuid2 cpuid;
2034
2035 r = -EFAULT;
2036 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2037 goto out;
2038 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
19355475 2039 cpuid_arg->entries);
674eea0f
AK		 2040 if (r)
2041 goto out;
2042
2043 r = -EFAULT;
2044 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2045 goto out;
2046 r = 0;
2047 break;
2048 }
890ca9ae
HY		 2049 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2050 u64 mce_cap;
2051
2052 mce_cap = KVM_MCE_CAP_SUPPORTED;
2053 r = -EFAULT;
2054 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2055 goto out;
2056 r = 0;
2057 break;
2058 }
043405e1
CO		 2059 default:
2060 r = -EINVAL;
2061 }
2062out:
2063 return r;
2064}
2065
f5f48ee1
SY		 2066static void wbinvd_ipi(void *garbage)
2067{
2068 wbinvd();
2069}
2070
2071static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2072{
2073 return vcpu->kvm->arch.iommu_domain &&
2074 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY);
2075}
2076
313a3dc7
CO		 2077void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2078{
f5f48ee1
SY		 2079 /* Address WBINVD may be executed by guest */
2080 if (need_emulate_wbinvd(vcpu)) {
2081 if (kvm_x86_ops->has_wbinvd_exit())
2082 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2083 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2084 smp_call_function_single(vcpu->cpu,
2085 wbinvd_ipi, NULL, 1);
2086 }
2087
313a3dc7 2088 kvm_x86_ops->vcpu_load(vcpu, cpu);
48434c20 2089 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
e48672fa
ZA		 2090 /* Make sure TSC doesn't go backwards */
2091 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2092 native_read_tsc() - vcpu->arch.last_host_tsc;
2093 if (tsc_delta < 0)
2094 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 2095 if (check_tsc_unstable()) {
e48672fa 2096 kvm_x86_ops->adjust_tsc_offset(vcpu, -tsc_delta);
c285545f
ZA		 2097 vcpu->arch.tsc_catchup = 1;
2098 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2099 }
2100 if (vcpu->cpu != cpu)
2101 kvm_migrate_timers(vcpu);
e48672fa 2102 vcpu->cpu = cpu;
6b7d7e76 2103 }
313a3dc7
CO		 2104}
2105
2106void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2107{
02daab21 2108 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2109 kvm_put_guest_fpu(vcpu);
e48672fa 2110 vcpu->arch.last_host_tsc = native_read_tsc();
313a3dc7
CO		 2111}
2112
07716717 2113static int is_efer_nx(void)
313a3dc7 2114{
e286e86e 2115 unsigned long long efer = 0;
313a3dc7 2116
e286e86e 2117 rdmsrl_safe(MSR_EFER, &efer);
07716717
DK		 2118 return efer & EFER_NX;
2119}
2120
2121static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
2122{
2123 int i;
2124 struct kvm_cpuid_entry2 *e, *entry;
2125
313a3dc7 2126 entry = NULL;
ad312c7c
ZX		 2127 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
2128 e = &vcpu->arch.cpuid_entries[i];
313a3dc7
CO		 2129 if (e->function == 0x80000001) {
2130 entry = e;
2131 break;
2132 }
2133 }
07716717 2134 if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) {
313a3dc7
CO		 2135 entry->edx &= ~(1 << 20);
2136 printk(KERN_INFO "kvm: guest NX capability removed\n");
2137 }
2138}
2139
07716717 2140/* when an old userspace process fills a new kernel module */
313a3dc7
CO		 2141static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
2142 struct kvm_cpuid *cpuid,
2143 struct kvm_cpuid_entry __user *entries)
07716717
DK		 2144{
2145 int r, i;
2146 struct kvm_cpuid_entry *cpuid_entries;
2147
2148 r = -E2BIG;
2149 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2150 goto out;
2151 r = -ENOMEM;
2152 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent);
2153 if (!cpuid_entries)
2154 goto out;
2155 r = -EFAULT;
2156 if (copy_from_user(cpuid_entries, entries,
2157 cpuid->nent * sizeof(struct kvm_cpuid_entry)))
2158 goto out_free;
2159 for (i = 0; i < cpuid->nent; i++) {
ad312c7c
ZX		 2160 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
2161 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
2162 vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx;
2163 vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx;
2164 vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx;
2165 vcpu->arch.cpuid_entries[i].index = 0;
2166 vcpu->arch.cpuid_entries[i].flags = 0;
2167 vcpu->arch.cpuid_entries[i].padding[0] = 0;
2168 vcpu->arch.cpuid_entries[i].padding[1] = 0;
2169 vcpu->arch.cpuid_entries[i].padding[2] = 0;
2170 }
2171 vcpu->arch.cpuid_nent = cpuid->nent;
07716717
DK		 2172 cpuid_fix_nx_cap(vcpu);
2173 r = 0;
fc61b800 2174 kvm_apic_set_version(vcpu);
0e851880 2175 kvm_x86_ops->cpuid_update(vcpu);
2acf923e 2176 update_cpuid(vcpu);
07716717
DK		 2177
2178out_free:
2179 vfree(cpuid_entries);
2180out:
2181 return r;
2182}
2183
2184static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 2185 struct kvm_cpuid2 *cpuid,
2186 struct kvm_cpuid_entry2 __user *entries)
313a3dc7
CO		 2187{
2188 int r;
2189
2190 r = -E2BIG;
2191 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2192 goto out;
2193 r = -EFAULT;
ad312c7c 2194 if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
07716717 2195 cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
313a3dc7 2196 goto out;
ad312c7c 2197 vcpu->arch.cpuid_nent = cpuid->nent;
fc61b800 2198 kvm_apic_set_version(vcpu);
0e851880 2199 kvm_x86_ops->cpuid_update(vcpu);
2acf923e 2200 update_cpuid(vcpu);
313a3dc7
CO		 2201 return 0;
2202
2203out:
2204 return r;
2205}
2206
07716717 2207static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 2208 struct kvm_cpuid2 *cpuid,
2209 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 2210{
2211 int r;
2212
2213 r = -E2BIG;
ad312c7c 2214 if (cpuid->nent < vcpu->arch.cpuid_nent)
07716717
DK		 2215 goto out;
2216 r = -EFAULT;
ad312c7c 2217 if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
19355475 2218 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 2219 goto out;
2220 return 0;
2221
2222out:
ad312c7c 2223 cpuid->nent = vcpu->arch.cpuid_nent;
07716717
DK		 2224 return r;
2225}
2226
07716717 2227static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function,
19355475 2228 u32 index)
07716717
DK		 2229{
2230 entry->function = function;
2231 entry->index = index;
2232 cpuid_count(entry->function, entry->index,
19355475 2233 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
07716717
DK		 2234 entry->flags = 0;
2235}
2236
7faa4ee1
AK		 2237#define F(x) bit(X86_FEATURE_##x)
2238
07716717
DK		 2239static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
2240 u32 index, int *nent, int maxnent)
2241{
7faa4ee1 2242 unsigned f_nx = is_efer_nx() ? F(NX) : 0;
07716717 2243#ifdef CONFIG_X86_64
17cc3935
SY		 2244 unsigned f_gbpages = (kvm_x86_ops->get_lpage_level() == PT_PDPE_LEVEL)
2245 ? F(GBPAGES) : 0;
7faa4ee1
AK		 2246 unsigned f_lm = F(LM);
2247#else
17cc3935 2248 unsigned f_gbpages = 0;
7faa4ee1 2249 unsigned f_lm = 0;
07716717 2250#endif
4e47c7a6 2251 unsigned f_rdtscp = kvm_x86_ops->rdtscp_supported() ? F(RDTSCP) : 0;
7faa4ee1
AK		 2252
2253 /* cpuid 1.edx */
2254 const u32 kvm_supported_word0_x86_features =
2255 F(FPU) | F(VME) | F(DE) | F(PSE) |
2256 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
2257 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) |
2258 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
2259 F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLSH) |
2260 0 /* Reserved, DS, ACPI */ | F(MMX) |
2261 F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) |
2262 0 /* HTT, TM, Reserved, PBE */;
2263 /* cpuid 0x80000001.edx */
2264 const u32 kvm_supported_word1_x86_features =
2265 F(FPU) | F(VME) | F(DE) | F(PSE) |
2266 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
2267 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) |
2268 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
2269 F(PAT) | F(PSE36) | 0 /* Reserved */ |
2270 f_nx | 0 /* Reserved */ | F(MMXEXT) | F(MMX) |
4e47c7a6 2271 F(FXSR) | F(FXSR_OPT) | f_gbpages | f_rdtscp |
7faa4ee1
AK		 2272 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW);
2273 /* cpuid 1.ecx */
2274 const u32 kvm_supported_word4_x86_features =
6c3f6041 2275 F(XMM3) | F(PCLMULQDQ) | 0 /* DTES64, MONITOR */ |
d149c731
AK		 2276 0 /* DS-CPL, VMX, SMX, EST */ |
2277 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ |
2278 0 /* Reserved */ | F(CX16) | 0 /* xTPR Update, PDCM */ |
2279 0 /* Reserved, DCA */ | F(XMM4_1) |
0105d1a5 2280 F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) |
6d886fd0
AP		 2281 0 /* Reserved*/ | F(AES) | F(XSAVE) | 0 /* OSXSAVE */ | F(AVX) |
2282 F(F16C);
7faa4ee1 2283 /* cpuid 0x80000001.ecx */
07716717 2284 const u32 kvm_supported_word6_x86_features =
4c62a2dc 2285 F(LAHF_LM) | F(CMP_LEGACY) | 0 /*SVM*/ | 0 /* ExtApicSpace */ |
7faa4ee1 2286 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) |
7ef8aa72 2287 F(3DNOWPREFETCH) | 0 /* OSVW */ | 0 /* IBS */ | F(XOP) |
6d886fd0 2288 0 /* SKINIT, WDT, LWP */ | F(FMA4) | F(TBM);
07716717 2289
19355475 2290 /* all calls to cpuid_count() should be made on the same cpu */
07716717
DK		 2291 get_cpu();
2292 do_cpuid_1_ent(entry, function, index);
2293 ++*nent;
2294
2295 switch (function) {
2296 case 0:
2acf923e 2297 entry->eax = min(entry->eax, (u32)0xd);
07716717
DK		 2298 break;
2299 case 1:
2300 entry->edx &= kvm_supported_word0_x86_features;
7faa4ee1 2301 entry->ecx &= kvm_supported_word4_x86_features;
0d1de2d9
GN		 2302 /* we support x2apic emulation even if host does not support
2303 * it since we emulate x2apic in software */
2304 entry->ecx |= F(X2APIC);
07716717
DK		 2305 break;
2306 /* function 2 entries are STATEFUL. That is, repeated cpuid commands
2307 * may return different values. This forces us to get_cpu() before
2308 * issuing the first command, and also to emulate this annoying behavior
2309 * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */
2310 case 2: {
2311 int t, times = entry->eax & 0xff;
2312
2313 entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
0fdf8e59 2314 entry->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
07716717
DK		 2315 for (t = 1; t < times && *nent < maxnent; ++t) {
2316 do_cpuid_1_ent(&entry[t], function, 0);
2317 entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
2318 ++*nent;
2319 }
2320 break;
2321 }
2322 /* function 4 and 0xb have additional index. */
2323 case 4: {
14af3f3c 2324 int i, cache_type;
07716717
DK		 2325
2326 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2327 /* read more entries until cache_type is zero */
14af3f3c
HH		 2328 for (i = 1; *nent < maxnent; ++i) {
2329 cache_type = entry[i - 1].eax & 0x1f;
07716717
DK		 2330 if (!cache_type)
2331 break;
14af3f3c
HH		 2332 do_cpuid_1_ent(&entry[i], function, i);
2333 entry[i].flags |=
07716717
DK		 2334 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2335 ++*nent;
2336 }
2337 break;
2338 }
2339 case 0xb: {
14af3f3c 2340 int i, level_type;
07716717
DK		 2341
2342 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2343 /* read more entries until level_type is zero */
14af3f3c 2344 for (i = 1; *nent < maxnent; ++i) {
0853d2c1 2345 level_type = entry[i - 1].ecx & 0xff00;
07716717
DK		 2346 if (!level_type)
2347 break;
14af3f3c
HH		 2348 do_cpuid_1_ent(&entry[i], function, i);
2349 entry[i].flags |=
07716717
DK		 2350 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2351 ++*nent;
2352 }
2353 break;
2354 }
2acf923e
DC		 2355 case 0xd: {
2356 int i;
2357
2358 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2359 for (i = 1; *nent < maxnent; ++i) {
2360 if (entry[i - 1].eax == 0 && i != 2)
2361 break;
2362 do_cpuid_1_ent(&entry[i], function, i);
2363 entry[i].flags |=
2364 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2365 ++*nent;
2366 }
2367 break;
2368 }
84478c82
GC		 2369 case KVM_CPUID_SIGNATURE: {
2370 char signature[12] = "KVMKVMKVM\0\0";
2371 u32 *sigptr = (u32 *)signature;
2372 entry->eax = 0;
2373 entry->ebx = sigptr[0];
2374 entry->ecx = sigptr[1];
2375 entry->edx = sigptr[2];
2376 break;
2377 }
2378 case KVM_CPUID_FEATURES:
2379 entry->eax = (1 << KVM_FEATURE_CLOCKSOURCE) |
2380 (1 << KVM_FEATURE_NOP_IO_DELAY) |
371bcf64
GC		 2381 (1 << KVM_FEATURE_CLOCKSOURCE2) |
2382 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT);
84478c82
GC		 2383 entry->ebx = 0;
2384 entry->ecx = 0;
2385 entry->edx = 0;
2386 break;
07716717
DK		 2387 case 0x80000000:
2388 entry->eax = min(entry->eax, 0x8000001a);
2389 break;
2390 case 0x80000001:
2391 entry->edx &= kvm_supported_word1_x86_features;
2392 entry->ecx &= kvm_supported_word6_x86_features;
2393 break;
2394 }
d4330ef2
JR		 2395
2396 kvm_x86_ops->set_supported_cpuid(function, entry);
2397
07716717
DK		 2398 put_cpu();
2399}
2400
7faa4ee1
AK		 2401#undef F
2402
674eea0f 2403static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
19355475 2404 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 2405{
2406 struct kvm_cpuid_entry2 *cpuid_entries;
2407 int limit, nent = 0, r = -E2BIG;
2408 u32 func;
2409
2410 if (cpuid->nent < 1)
2411 goto out;
6a544355
AK		 2412 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2413 cpuid->nent = KVM_MAX_CPUID_ENTRIES;
07716717
DK		 2414 r = -ENOMEM;
2415 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent);
2416 if (!cpuid_entries)
2417 goto out;
2418
2419 do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent);
2420 limit = cpuid_entries[0].eax;
2421 for (func = 1; func <= limit && nent < cpuid->nent; ++func)
2422 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 2423 &nent, cpuid->nent);
07716717
DK		 2424 r = -E2BIG;
2425 if (nent >= cpuid->nent)
2426 goto out_free;
2427
2428 do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent);
2429 limit = cpuid_entries[nent - 1].eax;
2430 for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func)
2431 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 2432 &nent, cpuid->nent);
84478c82
GC		 2433
2434
2435
2436 r = -E2BIG;
2437 if (nent >= cpuid->nent)
2438 goto out_free;
2439
2440 do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_SIGNATURE, 0, &nent,
2441 cpuid->nent);
2442
2443 r = -E2BIG;
2444 if (nent >= cpuid->nent)
2445 goto out_free;
2446
2447 do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_FEATURES, 0, &nent,
2448 cpuid->nent);
2449
cb007648
MM		 2450 r = -E2BIG;
2451 if (nent >= cpuid->nent)
2452 goto out_free;
2453
07716717
DK		 2454 r = -EFAULT;
2455 if (copy_to_user(entries, cpuid_entries,
19355475 2456 nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 2457 goto out_free;
2458 cpuid->nent = nent;
2459 r = 0;
2460
2461out_free:
2462 vfree(cpuid_entries);
2463out:
2464 return r;
2465}
2466
313a3dc7
CO		 2467static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2468 struct kvm_lapic_state *s)
2469{
ad312c7c 2470 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2471
2472 return 0;
2473}
2474
2475static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2476 struct kvm_lapic_state *s)
2477{
ad312c7c 2478 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
313a3dc7 2479 kvm_apic_post_state_restore(vcpu);
cb142eb7 2480 update_cr8_intercept(vcpu);
313a3dc7
CO		 2481
2482 return 0;
2483}
2484
f77bc6a4
ZX		 2485static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2486 struct kvm_interrupt *irq)
2487{
2488 if (irq->irq < 0 || irq->irq >= 256)
2489 return -EINVAL;
2490 if (irqchip_in_kernel(vcpu->kvm))
2491 return -ENXIO;
f77bc6a4 2492
66fd3f7f 2493 kvm_queue_interrupt(vcpu, irq->irq, false);
3842d135 2494 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4 2495
f77bc6a4
ZX		 2496 return 0;
2497}
2498
c4abb7c9
JK		 2499static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2500{
c4abb7c9 2501 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2502
2503 return 0;
2504}
2505
b209749f
AK		 2506static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2507 struct kvm_tpr_access_ctl *tac)
2508{
2509 if (tac->flags)
2510 return -EINVAL;
2511 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2512 return 0;
2513}
2514
890ca9ae
HY		 2515static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2516 u64 mcg_cap)
2517{
2518 int r;
2519 unsigned bank_num = mcg_cap & 0xff, bank;
2520
2521 r = -EINVAL;
a9e38c3e 2522 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2523 goto out;
2524 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2525 goto out;
2526 r = 0;
2527 vcpu->arch.mcg_cap = mcg_cap;
2528 /* Init IA32_MCG_CTL to all 1s */
2529 if (mcg_cap & MCG_CTL_P)
2530 vcpu->arch.mcg_ctl = ~(u64)0;
2531 /* Init IA32_MCi_CTL to all 1s */
2532 for (bank = 0; bank < bank_num; bank++)
2533 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2534out:
2535 return r;
2536}
2537
2538static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2539 struct kvm_x86_mce *mce)
2540{
2541 u64 mcg_cap = vcpu->arch.mcg_cap;
2542 unsigned bank_num = mcg_cap & 0xff;
2543 u64 *banks = vcpu->arch.mce_banks;
2544
2545 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2546 return -EINVAL;
2547 /*
2548 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2549 * reporting is disabled
2550 */
2551 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2552 vcpu->arch.mcg_ctl != ~(u64)0)
2553 return 0;
2554 banks += 4 * mce->bank;
2555 /*
2556 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2557 * reporting is disabled for the bank
2558 */
2559 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2560 return 0;
2561 if (mce->status & MCI_STATUS_UC) {
2562 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2563 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
890ca9ae
HY		 2564 printk(KERN_DEBUG "kvm: set_mce: "
2565 "injects mce exception while "
2566 "previous one is in progress!\n");
a8eeb04a 2567 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2568 return 0;
2569 }
2570 if (banks[1] & MCI_STATUS_VAL)
2571 mce->status |= MCI_STATUS_OVER;
2572 banks[2] = mce->addr;
2573 banks[3] = mce->misc;
2574 vcpu->arch.mcg_status = mce->mcg_status;
2575 banks[1] = mce->status;
2576 kvm_queue_exception(vcpu, MC_VECTOR);
2577 } else if (!(banks[1] & MCI_STATUS_VAL)
2578 || !(banks[1] & MCI_STATUS_UC)) {
2579 if (banks[1] & MCI_STATUS_VAL)
2580 mce->status |= MCI_STATUS_OVER;
2581 banks[2] = mce->addr;
2582 banks[3] = mce->misc;
2583 banks[1] = mce->status;
2584 } else
2585 banks[1] |= MCI_STATUS_OVER;
2586 return 0;
2587}
2588
3cfc3092
JK		 2589static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2590 struct kvm_vcpu_events *events)
2591{
03b82a30
JK		 2592 events->exception.injected =
2593 vcpu->arch.exception.pending &&
2594 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2595 events->exception.nr = vcpu->arch.exception.nr;
2596 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 2597 events->exception.pad = 0;
3cfc3092
JK		 2598 events->exception.error_code = vcpu->arch.exception.error_code;
2599
03b82a30
JK		 2600 events->interrupt.injected =
2601 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2602 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2603 events->interrupt.soft = 0;
48005f64
JK		 2604 events->interrupt.shadow =
2605 kvm_x86_ops->get_interrupt_shadow(vcpu,
2606 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
3cfc3092
JK		 2607
2608 events->nmi.injected = vcpu->arch.nmi_injected;
2609 events->nmi.pending = vcpu->arch.nmi_pending;
2610 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 2611 events->nmi.pad = 0;
3cfc3092
JK		 2612
2613 events->sipi_vector = vcpu->arch.sipi_vector;
2614
dab4b911 2615 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2616 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2617 | KVM_VCPUEVENT_VALID_SHADOW);
97e69aa6 2618 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 2619}
2620
2621static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2622 struct kvm_vcpu_events *events)
2623{
dab4b911 2624 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2625 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2626 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 2627 return -EINVAL;
2628
3cfc3092
JK		 2629 vcpu->arch.exception.pending = events->exception.injected;
2630 vcpu->arch.exception.nr = events->exception.nr;
2631 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2632 vcpu->arch.exception.error_code = events->exception.error_code;
2633
2634 vcpu->arch.interrupt.pending = events->interrupt.injected;
2635 vcpu->arch.interrupt.nr = events->interrupt.nr;
2636 vcpu->arch.interrupt.soft = events->interrupt.soft;
2637 if (vcpu->arch.interrupt.pending && irqchip_in_kernel(vcpu->kvm))
2638 kvm_pic_clear_isr_ack(vcpu->kvm);
48005f64
JK		 2639 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2640 kvm_x86_ops->set_interrupt_shadow(vcpu,
2641 events->interrupt.shadow);
3cfc3092
JK		 2642
2643 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2644 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2645 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2646 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2647
dab4b911
JK		 2648 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR)
2649 vcpu->arch.sipi_vector = events->sipi_vector;
3cfc3092 2650
3842d135
AK		 2651 kvm_make_request(KVM_REQ_EVENT, vcpu);
2652
3cfc3092
JK		 2653 return 0;
2654}
2655
a1efbe77
JK		 2656static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2657 struct kvm_debugregs *dbgregs)
2658{
a1efbe77
JK		 2659 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2660 dbgregs->dr6 = vcpu->arch.dr6;
2661 dbgregs->dr7 = vcpu->arch.dr7;
2662 dbgregs->flags = 0;
97e69aa6 2663 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 2664}
2665
2666static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2667 struct kvm_debugregs *dbgregs)
2668{
2669 if (dbgregs->flags)
2670 return -EINVAL;
2671
a1efbe77
JK		 2672 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2673 vcpu->arch.dr6 = dbgregs->dr6;
2674 vcpu->arch.dr7 = dbgregs->dr7;
2675
a1efbe77
JK		 2676 return 0;
2677}
2678
2d5b5a66
SY		 2679static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
2680 struct kvm_xsave *guest_xsave)
2681{
2682 if (cpu_has_xsave)
2683 memcpy(guest_xsave->region,
2684 &vcpu->arch.guest_fpu.state->xsave,
f45755b8 2685 xstate_size);
2d5b5a66
SY		 2686 else {
2687 memcpy(guest_xsave->region,
2688 &vcpu->arch.guest_fpu.state->fxsave,
2689 sizeof(struct i387_fxsave_struct));
2690 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
2691 XSTATE_FPSSE;
2692 }
2693}
2694
2695static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
2696 struct kvm_xsave *guest_xsave)
2697{
2698 u64 xstate_bv =
2699 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
2700
2701 if (cpu_has_xsave)
2702 memcpy(&vcpu->arch.guest_fpu.state->xsave,
f45755b8 2703 guest_xsave->region, xstate_size);
2d5b5a66
SY		 2704 else {
2705 if (xstate_bv & ~XSTATE_FPSSE)
2706 return -EINVAL;
2707 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
2708 guest_xsave->region, sizeof(struct i387_fxsave_struct));
2709 }
2710 return 0;
2711}
2712
2713static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
2714 struct kvm_xcrs *guest_xcrs)
2715{
2716 if (!cpu_has_xsave) {
2717 guest_xcrs->nr_xcrs = 0;
2718 return;
2719 }
2720
2721 guest_xcrs->nr_xcrs = 1;
2722 guest_xcrs->flags = 0;
2723 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
2724 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
2725}
2726
2727static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
2728 struct kvm_xcrs *guest_xcrs)
2729{
2730 int i, r = 0;
2731
2732 if (!cpu_has_xsave)
2733 return -EINVAL;
2734
2735 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
2736 return -EINVAL;
2737
2738 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
2739 /* Only support XCR0 currently */
2740 if (guest_xcrs->xcrs[0].xcr == XCR_XFEATURE_ENABLED_MASK) {
2741 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
2742 guest_xcrs->xcrs[0].value);
2743 break;
2744 }
2745 if (r)
2746 r = -EINVAL;
2747 return r;
2748}
2749
313a3dc7
CO		 2750long kvm_arch_vcpu_ioctl(struct file *filp,
2751 unsigned int ioctl, unsigned long arg)
2752{
2753 struct kvm_vcpu *vcpu = filp->private_data;
2754 void __user *argp = (void __user *)arg;
2755 int r;
d1ac91d8
AK		 2756 union {
2757 struct kvm_lapic_state *lapic;
2758 struct kvm_xsave *xsave;
2759 struct kvm_xcrs *xcrs;
2760 void *buffer;
2761 } u;
2762
2763 u.buffer = NULL;
313a3dc7
CO		 2764 switch (ioctl) {
2765 case KVM_GET_LAPIC: {
2204ae3c
MT		 2766 r = -EINVAL;
2767 if (!vcpu->arch.apic)
2768 goto out;
d1ac91d8 2769 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 2770
b772ff36 2771 r = -ENOMEM;
d1ac91d8 2772 if (!u.lapic)
b772ff36 2773 goto out;
d1ac91d8 2774 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 2775 if (r)
2776 goto out;
2777 r = -EFAULT;
d1ac91d8 2778 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 2779 goto out;
2780 r = 0;
2781 break;
2782 }
2783 case KVM_SET_LAPIC: {
2204ae3c
MT		 2784 r = -EINVAL;
2785 if (!vcpu->arch.apic)
2786 goto out;
d1ac91d8 2787 u.lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
b772ff36 2788 r = -ENOMEM;
d1ac91d8 2789 if (!u.lapic)
b772ff36 2790 goto out;
313a3dc7 2791 r = -EFAULT;
d1ac91d8 2792 if (copy_from_user(u.lapic, argp, sizeof(struct kvm_lapic_state)))
313a3dc7 2793 goto out;
d1ac91d8 2794 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 2795 if (r)
2796 goto out;
2797 r = 0;
2798 break;
2799 }
f77bc6a4
ZX		 2800 case KVM_INTERRUPT: {
2801 struct kvm_interrupt irq;
2802
2803 r = -EFAULT;
2804 if (copy_from_user(&irq, argp, sizeof irq))
2805 goto out;
2806 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
2807 if (r)
2808 goto out;
2809 r = 0;
2810 break;
2811 }
c4abb7c9
JK		 2812 case KVM_NMI: {
2813 r = kvm_vcpu_ioctl_nmi(vcpu);
2814 if (r)
2815 goto out;
2816 r = 0;
2817 break;
2818 }
313a3dc7
CO		 2819 case KVM_SET_CPUID: {
2820 struct kvm_cpuid __user *cpuid_arg = argp;
2821 struct kvm_cpuid cpuid;
2822
2823 r = -EFAULT;
2824 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2825 goto out;
2826 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
2827 if (r)
2828 goto out;
2829 break;
2830 }
07716717
DK		 2831 case KVM_SET_CPUID2: {
2832 struct kvm_cpuid2 __user *cpuid_arg = argp;
2833 struct kvm_cpuid2 cpuid;
2834
2835 r = -EFAULT;
2836 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2837 goto out;
2838 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 2839 cpuid_arg->entries);
07716717
DK		 2840 if (r)
2841 goto out;
2842 break;
2843 }
2844 case KVM_GET_CPUID2: {
2845 struct kvm_cpuid2 __user *cpuid_arg = argp;
2846 struct kvm_cpuid2 cpuid;
2847
2848 r = -EFAULT;
2849 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2850 goto out;
2851 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 2852 cpuid_arg->entries);
07716717
DK		 2853 if (r)
2854 goto out;
2855 r = -EFAULT;
2856 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2857 goto out;
2858 r = 0;
2859 break;
2860 }
313a3dc7
CO		 2861 case KVM_GET_MSRS:
2862 r = msr_io(vcpu, argp, kvm_get_msr, 1);
2863 break;
2864 case KVM_SET_MSRS:
2865 r = msr_io(vcpu, argp, do_set_msr, 0);
2866 break;
b209749f
AK		 2867 case KVM_TPR_ACCESS_REPORTING: {
2868 struct kvm_tpr_access_ctl tac;
2869
2870 r = -EFAULT;
2871 if (copy_from_user(&tac, argp, sizeof tac))
2872 goto out;
2873 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
2874 if (r)
2875 goto out;
2876 r = -EFAULT;
2877 if (copy_to_user(argp, &tac, sizeof tac))
2878 goto out;
2879 r = 0;
2880 break;
2881 };
b93463aa
AK		 2882 case KVM_SET_VAPIC_ADDR: {
2883 struct kvm_vapic_addr va;
2884
2885 r = -EINVAL;
2886 if (!irqchip_in_kernel(vcpu->kvm))
2887 goto out;
2888 r = -EFAULT;
2889 if (copy_from_user(&va, argp, sizeof va))
2890 goto out;
2891 r = 0;
2892 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
2893 break;
2894 }
890ca9ae
HY		 2895 case KVM_X86_SETUP_MCE: {
2896 u64 mcg_cap;
2897
2898 r = -EFAULT;
2899 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
2900 goto out;
2901 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
2902 break;
2903 }
2904 case KVM_X86_SET_MCE: {
2905 struct kvm_x86_mce mce;
2906
2907 r = -EFAULT;
2908 if (copy_from_user(&mce, argp, sizeof mce))
2909 goto out;
2910 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
2911 break;
2912 }
3cfc3092
JK		 2913 case KVM_GET_VCPU_EVENTS: {
2914 struct kvm_vcpu_events events;
2915
2916 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
2917
2918 r = -EFAULT;
2919 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
2920 break;
2921 r = 0;
2922 break;
2923 }
2924 case KVM_SET_VCPU_EVENTS: {
2925 struct kvm_vcpu_events events;
2926
2927 r = -EFAULT;
2928 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
2929 break;
2930
2931 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
2932 break;
2933 }
a1efbe77
JK		 2934 case KVM_GET_DEBUGREGS: {
2935 struct kvm_debugregs dbgregs;
2936
2937 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
2938
2939 r = -EFAULT;
2940 if (copy_to_user(argp, &dbgregs,
2941 sizeof(struct kvm_debugregs)))
2942 break;
2943 r = 0;
2944 break;
2945 }
2946 case KVM_SET_DEBUGREGS: {
2947 struct kvm_debugregs dbgregs;
2948
2949 r = -EFAULT;
2950 if (copy_from_user(&dbgregs, argp,
2951 sizeof(struct kvm_debugregs)))
2952 break;
2953
2954 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
2955 break;
2956 }
2d5b5a66 2957 case KVM_GET_XSAVE: {
d1ac91d8 2958 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 2959 r = -ENOMEM;
d1ac91d8 2960 if (!u.xsave)
2d5b5a66
SY		 2961 break;
2962
d1ac91d8 2963 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 2964
2965 r = -EFAULT;
d1ac91d8 2966 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 2967 break;
2968 r = 0;
2969 break;
2970 }
2971 case KVM_SET_XSAVE: {
d1ac91d8 2972 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 2973 r = -ENOMEM;
d1ac91d8 2974 if (!u.xsave)
2d5b5a66
SY		 2975 break;
2976
2977 r = -EFAULT;
d1ac91d8 2978 if (copy_from_user(u.xsave, argp, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 2979 break;
2980
d1ac91d8 2981 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 2982 break;
2983 }
2984 case KVM_GET_XCRS: {
d1ac91d8 2985 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 2986 r = -ENOMEM;
d1ac91d8 2987 if (!u.xcrs)
2d5b5a66
SY		 2988 break;
2989
d1ac91d8 2990 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 2991
2992 r = -EFAULT;
d1ac91d8 2993 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 2994 sizeof(struct kvm_xcrs)))
2995 break;
2996 r = 0;
2997 break;
2998 }
2999 case KVM_SET_XCRS: {
d1ac91d8 3000 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3001 r = -ENOMEM;
d1ac91d8 3002 if (!u.xcrs)
2d5b5a66
SY		 3003 break;
3004
3005 r = -EFAULT;
d1ac91d8 3006 if (copy_from_user(u.xcrs, argp,
2d5b5a66
SY		 3007 sizeof(struct kvm_xcrs)))
3008 break;
3009
d1ac91d8 3010 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3011 break;
3012 }
313a3dc7
CO		 3013 default:
3014 r = -EINVAL;
3015 }
3016out:
d1ac91d8 3017 kfree(u.buffer);
313a3dc7
CO		 3018 return r;
3019}
3020
1fe779f8
CO		 3021static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3022{
3023 int ret;
3024
3025 if (addr > (unsigned int)(-3 * PAGE_SIZE))
3026 return -1;
3027 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3028 return ret;
3029}
3030
b927a3ce
SY		 3031static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3032 u64 ident_addr)
3033{
3034 kvm->arch.ept_identity_map_addr = ident_addr;
3035 return 0;
3036}
3037
1fe779f8
CO		 3038static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3039 u32 kvm_nr_mmu_pages)
3040{
3041 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3042 return -EINVAL;
3043
79fac95e 3044 mutex_lock(&kvm->slots_lock);
7c8a83b7 3045 spin_lock(&kvm->mmu_lock);
1fe779f8
CO		 3046
3047 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3048 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3049
7c8a83b7 3050 spin_unlock(&kvm->mmu_lock);
79fac95e 3051 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3052 return 0;
3053}
3054
3055static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3056{
39de71ec 3057 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3058}
3059
1fe779f8
CO		 3060static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3061{
3062 int r;
3063
3064 r = 0;
3065 switch (chip->chip_id) {
3066 case KVM_IRQCHIP_PIC_MASTER:
3067 memcpy(&chip->chip.pic,
3068 &pic_irqchip(kvm)->pics[0],
3069 sizeof(struct kvm_pic_state));
3070 break;
3071 case KVM_IRQCHIP_PIC_SLAVE:
3072 memcpy(&chip->chip.pic,
3073 &pic_irqchip(kvm)->pics[1],
3074 sizeof(struct kvm_pic_state));
3075 break;
3076 case KVM_IRQCHIP_IOAPIC:
eba0226b 3077 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3078 break;
3079 default:
3080 r = -EINVAL;
3081 break;
3082 }
3083 return r;
3084}
3085
3086static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3087{
3088 int r;
3089
3090 r = 0;
3091 switch (chip->chip_id) {
3092 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3093 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3094 memcpy(&pic_irqchip(kvm)->pics[0],
3095 &chip->chip.pic,
3096 sizeof(struct kvm_pic_state));
f4f51050 3097 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3098 break;
3099 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3100 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3101 memcpy(&pic_irqchip(kvm)->pics[1],
3102 &chip->chip.pic,
3103 sizeof(struct kvm_pic_state));
f4f51050 3104 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3105 break;
3106 case KVM_IRQCHIP_IOAPIC:
eba0226b 3107 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3108 break;
3109 default:
3110 r = -EINVAL;
3111 break;
3112 }
3113 kvm_pic_update_irq(pic_irqchip(kvm));
3114 return r;
3115}
3116
e0f63cb9
SY		 3117static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3118{
3119 int r = 0;
3120
894a9c55 3121 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3122 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 3123 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3124 return r;
3125}
3126
3127static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3128{
3129 int r = 0;
3130
894a9c55 3131 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3132 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 3133 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3134 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3135 return r;
3136}
3137
3138static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3139{
3140 int r = 0;
3141
3142 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3143 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3144 sizeof(ps->channels));
3145 ps->flags = kvm->arch.vpit->pit_state.flags;
3146 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3147 memset(&ps->reserved, 0, sizeof(ps->reserved));
e9f42757
BK		 3148 return r;
3149}
3150
3151static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3152{
3153 int r = 0, start = 0;
3154 u32 prev_legacy, cur_legacy;
3155 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3156 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3157 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3158 if (!prev_legacy && cur_legacy)
3159 start = 1;
3160 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3161 sizeof(kvm->arch.vpit->pit_state.channels));
3162 kvm->arch.vpit->pit_state.flags = ps->flags;
3163 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 3164 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3165 return r;
3166}
3167
52d939a0
MT		 3168static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3169 struct kvm_reinject_control *control)
3170{
3171 if (!kvm->arch.vpit)
3172 return -ENXIO;
894a9c55 3173 mutex_lock(&kvm->arch.vpit->pit_state.lock);
52d939a0 3174 kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject;
894a9c55 3175 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3176 return 0;
3177}
3178
5bb064dc
ZX		 3179/*
3180 * Get (and clear) the dirty memory log for a memory slot.
3181 */
3182int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
3183 struct kvm_dirty_log *log)
3184{
87bf6e7d 3185 int r, i;
5bb064dc 3186 struct kvm_memory_slot *memslot;
87bf6e7d 3187 unsigned long n;
b050b015 3188 unsigned long is_dirty = 0;
5bb064dc 3189
79fac95e 3190 mutex_lock(&kvm->slots_lock);
5bb064dc 3191
b050b015
MT		 3192 r = -EINVAL;
3193 if (log->slot >= KVM_MEMORY_SLOTS)
3194 goto out;
3195
3196 memslot = &kvm->memslots->memslots[log->slot];
3197 r = -ENOENT;
3198 if (!memslot->dirty_bitmap)
3199 goto out;
3200
87bf6e7d 3201 n = kvm_dirty_bitmap_bytes(memslot);
b050b015 3202
b050b015
MT		 3203 for (i = 0; !is_dirty && i < n/sizeof(long); i++)
3204 is_dirty = memslot->dirty_bitmap[i];
5bb064dc
ZX		 3205
3206 /* If nothing is dirty, don't bother messing with page tables. */
3207 if (is_dirty) {
b050b015 3208 struct kvm_memslots *slots, *old_slots;
914ebccd 3209 unsigned long *dirty_bitmap;
b050b015 3210
914ebccd
TY		 3211 r = -ENOMEM;
3212 dirty_bitmap = vmalloc(n);
3213 if (!dirty_bitmap)
3214 goto out;
3215 memset(dirty_bitmap, 0, n);
b050b015 3216
914ebccd
TY		 3217 r = -ENOMEM;
3218 slots = kzalloc(sizeof(struct kvm_memslots), GFP_KERNEL);
3219 if (!slots) {
3220 vfree(dirty_bitmap);
3221 goto out;
3222 }
b050b015
MT		 3223 memcpy(slots, kvm->memslots, sizeof(struct kvm_memslots));
3224 slots->memslots[log->slot].dirty_bitmap = dirty_bitmap;
49c7754c 3225 slots->generation++;
b050b015
MT		 3226
3227 old_slots = kvm->memslots;
3228 rcu_assign_pointer(kvm->memslots, slots);
3229 synchronize_srcu_expedited(&kvm->srcu);
3230 dirty_bitmap = old_slots->memslots[log->slot].dirty_bitmap;
3231 kfree(old_slots);
914ebccd 3232
edde99ce
MT		 3233 spin_lock(&kvm->mmu_lock);
3234 kvm_mmu_slot_remove_write_access(kvm, log->slot);
3235 spin_unlock(&kvm->mmu_lock);
3236
914ebccd
TY		 3237 r = -EFAULT;
3238 if (copy_to_user(log->dirty_bitmap, dirty_bitmap, n)) {
3239 vfree(dirty_bitmap);
3240 goto out;
3241 }
3242 vfree(dirty_bitmap);
3243 } else {
3244 r = -EFAULT;
3245 if (clear_user(log->dirty_bitmap, n))
3246 goto out;
5bb064dc 3247 }
b050b015 3248
5bb064dc
ZX		 3249 r = 0;
3250out:
79fac95e 3251 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3252 return r;
3253}
3254
1fe779f8
CO		 3255long kvm_arch_vm_ioctl(struct file *filp,
3256 unsigned int ioctl, unsigned long arg)
3257{
3258 struct kvm *kvm = filp->private_data;
3259 void __user *argp = (void __user *)arg;
367e1319 3260 int r = -ENOTTY;
f0d66275
DH		 3261 /*
3262 * This union makes it completely explicit to gcc-3.x
3263 * that these two variables' stack usage should be
3264 * combined, not added together.
3265 */
3266 union {
3267 struct kvm_pit_state ps;
e9f42757 3268 struct kvm_pit_state2 ps2;
c5ff41ce 3269 struct kvm_pit_config pit_config;
f0d66275 3270 } u;
1fe779f8
CO		 3271
3272 switch (ioctl) {
3273 case KVM_SET_TSS_ADDR:
3274 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
3275 if (r < 0)
3276 goto out;
3277 break;
b927a3ce
SY		 3278 case KVM_SET_IDENTITY_MAP_ADDR: {
3279 u64 ident_addr;
3280
3281 r = -EFAULT;
3282 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3283 goto out;
3284 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
3285 if (r < 0)
3286 goto out;
3287 break;
3288 }
1fe779f8
CO		 3289 case KVM_SET_NR_MMU_PAGES:
3290 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
3291 if (r)
3292 goto out;
3293 break;
3294 case KVM_GET_NR_MMU_PAGES:
3295 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3296 break;
3ddea128
MT		 3297 case KVM_CREATE_IRQCHIP: {
3298 struct kvm_pic *vpic;
3299
3300 mutex_lock(&kvm->lock);
3301 r = -EEXIST;
3302 if (kvm->arch.vpic)
3303 goto create_irqchip_unlock;
1fe779f8 3304 r = -ENOMEM;
3ddea128
MT		 3305 vpic = kvm_create_pic(kvm);
3306 if (vpic) {
1fe779f8
CO		 3307 r = kvm_ioapic_init(kvm);
3308 if (r) {
72bb2fcd
WY		 3309 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3310 &vpic->dev);
3ddea128
MT		 3311 kfree(vpic);
3312 goto create_irqchip_unlock;
1fe779f8
CO		 3313 }
3314 } else
3ddea128
MT		 3315 goto create_irqchip_unlock;
3316 smp_wmb();
3317 kvm->arch.vpic = vpic;
3318 smp_wmb();
399ec807
AK		 3319 r = kvm_setup_default_irq_routing(kvm);
3320 if (r) {
3ddea128 3321 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 3322 kvm_ioapic_destroy(kvm);
3323 kvm_destroy_pic(kvm);
3ddea128 3324 mutex_unlock(&kvm->irq_lock);
399ec807 3325 }
3ddea128
MT		 3326 create_irqchip_unlock:
3327 mutex_unlock(&kvm->lock);
1fe779f8 3328 break;
3ddea128 3329 }
7837699f 3330 case KVM_CREATE_PIT:
c5ff41ce
JK		 3331 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3332 goto create_pit;
3333 case KVM_CREATE_PIT2:
3334 r = -EFAULT;
3335 if (copy_from_user(&u.pit_config, argp,
3336 sizeof(struct kvm_pit_config)))
3337 goto out;
3338 create_pit:
79fac95e 3339 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3340 r = -EEXIST;
3341 if (kvm->arch.vpit)
3342 goto create_pit_unlock;
7837699f 3343 r = -ENOMEM;
c5ff41ce 3344 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3345 if (kvm->arch.vpit)
3346 r = 0;
269e05e4 3347 create_pit_unlock:
79fac95e 3348 mutex_unlock(&kvm->slots_lock);
7837699f 3349 break;
4925663a 3350 case KVM_IRQ_LINE_STATUS:
1fe779f8
CO		 3351 case KVM_IRQ_LINE: {
3352 struct kvm_irq_level irq_event;
3353
3354 r = -EFAULT;
3355 if (copy_from_user(&irq_event, argp, sizeof irq_event))
3356 goto out;
160d2f6c 3357 r = -ENXIO;
1fe779f8 3358 if (irqchip_in_kernel(kvm)) {
4925663a 3359 __s32 status;
4925663a
GN		 3360 status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3361 irq_event.irq, irq_event.level);
4925663a 3362 if (ioctl == KVM_IRQ_LINE_STATUS) {
160d2f6c 3363 r = -EFAULT;
4925663a
GN		 3364 irq_event.status = status;
3365 if (copy_to_user(argp, &irq_event,
3366 sizeof irq_event))
3367 goto out;
3368 }
1fe779f8
CO		 3369 r = 0;
3370 }
3371 break;
3372 }
3373 case KVM_GET_IRQCHIP: {
3374 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 3375 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 3376
f0d66275
DH		 3377 r = -ENOMEM;
3378 if (!chip)
1fe779f8 3379 goto out;
f0d66275
DH		 3380 r = -EFAULT;
3381 if (copy_from_user(chip, argp, sizeof *chip))
3382 goto get_irqchip_out;
1fe779f8
CO		 3383 r = -ENXIO;
3384 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3385 goto get_irqchip_out;
3386 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3387 if (r)
f0d66275 3388 goto get_irqchip_out;
1fe779f8 3389 r = -EFAULT;
f0d66275
DH		 3390 if (copy_to_user(argp, chip, sizeof *chip))
3391 goto get_irqchip_out;
1fe779f8 3392 r = 0;
f0d66275
DH		 3393 get_irqchip_out:
3394 kfree(chip);
3395 if (r)
3396 goto out;
1fe779f8
CO		 3397 break;
3398 }
3399 case KVM_SET_IRQCHIP: {
3400 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 3401 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 3402
f0d66275
DH		 3403 r = -ENOMEM;
3404 if (!chip)
1fe779f8 3405 goto out;
f0d66275
DH		 3406 r = -EFAULT;
3407 if (copy_from_user(chip, argp, sizeof *chip))
3408 goto set_irqchip_out;
1fe779f8
CO		 3409 r = -ENXIO;
3410 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3411 goto set_irqchip_out;
3412 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3413 if (r)
f0d66275 3414 goto set_irqchip_out;
1fe779f8 3415 r = 0;
f0d66275
DH		 3416 set_irqchip_out:
3417 kfree(chip);
3418 if (r)
3419 goto out;
1fe779f8
CO		 3420 break;
3421 }
e0f63cb9 3422 case KVM_GET_PIT: {
e0f63cb9 3423 r = -EFAULT;
f0d66275 3424 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3425 goto out;
3426 r = -ENXIO;
3427 if (!kvm->arch.vpit)
3428 goto out;
f0d66275 3429 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3430 if (r)
3431 goto out;
3432 r = -EFAULT;
f0d66275 3433 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3434 goto out;
3435 r = 0;
3436 break;
3437 }
3438 case KVM_SET_PIT: {
e0f63cb9 3439 r = -EFAULT;
f0d66275 3440 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3441 goto out;
3442 r = -ENXIO;
3443 if (!kvm->arch.vpit)
3444 goto out;
f0d66275 3445 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3446 if (r)
3447 goto out;
3448 r = 0;
3449 break;
3450 }
e9f42757
BK		 3451 case KVM_GET_PIT2: {
3452 r = -ENXIO;
3453 if (!kvm->arch.vpit)
3454 goto out;
3455 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3456 if (r)
3457 goto out;
3458 r = -EFAULT;
3459 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3460 goto out;
3461 r = 0;
3462 break;
3463 }
3464 case KVM_SET_PIT2: {
3465 r = -EFAULT;
3466 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3467 goto out;
3468 r = -ENXIO;
3469 if (!kvm->arch.vpit)
3470 goto out;
3471 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
3472 if (r)
3473 goto out;
3474 r = 0;
3475 break;
3476 }
52d939a0
MT		 3477 case KVM_REINJECT_CONTROL: {
3478 struct kvm_reinject_control control;
3479 r = -EFAULT;
3480 if (copy_from_user(&control, argp, sizeof(control)))
3481 goto out;
3482 r = kvm_vm_ioctl_reinject(kvm, &control);
3483 if (r)
3484 goto out;
3485 r = 0;
3486 break;
3487 }
ffde22ac
ES		 3488 case KVM_XEN_HVM_CONFIG: {
3489 r = -EFAULT;
3490 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3491 sizeof(struct kvm_xen_hvm_config)))
3492 goto out;
3493 r = -EINVAL;
3494 if (kvm->arch.xen_hvm_config.flags)
3495 goto out;
3496 r = 0;
3497 break;
3498 }
afbcf7ab 3499 case KVM_SET_CLOCK: {
afbcf7ab
GC		 3500 struct kvm_clock_data user_ns;
3501 u64 now_ns;
3502 s64 delta;
3503
3504 r = -EFAULT;
3505 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3506 goto out;
3507
3508 r = -EINVAL;
3509 if (user_ns.flags)
3510 goto out;
3511
3512 r = 0;
395c6b0a 3513 local_irq_disable();
759379dd 3514 now_ns = get_kernel_ns();
afbcf7ab 3515 delta = user_ns.clock - now_ns;
395c6b0a 3516 local_irq_enable();
afbcf7ab
GC		 3517 kvm->arch.kvmclock_offset = delta;
3518 break;
3519 }
3520 case KVM_GET_CLOCK: {
afbcf7ab
GC		 3521 struct kvm_clock_data user_ns;
3522 u64 now_ns;
3523
395c6b0a 3524 local_irq_disable();
759379dd 3525 now_ns = get_kernel_ns();
afbcf7ab 3526 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 3527 local_irq_enable();
afbcf7ab 3528 user_ns.flags = 0;
97e69aa6 3529 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 3530
3531 r = -EFAULT;
3532 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3533 goto out;
3534 r = 0;
3535 break;
3536 }
3537
1fe779f8
CO		 3538 default:
3539 ;
3540 }
3541out:
3542 return r;
3543}
3544
a16b043c 3545static void kvm_init_msr_list(void)
043405e1
CO		 3546{
3547 u32 dummy[2];
3548 unsigned i, j;
3549
e3267cbb
GC		 3550 /* skip the first msrs in the list. KVM-specific */
3551 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3552 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3553 continue;
3554 if (j < i)
3555 msrs_to_save[j] = msrs_to_save[i];
3556 j++;
3557 }
3558 num_msrs_to_save = j;
3559}
3560
bda9020e
MT		 3561static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3562 const void *v)
bbd9b64e 3563{
bda9020e
MT		 3564 if (vcpu->arch.apic &&
3565 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, len, v))
3566 return 0;
bbd9b64e 3567
e93f8a0f 3568 return kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, len, v);
bbd9b64e
CO		 3569}
3570
bda9020e 3571static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 3572{
bda9020e
MT		 3573 if (vcpu->arch.apic &&
3574 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, len, v))
3575 return 0;
bbd9b64e 3576
e93f8a0f 3577 return kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, len, v);
bbd9b64e
CO		 3578}
3579
2dafc6c2
GN		 3580static void kvm_set_segment(struct kvm_vcpu *vcpu,
3581 struct kvm_segment *var, int seg)
3582{
3583 kvm_x86_ops->set_segment(vcpu, var, seg);
3584}
3585
3586void kvm_get_segment(struct kvm_vcpu *vcpu,
3587 struct kvm_segment *var, int seg)
3588{
3589 kvm_x86_ops->get_segment(vcpu, var, seg);
3590}
3591
c30a358d
JR		 3592static gpa_t translate_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
3593{
3594 return gpa;
3595}
3596
02f59dc9
JR		 3597static gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
3598{
3599 gpa_t t_gpa;
3600 u32 error;
3601
3602 BUG_ON(!mmu_is_nested(vcpu));
3603
3604 /* NPT walks are always user-walks */
3605 access |= PFERR_USER_MASK;
3606 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &error);
3607 if (t_gpa == UNMAPPED_GVA)
0959ffac 3608 vcpu->arch.fault.nested = true;
02f59dc9
JR		 3609
3610 return t_gpa;
3611}
3612
1871c602
GN		 3613gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3614{
3615 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
14dfe855 3616 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, error);
1871c602
GN		 3617}
3618
3619 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3620{
3621 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3622 access |= PFERR_FETCH_MASK;
14dfe855 3623 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, error);
1871c602
GN		 3624}
3625
3626gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3627{
3628 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3629 access |= PFERR_WRITE_MASK;
14dfe855 3630 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, error);
1871c602
GN		 3631}
3632
3633/* uses this to access any guest's mapped memory without checking CPL */
3634gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3635{
14dfe855 3636 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, error);
1871c602
GN		 3637}
3638
3639static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3640 struct kvm_vcpu *vcpu, u32 access,
3641 u32 *error)
bbd9b64e
CO		 3642{
3643 void *data = val;
10589a46 3644 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 3645
3646 while (bytes) {
14dfe855
JR		 3647 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
3648 error);
bbd9b64e 3649 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 3650 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 3651 int ret;
3652
10589a46
MT		 3653 if (gpa == UNMAPPED_GVA) {
3654 r = X86EMUL_PROPAGATE_FAULT;
3655 goto out;
3656 }
77c2002e 3657 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46 3658 if (ret < 0) {
c3cd7ffa 3659 r = X86EMUL_IO_NEEDED;
10589a46
MT		 3660 goto out;
3661 }
bbd9b64e 3662
77c2002e
IE		 3663 bytes -= toread;
3664 data += toread;
3665 addr += toread;
bbd9b64e 3666 }
10589a46 3667out:
10589a46 3668 return r;
bbd9b64e 3669}
77c2002e 3670
1871c602
GN		 3671/* used for instruction fetching */
3672static int kvm_fetch_guest_virt(gva_t addr, void *val, unsigned int bytes,
3673 struct kvm_vcpu *vcpu, u32 *error)
3674{
3675 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3676 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
3677 access | PFERR_FETCH_MASK, error);
3678}
3679
3680static int kvm_read_guest_virt(gva_t addr, void *val, unsigned int bytes,
3681 struct kvm_vcpu *vcpu, u32 *error)
3682{
3683 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3684 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
3685 error);
3686}
3687
3688static int kvm_read_guest_virt_system(gva_t addr, void *val, unsigned int bytes,
3689 struct kvm_vcpu *vcpu, u32 *error)
3690{
3691 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, error);
3692}
3693
7972995b 3694static int kvm_write_guest_virt_system(gva_t addr, void *val,
2dafc6c2 3695 unsigned int bytes,
7972995b 3696 struct kvm_vcpu *vcpu,
2dafc6c2 3697 u32 *error)
77c2002e
IE		 3698{
3699 void *data = val;
3700 int r = X86EMUL_CONTINUE;
3701
3702 while (bytes) {
14dfe855
JR		 3703 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
3704 PFERR_WRITE_MASK,
3705 error);
77c2002e
IE		 3706 unsigned offset = addr & (PAGE_SIZE-1);
3707 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
3708 int ret;
3709
3710 if (gpa == UNMAPPED_GVA) {
3711 r = X86EMUL_PROPAGATE_FAULT;
3712 goto out;
3713 }
3714 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
3715 if (ret < 0) {
c3cd7ffa 3716 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 3717 goto out;
3718 }
3719
3720 bytes -= towrite;
3721 data += towrite;
3722 addr += towrite;
3723 }
3724out:
3725 return r;
3726}
3727
bbd9b64e
CO		 3728static int emulator_read_emulated(unsigned long addr,
3729 void *val,
3730 unsigned int bytes,
8fe681e9 3731 unsigned int *error_code,
bbd9b64e
CO		 3732 struct kvm_vcpu *vcpu)
3733{
bbd9b64e
CO		 3734 gpa_t gpa;
3735
3736 if (vcpu->mmio_read_completed) {
3737 memcpy(val, vcpu->mmio_data, bytes);
aec51dc4
AK		 3738 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
3739 vcpu->mmio_phys_addr, *(u64 *)val);
bbd9b64e
CO		 3740 vcpu->mmio_read_completed = 0;
3741 return X86EMUL_CONTINUE;
3742 }
3743
8fe681e9 3744 gpa = kvm_mmu_gva_to_gpa_read(vcpu, addr, error_code);
1871c602 3745
8fe681e9 3746 if (gpa == UNMAPPED_GVA)
1871c602 3747 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 3748
3749 /* For APIC access vmexit */
3750 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3751 goto mmio;
3752
1871c602 3753 if (kvm_read_guest_virt(addr, val, bytes, vcpu, NULL)
77c2002e 3754 == X86EMUL_CONTINUE)
bbd9b64e 3755 return X86EMUL_CONTINUE;
bbd9b64e
CO		 3756
3757mmio:
3758 /*
3759 * Is this MMIO handled locally?
3760 */
aec51dc4
AK		 3761 if (!vcpu_mmio_read(vcpu, gpa, bytes, val)) {
3762 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 3763 return X86EMUL_CONTINUE;
3764 }
aec51dc4
AK		 3765
3766 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
bbd9b64e
CO		 3767
3768 vcpu->mmio_needed = 1;
411c35b7
GN		 3769 vcpu->run->exit_reason = KVM_EXIT_MMIO;
3770 vcpu->run->mmio.phys_addr = vcpu->mmio_phys_addr = gpa;
3771 vcpu->run->mmio.len = vcpu->mmio_size = bytes;
3772 vcpu->run->mmio.is_write = vcpu->mmio_is_write = 0;
bbd9b64e 3773
c3cd7ffa 3774 return X86EMUL_IO_NEEDED;
bbd9b64e
CO		 3775}
3776
3200f405 3777int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
9f811285 3778 const void *val, int bytes)
bbd9b64e
CO		 3779{
3780 int ret;
3781
3782 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 3783 if (ret < 0)
bbd9b64e 3784 return 0;
ad218f85 3785 kvm_mmu_pte_write(vcpu, gpa, val, bytes, 1);
bbd9b64e
CO		 3786 return 1;
3787}
3788
3789static int emulator_write_emulated_onepage(unsigned long addr,
3790 const void *val,
3791 unsigned int bytes,
8fe681e9 3792 unsigned int *error_code,
bbd9b64e
CO		 3793 struct kvm_vcpu *vcpu)
3794{
10589a46
MT		 3795 gpa_t gpa;
3796
8fe681e9 3797 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, error_code);
bbd9b64e 3798
8fe681e9 3799 if (gpa == UNMAPPED_GVA)
bbd9b64e 3800 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 3801
3802 /* For APIC access vmexit */
3803 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3804 goto mmio;
3805
3806 if (emulator_write_phys(vcpu, gpa, val, bytes))
3807 return X86EMUL_CONTINUE;
3808
3809mmio:
aec51dc4 3810 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 3811 /*
3812 * Is this MMIO handled locally?
3813 */
bda9020e 3814 if (!vcpu_mmio_write(vcpu, gpa, bytes, val))
bbd9b64e 3815 return X86EMUL_CONTINUE;
bbd9b64e
CO		 3816
3817 vcpu->mmio_needed = 1;
411c35b7
GN		 3818 vcpu->run->exit_reason = KVM_EXIT_MMIO;
3819 vcpu->run->mmio.phys_addr = vcpu->mmio_phys_addr = gpa;
3820 vcpu->run->mmio.len = vcpu->mmio_size = bytes;
3821 vcpu->run->mmio.is_write = vcpu->mmio_is_write = 1;
3822 memcpy(vcpu->run->mmio.data, val, bytes);
bbd9b64e
CO		 3823
3824 return X86EMUL_CONTINUE;
3825}
3826
3827int emulator_write_emulated(unsigned long addr,
8f6abd06
GN		 3828 const void *val,
3829 unsigned int bytes,
8fe681e9 3830 unsigned int *error_code,
8f6abd06 3831 struct kvm_vcpu *vcpu)
bbd9b64e
CO		 3832{
3833 /* Crossing a page boundary? */
3834 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
3835 int rc, now;
3836
3837 now = -addr & ~PAGE_MASK;
8fe681e9
GN		 3838 rc = emulator_write_emulated_onepage(addr, val, now, error_code,
3839 vcpu);
bbd9b64e
CO		 3840 if (rc != X86EMUL_CONTINUE)
3841 return rc;
3842 addr += now;
3843 val += now;
3844 bytes -= now;
3845 }
8fe681e9
GN		 3846 return emulator_write_emulated_onepage(addr, val, bytes, error_code,
3847 vcpu);
bbd9b64e 3848}
bbd9b64e 3849
daea3e73
AK		 3850#define CMPXCHG_TYPE(t, ptr, old, new) \
3851 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
3852
3853#ifdef CONFIG_X86_64
3854# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
3855#else
3856# define CMPXCHG64(ptr, old, new) \
9749a6c0 3857 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 3858#endif
3859
bbd9b64e
CO		 3860static int emulator_cmpxchg_emulated(unsigned long addr,
3861 const void *old,
3862 const void *new,
3863 unsigned int bytes,
8fe681e9 3864 unsigned int *error_code,
bbd9b64e
CO		 3865 struct kvm_vcpu *vcpu)
3866{
daea3e73
AK		 3867 gpa_t gpa;
3868 struct page *page;
3869 char *kaddr;
3870 bool exchanged;
2bacc55c 3871
daea3e73
AK		 3872 /* guests cmpxchg8b have to be emulated atomically */
3873 if (bytes > 8 || (bytes & (bytes - 1)))
3874 goto emul_write;
10589a46 3875
daea3e73 3876 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 3877
daea3e73
AK		 3878 if (gpa == UNMAPPED_GVA ||
3879 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3880 goto emul_write;
2bacc55c 3881
daea3e73
AK		 3882 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
3883 goto emul_write;
72dc67a6 3884
daea3e73 3885 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
c19b8bd6
WY		 3886 if (is_error_page(page)) {
3887 kvm_release_page_clean(page);
3888 goto emul_write;
3889 }
72dc67a6 3890
daea3e73
AK		 3891 kaddr = kmap_atomic(page, KM_USER0);
3892 kaddr += offset_in_page(gpa);
3893 switch (bytes) {
3894 case 1:
3895 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
3896 break;
3897 case 2:
3898 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
3899 break;
3900 case 4:
3901 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
3902 break;
3903 case 8:
3904 exchanged = CMPXCHG64(kaddr, old, new);
3905 break;
3906 default:
3907 BUG();
2bacc55c 3908 }
daea3e73
AK		 3909 kunmap_atomic(kaddr, KM_USER0);
3910 kvm_release_page_dirty(page);
3911
3912 if (!exchanged)
3913 return X86EMUL_CMPXCHG_FAILED;
3914
8f6abd06
GN		 3915 kvm_mmu_pte_write(vcpu, gpa, new, bytes, 1);
3916
3917 return X86EMUL_CONTINUE;
4a5f48f6 3918
3200f405 3919emul_write:
daea3e73 3920 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 3921
8fe681e9 3922 return emulator_write_emulated(addr, new, bytes, error_code, vcpu);
bbd9b64e
CO		 3923}
3924
cf8f70bf
GN		 3925static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
3926{
3927 /* TODO: String I/O for in kernel device */
3928 int r;
3929
3930 if (vcpu->arch.pio.in)
3931 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
3932 vcpu->arch.pio.size, pd);
3933 else
3934 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
3935 vcpu->arch.pio.port, vcpu->arch.pio.size,
3936 pd);
3937 return r;
3938}
3939
3940
3941static int emulator_pio_in_emulated(int size, unsigned short port, void *val,
3942 unsigned int count, struct kvm_vcpu *vcpu)
3943{
7972995b 3944 if (vcpu->arch.pio.count)
cf8f70bf
GN		 3945 goto data_avail;
3946
c41a15dd 3947 trace_kvm_pio(0, port, size, 1);
cf8f70bf
GN		 3948
3949 vcpu->arch.pio.port = port;
3950 vcpu->arch.pio.in = 1;
7972995b 3951 vcpu->arch.pio.count = count;
cf8f70bf
GN		 3952 vcpu->arch.pio.size = size;
3953
3954 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
3955 data_avail:
3956 memcpy(val, vcpu->arch.pio_data, size * count);
7972995b 3957 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 3958 return 1;
3959 }
3960
3961 vcpu->run->exit_reason = KVM_EXIT_IO;
3962 vcpu->run->io.direction = KVM_EXIT_IO_IN;
3963 vcpu->run->io.size = size;
3964 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
3965 vcpu->run->io.count = count;
3966 vcpu->run->io.port = port;
3967
3968 return 0;
3969}
3970
3971static int emulator_pio_out_emulated(int size, unsigned short port,
3972 const void *val, unsigned int count,
3973 struct kvm_vcpu *vcpu)
3974{
c41a15dd 3975 trace_kvm_pio(1, port, size, 1);
cf8f70bf
GN		 3976
3977 vcpu->arch.pio.port = port;
3978 vcpu->arch.pio.in = 0;
7972995b 3979 vcpu->arch.pio.count = count;
cf8f70bf
GN		 3980 vcpu->arch.pio.size = size;
3981
3982 memcpy(vcpu->arch.pio_data, val, size * count);
3983
3984 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 3985 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 3986 return 1;
3987 }
3988
3989 vcpu->run->exit_reason = KVM_EXIT_IO;
3990 vcpu->run->io.direction = KVM_EXIT_IO_OUT;
3991 vcpu->run->io.size = size;
3992 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
3993 vcpu->run->io.count = count;
3994 vcpu->run->io.port = port;
3995
3996 return 0;
3997}
3998
bbd9b64e
CO		 3999static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4000{
4001 return kvm_x86_ops->get_segment_base(vcpu, seg);
4002}
4003
4004int emulate_invlpg(struct kvm_vcpu *vcpu, gva_t address)
4005{
a7052897 4006 kvm_mmu_invlpg(vcpu, address);
bbd9b64e
CO		 4007 return X86EMUL_CONTINUE;
4008}
4009
f5f48ee1
SY		 4010int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4011{
4012 if (!need_emulate_wbinvd(vcpu))
4013 return X86EMUL_CONTINUE;
4014
4015 if (kvm_x86_ops->has_wbinvd_exit()) {
453d9c57 4016 preempt_disable();
f5f48ee1
SY		 4017 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4018 wbinvd_ipi, NULL, 1);
453d9c57 4019 preempt_enable();
f5f48ee1
SY		 4020 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
4021 }
4022 wbinvd();
4023 return X86EMUL_CONTINUE;
4024}
4025EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4026
bbd9b64e
CO		 4027int emulate_clts(struct kvm_vcpu *vcpu)
4028{
4d4ec087 4029 kvm_x86_ops->set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
6b52d186 4030 kvm_x86_ops->fpu_activate(vcpu);
bbd9b64e
CO		 4031 return X86EMUL_CONTINUE;
4032}
4033
35aa5375 4034int emulator_get_dr(int dr, unsigned long *dest, struct kvm_vcpu *vcpu)
bbd9b64e 4035{
338dbc97 4036 return _kvm_get_dr(vcpu, dr, dest);
bbd9b64e
CO		 4037}
4038
35aa5375 4039int emulator_set_dr(int dr, unsigned long value, struct kvm_vcpu *vcpu)
bbd9b64e 4040{
338dbc97
GN		 4041
4042 return __kvm_set_dr(vcpu, dr, value);
bbd9b64e
CO		 4043}
4044
52a46617 4045static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4046{
52a46617 4047 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4048}
4049
52a46617 4050static unsigned long emulator_get_cr(int cr, struct kvm_vcpu *vcpu)
bbd9b64e 4051{
52a46617
GN		 4052 unsigned long value;
4053
4054 switch (cr) {
4055 case 0:
4056 value = kvm_read_cr0(vcpu);
4057 break;
4058 case 2:
4059 value = vcpu->arch.cr2;
4060 break;
4061 case 3:
4062 value = vcpu->arch.cr3;
4063 break;
4064 case 4:
4065 value = kvm_read_cr4(vcpu);
4066 break;
4067 case 8:
4068 value = kvm_get_cr8(vcpu);
4069 break;
4070 default:
4071 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
4072 return 0;
4073 }
4074
4075 return value;
4076}
4077
0f12244f 4078static int emulator_set_cr(int cr, unsigned long val, struct kvm_vcpu *vcpu)
52a46617 4079{
0f12244f
GN		 4080 int res = 0;
4081
52a46617
GN		 4082 switch (cr) {
4083 case 0:
49a9b07e 4084 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4085 break;
4086 case 2:
4087 vcpu->arch.cr2 = val;
4088 break;
4089 case 3:
2390218b 4090 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4091 break;
4092 case 4:
a83b29c6 4093 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4094 break;
4095 case 8:
0f12244f 4096 res = __kvm_set_cr8(vcpu, val & 0xfUL);
52a46617
GN		 4097 break;
4098 default:
4099 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
0f12244f 4100 res = -1;
52a46617 4101 }
0f12244f
GN		 4102
4103 return res;
52a46617
GN		 4104}
4105
9c537244
GN		 4106static int emulator_get_cpl(struct kvm_vcpu *vcpu)
4107{
4108 return kvm_x86_ops->get_cpl(vcpu);
4109}
4110
2dafc6c2
GN		 4111static void emulator_get_gdt(struct desc_ptr *dt, struct kvm_vcpu *vcpu)
4112{
4113 kvm_x86_ops->get_gdt(vcpu, dt);
4114}
4115
160ce1f1
MG		 4116static void emulator_get_idt(struct desc_ptr *dt, struct kvm_vcpu *vcpu)
4117{
4118 kvm_x86_ops->get_idt(vcpu, dt);
4119}
4120
5951c442
GN		 4121static unsigned long emulator_get_cached_segment_base(int seg,
4122 struct kvm_vcpu *vcpu)
4123{
4124 return get_segment_base(vcpu, seg);
4125}
4126
2dafc6c2
GN		 4127static bool emulator_get_cached_descriptor(struct desc_struct *desc, int seg,
4128 struct kvm_vcpu *vcpu)
4129{
4130 struct kvm_segment var;
4131
4132 kvm_get_segment(vcpu, &var, seg);
4133
4134 if (var.unusable)
4135 return false;
4136
4137 if (var.g)
4138 var.limit >>= 12;
4139 set_desc_limit(desc, var.limit);
4140 set_desc_base(desc, (unsigned long)var.base);
4141 desc->type = var.type;
4142 desc->s = var.s;
4143 desc->dpl = var.dpl;
4144 desc->p = var.present;
4145 desc->avl = var.avl;
4146 desc->l = var.l;
4147 desc->d = var.db;
4148 desc->g = var.g;
4149
4150 return true;
4151}
4152
4153static void emulator_set_cached_descriptor(struct desc_struct *desc, int seg,
4154 struct kvm_vcpu *vcpu)
4155{
4156 struct kvm_segment var;
4157
4158 /* needed to preserve selector */
4159 kvm_get_segment(vcpu, &var, seg);
4160
4161 var.base = get_desc_base(desc);
4162 var.limit = get_desc_limit(desc);
4163 if (desc->g)
4164 var.limit = (var.limit << 12) | 0xfff;
4165 var.type = desc->type;
4166 var.present = desc->p;
4167 var.dpl = desc->dpl;
4168 var.db = desc->d;
4169 var.s = desc->s;
4170 var.l = desc->l;
4171 var.g = desc->g;
4172 var.avl = desc->avl;
4173 var.present = desc->p;
4174 var.unusable = !var.present;
4175 var.padding = 0;
4176
4177 kvm_set_segment(vcpu, &var, seg);
4178 return;
4179}
4180
4181static u16 emulator_get_segment_selector(int seg, struct kvm_vcpu *vcpu)
4182{
4183 struct kvm_segment kvm_seg;
4184
4185 kvm_get_segment(vcpu, &kvm_seg, seg);
4186 return kvm_seg.selector;
4187}
4188
4189static void emulator_set_segment_selector(u16 sel, int seg,
4190 struct kvm_vcpu *vcpu)
4191{
4192 struct kvm_segment kvm_seg;
4193
4194 kvm_get_segment(vcpu, &kvm_seg, seg);
4195 kvm_seg.selector = sel;
4196 kvm_set_segment(vcpu, &kvm_seg, seg);
4197}
4198
14af3f3c 4199static struct x86_emulate_ops emulate_ops = {
1871c602 4200 .read_std = kvm_read_guest_virt_system,
2dafc6c2 4201 .write_std = kvm_write_guest_virt_system,
1871c602 4202 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 4203 .read_emulated = emulator_read_emulated,
4204 .write_emulated = emulator_write_emulated,
4205 .cmpxchg_emulated = emulator_cmpxchg_emulated,
cf8f70bf
GN		 4206 .pio_in_emulated = emulator_pio_in_emulated,
4207 .pio_out_emulated = emulator_pio_out_emulated,
2dafc6c2
GN		 4208 .get_cached_descriptor = emulator_get_cached_descriptor,
4209 .set_cached_descriptor = emulator_set_cached_descriptor,
4210 .get_segment_selector = emulator_get_segment_selector,
4211 .set_segment_selector = emulator_set_segment_selector,
5951c442 4212 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 4213 .get_gdt = emulator_get_gdt,
160ce1f1 4214 .get_idt = emulator_get_idt,
52a46617
GN		 4215 .get_cr = emulator_get_cr,
4216 .set_cr = emulator_set_cr,
9c537244 4217 .cpl = emulator_get_cpl,
35aa5375
GN		 4218 .get_dr = emulator_get_dr,
4219 .set_dr = emulator_set_dr,
3fb1b5db
GN		 4220 .set_msr = kvm_set_msr,
4221 .get_msr = kvm_get_msr,
bbd9b64e
CO		 4222};
4223
5fdbf976
MT		 4224static void cache_all_regs(struct kvm_vcpu *vcpu)
4225{
4226 kvm_register_read(vcpu, VCPU_REGS_RAX);
4227 kvm_register_read(vcpu, VCPU_REGS_RSP);
4228 kvm_register_read(vcpu, VCPU_REGS_RIP);
4229 vcpu->arch.regs_dirty = ~0;
4230}
4231
95cb2295
GN		 4232static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4233{
4234 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
4235 /*
4236 * an sti; sti; sequence only disable interrupts for the first
4237 * instruction. So, if the last instruction, be it emulated or
4238 * not, left the system with the INT_STI flag enabled, it
4239 * means that the last instruction is an sti. We should not
4240 * leave the flag on in this case. The same goes for mov ss
4241 */
4242 if (!(int_shadow & mask))
4243 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4244}
4245
54b8486f
GN		 4246static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4247{
4248 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4249 if (ctxt->exception == PF_VECTOR)
d4f8cf66 4250 kvm_propagate_fault(vcpu);
54b8486f
GN		 4251 else if (ctxt->error_code_valid)
4252 kvm_queue_exception_e(vcpu, ctxt->exception, ctxt->error_code);
4253 else
4254 kvm_queue_exception(vcpu, ctxt->exception);
4255}
4256
8ec4722d
MG		 4257static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4258{
4259 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
4260 int cs_db, cs_l;
4261
4262 cache_all_regs(vcpu);
4263
4264 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4265
4266 vcpu->arch.emulate_ctxt.vcpu = vcpu;
4267 vcpu->arch.emulate_ctxt.eflags = kvm_x86_ops->get_rflags(vcpu);
4268 vcpu->arch.emulate_ctxt.eip = kvm_rip_read(vcpu);
4269 vcpu->arch.emulate_ctxt.mode =
4270 (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4271 (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM)
4272 ? X86EMUL_MODE_VM86 : cs_l
4273 ? X86EMUL_MODE_PROT64 : cs_db
4274 ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
4275 memset(c, 0, sizeof(struct decode_cache));
4276 memcpy(c->regs, vcpu->arch.regs, sizeof c->regs);
4277}
4278
63995653
MG		 4279int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq)
4280{
4281 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
4282 int ret;
4283
4284 init_emulate_ctxt(vcpu);
4285
4286 vcpu->arch.emulate_ctxt.decode.op_bytes = 2;
4287 vcpu->arch.emulate_ctxt.decode.ad_bytes = 2;
4288 vcpu->arch.emulate_ctxt.decode.eip = vcpu->arch.emulate_ctxt.eip;
4289 ret = emulate_int_real(&vcpu->arch.emulate_ctxt, &emulate_ops, irq);
4290
4291 if (ret != X86EMUL_CONTINUE)
4292 return EMULATE_FAIL;
4293
4294 vcpu->arch.emulate_ctxt.eip = c->eip;
4295 memcpy(vcpu->arch.regs, c->regs, sizeof c->regs);
4296 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.eip);
4297 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
4298
4299 if (irq == NMI_VECTOR)
4300 vcpu->arch.nmi_pending = false;
4301 else
4302 vcpu->arch.interrupt.pending = false;
4303
4304 return EMULATE_DONE;
4305}
4306EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4307
6d77dbfc
GN		 4308static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4309{
6d77dbfc
GN		 4310 ++vcpu->stat.insn_emulation_fail;
4311 trace_kvm_emulate_insn_failed(vcpu);
4312 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4313 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4314 vcpu->run->internal.ndata = 0;
4315 kvm_queue_exception(vcpu, UD_VECTOR);
4316 return EMULATE_FAIL;
4317}
4318
a6f177ef
GN		 4319static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t gva)
4320{
4321 gpa_t gpa;
4322
68be0803
GN		 4323 if (tdp_enabled)
4324 return false;
4325
a6f177ef
GN		 4326 /*
4327 * if emulation was due to access to shadowed page table
4328 * and it failed try to unshadow page and re-entetr the
4329 * guest to let CPU execute the instruction.
4330 */
4331 if (kvm_mmu_unprotect_page_virt(vcpu, gva))
4332 return true;
4333
4334 gpa = kvm_mmu_gva_to_gpa_system(vcpu, gva, NULL);
4335
4336 if (gpa == UNMAPPED_GVA)
4337 return true; /* let cpu generate fault */
4338
4339 if (!kvm_is_error_hva(gfn_to_hva(vcpu->kvm, gpa >> PAGE_SHIFT)))
4340 return true;
4341
4342 return false;
4343}
4344
bbd9b64e 4345int emulate_instruction(struct kvm_vcpu *vcpu,
bbd9b64e
CO		 4346 unsigned long cr2,
4347 u16 error_code,
571008da 4348 int emulation_type)
bbd9b64e 4349{
95cb2295 4350 int r;
4d2179e1 4351 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
bbd9b64e 4352
26eef70c 4353 kvm_clear_exception_queue(vcpu);
ad312c7c 4354 vcpu->arch.mmio_fault_cr2 = cr2;
5fdbf976 4355 /*
56e82318 4356 * TODO: fix emulate.c to use guest_read/write_register
5fdbf976
MT		 4357 * instead of direct ->regs accesses, can save hundred cycles
4358 * on Intel for instructions that don't read/change RSP, for
4359 * for example.
4360 */
4361 cache_all_regs(vcpu);
bbd9b64e 4362
571008da 4363 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 4364 init_emulate_ctxt(vcpu);
95cb2295 4365 vcpu->arch.emulate_ctxt.interruptibility = 0;
54b8486f 4366 vcpu->arch.emulate_ctxt.exception = -1;
4fc40f07 4367 vcpu->arch.emulate_ctxt.perm_ok = false;
bbd9b64e 4368
9aabc88f 4369 r = x86_decode_insn(&vcpu->arch.emulate_ctxt);
d47f00a6
JR		 4370 if (r == X86EMUL_PROPAGATE_FAULT)
4371 goto done;
bbd9b64e 4372
e46479f8 4373 trace_kvm_emulate_insn_start(vcpu);
571008da 4374
0cb5762e
AP		 4375 /* Only allow emulation of specific instructions on #UD
4376 * (namely VMMCALL, sysenter, sysexit, syscall)*/
0cb5762e
AP		 4377 if (emulation_type & EMULTYPE_TRAP_UD) {
4378 if (!c->twobyte)
4379 return EMULATE_FAIL;
4380 switch (c->b) {
4381 case 0x01: /* VMMCALL */
4382 if (c->modrm_mod != 3 || c->modrm_rm != 1)
4383 return EMULATE_FAIL;
4384 break;
4385 case 0x34: /* sysenter */
4386 case 0x35: /* sysexit */
4387 if (c->modrm_mod != 0 || c->modrm_rm != 0)
4388 return EMULATE_FAIL;
4389 break;
4390 case 0x05: /* syscall */
4391 if (c->modrm_mod != 0 || c->modrm_rm != 0)
4392 return EMULATE_FAIL;
4393 break;
4394 default:
4395 return EMULATE_FAIL;
4396 }
4397
4398 if (!(c->modrm_reg == 0 || c->modrm_reg == 3))
4399 return EMULATE_FAIL;
4400 }
571008da 4401
f2b5756b 4402 ++vcpu->stat.insn_emulation;
bbd9b64e 4403 if (r) {
a6f177ef 4404 if (reexecute_instruction(vcpu, cr2))
bbd9b64e 4405 return EMULATE_DONE;
6d77dbfc
GN		 4406 if (emulation_type & EMULTYPE_SKIP)
4407 return EMULATE_FAIL;
4408 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4409 }
4410 }
4411
ba8afb6b
GN		 4412 if (emulation_type & EMULTYPE_SKIP) {
4413 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.decode.eip);
4414 return EMULATE_DONE;
4415 }
4416
4d2179e1
GN		 4417 /* this is needed for vmware backdor interface to work since it
4418 changes registers values during IO operation */
4419 memcpy(c->regs, vcpu->arch.regs, sizeof c->regs);
4420
5cd21917 4421restart:
9aabc88f 4422 r = x86_emulate_insn(&vcpu->arch.emulate_ctxt);
bbd9b64e 4423
d2ddd1c4 4424 if (r == EMULATION_FAILED) {
a6f177ef 4425 if (reexecute_instruction(vcpu, cr2))
c3cd7ffa
GN		 4426 return EMULATE_DONE;
4427
6d77dbfc 4428 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4429 }
4430
d47f00a6 4431done:
54b8486f
GN		 4432 if (vcpu->arch.emulate_ctxt.exception >= 0) {
4433 inject_emulated_exception(vcpu);
d2ddd1c4
GN		 4434 r = EMULATE_DONE;
4435 } else if (vcpu->arch.pio.count) {
3457e419
GN		 4436 if (!vcpu->arch.pio.in)
4437 vcpu->arch.pio.count = 0;
e85d28f8
GN		 4438 r = EMULATE_DO_MMIO;
4439 } else if (vcpu->mmio_needed) {
3457e419
GN		 4440 if (vcpu->mmio_is_write)
4441 vcpu->mmio_needed = 0;
e85d28f8 4442 r = EMULATE_DO_MMIO;
d2ddd1c4 4443 } else if (r == EMULATION_RESTART)
5cd21917 4444 goto restart;
d2ddd1c4
GN		 4445 else
4446 r = EMULATE_DONE;
f850e2e6 4447
e85d28f8
GN		 4448 toggle_interruptibility(vcpu, vcpu->arch.emulate_ctxt.interruptibility);
4449 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
3842d135 4450 kvm_make_request(KVM_REQ_EVENT, vcpu);
e85d28f8
GN		 4451 memcpy(vcpu->arch.regs, c->regs, sizeof c->regs);
4452 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.eip);
4453
4454 return r;
de7d789a 4455}
bbd9b64e 4456EXPORT_SYMBOL_GPL(emulate_instruction);
de7d789a 4457
cf8f70bf 4458int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 4459{
cf8f70bf
GN		 4460 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
4461 int ret = emulator_pio_out_emulated(size, port, &val, 1, vcpu);
4462 /* do not return to emulator after return from userspace */
7972995b 4463 vcpu->arch.pio.count = 0;
de7d789a
CO		 4464 return ret;
4465}
cf8f70bf 4466EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 4467
8cfdc000
ZA		 4468static void tsc_bad(void *info)
4469{
4470 __get_cpu_var(cpu_tsc_khz) = 0;
4471}
4472
4473static void tsc_khz_changed(void *data)
c8076604 4474{
8cfdc000
ZA		 4475 struct cpufreq_freqs *freq = data;
4476 unsigned long khz = 0;
4477
4478 if (data)
4479 khz = freq->new;
4480 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4481 khz = cpufreq_quick_get(raw_smp_processor_id());
4482 if (!khz)
4483 khz = tsc_khz;
4484 __get_cpu_var(cpu_tsc_khz) = khz;
c8076604
GH		 4485}
4486
c8076604
GH		 4487static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
4488 void *data)
4489{
4490 struct cpufreq_freqs *freq = data;
4491 struct kvm *kvm;
4492 struct kvm_vcpu *vcpu;
4493 int i, send_ipi = 0;
4494
8cfdc000
ZA		 4495 /*
4496 * We allow guests to temporarily run on slowing clocks,
4497 * provided we notify them after, or to run on accelerating
4498 * clocks, provided we notify them before. Thus time never
4499 * goes backwards.
4500 *
4501 * However, we have a problem. We can't atomically update
4502 * the frequency of a given CPU from this function; it is
4503 * merely a notifier, which can be called from any CPU.
4504 * Changing the TSC frequency at arbitrary points in time
4505 * requires a recomputation of local variables related to
4506 * the TSC for each VCPU. We must flag these local variables
4507 * to be updated and be sure the update takes place with the
4508 * new frequency before any guests proceed.
4509 *
4510 * Unfortunately, the combination of hotplug CPU and frequency
4511 * change creates an intractable locking scenario; the order
4512 * of when these callouts happen is undefined with respect to
4513 * CPU hotplug, and they can race with each other. As such,
4514 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
4515 * undefined; you can actually have a CPU frequency change take
4516 * place in between the computation of X and the setting of the
4517 * variable. To protect against this problem, all updates of
4518 * the per_cpu tsc_khz variable are done in an interrupt
4519 * protected IPI, and all callers wishing to update the value
4520 * must wait for a synchronous IPI to complete (which is trivial
4521 * if the caller is on the CPU already). This establishes the
4522 * necessary total order on variable updates.
4523 *
4524 * Note that because a guest time update may take place
4525 * anytime after the setting of the VCPU's request bit, the
4526 * correct TSC value must be set before the request. However,
4527 * to ensure the update actually makes it to any guest which
4528 * starts running in hardware virtualization between the set
4529 * and the acquisition of the spinlock, we must also ping the
4530 * CPU after setting the request bit.
4531 *
4532 */
4533
c8076604
GH		 4534 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
4535 return 0;
4536 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
4537 return 0;
8cfdc000
ZA		 4538
4539 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 4540
4541 spin_lock(&kvm_lock);
4542 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 4543 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 4544 if (vcpu->cpu != freq->cpu)
4545 continue;
c285545f 4546 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 4547 if (vcpu->cpu != smp_processor_id())
8cfdc000 4548 send_ipi = 1;
c8076604
GH		 4549 }
4550 }
4551 spin_unlock(&kvm_lock);
4552
4553 if (freq->old < freq->new && send_ipi) {
4554 /*
4555 * We upscale the frequency. Must make the guest
4556 * doesn't see old kvmclock values while running with
4557 * the new frequency, otherwise we risk the guest sees
4558 * time go backwards.
4559 *
4560 * In case we update the frequency for another cpu
4561 * (which might be in guest context) send an interrupt
4562 * to kick the cpu out of guest context. Next time
4563 * guest context is entered kvmclock will be updated,
4564 * so the guest will not see stale values.
4565 */
8cfdc000 4566 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 4567 }
4568 return 0;
4569}
4570
4571static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 4572 .notifier_call = kvmclock_cpufreq_notifier
4573};
4574
4575static int kvmclock_cpu_notifier(struct notifier_block *nfb,
4576 unsigned long action, void *hcpu)
4577{
4578 unsigned int cpu = (unsigned long)hcpu;
4579
4580 switch (action) {
4581 case CPU_ONLINE:
4582 case CPU_DOWN_FAILED:
4583 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
4584 break;
4585 case CPU_DOWN_PREPARE:
4586 smp_call_function_single(cpu, tsc_bad, NULL, 1);
4587 break;
4588 }
4589 return NOTIFY_OK;
4590}
4591
4592static struct notifier_block kvmclock_cpu_notifier_block = {
4593 .notifier_call = kvmclock_cpu_notifier,
4594 .priority = -INT_MAX
c8076604
GH		 4595};
4596
b820cc0c
ZA		 4597static void kvm_timer_init(void)
4598{
4599 int cpu;
4600
c285545f 4601 max_tsc_khz = tsc_khz;
8cfdc000 4602 register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
b820cc0c 4603 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 4604#ifdef CONFIG_CPU_FREQ
4605 struct cpufreq_policy policy;
4606 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 4607 cpu = get_cpu();
4608 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 4609 if (policy.cpuinfo.max_freq)
4610 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 4611 put_cpu();
c285545f 4612#endif
b820cc0c
ZA		 4613 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
4614 CPUFREQ_TRANSITION_NOTIFIER);
4615 }
c285545f 4616 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 4617 for_each_online_cpu(cpu)
4618 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
b820cc0c
ZA		 4619}
4620
ff9d07a0
ZY		 4621static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
4622
4623static int kvm_is_in_guest(void)
4624{
4625 return percpu_read(current_vcpu) != NULL;
4626}
4627
4628static int kvm_is_user_mode(void)
4629{
4630 int user_mode = 3;
dcf46b94 4631
ff9d07a0
ZY		 4632 if (percpu_read(current_vcpu))
4633 user_mode = kvm_x86_ops->get_cpl(percpu_read(current_vcpu));
dcf46b94 4634
ff9d07a0
ZY		 4635 return user_mode != 0;
4636}
4637
4638static unsigned long kvm_get_guest_ip(void)
4639{
4640 unsigned long ip = 0;
dcf46b94 4641
ff9d07a0
ZY		 4642 if (percpu_read(current_vcpu))
4643 ip = kvm_rip_read(percpu_read(current_vcpu));
dcf46b94 4644
ff9d07a0
ZY		 4645 return ip;
4646}
4647
4648static struct perf_guest_info_callbacks kvm_guest_cbs = {
4649 .is_in_guest = kvm_is_in_guest,
4650 .is_user_mode = kvm_is_user_mode,
4651 .get_guest_ip = kvm_get_guest_ip,
4652};
4653
4654void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
4655{
4656 percpu_write(current_vcpu, vcpu);
4657}
4658EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
4659
4660void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
4661{
4662 percpu_write(current_vcpu, NULL);
4663}
4664EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
4665
f8c16bba 4666int kvm_arch_init(void *opaque)
043405e1 4667{
b820cc0c 4668 int r;
f8c16bba
ZX		 4669 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
4670
f8c16bba
ZX		 4671 if (kvm_x86_ops) {
4672 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 4673 r = -EEXIST;
4674 goto out;
f8c16bba
ZX		 4675 }
4676
4677 if (!ops->cpu_has_kvm_support()) {
4678 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 4679 r = -EOPNOTSUPP;
4680 goto out;
f8c16bba
ZX		 4681 }
4682 if (ops->disabled_by_bios()) {
4683 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 4684 r = -EOPNOTSUPP;
4685 goto out;
f8c16bba
ZX		 4686 }
4687
97db56ce
AK		 4688 r = kvm_mmu_module_init();
4689 if (r)
4690 goto out;
4691
4692 kvm_init_msr_list();
4693
f8c16bba 4694 kvm_x86_ops = ops;
56c6d28a 4695 kvm_mmu_set_nonpresent_ptes(0ull, 0ull);
7b52345e 4696 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 4697 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 4698
b820cc0c 4699 kvm_timer_init();
c8076604 4700
ff9d07a0
ZY		 4701 perf_register_guest_info_callbacks(&kvm_guest_cbs);
4702
2acf923e
DC		 4703 if (cpu_has_xsave)
4704 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
4705
f8c16bba 4706 return 0;
56c6d28a
ZX		 4707
4708out:
56c6d28a 4709 return r;
043405e1 4710}
8776e519 4711
f8c16bba
ZX		 4712void kvm_arch_exit(void)
4713{
ff9d07a0
ZY		 4714 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
4715
888d256e
JK		 4716 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4717 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
4718 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 4719 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
f8c16bba 4720 kvm_x86_ops = NULL;
56c6d28a
ZX		 4721 kvm_mmu_module_exit();
4722}
f8c16bba 4723
8776e519
HB		 4724int kvm_emulate_halt(struct kvm_vcpu *vcpu)
4725{
4726 ++vcpu->stat.halt_exits;
4727 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 4728 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 4729 return 1;
4730 } else {
4731 vcpu->run->exit_reason = KVM_EXIT_HLT;
4732 return 0;
4733 }
4734}
4735EXPORT_SYMBOL_GPL(kvm_emulate_halt);
4736
2f333bcb
MT		 4737static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0,
4738 unsigned long a1)
4739{
4740 if (is_long_mode(vcpu))
4741 return a0;
4742 else
4743 return a0 | ((gpa_t)a1 << 32);
4744}
4745
55cd8e5a
GN		 4746int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
4747{
4748 u64 param, ingpa, outgpa, ret;
4749 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
4750 bool fast, longmode;
4751 int cs_db, cs_l;
4752
4753 /*
4754 * hypercall generates UD from non zero cpl and real mode
4755 * per HYPER-V spec
4756 */
3eeb3288 4757 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 4758 kvm_queue_exception(vcpu, UD_VECTOR);
4759 return 0;
4760 }
4761
4762 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4763 longmode = is_long_mode(vcpu) && cs_l == 1;
4764
4765 if (!longmode) {
ccd46936
GN		 4766 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
4767 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
4768 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
4769 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
4770 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
4771 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 4772 }
4773#ifdef CONFIG_X86_64
4774 else {
4775 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
4776 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
4777 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
4778 }
4779#endif
4780
4781 code = param & 0xffff;
4782 fast = (param >> 16) & 0x1;
4783 rep_cnt = (param >> 32) & 0xfff;
4784 rep_idx = (param >> 48) & 0xfff;
4785
4786 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
4787
c25bc163
GN		 4788 switch (code) {
4789 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
4790 kvm_vcpu_on_spin(vcpu);
4791 break;
4792 default:
4793 res = HV_STATUS_INVALID_HYPERCALL_CODE;
4794 break;
4795 }
55cd8e5a
GN		 4796
4797 ret = res | (((u64)rep_done & 0xfff) << 32);
4798 if (longmode) {
4799 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
4800 } else {
4801 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
4802 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
4803 }
4804
4805 return 1;
4806}
4807
8776e519
HB		 4808int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
4809{
4810 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 4811 int r = 1;
8776e519 4812
55cd8e5a
GN		 4813 if (kvm_hv_hypercall_enabled(vcpu->kvm))
4814 return kvm_hv_hypercall(vcpu);
4815
5fdbf976
MT		 4816 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
4817 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
4818 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
4819 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
4820 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 4821
229456fc 4822 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 4823
8776e519
HB		 4824 if (!is_long_mode(vcpu)) {
4825 nr &= 0xFFFFFFFF;
4826 a0 &= 0xFFFFFFFF;
4827 a1 &= 0xFFFFFFFF;
4828 a2 &= 0xFFFFFFFF;
4829 a3 &= 0xFFFFFFFF;
4830 }
4831
07708c4a
JK		 4832 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
4833 ret = -KVM_EPERM;
4834 goto out;
4835 }
4836
8776e519 4837 switch (nr) {
b93463aa
AK		 4838 case KVM_HC_VAPIC_POLL_IRQ:
4839 ret = 0;
4840 break;
2f333bcb
MT		 4841 case KVM_HC_MMU_OP:
4842 r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret);
4843 break;
8776e519
HB		 4844 default:
4845 ret = -KVM_ENOSYS;
4846 break;
4847 }
07708c4a 4848out:
5fdbf976 4849 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 4850 ++vcpu->stat.hypercalls;
2f333bcb 4851 return r;
8776e519
HB		 4852}
4853EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
4854
4855int kvm_fix_hypercall(struct kvm_vcpu *vcpu)
4856{
4857 char instruction[3];
5fdbf976 4858 unsigned long rip = kvm_rip_read(vcpu);
8776e519 4859
8776e519
HB		 4860 /*
4861 * Blow out the MMU to ensure that no other VCPU has an active mapping
4862 * to ensure that the updated hypercall appears atomically across all
4863 * VCPUs.
4864 */
4865 kvm_mmu_zap_all(vcpu->kvm);
4866
8776e519 4867 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 4868
8fe681e9 4869 return emulator_write_emulated(rip, instruction, 3, NULL, vcpu);
8776e519
HB		 4870}
4871
8776e519
HB		 4872void realmode_lgdt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
4873{
89a27f4d 4874 struct desc_ptr dt = { limit, base };
8776e519
HB		 4875
4876 kvm_x86_ops->set_gdt(vcpu, &dt);
4877}
4878
4879void realmode_lidt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
4880{
89a27f4d 4881 struct desc_ptr dt = { limit, base };
8776e519
HB		 4882
4883 kvm_x86_ops->set_idt(vcpu, &dt);
4884}
4885
07716717
DK		 4886static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)
4887{
ad312c7c
ZX		 4888 struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];
4889 int j, nent = vcpu->arch.cpuid_nent;
07716717
DK		 4890
4891 e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;
4892 /* when no next entry is found, the current entry[i] is reselected */
0fdf8e59 4893 for (j = i + 1; ; j = (j + 1) % nent) {
ad312c7c 4894 struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j];
07716717
DK		 4895 if (ej->function == e->function) {
4896 ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
4897 return j;
4898 }
4899 }
4900 return 0; /* silence gcc, even though control never reaches here */
4901}
4902
4903/* find an entry with matching function, matching index (if needed), and that
4904 * should be read next (if it's stateful) */
4905static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e,
4906 u32 function, u32 index)
4907{
4908 if (e->function != function)
4909 return 0;
4910 if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index)
4911 return 0;
4912 if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) &&
19355475 4913 !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT))
07716717
DK		 4914 return 0;
4915 return 1;
4916}
4917
d8017474
AG		 4918struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
4919 u32 function, u32 index)
8776e519
HB		 4920{
4921 int i;
d8017474 4922 struct kvm_cpuid_entry2 *best = NULL;
8776e519 4923
ad312c7c 4924 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
d8017474
AG		 4925 struct kvm_cpuid_entry2 *e;
4926
ad312c7c 4927 e = &vcpu->arch.cpuid_entries[i];
07716717
DK		 4928 if (is_matching_cpuid_entry(e, function, index)) {
4929 if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC)
4930 move_to_next_stateful_cpuid_entry(vcpu, i);
8776e519
HB		 4931 best = e;
4932 break;
4933 }
4934 /*
4935 * Both basic or both extended?
4936 */
4937 if (((e->function ^ function) & 0x80000000) == 0)
4938 if (!best || e->function > best->function)
4939 best = e;
4940 }
d8017474
AG		 4941 return best;
4942}
0e851880 4943EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry);
d8017474 4944
82725b20
DE		 4945int cpuid_maxphyaddr(struct kvm_vcpu *vcpu)
4946{
4947 struct kvm_cpuid_entry2 *best;
4948
f7a71197
AK		 4949 best = kvm_find_cpuid_entry(vcpu, 0x80000000, 0);
4950 if (!best || best->eax < 0x80000008)
4951 goto not_found;
82725b20
DE		 4952 best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0);
4953 if (best)
4954 return best->eax & 0xff;
f7a71197 4955not_found:
82725b20
DE		 4956 return 36;
4957}
4958
d8017474
AG		 4959void kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
4960{
4961 u32 function, index;
4962 struct kvm_cpuid_entry2 *best;
4963
4964 function = kvm_register_read(vcpu, VCPU_REGS_RAX);
4965 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
4966 kvm_register_write(vcpu, VCPU_REGS_RAX, 0);
4967 kvm_register_write(vcpu, VCPU_REGS_RBX, 0);
4968 kvm_register_write(vcpu, VCPU_REGS_RCX, 0);
4969 kvm_register_write(vcpu, VCPU_REGS_RDX, 0);
4970 best = kvm_find_cpuid_entry(vcpu, function, index);
8776e519 4971 if (best) {
5fdbf976
MT		 4972 kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax);
4973 kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx);
4974 kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx);
4975 kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx);
8776e519 4976 }
8776e519 4977 kvm_x86_ops->skip_emulated_instruction(vcpu);
229456fc
MT		 4978 trace_kvm_cpuid(function,
4979 kvm_register_read(vcpu, VCPU_REGS_RAX),
4980 kvm_register_read(vcpu, VCPU_REGS_RBX),
4981 kvm_register_read(vcpu, VCPU_REGS_RCX),
4982 kvm_register_read(vcpu, VCPU_REGS_RDX));
8776e519
HB		 4983}
4984EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
d0752060 4985
b6c7a5dc
HB		 4986/*
4987 * Check if userspace requested an interrupt window, and that the
4988 * interrupt window is open.
4989 *
4990 * No need to exit to userspace if we already have an interrupt queued.
4991 */
851ba692 4992static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 4993{
8061823a 4994 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 4995 vcpu->run->request_interrupt_window &&
5df56646 4996 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 4997}
4998
851ba692 4999static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 5000{
851ba692
AK		 5001 struct kvm_run *kvm_run = vcpu->run;
5002
91586a3b 5003 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 5004 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 5005 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 5006 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 5007 kvm_run->ready_for_interrupt_injection = 1;
4531220b 5008 else
b6c7a5dc 5009 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 5010 kvm_arch_interrupt_allowed(vcpu) &&
5011 !kvm_cpu_has_interrupt(vcpu) &&
5012 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 5013}
5014
b93463aa
AK		 5015static void vapic_enter(struct kvm_vcpu *vcpu)
5016{
5017 struct kvm_lapic *apic = vcpu->arch.apic;
5018 struct page *page;
5019
5020 if (!apic || !apic->vapic_addr)
5021 return;
5022
5023 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
72dc67a6
IE		 5024
5025 vcpu->arch.apic->vapic_page = page;
b93463aa
AK		 5026}
5027
5028static void vapic_exit(struct kvm_vcpu *vcpu)
5029{
5030 struct kvm_lapic *apic = vcpu->arch.apic;
f656ce01 5031 int idx;
b93463aa
AK		 5032
5033 if (!apic || !apic->vapic_addr)
5034 return;
5035
f656ce01 5036 idx = srcu_read_lock(&vcpu->kvm->srcu);
b93463aa
AK		 5037 kvm_release_page_dirty(apic->vapic_page);
5038 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f656ce01 5039 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 5040}
5041
95ba8273
GN		 5042static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5043{
5044 int max_irr, tpr;
5045
5046 if (!kvm_x86_ops->update_cr8_intercept)
5047 return;
5048
88c808fd
AK		 5049 if (!vcpu->arch.apic)
5050 return;
5051
8db3baa2
GN		 5052 if (!vcpu->arch.apic->vapic_addr)
5053 max_irr = kvm_lapic_find_highest_irr(vcpu);
5054 else
5055 max_irr = -1;
95ba8273
GN		 5056
5057 if (max_irr != -1)
5058 max_irr >>= 4;
5059
5060 tpr = kvm_lapic_get_cr8(vcpu);
5061
5062 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5063}
5064
851ba692 5065static void inject_pending_event(struct kvm_vcpu *vcpu)
95ba8273
GN		 5066{
5067 /* try to reinject previous events if any */
b59bb7bd 5068 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 5069 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5070 vcpu->arch.exception.has_error_code,
5071 vcpu->arch.exception.error_code);
b59bb7bd
GN		 5072 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5073 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 5074 vcpu->arch.exception.error_code,
5075 vcpu->arch.exception.reinject);
b59bb7bd
GN		 5076 return;
5077 }
5078
95ba8273
GN		 5079 if (vcpu->arch.nmi_injected) {
5080 kvm_x86_ops->set_nmi(vcpu);
5081 return;
5082 }
5083
5084 if (vcpu->arch.interrupt.pending) {
66fd3f7f 5085 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5086 return;
5087 }
5088
5089 /* try to inject new event if pending */
5090 if (vcpu->arch.nmi_pending) {
5091 if (kvm_x86_ops->nmi_allowed(vcpu)) {
5092 vcpu->arch.nmi_pending = false;
5093 vcpu->arch.nmi_injected = true;
5094 kvm_x86_ops->set_nmi(vcpu);
5095 }
5096 } else if (kvm_cpu_has_interrupt(vcpu)) {
5097 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 5098 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5099 false);
5100 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5101 }
5102 }
5103}
5104
2acf923e
DC		 5105static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
5106{
5107 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
5108 !vcpu->guest_xcr0_loaded) {
5109 /* kvm_set_xcr() also depends on this */
5110 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
5111 vcpu->guest_xcr0_loaded = 1;
5112 }
5113}
5114
5115static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
5116{
5117 if (vcpu->guest_xcr0_loaded) {
5118 if (vcpu->arch.xcr0 != host_xcr0)
5119 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
5120 vcpu->guest_xcr0_loaded = 0;
5121 }
5122}
5123
851ba692 5124static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 5125{
5126 int r;
6a8b1d13 5127 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 5128 vcpu->run->request_interrupt_window;
b6c7a5dc 5129
3e007509 5130 if (vcpu->requests) {
a8eeb04a 5131 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 5132 kvm_mmu_unload(vcpu);
a8eeb04a 5133 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 5134 __kvm_migrate_timers(vcpu);
34c238a1
ZA		 5135 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
5136 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 5137 if (unlikely(r))
5138 goto out;
5139 }
a8eeb04a 5140 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 5141 kvm_mmu_sync_roots(vcpu);
a8eeb04a 5142 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
d4acf7e7 5143 kvm_x86_ops->tlb_flush(vcpu);
a8eeb04a 5144 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 5145 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 5146 r = 0;
5147 goto out;
5148 }
a8eeb04a 5149 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 5150 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 5151 r = 0;
5152 goto out;
5153 }
a8eeb04a 5154 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 5155 vcpu->fpu_active = 0;
5156 kvm_x86_ops->fpu_deactivate(vcpu);
5157 }
af585b92
GN		 5158 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
5159 /* Page is swapped out. Do synthetic halt */
5160 vcpu->arch.apf.halted = true;
5161 r = 1;
5162 goto out;
5163 }
2f52d58c 5164 }
b93463aa 5165
3e007509
AK		 5166 r = kvm_mmu_reload(vcpu);
5167 if (unlikely(r))
5168 goto out;
5169
b463a6f7
AK		 5170 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
5171 inject_pending_event(vcpu);
5172
5173 /* enable NMI/IRQ window open exits if needed */
5174 if (vcpu->arch.nmi_pending)
5175 kvm_x86_ops->enable_nmi_window(vcpu);
5176 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
5177 kvm_x86_ops->enable_irq_window(vcpu);
5178
5179 if (kvm_lapic_enabled(vcpu)) {
5180 update_cr8_intercept(vcpu);
5181 kvm_lapic_sync_to_vapic(vcpu);
5182 }
5183 }
5184
b6c7a5dc
HB		 5185 preempt_disable();
5186
5187 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 5188 if (vcpu->fpu_active)
5189 kvm_load_guest_fpu(vcpu);
2acf923e 5190 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 5191
d94e1dc9
AK		 5192 atomic_set(&vcpu->guest_mode, 1);
5193 smp_wmb();
b6c7a5dc 5194
d94e1dc9 5195 local_irq_disable();
32f88400 5196
d94e1dc9
AK		 5197 if (!atomic_read(&vcpu->guest_mode) || vcpu->requests
5198 || need_resched() || signal_pending(current)) {
5199 atomic_set(&vcpu->guest_mode, 0);
5200 smp_wmb();
6c142801
AK		 5201 local_irq_enable();
5202 preempt_enable();
b463a6f7 5203 kvm_x86_ops->cancel_injection(vcpu);
6c142801
AK		 5204 r = 1;
5205 goto out;
5206 }
5207
f656ce01 5208 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
3200f405 5209
b6c7a5dc
HB		 5210 kvm_guest_enter();
5211
42dbaa5a 5212 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 5213 set_debugreg(0, 7);
5214 set_debugreg(vcpu->arch.eff_db[0], 0);
5215 set_debugreg(vcpu->arch.eff_db[1], 1);
5216 set_debugreg(vcpu->arch.eff_db[2], 2);
5217 set_debugreg(vcpu->arch.eff_db[3], 3);
5218 }
b6c7a5dc 5219
229456fc 5220 trace_kvm_entry(vcpu->vcpu_id);
851ba692 5221 kvm_x86_ops->run(vcpu);
b6c7a5dc 5222
24f1e32c
FW		 5223 /*
5224 * If the guest has used debug registers, at least dr7
5225 * will be disabled while returning to the host.
5226 * If we don't have active breakpoints in the host, we don't
5227 * care about the messed up debug address registers. But if
5228 * we have some of them active, restore the old state.
5229 */
59d8eb53 5230 if (hw_breakpoint_active())
24f1e32c 5231 hw_breakpoint_restore();
42dbaa5a 5232
1d5f066e
ZA		 5233 kvm_get_msr(vcpu, MSR_IA32_TSC, &vcpu->arch.last_guest_tsc);
5234
d94e1dc9
AK		 5235 atomic_set(&vcpu->guest_mode, 0);
5236 smp_wmb();
b6c7a5dc
HB		 5237 local_irq_enable();
5238
5239 ++vcpu->stat.exits;
5240
5241 /*
5242 * We must have an instruction between local_irq_enable() and
5243 * kvm_guest_exit(), so the timer interrupt isn't delayed by
5244 * the interrupt shadow. The stat.exits increment will do nicely.
5245 * But we need to prevent reordering, hence this barrier():
5246 */
5247 barrier();
5248
5249 kvm_guest_exit();
5250
5251 preempt_enable();
5252
f656ce01 5253 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 5254
b6c7a5dc
HB		 5255 /*
5256 * Profile KVM exit RIPs:
5257 */
5258 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 5259 unsigned long rip = kvm_rip_read(vcpu);
5260 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 5261 }
5262
298101da 5263
b93463aa
AK		 5264 kvm_lapic_sync_from_vapic(vcpu);
5265
851ba692 5266 r = kvm_x86_ops->handle_exit(vcpu);
d7690175
MT		 5267out:
5268 return r;
5269}
b6c7a5dc 5270
09cec754 5271
851ba692 5272static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 5273{
5274 int r;
f656ce01 5275 struct kvm *kvm = vcpu->kvm;
d7690175
MT		 5276
5277 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
1b10bf31
JK		 5278 pr_debug("vcpu %d received sipi with vector # %x\n",
5279 vcpu->vcpu_id, vcpu->arch.sipi_vector);
d7690175 5280 kvm_lapic_reset(vcpu);
5f179287 5281 r = kvm_arch_vcpu_reset(vcpu);
d7690175
MT		 5282 if (r)
5283 return r;
5284 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 5285 }
5286
f656ce01 5287 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175
MT		 5288 vapic_enter(vcpu);
5289
5290 r = 1;
5291 while (r > 0) {
af585b92
GN		 5292 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
5293 !vcpu->arch.apf.halted)
851ba692 5294 r = vcpu_enter_guest(vcpu);
d7690175 5295 else {
f656ce01 5296 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 5297 kvm_vcpu_block(vcpu);
f656ce01 5298 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
a8eeb04a 5299 if (kvm_check_request(KVM_REQ_UNHALT, vcpu))
09cec754
GN		 5300 {
5301 switch(vcpu->arch.mp_state) {
5302 case KVM_MP_STATE_HALTED:
d7690175 5303 vcpu->arch.mp_state =
09cec754
GN		 5304 KVM_MP_STATE_RUNNABLE;
5305 case KVM_MP_STATE_RUNNABLE:
af585b92 5306 vcpu->arch.apf.halted = false;
09cec754
GN		 5307 break;
5308 case KVM_MP_STATE_SIPI_RECEIVED:
5309 default:
5310 r = -EINTR;
5311 break;
5312 }
5313 }
d7690175
MT		 5314 }
5315
09cec754
GN		 5316 if (r <= 0)
5317 break;
5318
5319 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
5320 if (kvm_cpu_has_pending_timer(vcpu))
5321 kvm_inject_pending_timer_irqs(vcpu);
5322
851ba692 5323 if (dm_request_for_irq_injection(vcpu)) {
09cec754 5324 r = -EINTR;
851ba692 5325 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5326 ++vcpu->stat.request_irq_exits;
5327 }
af585b92
GN		 5328
5329 kvm_check_async_pf_completion(vcpu);
5330
09cec754
GN		 5331 if (signal_pending(current)) {
5332 r = -EINTR;
851ba692 5333 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5334 ++vcpu->stat.signal_exits;
5335 }
5336 if (need_resched()) {
f656ce01 5337 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
09cec754 5338 kvm_resched(vcpu);
f656ce01 5339 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 5340 }
b6c7a5dc
HB		 5341 }
5342
f656ce01 5343 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc 5344
b93463aa
AK		 5345 vapic_exit(vcpu);
5346
b6c7a5dc
HB		 5347 return r;
5348}
5349
5350int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
5351{
5352 int r;
5353 sigset_t sigsaved;
5354
ac9f6dc0
AK		 5355 if (vcpu->sigset_active)
5356 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
5357
a4535290 5358 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 5359 kvm_vcpu_block(vcpu);
d7690175 5360 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 5361 r = -EAGAIN;
5362 goto out;
b6c7a5dc
HB		 5363 }
5364
b6c7a5dc
HB		 5365 /* re-sync apic's tpr */
5366 if (!irqchip_in_kernel(vcpu->kvm))
2d3ad1f4 5367 kvm_set_cr8(vcpu, kvm_run->cr8);
b6c7a5dc 5368
d2ddd1c4 5369 if (vcpu->arch.pio.count || vcpu->mmio_needed) {
92bf9748
GN		 5370 if (vcpu->mmio_needed) {
5371 memcpy(vcpu->mmio_data, kvm_run->mmio.data, 8);
5372 vcpu->mmio_read_completed = 1;
5373 vcpu->mmio_needed = 0;
b6c7a5dc 5374 }
f656ce01 5375 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5cd21917 5376 r = emulate_instruction(vcpu, 0, 0, EMULTYPE_NO_DECODE);
f656ce01 5377 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6d77dbfc 5378 if (r != EMULATE_DONE) {
b6c7a5dc
HB		 5379 r = 0;
5380 goto out;
5381 }
5382 }
5fdbf976
MT		 5383 if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL)
5384 kvm_register_write(vcpu, VCPU_REGS_RAX,
5385 kvm_run->hypercall.ret);
b6c7a5dc 5386
851ba692 5387 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 5388
5389out:
f1d86e46 5390 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 5391 if (vcpu->sigset_active)
5392 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
5393
b6c7a5dc
HB		 5394 return r;
5395}
5396
5397int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5398{
5fdbf976
MT		 5399 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
5400 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
5401 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
5402 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
5403 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
5404 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
5405 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
5406 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 5407#ifdef CONFIG_X86_64
5fdbf976
MT		 5408 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
5409 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
5410 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
5411 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
5412 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
5413 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
5414 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
5415 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 5416#endif
5417
5fdbf976 5418 regs->rip = kvm_rip_read(vcpu);
91586a3b 5419 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 5420
b6c7a5dc
HB		 5421 return 0;
5422}
5423
5424int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5425{
5fdbf976
MT		 5426 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
5427 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
5428 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
5429 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
5430 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
5431 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
5432 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
5433 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 5434#ifdef CONFIG_X86_64
5fdbf976
MT		 5435 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
5436 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
5437 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
5438 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
5439 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
5440 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
5441 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
5442 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 5443#endif
5444
5fdbf976 5445 kvm_rip_write(vcpu, regs->rip);
91586a3b 5446 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 5447
b4f14abd
JK		 5448 vcpu->arch.exception.pending = false;
5449
3842d135
AK		 5450 kvm_make_request(KVM_REQ_EVENT, vcpu);
5451
b6c7a5dc
HB		 5452 return 0;
5453}
5454
b6c7a5dc
HB		 5455void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
5456{
5457 struct kvm_segment cs;
5458
3e6e0aab 5459 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 5460 *db = cs.db;
5461 *l = cs.l;
5462}
5463EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
5464
5465int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
5466 struct kvm_sregs *sregs)
5467{
89a27f4d 5468 struct desc_ptr dt;
b6c7a5dc 5469
3e6e0aab
GT		 5470 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5471 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5472 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5473 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5474 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5475 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 5476
3e6e0aab
GT		 5477 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5478 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 5479
5480 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 5481 sregs->idt.limit = dt.size;
5482 sregs->idt.base = dt.address;
b6c7a5dc 5483 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 5484 sregs->gdt.limit = dt.size;
5485 sregs->gdt.base = dt.address;
b6c7a5dc 5486
4d4ec087 5487 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c
ZX		 5488 sregs->cr2 = vcpu->arch.cr2;
5489 sregs->cr3 = vcpu->arch.cr3;
fc78f519 5490 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 5491 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 5492 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 5493 sregs->apic_base = kvm_get_apic_base(vcpu);
5494
923c61bb 5495 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 5496
36752c9b 5497 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 5498 set_bit(vcpu->arch.interrupt.nr,
5499 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 5500
b6c7a5dc
HB		 5501 return 0;
5502}
5503
62d9f0db
MT		 5504int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
5505 struct kvm_mp_state *mp_state)
5506{
62d9f0db 5507 mp_state->mp_state = vcpu->arch.mp_state;
62d9f0db
MT		 5508 return 0;
5509}
5510
5511int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
5512 struct kvm_mp_state *mp_state)
5513{
62d9f0db 5514 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 5515 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 5516 return 0;
5517}
5518
e269fb21
JK		 5519int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason,
5520 bool has_error_code, u32 error_code)
b6c7a5dc 5521{
4d2179e1 5522 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
8ec4722d 5523 int ret;
e01c2426 5524
8ec4722d 5525 init_emulate_ctxt(vcpu);
c697518a 5526
9aabc88f 5527 ret = emulator_task_switch(&vcpu->arch.emulate_ctxt,
e269fb21
JK		 5528 tss_selector, reason, has_error_code,
5529 error_code);
c697518a 5530
c697518a 5531 if (ret)
19d04437 5532 return EMULATE_FAIL;
37817f29 5533
4d2179e1 5534 memcpy(vcpu->arch.regs, c->regs, sizeof c->regs);
95c55886 5535 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.eip);
19d04437 5536 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
3842d135 5537 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 5538 return EMULATE_DONE;
37817f29
IE		 5539}
5540EXPORT_SYMBOL_GPL(kvm_task_switch);
5541
b6c7a5dc
HB		 5542int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
5543 struct kvm_sregs *sregs)
5544{
5545 int mmu_reset_needed = 0;
923c61bb 5546 int pending_vec, max_bits;
89a27f4d 5547 struct desc_ptr dt;
b6c7a5dc 5548
89a27f4d
GN		 5549 dt.size = sregs->idt.limit;
5550 dt.address = sregs->idt.base;
b6c7a5dc 5551 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 5552 dt.size = sregs->gdt.limit;
5553 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 5554 kvm_x86_ops->set_gdt(vcpu, &dt);
5555
ad312c7c
ZX		 5556 vcpu->arch.cr2 = sregs->cr2;
5557 mmu_reset_needed |= vcpu->arch.cr3 != sregs->cr3;
dc7e795e 5558 vcpu->arch.cr3 = sregs->cr3;
b6c7a5dc 5559
2d3ad1f4 5560 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 5561
f6801dff 5562 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 5563 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 5564 kvm_set_apic_base(vcpu, sregs->apic_base);
5565
4d4ec087 5566 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 5567 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 5568 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 5569
fc78f519 5570 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 5571 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3ea3aa8c
SY		 5572 if (sregs->cr4 & X86_CR4_OSXSAVE)
5573 update_cpuid(vcpu);
7c93be44 5574 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
ff03a073 5575 load_pdptrs(vcpu, vcpu->arch.walk_mmu, vcpu->arch.cr3);
7c93be44
MT		 5576 mmu_reset_needed = 1;
5577 }
b6c7a5dc
HB		 5578
5579 if (mmu_reset_needed)
5580 kvm_mmu_reset_context(vcpu);
5581
923c61bb
GN		 5582 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
5583 pending_vec = find_first_bit(
5584 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
5585 if (pending_vec < max_bits) {
66fd3f7f 5586 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb
GN		 5587 pr_debug("Set back pending irq %d\n", pending_vec);
5588 if (irqchip_in_kernel(vcpu->kvm))
5589 kvm_pic_clear_isr_ack(vcpu->kvm);
b6c7a5dc
HB		 5590 }
5591
3e6e0aab
GT		 5592 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5593 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5594 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5595 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5596 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5597 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 5598
3e6e0aab
GT		 5599 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5600 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 5601
5f0269f5
ME		 5602 update_cr8_intercept(vcpu);
5603
9c3e4aab 5604 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 5605 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 5606 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 5607 !is_protmode(vcpu))
9c3e4aab
MT		 5608 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
5609
3842d135
AK		 5610 kvm_make_request(KVM_REQ_EVENT, vcpu);
5611
b6c7a5dc
HB		 5612 return 0;
5613}
5614
d0bfb940
JK		 5615int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
5616 struct kvm_guest_debug *dbg)
b6c7a5dc 5617{
355be0b9 5618 unsigned long rflags;
ae675ef0 5619 int i, r;
b6c7a5dc 5620
4f926bf2
JK		 5621 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
5622 r = -EBUSY;
5623 if (vcpu->arch.exception.pending)
2122ff5e 5624 goto out;
4f926bf2
JK		 5625 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
5626 kvm_queue_exception(vcpu, DB_VECTOR);
5627 else
5628 kvm_queue_exception(vcpu, BP_VECTOR);
5629 }
5630
91586a3b
JK		 5631 /*
5632 * Read rflags as long as potentially injected trace flags are still
5633 * filtered out.
5634 */
5635 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 5636
5637 vcpu->guest_debug = dbg->control;
5638 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
5639 vcpu->guest_debug = 0;
5640
5641 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 5642 for (i = 0; i < KVM_NR_DB_REGS; ++i)
5643 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
5644 vcpu->arch.switch_db_regs =
5645 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
5646 } else {
5647 for (i = 0; i < KVM_NR_DB_REGS; i++)
5648 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
5649 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
5650 }
5651
f92653ee
JK		 5652 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
5653 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
5654 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 5655
91586a3b
JK		 5656 /*
5657 * Trigger an rflags update that will inject or remove the trace
5658 * flags.
5659 */
5660 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 5661
355be0b9 5662 kvm_x86_ops->set_guest_debug(vcpu, dbg);
b6c7a5dc 5663
4f926bf2 5664 r = 0;
d0bfb940 5665
2122ff5e 5666out:
b6c7a5dc
HB		 5667
5668 return r;
5669}
5670
8b006791
ZX		 5671/*
5672 * Translate a guest virtual address to a guest physical address.
5673 */
5674int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
5675 struct kvm_translation *tr)
5676{
5677 unsigned long vaddr = tr->linear_address;
5678 gpa_t gpa;
f656ce01 5679 int idx;
8b006791 5680
f656ce01 5681 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 5682 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 5683 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 5684 tr->physical_address = gpa;
5685 tr->valid = gpa != UNMAPPED_GVA;
5686 tr->writeable = 1;
5687 tr->usermode = 0;
8b006791
ZX		 5688
5689 return 0;
5690}
5691
d0752060
HB		 5692int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5693{
98918833
SY		 5694 struct i387_fxsave_struct *fxsave =
5695 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 5696
d0752060
HB		 5697 memcpy(fpu->fpr, fxsave->st_space, 128);
5698 fpu->fcw = fxsave->cwd;
5699 fpu->fsw = fxsave->swd;
5700 fpu->ftwx = fxsave->twd;
5701 fpu->last_opcode = fxsave->fop;
5702 fpu->last_ip = fxsave->rip;
5703 fpu->last_dp = fxsave->rdp;
5704 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
5705
d0752060
HB		 5706 return 0;
5707}
5708
5709int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5710{
98918833
SY		 5711 struct i387_fxsave_struct *fxsave =
5712 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 5713
d0752060
HB		 5714 memcpy(fxsave->st_space, fpu->fpr, 128);
5715 fxsave->cwd = fpu->fcw;
5716 fxsave->swd = fpu->fsw;
5717 fxsave->twd = fpu->ftwx;
5718 fxsave->fop = fpu->last_opcode;
5719 fxsave->rip = fpu->last_ip;
5720 fxsave->rdp = fpu->last_dp;
5721 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
5722
d0752060
HB		 5723 return 0;
5724}
5725
10ab25cd 5726int fx_init(struct kvm_vcpu *vcpu)
d0752060 5727{
10ab25cd
JK		 5728 int err;
5729
5730 err = fpu_alloc(&vcpu->arch.guest_fpu);
5731 if (err)
5732 return err;
5733
98918833 5734 fpu_finit(&vcpu->arch.guest_fpu);
d0752060 5735
2acf923e
DC		 5736 /*
5737 * Ensure guest xcr0 is valid for loading
5738 */
5739 vcpu->arch.xcr0 = XSTATE_FP;
5740
ad312c7c 5741 vcpu->arch.cr0 |= X86_CR0_ET;
10ab25cd
JK		 5742
5743 return 0;
d0752060
HB		 5744}
5745EXPORT_SYMBOL_GPL(fx_init);
5746
98918833
SY		 5747static void fx_free(struct kvm_vcpu *vcpu)
5748{
5749 fpu_free(&vcpu->arch.guest_fpu);
5750}
5751
d0752060
HB		 5752void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
5753{
2608d7a1 5754 if (vcpu->guest_fpu_loaded)
d0752060
HB		 5755 return;
5756
2acf923e
DC		 5757 /*
5758 * Restore all possible states in the guest,
5759 * and assume host would use all available bits.
5760 * Guest xcr0 would be loaded later.
5761 */
5762 kvm_put_guest_xcr0(vcpu);
d0752060 5763 vcpu->guest_fpu_loaded = 1;
7cf30855 5764 unlazy_fpu(current);
98918833 5765 fpu_restore_checking(&vcpu->arch.guest_fpu);
0c04851c 5766 trace_kvm_fpu(1);
d0752060 5767}
d0752060
HB		 5768
5769void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
5770{
2acf923e
DC		 5771 kvm_put_guest_xcr0(vcpu);
5772
d0752060
HB		 5773 if (!vcpu->guest_fpu_loaded)
5774 return;
5775
5776 vcpu->guest_fpu_loaded = 0;
98918833 5777 fpu_save_init(&vcpu->arch.guest_fpu);
f096ed85 5778 ++vcpu->stat.fpu_reload;
a8eeb04a 5779 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
0c04851c 5780 trace_kvm_fpu(0);
d0752060 5781}
e9b11c17
ZX		 5782
5783void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
5784{
7f1ea208
JR		 5785 if (vcpu->arch.time_page) {
5786 kvm_release_page_dirty(vcpu->arch.time_page);
5787 vcpu->arch.time_page = NULL;
5788 }
5789
f5f48ee1 5790 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
98918833 5791 fx_free(vcpu);
e9b11c17
ZX		 5792 kvm_x86_ops->vcpu_free(vcpu);
5793}
5794
5795struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
5796 unsigned int id)
5797{
6755bae8
ZA		 5798 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
5799 printk_once(KERN_WARNING
5800 "kvm: SMP vm created on host with unstable TSC; "
5801 "guest TSC will not be reliable\n");
26e5215f
AK		 5802 return kvm_x86_ops->vcpu_create(kvm, id);
5803}
e9b11c17 5804
26e5215f
AK		 5805int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
5806{
5807 int r;
e9b11c17 5808
0bed3b56 5809 vcpu->arch.mtrr_state.have_fixed = 1;
e9b11c17
ZX		 5810 vcpu_load(vcpu);
5811 r = kvm_arch_vcpu_reset(vcpu);
5812 if (r == 0)
5813 r = kvm_mmu_setup(vcpu);
5814 vcpu_put(vcpu);
5815 if (r < 0)
5816 goto free_vcpu;
5817
26e5215f 5818 return 0;
e9b11c17
ZX		 5819free_vcpu:
5820 kvm_x86_ops->vcpu_free(vcpu);
26e5215f 5821 return r;
e9b11c17
ZX		 5822}
5823
d40ccc62 5824void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 5825{
344d9588
GN		 5826 vcpu->arch.apf.msr_val = 0;
5827
e9b11c17
ZX		 5828 vcpu_load(vcpu);
5829 kvm_mmu_unload(vcpu);
5830 vcpu_put(vcpu);
5831
98918833 5832 fx_free(vcpu);
e9b11c17
ZX		 5833 kvm_x86_ops->vcpu_free(vcpu);
5834}
5835
5836int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
5837{
448fa4a9
JK		 5838 vcpu->arch.nmi_pending = false;
5839 vcpu->arch.nmi_injected = false;
5840
42dbaa5a
JK		 5841 vcpu->arch.switch_db_regs = 0;
5842 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
5843 vcpu->arch.dr6 = DR6_FIXED_1;
5844 vcpu->arch.dr7 = DR7_FIXED_1;
5845
3842d135 5846 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 5847 vcpu->arch.apf.msr_val = 0;
3842d135 5848
af585b92
GN		 5849 kvm_clear_async_pf_completion_queue(vcpu);
5850 kvm_async_pf_hash_reset(vcpu);
5851 vcpu->arch.apf.halted = false;
5852
e9b11c17
ZX		 5853 return kvm_x86_ops->vcpu_reset(vcpu);
5854}
5855
10474ae8 5856int kvm_arch_hardware_enable(void *garbage)
e9b11c17 5857{
ca84d1a2
ZA		 5858 struct kvm *kvm;
5859 struct kvm_vcpu *vcpu;
5860 int i;
18863bdd
AK		 5861
5862 kvm_shared_msr_cpu_online();
ca84d1a2
ZA		 5863 list_for_each_entry(kvm, &vm_list, vm_list)
5864 kvm_for_each_vcpu(i, vcpu, kvm)
5865 if (vcpu->cpu == smp_processor_id())
c285545f 5866 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
10474ae8 5867 return kvm_x86_ops->hardware_enable(garbage);
e9b11c17
ZX		 5868}
5869
5870void kvm_arch_hardware_disable(void *garbage)
5871{
5872 kvm_x86_ops->hardware_disable(garbage);
3548bab5 5873 drop_user_return_notifiers(garbage);
e9b11c17
ZX		 5874}
5875
5876int kvm_arch_hardware_setup(void)
5877{
5878 return kvm_x86_ops->hardware_setup();
5879}
5880
5881void kvm_arch_hardware_unsetup(void)
5882{
5883 kvm_x86_ops->hardware_unsetup();
5884}
5885
5886void kvm_arch_check_processor_compat(void *rtn)
5887{
5888 kvm_x86_ops->check_processor_compatibility(rtn);
5889}
5890
5891int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
5892{
5893 struct page *page;
5894 struct kvm *kvm;
5895 int r;
5896
5897 BUG_ON(vcpu->kvm == NULL);
5898 kvm = vcpu->kvm;
5899
9aabc88f 5900 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
14dfe855 5901 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
ad312c7c 5902 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
c30a358d 5903 vcpu->arch.mmu.translate_gpa = translate_gpa;
02f59dc9 5904 vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa;
c5af89b6 5905 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 5906 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 5907 else
a4535290 5908 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 5909
5910 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
5911 if (!page) {
5912 r = -ENOMEM;
5913 goto fail;
5914 }
ad312c7c 5915 vcpu->arch.pio_data = page_address(page);
e9b11c17 5916
c285545f
ZA		 5917 if (!kvm->arch.virtual_tsc_khz)
5918 kvm_arch_set_tsc_khz(kvm, max_tsc_khz);
5919
e9b11c17
ZX		 5920 r = kvm_mmu_create(vcpu);
5921 if (r < 0)
5922 goto fail_free_pio_data;
5923
5924 if (irqchip_in_kernel(kvm)) {
5925 r = kvm_create_lapic(vcpu);
5926 if (r < 0)
5927 goto fail_mmu_destroy;
5928 }
5929
890ca9ae
HY		 5930 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
5931 GFP_KERNEL);
5932 if (!vcpu->arch.mce_banks) {
5933 r = -ENOMEM;
443c39bc 5934 goto fail_free_lapic;
890ca9ae
HY		 5935 }
5936 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
5937
f5f48ee1
SY		 5938 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL))
5939 goto fail_free_mce_banks;
5940
af585b92
GN		 5941 kvm_async_pf_hash_reset(vcpu);
5942
e9b11c17 5943 return 0;
f5f48ee1
SY		 5944fail_free_mce_banks:
5945 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 5946fail_free_lapic:
5947 kvm_free_lapic(vcpu);
e9b11c17
ZX		 5948fail_mmu_destroy:
5949 kvm_mmu_destroy(vcpu);
5950fail_free_pio_data:
ad312c7c 5951 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 5952fail:
5953 return r;
5954}
5955
5956void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
5957{
f656ce01
MT		 5958 int idx;
5959
36cb93fd 5960 kfree(vcpu->arch.mce_banks);
e9b11c17 5961 kvm_free_lapic(vcpu);
f656ce01 5962 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 5963 kvm_mmu_destroy(vcpu);
f656ce01 5964 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 5965 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17 5966}
d19a9cd2
ZX		 5967
5968struct kvm *kvm_arch_create_vm(void)
5969{
5970 struct kvm *kvm = kzalloc(sizeof(struct kvm), GFP_KERNEL);
5971
5972 if (!kvm)
5973 return ERR_PTR(-ENOMEM);
5974
f05e70ac 5975 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4d5c5d0f 5976 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2 5977
5550af4d
SY		 5978 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
5979 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
5980
99e3e30a 5981 spin_lock_init(&kvm->arch.tsc_write_lock);
53f658b3 5982
d19a9cd2
ZX		 5983 return kvm;
5984}
5985
5986static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
5987{
5988 vcpu_load(vcpu);
5989 kvm_mmu_unload(vcpu);
5990 vcpu_put(vcpu);
5991}
5992
5993static void kvm_free_vcpus(struct kvm *kvm)
5994{
5995 unsigned int i;
988a2cae 5996 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 5997
5998 /*
5999 * Unpin any mmu pages first.
6000 */
af585b92
GN		 6001 kvm_for_each_vcpu(i, vcpu, kvm) {
6002 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 6003 kvm_unload_vcpu_mmu(vcpu);
af585b92 6004 }
988a2cae
GN		 6005 kvm_for_each_vcpu(i, vcpu, kvm)
6006 kvm_arch_vcpu_free(vcpu);
6007
6008 mutex_lock(&kvm->lock);
6009 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
6010 kvm->vcpus[i] = NULL;
d19a9cd2 6011
988a2cae
GN		 6012 atomic_set(&kvm->online_vcpus, 0);
6013 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 6014}
6015
ad8ba2cd
SY		 6016void kvm_arch_sync_events(struct kvm *kvm)
6017{
ba4cef31 6018 kvm_free_all_assigned_devices(kvm);
aea924f6 6019 kvm_free_pit(kvm);
ad8ba2cd
SY		 6020}
6021
d19a9cd2
ZX		 6022void kvm_arch_destroy_vm(struct kvm *kvm)
6023{
6eb55818 6024 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 6025 kfree(kvm->arch.vpic);
6026 kfree(kvm->arch.vioapic);
d19a9cd2
ZX		 6027 kvm_free_vcpus(kvm);
6028 kvm_free_physmem(kvm);
3d45830c
AK		 6029 if (kvm->arch.apic_access_page)
6030 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 6031 if (kvm->arch.ept_identity_pagetable)
6032 put_page(kvm->arch.ept_identity_pagetable);
64749204 6033 cleanup_srcu_struct(&kvm->srcu);
d19a9cd2
ZX		 6034 kfree(kvm);
6035}
0de10343 6036
f7784b8e
MT		 6037int kvm_arch_prepare_memory_region(struct kvm *kvm,
6038 struct kvm_memory_slot *memslot,
0de10343 6039 struct kvm_memory_slot old,
f7784b8e 6040 struct kvm_userspace_memory_region *mem,
0de10343
ZX		 6041 int user_alloc)
6042{
f7784b8e 6043 int npages = memslot->npages;
7ac77099
AK		 6044 int map_flags = MAP_PRIVATE | MAP_ANONYMOUS;
6045
6046 /* Prevent internal slot pages from being moved by fork()/COW. */
6047 if (memslot->id >= KVM_MEMORY_SLOTS)
6048 map_flags = MAP_SHARED | MAP_ANONYMOUS;
0de10343
ZX		 6049
6050 /*To keep backward compatibility with older userspace,
6051 *x86 needs to hanlde !user_alloc case.
6052 */
6053 if (!user_alloc) {
6054 if (npages && !old.rmap) {
604b38ac
AA		 6055 unsigned long userspace_addr;
6056
72dc67a6 6057 down_write(&current->mm->mmap_sem);
604b38ac
AA		 6058 userspace_addr = do_mmap(NULL, 0,
6059 npages * PAGE_SIZE,
6060 PROT_READ | PROT_WRITE,
7ac77099 6061 map_flags,
604b38ac 6062 0);
72dc67a6 6063 up_write(&current->mm->mmap_sem);
0de10343 6064
604b38ac
AA		 6065 if (IS_ERR((void *)userspace_addr))
6066 return PTR_ERR((void *)userspace_addr);
6067
604b38ac 6068 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 6069 }
6070 }
6071
f7784b8e
MT		 6072
6073 return 0;
6074}
6075
6076void kvm_arch_commit_memory_region(struct kvm *kvm,
6077 struct kvm_userspace_memory_region *mem,
6078 struct kvm_memory_slot old,
6079 int user_alloc)
6080{
6081
6082 int npages = mem->memory_size >> PAGE_SHIFT;
6083
6084 if (!user_alloc && !old.user_alloc && old.rmap && !npages) {
6085 int ret;
6086
6087 down_write(&current->mm->mmap_sem);
6088 ret = do_munmap(current->mm, old.userspace_addr,
6089 old.npages * PAGE_SIZE);
6090 up_write(&current->mm->mmap_sem);
6091 if (ret < 0)
6092 printk(KERN_WARNING
6093 "kvm_vm_ioctl_set_memory_region: "
6094 "failed to munmap memory\n");
6095 }
6096
7c8a83b7 6097 spin_lock(&kvm->mmu_lock);
f05e70ac 6098 if (!kvm->arch.n_requested_mmu_pages) {
0de10343
ZX		 6099 unsigned int nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
6100 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
6101 }
6102
6103 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
7c8a83b7 6104 spin_unlock(&kvm->mmu_lock);
0de10343 6105}
1d737c8a 6106
34d4cb8f
MT		 6107void kvm_arch_flush_shadow(struct kvm *kvm)
6108{
6109 kvm_mmu_zap_all(kvm);
8986ecc0 6110 kvm_reload_remote_mmus(kvm);
34d4cb8f
MT		 6111}
6112
1d737c8a
ZX		 6113int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
6114{
af585b92
GN		 6115 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6116 !vcpu->arch.apf.halted)
6117 || !list_empty_careful(&vcpu->async_pf.done)
a1b37100
GN		 6118 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
6119 || vcpu->arch.nmi_pending ||
6120 (kvm_arch_interrupt_allowed(vcpu) &&
6121 kvm_cpu_has_interrupt(vcpu));
1d737c8a 6122}
5736199a 6123
5736199a
ZX		 6124void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
6125{
32f88400
MT		 6126 int me;
6127 int cpu = vcpu->cpu;
5736199a
ZX		 6128
6129 if (waitqueue_active(&vcpu->wq)) {
6130 wake_up_interruptible(&vcpu->wq);
6131 ++vcpu->stat.halt_wakeup;
6132 }
32f88400
MT		 6133
6134 me = get_cpu();
6135 if (cpu != me && (unsigned)cpu < nr_cpu_ids && cpu_online(cpu))
d94e1dc9 6136 if (atomic_xchg(&vcpu->guest_mode, 0))
32f88400 6137 smp_send_reschedule(cpu);
e9571ed5 6138 put_cpu();
5736199a 6139}
78646121
GN		 6140
6141int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
6142{
6143 return kvm_x86_ops->interrupt_allowed(vcpu);
6144}
229456fc 6145
f92653ee
JK		 6146bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
6147{
6148 unsigned long current_rip = kvm_rip_read(vcpu) +
6149 get_segment_base(vcpu, VCPU_SREG_CS);
6150
6151 return current_rip == linear_rip;
6152}
6153EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
6154
94fe45da
JK		 6155unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
6156{
6157 unsigned long rflags;
6158
6159 rflags = kvm_x86_ops->get_rflags(vcpu);
6160 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 6161 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 6162 return rflags;
6163}
6164EXPORT_SYMBOL_GPL(kvm_get_rflags);
6165
6166void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
6167{
6168 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 6169 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 6170 rflags |= X86_EFLAGS_TF;
94fe45da 6171 kvm_x86_ops->set_rflags(vcpu, rflags);
3842d135 6172 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 6173}
6174EXPORT_SYMBOL_GPL(kvm_set_rflags);
6175
56028d08
GN		 6176void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
6177{
6178 int r;
6179
6180 if (!vcpu->arch.mmu.direct_map || is_error_page(work->page))
6181 return;
6182
6183 r = kvm_mmu_reload(vcpu);
6184 if (unlikely(r))
6185 return;
6186
6187 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
6188}
6189
af585b92
GN		 6190static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
6191{
6192 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
6193}
6194
6195static inline u32 kvm_async_pf_next_probe(u32 key)
6196{
6197 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
6198}
6199
6200static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6201{
6202 u32 key = kvm_async_pf_hash_fn(gfn);
6203
6204 while (vcpu->arch.apf.gfns[key] != ~0)
6205 key = kvm_async_pf_next_probe(key);
6206
6207 vcpu->arch.apf.gfns[key] = gfn;
6208}
6209
6210static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
6211{
6212 int i;
6213 u32 key = kvm_async_pf_hash_fn(gfn);
6214
6215 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
6216 (vcpu->arch.apf.gfns[key] != gfn ||
6217 vcpu->arch.apf.gfns[key] == ~0); i++)
6218 key = kvm_async_pf_next_probe(key);
6219
6220 return key;
6221}
6222
6223bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6224{
6225 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
6226}
6227
6228static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6229{
6230 u32 i, j, k;
6231
6232 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
6233 while (true) {
6234 vcpu->arch.apf.gfns[i] = ~0;
6235 do {
6236 j = kvm_async_pf_next_probe(j);
6237 if (vcpu->arch.apf.gfns[j] == ~0)
6238 return;
6239 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
6240 /*
6241 * k lies cyclically in ]i,j]
6242 * | i.k.j |
6243 * |....j i.k.| or |.k..j i...|
6244 */
6245 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
6246 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
6247 i = j;
6248 }
6249}
6250
7c90705b
GN		 6251static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
6252{
6253
6254 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
6255 sizeof(val));
6256}
6257
af585b92
GN		 6258void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
6259 struct kvm_async_pf *work)
6260{
7c90705b 6261 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 6262 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 6263
6264 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 6265 (vcpu->arch.apf.send_user_only &&
6266 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 6267 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
6268 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6269 vcpu->arch.fault.error_code = 0;
6270 vcpu->arch.fault.address = work->arch.token;
6271 kvm_inject_page_fault(vcpu);
6272 }
af585b92
GN		 6273}
6274
6275void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
6276 struct kvm_async_pf *work)
6277{
7c90705b
GN		 6278 trace_kvm_async_pf_ready(work->arch.token, work->gva);
6279 if (is_error_page(work->page))
6280 work->arch.token = ~0; /* broadcast wakeup */
6281 else
6282 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
6283
6284 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
6285 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6286 vcpu->arch.fault.error_code = 0;
6287 vcpu->arch.fault.address = work->arch.token;
6288 kvm_inject_page_fault(vcpu);
6289 }
6290}
6291
6292bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
6293{
6294 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
6295 return true;
6296 else
6297 return !kvm_event_needs_reinjection(vcpu) &&
6298 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 6299}
6300
229456fc
MT		 6301EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
6302EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
6303EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
6304EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
6305EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 6306EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 6307EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 6308EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 6309EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 6310EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 6311EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 6312EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
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