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KVM: Fix mov cr4 #GP at wrong instruction
[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
221d059d 9 * Copyright 2010 Red Hat, Inc. and/or its affilates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
313a3dc7 29
18068523 30#include <linux/clocksource.h>
4d5c5d0f 31#include <linux/interrupt.h>
313a3dc7
CO		 32#include <linux/kvm.h>
33#include <linux/fs.h>
34#include <linux/vmalloc.h>
5fb76f9b 35#include <linux/module.h>
0de10343 36#include <linux/mman.h>
2bacc55c 37#include <linux/highmem.h>
19de40a8 38#include <linux/iommu.h>
62c476c7 39#include <linux/intel-iommu.h>
c8076604 40#include <linux/cpufreq.h>
18863bdd 41#include <linux/user-return-notifier.h>
a983fb23 42#include <linux/srcu.h>
5a0e3ad6 43#include <linux/slab.h>
ff9d07a0 44#include <linux/perf_event.h>
7bee342a 45#include <linux/uaccess.h>
aec51dc4 46#include <trace/events/kvm.h>
2ed152af 47
229456fc
MT		 48#define CREATE_TRACE_POINTS
49#include "trace.h"
043405e1 50
24f1e32c 51#include <asm/debugreg.h>
d825ed0a 52#include <asm/msr.h>
a5f61300 53#include <asm/desc.h>
0bed3b56 54#include <asm/mtrr.h>
890ca9ae 55#include <asm/mce.h>
7cf30855 56#include <asm/i387.h>
98918833 57#include <asm/xcr.h>
043405e1 58
313a3dc7 59#define MAX_IO_MSRS 256
a03490ed
CO		 60#define CR0_RESERVED_BITS \
61 (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \
62 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \
63 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG))
64#define CR4_RESERVED_BITS \
65 (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\
66 | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \
67 | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR \
2acf923e 68 | X86_CR4_OSXSAVE \
a03490ed
CO		 69 | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE))
70
71#define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
890ca9ae
HY		 72
73#define KVM_MAX_MCE_BANKS 32
74#define KVM_MCE_CAP_SUPPORTED MCG_CTL_P
75
50a37eb4
JR		 76/* EFER defaults:
77 * - enable syscall per default because its emulated by KVM
78 * - enable LME and LMA per default on 64 bit KVM
79 */
80#ifdef CONFIG_X86_64
81static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffafeULL;
82#else
83static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffffeULL;
84#endif
313a3dc7 85
ba1389b7
AK		 86#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
87#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 88
cb142eb7 89static void update_cr8_intercept(struct kvm_vcpu *vcpu);
674eea0f
AK		 90static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
91 struct kvm_cpuid_entry2 __user *entries);
92
97896d04 93struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 94EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 95
ed85c068
AP		 96int ignore_msrs = 0;
97module_param_named(ignore_msrs, ignore_msrs, bool, S_IRUGO | S_IWUSR);
98
18863bdd
AK		 99#define KVM_NR_SHARED_MSRS 16
100
101struct kvm_shared_msrs_global {
102 int nr;
2bf78fa7 103 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 104};
105
106struct kvm_shared_msrs {
107 struct user_return_notifier urn;
108 bool registered;
2bf78fa7
SY		 109 struct kvm_shared_msr_values {
110 u64 host;
111 u64 curr;
112 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 113};
114
115static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
116static DEFINE_PER_CPU(struct kvm_shared_msrs, shared_msrs);
117
417bc304 118struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 119 { "pf_fixed", VCPU_STAT(pf_fixed) },
120 { "pf_guest", VCPU_STAT(pf_guest) },
121 { "tlb_flush", VCPU_STAT(tlb_flush) },
122 { "invlpg", VCPU_STAT(invlpg) },
123 { "exits", VCPU_STAT(exits) },
124 { "io_exits", VCPU_STAT(io_exits) },
125 { "mmio_exits", VCPU_STAT(mmio_exits) },
126 { "signal_exits", VCPU_STAT(signal_exits) },
127 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 128 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 129 { "halt_exits", VCPU_STAT(halt_exits) },
130 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 131 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 132 { "request_irq", VCPU_STAT(request_irq_exits) },
133 { "irq_exits", VCPU_STAT(irq_exits) },
134 { "host_state_reload", VCPU_STAT(host_state_reload) },
135 { "efer_reload", VCPU_STAT(efer_reload) },
136 { "fpu_reload", VCPU_STAT(fpu_reload) },
137 { "insn_emulation", VCPU_STAT(insn_emulation) },
138 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 139 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 140 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 141 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
142 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
143 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
144 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
145 { "mmu_flooded", VM_STAT(mmu_flooded) },
146 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 147 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 148 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 149 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 150 { "largepages", VM_STAT(lpages) },
417bc304
HB		 151 { NULL }
152};
153
2acf923e
DC		 154u64 __read_mostly host_xcr0;
155
156static inline u32 bit(int bitno)
157{
158 return 1 << (bitno & 31);
159}
160
18863bdd
AK		 161static void kvm_on_user_return(struct user_return_notifier *urn)
162{
163 unsigned slot;
18863bdd
AK		 164 struct kvm_shared_msrs *locals
165 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 166 struct kvm_shared_msr_values *values;
18863bdd
AK		 167
168 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 169 values = &locals->values[slot];
170 if (values->host != values->curr) {
171 wrmsrl(shared_msrs_global.msrs[slot], values->host);
172 values->curr = values->host;
18863bdd
AK		 173 }
174 }
175 locals->registered = false;
176 user_return_notifier_unregister(urn);
177}
178
2bf78fa7 179static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 180{
2bf78fa7 181 struct kvm_shared_msrs *smsr;
18863bdd
AK		 182 u64 value;
183
2bf78fa7
SY		 184 smsr = &__get_cpu_var(shared_msrs);
185 /* only read, and nobody should modify it at this time,
186 * so don't need lock */
187 if (slot >= shared_msrs_global.nr) {
188 printk(KERN_ERR "kvm: invalid MSR slot!");
189 return;
190 }
191 rdmsrl_safe(msr, &value);
192 smsr->values[slot].host = value;
193 smsr->values[slot].curr = value;
194}
195
196void kvm_define_shared_msr(unsigned slot, u32 msr)
197{
18863bdd
AK		 198 if (slot >= shared_msrs_global.nr)
199 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 200 shared_msrs_global.msrs[slot] = msr;
201 /* we need ensured the shared_msr_global have been updated */
202 smp_wmb();
18863bdd
AK		 203}
204EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
205
206static void kvm_shared_msr_cpu_online(void)
207{
208 unsigned i;
18863bdd
AK		 209
210 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 211 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 212}
213
d5696725 214void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd
AK		 215{
216 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
217
2bf78fa7 218 if (((value ^ smsr->values[slot].curr) & mask) == 0)
18863bdd 219 return;
2bf78fa7
SY		 220 smsr->values[slot].curr = value;
221 wrmsrl(shared_msrs_global.msrs[slot], value);
18863bdd
AK		 222 if (!smsr->registered) {
223 smsr->urn.on_user_return = kvm_on_user_return;
224 user_return_notifier_register(&smsr->urn);
225 smsr->registered = true;
226 }
227}
228EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
229
3548bab5
AK		 230static void drop_user_return_notifiers(void *ignore)
231{
232 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
233
234 if (smsr->registered)
235 kvm_on_user_return(&smsr->urn);
236}
237
6866b83e
CO		 238u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
239{
240 if (irqchip_in_kernel(vcpu->kvm))
ad312c7c 241 return vcpu->arch.apic_base;
6866b83e 242 else
ad312c7c 243 return vcpu->arch.apic_base;
6866b83e
CO		 244}
245EXPORT_SYMBOL_GPL(kvm_get_apic_base);
246
247void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
248{
249 /* TODO: reserve bits check */
250 if (irqchip_in_kernel(vcpu->kvm))
251 kvm_lapic_set_base(vcpu, data);
252 else
ad312c7c 253 vcpu->arch.apic_base = data;
6866b83e
CO		 254}
255EXPORT_SYMBOL_GPL(kvm_set_apic_base);
256
3fd28fce
ED		 257#define EXCPT_BENIGN 0
258#define EXCPT_CONTRIBUTORY 1
259#define EXCPT_PF 2
260
261static int exception_class(int vector)
262{
263 switch (vector) {
264 case PF_VECTOR:
265 return EXCPT_PF;
266 case DE_VECTOR:
267 case TS_VECTOR:
268 case NP_VECTOR:
269 case SS_VECTOR:
270 case GP_VECTOR:
271 return EXCPT_CONTRIBUTORY;
272 default:
273 break;
274 }
275 return EXCPT_BENIGN;
276}
277
278static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 279 unsigned nr, bool has_error, u32 error_code,
280 bool reinject)
3fd28fce
ED		 281{
282 u32 prev_nr;
283 int class1, class2;
284
285 if (!vcpu->arch.exception.pending) {
286 queue:
287 vcpu->arch.exception.pending = true;
288 vcpu->arch.exception.has_error_code = has_error;
289 vcpu->arch.exception.nr = nr;
290 vcpu->arch.exception.error_code = error_code;
3f0fd292 291 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 292 return;
293 }
294
295 /* to check exception */
296 prev_nr = vcpu->arch.exception.nr;
297 if (prev_nr == DF_VECTOR) {
298 /* triple fault -> shutdown */
299 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
300 return;
301 }
302 class1 = exception_class(prev_nr);
303 class2 = exception_class(nr);
304 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
305 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
306 /* generate double fault per SDM Table 5-5 */
307 vcpu->arch.exception.pending = true;
308 vcpu->arch.exception.has_error_code = true;
309 vcpu->arch.exception.nr = DF_VECTOR;
310 vcpu->arch.exception.error_code = 0;
311 } else
312 /* replace previous exception with a new one in a hope
313 that instruction re-execution will regenerate lost
314 exception */
315 goto queue;
316}
317
298101da
AK		 318void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
319{
ce7ddec4 320 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 321}
322EXPORT_SYMBOL_GPL(kvm_queue_exception);
323
ce7ddec4
JR		 324void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
325{
326 kvm_multiple_exception(vcpu, nr, false, 0, true);
327}
328EXPORT_SYMBOL_GPL(kvm_requeue_exception);
329
c3c91fee
AK		 330void kvm_inject_page_fault(struct kvm_vcpu *vcpu, unsigned long addr,
331 u32 error_code)
332{
333 ++vcpu->stat.pf_guest;
ad312c7c 334 vcpu->arch.cr2 = addr;
c3c91fee
AK		 335 kvm_queue_exception_e(vcpu, PF_VECTOR, error_code);
336}
337
3419ffc8
SY		 338void kvm_inject_nmi(struct kvm_vcpu *vcpu)
339{
340 vcpu->arch.nmi_pending = 1;
341}
342EXPORT_SYMBOL_GPL(kvm_inject_nmi);
343
298101da
AK		 344void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
345{
ce7ddec4 346 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 347}
348EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
349
ce7ddec4
JR		 350void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
351{
352 kvm_multiple_exception(vcpu, nr, true, error_code, true);
353}
354EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
355
0a79b009
AK		 356/*
357 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
358 * a #GP and return false.
359 */
360bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 361{
0a79b009
AK		 362 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
363 return true;
364 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
365 return false;
298101da 366}
0a79b009 367EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 368
a03490ed
CO		 369/*
370 * Load the pae pdptrs. Return true is they are all valid.
371 */
372int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3)
373{
374 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
375 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
376 int i;
377 int ret;
ad312c7c 378 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
a03490ed 379
a03490ed
CO		 380 ret = kvm_read_guest_page(vcpu->kvm, pdpt_gfn, pdpte,
381 offset * sizeof(u64), sizeof(pdpte));
382 if (ret < 0) {
383 ret = 0;
384 goto out;
385 }
386 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 387 if (is_present_gpte(pdpte[i]) &&
20c466b5 388 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 389 ret = 0;
390 goto out;
391 }
392 }
393 ret = 1;
394
ad312c7c 395 memcpy(vcpu->arch.pdptrs, pdpte, sizeof(vcpu->arch.pdptrs));
6de4f3ad
AK		 396 __set_bit(VCPU_EXREG_PDPTR,
397 (unsigned long *)&vcpu->arch.regs_avail);
398 __set_bit(VCPU_EXREG_PDPTR,
399 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 400out:
a03490ed
CO		 401
402 return ret;
403}
cc4b6871 404EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 405
d835dfec
AK		 406static bool pdptrs_changed(struct kvm_vcpu *vcpu)
407{
ad312c7c 408 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
d835dfec
AK		 409 bool changed = true;
410 int r;
411
412 if (is_long_mode(vcpu) || !is_pae(vcpu))
413 return false;
414
6de4f3ad
AK		 415 if (!test_bit(VCPU_EXREG_PDPTR,
416 (unsigned long *)&vcpu->arch.regs_avail))
417 return true;
418
ad312c7c 419 r = kvm_read_guest(vcpu->kvm, vcpu->arch.cr3 & ~31u, pdpte, sizeof(pdpte));
d835dfec
AK		 420 if (r < 0)
421 goto out;
ad312c7c 422 changed = memcmp(pdpte, vcpu->arch.pdptrs, sizeof(pdpte)) != 0;
d835dfec 423out:
d835dfec
AK		 424
425 return changed;
426}
427
49a9b07e 428int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 429{
aad82703
SY		 430 unsigned long old_cr0 = kvm_read_cr0(vcpu);
431 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
432 X86_CR0_CD | X86_CR0_NW;
433
f9a48e6a
AK		 434 cr0 |= X86_CR0_ET;
435
ab344828 436#ifdef CONFIG_X86_64
0f12244f
GN		 437 if (cr0 & 0xffffffff00000000UL)
438 return 1;
ab344828
GN		 439#endif
440
441 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 442
0f12244f
GN		 443 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
444 return 1;
a03490ed 445
0f12244f
GN		 446 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
447 return 1;
a03490ed
CO		 448
449 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
450#ifdef CONFIG_X86_64
f6801dff 451 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 452 int cs_db, cs_l;
453
0f12244f
GN		 454 if (!is_pae(vcpu))
455 return 1;
a03490ed 456 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 457 if (cs_l)
458 return 1;
a03490ed
CO		 459 } else
460#endif
0f12244f
GN		 461 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.cr3))
462 return 1;
a03490ed
CO		 463 }
464
465 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 466
aad82703
SY		 467 if ((cr0 ^ old_cr0) & update_bits)
468 kvm_mmu_reset_context(vcpu);
0f12244f
GN		 469 return 0;
470}
2d3ad1f4 471EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 472
2d3ad1f4 473void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 474{
49a9b07e 475 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 476}
2d3ad1f4 477EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 478
2acf923e
DC		 479int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
480{
481 u64 xcr0;
482
483 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
484 if (index != XCR_XFEATURE_ENABLED_MASK)
485 return 1;
486 xcr0 = xcr;
487 if (kvm_x86_ops->get_cpl(vcpu) != 0)
488 return 1;
489 if (!(xcr0 & XSTATE_FP))
490 return 1;
491 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
492 return 1;
493 if (xcr0 & ~host_xcr0)
494 return 1;
495 vcpu->arch.xcr0 = xcr0;
496 vcpu->guest_xcr0_loaded = 0;
497 return 0;
498}
499
500int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
501{
502 if (__kvm_set_xcr(vcpu, index, xcr)) {
503 kvm_inject_gp(vcpu, 0);
504 return 1;
505 }
506 return 0;
507}
508EXPORT_SYMBOL_GPL(kvm_set_xcr);
509
510static bool guest_cpuid_has_xsave(struct kvm_vcpu *vcpu)
511{
512 struct kvm_cpuid_entry2 *best;
513
514 best = kvm_find_cpuid_entry(vcpu, 1, 0);
515 return best && (best->ecx & bit(X86_FEATURE_XSAVE));
516}
517
518static void update_cpuid(struct kvm_vcpu *vcpu)
519{
520 struct kvm_cpuid_entry2 *best;
521
522 best = kvm_find_cpuid_entry(vcpu, 1, 0);
523 if (!best)
524 return;
525
526 /* Update OSXSAVE bit */
527 if (cpu_has_xsave && best->function == 0x1) {
528 best->ecx &= ~(bit(X86_FEATURE_OSXSAVE));
529 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE))
530 best->ecx |= bit(X86_FEATURE_OSXSAVE);
531 }
532}
533
a83b29c6 534int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 535{
fc78f519 536 unsigned long old_cr4 = kvm_read_cr4(vcpu);
a2edf57f
AK		 537 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE;
538
0f12244f
GN		 539 if (cr4 & CR4_RESERVED_BITS)
540 return 1;
a03490ed 541
2acf923e
DC		 542 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
543 return 1;
544
a03490ed 545 if (is_long_mode(vcpu)) {
0f12244f
GN		 546 if (!(cr4 & X86_CR4_PAE))
547 return 1;
a2edf57f
AK		 548 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
549 && ((cr4 ^ old_cr4) & pdptr_bits)
0f12244f
GN		 550 && !load_pdptrs(vcpu, vcpu->arch.cr3))
551 return 1;
552
553 if (cr4 & X86_CR4_VMXE)
554 return 1;
a03490ed 555
a03490ed 556 kvm_x86_ops->set_cr4(vcpu, cr4);
62ad0755 557
aad82703
SY		 558 if ((cr4 ^ old_cr4) & pdptr_bits)
559 kvm_mmu_reset_context(vcpu);
0f12244f 560
2acf923e
DC		 561 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
562 update_cpuid(vcpu);
563
0f12244f
GN		 564 return 0;
565}
2d3ad1f4 566EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 567
0f12244f 568static int __kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 569{
ad312c7c 570 if (cr3 == vcpu->arch.cr3 && !pdptrs_changed(vcpu)) {
0ba73cda 571 kvm_mmu_sync_roots(vcpu);
d835dfec 572 kvm_mmu_flush_tlb(vcpu);
0f12244f 573 return 0;
d835dfec
AK		 574 }
575
a03490ed 576 if (is_long_mode(vcpu)) {
0f12244f
GN		 577 if (cr3 & CR3_L_MODE_RESERVED_BITS)
578 return 1;
a03490ed
CO		 579 } else {
580 if (is_pae(vcpu)) {
0f12244f
GN		 581 if (cr3 & CR3_PAE_RESERVED_BITS)
582 return 1;
583 if (is_paging(vcpu) && !load_pdptrs(vcpu, cr3))
584 return 1;
a03490ed
CO		 585 }
586 /*
587 * We don't check reserved bits in nonpae mode, because
588 * this isn't enforced, and VMware depends on this.
589 */
590 }
591
a03490ed
CO		 592 /*
593 * Does the new cr3 value map to physical memory? (Note, we
594 * catch an invalid cr3 even in real-mode, because it would
595 * cause trouble later on when we turn on paging anyway.)
596 *
597 * A real CPU would silently accept an invalid cr3 and would
598 * attempt to use it - with largely undefined (and often hard
599 * to debug) behavior on the guest side.
600 */
601 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
0f12244f
GN		 602 return 1;
603 vcpu->arch.cr3 = cr3;
604 vcpu->arch.mmu.new_cr3(vcpu);
605 return 0;
606}
607
608void kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
609{
610 if (__kvm_set_cr3(vcpu, cr3))
c1a5d4f9 611 kvm_inject_gp(vcpu, 0);
a03490ed 612}
2d3ad1f4 613EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 614
0f12244f 615int __kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 616{
0f12244f
GN		 617 if (cr8 & CR8_RESERVED_BITS)
618 return 1;
a03490ed
CO		 619 if (irqchip_in_kernel(vcpu->kvm))
620 kvm_lapic_set_tpr(vcpu, cr8);
621 else
ad312c7c 622 vcpu->arch.cr8 = cr8;
0f12244f
GN		 623 return 0;
624}
625
626void kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
627{
628 if (__kvm_set_cr8(vcpu, cr8))
629 kvm_inject_gp(vcpu, 0);
a03490ed 630}
2d3ad1f4 631EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 632
2d3ad1f4 633unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 634{
635 if (irqchip_in_kernel(vcpu->kvm))
636 return kvm_lapic_get_cr8(vcpu);
637 else
ad312c7c 638 return vcpu->arch.cr8;
a03490ed 639}
2d3ad1f4 640EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 641
338dbc97 642static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 643{
644 switch (dr) {
645 case 0 ... 3:
646 vcpu->arch.db[dr] = val;
647 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
648 vcpu->arch.eff_db[dr] = val;
649 break;
650 case 4:
338dbc97
GN		 651 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
652 return 1; /* #UD */
020df079
GN		 653 /* fall through */
654 case 6:
338dbc97
GN		 655 if (val & 0xffffffff00000000ULL)
656 return -1; /* #GP */
020df079
GN		 657 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
658 break;
659 case 5:
338dbc97
GN		 660 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
661 return 1; /* #UD */
020df079
GN		 662 /* fall through */
663 default: /* 7 */
338dbc97
GN		 664 if (val & 0xffffffff00000000ULL)
665 return -1; /* #GP */
020df079
GN		 666 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
667 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
668 kvm_x86_ops->set_dr7(vcpu, vcpu->arch.dr7);
669 vcpu->arch.switch_db_regs = (val & DR7_BP_EN_MASK);
670 }
671 break;
672 }
673
674 return 0;
675}
338dbc97
GN		 676
677int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
678{
679 int res;
680
681 res = __kvm_set_dr(vcpu, dr, val);
682 if (res > 0)
683 kvm_queue_exception(vcpu, UD_VECTOR);
684 else if (res < 0)
685 kvm_inject_gp(vcpu, 0);
686
687 return res;
688}
020df079
GN		 689EXPORT_SYMBOL_GPL(kvm_set_dr);
690
338dbc97 691static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 692{
693 switch (dr) {
694 case 0 ... 3:
695 *val = vcpu->arch.db[dr];
696 break;
697 case 4:
338dbc97 698 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 699 return 1;
020df079
GN		 700 /* fall through */
701 case 6:
702 *val = vcpu->arch.dr6;
703 break;
704 case 5:
338dbc97 705 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 706 return 1;
020df079
GN		 707 /* fall through */
708 default: /* 7 */
709 *val = vcpu->arch.dr7;
710 break;
711 }
712
713 return 0;
714}
338dbc97
GN		 715
716int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
717{
718 if (_kvm_get_dr(vcpu, dr, val)) {
719 kvm_queue_exception(vcpu, UD_VECTOR);
720 return 1;
721 }
722 return 0;
723}
020df079
GN		 724EXPORT_SYMBOL_GPL(kvm_get_dr);
725
043405e1
CO		 726/*
727 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
728 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
729 *
730 * This list is modified at module load time to reflect the
e3267cbb
GC		 731 * capabilities of the host cpu. This capabilities test skips MSRs that are
732 * kvm-specific. Those are put in the beginning of the list.
043405e1 733 */
e3267cbb 734
11c6bffa 735#define KVM_SAVE_MSRS_BEGIN 7
043405e1 736static u32 msrs_to_save[] = {
e3267cbb 737 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
11c6bffa 738 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
55cd8e5a 739 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
10388a07 740 HV_X64_MSR_APIC_ASSIST_PAGE,
043405e1
CO		 741 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
742 MSR_K6_STAR,
743#ifdef CONFIG_X86_64
744 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
745#endif
e3267cbb 746 MSR_IA32_TSC, MSR_IA32_PERF_STATUS, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
043405e1
CO		 747};
748
749static unsigned num_msrs_to_save;
750
751static u32 emulated_msrs[] = {
752 MSR_IA32_MISC_ENABLE,
753};
754
b69e8cae 755static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 756{
aad82703
SY		 757 u64 old_efer = vcpu->arch.efer;
758
b69e8cae
RJ		 759 if (efer & efer_reserved_bits)
760 return 1;
15c4a640
CO		 761
762 if (is_paging(vcpu)
b69e8cae
RJ		 763 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
764 return 1;
15c4a640 765
1b2fd70c
AG		 766 if (efer & EFER_FFXSR) {
767 struct kvm_cpuid_entry2 *feat;
768
769 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 770 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
771 return 1;
1b2fd70c
AG		 772 }
773
d8017474
AG		 774 if (efer & EFER_SVME) {
775 struct kvm_cpuid_entry2 *feat;
776
777 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 778 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
779 return 1;
d8017474
AG		 780 }
781
15c4a640 782 efer &= ~EFER_LMA;
f6801dff 783 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 784
a3d204e2
SY		 785 kvm_x86_ops->set_efer(vcpu, efer);
786
9645bb56
AK		 787 vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
788 kvm_mmu_reset_context(vcpu);
b69e8cae 789
aad82703
SY		 790 /* Update reserved bits */
791 if ((efer ^ old_efer) & EFER_NX)
792 kvm_mmu_reset_context(vcpu);
793
b69e8cae 794 return 0;
15c4a640
CO		 795}
796
f2b4b7dd
JR		 797void kvm_enable_efer_bits(u64 mask)
798{
799 efer_reserved_bits &= ~mask;
800}
801EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
802
803
15c4a640
CO		 804/*
805 * Writes msr value into into the appropriate "register".
806 * Returns 0 on success, non-0 otherwise.
807 * Assumes vcpu_load() was already called.
808 */
809int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
810{
811 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
812}
813
313a3dc7
CO		 814/*
815 * Adapt set_msr() to msr_io()'s calling convention
816 */
817static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
818{
819 return kvm_set_msr(vcpu, index, *data);
820}
821
18068523
GOC		 822static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
823{
9ed3c444
AK		 824 int version;
825 int r;
50d0a0f9 826 struct pvclock_wall_clock wc;
923de3cf 827 struct timespec boot;
18068523
GOC		 828
829 if (!wall_clock)
830 return;
831
9ed3c444
AK		 832 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
833 if (r)
834 return;
835
836 if (version & 1)
837 ++version; /* first time write, random junk */
838
839 ++version;
18068523 840
18068523
GOC		 841 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
842
50d0a0f9
GH		 843 /*
844 * The guest calculates current wall clock time by adding
845 * system time (updated by kvm_write_guest_time below) to the
846 * wall clock specified here. guest system time equals host
847 * system time for us, thus we must fill in host boot time here.
848 */
923de3cf 849 getboottime(&boot);
50d0a0f9
GH		 850
851 wc.sec = boot.tv_sec;
852 wc.nsec = boot.tv_nsec;
853 wc.version = version;
18068523
GOC		 854
855 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
856
857 version++;
858 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 859}
860
50d0a0f9
GH		 861static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
862{
863 uint32_t quotient, remainder;
864
865 /* Don't try to replace with do_div(), this one calculates
866 * "(dividend << 32) / divisor" */
867 __asm__ ( "divl %4"
868 : "=a" (quotient), "=d" (remainder)
869 : "0" (0), "1" (dividend), "r" (divisor) );
870 return quotient;
871}
872
873static void kvm_set_time_scale(uint32_t tsc_khz, struct pvclock_vcpu_time_info *hv_clock)
874{
875 uint64_t nsecs = 1000000000LL;
876 int32_t shift = 0;
877 uint64_t tps64;
878 uint32_t tps32;
879
880 tps64 = tsc_khz * 1000LL;
881 while (tps64 > nsecs*2) {
882 tps64 >>= 1;
883 shift--;
884 }
885
886 tps32 = (uint32_t)tps64;
887 while (tps32 <= (uint32_t)nsecs) {
888 tps32 <<= 1;
889 shift++;
890 }
891
892 hv_clock->tsc_shift = shift;
893 hv_clock->tsc_to_system_mul = div_frac(nsecs, tps32);
894
895 pr_debug("%s: tsc_khz %u, tsc_shift %d, tsc_mul %u\n",
80a914dc 896 __func__, tsc_khz, hv_clock->tsc_shift,
50d0a0f9
GH		 897 hv_clock->tsc_to_system_mul);
898}
899
c8076604
GH		 900static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
901
18068523
GOC		 902static void kvm_write_guest_time(struct kvm_vcpu *v)
903{
904 struct timespec ts;
905 unsigned long flags;
906 struct kvm_vcpu_arch *vcpu = &v->arch;
907 void *shared_kaddr;
463656c0 908 unsigned long this_tsc_khz;
18068523
GOC		 909
910 if ((!vcpu->time_page))
911 return;
912
463656c0
AK		 913 this_tsc_khz = get_cpu_var(cpu_tsc_khz);
914 if (unlikely(vcpu->hv_clock_tsc_khz != this_tsc_khz)) {
915 kvm_set_time_scale(this_tsc_khz, &vcpu->hv_clock);
916 vcpu->hv_clock_tsc_khz = this_tsc_khz;
50d0a0f9 917 }
463656c0 918 put_cpu_var(cpu_tsc_khz);
50d0a0f9 919
18068523
GOC		 920 /* Keep irq disabled to prevent changes to the clock */
921 local_irq_save(flags);
af24a4e4 922 kvm_get_msr(v, MSR_IA32_TSC, &vcpu->hv_clock.tsc_timestamp);
18068523 923 ktime_get_ts(&ts);
923de3cf 924 monotonic_to_bootbased(&ts);
18068523
GOC		 925 local_irq_restore(flags);
926
927 /* With all the info we got, fill in the values */
928
929 vcpu->hv_clock.system_time = ts.tv_nsec +
afbcf7ab
GC		 930 (NSEC_PER_SEC * (u64)ts.tv_sec) + v->kvm->arch.kvmclock_offset;
931
371bcf64
GC		 932 vcpu->hv_clock.flags = 0;
933
18068523
GOC		 934 /*
935 * The interface expects us to write an even number signaling that the
936 * update is finished. Since the guest won't see the intermediate
50d0a0f9 937 * state, we just increase by 2 at the end.
18068523 938 */
50d0a0f9 939 vcpu->hv_clock.version += 2;
18068523
GOC		 940
941 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
942
943 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
50d0a0f9 944 sizeof(vcpu->hv_clock));
18068523
GOC		 945
946 kunmap_atomic(shared_kaddr, KM_USER0);
947
948 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
949}
950
c8076604
GH		 951static int kvm_request_guest_time_update(struct kvm_vcpu *v)
952{
953 struct kvm_vcpu_arch *vcpu = &v->arch;
954
955 if (!vcpu->time_page)
956 return 0;
957 set_bit(KVM_REQ_KVMCLOCK_UPDATE, &v->requests);
958 return 1;
959}
960
9ba075a6
AK		 961static bool msr_mtrr_valid(unsigned msr)
962{
963 switch (msr) {
964 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
965 case MSR_MTRRfix64K_00000:
966 case MSR_MTRRfix16K_80000:
967 case MSR_MTRRfix16K_A0000:
968 case MSR_MTRRfix4K_C0000:
969 case MSR_MTRRfix4K_C8000:
970 case MSR_MTRRfix4K_D0000:
971 case MSR_MTRRfix4K_D8000:
972 case MSR_MTRRfix4K_E0000:
973 case MSR_MTRRfix4K_E8000:
974 case MSR_MTRRfix4K_F0000:
975 case MSR_MTRRfix4K_F8000:
976 case MSR_MTRRdefType:
977 case MSR_IA32_CR_PAT:
978 return true;
979 case 0x2f8:
980 return true;
981 }
982 return false;
983}
984
d6289b93
MT		 985static bool valid_pat_type(unsigned t)
986{
987 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
988}
989
990static bool valid_mtrr_type(unsigned t)
991{
992 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
993}
994
995static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
996{
997 int i;
998
999 if (!msr_mtrr_valid(msr))
1000 return false;
1001
1002 if (msr == MSR_IA32_CR_PAT) {
1003 for (i = 0; i < 8; i++)
1004 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1005 return false;
1006 return true;
1007 } else if (msr == MSR_MTRRdefType) {
1008 if (data & ~0xcff)
1009 return false;
1010 return valid_mtrr_type(data & 0xff);
1011 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1012 for (i = 0; i < 8 ; i++)
1013 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1014 return false;
1015 return true;
1016 }
1017
1018 /* variable MTRRs */
1019 return valid_mtrr_type(data & 0xff);
1020}
1021
9ba075a6
AK		 1022static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1023{
0bed3b56
SY		 1024 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1025
d6289b93 1026 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 1027 return 1;
1028
0bed3b56
SY		 1029 if (msr == MSR_MTRRdefType) {
1030 vcpu->arch.mtrr_state.def_type = data;
1031 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1032 } else if (msr == MSR_MTRRfix64K_00000)
1033 p[0] = data;
1034 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1035 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1036 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1037 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1038 else if (msr == MSR_IA32_CR_PAT)
1039 vcpu->arch.pat = data;
1040 else { /* Variable MTRRs */
1041 int idx, is_mtrr_mask;
1042 u64 *pt;
1043
1044 idx = (msr - 0x200) / 2;
1045 is_mtrr_mask = msr - 0x200 - 2 * idx;
1046 if (!is_mtrr_mask)
1047 pt =
1048 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1049 else
1050 pt =
1051 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1052 *pt = data;
1053 }
1054
1055 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 1056 return 0;
1057}
15c4a640 1058
890ca9ae 1059static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1060{
890ca9ae
HY		 1061 u64 mcg_cap = vcpu->arch.mcg_cap;
1062 unsigned bank_num = mcg_cap & 0xff;
1063
15c4a640 1064 switch (msr) {
15c4a640 1065 case MSR_IA32_MCG_STATUS:
890ca9ae 1066 vcpu->arch.mcg_status = data;
15c4a640 1067 break;
c7ac679c 1068 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1069 if (!(mcg_cap & MCG_CTL_P))
1070 return 1;
1071 if (data != 0 && data != ~(u64)0)
1072 return -1;
1073 vcpu->arch.mcg_ctl = data;
1074 break;
1075 default:
1076 if (msr >= MSR_IA32_MC0_CTL &&
1077 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1078 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1079 /* only 0 or all 1s can be written to IA32_MCi_CTL
1080 * some Linux kernels though clear bit 10 in bank 4 to
1081 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1082 * this to avoid an uncatched #GP in the guest
1083 */
890ca9ae 1084 if ((offset & 0x3) == 0 &&
114be429 1085 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1086 return -1;
1087 vcpu->arch.mce_banks[offset] = data;
1088 break;
1089 }
1090 return 1;
1091 }
1092 return 0;
1093}
1094
ffde22ac
ES		 1095static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1096{
1097 struct kvm *kvm = vcpu->kvm;
1098 int lm = is_long_mode(vcpu);
1099 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1100 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1101 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1102 : kvm->arch.xen_hvm_config.blob_size_32;
1103 u32 page_num = data & ~PAGE_MASK;
1104 u64 page_addr = data & PAGE_MASK;
1105 u8 *page;
1106 int r;
1107
1108 r = -E2BIG;
1109 if (page_num >= blob_size)
1110 goto out;
1111 r = -ENOMEM;
1112 page = kzalloc(PAGE_SIZE, GFP_KERNEL);
1113 if (!page)
1114 goto out;
1115 r = -EFAULT;
1116 if (copy_from_user(page, blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE))
1117 goto out_free;
1118 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1119 goto out_free;
1120 r = 0;
1121out_free:
1122 kfree(page);
1123out:
1124 return r;
1125}
1126
55cd8e5a
GN		 1127static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1128{
1129 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1130}
1131
1132static bool kvm_hv_msr_partition_wide(u32 msr)
1133{
1134 bool r = false;
1135 switch (msr) {
1136 case HV_X64_MSR_GUEST_OS_ID:
1137 case HV_X64_MSR_HYPERCALL:
1138 r = true;
1139 break;
1140 }
1141
1142 return r;
1143}
1144
1145static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1146{
1147 struct kvm *kvm = vcpu->kvm;
1148
1149 switch (msr) {
1150 case HV_X64_MSR_GUEST_OS_ID:
1151 kvm->arch.hv_guest_os_id = data;
1152 /* setting guest os id to zero disables hypercall page */
1153 if (!kvm->arch.hv_guest_os_id)
1154 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1155 break;
1156 case HV_X64_MSR_HYPERCALL: {
1157 u64 gfn;
1158 unsigned long addr;
1159 u8 instructions[4];
1160
1161 /* if guest os id is not set hypercall should remain disabled */
1162 if (!kvm->arch.hv_guest_os_id)
1163 break;
1164 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1165 kvm->arch.hv_hypercall = data;
1166 break;
1167 }
1168 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1169 addr = gfn_to_hva(kvm, gfn);
1170 if (kvm_is_error_hva(addr))
1171 return 1;
1172 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1173 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
1174 if (copy_to_user((void __user *)addr, instructions, 4))
1175 return 1;
1176 kvm->arch.hv_hypercall = data;
1177 break;
1178 }
1179 default:
1180 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1181 "data 0x%llx\n", msr, data);
1182 return 1;
1183 }
1184 return 0;
1185}
1186
1187static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1188{
10388a07
GN		 1189 switch (msr) {
1190 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1191 unsigned long addr;
55cd8e5a 1192
10388a07
GN		 1193 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1194 vcpu->arch.hv_vapic = data;
1195 break;
1196 }
1197 addr = gfn_to_hva(vcpu->kvm, data >>
1198 HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1199 if (kvm_is_error_hva(addr))
1200 return 1;
1201 if (clear_user((void __user *)addr, PAGE_SIZE))
1202 return 1;
1203 vcpu->arch.hv_vapic = data;
1204 break;
1205 }
1206 case HV_X64_MSR_EOI:
1207 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1208 case HV_X64_MSR_ICR:
1209 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1210 case HV_X64_MSR_TPR:
1211 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1212 default:
1213 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1214 "data 0x%llx\n", msr, data);
1215 return 1;
1216 }
1217
1218 return 0;
55cd8e5a
GN		 1219}
1220
15c4a640
CO		 1221int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1222{
1223 switch (msr) {
15c4a640 1224 case MSR_EFER:
b69e8cae 1225 return set_efer(vcpu, data);
8f1589d9
AP		 1226 case MSR_K7_HWCR:
1227 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 1228 data &= ~(u64)0x100; /* ignore ignne emulation enable */
8f1589d9
AP		 1229 if (data != 0) {
1230 pr_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1231 data);
1232 return 1;
1233 }
15c4a640 1234 break;
f7c6d140
AP		 1235 case MSR_FAM10H_MMIO_CONF_BASE:
1236 if (data != 0) {
1237 pr_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1238 "0x%llx\n", data);
1239 return 1;
1240 }
15c4a640 1241 break;
c323c0e5 1242 case MSR_AMD64_NB_CFG:
c7ac679c 1243 break;
b5e2fec0
AG		 1244 case MSR_IA32_DEBUGCTLMSR:
1245 if (!data) {
1246 /* We support the non-activated case already */
1247 break;
1248 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1249 /* Values other than LBR and BTF are vendor-specific,
1250 thus reserved and should throw a #GP */
1251 return 1;
1252 }
1253 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1254 __func__, data);
1255 break;
15c4a640
CO		 1256 case MSR_IA32_UCODE_REV:
1257 case MSR_IA32_UCODE_WRITE:
61a6bd67 1258 case MSR_VM_HSAVE_PA:
6098ca93 1259 case MSR_AMD64_PATCH_LOADER:
15c4a640 1260 break;
9ba075a6
AK		 1261 case 0x200 ... 0x2ff:
1262 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 1263 case MSR_IA32_APICBASE:
1264 kvm_set_apic_base(vcpu, data);
1265 break;
0105d1a5
GN		 1266 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1267 return kvm_x2apic_msr_write(vcpu, msr, data);
15c4a640 1268 case MSR_IA32_MISC_ENABLE:
ad312c7c 1269 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 1270 break;
11c6bffa 1271 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1272 case MSR_KVM_WALL_CLOCK:
1273 vcpu->kvm->arch.wall_clock = data;
1274 kvm_write_wall_clock(vcpu->kvm, data);
1275 break;
11c6bffa 1276 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 1277 case MSR_KVM_SYSTEM_TIME: {
1278 if (vcpu->arch.time_page) {
1279 kvm_release_page_dirty(vcpu->arch.time_page);
1280 vcpu->arch.time_page = NULL;
1281 }
1282
1283 vcpu->arch.time = data;
1284
1285 /* we verify if the enable bit is set... */
1286 if (!(data & 1))
1287 break;
1288
1289 /* ...but clean it before doing the actual write */
1290 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
1291
18068523
GOC		 1292 vcpu->arch.time_page =
1293 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
18068523
GOC		 1294
1295 if (is_error_page(vcpu->arch.time_page)) {
1296 kvm_release_page_clean(vcpu->arch.time_page);
1297 vcpu->arch.time_page = NULL;
1298 }
1299
c8076604 1300 kvm_request_guest_time_update(vcpu);
18068523
GOC		 1301 break;
1302 }
890ca9ae
HY		 1303 case MSR_IA32_MCG_CTL:
1304 case MSR_IA32_MCG_STATUS:
1305 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1306 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 1307
1308 /* Performance counters are not protected by a CPUID bit,
1309 * so we should check all of them in the generic path for the sake of
1310 * cross vendor migration.
1311 * Writing a zero into the event select MSRs disables them,
1312 * which we perfectly emulate ;-). Any other value should be at least
1313 * reported, some guests depend on them.
1314 */
1315 case MSR_P6_EVNTSEL0:
1316 case MSR_P6_EVNTSEL1:
1317 case MSR_K7_EVNTSEL0:
1318 case MSR_K7_EVNTSEL1:
1319 case MSR_K7_EVNTSEL2:
1320 case MSR_K7_EVNTSEL3:
1321 if (data != 0)
1322 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1323 "0x%x data 0x%llx\n", msr, data);
1324 break;
1325 /* at least RHEL 4 unconditionally writes to the perfctr registers,
1326 * so we ignore writes to make it happy.
1327 */
1328 case MSR_P6_PERFCTR0:
1329 case MSR_P6_PERFCTR1:
1330 case MSR_K7_PERFCTR0:
1331 case MSR_K7_PERFCTR1:
1332 case MSR_K7_PERFCTR2:
1333 case MSR_K7_PERFCTR3:
1334 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1335 "0x%x data 0x%llx\n", msr, data);
1336 break;
55cd8e5a
GN		 1337 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1338 if (kvm_hv_msr_partition_wide(msr)) {
1339 int r;
1340 mutex_lock(&vcpu->kvm->lock);
1341 r = set_msr_hyperv_pw(vcpu, msr, data);
1342 mutex_unlock(&vcpu->kvm->lock);
1343 return r;
1344 } else
1345 return set_msr_hyperv(vcpu, msr, data);
1346 break;
15c4a640 1347 default:
ffde22ac
ES		 1348 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
1349 return xen_hvm_config(vcpu, data);
ed85c068
AP		 1350 if (!ignore_msrs) {
1351 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
1352 msr, data);
1353 return 1;
1354 } else {
1355 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
1356 msr, data);
1357 break;
1358 }
15c4a640
CO		 1359 }
1360 return 0;
1361}
1362EXPORT_SYMBOL_GPL(kvm_set_msr_common);
1363
1364
1365/*
1366 * Reads an msr value (of 'msr_index') into 'pdata'.
1367 * Returns 0 on success, non-0 otherwise.
1368 * Assumes vcpu_load() was already called.
1369 */
1370int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1371{
1372 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
1373}
1374
9ba075a6
AK		 1375static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1376{
0bed3b56
SY		 1377 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1378
9ba075a6
AK		 1379 if (!msr_mtrr_valid(msr))
1380 return 1;
1381
0bed3b56
SY		 1382 if (msr == MSR_MTRRdefType)
1383 *pdata = vcpu->arch.mtrr_state.def_type +
1384 (vcpu->arch.mtrr_state.enabled << 10);
1385 else if (msr == MSR_MTRRfix64K_00000)
1386 *pdata = p[0];
1387 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1388 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
1389 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1390 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
1391 else if (msr == MSR_IA32_CR_PAT)
1392 *pdata = vcpu->arch.pat;
1393 else { /* Variable MTRRs */
1394 int idx, is_mtrr_mask;
1395 u64 *pt;
1396
1397 idx = (msr - 0x200) / 2;
1398 is_mtrr_mask = msr - 0x200 - 2 * idx;
1399 if (!is_mtrr_mask)
1400 pt =
1401 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1402 else
1403 pt =
1404 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1405 *pdata = *pt;
1406 }
1407
9ba075a6
AK		 1408 return 0;
1409}
1410
890ca9ae 1411static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 1412{
1413 u64 data;
890ca9ae
HY		 1414 u64 mcg_cap = vcpu->arch.mcg_cap;
1415 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 1416
1417 switch (msr) {
15c4a640
CO		 1418 case MSR_IA32_P5_MC_ADDR:
1419 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 1420 data = 0;
1421 break;
15c4a640 1422 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 1423 data = vcpu->arch.mcg_cap;
1424 break;
c7ac679c 1425 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1426 if (!(mcg_cap & MCG_CTL_P))
1427 return 1;
1428 data = vcpu->arch.mcg_ctl;
1429 break;
1430 case MSR_IA32_MCG_STATUS:
1431 data = vcpu->arch.mcg_status;
1432 break;
1433 default:
1434 if (msr >= MSR_IA32_MC0_CTL &&
1435 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1436 u32 offset = msr - MSR_IA32_MC0_CTL;
1437 data = vcpu->arch.mce_banks[offset];
1438 break;
1439 }
1440 return 1;
1441 }
1442 *pdata = data;
1443 return 0;
1444}
1445
55cd8e5a
GN		 1446static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1447{
1448 u64 data = 0;
1449 struct kvm *kvm = vcpu->kvm;
1450
1451 switch (msr) {
1452 case HV_X64_MSR_GUEST_OS_ID:
1453 data = kvm->arch.hv_guest_os_id;
1454 break;
1455 case HV_X64_MSR_HYPERCALL:
1456 data = kvm->arch.hv_hypercall;
1457 break;
1458 default:
1459 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1460 return 1;
1461 }
1462
1463 *pdata = data;
1464 return 0;
1465}
1466
1467static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1468{
1469 u64 data = 0;
1470
1471 switch (msr) {
1472 case HV_X64_MSR_VP_INDEX: {
1473 int r;
1474 struct kvm_vcpu *v;
1475 kvm_for_each_vcpu(r, v, vcpu->kvm)
1476 if (v == vcpu)
1477 data = r;
1478 break;
1479 }
10388a07
GN		 1480 case HV_X64_MSR_EOI:
1481 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
1482 case HV_X64_MSR_ICR:
1483 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
1484 case HV_X64_MSR_TPR:
1485 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
55cd8e5a
GN		 1486 default:
1487 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1488 return 1;
1489 }
1490 *pdata = data;
1491 return 0;
1492}
1493
890ca9ae
HY		 1494int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1495{
1496 u64 data;
1497
1498 switch (msr) {
890ca9ae 1499 case MSR_IA32_PLATFORM_ID:
15c4a640 1500 case MSR_IA32_UCODE_REV:
15c4a640 1501 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 1502 case MSR_IA32_DEBUGCTLMSR:
1503 case MSR_IA32_LASTBRANCHFROMIP:
1504 case MSR_IA32_LASTBRANCHTOIP:
1505 case MSR_IA32_LASTINTFROMIP:
1506 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 1507 case MSR_K8_SYSCFG:
1508 case MSR_K7_HWCR:
61a6bd67 1509 case MSR_VM_HSAVE_PA:
1f3ee616
AS		 1510 case MSR_P6_PERFCTR0:
1511 case MSR_P6_PERFCTR1:
7fe29e0f
AS		 1512 case MSR_P6_EVNTSEL0:
1513 case MSR_P6_EVNTSEL1:
9e699624 1514 case MSR_K7_EVNTSEL0:
1f3ee616 1515 case MSR_K7_PERFCTR0:
1fdbd48c 1516 case MSR_K8_INT_PENDING_MSG:
c323c0e5 1517 case MSR_AMD64_NB_CFG:
f7c6d140 1518 case MSR_FAM10H_MMIO_CONF_BASE:
15c4a640
CO		 1519 data = 0;
1520 break;
9ba075a6
AK		 1521 case MSR_MTRRcap:
1522 data = 0x500 | KVM_NR_VAR_MTRR;
1523 break;
1524 case 0x200 ... 0x2ff:
1525 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 1526 case 0xcd: /* fsb frequency */
1527 data = 3;
1528 break;
1529 case MSR_IA32_APICBASE:
1530 data = kvm_get_apic_base(vcpu);
1531 break;
0105d1a5
GN		 1532 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1533 return kvm_x2apic_msr_read(vcpu, msr, pdata);
1534 break;
15c4a640 1535 case MSR_IA32_MISC_ENABLE:
ad312c7c 1536 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 1537 break;
847f0ad8
AG		 1538 case MSR_IA32_PERF_STATUS:
1539 /* TSC increment by tick */
1540 data = 1000ULL;
1541 /* CPU multiplier */
1542 data |= (((uint64_t)4ULL) << 40);
1543 break;
15c4a640 1544 case MSR_EFER:
f6801dff 1545 data = vcpu->arch.efer;
15c4a640 1546 break;
18068523 1547 case MSR_KVM_WALL_CLOCK:
11c6bffa 1548 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1549 data = vcpu->kvm->arch.wall_clock;
1550 break;
1551 case MSR_KVM_SYSTEM_TIME:
11c6bffa 1552 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 1553 data = vcpu->arch.time;
1554 break;
890ca9ae
HY		 1555 case MSR_IA32_P5_MC_ADDR:
1556 case MSR_IA32_P5_MC_TYPE:
1557 case MSR_IA32_MCG_CAP:
1558 case MSR_IA32_MCG_CTL:
1559 case MSR_IA32_MCG_STATUS:
1560 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1561 return get_msr_mce(vcpu, msr, pdata);
55cd8e5a
GN		 1562 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1563 if (kvm_hv_msr_partition_wide(msr)) {
1564 int r;
1565 mutex_lock(&vcpu->kvm->lock);
1566 r = get_msr_hyperv_pw(vcpu, msr, pdata);
1567 mutex_unlock(&vcpu->kvm->lock);
1568 return r;
1569 } else
1570 return get_msr_hyperv(vcpu, msr, pdata);
1571 break;
15c4a640 1572 default:
ed85c068
AP		 1573 if (!ignore_msrs) {
1574 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
1575 return 1;
1576 } else {
1577 pr_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
1578 data = 0;
1579 }
1580 break;
15c4a640
CO		 1581 }
1582 *pdata = data;
1583 return 0;
1584}
1585EXPORT_SYMBOL_GPL(kvm_get_msr_common);
1586
313a3dc7
CO		 1587/*
1588 * Read or write a bunch of msrs. All parameters are kernel addresses.
1589 *
1590 * @return number of msrs set successfully.
1591 */
1592static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
1593 struct kvm_msr_entry *entries,
1594 int (*do_msr)(struct kvm_vcpu *vcpu,
1595 unsigned index, u64 *data))
1596{
f656ce01 1597 int i, idx;
313a3dc7 1598
f656ce01 1599 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 1600 for (i = 0; i < msrs->nmsrs; ++i)
1601 if (do_msr(vcpu, entries[i].index, &entries[i].data))
1602 break;
f656ce01 1603 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 1604
313a3dc7
CO		 1605 return i;
1606}
1607
1608/*
1609 * Read or write a bunch of msrs. Parameters are user addresses.
1610 *
1611 * @return number of msrs set successfully.
1612 */
1613static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
1614 int (*do_msr)(struct kvm_vcpu *vcpu,
1615 unsigned index, u64 *data),
1616 int writeback)
1617{
1618 struct kvm_msrs msrs;
1619 struct kvm_msr_entry *entries;
1620 int r, n;
1621 unsigned size;
1622
1623 r = -EFAULT;
1624 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
1625 goto out;
1626
1627 r = -E2BIG;
1628 if (msrs.nmsrs >= MAX_IO_MSRS)
1629 goto out;
1630
1631 r = -ENOMEM;
1632 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
7a73c028 1633 entries = kmalloc(size, GFP_KERNEL);
313a3dc7
CO		 1634 if (!entries)
1635 goto out;
1636
1637 r = -EFAULT;
1638 if (copy_from_user(entries, user_msrs->entries, size))
1639 goto out_free;
1640
1641 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
1642 if (r < 0)
1643 goto out_free;
1644
1645 r = -EFAULT;
1646 if (writeback && copy_to_user(user_msrs->entries, entries, size))
1647 goto out_free;
1648
1649 r = n;
1650
1651out_free:
7a73c028 1652 kfree(entries);
313a3dc7
CO		 1653out:
1654 return r;
1655}
1656
018d00d2
ZX		 1657int kvm_dev_ioctl_check_extension(long ext)
1658{
1659 int r;
1660
1661 switch (ext) {
1662 case KVM_CAP_IRQCHIP:
1663 case KVM_CAP_HLT:
1664 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 1665 case KVM_CAP_SET_TSS_ADDR:
07716717 1666 case KVM_CAP_EXT_CPUID:
c8076604 1667 case KVM_CAP_CLOCKSOURCE:
7837699f 1668 case KVM_CAP_PIT:
a28e4f5a 1669 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 1670 case KVM_CAP_MP_STATE:
ed848624 1671 case KVM_CAP_SYNC_MMU:
52d939a0 1672 case KVM_CAP_REINJECT_CONTROL:
4925663a 1673 case KVM_CAP_IRQ_INJECT_STATUS:
e56d532f 1674 case KVM_CAP_ASSIGN_DEV_IRQ:
721eecbf 1675 case KVM_CAP_IRQFD:
d34e6b17 1676 case KVM_CAP_IOEVENTFD:
c5ff41ce 1677 case KVM_CAP_PIT2:
e9f42757 1678 case KVM_CAP_PIT_STATE2:
b927a3ce 1679 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 1680 case KVM_CAP_XEN_HVM:
afbcf7ab 1681 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 1682 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 1683 case KVM_CAP_HYPERV:
10388a07 1684 case KVM_CAP_HYPERV_VAPIC:
c25bc163 1685 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 1686 case KVM_CAP_PCI_SEGMENT:
a1efbe77 1687 case KVM_CAP_DEBUGREGS:
d2be1651 1688 case KVM_CAP_X86_ROBUST_SINGLESTEP:
018d00d2
ZX		 1689 r = 1;
1690 break;
542472b5
LV		 1691 case KVM_CAP_COALESCED_MMIO:
1692 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
1693 break;
774ead3a
AK		 1694 case KVM_CAP_VAPIC:
1695 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
1696 break;
f725230a
AK		 1697 case KVM_CAP_NR_VCPUS:
1698 r = KVM_MAX_VCPUS;
1699 break;
a988b910
AK		 1700 case KVM_CAP_NR_MEMSLOTS:
1701 r = KVM_MEMORY_SLOTS;
1702 break;
a68a6a72
MT		 1703 case KVM_CAP_PV_MMU: /* obsolete */
1704 r = 0;
2f333bcb 1705 break;
62c476c7 1706 case KVM_CAP_IOMMU:
19de40a8 1707 r = iommu_found();
62c476c7 1708 break;
890ca9ae
HY		 1709 case KVM_CAP_MCE:
1710 r = KVM_MAX_MCE_BANKS;
1711 break;
018d00d2
ZX		 1712 default:
1713 r = 0;
1714 break;
1715 }
1716 return r;
1717
1718}
1719
043405e1
CO		 1720long kvm_arch_dev_ioctl(struct file *filp,
1721 unsigned int ioctl, unsigned long arg)
1722{
1723 void __user *argp = (void __user *)arg;
1724 long r;
1725
1726 switch (ioctl) {
1727 case KVM_GET_MSR_INDEX_LIST: {
1728 struct kvm_msr_list __user *user_msr_list = argp;
1729 struct kvm_msr_list msr_list;
1730 unsigned n;
1731
1732 r = -EFAULT;
1733 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
1734 goto out;
1735 n = msr_list.nmsrs;
1736 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
1737 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
1738 goto out;
1739 r = -E2BIG;
e125e7b6 1740 if (n < msr_list.nmsrs)
043405e1
CO		 1741 goto out;
1742 r = -EFAULT;
1743 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
1744 num_msrs_to_save * sizeof(u32)))
1745 goto out;
e125e7b6 1746 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 1747 &emulated_msrs,
1748 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
1749 goto out;
1750 r = 0;
1751 break;
1752 }
674eea0f
AK		 1753 case KVM_GET_SUPPORTED_CPUID: {
1754 struct kvm_cpuid2 __user *cpuid_arg = argp;
1755 struct kvm_cpuid2 cpuid;
1756
1757 r = -EFAULT;
1758 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1759 goto out;
1760 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
19355475 1761 cpuid_arg->entries);
674eea0f
AK		 1762 if (r)
1763 goto out;
1764
1765 r = -EFAULT;
1766 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
1767 goto out;
1768 r = 0;
1769 break;
1770 }
890ca9ae
HY		 1771 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
1772 u64 mce_cap;
1773
1774 mce_cap = KVM_MCE_CAP_SUPPORTED;
1775 r = -EFAULT;
1776 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
1777 goto out;
1778 r = 0;
1779 break;
1780 }
043405e1
CO		 1781 default:
1782 r = -EINVAL;
1783 }
1784out:
1785 return r;
1786}
1787
313a3dc7
CO		 1788void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1789{
1790 kvm_x86_ops->vcpu_load(vcpu, cpu);
6b7d7e76
ZA		 1791 if (unlikely(per_cpu(cpu_tsc_khz, cpu) == 0)) {
1792 unsigned long khz = cpufreq_quick_get(cpu);
1793 if (!khz)
1794 khz = tsc_khz;
1795 per_cpu(cpu_tsc_khz, cpu) = khz;
1796 }
c8076604 1797 kvm_request_guest_time_update(vcpu);
313a3dc7
CO		 1798}
1799
1800void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
1801{
02daab21 1802 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 1803 kvm_put_guest_fpu(vcpu);
313a3dc7
CO		 1804}
1805
07716717 1806static int is_efer_nx(void)
313a3dc7 1807{
e286e86e 1808 unsigned long long efer = 0;
313a3dc7 1809
e286e86e 1810 rdmsrl_safe(MSR_EFER, &efer);
07716717
DK		 1811 return efer & EFER_NX;
1812}
1813
1814static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
1815{
1816 int i;
1817 struct kvm_cpuid_entry2 *e, *entry;
1818
313a3dc7 1819 entry = NULL;
ad312c7c
ZX		 1820 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
1821 e = &vcpu->arch.cpuid_entries[i];
313a3dc7
CO		 1822 if (e->function == 0x80000001) {
1823 entry = e;
1824 break;
1825 }
1826 }
07716717 1827 if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) {
313a3dc7
CO		 1828 entry->edx &= ~(1 << 20);
1829 printk(KERN_INFO "kvm: guest NX capability removed\n");
1830 }
1831}
1832
07716717 1833/* when an old userspace process fills a new kernel module */
313a3dc7
CO		 1834static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
1835 struct kvm_cpuid *cpuid,
1836 struct kvm_cpuid_entry __user *entries)
07716717
DK		 1837{
1838 int r, i;
1839 struct kvm_cpuid_entry *cpuid_entries;
1840
1841 r = -E2BIG;
1842 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1843 goto out;
1844 r = -ENOMEM;
1845 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent);
1846 if (!cpuid_entries)
1847 goto out;
1848 r = -EFAULT;
1849 if (copy_from_user(cpuid_entries, entries,
1850 cpuid->nent * sizeof(struct kvm_cpuid_entry)))
1851 goto out_free;
1852 for (i = 0; i < cpuid->nent; i++) {
ad312c7c
ZX		 1853 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
1854 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
1855 vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx;
1856 vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx;
1857 vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx;
1858 vcpu->arch.cpuid_entries[i].index = 0;
1859 vcpu->arch.cpuid_entries[i].flags = 0;
1860 vcpu->arch.cpuid_entries[i].padding[0] = 0;
1861 vcpu->arch.cpuid_entries[i].padding[1] = 0;
1862 vcpu->arch.cpuid_entries[i].padding[2] = 0;
1863 }
1864 vcpu->arch.cpuid_nent = cpuid->nent;
07716717
DK		 1865 cpuid_fix_nx_cap(vcpu);
1866 r = 0;
fc61b800 1867 kvm_apic_set_version(vcpu);
0e851880 1868 kvm_x86_ops->cpuid_update(vcpu);
2acf923e 1869 update_cpuid(vcpu);
07716717
DK		 1870
1871out_free:
1872 vfree(cpuid_entries);
1873out:
1874 return r;
1875}
1876
1877static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 1878 struct kvm_cpuid2 *cpuid,
1879 struct kvm_cpuid_entry2 __user *entries)
313a3dc7
CO		 1880{
1881 int r;
1882
1883 r = -E2BIG;
1884 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1885 goto out;
1886 r = -EFAULT;
ad312c7c 1887 if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
07716717 1888 cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
313a3dc7 1889 goto out;
ad312c7c 1890 vcpu->arch.cpuid_nent = cpuid->nent;
fc61b800 1891 kvm_apic_set_version(vcpu);
0e851880 1892 kvm_x86_ops->cpuid_update(vcpu);
2acf923e 1893 update_cpuid(vcpu);
313a3dc7
CO		 1894 return 0;
1895
1896out:
1897 return r;
1898}
1899
07716717 1900static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 1901 struct kvm_cpuid2 *cpuid,
1902 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 1903{
1904 int r;
1905
1906 r = -E2BIG;
ad312c7c 1907 if (cpuid->nent < vcpu->arch.cpuid_nent)
07716717
DK		 1908 goto out;
1909 r = -EFAULT;
ad312c7c 1910 if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
19355475 1911 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 1912 goto out;
1913 return 0;
1914
1915out:
ad312c7c 1916 cpuid->nent = vcpu->arch.cpuid_nent;
07716717
DK		 1917 return r;
1918}
1919
07716717 1920static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function,
19355475 1921 u32 index)
07716717
DK		 1922{
1923 entry->function = function;
1924 entry->index = index;
1925 cpuid_count(entry->function, entry->index,
19355475 1926 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
07716717
DK		 1927 entry->flags = 0;
1928}
1929
7faa4ee1
AK		 1930#define F(x) bit(X86_FEATURE_##x)
1931
07716717
DK		 1932static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
1933 u32 index, int *nent, int maxnent)
1934{
7faa4ee1 1935 unsigned f_nx = is_efer_nx() ? F(NX) : 0;
07716717 1936#ifdef CONFIG_X86_64
17cc3935
SY		 1937 unsigned f_gbpages = (kvm_x86_ops->get_lpage_level() == PT_PDPE_LEVEL)
1938 ? F(GBPAGES) : 0;
7faa4ee1
AK		 1939 unsigned f_lm = F(LM);
1940#else
17cc3935 1941 unsigned f_gbpages = 0;
7faa4ee1 1942 unsigned f_lm = 0;
07716717 1943#endif
4e47c7a6 1944 unsigned f_rdtscp = kvm_x86_ops->rdtscp_supported() ? F(RDTSCP) : 0;
7faa4ee1
AK		 1945
1946 /* cpuid 1.edx */
1947 const u32 kvm_supported_word0_x86_features =
1948 F(FPU) | F(VME) | F(DE) | F(PSE) |
1949 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
1950 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) |
1951 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
1952 F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLSH) |
1953 0 /* Reserved, DS, ACPI */ | F(MMX) |
1954 F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) |
1955 0 /* HTT, TM, Reserved, PBE */;
1956 /* cpuid 0x80000001.edx */
1957 const u32 kvm_supported_word1_x86_features =
1958 F(FPU) | F(VME) | F(DE) | F(PSE) |
1959 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
1960 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) |
1961 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
1962 F(PAT) | F(PSE36) | 0 /* Reserved */ |
1963 f_nx | 0 /* Reserved */ | F(MMXEXT) | F(MMX) |
4e47c7a6 1964 F(FXSR) | F(FXSR_OPT) | f_gbpages | f_rdtscp |
7faa4ee1
AK		 1965 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW);
1966 /* cpuid 1.ecx */
1967 const u32 kvm_supported_word4_x86_features =
d149c731
AK		 1968 F(XMM3) | 0 /* Reserved, DTES64, MONITOR */ |
1969 0 /* DS-CPL, VMX, SMX, EST */ |
1970 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ |
1971 0 /* Reserved */ | F(CX16) | 0 /* xTPR Update, PDCM */ |
1972 0 /* Reserved, DCA */ | F(XMM4_1) |
0105d1a5 1973 F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) |
2acf923e 1974 0 /* Reserved, AES */ | F(XSAVE) | 0 /* OSXSAVE */;
7faa4ee1 1975 /* cpuid 0x80000001.ecx */
07716717 1976 const u32 kvm_supported_word6_x86_features =
7faa4ee1
AK		 1977 F(LAHF_LM) | F(CMP_LEGACY) | F(SVM) | 0 /* ExtApicSpace */ |
1978 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) |
1979 F(3DNOWPREFETCH) | 0 /* OSVW */ | 0 /* IBS */ | F(SSE5) |
1980 0 /* SKINIT */ | 0 /* WDT */;
07716717 1981
19355475 1982 /* all calls to cpuid_count() should be made on the same cpu */
07716717
DK		 1983 get_cpu();
1984 do_cpuid_1_ent(entry, function, index);
1985 ++*nent;
1986
1987 switch (function) {
1988 case 0:
2acf923e 1989 entry->eax = min(entry->eax, (u32)0xd);
07716717
DK		 1990 break;
1991 case 1:
1992 entry->edx &= kvm_supported_word0_x86_features;
7faa4ee1 1993 entry->ecx &= kvm_supported_word4_x86_features;
0d1de2d9
GN		 1994 /* we support x2apic emulation even if host does not support
1995 * it since we emulate x2apic in software */
1996 entry->ecx |= F(X2APIC);
07716717
DK		 1997 break;
1998 /* function 2 entries are STATEFUL. That is, repeated cpuid commands
1999 * may return different values. This forces us to get_cpu() before
2000 * issuing the first command, and also to emulate this annoying behavior
2001 * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */
2002 case 2: {
2003 int t, times = entry->eax & 0xff;
2004
2005 entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
0fdf8e59 2006 entry->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
07716717
DK		 2007 for (t = 1; t < times && *nent < maxnent; ++t) {
2008 do_cpuid_1_ent(&entry[t], function, 0);
2009 entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
2010 ++*nent;
2011 }
2012 break;
2013 }
2014 /* function 4 and 0xb have additional index. */
2015 case 4: {
14af3f3c 2016 int i, cache_type;
07716717
DK		 2017
2018 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2019 /* read more entries until cache_type is zero */
14af3f3c
HH		 2020 for (i = 1; *nent < maxnent; ++i) {
2021 cache_type = entry[i - 1].eax & 0x1f;
07716717
DK		 2022 if (!cache_type)
2023 break;
14af3f3c
HH		 2024 do_cpuid_1_ent(&entry[i], function, i);
2025 entry[i].flags |=
07716717
DK		 2026 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2027 ++*nent;
2028 }
2029 break;
2030 }
2031 case 0xb: {
14af3f3c 2032 int i, level_type;
07716717
DK		 2033
2034 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2035 /* read more entries until level_type is zero */
14af3f3c 2036 for (i = 1; *nent < maxnent; ++i) {
0853d2c1 2037 level_type = entry[i - 1].ecx & 0xff00;
07716717
DK		 2038 if (!level_type)
2039 break;
14af3f3c
HH		 2040 do_cpuid_1_ent(&entry[i], function, i);
2041 entry[i].flags |=
07716717
DK		 2042 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2043 ++*nent;
2044 }
2045 break;
2046 }
2acf923e
DC		 2047 case 0xd: {
2048 int i;
2049
2050 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2051 for (i = 1; *nent < maxnent; ++i) {
2052 if (entry[i - 1].eax == 0 && i != 2)
2053 break;
2054 do_cpuid_1_ent(&entry[i], function, i);
2055 entry[i].flags |=
2056 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2057 ++*nent;
2058 }
2059 break;
2060 }
84478c82
GC		 2061 case KVM_CPUID_SIGNATURE: {
2062 char signature[12] = "KVMKVMKVM\0\0";
2063 u32 *sigptr = (u32 *)signature;
2064 entry->eax = 0;
2065 entry->ebx = sigptr[0];
2066 entry->ecx = sigptr[1];
2067 entry->edx = sigptr[2];
2068 break;
2069 }
2070 case KVM_CPUID_FEATURES:
2071 entry->eax = (1 << KVM_FEATURE_CLOCKSOURCE) |
2072 (1 << KVM_FEATURE_NOP_IO_DELAY) |
371bcf64
GC		 2073 (1 << KVM_FEATURE_CLOCKSOURCE2) |
2074 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT);
84478c82
GC		 2075 entry->ebx = 0;
2076 entry->ecx = 0;
2077 entry->edx = 0;
2078 break;
07716717
DK		 2079 case 0x80000000:
2080 entry->eax = min(entry->eax, 0x8000001a);
2081 break;
2082 case 0x80000001:
2083 entry->edx &= kvm_supported_word1_x86_features;
2084 entry->ecx &= kvm_supported_word6_x86_features;
2085 break;
2086 }
d4330ef2
JR		 2087
2088 kvm_x86_ops->set_supported_cpuid(function, entry);
2089
07716717
DK		 2090 put_cpu();
2091}
2092
7faa4ee1
AK		 2093#undef F
2094
674eea0f 2095static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
19355475 2096 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 2097{
2098 struct kvm_cpuid_entry2 *cpuid_entries;
2099 int limit, nent = 0, r = -E2BIG;
2100 u32 func;
2101
2102 if (cpuid->nent < 1)
2103 goto out;
6a544355
AK		 2104 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2105 cpuid->nent = KVM_MAX_CPUID_ENTRIES;
07716717
DK		 2106 r = -ENOMEM;
2107 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent);
2108 if (!cpuid_entries)
2109 goto out;
2110
2111 do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent);
2112 limit = cpuid_entries[0].eax;
2113 for (func = 1; func <= limit && nent < cpuid->nent; ++func)
2114 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 2115 &nent, cpuid->nent);
07716717
DK		 2116 r = -E2BIG;
2117 if (nent >= cpuid->nent)
2118 goto out_free;
2119
2120 do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent);
2121 limit = cpuid_entries[nent - 1].eax;
2122 for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func)
2123 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 2124 &nent, cpuid->nent);
84478c82
GC		 2125
2126
2127
2128 r = -E2BIG;
2129 if (nent >= cpuid->nent)
2130 goto out_free;
2131
2132 do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_SIGNATURE, 0, &nent,
2133 cpuid->nent);
2134
2135 r = -E2BIG;
2136 if (nent >= cpuid->nent)
2137 goto out_free;
2138
2139 do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_FEATURES, 0, &nent,
2140 cpuid->nent);
2141
cb007648
MM		 2142 r = -E2BIG;
2143 if (nent >= cpuid->nent)
2144 goto out_free;
2145
07716717
DK		 2146 r = -EFAULT;
2147 if (copy_to_user(entries, cpuid_entries,
19355475 2148 nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 2149 goto out_free;
2150 cpuid->nent = nent;
2151 r = 0;
2152
2153out_free:
2154 vfree(cpuid_entries);
2155out:
2156 return r;
2157}
2158
313a3dc7
CO		 2159static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2160 struct kvm_lapic_state *s)
2161{
ad312c7c 2162 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2163
2164 return 0;
2165}
2166
2167static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2168 struct kvm_lapic_state *s)
2169{
ad312c7c 2170 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
313a3dc7 2171 kvm_apic_post_state_restore(vcpu);
cb142eb7 2172 update_cr8_intercept(vcpu);
313a3dc7
CO		 2173
2174 return 0;
2175}
2176
f77bc6a4
ZX		 2177static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2178 struct kvm_interrupt *irq)
2179{
2180 if (irq->irq < 0 || irq->irq >= 256)
2181 return -EINVAL;
2182 if (irqchip_in_kernel(vcpu->kvm))
2183 return -ENXIO;
f77bc6a4 2184
66fd3f7f 2185 kvm_queue_interrupt(vcpu, irq->irq, false);
f77bc6a4 2186
f77bc6a4
ZX		 2187 return 0;
2188}
2189
c4abb7c9
JK		 2190static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2191{
c4abb7c9 2192 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2193
2194 return 0;
2195}
2196
b209749f
AK		 2197static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2198 struct kvm_tpr_access_ctl *tac)
2199{
2200 if (tac->flags)
2201 return -EINVAL;
2202 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2203 return 0;
2204}
2205
890ca9ae
HY		 2206static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2207 u64 mcg_cap)
2208{
2209 int r;
2210 unsigned bank_num = mcg_cap & 0xff, bank;
2211
2212 r = -EINVAL;
a9e38c3e 2213 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2214 goto out;
2215 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2216 goto out;
2217 r = 0;
2218 vcpu->arch.mcg_cap = mcg_cap;
2219 /* Init IA32_MCG_CTL to all 1s */
2220 if (mcg_cap & MCG_CTL_P)
2221 vcpu->arch.mcg_ctl = ~(u64)0;
2222 /* Init IA32_MCi_CTL to all 1s */
2223 for (bank = 0; bank < bank_num; bank++)
2224 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2225out:
2226 return r;
2227}
2228
2229static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2230 struct kvm_x86_mce *mce)
2231{
2232 u64 mcg_cap = vcpu->arch.mcg_cap;
2233 unsigned bank_num = mcg_cap & 0xff;
2234 u64 *banks = vcpu->arch.mce_banks;
2235
2236 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2237 return -EINVAL;
2238 /*
2239 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2240 * reporting is disabled
2241 */
2242 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2243 vcpu->arch.mcg_ctl != ~(u64)0)
2244 return 0;
2245 banks += 4 * mce->bank;
2246 /*
2247 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2248 * reporting is disabled for the bank
2249 */
2250 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2251 return 0;
2252 if (mce->status & MCI_STATUS_UC) {
2253 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2254 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
890ca9ae
HY		 2255 printk(KERN_DEBUG "kvm: set_mce: "
2256 "injects mce exception while "
2257 "previous one is in progress!\n");
2258 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
2259 return 0;
2260 }
2261 if (banks[1] & MCI_STATUS_VAL)
2262 mce->status |= MCI_STATUS_OVER;
2263 banks[2] = mce->addr;
2264 banks[3] = mce->misc;
2265 vcpu->arch.mcg_status = mce->mcg_status;
2266 banks[1] = mce->status;
2267 kvm_queue_exception(vcpu, MC_VECTOR);
2268 } else if (!(banks[1] & MCI_STATUS_VAL)
2269 || !(banks[1] & MCI_STATUS_UC)) {
2270 if (banks[1] & MCI_STATUS_VAL)
2271 mce->status |= MCI_STATUS_OVER;
2272 banks[2] = mce->addr;
2273 banks[3] = mce->misc;
2274 banks[1] = mce->status;
2275 } else
2276 banks[1] |= MCI_STATUS_OVER;
2277 return 0;
2278}
2279
3cfc3092
JK		 2280static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2281 struct kvm_vcpu_events *events)
2282{
03b82a30
JK		 2283 events->exception.injected =
2284 vcpu->arch.exception.pending &&
2285 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2286 events->exception.nr = vcpu->arch.exception.nr;
2287 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
2288 events->exception.error_code = vcpu->arch.exception.error_code;
2289
03b82a30
JK		 2290 events->interrupt.injected =
2291 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2292 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2293 events->interrupt.soft = 0;
48005f64
JK		 2294 events->interrupt.shadow =
2295 kvm_x86_ops->get_interrupt_shadow(vcpu,
2296 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
3cfc3092
JK		 2297
2298 events->nmi.injected = vcpu->arch.nmi_injected;
2299 events->nmi.pending = vcpu->arch.nmi_pending;
2300 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
2301
2302 events->sipi_vector = vcpu->arch.sipi_vector;
2303
dab4b911 2304 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2305 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2306 | KVM_VCPUEVENT_VALID_SHADOW);
3cfc3092
JK		 2307}
2308
2309static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2310 struct kvm_vcpu_events *events)
2311{
dab4b911 2312 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2313 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2314 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 2315 return -EINVAL;
2316
3cfc3092
JK		 2317 vcpu->arch.exception.pending = events->exception.injected;
2318 vcpu->arch.exception.nr = events->exception.nr;
2319 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2320 vcpu->arch.exception.error_code = events->exception.error_code;
2321
2322 vcpu->arch.interrupt.pending = events->interrupt.injected;
2323 vcpu->arch.interrupt.nr = events->interrupt.nr;
2324 vcpu->arch.interrupt.soft = events->interrupt.soft;
2325 if (vcpu->arch.interrupt.pending && irqchip_in_kernel(vcpu->kvm))
2326 kvm_pic_clear_isr_ack(vcpu->kvm);
48005f64
JK		 2327 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2328 kvm_x86_ops->set_interrupt_shadow(vcpu,
2329 events->interrupt.shadow);
3cfc3092
JK		 2330
2331 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2332 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2333 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2334 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2335
dab4b911
JK		 2336 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR)
2337 vcpu->arch.sipi_vector = events->sipi_vector;
3cfc3092 2338
3cfc3092
JK		 2339 return 0;
2340}
2341
a1efbe77
JK		 2342static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2343 struct kvm_debugregs *dbgregs)
2344{
a1efbe77
JK		 2345 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2346 dbgregs->dr6 = vcpu->arch.dr6;
2347 dbgregs->dr7 = vcpu->arch.dr7;
2348 dbgregs->flags = 0;
a1efbe77
JK		 2349}
2350
2351static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2352 struct kvm_debugregs *dbgregs)
2353{
2354 if (dbgregs->flags)
2355 return -EINVAL;
2356
a1efbe77
JK		 2357 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2358 vcpu->arch.dr6 = dbgregs->dr6;
2359 vcpu->arch.dr7 = dbgregs->dr7;
2360
a1efbe77
JK		 2361 return 0;
2362}
2363
313a3dc7
CO		 2364long kvm_arch_vcpu_ioctl(struct file *filp,
2365 unsigned int ioctl, unsigned long arg)
2366{
2367 struct kvm_vcpu *vcpu = filp->private_data;
2368 void __user *argp = (void __user *)arg;
2369 int r;
b772ff36 2370 struct kvm_lapic_state *lapic = NULL;
313a3dc7
CO		 2371
2372 switch (ioctl) {
2373 case KVM_GET_LAPIC: {
2204ae3c
MT		 2374 r = -EINVAL;
2375 if (!vcpu->arch.apic)
2376 goto out;
b772ff36 2377 lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 2378
b772ff36
DH		 2379 r = -ENOMEM;
2380 if (!lapic)
2381 goto out;
2382 r = kvm_vcpu_ioctl_get_lapic(vcpu, lapic);
313a3dc7
CO		 2383 if (r)
2384 goto out;
2385 r = -EFAULT;
b772ff36 2386 if (copy_to_user(argp, lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 2387 goto out;
2388 r = 0;
2389 break;
2390 }
2391 case KVM_SET_LAPIC: {
2204ae3c
MT		 2392 r = -EINVAL;
2393 if (!vcpu->arch.apic)
2394 goto out;
b772ff36
DH		 2395 lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
2396 r = -ENOMEM;
2397 if (!lapic)
2398 goto out;
313a3dc7 2399 r = -EFAULT;
b772ff36 2400 if (copy_from_user(lapic, argp, sizeof(struct kvm_lapic_state)))
313a3dc7 2401 goto out;
b772ff36 2402 r = kvm_vcpu_ioctl_set_lapic(vcpu, lapic);
313a3dc7
CO		 2403 if (r)
2404 goto out;
2405 r = 0;
2406 break;
2407 }
f77bc6a4
ZX		 2408 case KVM_INTERRUPT: {
2409 struct kvm_interrupt irq;
2410
2411 r = -EFAULT;
2412 if (copy_from_user(&irq, argp, sizeof irq))
2413 goto out;
2414 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
2415 if (r)
2416 goto out;
2417 r = 0;
2418 break;
2419 }
c4abb7c9
JK		 2420 case KVM_NMI: {
2421 r = kvm_vcpu_ioctl_nmi(vcpu);
2422 if (r)
2423 goto out;
2424 r = 0;
2425 break;
2426 }
313a3dc7
CO		 2427 case KVM_SET_CPUID: {
2428 struct kvm_cpuid __user *cpuid_arg = argp;
2429 struct kvm_cpuid cpuid;
2430
2431 r = -EFAULT;
2432 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2433 goto out;
2434 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
2435 if (r)
2436 goto out;
2437 break;
2438 }
07716717
DK		 2439 case KVM_SET_CPUID2: {
2440 struct kvm_cpuid2 __user *cpuid_arg = argp;
2441 struct kvm_cpuid2 cpuid;
2442
2443 r = -EFAULT;
2444 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2445 goto out;
2446 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 2447 cpuid_arg->entries);
07716717
DK		 2448 if (r)
2449 goto out;
2450 break;
2451 }
2452 case KVM_GET_CPUID2: {
2453 struct kvm_cpuid2 __user *cpuid_arg = argp;
2454 struct kvm_cpuid2 cpuid;
2455
2456 r = -EFAULT;
2457 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2458 goto out;
2459 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 2460 cpuid_arg->entries);
07716717
DK		 2461 if (r)
2462 goto out;
2463 r = -EFAULT;
2464 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2465 goto out;
2466 r = 0;
2467 break;
2468 }
313a3dc7
CO		 2469 case KVM_GET_MSRS:
2470 r = msr_io(vcpu, argp, kvm_get_msr, 1);
2471 break;
2472 case KVM_SET_MSRS:
2473 r = msr_io(vcpu, argp, do_set_msr, 0);
2474 break;
b209749f
AK		 2475 case KVM_TPR_ACCESS_REPORTING: {
2476 struct kvm_tpr_access_ctl tac;
2477
2478 r = -EFAULT;
2479 if (copy_from_user(&tac, argp, sizeof tac))
2480 goto out;
2481 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
2482 if (r)
2483 goto out;
2484 r = -EFAULT;
2485 if (copy_to_user(argp, &tac, sizeof tac))
2486 goto out;
2487 r = 0;
2488 break;
2489 };
b93463aa
AK		 2490 case KVM_SET_VAPIC_ADDR: {
2491 struct kvm_vapic_addr va;
2492
2493 r = -EINVAL;
2494 if (!irqchip_in_kernel(vcpu->kvm))
2495 goto out;
2496 r = -EFAULT;
2497 if (copy_from_user(&va, argp, sizeof va))
2498 goto out;
2499 r = 0;
2500 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
2501 break;
2502 }
890ca9ae
HY		 2503 case KVM_X86_SETUP_MCE: {
2504 u64 mcg_cap;
2505
2506 r = -EFAULT;
2507 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
2508 goto out;
2509 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
2510 break;
2511 }
2512 case KVM_X86_SET_MCE: {
2513 struct kvm_x86_mce mce;
2514
2515 r = -EFAULT;
2516 if (copy_from_user(&mce, argp, sizeof mce))
2517 goto out;
2518 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
2519 break;
2520 }
3cfc3092
JK		 2521 case KVM_GET_VCPU_EVENTS: {
2522 struct kvm_vcpu_events events;
2523
2524 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
2525
2526 r = -EFAULT;
2527 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
2528 break;
2529 r = 0;
2530 break;
2531 }
2532 case KVM_SET_VCPU_EVENTS: {
2533 struct kvm_vcpu_events events;
2534
2535 r = -EFAULT;
2536 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
2537 break;
2538
2539 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
2540 break;
2541 }
a1efbe77
JK		 2542 case KVM_GET_DEBUGREGS: {
2543 struct kvm_debugregs dbgregs;
2544
2545 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
2546
2547 r = -EFAULT;
2548 if (copy_to_user(argp, &dbgregs,
2549 sizeof(struct kvm_debugregs)))
2550 break;
2551 r = 0;
2552 break;
2553 }
2554 case KVM_SET_DEBUGREGS: {
2555 struct kvm_debugregs dbgregs;
2556
2557 r = -EFAULT;
2558 if (copy_from_user(&dbgregs, argp,
2559 sizeof(struct kvm_debugregs)))
2560 break;
2561
2562 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
2563 break;
2564 }
313a3dc7
CO		 2565 default:
2566 r = -EINVAL;
2567 }
2568out:
7a6ce84c 2569 kfree(lapic);
313a3dc7
CO		 2570 return r;
2571}
2572
1fe779f8
CO		 2573static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
2574{
2575 int ret;
2576
2577 if (addr > (unsigned int)(-3 * PAGE_SIZE))
2578 return -1;
2579 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
2580 return ret;
2581}
2582
b927a3ce
SY		 2583static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
2584 u64 ident_addr)
2585{
2586 kvm->arch.ept_identity_map_addr = ident_addr;
2587 return 0;
2588}
2589
1fe779f8
CO		 2590static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
2591 u32 kvm_nr_mmu_pages)
2592{
2593 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
2594 return -EINVAL;
2595
79fac95e 2596 mutex_lock(&kvm->slots_lock);
7c8a83b7 2597 spin_lock(&kvm->mmu_lock);
1fe779f8
CO		 2598
2599 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 2600 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 2601
7c8a83b7 2602 spin_unlock(&kvm->mmu_lock);
79fac95e 2603 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 2604 return 0;
2605}
2606
2607static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
2608{
f05e70ac 2609 return kvm->arch.n_alloc_mmu_pages;
1fe779f8
CO		 2610}
2611
a983fb23
MT		 2612gfn_t unalias_gfn_instantiation(struct kvm *kvm, gfn_t gfn)
2613{
2614 int i;
2615 struct kvm_mem_alias *alias;
2616 struct kvm_mem_aliases *aliases;
2617
90d83dc3 2618 aliases = kvm_aliases(kvm);
a983fb23
MT		 2619
2620 for (i = 0; i < aliases->naliases; ++i) {
2621 alias = &aliases->aliases[i];
2622 if (alias->flags & KVM_ALIAS_INVALID)
2623 continue;
2624 if (gfn >= alias->base_gfn
2625 && gfn < alias->base_gfn + alias->npages)
2626 return alias->target_gfn + gfn - alias->base_gfn;
2627 }
2628 return gfn;
2629}
2630
e9f85cde
ZX		 2631gfn_t unalias_gfn(struct kvm *kvm, gfn_t gfn)
2632{
2633 int i;
2634 struct kvm_mem_alias *alias;
a983fb23
MT		 2635 struct kvm_mem_aliases *aliases;
2636
90d83dc3 2637 aliases = kvm_aliases(kvm);
e9f85cde 2638
fef9cce0
MT		 2639 for (i = 0; i < aliases->naliases; ++i) {
2640 alias = &aliases->aliases[i];
e9f85cde
ZX		 2641 if (gfn >= alias->base_gfn
2642 && gfn < alias->base_gfn + alias->npages)
2643 return alias->target_gfn + gfn - alias->base_gfn;
2644 }
2645 return gfn;
2646}
2647
1fe779f8
CO		 2648/*
2649 * Set a new alias region. Aliases map a portion of physical memory into
2650 * another portion. This is useful for memory windows, for example the PC
2651 * VGA region.
2652 */
2653static int kvm_vm_ioctl_set_memory_alias(struct kvm *kvm,
2654 struct kvm_memory_alias *alias)
2655{
2656 int r, n;
2657 struct kvm_mem_alias *p;
a983fb23 2658 struct kvm_mem_aliases *aliases, *old_aliases;
1fe779f8
CO		 2659
2660 r = -EINVAL;
2661 /* General sanity checks */
2662 if (alias->memory_size & (PAGE_SIZE - 1))
2663 goto out;
2664 if (alias->guest_phys_addr & (PAGE_SIZE - 1))
2665 goto out;
2666 if (alias->slot >= KVM_ALIAS_SLOTS)
2667 goto out;
2668 if (alias->guest_phys_addr + alias->memory_size
2669 < alias->guest_phys_addr)
2670 goto out;
2671 if (alias->target_phys_addr + alias->memory_size
2672 < alias->target_phys_addr)
2673 goto out;
2674
a983fb23
MT		 2675 r = -ENOMEM;
2676 aliases = kzalloc(sizeof(struct kvm_mem_aliases), GFP_KERNEL);
2677 if (!aliases)
2678 goto out;
2679
79fac95e 2680 mutex_lock(&kvm->slots_lock);
1fe779f8 2681
a983fb23
MT		 2682 /* invalidate any gfn reference in case of deletion/shrinking */
2683 memcpy(aliases, kvm->arch.aliases, sizeof(struct kvm_mem_aliases));
2684 aliases->aliases[alias->slot].flags |= KVM_ALIAS_INVALID;
2685 old_aliases = kvm->arch.aliases;
2686 rcu_assign_pointer(kvm->arch.aliases, aliases);
2687 synchronize_srcu_expedited(&kvm->srcu);
2688 kvm_mmu_zap_all(kvm);
2689 kfree(old_aliases);
2690
2691 r = -ENOMEM;
2692 aliases = kzalloc(sizeof(struct kvm_mem_aliases), GFP_KERNEL);
2693 if (!aliases)
2694 goto out_unlock;
2695
2696 memcpy(aliases, kvm->arch.aliases, sizeof(struct kvm_mem_aliases));
fef9cce0
MT		 2697
2698 p = &aliases->aliases[alias->slot];
1fe779f8
CO		 2699 p->base_gfn = alias->guest_phys_addr >> PAGE_SHIFT;
2700 p->npages = alias->memory_size >> PAGE_SHIFT;
2701 p->target_gfn = alias->target_phys_addr >> PAGE_SHIFT;
a983fb23 2702 p->flags &= ~(KVM_ALIAS_INVALID);
1fe779f8
CO		 2703
2704 for (n = KVM_ALIAS_SLOTS; n > 0; --n)
fef9cce0 2705 if (aliases->aliases[n - 1].npages)
1fe779f8 2706 break;
fef9cce0 2707 aliases->naliases = n;
1fe779f8 2708
a983fb23
MT		 2709 old_aliases = kvm->arch.aliases;
2710 rcu_assign_pointer(kvm->arch.aliases, aliases);
2711 synchronize_srcu_expedited(&kvm->srcu);
2712 kfree(old_aliases);
2713 r = 0;
1fe779f8 2714
a983fb23 2715out_unlock:
79fac95e 2716 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 2717out:
2718 return r;
2719}
2720
2721static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2722{
2723 int r;
2724
2725 r = 0;
2726 switch (chip->chip_id) {
2727 case KVM_IRQCHIP_PIC_MASTER:
2728 memcpy(&chip->chip.pic,
2729 &pic_irqchip(kvm)->pics[0],
2730 sizeof(struct kvm_pic_state));
2731 break;
2732 case KVM_IRQCHIP_PIC_SLAVE:
2733 memcpy(&chip->chip.pic,
2734 &pic_irqchip(kvm)->pics[1],
2735 sizeof(struct kvm_pic_state));
2736 break;
2737 case KVM_IRQCHIP_IOAPIC:
eba0226b 2738 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 2739 break;
2740 default:
2741 r = -EINVAL;
2742 break;
2743 }
2744 return r;
2745}
2746
2747static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2748{
2749 int r;
2750
2751 r = 0;
2752 switch (chip->chip_id) {
2753 case KVM_IRQCHIP_PIC_MASTER:
fa8273e9 2754 raw_spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2755 memcpy(&pic_irqchip(kvm)->pics[0],
2756 &chip->chip.pic,
2757 sizeof(struct kvm_pic_state));
fa8273e9 2758 raw_spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2759 break;
2760 case KVM_IRQCHIP_PIC_SLAVE:
fa8273e9 2761 raw_spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2762 memcpy(&pic_irqchip(kvm)->pics[1],
2763 &chip->chip.pic,
2764 sizeof(struct kvm_pic_state));
fa8273e9 2765 raw_spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2766 break;
2767 case KVM_IRQCHIP_IOAPIC:
eba0226b 2768 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 2769 break;
2770 default:
2771 r = -EINVAL;
2772 break;
2773 }
2774 kvm_pic_update_irq(pic_irqchip(kvm));
2775 return r;
2776}
2777
e0f63cb9
SY		 2778static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2779{
2780 int r = 0;
2781
894a9c55 2782 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 2783 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 2784 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 2785 return r;
2786}
2787
2788static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2789{
2790 int r = 0;
2791
894a9c55 2792 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 2793 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 2794 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
2795 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2796 return r;
2797}
2798
2799static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
2800{
2801 int r = 0;
2802
2803 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2804 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
2805 sizeof(ps->channels));
2806 ps->flags = kvm->arch.vpit->pit_state.flags;
2807 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2808 return r;
2809}
2810
2811static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
2812{
2813 int r = 0, start = 0;
2814 u32 prev_legacy, cur_legacy;
2815 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2816 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
2817 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
2818 if (!prev_legacy && cur_legacy)
2819 start = 1;
2820 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
2821 sizeof(kvm->arch.vpit->pit_state.channels));
2822 kvm->arch.vpit->pit_state.flags = ps->flags;
2823 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 2824 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 2825 return r;
2826}
2827
52d939a0
MT		 2828static int kvm_vm_ioctl_reinject(struct kvm *kvm,
2829 struct kvm_reinject_control *control)
2830{
2831 if (!kvm->arch.vpit)
2832 return -ENXIO;
894a9c55 2833 mutex_lock(&kvm->arch.vpit->pit_state.lock);
52d939a0 2834 kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject;
894a9c55 2835 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 2836 return 0;
2837}
2838
5bb064dc
ZX		 2839/*
2840 * Get (and clear) the dirty memory log for a memory slot.
2841 */
2842int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
2843 struct kvm_dirty_log *log)
2844{
87bf6e7d 2845 int r, i;
5bb064dc 2846 struct kvm_memory_slot *memslot;
87bf6e7d 2847 unsigned long n;
b050b015 2848 unsigned long is_dirty = 0;
5bb064dc 2849
79fac95e 2850 mutex_lock(&kvm->slots_lock);
5bb064dc 2851
b050b015
MT		 2852 r = -EINVAL;
2853 if (log->slot >= KVM_MEMORY_SLOTS)
2854 goto out;
2855
2856 memslot = &kvm->memslots->memslots[log->slot];
2857 r = -ENOENT;
2858 if (!memslot->dirty_bitmap)
2859 goto out;
2860
87bf6e7d 2861 n = kvm_dirty_bitmap_bytes(memslot);
b050b015 2862
b050b015
MT		 2863 for (i = 0; !is_dirty && i < n/sizeof(long); i++)
2864 is_dirty = memslot->dirty_bitmap[i];
5bb064dc
ZX		 2865
2866 /* If nothing is dirty, don't bother messing with page tables. */
2867 if (is_dirty) {
b050b015 2868 struct kvm_memslots *slots, *old_slots;
914ebccd 2869 unsigned long *dirty_bitmap;
b050b015 2870
7c8a83b7 2871 spin_lock(&kvm->mmu_lock);
5bb064dc 2872 kvm_mmu_slot_remove_write_access(kvm, log->slot);
7c8a83b7 2873 spin_unlock(&kvm->mmu_lock);
b050b015 2874
914ebccd
TY		 2875 r = -ENOMEM;
2876 dirty_bitmap = vmalloc(n);
2877 if (!dirty_bitmap)
2878 goto out;
2879 memset(dirty_bitmap, 0, n);
b050b015 2880
914ebccd
TY		 2881 r = -ENOMEM;
2882 slots = kzalloc(sizeof(struct kvm_memslots), GFP_KERNEL);
2883 if (!slots) {
2884 vfree(dirty_bitmap);
2885 goto out;
2886 }
b050b015
MT		 2887 memcpy(slots, kvm->memslots, sizeof(struct kvm_memslots));
2888 slots->memslots[log->slot].dirty_bitmap = dirty_bitmap;
2889
2890 old_slots = kvm->memslots;
2891 rcu_assign_pointer(kvm->memslots, slots);
2892 synchronize_srcu_expedited(&kvm->srcu);
2893 dirty_bitmap = old_slots->memslots[log->slot].dirty_bitmap;
2894 kfree(old_slots);
914ebccd
TY		 2895
2896 r = -EFAULT;
2897 if (copy_to_user(log->dirty_bitmap, dirty_bitmap, n)) {
2898 vfree(dirty_bitmap);
2899 goto out;
2900 }
2901 vfree(dirty_bitmap);
2902 } else {
2903 r = -EFAULT;
2904 if (clear_user(log->dirty_bitmap, n))
2905 goto out;
5bb064dc 2906 }
b050b015 2907
5bb064dc
ZX		 2908 r = 0;
2909out:
79fac95e 2910 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 2911 return r;
2912}
2913
1fe779f8
CO		 2914long kvm_arch_vm_ioctl(struct file *filp,
2915 unsigned int ioctl, unsigned long arg)
2916{
2917 struct kvm *kvm = filp->private_data;
2918 void __user *argp = (void __user *)arg;
367e1319 2919 int r = -ENOTTY;
f0d66275
DH		 2920 /*
2921 * This union makes it completely explicit to gcc-3.x
2922 * that these two variables' stack usage should be
2923 * combined, not added together.
2924 */
2925 union {
2926 struct kvm_pit_state ps;
e9f42757 2927 struct kvm_pit_state2 ps2;
f0d66275 2928 struct kvm_memory_alias alias;
c5ff41ce 2929 struct kvm_pit_config pit_config;
f0d66275 2930 } u;
1fe779f8
CO		 2931
2932 switch (ioctl) {
2933 case KVM_SET_TSS_ADDR:
2934 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
2935 if (r < 0)
2936 goto out;
2937 break;
b927a3ce
SY		 2938 case KVM_SET_IDENTITY_MAP_ADDR: {
2939 u64 ident_addr;
2940
2941 r = -EFAULT;
2942 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
2943 goto out;
2944 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
2945 if (r < 0)
2946 goto out;
2947 break;
2948 }
1fe779f8
CO		 2949 case KVM_SET_MEMORY_REGION: {
2950 struct kvm_memory_region kvm_mem;
2951 struct kvm_userspace_memory_region kvm_userspace_mem;
2952
2953 r = -EFAULT;
2954 if (copy_from_user(&kvm_mem, argp, sizeof kvm_mem))
2955 goto out;
2956 kvm_userspace_mem.slot = kvm_mem.slot;
2957 kvm_userspace_mem.flags = kvm_mem.flags;
2958 kvm_userspace_mem.guest_phys_addr = kvm_mem.guest_phys_addr;
2959 kvm_userspace_mem.memory_size = kvm_mem.memory_size;
2960 r = kvm_vm_ioctl_set_memory_region(kvm, &kvm_userspace_mem, 0);
2961 if (r)
2962 goto out;
2963 break;
2964 }
2965 case KVM_SET_NR_MMU_PAGES:
2966 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
2967 if (r)
2968 goto out;
2969 break;
2970 case KVM_GET_NR_MMU_PAGES:
2971 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
2972 break;
f0d66275 2973 case KVM_SET_MEMORY_ALIAS:
1fe779f8 2974 r = -EFAULT;
f0d66275 2975 if (copy_from_user(&u.alias, argp, sizeof(struct kvm_memory_alias)))
1fe779f8 2976 goto out;
f0d66275 2977 r = kvm_vm_ioctl_set_memory_alias(kvm, &u.alias);
1fe779f8
CO		 2978 if (r)
2979 goto out;
2980 break;
3ddea128
MT		 2981 case KVM_CREATE_IRQCHIP: {
2982 struct kvm_pic *vpic;
2983
2984 mutex_lock(&kvm->lock);
2985 r = -EEXIST;
2986 if (kvm->arch.vpic)
2987 goto create_irqchip_unlock;
1fe779f8 2988 r = -ENOMEM;
3ddea128
MT		 2989 vpic = kvm_create_pic(kvm);
2990 if (vpic) {
1fe779f8
CO		 2991 r = kvm_ioapic_init(kvm);
2992 if (r) {
72bb2fcd
WY		 2993 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
2994 &vpic->dev);
3ddea128
MT		 2995 kfree(vpic);
2996 goto create_irqchip_unlock;
1fe779f8
CO		 2997 }
2998 } else
3ddea128
MT		 2999 goto create_irqchip_unlock;
3000 smp_wmb();
3001 kvm->arch.vpic = vpic;
3002 smp_wmb();
399ec807
AK		 3003 r = kvm_setup_default_irq_routing(kvm);
3004 if (r) {
3ddea128 3005 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 3006 kvm_ioapic_destroy(kvm);
3007 kvm_destroy_pic(kvm);
3ddea128 3008 mutex_unlock(&kvm->irq_lock);
399ec807 3009 }
3ddea128
MT		 3010 create_irqchip_unlock:
3011 mutex_unlock(&kvm->lock);
1fe779f8 3012 break;
3ddea128 3013 }
7837699f 3014 case KVM_CREATE_PIT:
c5ff41ce
JK		 3015 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3016 goto create_pit;
3017 case KVM_CREATE_PIT2:
3018 r = -EFAULT;
3019 if (copy_from_user(&u.pit_config, argp,
3020 sizeof(struct kvm_pit_config)))
3021 goto out;
3022 create_pit:
79fac95e 3023 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3024 r = -EEXIST;
3025 if (kvm->arch.vpit)
3026 goto create_pit_unlock;
7837699f 3027 r = -ENOMEM;
c5ff41ce 3028 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3029 if (kvm->arch.vpit)
3030 r = 0;
269e05e4 3031 create_pit_unlock:
79fac95e 3032 mutex_unlock(&kvm->slots_lock);
7837699f 3033 break;
4925663a 3034 case KVM_IRQ_LINE_STATUS:
1fe779f8
CO		 3035 case KVM_IRQ_LINE: {
3036 struct kvm_irq_level irq_event;
3037
3038 r = -EFAULT;
3039 if (copy_from_user(&irq_event, argp, sizeof irq_event))
3040 goto out;
160d2f6c 3041 r = -ENXIO;
1fe779f8 3042 if (irqchip_in_kernel(kvm)) {
4925663a 3043 __s32 status;
4925663a
GN		 3044 status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3045 irq_event.irq, irq_event.level);
4925663a 3046 if (ioctl == KVM_IRQ_LINE_STATUS) {
160d2f6c 3047 r = -EFAULT;
4925663a
GN		 3048 irq_event.status = status;
3049 if (copy_to_user(argp, &irq_event,
3050 sizeof irq_event))
3051 goto out;
3052 }
1fe779f8
CO		 3053 r = 0;
3054 }
3055 break;
3056 }
3057 case KVM_GET_IRQCHIP: {
3058 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 3059 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 3060
f0d66275
DH		 3061 r = -ENOMEM;
3062 if (!chip)
1fe779f8 3063 goto out;
f0d66275
DH		 3064 r = -EFAULT;
3065 if (copy_from_user(chip, argp, sizeof *chip))
3066 goto get_irqchip_out;
1fe779f8
CO		 3067 r = -ENXIO;
3068 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3069 goto get_irqchip_out;
3070 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3071 if (r)
f0d66275 3072 goto get_irqchip_out;
1fe779f8 3073 r = -EFAULT;
f0d66275
DH		 3074 if (copy_to_user(argp, chip, sizeof *chip))
3075 goto get_irqchip_out;
1fe779f8 3076 r = 0;
f0d66275
DH		 3077 get_irqchip_out:
3078 kfree(chip);
3079 if (r)
3080 goto out;
1fe779f8
CO		 3081 break;
3082 }
3083 case KVM_SET_IRQCHIP: {
3084 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 3085 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 3086
f0d66275
DH		 3087 r = -ENOMEM;
3088 if (!chip)
1fe779f8 3089 goto out;
f0d66275
DH		 3090 r = -EFAULT;
3091 if (copy_from_user(chip, argp, sizeof *chip))
3092 goto set_irqchip_out;
1fe779f8
CO		 3093 r = -ENXIO;
3094 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3095 goto set_irqchip_out;
3096 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3097 if (r)
f0d66275 3098 goto set_irqchip_out;
1fe779f8 3099 r = 0;
f0d66275
DH		 3100 set_irqchip_out:
3101 kfree(chip);
3102 if (r)
3103 goto out;
1fe779f8
CO		 3104 break;
3105 }
e0f63cb9 3106 case KVM_GET_PIT: {
e0f63cb9 3107 r = -EFAULT;
f0d66275 3108 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3109 goto out;
3110 r = -ENXIO;
3111 if (!kvm->arch.vpit)
3112 goto out;
f0d66275 3113 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3114 if (r)
3115 goto out;
3116 r = -EFAULT;
f0d66275 3117 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3118 goto out;
3119 r = 0;
3120 break;
3121 }
3122 case KVM_SET_PIT: {
e0f63cb9 3123 r = -EFAULT;
f0d66275 3124 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3125 goto out;
3126 r = -ENXIO;
3127 if (!kvm->arch.vpit)
3128 goto out;
f0d66275 3129 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3130 if (r)
3131 goto out;
3132 r = 0;
3133 break;
3134 }
e9f42757
BK		 3135 case KVM_GET_PIT2: {
3136 r = -ENXIO;
3137 if (!kvm->arch.vpit)
3138 goto out;
3139 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3140 if (r)
3141 goto out;
3142 r = -EFAULT;
3143 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3144 goto out;
3145 r = 0;
3146 break;
3147 }
3148 case KVM_SET_PIT2: {
3149 r = -EFAULT;
3150 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3151 goto out;
3152 r = -ENXIO;
3153 if (!kvm->arch.vpit)
3154 goto out;
3155 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
3156 if (r)
3157 goto out;
3158 r = 0;
3159 break;
3160 }
52d939a0
MT		 3161 case KVM_REINJECT_CONTROL: {
3162 struct kvm_reinject_control control;
3163 r = -EFAULT;
3164 if (copy_from_user(&control, argp, sizeof(control)))
3165 goto out;
3166 r = kvm_vm_ioctl_reinject(kvm, &control);
3167 if (r)
3168 goto out;
3169 r = 0;
3170 break;
3171 }
ffde22ac
ES		 3172 case KVM_XEN_HVM_CONFIG: {
3173 r = -EFAULT;
3174 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3175 sizeof(struct kvm_xen_hvm_config)))
3176 goto out;
3177 r = -EINVAL;
3178 if (kvm->arch.xen_hvm_config.flags)
3179 goto out;
3180 r = 0;
3181 break;
3182 }
afbcf7ab
GC		 3183 case KVM_SET_CLOCK: {
3184 struct timespec now;
3185 struct kvm_clock_data user_ns;
3186 u64 now_ns;
3187 s64 delta;
3188
3189 r = -EFAULT;
3190 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3191 goto out;
3192
3193 r = -EINVAL;
3194 if (user_ns.flags)
3195 goto out;
3196
3197 r = 0;
3198 ktime_get_ts(&now);
3199 now_ns = timespec_to_ns(&now);
3200 delta = user_ns.clock - now_ns;
3201 kvm->arch.kvmclock_offset = delta;
3202 break;
3203 }
3204 case KVM_GET_CLOCK: {
3205 struct timespec now;
3206 struct kvm_clock_data user_ns;
3207 u64 now_ns;
3208
3209 ktime_get_ts(&now);
3210 now_ns = timespec_to_ns(&now);
3211 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
3212 user_ns.flags = 0;
3213
3214 r = -EFAULT;
3215 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3216 goto out;
3217 r = 0;
3218 break;
3219 }
3220
1fe779f8
CO		 3221 default:
3222 ;
3223 }
3224out:
3225 return r;
3226}
3227
a16b043c 3228static void kvm_init_msr_list(void)
043405e1
CO		 3229{
3230 u32 dummy[2];
3231 unsigned i, j;
3232
e3267cbb
GC		 3233 /* skip the first msrs in the list. KVM-specific */
3234 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3235 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3236 continue;
3237 if (j < i)
3238 msrs_to_save[j] = msrs_to_save[i];
3239 j++;
3240 }
3241 num_msrs_to_save = j;
3242}
3243
bda9020e
MT		 3244static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3245 const void *v)
bbd9b64e 3246{
bda9020e
MT		 3247 if (vcpu->arch.apic &&
3248 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, len, v))
3249 return 0;
bbd9b64e 3250
e93f8a0f 3251 return kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, len, v);
bbd9b64e
CO		 3252}
3253
bda9020e 3254static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 3255{
bda9020e
MT		 3256 if (vcpu->arch.apic &&
3257 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, len, v))
3258 return 0;
bbd9b64e 3259
e93f8a0f 3260 return kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, len, v);
bbd9b64e
CO		 3261}
3262
2dafc6c2
GN		 3263static void kvm_set_segment(struct kvm_vcpu *vcpu,
3264 struct kvm_segment *var, int seg)
3265{
3266 kvm_x86_ops->set_segment(vcpu, var, seg);
3267}
3268
3269void kvm_get_segment(struct kvm_vcpu *vcpu,
3270 struct kvm_segment *var, int seg)
3271{
3272 kvm_x86_ops->get_segment(vcpu, var, seg);
3273}
3274
1871c602
GN		 3275gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3276{
3277 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3278 return vcpu->arch.mmu.gva_to_gpa(vcpu, gva, access, error);
3279}
3280
3281 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3282{
3283 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3284 access |= PFERR_FETCH_MASK;
3285 return vcpu->arch.mmu.gva_to_gpa(vcpu, gva, access, error);
3286}
3287
3288gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3289{
3290 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3291 access |= PFERR_WRITE_MASK;
3292 return vcpu->arch.mmu.gva_to_gpa(vcpu, gva, access, error);
3293}
3294
3295/* uses this to access any guest's mapped memory without checking CPL */
3296gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3297{
3298 return vcpu->arch.mmu.gva_to_gpa(vcpu, gva, 0, error);
3299}
3300
3301static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3302 struct kvm_vcpu *vcpu, u32 access,
3303 u32 *error)
bbd9b64e
CO		 3304{
3305 void *data = val;
10589a46 3306 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 3307
3308 while (bytes) {
1871c602 3309 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr, access, error);
bbd9b64e 3310 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 3311 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 3312 int ret;
3313
10589a46
MT		 3314 if (gpa == UNMAPPED_GVA) {
3315 r = X86EMUL_PROPAGATE_FAULT;
3316 goto out;
3317 }
77c2002e 3318 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46 3319 if (ret < 0) {
c3cd7ffa 3320 r = X86EMUL_IO_NEEDED;
10589a46
MT		 3321 goto out;
3322 }
bbd9b64e 3323
77c2002e
IE		 3324 bytes -= toread;
3325 data += toread;
3326 addr += toread;
bbd9b64e 3327 }
10589a46 3328out:
10589a46 3329 return r;
bbd9b64e 3330}
77c2002e 3331
1871c602
GN		 3332/* used for instruction fetching */
3333static int kvm_fetch_guest_virt(gva_t addr, void *val, unsigned int bytes,
3334 struct kvm_vcpu *vcpu, u32 *error)
3335{
3336 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3337 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
3338 access | PFERR_FETCH_MASK, error);
3339}
3340
3341static int kvm_read_guest_virt(gva_t addr, void *val, unsigned int bytes,
3342 struct kvm_vcpu *vcpu, u32 *error)
3343{
3344 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3345 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
3346 error);
3347}
3348
3349static int kvm_read_guest_virt_system(gva_t addr, void *val, unsigned int bytes,
3350 struct kvm_vcpu *vcpu, u32 *error)
3351{
3352 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, error);
3353}
3354
7972995b 3355static int kvm_write_guest_virt_system(gva_t addr, void *val,
2dafc6c2 3356 unsigned int bytes,
7972995b 3357 struct kvm_vcpu *vcpu,
2dafc6c2 3358 u32 *error)
77c2002e
IE		 3359{
3360 void *data = val;
3361 int r = X86EMUL_CONTINUE;
3362
3363 while (bytes) {
7972995b
GN		 3364 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr,
3365 PFERR_WRITE_MASK, error);
77c2002e
IE		 3366 unsigned offset = addr & (PAGE_SIZE-1);
3367 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
3368 int ret;
3369
3370 if (gpa == UNMAPPED_GVA) {
3371 r = X86EMUL_PROPAGATE_FAULT;
3372 goto out;
3373 }
3374 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
3375 if (ret < 0) {
c3cd7ffa 3376 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 3377 goto out;
3378 }
3379
3380 bytes -= towrite;
3381 data += towrite;
3382 addr += towrite;
3383 }
3384out:
3385 return r;
3386}
3387
bbd9b64e
CO		 3388static int emulator_read_emulated(unsigned long addr,
3389 void *val,
3390 unsigned int bytes,
8fe681e9 3391 unsigned int *error_code,
bbd9b64e
CO		 3392 struct kvm_vcpu *vcpu)
3393{
bbd9b64e
CO		 3394 gpa_t gpa;
3395
3396 if (vcpu->mmio_read_completed) {
3397 memcpy(val, vcpu->mmio_data, bytes);
aec51dc4
AK		 3398 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
3399 vcpu->mmio_phys_addr, *(u64 *)val);
bbd9b64e
CO		 3400 vcpu->mmio_read_completed = 0;
3401 return X86EMUL_CONTINUE;
3402 }
3403
8fe681e9 3404 gpa = kvm_mmu_gva_to_gpa_read(vcpu, addr, error_code);
1871c602 3405
8fe681e9 3406 if (gpa == UNMAPPED_GVA)
1871c602 3407 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 3408
3409 /* For APIC access vmexit */
3410 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3411 goto mmio;
3412
1871c602 3413 if (kvm_read_guest_virt(addr, val, bytes, vcpu, NULL)
77c2002e 3414 == X86EMUL_CONTINUE)
bbd9b64e 3415 return X86EMUL_CONTINUE;
bbd9b64e
CO		 3416
3417mmio:
3418 /*
3419 * Is this MMIO handled locally?
3420 */
aec51dc4
AK		 3421 if (!vcpu_mmio_read(vcpu, gpa, bytes, val)) {
3422 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 3423 return X86EMUL_CONTINUE;
3424 }
aec51dc4
AK		 3425
3426 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
bbd9b64e
CO		 3427
3428 vcpu->mmio_needed = 1;
411c35b7
GN		 3429 vcpu->run->exit_reason = KVM_EXIT_MMIO;
3430 vcpu->run->mmio.phys_addr = vcpu->mmio_phys_addr = gpa;
3431 vcpu->run->mmio.len = vcpu->mmio_size = bytes;
3432 vcpu->run->mmio.is_write = vcpu->mmio_is_write = 0;
bbd9b64e 3433
c3cd7ffa 3434 return X86EMUL_IO_NEEDED;
bbd9b64e
CO		 3435}
3436
3200f405 3437int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
9f811285 3438 const void *val, int bytes)
bbd9b64e
CO		 3439{
3440 int ret;
3441
3442 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 3443 if (ret < 0)
bbd9b64e 3444 return 0;
ad218f85 3445 kvm_mmu_pte_write(vcpu, gpa, val, bytes, 1);
bbd9b64e
CO		 3446 return 1;
3447}
3448
3449static int emulator_write_emulated_onepage(unsigned long addr,
3450 const void *val,
3451 unsigned int bytes,
8fe681e9 3452 unsigned int *error_code,
bbd9b64e
CO		 3453 struct kvm_vcpu *vcpu)
3454{
10589a46
MT		 3455 gpa_t gpa;
3456
8fe681e9 3457 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, error_code);
bbd9b64e 3458
8fe681e9 3459 if (gpa == UNMAPPED_GVA)
bbd9b64e 3460 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 3461
3462 /* For APIC access vmexit */
3463 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3464 goto mmio;
3465
3466 if (emulator_write_phys(vcpu, gpa, val, bytes))
3467 return X86EMUL_CONTINUE;
3468
3469mmio:
aec51dc4 3470 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 3471 /*
3472 * Is this MMIO handled locally?
3473 */
bda9020e 3474 if (!vcpu_mmio_write(vcpu, gpa, bytes, val))
bbd9b64e 3475 return X86EMUL_CONTINUE;
bbd9b64e
CO		 3476
3477 vcpu->mmio_needed = 1;
411c35b7
GN		 3478 vcpu->run->exit_reason = KVM_EXIT_MMIO;
3479 vcpu->run->mmio.phys_addr = vcpu->mmio_phys_addr = gpa;
3480 vcpu->run->mmio.len = vcpu->mmio_size = bytes;
3481 vcpu->run->mmio.is_write = vcpu->mmio_is_write = 1;
3482 memcpy(vcpu->run->mmio.data, val, bytes);
bbd9b64e
CO		 3483
3484 return X86EMUL_CONTINUE;
3485}
3486
3487int emulator_write_emulated(unsigned long addr,
8f6abd06
GN		 3488 const void *val,
3489 unsigned int bytes,
8fe681e9 3490 unsigned int *error_code,
8f6abd06 3491 struct kvm_vcpu *vcpu)
bbd9b64e
CO		 3492{
3493 /* Crossing a page boundary? */
3494 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
3495 int rc, now;
3496
3497 now = -addr & ~PAGE_MASK;
8fe681e9
GN		 3498 rc = emulator_write_emulated_onepage(addr, val, now, error_code,
3499 vcpu);
bbd9b64e
CO		 3500 if (rc != X86EMUL_CONTINUE)
3501 return rc;
3502 addr += now;
3503 val += now;
3504 bytes -= now;
3505 }
8fe681e9
GN		 3506 return emulator_write_emulated_onepage(addr, val, bytes, error_code,
3507 vcpu);
bbd9b64e 3508}
bbd9b64e 3509
daea3e73
AK		 3510#define CMPXCHG_TYPE(t, ptr, old, new) \
3511 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
3512
3513#ifdef CONFIG_X86_64
3514# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
3515#else
3516# define CMPXCHG64(ptr, old, new) \
9749a6c0 3517 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 3518#endif
3519
bbd9b64e
CO		 3520static int emulator_cmpxchg_emulated(unsigned long addr,
3521 const void *old,
3522 const void *new,
3523 unsigned int bytes,
8fe681e9 3524 unsigned int *error_code,
bbd9b64e
CO		 3525 struct kvm_vcpu *vcpu)
3526{
daea3e73
AK		 3527 gpa_t gpa;
3528 struct page *page;
3529 char *kaddr;
3530 bool exchanged;
2bacc55c 3531
daea3e73
AK		 3532 /* guests cmpxchg8b have to be emulated atomically */
3533 if (bytes > 8 || (bytes & (bytes - 1)))
3534 goto emul_write;
10589a46 3535
daea3e73 3536 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 3537
daea3e73
AK		 3538 if (gpa == UNMAPPED_GVA ||
3539 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3540 goto emul_write;
2bacc55c 3541
daea3e73
AK		 3542 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
3543 goto emul_write;
72dc67a6 3544
daea3e73 3545 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
72dc67a6 3546
daea3e73
AK		 3547 kaddr = kmap_atomic(page, KM_USER0);
3548 kaddr += offset_in_page(gpa);
3549 switch (bytes) {
3550 case 1:
3551 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
3552 break;
3553 case 2:
3554 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
3555 break;
3556 case 4:
3557 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
3558 break;
3559 case 8:
3560 exchanged = CMPXCHG64(kaddr, old, new);
3561 break;
3562 default:
3563 BUG();
2bacc55c 3564 }
daea3e73
AK		 3565 kunmap_atomic(kaddr, KM_USER0);
3566 kvm_release_page_dirty(page);
3567
3568 if (!exchanged)
3569 return X86EMUL_CMPXCHG_FAILED;
3570
8f6abd06
GN		 3571 kvm_mmu_pte_write(vcpu, gpa, new, bytes, 1);
3572
3573 return X86EMUL_CONTINUE;
4a5f48f6 3574
3200f405 3575emul_write:
daea3e73 3576 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 3577
8fe681e9 3578 return emulator_write_emulated(addr, new, bytes, error_code, vcpu);
bbd9b64e
CO		 3579}
3580
cf8f70bf
GN		 3581static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
3582{
3583 /* TODO: String I/O for in kernel device */
3584 int r;
3585
3586 if (vcpu->arch.pio.in)
3587 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
3588 vcpu->arch.pio.size, pd);
3589 else
3590 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
3591 vcpu->arch.pio.port, vcpu->arch.pio.size,
3592 pd);
3593 return r;
3594}
3595
3596
3597static int emulator_pio_in_emulated(int size, unsigned short port, void *val,
3598 unsigned int count, struct kvm_vcpu *vcpu)
3599{
7972995b 3600 if (vcpu->arch.pio.count)
cf8f70bf
GN		 3601 goto data_avail;
3602
3603 trace_kvm_pio(1, port, size, 1);
3604
3605 vcpu->arch.pio.port = port;
3606 vcpu->arch.pio.in = 1;
7972995b 3607 vcpu->arch.pio.count = count;
cf8f70bf
GN		 3608 vcpu->arch.pio.size = size;
3609
3610 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
3611 data_avail:
3612 memcpy(val, vcpu->arch.pio_data, size * count);
7972995b 3613 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 3614 return 1;
3615 }
3616
3617 vcpu->run->exit_reason = KVM_EXIT_IO;
3618 vcpu->run->io.direction = KVM_EXIT_IO_IN;
3619 vcpu->run->io.size = size;
3620 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
3621 vcpu->run->io.count = count;
3622 vcpu->run->io.port = port;
3623
3624 return 0;
3625}
3626
3627static int emulator_pio_out_emulated(int size, unsigned short port,
3628 const void *val, unsigned int count,
3629 struct kvm_vcpu *vcpu)
3630{
3631 trace_kvm_pio(0, port, size, 1);
3632
3633 vcpu->arch.pio.port = port;
3634 vcpu->arch.pio.in = 0;
7972995b 3635 vcpu->arch.pio.count = count;
cf8f70bf
GN		 3636 vcpu->arch.pio.size = size;
3637
3638 memcpy(vcpu->arch.pio_data, val, size * count);
3639
3640 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 3641 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 3642 return 1;
3643 }
3644
3645 vcpu->run->exit_reason = KVM_EXIT_IO;
3646 vcpu->run->io.direction = KVM_EXIT_IO_OUT;
3647 vcpu->run->io.size = size;
3648 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
3649 vcpu->run->io.count = count;
3650 vcpu->run->io.port = port;
3651
3652 return 0;
3653}
3654
bbd9b64e
CO		 3655static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
3656{
3657 return kvm_x86_ops->get_segment_base(vcpu, seg);
3658}
3659
3660int emulate_invlpg(struct kvm_vcpu *vcpu, gva_t address)
3661{
a7052897 3662 kvm_mmu_invlpg(vcpu, address);
bbd9b64e
CO		 3663 return X86EMUL_CONTINUE;
3664}
3665
3666int emulate_clts(struct kvm_vcpu *vcpu)
3667{
4d4ec087 3668 kvm_x86_ops->set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
6b52d186 3669 kvm_x86_ops->fpu_activate(vcpu);
bbd9b64e
CO		 3670 return X86EMUL_CONTINUE;
3671}
3672
35aa5375 3673int emulator_get_dr(int dr, unsigned long *dest, struct kvm_vcpu *vcpu)
bbd9b64e 3674{
338dbc97 3675 return _kvm_get_dr(vcpu, dr, dest);
bbd9b64e
CO		 3676}
3677
35aa5375 3678int emulator_set_dr(int dr, unsigned long value, struct kvm_vcpu *vcpu)
bbd9b64e 3679{
338dbc97
GN		 3680
3681 return __kvm_set_dr(vcpu, dr, value);
bbd9b64e
CO		 3682}
3683
52a46617 3684static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 3685{
52a46617 3686 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 3687}
3688
52a46617 3689static unsigned long emulator_get_cr(int cr, struct kvm_vcpu *vcpu)
bbd9b64e 3690{
52a46617
GN		 3691 unsigned long value;
3692
3693 switch (cr) {
3694 case 0:
3695 value = kvm_read_cr0(vcpu);
3696 break;
3697 case 2:
3698 value = vcpu->arch.cr2;
3699 break;
3700 case 3:
3701 value = vcpu->arch.cr3;
3702 break;
3703 case 4:
3704 value = kvm_read_cr4(vcpu);
3705 break;
3706 case 8:
3707 value = kvm_get_cr8(vcpu);
3708 break;
3709 default:
3710 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
3711 return 0;
3712 }
3713
3714 return value;
3715}
3716
0f12244f 3717static int emulator_set_cr(int cr, unsigned long val, struct kvm_vcpu *vcpu)
52a46617 3718{
0f12244f
GN		 3719 int res = 0;
3720
52a46617
GN		 3721 switch (cr) {
3722 case 0:
49a9b07e 3723 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 3724 break;
3725 case 2:
3726 vcpu->arch.cr2 = val;
3727 break;
3728 case 3:
0f12244f 3729 res = __kvm_set_cr3(vcpu, val);
52a46617
GN		 3730 break;
3731 case 4:
a83b29c6 3732 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 3733 break;
3734 case 8:
0f12244f 3735 res = __kvm_set_cr8(vcpu, val & 0xfUL);
52a46617
GN		 3736 break;
3737 default:
3738 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
0f12244f 3739 res = -1;
52a46617 3740 }
0f12244f
GN		 3741
3742 return res;
52a46617
GN		 3743}
3744
9c537244
GN		 3745static int emulator_get_cpl(struct kvm_vcpu *vcpu)
3746{
3747 return kvm_x86_ops->get_cpl(vcpu);
3748}
3749
2dafc6c2
GN		 3750static void emulator_get_gdt(struct desc_ptr *dt, struct kvm_vcpu *vcpu)
3751{
3752 kvm_x86_ops->get_gdt(vcpu, dt);
3753}
3754
5951c442
GN		 3755static unsigned long emulator_get_cached_segment_base(int seg,
3756 struct kvm_vcpu *vcpu)
3757{
3758 return get_segment_base(vcpu, seg);
3759}
3760
2dafc6c2
GN		 3761static bool emulator_get_cached_descriptor(struct desc_struct *desc, int seg,
3762 struct kvm_vcpu *vcpu)
3763{
3764 struct kvm_segment var;
3765
3766 kvm_get_segment(vcpu, &var, seg);
3767
3768 if (var.unusable)
3769 return false;
3770
3771 if (var.g)
3772 var.limit >>= 12;
3773 set_desc_limit(desc, var.limit);
3774 set_desc_base(desc, (unsigned long)var.base);
3775 desc->type = var.type;
3776 desc->s = var.s;
3777 desc->dpl = var.dpl;
3778 desc->p = var.present;
3779 desc->avl = var.avl;
3780 desc->l = var.l;
3781 desc->d = var.db;
3782 desc->g = var.g;
3783
3784 return true;
3785}
3786
3787static void emulator_set_cached_descriptor(struct desc_struct *desc, int seg,
3788 struct kvm_vcpu *vcpu)
3789{
3790 struct kvm_segment var;
3791
3792 /* needed to preserve selector */
3793 kvm_get_segment(vcpu, &var, seg);
3794
3795 var.base = get_desc_base(desc);
3796 var.limit = get_desc_limit(desc);
3797 if (desc->g)
3798 var.limit = (var.limit << 12) | 0xfff;
3799 var.type = desc->type;
3800 var.present = desc->p;
3801 var.dpl = desc->dpl;
3802 var.db = desc->d;
3803 var.s = desc->s;
3804 var.l = desc->l;
3805 var.g = desc->g;
3806 var.avl = desc->avl;
3807 var.present = desc->p;
3808 var.unusable = !var.present;
3809 var.padding = 0;
3810
3811 kvm_set_segment(vcpu, &var, seg);
3812 return;
3813}
3814
3815static u16 emulator_get_segment_selector(int seg, struct kvm_vcpu *vcpu)
3816{
3817 struct kvm_segment kvm_seg;
3818
3819 kvm_get_segment(vcpu, &kvm_seg, seg);
3820 return kvm_seg.selector;
3821}
3822
3823static void emulator_set_segment_selector(u16 sel, int seg,
3824 struct kvm_vcpu *vcpu)
3825{
3826 struct kvm_segment kvm_seg;
3827
3828 kvm_get_segment(vcpu, &kvm_seg, seg);
3829 kvm_seg.selector = sel;
3830 kvm_set_segment(vcpu, &kvm_seg, seg);
3831}
3832
14af3f3c 3833static struct x86_emulate_ops emulate_ops = {
1871c602 3834 .read_std = kvm_read_guest_virt_system,
2dafc6c2 3835 .write_std = kvm_write_guest_virt_system,
1871c602 3836 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 3837 .read_emulated = emulator_read_emulated,
3838 .write_emulated = emulator_write_emulated,
3839 .cmpxchg_emulated = emulator_cmpxchg_emulated,
cf8f70bf
GN		 3840 .pio_in_emulated = emulator_pio_in_emulated,
3841 .pio_out_emulated = emulator_pio_out_emulated,
2dafc6c2
GN		 3842 .get_cached_descriptor = emulator_get_cached_descriptor,
3843 .set_cached_descriptor = emulator_set_cached_descriptor,
3844 .get_segment_selector = emulator_get_segment_selector,
3845 .set_segment_selector = emulator_set_segment_selector,
5951c442 3846 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 3847 .get_gdt = emulator_get_gdt,
52a46617
GN		 3848 .get_cr = emulator_get_cr,
3849 .set_cr = emulator_set_cr,
9c537244 3850 .cpl = emulator_get_cpl,
35aa5375
GN		 3851 .get_dr = emulator_get_dr,
3852 .set_dr = emulator_set_dr,
3fb1b5db
GN		 3853 .set_msr = kvm_set_msr,
3854 .get_msr = kvm_get_msr,
bbd9b64e
CO		 3855};
3856
5fdbf976
MT		 3857static void cache_all_regs(struct kvm_vcpu *vcpu)
3858{
3859 kvm_register_read(vcpu, VCPU_REGS_RAX);
3860 kvm_register_read(vcpu, VCPU_REGS_RSP);
3861 kvm_register_read(vcpu, VCPU_REGS_RIP);
3862 vcpu->arch.regs_dirty = ~0;
3863}
3864
95cb2295
GN		 3865static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
3866{
3867 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
3868 /*
3869 * an sti; sti; sequence only disable interrupts for the first
3870 * instruction. So, if the last instruction, be it emulated or
3871 * not, left the system with the INT_STI flag enabled, it
3872 * means that the last instruction is an sti. We should not
3873 * leave the flag on in this case. The same goes for mov ss
3874 */
3875 if (!(int_shadow & mask))
3876 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
3877}
3878
54b8486f
GN		 3879static void inject_emulated_exception(struct kvm_vcpu *vcpu)
3880{
3881 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
3882 if (ctxt->exception == PF_VECTOR)
3883 kvm_inject_page_fault(vcpu, ctxt->cr2, ctxt->error_code);
3884 else if (ctxt->error_code_valid)
3885 kvm_queue_exception_e(vcpu, ctxt->exception, ctxt->error_code);
3886 else
3887 kvm_queue_exception(vcpu, ctxt->exception);
3888}
3889
6d77dbfc
GN		 3890static int handle_emulation_failure(struct kvm_vcpu *vcpu)
3891{
6d77dbfc
GN		 3892 ++vcpu->stat.insn_emulation_fail;
3893 trace_kvm_emulate_insn_failed(vcpu);
3894 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3895 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
3896 vcpu->run->internal.ndata = 0;
3897 kvm_queue_exception(vcpu, UD_VECTOR);
3898 return EMULATE_FAIL;
3899}
3900
bbd9b64e 3901int emulate_instruction(struct kvm_vcpu *vcpu,
bbd9b64e
CO		 3902 unsigned long cr2,
3903 u16 error_code,
571008da 3904 int emulation_type)
bbd9b64e 3905{
95cb2295 3906 int r;
4d2179e1 3907 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
bbd9b64e 3908
26eef70c 3909 kvm_clear_exception_queue(vcpu);
ad312c7c 3910 vcpu->arch.mmio_fault_cr2 = cr2;
5fdbf976 3911 /*
56e82318 3912 * TODO: fix emulate.c to use guest_read/write_register
5fdbf976
MT		 3913 * instead of direct ->regs accesses, can save hundred cycles
3914 * on Intel for instructions that don't read/change RSP, for
3915 * for example.
3916 */
3917 cache_all_regs(vcpu);
bbd9b64e 3918
571008da 3919 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
bbd9b64e
CO		 3920 int cs_db, cs_l;
3921 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
3922
ad312c7c 3923 vcpu->arch.emulate_ctxt.vcpu = vcpu;
83bf0002 3924 vcpu->arch.emulate_ctxt.eflags = kvm_x86_ops->get_rflags(vcpu);
063db061 3925 vcpu->arch.emulate_ctxt.eip = kvm_rip_read(vcpu);
ad312c7c 3926 vcpu->arch.emulate_ctxt.mode =
a0044755 3927 (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
ad312c7c 3928 (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM)
a0044755 3929 ? X86EMUL_MODE_VM86 : cs_l
bbd9b64e
CO		 3930 ? X86EMUL_MODE_PROT64 : cs_db
3931 ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
4d2179e1
GN		 3932 memset(c, 0, sizeof(struct decode_cache));
3933 memcpy(c->regs, vcpu->arch.regs, sizeof c->regs);
95cb2295 3934 vcpu->arch.emulate_ctxt.interruptibility = 0;
54b8486f 3935 vcpu->arch.emulate_ctxt.exception = -1;
bbd9b64e 3936
ad312c7c 3937 r = x86_decode_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
e46479f8 3938 trace_kvm_emulate_insn_start(vcpu);
571008da 3939
0cb5762e
AP		 3940 /* Only allow emulation of specific instructions on #UD
3941 * (namely VMMCALL, sysenter, sysexit, syscall)*/
0cb5762e
AP		 3942 if (emulation_type & EMULTYPE_TRAP_UD) {
3943 if (!c->twobyte)
3944 return EMULATE_FAIL;
3945 switch (c->b) {
3946 case 0x01: /* VMMCALL */
3947 if (c->modrm_mod != 3 || c->modrm_rm != 1)
3948 return EMULATE_FAIL;
3949 break;
3950 case 0x34: /* sysenter */
3951 case 0x35: /* sysexit */
3952 if (c->modrm_mod != 0 || c->modrm_rm != 0)
3953 return EMULATE_FAIL;
3954 break;
3955 case 0x05: /* syscall */
3956 if (c->modrm_mod != 0 || c->modrm_rm != 0)
3957 return EMULATE_FAIL;
3958 break;
3959 default:
3960 return EMULATE_FAIL;
3961 }
3962
3963 if (!(c->modrm_reg == 0 || c->modrm_reg == 3))
3964 return EMULATE_FAIL;
3965 }
571008da 3966
f2b5756b 3967 ++vcpu->stat.insn_emulation;
bbd9b64e
CO		 3968 if (r) {
3969 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
3970 return EMULATE_DONE;
6d77dbfc
GN		 3971 if (emulation_type & EMULTYPE_SKIP)
3972 return EMULATE_FAIL;
3973 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 3974 }
3975 }
3976
ba8afb6b
GN		 3977 if (emulation_type & EMULTYPE_SKIP) {
3978 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.decode.eip);
3979 return EMULATE_DONE;
3980 }
3981
4d2179e1
GN		 3982 /* this is needed for vmware backdor interface to work since it
3983 changes registers values during IO operation */
3984 memcpy(c->regs, vcpu->arch.regs, sizeof c->regs);
3985
5cd21917 3986restart:
ad312c7c 3987 r = x86_emulate_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
bbd9b64e 3988
c3cd7ffa
GN		 3989 if (r) { /* emulation failed */
3990 /*
3991 * if emulation was due to access to shadowed page table
3992 * and it failed try to unshadow page and re-entetr the
3993 * guest to let CPU execute the instruction.
3994 */
3995 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
3996 return EMULATE_DONE;
3997
6d77dbfc 3998 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 3999 }
4000
95cb2295 4001 toggle_interruptibility(vcpu, vcpu->arch.emulate_ctxt.interruptibility);
ef050dc0 4002 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
4d2179e1 4003 memcpy(vcpu->arch.regs, c->regs, sizeof c->regs);
95c55886 4004 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.eip);
3457e419 4005
54b8486f
GN		 4006 if (vcpu->arch.emulate_ctxt.exception >= 0) {
4007 inject_emulated_exception(vcpu);
4008 return EMULATE_DONE;
4009 }
4010
3457e419
GN		 4011 if (vcpu->arch.pio.count) {
4012 if (!vcpu->arch.pio.in)
4013 vcpu->arch.pio.count = 0;
4014 return EMULATE_DO_MMIO;
4015 }
4016
4017 if (vcpu->mmio_needed) {
4018 if (vcpu->mmio_is_write)
4019 vcpu->mmio_needed = 0;
4020 return EMULATE_DO_MMIO;
4021 }
4022
5cd21917
GN		 4023 if (vcpu->arch.emulate_ctxt.restart)
4024 goto restart;
f850e2e6 4025
bbd9b64e 4026 return EMULATE_DONE;
de7d789a 4027}
bbd9b64e 4028EXPORT_SYMBOL_GPL(emulate_instruction);
de7d789a 4029
cf8f70bf 4030int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 4031{
cf8f70bf
GN		 4032 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
4033 int ret = emulator_pio_out_emulated(size, port, &val, 1, vcpu);
4034 /* do not return to emulator after return from userspace */
7972995b 4035 vcpu->arch.pio.count = 0;
de7d789a
CO		 4036 return ret;
4037}
cf8f70bf 4038EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 4039
c8076604
GH		 4040static void bounce_off(void *info)
4041{
4042 /* nothing */
4043}
4044
c8076604
GH		 4045static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
4046 void *data)
4047{
4048 struct cpufreq_freqs *freq = data;
4049 struct kvm *kvm;
4050 struct kvm_vcpu *vcpu;
4051 int i, send_ipi = 0;
4052
c8076604
GH		 4053 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
4054 return 0;
4055 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
4056 return 0;
0cca7907 4057 per_cpu(cpu_tsc_khz, freq->cpu) = freq->new;
c8076604
GH		 4058
4059 spin_lock(&kvm_lock);
4060 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 4061 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 4062 if (vcpu->cpu != freq->cpu)
4063 continue;
4064 if (!kvm_request_guest_time_update(vcpu))
4065 continue;
4066 if (vcpu->cpu != smp_processor_id())
4067 send_ipi++;
4068 }
4069 }
4070 spin_unlock(&kvm_lock);
4071
4072 if (freq->old < freq->new && send_ipi) {
4073 /*
4074 * We upscale the frequency. Must make the guest
4075 * doesn't see old kvmclock values while running with
4076 * the new frequency, otherwise we risk the guest sees
4077 * time go backwards.
4078 *
4079 * In case we update the frequency for another cpu
4080 * (which might be in guest context) send an interrupt
4081 * to kick the cpu out of guest context. Next time
4082 * guest context is entered kvmclock will be updated,
4083 * so the guest will not see stale values.
4084 */
4085 smp_call_function_single(freq->cpu, bounce_off, NULL, 1);
4086 }
4087 return 0;
4088}
4089
4090static struct notifier_block kvmclock_cpufreq_notifier_block = {
4091 .notifier_call = kvmclock_cpufreq_notifier
4092};
4093
b820cc0c
ZA		 4094static void kvm_timer_init(void)
4095{
4096 int cpu;
4097
b820cc0c 4098 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
b820cc0c
ZA		 4099 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
4100 CPUFREQ_TRANSITION_NOTIFIER);
6b7d7e76
ZA		 4101 for_each_online_cpu(cpu) {
4102 unsigned long khz = cpufreq_get(cpu);
4103 if (!khz)
4104 khz = tsc_khz;
4105 per_cpu(cpu_tsc_khz, cpu) = khz;
4106 }
0cca7907
ZA		 4107 } else {
4108 for_each_possible_cpu(cpu)
4109 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
b820cc0c
ZA		 4110 }
4111}
4112
ff9d07a0
ZY		 4113static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
4114
4115static int kvm_is_in_guest(void)
4116{
4117 return percpu_read(current_vcpu) != NULL;
4118}
4119
4120static int kvm_is_user_mode(void)
4121{
4122 int user_mode = 3;
dcf46b94 4123
ff9d07a0
ZY		 4124 if (percpu_read(current_vcpu))
4125 user_mode = kvm_x86_ops->get_cpl(percpu_read(current_vcpu));
dcf46b94 4126
ff9d07a0
ZY		 4127 return user_mode != 0;
4128}
4129
4130static unsigned long kvm_get_guest_ip(void)
4131{
4132 unsigned long ip = 0;
dcf46b94 4133
ff9d07a0
ZY		 4134 if (percpu_read(current_vcpu))
4135 ip = kvm_rip_read(percpu_read(current_vcpu));
dcf46b94 4136
ff9d07a0
ZY		 4137 return ip;
4138}
4139
4140static struct perf_guest_info_callbacks kvm_guest_cbs = {
4141 .is_in_guest = kvm_is_in_guest,
4142 .is_user_mode = kvm_is_user_mode,
4143 .get_guest_ip = kvm_get_guest_ip,
4144};
4145
4146void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
4147{
4148 percpu_write(current_vcpu, vcpu);
4149}
4150EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
4151
4152void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
4153{
4154 percpu_write(current_vcpu, NULL);
4155}
4156EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
4157
f8c16bba 4158int kvm_arch_init(void *opaque)
043405e1 4159{
b820cc0c 4160 int r;
f8c16bba
ZX		 4161 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
4162
f8c16bba
ZX		 4163 if (kvm_x86_ops) {
4164 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 4165 r = -EEXIST;
4166 goto out;
f8c16bba
ZX		 4167 }
4168
4169 if (!ops->cpu_has_kvm_support()) {
4170 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 4171 r = -EOPNOTSUPP;
4172 goto out;
f8c16bba
ZX		 4173 }
4174 if (ops->disabled_by_bios()) {
4175 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 4176 r = -EOPNOTSUPP;
4177 goto out;
f8c16bba
ZX		 4178 }
4179
97db56ce
AK		 4180 r = kvm_mmu_module_init();
4181 if (r)
4182 goto out;
4183
4184 kvm_init_msr_list();
4185
f8c16bba 4186 kvm_x86_ops = ops;
56c6d28a 4187 kvm_mmu_set_nonpresent_ptes(0ull, 0ull);
7b52345e
SY		 4188 kvm_mmu_set_base_ptes(PT_PRESENT_MASK);
4189 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 4190 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 4191
b820cc0c 4192 kvm_timer_init();
c8076604 4193
ff9d07a0
ZY		 4194 perf_register_guest_info_callbacks(&kvm_guest_cbs);
4195
2acf923e
DC		 4196 if (cpu_has_xsave)
4197 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
4198
f8c16bba 4199 return 0;
56c6d28a
ZX		 4200
4201out:
56c6d28a 4202 return r;
043405e1 4203}
8776e519 4204
f8c16bba
ZX		 4205void kvm_arch_exit(void)
4206{
ff9d07a0
ZY		 4207 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
4208
888d256e
JK		 4209 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4210 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
4211 CPUFREQ_TRANSITION_NOTIFIER);
f8c16bba 4212 kvm_x86_ops = NULL;
56c6d28a
ZX		 4213 kvm_mmu_module_exit();
4214}
f8c16bba 4215
8776e519
HB		 4216int kvm_emulate_halt(struct kvm_vcpu *vcpu)
4217{
4218 ++vcpu->stat.halt_exits;
4219 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 4220 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 4221 return 1;
4222 } else {
4223 vcpu->run->exit_reason = KVM_EXIT_HLT;
4224 return 0;
4225 }
4226}
4227EXPORT_SYMBOL_GPL(kvm_emulate_halt);
4228
2f333bcb
MT		 4229static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0,
4230 unsigned long a1)
4231{
4232 if (is_long_mode(vcpu))
4233 return a0;
4234 else
4235 return a0 | ((gpa_t)a1 << 32);
4236}
4237
55cd8e5a
GN		 4238int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
4239{
4240 u64 param, ingpa, outgpa, ret;
4241 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
4242 bool fast, longmode;
4243 int cs_db, cs_l;
4244
4245 /*
4246 * hypercall generates UD from non zero cpl and real mode
4247 * per HYPER-V spec
4248 */
3eeb3288 4249 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 4250 kvm_queue_exception(vcpu, UD_VECTOR);
4251 return 0;
4252 }
4253
4254 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4255 longmode = is_long_mode(vcpu) && cs_l == 1;
4256
4257 if (!longmode) {
ccd46936
GN		 4258 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
4259 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
4260 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
4261 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
4262 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
4263 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 4264 }
4265#ifdef CONFIG_X86_64
4266 else {
4267 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
4268 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
4269 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
4270 }
4271#endif
4272
4273 code = param & 0xffff;
4274 fast = (param >> 16) & 0x1;
4275 rep_cnt = (param >> 32) & 0xfff;
4276 rep_idx = (param >> 48) & 0xfff;
4277
4278 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
4279
c25bc163
GN		 4280 switch (code) {
4281 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
4282 kvm_vcpu_on_spin(vcpu);
4283 break;
4284 default:
4285 res = HV_STATUS_INVALID_HYPERCALL_CODE;
4286 break;
4287 }
55cd8e5a
GN		 4288
4289 ret = res | (((u64)rep_done & 0xfff) << 32);
4290 if (longmode) {
4291 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
4292 } else {
4293 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
4294 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
4295 }
4296
4297 return 1;
4298}
4299
8776e519
HB		 4300int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
4301{
4302 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 4303 int r = 1;
8776e519 4304
55cd8e5a
GN		 4305 if (kvm_hv_hypercall_enabled(vcpu->kvm))
4306 return kvm_hv_hypercall(vcpu);
4307
5fdbf976
MT		 4308 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
4309 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
4310 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
4311 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
4312 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 4313
229456fc 4314 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 4315
8776e519
HB		 4316 if (!is_long_mode(vcpu)) {
4317 nr &= 0xFFFFFFFF;
4318 a0 &= 0xFFFFFFFF;
4319 a1 &= 0xFFFFFFFF;
4320 a2 &= 0xFFFFFFFF;
4321 a3 &= 0xFFFFFFFF;
4322 }
4323
07708c4a
JK		 4324 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
4325 ret = -KVM_EPERM;
4326 goto out;
4327 }
4328
8776e519 4329 switch (nr) {
b93463aa
AK		 4330 case KVM_HC_VAPIC_POLL_IRQ:
4331 ret = 0;
4332 break;
2f333bcb
MT		 4333 case KVM_HC_MMU_OP:
4334 r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret);
4335 break;
8776e519
HB		 4336 default:
4337 ret = -KVM_ENOSYS;
4338 break;
4339 }
07708c4a 4340out:
5fdbf976 4341 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 4342 ++vcpu->stat.hypercalls;
2f333bcb 4343 return r;
8776e519
HB		 4344}
4345EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
4346
4347int kvm_fix_hypercall(struct kvm_vcpu *vcpu)
4348{
4349 char instruction[3];
5fdbf976 4350 unsigned long rip = kvm_rip_read(vcpu);
8776e519 4351
8776e519
HB		 4352 /*
4353 * Blow out the MMU to ensure that no other VCPU has an active mapping
4354 * to ensure that the updated hypercall appears atomically across all
4355 * VCPUs.
4356 */
4357 kvm_mmu_zap_all(vcpu->kvm);
4358
8776e519 4359 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 4360
8fe681e9 4361 return emulator_write_emulated(rip, instruction, 3, NULL, vcpu);
8776e519
HB		 4362}
4363
8776e519
HB		 4364void realmode_lgdt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
4365{
89a27f4d 4366 struct desc_ptr dt = { limit, base };
8776e519
HB		 4367
4368 kvm_x86_ops->set_gdt(vcpu, &dt);
4369}
4370
4371void realmode_lidt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
4372{
89a27f4d 4373 struct desc_ptr dt = { limit, base };
8776e519
HB		 4374
4375 kvm_x86_ops->set_idt(vcpu, &dt);
4376}
4377
07716717
DK		 4378static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)
4379{
ad312c7c
ZX		 4380 struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];
4381 int j, nent = vcpu->arch.cpuid_nent;
07716717
DK		 4382
4383 e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;
4384 /* when no next entry is found, the current entry[i] is reselected */
0fdf8e59 4385 for (j = i + 1; ; j = (j + 1) % nent) {
ad312c7c 4386 struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j];
07716717
DK		 4387 if (ej->function == e->function) {
4388 ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
4389 return j;
4390 }
4391 }
4392 return 0; /* silence gcc, even though control never reaches here */
4393}
4394
4395/* find an entry with matching function, matching index (if needed), and that
4396 * should be read next (if it's stateful) */
4397static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e,
4398 u32 function, u32 index)
4399{
4400 if (e->function != function)
4401 return 0;
4402 if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index)
4403 return 0;
4404 if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) &&
19355475 4405 !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT))
07716717
DK		 4406 return 0;
4407 return 1;
4408}
4409
d8017474
AG		 4410struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
4411 u32 function, u32 index)
8776e519
HB		 4412{
4413 int i;
d8017474 4414 struct kvm_cpuid_entry2 *best = NULL;
8776e519 4415
ad312c7c 4416 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
d8017474
AG		 4417 struct kvm_cpuid_entry2 *e;
4418
ad312c7c 4419 e = &vcpu->arch.cpuid_entries[i];
07716717
DK		 4420 if (is_matching_cpuid_entry(e, function, index)) {
4421 if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC)
4422 move_to_next_stateful_cpuid_entry(vcpu, i);
8776e519
HB		 4423 best = e;
4424 break;
4425 }
4426 /*
4427 * Both basic or both extended?
4428 */
4429 if (((e->function ^ function) & 0x80000000) == 0)
4430 if (!best || e->function > best->function)
4431 best = e;
4432 }
d8017474
AG		 4433 return best;
4434}
0e851880 4435EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry);
d8017474 4436
82725b20
DE		 4437int cpuid_maxphyaddr(struct kvm_vcpu *vcpu)
4438{
4439 struct kvm_cpuid_entry2 *best;
4440
f7a71197
AK		 4441 best = kvm_find_cpuid_entry(vcpu, 0x80000000, 0);
4442 if (!best || best->eax < 0x80000008)
4443 goto not_found;
82725b20
DE		 4444 best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0);
4445 if (best)
4446 return best->eax & 0xff;
f7a71197 4447not_found:
82725b20
DE		 4448 return 36;
4449}
4450
d8017474
AG		 4451void kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
4452{
4453 u32 function, index;
4454 struct kvm_cpuid_entry2 *best;
4455
4456 function = kvm_register_read(vcpu, VCPU_REGS_RAX);
4457 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
4458 kvm_register_write(vcpu, VCPU_REGS_RAX, 0);
4459 kvm_register_write(vcpu, VCPU_REGS_RBX, 0);
4460 kvm_register_write(vcpu, VCPU_REGS_RCX, 0);
4461 kvm_register_write(vcpu, VCPU_REGS_RDX, 0);
4462 best = kvm_find_cpuid_entry(vcpu, function, index);
8776e519 4463 if (best) {
5fdbf976
MT		 4464 kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax);
4465 kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx);
4466 kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx);
4467 kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx);
8776e519 4468 }
8776e519 4469 kvm_x86_ops->skip_emulated_instruction(vcpu);
229456fc
MT		 4470 trace_kvm_cpuid(function,
4471 kvm_register_read(vcpu, VCPU_REGS_RAX),
4472 kvm_register_read(vcpu, VCPU_REGS_RBX),
4473 kvm_register_read(vcpu, VCPU_REGS_RCX),
4474 kvm_register_read(vcpu, VCPU_REGS_RDX));
8776e519
HB		 4475}
4476EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
d0752060 4477
b6c7a5dc
HB		 4478/*
4479 * Check if userspace requested an interrupt window, and that the
4480 * interrupt window is open.
4481 *
4482 * No need to exit to userspace if we already have an interrupt queued.
4483 */
851ba692 4484static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 4485{
8061823a 4486 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 4487 vcpu->run->request_interrupt_window &&
5df56646 4488 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 4489}
4490
851ba692 4491static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 4492{
851ba692
AK		 4493 struct kvm_run *kvm_run = vcpu->run;
4494
91586a3b 4495 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 4496 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 4497 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 4498 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 4499 kvm_run->ready_for_interrupt_injection = 1;
4531220b 4500 else
b6c7a5dc 4501 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 4502 kvm_arch_interrupt_allowed(vcpu) &&
4503 !kvm_cpu_has_interrupt(vcpu) &&
4504 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 4505}
4506
b93463aa
AK		 4507static void vapic_enter(struct kvm_vcpu *vcpu)
4508{
4509 struct kvm_lapic *apic = vcpu->arch.apic;
4510 struct page *page;
4511
4512 if (!apic || !apic->vapic_addr)
4513 return;
4514
4515 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
72dc67a6
IE		 4516
4517 vcpu->arch.apic->vapic_page = page;
b93463aa
AK		 4518}
4519
4520static void vapic_exit(struct kvm_vcpu *vcpu)
4521{
4522 struct kvm_lapic *apic = vcpu->arch.apic;
f656ce01 4523 int idx;
b93463aa
AK		 4524
4525 if (!apic || !apic->vapic_addr)
4526 return;
4527
f656ce01 4528 idx = srcu_read_lock(&vcpu->kvm->srcu);
b93463aa
AK		 4529 kvm_release_page_dirty(apic->vapic_page);
4530 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f656ce01 4531 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 4532}
4533
95ba8273
GN		 4534static void update_cr8_intercept(struct kvm_vcpu *vcpu)
4535{
4536 int max_irr, tpr;
4537
4538 if (!kvm_x86_ops->update_cr8_intercept)
4539 return;
4540
88c808fd
AK		 4541 if (!vcpu->arch.apic)
4542 return;
4543
8db3baa2
GN		 4544 if (!vcpu->arch.apic->vapic_addr)
4545 max_irr = kvm_lapic_find_highest_irr(vcpu);
4546 else
4547 max_irr = -1;
95ba8273
GN		 4548
4549 if (max_irr != -1)
4550 max_irr >>= 4;
4551
4552 tpr = kvm_lapic_get_cr8(vcpu);
4553
4554 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
4555}
4556
851ba692 4557static void inject_pending_event(struct kvm_vcpu *vcpu)
95ba8273
GN		 4558{
4559 /* try to reinject previous events if any */
b59bb7bd 4560 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 4561 trace_kvm_inj_exception(vcpu->arch.exception.nr,
4562 vcpu->arch.exception.has_error_code,
4563 vcpu->arch.exception.error_code);
b59bb7bd
GN		 4564 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
4565 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 4566 vcpu->arch.exception.error_code,
4567 vcpu->arch.exception.reinject);
b59bb7bd
GN		 4568 return;
4569 }
4570
95ba8273
GN		 4571 if (vcpu->arch.nmi_injected) {
4572 kvm_x86_ops->set_nmi(vcpu);
4573 return;
4574 }
4575
4576 if (vcpu->arch.interrupt.pending) {
66fd3f7f 4577 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 4578 return;
4579 }
4580
4581 /* try to inject new event if pending */
4582 if (vcpu->arch.nmi_pending) {
4583 if (kvm_x86_ops->nmi_allowed(vcpu)) {
4584 vcpu->arch.nmi_pending = false;
4585 vcpu->arch.nmi_injected = true;
4586 kvm_x86_ops->set_nmi(vcpu);
4587 }
4588 } else if (kvm_cpu_has_interrupt(vcpu)) {
4589 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 4590 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
4591 false);
4592 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 4593 }
4594 }
4595}
4596
2acf923e
DC		 4597static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
4598{
4599 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
4600 !vcpu->guest_xcr0_loaded) {
4601 /* kvm_set_xcr() also depends on this */
4602 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
4603 vcpu->guest_xcr0_loaded = 1;
4604 }
4605}
4606
4607static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
4608{
4609 if (vcpu->guest_xcr0_loaded) {
4610 if (vcpu->arch.xcr0 != host_xcr0)
4611 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
4612 vcpu->guest_xcr0_loaded = 0;
4613 }
4614}
4615
851ba692 4616static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 4617{
4618 int r;
6a8b1d13 4619 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 4620 vcpu->run->request_interrupt_window;
b6c7a5dc 4621
2e53d63a
MT		 4622 if (vcpu->requests)
4623 if (test_and_clear_bit(KVM_REQ_MMU_RELOAD, &vcpu->requests))
4624 kvm_mmu_unload(vcpu);
4625
b6c7a5dc
HB		 4626 r = kvm_mmu_reload(vcpu);
4627 if (unlikely(r))
4628 goto out;
4629
2f52d58c
AK		 4630 if (vcpu->requests) {
4631 if (test_and_clear_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests))
2f599714 4632 __kvm_migrate_timers(vcpu);
c8076604
GH		 4633 if (test_and_clear_bit(KVM_REQ_KVMCLOCK_UPDATE, &vcpu->requests))
4634 kvm_write_guest_time(vcpu);
4731d4c7
MT		 4635 if (test_and_clear_bit(KVM_REQ_MMU_SYNC, &vcpu->requests))
4636 kvm_mmu_sync_roots(vcpu);
d4acf7e7
MT		 4637 if (test_and_clear_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests))
4638 kvm_x86_ops->tlb_flush(vcpu);
b93463aa
AK		 4639 if (test_and_clear_bit(KVM_REQ_REPORT_TPR_ACCESS,
4640 &vcpu->requests)) {
851ba692 4641 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 4642 r = 0;
4643 goto out;
4644 }
71c4dfaf 4645 if (test_and_clear_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests)) {
851ba692 4646 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 4647 r = 0;
4648 goto out;
4649 }
02daab21
AK		 4650 if (test_and_clear_bit(KVM_REQ_DEACTIVATE_FPU, &vcpu->requests)) {
4651 vcpu->fpu_active = 0;
4652 kvm_x86_ops->fpu_deactivate(vcpu);
4653 }
2f52d58c 4654 }
b93463aa 4655
b6c7a5dc
HB		 4656 preempt_disable();
4657
4658 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 4659 if (vcpu->fpu_active)
4660 kvm_load_guest_fpu(vcpu);
2acf923e 4661 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 4662
d94e1dc9
AK		 4663 atomic_set(&vcpu->guest_mode, 1);
4664 smp_wmb();
b6c7a5dc 4665
d94e1dc9 4666 local_irq_disable();
32f88400 4667
d94e1dc9
AK		 4668 if (!atomic_read(&vcpu->guest_mode) || vcpu->requests
4669 || need_resched() || signal_pending(current)) {
4670 atomic_set(&vcpu->guest_mode, 0);
4671 smp_wmb();
6c142801
AK		 4672 local_irq_enable();
4673 preempt_enable();
4674 r = 1;
4675 goto out;
4676 }
4677
851ba692 4678 inject_pending_event(vcpu);
b6c7a5dc 4679
6a8b1d13
GN		 4680 /* enable NMI/IRQ window open exits if needed */
4681 if (vcpu->arch.nmi_pending)
4682 kvm_x86_ops->enable_nmi_window(vcpu);
4683 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
4684 kvm_x86_ops->enable_irq_window(vcpu);
4685
95ba8273 4686 if (kvm_lapic_enabled(vcpu)) {
8db3baa2
GN		 4687 update_cr8_intercept(vcpu);
4688 kvm_lapic_sync_to_vapic(vcpu);
95ba8273 4689 }
b93463aa 4690
f656ce01 4691 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
3200f405 4692
b6c7a5dc
HB		 4693 kvm_guest_enter();
4694
42dbaa5a 4695 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 4696 set_debugreg(0, 7);
4697 set_debugreg(vcpu->arch.eff_db[0], 0);
4698 set_debugreg(vcpu->arch.eff_db[1], 1);
4699 set_debugreg(vcpu->arch.eff_db[2], 2);
4700 set_debugreg(vcpu->arch.eff_db[3], 3);
4701 }
b6c7a5dc 4702
229456fc 4703 trace_kvm_entry(vcpu->vcpu_id);
851ba692 4704 kvm_x86_ops->run(vcpu);
b6c7a5dc 4705
24f1e32c
FW		 4706 /*
4707 * If the guest has used debug registers, at least dr7
4708 * will be disabled while returning to the host.
4709 * If we don't have active breakpoints in the host, we don't
4710 * care about the messed up debug address registers. But if
4711 * we have some of them active, restore the old state.
4712 */
59d8eb53 4713 if (hw_breakpoint_active())
24f1e32c 4714 hw_breakpoint_restore();
42dbaa5a 4715
d94e1dc9
AK		 4716 atomic_set(&vcpu->guest_mode, 0);
4717 smp_wmb();
b6c7a5dc
HB		 4718 local_irq_enable();
4719
4720 ++vcpu->stat.exits;
4721
4722 /*
4723 * We must have an instruction between local_irq_enable() and
4724 * kvm_guest_exit(), so the timer interrupt isn't delayed by
4725 * the interrupt shadow. The stat.exits increment will do nicely.
4726 * But we need to prevent reordering, hence this barrier():
4727 */
4728 barrier();
4729
4730 kvm_guest_exit();
4731
4732 preempt_enable();
4733
f656ce01 4734 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 4735
b6c7a5dc
HB		 4736 /*
4737 * Profile KVM exit RIPs:
4738 */
4739 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 4740 unsigned long rip = kvm_rip_read(vcpu);
4741 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 4742 }
4743
298101da 4744
b93463aa
AK		 4745 kvm_lapic_sync_from_vapic(vcpu);
4746
851ba692 4747 r = kvm_x86_ops->handle_exit(vcpu);
d7690175
MT		 4748out:
4749 return r;
4750}
b6c7a5dc 4751
09cec754 4752
851ba692 4753static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 4754{
4755 int r;
f656ce01 4756 struct kvm *kvm = vcpu->kvm;
d7690175
MT		 4757
4758 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
1b10bf31
JK		 4759 pr_debug("vcpu %d received sipi with vector # %x\n",
4760 vcpu->vcpu_id, vcpu->arch.sipi_vector);
d7690175 4761 kvm_lapic_reset(vcpu);
5f179287 4762 r = kvm_arch_vcpu_reset(vcpu);
d7690175
MT		 4763 if (r)
4764 return r;
4765 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 4766 }
4767
f656ce01 4768 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175
MT		 4769 vapic_enter(vcpu);
4770
4771 r = 1;
4772 while (r > 0) {
af2152f5 4773 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE)
851ba692 4774 r = vcpu_enter_guest(vcpu);
d7690175 4775 else {
f656ce01 4776 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 4777 kvm_vcpu_block(vcpu);
f656ce01 4778 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 4779 if (test_and_clear_bit(KVM_REQ_UNHALT, &vcpu->requests))
09cec754
GN		 4780 {
4781 switch(vcpu->arch.mp_state) {
4782 case KVM_MP_STATE_HALTED:
d7690175 4783 vcpu->arch.mp_state =
09cec754
GN		 4784 KVM_MP_STATE_RUNNABLE;
4785 case KVM_MP_STATE_RUNNABLE:
4786 break;
4787 case KVM_MP_STATE_SIPI_RECEIVED:
4788 default:
4789 r = -EINTR;
4790 break;
4791 }
4792 }
d7690175
MT		 4793 }
4794
09cec754
GN		 4795 if (r <= 0)
4796 break;
4797
4798 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
4799 if (kvm_cpu_has_pending_timer(vcpu))
4800 kvm_inject_pending_timer_irqs(vcpu);
4801
851ba692 4802 if (dm_request_for_irq_injection(vcpu)) {
09cec754 4803 r = -EINTR;
851ba692 4804 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 4805 ++vcpu->stat.request_irq_exits;
4806 }
4807 if (signal_pending(current)) {
4808 r = -EINTR;
851ba692 4809 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 4810 ++vcpu->stat.signal_exits;
4811 }
4812 if (need_resched()) {
f656ce01 4813 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
09cec754 4814 kvm_resched(vcpu);
f656ce01 4815 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 4816 }
b6c7a5dc
HB		 4817 }
4818
f656ce01 4819 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc 4820
b93463aa
AK		 4821 vapic_exit(vcpu);
4822
b6c7a5dc
HB		 4823 return r;
4824}
4825
4826int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
4827{
4828 int r;
4829 sigset_t sigsaved;
4830
ac9f6dc0
AK		 4831 if (vcpu->sigset_active)
4832 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
4833
a4535290 4834 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 4835 kvm_vcpu_block(vcpu);
d7690175 4836 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 4837 r = -EAGAIN;
4838 goto out;
b6c7a5dc
HB		 4839 }
4840
b6c7a5dc
HB		 4841 /* re-sync apic's tpr */
4842 if (!irqchip_in_kernel(vcpu->kvm))
2d3ad1f4 4843 kvm_set_cr8(vcpu, kvm_run->cr8);
b6c7a5dc 4844
92bf9748
GN		 4845 if (vcpu->arch.pio.count || vcpu->mmio_needed ||
4846 vcpu->arch.emulate_ctxt.restart) {
4847 if (vcpu->mmio_needed) {
4848 memcpy(vcpu->mmio_data, kvm_run->mmio.data, 8);
4849 vcpu->mmio_read_completed = 1;
4850 vcpu->mmio_needed = 0;
b6c7a5dc 4851 }
f656ce01 4852 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5cd21917 4853 r = emulate_instruction(vcpu, 0, 0, EMULTYPE_NO_DECODE);
f656ce01 4854 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6d77dbfc 4855 if (r != EMULATE_DONE) {
b6c7a5dc
HB		 4856 r = 0;
4857 goto out;
4858 }
4859 }
5fdbf976
MT		 4860 if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL)
4861 kvm_register_write(vcpu, VCPU_REGS_RAX,
4862 kvm_run->hypercall.ret);
b6c7a5dc 4863
851ba692 4864 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 4865
4866out:
f1d86e46 4867 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 4868 if (vcpu->sigset_active)
4869 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
4870
b6c7a5dc
HB		 4871 return r;
4872}
4873
4874int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
4875{
5fdbf976
MT		 4876 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
4877 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
4878 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
4879 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
4880 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
4881 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
4882 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
4883 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 4884#ifdef CONFIG_X86_64
5fdbf976
MT		 4885 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
4886 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
4887 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
4888 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
4889 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
4890 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
4891 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
4892 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 4893#endif
4894
5fdbf976 4895 regs->rip = kvm_rip_read(vcpu);
91586a3b 4896 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 4897
b6c7a5dc
HB		 4898 return 0;
4899}
4900
4901int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
4902{
5fdbf976
MT		 4903 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
4904 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
4905 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
4906 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
4907 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
4908 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
4909 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
4910 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 4911#ifdef CONFIG_X86_64
5fdbf976
MT		 4912 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
4913 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
4914 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
4915 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
4916 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
4917 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
4918 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
4919 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 4920#endif
4921
5fdbf976 4922 kvm_rip_write(vcpu, regs->rip);
91586a3b 4923 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 4924
b4f14abd
JK		 4925 vcpu->arch.exception.pending = false;
4926
b6c7a5dc
HB		 4927 return 0;
4928}
4929
b6c7a5dc
HB		 4930void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
4931{
4932 struct kvm_segment cs;
4933
3e6e0aab 4934 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 4935 *db = cs.db;
4936 *l = cs.l;
4937}
4938EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
4939
4940int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
4941 struct kvm_sregs *sregs)
4942{
89a27f4d 4943 struct desc_ptr dt;
b6c7a5dc 4944
3e6e0aab
GT		 4945 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
4946 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
4947 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
4948 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
4949 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
4950 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 4951
3e6e0aab
GT		 4952 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
4953 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 4954
4955 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 4956 sregs->idt.limit = dt.size;
4957 sregs->idt.base = dt.address;
b6c7a5dc 4958 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 4959 sregs->gdt.limit = dt.size;
4960 sregs->gdt.base = dt.address;
b6c7a5dc 4961
4d4ec087 4962 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c
ZX		 4963 sregs->cr2 = vcpu->arch.cr2;
4964 sregs->cr3 = vcpu->arch.cr3;
fc78f519 4965 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 4966 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 4967 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 4968 sregs->apic_base = kvm_get_apic_base(vcpu);
4969
923c61bb 4970 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 4971
36752c9b 4972 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 4973 set_bit(vcpu->arch.interrupt.nr,
4974 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 4975
b6c7a5dc
HB		 4976 return 0;
4977}
4978
62d9f0db
MT		 4979int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
4980 struct kvm_mp_state *mp_state)
4981{
62d9f0db 4982 mp_state->mp_state = vcpu->arch.mp_state;
62d9f0db
MT		 4983 return 0;
4984}
4985
4986int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
4987 struct kvm_mp_state *mp_state)
4988{
62d9f0db 4989 vcpu->arch.mp_state = mp_state->mp_state;
62d9f0db
MT		 4990 return 0;
4991}
4992
e269fb21
JK		 4993int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason,
4994 bool has_error_code, u32 error_code)
b6c7a5dc 4995{
4d2179e1 4996 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
ceffb459
GN		 4997 int cs_db, cs_l, ret;
4998 cache_all_regs(vcpu);
37817f29 4999
ceffb459 5000 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
e01c2426 5001
ceffb459
GN		 5002 vcpu->arch.emulate_ctxt.vcpu = vcpu;
5003 vcpu->arch.emulate_ctxt.eflags = kvm_x86_ops->get_rflags(vcpu);
5004 vcpu->arch.emulate_ctxt.eip = kvm_rip_read(vcpu);
5005 vcpu->arch.emulate_ctxt.mode =
5006 (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5007 (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM)
5008 ? X86EMUL_MODE_VM86 : cs_l
5009 ? X86EMUL_MODE_PROT64 : cs_db
5010 ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
4d2179e1
GN		 5011 memset(c, 0, sizeof(struct decode_cache));
5012 memcpy(c->regs, vcpu->arch.regs, sizeof c->regs);
c697518a 5013
ceffb459 5014 ret = emulator_task_switch(&vcpu->arch.emulate_ctxt, &emulate_ops,
e269fb21
JK		 5015 tss_selector, reason, has_error_code,
5016 error_code);
c697518a 5017
c697518a 5018 if (ret)
19d04437 5019 return EMULATE_FAIL;
37817f29 5020
4d2179e1 5021 memcpy(vcpu->arch.regs, c->regs, sizeof c->regs);
95c55886 5022 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.eip);
19d04437
GN		 5023 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
5024 return EMULATE_DONE;
37817f29
IE		 5025}
5026EXPORT_SYMBOL_GPL(kvm_task_switch);
5027
b6c7a5dc
HB		 5028int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
5029 struct kvm_sregs *sregs)
5030{
5031 int mmu_reset_needed = 0;
923c61bb 5032 int pending_vec, max_bits;
89a27f4d 5033 struct desc_ptr dt;
b6c7a5dc 5034
89a27f4d
GN		 5035 dt.size = sregs->idt.limit;
5036 dt.address = sregs->idt.base;
b6c7a5dc 5037 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 5038 dt.size = sregs->gdt.limit;
5039 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 5040 kvm_x86_ops->set_gdt(vcpu, &dt);
5041
ad312c7c
ZX		 5042 vcpu->arch.cr2 = sregs->cr2;
5043 mmu_reset_needed |= vcpu->arch.cr3 != sregs->cr3;
dc7e795e 5044 vcpu->arch.cr3 = sregs->cr3;
b6c7a5dc 5045
2d3ad1f4 5046 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 5047
f6801dff 5048 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 5049 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 5050 kvm_set_apic_base(vcpu, sregs->apic_base);
5051
4d4ec087 5052 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 5053 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 5054 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 5055
fc78f519 5056 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 5057 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
7c93be44 5058 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
ad312c7c 5059 load_pdptrs(vcpu, vcpu->arch.cr3);
7c93be44
MT		 5060 mmu_reset_needed = 1;
5061 }
b6c7a5dc
HB		 5062
5063 if (mmu_reset_needed)
5064 kvm_mmu_reset_context(vcpu);
5065
923c61bb
GN		 5066 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
5067 pending_vec = find_first_bit(
5068 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
5069 if (pending_vec < max_bits) {
66fd3f7f 5070 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb
GN		 5071 pr_debug("Set back pending irq %d\n", pending_vec);
5072 if (irqchip_in_kernel(vcpu->kvm))
5073 kvm_pic_clear_isr_ack(vcpu->kvm);
b6c7a5dc
HB		 5074 }
5075
3e6e0aab
GT		 5076 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5077 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5078 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5079 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5080 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5081 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 5082
3e6e0aab
GT		 5083 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5084 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 5085
5f0269f5
ME		 5086 update_cr8_intercept(vcpu);
5087
9c3e4aab 5088 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 5089 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 5090 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 5091 !is_protmode(vcpu))
9c3e4aab
MT		 5092 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
5093
b6c7a5dc
HB		 5094 return 0;
5095}
5096
d0bfb940
JK		 5097int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
5098 struct kvm_guest_debug *dbg)
b6c7a5dc 5099{
355be0b9 5100 unsigned long rflags;
ae675ef0 5101 int i, r;
b6c7a5dc 5102
4f926bf2
JK		 5103 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
5104 r = -EBUSY;
5105 if (vcpu->arch.exception.pending)
2122ff5e 5106 goto out;
4f926bf2
JK		 5107 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
5108 kvm_queue_exception(vcpu, DB_VECTOR);
5109 else
5110 kvm_queue_exception(vcpu, BP_VECTOR);
5111 }
5112
91586a3b
JK		 5113 /*
5114 * Read rflags as long as potentially injected trace flags are still
5115 * filtered out.
5116 */
5117 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 5118
5119 vcpu->guest_debug = dbg->control;
5120 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
5121 vcpu->guest_debug = 0;
5122
5123 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 5124 for (i = 0; i < KVM_NR_DB_REGS; ++i)
5125 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
5126 vcpu->arch.switch_db_regs =
5127 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
5128 } else {
5129 for (i = 0; i < KVM_NR_DB_REGS; i++)
5130 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
5131 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
5132 }
5133
f92653ee
JK		 5134 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
5135 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
5136 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 5137
91586a3b
JK		 5138 /*
5139 * Trigger an rflags update that will inject or remove the trace
5140 * flags.
5141 */
5142 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 5143
355be0b9 5144 kvm_x86_ops->set_guest_debug(vcpu, dbg);
b6c7a5dc 5145
4f926bf2 5146 r = 0;
d0bfb940 5147
2122ff5e 5148out:
b6c7a5dc
HB		 5149
5150 return r;
5151}
5152
8b006791
ZX		 5153/*
5154 * Translate a guest virtual address to a guest physical address.
5155 */
5156int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
5157 struct kvm_translation *tr)
5158{
5159 unsigned long vaddr = tr->linear_address;
5160 gpa_t gpa;
f656ce01 5161 int idx;
8b006791 5162
f656ce01 5163 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 5164 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 5165 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 5166 tr->physical_address = gpa;
5167 tr->valid = gpa != UNMAPPED_GVA;
5168 tr->writeable = 1;
5169 tr->usermode = 0;
8b006791
ZX		 5170
5171 return 0;
5172}
5173
d0752060
HB		 5174int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5175{
98918833
SY		 5176 struct i387_fxsave_struct *fxsave =
5177 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 5178
d0752060
HB		 5179 memcpy(fpu->fpr, fxsave->st_space, 128);
5180 fpu->fcw = fxsave->cwd;
5181 fpu->fsw = fxsave->swd;
5182 fpu->ftwx = fxsave->twd;
5183 fpu->last_opcode = fxsave->fop;
5184 fpu->last_ip = fxsave->rip;
5185 fpu->last_dp = fxsave->rdp;
5186 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
5187
d0752060
HB		 5188 return 0;
5189}
5190
5191int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5192{
98918833
SY		 5193 struct i387_fxsave_struct *fxsave =
5194 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 5195
d0752060
HB		 5196 memcpy(fxsave->st_space, fpu->fpr, 128);
5197 fxsave->cwd = fpu->fcw;
5198 fxsave->swd = fpu->fsw;
5199 fxsave->twd = fpu->ftwx;
5200 fxsave->fop = fpu->last_opcode;
5201 fxsave->rip = fpu->last_ip;
5202 fxsave->rdp = fpu->last_dp;
5203 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
5204
d0752060
HB		 5205 return 0;
5206}
5207
10ab25cd 5208int fx_init(struct kvm_vcpu *vcpu)
d0752060 5209{
10ab25cd
JK		 5210 int err;
5211
5212 err = fpu_alloc(&vcpu->arch.guest_fpu);
5213 if (err)
5214 return err;
5215
98918833 5216 fpu_finit(&vcpu->arch.guest_fpu);
d0752060 5217
2acf923e
DC		 5218 /*
5219 * Ensure guest xcr0 is valid for loading
5220 */
5221 vcpu->arch.xcr0 = XSTATE_FP;
5222
ad312c7c 5223 vcpu->arch.cr0 |= X86_CR0_ET;
10ab25cd
JK		 5224
5225 return 0;
d0752060
HB		 5226}
5227EXPORT_SYMBOL_GPL(fx_init);
5228
98918833
SY		 5229static void fx_free(struct kvm_vcpu *vcpu)
5230{
5231 fpu_free(&vcpu->arch.guest_fpu);
5232}
5233
d0752060
HB		 5234void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
5235{
2608d7a1 5236 if (vcpu->guest_fpu_loaded)
d0752060
HB		 5237 return;
5238
2acf923e
DC		 5239 /*
5240 * Restore all possible states in the guest,
5241 * and assume host would use all available bits.
5242 * Guest xcr0 would be loaded later.
5243 */
5244 kvm_put_guest_xcr0(vcpu);
d0752060 5245 vcpu->guest_fpu_loaded = 1;
7cf30855 5246 unlazy_fpu(current);
98918833 5247 fpu_restore_checking(&vcpu->arch.guest_fpu);
0c04851c 5248 trace_kvm_fpu(1);
d0752060 5249}
d0752060
HB		 5250
5251void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
5252{
2acf923e
DC		 5253 kvm_put_guest_xcr0(vcpu);
5254
d0752060
HB		 5255 if (!vcpu->guest_fpu_loaded)
5256 return;
5257
5258 vcpu->guest_fpu_loaded = 0;
98918833 5259 fpu_save_init(&vcpu->arch.guest_fpu);
f096ed85 5260 ++vcpu->stat.fpu_reload;
02daab21 5261 set_bit(KVM_REQ_DEACTIVATE_FPU, &vcpu->requests);
0c04851c 5262 trace_kvm_fpu(0);
d0752060 5263}
e9b11c17
ZX		 5264
5265void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
5266{
7f1ea208
JR		 5267 if (vcpu->arch.time_page) {
5268 kvm_release_page_dirty(vcpu->arch.time_page);
5269 vcpu->arch.time_page = NULL;
5270 }
5271
98918833 5272 fx_free(vcpu);
e9b11c17
ZX		 5273 kvm_x86_ops->vcpu_free(vcpu);
5274}
5275
5276struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
5277 unsigned int id)
5278{
26e5215f
AK		 5279 return kvm_x86_ops->vcpu_create(kvm, id);
5280}
e9b11c17 5281
26e5215f
AK		 5282int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
5283{
5284 int r;
e9b11c17 5285
0bed3b56 5286 vcpu->arch.mtrr_state.have_fixed = 1;
e9b11c17
ZX		 5287 vcpu_load(vcpu);
5288 r = kvm_arch_vcpu_reset(vcpu);
5289 if (r == 0)
5290 r = kvm_mmu_setup(vcpu);
5291 vcpu_put(vcpu);
5292 if (r < 0)
5293 goto free_vcpu;
5294
26e5215f 5295 return 0;
e9b11c17
ZX		 5296free_vcpu:
5297 kvm_x86_ops->vcpu_free(vcpu);
26e5215f 5298 return r;
e9b11c17
ZX		 5299}
5300
d40ccc62 5301void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17
ZX		 5302{
5303 vcpu_load(vcpu);
5304 kvm_mmu_unload(vcpu);
5305 vcpu_put(vcpu);
5306
98918833 5307 fx_free(vcpu);
e9b11c17
ZX		 5308 kvm_x86_ops->vcpu_free(vcpu);
5309}
5310
5311int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
5312{
448fa4a9
JK		 5313 vcpu->arch.nmi_pending = false;
5314 vcpu->arch.nmi_injected = false;
5315
42dbaa5a
JK		 5316 vcpu->arch.switch_db_regs = 0;
5317 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
5318 vcpu->arch.dr6 = DR6_FIXED_1;
5319 vcpu->arch.dr7 = DR7_FIXED_1;
5320
e9b11c17
ZX		 5321 return kvm_x86_ops->vcpu_reset(vcpu);
5322}
5323
10474ae8 5324int kvm_arch_hardware_enable(void *garbage)
e9b11c17 5325{
0cca7907
ZA		 5326 /*
5327 * Since this may be called from a hotplug notifcation,
5328 * we can't get the CPU frequency directly.
5329 */
5330 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
5331 int cpu = raw_smp_processor_id();
5332 per_cpu(cpu_tsc_khz, cpu) = 0;
5333 }
18863bdd
AK		 5334
5335 kvm_shared_msr_cpu_online();
5336
10474ae8 5337 return kvm_x86_ops->hardware_enable(garbage);
e9b11c17
ZX		 5338}
5339
5340void kvm_arch_hardware_disable(void *garbage)
5341{
5342 kvm_x86_ops->hardware_disable(garbage);
3548bab5 5343 drop_user_return_notifiers(garbage);
e9b11c17
ZX		 5344}
5345
5346int kvm_arch_hardware_setup(void)
5347{
5348 return kvm_x86_ops->hardware_setup();
5349}
5350
5351void kvm_arch_hardware_unsetup(void)
5352{
5353 kvm_x86_ops->hardware_unsetup();
5354}
5355
5356void kvm_arch_check_processor_compat(void *rtn)
5357{
5358 kvm_x86_ops->check_processor_compatibility(rtn);
5359}
5360
5361int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
5362{
5363 struct page *page;
5364 struct kvm *kvm;
5365 int r;
5366
5367 BUG_ON(vcpu->kvm == NULL);
5368 kvm = vcpu->kvm;
5369
ad312c7c 5370 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
c5af89b6 5371 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 5372 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 5373 else
a4535290 5374 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 5375
5376 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
5377 if (!page) {
5378 r = -ENOMEM;
5379 goto fail;
5380 }
ad312c7c 5381 vcpu->arch.pio_data = page_address(page);
e9b11c17
ZX		 5382
5383 r = kvm_mmu_create(vcpu);
5384 if (r < 0)
5385 goto fail_free_pio_data;
5386
5387 if (irqchip_in_kernel(kvm)) {
5388 r = kvm_create_lapic(vcpu);
5389 if (r < 0)
5390 goto fail_mmu_destroy;
5391 }
5392
890ca9ae
HY		 5393 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
5394 GFP_KERNEL);
5395 if (!vcpu->arch.mce_banks) {
5396 r = -ENOMEM;
443c39bc 5397 goto fail_free_lapic;
890ca9ae
HY		 5398 }
5399 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
5400
e9b11c17 5401 return 0;
443c39bc
WY		 5402fail_free_lapic:
5403 kvm_free_lapic(vcpu);
e9b11c17
ZX		 5404fail_mmu_destroy:
5405 kvm_mmu_destroy(vcpu);
5406fail_free_pio_data:
ad312c7c 5407 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 5408fail:
5409 return r;
5410}
5411
5412void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
5413{
f656ce01
MT		 5414 int idx;
5415
36cb93fd 5416 kfree(vcpu->arch.mce_banks);
e9b11c17 5417 kvm_free_lapic(vcpu);
f656ce01 5418 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 5419 kvm_mmu_destroy(vcpu);
f656ce01 5420 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 5421 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17 5422}
d19a9cd2
ZX		 5423
5424struct kvm *kvm_arch_create_vm(void)
5425{
5426 struct kvm *kvm = kzalloc(sizeof(struct kvm), GFP_KERNEL);
5427
5428 if (!kvm)
5429 return ERR_PTR(-ENOMEM);
5430
fef9cce0
MT		 5431 kvm->arch.aliases = kzalloc(sizeof(struct kvm_mem_aliases), GFP_KERNEL);
5432 if (!kvm->arch.aliases) {
5433 kfree(kvm);
5434 return ERR_PTR(-ENOMEM);
5435 }
5436
f05e70ac 5437 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4d5c5d0f 5438 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2 5439
5550af4d
SY		 5440 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
5441 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
5442
53f658b3
MT		 5443 rdtscll(kvm->arch.vm_init_tsc);
5444
d19a9cd2
ZX		 5445 return kvm;
5446}
5447
5448static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
5449{
5450 vcpu_load(vcpu);
5451 kvm_mmu_unload(vcpu);
5452 vcpu_put(vcpu);
5453}
5454
5455static void kvm_free_vcpus(struct kvm *kvm)
5456{
5457 unsigned int i;
988a2cae 5458 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 5459
5460 /*
5461 * Unpin any mmu pages first.
5462 */
988a2cae
GN		 5463 kvm_for_each_vcpu(i, vcpu, kvm)
5464 kvm_unload_vcpu_mmu(vcpu);
5465 kvm_for_each_vcpu(i, vcpu, kvm)
5466 kvm_arch_vcpu_free(vcpu);
5467
5468 mutex_lock(&kvm->lock);
5469 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
5470 kvm->vcpus[i] = NULL;
d19a9cd2 5471
988a2cae
GN		 5472 atomic_set(&kvm->online_vcpus, 0);
5473 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 5474}
5475
ad8ba2cd
SY		 5476void kvm_arch_sync_events(struct kvm *kvm)
5477{
ba4cef31 5478 kvm_free_all_assigned_devices(kvm);
ad8ba2cd
SY		 5479}
5480
d19a9cd2
ZX		 5481void kvm_arch_destroy_vm(struct kvm *kvm)
5482{
6eb55818 5483 kvm_iommu_unmap_guest(kvm);
7837699f 5484 kvm_free_pit(kvm);
d7deeeb0
ZX		 5485 kfree(kvm->arch.vpic);
5486 kfree(kvm->arch.vioapic);
d19a9cd2
ZX		 5487 kvm_free_vcpus(kvm);
5488 kvm_free_physmem(kvm);
3d45830c
AK		 5489 if (kvm->arch.apic_access_page)
5490 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 5491 if (kvm->arch.ept_identity_pagetable)
5492 put_page(kvm->arch.ept_identity_pagetable);
64749204 5493 cleanup_srcu_struct(&kvm->srcu);
fef9cce0 5494 kfree(kvm->arch.aliases);
d19a9cd2
ZX		 5495 kfree(kvm);
5496}
0de10343 5497
f7784b8e
MT		 5498int kvm_arch_prepare_memory_region(struct kvm *kvm,
5499 struct kvm_memory_slot *memslot,
0de10343 5500 struct kvm_memory_slot old,
f7784b8e 5501 struct kvm_userspace_memory_region *mem,
0de10343
ZX		 5502 int user_alloc)
5503{
f7784b8e 5504 int npages = memslot->npages;
0de10343
ZX		 5505
5506 /*To keep backward compatibility with older userspace,
5507 *x86 needs to hanlde !user_alloc case.
5508 */
5509 if (!user_alloc) {
5510 if (npages && !old.rmap) {
604b38ac
AA		 5511 unsigned long userspace_addr;
5512
72dc67a6 5513 down_write(&current->mm->mmap_sem);
604b38ac
AA		 5514 userspace_addr = do_mmap(NULL, 0,
5515 npages * PAGE_SIZE,
5516 PROT_READ | PROT_WRITE,
acee3c04 5517 MAP_PRIVATE | MAP_ANONYMOUS,
604b38ac 5518 0);
72dc67a6 5519 up_write(&current->mm->mmap_sem);
0de10343 5520
604b38ac
AA		 5521 if (IS_ERR((void *)userspace_addr))
5522 return PTR_ERR((void *)userspace_addr);
5523
604b38ac 5524 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 5525 }
5526 }
5527
f7784b8e
MT		 5528
5529 return 0;
5530}
5531
5532void kvm_arch_commit_memory_region(struct kvm *kvm,
5533 struct kvm_userspace_memory_region *mem,
5534 struct kvm_memory_slot old,
5535 int user_alloc)
5536{
5537
5538 int npages = mem->memory_size >> PAGE_SHIFT;
5539
5540 if (!user_alloc && !old.user_alloc && old.rmap && !npages) {
5541 int ret;
5542
5543 down_write(&current->mm->mmap_sem);
5544 ret = do_munmap(current->mm, old.userspace_addr,
5545 old.npages * PAGE_SIZE);
5546 up_write(&current->mm->mmap_sem);
5547 if (ret < 0)
5548 printk(KERN_WARNING
5549 "kvm_vm_ioctl_set_memory_region: "
5550 "failed to munmap memory\n");
5551 }
5552
7c8a83b7 5553 spin_lock(&kvm->mmu_lock);
f05e70ac 5554 if (!kvm->arch.n_requested_mmu_pages) {
0de10343
ZX		 5555 unsigned int nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
5556 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
5557 }
5558
5559 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
7c8a83b7 5560 spin_unlock(&kvm->mmu_lock);
0de10343 5561}
1d737c8a 5562
34d4cb8f
MT		 5563void kvm_arch_flush_shadow(struct kvm *kvm)
5564{
5565 kvm_mmu_zap_all(kvm);
8986ecc0 5566 kvm_reload_remote_mmus(kvm);
34d4cb8f
MT		 5567}
5568
1d737c8a
ZX		 5569int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
5570{
a4535290 5571 return vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE
a1b37100
GN		 5572 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
5573 || vcpu->arch.nmi_pending ||
5574 (kvm_arch_interrupt_allowed(vcpu) &&
5575 kvm_cpu_has_interrupt(vcpu));
1d737c8a 5576}
5736199a 5577
5736199a
ZX		 5578void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
5579{
32f88400
MT		 5580 int me;
5581 int cpu = vcpu->cpu;
5736199a
ZX		 5582
5583 if (waitqueue_active(&vcpu->wq)) {
5584 wake_up_interruptible(&vcpu->wq);
5585 ++vcpu->stat.halt_wakeup;
5586 }
32f88400
MT		 5587
5588 me = get_cpu();
5589 if (cpu != me && (unsigned)cpu < nr_cpu_ids && cpu_online(cpu))
d94e1dc9 5590 if (atomic_xchg(&vcpu->guest_mode, 0))
32f88400 5591 smp_send_reschedule(cpu);
e9571ed5 5592 put_cpu();
5736199a 5593}
78646121
GN		 5594
5595int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
5596{
5597 return kvm_x86_ops->interrupt_allowed(vcpu);
5598}
229456fc 5599
f92653ee
JK		 5600bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
5601{
5602 unsigned long current_rip = kvm_rip_read(vcpu) +
5603 get_segment_base(vcpu, VCPU_SREG_CS);
5604
5605 return current_rip == linear_rip;
5606}
5607EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
5608
94fe45da
JK		 5609unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
5610{
5611 unsigned long rflags;
5612
5613 rflags = kvm_x86_ops->get_rflags(vcpu);
5614 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 5615 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 5616 return rflags;
5617}
5618EXPORT_SYMBOL_GPL(kvm_get_rflags);
5619
5620void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
5621{
5622 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 5623 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 5624 rflags |= X86_EFLAGS_TF;
94fe45da
JK		 5625 kvm_x86_ops->set_rflags(vcpu, rflags);
5626}
5627EXPORT_SYMBOL_GPL(kvm_set_rflags);
5628
229456fc
MT		 5629EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
5630EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
5631EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
5632EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
5633EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 5634EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 5635EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 5636EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 5637EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 5638EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 5639EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 5640EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
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