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x86: kvmclock: abstract save/restore sched_clock_state
[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
313a3dc7 30
18068523 31#include <linux/clocksource.h>
4d5c5d0f 32#include <linux/interrupt.h>
313a3dc7
CO		 33#include <linux/kvm.h>
34#include <linux/fs.h>
35#include <linux/vmalloc.h>
5fb76f9b 36#include <linux/module.h>
0de10343 37#include <linux/mman.h>
2bacc55c 38#include <linux/highmem.h>
19de40a8 39#include <linux/iommu.h>
62c476c7 40#include <linux/intel-iommu.h>
c8076604 41#include <linux/cpufreq.h>
18863bdd 42#include <linux/user-return-notifier.h>
a983fb23 43#include <linux/srcu.h>
5a0e3ad6 44#include <linux/slab.h>
ff9d07a0 45#include <linux/perf_event.h>
7bee342a 46#include <linux/uaccess.h>
af585b92 47#include <linux/hash.h>
a1b60c1c 48#include <linux/pci.h>
aec51dc4 49#include <trace/events/kvm.h>
2ed152af 50
229456fc
MT		 51#define CREATE_TRACE_POINTS
52#include "trace.h"
043405e1 53
24f1e32c 54#include <asm/debugreg.h>
d825ed0a 55#include <asm/msr.h>
a5f61300 56#include <asm/desc.h>
0bed3b56 57#include <asm/mtrr.h>
890ca9ae 58#include <asm/mce.h>
7cf30855 59#include <asm/i387.h>
98918833 60#include <asm/xcr.h>
1d5f066e 61#include <asm/pvclock.h>
217fc9cf 62#include <asm/div64.h>
043405e1 63
313a3dc7 64#define MAX_IO_MSRS 256
890ca9ae 65#define KVM_MAX_MCE_BANKS 32
5854dbca 66#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 67
0f65dd70
AK		 68#define emul_to_vcpu(ctxt) \
69 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
70
50a37eb4
JR		 71/* EFER defaults:
72 * - enable syscall per default because its emulated by KVM
73 * - enable LME and LMA per default on 64 bit KVM
74 */
75#ifdef CONFIG_X86_64
1260edbe
LJ		 76static
77u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 78#else
1260edbe 79static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 80#endif
313a3dc7 81
ba1389b7
AK		 82#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
83#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 84
cb142eb7 85static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 86static void process_nmi(struct kvm_vcpu *vcpu);
674eea0f 87
97896d04 88struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 89EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 90
476bc001
RR		 91static bool ignore_msrs = 0;
92module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 93
92a1f12d
JR		 94bool kvm_has_tsc_control;
95EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
96u32 kvm_max_guest_tsc_khz;
97EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
98
cc578287
ZA		 99/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
100static u32 tsc_tolerance_ppm = 250;
101module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
102
18863bdd
AK		 103#define KVM_NR_SHARED_MSRS 16
104
105struct kvm_shared_msrs_global {
106 int nr;
2bf78fa7 107 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 108};
109
110struct kvm_shared_msrs {
111 struct user_return_notifier urn;
112 bool registered;
2bf78fa7
SY		 113 struct kvm_shared_msr_values {
114 u64 host;
115 u64 curr;
116 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 117};
118
119static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
120static DEFINE_PER_CPU(struct kvm_shared_msrs, shared_msrs);
121
417bc304 122struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 123 { "pf_fixed", VCPU_STAT(pf_fixed) },
124 { "pf_guest", VCPU_STAT(pf_guest) },
125 { "tlb_flush", VCPU_STAT(tlb_flush) },
126 { "invlpg", VCPU_STAT(invlpg) },
127 { "exits", VCPU_STAT(exits) },
128 { "io_exits", VCPU_STAT(io_exits) },
129 { "mmio_exits", VCPU_STAT(mmio_exits) },
130 { "signal_exits", VCPU_STAT(signal_exits) },
131 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 132 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 133 { "halt_exits", VCPU_STAT(halt_exits) },
134 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 135 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 136 { "request_irq", VCPU_STAT(request_irq_exits) },
137 { "irq_exits", VCPU_STAT(irq_exits) },
138 { "host_state_reload", VCPU_STAT(host_state_reload) },
139 { "efer_reload", VCPU_STAT(efer_reload) },
140 { "fpu_reload", VCPU_STAT(fpu_reload) },
141 { "insn_emulation", VCPU_STAT(insn_emulation) },
142 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 143 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 144 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 145 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
146 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
147 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
148 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
149 { "mmu_flooded", VM_STAT(mmu_flooded) },
150 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 151 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 152 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 153 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 154 { "largepages", VM_STAT(lpages) },
417bc304
HB		 155 { NULL }
156};
157
2acf923e
DC		 158u64 __read_mostly host_xcr0;
159
d6aa1000
AK		 160int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
161
af585b92
GN		 162static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
163{
164 int i;
165 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
166 vcpu->arch.apf.gfns[i] = ~0;
167}
168
18863bdd
AK		 169static void kvm_on_user_return(struct user_return_notifier *urn)
170{
171 unsigned slot;
18863bdd
AK		 172 struct kvm_shared_msrs *locals
173 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 174 struct kvm_shared_msr_values *values;
18863bdd
AK		 175
176 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 177 values = &locals->values[slot];
178 if (values->host != values->curr) {
179 wrmsrl(shared_msrs_global.msrs[slot], values->host);
180 values->curr = values->host;
18863bdd
AK		 181 }
182 }
183 locals->registered = false;
184 user_return_notifier_unregister(urn);
185}
186
2bf78fa7 187static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 188{
2bf78fa7 189 struct kvm_shared_msrs *smsr;
18863bdd
AK		 190 u64 value;
191
2bf78fa7
SY		 192 smsr = &__get_cpu_var(shared_msrs);
193 /* only read, and nobody should modify it at this time,
194 * so don't need lock */
195 if (slot >= shared_msrs_global.nr) {
196 printk(KERN_ERR "kvm: invalid MSR slot!");
197 return;
198 }
199 rdmsrl_safe(msr, &value);
200 smsr->values[slot].host = value;
201 smsr->values[slot].curr = value;
202}
203
204void kvm_define_shared_msr(unsigned slot, u32 msr)
205{
18863bdd
AK		 206 if (slot >= shared_msrs_global.nr)
207 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 208 shared_msrs_global.msrs[slot] = msr;
209 /* we need ensured the shared_msr_global have been updated */
210 smp_wmb();
18863bdd
AK		 211}
212EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
213
214static void kvm_shared_msr_cpu_online(void)
215{
216 unsigned i;
18863bdd
AK		 217
218 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 219 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 220}
221
d5696725 222void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd
AK		 223{
224 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
225
2bf78fa7 226 if (((value ^ smsr->values[slot].curr) & mask) == 0)
18863bdd 227 return;
2bf78fa7
SY		 228 smsr->values[slot].curr = value;
229 wrmsrl(shared_msrs_global.msrs[slot], value);
18863bdd
AK		 230 if (!smsr->registered) {
231 smsr->urn.on_user_return = kvm_on_user_return;
232 user_return_notifier_register(&smsr->urn);
233 smsr->registered = true;
234 }
235}
236EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
237
3548bab5
AK		 238static void drop_user_return_notifiers(void *ignore)
239{
240 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
241
242 if (smsr->registered)
243 kvm_on_user_return(&smsr->urn);
244}
245
6866b83e
CO		 246u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
247{
248 if (irqchip_in_kernel(vcpu->kvm))
ad312c7c 249 return vcpu->arch.apic_base;
6866b83e 250 else
ad312c7c 251 return vcpu->arch.apic_base;
6866b83e
CO		 252}
253EXPORT_SYMBOL_GPL(kvm_get_apic_base);
254
255void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
256{
257 /* TODO: reserve bits check */
258 if (irqchip_in_kernel(vcpu->kvm))
259 kvm_lapic_set_base(vcpu, data);
260 else
ad312c7c 261 vcpu->arch.apic_base = data;
6866b83e
CO		 262}
263EXPORT_SYMBOL_GPL(kvm_set_apic_base);
264
3fd28fce
ED		 265#define EXCPT_BENIGN 0
266#define EXCPT_CONTRIBUTORY 1
267#define EXCPT_PF 2
268
269static int exception_class(int vector)
270{
271 switch (vector) {
272 case PF_VECTOR:
273 return EXCPT_PF;
274 case DE_VECTOR:
275 case TS_VECTOR:
276 case NP_VECTOR:
277 case SS_VECTOR:
278 case GP_VECTOR:
279 return EXCPT_CONTRIBUTORY;
280 default:
281 break;
282 }
283 return EXCPT_BENIGN;
284}
285
286static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 287 unsigned nr, bool has_error, u32 error_code,
288 bool reinject)
3fd28fce
ED		 289{
290 u32 prev_nr;
291 int class1, class2;
292
3842d135
AK		 293 kvm_make_request(KVM_REQ_EVENT, vcpu);
294
3fd28fce
ED		 295 if (!vcpu->arch.exception.pending) {
296 queue:
297 vcpu->arch.exception.pending = true;
298 vcpu->arch.exception.has_error_code = has_error;
299 vcpu->arch.exception.nr = nr;
300 vcpu->arch.exception.error_code = error_code;
3f0fd292 301 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 302 return;
303 }
304
305 /* to check exception */
306 prev_nr = vcpu->arch.exception.nr;
307 if (prev_nr == DF_VECTOR) {
308 /* triple fault -> shutdown */
a8eeb04a 309 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 310 return;
311 }
312 class1 = exception_class(prev_nr);
313 class2 = exception_class(nr);
314 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
315 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
316 /* generate double fault per SDM Table 5-5 */
317 vcpu->arch.exception.pending = true;
318 vcpu->arch.exception.has_error_code = true;
319 vcpu->arch.exception.nr = DF_VECTOR;
320 vcpu->arch.exception.error_code = 0;
321 } else
322 /* replace previous exception with a new one in a hope
323 that instruction re-execution will regenerate lost
324 exception */
325 goto queue;
326}
327
298101da
AK		 328void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
329{
ce7ddec4 330 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 331}
332EXPORT_SYMBOL_GPL(kvm_queue_exception);
333
ce7ddec4
JR		 334void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
335{
336 kvm_multiple_exception(vcpu, nr, false, 0, true);
337}
338EXPORT_SYMBOL_GPL(kvm_requeue_exception);
339
db8fcefa 340void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 341{
db8fcefa
AP		 342 if (err)
343 kvm_inject_gp(vcpu, 0);
344 else
345 kvm_x86_ops->skip_emulated_instruction(vcpu);
346}
347EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 348
6389ee94 349void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 350{
351 ++vcpu->stat.pf_guest;
6389ee94
AK		 352 vcpu->arch.cr2 = fault->address;
353 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 354}
27d6c865 355EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 356
6389ee94 357void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 358{
6389ee94
AK		 359 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
360 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 361 else
6389ee94 362 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
d4f8cf66
JR		 363}
364
3419ffc8
SY		 365void kvm_inject_nmi(struct kvm_vcpu *vcpu)
366{
7460fb4a
AK		 367 atomic_inc(&vcpu->arch.nmi_queued);
368 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 369}
370EXPORT_SYMBOL_GPL(kvm_inject_nmi);
371
298101da
AK		 372void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
373{
ce7ddec4 374 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 375}
376EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
377
ce7ddec4
JR		 378void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
379{
380 kvm_multiple_exception(vcpu, nr, true, error_code, true);
381}
382EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
383
0a79b009
AK		 384/*
385 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
386 * a #GP and return false.
387 */
388bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 389{
0a79b009
AK		 390 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
391 return true;
392 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
393 return false;
298101da 394}
0a79b009 395EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 396
ec92fe44
JR		 397/*
398 * This function will be used to read from the physical memory of the currently
399 * running guest. The difference to kvm_read_guest_page is that this function
400 * can read from guest physical or from the guest's guest physical memory.
401 */
402int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
403 gfn_t ngfn, void *data, int offset, int len,
404 u32 access)
405{
406 gfn_t real_gfn;
407 gpa_t ngpa;
408
409 ngpa = gfn_to_gpa(ngfn);
410 real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
411 if (real_gfn == UNMAPPED_GVA)
412 return -EFAULT;
413
414 real_gfn = gpa_to_gfn(real_gfn);
415
416 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
417}
418EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
419
3d06b8bf
JR		 420int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
421 void *data, int offset, int len, u32 access)
422{
423 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
424 data, offset, len, access);
425}
426
a03490ed
CO		 427/*
428 * Load the pae pdptrs. Return true is they are all valid.
429 */
ff03a073 430int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 431{
432 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
433 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
434 int i;
435 int ret;
ff03a073 436 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 437
ff03a073
JR		 438 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
439 offset * sizeof(u64), sizeof(pdpte),
440 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 441 if (ret < 0) {
442 ret = 0;
443 goto out;
444 }
445 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 446 if (is_present_gpte(pdpte[i]) &&
20c466b5 447 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 448 ret = 0;
449 goto out;
450 }
451 }
452 ret = 1;
453
ff03a073 454 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 455 __set_bit(VCPU_EXREG_PDPTR,
456 (unsigned long *)&vcpu->arch.regs_avail);
457 __set_bit(VCPU_EXREG_PDPTR,
458 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 459out:
a03490ed
CO		 460
461 return ret;
462}
cc4b6871 463EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 464
d835dfec
AK		 465static bool pdptrs_changed(struct kvm_vcpu *vcpu)
466{
ff03a073 467 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 468 bool changed = true;
3d06b8bf
JR		 469 int offset;
470 gfn_t gfn;
d835dfec
AK		 471 int r;
472
473 if (is_long_mode(vcpu) || !is_pae(vcpu))
474 return false;
475
6de4f3ad
AK		 476 if (!test_bit(VCPU_EXREG_PDPTR,
477 (unsigned long *)&vcpu->arch.regs_avail))
478 return true;
479
9f8fe504
AK		 480 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
481 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 482 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
483 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 484 if (r < 0)
485 goto out;
ff03a073 486 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 487out:
d835dfec
AK		 488
489 return changed;
490}
491
49a9b07e 492int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 493{
aad82703
SY		 494 unsigned long old_cr0 = kvm_read_cr0(vcpu);
495 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
496 X86_CR0_CD | X86_CR0_NW;
497
f9a48e6a
AK		 498 cr0 |= X86_CR0_ET;
499
ab344828 500#ifdef CONFIG_X86_64
0f12244f
GN		 501 if (cr0 & 0xffffffff00000000UL)
502 return 1;
ab344828
GN		 503#endif
504
505 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 506
0f12244f
GN		 507 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
508 return 1;
a03490ed 509
0f12244f
GN		 510 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
511 return 1;
a03490ed
CO		 512
513 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
514#ifdef CONFIG_X86_64
f6801dff 515 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 516 int cs_db, cs_l;
517
0f12244f
GN		 518 if (!is_pae(vcpu))
519 return 1;
a03490ed 520 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 521 if (cs_l)
522 return 1;
a03490ed
CO		 523 } else
524#endif
ff03a073 525 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 526 kvm_read_cr3(vcpu)))
0f12244f 527 return 1;
a03490ed
CO		 528 }
529
530 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 531
d170c419 532 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 533 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 534 kvm_async_pf_hash_reset(vcpu);
535 }
e5f3f027 536
aad82703
SY		 537 if ((cr0 ^ old_cr0) & update_bits)
538 kvm_mmu_reset_context(vcpu);
0f12244f
GN		 539 return 0;
540}
2d3ad1f4 541EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 542
2d3ad1f4 543void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 544{
49a9b07e 545 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 546}
2d3ad1f4 547EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 548
2acf923e
DC		 549int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
550{
551 u64 xcr0;
552
553 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
554 if (index != XCR_XFEATURE_ENABLED_MASK)
555 return 1;
556 xcr0 = xcr;
557 if (kvm_x86_ops->get_cpl(vcpu) != 0)
558 return 1;
559 if (!(xcr0 & XSTATE_FP))
560 return 1;
561 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
562 return 1;
563 if (xcr0 & ~host_xcr0)
564 return 1;
565 vcpu->arch.xcr0 = xcr0;
566 vcpu->guest_xcr0_loaded = 0;
567 return 0;
568}
569
570int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
571{
572 if (__kvm_set_xcr(vcpu, index, xcr)) {
573 kvm_inject_gp(vcpu, 0);
574 return 1;
575 }
576 return 0;
577}
578EXPORT_SYMBOL_GPL(kvm_set_xcr);
579
a83b29c6 580int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 581{
fc78f519 582 unsigned long old_cr4 = kvm_read_cr4(vcpu);
c68b734f
YW		 583 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE |
584 X86_CR4_PAE | X86_CR4_SMEP;
0f12244f
GN		 585 if (cr4 & CR4_RESERVED_BITS)
586 return 1;
a03490ed 587
2acf923e
DC		 588 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
589 return 1;
590
c68b734f
YW		 591 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
592 return 1;
593
74dc2b4f
YW		 594 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_RDWRGSFS))
595 return 1;
596
a03490ed 597 if (is_long_mode(vcpu)) {
0f12244f
GN		 598 if (!(cr4 & X86_CR4_PAE))
599 return 1;
a2edf57f
AK		 600 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
601 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 602 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
603 kvm_read_cr3(vcpu)))
0f12244f
GN		 604 return 1;
605
5e1746d6 606 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 607 return 1;
a03490ed 608
aad82703
SY		 609 if ((cr4 ^ old_cr4) & pdptr_bits)
610 kvm_mmu_reset_context(vcpu);
0f12244f 611
2acf923e 612 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
00b27a3e 613 kvm_update_cpuid(vcpu);
2acf923e 614
0f12244f
GN		 615 return 0;
616}
2d3ad1f4 617EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 618
2390218b 619int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 620{
9f8fe504 621 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 622 kvm_mmu_sync_roots(vcpu);
d835dfec 623 kvm_mmu_flush_tlb(vcpu);
0f12244f 624 return 0;
d835dfec
AK		 625 }
626
a03490ed 627 if (is_long_mode(vcpu)) {
0f12244f
GN		 628 if (cr3 & CR3_L_MODE_RESERVED_BITS)
629 return 1;
a03490ed
CO		 630 } else {
631 if (is_pae(vcpu)) {
0f12244f
GN		 632 if (cr3 & CR3_PAE_RESERVED_BITS)
633 return 1;
ff03a073
JR		 634 if (is_paging(vcpu) &&
635 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
0f12244f 636 return 1;
a03490ed
CO		 637 }
638 /*
639 * We don't check reserved bits in nonpae mode, because
640 * this isn't enforced, and VMware depends on this.
641 */
642 }
643
a03490ed
CO		 644 /*
645 * Does the new cr3 value map to physical memory? (Note, we
646 * catch an invalid cr3 even in real-mode, because it would
647 * cause trouble later on when we turn on paging anyway.)
648 *
649 * A real CPU would silently accept an invalid cr3 and would
650 * attempt to use it - with largely undefined (and often hard
651 * to debug) behavior on the guest side.
652 */
653 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
0f12244f
GN		 654 return 1;
655 vcpu->arch.cr3 = cr3;
aff48baa 656 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
0f12244f
GN		 657 vcpu->arch.mmu.new_cr3(vcpu);
658 return 0;
659}
2d3ad1f4 660EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 661
eea1cff9 662int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 663{
0f12244f
GN		 664 if (cr8 & CR8_RESERVED_BITS)
665 return 1;
a03490ed
CO		 666 if (irqchip_in_kernel(vcpu->kvm))
667 kvm_lapic_set_tpr(vcpu, cr8);
668 else
ad312c7c 669 vcpu->arch.cr8 = cr8;
0f12244f
GN		 670 return 0;
671}
2d3ad1f4 672EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 673
2d3ad1f4 674unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 675{
676 if (irqchip_in_kernel(vcpu->kvm))
677 return kvm_lapic_get_cr8(vcpu);
678 else
ad312c7c 679 return vcpu->arch.cr8;
a03490ed 680}
2d3ad1f4 681EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 682
338dbc97 683static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 684{
685 switch (dr) {
686 case 0 ... 3:
687 vcpu->arch.db[dr] = val;
688 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
689 vcpu->arch.eff_db[dr] = val;
690 break;
691 case 4:
338dbc97
GN		 692 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
693 return 1; /* #UD */
020df079
GN		 694 /* fall through */
695 case 6:
338dbc97
GN		 696 if (val & 0xffffffff00000000ULL)
697 return -1; /* #GP */
020df079
GN		 698 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
699 break;
700 case 5:
338dbc97
GN		 701 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
702 return 1; /* #UD */
020df079
GN		 703 /* fall through */
704 default: /* 7 */
338dbc97
GN		 705 if (val & 0xffffffff00000000ULL)
706 return -1; /* #GP */
020df079
GN		 707 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
708 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
709 kvm_x86_ops->set_dr7(vcpu, vcpu->arch.dr7);
710 vcpu->arch.switch_db_regs = (val & DR7_BP_EN_MASK);
711 }
712 break;
713 }
714
715 return 0;
716}
338dbc97
GN		 717
718int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
719{
720 int res;
721
722 res = __kvm_set_dr(vcpu, dr, val);
723 if (res > 0)
724 kvm_queue_exception(vcpu, UD_VECTOR);
725 else if (res < 0)
726 kvm_inject_gp(vcpu, 0);
727
728 return res;
729}
020df079
GN		 730EXPORT_SYMBOL_GPL(kvm_set_dr);
731
338dbc97 732static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 733{
734 switch (dr) {
735 case 0 ... 3:
736 *val = vcpu->arch.db[dr];
737 break;
738 case 4:
338dbc97 739 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 740 return 1;
020df079
GN		 741 /* fall through */
742 case 6:
743 *val = vcpu->arch.dr6;
744 break;
745 case 5:
338dbc97 746 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 747 return 1;
020df079
GN		 748 /* fall through */
749 default: /* 7 */
750 *val = vcpu->arch.dr7;
751 break;
752 }
753
754 return 0;
755}
338dbc97
GN		 756
757int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
758{
759 if (_kvm_get_dr(vcpu, dr, val)) {
760 kvm_queue_exception(vcpu, UD_VECTOR);
761 return 1;
762 }
763 return 0;
764}
020df079
GN		 765EXPORT_SYMBOL_GPL(kvm_get_dr);
766
022cd0e8
AK		 767bool kvm_rdpmc(struct kvm_vcpu *vcpu)
768{
769 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
770 u64 data;
771 int err;
772
773 err = kvm_pmu_read_pmc(vcpu, ecx, &data);
774 if (err)
775 return err;
776 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
777 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
778 return err;
779}
780EXPORT_SYMBOL_GPL(kvm_rdpmc);
781
043405e1
CO		 782/*
783 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
784 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
785 *
786 * This list is modified at module load time to reflect the
e3267cbb
GC		 787 * capabilities of the host cpu. This capabilities test skips MSRs that are
788 * kvm-specific. Those are put in the beginning of the list.
043405e1 789 */
e3267cbb 790
c9aaa895 791#define KVM_SAVE_MSRS_BEGIN 9
043405e1 792static u32 msrs_to_save[] = {
e3267cbb 793 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
11c6bffa 794 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
55cd8e5a 795 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
c9aaa895 796 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
043405e1 797 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 798 MSR_STAR,
043405e1
CO		 799#ifdef CONFIG_X86_64
800 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
801#endif
e90aa41e 802 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
043405e1
CO		 803};
804
805static unsigned num_msrs_to_save;
806
807static u32 emulated_msrs[] = {
a3e06bbe 808 MSR_IA32_TSCDEADLINE,
043405e1 809 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 810 MSR_IA32_MCG_STATUS,
811 MSR_IA32_MCG_CTL,
043405e1
CO		 812};
813
b69e8cae 814static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 815{
aad82703
SY		 816 u64 old_efer = vcpu->arch.efer;
817
b69e8cae
RJ		 818 if (efer & efer_reserved_bits)
819 return 1;
15c4a640
CO		 820
821 if (is_paging(vcpu)
b69e8cae
RJ		 822 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
823 return 1;
15c4a640 824
1b2fd70c
AG		 825 if (efer & EFER_FFXSR) {
826 struct kvm_cpuid_entry2 *feat;
827
828 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 829 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
830 return 1;
1b2fd70c
AG		 831 }
832
d8017474
AG		 833 if (efer & EFER_SVME) {
834 struct kvm_cpuid_entry2 *feat;
835
836 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 837 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
838 return 1;
d8017474
AG		 839 }
840
15c4a640 841 efer &= ~EFER_LMA;
f6801dff 842 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 843
a3d204e2
SY		 844 kvm_x86_ops->set_efer(vcpu, efer);
845
9645bb56 846 vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
b69e8cae 847
aad82703
SY		 848 /* Update reserved bits */
849 if ((efer ^ old_efer) & EFER_NX)
850 kvm_mmu_reset_context(vcpu);
851
b69e8cae 852 return 0;
15c4a640
CO		 853}
854
f2b4b7dd
JR		 855void kvm_enable_efer_bits(u64 mask)
856{
857 efer_reserved_bits &= ~mask;
858}
859EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
860
861
15c4a640
CO		 862/*
863 * Writes msr value into into the appropriate "register".
864 * Returns 0 on success, non-0 otherwise.
865 * Assumes vcpu_load() was already called.
866 */
867int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
868{
869 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
870}
871
313a3dc7
CO		 872/*
873 * Adapt set_msr() to msr_io()'s calling convention
874 */
875static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
876{
877 return kvm_set_msr(vcpu, index, *data);
878}
879
18068523
GOC		 880static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
881{
9ed3c444
AK		 882 int version;
883 int r;
50d0a0f9 884 struct pvclock_wall_clock wc;
923de3cf 885 struct timespec boot;
18068523
GOC		 886
887 if (!wall_clock)
888 return;
889
9ed3c444
AK		 890 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
891 if (r)
892 return;
893
894 if (version & 1)
895 ++version; /* first time write, random junk */
896
897 ++version;
18068523 898
18068523
GOC		 899 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
900
50d0a0f9
GH		 901 /*
902 * The guest calculates current wall clock time by adding
34c238a1 903 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 904 * wall clock specified here. guest system time equals host
905 * system time for us, thus we must fill in host boot time here.
906 */
923de3cf 907 getboottime(&boot);
50d0a0f9
GH		 908
909 wc.sec = boot.tv_sec;
910 wc.nsec = boot.tv_nsec;
911 wc.version = version;
18068523
GOC		 912
913 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
914
915 version++;
916 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 917}
918
50d0a0f9
GH		 919static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
920{
921 uint32_t quotient, remainder;
922
923 /* Don't try to replace with do_div(), this one calculates
924 * "(dividend << 32) / divisor" */
925 __asm__ ( "divl %4"
926 : "=a" (quotient), "=d" (remainder)
927 : "0" (0), "1" (dividend), "r" (divisor) );
928 return quotient;
929}
930
5f4e3f88
ZA		 931static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
932 s8 *pshift, u32 *pmultiplier)
50d0a0f9 933{
5f4e3f88 934 uint64_t scaled64;
50d0a0f9
GH		 935 int32_t shift = 0;
936 uint64_t tps64;
937 uint32_t tps32;
938
5f4e3f88
ZA		 939 tps64 = base_khz * 1000LL;
940 scaled64 = scaled_khz * 1000LL;
50933623 941 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 942 tps64 >>= 1;
943 shift--;
944 }
945
946 tps32 = (uint32_t)tps64;
50933623
JK		 947 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
948 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 949 scaled64 >>= 1;
950 else
951 tps32 <<= 1;
50d0a0f9
GH		 952 shift++;
953 }
954
5f4e3f88
ZA		 955 *pshift = shift;
956 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 957
5f4e3f88
ZA		 958 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
959 __func__, base_khz, scaled_khz, shift, *pmultiplier);
50d0a0f9
GH		 960}
961
759379dd
ZA		 962static inline u64 get_kernel_ns(void)
963{
964 struct timespec ts;
965
966 WARN_ON(preemptible());
967 ktime_get_ts(&ts);
968 monotonic_to_bootbased(&ts);
969 return timespec_to_ns(&ts);
50d0a0f9
GH		 970}
971
c8076604 972static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
c285545f 973unsigned long max_tsc_khz;
c8076604 974
cc578287 975static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
8cfdc000 976{
cc578287
ZA		 977 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
978 vcpu->arch.virtual_tsc_shift);
8cfdc000
ZA		 979}
980
cc578287 981static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 982{
cc578287
ZA		 983 u64 v = (u64)khz * (1000000 + ppm);
984 do_div(v, 1000000);
985 return v;
1e993611
JR		 986}
987
cc578287 988static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
759379dd 989{
cc578287
ZA		 990 u32 thresh_lo, thresh_hi;
991 int use_scaling = 0;
217fc9cf 992
c285545f
ZA		 993 /* Compute a scale to convert nanoseconds in TSC cycles */
994 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
cc578287
ZA		 995 &vcpu->arch.virtual_tsc_shift,
996 &vcpu->arch.virtual_tsc_mult);
997 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
998
999 /*
1000 * Compute the variation in TSC rate which is acceptable
1001 * within the range of tolerance and decide if the
1002 * rate being applied is within that bounds of the hardware
1003 * rate. If so, no scaling or compensation need be done.
1004 */
1005 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1006 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1007 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1008 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1009 use_scaling = 1;
1010 }
1011 kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
c285545f
ZA		 1012}
1013
1014static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1015{
e26101b1 1016 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1017 vcpu->arch.virtual_tsc_mult,
1018 vcpu->arch.virtual_tsc_shift);
e26101b1 1019 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1020 return tsc;
1021}
1022
99e3e30a
ZA		 1023void kvm_write_tsc(struct kvm_vcpu *vcpu, u64 data)
1024{
1025 struct kvm *kvm = vcpu->kvm;
f38e098f 1026 u64 offset, ns, elapsed;
99e3e30a 1027 unsigned long flags;
5d3cb0f6 1028 s64 nsdiff;
99e3e30a 1029
038f8c11 1030 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
857e4099 1031 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1032 ns = get_kernel_ns();
f38e098f 1033 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6
ZA		 1034
1035 /* n.b - signed multiplication and division required */
1036 nsdiff = data - kvm->arch.last_tsc_write;
1037#ifdef CONFIG_X86_64
1038 nsdiff = (nsdiff * 1000) / vcpu->arch.virtual_tsc_khz;
1039#else
1040 /* do_div() only does unsigned */
1041 asm("idivl %2; xor %%edx, %%edx"
1042 : "=A"(nsdiff)
1043 : "A"(nsdiff * 1000), "rm"(vcpu->arch.virtual_tsc_khz));
1044#endif
1045 nsdiff -= elapsed;
1046 if (nsdiff < 0)
1047 nsdiff = -nsdiff;
f38e098f
ZA		 1048
1049 /*
5d3cb0f6
ZA		 1050 * Special case: TSC write with a small delta (1 second) of virtual
1051 * cycle time against real time is interpreted as an attempt to
1052 * synchronize the CPU.
1053 *
1054 * For a reliable TSC, we can match TSC offsets, and for an unstable
1055 * TSC, we add elapsed time in this computation. We could let the
1056 * compensation code attempt to catch up if we fall behind, but
1057 * it's better to try to match offsets from the beginning.
1058 */
1059 if (nsdiff < NSEC_PER_SEC &&
1060 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1061 if (!check_tsc_unstable()) {
e26101b1 1062 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1063 pr_debug("kvm: matched tsc offset for %llu\n", data);
1064 } else {
857e4099 1065 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6
ZA		 1066 data += delta;
1067 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1068 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1069 }
e26101b1
ZA		 1070 } else {
1071 /*
1072 * We split periods of matched TSC writes into generations.
1073 * For each generation, we track the original measured
1074 * nanosecond time, offset, and write, so if TSCs are in
1075 * sync, we can match exact offset, and if not, we can match
1076 * exact software computaion in compute_guest_tsc()
1077 *
1078 * These values are tracked in kvm->arch.cur_xxx variables.
1079 */
1080 kvm->arch.cur_tsc_generation++;
1081 kvm->arch.cur_tsc_nsec = ns;
1082 kvm->arch.cur_tsc_write = data;
1083 kvm->arch.cur_tsc_offset = offset;
1084 pr_debug("kvm: new tsc generation %u, clock %llu\n",
1085 kvm->arch.cur_tsc_generation, data);
f38e098f 1086 }
e26101b1
ZA		 1087
1088 /*
1089 * We also track th most recent recorded KHZ, write and time to
1090 * allow the matching interval to be extended at each write.
1091 */
f38e098f
ZA		 1092 kvm->arch.last_tsc_nsec = ns;
1093 kvm->arch.last_tsc_write = data;
5d3cb0f6 1094 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a
ZA		 1095
1096 /* Reset of TSC must disable overshoot protection below */
1097 vcpu->arch.hv_clock.tsc_timestamp = 0;
b183aa58 1098 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1099
1100 /* Keep track of which generation this VCPU has synchronized to */
1101 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1102 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1103 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1104
1105 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1106 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
99e3e30a 1107}
e26101b1 1108
99e3e30a
ZA		 1109EXPORT_SYMBOL_GPL(kvm_write_tsc);
1110
34c238a1 1111static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1112{
18068523
GOC		 1113 unsigned long flags;
1114 struct kvm_vcpu_arch *vcpu = &v->arch;
1115 void *shared_kaddr;
463656c0 1116 unsigned long this_tsc_khz;
1d5f066e
ZA		 1117 s64 kernel_ns, max_kernel_ns;
1118 u64 tsc_timestamp;
18068523 1119
18068523
GOC		 1120 /* Keep irq disabled to prevent changes to the clock */
1121 local_irq_save(flags);
d5c1785d 1122 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v);
759379dd 1123 kernel_ns = get_kernel_ns();
cc578287 1124 this_tsc_khz = __get_cpu_var(cpu_tsc_khz);
8cfdc000 1125 if (unlikely(this_tsc_khz == 0)) {
c285545f 1126 local_irq_restore(flags);
34c238a1 1127 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
8cfdc000
ZA		 1128 return 1;
1129 }
18068523 1130
c285545f
ZA		 1131 /*
1132 * We may have to catch up the TSC to match elapsed wall clock
1133 * time for two reasons, even if kvmclock is used.
1134 * 1) CPU could have been running below the maximum TSC rate
1135 * 2) Broken TSC compensation resets the base at each VCPU
1136 * entry to avoid unknown leaps of TSC even when running
1137 * again on the same CPU. This may cause apparent elapsed
1138 * time to disappear, and the guest to stand still or run
1139 * very slowly.
1140 */
1141 if (vcpu->tsc_catchup) {
1142 u64 tsc = compute_guest_tsc(v, kernel_ns);
1143 if (tsc > tsc_timestamp) {
f1e2b260 1144 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1145 tsc_timestamp = tsc;
1146 }
50d0a0f9
GH		 1147 }
1148
18068523
GOC		 1149 local_irq_restore(flags);
1150
c285545f
ZA		 1151 if (!vcpu->time_page)
1152 return 0;
18068523 1153
1d5f066e
ZA		 1154 /*
1155 * Time as measured by the TSC may go backwards when resetting the base
1156 * tsc_timestamp. The reason for this is that the TSC resolution is
1157 * higher than the resolution of the other clock scales. Thus, many
1158 * possible measurments of the TSC correspond to one measurement of any
1159 * other clock, and so a spread of values is possible. This is not a
1160 * problem for the computation of the nanosecond clock; with TSC rates
1161 * around 1GHZ, there can only be a few cycles which correspond to one
1162 * nanosecond value, and any path through this code will inevitably
1163 * take longer than that. However, with the kernel_ns value itself,
1164 * the precision may be much lower, down to HZ granularity. If the
1165 * first sampling of TSC against kernel_ns ends in the low part of the
1166 * range, and the second in the high end of the range, we can get:
1167 *
1168 * (TSC - offset_low) * S + kns_old > (TSC - offset_high) * S + kns_new
1169 *
1170 * As the sampling errors potentially range in the thousands of cycles,
1171 * it is possible such a time value has already been observed by the
1172 * guest. To protect against this, we must compute the system time as
1173 * observed by the guest and ensure the new system time is greater.
1174 */
1175 max_kernel_ns = 0;
b183aa58 1176 if (vcpu->hv_clock.tsc_timestamp) {
1d5f066e
ZA		 1177 max_kernel_ns = vcpu->last_guest_tsc -
1178 vcpu->hv_clock.tsc_timestamp;
1179 max_kernel_ns = pvclock_scale_delta(max_kernel_ns,
1180 vcpu->hv_clock.tsc_to_system_mul,
1181 vcpu->hv_clock.tsc_shift);
1182 max_kernel_ns += vcpu->last_kernel_ns;
1183 }
afbcf7ab 1184
e48672fa 1185 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
5f4e3f88
ZA		 1186 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1187 &vcpu->hv_clock.tsc_shift,
1188 &vcpu->hv_clock.tsc_to_system_mul);
e48672fa 1189 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1190 }
1191
1d5f066e
ZA		 1192 if (max_kernel_ns > kernel_ns)
1193 kernel_ns = max_kernel_ns;
1194
8cfdc000 1195 /* With all the info we got, fill in the values */
1d5f066e 1196 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1197 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1d5f066e 1198 vcpu->last_kernel_ns = kernel_ns;
28e4639a 1199 vcpu->last_guest_tsc = tsc_timestamp;
371bcf64
GC		 1200 vcpu->hv_clock.flags = 0;
1201
18068523
GOC		 1202 /*
1203 * The interface expects us to write an even number signaling that the
1204 * update is finished. Since the guest won't see the intermediate
50d0a0f9 1205 * state, we just increase by 2 at the end.
18068523 1206 */
50d0a0f9 1207 vcpu->hv_clock.version += 2;
18068523
GOC		 1208
1209 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
1210
1211 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
50d0a0f9 1212 sizeof(vcpu->hv_clock));
18068523
GOC		 1213
1214 kunmap_atomic(shared_kaddr, KM_USER0);
1215
1216 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
8cfdc000 1217 return 0;
c8076604
GH		 1218}
1219
9ba075a6
AK		 1220static bool msr_mtrr_valid(unsigned msr)
1221{
1222 switch (msr) {
1223 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1224 case MSR_MTRRfix64K_00000:
1225 case MSR_MTRRfix16K_80000:
1226 case MSR_MTRRfix16K_A0000:
1227 case MSR_MTRRfix4K_C0000:
1228 case MSR_MTRRfix4K_C8000:
1229 case MSR_MTRRfix4K_D0000:
1230 case MSR_MTRRfix4K_D8000:
1231 case MSR_MTRRfix4K_E0000:
1232 case MSR_MTRRfix4K_E8000:
1233 case MSR_MTRRfix4K_F0000:
1234 case MSR_MTRRfix4K_F8000:
1235 case MSR_MTRRdefType:
1236 case MSR_IA32_CR_PAT:
1237 return true;
1238 case 0x2f8:
1239 return true;
1240 }
1241 return false;
1242}
1243
d6289b93
MT		 1244static bool valid_pat_type(unsigned t)
1245{
1246 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1247}
1248
1249static bool valid_mtrr_type(unsigned t)
1250{
1251 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1252}
1253
1254static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1255{
1256 int i;
1257
1258 if (!msr_mtrr_valid(msr))
1259 return false;
1260
1261 if (msr == MSR_IA32_CR_PAT) {
1262 for (i = 0; i < 8; i++)
1263 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1264 return false;
1265 return true;
1266 } else if (msr == MSR_MTRRdefType) {
1267 if (data & ~0xcff)
1268 return false;
1269 return valid_mtrr_type(data & 0xff);
1270 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1271 for (i = 0; i < 8 ; i++)
1272 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1273 return false;
1274 return true;
1275 }
1276
1277 /* variable MTRRs */
1278 return valid_mtrr_type(data & 0xff);
1279}
1280
9ba075a6
AK		 1281static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1282{
0bed3b56
SY		 1283 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1284
d6289b93 1285 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 1286 return 1;
1287
0bed3b56
SY		 1288 if (msr == MSR_MTRRdefType) {
1289 vcpu->arch.mtrr_state.def_type = data;
1290 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1291 } else if (msr == MSR_MTRRfix64K_00000)
1292 p[0] = data;
1293 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1294 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1295 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1296 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1297 else if (msr == MSR_IA32_CR_PAT)
1298 vcpu->arch.pat = data;
1299 else { /* Variable MTRRs */
1300 int idx, is_mtrr_mask;
1301 u64 *pt;
1302
1303 idx = (msr - 0x200) / 2;
1304 is_mtrr_mask = msr - 0x200 - 2 * idx;
1305 if (!is_mtrr_mask)
1306 pt =
1307 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1308 else
1309 pt =
1310 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1311 *pt = data;
1312 }
1313
1314 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 1315 return 0;
1316}
15c4a640 1317
890ca9ae 1318static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1319{
890ca9ae
HY		 1320 u64 mcg_cap = vcpu->arch.mcg_cap;
1321 unsigned bank_num = mcg_cap & 0xff;
1322
15c4a640 1323 switch (msr) {
15c4a640 1324 case MSR_IA32_MCG_STATUS:
890ca9ae 1325 vcpu->arch.mcg_status = data;
15c4a640 1326 break;
c7ac679c 1327 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1328 if (!(mcg_cap & MCG_CTL_P))
1329 return 1;
1330 if (data != 0 && data != ~(u64)0)
1331 return -1;
1332 vcpu->arch.mcg_ctl = data;
1333 break;
1334 default:
1335 if (msr >= MSR_IA32_MC0_CTL &&
1336 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1337 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1338 /* only 0 or all 1s can be written to IA32_MCi_CTL
1339 * some Linux kernels though clear bit 10 in bank 4 to
1340 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1341 * this to avoid an uncatched #GP in the guest
1342 */
890ca9ae 1343 if ((offset & 0x3) == 0 &&
114be429 1344 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1345 return -1;
1346 vcpu->arch.mce_banks[offset] = data;
1347 break;
1348 }
1349 return 1;
1350 }
1351 return 0;
1352}
1353
ffde22ac
ES		 1354static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1355{
1356 struct kvm *kvm = vcpu->kvm;
1357 int lm = is_long_mode(vcpu);
1358 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1359 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1360 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1361 : kvm->arch.xen_hvm_config.blob_size_32;
1362 u32 page_num = data & ~PAGE_MASK;
1363 u64 page_addr = data & PAGE_MASK;
1364 u8 *page;
1365 int r;
1366
1367 r = -E2BIG;
1368 if (page_num >= blob_size)
1369 goto out;
1370 r = -ENOMEM;
ff5c2c03
SL		 1371 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1372 if (IS_ERR(page)) {
1373 r = PTR_ERR(page);
ffde22ac 1374 goto out;
ff5c2c03 1375 }
ffde22ac
ES		 1376 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1377 goto out_free;
1378 r = 0;
1379out_free:
1380 kfree(page);
1381out:
1382 return r;
1383}
1384
55cd8e5a
GN		 1385static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1386{
1387 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1388}
1389
1390static bool kvm_hv_msr_partition_wide(u32 msr)
1391{
1392 bool r = false;
1393 switch (msr) {
1394 case HV_X64_MSR_GUEST_OS_ID:
1395 case HV_X64_MSR_HYPERCALL:
1396 r = true;
1397 break;
1398 }
1399
1400 return r;
1401}
1402
1403static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1404{
1405 struct kvm *kvm = vcpu->kvm;
1406
1407 switch (msr) {
1408 case HV_X64_MSR_GUEST_OS_ID:
1409 kvm->arch.hv_guest_os_id = data;
1410 /* setting guest os id to zero disables hypercall page */
1411 if (!kvm->arch.hv_guest_os_id)
1412 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1413 break;
1414 case HV_X64_MSR_HYPERCALL: {
1415 u64 gfn;
1416 unsigned long addr;
1417 u8 instructions[4];
1418
1419 /* if guest os id is not set hypercall should remain disabled */
1420 if (!kvm->arch.hv_guest_os_id)
1421 break;
1422 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1423 kvm->arch.hv_hypercall = data;
1424 break;
1425 }
1426 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1427 addr = gfn_to_hva(kvm, gfn);
1428 if (kvm_is_error_hva(addr))
1429 return 1;
1430 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1431 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
8b0cedff 1432 if (__copy_to_user((void __user *)addr, instructions, 4))
55cd8e5a
GN		 1433 return 1;
1434 kvm->arch.hv_hypercall = data;
1435 break;
1436 }
1437 default:
1438 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1439 "data 0x%llx\n", msr, data);
1440 return 1;
1441 }
1442 return 0;
1443}
1444
1445static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1446{
10388a07
GN		 1447 switch (msr) {
1448 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1449 unsigned long addr;
55cd8e5a 1450
10388a07
GN		 1451 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1452 vcpu->arch.hv_vapic = data;
1453 break;
1454 }
1455 addr = gfn_to_hva(vcpu->kvm, data >>
1456 HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1457 if (kvm_is_error_hva(addr))
1458 return 1;
8b0cedff 1459 if (__clear_user((void __user *)addr, PAGE_SIZE))
10388a07
GN		 1460 return 1;
1461 vcpu->arch.hv_vapic = data;
1462 break;
1463 }
1464 case HV_X64_MSR_EOI:
1465 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1466 case HV_X64_MSR_ICR:
1467 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1468 case HV_X64_MSR_TPR:
1469 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1470 default:
1471 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1472 "data 0x%llx\n", msr, data);
1473 return 1;
1474 }
1475
1476 return 0;
55cd8e5a
GN		 1477}
1478
344d9588
GN		 1479static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1480{
1481 gpa_t gpa = data & ~0x3f;
1482
6adba527
GN		 1483 /* Bits 2:5 are resrved, Should be zero */
1484 if (data & 0x3c)
344d9588
GN		 1485 return 1;
1486
1487 vcpu->arch.apf.msr_val = data;
1488
1489 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1490 kvm_clear_async_pf_completion_queue(vcpu);
1491 kvm_async_pf_hash_reset(vcpu);
1492 return 0;
1493 }
1494
1495 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa))
1496 return 1;
1497
6adba527 1498 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 1499 kvm_async_pf_wakeup_all(vcpu);
1500 return 0;
1501}
1502
12f9a48f
GC		 1503static void kvmclock_reset(struct kvm_vcpu *vcpu)
1504{
1505 if (vcpu->arch.time_page) {
1506 kvm_release_page_dirty(vcpu->arch.time_page);
1507 vcpu->arch.time_page = NULL;
1508 }
1509}
1510
c9aaa895
GC		 1511static void accumulate_steal_time(struct kvm_vcpu *vcpu)
1512{
1513 u64 delta;
1514
1515 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1516 return;
1517
1518 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
1519 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1520 vcpu->arch.st.accum_steal = delta;
1521}
1522
1523static void record_steal_time(struct kvm_vcpu *vcpu)
1524{
1525 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1526 return;
1527
1528 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1529 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
1530 return;
1531
1532 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
1533 vcpu->arch.st.steal.version += 2;
1534 vcpu->arch.st.accum_steal = 0;
1535
1536 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1537 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
1538}
1539
15c4a640
CO		 1540int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1541{
5753785f
GN		 1542 bool pr = false;
1543
15c4a640 1544 switch (msr) {
15c4a640 1545 case MSR_EFER:
b69e8cae 1546 return set_efer(vcpu, data);
8f1589d9
AP		 1547 case MSR_K7_HWCR:
1548 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 1549 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 1550 data &= ~(u64)0x8; /* ignore TLB cache disable */
8f1589d9
AP		 1551 if (data != 0) {
1552 pr_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1553 data);
1554 return 1;
1555 }
15c4a640 1556 break;
f7c6d140
AP		 1557 case MSR_FAM10H_MMIO_CONF_BASE:
1558 if (data != 0) {
1559 pr_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1560 "0x%llx\n", data);
1561 return 1;
1562 }
15c4a640 1563 break;
c323c0e5 1564 case MSR_AMD64_NB_CFG:
c7ac679c 1565 break;
b5e2fec0
AG		 1566 case MSR_IA32_DEBUGCTLMSR:
1567 if (!data) {
1568 /* We support the non-activated case already */
1569 break;
1570 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1571 /* Values other than LBR and BTF are vendor-specific,
1572 thus reserved and should throw a #GP */
1573 return 1;
1574 }
1575 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1576 __func__, data);
1577 break;
15c4a640
CO		 1578 case MSR_IA32_UCODE_REV:
1579 case MSR_IA32_UCODE_WRITE:
61a6bd67 1580 case MSR_VM_HSAVE_PA:
6098ca93 1581 case MSR_AMD64_PATCH_LOADER:
15c4a640 1582 break;
9ba075a6
AK		 1583 case 0x200 ... 0x2ff:
1584 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 1585 case MSR_IA32_APICBASE:
1586 kvm_set_apic_base(vcpu, data);
1587 break;
0105d1a5
GN		 1588 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1589 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 1590 case MSR_IA32_TSCDEADLINE:
1591 kvm_set_lapic_tscdeadline_msr(vcpu, data);
1592 break;
15c4a640 1593 case MSR_IA32_MISC_ENABLE:
ad312c7c 1594 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 1595 break;
11c6bffa 1596 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1597 case MSR_KVM_WALL_CLOCK:
1598 vcpu->kvm->arch.wall_clock = data;
1599 kvm_write_wall_clock(vcpu->kvm, data);
1600 break;
11c6bffa 1601 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 1602 case MSR_KVM_SYSTEM_TIME: {
12f9a48f 1603 kvmclock_reset(vcpu);
18068523
GOC		 1604
1605 vcpu->arch.time = data;
c285545f 1606 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
18068523
GOC		 1607
1608 /* we verify if the enable bit is set... */
1609 if (!(data & 1))
1610 break;
1611
1612 /* ...but clean it before doing the actual write */
1613 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
1614
18068523
GOC		 1615 vcpu->arch.time_page =
1616 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
18068523
GOC		 1617
1618 if (is_error_page(vcpu->arch.time_page)) {
1619 kvm_release_page_clean(vcpu->arch.time_page);
1620 vcpu->arch.time_page = NULL;
1621 }
18068523
GOC		 1622 break;
1623 }
344d9588
GN		 1624 case MSR_KVM_ASYNC_PF_EN:
1625 if (kvm_pv_enable_async_pf(vcpu, data))
1626 return 1;
1627 break;
c9aaa895
GC		 1628 case MSR_KVM_STEAL_TIME:
1629
1630 if (unlikely(!sched_info_on()))
1631 return 1;
1632
1633 if (data & KVM_STEAL_RESERVED_MASK)
1634 return 1;
1635
1636 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
1637 data & KVM_STEAL_VALID_BITS))
1638 return 1;
1639
1640 vcpu->arch.st.msr_val = data;
1641
1642 if (!(data & KVM_MSR_ENABLED))
1643 break;
1644
1645 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1646
1647 preempt_disable();
1648 accumulate_steal_time(vcpu);
1649 preempt_enable();
1650
1651 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
1652
1653 break;
1654
890ca9ae
HY		 1655 case MSR_IA32_MCG_CTL:
1656 case MSR_IA32_MCG_STATUS:
1657 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1658 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 1659
1660 /* Performance counters are not protected by a CPUID bit,
1661 * so we should check all of them in the generic path for the sake of
1662 * cross vendor migration.
1663 * Writing a zero into the event select MSRs disables them,
1664 * which we perfectly emulate ;-). Any other value should be at least
1665 * reported, some guests depend on them.
1666 */
71db6023
AP		 1667 case MSR_K7_EVNTSEL0:
1668 case MSR_K7_EVNTSEL1:
1669 case MSR_K7_EVNTSEL2:
1670 case MSR_K7_EVNTSEL3:
1671 if (data != 0)
1672 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1673 "0x%x data 0x%llx\n", msr, data);
1674 break;
1675 /* at least RHEL 4 unconditionally writes to the perfctr registers,
1676 * so we ignore writes to make it happy.
1677 */
71db6023
AP		 1678 case MSR_K7_PERFCTR0:
1679 case MSR_K7_PERFCTR1:
1680 case MSR_K7_PERFCTR2:
1681 case MSR_K7_PERFCTR3:
1682 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1683 "0x%x data 0x%llx\n", msr, data);
1684 break;
5753785f
GN		 1685 case MSR_P6_PERFCTR0:
1686 case MSR_P6_PERFCTR1:
1687 pr = true;
1688 case MSR_P6_EVNTSEL0:
1689 case MSR_P6_EVNTSEL1:
1690 if (kvm_pmu_msr(vcpu, msr))
1691 return kvm_pmu_set_msr(vcpu, msr, data);
1692
1693 if (pr || data != 0)
1694 pr_unimpl(vcpu, "disabled perfctr wrmsr: "
1695 "0x%x data 0x%llx\n", msr, data);
1696 break;
84e0cefa
JS		 1697 case MSR_K7_CLK_CTL:
1698 /*
1699 * Ignore all writes to this no longer documented MSR.
1700 * Writes are only relevant for old K7 processors,
1701 * all pre-dating SVM, but a recommended workaround from
1702 * AMD for these chips. It is possible to speicify the
1703 * affected processor models on the command line, hence
1704 * the need to ignore the workaround.
1705 */
1706 break;
55cd8e5a
GN		 1707 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1708 if (kvm_hv_msr_partition_wide(msr)) {
1709 int r;
1710 mutex_lock(&vcpu->kvm->lock);
1711 r = set_msr_hyperv_pw(vcpu, msr, data);
1712 mutex_unlock(&vcpu->kvm->lock);
1713 return r;
1714 } else
1715 return set_msr_hyperv(vcpu, msr, data);
1716 break;
91c9c3ed 1717 case MSR_IA32_BBL_CR_CTL3:
1718 /* Drop writes to this legacy MSR -- see rdmsr
1719 * counterpart for further detail.
1720 */
1721 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
1722 break;
2b036c6b
BO		 1723 case MSR_AMD64_OSVW_ID_LENGTH:
1724 if (!guest_cpuid_has_osvw(vcpu))
1725 return 1;
1726 vcpu->arch.osvw.length = data;
1727 break;
1728 case MSR_AMD64_OSVW_STATUS:
1729 if (!guest_cpuid_has_osvw(vcpu))
1730 return 1;
1731 vcpu->arch.osvw.status = data;
1732 break;
15c4a640 1733 default:
ffde22ac
ES		 1734 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
1735 return xen_hvm_config(vcpu, data);
f5132b01
GN		 1736 if (kvm_pmu_msr(vcpu, msr))
1737 return kvm_pmu_set_msr(vcpu, msr, data);
ed85c068
AP		 1738 if (!ignore_msrs) {
1739 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
1740 msr, data);
1741 return 1;
1742 } else {
1743 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
1744 msr, data);
1745 break;
1746 }
15c4a640
CO		 1747 }
1748 return 0;
1749}
1750EXPORT_SYMBOL_GPL(kvm_set_msr_common);
1751
1752
1753/*
1754 * Reads an msr value (of 'msr_index') into 'pdata'.
1755 * Returns 0 on success, non-0 otherwise.
1756 * Assumes vcpu_load() was already called.
1757 */
1758int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1759{
1760 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
1761}
1762
9ba075a6
AK		 1763static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1764{
0bed3b56
SY		 1765 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1766
9ba075a6
AK		 1767 if (!msr_mtrr_valid(msr))
1768 return 1;
1769
0bed3b56
SY		 1770 if (msr == MSR_MTRRdefType)
1771 *pdata = vcpu->arch.mtrr_state.def_type +
1772 (vcpu->arch.mtrr_state.enabled << 10);
1773 else if (msr == MSR_MTRRfix64K_00000)
1774 *pdata = p[0];
1775 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1776 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
1777 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1778 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
1779 else if (msr == MSR_IA32_CR_PAT)
1780 *pdata = vcpu->arch.pat;
1781 else { /* Variable MTRRs */
1782 int idx, is_mtrr_mask;
1783 u64 *pt;
1784
1785 idx = (msr - 0x200) / 2;
1786 is_mtrr_mask = msr - 0x200 - 2 * idx;
1787 if (!is_mtrr_mask)
1788 pt =
1789 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1790 else
1791 pt =
1792 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1793 *pdata = *pt;
1794 }
1795
9ba075a6
AK		 1796 return 0;
1797}
1798
890ca9ae 1799static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 1800{
1801 u64 data;
890ca9ae
HY		 1802 u64 mcg_cap = vcpu->arch.mcg_cap;
1803 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 1804
1805 switch (msr) {
15c4a640
CO		 1806 case MSR_IA32_P5_MC_ADDR:
1807 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 1808 data = 0;
1809 break;
15c4a640 1810 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 1811 data = vcpu->arch.mcg_cap;
1812 break;
c7ac679c 1813 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1814 if (!(mcg_cap & MCG_CTL_P))
1815 return 1;
1816 data = vcpu->arch.mcg_ctl;
1817 break;
1818 case MSR_IA32_MCG_STATUS:
1819 data = vcpu->arch.mcg_status;
1820 break;
1821 default:
1822 if (msr >= MSR_IA32_MC0_CTL &&
1823 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1824 u32 offset = msr - MSR_IA32_MC0_CTL;
1825 data = vcpu->arch.mce_banks[offset];
1826 break;
1827 }
1828 return 1;
1829 }
1830 *pdata = data;
1831 return 0;
1832}
1833
55cd8e5a
GN		 1834static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1835{
1836 u64 data = 0;
1837 struct kvm *kvm = vcpu->kvm;
1838
1839 switch (msr) {
1840 case HV_X64_MSR_GUEST_OS_ID:
1841 data = kvm->arch.hv_guest_os_id;
1842 break;
1843 case HV_X64_MSR_HYPERCALL:
1844 data = kvm->arch.hv_hypercall;
1845 break;
1846 default:
1847 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1848 return 1;
1849 }
1850
1851 *pdata = data;
1852 return 0;
1853}
1854
1855static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1856{
1857 u64 data = 0;
1858
1859 switch (msr) {
1860 case HV_X64_MSR_VP_INDEX: {
1861 int r;
1862 struct kvm_vcpu *v;
1863 kvm_for_each_vcpu(r, v, vcpu->kvm)
1864 if (v == vcpu)
1865 data = r;
1866 break;
1867 }
10388a07
GN		 1868 case HV_X64_MSR_EOI:
1869 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
1870 case HV_X64_MSR_ICR:
1871 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
1872 case HV_X64_MSR_TPR:
1873 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
14fa67ee 1874 case HV_X64_MSR_APIC_ASSIST_PAGE:
d1613ad5
MW		 1875 data = vcpu->arch.hv_vapic;
1876 break;
55cd8e5a
GN		 1877 default:
1878 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1879 return 1;
1880 }
1881 *pdata = data;
1882 return 0;
1883}
1884
890ca9ae
HY		 1885int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1886{
1887 u64 data;
1888
1889 switch (msr) {
890ca9ae 1890 case MSR_IA32_PLATFORM_ID:
15c4a640 1891 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 1892 case MSR_IA32_DEBUGCTLMSR:
1893 case MSR_IA32_LASTBRANCHFROMIP:
1894 case MSR_IA32_LASTBRANCHTOIP:
1895 case MSR_IA32_LASTINTFROMIP:
1896 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 1897 case MSR_K8_SYSCFG:
1898 case MSR_K7_HWCR:
61a6bd67 1899 case MSR_VM_HSAVE_PA:
9e699624 1900 case MSR_K7_EVNTSEL0:
1f3ee616 1901 case MSR_K7_PERFCTR0:
1fdbd48c 1902 case MSR_K8_INT_PENDING_MSG:
c323c0e5 1903 case MSR_AMD64_NB_CFG:
f7c6d140 1904 case MSR_FAM10H_MMIO_CONF_BASE:
15c4a640
CO		 1905 data = 0;
1906 break;
5753785f
GN		 1907 case MSR_P6_PERFCTR0:
1908 case MSR_P6_PERFCTR1:
1909 case MSR_P6_EVNTSEL0:
1910 case MSR_P6_EVNTSEL1:
1911 if (kvm_pmu_msr(vcpu, msr))
1912 return kvm_pmu_get_msr(vcpu, msr, pdata);
1913 data = 0;
1914 break;
742bc670
MT		 1915 case MSR_IA32_UCODE_REV:
1916 data = 0x100000000ULL;
1917 break;
9ba075a6
AK		 1918 case MSR_MTRRcap:
1919 data = 0x500 | KVM_NR_VAR_MTRR;
1920 break;
1921 case 0x200 ... 0x2ff:
1922 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 1923 case 0xcd: /* fsb frequency */
1924 data = 3;
1925 break;
7b914098
JS		 1926 /*
1927 * MSR_EBC_FREQUENCY_ID
1928 * Conservative value valid for even the basic CPU models.
1929 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
1930 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
1931 * and 266MHz for model 3, or 4. Set Core Clock
1932 * Frequency to System Bus Frequency Ratio to 1 (bits
1933 * 31:24) even though these are only valid for CPU
1934 * models > 2, however guests may end up dividing or
1935 * multiplying by zero otherwise.
1936 */
1937 case MSR_EBC_FREQUENCY_ID:
1938 data = 1 << 24;
1939 break;
15c4a640
CO		 1940 case MSR_IA32_APICBASE:
1941 data = kvm_get_apic_base(vcpu);
1942 break;
0105d1a5
GN		 1943 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1944 return kvm_x2apic_msr_read(vcpu, msr, pdata);
1945 break;
a3e06bbe
LJ		 1946 case MSR_IA32_TSCDEADLINE:
1947 data = kvm_get_lapic_tscdeadline_msr(vcpu);
1948 break;
15c4a640 1949 case MSR_IA32_MISC_ENABLE:
ad312c7c 1950 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 1951 break;
847f0ad8
AG		 1952 case MSR_IA32_PERF_STATUS:
1953 /* TSC increment by tick */
1954 data = 1000ULL;
1955 /* CPU multiplier */
1956 data |= (((uint64_t)4ULL) << 40);
1957 break;
15c4a640 1958 case MSR_EFER:
f6801dff 1959 data = vcpu->arch.efer;
15c4a640 1960 break;
18068523 1961 case MSR_KVM_WALL_CLOCK:
11c6bffa 1962 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1963 data = vcpu->kvm->arch.wall_clock;
1964 break;
1965 case MSR_KVM_SYSTEM_TIME:
11c6bffa 1966 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 1967 data = vcpu->arch.time;
1968 break;
344d9588
GN		 1969 case MSR_KVM_ASYNC_PF_EN:
1970 data = vcpu->arch.apf.msr_val;
1971 break;
c9aaa895
GC		 1972 case MSR_KVM_STEAL_TIME:
1973 data = vcpu->arch.st.msr_val;
1974 break;
890ca9ae
HY		 1975 case MSR_IA32_P5_MC_ADDR:
1976 case MSR_IA32_P5_MC_TYPE:
1977 case MSR_IA32_MCG_CAP:
1978 case MSR_IA32_MCG_CTL:
1979 case MSR_IA32_MCG_STATUS:
1980 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1981 return get_msr_mce(vcpu, msr, pdata);
84e0cefa
JS		 1982 case MSR_K7_CLK_CTL:
1983 /*
1984 * Provide expected ramp-up count for K7. All other
1985 * are set to zero, indicating minimum divisors for
1986 * every field.
1987 *
1988 * This prevents guest kernels on AMD host with CPU
1989 * type 6, model 8 and higher from exploding due to
1990 * the rdmsr failing.
1991 */
1992 data = 0x20000000;
1993 break;
55cd8e5a
GN		 1994 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1995 if (kvm_hv_msr_partition_wide(msr)) {
1996 int r;
1997 mutex_lock(&vcpu->kvm->lock);
1998 r = get_msr_hyperv_pw(vcpu, msr, pdata);
1999 mutex_unlock(&vcpu->kvm->lock);
2000 return r;
2001 } else
2002 return get_msr_hyperv(vcpu, msr, pdata);
2003 break;
91c9c3ed 2004 case MSR_IA32_BBL_CR_CTL3:
2005 /* This legacy MSR exists but isn't fully documented in current
2006 * silicon. It is however accessed by winxp in very narrow
2007 * scenarios where it sets bit #19, itself documented as
2008 * a "reserved" bit. Best effort attempt to source coherent
2009 * read data here should the balance of the register be
2010 * interpreted by the guest:
2011 *
2012 * L2 cache control register 3: 64GB range, 256KB size,
2013 * enabled, latency 0x1, configured
2014 */
2015 data = 0xbe702111;
2016 break;
2b036c6b
BO		 2017 case MSR_AMD64_OSVW_ID_LENGTH:
2018 if (!guest_cpuid_has_osvw(vcpu))
2019 return 1;
2020 data = vcpu->arch.osvw.length;
2021 break;
2022 case MSR_AMD64_OSVW_STATUS:
2023 if (!guest_cpuid_has_osvw(vcpu))
2024 return 1;
2025 data = vcpu->arch.osvw.status;
2026 break;
15c4a640 2027 default:
f5132b01
GN		 2028 if (kvm_pmu_msr(vcpu, msr))
2029 return kvm_pmu_get_msr(vcpu, msr, pdata);
ed85c068
AP		 2030 if (!ignore_msrs) {
2031 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
2032 return 1;
2033 } else {
2034 pr_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
2035 data = 0;
2036 }
2037 break;
15c4a640
CO		 2038 }
2039 *pdata = data;
2040 return 0;
2041}
2042EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2043
313a3dc7
CO		 2044/*
2045 * Read or write a bunch of msrs. All parameters are kernel addresses.
2046 *
2047 * @return number of msrs set successfully.
2048 */
2049static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2050 struct kvm_msr_entry *entries,
2051 int (*do_msr)(struct kvm_vcpu *vcpu,
2052 unsigned index, u64 *data))
2053{
f656ce01 2054 int i, idx;
313a3dc7 2055
f656ce01 2056 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2057 for (i = 0; i < msrs->nmsrs; ++i)
2058 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2059 break;
f656ce01 2060 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2061
313a3dc7
CO		 2062 return i;
2063}
2064
2065/*
2066 * Read or write a bunch of msrs. Parameters are user addresses.
2067 *
2068 * @return number of msrs set successfully.
2069 */
2070static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2071 int (*do_msr)(struct kvm_vcpu *vcpu,
2072 unsigned index, u64 *data),
2073 int writeback)
2074{
2075 struct kvm_msrs msrs;
2076 struct kvm_msr_entry *entries;
2077 int r, n;
2078 unsigned size;
2079
2080 r = -EFAULT;
2081 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2082 goto out;
2083
2084 r = -E2BIG;
2085 if (msrs.nmsrs >= MAX_IO_MSRS)
2086 goto out;
2087
313a3dc7 2088 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2089 entries = memdup_user(user_msrs->entries, size);
2090 if (IS_ERR(entries)) {
2091 r = PTR_ERR(entries);
313a3dc7 2092 goto out;
ff5c2c03 2093 }
313a3dc7
CO		 2094
2095 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2096 if (r < 0)
2097 goto out_free;
2098
2099 r = -EFAULT;
2100 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2101 goto out_free;
2102
2103 r = n;
2104
2105out_free:
7a73c028 2106 kfree(entries);
313a3dc7
CO		 2107out:
2108 return r;
2109}
2110
018d00d2
ZX		 2111int kvm_dev_ioctl_check_extension(long ext)
2112{
2113 int r;
2114
2115 switch (ext) {
2116 case KVM_CAP_IRQCHIP:
2117 case KVM_CAP_HLT:
2118 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2119 case KVM_CAP_SET_TSS_ADDR:
07716717 2120 case KVM_CAP_EXT_CPUID:
c8076604 2121 case KVM_CAP_CLOCKSOURCE:
7837699f 2122 case KVM_CAP_PIT:
a28e4f5a 2123 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2124 case KVM_CAP_MP_STATE:
ed848624 2125 case KVM_CAP_SYNC_MMU:
a355c85c 2126 case KVM_CAP_USER_NMI:
52d939a0 2127 case KVM_CAP_REINJECT_CONTROL:
4925663a 2128 case KVM_CAP_IRQ_INJECT_STATUS:
e56d532f 2129 case KVM_CAP_ASSIGN_DEV_IRQ:
721eecbf 2130 case KVM_CAP_IRQFD:
d34e6b17 2131 case KVM_CAP_IOEVENTFD:
c5ff41ce 2132 case KVM_CAP_PIT2:
e9f42757 2133 case KVM_CAP_PIT_STATE2:
b927a3ce 2134 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2135 case KVM_CAP_XEN_HVM:
afbcf7ab 2136 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 2137 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2138 case KVM_CAP_HYPERV:
10388a07 2139 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2140 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 2141 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2142 case KVM_CAP_DEBUGREGS:
d2be1651 2143 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2144 case KVM_CAP_XSAVE:
344d9588 2145 case KVM_CAP_ASYNC_PF:
92a1f12d 2146 case KVM_CAP_GET_TSC_KHZ:
07700a94 2147 case KVM_CAP_PCI_2_3:
018d00d2
ZX		 2148 r = 1;
2149 break;
542472b5
LV		 2150 case KVM_CAP_COALESCED_MMIO:
2151 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2152 break;
774ead3a
AK		 2153 case KVM_CAP_VAPIC:
2154 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2155 break;
f725230a 2156 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2157 r = KVM_SOFT_MAX_VCPUS;
2158 break;
2159 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2160 r = KVM_MAX_VCPUS;
2161 break;
a988b910
AK		 2162 case KVM_CAP_NR_MEMSLOTS:
2163 r = KVM_MEMORY_SLOTS;
2164 break;
a68a6a72
MT		 2165 case KVM_CAP_PV_MMU: /* obsolete */
2166 r = 0;
2f333bcb 2167 break;
62c476c7 2168 case KVM_CAP_IOMMU:
a1b60c1c 2169 r = iommu_present(&pci_bus_type);
62c476c7 2170 break;
890ca9ae
HY		 2171 case KVM_CAP_MCE:
2172 r = KVM_MAX_MCE_BANKS;
2173 break;
2d5b5a66
SY		 2174 case KVM_CAP_XCRS:
2175 r = cpu_has_xsave;
2176 break;
92a1f12d
JR		 2177 case KVM_CAP_TSC_CONTROL:
2178 r = kvm_has_tsc_control;
2179 break;
4d25a066
JK		 2180 case KVM_CAP_TSC_DEADLINE_TIMER:
2181 r = boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER);
2182 break;
018d00d2
ZX		 2183 default:
2184 r = 0;
2185 break;
2186 }
2187 return r;
2188
2189}
2190
043405e1
CO		 2191long kvm_arch_dev_ioctl(struct file *filp,
2192 unsigned int ioctl, unsigned long arg)
2193{
2194 void __user *argp = (void __user *)arg;
2195 long r;
2196
2197 switch (ioctl) {
2198 case KVM_GET_MSR_INDEX_LIST: {
2199 struct kvm_msr_list __user *user_msr_list = argp;
2200 struct kvm_msr_list msr_list;
2201 unsigned n;
2202
2203 r = -EFAULT;
2204 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2205 goto out;
2206 n = msr_list.nmsrs;
2207 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2208 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2209 goto out;
2210 r = -E2BIG;
e125e7b6 2211 if (n < msr_list.nmsrs)
043405e1
CO		 2212 goto out;
2213 r = -EFAULT;
2214 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2215 num_msrs_to_save * sizeof(u32)))
2216 goto out;
e125e7b6 2217 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 2218 &emulated_msrs,
2219 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2220 goto out;
2221 r = 0;
2222 break;
2223 }
674eea0f
AK		 2224 case KVM_GET_SUPPORTED_CPUID: {
2225 struct kvm_cpuid2 __user *cpuid_arg = argp;
2226 struct kvm_cpuid2 cpuid;
2227
2228 r = -EFAULT;
2229 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2230 goto out;
2231 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
19355475 2232 cpuid_arg->entries);
674eea0f
AK		 2233 if (r)
2234 goto out;
2235
2236 r = -EFAULT;
2237 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2238 goto out;
2239 r = 0;
2240 break;
2241 }
890ca9ae
HY		 2242 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2243 u64 mce_cap;
2244
2245 mce_cap = KVM_MCE_CAP_SUPPORTED;
2246 r = -EFAULT;
2247 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2248 goto out;
2249 r = 0;
2250 break;
2251 }
043405e1
CO		 2252 default:
2253 r = -EINVAL;
2254 }
2255out:
2256 return r;
2257}
2258
f5f48ee1
SY		 2259static void wbinvd_ipi(void *garbage)
2260{
2261 wbinvd();
2262}
2263
2264static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2265{
2266 return vcpu->kvm->arch.iommu_domain &&
2267 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY);
2268}
2269
313a3dc7
CO		 2270void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2271{
f5f48ee1
SY		 2272 /* Address WBINVD may be executed by guest */
2273 if (need_emulate_wbinvd(vcpu)) {
2274 if (kvm_x86_ops->has_wbinvd_exit())
2275 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2276 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2277 smp_call_function_single(vcpu->cpu,
2278 wbinvd_ipi, NULL, 1);
2279 }
2280
313a3dc7 2281 kvm_x86_ops->vcpu_load(vcpu, cpu);
0dd6a6ed
ZA		 2282
2283 /* Apply any externally detected TSC adjustments (due to suspend) */
2284 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2285 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2286 vcpu->arch.tsc_offset_adjustment = 0;
2287 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
2288 }
2289
48434c20 2290 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5
ZA		 2291 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2292 native_read_tsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2293 if (tsc_delta < 0)
2294 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 2295 if (check_tsc_unstable()) {
b183aa58
ZA		 2296 u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
2297 vcpu->arch.last_guest_tsc);
2298 kvm_x86_ops->write_tsc_offset(vcpu, offset);
c285545f 2299 vcpu->arch.tsc_catchup = 1;
c285545f 2300 }
1aa8ceef 2301 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c285545f
ZA		 2302 if (vcpu->cpu != cpu)
2303 kvm_migrate_timers(vcpu);
e48672fa 2304 vcpu->cpu = cpu;
6b7d7e76 2305 }
c9aaa895
GC		 2306
2307 accumulate_steal_time(vcpu);
2308 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2309}
2310
2311void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2312{
02daab21 2313 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2314 kvm_put_guest_fpu(vcpu);
6f526ec5 2315 vcpu->arch.last_host_tsc = native_read_tsc();
313a3dc7
CO		 2316}
2317
313a3dc7
CO		 2318static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2319 struct kvm_lapic_state *s)
2320{
ad312c7c 2321 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2322
2323 return 0;
2324}
2325
2326static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2327 struct kvm_lapic_state *s)
2328{
ad312c7c 2329 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
313a3dc7 2330 kvm_apic_post_state_restore(vcpu);
cb142eb7 2331 update_cr8_intercept(vcpu);
313a3dc7
CO		 2332
2333 return 0;
2334}
2335
f77bc6a4
ZX		 2336static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2337 struct kvm_interrupt *irq)
2338{
2339 if (irq->irq < 0 || irq->irq >= 256)
2340 return -EINVAL;
2341 if (irqchip_in_kernel(vcpu->kvm))
2342 return -ENXIO;
f77bc6a4 2343
66fd3f7f 2344 kvm_queue_interrupt(vcpu, irq->irq, false);
3842d135 2345 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4 2346
f77bc6a4
ZX		 2347 return 0;
2348}
2349
c4abb7c9
JK		 2350static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2351{
c4abb7c9 2352 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2353
2354 return 0;
2355}
2356
b209749f
AK		 2357static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2358 struct kvm_tpr_access_ctl *tac)
2359{
2360 if (tac->flags)
2361 return -EINVAL;
2362 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2363 return 0;
2364}
2365
890ca9ae
HY		 2366static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2367 u64 mcg_cap)
2368{
2369 int r;
2370 unsigned bank_num = mcg_cap & 0xff, bank;
2371
2372 r = -EINVAL;
a9e38c3e 2373 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2374 goto out;
2375 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2376 goto out;
2377 r = 0;
2378 vcpu->arch.mcg_cap = mcg_cap;
2379 /* Init IA32_MCG_CTL to all 1s */
2380 if (mcg_cap & MCG_CTL_P)
2381 vcpu->arch.mcg_ctl = ~(u64)0;
2382 /* Init IA32_MCi_CTL to all 1s */
2383 for (bank = 0; bank < bank_num; bank++)
2384 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2385out:
2386 return r;
2387}
2388
2389static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2390 struct kvm_x86_mce *mce)
2391{
2392 u64 mcg_cap = vcpu->arch.mcg_cap;
2393 unsigned bank_num = mcg_cap & 0xff;
2394 u64 *banks = vcpu->arch.mce_banks;
2395
2396 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2397 return -EINVAL;
2398 /*
2399 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2400 * reporting is disabled
2401 */
2402 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2403 vcpu->arch.mcg_ctl != ~(u64)0)
2404 return 0;
2405 banks += 4 * mce->bank;
2406 /*
2407 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2408 * reporting is disabled for the bank
2409 */
2410 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2411 return 0;
2412 if (mce->status & MCI_STATUS_UC) {
2413 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2414 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 2415 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2416 return 0;
2417 }
2418 if (banks[1] & MCI_STATUS_VAL)
2419 mce->status |= MCI_STATUS_OVER;
2420 banks[2] = mce->addr;
2421 banks[3] = mce->misc;
2422 vcpu->arch.mcg_status = mce->mcg_status;
2423 banks[1] = mce->status;
2424 kvm_queue_exception(vcpu, MC_VECTOR);
2425 } else if (!(banks[1] & MCI_STATUS_VAL)
2426 || !(banks[1] & MCI_STATUS_UC)) {
2427 if (banks[1] & MCI_STATUS_VAL)
2428 mce->status |= MCI_STATUS_OVER;
2429 banks[2] = mce->addr;
2430 banks[3] = mce->misc;
2431 banks[1] = mce->status;
2432 } else
2433 banks[1] |= MCI_STATUS_OVER;
2434 return 0;
2435}
2436
3cfc3092
JK		 2437static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2438 struct kvm_vcpu_events *events)
2439{
7460fb4a 2440 process_nmi(vcpu);
03b82a30
JK		 2441 events->exception.injected =
2442 vcpu->arch.exception.pending &&
2443 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2444 events->exception.nr = vcpu->arch.exception.nr;
2445 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 2446 events->exception.pad = 0;
3cfc3092
JK		 2447 events->exception.error_code = vcpu->arch.exception.error_code;
2448
03b82a30
JK		 2449 events->interrupt.injected =
2450 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2451 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2452 events->interrupt.soft = 0;
48005f64
JK		 2453 events->interrupt.shadow =
2454 kvm_x86_ops->get_interrupt_shadow(vcpu,
2455 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
3cfc3092
JK		 2456
2457 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 2458 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 2459 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 2460 events->nmi.pad = 0;
3cfc3092
JK		 2461
2462 events->sipi_vector = vcpu->arch.sipi_vector;
2463
dab4b911 2464 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2465 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2466 | KVM_VCPUEVENT_VALID_SHADOW);
97e69aa6 2467 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 2468}
2469
2470static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2471 struct kvm_vcpu_events *events)
2472{
dab4b911 2473 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2474 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2475 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 2476 return -EINVAL;
2477
7460fb4a 2478 process_nmi(vcpu);
3cfc3092
JK		 2479 vcpu->arch.exception.pending = events->exception.injected;
2480 vcpu->arch.exception.nr = events->exception.nr;
2481 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2482 vcpu->arch.exception.error_code = events->exception.error_code;
2483
2484 vcpu->arch.interrupt.pending = events->interrupt.injected;
2485 vcpu->arch.interrupt.nr = events->interrupt.nr;
2486 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 2487 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2488 kvm_x86_ops->set_interrupt_shadow(vcpu,
2489 events->interrupt.shadow);
3cfc3092
JK		 2490
2491 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2492 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2493 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2494 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2495
dab4b911
JK		 2496 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR)
2497 vcpu->arch.sipi_vector = events->sipi_vector;
3cfc3092 2498
3842d135
AK		 2499 kvm_make_request(KVM_REQ_EVENT, vcpu);
2500
3cfc3092
JK		 2501 return 0;
2502}
2503
a1efbe77
JK		 2504static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2505 struct kvm_debugregs *dbgregs)
2506{
a1efbe77
JK		 2507 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2508 dbgregs->dr6 = vcpu->arch.dr6;
2509 dbgregs->dr7 = vcpu->arch.dr7;
2510 dbgregs->flags = 0;
97e69aa6 2511 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 2512}
2513
2514static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2515 struct kvm_debugregs *dbgregs)
2516{
2517 if (dbgregs->flags)
2518 return -EINVAL;
2519
a1efbe77
JK		 2520 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2521 vcpu->arch.dr6 = dbgregs->dr6;
2522 vcpu->arch.dr7 = dbgregs->dr7;
2523
a1efbe77
JK		 2524 return 0;
2525}
2526
2d5b5a66
SY		 2527static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
2528 struct kvm_xsave *guest_xsave)
2529{
2530 if (cpu_has_xsave)
2531 memcpy(guest_xsave->region,
2532 &vcpu->arch.guest_fpu.state->xsave,
f45755b8 2533 xstate_size);
2d5b5a66
SY		 2534 else {
2535 memcpy(guest_xsave->region,
2536 &vcpu->arch.guest_fpu.state->fxsave,
2537 sizeof(struct i387_fxsave_struct));
2538 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
2539 XSTATE_FPSSE;
2540 }
2541}
2542
2543static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
2544 struct kvm_xsave *guest_xsave)
2545{
2546 u64 xstate_bv =
2547 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
2548
2549 if (cpu_has_xsave)
2550 memcpy(&vcpu->arch.guest_fpu.state->xsave,
f45755b8 2551 guest_xsave->region, xstate_size);
2d5b5a66
SY		 2552 else {
2553 if (xstate_bv & ~XSTATE_FPSSE)
2554 return -EINVAL;
2555 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
2556 guest_xsave->region, sizeof(struct i387_fxsave_struct));
2557 }
2558 return 0;
2559}
2560
2561static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
2562 struct kvm_xcrs *guest_xcrs)
2563{
2564 if (!cpu_has_xsave) {
2565 guest_xcrs->nr_xcrs = 0;
2566 return;
2567 }
2568
2569 guest_xcrs->nr_xcrs = 1;
2570 guest_xcrs->flags = 0;
2571 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
2572 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
2573}
2574
2575static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
2576 struct kvm_xcrs *guest_xcrs)
2577{
2578 int i, r = 0;
2579
2580 if (!cpu_has_xsave)
2581 return -EINVAL;
2582
2583 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
2584 return -EINVAL;
2585
2586 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
2587 /* Only support XCR0 currently */
2588 if (guest_xcrs->xcrs[0].xcr == XCR_XFEATURE_ENABLED_MASK) {
2589 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
2590 guest_xcrs->xcrs[0].value);
2591 break;
2592 }
2593 if (r)
2594 r = -EINVAL;
2595 return r;
2596}
2597
313a3dc7
CO		 2598long kvm_arch_vcpu_ioctl(struct file *filp,
2599 unsigned int ioctl, unsigned long arg)
2600{
2601 struct kvm_vcpu *vcpu = filp->private_data;
2602 void __user *argp = (void __user *)arg;
2603 int r;
d1ac91d8
AK		 2604 union {
2605 struct kvm_lapic_state *lapic;
2606 struct kvm_xsave *xsave;
2607 struct kvm_xcrs *xcrs;
2608 void *buffer;
2609 } u;
2610
2611 u.buffer = NULL;
313a3dc7
CO		 2612 switch (ioctl) {
2613 case KVM_GET_LAPIC: {
2204ae3c
MT		 2614 r = -EINVAL;
2615 if (!vcpu->arch.apic)
2616 goto out;
d1ac91d8 2617 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 2618
b772ff36 2619 r = -ENOMEM;
d1ac91d8 2620 if (!u.lapic)
b772ff36 2621 goto out;
d1ac91d8 2622 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 2623 if (r)
2624 goto out;
2625 r = -EFAULT;
d1ac91d8 2626 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 2627 goto out;
2628 r = 0;
2629 break;
2630 }
2631 case KVM_SET_LAPIC: {
2204ae3c
MT		 2632 r = -EINVAL;
2633 if (!vcpu->arch.apic)
2634 goto out;
ff5c2c03
SL		 2635 u.lapic = memdup_user(argp, sizeof(*u.lapic));
2636 if (IS_ERR(u.lapic)) {
2637 r = PTR_ERR(u.lapic);
313a3dc7 2638 goto out;
ff5c2c03
SL		 2639 }
2640
d1ac91d8 2641 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 2642 if (r)
2643 goto out;
2644 r = 0;
2645 break;
2646 }
f77bc6a4
ZX		 2647 case KVM_INTERRUPT: {
2648 struct kvm_interrupt irq;
2649
2650 r = -EFAULT;
2651 if (copy_from_user(&irq, argp, sizeof irq))
2652 goto out;
2653 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
2654 if (r)
2655 goto out;
2656 r = 0;
2657 break;
2658 }
c4abb7c9
JK		 2659 case KVM_NMI: {
2660 r = kvm_vcpu_ioctl_nmi(vcpu);
2661 if (r)
2662 goto out;
2663 r = 0;
2664 break;
2665 }
313a3dc7
CO		 2666 case KVM_SET_CPUID: {
2667 struct kvm_cpuid __user *cpuid_arg = argp;
2668 struct kvm_cpuid cpuid;
2669
2670 r = -EFAULT;
2671 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2672 goto out;
2673 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
2674 if (r)
2675 goto out;
2676 break;
2677 }
07716717
DK		 2678 case KVM_SET_CPUID2: {
2679 struct kvm_cpuid2 __user *cpuid_arg = argp;
2680 struct kvm_cpuid2 cpuid;
2681
2682 r = -EFAULT;
2683 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2684 goto out;
2685 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 2686 cpuid_arg->entries);
07716717
DK		 2687 if (r)
2688 goto out;
2689 break;
2690 }
2691 case KVM_GET_CPUID2: {
2692 struct kvm_cpuid2 __user *cpuid_arg = argp;
2693 struct kvm_cpuid2 cpuid;
2694
2695 r = -EFAULT;
2696 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2697 goto out;
2698 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 2699 cpuid_arg->entries);
07716717
DK		 2700 if (r)
2701 goto out;
2702 r = -EFAULT;
2703 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2704 goto out;
2705 r = 0;
2706 break;
2707 }
313a3dc7
CO		 2708 case KVM_GET_MSRS:
2709 r = msr_io(vcpu, argp, kvm_get_msr, 1);
2710 break;
2711 case KVM_SET_MSRS:
2712 r = msr_io(vcpu, argp, do_set_msr, 0);
2713 break;
b209749f
AK		 2714 case KVM_TPR_ACCESS_REPORTING: {
2715 struct kvm_tpr_access_ctl tac;
2716
2717 r = -EFAULT;
2718 if (copy_from_user(&tac, argp, sizeof tac))
2719 goto out;
2720 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
2721 if (r)
2722 goto out;
2723 r = -EFAULT;
2724 if (copy_to_user(argp, &tac, sizeof tac))
2725 goto out;
2726 r = 0;
2727 break;
2728 };
b93463aa
AK		 2729 case KVM_SET_VAPIC_ADDR: {
2730 struct kvm_vapic_addr va;
2731
2732 r = -EINVAL;
2733 if (!irqchip_in_kernel(vcpu->kvm))
2734 goto out;
2735 r = -EFAULT;
2736 if (copy_from_user(&va, argp, sizeof va))
2737 goto out;
2738 r = 0;
2739 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
2740 break;
2741 }
890ca9ae
HY		 2742 case KVM_X86_SETUP_MCE: {
2743 u64 mcg_cap;
2744
2745 r = -EFAULT;
2746 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
2747 goto out;
2748 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
2749 break;
2750 }
2751 case KVM_X86_SET_MCE: {
2752 struct kvm_x86_mce mce;
2753
2754 r = -EFAULT;
2755 if (copy_from_user(&mce, argp, sizeof mce))
2756 goto out;
2757 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
2758 break;
2759 }
3cfc3092
JK		 2760 case KVM_GET_VCPU_EVENTS: {
2761 struct kvm_vcpu_events events;
2762
2763 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
2764
2765 r = -EFAULT;
2766 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
2767 break;
2768 r = 0;
2769 break;
2770 }
2771 case KVM_SET_VCPU_EVENTS: {
2772 struct kvm_vcpu_events events;
2773
2774 r = -EFAULT;
2775 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
2776 break;
2777
2778 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
2779 break;
2780 }
a1efbe77
JK		 2781 case KVM_GET_DEBUGREGS: {
2782 struct kvm_debugregs dbgregs;
2783
2784 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
2785
2786 r = -EFAULT;
2787 if (copy_to_user(argp, &dbgregs,
2788 sizeof(struct kvm_debugregs)))
2789 break;
2790 r = 0;
2791 break;
2792 }
2793 case KVM_SET_DEBUGREGS: {
2794 struct kvm_debugregs dbgregs;
2795
2796 r = -EFAULT;
2797 if (copy_from_user(&dbgregs, argp,
2798 sizeof(struct kvm_debugregs)))
2799 break;
2800
2801 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
2802 break;
2803 }
2d5b5a66 2804 case KVM_GET_XSAVE: {
d1ac91d8 2805 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 2806 r = -ENOMEM;
d1ac91d8 2807 if (!u.xsave)
2d5b5a66
SY		 2808 break;
2809
d1ac91d8 2810 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 2811
2812 r = -EFAULT;
d1ac91d8 2813 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 2814 break;
2815 r = 0;
2816 break;
2817 }
2818 case KVM_SET_XSAVE: {
ff5c2c03
SL		 2819 u.xsave = memdup_user(argp, sizeof(*u.xsave));
2820 if (IS_ERR(u.xsave)) {
2821 r = PTR_ERR(u.xsave);
2822 goto out;
2823 }
2d5b5a66 2824
d1ac91d8 2825 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 2826 break;
2827 }
2828 case KVM_GET_XCRS: {
d1ac91d8 2829 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 2830 r = -ENOMEM;
d1ac91d8 2831 if (!u.xcrs)
2d5b5a66
SY		 2832 break;
2833
d1ac91d8 2834 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 2835
2836 r = -EFAULT;
d1ac91d8 2837 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 2838 sizeof(struct kvm_xcrs)))
2839 break;
2840 r = 0;
2841 break;
2842 }
2843 case KVM_SET_XCRS: {
ff5c2c03
SL		 2844 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
2845 if (IS_ERR(u.xcrs)) {
2846 r = PTR_ERR(u.xcrs);
2847 goto out;
2848 }
2d5b5a66 2849
d1ac91d8 2850 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 2851 break;
2852 }
92a1f12d
JR		 2853 case KVM_SET_TSC_KHZ: {
2854 u32 user_tsc_khz;
2855
2856 r = -EINVAL;
92a1f12d
JR		 2857 user_tsc_khz = (u32)arg;
2858
2859 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
2860 goto out;
2861
cc578287
ZA		 2862 if (user_tsc_khz == 0)
2863 user_tsc_khz = tsc_khz;
2864
2865 kvm_set_tsc_khz(vcpu, user_tsc_khz);
92a1f12d
JR		 2866
2867 r = 0;
2868 goto out;
2869 }
2870 case KVM_GET_TSC_KHZ: {
cc578287 2871 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 2872 goto out;
2873 }
313a3dc7
CO		 2874 default:
2875 r = -EINVAL;
2876 }
2877out:
d1ac91d8 2878 kfree(u.buffer);
313a3dc7
CO		 2879 return r;
2880}
2881
5b1c1493
CO		 2882int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
2883{
2884 return VM_FAULT_SIGBUS;
2885}
2886
1fe779f8
CO		 2887static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
2888{
2889 int ret;
2890
2891 if (addr > (unsigned int)(-3 * PAGE_SIZE))
2892 return -1;
2893 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
2894 return ret;
2895}
2896
b927a3ce
SY		 2897static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
2898 u64 ident_addr)
2899{
2900 kvm->arch.ept_identity_map_addr = ident_addr;
2901 return 0;
2902}
2903
1fe779f8
CO		 2904static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
2905 u32 kvm_nr_mmu_pages)
2906{
2907 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
2908 return -EINVAL;
2909
79fac95e 2910 mutex_lock(&kvm->slots_lock);
7c8a83b7 2911 spin_lock(&kvm->mmu_lock);
1fe779f8
CO		 2912
2913 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 2914 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 2915
7c8a83b7 2916 spin_unlock(&kvm->mmu_lock);
79fac95e 2917 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 2918 return 0;
2919}
2920
2921static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
2922{
39de71ec 2923 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 2924}
2925
1fe779f8
CO		 2926static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2927{
2928 int r;
2929
2930 r = 0;
2931 switch (chip->chip_id) {
2932 case KVM_IRQCHIP_PIC_MASTER:
2933 memcpy(&chip->chip.pic,
2934 &pic_irqchip(kvm)->pics[0],
2935 sizeof(struct kvm_pic_state));
2936 break;
2937 case KVM_IRQCHIP_PIC_SLAVE:
2938 memcpy(&chip->chip.pic,
2939 &pic_irqchip(kvm)->pics[1],
2940 sizeof(struct kvm_pic_state));
2941 break;
2942 case KVM_IRQCHIP_IOAPIC:
eba0226b 2943 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 2944 break;
2945 default:
2946 r = -EINVAL;
2947 break;
2948 }
2949 return r;
2950}
2951
2952static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2953{
2954 int r;
2955
2956 r = 0;
2957 switch (chip->chip_id) {
2958 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 2959 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2960 memcpy(&pic_irqchip(kvm)->pics[0],
2961 &chip->chip.pic,
2962 sizeof(struct kvm_pic_state));
f4f51050 2963 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2964 break;
2965 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 2966 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2967 memcpy(&pic_irqchip(kvm)->pics[1],
2968 &chip->chip.pic,
2969 sizeof(struct kvm_pic_state));
f4f51050 2970 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2971 break;
2972 case KVM_IRQCHIP_IOAPIC:
eba0226b 2973 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 2974 break;
2975 default:
2976 r = -EINVAL;
2977 break;
2978 }
2979 kvm_pic_update_irq(pic_irqchip(kvm));
2980 return r;
2981}
2982
e0f63cb9
SY		 2983static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2984{
2985 int r = 0;
2986
894a9c55 2987 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 2988 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 2989 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 2990 return r;
2991}
2992
2993static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2994{
2995 int r = 0;
2996
894a9c55 2997 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 2998 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 2999 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3000 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3001 return r;
3002}
3003
3004static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3005{
3006 int r = 0;
3007
3008 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3009 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3010 sizeof(ps->channels));
3011 ps->flags = kvm->arch.vpit->pit_state.flags;
3012 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3013 memset(&ps->reserved, 0, sizeof(ps->reserved));
e9f42757
BK		 3014 return r;
3015}
3016
3017static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3018{
3019 int r = 0, start = 0;
3020 u32 prev_legacy, cur_legacy;
3021 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3022 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3023 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3024 if (!prev_legacy && cur_legacy)
3025 start = 1;
3026 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3027 sizeof(kvm->arch.vpit->pit_state.channels));
3028 kvm->arch.vpit->pit_state.flags = ps->flags;
3029 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 3030 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3031 return r;
3032}
3033
52d939a0
MT		 3034static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3035 struct kvm_reinject_control *control)
3036{
3037 if (!kvm->arch.vpit)
3038 return -ENXIO;
894a9c55 3039 mutex_lock(&kvm->arch.vpit->pit_state.lock);
52d939a0 3040 kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject;
894a9c55 3041 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3042 return 0;
3043}
3044
95d4c16c
TY		 3045/**
3046 * write_protect_slot - write protect a slot for dirty logging
3047 * @kvm: the kvm instance
3048 * @memslot: the slot we protect
3049 * @dirty_bitmap: the bitmap indicating which pages are dirty
3050 * @nr_dirty_pages: the number of dirty pages
3051 *
3052 * We have two ways to find all sptes to protect:
3053 * 1. Use kvm_mmu_slot_remove_write_access() which walks all shadow pages and
3054 * checks ones that have a spte mapping a page in the slot.
3055 * 2. Use kvm_mmu_rmap_write_protect() for each gfn found in the bitmap.
3056 *
3057 * Generally speaking, if there are not so many dirty pages compared to the
3058 * number of shadow pages, we should use the latter.
3059 *
3060 * Note that letting others write into a page marked dirty in the old bitmap
3061 * by using the remaining tlb entry is not a problem. That page will become
3062 * write protected again when we flush the tlb and then be reported dirty to
3063 * the user space by copying the old bitmap.
3064 */
3065static void write_protect_slot(struct kvm *kvm,
3066 struct kvm_memory_slot *memslot,
3067 unsigned long *dirty_bitmap,
3068 unsigned long nr_dirty_pages)
3069{
6dbf79e7
TY		 3070 spin_lock(&kvm->mmu_lock);
3071
95d4c16c
TY		 3072 /* Not many dirty pages compared to # of shadow pages. */
3073 if (nr_dirty_pages < kvm->arch.n_used_mmu_pages) {
3074 unsigned long gfn_offset;
3075
3076 for_each_set_bit(gfn_offset, dirty_bitmap, memslot->npages) {
3077 unsigned long gfn = memslot->base_gfn + gfn_offset;
3078
95d4c16c 3079 kvm_mmu_rmap_write_protect(kvm, gfn, memslot);
95d4c16c
TY		 3080 }
3081 kvm_flush_remote_tlbs(kvm);
6dbf79e7 3082 } else
95d4c16c 3083 kvm_mmu_slot_remove_write_access(kvm, memslot->id);
6dbf79e7
TY		 3084
3085 spin_unlock(&kvm->mmu_lock);
95d4c16c
TY		 3086}
3087
5bb064dc
ZX		 3088/*
3089 * Get (and clear) the dirty memory log for a memory slot.
3090 */
3091int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
3092 struct kvm_dirty_log *log)
3093{
7850ac54 3094 int r;
5bb064dc 3095 struct kvm_memory_slot *memslot;
95d4c16c 3096 unsigned long n, nr_dirty_pages;
5bb064dc 3097
79fac95e 3098 mutex_lock(&kvm->slots_lock);
5bb064dc 3099
b050b015
MT		 3100 r = -EINVAL;
3101 if (log->slot >= KVM_MEMORY_SLOTS)
3102 goto out;
3103
28a37544 3104 memslot = id_to_memslot(kvm->memslots, log->slot);
b050b015
MT		 3105 r = -ENOENT;
3106 if (!memslot->dirty_bitmap)
3107 goto out;
3108
87bf6e7d 3109 n = kvm_dirty_bitmap_bytes(memslot);
95d4c16c 3110 nr_dirty_pages = memslot->nr_dirty_pages;
b050b015 3111
5bb064dc 3112 /* If nothing is dirty, don't bother messing with page tables. */
95d4c16c 3113 if (nr_dirty_pages) {
b050b015 3114 struct kvm_memslots *slots, *old_slots;
28a37544 3115 unsigned long *dirty_bitmap, *dirty_bitmap_head;
b050b015 3116
28a37544
XG		 3117 dirty_bitmap = memslot->dirty_bitmap;
3118 dirty_bitmap_head = memslot->dirty_bitmap_head;
3119 if (dirty_bitmap == dirty_bitmap_head)
3120 dirty_bitmap_head += n / sizeof(long);
3121 memset(dirty_bitmap_head, 0, n);
b050b015 3122
914ebccd 3123 r = -ENOMEM;
cdfca7b3 3124 slots = kmemdup(kvm->memslots, sizeof(*kvm->memslots), GFP_KERNEL);
515a0127 3125 if (!slots)
914ebccd 3126 goto out;
cdfca7b3 3127
28a37544 3128 memslot = id_to_memslot(slots, log->slot);
95d4c16c 3129 memslot->nr_dirty_pages = 0;
28a37544 3130 memslot->dirty_bitmap = dirty_bitmap_head;
be593d62 3131 update_memslots(slots, NULL);
b050b015
MT		 3132
3133 old_slots = kvm->memslots;
3134 rcu_assign_pointer(kvm->memslots, slots);
3135 synchronize_srcu_expedited(&kvm->srcu);
b050b015 3136 kfree(old_slots);
914ebccd 3137
95d4c16c 3138 write_protect_slot(kvm, memslot, dirty_bitmap, nr_dirty_pages);
edde99ce 3139
914ebccd 3140 r = -EFAULT;
515a0127 3141 if (copy_to_user(log->dirty_bitmap, dirty_bitmap, n))
914ebccd 3142 goto out;
914ebccd
TY		 3143 } else {
3144 r = -EFAULT;
3145 if (clear_user(log->dirty_bitmap, n))
3146 goto out;
5bb064dc 3147 }
b050b015 3148
5bb064dc
ZX		 3149 r = 0;
3150out:
79fac95e 3151 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3152 return r;
3153}
3154
1fe779f8
CO		 3155long kvm_arch_vm_ioctl(struct file *filp,
3156 unsigned int ioctl, unsigned long arg)
3157{
3158 struct kvm *kvm = filp->private_data;
3159 void __user *argp = (void __user *)arg;
367e1319 3160 int r = -ENOTTY;
f0d66275
DH		 3161 /*
3162 * This union makes it completely explicit to gcc-3.x
3163 * that these two variables' stack usage should be
3164 * combined, not added together.
3165 */
3166 union {
3167 struct kvm_pit_state ps;
e9f42757 3168 struct kvm_pit_state2 ps2;
c5ff41ce 3169 struct kvm_pit_config pit_config;
f0d66275 3170 } u;
1fe779f8
CO		 3171
3172 switch (ioctl) {
3173 case KVM_SET_TSS_ADDR:
3174 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
3175 if (r < 0)
3176 goto out;
3177 break;
b927a3ce
SY		 3178 case KVM_SET_IDENTITY_MAP_ADDR: {
3179 u64 ident_addr;
3180
3181 r = -EFAULT;
3182 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3183 goto out;
3184 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
3185 if (r < 0)
3186 goto out;
3187 break;
3188 }
1fe779f8
CO		 3189 case KVM_SET_NR_MMU_PAGES:
3190 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
3191 if (r)
3192 goto out;
3193 break;
3194 case KVM_GET_NR_MMU_PAGES:
3195 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3196 break;
3ddea128
MT		 3197 case KVM_CREATE_IRQCHIP: {
3198 struct kvm_pic *vpic;
3199
3200 mutex_lock(&kvm->lock);
3201 r = -EEXIST;
3202 if (kvm->arch.vpic)
3203 goto create_irqchip_unlock;
3e515705
AK		 3204 r = -EINVAL;
3205 if (atomic_read(&kvm->online_vcpus))
3206 goto create_irqchip_unlock;
1fe779f8 3207 r = -ENOMEM;
3ddea128
MT		 3208 vpic = kvm_create_pic(kvm);
3209 if (vpic) {
1fe779f8
CO		 3210 r = kvm_ioapic_init(kvm);
3211 if (r) {
175504cd 3212 mutex_lock(&kvm->slots_lock);
72bb2fcd 3213 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
743eeb0b
SL		 3214 &vpic->dev_master);
3215 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3216 &vpic->dev_slave);
3217 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3218 &vpic->dev_eclr);
175504cd 3219 mutex_unlock(&kvm->slots_lock);
3ddea128
MT		 3220 kfree(vpic);
3221 goto create_irqchip_unlock;
1fe779f8
CO		 3222 }
3223 } else
3ddea128
MT		 3224 goto create_irqchip_unlock;
3225 smp_wmb();
3226 kvm->arch.vpic = vpic;
3227 smp_wmb();
399ec807
AK		 3228 r = kvm_setup_default_irq_routing(kvm);
3229 if (r) {
175504cd 3230 mutex_lock(&kvm->slots_lock);
3ddea128 3231 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 3232 kvm_ioapic_destroy(kvm);
3233 kvm_destroy_pic(kvm);
3ddea128 3234 mutex_unlock(&kvm->irq_lock);
175504cd 3235 mutex_unlock(&kvm->slots_lock);
399ec807 3236 }
3ddea128
MT		 3237 create_irqchip_unlock:
3238 mutex_unlock(&kvm->lock);
1fe779f8 3239 break;
3ddea128 3240 }
7837699f 3241 case KVM_CREATE_PIT:
c5ff41ce
JK		 3242 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3243 goto create_pit;
3244 case KVM_CREATE_PIT2:
3245 r = -EFAULT;
3246 if (copy_from_user(&u.pit_config, argp,
3247 sizeof(struct kvm_pit_config)))
3248 goto out;
3249 create_pit:
79fac95e 3250 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3251 r = -EEXIST;
3252 if (kvm->arch.vpit)
3253 goto create_pit_unlock;
7837699f 3254 r = -ENOMEM;
c5ff41ce 3255 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3256 if (kvm->arch.vpit)
3257 r = 0;
269e05e4 3258 create_pit_unlock:
79fac95e 3259 mutex_unlock(&kvm->slots_lock);
7837699f 3260 break;
4925663a 3261 case KVM_IRQ_LINE_STATUS:
1fe779f8
CO		 3262 case KVM_IRQ_LINE: {
3263 struct kvm_irq_level irq_event;
3264
3265 r = -EFAULT;
3266 if (copy_from_user(&irq_event, argp, sizeof irq_event))
3267 goto out;
160d2f6c 3268 r = -ENXIO;
1fe779f8 3269 if (irqchip_in_kernel(kvm)) {
4925663a 3270 __s32 status;
4925663a
GN		 3271 status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3272 irq_event.irq, irq_event.level);
4925663a 3273 if (ioctl == KVM_IRQ_LINE_STATUS) {
160d2f6c 3274 r = -EFAULT;
4925663a
GN		 3275 irq_event.status = status;
3276 if (copy_to_user(argp, &irq_event,
3277 sizeof irq_event))
3278 goto out;
3279 }
1fe779f8
CO		 3280 r = 0;
3281 }
3282 break;
3283 }
3284 case KVM_GET_IRQCHIP: {
3285 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3286 struct kvm_irqchip *chip;
1fe779f8 3287
ff5c2c03
SL		 3288 chip = memdup_user(argp, sizeof(*chip));
3289 if (IS_ERR(chip)) {
3290 r = PTR_ERR(chip);
1fe779f8 3291 goto out;
ff5c2c03
SL		 3292 }
3293
1fe779f8
CO		 3294 r = -ENXIO;
3295 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3296 goto get_irqchip_out;
3297 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3298 if (r)
f0d66275 3299 goto get_irqchip_out;
1fe779f8 3300 r = -EFAULT;
f0d66275
DH		 3301 if (copy_to_user(argp, chip, sizeof *chip))
3302 goto get_irqchip_out;
1fe779f8 3303 r = 0;
f0d66275
DH		 3304 get_irqchip_out:
3305 kfree(chip);
3306 if (r)
3307 goto out;
1fe779f8
CO		 3308 break;
3309 }
3310 case KVM_SET_IRQCHIP: {
3311 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3312 struct kvm_irqchip *chip;
1fe779f8 3313
ff5c2c03
SL		 3314 chip = memdup_user(argp, sizeof(*chip));
3315 if (IS_ERR(chip)) {
3316 r = PTR_ERR(chip);
1fe779f8 3317 goto out;
ff5c2c03
SL		 3318 }
3319
1fe779f8
CO		 3320 r = -ENXIO;
3321 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3322 goto set_irqchip_out;
3323 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3324 if (r)
f0d66275 3325 goto set_irqchip_out;
1fe779f8 3326 r = 0;
f0d66275
DH		 3327 set_irqchip_out:
3328 kfree(chip);
3329 if (r)
3330 goto out;
1fe779f8
CO		 3331 break;
3332 }
e0f63cb9 3333 case KVM_GET_PIT: {
e0f63cb9 3334 r = -EFAULT;
f0d66275 3335 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3336 goto out;
3337 r = -ENXIO;
3338 if (!kvm->arch.vpit)
3339 goto out;
f0d66275 3340 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3341 if (r)
3342 goto out;
3343 r = -EFAULT;
f0d66275 3344 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3345 goto out;
3346 r = 0;
3347 break;
3348 }
3349 case KVM_SET_PIT: {
e0f63cb9 3350 r = -EFAULT;
f0d66275 3351 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3352 goto out;
3353 r = -ENXIO;
3354 if (!kvm->arch.vpit)
3355 goto out;
f0d66275 3356 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3357 if (r)
3358 goto out;
3359 r = 0;
3360 break;
3361 }
e9f42757
BK		 3362 case KVM_GET_PIT2: {
3363 r = -ENXIO;
3364 if (!kvm->arch.vpit)
3365 goto out;
3366 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3367 if (r)
3368 goto out;
3369 r = -EFAULT;
3370 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3371 goto out;
3372 r = 0;
3373 break;
3374 }
3375 case KVM_SET_PIT2: {
3376 r = -EFAULT;
3377 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3378 goto out;
3379 r = -ENXIO;
3380 if (!kvm->arch.vpit)
3381 goto out;
3382 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
3383 if (r)
3384 goto out;
3385 r = 0;
3386 break;
3387 }
52d939a0
MT		 3388 case KVM_REINJECT_CONTROL: {
3389 struct kvm_reinject_control control;
3390 r = -EFAULT;
3391 if (copy_from_user(&control, argp, sizeof(control)))
3392 goto out;
3393 r = kvm_vm_ioctl_reinject(kvm, &control);
3394 if (r)
3395 goto out;
3396 r = 0;
3397 break;
3398 }
ffde22ac
ES		 3399 case KVM_XEN_HVM_CONFIG: {
3400 r = -EFAULT;
3401 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3402 sizeof(struct kvm_xen_hvm_config)))
3403 goto out;
3404 r = -EINVAL;
3405 if (kvm->arch.xen_hvm_config.flags)
3406 goto out;
3407 r = 0;
3408 break;
3409 }
afbcf7ab 3410 case KVM_SET_CLOCK: {
afbcf7ab
GC		 3411 struct kvm_clock_data user_ns;
3412 u64 now_ns;
3413 s64 delta;
3414
3415 r = -EFAULT;
3416 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3417 goto out;
3418
3419 r = -EINVAL;
3420 if (user_ns.flags)
3421 goto out;
3422
3423 r = 0;
395c6b0a 3424 local_irq_disable();
759379dd 3425 now_ns = get_kernel_ns();
afbcf7ab 3426 delta = user_ns.clock - now_ns;
395c6b0a 3427 local_irq_enable();
afbcf7ab
GC		 3428 kvm->arch.kvmclock_offset = delta;
3429 break;
3430 }
3431 case KVM_GET_CLOCK: {
afbcf7ab
GC		 3432 struct kvm_clock_data user_ns;
3433 u64 now_ns;
3434
395c6b0a 3435 local_irq_disable();
759379dd 3436 now_ns = get_kernel_ns();
afbcf7ab 3437 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 3438 local_irq_enable();
afbcf7ab 3439 user_ns.flags = 0;
97e69aa6 3440 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 3441
3442 r = -EFAULT;
3443 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3444 goto out;
3445 r = 0;
3446 break;
3447 }
3448
1fe779f8
CO		 3449 default:
3450 ;
3451 }
3452out:
3453 return r;
3454}
3455
a16b043c 3456static void kvm_init_msr_list(void)
043405e1
CO		 3457{
3458 u32 dummy[2];
3459 unsigned i, j;
3460
e3267cbb
GC		 3461 /* skip the first msrs in the list. KVM-specific */
3462 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3463 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3464 continue;
3465 if (j < i)
3466 msrs_to_save[j] = msrs_to_save[i];
3467 j++;
3468 }
3469 num_msrs_to_save = j;
3470}
3471
bda9020e
MT		 3472static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3473 const void *v)
bbd9b64e 3474{
70252a10
AK		 3475 int handled = 0;
3476 int n;
3477
3478 do {
3479 n = min(len, 8);
3480 if (!(vcpu->arch.apic &&
3481 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v))
3482 && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3483 break;
3484 handled += n;
3485 addr += n;
3486 len -= n;
3487 v += n;
3488 } while (len);
bbd9b64e 3489
70252a10 3490 return handled;
bbd9b64e
CO		 3491}
3492
bda9020e 3493static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 3494{
70252a10
AK		 3495 int handled = 0;
3496 int n;
3497
3498 do {
3499 n = min(len, 8);
3500 if (!(vcpu->arch.apic &&
3501 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v))
3502 && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3503 break;
3504 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
3505 handled += n;
3506 addr += n;
3507 len -= n;
3508 v += n;
3509 } while (len);
bbd9b64e 3510
70252a10 3511 return handled;
bbd9b64e
CO		 3512}
3513
2dafc6c2
GN		 3514static void kvm_set_segment(struct kvm_vcpu *vcpu,
3515 struct kvm_segment *var, int seg)
3516{
3517 kvm_x86_ops->set_segment(vcpu, var, seg);
3518}
3519
3520void kvm_get_segment(struct kvm_vcpu *vcpu,
3521 struct kvm_segment *var, int seg)
3522{
3523 kvm_x86_ops->get_segment(vcpu, var, seg);
3524}
3525
e459e322 3526gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
02f59dc9
JR		 3527{
3528 gpa_t t_gpa;
ab9ae313 3529 struct x86_exception exception;
02f59dc9
JR		 3530
3531 BUG_ON(!mmu_is_nested(vcpu));
3532
3533 /* NPT walks are always user-walks */
3534 access |= PFERR_USER_MASK;
ab9ae313 3535 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &exception);
02f59dc9
JR		 3536
3537 return t_gpa;
3538}
3539
ab9ae313
AK		 3540gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
3541 struct x86_exception *exception)
1871c602
GN		 3542{
3543 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 3544 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3545}
3546
ab9ae313
AK		 3547 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
3548 struct x86_exception *exception)
1871c602
GN		 3549{
3550 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3551 access |= PFERR_FETCH_MASK;
ab9ae313 3552 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3553}
3554
ab9ae313
AK		 3555gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
3556 struct x86_exception *exception)
1871c602
GN		 3557{
3558 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3559 access |= PFERR_WRITE_MASK;
ab9ae313 3560 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3561}
3562
3563/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 3564gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
3565 struct x86_exception *exception)
1871c602 3566{
ab9ae313 3567 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 3568}
3569
3570static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3571 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 3572 struct x86_exception *exception)
bbd9b64e
CO		 3573{
3574 void *data = val;
10589a46 3575 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 3576
3577 while (bytes) {
14dfe855 3578 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 3579 exception);
bbd9b64e 3580 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 3581 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 3582 int ret;
3583
bcc55cba 3584 if (gpa == UNMAPPED_GVA)
ab9ae313 3585 return X86EMUL_PROPAGATE_FAULT;
77c2002e 3586 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46 3587 if (ret < 0) {
c3cd7ffa 3588 r = X86EMUL_IO_NEEDED;
10589a46
MT		 3589 goto out;
3590 }
bbd9b64e 3591
77c2002e
IE		 3592 bytes -= toread;
3593 data += toread;
3594 addr += toread;
bbd9b64e 3595 }
10589a46 3596out:
10589a46 3597 return r;
bbd9b64e 3598}
77c2002e 3599
1871c602 3600/* used for instruction fetching */
0f65dd70
AK		 3601static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
3602 gva_t addr, void *val, unsigned int bytes,
bcc55cba 3603 struct x86_exception *exception)
1871c602 3604{
0f65dd70 3605 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 3606 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 3607
1871c602 3608 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
bcc55cba
AK		 3609 access | PFERR_FETCH_MASK,
3610 exception);
1871c602
GN		 3611}
3612
064aea77 3613int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 3614 gva_t addr, void *val, unsigned int bytes,
bcc55cba 3615 struct x86_exception *exception)
1871c602 3616{
0f65dd70 3617 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 3618 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 3619
1871c602 3620 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 3621 exception);
1871c602 3622}
064aea77 3623EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 3624
0f65dd70
AK		 3625static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
3626 gva_t addr, void *val, unsigned int bytes,
bcc55cba 3627 struct x86_exception *exception)
1871c602 3628{
0f65dd70 3629 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 3630 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 3631}
3632
6a4d7550 3633int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 3634 gva_t addr, void *val,
2dafc6c2 3635 unsigned int bytes,
bcc55cba 3636 struct x86_exception *exception)
77c2002e 3637{
0f65dd70 3638 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 3639 void *data = val;
3640 int r = X86EMUL_CONTINUE;
3641
3642 while (bytes) {
14dfe855
JR		 3643 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
3644 PFERR_WRITE_MASK,
ab9ae313 3645 exception);
77c2002e
IE		 3646 unsigned offset = addr & (PAGE_SIZE-1);
3647 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
3648 int ret;
3649
bcc55cba 3650 if (gpa == UNMAPPED_GVA)
ab9ae313 3651 return X86EMUL_PROPAGATE_FAULT;
77c2002e
IE		 3652 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
3653 if (ret < 0) {
c3cd7ffa 3654 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 3655 goto out;
3656 }
3657
3658 bytes -= towrite;
3659 data += towrite;
3660 addr += towrite;
3661 }
3662out:
3663 return r;
3664}
6a4d7550 3665EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 3666
af7cc7d1
XG		 3667static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
3668 gpa_t *gpa, struct x86_exception *exception,
3669 bool write)
3670{
3671 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3672
bebb106a
XG		 3673 if (vcpu_match_mmio_gva(vcpu, gva) &&
3674 check_write_user_access(vcpu, write, access,
3675 vcpu->arch.access)) {
3676 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
3677 (gva & (PAGE_SIZE - 1));
4f022648 3678 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 3679 return 1;
3680 }
3681
af7cc7d1
XG		 3682 if (write)
3683 access |= PFERR_WRITE_MASK;
3684
3685 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3686
3687 if (*gpa == UNMAPPED_GVA)
3688 return -1;
3689
3690 /* For APIC access vmexit */
3691 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3692 return 1;
3693
4f022648
XG		 3694 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
3695 trace_vcpu_match_mmio(gva, *gpa, write, true);
bebb106a 3696 return 1;
4f022648 3697 }
bebb106a 3698
af7cc7d1
XG		 3699 return 0;
3700}
3701
3200f405 3702int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 3703 const void *val, int bytes)
bbd9b64e
CO		 3704{
3705 int ret;
3706
3707 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 3708 if (ret < 0)
bbd9b64e 3709 return 0;
f57f2ef5 3710 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 3711 return 1;
3712}
3713
77d197b2
XG		 3714struct read_write_emulator_ops {
3715 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
3716 int bytes);
3717 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
3718 void *val, int bytes);
3719 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
3720 int bytes, void *val);
3721 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
3722 void *val, int bytes);
3723 bool write;
3724};
3725
3726static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
3727{
3728 if (vcpu->mmio_read_completed) {
3729 memcpy(val, vcpu->mmio_data, bytes);
3730 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
3731 vcpu->mmio_phys_addr, *(u64 *)val);
3732 vcpu->mmio_read_completed = 0;
3733 return 1;
3734 }
3735
3736 return 0;
3737}
3738
3739static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
3740 void *val, int bytes)
3741{
3742 return !kvm_read_guest(vcpu->kvm, gpa, val, bytes);
3743}
3744
3745static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
3746 void *val, int bytes)
3747{
3748 return emulator_write_phys(vcpu, gpa, val, bytes);
3749}
3750
3751static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
3752{
3753 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
3754 return vcpu_mmio_write(vcpu, gpa, bytes, val);
3755}
3756
3757static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
3758 void *val, int bytes)
3759{
3760 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
3761 return X86EMUL_IO_NEEDED;
3762}
3763
3764static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
3765 void *val, int bytes)
3766{
3767 memcpy(vcpu->mmio_data, val, bytes);
3768 memcpy(vcpu->run->mmio.data, vcpu->mmio_data, 8);
3769 return X86EMUL_CONTINUE;
3770}
3771
3772static struct read_write_emulator_ops read_emultor = {
3773 .read_write_prepare = read_prepare,
3774 .read_write_emulate = read_emulate,
3775 .read_write_mmio = vcpu_mmio_read,
3776 .read_write_exit_mmio = read_exit_mmio,
3777};
3778
3779static struct read_write_emulator_ops write_emultor = {
3780 .read_write_emulate = write_emulate,
3781 .read_write_mmio = write_mmio,
3782 .read_write_exit_mmio = write_exit_mmio,
3783 .write = true,
3784};
3785
22388a3c
XG		 3786static int emulator_read_write_onepage(unsigned long addr, void *val,
3787 unsigned int bytes,
3788 struct x86_exception *exception,
3789 struct kvm_vcpu *vcpu,
3790 struct read_write_emulator_ops *ops)
bbd9b64e 3791{
af7cc7d1
XG		 3792 gpa_t gpa;
3793 int handled, ret;
22388a3c
XG		 3794 bool write = ops->write;
3795
3796 if (ops->read_write_prepare &&
3797 ops->read_write_prepare(vcpu, val, bytes))
3798 return X86EMUL_CONTINUE;
10589a46 3799
22388a3c 3800 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 3801
af7cc7d1 3802 if (ret < 0)
bbd9b64e 3803 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 3804
3805 /* For APIC access vmexit */
af7cc7d1 3806 if (ret)
bbd9b64e
CO		 3807 goto mmio;
3808
22388a3c 3809 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 3810 return X86EMUL_CONTINUE;
3811
3812mmio:
3813 /*
3814 * Is this MMIO handled locally?
3815 */
22388a3c 3816 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 3817 if (handled == bytes)
bbd9b64e 3818 return X86EMUL_CONTINUE;
bbd9b64e 3819
70252a10
AK		 3820 gpa += handled;
3821 bytes -= handled;
3822 val += handled;
3823
bbd9b64e 3824 vcpu->mmio_needed = 1;
411c35b7
GN		 3825 vcpu->run->exit_reason = KVM_EXIT_MMIO;
3826 vcpu->run->mmio.phys_addr = vcpu->mmio_phys_addr = gpa;
cef4dea0
AK		 3827 vcpu->mmio_size = bytes;
3828 vcpu->run->mmio.len = min(vcpu->mmio_size, 8);
22388a3c 3829 vcpu->run->mmio.is_write = vcpu->mmio_is_write = write;
cef4dea0 3830 vcpu->mmio_index = 0;
bbd9b64e 3831
22388a3c 3832 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
bbd9b64e
CO		 3833}
3834
22388a3c
XG		 3835int emulator_read_write(struct x86_emulate_ctxt *ctxt, unsigned long addr,
3836 void *val, unsigned int bytes,
3837 struct x86_exception *exception,
3838 struct read_write_emulator_ops *ops)
bbd9b64e 3839{
0f65dd70
AK		 3840 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3841
bbd9b64e
CO		 3842 /* Crossing a page boundary? */
3843 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
3844 int rc, now;
3845
3846 now = -addr & ~PAGE_MASK;
22388a3c
XG		 3847 rc = emulator_read_write_onepage(addr, val, now, exception,
3848 vcpu, ops);
3849
bbd9b64e
CO		 3850 if (rc != X86EMUL_CONTINUE)
3851 return rc;
3852 addr += now;
3853 val += now;
3854 bytes -= now;
3855 }
22388a3c
XG		 3856
3857 return emulator_read_write_onepage(addr, val, bytes, exception,
3858 vcpu, ops);
3859}
3860
3861static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
3862 unsigned long addr,
3863 void *val,
3864 unsigned int bytes,
3865 struct x86_exception *exception)
3866{
3867 return emulator_read_write(ctxt, addr, val, bytes,
3868 exception, &read_emultor);
3869}
3870
3871int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
3872 unsigned long addr,
3873 const void *val,
3874 unsigned int bytes,
3875 struct x86_exception *exception)
3876{
3877 return emulator_read_write(ctxt, addr, (void *)val, bytes,
3878 exception, &write_emultor);
bbd9b64e 3879}
bbd9b64e 3880
daea3e73
AK		 3881#define CMPXCHG_TYPE(t, ptr, old, new) \
3882 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
3883
3884#ifdef CONFIG_X86_64
3885# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
3886#else
3887# define CMPXCHG64(ptr, old, new) \
9749a6c0 3888 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 3889#endif
3890
0f65dd70
AK		 3891static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
3892 unsigned long addr,
bbd9b64e
CO		 3893 const void *old,
3894 const void *new,
3895 unsigned int bytes,
0f65dd70 3896 struct x86_exception *exception)
bbd9b64e 3897{
0f65dd70 3898 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 3899 gpa_t gpa;
3900 struct page *page;
3901 char *kaddr;
3902 bool exchanged;
2bacc55c 3903
daea3e73
AK		 3904 /* guests cmpxchg8b have to be emulated atomically */
3905 if (bytes > 8 || (bytes & (bytes - 1)))
3906 goto emul_write;
10589a46 3907
daea3e73 3908 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 3909
daea3e73
AK		 3910 if (gpa == UNMAPPED_GVA ||
3911 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3912 goto emul_write;
2bacc55c 3913
daea3e73
AK		 3914 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
3915 goto emul_write;
72dc67a6 3916
daea3e73 3917 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
c19b8bd6
WY		 3918 if (is_error_page(page)) {
3919 kvm_release_page_clean(page);
3920 goto emul_write;
3921 }
72dc67a6 3922
daea3e73
AK		 3923 kaddr = kmap_atomic(page, KM_USER0);
3924 kaddr += offset_in_page(gpa);
3925 switch (bytes) {
3926 case 1:
3927 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
3928 break;
3929 case 2:
3930 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
3931 break;
3932 case 4:
3933 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
3934 break;
3935 case 8:
3936 exchanged = CMPXCHG64(kaddr, old, new);
3937 break;
3938 default:
3939 BUG();
2bacc55c 3940 }
daea3e73
AK		 3941 kunmap_atomic(kaddr, KM_USER0);
3942 kvm_release_page_dirty(page);
3943
3944 if (!exchanged)
3945 return X86EMUL_CMPXCHG_FAILED;
3946
f57f2ef5 3947 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 3948
3949 return X86EMUL_CONTINUE;
4a5f48f6 3950
3200f405 3951emul_write:
daea3e73 3952 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 3953
0f65dd70 3954 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 3955}
3956
cf8f70bf
GN		 3957static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
3958{
3959 /* TODO: String I/O for in kernel device */
3960 int r;
3961
3962 if (vcpu->arch.pio.in)
3963 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
3964 vcpu->arch.pio.size, pd);
3965 else
3966 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
3967 vcpu->arch.pio.port, vcpu->arch.pio.size,
3968 pd);
3969 return r;
3970}
3971
6f6fbe98
XG		 3972static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
3973 unsigned short port, void *val,
3974 unsigned int count, bool in)
cf8f70bf 3975{
6f6fbe98 3976 trace_kvm_pio(!in, port, size, count);
cf8f70bf
GN		 3977
3978 vcpu->arch.pio.port = port;
6f6fbe98 3979 vcpu->arch.pio.in = in;
7972995b 3980 vcpu->arch.pio.count = count;
cf8f70bf
GN		 3981 vcpu->arch.pio.size = size;
3982
3983 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 3984 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 3985 return 1;
3986 }
3987
3988 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 3989 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 3990 vcpu->run->io.size = size;
3991 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
3992 vcpu->run->io.count = count;
3993 vcpu->run->io.port = port;
3994
3995 return 0;
3996}
3997
6f6fbe98
XG		 3998static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
3999 int size, unsigned short port, void *val,
4000 unsigned int count)
cf8f70bf 4001{
ca1d4a9e 4002 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4003 int ret;
ca1d4a9e 4004
6f6fbe98
XG		 4005 if (vcpu->arch.pio.count)
4006 goto data_avail;
cf8f70bf 4007
6f6fbe98
XG		 4008 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4009 if (ret) {
4010data_avail:
4011 memcpy(val, vcpu->arch.pio_data, size * count);
7972995b 4012 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4013 return 1;
4014 }
4015
cf8f70bf
GN		 4016 return 0;
4017}
4018
6f6fbe98
XG		 4019static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4020 int size, unsigned short port,
4021 const void *val, unsigned int count)
4022{
4023 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4024
4025 memcpy(vcpu->arch.pio_data, val, size * count);
4026 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4027}
4028
bbd9b64e
CO		 4029static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4030{
4031 return kvm_x86_ops->get_segment_base(vcpu, seg);
4032}
4033
3cb16fe7 4034static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4035{
3cb16fe7 4036 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4037}
4038
f5f48ee1
SY		 4039int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4040{
4041 if (!need_emulate_wbinvd(vcpu))
4042 return X86EMUL_CONTINUE;
4043
4044 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4045 int cpu = get_cpu();
4046
4047 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4048 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4049 wbinvd_ipi, NULL, 1);
2eec7343 4050 put_cpu();
f5f48ee1 4051 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4052 } else
4053 wbinvd();
f5f48ee1
SY		 4054 return X86EMUL_CONTINUE;
4055}
4056EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4057
bcaf5cc5
AK		 4058static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4059{
4060 kvm_emulate_wbinvd(emul_to_vcpu(ctxt));
4061}
4062
717746e3 4063int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
bbd9b64e 4064{
717746e3 4065 return _kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4066}
4067
717746e3 4068int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
bbd9b64e 4069{
338dbc97 4070
717746e3 4071 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4072}
4073
52a46617 4074static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4075{
52a46617 4076 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4077}
4078
717746e3 4079static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4080{
717746e3 4081 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4082 unsigned long value;
4083
4084 switch (cr) {
4085 case 0:
4086 value = kvm_read_cr0(vcpu);
4087 break;
4088 case 2:
4089 value = vcpu->arch.cr2;
4090 break;
4091 case 3:
9f8fe504 4092 value = kvm_read_cr3(vcpu);
52a46617
GN		 4093 break;
4094 case 4:
4095 value = kvm_read_cr4(vcpu);
4096 break;
4097 case 8:
4098 value = kvm_get_cr8(vcpu);
4099 break;
4100 default:
4101 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
4102 return 0;
4103 }
4104
4105 return value;
4106}
4107
717746e3 4108static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4109{
717746e3 4110 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4111 int res = 0;
4112
52a46617
GN		 4113 switch (cr) {
4114 case 0:
49a9b07e 4115 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4116 break;
4117 case 2:
4118 vcpu->arch.cr2 = val;
4119 break;
4120 case 3:
2390218b 4121 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4122 break;
4123 case 4:
a83b29c6 4124 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4125 break;
4126 case 8:
eea1cff9 4127 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4128 break;
4129 default:
4130 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
0f12244f 4131 res = -1;
52a46617 4132 }
0f12244f
GN		 4133
4134 return res;
52a46617
GN		 4135}
4136
4cee4798
KW		 4137static void emulator_set_rflags(struct x86_emulate_ctxt *ctxt, ulong val)
4138{
4139 kvm_set_rflags(emul_to_vcpu(ctxt), val);
4140}
4141
717746e3 4142static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 4143{
717746e3 4144 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 4145}
4146
4bff1e86 4147static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 4148{
4bff1e86 4149 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 4150}
4151
4bff1e86 4152static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 4153{
4bff1e86 4154 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 4155}
4156
1ac9d0cf
AK		 4157static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4158{
4159 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4160}
4161
4162static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4163{
4164 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4165}
4166
4bff1e86
AK		 4167static unsigned long emulator_get_cached_segment_base(
4168 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 4169{
4bff1e86 4170 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 4171}
4172
1aa36616
AK		 4173static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4174 struct desc_struct *desc, u32 *base3,
4175 int seg)
2dafc6c2
GN		 4176{
4177 struct kvm_segment var;
4178
4bff1e86 4179 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 4180 *selector = var.selector;
2dafc6c2
GN		 4181
4182 if (var.unusable)
4183 return false;
4184
4185 if (var.g)
4186 var.limit >>= 12;
4187 set_desc_limit(desc, var.limit);
4188 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 4189#ifdef CONFIG_X86_64
4190 if (base3)
4191 *base3 = var.base >> 32;
4192#endif
2dafc6c2
GN		 4193 desc->type = var.type;
4194 desc->s = var.s;
4195 desc->dpl = var.dpl;
4196 desc->p = var.present;
4197 desc->avl = var.avl;
4198 desc->l = var.l;
4199 desc->d = var.db;
4200 desc->g = var.g;
4201
4202 return true;
4203}
4204
1aa36616
AK		 4205static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4206 struct desc_struct *desc, u32 base3,
4207 int seg)
2dafc6c2 4208{
4bff1e86 4209 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 4210 struct kvm_segment var;
4211
1aa36616 4212 var.selector = selector;
2dafc6c2 4213 var.base = get_desc_base(desc);
5601d05b
GN		 4214#ifdef CONFIG_X86_64
4215 var.base |= ((u64)base3) << 32;
4216#endif
2dafc6c2
GN		 4217 var.limit = get_desc_limit(desc);
4218 if (desc->g)
4219 var.limit = (var.limit << 12) | 0xfff;
4220 var.type = desc->type;
4221 var.present = desc->p;
4222 var.dpl = desc->dpl;
4223 var.db = desc->d;
4224 var.s = desc->s;
4225 var.l = desc->l;
4226 var.g = desc->g;
4227 var.avl = desc->avl;
4228 var.present = desc->p;
4229 var.unusable = !var.present;
4230 var.padding = 0;
4231
4232 kvm_set_segment(vcpu, &var, seg);
4233 return;
4234}
4235
717746e3
AK		 4236static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4237 u32 msr_index, u64 *pdata)
4238{
4239 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
4240}
4241
4242static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4243 u32 msr_index, u64 data)
4244{
4245 return kvm_set_msr(emul_to_vcpu(ctxt), msr_index, data);
4246}
4247
222d21aa
AK		 4248static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4249 u32 pmc, u64 *pdata)
4250{
4251 return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata);
4252}
4253
6c3287f7
AK		 4254static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4255{
4256 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4257}
4258
5037f6f3
AK		 4259static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4260{
4261 preempt_disable();
5197b808 4262 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 4263 /*
4264 * CR0.TS may reference the host fpu state, not the guest fpu state,
4265 * so it may be clear at this point.
4266 */
4267 clts();
4268}
4269
4270static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4271{
4272 preempt_enable();
4273}
4274
2953538e 4275static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 4276 struct x86_instruction_info *info,
c4f035c6
AK		 4277 enum x86_intercept_stage stage)
4278{
2953538e 4279 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 4280}
4281
bdb42f5a
SB		 4282static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
4283 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4284{
4285 struct kvm_cpuid_entry2 *cpuid = NULL;
4286
4287 if (eax && ecx)
4288 cpuid = kvm_find_cpuid_entry(emul_to_vcpu(ctxt),
4289 *eax, *ecx);
4290
4291 if (cpuid) {
4292 *eax = cpuid->eax;
4293 *ecx = cpuid->ecx;
4294 if (ebx)
4295 *ebx = cpuid->ebx;
4296 if (edx)
4297 *edx = cpuid->edx;
4298 return true;
4299 }
4300
4301 return false;
4302}
4303
14af3f3c 4304static struct x86_emulate_ops emulate_ops = {
1871c602 4305 .read_std = kvm_read_guest_virt_system,
2dafc6c2 4306 .write_std = kvm_write_guest_virt_system,
1871c602 4307 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 4308 .read_emulated = emulator_read_emulated,
4309 .write_emulated = emulator_write_emulated,
4310 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 4311 .invlpg = emulator_invlpg,
cf8f70bf
GN		 4312 .pio_in_emulated = emulator_pio_in_emulated,
4313 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 4314 .get_segment = emulator_get_segment,
4315 .set_segment = emulator_set_segment,
5951c442 4316 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 4317 .get_gdt = emulator_get_gdt,
160ce1f1 4318 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 4319 .set_gdt = emulator_set_gdt,
4320 .set_idt = emulator_set_idt,
52a46617
GN		 4321 .get_cr = emulator_get_cr,
4322 .set_cr = emulator_set_cr,
4cee4798 4323 .set_rflags = emulator_set_rflags,
9c537244 4324 .cpl = emulator_get_cpl,
35aa5375
GN		 4325 .get_dr = emulator_get_dr,
4326 .set_dr = emulator_set_dr,
717746e3
AK		 4327 .set_msr = emulator_set_msr,
4328 .get_msr = emulator_get_msr,
222d21aa 4329 .read_pmc = emulator_read_pmc,
6c3287f7 4330 .halt = emulator_halt,
bcaf5cc5 4331 .wbinvd = emulator_wbinvd,
d6aa1000 4332 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 4333 .get_fpu = emulator_get_fpu,
4334 .put_fpu = emulator_put_fpu,
c4f035c6 4335 .intercept = emulator_intercept,
bdb42f5a 4336 .get_cpuid = emulator_get_cpuid,
bbd9b64e
CO		 4337};
4338
5fdbf976
MT		 4339static void cache_all_regs(struct kvm_vcpu *vcpu)
4340{
4341 kvm_register_read(vcpu, VCPU_REGS_RAX);
4342 kvm_register_read(vcpu, VCPU_REGS_RSP);
4343 kvm_register_read(vcpu, VCPU_REGS_RIP);
4344 vcpu->arch.regs_dirty = ~0;
4345}
4346
95cb2295
GN		 4347static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4348{
4349 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
4350 /*
4351 * an sti; sti; sequence only disable interrupts for the first
4352 * instruction. So, if the last instruction, be it emulated or
4353 * not, left the system with the INT_STI flag enabled, it
4354 * means that the last instruction is an sti. We should not
4355 * leave the flag on in this case. The same goes for mov ss
4356 */
4357 if (!(int_shadow & mask))
4358 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4359}
4360
54b8486f
GN		 4361static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4362{
4363 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 4364 if (ctxt->exception.vector == PF_VECTOR)
6389ee94 4365 kvm_propagate_fault(vcpu, &ctxt->exception);
da9cb575
AK		 4366 else if (ctxt->exception.error_code_valid)
4367 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4368 ctxt->exception.error_code);
54b8486f 4369 else
da9cb575 4370 kvm_queue_exception(vcpu, ctxt->exception.vector);
54b8486f
GN		 4371}
4372
9dac77fa 4373static void init_decode_cache(struct x86_emulate_ctxt *ctxt,
b5c9ff73
TY		 4374 const unsigned long *regs)
4375{
9dac77fa
AK		 4376 memset(&ctxt->twobyte, 0,
4377 (void *)&ctxt->regs - (void *)&ctxt->twobyte);
4378 memcpy(ctxt->regs, regs, sizeof(ctxt->regs));
b5c9ff73 4379
9dac77fa
AK		 4380 ctxt->fetch.start = 0;
4381 ctxt->fetch.end = 0;
4382 ctxt->io_read.pos = 0;
4383 ctxt->io_read.end = 0;
4384 ctxt->mem_read.pos = 0;
4385 ctxt->mem_read.end = 0;
b5c9ff73
TY		 4386}
4387
8ec4722d
MG		 4388static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4389{
adf52235 4390 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 4391 int cs_db, cs_l;
4392
2aab2c5b
GN		 4393 /*
4394 * TODO: fix emulate.c to use guest_read/write_register
4395 * instead of direct ->regs accesses, can save hundred cycles
4396 * on Intel for instructions that don't read/change RSP, for
4397 * for example.
4398 */
8ec4722d
MG		 4399 cache_all_regs(vcpu);
4400
4401 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4402
adf52235
TY		 4403 ctxt->eflags = kvm_get_rflags(vcpu);
4404 ctxt->eip = kvm_rip_read(vcpu);
4405 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4406 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
4407 cs_l ? X86EMUL_MODE_PROT64 :
4408 cs_db ? X86EMUL_MODE_PROT32 :
4409 X86EMUL_MODE_PROT16;
4410 ctxt->guest_mode = is_guest_mode(vcpu);
4411
9dac77fa 4412 init_decode_cache(ctxt, vcpu->arch.regs);
7ae441ea 4413 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 4414}
4415
71f9833b 4416int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 4417{
9d74191a 4418 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 4419 int ret;
4420
4421 init_emulate_ctxt(vcpu);
4422
9dac77fa
AK		 4423 ctxt->op_bytes = 2;
4424 ctxt->ad_bytes = 2;
4425 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 4426 ret = emulate_int_real(ctxt, irq);
63995653
MG		 4427
4428 if (ret != X86EMUL_CONTINUE)
4429 return EMULATE_FAIL;
4430
9dac77fa
AK		 4431 ctxt->eip = ctxt->_eip;
4432 memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs);
9d74191a
TY		 4433 kvm_rip_write(vcpu, ctxt->eip);
4434 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 4435
4436 if (irq == NMI_VECTOR)
7460fb4a 4437 vcpu->arch.nmi_pending = 0;
63995653
MG		 4438 else
4439 vcpu->arch.interrupt.pending = false;
4440
4441 return EMULATE_DONE;
4442}
4443EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4444
6d77dbfc
GN		 4445static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4446{
fc3a9157
JR		 4447 int r = EMULATE_DONE;
4448
6d77dbfc
GN		 4449 ++vcpu->stat.insn_emulation_fail;
4450 trace_kvm_emulate_insn_failed(vcpu);
fc3a9157
JR		 4451 if (!is_guest_mode(vcpu)) {
4452 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4453 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4454 vcpu->run->internal.ndata = 0;
4455 r = EMULATE_FAIL;
4456 }
6d77dbfc 4457 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 4458
4459 return r;
6d77dbfc
GN		 4460}
4461
a6f177ef
GN		 4462static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t gva)
4463{
4464 gpa_t gpa;
4465
68be0803
GN		 4466 if (tdp_enabled)
4467 return false;
4468
a6f177ef
GN		 4469 /*
4470 * if emulation was due to access to shadowed page table
4471 * and it failed try to unshadow page and re-entetr the
4472 * guest to let CPU execute the instruction.
4473 */
4474 if (kvm_mmu_unprotect_page_virt(vcpu, gva))
4475 return true;
4476
4477 gpa = kvm_mmu_gva_to_gpa_system(vcpu, gva, NULL);
4478
4479 if (gpa == UNMAPPED_GVA)
4480 return true; /* let cpu generate fault */
4481
4482 if (!kvm_is_error_hva(gfn_to_hva(vcpu->kvm, gpa >> PAGE_SHIFT)))
4483 return true;
4484
4485 return false;
4486}
4487
1cb3f3ae
XG		 4488static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
4489 unsigned long cr2, int emulation_type)
4490{
4491 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4492 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
4493
4494 last_retry_eip = vcpu->arch.last_retry_eip;
4495 last_retry_addr = vcpu->arch.last_retry_addr;
4496
4497 /*
4498 * If the emulation is caused by #PF and it is non-page_table
4499 * writing instruction, it means the VM-EXIT is caused by shadow
4500 * page protected, we can zap the shadow page and retry this
4501 * instruction directly.
4502 *
4503 * Note: if the guest uses a non-page-table modifying instruction
4504 * on the PDE that points to the instruction, then we will unmap
4505 * the instruction and go to an infinite loop. So, we cache the
4506 * last retried eip and the last fault address, if we meet the eip
4507 * and the address again, we can break out of the potential infinite
4508 * loop.
4509 */
4510 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
4511
4512 if (!(emulation_type & EMULTYPE_RETRY))
4513 return false;
4514
4515 if (x86_page_table_writing_insn(ctxt))
4516 return false;
4517
4518 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
4519 return false;
4520
4521 vcpu->arch.last_retry_eip = ctxt->eip;
4522 vcpu->arch.last_retry_addr = cr2;
4523
4524 if (!vcpu->arch.mmu.direct_map)
4525 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
4526
4527 kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT);
4528
4529 return true;
4530}
4531
51d8b661
AP		 4532int x86_emulate_instruction(struct kvm_vcpu *vcpu,
4533 unsigned long cr2,
dc25e89e
AP		 4534 int emulation_type,
4535 void *insn,
4536 int insn_len)
bbd9b64e 4537{
95cb2295 4538 int r;
9d74191a 4539 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 4540 bool writeback = true;
bbd9b64e 4541
26eef70c 4542 kvm_clear_exception_queue(vcpu);
8d7d8102 4543
571008da 4544 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 4545 init_emulate_ctxt(vcpu);
9d74191a
TY		 4546 ctxt->interruptibility = 0;
4547 ctxt->have_exception = false;
4548 ctxt->perm_ok = false;
bbd9b64e 4549
9d74191a 4550 ctxt->only_vendor_specific_insn
4005996e
AK		 4551 = emulation_type & EMULTYPE_TRAP_UD;
4552
9d74191a 4553 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 4554
e46479f8 4555 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 4556 ++vcpu->stat.insn_emulation;
1d2887e2 4557 if (r != EMULATION_OK) {
4005996e
AK		 4558 if (emulation_type & EMULTYPE_TRAP_UD)
4559 return EMULATE_FAIL;
a6f177ef 4560 if (reexecute_instruction(vcpu, cr2))
bbd9b64e 4561 return EMULATE_DONE;
6d77dbfc
GN		 4562 if (emulation_type & EMULTYPE_SKIP)
4563 return EMULATE_FAIL;
4564 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4565 }
4566 }
4567
ba8afb6b 4568 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 4569 kvm_rip_write(vcpu, ctxt->_eip);
ba8afb6b
GN		 4570 return EMULATE_DONE;
4571 }
4572
1cb3f3ae
XG		 4573 if (retry_instruction(ctxt, cr2, emulation_type))
4574 return EMULATE_DONE;
4575
7ae441ea 4576 /* this is needed for vmware backdoor interface to work since it
4d2179e1 4577 changes registers values during IO operation */
7ae441ea
GN		 4578 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
4579 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
9dac77fa 4580 memcpy(ctxt->regs, vcpu->arch.regs, sizeof ctxt->regs);
7ae441ea 4581 }
4d2179e1 4582
5cd21917 4583restart:
9d74191a 4584 r = x86_emulate_insn(ctxt);
bbd9b64e 4585
775fde86
JR		 4586 if (r == EMULATION_INTERCEPTED)
4587 return EMULATE_DONE;
4588
d2ddd1c4 4589 if (r == EMULATION_FAILED) {
a6f177ef 4590 if (reexecute_instruction(vcpu, cr2))
c3cd7ffa
GN		 4591 return EMULATE_DONE;
4592
6d77dbfc 4593 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4594 }
4595
9d74191a 4596 if (ctxt->have_exception) {
54b8486f 4597 inject_emulated_exception(vcpu);
d2ddd1c4
GN		 4598 r = EMULATE_DONE;
4599 } else if (vcpu->arch.pio.count) {
3457e419
GN		 4600 if (!vcpu->arch.pio.in)
4601 vcpu->arch.pio.count = 0;
7ae441ea
GN		 4602 else
4603 writeback = false;
e85d28f8 4604 r = EMULATE_DO_MMIO;
7ae441ea
GN		 4605 } else if (vcpu->mmio_needed) {
4606 if (!vcpu->mmio_is_write)
4607 writeback = false;
e85d28f8 4608 r = EMULATE_DO_MMIO;
7ae441ea 4609 } else if (r == EMULATION_RESTART)
5cd21917 4610 goto restart;
d2ddd1c4
GN		 4611 else
4612 r = EMULATE_DONE;
f850e2e6 4613
7ae441ea 4614 if (writeback) {
9d74191a
TY		 4615 toggle_interruptibility(vcpu, ctxt->interruptibility);
4616 kvm_set_rflags(vcpu, ctxt->eflags);
7ae441ea 4617 kvm_make_request(KVM_REQ_EVENT, vcpu);
9dac77fa 4618 memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs);
7ae441ea 4619 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 4620 kvm_rip_write(vcpu, ctxt->eip);
7ae441ea
GN		 4621 } else
4622 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 4623
4624 return r;
de7d789a 4625}
51d8b661 4626EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 4627
cf8f70bf 4628int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 4629{
cf8f70bf 4630 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 4631 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
4632 size, port, &val, 1);
cf8f70bf 4633 /* do not return to emulator after return from userspace */
7972995b 4634 vcpu->arch.pio.count = 0;
de7d789a
CO		 4635 return ret;
4636}
cf8f70bf 4637EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 4638
8cfdc000
ZA		 4639static void tsc_bad(void *info)
4640{
0a3aee0d 4641 __this_cpu_write(cpu_tsc_khz, 0);
8cfdc000
ZA		 4642}
4643
4644static void tsc_khz_changed(void *data)
c8076604 4645{
8cfdc000
ZA		 4646 struct cpufreq_freqs *freq = data;
4647 unsigned long khz = 0;
4648
4649 if (data)
4650 khz = freq->new;
4651 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4652 khz = cpufreq_quick_get(raw_smp_processor_id());
4653 if (!khz)
4654 khz = tsc_khz;
0a3aee0d 4655 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 4656}
4657
c8076604
GH		 4658static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
4659 void *data)
4660{
4661 struct cpufreq_freqs *freq = data;
4662 struct kvm *kvm;
4663 struct kvm_vcpu *vcpu;
4664 int i, send_ipi = 0;
4665
8cfdc000
ZA		 4666 /*
4667 * We allow guests to temporarily run on slowing clocks,
4668 * provided we notify them after, or to run on accelerating
4669 * clocks, provided we notify them before. Thus time never
4670 * goes backwards.
4671 *
4672 * However, we have a problem. We can't atomically update
4673 * the frequency of a given CPU from this function; it is
4674 * merely a notifier, which can be called from any CPU.
4675 * Changing the TSC frequency at arbitrary points in time
4676 * requires a recomputation of local variables related to
4677 * the TSC for each VCPU. We must flag these local variables
4678 * to be updated and be sure the update takes place with the
4679 * new frequency before any guests proceed.
4680 *
4681 * Unfortunately, the combination of hotplug CPU and frequency
4682 * change creates an intractable locking scenario; the order
4683 * of when these callouts happen is undefined with respect to
4684 * CPU hotplug, and they can race with each other. As such,
4685 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
4686 * undefined; you can actually have a CPU frequency change take
4687 * place in between the computation of X and the setting of the
4688 * variable. To protect against this problem, all updates of
4689 * the per_cpu tsc_khz variable are done in an interrupt
4690 * protected IPI, and all callers wishing to update the value
4691 * must wait for a synchronous IPI to complete (which is trivial
4692 * if the caller is on the CPU already). This establishes the
4693 * necessary total order on variable updates.
4694 *
4695 * Note that because a guest time update may take place
4696 * anytime after the setting of the VCPU's request bit, the
4697 * correct TSC value must be set before the request. However,
4698 * to ensure the update actually makes it to any guest which
4699 * starts running in hardware virtualization between the set
4700 * and the acquisition of the spinlock, we must also ping the
4701 * CPU after setting the request bit.
4702 *
4703 */
4704
c8076604
GH		 4705 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
4706 return 0;
4707 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
4708 return 0;
8cfdc000
ZA		 4709
4710 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 4711
e935b837 4712 raw_spin_lock(&kvm_lock);
c8076604 4713 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 4714 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 4715 if (vcpu->cpu != freq->cpu)
4716 continue;
c285545f 4717 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 4718 if (vcpu->cpu != smp_processor_id())
8cfdc000 4719 send_ipi = 1;
c8076604
GH		 4720 }
4721 }
e935b837 4722 raw_spin_unlock(&kvm_lock);
c8076604
GH		 4723
4724 if (freq->old < freq->new && send_ipi) {
4725 /*
4726 * We upscale the frequency. Must make the guest
4727 * doesn't see old kvmclock values while running with
4728 * the new frequency, otherwise we risk the guest sees
4729 * time go backwards.
4730 *
4731 * In case we update the frequency for another cpu
4732 * (which might be in guest context) send an interrupt
4733 * to kick the cpu out of guest context. Next time
4734 * guest context is entered kvmclock will be updated,
4735 * so the guest will not see stale values.
4736 */
8cfdc000 4737 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 4738 }
4739 return 0;
4740}
4741
4742static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 4743 .notifier_call = kvmclock_cpufreq_notifier
4744};
4745
4746static int kvmclock_cpu_notifier(struct notifier_block *nfb,
4747 unsigned long action, void *hcpu)
4748{
4749 unsigned int cpu = (unsigned long)hcpu;
4750
4751 switch (action) {
4752 case CPU_ONLINE:
4753 case CPU_DOWN_FAILED:
4754 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
4755 break;
4756 case CPU_DOWN_PREPARE:
4757 smp_call_function_single(cpu, tsc_bad, NULL, 1);
4758 break;
4759 }
4760 return NOTIFY_OK;
4761}
4762
4763static struct notifier_block kvmclock_cpu_notifier_block = {
4764 .notifier_call = kvmclock_cpu_notifier,
4765 .priority = -INT_MAX
c8076604
GH		 4766};
4767
b820cc0c
ZA		 4768static void kvm_timer_init(void)
4769{
4770 int cpu;
4771
c285545f 4772 max_tsc_khz = tsc_khz;
8cfdc000 4773 register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
b820cc0c 4774 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 4775#ifdef CONFIG_CPU_FREQ
4776 struct cpufreq_policy policy;
4777 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 4778 cpu = get_cpu();
4779 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 4780 if (policy.cpuinfo.max_freq)
4781 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 4782 put_cpu();
c285545f 4783#endif
b820cc0c
ZA		 4784 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
4785 CPUFREQ_TRANSITION_NOTIFIER);
4786 }
c285545f 4787 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 4788 for_each_online_cpu(cpu)
4789 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
b820cc0c
ZA		 4790}
4791
ff9d07a0
ZY		 4792static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
4793
f5132b01 4794int kvm_is_in_guest(void)
ff9d07a0 4795{
086c9855 4796 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 4797}
4798
4799static int kvm_is_user_mode(void)
4800{
4801 int user_mode = 3;
dcf46b94 4802
086c9855
AS		 4803 if (__this_cpu_read(current_vcpu))
4804 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 4805
ff9d07a0
ZY		 4806 return user_mode != 0;
4807}
4808
4809static unsigned long kvm_get_guest_ip(void)
4810{
4811 unsigned long ip = 0;
dcf46b94 4812
086c9855
AS		 4813 if (__this_cpu_read(current_vcpu))
4814 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 4815
ff9d07a0
ZY		 4816 return ip;
4817}
4818
4819static struct perf_guest_info_callbacks kvm_guest_cbs = {
4820 .is_in_guest = kvm_is_in_guest,
4821 .is_user_mode = kvm_is_user_mode,
4822 .get_guest_ip = kvm_get_guest_ip,
4823};
4824
4825void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
4826{
086c9855 4827 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 4828}
4829EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
4830
4831void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
4832{
086c9855 4833 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 4834}
4835EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
4836
ce88decf
XG		 4837static void kvm_set_mmio_spte_mask(void)
4838{
4839 u64 mask;
4840 int maxphyaddr = boot_cpu_data.x86_phys_bits;
4841
4842 /*
4843 * Set the reserved bits and the present bit of an paging-structure
4844 * entry to generate page fault with PFER.RSV = 1.
4845 */
4846 mask = ((1ull << (62 - maxphyaddr + 1)) - 1) << maxphyaddr;
4847 mask |= 1ull;
4848
4849#ifdef CONFIG_X86_64
4850 /*
4851 * If reserved bit is not supported, clear the present bit to disable
4852 * mmio page fault.
4853 */
4854 if (maxphyaddr == 52)
4855 mask &= ~1ull;
4856#endif
4857
4858 kvm_mmu_set_mmio_spte_mask(mask);
4859}
4860
f8c16bba 4861int kvm_arch_init(void *opaque)
043405e1 4862{
b820cc0c 4863 int r;
f8c16bba
ZX		 4864 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
4865
f8c16bba
ZX		 4866 if (kvm_x86_ops) {
4867 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 4868 r = -EEXIST;
4869 goto out;
f8c16bba
ZX		 4870 }
4871
4872 if (!ops->cpu_has_kvm_support()) {
4873 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 4874 r = -EOPNOTSUPP;
4875 goto out;
f8c16bba
ZX		 4876 }
4877 if (ops->disabled_by_bios()) {
4878 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 4879 r = -EOPNOTSUPP;
4880 goto out;
f8c16bba
ZX		 4881 }
4882
97db56ce
AK		 4883 r = kvm_mmu_module_init();
4884 if (r)
4885 goto out;
4886
ce88decf 4887 kvm_set_mmio_spte_mask();
97db56ce
AK		 4888 kvm_init_msr_list();
4889
f8c16bba 4890 kvm_x86_ops = ops;
7b52345e 4891 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 4892 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 4893
b820cc0c 4894 kvm_timer_init();
c8076604 4895
ff9d07a0
ZY		 4896 perf_register_guest_info_callbacks(&kvm_guest_cbs);
4897
2acf923e
DC		 4898 if (cpu_has_xsave)
4899 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
4900
f8c16bba 4901 return 0;
56c6d28a
ZX		 4902
4903out:
56c6d28a 4904 return r;
043405e1 4905}
8776e519 4906
f8c16bba
ZX		 4907void kvm_arch_exit(void)
4908{
ff9d07a0
ZY		 4909 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
4910
888d256e
JK		 4911 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4912 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
4913 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 4914 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
f8c16bba 4915 kvm_x86_ops = NULL;
56c6d28a
ZX		 4916 kvm_mmu_module_exit();
4917}
f8c16bba 4918
8776e519
HB		 4919int kvm_emulate_halt(struct kvm_vcpu *vcpu)
4920{
4921 ++vcpu->stat.halt_exits;
4922 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 4923 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 4924 return 1;
4925 } else {
4926 vcpu->run->exit_reason = KVM_EXIT_HLT;
4927 return 0;
4928 }
4929}
4930EXPORT_SYMBOL_GPL(kvm_emulate_halt);
4931
55cd8e5a
GN		 4932int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
4933{
4934 u64 param, ingpa, outgpa, ret;
4935 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
4936 bool fast, longmode;
4937 int cs_db, cs_l;
4938
4939 /*
4940 * hypercall generates UD from non zero cpl and real mode
4941 * per HYPER-V spec
4942 */
3eeb3288 4943 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 4944 kvm_queue_exception(vcpu, UD_VECTOR);
4945 return 0;
4946 }
4947
4948 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4949 longmode = is_long_mode(vcpu) && cs_l == 1;
4950
4951 if (!longmode) {
ccd46936
GN		 4952 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
4953 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
4954 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
4955 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
4956 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
4957 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 4958 }
4959#ifdef CONFIG_X86_64
4960 else {
4961 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
4962 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
4963 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
4964 }
4965#endif
4966
4967 code = param & 0xffff;
4968 fast = (param >> 16) & 0x1;
4969 rep_cnt = (param >> 32) & 0xfff;
4970 rep_idx = (param >> 48) & 0xfff;
4971
4972 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
4973
c25bc163
GN		 4974 switch (code) {
4975 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
4976 kvm_vcpu_on_spin(vcpu);
4977 break;
4978 default:
4979 res = HV_STATUS_INVALID_HYPERCALL_CODE;
4980 break;
4981 }
55cd8e5a
GN		 4982
4983 ret = res | (((u64)rep_done & 0xfff) << 32);
4984 if (longmode) {
4985 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
4986 } else {
4987 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
4988 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
4989 }
4990
4991 return 1;
4992}
4993
8776e519
HB		 4994int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
4995{
4996 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 4997 int r = 1;
8776e519 4998
55cd8e5a
GN		 4999 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5000 return kvm_hv_hypercall(vcpu);
5001
5fdbf976
MT		 5002 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5003 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5004 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5005 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5006 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 5007
229456fc 5008 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 5009
8776e519
HB		 5010 if (!is_long_mode(vcpu)) {
5011 nr &= 0xFFFFFFFF;
5012 a0 &= 0xFFFFFFFF;
5013 a1 &= 0xFFFFFFFF;
5014 a2 &= 0xFFFFFFFF;
5015 a3 &= 0xFFFFFFFF;
5016 }
5017
07708c4a
JK		 5018 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5019 ret = -KVM_EPERM;
5020 goto out;
5021 }
5022
8776e519 5023 switch (nr) {
b93463aa
AK		 5024 case KVM_HC_VAPIC_POLL_IRQ:
5025 ret = 0;
5026 break;
8776e519
HB		 5027 default:
5028 ret = -KVM_ENOSYS;
5029 break;
5030 }
07708c4a 5031out:
5fdbf976 5032 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 5033 ++vcpu->stat.hypercalls;
2f333bcb 5034 return r;
8776e519
HB		 5035}
5036EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5037
d6aa1000 5038int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 5039{
d6aa1000 5040 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 5041 char instruction[3];
5fdbf976 5042 unsigned long rip = kvm_rip_read(vcpu);
8776e519 5043
8776e519
HB		 5044 /*
5045 * Blow out the MMU to ensure that no other VCPU has an active mapping
5046 * to ensure that the updated hypercall appears atomically across all
5047 * VCPUs.
5048 */
5049 kvm_mmu_zap_all(vcpu->kvm);
5050
8776e519 5051 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 5052
9d74191a 5053 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
8776e519
HB		 5054}
5055
b6c7a5dc
HB		 5056/*
5057 * Check if userspace requested an interrupt window, and that the
5058 * interrupt window is open.
5059 *
5060 * No need to exit to userspace if we already have an interrupt queued.
5061 */
851ba692 5062static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 5063{
8061823a 5064 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 5065 vcpu->run->request_interrupt_window &&
5df56646 5066 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 5067}
5068
851ba692 5069static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 5070{
851ba692
AK		 5071 struct kvm_run *kvm_run = vcpu->run;
5072
91586a3b 5073 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 5074 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 5075 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 5076 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 5077 kvm_run->ready_for_interrupt_injection = 1;
4531220b 5078 else
b6c7a5dc 5079 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 5080 kvm_arch_interrupt_allowed(vcpu) &&
5081 !kvm_cpu_has_interrupt(vcpu) &&
5082 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 5083}
5084
b93463aa
AK		 5085static void vapic_enter(struct kvm_vcpu *vcpu)
5086{
5087 struct kvm_lapic *apic = vcpu->arch.apic;
5088 struct page *page;
5089
5090 if (!apic || !apic->vapic_addr)
5091 return;
5092
5093 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
72dc67a6
IE		 5094
5095 vcpu->arch.apic->vapic_page = page;
b93463aa
AK		 5096}
5097
5098static void vapic_exit(struct kvm_vcpu *vcpu)
5099{
5100 struct kvm_lapic *apic = vcpu->arch.apic;
f656ce01 5101 int idx;
b93463aa
AK		 5102
5103 if (!apic || !apic->vapic_addr)
5104 return;
5105
f656ce01 5106 idx = srcu_read_lock(&vcpu->kvm->srcu);
b93463aa
AK		 5107 kvm_release_page_dirty(apic->vapic_page);
5108 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f656ce01 5109 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 5110}
5111
95ba8273
GN		 5112static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5113{
5114 int max_irr, tpr;
5115
5116 if (!kvm_x86_ops->update_cr8_intercept)
5117 return;
5118
88c808fd
AK		 5119 if (!vcpu->arch.apic)
5120 return;
5121
8db3baa2
GN		 5122 if (!vcpu->arch.apic->vapic_addr)
5123 max_irr = kvm_lapic_find_highest_irr(vcpu);
5124 else
5125 max_irr = -1;
95ba8273
GN		 5126
5127 if (max_irr != -1)
5128 max_irr >>= 4;
5129
5130 tpr = kvm_lapic_get_cr8(vcpu);
5131
5132 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5133}
5134
851ba692 5135static void inject_pending_event(struct kvm_vcpu *vcpu)
95ba8273
GN		 5136{
5137 /* try to reinject previous events if any */
b59bb7bd 5138 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 5139 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5140 vcpu->arch.exception.has_error_code,
5141 vcpu->arch.exception.error_code);
b59bb7bd
GN		 5142 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5143 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 5144 vcpu->arch.exception.error_code,
5145 vcpu->arch.exception.reinject);
b59bb7bd
GN		 5146 return;
5147 }
5148
95ba8273
GN		 5149 if (vcpu->arch.nmi_injected) {
5150 kvm_x86_ops->set_nmi(vcpu);
5151 return;
5152 }
5153
5154 if (vcpu->arch.interrupt.pending) {
66fd3f7f 5155 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5156 return;
5157 }
5158
5159 /* try to inject new event if pending */
5160 if (vcpu->arch.nmi_pending) {
5161 if (kvm_x86_ops->nmi_allowed(vcpu)) {
7460fb4a 5162 --vcpu->arch.nmi_pending;
95ba8273
GN		 5163 vcpu->arch.nmi_injected = true;
5164 kvm_x86_ops->set_nmi(vcpu);
5165 }
5166 } else if (kvm_cpu_has_interrupt(vcpu)) {
5167 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 5168 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5169 false);
5170 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5171 }
5172 }
5173}
5174
2acf923e
DC		 5175static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
5176{
5177 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
5178 !vcpu->guest_xcr0_loaded) {
5179 /* kvm_set_xcr() also depends on this */
5180 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
5181 vcpu->guest_xcr0_loaded = 1;
5182 }
5183}
5184
5185static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
5186{
5187 if (vcpu->guest_xcr0_loaded) {
5188 if (vcpu->arch.xcr0 != host_xcr0)
5189 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
5190 vcpu->guest_xcr0_loaded = 0;
5191 }
5192}
5193
7460fb4a
AK		 5194static void process_nmi(struct kvm_vcpu *vcpu)
5195{
5196 unsigned limit = 2;
5197
5198 /*
5199 * x86 is limited to one NMI running, and one NMI pending after it.
5200 * If an NMI is already in progress, limit further NMIs to just one.
5201 * Otherwise, allow two (and we'll inject the first one immediately).
5202 */
5203 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
5204 limit = 1;
5205
5206 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
5207 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
5208 kvm_make_request(KVM_REQ_EVENT, vcpu);
5209}
5210
851ba692 5211static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 5212{
5213 int r;
6a8b1d13 5214 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 5215 vcpu->run->request_interrupt_window;
d6185f20 5216 bool req_immediate_exit = 0;
b6c7a5dc 5217
3e007509 5218 if (vcpu->requests) {
a8eeb04a 5219 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 5220 kvm_mmu_unload(vcpu);
a8eeb04a 5221 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 5222 __kvm_migrate_timers(vcpu);
34c238a1
ZA		 5223 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
5224 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 5225 if (unlikely(r))
5226 goto out;
5227 }
a8eeb04a 5228 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 5229 kvm_mmu_sync_roots(vcpu);
a8eeb04a 5230 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
d4acf7e7 5231 kvm_x86_ops->tlb_flush(vcpu);
a8eeb04a 5232 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 5233 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 5234 r = 0;
5235 goto out;
5236 }
a8eeb04a 5237 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 5238 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 5239 r = 0;
5240 goto out;
5241 }
a8eeb04a 5242 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 5243 vcpu->fpu_active = 0;
5244 kvm_x86_ops->fpu_deactivate(vcpu);
5245 }
af585b92
GN		 5246 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
5247 /* Page is swapped out. Do synthetic halt */
5248 vcpu->arch.apf.halted = true;
5249 r = 1;
5250 goto out;
5251 }
c9aaa895
GC		 5252 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
5253 record_steal_time(vcpu);
7460fb4a
AK		 5254 if (kvm_check_request(KVM_REQ_NMI, vcpu))
5255 process_nmi(vcpu);
d6185f20
NHE		 5256 req_immediate_exit =
5257 kvm_check_request(KVM_REQ_IMMEDIATE_EXIT, vcpu);
f5132b01
GN		 5258 if (kvm_check_request(KVM_REQ_PMU, vcpu))
5259 kvm_handle_pmu_event(vcpu);
5260 if (kvm_check_request(KVM_REQ_PMI, vcpu))
5261 kvm_deliver_pmi(vcpu);
2f52d58c 5262 }
b93463aa 5263
3e007509
AK		 5264 r = kvm_mmu_reload(vcpu);
5265 if (unlikely(r))
5266 goto out;
5267
b463a6f7
AK		 5268 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
5269 inject_pending_event(vcpu);
5270
5271 /* enable NMI/IRQ window open exits if needed */
7460fb4a 5272 if (vcpu->arch.nmi_pending)
b463a6f7
AK		 5273 kvm_x86_ops->enable_nmi_window(vcpu);
5274 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
5275 kvm_x86_ops->enable_irq_window(vcpu);
5276
5277 if (kvm_lapic_enabled(vcpu)) {
5278 update_cr8_intercept(vcpu);
5279 kvm_lapic_sync_to_vapic(vcpu);
5280 }
5281 }
5282
b6c7a5dc
HB		 5283 preempt_disable();
5284
5285 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 5286 if (vcpu->fpu_active)
5287 kvm_load_guest_fpu(vcpu);
2acf923e 5288 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 5289
6b7e2d09
XG		 5290 vcpu->mode = IN_GUEST_MODE;
5291
5292 /* We should set ->mode before check ->requests,
5293 * see the comment in make_all_cpus_request.
5294 */
5295 smp_mb();
b6c7a5dc 5296
d94e1dc9 5297 local_irq_disable();
32f88400 5298
6b7e2d09 5299 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 5300 || need_resched() || signal_pending(current)) {
6b7e2d09 5301 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 5302 smp_wmb();
6c142801
AK		 5303 local_irq_enable();
5304 preempt_enable();
b463a6f7 5305 kvm_x86_ops->cancel_injection(vcpu);
6c142801
AK		 5306 r = 1;
5307 goto out;
5308 }
5309
f656ce01 5310 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
3200f405 5311
d6185f20
NHE		 5312 if (req_immediate_exit)
5313 smp_send_reschedule(vcpu->cpu);
5314
b6c7a5dc
HB		 5315 kvm_guest_enter();
5316
42dbaa5a 5317 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 5318 set_debugreg(0, 7);
5319 set_debugreg(vcpu->arch.eff_db[0], 0);
5320 set_debugreg(vcpu->arch.eff_db[1], 1);
5321 set_debugreg(vcpu->arch.eff_db[2], 2);
5322 set_debugreg(vcpu->arch.eff_db[3], 3);
5323 }
b6c7a5dc 5324
229456fc 5325 trace_kvm_entry(vcpu->vcpu_id);
851ba692 5326 kvm_x86_ops->run(vcpu);
b6c7a5dc 5327
24f1e32c
FW		 5328 /*
5329 * If the guest has used debug registers, at least dr7
5330 * will be disabled while returning to the host.
5331 * If we don't have active breakpoints in the host, we don't
5332 * care about the messed up debug address registers. But if
5333 * we have some of them active, restore the old state.
5334 */
59d8eb53 5335 if (hw_breakpoint_active())
24f1e32c 5336 hw_breakpoint_restore();
42dbaa5a 5337
d5c1785d 5338 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu);
1d5f066e 5339
6b7e2d09 5340 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 5341 smp_wmb();
b6c7a5dc
HB		 5342 local_irq_enable();
5343
5344 ++vcpu->stat.exits;
5345
5346 /*
5347 * We must have an instruction between local_irq_enable() and
5348 * kvm_guest_exit(), so the timer interrupt isn't delayed by
5349 * the interrupt shadow. The stat.exits increment will do nicely.
5350 * But we need to prevent reordering, hence this barrier():
5351 */
5352 barrier();
5353
5354 kvm_guest_exit();
5355
5356 preempt_enable();
5357
f656ce01 5358 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 5359
b6c7a5dc
HB		 5360 /*
5361 * Profile KVM exit RIPs:
5362 */
5363 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 5364 unsigned long rip = kvm_rip_read(vcpu);
5365 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 5366 }
5367
cc578287
ZA		 5368 if (unlikely(vcpu->arch.tsc_always_catchup))
5369 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 5370
b93463aa
AK		 5371 kvm_lapic_sync_from_vapic(vcpu);
5372
851ba692 5373 r = kvm_x86_ops->handle_exit(vcpu);
d7690175
MT		 5374out:
5375 return r;
5376}
b6c7a5dc 5377
09cec754 5378
851ba692 5379static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 5380{
5381 int r;
f656ce01 5382 struct kvm *kvm = vcpu->kvm;
d7690175
MT		 5383
5384 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
1b10bf31
JK		 5385 pr_debug("vcpu %d received sipi with vector # %x\n",
5386 vcpu->vcpu_id, vcpu->arch.sipi_vector);
d7690175 5387 kvm_lapic_reset(vcpu);
5f179287 5388 r = kvm_arch_vcpu_reset(vcpu);
d7690175
MT		 5389 if (r)
5390 return r;
5391 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 5392 }
5393
f656ce01 5394 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175
MT		 5395 vapic_enter(vcpu);
5396
5397 r = 1;
5398 while (r > 0) {
af585b92
GN		 5399 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
5400 !vcpu->arch.apf.halted)
851ba692 5401 r = vcpu_enter_guest(vcpu);
d7690175 5402 else {
f656ce01 5403 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 5404 kvm_vcpu_block(vcpu);
f656ce01 5405 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
a8eeb04a 5406 if (kvm_check_request(KVM_REQ_UNHALT, vcpu))
09cec754
GN		 5407 {
5408 switch(vcpu->arch.mp_state) {
5409 case KVM_MP_STATE_HALTED:
d7690175 5410 vcpu->arch.mp_state =
09cec754
GN		 5411 KVM_MP_STATE_RUNNABLE;
5412 case KVM_MP_STATE_RUNNABLE:
af585b92 5413 vcpu->arch.apf.halted = false;
09cec754
GN		 5414 break;
5415 case KVM_MP_STATE_SIPI_RECEIVED:
5416 default:
5417 r = -EINTR;
5418 break;
5419 }
5420 }
d7690175
MT		 5421 }
5422
09cec754
GN		 5423 if (r <= 0)
5424 break;
5425
5426 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
5427 if (kvm_cpu_has_pending_timer(vcpu))
5428 kvm_inject_pending_timer_irqs(vcpu);
5429
851ba692 5430 if (dm_request_for_irq_injection(vcpu)) {
09cec754 5431 r = -EINTR;
851ba692 5432 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5433 ++vcpu->stat.request_irq_exits;
5434 }
af585b92
GN		 5435
5436 kvm_check_async_pf_completion(vcpu);
5437
09cec754
GN		 5438 if (signal_pending(current)) {
5439 r = -EINTR;
851ba692 5440 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5441 ++vcpu->stat.signal_exits;
5442 }
5443 if (need_resched()) {
f656ce01 5444 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
09cec754 5445 kvm_resched(vcpu);
f656ce01 5446 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 5447 }
b6c7a5dc
HB		 5448 }
5449
f656ce01 5450 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc 5451
b93463aa
AK		 5452 vapic_exit(vcpu);
5453
b6c7a5dc
HB		 5454 return r;
5455}
5456
5287f194
AK		 5457static int complete_mmio(struct kvm_vcpu *vcpu)
5458{
5459 struct kvm_run *run = vcpu->run;
5460 int r;
5461
5462 if (!(vcpu->arch.pio.count || vcpu->mmio_needed))
5463 return 1;
5464
5465 if (vcpu->mmio_needed) {
5287f194 5466 vcpu->mmio_needed = 0;
cef4dea0 5467 if (!vcpu->mmio_is_write)
0004c7c2
GN		 5468 memcpy(vcpu->mmio_data + vcpu->mmio_index,
5469 run->mmio.data, 8);
cef4dea0
AK		 5470 vcpu->mmio_index += 8;
5471 if (vcpu->mmio_index < vcpu->mmio_size) {
5472 run->exit_reason = KVM_EXIT_MMIO;
5473 run->mmio.phys_addr = vcpu->mmio_phys_addr + vcpu->mmio_index;
5474 memcpy(run->mmio.data, vcpu->mmio_data + vcpu->mmio_index, 8);
5475 run->mmio.len = min(vcpu->mmio_size - vcpu->mmio_index, 8);
5476 run->mmio.is_write = vcpu->mmio_is_write;
5477 vcpu->mmio_needed = 1;
5478 return 0;
5479 }
5480 if (vcpu->mmio_is_write)
5481 return 1;
5482 vcpu->mmio_read_completed = 1;
5287f194
AK		 5483 }
5484 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5485 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
5486 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
5487 if (r != EMULATE_DONE)
5488 return 0;
5489 return 1;
5490}
5491
b6c7a5dc
HB		 5492int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
5493{
5494 int r;
5495 sigset_t sigsaved;
5496
e5c30142
AK		 5497 if (!tsk_used_math(current) && init_fpu(current))
5498 return -ENOMEM;
5499
ac9f6dc0
AK		 5500 if (vcpu->sigset_active)
5501 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
5502
a4535290 5503 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 5504 kvm_vcpu_block(vcpu);
d7690175 5505 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 5506 r = -EAGAIN;
5507 goto out;
b6c7a5dc
HB		 5508 }
5509
b6c7a5dc 5510 /* re-sync apic's tpr */
eea1cff9
AP		 5511 if (!irqchip_in_kernel(vcpu->kvm)) {
5512 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
5513 r = -EINVAL;
5514 goto out;
5515 }
5516 }
b6c7a5dc 5517
5287f194
AK		 5518 r = complete_mmio(vcpu);
5519 if (r <= 0)
5520 goto out;
5521
851ba692 5522 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 5523
5524out:
f1d86e46 5525 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 5526 if (vcpu->sigset_active)
5527 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
5528
b6c7a5dc
HB		 5529 return r;
5530}
5531
5532int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5533{
7ae441ea
GN		 5534 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
5535 /*
5536 * We are here if userspace calls get_regs() in the middle of
5537 * instruction emulation. Registers state needs to be copied
5538 * back from emulation context to vcpu. Usrapace shouldn't do
5539 * that usually, but some bad designed PV devices (vmware
5540 * backdoor interface) need this to work
5541 */
9dac77fa
AK		 5542 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5543 memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs);
7ae441ea
GN		 5544 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5545 }
5fdbf976
MT		 5546 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
5547 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
5548 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
5549 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
5550 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
5551 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
5552 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
5553 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 5554#ifdef CONFIG_X86_64
5fdbf976
MT		 5555 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
5556 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
5557 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
5558 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
5559 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
5560 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
5561 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
5562 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 5563#endif
5564
5fdbf976 5565 regs->rip = kvm_rip_read(vcpu);
91586a3b 5566 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 5567
b6c7a5dc
HB		 5568 return 0;
5569}
5570
5571int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5572{
7ae441ea
GN		 5573 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
5574 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5575
5fdbf976
MT		 5576 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
5577 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
5578 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
5579 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
5580 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
5581 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
5582 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
5583 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 5584#ifdef CONFIG_X86_64
5fdbf976
MT		 5585 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
5586 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
5587 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
5588 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
5589 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
5590 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
5591 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
5592 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 5593#endif
5594
5fdbf976 5595 kvm_rip_write(vcpu, regs->rip);
91586a3b 5596 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 5597
b4f14abd
JK		 5598 vcpu->arch.exception.pending = false;
5599
3842d135
AK		 5600 kvm_make_request(KVM_REQ_EVENT, vcpu);
5601
b6c7a5dc
HB		 5602 return 0;
5603}
5604
b6c7a5dc
HB		 5605void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
5606{
5607 struct kvm_segment cs;
5608
3e6e0aab 5609 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 5610 *db = cs.db;
5611 *l = cs.l;
5612}
5613EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
5614
5615int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
5616 struct kvm_sregs *sregs)
5617{
89a27f4d 5618 struct desc_ptr dt;
b6c7a5dc 5619
3e6e0aab
GT		 5620 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5621 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5622 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5623 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5624 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5625 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 5626
3e6e0aab
GT		 5627 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5628 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 5629
5630 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 5631 sregs->idt.limit = dt.size;
5632 sregs->idt.base = dt.address;
b6c7a5dc 5633 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 5634 sregs->gdt.limit = dt.size;
5635 sregs->gdt.base = dt.address;
b6c7a5dc 5636
4d4ec087 5637 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 5638 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 5639 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 5640 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 5641 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 5642 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 5643 sregs->apic_base = kvm_get_apic_base(vcpu);
5644
923c61bb 5645 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 5646
36752c9b 5647 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 5648 set_bit(vcpu->arch.interrupt.nr,
5649 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 5650
b6c7a5dc
HB		 5651 return 0;
5652}
5653
62d9f0db
MT		 5654int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
5655 struct kvm_mp_state *mp_state)
5656{
62d9f0db 5657 mp_state->mp_state = vcpu->arch.mp_state;
62d9f0db
MT		 5658 return 0;
5659}
5660
5661int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
5662 struct kvm_mp_state *mp_state)
5663{
62d9f0db 5664 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 5665 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 5666 return 0;
5667}
5668
7f3d35fd
KW		 5669int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
5670 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 5671{
9d74191a 5672 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 5673 int ret;
e01c2426 5674
8ec4722d 5675 init_emulate_ctxt(vcpu);
c697518a 5676
7f3d35fd 5677 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 5678 has_error_code, error_code);
c697518a 5679
c697518a 5680 if (ret)
19d04437 5681 return EMULATE_FAIL;
37817f29 5682
9dac77fa 5683 memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs);
9d74191a
TY		 5684 kvm_rip_write(vcpu, ctxt->eip);
5685 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 5686 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 5687 return EMULATE_DONE;
37817f29
IE		 5688}
5689EXPORT_SYMBOL_GPL(kvm_task_switch);
5690
b6c7a5dc
HB		 5691int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
5692 struct kvm_sregs *sregs)
5693{
5694 int mmu_reset_needed = 0;
63f42e02 5695 int pending_vec, max_bits, idx;
89a27f4d 5696 struct desc_ptr dt;
b6c7a5dc 5697
89a27f4d
GN		 5698 dt.size = sregs->idt.limit;
5699 dt.address = sregs->idt.base;
b6c7a5dc 5700 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 5701 dt.size = sregs->gdt.limit;
5702 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 5703 kvm_x86_ops->set_gdt(vcpu, &dt);
5704
ad312c7c 5705 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 5706 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 5707 vcpu->arch.cr3 = sregs->cr3;
aff48baa 5708 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 5709
2d3ad1f4 5710 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 5711
f6801dff 5712 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 5713 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 5714 kvm_set_apic_base(vcpu, sregs->apic_base);
5715
4d4ec087 5716 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 5717 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 5718 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 5719
fc78f519 5720 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 5721 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3ea3aa8c 5722 if (sregs->cr4 & X86_CR4_OSXSAVE)
00b27a3e 5723 kvm_update_cpuid(vcpu);
63f42e02
XG		 5724
5725 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 5726 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 5727 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 5728 mmu_reset_needed = 1;
5729 }
63f42e02 5730 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 5731
5732 if (mmu_reset_needed)
5733 kvm_mmu_reset_context(vcpu);
5734
923c61bb
GN		 5735 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
5736 pending_vec = find_first_bit(
5737 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
5738 if (pending_vec < max_bits) {
66fd3f7f 5739 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 5740 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 5741 }
5742
3e6e0aab
GT		 5743 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5744 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5745 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5746 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5747 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5748 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 5749
3e6e0aab
GT		 5750 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5751 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 5752
5f0269f5
ME		 5753 update_cr8_intercept(vcpu);
5754
9c3e4aab 5755 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 5756 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 5757 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 5758 !is_protmode(vcpu))
9c3e4aab
MT		 5759 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
5760
3842d135
AK		 5761 kvm_make_request(KVM_REQ_EVENT, vcpu);
5762
b6c7a5dc
HB		 5763 return 0;
5764}
5765
d0bfb940
JK		 5766int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
5767 struct kvm_guest_debug *dbg)
b6c7a5dc 5768{
355be0b9 5769 unsigned long rflags;
ae675ef0 5770 int i, r;
b6c7a5dc 5771
4f926bf2
JK		 5772 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
5773 r = -EBUSY;
5774 if (vcpu->arch.exception.pending)
2122ff5e 5775 goto out;
4f926bf2
JK		 5776 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
5777 kvm_queue_exception(vcpu, DB_VECTOR);
5778 else
5779 kvm_queue_exception(vcpu, BP_VECTOR);
5780 }
5781
91586a3b
JK		 5782 /*
5783 * Read rflags as long as potentially injected trace flags are still
5784 * filtered out.
5785 */
5786 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 5787
5788 vcpu->guest_debug = dbg->control;
5789 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
5790 vcpu->guest_debug = 0;
5791
5792 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 5793 for (i = 0; i < KVM_NR_DB_REGS; ++i)
5794 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
5795 vcpu->arch.switch_db_regs =
5796 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
5797 } else {
5798 for (i = 0; i < KVM_NR_DB_REGS; i++)
5799 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
5800 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
5801 }
5802
f92653ee
JK		 5803 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
5804 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
5805 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 5806
91586a3b
JK		 5807 /*
5808 * Trigger an rflags update that will inject or remove the trace
5809 * flags.
5810 */
5811 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 5812
355be0b9 5813 kvm_x86_ops->set_guest_debug(vcpu, dbg);
b6c7a5dc 5814
4f926bf2 5815 r = 0;
d0bfb940 5816
2122ff5e 5817out:
b6c7a5dc
HB		 5818
5819 return r;
5820}
5821
8b006791
ZX		 5822/*
5823 * Translate a guest virtual address to a guest physical address.
5824 */
5825int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
5826 struct kvm_translation *tr)
5827{
5828 unsigned long vaddr = tr->linear_address;
5829 gpa_t gpa;
f656ce01 5830 int idx;
8b006791 5831
f656ce01 5832 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 5833 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 5834 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 5835 tr->physical_address = gpa;
5836 tr->valid = gpa != UNMAPPED_GVA;
5837 tr->writeable = 1;
5838 tr->usermode = 0;
8b006791
ZX		 5839
5840 return 0;
5841}
5842
d0752060
HB		 5843int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5844{
98918833
SY		 5845 struct i387_fxsave_struct *fxsave =
5846 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 5847
d0752060
HB		 5848 memcpy(fpu->fpr, fxsave->st_space, 128);
5849 fpu->fcw = fxsave->cwd;
5850 fpu->fsw = fxsave->swd;
5851 fpu->ftwx = fxsave->twd;
5852 fpu->last_opcode = fxsave->fop;
5853 fpu->last_ip = fxsave->rip;
5854 fpu->last_dp = fxsave->rdp;
5855 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
5856
d0752060
HB		 5857 return 0;
5858}
5859
5860int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5861{
98918833
SY		 5862 struct i387_fxsave_struct *fxsave =
5863 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 5864
d0752060
HB		 5865 memcpy(fxsave->st_space, fpu->fpr, 128);
5866 fxsave->cwd = fpu->fcw;
5867 fxsave->swd = fpu->fsw;
5868 fxsave->twd = fpu->ftwx;
5869 fxsave->fop = fpu->last_opcode;
5870 fxsave->rip = fpu->last_ip;
5871 fxsave->rdp = fpu->last_dp;
5872 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
5873
d0752060
HB		 5874 return 0;
5875}
5876
10ab25cd 5877int fx_init(struct kvm_vcpu *vcpu)
d0752060 5878{
10ab25cd
JK		 5879 int err;
5880
5881 err = fpu_alloc(&vcpu->arch.guest_fpu);
5882 if (err)
5883 return err;
5884
98918833 5885 fpu_finit(&vcpu->arch.guest_fpu);
d0752060 5886
2acf923e
DC		 5887 /*
5888 * Ensure guest xcr0 is valid for loading
5889 */
5890 vcpu->arch.xcr0 = XSTATE_FP;
5891
ad312c7c 5892 vcpu->arch.cr0 |= X86_CR0_ET;
10ab25cd
JK		 5893
5894 return 0;
d0752060
HB		 5895}
5896EXPORT_SYMBOL_GPL(fx_init);
5897
98918833
SY		 5898static void fx_free(struct kvm_vcpu *vcpu)
5899{
5900 fpu_free(&vcpu->arch.guest_fpu);
5901}
5902
d0752060
HB		 5903void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
5904{
2608d7a1 5905 if (vcpu->guest_fpu_loaded)
d0752060
HB		 5906 return;
5907
2acf923e
DC		 5908 /*
5909 * Restore all possible states in the guest,
5910 * and assume host would use all available bits.
5911 * Guest xcr0 would be loaded later.
5912 */
5913 kvm_put_guest_xcr0(vcpu);
d0752060 5914 vcpu->guest_fpu_loaded = 1;
7cf30855 5915 unlazy_fpu(current);
98918833 5916 fpu_restore_checking(&vcpu->arch.guest_fpu);
0c04851c 5917 trace_kvm_fpu(1);
d0752060 5918}
d0752060
HB		 5919
5920void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
5921{
2acf923e
DC		 5922 kvm_put_guest_xcr0(vcpu);
5923
d0752060
HB		 5924 if (!vcpu->guest_fpu_loaded)
5925 return;
5926
5927 vcpu->guest_fpu_loaded = 0;
98918833 5928 fpu_save_init(&vcpu->arch.guest_fpu);
f096ed85 5929 ++vcpu->stat.fpu_reload;
a8eeb04a 5930 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
0c04851c 5931 trace_kvm_fpu(0);
d0752060 5932}
e9b11c17
ZX		 5933
5934void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
5935{
12f9a48f 5936 kvmclock_reset(vcpu);
7f1ea208 5937
f5f48ee1 5938 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
98918833 5939 fx_free(vcpu);
e9b11c17
ZX		 5940 kvm_x86_ops->vcpu_free(vcpu);
5941}
5942
5943struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
5944 unsigned int id)
5945{
6755bae8
ZA		 5946 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
5947 printk_once(KERN_WARNING
5948 "kvm: SMP vm created on host with unstable TSC; "
5949 "guest TSC will not be reliable\n");
26e5215f
AK		 5950 return kvm_x86_ops->vcpu_create(kvm, id);
5951}
e9b11c17 5952
26e5215f
AK		 5953int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
5954{
5955 int r;
e9b11c17 5956
0bed3b56 5957 vcpu->arch.mtrr_state.have_fixed = 1;
e9b11c17
ZX		 5958 vcpu_load(vcpu);
5959 r = kvm_arch_vcpu_reset(vcpu);
5960 if (r == 0)
5961 r = kvm_mmu_setup(vcpu);
5962 vcpu_put(vcpu);
e9b11c17 5963
26e5215f 5964 return r;
e9b11c17
ZX		 5965}
5966
d40ccc62 5967void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 5968{
344d9588
GN		 5969 vcpu->arch.apf.msr_val = 0;
5970
e9b11c17
ZX		 5971 vcpu_load(vcpu);
5972 kvm_mmu_unload(vcpu);
5973 vcpu_put(vcpu);
5974
98918833 5975 fx_free(vcpu);
e9b11c17
ZX		 5976 kvm_x86_ops->vcpu_free(vcpu);
5977}
5978
5979int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
5980{
7460fb4a
AK		 5981 atomic_set(&vcpu->arch.nmi_queued, 0);
5982 vcpu->arch.nmi_pending = 0;
448fa4a9
JK		 5983 vcpu->arch.nmi_injected = false;
5984
42dbaa5a
JK		 5985 vcpu->arch.switch_db_regs = 0;
5986 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
5987 vcpu->arch.dr6 = DR6_FIXED_1;
5988 vcpu->arch.dr7 = DR7_FIXED_1;
5989
3842d135 5990 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 5991 vcpu->arch.apf.msr_val = 0;
c9aaa895 5992 vcpu->arch.st.msr_val = 0;
3842d135 5993
12f9a48f
GC		 5994 kvmclock_reset(vcpu);
5995
af585b92
GN		 5996 kvm_clear_async_pf_completion_queue(vcpu);
5997 kvm_async_pf_hash_reset(vcpu);
5998 vcpu->arch.apf.halted = false;
3842d135 5999
f5132b01
GN		 6000 kvm_pmu_reset(vcpu);
6001
e9b11c17
ZX		 6002 return kvm_x86_ops->vcpu_reset(vcpu);
6003}
6004
10474ae8 6005int kvm_arch_hardware_enable(void *garbage)
e9b11c17 6006{
ca84d1a2
ZA		 6007 struct kvm *kvm;
6008 struct kvm_vcpu *vcpu;
6009 int i;
0dd6a6ed
ZA		 6010 int ret;
6011 u64 local_tsc;
6012 u64 max_tsc = 0;
6013 bool stable, backwards_tsc = false;
18863bdd
AK		 6014
6015 kvm_shared_msr_cpu_online();
0dd6a6ed
ZA		 6016 ret = kvm_x86_ops->hardware_enable(garbage);
6017 if (ret != 0)
6018 return ret;
6019
6020 local_tsc = native_read_tsc();
6021 stable = !check_tsc_unstable();
6022 list_for_each_entry(kvm, &vm_list, vm_list) {
6023 kvm_for_each_vcpu(i, vcpu, kvm) {
6024 if (!stable && vcpu->cpu == smp_processor_id())
6025 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
6026 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
6027 backwards_tsc = true;
6028 if (vcpu->arch.last_host_tsc > max_tsc)
6029 max_tsc = vcpu->arch.last_host_tsc;
6030 }
6031 }
6032 }
6033
6034 /*
6035 * Sometimes, even reliable TSCs go backwards. This happens on
6036 * platforms that reset TSC during suspend or hibernate actions, but
6037 * maintain synchronization. We must compensate. Fortunately, we can
6038 * detect that condition here, which happens early in CPU bringup,
6039 * before any KVM threads can be running. Unfortunately, we can't
6040 * bring the TSCs fully up to date with real time, as we aren't yet far
6041 * enough into CPU bringup that we know how much real time has actually
6042 * elapsed; our helper function, get_kernel_ns() will be using boot
6043 * variables that haven't been updated yet.
6044 *
6045 * So we simply find the maximum observed TSC above, then record the
6046 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
6047 * the adjustment will be applied. Note that we accumulate
6048 * adjustments, in case multiple suspend cycles happen before some VCPU
6049 * gets a chance to run again. In the event that no KVM threads get a
6050 * chance to run, we will miss the entire elapsed period, as we'll have
6051 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
6052 * loose cycle time. This isn't too big a deal, since the loss will be
6053 * uniform across all VCPUs (not to mention the scenario is extremely
6054 * unlikely). It is possible that a second hibernate recovery happens
6055 * much faster than a first, causing the observed TSC here to be
6056 * smaller; this would require additional padding adjustment, which is
6057 * why we set last_host_tsc to the local tsc observed here.
6058 *
6059 * N.B. - this code below runs only on platforms with reliable TSC,
6060 * as that is the only way backwards_tsc is set above. Also note
6061 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
6062 * have the same delta_cyc adjustment applied if backwards_tsc
6063 * is detected. Note further, this adjustment is only done once,
6064 * as we reset last_host_tsc on all VCPUs to stop this from being
6065 * called multiple times (one for each physical CPU bringup).
6066 *
6067 * Platforms with unnreliable TSCs don't have to deal with this, they
6068 * will be compensated by the logic in vcpu_load, which sets the TSC to
6069 * catchup mode. This will catchup all VCPUs to real time, but cannot
6070 * guarantee that they stay in perfect synchronization.
6071 */
6072 if (backwards_tsc) {
6073 u64 delta_cyc = max_tsc - local_tsc;
6074 list_for_each_entry(kvm, &vm_list, vm_list) {
6075 kvm_for_each_vcpu(i, vcpu, kvm) {
6076 vcpu->arch.tsc_offset_adjustment += delta_cyc;
6077 vcpu->arch.last_host_tsc = local_tsc;
6078 }
6079
6080 /*
6081 * We have to disable TSC offset matching.. if you were
6082 * booting a VM while issuing an S4 host suspend....
6083 * you may have some problem. Solving this issue is
6084 * left as an exercise to the reader.
6085 */
6086 kvm->arch.last_tsc_nsec = 0;
6087 kvm->arch.last_tsc_write = 0;
6088 }
6089
6090 }
6091 return 0;
e9b11c17
ZX		 6092}
6093
6094void kvm_arch_hardware_disable(void *garbage)
6095{
6096 kvm_x86_ops->hardware_disable(garbage);
3548bab5 6097 drop_user_return_notifiers(garbage);
e9b11c17
ZX		 6098}
6099
6100int kvm_arch_hardware_setup(void)
6101{
6102 return kvm_x86_ops->hardware_setup();
6103}
6104
6105void kvm_arch_hardware_unsetup(void)
6106{
6107 kvm_x86_ops->hardware_unsetup();
6108}
6109
6110void kvm_arch_check_processor_compat(void *rtn)
6111{
6112 kvm_x86_ops->check_processor_compatibility(rtn);
6113}
6114
3e515705
AK		 6115bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
6116{
6117 return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL);
6118}
6119
e9b11c17
ZX		 6120int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
6121{
6122 struct page *page;
6123 struct kvm *kvm;
6124 int r;
6125
6126 BUG_ON(vcpu->kvm == NULL);
6127 kvm = vcpu->kvm;
6128
9aabc88f 6129 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
c5af89b6 6130 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 6131 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 6132 else
a4535290 6133 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 6134
6135 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
6136 if (!page) {
6137 r = -ENOMEM;
6138 goto fail;
6139 }
ad312c7c 6140 vcpu->arch.pio_data = page_address(page);
e9b11c17 6141
cc578287 6142 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 6143
e9b11c17
ZX		 6144 r = kvm_mmu_create(vcpu);
6145 if (r < 0)
6146 goto fail_free_pio_data;
6147
6148 if (irqchip_in_kernel(kvm)) {
6149 r = kvm_create_lapic(vcpu);
6150 if (r < 0)
6151 goto fail_mmu_destroy;
6152 }
6153
890ca9ae
HY		 6154 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
6155 GFP_KERNEL);
6156 if (!vcpu->arch.mce_banks) {
6157 r = -ENOMEM;
443c39bc 6158 goto fail_free_lapic;
890ca9ae
HY		 6159 }
6160 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
6161
f5f48ee1
SY		 6162 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL))
6163 goto fail_free_mce_banks;
6164
af585b92 6165 kvm_async_pf_hash_reset(vcpu);
f5132b01 6166 kvm_pmu_init(vcpu);
af585b92 6167
e9b11c17 6168 return 0;
f5f48ee1
SY		 6169fail_free_mce_banks:
6170 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 6171fail_free_lapic:
6172 kvm_free_lapic(vcpu);
e9b11c17
ZX		 6173fail_mmu_destroy:
6174 kvm_mmu_destroy(vcpu);
6175fail_free_pio_data:
ad312c7c 6176 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 6177fail:
6178 return r;
6179}
6180
6181void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
6182{
f656ce01
MT		 6183 int idx;
6184
f5132b01 6185 kvm_pmu_destroy(vcpu);
36cb93fd 6186 kfree(vcpu->arch.mce_banks);
e9b11c17 6187 kvm_free_lapic(vcpu);
f656ce01 6188 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 6189 kvm_mmu_destroy(vcpu);
f656ce01 6190 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 6191 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17 6192}
d19a9cd2 6193
e08b9637 6194int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 6195{
e08b9637
CO		 6196 if (type)
6197 return -EINVAL;
6198
f05e70ac 6199 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4d5c5d0f 6200 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2 6201
5550af4d
SY		 6202 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
6203 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
6204
038f8c11 6205 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
53f658b3 6206
d89f5eff 6207 return 0;
d19a9cd2
ZX		 6208}
6209
6210static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
6211{
6212 vcpu_load(vcpu);
6213 kvm_mmu_unload(vcpu);
6214 vcpu_put(vcpu);
6215}
6216
6217static void kvm_free_vcpus(struct kvm *kvm)
6218{
6219 unsigned int i;
988a2cae 6220 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 6221
6222 /*
6223 * Unpin any mmu pages first.
6224 */
af585b92
GN		 6225 kvm_for_each_vcpu(i, vcpu, kvm) {
6226 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 6227 kvm_unload_vcpu_mmu(vcpu);
af585b92 6228 }
988a2cae
GN		 6229 kvm_for_each_vcpu(i, vcpu, kvm)
6230 kvm_arch_vcpu_free(vcpu);
6231
6232 mutex_lock(&kvm->lock);
6233 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
6234 kvm->vcpus[i] = NULL;
d19a9cd2 6235
988a2cae
GN		 6236 atomic_set(&kvm->online_vcpus, 0);
6237 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 6238}
6239
ad8ba2cd
SY		 6240void kvm_arch_sync_events(struct kvm *kvm)
6241{
ba4cef31 6242 kvm_free_all_assigned_devices(kvm);
aea924f6 6243 kvm_free_pit(kvm);
ad8ba2cd
SY		 6244}
6245
d19a9cd2
ZX		 6246void kvm_arch_destroy_vm(struct kvm *kvm)
6247{
6eb55818 6248 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 6249 kfree(kvm->arch.vpic);
6250 kfree(kvm->arch.vioapic);
d19a9cd2 6251 kvm_free_vcpus(kvm);
3d45830c
AK		 6252 if (kvm->arch.apic_access_page)
6253 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 6254 if (kvm->arch.ept_identity_pagetable)
6255 put_page(kvm->arch.ept_identity_pagetable);
d19a9cd2 6256}
0de10343 6257
db3fe4eb
TY		 6258void kvm_arch_free_memslot(struct kvm_memory_slot *free,
6259 struct kvm_memory_slot *dont)
6260{
6261 int i;
6262
6263 for (i = 0; i < KVM_NR_PAGE_SIZES - 1; ++i) {
6264 if (!dont || free->arch.lpage_info[i] != dont->arch.lpage_info[i]) {
6265 vfree(free->arch.lpage_info[i]);
6266 free->arch.lpage_info[i] = NULL;
6267 }
6268 }
6269}
6270
6271int kvm_arch_create_memslot(struct kvm_memory_slot *slot, unsigned long npages)
6272{
6273 int i;
6274
6275 for (i = 0; i < KVM_NR_PAGE_SIZES - 1; ++i) {
6276 unsigned long ugfn;
6277 int lpages;
6278 int level = i + 2;
6279
6280 lpages = gfn_to_index(slot->base_gfn + npages - 1,
6281 slot->base_gfn, level) + 1;
6282
6283 slot->arch.lpage_info[i] =
6284 vzalloc(lpages * sizeof(*slot->arch.lpage_info[i]));
6285 if (!slot->arch.lpage_info[i])
6286 goto out_free;
6287
6288 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
6289 slot->arch.lpage_info[i][0].write_count = 1;
6290 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
6291 slot->arch.lpage_info[i][lpages - 1].write_count = 1;
6292 ugfn = slot->userspace_addr >> PAGE_SHIFT;
6293 /*
6294 * If the gfn and userspace address are not aligned wrt each
6295 * other, or if explicitly asked to, disable large page
6296 * support for this slot
6297 */
6298 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
6299 !kvm_largepages_enabled()) {
6300 unsigned long j;
6301
6302 for (j = 0; j < lpages; ++j)
6303 slot->arch.lpage_info[i][j].write_count = 1;
6304 }
6305 }
6306
6307 return 0;
6308
6309out_free:
6310 for (i = 0; i < KVM_NR_PAGE_SIZES - 1; ++i) {
6311 vfree(slot->arch.lpage_info[i]);
6312 slot->arch.lpage_info[i] = NULL;
6313 }
6314 return -ENOMEM;
6315}
6316
f7784b8e
MT		 6317int kvm_arch_prepare_memory_region(struct kvm *kvm,
6318 struct kvm_memory_slot *memslot,
0de10343 6319 struct kvm_memory_slot old,
f7784b8e 6320 struct kvm_userspace_memory_region *mem,
0de10343
ZX		 6321 int user_alloc)
6322{
f7784b8e 6323 int npages = memslot->npages;
7ac77099
AK		 6324 int map_flags = MAP_PRIVATE | MAP_ANONYMOUS;
6325
6326 /* Prevent internal slot pages from being moved by fork()/COW. */
6327 if (memslot->id >= KVM_MEMORY_SLOTS)
6328 map_flags = MAP_SHARED | MAP_ANONYMOUS;
0de10343
ZX		 6329
6330 /*To keep backward compatibility with older userspace,
6331 *x86 needs to hanlde !user_alloc case.
6332 */
6333 if (!user_alloc) {
6334 if (npages && !old.rmap) {
604b38ac
AA		 6335 unsigned long userspace_addr;
6336
72dc67a6 6337 down_write(&current->mm->mmap_sem);
604b38ac
AA		 6338 userspace_addr = do_mmap(NULL, 0,
6339 npages * PAGE_SIZE,
6340 PROT_READ | PROT_WRITE,
7ac77099 6341 map_flags,
604b38ac 6342 0);
72dc67a6 6343 up_write(&current->mm->mmap_sem);
0de10343 6344
604b38ac
AA		 6345 if (IS_ERR((void *)userspace_addr))
6346 return PTR_ERR((void *)userspace_addr);
6347
604b38ac 6348 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 6349 }
6350 }
6351
f7784b8e
MT		 6352
6353 return 0;
6354}
6355
6356void kvm_arch_commit_memory_region(struct kvm *kvm,
6357 struct kvm_userspace_memory_region *mem,
6358 struct kvm_memory_slot old,
6359 int user_alloc)
6360{
6361
48c0e4e9 6362 int nr_mmu_pages = 0, npages = mem->memory_size >> PAGE_SHIFT;
f7784b8e
MT		 6363
6364 if (!user_alloc && !old.user_alloc && old.rmap && !npages) {
6365 int ret;
6366
6367 down_write(&current->mm->mmap_sem);
6368 ret = do_munmap(current->mm, old.userspace_addr,
6369 old.npages * PAGE_SIZE);
6370 up_write(&current->mm->mmap_sem);
6371 if (ret < 0)
6372 printk(KERN_WARNING
6373 "kvm_vm_ioctl_set_memory_region: "
6374 "failed to munmap memory\n");
6375 }
6376
48c0e4e9
XG		 6377 if (!kvm->arch.n_requested_mmu_pages)
6378 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
6379
7c8a83b7 6380 spin_lock(&kvm->mmu_lock);
48c0e4e9 6381 if (nr_mmu_pages)
0de10343 6382 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
0de10343 6383 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
7c8a83b7 6384 spin_unlock(&kvm->mmu_lock);
0de10343 6385}
1d737c8a 6386
34d4cb8f
MT		 6387void kvm_arch_flush_shadow(struct kvm *kvm)
6388{
6389 kvm_mmu_zap_all(kvm);
8986ecc0 6390 kvm_reload_remote_mmus(kvm);
34d4cb8f
MT		 6391}
6392
1d737c8a
ZX		 6393int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
6394{
af585b92
GN		 6395 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6396 !vcpu->arch.apf.halted)
6397 || !list_empty_careful(&vcpu->async_pf.done)
a1b37100 6398 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
7460fb4a 6399 || atomic_read(&vcpu->arch.nmi_queued) ||
a1b37100
GN		 6400 (kvm_arch_interrupt_allowed(vcpu) &&
6401 kvm_cpu_has_interrupt(vcpu));
1d737c8a 6402}
5736199a 6403
5736199a
ZX		 6404void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
6405{
32f88400
MT		 6406 int me;
6407 int cpu = vcpu->cpu;
5736199a
ZX		 6408
6409 if (waitqueue_active(&vcpu->wq)) {
6410 wake_up_interruptible(&vcpu->wq);
6411 ++vcpu->stat.halt_wakeup;
6412 }
32f88400
MT		 6413
6414 me = get_cpu();
6415 if (cpu != me && (unsigned)cpu < nr_cpu_ids && cpu_online(cpu))
6b7e2d09 6416 if (kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE)
32f88400 6417 smp_send_reschedule(cpu);
e9571ed5 6418 put_cpu();
5736199a 6419}
78646121
GN		 6420
6421int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
6422{
6423 return kvm_x86_ops->interrupt_allowed(vcpu);
6424}
229456fc 6425
f92653ee
JK		 6426bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
6427{
6428 unsigned long current_rip = kvm_rip_read(vcpu) +
6429 get_segment_base(vcpu, VCPU_SREG_CS);
6430
6431 return current_rip == linear_rip;
6432}
6433EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
6434
94fe45da
JK		 6435unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
6436{
6437 unsigned long rflags;
6438
6439 rflags = kvm_x86_ops->get_rflags(vcpu);
6440 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 6441 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 6442 return rflags;
6443}
6444EXPORT_SYMBOL_GPL(kvm_get_rflags);
6445
6446void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
6447{
6448 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 6449 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 6450 rflags |= X86_EFLAGS_TF;
94fe45da 6451 kvm_x86_ops->set_rflags(vcpu, rflags);
3842d135 6452 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 6453}
6454EXPORT_SYMBOL_GPL(kvm_set_rflags);
6455
56028d08
GN		 6456void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
6457{
6458 int r;
6459
fb67e14f 6460 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
c4806acd 6461 is_error_page(work->page))
56028d08
GN		 6462 return;
6463
6464 r = kvm_mmu_reload(vcpu);
6465 if (unlikely(r))
6466 return;
6467
fb67e14f
XG		 6468 if (!vcpu->arch.mmu.direct_map &&
6469 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
6470 return;
6471
56028d08
GN		 6472 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
6473}
6474
af585b92
GN		 6475static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
6476{
6477 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
6478}
6479
6480static inline u32 kvm_async_pf_next_probe(u32 key)
6481{
6482 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
6483}
6484
6485static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6486{
6487 u32 key = kvm_async_pf_hash_fn(gfn);
6488
6489 while (vcpu->arch.apf.gfns[key] != ~0)
6490 key = kvm_async_pf_next_probe(key);
6491
6492 vcpu->arch.apf.gfns[key] = gfn;
6493}
6494
6495static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
6496{
6497 int i;
6498 u32 key = kvm_async_pf_hash_fn(gfn);
6499
6500 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 6501 (vcpu->arch.apf.gfns[key] != gfn &&
6502 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 6503 key = kvm_async_pf_next_probe(key);
6504
6505 return key;
6506}
6507
6508bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6509{
6510 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
6511}
6512
6513static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6514{
6515 u32 i, j, k;
6516
6517 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
6518 while (true) {
6519 vcpu->arch.apf.gfns[i] = ~0;
6520 do {
6521 j = kvm_async_pf_next_probe(j);
6522 if (vcpu->arch.apf.gfns[j] == ~0)
6523 return;
6524 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
6525 /*
6526 * k lies cyclically in ]i,j]
6527 * | i.k.j |
6528 * |....j i.k.| or |.k..j i...|
6529 */
6530 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
6531 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
6532 i = j;
6533 }
6534}
6535
7c90705b
GN		 6536static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
6537{
6538
6539 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
6540 sizeof(val));
6541}
6542
af585b92
GN		 6543void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
6544 struct kvm_async_pf *work)
6545{
6389ee94
AK		 6546 struct x86_exception fault;
6547
7c90705b 6548 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 6549 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 6550
6551 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 6552 (vcpu->arch.apf.send_user_only &&
6553 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 6554 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
6555 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 6556 fault.vector = PF_VECTOR;
6557 fault.error_code_valid = true;
6558 fault.error_code = 0;
6559 fault.nested_page_fault = false;
6560 fault.address = work->arch.token;
6561 kvm_inject_page_fault(vcpu, &fault);
7c90705b 6562 }
af585b92
GN		 6563}
6564
6565void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
6566 struct kvm_async_pf *work)
6567{
6389ee94
AK		 6568 struct x86_exception fault;
6569
7c90705b
GN		 6570 trace_kvm_async_pf_ready(work->arch.token, work->gva);
6571 if (is_error_page(work->page))
6572 work->arch.token = ~0; /* broadcast wakeup */
6573 else
6574 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
6575
6576 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
6577 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 6578 fault.vector = PF_VECTOR;
6579 fault.error_code_valid = true;
6580 fault.error_code = 0;
6581 fault.nested_page_fault = false;
6582 fault.address = work->arch.token;
6583 kvm_inject_page_fault(vcpu, &fault);
7c90705b 6584 }
e6d53e3b 6585 vcpu->arch.apf.halted = false;
7c90705b
GN		 6586}
6587
6588bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
6589{
6590 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
6591 return true;
6592 else
6593 return !kvm_event_needs_reinjection(vcpu) &&
6594 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 6595}
6596
229456fc
MT		 6597EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
6598EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
6599EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
6600EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
6601EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 6602EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 6603EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 6604EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 6605EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 6606EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 6607EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 6608EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
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