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296af7c9 BS |
1 | /* |
2 | * QEMU System Emulator | |
3 | * | |
4 | * Copyright (c) 2003-2008 Fabrice Bellard | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
24 | ||
25 | /* Needed early for CONFIG_BSD etc. */ | |
26 | #include "config-host.h" | |
27 | ||
28 | #include "monitor.h" | |
29 | #include "sysemu.h" | |
30 | #include "gdbstub.h" | |
31 | #include "dma.h" | |
32 | #include "kvm.h" | |
de0b36b6 | 33 | #include "qmp-commands.h" |
296af7c9 | 34 | |
96284e89 | 35 | #include "qemu-thread.h" |
296af7c9 | 36 | #include "cpus.h" |
8156be56 | 37 | #include "qtest.h" |
44a9b356 | 38 | #include "main-loop.h" |
ee785fed | 39 | #include "bitmap.h" |
0ff0fc19 JK |
40 | |
41 | #ifndef _WIN32 | |
a8486bc9 | 42 | #include "compatfd.h" |
0ff0fc19 | 43 | #endif |
296af7c9 | 44 | |
6d9cb73c JK |
45 | #ifdef CONFIG_LINUX |
46 | ||
47 | #include <sys/prctl.h> | |
48 | ||
c0532a76 MT |
49 | #ifndef PR_MCE_KILL |
50 | #define PR_MCE_KILL 33 | |
51 | #endif | |
52 | ||
6d9cb73c JK |
53 | #ifndef PR_MCE_KILL_SET |
54 | #define PR_MCE_KILL_SET 1 | |
55 | #endif | |
56 | ||
57 | #ifndef PR_MCE_KILL_EARLY | |
58 | #define PR_MCE_KILL_EARLY 1 | |
59 | #endif | |
60 | ||
61 | #endif /* CONFIG_LINUX */ | |
62 | ||
9349b4f9 | 63 | static CPUArchState *next_cpu; |
296af7c9 | 64 | |
ac873f1e PM |
65 | static bool cpu_thread_is_idle(CPUArchState *env) |
66 | { | |
4fdeee7c AF |
67 | CPUState *cpu = ENV_GET_CPU(env); |
68 | ||
69 | if (cpu->stop || env->queued_work_first) { | |
ac873f1e PM |
70 | return false; |
71 | } | |
72 | if (env->stopped || !runstate_is_running()) { | |
73 | return true; | |
74 | } | |
7ae26bd4 PM |
75 | if (!env->halted || qemu_cpu_has_work(env) || |
76 | kvm_async_interrupts_enabled()) { | |
ac873f1e PM |
77 | return false; |
78 | } | |
79 | return true; | |
80 | } | |
81 | ||
82 | static bool all_cpu_threads_idle(void) | |
83 | { | |
84 | CPUArchState *env; | |
85 | ||
86 | for (env = first_cpu; env != NULL; env = env->next_cpu) { | |
87 | if (!cpu_thread_is_idle(env)) { | |
88 | return false; | |
89 | } | |
90 | } | |
91 | return true; | |
92 | } | |
93 | ||
946fb27c PB |
94 | /***********************************************************/ |
95 | /* guest cycle counter */ | |
96 | ||
97 | /* Conversion factor from emulated instructions to virtual clock ticks. */ | |
98 | static int icount_time_shift; | |
99 | /* Arbitrarily pick 1MIPS as the minimum allowable speed. */ | |
100 | #define MAX_ICOUNT_SHIFT 10 | |
101 | /* Compensate for varying guest execution speed. */ | |
102 | static int64_t qemu_icount_bias; | |
103 | static QEMUTimer *icount_rt_timer; | |
104 | static QEMUTimer *icount_vm_timer; | |
105 | static QEMUTimer *icount_warp_timer; | |
106 | static int64_t vm_clock_warp_start; | |
107 | static int64_t qemu_icount; | |
108 | ||
109 | typedef struct TimersState { | |
110 | int64_t cpu_ticks_prev; | |
111 | int64_t cpu_ticks_offset; | |
112 | int64_t cpu_clock_offset; | |
113 | int32_t cpu_ticks_enabled; | |
114 | int64_t dummy; | |
115 | } TimersState; | |
116 | ||
117 | TimersState timers_state; | |
118 | ||
119 | /* Return the virtual CPU time, based on the instruction counter. */ | |
120 | int64_t cpu_get_icount(void) | |
121 | { | |
122 | int64_t icount; | |
9349b4f9 | 123 | CPUArchState *env = cpu_single_env; |
946fb27c PB |
124 | |
125 | icount = qemu_icount; | |
126 | if (env) { | |
127 | if (!can_do_io(env)) { | |
128 | fprintf(stderr, "Bad clock read\n"); | |
129 | } | |
130 | icount -= (env->icount_decr.u16.low + env->icount_extra); | |
131 | } | |
132 | return qemu_icount_bias + (icount << icount_time_shift); | |
133 | } | |
134 | ||
135 | /* return the host CPU cycle counter and handle stop/restart */ | |
136 | int64_t cpu_get_ticks(void) | |
137 | { | |
138 | if (use_icount) { | |
139 | return cpu_get_icount(); | |
140 | } | |
141 | if (!timers_state.cpu_ticks_enabled) { | |
142 | return timers_state.cpu_ticks_offset; | |
143 | } else { | |
144 | int64_t ticks; | |
145 | ticks = cpu_get_real_ticks(); | |
146 | if (timers_state.cpu_ticks_prev > ticks) { | |
147 | /* Note: non increasing ticks may happen if the host uses | |
148 | software suspend */ | |
149 | timers_state.cpu_ticks_offset += timers_state.cpu_ticks_prev - ticks; | |
150 | } | |
151 | timers_state.cpu_ticks_prev = ticks; | |
152 | return ticks + timers_state.cpu_ticks_offset; | |
153 | } | |
154 | } | |
155 | ||
156 | /* return the host CPU monotonic timer and handle stop/restart */ | |
157 | int64_t cpu_get_clock(void) | |
158 | { | |
159 | int64_t ti; | |
160 | if (!timers_state.cpu_ticks_enabled) { | |
161 | return timers_state.cpu_clock_offset; | |
162 | } else { | |
163 | ti = get_clock(); | |
164 | return ti + timers_state.cpu_clock_offset; | |
165 | } | |
166 | } | |
167 | ||
168 | /* enable cpu_get_ticks() */ | |
169 | void cpu_enable_ticks(void) | |
170 | { | |
171 | if (!timers_state.cpu_ticks_enabled) { | |
172 | timers_state.cpu_ticks_offset -= cpu_get_real_ticks(); | |
173 | timers_state.cpu_clock_offset -= get_clock(); | |
174 | timers_state.cpu_ticks_enabled = 1; | |
175 | } | |
176 | } | |
177 | ||
178 | /* disable cpu_get_ticks() : the clock is stopped. You must not call | |
179 | cpu_get_ticks() after that. */ | |
180 | void cpu_disable_ticks(void) | |
181 | { | |
182 | if (timers_state.cpu_ticks_enabled) { | |
183 | timers_state.cpu_ticks_offset = cpu_get_ticks(); | |
184 | timers_state.cpu_clock_offset = cpu_get_clock(); | |
185 | timers_state.cpu_ticks_enabled = 0; | |
186 | } | |
187 | } | |
188 | ||
189 | /* Correlation between real and virtual time is always going to be | |
190 | fairly approximate, so ignore small variation. | |
191 | When the guest is idle real and virtual time will be aligned in | |
192 | the IO wait loop. */ | |
193 | #define ICOUNT_WOBBLE (get_ticks_per_sec() / 10) | |
194 | ||
195 | static void icount_adjust(void) | |
196 | { | |
197 | int64_t cur_time; | |
198 | int64_t cur_icount; | |
199 | int64_t delta; | |
200 | static int64_t last_delta; | |
201 | /* If the VM is not running, then do nothing. */ | |
202 | if (!runstate_is_running()) { | |
203 | return; | |
204 | } | |
205 | cur_time = cpu_get_clock(); | |
206 | cur_icount = qemu_get_clock_ns(vm_clock); | |
207 | delta = cur_icount - cur_time; | |
208 | /* FIXME: This is a very crude algorithm, somewhat prone to oscillation. */ | |
209 | if (delta > 0 | |
210 | && last_delta + ICOUNT_WOBBLE < delta * 2 | |
211 | && icount_time_shift > 0) { | |
212 | /* The guest is getting too far ahead. Slow time down. */ | |
213 | icount_time_shift--; | |
214 | } | |
215 | if (delta < 0 | |
216 | && last_delta - ICOUNT_WOBBLE > delta * 2 | |
217 | && icount_time_shift < MAX_ICOUNT_SHIFT) { | |
218 | /* The guest is getting too far behind. Speed time up. */ | |
219 | icount_time_shift++; | |
220 | } | |
221 | last_delta = delta; | |
222 | qemu_icount_bias = cur_icount - (qemu_icount << icount_time_shift); | |
223 | } | |
224 | ||
225 | static void icount_adjust_rt(void *opaque) | |
226 | { | |
227 | qemu_mod_timer(icount_rt_timer, | |
228 | qemu_get_clock_ms(rt_clock) + 1000); | |
229 | icount_adjust(); | |
230 | } | |
231 | ||
232 | static void icount_adjust_vm(void *opaque) | |
233 | { | |
234 | qemu_mod_timer(icount_vm_timer, | |
235 | qemu_get_clock_ns(vm_clock) + get_ticks_per_sec() / 10); | |
236 | icount_adjust(); | |
237 | } | |
238 | ||
239 | static int64_t qemu_icount_round(int64_t count) | |
240 | { | |
241 | return (count + (1 << icount_time_shift) - 1) >> icount_time_shift; | |
242 | } | |
243 | ||
244 | static void icount_warp_rt(void *opaque) | |
245 | { | |
246 | if (vm_clock_warp_start == -1) { | |
247 | return; | |
248 | } | |
249 | ||
250 | if (runstate_is_running()) { | |
251 | int64_t clock = qemu_get_clock_ns(rt_clock); | |
252 | int64_t warp_delta = clock - vm_clock_warp_start; | |
253 | if (use_icount == 1) { | |
254 | qemu_icount_bias += warp_delta; | |
255 | } else { | |
256 | /* | |
257 | * In adaptive mode, do not let the vm_clock run too | |
258 | * far ahead of real time. | |
259 | */ | |
260 | int64_t cur_time = cpu_get_clock(); | |
261 | int64_t cur_icount = qemu_get_clock_ns(vm_clock); | |
262 | int64_t delta = cur_time - cur_icount; | |
263 | qemu_icount_bias += MIN(warp_delta, delta); | |
264 | } | |
265 | if (qemu_clock_expired(vm_clock)) { | |
266 | qemu_notify_event(); | |
267 | } | |
268 | } | |
269 | vm_clock_warp_start = -1; | |
270 | } | |
271 | ||
8156be56 PB |
272 | void qtest_clock_warp(int64_t dest) |
273 | { | |
274 | int64_t clock = qemu_get_clock_ns(vm_clock); | |
275 | assert(qtest_enabled()); | |
276 | while (clock < dest) { | |
277 | int64_t deadline = qemu_clock_deadline(vm_clock); | |
278 | int64_t warp = MIN(dest - clock, deadline); | |
279 | qemu_icount_bias += warp; | |
280 | qemu_run_timers(vm_clock); | |
281 | clock = qemu_get_clock_ns(vm_clock); | |
282 | } | |
283 | qemu_notify_event(); | |
284 | } | |
285 | ||
946fb27c PB |
286 | void qemu_clock_warp(QEMUClock *clock) |
287 | { | |
288 | int64_t deadline; | |
289 | ||
290 | /* | |
291 | * There are too many global variables to make the "warp" behavior | |
292 | * applicable to other clocks. But a clock argument removes the | |
293 | * need for if statements all over the place. | |
294 | */ | |
295 | if (clock != vm_clock || !use_icount) { | |
296 | return; | |
297 | } | |
298 | ||
299 | /* | |
300 | * If the CPUs have been sleeping, advance the vm_clock timer now. This | |
301 | * ensures that the deadline for the timer is computed correctly below. | |
302 | * This also makes sure that the insn counter is synchronized before the | |
303 | * CPU starts running, in case the CPU is woken by an event other than | |
304 | * the earliest vm_clock timer. | |
305 | */ | |
306 | icount_warp_rt(NULL); | |
307 | if (!all_cpu_threads_idle() || !qemu_clock_has_timers(vm_clock)) { | |
308 | qemu_del_timer(icount_warp_timer); | |
309 | return; | |
310 | } | |
311 | ||
8156be56 PB |
312 | if (qtest_enabled()) { |
313 | /* When testing, qtest commands advance icount. */ | |
314 | return; | |
315 | } | |
316 | ||
946fb27c PB |
317 | vm_clock_warp_start = qemu_get_clock_ns(rt_clock); |
318 | deadline = qemu_clock_deadline(vm_clock); | |
319 | if (deadline > 0) { | |
320 | /* | |
321 | * Ensure the vm_clock proceeds even when the virtual CPU goes to | |
322 | * sleep. Otherwise, the CPU might be waiting for a future timer | |
323 | * interrupt to wake it up, but the interrupt never comes because | |
324 | * the vCPU isn't running any insns and thus doesn't advance the | |
325 | * vm_clock. | |
326 | * | |
327 | * An extreme solution for this problem would be to never let VCPUs | |
328 | * sleep in icount mode if there is a pending vm_clock timer; rather | |
329 | * time could just advance to the next vm_clock event. Instead, we | |
330 | * do stop VCPUs and only advance vm_clock after some "real" time, | |
331 | * (related to the time left until the next event) has passed. This | |
332 | * rt_clock timer will do this. This avoids that the warps are too | |
333 | * visible externally---for example, you will not be sending network | |
07f35073 | 334 | * packets continuously instead of every 100ms. |
946fb27c PB |
335 | */ |
336 | qemu_mod_timer(icount_warp_timer, vm_clock_warp_start + deadline); | |
337 | } else { | |
338 | qemu_notify_event(); | |
339 | } | |
340 | } | |
341 | ||
342 | static const VMStateDescription vmstate_timers = { | |
343 | .name = "timer", | |
344 | .version_id = 2, | |
345 | .minimum_version_id = 1, | |
346 | .minimum_version_id_old = 1, | |
347 | .fields = (VMStateField[]) { | |
348 | VMSTATE_INT64(cpu_ticks_offset, TimersState), | |
349 | VMSTATE_INT64(dummy, TimersState), | |
350 | VMSTATE_INT64_V(cpu_clock_offset, TimersState, 2), | |
351 | VMSTATE_END_OF_LIST() | |
352 | } | |
353 | }; | |
354 | ||
355 | void configure_icount(const char *option) | |
356 | { | |
357 | vmstate_register(NULL, 0, &vmstate_timers, &timers_state); | |
358 | if (!option) { | |
359 | return; | |
360 | } | |
361 | ||
362 | icount_warp_timer = qemu_new_timer_ns(rt_clock, icount_warp_rt, NULL); | |
363 | if (strcmp(option, "auto") != 0) { | |
364 | icount_time_shift = strtol(option, NULL, 0); | |
365 | use_icount = 1; | |
366 | return; | |
367 | } | |
368 | ||
369 | use_icount = 2; | |
370 | ||
371 | /* 125MIPS seems a reasonable initial guess at the guest speed. | |
372 | It will be corrected fairly quickly anyway. */ | |
373 | icount_time_shift = 3; | |
374 | ||
375 | /* Have both realtime and virtual time triggers for speed adjustment. | |
376 | The realtime trigger catches emulated time passing too slowly, | |
377 | the virtual time trigger catches emulated time passing too fast. | |
378 | Realtime triggers occur even when idle, so use them less frequently | |
379 | than VM triggers. */ | |
380 | icount_rt_timer = qemu_new_timer_ms(rt_clock, icount_adjust_rt, NULL); | |
381 | qemu_mod_timer(icount_rt_timer, | |
382 | qemu_get_clock_ms(rt_clock) + 1000); | |
383 | icount_vm_timer = qemu_new_timer_ns(vm_clock, icount_adjust_vm, NULL); | |
384 | qemu_mod_timer(icount_vm_timer, | |
385 | qemu_get_clock_ns(vm_clock) + get_ticks_per_sec() / 10); | |
386 | } | |
387 | ||
296af7c9 BS |
388 | /***********************************************************/ |
389 | void hw_error(const char *fmt, ...) | |
390 | { | |
391 | va_list ap; | |
9349b4f9 | 392 | CPUArchState *env; |
296af7c9 BS |
393 | |
394 | va_start(ap, fmt); | |
395 | fprintf(stderr, "qemu: hardware error: "); | |
396 | vfprintf(stderr, fmt, ap); | |
397 | fprintf(stderr, "\n"); | |
398 | for(env = first_cpu; env != NULL; env = env->next_cpu) { | |
399 | fprintf(stderr, "CPU #%d:\n", env->cpu_index); | |
6fd2a026 | 400 | cpu_dump_state(env, stderr, fprintf, CPU_DUMP_FPU); |
296af7c9 BS |
401 | } |
402 | va_end(ap); | |
403 | abort(); | |
404 | } | |
405 | ||
406 | void cpu_synchronize_all_states(void) | |
407 | { | |
9349b4f9 | 408 | CPUArchState *cpu; |
296af7c9 BS |
409 | |
410 | for (cpu = first_cpu; cpu; cpu = cpu->next_cpu) { | |
411 | cpu_synchronize_state(cpu); | |
412 | } | |
413 | } | |
414 | ||
415 | void cpu_synchronize_all_post_reset(void) | |
416 | { | |
9349b4f9 | 417 | CPUArchState *cpu; |
296af7c9 BS |
418 | |
419 | for (cpu = first_cpu; cpu; cpu = cpu->next_cpu) { | |
420 | cpu_synchronize_post_reset(cpu); | |
421 | } | |
422 | } | |
423 | ||
424 | void cpu_synchronize_all_post_init(void) | |
425 | { | |
9349b4f9 | 426 | CPUArchState *cpu; |
296af7c9 BS |
427 | |
428 | for (cpu = first_cpu; cpu; cpu = cpu->next_cpu) { | |
429 | cpu_synchronize_post_init(cpu); | |
430 | } | |
431 | } | |
432 | ||
9349b4f9 | 433 | int cpu_is_stopped(CPUArchState *env) |
3ae9501c | 434 | { |
1354869c | 435 | return !runstate_is_running() || env->stopped; |
3ae9501c MT |
436 | } |
437 | ||
1dfb4dd9 | 438 | static void do_vm_stop(RunState state) |
296af7c9 | 439 | { |
1354869c | 440 | if (runstate_is_running()) { |
296af7c9 | 441 | cpu_disable_ticks(); |
296af7c9 | 442 | pause_all_vcpus(); |
f5bbfba1 | 443 | runstate_set(state); |
1dfb4dd9 | 444 | vm_state_notify(0, state); |
922453bc | 445 | bdrv_drain_all(); |
55df6f33 | 446 | bdrv_flush_all(); |
296af7c9 BS |
447 | monitor_protocol_event(QEVENT_STOP, NULL); |
448 | } | |
449 | } | |
450 | ||
9349b4f9 | 451 | static int cpu_can_run(CPUArchState *env) |
296af7c9 | 452 | { |
4fdeee7c AF |
453 | CPUState *cpu = ENV_GET_CPU(env); |
454 | ||
455 | if (cpu->stop) { | |
296af7c9 | 456 | return 0; |
0ab07c62 | 457 | } |
1354869c | 458 | if (env->stopped || !runstate_is_running()) { |
296af7c9 | 459 | return 0; |
0ab07c62 | 460 | } |
296af7c9 BS |
461 | return 1; |
462 | } | |
463 | ||
9349b4f9 | 464 | static void cpu_handle_guest_debug(CPUArchState *env) |
83f338f7 | 465 | { |
3c638d06 | 466 | gdb_set_stop_cpu(env); |
8cf71710 | 467 | qemu_system_debug_request(); |
83f338f7 | 468 | env->stopped = 1; |
3c638d06 JK |
469 | } |
470 | ||
714bd040 PB |
471 | static void cpu_signal(int sig) |
472 | { | |
473 | if (cpu_single_env) { | |
474 | cpu_exit(cpu_single_env); | |
475 | } | |
476 | exit_request = 1; | |
477 | } | |
714bd040 | 478 | |
6d9cb73c JK |
479 | #ifdef CONFIG_LINUX |
480 | static void sigbus_reraise(void) | |
481 | { | |
482 | sigset_t set; | |
483 | struct sigaction action; | |
484 | ||
485 | memset(&action, 0, sizeof(action)); | |
486 | action.sa_handler = SIG_DFL; | |
487 | if (!sigaction(SIGBUS, &action, NULL)) { | |
488 | raise(SIGBUS); | |
489 | sigemptyset(&set); | |
490 | sigaddset(&set, SIGBUS); | |
491 | sigprocmask(SIG_UNBLOCK, &set, NULL); | |
492 | } | |
493 | perror("Failed to re-raise SIGBUS!\n"); | |
494 | abort(); | |
495 | } | |
496 | ||
497 | static void sigbus_handler(int n, struct qemu_signalfd_siginfo *siginfo, | |
498 | void *ctx) | |
499 | { | |
500 | if (kvm_on_sigbus(siginfo->ssi_code, | |
501 | (void *)(intptr_t)siginfo->ssi_addr)) { | |
502 | sigbus_reraise(); | |
503 | } | |
504 | } | |
505 | ||
506 | static void qemu_init_sigbus(void) | |
507 | { | |
508 | struct sigaction action; | |
509 | ||
510 | memset(&action, 0, sizeof(action)); | |
511 | action.sa_flags = SA_SIGINFO; | |
512 | action.sa_sigaction = (void (*)(int, siginfo_t*, void*))sigbus_handler; | |
513 | sigaction(SIGBUS, &action, NULL); | |
514 | ||
515 | prctl(PR_MCE_KILL, PR_MCE_KILL_SET, PR_MCE_KILL_EARLY, 0, 0); | |
516 | } | |
517 | ||
9349b4f9 | 518 | static void qemu_kvm_eat_signals(CPUArchState *env) |
1ab3c6c0 JK |
519 | { |
520 | struct timespec ts = { 0, 0 }; | |
521 | siginfo_t siginfo; | |
522 | sigset_t waitset; | |
523 | sigset_t chkset; | |
524 | int r; | |
525 | ||
526 | sigemptyset(&waitset); | |
527 | sigaddset(&waitset, SIG_IPI); | |
528 | sigaddset(&waitset, SIGBUS); | |
529 | ||
530 | do { | |
531 | r = sigtimedwait(&waitset, &siginfo, &ts); | |
532 | if (r == -1 && !(errno == EAGAIN || errno == EINTR)) { | |
533 | perror("sigtimedwait"); | |
534 | exit(1); | |
535 | } | |
536 | ||
537 | switch (r) { | |
538 | case SIGBUS: | |
539 | if (kvm_on_sigbus_vcpu(env, siginfo.si_code, siginfo.si_addr)) { | |
540 | sigbus_reraise(); | |
541 | } | |
542 | break; | |
543 | default: | |
544 | break; | |
545 | } | |
546 | ||
547 | r = sigpending(&chkset); | |
548 | if (r == -1) { | |
549 | perror("sigpending"); | |
550 | exit(1); | |
551 | } | |
552 | } while (sigismember(&chkset, SIG_IPI) || sigismember(&chkset, SIGBUS)); | |
1ab3c6c0 JK |
553 | } |
554 | ||
6d9cb73c JK |
555 | #else /* !CONFIG_LINUX */ |
556 | ||
557 | static void qemu_init_sigbus(void) | |
558 | { | |
559 | } | |
1ab3c6c0 | 560 | |
9349b4f9 | 561 | static void qemu_kvm_eat_signals(CPUArchState *env) |
1ab3c6c0 JK |
562 | { |
563 | } | |
6d9cb73c JK |
564 | #endif /* !CONFIG_LINUX */ |
565 | ||
296af7c9 | 566 | #ifndef _WIN32 |
55f8d6ac JK |
567 | static void dummy_signal(int sig) |
568 | { | |
569 | } | |
55f8d6ac | 570 | |
9349b4f9 | 571 | static void qemu_kvm_init_cpu_signals(CPUArchState *env) |
714bd040 PB |
572 | { |
573 | int r; | |
574 | sigset_t set; | |
575 | struct sigaction sigact; | |
576 | ||
577 | memset(&sigact, 0, sizeof(sigact)); | |
578 | sigact.sa_handler = dummy_signal; | |
579 | sigaction(SIG_IPI, &sigact, NULL); | |
580 | ||
714bd040 PB |
581 | pthread_sigmask(SIG_BLOCK, NULL, &set); |
582 | sigdelset(&set, SIG_IPI); | |
714bd040 PB |
583 | sigdelset(&set, SIGBUS); |
584 | r = kvm_set_signal_mask(env, &set); | |
585 | if (r) { | |
586 | fprintf(stderr, "kvm_set_signal_mask: %s\n", strerror(-r)); | |
587 | exit(1); | |
588 | } | |
589 | } | |
590 | ||
591 | static void qemu_tcg_init_cpu_signals(void) | |
592 | { | |
714bd040 PB |
593 | sigset_t set; |
594 | struct sigaction sigact; | |
595 | ||
596 | memset(&sigact, 0, sizeof(sigact)); | |
597 | sigact.sa_handler = cpu_signal; | |
598 | sigaction(SIG_IPI, &sigact, NULL); | |
599 | ||
600 | sigemptyset(&set); | |
601 | sigaddset(&set, SIG_IPI); | |
602 | pthread_sigmask(SIG_UNBLOCK, &set, NULL); | |
714bd040 PB |
603 | } |
604 | ||
55f8d6ac | 605 | #else /* _WIN32 */ |
9349b4f9 | 606 | static void qemu_kvm_init_cpu_signals(CPUArchState *env) |
ff48eb5f | 607 | { |
714bd040 PB |
608 | abort(); |
609 | } | |
ff48eb5f | 610 | |
714bd040 PB |
611 | static void qemu_tcg_init_cpu_signals(void) |
612 | { | |
ff48eb5f | 613 | } |
714bd040 | 614 | #endif /* _WIN32 */ |
ff48eb5f | 615 | |
b2532d88 | 616 | static QemuMutex qemu_global_mutex; |
46daff13 PB |
617 | static QemuCond qemu_io_proceeded_cond; |
618 | static bool iothread_requesting_mutex; | |
296af7c9 BS |
619 | |
620 | static QemuThread io_thread; | |
621 | ||
622 | static QemuThread *tcg_cpu_thread; | |
623 | static QemuCond *tcg_halt_cond; | |
624 | ||
296af7c9 BS |
625 | /* cpu creation */ |
626 | static QemuCond qemu_cpu_cond; | |
627 | /* system init */ | |
296af7c9 | 628 | static QemuCond qemu_pause_cond; |
e82bcec2 | 629 | static QemuCond qemu_work_cond; |
296af7c9 | 630 | |
d3b12f5d | 631 | void qemu_init_cpu_loop(void) |
296af7c9 | 632 | { |
6d9cb73c | 633 | qemu_init_sigbus(); |
ed94592b | 634 | qemu_cond_init(&qemu_cpu_cond); |
ed94592b AL |
635 | qemu_cond_init(&qemu_pause_cond); |
636 | qemu_cond_init(&qemu_work_cond); | |
46daff13 | 637 | qemu_cond_init(&qemu_io_proceeded_cond); |
296af7c9 | 638 | qemu_mutex_init(&qemu_global_mutex); |
296af7c9 | 639 | |
b7680cb6 | 640 | qemu_thread_get_self(&io_thread); |
296af7c9 BS |
641 | } |
642 | ||
9349b4f9 | 643 | void run_on_cpu(CPUArchState *env, void (*func)(void *data), void *data) |
e82bcec2 | 644 | { |
60e82579 | 645 | CPUState *cpu = ENV_GET_CPU(env); |
e82bcec2 MT |
646 | struct qemu_work_item wi; |
647 | ||
60e82579 | 648 | if (qemu_cpu_is_self(cpu)) { |
e82bcec2 MT |
649 | func(data); |
650 | return; | |
651 | } | |
652 | ||
653 | wi.func = func; | |
654 | wi.data = data; | |
0ab07c62 | 655 | if (!env->queued_work_first) { |
e82bcec2 | 656 | env->queued_work_first = &wi; |
0ab07c62 | 657 | } else { |
e82bcec2 | 658 | env->queued_work_last->next = &wi; |
0ab07c62 | 659 | } |
e82bcec2 MT |
660 | env->queued_work_last = &wi; |
661 | wi.next = NULL; | |
662 | wi.done = false; | |
663 | ||
664 | qemu_cpu_kick(env); | |
665 | while (!wi.done) { | |
9349b4f9 | 666 | CPUArchState *self_env = cpu_single_env; |
e82bcec2 MT |
667 | |
668 | qemu_cond_wait(&qemu_work_cond, &qemu_global_mutex); | |
669 | cpu_single_env = self_env; | |
670 | } | |
671 | } | |
672 | ||
9349b4f9 | 673 | static void flush_queued_work(CPUArchState *env) |
e82bcec2 MT |
674 | { |
675 | struct qemu_work_item *wi; | |
676 | ||
0ab07c62 | 677 | if (!env->queued_work_first) { |
e82bcec2 | 678 | return; |
0ab07c62 | 679 | } |
e82bcec2 MT |
680 | |
681 | while ((wi = env->queued_work_first)) { | |
682 | env->queued_work_first = wi->next; | |
683 | wi->func(wi->data); | |
684 | wi->done = true; | |
685 | } | |
686 | env->queued_work_last = NULL; | |
687 | qemu_cond_broadcast(&qemu_work_cond); | |
688 | } | |
689 | ||
9349b4f9 | 690 | static void qemu_wait_io_event_common(CPUArchState *env) |
296af7c9 | 691 | { |
216fc9a4 AF |
692 | CPUState *cpu = ENV_GET_CPU(env); |
693 | ||
4fdeee7c AF |
694 | if (cpu->stop) { |
695 | cpu->stop = false; | |
296af7c9 BS |
696 | env->stopped = 1; |
697 | qemu_cond_signal(&qemu_pause_cond); | |
698 | } | |
e82bcec2 | 699 | flush_queued_work(env); |
216fc9a4 | 700 | cpu->thread_kicked = false; |
296af7c9 BS |
701 | } |
702 | ||
6cabe1f3 | 703 | static void qemu_tcg_wait_io_event(void) |
296af7c9 | 704 | { |
9349b4f9 | 705 | CPUArchState *env; |
6cabe1f3 | 706 | |
16400322 | 707 | while (all_cpu_threads_idle()) { |
ab33fcda PB |
708 | /* Start accounting real time to the virtual clock if the CPUs |
709 | are idle. */ | |
710 | qemu_clock_warp(vm_clock); | |
9705fbb5 | 711 | qemu_cond_wait(tcg_halt_cond, &qemu_global_mutex); |
16400322 | 712 | } |
296af7c9 | 713 | |
46daff13 PB |
714 | while (iothread_requesting_mutex) { |
715 | qemu_cond_wait(&qemu_io_proceeded_cond, &qemu_global_mutex); | |
716 | } | |
6cabe1f3 JK |
717 | |
718 | for (env = first_cpu; env != NULL; env = env->next_cpu) { | |
719 | qemu_wait_io_event_common(env); | |
720 | } | |
296af7c9 BS |
721 | } |
722 | ||
9349b4f9 | 723 | static void qemu_kvm_wait_io_event(CPUArchState *env) |
296af7c9 | 724 | { |
16400322 | 725 | while (cpu_thread_is_idle(env)) { |
9705fbb5 | 726 | qemu_cond_wait(env->halt_cond, &qemu_global_mutex); |
16400322 | 727 | } |
296af7c9 | 728 | |
5db5bdac | 729 | qemu_kvm_eat_signals(env); |
296af7c9 BS |
730 | qemu_wait_io_event_common(env); |
731 | } | |
732 | ||
7e97cd88 | 733 | static void *qemu_kvm_cpu_thread_fn(void *arg) |
296af7c9 | 734 | { |
9349b4f9 | 735 | CPUArchState *env = arg; |
814e612e | 736 | CPUState *cpu = ENV_GET_CPU(env); |
84b4915d | 737 | int r; |
296af7c9 | 738 | |
6164e6d6 | 739 | qemu_mutex_lock(&qemu_global_mutex); |
814e612e | 740 | qemu_thread_get_self(cpu->thread); |
dc7a09cf | 741 | env->thread_id = qemu_get_thread_id(); |
e479c207 | 742 | cpu_single_env = env; |
296af7c9 | 743 | |
84b4915d JK |
744 | r = kvm_init_vcpu(env); |
745 | if (r < 0) { | |
746 | fprintf(stderr, "kvm_init_vcpu failed: %s\n", strerror(-r)); | |
747 | exit(1); | |
748 | } | |
296af7c9 | 749 | |
55f8d6ac | 750 | qemu_kvm_init_cpu_signals(env); |
296af7c9 BS |
751 | |
752 | /* signal CPU creation */ | |
61a46217 | 753 | cpu->created = true; |
296af7c9 BS |
754 | qemu_cond_signal(&qemu_cpu_cond); |
755 | ||
296af7c9 | 756 | while (1) { |
0ab07c62 | 757 | if (cpu_can_run(env)) { |
6792a57b | 758 | r = kvm_cpu_exec(env); |
83f338f7 | 759 | if (r == EXCP_DEBUG) { |
1009d2ed | 760 | cpu_handle_guest_debug(env); |
83f338f7 | 761 | } |
0ab07c62 | 762 | } |
296af7c9 BS |
763 | qemu_kvm_wait_io_event(env); |
764 | } | |
765 | ||
766 | return NULL; | |
767 | } | |
768 | ||
c7f0f3b1 AL |
769 | static void *qemu_dummy_cpu_thread_fn(void *arg) |
770 | { | |
771 | #ifdef _WIN32 | |
772 | fprintf(stderr, "qtest is not supported under Windows\n"); | |
773 | exit(1); | |
774 | #else | |
775 | CPUArchState *env = arg; | |
814e612e | 776 | CPUState *cpu = ENV_GET_CPU(env); |
c7f0f3b1 AL |
777 | sigset_t waitset; |
778 | int r; | |
779 | ||
780 | qemu_mutex_lock_iothread(); | |
814e612e | 781 | qemu_thread_get_self(cpu->thread); |
c7f0f3b1 AL |
782 | env->thread_id = qemu_get_thread_id(); |
783 | ||
784 | sigemptyset(&waitset); | |
785 | sigaddset(&waitset, SIG_IPI); | |
786 | ||
787 | /* signal CPU creation */ | |
61a46217 | 788 | cpu->created = true; |
c7f0f3b1 AL |
789 | qemu_cond_signal(&qemu_cpu_cond); |
790 | ||
791 | cpu_single_env = env; | |
792 | while (1) { | |
793 | cpu_single_env = NULL; | |
794 | qemu_mutex_unlock_iothread(); | |
795 | do { | |
796 | int sig; | |
797 | r = sigwait(&waitset, &sig); | |
798 | } while (r == -1 && (errno == EAGAIN || errno == EINTR)); | |
799 | if (r == -1) { | |
800 | perror("sigwait"); | |
801 | exit(1); | |
802 | } | |
803 | qemu_mutex_lock_iothread(); | |
804 | cpu_single_env = env; | |
805 | qemu_wait_io_event_common(env); | |
806 | } | |
807 | ||
808 | return NULL; | |
809 | #endif | |
810 | } | |
811 | ||
bdb7ca67 JK |
812 | static void tcg_exec_all(void); |
813 | ||
7e97cd88 | 814 | static void *qemu_tcg_cpu_thread_fn(void *arg) |
296af7c9 | 815 | { |
9349b4f9 | 816 | CPUArchState *env = arg; |
814e612e | 817 | CPUState *cpu = ENV_GET_CPU(env); |
296af7c9 | 818 | |
55f8d6ac | 819 | qemu_tcg_init_cpu_signals(); |
814e612e | 820 | qemu_thread_get_self(cpu->thread); |
296af7c9 BS |
821 | |
822 | /* signal CPU creation */ | |
823 | qemu_mutex_lock(&qemu_global_mutex); | |
0ab07c62 | 824 | for (env = first_cpu; env != NULL; env = env->next_cpu) { |
61a46217 | 825 | cpu = ENV_GET_CPU(env); |
dc7a09cf | 826 | env->thread_id = qemu_get_thread_id(); |
61a46217 | 827 | cpu->created = true; |
0ab07c62 | 828 | } |
296af7c9 BS |
829 | qemu_cond_signal(&qemu_cpu_cond); |
830 | ||
fa7d1867 JK |
831 | /* wait for initial kick-off after machine start */ |
832 | while (first_cpu->stopped) { | |
833 | qemu_cond_wait(tcg_halt_cond, &qemu_global_mutex); | |
8e564b4e JK |
834 | |
835 | /* process any pending work */ | |
836 | for (env = first_cpu; env != NULL; env = env->next_cpu) { | |
837 | qemu_wait_io_event_common(env); | |
838 | } | |
0ab07c62 | 839 | } |
296af7c9 BS |
840 | |
841 | while (1) { | |
bdb7ca67 | 842 | tcg_exec_all(); |
946fb27c | 843 | if (use_icount && qemu_clock_deadline(vm_clock) <= 0) { |
3b2319a3 PB |
844 | qemu_notify_event(); |
845 | } | |
6cabe1f3 | 846 | qemu_tcg_wait_io_event(); |
296af7c9 BS |
847 | } |
848 | ||
849 | return NULL; | |
850 | } | |
851 | ||
2ff09a40 | 852 | static void qemu_cpu_kick_thread(CPUState *cpu) |
cc015e9a PB |
853 | { |
854 | #ifndef _WIN32 | |
855 | int err; | |
856 | ||
814e612e | 857 | err = pthread_kill(cpu->thread->thread, SIG_IPI); |
cc015e9a PB |
858 | if (err) { |
859 | fprintf(stderr, "qemu:%s: %s", __func__, strerror(err)); | |
860 | exit(1); | |
861 | } | |
862 | #else /* _WIN32 */ | |
60e82579 | 863 | if (!qemu_cpu_is_self(cpu)) { |
bcba2a72 | 864 | SuspendThread(cpu->hThread); |
cc015e9a | 865 | cpu_signal(0); |
bcba2a72 | 866 | ResumeThread(cpu->hThread); |
cc015e9a PB |
867 | } |
868 | #endif | |
869 | } | |
870 | ||
296af7c9 BS |
871 | void qemu_cpu_kick(void *_env) |
872 | { | |
9349b4f9 | 873 | CPUArchState *env = _env; |
216fc9a4 | 874 | CPUState *cpu = ENV_GET_CPU(env); |
296af7c9 | 875 | |
296af7c9 | 876 | qemu_cond_broadcast(env->halt_cond); |
216fc9a4 | 877 | if (!tcg_enabled() && !cpu->thread_kicked) { |
2ff09a40 | 878 | qemu_cpu_kick_thread(cpu); |
216fc9a4 | 879 | cpu->thread_kicked = true; |
aa2c364b | 880 | } |
296af7c9 BS |
881 | } |
882 | ||
46d62fac | 883 | void qemu_cpu_kick_self(void) |
296af7c9 | 884 | { |
b55c22c6 | 885 | #ifndef _WIN32 |
46d62fac | 886 | assert(cpu_single_env); |
216fc9a4 | 887 | CPUState *cpu_single_cpu = ENV_GET_CPU(cpu_single_env); |
296af7c9 | 888 | |
216fc9a4 | 889 | if (!cpu_single_cpu->thread_kicked) { |
2ff09a40 | 890 | qemu_cpu_kick_thread(cpu_single_cpu); |
216fc9a4 | 891 | cpu_single_cpu->thread_kicked = true; |
296af7c9 | 892 | } |
b55c22c6 PB |
893 | #else |
894 | abort(); | |
895 | #endif | |
296af7c9 BS |
896 | } |
897 | ||
60e82579 | 898 | bool qemu_cpu_is_self(CPUState *cpu) |
296af7c9 | 899 | { |
814e612e | 900 | return qemu_thread_is_self(cpu->thread); |
296af7c9 BS |
901 | } |
902 | ||
aa723c23 JQ |
903 | static bool qemu_in_vcpu_thread(void) |
904 | { | |
60e82579 | 905 | return cpu_single_env && qemu_cpu_is_self(ENV_GET_CPU(cpu_single_env)); |
aa723c23 JQ |
906 | } |
907 | ||
296af7c9 BS |
908 | void qemu_mutex_lock_iothread(void) |
909 | { | |
c7f0f3b1 | 910 | if (!tcg_enabled()) { |
296af7c9 | 911 | qemu_mutex_lock(&qemu_global_mutex); |
1a28cac3 | 912 | } else { |
46daff13 | 913 | iothread_requesting_mutex = true; |
1a28cac3 | 914 | if (qemu_mutex_trylock(&qemu_global_mutex)) { |
2ff09a40 | 915 | qemu_cpu_kick_thread(ENV_GET_CPU(first_cpu)); |
1a28cac3 MT |
916 | qemu_mutex_lock(&qemu_global_mutex); |
917 | } | |
46daff13 PB |
918 | iothread_requesting_mutex = false; |
919 | qemu_cond_broadcast(&qemu_io_proceeded_cond); | |
1a28cac3 | 920 | } |
296af7c9 BS |
921 | } |
922 | ||
923 | void qemu_mutex_unlock_iothread(void) | |
924 | { | |
925 | qemu_mutex_unlock(&qemu_global_mutex); | |
926 | } | |
927 | ||
928 | static int all_vcpus_paused(void) | |
929 | { | |
9349b4f9 | 930 | CPUArchState *penv = first_cpu; |
296af7c9 BS |
931 | |
932 | while (penv) { | |
0ab07c62 | 933 | if (!penv->stopped) { |
296af7c9 | 934 | return 0; |
0ab07c62 | 935 | } |
5207a5e0 | 936 | penv = penv->next_cpu; |
296af7c9 BS |
937 | } |
938 | ||
939 | return 1; | |
940 | } | |
941 | ||
942 | void pause_all_vcpus(void) | |
943 | { | |
9349b4f9 | 944 | CPUArchState *penv = first_cpu; |
296af7c9 | 945 | |
a5c57d64 | 946 | qemu_clock_enable(vm_clock, false); |
296af7c9 | 947 | while (penv) { |
4fdeee7c AF |
948 | CPUState *pcpu = ENV_GET_CPU(penv); |
949 | pcpu->stop = true; | |
296af7c9 | 950 | qemu_cpu_kick(penv); |
5207a5e0 | 951 | penv = penv->next_cpu; |
296af7c9 BS |
952 | } |
953 | ||
aa723c23 | 954 | if (qemu_in_vcpu_thread()) { |
d798e974 JK |
955 | cpu_stop_current(); |
956 | if (!kvm_enabled()) { | |
957 | while (penv) { | |
4fdeee7c AF |
958 | CPUState *pcpu = ENV_GET_CPU(penv); |
959 | pcpu->stop = 0; | |
d798e974 JK |
960 | penv->stopped = 1; |
961 | penv = penv->next_cpu; | |
962 | } | |
963 | return; | |
964 | } | |
965 | } | |
966 | ||
296af7c9 | 967 | while (!all_vcpus_paused()) { |
be7d6c57 | 968 | qemu_cond_wait(&qemu_pause_cond, &qemu_global_mutex); |
296af7c9 BS |
969 | penv = first_cpu; |
970 | while (penv) { | |
1fbb22e5 | 971 | qemu_cpu_kick(penv); |
5207a5e0 | 972 | penv = penv->next_cpu; |
296af7c9 BS |
973 | } |
974 | } | |
975 | } | |
976 | ||
977 | void resume_all_vcpus(void) | |
978 | { | |
9349b4f9 | 979 | CPUArchState *penv = first_cpu; |
296af7c9 | 980 | |
47113ab6 | 981 | qemu_clock_enable(vm_clock, true); |
296af7c9 | 982 | while (penv) { |
4fdeee7c AF |
983 | CPUState *pcpu = ENV_GET_CPU(penv); |
984 | pcpu->stop = false; | |
296af7c9 | 985 | penv->stopped = 0; |
296af7c9 | 986 | qemu_cpu_kick(penv); |
5207a5e0 | 987 | penv = penv->next_cpu; |
296af7c9 BS |
988 | } |
989 | } | |
990 | ||
7e97cd88 | 991 | static void qemu_tcg_init_vcpu(void *_env) |
296af7c9 | 992 | { |
9349b4f9 | 993 | CPUArchState *env = _env; |
bcba2a72 | 994 | CPUState *cpu = ENV_GET_CPU(env); |
0ab07c62 | 995 | |
296af7c9 BS |
996 | /* share a single thread for all cpus with TCG */ |
997 | if (!tcg_cpu_thread) { | |
814e612e | 998 | cpu->thread = g_malloc0(sizeof(QemuThread)); |
7267c094 | 999 | env->halt_cond = g_malloc0(sizeof(QemuCond)); |
296af7c9 | 1000 | qemu_cond_init(env->halt_cond); |
fa7d1867 | 1001 | tcg_halt_cond = env->halt_cond; |
814e612e | 1002 | qemu_thread_create(cpu->thread, qemu_tcg_cpu_thread_fn, env, |
1ecf47bf PB |
1003 | QEMU_THREAD_JOINABLE); |
1004 | #ifdef _WIN32 | |
814e612e | 1005 | cpu->hThread = qemu_thread_get_handle(cpu->thread); |
1ecf47bf | 1006 | #endif |
61a46217 | 1007 | while (!cpu->created) { |
18a85728 | 1008 | qemu_cond_wait(&qemu_cpu_cond, &qemu_global_mutex); |
0ab07c62 | 1009 | } |
814e612e | 1010 | tcg_cpu_thread = cpu->thread; |
296af7c9 | 1011 | } else { |
814e612e | 1012 | cpu->thread = tcg_cpu_thread; |
296af7c9 BS |
1013 | env->halt_cond = tcg_halt_cond; |
1014 | } | |
1015 | } | |
1016 | ||
9349b4f9 | 1017 | static void qemu_kvm_start_vcpu(CPUArchState *env) |
296af7c9 | 1018 | { |
814e612e AF |
1019 | CPUState *cpu = ENV_GET_CPU(env); |
1020 | ||
1021 | cpu->thread = g_malloc0(sizeof(QemuThread)); | |
7267c094 | 1022 | env->halt_cond = g_malloc0(sizeof(QemuCond)); |
296af7c9 | 1023 | qemu_cond_init(env->halt_cond); |
814e612e | 1024 | qemu_thread_create(cpu->thread, qemu_kvm_cpu_thread_fn, env, |
1ecf47bf | 1025 | QEMU_THREAD_JOINABLE); |
61a46217 | 1026 | while (!cpu->created) { |
18a85728 | 1027 | qemu_cond_wait(&qemu_cpu_cond, &qemu_global_mutex); |
0ab07c62 | 1028 | } |
296af7c9 BS |
1029 | } |
1030 | ||
c7f0f3b1 AL |
1031 | static void qemu_dummy_start_vcpu(CPUArchState *env) |
1032 | { | |
814e612e AF |
1033 | CPUState *cpu = ENV_GET_CPU(env); |
1034 | ||
1035 | cpu->thread = g_malloc0(sizeof(QemuThread)); | |
c7f0f3b1 AL |
1036 | env->halt_cond = g_malloc0(sizeof(QemuCond)); |
1037 | qemu_cond_init(env->halt_cond); | |
814e612e | 1038 | qemu_thread_create(cpu->thread, qemu_dummy_cpu_thread_fn, env, |
c7f0f3b1 | 1039 | QEMU_THREAD_JOINABLE); |
61a46217 | 1040 | while (!cpu->created) { |
c7f0f3b1 AL |
1041 | qemu_cond_wait(&qemu_cpu_cond, &qemu_global_mutex); |
1042 | } | |
1043 | } | |
1044 | ||
296af7c9 BS |
1045 | void qemu_init_vcpu(void *_env) |
1046 | { | |
9349b4f9 | 1047 | CPUArchState *env = _env; |
296af7c9 BS |
1048 | |
1049 | env->nr_cores = smp_cores; | |
1050 | env->nr_threads = smp_threads; | |
fa7d1867 | 1051 | env->stopped = 1; |
0ab07c62 | 1052 | if (kvm_enabled()) { |
7e97cd88 | 1053 | qemu_kvm_start_vcpu(env); |
c7f0f3b1 | 1054 | } else if (tcg_enabled()) { |
7e97cd88 | 1055 | qemu_tcg_init_vcpu(env); |
c7f0f3b1 AL |
1056 | } else { |
1057 | qemu_dummy_start_vcpu(env); | |
0ab07c62 | 1058 | } |
296af7c9 BS |
1059 | } |
1060 | ||
b4a3d965 | 1061 | void cpu_stop_current(void) |
296af7c9 | 1062 | { |
b4a3d965 | 1063 | if (cpu_single_env) { |
4fdeee7c AF |
1064 | CPUState *cpu_single_cpu = ENV_GET_CPU(cpu_single_env); |
1065 | cpu_single_cpu->stop = false; | |
b4a3d965 JK |
1066 | cpu_single_env->stopped = 1; |
1067 | cpu_exit(cpu_single_env); | |
67bb172f | 1068 | qemu_cond_signal(&qemu_pause_cond); |
b4a3d965 | 1069 | } |
296af7c9 BS |
1070 | } |
1071 | ||
1dfb4dd9 | 1072 | void vm_stop(RunState state) |
296af7c9 | 1073 | { |
aa723c23 | 1074 | if (qemu_in_vcpu_thread()) { |
1dfb4dd9 | 1075 | qemu_system_vmstop_request(state); |
296af7c9 BS |
1076 | /* |
1077 | * FIXME: should not return to device code in case | |
1078 | * vm_stop() has been requested. | |
1079 | */ | |
b4a3d965 | 1080 | cpu_stop_current(); |
296af7c9 BS |
1081 | return; |
1082 | } | |
1dfb4dd9 | 1083 | do_vm_stop(state); |
296af7c9 BS |
1084 | } |
1085 | ||
8a9236f1 LC |
1086 | /* does a state transition even if the VM is already stopped, |
1087 | current state is forgotten forever */ | |
1088 | void vm_stop_force_state(RunState state) | |
1089 | { | |
1090 | if (runstate_is_running()) { | |
1091 | vm_stop(state); | |
1092 | } else { | |
1093 | runstate_set(state); | |
1094 | } | |
1095 | } | |
1096 | ||
9349b4f9 | 1097 | static int tcg_cpu_exec(CPUArchState *env) |
296af7c9 BS |
1098 | { |
1099 | int ret; | |
1100 | #ifdef CONFIG_PROFILER | |
1101 | int64_t ti; | |
1102 | #endif | |
1103 | ||
1104 | #ifdef CONFIG_PROFILER | |
1105 | ti = profile_getclock(); | |
1106 | #endif | |
1107 | if (use_icount) { | |
1108 | int64_t count; | |
1109 | int decr; | |
1110 | qemu_icount -= (env->icount_decr.u16.low + env->icount_extra); | |
1111 | env->icount_decr.u16.low = 0; | |
1112 | env->icount_extra = 0; | |
946fb27c | 1113 | count = qemu_icount_round(qemu_clock_deadline(vm_clock)); |
296af7c9 BS |
1114 | qemu_icount += count; |
1115 | decr = (count > 0xffff) ? 0xffff : count; | |
1116 | count -= decr; | |
1117 | env->icount_decr.u16.low = decr; | |
1118 | env->icount_extra = count; | |
1119 | } | |
1120 | ret = cpu_exec(env); | |
1121 | #ifdef CONFIG_PROFILER | |
1122 | qemu_time += profile_getclock() - ti; | |
1123 | #endif | |
1124 | if (use_icount) { | |
1125 | /* Fold pending instructions back into the | |
1126 | instruction counter, and clear the interrupt flag. */ | |
1127 | qemu_icount -= (env->icount_decr.u16.low | |
1128 | + env->icount_extra); | |
1129 | env->icount_decr.u32 = 0; | |
1130 | env->icount_extra = 0; | |
1131 | } | |
1132 | return ret; | |
1133 | } | |
1134 | ||
bdb7ca67 | 1135 | static void tcg_exec_all(void) |
296af7c9 | 1136 | { |
9a36085b JK |
1137 | int r; |
1138 | ||
ab33fcda PB |
1139 | /* Account partial waits to the vm_clock. */ |
1140 | qemu_clock_warp(vm_clock); | |
1141 | ||
0ab07c62 | 1142 | if (next_cpu == NULL) { |
296af7c9 | 1143 | next_cpu = first_cpu; |
0ab07c62 | 1144 | } |
c629a4bc | 1145 | for (; next_cpu != NULL && !exit_request; next_cpu = next_cpu->next_cpu) { |
9349b4f9 | 1146 | CPUArchState *env = next_cpu; |
4fdeee7c | 1147 | CPUState *cpu = ENV_GET_CPU(env); |
296af7c9 BS |
1148 | |
1149 | qemu_clock_enable(vm_clock, | |
345f4426 | 1150 | (env->singlestep_enabled & SSTEP_NOTIMER) == 0); |
296af7c9 | 1151 | |
3c638d06 | 1152 | if (cpu_can_run(env)) { |
bdb7ca67 | 1153 | r = tcg_cpu_exec(env); |
9a36085b | 1154 | if (r == EXCP_DEBUG) { |
1009d2ed | 1155 | cpu_handle_guest_debug(env); |
3c638d06 JK |
1156 | break; |
1157 | } | |
4fdeee7c | 1158 | } else if (cpu->stop || env->stopped) { |
296af7c9 BS |
1159 | break; |
1160 | } | |
1161 | } | |
c629a4bc | 1162 | exit_request = 0; |
296af7c9 BS |
1163 | } |
1164 | ||
1165 | void set_numa_modes(void) | |
1166 | { | |
9349b4f9 | 1167 | CPUArchState *env; |
296af7c9 BS |
1168 | int i; |
1169 | ||
1170 | for (env = first_cpu; env != NULL; env = env->next_cpu) { | |
1171 | for (i = 0; i < nb_numa_nodes; i++) { | |
ee785fed | 1172 | if (test_bit(env->cpu_index, node_cpumask[i])) { |
296af7c9 BS |
1173 | env->numa_node = i; |
1174 | } | |
1175 | } | |
1176 | } | |
1177 | } | |
1178 | ||
1179 | void set_cpu_log(const char *optarg) | |
1180 | { | |
1181 | int mask; | |
1182 | const CPULogItem *item; | |
1183 | ||
1184 | mask = cpu_str_to_log_mask(optarg); | |
1185 | if (!mask) { | |
1186 | printf("Log items (comma separated):\n"); | |
1187 | for (item = cpu_log_items; item->mask != 0; item++) { | |
1188 | printf("%-10s %s\n", item->name, item->help); | |
1189 | } | |
1190 | exit(1); | |
1191 | } | |
1192 | cpu_set_log(mask); | |
1193 | } | |
29e922b6 | 1194 | |
c235d738 MF |
1195 | void set_cpu_log_filename(const char *optarg) |
1196 | { | |
1197 | cpu_set_log_filename(optarg); | |
1198 | } | |
1199 | ||
9a78eead | 1200 | void list_cpus(FILE *f, fprintf_function cpu_fprintf, const char *optarg) |
262353cb BS |
1201 | { |
1202 | /* XXX: implement xxx_cpu_list for targets that still miss it */ | |
e916cbf8 PM |
1203 | #if defined(cpu_list) |
1204 | cpu_list(f, cpu_fprintf); | |
262353cb BS |
1205 | #endif |
1206 | } | |
de0b36b6 LC |
1207 | |
1208 | CpuInfoList *qmp_query_cpus(Error **errp) | |
1209 | { | |
1210 | CpuInfoList *head = NULL, *cur_item = NULL; | |
9349b4f9 | 1211 | CPUArchState *env; |
de0b36b6 LC |
1212 | |
1213 | for(env = first_cpu; env != NULL; env = env->next_cpu) { | |
1214 | CpuInfoList *info; | |
1215 | ||
1216 | cpu_synchronize_state(env); | |
1217 | ||
1218 | info = g_malloc0(sizeof(*info)); | |
1219 | info->value = g_malloc0(sizeof(*info->value)); | |
1220 | info->value->CPU = env->cpu_index; | |
1221 | info->value->current = (env == first_cpu); | |
1222 | info->value->halted = env->halted; | |
1223 | info->value->thread_id = env->thread_id; | |
1224 | #if defined(TARGET_I386) | |
1225 | info->value->has_pc = true; | |
1226 | info->value->pc = env->eip + env->segs[R_CS].base; | |
1227 | #elif defined(TARGET_PPC) | |
1228 | info->value->has_nip = true; | |
1229 | info->value->nip = env->nip; | |
1230 | #elif defined(TARGET_SPARC) | |
1231 | info->value->has_pc = true; | |
1232 | info->value->pc = env->pc; | |
1233 | info->value->has_npc = true; | |
1234 | info->value->npc = env->npc; | |
1235 | #elif defined(TARGET_MIPS) | |
1236 | info->value->has_PC = true; | |
1237 | info->value->PC = env->active_tc.PC; | |
1238 | #endif | |
1239 | ||
1240 | /* XXX: waiting for the qapi to support GSList */ | |
1241 | if (!cur_item) { | |
1242 | head = cur_item = info; | |
1243 | } else { | |
1244 | cur_item->next = info; | |
1245 | cur_item = info; | |
1246 | } | |
1247 | } | |
1248 | ||
1249 | return head; | |
1250 | } | |
0cfd6a9a LC |
1251 | |
1252 | void qmp_memsave(int64_t addr, int64_t size, const char *filename, | |
1253 | bool has_cpu, int64_t cpu_index, Error **errp) | |
1254 | { | |
1255 | FILE *f; | |
1256 | uint32_t l; | |
9349b4f9 | 1257 | CPUArchState *env; |
0cfd6a9a LC |
1258 | uint8_t buf[1024]; |
1259 | ||
1260 | if (!has_cpu) { | |
1261 | cpu_index = 0; | |
1262 | } | |
1263 | ||
1264 | for (env = first_cpu; env; env = env->next_cpu) { | |
1265 | if (cpu_index == env->cpu_index) { | |
1266 | break; | |
1267 | } | |
1268 | } | |
1269 | ||
1270 | if (env == NULL) { | |
1271 | error_set(errp, QERR_INVALID_PARAMETER_VALUE, "cpu-index", | |
1272 | "a CPU number"); | |
1273 | return; | |
1274 | } | |
1275 | ||
1276 | f = fopen(filename, "wb"); | |
1277 | if (!f) { | |
1278 | error_set(errp, QERR_OPEN_FILE_FAILED, filename); | |
1279 | return; | |
1280 | } | |
1281 | ||
1282 | while (size != 0) { | |
1283 | l = sizeof(buf); | |
1284 | if (l > size) | |
1285 | l = size; | |
1286 | cpu_memory_rw_debug(env, addr, buf, l, 0); | |
1287 | if (fwrite(buf, 1, l, f) != l) { | |
1288 | error_set(errp, QERR_IO_ERROR); | |
1289 | goto exit; | |
1290 | } | |
1291 | addr += l; | |
1292 | size -= l; | |
1293 | } | |
1294 | ||
1295 | exit: | |
1296 | fclose(f); | |
1297 | } | |
6d3962bf LC |
1298 | |
1299 | void qmp_pmemsave(int64_t addr, int64_t size, const char *filename, | |
1300 | Error **errp) | |
1301 | { | |
1302 | FILE *f; | |
1303 | uint32_t l; | |
1304 | uint8_t buf[1024]; | |
1305 | ||
1306 | f = fopen(filename, "wb"); | |
1307 | if (!f) { | |
1308 | error_set(errp, QERR_OPEN_FILE_FAILED, filename); | |
1309 | return; | |
1310 | } | |
1311 | ||
1312 | while (size != 0) { | |
1313 | l = sizeof(buf); | |
1314 | if (l > size) | |
1315 | l = size; | |
1316 | cpu_physical_memory_rw(addr, buf, l, 0); | |
1317 | if (fwrite(buf, 1, l, f) != l) { | |
1318 | error_set(errp, QERR_IO_ERROR); | |
1319 | goto exit; | |
1320 | } | |
1321 | addr += l; | |
1322 | size -= l; | |
1323 | } | |
1324 | ||
1325 | exit: | |
1326 | fclose(f); | |
1327 | } | |
ab49ab5c LC |
1328 | |
1329 | void qmp_inject_nmi(Error **errp) | |
1330 | { | |
1331 | #if defined(TARGET_I386) | |
9349b4f9 | 1332 | CPUArchState *env; |
ab49ab5c LC |
1333 | |
1334 | for (env = first_cpu; env != NULL; env = env->next_cpu) { | |
02c09195 JK |
1335 | if (!env->apic_state) { |
1336 | cpu_interrupt(env, CPU_INTERRUPT_NMI); | |
1337 | } else { | |
1338 | apic_deliver_nmi(env->apic_state); | |
1339 | } | |
ab49ab5c LC |
1340 | } |
1341 | #else | |
1342 | error_set(errp, QERR_UNSUPPORTED); | |
1343 | #endif | |
1344 | } |