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76aaf220 DV |
1 | /* |
2 | * Copyright © 2010 Daniel Vetter | |
c4ac524c | 3 | * Copyright © 2011-2014 Intel Corporation |
76aaf220 DV |
4 | * |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
22 | * IN THE SOFTWARE. | |
23 | * | |
24 | */ | |
25 | ||
0e46ce2e | 26 | #include <linux/seq_file.h> |
760285e7 DH |
27 | #include <drm/drmP.h> |
28 | #include <drm/i915_drm.h> | |
76aaf220 | 29 | #include "i915_drv.h" |
5dda8fa3 | 30 | #include "i915_vgpu.h" |
76aaf220 DV |
31 | #include "i915_trace.h" |
32 | #include "intel_drv.h" | |
33 | ||
45f8f69a TU |
34 | /** |
35 | * DOC: Global GTT views | |
36 | * | |
37 | * Background and previous state | |
38 | * | |
39 | * Historically objects could exists (be bound) in global GTT space only as | |
40 | * singular instances with a view representing all of the object's backing pages | |
41 | * in a linear fashion. This view will be called a normal view. | |
42 | * | |
43 | * To support multiple views of the same object, where the number of mapped | |
44 | * pages is not equal to the backing store, or where the layout of the pages | |
45 | * is not linear, concept of a GGTT view was added. | |
46 | * | |
47 | * One example of an alternative view is a stereo display driven by a single | |
48 | * image. In this case we would have a framebuffer looking like this | |
49 | * (2x2 pages): | |
50 | * | |
51 | * 12 | |
52 | * 34 | |
53 | * | |
54 | * Above would represent a normal GGTT view as normally mapped for GPU or CPU | |
55 | * rendering. In contrast, fed to the display engine would be an alternative | |
56 | * view which could look something like this: | |
57 | * | |
58 | * 1212 | |
59 | * 3434 | |
60 | * | |
61 | * In this example both the size and layout of pages in the alternative view is | |
62 | * different from the normal view. | |
63 | * | |
64 | * Implementation and usage | |
65 | * | |
66 | * GGTT views are implemented using VMAs and are distinguished via enum | |
67 | * i915_ggtt_view_type and struct i915_ggtt_view. | |
68 | * | |
69 | * A new flavour of core GEM functions which work with GGTT bound objects were | |
ec7adb6e JL |
70 | * added with the _ggtt_ infix, and sometimes with _view postfix to avoid |
71 | * renaming in large amounts of code. They take the struct i915_ggtt_view | |
72 | * parameter encapsulating all metadata required to implement a view. | |
45f8f69a TU |
73 | * |
74 | * As a helper for callers which are only interested in the normal view, | |
75 | * globally const i915_ggtt_view_normal singleton instance exists. All old core | |
76 | * GEM API functions, the ones not taking the view parameter, are operating on, | |
77 | * or with the normal GGTT view. | |
78 | * | |
79 | * Code wanting to add or use a new GGTT view needs to: | |
80 | * | |
81 | * 1. Add a new enum with a suitable name. | |
82 | * 2. Extend the metadata in the i915_ggtt_view structure if required. | |
83 | * 3. Add support to i915_get_vma_pages(). | |
84 | * | |
85 | * New views are required to build a scatter-gather table from within the | |
86 | * i915_get_vma_pages function. This table is stored in the vma.ggtt_view and | |
87 | * exists for the lifetime of an VMA. | |
88 | * | |
89 | * Core API is designed to have copy semantics which means that passed in | |
90 | * struct i915_ggtt_view does not need to be persistent (left around after | |
91 | * calling the core API functions). | |
92 | * | |
93 | */ | |
94 | ||
70b9f6f8 DV |
95 | static int |
96 | i915_get_ggtt_vma_pages(struct i915_vma *vma); | |
97 | ||
fe14d5f4 | 98 | const struct i915_ggtt_view i915_ggtt_view_normal; |
9abc4648 JL |
99 | const struct i915_ggtt_view i915_ggtt_view_rotated = { |
100 | .type = I915_GGTT_VIEW_ROTATED | |
101 | }; | |
fe14d5f4 | 102 | |
cfa7c862 DV |
103 | static int sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt) |
104 | { | |
1893a71b CW |
105 | bool has_aliasing_ppgtt; |
106 | bool has_full_ppgtt; | |
107 | ||
108 | has_aliasing_ppgtt = INTEL_INFO(dev)->gen >= 6; | |
109 | has_full_ppgtt = INTEL_INFO(dev)->gen >= 7; | |
1893a71b | 110 | |
71ba2d64 YZ |
111 | if (intel_vgpu_active(dev)) |
112 | has_full_ppgtt = false; /* emulation is too hard */ | |
113 | ||
70ee45e1 DL |
114 | /* |
115 | * We don't allow disabling PPGTT for gen9+ as it's a requirement for | |
116 | * execlists, the sole mechanism available to submit work. | |
117 | */ | |
118 | if (INTEL_INFO(dev)->gen < 9 && | |
119 | (enable_ppgtt == 0 || !has_aliasing_ppgtt)) | |
cfa7c862 DV |
120 | return 0; |
121 | ||
122 | if (enable_ppgtt == 1) | |
123 | return 1; | |
124 | ||
1893a71b | 125 | if (enable_ppgtt == 2 && has_full_ppgtt) |
cfa7c862 DV |
126 | return 2; |
127 | ||
93a25a9e DV |
128 | #ifdef CONFIG_INTEL_IOMMU |
129 | /* Disable ppgtt on SNB if VT-d is on. */ | |
130 | if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) { | |
131 | DRM_INFO("Disabling PPGTT because VT-d is on\n"); | |
cfa7c862 | 132 | return 0; |
93a25a9e DV |
133 | } |
134 | #endif | |
135 | ||
62942ed7 | 136 | /* Early VLV doesn't have this */ |
ca2aed6c VS |
137 | if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && |
138 | dev->pdev->revision < 0xb) { | |
62942ed7 JB |
139 | DRM_DEBUG_DRIVER("disabling PPGTT on pre-B3 step VLV\n"); |
140 | return 0; | |
141 | } | |
142 | ||
2f82bbdf MT |
143 | if (INTEL_INFO(dev)->gen >= 8 && i915.enable_execlists) |
144 | return 2; | |
145 | else | |
146 | return has_aliasing_ppgtt ? 1 : 0; | |
93a25a9e DV |
147 | } |
148 | ||
70b9f6f8 DV |
149 | static int ppgtt_bind_vma(struct i915_vma *vma, |
150 | enum i915_cache_level cache_level, | |
151 | u32 unused) | |
47552659 DV |
152 | { |
153 | u32 pte_flags = 0; | |
154 | ||
155 | /* Currently applicable only to VLV */ | |
156 | if (vma->obj->gt_ro) | |
157 | pte_flags |= PTE_READ_ONLY; | |
158 | ||
159 | vma->vm->insert_entries(vma->vm, vma->obj->pages, vma->node.start, | |
160 | cache_level, pte_flags); | |
70b9f6f8 DV |
161 | |
162 | return 0; | |
47552659 DV |
163 | } |
164 | ||
165 | static void ppgtt_unbind_vma(struct i915_vma *vma) | |
166 | { | |
167 | vma->vm->clear_range(vma->vm, | |
168 | vma->node.start, | |
169 | vma->obj->base.size, | |
170 | true); | |
171 | } | |
6f65e29a | 172 | |
2c642b07 DV |
173 | static gen8_pte_t gen8_pte_encode(dma_addr_t addr, |
174 | enum i915_cache_level level, | |
175 | bool valid) | |
94ec8f61 | 176 | { |
07749ef3 | 177 | gen8_pte_t pte = valid ? _PAGE_PRESENT | _PAGE_RW : 0; |
94ec8f61 | 178 | pte |= addr; |
63c42e56 BW |
179 | |
180 | switch (level) { | |
181 | case I915_CACHE_NONE: | |
fbe5d36e | 182 | pte |= PPAT_UNCACHED_INDEX; |
63c42e56 BW |
183 | break; |
184 | case I915_CACHE_WT: | |
185 | pte |= PPAT_DISPLAY_ELLC_INDEX; | |
186 | break; | |
187 | default: | |
188 | pte |= PPAT_CACHED_INDEX; | |
189 | break; | |
190 | } | |
191 | ||
94ec8f61 BW |
192 | return pte; |
193 | } | |
194 | ||
fe36f55d MK |
195 | static gen8_pde_t gen8_pde_encode(const dma_addr_t addr, |
196 | const enum i915_cache_level level) | |
b1fe6673 | 197 | { |
07749ef3 | 198 | gen8_pde_t pde = _PAGE_PRESENT | _PAGE_RW; |
b1fe6673 BW |
199 | pde |= addr; |
200 | if (level != I915_CACHE_NONE) | |
201 | pde |= PPAT_CACHED_PDE_INDEX; | |
202 | else | |
203 | pde |= PPAT_UNCACHED_INDEX; | |
204 | return pde; | |
205 | } | |
206 | ||
07749ef3 MT |
207 | static gen6_pte_t snb_pte_encode(dma_addr_t addr, |
208 | enum i915_cache_level level, | |
209 | bool valid, u32 unused) | |
54d12527 | 210 | { |
07749ef3 | 211 | gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
54d12527 | 212 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
e7210c3c BW |
213 | |
214 | switch (level) { | |
350ec881 CW |
215 | case I915_CACHE_L3_LLC: |
216 | case I915_CACHE_LLC: | |
217 | pte |= GEN6_PTE_CACHE_LLC; | |
218 | break; | |
219 | case I915_CACHE_NONE: | |
220 | pte |= GEN6_PTE_UNCACHED; | |
221 | break; | |
222 | default: | |
5f77eeb0 | 223 | MISSING_CASE(level); |
350ec881 CW |
224 | } |
225 | ||
226 | return pte; | |
227 | } | |
228 | ||
07749ef3 MT |
229 | static gen6_pte_t ivb_pte_encode(dma_addr_t addr, |
230 | enum i915_cache_level level, | |
231 | bool valid, u32 unused) | |
350ec881 | 232 | { |
07749ef3 | 233 | gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
350ec881 CW |
234 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
235 | ||
236 | switch (level) { | |
237 | case I915_CACHE_L3_LLC: | |
238 | pte |= GEN7_PTE_CACHE_L3_LLC; | |
e7210c3c BW |
239 | break; |
240 | case I915_CACHE_LLC: | |
241 | pte |= GEN6_PTE_CACHE_LLC; | |
242 | break; | |
243 | case I915_CACHE_NONE: | |
9119708c | 244 | pte |= GEN6_PTE_UNCACHED; |
e7210c3c BW |
245 | break; |
246 | default: | |
5f77eeb0 | 247 | MISSING_CASE(level); |
e7210c3c BW |
248 | } |
249 | ||
54d12527 BW |
250 | return pte; |
251 | } | |
252 | ||
07749ef3 MT |
253 | static gen6_pte_t byt_pte_encode(dma_addr_t addr, |
254 | enum i915_cache_level level, | |
255 | bool valid, u32 flags) | |
93c34e70 | 256 | { |
07749ef3 | 257 | gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
93c34e70 KG |
258 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
259 | ||
24f3a8cf AG |
260 | if (!(flags & PTE_READ_ONLY)) |
261 | pte |= BYT_PTE_WRITEABLE; | |
93c34e70 KG |
262 | |
263 | if (level != I915_CACHE_NONE) | |
264 | pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES; | |
265 | ||
266 | return pte; | |
267 | } | |
268 | ||
07749ef3 MT |
269 | static gen6_pte_t hsw_pte_encode(dma_addr_t addr, |
270 | enum i915_cache_level level, | |
271 | bool valid, u32 unused) | |
9119708c | 272 | { |
07749ef3 | 273 | gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
0d8ff15e | 274 | pte |= HSW_PTE_ADDR_ENCODE(addr); |
9119708c KG |
275 | |
276 | if (level != I915_CACHE_NONE) | |
87a6b688 | 277 | pte |= HSW_WB_LLC_AGE3; |
9119708c KG |
278 | |
279 | return pte; | |
280 | } | |
281 | ||
07749ef3 MT |
282 | static gen6_pte_t iris_pte_encode(dma_addr_t addr, |
283 | enum i915_cache_level level, | |
284 | bool valid, u32 unused) | |
4d15c145 | 285 | { |
07749ef3 | 286 | gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
4d15c145 BW |
287 | pte |= HSW_PTE_ADDR_ENCODE(addr); |
288 | ||
651d794f CW |
289 | switch (level) { |
290 | case I915_CACHE_NONE: | |
291 | break; | |
292 | case I915_CACHE_WT: | |
c51e9701 | 293 | pte |= HSW_WT_ELLC_LLC_AGE3; |
651d794f CW |
294 | break; |
295 | default: | |
c51e9701 | 296 | pte |= HSW_WB_ELLC_LLC_AGE3; |
651d794f CW |
297 | break; |
298 | } | |
4d15c145 BW |
299 | |
300 | return pte; | |
301 | } | |
302 | ||
c114f76a MK |
303 | static int __setup_page_dma(struct drm_device *dev, |
304 | struct i915_page_dma *p, gfp_t flags) | |
678d96fb BW |
305 | { |
306 | struct device *device = &dev->pdev->dev; | |
307 | ||
c114f76a | 308 | p->page = alloc_page(flags); |
44159ddb MK |
309 | if (!p->page) |
310 | return -ENOMEM; | |
678d96fb | 311 | |
44159ddb MK |
312 | p->daddr = dma_map_page(device, |
313 | p->page, 0, 4096, PCI_DMA_BIDIRECTIONAL); | |
678d96fb | 314 | |
44159ddb MK |
315 | if (dma_mapping_error(device, p->daddr)) { |
316 | __free_page(p->page); | |
317 | return -EINVAL; | |
318 | } | |
1266cdb1 MT |
319 | |
320 | return 0; | |
678d96fb BW |
321 | } |
322 | ||
c114f76a MK |
323 | static int setup_page_dma(struct drm_device *dev, struct i915_page_dma *p) |
324 | { | |
325 | return __setup_page_dma(dev, p, GFP_KERNEL); | |
326 | } | |
327 | ||
44159ddb | 328 | static void cleanup_page_dma(struct drm_device *dev, struct i915_page_dma *p) |
06fda602 | 329 | { |
44159ddb | 330 | if (WARN_ON(!p->page)) |
06fda602 | 331 | return; |
678d96fb | 332 | |
44159ddb MK |
333 | dma_unmap_page(&dev->pdev->dev, p->daddr, 4096, PCI_DMA_BIDIRECTIONAL); |
334 | __free_page(p->page); | |
335 | memset(p, 0, sizeof(*p)); | |
336 | } | |
337 | ||
d1c54acd | 338 | static void *kmap_page_dma(struct i915_page_dma *p) |
73eeea53 | 339 | { |
d1c54acd MK |
340 | return kmap_atomic(p->page); |
341 | } | |
73eeea53 | 342 | |
d1c54acd MK |
343 | /* We use the flushing unmap only with ppgtt structures: |
344 | * page directories, page tables and scratch pages. | |
345 | */ | |
346 | static void kunmap_page_dma(struct drm_device *dev, void *vaddr) | |
347 | { | |
73eeea53 MK |
348 | /* There are only few exceptions for gen >=6. chv and bxt. |
349 | * And we are not sure about the latter so play safe for now. | |
350 | */ | |
351 | if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev)) | |
352 | drm_clflush_virt_range(vaddr, PAGE_SIZE); | |
353 | ||
354 | kunmap_atomic(vaddr); | |
355 | } | |
356 | ||
567047be | 357 | #define kmap_px(px) kmap_page_dma(px_base(px)) |
d1c54acd MK |
358 | #define kunmap_px(ppgtt, vaddr) kunmap_page_dma((ppgtt)->base.dev, (vaddr)) |
359 | ||
567047be MK |
360 | #define setup_px(dev, px) setup_page_dma((dev), px_base(px)) |
361 | #define cleanup_px(dev, px) cleanup_page_dma((dev), px_base(px)) | |
362 | #define fill_px(dev, px, v) fill_page_dma((dev), px_base(px), (v)) | |
363 | #define fill32_px(dev, px, v) fill_page_dma_32((dev), px_base(px), (v)) | |
364 | ||
d1c54acd MK |
365 | static void fill_page_dma(struct drm_device *dev, struct i915_page_dma *p, |
366 | const uint64_t val) | |
367 | { | |
368 | int i; | |
369 | uint64_t * const vaddr = kmap_page_dma(p); | |
370 | ||
371 | for (i = 0; i < 512; i++) | |
372 | vaddr[i] = val; | |
373 | ||
374 | kunmap_page_dma(dev, vaddr); | |
375 | } | |
376 | ||
73eeea53 MK |
377 | static void fill_page_dma_32(struct drm_device *dev, struct i915_page_dma *p, |
378 | const uint32_t val32) | |
379 | { | |
380 | uint64_t v = val32; | |
381 | ||
382 | v = v << 32 | val32; | |
383 | ||
384 | fill_page_dma(dev, p, v); | |
385 | } | |
386 | ||
4ad2af1e MK |
387 | static struct i915_page_scratch *alloc_scratch_page(struct drm_device *dev) |
388 | { | |
389 | struct i915_page_scratch *sp; | |
390 | int ret; | |
391 | ||
392 | sp = kzalloc(sizeof(*sp), GFP_KERNEL); | |
393 | if (sp == NULL) | |
394 | return ERR_PTR(-ENOMEM); | |
395 | ||
396 | ret = __setup_page_dma(dev, px_base(sp), GFP_DMA32 | __GFP_ZERO); | |
397 | if (ret) { | |
398 | kfree(sp); | |
399 | return ERR_PTR(ret); | |
400 | } | |
401 | ||
402 | set_pages_uc(px_page(sp), 1); | |
403 | ||
404 | return sp; | |
405 | } | |
406 | ||
407 | static void free_scratch_page(struct drm_device *dev, | |
408 | struct i915_page_scratch *sp) | |
409 | { | |
410 | set_pages_wb(px_page(sp), 1); | |
411 | ||
412 | cleanup_px(dev, sp); | |
413 | kfree(sp); | |
414 | } | |
415 | ||
8a1ebd74 | 416 | static struct i915_page_table *alloc_pt(struct drm_device *dev) |
06fda602 | 417 | { |
ec565b3c | 418 | struct i915_page_table *pt; |
678d96fb BW |
419 | const size_t count = INTEL_INFO(dev)->gen >= 8 ? |
420 | GEN8_PTES : GEN6_PTES; | |
421 | int ret = -ENOMEM; | |
06fda602 BW |
422 | |
423 | pt = kzalloc(sizeof(*pt), GFP_KERNEL); | |
424 | if (!pt) | |
425 | return ERR_PTR(-ENOMEM); | |
426 | ||
678d96fb BW |
427 | pt->used_ptes = kcalloc(BITS_TO_LONGS(count), sizeof(*pt->used_ptes), |
428 | GFP_KERNEL); | |
429 | ||
430 | if (!pt->used_ptes) | |
431 | goto fail_bitmap; | |
432 | ||
567047be | 433 | ret = setup_px(dev, pt); |
678d96fb | 434 | if (ret) |
44159ddb | 435 | goto fail_page_m; |
06fda602 BW |
436 | |
437 | return pt; | |
678d96fb | 438 | |
44159ddb | 439 | fail_page_m: |
678d96fb BW |
440 | kfree(pt->used_ptes); |
441 | fail_bitmap: | |
442 | kfree(pt); | |
443 | ||
444 | return ERR_PTR(ret); | |
06fda602 BW |
445 | } |
446 | ||
2e906bea | 447 | static void free_pt(struct drm_device *dev, struct i915_page_table *pt) |
06fda602 | 448 | { |
2e906bea MK |
449 | cleanup_px(dev, pt); |
450 | kfree(pt->used_ptes); | |
451 | kfree(pt); | |
452 | } | |
453 | ||
454 | static void gen8_initialize_pt(struct i915_address_space *vm, | |
455 | struct i915_page_table *pt) | |
456 | { | |
457 | gen8_pte_t scratch_pte; | |
458 | ||
459 | scratch_pte = gen8_pte_encode(px_dma(vm->scratch_page), | |
460 | I915_CACHE_LLC, true); | |
461 | ||
462 | fill_px(vm->dev, pt, scratch_pte); | |
463 | } | |
464 | ||
465 | static void gen6_initialize_pt(struct i915_address_space *vm, | |
466 | struct i915_page_table *pt) | |
467 | { | |
468 | gen6_pte_t scratch_pte; | |
469 | ||
470 | WARN_ON(px_dma(vm->scratch_page) == 0); | |
471 | ||
472 | scratch_pte = vm->pte_encode(px_dma(vm->scratch_page), | |
473 | I915_CACHE_LLC, true, 0); | |
474 | ||
475 | fill32_px(vm->dev, pt, scratch_pte); | |
06fda602 BW |
476 | } |
477 | ||
8a1ebd74 | 478 | static struct i915_page_directory *alloc_pd(struct drm_device *dev) |
06fda602 | 479 | { |
ec565b3c | 480 | struct i915_page_directory *pd; |
33c8819f | 481 | int ret = -ENOMEM; |
06fda602 BW |
482 | |
483 | pd = kzalloc(sizeof(*pd), GFP_KERNEL); | |
484 | if (!pd) | |
485 | return ERR_PTR(-ENOMEM); | |
486 | ||
33c8819f MT |
487 | pd->used_pdes = kcalloc(BITS_TO_LONGS(I915_PDES), |
488 | sizeof(*pd->used_pdes), GFP_KERNEL); | |
489 | if (!pd->used_pdes) | |
a08e111a | 490 | goto fail_bitmap; |
33c8819f | 491 | |
567047be | 492 | ret = setup_px(dev, pd); |
33c8819f | 493 | if (ret) |
a08e111a | 494 | goto fail_page_m; |
e5815a2e | 495 | |
06fda602 | 496 | return pd; |
33c8819f | 497 | |
a08e111a | 498 | fail_page_m: |
33c8819f | 499 | kfree(pd->used_pdes); |
a08e111a | 500 | fail_bitmap: |
33c8819f MT |
501 | kfree(pd); |
502 | ||
503 | return ERR_PTR(ret); | |
06fda602 BW |
504 | } |
505 | ||
2e906bea MK |
506 | static void free_pd(struct drm_device *dev, struct i915_page_directory *pd) |
507 | { | |
508 | if (px_page(pd)) { | |
509 | cleanup_px(dev, pd); | |
510 | kfree(pd->used_pdes); | |
511 | kfree(pd); | |
512 | } | |
513 | } | |
514 | ||
515 | static void gen8_initialize_pd(struct i915_address_space *vm, | |
516 | struct i915_page_directory *pd) | |
517 | { | |
518 | gen8_pde_t scratch_pde; | |
519 | ||
520 | scratch_pde = gen8_pde_encode(px_dma(vm->scratch_pt), I915_CACHE_LLC); | |
521 | ||
522 | fill_px(vm->dev, pd, scratch_pde); | |
523 | } | |
524 | ||
94e409c1 | 525 | /* Broadwell Page Directory Pointer Descriptors */ |
e85b26dc | 526 | static int gen8_write_pdp(struct drm_i915_gem_request *req, |
7cb6d7ac MT |
527 | unsigned entry, |
528 | dma_addr_t addr) | |
94e409c1 | 529 | { |
e85b26dc | 530 | struct intel_engine_cs *ring = req->ring; |
94e409c1 BW |
531 | int ret; |
532 | ||
533 | BUG_ON(entry >= 4); | |
534 | ||
5fb9de1a | 535 | ret = intel_ring_begin(req, 6); |
94e409c1 BW |
536 | if (ret) |
537 | return ret; | |
538 | ||
539 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
540 | intel_ring_emit(ring, GEN8_RING_PDP_UDW(ring, entry)); | |
7cb6d7ac | 541 | intel_ring_emit(ring, upper_32_bits(addr)); |
94e409c1 BW |
542 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); |
543 | intel_ring_emit(ring, GEN8_RING_PDP_LDW(ring, entry)); | |
7cb6d7ac | 544 | intel_ring_emit(ring, lower_32_bits(addr)); |
94e409c1 BW |
545 | intel_ring_advance(ring); |
546 | ||
547 | return 0; | |
548 | } | |
549 | ||
eeb9488e | 550 | static int gen8_mm_switch(struct i915_hw_ppgtt *ppgtt, |
e85b26dc | 551 | struct drm_i915_gem_request *req) |
94e409c1 | 552 | { |
eeb9488e | 553 | int i, ret; |
94e409c1 | 554 | |
7cb6d7ac | 555 | for (i = GEN8_LEGACY_PDPES - 1; i >= 0; i--) { |
d852c7bf MK |
556 | const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i); |
557 | ||
e85b26dc | 558 | ret = gen8_write_pdp(req, i, pd_daddr); |
eeb9488e BW |
559 | if (ret) |
560 | return ret; | |
94e409c1 | 561 | } |
d595bd4b | 562 | |
eeb9488e | 563 | return 0; |
94e409c1 BW |
564 | } |
565 | ||
459108b8 | 566 | static void gen8_ppgtt_clear_range(struct i915_address_space *vm, |
782f1495 BW |
567 | uint64_t start, |
568 | uint64_t length, | |
459108b8 BW |
569 | bool use_scratch) |
570 | { | |
571 | struct i915_hw_ppgtt *ppgtt = | |
572 | container_of(vm, struct i915_hw_ppgtt, base); | |
07749ef3 | 573 | gen8_pte_t *pt_vaddr, scratch_pte; |
7ad47cf2 BW |
574 | unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK; |
575 | unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK; | |
576 | unsigned pte = start >> GEN8_PTE_SHIFT & GEN8_PTE_MASK; | |
782f1495 | 577 | unsigned num_entries = length >> PAGE_SHIFT; |
459108b8 BW |
578 | unsigned last_pte, i; |
579 | ||
c114f76a | 580 | scratch_pte = gen8_pte_encode(px_dma(ppgtt->base.scratch_page), |
459108b8 BW |
581 | I915_CACHE_LLC, use_scratch); |
582 | ||
583 | while (num_entries) { | |
ec565b3c MT |
584 | struct i915_page_directory *pd; |
585 | struct i915_page_table *pt; | |
06fda602 BW |
586 | |
587 | if (WARN_ON(!ppgtt->pdp.page_directory[pdpe])) | |
00245266 | 588 | break; |
06fda602 BW |
589 | |
590 | pd = ppgtt->pdp.page_directory[pdpe]; | |
591 | ||
592 | if (WARN_ON(!pd->page_table[pde])) | |
00245266 | 593 | break; |
06fda602 BW |
594 | |
595 | pt = pd->page_table[pde]; | |
596 | ||
567047be | 597 | if (WARN_ON(!px_page(pt))) |
00245266 | 598 | break; |
06fda602 | 599 | |
7ad47cf2 | 600 | last_pte = pte + num_entries; |
07749ef3 MT |
601 | if (last_pte > GEN8_PTES) |
602 | last_pte = GEN8_PTES; | |
459108b8 | 603 | |
d1c54acd | 604 | pt_vaddr = kmap_px(pt); |
459108b8 | 605 | |
7ad47cf2 | 606 | for (i = pte; i < last_pte; i++) { |
459108b8 | 607 | pt_vaddr[i] = scratch_pte; |
7ad47cf2 BW |
608 | num_entries--; |
609 | } | |
459108b8 | 610 | |
d1c54acd | 611 | kunmap_px(ppgtt, pt); |
459108b8 | 612 | |
7ad47cf2 | 613 | pte = 0; |
07749ef3 | 614 | if (++pde == I915_PDES) { |
7ad47cf2 BW |
615 | pdpe++; |
616 | pde = 0; | |
617 | } | |
459108b8 BW |
618 | } |
619 | } | |
620 | ||
9df15b49 BW |
621 | static void gen8_ppgtt_insert_entries(struct i915_address_space *vm, |
622 | struct sg_table *pages, | |
782f1495 | 623 | uint64_t start, |
24f3a8cf | 624 | enum i915_cache_level cache_level, u32 unused) |
9df15b49 BW |
625 | { |
626 | struct i915_hw_ppgtt *ppgtt = | |
627 | container_of(vm, struct i915_hw_ppgtt, base); | |
07749ef3 | 628 | gen8_pte_t *pt_vaddr; |
7ad47cf2 BW |
629 | unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK; |
630 | unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK; | |
631 | unsigned pte = start >> GEN8_PTE_SHIFT & GEN8_PTE_MASK; | |
9df15b49 BW |
632 | struct sg_page_iter sg_iter; |
633 | ||
6f1cc993 | 634 | pt_vaddr = NULL; |
7ad47cf2 | 635 | |
9df15b49 | 636 | for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) { |
76643600 | 637 | if (WARN_ON(pdpe >= GEN8_LEGACY_PDPES)) |
7ad47cf2 BW |
638 | break; |
639 | ||
d7b3de91 | 640 | if (pt_vaddr == NULL) { |
ec565b3c MT |
641 | struct i915_page_directory *pd = ppgtt->pdp.page_directory[pdpe]; |
642 | struct i915_page_table *pt = pd->page_table[pde]; | |
d1c54acd | 643 | pt_vaddr = kmap_px(pt); |
d7b3de91 | 644 | } |
9df15b49 | 645 | |
7ad47cf2 | 646 | pt_vaddr[pte] = |
6f1cc993 CW |
647 | gen8_pte_encode(sg_page_iter_dma_address(&sg_iter), |
648 | cache_level, true); | |
07749ef3 | 649 | if (++pte == GEN8_PTES) { |
d1c54acd | 650 | kunmap_px(ppgtt, pt_vaddr); |
6f1cc993 | 651 | pt_vaddr = NULL; |
07749ef3 | 652 | if (++pde == I915_PDES) { |
7ad47cf2 BW |
653 | pdpe++; |
654 | pde = 0; | |
655 | } | |
656 | pte = 0; | |
9df15b49 BW |
657 | } |
658 | } | |
d1c54acd MK |
659 | |
660 | if (pt_vaddr) | |
661 | kunmap_px(ppgtt, pt_vaddr); | |
9df15b49 BW |
662 | } |
663 | ||
f37c0505 MT |
664 | static void gen8_free_page_tables(struct drm_device *dev, |
665 | struct i915_page_directory *pd) | |
7ad47cf2 BW |
666 | { |
667 | int i; | |
668 | ||
567047be | 669 | if (!px_page(pd)) |
7ad47cf2 BW |
670 | return; |
671 | ||
33c8819f | 672 | for_each_set_bit(i, pd->used_pdes, I915_PDES) { |
06fda602 BW |
673 | if (WARN_ON(!pd->page_table[i])) |
674 | continue; | |
7ad47cf2 | 675 | |
a08e111a | 676 | free_pt(dev, pd->page_table[i]); |
06fda602 BW |
677 | pd->page_table[i] = NULL; |
678 | } | |
d7b3de91 BW |
679 | } |
680 | ||
8776f02b MK |
681 | static int gen8_init_scratch(struct i915_address_space *vm) |
682 | { | |
683 | struct drm_device *dev = vm->dev; | |
684 | ||
685 | vm->scratch_page = alloc_scratch_page(dev); | |
686 | if (IS_ERR(vm->scratch_page)) | |
687 | return PTR_ERR(vm->scratch_page); | |
688 | ||
689 | vm->scratch_pt = alloc_pt(dev); | |
690 | if (IS_ERR(vm->scratch_pt)) { | |
691 | free_scratch_page(dev, vm->scratch_page); | |
692 | return PTR_ERR(vm->scratch_pt); | |
693 | } | |
694 | ||
695 | vm->scratch_pd = alloc_pd(dev); | |
696 | if (IS_ERR(vm->scratch_pd)) { | |
697 | free_pt(dev, vm->scratch_pt); | |
698 | free_scratch_page(dev, vm->scratch_page); | |
699 | return PTR_ERR(vm->scratch_pd); | |
700 | } | |
701 | ||
702 | gen8_initialize_pt(vm, vm->scratch_pt); | |
703 | gen8_initialize_pd(vm, vm->scratch_pd); | |
704 | ||
705 | return 0; | |
706 | } | |
707 | ||
708 | static void gen8_free_scratch(struct i915_address_space *vm) | |
709 | { | |
710 | struct drm_device *dev = vm->dev; | |
711 | ||
712 | free_pd(dev, vm->scratch_pd); | |
713 | free_pt(dev, vm->scratch_pt); | |
714 | free_scratch_page(dev, vm->scratch_page); | |
715 | } | |
716 | ||
061dd493 | 717 | static void gen8_ppgtt_cleanup(struct i915_address_space *vm) |
b45a6715 | 718 | { |
061dd493 DV |
719 | struct i915_hw_ppgtt *ppgtt = |
720 | container_of(vm, struct i915_hw_ppgtt, base); | |
b45a6715 BW |
721 | int i; |
722 | ||
33c8819f | 723 | for_each_set_bit(i, ppgtt->pdp.used_pdpes, GEN8_LEGACY_PDPES) { |
06fda602 BW |
724 | if (WARN_ON(!ppgtt->pdp.page_directory[i])) |
725 | continue; | |
726 | ||
f37c0505 MT |
727 | gen8_free_page_tables(ppgtt->base.dev, |
728 | ppgtt->pdp.page_directory[i]); | |
a08e111a | 729 | free_pd(ppgtt->base.dev, ppgtt->pdp.page_directory[i]); |
7ad47cf2 | 730 | } |
69876bed | 731 | |
8776f02b | 732 | gen8_free_scratch(vm); |
b45a6715 BW |
733 | } |
734 | ||
d7b2633d MT |
735 | /** |
736 | * gen8_ppgtt_alloc_pagetabs() - Allocate page tables for VA range. | |
737 | * @ppgtt: Master ppgtt structure. | |
738 | * @pd: Page directory for this address range. | |
739 | * @start: Starting virtual address to begin allocations. | |
740 | * @length Size of the allocations. | |
741 | * @new_pts: Bitmap set by function with new allocations. Likely used by the | |
742 | * caller to free on error. | |
743 | * | |
744 | * Allocate the required number of page tables. Extremely similar to | |
745 | * gen8_ppgtt_alloc_page_directories(). The main difference is here we are limited by | |
746 | * the page directory boundary (instead of the page directory pointer). That | |
747 | * boundary is 1GB virtual. Therefore, unlike gen8_ppgtt_alloc_page_directories(), it is | |
748 | * possible, and likely that the caller will need to use multiple calls of this | |
749 | * function to achieve the appropriate allocation. | |
750 | * | |
751 | * Return: 0 if success; negative error code otherwise. | |
752 | */ | |
e5815a2e MT |
753 | static int gen8_ppgtt_alloc_pagetabs(struct i915_hw_ppgtt *ppgtt, |
754 | struct i915_page_directory *pd, | |
5441f0cb | 755 | uint64_t start, |
d7b2633d MT |
756 | uint64_t length, |
757 | unsigned long *new_pts) | |
bf2b4ed2 | 758 | { |
e5815a2e | 759 | struct drm_device *dev = ppgtt->base.dev; |
d7b2633d | 760 | struct i915_page_table *pt; |
5441f0cb MT |
761 | uint64_t temp; |
762 | uint32_t pde; | |
bf2b4ed2 | 763 | |
d7b2633d MT |
764 | gen8_for_each_pde(pt, pd, start, length, temp, pde) { |
765 | /* Don't reallocate page tables */ | |
766 | if (pt) { | |
767 | /* Scratch is never allocated this way */ | |
79ab9370 | 768 | WARN_ON(pt == ppgtt->base.scratch_pt); |
d7b2633d MT |
769 | continue; |
770 | } | |
771 | ||
8a1ebd74 | 772 | pt = alloc_pt(dev); |
d7b2633d | 773 | if (IS_ERR(pt)) |
5441f0cb MT |
774 | goto unwind_out; |
775 | ||
d7b2633d MT |
776 | gen8_initialize_pt(&ppgtt->base, pt); |
777 | pd->page_table[pde] = pt; | |
966082c9 | 778 | __set_bit(pde, new_pts); |
7ad47cf2 BW |
779 | } |
780 | ||
bf2b4ed2 | 781 | return 0; |
7ad47cf2 BW |
782 | |
783 | unwind_out: | |
d7b2633d | 784 | for_each_set_bit(pde, new_pts, I915_PDES) |
a08e111a | 785 | free_pt(dev, pd->page_table[pde]); |
7ad47cf2 | 786 | |
d7b3de91 | 787 | return -ENOMEM; |
bf2b4ed2 BW |
788 | } |
789 | ||
d7b2633d MT |
790 | /** |
791 | * gen8_ppgtt_alloc_page_directories() - Allocate page directories for VA range. | |
792 | * @ppgtt: Master ppgtt structure. | |
793 | * @pdp: Page directory pointer for this address range. | |
794 | * @start: Starting virtual address to begin allocations. | |
795 | * @length Size of the allocations. | |
796 | * @new_pds Bitmap set by function with new allocations. Likely used by the | |
797 | * caller to free on error. | |
798 | * | |
799 | * Allocate the required number of page directories starting at the pde index of | |
800 | * @start, and ending at the pde index @start + @length. This function will skip | |
801 | * over already allocated page directories within the range, and only allocate | |
802 | * new ones, setting the appropriate pointer within the pdp as well as the | |
803 | * correct position in the bitmap @new_pds. | |
804 | * | |
805 | * The function will only allocate the pages within the range for a give page | |
806 | * directory pointer. In other words, if @start + @length straddles a virtually | |
807 | * addressed PDP boundary (512GB for 4k pages), there will be more allocations | |
808 | * required by the caller, This is not currently possible, and the BUG in the | |
809 | * code will prevent it. | |
810 | * | |
811 | * Return: 0 if success; negative error code otherwise. | |
812 | */ | |
c488dbba MT |
813 | static int gen8_ppgtt_alloc_page_directories(struct i915_hw_ppgtt *ppgtt, |
814 | struct i915_page_directory_pointer *pdp, | |
69876bed | 815 | uint64_t start, |
d7b2633d MT |
816 | uint64_t length, |
817 | unsigned long *new_pds) | |
bf2b4ed2 | 818 | { |
e5815a2e | 819 | struct drm_device *dev = ppgtt->base.dev; |
d7b2633d | 820 | struct i915_page_directory *pd; |
69876bed MT |
821 | uint64_t temp; |
822 | uint32_t pdpe; | |
823 | ||
d7b2633d MT |
824 | WARN_ON(!bitmap_empty(new_pds, GEN8_LEGACY_PDPES)); |
825 | ||
d7b2633d MT |
826 | gen8_for_each_pdpe(pd, pdp, start, length, temp, pdpe) { |
827 | if (pd) | |
828 | continue; | |
33c8819f | 829 | |
8a1ebd74 | 830 | pd = alloc_pd(dev); |
d7b2633d | 831 | if (IS_ERR(pd)) |
d7b3de91 | 832 | goto unwind_out; |
69876bed | 833 | |
d7b2633d MT |
834 | gen8_initialize_pd(&ppgtt->base, pd); |
835 | pdp->page_directory[pdpe] = pd; | |
966082c9 | 836 | __set_bit(pdpe, new_pds); |
d7b3de91 BW |
837 | } |
838 | ||
bf2b4ed2 | 839 | return 0; |
d7b3de91 BW |
840 | |
841 | unwind_out: | |
d7b2633d | 842 | for_each_set_bit(pdpe, new_pds, GEN8_LEGACY_PDPES) |
a08e111a | 843 | free_pd(dev, pdp->page_directory[pdpe]); |
d7b3de91 BW |
844 | |
845 | return -ENOMEM; | |
bf2b4ed2 BW |
846 | } |
847 | ||
d7b2633d MT |
848 | static void |
849 | free_gen8_temp_bitmaps(unsigned long *new_pds, unsigned long **new_pts) | |
850 | { | |
851 | int i; | |
852 | ||
853 | for (i = 0; i < GEN8_LEGACY_PDPES; i++) | |
854 | kfree(new_pts[i]); | |
855 | kfree(new_pts); | |
856 | kfree(new_pds); | |
857 | } | |
858 | ||
859 | /* Fills in the page directory bitmap, and the array of page tables bitmap. Both | |
860 | * of these are based on the number of PDPEs in the system. | |
861 | */ | |
862 | static | |
863 | int __must_check alloc_gen8_temp_bitmaps(unsigned long **new_pds, | |
864 | unsigned long ***new_pts) | |
865 | { | |
866 | int i; | |
867 | unsigned long *pds; | |
868 | unsigned long **pts; | |
869 | ||
870 | pds = kcalloc(BITS_TO_LONGS(GEN8_LEGACY_PDPES), sizeof(unsigned long), GFP_KERNEL); | |
871 | if (!pds) | |
872 | return -ENOMEM; | |
873 | ||
874 | pts = kcalloc(GEN8_LEGACY_PDPES, sizeof(unsigned long *), GFP_KERNEL); | |
875 | if (!pts) { | |
876 | kfree(pds); | |
877 | return -ENOMEM; | |
878 | } | |
879 | ||
880 | for (i = 0; i < GEN8_LEGACY_PDPES; i++) { | |
881 | pts[i] = kcalloc(BITS_TO_LONGS(I915_PDES), | |
882 | sizeof(unsigned long), GFP_KERNEL); | |
883 | if (!pts[i]) | |
884 | goto err_out; | |
885 | } | |
886 | ||
887 | *new_pds = pds; | |
888 | *new_pts = pts; | |
889 | ||
890 | return 0; | |
891 | ||
892 | err_out: | |
893 | free_gen8_temp_bitmaps(pds, pts); | |
894 | return -ENOMEM; | |
895 | } | |
896 | ||
5b7e4c9c MK |
897 | /* PDE TLBs are a pain to invalidate on GEN8+. When we modify |
898 | * the page table structures, we mark them dirty so that | |
899 | * context switching/execlist queuing code takes extra steps | |
900 | * to ensure that tlbs are flushed. | |
901 | */ | |
902 | static void mark_tlbs_dirty(struct i915_hw_ppgtt *ppgtt) | |
903 | { | |
904 | ppgtt->pd_dirty_rings = INTEL_INFO(ppgtt->base.dev)->ring_mask; | |
905 | } | |
906 | ||
e5815a2e MT |
907 | static int gen8_alloc_va_range(struct i915_address_space *vm, |
908 | uint64_t start, | |
909 | uint64_t length) | |
bf2b4ed2 | 910 | { |
e5815a2e MT |
911 | struct i915_hw_ppgtt *ppgtt = |
912 | container_of(vm, struct i915_hw_ppgtt, base); | |
d7b2633d | 913 | unsigned long *new_page_dirs, **new_page_tables; |
5441f0cb | 914 | struct i915_page_directory *pd; |
33c8819f MT |
915 | const uint64_t orig_start = start; |
916 | const uint64_t orig_length = length; | |
5441f0cb MT |
917 | uint64_t temp; |
918 | uint32_t pdpe; | |
bf2b4ed2 BW |
919 | int ret; |
920 | ||
d7b2633d MT |
921 | /* Wrap is never okay since we can only represent 48b, and we don't |
922 | * actually use the other side of the canonical address space. | |
923 | */ | |
924 | if (WARN_ON(start + length < start)) | |
a05d80ee MK |
925 | return -ENODEV; |
926 | ||
927 | if (WARN_ON(start + length > ppgtt->base.total)) | |
928 | return -ENODEV; | |
d7b2633d MT |
929 | |
930 | ret = alloc_gen8_temp_bitmaps(&new_page_dirs, &new_page_tables); | |
bf2b4ed2 BW |
931 | if (ret) |
932 | return ret; | |
933 | ||
d7b2633d MT |
934 | /* Do the allocations first so we can easily bail out */ |
935 | ret = gen8_ppgtt_alloc_page_directories(ppgtt, &ppgtt->pdp, start, length, | |
936 | new_page_dirs); | |
937 | if (ret) { | |
938 | free_gen8_temp_bitmaps(new_page_dirs, new_page_tables); | |
939 | return ret; | |
940 | } | |
941 | ||
942 | /* For every page directory referenced, allocate page tables */ | |
5441f0cb | 943 | gen8_for_each_pdpe(pd, &ppgtt->pdp, start, length, temp, pdpe) { |
d7b2633d MT |
944 | ret = gen8_ppgtt_alloc_pagetabs(ppgtt, pd, start, length, |
945 | new_page_tables[pdpe]); | |
5441f0cb MT |
946 | if (ret) |
947 | goto err_out; | |
5441f0cb MT |
948 | } |
949 | ||
33c8819f MT |
950 | start = orig_start; |
951 | length = orig_length; | |
952 | ||
d7b2633d MT |
953 | /* Allocations have completed successfully, so set the bitmaps, and do |
954 | * the mappings. */ | |
33c8819f | 955 | gen8_for_each_pdpe(pd, &ppgtt->pdp, start, length, temp, pdpe) { |
d1c54acd | 956 | gen8_pde_t *const page_directory = kmap_px(pd); |
33c8819f | 957 | struct i915_page_table *pt; |
09120d4e | 958 | uint64_t pd_len = length; |
33c8819f MT |
959 | uint64_t pd_start = start; |
960 | uint32_t pde; | |
961 | ||
d7b2633d MT |
962 | /* Every pd should be allocated, we just did that above. */ |
963 | WARN_ON(!pd); | |
964 | ||
965 | gen8_for_each_pde(pt, pd, pd_start, pd_len, temp, pde) { | |
966 | /* Same reasoning as pd */ | |
967 | WARN_ON(!pt); | |
968 | WARN_ON(!pd_len); | |
969 | WARN_ON(!gen8_pte_count(pd_start, pd_len)); | |
970 | ||
971 | /* Set our used ptes within the page table */ | |
972 | bitmap_set(pt->used_ptes, | |
973 | gen8_pte_index(pd_start), | |
974 | gen8_pte_count(pd_start, pd_len)); | |
975 | ||
976 | /* Our pde is now pointing to the pagetable, pt */ | |
966082c9 | 977 | __set_bit(pde, pd->used_pdes); |
d7b2633d MT |
978 | |
979 | /* Map the PDE to the page table */ | |
fe36f55d MK |
980 | page_directory[pde] = gen8_pde_encode(px_dma(pt), |
981 | I915_CACHE_LLC); | |
d7b2633d MT |
982 | |
983 | /* NB: We haven't yet mapped ptes to pages. At this | |
984 | * point we're still relying on insert_entries() */ | |
33c8819f | 985 | } |
d7b2633d | 986 | |
d1c54acd | 987 | kunmap_px(ppgtt, page_directory); |
d7b2633d | 988 | |
966082c9 | 989 | __set_bit(pdpe, ppgtt->pdp.used_pdpes); |
33c8819f MT |
990 | } |
991 | ||
d7b2633d | 992 | free_gen8_temp_bitmaps(new_page_dirs, new_page_tables); |
5b7e4c9c | 993 | mark_tlbs_dirty(ppgtt); |
d7b3de91 | 994 | return 0; |
bf2b4ed2 | 995 | |
d7b3de91 | 996 | err_out: |
d7b2633d MT |
997 | while (pdpe--) { |
998 | for_each_set_bit(temp, new_page_tables[pdpe], I915_PDES) | |
a08e111a | 999 | free_pt(vm->dev, ppgtt->pdp.page_directory[pdpe]->page_table[temp]); |
d7b2633d MT |
1000 | } |
1001 | ||
1002 | for_each_set_bit(pdpe, new_page_dirs, GEN8_LEGACY_PDPES) | |
a08e111a | 1003 | free_pd(vm->dev, ppgtt->pdp.page_directory[pdpe]); |
d7b2633d MT |
1004 | |
1005 | free_gen8_temp_bitmaps(new_page_dirs, new_page_tables); | |
5b7e4c9c | 1006 | mark_tlbs_dirty(ppgtt); |
bf2b4ed2 BW |
1007 | return ret; |
1008 | } | |
1009 | ||
eb0b44ad | 1010 | /* |
f3a964b9 BW |
1011 | * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers |
1012 | * with a net effect resembling a 2-level page table in normal x86 terms. Each | |
1013 | * PDP represents 1GB of memory 4 * 512 * 512 * 4096 = 4GB legacy 32b address | |
1014 | * space. | |
37aca44a | 1015 | * |
f3a964b9 | 1016 | */ |
5c5f6457 | 1017 | static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt) |
37aca44a | 1018 | { |
8776f02b | 1019 | int ret; |
7cb6d7ac | 1020 | |
8776f02b MK |
1021 | ret = gen8_init_scratch(&ppgtt->base); |
1022 | if (ret) | |
1023 | return ret; | |
69876bed | 1024 | |
d7b2633d | 1025 | ppgtt->base.start = 0; |
5c5f6457 | 1026 | ppgtt->base.total = 1ULL << 32; |
501fd70f MT |
1027 | if (IS_ENABLED(CONFIG_X86_32)) |
1028 | /* While we have a proliferation of size_t variables | |
1029 | * we cannot represent the full ppgtt size on 32bit, | |
1030 | * so limit it to the same size as the GGTT (currently | |
1031 | * 2GiB). | |
1032 | */ | |
1033 | ppgtt->base.total = to_i915(ppgtt->base.dev)->gtt.base.total; | |
d7b2633d | 1034 | ppgtt->base.cleanup = gen8_ppgtt_cleanup; |
5c5f6457 | 1035 | ppgtt->base.allocate_va_range = gen8_alloc_va_range; |
d7b2633d | 1036 | ppgtt->base.insert_entries = gen8_ppgtt_insert_entries; |
c7e16f22 | 1037 | ppgtt->base.clear_range = gen8_ppgtt_clear_range; |
777dc5bb DV |
1038 | ppgtt->base.unbind_vma = ppgtt_unbind_vma; |
1039 | ppgtt->base.bind_vma = ppgtt_bind_vma; | |
d7b2633d MT |
1040 | |
1041 | ppgtt->switch_mm = gen8_mm_switch; | |
1042 | ||
1043 | return 0; | |
1044 | } | |
1045 | ||
87d60b63 BW |
1046 | static void gen6_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m) |
1047 | { | |
87d60b63 | 1048 | struct i915_address_space *vm = &ppgtt->base; |
09942c65 | 1049 | struct i915_page_table *unused; |
07749ef3 | 1050 | gen6_pte_t scratch_pte; |
87d60b63 | 1051 | uint32_t pd_entry; |
09942c65 MT |
1052 | uint32_t pte, pde, temp; |
1053 | uint32_t start = ppgtt->base.start, length = ppgtt->base.total; | |
87d60b63 | 1054 | |
79ab9370 MK |
1055 | scratch_pte = vm->pte_encode(px_dma(vm->scratch_page), |
1056 | I915_CACHE_LLC, true, 0); | |
87d60b63 | 1057 | |
09942c65 | 1058 | gen6_for_each_pde(unused, &ppgtt->pd, start, length, temp, pde) { |
87d60b63 | 1059 | u32 expected; |
07749ef3 | 1060 | gen6_pte_t *pt_vaddr; |
567047be | 1061 | const dma_addr_t pt_addr = px_dma(ppgtt->pd.page_table[pde]); |
09942c65 | 1062 | pd_entry = readl(ppgtt->pd_addr + pde); |
87d60b63 BW |
1063 | expected = (GEN6_PDE_ADDR_ENCODE(pt_addr) | GEN6_PDE_VALID); |
1064 | ||
1065 | if (pd_entry != expected) | |
1066 | seq_printf(m, "\tPDE #%d mismatch: Actual PDE: %x Expected PDE: %x\n", | |
1067 | pde, | |
1068 | pd_entry, | |
1069 | expected); | |
1070 | seq_printf(m, "\tPDE: %x\n", pd_entry); | |
1071 | ||
d1c54acd MK |
1072 | pt_vaddr = kmap_px(ppgtt->pd.page_table[pde]); |
1073 | ||
07749ef3 | 1074 | for (pte = 0; pte < GEN6_PTES; pte+=4) { |
87d60b63 | 1075 | unsigned long va = |
07749ef3 | 1076 | (pde * PAGE_SIZE * GEN6_PTES) + |
87d60b63 BW |
1077 | (pte * PAGE_SIZE); |
1078 | int i; | |
1079 | bool found = false; | |
1080 | for (i = 0; i < 4; i++) | |
1081 | if (pt_vaddr[pte + i] != scratch_pte) | |
1082 | found = true; | |
1083 | if (!found) | |
1084 | continue; | |
1085 | ||
1086 | seq_printf(m, "\t\t0x%lx [%03d,%04d]: =", va, pde, pte); | |
1087 | for (i = 0; i < 4; i++) { | |
1088 | if (pt_vaddr[pte + i] != scratch_pte) | |
1089 | seq_printf(m, " %08x", pt_vaddr[pte + i]); | |
1090 | else | |
1091 | seq_puts(m, " SCRATCH "); | |
1092 | } | |
1093 | seq_puts(m, "\n"); | |
1094 | } | |
d1c54acd | 1095 | kunmap_px(ppgtt, pt_vaddr); |
87d60b63 BW |
1096 | } |
1097 | } | |
1098 | ||
678d96fb | 1099 | /* Write pde (index) from the page directory @pd to the page table @pt */ |
ec565b3c MT |
1100 | static void gen6_write_pde(struct i915_page_directory *pd, |
1101 | const int pde, struct i915_page_table *pt) | |
6197349b | 1102 | { |
678d96fb BW |
1103 | /* Caller needs to make sure the write completes if necessary */ |
1104 | struct i915_hw_ppgtt *ppgtt = | |
1105 | container_of(pd, struct i915_hw_ppgtt, pd); | |
1106 | u32 pd_entry; | |
6197349b | 1107 | |
567047be | 1108 | pd_entry = GEN6_PDE_ADDR_ENCODE(px_dma(pt)); |
678d96fb | 1109 | pd_entry |= GEN6_PDE_VALID; |
6197349b | 1110 | |
678d96fb BW |
1111 | writel(pd_entry, ppgtt->pd_addr + pde); |
1112 | } | |
6197349b | 1113 | |
678d96fb BW |
1114 | /* Write all the page tables found in the ppgtt structure to incrementing page |
1115 | * directories. */ | |
1116 | static void gen6_write_page_range(struct drm_i915_private *dev_priv, | |
ec565b3c | 1117 | struct i915_page_directory *pd, |
678d96fb BW |
1118 | uint32_t start, uint32_t length) |
1119 | { | |
ec565b3c | 1120 | struct i915_page_table *pt; |
678d96fb BW |
1121 | uint32_t pde, temp; |
1122 | ||
1123 | gen6_for_each_pde(pt, pd, start, length, temp, pde) | |
1124 | gen6_write_pde(pd, pde, pt); | |
1125 | ||
1126 | /* Make sure write is complete before other code can use this page | |
1127 | * table. Also require for WC mapped PTEs */ | |
1128 | readl(dev_priv->gtt.gsm); | |
3e302542 BW |
1129 | } |
1130 | ||
b4a74e3a | 1131 | static uint32_t get_pd_offset(struct i915_hw_ppgtt *ppgtt) |
3e302542 | 1132 | { |
44159ddb | 1133 | BUG_ON(ppgtt->pd.base.ggtt_offset & 0x3f); |
b4a74e3a | 1134 | |
44159ddb | 1135 | return (ppgtt->pd.base.ggtt_offset / 64) << 16; |
b4a74e3a BW |
1136 | } |
1137 | ||
90252e5c | 1138 | static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt, |
e85b26dc | 1139 | struct drm_i915_gem_request *req) |
90252e5c | 1140 | { |
e85b26dc | 1141 | struct intel_engine_cs *ring = req->ring; |
90252e5c BW |
1142 | int ret; |
1143 | ||
90252e5c | 1144 | /* NB: TLBs must be flushed and invalidated before a switch */ |
a84c3ae1 | 1145 | ret = ring->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); |
90252e5c BW |
1146 | if (ret) |
1147 | return ret; | |
1148 | ||
5fb9de1a | 1149 | ret = intel_ring_begin(req, 6); |
90252e5c BW |
1150 | if (ret) |
1151 | return ret; | |
1152 | ||
1153 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2)); | |
1154 | intel_ring_emit(ring, RING_PP_DIR_DCLV(ring)); | |
1155 | intel_ring_emit(ring, PP_DIR_DCLV_2G); | |
1156 | intel_ring_emit(ring, RING_PP_DIR_BASE(ring)); | |
1157 | intel_ring_emit(ring, get_pd_offset(ppgtt)); | |
1158 | intel_ring_emit(ring, MI_NOOP); | |
1159 | intel_ring_advance(ring); | |
1160 | ||
1161 | return 0; | |
1162 | } | |
1163 | ||
71ba2d64 | 1164 | static int vgpu_mm_switch(struct i915_hw_ppgtt *ppgtt, |
e85b26dc | 1165 | struct drm_i915_gem_request *req) |
71ba2d64 | 1166 | { |
e85b26dc | 1167 | struct intel_engine_cs *ring = req->ring; |
71ba2d64 YZ |
1168 | struct drm_i915_private *dev_priv = to_i915(ppgtt->base.dev); |
1169 | ||
1170 | I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G); | |
1171 | I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt)); | |
1172 | return 0; | |
1173 | } | |
1174 | ||
48a10389 | 1175 | static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt, |
e85b26dc | 1176 | struct drm_i915_gem_request *req) |
48a10389 | 1177 | { |
e85b26dc | 1178 | struct intel_engine_cs *ring = req->ring; |
48a10389 BW |
1179 | int ret; |
1180 | ||
48a10389 | 1181 | /* NB: TLBs must be flushed and invalidated before a switch */ |
a84c3ae1 | 1182 | ret = ring->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); |
48a10389 BW |
1183 | if (ret) |
1184 | return ret; | |
1185 | ||
5fb9de1a | 1186 | ret = intel_ring_begin(req, 6); |
48a10389 BW |
1187 | if (ret) |
1188 | return ret; | |
1189 | ||
1190 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2)); | |
1191 | intel_ring_emit(ring, RING_PP_DIR_DCLV(ring)); | |
1192 | intel_ring_emit(ring, PP_DIR_DCLV_2G); | |
1193 | intel_ring_emit(ring, RING_PP_DIR_BASE(ring)); | |
1194 | intel_ring_emit(ring, get_pd_offset(ppgtt)); | |
1195 | intel_ring_emit(ring, MI_NOOP); | |
1196 | intel_ring_advance(ring); | |
1197 | ||
90252e5c BW |
1198 | /* XXX: RCS is the only one to auto invalidate the TLBs? */ |
1199 | if (ring->id != RCS) { | |
a84c3ae1 | 1200 | ret = ring->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); |
90252e5c BW |
1201 | if (ret) |
1202 | return ret; | |
1203 | } | |
1204 | ||
48a10389 BW |
1205 | return 0; |
1206 | } | |
1207 | ||
eeb9488e | 1208 | static int gen6_mm_switch(struct i915_hw_ppgtt *ppgtt, |
e85b26dc | 1209 | struct drm_i915_gem_request *req) |
eeb9488e | 1210 | { |
e85b26dc | 1211 | struct intel_engine_cs *ring = req->ring; |
eeb9488e BW |
1212 | struct drm_device *dev = ppgtt->base.dev; |
1213 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1214 | ||
48a10389 | 1215 | |
eeb9488e BW |
1216 | I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G); |
1217 | I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt)); | |
1218 | ||
1219 | POSTING_READ(RING_PP_DIR_DCLV(ring)); | |
1220 | ||
1221 | return 0; | |
1222 | } | |
1223 | ||
82460d97 | 1224 | static void gen8_ppgtt_enable(struct drm_device *dev) |
eeb9488e | 1225 | { |
eeb9488e | 1226 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 1227 | struct intel_engine_cs *ring; |
82460d97 | 1228 | int j; |
3e302542 | 1229 | |
eeb9488e BW |
1230 | for_each_ring(ring, dev_priv, j) { |
1231 | I915_WRITE(RING_MODE_GEN7(ring), | |
1232 | _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
eeb9488e | 1233 | } |
eeb9488e | 1234 | } |
6197349b | 1235 | |
82460d97 | 1236 | static void gen7_ppgtt_enable(struct drm_device *dev) |
3e302542 | 1237 | { |
50227e1c | 1238 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 1239 | struct intel_engine_cs *ring; |
b4a74e3a | 1240 | uint32_t ecochk, ecobits; |
3e302542 | 1241 | int i; |
6197349b | 1242 | |
b4a74e3a BW |
1243 | ecobits = I915_READ(GAC_ECO_BITS); |
1244 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B); | |
a65c2fcd | 1245 | |
b4a74e3a BW |
1246 | ecochk = I915_READ(GAM_ECOCHK); |
1247 | if (IS_HASWELL(dev)) { | |
1248 | ecochk |= ECOCHK_PPGTT_WB_HSW; | |
1249 | } else { | |
1250 | ecochk |= ECOCHK_PPGTT_LLC_IVB; | |
1251 | ecochk &= ~ECOCHK_PPGTT_GFDT_IVB; | |
1252 | } | |
1253 | I915_WRITE(GAM_ECOCHK, ecochk); | |
a65c2fcd | 1254 | |
b4a74e3a | 1255 | for_each_ring(ring, dev_priv, i) { |
6197349b | 1256 | /* GFX_MODE is per-ring on gen7+ */ |
b4a74e3a BW |
1257 | I915_WRITE(RING_MODE_GEN7(ring), |
1258 | _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
6197349b | 1259 | } |
b4a74e3a | 1260 | } |
6197349b | 1261 | |
82460d97 | 1262 | static void gen6_ppgtt_enable(struct drm_device *dev) |
b4a74e3a | 1263 | { |
50227e1c | 1264 | struct drm_i915_private *dev_priv = dev->dev_private; |
b4a74e3a | 1265 | uint32_t ecochk, gab_ctl, ecobits; |
a65c2fcd | 1266 | |
b4a74e3a BW |
1267 | ecobits = I915_READ(GAC_ECO_BITS); |
1268 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT | | |
1269 | ECOBITS_PPGTT_CACHE64B); | |
6197349b | 1270 | |
b4a74e3a BW |
1271 | gab_ctl = I915_READ(GAB_CTL); |
1272 | I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT); | |
1273 | ||
1274 | ecochk = I915_READ(GAM_ECOCHK); | |
1275 | I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B); | |
1276 | ||
1277 | I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
6197349b BW |
1278 | } |
1279 | ||
1d2a314c | 1280 | /* PPGTT support for Sandybdrige/Gen6 and later */ |
853ba5d2 | 1281 | static void gen6_ppgtt_clear_range(struct i915_address_space *vm, |
782f1495 BW |
1282 | uint64_t start, |
1283 | uint64_t length, | |
828c7908 | 1284 | bool use_scratch) |
1d2a314c | 1285 | { |
853ba5d2 BW |
1286 | struct i915_hw_ppgtt *ppgtt = |
1287 | container_of(vm, struct i915_hw_ppgtt, base); | |
07749ef3 | 1288 | gen6_pte_t *pt_vaddr, scratch_pte; |
782f1495 BW |
1289 | unsigned first_entry = start >> PAGE_SHIFT; |
1290 | unsigned num_entries = length >> PAGE_SHIFT; | |
07749ef3 MT |
1291 | unsigned act_pt = first_entry / GEN6_PTES; |
1292 | unsigned first_pte = first_entry % GEN6_PTES; | |
7bddb01f | 1293 | unsigned last_pte, i; |
1d2a314c | 1294 | |
c114f76a MK |
1295 | scratch_pte = vm->pte_encode(px_dma(vm->scratch_page), |
1296 | I915_CACHE_LLC, true, 0); | |
1d2a314c | 1297 | |
7bddb01f DV |
1298 | while (num_entries) { |
1299 | last_pte = first_pte + num_entries; | |
07749ef3 MT |
1300 | if (last_pte > GEN6_PTES) |
1301 | last_pte = GEN6_PTES; | |
7bddb01f | 1302 | |
d1c54acd | 1303 | pt_vaddr = kmap_px(ppgtt->pd.page_table[act_pt]); |
1d2a314c | 1304 | |
7bddb01f DV |
1305 | for (i = first_pte; i < last_pte; i++) |
1306 | pt_vaddr[i] = scratch_pte; | |
1d2a314c | 1307 | |
d1c54acd | 1308 | kunmap_px(ppgtt, pt_vaddr); |
1d2a314c | 1309 | |
7bddb01f DV |
1310 | num_entries -= last_pte - first_pte; |
1311 | first_pte = 0; | |
a15326a5 | 1312 | act_pt++; |
7bddb01f | 1313 | } |
1d2a314c DV |
1314 | } |
1315 | ||
853ba5d2 | 1316 | static void gen6_ppgtt_insert_entries(struct i915_address_space *vm, |
def886c3 | 1317 | struct sg_table *pages, |
782f1495 | 1318 | uint64_t start, |
24f3a8cf | 1319 | enum i915_cache_level cache_level, u32 flags) |
def886c3 | 1320 | { |
853ba5d2 BW |
1321 | struct i915_hw_ppgtt *ppgtt = |
1322 | container_of(vm, struct i915_hw_ppgtt, base); | |
07749ef3 | 1323 | gen6_pte_t *pt_vaddr; |
782f1495 | 1324 | unsigned first_entry = start >> PAGE_SHIFT; |
07749ef3 MT |
1325 | unsigned act_pt = first_entry / GEN6_PTES; |
1326 | unsigned act_pte = first_entry % GEN6_PTES; | |
6e995e23 ID |
1327 | struct sg_page_iter sg_iter; |
1328 | ||
cc79714f | 1329 | pt_vaddr = NULL; |
6e995e23 | 1330 | for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) { |
cc79714f | 1331 | if (pt_vaddr == NULL) |
d1c54acd | 1332 | pt_vaddr = kmap_px(ppgtt->pd.page_table[act_pt]); |
6e995e23 | 1333 | |
cc79714f CW |
1334 | pt_vaddr[act_pte] = |
1335 | vm->pte_encode(sg_page_iter_dma_address(&sg_iter), | |
24f3a8cf AG |
1336 | cache_level, true, flags); |
1337 | ||
07749ef3 | 1338 | if (++act_pte == GEN6_PTES) { |
d1c54acd | 1339 | kunmap_px(ppgtt, pt_vaddr); |
cc79714f | 1340 | pt_vaddr = NULL; |
a15326a5 | 1341 | act_pt++; |
6e995e23 | 1342 | act_pte = 0; |
def886c3 | 1343 | } |
def886c3 | 1344 | } |
cc79714f | 1345 | if (pt_vaddr) |
d1c54acd | 1346 | kunmap_px(ppgtt, pt_vaddr); |
def886c3 DV |
1347 | } |
1348 | ||
678d96fb | 1349 | static int gen6_alloc_va_range(struct i915_address_space *vm, |
a05d80ee | 1350 | uint64_t start_in, uint64_t length_in) |
678d96fb | 1351 | { |
4933d519 MT |
1352 | DECLARE_BITMAP(new_page_tables, I915_PDES); |
1353 | struct drm_device *dev = vm->dev; | |
1354 | struct drm_i915_private *dev_priv = dev->dev_private; | |
678d96fb BW |
1355 | struct i915_hw_ppgtt *ppgtt = |
1356 | container_of(vm, struct i915_hw_ppgtt, base); | |
ec565b3c | 1357 | struct i915_page_table *pt; |
a05d80ee | 1358 | uint32_t start, length, start_save, length_save; |
678d96fb | 1359 | uint32_t pde, temp; |
4933d519 MT |
1360 | int ret; |
1361 | ||
a05d80ee MK |
1362 | if (WARN_ON(start_in + length_in > ppgtt->base.total)) |
1363 | return -ENODEV; | |
1364 | ||
1365 | start = start_save = start_in; | |
1366 | length = length_save = length_in; | |
4933d519 MT |
1367 | |
1368 | bitmap_zero(new_page_tables, I915_PDES); | |
1369 | ||
1370 | /* The allocation is done in two stages so that we can bail out with | |
1371 | * minimal amount of pain. The first stage finds new page tables that | |
1372 | * need allocation. The second stage marks use ptes within the page | |
1373 | * tables. | |
1374 | */ | |
1375 | gen6_for_each_pde(pt, &ppgtt->pd, start, length, temp, pde) { | |
79ab9370 | 1376 | if (pt != vm->scratch_pt) { |
4933d519 MT |
1377 | WARN_ON(bitmap_empty(pt->used_ptes, GEN6_PTES)); |
1378 | continue; | |
1379 | } | |
1380 | ||
1381 | /* We've already allocated a page table */ | |
1382 | WARN_ON(!bitmap_empty(pt->used_ptes, GEN6_PTES)); | |
1383 | ||
8a1ebd74 | 1384 | pt = alloc_pt(dev); |
4933d519 MT |
1385 | if (IS_ERR(pt)) { |
1386 | ret = PTR_ERR(pt); | |
1387 | goto unwind_out; | |
1388 | } | |
1389 | ||
1390 | gen6_initialize_pt(vm, pt); | |
1391 | ||
1392 | ppgtt->pd.page_table[pde] = pt; | |
966082c9 | 1393 | __set_bit(pde, new_page_tables); |
72744cb1 | 1394 | trace_i915_page_table_entry_alloc(vm, pde, start, GEN6_PDE_SHIFT); |
4933d519 MT |
1395 | } |
1396 | ||
1397 | start = start_save; | |
1398 | length = length_save; | |
678d96fb BW |
1399 | |
1400 | gen6_for_each_pde(pt, &ppgtt->pd, start, length, temp, pde) { | |
1401 | DECLARE_BITMAP(tmp_bitmap, GEN6_PTES); | |
1402 | ||
1403 | bitmap_zero(tmp_bitmap, GEN6_PTES); | |
1404 | bitmap_set(tmp_bitmap, gen6_pte_index(start), | |
1405 | gen6_pte_count(start, length)); | |
1406 | ||
966082c9 | 1407 | if (__test_and_clear_bit(pde, new_page_tables)) |
4933d519 MT |
1408 | gen6_write_pde(&ppgtt->pd, pde, pt); |
1409 | ||
72744cb1 MT |
1410 | trace_i915_page_table_entry_map(vm, pde, pt, |
1411 | gen6_pte_index(start), | |
1412 | gen6_pte_count(start, length), | |
1413 | GEN6_PTES); | |
4933d519 | 1414 | bitmap_or(pt->used_ptes, tmp_bitmap, pt->used_ptes, |
678d96fb BW |
1415 | GEN6_PTES); |
1416 | } | |
1417 | ||
4933d519 MT |
1418 | WARN_ON(!bitmap_empty(new_page_tables, I915_PDES)); |
1419 | ||
1420 | /* Make sure write is complete before other code can use this page | |
1421 | * table. Also require for WC mapped PTEs */ | |
1422 | readl(dev_priv->gtt.gsm); | |
1423 | ||
563222a7 | 1424 | mark_tlbs_dirty(ppgtt); |
678d96fb | 1425 | return 0; |
4933d519 MT |
1426 | |
1427 | unwind_out: | |
1428 | for_each_set_bit(pde, new_page_tables, I915_PDES) { | |
ec565b3c | 1429 | struct i915_page_table *pt = ppgtt->pd.page_table[pde]; |
4933d519 | 1430 | |
79ab9370 | 1431 | ppgtt->pd.page_table[pde] = vm->scratch_pt; |
a08e111a | 1432 | free_pt(vm->dev, pt); |
4933d519 MT |
1433 | } |
1434 | ||
1435 | mark_tlbs_dirty(ppgtt); | |
1436 | return ret; | |
678d96fb BW |
1437 | } |
1438 | ||
8776f02b MK |
1439 | static int gen6_init_scratch(struct i915_address_space *vm) |
1440 | { | |
1441 | struct drm_device *dev = vm->dev; | |
1442 | ||
1443 | vm->scratch_page = alloc_scratch_page(dev); | |
1444 | if (IS_ERR(vm->scratch_page)) | |
1445 | return PTR_ERR(vm->scratch_page); | |
1446 | ||
1447 | vm->scratch_pt = alloc_pt(dev); | |
1448 | if (IS_ERR(vm->scratch_pt)) { | |
1449 | free_scratch_page(dev, vm->scratch_page); | |
1450 | return PTR_ERR(vm->scratch_pt); | |
1451 | } | |
1452 | ||
1453 | gen6_initialize_pt(vm, vm->scratch_pt); | |
1454 | ||
1455 | return 0; | |
1456 | } | |
1457 | ||
1458 | static void gen6_free_scratch(struct i915_address_space *vm) | |
1459 | { | |
1460 | struct drm_device *dev = vm->dev; | |
1461 | ||
1462 | free_pt(dev, vm->scratch_pt); | |
1463 | free_scratch_page(dev, vm->scratch_page); | |
1464 | } | |
1465 | ||
061dd493 | 1466 | static void gen6_ppgtt_cleanup(struct i915_address_space *vm) |
a00d825d | 1467 | { |
061dd493 DV |
1468 | struct i915_hw_ppgtt *ppgtt = |
1469 | container_of(vm, struct i915_hw_ppgtt, base); | |
09942c65 MT |
1470 | struct i915_page_table *pt; |
1471 | uint32_t pde; | |
4933d519 | 1472 | |
061dd493 DV |
1473 | drm_mm_remove_node(&ppgtt->node); |
1474 | ||
09942c65 | 1475 | gen6_for_all_pdes(pt, ppgtt, pde) { |
79ab9370 | 1476 | if (pt != vm->scratch_pt) |
a08e111a | 1477 | free_pt(ppgtt->base.dev, pt); |
4933d519 | 1478 | } |
06fda602 | 1479 | |
8776f02b | 1480 | gen6_free_scratch(vm); |
3440d265 DV |
1481 | } |
1482 | ||
b146520f | 1483 | static int gen6_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt) |
3440d265 | 1484 | { |
8776f02b | 1485 | struct i915_address_space *vm = &ppgtt->base; |
853ba5d2 | 1486 | struct drm_device *dev = ppgtt->base.dev; |
1d2a314c | 1487 | struct drm_i915_private *dev_priv = dev->dev_private; |
e3cc1995 | 1488 | bool retried = false; |
b146520f | 1489 | int ret; |
1d2a314c | 1490 | |
c8d4c0d6 BW |
1491 | /* PPGTT PDEs reside in the GGTT and consists of 512 entries. The |
1492 | * allocator works in address space sizes, so it's multiplied by page | |
1493 | * size. We allocate at the top of the GTT to avoid fragmentation. | |
1494 | */ | |
1495 | BUG_ON(!drm_mm_initialized(&dev_priv->gtt.base.mm)); | |
4933d519 | 1496 | |
8776f02b MK |
1497 | ret = gen6_init_scratch(vm); |
1498 | if (ret) | |
1499 | return ret; | |
4933d519 | 1500 | |
e3cc1995 | 1501 | alloc: |
c8d4c0d6 BW |
1502 | ret = drm_mm_insert_node_in_range_generic(&dev_priv->gtt.base.mm, |
1503 | &ppgtt->node, GEN6_PD_SIZE, | |
1504 | GEN6_PD_ALIGN, 0, | |
1505 | 0, dev_priv->gtt.base.total, | |
3e8b5ae9 | 1506 | DRM_MM_TOPDOWN); |
e3cc1995 BW |
1507 | if (ret == -ENOSPC && !retried) { |
1508 | ret = i915_gem_evict_something(dev, &dev_priv->gtt.base, | |
1509 | GEN6_PD_SIZE, GEN6_PD_ALIGN, | |
d23db88c CW |
1510 | I915_CACHE_NONE, |
1511 | 0, dev_priv->gtt.base.total, | |
1512 | 0); | |
e3cc1995 | 1513 | if (ret) |
678d96fb | 1514 | goto err_out; |
e3cc1995 BW |
1515 | |
1516 | retried = true; | |
1517 | goto alloc; | |
1518 | } | |
c8d4c0d6 | 1519 | |
c8c26622 | 1520 | if (ret) |
678d96fb BW |
1521 | goto err_out; |
1522 | ||
c8c26622 | 1523 | |
c8d4c0d6 BW |
1524 | if (ppgtt->node.start < dev_priv->gtt.mappable_end) |
1525 | DRM_DEBUG("Forced to use aperture for PDEs\n"); | |
1d2a314c | 1526 | |
c8c26622 | 1527 | return 0; |
678d96fb BW |
1528 | |
1529 | err_out: | |
8776f02b | 1530 | gen6_free_scratch(vm); |
678d96fb | 1531 | return ret; |
b146520f BW |
1532 | } |
1533 | ||
b146520f BW |
1534 | static int gen6_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt) |
1535 | { | |
2f2cf682 | 1536 | return gen6_ppgtt_allocate_page_directories(ppgtt); |
4933d519 | 1537 | } |
06dc68d6 | 1538 | |
4933d519 MT |
1539 | static void gen6_scratch_va_range(struct i915_hw_ppgtt *ppgtt, |
1540 | uint64_t start, uint64_t length) | |
1541 | { | |
ec565b3c | 1542 | struct i915_page_table *unused; |
4933d519 | 1543 | uint32_t pde, temp; |
1d2a314c | 1544 | |
4933d519 | 1545 | gen6_for_each_pde(unused, &ppgtt->pd, start, length, temp, pde) |
79ab9370 | 1546 | ppgtt->pd.page_table[pde] = ppgtt->base.scratch_pt; |
b146520f BW |
1547 | } |
1548 | ||
5c5f6457 | 1549 | static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt) |
b146520f BW |
1550 | { |
1551 | struct drm_device *dev = ppgtt->base.dev; | |
1552 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1553 | int ret; | |
1554 | ||
1555 | ppgtt->base.pte_encode = dev_priv->gtt.base.pte_encode; | |
1556 | if (IS_GEN6(dev)) { | |
b146520f BW |
1557 | ppgtt->switch_mm = gen6_mm_switch; |
1558 | } else if (IS_HASWELL(dev)) { | |
b146520f BW |
1559 | ppgtt->switch_mm = hsw_mm_switch; |
1560 | } else if (IS_GEN7(dev)) { | |
b146520f BW |
1561 | ppgtt->switch_mm = gen7_mm_switch; |
1562 | } else | |
1563 | BUG(); | |
1564 | ||
71ba2d64 YZ |
1565 | if (intel_vgpu_active(dev)) |
1566 | ppgtt->switch_mm = vgpu_mm_switch; | |
1567 | ||
b146520f BW |
1568 | ret = gen6_ppgtt_alloc(ppgtt); |
1569 | if (ret) | |
1570 | return ret; | |
1571 | ||
5c5f6457 | 1572 | ppgtt->base.allocate_va_range = gen6_alloc_va_range; |
b146520f BW |
1573 | ppgtt->base.clear_range = gen6_ppgtt_clear_range; |
1574 | ppgtt->base.insert_entries = gen6_ppgtt_insert_entries; | |
777dc5bb DV |
1575 | ppgtt->base.unbind_vma = ppgtt_unbind_vma; |
1576 | ppgtt->base.bind_vma = ppgtt_bind_vma; | |
b146520f | 1577 | ppgtt->base.cleanup = gen6_ppgtt_cleanup; |
b146520f | 1578 | ppgtt->base.start = 0; |
09942c65 | 1579 | ppgtt->base.total = I915_PDES * GEN6_PTES * PAGE_SIZE; |
87d60b63 | 1580 | ppgtt->debug_dump = gen6_dump_ppgtt; |
1d2a314c | 1581 | |
44159ddb | 1582 | ppgtt->pd.base.ggtt_offset = |
07749ef3 | 1583 | ppgtt->node.start / PAGE_SIZE * sizeof(gen6_pte_t); |
1d2a314c | 1584 | |
678d96fb | 1585 | ppgtt->pd_addr = (gen6_pte_t __iomem *)dev_priv->gtt.gsm + |
44159ddb | 1586 | ppgtt->pd.base.ggtt_offset / sizeof(gen6_pte_t); |
678d96fb | 1587 | |
5c5f6457 | 1588 | gen6_scratch_va_range(ppgtt, 0, ppgtt->base.total); |
1d2a314c | 1589 | |
678d96fb BW |
1590 | gen6_write_page_range(dev_priv, &ppgtt->pd, 0, ppgtt->base.total); |
1591 | ||
440fd528 | 1592 | DRM_DEBUG_DRIVER("Allocated pde space (%lldM) at GTT entry: %llx\n", |
b146520f BW |
1593 | ppgtt->node.size >> 20, |
1594 | ppgtt->node.start / PAGE_SIZE); | |
3440d265 | 1595 | |
fa76da34 | 1596 | DRM_DEBUG("Adding PPGTT at offset %x\n", |
44159ddb | 1597 | ppgtt->pd.base.ggtt_offset << 10); |
fa76da34 | 1598 | |
b146520f | 1599 | return 0; |
3440d265 DV |
1600 | } |
1601 | ||
5c5f6457 | 1602 | static int __hw_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt) |
3440d265 | 1603 | { |
853ba5d2 | 1604 | ppgtt->base.dev = dev; |
3440d265 | 1605 | |
3ed124b2 | 1606 | if (INTEL_INFO(dev)->gen < 8) |
5c5f6457 | 1607 | return gen6_ppgtt_init(ppgtt); |
3ed124b2 | 1608 | else |
d7b2633d | 1609 | return gen8_ppgtt_init(ppgtt); |
fa76da34 | 1610 | } |
c114f76a | 1611 | |
fa76da34 DV |
1612 | int i915_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt) |
1613 | { | |
1614 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1615 | int ret = 0; | |
3ed124b2 | 1616 | |
5c5f6457 | 1617 | ret = __hw_ppgtt_init(dev, ppgtt); |
fa76da34 | 1618 | if (ret == 0) { |
c7c48dfd | 1619 | kref_init(&ppgtt->ref); |
93bd8649 BW |
1620 | drm_mm_init(&ppgtt->base.mm, ppgtt->base.start, |
1621 | ppgtt->base.total); | |
7e0d96bc | 1622 | i915_init_vm(dev_priv, &ppgtt->base); |
93bd8649 | 1623 | } |
1d2a314c DV |
1624 | |
1625 | return ret; | |
1626 | } | |
1627 | ||
82460d97 DV |
1628 | int i915_ppgtt_init_hw(struct drm_device *dev) |
1629 | { | |
671b5013 TD |
1630 | /* In the case of execlists, PPGTT is enabled by the context descriptor |
1631 | * and the PDPs are contained within the context itself. We don't | |
1632 | * need to do anything here. */ | |
1633 | if (i915.enable_execlists) | |
1634 | return 0; | |
1635 | ||
82460d97 DV |
1636 | if (!USES_PPGTT(dev)) |
1637 | return 0; | |
1638 | ||
1639 | if (IS_GEN6(dev)) | |
1640 | gen6_ppgtt_enable(dev); | |
1641 | else if (IS_GEN7(dev)) | |
1642 | gen7_ppgtt_enable(dev); | |
1643 | else if (INTEL_INFO(dev)->gen >= 8) | |
1644 | gen8_ppgtt_enable(dev); | |
1645 | else | |
5f77eeb0 | 1646 | MISSING_CASE(INTEL_INFO(dev)->gen); |
82460d97 | 1647 | |
4ad2fd88 JH |
1648 | return 0; |
1649 | } | |
1d2a314c | 1650 | |
b3dd6b96 | 1651 | int i915_ppgtt_init_ring(struct drm_i915_gem_request *req) |
4ad2fd88 | 1652 | { |
b3dd6b96 | 1653 | struct drm_i915_private *dev_priv = req->ring->dev->dev_private; |
4ad2fd88 JH |
1654 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; |
1655 | ||
1656 | if (i915.enable_execlists) | |
1657 | return 0; | |
1658 | ||
1659 | if (!ppgtt) | |
1660 | return 0; | |
1661 | ||
e85b26dc | 1662 | return ppgtt->switch_mm(ppgtt, req); |
1d2a314c | 1663 | } |
4ad2fd88 | 1664 | |
4d884705 DV |
1665 | struct i915_hw_ppgtt * |
1666 | i915_ppgtt_create(struct drm_device *dev, struct drm_i915_file_private *fpriv) | |
1667 | { | |
1668 | struct i915_hw_ppgtt *ppgtt; | |
1669 | int ret; | |
1670 | ||
1671 | ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL); | |
1672 | if (!ppgtt) | |
1673 | return ERR_PTR(-ENOMEM); | |
1674 | ||
1675 | ret = i915_ppgtt_init(dev, ppgtt); | |
1676 | if (ret) { | |
1677 | kfree(ppgtt); | |
1678 | return ERR_PTR(ret); | |
1679 | } | |
1680 | ||
1681 | ppgtt->file_priv = fpriv; | |
1682 | ||
198c974d DCS |
1683 | trace_i915_ppgtt_create(&ppgtt->base); |
1684 | ||
4d884705 DV |
1685 | return ppgtt; |
1686 | } | |
1687 | ||
ee960be7 DV |
1688 | void i915_ppgtt_release(struct kref *kref) |
1689 | { | |
1690 | struct i915_hw_ppgtt *ppgtt = | |
1691 | container_of(kref, struct i915_hw_ppgtt, ref); | |
1692 | ||
198c974d DCS |
1693 | trace_i915_ppgtt_release(&ppgtt->base); |
1694 | ||
ee960be7 DV |
1695 | /* vmas should already be unbound */ |
1696 | WARN_ON(!list_empty(&ppgtt->base.active_list)); | |
1697 | WARN_ON(!list_empty(&ppgtt->base.inactive_list)); | |
1698 | ||
19dd120c DV |
1699 | list_del(&ppgtt->base.global_link); |
1700 | drm_mm_takedown(&ppgtt->base.mm); | |
1701 | ||
ee960be7 DV |
1702 | ppgtt->base.cleanup(&ppgtt->base); |
1703 | kfree(ppgtt); | |
1704 | } | |
1d2a314c | 1705 | |
a81cc00c BW |
1706 | extern int intel_iommu_gfx_mapped; |
1707 | /* Certain Gen5 chipsets require require idling the GPU before | |
1708 | * unmapping anything from the GTT when VT-d is enabled. | |
1709 | */ | |
2c642b07 | 1710 | static bool needs_idle_maps(struct drm_device *dev) |
a81cc00c BW |
1711 | { |
1712 | #ifdef CONFIG_INTEL_IOMMU | |
1713 | /* Query intel_iommu to see if we need the workaround. Presumably that | |
1714 | * was loaded first. | |
1715 | */ | |
1716 | if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped) | |
1717 | return true; | |
1718 | #endif | |
1719 | return false; | |
1720 | } | |
1721 | ||
5c042287 BW |
1722 | static bool do_idling(struct drm_i915_private *dev_priv) |
1723 | { | |
1724 | bool ret = dev_priv->mm.interruptible; | |
1725 | ||
a81cc00c | 1726 | if (unlikely(dev_priv->gtt.do_idle_maps)) { |
5c042287 | 1727 | dev_priv->mm.interruptible = false; |
b2da9fe5 | 1728 | if (i915_gpu_idle(dev_priv->dev)) { |
5c042287 BW |
1729 | DRM_ERROR("Couldn't idle GPU\n"); |
1730 | /* Wait a bit, in hopes it avoids the hang */ | |
1731 | udelay(10); | |
1732 | } | |
1733 | } | |
1734 | ||
1735 | return ret; | |
1736 | } | |
1737 | ||
1738 | static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible) | |
1739 | { | |
a81cc00c | 1740 | if (unlikely(dev_priv->gtt.do_idle_maps)) |
5c042287 BW |
1741 | dev_priv->mm.interruptible = interruptible; |
1742 | } | |
1743 | ||
828c7908 BW |
1744 | void i915_check_and_clear_faults(struct drm_device *dev) |
1745 | { | |
1746 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a4872ba6 | 1747 | struct intel_engine_cs *ring; |
828c7908 BW |
1748 | int i; |
1749 | ||
1750 | if (INTEL_INFO(dev)->gen < 6) | |
1751 | return; | |
1752 | ||
1753 | for_each_ring(ring, dev_priv, i) { | |
1754 | u32 fault_reg; | |
1755 | fault_reg = I915_READ(RING_FAULT_REG(ring)); | |
1756 | if (fault_reg & RING_FAULT_VALID) { | |
1757 | DRM_DEBUG_DRIVER("Unexpected fault\n" | |
59a5d290 | 1758 | "\tAddr: 0x%08lx\n" |
828c7908 BW |
1759 | "\tAddress space: %s\n" |
1760 | "\tSource ID: %d\n" | |
1761 | "\tType: %d\n", | |
1762 | fault_reg & PAGE_MASK, | |
1763 | fault_reg & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT", | |
1764 | RING_FAULT_SRCID(fault_reg), | |
1765 | RING_FAULT_FAULT_TYPE(fault_reg)); | |
1766 | I915_WRITE(RING_FAULT_REG(ring), | |
1767 | fault_reg & ~RING_FAULT_VALID); | |
1768 | } | |
1769 | } | |
1770 | POSTING_READ(RING_FAULT_REG(&dev_priv->ring[RCS])); | |
1771 | } | |
1772 | ||
91e56499 CW |
1773 | static void i915_ggtt_flush(struct drm_i915_private *dev_priv) |
1774 | { | |
1775 | if (INTEL_INFO(dev_priv->dev)->gen < 6) { | |
1776 | intel_gtt_chipset_flush(); | |
1777 | } else { | |
1778 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
1779 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
1780 | } | |
1781 | } | |
1782 | ||
828c7908 BW |
1783 | void i915_gem_suspend_gtt_mappings(struct drm_device *dev) |
1784 | { | |
1785 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1786 | ||
1787 | /* Don't bother messing with faults pre GEN6 as we have little | |
1788 | * documentation supporting that it's a good idea. | |
1789 | */ | |
1790 | if (INTEL_INFO(dev)->gen < 6) | |
1791 | return; | |
1792 | ||
1793 | i915_check_and_clear_faults(dev); | |
1794 | ||
1795 | dev_priv->gtt.base.clear_range(&dev_priv->gtt.base, | |
782f1495 BW |
1796 | dev_priv->gtt.base.start, |
1797 | dev_priv->gtt.base.total, | |
e568af1c | 1798 | true); |
91e56499 CW |
1799 | |
1800 | i915_ggtt_flush(dev_priv); | |
828c7908 BW |
1801 | } |
1802 | ||
74163907 | 1803 | int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj) |
7c2e6fdf | 1804 | { |
9da3da66 CW |
1805 | if (!dma_map_sg(&obj->base.dev->pdev->dev, |
1806 | obj->pages->sgl, obj->pages->nents, | |
1807 | PCI_DMA_BIDIRECTIONAL)) | |
1808 | return -ENOSPC; | |
1809 | ||
1810 | return 0; | |
7c2e6fdf DV |
1811 | } |
1812 | ||
2c642b07 | 1813 | static void gen8_set_pte(void __iomem *addr, gen8_pte_t pte) |
94ec8f61 BW |
1814 | { |
1815 | #ifdef writeq | |
1816 | writeq(pte, addr); | |
1817 | #else | |
1818 | iowrite32((u32)pte, addr); | |
1819 | iowrite32(pte >> 32, addr + 4); | |
1820 | #endif | |
1821 | } | |
1822 | ||
1823 | static void gen8_ggtt_insert_entries(struct i915_address_space *vm, | |
1824 | struct sg_table *st, | |
782f1495 | 1825 | uint64_t start, |
24f3a8cf | 1826 | enum i915_cache_level level, u32 unused) |
94ec8f61 BW |
1827 | { |
1828 | struct drm_i915_private *dev_priv = vm->dev->dev_private; | |
782f1495 | 1829 | unsigned first_entry = start >> PAGE_SHIFT; |
07749ef3 MT |
1830 | gen8_pte_t __iomem *gtt_entries = |
1831 | (gen8_pte_t __iomem *)dev_priv->gtt.gsm + first_entry; | |
94ec8f61 BW |
1832 | int i = 0; |
1833 | struct sg_page_iter sg_iter; | |
57007df7 | 1834 | dma_addr_t addr = 0; /* shut up gcc */ |
94ec8f61 BW |
1835 | |
1836 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) { | |
1837 | addr = sg_dma_address(sg_iter.sg) + | |
1838 | (sg_iter.sg_pgoffset << PAGE_SHIFT); | |
1839 | gen8_set_pte(>t_entries[i], | |
1840 | gen8_pte_encode(addr, level, true)); | |
1841 | i++; | |
1842 | } | |
1843 | ||
1844 | /* | |
1845 | * XXX: This serves as a posting read to make sure that the PTE has | |
1846 | * actually been updated. There is some concern that even though | |
1847 | * registers and PTEs are within the same BAR that they are potentially | |
1848 | * of NUMA access patterns. Therefore, even with the way we assume | |
1849 | * hardware should work, we must keep this posting read for paranoia. | |
1850 | */ | |
1851 | if (i != 0) | |
1852 | WARN_ON(readq(>t_entries[i-1]) | |
1853 | != gen8_pte_encode(addr, level, true)); | |
1854 | ||
94ec8f61 BW |
1855 | /* This next bit makes the above posting read even more important. We |
1856 | * want to flush the TLBs only after we're certain all the PTE updates | |
1857 | * have finished. | |
1858 | */ | |
1859 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
1860 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
94ec8f61 BW |
1861 | } |
1862 | ||
e76e9aeb BW |
1863 | /* |
1864 | * Binds an object into the global gtt with the specified cache level. The object | |
1865 | * will be accessible to the GPU via commands whose operands reference offsets | |
1866 | * within the global GTT as well as accessible by the GPU through the GMADR | |
1867 | * mapped BAR (dev_priv->mm.gtt->gtt). | |
1868 | */ | |
853ba5d2 | 1869 | static void gen6_ggtt_insert_entries(struct i915_address_space *vm, |
7faf1ab2 | 1870 | struct sg_table *st, |
782f1495 | 1871 | uint64_t start, |
24f3a8cf | 1872 | enum i915_cache_level level, u32 flags) |
e76e9aeb | 1873 | { |
853ba5d2 | 1874 | struct drm_i915_private *dev_priv = vm->dev->dev_private; |
782f1495 | 1875 | unsigned first_entry = start >> PAGE_SHIFT; |
07749ef3 MT |
1876 | gen6_pte_t __iomem *gtt_entries = |
1877 | (gen6_pte_t __iomem *)dev_priv->gtt.gsm + first_entry; | |
6e995e23 ID |
1878 | int i = 0; |
1879 | struct sg_page_iter sg_iter; | |
57007df7 | 1880 | dma_addr_t addr = 0; |
e76e9aeb | 1881 | |
6e995e23 | 1882 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) { |
2db76d7c | 1883 | addr = sg_page_iter_dma_address(&sg_iter); |
24f3a8cf | 1884 | iowrite32(vm->pte_encode(addr, level, true, flags), >t_entries[i]); |
6e995e23 | 1885 | i++; |
e76e9aeb BW |
1886 | } |
1887 | ||
e76e9aeb BW |
1888 | /* XXX: This serves as a posting read to make sure that the PTE has |
1889 | * actually been updated. There is some concern that even though | |
1890 | * registers and PTEs are within the same BAR that they are potentially | |
1891 | * of NUMA access patterns. Therefore, even with the way we assume | |
1892 | * hardware should work, we must keep this posting read for paranoia. | |
1893 | */ | |
57007df7 PM |
1894 | if (i != 0) { |
1895 | unsigned long gtt = readl(>t_entries[i-1]); | |
1896 | WARN_ON(gtt != vm->pte_encode(addr, level, true, flags)); | |
1897 | } | |
0f9b91c7 BW |
1898 | |
1899 | /* This next bit makes the above posting read even more important. We | |
1900 | * want to flush the TLBs only after we're certain all the PTE updates | |
1901 | * have finished. | |
1902 | */ | |
1903 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
1904 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
e76e9aeb BW |
1905 | } |
1906 | ||
94ec8f61 | 1907 | static void gen8_ggtt_clear_range(struct i915_address_space *vm, |
782f1495 BW |
1908 | uint64_t start, |
1909 | uint64_t length, | |
94ec8f61 BW |
1910 | bool use_scratch) |
1911 | { | |
1912 | struct drm_i915_private *dev_priv = vm->dev->dev_private; | |
782f1495 BW |
1913 | unsigned first_entry = start >> PAGE_SHIFT; |
1914 | unsigned num_entries = length >> PAGE_SHIFT; | |
07749ef3 MT |
1915 | gen8_pte_t scratch_pte, __iomem *gtt_base = |
1916 | (gen8_pte_t __iomem *) dev_priv->gtt.gsm + first_entry; | |
94ec8f61 BW |
1917 | const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry; |
1918 | int i; | |
1919 | ||
1920 | if (WARN(num_entries > max_entries, | |
1921 | "First entry = %d; Num entries = %d (max=%d)\n", | |
1922 | first_entry, num_entries, max_entries)) | |
1923 | num_entries = max_entries; | |
1924 | ||
c114f76a | 1925 | scratch_pte = gen8_pte_encode(px_dma(vm->scratch_page), |
94ec8f61 BW |
1926 | I915_CACHE_LLC, |
1927 | use_scratch); | |
1928 | for (i = 0; i < num_entries; i++) | |
1929 | gen8_set_pte(>t_base[i], scratch_pte); | |
1930 | readl(gtt_base); | |
1931 | } | |
1932 | ||
853ba5d2 | 1933 | static void gen6_ggtt_clear_range(struct i915_address_space *vm, |
782f1495 BW |
1934 | uint64_t start, |
1935 | uint64_t length, | |
828c7908 | 1936 | bool use_scratch) |
7faf1ab2 | 1937 | { |
853ba5d2 | 1938 | struct drm_i915_private *dev_priv = vm->dev->dev_private; |
782f1495 BW |
1939 | unsigned first_entry = start >> PAGE_SHIFT; |
1940 | unsigned num_entries = length >> PAGE_SHIFT; | |
07749ef3 MT |
1941 | gen6_pte_t scratch_pte, __iomem *gtt_base = |
1942 | (gen6_pte_t __iomem *) dev_priv->gtt.gsm + first_entry; | |
a54c0c27 | 1943 | const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry; |
7faf1ab2 DV |
1944 | int i; |
1945 | ||
1946 | if (WARN(num_entries > max_entries, | |
1947 | "First entry = %d; Num entries = %d (max=%d)\n", | |
1948 | first_entry, num_entries, max_entries)) | |
1949 | num_entries = max_entries; | |
1950 | ||
c114f76a MK |
1951 | scratch_pte = vm->pte_encode(px_dma(vm->scratch_page), |
1952 | I915_CACHE_LLC, use_scratch, 0); | |
828c7908 | 1953 | |
7faf1ab2 DV |
1954 | for (i = 0; i < num_entries; i++) |
1955 | iowrite32(scratch_pte, >t_base[i]); | |
1956 | readl(gtt_base); | |
1957 | } | |
1958 | ||
d369d2d9 DV |
1959 | static void i915_ggtt_insert_entries(struct i915_address_space *vm, |
1960 | struct sg_table *pages, | |
1961 | uint64_t start, | |
1962 | enum i915_cache_level cache_level, u32 unused) | |
7faf1ab2 DV |
1963 | { |
1964 | unsigned int flags = (cache_level == I915_CACHE_NONE) ? | |
1965 | AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY; | |
1966 | ||
d369d2d9 | 1967 | intel_gtt_insert_sg_entries(pages, start >> PAGE_SHIFT, flags); |
0875546c | 1968 | |
7faf1ab2 DV |
1969 | } |
1970 | ||
853ba5d2 | 1971 | static void i915_ggtt_clear_range(struct i915_address_space *vm, |
782f1495 BW |
1972 | uint64_t start, |
1973 | uint64_t length, | |
828c7908 | 1974 | bool unused) |
7faf1ab2 | 1975 | { |
782f1495 BW |
1976 | unsigned first_entry = start >> PAGE_SHIFT; |
1977 | unsigned num_entries = length >> PAGE_SHIFT; | |
7faf1ab2 DV |
1978 | intel_gtt_clear_range(first_entry, num_entries); |
1979 | } | |
1980 | ||
70b9f6f8 DV |
1981 | static int ggtt_bind_vma(struct i915_vma *vma, |
1982 | enum i915_cache_level cache_level, | |
1983 | u32 flags) | |
d5bd1449 | 1984 | { |
6f65e29a | 1985 | struct drm_device *dev = vma->vm->dev; |
7faf1ab2 | 1986 | struct drm_i915_private *dev_priv = dev->dev_private; |
6f65e29a | 1987 | struct drm_i915_gem_object *obj = vma->obj; |
ec7adb6e | 1988 | struct sg_table *pages = obj->pages; |
f329f5f6 | 1989 | u32 pte_flags = 0; |
70b9f6f8 DV |
1990 | int ret; |
1991 | ||
1992 | ret = i915_get_ggtt_vma_pages(vma); | |
1993 | if (ret) | |
1994 | return ret; | |
1995 | pages = vma->ggtt_view.pages; | |
7faf1ab2 | 1996 | |
24f3a8cf AG |
1997 | /* Currently applicable only to VLV */ |
1998 | if (obj->gt_ro) | |
f329f5f6 | 1999 | pte_flags |= PTE_READ_ONLY; |
24f3a8cf | 2000 | |
ec7adb6e | 2001 | |
6f65e29a | 2002 | if (!dev_priv->mm.aliasing_ppgtt || flags & GLOBAL_BIND) { |
0875546c DV |
2003 | vma->vm->insert_entries(vma->vm, pages, |
2004 | vma->node.start, | |
2005 | cache_level, pte_flags); | |
d0e30adc CW |
2006 | |
2007 | /* Note the inconsistency here is due to absence of the | |
2008 | * aliasing ppgtt on gen4 and earlier. Though we always | |
2009 | * request PIN_USER for execbuffer (translated to LOCAL_BIND), | |
2010 | * without the appgtt, we cannot honour that request and so | |
2011 | * must substitute it with a global binding. Since we do this | |
2012 | * behind the upper layers back, we need to explicitly set | |
2013 | * the bound flag ourselves. | |
2014 | */ | |
2015 | vma->bound |= GLOBAL_BIND; | |
2016 | ||
6f65e29a | 2017 | } |
d5bd1449 | 2018 | |
0875546c | 2019 | if (dev_priv->mm.aliasing_ppgtt && flags & LOCAL_BIND) { |
6f65e29a | 2020 | struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt; |
ec7adb6e | 2021 | appgtt->base.insert_entries(&appgtt->base, pages, |
782f1495 | 2022 | vma->node.start, |
f329f5f6 | 2023 | cache_level, pte_flags); |
6f65e29a | 2024 | } |
70b9f6f8 DV |
2025 | |
2026 | return 0; | |
d5bd1449 CW |
2027 | } |
2028 | ||
6f65e29a | 2029 | static void ggtt_unbind_vma(struct i915_vma *vma) |
74163907 | 2030 | { |
6f65e29a | 2031 | struct drm_device *dev = vma->vm->dev; |
7faf1ab2 | 2032 | struct drm_i915_private *dev_priv = dev->dev_private; |
6f65e29a | 2033 | struct drm_i915_gem_object *obj = vma->obj; |
06615ee5 JL |
2034 | const uint64_t size = min_t(uint64_t, |
2035 | obj->base.size, | |
2036 | vma->node.size); | |
6f65e29a | 2037 | |
aff43766 | 2038 | if (vma->bound & GLOBAL_BIND) { |
782f1495 BW |
2039 | vma->vm->clear_range(vma->vm, |
2040 | vma->node.start, | |
06615ee5 | 2041 | size, |
6f65e29a | 2042 | true); |
6f65e29a | 2043 | } |
74898d7e | 2044 | |
0875546c | 2045 | if (dev_priv->mm.aliasing_ppgtt && vma->bound & LOCAL_BIND) { |
6f65e29a | 2046 | struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt; |
06615ee5 | 2047 | |
6f65e29a | 2048 | appgtt->base.clear_range(&appgtt->base, |
782f1495 | 2049 | vma->node.start, |
06615ee5 | 2050 | size, |
6f65e29a | 2051 | true); |
6f65e29a | 2052 | } |
74163907 DV |
2053 | } |
2054 | ||
2055 | void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj) | |
7c2e6fdf | 2056 | { |
5c042287 BW |
2057 | struct drm_device *dev = obj->base.dev; |
2058 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2059 | bool interruptible; | |
2060 | ||
2061 | interruptible = do_idling(dev_priv); | |
2062 | ||
5ec5b516 ID |
2063 | dma_unmap_sg(&dev->pdev->dev, obj->pages->sgl, obj->pages->nents, |
2064 | PCI_DMA_BIDIRECTIONAL); | |
5c042287 BW |
2065 | |
2066 | undo_idling(dev_priv, interruptible); | |
7c2e6fdf | 2067 | } |
644ec02b | 2068 | |
42d6ab48 CW |
2069 | static void i915_gtt_color_adjust(struct drm_mm_node *node, |
2070 | unsigned long color, | |
440fd528 TR |
2071 | u64 *start, |
2072 | u64 *end) | |
42d6ab48 CW |
2073 | { |
2074 | if (node->color != color) | |
2075 | *start += 4096; | |
2076 | ||
2077 | if (!list_empty(&node->node_list)) { | |
2078 | node = list_entry(node->node_list.next, | |
2079 | struct drm_mm_node, | |
2080 | node_list); | |
2081 | if (node->allocated && node->color != color) | |
2082 | *end -= 4096; | |
2083 | } | |
2084 | } | |
fbe5d36e | 2085 | |
f548c0e9 DV |
2086 | static int i915_gem_setup_global_gtt(struct drm_device *dev, |
2087 | unsigned long start, | |
2088 | unsigned long mappable_end, | |
2089 | unsigned long end) | |
644ec02b | 2090 | { |
e78891ca BW |
2091 | /* Let GEM Manage all of the aperture. |
2092 | * | |
2093 | * However, leave one page at the end still bound to the scratch page. | |
2094 | * There are a number of places where the hardware apparently prefetches | |
2095 | * past the end of the object, and we've seen multiple hangs with the | |
2096 | * GPU head pointer stuck in a batchbuffer bound at the last page of the | |
2097 | * aperture. One page should be enough to keep any prefetching inside | |
2098 | * of the aperture. | |
2099 | */ | |
40d74980 BW |
2100 | struct drm_i915_private *dev_priv = dev->dev_private; |
2101 | struct i915_address_space *ggtt_vm = &dev_priv->gtt.base; | |
ed2f3452 CW |
2102 | struct drm_mm_node *entry; |
2103 | struct drm_i915_gem_object *obj; | |
2104 | unsigned long hole_start, hole_end; | |
fa76da34 | 2105 | int ret; |
644ec02b | 2106 | |
35451cb6 BW |
2107 | BUG_ON(mappable_end > end); |
2108 | ||
ed2f3452 | 2109 | /* Subtract the guard page ... */ |
40d74980 | 2110 | drm_mm_init(&ggtt_vm->mm, start, end - start - PAGE_SIZE); |
5dda8fa3 YZ |
2111 | |
2112 | dev_priv->gtt.base.start = start; | |
2113 | dev_priv->gtt.base.total = end - start; | |
2114 | ||
2115 | if (intel_vgpu_active(dev)) { | |
2116 | ret = intel_vgt_balloon(dev); | |
2117 | if (ret) | |
2118 | return ret; | |
2119 | } | |
2120 | ||
42d6ab48 | 2121 | if (!HAS_LLC(dev)) |
93bd8649 | 2122 | dev_priv->gtt.base.mm.color_adjust = i915_gtt_color_adjust; |
644ec02b | 2123 | |
ed2f3452 | 2124 | /* Mark any preallocated objects as occupied */ |
35c20a60 | 2125 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
40d74980 | 2126 | struct i915_vma *vma = i915_gem_obj_to_vma(obj, ggtt_vm); |
fa76da34 | 2127 | |
edd41a87 | 2128 | DRM_DEBUG_KMS("reserving preallocated space: %lx + %zx\n", |
c6cfb325 BW |
2129 | i915_gem_obj_ggtt_offset(obj), obj->base.size); |
2130 | ||
2131 | WARN_ON(i915_gem_obj_ggtt_bound(obj)); | |
40d74980 | 2132 | ret = drm_mm_reserve_node(&ggtt_vm->mm, &vma->node); |
6c5566a8 DV |
2133 | if (ret) { |
2134 | DRM_DEBUG_KMS("Reservation failed: %i\n", ret); | |
2135 | return ret; | |
2136 | } | |
aff43766 | 2137 | vma->bound |= GLOBAL_BIND; |
ed2f3452 CW |
2138 | } |
2139 | ||
ed2f3452 | 2140 | /* Clear any non-preallocated blocks */ |
40d74980 | 2141 | drm_mm_for_each_hole(entry, &ggtt_vm->mm, hole_start, hole_end) { |
ed2f3452 CW |
2142 | DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n", |
2143 | hole_start, hole_end); | |
782f1495 BW |
2144 | ggtt_vm->clear_range(ggtt_vm, hole_start, |
2145 | hole_end - hole_start, true); | |
ed2f3452 CW |
2146 | } |
2147 | ||
2148 | /* And finally clear the reserved guard page */ | |
782f1495 | 2149 | ggtt_vm->clear_range(ggtt_vm, end - PAGE_SIZE, PAGE_SIZE, true); |
6c5566a8 | 2150 | |
fa76da34 DV |
2151 | if (USES_PPGTT(dev) && !USES_FULL_PPGTT(dev)) { |
2152 | struct i915_hw_ppgtt *ppgtt; | |
2153 | ||
2154 | ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL); | |
2155 | if (!ppgtt) | |
2156 | return -ENOMEM; | |
2157 | ||
5c5f6457 DV |
2158 | ret = __hw_ppgtt_init(dev, ppgtt); |
2159 | if (ret) { | |
2160 | ppgtt->base.cleanup(&ppgtt->base); | |
2161 | kfree(ppgtt); | |
2162 | return ret; | |
2163 | } | |
2164 | ||
2165 | if (ppgtt->base.allocate_va_range) | |
2166 | ret = ppgtt->base.allocate_va_range(&ppgtt->base, 0, | |
2167 | ppgtt->base.total); | |
4933d519 | 2168 | if (ret) { |
061dd493 | 2169 | ppgtt->base.cleanup(&ppgtt->base); |
4933d519 | 2170 | kfree(ppgtt); |
fa76da34 | 2171 | return ret; |
4933d519 | 2172 | } |
fa76da34 | 2173 | |
5c5f6457 DV |
2174 | ppgtt->base.clear_range(&ppgtt->base, |
2175 | ppgtt->base.start, | |
2176 | ppgtt->base.total, | |
2177 | true); | |
2178 | ||
fa76da34 DV |
2179 | dev_priv->mm.aliasing_ppgtt = ppgtt; |
2180 | } | |
2181 | ||
6c5566a8 | 2182 | return 0; |
e76e9aeb BW |
2183 | } |
2184 | ||
d7e5008f BW |
2185 | void i915_gem_init_global_gtt(struct drm_device *dev) |
2186 | { | |
2187 | struct drm_i915_private *dev_priv = dev->dev_private; | |
c44ef60e | 2188 | u64 gtt_size, mappable_size; |
d7e5008f | 2189 | |
853ba5d2 | 2190 | gtt_size = dev_priv->gtt.base.total; |
93d18799 | 2191 | mappable_size = dev_priv->gtt.mappable_end; |
d7e5008f | 2192 | |
e78891ca | 2193 | i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size); |
e76e9aeb BW |
2194 | } |
2195 | ||
90d0a0e8 DV |
2196 | void i915_global_gtt_cleanup(struct drm_device *dev) |
2197 | { | |
2198 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2199 | struct i915_address_space *vm = &dev_priv->gtt.base; | |
2200 | ||
70e32544 DV |
2201 | if (dev_priv->mm.aliasing_ppgtt) { |
2202 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
2203 | ||
2204 | ppgtt->base.cleanup(&ppgtt->base); | |
2205 | } | |
2206 | ||
90d0a0e8 | 2207 | if (drm_mm_initialized(&vm->mm)) { |
5dda8fa3 YZ |
2208 | if (intel_vgpu_active(dev)) |
2209 | intel_vgt_deballoon(); | |
2210 | ||
90d0a0e8 DV |
2211 | drm_mm_takedown(&vm->mm); |
2212 | list_del(&vm->global_link); | |
2213 | } | |
2214 | ||
2215 | vm->cleanup(vm); | |
2216 | } | |
70e32544 | 2217 | |
2c642b07 | 2218 | static unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl) |
e76e9aeb BW |
2219 | { |
2220 | snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT; | |
2221 | snb_gmch_ctl &= SNB_GMCH_GGMS_MASK; | |
2222 | return snb_gmch_ctl << 20; | |
2223 | } | |
2224 | ||
2c642b07 | 2225 | static unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl) |
9459d252 BW |
2226 | { |
2227 | bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT; | |
2228 | bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK; | |
2229 | if (bdw_gmch_ctl) | |
2230 | bdw_gmch_ctl = 1 << bdw_gmch_ctl; | |
562d55d9 BW |
2231 | |
2232 | #ifdef CONFIG_X86_32 | |
2233 | /* Limit 32b platforms to a 2GB GGTT: 4 << 20 / pte size * PAGE_SIZE */ | |
2234 | if (bdw_gmch_ctl > 4) | |
2235 | bdw_gmch_ctl = 4; | |
2236 | #endif | |
2237 | ||
9459d252 BW |
2238 | return bdw_gmch_ctl << 20; |
2239 | } | |
2240 | ||
2c642b07 | 2241 | static unsigned int chv_get_total_gtt_size(u16 gmch_ctrl) |
d7f25f23 DL |
2242 | { |
2243 | gmch_ctrl >>= SNB_GMCH_GGMS_SHIFT; | |
2244 | gmch_ctrl &= SNB_GMCH_GGMS_MASK; | |
2245 | ||
2246 | if (gmch_ctrl) | |
2247 | return 1 << (20 + gmch_ctrl); | |
2248 | ||
2249 | return 0; | |
2250 | } | |
2251 | ||
2c642b07 | 2252 | static size_t gen6_get_stolen_size(u16 snb_gmch_ctl) |
e76e9aeb BW |
2253 | { |
2254 | snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT; | |
2255 | snb_gmch_ctl &= SNB_GMCH_GMS_MASK; | |
2256 | return snb_gmch_ctl << 25; /* 32 MB units */ | |
2257 | } | |
2258 | ||
2c642b07 | 2259 | static size_t gen8_get_stolen_size(u16 bdw_gmch_ctl) |
9459d252 BW |
2260 | { |
2261 | bdw_gmch_ctl >>= BDW_GMCH_GMS_SHIFT; | |
2262 | bdw_gmch_ctl &= BDW_GMCH_GMS_MASK; | |
2263 | return bdw_gmch_ctl << 25; /* 32 MB units */ | |
2264 | } | |
2265 | ||
d7f25f23 DL |
2266 | static size_t chv_get_stolen_size(u16 gmch_ctrl) |
2267 | { | |
2268 | gmch_ctrl >>= SNB_GMCH_GMS_SHIFT; | |
2269 | gmch_ctrl &= SNB_GMCH_GMS_MASK; | |
2270 | ||
2271 | /* | |
2272 | * 0x0 to 0x10: 32MB increments starting at 0MB | |
2273 | * 0x11 to 0x16: 4MB increments starting at 8MB | |
2274 | * 0x17 to 0x1d: 4MB increments start at 36MB | |
2275 | */ | |
2276 | if (gmch_ctrl < 0x11) | |
2277 | return gmch_ctrl << 25; | |
2278 | else if (gmch_ctrl < 0x17) | |
2279 | return (gmch_ctrl - 0x11 + 2) << 22; | |
2280 | else | |
2281 | return (gmch_ctrl - 0x17 + 9) << 22; | |
2282 | } | |
2283 | ||
66375014 DL |
2284 | static size_t gen9_get_stolen_size(u16 gen9_gmch_ctl) |
2285 | { | |
2286 | gen9_gmch_ctl >>= BDW_GMCH_GMS_SHIFT; | |
2287 | gen9_gmch_ctl &= BDW_GMCH_GMS_MASK; | |
2288 | ||
2289 | if (gen9_gmch_ctl < 0xf0) | |
2290 | return gen9_gmch_ctl << 25; /* 32 MB units */ | |
2291 | else | |
2292 | /* 4MB increments starting at 0xf0 for 4MB */ | |
2293 | return (gen9_gmch_ctl - 0xf0 + 1) << 22; | |
2294 | } | |
2295 | ||
63340133 BW |
2296 | static int ggtt_probe_common(struct drm_device *dev, |
2297 | size_t gtt_size) | |
2298 | { | |
2299 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4ad2af1e | 2300 | struct i915_page_scratch *scratch_page; |
21c34607 | 2301 | phys_addr_t gtt_phys_addr; |
63340133 BW |
2302 | |
2303 | /* For Modern GENs the PTEs and register space are split in the BAR */ | |
21c34607 | 2304 | gtt_phys_addr = pci_resource_start(dev->pdev, 0) + |
63340133 BW |
2305 | (pci_resource_len(dev->pdev, 0) / 2); |
2306 | ||
2a073f89 ID |
2307 | /* |
2308 | * On BXT writes larger than 64 bit to the GTT pagetable range will be | |
2309 | * dropped. For WC mappings in general we have 64 byte burst writes | |
2310 | * when the WC buffer is flushed, so we can't use it, but have to | |
2311 | * resort to an uncached mapping. The WC issue is easily caught by the | |
2312 | * readback check when writing GTT PTE entries. | |
2313 | */ | |
2314 | if (IS_BROXTON(dev)) | |
2315 | dev_priv->gtt.gsm = ioremap_nocache(gtt_phys_addr, gtt_size); | |
2316 | else | |
2317 | dev_priv->gtt.gsm = ioremap_wc(gtt_phys_addr, gtt_size); | |
63340133 BW |
2318 | if (!dev_priv->gtt.gsm) { |
2319 | DRM_ERROR("Failed to map the gtt page table\n"); | |
2320 | return -ENOMEM; | |
2321 | } | |
2322 | ||
4ad2af1e MK |
2323 | scratch_page = alloc_scratch_page(dev); |
2324 | if (IS_ERR(scratch_page)) { | |
63340133 BW |
2325 | DRM_ERROR("Scratch setup failed\n"); |
2326 | /* iounmap will also get called at remove, but meh */ | |
2327 | iounmap(dev_priv->gtt.gsm); | |
4ad2af1e | 2328 | return PTR_ERR(scratch_page); |
63340133 BW |
2329 | } |
2330 | ||
4ad2af1e MK |
2331 | dev_priv->gtt.base.scratch_page = scratch_page; |
2332 | ||
2333 | return 0; | |
63340133 BW |
2334 | } |
2335 | ||
fbe5d36e BW |
2336 | /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability |
2337 | * bits. When using advanced contexts each context stores its own PAT, but | |
2338 | * writing this data shouldn't be harmful even in those cases. */ | |
ee0ce478 | 2339 | static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv) |
fbe5d36e | 2340 | { |
fbe5d36e BW |
2341 | uint64_t pat; |
2342 | ||
2343 | pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC) | /* for normal objects, no eLLC */ | |
2344 | GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something pointing to ptes? */ | |
2345 | GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC) | /* for scanout with eLLC */ | |
2346 | GEN8_PPAT(3, GEN8_PPAT_UC) | /* Uncached objects, mostly for scanout */ | |
2347 | GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) | | |
2348 | GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) | | |
2349 | GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) | | |
2350 | GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3)); | |
2351 | ||
d6a8b72e RV |
2352 | if (!USES_PPGTT(dev_priv->dev)) |
2353 | /* Spec: "For GGTT, there is NO pat_sel[2:0] from the entry, | |
2354 | * so RTL will always use the value corresponding to | |
2355 | * pat_sel = 000". | |
2356 | * So let's disable cache for GGTT to avoid screen corruptions. | |
2357 | * MOCS still can be used though. | |
2358 | * - System agent ggtt writes (i.e. cpu gtt mmaps) already work | |
2359 | * before this patch, i.e. the same uncached + snooping access | |
2360 | * like on gen6/7 seems to be in effect. | |
2361 | * - So this just fixes blitter/render access. Again it looks | |
2362 | * like it's not just uncached access, but uncached + snooping. | |
2363 | * So we can still hold onto all our assumptions wrt cpu | |
2364 | * clflushing on LLC machines. | |
2365 | */ | |
2366 | pat = GEN8_PPAT(0, GEN8_PPAT_UC); | |
2367 | ||
fbe5d36e BW |
2368 | /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b |
2369 | * write would work. */ | |
2370 | I915_WRITE(GEN8_PRIVATE_PAT, pat); | |
2371 | I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32); | |
2372 | } | |
2373 | ||
ee0ce478 VS |
2374 | static void chv_setup_private_ppat(struct drm_i915_private *dev_priv) |
2375 | { | |
2376 | uint64_t pat; | |
2377 | ||
2378 | /* | |
2379 | * Map WB on BDW to snooped on CHV. | |
2380 | * | |
2381 | * Only the snoop bit has meaning for CHV, the rest is | |
2382 | * ignored. | |
2383 | * | |
cf3d262e VS |
2384 | * The hardware will never snoop for certain types of accesses: |
2385 | * - CPU GTT (GMADR->GGTT->no snoop->memory) | |
2386 | * - PPGTT page tables | |
2387 | * - some other special cycles | |
2388 | * | |
2389 | * As with BDW, we also need to consider the following for GT accesses: | |
2390 | * "For GGTT, there is NO pat_sel[2:0] from the entry, | |
2391 | * so RTL will always use the value corresponding to | |
2392 | * pat_sel = 000". | |
2393 | * Which means we must set the snoop bit in PAT entry 0 | |
2394 | * in order to keep the global status page working. | |
ee0ce478 VS |
2395 | */ |
2396 | pat = GEN8_PPAT(0, CHV_PPAT_SNOOP) | | |
2397 | GEN8_PPAT(1, 0) | | |
2398 | GEN8_PPAT(2, 0) | | |
2399 | GEN8_PPAT(3, 0) | | |
2400 | GEN8_PPAT(4, CHV_PPAT_SNOOP) | | |
2401 | GEN8_PPAT(5, CHV_PPAT_SNOOP) | | |
2402 | GEN8_PPAT(6, CHV_PPAT_SNOOP) | | |
2403 | GEN8_PPAT(7, CHV_PPAT_SNOOP); | |
2404 | ||
2405 | I915_WRITE(GEN8_PRIVATE_PAT, pat); | |
2406 | I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32); | |
2407 | } | |
2408 | ||
63340133 | 2409 | static int gen8_gmch_probe(struct drm_device *dev, |
c44ef60e | 2410 | u64 *gtt_total, |
63340133 BW |
2411 | size_t *stolen, |
2412 | phys_addr_t *mappable_base, | |
c44ef60e | 2413 | u64 *mappable_end) |
63340133 BW |
2414 | { |
2415 | struct drm_i915_private *dev_priv = dev->dev_private; | |
c44ef60e | 2416 | u64 gtt_size; |
63340133 BW |
2417 | u16 snb_gmch_ctl; |
2418 | int ret; | |
2419 | ||
2420 | /* TODO: We're not aware of mappable constraints on gen8 yet */ | |
2421 | *mappable_base = pci_resource_start(dev->pdev, 2); | |
2422 | *mappable_end = pci_resource_len(dev->pdev, 2); | |
2423 | ||
2424 | if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(39))) | |
2425 | pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(39)); | |
2426 | ||
2427 | pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl); | |
2428 | ||
66375014 DL |
2429 | if (INTEL_INFO(dev)->gen >= 9) { |
2430 | *stolen = gen9_get_stolen_size(snb_gmch_ctl); | |
2431 | gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl); | |
2432 | } else if (IS_CHERRYVIEW(dev)) { | |
d7f25f23 DL |
2433 | *stolen = chv_get_stolen_size(snb_gmch_ctl); |
2434 | gtt_size = chv_get_total_gtt_size(snb_gmch_ctl); | |
2435 | } else { | |
2436 | *stolen = gen8_get_stolen_size(snb_gmch_ctl); | |
2437 | gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl); | |
2438 | } | |
63340133 | 2439 | |
07749ef3 | 2440 | *gtt_total = (gtt_size / sizeof(gen8_pte_t)) << PAGE_SHIFT; |
63340133 | 2441 | |
5a4e33a3 | 2442 | if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev)) |
ee0ce478 VS |
2443 | chv_setup_private_ppat(dev_priv); |
2444 | else | |
2445 | bdw_setup_private_ppat(dev_priv); | |
fbe5d36e | 2446 | |
63340133 BW |
2447 | ret = ggtt_probe_common(dev, gtt_size); |
2448 | ||
94ec8f61 BW |
2449 | dev_priv->gtt.base.clear_range = gen8_ggtt_clear_range; |
2450 | dev_priv->gtt.base.insert_entries = gen8_ggtt_insert_entries; | |
777dc5bb DV |
2451 | dev_priv->gtt.base.bind_vma = ggtt_bind_vma; |
2452 | dev_priv->gtt.base.unbind_vma = ggtt_unbind_vma; | |
63340133 BW |
2453 | |
2454 | return ret; | |
2455 | } | |
2456 | ||
baa09f5f | 2457 | static int gen6_gmch_probe(struct drm_device *dev, |
c44ef60e | 2458 | u64 *gtt_total, |
41907ddc BW |
2459 | size_t *stolen, |
2460 | phys_addr_t *mappable_base, | |
c44ef60e | 2461 | u64 *mappable_end) |
e76e9aeb BW |
2462 | { |
2463 | struct drm_i915_private *dev_priv = dev->dev_private; | |
baa09f5f | 2464 | unsigned int gtt_size; |
e76e9aeb | 2465 | u16 snb_gmch_ctl; |
e76e9aeb BW |
2466 | int ret; |
2467 | ||
41907ddc BW |
2468 | *mappable_base = pci_resource_start(dev->pdev, 2); |
2469 | *mappable_end = pci_resource_len(dev->pdev, 2); | |
2470 | ||
baa09f5f BW |
2471 | /* 64/512MB is the current min/max we actually know of, but this is just |
2472 | * a coarse sanity check. | |
e76e9aeb | 2473 | */ |
41907ddc | 2474 | if ((*mappable_end < (64<<20) || (*mappable_end > (512<<20)))) { |
c44ef60e | 2475 | DRM_ERROR("Unknown GMADR size (%llx)\n", |
baa09f5f BW |
2476 | dev_priv->gtt.mappable_end); |
2477 | return -ENXIO; | |
e76e9aeb BW |
2478 | } |
2479 | ||
e76e9aeb BW |
2480 | if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40))) |
2481 | pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40)); | |
e76e9aeb | 2482 | pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl); |
e76e9aeb | 2483 | |
c4ae25ec | 2484 | *stolen = gen6_get_stolen_size(snb_gmch_ctl); |
a93e4161 | 2485 | |
63340133 | 2486 | gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl); |
07749ef3 | 2487 | *gtt_total = (gtt_size / sizeof(gen6_pte_t)) << PAGE_SHIFT; |
e76e9aeb | 2488 | |
63340133 | 2489 | ret = ggtt_probe_common(dev, gtt_size); |
e76e9aeb | 2490 | |
853ba5d2 BW |
2491 | dev_priv->gtt.base.clear_range = gen6_ggtt_clear_range; |
2492 | dev_priv->gtt.base.insert_entries = gen6_ggtt_insert_entries; | |
777dc5bb DV |
2493 | dev_priv->gtt.base.bind_vma = ggtt_bind_vma; |
2494 | dev_priv->gtt.base.unbind_vma = ggtt_unbind_vma; | |
7faf1ab2 | 2495 | |
e76e9aeb BW |
2496 | return ret; |
2497 | } | |
2498 | ||
853ba5d2 | 2499 | static void gen6_gmch_remove(struct i915_address_space *vm) |
e76e9aeb | 2500 | { |
853ba5d2 BW |
2501 | |
2502 | struct i915_gtt *gtt = container_of(vm, struct i915_gtt, base); | |
5ed16782 | 2503 | |
853ba5d2 | 2504 | iounmap(gtt->gsm); |
4ad2af1e | 2505 | free_scratch_page(vm->dev, vm->scratch_page); |
644ec02b | 2506 | } |
baa09f5f BW |
2507 | |
2508 | static int i915_gmch_probe(struct drm_device *dev, | |
c44ef60e | 2509 | u64 *gtt_total, |
41907ddc BW |
2510 | size_t *stolen, |
2511 | phys_addr_t *mappable_base, | |
c44ef60e | 2512 | u64 *mappable_end) |
baa09f5f BW |
2513 | { |
2514 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2515 | int ret; | |
2516 | ||
baa09f5f BW |
2517 | ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->dev->pdev, NULL); |
2518 | if (!ret) { | |
2519 | DRM_ERROR("failed to set up gmch\n"); | |
2520 | return -EIO; | |
2521 | } | |
2522 | ||
41907ddc | 2523 | intel_gtt_get(gtt_total, stolen, mappable_base, mappable_end); |
baa09f5f BW |
2524 | |
2525 | dev_priv->gtt.do_idle_maps = needs_idle_maps(dev_priv->dev); | |
d369d2d9 | 2526 | dev_priv->gtt.base.insert_entries = i915_ggtt_insert_entries; |
853ba5d2 | 2527 | dev_priv->gtt.base.clear_range = i915_ggtt_clear_range; |
d369d2d9 DV |
2528 | dev_priv->gtt.base.bind_vma = ggtt_bind_vma; |
2529 | dev_priv->gtt.base.unbind_vma = ggtt_unbind_vma; | |
baa09f5f | 2530 | |
c0a7f818 CW |
2531 | if (unlikely(dev_priv->gtt.do_idle_maps)) |
2532 | DRM_INFO("applying Ironlake quirks for intel_iommu\n"); | |
2533 | ||
baa09f5f BW |
2534 | return 0; |
2535 | } | |
2536 | ||
853ba5d2 | 2537 | static void i915_gmch_remove(struct i915_address_space *vm) |
baa09f5f BW |
2538 | { |
2539 | intel_gmch_remove(); | |
2540 | } | |
2541 | ||
2542 | int i915_gem_gtt_init(struct drm_device *dev) | |
2543 | { | |
2544 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2545 | struct i915_gtt *gtt = &dev_priv->gtt; | |
baa09f5f BW |
2546 | int ret; |
2547 | ||
baa09f5f | 2548 | if (INTEL_INFO(dev)->gen <= 5) { |
b2f21b4d | 2549 | gtt->gtt_probe = i915_gmch_probe; |
853ba5d2 | 2550 | gtt->base.cleanup = i915_gmch_remove; |
63340133 | 2551 | } else if (INTEL_INFO(dev)->gen < 8) { |
b2f21b4d | 2552 | gtt->gtt_probe = gen6_gmch_probe; |
853ba5d2 | 2553 | gtt->base.cleanup = gen6_gmch_remove; |
4d15c145 | 2554 | if (IS_HASWELL(dev) && dev_priv->ellc_size) |
853ba5d2 | 2555 | gtt->base.pte_encode = iris_pte_encode; |
4d15c145 | 2556 | else if (IS_HASWELL(dev)) |
853ba5d2 | 2557 | gtt->base.pte_encode = hsw_pte_encode; |
b2f21b4d | 2558 | else if (IS_VALLEYVIEW(dev)) |
853ba5d2 | 2559 | gtt->base.pte_encode = byt_pte_encode; |
350ec881 CW |
2560 | else if (INTEL_INFO(dev)->gen >= 7) |
2561 | gtt->base.pte_encode = ivb_pte_encode; | |
b2f21b4d | 2562 | else |
350ec881 | 2563 | gtt->base.pte_encode = snb_pte_encode; |
63340133 BW |
2564 | } else { |
2565 | dev_priv->gtt.gtt_probe = gen8_gmch_probe; | |
2566 | dev_priv->gtt.base.cleanup = gen6_gmch_remove; | |
baa09f5f BW |
2567 | } |
2568 | ||
c114f76a MK |
2569 | gtt->base.dev = dev; |
2570 | ||
853ba5d2 | 2571 | ret = gtt->gtt_probe(dev, >t->base.total, >t->stolen_size, |
b2f21b4d | 2572 | >t->mappable_base, >t->mappable_end); |
a54c0c27 | 2573 | if (ret) |
baa09f5f | 2574 | return ret; |
baa09f5f | 2575 | |
baa09f5f | 2576 | /* GMADR is the PCI mmio aperture into the global GTT. */ |
c44ef60e | 2577 | DRM_INFO("Memory usable by graphics device = %lluM\n", |
853ba5d2 | 2578 | gtt->base.total >> 20); |
c44ef60e | 2579 | DRM_DEBUG_DRIVER("GMADR size = %lldM\n", gtt->mappable_end >> 20); |
b2f21b4d | 2580 | DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt->stolen_size >> 20); |
5db6c735 DV |
2581 | #ifdef CONFIG_INTEL_IOMMU |
2582 | if (intel_iommu_gfx_mapped) | |
2583 | DRM_INFO("VT-d active for gfx access\n"); | |
2584 | #endif | |
cfa7c862 DV |
2585 | /* |
2586 | * i915.enable_ppgtt is read-only, so do an early pass to validate the | |
2587 | * user's requested state against the hardware/driver capabilities. We | |
2588 | * do this now so that we can print out any log messages once rather | |
2589 | * than every time we check intel_enable_ppgtt(). | |
2590 | */ | |
2591 | i915.enable_ppgtt = sanitize_enable_ppgtt(dev, i915.enable_ppgtt); | |
2592 | DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915.enable_ppgtt); | |
baa09f5f BW |
2593 | |
2594 | return 0; | |
2595 | } | |
6f65e29a | 2596 | |
fa42331b DV |
2597 | void i915_gem_restore_gtt_mappings(struct drm_device *dev) |
2598 | { | |
2599 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2600 | struct drm_i915_gem_object *obj; | |
2601 | struct i915_address_space *vm; | |
2c3d9984 TU |
2602 | struct i915_vma *vma; |
2603 | bool flush; | |
fa42331b DV |
2604 | |
2605 | i915_check_and_clear_faults(dev); | |
2606 | ||
2607 | /* First fill our portion of the GTT with scratch pages */ | |
2608 | dev_priv->gtt.base.clear_range(&dev_priv->gtt.base, | |
2609 | dev_priv->gtt.base.start, | |
2610 | dev_priv->gtt.base.total, | |
2611 | true); | |
2612 | ||
2c3d9984 TU |
2613 | /* Cache flush objects bound into GGTT and rebind them. */ |
2614 | vm = &dev_priv->gtt.base; | |
fa42331b | 2615 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
2c3d9984 TU |
2616 | flush = false; |
2617 | list_for_each_entry(vma, &obj->vma_list, vma_link) { | |
2618 | if (vma->vm != vm) | |
2619 | continue; | |
fa42331b | 2620 | |
2c3d9984 TU |
2621 | WARN_ON(i915_vma_bind(vma, obj->cache_level, |
2622 | PIN_UPDATE)); | |
fa42331b | 2623 | |
2c3d9984 TU |
2624 | flush = true; |
2625 | } | |
2626 | ||
2627 | if (flush) | |
2628 | i915_gem_clflush_object(obj, obj->pin_display); | |
2629 | } | |
fa42331b DV |
2630 | |
2631 | if (INTEL_INFO(dev)->gen >= 8) { | |
2632 | if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev)) | |
2633 | chv_setup_private_ppat(dev_priv); | |
2634 | else | |
2635 | bdw_setup_private_ppat(dev_priv); | |
2636 | ||
2637 | return; | |
2638 | } | |
2639 | ||
2640 | if (USES_PPGTT(dev)) { | |
2641 | list_for_each_entry(vm, &dev_priv->vm_list, global_link) { | |
2642 | /* TODO: Perhaps it shouldn't be gen6 specific */ | |
2643 | ||
2644 | struct i915_hw_ppgtt *ppgtt = | |
2645 | container_of(vm, struct i915_hw_ppgtt, | |
2646 | base); | |
2647 | ||
2648 | if (i915_is_ggtt(vm)) | |
2649 | ppgtt = dev_priv->mm.aliasing_ppgtt; | |
2650 | ||
2651 | gen6_write_page_range(dev_priv, &ppgtt->pd, | |
2652 | 0, ppgtt->base.total); | |
2653 | } | |
2654 | } | |
2655 | ||
2656 | i915_ggtt_flush(dev_priv); | |
2657 | } | |
2658 | ||
ec7adb6e JL |
2659 | static struct i915_vma * |
2660 | __i915_gem_vma_create(struct drm_i915_gem_object *obj, | |
2661 | struct i915_address_space *vm, | |
2662 | const struct i915_ggtt_view *ggtt_view) | |
6f65e29a | 2663 | { |
dabde5c7 | 2664 | struct i915_vma *vma; |
6f65e29a | 2665 | |
ec7adb6e JL |
2666 | if (WARN_ON(i915_is_ggtt(vm) != !!ggtt_view)) |
2667 | return ERR_PTR(-EINVAL); | |
e20d2ab7 CW |
2668 | |
2669 | vma = kmem_cache_zalloc(to_i915(obj->base.dev)->vmas, GFP_KERNEL); | |
dabde5c7 DC |
2670 | if (vma == NULL) |
2671 | return ERR_PTR(-ENOMEM); | |
ec7adb6e | 2672 | |
6f65e29a BW |
2673 | INIT_LIST_HEAD(&vma->vma_link); |
2674 | INIT_LIST_HEAD(&vma->mm_list); | |
2675 | INIT_LIST_HEAD(&vma->exec_list); | |
2676 | vma->vm = vm; | |
2677 | vma->obj = obj; | |
2678 | ||
777dc5bb | 2679 | if (i915_is_ggtt(vm)) |
ec7adb6e | 2680 | vma->ggtt_view = *ggtt_view; |
6f65e29a | 2681 | |
f7635669 TU |
2682 | list_add_tail(&vma->vma_link, &obj->vma_list); |
2683 | if (!i915_is_ggtt(vm)) | |
e07f0552 | 2684 | i915_ppgtt_get(i915_vm_to_ppgtt(vm)); |
6f65e29a BW |
2685 | |
2686 | return vma; | |
2687 | } | |
2688 | ||
2689 | struct i915_vma * | |
ec7adb6e JL |
2690 | i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj, |
2691 | struct i915_address_space *vm) | |
2692 | { | |
2693 | struct i915_vma *vma; | |
2694 | ||
2695 | vma = i915_gem_obj_to_vma(obj, vm); | |
2696 | if (!vma) | |
2697 | vma = __i915_gem_vma_create(obj, vm, | |
2698 | i915_is_ggtt(vm) ? &i915_ggtt_view_normal : NULL); | |
2699 | ||
2700 | return vma; | |
2701 | } | |
2702 | ||
2703 | struct i915_vma * | |
2704 | i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object *obj, | |
fe14d5f4 | 2705 | const struct i915_ggtt_view *view) |
6f65e29a | 2706 | { |
ec7adb6e | 2707 | struct i915_address_space *ggtt = i915_obj_to_ggtt(obj); |
6f65e29a BW |
2708 | struct i915_vma *vma; |
2709 | ||
ec7adb6e JL |
2710 | if (WARN_ON(!view)) |
2711 | return ERR_PTR(-EINVAL); | |
2712 | ||
2713 | vma = i915_gem_obj_to_ggtt_view(obj, view); | |
2714 | ||
2715 | if (IS_ERR(vma)) | |
2716 | return vma; | |
2717 | ||
6f65e29a | 2718 | if (!vma) |
ec7adb6e | 2719 | vma = __i915_gem_vma_create(obj, ggtt, view); |
6f65e29a BW |
2720 | |
2721 | return vma; | |
ec7adb6e | 2722 | |
6f65e29a | 2723 | } |
fe14d5f4 | 2724 | |
50470bb0 TU |
2725 | static void |
2726 | rotate_pages(dma_addr_t *in, unsigned int width, unsigned int height, | |
2727 | struct sg_table *st) | |
2728 | { | |
2729 | unsigned int column, row; | |
2730 | unsigned int src_idx; | |
2731 | struct scatterlist *sg = st->sgl; | |
2732 | ||
2733 | st->nents = 0; | |
2734 | ||
2735 | for (column = 0; column < width; column++) { | |
2736 | src_idx = width * (height - 1) + column; | |
2737 | for (row = 0; row < height; row++) { | |
2738 | st->nents++; | |
2739 | /* We don't need the pages, but need to initialize | |
2740 | * the entries so the sg list can be happily traversed. | |
2741 | * The only thing we need are DMA addresses. | |
2742 | */ | |
2743 | sg_set_page(sg, NULL, PAGE_SIZE, 0); | |
2744 | sg_dma_address(sg) = in[src_idx]; | |
2745 | sg_dma_len(sg) = PAGE_SIZE; | |
2746 | sg = sg_next(sg); | |
2747 | src_idx -= width; | |
2748 | } | |
2749 | } | |
2750 | } | |
2751 | ||
2752 | static struct sg_table * | |
2753 | intel_rotate_fb_obj_pages(struct i915_ggtt_view *ggtt_view, | |
2754 | struct drm_i915_gem_object *obj) | |
2755 | { | |
50470bb0 | 2756 | struct intel_rotation_info *rot_info = &ggtt_view->rotation_info; |
84fe03f7 | 2757 | unsigned int size_pages = rot_info->size >> PAGE_SHIFT; |
50470bb0 TU |
2758 | struct sg_page_iter sg_iter; |
2759 | unsigned long i; | |
2760 | dma_addr_t *page_addr_list; | |
2761 | struct sg_table *st; | |
1d00dad5 | 2762 | int ret = -ENOMEM; |
50470bb0 | 2763 | |
50470bb0 | 2764 | /* Allocate a temporary list of source pages for random access. */ |
84fe03f7 TU |
2765 | page_addr_list = drm_malloc_ab(obj->base.size / PAGE_SIZE, |
2766 | sizeof(dma_addr_t)); | |
50470bb0 TU |
2767 | if (!page_addr_list) |
2768 | return ERR_PTR(ret); | |
2769 | ||
2770 | /* Allocate target SG list. */ | |
2771 | st = kmalloc(sizeof(*st), GFP_KERNEL); | |
2772 | if (!st) | |
2773 | goto err_st_alloc; | |
2774 | ||
84fe03f7 | 2775 | ret = sg_alloc_table(st, size_pages, GFP_KERNEL); |
50470bb0 TU |
2776 | if (ret) |
2777 | goto err_sg_alloc; | |
2778 | ||
2779 | /* Populate source page list from the object. */ | |
2780 | i = 0; | |
2781 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) { | |
2782 | page_addr_list[i] = sg_page_iter_dma_address(&sg_iter); | |
2783 | i++; | |
2784 | } | |
2785 | ||
2786 | /* Rotate the pages. */ | |
84fe03f7 TU |
2787 | rotate_pages(page_addr_list, |
2788 | rot_info->width_pages, rot_info->height_pages, | |
2789 | st); | |
50470bb0 TU |
2790 | |
2791 | DRM_DEBUG_KMS( | |
84fe03f7 | 2792 | "Created rotated page mapping for object size %zu (pitch=%u, height=%u, pixel_format=0x%x, %ux%u tiles, %u pages).\n", |
c9f8fd2d | 2793 | obj->base.size, rot_info->pitch, rot_info->height, |
84fe03f7 TU |
2794 | rot_info->pixel_format, rot_info->width_pages, |
2795 | rot_info->height_pages, size_pages); | |
50470bb0 TU |
2796 | |
2797 | drm_free_large(page_addr_list); | |
2798 | ||
2799 | return st; | |
2800 | ||
2801 | err_sg_alloc: | |
2802 | kfree(st); | |
2803 | err_st_alloc: | |
2804 | drm_free_large(page_addr_list); | |
2805 | ||
2806 | DRM_DEBUG_KMS( | |
84fe03f7 | 2807 | "Failed to create rotated mapping for object size %zu! (%d) (pitch=%u, height=%u, pixel_format=0x%x, %ux%u tiles, %u pages)\n", |
c9f8fd2d | 2808 | obj->base.size, ret, rot_info->pitch, rot_info->height, |
84fe03f7 TU |
2809 | rot_info->pixel_format, rot_info->width_pages, |
2810 | rot_info->height_pages, size_pages); | |
50470bb0 TU |
2811 | return ERR_PTR(ret); |
2812 | } | |
ec7adb6e | 2813 | |
8bd7ef16 JL |
2814 | static struct sg_table * |
2815 | intel_partial_pages(const struct i915_ggtt_view *view, | |
2816 | struct drm_i915_gem_object *obj) | |
2817 | { | |
2818 | struct sg_table *st; | |
2819 | struct scatterlist *sg; | |
2820 | struct sg_page_iter obj_sg_iter; | |
2821 | int ret = -ENOMEM; | |
2822 | ||
2823 | st = kmalloc(sizeof(*st), GFP_KERNEL); | |
2824 | if (!st) | |
2825 | goto err_st_alloc; | |
2826 | ||
2827 | ret = sg_alloc_table(st, view->params.partial.size, GFP_KERNEL); | |
2828 | if (ret) | |
2829 | goto err_sg_alloc; | |
2830 | ||
2831 | sg = st->sgl; | |
2832 | st->nents = 0; | |
2833 | for_each_sg_page(obj->pages->sgl, &obj_sg_iter, obj->pages->nents, | |
2834 | view->params.partial.offset) | |
2835 | { | |
2836 | if (st->nents >= view->params.partial.size) | |
2837 | break; | |
2838 | ||
2839 | sg_set_page(sg, NULL, PAGE_SIZE, 0); | |
2840 | sg_dma_address(sg) = sg_page_iter_dma_address(&obj_sg_iter); | |
2841 | sg_dma_len(sg) = PAGE_SIZE; | |
2842 | ||
2843 | sg = sg_next(sg); | |
2844 | st->nents++; | |
2845 | } | |
2846 | ||
2847 | return st; | |
2848 | ||
2849 | err_sg_alloc: | |
2850 | kfree(st); | |
2851 | err_st_alloc: | |
2852 | return ERR_PTR(ret); | |
2853 | } | |
2854 | ||
70b9f6f8 | 2855 | static int |
50470bb0 | 2856 | i915_get_ggtt_vma_pages(struct i915_vma *vma) |
fe14d5f4 | 2857 | { |
50470bb0 TU |
2858 | int ret = 0; |
2859 | ||
fe14d5f4 TU |
2860 | if (vma->ggtt_view.pages) |
2861 | return 0; | |
2862 | ||
2863 | if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) | |
2864 | vma->ggtt_view.pages = vma->obj->pages; | |
50470bb0 TU |
2865 | else if (vma->ggtt_view.type == I915_GGTT_VIEW_ROTATED) |
2866 | vma->ggtt_view.pages = | |
2867 | intel_rotate_fb_obj_pages(&vma->ggtt_view, vma->obj); | |
8bd7ef16 JL |
2868 | else if (vma->ggtt_view.type == I915_GGTT_VIEW_PARTIAL) |
2869 | vma->ggtt_view.pages = | |
2870 | intel_partial_pages(&vma->ggtt_view, vma->obj); | |
fe14d5f4 TU |
2871 | else |
2872 | WARN_ONCE(1, "GGTT view %u not implemented!\n", | |
2873 | vma->ggtt_view.type); | |
2874 | ||
2875 | if (!vma->ggtt_view.pages) { | |
ec7adb6e | 2876 | DRM_ERROR("Failed to get pages for GGTT view type %u!\n", |
fe14d5f4 | 2877 | vma->ggtt_view.type); |
50470bb0 TU |
2878 | ret = -EINVAL; |
2879 | } else if (IS_ERR(vma->ggtt_view.pages)) { | |
2880 | ret = PTR_ERR(vma->ggtt_view.pages); | |
2881 | vma->ggtt_view.pages = NULL; | |
2882 | DRM_ERROR("Failed to get pages for VMA view type %u (%d)!\n", | |
2883 | vma->ggtt_view.type, ret); | |
fe14d5f4 TU |
2884 | } |
2885 | ||
50470bb0 | 2886 | return ret; |
fe14d5f4 TU |
2887 | } |
2888 | ||
2889 | /** | |
2890 | * i915_vma_bind - Sets up PTEs for an VMA in it's corresponding address space. | |
2891 | * @vma: VMA to map | |
2892 | * @cache_level: mapping cache level | |
2893 | * @flags: flags like global or local mapping | |
2894 | * | |
2895 | * DMA addresses are taken from the scatter-gather table of this object (or of | |
2896 | * this VMA in case of non-default GGTT views) and PTE entries set up. | |
2897 | * Note that DMA addresses are also the only part of the SG table we care about. | |
2898 | */ | |
2899 | int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level, | |
2900 | u32 flags) | |
2901 | { | |
75d04a37 MK |
2902 | int ret; |
2903 | u32 bind_flags; | |
1d335d1b | 2904 | |
75d04a37 MK |
2905 | if (WARN_ON(flags == 0)) |
2906 | return -EINVAL; | |
1d335d1b | 2907 | |
75d04a37 | 2908 | bind_flags = 0; |
0875546c DV |
2909 | if (flags & PIN_GLOBAL) |
2910 | bind_flags |= GLOBAL_BIND; | |
2911 | if (flags & PIN_USER) | |
2912 | bind_flags |= LOCAL_BIND; | |
2913 | ||
2914 | if (flags & PIN_UPDATE) | |
2915 | bind_flags |= vma->bound; | |
2916 | else | |
2917 | bind_flags &= ~vma->bound; | |
2918 | ||
75d04a37 MK |
2919 | if (bind_flags == 0) |
2920 | return 0; | |
2921 | ||
2922 | if (vma->bound == 0 && vma->vm->allocate_va_range) { | |
2923 | trace_i915_va_alloc(vma->vm, | |
2924 | vma->node.start, | |
2925 | vma->node.size, | |
2926 | VM_TO_TRACE_NAME(vma->vm)); | |
2927 | ||
b2dd4511 MK |
2928 | /* XXX: i915_vma_pin() will fix this +- hack */ |
2929 | vma->pin_count++; | |
75d04a37 MK |
2930 | ret = vma->vm->allocate_va_range(vma->vm, |
2931 | vma->node.start, | |
2932 | vma->node.size); | |
b2dd4511 | 2933 | vma->pin_count--; |
75d04a37 MK |
2934 | if (ret) |
2935 | return ret; | |
2936 | } | |
2937 | ||
2938 | ret = vma->vm->bind_vma(vma, cache_level, bind_flags); | |
70b9f6f8 DV |
2939 | if (ret) |
2940 | return ret; | |
0875546c DV |
2941 | |
2942 | vma->bound |= bind_flags; | |
fe14d5f4 TU |
2943 | |
2944 | return 0; | |
2945 | } | |
91e6711e JL |
2946 | |
2947 | /** | |
2948 | * i915_ggtt_view_size - Get the size of a GGTT view. | |
2949 | * @obj: Object the view is of. | |
2950 | * @view: The view in question. | |
2951 | * | |
2952 | * @return The size of the GGTT view in bytes. | |
2953 | */ | |
2954 | size_t | |
2955 | i915_ggtt_view_size(struct drm_i915_gem_object *obj, | |
2956 | const struct i915_ggtt_view *view) | |
2957 | { | |
9e759ff1 | 2958 | if (view->type == I915_GGTT_VIEW_NORMAL) { |
91e6711e | 2959 | return obj->base.size; |
9e759ff1 TU |
2960 | } else if (view->type == I915_GGTT_VIEW_ROTATED) { |
2961 | return view->rotation_info.size; | |
8bd7ef16 JL |
2962 | } else if (view->type == I915_GGTT_VIEW_PARTIAL) { |
2963 | return view->params.partial.size << PAGE_SHIFT; | |
91e6711e JL |
2964 | } else { |
2965 | WARN_ONCE(1, "GGTT view %u not implemented!\n", view->type); | |
2966 | return obj->base.size; | |
2967 | } | |
2968 | } |