]>
Commit | Line | Data |
---|---|---|
76aaf220 DV |
1 | /* |
2 | * Copyright © 2010 Daniel Vetter | |
c4ac524c | 3 | * Copyright © 2011-2014 Intel Corporation |
76aaf220 DV |
4 | * |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
22 | * IN THE SOFTWARE. | |
23 | * | |
24 | */ | |
25 | ||
e007b19d | 26 | #include <linux/log2.h> |
606fec95 | 27 | #include <linux/random.h> |
0e46ce2e | 28 | #include <linux/seq_file.h> |
5bab6f60 | 29 | #include <linux/stop_machine.h> |
e007b19d | 30 | |
760285e7 DH |
31 | #include <drm/drmP.h> |
32 | #include <drm/i915_drm.h> | |
e007b19d | 33 | |
76aaf220 | 34 | #include "i915_drv.h" |
5dda8fa3 | 35 | #include "i915_vgpu.h" |
76aaf220 DV |
36 | #include "i915_trace.h" |
37 | #include "intel_drv.h" | |
d07f0e59 | 38 | #include "intel_frontbuffer.h" |
76aaf220 | 39 | |
bb8f9cff CW |
40 | #define I915_GFP_DMA (GFP_KERNEL | __GFP_HIGHMEM) |
41 | ||
45f8f69a TU |
42 | /** |
43 | * DOC: Global GTT views | |
44 | * | |
45 | * Background and previous state | |
46 | * | |
47 | * Historically objects could exists (be bound) in global GTT space only as | |
48 | * singular instances with a view representing all of the object's backing pages | |
49 | * in a linear fashion. This view will be called a normal view. | |
50 | * | |
51 | * To support multiple views of the same object, where the number of mapped | |
52 | * pages is not equal to the backing store, or where the layout of the pages | |
53 | * is not linear, concept of a GGTT view was added. | |
54 | * | |
55 | * One example of an alternative view is a stereo display driven by a single | |
56 | * image. In this case we would have a framebuffer looking like this | |
57 | * (2x2 pages): | |
58 | * | |
59 | * 12 | |
60 | * 34 | |
61 | * | |
62 | * Above would represent a normal GGTT view as normally mapped for GPU or CPU | |
63 | * rendering. In contrast, fed to the display engine would be an alternative | |
64 | * view which could look something like this: | |
65 | * | |
66 | * 1212 | |
67 | * 3434 | |
68 | * | |
69 | * In this example both the size and layout of pages in the alternative view is | |
70 | * different from the normal view. | |
71 | * | |
72 | * Implementation and usage | |
73 | * | |
74 | * GGTT views are implemented using VMAs and are distinguished via enum | |
75 | * i915_ggtt_view_type and struct i915_ggtt_view. | |
76 | * | |
77 | * A new flavour of core GEM functions which work with GGTT bound objects were | |
ec7adb6e JL |
78 | * added with the _ggtt_ infix, and sometimes with _view postfix to avoid |
79 | * renaming in large amounts of code. They take the struct i915_ggtt_view | |
80 | * parameter encapsulating all metadata required to implement a view. | |
45f8f69a TU |
81 | * |
82 | * As a helper for callers which are only interested in the normal view, | |
83 | * globally const i915_ggtt_view_normal singleton instance exists. All old core | |
84 | * GEM API functions, the ones not taking the view parameter, are operating on, | |
85 | * or with the normal GGTT view. | |
86 | * | |
87 | * Code wanting to add or use a new GGTT view needs to: | |
88 | * | |
89 | * 1. Add a new enum with a suitable name. | |
90 | * 2. Extend the metadata in the i915_ggtt_view structure if required. | |
91 | * 3. Add support to i915_get_vma_pages(). | |
92 | * | |
93 | * New views are required to build a scatter-gather table from within the | |
94 | * i915_get_vma_pages function. This table is stored in the vma.ggtt_view and | |
95 | * exists for the lifetime of an VMA. | |
96 | * | |
97 | * Core API is designed to have copy semantics which means that passed in | |
98 | * struct i915_ggtt_view does not need to be persistent (left around after | |
99 | * calling the core API functions). | |
100 | * | |
101 | */ | |
102 | ||
70b9f6f8 DV |
103 | static int |
104 | i915_get_ggtt_vma_pages(struct i915_vma *vma); | |
105 | ||
b5e16987 VS |
106 | const struct i915_ggtt_view i915_ggtt_view_normal = { |
107 | .type = I915_GGTT_VIEW_NORMAL, | |
108 | }; | |
9abc4648 | 109 | const struct i915_ggtt_view i915_ggtt_view_rotated = { |
b5e16987 | 110 | .type = I915_GGTT_VIEW_ROTATED, |
9abc4648 | 111 | }; |
fe14d5f4 | 112 | |
c033666a CW |
113 | int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv, |
114 | int enable_ppgtt) | |
cfa7c862 | 115 | { |
1893a71b CW |
116 | bool has_aliasing_ppgtt; |
117 | bool has_full_ppgtt; | |
1f9a99e0 | 118 | bool has_full_48bit_ppgtt; |
1893a71b | 119 | |
9e1d0e60 MT |
120 | has_aliasing_ppgtt = dev_priv->info.has_aliasing_ppgtt; |
121 | has_full_ppgtt = dev_priv->info.has_full_ppgtt; | |
122 | has_full_48bit_ppgtt = dev_priv->info.has_full_48bit_ppgtt; | |
1893a71b | 123 | |
e320d400 ZW |
124 | if (intel_vgpu_active(dev_priv)) { |
125 | /* emulation is too hard */ | |
126 | has_full_ppgtt = false; | |
127 | has_full_48bit_ppgtt = false; | |
128 | } | |
71ba2d64 | 129 | |
0e4ca100 CW |
130 | if (!has_aliasing_ppgtt) |
131 | return 0; | |
132 | ||
70ee45e1 DL |
133 | /* |
134 | * We don't allow disabling PPGTT for gen9+ as it's a requirement for | |
135 | * execlists, the sole mechanism available to submit work. | |
136 | */ | |
c033666a | 137 | if (enable_ppgtt == 0 && INTEL_GEN(dev_priv) < 9) |
cfa7c862 DV |
138 | return 0; |
139 | ||
140 | if (enable_ppgtt == 1) | |
141 | return 1; | |
142 | ||
1893a71b | 143 | if (enable_ppgtt == 2 && has_full_ppgtt) |
cfa7c862 DV |
144 | return 2; |
145 | ||
1f9a99e0 MT |
146 | if (enable_ppgtt == 3 && has_full_48bit_ppgtt) |
147 | return 3; | |
148 | ||
93a25a9e DV |
149 | #ifdef CONFIG_INTEL_IOMMU |
150 | /* Disable ppgtt on SNB if VT-d is on. */ | |
c033666a | 151 | if (IS_GEN6(dev_priv) && intel_iommu_gfx_mapped) { |
93a25a9e | 152 | DRM_INFO("Disabling PPGTT because VT-d is on\n"); |
cfa7c862 | 153 | return 0; |
93a25a9e DV |
154 | } |
155 | #endif | |
156 | ||
62942ed7 | 157 | /* Early VLV doesn't have this */ |
91c8a326 | 158 | if (IS_VALLEYVIEW(dev_priv) && dev_priv->drm.pdev->revision < 0xb) { |
62942ed7 JB |
159 | DRM_DEBUG_DRIVER("disabling PPGTT on pre-B3 step VLV\n"); |
160 | return 0; | |
161 | } | |
162 | ||
e320d400 | 163 | if (INTEL_GEN(dev_priv) >= 8 && i915.enable_execlists && has_full_ppgtt) |
1f9a99e0 | 164 | return has_full_48bit_ppgtt ? 3 : 2; |
2f82bbdf MT |
165 | else |
166 | return has_aliasing_ppgtt ? 1 : 0; | |
93a25a9e DV |
167 | } |
168 | ||
70b9f6f8 DV |
169 | static int ppgtt_bind_vma(struct i915_vma *vma, |
170 | enum i915_cache_level cache_level, | |
171 | u32 unused) | |
47552659 DV |
172 | { |
173 | u32 pte_flags = 0; | |
174 | ||
a4f5ea64 | 175 | vma->pages = vma->obj->mm.pages; |
247177dd | 176 | |
47552659 DV |
177 | /* Currently applicable only to VLV */ |
178 | if (vma->obj->gt_ro) | |
179 | pte_flags |= PTE_READ_ONLY; | |
180 | ||
247177dd | 181 | vma->vm->insert_entries(vma->vm, vma->pages, vma->node.start, |
47552659 | 182 | cache_level, pte_flags); |
70b9f6f8 DV |
183 | |
184 | return 0; | |
47552659 DV |
185 | } |
186 | ||
187 | static void ppgtt_unbind_vma(struct i915_vma *vma) | |
188 | { | |
189 | vma->vm->clear_range(vma->vm, | |
190 | vma->node.start, | |
4fb84d99 | 191 | vma->size); |
47552659 | 192 | } |
6f65e29a | 193 | |
2c642b07 | 194 | static gen8_pte_t gen8_pte_encode(dma_addr_t addr, |
4fb84d99 | 195 | enum i915_cache_level level) |
94ec8f61 | 196 | { |
4fb84d99 | 197 | gen8_pte_t pte = _PAGE_PRESENT | _PAGE_RW; |
94ec8f61 | 198 | pte |= addr; |
63c42e56 BW |
199 | |
200 | switch (level) { | |
201 | case I915_CACHE_NONE: | |
fbe5d36e | 202 | pte |= PPAT_UNCACHED_INDEX; |
63c42e56 BW |
203 | break; |
204 | case I915_CACHE_WT: | |
205 | pte |= PPAT_DISPLAY_ELLC_INDEX; | |
206 | break; | |
207 | default: | |
208 | pte |= PPAT_CACHED_INDEX; | |
209 | break; | |
210 | } | |
211 | ||
94ec8f61 BW |
212 | return pte; |
213 | } | |
214 | ||
fe36f55d MK |
215 | static gen8_pde_t gen8_pde_encode(const dma_addr_t addr, |
216 | const enum i915_cache_level level) | |
b1fe6673 | 217 | { |
07749ef3 | 218 | gen8_pde_t pde = _PAGE_PRESENT | _PAGE_RW; |
b1fe6673 BW |
219 | pde |= addr; |
220 | if (level != I915_CACHE_NONE) | |
221 | pde |= PPAT_CACHED_PDE_INDEX; | |
222 | else | |
223 | pde |= PPAT_UNCACHED_INDEX; | |
224 | return pde; | |
225 | } | |
226 | ||
762d9936 MT |
227 | #define gen8_pdpe_encode gen8_pde_encode |
228 | #define gen8_pml4e_encode gen8_pde_encode | |
229 | ||
07749ef3 MT |
230 | static gen6_pte_t snb_pte_encode(dma_addr_t addr, |
231 | enum i915_cache_level level, | |
4fb84d99 | 232 | u32 unused) |
54d12527 | 233 | { |
4fb84d99 | 234 | gen6_pte_t pte = GEN6_PTE_VALID; |
54d12527 | 235 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
e7210c3c BW |
236 | |
237 | switch (level) { | |
350ec881 CW |
238 | case I915_CACHE_L3_LLC: |
239 | case I915_CACHE_LLC: | |
240 | pte |= GEN6_PTE_CACHE_LLC; | |
241 | break; | |
242 | case I915_CACHE_NONE: | |
243 | pte |= GEN6_PTE_UNCACHED; | |
244 | break; | |
245 | default: | |
5f77eeb0 | 246 | MISSING_CASE(level); |
350ec881 CW |
247 | } |
248 | ||
249 | return pte; | |
250 | } | |
251 | ||
07749ef3 MT |
252 | static gen6_pte_t ivb_pte_encode(dma_addr_t addr, |
253 | enum i915_cache_level level, | |
4fb84d99 | 254 | u32 unused) |
350ec881 | 255 | { |
4fb84d99 | 256 | gen6_pte_t pte = GEN6_PTE_VALID; |
350ec881 CW |
257 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
258 | ||
259 | switch (level) { | |
260 | case I915_CACHE_L3_LLC: | |
261 | pte |= GEN7_PTE_CACHE_L3_LLC; | |
e7210c3c BW |
262 | break; |
263 | case I915_CACHE_LLC: | |
264 | pte |= GEN6_PTE_CACHE_LLC; | |
265 | break; | |
266 | case I915_CACHE_NONE: | |
9119708c | 267 | pte |= GEN6_PTE_UNCACHED; |
e7210c3c BW |
268 | break; |
269 | default: | |
5f77eeb0 | 270 | MISSING_CASE(level); |
e7210c3c BW |
271 | } |
272 | ||
54d12527 BW |
273 | return pte; |
274 | } | |
275 | ||
07749ef3 MT |
276 | static gen6_pte_t byt_pte_encode(dma_addr_t addr, |
277 | enum i915_cache_level level, | |
4fb84d99 | 278 | u32 flags) |
93c34e70 | 279 | { |
4fb84d99 | 280 | gen6_pte_t pte = GEN6_PTE_VALID; |
93c34e70 KG |
281 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
282 | ||
24f3a8cf AG |
283 | if (!(flags & PTE_READ_ONLY)) |
284 | pte |= BYT_PTE_WRITEABLE; | |
93c34e70 KG |
285 | |
286 | if (level != I915_CACHE_NONE) | |
287 | pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES; | |
288 | ||
289 | return pte; | |
290 | } | |
291 | ||
07749ef3 MT |
292 | static gen6_pte_t hsw_pte_encode(dma_addr_t addr, |
293 | enum i915_cache_level level, | |
4fb84d99 | 294 | u32 unused) |
9119708c | 295 | { |
4fb84d99 | 296 | gen6_pte_t pte = GEN6_PTE_VALID; |
0d8ff15e | 297 | pte |= HSW_PTE_ADDR_ENCODE(addr); |
9119708c KG |
298 | |
299 | if (level != I915_CACHE_NONE) | |
87a6b688 | 300 | pte |= HSW_WB_LLC_AGE3; |
9119708c KG |
301 | |
302 | return pte; | |
303 | } | |
304 | ||
07749ef3 MT |
305 | static gen6_pte_t iris_pte_encode(dma_addr_t addr, |
306 | enum i915_cache_level level, | |
4fb84d99 | 307 | u32 unused) |
4d15c145 | 308 | { |
4fb84d99 | 309 | gen6_pte_t pte = GEN6_PTE_VALID; |
4d15c145 BW |
310 | pte |= HSW_PTE_ADDR_ENCODE(addr); |
311 | ||
651d794f CW |
312 | switch (level) { |
313 | case I915_CACHE_NONE: | |
314 | break; | |
315 | case I915_CACHE_WT: | |
c51e9701 | 316 | pte |= HSW_WT_ELLC_LLC_AGE3; |
651d794f CW |
317 | break; |
318 | default: | |
c51e9701 | 319 | pte |= HSW_WB_ELLC_LLC_AGE3; |
651d794f CW |
320 | break; |
321 | } | |
4d15c145 BW |
322 | |
323 | return pte; | |
324 | } | |
325 | ||
275a991c | 326 | static int __setup_page_dma(struct drm_i915_private *dev_priv, |
c114f76a | 327 | struct i915_page_dma *p, gfp_t flags) |
678d96fb | 328 | { |
275a991c | 329 | struct device *kdev = &dev_priv->drm.pdev->dev; |
678d96fb | 330 | |
c114f76a | 331 | p->page = alloc_page(flags); |
44159ddb MK |
332 | if (!p->page) |
333 | return -ENOMEM; | |
678d96fb | 334 | |
c49d13ee | 335 | p->daddr = dma_map_page(kdev, |
f51455d4 | 336 | p->page, 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); |
678d96fb | 337 | |
c49d13ee | 338 | if (dma_mapping_error(kdev, p->daddr)) { |
44159ddb MK |
339 | __free_page(p->page); |
340 | return -EINVAL; | |
341 | } | |
1266cdb1 MT |
342 | |
343 | return 0; | |
678d96fb BW |
344 | } |
345 | ||
275a991c TU |
346 | static int setup_page_dma(struct drm_i915_private *dev_priv, |
347 | struct i915_page_dma *p) | |
c114f76a | 348 | { |
275a991c | 349 | return __setup_page_dma(dev_priv, p, I915_GFP_DMA); |
c114f76a MK |
350 | } |
351 | ||
275a991c TU |
352 | static void cleanup_page_dma(struct drm_i915_private *dev_priv, |
353 | struct i915_page_dma *p) | |
06fda602 | 354 | { |
275a991c | 355 | struct pci_dev *pdev = dev_priv->drm.pdev; |
52a05c30 | 356 | |
44159ddb | 357 | if (WARN_ON(!p->page)) |
06fda602 | 358 | return; |
678d96fb | 359 | |
f51455d4 | 360 | dma_unmap_page(&pdev->dev, p->daddr, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); |
44159ddb MK |
361 | __free_page(p->page); |
362 | memset(p, 0, sizeof(*p)); | |
363 | } | |
364 | ||
d1c54acd | 365 | static void *kmap_page_dma(struct i915_page_dma *p) |
73eeea53 | 366 | { |
d1c54acd MK |
367 | return kmap_atomic(p->page); |
368 | } | |
73eeea53 | 369 | |
d1c54acd MK |
370 | /* We use the flushing unmap only with ppgtt structures: |
371 | * page directories, page tables and scratch pages. | |
372 | */ | |
e2d214ae | 373 | static void kunmap_page_dma(struct drm_i915_private *dev_priv, void *vaddr) |
d1c54acd | 374 | { |
73eeea53 MK |
375 | /* There are only few exceptions for gen >=6. chv and bxt. |
376 | * And we are not sure about the latter so play safe for now. | |
377 | */ | |
cc3f90f0 | 378 | if (IS_CHERRYVIEW(dev_priv) || IS_GEN9_LP(dev_priv)) |
73eeea53 MK |
379 | drm_clflush_virt_range(vaddr, PAGE_SIZE); |
380 | ||
381 | kunmap_atomic(vaddr); | |
382 | } | |
383 | ||
567047be | 384 | #define kmap_px(px) kmap_page_dma(px_base(px)) |
e2d214ae | 385 | #define kunmap_px(ppgtt, vaddr) \ |
49d73912 | 386 | kunmap_page_dma((ppgtt)->base.i915, (vaddr)) |
d1c54acd | 387 | |
275a991c TU |
388 | #define setup_px(dev_priv, px) setup_page_dma((dev_priv), px_base(px)) |
389 | #define cleanup_px(dev_priv, px) cleanup_page_dma((dev_priv), px_base(px)) | |
e2d214ae TU |
390 | #define fill_px(dev_priv, px, v) fill_page_dma((dev_priv), px_base(px), (v)) |
391 | #define fill32_px(dev_priv, px, v) \ | |
392 | fill_page_dma_32((dev_priv), px_base(px), (v)) | |
567047be | 393 | |
e2d214ae TU |
394 | static void fill_page_dma(struct drm_i915_private *dev_priv, |
395 | struct i915_page_dma *p, const uint64_t val) | |
d1c54acd MK |
396 | { |
397 | int i; | |
398 | uint64_t * const vaddr = kmap_page_dma(p); | |
399 | ||
400 | for (i = 0; i < 512; i++) | |
401 | vaddr[i] = val; | |
402 | ||
e2d214ae | 403 | kunmap_page_dma(dev_priv, vaddr); |
d1c54acd MK |
404 | } |
405 | ||
e2d214ae TU |
406 | static void fill_page_dma_32(struct drm_i915_private *dev_priv, |
407 | struct i915_page_dma *p, const uint32_t val32) | |
73eeea53 MK |
408 | { |
409 | uint64_t v = val32; | |
410 | ||
411 | v = v << 32 | val32; | |
412 | ||
e2d214ae | 413 | fill_page_dma(dev_priv, p, v); |
73eeea53 MK |
414 | } |
415 | ||
8bcdd0f7 | 416 | static int |
275a991c | 417 | setup_scratch_page(struct drm_i915_private *dev_priv, |
bb8f9cff CW |
418 | struct i915_page_dma *scratch, |
419 | gfp_t gfp) | |
4ad2af1e | 420 | { |
275a991c | 421 | return __setup_page_dma(dev_priv, scratch, gfp | __GFP_ZERO); |
4ad2af1e MK |
422 | } |
423 | ||
275a991c | 424 | static void cleanup_scratch_page(struct drm_i915_private *dev_priv, |
8bcdd0f7 | 425 | struct i915_page_dma *scratch) |
4ad2af1e | 426 | { |
275a991c | 427 | cleanup_page_dma(dev_priv, scratch); |
4ad2af1e MK |
428 | } |
429 | ||
275a991c | 430 | static struct i915_page_table *alloc_pt(struct drm_i915_private *dev_priv) |
06fda602 | 431 | { |
ec565b3c | 432 | struct i915_page_table *pt; |
275a991c | 433 | const size_t count = INTEL_GEN(dev_priv) >= 8 ? GEN8_PTES : GEN6_PTES; |
678d96fb | 434 | int ret = -ENOMEM; |
06fda602 BW |
435 | |
436 | pt = kzalloc(sizeof(*pt), GFP_KERNEL); | |
437 | if (!pt) | |
438 | return ERR_PTR(-ENOMEM); | |
439 | ||
678d96fb BW |
440 | pt->used_ptes = kcalloc(BITS_TO_LONGS(count), sizeof(*pt->used_ptes), |
441 | GFP_KERNEL); | |
442 | ||
443 | if (!pt->used_ptes) | |
444 | goto fail_bitmap; | |
445 | ||
275a991c | 446 | ret = setup_px(dev_priv, pt); |
678d96fb | 447 | if (ret) |
44159ddb | 448 | goto fail_page_m; |
06fda602 BW |
449 | |
450 | return pt; | |
678d96fb | 451 | |
44159ddb | 452 | fail_page_m: |
678d96fb BW |
453 | kfree(pt->used_ptes); |
454 | fail_bitmap: | |
455 | kfree(pt); | |
456 | ||
457 | return ERR_PTR(ret); | |
06fda602 BW |
458 | } |
459 | ||
275a991c TU |
460 | static void free_pt(struct drm_i915_private *dev_priv, |
461 | struct i915_page_table *pt) | |
06fda602 | 462 | { |
275a991c | 463 | cleanup_px(dev_priv, pt); |
2e906bea MK |
464 | kfree(pt->used_ptes); |
465 | kfree(pt); | |
466 | } | |
467 | ||
468 | static void gen8_initialize_pt(struct i915_address_space *vm, | |
469 | struct i915_page_table *pt) | |
470 | { | |
471 | gen8_pte_t scratch_pte; | |
472 | ||
8bcdd0f7 | 473 | scratch_pte = gen8_pte_encode(vm->scratch_page.daddr, |
4fb84d99 | 474 | I915_CACHE_LLC); |
2e906bea | 475 | |
49d73912 | 476 | fill_px(vm->i915, pt, scratch_pte); |
2e906bea MK |
477 | } |
478 | ||
479 | static void gen6_initialize_pt(struct i915_address_space *vm, | |
480 | struct i915_page_table *pt) | |
481 | { | |
482 | gen6_pte_t scratch_pte; | |
483 | ||
8bcdd0f7 | 484 | WARN_ON(vm->scratch_page.daddr == 0); |
2e906bea | 485 | |
8bcdd0f7 | 486 | scratch_pte = vm->pte_encode(vm->scratch_page.daddr, |
4fb84d99 | 487 | I915_CACHE_LLC, 0); |
2e906bea | 488 | |
49d73912 | 489 | fill32_px(vm->i915, pt, scratch_pte); |
06fda602 BW |
490 | } |
491 | ||
275a991c | 492 | static struct i915_page_directory *alloc_pd(struct drm_i915_private *dev_priv) |
06fda602 | 493 | { |
ec565b3c | 494 | struct i915_page_directory *pd; |
33c8819f | 495 | int ret = -ENOMEM; |
06fda602 BW |
496 | |
497 | pd = kzalloc(sizeof(*pd), GFP_KERNEL); | |
498 | if (!pd) | |
499 | return ERR_PTR(-ENOMEM); | |
500 | ||
33c8819f MT |
501 | pd->used_pdes = kcalloc(BITS_TO_LONGS(I915_PDES), |
502 | sizeof(*pd->used_pdes), GFP_KERNEL); | |
503 | if (!pd->used_pdes) | |
a08e111a | 504 | goto fail_bitmap; |
33c8819f | 505 | |
275a991c | 506 | ret = setup_px(dev_priv, pd); |
33c8819f | 507 | if (ret) |
a08e111a | 508 | goto fail_page_m; |
e5815a2e | 509 | |
06fda602 | 510 | return pd; |
33c8819f | 511 | |
a08e111a | 512 | fail_page_m: |
33c8819f | 513 | kfree(pd->used_pdes); |
a08e111a | 514 | fail_bitmap: |
33c8819f MT |
515 | kfree(pd); |
516 | ||
517 | return ERR_PTR(ret); | |
06fda602 BW |
518 | } |
519 | ||
275a991c TU |
520 | static void free_pd(struct drm_i915_private *dev_priv, |
521 | struct i915_page_directory *pd) | |
2e906bea MK |
522 | { |
523 | if (px_page(pd)) { | |
275a991c | 524 | cleanup_px(dev_priv, pd); |
2e906bea MK |
525 | kfree(pd->used_pdes); |
526 | kfree(pd); | |
527 | } | |
528 | } | |
529 | ||
530 | static void gen8_initialize_pd(struct i915_address_space *vm, | |
531 | struct i915_page_directory *pd) | |
532 | { | |
533 | gen8_pde_t scratch_pde; | |
534 | ||
535 | scratch_pde = gen8_pde_encode(px_dma(vm->scratch_pt), I915_CACHE_LLC); | |
536 | ||
49d73912 | 537 | fill_px(vm->i915, pd, scratch_pde); |
2e906bea MK |
538 | } |
539 | ||
275a991c | 540 | static int __pdp_init(struct drm_i915_private *dev_priv, |
6ac18502 MT |
541 | struct i915_page_directory_pointer *pdp) |
542 | { | |
275a991c | 543 | size_t pdpes = I915_PDPES_PER_PDP(dev_priv); |
6ac18502 MT |
544 | |
545 | pdp->used_pdpes = kcalloc(BITS_TO_LONGS(pdpes), | |
546 | sizeof(unsigned long), | |
547 | GFP_KERNEL); | |
548 | if (!pdp->used_pdpes) | |
549 | return -ENOMEM; | |
550 | ||
551 | pdp->page_directory = kcalloc(pdpes, sizeof(*pdp->page_directory), | |
552 | GFP_KERNEL); | |
553 | if (!pdp->page_directory) { | |
554 | kfree(pdp->used_pdpes); | |
555 | /* the PDP might be the statically allocated top level. Keep it | |
556 | * as clean as possible */ | |
557 | pdp->used_pdpes = NULL; | |
558 | return -ENOMEM; | |
559 | } | |
560 | ||
561 | return 0; | |
562 | } | |
563 | ||
564 | static void __pdp_fini(struct i915_page_directory_pointer *pdp) | |
565 | { | |
566 | kfree(pdp->used_pdpes); | |
567 | kfree(pdp->page_directory); | |
568 | pdp->page_directory = NULL; | |
569 | } | |
570 | ||
762d9936 | 571 | static struct |
275a991c | 572 | i915_page_directory_pointer *alloc_pdp(struct drm_i915_private *dev_priv) |
762d9936 MT |
573 | { |
574 | struct i915_page_directory_pointer *pdp; | |
575 | int ret = -ENOMEM; | |
576 | ||
275a991c | 577 | WARN_ON(!USES_FULL_48BIT_PPGTT(dev_priv)); |
762d9936 MT |
578 | |
579 | pdp = kzalloc(sizeof(*pdp), GFP_KERNEL); | |
580 | if (!pdp) | |
581 | return ERR_PTR(-ENOMEM); | |
582 | ||
275a991c | 583 | ret = __pdp_init(dev_priv, pdp); |
762d9936 MT |
584 | if (ret) |
585 | goto fail_bitmap; | |
586 | ||
275a991c | 587 | ret = setup_px(dev_priv, pdp); |
762d9936 MT |
588 | if (ret) |
589 | goto fail_page_m; | |
590 | ||
591 | return pdp; | |
592 | ||
593 | fail_page_m: | |
594 | __pdp_fini(pdp); | |
595 | fail_bitmap: | |
596 | kfree(pdp); | |
597 | ||
598 | return ERR_PTR(ret); | |
599 | } | |
600 | ||
275a991c | 601 | static void free_pdp(struct drm_i915_private *dev_priv, |
6ac18502 MT |
602 | struct i915_page_directory_pointer *pdp) |
603 | { | |
604 | __pdp_fini(pdp); | |
275a991c TU |
605 | if (USES_FULL_48BIT_PPGTT(dev_priv)) { |
606 | cleanup_px(dev_priv, pdp); | |
762d9936 MT |
607 | kfree(pdp); |
608 | } | |
609 | } | |
610 | ||
69ab76fd MT |
611 | static void gen8_initialize_pdp(struct i915_address_space *vm, |
612 | struct i915_page_directory_pointer *pdp) | |
613 | { | |
614 | gen8_ppgtt_pdpe_t scratch_pdpe; | |
615 | ||
616 | scratch_pdpe = gen8_pdpe_encode(px_dma(vm->scratch_pd), I915_CACHE_LLC); | |
617 | ||
49d73912 | 618 | fill_px(vm->i915, pdp, scratch_pdpe); |
69ab76fd MT |
619 | } |
620 | ||
621 | static void gen8_initialize_pml4(struct i915_address_space *vm, | |
622 | struct i915_pml4 *pml4) | |
623 | { | |
624 | gen8_ppgtt_pml4e_t scratch_pml4e; | |
625 | ||
626 | scratch_pml4e = gen8_pml4e_encode(px_dma(vm->scratch_pdp), | |
627 | I915_CACHE_LLC); | |
628 | ||
49d73912 | 629 | fill_px(vm->i915, pml4, scratch_pml4e); |
69ab76fd MT |
630 | } |
631 | ||
762d9936 | 632 | static void |
5c693b2b MA |
633 | gen8_setup_pdpe(struct i915_hw_ppgtt *ppgtt, |
634 | struct i915_page_directory_pointer *pdp, | |
635 | struct i915_page_directory *pd, | |
636 | int index) | |
762d9936 MT |
637 | { |
638 | gen8_ppgtt_pdpe_t *page_directorypo; | |
639 | ||
275a991c | 640 | if (!USES_FULL_48BIT_PPGTT(to_i915(ppgtt->base.dev))) |
762d9936 MT |
641 | return; |
642 | ||
643 | page_directorypo = kmap_px(pdp); | |
644 | page_directorypo[index] = gen8_pdpe_encode(px_dma(pd), I915_CACHE_LLC); | |
645 | kunmap_px(ppgtt, page_directorypo); | |
646 | } | |
647 | ||
648 | static void | |
56843107 MA |
649 | gen8_setup_pml4e(struct i915_hw_ppgtt *ppgtt, |
650 | struct i915_pml4 *pml4, | |
651 | struct i915_page_directory_pointer *pdp, | |
652 | int index) | |
762d9936 MT |
653 | { |
654 | gen8_ppgtt_pml4e_t *pagemap = kmap_px(pml4); | |
655 | ||
275a991c | 656 | WARN_ON(!USES_FULL_48BIT_PPGTT(to_i915(ppgtt->base.dev))); |
762d9936 MT |
657 | pagemap[index] = gen8_pml4e_encode(px_dma(pdp), I915_CACHE_LLC); |
658 | kunmap_px(ppgtt, pagemap); | |
6ac18502 MT |
659 | } |
660 | ||
94e409c1 | 661 | /* Broadwell Page Directory Pointer Descriptors */ |
e85b26dc | 662 | static int gen8_write_pdp(struct drm_i915_gem_request *req, |
7cb6d7ac MT |
663 | unsigned entry, |
664 | dma_addr_t addr) | |
94e409c1 | 665 | { |
7e37f889 | 666 | struct intel_ring *ring = req->ring; |
4a570db5 | 667 | struct intel_engine_cs *engine = req->engine; |
94e409c1 BW |
668 | int ret; |
669 | ||
670 | BUG_ON(entry >= 4); | |
671 | ||
5fb9de1a | 672 | ret = intel_ring_begin(req, 6); |
94e409c1 BW |
673 | if (ret) |
674 | return ret; | |
675 | ||
b5321f30 CW |
676 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); |
677 | intel_ring_emit_reg(ring, GEN8_RING_PDP_UDW(engine, entry)); | |
678 | intel_ring_emit(ring, upper_32_bits(addr)); | |
679 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
680 | intel_ring_emit_reg(ring, GEN8_RING_PDP_LDW(engine, entry)); | |
681 | intel_ring_emit(ring, lower_32_bits(addr)); | |
682 | intel_ring_advance(ring); | |
94e409c1 BW |
683 | |
684 | return 0; | |
685 | } | |
686 | ||
2dba3239 MT |
687 | static int gen8_legacy_mm_switch(struct i915_hw_ppgtt *ppgtt, |
688 | struct drm_i915_gem_request *req) | |
94e409c1 | 689 | { |
eeb9488e | 690 | int i, ret; |
94e409c1 | 691 | |
7cb6d7ac | 692 | for (i = GEN8_LEGACY_PDPES - 1; i >= 0; i--) { |
d852c7bf MK |
693 | const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i); |
694 | ||
e85b26dc | 695 | ret = gen8_write_pdp(req, i, pd_daddr); |
eeb9488e BW |
696 | if (ret) |
697 | return ret; | |
94e409c1 | 698 | } |
d595bd4b | 699 | |
eeb9488e | 700 | return 0; |
94e409c1 BW |
701 | } |
702 | ||
2dba3239 MT |
703 | static int gen8_48b_mm_switch(struct i915_hw_ppgtt *ppgtt, |
704 | struct drm_i915_gem_request *req) | |
705 | { | |
706 | return gen8_write_pdp(req, 0, px_dma(&ppgtt->pml4)); | |
707 | } | |
708 | ||
fce93755 MK |
709 | /* PDE TLBs are a pain to invalidate on GEN8+. When we modify |
710 | * the page table structures, we mark them dirty so that | |
711 | * context switching/execlist queuing code takes extra steps | |
712 | * to ensure that tlbs are flushed. | |
713 | */ | |
714 | static void mark_tlbs_dirty(struct i915_hw_ppgtt *ppgtt) | |
715 | { | |
49d73912 | 716 | ppgtt->pd_dirty_rings = INTEL_INFO(ppgtt->base.i915)->ring_mask; |
fce93755 MK |
717 | } |
718 | ||
2ce5179f MW |
719 | /* Removes entries from a single page table, releasing it if it's empty. |
720 | * Caller can use the return value to update higher-level entries. | |
721 | */ | |
722 | static bool gen8_ppgtt_clear_pt(struct i915_address_space *vm, | |
d209b9c3 MW |
723 | struct i915_page_table *pt, |
724 | uint64_t start, | |
725 | uint64_t length) | |
459108b8 | 726 | { |
e5716f55 | 727 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
d209b9c3 | 728 | unsigned int num_entries = gen8_pte_count(start, length); |
37c63934 MK |
729 | unsigned int pte = gen8_pte_index(start); |
730 | unsigned int pte_end = pte + num_entries; | |
f9b5b782 | 731 | gen8_pte_t *pt_vaddr; |
d209b9c3 MW |
732 | gen8_pte_t scratch_pte = gen8_pte_encode(vm->scratch_page.daddr, |
733 | I915_CACHE_LLC); | |
459108b8 | 734 | |
d209b9c3 | 735 | if (WARN_ON(!px_page(pt))) |
2ce5179f | 736 | return false; |
459108b8 | 737 | |
37c63934 MK |
738 | GEM_BUG_ON(pte_end > GEN8_PTES); |
739 | ||
740 | bitmap_clear(pt->used_ptes, pte, num_entries); | |
06fda602 | 741 | |
a18dbba8 | 742 | if (bitmap_empty(pt->used_ptes, GEN8_PTES)) |
2ce5179f | 743 | return true; |
2ce5179f | 744 | |
d209b9c3 MW |
745 | pt_vaddr = kmap_px(pt); |
746 | ||
37c63934 MK |
747 | while (pte < pte_end) |
748 | pt_vaddr[pte++] = scratch_pte; | |
06fda602 | 749 | |
d209b9c3 | 750 | kunmap_px(ppgtt, pt_vaddr); |
2ce5179f MW |
751 | |
752 | return false; | |
d209b9c3 | 753 | } |
06fda602 | 754 | |
2ce5179f MW |
755 | /* Removes entries from a single page dir, releasing it if it's empty. |
756 | * Caller can use the return value to update higher-level entries | |
757 | */ | |
758 | static bool gen8_ppgtt_clear_pd(struct i915_address_space *vm, | |
d209b9c3 MW |
759 | struct i915_page_directory *pd, |
760 | uint64_t start, | |
761 | uint64_t length) | |
762 | { | |
2ce5179f | 763 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
d209b9c3 MW |
764 | struct i915_page_table *pt; |
765 | uint64_t pde; | |
2ce5179f MW |
766 | gen8_pde_t *pde_vaddr; |
767 | gen8_pde_t scratch_pde = gen8_pde_encode(px_dma(vm->scratch_pt), | |
768 | I915_CACHE_LLC); | |
d209b9c3 MW |
769 | |
770 | gen8_for_each_pde(pt, pd, start, length, pde) { | |
06fda602 | 771 | if (WARN_ON(!pd->page_table[pde])) |
00245266 | 772 | break; |
06fda602 | 773 | |
2ce5179f MW |
774 | if (gen8_ppgtt_clear_pt(vm, pt, start, length)) { |
775 | __clear_bit(pde, pd->used_pdes); | |
776 | pde_vaddr = kmap_px(pd); | |
777 | pde_vaddr[pde] = scratch_pde; | |
778 | kunmap_px(ppgtt, pde_vaddr); | |
49d73912 | 779 | free_pt(vm->i915, pt); |
2ce5179f MW |
780 | } |
781 | } | |
782 | ||
a18dbba8 | 783 | if (bitmap_empty(pd->used_pdes, I915_PDES)) |
2ce5179f | 784 | return true; |
2ce5179f MW |
785 | |
786 | return false; | |
d209b9c3 | 787 | } |
06fda602 | 788 | |
2ce5179f MW |
789 | /* Removes entries from a single page dir pointer, releasing it if it's empty. |
790 | * Caller can use the return value to update higher-level entries | |
791 | */ | |
792 | static bool gen8_ppgtt_clear_pdp(struct i915_address_space *vm, | |
d209b9c3 MW |
793 | struct i915_page_directory_pointer *pdp, |
794 | uint64_t start, | |
795 | uint64_t length) | |
796 | { | |
2ce5179f | 797 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
d209b9c3 MW |
798 | struct i915_page_directory *pd; |
799 | uint64_t pdpe; | |
06fda602 | 800 | |
d209b9c3 MW |
801 | gen8_for_each_pdpe(pd, pdp, start, length, pdpe) { |
802 | if (WARN_ON(!pdp->page_directory[pdpe])) | |
803 | break; | |
459108b8 | 804 | |
2ce5179f MW |
805 | if (gen8_ppgtt_clear_pd(vm, pd, start, length)) { |
806 | __clear_bit(pdpe, pdp->used_pdpes); | |
9e65a378 | 807 | gen8_setup_pdpe(ppgtt, pdp, vm->scratch_pd, pdpe); |
49d73912 | 808 | free_pd(vm->i915, pd); |
2ce5179f MW |
809 | } |
810 | } | |
811 | ||
fce93755 MK |
812 | mark_tlbs_dirty(ppgtt); |
813 | ||
a18dbba8 | 814 | if (bitmap_empty(pdp->used_pdpes, I915_PDPES_PER_PDP(dev_priv))) |
2ce5179f | 815 | return true; |
2ce5179f MW |
816 | |
817 | return false; | |
d209b9c3 | 818 | } |
459108b8 | 819 | |
2ce5179f MW |
820 | /* Removes entries from a single pml4. |
821 | * This is the top-level structure in 4-level page tables used on gen8+. | |
822 | * Empty entries are always scratch pml4e. | |
823 | */ | |
d209b9c3 MW |
824 | static void gen8_ppgtt_clear_pml4(struct i915_address_space *vm, |
825 | struct i915_pml4 *pml4, | |
826 | uint64_t start, | |
827 | uint64_t length) | |
828 | { | |
2ce5179f | 829 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
d209b9c3 MW |
830 | struct i915_page_directory_pointer *pdp; |
831 | uint64_t pml4e; | |
2ce5179f | 832 | |
49d73912 | 833 | GEM_BUG_ON(!USES_FULL_48BIT_PPGTT(vm->i915)); |
459108b8 | 834 | |
d209b9c3 MW |
835 | gen8_for_each_pml4e(pdp, pml4, start, length, pml4e) { |
836 | if (WARN_ON(!pml4->pdps[pml4e])) | |
837 | break; | |
459108b8 | 838 | |
2ce5179f MW |
839 | if (gen8_ppgtt_clear_pdp(vm, pdp, start, length)) { |
840 | __clear_bit(pml4e, pml4->used_pml4es); | |
9e65a378 | 841 | gen8_setup_pml4e(ppgtt, pml4, vm->scratch_pdp, pml4e); |
49d73912 | 842 | free_pdp(vm->i915, pdp); |
2ce5179f | 843 | } |
459108b8 BW |
844 | } |
845 | } | |
846 | ||
f9b5b782 | 847 | static void gen8_ppgtt_clear_range(struct i915_address_space *vm, |
4fb84d99 | 848 | uint64_t start, uint64_t length) |
9df15b49 | 849 | { |
e5716f55 | 850 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
f9b5b782 | 851 | |
c6385c94 | 852 | if (USES_FULL_48BIT_PPGTT(vm->i915)) |
d209b9c3 MW |
853 | gen8_ppgtt_clear_pml4(vm, &ppgtt->pml4, start, length); |
854 | else | |
855 | gen8_ppgtt_clear_pdp(vm, &ppgtt->pdp, start, length); | |
f9b5b782 MT |
856 | } |
857 | ||
858 | static void | |
859 | gen8_ppgtt_insert_pte_entries(struct i915_address_space *vm, | |
860 | struct i915_page_directory_pointer *pdp, | |
3387d433 | 861 | struct sg_page_iter *sg_iter, |
f9b5b782 MT |
862 | uint64_t start, |
863 | enum i915_cache_level cache_level) | |
864 | { | |
e5716f55 | 865 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
07749ef3 | 866 | gen8_pte_t *pt_vaddr; |
de5ba8eb MT |
867 | unsigned pdpe = gen8_pdpe_index(start); |
868 | unsigned pde = gen8_pde_index(start); | |
869 | unsigned pte = gen8_pte_index(start); | |
9df15b49 | 870 | |
6f1cc993 | 871 | pt_vaddr = NULL; |
7ad47cf2 | 872 | |
3387d433 | 873 | while (__sg_page_iter_next(sg_iter)) { |
d7b3de91 | 874 | if (pt_vaddr == NULL) { |
d4ec9da0 | 875 | struct i915_page_directory *pd = pdp->page_directory[pdpe]; |
ec565b3c | 876 | struct i915_page_table *pt = pd->page_table[pde]; |
d1c54acd | 877 | pt_vaddr = kmap_px(pt); |
d7b3de91 | 878 | } |
9df15b49 | 879 | |
7ad47cf2 | 880 | pt_vaddr[pte] = |
3387d433 | 881 | gen8_pte_encode(sg_page_iter_dma_address(sg_iter), |
4fb84d99 | 882 | cache_level); |
07749ef3 | 883 | if (++pte == GEN8_PTES) { |
d1c54acd | 884 | kunmap_px(ppgtt, pt_vaddr); |
6f1cc993 | 885 | pt_vaddr = NULL; |
07749ef3 | 886 | if (++pde == I915_PDES) { |
c6385c94 | 887 | if (++pdpe == I915_PDPES_PER_PDP(vm->i915)) |
de5ba8eb | 888 | break; |
7ad47cf2 BW |
889 | pde = 0; |
890 | } | |
891 | pte = 0; | |
9df15b49 BW |
892 | } |
893 | } | |
d1c54acd MK |
894 | |
895 | if (pt_vaddr) | |
896 | kunmap_px(ppgtt, pt_vaddr); | |
9df15b49 BW |
897 | } |
898 | ||
f9b5b782 MT |
899 | static void gen8_ppgtt_insert_entries(struct i915_address_space *vm, |
900 | struct sg_table *pages, | |
901 | uint64_t start, | |
902 | enum i915_cache_level cache_level, | |
903 | u32 unused) | |
904 | { | |
e5716f55 | 905 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
3387d433 | 906 | struct sg_page_iter sg_iter; |
f9b5b782 | 907 | |
3387d433 | 908 | __sg_page_iter_start(&sg_iter, pages->sgl, sg_nents(pages->sgl), 0); |
de5ba8eb | 909 | |
c6385c94 | 910 | if (!USES_FULL_48BIT_PPGTT(vm->i915)) { |
de5ba8eb MT |
911 | gen8_ppgtt_insert_pte_entries(vm, &ppgtt->pdp, &sg_iter, start, |
912 | cache_level); | |
913 | } else { | |
914 | struct i915_page_directory_pointer *pdp; | |
e8ebd8e2 | 915 | uint64_t pml4e; |
de5ba8eb MT |
916 | uint64_t length = (uint64_t)pages->orig_nents << PAGE_SHIFT; |
917 | ||
e8ebd8e2 | 918 | gen8_for_each_pml4e(pdp, &ppgtt->pml4, start, length, pml4e) { |
de5ba8eb MT |
919 | gen8_ppgtt_insert_pte_entries(vm, pdp, &sg_iter, |
920 | start, cache_level); | |
921 | } | |
922 | } | |
f9b5b782 MT |
923 | } |
924 | ||
275a991c | 925 | static void gen8_free_page_tables(struct drm_i915_private *dev_priv, |
f37c0505 | 926 | struct i915_page_directory *pd) |
7ad47cf2 BW |
927 | { |
928 | int i; | |
929 | ||
567047be | 930 | if (!px_page(pd)) |
7ad47cf2 BW |
931 | return; |
932 | ||
33c8819f | 933 | for_each_set_bit(i, pd->used_pdes, I915_PDES) { |
06fda602 BW |
934 | if (WARN_ON(!pd->page_table[i])) |
935 | continue; | |
7ad47cf2 | 936 | |
275a991c | 937 | free_pt(dev_priv, pd->page_table[i]); |
06fda602 BW |
938 | pd->page_table[i] = NULL; |
939 | } | |
d7b3de91 BW |
940 | } |
941 | ||
8776f02b MK |
942 | static int gen8_init_scratch(struct i915_address_space *vm) |
943 | { | |
49d73912 | 944 | struct drm_i915_private *dev_priv = vm->i915; |
64c050db | 945 | int ret; |
8776f02b | 946 | |
275a991c | 947 | ret = setup_scratch_page(dev_priv, &vm->scratch_page, I915_GFP_DMA); |
8bcdd0f7 CW |
948 | if (ret) |
949 | return ret; | |
8776f02b | 950 | |
275a991c | 951 | vm->scratch_pt = alloc_pt(dev_priv); |
8776f02b | 952 | if (IS_ERR(vm->scratch_pt)) { |
64c050db MA |
953 | ret = PTR_ERR(vm->scratch_pt); |
954 | goto free_scratch_page; | |
8776f02b MK |
955 | } |
956 | ||
275a991c | 957 | vm->scratch_pd = alloc_pd(dev_priv); |
8776f02b | 958 | if (IS_ERR(vm->scratch_pd)) { |
64c050db MA |
959 | ret = PTR_ERR(vm->scratch_pd); |
960 | goto free_pt; | |
8776f02b MK |
961 | } |
962 | ||
275a991c TU |
963 | if (USES_FULL_48BIT_PPGTT(dev_priv)) { |
964 | vm->scratch_pdp = alloc_pdp(dev_priv); | |
69ab76fd | 965 | if (IS_ERR(vm->scratch_pdp)) { |
64c050db MA |
966 | ret = PTR_ERR(vm->scratch_pdp); |
967 | goto free_pd; | |
69ab76fd MT |
968 | } |
969 | } | |
970 | ||
8776f02b MK |
971 | gen8_initialize_pt(vm, vm->scratch_pt); |
972 | gen8_initialize_pd(vm, vm->scratch_pd); | |
275a991c | 973 | if (USES_FULL_48BIT_PPGTT(dev_priv)) |
69ab76fd | 974 | gen8_initialize_pdp(vm, vm->scratch_pdp); |
8776f02b MK |
975 | |
976 | return 0; | |
64c050db MA |
977 | |
978 | free_pd: | |
275a991c | 979 | free_pd(dev_priv, vm->scratch_pd); |
64c050db | 980 | free_pt: |
275a991c | 981 | free_pt(dev_priv, vm->scratch_pt); |
64c050db | 982 | free_scratch_page: |
275a991c | 983 | cleanup_scratch_page(dev_priv, &vm->scratch_page); |
64c050db MA |
984 | |
985 | return ret; | |
8776f02b MK |
986 | } |
987 | ||
650da34c ZL |
988 | static int gen8_ppgtt_notify_vgt(struct i915_hw_ppgtt *ppgtt, bool create) |
989 | { | |
990 | enum vgt_g2v_type msg; | |
49d73912 | 991 | struct drm_i915_private *dev_priv = ppgtt->base.i915; |
650da34c ZL |
992 | int i; |
993 | ||
df28564d | 994 | if (USES_FULL_48BIT_PPGTT(dev_priv)) { |
650da34c ZL |
995 | u64 daddr = px_dma(&ppgtt->pml4); |
996 | ||
ab75bb5d VS |
997 | I915_WRITE(vgtif_reg(pdp[0].lo), lower_32_bits(daddr)); |
998 | I915_WRITE(vgtif_reg(pdp[0].hi), upper_32_bits(daddr)); | |
650da34c ZL |
999 | |
1000 | msg = (create ? VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE : | |
1001 | VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY); | |
1002 | } else { | |
1003 | for (i = 0; i < GEN8_LEGACY_PDPES; i++) { | |
1004 | u64 daddr = i915_page_dir_dma_addr(ppgtt, i); | |
1005 | ||
ab75bb5d VS |
1006 | I915_WRITE(vgtif_reg(pdp[i].lo), lower_32_bits(daddr)); |
1007 | I915_WRITE(vgtif_reg(pdp[i].hi), upper_32_bits(daddr)); | |
650da34c ZL |
1008 | } |
1009 | ||
1010 | msg = (create ? VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE : | |
1011 | VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY); | |
1012 | } | |
1013 | ||
1014 | I915_WRITE(vgtif_reg(g2v_notify), msg); | |
1015 | ||
1016 | return 0; | |
1017 | } | |
1018 | ||
8776f02b MK |
1019 | static void gen8_free_scratch(struct i915_address_space *vm) |
1020 | { | |
49d73912 | 1021 | struct drm_i915_private *dev_priv = vm->i915; |
8776f02b | 1022 | |
275a991c TU |
1023 | if (USES_FULL_48BIT_PPGTT(dev_priv)) |
1024 | free_pdp(dev_priv, vm->scratch_pdp); | |
1025 | free_pd(dev_priv, vm->scratch_pd); | |
1026 | free_pt(dev_priv, vm->scratch_pt); | |
1027 | cleanup_scratch_page(dev_priv, &vm->scratch_page); | |
8776f02b MK |
1028 | } |
1029 | ||
275a991c | 1030 | static void gen8_ppgtt_cleanup_3lvl(struct drm_i915_private *dev_priv, |
762d9936 | 1031 | struct i915_page_directory_pointer *pdp) |
b45a6715 BW |
1032 | { |
1033 | int i; | |
1034 | ||
275a991c | 1035 | for_each_set_bit(i, pdp->used_pdpes, I915_PDPES_PER_PDP(dev_priv)) { |
d4ec9da0 | 1036 | if (WARN_ON(!pdp->page_directory[i])) |
06fda602 BW |
1037 | continue; |
1038 | ||
275a991c TU |
1039 | gen8_free_page_tables(dev_priv, pdp->page_directory[i]); |
1040 | free_pd(dev_priv, pdp->page_directory[i]); | |
7ad47cf2 | 1041 | } |
69876bed | 1042 | |
275a991c | 1043 | free_pdp(dev_priv, pdp); |
762d9936 MT |
1044 | } |
1045 | ||
1046 | static void gen8_ppgtt_cleanup_4lvl(struct i915_hw_ppgtt *ppgtt) | |
1047 | { | |
49d73912 | 1048 | struct drm_i915_private *dev_priv = ppgtt->base.i915; |
762d9936 MT |
1049 | int i; |
1050 | ||
1051 | for_each_set_bit(i, ppgtt->pml4.used_pml4es, GEN8_PML4ES_PER_PML4) { | |
1052 | if (WARN_ON(!ppgtt->pml4.pdps[i])) | |
1053 | continue; | |
1054 | ||
275a991c | 1055 | gen8_ppgtt_cleanup_3lvl(dev_priv, ppgtt->pml4.pdps[i]); |
762d9936 MT |
1056 | } |
1057 | ||
275a991c | 1058 | cleanup_px(dev_priv, &ppgtt->pml4); |
762d9936 MT |
1059 | } |
1060 | ||
1061 | static void gen8_ppgtt_cleanup(struct i915_address_space *vm) | |
1062 | { | |
49d73912 | 1063 | struct drm_i915_private *dev_priv = vm->i915; |
e5716f55 | 1064 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
762d9936 | 1065 | |
275a991c | 1066 | if (intel_vgpu_active(dev_priv)) |
650da34c ZL |
1067 | gen8_ppgtt_notify_vgt(ppgtt, false); |
1068 | ||
275a991c TU |
1069 | if (!USES_FULL_48BIT_PPGTT(dev_priv)) |
1070 | gen8_ppgtt_cleanup_3lvl(dev_priv, &ppgtt->pdp); | |
762d9936 MT |
1071 | else |
1072 | gen8_ppgtt_cleanup_4lvl(ppgtt); | |
d4ec9da0 | 1073 | |
8776f02b | 1074 | gen8_free_scratch(vm); |
b45a6715 BW |
1075 | } |
1076 | ||
d7b2633d MT |
1077 | /** |
1078 | * gen8_ppgtt_alloc_pagetabs() - Allocate page tables for VA range. | |
d4ec9da0 MT |
1079 | * @vm: Master vm structure. |
1080 | * @pd: Page directory for this address range. | |
d7b2633d | 1081 | * @start: Starting virtual address to begin allocations. |
d4ec9da0 | 1082 | * @length: Size of the allocations. |
d7b2633d MT |
1083 | * @new_pts: Bitmap set by function with new allocations. Likely used by the |
1084 | * caller to free on error. | |
1085 | * | |
1086 | * Allocate the required number of page tables. Extremely similar to | |
1087 | * gen8_ppgtt_alloc_page_directories(). The main difference is here we are limited by | |
1088 | * the page directory boundary (instead of the page directory pointer). That | |
1089 | * boundary is 1GB virtual. Therefore, unlike gen8_ppgtt_alloc_page_directories(), it is | |
1090 | * possible, and likely that the caller will need to use multiple calls of this | |
1091 | * function to achieve the appropriate allocation. | |
1092 | * | |
1093 | * Return: 0 if success; negative error code otherwise. | |
1094 | */ | |
d4ec9da0 | 1095 | static int gen8_ppgtt_alloc_pagetabs(struct i915_address_space *vm, |
e5815a2e | 1096 | struct i915_page_directory *pd, |
5441f0cb | 1097 | uint64_t start, |
d7b2633d MT |
1098 | uint64_t length, |
1099 | unsigned long *new_pts) | |
bf2b4ed2 | 1100 | { |
49d73912 | 1101 | struct drm_i915_private *dev_priv = vm->i915; |
d7b2633d | 1102 | struct i915_page_table *pt; |
5441f0cb | 1103 | uint32_t pde; |
bf2b4ed2 | 1104 | |
e8ebd8e2 | 1105 | gen8_for_each_pde(pt, pd, start, length, pde) { |
d7b2633d | 1106 | /* Don't reallocate page tables */ |
6ac18502 | 1107 | if (test_bit(pde, pd->used_pdes)) { |
d7b2633d | 1108 | /* Scratch is never allocated this way */ |
d4ec9da0 | 1109 | WARN_ON(pt == vm->scratch_pt); |
d7b2633d MT |
1110 | continue; |
1111 | } | |
1112 | ||
275a991c | 1113 | pt = alloc_pt(dev_priv); |
d7b2633d | 1114 | if (IS_ERR(pt)) |
5441f0cb MT |
1115 | goto unwind_out; |
1116 | ||
d4ec9da0 | 1117 | gen8_initialize_pt(vm, pt); |
d7b2633d | 1118 | pd->page_table[pde] = pt; |
966082c9 | 1119 | __set_bit(pde, new_pts); |
4c06ec8d | 1120 | trace_i915_page_table_entry_alloc(vm, pde, start, GEN8_PDE_SHIFT); |
7ad47cf2 BW |
1121 | } |
1122 | ||
bf2b4ed2 | 1123 | return 0; |
7ad47cf2 BW |
1124 | |
1125 | unwind_out: | |
d7b2633d | 1126 | for_each_set_bit(pde, new_pts, I915_PDES) |
275a991c | 1127 | free_pt(dev_priv, pd->page_table[pde]); |
7ad47cf2 | 1128 | |
d7b3de91 | 1129 | return -ENOMEM; |
bf2b4ed2 BW |
1130 | } |
1131 | ||
d7b2633d MT |
1132 | /** |
1133 | * gen8_ppgtt_alloc_page_directories() - Allocate page directories for VA range. | |
d4ec9da0 | 1134 | * @vm: Master vm structure. |
d7b2633d MT |
1135 | * @pdp: Page directory pointer for this address range. |
1136 | * @start: Starting virtual address to begin allocations. | |
d4ec9da0 MT |
1137 | * @length: Size of the allocations. |
1138 | * @new_pds: Bitmap set by function with new allocations. Likely used by the | |
d7b2633d MT |
1139 | * caller to free on error. |
1140 | * | |
1141 | * Allocate the required number of page directories starting at the pde index of | |
1142 | * @start, and ending at the pde index @start + @length. This function will skip | |
1143 | * over already allocated page directories within the range, and only allocate | |
1144 | * new ones, setting the appropriate pointer within the pdp as well as the | |
1145 | * correct position in the bitmap @new_pds. | |
1146 | * | |
1147 | * The function will only allocate the pages within the range for a give page | |
1148 | * directory pointer. In other words, if @start + @length straddles a virtually | |
1149 | * addressed PDP boundary (512GB for 4k pages), there will be more allocations | |
1150 | * required by the caller, This is not currently possible, and the BUG in the | |
1151 | * code will prevent it. | |
1152 | * | |
1153 | * Return: 0 if success; negative error code otherwise. | |
1154 | */ | |
d4ec9da0 MT |
1155 | static int |
1156 | gen8_ppgtt_alloc_page_directories(struct i915_address_space *vm, | |
1157 | struct i915_page_directory_pointer *pdp, | |
1158 | uint64_t start, | |
1159 | uint64_t length, | |
1160 | unsigned long *new_pds) | |
bf2b4ed2 | 1161 | { |
49d73912 | 1162 | struct drm_i915_private *dev_priv = vm->i915; |
d7b2633d | 1163 | struct i915_page_directory *pd; |
69876bed | 1164 | uint32_t pdpe; |
275a991c | 1165 | uint32_t pdpes = I915_PDPES_PER_PDP(dev_priv); |
69876bed | 1166 | |
6ac18502 | 1167 | WARN_ON(!bitmap_empty(new_pds, pdpes)); |
d7b2633d | 1168 | |
e8ebd8e2 | 1169 | gen8_for_each_pdpe(pd, pdp, start, length, pdpe) { |
6ac18502 | 1170 | if (test_bit(pdpe, pdp->used_pdpes)) |
d7b2633d | 1171 | continue; |
33c8819f | 1172 | |
275a991c | 1173 | pd = alloc_pd(dev_priv); |
d7b2633d | 1174 | if (IS_ERR(pd)) |
d7b3de91 | 1175 | goto unwind_out; |
69876bed | 1176 | |
d4ec9da0 | 1177 | gen8_initialize_pd(vm, pd); |
d7b2633d | 1178 | pdp->page_directory[pdpe] = pd; |
966082c9 | 1179 | __set_bit(pdpe, new_pds); |
4c06ec8d | 1180 | trace_i915_page_directory_entry_alloc(vm, pdpe, start, GEN8_PDPE_SHIFT); |
d7b3de91 BW |
1181 | } |
1182 | ||
bf2b4ed2 | 1183 | return 0; |
d7b3de91 BW |
1184 | |
1185 | unwind_out: | |
6ac18502 | 1186 | for_each_set_bit(pdpe, new_pds, pdpes) |
275a991c | 1187 | free_pd(dev_priv, pdp->page_directory[pdpe]); |
d7b3de91 BW |
1188 | |
1189 | return -ENOMEM; | |
bf2b4ed2 BW |
1190 | } |
1191 | ||
762d9936 MT |
1192 | /** |
1193 | * gen8_ppgtt_alloc_page_dirpointers() - Allocate pdps for VA range. | |
1194 | * @vm: Master vm structure. | |
1195 | * @pml4: Page map level 4 for this address range. | |
1196 | * @start: Starting virtual address to begin allocations. | |
1197 | * @length: Size of the allocations. | |
1198 | * @new_pdps: Bitmap set by function with new allocations. Likely used by the | |
1199 | * caller to free on error. | |
1200 | * | |
1201 | * Allocate the required number of page directory pointers. Extremely similar to | |
1202 | * gen8_ppgtt_alloc_page_directories() and gen8_ppgtt_alloc_pagetabs(). | |
1203 | * The main difference is here we are limited by the pml4 boundary (instead of | |
1204 | * the page directory pointer). | |
1205 | * | |
1206 | * Return: 0 if success; negative error code otherwise. | |
1207 | */ | |
1208 | static int | |
1209 | gen8_ppgtt_alloc_page_dirpointers(struct i915_address_space *vm, | |
1210 | struct i915_pml4 *pml4, | |
1211 | uint64_t start, | |
1212 | uint64_t length, | |
1213 | unsigned long *new_pdps) | |
1214 | { | |
49d73912 | 1215 | struct drm_i915_private *dev_priv = vm->i915; |
762d9936 | 1216 | struct i915_page_directory_pointer *pdp; |
762d9936 MT |
1217 | uint32_t pml4e; |
1218 | ||
1219 | WARN_ON(!bitmap_empty(new_pdps, GEN8_PML4ES_PER_PML4)); | |
1220 | ||
e8ebd8e2 | 1221 | gen8_for_each_pml4e(pdp, pml4, start, length, pml4e) { |
762d9936 | 1222 | if (!test_bit(pml4e, pml4->used_pml4es)) { |
275a991c | 1223 | pdp = alloc_pdp(dev_priv); |
762d9936 MT |
1224 | if (IS_ERR(pdp)) |
1225 | goto unwind_out; | |
1226 | ||
69ab76fd | 1227 | gen8_initialize_pdp(vm, pdp); |
762d9936 MT |
1228 | pml4->pdps[pml4e] = pdp; |
1229 | __set_bit(pml4e, new_pdps); | |
1230 | trace_i915_page_directory_pointer_entry_alloc(vm, | |
1231 | pml4e, | |
1232 | start, | |
1233 | GEN8_PML4E_SHIFT); | |
1234 | } | |
1235 | } | |
1236 | ||
1237 | return 0; | |
1238 | ||
1239 | unwind_out: | |
1240 | for_each_set_bit(pml4e, new_pdps, GEN8_PML4ES_PER_PML4) | |
275a991c | 1241 | free_pdp(dev_priv, pml4->pdps[pml4e]); |
762d9936 MT |
1242 | |
1243 | return -ENOMEM; | |
1244 | } | |
1245 | ||
d7b2633d | 1246 | static void |
3a41a05d | 1247 | free_gen8_temp_bitmaps(unsigned long *new_pds, unsigned long *new_pts) |
d7b2633d | 1248 | { |
d7b2633d MT |
1249 | kfree(new_pts); |
1250 | kfree(new_pds); | |
1251 | } | |
1252 | ||
1253 | /* Fills in the page directory bitmap, and the array of page tables bitmap. Both | |
1254 | * of these are based on the number of PDPEs in the system. | |
1255 | */ | |
1256 | static | |
1257 | int __must_check alloc_gen8_temp_bitmaps(unsigned long **new_pds, | |
3a41a05d | 1258 | unsigned long **new_pts, |
6ac18502 | 1259 | uint32_t pdpes) |
d7b2633d | 1260 | { |
d7b2633d | 1261 | unsigned long *pds; |
3a41a05d | 1262 | unsigned long *pts; |
d7b2633d | 1263 | |
3a41a05d | 1264 | pds = kcalloc(BITS_TO_LONGS(pdpes), sizeof(unsigned long), GFP_TEMPORARY); |
d7b2633d MT |
1265 | if (!pds) |
1266 | return -ENOMEM; | |
1267 | ||
3a41a05d MW |
1268 | pts = kcalloc(pdpes, BITS_TO_LONGS(I915_PDES) * sizeof(unsigned long), |
1269 | GFP_TEMPORARY); | |
1270 | if (!pts) | |
1271 | goto err_out; | |
d7b2633d MT |
1272 | |
1273 | *new_pds = pds; | |
1274 | *new_pts = pts; | |
1275 | ||
1276 | return 0; | |
1277 | ||
1278 | err_out: | |
3a41a05d | 1279 | free_gen8_temp_bitmaps(pds, pts); |
d7b2633d MT |
1280 | return -ENOMEM; |
1281 | } | |
1282 | ||
762d9936 MT |
1283 | static int gen8_alloc_va_range_3lvl(struct i915_address_space *vm, |
1284 | struct i915_page_directory_pointer *pdp, | |
1285 | uint64_t start, | |
1286 | uint64_t length) | |
bf2b4ed2 | 1287 | { |
e5716f55 | 1288 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
3a41a05d | 1289 | unsigned long *new_page_dirs, *new_page_tables; |
49d73912 | 1290 | struct drm_i915_private *dev_priv = vm->i915; |
5441f0cb | 1291 | struct i915_page_directory *pd; |
33c8819f MT |
1292 | const uint64_t orig_start = start; |
1293 | const uint64_t orig_length = length; | |
5441f0cb | 1294 | uint32_t pdpe; |
275a991c | 1295 | uint32_t pdpes = I915_PDPES_PER_PDP(dev_priv); |
bf2b4ed2 BW |
1296 | int ret; |
1297 | ||
6ac18502 | 1298 | ret = alloc_gen8_temp_bitmaps(&new_page_dirs, &new_page_tables, pdpes); |
bf2b4ed2 BW |
1299 | if (ret) |
1300 | return ret; | |
1301 | ||
d7b2633d | 1302 | /* Do the allocations first so we can easily bail out */ |
d4ec9da0 MT |
1303 | ret = gen8_ppgtt_alloc_page_directories(vm, pdp, start, length, |
1304 | new_page_dirs); | |
d7b2633d | 1305 | if (ret) { |
3a41a05d | 1306 | free_gen8_temp_bitmaps(new_page_dirs, new_page_tables); |
d7b2633d MT |
1307 | return ret; |
1308 | } | |
1309 | ||
1310 | /* For every page directory referenced, allocate page tables */ | |
e8ebd8e2 | 1311 | gen8_for_each_pdpe(pd, pdp, start, length, pdpe) { |
d4ec9da0 | 1312 | ret = gen8_ppgtt_alloc_pagetabs(vm, pd, start, length, |
3a41a05d | 1313 | new_page_tables + pdpe * BITS_TO_LONGS(I915_PDES)); |
5441f0cb MT |
1314 | if (ret) |
1315 | goto err_out; | |
5441f0cb MT |
1316 | } |
1317 | ||
33c8819f MT |
1318 | start = orig_start; |
1319 | length = orig_length; | |
1320 | ||
d7b2633d MT |
1321 | /* Allocations have completed successfully, so set the bitmaps, and do |
1322 | * the mappings. */ | |
e8ebd8e2 | 1323 | gen8_for_each_pdpe(pd, pdp, start, length, pdpe) { |
d1c54acd | 1324 | gen8_pde_t *const page_directory = kmap_px(pd); |
33c8819f | 1325 | struct i915_page_table *pt; |
09120d4e | 1326 | uint64_t pd_len = length; |
33c8819f MT |
1327 | uint64_t pd_start = start; |
1328 | uint32_t pde; | |
1329 | ||
d7b2633d MT |
1330 | /* Every pd should be allocated, we just did that above. */ |
1331 | WARN_ON(!pd); | |
1332 | ||
e8ebd8e2 | 1333 | gen8_for_each_pde(pt, pd, pd_start, pd_len, pde) { |
d7b2633d MT |
1334 | /* Same reasoning as pd */ |
1335 | WARN_ON(!pt); | |
1336 | WARN_ON(!pd_len); | |
1337 | WARN_ON(!gen8_pte_count(pd_start, pd_len)); | |
1338 | ||
1339 | /* Set our used ptes within the page table */ | |
1340 | bitmap_set(pt->used_ptes, | |
1341 | gen8_pte_index(pd_start), | |
1342 | gen8_pte_count(pd_start, pd_len)); | |
1343 | ||
1344 | /* Our pde is now pointing to the pagetable, pt */ | |
966082c9 | 1345 | __set_bit(pde, pd->used_pdes); |
d7b2633d MT |
1346 | |
1347 | /* Map the PDE to the page table */ | |
fe36f55d MK |
1348 | page_directory[pde] = gen8_pde_encode(px_dma(pt), |
1349 | I915_CACHE_LLC); | |
4c06ec8d MT |
1350 | trace_i915_page_table_entry_map(&ppgtt->base, pde, pt, |
1351 | gen8_pte_index(start), | |
1352 | gen8_pte_count(start, length), | |
1353 | GEN8_PTES); | |
d7b2633d MT |
1354 | |
1355 | /* NB: We haven't yet mapped ptes to pages. At this | |
1356 | * point we're still relying on insert_entries() */ | |
33c8819f | 1357 | } |
d7b2633d | 1358 | |
d1c54acd | 1359 | kunmap_px(ppgtt, page_directory); |
d4ec9da0 | 1360 | __set_bit(pdpe, pdp->used_pdpes); |
5c693b2b | 1361 | gen8_setup_pdpe(ppgtt, pdp, pd, pdpe); |
33c8819f MT |
1362 | } |
1363 | ||
3a41a05d | 1364 | free_gen8_temp_bitmaps(new_page_dirs, new_page_tables); |
5b7e4c9c | 1365 | mark_tlbs_dirty(ppgtt); |
d7b3de91 | 1366 | return 0; |
bf2b4ed2 | 1367 | |
d7b3de91 | 1368 | err_out: |
d7b2633d | 1369 | while (pdpe--) { |
e8ebd8e2 DG |
1370 | unsigned long temp; |
1371 | ||
3a41a05d MW |
1372 | for_each_set_bit(temp, new_page_tables + pdpe * |
1373 | BITS_TO_LONGS(I915_PDES), I915_PDES) | |
275a991c TU |
1374 | free_pt(dev_priv, |
1375 | pdp->page_directory[pdpe]->page_table[temp]); | |
d7b2633d MT |
1376 | } |
1377 | ||
6ac18502 | 1378 | for_each_set_bit(pdpe, new_page_dirs, pdpes) |
275a991c | 1379 | free_pd(dev_priv, pdp->page_directory[pdpe]); |
d7b2633d | 1380 | |
3a41a05d | 1381 | free_gen8_temp_bitmaps(new_page_dirs, new_page_tables); |
5b7e4c9c | 1382 | mark_tlbs_dirty(ppgtt); |
bf2b4ed2 BW |
1383 | return ret; |
1384 | } | |
1385 | ||
762d9936 MT |
1386 | static int gen8_alloc_va_range_4lvl(struct i915_address_space *vm, |
1387 | struct i915_pml4 *pml4, | |
1388 | uint64_t start, | |
1389 | uint64_t length) | |
1390 | { | |
1391 | DECLARE_BITMAP(new_pdps, GEN8_PML4ES_PER_PML4); | |
e5716f55 | 1392 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
762d9936 | 1393 | struct i915_page_directory_pointer *pdp; |
e8ebd8e2 | 1394 | uint64_t pml4e; |
762d9936 MT |
1395 | int ret = 0; |
1396 | ||
1397 | /* Do the pml4 allocations first, so we don't need to track the newly | |
1398 | * allocated tables below the pdp */ | |
1399 | bitmap_zero(new_pdps, GEN8_PML4ES_PER_PML4); | |
1400 | ||
1401 | /* The pagedirectory and pagetable allocations are done in the shared 3 | |
1402 | * and 4 level code. Just allocate the pdps. | |
1403 | */ | |
1404 | ret = gen8_ppgtt_alloc_page_dirpointers(vm, pml4, start, length, | |
1405 | new_pdps); | |
1406 | if (ret) | |
1407 | return ret; | |
1408 | ||
1409 | WARN(bitmap_weight(new_pdps, GEN8_PML4ES_PER_PML4) > 2, | |
1410 | "The allocation has spanned more than 512GB. " | |
1411 | "It is highly likely this is incorrect."); | |
1412 | ||
e8ebd8e2 | 1413 | gen8_for_each_pml4e(pdp, pml4, start, length, pml4e) { |
762d9936 MT |
1414 | WARN_ON(!pdp); |
1415 | ||
1416 | ret = gen8_alloc_va_range_3lvl(vm, pdp, start, length); | |
1417 | if (ret) | |
1418 | goto err_out; | |
1419 | ||
56843107 | 1420 | gen8_setup_pml4e(ppgtt, pml4, pdp, pml4e); |
762d9936 MT |
1421 | } |
1422 | ||
1423 | bitmap_or(pml4->used_pml4es, new_pdps, pml4->used_pml4es, | |
1424 | GEN8_PML4ES_PER_PML4); | |
1425 | ||
1426 | return 0; | |
1427 | ||
1428 | err_out: | |
1429 | for_each_set_bit(pml4e, new_pdps, GEN8_PML4ES_PER_PML4) | |
49d73912 | 1430 | gen8_ppgtt_cleanup_3lvl(vm->i915, pml4->pdps[pml4e]); |
762d9936 MT |
1431 | |
1432 | return ret; | |
1433 | } | |
1434 | ||
1435 | static int gen8_alloc_va_range(struct i915_address_space *vm, | |
1436 | uint64_t start, uint64_t length) | |
1437 | { | |
e5716f55 | 1438 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
762d9936 | 1439 | |
c6385c94 | 1440 | if (USES_FULL_48BIT_PPGTT(vm->i915)) |
762d9936 MT |
1441 | return gen8_alloc_va_range_4lvl(vm, &ppgtt->pml4, start, length); |
1442 | else | |
1443 | return gen8_alloc_va_range_3lvl(vm, &ppgtt->pdp, start, length); | |
1444 | } | |
1445 | ||
ea91e401 MT |
1446 | static void gen8_dump_pdp(struct i915_page_directory_pointer *pdp, |
1447 | uint64_t start, uint64_t length, | |
1448 | gen8_pte_t scratch_pte, | |
1449 | struct seq_file *m) | |
1450 | { | |
1451 | struct i915_page_directory *pd; | |
ea91e401 MT |
1452 | uint32_t pdpe; |
1453 | ||
e8ebd8e2 | 1454 | gen8_for_each_pdpe(pd, pdp, start, length, pdpe) { |
ea91e401 MT |
1455 | struct i915_page_table *pt; |
1456 | uint64_t pd_len = length; | |
1457 | uint64_t pd_start = start; | |
1458 | uint32_t pde; | |
1459 | ||
1460 | if (!test_bit(pdpe, pdp->used_pdpes)) | |
1461 | continue; | |
1462 | ||
1463 | seq_printf(m, "\tPDPE #%d\n", pdpe); | |
e8ebd8e2 | 1464 | gen8_for_each_pde(pt, pd, pd_start, pd_len, pde) { |
ea91e401 MT |
1465 | uint32_t pte; |
1466 | gen8_pte_t *pt_vaddr; | |
1467 | ||
1468 | if (!test_bit(pde, pd->used_pdes)) | |
1469 | continue; | |
1470 | ||
1471 | pt_vaddr = kmap_px(pt); | |
1472 | for (pte = 0; pte < GEN8_PTES; pte += 4) { | |
1473 | uint64_t va = | |
1474 | (pdpe << GEN8_PDPE_SHIFT) | | |
1475 | (pde << GEN8_PDE_SHIFT) | | |
1476 | (pte << GEN8_PTE_SHIFT); | |
1477 | int i; | |
1478 | bool found = false; | |
1479 | ||
1480 | for (i = 0; i < 4; i++) | |
1481 | if (pt_vaddr[pte + i] != scratch_pte) | |
1482 | found = true; | |
1483 | if (!found) | |
1484 | continue; | |
1485 | ||
1486 | seq_printf(m, "\t\t0x%llx [%03d,%03d,%04d]: =", va, pdpe, pde, pte); | |
1487 | for (i = 0; i < 4; i++) { | |
1488 | if (pt_vaddr[pte + i] != scratch_pte) | |
1489 | seq_printf(m, " %llx", pt_vaddr[pte + i]); | |
1490 | else | |
1491 | seq_puts(m, " SCRATCH "); | |
1492 | } | |
1493 | seq_puts(m, "\n"); | |
1494 | } | |
1495 | /* don't use kunmap_px, it could trigger | |
1496 | * an unnecessary flush. | |
1497 | */ | |
1498 | kunmap_atomic(pt_vaddr); | |
1499 | } | |
1500 | } | |
1501 | } | |
1502 | ||
1503 | static void gen8_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m) | |
1504 | { | |
1505 | struct i915_address_space *vm = &ppgtt->base; | |
1506 | uint64_t start = ppgtt->base.start; | |
1507 | uint64_t length = ppgtt->base.total; | |
8bcdd0f7 | 1508 | gen8_pte_t scratch_pte = gen8_pte_encode(vm->scratch_page.daddr, |
4fb84d99 | 1509 | I915_CACHE_LLC); |
ea91e401 | 1510 | |
c6385c94 | 1511 | if (!USES_FULL_48BIT_PPGTT(vm->i915)) { |
ea91e401 MT |
1512 | gen8_dump_pdp(&ppgtt->pdp, start, length, scratch_pte, m); |
1513 | } else { | |
e8ebd8e2 | 1514 | uint64_t pml4e; |
ea91e401 MT |
1515 | struct i915_pml4 *pml4 = &ppgtt->pml4; |
1516 | struct i915_page_directory_pointer *pdp; | |
1517 | ||
e8ebd8e2 | 1518 | gen8_for_each_pml4e(pdp, pml4, start, length, pml4e) { |
ea91e401 MT |
1519 | if (!test_bit(pml4e, pml4->used_pml4es)) |
1520 | continue; | |
1521 | ||
1522 | seq_printf(m, " PML4E #%llu\n", pml4e); | |
1523 | gen8_dump_pdp(pdp, start, length, scratch_pte, m); | |
1524 | } | |
1525 | } | |
1526 | } | |
1527 | ||
331f38e7 ZL |
1528 | static int gen8_preallocate_top_level_pdps(struct i915_hw_ppgtt *ppgtt) |
1529 | { | |
3a41a05d | 1530 | unsigned long *new_page_dirs, *new_page_tables; |
275a991c | 1531 | uint32_t pdpes = I915_PDPES_PER_PDP(to_i915(ppgtt->base.dev)); |
331f38e7 ZL |
1532 | int ret; |
1533 | ||
1534 | /* We allocate temp bitmap for page tables for no gain | |
1535 | * but as this is for init only, lets keep the things simple | |
1536 | */ | |
1537 | ret = alloc_gen8_temp_bitmaps(&new_page_dirs, &new_page_tables, pdpes); | |
1538 | if (ret) | |
1539 | return ret; | |
1540 | ||
1541 | /* Allocate for all pdps regardless of how the ppgtt | |
1542 | * was defined. | |
1543 | */ | |
1544 | ret = gen8_ppgtt_alloc_page_directories(&ppgtt->base, &ppgtt->pdp, | |
1545 | 0, 1ULL << 32, | |
1546 | new_page_dirs); | |
1547 | if (!ret) | |
1548 | *ppgtt->pdp.used_pdpes = *new_page_dirs; | |
1549 | ||
3a41a05d | 1550 | free_gen8_temp_bitmaps(new_page_dirs, new_page_tables); |
331f38e7 ZL |
1551 | |
1552 | return ret; | |
1553 | } | |
1554 | ||
eb0b44ad | 1555 | /* |
f3a964b9 BW |
1556 | * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers |
1557 | * with a net effect resembling a 2-level page table in normal x86 terms. Each | |
1558 | * PDP represents 1GB of memory 4 * 512 * 512 * 4096 = 4GB legacy 32b address | |
1559 | * space. | |
37aca44a | 1560 | * |
f3a964b9 | 1561 | */ |
5c5f6457 | 1562 | static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt) |
37aca44a | 1563 | { |
49d73912 | 1564 | struct drm_i915_private *dev_priv = ppgtt->base.i915; |
8776f02b | 1565 | int ret; |
7cb6d7ac | 1566 | |
8776f02b MK |
1567 | ret = gen8_init_scratch(&ppgtt->base); |
1568 | if (ret) | |
1569 | return ret; | |
69876bed | 1570 | |
d7b2633d | 1571 | ppgtt->base.start = 0; |
d7b2633d | 1572 | ppgtt->base.cleanup = gen8_ppgtt_cleanup; |
5c5f6457 | 1573 | ppgtt->base.allocate_va_range = gen8_alloc_va_range; |
d7b2633d | 1574 | ppgtt->base.insert_entries = gen8_ppgtt_insert_entries; |
c7e16f22 | 1575 | ppgtt->base.clear_range = gen8_ppgtt_clear_range; |
777dc5bb DV |
1576 | ppgtt->base.unbind_vma = ppgtt_unbind_vma; |
1577 | ppgtt->base.bind_vma = ppgtt_bind_vma; | |
ea91e401 | 1578 | ppgtt->debug_dump = gen8_dump_ppgtt; |
d7b2633d | 1579 | |
275a991c TU |
1580 | if (USES_FULL_48BIT_PPGTT(dev_priv)) { |
1581 | ret = setup_px(dev_priv, &ppgtt->pml4); | |
762d9936 MT |
1582 | if (ret) |
1583 | goto free_scratch; | |
6ac18502 | 1584 | |
69ab76fd MT |
1585 | gen8_initialize_pml4(&ppgtt->base, &ppgtt->pml4); |
1586 | ||
762d9936 | 1587 | ppgtt->base.total = 1ULL << 48; |
2dba3239 | 1588 | ppgtt->switch_mm = gen8_48b_mm_switch; |
762d9936 | 1589 | } else { |
275a991c | 1590 | ret = __pdp_init(dev_priv, &ppgtt->pdp); |
81ba8aef MT |
1591 | if (ret) |
1592 | goto free_scratch; | |
1593 | ||
1594 | ppgtt->base.total = 1ULL << 32; | |
2dba3239 | 1595 | ppgtt->switch_mm = gen8_legacy_mm_switch; |
762d9936 MT |
1596 | trace_i915_page_directory_pointer_entry_alloc(&ppgtt->base, |
1597 | 0, 0, | |
1598 | GEN8_PML4E_SHIFT); | |
331f38e7 | 1599 | |
275a991c | 1600 | if (intel_vgpu_active(dev_priv)) { |
331f38e7 ZL |
1601 | ret = gen8_preallocate_top_level_pdps(ppgtt); |
1602 | if (ret) | |
1603 | goto free_scratch; | |
1604 | } | |
81ba8aef | 1605 | } |
6ac18502 | 1606 | |
275a991c | 1607 | if (intel_vgpu_active(dev_priv)) |
650da34c ZL |
1608 | gen8_ppgtt_notify_vgt(ppgtt, true); |
1609 | ||
d7b2633d | 1610 | return 0; |
6ac18502 MT |
1611 | |
1612 | free_scratch: | |
1613 | gen8_free_scratch(&ppgtt->base); | |
1614 | return ret; | |
d7b2633d MT |
1615 | } |
1616 | ||
87d60b63 BW |
1617 | static void gen6_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m) |
1618 | { | |
87d60b63 | 1619 | struct i915_address_space *vm = &ppgtt->base; |
09942c65 | 1620 | struct i915_page_table *unused; |
07749ef3 | 1621 | gen6_pte_t scratch_pte; |
87d60b63 | 1622 | uint32_t pd_entry; |
731f74c5 | 1623 | uint32_t pte, pde; |
09942c65 | 1624 | uint32_t start = ppgtt->base.start, length = ppgtt->base.total; |
87d60b63 | 1625 | |
8bcdd0f7 | 1626 | scratch_pte = vm->pte_encode(vm->scratch_page.daddr, |
4fb84d99 | 1627 | I915_CACHE_LLC, 0); |
87d60b63 | 1628 | |
731f74c5 | 1629 | gen6_for_each_pde(unused, &ppgtt->pd, start, length, pde) { |
87d60b63 | 1630 | u32 expected; |
07749ef3 | 1631 | gen6_pte_t *pt_vaddr; |
567047be | 1632 | const dma_addr_t pt_addr = px_dma(ppgtt->pd.page_table[pde]); |
09942c65 | 1633 | pd_entry = readl(ppgtt->pd_addr + pde); |
87d60b63 BW |
1634 | expected = (GEN6_PDE_ADDR_ENCODE(pt_addr) | GEN6_PDE_VALID); |
1635 | ||
1636 | if (pd_entry != expected) | |
1637 | seq_printf(m, "\tPDE #%d mismatch: Actual PDE: %x Expected PDE: %x\n", | |
1638 | pde, | |
1639 | pd_entry, | |
1640 | expected); | |
1641 | seq_printf(m, "\tPDE: %x\n", pd_entry); | |
1642 | ||
d1c54acd MK |
1643 | pt_vaddr = kmap_px(ppgtt->pd.page_table[pde]); |
1644 | ||
07749ef3 | 1645 | for (pte = 0; pte < GEN6_PTES; pte+=4) { |
87d60b63 | 1646 | unsigned long va = |
07749ef3 | 1647 | (pde * PAGE_SIZE * GEN6_PTES) + |
87d60b63 BW |
1648 | (pte * PAGE_SIZE); |
1649 | int i; | |
1650 | bool found = false; | |
1651 | for (i = 0; i < 4; i++) | |
1652 | if (pt_vaddr[pte + i] != scratch_pte) | |
1653 | found = true; | |
1654 | if (!found) | |
1655 | continue; | |
1656 | ||
1657 | seq_printf(m, "\t\t0x%lx [%03d,%04d]: =", va, pde, pte); | |
1658 | for (i = 0; i < 4; i++) { | |
1659 | if (pt_vaddr[pte + i] != scratch_pte) | |
1660 | seq_printf(m, " %08x", pt_vaddr[pte + i]); | |
1661 | else | |
1662 | seq_puts(m, " SCRATCH "); | |
1663 | } | |
1664 | seq_puts(m, "\n"); | |
1665 | } | |
d1c54acd | 1666 | kunmap_px(ppgtt, pt_vaddr); |
87d60b63 BW |
1667 | } |
1668 | } | |
1669 | ||
678d96fb | 1670 | /* Write pde (index) from the page directory @pd to the page table @pt */ |
ec565b3c MT |
1671 | static void gen6_write_pde(struct i915_page_directory *pd, |
1672 | const int pde, struct i915_page_table *pt) | |
6197349b | 1673 | { |
678d96fb BW |
1674 | /* Caller needs to make sure the write completes if necessary */ |
1675 | struct i915_hw_ppgtt *ppgtt = | |
1676 | container_of(pd, struct i915_hw_ppgtt, pd); | |
1677 | u32 pd_entry; | |
6197349b | 1678 | |
567047be | 1679 | pd_entry = GEN6_PDE_ADDR_ENCODE(px_dma(pt)); |
678d96fb | 1680 | pd_entry |= GEN6_PDE_VALID; |
6197349b | 1681 | |
678d96fb BW |
1682 | writel(pd_entry, ppgtt->pd_addr + pde); |
1683 | } | |
6197349b | 1684 | |
678d96fb BW |
1685 | /* Write all the page tables found in the ppgtt structure to incrementing page |
1686 | * directories. */ | |
1687 | static void gen6_write_page_range(struct drm_i915_private *dev_priv, | |
ec565b3c | 1688 | struct i915_page_directory *pd, |
678d96fb BW |
1689 | uint32_t start, uint32_t length) |
1690 | { | |
72e96d64 | 1691 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
ec565b3c | 1692 | struct i915_page_table *pt; |
731f74c5 | 1693 | uint32_t pde; |
678d96fb | 1694 | |
731f74c5 | 1695 | gen6_for_each_pde(pt, pd, start, length, pde) |
678d96fb BW |
1696 | gen6_write_pde(pd, pde, pt); |
1697 | ||
1698 | /* Make sure write is complete before other code can use this page | |
1699 | * table. Also require for WC mapped PTEs */ | |
72e96d64 | 1700 | readl(ggtt->gsm); |
3e302542 BW |
1701 | } |
1702 | ||
b4a74e3a | 1703 | static uint32_t get_pd_offset(struct i915_hw_ppgtt *ppgtt) |
3e302542 | 1704 | { |
44159ddb | 1705 | BUG_ON(ppgtt->pd.base.ggtt_offset & 0x3f); |
b4a74e3a | 1706 | |
44159ddb | 1707 | return (ppgtt->pd.base.ggtt_offset / 64) << 16; |
b4a74e3a BW |
1708 | } |
1709 | ||
90252e5c | 1710 | static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt, |
e85b26dc | 1711 | struct drm_i915_gem_request *req) |
90252e5c | 1712 | { |
7e37f889 | 1713 | struct intel_ring *ring = req->ring; |
4a570db5 | 1714 | struct intel_engine_cs *engine = req->engine; |
90252e5c BW |
1715 | int ret; |
1716 | ||
90252e5c | 1717 | /* NB: TLBs must be flushed and invalidated before a switch */ |
7c9cf4e3 | 1718 | ret = engine->emit_flush(req, EMIT_INVALIDATE | EMIT_FLUSH); |
90252e5c BW |
1719 | if (ret) |
1720 | return ret; | |
1721 | ||
5fb9de1a | 1722 | ret = intel_ring_begin(req, 6); |
90252e5c BW |
1723 | if (ret) |
1724 | return ret; | |
1725 | ||
b5321f30 CW |
1726 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2)); |
1727 | intel_ring_emit_reg(ring, RING_PP_DIR_DCLV(engine)); | |
1728 | intel_ring_emit(ring, PP_DIR_DCLV_2G); | |
1729 | intel_ring_emit_reg(ring, RING_PP_DIR_BASE(engine)); | |
1730 | intel_ring_emit(ring, get_pd_offset(ppgtt)); | |
1731 | intel_ring_emit(ring, MI_NOOP); | |
1732 | intel_ring_advance(ring); | |
90252e5c BW |
1733 | |
1734 | return 0; | |
1735 | } | |
1736 | ||
48a10389 | 1737 | static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt, |
e85b26dc | 1738 | struct drm_i915_gem_request *req) |
48a10389 | 1739 | { |
7e37f889 | 1740 | struct intel_ring *ring = req->ring; |
4a570db5 | 1741 | struct intel_engine_cs *engine = req->engine; |
48a10389 BW |
1742 | int ret; |
1743 | ||
48a10389 | 1744 | /* NB: TLBs must be flushed and invalidated before a switch */ |
7c9cf4e3 | 1745 | ret = engine->emit_flush(req, EMIT_INVALIDATE | EMIT_FLUSH); |
48a10389 BW |
1746 | if (ret) |
1747 | return ret; | |
1748 | ||
5fb9de1a | 1749 | ret = intel_ring_begin(req, 6); |
48a10389 BW |
1750 | if (ret) |
1751 | return ret; | |
1752 | ||
b5321f30 CW |
1753 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2)); |
1754 | intel_ring_emit_reg(ring, RING_PP_DIR_DCLV(engine)); | |
1755 | intel_ring_emit(ring, PP_DIR_DCLV_2G); | |
1756 | intel_ring_emit_reg(ring, RING_PP_DIR_BASE(engine)); | |
1757 | intel_ring_emit(ring, get_pd_offset(ppgtt)); | |
1758 | intel_ring_emit(ring, MI_NOOP); | |
1759 | intel_ring_advance(ring); | |
48a10389 | 1760 | |
90252e5c | 1761 | /* XXX: RCS is the only one to auto invalidate the TLBs? */ |
e2f80391 | 1762 | if (engine->id != RCS) { |
7c9cf4e3 | 1763 | ret = engine->emit_flush(req, EMIT_INVALIDATE | EMIT_FLUSH); |
90252e5c BW |
1764 | if (ret) |
1765 | return ret; | |
1766 | } | |
1767 | ||
48a10389 BW |
1768 | return 0; |
1769 | } | |
1770 | ||
eeb9488e | 1771 | static int gen6_mm_switch(struct i915_hw_ppgtt *ppgtt, |
e85b26dc | 1772 | struct drm_i915_gem_request *req) |
eeb9488e | 1773 | { |
4a570db5 | 1774 | struct intel_engine_cs *engine = req->engine; |
8eb95204 | 1775 | struct drm_i915_private *dev_priv = req->i915; |
48a10389 | 1776 | |
e2f80391 TU |
1777 | I915_WRITE(RING_PP_DIR_DCLV(engine), PP_DIR_DCLV_2G); |
1778 | I915_WRITE(RING_PP_DIR_BASE(engine), get_pd_offset(ppgtt)); | |
eeb9488e BW |
1779 | return 0; |
1780 | } | |
1781 | ||
c6be607a | 1782 | static void gen8_ppgtt_enable(struct drm_i915_private *dev_priv) |
eeb9488e | 1783 | { |
e2f80391 | 1784 | struct intel_engine_cs *engine; |
3b3f1650 | 1785 | enum intel_engine_id id; |
3e302542 | 1786 | |
3b3f1650 | 1787 | for_each_engine(engine, dev_priv, id) { |
c6be607a TU |
1788 | u32 four_level = USES_FULL_48BIT_PPGTT(dev_priv) ? |
1789 | GEN8_GFX_PPGTT_48B : 0; | |
e2f80391 | 1790 | I915_WRITE(RING_MODE_GEN7(engine), |
2dba3239 | 1791 | _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE | four_level)); |
eeb9488e | 1792 | } |
eeb9488e | 1793 | } |
6197349b | 1794 | |
c6be607a | 1795 | static void gen7_ppgtt_enable(struct drm_i915_private *dev_priv) |
3e302542 | 1796 | { |
e2f80391 | 1797 | struct intel_engine_cs *engine; |
b4a74e3a | 1798 | uint32_t ecochk, ecobits; |
3b3f1650 | 1799 | enum intel_engine_id id; |
6197349b | 1800 | |
b4a74e3a BW |
1801 | ecobits = I915_READ(GAC_ECO_BITS); |
1802 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B); | |
a65c2fcd | 1803 | |
b4a74e3a | 1804 | ecochk = I915_READ(GAM_ECOCHK); |
772c2a51 | 1805 | if (IS_HASWELL(dev_priv)) { |
b4a74e3a BW |
1806 | ecochk |= ECOCHK_PPGTT_WB_HSW; |
1807 | } else { | |
1808 | ecochk |= ECOCHK_PPGTT_LLC_IVB; | |
1809 | ecochk &= ~ECOCHK_PPGTT_GFDT_IVB; | |
1810 | } | |
1811 | I915_WRITE(GAM_ECOCHK, ecochk); | |
a65c2fcd | 1812 | |
3b3f1650 | 1813 | for_each_engine(engine, dev_priv, id) { |
6197349b | 1814 | /* GFX_MODE is per-ring on gen7+ */ |
e2f80391 | 1815 | I915_WRITE(RING_MODE_GEN7(engine), |
b4a74e3a | 1816 | _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); |
6197349b | 1817 | } |
b4a74e3a | 1818 | } |
6197349b | 1819 | |
c6be607a | 1820 | static void gen6_ppgtt_enable(struct drm_i915_private *dev_priv) |
b4a74e3a | 1821 | { |
b4a74e3a | 1822 | uint32_t ecochk, gab_ctl, ecobits; |
a65c2fcd | 1823 | |
b4a74e3a BW |
1824 | ecobits = I915_READ(GAC_ECO_BITS); |
1825 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT | | |
1826 | ECOBITS_PPGTT_CACHE64B); | |
6197349b | 1827 | |
b4a74e3a BW |
1828 | gab_ctl = I915_READ(GAB_CTL); |
1829 | I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT); | |
1830 | ||
1831 | ecochk = I915_READ(GAM_ECOCHK); | |
1832 | I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B); | |
1833 | ||
1834 | I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
6197349b BW |
1835 | } |
1836 | ||
1d2a314c | 1837 | /* PPGTT support for Sandybdrige/Gen6 and later */ |
853ba5d2 | 1838 | static void gen6_ppgtt_clear_range(struct i915_address_space *vm, |
782f1495 | 1839 | uint64_t start, |
4fb84d99 | 1840 | uint64_t length) |
1d2a314c | 1841 | { |
e5716f55 | 1842 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
07749ef3 | 1843 | gen6_pte_t *pt_vaddr, scratch_pte; |
782f1495 BW |
1844 | unsigned first_entry = start >> PAGE_SHIFT; |
1845 | unsigned num_entries = length >> PAGE_SHIFT; | |
07749ef3 MT |
1846 | unsigned act_pt = first_entry / GEN6_PTES; |
1847 | unsigned first_pte = first_entry % GEN6_PTES; | |
7bddb01f | 1848 | unsigned last_pte, i; |
1d2a314c | 1849 | |
8bcdd0f7 | 1850 | scratch_pte = vm->pte_encode(vm->scratch_page.daddr, |
4fb84d99 | 1851 | I915_CACHE_LLC, 0); |
1d2a314c | 1852 | |
7bddb01f DV |
1853 | while (num_entries) { |
1854 | last_pte = first_pte + num_entries; | |
07749ef3 MT |
1855 | if (last_pte > GEN6_PTES) |
1856 | last_pte = GEN6_PTES; | |
7bddb01f | 1857 | |
d1c54acd | 1858 | pt_vaddr = kmap_px(ppgtt->pd.page_table[act_pt]); |
1d2a314c | 1859 | |
7bddb01f DV |
1860 | for (i = first_pte; i < last_pte; i++) |
1861 | pt_vaddr[i] = scratch_pte; | |
1d2a314c | 1862 | |
d1c54acd | 1863 | kunmap_px(ppgtt, pt_vaddr); |
1d2a314c | 1864 | |
7bddb01f DV |
1865 | num_entries -= last_pte - first_pte; |
1866 | first_pte = 0; | |
a15326a5 | 1867 | act_pt++; |
7bddb01f | 1868 | } |
1d2a314c DV |
1869 | } |
1870 | ||
853ba5d2 | 1871 | static void gen6_ppgtt_insert_entries(struct i915_address_space *vm, |
def886c3 | 1872 | struct sg_table *pages, |
782f1495 | 1873 | uint64_t start, |
24f3a8cf | 1874 | enum i915_cache_level cache_level, u32 flags) |
def886c3 | 1875 | { |
e5716f55 | 1876 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
782f1495 | 1877 | unsigned first_entry = start >> PAGE_SHIFT; |
07749ef3 MT |
1878 | unsigned act_pt = first_entry / GEN6_PTES; |
1879 | unsigned act_pte = first_entry % GEN6_PTES; | |
85d1225e DG |
1880 | gen6_pte_t *pt_vaddr = NULL; |
1881 | struct sgt_iter sgt_iter; | |
1882 | dma_addr_t addr; | |
6e995e23 | 1883 | |
85d1225e | 1884 | for_each_sgt_dma(addr, sgt_iter, pages) { |
cc79714f | 1885 | if (pt_vaddr == NULL) |
d1c54acd | 1886 | pt_vaddr = kmap_px(ppgtt->pd.page_table[act_pt]); |
6e995e23 | 1887 | |
cc79714f | 1888 | pt_vaddr[act_pte] = |
4fb84d99 | 1889 | vm->pte_encode(addr, cache_level, flags); |
24f3a8cf | 1890 | |
07749ef3 | 1891 | if (++act_pte == GEN6_PTES) { |
d1c54acd | 1892 | kunmap_px(ppgtt, pt_vaddr); |
cc79714f | 1893 | pt_vaddr = NULL; |
a15326a5 | 1894 | act_pt++; |
6e995e23 | 1895 | act_pte = 0; |
def886c3 | 1896 | } |
def886c3 | 1897 | } |
85d1225e | 1898 | |
cc79714f | 1899 | if (pt_vaddr) |
d1c54acd | 1900 | kunmap_px(ppgtt, pt_vaddr); |
def886c3 DV |
1901 | } |
1902 | ||
678d96fb | 1903 | static int gen6_alloc_va_range(struct i915_address_space *vm, |
a05d80ee | 1904 | uint64_t start_in, uint64_t length_in) |
678d96fb | 1905 | { |
4933d519 | 1906 | DECLARE_BITMAP(new_page_tables, I915_PDES); |
49d73912 | 1907 | struct drm_i915_private *dev_priv = vm->i915; |
72e96d64 | 1908 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
e5716f55 | 1909 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
ec565b3c | 1910 | struct i915_page_table *pt; |
a05d80ee | 1911 | uint32_t start, length, start_save, length_save; |
731f74c5 | 1912 | uint32_t pde; |
4933d519 MT |
1913 | int ret; |
1914 | ||
a05d80ee MK |
1915 | start = start_save = start_in; |
1916 | length = length_save = length_in; | |
4933d519 MT |
1917 | |
1918 | bitmap_zero(new_page_tables, I915_PDES); | |
1919 | ||
1920 | /* The allocation is done in two stages so that we can bail out with | |
1921 | * minimal amount of pain. The first stage finds new page tables that | |
1922 | * need allocation. The second stage marks use ptes within the page | |
1923 | * tables. | |
1924 | */ | |
731f74c5 | 1925 | gen6_for_each_pde(pt, &ppgtt->pd, start, length, pde) { |
79ab9370 | 1926 | if (pt != vm->scratch_pt) { |
4933d519 MT |
1927 | WARN_ON(bitmap_empty(pt->used_ptes, GEN6_PTES)); |
1928 | continue; | |
1929 | } | |
1930 | ||
1931 | /* We've already allocated a page table */ | |
1932 | WARN_ON(!bitmap_empty(pt->used_ptes, GEN6_PTES)); | |
1933 | ||
275a991c | 1934 | pt = alloc_pt(dev_priv); |
4933d519 MT |
1935 | if (IS_ERR(pt)) { |
1936 | ret = PTR_ERR(pt); | |
1937 | goto unwind_out; | |
1938 | } | |
1939 | ||
1940 | gen6_initialize_pt(vm, pt); | |
1941 | ||
1942 | ppgtt->pd.page_table[pde] = pt; | |
966082c9 | 1943 | __set_bit(pde, new_page_tables); |
72744cb1 | 1944 | trace_i915_page_table_entry_alloc(vm, pde, start, GEN6_PDE_SHIFT); |
4933d519 MT |
1945 | } |
1946 | ||
1947 | start = start_save; | |
1948 | length = length_save; | |
678d96fb | 1949 | |
731f74c5 | 1950 | gen6_for_each_pde(pt, &ppgtt->pd, start, length, pde) { |
678d96fb BW |
1951 | DECLARE_BITMAP(tmp_bitmap, GEN6_PTES); |
1952 | ||
1953 | bitmap_zero(tmp_bitmap, GEN6_PTES); | |
1954 | bitmap_set(tmp_bitmap, gen6_pte_index(start), | |
1955 | gen6_pte_count(start, length)); | |
1956 | ||
966082c9 | 1957 | if (__test_and_clear_bit(pde, new_page_tables)) |
4933d519 MT |
1958 | gen6_write_pde(&ppgtt->pd, pde, pt); |
1959 | ||
72744cb1 MT |
1960 | trace_i915_page_table_entry_map(vm, pde, pt, |
1961 | gen6_pte_index(start), | |
1962 | gen6_pte_count(start, length), | |
1963 | GEN6_PTES); | |
4933d519 | 1964 | bitmap_or(pt->used_ptes, tmp_bitmap, pt->used_ptes, |
678d96fb BW |
1965 | GEN6_PTES); |
1966 | } | |
1967 | ||
4933d519 MT |
1968 | WARN_ON(!bitmap_empty(new_page_tables, I915_PDES)); |
1969 | ||
1970 | /* Make sure write is complete before other code can use this page | |
1971 | * table. Also require for WC mapped PTEs */ | |
72e96d64 | 1972 | readl(ggtt->gsm); |
4933d519 | 1973 | |
563222a7 | 1974 | mark_tlbs_dirty(ppgtt); |
678d96fb | 1975 | return 0; |
4933d519 MT |
1976 | |
1977 | unwind_out: | |
1978 | for_each_set_bit(pde, new_page_tables, I915_PDES) { | |
ec565b3c | 1979 | struct i915_page_table *pt = ppgtt->pd.page_table[pde]; |
4933d519 | 1980 | |
79ab9370 | 1981 | ppgtt->pd.page_table[pde] = vm->scratch_pt; |
275a991c | 1982 | free_pt(dev_priv, pt); |
4933d519 MT |
1983 | } |
1984 | ||
1985 | mark_tlbs_dirty(ppgtt); | |
1986 | return ret; | |
678d96fb BW |
1987 | } |
1988 | ||
8776f02b MK |
1989 | static int gen6_init_scratch(struct i915_address_space *vm) |
1990 | { | |
49d73912 | 1991 | struct drm_i915_private *dev_priv = vm->i915; |
8bcdd0f7 | 1992 | int ret; |
8776f02b | 1993 | |
275a991c | 1994 | ret = setup_scratch_page(dev_priv, &vm->scratch_page, I915_GFP_DMA); |
8bcdd0f7 CW |
1995 | if (ret) |
1996 | return ret; | |
8776f02b | 1997 | |
275a991c | 1998 | vm->scratch_pt = alloc_pt(dev_priv); |
8776f02b | 1999 | if (IS_ERR(vm->scratch_pt)) { |
275a991c | 2000 | cleanup_scratch_page(dev_priv, &vm->scratch_page); |
8776f02b MK |
2001 | return PTR_ERR(vm->scratch_pt); |
2002 | } | |
2003 | ||
2004 | gen6_initialize_pt(vm, vm->scratch_pt); | |
2005 | ||
2006 | return 0; | |
2007 | } | |
2008 | ||
2009 | static void gen6_free_scratch(struct i915_address_space *vm) | |
2010 | { | |
49d73912 | 2011 | struct drm_i915_private *dev_priv = vm->i915; |
8776f02b | 2012 | |
275a991c TU |
2013 | free_pt(dev_priv, vm->scratch_pt); |
2014 | cleanup_scratch_page(dev_priv, &vm->scratch_page); | |
8776f02b MK |
2015 | } |
2016 | ||
061dd493 | 2017 | static void gen6_ppgtt_cleanup(struct i915_address_space *vm) |
a00d825d | 2018 | { |
e5716f55 | 2019 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
731f74c5 | 2020 | struct i915_page_directory *pd = &ppgtt->pd; |
49d73912 | 2021 | struct drm_i915_private *dev_priv = vm->i915; |
09942c65 MT |
2022 | struct i915_page_table *pt; |
2023 | uint32_t pde; | |
4933d519 | 2024 | |
061dd493 DV |
2025 | drm_mm_remove_node(&ppgtt->node); |
2026 | ||
731f74c5 | 2027 | gen6_for_all_pdes(pt, pd, pde) |
79ab9370 | 2028 | if (pt != vm->scratch_pt) |
275a991c | 2029 | free_pt(dev_priv, pt); |
06fda602 | 2030 | |
8776f02b | 2031 | gen6_free_scratch(vm); |
3440d265 DV |
2032 | } |
2033 | ||
b146520f | 2034 | static int gen6_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt) |
3440d265 | 2035 | { |
8776f02b | 2036 | struct i915_address_space *vm = &ppgtt->base; |
49d73912 | 2037 | struct drm_i915_private *dev_priv = ppgtt->base.i915; |
72e96d64 | 2038 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
b146520f | 2039 | int ret; |
1d2a314c | 2040 | |
c8d4c0d6 BW |
2041 | /* PPGTT PDEs reside in the GGTT and consists of 512 entries. The |
2042 | * allocator works in address space sizes, so it's multiplied by page | |
2043 | * size. We allocate at the top of the GTT to avoid fragmentation. | |
2044 | */ | |
72e96d64 | 2045 | BUG_ON(!drm_mm_initialized(&ggtt->base.mm)); |
4933d519 | 2046 | |
8776f02b MK |
2047 | ret = gen6_init_scratch(vm); |
2048 | if (ret) | |
2049 | return ret; | |
4933d519 | 2050 | |
e007b19d CW |
2051 | ret = i915_gem_gtt_insert(&ggtt->base, &ppgtt->node, |
2052 | GEN6_PD_SIZE, GEN6_PD_ALIGN, | |
2053 | I915_COLOR_UNEVICTABLE, | |
2054 | 0, ggtt->base.total, | |
2055 | PIN_HIGH); | |
c8c26622 | 2056 | if (ret) |
678d96fb BW |
2057 | goto err_out; |
2058 | ||
72e96d64 | 2059 | if (ppgtt->node.start < ggtt->mappable_end) |
c8d4c0d6 | 2060 | DRM_DEBUG("Forced to use aperture for PDEs\n"); |
1d2a314c | 2061 | |
c8c26622 | 2062 | return 0; |
678d96fb BW |
2063 | |
2064 | err_out: | |
8776f02b | 2065 | gen6_free_scratch(vm); |
678d96fb | 2066 | return ret; |
b146520f BW |
2067 | } |
2068 | ||
b146520f BW |
2069 | static int gen6_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt) |
2070 | { | |
2f2cf682 | 2071 | return gen6_ppgtt_allocate_page_directories(ppgtt); |
4933d519 | 2072 | } |
06dc68d6 | 2073 | |
4933d519 MT |
2074 | static void gen6_scratch_va_range(struct i915_hw_ppgtt *ppgtt, |
2075 | uint64_t start, uint64_t length) | |
2076 | { | |
ec565b3c | 2077 | struct i915_page_table *unused; |
731f74c5 | 2078 | uint32_t pde; |
1d2a314c | 2079 | |
731f74c5 | 2080 | gen6_for_each_pde(unused, &ppgtt->pd, start, length, pde) |
79ab9370 | 2081 | ppgtt->pd.page_table[pde] = ppgtt->base.scratch_pt; |
b146520f BW |
2082 | } |
2083 | ||
5c5f6457 | 2084 | static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt) |
b146520f | 2085 | { |
49d73912 | 2086 | struct drm_i915_private *dev_priv = ppgtt->base.i915; |
72e96d64 | 2087 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
b146520f BW |
2088 | int ret; |
2089 | ||
72e96d64 | 2090 | ppgtt->base.pte_encode = ggtt->base.pte_encode; |
5db94019 | 2091 | if (intel_vgpu_active(dev_priv) || IS_GEN6(dev_priv)) |
b146520f | 2092 | ppgtt->switch_mm = gen6_mm_switch; |
772c2a51 | 2093 | else if (IS_HASWELL(dev_priv)) |
b146520f | 2094 | ppgtt->switch_mm = hsw_mm_switch; |
5db94019 | 2095 | else if (IS_GEN7(dev_priv)) |
b146520f | 2096 | ppgtt->switch_mm = gen7_mm_switch; |
8eb95204 | 2097 | else |
b146520f BW |
2098 | BUG(); |
2099 | ||
2100 | ret = gen6_ppgtt_alloc(ppgtt); | |
2101 | if (ret) | |
2102 | return ret; | |
2103 | ||
5c5f6457 | 2104 | ppgtt->base.allocate_va_range = gen6_alloc_va_range; |
b146520f BW |
2105 | ppgtt->base.clear_range = gen6_ppgtt_clear_range; |
2106 | ppgtt->base.insert_entries = gen6_ppgtt_insert_entries; | |
777dc5bb DV |
2107 | ppgtt->base.unbind_vma = ppgtt_unbind_vma; |
2108 | ppgtt->base.bind_vma = ppgtt_bind_vma; | |
b146520f | 2109 | ppgtt->base.cleanup = gen6_ppgtt_cleanup; |
b146520f | 2110 | ppgtt->base.start = 0; |
09942c65 | 2111 | ppgtt->base.total = I915_PDES * GEN6_PTES * PAGE_SIZE; |
87d60b63 | 2112 | ppgtt->debug_dump = gen6_dump_ppgtt; |
1d2a314c | 2113 | |
44159ddb | 2114 | ppgtt->pd.base.ggtt_offset = |
07749ef3 | 2115 | ppgtt->node.start / PAGE_SIZE * sizeof(gen6_pte_t); |
1d2a314c | 2116 | |
72e96d64 | 2117 | ppgtt->pd_addr = (gen6_pte_t __iomem *)ggtt->gsm + |
44159ddb | 2118 | ppgtt->pd.base.ggtt_offset / sizeof(gen6_pte_t); |
678d96fb | 2119 | |
5c5f6457 | 2120 | gen6_scratch_va_range(ppgtt, 0, ppgtt->base.total); |
1d2a314c | 2121 | |
678d96fb BW |
2122 | gen6_write_page_range(dev_priv, &ppgtt->pd, 0, ppgtt->base.total); |
2123 | ||
440fd528 | 2124 | DRM_DEBUG_DRIVER("Allocated pde space (%lldM) at GTT entry: %llx\n", |
b146520f BW |
2125 | ppgtt->node.size >> 20, |
2126 | ppgtt->node.start / PAGE_SIZE); | |
3440d265 | 2127 | |
fa76da34 | 2128 | DRM_DEBUG("Adding PPGTT at offset %x\n", |
44159ddb | 2129 | ppgtt->pd.base.ggtt_offset << 10); |
fa76da34 | 2130 | |
b146520f | 2131 | return 0; |
3440d265 DV |
2132 | } |
2133 | ||
2bfa996e CW |
2134 | static int __hw_ppgtt_init(struct i915_hw_ppgtt *ppgtt, |
2135 | struct drm_i915_private *dev_priv) | |
3440d265 | 2136 | { |
49d73912 | 2137 | ppgtt->base.i915 = dev_priv; |
3440d265 | 2138 | |
2bfa996e | 2139 | if (INTEL_INFO(dev_priv)->gen < 8) |
5c5f6457 | 2140 | return gen6_ppgtt_init(ppgtt); |
3ed124b2 | 2141 | else |
d7b2633d | 2142 | return gen8_ppgtt_init(ppgtt); |
fa76da34 | 2143 | } |
c114f76a | 2144 | |
a2cad9df | 2145 | static void i915_address_space_init(struct i915_address_space *vm, |
80b204bc CW |
2146 | struct drm_i915_private *dev_priv, |
2147 | const char *name) | |
a2cad9df | 2148 | { |
80b204bc | 2149 | i915_gem_timeline_init(dev_priv, &vm->timeline, name); |
a2cad9df | 2150 | drm_mm_init(&vm->mm, vm->start, vm->total); |
a2cad9df MW |
2151 | INIT_LIST_HEAD(&vm->active_list); |
2152 | INIT_LIST_HEAD(&vm->inactive_list); | |
50e046b6 | 2153 | INIT_LIST_HEAD(&vm->unbound_list); |
a2cad9df MW |
2154 | list_add_tail(&vm->global_link, &dev_priv->vm_list); |
2155 | } | |
2156 | ||
ed9724dd MA |
2157 | static void i915_address_space_fini(struct i915_address_space *vm) |
2158 | { | |
2159 | i915_gem_timeline_fini(&vm->timeline); | |
2160 | drm_mm_takedown(&vm->mm); | |
2161 | list_del(&vm->global_link); | |
2162 | } | |
2163 | ||
c6be607a | 2164 | static void gtt_write_workarounds(struct drm_i915_private *dev_priv) |
d5165ebd | 2165 | { |
d5165ebd TG |
2166 | /* This function is for gtt related workarounds. This function is |
2167 | * called on driver load and after a GPU reset, so you can place | |
2168 | * workarounds here even if they get overwritten by GPU reset. | |
2169 | */ | |
2170 | /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt */ | |
8652744b | 2171 | if (IS_BROADWELL(dev_priv)) |
d5165ebd | 2172 | I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW); |
920a14b2 | 2173 | else if (IS_CHERRYVIEW(dev_priv)) |
d5165ebd | 2174 | I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV); |
d9486e65 | 2175 | else if (IS_SKYLAKE(dev_priv)) |
d5165ebd | 2176 | I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL); |
e2d214ae | 2177 | else if (IS_BROXTON(dev_priv)) |
d5165ebd TG |
2178 | I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT); |
2179 | } | |
2180 | ||
2bfa996e CW |
2181 | static int i915_ppgtt_init(struct i915_hw_ppgtt *ppgtt, |
2182 | struct drm_i915_private *dev_priv, | |
80b204bc CW |
2183 | struct drm_i915_file_private *file_priv, |
2184 | const char *name) | |
fa76da34 | 2185 | { |
2bfa996e | 2186 | int ret; |
3ed124b2 | 2187 | |
2bfa996e | 2188 | ret = __hw_ppgtt_init(ppgtt, dev_priv); |
fa76da34 | 2189 | if (ret == 0) { |
c7c48dfd | 2190 | kref_init(&ppgtt->ref); |
80b204bc | 2191 | i915_address_space_init(&ppgtt->base, dev_priv, name); |
2bfa996e | 2192 | ppgtt->base.file = file_priv; |
93bd8649 | 2193 | } |
1d2a314c DV |
2194 | |
2195 | return ret; | |
2196 | } | |
2197 | ||
c6be607a | 2198 | int i915_ppgtt_init_hw(struct drm_i915_private *dev_priv) |
82460d97 | 2199 | { |
c6be607a | 2200 | gtt_write_workarounds(dev_priv); |
d5165ebd | 2201 | |
671b5013 TD |
2202 | /* In the case of execlists, PPGTT is enabled by the context descriptor |
2203 | * and the PDPs are contained within the context itself. We don't | |
2204 | * need to do anything here. */ | |
2205 | if (i915.enable_execlists) | |
2206 | return 0; | |
2207 | ||
c6be607a | 2208 | if (!USES_PPGTT(dev_priv)) |
82460d97 DV |
2209 | return 0; |
2210 | ||
5db94019 | 2211 | if (IS_GEN6(dev_priv)) |
c6be607a | 2212 | gen6_ppgtt_enable(dev_priv); |
5db94019 | 2213 | else if (IS_GEN7(dev_priv)) |
c6be607a TU |
2214 | gen7_ppgtt_enable(dev_priv); |
2215 | else if (INTEL_GEN(dev_priv) >= 8) | |
2216 | gen8_ppgtt_enable(dev_priv); | |
82460d97 | 2217 | else |
c6be607a | 2218 | MISSING_CASE(INTEL_GEN(dev_priv)); |
82460d97 | 2219 | |
4ad2fd88 JH |
2220 | return 0; |
2221 | } | |
1d2a314c | 2222 | |
4d884705 | 2223 | struct i915_hw_ppgtt * |
2bfa996e | 2224 | i915_ppgtt_create(struct drm_i915_private *dev_priv, |
80b204bc CW |
2225 | struct drm_i915_file_private *fpriv, |
2226 | const char *name) | |
4d884705 DV |
2227 | { |
2228 | struct i915_hw_ppgtt *ppgtt; | |
2229 | int ret; | |
2230 | ||
2231 | ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL); | |
2232 | if (!ppgtt) | |
2233 | return ERR_PTR(-ENOMEM); | |
2234 | ||
80b204bc | 2235 | ret = i915_ppgtt_init(ppgtt, dev_priv, fpriv, name); |
4d884705 DV |
2236 | if (ret) { |
2237 | kfree(ppgtt); | |
2238 | return ERR_PTR(ret); | |
2239 | } | |
2240 | ||
198c974d DCS |
2241 | trace_i915_ppgtt_create(&ppgtt->base); |
2242 | ||
4d884705 DV |
2243 | return ppgtt; |
2244 | } | |
2245 | ||
ed9724dd | 2246 | void i915_ppgtt_release(struct kref *kref) |
ee960be7 DV |
2247 | { |
2248 | struct i915_hw_ppgtt *ppgtt = | |
2249 | container_of(kref, struct i915_hw_ppgtt, ref); | |
2250 | ||
198c974d DCS |
2251 | trace_i915_ppgtt_release(&ppgtt->base); |
2252 | ||
50e046b6 | 2253 | /* vmas should already be unbound and destroyed */ |
ee960be7 DV |
2254 | WARN_ON(!list_empty(&ppgtt->base.active_list)); |
2255 | WARN_ON(!list_empty(&ppgtt->base.inactive_list)); | |
50e046b6 | 2256 | WARN_ON(!list_empty(&ppgtt->base.unbound_list)); |
ee960be7 | 2257 | |
ed9724dd | 2258 | i915_address_space_fini(&ppgtt->base); |
19dd120c | 2259 | |
ee960be7 DV |
2260 | ppgtt->base.cleanup(&ppgtt->base); |
2261 | kfree(ppgtt); | |
2262 | } | |
1d2a314c | 2263 | |
a81cc00c BW |
2264 | /* Certain Gen5 chipsets require require idling the GPU before |
2265 | * unmapping anything from the GTT when VT-d is enabled. | |
2266 | */ | |
97d6d7ab | 2267 | static bool needs_idle_maps(struct drm_i915_private *dev_priv) |
a81cc00c BW |
2268 | { |
2269 | #ifdef CONFIG_INTEL_IOMMU | |
2270 | /* Query intel_iommu to see if we need the workaround. Presumably that | |
2271 | * was loaded first. | |
2272 | */ | |
97d6d7ab | 2273 | if (IS_GEN5(dev_priv) && IS_MOBILE(dev_priv) && intel_iommu_gfx_mapped) |
a81cc00c BW |
2274 | return true; |
2275 | #endif | |
2276 | return false; | |
2277 | } | |
2278 | ||
dc97997a | 2279 | void i915_check_and_clear_faults(struct drm_i915_private *dev_priv) |
828c7908 | 2280 | { |
e2f80391 | 2281 | struct intel_engine_cs *engine; |
3b3f1650 | 2282 | enum intel_engine_id id; |
828c7908 | 2283 | |
dc97997a | 2284 | if (INTEL_INFO(dev_priv)->gen < 6) |
828c7908 BW |
2285 | return; |
2286 | ||
3b3f1650 | 2287 | for_each_engine(engine, dev_priv, id) { |
828c7908 | 2288 | u32 fault_reg; |
e2f80391 | 2289 | fault_reg = I915_READ(RING_FAULT_REG(engine)); |
828c7908 BW |
2290 | if (fault_reg & RING_FAULT_VALID) { |
2291 | DRM_DEBUG_DRIVER("Unexpected fault\n" | |
59a5d290 | 2292 | "\tAddr: 0x%08lx\n" |
828c7908 BW |
2293 | "\tAddress space: %s\n" |
2294 | "\tSource ID: %d\n" | |
2295 | "\tType: %d\n", | |
2296 | fault_reg & PAGE_MASK, | |
2297 | fault_reg & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT", | |
2298 | RING_FAULT_SRCID(fault_reg), | |
2299 | RING_FAULT_FAULT_TYPE(fault_reg)); | |
e2f80391 | 2300 | I915_WRITE(RING_FAULT_REG(engine), |
828c7908 BW |
2301 | fault_reg & ~RING_FAULT_VALID); |
2302 | } | |
2303 | } | |
3b3f1650 AG |
2304 | |
2305 | /* Engine specific init may not have been done till this point. */ | |
2306 | if (dev_priv->engine[RCS]) | |
2307 | POSTING_READ(RING_FAULT_REG(dev_priv->engine[RCS])); | |
828c7908 BW |
2308 | } |
2309 | ||
91e56499 CW |
2310 | static void i915_ggtt_flush(struct drm_i915_private *dev_priv) |
2311 | { | |
2d1fe073 | 2312 | if (INTEL_INFO(dev_priv)->gen < 6) { |
91e56499 CW |
2313 | intel_gtt_chipset_flush(); |
2314 | } else { | |
2315 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
2316 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
2317 | } | |
2318 | } | |
2319 | ||
275a991c | 2320 | void i915_gem_suspend_gtt_mappings(struct drm_i915_private *dev_priv) |
828c7908 | 2321 | { |
72e96d64 | 2322 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
828c7908 BW |
2323 | |
2324 | /* Don't bother messing with faults pre GEN6 as we have little | |
2325 | * documentation supporting that it's a good idea. | |
2326 | */ | |
275a991c | 2327 | if (INTEL_GEN(dev_priv) < 6) |
828c7908 BW |
2328 | return; |
2329 | ||
dc97997a | 2330 | i915_check_and_clear_faults(dev_priv); |
828c7908 | 2331 | |
4fb84d99 | 2332 | ggtt->base.clear_range(&ggtt->base, ggtt->base.start, ggtt->base.total); |
91e56499 CW |
2333 | |
2334 | i915_ggtt_flush(dev_priv); | |
828c7908 BW |
2335 | } |
2336 | ||
03ac84f1 CW |
2337 | int i915_gem_gtt_prepare_pages(struct drm_i915_gem_object *obj, |
2338 | struct sg_table *pages) | |
7c2e6fdf | 2339 | { |
1a292fa5 CW |
2340 | do { |
2341 | if (dma_map_sg(&obj->base.dev->pdev->dev, | |
2342 | pages->sgl, pages->nents, | |
2343 | PCI_DMA_BIDIRECTIONAL)) | |
2344 | return 0; | |
2345 | ||
2346 | /* If the DMA remap fails, one cause can be that we have | |
2347 | * too many objects pinned in a small remapping table, | |
2348 | * such as swiotlb. Incrementally purge all other objects and | |
2349 | * try again - if there are no more pages to remove from | |
2350 | * the DMA remapper, i915_gem_shrink will return 0. | |
2351 | */ | |
2352 | GEM_BUG_ON(obj->mm.pages == pages); | |
2353 | } while (i915_gem_shrink(to_i915(obj->base.dev), | |
2354 | obj->base.size >> PAGE_SHIFT, | |
2355 | I915_SHRINK_BOUND | | |
2356 | I915_SHRINK_UNBOUND | | |
2357 | I915_SHRINK_ACTIVE)); | |
9da3da66 | 2358 | |
03ac84f1 | 2359 | return -ENOSPC; |
7c2e6fdf DV |
2360 | } |
2361 | ||
2c642b07 | 2362 | static void gen8_set_pte(void __iomem *addr, gen8_pte_t pte) |
94ec8f61 | 2363 | { |
94ec8f61 | 2364 | writeq(pte, addr); |
94ec8f61 BW |
2365 | } |
2366 | ||
d6473f56 CW |
2367 | static void gen8_ggtt_insert_page(struct i915_address_space *vm, |
2368 | dma_addr_t addr, | |
2369 | uint64_t offset, | |
2370 | enum i915_cache_level level, | |
2371 | u32 unused) | |
2372 | { | |
49d73912 | 2373 | struct drm_i915_private *dev_priv = vm->i915; |
d6473f56 CW |
2374 | gen8_pte_t __iomem *pte = |
2375 | (gen8_pte_t __iomem *)dev_priv->ggtt.gsm + | |
2376 | (offset >> PAGE_SHIFT); | |
d6473f56 | 2377 | |
4fb84d99 | 2378 | gen8_set_pte(pte, gen8_pte_encode(addr, level)); |
d6473f56 CW |
2379 | |
2380 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
2381 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
d6473f56 CW |
2382 | } |
2383 | ||
94ec8f61 BW |
2384 | static void gen8_ggtt_insert_entries(struct i915_address_space *vm, |
2385 | struct sg_table *st, | |
782f1495 | 2386 | uint64_t start, |
24f3a8cf | 2387 | enum i915_cache_level level, u32 unused) |
94ec8f61 | 2388 | { |
49d73912 | 2389 | struct drm_i915_private *dev_priv = vm->i915; |
ce7fda2e | 2390 | struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm); |
85d1225e DG |
2391 | struct sgt_iter sgt_iter; |
2392 | gen8_pte_t __iomem *gtt_entries; | |
2393 | gen8_pte_t gtt_entry; | |
2394 | dma_addr_t addr; | |
85d1225e | 2395 | int i = 0; |
be69459a | 2396 | |
85d1225e DG |
2397 | gtt_entries = (gen8_pte_t __iomem *)ggtt->gsm + (start >> PAGE_SHIFT); |
2398 | ||
2399 | for_each_sgt_dma(addr, sgt_iter, st) { | |
4fb84d99 | 2400 | gtt_entry = gen8_pte_encode(addr, level); |
85d1225e | 2401 | gen8_set_pte(>t_entries[i++], gtt_entry); |
94ec8f61 BW |
2402 | } |
2403 | ||
2404 | /* | |
2405 | * XXX: This serves as a posting read to make sure that the PTE has | |
2406 | * actually been updated. There is some concern that even though | |
2407 | * registers and PTEs are within the same BAR that they are potentially | |
2408 | * of NUMA access patterns. Therefore, even with the way we assume | |
2409 | * hardware should work, we must keep this posting read for paranoia. | |
2410 | */ | |
2411 | if (i != 0) | |
85d1225e | 2412 | WARN_ON(readq(>t_entries[i-1]) != gtt_entry); |
94ec8f61 | 2413 | |
94ec8f61 BW |
2414 | /* This next bit makes the above posting read even more important. We |
2415 | * want to flush the TLBs only after we're certain all the PTE updates | |
2416 | * have finished. | |
2417 | */ | |
2418 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
2419 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
94ec8f61 BW |
2420 | } |
2421 | ||
c140330b CW |
2422 | struct insert_entries { |
2423 | struct i915_address_space *vm; | |
2424 | struct sg_table *st; | |
2425 | uint64_t start; | |
2426 | enum i915_cache_level level; | |
2427 | u32 flags; | |
2428 | }; | |
2429 | ||
2430 | static int gen8_ggtt_insert_entries__cb(void *_arg) | |
2431 | { | |
2432 | struct insert_entries *arg = _arg; | |
2433 | gen8_ggtt_insert_entries(arg->vm, arg->st, | |
2434 | arg->start, arg->level, arg->flags); | |
2435 | return 0; | |
2436 | } | |
2437 | ||
2438 | static void gen8_ggtt_insert_entries__BKL(struct i915_address_space *vm, | |
2439 | struct sg_table *st, | |
2440 | uint64_t start, | |
2441 | enum i915_cache_level level, | |
2442 | u32 flags) | |
2443 | { | |
2444 | struct insert_entries arg = { vm, st, start, level, flags }; | |
2445 | stop_machine(gen8_ggtt_insert_entries__cb, &arg, NULL); | |
2446 | } | |
2447 | ||
d6473f56 CW |
2448 | static void gen6_ggtt_insert_page(struct i915_address_space *vm, |
2449 | dma_addr_t addr, | |
2450 | uint64_t offset, | |
2451 | enum i915_cache_level level, | |
2452 | u32 flags) | |
2453 | { | |
49d73912 | 2454 | struct drm_i915_private *dev_priv = vm->i915; |
d6473f56 CW |
2455 | gen6_pte_t __iomem *pte = |
2456 | (gen6_pte_t __iomem *)dev_priv->ggtt.gsm + | |
2457 | (offset >> PAGE_SHIFT); | |
d6473f56 | 2458 | |
4fb84d99 | 2459 | iowrite32(vm->pte_encode(addr, level, flags), pte); |
d6473f56 CW |
2460 | |
2461 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
2462 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
d6473f56 CW |
2463 | } |
2464 | ||
e76e9aeb BW |
2465 | /* |
2466 | * Binds an object into the global gtt with the specified cache level. The object | |
2467 | * will be accessible to the GPU via commands whose operands reference offsets | |
2468 | * within the global GTT as well as accessible by the GPU through the GMADR | |
2469 | * mapped BAR (dev_priv->mm.gtt->gtt). | |
2470 | */ | |
853ba5d2 | 2471 | static void gen6_ggtt_insert_entries(struct i915_address_space *vm, |
7faf1ab2 | 2472 | struct sg_table *st, |
782f1495 | 2473 | uint64_t start, |
24f3a8cf | 2474 | enum i915_cache_level level, u32 flags) |
e76e9aeb | 2475 | { |
49d73912 | 2476 | struct drm_i915_private *dev_priv = vm->i915; |
ce7fda2e | 2477 | struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm); |
85d1225e DG |
2478 | struct sgt_iter sgt_iter; |
2479 | gen6_pte_t __iomem *gtt_entries; | |
2480 | gen6_pte_t gtt_entry; | |
2481 | dma_addr_t addr; | |
85d1225e | 2482 | int i = 0; |
be69459a | 2483 | |
85d1225e DG |
2484 | gtt_entries = (gen6_pte_t __iomem *)ggtt->gsm + (start >> PAGE_SHIFT); |
2485 | ||
2486 | for_each_sgt_dma(addr, sgt_iter, st) { | |
4fb84d99 | 2487 | gtt_entry = vm->pte_encode(addr, level, flags); |
85d1225e | 2488 | iowrite32(gtt_entry, >t_entries[i++]); |
e76e9aeb BW |
2489 | } |
2490 | ||
e76e9aeb BW |
2491 | /* XXX: This serves as a posting read to make sure that the PTE has |
2492 | * actually been updated. There is some concern that even though | |
2493 | * registers and PTEs are within the same BAR that they are potentially | |
2494 | * of NUMA access patterns. Therefore, even with the way we assume | |
2495 | * hardware should work, we must keep this posting read for paranoia. | |
2496 | */ | |
85d1225e DG |
2497 | if (i != 0) |
2498 | WARN_ON(readl(>t_entries[i-1]) != gtt_entry); | |
0f9b91c7 BW |
2499 | |
2500 | /* This next bit makes the above posting read even more important. We | |
2501 | * want to flush the TLBs only after we're certain all the PTE updates | |
2502 | * have finished. | |
2503 | */ | |
2504 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
2505 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
e76e9aeb BW |
2506 | } |
2507 | ||
f7770bfd | 2508 | static void nop_clear_range(struct i915_address_space *vm, |
4fb84d99 | 2509 | uint64_t start, uint64_t length) |
f7770bfd CW |
2510 | { |
2511 | } | |
2512 | ||
94ec8f61 | 2513 | static void gen8_ggtt_clear_range(struct i915_address_space *vm, |
4fb84d99 | 2514 | uint64_t start, uint64_t length) |
94ec8f61 | 2515 | { |
ce7fda2e | 2516 | struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm); |
782f1495 BW |
2517 | unsigned first_entry = start >> PAGE_SHIFT; |
2518 | unsigned num_entries = length >> PAGE_SHIFT; | |
07749ef3 | 2519 | gen8_pte_t scratch_pte, __iomem *gtt_base = |
72e96d64 JL |
2520 | (gen8_pte_t __iomem *)ggtt->gsm + first_entry; |
2521 | const int max_entries = ggtt_total_entries(ggtt) - first_entry; | |
94ec8f61 BW |
2522 | int i; |
2523 | ||
2524 | if (WARN(num_entries > max_entries, | |
2525 | "First entry = %d; Num entries = %d (max=%d)\n", | |
2526 | first_entry, num_entries, max_entries)) | |
2527 | num_entries = max_entries; | |
2528 | ||
8bcdd0f7 | 2529 | scratch_pte = gen8_pte_encode(vm->scratch_page.daddr, |
4fb84d99 | 2530 | I915_CACHE_LLC); |
94ec8f61 BW |
2531 | for (i = 0; i < num_entries; i++) |
2532 | gen8_set_pte(>t_base[i], scratch_pte); | |
2533 | readl(gtt_base); | |
2534 | } | |
2535 | ||
853ba5d2 | 2536 | static void gen6_ggtt_clear_range(struct i915_address_space *vm, |
782f1495 | 2537 | uint64_t start, |
4fb84d99 | 2538 | uint64_t length) |
7faf1ab2 | 2539 | { |
ce7fda2e | 2540 | struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm); |
782f1495 BW |
2541 | unsigned first_entry = start >> PAGE_SHIFT; |
2542 | unsigned num_entries = length >> PAGE_SHIFT; | |
07749ef3 | 2543 | gen6_pte_t scratch_pte, __iomem *gtt_base = |
72e96d64 JL |
2544 | (gen6_pte_t __iomem *)ggtt->gsm + first_entry; |
2545 | const int max_entries = ggtt_total_entries(ggtt) - first_entry; | |
7faf1ab2 DV |
2546 | int i; |
2547 | ||
2548 | if (WARN(num_entries > max_entries, | |
2549 | "First entry = %d; Num entries = %d (max=%d)\n", | |
2550 | first_entry, num_entries, max_entries)) | |
2551 | num_entries = max_entries; | |
2552 | ||
8bcdd0f7 | 2553 | scratch_pte = vm->pte_encode(vm->scratch_page.daddr, |
4fb84d99 | 2554 | I915_CACHE_LLC, 0); |
828c7908 | 2555 | |
7faf1ab2 DV |
2556 | for (i = 0; i < num_entries; i++) |
2557 | iowrite32(scratch_pte, >t_base[i]); | |
2558 | readl(gtt_base); | |
2559 | } | |
2560 | ||
d6473f56 CW |
2561 | static void i915_ggtt_insert_page(struct i915_address_space *vm, |
2562 | dma_addr_t addr, | |
2563 | uint64_t offset, | |
2564 | enum i915_cache_level cache_level, | |
2565 | u32 unused) | |
2566 | { | |
d6473f56 CW |
2567 | unsigned int flags = (cache_level == I915_CACHE_NONE) ? |
2568 | AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY; | |
d6473f56 CW |
2569 | |
2570 | intel_gtt_insert_page(addr, offset >> PAGE_SHIFT, flags); | |
d6473f56 CW |
2571 | } |
2572 | ||
d369d2d9 DV |
2573 | static void i915_ggtt_insert_entries(struct i915_address_space *vm, |
2574 | struct sg_table *pages, | |
2575 | uint64_t start, | |
2576 | enum i915_cache_level cache_level, u32 unused) | |
7faf1ab2 DV |
2577 | { |
2578 | unsigned int flags = (cache_level == I915_CACHE_NONE) ? | |
2579 | AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY; | |
2580 | ||
d369d2d9 | 2581 | intel_gtt_insert_sg_entries(pages, start >> PAGE_SHIFT, flags); |
0875546c | 2582 | |
7faf1ab2 DV |
2583 | } |
2584 | ||
853ba5d2 | 2585 | static void i915_ggtt_clear_range(struct i915_address_space *vm, |
782f1495 | 2586 | uint64_t start, |
4fb84d99 | 2587 | uint64_t length) |
7faf1ab2 | 2588 | { |
2eedfc7d | 2589 | intel_gtt_clear_range(start >> PAGE_SHIFT, length >> PAGE_SHIFT); |
7faf1ab2 DV |
2590 | } |
2591 | ||
70b9f6f8 DV |
2592 | static int ggtt_bind_vma(struct i915_vma *vma, |
2593 | enum i915_cache_level cache_level, | |
2594 | u32 flags) | |
0a878716 | 2595 | { |
49d73912 | 2596 | struct drm_i915_private *i915 = vma->vm->i915; |
0a878716 DV |
2597 | struct drm_i915_gem_object *obj = vma->obj; |
2598 | u32 pte_flags = 0; | |
2599 | int ret; | |
2600 | ||
2601 | ret = i915_get_ggtt_vma_pages(vma); | |
2602 | if (ret) | |
2603 | return ret; | |
2604 | ||
2605 | /* Currently applicable only to VLV */ | |
2606 | if (obj->gt_ro) | |
2607 | pte_flags |= PTE_READ_ONLY; | |
2608 | ||
9c870d03 | 2609 | intel_runtime_pm_get(i915); |
247177dd | 2610 | vma->vm->insert_entries(vma->vm, vma->pages, vma->node.start, |
0a878716 | 2611 | cache_level, pte_flags); |
9c870d03 | 2612 | intel_runtime_pm_put(i915); |
0a878716 DV |
2613 | |
2614 | /* | |
2615 | * Without aliasing PPGTT there's no difference between | |
2616 | * GLOBAL/LOCAL_BIND, it's all the same ptes. Hence unconditionally | |
2617 | * upgrade to both bound if we bind either to avoid double-binding. | |
2618 | */ | |
3272db53 | 2619 | vma->flags |= I915_VMA_GLOBAL_BIND | I915_VMA_LOCAL_BIND; |
0a878716 DV |
2620 | |
2621 | return 0; | |
2622 | } | |
2623 | ||
2624 | static int aliasing_gtt_bind_vma(struct i915_vma *vma, | |
2625 | enum i915_cache_level cache_level, | |
2626 | u32 flags) | |
d5bd1449 | 2627 | { |
49d73912 | 2628 | struct drm_i915_private *i915 = vma->vm->i915; |
321d178e | 2629 | u32 pte_flags; |
70b9f6f8 DV |
2630 | int ret; |
2631 | ||
2632 | ret = i915_get_ggtt_vma_pages(vma); | |
2633 | if (ret) | |
2634 | return ret; | |
7faf1ab2 | 2635 | |
24f3a8cf | 2636 | /* Currently applicable only to VLV */ |
321d178e CW |
2637 | pte_flags = 0; |
2638 | if (vma->obj->gt_ro) | |
f329f5f6 | 2639 | pte_flags |= PTE_READ_ONLY; |
24f3a8cf | 2640 | |
ec7adb6e | 2641 | |
3272db53 | 2642 | if (flags & I915_VMA_GLOBAL_BIND) { |
9c870d03 | 2643 | intel_runtime_pm_get(i915); |
321d178e | 2644 | vma->vm->insert_entries(vma->vm, |
247177dd | 2645 | vma->pages, vma->node.start, |
0875546c | 2646 | cache_level, pte_flags); |
9c870d03 | 2647 | intel_runtime_pm_put(i915); |
6f65e29a | 2648 | } |
d5bd1449 | 2649 | |
3272db53 | 2650 | if (flags & I915_VMA_LOCAL_BIND) { |
9c870d03 | 2651 | struct i915_hw_ppgtt *appgtt = i915->mm.aliasing_ppgtt; |
321d178e | 2652 | appgtt->base.insert_entries(&appgtt->base, |
247177dd | 2653 | vma->pages, vma->node.start, |
f329f5f6 | 2654 | cache_level, pte_flags); |
6f65e29a | 2655 | } |
70b9f6f8 DV |
2656 | |
2657 | return 0; | |
d5bd1449 CW |
2658 | } |
2659 | ||
6f65e29a | 2660 | static void ggtt_unbind_vma(struct i915_vma *vma) |
74163907 | 2661 | { |
49d73912 | 2662 | struct drm_i915_private *i915 = vma->vm->i915; |
9c870d03 | 2663 | struct i915_hw_ppgtt *appgtt = i915->mm.aliasing_ppgtt; |
de180033 | 2664 | const u64 size = min(vma->size, vma->node.size); |
6f65e29a | 2665 | |
9c870d03 CW |
2666 | if (vma->flags & I915_VMA_GLOBAL_BIND) { |
2667 | intel_runtime_pm_get(i915); | |
782f1495 | 2668 | vma->vm->clear_range(vma->vm, |
4fb84d99 | 2669 | vma->node.start, size); |
9c870d03 CW |
2670 | intel_runtime_pm_put(i915); |
2671 | } | |
06615ee5 | 2672 | |
3272db53 | 2673 | if (vma->flags & I915_VMA_LOCAL_BIND && appgtt) |
6f65e29a | 2674 | appgtt->base.clear_range(&appgtt->base, |
4fb84d99 | 2675 | vma->node.start, size); |
74163907 DV |
2676 | } |
2677 | ||
03ac84f1 CW |
2678 | void i915_gem_gtt_finish_pages(struct drm_i915_gem_object *obj, |
2679 | struct sg_table *pages) | |
7c2e6fdf | 2680 | { |
52a05c30 DW |
2681 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
2682 | struct device *kdev = &dev_priv->drm.pdev->dev; | |
307dc25b | 2683 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
5c042287 | 2684 | |
307dc25b | 2685 | if (unlikely(ggtt->do_idle_maps)) { |
22dd3bb9 | 2686 | if (i915_gem_wait_for_idle(dev_priv, I915_WAIT_LOCKED)) { |
307dc25b CW |
2687 | DRM_ERROR("Failed to wait for idle; VT'd may hang.\n"); |
2688 | /* Wait a bit, in hopes it avoids the hang */ | |
2689 | udelay(10); | |
2690 | } | |
2691 | } | |
5c042287 | 2692 | |
03ac84f1 | 2693 | dma_unmap_sg(kdev, pages->sgl, pages->nents, PCI_DMA_BIDIRECTIONAL); |
7c2e6fdf | 2694 | } |
644ec02b | 2695 | |
45b186f1 | 2696 | static void i915_gtt_color_adjust(const struct drm_mm_node *node, |
42d6ab48 | 2697 | unsigned long color, |
440fd528 TR |
2698 | u64 *start, |
2699 | u64 *end) | |
42d6ab48 CW |
2700 | { |
2701 | if (node->color != color) | |
f51455d4 | 2702 | *start += I915_GTT_PAGE_SIZE; |
42d6ab48 | 2703 | |
b44f97fd CW |
2704 | node = list_next_entry(node, node_list); |
2705 | if (node->allocated && node->color != color) | |
f51455d4 | 2706 | *end -= I915_GTT_PAGE_SIZE; |
42d6ab48 | 2707 | } |
fbe5d36e | 2708 | |
f6b9d5ca | 2709 | int i915_gem_init_ggtt(struct drm_i915_private *dev_priv) |
644ec02b | 2710 | { |
e78891ca BW |
2711 | /* Let GEM Manage all of the aperture. |
2712 | * | |
2713 | * However, leave one page at the end still bound to the scratch page. | |
2714 | * There are a number of places where the hardware apparently prefetches | |
2715 | * past the end of the object, and we've seen multiple hangs with the | |
2716 | * GPU head pointer stuck in a batchbuffer bound at the last page of the | |
2717 | * aperture. One page should be enough to keep any prefetching inside | |
2718 | * of the aperture. | |
2719 | */ | |
72e96d64 | 2720 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
ed2f3452 | 2721 | unsigned long hole_start, hole_end; |
95374d75 | 2722 | struct i915_hw_ppgtt *ppgtt; |
f6b9d5ca | 2723 | struct drm_mm_node *entry; |
fa76da34 | 2724 | int ret; |
644ec02b | 2725 | |
b02d22a3 ZW |
2726 | ret = intel_vgt_balloon(dev_priv); |
2727 | if (ret) | |
2728 | return ret; | |
5dda8fa3 | 2729 | |
95374d75 CW |
2730 | /* Reserve a mappable slot for our lockless error capture */ |
2731 | ret = drm_mm_insert_node_in_range_generic(&ggtt->base.mm, | |
2732 | &ggtt->error_capture, | |
f51455d4 | 2733 | PAGE_SIZE, 0, |
85fd4f58 | 2734 | I915_COLOR_UNEVICTABLE, |
95374d75 CW |
2735 | 0, ggtt->mappable_end, |
2736 | 0, 0); | |
2737 | if (ret) | |
2738 | return ret; | |
2739 | ||
ed2f3452 | 2740 | /* Clear any non-preallocated blocks */ |
72e96d64 | 2741 | drm_mm_for_each_hole(entry, &ggtt->base.mm, hole_start, hole_end) { |
ed2f3452 CW |
2742 | DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n", |
2743 | hole_start, hole_end); | |
72e96d64 | 2744 | ggtt->base.clear_range(&ggtt->base, hole_start, |
4fb84d99 | 2745 | hole_end - hole_start); |
ed2f3452 CW |
2746 | } |
2747 | ||
2748 | /* And finally clear the reserved guard page */ | |
f6b9d5ca | 2749 | ggtt->base.clear_range(&ggtt->base, |
4fb84d99 | 2750 | ggtt->base.total - PAGE_SIZE, PAGE_SIZE); |
6c5566a8 | 2751 | |
97d6d7ab | 2752 | if (USES_PPGTT(dev_priv) && !USES_FULL_PPGTT(dev_priv)) { |
fa76da34 | 2753 | ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL); |
95374d75 CW |
2754 | if (!ppgtt) { |
2755 | ret = -ENOMEM; | |
2756 | goto err; | |
2757 | } | |
fa76da34 | 2758 | |
2bfa996e | 2759 | ret = __hw_ppgtt_init(ppgtt, dev_priv); |
95374d75 CW |
2760 | if (ret) |
2761 | goto err_ppgtt; | |
5c5f6457 | 2762 | |
95374d75 | 2763 | if (ppgtt->base.allocate_va_range) { |
5c5f6457 DV |
2764 | ret = ppgtt->base.allocate_va_range(&ppgtt->base, 0, |
2765 | ppgtt->base.total); | |
95374d75 CW |
2766 | if (ret) |
2767 | goto err_ppgtt_cleanup; | |
4933d519 | 2768 | } |
fa76da34 | 2769 | |
5c5f6457 DV |
2770 | ppgtt->base.clear_range(&ppgtt->base, |
2771 | ppgtt->base.start, | |
4fb84d99 | 2772 | ppgtt->base.total); |
5c5f6457 | 2773 | |
fa76da34 | 2774 | dev_priv->mm.aliasing_ppgtt = ppgtt; |
72e96d64 JL |
2775 | WARN_ON(ggtt->base.bind_vma != ggtt_bind_vma); |
2776 | ggtt->base.bind_vma = aliasing_gtt_bind_vma; | |
fa76da34 DV |
2777 | } |
2778 | ||
6c5566a8 | 2779 | return 0; |
95374d75 CW |
2780 | |
2781 | err_ppgtt_cleanup: | |
2782 | ppgtt->base.cleanup(&ppgtt->base); | |
2783 | err_ppgtt: | |
2784 | kfree(ppgtt); | |
2785 | err: | |
2786 | drm_mm_remove_node(&ggtt->error_capture); | |
2787 | return ret; | |
e76e9aeb BW |
2788 | } |
2789 | ||
d85489d3 JL |
2790 | /** |
2791 | * i915_ggtt_cleanup_hw - Clean up GGTT hardware initialization | |
97d6d7ab | 2792 | * @dev_priv: i915 device |
d85489d3 | 2793 | */ |
97d6d7ab | 2794 | void i915_ggtt_cleanup_hw(struct drm_i915_private *dev_priv) |
90d0a0e8 | 2795 | { |
72e96d64 | 2796 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
90d0a0e8 | 2797 | |
70e32544 DV |
2798 | if (dev_priv->mm.aliasing_ppgtt) { |
2799 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
70e32544 | 2800 | ppgtt->base.cleanup(&ppgtt->base); |
cb7f2760 | 2801 | kfree(ppgtt); |
70e32544 DV |
2802 | } |
2803 | ||
97d6d7ab | 2804 | i915_gem_cleanup_stolen(&dev_priv->drm); |
a4eba47b | 2805 | |
95374d75 CW |
2806 | if (drm_mm_node_allocated(&ggtt->error_capture)) |
2807 | drm_mm_remove_node(&ggtt->error_capture); | |
2808 | ||
72e96d64 | 2809 | if (drm_mm_initialized(&ggtt->base.mm)) { |
b02d22a3 | 2810 | intel_vgt_deballoon(dev_priv); |
5dda8fa3 | 2811 | |
ed9724dd MA |
2812 | mutex_lock(&dev_priv->drm.struct_mutex); |
2813 | i915_address_space_fini(&ggtt->base); | |
2814 | mutex_unlock(&dev_priv->drm.struct_mutex); | |
90d0a0e8 DV |
2815 | } |
2816 | ||
72e96d64 | 2817 | ggtt->base.cleanup(&ggtt->base); |
f6b9d5ca CW |
2818 | |
2819 | arch_phys_wc_del(ggtt->mtrr); | |
f7bbe788 | 2820 | io_mapping_fini(&ggtt->mappable); |
90d0a0e8 | 2821 | } |
70e32544 | 2822 | |
2c642b07 | 2823 | static unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl) |
e76e9aeb BW |
2824 | { |
2825 | snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT; | |
2826 | snb_gmch_ctl &= SNB_GMCH_GGMS_MASK; | |
2827 | return snb_gmch_ctl << 20; | |
2828 | } | |
2829 | ||
2c642b07 | 2830 | static unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl) |
9459d252 BW |
2831 | { |
2832 | bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT; | |
2833 | bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK; | |
2834 | if (bdw_gmch_ctl) | |
2835 | bdw_gmch_ctl = 1 << bdw_gmch_ctl; | |
562d55d9 BW |
2836 | |
2837 | #ifdef CONFIG_X86_32 | |
2838 | /* Limit 32b platforms to a 2GB GGTT: 4 << 20 / pte size * PAGE_SIZE */ | |
2839 | if (bdw_gmch_ctl > 4) | |
2840 | bdw_gmch_ctl = 4; | |
2841 | #endif | |
2842 | ||
9459d252 BW |
2843 | return bdw_gmch_ctl << 20; |
2844 | } | |
2845 | ||
2c642b07 | 2846 | static unsigned int chv_get_total_gtt_size(u16 gmch_ctrl) |
d7f25f23 DL |
2847 | { |
2848 | gmch_ctrl >>= SNB_GMCH_GGMS_SHIFT; | |
2849 | gmch_ctrl &= SNB_GMCH_GGMS_MASK; | |
2850 | ||
2851 | if (gmch_ctrl) | |
2852 | return 1 << (20 + gmch_ctrl); | |
2853 | ||
2854 | return 0; | |
2855 | } | |
2856 | ||
2c642b07 | 2857 | static size_t gen6_get_stolen_size(u16 snb_gmch_ctl) |
e76e9aeb BW |
2858 | { |
2859 | snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT; | |
2860 | snb_gmch_ctl &= SNB_GMCH_GMS_MASK; | |
2861 | return snb_gmch_ctl << 25; /* 32 MB units */ | |
2862 | } | |
2863 | ||
2c642b07 | 2864 | static size_t gen8_get_stolen_size(u16 bdw_gmch_ctl) |
9459d252 BW |
2865 | { |
2866 | bdw_gmch_ctl >>= BDW_GMCH_GMS_SHIFT; | |
2867 | bdw_gmch_ctl &= BDW_GMCH_GMS_MASK; | |
2868 | return bdw_gmch_ctl << 25; /* 32 MB units */ | |
2869 | } | |
2870 | ||
d7f25f23 DL |
2871 | static size_t chv_get_stolen_size(u16 gmch_ctrl) |
2872 | { | |
2873 | gmch_ctrl >>= SNB_GMCH_GMS_SHIFT; | |
2874 | gmch_ctrl &= SNB_GMCH_GMS_MASK; | |
2875 | ||
2876 | /* | |
2877 | * 0x0 to 0x10: 32MB increments starting at 0MB | |
2878 | * 0x11 to 0x16: 4MB increments starting at 8MB | |
2879 | * 0x17 to 0x1d: 4MB increments start at 36MB | |
2880 | */ | |
2881 | if (gmch_ctrl < 0x11) | |
2882 | return gmch_ctrl << 25; | |
2883 | else if (gmch_ctrl < 0x17) | |
2884 | return (gmch_ctrl - 0x11 + 2) << 22; | |
2885 | else | |
2886 | return (gmch_ctrl - 0x17 + 9) << 22; | |
2887 | } | |
2888 | ||
66375014 DL |
2889 | static size_t gen9_get_stolen_size(u16 gen9_gmch_ctl) |
2890 | { | |
2891 | gen9_gmch_ctl >>= BDW_GMCH_GMS_SHIFT; | |
2892 | gen9_gmch_ctl &= BDW_GMCH_GMS_MASK; | |
2893 | ||
2894 | if (gen9_gmch_ctl < 0xf0) | |
2895 | return gen9_gmch_ctl << 25; /* 32 MB units */ | |
2896 | else | |
2897 | /* 4MB increments starting at 0xf0 for 4MB */ | |
2898 | return (gen9_gmch_ctl - 0xf0 + 1) << 22; | |
2899 | } | |
2900 | ||
34c998b4 | 2901 | static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size) |
63340133 | 2902 | { |
49d73912 CW |
2903 | struct drm_i915_private *dev_priv = ggtt->base.i915; |
2904 | struct pci_dev *pdev = dev_priv->drm.pdev; | |
34c998b4 | 2905 | phys_addr_t phys_addr; |
8bcdd0f7 | 2906 | int ret; |
63340133 BW |
2907 | |
2908 | /* For Modern GENs the PTEs and register space are split in the BAR */ | |
34c998b4 | 2909 | phys_addr = pci_resource_start(pdev, 0) + pci_resource_len(pdev, 0) / 2; |
63340133 | 2910 | |
2a073f89 ID |
2911 | /* |
2912 | * On BXT writes larger than 64 bit to the GTT pagetable range will be | |
2913 | * dropped. For WC mappings in general we have 64 byte burst writes | |
2914 | * when the WC buffer is flushed, so we can't use it, but have to | |
2915 | * resort to an uncached mapping. The WC issue is easily caught by the | |
2916 | * readback check when writing GTT PTE entries. | |
2917 | */ | |
cc3f90f0 | 2918 | if (IS_GEN9_LP(dev_priv)) |
34c998b4 | 2919 | ggtt->gsm = ioremap_nocache(phys_addr, size); |
2a073f89 | 2920 | else |
34c998b4 | 2921 | ggtt->gsm = ioremap_wc(phys_addr, size); |
72e96d64 | 2922 | if (!ggtt->gsm) { |
34c998b4 | 2923 | DRM_ERROR("Failed to map the ggtt page table\n"); |
63340133 BW |
2924 | return -ENOMEM; |
2925 | } | |
2926 | ||
275a991c | 2927 | ret = setup_scratch_page(dev_priv, &ggtt->base.scratch_page, GFP_DMA32); |
8bcdd0f7 | 2928 | if (ret) { |
63340133 BW |
2929 | DRM_ERROR("Scratch setup failed\n"); |
2930 | /* iounmap will also get called at remove, but meh */ | |
72e96d64 | 2931 | iounmap(ggtt->gsm); |
8bcdd0f7 | 2932 | return ret; |
63340133 BW |
2933 | } |
2934 | ||
4ad2af1e | 2935 | return 0; |
63340133 BW |
2936 | } |
2937 | ||
fbe5d36e BW |
2938 | /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability |
2939 | * bits. When using advanced contexts each context stores its own PAT, but | |
2940 | * writing this data shouldn't be harmful even in those cases. */ | |
ee0ce478 | 2941 | static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv) |
fbe5d36e | 2942 | { |
fbe5d36e BW |
2943 | uint64_t pat; |
2944 | ||
2945 | pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC) | /* for normal objects, no eLLC */ | |
2946 | GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something pointing to ptes? */ | |
2947 | GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC) | /* for scanout with eLLC */ | |
2948 | GEN8_PPAT(3, GEN8_PPAT_UC) | /* Uncached objects, mostly for scanout */ | |
2949 | GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) | | |
2950 | GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) | | |
2951 | GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) | | |
2952 | GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3)); | |
2953 | ||
2d1fe073 | 2954 | if (!USES_PPGTT(dev_priv)) |
d6a8b72e RV |
2955 | /* Spec: "For GGTT, there is NO pat_sel[2:0] from the entry, |
2956 | * so RTL will always use the value corresponding to | |
2957 | * pat_sel = 000". | |
2958 | * So let's disable cache for GGTT to avoid screen corruptions. | |
2959 | * MOCS still can be used though. | |
2960 | * - System agent ggtt writes (i.e. cpu gtt mmaps) already work | |
2961 | * before this patch, i.e. the same uncached + snooping access | |
2962 | * like on gen6/7 seems to be in effect. | |
2963 | * - So this just fixes blitter/render access. Again it looks | |
2964 | * like it's not just uncached access, but uncached + snooping. | |
2965 | * So we can still hold onto all our assumptions wrt cpu | |
2966 | * clflushing on LLC machines. | |
2967 | */ | |
2968 | pat = GEN8_PPAT(0, GEN8_PPAT_UC); | |
2969 | ||
fbe5d36e BW |
2970 | /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b |
2971 | * write would work. */ | |
7e435ad2 VS |
2972 | I915_WRITE(GEN8_PRIVATE_PAT_LO, pat); |
2973 | I915_WRITE(GEN8_PRIVATE_PAT_HI, pat >> 32); | |
fbe5d36e BW |
2974 | } |
2975 | ||
ee0ce478 VS |
2976 | static void chv_setup_private_ppat(struct drm_i915_private *dev_priv) |
2977 | { | |
2978 | uint64_t pat; | |
2979 | ||
2980 | /* | |
2981 | * Map WB on BDW to snooped on CHV. | |
2982 | * | |
2983 | * Only the snoop bit has meaning for CHV, the rest is | |
2984 | * ignored. | |
2985 | * | |
cf3d262e VS |
2986 | * The hardware will never snoop for certain types of accesses: |
2987 | * - CPU GTT (GMADR->GGTT->no snoop->memory) | |
2988 | * - PPGTT page tables | |
2989 | * - some other special cycles | |
2990 | * | |
2991 | * As with BDW, we also need to consider the following for GT accesses: | |
2992 | * "For GGTT, there is NO pat_sel[2:0] from the entry, | |
2993 | * so RTL will always use the value corresponding to | |
2994 | * pat_sel = 000". | |
2995 | * Which means we must set the snoop bit in PAT entry 0 | |
2996 | * in order to keep the global status page working. | |
ee0ce478 VS |
2997 | */ |
2998 | pat = GEN8_PPAT(0, CHV_PPAT_SNOOP) | | |
2999 | GEN8_PPAT(1, 0) | | |
3000 | GEN8_PPAT(2, 0) | | |
3001 | GEN8_PPAT(3, 0) | | |
3002 | GEN8_PPAT(4, CHV_PPAT_SNOOP) | | |
3003 | GEN8_PPAT(5, CHV_PPAT_SNOOP) | | |
3004 | GEN8_PPAT(6, CHV_PPAT_SNOOP) | | |
3005 | GEN8_PPAT(7, CHV_PPAT_SNOOP); | |
3006 | ||
7e435ad2 VS |
3007 | I915_WRITE(GEN8_PRIVATE_PAT_LO, pat); |
3008 | I915_WRITE(GEN8_PRIVATE_PAT_HI, pat >> 32); | |
ee0ce478 VS |
3009 | } |
3010 | ||
34c998b4 CW |
3011 | static void gen6_gmch_remove(struct i915_address_space *vm) |
3012 | { | |
3013 | struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm); | |
3014 | ||
3015 | iounmap(ggtt->gsm); | |
49d73912 | 3016 | cleanup_scratch_page(vm->i915, &vm->scratch_page); |
34c998b4 CW |
3017 | } |
3018 | ||
d507d735 | 3019 | static int gen8_gmch_probe(struct i915_ggtt *ggtt) |
63340133 | 3020 | { |
49d73912 | 3021 | struct drm_i915_private *dev_priv = ggtt->base.i915; |
97d6d7ab | 3022 | struct pci_dev *pdev = dev_priv->drm.pdev; |
34c998b4 | 3023 | unsigned int size; |
63340133 | 3024 | u16 snb_gmch_ctl; |
63340133 BW |
3025 | |
3026 | /* TODO: We're not aware of mappable constraints on gen8 yet */ | |
97d6d7ab CW |
3027 | ggtt->mappable_base = pci_resource_start(pdev, 2); |
3028 | ggtt->mappable_end = pci_resource_len(pdev, 2); | |
63340133 | 3029 | |
97d6d7ab CW |
3030 | if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(39))) |
3031 | pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(39)); | |
63340133 | 3032 | |
97d6d7ab | 3033 | pci_read_config_word(pdev, SNB_GMCH_CTRL, &snb_gmch_ctl); |
63340133 | 3034 | |
97d6d7ab | 3035 | if (INTEL_GEN(dev_priv) >= 9) { |
d507d735 | 3036 | ggtt->stolen_size = gen9_get_stolen_size(snb_gmch_ctl); |
34c998b4 | 3037 | size = gen8_get_total_gtt_size(snb_gmch_ctl); |
97d6d7ab | 3038 | } else if (IS_CHERRYVIEW(dev_priv)) { |
d507d735 | 3039 | ggtt->stolen_size = chv_get_stolen_size(snb_gmch_ctl); |
34c998b4 | 3040 | size = chv_get_total_gtt_size(snb_gmch_ctl); |
d7f25f23 | 3041 | } else { |
d507d735 | 3042 | ggtt->stolen_size = gen8_get_stolen_size(snb_gmch_ctl); |
34c998b4 | 3043 | size = gen8_get_total_gtt_size(snb_gmch_ctl); |
d7f25f23 | 3044 | } |
63340133 | 3045 | |
34c998b4 | 3046 | ggtt->base.total = (size / sizeof(gen8_pte_t)) << PAGE_SHIFT; |
63340133 | 3047 | |
cc3f90f0 | 3048 | if (IS_CHERRYVIEW(dev_priv) || IS_GEN9_LP(dev_priv)) |
ee0ce478 VS |
3049 | chv_setup_private_ppat(dev_priv); |
3050 | else | |
3051 | bdw_setup_private_ppat(dev_priv); | |
fbe5d36e | 3052 | |
34c998b4 | 3053 | ggtt->base.cleanup = gen6_gmch_remove; |
d507d735 JL |
3054 | ggtt->base.bind_vma = ggtt_bind_vma; |
3055 | ggtt->base.unbind_vma = ggtt_unbind_vma; | |
d6473f56 | 3056 | ggtt->base.insert_page = gen8_ggtt_insert_page; |
f7770bfd | 3057 | ggtt->base.clear_range = nop_clear_range; |
48f112fe | 3058 | if (!USES_FULL_PPGTT(dev_priv) || intel_scanout_needs_vtd_wa(dev_priv)) |
f7770bfd CW |
3059 | ggtt->base.clear_range = gen8_ggtt_clear_range; |
3060 | ||
3061 | ggtt->base.insert_entries = gen8_ggtt_insert_entries; | |
3062 | if (IS_CHERRYVIEW(dev_priv)) | |
3063 | ggtt->base.insert_entries = gen8_ggtt_insert_entries__BKL; | |
3064 | ||
34c998b4 | 3065 | return ggtt_probe_common(ggtt, size); |
63340133 BW |
3066 | } |
3067 | ||
d507d735 | 3068 | static int gen6_gmch_probe(struct i915_ggtt *ggtt) |
e76e9aeb | 3069 | { |
49d73912 | 3070 | struct drm_i915_private *dev_priv = ggtt->base.i915; |
97d6d7ab | 3071 | struct pci_dev *pdev = dev_priv->drm.pdev; |
34c998b4 | 3072 | unsigned int size; |
e76e9aeb | 3073 | u16 snb_gmch_ctl; |
e76e9aeb | 3074 | |
97d6d7ab CW |
3075 | ggtt->mappable_base = pci_resource_start(pdev, 2); |
3076 | ggtt->mappable_end = pci_resource_len(pdev, 2); | |
41907ddc | 3077 | |
baa09f5f BW |
3078 | /* 64/512MB is the current min/max we actually know of, but this is just |
3079 | * a coarse sanity check. | |
e76e9aeb | 3080 | */ |
34c998b4 | 3081 | if (ggtt->mappable_end < (64<<20) || ggtt->mappable_end > (512<<20)) { |
d507d735 | 3082 | DRM_ERROR("Unknown GMADR size (%llx)\n", ggtt->mappable_end); |
baa09f5f | 3083 | return -ENXIO; |
e76e9aeb BW |
3084 | } |
3085 | ||
97d6d7ab CW |
3086 | if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(40))) |
3087 | pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(40)); | |
3088 | pci_read_config_word(pdev, SNB_GMCH_CTRL, &snb_gmch_ctl); | |
e76e9aeb | 3089 | |
d507d735 | 3090 | ggtt->stolen_size = gen6_get_stolen_size(snb_gmch_ctl); |
e76e9aeb | 3091 | |
34c998b4 CW |
3092 | size = gen6_get_total_gtt_size(snb_gmch_ctl); |
3093 | ggtt->base.total = (size / sizeof(gen6_pte_t)) << PAGE_SHIFT; | |
e76e9aeb | 3094 | |
d507d735 | 3095 | ggtt->base.clear_range = gen6_ggtt_clear_range; |
d6473f56 | 3096 | ggtt->base.insert_page = gen6_ggtt_insert_page; |
d507d735 JL |
3097 | ggtt->base.insert_entries = gen6_ggtt_insert_entries; |
3098 | ggtt->base.bind_vma = ggtt_bind_vma; | |
3099 | ggtt->base.unbind_vma = ggtt_unbind_vma; | |
34c998b4 CW |
3100 | ggtt->base.cleanup = gen6_gmch_remove; |
3101 | ||
3102 | if (HAS_EDRAM(dev_priv)) | |
3103 | ggtt->base.pte_encode = iris_pte_encode; | |
3104 | else if (IS_HASWELL(dev_priv)) | |
3105 | ggtt->base.pte_encode = hsw_pte_encode; | |
3106 | else if (IS_VALLEYVIEW(dev_priv)) | |
3107 | ggtt->base.pte_encode = byt_pte_encode; | |
3108 | else if (INTEL_GEN(dev_priv) >= 7) | |
3109 | ggtt->base.pte_encode = ivb_pte_encode; | |
3110 | else | |
3111 | ggtt->base.pte_encode = snb_pte_encode; | |
7faf1ab2 | 3112 | |
34c998b4 | 3113 | return ggtt_probe_common(ggtt, size); |
e76e9aeb BW |
3114 | } |
3115 | ||
34c998b4 | 3116 | static void i915_gmch_remove(struct i915_address_space *vm) |
e76e9aeb | 3117 | { |
34c998b4 | 3118 | intel_gmch_remove(); |
644ec02b | 3119 | } |
baa09f5f | 3120 | |
d507d735 | 3121 | static int i915_gmch_probe(struct i915_ggtt *ggtt) |
baa09f5f | 3122 | { |
49d73912 | 3123 | struct drm_i915_private *dev_priv = ggtt->base.i915; |
baa09f5f BW |
3124 | int ret; |
3125 | ||
91c8a326 | 3126 | ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->drm.pdev, NULL); |
baa09f5f BW |
3127 | if (!ret) { |
3128 | DRM_ERROR("failed to set up gmch\n"); | |
3129 | return -EIO; | |
3130 | } | |
3131 | ||
edd1f2fe CW |
3132 | intel_gtt_get(&ggtt->base.total, |
3133 | &ggtt->stolen_size, | |
3134 | &ggtt->mappable_base, | |
3135 | &ggtt->mappable_end); | |
baa09f5f | 3136 | |
97d6d7ab | 3137 | ggtt->do_idle_maps = needs_idle_maps(dev_priv); |
d6473f56 | 3138 | ggtt->base.insert_page = i915_ggtt_insert_page; |
d507d735 JL |
3139 | ggtt->base.insert_entries = i915_ggtt_insert_entries; |
3140 | ggtt->base.clear_range = i915_ggtt_clear_range; | |
3141 | ggtt->base.bind_vma = ggtt_bind_vma; | |
3142 | ggtt->base.unbind_vma = ggtt_unbind_vma; | |
34c998b4 | 3143 | ggtt->base.cleanup = i915_gmch_remove; |
baa09f5f | 3144 | |
d507d735 | 3145 | if (unlikely(ggtt->do_idle_maps)) |
c0a7f818 CW |
3146 | DRM_INFO("applying Ironlake quirks for intel_iommu\n"); |
3147 | ||
baa09f5f BW |
3148 | return 0; |
3149 | } | |
3150 | ||
d85489d3 | 3151 | /** |
0088e522 | 3152 | * i915_ggtt_probe_hw - Probe GGTT hardware location |
97d6d7ab | 3153 | * @dev_priv: i915 device |
d85489d3 | 3154 | */ |
97d6d7ab | 3155 | int i915_ggtt_probe_hw(struct drm_i915_private *dev_priv) |
baa09f5f | 3156 | { |
62106b4f | 3157 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
baa09f5f BW |
3158 | int ret; |
3159 | ||
49d73912 | 3160 | ggtt->base.i915 = dev_priv; |
c114f76a | 3161 | |
34c998b4 CW |
3162 | if (INTEL_GEN(dev_priv) <= 5) |
3163 | ret = i915_gmch_probe(ggtt); | |
3164 | else if (INTEL_GEN(dev_priv) < 8) | |
3165 | ret = gen6_gmch_probe(ggtt); | |
3166 | else | |
3167 | ret = gen8_gmch_probe(ggtt); | |
a54c0c27 | 3168 | if (ret) |
baa09f5f | 3169 | return ret; |
baa09f5f | 3170 | |
db9309a5 CW |
3171 | /* Trim the GGTT to fit the GuC mappable upper range (when enabled). |
3172 | * This is easier than doing range restriction on the fly, as we | |
3173 | * currently don't have any bits spare to pass in this upper | |
3174 | * restriction! | |
3175 | */ | |
3176 | if (HAS_GUC(dev_priv) && i915.enable_guc_loading) { | |
3177 | ggtt->base.total = min_t(u64, ggtt->base.total, GUC_GGTT_TOP); | |
3178 | ggtt->mappable_end = min(ggtt->mappable_end, ggtt->base.total); | |
3179 | } | |
3180 | ||
c890e2d5 CW |
3181 | if ((ggtt->base.total - 1) >> 32) { |
3182 | DRM_ERROR("We never expected a Global GTT with more than 32bits" | |
f6b9d5ca | 3183 | " of address space! Found %lldM!\n", |
c890e2d5 CW |
3184 | ggtt->base.total >> 20); |
3185 | ggtt->base.total = 1ULL << 32; | |
3186 | ggtt->mappable_end = min(ggtt->mappable_end, ggtt->base.total); | |
3187 | } | |
3188 | ||
f6b9d5ca CW |
3189 | if (ggtt->mappable_end > ggtt->base.total) { |
3190 | DRM_ERROR("mappable aperture extends past end of GGTT," | |
3191 | " aperture=%llx, total=%llx\n", | |
3192 | ggtt->mappable_end, ggtt->base.total); | |
3193 | ggtt->mappable_end = ggtt->base.total; | |
3194 | } | |
3195 | ||
baa09f5f | 3196 | /* GMADR is the PCI mmio aperture into the global GTT. */ |
c44ef60e | 3197 | DRM_INFO("Memory usable by graphics device = %lluM\n", |
62106b4f JL |
3198 | ggtt->base.total >> 20); |
3199 | DRM_DEBUG_DRIVER("GMADR size = %lldM\n", ggtt->mappable_end >> 20); | |
edd1f2fe | 3200 | DRM_DEBUG_DRIVER("GTT stolen size = %uM\n", ggtt->stolen_size >> 20); |
5db6c735 DV |
3201 | #ifdef CONFIG_INTEL_IOMMU |
3202 | if (intel_iommu_gfx_mapped) | |
3203 | DRM_INFO("VT-d active for gfx access\n"); | |
3204 | #endif | |
baa09f5f BW |
3205 | |
3206 | return 0; | |
0088e522 CW |
3207 | } |
3208 | ||
3209 | /** | |
3210 | * i915_ggtt_init_hw - Initialize GGTT hardware | |
97d6d7ab | 3211 | * @dev_priv: i915 device |
0088e522 | 3212 | */ |
97d6d7ab | 3213 | int i915_ggtt_init_hw(struct drm_i915_private *dev_priv) |
0088e522 | 3214 | { |
0088e522 CW |
3215 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
3216 | int ret; | |
3217 | ||
f6b9d5ca CW |
3218 | INIT_LIST_HEAD(&dev_priv->vm_list); |
3219 | ||
3220 | /* Subtract the guard page before address space initialization to | |
3221 | * shrink the range used by drm_mm. | |
3222 | */ | |
80b204bc | 3223 | mutex_lock(&dev_priv->drm.struct_mutex); |
f6b9d5ca | 3224 | ggtt->base.total -= PAGE_SIZE; |
80b204bc | 3225 | i915_address_space_init(&ggtt->base, dev_priv, "[global]"); |
f6b9d5ca CW |
3226 | ggtt->base.total += PAGE_SIZE; |
3227 | if (!HAS_LLC(dev_priv)) | |
3228 | ggtt->base.mm.color_adjust = i915_gtt_color_adjust; | |
80b204bc | 3229 | mutex_unlock(&dev_priv->drm.struct_mutex); |
f6b9d5ca | 3230 | |
f7bbe788 CW |
3231 | if (!io_mapping_init_wc(&dev_priv->ggtt.mappable, |
3232 | dev_priv->ggtt.mappable_base, | |
3233 | dev_priv->ggtt.mappable_end)) { | |
f6b9d5ca CW |
3234 | ret = -EIO; |
3235 | goto out_gtt_cleanup; | |
3236 | } | |
3237 | ||
3238 | ggtt->mtrr = arch_phys_wc_add(ggtt->mappable_base, ggtt->mappable_end); | |
3239 | ||
0088e522 CW |
3240 | /* |
3241 | * Initialise stolen early so that we may reserve preallocated | |
3242 | * objects for the BIOS to KMS transition. | |
3243 | */ | |
7ace3d30 | 3244 | ret = i915_gem_init_stolen(dev_priv); |
0088e522 CW |
3245 | if (ret) |
3246 | goto out_gtt_cleanup; | |
3247 | ||
3248 | return 0; | |
a4eba47b ID |
3249 | |
3250 | out_gtt_cleanup: | |
72e96d64 | 3251 | ggtt->base.cleanup(&ggtt->base); |
a4eba47b | 3252 | return ret; |
baa09f5f | 3253 | } |
6f65e29a | 3254 | |
97d6d7ab | 3255 | int i915_ggtt_enable_hw(struct drm_i915_private *dev_priv) |
ac840ae5 | 3256 | { |
97d6d7ab | 3257 | if (INTEL_GEN(dev_priv) < 6 && !intel_enable_gtt()) |
ac840ae5 VS |
3258 | return -EIO; |
3259 | ||
3260 | return 0; | |
3261 | } | |
3262 | ||
275a991c | 3263 | void i915_gem_restore_gtt_mappings(struct drm_i915_private *dev_priv) |
fa42331b | 3264 | { |
72e96d64 | 3265 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
fbb30a5c | 3266 | struct drm_i915_gem_object *obj, *on; |
fa42331b | 3267 | |
dc97997a | 3268 | i915_check_and_clear_faults(dev_priv); |
fa42331b DV |
3269 | |
3270 | /* First fill our portion of the GTT with scratch pages */ | |
4fb84d99 | 3271 | ggtt->base.clear_range(&ggtt->base, ggtt->base.start, ggtt->base.total); |
fa42331b | 3272 | |
fbb30a5c CW |
3273 | ggtt->base.closed = true; /* skip rewriting PTE on VMA unbind */ |
3274 | ||
3275 | /* clflush objects bound into the GGTT and rebind them. */ | |
3276 | list_for_each_entry_safe(obj, on, | |
56cea323 | 3277 | &dev_priv->mm.bound_list, global_link) { |
fbb30a5c CW |
3278 | bool ggtt_bound = false; |
3279 | struct i915_vma *vma; | |
3280 | ||
1c7f4bca | 3281 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
72e96d64 | 3282 | if (vma->vm != &ggtt->base) |
2c3d9984 | 3283 | continue; |
fa42331b | 3284 | |
fbb30a5c CW |
3285 | if (!i915_vma_unbind(vma)) |
3286 | continue; | |
3287 | ||
2c3d9984 TU |
3288 | WARN_ON(i915_vma_bind(vma, obj->cache_level, |
3289 | PIN_UPDATE)); | |
fbb30a5c | 3290 | ggtt_bound = true; |
2c3d9984 TU |
3291 | } |
3292 | ||
fbb30a5c | 3293 | if (ggtt_bound) |
975f7ff4 | 3294 | WARN_ON(i915_gem_object_set_to_gtt_domain(obj, false)); |
2c3d9984 | 3295 | } |
fa42331b | 3296 | |
fbb30a5c CW |
3297 | ggtt->base.closed = false; |
3298 | ||
275a991c | 3299 | if (INTEL_GEN(dev_priv) >= 8) { |
cc3f90f0 | 3300 | if (IS_CHERRYVIEW(dev_priv) || IS_GEN9_LP(dev_priv)) |
fa42331b DV |
3301 | chv_setup_private_ppat(dev_priv); |
3302 | else | |
3303 | bdw_setup_private_ppat(dev_priv); | |
3304 | ||
3305 | return; | |
3306 | } | |
3307 | ||
275a991c | 3308 | if (USES_PPGTT(dev_priv)) { |
72e96d64 JL |
3309 | struct i915_address_space *vm; |
3310 | ||
fa42331b DV |
3311 | list_for_each_entry(vm, &dev_priv->vm_list, global_link) { |
3312 | /* TODO: Perhaps it shouldn't be gen6 specific */ | |
3313 | ||
e5716f55 | 3314 | struct i915_hw_ppgtt *ppgtt; |
fa42331b | 3315 | |
2bfa996e | 3316 | if (i915_is_ggtt(vm)) |
fa42331b | 3317 | ppgtt = dev_priv->mm.aliasing_ppgtt; |
e5716f55 JL |
3318 | else |
3319 | ppgtt = i915_vm_to_ppgtt(vm); | |
fa42331b DV |
3320 | |
3321 | gen6_write_page_range(dev_priv, &ppgtt->pd, | |
3322 | 0, ppgtt->base.total); | |
3323 | } | |
3324 | } | |
3325 | ||
3326 | i915_ggtt_flush(dev_priv); | |
3327 | } | |
3328 | ||
6f65e29a | 3329 | struct i915_vma * |
058d88c4 CW |
3330 | i915_gem_obj_to_vma(struct drm_i915_gem_object *obj, |
3331 | struct i915_address_space *vm, | |
3332 | const struct i915_ggtt_view *view) | |
ec7adb6e | 3333 | { |
db6c2b41 | 3334 | struct rb_node *rb; |
ec7adb6e | 3335 | |
db6c2b41 CW |
3336 | rb = obj->vma_tree.rb_node; |
3337 | while (rb) { | |
3338 | struct i915_vma *vma = rb_entry(rb, struct i915_vma, obj_node); | |
3339 | long cmp; | |
3340 | ||
b42fe9ca | 3341 | cmp = i915_vma_compare(vma, vm, view); |
db6c2b41 | 3342 | if (cmp == 0) |
058d88c4 | 3343 | return vma; |
ec7adb6e | 3344 | |
db6c2b41 CW |
3345 | if (cmp < 0) |
3346 | rb = rb->rb_right; | |
3347 | else | |
3348 | rb = rb->rb_left; | |
3349 | } | |
3350 | ||
058d88c4 | 3351 | return NULL; |
ec7adb6e JL |
3352 | } |
3353 | ||
3354 | struct i915_vma * | |
058d88c4 CW |
3355 | i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj, |
3356 | struct i915_address_space *vm, | |
3357 | const struct i915_ggtt_view *view) | |
6f65e29a | 3358 | { |
058d88c4 | 3359 | struct i915_vma *vma; |
ec7adb6e | 3360 | |
4c7d62c6 | 3361 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
058d88c4 | 3362 | GEM_BUG_ON(view && !i915_is_ggtt(vm)); |
de895082 | 3363 | |
058d88c4 | 3364 | vma = i915_gem_obj_to_vma(obj, vm, view); |
db6c2b41 | 3365 | if (!vma) { |
b42fe9ca | 3366 | vma = i915_vma_create(obj, vm, view); |
db6c2b41 CW |
3367 | GEM_BUG_ON(vma != i915_gem_obj_to_vma(obj, vm, view)); |
3368 | } | |
6f65e29a | 3369 | |
3272db53 | 3370 | GEM_BUG_ON(i915_vma_is_closed(vma)); |
6f65e29a BW |
3371 | return vma; |
3372 | } | |
fe14d5f4 | 3373 | |
804beb4b | 3374 | static struct scatterlist * |
2d7f3bdb | 3375 | rotate_pages(const dma_addr_t *in, unsigned int offset, |
804beb4b | 3376 | unsigned int width, unsigned int height, |
87130255 | 3377 | unsigned int stride, |
804beb4b | 3378 | struct sg_table *st, struct scatterlist *sg) |
50470bb0 TU |
3379 | { |
3380 | unsigned int column, row; | |
3381 | unsigned int src_idx; | |
50470bb0 | 3382 | |
50470bb0 | 3383 | for (column = 0; column < width; column++) { |
87130255 | 3384 | src_idx = stride * (height - 1) + column; |
50470bb0 TU |
3385 | for (row = 0; row < height; row++) { |
3386 | st->nents++; | |
3387 | /* We don't need the pages, but need to initialize | |
3388 | * the entries so the sg list can be happily traversed. | |
3389 | * The only thing we need are DMA addresses. | |
3390 | */ | |
3391 | sg_set_page(sg, NULL, PAGE_SIZE, 0); | |
804beb4b | 3392 | sg_dma_address(sg) = in[offset + src_idx]; |
50470bb0 TU |
3393 | sg_dma_len(sg) = PAGE_SIZE; |
3394 | sg = sg_next(sg); | |
87130255 | 3395 | src_idx -= stride; |
50470bb0 TU |
3396 | } |
3397 | } | |
804beb4b TU |
3398 | |
3399 | return sg; | |
50470bb0 TU |
3400 | } |
3401 | ||
3402 | static struct sg_table * | |
6687c906 | 3403 | intel_rotate_fb_obj_pages(const struct intel_rotation_info *rot_info, |
50470bb0 TU |
3404 | struct drm_i915_gem_object *obj) |
3405 | { | |
85d1225e | 3406 | const size_t n_pages = obj->base.size / PAGE_SIZE; |
6687c906 | 3407 | unsigned int size = intel_rotation_info_size(rot_info); |
85d1225e DG |
3408 | struct sgt_iter sgt_iter; |
3409 | dma_addr_t dma_addr; | |
50470bb0 TU |
3410 | unsigned long i; |
3411 | dma_addr_t *page_addr_list; | |
3412 | struct sg_table *st; | |
89e3e142 | 3413 | struct scatterlist *sg; |
1d00dad5 | 3414 | int ret = -ENOMEM; |
50470bb0 | 3415 | |
50470bb0 | 3416 | /* Allocate a temporary list of source pages for random access. */ |
85d1225e | 3417 | page_addr_list = drm_malloc_gfp(n_pages, |
f2a85e19 CW |
3418 | sizeof(dma_addr_t), |
3419 | GFP_TEMPORARY); | |
50470bb0 TU |
3420 | if (!page_addr_list) |
3421 | return ERR_PTR(ret); | |
3422 | ||
3423 | /* Allocate target SG list. */ | |
3424 | st = kmalloc(sizeof(*st), GFP_KERNEL); | |
3425 | if (!st) | |
3426 | goto err_st_alloc; | |
3427 | ||
6687c906 | 3428 | ret = sg_alloc_table(st, size, GFP_KERNEL); |
50470bb0 TU |
3429 | if (ret) |
3430 | goto err_sg_alloc; | |
3431 | ||
3432 | /* Populate source page list from the object. */ | |
3433 | i = 0; | |
a4f5ea64 | 3434 | for_each_sgt_dma(dma_addr, sgt_iter, obj->mm.pages) |
85d1225e | 3435 | page_addr_list[i++] = dma_addr; |
50470bb0 | 3436 | |
85d1225e | 3437 | GEM_BUG_ON(i != n_pages); |
11f20322 VS |
3438 | st->nents = 0; |
3439 | sg = st->sgl; | |
3440 | ||
6687c906 VS |
3441 | for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++) { |
3442 | sg = rotate_pages(page_addr_list, rot_info->plane[i].offset, | |
3443 | rot_info->plane[i].width, rot_info->plane[i].height, | |
3444 | rot_info->plane[i].stride, st, sg); | |
89e3e142 TU |
3445 | } |
3446 | ||
6687c906 VS |
3447 | DRM_DEBUG_KMS("Created rotated page mapping for object size %zu (%ux%u tiles, %u pages)\n", |
3448 | obj->base.size, rot_info->plane[0].width, rot_info->plane[0].height, size); | |
50470bb0 TU |
3449 | |
3450 | drm_free_large(page_addr_list); | |
3451 | ||
3452 | return st; | |
3453 | ||
3454 | err_sg_alloc: | |
3455 | kfree(st); | |
3456 | err_st_alloc: | |
3457 | drm_free_large(page_addr_list); | |
3458 | ||
6687c906 VS |
3459 | DRM_DEBUG_KMS("Failed to create rotated mapping for object size %zu! (%ux%u tiles, %u pages)\n", |
3460 | obj->base.size, rot_info->plane[0].width, rot_info->plane[0].height, size); | |
3461 | ||
50470bb0 TU |
3462 | return ERR_PTR(ret); |
3463 | } | |
ec7adb6e | 3464 | |
8bd7ef16 JL |
3465 | static struct sg_table * |
3466 | intel_partial_pages(const struct i915_ggtt_view *view, | |
3467 | struct drm_i915_gem_object *obj) | |
3468 | { | |
3469 | struct sg_table *st; | |
d2a84a76 CW |
3470 | struct scatterlist *sg, *iter; |
3471 | unsigned int count = view->params.partial.size; | |
3472 | unsigned int offset; | |
8bd7ef16 JL |
3473 | int ret = -ENOMEM; |
3474 | ||
3475 | st = kmalloc(sizeof(*st), GFP_KERNEL); | |
3476 | if (!st) | |
3477 | goto err_st_alloc; | |
3478 | ||
d2a84a76 | 3479 | ret = sg_alloc_table(st, count, GFP_KERNEL); |
8bd7ef16 JL |
3480 | if (ret) |
3481 | goto err_sg_alloc; | |
3482 | ||
d2a84a76 CW |
3483 | iter = i915_gem_object_get_sg(obj, |
3484 | view->params.partial.offset, | |
3485 | &offset); | |
3486 | GEM_BUG_ON(!iter); | |
3487 | ||
8bd7ef16 JL |
3488 | sg = st->sgl; |
3489 | st->nents = 0; | |
d2a84a76 CW |
3490 | do { |
3491 | unsigned int len; | |
8bd7ef16 | 3492 | |
d2a84a76 CW |
3493 | len = min(iter->length - (offset << PAGE_SHIFT), |
3494 | count << PAGE_SHIFT); | |
3495 | sg_set_page(sg, NULL, len, 0); | |
3496 | sg_dma_address(sg) = | |
3497 | sg_dma_address(iter) + (offset << PAGE_SHIFT); | |
3498 | sg_dma_len(sg) = len; | |
8bd7ef16 | 3499 | |
8bd7ef16 | 3500 | st->nents++; |
d2a84a76 CW |
3501 | count -= len >> PAGE_SHIFT; |
3502 | if (count == 0) { | |
3503 | sg_mark_end(sg); | |
3504 | return st; | |
3505 | } | |
8bd7ef16 | 3506 | |
d2a84a76 CW |
3507 | sg = __sg_next(sg); |
3508 | iter = __sg_next(iter); | |
3509 | offset = 0; | |
3510 | } while (1); | |
8bd7ef16 JL |
3511 | |
3512 | err_sg_alloc: | |
3513 | kfree(st); | |
3514 | err_st_alloc: | |
3515 | return ERR_PTR(ret); | |
3516 | } | |
3517 | ||
70b9f6f8 | 3518 | static int |
50470bb0 | 3519 | i915_get_ggtt_vma_pages(struct i915_vma *vma) |
fe14d5f4 | 3520 | { |
50470bb0 TU |
3521 | int ret = 0; |
3522 | ||
2c3a3f44 CW |
3523 | /* The vma->pages are only valid within the lifespan of the borrowed |
3524 | * obj->mm.pages. When the obj->mm.pages sg_table is regenerated, so | |
3525 | * must be the vma->pages. A simple rule is that vma->pages must only | |
3526 | * be accessed when the obj->mm.pages are pinned. | |
3527 | */ | |
3528 | GEM_BUG_ON(!i915_gem_object_has_pinned_pages(vma->obj)); | |
3529 | ||
247177dd | 3530 | if (vma->pages) |
fe14d5f4 TU |
3531 | return 0; |
3532 | ||
3533 | if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) | |
a4f5ea64 | 3534 | vma->pages = vma->obj->mm.pages; |
50470bb0 | 3535 | else if (vma->ggtt_view.type == I915_GGTT_VIEW_ROTATED) |
247177dd | 3536 | vma->pages = |
11d23e6f | 3537 | intel_rotate_fb_obj_pages(&vma->ggtt_view.params.rotated, vma->obj); |
8bd7ef16 | 3538 | else if (vma->ggtt_view.type == I915_GGTT_VIEW_PARTIAL) |
247177dd | 3539 | vma->pages = intel_partial_pages(&vma->ggtt_view, vma->obj); |
fe14d5f4 TU |
3540 | else |
3541 | WARN_ONCE(1, "GGTT view %u not implemented!\n", | |
3542 | vma->ggtt_view.type); | |
3543 | ||
247177dd | 3544 | if (!vma->pages) { |
ec7adb6e | 3545 | DRM_ERROR("Failed to get pages for GGTT view type %u!\n", |
fe14d5f4 | 3546 | vma->ggtt_view.type); |
50470bb0 | 3547 | ret = -EINVAL; |
247177dd CW |
3548 | } else if (IS_ERR(vma->pages)) { |
3549 | ret = PTR_ERR(vma->pages); | |
3550 | vma->pages = NULL; | |
50470bb0 TU |
3551 | DRM_ERROR("Failed to get pages for VMA view type %u (%d)!\n", |
3552 | vma->ggtt_view.type, ret); | |
fe14d5f4 TU |
3553 | } |
3554 | ||
50470bb0 | 3555 | return ret; |
fe14d5f4 TU |
3556 | } |
3557 | ||
625d988a CW |
3558 | /** |
3559 | * i915_gem_gtt_reserve - reserve a node in an address_space (GTT) | |
3560 | * @vm - the &struct i915_address_space | |
3561 | * @node - the &struct drm_mm_node (typically i915_vma.mode) | |
3562 | * @size - how much space to allocate inside the GTT, | |
3563 | * must be #I915_GTT_PAGE_SIZE aligned | |
3564 | * @offset - where to insert inside the GTT, | |
3565 | * must be #I915_GTT_MIN_ALIGNMENT aligned, and the node | |
3566 | * (@offset + @size) must fit within the address space | |
3567 | * @color - color to apply to node, if this node is not from a VMA, | |
3568 | * color must be #I915_COLOR_UNEVICTABLE | |
3569 | * @flags - control search and eviction behaviour | |
3570 | * | |
3571 | * i915_gem_gtt_reserve() tries to insert the @node at the exact @offset inside | |
3572 | * the address space (using @size and @color). If the @node does not fit, it | |
3573 | * tries to evict any overlapping nodes from the GTT, including any | |
3574 | * neighbouring nodes if the colors do not match (to ensure guard pages between | |
3575 | * differing domains). See i915_gem_evict_for_node() for the gory details | |
3576 | * on the eviction algorithm. #PIN_NONBLOCK may used to prevent waiting on | |
3577 | * evicting active overlapping objects, and any overlapping node that is pinned | |
3578 | * or marked as unevictable will also result in failure. | |
3579 | * | |
3580 | * Returns: 0 on success, -ENOSPC if no suitable hole is found, -EINTR if | |
3581 | * asked to wait for eviction and interrupted. | |
3582 | */ | |
3583 | int i915_gem_gtt_reserve(struct i915_address_space *vm, | |
3584 | struct drm_mm_node *node, | |
3585 | u64 size, u64 offset, unsigned long color, | |
3586 | unsigned int flags) | |
3587 | { | |
3588 | int err; | |
3589 | ||
3590 | GEM_BUG_ON(!size); | |
3591 | GEM_BUG_ON(!IS_ALIGNED(size, I915_GTT_PAGE_SIZE)); | |
3592 | GEM_BUG_ON(!IS_ALIGNED(offset, I915_GTT_MIN_ALIGNMENT)); | |
3593 | GEM_BUG_ON(range_overflows(offset, size, vm->total)); | |
3594 | ||
3595 | node->size = size; | |
3596 | node->start = offset; | |
3597 | node->color = color; | |
3598 | ||
3599 | err = drm_mm_reserve_node(&vm->mm, node); | |
3600 | if (err != -ENOSPC) | |
3601 | return err; | |
3602 | ||
3603 | err = i915_gem_evict_for_node(vm, node, flags); | |
3604 | if (err == 0) | |
3605 | err = drm_mm_reserve_node(&vm->mm, node); | |
3606 | ||
3607 | return err; | |
3608 | } | |
3609 | ||
606fec95 CW |
3610 | static u64 random_offset(u64 start, u64 end, u64 len, u64 align) |
3611 | { | |
3612 | u64 range, addr; | |
3613 | ||
3614 | GEM_BUG_ON(range_overflows(start, len, end)); | |
3615 | GEM_BUG_ON(round_up(start, align) > round_down(end - len, align)); | |
3616 | ||
3617 | range = round_down(end - len, align) - round_up(start, align); | |
3618 | if (range) { | |
3619 | if (sizeof(unsigned long) == sizeof(u64)) { | |
3620 | addr = get_random_long(); | |
3621 | } else { | |
3622 | addr = get_random_int(); | |
3623 | if (range > U32_MAX) { | |
3624 | addr <<= 32; | |
3625 | addr |= get_random_int(); | |
3626 | } | |
3627 | } | |
3628 | div64_u64_rem(addr, range, &addr); | |
3629 | start += addr; | |
3630 | } | |
3631 | ||
3632 | return round_up(start, align); | |
3633 | } | |
3634 | ||
e007b19d CW |
3635 | /** |
3636 | * i915_gem_gtt_insert - insert a node into an address_space (GTT) | |
3637 | * @vm - the &struct i915_address_space | |
3638 | * @node - the &struct drm_mm_node (typically i915_vma.node) | |
3639 | * @size - how much space to allocate inside the GTT, | |
3640 | * must be #I915_GTT_PAGE_SIZE aligned | |
3641 | * @alignment - required alignment of starting offset, may be 0 but | |
3642 | * if specified, this must be a power-of-two and at least | |
3643 | * #I915_GTT_MIN_ALIGNMENT | |
3644 | * @color - color to apply to node | |
3645 | * @start - start of any range restriction inside GTT (0 for all), | |
3646 | * must be #I915_GTT_PAGE_SIZE aligned | |
3647 | * @end - end of any range restriction inside GTT (U64_MAX for all), | |
3648 | * must be #I915_GTT_PAGE_SIZE aligned if not U64_MAX | |
3649 | * @flags - control search and eviction behaviour | |
3650 | * | |
3651 | * i915_gem_gtt_insert() first searches for an available hole into which | |
3652 | * is can insert the node. The hole address is aligned to @alignment and | |
3653 | * its @size must then fit entirely within the [@start, @end] bounds. The | |
3654 | * nodes on either side of the hole must match @color, or else a guard page | |
3655 | * will be inserted between the two nodes (or the node evicted). If no | |
606fec95 CW |
3656 | * suitable hole is found, first a victim is randomly selected and tested |
3657 | * for eviction, otherwise then the LRU list of objects within the GTT | |
e007b19d CW |
3658 | * is scanned to find the first set of replacement nodes to create the hole. |
3659 | * Those old overlapping nodes are evicted from the GTT (and so must be | |
3660 | * rebound before any future use). Any node that is currently pinned cannot | |
3661 | * be evicted (see i915_vma_pin()). Similar if the node's VMA is currently | |
3662 | * active and #PIN_NONBLOCK is specified, that node is also skipped when | |
3663 | * searching for an eviction candidate. See i915_gem_evict_something() for | |
3664 | * the gory details on the eviction algorithm. | |
3665 | * | |
3666 | * Returns: 0 on success, -ENOSPC if no suitable hole is found, -EINTR if | |
3667 | * asked to wait for eviction and interrupted. | |
3668 | */ | |
3669 | int i915_gem_gtt_insert(struct i915_address_space *vm, | |
3670 | struct drm_mm_node *node, | |
3671 | u64 size, u64 alignment, unsigned long color, | |
3672 | u64 start, u64 end, unsigned int flags) | |
3673 | { | |
3674 | u32 search_flag, alloc_flag; | |
606fec95 | 3675 | u64 offset; |
e007b19d CW |
3676 | int err; |
3677 | ||
3678 | lockdep_assert_held(&vm->i915->drm.struct_mutex); | |
3679 | GEM_BUG_ON(!size); | |
3680 | GEM_BUG_ON(!IS_ALIGNED(size, I915_GTT_PAGE_SIZE)); | |
3681 | GEM_BUG_ON(alignment && !is_power_of_2(alignment)); | |
3682 | GEM_BUG_ON(alignment && !IS_ALIGNED(alignment, I915_GTT_MIN_ALIGNMENT)); | |
3683 | GEM_BUG_ON(start >= end); | |
3684 | GEM_BUG_ON(start > 0 && !IS_ALIGNED(start, I915_GTT_PAGE_SIZE)); | |
3685 | GEM_BUG_ON(end < U64_MAX && !IS_ALIGNED(end, I915_GTT_PAGE_SIZE)); | |
3686 | ||
3687 | if (unlikely(range_overflows(start, size, end))) | |
3688 | return -ENOSPC; | |
3689 | ||
3690 | if (unlikely(round_up(start, alignment) > round_down(end - size, alignment))) | |
3691 | return -ENOSPC; | |
3692 | ||
3693 | if (flags & PIN_HIGH) { | |
3694 | search_flag = DRM_MM_SEARCH_BELOW; | |
3695 | alloc_flag = DRM_MM_CREATE_TOP; | |
3696 | } else { | |
3697 | search_flag = DRM_MM_SEARCH_DEFAULT; | |
3698 | alloc_flag = DRM_MM_CREATE_DEFAULT; | |
3699 | } | |
3700 | ||
3701 | /* We only allocate in PAGE_SIZE/GTT_PAGE_SIZE (4096) chunks, | |
3702 | * so we know that we always have a minimum alignment of 4096. | |
3703 | * The drm_mm range manager is optimised to return results | |
3704 | * with zero alignment, so where possible use the optimal | |
3705 | * path. | |
3706 | */ | |
3707 | BUILD_BUG_ON(I915_GTT_MIN_ALIGNMENT > I915_GTT_PAGE_SIZE); | |
3708 | if (alignment <= I915_GTT_MIN_ALIGNMENT) | |
3709 | alignment = 0; | |
3710 | ||
3711 | err = drm_mm_insert_node_in_range_generic(&vm->mm, node, | |
3712 | size, alignment, color, | |
3713 | start, end, | |
3714 | search_flag, alloc_flag); | |
3715 | if (err != -ENOSPC) | |
3716 | return err; | |
3717 | ||
606fec95 CW |
3718 | /* No free space, pick a slot at random. |
3719 | * | |
3720 | * There is a pathological case here using a GTT shared between | |
3721 | * mmap and GPU (i.e. ggtt/aliasing_ppgtt but not full-ppgtt): | |
3722 | * | |
3723 | * |<-- 256 MiB aperture -->||<-- 1792 MiB unmappable -->| | |
3724 | * (64k objects) (448k objects) | |
3725 | * | |
3726 | * Now imagine that the eviction LRU is ordered top-down (just because | |
3727 | * pathology meets real life), and that we need to evict an object to | |
3728 | * make room inside the aperture. The eviction scan then has to walk | |
3729 | * the 448k list before it finds one within range. And now imagine that | |
3730 | * it has to search for a new hole between every byte inside the memcpy, | |
3731 | * for several simultaneous clients. | |
3732 | * | |
3733 | * On a full-ppgtt system, if we have run out of available space, there | |
3734 | * will be lots and lots of objects in the eviction list! Again, | |
3735 | * searching that LRU list may be slow if we are also applying any | |
3736 | * range restrictions (e.g. restriction to low 4GiB) and so, for | |
3737 | * simplicity and similarilty between different GTT, try the single | |
3738 | * random replacement first. | |
3739 | */ | |
3740 | offset = random_offset(start, end, | |
3741 | size, alignment ?: I915_GTT_MIN_ALIGNMENT); | |
3742 | err = i915_gem_gtt_reserve(vm, node, size, offset, color, flags); | |
3743 | if (err != -ENOSPC) | |
3744 | return err; | |
3745 | ||
3746 | /* Randomly selected placement is pinned, do a search */ | |
e007b19d CW |
3747 | err = i915_gem_evict_something(vm, size, alignment, color, |
3748 | start, end, flags); | |
3749 | if (err) | |
3750 | return err; | |
3751 | ||
3752 | search_flag = DRM_MM_SEARCH_DEFAULT; | |
3753 | return drm_mm_insert_node_in_range_generic(&vm->mm, node, | |
3754 | size, alignment, color, | |
3755 | start, end, | |
3756 | search_flag, alloc_flag); | |
3757 | } |