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76aaf220 DV |
1 | /* |
2 | * Copyright © 2010 Daniel Vetter | |
c4ac524c | 3 | * Copyright © 2011-2014 Intel Corporation |
76aaf220 DV |
4 | * |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
22 | * IN THE SOFTWARE. | |
23 | * | |
24 | */ | |
25 | ||
0e46ce2e | 26 | #include <linux/seq_file.h> |
5bab6f60 | 27 | #include <linux/stop_machine.h> |
760285e7 DH |
28 | #include <drm/drmP.h> |
29 | #include <drm/i915_drm.h> | |
76aaf220 | 30 | #include "i915_drv.h" |
5dda8fa3 | 31 | #include "i915_vgpu.h" |
76aaf220 DV |
32 | #include "i915_trace.h" |
33 | #include "intel_drv.h" | |
d07f0e59 | 34 | #include "intel_frontbuffer.h" |
76aaf220 | 35 | |
bb8f9cff CW |
36 | #define I915_GFP_DMA (GFP_KERNEL | __GFP_HIGHMEM) |
37 | ||
45f8f69a TU |
38 | /** |
39 | * DOC: Global GTT views | |
40 | * | |
41 | * Background and previous state | |
42 | * | |
43 | * Historically objects could exists (be bound) in global GTT space only as | |
44 | * singular instances with a view representing all of the object's backing pages | |
45 | * in a linear fashion. This view will be called a normal view. | |
46 | * | |
47 | * To support multiple views of the same object, where the number of mapped | |
48 | * pages is not equal to the backing store, or where the layout of the pages | |
49 | * is not linear, concept of a GGTT view was added. | |
50 | * | |
51 | * One example of an alternative view is a stereo display driven by a single | |
52 | * image. In this case we would have a framebuffer looking like this | |
53 | * (2x2 pages): | |
54 | * | |
55 | * 12 | |
56 | * 34 | |
57 | * | |
58 | * Above would represent a normal GGTT view as normally mapped for GPU or CPU | |
59 | * rendering. In contrast, fed to the display engine would be an alternative | |
60 | * view which could look something like this: | |
61 | * | |
62 | * 1212 | |
63 | * 3434 | |
64 | * | |
65 | * In this example both the size and layout of pages in the alternative view is | |
66 | * different from the normal view. | |
67 | * | |
68 | * Implementation and usage | |
69 | * | |
70 | * GGTT views are implemented using VMAs and are distinguished via enum | |
71 | * i915_ggtt_view_type and struct i915_ggtt_view. | |
72 | * | |
73 | * A new flavour of core GEM functions which work with GGTT bound objects were | |
ec7adb6e JL |
74 | * added with the _ggtt_ infix, and sometimes with _view postfix to avoid |
75 | * renaming in large amounts of code. They take the struct i915_ggtt_view | |
76 | * parameter encapsulating all metadata required to implement a view. | |
45f8f69a TU |
77 | * |
78 | * As a helper for callers which are only interested in the normal view, | |
79 | * globally const i915_ggtt_view_normal singleton instance exists. All old core | |
80 | * GEM API functions, the ones not taking the view parameter, are operating on, | |
81 | * or with the normal GGTT view. | |
82 | * | |
83 | * Code wanting to add or use a new GGTT view needs to: | |
84 | * | |
85 | * 1. Add a new enum with a suitable name. | |
86 | * 2. Extend the metadata in the i915_ggtt_view structure if required. | |
87 | * 3. Add support to i915_get_vma_pages(). | |
88 | * | |
89 | * New views are required to build a scatter-gather table from within the | |
90 | * i915_get_vma_pages function. This table is stored in the vma.ggtt_view and | |
91 | * exists for the lifetime of an VMA. | |
92 | * | |
93 | * Core API is designed to have copy semantics which means that passed in | |
94 | * struct i915_ggtt_view does not need to be persistent (left around after | |
95 | * calling the core API functions). | |
96 | * | |
97 | */ | |
98 | ||
ce7fda2e CW |
99 | static inline struct i915_ggtt * |
100 | i915_vm_to_ggtt(struct i915_address_space *vm) | |
101 | { | |
102 | GEM_BUG_ON(!i915_is_ggtt(vm)); | |
103 | return container_of(vm, struct i915_ggtt, base); | |
104 | } | |
105 | ||
70b9f6f8 DV |
106 | static int |
107 | i915_get_ggtt_vma_pages(struct i915_vma *vma); | |
108 | ||
b5e16987 VS |
109 | const struct i915_ggtt_view i915_ggtt_view_normal = { |
110 | .type = I915_GGTT_VIEW_NORMAL, | |
111 | }; | |
9abc4648 | 112 | const struct i915_ggtt_view i915_ggtt_view_rotated = { |
b5e16987 | 113 | .type = I915_GGTT_VIEW_ROTATED, |
9abc4648 | 114 | }; |
fe14d5f4 | 115 | |
c033666a CW |
116 | int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv, |
117 | int enable_ppgtt) | |
cfa7c862 | 118 | { |
1893a71b CW |
119 | bool has_aliasing_ppgtt; |
120 | bool has_full_ppgtt; | |
1f9a99e0 | 121 | bool has_full_48bit_ppgtt; |
1893a71b | 122 | |
c033666a CW |
123 | has_aliasing_ppgtt = INTEL_GEN(dev_priv) >= 6; |
124 | has_full_ppgtt = INTEL_GEN(dev_priv) >= 7; | |
125 | has_full_48bit_ppgtt = | |
126 | IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9; | |
1893a71b | 127 | |
e320d400 ZW |
128 | if (intel_vgpu_active(dev_priv)) { |
129 | /* emulation is too hard */ | |
130 | has_full_ppgtt = false; | |
131 | has_full_48bit_ppgtt = false; | |
132 | } | |
71ba2d64 | 133 | |
0e4ca100 CW |
134 | if (!has_aliasing_ppgtt) |
135 | return 0; | |
136 | ||
70ee45e1 DL |
137 | /* |
138 | * We don't allow disabling PPGTT for gen9+ as it's a requirement for | |
139 | * execlists, the sole mechanism available to submit work. | |
140 | */ | |
c033666a | 141 | if (enable_ppgtt == 0 && INTEL_GEN(dev_priv) < 9) |
cfa7c862 DV |
142 | return 0; |
143 | ||
144 | if (enable_ppgtt == 1) | |
145 | return 1; | |
146 | ||
1893a71b | 147 | if (enable_ppgtt == 2 && has_full_ppgtt) |
cfa7c862 DV |
148 | return 2; |
149 | ||
1f9a99e0 MT |
150 | if (enable_ppgtt == 3 && has_full_48bit_ppgtt) |
151 | return 3; | |
152 | ||
93a25a9e DV |
153 | #ifdef CONFIG_INTEL_IOMMU |
154 | /* Disable ppgtt on SNB if VT-d is on. */ | |
c033666a | 155 | if (IS_GEN6(dev_priv) && intel_iommu_gfx_mapped) { |
93a25a9e | 156 | DRM_INFO("Disabling PPGTT because VT-d is on\n"); |
cfa7c862 | 157 | return 0; |
93a25a9e DV |
158 | } |
159 | #endif | |
160 | ||
62942ed7 | 161 | /* Early VLV doesn't have this */ |
91c8a326 | 162 | if (IS_VALLEYVIEW(dev_priv) && dev_priv->drm.pdev->revision < 0xb) { |
62942ed7 JB |
163 | DRM_DEBUG_DRIVER("disabling PPGTT on pre-B3 step VLV\n"); |
164 | return 0; | |
165 | } | |
166 | ||
e320d400 | 167 | if (INTEL_GEN(dev_priv) >= 8 && i915.enable_execlists && has_full_ppgtt) |
1f9a99e0 | 168 | return has_full_48bit_ppgtt ? 3 : 2; |
2f82bbdf MT |
169 | else |
170 | return has_aliasing_ppgtt ? 1 : 0; | |
93a25a9e DV |
171 | } |
172 | ||
70b9f6f8 DV |
173 | static int ppgtt_bind_vma(struct i915_vma *vma, |
174 | enum i915_cache_level cache_level, | |
175 | u32 unused) | |
47552659 DV |
176 | { |
177 | u32 pte_flags = 0; | |
178 | ||
a4f5ea64 | 179 | vma->pages = vma->obj->mm.pages; |
247177dd | 180 | |
47552659 DV |
181 | /* Currently applicable only to VLV */ |
182 | if (vma->obj->gt_ro) | |
183 | pte_flags |= PTE_READ_ONLY; | |
184 | ||
247177dd | 185 | vma->vm->insert_entries(vma->vm, vma->pages, vma->node.start, |
47552659 | 186 | cache_level, pte_flags); |
70b9f6f8 DV |
187 | |
188 | return 0; | |
47552659 DV |
189 | } |
190 | ||
191 | static void ppgtt_unbind_vma(struct i915_vma *vma) | |
192 | { | |
193 | vma->vm->clear_range(vma->vm, | |
194 | vma->node.start, | |
4fb84d99 | 195 | vma->size); |
47552659 | 196 | } |
6f65e29a | 197 | |
2c642b07 | 198 | static gen8_pte_t gen8_pte_encode(dma_addr_t addr, |
4fb84d99 | 199 | enum i915_cache_level level) |
94ec8f61 | 200 | { |
4fb84d99 | 201 | gen8_pte_t pte = _PAGE_PRESENT | _PAGE_RW; |
94ec8f61 | 202 | pte |= addr; |
63c42e56 BW |
203 | |
204 | switch (level) { | |
205 | case I915_CACHE_NONE: | |
fbe5d36e | 206 | pte |= PPAT_UNCACHED_INDEX; |
63c42e56 BW |
207 | break; |
208 | case I915_CACHE_WT: | |
209 | pte |= PPAT_DISPLAY_ELLC_INDEX; | |
210 | break; | |
211 | default: | |
212 | pte |= PPAT_CACHED_INDEX; | |
213 | break; | |
214 | } | |
215 | ||
94ec8f61 BW |
216 | return pte; |
217 | } | |
218 | ||
fe36f55d MK |
219 | static gen8_pde_t gen8_pde_encode(const dma_addr_t addr, |
220 | const enum i915_cache_level level) | |
b1fe6673 | 221 | { |
07749ef3 | 222 | gen8_pde_t pde = _PAGE_PRESENT | _PAGE_RW; |
b1fe6673 BW |
223 | pde |= addr; |
224 | if (level != I915_CACHE_NONE) | |
225 | pde |= PPAT_CACHED_PDE_INDEX; | |
226 | else | |
227 | pde |= PPAT_UNCACHED_INDEX; | |
228 | return pde; | |
229 | } | |
230 | ||
762d9936 MT |
231 | #define gen8_pdpe_encode gen8_pde_encode |
232 | #define gen8_pml4e_encode gen8_pde_encode | |
233 | ||
07749ef3 MT |
234 | static gen6_pte_t snb_pte_encode(dma_addr_t addr, |
235 | enum i915_cache_level level, | |
4fb84d99 | 236 | u32 unused) |
54d12527 | 237 | { |
4fb84d99 | 238 | gen6_pte_t pte = GEN6_PTE_VALID; |
54d12527 | 239 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
e7210c3c BW |
240 | |
241 | switch (level) { | |
350ec881 CW |
242 | case I915_CACHE_L3_LLC: |
243 | case I915_CACHE_LLC: | |
244 | pte |= GEN6_PTE_CACHE_LLC; | |
245 | break; | |
246 | case I915_CACHE_NONE: | |
247 | pte |= GEN6_PTE_UNCACHED; | |
248 | break; | |
249 | default: | |
5f77eeb0 | 250 | MISSING_CASE(level); |
350ec881 CW |
251 | } |
252 | ||
253 | return pte; | |
254 | } | |
255 | ||
07749ef3 MT |
256 | static gen6_pte_t ivb_pte_encode(dma_addr_t addr, |
257 | enum i915_cache_level level, | |
4fb84d99 | 258 | u32 unused) |
350ec881 | 259 | { |
4fb84d99 | 260 | gen6_pte_t pte = GEN6_PTE_VALID; |
350ec881 CW |
261 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
262 | ||
263 | switch (level) { | |
264 | case I915_CACHE_L3_LLC: | |
265 | pte |= GEN7_PTE_CACHE_L3_LLC; | |
e7210c3c BW |
266 | break; |
267 | case I915_CACHE_LLC: | |
268 | pte |= GEN6_PTE_CACHE_LLC; | |
269 | break; | |
270 | case I915_CACHE_NONE: | |
9119708c | 271 | pte |= GEN6_PTE_UNCACHED; |
e7210c3c BW |
272 | break; |
273 | default: | |
5f77eeb0 | 274 | MISSING_CASE(level); |
e7210c3c BW |
275 | } |
276 | ||
54d12527 BW |
277 | return pte; |
278 | } | |
279 | ||
07749ef3 MT |
280 | static gen6_pte_t byt_pte_encode(dma_addr_t addr, |
281 | enum i915_cache_level level, | |
4fb84d99 | 282 | u32 flags) |
93c34e70 | 283 | { |
4fb84d99 | 284 | gen6_pte_t pte = GEN6_PTE_VALID; |
93c34e70 KG |
285 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
286 | ||
24f3a8cf AG |
287 | if (!(flags & PTE_READ_ONLY)) |
288 | pte |= BYT_PTE_WRITEABLE; | |
93c34e70 KG |
289 | |
290 | if (level != I915_CACHE_NONE) | |
291 | pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES; | |
292 | ||
293 | return pte; | |
294 | } | |
295 | ||
07749ef3 MT |
296 | static gen6_pte_t hsw_pte_encode(dma_addr_t addr, |
297 | enum i915_cache_level level, | |
4fb84d99 | 298 | u32 unused) |
9119708c | 299 | { |
4fb84d99 | 300 | gen6_pte_t pte = GEN6_PTE_VALID; |
0d8ff15e | 301 | pte |= HSW_PTE_ADDR_ENCODE(addr); |
9119708c KG |
302 | |
303 | if (level != I915_CACHE_NONE) | |
87a6b688 | 304 | pte |= HSW_WB_LLC_AGE3; |
9119708c KG |
305 | |
306 | return pte; | |
307 | } | |
308 | ||
07749ef3 MT |
309 | static gen6_pte_t iris_pte_encode(dma_addr_t addr, |
310 | enum i915_cache_level level, | |
4fb84d99 | 311 | u32 unused) |
4d15c145 | 312 | { |
4fb84d99 | 313 | gen6_pte_t pte = GEN6_PTE_VALID; |
4d15c145 BW |
314 | pte |= HSW_PTE_ADDR_ENCODE(addr); |
315 | ||
651d794f CW |
316 | switch (level) { |
317 | case I915_CACHE_NONE: | |
318 | break; | |
319 | case I915_CACHE_WT: | |
c51e9701 | 320 | pte |= HSW_WT_ELLC_LLC_AGE3; |
651d794f CW |
321 | break; |
322 | default: | |
c51e9701 | 323 | pte |= HSW_WB_ELLC_LLC_AGE3; |
651d794f CW |
324 | break; |
325 | } | |
4d15c145 BW |
326 | |
327 | return pte; | |
328 | } | |
329 | ||
c114f76a MK |
330 | static int __setup_page_dma(struct drm_device *dev, |
331 | struct i915_page_dma *p, gfp_t flags) | |
678d96fb | 332 | { |
c49d13ee | 333 | struct device *kdev = &dev->pdev->dev; |
678d96fb | 334 | |
c114f76a | 335 | p->page = alloc_page(flags); |
44159ddb MK |
336 | if (!p->page) |
337 | return -ENOMEM; | |
678d96fb | 338 | |
c49d13ee | 339 | p->daddr = dma_map_page(kdev, |
44159ddb | 340 | p->page, 0, 4096, PCI_DMA_BIDIRECTIONAL); |
678d96fb | 341 | |
c49d13ee | 342 | if (dma_mapping_error(kdev, p->daddr)) { |
44159ddb MK |
343 | __free_page(p->page); |
344 | return -EINVAL; | |
345 | } | |
1266cdb1 MT |
346 | |
347 | return 0; | |
678d96fb BW |
348 | } |
349 | ||
c114f76a MK |
350 | static int setup_page_dma(struct drm_device *dev, struct i915_page_dma *p) |
351 | { | |
bb8f9cff | 352 | return __setup_page_dma(dev, p, I915_GFP_DMA); |
c114f76a MK |
353 | } |
354 | ||
44159ddb | 355 | static void cleanup_page_dma(struct drm_device *dev, struct i915_page_dma *p) |
06fda602 | 356 | { |
52a05c30 DW |
357 | struct pci_dev *pdev = dev->pdev; |
358 | ||
44159ddb | 359 | if (WARN_ON(!p->page)) |
06fda602 | 360 | return; |
678d96fb | 361 | |
52a05c30 | 362 | dma_unmap_page(&pdev->dev, p->daddr, 4096, PCI_DMA_BIDIRECTIONAL); |
44159ddb MK |
363 | __free_page(p->page); |
364 | memset(p, 0, sizeof(*p)); | |
365 | } | |
366 | ||
d1c54acd | 367 | static void *kmap_page_dma(struct i915_page_dma *p) |
73eeea53 | 368 | { |
d1c54acd MK |
369 | return kmap_atomic(p->page); |
370 | } | |
73eeea53 | 371 | |
d1c54acd MK |
372 | /* We use the flushing unmap only with ppgtt structures: |
373 | * page directories, page tables and scratch pages. | |
374 | */ | |
e2d214ae | 375 | static void kunmap_page_dma(struct drm_i915_private *dev_priv, void *vaddr) |
d1c54acd | 376 | { |
73eeea53 MK |
377 | /* There are only few exceptions for gen >=6. chv and bxt. |
378 | * And we are not sure about the latter so play safe for now. | |
379 | */ | |
e2d214ae | 380 | if (IS_CHERRYVIEW(dev_priv) || IS_BROXTON(dev_priv)) |
73eeea53 MK |
381 | drm_clflush_virt_range(vaddr, PAGE_SIZE); |
382 | ||
383 | kunmap_atomic(vaddr); | |
384 | } | |
385 | ||
567047be | 386 | #define kmap_px(px) kmap_page_dma(px_base(px)) |
e2d214ae TU |
387 | #define kunmap_px(ppgtt, vaddr) \ |
388 | kunmap_page_dma(to_i915((ppgtt)->base.dev), (vaddr)) | |
d1c54acd | 389 | |
567047be MK |
390 | #define setup_px(dev, px) setup_page_dma((dev), px_base(px)) |
391 | #define cleanup_px(dev, px) cleanup_page_dma((dev), px_base(px)) | |
e2d214ae TU |
392 | #define fill_px(dev_priv, px, v) fill_page_dma((dev_priv), px_base(px), (v)) |
393 | #define fill32_px(dev_priv, px, v) \ | |
394 | fill_page_dma_32((dev_priv), px_base(px), (v)) | |
567047be | 395 | |
e2d214ae TU |
396 | static void fill_page_dma(struct drm_i915_private *dev_priv, |
397 | struct i915_page_dma *p, const uint64_t val) | |
d1c54acd MK |
398 | { |
399 | int i; | |
400 | uint64_t * const vaddr = kmap_page_dma(p); | |
401 | ||
402 | for (i = 0; i < 512; i++) | |
403 | vaddr[i] = val; | |
404 | ||
e2d214ae | 405 | kunmap_page_dma(dev_priv, vaddr); |
d1c54acd MK |
406 | } |
407 | ||
e2d214ae TU |
408 | static void fill_page_dma_32(struct drm_i915_private *dev_priv, |
409 | struct i915_page_dma *p, const uint32_t val32) | |
73eeea53 MK |
410 | { |
411 | uint64_t v = val32; | |
412 | ||
413 | v = v << 32 | val32; | |
414 | ||
e2d214ae | 415 | fill_page_dma(dev_priv, p, v); |
73eeea53 MK |
416 | } |
417 | ||
8bcdd0f7 | 418 | static int |
bb8f9cff CW |
419 | setup_scratch_page(struct drm_device *dev, |
420 | struct i915_page_dma *scratch, | |
421 | gfp_t gfp) | |
4ad2af1e | 422 | { |
bb8f9cff | 423 | return __setup_page_dma(dev, scratch, gfp | __GFP_ZERO); |
4ad2af1e MK |
424 | } |
425 | ||
8bcdd0f7 CW |
426 | static void cleanup_scratch_page(struct drm_device *dev, |
427 | struct i915_page_dma *scratch) | |
4ad2af1e | 428 | { |
8bcdd0f7 | 429 | cleanup_page_dma(dev, scratch); |
4ad2af1e MK |
430 | } |
431 | ||
8a1ebd74 | 432 | static struct i915_page_table *alloc_pt(struct drm_device *dev) |
06fda602 | 433 | { |
ec565b3c | 434 | struct i915_page_table *pt; |
678d96fb BW |
435 | const size_t count = INTEL_INFO(dev)->gen >= 8 ? |
436 | GEN8_PTES : GEN6_PTES; | |
437 | int ret = -ENOMEM; | |
06fda602 BW |
438 | |
439 | pt = kzalloc(sizeof(*pt), GFP_KERNEL); | |
440 | if (!pt) | |
441 | return ERR_PTR(-ENOMEM); | |
442 | ||
678d96fb BW |
443 | pt->used_ptes = kcalloc(BITS_TO_LONGS(count), sizeof(*pt->used_ptes), |
444 | GFP_KERNEL); | |
445 | ||
446 | if (!pt->used_ptes) | |
447 | goto fail_bitmap; | |
448 | ||
567047be | 449 | ret = setup_px(dev, pt); |
678d96fb | 450 | if (ret) |
44159ddb | 451 | goto fail_page_m; |
06fda602 BW |
452 | |
453 | return pt; | |
678d96fb | 454 | |
44159ddb | 455 | fail_page_m: |
678d96fb BW |
456 | kfree(pt->used_ptes); |
457 | fail_bitmap: | |
458 | kfree(pt); | |
459 | ||
460 | return ERR_PTR(ret); | |
06fda602 BW |
461 | } |
462 | ||
2e906bea | 463 | static void free_pt(struct drm_device *dev, struct i915_page_table *pt) |
06fda602 | 464 | { |
2e906bea MK |
465 | cleanup_px(dev, pt); |
466 | kfree(pt->used_ptes); | |
467 | kfree(pt); | |
468 | } | |
469 | ||
470 | static void gen8_initialize_pt(struct i915_address_space *vm, | |
471 | struct i915_page_table *pt) | |
472 | { | |
473 | gen8_pte_t scratch_pte; | |
474 | ||
8bcdd0f7 | 475 | scratch_pte = gen8_pte_encode(vm->scratch_page.daddr, |
4fb84d99 | 476 | I915_CACHE_LLC); |
2e906bea | 477 | |
e2d214ae | 478 | fill_px(to_i915(vm->dev), pt, scratch_pte); |
2e906bea MK |
479 | } |
480 | ||
481 | static void gen6_initialize_pt(struct i915_address_space *vm, | |
482 | struct i915_page_table *pt) | |
483 | { | |
484 | gen6_pte_t scratch_pte; | |
485 | ||
8bcdd0f7 | 486 | WARN_ON(vm->scratch_page.daddr == 0); |
2e906bea | 487 | |
8bcdd0f7 | 488 | scratch_pte = vm->pte_encode(vm->scratch_page.daddr, |
4fb84d99 | 489 | I915_CACHE_LLC, 0); |
2e906bea | 490 | |
e2d214ae | 491 | fill32_px(to_i915(vm->dev), pt, scratch_pte); |
06fda602 BW |
492 | } |
493 | ||
8a1ebd74 | 494 | static struct i915_page_directory *alloc_pd(struct drm_device *dev) |
06fda602 | 495 | { |
ec565b3c | 496 | struct i915_page_directory *pd; |
33c8819f | 497 | int ret = -ENOMEM; |
06fda602 BW |
498 | |
499 | pd = kzalloc(sizeof(*pd), GFP_KERNEL); | |
500 | if (!pd) | |
501 | return ERR_PTR(-ENOMEM); | |
502 | ||
33c8819f MT |
503 | pd->used_pdes = kcalloc(BITS_TO_LONGS(I915_PDES), |
504 | sizeof(*pd->used_pdes), GFP_KERNEL); | |
505 | if (!pd->used_pdes) | |
a08e111a | 506 | goto fail_bitmap; |
33c8819f | 507 | |
567047be | 508 | ret = setup_px(dev, pd); |
33c8819f | 509 | if (ret) |
a08e111a | 510 | goto fail_page_m; |
e5815a2e | 511 | |
06fda602 | 512 | return pd; |
33c8819f | 513 | |
a08e111a | 514 | fail_page_m: |
33c8819f | 515 | kfree(pd->used_pdes); |
a08e111a | 516 | fail_bitmap: |
33c8819f MT |
517 | kfree(pd); |
518 | ||
519 | return ERR_PTR(ret); | |
06fda602 BW |
520 | } |
521 | ||
2e906bea MK |
522 | static void free_pd(struct drm_device *dev, struct i915_page_directory *pd) |
523 | { | |
524 | if (px_page(pd)) { | |
525 | cleanup_px(dev, pd); | |
526 | kfree(pd->used_pdes); | |
527 | kfree(pd); | |
528 | } | |
529 | } | |
530 | ||
531 | static void gen8_initialize_pd(struct i915_address_space *vm, | |
532 | struct i915_page_directory *pd) | |
533 | { | |
534 | gen8_pde_t scratch_pde; | |
535 | ||
536 | scratch_pde = gen8_pde_encode(px_dma(vm->scratch_pt), I915_CACHE_LLC); | |
537 | ||
e2d214ae | 538 | fill_px(to_i915(vm->dev), pd, scratch_pde); |
2e906bea MK |
539 | } |
540 | ||
6ac18502 MT |
541 | static int __pdp_init(struct drm_device *dev, |
542 | struct i915_page_directory_pointer *pdp) | |
543 | { | |
544 | size_t pdpes = I915_PDPES_PER_PDP(dev); | |
545 | ||
546 | pdp->used_pdpes = kcalloc(BITS_TO_LONGS(pdpes), | |
547 | sizeof(unsigned long), | |
548 | GFP_KERNEL); | |
549 | if (!pdp->used_pdpes) | |
550 | return -ENOMEM; | |
551 | ||
552 | pdp->page_directory = kcalloc(pdpes, sizeof(*pdp->page_directory), | |
553 | GFP_KERNEL); | |
554 | if (!pdp->page_directory) { | |
555 | kfree(pdp->used_pdpes); | |
556 | /* the PDP might be the statically allocated top level. Keep it | |
557 | * as clean as possible */ | |
558 | pdp->used_pdpes = NULL; | |
559 | return -ENOMEM; | |
560 | } | |
561 | ||
562 | return 0; | |
563 | } | |
564 | ||
565 | static void __pdp_fini(struct i915_page_directory_pointer *pdp) | |
566 | { | |
567 | kfree(pdp->used_pdpes); | |
568 | kfree(pdp->page_directory); | |
569 | pdp->page_directory = NULL; | |
570 | } | |
571 | ||
762d9936 MT |
572 | static struct |
573 | i915_page_directory_pointer *alloc_pdp(struct drm_device *dev) | |
574 | { | |
575 | struct i915_page_directory_pointer *pdp; | |
576 | int ret = -ENOMEM; | |
577 | ||
578 | WARN_ON(!USES_FULL_48BIT_PPGTT(dev)); | |
579 | ||
580 | pdp = kzalloc(sizeof(*pdp), GFP_KERNEL); | |
581 | if (!pdp) | |
582 | return ERR_PTR(-ENOMEM); | |
583 | ||
584 | ret = __pdp_init(dev, pdp); | |
585 | if (ret) | |
586 | goto fail_bitmap; | |
587 | ||
588 | ret = setup_px(dev, pdp); | |
589 | if (ret) | |
590 | goto fail_page_m; | |
591 | ||
592 | return pdp; | |
593 | ||
594 | fail_page_m: | |
595 | __pdp_fini(pdp); | |
596 | fail_bitmap: | |
597 | kfree(pdp); | |
598 | ||
599 | return ERR_PTR(ret); | |
600 | } | |
601 | ||
6ac18502 MT |
602 | static void free_pdp(struct drm_device *dev, |
603 | struct i915_page_directory_pointer *pdp) | |
604 | { | |
605 | __pdp_fini(pdp); | |
762d9936 MT |
606 | if (USES_FULL_48BIT_PPGTT(dev)) { |
607 | cleanup_px(dev, pdp); | |
608 | kfree(pdp); | |
609 | } | |
610 | } | |
611 | ||
69ab76fd MT |
612 | static void gen8_initialize_pdp(struct i915_address_space *vm, |
613 | struct i915_page_directory_pointer *pdp) | |
614 | { | |
615 | gen8_ppgtt_pdpe_t scratch_pdpe; | |
616 | ||
617 | scratch_pdpe = gen8_pdpe_encode(px_dma(vm->scratch_pd), I915_CACHE_LLC); | |
618 | ||
e2d214ae | 619 | fill_px(to_i915(vm->dev), pdp, scratch_pdpe); |
69ab76fd MT |
620 | } |
621 | ||
622 | static void gen8_initialize_pml4(struct i915_address_space *vm, | |
623 | struct i915_pml4 *pml4) | |
624 | { | |
625 | gen8_ppgtt_pml4e_t scratch_pml4e; | |
626 | ||
627 | scratch_pml4e = gen8_pml4e_encode(px_dma(vm->scratch_pdp), | |
628 | I915_CACHE_LLC); | |
629 | ||
e2d214ae | 630 | fill_px(to_i915(vm->dev), pml4, scratch_pml4e); |
69ab76fd MT |
631 | } |
632 | ||
762d9936 MT |
633 | static void |
634 | gen8_setup_page_directory(struct i915_hw_ppgtt *ppgtt, | |
635 | struct i915_page_directory_pointer *pdp, | |
636 | struct i915_page_directory *pd, | |
637 | int index) | |
638 | { | |
639 | gen8_ppgtt_pdpe_t *page_directorypo; | |
640 | ||
641 | if (!USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) | |
642 | return; | |
643 | ||
644 | page_directorypo = kmap_px(pdp); | |
645 | page_directorypo[index] = gen8_pdpe_encode(px_dma(pd), I915_CACHE_LLC); | |
646 | kunmap_px(ppgtt, page_directorypo); | |
647 | } | |
648 | ||
649 | static void | |
650 | gen8_setup_page_directory_pointer(struct i915_hw_ppgtt *ppgtt, | |
651 | struct i915_pml4 *pml4, | |
652 | struct i915_page_directory_pointer *pdp, | |
653 | int index) | |
654 | { | |
655 | gen8_ppgtt_pml4e_t *pagemap = kmap_px(pml4); | |
656 | ||
657 | WARN_ON(!USES_FULL_48BIT_PPGTT(ppgtt->base.dev)); | |
658 | pagemap[index] = gen8_pml4e_encode(px_dma(pdp), I915_CACHE_LLC); | |
659 | kunmap_px(ppgtt, pagemap); | |
6ac18502 MT |
660 | } |
661 | ||
94e409c1 | 662 | /* Broadwell Page Directory Pointer Descriptors */ |
e85b26dc | 663 | static int gen8_write_pdp(struct drm_i915_gem_request *req, |
7cb6d7ac MT |
664 | unsigned entry, |
665 | dma_addr_t addr) | |
94e409c1 | 666 | { |
7e37f889 | 667 | struct intel_ring *ring = req->ring; |
4a570db5 | 668 | struct intel_engine_cs *engine = req->engine; |
94e409c1 BW |
669 | int ret; |
670 | ||
671 | BUG_ON(entry >= 4); | |
672 | ||
5fb9de1a | 673 | ret = intel_ring_begin(req, 6); |
94e409c1 BW |
674 | if (ret) |
675 | return ret; | |
676 | ||
b5321f30 CW |
677 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); |
678 | intel_ring_emit_reg(ring, GEN8_RING_PDP_UDW(engine, entry)); | |
679 | intel_ring_emit(ring, upper_32_bits(addr)); | |
680 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
681 | intel_ring_emit_reg(ring, GEN8_RING_PDP_LDW(engine, entry)); | |
682 | intel_ring_emit(ring, lower_32_bits(addr)); | |
683 | intel_ring_advance(ring); | |
94e409c1 BW |
684 | |
685 | return 0; | |
686 | } | |
687 | ||
2dba3239 MT |
688 | static int gen8_legacy_mm_switch(struct i915_hw_ppgtt *ppgtt, |
689 | struct drm_i915_gem_request *req) | |
94e409c1 | 690 | { |
eeb9488e | 691 | int i, ret; |
94e409c1 | 692 | |
7cb6d7ac | 693 | for (i = GEN8_LEGACY_PDPES - 1; i >= 0; i--) { |
d852c7bf MK |
694 | const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i); |
695 | ||
e85b26dc | 696 | ret = gen8_write_pdp(req, i, pd_daddr); |
eeb9488e BW |
697 | if (ret) |
698 | return ret; | |
94e409c1 | 699 | } |
d595bd4b | 700 | |
eeb9488e | 701 | return 0; |
94e409c1 BW |
702 | } |
703 | ||
2dba3239 MT |
704 | static int gen8_48b_mm_switch(struct i915_hw_ppgtt *ppgtt, |
705 | struct drm_i915_gem_request *req) | |
706 | { | |
707 | return gen8_write_pdp(req, 0, px_dma(&ppgtt->pml4)); | |
708 | } | |
709 | ||
fce93755 MK |
710 | /* PDE TLBs are a pain to invalidate on GEN8+. When we modify |
711 | * the page table structures, we mark them dirty so that | |
712 | * context switching/execlist queuing code takes extra steps | |
713 | * to ensure that tlbs are flushed. | |
714 | */ | |
715 | static void mark_tlbs_dirty(struct i915_hw_ppgtt *ppgtt) | |
716 | { | |
717 | ppgtt->pd_dirty_rings = INTEL_INFO(ppgtt->base.dev)->ring_mask; | |
718 | } | |
719 | ||
2ce5179f MW |
720 | /* Removes entries from a single page table, releasing it if it's empty. |
721 | * Caller can use the return value to update higher-level entries. | |
722 | */ | |
723 | static bool gen8_ppgtt_clear_pt(struct i915_address_space *vm, | |
d209b9c3 MW |
724 | struct i915_page_table *pt, |
725 | uint64_t start, | |
726 | uint64_t length) | |
459108b8 | 727 | { |
e5716f55 | 728 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
d209b9c3 | 729 | unsigned int num_entries = gen8_pte_count(start, length); |
37c63934 MK |
730 | unsigned int pte = gen8_pte_index(start); |
731 | unsigned int pte_end = pte + num_entries; | |
f9b5b782 | 732 | gen8_pte_t *pt_vaddr; |
d209b9c3 MW |
733 | gen8_pte_t scratch_pte = gen8_pte_encode(vm->scratch_page.daddr, |
734 | I915_CACHE_LLC); | |
459108b8 | 735 | |
d209b9c3 | 736 | if (WARN_ON(!px_page(pt))) |
2ce5179f | 737 | return false; |
459108b8 | 738 | |
37c63934 MK |
739 | GEM_BUG_ON(pte_end > GEN8_PTES); |
740 | ||
741 | bitmap_clear(pt->used_ptes, pte, num_entries); | |
06fda602 | 742 | |
2ce5179f MW |
743 | if (bitmap_empty(pt->used_ptes, GEN8_PTES)) { |
744 | free_pt(vm->dev, pt); | |
745 | return true; | |
746 | } | |
747 | ||
d209b9c3 MW |
748 | pt_vaddr = kmap_px(pt); |
749 | ||
37c63934 MK |
750 | while (pte < pte_end) |
751 | pt_vaddr[pte++] = scratch_pte; | |
06fda602 | 752 | |
d209b9c3 | 753 | kunmap_px(ppgtt, pt_vaddr); |
2ce5179f MW |
754 | |
755 | return false; | |
d209b9c3 | 756 | } |
06fda602 | 757 | |
2ce5179f MW |
758 | /* Removes entries from a single page dir, releasing it if it's empty. |
759 | * Caller can use the return value to update higher-level entries | |
760 | */ | |
761 | static bool gen8_ppgtt_clear_pd(struct i915_address_space *vm, | |
d209b9c3 MW |
762 | struct i915_page_directory *pd, |
763 | uint64_t start, | |
764 | uint64_t length) | |
765 | { | |
2ce5179f | 766 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
d209b9c3 MW |
767 | struct i915_page_table *pt; |
768 | uint64_t pde; | |
2ce5179f MW |
769 | gen8_pde_t *pde_vaddr; |
770 | gen8_pde_t scratch_pde = gen8_pde_encode(px_dma(vm->scratch_pt), | |
771 | I915_CACHE_LLC); | |
d209b9c3 MW |
772 | |
773 | gen8_for_each_pde(pt, pd, start, length, pde) { | |
06fda602 | 774 | if (WARN_ON(!pd->page_table[pde])) |
00245266 | 775 | break; |
06fda602 | 776 | |
2ce5179f MW |
777 | if (gen8_ppgtt_clear_pt(vm, pt, start, length)) { |
778 | __clear_bit(pde, pd->used_pdes); | |
779 | pde_vaddr = kmap_px(pd); | |
780 | pde_vaddr[pde] = scratch_pde; | |
781 | kunmap_px(ppgtt, pde_vaddr); | |
782 | } | |
783 | } | |
784 | ||
785 | if (bitmap_empty(pd->used_pdes, I915_PDES)) { | |
786 | free_pd(vm->dev, pd); | |
787 | return true; | |
d209b9c3 | 788 | } |
2ce5179f MW |
789 | |
790 | return false; | |
d209b9c3 | 791 | } |
06fda602 | 792 | |
2ce5179f MW |
793 | /* Removes entries from a single page dir pointer, releasing it if it's empty. |
794 | * Caller can use the return value to update higher-level entries | |
795 | */ | |
796 | static bool gen8_ppgtt_clear_pdp(struct i915_address_space *vm, | |
d209b9c3 MW |
797 | struct i915_page_directory_pointer *pdp, |
798 | uint64_t start, | |
799 | uint64_t length) | |
800 | { | |
2ce5179f | 801 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
d209b9c3 MW |
802 | struct i915_page_directory *pd; |
803 | uint64_t pdpe; | |
2ce5179f MW |
804 | gen8_ppgtt_pdpe_t *pdpe_vaddr; |
805 | gen8_ppgtt_pdpe_t scratch_pdpe = | |
806 | gen8_pdpe_encode(px_dma(vm->scratch_pd), I915_CACHE_LLC); | |
06fda602 | 807 | |
d209b9c3 MW |
808 | gen8_for_each_pdpe(pd, pdp, start, length, pdpe) { |
809 | if (WARN_ON(!pdp->page_directory[pdpe])) | |
810 | break; | |
459108b8 | 811 | |
2ce5179f MW |
812 | if (gen8_ppgtt_clear_pd(vm, pd, start, length)) { |
813 | __clear_bit(pdpe, pdp->used_pdpes); | |
814 | if (USES_FULL_48BIT_PPGTT(vm->dev)) { | |
815 | pdpe_vaddr = kmap_px(pdp); | |
816 | pdpe_vaddr[pdpe] = scratch_pdpe; | |
817 | kunmap_px(ppgtt, pdpe_vaddr); | |
818 | } | |
819 | } | |
820 | } | |
821 | ||
fce93755 MK |
822 | mark_tlbs_dirty(ppgtt); |
823 | ||
2ce5179f MW |
824 | if (USES_FULL_48BIT_PPGTT(vm->dev) && |
825 | bitmap_empty(pdp->used_pdpes, I915_PDPES_PER_PDP(vm->dev))) { | |
826 | free_pdp(vm->dev, pdp); | |
827 | return true; | |
d209b9c3 | 828 | } |
2ce5179f MW |
829 | |
830 | return false; | |
d209b9c3 | 831 | } |
459108b8 | 832 | |
2ce5179f MW |
833 | /* Removes entries from a single pml4. |
834 | * This is the top-level structure in 4-level page tables used on gen8+. | |
835 | * Empty entries are always scratch pml4e. | |
836 | */ | |
d209b9c3 MW |
837 | static void gen8_ppgtt_clear_pml4(struct i915_address_space *vm, |
838 | struct i915_pml4 *pml4, | |
839 | uint64_t start, | |
840 | uint64_t length) | |
841 | { | |
2ce5179f | 842 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
d209b9c3 MW |
843 | struct i915_page_directory_pointer *pdp; |
844 | uint64_t pml4e; | |
2ce5179f MW |
845 | gen8_ppgtt_pml4e_t *pml4e_vaddr; |
846 | gen8_ppgtt_pml4e_t scratch_pml4e = | |
847 | gen8_pml4e_encode(px_dma(vm->scratch_pdp), I915_CACHE_LLC); | |
848 | ||
849 | GEM_BUG_ON(!USES_FULL_48BIT_PPGTT(vm->dev)); | |
459108b8 | 850 | |
d209b9c3 MW |
851 | gen8_for_each_pml4e(pdp, pml4, start, length, pml4e) { |
852 | if (WARN_ON(!pml4->pdps[pml4e])) | |
853 | break; | |
459108b8 | 854 | |
2ce5179f MW |
855 | if (gen8_ppgtt_clear_pdp(vm, pdp, start, length)) { |
856 | __clear_bit(pml4e, pml4->used_pml4es); | |
857 | pml4e_vaddr = kmap_px(pml4); | |
858 | pml4e_vaddr[pml4e] = scratch_pml4e; | |
859 | kunmap_px(ppgtt, pml4e_vaddr); | |
860 | } | |
459108b8 BW |
861 | } |
862 | } | |
863 | ||
f9b5b782 | 864 | static void gen8_ppgtt_clear_range(struct i915_address_space *vm, |
4fb84d99 | 865 | uint64_t start, uint64_t length) |
9df15b49 | 866 | { |
e5716f55 | 867 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
f9b5b782 | 868 | |
d209b9c3 MW |
869 | if (USES_FULL_48BIT_PPGTT(vm->dev)) |
870 | gen8_ppgtt_clear_pml4(vm, &ppgtt->pml4, start, length); | |
871 | else | |
872 | gen8_ppgtt_clear_pdp(vm, &ppgtt->pdp, start, length); | |
f9b5b782 MT |
873 | } |
874 | ||
875 | static void | |
876 | gen8_ppgtt_insert_pte_entries(struct i915_address_space *vm, | |
877 | struct i915_page_directory_pointer *pdp, | |
3387d433 | 878 | struct sg_page_iter *sg_iter, |
f9b5b782 MT |
879 | uint64_t start, |
880 | enum i915_cache_level cache_level) | |
881 | { | |
e5716f55 | 882 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
07749ef3 | 883 | gen8_pte_t *pt_vaddr; |
de5ba8eb MT |
884 | unsigned pdpe = gen8_pdpe_index(start); |
885 | unsigned pde = gen8_pde_index(start); | |
886 | unsigned pte = gen8_pte_index(start); | |
9df15b49 | 887 | |
6f1cc993 | 888 | pt_vaddr = NULL; |
7ad47cf2 | 889 | |
3387d433 | 890 | while (__sg_page_iter_next(sg_iter)) { |
d7b3de91 | 891 | if (pt_vaddr == NULL) { |
d4ec9da0 | 892 | struct i915_page_directory *pd = pdp->page_directory[pdpe]; |
ec565b3c | 893 | struct i915_page_table *pt = pd->page_table[pde]; |
d1c54acd | 894 | pt_vaddr = kmap_px(pt); |
d7b3de91 | 895 | } |
9df15b49 | 896 | |
7ad47cf2 | 897 | pt_vaddr[pte] = |
3387d433 | 898 | gen8_pte_encode(sg_page_iter_dma_address(sg_iter), |
4fb84d99 | 899 | cache_level); |
07749ef3 | 900 | if (++pte == GEN8_PTES) { |
d1c54acd | 901 | kunmap_px(ppgtt, pt_vaddr); |
6f1cc993 | 902 | pt_vaddr = NULL; |
07749ef3 | 903 | if (++pde == I915_PDES) { |
de5ba8eb MT |
904 | if (++pdpe == I915_PDPES_PER_PDP(vm->dev)) |
905 | break; | |
7ad47cf2 BW |
906 | pde = 0; |
907 | } | |
908 | pte = 0; | |
9df15b49 BW |
909 | } |
910 | } | |
d1c54acd MK |
911 | |
912 | if (pt_vaddr) | |
913 | kunmap_px(ppgtt, pt_vaddr); | |
9df15b49 BW |
914 | } |
915 | ||
f9b5b782 MT |
916 | static void gen8_ppgtt_insert_entries(struct i915_address_space *vm, |
917 | struct sg_table *pages, | |
918 | uint64_t start, | |
919 | enum i915_cache_level cache_level, | |
920 | u32 unused) | |
921 | { | |
e5716f55 | 922 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
3387d433 | 923 | struct sg_page_iter sg_iter; |
f9b5b782 | 924 | |
3387d433 | 925 | __sg_page_iter_start(&sg_iter, pages->sgl, sg_nents(pages->sgl), 0); |
de5ba8eb MT |
926 | |
927 | if (!USES_FULL_48BIT_PPGTT(vm->dev)) { | |
928 | gen8_ppgtt_insert_pte_entries(vm, &ppgtt->pdp, &sg_iter, start, | |
929 | cache_level); | |
930 | } else { | |
931 | struct i915_page_directory_pointer *pdp; | |
e8ebd8e2 | 932 | uint64_t pml4e; |
de5ba8eb MT |
933 | uint64_t length = (uint64_t)pages->orig_nents << PAGE_SHIFT; |
934 | ||
e8ebd8e2 | 935 | gen8_for_each_pml4e(pdp, &ppgtt->pml4, start, length, pml4e) { |
de5ba8eb MT |
936 | gen8_ppgtt_insert_pte_entries(vm, pdp, &sg_iter, |
937 | start, cache_level); | |
938 | } | |
939 | } | |
f9b5b782 MT |
940 | } |
941 | ||
f37c0505 MT |
942 | static void gen8_free_page_tables(struct drm_device *dev, |
943 | struct i915_page_directory *pd) | |
7ad47cf2 BW |
944 | { |
945 | int i; | |
946 | ||
567047be | 947 | if (!px_page(pd)) |
7ad47cf2 BW |
948 | return; |
949 | ||
33c8819f | 950 | for_each_set_bit(i, pd->used_pdes, I915_PDES) { |
06fda602 BW |
951 | if (WARN_ON(!pd->page_table[i])) |
952 | continue; | |
7ad47cf2 | 953 | |
a08e111a | 954 | free_pt(dev, pd->page_table[i]); |
06fda602 BW |
955 | pd->page_table[i] = NULL; |
956 | } | |
d7b3de91 BW |
957 | } |
958 | ||
8776f02b MK |
959 | static int gen8_init_scratch(struct i915_address_space *vm) |
960 | { | |
961 | struct drm_device *dev = vm->dev; | |
64c050db | 962 | int ret; |
8776f02b | 963 | |
bb8f9cff | 964 | ret = setup_scratch_page(dev, &vm->scratch_page, I915_GFP_DMA); |
8bcdd0f7 CW |
965 | if (ret) |
966 | return ret; | |
8776f02b MK |
967 | |
968 | vm->scratch_pt = alloc_pt(dev); | |
969 | if (IS_ERR(vm->scratch_pt)) { | |
64c050db MA |
970 | ret = PTR_ERR(vm->scratch_pt); |
971 | goto free_scratch_page; | |
8776f02b MK |
972 | } |
973 | ||
974 | vm->scratch_pd = alloc_pd(dev); | |
975 | if (IS_ERR(vm->scratch_pd)) { | |
64c050db MA |
976 | ret = PTR_ERR(vm->scratch_pd); |
977 | goto free_pt; | |
8776f02b MK |
978 | } |
979 | ||
69ab76fd MT |
980 | if (USES_FULL_48BIT_PPGTT(dev)) { |
981 | vm->scratch_pdp = alloc_pdp(dev); | |
982 | if (IS_ERR(vm->scratch_pdp)) { | |
64c050db MA |
983 | ret = PTR_ERR(vm->scratch_pdp); |
984 | goto free_pd; | |
69ab76fd MT |
985 | } |
986 | } | |
987 | ||
8776f02b MK |
988 | gen8_initialize_pt(vm, vm->scratch_pt); |
989 | gen8_initialize_pd(vm, vm->scratch_pd); | |
69ab76fd MT |
990 | if (USES_FULL_48BIT_PPGTT(dev)) |
991 | gen8_initialize_pdp(vm, vm->scratch_pdp); | |
8776f02b MK |
992 | |
993 | return 0; | |
64c050db MA |
994 | |
995 | free_pd: | |
996 | free_pd(dev, vm->scratch_pd); | |
997 | free_pt: | |
998 | free_pt(dev, vm->scratch_pt); | |
999 | free_scratch_page: | |
8bcdd0f7 | 1000 | cleanup_scratch_page(dev, &vm->scratch_page); |
64c050db MA |
1001 | |
1002 | return ret; | |
8776f02b MK |
1003 | } |
1004 | ||
650da34c ZL |
1005 | static int gen8_ppgtt_notify_vgt(struct i915_hw_ppgtt *ppgtt, bool create) |
1006 | { | |
1007 | enum vgt_g2v_type msg; | |
df28564d | 1008 | struct drm_i915_private *dev_priv = to_i915(ppgtt->base.dev); |
650da34c ZL |
1009 | int i; |
1010 | ||
df28564d | 1011 | if (USES_FULL_48BIT_PPGTT(dev_priv)) { |
650da34c ZL |
1012 | u64 daddr = px_dma(&ppgtt->pml4); |
1013 | ||
ab75bb5d VS |
1014 | I915_WRITE(vgtif_reg(pdp[0].lo), lower_32_bits(daddr)); |
1015 | I915_WRITE(vgtif_reg(pdp[0].hi), upper_32_bits(daddr)); | |
650da34c ZL |
1016 | |
1017 | msg = (create ? VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE : | |
1018 | VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY); | |
1019 | } else { | |
1020 | for (i = 0; i < GEN8_LEGACY_PDPES; i++) { | |
1021 | u64 daddr = i915_page_dir_dma_addr(ppgtt, i); | |
1022 | ||
ab75bb5d VS |
1023 | I915_WRITE(vgtif_reg(pdp[i].lo), lower_32_bits(daddr)); |
1024 | I915_WRITE(vgtif_reg(pdp[i].hi), upper_32_bits(daddr)); | |
650da34c ZL |
1025 | } |
1026 | ||
1027 | msg = (create ? VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE : | |
1028 | VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY); | |
1029 | } | |
1030 | ||
1031 | I915_WRITE(vgtif_reg(g2v_notify), msg); | |
1032 | ||
1033 | return 0; | |
1034 | } | |
1035 | ||
8776f02b MK |
1036 | static void gen8_free_scratch(struct i915_address_space *vm) |
1037 | { | |
1038 | struct drm_device *dev = vm->dev; | |
1039 | ||
69ab76fd MT |
1040 | if (USES_FULL_48BIT_PPGTT(dev)) |
1041 | free_pdp(dev, vm->scratch_pdp); | |
8776f02b MK |
1042 | free_pd(dev, vm->scratch_pd); |
1043 | free_pt(dev, vm->scratch_pt); | |
8bcdd0f7 | 1044 | cleanup_scratch_page(dev, &vm->scratch_page); |
8776f02b MK |
1045 | } |
1046 | ||
762d9936 MT |
1047 | static void gen8_ppgtt_cleanup_3lvl(struct drm_device *dev, |
1048 | struct i915_page_directory_pointer *pdp) | |
b45a6715 BW |
1049 | { |
1050 | int i; | |
1051 | ||
d4ec9da0 MT |
1052 | for_each_set_bit(i, pdp->used_pdpes, I915_PDPES_PER_PDP(dev)) { |
1053 | if (WARN_ON(!pdp->page_directory[i])) | |
06fda602 BW |
1054 | continue; |
1055 | ||
d4ec9da0 MT |
1056 | gen8_free_page_tables(dev, pdp->page_directory[i]); |
1057 | free_pd(dev, pdp->page_directory[i]); | |
7ad47cf2 | 1058 | } |
69876bed | 1059 | |
d4ec9da0 | 1060 | free_pdp(dev, pdp); |
762d9936 MT |
1061 | } |
1062 | ||
1063 | static void gen8_ppgtt_cleanup_4lvl(struct i915_hw_ppgtt *ppgtt) | |
1064 | { | |
1065 | int i; | |
1066 | ||
1067 | for_each_set_bit(i, ppgtt->pml4.used_pml4es, GEN8_PML4ES_PER_PML4) { | |
1068 | if (WARN_ON(!ppgtt->pml4.pdps[i])) | |
1069 | continue; | |
1070 | ||
1071 | gen8_ppgtt_cleanup_3lvl(ppgtt->base.dev, ppgtt->pml4.pdps[i]); | |
1072 | } | |
1073 | ||
1074 | cleanup_px(ppgtt->base.dev, &ppgtt->pml4); | |
1075 | } | |
1076 | ||
1077 | static void gen8_ppgtt_cleanup(struct i915_address_space *vm) | |
1078 | { | |
e5716f55 | 1079 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
762d9936 | 1080 | |
c033666a | 1081 | if (intel_vgpu_active(to_i915(vm->dev))) |
650da34c ZL |
1082 | gen8_ppgtt_notify_vgt(ppgtt, false); |
1083 | ||
762d9936 MT |
1084 | if (!USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) |
1085 | gen8_ppgtt_cleanup_3lvl(ppgtt->base.dev, &ppgtt->pdp); | |
1086 | else | |
1087 | gen8_ppgtt_cleanup_4lvl(ppgtt); | |
d4ec9da0 | 1088 | |
8776f02b | 1089 | gen8_free_scratch(vm); |
b45a6715 BW |
1090 | } |
1091 | ||
d7b2633d MT |
1092 | /** |
1093 | * gen8_ppgtt_alloc_pagetabs() - Allocate page tables for VA range. | |
d4ec9da0 MT |
1094 | * @vm: Master vm structure. |
1095 | * @pd: Page directory for this address range. | |
d7b2633d | 1096 | * @start: Starting virtual address to begin allocations. |
d4ec9da0 | 1097 | * @length: Size of the allocations. |
d7b2633d MT |
1098 | * @new_pts: Bitmap set by function with new allocations. Likely used by the |
1099 | * caller to free on error. | |
1100 | * | |
1101 | * Allocate the required number of page tables. Extremely similar to | |
1102 | * gen8_ppgtt_alloc_page_directories(). The main difference is here we are limited by | |
1103 | * the page directory boundary (instead of the page directory pointer). That | |
1104 | * boundary is 1GB virtual. Therefore, unlike gen8_ppgtt_alloc_page_directories(), it is | |
1105 | * possible, and likely that the caller will need to use multiple calls of this | |
1106 | * function to achieve the appropriate allocation. | |
1107 | * | |
1108 | * Return: 0 if success; negative error code otherwise. | |
1109 | */ | |
d4ec9da0 | 1110 | static int gen8_ppgtt_alloc_pagetabs(struct i915_address_space *vm, |
e5815a2e | 1111 | struct i915_page_directory *pd, |
5441f0cb | 1112 | uint64_t start, |
d7b2633d MT |
1113 | uint64_t length, |
1114 | unsigned long *new_pts) | |
bf2b4ed2 | 1115 | { |
d4ec9da0 | 1116 | struct drm_device *dev = vm->dev; |
d7b2633d | 1117 | struct i915_page_table *pt; |
5441f0cb | 1118 | uint32_t pde; |
bf2b4ed2 | 1119 | |
e8ebd8e2 | 1120 | gen8_for_each_pde(pt, pd, start, length, pde) { |
d7b2633d | 1121 | /* Don't reallocate page tables */ |
6ac18502 | 1122 | if (test_bit(pde, pd->used_pdes)) { |
d7b2633d | 1123 | /* Scratch is never allocated this way */ |
d4ec9da0 | 1124 | WARN_ON(pt == vm->scratch_pt); |
d7b2633d MT |
1125 | continue; |
1126 | } | |
1127 | ||
8a1ebd74 | 1128 | pt = alloc_pt(dev); |
d7b2633d | 1129 | if (IS_ERR(pt)) |
5441f0cb MT |
1130 | goto unwind_out; |
1131 | ||
d4ec9da0 | 1132 | gen8_initialize_pt(vm, pt); |
d7b2633d | 1133 | pd->page_table[pde] = pt; |
966082c9 | 1134 | __set_bit(pde, new_pts); |
4c06ec8d | 1135 | trace_i915_page_table_entry_alloc(vm, pde, start, GEN8_PDE_SHIFT); |
7ad47cf2 BW |
1136 | } |
1137 | ||
bf2b4ed2 | 1138 | return 0; |
7ad47cf2 BW |
1139 | |
1140 | unwind_out: | |
d7b2633d | 1141 | for_each_set_bit(pde, new_pts, I915_PDES) |
a08e111a | 1142 | free_pt(dev, pd->page_table[pde]); |
7ad47cf2 | 1143 | |
d7b3de91 | 1144 | return -ENOMEM; |
bf2b4ed2 BW |
1145 | } |
1146 | ||
d7b2633d MT |
1147 | /** |
1148 | * gen8_ppgtt_alloc_page_directories() - Allocate page directories for VA range. | |
d4ec9da0 | 1149 | * @vm: Master vm structure. |
d7b2633d MT |
1150 | * @pdp: Page directory pointer for this address range. |
1151 | * @start: Starting virtual address to begin allocations. | |
d4ec9da0 MT |
1152 | * @length: Size of the allocations. |
1153 | * @new_pds: Bitmap set by function with new allocations. Likely used by the | |
d7b2633d MT |
1154 | * caller to free on error. |
1155 | * | |
1156 | * Allocate the required number of page directories starting at the pde index of | |
1157 | * @start, and ending at the pde index @start + @length. This function will skip | |
1158 | * over already allocated page directories within the range, and only allocate | |
1159 | * new ones, setting the appropriate pointer within the pdp as well as the | |
1160 | * correct position in the bitmap @new_pds. | |
1161 | * | |
1162 | * The function will only allocate the pages within the range for a give page | |
1163 | * directory pointer. In other words, if @start + @length straddles a virtually | |
1164 | * addressed PDP boundary (512GB for 4k pages), there will be more allocations | |
1165 | * required by the caller, This is not currently possible, and the BUG in the | |
1166 | * code will prevent it. | |
1167 | * | |
1168 | * Return: 0 if success; negative error code otherwise. | |
1169 | */ | |
d4ec9da0 MT |
1170 | static int |
1171 | gen8_ppgtt_alloc_page_directories(struct i915_address_space *vm, | |
1172 | struct i915_page_directory_pointer *pdp, | |
1173 | uint64_t start, | |
1174 | uint64_t length, | |
1175 | unsigned long *new_pds) | |
bf2b4ed2 | 1176 | { |
d4ec9da0 | 1177 | struct drm_device *dev = vm->dev; |
d7b2633d | 1178 | struct i915_page_directory *pd; |
69876bed | 1179 | uint32_t pdpe; |
6ac18502 | 1180 | uint32_t pdpes = I915_PDPES_PER_PDP(dev); |
69876bed | 1181 | |
6ac18502 | 1182 | WARN_ON(!bitmap_empty(new_pds, pdpes)); |
d7b2633d | 1183 | |
e8ebd8e2 | 1184 | gen8_for_each_pdpe(pd, pdp, start, length, pdpe) { |
6ac18502 | 1185 | if (test_bit(pdpe, pdp->used_pdpes)) |
d7b2633d | 1186 | continue; |
33c8819f | 1187 | |
8a1ebd74 | 1188 | pd = alloc_pd(dev); |
d7b2633d | 1189 | if (IS_ERR(pd)) |
d7b3de91 | 1190 | goto unwind_out; |
69876bed | 1191 | |
d4ec9da0 | 1192 | gen8_initialize_pd(vm, pd); |
d7b2633d | 1193 | pdp->page_directory[pdpe] = pd; |
966082c9 | 1194 | __set_bit(pdpe, new_pds); |
4c06ec8d | 1195 | trace_i915_page_directory_entry_alloc(vm, pdpe, start, GEN8_PDPE_SHIFT); |
d7b3de91 BW |
1196 | } |
1197 | ||
bf2b4ed2 | 1198 | return 0; |
d7b3de91 BW |
1199 | |
1200 | unwind_out: | |
6ac18502 | 1201 | for_each_set_bit(pdpe, new_pds, pdpes) |
a08e111a | 1202 | free_pd(dev, pdp->page_directory[pdpe]); |
d7b3de91 BW |
1203 | |
1204 | return -ENOMEM; | |
bf2b4ed2 BW |
1205 | } |
1206 | ||
762d9936 MT |
1207 | /** |
1208 | * gen8_ppgtt_alloc_page_dirpointers() - Allocate pdps for VA range. | |
1209 | * @vm: Master vm structure. | |
1210 | * @pml4: Page map level 4 for this address range. | |
1211 | * @start: Starting virtual address to begin allocations. | |
1212 | * @length: Size of the allocations. | |
1213 | * @new_pdps: Bitmap set by function with new allocations. Likely used by the | |
1214 | * caller to free on error. | |
1215 | * | |
1216 | * Allocate the required number of page directory pointers. Extremely similar to | |
1217 | * gen8_ppgtt_alloc_page_directories() and gen8_ppgtt_alloc_pagetabs(). | |
1218 | * The main difference is here we are limited by the pml4 boundary (instead of | |
1219 | * the page directory pointer). | |
1220 | * | |
1221 | * Return: 0 if success; negative error code otherwise. | |
1222 | */ | |
1223 | static int | |
1224 | gen8_ppgtt_alloc_page_dirpointers(struct i915_address_space *vm, | |
1225 | struct i915_pml4 *pml4, | |
1226 | uint64_t start, | |
1227 | uint64_t length, | |
1228 | unsigned long *new_pdps) | |
1229 | { | |
1230 | struct drm_device *dev = vm->dev; | |
1231 | struct i915_page_directory_pointer *pdp; | |
762d9936 MT |
1232 | uint32_t pml4e; |
1233 | ||
1234 | WARN_ON(!bitmap_empty(new_pdps, GEN8_PML4ES_PER_PML4)); | |
1235 | ||
e8ebd8e2 | 1236 | gen8_for_each_pml4e(pdp, pml4, start, length, pml4e) { |
762d9936 MT |
1237 | if (!test_bit(pml4e, pml4->used_pml4es)) { |
1238 | pdp = alloc_pdp(dev); | |
1239 | if (IS_ERR(pdp)) | |
1240 | goto unwind_out; | |
1241 | ||
69ab76fd | 1242 | gen8_initialize_pdp(vm, pdp); |
762d9936 MT |
1243 | pml4->pdps[pml4e] = pdp; |
1244 | __set_bit(pml4e, new_pdps); | |
1245 | trace_i915_page_directory_pointer_entry_alloc(vm, | |
1246 | pml4e, | |
1247 | start, | |
1248 | GEN8_PML4E_SHIFT); | |
1249 | } | |
1250 | } | |
1251 | ||
1252 | return 0; | |
1253 | ||
1254 | unwind_out: | |
1255 | for_each_set_bit(pml4e, new_pdps, GEN8_PML4ES_PER_PML4) | |
1256 | free_pdp(dev, pml4->pdps[pml4e]); | |
1257 | ||
1258 | return -ENOMEM; | |
1259 | } | |
1260 | ||
d7b2633d | 1261 | static void |
3a41a05d | 1262 | free_gen8_temp_bitmaps(unsigned long *new_pds, unsigned long *new_pts) |
d7b2633d | 1263 | { |
d7b2633d MT |
1264 | kfree(new_pts); |
1265 | kfree(new_pds); | |
1266 | } | |
1267 | ||
1268 | /* Fills in the page directory bitmap, and the array of page tables bitmap. Both | |
1269 | * of these are based on the number of PDPEs in the system. | |
1270 | */ | |
1271 | static | |
1272 | int __must_check alloc_gen8_temp_bitmaps(unsigned long **new_pds, | |
3a41a05d | 1273 | unsigned long **new_pts, |
6ac18502 | 1274 | uint32_t pdpes) |
d7b2633d | 1275 | { |
d7b2633d | 1276 | unsigned long *pds; |
3a41a05d | 1277 | unsigned long *pts; |
d7b2633d | 1278 | |
3a41a05d | 1279 | pds = kcalloc(BITS_TO_LONGS(pdpes), sizeof(unsigned long), GFP_TEMPORARY); |
d7b2633d MT |
1280 | if (!pds) |
1281 | return -ENOMEM; | |
1282 | ||
3a41a05d MW |
1283 | pts = kcalloc(pdpes, BITS_TO_LONGS(I915_PDES) * sizeof(unsigned long), |
1284 | GFP_TEMPORARY); | |
1285 | if (!pts) | |
1286 | goto err_out; | |
d7b2633d MT |
1287 | |
1288 | *new_pds = pds; | |
1289 | *new_pts = pts; | |
1290 | ||
1291 | return 0; | |
1292 | ||
1293 | err_out: | |
3a41a05d | 1294 | free_gen8_temp_bitmaps(pds, pts); |
d7b2633d MT |
1295 | return -ENOMEM; |
1296 | } | |
1297 | ||
762d9936 MT |
1298 | static int gen8_alloc_va_range_3lvl(struct i915_address_space *vm, |
1299 | struct i915_page_directory_pointer *pdp, | |
1300 | uint64_t start, | |
1301 | uint64_t length) | |
bf2b4ed2 | 1302 | { |
e5716f55 | 1303 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
3a41a05d | 1304 | unsigned long *new_page_dirs, *new_page_tables; |
d4ec9da0 | 1305 | struct drm_device *dev = vm->dev; |
5441f0cb | 1306 | struct i915_page_directory *pd; |
33c8819f MT |
1307 | const uint64_t orig_start = start; |
1308 | const uint64_t orig_length = length; | |
5441f0cb | 1309 | uint32_t pdpe; |
d4ec9da0 | 1310 | uint32_t pdpes = I915_PDPES_PER_PDP(dev); |
bf2b4ed2 BW |
1311 | int ret; |
1312 | ||
d7b2633d MT |
1313 | /* Wrap is never okay since we can only represent 48b, and we don't |
1314 | * actually use the other side of the canonical address space. | |
1315 | */ | |
1316 | if (WARN_ON(start + length < start)) | |
a05d80ee MK |
1317 | return -ENODEV; |
1318 | ||
d4ec9da0 | 1319 | if (WARN_ON(start + length > vm->total)) |
a05d80ee | 1320 | return -ENODEV; |
d7b2633d | 1321 | |
6ac18502 | 1322 | ret = alloc_gen8_temp_bitmaps(&new_page_dirs, &new_page_tables, pdpes); |
bf2b4ed2 BW |
1323 | if (ret) |
1324 | return ret; | |
1325 | ||
d7b2633d | 1326 | /* Do the allocations first so we can easily bail out */ |
d4ec9da0 MT |
1327 | ret = gen8_ppgtt_alloc_page_directories(vm, pdp, start, length, |
1328 | new_page_dirs); | |
d7b2633d | 1329 | if (ret) { |
3a41a05d | 1330 | free_gen8_temp_bitmaps(new_page_dirs, new_page_tables); |
d7b2633d MT |
1331 | return ret; |
1332 | } | |
1333 | ||
1334 | /* For every page directory referenced, allocate page tables */ | |
e8ebd8e2 | 1335 | gen8_for_each_pdpe(pd, pdp, start, length, pdpe) { |
d4ec9da0 | 1336 | ret = gen8_ppgtt_alloc_pagetabs(vm, pd, start, length, |
3a41a05d | 1337 | new_page_tables + pdpe * BITS_TO_LONGS(I915_PDES)); |
5441f0cb MT |
1338 | if (ret) |
1339 | goto err_out; | |
5441f0cb MT |
1340 | } |
1341 | ||
33c8819f MT |
1342 | start = orig_start; |
1343 | length = orig_length; | |
1344 | ||
d7b2633d MT |
1345 | /* Allocations have completed successfully, so set the bitmaps, and do |
1346 | * the mappings. */ | |
e8ebd8e2 | 1347 | gen8_for_each_pdpe(pd, pdp, start, length, pdpe) { |
d1c54acd | 1348 | gen8_pde_t *const page_directory = kmap_px(pd); |
33c8819f | 1349 | struct i915_page_table *pt; |
09120d4e | 1350 | uint64_t pd_len = length; |
33c8819f MT |
1351 | uint64_t pd_start = start; |
1352 | uint32_t pde; | |
1353 | ||
d7b2633d MT |
1354 | /* Every pd should be allocated, we just did that above. */ |
1355 | WARN_ON(!pd); | |
1356 | ||
e8ebd8e2 | 1357 | gen8_for_each_pde(pt, pd, pd_start, pd_len, pde) { |
d7b2633d MT |
1358 | /* Same reasoning as pd */ |
1359 | WARN_ON(!pt); | |
1360 | WARN_ON(!pd_len); | |
1361 | WARN_ON(!gen8_pte_count(pd_start, pd_len)); | |
1362 | ||
1363 | /* Set our used ptes within the page table */ | |
1364 | bitmap_set(pt->used_ptes, | |
1365 | gen8_pte_index(pd_start), | |
1366 | gen8_pte_count(pd_start, pd_len)); | |
1367 | ||
1368 | /* Our pde is now pointing to the pagetable, pt */ | |
966082c9 | 1369 | __set_bit(pde, pd->used_pdes); |
d7b2633d MT |
1370 | |
1371 | /* Map the PDE to the page table */ | |
fe36f55d MK |
1372 | page_directory[pde] = gen8_pde_encode(px_dma(pt), |
1373 | I915_CACHE_LLC); | |
4c06ec8d MT |
1374 | trace_i915_page_table_entry_map(&ppgtt->base, pde, pt, |
1375 | gen8_pte_index(start), | |
1376 | gen8_pte_count(start, length), | |
1377 | GEN8_PTES); | |
d7b2633d MT |
1378 | |
1379 | /* NB: We haven't yet mapped ptes to pages. At this | |
1380 | * point we're still relying on insert_entries() */ | |
33c8819f | 1381 | } |
d7b2633d | 1382 | |
d1c54acd | 1383 | kunmap_px(ppgtt, page_directory); |
d4ec9da0 | 1384 | __set_bit(pdpe, pdp->used_pdpes); |
762d9936 | 1385 | gen8_setup_page_directory(ppgtt, pdp, pd, pdpe); |
33c8819f MT |
1386 | } |
1387 | ||
3a41a05d | 1388 | free_gen8_temp_bitmaps(new_page_dirs, new_page_tables); |
5b7e4c9c | 1389 | mark_tlbs_dirty(ppgtt); |
d7b3de91 | 1390 | return 0; |
bf2b4ed2 | 1391 | |
d7b3de91 | 1392 | err_out: |
d7b2633d | 1393 | while (pdpe--) { |
e8ebd8e2 DG |
1394 | unsigned long temp; |
1395 | ||
3a41a05d MW |
1396 | for_each_set_bit(temp, new_page_tables + pdpe * |
1397 | BITS_TO_LONGS(I915_PDES), I915_PDES) | |
d4ec9da0 | 1398 | free_pt(dev, pdp->page_directory[pdpe]->page_table[temp]); |
d7b2633d MT |
1399 | } |
1400 | ||
6ac18502 | 1401 | for_each_set_bit(pdpe, new_page_dirs, pdpes) |
d4ec9da0 | 1402 | free_pd(dev, pdp->page_directory[pdpe]); |
d7b2633d | 1403 | |
3a41a05d | 1404 | free_gen8_temp_bitmaps(new_page_dirs, new_page_tables); |
5b7e4c9c | 1405 | mark_tlbs_dirty(ppgtt); |
bf2b4ed2 BW |
1406 | return ret; |
1407 | } | |
1408 | ||
762d9936 MT |
1409 | static int gen8_alloc_va_range_4lvl(struct i915_address_space *vm, |
1410 | struct i915_pml4 *pml4, | |
1411 | uint64_t start, | |
1412 | uint64_t length) | |
1413 | { | |
1414 | DECLARE_BITMAP(new_pdps, GEN8_PML4ES_PER_PML4); | |
e5716f55 | 1415 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
762d9936 | 1416 | struct i915_page_directory_pointer *pdp; |
e8ebd8e2 | 1417 | uint64_t pml4e; |
762d9936 MT |
1418 | int ret = 0; |
1419 | ||
1420 | /* Do the pml4 allocations first, so we don't need to track the newly | |
1421 | * allocated tables below the pdp */ | |
1422 | bitmap_zero(new_pdps, GEN8_PML4ES_PER_PML4); | |
1423 | ||
1424 | /* The pagedirectory and pagetable allocations are done in the shared 3 | |
1425 | * and 4 level code. Just allocate the pdps. | |
1426 | */ | |
1427 | ret = gen8_ppgtt_alloc_page_dirpointers(vm, pml4, start, length, | |
1428 | new_pdps); | |
1429 | if (ret) | |
1430 | return ret; | |
1431 | ||
1432 | WARN(bitmap_weight(new_pdps, GEN8_PML4ES_PER_PML4) > 2, | |
1433 | "The allocation has spanned more than 512GB. " | |
1434 | "It is highly likely this is incorrect."); | |
1435 | ||
e8ebd8e2 | 1436 | gen8_for_each_pml4e(pdp, pml4, start, length, pml4e) { |
762d9936 MT |
1437 | WARN_ON(!pdp); |
1438 | ||
1439 | ret = gen8_alloc_va_range_3lvl(vm, pdp, start, length); | |
1440 | if (ret) | |
1441 | goto err_out; | |
1442 | ||
1443 | gen8_setup_page_directory_pointer(ppgtt, pml4, pdp, pml4e); | |
1444 | } | |
1445 | ||
1446 | bitmap_or(pml4->used_pml4es, new_pdps, pml4->used_pml4es, | |
1447 | GEN8_PML4ES_PER_PML4); | |
1448 | ||
1449 | return 0; | |
1450 | ||
1451 | err_out: | |
1452 | for_each_set_bit(pml4e, new_pdps, GEN8_PML4ES_PER_PML4) | |
1453 | gen8_ppgtt_cleanup_3lvl(vm->dev, pml4->pdps[pml4e]); | |
1454 | ||
1455 | return ret; | |
1456 | } | |
1457 | ||
1458 | static int gen8_alloc_va_range(struct i915_address_space *vm, | |
1459 | uint64_t start, uint64_t length) | |
1460 | { | |
e5716f55 | 1461 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
762d9936 MT |
1462 | |
1463 | if (USES_FULL_48BIT_PPGTT(vm->dev)) | |
1464 | return gen8_alloc_va_range_4lvl(vm, &ppgtt->pml4, start, length); | |
1465 | else | |
1466 | return gen8_alloc_va_range_3lvl(vm, &ppgtt->pdp, start, length); | |
1467 | } | |
1468 | ||
ea91e401 MT |
1469 | static void gen8_dump_pdp(struct i915_page_directory_pointer *pdp, |
1470 | uint64_t start, uint64_t length, | |
1471 | gen8_pte_t scratch_pte, | |
1472 | struct seq_file *m) | |
1473 | { | |
1474 | struct i915_page_directory *pd; | |
ea91e401 MT |
1475 | uint32_t pdpe; |
1476 | ||
e8ebd8e2 | 1477 | gen8_for_each_pdpe(pd, pdp, start, length, pdpe) { |
ea91e401 MT |
1478 | struct i915_page_table *pt; |
1479 | uint64_t pd_len = length; | |
1480 | uint64_t pd_start = start; | |
1481 | uint32_t pde; | |
1482 | ||
1483 | if (!test_bit(pdpe, pdp->used_pdpes)) | |
1484 | continue; | |
1485 | ||
1486 | seq_printf(m, "\tPDPE #%d\n", pdpe); | |
e8ebd8e2 | 1487 | gen8_for_each_pde(pt, pd, pd_start, pd_len, pde) { |
ea91e401 MT |
1488 | uint32_t pte; |
1489 | gen8_pte_t *pt_vaddr; | |
1490 | ||
1491 | if (!test_bit(pde, pd->used_pdes)) | |
1492 | continue; | |
1493 | ||
1494 | pt_vaddr = kmap_px(pt); | |
1495 | for (pte = 0; pte < GEN8_PTES; pte += 4) { | |
1496 | uint64_t va = | |
1497 | (pdpe << GEN8_PDPE_SHIFT) | | |
1498 | (pde << GEN8_PDE_SHIFT) | | |
1499 | (pte << GEN8_PTE_SHIFT); | |
1500 | int i; | |
1501 | bool found = false; | |
1502 | ||
1503 | for (i = 0; i < 4; i++) | |
1504 | if (pt_vaddr[pte + i] != scratch_pte) | |
1505 | found = true; | |
1506 | if (!found) | |
1507 | continue; | |
1508 | ||
1509 | seq_printf(m, "\t\t0x%llx [%03d,%03d,%04d]: =", va, pdpe, pde, pte); | |
1510 | for (i = 0; i < 4; i++) { | |
1511 | if (pt_vaddr[pte + i] != scratch_pte) | |
1512 | seq_printf(m, " %llx", pt_vaddr[pte + i]); | |
1513 | else | |
1514 | seq_puts(m, " SCRATCH "); | |
1515 | } | |
1516 | seq_puts(m, "\n"); | |
1517 | } | |
1518 | /* don't use kunmap_px, it could trigger | |
1519 | * an unnecessary flush. | |
1520 | */ | |
1521 | kunmap_atomic(pt_vaddr); | |
1522 | } | |
1523 | } | |
1524 | } | |
1525 | ||
1526 | static void gen8_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m) | |
1527 | { | |
1528 | struct i915_address_space *vm = &ppgtt->base; | |
1529 | uint64_t start = ppgtt->base.start; | |
1530 | uint64_t length = ppgtt->base.total; | |
8bcdd0f7 | 1531 | gen8_pte_t scratch_pte = gen8_pte_encode(vm->scratch_page.daddr, |
4fb84d99 | 1532 | I915_CACHE_LLC); |
ea91e401 MT |
1533 | |
1534 | if (!USES_FULL_48BIT_PPGTT(vm->dev)) { | |
1535 | gen8_dump_pdp(&ppgtt->pdp, start, length, scratch_pte, m); | |
1536 | } else { | |
e8ebd8e2 | 1537 | uint64_t pml4e; |
ea91e401 MT |
1538 | struct i915_pml4 *pml4 = &ppgtt->pml4; |
1539 | struct i915_page_directory_pointer *pdp; | |
1540 | ||
e8ebd8e2 | 1541 | gen8_for_each_pml4e(pdp, pml4, start, length, pml4e) { |
ea91e401 MT |
1542 | if (!test_bit(pml4e, pml4->used_pml4es)) |
1543 | continue; | |
1544 | ||
1545 | seq_printf(m, " PML4E #%llu\n", pml4e); | |
1546 | gen8_dump_pdp(pdp, start, length, scratch_pte, m); | |
1547 | } | |
1548 | } | |
1549 | } | |
1550 | ||
331f38e7 ZL |
1551 | static int gen8_preallocate_top_level_pdps(struct i915_hw_ppgtt *ppgtt) |
1552 | { | |
3a41a05d | 1553 | unsigned long *new_page_dirs, *new_page_tables; |
331f38e7 ZL |
1554 | uint32_t pdpes = I915_PDPES_PER_PDP(dev); |
1555 | int ret; | |
1556 | ||
1557 | /* We allocate temp bitmap for page tables for no gain | |
1558 | * but as this is for init only, lets keep the things simple | |
1559 | */ | |
1560 | ret = alloc_gen8_temp_bitmaps(&new_page_dirs, &new_page_tables, pdpes); | |
1561 | if (ret) | |
1562 | return ret; | |
1563 | ||
1564 | /* Allocate for all pdps regardless of how the ppgtt | |
1565 | * was defined. | |
1566 | */ | |
1567 | ret = gen8_ppgtt_alloc_page_directories(&ppgtt->base, &ppgtt->pdp, | |
1568 | 0, 1ULL << 32, | |
1569 | new_page_dirs); | |
1570 | if (!ret) | |
1571 | *ppgtt->pdp.used_pdpes = *new_page_dirs; | |
1572 | ||
3a41a05d | 1573 | free_gen8_temp_bitmaps(new_page_dirs, new_page_tables); |
331f38e7 ZL |
1574 | |
1575 | return ret; | |
1576 | } | |
1577 | ||
eb0b44ad | 1578 | /* |
f3a964b9 BW |
1579 | * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers |
1580 | * with a net effect resembling a 2-level page table in normal x86 terms. Each | |
1581 | * PDP represents 1GB of memory 4 * 512 * 512 * 4096 = 4GB legacy 32b address | |
1582 | * space. | |
37aca44a | 1583 | * |
f3a964b9 | 1584 | */ |
5c5f6457 | 1585 | static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt) |
37aca44a | 1586 | { |
8776f02b | 1587 | int ret; |
7cb6d7ac | 1588 | |
8776f02b MK |
1589 | ret = gen8_init_scratch(&ppgtt->base); |
1590 | if (ret) | |
1591 | return ret; | |
69876bed | 1592 | |
d7b2633d | 1593 | ppgtt->base.start = 0; |
d7b2633d | 1594 | ppgtt->base.cleanup = gen8_ppgtt_cleanup; |
5c5f6457 | 1595 | ppgtt->base.allocate_va_range = gen8_alloc_va_range; |
d7b2633d | 1596 | ppgtt->base.insert_entries = gen8_ppgtt_insert_entries; |
c7e16f22 | 1597 | ppgtt->base.clear_range = gen8_ppgtt_clear_range; |
777dc5bb DV |
1598 | ppgtt->base.unbind_vma = ppgtt_unbind_vma; |
1599 | ppgtt->base.bind_vma = ppgtt_bind_vma; | |
ea91e401 | 1600 | ppgtt->debug_dump = gen8_dump_ppgtt; |
d7b2633d | 1601 | |
762d9936 MT |
1602 | if (USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) { |
1603 | ret = setup_px(ppgtt->base.dev, &ppgtt->pml4); | |
1604 | if (ret) | |
1605 | goto free_scratch; | |
6ac18502 | 1606 | |
69ab76fd MT |
1607 | gen8_initialize_pml4(&ppgtt->base, &ppgtt->pml4); |
1608 | ||
762d9936 | 1609 | ppgtt->base.total = 1ULL << 48; |
2dba3239 | 1610 | ppgtt->switch_mm = gen8_48b_mm_switch; |
762d9936 | 1611 | } else { |
25f50337 | 1612 | ret = __pdp_init(ppgtt->base.dev, &ppgtt->pdp); |
81ba8aef MT |
1613 | if (ret) |
1614 | goto free_scratch; | |
1615 | ||
1616 | ppgtt->base.total = 1ULL << 32; | |
2dba3239 | 1617 | ppgtt->switch_mm = gen8_legacy_mm_switch; |
762d9936 MT |
1618 | trace_i915_page_directory_pointer_entry_alloc(&ppgtt->base, |
1619 | 0, 0, | |
1620 | GEN8_PML4E_SHIFT); | |
331f38e7 | 1621 | |
c033666a | 1622 | if (intel_vgpu_active(to_i915(ppgtt->base.dev))) { |
331f38e7 ZL |
1623 | ret = gen8_preallocate_top_level_pdps(ppgtt); |
1624 | if (ret) | |
1625 | goto free_scratch; | |
1626 | } | |
81ba8aef | 1627 | } |
6ac18502 | 1628 | |
c033666a | 1629 | if (intel_vgpu_active(to_i915(ppgtt->base.dev))) |
650da34c ZL |
1630 | gen8_ppgtt_notify_vgt(ppgtt, true); |
1631 | ||
d7b2633d | 1632 | return 0; |
6ac18502 MT |
1633 | |
1634 | free_scratch: | |
1635 | gen8_free_scratch(&ppgtt->base); | |
1636 | return ret; | |
d7b2633d MT |
1637 | } |
1638 | ||
87d60b63 BW |
1639 | static void gen6_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m) |
1640 | { | |
87d60b63 | 1641 | struct i915_address_space *vm = &ppgtt->base; |
09942c65 | 1642 | struct i915_page_table *unused; |
07749ef3 | 1643 | gen6_pte_t scratch_pte; |
87d60b63 | 1644 | uint32_t pd_entry; |
731f74c5 | 1645 | uint32_t pte, pde; |
09942c65 | 1646 | uint32_t start = ppgtt->base.start, length = ppgtt->base.total; |
87d60b63 | 1647 | |
8bcdd0f7 | 1648 | scratch_pte = vm->pte_encode(vm->scratch_page.daddr, |
4fb84d99 | 1649 | I915_CACHE_LLC, 0); |
87d60b63 | 1650 | |
731f74c5 | 1651 | gen6_for_each_pde(unused, &ppgtt->pd, start, length, pde) { |
87d60b63 | 1652 | u32 expected; |
07749ef3 | 1653 | gen6_pte_t *pt_vaddr; |
567047be | 1654 | const dma_addr_t pt_addr = px_dma(ppgtt->pd.page_table[pde]); |
09942c65 | 1655 | pd_entry = readl(ppgtt->pd_addr + pde); |
87d60b63 BW |
1656 | expected = (GEN6_PDE_ADDR_ENCODE(pt_addr) | GEN6_PDE_VALID); |
1657 | ||
1658 | if (pd_entry != expected) | |
1659 | seq_printf(m, "\tPDE #%d mismatch: Actual PDE: %x Expected PDE: %x\n", | |
1660 | pde, | |
1661 | pd_entry, | |
1662 | expected); | |
1663 | seq_printf(m, "\tPDE: %x\n", pd_entry); | |
1664 | ||
d1c54acd MK |
1665 | pt_vaddr = kmap_px(ppgtt->pd.page_table[pde]); |
1666 | ||
07749ef3 | 1667 | for (pte = 0; pte < GEN6_PTES; pte+=4) { |
87d60b63 | 1668 | unsigned long va = |
07749ef3 | 1669 | (pde * PAGE_SIZE * GEN6_PTES) + |
87d60b63 BW |
1670 | (pte * PAGE_SIZE); |
1671 | int i; | |
1672 | bool found = false; | |
1673 | for (i = 0; i < 4; i++) | |
1674 | if (pt_vaddr[pte + i] != scratch_pte) | |
1675 | found = true; | |
1676 | if (!found) | |
1677 | continue; | |
1678 | ||
1679 | seq_printf(m, "\t\t0x%lx [%03d,%04d]: =", va, pde, pte); | |
1680 | for (i = 0; i < 4; i++) { | |
1681 | if (pt_vaddr[pte + i] != scratch_pte) | |
1682 | seq_printf(m, " %08x", pt_vaddr[pte + i]); | |
1683 | else | |
1684 | seq_puts(m, " SCRATCH "); | |
1685 | } | |
1686 | seq_puts(m, "\n"); | |
1687 | } | |
d1c54acd | 1688 | kunmap_px(ppgtt, pt_vaddr); |
87d60b63 BW |
1689 | } |
1690 | } | |
1691 | ||
678d96fb | 1692 | /* Write pde (index) from the page directory @pd to the page table @pt */ |
ec565b3c MT |
1693 | static void gen6_write_pde(struct i915_page_directory *pd, |
1694 | const int pde, struct i915_page_table *pt) | |
6197349b | 1695 | { |
678d96fb BW |
1696 | /* Caller needs to make sure the write completes if necessary */ |
1697 | struct i915_hw_ppgtt *ppgtt = | |
1698 | container_of(pd, struct i915_hw_ppgtt, pd); | |
1699 | u32 pd_entry; | |
6197349b | 1700 | |
567047be | 1701 | pd_entry = GEN6_PDE_ADDR_ENCODE(px_dma(pt)); |
678d96fb | 1702 | pd_entry |= GEN6_PDE_VALID; |
6197349b | 1703 | |
678d96fb BW |
1704 | writel(pd_entry, ppgtt->pd_addr + pde); |
1705 | } | |
6197349b | 1706 | |
678d96fb BW |
1707 | /* Write all the page tables found in the ppgtt structure to incrementing page |
1708 | * directories. */ | |
1709 | static void gen6_write_page_range(struct drm_i915_private *dev_priv, | |
ec565b3c | 1710 | struct i915_page_directory *pd, |
678d96fb BW |
1711 | uint32_t start, uint32_t length) |
1712 | { | |
72e96d64 | 1713 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
ec565b3c | 1714 | struct i915_page_table *pt; |
731f74c5 | 1715 | uint32_t pde; |
678d96fb | 1716 | |
731f74c5 | 1717 | gen6_for_each_pde(pt, pd, start, length, pde) |
678d96fb BW |
1718 | gen6_write_pde(pd, pde, pt); |
1719 | ||
1720 | /* Make sure write is complete before other code can use this page | |
1721 | * table. Also require for WC mapped PTEs */ | |
72e96d64 | 1722 | readl(ggtt->gsm); |
3e302542 BW |
1723 | } |
1724 | ||
b4a74e3a | 1725 | static uint32_t get_pd_offset(struct i915_hw_ppgtt *ppgtt) |
3e302542 | 1726 | { |
44159ddb | 1727 | BUG_ON(ppgtt->pd.base.ggtt_offset & 0x3f); |
b4a74e3a | 1728 | |
44159ddb | 1729 | return (ppgtt->pd.base.ggtt_offset / 64) << 16; |
b4a74e3a BW |
1730 | } |
1731 | ||
90252e5c | 1732 | static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt, |
e85b26dc | 1733 | struct drm_i915_gem_request *req) |
90252e5c | 1734 | { |
7e37f889 | 1735 | struct intel_ring *ring = req->ring; |
4a570db5 | 1736 | struct intel_engine_cs *engine = req->engine; |
90252e5c BW |
1737 | int ret; |
1738 | ||
90252e5c | 1739 | /* NB: TLBs must be flushed and invalidated before a switch */ |
7c9cf4e3 | 1740 | ret = engine->emit_flush(req, EMIT_INVALIDATE | EMIT_FLUSH); |
90252e5c BW |
1741 | if (ret) |
1742 | return ret; | |
1743 | ||
5fb9de1a | 1744 | ret = intel_ring_begin(req, 6); |
90252e5c BW |
1745 | if (ret) |
1746 | return ret; | |
1747 | ||
b5321f30 CW |
1748 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2)); |
1749 | intel_ring_emit_reg(ring, RING_PP_DIR_DCLV(engine)); | |
1750 | intel_ring_emit(ring, PP_DIR_DCLV_2G); | |
1751 | intel_ring_emit_reg(ring, RING_PP_DIR_BASE(engine)); | |
1752 | intel_ring_emit(ring, get_pd_offset(ppgtt)); | |
1753 | intel_ring_emit(ring, MI_NOOP); | |
1754 | intel_ring_advance(ring); | |
90252e5c BW |
1755 | |
1756 | return 0; | |
1757 | } | |
1758 | ||
48a10389 | 1759 | static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt, |
e85b26dc | 1760 | struct drm_i915_gem_request *req) |
48a10389 | 1761 | { |
7e37f889 | 1762 | struct intel_ring *ring = req->ring; |
4a570db5 | 1763 | struct intel_engine_cs *engine = req->engine; |
48a10389 BW |
1764 | int ret; |
1765 | ||
48a10389 | 1766 | /* NB: TLBs must be flushed and invalidated before a switch */ |
7c9cf4e3 | 1767 | ret = engine->emit_flush(req, EMIT_INVALIDATE | EMIT_FLUSH); |
48a10389 BW |
1768 | if (ret) |
1769 | return ret; | |
1770 | ||
5fb9de1a | 1771 | ret = intel_ring_begin(req, 6); |
48a10389 BW |
1772 | if (ret) |
1773 | return ret; | |
1774 | ||
b5321f30 CW |
1775 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2)); |
1776 | intel_ring_emit_reg(ring, RING_PP_DIR_DCLV(engine)); | |
1777 | intel_ring_emit(ring, PP_DIR_DCLV_2G); | |
1778 | intel_ring_emit_reg(ring, RING_PP_DIR_BASE(engine)); | |
1779 | intel_ring_emit(ring, get_pd_offset(ppgtt)); | |
1780 | intel_ring_emit(ring, MI_NOOP); | |
1781 | intel_ring_advance(ring); | |
48a10389 | 1782 | |
90252e5c | 1783 | /* XXX: RCS is the only one to auto invalidate the TLBs? */ |
e2f80391 | 1784 | if (engine->id != RCS) { |
7c9cf4e3 | 1785 | ret = engine->emit_flush(req, EMIT_INVALIDATE | EMIT_FLUSH); |
90252e5c BW |
1786 | if (ret) |
1787 | return ret; | |
1788 | } | |
1789 | ||
48a10389 BW |
1790 | return 0; |
1791 | } | |
1792 | ||
eeb9488e | 1793 | static int gen6_mm_switch(struct i915_hw_ppgtt *ppgtt, |
e85b26dc | 1794 | struct drm_i915_gem_request *req) |
eeb9488e | 1795 | { |
4a570db5 | 1796 | struct intel_engine_cs *engine = req->engine; |
8eb95204 | 1797 | struct drm_i915_private *dev_priv = req->i915; |
48a10389 | 1798 | |
e2f80391 TU |
1799 | I915_WRITE(RING_PP_DIR_DCLV(engine), PP_DIR_DCLV_2G); |
1800 | I915_WRITE(RING_PP_DIR_BASE(engine), get_pd_offset(ppgtt)); | |
eeb9488e BW |
1801 | return 0; |
1802 | } | |
1803 | ||
82460d97 | 1804 | static void gen8_ppgtt_enable(struct drm_device *dev) |
eeb9488e | 1805 | { |
fac5e23e | 1806 | struct drm_i915_private *dev_priv = to_i915(dev); |
e2f80391 | 1807 | struct intel_engine_cs *engine; |
3b3f1650 | 1808 | enum intel_engine_id id; |
3e302542 | 1809 | |
3b3f1650 | 1810 | for_each_engine(engine, dev_priv, id) { |
2dba3239 | 1811 | u32 four_level = USES_FULL_48BIT_PPGTT(dev) ? GEN8_GFX_PPGTT_48B : 0; |
e2f80391 | 1812 | I915_WRITE(RING_MODE_GEN7(engine), |
2dba3239 | 1813 | _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE | four_level)); |
eeb9488e | 1814 | } |
eeb9488e | 1815 | } |
6197349b | 1816 | |
82460d97 | 1817 | static void gen7_ppgtt_enable(struct drm_device *dev) |
3e302542 | 1818 | { |
fac5e23e | 1819 | struct drm_i915_private *dev_priv = to_i915(dev); |
e2f80391 | 1820 | struct intel_engine_cs *engine; |
b4a74e3a | 1821 | uint32_t ecochk, ecobits; |
3b3f1650 | 1822 | enum intel_engine_id id; |
6197349b | 1823 | |
b4a74e3a BW |
1824 | ecobits = I915_READ(GAC_ECO_BITS); |
1825 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B); | |
a65c2fcd | 1826 | |
b4a74e3a | 1827 | ecochk = I915_READ(GAM_ECOCHK); |
772c2a51 | 1828 | if (IS_HASWELL(dev_priv)) { |
b4a74e3a BW |
1829 | ecochk |= ECOCHK_PPGTT_WB_HSW; |
1830 | } else { | |
1831 | ecochk |= ECOCHK_PPGTT_LLC_IVB; | |
1832 | ecochk &= ~ECOCHK_PPGTT_GFDT_IVB; | |
1833 | } | |
1834 | I915_WRITE(GAM_ECOCHK, ecochk); | |
a65c2fcd | 1835 | |
3b3f1650 | 1836 | for_each_engine(engine, dev_priv, id) { |
6197349b | 1837 | /* GFX_MODE is per-ring on gen7+ */ |
e2f80391 | 1838 | I915_WRITE(RING_MODE_GEN7(engine), |
b4a74e3a | 1839 | _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); |
6197349b | 1840 | } |
b4a74e3a | 1841 | } |
6197349b | 1842 | |
82460d97 | 1843 | static void gen6_ppgtt_enable(struct drm_device *dev) |
b4a74e3a | 1844 | { |
fac5e23e | 1845 | struct drm_i915_private *dev_priv = to_i915(dev); |
b4a74e3a | 1846 | uint32_t ecochk, gab_ctl, ecobits; |
a65c2fcd | 1847 | |
b4a74e3a BW |
1848 | ecobits = I915_READ(GAC_ECO_BITS); |
1849 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT | | |
1850 | ECOBITS_PPGTT_CACHE64B); | |
6197349b | 1851 | |
b4a74e3a BW |
1852 | gab_ctl = I915_READ(GAB_CTL); |
1853 | I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT); | |
1854 | ||
1855 | ecochk = I915_READ(GAM_ECOCHK); | |
1856 | I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B); | |
1857 | ||
1858 | I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
6197349b BW |
1859 | } |
1860 | ||
1d2a314c | 1861 | /* PPGTT support for Sandybdrige/Gen6 and later */ |
853ba5d2 | 1862 | static void gen6_ppgtt_clear_range(struct i915_address_space *vm, |
782f1495 | 1863 | uint64_t start, |
4fb84d99 | 1864 | uint64_t length) |
1d2a314c | 1865 | { |
e5716f55 | 1866 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
07749ef3 | 1867 | gen6_pte_t *pt_vaddr, scratch_pte; |
782f1495 BW |
1868 | unsigned first_entry = start >> PAGE_SHIFT; |
1869 | unsigned num_entries = length >> PAGE_SHIFT; | |
07749ef3 MT |
1870 | unsigned act_pt = first_entry / GEN6_PTES; |
1871 | unsigned first_pte = first_entry % GEN6_PTES; | |
7bddb01f | 1872 | unsigned last_pte, i; |
1d2a314c | 1873 | |
8bcdd0f7 | 1874 | scratch_pte = vm->pte_encode(vm->scratch_page.daddr, |
4fb84d99 | 1875 | I915_CACHE_LLC, 0); |
1d2a314c | 1876 | |
7bddb01f DV |
1877 | while (num_entries) { |
1878 | last_pte = first_pte + num_entries; | |
07749ef3 MT |
1879 | if (last_pte > GEN6_PTES) |
1880 | last_pte = GEN6_PTES; | |
7bddb01f | 1881 | |
d1c54acd | 1882 | pt_vaddr = kmap_px(ppgtt->pd.page_table[act_pt]); |
1d2a314c | 1883 | |
7bddb01f DV |
1884 | for (i = first_pte; i < last_pte; i++) |
1885 | pt_vaddr[i] = scratch_pte; | |
1d2a314c | 1886 | |
d1c54acd | 1887 | kunmap_px(ppgtt, pt_vaddr); |
1d2a314c | 1888 | |
7bddb01f DV |
1889 | num_entries -= last_pte - first_pte; |
1890 | first_pte = 0; | |
a15326a5 | 1891 | act_pt++; |
7bddb01f | 1892 | } |
1d2a314c DV |
1893 | } |
1894 | ||
853ba5d2 | 1895 | static void gen6_ppgtt_insert_entries(struct i915_address_space *vm, |
def886c3 | 1896 | struct sg_table *pages, |
782f1495 | 1897 | uint64_t start, |
24f3a8cf | 1898 | enum i915_cache_level cache_level, u32 flags) |
def886c3 | 1899 | { |
e5716f55 | 1900 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
782f1495 | 1901 | unsigned first_entry = start >> PAGE_SHIFT; |
07749ef3 MT |
1902 | unsigned act_pt = first_entry / GEN6_PTES; |
1903 | unsigned act_pte = first_entry % GEN6_PTES; | |
85d1225e DG |
1904 | gen6_pte_t *pt_vaddr = NULL; |
1905 | struct sgt_iter sgt_iter; | |
1906 | dma_addr_t addr; | |
6e995e23 | 1907 | |
85d1225e | 1908 | for_each_sgt_dma(addr, sgt_iter, pages) { |
cc79714f | 1909 | if (pt_vaddr == NULL) |
d1c54acd | 1910 | pt_vaddr = kmap_px(ppgtt->pd.page_table[act_pt]); |
6e995e23 | 1911 | |
cc79714f | 1912 | pt_vaddr[act_pte] = |
4fb84d99 | 1913 | vm->pte_encode(addr, cache_level, flags); |
24f3a8cf | 1914 | |
07749ef3 | 1915 | if (++act_pte == GEN6_PTES) { |
d1c54acd | 1916 | kunmap_px(ppgtt, pt_vaddr); |
cc79714f | 1917 | pt_vaddr = NULL; |
a15326a5 | 1918 | act_pt++; |
6e995e23 | 1919 | act_pte = 0; |
def886c3 | 1920 | } |
def886c3 | 1921 | } |
85d1225e | 1922 | |
cc79714f | 1923 | if (pt_vaddr) |
d1c54acd | 1924 | kunmap_px(ppgtt, pt_vaddr); |
def886c3 DV |
1925 | } |
1926 | ||
678d96fb | 1927 | static int gen6_alloc_va_range(struct i915_address_space *vm, |
a05d80ee | 1928 | uint64_t start_in, uint64_t length_in) |
678d96fb | 1929 | { |
4933d519 MT |
1930 | DECLARE_BITMAP(new_page_tables, I915_PDES); |
1931 | struct drm_device *dev = vm->dev; | |
72e96d64 JL |
1932 | struct drm_i915_private *dev_priv = to_i915(dev); |
1933 | struct i915_ggtt *ggtt = &dev_priv->ggtt; | |
e5716f55 | 1934 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
ec565b3c | 1935 | struct i915_page_table *pt; |
a05d80ee | 1936 | uint32_t start, length, start_save, length_save; |
731f74c5 | 1937 | uint32_t pde; |
4933d519 MT |
1938 | int ret; |
1939 | ||
a05d80ee MK |
1940 | if (WARN_ON(start_in + length_in > ppgtt->base.total)) |
1941 | return -ENODEV; | |
1942 | ||
1943 | start = start_save = start_in; | |
1944 | length = length_save = length_in; | |
4933d519 MT |
1945 | |
1946 | bitmap_zero(new_page_tables, I915_PDES); | |
1947 | ||
1948 | /* The allocation is done in two stages so that we can bail out with | |
1949 | * minimal amount of pain. The first stage finds new page tables that | |
1950 | * need allocation. The second stage marks use ptes within the page | |
1951 | * tables. | |
1952 | */ | |
731f74c5 | 1953 | gen6_for_each_pde(pt, &ppgtt->pd, start, length, pde) { |
79ab9370 | 1954 | if (pt != vm->scratch_pt) { |
4933d519 MT |
1955 | WARN_ON(bitmap_empty(pt->used_ptes, GEN6_PTES)); |
1956 | continue; | |
1957 | } | |
1958 | ||
1959 | /* We've already allocated a page table */ | |
1960 | WARN_ON(!bitmap_empty(pt->used_ptes, GEN6_PTES)); | |
1961 | ||
8a1ebd74 | 1962 | pt = alloc_pt(dev); |
4933d519 MT |
1963 | if (IS_ERR(pt)) { |
1964 | ret = PTR_ERR(pt); | |
1965 | goto unwind_out; | |
1966 | } | |
1967 | ||
1968 | gen6_initialize_pt(vm, pt); | |
1969 | ||
1970 | ppgtt->pd.page_table[pde] = pt; | |
966082c9 | 1971 | __set_bit(pde, new_page_tables); |
72744cb1 | 1972 | trace_i915_page_table_entry_alloc(vm, pde, start, GEN6_PDE_SHIFT); |
4933d519 MT |
1973 | } |
1974 | ||
1975 | start = start_save; | |
1976 | length = length_save; | |
678d96fb | 1977 | |
731f74c5 | 1978 | gen6_for_each_pde(pt, &ppgtt->pd, start, length, pde) { |
678d96fb BW |
1979 | DECLARE_BITMAP(tmp_bitmap, GEN6_PTES); |
1980 | ||
1981 | bitmap_zero(tmp_bitmap, GEN6_PTES); | |
1982 | bitmap_set(tmp_bitmap, gen6_pte_index(start), | |
1983 | gen6_pte_count(start, length)); | |
1984 | ||
966082c9 | 1985 | if (__test_and_clear_bit(pde, new_page_tables)) |
4933d519 MT |
1986 | gen6_write_pde(&ppgtt->pd, pde, pt); |
1987 | ||
72744cb1 MT |
1988 | trace_i915_page_table_entry_map(vm, pde, pt, |
1989 | gen6_pte_index(start), | |
1990 | gen6_pte_count(start, length), | |
1991 | GEN6_PTES); | |
4933d519 | 1992 | bitmap_or(pt->used_ptes, tmp_bitmap, pt->used_ptes, |
678d96fb BW |
1993 | GEN6_PTES); |
1994 | } | |
1995 | ||
4933d519 MT |
1996 | WARN_ON(!bitmap_empty(new_page_tables, I915_PDES)); |
1997 | ||
1998 | /* Make sure write is complete before other code can use this page | |
1999 | * table. Also require for WC mapped PTEs */ | |
72e96d64 | 2000 | readl(ggtt->gsm); |
4933d519 | 2001 | |
563222a7 | 2002 | mark_tlbs_dirty(ppgtt); |
678d96fb | 2003 | return 0; |
4933d519 MT |
2004 | |
2005 | unwind_out: | |
2006 | for_each_set_bit(pde, new_page_tables, I915_PDES) { | |
ec565b3c | 2007 | struct i915_page_table *pt = ppgtt->pd.page_table[pde]; |
4933d519 | 2008 | |
79ab9370 | 2009 | ppgtt->pd.page_table[pde] = vm->scratch_pt; |
a08e111a | 2010 | free_pt(vm->dev, pt); |
4933d519 MT |
2011 | } |
2012 | ||
2013 | mark_tlbs_dirty(ppgtt); | |
2014 | return ret; | |
678d96fb BW |
2015 | } |
2016 | ||
8776f02b MK |
2017 | static int gen6_init_scratch(struct i915_address_space *vm) |
2018 | { | |
2019 | struct drm_device *dev = vm->dev; | |
8bcdd0f7 | 2020 | int ret; |
8776f02b | 2021 | |
bb8f9cff | 2022 | ret = setup_scratch_page(dev, &vm->scratch_page, I915_GFP_DMA); |
8bcdd0f7 CW |
2023 | if (ret) |
2024 | return ret; | |
8776f02b MK |
2025 | |
2026 | vm->scratch_pt = alloc_pt(dev); | |
2027 | if (IS_ERR(vm->scratch_pt)) { | |
8bcdd0f7 | 2028 | cleanup_scratch_page(dev, &vm->scratch_page); |
8776f02b MK |
2029 | return PTR_ERR(vm->scratch_pt); |
2030 | } | |
2031 | ||
2032 | gen6_initialize_pt(vm, vm->scratch_pt); | |
2033 | ||
2034 | return 0; | |
2035 | } | |
2036 | ||
2037 | static void gen6_free_scratch(struct i915_address_space *vm) | |
2038 | { | |
2039 | struct drm_device *dev = vm->dev; | |
2040 | ||
2041 | free_pt(dev, vm->scratch_pt); | |
8bcdd0f7 | 2042 | cleanup_scratch_page(dev, &vm->scratch_page); |
8776f02b MK |
2043 | } |
2044 | ||
061dd493 | 2045 | static void gen6_ppgtt_cleanup(struct i915_address_space *vm) |
a00d825d | 2046 | { |
e5716f55 | 2047 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
731f74c5 DG |
2048 | struct i915_page_directory *pd = &ppgtt->pd; |
2049 | struct drm_device *dev = vm->dev; | |
09942c65 MT |
2050 | struct i915_page_table *pt; |
2051 | uint32_t pde; | |
4933d519 | 2052 | |
061dd493 DV |
2053 | drm_mm_remove_node(&ppgtt->node); |
2054 | ||
731f74c5 | 2055 | gen6_for_all_pdes(pt, pd, pde) |
79ab9370 | 2056 | if (pt != vm->scratch_pt) |
731f74c5 | 2057 | free_pt(dev, pt); |
06fda602 | 2058 | |
8776f02b | 2059 | gen6_free_scratch(vm); |
3440d265 DV |
2060 | } |
2061 | ||
b146520f | 2062 | static int gen6_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt) |
3440d265 | 2063 | { |
8776f02b | 2064 | struct i915_address_space *vm = &ppgtt->base; |
853ba5d2 | 2065 | struct drm_device *dev = ppgtt->base.dev; |
72e96d64 JL |
2066 | struct drm_i915_private *dev_priv = to_i915(dev); |
2067 | struct i915_ggtt *ggtt = &dev_priv->ggtt; | |
e3cc1995 | 2068 | bool retried = false; |
b146520f | 2069 | int ret; |
1d2a314c | 2070 | |
c8d4c0d6 BW |
2071 | /* PPGTT PDEs reside in the GGTT and consists of 512 entries. The |
2072 | * allocator works in address space sizes, so it's multiplied by page | |
2073 | * size. We allocate at the top of the GTT to avoid fragmentation. | |
2074 | */ | |
72e96d64 | 2075 | BUG_ON(!drm_mm_initialized(&ggtt->base.mm)); |
4933d519 | 2076 | |
8776f02b MK |
2077 | ret = gen6_init_scratch(vm); |
2078 | if (ret) | |
2079 | return ret; | |
4933d519 | 2080 | |
e3cc1995 | 2081 | alloc: |
72e96d64 | 2082 | ret = drm_mm_insert_node_in_range_generic(&ggtt->base.mm, |
c8d4c0d6 BW |
2083 | &ppgtt->node, GEN6_PD_SIZE, |
2084 | GEN6_PD_ALIGN, 0, | |
72e96d64 | 2085 | 0, ggtt->base.total, |
3e8b5ae9 | 2086 | DRM_MM_TOPDOWN); |
e3cc1995 | 2087 | if (ret == -ENOSPC && !retried) { |
e522ac23 | 2088 | ret = i915_gem_evict_something(&ggtt->base, |
e3cc1995 | 2089 | GEN6_PD_SIZE, GEN6_PD_ALIGN, |
d23db88c | 2090 | I915_CACHE_NONE, |
72e96d64 | 2091 | 0, ggtt->base.total, |
d23db88c | 2092 | 0); |
e3cc1995 | 2093 | if (ret) |
678d96fb | 2094 | goto err_out; |
e3cc1995 BW |
2095 | |
2096 | retried = true; | |
2097 | goto alloc; | |
2098 | } | |
c8d4c0d6 | 2099 | |
c8c26622 | 2100 | if (ret) |
678d96fb BW |
2101 | goto err_out; |
2102 | ||
c8c26622 | 2103 | |
72e96d64 | 2104 | if (ppgtt->node.start < ggtt->mappable_end) |
c8d4c0d6 | 2105 | DRM_DEBUG("Forced to use aperture for PDEs\n"); |
1d2a314c | 2106 | |
c8c26622 | 2107 | return 0; |
678d96fb BW |
2108 | |
2109 | err_out: | |
8776f02b | 2110 | gen6_free_scratch(vm); |
678d96fb | 2111 | return ret; |
b146520f BW |
2112 | } |
2113 | ||
b146520f BW |
2114 | static int gen6_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt) |
2115 | { | |
2f2cf682 | 2116 | return gen6_ppgtt_allocate_page_directories(ppgtt); |
4933d519 | 2117 | } |
06dc68d6 | 2118 | |
4933d519 MT |
2119 | static void gen6_scratch_va_range(struct i915_hw_ppgtt *ppgtt, |
2120 | uint64_t start, uint64_t length) | |
2121 | { | |
ec565b3c | 2122 | struct i915_page_table *unused; |
731f74c5 | 2123 | uint32_t pde; |
1d2a314c | 2124 | |
731f74c5 | 2125 | gen6_for_each_pde(unused, &ppgtt->pd, start, length, pde) |
79ab9370 | 2126 | ppgtt->pd.page_table[pde] = ppgtt->base.scratch_pt; |
b146520f BW |
2127 | } |
2128 | ||
5c5f6457 | 2129 | static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt) |
b146520f BW |
2130 | { |
2131 | struct drm_device *dev = ppgtt->base.dev; | |
72e96d64 JL |
2132 | struct drm_i915_private *dev_priv = to_i915(dev); |
2133 | struct i915_ggtt *ggtt = &dev_priv->ggtt; | |
b146520f BW |
2134 | int ret; |
2135 | ||
72e96d64 | 2136 | ppgtt->base.pte_encode = ggtt->base.pte_encode; |
5db94019 | 2137 | if (intel_vgpu_active(dev_priv) || IS_GEN6(dev_priv)) |
b146520f | 2138 | ppgtt->switch_mm = gen6_mm_switch; |
772c2a51 | 2139 | else if (IS_HASWELL(dev_priv)) |
b146520f | 2140 | ppgtt->switch_mm = hsw_mm_switch; |
5db94019 | 2141 | else if (IS_GEN7(dev_priv)) |
b146520f | 2142 | ppgtt->switch_mm = gen7_mm_switch; |
8eb95204 | 2143 | else |
b146520f BW |
2144 | BUG(); |
2145 | ||
2146 | ret = gen6_ppgtt_alloc(ppgtt); | |
2147 | if (ret) | |
2148 | return ret; | |
2149 | ||
5c5f6457 | 2150 | ppgtt->base.allocate_va_range = gen6_alloc_va_range; |
b146520f BW |
2151 | ppgtt->base.clear_range = gen6_ppgtt_clear_range; |
2152 | ppgtt->base.insert_entries = gen6_ppgtt_insert_entries; | |
777dc5bb DV |
2153 | ppgtt->base.unbind_vma = ppgtt_unbind_vma; |
2154 | ppgtt->base.bind_vma = ppgtt_bind_vma; | |
b146520f | 2155 | ppgtt->base.cleanup = gen6_ppgtt_cleanup; |
b146520f | 2156 | ppgtt->base.start = 0; |
09942c65 | 2157 | ppgtt->base.total = I915_PDES * GEN6_PTES * PAGE_SIZE; |
87d60b63 | 2158 | ppgtt->debug_dump = gen6_dump_ppgtt; |
1d2a314c | 2159 | |
44159ddb | 2160 | ppgtt->pd.base.ggtt_offset = |
07749ef3 | 2161 | ppgtt->node.start / PAGE_SIZE * sizeof(gen6_pte_t); |
1d2a314c | 2162 | |
72e96d64 | 2163 | ppgtt->pd_addr = (gen6_pte_t __iomem *)ggtt->gsm + |
44159ddb | 2164 | ppgtt->pd.base.ggtt_offset / sizeof(gen6_pte_t); |
678d96fb | 2165 | |
5c5f6457 | 2166 | gen6_scratch_va_range(ppgtt, 0, ppgtt->base.total); |
1d2a314c | 2167 | |
678d96fb BW |
2168 | gen6_write_page_range(dev_priv, &ppgtt->pd, 0, ppgtt->base.total); |
2169 | ||
440fd528 | 2170 | DRM_DEBUG_DRIVER("Allocated pde space (%lldM) at GTT entry: %llx\n", |
b146520f BW |
2171 | ppgtt->node.size >> 20, |
2172 | ppgtt->node.start / PAGE_SIZE); | |
3440d265 | 2173 | |
fa76da34 | 2174 | DRM_DEBUG("Adding PPGTT at offset %x\n", |
44159ddb | 2175 | ppgtt->pd.base.ggtt_offset << 10); |
fa76da34 | 2176 | |
b146520f | 2177 | return 0; |
3440d265 DV |
2178 | } |
2179 | ||
2bfa996e CW |
2180 | static int __hw_ppgtt_init(struct i915_hw_ppgtt *ppgtt, |
2181 | struct drm_i915_private *dev_priv) | |
3440d265 | 2182 | { |
2bfa996e | 2183 | ppgtt->base.dev = &dev_priv->drm; |
3440d265 | 2184 | |
2bfa996e | 2185 | if (INTEL_INFO(dev_priv)->gen < 8) |
5c5f6457 | 2186 | return gen6_ppgtt_init(ppgtt); |
3ed124b2 | 2187 | else |
d7b2633d | 2188 | return gen8_ppgtt_init(ppgtt); |
fa76da34 | 2189 | } |
c114f76a | 2190 | |
a2cad9df | 2191 | static void i915_address_space_init(struct i915_address_space *vm, |
80b204bc CW |
2192 | struct drm_i915_private *dev_priv, |
2193 | const char *name) | |
a2cad9df | 2194 | { |
80b204bc | 2195 | i915_gem_timeline_init(dev_priv, &vm->timeline, name); |
a2cad9df | 2196 | drm_mm_init(&vm->mm, vm->start, vm->total); |
a2cad9df MW |
2197 | INIT_LIST_HEAD(&vm->active_list); |
2198 | INIT_LIST_HEAD(&vm->inactive_list); | |
50e046b6 | 2199 | INIT_LIST_HEAD(&vm->unbound_list); |
a2cad9df MW |
2200 | list_add_tail(&vm->global_link, &dev_priv->vm_list); |
2201 | } | |
2202 | ||
d5165ebd TG |
2203 | static void gtt_write_workarounds(struct drm_device *dev) |
2204 | { | |
fac5e23e | 2205 | struct drm_i915_private *dev_priv = to_i915(dev); |
d5165ebd TG |
2206 | |
2207 | /* This function is for gtt related workarounds. This function is | |
2208 | * called on driver load and after a GPU reset, so you can place | |
2209 | * workarounds here even if they get overwritten by GPU reset. | |
2210 | */ | |
2211 | /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt */ | |
8652744b | 2212 | if (IS_BROADWELL(dev_priv)) |
d5165ebd | 2213 | I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW); |
920a14b2 | 2214 | else if (IS_CHERRYVIEW(dev_priv)) |
d5165ebd | 2215 | I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV); |
d9486e65 | 2216 | else if (IS_SKYLAKE(dev_priv)) |
d5165ebd | 2217 | I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL); |
e2d214ae | 2218 | else if (IS_BROXTON(dev_priv)) |
d5165ebd TG |
2219 | I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT); |
2220 | } | |
2221 | ||
2bfa996e CW |
2222 | static int i915_ppgtt_init(struct i915_hw_ppgtt *ppgtt, |
2223 | struct drm_i915_private *dev_priv, | |
80b204bc CW |
2224 | struct drm_i915_file_private *file_priv, |
2225 | const char *name) | |
fa76da34 | 2226 | { |
2bfa996e | 2227 | int ret; |
3ed124b2 | 2228 | |
2bfa996e | 2229 | ret = __hw_ppgtt_init(ppgtt, dev_priv); |
fa76da34 | 2230 | if (ret == 0) { |
c7c48dfd | 2231 | kref_init(&ppgtt->ref); |
80b204bc | 2232 | i915_address_space_init(&ppgtt->base, dev_priv, name); |
2bfa996e | 2233 | ppgtt->base.file = file_priv; |
93bd8649 | 2234 | } |
1d2a314c DV |
2235 | |
2236 | return ret; | |
2237 | } | |
2238 | ||
82460d97 DV |
2239 | int i915_ppgtt_init_hw(struct drm_device *dev) |
2240 | { | |
5db94019 TU |
2241 | struct drm_i915_private *dev_priv = to_i915(dev); |
2242 | ||
d5165ebd TG |
2243 | gtt_write_workarounds(dev); |
2244 | ||
671b5013 TD |
2245 | /* In the case of execlists, PPGTT is enabled by the context descriptor |
2246 | * and the PDPs are contained within the context itself. We don't | |
2247 | * need to do anything here. */ | |
2248 | if (i915.enable_execlists) | |
2249 | return 0; | |
2250 | ||
82460d97 DV |
2251 | if (!USES_PPGTT(dev)) |
2252 | return 0; | |
2253 | ||
5db94019 | 2254 | if (IS_GEN6(dev_priv)) |
82460d97 | 2255 | gen6_ppgtt_enable(dev); |
5db94019 | 2256 | else if (IS_GEN7(dev_priv)) |
82460d97 DV |
2257 | gen7_ppgtt_enable(dev); |
2258 | else if (INTEL_INFO(dev)->gen >= 8) | |
2259 | gen8_ppgtt_enable(dev); | |
2260 | else | |
5f77eeb0 | 2261 | MISSING_CASE(INTEL_INFO(dev)->gen); |
82460d97 | 2262 | |
4ad2fd88 JH |
2263 | return 0; |
2264 | } | |
1d2a314c | 2265 | |
4d884705 | 2266 | struct i915_hw_ppgtt * |
2bfa996e | 2267 | i915_ppgtt_create(struct drm_i915_private *dev_priv, |
80b204bc CW |
2268 | struct drm_i915_file_private *fpriv, |
2269 | const char *name) | |
4d884705 DV |
2270 | { |
2271 | struct i915_hw_ppgtt *ppgtt; | |
2272 | int ret; | |
2273 | ||
2274 | ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL); | |
2275 | if (!ppgtt) | |
2276 | return ERR_PTR(-ENOMEM); | |
2277 | ||
80b204bc | 2278 | ret = i915_ppgtt_init(ppgtt, dev_priv, fpriv, name); |
4d884705 DV |
2279 | if (ret) { |
2280 | kfree(ppgtt); | |
2281 | return ERR_PTR(ret); | |
2282 | } | |
2283 | ||
198c974d DCS |
2284 | trace_i915_ppgtt_create(&ppgtt->base); |
2285 | ||
4d884705 DV |
2286 | return ppgtt; |
2287 | } | |
2288 | ||
ee960be7 DV |
2289 | void i915_ppgtt_release(struct kref *kref) |
2290 | { | |
2291 | struct i915_hw_ppgtt *ppgtt = | |
2292 | container_of(kref, struct i915_hw_ppgtt, ref); | |
2293 | ||
198c974d DCS |
2294 | trace_i915_ppgtt_release(&ppgtt->base); |
2295 | ||
50e046b6 | 2296 | /* vmas should already be unbound and destroyed */ |
ee960be7 DV |
2297 | WARN_ON(!list_empty(&ppgtt->base.active_list)); |
2298 | WARN_ON(!list_empty(&ppgtt->base.inactive_list)); | |
50e046b6 | 2299 | WARN_ON(!list_empty(&ppgtt->base.unbound_list)); |
ee960be7 | 2300 | |
80b204bc | 2301 | i915_gem_timeline_fini(&ppgtt->base.timeline); |
19dd120c DV |
2302 | list_del(&ppgtt->base.global_link); |
2303 | drm_mm_takedown(&ppgtt->base.mm); | |
2304 | ||
ee960be7 DV |
2305 | ppgtt->base.cleanup(&ppgtt->base); |
2306 | kfree(ppgtt); | |
2307 | } | |
1d2a314c | 2308 | |
a81cc00c BW |
2309 | /* Certain Gen5 chipsets require require idling the GPU before |
2310 | * unmapping anything from the GTT when VT-d is enabled. | |
2311 | */ | |
97d6d7ab | 2312 | static bool needs_idle_maps(struct drm_i915_private *dev_priv) |
a81cc00c BW |
2313 | { |
2314 | #ifdef CONFIG_INTEL_IOMMU | |
2315 | /* Query intel_iommu to see if we need the workaround. Presumably that | |
2316 | * was loaded first. | |
2317 | */ | |
97d6d7ab | 2318 | if (IS_GEN5(dev_priv) && IS_MOBILE(dev_priv) && intel_iommu_gfx_mapped) |
a81cc00c BW |
2319 | return true; |
2320 | #endif | |
2321 | return false; | |
2322 | } | |
2323 | ||
dc97997a | 2324 | void i915_check_and_clear_faults(struct drm_i915_private *dev_priv) |
828c7908 | 2325 | { |
e2f80391 | 2326 | struct intel_engine_cs *engine; |
3b3f1650 | 2327 | enum intel_engine_id id; |
828c7908 | 2328 | |
dc97997a | 2329 | if (INTEL_INFO(dev_priv)->gen < 6) |
828c7908 BW |
2330 | return; |
2331 | ||
3b3f1650 | 2332 | for_each_engine(engine, dev_priv, id) { |
828c7908 | 2333 | u32 fault_reg; |
e2f80391 | 2334 | fault_reg = I915_READ(RING_FAULT_REG(engine)); |
828c7908 BW |
2335 | if (fault_reg & RING_FAULT_VALID) { |
2336 | DRM_DEBUG_DRIVER("Unexpected fault\n" | |
59a5d290 | 2337 | "\tAddr: 0x%08lx\n" |
828c7908 BW |
2338 | "\tAddress space: %s\n" |
2339 | "\tSource ID: %d\n" | |
2340 | "\tType: %d\n", | |
2341 | fault_reg & PAGE_MASK, | |
2342 | fault_reg & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT", | |
2343 | RING_FAULT_SRCID(fault_reg), | |
2344 | RING_FAULT_FAULT_TYPE(fault_reg)); | |
e2f80391 | 2345 | I915_WRITE(RING_FAULT_REG(engine), |
828c7908 BW |
2346 | fault_reg & ~RING_FAULT_VALID); |
2347 | } | |
2348 | } | |
3b3f1650 AG |
2349 | |
2350 | /* Engine specific init may not have been done till this point. */ | |
2351 | if (dev_priv->engine[RCS]) | |
2352 | POSTING_READ(RING_FAULT_REG(dev_priv->engine[RCS])); | |
828c7908 BW |
2353 | } |
2354 | ||
91e56499 CW |
2355 | static void i915_ggtt_flush(struct drm_i915_private *dev_priv) |
2356 | { | |
2d1fe073 | 2357 | if (INTEL_INFO(dev_priv)->gen < 6) { |
91e56499 CW |
2358 | intel_gtt_chipset_flush(); |
2359 | } else { | |
2360 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
2361 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
2362 | } | |
2363 | } | |
2364 | ||
828c7908 BW |
2365 | void i915_gem_suspend_gtt_mappings(struct drm_device *dev) |
2366 | { | |
72e96d64 JL |
2367 | struct drm_i915_private *dev_priv = to_i915(dev); |
2368 | struct i915_ggtt *ggtt = &dev_priv->ggtt; | |
828c7908 BW |
2369 | |
2370 | /* Don't bother messing with faults pre GEN6 as we have little | |
2371 | * documentation supporting that it's a good idea. | |
2372 | */ | |
2373 | if (INTEL_INFO(dev)->gen < 6) | |
2374 | return; | |
2375 | ||
dc97997a | 2376 | i915_check_and_clear_faults(dev_priv); |
828c7908 | 2377 | |
4fb84d99 | 2378 | ggtt->base.clear_range(&ggtt->base, ggtt->base.start, ggtt->base.total); |
91e56499 CW |
2379 | |
2380 | i915_ggtt_flush(dev_priv); | |
828c7908 BW |
2381 | } |
2382 | ||
03ac84f1 CW |
2383 | int i915_gem_gtt_prepare_pages(struct drm_i915_gem_object *obj, |
2384 | struct sg_table *pages) | |
7c2e6fdf | 2385 | { |
03ac84f1 CW |
2386 | if (dma_map_sg(&obj->base.dev->pdev->dev, |
2387 | pages->sgl, pages->nents, | |
2388 | PCI_DMA_BIDIRECTIONAL)) | |
2389 | return 0; | |
9da3da66 | 2390 | |
03ac84f1 | 2391 | return -ENOSPC; |
7c2e6fdf DV |
2392 | } |
2393 | ||
2c642b07 | 2394 | static void gen8_set_pte(void __iomem *addr, gen8_pte_t pte) |
94ec8f61 | 2395 | { |
94ec8f61 | 2396 | writeq(pte, addr); |
94ec8f61 BW |
2397 | } |
2398 | ||
d6473f56 CW |
2399 | static void gen8_ggtt_insert_page(struct i915_address_space *vm, |
2400 | dma_addr_t addr, | |
2401 | uint64_t offset, | |
2402 | enum i915_cache_level level, | |
2403 | u32 unused) | |
2404 | { | |
2405 | struct drm_i915_private *dev_priv = to_i915(vm->dev); | |
2406 | gen8_pte_t __iomem *pte = | |
2407 | (gen8_pte_t __iomem *)dev_priv->ggtt.gsm + | |
2408 | (offset >> PAGE_SHIFT); | |
d6473f56 | 2409 | |
4fb84d99 | 2410 | gen8_set_pte(pte, gen8_pte_encode(addr, level)); |
d6473f56 CW |
2411 | |
2412 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
2413 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
d6473f56 CW |
2414 | } |
2415 | ||
94ec8f61 BW |
2416 | static void gen8_ggtt_insert_entries(struct i915_address_space *vm, |
2417 | struct sg_table *st, | |
782f1495 | 2418 | uint64_t start, |
24f3a8cf | 2419 | enum i915_cache_level level, u32 unused) |
94ec8f61 | 2420 | { |
72e96d64 | 2421 | struct drm_i915_private *dev_priv = to_i915(vm->dev); |
ce7fda2e | 2422 | struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm); |
85d1225e DG |
2423 | struct sgt_iter sgt_iter; |
2424 | gen8_pte_t __iomem *gtt_entries; | |
2425 | gen8_pte_t gtt_entry; | |
2426 | dma_addr_t addr; | |
85d1225e | 2427 | int i = 0; |
be69459a | 2428 | |
85d1225e DG |
2429 | gtt_entries = (gen8_pte_t __iomem *)ggtt->gsm + (start >> PAGE_SHIFT); |
2430 | ||
2431 | for_each_sgt_dma(addr, sgt_iter, st) { | |
4fb84d99 | 2432 | gtt_entry = gen8_pte_encode(addr, level); |
85d1225e | 2433 | gen8_set_pte(>t_entries[i++], gtt_entry); |
94ec8f61 BW |
2434 | } |
2435 | ||
2436 | /* | |
2437 | * XXX: This serves as a posting read to make sure that the PTE has | |
2438 | * actually been updated. There is some concern that even though | |
2439 | * registers and PTEs are within the same BAR that they are potentially | |
2440 | * of NUMA access patterns. Therefore, even with the way we assume | |
2441 | * hardware should work, we must keep this posting read for paranoia. | |
2442 | */ | |
2443 | if (i != 0) | |
85d1225e | 2444 | WARN_ON(readq(>t_entries[i-1]) != gtt_entry); |
94ec8f61 | 2445 | |
94ec8f61 BW |
2446 | /* This next bit makes the above posting read even more important. We |
2447 | * want to flush the TLBs only after we're certain all the PTE updates | |
2448 | * have finished. | |
2449 | */ | |
2450 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
2451 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
94ec8f61 BW |
2452 | } |
2453 | ||
c140330b CW |
2454 | struct insert_entries { |
2455 | struct i915_address_space *vm; | |
2456 | struct sg_table *st; | |
2457 | uint64_t start; | |
2458 | enum i915_cache_level level; | |
2459 | u32 flags; | |
2460 | }; | |
2461 | ||
2462 | static int gen8_ggtt_insert_entries__cb(void *_arg) | |
2463 | { | |
2464 | struct insert_entries *arg = _arg; | |
2465 | gen8_ggtt_insert_entries(arg->vm, arg->st, | |
2466 | arg->start, arg->level, arg->flags); | |
2467 | return 0; | |
2468 | } | |
2469 | ||
2470 | static void gen8_ggtt_insert_entries__BKL(struct i915_address_space *vm, | |
2471 | struct sg_table *st, | |
2472 | uint64_t start, | |
2473 | enum i915_cache_level level, | |
2474 | u32 flags) | |
2475 | { | |
2476 | struct insert_entries arg = { vm, st, start, level, flags }; | |
2477 | stop_machine(gen8_ggtt_insert_entries__cb, &arg, NULL); | |
2478 | } | |
2479 | ||
d6473f56 CW |
2480 | static void gen6_ggtt_insert_page(struct i915_address_space *vm, |
2481 | dma_addr_t addr, | |
2482 | uint64_t offset, | |
2483 | enum i915_cache_level level, | |
2484 | u32 flags) | |
2485 | { | |
2486 | struct drm_i915_private *dev_priv = to_i915(vm->dev); | |
2487 | gen6_pte_t __iomem *pte = | |
2488 | (gen6_pte_t __iomem *)dev_priv->ggtt.gsm + | |
2489 | (offset >> PAGE_SHIFT); | |
d6473f56 | 2490 | |
4fb84d99 | 2491 | iowrite32(vm->pte_encode(addr, level, flags), pte); |
d6473f56 CW |
2492 | |
2493 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
2494 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
d6473f56 CW |
2495 | } |
2496 | ||
e76e9aeb BW |
2497 | /* |
2498 | * Binds an object into the global gtt with the specified cache level. The object | |
2499 | * will be accessible to the GPU via commands whose operands reference offsets | |
2500 | * within the global GTT as well as accessible by the GPU through the GMADR | |
2501 | * mapped BAR (dev_priv->mm.gtt->gtt). | |
2502 | */ | |
853ba5d2 | 2503 | static void gen6_ggtt_insert_entries(struct i915_address_space *vm, |
7faf1ab2 | 2504 | struct sg_table *st, |
782f1495 | 2505 | uint64_t start, |
24f3a8cf | 2506 | enum i915_cache_level level, u32 flags) |
e76e9aeb | 2507 | { |
72e96d64 | 2508 | struct drm_i915_private *dev_priv = to_i915(vm->dev); |
ce7fda2e | 2509 | struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm); |
85d1225e DG |
2510 | struct sgt_iter sgt_iter; |
2511 | gen6_pte_t __iomem *gtt_entries; | |
2512 | gen6_pte_t gtt_entry; | |
2513 | dma_addr_t addr; | |
85d1225e | 2514 | int i = 0; |
be69459a | 2515 | |
85d1225e DG |
2516 | gtt_entries = (gen6_pte_t __iomem *)ggtt->gsm + (start >> PAGE_SHIFT); |
2517 | ||
2518 | for_each_sgt_dma(addr, sgt_iter, st) { | |
4fb84d99 | 2519 | gtt_entry = vm->pte_encode(addr, level, flags); |
85d1225e | 2520 | iowrite32(gtt_entry, >t_entries[i++]); |
e76e9aeb BW |
2521 | } |
2522 | ||
e76e9aeb BW |
2523 | /* XXX: This serves as a posting read to make sure that the PTE has |
2524 | * actually been updated. There is some concern that even though | |
2525 | * registers and PTEs are within the same BAR that they are potentially | |
2526 | * of NUMA access patterns. Therefore, even with the way we assume | |
2527 | * hardware should work, we must keep this posting read for paranoia. | |
2528 | */ | |
85d1225e DG |
2529 | if (i != 0) |
2530 | WARN_ON(readl(>t_entries[i-1]) != gtt_entry); | |
0f9b91c7 BW |
2531 | |
2532 | /* This next bit makes the above posting read even more important. We | |
2533 | * want to flush the TLBs only after we're certain all the PTE updates | |
2534 | * have finished. | |
2535 | */ | |
2536 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
2537 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
e76e9aeb BW |
2538 | } |
2539 | ||
f7770bfd | 2540 | static void nop_clear_range(struct i915_address_space *vm, |
4fb84d99 | 2541 | uint64_t start, uint64_t length) |
f7770bfd CW |
2542 | { |
2543 | } | |
2544 | ||
94ec8f61 | 2545 | static void gen8_ggtt_clear_range(struct i915_address_space *vm, |
4fb84d99 | 2546 | uint64_t start, uint64_t length) |
94ec8f61 | 2547 | { |
ce7fda2e | 2548 | struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm); |
782f1495 BW |
2549 | unsigned first_entry = start >> PAGE_SHIFT; |
2550 | unsigned num_entries = length >> PAGE_SHIFT; | |
07749ef3 | 2551 | gen8_pte_t scratch_pte, __iomem *gtt_base = |
72e96d64 JL |
2552 | (gen8_pte_t __iomem *)ggtt->gsm + first_entry; |
2553 | const int max_entries = ggtt_total_entries(ggtt) - first_entry; | |
94ec8f61 BW |
2554 | int i; |
2555 | ||
2556 | if (WARN(num_entries > max_entries, | |
2557 | "First entry = %d; Num entries = %d (max=%d)\n", | |
2558 | first_entry, num_entries, max_entries)) | |
2559 | num_entries = max_entries; | |
2560 | ||
8bcdd0f7 | 2561 | scratch_pte = gen8_pte_encode(vm->scratch_page.daddr, |
4fb84d99 | 2562 | I915_CACHE_LLC); |
94ec8f61 BW |
2563 | for (i = 0; i < num_entries; i++) |
2564 | gen8_set_pte(>t_base[i], scratch_pte); | |
2565 | readl(gtt_base); | |
2566 | } | |
2567 | ||
853ba5d2 | 2568 | static void gen6_ggtt_clear_range(struct i915_address_space *vm, |
782f1495 | 2569 | uint64_t start, |
4fb84d99 | 2570 | uint64_t length) |
7faf1ab2 | 2571 | { |
ce7fda2e | 2572 | struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm); |
782f1495 BW |
2573 | unsigned first_entry = start >> PAGE_SHIFT; |
2574 | unsigned num_entries = length >> PAGE_SHIFT; | |
07749ef3 | 2575 | gen6_pte_t scratch_pte, __iomem *gtt_base = |
72e96d64 JL |
2576 | (gen6_pte_t __iomem *)ggtt->gsm + first_entry; |
2577 | const int max_entries = ggtt_total_entries(ggtt) - first_entry; | |
7faf1ab2 DV |
2578 | int i; |
2579 | ||
2580 | if (WARN(num_entries > max_entries, | |
2581 | "First entry = %d; Num entries = %d (max=%d)\n", | |
2582 | first_entry, num_entries, max_entries)) | |
2583 | num_entries = max_entries; | |
2584 | ||
8bcdd0f7 | 2585 | scratch_pte = vm->pte_encode(vm->scratch_page.daddr, |
4fb84d99 | 2586 | I915_CACHE_LLC, 0); |
828c7908 | 2587 | |
7faf1ab2 DV |
2588 | for (i = 0; i < num_entries; i++) |
2589 | iowrite32(scratch_pte, >t_base[i]); | |
2590 | readl(gtt_base); | |
2591 | } | |
2592 | ||
d6473f56 CW |
2593 | static void i915_ggtt_insert_page(struct i915_address_space *vm, |
2594 | dma_addr_t addr, | |
2595 | uint64_t offset, | |
2596 | enum i915_cache_level cache_level, | |
2597 | u32 unused) | |
2598 | { | |
d6473f56 CW |
2599 | unsigned int flags = (cache_level == I915_CACHE_NONE) ? |
2600 | AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY; | |
d6473f56 CW |
2601 | |
2602 | intel_gtt_insert_page(addr, offset >> PAGE_SHIFT, flags); | |
d6473f56 CW |
2603 | } |
2604 | ||
d369d2d9 DV |
2605 | static void i915_ggtt_insert_entries(struct i915_address_space *vm, |
2606 | struct sg_table *pages, | |
2607 | uint64_t start, | |
2608 | enum i915_cache_level cache_level, u32 unused) | |
7faf1ab2 DV |
2609 | { |
2610 | unsigned int flags = (cache_level == I915_CACHE_NONE) ? | |
2611 | AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY; | |
2612 | ||
d369d2d9 | 2613 | intel_gtt_insert_sg_entries(pages, start >> PAGE_SHIFT, flags); |
0875546c | 2614 | |
7faf1ab2 DV |
2615 | } |
2616 | ||
853ba5d2 | 2617 | static void i915_ggtt_clear_range(struct i915_address_space *vm, |
782f1495 | 2618 | uint64_t start, |
4fb84d99 | 2619 | uint64_t length) |
7faf1ab2 | 2620 | { |
2eedfc7d | 2621 | intel_gtt_clear_range(start >> PAGE_SHIFT, length >> PAGE_SHIFT); |
7faf1ab2 DV |
2622 | } |
2623 | ||
70b9f6f8 DV |
2624 | static int ggtt_bind_vma(struct i915_vma *vma, |
2625 | enum i915_cache_level cache_level, | |
2626 | u32 flags) | |
0a878716 | 2627 | { |
9c870d03 | 2628 | struct drm_i915_private *i915 = to_i915(vma->vm->dev); |
0a878716 DV |
2629 | struct drm_i915_gem_object *obj = vma->obj; |
2630 | u32 pte_flags = 0; | |
2631 | int ret; | |
2632 | ||
2633 | ret = i915_get_ggtt_vma_pages(vma); | |
2634 | if (ret) | |
2635 | return ret; | |
2636 | ||
2637 | /* Currently applicable only to VLV */ | |
2638 | if (obj->gt_ro) | |
2639 | pte_flags |= PTE_READ_ONLY; | |
2640 | ||
9c870d03 | 2641 | intel_runtime_pm_get(i915); |
247177dd | 2642 | vma->vm->insert_entries(vma->vm, vma->pages, vma->node.start, |
0a878716 | 2643 | cache_level, pte_flags); |
9c870d03 | 2644 | intel_runtime_pm_put(i915); |
0a878716 DV |
2645 | |
2646 | /* | |
2647 | * Without aliasing PPGTT there's no difference between | |
2648 | * GLOBAL/LOCAL_BIND, it's all the same ptes. Hence unconditionally | |
2649 | * upgrade to both bound if we bind either to avoid double-binding. | |
2650 | */ | |
3272db53 | 2651 | vma->flags |= I915_VMA_GLOBAL_BIND | I915_VMA_LOCAL_BIND; |
0a878716 DV |
2652 | |
2653 | return 0; | |
2654 | } | |
2655 | ||
2656 | static int aliasing_gtt_bind_vma(struct i915_vma *vma, | |
2657 | enum i915_cache_level cache_level, | |
2658 | u32 flags) | |
d5bd1449 | 2659 | { |
9c870d03 | 2660 | struct drm_i915_private *i915 = to_i915(vma->vm->dev); |
321d178e | 2661 | u32 pte_flags; |
70b9f6f8 DV |
2662 | int ret; |
2663 | ||
2664 | ret = i915_get_ggtt_vma_pages(vma); | |
2665 | if (ret) | |
2666 | return ret; | |
7faf1ab2 | 2667 | |
24f3a8cf | 2668 | /* Currently applicable only to VLV */ |
321d178e CW |
2669 | pte_flags = 0; |
2670 | if (vma->obj->gt_ro) | |
f329f5f6 | 2671 | pte_flags |= PTE_READ_ONLY; |
24f3a8cf | 2672 | |
ec7adb6e | 2673 | |
3272db53 | 2674 | if (flags & I915_VMA_GLOBAL_BIND) { |
9c870d03 | 2675 | intel_runtime_pm_get(i915); |
321d178e | 2676 | vma->vm->insert_entries(vma->vm, |
247177dd | 2677 | vma->pages, vma->node.start, |
0875546c | 2678 | cache_level, pte_flags); |
9c870d03 | 2679 | intel_runtime_pm_put(i915); |
6f65e29a | 2680 | } |
d5bd1449 | 2681 | |
3272db53 | 2682 | if (flags & I915_VMA_LOCAL_BIND) { |
9c870d03 | 2683 | struct i915_hw_ppgtt *appgtt = i915->mm.aliasing_ppgtt; |
321d178e | 2684 | appgtt->base.insert_entries(&appgtt->base, |
247177dd | 2685 | vma->pages, vma->node.start, |
f329f5f6 | 2686 | cache_level, pte_flags); |
6f65e29a | 2687 | } |
70b9f6f8 DV |
2688 | |
2689 | return 0; | |
d5bd1449 CW |
2690 | } |
2691 | ||
6f65e29a | 2692 | static void ggtt_unbind_vma(struct i915_vma *vma) |
74163907 | 2693 | { |
9c870d03 CW |
2694 | struct drm_i915_private *i915 = to_i915(vma->vm->dev); |
2695 | struct i915_hw_ppgtt *appgtt = i915->mm.aliasing_ppgtt; | |
de180033 | 2696 | const u64 size = min(vma->size, vma->node.size); |
6f65e29a | 2697 | |
9c870d03 CW |
2698 | if (vma->flags & I915_VMA_GLOBAL_BIND) { |
2699 | intel_runtime_pm_get(i915); | |
782f1495 | 2700 | vma->vm->clear_range(vma->vm, |
4fb84d99 | 2701 | vma->node.start, size); |
9c870d03 CW |
2702 | intel_runtime_pm_put(i915); |
2703 | } | |
06615ee5 | 2704 | |
3272db53 | 2705 | if (vma->flags & I915_VMA_LOCAL_BIND && appgtt) |
6f65e29a | 2706 | appgtt->base.clear_range(&appgtt->base, |
4fb84d99 | 2707 | vma->node.start, size); |
74163907 DV |
2708 | } |
2709 | ||
03ac84f1 CW |
2710 | void i915_gem_gtt_finish_pages(struct drm_i915_gem_object *obj, |
2711 | struct sg_table *pages) | |
7c2e6fdf | 2712 | { |
52a05c30 DW |
2713 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
2714 | struct device *kdev = &dev_priv->drm.pdev->dev; | |
307dc25b | 2715 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
5c042287 | 2716 | |
307dc25b | 2717 | if (unlikely(ggtt->do_idle_maps)) { |
22dd3bb9 | 2718 | if (i915_gem_wait_for_idle(dev_priv, I915_WAIT_LOCKED)) { |
307dc25b CW |
2719 | DRM_ERROR("Failed to wait for idle; VT'd may hang.\n"); |
2720 | /* Wait a bit, in hopes it avoids the hang */ | |
2721 | udelay(10); | |
2722 | } | |
2723 | } | |
5c042287 | 2724 | |
03ac84f1 | 2725 | dma_unmap_sg(kdev, pages->sgl, pages->nents, PCI_DMA_BIDIRECTIONAL); |
7c2e6fdf | 2726 | } |
644ec02b | 2727 | |
42d6ab48 CW |
2728 | static void i915_gtt_color_adjust(struct drm_mm_node *node, |
2729 | unsigned long color, | |
440fd528 TR |
2730 | u64 *start, |
2731 | u64 *end) | |
42d6ab48 CW |
2732 | { |
2733 | if (node->color != color) | |
2734 | *start += 4096; | |
2735 | ||
2a1d7752 CW |
2736 | node = list_first_entry_or_null(&node->node_list, |
2737 | struct drm_mm_node, | |
2738 | node_list); | |
2739 | if (node && node->allocated && node->color != color) | |
2740 | *end -= 4096; | |
42d6ab48 | 2741 | } |
fbe5d36e | 2742 | |
f6b9d5ca | 2743 | int i915_gem_init_ggtt(struct drm_i915_private *dev_priv) |
644ec02b | 2744 | { |
e78891ca BW |
2745 | /* Let GEM Manage all of the aperture. |
2746 | * | |
2747 | * However, leave one page at the end still bound to the scratch page. | |
2748 | * There are a number of places where the hardware apparently prefetches | |
2749 | * past the end of the object, and we've seen multiple hangs with the | |
2750 | * GPU head pointer stuck in a batchbuffer bound at the last page of the | |
2751 | * aperture. One page should be enough to keep any prefetching inside | |
2752 | * of the aperture. | |
2753 | */ | |
72e96d64 | 2754 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
ed2f3452 | 2755 | unsigned long hole_start, hole_end; |
95374d75 | 2756 | struct i915_hw_ppgtt *ppgtt; |
f6b9d5ca | 2757 | struct drm_mm_node *entry; |
fa76da34 | 2758 | int ret; |
644ec02b | 2759 | |
b02d22a3 ZW |
2760 | ret = intel_vgt_balloon(dev_priv); |
2761 | if (ret) | |
2762 | return ret; | |
5dda8fa3 | 2763 | |
95374d75 CW |
2764 | /* Reserve a mappable slot for our lockless error capture */ |
2765 | ret = drm_mm_insert_node_in_range_generic(&ggtt->base.mm, | |
2766 | &ggtt->error_capture, | |
2767 | 4096, 0, -1, | |
2768 | 0, ggtt->mappable_end, | |
2769 | 0, 0); | |
2770 | if (ret) | |
2771 | return ret; | |
2772 | ||
ed2f3452 | 2773 | /* Clear any non-preallocated blocks */ |
72e96d64 | 2774 | drm_mm_for_each_hole(entry, &ggtt->base.mm, hole_start, hole_end) { |
ed2f3452 CW |
2775 | DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n", |
2776 | hole_start, hole_end); | |
72e96d64 | 2777 | ggtt->base.clear_range(&ggtt->base, hole_start, |
4fb84d99 | 2778 | hole_end - hole_start); |
ed2f3452 CW |
2779 | } |
2780 | ||
2781 | /* And finally clear the reserved guard page */ | |
f6b9d5ca | 2782 | ggtt->base.clear_range(&ggtt->base, |
4fb84d99 | 2783 | ggtt->base.total - PAGE_SIZE, PAGE_SIZE); |
6c5566a8 | 2784 | |
97d6d7ab | 2785 | if (USES_PPGTT(dev_priv) && !USES_FULL_PPGTT(dev_priv)) { |
fa76da34 | 2786 | ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL); |
95374d75 CW |
2787 | if (!ppgtt) { |
2788 | ret = -ENOMEM; | |
2789 | goto err; | |
2790 | } | |
fa76da34 | 2791 | |
2bfa996e | 2792 | ret = __hw_ppgtt_init(ppgtt, dev_priv); |
95374d75 CW |
2793 | if (ret) |
2794 | goto err_ppgtt; | |
5c5f6457 | 2795 | |
95374d75 | 2796 | if (ppgtt->base.allocate_va_range) { |
5c5f6457 DV |
2797 | ret = ppgtt->base.allocate_va_range(&ppgtt->base, 0, |
2798 | ppgtt->base.total); | |
95374d75 CW |
2799 | if (ret) |
2800 | goto err_ppgtt_cleanup; | |
4933d519 | 2801 | } |
fa76da34 | 2802 | |
5c5f6457 DV |
2803 | ppgtt->base.clear_range(&ppgtt->base, |
2804 | ppgtt->base.start, | |
4fb84d99 | 2805 | ppgtt->base.total); |
5c5f6457 | 2806 | |
fa76da34 | 2807 | dev_priv->mm.aliasing_ppgtt = ppgtt; |
72e96d64 JL |
2808 | WARN_ON(ggtt->base.bind_vma != ggtt_bind_vma); |
2809 | ggtt->base.bind_vma = aliasing_gtt_bind_vma; | |
fa76da34 DV |
2810 | } |
2811 | ||
6c5566a8 | 2812 | return 0; |
95374d75 CW |
2813 | |
2814 | err_ppgtt_cleanup: | |
2815 | ppgtt->base.cleanup(&ppgtt->base); | |
2816 | err_ppgtt: | |
2817 | kfree(ppgtt); | |
2818 | err: | |
2819 | drm_mm_remove_node(&ggtt->error_capture); | |
2820 | return ret; | |
e76e9aeb BW |
2821 | } |
2822 | ||
d85489d3 JL |
2823 | /** |
2824 | * i915_ggtt_cleanup_hw - Clean up GGTT hardware initialization | |
97d6d7ab | 2825 | * @dev_priv: i915 device |
d85489d3 | 2826 | */ |
97d6d7ab | 2827 | void i915_ggtt_cleanup_hw(struct drm_i915_private *dev_priv) |
90d0a0e8 | 2828 | { |
72e96d64 | 2829 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
90d0a0e8 | 2830 | |
70e32544 DV |
2831 | if (dev_priv->mm.aliasing_ppgtt) { |
2832 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
70e32544 | 2833 | ppgtt->base.cleanup(&ppgtt->base); |
cb7f2760 | 2834 | kfree(ppgtt); |
70e32544 DV |
2835 | } |
2836 | ||
97d6d7ab | 2837 | i915_gem_cleanup_stolen(&dev_priv->drm); |
a4eba47b | 2838 | |
95374d75 CW |
2839 | if (drm_mm_node_allocated(&ggtt->error_capture)) |
2840 | drm_mm_remove_node(&ggtt->error_capture); | |
2841 | ||
72e96d64 | 2842 | if (drm_mm_initialized(&ggtt->base.mm)) { |
b02d22a3 | 2843 | intel_vgt_deballoon(dev_priv); |
5dda8fa3 | 2844 | |
72e96d64 JL |
2845 | drm_mm_takedown(&ggtt->base.mm); |
2846 | list_del(&ggtt->base.global_link); | |
90d0a0e8 DV |
2847 | } |
2848 | ||
72e96d64 | 2849 | ggtt->base.cleanup(&ggtt->base); |
f6b9d5ca CW |
2850 | |
2851 | arch_phys_wc_del(ggtt->mtrr); | |
f7bbe788 | 2852 | io_mapping_fini(&ggtt->mappable); |
90d0a0e8 | 2853 | } |
70e32544 | 2854 | |
2c642b07 | 2855 | static unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl) |
e76e9aeb BW |
2856 | { |
2857 | snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT; | |
2858 | snb_gmch_ctl &= SNB_GMCH_GGMS_MASK; | |
2859 | return snb_gmch_ctl << 20; | |
2860 | } | |
2861 | ||
2c642b07 | 2862 | static unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl) |
9459d252 BW |
2863 | { |
2864 | bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT; | |
2865 | bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK; | |
2866 | if (bdw_gmch_ctl) | |
2867 | bdw_gmch_ctl = 1 << bdw_gmch_ctl; | |
562d55d9 BW |
2868 | |
2869 | #ifdef CONFIG_X86_32 | |
2870 | /* Limit 32b platforms to a 2GB GGTT: 4 << 20 / pte size * PAGE_SIZE */ | |
2871 | if (bdw_gmch_ctl > 4) | |
2872 | bdw_gmch_ctl = 4; | |
2873 | #endif | |
2874 | ||
9459d252 BW |
2875 | return bdw_gmch_ctl << 20; |
2876 | } | |
2877 | ||
2c642b07 | 2878 | static unsigned int chv_get_total_gtt_size(u16 gmch_ctrl) |
d7f25f23 DL |
2879 | { |
2880 | gmch_ctrl >>= SNB_GMCH_GGMS_SHIFT; | |
2881 | gmch_ctrl &= SNB_GMCH_GGMS_MASK; | |
2882 | ||
2883 | if (gmch_ctrl) | |
2884 | return 1 << (20 + gmch_ctrl); | |
2885 | ||
2886 | return 0; | |
2887 | } | |
2888 | ||
2c642b07 | 2889 | static size_t gen6_get_stolen_size(u16 snb_gmch_ctl) |
e76e9aeb BW |
2890 | { |
2891 | snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT; | |
2892 | snb_gmch_ctl &= SNB_GMCH_GMS_MASK; | |
2893 | return snb_gmch_ctl << 25; /* 32 MB units */ | |
2894 | } | |
2895 | ||
2c642b07 | 2896 | static size_t gen8_get_stolen_size(u16 bdw_gmch_ctl) |
9459d252 BW |
2897 | { |
2898 | bdw_gmch_ctl >>= BDW_GMCH_GMS_SHIFT; | |
2899 | bdw_gmch_ctl &= BDW_GMCH_GMS_MASK; | |
2900 | return bdw_gmch_ctl << 25; /* 32 MB units */ | |
2901 | } | |
2902 | ||
d7f25f23 DL |
2903 | static size_t chv_get_stolen_size(u16 gmch_ctrl) |
2904 | { | |
2905 | gmch_ctrl >>= SNB_GMCH_GMS_SHIFT; | |
2906 | gmch_ctrl &= SNB_GMCH_GMS_MASK; | |
2907 | ||
2908 | /* | |
2909 | * 0x0 to 0x10: 32MB increments starting at 0MB | |
2910 | * 0x11 to 0x16: 4MB increments starting at 8MB | |
2911 | * 0x17 to 0x1d: 4MB increments start at 36MB | |
2912 | */ | |
2913 | if (gmch_ctrl < 0x11) | |
2914 | return gmch_ctrl << 25; | |
2915 | else if (gmch_ctrl < 0x17) | |
2916 | return (gmch_ctrl - 0x11 + 2) << 22; | |
2917 | else | |
2918 | return (gmch_ctrl - 0x17 + 9) << 22; | |
2919 | } | |
2920 | ||
66375014 DL |
2921 | static size_t gen9_get_stolen_size(u16 gen9_gmch_ctl) |
2922 | { | |
2923 | gen9_gmch_ctl >>= BDW_GMCH_GMS_SHIFT; | |
2924 | gen9_gmch_ctl &= BDW_GMCH_GMS_MASK; | |
2925 | ||
2926 | if (gen9_gmch_ctl < 0xf0) | |
2927 | return gen9_gmch_ctl << 25; /* 32 MB units */ | |
2928 | else | |
2929 | /* 4MB increments starting at 0xf0 for 4MB */ | |
2930 | return (gen9_gmch_ctl - 0xf0 + 1) << 22; | |
2931 | } | |
2932 | ||
34c998b4 | 2933 | static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size) |
63340133 | 2934 | { |
34c998b4 | 2935 | struct pci_dev *pdev = ggtt->base.dev->pdev; |
34c998b4 | 2936 | phys_addr_t phys_addr; |
8bcdd0f7 | 2937 | int ret; |
63340133 BW |
2938 | |
2939 | /* For Modern GENs the PTEs and register space are split in the BAR */ | |
34c998b4 | 2940 | phys_addr = pci_resource_start(pdev, 0) + pci_resource_len(pdev, 0) / 2; |
63340133 | 2941 | |
2a073f89 ID |
2942 | /* |
2943 | * On BXT writes larger than 64 bit to the GTT pagetable range will be | |
2944 | * dropped. For WC mappings in general we have 64 byte burst writes | |
2945 | * when the WC buffer is flushed, so we can't use it, but have to | |
2946 | * resort to an uncached mapping. The WC issue is easily caught by the | |
2947 | * readback check when writing GTT PTE entries. | |
2948 | */ | |
e2d214ae | 2949 | if (IS_BROXTON(to_i915(ggtt->base.dev))) |
34c998b4 | 2950 | ggtt->gsm = ioremap_nocache(phys_addr, size); |
2a073f89 | 2951 | else |
34c998b4 | 2952 | ggtt->gsm = ioremap_wc(phys_addr, size); |
72e96d64 | 2953 | if (!ggtt->gsm) { |
34c998b4 | 2954 | DRM_ERROR("Failed to map the ggtt page table\n"); |
63340133 BW |
2955 | return -ENOMEM; |
2956 | } | |
2957 | ||
bb8f9cff CW |
2958 | ret = setup_scratch_page(ggtt->base.dev, |
2959 | &ggtt->base.scratch_page, | |
2960 | GFP_DMA32); | |
8bcdd0f7 | 2961 | if (ret) { |
63340133 BW |
2962 | DRM_ERROR("Scratch setup failed\n"); |
2963 | /* iounmap will also get called at remove, but meh */ | |
72e96d64 | 2964 | iounmap(ggtt->gsm); |
8bcdd0f7 | 2965 | return ret; |
63340133 BW |
2966 | } |
2967 | ||
4ad2af1e | 2968 | return 0; |
63340133 BW |
2969 | } |
2970 | ||
fbe5d36e BW |
2971 | /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability |
2972 | * bits. When using advanced contexts each context stores its own PAT, but | |
2973 | * writing this data shouldn't be harmful even in those cases. */ | |
ee0ce478 | 2974 | static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv) |
fbe5d36e | 2975 | { |
fbe5d36e BW |
2976 | uint64_t pat; |
2977 | ||
2978 | pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC) | /* for normal objects, no eLLC */ | |
2979 | GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something pointing to ptes? */ | |
2980 | GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC) | /* for scanout with eLLC */ | |
2981 | GEN8_PPAT(3, GEN8_PPAT_UC) | /* Uncached objects, mostly for scanout */ | |
2982 | GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) | | |
2983 | GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) | | |
2984 | GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) | | |
2985 | GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3)); | |
2986 | ||
2d1fe073 | 2987 | if (!USES_PPGTT(dev_priv)) |
d6a8b72e RV |
2988 | /* Spec: "For GGTT, there is NO pat_sel[2:0] from the entry, |
2989 | * so RTL will always use the value corresponding to | |
2990 | * pat_sel = 000". | |
2991 | * So let's disable cache for GGTT to avoid screen corruptions. | |
2992 | * MOCS still can be used though. | |
2993 | * - System agent ggtt writes (i.e. cpu gtt mmaps) already work | |
2994 | * before this patch, i.e. the same uncached + snooping access | |
2995 | * like on gen6/7 seems to be in effect. | |
2996 | * - So this just fixes blitter/render access. Again it looks | |
2997 | * like it's not just uncached access, but uncached + snooping. | |
2998 | * So we can still hold onto all our assumptions wrt cpu | |
2999 | * clflushing on LLC machines. | |
3000 | */ | |
3001 | pat = GEN8_PPAT(0, GEN8_PPAT_UC); | |
3002 | ||
fbe5d36e BW |
3003 | /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b |
3004 | * write would work. */ | |
7e435ad2 VS |
3005 | I915_WRITE(GEN8_PRIVATE_PAT_LO, pat); |
3006 | I915_WRITE(GEN8_PRIVATE_PAT_HI, pat >> 32); | |
fbe5d36e BW |
3007 | } |
3008 | ||
ee0ce478 VS |
3009 | static void chv_setup_private_ppat(struct drm_i915_private *dev_priv) |
3010 | { | |
3011 | uint64_t pat; | |
3012 | ||
3013 | /* | |
3014 | * Map WB on BDW to snooped on CHV. | |
3015 | * | |
3016 | * Only the snoop bit has meaning for CHV, the rest is | |
3017 | * ignored. | |
3018 | * | |
cf3d262e VS |
3019 | * The hardware will never snoop for certain types of accesses: |
3020 | * - CPU GTT (GMADR->GGTT->no snoop->memory) | |
3021 | * - PPGTT page tables | |
3022 | * - some other special cycles | |
3023 | * | |
3024 | * As with BDW, we also need to consider the following for GT accesses: | |
3025 | * "For GGTT, there is NO pat_sel[2:0] from the entry, | |
3026 | * so RTL will always use the value corresponding to | |
3027 | * pat_sel = 000". | |
3028 | * Which means we must set the snoop bit in PAT entry 0 | |
3029 | * in order to keep the global status page working. | |
ee0ce478 VS |
3030 | */ |
3031 | pat = GEN8_PPAT(0, CHV_PPAT_SNOOP) | | |
3032 | GEN8_PPAT(1, 0) | | |
3033 | GEN8_PPAT(2, 0) | | |
3034 | GEN8_PPAT(3, 0) | | |
3035 | GEN8_PPAT(4, CHV_PPAT_SNOOP) | | |
3036 | GEN8_PPAT(5, CHV_PPAT_SNOOP) | | |
3037 | GEN8_PPAT(6, CHV_PPAT_SNOOP) | | |
3038 | GEN8_PPAT(7, CHV_PPAT_SNOOP); | |
3039 | ||
7e435ad2 VS |
3040 | I915_WRITE(GEN8_PRIVATE_PAT_LO, pat); |
3041 | I915_WRITE(GEN8_PRIVATE_PAT_HI, pat >> 32); | |
ee0ce478 VS |
3042 | } |
3043 | ||
34c998b4 CW |
3044 | static void gen6_gmch_remove(struct i915_address_space *vm) |
3045 | { | |
3046 | struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm); | |
3047 | ||
3048 | iounmap(ggtt->gsm); | |
8bcdd0f7 | 3049 | cleanup_scratch_page(vm->dev, &vm->scratch_page); |
34c998b4 CW |
3050 | } |
3051 | ||
d507d735 | 3052 | static int gen8_gmch_probe(struct i915_ggtt *ggtt) |
63340133 | 3053 | { |
97d6d7ab CW |
3054 | struct drm_i915_private *dev_priv = to_i915(ggtt->base.dev); |
3055 | struct pci_dev *pdev = dev_priv->drm.pdev; | |
34c998b4 | 3056 | unsigned int size; |
63340133 | 3057 | u16 snb_gmch_ctl; |
63340133 BW |
3058 | |
3059 | /* TODO: We're not aware of mappable constraints on gen8 yet */ | |
97d6d7ab CW |
3060 | ggtt->mappable_base = pci_resource_start(pdev, 2); |
3061 | ggtt->mappable_end = pci_resource_len(pdev, 2); | |
63340133 | 3062 | |
97d6d7ab CW |
3063 | if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(39))) |
3064 | pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(39)); | |
63340133 | 3065 | |
97d6d7ab | 3066 | pci_read_config_word(pdev, SNB_GMCH_CTRL, &snb_gmch_ctl); |
63340133 | 3067 | |
97d6d7ab | 3068 | if (INTEL_GEN(dev_priv) >= 9) { |
d507d735 | 3069 | ggtt->stolen_size = gen9_get_stolen_size(snb_gmch_ctl); |
34c998b4 | 3070 | size = gen8_get_total_gtt_size(snb_gmch_ctl); |
97d6d7ab | 3071 | } else if (IS_CHERRYVIEW(dev_priv)) { |
d507d735 | 3072 | ggtt->stolen_size = chv_get_stolen_size(snb_gmch_ctl); |
34c998b4 | 3073 | size = chv_get_total_gtt_size(snb_gmch_ctl); |
d7f25f23 | 3074 | } else { |
d507d735 | 3075 | ggtt->stolen_size = gen8_get_stolen_size(snb_gmch_ctl); |
34c998b4 | 3076 | size = gen8_get_total_gtt_size(snb_gmch_ctl); |
d7f25f23 | 3077 | } |
63340133 | 3078 | |
34c998b4 | 3079 | ggtt->base.total = (size / sizeof(gen8_pte_t)) << PAGE_SHIFT; |
63340133 | 3080 | |
97d6d7ab | 3081 | if (IS_CHERRYVIEW(dev_priv) || IS_BROXTON(dev_priv)) |
ee0ce478 VS |
3082 | chv_setup_private_ppat(dev_priv); |
3083 | else | |
3084 | bdw_setup_private_ppat(dev_priv); | |
fbe5d36e | 3085 | |
34c998b4 | 3086 | ggtt->base.cleanup = gen6_gmch_remove; |
d507d735 JL |
3087 | ggtt->base.bind_vma = ggtt_bind_vma; |
3088 | ggtt->base.unbind_vma = ggtt_unbind_vma; | |
d6473f56 | 3089 | ggtt->base.insert_page = gen8_ggtt_insert_page; |
f7770bfd | 3090 | ggtt->base.clear_range = nop_clear_range; |
48f112fe | 3091 | if (!USES_FULL_PPGTT(dev_priv) || intel_scanout_needs_vtd_wa(dev_priv)) |
f7770bfd CW |
3092 | ggtt->base.clear_range = gen8_ggtt_clear_range; |
3093 | ||
3094 | ggtt->base.insert_entries = gen8_ggtt_insert_entries; | |
3095 | if (IS_CHERRYVIEW(dev_priv)) | |
3096 | ggtt->base.insert_entries = gen8_ggtt_insert_entries__BKL; | |
3097 | ||
34c998b4 | 3098 | return ggtt_probe_common(ggtt, size); |
63340133 BW |
3099 | } |
3100 | ||
d507d735 | 3101 | static int gen6_gmch_probe(struct i915_ggtt *ggtt) |
e76e9aeb | 3102 | { |
97d6d7ab CW |
3103 | struct drm_i915_private *dev_priv = to_i915(ggtt->base.dev); |
3104 | struct pci_dev *pdev = dev_priv->drm.pdev; | |
34c998b4 | 3105 | unsigned int size; |
e76e9aeb | 3106 | u16 snb_gmch_ctl; |
e76e9aeb | 3107 | |
97d6d7ab CW |
3108 | ggtt->mappable_base = pci_resource_start(pdev, 2); |
3109 | ggtt->mappable_end = pci_resource_len(pdev, 2); | |
41907ddc | 3110 | |
baa09f5f BW |
3111 | /* 64/512MB is the current min/max we actually know of, but this is just |
3112 | * a coarse sanity check. | |
e76e9aeb | 3113 | */ |
34c998b4 | 3114 | if (ggtt->mappable_end < (64<<20) || ggtt->mappable_end > (512<<20)) { |
d507d735 | 3115 | DRM_ERROR("Unknown GMADR size (%llx)\n", ggtt->mappable_end); |
baa09f5f | 3116 | return -ENXIO; |
e76e9aeb BW |
3117 | } |
3118 | ||
97d6d7ab CW |
3119 | if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(40))) |
3120 | pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(40)); | |
3121 | pci_read_config_word(pdev, SNB_GMCH_CTRL, &snb_gmch_ctl); | |
e76e9aeb | 3122 | |
d507d735 | 3123 | ggtt->stolen_size = gen6_get_stolen_size(snb_gmch_ctl); |
e76e9aeb | 3124 | |
34c998b4 CW |
3125 | size = gen6_get_total_gtt_size(snb_gmch_ctl); |
3126 | ggtt->base.total = (size / sizeof(gen6_pte_t)) << PAGE_SHIFT; | |
e76e9aeb | 3127 | |
d507d735 | 3128 | ggtt->base.clear_range = gen6_ggtt_clear_range; |
d6473f56 | 3129 | ggtt->base.insert_page = gen6_ggtt_insert_page; |
d507d735 JL |
3130 | ggtt->base.insert_entries = gen6_ggtt_insert_entries; |
3131 | ggtt->base.bind_vma = ggtt_bind_vma; | |
3132 | ggtt->base.unbind_vma = ggtt_unbind_vma; | |
34c998b4 CW |
3133 | ggtt->base.cleanup = gen6_gmch_remove; |
3134 | ||
3135 | if (HAS_EDRAM(dev_priv)) | |
3136 | ggtt->base.pte_encode = iris_pte_encode; | |
3137 | else if (IS_HASWELL(dev_priv)) | |
3138 | ggtt->base.pte_encode = hsw_pte_encode; | |
3139 | else if (IS_VALLEYVIEW(dev_priv)) | |
3140 | ggtt->base.pte_encode = byt_pte_encode; | |
3141 | else if (INTEL_GEN(dev_priv) >= 7) | |
3142 | ggtt->base.pte_encode = ivb_pte_encode; | |
3143 | else | |
3144 | ggtt->base.pte_encode = snb_pte_encode; | |
7faf1ab2 | 3145 | |
34c998b4 | 3146 | return ggtt_probe_common(ggtt, size); |
e76e9aeb BW |
3147 | } |
3148 | ||
34c998b4 | 3149 | static void i915_gmch_remove(struct i915_address_space *vm) |
e76e9aeb | 3150 | { |
34c998b4 | 3151 | intel_gmch_remove(); |
644ec02b | 3152 | } |
baa09f5f | 3153 | |
d507d735 | 3154 | static int i915_gmch_probe(struct i915_ggtt *ggtt) |
baa09f5f | 3155 | { |
97d6d7ab | 3156 | struct drm_i915_private *dev_priv = to_i915(ggtt->base.dev); |
baa09f5f BW |
3157 | int ret; |
3158 | ||
91c8a326 | 3159 | ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->drm.pdev, NULL); |
baa09f5f BW |
3160 | if (!ret) { |
3161 | DRM_ERROR("failed to set up gmch\n"); | |
3162 | return -EIO; | |
3163 | } | |
3164 | ||
d507d735 JL |
3165 | intel_gtt_get(&ggtt->base.total, &ggtt->stolen_size, |
3166 | &ggtt->mappable_base, &ggtt->mappable_end); | |
baa09f5f | 3167 | |
97d6d7ab | 3168 | ggtt->do_idle_maps = needs_idle_maps(dev_priv); |
d6473f56 | 3169 | ggtt->base.insert_page = i915_ggtt_insert_page; |
d507d735 JL |
3170 | ggtt->base.insert_entries = i915_ggtt_insert_entries; |
3171 | ggtt->base.clear_range = i915_ggtt_clear_range; | |
3172 | ggtt->base.bind_vma = ggtt_bind_vma; | |
3173 | ggtt->base.unbind_vma = ggtt_unbind_vma; | |
34c998b4 | 3174 | ggtt->base.cleanup = i915_gmch_remove; |
baa09f5f | 3175 | |
d507d735 | 3176 | if (unlikely(ggtt->do_idle_maps)) |
c0a7f818 CW |
3177 | DRM_INFO("applying Ironlake quirks for intel_iommu\n"); |
3178 | ||
baa09f5f BW |
3179 | return 0; |
3180 | } | |
3181 | ||
d85489d3 | 3182 | /** |
0088e522 | 3183 | * i915_ggtt_probe_hw - Probe GGTT hardware location |
97d6d7ab | 3184 | * @dev_priv: i915 device |
d85489d3 | 3185 | */ |
97d6d7ab | 3186 | int i915_ggtt_probe_hw(struct drm_i915_private *dev_priv) |
baa09f5f | 3187 | { |
62106b4f | 3188 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
baa09f5f BW |
3189 | int ret; |
3190 | ||
97d6d7ab | 3191 | ggtt->base.dev = &dev_priv->drm; |
c114f76a | 3192 | |
34c998b4 CW |
3193 | if (INTEL_GEN(dev_priv) <= 5) |
3194 | ret = i915_gmch_probe(ggtt); | |
3195 | else if (INTEL_GEN(dev_priv) < 8) | |
3196 | ret = gen6_gmch_probe(ggtt); | |
3197 | else | |
3198 | ret = gen8_gmch_probe(ggtt); | |
a54c0c27 | 3199 | if (ret) |
baa09f5f | 3200 | return ret; |
baa09f5f | 3201 | |
c890e2d5 CW |
3202 | if ((ggtt->base.total - 1) >> 32) { |
3203 | DRM_ERROR("We never expected a Global GTT with more than 32bits" | |
f6b9d5ca | 3204 | " of address space! Found %lldM!\n", |
c890e2d5 CW |
3205 | ggtt->base.total >> 20); |
3206 | ggtt->base.total = 1ULL << 32; | |
3207 | ggtt->mappable_end = min(ggtt->mappable_end, ggtt->base.total); | |
3208 | } | |
3209 | ||
f6b9d5ca CW |
3210 | if (ggtt->mappable_end > ggtt->base.total) { |
3211 | DRM_ERROR("mappable aperture extends past end of GGTT," | |
3212 | " aperture=%llx, total=%llx\n", | |
3213 | ggtt->mappable_end, ggtt->base.total); | |
3214 | ggtt->mappable_end = ggtt->base.total; | |
3215 | } | |
3216 | ||
baa09f5f | 3217 | /* GMADR is the PCI mmio aperture into the global GTT. */ |
c44ef60e | 3218 | DRM_INFO("Memory usable by graphics device = %lluM\n", |
62106b4f JL |
3219 | ggtt->base.total >> 20); |
3220 | DRM_DEBUG_DRIVER("GMADR size = %lldM\n", ggtt->mappable_end >> 20); | |
3221 | DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", ggtt->stolen_size >> 20); | |
5db6c735 DV |
3222 | #ifdef CONFIG_INTEL_IOMMU |
3223 | if (intel_iommu_gfx_mapped) | |
3224 | DRM_INFO("VT-d active for gfx access\n"); | |
3225 | #endif | |
baa09f5f BW |
3226 | |
3227 | return 0; | |
0088e522 CW |
3228 | } |
3229 | ||
3230 | /** | |
3231 | * i915_ggtt_init_hw - Initialize GGTT hardware | |
97d6d7ab | 3232 | * @dev_priv: i915 device |
0088e522 | 3233 | */ |
97d6d7ab | 3234 | int i915_ggtt_init_hw(struct drm_i915_private *dev_priv) |
0088e522 | 3235 | { |
0088e522 CW |
3236 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
3237 | int ret; | |
3238 | ||
f6b9d5ca CW |
3239 | INIT_LIST_HEAD(&dev_priv->vm_list); |
3240 | ||
3241 | /* Subtract the guard page before address space initialization to | |
3242 | * shrink the range used by drm_mm. | |
3243 | */ | |
80b204bc | 3244 | mutex_lock(&dev_priv->drm.struct_mutex); |
f6b9d5ca | 3245 | ggtt->base.total -= PAGE_SIZE; |
80b204bc | 3246 | i915_address_space_init(&ggtt->base, dev_priv, "[global]"); |
f6b9d5ca CW |
3247 | ggtt->base.total += PAGE_SIZE; |
3248 | if (!HAS_LLC(dev_priv)) | |
3249 | ggtt->base.mm.color_adjust = i915_gtt_color_adjust; | |
80b204bc | 3250 | mutex_unlock(&dev_priv->drm.struct_mutex); |
f6b9d5ca | 3251 | |
f7bbe788 CW |
3252 | if (!io_mapping_init_wc(&dev_priv->ggtt.mappable, |
3253 | dev_priv->ggtt.mappable_base, | |
3254 | dev_priv->ggtt.mappable_end)) { | |
f6b9d5ca CW |
3255 | ret = -EIO; |
3256 | goto out_gtt_cleanup; | |
3257 | } | |
3258 | ||
3259 | ggtt->mtrr = arch_phys_wc_add(ggtt->mappable_base, ggtt->mappable_end); | |
3260 | ||
0088e522 CW |
3261 | /* |
3262 | * Initialise stolen early so that we may reserve preallocated | |
3263 | * objects for the BIOS to KMS transition. | |
3264 | */ | |
97d6d7ab | 3265 | ret = i915_gem_init_stolen(&dev_priv->drm); |
0088e522 CW |
3266 | if (ret) |
3267 | goto out_gtt_cleanup; | |
3268 | ||
3269 | return 0; | |
a4eba47b ID |
3270 | |
3271 | out_gtt_cleanup: | |
72e96d64 | 3272 | ggtt->base.cleanup(&ggtt->base); |
a4eba47b | 3273 | return ret; |
baa09f5f | 3274 | } |
6f65e29a | 3275 | |
97d6d7ab | 3276 | int i915_ggtt_enable_hw(struct drm_i915_private *dev_priv) |
ac840ae5 | 3277 | { |
97d6d7ab | 3278 | if (INTEL_GEN(dev_priv) < 6 && !intel_enable_gtt()) |
ac840ae5 VS |
3279 | return -EIO; |
3280 | ||
3281 | return 0; | |
3282 | } | |
3283 | ||
fa42331b DV |
3284 | void i915_gem_restore_gtt_mappings(struct drm_device *dev) |
3285 | { | |
72e96d64 JL |
3286 | struct drm_i915_private *dev_priv = to_i915(dev); |
3287 | struct i915_ggtt *ggtt = &dev_priv->ggtt; | |
fbb30a5c | 3288 | struct drm_i915_gem_object *obj, *on; |
fa42331b | 3289 | |
dc97997a | 3290 | i915_check_and_clear_faults(dev_priv); |
fa42331b DV |
3291 | |
3292 | /* First fill our portion of the GTT with scratch pages */ | |
4fb84d99 | 3293 | ggtt->base.clear_range(&ggtt->base, ggtt->base.start, ggtt->base.total); |
fa42331b | 3294 | |
fbb30a5c CW |
3295 | ggtt->base.closed = true; /* skip rewriting PTE on VMA unbind */ |
3296 | ||
3297 | /* clflush objects bound into the GGTT and rebind them. */ | |
3298 | list_for_each_entry_safe(obj, on, | |
3299 | &dev_priv->mm.bound_list, global_list) { | |
3300 | bool ggtt_bound = false; | |
3301 | struct i915_vma *vma; | |
3302 | ||
1c7f4bca | 3303 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
72e96d64 | 3304 | if (vma->vm != &ggtt->base) |
2c3d9984 | 3305 | continue; |
fa42331b | 3306 | |
fbb30a5c CW |
3307 | if (!i915_vma_unbind(vma)) |
3308 | continue; | |
3309 | ||
2c3d9984 TU |
3310 | WARN_ON(i915_vma_bind(vma, obj->cache_level, |
3311 | PIN_UPDATE)); | |
fbb30a5c | 3312 | ggtt_bound = true; |
2c3d9984 TU |
3313 | } |
3314 | ||
fbb30a5c | 3315 | if (ggtt_bound) |
975f7ff4 | 3316 | WARN_ON(i915_gem_object_set_to_gtt_domain(obj, false)); |
2c3d9984 | 3317 | } |
fa42331b | 3318 | |
fbb30a5c CW |
3319 | ggtt->base.closed = false; |
3320 | ||
fa42331b | 3321 | if (INTEL_INFO(dev)->gen >= 8) { |
e2d214ae | 3322 | if (IS_CHERRYVIEW(dev_priv) || IS_BROXTON(dev_priv)) |
fa42331b DV |
3323 | chv_setup_private_ppat(dev_priv); |
3324 | else | |
3325 | bdw_setup_private_ppat(dev_priv); | |
3326 | ||
3327 | return; | |
3328 | } | |
3329 | ||
3330 | if (USES_PPGTT(dev)) { | |
72e96d64 JL |
3331 | struct i915_address_space *vm; |
3332 | ||
fa42331b DV |
3333 | list_for_each_entry(vm, &dev_priv->vm_list, global_link) { |
3334 | /* TODO: Perhaps it shouldn't be gen6 specific */ | |
3335 | ||
e5716f55 | 3336 | struct i915_hw_ppgtt *ppgtt; |
fa42331b | 3337 | |
2bfa996e | 3338 | if (i915_is_ggtt(vm)) |
fa42331b | 3339 | ppgtt = dev_priv->mm.aliasing_ppgtt; |
e5716f55 JL |
3340 | else |
3341 | ppgtt = i915_vm_to_ppgtt(vm); | |
fa42331b DV |
3342 | |
3343 | gen6_write_page_range(dev_priv, &ppgtt->pd, | |
3344 | 0, ppgtt->base.total); | |
3345 | } | |
3346 | } | |
3347 | ||
3348 | i915_ggtt_flush(dev_priv); | |
3349 | } | |
3350 | ||
b0decaf7 CW |
3351 | static void |
3352 | i915_vma_retire(struct i915_gem_active *active, | |
3353 | struct drm_i915_gem_request *rq) | |
3354 | { | |
3355 | const unsigned int idx = rq->engine->id; | |
3356 | struct i915_vma *vma = | |
3357 | container_of(active, struct i915_vma, last_read[idx]); | |
d07f0e59 | 3358 | struct drm_i915_gem_object *obj = vma->obj; |
b0decaf7 CW |
3359 | |
3360 | GEM_BUG_ON(!i915_vma_has_active_engine(vma, idx)); | |
3361 | ||
3362 | i915_vma_clear_active(vma, idx); | |
3363 | if (i915_vma_is_active(vma)) | |
3364 | return; | |
3365 | ||
3366 | list_move_tail(&vma->vm_link, &vma->vm->inactive_list); | |
3272db53 | 3367 | if (unlikely(i915_vma_is_closed(vma) && !i915_vma_is_pinned(vma))) |
b1f788c6 | 3368 | WARN_ON(i915_vma_unbind(vma)); |
d07f0e59 CW |
3369 | |
3370 | GEM_BUG_ON(!i915_gem_object_is_active(obj)); | |
3371 | if (--obj->active_count) | |
3372 | return; | |
3373 | ||
3374 | /* Bump our place on the bound list to keep it roughly in LRU order | |
3375 | * so that we don't steal from recently used but inactive objects | |
3376 | * (unless we are forced to ofc!) | |
3377 | */ | |
3378 | if (obj->bind_count) | |
3379 | list_move_tail(&obj->global_list, &rq->i915->mm.bound_list); | |
3380 | ||
3381 | obj->mm.dirty = true; /* be paranoid */ | |
3382 | ||
3383 | if (i915_gem_object_has_active_reference(obj)) { | |
3384 | i915_gem_object_clear_active_reference(obj); | |
3385 | i915_gem_object_put(obj); | |
3386 | } | |
3387 | } | |
3388 | ||
3389 | static void | |
3390 | i915_ggtt_retire__write(struct i915_gem_active *active, | |
3391 | struct drm_i915_gem_request *request) | |
3392 | { | |
3393 | struct i915_vma *vma = | |
3394 | container_of(active, struct i915_vma, last_write); | |
3395 | ||
3396 | intel_fb_obj_flush(vma->obj, true, ORIGIN_CS); | |
b1f788c6 CW |
3397 | } |
3398 | ||
3399 | void i915_vma_destroy(struct i915_vma *vma) | |
3400 | { | |
3401 | GEM_BUG_ON(vma->node.allocated); | |
3402 | GEM_BUG_ON(i915_vma_is_active(vma)); | |
3272db53 | 3403 | GEM_BUG_ON(!i915_vma_is_closed(vma)); |
49ef5294 | 3404 | GEM_BUG_ON(vma->fence); |
b1f788c6 | 3405 | |
db6c2b41 | 3406 | rb_erase(&vma->obj_node, &vma->obj->vma_tree); |
b1f788c6 | 3407 | list_del(&vma->vm_link); |
3272db53 | 3408 | if (!i915_vma_is_ggtt(vma)) |
b1f788c6 CW |
3409 | i915_ppgtt_put(i915_vm_to_ppgtt(vma->vm)); |
3410 | ||
3411 | kmem_cache_free(to_i915(vma->obj->base.dev)->vmas, vma); | |
3412 | } | |
3413 | ||
3414 | void i915_vma_close(struct i915_vma *vma) | |
3415 | { | |
3272db53 CW |
3416 | GEM_BUG_ON(i915_vma_is_closed(vma)); |
3417 | vma->flags |= I915_VMA_CLOSED; | |
b1f788c6 CW |
3418 | |
3419 | list_del_init(&vma->obj_link); | |
20dfbde4 | 3420 | if (!i915_vma_is_active(vma) && !i915_vma_is_pinned(vma)) |
df0e9a28 | 3421 | WARN_ON(i915_vma_unbind(vma)); |
b0decaf7 CW |
3422 | } |
3423 | ||
db6c2b41 CW |
3424 | static inline long vma_compare(struct i915_vma *vma, |
3425 | struct i915_address_space *vm, | |
3426 | const struct i915_ggtt_view *view) | |
3427 | { | |
3428 | GEM_BUG_ON(view && !i915_vma_is_ggtt(vma)); | |
3429 | ||
3430 | if (vma->vm != vm) | |
3431 | return vma->vm - vm; | |
3432 | ||
3433 | if (!view) | |
3434 | return vma->ggtt_view.type; | |
3435 | ||
3436 | if (vma->ggtt_view.type != view->type) | |
3437 | return vma->ggtt_view.type - view->type; | |
3438 | ||
3439 | return memcmp(&vma->ggtt_view.params, | |
3440 | &view->params, | |
3441 | sizeof(view->params)); | |
3442 | } | |
3443 | ||
ec7adb6e | 3444 | static struct i915_vma * |
058d88c4 CW |
3445 | __i915_vma_create(struct drm_i915_gem_object *obj, |
3446 | struct i915_address_space *vm, | |
3447 | const struct i915_ggtt_view *view) | |
6f65e29a | 3448 | { |
dabde5c7 | 3449 | struct i915_vma *vma; |
db6c2b41 | 3450 | struct rb_node *rb, **p; |
b0decaf7 | 3451 | int i; |
6f65e29a | 3452 | |
50e046b6 CW |
3453 | GEM_BUG_ON(vm->closed); |
3454 | ||
e20d2ab7 | 3455 | vma = kmem_cache_zalloc(to_i915(obj->base.dev)->vmas, GFP_KERNEL); |
dabde5c7 DC |
3456 | if (vma == NULL) |
3457 | return ERR_PTR(-ENOMEM); | |
ec7adb6e | 3458 | |
6f65e29a | 3459 | INIT_LIST_HEAD(&vma->exec_list); |
b0decaf7 CW |
3460 | for (i = 0; i < ARRAY_SIZE(vma->last_read); i++) |
3461 | init_request_active(&vma->last_read[i], i915_vma_retire); | |
d07f0e59 CW |
3462 | init_request_active(&vma->last_write, |
3463 | i915_is_ggtt(vm) ? i915_ggtt_retire__write : NULL); | |
49ef5294 | 3464 | init_request_active(&vma->last_fence, NULL); |
50e046b6 | 3465 | list_add(&vma->vm_link, &vm->unbound_list); |
6f65e29a BW |
3466 | vma->vm = vm; |
3467 | vma->obj = obj; | |
de180033 | 3468 | vma->size = obj->base.size; |
6f65e29a | 3469 | |
058d88c4 | 3470 | if (view) { |
de180033 CW |
3471 | vma->ggtt_view = *view; |
3472 | if (view->type == I915_GGTT_VIEW_PARTIAL) { | |
3473 | vma->size = view->params.partial.size; | |
3474 | vma->size <<= PAGE_SHIFT; | |
3475 | } else if (view->type == I915_GGTT_VIEW_ROTATED) { | |
3476 | vma->size = | |
3477 | intel_rotation_info_size(&view->params.rotated); | |
3478 | vma->size <<= PAGE_SHIFT; | |
3479 | } | |
058d88c4 CW |
3480 | } |
3481 | ||
3482 | if (i915_is_ggtt(vm)) { | |
3483 | vma->flags |= I915_VMA_GGTT; | |
db6c2b41 | 3484 | list_add(&vma->obj_link, &obj->vma_list); |
de180033 | 3485 | } else { |
596c5923 | 3486 | i915_ppgtt_get(i915_vm_to_ppgtt(vm)); |
db6c2b41 | 3487 | list_add_tail(&vma->obj_link, &obj->vma_list); |
de180033 | 3488 | } |
6f65e29a | 3489 | |
db6c2b41 CW |
3490 | rb = NULL; |
3491 | p = &obj->vma_tree.rb_node; | |
3492 | while (*p) { | |
3493 | struct i915_vma *pos; | |
058d88c4 | 3494 | |
db6c2b41 CW |
3495 | rb = *p; |
3496 | pos = rb_entry(rb, struct i915_vma, obj_node); | |
3497 | if (vma_compare(pos, vm, view) < 0) | |
3498 | p = &rb->rb_right; | |
3499 | else | |
3500 | p = &rb->rb_left; | |
3501 | } | |
3502 | rb_link_node(&vma->obj_node, rb, p); | |
3503 | rb_insert_color(&vma->obj_node, &obj->vma_tree); | |
058d88c4 | 3504 | |
db6c2b41 | 3505 | return vma; |
058d88c4 CW |
3506 | } |
3507 | ||
81a8aa4a CW |
3508 | struct i915_vma * |
3509 | i915_vma_create(struct drm_i915_gem_object *obj, | |
3510 | struct i915_address_space *vm, | |
3511 | const struct i915_ggtt_view *view) | |
3512 | { | |
4c7d62c6 | 3513 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
81a8aa4a | 3514 | GEM_BUG_ON(view && !i915_is_ggtt(vm)); |
058d88c4 | 3515 | GEM_BUG_ON(i915_gem_obj_to_vma(obj, vm, view)); |
81a8aa4a | 3516 | |
058d88c4 | 3517 | return __i915_vma_create(obj, vm, view); |
81a8aa4a CW |
3518 | } |
3519 | ||
6f65e29a | 3520 | struct i915_vma * |
058d88c4 CW |
3521 | i915_gem_obj_to_vma(struct drm_i915_gem_object *obj, |
3522 | struct i915_address_space *vm, | |
3523 | const struct i915_ggtt_view *view) | |
ec7adb6e | 3524 | { |
db6c2b41 | 3525 | struct rb_node *rb; |
ec7adb6e | 3526 | |
db6c2b41 CW |
3527 | rb = obj->vma_tree.rb_node; |
3528 | while (rb) { | |
3529 | struct i915_vma *vma = rb_entry(rb, struct i915_vma, obj_node); | |
3530 | long cmp; | |
3531 | ||
3532 | cmp = vma_compare(vma, vm, view); | |
3533 | if (cmp == 0) | |
058d88c4 | 3534 | return vma; |
ec7adb6e | 3535 | |
db6c2b41 CW |
3536 | if (cmp < 0) |
3537 | rb = rb->rb_right; | |
3538 | else | |
3539 | rb = rb->rb_left; | |
3540 | } | |
3541 | ||
058d88c4 | 3542 | return NULL; |
ec7adb6e JL |
3543 | } |
3544 | ||
3545 | struct i915_vma * | |
058d88c4 CW |
3546 | i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj, |
3547 | struct i915_address_space *vm, | |
3548 | const struct i915_ggtt_view *view) | |
6f65e29a | 3549 | { |
058d88c4 | 3550 | struct i915_vma *vma; |
ec7adb6e | 3551 | |
4c7d62c6 | 3552 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
058d88c4 | 3553 | GEM_BUG_ON(view && !i915_is_ggtt(vm)); |
de895082 | 3554 | |
058d88c4 | 3555 | vma = i915_gem_obj_to_vma(obj, vm, view); |
db6c2b41 | 3556 | if (!vma) { |
058d88c4 | 3557 | vma = __i915_vma_create(obj, vm, view); |
db6c2b41 CW |
3558 | GEM_BUG_ON(vma != i915_gem_obj_to_vma(obj, vm, view)); |
3559 | } | |
6f65e29a | 3560 | |
3272db53 | 3561 | GEM_BUG_ON(i915_vma_is_closed(vma)); |
6f65e29a BW |
3562 | return vma; |
3563 | } | |
fe14d5f4 | 3564 | |
804beb4b | 3565 | static struct scatterlist * |
2d7f3bdb | 3566 | rotate_pages(const dma_addr_t *in, unsigned int offset, |
804beb4b | 3567 | unsigned int width, unsigned int height, |
87130255 | 3568 | unsigned int stride, |
804beb4b | 3569 | struct sg_table *st, struct scatterlist *sg) |
50470bb0 TU |
3570 | { |
3571 | unsigned int column, row; | |
3572 | unsigned int src_idx; | |
50470bb0 | 3573 | |
50470bb0 | 3574 | for (column = 0; column < width; column++) { |
87130255 | 3575 | src_idx = stride * (height - 1) + column; |
50470bb0 TU |
3576 | for (row = 0; row < height; row++) { |
3577 | st->nents++; | |
3578 | /* We don't need the pages, but need to initialize | |
3579 | * the entries so the sg list can be happily traversed. | |
3580 | * The only thing we need are DMA addresses. | |
3581 | */ | |
3582 | sg_set_page(sg, NULL, PAGE_SIZE, 0); | |
804beb4b | 3583 | sg_dma_address(sg) = in[offset + src_idx]; |
50470bb0 TU |
3584 | sg_dma_len(sg) = PAGE_SIZE; |
3585 | sg = sg_next(sg); | |
87130255 | 3586 | src_idx -= stride; |
50470bb0 TU |
3587 | } |
3588 | } | |
804beb4b TU |
3589 | |
3590 | return sg; | |
50470bb0 TU |
3591 | } |
3592 | ||
3593 | static struct sg_table * | |
6687c906 | 3594 | intel_rotate_fb_obj_pages(const struct intel_rotation_info *rot_info, |
50470bb0 TU |
3595 | struct drm_i915_gem_object *obj) |
3596 | { | |
85d1225e | 3597 | const size_t n_pages = obj->base.size / PAGE_SIZE; |
6687c906 | 3598 | unsigned int size = intel_rotation_info_size(rot_info); |
85d1225e DG |
3599 | struct sgt_iter sgt_iter; |
3600 | dma_addr_t dma_addr; | |
50470bb0 TU |
3601 | unsigned long i; |
3602 | dma_addr_t *page_addr_list; | |
3603 | struct sg_table *st; | |
89e3e142 | 3604 | struct scatterlist *sg; |
1d00dad5 | 3605 | int ret = -ENOMEM; |
50470bb0 | 3606 | |
50470bb0 | 3607 | /* Allocate a temporary list of source pages for random access. */ |
85d1225e | 3608 | page_addr_list = drm_malloc_gfp(n_pages, |
f2a85e19 CW |
3609 | sizeof(dma_addr_t), |
3610 | GFP_TEMPORARY); | |
50470bb0 TU |
3611 | if (!page_addr_list) |
3612 | return ERR_PTR(ret); | |
3613 | ||
3614 | /* Allocate target SG list. */ | |
3615 | st = kmalloc(sizeof(*st), GFP_KERNEL); | |
3616 | if (!st) | |
3617 | goto err_st_alloc; | |
3618 | ||
6687c906 | 3619 | ret = sg_alloc_table(st, size, GFP_KERNEL); |
50470bb0 TU |
3620 | if (ret) |
3621 | goto err_sg_alloc; | |
3622 | ||
3623 | /* Populate source page list from the object. */ | |
3624 | i = 0; | |
a4f5ea64 | 3625 | for_each_sgt_dma(dma_addr, sgt_iter, obj->mm.pages) |
85d1225e | 3626 | page_addr_list[i++] = dma_addr; |
50470bb0 | 3627 | |
85d1225e | 3628 | GEM_BUG_ON(i != n_pages); |
11f20322 VS |
3629 | st->nents = 0; |
3630 | sg = st->sgl; | |
3631 | ||
6687c906 VS |
3632 | for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++) { |
3633 | sg = rotate_pages(page_addr_list, rot_info->plane[i].offset, | |
3634 | rot_info->plane[i].width, rot_info->plane[i].height, | |
3635 | rot_info->plane[i].stride, st, sg); | |
89e3e142 TU |
3636 | } |
3637 | ||
6687c906 VS |
3638 | DRM_DEBUG_KMS("Created rotated page mapping for object size %zu (%ux%u tiles, %u pages)\n", |
3639 | obj->base.size, rot_info->plane[0].width, rot_info->plane[0].height, size); | |
50470bb0 TU |
3640 | |
3641 | drm_free_large(page_addr_list); | |
3642 | ||
3643 | return st; | |
3644 | ||
3645 | err_sg_alloc: | |
3646 | kfree(st); | |
3647 | err_st_alloc: | |
3648 | drm_free_large(page_addr_list); | |
3649 | ||
6687c906 VS |
3650 | DRM_DEBUG_KMS("Failed to create rotated mapping for object size %zu! (%ux%u tiles, %u pages)\n", |
3651 | obj->base.size, rot_info->plane[0].width, rot_info->plane[0].height, size); | |
3652 | ||
50470bb0 TU |
3653 | return ERR_PTR(ret); |
3654 | } | |
ec7adb6e | 3655 | |
8bd7ef16 JL |
3656 | static struct sg_table * |
3657 | intel_partial_pages(const struct i915_ggtt_view *view, | |
3658 | struct drm_i915_gem_object *obj) | |
3659 | { | |
3660 | struct sg_table *st; | |
d2a84a76 CW |
3661 | struct scatterlist *sg, *iter; |
3662 | unsigned int count = view->params.partial.size; | |
3663 | unsigned int offset; | |
8bd7ef16 JL |
3664 | int ret = -ENOMEM; |
3665 | ||
3666 | st = kmalloc(sizeof(*st), GFP_KERNEL); | |
3667 | if (!st) | |
3668 | goto err_st_alloc; | |
3669 | ||
d2a84a76 | 3670 | ret = sg_alloc_table(st, count, GFP_KERNEL); |
8bd7ef16 JL |
3671 | if (ret) |
3672 | goto err_sg_alloc; | |
3673 | ||
d2a84a76 CW |
3674 | iter = i915_gem_object_get_sg(obj, |
3675 | view->params.partial.offset, | |
3676 | &offset); | |
3677 | GEM_BUG_ON(!iter); | |
3678 | ||
8bd7ef16 JL |
3679 | sg = st->sgl; |
3680 | st->nents = 0; | |
d2a84a76 CW |
3681 | do { |
3682 | unsigned int len; | |
8bd7ef16 | 3683 | |
d2a84a76 CW |
3684 | len = min(iter->length - (offset << PAGE_SHIFT), |
3685 | count << PAGE_SHIFT); | |
3686 | sg_set_page(sg, NULL, len, 0); | |
3687 | sg_dma_address(sg) = | |
3688 | sg_dma_address(iter) + (offset << PAGE_SHIFT); | |
3689 | sg_dma_len(sg) = len; | |
8bd7ef16 | 3690 | |
8bd7ef16 | 3691 | st->nents++; |
d2a84a76 CW |
3692 | count -= len >> PAGE_SHIFT; |
3693 | if (count == 0) { | |
3694 | sg_mark_end(sg); | |
3695 | return st; | |
3696 | } | |
8bd7ef16 | 3697 | |
d2a84a76 CW |
3698 | sg = __sg_next(sg); |
3699 | iter = __sg_next(iter); | |
3700 | offset = 0; | |
3701 | } while (1); | |
8bd7ef16 JL |
3702 | |
3703 | err_sg_alloc: | |
3704 | kfree(st); | |
3705 | err_st_alloc: | |
3706 | return ERR_PTR(ret); | |
3707 | } | |
3708 | ||
70b9f6f8 | 3709 | static int |
50470bb0 | 3710 | i915_get_ggtt_vma_pages(struct i915_vma *vma) |
fe14d5f4 | 3711 | { |
50470bb0 TU |
3712 | int ret = 0; |
3713 | ||
247177dd | 3714 | if (vma->pages) |
fe14d5f4 TU |
3715 | return 0; |
3716 | ||
3717 | if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) | |
a4f5ea64 | 3718 | vma->pages = vma->obj->mm.pages; |
50470bb0 | 3719 | else if (vma->ggtt_view.type == I915_GGTT_VIEW_ROTATED) |
247177dd | 3720 | vma->pages = |
11d23e6f | 3721 | intel_rotate_fb_obj_pages(&vma->ggtt_view.params.rotated, vma->obj); |
8bd7ef16 | 3722 | else if (vma->ggtt_view.type == I915_GGTT_VIEW_PARTIAL) |
247177dd | 3723 | vma->pages = intel_partial_pages(&vma->ggtt_view, vma->obj); |
fe14d5f4 TU |
3724 | else |
3725 | WARN_ONCE(1, "GGTT view %u not implemented!\n", | |
3726 | vma->ggtt_view.type); | |
3727 | ||
247177dd | 3728 | if (!vma->pages) { |
ec7adb6e | 3729 | DRM_ERROR("Failed to get pages for GGTT view type %u!\n", |
fe14d5f4 | 3730 | vma->ggtt_view.type); |
50470bb0 | 3731 | ret = -EINVAL; |
247177dd CW |
3732 | } else if (IS_ERR(vma->pages)) { |
3733 | ret = PTR_ERR(vma->pages); | |
3734 | vma->pages = NULL; | |
50470bb0 TU |
3735 | DRM_ERROR("Failed to get pages for VMA view type %u (%d)!\n", |
3736 | vma->ggtt_view.type, ret); | |
fe14d5f4 TU |
3737 | } |
3738 | ||
50470bb0 | 3739 | return ret; |
fe14d5f4 TU |
3740 | } |
3741 | ||
3742 | /** | |
3743 | * i915_vma_bind - Sets up PTEs for an VMA in it's corresponding address space. | |
3744 | * @vma: VMA to map | |
3745 | * @cache_level: mapping cache level | |
3746 | * @flags: flags like global or local mapping | |
3747 | * | |
3748 | * DMA addresses are taken from the scatter-gather table of this object (or of | |
3749 | * this VMA in case of non-default GGTT views) and PTE entries set up. | |
3750 | * Note that DMA addresses are also the only part of the SG table we care about. | |
3751 | */ | |
3752 | int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level, | |
3753 | u32 flags) | |
3754 | { | |
75d04a37 | 3755 | u32 bind_flags; |
3272db53 CW |
3756 | u32 vma_flags; |
3757 | int ret; | |
1d335d1b | 3758 | |
75d04a37 MK |
3759 | if (WARN_ON(flags == 0)) |
3760 | return -EINVAL; | |
1d335d1b | 3761 | |
75d04a37 | 3762 | bind_flags = 0; |
0875546c | 3763 | if (flags & PIN_GLOBAL) |
3272db53 | 3764 | bind_flags |= I915_VMA_GLOBAL_BIND; |
0875546c | 3765 | if (flags & PIN_USER) |
3272db53 | 3766 | bind_flags |= I915_VMA_LOCAL_BIND; |
0875546c | 3767 | |
3272db53 | 3768 | vma_flags = vma->flags & (I915_VMA_GLOBAL_BIND | I915_VMA_LOCAL_BIND); |
0875546c | 3769 | if (flags & PIN_UPDATE) |
3272db53 | 3770 | bind_flags |= vma_flags; |
0875546c | 3771 | else |
3272db53 | 3772 | bind_flags &= ~vma_flags; |
75d04a37 MK |
3773 | if (bind_flags == 0) |
3774 | return 0; | |
3775 | ||
3272db53 | 3776 | if (vma_flags == 0 && vma->vm->allocate_va_range) { |
596c5923 | 3777 | trace_i915_va_alloc(vma); |
75d04a37 MK |
3778 | ret = vma->vm->allocate_va_range(vma->vm, |
3779 | vma->node.start, | |
3780 | vma->node.size); | |
3781 | if (ret) | |
3782 | return ret; | |
3783 | } | |
3784 | ||
3785 | ret = vma->vm->bind_vma(vma, cache_level, bind_flags); | |
70b9f6f8 DV |
3786 | if (ret) |
3787 | return ret; | |
0875546c | 3788 | |
3272db53 | 3789 | vma->flags |= bind_flags; |
fe14d5f4 TU |
3790 | return 0; |
3791 | } | |
91e6711e | 3792 | |
8ef8561f CW |
3793 | void __iomem *i915_vma_pin_iomap(struct i915_vma *vma) |
3794 | { | |
3795 | void __iomem *ptr; | |
3796 | ||
e5cdb22b CW |
3797 | /* Access through the GTT requires the device to be awake. */ |
3798 | assert_rpm_wakelock_held(to_i915(vma->vm->dev)); | |
3799 | ||
8ef8561f | 3800 | lockdep_assert_held(&vma->vm->dev->struct_mutex); |
05a20d09 | 3801 | if (WARN_ON(!i915_vma_is_map_and_fenceable(vma))) |
406ea8d2 | 3802 | return IO_ERR_PTR(-ENODEV); |
8ef8561f | 3803 | |
3272db53 CW |
3804 | GEM_BUG_ON(!i915_vma_is_ggtt(vma)); |
3805 | GEM_BUG_ON((vma->flags & I915_VMA_GLOBAL_BIND) == 0); | |
8ef8561f CW |
3806 | |
3807 | ptr = vma->iomap; | |
3808 | if (ptr == NULL) { | |
f7bbe788 | 3809 | ptr = io_mapping_map_wc(&i915_vm_to_ggtt(vma->vm)->mappable, |
8ef8561f CW |
3810 | vma->node.start, |
3811 | vma->node.size); | |
3812 | if (ptr == NULL) | |
406ea8d2 | 3813 | return IO_ERR_PTR(-ENOMEM); |
8ef8561f CW |
3814 | |
3815 | vma->iomap = ptr; | |
3816 | } | |
3817 | ||
20dfbde4 | 3818 | __i915_vma_pin(vma); |
8ef8561f CW |
3819 | return ptr; |
3820 | } | |
19880c4a CW |
3821 | |
3822 | void i915_vma_unpin_and_release(struct i915_vma **p_vma) | |
3823 | { | |
3824 | struct i915_vma *vma; | |
f8a7fde4 | 3825 | struct drm_i915_gem_object *obj; |
19880c4a CW |
3826 | |
3827 | vma = fetch_and_zero(p_vma); | |
3828 | if (!vma) | |
3829 | return; | |
3830 | ||
f8a7fde4 CW |
3831 | obj = vma->obj; |
3832 | ||
19880c4a | 3833 | i915_vma_unpin(vma); |
f8a7fde4 CW |
3834 | i915_vma_close(vma); |
3835 | ||
3836 | __i915_gem_object_release_unless_active(obj); | |
19880c4a | 3837 | } |