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76aaf220 DV |
1 | /* |
2 | * Copyright © 2010 Daniel Vetter | |
c4ac524c | 3 | * Copyright © 2011-2014 Intel Corporation |
76aaf220 DV |
4 | * |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
22 | * IN THE SOFTWARE. | |
23 | * | |
24 | */ | |
25 | ||
0e46ce2e | 26 | #include <linux/seq_file.h> |
760285e7 DH |
27 | #include <drm/drmP.h> |
28 | #include <drm/i915_drm.h> | |
76aaf220 | 29 | #include "i915_drv.h" |
5dda8fa3 | 30 | #include "i915_vgpu.h" |
76aaf220 DV |
31 | #include "i915_trace.h" |
32 | #include "intel_drv.h" | |
33 | ||
45f8f69a TU |
34 | /** |
35 | * DOC: Global GTT views | |
36 | * | |
37 | * Background and previous state | |
38 | * | |
39 | * Historically objects could exists (be bound) in global GTT space only as | |
40 | * singular instances with a view representing all of the object's backing pages | |
41 | * in a linear fashion. This view will be called a normal view. | |
42 | * | |
43 | * To support multiple views of the same object, where the number of mapped | |
44 | * pages is not equal to the backing store, or where the layout of the pages | |
45 | * is not linear, concept of a GGTT view was added. | |
46 | * | |
47 | * One example of an alternative view is a stereo display driven by a single | |
48 | * image. In this case we would have a framebuffer looking like this | |
49 | * (2x2 pages): | |
50 | * | |
51 | * 12 | |
52 | * 34 | |
53 | * | |
54 | * Above would represent a normal GGTT view as normally mapped for GPU or CPU | |
55 | * rendering. In contrast, fed to the display engine would be an alternative | |
56 | * view which could look something like this: | |
57 | * | |
58 | * 1212 | |
59 | * 3434 | |
60 | * | |
61 | * In this example both the size and layout of pages in the alternative view is | |
62 | * different from the normal view. | |
63 | * | |
64 | * Implementation and usage | |
65 | * | |
66 | * GGTT views are implemented using VMAs and are distinguished via enum | |
67 | * i915_ggtt_view_type and struct i915_ggtt_view. | |
68 | * | |
69 | * A new flavour of core GEM functions which work with GGTT bound objects were | |
ec7adb6e JL |
70 | * added with the _ggtt_ infix, and sometimes with _view postfix to avoid |
71 | * renaming in large amounts of code. They take the struct i915_ggtt_view | |
72 | * parameter encapsulating all metadata required to implement a view. | |
45f8f69a TU |
73 | * |
74 | * As a helper for callers which are only interested in the normal view, | |
75 | * globally const i915_ggtt_view_normal singleton instance exists. All old core | |
76 | * GEM API functions, the ones not taking the view parameter, are operating on, | |
77 | * or with the normal GGTT view. | |
78 | * | |
79 | * Code wanting to add or use a new GGTT view needs to: | |
80 | * | |
81 | * 1. Add a new enum with a suitable name. | |
82 | * 2. Extend the metadata in the i915_ggtt_view structure if required. | |
83 | * 3. Add support to i915_get_vma_pages(). | |
84 | * | |
85 | * New views are required to build a scatter-gather table from within the | |
86 | * i915_get_vma_pages function. This table is stored in the vma.ggtt_view and | |
87 | * exists for the lifetime of an VMA. | |
88 | * | |
89 | * Core API is designed to have copy semantics which means that passed in | |
90 | * struct i915_ggtt_view does not need to be persistent (left around after | |
91 | * calling the core API functions). | |
92 | * | |
93 | */ | |
94 | ||
fe14d5f4 | 95 | const struct i915_ggtt_view i915_ggtt_view_normal; |
9abc4648 JL |
96 | const struct i915_ggtt_view i915_ggtt_view_rotated = { |
97 | .type = I915_GGTT_VIEW_ROTATED | |
98 | }; | |
fe14d5f4 | 99 | |
ee0ce478 VS |
100 | static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv); |
101 | static void chv_setup_private_ppat(struct drm_i915_private *dev_priv); | |
a2319c08 | 102 | |
cfa7c862 DV |
103 | static int sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt) |
104 | { | |
1893a71b CW |
105 | bool has_aliasing_ppgtt; |
106 | bool has_full_ppgtt; | |
107 | ||
108 | has_aliasing_ppgtt = INTEL_INFO(dev)->gen >= 6; | |
109 | has_full_ppgtt = INTEL_INFO(dev)->gen >= 7; | |
1893a71b | 110 | |
71ba2d64 YZ |
111 | if (intel_vgpu_active(dev)) |
112 | has_full_ppgtt = false; /* emulation is too hard */ | |
113 | ||
70ee45e1 DL |
114 | /* |
115 | * We don't allow disabling PPGTT for gen9+ as it's a requirement for | |
116 | * execlists, the sole mechanism available to submit work. | |
117 | */ | |
118 | if (INTEL_INFO(dev)->gen < 9 && | |
119 | (enable_ppgtt == 0 || !has_aliasing_ppgtt)) | |
cfa7c862 DV |
120 | return 0; |
121 | ||
122 | if (enable_ppgtt == 1) | |
123 | return 1; | |
124 | ||
1893a71b | 125 | if (enable_ppgtt == 2 && has_full_ppgtt) |
cfa7c862 DV |
126 | return 2; |
127 | ||
93a25a9e DV |
128 | #ifdef CONFIG_INTEL_IOMMU |
129 | /* Disable ppgtt on SNB if VT-d is on. */ | |
130 | if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) { | |
131 | DRM_INFO("Disabling PPGTT because VT-d is on\n"); | |
cfa7c862 | 132 | return 0; |
93a25a9e DV |
133 | } |
134 | #endif | |
135 | ||
62942ed7 | 136 | /* Early VLV doesn't have this */ |
ca2aed6c VS |
137 | if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && |
138 | dev->pdev->revision < 0xb) { | |
62942ed7 JB |
139 | DRM_DEBUG_DRIVER("disabling PPGTT on pre-B3 step VLV\n"); |
140 | return 0; | |
141 | } | |
142 | ||
2f82bbdf MT |
143 | if (INTEL_INFO(dev)->gen >= 8 && i915.enable_execlists) |
144 | return 2; | |
145 | else | |
146 | return has_aliasing_ppgtt ? 1 : 0; | |
93a25a9e DV |
147 | } |
148 | ||
6f65e29a BW |
149 | static void ppgtt_bind_vma(struct i915_vma *vma, |
150 | enum i915_cache_level cache_level, | |
151 | u32 flags); | |
152 | static void ppgtt_unbind_vma(struct i915_vma *vma); | |
153 | ||
07749ef3 MT |
154 | static inline gen8_pte_t gen8_pte_encode(dma_addr_t addr, |
155 | enum i915_cache_level level, | |
156 | bool valid) | |
94ec8f61 | 157 | { |
07749ef3 | 158 | gen8_pte_t pte = valid ? _PAGE_PRESENT | _PAGE_RW : 0; |
94ec8f61 | 159 | pte |= addr; |
63c42e56 BW |
160 | |
161 | switch (level) { | |
162 | case I915_CACHE_NONE: | |
fbe5d36e | 163 | pte |= PPAT_UNCACHED_INDEX; |
63c42e56 BW |
164 | break; |
165 | case I915_CACHE_WT: | |
166 | pte |= PPAT_DISPLAY_ELLC_INDEX; | |
167 | break; | |
168 | default: | |
169 | pte |= PPAT_CACHED_INDEX; | |
170 | break; | |
171 | } | |
172 | ||
94ec8f61 BW |
173 | return pte; |
174 | } | |
175 | ||
07749ef3 MT |
176 | static inline gen8_pde_t gen8_pde_encode(struct drm_device *dev, |
177 | dma_addr_t addr, | |
178 | enum i915_cache_level level) | |
b1fe6673 | 179 | { |
07749ef3 | 180 | gen8_pde_t pde = _PAGE_PRESENT | _PAGE_RW; |
b1fe6673 BW |
181 | pde |= addr; |
182 | if (level != I915_CACHE_NONE) | |
183 | pde |= PPAT_CACHED_PDE_INDEX; | |
184 | else | |
185 | pde |= PPAT_UNCACHED_INDEX; | |
186 | return pde; | |
187 | } | |
188 | ||
07749ef3 MT |
189 | static gen6_pte_t snb_pte_encode(dma_addr_t addr, |
190 | enum i915_cache_level level, | |
191 | bool valid, u32 unused) | |
54d12527 | 192 | { |
07749ef3 | 193 | gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
54d12527 | 194 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
e7210c3c BW |
195 | |
196 | switch (level) { | |
350ec881 CW |
197 | case I915_CACHE_L3_LLC: |
198 | case I915_CACHE_LLC: | |
199 | pte |= GEN6_PTE_CACHE_LLC; | |
200 | break; | |
201 | case I915_CACHE_NONE: | |
202 | pte |= GEN6_PTE_UNCACHED; | |
203 | break; | |
204 | default: | |
5f77eeb0 | 205 | MISSING_CASE(level); |
350ec881 CW |
206 | } |
207 | ||
208 | return pte; | |
209 | } | |
210 | ||
07749ef3 MT |
211 | static gen6_pte_t ivb_pte_encode(dma_addr_t addr, |
212 | enum i915_cache_level level, | |
213 | bool valid, u32 unused) | |
350ec881 | 214 | { |
07749ef3 | 215 | gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
350ec881 CW |
216 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
217 | ||
218 | switch (level) { | |
219 | case I915_CACHE_L3_LLC: | |
220 | pte |= GEN7_PTE_CACHE_L3_LLC; | |
e7210c3c BW |
221 | break; |
222 | case I915_CACHE_LLC: | |
223 | pte |= GEN6_PTE_CACHE_LLC; | |
224 | break; | |
225 | case I915_CACHE_NONE: | |
9119708c | 226 | pte |= GEN6_PTE_UNCACHED; |
e7210c3c BW |
227 | break; |
228 | default: | |
5f77eeb0 | 229 | MISSING_CASE(level); |
e7210c3c BW |
230 | } |
231 | ||
54d12527 BW |
232 | return pte; |
233 | } | |
234 | ||
07749ef3 MT |
235 | static gen6_pte_t byt_pte_encode(dma_addr_t addr, |
236 | enum i915_cache_level level, | |
237 | bool valid, u32 flags) | |
93c34e70 | 238 | { |
07749ef3 | 239 | gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
93c34e70 KG |
240 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
241 | ||
24f3a8cf AG |
242 | if (!(flags & PTE_READ_ONLY)) |
243 | pte |= BYT_PTE_WRITEABLE; | |
93c34e70 KG |
244 | |
245 | if (level != I915_CACHE_NONE) | |
246 | pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES; | |
247 | ||
248 | return pte; | |
249 | } | |
250 | ||
07749ef3 MT |
251 | static gen6_pte_t hsw_pte_encode(dma_addr_t addr, |
252 | enum i915_cache_level level, | |
253 | bool valid, u32 unused) | |
9119708c | 254 | { |
07749ef3 | 255 | gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
0d8ff15e | 256 | pte |= HSW_PTE_ADDR_ENCODE(addr); |
9119708c KG |
257 | |
258 | if (level != I915_CACHE_NONE) | |
87a6b688 | 259 | pte |= HSW_WB_LLC_AGE3; |
9119708c KG |
260 | |
261 | return pte; | |
262 | } | |
263 | ||
07749ef3 MT |
264 | static gen6_pte_t iris_pte_encode(dma_addr_t addr, |
265 | enum i915_cache_level level, | |
266 | bool valid, u32 unused) | |
4d15c145 | 267 | { |
07749ef3 | 268 | gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
4d15c145 BW |
269 | pte |= HSW_PTE_ADDR_ENCODE(addr); |
270 | ||
651d794f CW |
271 | switch (level) { |
272 | case I915_CACHE_NONE: | |
273 | break; | |
274 | case I915_CACHE_WT: | |
c51e9701 | 275 | pte |= HSW_WT_ELLC_LLC_AGE3; |
651d794f CW |
276 | break; |
277 | default: | |
c51e9701 | 278 | pte |= HSW_WB_ELLC_LLC_AGE3; |
651d794f CW |
279 | break; |
280 | } | |
4d15c145 BW |
281 | |
282 | return pte; | |
283 | } | |
284 | ||
678d96fb BW |
285 | #define i915_dma_unmap_single(px, dev) \ |
286 | __i915_dma_unmap_single((px)->daddr, dev) | |
287 | ||
288 | static inline void __i915_dma_unmap_single(dma_addr_t daddr, | |
289 | struct drm_device *dev) | |
290 | { | |
291 | struct device *device = &dev->pdev->dev; | |
292 | ||
293 | dma_unmap_page(device, daddr, 4096, PCI_DMA_BIDIRECTIONAL); | |
294 | } | |
295 | ||
296 | /** | |
297 | * i915_dma_map_single() - Create a dma mapping for a page table/dir/etc. | |
298 | * @px: Page table/dir/etc to get a DMA map for | |
299 | * @dev: drm device | |
300 | * | |
301 | * Page table allocations are unified across all gens. They always require a | |
302 | * single 4k allocation, as well as a DMA mapping. If we keep the structs | |
303 | * symmetric here, the simple macro covers us for every page table type. | |
304 | * | |
305 | * Return: 0 if success. | |
306 | */ | |
307 | #define i915_dma_map_single(px, dev) \ | |
308 | i915_dma_map_page_single((px)->page, (dev), &(px)->daddr) | |
309 | ||
310 | static inline int i915_dma_map_page_single(struct page *page, | |
311 | struct drm_device *dev, | |
312 | dma_addr_t *daddr) | |
313 | { | |
314 | struct device *device = &dev->pdev->dev; | |
315 | ||
316 | *daddr = dma_map_page(device, page, 0, 4096, PCI_DMA_BIDIRECTIONAL); | |
1266cdb1 MT |
317 | if (dma_mapping_error(device, *daddr)) |
318 | return -ENOMEM; | |
319 | ||
320 | return 0; | |
678d96fb BW |
321 | } |
322 | ||
ec565b3c | 323 | static void unmap_and_free_pt(struct i915_page_table *pt, |
678d96fb | 324 | struct drm_device *dev) |
06fda602 BW |
325 | { |
326 | if (WARN_ON(!pt->page)) | |
327 | return; | |
678d96fb BW |
328 | |
329 | i915_dma_unmap_single(pt, dev); | |
06fda602 | 330 | __free_page(pt->page); |
678d96fb | 331 | kfree(pt->used_ptes); |
06fda602 BW |
332 | kfree(pt); |
333 | } | |
334 | ||
5a8e9943 | 335 | static void gen8_initialize_pt(struct i915_address_space *vm, |
e5815a2e | 336 | struct i915_page_table *pt) |
5a8e9943 MT |
337 | { |
338 | gen8_pte_t *pt_vaddr, scratch_pte; | |
339 | int i; | |
340 | ||
341 | pt_vaddr = kmap_atomic(pt->page); | |
342 | scratch_pte = gen8_pte_encode(vm->scratch.addr, | |
343 | I915_CACHE_LLC, true); | |
344 | ||
345 | for (i = 0; i < GEN8_PTES; i++) | |
346 | pt_vaddr[i] = scratch_pte; | |
347 | ||
348 | if (!HAS_LLC(vm->dev)) | |
349 | drm_clflush_virt_range(pt_vaddr, PAGE_SIZE); | |
350 | kunmap_atomic(pt_vaddr); | |
351 | } | |
352 | ||
ec565b3c | 353 | static struct i915_page_table *alloc_pt_single(struct drm_device *dev) |
06fda602 | 354 | { |
ec565b3c | 355 | struct i915_page_table *pt; |
678d96fb BW |
356 | const size_t count = INTEL_INFO(dev)->gen >= 8 ? |
357 | GEN8_PTES : GEN6_PTES; | |
358 | int ret = -ENOMEM; | |
06fda602 BW |
359 | |
360 | pt = kzalloc(sizeof(*pt), GFP_KERNEL); | |
361 | if (!pt) | |
362 | return ERR_PTR(-ENOMEM); | |
363 | ||
678d96fb BW |
364 | pt->used_ptes = kcalloc(BITS_TO_LONGS(count), sizeof(*pt->used_ptes), |
365 | GFP_KERNEL); | |
366 | ||
367 | if (!pt->used_ptes) | |
368 | goto fail_bitmap; | |
369 | ||
4933d519 | 370 | pt->page = alloc_page(GFP_KERNEL); |
678d96fb BW |
371 | if (!pt->page) |
372 | goto fail_page; | |
373 | ||
374 | ret = i915_dma_map_single(pt, dev); | |
375 | if (ret) | |
376 | goto fail_dma; | |
06fda602 BW |
377 | |
378 | return pt; | |
678d96fb BW |
379 | |
380 | fail_dma: | |
381 | __free_page(pt->page); | |
382 | fail_page: | |
383 | kfree(pt->used_ptes); | |
384 | fail_bitmap: | |
385 | kfree(pt); | |
386 | ||
387 | return ERR_PTR(ret); | |
06fda602 BW |
388 | } |
389 | ||
e5815a2e MT |
390 | static void unmap_and_free_pd(struct i915_page_directory *pd, |
391 | struct drm_device *dev) | |
06fda602 BW |
392 | { |
393 | if (pd->page) { | |
e5815a2e | 394 | i915_dma_unmap_single(pd, dev); |
06fda602 | 395 | __free_page(pd->page); |
33c8819f | 396 | kfree(pd->used_pdes); |
06fda602 BW |
397 | kfree(pd); |
398 | } | |
399 | } | |
400 | ||
e5815a2e | 401 | static struct i915_page_directory *alloc_pd_single(struct drm_device *dev) |
06fda602 | 402 | { |
ec565b3c | 403 | struct i915_page_directory *pd; |
33c8819f | 404 | int ret = -ENOMEM; |
06fda602 BW |
405 | |
406 | pd = kzalloc(sizeof(*pd), GFP_KERNEL); | |
407 | if (!pd) | |
408 | return ERR_PTR(-ENOMEM); | |
409 | ||
33c8819f MT |
410 | pd->used_pdes = kcalloc(BITS_TO_LONGS(I915_PDES), |
411 | sizeof(*pd->used_pdes), GFP_KERNEL); | |
412 | if (!pd->used_pdes) | |
413 | goto free_pd; | |
414 | ||
5a8e9943 | 415 | pd->page = alloc_page(GFP_KERNEL); |
33c8819f MT |
416 | if (!pd->page) |
417 | goto free_bitmap; | |
06fda602 | 418 | |
e5815a2e | 419 | ret = i915_dma_map_single(pd, dev); |
33c8819f MT |
420 | if (ret) |
421 | goto free_page; | |
e5815a2e | 422 | |
06fda602 | 423 | return pd; |
33c8819f MT |
424 | |
425 | free_page: | |
426 | __free_page(pd->page); | |
427 | free_bitmap: | |
428 | kfree(pd->used_pdes); | |
429 | free_pd: | |
430 | kfree(pd); | |
431 | ||
432 | return ERR_PTR(ret); | |
06fda602 BW |
433 | } |
434 | ||
94e409c1 | 435 | /* Broadwell Page Directory Pointer Descriptors */ |
7cb6d7ac MT |
436 | static int gen8_write_pdp(struct intel_engine_cs *ring, |
437 | unsigned entry, | |
438 | dma_addr_t addr) | |
94e409c1 BW |
439 | { |
440 | int ret; | |
441 | ||
442 | BUG_ON(entry >= 4); | |
443 | ||
444 | ret = intel_ring_begin(ring, 6); | |
445 | if (ret) | |
446 | return ret; | |
447 | ||
448 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
449 | intel_ring_emit(ring, GEN8_RING_PDP_UDW(ring, entry)); | |
7cb6d7ac | 450 | intel_ring_emit(ring, upper_32_bits(addr)); |
94e409c1 BW |
451 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); |
452 | intel_ring_emit(ring, GEN8_RING_PDP_LDW(ring, entry)); | |
7cb6d7ac | 453 | intel_ring_emit(ring, lower_32_bits(addr)); |
94e409c1 BW |
454 | intel_ring_advance(ring); |
455 | ||
456 | return 0; | |
457 | } | |
458 | ||
eeb9488e | 459 | static int gen8_mm_switch(struct i915_hw_ppgtt *ppgtt, |
6689c167 | 460 | struct intel_engine_cs *ring) |
94e409c1 | 461 | { |
eeb9488e | 462 | int i, ret; |
94e409c1 | 463 | |
7cb6d7ac MT |
464 | for (i = GEN8_LEGACY_PDPES - 1; i >= 0; i--) { |
465 | struct i915_page_directory *pd = ppgtt->pdp.page_directory[i]; | |
466 | dma_addr_t pd_daddr = pd ? pd->daddr : ppgtt->scratch_pd->daddr; | |
467 | /* The page directory might be NULL, but we need to clear out | |
468 | * whatever the previous context might have used. */ | |
469 | ret = gen8_write_pdp(ring, i, pd_daddr); | |
eeb9488e BW |
470 | if (ret) |
471 | return ret; | |
94e409c1 | 472 | } |
d595bd4b | 473 | |
eeb9488e | 474 | return 0; |
94e409c1 BW |
475 | } |
476 | ||
459108b8 | 477 | static void gen8_ppgtt_clear_range(struct i915_address_space *vm, |
782f1495 BW |
478 | uint64_t start, |
479 | uint64_t length, | |
459108b8 BW |
480 | bool use_scratch) |
481 | { | |
482 | struct i915_hw_ppgtt *ppgtt = | |
483 | container_of(vm, struct i915_hw_ppgtt, base); | |
07749ef3 | 484 | gen8_pte_t *pt_vaddr, scratch_pte; |
7ad47cf2 BW |
485 | unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK; |
486 | unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK; | |
487 | unsigned pte = start >> GEN8_PTE_SHIFT & GEN8_PTE_MASK; | |
782f1495 | 488 | unsigned num_entries = length >> PAGE_SHIFT; |
459108b8 BW |
489 | unsigned last_pte, i; |
490 | ||
491 | scratch_pte = gen8_pte_encode(ppgtt->base.scratch.addr, | |
492 | I915_CACHE_LLC, use_scratch); | |
493 | ||
494 | while (num_entries) { | |
ec565b3c MT |
495 | struct i915_page_directory *pd; |
496 | struct i915_page_table *pt; | |
06fda602 BW |
497 | struct page *page_table; |
498 | ||
499 | if (WARN_ON(!ppgtt->pdp.page_directory[pdpe])) | |
500 | continue; | |
501 | ||
502 | pd = ppgtt->pdp.page_directory[pdpe]; | |
503 | ||
504 | if (WARN_ON(!pd->page_table[pde])) | |
505 | continue; | |
506 | ||
507 | pt = pd->page_table[pde]; | |
508 | ||
509 | if (WARN_ON(!pt->page)) | |
510 | continue; | |
511 | ||
512 | page_table = pt->page; | |
459108b8 | 513 | |
7ad47cf2 | 514 | last_pte = pte + num_entries; |
07749ef3 MT |
515 | if (last_pte > GEN8_PTES) |
516 | last_pte = GEN8_PTES; | |
459108b8 BW |
517 | |
518 | pt_vaddr = kmap_atomic(page_table); | |
519 | ||
7ad47cf2 | 520 | for (i = pte; i < last_pte; i++) { |
459108b8 | 521 | pt_vaddr[i] = scratch_pte; |
7ad47cf2 BW |
522 | num_entries--; |
523 | } | |
459108b8 | 524 | |
fd1ab8f4 RB |
525 | if (!HAS_LLC(ppgtt->base.dev)) |
526 | drm_clflush_virt_range(pt_vaddr, PAGE_SIZE); | |
459108b8 BW |
527 | kunmap_atomic(pt_vaddr); |
528 | ||
7ad47cf2 | 529 | pte = 0; |
07749ef3 | 530 | if (++pde == I915_PDES) { |
7ad47cf2 BW |
531 | pdpe++; |
532 | pde = 0; | |
533 | } | |
459108b8 BW |
534 | } |
535 | } | |
536 | ||
9df15b49 BW |
537 | static void gen8_ppgtt_insert_entries(struct i915_address_space *vm, |
538 | struct sg_table *pages, | |
782f1495 | 539 | uint64_t start, |
24f3a8cf | 540 | enum i915_cache_level cache_level, u32 unused) |
9df15b49 BW |
541 | { |
542 | struct i915_hw_ppgtt *ppgtt = | |
543 | container_of(vm, struct i915_hw_ppgtt, base); | |
07749ef3 | 544 | gen8_pte_t *pt_vaddr; |
7ad47cf2 BW |
545 | unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK; |
546 | unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK; | |
547 | unsigned pte = start >> GEN8_PTE_SHIFT & GEN8_PTE_MASK; | |
9df15b49 BW |
548 | struct sg_page_iter sg_iter; |
549 | ||
6f1cc993 | 550 | pt_vaddr = NULL; |
7ad47cf2 | 551 | |
9df15b49 | 552 | for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) { |
76643600 | 553 | if (WARN_ON(pdpe >= GEN8_LEGACY_PDPES)) |
7ad47cf2 BW |
554 | break; |
555 | ||
d7b3de91 | 556 | if (pt_vaddr == NULL) { |
ec565b3c MT |
557 | struct i915_page_directory *pd = ppgtt->pdp.page_directory[pdpe]; |
558 | struct i915_page_table *pt = pd->page_table[pde]; | |
06fda602 | 559 | struct page *page_table = pt->page; |
d7b3de91 BW |
560 | |
561 | pt_vaddr = kmap_atomic(page_table); | |
562 | } | |
9df15b49 | 563 | |
7ad47cf2 | 564 | pt_vaddr[pte] = |
6f1cc993 CW |
565 | gen8_pte_encode(sg_page_iter_dma_address(&sg_iter), |
566 | cache_level, true); | |
07749ef3 | 567 | if (++pte == GEN8_PTES) { |
fd1ab8f4 RB |
568 | if (!HAS_LLC(ppgtt->base.dev)) |
569 | drm_clflush_virt_range(pt_vaddr, PAGE_SIZE); | |
9df15b49 | 570 | kunmap_atomic(pt_vaddr); |
6f1cc993 | 571 | pt_vaddr = NULL; |
07749ef3 | 572 | if (++pde == I915_PDES) { |
7ad47cf2 BW |
573 | pdpe++; |
574 | pde = 0; | |
575 | } | |
576 | pte = 0; | |
9df15b49 BW |
577 | } |
578 | } | |
fd1ab8f4 RB |
579 | if (pt_vaddr) { |
580 | if (!HAS_LLC(ppgtt->base.dev)) | |
581 | drm_clflush_virt_range(pt_vaddr, PAGE_SIZE); | |
6f1cc993 | 582 | kunmap_atomic(pt_vaddr); |
fd1ab8f4 | 583 | } |
9df15b49 BW |
584 | } |
585 | ||
69876bed MT |
586 | static void __gen8_do_map_pt(gen8_pde_t * const pde, |
587 | struct i915_page_table *pt, | |
588 | struct drm_device *dev) | |
589 | { | |
590 | gen8_pde_t entry = | |
591 | gen8_pde_encode(dev, pt->daddr, I915_CACHE_LLC); | |
592 | *pde = entry; | |
593 | } | |
594 | ||
595 | static void gen8_initialize_pd(struct i915_address_space *vm, | |
596 | struct i915_page_directory *pd) | |
597 | { | |
598 | struct i915_hw_ppgtt *ppgtt = | |
599 | container_of(vm, struct i915_hw_ppgtt, base); | |
600 | gen8_pde_t *page_directory; | |
601 | struct i915_page_table *pt; | |
602 | int i; | |
603 | ||
604 | page_directory = kmap_atomic(pd->page); | |
605 | pt = ppgtt->scratch_pt; | |
606 | for (i = 0; i < I915_PDES; i++) | |
607 | /* Map the PDE to the page table */ | |
608 | __gen8_do_map_pt(page_directory + i, pt, vm->dev); | |
609 | ||
610 | if (!HAS_LLC(vm->dev)) | |
611 | drm_clflush_virt_range(page_directory, PAGE_SIZE); | |
e5815a2e MT |
612 | kunmap_atomic(page_directory); |
613 | } | |
614 | ||
ec565b3c | 615 | static void gen8_free_page_tables(struct i915_page_directory *pd, struct drm_device *dev) |
7ad47cf2 BW |
616 | { |
617 | int i; | |
618 | ||
06fda602 | 619 | if (!pd->page) |
7ad47cf2 BW |
620 | return; |
621 | ||
33c8819f | 622 | for_each_set_bit(i, pd->used_pdes, I915_PDES) { |
06fda602 BW |
623 | if (WARN_ON(!pd->page_table[i])) |
624 | continue; | |
7ad47cf2 | 625 | |
06dc68d6 | 626 | unmap_and_free_pt(pd->page_table[i], dev); |
06fda602 BW |
627 | pd->page_table[i] = NULL; |
628 | } | |
d7b3de91 BW |
629 | } |
630 | ||
061dd493 | 631 | static void gen8_ppgtt_cleanup(struct i915_address_space *vm) |
b45a6715 | 632 | { |
061dd493 DV |
633 | struct i915_hw_ppgtt *ppgtt = |
634 | container_of(vm, struct i915_hw_ppgtt, base); | |
b45a6715 BW |
635 | int i; |
636 | ||
33c8819f | 637 | for_each_set_bit(i, ppgtt->pdp.used_pdpes, GEN8_LEGACY_PDPES) { |
06fda602 BW |
638 | if (WARN_ON(!ppgtt->pdp.page_directory[i])) |
639 | continue; | |
640 | ||
06dc68d6 | 641 | gen8_free_page_tables(ppgtt->pdp.page_directory[i], ppgtt->base.dev); |
e5815a2e | 642 | unmap_and_free_pd(ppgtt->pdp.page_directory[i], ppgtt->base.dev); |
7ad47cf2 | 643 | } |
69876bed | 644 | |
e5815a2e | 645 | unmap_and_free_pd(ppgtt->scratch_pd, ppgtt->base.dev); |
69876bed | 646 | unmap_and_free_pt(ppgtt->scratch_pt, ppgtt->base.dev); |
b45a6715 BW |
647 | } |
648 | ||
d7b2633d MT |
649 | /** |
650 | * gen8_ppgtt_alloc_pagetabs() - Allocate page tables for VA range. | |
651 | * @ppgtt: Master ppgtt structure. | |
652 | * @pd: Page directory for this address range. | |
653 | * @start: Starting virtual address to begin allocations. | |
654 | * @length Size of the allocations. | |
655 | * @new_pts: Bitmap set by function with new allocations. Likely used by the | |
656 | * caller to free on error. | |
657 | * | |
658 | * Allocate the required number of page tables. Extremely similar to | |
659 | * gen8_ppgtt_alloc_page_directories(). The main difference is here we are limited by | |
660 | * the page directory boundary (instead of the page directory pointer). That | |
661 | * boundary is 1GB virtual. Therefore, unlike gen8_ppgtt_alloc_page_directories(), it is | |
662 | * possible, and likely that the caller will need to use multiple calls of this | |
663 | * function to achieve the appropriate allocation. | |
664 | * | |
665 | * Return: 0 if success; negative error code otherwise. | |
666 | */ | |
e5815a2e MT |
667 | static int gen8_ppgtt_alloc_pagetabs(struct i915_hw_ppgtt *ppgtt, |
668 | struct i915_page_directory *pd, | |
5441f0cb | 669 | uint64_t start, |
d7b2633d MT |
670 | uint64_t length, |
671 | unsigned long *new_pts) | |
bf2b4ed2 | 672 | { |
e5815a2e | 673 | struct drm_device *dev = ppgtt->base.dev; |
d7b2633d | 674 | struct i915_page_table *pt; |
5441f0cb MT |
675 | uint64_t temp; |
676 | uint32_t pde; | |
bf2b4ed2 | 677 | |
d7b2633d MT |
678 | gen8_for_each_pde(pt, pd, start, length, temp, pde) { |
679 | /* Don't reallocate page tables */ | |
680 | if (pt) { | |
681 | /* Scratch is never allocated this way */ | |
682 | WARN_ON(pt == ppgtt->scratch_pt); | |
683 | continue; | |
684 | } | |
685 | ||
686 | pt = alloc_pt_single(dev); | |
687 | if (IS_ERR(pt)) | |
5441f0cb MT |
688 | goto unwind_out; |
689 | ||
d7b2633d MT |
690 | gen8_initialize_pt(&ppgtt->base, pt); |
691 | pd->page_table[pde] = pt; | |
692 | set_bit(pde, new_pts); | |
7ad47cf2 BW |
693 | } |
694 | ||
bf2b4ed2 | 695 | return 0; |
7ad47cf2 BW |
696 | |
697 | unwind_out: | |
d7b2633d | 698 | for_each_set_bit(pde, new_pts, I915_PDES) |
e5815a2e | 699 | unmap_and_free_pt(pd->page_table[pde], dev); |
7ad47cf2 | 700 | |
d7b3de91 | 701 | return -ENOMEM; |
bf2b4ed2 BW |
702 | } |
703 | ||
d7b2633d MT |
704 | /** |
705 | * gen8_ppgtt_alloc_page_directories() - Allocate page directories for VA range. | |
706 | * @ppgtt: Master ppgtt structure. | |
707 | * @pdp: Page directory pointer for this address range. | |
708 | * @start: Starting virtual address to begin allocations. | |
709 | * @length Size of the allocations. | |
710 | * @new_pds Bitmap set by function with new allocations. Likely used by the | |
711 | * caller to free on error. | |
712 | * | |
713 | * Allocate the required number of page directories starting at the pde index of | |
714 | * @start, and ending at the pde index @start + @length. This function will skip | |
715 | * over already allocated page directories within the range, and only allocate | |
716 | * new ones, setting the appropriate pointer within the pdp as well as the | |
717 | * correct position in the bitmap @new_pds. | |
718 | * | |
719 | * The function will only allocate the pages within the range for a give page | |
720 | * directory pointer. In other words, if @start + @length straddles a virtually | |
721 | * addressed PDP boundary (512GB for 4k pages), there will be more allocations | |
722 | * required by the caller, This is not currently possible, and the BUG in the | |
723 | * code will prevent it. | |
724 | * | |
725 | * Return: 0 if success; negative error code otherwise. | |
726 | */ | |
c488dbba MT |
727 | static int gen8_ppgtt_alloc_page_directories(struct i915_hw_ppgtt *ppgtt, |
728 | struct i915_page_directory_pointer *pdp, | |
69876bed | 729 | uint64_t start, |
d7b2633d MT |
730 | uint64_t length, |
731 | unsigned long *new_pds) | |
bf2b4ed2 | 732 | { |
e5815a2e | 733 | struct drm_device *dev = ppgtt->base.dev; |
d7b2633d | 734 | struct i915_page_directory *pd; |
69876bed MT |
735 | uint64_t temp; |
736 | uint32_t pdpe; | |
737 | ||
d7b2633d MT |
738 | WARN_ON(!bitmap_empty(new_pds, GEN8_LEGACY_PDPES)); |
739 | ||
69876bed MT |
740 | /* FIXME: PPGTT container_of won't work for 64b */ |
741 | WARN_ON((start + length) > 0x800000000ULL); | |
742 | ||
d7b2633d MT |
743 | gen8_for_each_pdpe(pd, pdp, start, length, temp, pdpe) { |
744 | if (pd) | |
745 | continue; | |
33c8819f | 746 | |
d7b2633d MT |
747 | pd = alloc_pd_single(dev); |
748 | if (IS_ERR(pd)) | |
d7b3de91 | 749 | goto unwind_out; |
69876bed | 750 | |
d7b2633d MT |
751 | gen8_initialize_pd(&ppgtt->base, pd); |
752 | pdp->page_directory[pdpe] = pd; | |
753 | set_bit(pdpe, new_pds); | |
d7b3de91 BW |
754 | } |
755 | ||
bf2b4ed2 | 756 | return 0; |
d7b3de91 BW |
757 | |
758 | unwind_out: | |
d7b2633d | 759 | for_each_set_bit(pdpe, new_pds, GEN8_LEGACY_PDPES) |
e5815a2e | 760 | unmap_and_free_pd(pdp->page_directory[pdpe], dev); |
d7b3de91 BW |
761 | |
762 | return -ENOMEM; | |
bf2b4ed2 BW |
763 | } |
764 | ||
d7b2633d MT |
765 | static void |
766 | free_gen8_temp_bitmaps(unsigned long *new_pds, unsigned long **new_pts) | |
767 | { | |
768 | int i; | |
769 | ||
770 | for (i = 0; i < GEN8_LEGACY_PDPES; i++) | |
771 | kfree(new_pts[i]); | |
772 | kfree(new_pts); | |
773 | kfree(new_pds); | |
774 | } | |
775 | ||
776 | /* Fills in the page directory bitmap, and the array of page tables bitmap. Both | |
777 | * of these are based on the number of PDPEs in the system. | |
778 | */ | |
779 | static | |
780 | int __must_check alloc_gen8_temp_bitmaps(unsigned long **new_pds, | |
781 | unsigned long ***new_pts) | |
782 | { | |
783 | int i; | |
784 | unsigned long *pds; | |
785 | unsigned long **pts; | |
786 | ||
787 | pds = kcalloc(BITS_TO_LONGS(GEN8_LEGACY_PDPES), sizeof(unsigned long), GFP_KERNEL); | |
788 | if (!pds) | |
789 | return -ENOMEM; | |
790 | ||
791 | pts = kcalloc(GEN8_LEGACY_PDPES, sizeof(unsigned long *), GFP_KERNEL); | |
792 | if (!pts) { | |
793 | kfree(pds); | |
794 | return -ENOMEM; | |
795 | } | |
796 | ||
797 | for (i = 0; i < GEN8_LEGACY_PDPES; i++) { | |
798 | pts[i] = kcalloc(BITS_TO_LONGS(I915_PDES), | |
799 | sizeof(unsigned long), GFP_KERNEL); | |
800 | if (!pts[i]) | |
801 | goto err_out; | |
802 | } | |
803 | ||
804 | *new_pds = pds; | |
805 | *new_pts = pts; | |
806 | ||
807 | return 0; | |
808 | ||
809 | err_out: | |
810 | free_gen8_temp_bitmaps(pds, pts); | |
811 | return -ENOMEM; | |
812 | } | |
813 | ||
e5815a2e MT |
814 | static int gen8_alloc_va_range(struct i915_address_space *vm, |
815 | uint64_t start, | |
816 | uint64_t length) | |
bf2b4ed2 | 817 | { |
e5815a2e MT |
818 | struct i915_hw_ppgtt *ppgtt = |
819 | container_of(vm, struct i915_hw_ppgtt, base); | |
d7b2633d | 820 | unsigned long *new_page_dirs, **new_page_tables; |
5441f0cb | 821 | struct i915_page_directory *pd; |
33c8819f MT |
822 | const uint64_t orig_start = start; |
823 | const uint64_t orig_length = length; | |
5441f0cb MT |
824 | uint64_t temp; |
825 | uint32_t pdpe; | |
bf2b4ed2 BW |
826 | int ret; |
827 | ||
d7b2633d MT |
828 | #ifndef CONFIG_64BIT |
829 | /* Disallow 64b address on 32b platforms. Nothing is wrong with doing | |
830 | * this in hardware, but a lot of the drm code is not prepared to handle | |
831 | * 64b offset on 32b platforms. | |
832 | * This will be addressed when 48b PPGTT is added */ | |
833 | if (start + length > 0x100000000ULL) | |
834 | return -E2BIG; | |
835 | #endif | |
836 | ||
837 | /* Wrap is never okay since we can only represent 48b, and we don't | |
838 | * actually use the other side of the canonical address space. | |
839 | */ | |
840 | if (WARN_ON(start + length < start)) | |
841 | return -ERANGE; | |
842 | ||
843 | ret = alloc_gen8_temp_bitmaps(&new_page_dirs, &new_page_tables); | |
bf2b4ed2 BW |
844 | if (ret) |
845 | return ret; | |
846 | ||
d7b2633d MT |
847 | /* Do the allocations first so we can easily bail out */ |
848 | ret = gen8_ppgtt_alloc_page_directories(ppgtt, &ppgtt->pdp, start, length, | |
849 | new_page_dirs); | |
850 | if (ret) { | |
851 | free_gen8_temp_bitmaps(new_page_dirs, new_page_tables); | |
852 | return ret; | |
853 | } | |
854 | ||
855 | /* For every page directory referenced, allocate page tables */ | |
5441f0cb | 856 | gen8_for_each_pdpe(pd, &ppgtt->pdp, start, length, temp, pdpe) { |
d7b2633d MT |
857 | ret = gen8_ppgtt_alloc_pagetabs(ppgtt, pd, start, length, |
858 | new_page_tables[pdpe]); | |
5441f0cb MT |
859 | if (ret) |
860 | goto err_out; | |
5441f0cb MT |
861 | } |
862 | ||
33c8819f MT |
863 | start = orig_start; |
864 | length = orig_length; | |
865 | ||
d7b2633d MT |
866 | /* Allocations have completed successfully, so set the bitmaps, and do |
867 | * the mappings. */ | |
33c8819f | 868 | gen8_for_each_pdpe(pd, &ppgtt->pdp, start, length, temp, pdpe) { |
d7b2633d | 869 | gen8_pde_t *const page_directory = kmap_atomic(pd->page); |
33c8819f MT |
870 | struct i915_page_table *pt; |
871 | uint64_t pd_len = gen8_clamp_pd(start, length); | |
872 | uint64_t pd_start = start; | |
873 | uint32_t pde; | |
874 | ||
d7b2633d MT |
875 | /* Every pd should be allocated, we just did that above. */ |
876 | WARN_ON(!pd); | |
877 | ||
878 | gen8_for_each_pde(pt, pd, pd_start, pd_len, temp, pde) { | |
879 | /* Same reasoning as pd */ | |
880 | WARN_ON(!pt); | |
881 | WARN_ON(!pd_len); | |
882 | WARN_ON(!gen8_pte_count(pd_start, pd_len)); | |
883 | ||
884 | /* Set our used ptes within the page table */ | |
885 | bitmap_set(pt->used_ptes, | |
886 | gen8_pte_index(pd_start), | |
887 | gen8_pte_count(pd_start, pd_len)); | |
888 | ||
889 | /* Our pde is now pointing to the pagetable, pt */ | |
33c8819f | 890 | set_bit(pde, pd->used_pdes); |
d7b2633d MT |
891 | |
892 | /* Map the PDE to the page table */ | |
893 | __gen8_do_map_pt(page_directory + pde, pt, vm->dev); | |
894 | ||
895 | /* NB: We haven't yet mapped ptes to pages. At this | |
896 | * point we're still relying on insert_entries() */ | |
33c8819f | 897 | } |
d7b2633d MT |
898 | |
899 | if (!HAS_LLC(vm->dev)) | |
900 | drm_clflush_virt_range(page_directory, PAGE_SIZE); | |
901 | ||
902 | kunmap_atomic(page_directory); | |
903 | ||
33c8819f MT |
904 | set_bit(pdpe, ppgtt->pdp.used_pdpes); |
905 | } | |
906 | ||
d7b2633d | 907 | free_gen8_temp_bitmaps(new_page_dirs, new_page_tables); |
d7b3de91 | 908 | return 0; |
bf2b4ed2 | 909 | |
d7b3de91 | 910 | err_out: |
d7b2633d MT |
911 | while (pdpe--) { |
912 | for_each_set_bit(temp, new_page_tables[pdpe], I915_PDES) | |
913 | unmap_and_free_pt(ppgtt->pdp.page_directory[pdpe]->page_table[temp], vm->dev); | |
914 | } | |
915 | ||
916 | for_each_set_bit(pdpe, new_page_dirs, GEN8_LEGACY_PDPES) | |
917 | unmap_and_free_pd(ppgtt->pdp.page_directory[pdpe], vm->dev); | |
918 | ||
919 | free_gen8_temp_bitmaps(new_page_dirs, new_page_tables); | |
bf2b4ed2 BW |
920 | return ret; |
921 | } | |
922 | ||
eb0b44ad | 923 | /* |
f3a964b9 BW |
924 | * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers |
925 | * with a net effect resembling a 2-level page table in normal x86 terms. Each | |
926 | * PDP represents 1GB of memory 4 * 512 * 512 * 4096 = 4GB legacy 32b address | |
927 | * space. | |
37aca44a | 928 | * |
f3a964b9 | 929 | */ |
5c5f6457 | 930 | static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt) |
37aca44a | 931 | { |
69876bed MT |
932 | ppgtt->scratch_pt = alloc_pt_single(ppgtt->base.dev); |
933 | if (IS_ERR(ppgtt->scratch_pt)) | |
934 | return PTR_ERR(ppgtt->scratch_pt); | |
935 | ||
e5815a2e | 936 | ppgtt->scratch_pd = alloc_pd_single(ppgtt->base.dev); |
7cb6d7ac MT |
937 | if (IS_ERR(ppgtt->scratch_pd)) |
938 | return PTR_ERR(ppgtt->scratch_pd); | |
939 | ||
69876bed | 940 | gen8_initialize_pt(&ppgtt->base, ppgtt->scratch_pt); |
7cb6d7ac | 941 | gen8_initialize_pd(&ppgtt->base, ppgtt->scratch_pd); |
69876bed | 942 | |
d7b2633d | 943 | ppgtt->base.start = 0; |
5c5f6457 | 944 | ppgtt->base.total = 1ULL << 32; |
d7b2633d | 945 | ppgtt->base.cleanup = gen8_ppgtt_cleanup; |
5c5f6457 | 946 | ppgtt->base.allocate_va_range = gen8_alloc_va_range; |
d7b2633d | 947 | ppgtt->base.insert_entries = gen8_ppgtt_insert_entries; |
c7e16f22 | 948 | ppgtt->base.clear_range = gen8_ppgtt_clear_range; |
777dc5bb DV |
949 | ppgtt->base.unbind_vma = ppgtt_unbind_vma; |
950 | ppgtt->base.bind_vma = ppgtt_bind_vma; | |
d7b2633d MT |
951 | |
952 | ppgtt->switch_mm = gen8_mm_switch; | |
953 | ||
954 | return 0; | |
955 | } | |
956 | ||
87d60b63 BW |
957 | static void gen6_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m) |
958 | { | |
87d60b63 | 959 | struct i915_address_space *vm = &ppgtt->base; |
09942c65 | 960 | struct i915_page_table *unused; |
07749ef3 | 961 | gen6_pte_t scratch_pte; |
87d60b63 | 962 | uint32_t pd_entry; |
09942c65 MT |
963 | uint32_t pte, pde, temp; |
964 | uint32_t start = ppgtt->base.start, length = ppgtt->base.total; | |
87d60b63 | 965 | |
24f3a8cf | 966 | scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true, 0); |
87d60b63 | 967 | |
09942c65 | 968 | gen6_for_each_pde(unused, &ppgtt->pd, start, length, temp, pde) { |
87d60b63 | 969 | u32 expected; |
07749ef3 | 970 | gen6_pte_t *pt_vaddr; |
06fda602 | 971 | dma_addr_t pt_addr = ppgtt->pd.page_table[pde]->daddr; |
09942c65 | 972 | pd_entry = readl(ppgtt->pd_addr + pde); |
87d60b63 BW |
973 | expected = (GEN6_PDE_ADDR_ENCODE(pt_addr) | GEN6_PDE_VALID); |
974 | ||
975 | if (pd_entry != expected) | |
976 | seq_printf(m, "\tPDE #%d mismatch: Actual PDE: %x Expected PDE: %x\n", | |
977 | pde, | |
978 | pd_entry, | |
979 | expected); | |
980 | seq_printf(m, "\tPDE: %x\n", pd_entry); | |
981 | ||
06fda602 | 982 | pt_vaddr = kmap_atomic(ppgtt->pd.page_table[pde]->page); |
07749ef3 | 983 | for (pte = 0; pte < GEN6_PTES; pte+=4) { |
87d60b63 | 984 | unsigned long va = |
07749ef3 | 985 | (pde * PAGE_SIZE * GEN6_PTES) + |
87d60b63 BW |
986 | (pte * PAGE_SIZE); |
987 | int i; | |
988 | bool found = false; | |
989 | for (i = 0; i < 4; i++) | |
990 | if (pt_vaddr[pte + i] != scratch_pte) | |
991 | found = true; | |
992 | if (!found) | |
993 | continue; | |
994 | ||
995 | seq_printf(m, "\t\t0x%lx [%03d,%04d]: =", va, pde, pte); | |
996 | for (i = 0; i < 4; i++) { | |
997 | if (pt_vaddr[pte + i] != scratch_pte) | |
998 | seq_printf(m, " %08x", pt_vaddr[pte + i]); | |
999 | else | |
1000 | seq_puts(m, " SCRATCH "); | |
1001 | } | |
1002 | seq_puts(m, "\n"); | |
1003 | } | |
1004 | kunmap_atomic(pt_vaddr); | |
1005 | } | |
1006 | } | |
1007 | ||
678d96fb | 1008 | /* Write pde (index) from the page directory @pd to the page table @pt */ |
ec565b3c MT |
1009 | static void gen6_write_pde(struct i915_page_directory *pd, |
1010 | const int pde, struct i915_page_table *pt) | |
6197349b | 1011 | { |
678d96fb BW |
1012 | /* Caller needs to make sure the write completes if necessary */ |
1013 | struct i915_hw_ppgtt *ppgtt = | |
1014 | container_of(pd, struct i915_hw_ppgtt, pd); | |
1015 | u32 pd_entry; | |
6197349b | 1016 | |
678d96fb BW |
1017 | pd_entry = GEN6_PDE_ADDR_ENCODE(pt->daddr); |
1018 | pd_entry |= GEN6_PDE_VALID; | |
6197349b | 1019 | |
678d96fb BW |
1020 | writel(pd_entry, ppgtt->pd_addr + pde); |
1021 | } | |
6197349b | 1022 | |
678d96fb BW |
1023 | /* Write all the page tables found in the ppgtt structure to incrementing page |
1024 | * directories. */ | |
1025 | static void gen6_write_page_range(struct drm_i915_private *dev_priv, | |
ec565b3c | 1026 | struct i915_page_directory *pd, |
678d96fb BW |
1027 | uint32_t start, uint32_t length) |
1028 | { | |
ec565b3c | 1029 | struct i915_page_table *pt; |
678d96fb BW |
1030 | uint32_t pde, temp; |
1031 | ||
1032 | gen6_for_each_pde(pt, pd, start, length, temp, pde) | |
1033 | gen6_write_pde(pd, pde, pt); | |
1034 | ||
1035 | /* Make sure write is complete before other code can use this page | |
1036 | * table. Also require for WC mapped PTEs */ | |
1037 | readl(dev_priv->gtt.gsm); | |
3e302542 BW |
1038 | } |
1039 | ||
b4a74e3a | 1040 | static uint32_t get_pd_offset(struct i915_hw_ppgtt *ppgtt) |
3e302542 | 1041 | { |
7324cc04 | 1042 | BUG_ON(ppgtt->pd.pd_offset & 0x3f); |
b4a74e3a | 1043 | |
7324cc04 | 1044 | return (ppgtt->pd.pd_offset / 64) << 16; |
b4a74e3a BW |
1045 | } |
1046 | ||
90252e5c | 1047 | static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt, |
6689c167 | 1048 | struct intel_engine_cs *ring) |
90252e5c | 1049 | { |
90252e5c BW |
1050 | int ret; |
1051 | ||
90252e5c BW |
1052 | /* NB: TLBs must be flushed and invalidated before a switch */ |
1053 | ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); | |
1054 | if (ret) | |
1055 | return ret; | |
1056 | ||
1057 | ret = intel_ring_begin(ring, 6); | |
1058 | if (ret) | |
1059 | return ret; | |
1060 | ||
1061 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2)); | |
1062 | intel_ring_emit(ring, RING_PP_DIR_DCLV(ring)); | |
1063 | intel_ring_emit(ring, PP_DIR_DCLV_2G); | |
1064 | intel_ring_emit(ring, RING_PP_DIR_BASE(ring)); | |
1065 | intel_ring_emit(ring, get_pd_offset(ppgtt)); | |
1066 | intel_ring_emit(ring, MI_NOOP); | |
1067 | intel_ring_advance(ring); | |
1068 | ||
1069 | return 0; | |
1070 | } | |
1071 | ||
71ba2d64 YZ |
1072 | static int vgpu_mm_switch(struct i915_hw_ppgtt *ppgtt, |
1073 | struct intel_engine_cs *ring) | |
1074 | { | |
1075 | struct drm_i915_private *dev_priv = to_i915(ppgtt->base.dev); | |
1076 | ||
1077 | I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G); | |
1078 | I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt)); | |
1079 | return 0; | |
1080 | } | |
1081 | ||
48a10389 | 1082 | static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt, |
6689c167 | 1083 | struct intel_engine_cs *ring) |
48a10389 | 1084 | { |
48a10389 BW |
1085 | int ret; |
1086 | ||
48a10389 BW |
1087 | /* NB: TLBs must be flushed and invalidated before a switch */ |
1088 | ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); | |
1089 | if (ret) | |
1090 | return ret; | |
1091 | ||
1092 | ret = intel_ring_begin(ring, 6); | |
1093 | if (ret) | |
1094 | return ret; | |
1095 | ||
1096 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2)); | |
1097 | intel_ring_emit(ring, RING_PP_DIR_DCLV(ring)); | |
1098 | intel_ring_emit(ring, PP_DIR_DCLV_2G); | |
1099 | intel_ring_emit(ring, RING_PP_DIR_BASE(ring)); | |
1100 | intel_ring_emit(ring, get_pd_offset(ppgtt)); | |
1101 | intel_ring_emit(ring, MI_NOOP); | |
1102 | intel_ring_advance(ring); | |
1103 | ||
90252e5c BW |
1104 | /* XXX: RCS is the only one to auto invalidate the TLBs? */ |
1105 | if (ring->id != RCS) { | |
1106 | ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); | |
1107 | if (ret) | |
1108 | return ret; | |
1109 | } | |
1110 | ||
48a10389 BW |
1111 | return 0; |
1112 | } | |
1113 | ||
eeb9488e | 1114 | static int gen6_mm_switch(struct i915_hw_ppgtt *ppgtt, |
6689c167 | 1115 | struct intel_engine_cs *ring) |
eeb9488e BW |
1116 | { |
1117 | struct drm_device *dev = ppgtt->base.dev; | |
1118 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1119 | ||
48a10389 | 1120 | |
eeb9488e BW |
1121 | I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G); |
1122 | I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt)); | |
1123 | ||
1124 | POSTING_READ(RING_PP_DIR_DCLV(ring)); | |
1125 | ||
1126 | return 0; | |
1127 | } | |
1128 | ||
82460d97 | 1129 | static void gen8_ppgtt_enable(struct drm_device *dev) |
eeb9488e | 1130 | { |
eeb9488e | 1131 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 1132 | struct intel_engine_cs *ring; |
82460d97 | 1133 | int j; |
3e302542 | 1134 | |
eeb9488e BW |
1135 | for_each_ring(ring, dev_priv, j) { |
1136 | I915_WRITE(RING_MODE_GEN7(ring), | |
1137 | _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
eeb9488e | 1138 | } |
eeb9488e | 1139 | } |
6197349b | 1140 | |
82460d97 | 1141 | static void gen7_ppgtt_enable(struct drm_device *dev) |
3e302542 | 1142 | { |
50227e1c | 1143 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 1144 | struct intel_engine_cs *ring; |
b4a74e3a | 1145 | uint32_t ecochk, ecobits; |
3e302542 | 1146 | int i; |
6197349b | 1147 | |
b4a74e3a BW |
1148 | ecobits = I915_READ(GAC_ECO_BITS); |
1149 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B); | |
a65c2fcd | 1150 | |
b4a74e3a BW |
1151 | ecochk = I915_READ(GAM_ECOCHK); |
1152 | if (IS_HASWELL(dev)) { | |
1153 | ecochk |= ECOCHK_PPGTT_WB_HSW; | |
1154 | } else { | |
1155 | ecochk |= ECOCHK_PPGTT_LLC_IVB; | |
1156 | ecochk &= ~ECOCHK_PPGTT_GFDT_IVB; | |
1157 | } | |
1158 | I915_WRITE(GAM_ECOCHK, ecochk); | |
a65c2fcd | 1159 | |
b4a74e3a | 1160 | for_each_ring(ring, dev_priv, i) { |
6197349b | 1161 | /* GFX_MODE is per-ring on gen7+ */ |
b4a74e3a BW |
1162 | I915_WRITE(RING_MODE_GEN7(ring), |
1163 | _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
6197349b | 1164 | } |
b4a74e3a | 1165 | } |
6197349b | 1166 | |
82460d97 | 1167 | static void gen6_ppgtt_enable(struct drm_device *dev) |
b4a74e3a | 1168 | { |
50227e1c | 1169 | struct drm_i915_private *dev_priv = dev->dev_private; |
b4a74e3a | 1170 | uint32_t ecochk, gab_ctl, ecobits; |
a65c2fcd | 1171 | |
b4a74e3a BW |
1172 | ecobits = I915_READ(GAC_ECO_BITS); |
1173 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT | | |
1174 | ECOBITS_PPGTT_CACHE64B); | |
6197349b | 1175 | |
b4a74e3a BW |
1176 | gab_ctl = I915_READ(GAB_CTL); |
1177 | I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT); | |
1178 | ||
1179 | ecochk = I915_READ(GAM_ECOCHK); | |
1180 | I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B); | |
1181 | ||
1182 | I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
6197349b BW |
1183 | } |
1184 | ||
1d2a314c | 1185 | /* PPGTT support for Sandybdrige/Gen6 and later */ |
853ba5d2 | 1186 | static void gen6_ppgtt_clear_range(struct i915_address_space *vm, |
782f1495 BW |
1187 | uint64_t start, |
1188 | uint64_t length, | |
828c7908 | 1189 | bool use_scratch) |
1d2a314c | 1190 | { |
853ba5d2 BW |
1191 | struct i915_hw_ppgtt *ppgtt = |
1192 | container_of(vm, struct i915_hw_ppgtt, base); | |
07749ef3 | 1193 | gen6_pte_t *pt_vaddr, scratch_pte; |
782f1495 BW |
1194 | unsigned first_entry = start >> PAGE_SHIFT; |
1195 | unsigned num_entries = length >> PAGE_SHIFT; | |
07749ef3 MT |
1196 | unsigned act_pt = first_entry / GEN6_PTES; |
1197 | unsigned first_pte = first_entry % GEN6_PTES; | |
7bddb01f | 1198 | unsigned last_pte, i; |
1d2a314c | 1199 | |
24f3a8cf | 1200 | scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true, 0); |
1d2a314c | 1201 | |
7bddb01f DV |
1202 | while (num_entries) { |
1203 | last_pte = first_pte + num_entries; | |
07749ef3 MT |
1204 | if (last_pte > GEN6_PTES) |
1205 | last_pte = GEN6_PTES; | |
7bddb01f | 1206 | |
06fda602 | 1207 | pt_vaddr = kmap_atomic(ppgtt->pd.page_table[act_pt]->page); |
1d2a314c | 1208 | |
7bddb01f DV |
1209 | for (i = first_pte; i < last_pte; i++) |
1210 | pt_vaddr[i] = scratch_pte; | |
1d2a314c DV |
1211 | |
1212 | kunmap_atomic(pt_vaddr); | |
1d2a314c | 1213 | |
7bddb01f DV |
1214 | num_entries -= last_pte - first_pte; |
1215 | first_pte = 0; | |
a15326a5 | 1216 | act_pt++; |
7bddb01f | 1217 | } |
1d2a314c DV |
1218 | } |
1219 | ||
853ba5d2 | 1220 | static void gen6_ppgtt_insert_entries(struct i915_address_space *vm, |
def886c3 | 1221 | struct sg_table *pages, |
782f1495 | 1222 | uint64_t start, |
24f3a8cf | 1223 | enum i915_cache_level cache_level, u32 flags) |
def886c3 | 1224 | { |
853ba5d2 BW |
1225 | struct i915_hw_ppgtt *ppgtt = |
1226 | container_of(vm, struct i915_hw_ppgtt, base); | |
07749ef3 | 1227 | gen6_pte_t *pt_vaddr; |
782f1495 | 1228 | unsigned first_entry = start >> PAGE_SHIFT; |
07749ef3 MT |
1229 | unsigned act_pt = first_entry / GEN6_PTES; |
1230 | unsigned act_pte = first_entry % GEN6_PTES; | |
6e995e23 ID |
1231 | struct sg_page_iter sg_iter; |
1232 | ||
cc79714f | 1233 | pt_vaddr = NULL; |
6e995e23 | 1234 | for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) { |
cc79714f | 1235 | if (pt_vaddr == NULL) |
06fda602 | 1236 | pt_vaddr = kmap_atomic(ppgtt->pd.page_table[act_pt]->page); |
6e995e23 | 1237 | |
cc79714f CW |
1238 | pt_vaddr[act_pte] = |
1239 | vm->pte_encode(sg_page_iter_dma_address(&sg_iter), | |
24f3a8cf AG |
1240 | cache_level, true, flags); |
1241 | ||
07749ef3 | 1242 | if (++act_pte == GEN6_PTES) { |
6e995e23 | 1243 | kunmap_atomic(pt_vaddr); |
cc79714f | 1244 | pt_vaddr = NULL; |
a15326a5 | 1245 | act_pt++; |
6e995e23 | 1246 | act_pte = 0; |
def886c3 | 1247 | } |
def886c3 | 1248 | } |
cc79714f CW |
1249 | if (pt_vaddr) |
1250 | kunmap_atomic(pt_vaddr); | |
def886c3 DV |
1251 | } |
1252 | ||
563222a7 BW |
1253 | /* PDE TLBs are a pain invalidate pre GEN8. It requires a context reload. If we |
1254 | * are switching between contexts with the same LRCA, we also must do a force | |
1255 | * restore. | |
1256 | */ | |
1257 | static inline void mark_tlbs_dirty(struct i915_hw_ppgtt *ppgtt) | |
1258 | { | |
1259 | /* If current vm != vm, */ | |
1260 | ppgtt->pd_dirty_rings = INTEL_INFO(ppgtt->base.dev)->ring_mask; | |
1261 | } | |
1262 | ||
4933d519 | 1263 | static void gen6_initialize_pt(struct i915_address_space *vm, |
ec565b3c | 1264 | struct i915_page_table *pt) |
4933d519 MT |
1265 | { |
1266 | gen6_pte_t *pt_vaddr, scratch_pte; | |
1267 | int i; | |
1268 | ||
1269 | WARN_ON(vm->scratch.addr == 0); | |
1270 | ||
1271 | scratch_pte = vm->pte_encode(vm->scratch.addr, | |
1272 | I915_CACHE_LLC, true, 0); | |
1273 | ||
1274 | pt_vaddr = kmap_atomic(pt->page); | |
1275 | ||
1276 | for (i = 0; i < GEN6_PTES; i++) | |
1277 | pt_vaddr[i] = scratch_pte; | |
1278 | ||
1279 | kunmap_atomic(pt_vaddr); | |
1280 | } | |
1281 | ||
678d96fb BW |
1282 | static int gen6_alloc_va_range(struct i915_address_space *vm, |
1283 | uint64_t start, uint64_t length) | |
1284 | { | |
4933d519 MT |
1285 | DECLARE_BITMAP(new_page_tables, I915_PDES); |
1286 | struct drm_device *dev = vm->dev; | |
1287 | struct drm_i915_private *dev_priv = dev->dev_private; | |
678d96fb BW |
1288 | struct i915_hw_ppgtt *ppgtt = |
1289 | container_of(vm, struct i915_hw_ppgtt, base); | |
ec565b3c | 1290 | struct i915_page_table *pt; |
4933d519 | 1291 | const uint32_t start_save = start, length_save = length; |
678d96fb | 1292 | uint32_t pde, temp; |
4933d519 MT |
1293 | int ret; |
1294 | ||
1295 | WARN_ON(upper_32_bits(start)); | |
1296 | ||
1297 | bitmap_zero(new_page_tables, I915_PDES); | |
1298 | ||
1299 | /* The allocation is done in two stages so that we can bail out with | |
1300 | * minimal amount of pain. The first stage finds new page tables that | |
1301 | * need allocation. The second stage marks use ptes within the page | |
1302 | * tables. | |
1303 | */ | |
1304 | gen6_for_each_pde(pt, &ppgtt->pd, start, length, temp, pde) { | |
1305 | if (pt != ppgtt->scratch_pt) { | |
1306 | WARN_ON(bitmap_empty(pt->used_ptes, GEN6_PTES)); | |
1307 | continue; | |
1308 | } | |
1309 | ||
1310 | /* We've already allocated a page table */ | |
1311 | WARN_ON(!bitmap_empty(pt->used_ptes, GEN6_PTES)); | |
1312 | ||
1313 | pt = alloc_pt_single(dev); | |
1314 | if (IS_ERR(pt)) { | |
1315 | ret = PTR_ERR(pt); | |
1316 | goto unwind_out; | |
1317 | } | |
1318 | ||
1319 | gen6_initialize_pt(vm, pt); | |
1320 | ||
1321 | ppgtt->pd.page_table[pde] = pt; | |
1322 | set_bit(pde, new_page_tables); | |
72744cb1 | 1323 | trace_i915_page_table_entry_alloc(vm, pde, start, GEN6_PDE_SHIFT); |
4933d519 MT |
1324 | } |
1325 | ||
1326 | start = start_save; | |
1327 | length = length_save; | |
678d96fb BW |
1328 | |
1329 | gen6_for_each_pde(pt, &ppgtt->pd, start, length, temp, pde) { | |
1330 | DECLARE_BITMAP(tmp_bitmap, GEN6_PTES); | |
1331 | ||
1332 | bitmap_zero(tmp_bitmap, GEN6_PTES); | |
1333 | bitmap_set(tmp_bitmap, gen6_pte_index(start), | |
1334 | gen6_pte_count(start, length)); | |
1335 | ||
4933d519 MT |
1336 | if (test_and_clear_bit(pde, new_page_tables)) |
1337 | gen6_write_pde(&ppgtt->pd, pde, pt); | |
1338 | ||
72744cb1 MT |
1339 | trace_i915_page_table_entry_map(vm, pde, pt, |
1340 | gen6_pte_index(start), | |
1341 | gen6_pte_count(start, length), | |
1342 | GEN6_PTES); | |
4933d519 | 1343 | bitmap_or(pt->used_ptes, tmp_bitmap, pt->used_ptes, |
678d96fb BW |
1344 | GEN6_PTES); |
1345 | } | |
1346 | ||
4933d519 MT |
1347 | WARN_ON(!bitmap_empty(new_page_tables, I915_PDES)); |
1348 | ||
1349 | /* Make sure write is complete before other code can use this page | |
1350 | * table. Also require for WC mapped PTEs */ | |
1351 | readl(dev_priv->gtt.gsm); | |
1352 | ||
563222a7 | 1353 | mark_tlbs_dirty(ppgtt); |
678d96fb | 1354 | return 0; |
4933d519 MT |
1355 | |
1356 | unwind_out: | |
1357 | for_each_set_bit(pde, new_page_tables, I915_PDES) { | |
ec565b3c | 1358 | struct i915_page_table *pt = ppgtt->pd.page_table[pde]; |
4933d519 MT |
1359 | |
1360 | ppgtt->pd.page_table[pde] = ppgtt->scratch_pt; | |
1361 | unmap_and_free_pt(pt, vm->dev); | |
1362 | } | |
1363 | ||
1364 | mark_tlbs_dirty(ppgtt); | |
1365 | return ret; | |
678d96fb BW |
1366 | } |
1367 | ||
061dd493 | 1368 | static void gen6_ppgtt_cleanup(struct i915_address_space *vm) |
a00d825d | 1369 | { |
061dd493 DV |
1370 | struct i915_hw_ppgtt *ppgtt = |
1371 | container_of(vm, struct i915_hw_ppgtt, base); | |
09942c65 MT |
1372 | struct i915_page_table *pt; |
1373 | uint32_t pde; | |
4933d519 | 1374 | |
061dd493 DV |
1375 | |
1376 | drm_mm_remove_node(&ppgtt->node); | |
1377 | ||
09942c65 | 1378 | gen6_for_all_pdes(pt, ppgtt, pde) { |
4933d519 | 1379 | if (pt != ppgtt->scratch_pt) |
09942c65 | 1380 | unmap_and_free_pt(pt, ppgtt->base.dev); |
4933d519 | 1381 | } |
06fda602 | 1382 | |
4933d519 | 1383 | unmap_and_free_pt(ppgtt->scratch_pt, ppgtt->base.dev); |
e5815a2e | 1384 | unmap_and_free_pd(&ppgtt->pd, ppgtt->base.dev); |
3440d265 DV |
1385 | } |
1386 | ||
b146520f | 1387 | static int gen6_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt) |
3440d265 | 1388 | { |
853ba5d2 | 1389 | struct drm_device *dev = ppgtt->base.dev; |
1d2a314c | 1390 | struct drm_i915_private *dev_priv = dev->dev_private; |
e3cc1995 | 1391 | bool retried = false; |
b146520f | 1392 | int ret; |
1d2a314c | 1393 | |
c8d4c0d6 BW |
1394 | /* PPGTT PDEs reside in the GGTT and consists of 512 entries. The |
1395 | * allocator works in address space sizes, so it's multiplied by page | |
1396 | * size. We allocate at the top of the GTT to avoid fragmentation. | |
1397 | */ | |
1398 | BUG_ON(!drm_mm_initialized(&dev_priv->gtt.base.mm)); | |
4933d519 MT |
1399 | ppgtt->scratch_pt = alloc_pt_single(ppgtt->base.dev); |
1400 | if (IS_ERR(ppgtt->scratch_pt)) | |
1401 | return PTR_ERR(ppgtt->scratch_pt); | |
1402 | ||
1403 | gen6_initialize_pt(&ppgtt->base, ppgtt->scratch_pt); | |
1404 | ||
e3cc1995 | 1405 | alloc: |
c8d4c0d6 BW |
1406 | ret = drm_mm_insert_node_in_range_generic(&dev_priv->gtt.base.mm, |
1407 | &ppgtt->node, GEN6_PD_SIZE, | |
1408 | GEN6_PD_ALIGN, 0, | |
1409 | 0, dev_priv->gtt.base.total, | |
3e8b5ae9 | 1410 | DRM_MM_TOPDOWN); |
e3cc1995 BW |
1411 | if (ret == -ENOSPC && !retried) { |
1412 | ret = i915_gem_evict_something(dev, &dev_priv->gtt.base, | |
1413 | GEN6_PD_SIZE, GEN6_PD_ALIGN, | |
d23db88c CW |
1414 | I915_CACHE_NONE, |
1415 | 0, dev_priv->gtt.base.total, | |
1416 | 0); | |
e3cc1995 | 1417 | if (ret) |
678d96fb | 1418 | goto err_out; |
e3cc1995 BW |
1419 | |
1420 | retried = true; | |
1421 | goto alloc; | |
1422 | } | |
c8d4c0d6 | 1423 | |
c8c26622 | 1424 | if (ret) |
678d96fb BW |
1425 | goto err_out; |
1426 | ||
c8c26622 | 1427 | |
c8d4c0d6 BW |
1428 | if (ppgtt->node.start < dev_priv->gtt.mappable_end) |
1429 | DRM_DEBUG("Forced to use aperture for PDEs\n"); | |
1d2a314c | 1430 | |
c8c26622 | 1431 | return 0; |
678d96fb BW |
1432 | |
1433 | err_out: | |
4933d519 | 1434 | unmap_and_free_pt(ppgtt->scratch_pt, ppgtt->base.dev); |
678d96fb | 1435 | return ret; |
b146520f BW |
1436 | } |
1437 | ||
b146520f BW |
1438 | static int gen6_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt) |
1439 | { | |
2f2cf682 | 1440 | return gen6_ppgtt_allocate_page_directories(ppgtt); |
4933d519 | 1441 | } |
06dc68d6 | 1442 | |
4933d519 MT |
1443 | static void gen6_scratch_va_range(struct i915_hw_ppgtt *ppgtt, |
1444 | uint64_t start, uint64_t length) | |
1445 | { | |
ec565b3c | 1446 | struct i915_page_table *unused; |
4933d519 | 1447 | uint32_t pde, temp; |
1d2a314c | 1448 | |
4933d519 MT |
1449 | gen6_for_each_pde(unused, &ppgtt->pd, start, length, temp, pde) |
1450 | ppgtt->pd.page_table[pde] = ppgtt->scratch_pt; | |
b146520f BW |
1451 | } |
1452 | ||
5c5f6457 | 1453 | static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt) |
b146520f BW |
1454 | { |
1455 | struct drm_device *dev = ppgtt->base.dev; | |
1456 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1457 | int ret; | |
1458 | ||
1459 | ppgtt->base.pte_encode = dev_priv->gtt.base.pte_encode; | |
1460 | if (IS_GEN6(dev)) { | |
b146520f BW |
1461 | ppgtt->switch_mm = gen6_mm_switch; |
1462 | } else if (IS_HASWELL(dev)) { | |
b146520f BW |
1463 | ppgtt->switch_mm = hsw_mm_switch; |
1464 | } else if (IS_GEN7(dev)) { | |
b146520f BW |
1465 | ppgtt->switch_mm = gen7_mm_switch; |
1466 | } else | |
1467 | BUG(); | |
1468 | ||
71ba2d64 YZ |
1469 | if (intel_vgpu_active(dev)) |
1470 | ppgtt->switch_mm = vgpu_mm_switch; | |
1471 | ||
b146520f BW |
1472 | ret = gen6_ppgtt_alloc(ppgtt); |
1473 | if (ret) | |
1474 | return ret; | |
1475 | ||
5c5f6457 | 1476 | ppgtt->base.allocate_va_range = gen6_alloc_va_range; |
b146520f BW |
1477 | ppgtt->base.clear_range = gen6_ppgtt_clear_range; |
1478 | ppgtt->base.insert_entries = gen6_ppgtt_insert_entries; | |
777dc5bb DV |
1479 | ppgtt->base.unbind_vma = ppgtt_unbind_vma; |
1480 | ppgtt->base.bind_vma = ppgtt_bind_vma; | |
b146520f | 1481 | ppgtt->base.cleanup = gen6_ppgtt_cleanup; |
b146520f | 1482 | ppgtt->base.start = 0; |
09942c65 | 1483 | ppgtt->base.total = I915_PDES * GEN6_PTES * PAGE_SIZE; |
87d60b63 | 1484 | ppgtt->debug_dump = gen6_dump_ppgtt; |
1d2a314c | 1485 | |
7324cc04 | 1486 | ppgtt->pd.pd_offset = |
07749ef3 | 1487 | ppgtt->node.start / PAGE_SIZE * sizeof(gen6_pte_t); |
1d2a314c | 1488 | |
678d96fb BW |
1489 | ppgtt->pd_addr = (gen6_pte_t __iomem *)dev_priv->gtt.gsm + |
1490 | ppgtt->pd.pd_offset / sizeof(gen6_pte_t); | |
1491 | ||
5c5f6457 | 1492 | gen6_scratch_va_range(ppgtt, 0, ppgtt->base.total); |
1d2a314c | 1493 | |
678d96fb BW |
1494 | gen6_write_page_range(dev_priv, &ppgtt->pd, 0, ppgtt->base.total); |
1495 | ||
440fd528 | 1496 | DRM_DEBUG_DRIVER("Allocated pde space (%lldM) at GTT entry: %llx\n", |
b146520f BW |
1497 | ppgtt->node.size >> 20, |
1498 | ppgtt->node.start / PAGE_SIZE); | |
3440d265 | 1499 | |
fa76da34 | 1500 | DRM_DEBUG("Adding PPGTT at offset %x\n", |
7324cc04 | 1501 | ppgtt->pd.pd_offset << 10); |
fa76da34 | 1502 | |
b146520f | 1503 | return 0; |
3440d265 DV |
1504 | } |
1505 | ||
5c5f6457 | 1506 | static int __hw_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt) |
3440d265 DV |
1507 | { |
1508 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3440d265 | 1509 | |
853ba5d2 | 1510 | ppgtt->base.dev = dev; |
8407bb91 | 1511 | ppgtt->base.scratch = dev_priv->gtt.base.scratch; |
3440d265 | 1512 | |
3ed124b2 | 1513 | if (INTEL_INFO(dev)->gen < 8) |
5c5f6457 | 1514 | return gen6_ppgtt_init(ppgtt); |
3ed124b2 | 1515 | else |
d7b2633d | 1516 | return gen8_ppgtt_init(ppgtt); |
fa76da34 DV |
1517 | } |
1518 | int i915_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt) | |
1519 | { | |
1520 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1521 | int ret = 0; | |
3ed124b2 | 1522 | |
5c5f6457 | 1523 | ret = __hw_ppgtt_init(dev, ppgtt); |
fa76da34 | 1524 | if (ret == 0) { |
c7c48dfd | 1525 | kref_init(&ppgtt->ref); |
93bd8649 BW |
1526 | drm_mm_init(&ppgtt->base.mm, ppgtt->base.start, |
1527 | ppgtt->base.total); | |
7e0d96bc | 1528 | i915_init_vm(dev_priv, &ppgtt->base); |
93bd8649 | 1529 | } |
1d2a314c DV |
1530 | |
1531 | return ret; | |
1532 | } | |
1533 | ||
82460d97 DV |
1534 | int i915_ppgtt_init_hw(struct drm_device *dev) |
1535 | { | |
1536 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1537 | struct intel_engine_cs *ring; | |
1538 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
1539 | int i, ret = 0; | |
1540 | ||
671b5013 TD |
1541 | /* In the case of execlists, PPGTT is enabled by the context descriptor |
1542 | * and the PDPs are contained within the context itself. We don't | |
1543 | * need to do anything here. */ | |
1544 | if (i915.enable_execlists) | |
1545 | return 0; | |
1546 | ||
82460d97 DV |
1547 | if (!USES_PPGTT(dev)) |
1548 | return 0; | |
1549 | ||
1550 | if (IS_GEN6(dev)) | |
1551 | gen6_ppgtt_enable(dev); | |
1552 | else if (IS_GEN7(dev)) | |
1553 | gen7_ppgtt_enable(dev); | |
1554 | else if (INTEL_INFO(dev)->gen >= 8) | |
1555 | gen8_ppgtt_enable(dev); | |
1556 | else | |
5f77eeb0 | 1557 | MISSING_CASE(INTEL_INFO(dev)->gen); |
82460d97 DV |
1558 | |
1559 | if (ppgtt) { | |
1560 | for_each_ring(ring, dev_priv, i) { | |
6689c167 | 1561 | ret = ppgtt->switch_mm(ppgtt, ring); |
82460d97 DV |
1562 | if (ret != 0) |
1563 | return ret; | |
7e0d96bc | 1564 | } |
93bd8649 | 1565 | } |
1d2a314c DV |
1566 | |
1567 | return ret; | |
1568 | } | |
4d884705 DV |
1569 | struct i915_hw_ppgtt * |
1570 | i915_ppgtt_create(struct drm_device *dev, struct drm_i915_file_private *fpriv) | |
1571 | { | |
1572 | struct i915_hw_ppgtt *ppgtt; | |
1573 | int ret; | |
1574 | ||
1575 | ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL); | |
1576 | if (!ppgtt) | |
1577 | return ERR_PTR(-ENOMEM); | |
1578 | ||
1579 | ret = i915_ppgtt_init(dev, ppgtt); | |
1580 | if (ret) { | |
1581 | kfree(ppgtt); | |
1582 | return ERR_PTR(ret); | |
1583 | } | |
1584 | ||
1585 | ppgtt->file_priv = fpriv; | |
1586 | ||
198c974d DCS |
1587 | trace_i915_ppgtt_create(&ppgtt->base); |
1588 | ||
4d884705 DV |
1589 | return ppgtt; |
1590 | } | |
1591 | ||
ee960be7 DV |
1592 | void i915_ppgtt_release(struct kref *kref) |
1593 | { | |
1594 | struct i915_hw_ppgtt *ppgtt = | |
1595 | container_of(kref, struct i915_hw_ppgtt, ref); | |
1596 | ||
198c974d DCS |
1597 | trace_i915_ppgtt_release(&ppgtt->base); |
1598 | ||
ee960be7 DV |
1599 | /* vmas should already be unbound */ |
1600 | WARN_ON(!list_empty(&ppgtt->base.active_list)); | |
1601 | WARN_ON(!list_empty(&ppgtt->base.inactive_list)); | |
1602 | ||
19dd120c DV |
1603 | list_del(&ppgtt->base.global_link); |
1604 | drm_mm_takedown(&ppgtt->base.mm); | |
1605 | ||
ee960be7 DV |
1606 | ppgtt->base.cleanup(&ppgtt->base); |
1607 | kfree(ppgtt); | |
1608 | } | |
1d2a314c | 1609 | |
7e0d96bc | 1610 | static void |
6f65e29a BW |
1611 | ppgtt_bind_vma(struct i915_vma *vma, |
1612 | enum i915_cache_level cache_level, | |
1613 | u32 flags) | |
1d2a314c | 1614 | { |
24f3a8cf AG |
1615 | /* Currently applicable only to VLV */ |
1616 | if (vma->obj->gt_ro) | |
1617 | flags |= PTE_READ_ONLY; | |
1618 | ||
782f1495 | 1619 | vma->vm->insert_entries(vma->vm, vma->obj->pages, vma->node.start, |
24f3a8cf | 1620 | cache_level, flags); |
1d2a314c DV |
1621 | } |
1622 | ||
7e0d96bc | 1623 | static void ppgtt_unbind_vma(struct i915_vma *vma) |
7bddb01f | 1624 | { |
6f65e29a | 1625 | vma->vm->clear_range(vma->vm, |
782f1495 BW |
1626 | vma->node.start, |
1627 | vma->obj->base.size, | |
6f65e29a | 1628 | true); |
7bddb01f DV |
1629 | } |
1630 | ||
a81cc00c BW |
1631 | extern int intel_iommu_gfx_mapped; |
1632 | /* Certain Gen5 chipsets require require idling the GPU before | |
1633 | * unmapping anything from the GTT when VT-d is enabled. | |
1634 | */ | |
1635 | static inline bool needs_idle_maps(struct drm_device *dev) | |
1636 | { | |
1637 | #ifdef CONFIG_INTEL_IOMMU | |
1638 | /* Query intel_iommu to see if we need the workaround. Presumably that | |
1639 | * was loaded first. | |
1640 | */ | |
1641 | if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped) | |
1642 | return true; | |
1643 | #endif | |
1644 | return false; | |
1645 | } | |
1646 | ||
5c042287 BW |
1647 | static bool do_idling(struct drm_i915_private *dev_priv) |
1648 | { | |
1649 | bool ret = dev_priv->mm.interruptible; | |
1650 | ||
a81cc00c | 1651 | if (unlikely(dev_priv->gtt.do_idle_maps)) { |
5c042287 | 1652 | dev_priv->mm.interruptible = false; |
b2da9fe5 | 1653 | if (i915_gpu_idle(dev_priv->dev)) { |
5c042287 BW |
1654 | DRM_ERROR("Couldn't idle GPU\n"); |
1655 | /* Wait a bit, in hopes it avoids the hang */ | |
1656 | udelay(10); | |
1657 | } | |
1658 | } | |
1659 | ||
1660 | return ret; | |
1661 | } | |
1662 | ||
1663 | static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible) | |
1664 | { | |
a81cc00c | 1665 | if (unlikely(dev_priv->gtt.do_idle_maps)) |
5c042287 BW |
1666 | dev_priv->mm.interruptible = interruptible; |
1667 | } | |
1668 | ||
828c7908 BW |
1669 | void i915_check_and_clear_faults(struct drm_device *dev) |
1670 | { | |
1671 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a4872ba6 | 1672 | struct intel_engine_cs *ring; |
828c7908 BW |
1673 | int i; |
1674 | ||
1675 | if (INTEL_INFO(dev)->gen < 6) | |
1676 | return; | |
1677 | ||
1678 | for_each_ring(ring, dev_priv, i) { | |
1679 | u32 fault_reg; | |
1680 | fault_reg = I915_READ(RING_FAULT_REG(ring)); | |
1681 | if (fault_reg & RING_FAULT_VALID) { | |
1682 | DRM_DEBUG_DRIVER("Unexpected fault\n" | |
59a5d290 | 1683 | "\tAddr: 0x%08lx\n" |
828c7908 BW |
1684 | "\tAddress space: %s\n" |
1685 | "\tSource ID: %d\n" | |
1686 | "\tType: %d\n", | |
1687 | fault_reg & PAGE_MASK, | |
1688 | fault_reg & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT", | |
1689 | RING_FAULT_SRCID(fault_reg), | |
1690 | RING_FAULT_FAULT_TYPE(fault_reg)); | |
1691 | I915_WRITE(RING_FAULT_REG(ring), | |
1692 | fault_reg & ~RING_FAULT_VALID); | |
1693 | } | |
1694 | } | |
1695 | POSTING_READ(RING_FAULT_REG(&dev_priv->ring[RCS])); | |
1696 | } | |
1697 | ||
91e56499 CW |
1698 | static void i915_ggtt_flush(struct drm_i915_private *dev_priv) |
1699 | { | |
1700 | if (INTEL_INFO(dev_priv->dev)->gen < 6) { | |
1701 | intel_gtt_chipset_flush(); | |
1702 | } else { | |
1703 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
1704 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
1705 | } | |
1706 | } | |
1707 | ||
828c7908 BW |
1708 | void i915_gem_suspend_gtt_mappings(struct drm_device *dev) |
1709 | { | |
1710 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1711 | ||
1712 | /* Don't bother messing with faults pre GEN6 as we have little | |
1713 | * documentation supporting that it's a good idea. | |
1714 | */ | |
1715 | if (INTEL_INFO(dev)->gen < 6) | |
1716 | return; | |
1717 | ||
1718 | i915_check_and_clear_faults(dev); | |
1719 | ||
1720 | dev_priv->gtt.base.clear_range(&dev_priv->gtt.base, | |
782f1495 BW |
1721 | dev_priv->gtt.base.start, |
1722 | dev_priv->gtt.base.total, | |
e568af1c | 1723 | true); |
91e56499 CW |
1724 | |
1725 | i915_ggtt_flush(dev_priv); | |
828c7908 BW |
1726 | } |
1727 | ||
76aaf220 DV |
1728 | void i915_gem_restore_gtt_mappings(struct drm_device *dev) |
1729 | { | |
1730 | struct drm_i915_private *dev_priv = dev->dev_private; | |
05394f39 | 1731 | struct drm_i915_gem_object *obj; |
80da2161 | 1732 | struct i915_address_space *vm; |
76aaf220 | 1733 | |
828c7908 BW |
1734 | i915_check_and_clear_faults(dev); |
1735 | ||
bee4a186 | 1736 | /* First fill our portion of the GTT with scratch pages */ |
853ba5d2 | 1737 | dev_priv->gtt.base.clear_range(&dev_priv->gtt.base, |
782f1495 BW |
1738 | dev_priv->gtt.base.start, |
1739 | dev_priv->gtt.base.total, | |
828c7908 | 1740 | true); |
bee4a186 | 1741 | |
35c20a60 | 1742 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
6f65e29a BW |
1743 | struct i915_vma *vma = i915_gem_obj_to_vma(obj, |
1744 | &dev_priv->gtt.base); | |
1745 | if (!vma) | |
1746 | continue; | |
1747 | ||
2c22569b | 1748 | i915_gem_clflush_object(obj, obj->pin_display); |
6f65e29a BW |
1749 | /* The bind_vma code tries to be smart about tracking mappings. |
1750 | * Unfortunately above, we've just wiped out the mappings | |
1751 | * without telling our object about it. So we need to fake it. | |
fe14d5f4 TU |
1752 | * |
1753 | * Bind is not expected to fail since this is only called on | |
1754 | * resume and assumption is all requirements exist already. | |
6f65e29a | 1755 | */ |
aff43766 | 1756 | vma->bound &= ~GLOBAL_BIND; |
fe14d5f4 | 1757 | WARN_ON(i915_vma_bind(vma, obj->cache_level, GLOBAL_BIND)); |
76aaf220 DV |
1758 | } |
1759 | ||
80da2161 | 1760 | |
a2319c08 | 1761 | if (INTEL_INFO(dev)->gen >= 8) { |
5a4e33a3 | 1762 | if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev)) |
ee0ce478 VS |
1763 | chv_setup_private_ppat(dev_priv); |
1764 | else | |
1765 | bdw_setup_private_ppat(dev_priv); | |
1766 | ||
80da2161 | 1767 | return; |
a2319c08 | 1768 | } |
80da2161 | 1769 | |
678d96fb BW |
1770 | if (USES_PPGTT(dev)) { |
1771 | list_for_each_entry(vm, &dev_priv->vm_list, global_link) { | |
1772 | /* TODO: Perhaps it shouldn't be gen6 specific */ | |
1773 | ||
1774 | struct i915_hw_ppgtt *ppgtt = | |
1775 | container_of(vm, struct i915_hw_ppgtt, | |
1776 | base); | |
80da2161 | 1777 | |
678d96fb BW |
1778 | if (i915_is_ggtt(vm)) |
1779 | ppgtt = dev_priv->mm.aliasing_ppgtt; | |
1780 | ||
1781 | gen6_write_page_range(dev_priv, &ppgtt->pd, | |
1782 | 0, ppgtt->base.total); | |
1783 | } | |
76aaf220 DV |
1784 | } |
1785 | ||
91e56499 | 1786 | i915_ggtt_flush(dev_priv); |
76aaf220 | 1787 | } |
7c2e6fdf | 1788 | |
74163907 | 1789 | int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj) |
7c2e6fdf | 1790 | { |
9da3da66 | 1791 | if (obj->has_dma_mapping) |
74163907 | 1792 | return 0; |
9da3da66 CW |
1793 | |
1794 | if (!dma_map_sg(&obj->base.dev->pdev->dev, | |
1795 | obj->pages->sgl, obj->pages->nents, | |
1796 | PCI_DMA_BIDIRECTIONAL)) | |
1797 | return -ENOSPC; | |
1798 | ||
1799 | return 0; | |
7c2e6fdf DV |
1800 | } |
1801 | ||
07749ef3 | 1802 | static inline void gen8_set_pte(void __iomem *addr, gen8_pte_t pte) |
94ec8f61 BW |
1803 | { |
1804 | #ifdef writeq | |
1805 | writeq(pte, addr); | |
1806 | #else | |
1807 | iowrite32((u32)pte, addr); | |
1808 | iowrite32(pte >> 32, addr + 4); | |
1809 | #endif | |
1810 | } | |
1811 | ||
1812 | static void gen8_ggtt_insert_entries(struct i915_address_space *vm, | |
1813 | struct sg_table *st, | |
782f1495 | 1814 | uint64_t start, |
24f3a8cf | 1815 | enum i915_cache_level level, u32 unused) |
94ec8f61 BW |
1816 | { |
1817 | struct drm_i915_private *dev_priv = vm->dev->dev_private; | |
782f1495 | 1818 | unsigned first_entry = start >> PAGE_SHIFT; |
07749ef3 MT |
1819 | gen8_pte_t __iomem *gtt_entries = |
1820 | (gen8_pte_t __iomem *)dev_priv->gtt.gsm + first_entry; | |
94ec8f61 BW |
1821 | int i = 0; |
1822 | struct sg_page_iter sg_iter; | |
57007df7 | 1823 | dma_addr_t addr = 0; /* shut up gcc */ |
94ec8f61 BW |
1824 | |
1825 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) { | |
1826 | addr = sg_dma_address(sg_iter.sg) + | |
1827 | (sg_iter.sg_pgoffset << PAGE_SHIFT); | |
1828 | gen8_set_pte(>t_entries[i], | |
1829 | gen8_pte_encode(addr, level, true)); | |
1830 | i++; | |
1831 | } | |
1832 | ||
1833 | /* | |
1834 | * XXX: This serves as a posting read to make sure that the PTE has | |
1835 | * actually been updated. There is some concern that even though | |
1836 | * registers and PTEs are within the same BAR that they are potentially | |
1837 | * of NUMA access patterns. Therefore, even with the way we assume | |
1838 | * hardware should work, we must keep this posting read for paranoia. | |
1839 | */ | |
1840 | if (i != 0) | |
1841 | WARN_ON(readq(>t_entries[i-1]) | |
1842 | != gen8_pte_encode(addr, level, true)); | |
1843 | ||
94ec8f61 BW |
1844 | /* This next bit makes the above posting read even more important. We |
1845 | * want to flush the TLBs only after we're certain all the PTE updates | |
1846 | * have finished. | |
1847 | */ | |
1848 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
1849 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
94ec8f61 BW |
1850 | } |
1851 | ||
e76e9aeb BW |
1852 | /* |
1853 | * Binds an object into the global gtt with the specified cache level. The object | |
1854 | * will be accessible to the GPU via commands whose operands reference offsets | |
1855 | * within the global GTT as well as accessible by the GPU through the GMADR | |
1856 | * mapped BAR (dev_priv->mm.gtt->gtt). | |
1857 | */ | |
853ba5d2 | 1858 | static void gen6_ggtt_insert_entries(struct i915_address_space *vm, |
7faf1ab2 | 1859 | struct sg_table *st, |
782f1495 | 1860 | uint64_t start, |
24f3a8cf | 1861 | enum i915_cache_level level, u32 flags) |
e76e9aeb | 1862 | { |
853ba5d2 | 1863 | struct drm_i915_private *dev_priv = vm->dev->dev_private; |
782f1495 | 1864 | unsigned first_entry = start >> PAGE_SHIFT; |
07749ef3 MT |
1865 | gen6_pte_t __iomem *gtt_entries = |
1866 | (gen6_pte_t __iomem *)dev_priv->gtt.gsm + first_entry; | |
6e995e23 ID |
1867 | int i = 0; |
1868 | struct sg_page_iter sg_iter; | |
57007df7 | 1869 | dma_addr_t addr = 0; |
e76e9aeb | 1870 | |
6e995e23 | 1871 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) { |
2db76d7c | 1872 | addr = sg_page_iter_dma_address(&sg_iter); |
24f3a8cf | 1873 | iowrite32(vm->pte_encode(addr, level, true, flags), >t_entries[i]); |
6e995e23 | 1874 | i++; |
e76e9aeb BW |
1875 | } |
1876 | ||
e76e9aeb BW |
1877 | /* XXX: This serves as a posting read to make sure that the PTE has |
1878 | * actually been updated. There is some concern that even though | |
1879 | * registers and PTEs are within the same BAR that they are potentially | |
1880 | * of NUMA access patterns. Therefore, even with the way we assume | |
1881 | * hardware should work, we must keep this posting read for paranoia. | |
1882 | */ | |
57007df7 PM |
1883 | if (i != 0) { |
1884 | unsigned long gtt = readl(>t_entries[i-1]); | |
1885 | WARN_ON(gtt != vm->pte_encode(addr, level, true, flags)); | |
1886 | } | |
0f9b91c7 BW |
1887 | |
1888 | /* This next bit makes the above posting read even more important. We | |
1889 | * want to flush the TLBs only after we're certain all the PTE updates | |
1890 | * have finished. | |
1891 | */ | |
1892 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
1893 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
e76e9aeb BW |
1894 | } |
1895 | ||
94ec8f61 | 1896 | static void gen8_ggtt_clear_range(struct i915_address_space *vm, |
782f1495 BW |
1897 | uint64_t start, |
1898 | uint64_t length, | |
94ec8f61 BW |
1899 | bool use_scratch) |
1900 | { | |
1901 | struct drm_i915_private *dev_priv = vm->dev->dev_private; | |
782f1495 BW |
1902 | unsigned first_entry = start >> PAGE_SHIFT; |
1903 | unsigned num_entries = length >> PAGE_SHIFT; | |
07749ef3 MT |
1904 | gen8_pte_t scratch_pte, __iomem *gtt_base = |
1905 | (gen8_pte_t __iomem *) dev_priv->gtt.gsm + first_entry; | |
94ec8f61 BW |
1906 | const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry; |
1907 | int i; | |
1908 | ||
1909 | if (WARN(num_entries > max_entries, | |
1910 | "First entry = %d; Num entries = %d (max=%d)\n", | |
1911 | first_entry, num_entries, max_entries)) | |
1912 | num_entries = max_entries; | |
1913 | ||
1914 | scratch_pte = gen8_pte_encode(vm->scratch.addr, | |
1915 | I915_CACHE_LLC, | |
1916 | use_scratch); | |
1917 | for (i = 0; i < num_entries; i++) | |
1918 | gen8_set_pte(>t_base[i], scratch_pte); | |
1919 | readl(gtt_base); | |
1920 | } | |
1921 | ||
853ba5d2 | 1922 | static void gen6_ggtt_clear_range(struct i915_address_space *vm, |
782f1495 BW |
1923 | uint64_t start, |
1924 | uint64_t length, | |
828c7908 | 1925 | bool use_scratch) |
7faf1ab2 | 1926 | { |
853ba5d2 | 1927 | struct drm_i915_private *dev_priv = vm->dev->dev_private; |
782f1495 BW |
1928 | unsigned first_entry = start >> PAGE_SHIFT; |
1929 | unsigned num_entries = length >> PAGE_SHIFT; | |
07749ef3 MT |
1930 | gen6_pte_t scratch_pte, __iomem *gtt_base = |
1931 | (gen6_pte_t __iomem *) dev_priv->gtt.gsm + first_entry; | |
a54c0c27 | 1932 | const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry; |
7faf1ab2 DV |
1933 | int i; |
1934 | ||
1935 | if (WARN(num_entries > max_entries, | |
1936 | "First entry = %d; Num entries = %d (max=%d)\n", | |
1937 | first_entry, num_entries, max_entries)) | |
1938 | num_entries = max_entries; | |
1939 | ||
24f3a8cf | 1940 | scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, use_scratch, 0); |
828c7908 | 1941 | |
7faf1ab2 DV |
1942 | for (i = 0; i < num_entries; i++) |
1943 | iowrite32(scratch_pte, >t_base[i]); | |
1944 | readl(gtt_base); | |
1945 | } | |
1946 | ||
6f65e29a BW |
1947 | |
1948 | static void i915_ggtt_bind_vma(struct i915_vma *vma, | |
1949 | enum i915_cache_level cache_level, | |
1950 | u32 unused) | |
7faf1ab2 | 1951 | { |
6f65e29a | 1952 | const unsigned long entry = vma->node.start >> PAGE_SHIFT; |
7faf1ab2 DV |
1953 | unsigned int flags = (cache_level == I915_CACHE_NONE) ? |
1954 | AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY; | |
1955 | ||
6f65e29a | 1956 | BUG_ON(!i915_is_ggtt(vma->vm)); |
fe14d5f4 | 1957 | intel_gtt_insert_sg_entries(vma->ggtt_view.pages, entry, flags); |
aff43766 | 1958 | vma->bound = GLOBAL_BIND; |
7faf1ab2 DV |
1959 | } |
1960 | ||
853ba5d2 | 1961 | static void i915_ggtt_clear_range(struct i915_address_space *vm, |
782f1495 BW |
1962 | uint64_t start, |
1963 | uint64_t length, | |
828c7908 | 1964 | bool unused) |
7faf1ab2 | 1965 | { |
782f1495 BW |
1966 | unsigned first_entry = start >> PAGE_SHIFT; |
1967 | unsigned num_entries = length >> PAGE_SHIFT; | |
7faf1ab2 DV |
1968 | intel_gtt_clear_range(first_entry, num_entries); |
1969 | } | |
1970 | ||
6f65e29a BW |
1971 | static void i915_ggtt_unbind_vma(struct i915_vma *vma) |
1972 | { | |
1973 | const unsigned int first = vma->node.start >> PAGE_SHIFT; | |
1974 | const unsigned int size = vma->obj->base.size >> PAGE_SHIFT; | |
7faf1ab2 | 1975 | |
6f65e29a | 1976 | BUG_ON(!i915_is_ggtt(vma->vm)); |
aff43766 | 1977 | vma->bound = 0; |
6f65e29a BW |
1978 | intel_gtt_clear_range(first, size); |
1979 | } | |
7faf1ab2 | 1980 | |
6f65e29a BW |
1981 | static void ggtt_bind_vma(struct i915_vma *vma, |
1982 | enum i915_cache_level cache_level, | |
1983 | u32 flags) | |
d5bd1449 | 1984 | { |
6f65e29a | 1985 | struct drm_device *dev = vma->vm->dev; |
7faf1ab2 | 1986 | struct drm_i915_private *dev_priv = dev->dev_private; |
6f65e29a | 1987 | struct drm_i915_gem_object *obj = vma->obj; |
ec7adb6e | 1988 | struct sg_table *pages = obj->pages; |
7faf1ab2 | 1989 | |
24f3a8cf AG |
1990 | /* Currently applicable only to VLV */ |
1991 | if (obj->gt_ro) | |
1992 | flags |= PTE_READ_ONLY; | |
1993 | ||
ec7adb6e JL |
1994 | if (i915_is_ggtt(vma->vm)) |
1995 | pages = vma->ggtt_view.pages; | |
1996 | ||
6f65e29a BW |
1997 | /* If there is no aliasing PPGTT, or the caller needs a global mapping, |
1998 | * or we have a global mapping already but the cacheability flags have | |
1999 | * changed, set the global PTEs. | |
2000 | * | |
2001 | * If there is an aliasing PPGTT it is anecdotally faster, so use that | |
2002 | * instead if none of the above hold true. | |
2003 | * | |
2004 | * NB: A global mapping should only be needed for special regions like | |
2005 | * "gtt mappable", SNB errata, or if specified via special execbuf | |
2006 | * flags. At all other times, the GPU will use the aliasing PPGTT. | |
2007 | */ | |
2008 | if (!dev_priv->mm.aliasing_ppgtt || flags & GLOBAL_BIND) { | |
aff43766 | 2009 | if (!(vma->bound & GLOBAL_BIND) || |
6f65e29a | 2010 | (cache_level != obj->cache_level)) { |
ec7adb6e | 2011 | vma->vm->insert_entries(vma->vm, pages, |
782f1495 | 2012 | vma->node.start, |
24f3a8cf | 2013 | cache_level, flags); |
aff43766 | 2014 | vma->bound |= GLOBAL_BIND; |
6f65e29a BW |
2015 | } |
2016 | } | |
d5bd1449 | 2017 | |
6f65e29a | 2018 | if (dev_priv->mm.aliasing_ppgtt && |
aff43766 | 2019 | (!(vma->bound & LOCAL_BIND) || |
6f65e29a BW |
2020 | (cache_level != obj->cache_level))) { |
2021 | struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt; | |
ec7adb6e | 2022 | appgtt->base.insert_entries(&appgtt->base, pages, |
782f1495 | 2023 | vma->node.start, |
24f3a8cf | 2024 | cache_level, flags); |
aff43766 | 2025 | vma->bound |= LOCAL_BIND; |
6f65e29a | 2026 | } |
d5bd1449 CW |
2027 | } |
2028 | ||
6f65e29a | 2029 | static void ggtt_unbind_vma(struct i915_vma *vma) |
74163907 | 2030 | { |
6f65e29a | 2031 | struct drm_device *dev = vma->vm->dev; |
7faf1ab2 | 2032 | struct drm_i915_private *dev_priv = dev->dev_private; |
6f65e29a | 2033 | struct drm_i915_gem_object *obj = vma->obj; |
6f65e29a | 2034 | |
aff43766 | 2035 | if (vma->bound & GLOBAL_BIND) { |
782f1495 BW |
2036 | vma->vm->clear_range(vma->vm, |
2037 | vma->node.start, | |
2038 | obj->base.size, | |
6f65e29a | 2039 | true); |
aff43766 | 2040 | vma->bound &= ~GLOBAL_BIND; |
6f65e29a | 2041 | } |
74898d7e | 2042 | |
aff43766 | 2043 | if (vma->bound & LOCAL_BIND) { |
6f65e29a BW |
2044 | struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt; |
2045 | appgtt->base.clear_range(&appgtt->base, | |
782f1495 BW |
2046 | vma->node.start, |
2047 | obj->base.size, | |
6f65e29a | 2048 | true); |
aff43766 | 2049 | vma->bound &= ~LOCAL_BIND; |
6f65e29a | 2050 | } |
74163907 DV |
2051 | } |
2052 | ||
2053 | void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj) | |
7c2e6fdf | 2054 | { |
5c042287 BW |
2055 | struct drm_device *dev = obj->base.dev; |
2056 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2057 | bool interruptible; | |
2058 | ||
2059 | interruptible = do_idling(dev_priv); | |
2060 | ||
9da3da66 CW |
2061 | if (!obj->has_dma_mapping) |
2062 | dma_unmap_sg(&dev->pdev->dev, | |
2063 | obj->pages->sgl, obj->pages->nents, | |
2064 | PCI_DMA_BIDIRECTIONAL); | |
5c042287 BW |
2065 | |
2066 | undo_idling(dev_priv, interruptible); | |
7c2e6fdf | 2067 | } |
644ec02b | 2068 | |
42d6ab48 CW |
2069 | static void i915_gtt_color_adjust(struct drm_mm_node *node, |
2070 | unsigned long color, | |
440fd528 TR |
2071 | u64 *start, |
2072 | u64 *end) | |
42d6ab48 CW |
2073 | { |
2074 | if (node->color != color) | |
2075 | *start += 4096; | |
2076 | ||
2077 | if (!list_empty(&node->node_list)) { | |
2078 | node = list_entry(node->node_list.next, | |
2079 | struct drm_mm_node, | |
2080 | node_list); | |
2081 | if (node->allocated && node->color != color) | |
2082 | *end -= 4096; | |
2083 | } | |
2084 | } | |
fbe5d36e | 2085 | |
f548c0e9 DV |
2086 | static int i915_gem_setup_global_gtt(struct drm_device *dev, |
2087 | unsigned long start, | |
2088 | unsigned long mappable_end, | |
2089 | unsigned long end) | |
644ec02b | 2090 | { |
e78891ca BW |
2091 | /* Let GEM Manage all of the aperture. |
2092 | * | |
2093 | * However, leave one page at the end still bound to the scratch page. | |
2094 | * There are a number of places where the hardware apparently prefetches | |
2095 | * past the end of the object, and we've seen multiple hangs with the | |
2096 | * GPU head pointer stuck in a batchbuffer bound at the last page of the | |
2097 | * aperture. One page should be enough to keep any prefetching inside | |
2098 | * of the aperture. | |
2099 | */ | |
40d74980 BW |
2100 | struct drm_i915_private *dev_priv = dev->dev_private; |
2101 | struct i915_address_space *ggtt_vm = &dev_priv->gtt.base; | |
ed2f3452 CW |
2102 | struct drm_mm_node *entry; |
2103 | struct drm_i915_gem_object *obj; | |
2104 | unsigned long hole_start, hole_end; | |
fa76da34 | 2105 | int ret; |
644ec02b | 2106 | |
35451cb6 BW |
2107 | BUG_ON(mappable_end > end); |
2108 | ||
ed2f3452 | 2109 | /* Subtract the guard page ... */ |
40d74980 | 2110 | drm_mm_init(&ggtt_vm->mm, start, end - start - PAGE_SIZE); |
5dda8fa3 YZ |
2111 | |
2112 | dev_priv->gtt.base.start = start; | |
2113 | dev_priv->gtt.base.total = end - start; | |
2114 | ||
2115 | if (intel_vgpu_active(dev)) { | |
2116 | ret = intel_vgt_balloon(dev); | |
2117 | if (ret) | |
2118 | return ret; | |
2119 | } | |
2120 | ||
42d6ab48 | 2121 | if (!HAS_LLC(dev)) |
93bd8649 | 2122 | dev_priv->gtt.base.mm.color_adjust = i915_gtt_color_adjust; |
644ec02b | 2123 | |
ed2f3452 | 2124 | /* Mark any preallocated objects as occupied */ |
35c20a60 | 2125 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
40d74980 | 2126 | struct i915_vma *vma = i915_gem_obj_to_vma(obj, ggtt_vm); |
fa76da34 | 2127 | |
edd41a87 | 2128 | DRM_DEBUG_KMS("reserving preallocated space: %lx + %zx\n", |
c6cfb325 BW |
2129 | i915_gem_obj_ggtt_offset(obj), obj->base.size); |
2130 | ||
2131 | WARN_ON(i915_gem_obj_ggtt_bound(obj)); | |
40d74980 | 2132 | ret = drm_mm_reserve_node(&ggtt_vm->mm, &vma->node); |
6c5566a8 DV |
2133 | if (ret) { |
2134 | DRM_DEBUG_KMS("Reservation failed: %i\n", ret); | |
2135 | return ret; | |
2136 | } | |
aff43766 | 2137 | vma->bound |= GLOBAL_BIND; |
ed2f3452 CW |
2138 | } |
2139 | ||
ed2f3452 | 2140 | /* Clear any non-preallocated blocks */ |
40d74980 | 2141 | drm_mm_for_each_hole(entry, &ggtt_vm->mm, hole_start, hole_end) { |
ed2f3452 CW |
2142 | DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n", |
2143 | hole_start, hole_end); | |
782f1495 BW |
2144 | ggtt_vm->clear_range(ggtt_vm, hole_start, |
2145 | hole_end - hole_start, true); | |
ed2f3452 CW |
2146 | } |
2147 | ||
2148 | /* And finally clear the reserved guard page */ | |
782f1495 | 2149 | ggtt_vm->clear_range(ggtt_vm, end - PAGE_SIZE, PAGE_SIZE, true); |
6c5566a8 | 2150 | |
fa76da34 DV |
2151 | if (USES_PPGTT(dev) && !USES_FULL_PPGTT(dev)) { |
2152 | struct i915_hw_ppgtt *ppgtt; | |
2153 | ||
2154 | ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL); | |
2155 | if (!ppgtt) | |
2156 | return -ENOMEM; | |
2157 | ||
5c5f6457 DV |
2158 | ret = __hw_ppgtt_init(dev, ppgtt); |
2159 | if (ret) { | |
2160 | ppgtt->base.cleanup(&ppgtt->base); | |
2161 | kfree(ppgtt); | |
2162 | return ret; | |
2163 | } | |
2164 | ||
2165 | if (ppgtt->base.allocate_va_range) | |
2166 | ret = ppgtt->base.allocate_va_range(&ppgtt->base, 0, | |
2167 | ppgtt->base.total); | |
4933d519 | 2168 | if (ret) { |
061dd493 | 2169 | ppgtt->base.cleanup(&ppgtt->base); |
4933d519 | 2170 | kfree(ppgtt); |
fa76da34 | 2171 | return ret; |
4933d519 | 2172 | } |
fa76da34 | 2173 | |
5c5f6457 DV |
2174 | ppgtt->base.clear_range(&ppgtt->base, |
2175 | ppgtt->base.start, | |
2176 | ppgtt->base.total, | |
2177 | true); | |
2178 | ||
fa76da34 DV |
2179 | dev_priv->mm.aliasing_ppgtt = ppgtt; |
2180 | } | |
2181 | ||
6c5566a8 | 2182 | return 0; |
e76e9aeb BW |
2183 | } |
2184 | ||
d7e5008f BW |
2185 | void i915_gem_init_global_gtt(struct drm_device *dev) |
2186 | { | |
2187 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2188 | unsigned long gtt_size, mappable_size; | |
d7e5008f | 2189 | |
853ba5d2 | 2190 | gtt_size = dev_priv->gtt.base.total; |
93d18799 | 2191 | mappable_size = dev_priv->gtt.mappable_end; |
d7e5008f | 2192 | |
e78891ca | 2193 | i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size); |
e76e9aeb BW |
2194 | } |
2195 | ||
90d0a0e8 DV |
2196 | void i915_global_gtt_cleanup(struct drm_device *dev) |
2197 | { | |
2198 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2199 | struct i915_address_space *vm = &dev_priv->gtt.base; | |
2200 | ||
70e32544 DV |
2201 | if (dev_priv->mm.aliasing_ppgtt) { |
2202 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
2203 | ||
2204 | ppgtt->base.cleanup(&ppgtt->base); | |
2205 | } | |
2206 | ||
90d0a0e8 | 2207 | if (drm_mm_initialized(&vm->mm)) { |
5dda8fa3 YZ |
2208 | if (intel_vgpu_active(dev)) |
2209 | intel_vgt_deballoon(); | |
2210 | ||
90d0a0e8 DV |
2211 | drm_mm_takedown(&vm->mm); |
2212 | list_del(&vm->global_link); | |
2213 | } | |
2214 | ||
2215 | vm->cleanup(vm); | |
2216 | } | |
70e32544 | 2217 | |
e76e9aeb BW |
2218 | static int setup_scratch_page(struct drm_device *dev) |
2219 | { | |
2220 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2221 | struct page *page; | |
2222 | dma_addr_t dma_addr; | |
2223 | ||
2224 | page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO); | |
2225 | if (page == NULL) | |
2226 | return -ENOMEM; | |
e76e9aeb BW |
2227 | set_pages_uc(page, 1); |
2228 | ||
2229 | #ifdef CONFIG_INTEL_IOMMU | |
2230 | dma_addr = pci_map_page(dev->pdev, page, 0, PAGE_SIZE, | |
2231 | PCI_DMA_BIDIRECTIONAL); | |
2232 | if (pci_dma_mapping_error(dev->pdev, dma_addr)) | |
2233 | return -EINVAL; | |
2234 | #else | |
2235 | dma_addr = page_to_phys(page); | |
2236 | #endif | |
853ba5d2 BW |
2237 | dev_priv->gtt.base.scratch.page = page; |
2238 | dev_priv->gtt.base.scratch.addr = dma_addr; | |
e76e9aeb BW |
2239 | |
2240 | return 0; | |
2241 | } | |
2242 | ||
2243 | static void teardown_scratch_page(struct drm_device *dev) | |
2244 | { | |
2245 | struct drm_i915_private *dev_priv = dev->dev_private; | |
853ba5d2 BW |
2246 | struct page *page = dev_priv->gtt.base.scratch.page; |
2247 | ||
2248 | set_pages_wb(page, 1); | |
2249 | pci_unmap_page(dev->pdev, dev_priv->gtt.base.scratch.addr, | |
e76e9aeb | 2250 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); |
853ba5d2 | 2251 | __free_page(page); |
e76e9aeb BW |
2252 | } |
2253 | ||
2254 | static inline unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl) | |
2255 | { | |
2256 | snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT; | |
2257 | snb_gmch_ctl &= SNB_GMCH_GGMS_MASK; | |
2258 | return snb_gmch_ctl << 20; | |
2259 | } | |
2260 | ||
9459d252 BW |
2261 | static inline unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl) |
2262 | { | |
2263 | bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT; | |
2264 | bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK; | |
2265 | if (bdw_gmch_ctl) | |
2266 | bdw_gmch_ctl = 1 << bdw_gmch_ctl; | |
562d55d9 BW |
2267 | |
2268 | #ifdef CONFIG_X86_32 | |
2269 | /* Limit 32b platforms to a 2GB GGTT: 4 << 20 / pte size * PAGE_SIZE */ | |
2270 | if (bdw_gmch_ctl > 4) | |
2271 | bdw_gmch_ctl = 4; | |
2272 | #endif | |
2273 | ||
9459d252 BW |
2274 | return bdw_gmch_ctl << 20; |
2275 | } | |
2276 | ||
d7f25f23 DL |
2277 | static inline unsigned int chv_get_total_gtt_size(u16 gmch_ctrl) |
2278 | { | |
2279 | gmch_ctrl >>= SNB_GMCH_GGMS_SHIFT; | |
2280 | gmch_ctrl &= SNB_GMCH_GGMS_MASK; | |
2281 | ||
2282 | if (gmch_ctrl) | |
2283 | return 1 << (20 + gmch_ctrl); | |
2284 | ||
2285 | return 0; | |
2286 | } | |
2287 | ||
baa09f5f | 2288 | static inline size_t gen6_get_stolen_size(u16 snb_gmch_ctl) |
e76e9aeb BW |
2289 | { |
2290 | snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT; | |
2291 | snb_gmch_ctl &= SNB_GMCH_GMS_MASK; | |
2292 | return snb_gmch_ctl << 25; /* 32 MB units */ | |
2293 | } | |
2294 | ||
9459d252 BW |
2295 | static inline size_t gen8_get_stolen_size(u16 bdw_gmch_ctl) |
2296 | { | |
2297 | bdw_gmch_ctl >>= BDW_GMCH_GMS_SHIFT; | |
2298 | bdw_gmch_ctl &= BDW_GMCH_GMS_MASK; | |
2299 | return bdw_gmch_ctl << 25; /* 32 MB units */ | |
2300 | } | |
2301 | ||
d7f25f23 DL |
2302 | static size_t chv_get_stolen_size(u16 gmch_ctrl) |
2303 | { | |
2304 | gmch_ctrl >>= SNB_GMCH_GMS_SHIFT; | |
2305 | gmch_ctrl &= SNB_GMCH_GMS_MASK; | |
2306 | ||
2307 | /* | |
2308 | * 0x0 to 0x10: 32MB increments starting at 0MB | |
2309 | * 0x11 to 0x16: 4MB increments starting at 8MB | |
2310 | * 0x17 to 0x1d: 4MB increments start at 36MB | |
2311 | */ | |
2312 | if (gmch_ctrl < 0x11) | |
2313 | return gmch_ctrl << 25; | |
2314 | else if (gmch_ctrl < 0x17) | |
2315 | return (gmch_ctrl - 0x11 + 2) << 22; | |
2316 | else | |
2317 | return (gmch_ctrl - 0x17 + 9) << 22; | |
2318 | } | |
2319 | ||
66375014 DL |
2320 | static size_t gen9_get_stolen_size(u16 gen9_gmch_ctl) |
2321 | { | |
2322 | gen9_gmch_ctl >>= BDW_GMCH_GMS_SHIFT; | |
2323 | gen9_gmch_ctl &= BDW_GMCH_GMS_MASK; | |
2324 | ||
2325 | if (gen9_gmch_ctl < 0xf0) | |
2326 | return gen9_gmch_ctl << 25; /* 32 MB units */ | |
2327 | else | |
2328 | /* 4MB increments starting at 0xf0 for 4MB */ | |
2329 | return (gen9_gmch_ctl - 0xf0 + 1) << 22; | |
2330 | } | |
2331 | ||
63340133 BW |
2332 | static int ggtt_probe_common(struct drm_device *dev, |
2333 | size_t gtt_size) | |
2334 | { | |
2335 | struct drm_i915_private *dev_priv = dev->dev_private; | |
21c34607 | 2336 | phys_addr_t gtt_phys_addr; |
63340133 BW |
2337 | int ret; |
2338 | ||
2339 | /* For Modern GENs the PTEs and register space are split in the BAR */ | |
21c34607 | 2340 | gtt_phys_addr = pci_resource_start(dev->pdev, 0) + |
63340133 BW |
2341 | (pci_resource_len(dev->pdev, 0) / 2); |
2342 | ||
2a073f89 ID |
2343 | /* |
2344 | * On BXT writes larger than 64 bit to the GTT pagetable range will be | |
2345 | * dropped. For WC mappings in general we have 64 byte burst writes | |
2346 | * when the WC buffer is flushed, so we can't use it, but have to | |
2347 | * resort to an uncached mapping. The WC issue is easily caught by the | |
2348 | * readback check when writing GTT PTE entries. | |
2349 | */ | |
2350 | if (IS_BROXTON(dev)) | |
2351 | dev_priv->gtt.gsm = ioremap_nocache(gtt_phys_addr, gtt_size); | |
2352 | else | |
2353 | dev_priv->gtt.gsm = ioremap_wc(gtt_phys_addr, gtt_size); | |
63340133 BW |
2354 | if (!dev_priv->gtt.gsm) { |
2355 | DRM_ERROR("Failed to map the gtt page table\n"); | |
2356 | return -ENOMEM; | |
2357 | } | |
2358 | ||
2359 | ret = setup_scratch_page(dev); | |
2360 | if (ret) { | |
2361 | DRM_ERROR("Scratch setup failed\n"); | |
2362 | /* iounmap will also get called at remove, but meh */ | |
2363 | iounmap(dev_priv->gtt.gsm); | |
2364 | } | |
2365 | ||
2366 | return ret; | |
2367 | } | |
2368 | ||
fbe5d36e BW |
2369 | /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability |
2370 | * bits. When using advanced contexts each context stores its own PAT, but | |
2371 | * writing this data shouldn't be harmful even in those cases. */ | |
ee0ce478 | 2372 | static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv) |
fbe5d36e | 2373 | { |
fbe5d36e BW |
2374 | uint64_t pat; |
2375 | ||
2376 | pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC) | /* for normal objects, no eLLC */ | |
2377 | GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something pointing to ptes? */ | |
2378 | GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC) | /* for scanout with eLLC */ | |
2379 | GEN8_PPAT(3, GEN8_PPAT_UC) | /* Uncached objects, mostly for scanout */ | |
2380 | GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) | | |
2381 | GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) | | |
2382 | GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) | | |
2383 | GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3)); | |
2384 | ||
d6a8b72e RV |
2385 | if (!USES_PPGTT(dev_priv->dev)) |
2386 | /* Spec: "For GGTT, there is NO pat_sel[2:0] from the entry, | |
2387 | * so RTL will always use the value corresponding to | |
2388 | * pat_sel = 000". | |
2389 | * So let's disable cache for GGTT to avoid screen corruptions. | |
2390 | * MOCS still can be used though. | |
2391 | * - System agent ggtt writes (i.e. cpu gtt mmaps) already work | |
2392 | * before this patch, i.e. the same uncached + snooping access | |
2393 | * like on gen6/7 seems to be in effect. | |
2394 | * - So this just fixes blitter/render access. Again it looks | |
2395 | * like it's not just uncached access, but uncached + snooping. | |
2396 | * So we can still hold onto all our assumptions wrt cpu | |
2397 | * clflushing on LLC machines. | |
2398 | */ | |
2399 | pat = GEN8_PPAT(0, GEN8_PPAT_UC); | |
2400 | ||
fbe5d36e BW |
2401 | /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b |
2402 | * write would work. */ | |
2403 | I915_WRITE(GEN8_PRIVATE_PAT, pat); | |
2404 | I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32); | |
2405 | } | |
2406 | ||
ee0ce478 VS |
2407 | static void chv_setup_private_ppat(struct drm_i915_private *dev_priv) |
2408 | { | |
2409 | uint64_t pat; | |
2410 | ||
2411 | /* | |
2412 | * Map WB on BDW to snooped on CHV. | |
2413 | * | |
2414 | * Only the snoop bit has meaning for CHV, the rest is | |
2415 | * ignored. | |
2416 | * | |
cf3d262e VS |
2417 | * The hardware will never snoop for certain types of accesses: |
2418 | * - CPU GTT (GMADR->GGTT->no snoop->memory) | |
2419 | * - PPGTT page tables | |
2420 | * - some other special cycles | |
2421 | * | |
2422 | * As with BDW, we also need to consider the following for GT accesses: | |
2423 | * "For GGTT, there is NO pat_sel[2:0] from the entry, | |
2424 | * so RTL will always use the value corresponding to | |
2425 | * pat_sel = 000". | |
2426 | * Which means we must set the snoop bit in PAT entry 0 | |
2427 | * in order to keep the global status page working. | |
ee0ce478 VS |
2428 | */ |
2429 | pat = GEN8_PPAT(0, CHV_PPAT_SNOOP) | | |
2430 | GEN8_PPAT(1, 0) | | |
2431 | GEN8_PPAT(2, 0) | | |
2432 | GEN8_PPAT(3, 0) | | |
2433 | GEN8_PPAT(4, CHV_PPAT_SNOOP) | | |
2434 | GEN8_PPAT(5, CHV_PPAT_SNOOP) | | |
2435 | GEN8_PPAT(6, CHV_PPAT_SNOOP) | | |
2436 | GEN8_PPAT(7, CHV_PPAT_SNOOP); | |
2437 | ||
2438 | I915_WRITE(GEN8_PRIVATE_PAT, pat); | |
2439 | I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32); | |
2440 | } | |
2441 | ||
63340133 BW |
2442 | static int gen8_gmch_probe(struct drm_device *dev, |
2443 | size_t *gtt_total, | |
2444 | size_t *stolen, | |
2445 | phys_addr_t *mappable_base, | |
2446 | unsigned long *mappable_end) | |
2447 | { | |
2448 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2449 | unsigned int gtt_size; | |
2450 | u16 snb_gmch_ctl; | |
2451 | int ret; | |
2452 | ||
2453 | /* TODO: We're not aware of mappable constraints on gen8 yet */ | |
2454 | *mappable_base = pci_resource_start(dev->pdev, 2); | |
2455 | *mappable_end = pci_resource_len(dev->pdev, 2); | |
2456 | ||
2457 | if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(39))) | |
2458 | pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(39)); | |
2459 | ||
2460 | pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl); | |
2461 | ||
66375014 DL |
2462 | if (INTEL_INFO(dev)->gen >= 9) { |
2463 | *stolen = gen9_get_stolen_size(snb_gmch_ctl); | |
2464 | gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl); | |
2465 | } else if (IS_CHERRYVIEW(dev)) { | |
d7f25f23 DL |
2466 | *stolen = chv_get_stolen_size(snb_gmch_ctl); |
2467 | gtt_size = chv_get_total_gtt_size(snb_gmch_ctl); | |
2468 | } else { | |
2469 | *stolen = gen8_get_stolen_size(snb_gmch_ctl); | |
2470 | gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl); | |
2471 | } | |
63340133 | 2472 | |
07749ef3 | 2473 | *gtt_total = (gtt_size / sizeof(gen8_pte_t)) << PAGE_SHIFT; |
63340133 | 2474 | |
5a4e33a3 | 2475 | if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev)) |
ee0ce478 VS |
2476 | chv_setup_private_ppat(dev_priv); |
2477 | else | |
2478 | bdw_setup_private_ppat(dev_priv); | |
fbe5d36e | 2479 | |
63340133 BW |
2480 | ret = ggtt_probe_common(dev, gtt_size); |
2481 | ||
94ec8f61 BW |
2482 | dev_priv->gtt.base.clear_range = gen8_ggtt_clear_range; |
2483 | dev_priv->gtt.base.insert_entries = gen8_ggtt_insert_entries; | |
777dc5bb DV |
2484 | dev_priv->gtt.base.bind_vma = ggtt_bind_vma; |
2485 | dev_priv->gtt.base.unbind_vma = ggtt_unbind_vma; | |
63340133 BW |
2486 | |
2487 | return ret; | |
2488 | } | |
2489 | ||
baa09f5f BW |
2490 | static int gen6_gmch_probe(struct drm_device *dev, |
2491 | size_t *gtt_total, | |
41907ddc BW |
2492 | size_t *stolen, |
2493 | phys_addr_t *mappable_base, | |
2494 | unsigned long *mappable_end) | |
e76e9aeb BW |
2495 | { |
2496 | struct drm_i915_private *dev_priv = dev->dev_private; | |
baa09f5f | 2497 | unsigned int gtt_size; |
e76e9aeb | 2498 | u16 snb_gmch_ctl; |
e76e9aeb BW |
2499 | int ret; |
2500 | ||
41907ddc BW |
2501 | *mappable_base = pci_resource_start(dev->pdev, 2); |
2502 | *mappable_end = pci_resource_len(dev->pdev, 2); | |
2503 | ||
baa09f5f BW |
2504 | /* 64/512MB is the current min/max we actually know of, but this is just |
2505 | * a coarse sanity check. | |
e76e9aeb | 2506 | */ |
41907ddc | 2507 | if ((*mappable_end < (64<<20) || (*mappable_end > (512<<20)))) { |
baa09f5f BW |
2508 | DRM_ERROR("Unknown GMADR size (%lx)\n", |
2509 | dev_priv->gtt.mappable_end); | |
2510 | return -ENXIO; | |
e76e9aeb BW |
2511 | } |
2512 | ||
e76e9aeb BW |
2513 | if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40))) |
2514 | pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40)); | |
e76e9aeb | 2515 | pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl); |
e76e9aeb | 2516 | |
c4ae25ec | 2517 | *stolen = gen6_get_stolen_size(snb_gmch_ctl); |
a93e4161 | 2518 | |
63340133 | 2519 | gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl); |
07749ef3 | 2520 | *gtt_total = (gtt_size / sizeof(gen6_pte_t)) << PAGE_SHIFT; |
e76e9aeb | 2521 | |
63340133 | 2522 | ret = ggtt_probe_common(dev, gtt_size); |
e76e9aeb | 2523 | |
853ba5d2 BW |
2524 | dev_priv->gtt.base.clear_range = gen6_ggtt_clear_range; |
2525 | dev_priv->gtt.base.insert_entries = gen6_ggtt_insert_entries; | |
777dc5bb DV |
2526 | dev_priv->gtt.base.bind_vma = ggtt_bind_vma; |
2527 | dev_priv->gtt.base.unbind_vma = ggtt_unbind_vma; | |
7faf1ab2 | 2528 | |
e76e9aeb BW |
2529 | return ret; |
2530 | } | |
2531 | ||
853ba5d2 | 2532 | static void gen6_gmch_remove(struct i915_address_space *vm) |
e76e9aeb | 2533 | { |
853ba5d2 BW |
2534 | |
2535 | struct i915_gtt *gtt = container_of(vm, struct i915_gtt, base); | |
5ed16782 | 2536 | |
853ba5d2 BW |
2537 | iounmap(gtt->gsm); |
2538 | teardown_scratch_page(vm->dev); | |
644ec02b | 2539 | } |
baa09f5f BW |
2540 | |
2541 | static int i915_gmch_probe(struct drm_device *dev, | |
2542 | size_t *gtt_total, | |
41907ddc BW |
2543 | size_t *stolen, |
2544 | phys_addr_t *mappable_base, | |
2545 | unsigned long *mappable_end) | |
baa09f5f BW |
2546 | { |
2547 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2548 | int ret; | |
2549 | ||
baa09f5f BW |
2550 | ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->dev->pdev, NULL); |
2551 | if (!ret) { | |
2552 | DRM_ERROR("failed to set up gmch\n"); | |
2553 | return -EIO; | |
2554 | } | |
2555 | ||
41907ddc | 2556 | intel_gtt_get(gtt_total, stolen, mappable_base, mappable_end); |
baa09f5f BW |
2557 | |
2558 | dev_priv->gtt.do_idle_maps = needs_idle_maps(dev_priv->dev); | |
853ba5d2 | 2559 | dev_priv->gtt.base.clear_range = i915_ggtt_clear_range; |
777dc5bb DV |
2560 | dev_priv->gtt.base.bind_vma = i915_ggtt_bind_vma; |
2561 | dev_priv->gtt.base.unbind_vma = i915_ggtt_unbind_vma; | |
baa09f5f | 2562 | |
c0a7f818 CW |
2563 | if (unlikely(dev_priv->gtt.do_idle_maps)) |
2564 | DRM_INFO("applying Ironlake quirks for intel_iommu\n"); | |
2565 | ||
baa09f5f BW |
2566 | return 0; |
2567 | } | |
2568 | ||
853ba5d2 | 2569 | static void i915_gmch_remove(struct i915_address_space *vm) |
baa09f5f BW |
2570 | { |
2571 | intel_gmch_remove(); | |
2572 | } | |
2573 | ||
2574 | int i915_gem_gtt_init(struct drm_device *dev) | |
2575 | { | |
2576 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2577 | struct i915_gtt *gtt = &dev_priv->gtt; | |
baa09f5f BW |
2578 | int ret; |
2579 | ||
baa09f5f | 2580 | if (INTEL_INFO(dev)->gen <= 5) { |
b2f21b4d | 2581 | gtt->gtt_probe = i915_gmch_probe; |
853ba5d2 | 2582 | gtt->base.cleanup = i915_gmch_remove; |
63340133 | 2583 | } else if (INTEL_INFO(dev)->gen < 8) { |
b2f21b4d | 2584 | gtt->gtt_probe = gen6_gmch_probe; |
853ba5d2 | 2585 | gtt->base.cleanup = gen6_gmch_remove; |
4d15c145 | 2586 | if (IS_HASWELL(dev) && dev_priv->ellc_size) |
853ba5d2 | 2587 | gtt->base.pte_encode = iris_pte_encode; |
4d15c145 | 2588 | else if (IS_HASWELL(dev)) |
853ba5d2 | 2589 | gtt->base.pte_encode = hsw_pte_encode; |
b2f21b4d | 2590 | else if (IS_VALLEYVIEW(dev)) |
853ba5d2 | 2591 | gtt->base.pte_encode = byt_pte_encode; |
350ec881 CW |
2592 | else if (INTEL_INFO(dev)->gen >= 7) |
2593 | gtt->base.pte_encode = ivb_pte_encode; | |
b2f21b4d | 2594 | else |
350ec881 | 2595 | gtt->base.pte_encode = snb_pte_encode; |
63340133 BW |
2596 | } else { |
2597 | dev_priv->gtt.gtt_probe = gen8_gmch_probe; | |
2598 | dev_priv->gtt.base.cleanup = gen6_gmch_remove; | |
baa09f5f BW |
2599 | } |
2600 | ||
853ba5d2 | 2601 | ret = gtt->gtt_probe(dev, >t->base.total, >t->stolen_size, |
b2f21b4d | 2602 | >t->mappable_base, >t->mappable_end); |
a54c0c27 | 2603 | if (ret) |
baa09f5f | 2604 | return ret; |
baa09f5f | 2605 | |
853ba5d2 BW |
2606 | gtt->base.dev = dev; |
2607 | ||
baa09f5f | 2608 | /* GMADR is the PCI mmio aperture into the global GTT. */ |
853ba5d2 BW |
2609 | DRM_INFO("Memory usable by graphics device = %zdM\n", |
2610 | gtt->base.total >> 20); | |
b2f21b4d BW |
2611 | DRM_DEBUG_DRIVER("GMADR size = %ldM\n", gtt->mappable_end >> 20); |
2612 | DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt->stolen_size >> 20); | |
5db6c735 DV |
2613 | #ifdef CONFIG_INTEL_IOMMU |
2614 | if (intel_iommu_gfx_mapped) | |
2615 | DRM_INFO("VT-d active for gfx access\n"); | |
2616 | #endif | |
cfa7c862 DV |
2617 | /* |
2618 | * i915.enable_ppgtt is read-only, so do an early pass to validate the | |
2619 | * user's requested state against the hardware/driver capabilities. We | |
2620 | * do this now so that we can print out any log messages once rather | |
2621 | * than every time we check intel_enable_ppgtt(). | |
2622 | */ | |
2623 | i915.enable_ppgtt = sanitize_enable_ppgtt(dev, i915.enable_ppgtt); | |
2624 | DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915.enable_ppgtt); | |
baa09f5f BW |
2625 | |
2626 | return 0; | |
2627 | } | |
6f65e29a | 2628 | |
ec7adb6e JL |
2629 | static struct i915_vma * |
2630 | __i915_gem_vma_create(struct drm_i915_gem_object *obj, | |
2631 | struct i915_address_space *vm, | |
2632 | const struct i915_ggtt_view *ggtt_view) | |
6f65e29a | 2633 | { |
dabde5c7 | 2634 | struct i915_vma *vma; |
6f65e29a | 2635 | |
ec7adb6e JL |
2636 | if (WARN_ON(i915_is_ggtt(vm) != !!ggtt_view)) |
2637 | return ERR_PTR(-EINVAL); | |
e20d2ab7 CW |
2638 | |
2639 | vma = kmem_cache_zalloc(to_i915(obj->base.dev)->vmas, GFP_KERNEL); | |
dabde5c7 DC |
2640 | if (vma == NULL) |
2641 | return ERR_PTR(-ENOMEM); | |
ec7adb6e | 2642 | |
6f65e29a BW |
2643 | INIT_LIST_HEAD(&vma->vma_link); |
2644 | INIT_LIST_HEAD(&vma->mm_list); | |
2645 | INIT_LIST_HEAD(&vma->exec_list); | |
2646 | vma->vm = vm; | |
2647 | vma->obj = obj; | |
2648 | ||
777dc5bb | 2649 | if (i915_is_ggtt(vm)) |
ec7adb6e | 2650 | vma->ggtt_view = *ggtt_view; |
6f65e29a | 2651 | |
f7635669 TU |
2652 | list_add_tail(&vma->vma_link, &obj->vma_list); |
2653 | if (!i915_is_ggtt(vm)) | |
e07f0552 | 2654 | i915_ppgtt_get(i915_vm_to_ppgtt(vm)); |
6f65e29a BW |
2655 | |
2656 | return vma; | |
2657 | } | |
2658 | ||
2659 | struct i915_vma * | |
ec7adb6e JL |
2660 | i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj, |
2661 | struct i915_address_space *vm) | |
2662 | { | |
2663 | struct i915_vma *vma; | |
2664 | ||
2665 | vma = i915_gem_obj_to_vma(obj, vm); | |
2666 | if (!vma) | |
2667 | vma = __i915_gem_vma_create(obj, vm, | |
2668 | i915_is_ggtt(vm) ? &i915_ggtt_view_normal : NULL); | |
2669 | ||
2670 | return vma; | |
2671 | } | |
2672 | ||
2673 | struct i915_vma * | |
2674 | i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object *obj, | |
fe14d5f4 | 2675 | const struct i915_ggtt_view *view) |
6f65e29a | 2676 | { |
ec7adb6e | 2677 | struct i915_address_space *ggtt = i915_obj_to_ggtt(obj); |
6f65e29a BW |
2678 | struct i915_vma *vma; |
2679 | ||
ec7adb6e JL |
2680 | if (WARN_ON(!view)) |
2681 | return ERR_PTR(-EINVAL); | |
2682 | ||
2683 | vma = i915_gem_obj_to_ggtt_view(obj, view); | |
2684 | ||
2685 | if (IS_ERR(vma)) | |
2686 | return vma; | |
2687 | ||
6f65e29a | 2688 | if (!vma) |
ec7adb6e | 2689 | vma = __i915_gem_vma_create(obj, ggtt, view); |
6f65e29a BW |
2690 | |
2691 | return vma; | |
ec7adb6e | 2692 | |
6f65e29a | 2693 | } |
fe14d5f4 | 2694 | |
50470bb0 TU |
2695 | static void |
2696 | rotate_pages(dma_addr_t *in, unsigned int width, unsigned int height, | |
2697 | struct sg_table *st) | |
2698 | { | |
2699 | unsigned int column, row; | |
2700 | unsigned int src_idx; | |
2701 | struct scatterlist *sg = st->sgl; | |
2702 | ||
2703 | st->nents = 0; | |
2704 | ||
2705 | for (column = 0; column < width; column++) { | |
2706 | src_idx = width * (height - 1) + column; | |
2707 | for (row = 0; row < height; row++) { | |
2708 | st->nents++; | |
2709 | /* We don't need the pages, but need to initialize | |
2710 | * the entries so the sg list can be happily traversed. | |
2711 | * The only thing we need are DMA addresses. | |
2712 | */ | |
2713 | sg_set_page(sg, NULL, PAGE_SIZE, 0); | |
2714 | sg_dma_address(sg) = in[src_idx]; | |
2715 | sg_dma_len(sg) = PAGE_SIZE; | |
2716 | sg = sg_next(sg); | |
2717 | src_idx -= width; | |
2718 | } | |
2719 | } | |
2720 | } | |
2721 | ||
2722 | static struct sg_table * | |
2723 | intel_rotate_fb_obj_pages(struct i915_ggtt_view *ggtt_view, | |
2724 | struct drm_i915_gem_object *obj) | |
2725 | { | |
2726 | struct drm_device *dev = obj->base.dev; | |
2727 | struct intel_rotation_info *rot_info = &ggtt_view->rotation_info; | |
2728 | unsigned long size, pages, rot_pages; | |
2729 | struct sg_page_iter sg_iter; | |
2730 | unsigned long i; | |
2731 | dma_addr_t *page_addr_list; | |
2732 | struct sg_table *st; | |
2733 | unsigned int tile_pitch, tile_height; | |
2734 | unsigned int width_pages, height_pages; | |
1d00dad5 | 2735 | int ret = -ENOMEM; |
50470bb0 TU |
2736 | |
2737 | pages = obj->base.size / PAGE_SIZE; | |
2738 | ||
2739 | /* Calculate tiling geometry. */ | |
2740 | tile_height = intel_tile_height(dev, rot_info->pixel_format, | |
2741 | rot_info->fb_modifier); | |
2742 | tile_pitch = PAGE_SIZE / tile_height; | |
2743 | width_pages = DIV_ROUND_UP(rot_info->pitch, tile_pitch); | |
2744 | height_pages = DIV_ROUND_UP(rot_info->height, tile_height); | |
2745 | rot_pages = width_pages * height_pages; | |
2746 | size = rot_pages * PAGE_SIZE; | |
2747 | ||
2748 | /* Allocate a temporary list of source pages for random access. */ | |
2749 | page_addr_list = drm_malloc_ab(pages, sizeof(dma_addr_t)); | |
2750 | if (!page_addr_list) | |
2751 | return ERR_PTR(ret); | |
2752 | ||
2753 | /* Allocate target SG list. */ | |
2754 | st = kmalloc(sizeof(*st), GFP_KERNEL); | |
2755 | if (!st) | |
2756 | goto err_st_alloc; | |
2757 | ||
2758 | ret = sg_alloc_table(st, rot_pages, GFP_KERNEL); | |
2759 | if (ret) | |
2760 | goto err_sg_alloc; | |
2761 | ||
2762 | /* Populate source page list from the object. */ | |
2763 | i = 0; | |
2764 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) { | |
2765 | page_addr_list[i] = sg_page_iter_dma_address(&sg_iter); | |
2766 | i++; | |
2767 | } | |
2768 | ||
2769 | /* Rotate the pages. */ | |
2770 | rotate_pages(page_addr_list, width_pages, height_pages, st); | |
2771 | ||
2772 | DRM_DEBUG_KMS( | |
2773 | "Created rotated page mapping for object size %lu (pitch=%u, height=%u, pixel_format=0x%x, %ux%u tiles, %lu pages).\n", | |
2774 | size, rot_info->pitch, rot_info->height, | |
2775 | rot_info->pixel_format, width_pages, height_pages, | |
2776 | rot_pages); | |
2777 | ||
2778 | drm_free_large(page_addr_list); | |
2779 | ||
2780 | return st; | |
2781 | ||
2782 | err_sg_alloc: | |
2783 | kfree(st); | |
2784 | err_st_alloc: | |
2785 | drm_free_large(page_addr_list); | |
2786 | ||
2787 | DRM_DEBUG_KMS( | |
2788 | "Failed to create rotated mapping for object size %lu! (%d) (pitch=%u, height=%u, pixel_format=0x%x, %ux%u tiles, %lu pages)\n", | |
2789 | size, ret, rot_info->pitch, rot_info->height, | |
2790 | rot_info->pixel_format, width_pages, height_pages, | |
2791 | rot_pages); | |
2792 | return ERR_PTR(ret); | |
2793 | } | |
ec7adb6e | 2794 | |
50470bb0 TU |
2795 | static inline int |
2796 | i915_get_ggtt_vma_pages(struct i915_vma *vma) | |
fe14d5f4 | 2797 | { |
50470bb0 TU |
2798 | int ret = 0; |
2799 | ||
fe14d5f4 TU |
2800 | if (vma->ggtt_view.pages) |
2801 | return 0; | |
2802 | ||
2803 | if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) | |
2804 | vma->ggtt_view.pages = vma->obj->pages; | |
50470bb0 TU |
2805 | else if (vma->ggtt_view.type == I915_GGTT_VIEW_ROTATED) |
2806 | vma->ggtt_view.pages = | |
2807 | intel_rotate_fb_obj_pages(&vma->ggtt_view, vma->obj); | |
fe14d5f4 TU |
2808 | else |
2809 | WARN_ONCE(1, "GGTT view %u not implemented!\n", | |
2810 | vma->ggtt_view.type); | |
2811 | ||
2812 | if (!vma->ggtt_view.pages) { | |
ec7adb6e | 2813 | DRM_ERROR("Failed to get pages for GGTT view type %u!\n", |
fe14d5f4 | 2814 | vma->ggtt_view.type); |
50470bb0 TU |
2815 | ret = -EINVAL; |
2816 | } else if (IS_ERR(vma->ggtt_view.pages)) { | |
2817 | ret = PTR_ERR(vma->ggtt_view.pages); | |
2818 | vma->ggtt_view.pages = NULL; | |
2819 | DRM_ERROR("Failed to get pages for VMA view type %u (%d)!\n", | |
2820 | vma->ggtt_view.type, ret); | |
fe14d5f4 TU |
2821 | } |
2822 | ||
50470bb0 | 2823 | return ret; |
fe14d5f4 TU |
2824 | } |
2825 | ||
2826 | /** | |
2827 | * i915_vma_bind - Sets up PTEs for an VMA in it's corresponding address space. | |
2828 | * @vma: VMA to map | |
2829 | * @cache_level: mapping cache level | |
2830 | * @flags: flags like global or local mapping | |
2831 | * | |
2832 | * DMA addresses are taken from the scatter-gather table of this object (or of | |
2833 | * this VMA in case of non-default GGTT views) and PTE entries set up. | |
2834 | * Note that DMA addresses are also the only part of the SG table we care about. | |
2835 | */ | |
2836 | int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level, | |
2837 | u32 flags) | |
2838 | { | |
1d335d1b MK |
2839 | int ret; |
2840 | ||
2841 | if (vma->vm->allocate_va_range) { | |
2842 | trace_i915_va_alloc(vma->vm, vma->node.start, | |
2843 | vma->node.size, | |
2844 | VM_TO_TRACE_NAME(vma->vm)); | |
2845 | ||
2846 | ret = vma->vm->allocate_va_range(vma->vm, | |
2847 | vma->node.start, | |
2848 | vma->node.size); | |
2849 | if (ret) | |
2850 | return ret; | |
2851 | } | |
2852 | ||
ec7adb6e | 2853 | if (i915_is_ggtt(vma->vm)) { |
1d335d1b | 2854 | ret = i915_get_ggtt_vma_pages(vma); |
fe14d5f4 | 2855 | |
ec7adb6e JL |
2856 | if (ret) |
2857 | return ret; | |
2858 | } | |
fe14d5f4 | 2859 | |
777dc5bb | 2860 | vma->vm->bind_vma(vma, cache_level, flags); |
fe14d5f4 TU |
2861 | |
2862 | return 0; | |
2863 | } |