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76aaf220 DV |
1 | /* |
2 | * Copyright © 2010 Daniel Vetter | |
c4ac524c | 3 | * Copyright © 2011-2014 Intel Corporation |
76aaf220 DV |
4 | * |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
22 | * IN THE SOFTWARE. | |
23 | * | |
24 | */ | |
25 | ||
e007b19d | 26 | #include <linux/log2.h> |
0e46ce2e | 27 | #include <linux/seq_file.h> |
5bab6f60 | 28 | #include <linux/stop_machine.h> |
e007b19d | 29 | |
760285e7 DH |
30 | #include <drm/drmP.h> |
31 | #include <drm/i915_drm.h> | |
e007b19d | 32 | |
76aaf220 | 33 | #include "i915_drv.h" |
5dda8fa3 | 34 | #include "i915_vgpu.h" |
76aaf220 DV |
35 | #include "i915_trace.h" |
36 | #include "intel_drv.h" | |
d07f0e59 | 37 | #include "intel_frontbuffer.h" |
76aaf220 | 38 | |
bb8f9cff CW |
39 | #define I915_GFP_DMA (GFP_KERNEL | __GFP_HIGHMEM) |
40 | ||
45f8f69a TU |
41 | /** |
42 | * DOC: Global GTT views | |
43 | * | |
44 | * Background and previous state | |
45 | * | |
46 | * Historically objects could exists (be bound) in global GTT space only as | |
47 | * singular instances with a view representing all of the object's backing pages | |
48 | * in a linear fashion. This view will be called a normal view. | |
49 | * | |
50 | * To support multiple views of the same object, where the number of mapped | |
51 | * pages is not equal to the backing store, or where the layout of the pages | |
52 | * is not linear, concept of a GGTT view was added. | |
53 | * | |
54 | * One example of an alternative view is a stereo display driven by a single | |
55 | * image. In this case we would have a framebuffer looking like this | |
56 | * (2x2 pages): | |
57 | * | |
58 | * 12 | |
59 | * 34 | |
60 | * | |
61 | * Above would represent a normal GGTT view as normally mapped for GPU or CPU | |
62 | * rendering. In contrast, fed to the display engine would be an alternative | |
63 | * view which could look something like this: | |
64 | * | |
65 | * 1212 | |
66 | * 3434 | |
67 | * | |
68 | * In this example both the size and layout of pages in the alternative view is | |
69 | * different from the normal view. | |
70 | * | |
71 | * Implementation and usage | |
72 | * | |
73 | * GGTT views are implemented using VMAs and are distinguished via enum | |
74 | * i915_ggtt_view_type and struct i915_ggtt_view. | |
75 | * | |
76 | * A new flavour of core GEM functions which work with GGTT bound objects were | |
ec7adb6e JL |
77 | * added with the _ggtt_ infix, and sometimes with _view postfix to avoid |
78 | * renaming in large amounts of code. They take the struct i915_ggtt_view | |
79 | * parameter encapsulating all metadata required to implement a view. | |
45f8f69a TU |
80 | * |
81 | * As a helper for callers which are only interested in the normal view, | |
82 | * globally const i915_ggtt_view_normal singleton instance exists. All old core | |
83 | * GEM API functions, the ones not taking the view parameter, are operating on, | |
84 | * or with the normal GGTT view. | |
85 | * | |
86 | * Code wanting to add or use a new GGTT view needs to: | |
87 | * | |
88 | * 1. Add a new enum with a suitable name. | |
89 | * 2. Extend the metadata in the i915_ggtt_view structure if required. | |
90 | * 3. Add support to i915_get_vma_pages(). | |
91 | * | |
92 | * New views are required to build a scatter-gather table from within the | |
93 | * i915_get_vma_pages function. This table is stored in the vma.ggtt_view and | |
94 | * exists for the lifetime of an VMA. | |
95 | * | |
96 | * Core API is designed to have copy semantics which means that passed in | |
97 | * struct i915_ggtt_view does not need to be persistent (left around after | |
98 | * calling the core API functions). | |
99 | * | |
100 | */ | |
101 | ||
70b9f6f8 DV |
102 | static int |
103 | i915_get_ggtt_vma_pages(struct i915_vma *vma); | |
104 | ||
b5e16987 VS |
105 | const struct i915_ggtt_view i915_ggtt_view_normal = { |
106 | .type = I915_GGTT_VIEW_NORMAL, | |
107 | }; | |
9abc4648 | 108 | const struct i915_ggtt_view i915_ggtt_view_rotated = { |
b5e16987 | 109 | .type = I915_GGTT_VIEW_ROTATED, |
9abc4648 | 110 | }; |
fe14d5f4 | 111 | |
c033666a CW |
112 | int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv, |
113 | int enable_ppgtt) | |
cfa7c862 | 114 | { |
1893a71b CW |
115 | bool has_aliasing_ppgtt; |
116 | bool has_full_ppgtt; | |
1f9a99e0 | 117 | bool has_full_48bit_ppgtt; |
1893a71b | 118 | |
9e1d0e60 MT |
119 | has_aliasing_ppgtt = dev_priv->info.has_aliasing_ppgtt; |
120 | has_full_ppgtt = dev_priv->info.has_full_ppgtt; | |
121 | has_full_48bit_ppgtt = dev_priv->info.has_full_48bit_ppgtt; | |
1893a71b | 122 | |
e320d400 ZW |
123 | if (intel_vgpu_active(dev_priv)) { |
124 | /* emulation is too hard */ | |
125 | has_full_ppgtt = false; | |
126 | has_full_48bit_ppgtt = false; | |
127 | } | |
71ba2d64 | 128 | |
0e4ca100 CW |
129 | if (!has_aliasing_ppgtt) |
130 | return 0; | |
131 | ||
70ee45e1 DL |
132 | /* |
133 | * We don't allow disabling PPGTT for gen9+ as it's a requirement for | |
134 | * execlists, the sole mechanism available to submit work. | |
135 | */ | |
c033666a | 136 | if (enable_ppgtt == 0 && INTEL_GEN(dev_priv) < 9) |
cfa7c862 DV |
137 | return 0; |
138 | ||
139 | if (enable_ppgtt == 1) | |
140 | return 1; | |
141 | ||
1893a71b | 142 | if (enable_ppgtt == 2 && has_full_ppgtt) |
cfa7c862 DV |
143 | return 2; |
144 | ||
1f9a99e0 MT |
145 | if (enable_ppgtt == 3 && has_full_48bit_ppgtt) |
146 | return 3; | |
147 | ||
93a25a9e DV |
148 | #ifdef CONFIG_INTEL_IOMMU |
149 | /* Disable ppgtt on SNB if VT-d is on. */ | |
c033666a | 150 | if (IS_GEN6(dev_priv) && intel_iommu_gfx_mapped) { |
93a25a9e | 151 | DRM_INFO("Disabling PPGTT because VT-d is on\n"); |
cfa7c862 | 152 | return 0; |
93a25a9e DV |
153 | } |
154 | #endif | |
155 | ||
62942ed7 | 156 | /* Early VLV doesn't have this */ |
91c8a326 | 157 | if (IS_VALLEYVIEW(dev_priv) && dev_priv->drm.pdev->revision < 0xb) { |
62942ed7 JB |
158 | DRM_DEBUG_DRIVER("disabling PPGTT on pre-B3 step VLV\n"); |
159 | return 0; | |
160 | } | |
161 | ||
e320d400 | 162 | if (INTEL_GEN(dev_priv) >= 8 && i915.enable_execlists && has_full_ppgtt) |
1f9a99e0 | 163 | return has_full_48bit_ppgtt ? 3 : 2; |
2f82bbdf MT |
164 | else |
165 | return has_aliasing_ppgtt ? 1 : 0; | |
93a25a9e DV |
166 | } |
167 | ||
70b9f6f8 DV |
168 | static int ppgtt_bind_vma(struct i915_vma *vma, |
169 | enum i915_cache_level cache_level, | |
170 | u32 unused) | |
47552659 DV |
171 | { |
172 | u32 pte_flags = 0; | |
173 | ||
a4f5ea64 | 174 | vma->pages = vma->obj->mm.pages; |
247177dd | 175 | |
47552659 DV |
176 | /* Currently applicable only to VLV */ |
177 | if (vma->obj->gt_ro) | |
178 | pte_flags |= PTE_READ_ONLY; | |
179 | ||
247177dd | 180 | vma->vm->insert_entries(vma->vm, vma->pages, vma->node.start, |
47552659 | 181 | cache_level, pte_flags); |
70b9f6f8 DV |
182 | |
183 | return 0; | |
47552659 DV |
184 | } |
185 | ||
186 | static void ppgtt_unbind_vma(struct i915_vma *vma) | |
187 | { | |
188 | vma->vm->clear_range(vma->vm, | |
189 | vma->node.start, | |
4fb84d99 | 190 | vma->size); |
47552659 | 191 | } |
6f65e29a | 192 | |
2c642b07 | 193 | static gen8_pte_t gen8_pte_encode(dma_addr_t addr, |
4fb84d99 | 194 | enum i915_cache_level level) |
94ec8f61 | 195 | { |
4fb84d99 | 196 | gen8_pte_t pte = _PAGE_PRESENT | _PAGE_RW; |
94ec8f61 | 197 | pte |= addr; |
63c42e56 BW |
198 | |
199 | switch (level) { | |
200 | case I915_CACHE_NONE: | |
fbe5d36e | 201 | pte |= PPAT_UNCACHED_INDEX; |
63c42e56 BW |
202 | break; |
203 | case I915_CACHE_WT: | |
204 | pte |= PPAT_DISPLAY_ELLC_INDEX; | |
205 | break; | |
206 | default: | |
207 | pte |= PPAT_CACHED_INDEX; | |
208 | break; | |
209 | } | |
210 | ||
94ec8f61 BW |
211 | return pte; |
212 | } | |
213 | ||
fe36f55d MK |
214 | static gen8_pde_t gen8_pde_encode(const dma_addr_t addr, |
215 | const enum i915_cache_level level) | |
b1fe6673 | 216 | { |
07749ef3 | 217 | gen8_pde_t pde = _PAGE_PRESENT | _PAGE_RW; |
b1fe6673 BW |
218 | pde |= addr; |
219 | if (level != I915_CACHE_NONE) | |
220 | pde |= PPAT_CACHED_PDE_INDEX; | |
221 | else | |
222 | pde |= PPAT_UNCACHED_INDEX; | |
223 | return pde; | |
224 | } | |
225 | ||
762d9936 MT |
226 | #define gen8_pdpe_encode gen8_pde_encode |
227 | #define gen8_pml4e_encode gen8_pde_encode | |
228 | ||
07749ef3 MT |
229 | static gen6_pte_t snb_pte_encode(dma_addr_t addr, |
230 | enum i915_cache_level level, | |
4fb84d99 | 231 | u32 unused) |
54d12527 | 232 | { |
4fb84d99 | 233 | gen6_pte_t pte = GEN6_PTE_VALID; |
54d12527 | 234 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
e7210c3c BW |
235 | |
236 | switch (level) { | |
350ec881 CW |
237 | case I915_CACHE_L3_LLC: |
238 | case I915_CACHE_LLC: | |
239 | pte |= GEN6_PTE_CACHE_LLC; | |
240 | break; | |
241 | case I915_CACHE_NONE: | |
242 | pte |= GEN6_PTE_UNCACHED; | |
243 | break; | |
244 | default: | |
5f77eeb0 | 245 | MISSING_CASE(level); |
350ec881 CW |
246 | } |
247 | ||
248 | return pte; | |
249 | } | |
250 | ||
07749ef3 MT |
251 | static gen6_pte_t ivb_pte_encode(dma_addr_t addr, |
252 | enum i915_cache_level level, | |
4fb84d99 | 253 | u32 unused) |
350ec881 | 254 | { |
4fb84d99 | 255 | gen6_pte_t pte = GEN6_PTE_VALID; |
350ec881 CW |
256 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
257 | ||
258 | switch (level) { | |
259 | case I915_CACHE_L3_LLC: | |
260 | pte |= GEN7_PTE_CACHE_L3_LLC; | |
e7210c3c BW |
261 | break; |
262 | case I915_CACHE_LLC: | |
263 | pte |= GEN6_PTE_CACHE_LLC; | |
264 | break; | |
265 | case I915_CACHE_NONE: | |
9119708c | 266 | pte |= GEN6_PTE_UNCACHED; |
e7210c3c BW |
267 | break; |
268 | default: | |
5f77eeb0 | 269 | MISSING_CASE(level); |
e7210c3c BW |
270 | } |
271 | ||
54d12527 BW |
272 | return pte; |
273 | } | |
274 | ||
07749ef3 MT |
275 | static gen6_pte_t byt_pte_encode(dma_addr_t addr, |
276 | enum i915_cache_level level, | |
4fb84d99 | 277 | u32 flags) |
93c34e70 | 278 | { |
4fb84d99 | 279 | gen6_pte_t pte = GEN6_PTE_VALID; |
93c34e70 KG |
280 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
281 | ||
24f3a8cf AG |
282 | if (!(flags & PTE_READ_ONLY)) |
283 | pte |= BYT_PTE_WRITEABLE; | |
93c34e70 KG |
284 | |
285 | if (level != I915_CACHE_NONE) | |
286 | pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES; | |
287 | ||
288 | return pte; | |
289 | } | |
290 | ||
07749ef3 MT |
291 | static gen6_pte_t hsw_pte_encode(dma_addr_t addr, |
292 | enum i915_cache_level level, | |
4fb84d99 | 293 | u32 unused) |
9119708c | 294 | { |
4fb84d99 | 295 | gen6_pte_t pte = GEN6_PTE_VALID; |
0d8ff15e | 296 | pte |= HSW_PTE_ADDR_ENCODE(addr); |
9119708c KG |
297 | |
298 | if (level != I915_CACHE_NONE) | |
87a6b688 | 299 | pte |= HSW_WB_LLC_AGE3; |
9119708c KG |
300 | |
301 | return pte; | |
302 | } | |
303 | ||
07749ef3 MT |
304 | static gen6_pte_t iris_pte_encode(dma_addr_t addr, |
305 | enum i915_cache_level level, | |
4fb84d99 | 306 | u32 unused) |
4d15c145 | 307 | { |
4fb84d99 | 308 | gen6_pte_t pte = GEN6_PTE_VALID; |
4d15c145 BW |
309 | pte |= HSW_PTE_ADDR_ENCODE(addr); |
310 | ||
651d794f CW |
311 | switch (level) { |
312 | case I915_CACHE_NONE: | |
313 | break; | |
314 | case I915_CACHE_WT: | |
c51e9701 | 315 | pte |= HSW_WT_ELLC_LLC_AGE3; |
651d794f CW |
316 | break; |
317 | default: | |
c51e9701 | 318 | pte |= HSW_WB_ELLC_LLC_AGE3; |
651d794f CW |
319 | break; |
320 | } | |
4d15c145 BW |
321 | |
322 | return pte; | |
323 | } | |
324 | ||
275a991c | 325 | static int __setup_page_dma(struct drm_i915_private *dev_priv, |
c114f76a | 326 | struct i915_page_dma *p, gfp_t flags) |
678d96fb | 327 | { |
275a991c | 328 | struct device *kdev = &dev_priv->drm.pdev->dev; |
678d96fb | 329 | |
c114f76a | 330 | p->page = alloc_page(flags); |
44159ddb MK |
331 | if (!p->page) |
332 | return -ENOMEM; | |
678d96fb | 333 | |
c49d13ee | 334 | p->daddr = dma_map_page(kdev, |
f51455d4 | 335 | p->page, 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); |
678d96fb | 336 | |
c49d13ee | 337 | if (dma_mapping_error(kdev, p->daddr)) { |
44159ddb MK |
338 | __free_page(p->page); |
339 | return -EINVAL; | |
340 | } | |
1266cdb1 MT |
341 | |
342 | return 0; | |
678d96fb BW |
343 | } |
344 | ||
275a991c TU |
345 | static int setup_page_dma(struct drm_i915_private *dev_priv, |
346 | struct i915_page_dma *p) | |
c114f76a | 347 | { |
275a991c | 348 | return __setup_page_dma(dev_priv, p, I915_GFP_DMA); |
c114f76a MK |
349 | } |
350 | ||
275a991c TU |
351 | static void cleanup_page_dma(struct drm_i915_private *dev_priv, |
352 | struct i915_page_dma *p) | |
06fda602 | 353 | { |
275a991c | 354 | struct pci_dev *pdev = dev_priv->drm.pdev; |
52a05c30 | 355 | |
44159ddb | 356 | if (WARN_ON(!p->page)) |
06fda602 | 357 | return; |
678d96fb | 358 | |
f51455d4 | 359 | dma_unmap_page(&pdev->dev, p->daddr, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); |
44159ddb MK |
360 | __free_page(p->page); |
361 | memset(p, 0, sizeof(*p)); | |
362 | } | |
363 | ||
d1c54acd | 364 | static void *kmap_page_dma(struct i915_page_dma *p) |
73eeea53 | 365 | { |
d1c54acd MK |
366 | return kmap_atomic(p->page); |
367 | } | |
73eeea53 | 368 | |
d1c54acd MK |
369 | /* We use the flushing unmap only with ppgtt structures: |
370 | * page directories, page tables and scratch pages. | |
371 | */ | |
e2d214ae | 372 | static void kunmap_page_dma(struct drm_i915_private *dev_priv, void *vaddr) |
d1c54acd | 373 | { |
73eeea53 MK |
374 | /* There are only few exceptions for gen >=6. chv and bxt. |
375 | * And we are not sure about the latter so play safe for now. | |
376 | */ | |
cc3f90f0 | 377 | if (IS_CHERRYVIEW(dev_priv) || IS_GEN9_LP(dev_priv)) |
73eeea53 MK |
378 | drm_clflush_virt_range(vaddr, PAGE_SIZE); |
379 | ||
380 | kunmap_atomic(vaddr); | |
381 | } | |
382 | ||
567047be | 383 | #define kmap_px(px) kmap_page_dma(px_base(px)) |
e2d214ae | 384 | #define kunmap_px(ppgtt, vaddr) \ |
49d73912 | 385 | kunmap_page_dma((ppgtt)->base.i915, (vaddr)) |
d1c54acd | 386 | |
275a991c TU |
387 | #define setup_px(dev_priv, px) setup_page_dma((dev_priv), px_base(px)) |
388 | #define cleanup_px(dev_priv, px) cleanup_page_dma((dev_priv), px_base(px)) | |
e2d214ae TU |
389 | #define fill_px(dev_priv, px, v) fill_page_dma((dev_priv), px_base(px), (v)) |
390 | #define fill32_px(dev_priv, px, v) \ | |
391 | fill_page_dma_32((dev_priv), px_base(px), (v)) | |
567047be | 392 | |
e2d214ae TU |
393 | static void fill_page_dma(struct drm_i915_private *dev_priv, |
394 | struct i915_page_dma *p, const uint64_t val) | |
d1c54acd MK |
395 | { |
396 | int i; | |
397 | uint64_t * const vaddr = kmap_page_dma(p); | |
398 | ||
399 | for (i = 0; i < 512; i++) | |
400 | vaddr[i] = val; | |
401 | ||
e2d214ae | 402 | kunmap_page_dma(dev_priv, vaddr); |
d1c54acd MK |
403 | } |
404 | ||
e2d214ae TU |
405 | static void fill_page_dma_32(struct drm_i915_private *dev_priv, |
406 | struct i915_page_dma *p, const uint32_t val32) | |
73eeea53 MK |
407 | { |
408 | uint64_t v = val32; | |
409 | ||
410 | v = v << 32 | val32; | |
411 | ||
e2d214ae | 412 | fill_page_dma(dev_priv, p, v); |
73eeea53 MK |
413 | } |
414 | ||
8bcdd0f7 | 415 | static int |
275a991c | 416 | setup_scratch_page(struct drm_i915_private *dev_priv, |
bb8f9cff CW |
417 | struct i915_page_dma *scratch, |
418 | gfp_t gfp) | |
4ad2af1e | 419 | { |
275a991c | 420 | return __setup_page_dma(dev_priv, scratch, gfp | __GFP_ZERO); |
4ad2af1e MK |
421 | } |
422 | ||
275a991c | 423 | static void cleanup_scratch_page(struct drm_i915_private *dev_priv, |
8bcdd0f7 | 424 | struct i915_page_dma *scratch) |
4ad2af1e | 425 | { |
275a991c | 426 | cleanup_page_dma(dev_priv, scratch); |
4ad2af1e MK |
427 | } |
428 | ||
275a991c | 429 | static struct i915_page_table *alloc_pt(struct drm_i915_private *dev_priv) |
06fda602 | 430 | { |
ec565b3c | 431 | struct i915_page_table *pt; |
275a991c | 432 | const size_t count = INTEL_GEN(dev_priv) >= 8 ? GEN8_PTES : GEN6_PTES; |
678d96fb | 433 | int ret = -ENOMEM; |
06fda602 BW |
434 | |
435 | pt = kzalloc(sizeof(*pt), GFP_KERNEL); | |
436 | if (!pt) | |
437 | return ERR_PTR(-ENOMEM); | |
438 | ||
678d96fb BW |
439 | pt->used_ptes = kcalloc(BITS_TO_LONGS(count), sizeof(*pt->used_ptes), |
440 | GFP_KERNEL); | |
441 | ||
442 | if (!pt->used_ptes) | |
443 | goto fail_bitmap; | |
444 | ||
275a991c | 445 | ret = setup_px(dev_priv, pt); |
678d96fb | 446 | if (ret) |
44159ddb | 447 | goto fail_page_m; |
06fda602 BW |
448 | |
449 | return pt; | |
678d96fb | 450 | |
44159ddb | 451 | fail_page_m: |
678d96fb BW |
452 | kfree(pt->used_ptes); |
453 | fail_bitmap: | |
454 | kfree(pt); | |
455 | ||
456 | return ERR_PTR(ret); | |
06fda602 BW |
457 | } |
458 | ||
275a991c TU |
459 | static void free_pt(struct drm_i915_private *dev_priv, |
460 | struct i915_page_table *pt) | |
06fda602 | 461 | { |
275a991c | 462 | cleanup_px(dev_priv, pt); |
2e906bea MK |
463 | kfree(pt->used_ptes); |
464 | kfree(pt); | |
465 | } | |
466 | ||
467 | static void gen8_initialize_pt(struct i915_address_space *vm, | |
468 | struct i915_page_table *pt) | |
469 | { | |
470 | gen8_pte_t scratch_pte; | |
471 | ||
8bcdd0f7 | 472 | scratch_pte = gen8_pte_encode(vm->scratch_page.daddr, |
4fb84d99 | 473 | I915_CACHE_LLC); |
2e906bea | 474 | |
49d73912 | 475 | fill_px(vm->i915, pt, scratch_pte); |
2e906bea MK |
476 | } |
477 | ||
478 | static void gen6_initialize_pt(struct i915_address_space *vm, | |
479 | struct i915_page_table *pt) | |
480 | { | |
481 | gen6_pte_t scratch_pte; | |
482 | ||
8bcdd0f7 | 483 | WARN_ON(vm->scratch_page.daddr == 0); |
2e906bea | 484 | |
8bcdd0f7 | 485 | scratch_pte = vm->pte_encode(vm->scratch_page.daddr, |
4fb84d99 | 486 | I915_CACHE_LLC, 0); |
2e906bea | 487 | |
49d73912 | 488 | fill32_px(vm->i915, pt, scratch_pte); |
06fda602 BW |
489 | } |
490 | ||
275a991c | 491 | static struct i915_page_directory *alloc_pd(struct drm_i915_private *dev_priv) |
06fda602 | 492 | { |
ec565b3c | 493 | struct i915_page_directory *pd; |
33c8819f | 494 | int ret = -ENOMEM; |
06fda602 BW |
495 | |
496 | pd = kzalloc(sizeof(*pd), GFP_KERNEL); | |
497 | if (!pd) | |
498 | return ERR_PTR(-ENOMEM); | |
499 | ||
33c8819f MT |
500 | pd->used_pdes = kcalloc(BITS_TO_LONGS(I915_PDES), |
501 | sizeof(*pd->used_pdes), GFP_KERNEL); | |
502 | if (!pd->used_pdes) | |
a08e111a | 503 | goto fail_bitmap; |
33c8819f | 504 | |
275a991c | 505 | ret = setup_px(dev_priv, pd); |
33c8819f | 506 | if (ret) |
a08e111a | 507 | goto fail_page_m; |
e5815a2e | 508 | |
06fda602 | 509 | return pd; |
33c8819f | 510 | |
a08e111a | 511 | fail_page_m: |
33c8819f | 512 | kfree(pd->used_pdes); |
a08e111a | 513 | fail_bitmap: |
33c8819f MT |
514 | kfree(pd); |
515 | ||
516 | return ERR_PTR(ret); | |
06fda602 BW |
517 | } |
518 | ||
275a991c TU |
519 | static void free_pd(struct drm_i915_private *dev_priv, |
520 | struct i915_page_directory *pd) | |
2e906bea MK |
521 | { |
522 | if (px_page(pd)) { | |
275a991c | 523 | cleanup_px(dev_priv, pd); |
2e906bea MK |
524 | kfree(pd->used_pdes); |
525 | kfree(pd); | |
526 | } | |
527 | } | |
528 | ||
529 | static void gen8_initialize_pd(struct i915_address_space *vm, | |
530 | struct i915_page_directory *pd) | |
531 | { | |
532 | gen8_pde_t scratch_pde; | |
533 | ||
534 | scratch_pde = gen8_pde_encode(px_dma(vm->scratch_pt), I915_CACHE_LLC); | |
535 | ||
49d73912 | 536 | fill_px(vm->i915, pd, scratch_pde); |
2e906bea MK |
537 | } |
538 | ||
275a991c | 539 | static int __pdp_init(struct drm_i915_private *dev_priv, |
6ac18502 MT |
540 | struct i915_page_directory_pointer *pdp) |
541 | { | |
275a991c | 542 | size_t pdpes = I915_PDPES_PER_PDP(dev_priv); |
6ac18502 MT |
543 | |
544 | pdp->used_pdpes = kcalloc(BITS_TO_LONGS(pdpes), | |
545 | sizeof(unsigned long), | |
546 | GFP_KERNEL); | |
547 | if (!pdp->used_pdpes) | |
548 | return -ENOMEM; | |
549 | ||
550 | pdp->page_directory = kcalloc(pdpes, sizeof(*pdp->page_directory), | |
551 | GFP_KERNEL); | |
552 | if (!pdp->page_directory) { | |
553 | kfree(pdp->used_pdpes); | |
554 | /* the PDP might be the statically allocated top level. Keep it | |
555 | * as clean as possible */ | |
556 | pdp->used_pdpes = NULL; | |
557 | return -ENOMEM; | |
558 | } | |
559 | ||
560 | return 0; | |
561 | } | |
562 | ||
563 | static void __pdp_fini(struct i915_page_directory_pointer *pdp) | |
564 | { | |
565 | kfree(pdp->used_pdpes); | |
566 | kfree(pdp->page_directory); | |
567 | pdp->page_directory = NULL; | |
568 | } | |
569 | ||
762d9936 | 570 | static struct |
275a991c | 571 | i915_page_directory_pointer *alloc_pdp(struct drm_i915_private *dev_priv) |
762d9936 MT |
572 | { |
573 | struct i915_page_directory_pointer *pdp; | |
574 | int ret = -ENOMEM; | |
575 | ||
275a991c | 576 | WARN_ON(!USES_FULL_48BIT_PPGTT(dev_priv)); |
762d9936 MT |
577 | |
578 | pdp = kzalloc(sizeof(*pdp), GFP_KERNEL); | |
579 | if (!pdp) | |
580 | return ERR_PTR(-ENOMEM); | |
581 | ||
275a991c | 582 | ret = __pdp_init(dev_priv, pdp); |
762d9936 MT |
583 | if (ret) |
584 | goto fail_bitmap; | |
585 | ||
275a991c | 586 | ret = setup_px(dev_priv, pdp); |
762d9936 MT |
587 | if (ret) |
588 | goto fail_page_m; | |
589 | ||
590 | return pdp; | |
591 | ||
592 | fail_page_m: | |
593 | __pdp_fini(pdp); | |
594 | fail_bitmap: | |
595 | kfree(pdp); | |
596 | ||
597 | return ERR_PTR(ret); | |
598 | } | |
599 | ||
275a991c | 600 | static void free_pdp(struct drm_i915_private *dev_priv, |
6ac18502 MT |
601 | struct i915_page_directory_pointer *pdp) |
602 | { | |
603 | __pdp_fini(pdp); | |
275a991c TU |
604 | if (USES_FULL_48BIT_PPGTT(dev_priv)) { |
605 | cleanup_px(dev_priv, pdp); | |
762d9936 MT |
606 | kfree(pdp); |
607 | } | |
608 | } | |
609 | ||
69ab76fd MT |
610 | static void gen8_initialize_pdp(struct i915_address_space *vm, |
611 | struct i915_page_directory_pointer *pdp) | |
612 | { | |
613 | gen8_ppgtt_pdpe_t scratch_pdpe; | |
614 | ||
615 | scratch_pdpe = gen8_pdpe_encode(px_dma(vm->scratch_pd), I915_CACHE_LLC); | |
616 | ||
49d73912 | 617 | fill_px(vm->i915, pdp, scratch_pdpe); |
69ab76fd MT |
618 | } |
619 | ||
620 | static void gen8_initialize_pml4(struct i915_address_space *vm, | |
621 | struct i915_pml4 *pml4) | |
622 | { | |
623 | gen8_ppgtt_pml4e_t scratch_pml4e; | |
624 | ||
625 | scratch_pml4e = gen8_pml4e_encode(px_dma(vm->scratch_pdp), | |
626 | I915_CACHE_LLC); | |
627 | ||
49d73912 | 628 | fill_px(vm->i915, pml4, scratch_pml4e); |
69ab76fd MT |
629 | } |
630 | ||
762d9936 | 631 | static void |
5c693b2b MA |
632 | gen8_setup_pdpe(struct i915_hw_ppgtt *ppgtt, |
633 | struct i915_page_directory_pointer *pdp, | |
634 | struct i915_page_directory *pd, | |
635 | int index) | |
762d9936 MT |
636 | { |
637 | gen8_ppgtt_pdpe_t *page_directorypo; | |
638 | ||
275a991c | 639 | if (!USES_FULL_48BIT_PPGTT(to_i915(ppgtt->base.dev))) |
762d9936 MT |
640 | return; |
641 | ||
642 | page_directorypo = kmap_px(pdp); | |
643 | page_directorypo[index] = gen8_pdpe_encode(px_dma(pd), I915_CACHE_LLC); | |
644 | kunmap_px(ppgtt, page_directorypo); | |
645 | } | |
646 | ||
647 | static void | |
56843107 MA |
648 | gen8_setup_pml4e(struct i915_hw_ppgtt *ppgtt, |
649 | struct i915_pml4 *pml4, | |
650 | struct i915_page_directory_pointer *pdp, | |
651 | int index) | |
762d9936 MT |
652 | { |
653 | gen8_ppgtt_pml4e_t *pagemap = kmap_px(pml4); | |
654 | ||
275a991c | 655 | WARN_ON(!USES_FULL_48BIT_PPGTT(to_i915(ppgtt->base.dev))); |
762d9936 MT |
656 | pagemap[index] = gen8_pml4e_encode(px_dma(pdp), I915_CACHE_LLC); |
657 | kunmap_px(ppgtt, pagemap); | |
6ac18502 MT |
658 | } |
659 | ||
94e409c1 | 660 | /* Broadwell Page Directory Pointer Descriptors */ |
e85b26dc | 661 | static int gen8_write_pdp(struct drm_i915_gem_request *req, |
7cb6d7ac MT |
662 | unsigned entry, |
663 | dma_addr_t addr) | |
94e409c1 | 664 | { |
7e37f889 | 665 | struct intel_ring *ring = req->ring; |
4a570db5 | 666 | struct intel_engine_cs *engine = req->engine; |
94e409c1 BW |
667 | int ret; |
668 | ||
669 | BUG_ON(entry >= 4); | |
670 | ||
5fb9de1a | 671 | ret = intel_ring_begin(req, 6); |
94e409c1 BW |
672 | if (ret) |
673 | return ret; | |
674 | ||
b5321f30 CW |
675 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); |
676 | intel_ring_emit_reg(ring, GEN8_RING_PDP_UDW(engine, entry)); | |
677 | intel_ring_emit(ring, upper_32_bits(addr)); | |
678 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
679 | intel_ring_emit_reg(ring, GEN8_RING_PDP_LDW(engine, entry)); | |
680 | intel_ring_emit(ring, lower_32_bits(addr)); | |
681 | intel_ring_advance(ring); | |
94e409c1 BW |
682 | |
683 | return 0; | |
684 | } | |
685 | ||
2dba3239 MT |
686 | static int gen8_legacy_mm_switch(struct i915_hw_ppgtt *ppgtt, |
687 | struct drm_i915_gem_request *req) | |
94e409c1 | 688 | { |
eeb9488e | 689 | int i, ret; |
94e409c1 | 690 | |
7cb6d7ac | 691 | for (i = GEN8_LEGACY_PDPES - 1; i >= 0; i--) { |
d852c7bf MK |
692 | const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i); |
693 | ||
e85b26dc | 694 | ret = gen8_write_pdp(req, i, pd_daddr); |
eeb9488e BW |
695 | if (ret) |
696 | return ret; | |
94e409c1 | 697 | } |
d595bd4b | 698 | |
eeb9488e | 699 | return 0; |
94e409c1 BW |
700 | } |
701 | ||
2dba3239 MT |
702 | static int gen8_48b_mm_switch(struct i915_hw_ppgtt *ppgtt, |
703 | struct drm_i915_gem_request *req) | |
704 | { | |
705 | return gen8_write_pdp(req, 0, px_dma(&ppgtt->pml4)); | |
706 | } | |
707 | ||
fce93755 MK |
708 | /* PDE TLBs are a pain to invalidate on GEN8+. When we modify |
709 | * the page table structures, we mark them dirty so that | |
710 | * context switching/execlist queuing code takes extra steps | |
711 | * to ensure that tlbs are flushed. | |
712 | */ | |
713 | static void mark_tlbs_dirty(struct i915_hw_ppgtt *ppgtt) | |
714 | { | |
49d73912 | 715 | ppgtt->pd_dirty_rings = INTEL_INFO(ppgtt->base.i915)->ring_mask; |
fce93755 MK |
716 | } |
717 | ||
2ce5179f MW |
718 | /* Removes entries from a single page table, releasing it if it's empty. |
719 | * Caller can use the return value to update higher-level entries. | |
720 | */ | |
721 | static bool gen8_ppgtt_clear_pt(struct i915_address_space *vm, | |
d209b9c3 MW |
722 | struct i915_page_table *pt, |
723 | uint64_t start, | |
724 | uint64_t length) | |
459108b8 | 725 | { |
e5716f55 | 726 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
d209b9c3 | 727 | unsigned int num_entries = gen8_pte_count(start, length); |
37c63934 MK |
728 | unsigned int pte = gen8_pte_index(start); |
729 | unsigned int pte_end = pte + num_entries; | |
f9b5b782 | 730 | gen8_pte_t *pt_vaddr; |
d209b9c3 MW |
731 | gen8_pte_t scratch_pte = gen8_pte_encode(vm->scratch_page.daddr, |
732 | I915_CACHE_LLC); | |
459108b8 | 733 | |
d209b9c3 | 734 | if (WARN_ON(!px_page(pt))) |
2ce5179f | 735 | return false; |
459108b8 | 736 | |
37c63934 MK |
737 | GEM_BUG_ON(pte_end > GEN8_PTES); |
738 | ||
739 | bitmap_clear(pt->used_ptes, pte, num_entries); | |
06fda602 | 740 | |
a18dbba8 | 741 | if (bitmap_empty(pt->used_ptes, GEN8_PTES)) |
2ce5179f | 742 | return true; |
2ce5179f | 743 | |
d209b9c3 MW |
744 | pt_vaddr = kmap_px(pt); |
745 | ||
37c63934 MK |
746 | while (pte < pte_end) |
747 | pt_vaddr[pte++] = scratch_pte; | |
06fda602 | 748 | |
d209b9c3 | 749 | kunmap_px(ppgtt, pt_vaddr); |
2ce5179f MW |
750 | |
751 | return false; | |
d209b9c3 | 752 | } |
06fda602 | 753 | |
2ce5179f MW |
754 | /* Removes entries from a single page dir, releasing it if it's empty. |
755 | * Caller can use the return value to update higher-level entries | |
756 | */ | |
757 | static bool gen8_ppgtt_clear_pd(struct i915_address_space *vm, | |
d209b9c3 MW |
758 | struct i915_page_directory *pd, |
759 | uint64_t start, | |
760 | uint64_t length) | |
761 | { | |
2ce5179f | 762 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
d209b9c3 MW |
763 | struct i915_page_table *pt; |
764 | uint64_t pde; | |
2ce5179f MW |
765 | gen8_pde_t *pde_vaddr; |
766 | gen8_pde_t scratch_pde = gen8_pde_encode(px_dma(vm->scratch_pt), | |
767 | I915_CACHE_LLC); | |
d209b9c3 MW |
768 | |
769 | gen8_for_each_pde(pt, pd, start, length, pde) { | |
06fda602 | 770 | if (WARN_ON(!pd->page_table[pde])) |
00245266 | 771 | break; |
06fda602 | 772 | |
2ce5179f MW |
773 | if (gen8_ppgtt_clear_pt(vm, pt, start, length)) { |
774 | __clear_bit(pde, pd->used_pdes); | |
775 | pde_vaddr = kmap_px(pd); | |
776 | pde_vaddr[pde] = scratch_pde; | |
777 | kunmap_px(ppgtt, pde_vaddr); | |
49d73912 | 778 | free_pt(vm->i915, pt); |
2ce5179f MW |
779 | } |
780 | } | |
781 | ||
a18dbba8 | 782 | if (bitmap_empty(pd->used_pdes, I915_PDES)) |
2ce5179f | 783 | return true; |
2ce5179f MW |
784 | |
785 | return false; | |
d209b9c3 | 786 | } |
06fda602 | 787 | |
2ce5179f MW |
788 | /* Removes entries from a single page dir pointer, releasing it if it's empty. |
789 | * Caller can use the return value to update higher-level entries | |
790 | */ | |
791 | static bool gen8_ppgtt_clear_pdp(struct i915_address_space *vm, | |
d209b9c3 MW |
792 | struct i915_page_directory_pointer *pdp, |
793 | uint64_t start, | |
794 | uint64_t length) | |
795 | { | |
2ce5179f | 796 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
d209b9c3 MW |
797 | struct i915_page_directory *pd; |
798 | uint64_t pdpe; | |
06fda602 | 799 | |
d209b9c3 MW |
800 | gen8_for_each_pdpe(pd, pdp, start, length, pdpe) { |
801 | if (WARN_ON(!pdp->page_directory[pdpe])) | |
802 | break; | |
459108b8 | 803 | |
2ce5179f MW |
804 | if (gen8_ppgtt_clear_pd(vm, pd, start, length)) { |
805 | __clear_bit(pdpe, pdp->used_pdpes); | |
9e65a378 | 806 | gen8_setup_pdpe(ppgtt, pdp, vm->scratch_pd, pdpe); |
49d73912 | 807 | free_pd(vm->i915, pd); |
2ce5179f MW |
808 | } |
809 | } | |
810 | ||
fce93755 MK |
811 | mark_tlbs_dirty(ppgtt); |
812 | ||
a18dbba8 | 813 | if (bitmap_empty(pdp->used_pdpes, I915_PDPES_PER_PDP(dev_priv))) |
2ce5179f | 814 | return true; |
2ce5179f MW |
815 | |
816 | return false; | |
d209b9c3 | 817 | } |
459108b8 | 818 | |
2ce5179f MW |
819 | /* Removes entries from a single pml4. |
820 | * This is the top-level structure in 4-level page tables used on gen8+. | |
821 | * Empty entries are always scratch pml4e. | |
822 | */ | |
d209b9c3 MW |
823 | static void gen8_ppgtt_clear_pml4(struct i915_address_space *vm, |
824 | struct i915_pml4 *pml4, | |
825 | uint64_t start, | |
826 | uint64_t length) | |
827 | { | |
2ce5179f | 828 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
d209b9c3 MW |
829 | struct i915_page_directory_pointer *pdp; |
830 | uint64_t pml4e; | |
2ce5179f | 831 | |
49d73912 | 832 | GEM_BUG_ON(!USES_FULL_48BIT_PPGTT(vm->i915)); |
459108b8 | 833 | |
d209b9c3 MW |
834 | gen8_for_each_pml4e(pdp, pml4, start, length, pml4e) { |
835 | if (WARN_ON(!pml4->pdps[pml4e])) | |
836 | break; | |
459108b8 | 837 | |
2ce5179f MW |
838 | if (gen8_ppgtt_clear_pdp(vm, pdp, start, length)) { |
839 | __clear_bit(pml4e, pml4->used_pml4es); | |
9e65a378 | 840 | gen8_setup_pml4e(ppgtt, pml4, vm->scratch_pdp, pml4e); |
49d73912 | 841 | free_pdp(vm->i915, pdp); |
2ce5179f | 842 | } |
459108b8 BW |
843 | } |
844 | } | |
845 | ||
f9b5b782 | 846 | static void gen8_ppgtt_clear_range(struct i915_address_space *vm, |
4fb84d99 | 847 | uint64_t start, uint64_t length) |
9df15b49 | 848 | { |
e5716f55 | 849 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
f9b5b782 | 850 | |
c6385c94 | 851 | if (USES_FULL_48BIT_PPGTT(vm->i915)) |
d209b9c3 MW |
852 | gen8_ppgtt_clear_pml4(vm, &ppgtt->pml4, start, length); |
853 | else | |
854 | gen8_ppgtt_clear_pdp(vm, &ppgtt->pdp, start, length); | |
f9b5b782 MT |
855 | } |
856 | ||
857 | static void | |
858 | gen8_ppgtt_insert_pte_entries(struct i915_address_space *vm, | |
859 | struct i915_page_directory_pointer *pdp, | |
3387d433 | 860 | struct sg_page_iter *sg_iter, |
f9b5b782 MT |
861 | uint64_t start, |
862 | enum i915_cache_level cache_level) | |
863 | { | |
e5716f55 | 864 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
07749ef3 | 865 | gen8_pte_t *pt_vaddr; |
de5ba8eb MT |
866 | unsigned pdpe = gen8_pdpe_index(start); |
867 | unsigned pde = gen8_pde_index(start); | |
868 | unsigned pte = gen8_pte_index(start); | |
9df15b49 | 869 | |
6f1cc993 | 870 | pt_vaddr = NULL; |
7ad47cf2 | 871 | |
3387d433 | 872 | while (__sg_page_iter_next(sg_iter)) { |
d7b3de91 | 873 | if (pt_vaddr == NULL) { |
d4ec9da0 | 874 | struct i915_page_directory *pd = pdp->page_directory[pdpe]; |
ec565b3c | 875 | struct i915_page_table *pt = pd->page_table[pde]; |
d1c54acd | 876 | pt_vaddr = kmap_px(pt); |
d7b3de91 | 877 | } |
9df15b49 | 878 | |
7ad47cf2 | 879 | pt_vaddr[pte] = |
3387d433 | 880 | gen8_pte_encode(sg_page_iter_dma_address(sg_iter), |
4fb84d99 | 881 | cache_level); |
07749ef3 | 882 | if (++pte == GEN8_PTES) { |
d1c54acd | 883 | kunmap_px(ppgtt, pt_vaddr); |
6f1cc993 | 884 | pt_vaddr = NULL; |
07749ef3 | 885 | if (++pde == I915_PDES) { |
c6385c94 | 886 | if (++pdpe == I915_PDPES_PER_PDP(vm->i915)) |
de5ba8eb | 887 | break; |
7ad47cf2 BW |
888 | pde = 0; |
889 | } | |
890 | pte = 0; | |
9df15b49 BW |
891 | } |
892 | } | |
d1c54acd MK |
893 | |
894 | if (pt_vaddr) | |
895 | kunmap_px(ppgtt, pt_vaddr); | |
9df15b49 BW |
896 | } |
897 | ||
f9b5b782 MT |
898 | static void gen8_ppgtt_insert_entries(struct i915_address_space *vm, |
899 | struct sg_table *pages, | |
900 | uint64_t start, | |
901 | enum i915_cache_level cache_level, | |
902 | u32 unused) | |
903 | { | |
e5716f55 | 904 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
3387d433 | 905 | struct sg_page_iter sg_iter; |
f9b5b782 | 906 | |
3387d433 | 907 | __sg_page_iter_start(&sg_iter, pages->sgl, sg_nents(pages->sgl), 0); |
de5ba8eb | 908 | |
c6385c94 | 909 | if (!USES_FULL_48BIT_PPGTT(vm->i915)) { |
de5ba8eb MT |
910 | gen8_ppgtt_insert_pte_entries(vm, &ppgtt->pdp, &sg_iter, start, |
911 | cache_level); | |
912 | } else { | |
913 | struct i915_page_directory_pointer *pdp; | |
e8ebd8e2 | 914 | uint64_t pml4e; |
de5ba8eb MT |
915 | uint64_t length = (uint64_t)pages->orig_nents << PAGE_SHIFT; |
916 | ||
e8ebd8e2 | 917 | gen8_for_each_pml4e(pdp, &ppgtt->pml4, start, length, pml4e) { |
de5ba8eb MT |
918 | gen8_ppgtt_insert_pte_entries(vm, pdp, &sg_iter, |
919 | start, cache_level); | |
920 | } | |
921 | } | |
f9b5b782 MT |
922 | } |
923 | ||
275a991c | 924 | static void gen8_free_page_tables(struct drm_i915_private *dev_priv, |
f37c0505 | 925 | struct i915_page_directory *pd) |
7ad47cf2 BW |
926 | { |
927 | int i; | |
928 | ||
567047be | 929 | if (!px_page(pd)) |
7ad47cf2 BW |
930 | return; |
931 | ||
33c8819f | 932 | for_each_set_bit(i, pd->used_pdes, I915_PDES) { |
06fda602 BW |
933 | if (WARN_ON(!pd->page_table[i])) |
934 | continue; | |
7ad47cf2 | 935 | |
275a991c | 936 | free_pt(dev_priv, pd->page_table[i]); |
06fda602 BW |
937 | pd->page_table[i] = NULL; |
938 | } | |
d7b3de91 BW |
939 | } |
940 | ||
8776f02b MK |
941 | static int gen8_init_scratch(struct i915_address_space *vm) |
942 | { | |
49d73912 | 943 | struct drm_i915_private *dev_priv = vm->i915; |
64c050db | 944 | int ret; |
8776f02b | 945 | |
275a991c | 946 | ret = setup_scratch_page(dev_priv, &vm->scratch_page, I915_GFP_DMA); |
8bcdd0f7 CW |
947 | if (ret) |
948 | return ret; | |
8776f02b | 949 | |
275a991c | 950 | vm->scratch_pt = alloc_pt(dev_priv); |
8776f02b | 951 | if (IS_ERR(vm->scratch_pt)) { |
64c050db MA |
952 | ret = PTR_ERR(vm->scratch_pt); |
953 | goto free_scratch_page; | |
8776f02b MK |
954 | } |
955 | ||
275a991c | 956 | vm->scratch_pd = alloc_pd(dev_priv); |
8776f02b | 957 | if (IS_ERR(vm->scratch_pd)) { |
64c050db MA |
958 | ret = PTR_ERR(vm->scratch_pd); |
959 | goto free_pt; | |
8776f02b MK |
960 | } |
961 | ||
275a991c TU |
962 | if (USES_FULL_48BIT_PPGTT(dev_priv)) { |
963 | vm->scratch_pdp = alloc_pdp(dev_priv); | |
69ab76fd | 964 | if (IS_ERR(vm->scratch_pdp)) { |
64c050db MA |
965 | ret = PTR_ERR(vm->scratch_pdp); |
966 | goto free_pd; | |
69ab76fd MT |
967 | } |
968 | } | |
969 | ||
8776f02b MK |
970 | gen8_initialize_pt(vm, vm->scratch_pt); |
971 | gen8_initialize_pd(vm, vm->scratch_pd); | |
275a991c | 972 | if (USES_FULL_48BIT_PPGTT(dev_priv)) |
69ab76fd | 973 | gen8_initialize_pdp(vm, vm->scratch_pdp); |
8776f02b MK |
974 | |
975 | return 0; | |
64c050db MA |
976 | |
977 | free_pd: | |
275a991c | 978 | free_pd(dev_priv, vm->scratch_pd); |
64c050db | 979 | free_pt: |
275a991c | 980 | free_pt(dev_priv, vm->scratch_pt); |
64c050db | 981 | free_scratch_page: |
275a991c | 982 | cleanup_scratch_page(dev_priv, &vm->scratch_page); |
64c050db MA |
983 | |
984 | return ret; | |
8776f02b MK |
985 | } |
986 | ||
650da34c ZL |
987 | static int gen8_ppgtt_notify_vgt(struct i915_hw_ppgtt *ppgtt, bool create) |
988 | { | |
989 | enum vgt_g2v_type msg; | |
49d73912 | 990 | struct drm_i915_private *dev_priv = ppgtt->base.i915; |
650da34c ZL |
991 | int i; |
992 | ||
df28564d | 993 | if (USES_FULL_48BIT_PPGTT(dev_priv)) { |
650da34c ZL |
994 | u64 daddr = px_dma(&ppgtt->pml4); |
995 | ||
ab75bb5d VS |
996 | I915_WRITE(vgtif_reg(pdp[0].lo), lower_32_bits(daddr)); |
997 | I915_WRITE(vgtif_reg(pdp[0].hi), upper_32_bits(daddr)); | |
650da34c ZL |
998 | |
999 | msg = (create ? VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE : | |
1000 | VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY); | |
1001 | } else { | |
1002 | for (i = 0; i < GEN8_LEGACY_PDPES; i++) { | |
1003 | u64 daddr = i915_page_dir_dma_addr(ppgtt, i); | |
1004 | ||
ab75bb5d VS |
1005 | I915_WRITE(vgtif_reg(pdp[i].lo), lower_32_bits(daddr)); |
1006 | I915_WRITE(vgtif_reg(pdp[i].hi), upper_32_bits(daddr)); | |
650da34c ZL |
1007 | } |
1008 | ||
1009 | msg = (create ? VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE : | |
1010 | VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY); | |
1011 | } | |
1012 | ||
1013 | I915_WRITE(vgtif_reg(g2v_notify), msg); | |
1014 | ||
1015 | return 0; | |
1016 | } | |
1017 | ||
8776f02b MK |
1018 | static void gen8_free_scratch(struct i915_address_space *vm) |
1019 | { | |
49d73912 | 1020 | struct drm_i915_private *dev_priv = vm->i915; |
8776f02b | 1021 | |
275a991c TU |
1022 | if (USES_FULL_48BIT_PPGTT(dev_priv)) |
1023 | free_pdp(dev_priv, vm->scratch_pdp); | |
1024 | free_pd(dev_priv, vm->scratch_pd); | |
1025 | free_pt(dev_priv, vm->scratch_pt); | |
1026 | cleanup_scratch_page(dev_priv, &vm->scratch_page); | |
8776f02b MK |
1027 | } |
1028 | ||
275a991c | 1029 | static void gen8_ppgtt_cleanup_3lvl(struct drm_i915_private *dev_priv, |
762d9936 | 1030 | struct i915_page_directory_pointer *pdp) |
b45a6715 BW |
1031 | { |
1032 | int i; | |
1033 | ||
275a991c | 1034 | for_each_set_bit(i, pdp->used_pdpes, I915_PDPES_PER_PDP(dev_priv)) { |
d4ec9da0 | 1035 | if (WARN_ON(!pdp->page_directory[i])) |
06fda602 BW |
1036 | continue; |
1037 | ||
275a991c TU |
1038 | gen8_free_page_tables(dev_priv, pdp->page_directory[i]); |
1039 | free_pd(dev_priv, pdp->page_directory[i]); | |
7ad47cf2 | 1040 | } |
69876bed | 1041 | |
275a991c | 1042 | free_pdp(dev_priv, pdp); |
762d9936 MT |
1043 | } |
1044 | ||
1045 | static void gen8_ppgtt_cleanup_4lvl(struct i915_hw_ppgtt *ppgtt) | |
1046 | { | |
49d73912 | 1047 | struct drm_i915_private *dev_priv = ppgtt->base.i915; |
762d9936 MT |
1048 | int i; |
1049 | ||
1050 | for_each_set_bit(i, ppgtt->pml4.used_pml4es, GEN8_PML4ES_PER_PML4) { | |
1051 | if (WARN_ON(!ppgtt->pml4.pdps[i])) | |
1052 | continue; | |
1053 | ||
275a991c | 1054 | gen8_ppgtt_cleanup_3lvl(dev_priv, ppgtt->pml4.pdps[i]); |
762d9936 MT |
1055 | } |
1056 | ||
275a991c | 1057 | cleanup_px(dev_priv, &ppgtt->pml4); |
762d9936 MT |
1058 | } |
1059 | ||
1060 | static void gen8_ppgtt_cleanup(struct i915_address_space *vm) | |
1061 | { | |
49d73912 | 1062 | struct drm_i915_private *dev_priv = vm->i915; |
e5716f55 | 1063 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
762d9936 | 1064 | |
275a991c | 1065 | if (intel_vgpu_active(dev_priv)) |
650da34c ZL |
1066 | gen8_ppgtt_notify_vgt(ppgtt, false); |
1067 | ||
275a991c TU |
1068 | if (!USES_FULL_48BIT_PPGTT(dev_priv)) |
1069 | gen8_ppgtt_cleanup_3lvl(dev_priv, &ppgtt->pdp); | |
762d9936 MT |
1070 | else |
1071 | gen8_ppgtt_cleanup_4lvl(ppgtt); | |
d4ec9da0 | 1072 | |
8776f02b | 1073 | gen8_free_scratch(vm); |
b45a6715 BW |
1074 | } |
1075 | ||
d7b2633d MT |
1076 | /** |
1077 | * gen8_ppgtt_alloc_pagetabs() - Allocate page tables for VA range. | |
d4ec9da0 MT |
1078 | * @vm: Master vm structure. |
1079 | * @pd: Page directory for this address range. | |
d7b2633d | 1080 | * @start: Starting virtual address to begin allocations. |
d4ec9da0 | 1081 | * @length: Size of the allocations. |
d7b2633d MT |
1082 | * @new_pts: Bitmap set by function with new allocations. Likely used by the |
1083 | * caller to free on error. | |
1084 | * | |
1085 | * Allocate the required number of page tables. Extremely similar to | |
1086 | * gen8_ppgtt_alloc_page_directories(). The main difference is here we are limited by | |
1087 | * the page directory boundary (instead of the page directory pointer). That | |
1088 | * boundary is 1GB virtual. Therefore, unlike gen8_ppgtt_alloc_page_directories(), it is | |
1089 | * possible, and likely that the caller will need to use multiple calls of this | |
1090 | * function to achieve the appropriate allocation. | |
1091 | * | |
1092 | * Return: 0 if success; negative error code otherwise. | |
1093 | */ | |
d4ec9da0 | 1094 | static int gen8_ppgtt_alloc_pagetabs(struct i915_address_space *vm, |
e5815a2e | 1095 | struct i915_page_directory *pd, |
5441f0cb | 1096 | uint64_t start, |
d7b2633d MT |
1097 | uint64_t length, |
1098 | unsigned long *new_pts) | |
bf2b4ed2 | 1099 | { |
49d73912 | 1100 | struct drm_i915_private *dev_priv = vm->i915; |
d7b2633d | 1101 | struct i915_page_table *pt; |
5441f0cb | 1102 | uint32_t pde; |
bf2b4ed2 | 1103 | |
e8ebd8e2 | 1104 | gen8_for_each_pde(pt, pd, start, length, pde) { |
d7b2633d | 1105 | /* Don't reallocate page tables */ |
6ac18502 | 1106 | if (test_bit(pde, pd->used_pdes)) { |
d7b2633d | 1107 | /* Scratch is never allocated this way */ |
d4ec9da0 | 1108 | WARN_ON(pt == vm->scratch_pt); |
d7b2633d MT |
1109 | continue; |
1110 | } | |
1111 | ||
275a991c | 1112 | pt = alloc_pt(dev_priv); |
d7b2633d | 1113 | if (IS_ERR(pt)) |
5441f0cb MT |
1114 | goto unwind_out; |
1115 | ||
d4ec9da0 | 1116 | gen8_initialize_pt(vm, pt); |
d7b2633d | 1117 | pd->page_table[pde] = pt; |
966082c9 | 1118 | __set_bit(pde, new_pts); |
4c06ec8d | 1119 | trace_i915_page_table_entry_alloc(vm, pde, start, GEN8_PDE_SHIFT); |
7ad47cf2 BW |
1120 | } |
1121 | ||
bf2b4ed2 | 1122 | return 0; |
7ad47cf2 BW |
1123 | |
1124 | unwind_out: | |
d7b2633d | 1125 | for_each_set_bit(pde, new_pts, I915_PDES) |
275a991c | 1126 | free_pt(dev_priv, pd->page_table[pde]); |
7ad47cf2 | 1127 | |
d7b3de91 | 1128 | return -ENOMEM; |
bf2b4ed2 BW |
1129 | } |
1130 | ||
d7b2633d MT |
1131 | /** |
1132 | * gen8_ppgtt_alloc_page_directories() - Allocate page directories for VA range. | |
d4ec9da0 | 1133 | * @vm: Master vm structure. |
d7b2633d MT |
1134 | * @pdp: Page directory pointer for this address range. |
1135 | * @start: Starting virtual address to begin allocations. | |
d4ec9da0 MT |
1136 | * @length: Size of the allocations. |
1137 | * @new_pds: Bitmap set by function with new allocations. Likely used by the | |
d7b2633d MT |
1138 | * caller to free on error. |
1139 | * | |
1140 | * Allocate the required number of page directories starting at the pde index of | |
1141 | * @start, and ending at the pde index @start + @length. This function will skip | |
1142 | * over already allocated page directories within the range, and only allocate | |
1143 | * new ones, setting the appropriate pointer within the pdp as well as the | |
1144 | * correct position in the bitmap @new_pds. | |
1145 | * | |
1146 | * The function will only allocate the pages within the range for a give page | |
1147 | * directory pointer. In other words, if @start + @length straddles a virtually | |
1148 | * addressed PDP boundary (512GB for 4k pages), there will be more allocations | |
1149 | * required by the caller, This is not currently possible, and the BUG in the | |
1150 | * code will prevent it. | |
1151 | * | |
1152 | * Return: 0 if success; negative error code otherwise. | |
1153 | */ | |
d4ec9da0 MT |
1154 | static int |
1155 | gen8_ppgtt_alloc_page_directories(struct i915_address_space *vm, | |
1156 | struct i915_page_directory_pointer *pdp, | |
1157 | uint64_t start, | |
1158 | uint64_t length, | |
1159 | unsigned long *new_pds) | |
bf2b4ed2 | 1160 | { |
49d73912 | 1161 | struct drm_i915_private *dev_priv = vm->i915; |
d7b2633d | 1162 | struct i915_page_directory *pd; |
69876bed | 1163 | uint32_t pdpe; |
275a991c | 1164 | uint32_t pdpes = I915_PDPES_PER_PDP(dev_priv); |
69876bed | 1165 | |
6ac18502 | 1166 | WARN_ON(!bitmap_empty(new_pds, pdpes)); |
d7b2633d | 1167 | |
e8ebd8e2 | 1168 | gen8_for_each_pdpe(pd, pdp, start, length, pdpe) { |
6ac18502 | 1169 | if (test_bit(pdpe, pdp->used_pdpes)) |
d7b2633d | 1170 | continue; |
33c8819f | 1171 | |
275a991c | 1172 | pd = alloc_pd(dev_priv); |
d7b2633d | 1173 | if (IS_ERR(pd)) |
d7b3de91 | 1174 | goto unwind_out; |
69876bed | 1175 | |
d4ec9da0 | 1176 | gen8_initialize_pd(vm, pd); |
d7b2633d | 1177 | pdp->page_directory[pdpe] = pd; |
966082c9 | 1178 | __set_bit(pdpe, new_pds); |
4c06ec8d | 1179 | trace_i915_page_directory_entry_alloc(vm, pdpe, start, GEN8_PDPE_SHIFT); |
d7b3de91 BW |
1180 | } |
1181 | ||
bf2b4ed2 | 1182 | return 0; |
d7b3de91 BW |
1183 | |
1184 | unwind_out: | |
6ac18502 | 1185 | for_each_set_bit(pdpe, new_pds, pdpes) |
275a991c | 1186 | free_pd(dev_priv, pdp->page_directory[pdpe]); |
d7b3de91 BW |
1187 | |
1188 | return -ENOMEM; | |
bf2b4ed2 BW |
1189 | } |
1190 | ||
762d9936 MT |
1191 | /** |
1192 | * gen8_ppgtt_alloc_page_dirpointers() - Allocate pdps for VA range. | |
1193 | * @vm: Master vm structure. | |
1194 | * @pml4: Page map level 4 for this address range. | |
1195 | * @start: Starting virtual address to begin allocations. | |
1196 | * @length: Size of the allocations. | |
1197 | * @new_pdps: Bitmap set by function with new allocations. Likely used by the | |
1198 | * caller to free on error. | |
1199 | * | |
1200 | * Allocate the required number of page directory pointers. Extremely similar to | |
1201 | * gen8_ppgtt_alloc_page_directories() and gen8_ppgtt_alloc_pagetabs(). | |
1202 | * The main difference is here we are limited by the pml4 boundary (instead of | |
1203 | * the page directory pointer). | |
1204 | * | |
1205 | * Return: 0 if success; negative error code otherwise. | |
1206 | */ | |
1207 | static int | |
1208 | gen8_ppgtt_alloc_page_dirpointers(struct i915_address_space *vm, | |
1209 | struct i915_pml4 *pml4, | |
1210 | uint64_t start, | |
1211 | uint64_t length, | |
1212 | unsigned long *new_pdps) | |
1213 | { | |
49d73912 | 1214 | struct drm_i915_private *dev_priv = vm->i915; |
762d9936 | 1215 | struct i915_page_directory_pointer *pdp; |
762d9936 MT |
1216 | uint32_t pml4e; |
1217 | ||
1218 | WARN_ON(!bitmap_empty(new_pdps, GEN8_PML4ES_PER_PML4)); | |
1219 | ||
e8ebd8e2 | 1220 | gen8_for_each_pml4e(pdp, pml4, start, length, pml4e) { |
762d9936 | 1221 | if (!test_bit(pml4e, pml4->used_pml4es)) { |
275a991c | 1222 | pdp = alloc_pdp(dev_priv); |
762d9936 MT |
1223 | if (IS_ERR(pdp)) |
1224 | goto unwind_out; | |
1225 | ||
69ab76fd | 1226 | gen8_initialize_pdp(vm, pdp); |
762d9936 MT |
1227 | pml4->pdps[pml4e] = pdp; |
1228 | __set_bit(pml4e, new_pdps); | |
1229 | trace_i915_page_directory_pointer_entry_alloc(vm, | |
1230 | pml4e, | |
1231 | start, | |
1232 | GEN8_PML4E_SHIFT); | |
1233 | } | |
1234 | } | |
1235 | ||
1236 | return 0; | |
1237 | ||
1238 | unwind_out: | |
1239 | for_each_set_bit(pml4e, new_pdps, GEN8_PML4ES_PER_PML4) | |
275a991c | 1240 | free_pdp(dev_priv, pml4->pdps[pml4e]); |
762d9936 MT |
1241 | |
1242 | return -ENOMEM; | |
1243 | } | |
1244 | ||
d7b2633d | 1245 | static void |
3a41a05d | 1246 | free_gen8_temp_bitmaps(unsigned long *new_pds, unsigned long *new_pts) |
d7b2633d | 1247 | { |
d7b2633d MT |
1248 | kfree(new_pts); |
1249 | kfree(new_pds); | |
1250 | } | |
1251 | ||
1252 | /* Fills in the page directory bitmap, and the array of page tables bitmap. Both | |
1253 | * of these are based on the number of PDPEs in the system. | |
1254 | */ | |
1255 | static | |
1256 | int __must_check alloc_gen8_temp_bitmaps(unsigned long **new_pds, | |
3a41a05d | 1257 | unsigned long **new_pts, |
6ac18502 | 1258 | uint32_t pdpes) |
d7b2633d | 1259 | { |
d7b2633d | 1260 | unsigned long *pds; |
3a41a05d | 1261 | unsigned long *pts; |
d7b2633d | 1262 | |
3a41a05d | 1263 | pds = kcalloc(BITS_TO_LONGS(pdpes), sizeof(unsigned long), GFP_TEMPORARY); |
d7b2633d MT |
1264 | if (!pds) |
1265 | return -ENOMEM; | |
1266 | ||
3a41a05d MW |
1267 | pts = kcalloc(pdpes, BITS_TO_LONGS(I915_PDES) * sizeof(unsigned long), |
1268 | GFP_TEMPORARY); | |
1269 | if (!pts) | |
1270 | goto err_out; | |
d7b2633d MT |
1271 | |
1272 | *new_pds = pds; | |
1273 | *new_pts = pts; | |
1274 | ||
1275 | return 0; | |
1276 | ||
1277 | err_out: | |
3a41a05d | 1278 | free_gen8_temp_bitmaps(pds, pts); |
d7b2633d MT |
1279 | return -ENOMEM; |
1280 | } | |
1281 | ||
762d9936 MT |
1282 | static int gen8_alloc_va_range_3lvl(struct i915_address_space *vm, |
1283 | struct i915_page_directory_pointer *pdp, | |
1284 | uint64_t start, | |
1285 | uint64_t length) | |
bf2b4ed2 | 1286 | { |
e5716f55 | 1287 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
3a41a05d | 1288 | unsigned long *new_page_dirs, *new_page_tables; |
49d73912 | 1289 | struct drm_i915_private *dev_priv = vm->i915; |
5441f0cb | 1290 | struct i915_page_directory *pd; |
33c8819f MT |
1291 | const uint64_t orig_start = start; |
1292 | const uint64_t orig_length = length; | |
5441f0cb | 1293 | uint32_t pdpe; |
275a991c | 1294 | uint32_t pdpes = I915_PDPES_PER_PDP(dev_priv); |
bf2b4ed2 BW |
1295 | int ret; |
1296 | ||
6ac18502 | 1297 | ret = alloc_gen8_temp_bitmaps(&new_page_dirs, &new_page_tables, pdpes); |
bf2b4ed2 BW |
1298 | if (ret) |
1299 | return ret; | |
1300 | ||
d7b2633d | 1301 | /* Do the allocations first so we can easily bail out */ |
d4ec9da0 MT |
1302 | ret = gen8_ppgtt_alloc_page_directories(vm, pdp, start, length, |
1303 | new_page_dirs); | |
d7b2633d | 1304 | if (ret) { |
3a41a05d | 1305 | free_gen8_temp_bitmaps(new_page_dirs, new_page_tables); |
d7b2633d MT |
1306 | return ret; |
1307 | } | |
1308 | ||
1309 | /* For every page directory referenced, allocate page tables */ | |
e8ebd8e2 | 1310 | gen8_for_each_pdpe(pd, pdp, start, length, pdpe) { |
d4ec9da0 | 1311 | ret = gen8_ppgtt_alloc_pagetabs(vm, pd, start, length, |
3a41a05d | 1312 | new_page_tables + pdpe * BITS_TO_LONGS(I915_PDES)); |
5441f0cb MT |
1313 | if (ret) |
1314 | goto err_out; | |
5441f0cb MT |
1315 | } |
1316 | ||
33c8819f MT |
1317 | start = orig_start; |
1318 | length = orig_length; | |
1319 | ||
d7b2633d MT |
1320 | /* Allocations have completed successfully, so set the bitmaps, and do |
1321 | * the mappings. */ | |
e8ebd8e2 | 1322 | gen8_for_each_pdpe(pd, pdp, start, length, pdpe) { |
d1c54acd | 1323 | gen8_pde_t *const page_directory = kmap_px(pd); |
33c8819f | 1324 | struct i915_page_table *pt; |
09120d4e | 1325 | uint64_t pd_len = length; |
33c8819f MT |
1326 | uint64_t pd_start = start; |
1327 | uint32_t pde; | |
1328 | ||
d7b2633d MT |
1329 | /* Every pd should be allocated, we just did that above. */ |
1330 | WARN_ON(!pd); | |
1331 | ||
e8ebd8e2 | 1332 | gen8_for_each_pde(pt, pd, pd_start, pd_len, pde) { |
d7b2633d MT |
1333 | /* Same reasoning as pd */ |
1334 | WARN_ON(!pt); | |
1335 | WARN_ON(!pd_len); | |
1336 | WARN_ON(!gen8_pte_count(pd_start, pd_len)); | |
1337 | ||
1338 | /* Set our used ptes within the page table */ | |
1339 | bitmap_set(pt->used_ptes, | |
1340 | gen8_pte_index(pd_start), | |
1341 | gen8_pte_count(pd_start, pd_len)); | |
1342 | ||
1343 | /* Our pde is now pointing to the pagetable, pt */ | |
966082c9 | 1344 | __set_bit(pde, pd->used_pdes); |
d7b2633d MT |
1345 | |
1346 | /* Map the PDE to the page table */ | |
fe36f55d MK |
1347 | page_directory[pde] = gen8_pde_encode(px_dma(pt), |
1348 | I915_CACHE_LLC); | |
4c06ec8d MT |
1349 | trace_i915_page_table_entry_map(&ppgtt->base, pde, pt, |
1350 | gen8_pte_index(start), | |
1351 | gen8_pte_count(start, length), | |
1352 | GEN8_PTES); | |
d7b2633d MT |
1353 | |
1354 | /* NB: We haven't yet mapped ptes to pages. At this | |
1355 | * point we're still relying on insert_entries() */ | |
33c8819f | 1356 | } |
d7b2633d | 1357 | |
d1c54acd | 1358 | kunmap_px(ppgtt, page_directory); |
d4ec9da0 | 1359 | __set_bit(pdpe, pdp->used_pdpes); |
5c693b2b | 1360 | gen8_setup_pdpe(ppgtt, pdp, pd, pdpe); |
33c8819f MT |
1361 | } |
1362 | ||
3a41a05d | 1363 | free_gen8_temp_bitmaps(new_page_dirs, new_page_tables); |
5b7e4c9c | 1364 | mark_tlbs_dirty(ppgtt); |
d7b3de91 | 1365 | return 0; |
bf2b4ed2 | 1366 | |
d7b3de91 | 1367 | err_out: |
d7b2633d | 1368 | while (pdpe--) { |
e8ebd8e2 DG |
1369 | unsigned long temp; |
1370 | ||
3a41a05d MW |
1371 | for_each_set_bit(temp, new_page_tables + pdpe * |
1372 | BITS_TO_LONGS(I915_PDES), I915_PDES) | |
275a991c TU |
1373 | free_pt(dev_priv, |
1374 | pdp->page_directory[pdpe]->page_table[temp]); | |
d7b2633d MT |
1375 | } |
1376 | ||
6ac18502 | 1377 | for_each_set_bit(pdpe, new_page_dirs, pdpes) |
275a991c | 1378 | free_pd(dev_priv, pdp->page_directory[pdpe]); |
d7b2633d | 1379 | |
3a41a05d | 1380 | free_gen8_temp_bitmaps(new_page_dirs, new_page_tables); |
5b7e4c9c | 1381 | mark_tlbs_dirty(ppgtt); |
bf2b4ed2 BW |
1382 | return ret; |
1383 | } | |
1384 | ||
762d9936 MT |
1385 | static int gen8_alloc_va_range_4lvl(struct i915_address_space *vm, |
1386 | struct i915_pml4 *pml4, | |
1387 | uint64_t start, | |
1388 | uint64_t length) | |
1389 | { | |
1390 | DECLARE_BITMAP(new_pdps, GEN8_PML4ES_PER_PML4); | |
e5716f55 | 1391 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
762d9936 | 1392 | struct i915_page_directory_pointer *pdp; |
e8ebd8e2 | 1393 | uint64_t pml4e; |
762d9936 MT |
1394 | int ret = 0; |
1395 | ||
1396 | /* Do the pml4 allocations first, so we don't need to track the newly | |
1397 | * allocated tables below the pdp */ | |
1398 | bitmap_zero(new_pdps, GEN8_PML4ES_PER_PML4); | |
1399 | ||
1400 | /* The pagedirectory and pagetable allocations are done in the shared 3 | |
1401 | * and 4 level code. Just allocate the pdps. | |
1402 | */ | |
1403 | ret = gen8_ppgtt_alloc_page_dirpointers(vm, pml4, start, length, | |
1404 | new_pdps); | |
1405 | if (ret) | |
1406 | return ret; | |
1407 | ||
1408 | WARN(bitmap_weight(new_pdps, GEN8_PML4ES_PER_PML4) > 2, | |
1409 | "The allocation has spanned more than 512GB. " | |
1410 | "It is highly likely this is incorrect."); | |
1411 | ||
e8ebd8e2 | 1412 | gen8_for_each_pml4e(pdp, pml4, start, length, pml4e) { |
762d9936 MT |
1413 | WARN_ON(!pdp); |
1414 | ||
1415 | ret = gen8_alloc_va_range_3lvl(vm, pdp, start, length); | |
1416 | if (ret) | |
1417 | goto err_out; | |
1418 | ||
56843107 | 1419 | gen8_setup_pml4e(ppgtt, pml4, pdp, pml4e); |
762d9936 MT |
1420 | } |
1421 | ||
1422 | bitmap_or(pml4->used_pml4es, new_pdps, pml4->used_pml4es, | |
1423 | GEN8_PML4ES_PER_PML4); | |
1424 | ||
1425 | return 0; | |
1426 | ||
1427 | err_out: | |
1428 | for_each_set_bit(pml4e, new_pdps, GEN8_PML4ES_PER_PML4) | |
49d73912 | 1429 | gen8_ppgtt_cleanup_3lvl(vm->i915, pml4->pdps[pml4e]); |
762d9936 MT |
1430 | |
1431 | return ret; | |
1432 | } | |
1433 | ||
1434 | static int gen8_alloc_va_range(struct i915_address_space *vm, | |
1435 | uint64_t start, uint64_t length) | |
1436 | { | |
e5716f55 | 1437 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
762d9936 | 1438 | |
c6385c94 | 1439 | if (USES_FULL_48BIT_PPGTT(vm->i915)) |
762d9936 MT |
1440 | return gen8_alloc_va_range_4lvl(vm, &ppgtt->pml4, start, length); |
1441 | else | |
1442 | return gen8_alloc_va_range_3lvl(vm, &ppgtt->pdp, start, length); | |
1443 | } | |
1444 | ||
ea91e401 MT |
1445 | static void gen8_dump_pdp(struct i915_page_directory_pointer *pdp, |
1446 | uint64_t start, uint64_t length, | |
1447 | gen8_pte_t scratch_pte, | |
1448 | struct seq_file *m) | |
1449 | { | |
1450 | struct i915_page_directory *pd; | |
ea91e401 MT |
1451 | uint32_t pdpe; |
1452 | ||
e8ebd8e2 | 1453 | gen8_for_each_pdpe(pd, pdp, start, length, pdpe) { |
ea91e401 MT |
1454 | struct i915_page_table *pt; |
1455 | uint64_t pd_len = length; | |
1456 | uint64_t pd_start = start; | |
1457 | uint32_t pde; | |
1458 | ||
1459 | if (!test_bit(pdpe, pdp->used_pdpes)) | |
1460 | continue; | |
1461 | ||
1462 | seq_printf(m, "\tPDPE #%d\n", pdpe); | |
e8ebd8e2 | 1463 | gen8_for_each_pde(pt, pd, pd_start, pd_len, pde) { |
ea91e401 MT |
1464 | uint32_t pte; |
1465 | gen8_pte_t *pt_vaddr; | |
1466 | ||
1467 | if (!test_bit(pde, pd->used_pdes)) | |
1468 | continue; | |
1469 | ||
1470 | pt_vaddr = kmap_px(pt); | |
1471 | for (pte = 0; pte < GEN8_PTES; pte += 4) { | |
1472 | uint64_t va = | |
1473 | (pdpe << GEN8_PDPE_SHIFT) | | |
1474 | (pde << GEN8_PDE_SHIFT) | | |
1475 | (pte << GEN8_PTE_SHIFT); | |
1476 | int i; | |
1477 | bool found = false; | |
1478 | ||
1479 | for (i = 0; i < 4; i++) | |
1480 | if (pt_vaddr[pte + i] != scratch_pte) | |
1481 | found = true; | |
1482 | if (!found) | |
1483 | continue; | |
1484 | ||
1485 | seq_printf(m, "\t\t0x%llx [%03d,%03d,%04d]: =", va, pdpe, pde, pte); | |
1486 | for (i = 0; i < 4; i++) { | |
1487 | if (pt_vaddr[pte + i] != scratch_pte) | |
1488 | seq_printf(m, " %llx", pt_vaddr[pte + i]); | |
1489 | else | |
1490 | seq_puts(m, " SCRATCH "); | |
1491 | } | |
1492 | seq_puts(m, "\n"); | |
1493 | } | |
1494 | /* don't use kunmap_px, it could trigger | |
1495 | * an unnecessary flush. | |
1496 | */ | |
1497 | kunmap_atomic(pt_vaddr); | |
1498 | } | |
1499 | } | |
1500 | } | |
1501 | ||
1502 | static void gen8_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m) | |
1503 | { | |
1504 | struct i915_address_space *vm = &ppgtt->base; | |
1505 | uint64_t start = ppgtt->base.start; | |
1506 | uint64_t length = ppgtt->base.total; | |
8bcdd0f7 | 1507 | gen8_pte_t scratch_pte = gen8_pte_encode(vm->scratch_page.daddr, |
4fb84d99 | 1508 | I915_CACHE_LLC); |
ea91e401 | 1509 | |
c6385c94 | 1510 | if (!USES_FULL_48BIT_PPGTT(vm->i915)) { |
ea91e401 MT |
1511 | gen8_dump_pdp(&ppgtt->pdp, start, length, scratch_pte, m); |
1512 | } else { | |
e8ebd8e2 | 1513 | uint64_t pml4e; |
ea91e401 MT |
1514 | struct i915_pml4 *pml4 = &ppgtt->pml4; |
1515 | struct i915_page_directory_pointer *pdp; | |
1516 | ||
e8ebd8e2 | 1517 | gen8_for_each_pml4e(pdp, pml4, start, length, pml4e) { |
ea91e401 MT |
1518 | if (!test_bit(pml4e, pml4->used_pml4es)) |
1519 | continue; | |
1520 | ||
1521 | seq_printf(m, " PML4E #%llu\n", pml4e); | |
1522 | gen8_dump_pdp(pdp, start, length, scratch_pte, m); | |
1523 | } | |
1524 | } | |
1525 | } | |
1526 | ||
331f38e7 ZL |
1527 | static int gen8_preallocate_top_level_pdps(struct i915_hw_ppgtt *ppgtt) |
1528 | { | |
3a41a05d | 1529 | unsigned long *new_page_dirs, *new_page_tables; |
275a991c | 1530 | uint32_t pdpes = I915_PDPES_PER_PDP(to_i915(ppgtt->base.dev)); |
331f38e7 ZL |
1531 | int ret; |
1532 | ||
1533 | /* We allocate temp bitmap for page tables for no gain | |
1534 | * but as this is for init only, lets keep the things simple | |
1535 | */ | |
1536 | ret = alloc_gen8_temp_bitmaps(&new_page_dirs, &new_page_tables, pdpes); | |
1537 | if (ret) | |
1538 | return ret; | |
1539 | ||
1540 | /* Allocate for all pdps regardless of how the ppgtt | |
1541 | * was defined. | |
1542 | */ | |
1543 | ret = gen8_ppgtt_alloc_page_directories(&ppgtt->base, &ppgtt->pdp, | |
1544 | 0, 1ULL << 32, | |
1545 | new_page_dirs); | |
1546 | if (!ret) | |
1547 | *ppgtt->pdp.used_pdpes = *new_page_dirs; | |
1548 | ||
3a41a05d | 1549 | free_gen8_temp_bitmaps(new_page_dirs, new_page_tables); |
331f38e7 ZL |
1550 | |
1551 | return ret; | |
1552 | } | |
1553 | ||
eb0b44ad | 1554 | /* |
f3a964b9 BW |
1555 | * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers |
1556 | * with a net effect resembling a 2-level page table in normal x86 terms. Each | |
1557 | * PDP represents 1GB of memory 4 * 512 * 512 * 4096 = 4GB legacy 32b address | |
1558 | * space. | |
37aca44a | 1559 | * |
f3a964b9 | 1560 | */ |
5c5f6457 | 1561 | static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt) |
37aca44a | 1562 | { |
49d73912 | 1563 | struct drm_i915_private *dev_priv = ppgtt->base.i915; |
8776f02b | 1564 | int ret; |
7cb6d7ac | 1565 | |
8776f02b MK |
1566 | ret = gen8_init_scratch(&ppgtt->base); |
1567 | if (ret) | |
1568 | return ret; | |
69876bed | 1569 | |
d7b2633d | 1570 | ppgtt->base.start = 0; |
d7b2633d | 1571 | ppgtt->base.cleanup = gen8_ppgtt_cleanup; |
5c5f6457 | 1572 | ppgtt->base.allocate_va_range = gen8_alloc_va_range; |
d7b2633d | 1573 | ppgtt->base.insert_entries = gen8_ppgtt_insert_entries; |
c7e16f22 | 1574 | ppgtt->base.clear_range = gen8_ppgtt_clear_range; |
777dc5bb DV |
1575 | ppgtt->base.unbind_vma = ppgtt_unbind_vma; |
1576 | ppgtt->base.bind_vma = ppgtt_bind_vma; | |
ea91e401 | 1577 | ppgtt->debug_dump = gen8_dump_ppgtt; |
d7b2633d | 1578 | |
275a991c TU |
1579 | if (USES_FULL_48BIT_PPGTT(dev_priv)) { |
1580 | ret = setup_px(dev_priv, &ppgtt->pml4); | |
762d9936 MT |
1581 | if (ret) |
1582 | goto free_scratch; | |
6ac18502 | 1583 | |
69ab76fd MT |
1584 | gen8_initialize_pml4(&ppgtt->base, &ppgtt->pml4); |
1585 | ||
762d9936 | 1586 | ppgtt->base.total = 1ULL << 48; |
2dba3239 | 1587 | ppgtt->switch_mm = gen8_48b_mm_switch; |
762d9936 | 1588 | } else { |
275a991c | 1589 | ret = __pdp_init(dev_priv, &ppgtt->pdp); |
81ba8aef MT |
1590 | if (ret) |
1591 | goto free_scratch; | |
1592 | ||
1593 | ppgtt->base.total = 1ULL << 32; | |
2dba3239 | 1594 | ppgtt->switch_mm = gen8_legacy_mm_switch; |
762d9936 MT |
1595 | trace_i915_page_directory_pointer_entry_alloc(&ppgtt->base, |
1596 | 0, 0, | |
1597 | GEN8_PML4E_SHIFT); | |
331f38e7 | 1598 | |
275a991c | 1599 | if (intel_vgpu_active(dev_priv)) { |
331f38e7 ZL |
1600 | ret = gen8_preallocate_top_level_pdps(ppgtt); |
1601 | if (ret) | |
1602 | goto free_scratch; | |
1603 | } | |
81ba8aef | 1604 | } |
6ac18502 | 1605 | |
275a991c | 1606 | if (intel_vgpu_active(dev_priv)) |
650da34c ZL |
1607 | gen8_ppgtt_notify_vgt(ppgtt, true); |
1608 | ||
d7b2633d | 1609 | return 0; |
6ac18502 MT |
1610 | |
1611 | free_scratch: | |
1612 | gen8_free_scratch(&ppgtt->base); | |
1613 | return ret; | |
d7b2633d MT |
1614 | } |
1615 | ||
87d60b63 BW |
1616 | static void gen6_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m) |
1617 | { | |
87d60b63 | 1618 | struct i915_address_space *vm = &ppgtt->base; |
09942c65 | 1619 | struct i915_page_table *unused; |
07749ef3 | 1620 | gen6_pte_t scratch_pte; |
87d60b63 | 1621 | uint32_t pd_entry; |
731f74c5 | 1622 | uint32_t pte, pde; |
09942c65 | 1623 | uint32_t start = ppgtt->base.start, length = ppgtt->base.total; |
87d60b63 | 1624 | |
8bcdd0f7 | 1625 | scratch_pte = vm->pte_encode(vm->scratch_page.daddr, |
4fb84d99 | 1626 | I915_CACHE_LLC, 0); |
87d60b63 | 1627 | |
731f74c5 | 1628 | gen6_for_each_pde(unused, &ppgtt->pd, start, length, pde) { |
87d60b63 | 1629 | u32 expected; |
07749ef3 | 1630 | gen6_pte_t *pt_vaddr; |
567047be | 1631 | const dma_addr_t pt_addr = px_dma(ppgtt->pd.page_table[pde]); |
09942c65 | 1632 | pd_entry = readl(ppgtt->pd_addr + pde); |
87d60b63 BW |
1633 | expected = (GEN6_PDE_ADDR_ENCODE(pt_addr) | GEN6_PDE_VALID); |
1634 | ||
1635 | if (pd_entry != expected) | |
1636 | seq_printf(m, "\tPDE #%d mismatch: Actual PDE: %x Expected PDE: %x\n", | |
1637 | pde, | |
1638 | pd_entry, | |
1639 | expected); | |
1640 | seq_printf(m, "\tPDE: %x\n", pd_entry); | |
1641 | ||
d1c54acd MK |
1642 | pt_vaddr = kmap_px(ppgtt->pd.page_table[pde]); |
1643 | ||
07749ef3 | 1644 | for (pte = 0; pte < GEN6_PTES; pte+=4) { |
87d60b63 | 1645 | unsigned long va = |
07749ef3 | 1646 | (pde * PAGE_SIZE * GEN6_PTES) + |
87d60b63 BW |
1647 | (pte * PAGE_SIZE); |
1648 | int i; | |
1649 | bool found = false; | |
1650 | for (i = 0; i < 4; i++) | |
1651 | if (pt_vaddr[pte + i] != scratch_pte) | |
1652 | found = true; | |
1653 | if (!found) | |
1654 | continue; | |
1655 | ||
1656 | seq_printf(m, "\t\t0x%lx [%03d,%04d]: =", va, pde, pte); | |
1657 | for (i = 0; i < 4; i++) { | |
1658 | if (pt_vaddr[pte + i] != scratch_pte) | |
1659 | seq_printf(m, " %08x", pt_vaddr[pte + i]); | |
1660 | else | |
1661 | seq_puts(m, " SCRATCH "); | |
1662 | } | |
1663 | seq_puts(m, "\n"); | |
1664 | } | |
d1c54acd | 1665 | kunmap_px(ppgtt, pt_vaddr); |
87d60b63 BW |
1666 | } |
1667 | } | |
1668 | ||
678d96fb | 1669 | /* Write pde (index) from the page directory @pd to the page table @pt */ |
ec565b3c MT |
1670 | static void gen6_write_pde(struct i915_page_directory *pd, |
1671 | const int pde, struct i915_page_table *pt) | |
6197349b | 1672 | { |
678d96fb BW |
1673 | /* Caller needs to make sure the write completes if necessary */ |
1674 | struct i915_hw_ppgtt *ppgtt = | |
1675 | container_of(pd, struct i915_hw_ppgtt, pd); | |
1676 | u32 pd_entry; | |
6197349b | 1677 | |
567047be | 1678 | pd_entry = GEN6_PDE_ADDR_ENCODE(px_dma(pt)); |
678d96fb | 1679 | pd_entry |= GEN6_PDE_VALID; |
6197349b | 1680 | |
678d96fb BW |
1681 | writel(pd_entry, ppgtt->pd_addr + pde); |
1682 | } | |
6197349b | 1683 | |
678d96fb BW |
1684 | /* Write all the page tables found in the ppgtt structure to incrementing page |
1685 | * directories. */ | |
1686 | static void gen6_write_page_range(struct drm_i915_private *dev_priv, | |
ec565b3c | 1687 | struct i915_page_directory *pd, |
678d96fb BW |
1688 | uint32_t start, uint32_t length) |
1689 | { | |
72e96d64 | 1690 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
ec565b3c | 1691 | struct i915_page_table *pt; |
731f74c5 | 1692 | uint32_t pde; |
678d96fb | 1693 | |
731f74c5 | 1694 | gen6_for_each_pde(pt, pd, start, length, pde) |
678d96fb BW |
1695 | gen6_write_pde(pd, pde, pt); |
1696 | ||
1697 | /* Make sure write is complete before other code can use this page | |
1698 | * table. Also require for WC mapped PTEs */ | |
72e96d64 | 1699 | readl(ggtt->gsm); |
3e302542 BW |
1700 | } |
1701 | ||
b4a74e3a | 1702 | static uint32_t get_pd_offset(struct i915_hw_ppgtt *ppgtt) |
3e302542 | 1703 | { |
44159ddb | 1704 | BUG_ON(ppgtt->pd.base.ggtt_offset & 0x3f); |
b4a74e3a | 1705 | |
44159ddb | 1706 | return (ppgtt->pd.base.ggtt_offset / 64) << 16; |
b4a74e3a BW |
1707 | } |
1708 | ||
90252e5c | 1709 | static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt, |
e85b26dc | 1710 | struct drm_i915_gem_request *req) |
90252e5c | 1711 | { |
7e37f889 | 1712 | struct intel_ring *ring = req->ring; |
4a570db5 | 1713 | struct intel_engine_cs *engine = req->engine; |
90252e5c BW |
1714 | int ret; |
1715 | ||
90252e5c | 1716 | /* NB: TLBs must be flushed and invalidated before a switch */ |
7c9cf4e3 | 1717 | ret = engine->emit_flush(req, EMIT_INVALIDATE | EMIT_FLUSH); |
90252e5c BW |
1718 | if (ret) |
1719 | return ret; | |
1720 | ||
5fb9de1a | 1721 | ret = intel_ring_begin(req, 6); |
90252e5c BW |
1722 | if (ret) |
1723 | return ret; | |
1724 | ||
b5321f30 CW |
1725 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2)); |
1726 | intel_ring_emit_reg(ring, RING_PP_DIR_DCLV(engine)); | |
1727 | intel_ring_emit(ring, PP_DIR_DCLV_2G); | |
1728 | intel_ring_emit_reg(ring, RING_PP_DIR_BASE(engine)); | |
1729 | intel_ring_emit(ring, get_pd_offset(ppgtt)); | |
1730 | intel_ring_emit(ring, MI_NOOP); | |
1731 | intel_ring_advance(ring); | |
90252e5c BW |
1732 | |
1733 | return 0; | |
1734 | } | |
1735 | ||
48a10389 | 1736 | static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt, |
e85b26dc | 1737 | struct drm_i915_gem_request *req) |
48a10389 | 1738 | { |
7e37f889 | 1739 | struct intel_ring *ring = req->ring; |
4a570db5 | 1740 | struct intel_engine_cs *engine = req->engine; |
48a10389 BW |
1741 | int ret; |
1742 | ||
48a10389 | 1743 | /* NB: TLBs must be flushed and invalidated before a switch */ |
7c9cf4e3 | 1744 | ret = engine->emit_flush(req, EMIT_INVALIDATE | EMIT_FLUSH); |
48a10389 BW |
1745 | if (ret) |
1746 | return ret; | |
1747 | ||
5fb9de1a | 1748 | ret = intel_ring_begin(req, 6); |
48a10389 BW |
1749 | if (ret) |
1750 | return ret; | |
1751 | ||
b5321f30 CW |
1752 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2)); |
1753 | intel_ring_emit_reg(ring, RING_PP_DIR_DCLV(engine)); | |
1754 | intel_ring_emit(ring, PP_DIR_DCLV_2G); | |
1755 | intel_ring_emit_reg(ring, RING_PP_DIR_BASE(engine)); | |
1756 | intel_ring_emit(ring, get_pd_offset(ppgtt)); | |
1757 | intel_ring_emit(ring, MI_NOOP); | |
1758 | intel_ring_advance(ring); | |
48a10389 | 1759 | |
90252e5c | 1760 | /* XXX: RCS is the only one to auto invalidate the TLBs? */ |
e2f80391 | 1761 | if (engine->id != RCS) { |
7c9cf4e3 | 1762 | ret = engine->emit_flush(req, EMIT_INVALIDATE | EMIT_FLUSH); |
90252e5c BW |
1763 | if (ret) |
1764 | return ret; | |
1765 | } | |
1766 | ||
48a10389 BW |
1767 | return 0; |
1768 | } | |
1769 | ||
eeb9488e | 1770 | static int gen6_mm_switch(struct i915_hw_ppgtt *ppgtt, |
e85b26dc | 1771 | struct drm_i915_gem_request *req) |
eeb9488e | 1772 | { |
4a570db5 | 1773 | struct intel_engine_cs *engine = req->engine; |
8eb95204 | 1774 | struct drm_i915_private *dev_priv = req->i915; |
48a10389 | 1775 | |
e2f80391 TU |
1776 | I915_WRITE(RING_PP_DIR_DCLV(engine), PP_DIR_DCLV_2G); |
1777 | I915_WRITE(RING_PP_DIR_BASE(engine), get_pd_offset(ppgtt)); | |
eeb9488e BW |
1778 | return 0; |
1779 | } | |
1780 | ||
c6be607a | 1781 | static void gen8_ppgtt_enable(struct drm_i915_private *dev_priv) |
eeb9488e | 1782 | { |
e2f80391 | 1783 | struct intel_engine_cs *engine; |
3b3f1650 | 1784 | enum intel_engine_id id; |
3e302542 | 1785 | |
3b3f1650 | 1786 | for_each_engine(engine, dev_priv, id) { |
c6be607a TU |
1787 | u32 four_level = USES_FULL_48BIT_PPGTT(dev_priv) ? |
1788 | GEN8_GFX_PPGTT_48B : 0; | |
e2f80391 | 1789 | I915_WRITE(RING_MODE_GEN7(engine), |
2dba3239 | 1790 | _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE | four_level)); |
eeb9488e | 1791 | } |
eeb9488e | 1792 | } |
6197349b | 1793 | |
c6be607a | 1794 | static void gen7_ppgtt_enable(struct drm_i915_private *dev_priv) |
3e302542 | 1795 | { |
e2f80391 | 1796 | struct intel_engine_cs *engine; |
b4a74e3a | 1797 | uint32_t ecochk, ecobits; |
3b3f1650 | 1798 | enum intel_engine_id id; |
6197349b | 1799 | |
b4a74e3a BW |
1800 | ecobits = I915_READ(GAC_ECO_BITS); |
1801 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B); | |
a65c2fcd | 1802 | |
b4a74e3a | 1803 | ecochk = I915_READ(GAM_ECOCHK); |
772c2a51 | 1804 | if (IS_HASWELL(dev_priv)) { |
b4a74e3a BW |
1805 | ecochk |= ECOCHK_PPGTT_WB_HSW; |
1806 | } else { | |
1807 | ecochk |= ECOCHK_PPGTT_LLC_IVB; | |
1808 | ecochk &= ~ECOCHK_PPGTT_GFDT_IVB; | |
1809 | } | |
1810 | I915_WRITE(GAM_ECOCHK, ecochk); | |
a65c2fcd | 1811 | |
3b3f1650 | 1812 | for_each_engine(engine, dev_priv, id) { |
6197349b | 1813 | /* GFX_MODE is per-ring on gen7+ */ |
e2f80391 | 1814 | I915_WRITE(RING_MODE_GEN7(engine), |
b4a74e3a | 1815 | _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); |
6197349b | 1816 | } |
b4a74e3a | 1817 | } |
6197349b | 1818 | |
c6be607a | 1819 | static void gen6_ppgtt_enable(struct drm_i915_private *dev_priv) |
b4a74e3a | 1820 | { |
b4a74e3a | 1821 | uint32_t ecochk, gab_ctl, ecobits; |
a65c2fcd | 1822 | |
b4a74e3a BW |
1823 | ecobits = I915_READ(GAC_ECO_BITS); |
1824 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT | | |
1825 | ECOBITS_PPGTT_CACHE64B); | |
6197349b | 1826 | |
b4a74e3a BW |
1827 | gab_ctl = I915_READ(GAB_CTL); |
1828 | I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT); | |
1829 | ||
1830 | ecochk = I915_READ(GAM_ECOCHK); | |
1831 | I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B); | |
1832 | ||
1833 | I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
6197349b BW |
1834 | } |
1835 | ||
1d2a314c | 1836 | /* PPGTT support for Sandybdrige/Gen6 and later */ |
853ba5d2 | 1837 | static void gen6_ppgtt_clear_range(struct i915_address_space *vm, |
782f1495 | 1838 | uint64_t start, |
4fb84d99 | 1839 | uint64_t length) |
1d2a314c | 1840 | { |
e5716f55 | 1841 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
07749ef3 | 1842 | gen6_pte_t *pt_vaddr, scratch_pte; |
782f1495 BW |
1843 | unsigned first_entry = start >> PAGE_SHIFT; |
1844 | unsigned num_entries = length >> PAGE_SHIFT; | |
07749ef3 MT |
1845 | unsigned act_pt = first_entry / GEN6_PTES; |
1846 | unsigned first_pte = first_entry % GEN6_PTES; | |
7bddb01f | 1847 | unsigned last_pte, i; |
1d2a314c | 1848 | |
8bcdd0f7 | 1849 | scratch_pte = vm->pte_encode(vm->scratch_page.daddr, |
4fb84d99 | 1850 | I915_CACHE_LLC, 0); |
1d2a314c | 1851 | |
7bddb01f DV |
1852 | while (num_entries) { |
1853 | last_pte = first_pte + num_entries; | |
07749ef3 MT |
1854 | if (last_pte > GEN6_PTES) |
1855 | last_pte = GEN6_PTES; | |
7bddb01f | 1856 | |
d1c54acd | 1857 | pt_vaddr = kmap_px(ppgtt->pd.page_table[act_pt]); |
1d2a314c | 1858 | |
7bddb01f DV |
1859 | for (i = first_pte; i < last_pte; i++) |
1860 | pt_vaddr[i] = scratch_pte; | |
1d2a314c | 1861 | |
d1c54acd | 1862 | kunmap_px(ppgtt, pt_vaddr); |
1d2a314c | 1863 | |
7bddb01f DV |
1864 | num_entries -= last_pte - first_pte; |
1865 | first_pte = 0; | |
a15326a5 | 1866 | act_pt++; |
7bddb01f | 1867 | } |
1d2a314c DV |
1868 | } |
1869 | ||
853ba5d2 | 1870 | static void gen6_ppgtt_insert_entries(struct i915_address_space *vm, |
def886c3 | 1871 | struct sg_table *pages, |
782f1495 | 1872 | uint64_t start, |
24f3a8cf | 1873 | enum i915_cache_level cache_level, u32 flags) |
def886c3 | 1874 | { |
e5716f55 | 1875 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
782f1495 | 1876 | unsigned first_entry = start >> PAGE_SHIFT; |
07749ef3 MT |
1877 | unsigned act_pt = first_entry / GEN6_PTES; |
1878 | unsigned act_pte = first_entry % GEN6_PTES; | |
85d1225e DG |
1879 | gen6_pte_t *pt_vaddr = NULL; |
1880 | struct sgt_iter sgt_iter; | |
1881 | dma_addr_t addr; | |
6e995e23 | 1882 | |
85d1225e | 1883 | for_each_sgt_dma(addr, sgt_iter, pages) { |
cc79714f | 1884 | if (pt_vaddr == NULL) |
d1c54acd | 1885 | pt_vaddr = kmap_px(ppgtt->pd.page_table[act_pt]); |
6e995e23 | 1886 | |
cc79714f | 1887 | pt_vaddr[act_pte] = |
4fb84d99 | 1888 | vm->pte_encode(addr, cache_level, flags); |
24f3a8cf | 1889 | |
07749ef3 | 1890 | if (++act_pte == GEN6_PTES) { |
d1c54acd | 1891 | kunmap_px(ppgtt, pt_vaddr); |
cc79714f | 1892 | pt_vaddr = NULL; |
a15326a5 | 1893 | act_pt++; |
6e995e23 | 1894 | act_pte = 0; |
def886c3 | 1895 | } |
def886c3 | 1896 | } |
85d1225e | 1897 | |
cc79714f | 1898 | if (pt_vaddr) |
d1c54acd | 1899 | kunmap_px(ppgtt, pt_vaddr); |
def886c3 DV |
1900 | } |
1901 | ||
678d96fb | 1902 | static int gen6_alloc_va_range(struct i915_address_space *vm, |
a05d80ee | 1903 | uint64_t start_in, uint64_t length_in) |
678d96fb | 1904 | { |
4933d519 | 1905 | DECLARE_BITMAP(new_page_tables, I915_PDES); |
49d73912 | 1906 | struct drm_i915_private *dev_priv = vm->i915; |
72e96d64 | 1907 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
e5716f55 | 1908 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
ec565b3c | 1909 | struct i915_page_table *pt; |
a05d80ee | 1910 | uint32_t start, length, start_save, length_save; |
731f74c5 | 1911 | uint32_t pde; |
4933d519 MT |
1912 | int ret; |
1913 | ||
a05d80ee MK |
1914 | start = start_save = start_in; |
1915 | length = length_save = length_in; | |
4933d519 MT |
1916 | |
1917 | bitmap_zero(new_page_tables, I915_PDES); | |
1918 | ||
1919 | /* The allocation is done in two stages so that we can bail out with | |
1920 | * minimal amount of pain. The first stage finds new page tables that | |
1921 | * need allocation. The second stage marks use ptes within the page | |
1922 | * tables. | |
1923 | */ | |
731f74c5 | 1924 | gen6_for_each_pde(pt, &ppgtt->pd, start, length, pde) { |
79ab9370 | 1925 | if (pt != vm->scratch_pt) { |
4933d519 MT |
1926 | WARN_ON(bitmap_empty(pt->used_ptes, GEN6_PTES)); |
1927 | continue; | |
1928 | } | |
1929 | ||
1930 | /* We've already allocated a page table */ | |
1931 | WARN_ON(!bitmap_empty(pt->used_ptes, GEN6_PTES)); | |
1932 | ||
275a991c | 1933 | pt = alloc_pt(dev_priv); |
4933d519 MT |
1934 | if (IS_ERR(pt)) { |
1935 | ret = PTR_ERR(pt); | |
1936 | goto unwind_out; | |
1937 | } | |
1938 | ||
1939 | gen6_initialize_pt(vm, pt); | |
1940 | ||
1941 | ppgtt->pd.page_table[pde] = pt; | |
966082c9 | 1942 | __set_bit(pde, new_page_tables); |
72744cb1 | 1943 | trace_i915_page_table_entry_alloc(vm, pde, start, GEN6_PDE_SHIFT); |
4933d519 MT |
1944 | } |
1945 | ||
1946 | start = start_save; | |
1947 | length = length_save; | |
678d96fb | 1948 | |
731f74c5 | 1949 | gen6_for_each_pde(pt, &ppgtt->pd, start, length, pde) { |
678d96fb BW |
1950 | DECLARE_BITMAP(tmp_bitmap, GEN6_PTES); |
1951 | ||
1952 | bitmap_zero(tmp_bitmap, GEN6_PTES); | |
1953 | bitmap_set(tmp_bitmap, gen6_pte_index(start), | |
1954 | gen6_pte_count(start, length)); | |
1955 | ||
966082c9 | 1956 | if (__test_and_clear_bit(pde, new_page_tables)) |
4933d519 MT |
1957 | gen6_write_pde(&ppgtt->pd, pde, pt); |
1958 | ||
72744cb1 MT |
1959 | trace_i915_page_table_entry_map(vm, pde, pt, |
1960 | gen6_pte_index(start), | |
1961 | gen6_pte_count(start, length), | |
1962 | GEN6_PTES); | |
4933d519 | 1963 | bitmap_or(pt->used_ptes, tmp_bitmap, pt->used_ptes, |
678d96fb BW |
1964 | GEN6_PTES); |
1965 | } | |
1966 | ||
4933d519 MT |
1967 | WARN_ON(!bitmap_empty(new_page_tables, I915_PDES)); |
1968 | ||
1969 | /* Make sure write is complete before other code can use this page | |
1970 | * table. Also require for WC mapped PTEs */ | |
72e96d64 | 1971 | readl(ggtt->gsm); |
4933d519 | 1972 | |
563222a7 | 1973 | mark_tlbs_dirty(ppgtt); |
678d96fb | 1974 | return 0; |
4933d519 MT |
1975 | |
1976 | unwind_out: | |
1977 | for_each_set_bit(pde, new_page_tables, I915_PDES) { | |
ec565b3c | 1978 | struct i915_page_table *pt = ppgtt->pd.page_table[pde]; |
4933d519 | 1979 | |
79ab9370 | 1980 | ppgtt->pd.page_table[pde] = vm->scratch_pt; |
275a991c | 1981 | free_pt(dev_priv, pt); |
4933d519 MT |
1982 | } |
1983 | ||
1984 | mark_tlbs_dirty(ppgtt); | |
1985 | return ret; | |
678d96fb BW |
1986 | } |
1987 | ||
8776f02b MK |
1988 | static int gen6_init_scratch(struct i915_address_space *vm) |
1989 | { | |
49d73912 | 1990 | struct drm_i915_private *dev_priv = vm->i915; |
8bcdd0f7 | 1991 | int ret; |
8776f02b | 1992 | |
275a991c | 1993 | ret = setup_scratch_page(dev_priv, &vm->scratch_page, I915_GFP_DMA); |
8bcdd0f7 CW |
1994 | if (ret) |
1995 | return ret; | |
8776f02b | 1996 | |
275a991c | 1997 | vm->scratch_pt = alloc_pt(dev_priv); |
8776f02b | 1998 | if (IS_ERR(vm->scratch_pt)) { |
275a991c | 1999 | cleanup_scratch_page(dev_priv, &vm->scratch_page); |
8776f02b MK |
2000 | return PTR_ERR(vm->scratch_pt); |
2001 | } | |
2002 | ||
2003 | gen6_initialize_pt(vm, vm->scratch_pt); | |
2004 | ||
2005 | return 0; | |
2006 | } | |
2007 | ||
2008 | static void gen6_free_scratch(struct i915_address_space *vm) | |
2009 | { | |
49d73912 | 2010 | struct drm_i915_private *dev_priv = vm->i915; |
8776f02b | 2011 | |
275a991c TU |
2012 | free_pt(dev_priv, vm->scratch_pt); |
2013 | cleanup_scratch_page(dev_priv, &vm->scratch_page); | |
8776f02b MK |
2014 | } |
2015 | ||
061dd493 | 2016 | static void gen6_ppgtt_cleanup(struct i915_address_space *vm) |
a00d825d | 2017 | { |
e5716f55 | 2018 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
731f74c5 | 2019 | struct i915_page_directory *pd = &ppgtt->pd; |
49d73912 | 2020 | struct drm_i915_private *dev_priv = vm->i915; |
09942c65 MT |
2021 | struct i915_page_table *pt; |
2022 | uint32_t pde; | |
4933d519 | 2023 | |
061dd493 DV |
2024 | drm_mm_remove_node(&ppgtt->node); |
2025 | ||
731f74c5 | 2026 | gen6_for_all_pdes(pt, pd, pde) |
79ab9370 | 2027 | if (pt != vm->scratch_pt) |
275a991c | 2028 | free_pt(dev_priv, pt); |
06fda602 | 2029 | |
8776f02b | 2030 | gen6_free_scratch(vm); |
3440d265 DV |
2031 | } |
2032 | ||
b146520f | 2033 | static int gen6_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt) |
3440d265 | 2034 | { |
8776f02b | 2035 | struct i915_address_space *vm = &ppgtt->base; |
49d73912 | 2036 | struct drm_i915_private *dev_priv = ppgtt->base.i915; |
72e96d64 | 2037 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
b146520f | 2038 | int ret; |
1d2a314c | 2039 | |
c8d4c0d6 BW |
2040 | /* PPGTT PDEs reside in the GGTT and consists of 512 entries. The |
2041 | * allocator works in address space sizes, so it's multiplied by page | |
2042 | * size. We allocate at the top of the GTT to avoid fragmentation. | |
2043 | */ | |
72e96d64 | 2044 | BUG_ON(!drm_mm_initialized(&ggtt->base.mm)); |
4933d519 | 2045 | |
8776f02b MK |
2046 | ret = gen6_init_scratch(vm); |
2047 | if (ret) | |
2048 | return ret; | |
4933d519 | 2049 | |
e007b19d CW |
2050 | ret = i915_gem_gtt_insert(&ggtt->base, &ppgtt->node, |
2051 | GEN6_PD_SIZE, GEN6_PD_ALIGN, | |
2052 | I915_COLOR_UNEVICTABLE, | |
2053 | 0, ggtt->base.total, | |
2054 | PIN_HIGH); | |
c8c26622 | 2055 | if (ret) |
678d96fb BW |
2056 | goto err_out; |
2057 | ||
72e96d64 | 2058 | if (ppgtt->node.start < ggtt->mappable_end) |
c8d4c0d6 | 2059 | DRM_DEBUG("Forced to use aperture for PDEs\n"); |
1d2a314c | 2060 | |
c8c26622 | 2061 | return 0; |
678d96fb BW |
2062 | |
2063 | err_out: | |
8776f02b | 2064 | gen6_free_scratch(vm); |
678d96fb | 2065 | return ret; |
b146520f BW |
2066 | } |
2067 | ||
b146520f BW |
2068 | static int gen6_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt) |
2069 | { | |
2f2cf682 | 2070 | return gen6_ppgtt_allocate_page_directories(ppgtt); |
4933d519 | 2071 | } |
06dc68d6 | 2072 | |
4933d519 MT |
2073 | static void gen6_scratch_va_range(struct i915_hw_ppgtt *ppgtt, |
2074 | uint64_t start, uint64_t length) | |
2075 | { | |
ec565b3c | 2076 | struct i915_page_table *unused; |
731f74c5 | 2077 | uint32_t pde; |
1d2a314c | 2078 | |
731f74c5 | 2079 | gen6_for_each_pde(unused, &ppgtt->pd, start, length, pde) |
79ab9370 | 2080 | ppgtt->pd.page_table[pde] = ppgtt->base.scratch_pt; |
b146520f BW |
2081 | } |
2082 | ||
5c5f6457 | 2083 | static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt) |
b146520f | 2084 | { |
49d73912 | 2085 | struct drm_i915_private *dev_priv = ppgtt->base.i915; |
72e96d64 | 2086 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
b146520f BW |
2087 | int ret; |
2088 | ||
72e96d64 | 2089 | ppgtt->base.pte_encode = ggtt->base.pte_encode; |
5db94019 | 2090 | if (intel_vgpu_active(dev_priv) || IS_GEN6(dev_priv)) |
b146520f | 2091 | ppgtt->switch_mm = gen6_mm_switch; |
772c2a51 | 2092 | else if (IS_HASWELL(dev_priv)) |
b146520f | 2093 | ppgtt->switch_mm = hsw_mm_switch; |
5db94019 | 2094 | else if (IS_GEN7(dev_priv)) |
b146520f | 2095 | ppgtt->switch_mm = gen7_mm_switch; |
8eb95204 | 2096 | else |
b146520f BW |
2097 | BUG(); |
2098 | ||
2099 | ret = gen6_ppgtt_alloc(ppgtt); | |
2100 | if (ret) | |
2101 | return ret; | |
2102 | ||
5c5f6457 | 2103 | ppgtt->base.allocate_va_range = gen6_alloc_va_range; |
b146520f BW |
2104 | ppgtt->base.clear_range = gen6_ppgtt_clear_range; |
2105 | ppgtt->base.insert_entries = gen6_ppgtt_insert_entries; | |
777dc5bb DV |
2106 | ppgtt->base.unbind_vma = ppgtt_unbind_vma; |
2107 | ppgtt->base.bind_vma = ppgtt_bind_vma; | |
b146520f | 2108 | ppgtt->base.cleanup = gen6_ppgtt_cleanup; |
b146520f | 2109 | ppgtt->base.start = 0; |
09942c65 | 2110 | ppgtt->base.total = I915_PDES * GEN6_PTES * PAGE_SIZE; |
87d60b63 | 2111 | ppgtt->debug_dump = gen6_dump_ppgtt; |
1d2a314c | 2112 | |
44159ddb | 2113 | ppgtt->pd.base.ggtt_offset = |
07749ef3 | 2114 | ppgtt->node.start / PAGE_SIZE * sizeof(gen6_pte_t); |
1d2a314c | 2115 | |
72e96d64 | 2116 | ppgtt->pd_addr = (gen6_pte_t __iomem *)ggtt->gsm + |
44159ddb | 2117 | ppgtt->pd.base.ggtt_offset / sizeof(gen6_pte_t); |
678d96fb | 2118 | |
5c5f6457 | 2119 | gen6_scratch_va_range(ppgtt, 0, ppgtt->base.total); |
1d2a314c | 2120 | |
678d96fb BW |
2121 | gen6_write_page_range(dev_priv, &ppgtt->pd, 0, ppgtt->base.total); |
2122 | ||
440fd528 | 2123 | DRM_DEBUG_DRIVER("Allocated pde space (%lldM) at GTT entry: %llx\n", |
b146520f BW |
2124 | ppgtt->node.size >> 20, |
2125 | ppgtt->node.start / PAGE_SIZE); | |
3440d265 | 2126 | |
fa76da34 | 2127 | DRM_DEBUG("Adding PPGTT at offset %x\n", |
44159ddb | 2128 | ppgtt->pd.base.ggtt_offset << 10); |
fa76da34 | 2129 | |
b146520f | 2130 | return 0; |
3440d265 DV |
2131 | } |
2132 | ||
2bfa996e CW |
2133 | static int __hw_ppgtt_init(struct i915_hw_ppgtt *ppgtt, |
2134 | struct drm_i915_private *dev_priv) | |
3440d265 | 2135 | { |
49d73912 | 2136 | ppgtt->base.i915 = dev_priv; |
3440d265 | 2137 | |
2bfa996e | 2138 | if (INTEL_INFO(dev_priv)->gen < 8) |
5c5f6457 | 2139 | return gen6_ppgtt_init(ppgtt); |
3ed124b2 | 2140 | else |
d7b2633d | 2141 | return gen8_ppgtt_init(ppgtt); |
fa76da34 | 2142 | } |
c114f76a | 2143 | |
a2cad9df | 2144 | static void i915_address_space_init(struct i915_address_space *vm, |
80b204bc CW |
2145 | struct drm_i915_private *dev_priv, |
2146 | const char *name) | |
a2cad9df | 2147 | { |
80b204bc | 2148 | i915_gem_timeline_init(dev_priv, &vm->timeline, name); |
a2cad9df | 2149 | drm_mm_init(&vm->mm, vm->start, vm->total); |
a2cad9df MW |
2150 | INIT_LIST_HEAD(&vm->active_list); |
2151 | INIT_LIST_HEAD(&vm->inactive_list); | |
50e046b6 | 2152 | INIT_LIST_HEAD(&vm->unbound_list); |
a2cad9df MW |
2153 | list_add_tail(&vm->global_link, &dev_priv->vm_list); |
2154 | } | |
2155 | ||
ed9724dd MA |
2156 | static void i915_address_space_fini(struct i915_address_space *vm) |
2157 | { | |
2158 | i915_gem_timeline_fini(&vm->timeline); | |
2159 | drm_mm_takedown(&vm->mm); | |
2160 | list_del(&vm->global_link); | |
2161 | } | |
2162 | ||
c6be607a | 2163 | static void gtt_write_workarounds(struct drm_i915_private *dev_priv) |
d5165ebd | 2164 | { |
d5165ebd TG |
2165 | /* This function is for gtt related workarounds. This function is |
2166 | * called on driver load and after a GPU reset, so you can place | |
2167 | * workarounds here even if they get overwritten by GPU reset. | |
2168 | */ | |
2169 | /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt */ | |
8652744b | 2170 | if (IS_BROADWELL(dev_priv)) |
d5165ebd | 2171 | I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW); |
920a14b2 | 2172 | else if (IS_CHERRYVIEW(dev_priv)) |
d5165ebd | 2173 | I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV); |
d9486e65 | 2174 | else if (IS_SKYLAKE(dev_priv)) |
d5165ebd | 2175 | I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL); |
e2d214ae | 2176 | else if (IS_BROXTON(dev_priv)) |
d5165ebd TG |
2177 | I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT); |
2178 | } | |
2179 | ||
2bfa996e CW |
2180 | static int i915_ppgtt_init(struct i915_hw_ppgtt *ppgtt, |
2181 | struct drm_i915_private *dev_priv, | |
80b204bc CW |
2182 | struct drm_i915_file_private *file_priv, |
2183 | const char *name) | |
fa76da34 | 2184 | { |
2bfa996e | 2185 | int ret; |
3ed124b2 | 2186 | |
2bfa996e | 2187 | ret = __hw_ppgtt_init(ppgtt, dev_priv); |
fa76da34 | 2188 | if (ret == 0) { |
c7c48dfd | 2189 | kref_init(&ppgtt->ref); |
80b204bc | 2190 | i915_address_space_init(&ppgtt->base, dev_priv, name); |
2bfa996e | 2191 | ppgtt->base.file = file_priv; |
93bd8649 | 2192 | } |
1d2a314c DV |
2193 | |
2194 | return ret; | |
2195 | } | |
2196 | ||
c6be607a | 2197 | int i915_ppgtt_init_hw(struct drm_i915_private *dev_priv) |
82460d97 | 2198 | { |
c6be607a | 2199 | gtt_write_workarounds(dev_priv); |
d5165ebd | 2200 | |
671b5013 TD |
2201 | /* In the case of execlists, PPGTT is enabled by the context descriptor |
2202 | * and the PDPs are contained within the context itself. We don't | |
2203 | * need to do anything here. */ | |
2204 | if (i915.enable_execlists) | |
2205 | return 0; | |
2206 | ||
c6be607a | 2207 | if (!USES_PPGTT(dev_priv)) |
82460d97 DV |
2208 | return 0; |
2209 | ||
5db94019 | 2210 | if (IS_GEN6(dev_priv)) |
c6be607a | 2211 | gen6_ppgtt_enable(dev_priv); |
5db94019 | 2212 | else if (IS_GEN7(dev_priv)) |
c6be607a TU |
2213 | gen7_ppgtt_enable(dev_priv); |
2214 | else if (INTEL_GEN(dev_priv) >= 8) | |
2215 | gen8_ppgtt_enable(dev_priv); | |
82460d97 | 2216 | else |
c6be607a | 2217 | MISSING_CASE(INTEL_GEN(dev_priv)); |
82460d97 | 2218 | |
4ad2fd88 JH |
2219 | return 0; |
2220 | } | |
1d2a314c | 2221 | |
4d884705 | 2222 | struct i915_hw_ppgtt * |
2bfa996e | 2223 | i915_ppgtt_create(struct drm_i915_private *dev_priv, |
80b204bc CW |
2224 | struct drm_i915_file_private *fpriv, |
2225 | const char *name) | |
4d884705 DV |
2226 | { |
2227 | struct i915_hw_ppgtt *ppgtt; | |
2228 | int ret; | |
2229 | ||
2230 | ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL); | |
2231 | if (!ppgtt) | |
2232 | return ERR_PTR(-ENOMEM); | |
2233 | ||
80b204bc | 2234 | ret = i915_ppgtt_init(ppgtt, dev_priv, fpriv, name); |
4d884705 DV |
2235 | if (ret) { |
2236 | kfree(ppgtt); | |
2237 | return ERR_PTR(ret); | |
2238 | } | |
2239 | ||
198c974d DCS |
2240 | trace_i915_ppgtt_create(&ppgtt->base); |
2241 | ||
4d884705 DV |
2242 | return ppgtt; |
2243 | } | |
2244 | ||
ed9724dd | 2245 | void i915_ppgtt_release(struct kref *kref) |
ee960be7 DV |
2246 | { |
2247 | struct i915_hw_ppgtt *ppgtt = | |
2248 | container_of(kref, struct i915_hw_ppgtt, ref); | |
2249 | ||
198c974d DCS |
2250 | trace_i915_ppgtt_release(&ppgtt->base); |
2251 | ||
50e046b6 | 2252 | /* vmas should already be unbound and destroyed */ |
ee960be7 DV |
2253 | WARN_ON(!list_empty(&ppgtt->base.active_list)); |
2254 | WARN_ON(!list_empty(&ppgtt->base.inactive_list)); | |
50e046b6 | 2255 | WARN_ON(!list_empty(&ppgtt->base.unbound_list)); |
ee960be7 | 2256 | |
ed9724dd | 2257 | i915_address_space_fini(&ppgtt->base); |
19dd120c | 2258 | |
ee960be7 DV |
2259 | ppgtt->base.cleanup(&ppgtt->base); |
2260 | kfree(ppgtt); | |
2261 | } | |
1d2a314c | 2262 | |
a81cc00c BW |
2263 | /* Certain Gen5 chipsets require require idling the GPU before |
2264 | * unmapping anything from the GTT when VT-d is enabled. | |
2265 | */ | |
97d6d7ab | 2266 | static bool needs_idle_maps(struct drm_i915_private *dev_priv) |
a81cc00c BW |
2267 | { |
2268 | #ifdef CONFIG_INTEL_IOMMU | |
2269 | /* Query intel_iommu to see if we need the workaround. Presumably that | |
2270 | * was loaded first. | |
2271 | */ | |
97d6d7ab | 2272 | if (IS_GEN5(dev_priv) && IS_MOBILE(dev_priv) && intel_iommu_gfx_mapped) |
a81cc00c BW |
2273 | return true; |
2274 | #endif | |
2275 | return false; | |
2276 | } | |
2277 | ||
dc97997a | 2278 | void i915_check_and_clear_faults(struct drm_i915_private *dev_priv) |
828c7908 | 2279 | { |
e2f80391 | 2280 | struct intel_engine_cs *engine; |
3b3f1650 | 2281 | enum intel_engine_id id; |
828c7908 | 2282 | |
dc97997a | 2283 | if (INTEL_INFO(dev_priv)->gen < 6) |
828c7908 BW |
2284 | return; |
2285 | ||
3b3f1650 | 2286 | for_each_engine(engine, dev_priv, id) { |
828c7908 | 2287 | u32 fault_reg; |
e2f80391 | 2288 | fault_reg = I915_READ(RING_FAULT_REG(engine)); |
828c7908 BW |
2289 | if (fault_reg & RING_FAULT_VALID) { |
2290 | DRM_DEBUG_DRIVER("Unexpected fault\n" | |
59a5d290 | 2291 | "\tAddr: 0x%08lx\n" |
828c7908 BW |
2292 | "\tAddress space: %s\n" |
2293 | "\tSource ID: %d\n" | |
2294 | "\tType: %d\n", | |
2295 | fault_reg & PAGE_MASK, | |
2296 | fault_reg & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT", | |
2297 | RING_FAULT_SRCID(fault_reg), | |
2298 | RING_FAULT_FAULT_TYPE(fault_reg)); | |
e2f80391 | 2299 | I915_WRITE(RING_FAULT_REG(engine), |
828c7908 BW |
2300 | fault_reg & ~RING_FAULT_VALID); |
2301 | } | |
2302 | } | |
3b3f1650 AG |
2303 | |
2304 | /* Engine specific init may not have been done till this point. */ | |
2305 | if (dev_priv->engine[RCS]) | |
2306 | POSTING_READ(RING_FAULT_REG(dev_priv->engine[RCS])); | |
828c7908 BW |
2307 | } |
2308 | ||
91e56499 CW |
2309 | static void i915_ggtt_flush(struct drm_i915_private *dev_priv) |
2310 | { | |
2d1fe073 | 2311 | if (INTEL_INFO(dev_priv)->gen < 6) { |
91e56499 CW |
2312 | intel_gtt_chipset_flush(); |
2313 | } else { | |
2314 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
2315 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
2316 | } | |
2317 | } | |
2318 | ||
275a991c | 2319 | void i915_gem_suspend_gtt_mappings(struct drm_i915_private *dev_priv) |
828c7908 | 2320 | { |
72e96d64 | 2321 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
828c7908 BW |
2322 | |
2323 | /* Don't bother messing with faults pre GEN6 as we have little | |
2324 | * documentation supporting that it's a good idea. | |
2325 | */ | |
275a991c | 2326 | if (INTEL_GEN(dev_priv) < 6) |
828c7908 BW |
2327 | return; |
2328 | ||
dc97997a | 2329 | i915_check_and_clear_faults(dev_priv); |
828c7908 | 2330 | |
4fb84d99 | 2331 | ggtt->base.clear_range(&ggtt->base, ggtt->base.start, ggtt->base.total); |
91e56499 CW |
2332 | |
2333 | i915_ggtt_flush(dev_priv); | |
828c7908 BW |
2334 | } |
2335 | ||
03ac84f1 CW |
2336 | int i915_gem_gtt_prepare_pages(struct drm_i915_gem_object *obj, |
2337 | struct sg_table *pages) | |
7c2e6fdf | 2338 | { |
1a292fa5 CW |
2339 | do { |
2340 | if (dma_map_sg(&obj->base.dev->pdev->dev, | |
2341 | pages->sgl, pages->nents, | |
2342 | PCI_DMA_BIDIRECTIONAL)) | |
2343 | return 0; | |
2344 | ||
2345 | /* If the DMA remap fails, one cause can be that we have | |
2346 | * too many objects pinned in a small remapping table, | |
2347 | * such as swiotlb. Incrementally purge all other objects and | |
2348 | * try again - if there are no more pages to remove from | |
2349 | * the DMA remapper, i915_gem_shrink will return 0. | |
2350 | */ | |
2351 | GEM_BUG_ON(obj->mm.pages == pages); | |
2352 | } while (i915_gem_shrink(to_i915(obj->base.dev), | |
2353 | obj->base.size >> PAGE_SHIFT, | |
2354 | I915_SHRINK_BOUND | | |
2355 | I915_SHRINK_UNBOUND | | |
2356 | I915_SHRINK_ACTIVE)); | |
9da3da66 | 2357 | |
03ac84f1 | 2358 | return -ENOSPC; |
7c2e6fdf DV |
2359 | } |
2360 | ||
2c642b07 | 2361 | static void gen8_set_pte(void __iomem *addr, gen8_pte_t pte) |
94ec8f61 | 2362 | { |
94ec8f61 | 2363 | writeq(pte, addr); |
94ec8f61 BW |
2364 | } |
2365 | ||
d6473f56 CW |
2366 | static void gen8_ggtt_insert_page(struct i915_address_space *vm, |
2367 | dma_addr_t addr, | |
2368 | uint64_t offset, | |
2369 | enum i915_cache_level level, | |
2370 | u32 unused) | |
2371 | { | |
49d73912 | 2372 | struct drm_i915_private *dev_priv = vm->i915; |
d6473f56 CW |
2373 | gen8_pte_t __iomem *pte = |
2374 | (gen8_pte_t __iomem *)dev_priv->ggtt.gsm + | |
2375 | (offset >> PAGE_SHIFT); | |
d6473f56 | 2376 | |
4fb84d99 | 2377 | gen8_set_pte(pte, gen8_pte_encode(addr, level)); |
d6473f56 CW |
2378 | |
2379 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
2380 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
d6473f56 CW |
2381 | } |
2382 | ||
94ec8f61 BW |
2383 | static void gen8_ggtt_insert_entries(struct i915_address_space *vm, |
2384 | struct sg_table *st, | |
782f1495 | 2385 | uint64_t start, |
24f3a8cf | 2386 | enum i915_cache_level level, u32 unused) |
94ec8f61 | 2387 | { |
49d73912 | 2388 | struct drm_i915_private *dev_priv = vm->i915; |
ce7fda2e | 2389 | struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm); |
85d1225e DG |
2390 | struct sgt_iter sgt_iter; |
2391 | gen8_pte_t __iomem *gtt_entries; | |
2392 | gen8_pte_t gtt_entry; | |
2393 | dma_addr_t addr; | |
85d1225e | 2394 | int i = 0; |
be69459a | 2395 | |
85d1225e DG |
2396 | gtt_entries = (gen8_pte_t __iomem *)ggtt->gsm + (start >> PAGE_SHIFT); |
2397 | ||
2398 | for_each_sgt_dma(addr, sgt_iter, st) { | |
4fb84d99 | 2399 | gtt_entry = gen8_pte_encode(addr, level); |
85d1225e | 2400 | gen8_set_pte(>t_entries[i++], gtt_entry); |
94ec8f61 BW |
2401 | } |
2402 | ||
2403 | /* | |
2404 | * XXX: This serves as a posting read to make sure that the PTE has | |
2405 | * actually been updated. There is some concern that even though | |
2406 | * registers and PTEs are within the same BAR that they are potentially | |
2407 | * of NUMA access patterns. Therefore, even with the way we assume | |
2408 | * hardware should work, we must keep this posting read for paranoia. | |
2409 | */ | |
2410 | if (i != 0) | |
85d1225e | 2411 | WARN_ON(readq(>t_entries[i-1]) != gtt_entry); |
94ec8f61 | 2412 | |
94ec8f61 BW |
2413 | /* This next bit makes the above posting read even more important. We |
2414 | * want to flush the TLBs only after we're certain all the PTE updates | |
2415 | * have finished. | |
2416 | */ | |
2417 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
2418 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
94ec8f61 BW |
2419 | } |
2420 | ||
c140330b CW |
2421 | struct insert_entries { |
2422 | struct i915_address_space *vm; | |
2423 | struct sg_table *st; | |
2424 | uint64_t start; | |
2425 | enum i915_cache_level level; | |
2426 | u32 flags; | |
2427 | }; | |
2428 | ||
2429 | static int gen8_ggtt_insert_entries__cb(void *_arg) | |
2430 | { | |
2431 | struct insert_entries *arg = _arg; | |
2432 | gen8_ggtt_insert_entries(arg->vm, arg->st, | |
2433 | arg->start, arg->level, arg->flags); | |
2434 | return 0; | |
2435 | } | |
2436 | ||
2437 | static void gen8_ggtt_insert_entries__BKL(struct i915_address_space *vm, | |
2438 | struct sg_table *st, | |
2439 | uint64_t start, | |
2440 | enum i915_cache_level level, | |
2441 | u32 flags) | |
2442 | { | |
2443 | struct insert_entries arg = { vm, st, start, level, flags }; | |
2444 | stop_machine(gen8_ggtt_insert_entries__cb, &arg, NULL); | |
2445 | } | |
2446 | ||
d6473f56 CW |
2447 | static void gen6_ggtt_insert_page(struct i915_address_space *vm, |
2448 | dma_addr_t addr, | |
2449 | uint64_t offset, | |
2450 | enum i915_cache_level level, | |
2451 | u32 flags) | |
2452 | { | |
49d73912 | 2453 | struct drm_i915_private *dev_priv = vm->i915; |
d6473f56 CW |
2454 | gen6_pte_t __iomem *pte = |
2455 | (gen6_pte_t __iomem *)dev_priv->ggtt.gsm + | |
2456 | (offset >> PAGE_SHIFT); | |
d6473f56 | 2457 | |
4fb84d99 | 2458 | iowrite32(vm->pte_encode(addr, level, flags), pte); |
d6473f56 CW |
2459 | |
2460 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
2461 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
d6473f56 CW |
2462 | } |
2463 | ||
e76e9aeb BW |
2464 | /* |
2465 | * Binds an object into the global gtt with the specified cache level. The object | |
2466 | * will be accessible to the GPU via commands whose operands reference offsets | |
2467 | * within the global GTT as well as accessible by the GPU through the GMADR | |
2468 | * mapped BAR (dev_priv->mm.gtt->gtt). | |
2469 | */ | |
853ba5d2 | 2470 | static void gen6_ggtt_insert_entries(struct i915_address_space *vm, |
7faf1ab2 | 2471 | struct sg_table *st, |
782f1495 | 2472 | uint64_t start, |
24f3a8cf | 2473 | enum i915_cache_level level, u32 flags) |
e76e9aeb | 2474 | { |
49d73912 | 2475 | struct drm_i915_private *dev_priv = vm->i915; |
ce7fda2e | 2476 | struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm); |
85d1225e DG |
2477 | struct sgt_iter sgt_iter; |
2478 | gen6_pte_t __iomem *gtt_entries; | |
2479 | gen6_pte_t gtt_entry; | |
2480 | dma_addr_t addr; | |
85d1225e | 2481 | int i = 0; |
be69459a | 2482 | |
85d1225e DG |
2483 | gtt_entries = (gen6_pte_t __iomem *)ggtt->gsm + (start >> PAGE_SHIFT); |
2484 | ||
2485 | for_each_sgt_dma(addr, sgt_iter, st) { | |
4fb84d99 | 2486 | gtt_entry = vm->pte_encode(addr, level, flags); |
85d1225e | 2487 | iowrite32(gtt_entry, >t_entries[i++]); |
e76e9aeb BW |
2488 | } |
2489 | ||
e76e9aeb BW |
2490 | /* XXX: This serves as a posting read to make sure that the PTE has |
2491 | * actually been updated. There is some concern that even though | |
2492 | * registers and PTEs are within the same BAR that they are potentially | |
2493 | * of NUMA access patterns. Therefore, even with the way we assume | |
2494 | * hardware should work, we must keep this posting read for paranoia. | |
2495 | */ | |
85d1225e DG |
2496 | if (i != 0) |
2497 | WARN_ON(readl(>t_entries[i-1]) != gtt_entry); | |
0f9b91c7 BW |
2498 | |
2499 | /* This next bit makes the above posting read even more important. We | |
2500 | * want to flush the TLBs only after we're certain all the PTE updates | |
2501 | * have finished. | |
2502 | */ | |
2503 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
2504 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
e76e9aeb BW |
2505 | } |
2506 | ||
f7770bfd | 2507 | static void nop_clear_range(struct i915_address_space *vm, |
4fb84d99 | 2508 | uint64_t start, uint64_t length) |
f7770bfd CW |
2509 | { |
2510 | } | |
2511 | ||
94ec8f61 | 2512 | static void gen8_ggtt_clear_range(struct i915_address_space *vm, |
4fb84d99 | 2513 | uint64_t start, uint64_t length) |
94ec8f61 | 2514 | { |
ce7fda2e | 2515 | struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm); |
782f1495 BW |
2516 | unsigned first_entry = start >> PAGE_SHIFT; |
2517 | unsigned num_entries = length >> PAGE_SHIFT; | |
07749ef3 | 2518 | gen8_pte_t scratch_pte, __iomem *gtt_base = |
72e96d64 JL |
2519 | (gen8_pte_t __iomem *)ggtt->gsm + first_entry; |
2520 | const int max_entries = ggtt_total_entries(ggtt) - first_entry; | |
94ec8f61 BW |
2521 | int i; |
2522 | ||
2523 | if (WARN(num_entries > max_entries, | |
2524 | "First entry = %d; Num entries = %d (max=%d)\n", | |
2525 | first_entry, num_entries, max_entries)) | |
2526 | num_entries = max_entries; | |
2527 | ||
8bcdd0f7 | 2528 | scratch_pte = gen8_pte_encode(vm->scratch_page.daddr, |
4fb84d99 | 2529 | I915_CACHE_LLC); |
94ec8f61 BW |
2530 | for (i = 0; i < num_entries; i++) |
2531 | gen8_set_pte(>t_base[i], scratch_pte); | |
2532 | readl(gtt_base); | |
2533 | } | |
2534 | ||
853ba5d2 | 2535 | static void gen6_ggtt_clear_range(struct i915_address_space *vm, |
782f1495 | 2536 | uint64_t start, |
4fb84d99 | 2537 | uint64_t length) |
7faf1ab2 | 2538 | { |
ce7fda2e | 2539 | struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm); |
782f1495 BW |
2540 | unsigned first_entry = start >> PAGE_SHIFT; |
2541 | unsigned num_entries = length >> PAGE_SHIFT; | |
07749ef3 | 2542 | gen6_pte_t scratch_pte, __iomem *gtt_base = |
72e96d64 JL |
2543 | (gen6_pte_t __iomem *)ggtt->gsm + first_entry; |
2544 | const int max_entries = ggtt_total_entries(ggtt) - first_entry; | |
7faf1ab2 DV |
2545 | int i; |
2546 | ||
2547 | if (WARN(num_entries > max_entries, | |
2548 | "First entry = %d; Num entries = %d (max=%d)\n", | |
2549 | first_entry, num_entries, max_entries)) | |
2550 | num_entries = max_entries; | |
2551 | ||
8bcdd0f7 | 2552 | scratch_pte = vm->pte_encode(vm->scratch_page.daddr, |
4fb84d99 | 2553 | I915_CACHE_LLC, 0); |
828c7908 | 2554 | |
7faf1ab2 DV |
2555 | for (i = 0; i < num_entries; i++) |
2556 | iowrite32(scratch_pte, >t_base[i]); | |
2557 | readl(gtt_base); | |
2558 | } | |
2559 | ||
d6473f56 CW |
2560 | static void i915_ggtt_insert_page(struct i915_address_space *vm, |
2561 | dma_addr_t addr, | |
2562 | uint64_t offset, | |
2563 | enum i915_cache_level cache_level, | |
2564 | u32 unused) | |
2565 | { | |
d6473f56 CW |
2566 | unsigned int flags = (cache_level == I915_CACHE_NONE) ? |
2567 | AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY; | |
d6473f56 CW |
2568 | |
2569 | intel_gtt_insert_page(addr, offset >> PAGE_SHIFT, flags); | |
d6473f56 CW |
2570 | } |
2571 | ||
d369d2d9 DV |
2572 | static void i915_ggtt_insert_entries(struct i915_address_space *vm, |
2573 | struct sg_table *pages, | |
2574 | uint64_t start, | |
2575 | enum i915_cache_level cache_level, u32 unused) | |
7faf1ab2 DV |
2576 | { |
2577 | unsigned int flags = (cache_level == I915_CACHE_NONE) ? | |
2578 | AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY; | |
2579 | ||
d369d2d9 | 2580 | intel_gtt_insert_sg_entries(pages, start >> PAGE_SHIFT, flags); |
0875546c | 2581 | |
7faf1ab2 DV |
2582 | } |
2583 | ||
853ba5d2 | 2584 | static void i915_ggtt_clear_range(struct i915_address_space *vm, |
782f1495 | 2585 | uint64_t start, |
4fb84d99 | 2586 | uint64_t length) |
7faf1ab2 | 2587 | { |
2eedfc7d | 2588 | intel_gtt_clear_range(start >> PAGE_SHIFT, length >> PAGE_SHIFT); |
7faf1ab2 DV |
2589 | } |
2590 | ||
70b9f6f8 DV |
2591 | static int ggtt_bind_vma(struct i915_vma *vma, |
2592 | enum i915_cache_level cache_level, | |
2593 | u32 flags) | |
0a878716 | 2594 | { |
49d73912 | 2595 | struct drm_i915_private *i915 = vma->vm->i915; |
0a878716 DV |
2596 | struct drm_i915_gem_object *obj = vma->obj; |
2597 | u32 pte_flags = 0; | |
2598 | int ret; | |
2599 | ||
2600 | ret = i915_get_ggtt_vma_pages(vma); | |
2601 | if (ret) | |
2602 | return ret; | |
2603 | ||
2604 | /* Currently applicable only to VLV */ | |
2605 | if (obj->gt_ro) | |
2606 | pte_flags |= PTE_READ_ONLY; | |
2607 | ||
9c870d03 | 2608 | intel_runtime_pm_get(i915); |
247177dd | 2609 | vma->vm->insert_entries(vma->vm, vma->pages, vma->node.start, |
0a878716 | 2610 | cache_level, pte_flags); |
9c870d03 | 2611 | intel_runtime_pm_put(i915); |
0a878716 DV |
2612 | |
2613 | /* | |
2614 | * Without aliasing PPGTT there's no difference between | |
2615 | * GLOBAL/LOCAL_BIND, it's all the same ptes. Hence unconditionally | |
2616 | * upgrade to both bound if we bind either to avoid double-binding. | |
2617 | */ | |
3272db53 | 2618 | vma->flags |= I915_VMA_GLOBAL_BIND | I915_VMA_LOCAL_BIND; |
0a878716 DV |
2619 | |
2620 | return 0; | |
2621 | } | |
2622 | ||
2623 | static int aliasing_gtt_bind_vma(struct i915_vma *vma, | |
2624 | enum i915_cache_level cache_level, | |
2625 | u32 flags) | |
d5bd1449 | 2626 | { |
49d73912 | 2627 | struct drm_i915_private *i915 = vma->vm->i915; |
321d178e | 2628 | u32 pte_flags; |
70b9f6f8 DV |
2629 | int ret; |
2630 | ||
2631 | ret = i915_get_ggtt_vma_pages(vma); | |
2632 | if (ret) | |
2633 | return ret; | |
7faf1ab2 | 2634 | |
24f3a8cf | 2635 | /* Currently applicable only to VLV */ |
321d178e CW |
2636 | pte_flags = 0; |
2637 | if (vma->obj->gt_ro) | |
f329f5f6 | 2638 | pte_flags |= PTE_READ_ONLY; |
24f3a8cf | 2639 | |
ec7adb6e | 2640 | |
3272db53 | 2641 | if (flags & I915_VMA_GLOBAL_BIND) { |
9c870d03 | 2642 | intel_runtime_pm_get(i915); |
321d178e | 2643 | vma->vm->insert_entries(vma->vm, |
247177dd | 2644 | vma->pages, vma->node.start, |
0875546c | 2645 | cache_level, pte_flags); |
9c870d03 | 2646 | intel_runtime_pm_put(i915); |
6f65e29a | 2647 | } |
d5bd1449 | 2648 | |
3272db53 | 2649 | if (flags & I915_VMA_LOCAL_BIND) { |
9c870d03 | 2650 | struct i915_hw_ppgtt *appgtt = i915->mm.aliasing_ppgtt; |
321d178e | 2651 | appgtt->base.insert_entries(&appgtt->base, |
247177dd | 2652 | vma->pages, vma->node.start, |
f329f5f6 | 2653 | cache_level, pte_flags); |
6f65e29a | 2654 | } |
70b9f6f8 DV |
2655 | |
2656 | return 0; | |
d5bd1449 CW |
2657 | } |
2658 | ||
6f65e29a | 2659 | static void ggtt_unbind_vma(struct i915_vma *vma) |
74163907 | 2660 | { |
49d73912 | 2661 | struct drm_i915_private *i915 = vma->vm->i915; |
9c870d03 | 2662 | struct i915_hw_ppgtt *appgtt = i915->mm.aliasing_ppgtt; |
de180033 | 2663 | const u64 size = min(vma->size, vma->node.size); |
6f65e29a | 2664 | |
9c870d03 CW |
2665 | if (vma->flags & I915_VMA_GLOBAL_BIND) { |
2666 | intel_runtime_pm_get(i915); | |
782f1495 | 2667 | vma->vm->clear_range(vma->vm, |
4fb84d99 | 2668 | vma->node.start, size); |
9c870d03 CW |
2669 | intel_runtime_pm_put(i915); |
2670 | } | |
06615ee5 | 2671 | |
3272db53 | 2672 | if (vma->flags & I915_VMA_LOCAL_BIND && appgtt) |
6f65e29a | 2673 | appgtt->base.clear_range(&appgtt->base, |
4fb84d99 | 2674 | vma->node.start, size); |
74163907 DV |
2675 | } |
2676 | ||
03ac84f1 CW |
2677 | void i915_gem_gtt_finish_pages(struct drm_i915_gem_object *obj, |
2678 | struct sg_table *pages) | |
7c2e6fdf | 2679 | { |
52a05c30 DW |
2680 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
2681 | struct device *kdev = &dev_priv->drm.pdev->dev; | |
307dc25b | 2682 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
5c042287 | 2683 | |
307dc25b | 2684 | if (unlikely(ggtt->do_idle_maps)) { |
22dd3bb9 | 2685 | if (i915_gem_wait_for_idle(dev_priv, I915_WAIT_LOCKED)) { |
307dc25b CW |
2686 | DRM_ERROR("Failed to wait for idle; VT'd may hang.\n"); |
2687 | /* Wait a bit, in hopes it avoids the hang */ | |
2688 | udelay(10); | |
2689 | } | |
2690 | } | |
5c042287 | 2691 | |
03ac84f1 | 2692 | dma_unmap_sg(kdev, pages->sgl, pages->nents, PCI_DMA_BIDIRECTIONAL); |
7c2e6fdf | 2693 | } |
644ec02b | 2694 | |
45b186f1 | 2695 | static void i915_gtt_color_adjust(const struct drm_mm_node *node, |
42d6ab48 | 2696 | unsigned long color, |
440fd528 TR |
2697 | u64 *start, |
2698 | u64 *end) | |
42d6ab48 CW |
2699 | { |
2700 | if (node->color != color) | |
f51455d4 | 2701 | *start += I915_GTT_PAGE_SIZE; |
42d6ab48 | 2702 | |
b44f97fd CW |
2703 | node = list_next_entry(node, node_list); |
2704 | if (node->allocated && node->color != color) | |
f51455d4 | 2705 | *end -= I915_GTT_PAGE_SIZE; |
42d6ab48 | 2706 | } |
fbe5d36e | 2707 | |
f6b9d5ca | 2708 | int i915_gem_init_ggtt(struct drm_i915_private *dev_priv) |
644ec02b | 2709 | { |
e78891ca BW |
2710 | /* Let GEM Manage all of the aperture. |
2711 | * | |
2712 | * However, leave one page at the end still bound to the scratch page. | |
2713 | * There are a number of places where the hardware apparently prefetches | |
2714 | * past the end of the object, and we've seen multiple hangs with the | |
2715 | * GPU head pointer stuck in a batchbuffer bound at the last page of the | |
2716 | * aperture. One page should be enough to keep any prefetching inside | |
2717 | * of the aperture. | |
2718 | */ | |
72e96d64 | 2719 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
ed2f3452 | 2720 | unsigned long hole_start, hole_end; |
95374d75 | 2721 | struct i915_hw_ppgtt *ppgtt; |
f6b9d5ca | 2722 | struct drm_mm_node *entry; |
fa76da34 | 2723 | int ret; |
644ec02b | 2724 | |
b02d22a3 ZW |
2725 | ret = intel_vgt_balloon(dev_priv); |
2726 | if (ret) | |
2727 | return ret; | |
5dda8fa3 | 2728 | |
95374d75 CW |
2729 | /* Reserve a mappable slot for our lockless error capture */ |
2730 | ret = drm_mm_insert_node_in_range_generic(&ggtt->base.mm, | |
2731 | &ggtt->error_capture, | |
f51455d4 | 2732 | PAGE_SIZE, 0, |
85fd4f58 | 2733 | I915_COLOR_UNEVICTABLE, |
95374d75 CW |
2734 | 0, ggtt->mappable_end, |
2735 | 0, 0); | |
2736 | if (ret) | |
2737 | return ret; | |
2738 | ||
ed2f3452 | 2739 | /* Clear any non-preallocated blocks */ |
72e96d64 | 2740 | drm_mm_for_each_hole(entry, &ggtt->base.mm, hole_start, hole_end) { |
ed2f3452 CW |
2741 | DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n", |
2742 | hole_start, hole_end); | |
72e96d64 | 2743 | ggtt->base.clear_range(&ggtt->base, hole_start, |
4fb84d99 | 2744 | hole_end - hole_start); |
ed2f3452 CW |
2745 | } |
2746 | ||
2747 | /* And finally clear the reserved guard page */ | |
f6b9d5ca | 2748 | ggtt->base.clear_range(&ggtt->base, |
4fb84d99 | 2749 | ggtt->base.total - PAGE_SIZE, PAGE_SIZE); |
6c5566a8 | 2750 | |
97d6d7ab | 2751 | if (USES_PPGTT(dev_priv) && !USES_FULL_PPGTT(dev_priv)) { |
fa76da34 | 2752 | ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL); |
95374d75 CW |
2753 | if (!ppgtt) { |
2754 | ret = -ENOMEM; | |
2755 | goto err; | |
2756 | } | |
fa76da34 | 2757 | |
2bfa996e | 2758 | ret = __hw_ppgtt_init(ppgtt, dev_priv); |
95374d75 CW |
2759 | if (ret) |
2760 | goto err_ppgtt; | |
5c5f6457 | 2761 | |
95374d75 | 2762 | if (ppgtt->base.allocate_va_range) { |
5c5f6457 DV |
2763 | ret = ppgtt->base.allocate_va_range(&ppgtt->base, 0, |
2764 | ppgtt->base.total); | |
95374d75 CW |
2765 | if (ret) |
2766 | goto err_ppgtt_cleanup; | |
4933d519 | 2767 | } |
fa76da34 | 2768 | |
5c5f6457 DV |
2769 | ppgtt->base.clear_range(&ppgtt->base, |
2770 | ppgtt->base.start, | |
4fb84d99 | 2771 | ppgtt->base.total); |
5c5f6457 | 2772 | |
fa76da34 | 2773 | dev_priv->mm.aliasing_ppgtt = ppgtt; |
72e96d64 JL |
2774 | WARN_ON(ggtt->base.bind_vma != ggtt_bind_vma); |
2775 | ggtt->base.bind_vma = aliasing_gtt_bind_vma; | |
fa76da34 DV |
2776 | } |
2777 | ||
6c5566a8 | 2778 | return 0; |
95374d75 CW |
2779 | |
2780 | err_ppgtt_cleanup: | |
2781 | ppgtt->base.cleanup(&ppgtt->base); | |
2782 | err_ppgtt: | |
2783 | kfree(ppgtt); | |
2784 | err: | |
2785 | drm_mm_remove_node(&ggtt->error_capture); | |
2786 | return ret; | |
e76e9aeb BW |
2787 | } |
2788 | ||
d85489d3 JL |
2789 | /** |
2790 | * i915_ggtt_cleanup_hw - Clean up GGTT hardware initialization | |
97d6d7ab | 2791 | * @dev_priv: i915 device |
d85489d3 | 2792 | */ |
97d6d7ab | 2793 | void i915_ggtt_cleanup_hw(struct drm_i915_private *dev_priv) |
90d0a0e8 | 2794 | { |
72e96d64 | 2795 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
90d0a0e8 | 2796 | |
70e32544 DV |
2797 | if (dev_priv->mm.aliasing_ppgtt) { |
2798 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
70e32544 | 2799 | ppgtt->base.cleanup(&ppgtt->base); |
cb7f2760 | 2800 | kfree(ppgtt); |
70e32544 DV |
2801 | } |
2802 | ||
97d6d7ab | 2803 | i915_gem_cleanup_stolen(&dev_priv->drm); |
a4eba47b | 2804 | |
95374d75 CW |
2805 | if (drm_mm_node_allocated(&ggtt->error_capture)) |
2806 | drm_mm_remove_node(&ggtt->error_capture); | |
2807 | ||
72e96d64 | 2808 | if (drm_mm_initialized(&ggtt->base.mm)) { |
b02d22a3 | 2809 | intel_vgt_deballoon(dev_priv); |
5dda8fa3 | 2810 | |
ed9724dd MA |
2811 | mutex_lock(&dev_priv->drm.struct_mutex); |
2812 | i915_address_space_fini(&ggtt->base); | |
2813 | mutex_unlock(&dev_priv->drm.struct_mutex); | |
90d0a0e8 DV |
2814 | } |
2815 | ||
72e96d64 | 2816 | ggtt->base.cleanup(&ggtt->base); |
f6b9d5ca CW |
2817 | |
2818 | arch_phys_wc_del(ggtt->mtrr); | |
f7bbe788 | 2819 | io_mapping_fini(&ggtt->mappable); |
90d0a0e8 | 2820 | } |
70e32544 | 2821 | |
2c642b07 | 2822 | static unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl) |
e76e9aeb BW |
2823 | { |
2824 | snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT; | |
2825 | snb_gmch_ctl &= SNB_GMCH_GGMS_MASK; | |
2826 | return snb_gmch_ctl << 20; | |
2827 | } | |
2828 | ||
2c642b07 | 2829 | static unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl) |
9459d252 BW |
2830 | { |
2831 | bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT; | |
2832 | bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK; | |
2833 | if (bdw_gmch_ctl) | |
2834 | bdw_gmch_ctl = 1 << bdw_gmch_ctl; | |
562d55d9 BW |
2835 | |
2836 | #ifdef CONFIG_X86_32 | |
2837 | /* Limit 32b platforms to a 2GB GGTT: 4 << 20 / pte size * PAGE_SIZE */ | |
2838 | if (bdw_gmch_ctl > 4) | |
2839 | bdw_gmch_ctl = 4; | |
2840 | #endif | |
2841 | ||
9459d252 BW |
2842 | return bdw_gmch_ctl << 20; |
2843 | } | |
2844 | ||
2c642b07 | 2845 | static unsigned int chv_get_total_gtt_size(u16 gmch_ctrl) |
d7f25f23 DL |
2846 | { |
2847 | gmch_ctrl >>= SNB_GMCH_GGMS_SHIFT; | |
2848 | gmch_ctrl &= SNB_GMCH_GGMS_MASK; | |
2849 | ||
2850 | if (gmch_ctrl) | |
2851 | return 1 << (20 + gmch_ctrl); | |
2852 | ||
2853 | return 0; | |
2854 | } | |
2855 | ||
2c642b07 | 2856 | static size_t gen6_get_stolen_size(u16 snb_gmch_ctl) |
e76e9aeb BW |
2857 | { |
2858 | snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT; | |
2859 | snb_gmch_ctl &= SNB_GMCH_GMS_MASK; | |
2860 | return snb_gmch_ctl << 25; /* 32 MB units */ | |
2861 | } | |
2862 | ||
2c642b07 | 2863 | static size_t gen8_get_stolen_size(u16 bdw_gmch_ctl) |
9459d252 BW |
2864 | { |
2865 | bdw_gmch_ctl >>= BDW_GMCH_GMS_SHIFT; | |
2866 | bdw_gmch_ctl &= BDW_GMCH_GMS_MASK; | |
2867 | return bdw_gmch_ctl << 25; /* 32 MB units */ | |
2868 | } | |
2869 | ||
d7f25f23 DL |
2870 | static size_t chv_get_stolen_size(u16 gmch_ctrl) |
2871 | { | |
2872 | gmch_ctrl >>= SNB_GMCH_GMS_SHIFT; | |
2873 | gmch_ctrl &= SNB_GMCH_GMS_MASK; | |
2874 | ||
2875 | /* | |
2876 | * 0x0 to 0x10: 32MB increments starting at 0MB | |
2877 | * 0x11 to 0x16: 4MB increments starting at 8MB | |
2878 | * 0x17 to 0x1d: 4MB increments start at 36MB | |
2879 | */ | |
2880 | if (gmch_ctrl < 0x11) | |
2881 | return gmch_ctrl << 25; | |
2882 | else if (gmch_ctrl < 0x17) | |
2883 | return (gmch_ctrl - 0x11 + 2) << 22; | |
2884 | else | |
2885 | return (gmch_ctrl - 0x17 + 9) << 22; | |
2886 | } | |
2887 | ||
66375014 DL |
2888 | static size_t gen9_get_stolen_size(u16 gen9_gmch_ctl) |
2889 | { | |
2890 | gen9_gmch_ctl >>= BDW_GMCH_GMS_SHIFT; | |
2891 | gen9_gmch_ctl &= BDW_GMCH_GMS_MASK; | |
2892 | ||
2893 | if (gen9_gmch_ctl < 0xf0) | |
2894 | return gen9_gmch_ctl << 25; /* 32 MB units */ | |
2895 | else | |
2896 | /* 4MB increments starting at 0xf0 for 4MB */ | |
2897 | return (gen9_gmch_ctl - 0xf0 + 1) << 22; | |
2898 | } | |
2899 | ||
34c998b4 | 2900 | static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size) |
63340133 | 2901 | { |
49d73912 CW |
2902 | struct drm_i915_private *dev_priv = ggtt->base.i915; |
2903 | struct pci_dev *pdev = dev_priv->drm.pdev; | |
34c998b4 | 2904 | phys_addr_t phys_addr; |
8bcdd0f7 | 2905 | int ret; |
63340133 BW |
2906 | |
2907 | /* For Modern GENs the PTEs and register space are split in the BAR */ | |
34c998b4 | 2908 | phys_addr = pci_resource_start(pdev, 0) + pci_resource_len(pdev, 0) / 2; |
63340133 | 2909 | |
2a073f89 ID |
2910 | /* |
2911 | * On BXT writes larger than 64 bit to the GTT pagetable range will be | |
2912 | * dropped. For WC mappings in general we have 64 byte burst writes | |
2913 | * when the WC buffer is flushed, so we can't use it, but have to | |
2914 | * resort to an uncached mapping. The WC issue is easily caught by the | |
2915 | * readback check when writing GTT PTE entries. | |
2916 | */ | |
cc3f90f0 | 2917 | if (IS_GEN9_LP(dev_priv)) |
34c998b4 | 2918 | ggtt->gsm = ioremap_nocache(phys_addr, size); |
2a073f89 | 2919 | else |
34c998b4 | 2920 | ggtt->gsm = ioremap_wc(phys_addr, size); |
72e96d64 | 2921 | if (!ggtt->gsm) { |
34c998b4 | 2922 | DRM_ERROR("Failed to map the ggtt page table\n"); |
63340133 BW |
2923 | return -ENOMEM; |
2924 | } | |
2925 | ||
275a991c | 2926 | ret = setup_scratch_page(dev_priv, &ggtt->base.scratch_page, GFP_DMA32); |
8bcdd0f7 | 2927 | if (ret) { |
63340133 BW |
2928 | DRM_ERROR("Scratch setup failed\n"); |
2929 | /* iounmap will also get called at remove, but meh */ | |
72e96d64 | 2930 | iounmap(ggtt->gsm); |
8bcdd0f7 | 2931 | return ret; |
63340133 BW |
2932 | } |
2933 | ||
4ad2af1e | 2934 | return 0; |
63340133 BW |
2935 | } |
2936 | ||
fbe5d36e BW |
2937 | /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability |
2938 | * bits. When using advanced contexts each context stores its own PAT, but | |
2939 | * writing this data shouldn't be harmful even in those cases. */ | |
ee0ce478 | 2940 | static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv) |
fbe5d36e | 2941 | { |
fbe5d36e BW |
2942 | uint64_t pat; |
2943 | ||
2944 | pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC) | /* for normal objects, no eLLC */ | |
2945 | GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something pointing to ptes? */ | |
2946 | GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC) | /* for scanout with eLLC */ | |
2947 | GEN8_PPAT(3, GEN8_PPAT_UC) | /* Uncached objects, mostly for scanout */ | |
2948 | GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) | | |
2949 | GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) | | |
2950 | GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) | | |
2951 | GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3)); | |
2952 | ||
2d1fe073 | 2953 | if (!USES_PPGTT(dev_priv)) |
d6a8b72e RV |
2954 | /* Spec: "For GGTT, there is NO pat_sel[2:0] from the entry, |
2955 | * so RTL will always use the value corresponding to | |
2956 | * pat_sel = 000". | |
2957 | * So let's disable cache for GGTT to avoid screen corruptions. | |
2958 | * MOCS still can be used though. | |
2959 | * - System agent ggtt writes (i.e. cpu gtt mmaps) already work | |
2960 | * before this patch, i.e. the same uncached + snooping access | |
2961 | * like on gen6/7 seems to be in effect. | |
2962 | * - So this just fixes blitter/render access. Again it looks | |
2963 | * like it's not just uncached access, but uncached + snooping. | |
2964 | * So we can still hold onto all our assumptions wrt cpu | |
2965 | * clflushing on LLC machines. | |
2966 | */ | |
2967 | pat = GEN8_PPAT(0, GEN8_PPAT_UC); | |
2968 | ||
fbe5d36e BW |
2969 | /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b |
2970 | * write would work. */ | |
7e435ad2 VS |
2971 | I915_WRITE(GEN8_PRIVATE_PAT_LO, pat); |
2972 | I915_WRITE(GEN8_PRIVATE_PAT_HI, pat >> 32); | |
fbe5d36e BW |
2973 | } |
2974 | ||
ee0ce478 VS |
2975 | static void chv_setup_private_ppat(struct drm_i915_private *dev_priv) |
2976 | { | |
2977 | uint64_t pat; | |
2978 | ||
2979 | /* | |
2980 | * Map WB on BDW to snooped on CHV. | |
2981 | * | |
2982 | * Only the snoop bit has meaning for CHV, the rest is | |
2983 | * ignored. | |
2984 | * | |
cf3d262e VS |
2985 | * The hardware will never snoop for certain types of accesses: |
2986 | * - CPU GTT (GMADR->GGTT->no snoop->memory) | |
2987 | * - PPGTT page tables | |
2988 | * - some other special cycles | |
2989 | * | |
2990 | * As with BDW, we also need to consider the following for GT accesses: | |
2991 | * "For GGTT, there is NO pat_sel[2:0] from the entry, | |
2992 | * so RTL will always use the value corresponding to | |
2993 | * pat_sel = 000". | |
2994 | * Which means we must set the snoop bit in PAT entry 0 | |
2995 | * in order to keep the global status page working. | |
ee0ce478 VS |
2996 | */ |
2997 | pat = GEN8_PPAT(0, CHV_PPAT_SNOOP) | | |
2998 | GEN8_PPAT(1, 0) | | |
2999 | GEN8_PPAT(2, 0) | | |
3000 | GEN8_PPAT(3, 0) | | |
3001 | GEN8_PPAT(4, CHV_PPAT_SNOOP) | | |
3002 | GEN8_PPAT(5, CHV_PPAT_SNOOP) | | |
3003 | GEN8_PPAT(6, CHV_PPAT_SNOOP) | | |
3004 | GEN8_PPAT(7, CHV_PPAT_SNOOP); | |
3005 | ||
7e435ad2 VS |
3006 | I915_WRITE(GEN8_PRIVATE_PAT_LO, pat); |
3007 | I915_WRITE(GEN8_PRIVATE_PAT_HI, pat >> 32); | |
ee0ce478 VS |
3008 | } |
3009 | ||
34c998b4 CW |
3010 | static void gen6_gmch_remove(struct i915_address_space *vm) |
3011 | { | |
3012 | struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm); | |
3013 | ||
3014 | iounmap(ggtt->gsm); | |
49d73912 | 3015 | cleanup_scratch_page(vm->i915, &vm->scratch_page); |
34c998b4 CW |
3016 | } |
3017 | ||
d507d735 | 3018 | static int gen8_gmch_probe(struct i915_ggtt *ggtt) |
63340133 | 3019 | { |
49d73912 | 3020 | struct drm_i915_private *dev_priv = ggtt->base.i915; |
97d6d7ab | 3021 | struct pci_dev *pdev = dev_priv->drm.pdev; |
34c998b4 | 3022 | unsigned int size; |
63340133 | 3023 | u16 snb_gmch_ctl; |
63340133 BW |
3024 | |
3025 | /* TODO: We're not aware of mappable constraints on gen8 yet */ | |
97d6d7ab CW |
3026 | ggtt->mappable_base = pci_resource_start(pdev, 2); |
3027 | ggtt->mappable_end = pci_resource_len(pdev, 2); | |
63340133 | 3028 | |
97d6d7ab CW |
3029 | if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(39))) |
3030 | pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(39)); | |
63340133 | 3031 | |
97d6d7ab | 3032 | pci_read_config_word(pdev, SNB_GMCH_CTRL, &snb_gmch_ctl); |
63340133 | 3033 | |
97d6d7ab | 3034 | if (INTEL_GEN(dev_priv) >= 9) { |
d507d735 | 3035 | ggtt->stolen_size = gen9_get_stolen_size(snb_gmch_ctl); |
34c998b4 | 3036 | size = gen8_get_total_gtt_size(snb_gmch_ctl); |
97d6d7ab | 3037 | } else if (IS_CHERRYVIEW(dev_priv)) { |
d507d735 | 3038 | ggtt->stolen_size = chv_get_stolen_size(snb_gmch_ctl); |
34c998b4 | 3039 | size = chv_get_total_gtt_size(snb_gmch_ctl); |
d7f25f23 | 3040 | } else { |
d507d735 | 3041 | ggtt->stolen_size = gen8_get_stolen_size(snb_gmch_ctl); |
34c998b4 | 3042 | size = gen8_get_total_gtt_size(snb_gmch_ctl); |
d7f25f23 | 3043 | } |
63340133 | 3044 | |
34c998b4 | 3045 | ggtt->base.total = (size / sizeof(gen8_pte_t)) << PAGE_SHIFT; |
63340133 | 3046 | |
cc3f90f0 | 3047 | if (IS_CHERRYVIEW(dev_priv) || IS_GEN9_LP(dev_priv)) |
ee0ce478 VS |
3048 | chv_setup_private_ppat(dev_priv); |
3049 | else | |
3050 | bdw_setup_private_ppat(dev_priv); | |
fbe5d36e | 3051 | |
34c998b4 | 3052 | ggtt->base.cleanup = gen6_gmch_remove; |
d507d735 JL |
3053 | ggtt->base.bind_vma = ggtt_bind_vma; |
3054 | ggtt->base.unbind_vma = ggtt_unbind_vma; | |
d6473f56 | 3055 | ggtt->base.insert_page = gen8_ggtt_insert_page; |
f7770bfd | 3056 | ggtt->base.clear_range = nop_clear_range; |
48f112fe | 3057 | if (!USES_FULL_PPGTT(dev_priv) || intel_scanout_needs_vtd_wa(dev_priv)) |
f7770bfd CW |
3058 | ggtt->base.clear_range = gen8_ggtt_clear_range; |
3059 | ||
3060 | ggtt->base.insert_entries = gen8_ggtt_insert_entries; | |
3061 | if (IS_CHERRYVIEW(dev_priv)) | |
3062 | ggtt->base.insert_entries = gen8_ggtt_insert_entries__BKL; | |
3063 | ||
34c998b4 | 3064 | return ggtt_probe_common(ggtt, size); |
63340133 BW |
3065 | } |
3066 | ||
d507d735 | 3067 | static int gen6_gmch_probe(struct i915_ggtt *ggtt) |
e76e9aeb | 3068 | { |
49d73912 | 3069 | struct drm_i915_private *dev_priv = ggtt->base.i915; |
97d6d7ab | 3070 | struct pci_dev *pdev = dev_priv->drm.pdev; |
34c998b4 | 3071 | unsigned int size; |
e76e9aeb | 3072 | u16 snb_gmch_ctl; |
e76e9aeb | 3073 | |
97d6d7ab CW |
3074 | ggtt->mappable_base = pci_resource_start(pdev, 2); |
3075 | ggtt->mappable_end = pci_resource_len(pdev, 2); | |
41907ddc | 3076 | |
baa09f5f BW |
3077 | /* 64/512MB is the current min/max we actually know of, but this is just |
3078 | * a coarse sanity check. | |
e76e9aeb | 3079 | */ |
34c998b4 | 3080 | if (ggtt->mappable_end < (64<<20) || ggtt->mappable_end > (512<<20)) { |
d507d735 | 3081 | DRM_ERROR("Unknown GMADR size (%llx)\n", ggtt->mappable_end); |
baa09f5f | 3082 | return -ENXIO; |
e76e9aeb BW |
3083 | } |
3084 | ||
97d6d7ab CW |
3085 | if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(40))) |
3086 | pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(40)); | |
3087 | pci_read_config_word(pdev, SNB_GMCH_CTRL, &snb_gmch_ctl); | |
e76e9aeb | 3088 | |
d507d735 | 3089 | ggtt->stolen_size = gen6_get_stolen_size(snb_gmch_ctl); |
e76e9aeb | 3090 | |
34c998b4 CW |
3091 | size = gen6_get_total_gtt_size(snb_gmch_ctl); |
3092 | ggtt->base.total = (size / sizeof(gen6_pte_t)) << PAGE_SHIFT; | |
e76e9aeb | 3093 | |
d507d735 | 3094 | ggtt->base.clear_range = gen6_ggtt_clear_range; |
d6473f56 | 3095 | ggtt->base.insert_page = gen6_ggtt_insert_page; |
d507d735 JL |
3096 | ggtt->base.insert_entries = gen6_ggtt_insert_entries; |
3097 | ggtt->base.bind_vma = ggtt_bind_vma; | |
3098 | ggtt->base.unbind_vma = ggtt_unbind_vma; | |
34c998b4 CW |
3099 | ggtt->base.cleanup = gen6_gmch_remove; |
3100 | ||
3101 | if (HAS_EDRAM(dev_priv)) | |
3102 | ggtt->base.pte_encode = iris_pte_encode; | |
3103 | else if (IS_HASWELL(dev_priv)) | |
3104 | ggtt->base.pte_encode = hsw_pte_encode; | |
3105 | else if (IS_VALLEYVIEW(dev_priv)) | |
3106 | ggtt->base.pte_encode = byt_pte_encode; | |
3107 | else if (INTEL_GEN(dev_priv) >= 7) | |
3108 | ggtt->base.pte_encode = ivb_pte_encode; | |
3109 | else | |
3110 | ggtt->base.pte_encode = snb_pte_encode; | |
7faf1ab2 | 3111 | |
34c998b4 | 3112 | return ggtt_probe_common(ggtt, size); |
e76e9aeb BW |
3113 | } |
3114 | ||
34c998b4 | 3115 | static void i915_gmch_remove(struct i915_address_space *vm) |
e76e9aeb | 3116 | { |
34c998b4 | 3117 | intel_gmch_remove(); |
644ec02b | 3118 | } |
baa09f5f | 3119 | |
d507d735 | 3120 | static int i915_gmch_probe(struct i915_ggtt *ggtt) |
baa09f5f | 3121 | { |
49d73912 | 3122 | struct drm_i915_private *dev_priv = ggtt->base.i915; |
baa09f5f BW |
3123 | int ret; |
3124 | ||
91c8a326 | 3125 | ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->drm.pdev, NULL); |
baa09f5f BW |
3126 | if (!ret) { |
3127 | DRM_ERROR("failed to set up gmch\n"); | |
3128 | return -EIO; | |
3129 | } | |
3130 | ||
edd1f2fe CW |
3131 | intel_gtt_get(&ggtt->base.total, |
3132 | &ggtt->stolen_size, | |
3133 | &ggtt->mappable_base, | |
3134 | &ggtt->mappable_end); | |
baa09f5f | 3135 | |
97d6d7ab | 3136 | ggtt->do_idle_maps = needs_idle_maps(dev_priv); |
d6473f56 | 3137 | ggtt->base.insert_page = i915_ggtt_insert_page; |
d507d735 JL |
3138 | ggtt->base.insert_entries = i915_ggtt_insert_entries; |
3139 | ggtt->base.clear_range = i915_ggtt_clear_range; | |
3140 | ggtt->base.bind_vma = ggtt_bind_vma; | |
3141 | ggtt->base.unbind_vma = ggtt_unbind_vma; | |
34c998b4 | 3142 | ggtt->base.cleanup = i915_gmch_remove; |
baa09f5f | 3143 | |
d507d735 | 3144 | if (unlikely(ggtt->do_idle_maps)) |
c0a7f818 CW |
3145 | DRM_INFO("applying Ironlake quirks for intel_iommu\n"); |
3146 | ||
baa09f5f BW |
3147 | return 0; |
3148 | } | |
3149 | ||
d85489d3 | 3150 | /** |
0088e522 | 3151 | * i915_ggtt_probe_hw - Probe GGTT hardware location |
97d6d7ab | 3152 | * @dev_priv: i915 device |
d85489d3 | 3153 | */ |
97d6d7ab | 3154 | int i915_ggtt_probe_hw(struct drm_i915_private *dev_priv) |
baa09f5f | 3155 | { |
62106b4f | 3156 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
baa09f5f BW |
3157 | int ret; |
3158 | ||
49d73912 | 3159 | ggtt->base.i915 = dev_priv; |
c114f76a | 3160 | |
34c998b4 CW |
3161 | if (INTEL_GEN(dev_priv) <= 5) |
3162 | ret = i915_gmch_probe(ggtt); | |
3163 | else if (INTEL_GEN(dev_priv) < 8) | |
3164 | ret = gen6_gmch_probe(ggtt); | |
3165 | else | |
3166 | ret = gen8_gmch_probe(ggtt); | |
a54c0c27 | 3167 | if (ret) |
baa09f5f | 3168 | return ret; |
baa09f5f | 3169 | |
db9309a5 CW |
3170 | /* Trim the GGTT to fit the GuC mappable upper range (when enabled). |
3171 | * This is easier than doing range restriction on the fly, as we | |
3172 | * currently don't have any bits spare to pass in this upper | |
3173 | * restriction! | |
3174 | */ | |
3175 | if (HAS_GUC(dev_priv) && i915.enable_guc_loading) { | |
3176 | ggtt->base.total = min_t(u64, ggtt->base.total, GUC_GGTT_TOP); | |
3177 | ggtt->mappable_end = min(ggtt->mappable_end, ggtt->base.total); | |
3178 | } | |
3179 | ||
c890e2d5 CW |
3180 | if ((ggtt->base.total - 1) >> 32) { |
3181 | DRM_ERROR("We never expected a Global GTT with more than 32bits" | |
f6b9d5ca | 3182 | " of address space! Found %lldM!\n", |
c890e2d5 CW |
3183 | ggtt->base.total >> 20); |
3184 | ggtt->base.total = 1ULL << 32; | |
3185 | ggtt->mappable_end = min(ggtt->mappable_end, ggtt->base.total); | |
3186 | } | |
3187 | ||
f6b9d5ca CW |
3188 | if (ggtt->mappable_end > ggtt->base.total) { |
3189 | DRM_ERROR("mappable aperture extends past end of GGTT," | |
3190 | " aperture=%llx, total=%llx\n", | |
3191 | ggtt->mappable_end, ggtt->base.total); | |
3192 | ggtt->mappable_end = ggtt->base.total; | |
3193 | } | |
3194 | ||
baa09f5f | 3195 | /* GMADR is the PCI mmio aperture into the global GTT. */ |
c44ef60e | 3196 | DRM_INFO("Memory usable by graphics device = %lluM\n", |
62106b4f JL |
3197 | ggtt->base.total >> 20); |
3198 | DRM_DEBUG_DRIVER("GMADR size = %lldM\n", ggtt->mappable_end >> 20); | |
edd1f2fe | 3199 | DRM_DEBUG_DRIVER("GTT stolen size = %uM\n", ggtt->stolen_size >> 20); |
5db6c735 DV |
3200 | #ifdef CONFIG_INTEL_IOMMU |
3201 | if (intel_iommu_gfx_mapped) | |
3202 | DRM_INFO("VT-d active for gfx access\n"); | |
3203 | #endif | |
baa09f5f BW |
3204 | |
3205 | return 0; | |
0088e522 CW |
3206 | } |
3207 | ||
3208 | /** | |
3209 | * i915_ggtt_init_hw - Initialize GGTT hardware | |
97d6d7ab | 3210 | * @dev_priv: i915 device |
0088e522 | 3211 | */ |
97d6d7ab | 3212 | int i915_ggtt_init_hw(struct drm_i915_private *dev_priv) |
0088e522 | 3213 | { |
0088e522 CW |
3214 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
3215 | int ret; | |
3216 | ||
f6b9d5ca CW |
3217 | INIT_LIST_HEAD(&dev_priv->vm_list); |
3218 | ||
3219 | /* Subtract the guard page before address space initialization to | |
3220 | * shrink the range used by drm_mm. | |
3221 | */ | |
80b204bc | 3222 | mutex_lock(&dev_priv->drm.struct_mutex); |
f6b9d5ca | 3223 | ggtt->base.total -= PAGE_SIZE; |
80b204bc | 3224 | i915_address_space_init(&ggtt->base, dev_priv, "[global]"); |
f6b9d5ca CW |
3225 | ggtt->base.total += PAGE_SIZE; |
3226 | if (!HAS_LLC(dev_priv)) | |
3227 | ggtt->base.mm.color_adjust = i915_gtt_color_adjust; | |
80b204bc | 3228 | mutex_unlock(&dev_priv->drm.struct_mutex); |
f6b9d5ca | 3229 | |
f7bbe788 CW |
3230 | if (!io_mapping_init_wc(&dev_priv->ggtt.mappable, |
3231 | dev_priv->ggtt.mappable_base, | |
3232 | dev_priv->ggtt.mappable_end)) { | |
f6b9d5ca CW |
3233 | ret = -EIO; |
3234 | goto out_gtt_cleanup; | |
3235 | } | |
3236 | ||
3237 | ggtt->mtrr = arch_phys_wc_add(ggtt->mappable_base, ggtt->mappable_end); | |
3238 | ||
0088e522 CW |
3239 | /* |
3240 | * Initialise stolen early so that we may reserve preallocated | |
3241 | * objects for the BIOS to KMS transition. | |
3242 | */ | |
7ace3d30 | 3243 | ret = i915_gem_init_stolen(dev_priv); |
0088e522 CW |
3244 | if (ret) |
3245 | goto out_gtt_cleanup; | |
3246 | ||
3247 | return 0; | |
a4eba47b ID |
3248 | |
3249 | out_gtt_cleanup: | |
72e96d64 | 3250 | ggtt->base.cleanup(&ggtt->base); |
a4eba47b | 3251 | return ret; |
baa09f5f | 3252 | } |
6f65e29a | 3253 | |
97d6d7ab | 3254 | int i915_ggtt_enable_hw(struct drm_i915_private *dev_priv) |
ac840ae5 | 3255 | { |
97d6d7ab | 3256 | if (INTEL_GEN(dev_priv) < 6 && !intel_enable_gtt()) |
ac840ae5 VS |
3257 | return -EIO; |
3258 | ||
3259 | return 0; | |
3260 | } | |
3261 | ||
275a991c | 3262 | void i915_gem_restore_gtt_mappings(struct drm_i915_private *dev_priv) |
fa42331b | 3263 | { |
72e96d64 | 3264 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
fbb30a5c | 3265 | struct drm_i915_gem_object *obj, *on; |
fa42331b | 3266 | |
dc97997a | 3267 | i915_check_and_clear_faults(dev_priv); |
fa42331b DV |
3268 | |
3269 | /* First fill our portion of the GTT with scratch pages */ | |
4fb84d99 | 3270 | ggtt->base.clear_range(&ggtt->base, ggtt->base.start, ggtt->base.total); |
fa42331b | 3271 | |
fbb30a5c CW |
3272 | ggtt->base.closed = true; /* skip rewriting PTE on VMA unbind */ |
3273 | ||
3274 | /* clflush objects bound into the GGTT and rebind them. */ | |
3275 | list_for_each_entry_safe(obj, on, | |
56cea323 | 3276 | &dev_priv->mm.bound_list, global_link) { |
fbb30a5c CW |
3277 | bool ggtt_bound = false; |
3278 | struct i915_vma *vma; | |
3279 | ||
1c7f4bca | 3280 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
72e96d64 | 3281 | if (vma->vm != &ggtt->base) |
2c3d9984 | 3282 | continue; |
fa42331b | 3283 | |
fbb30a5c CW |
3284 | if (!i915_vma_unbind(vma)) |
3285 | continue; | |
3286 | ||
2c3d9984 TU |
3287 | WARN_ON(i915_vma_bind(vma, obj->cache_level, |
3288 | PIN_UPDATE)); | |
fbb30a5c | 3289 | ggtt_bound = true; |
2c3d9984 TU |
3290 | } |
3291 | ||
fbb30a5c | 3292 | if (ggtt_bound) |
975f7ff4 | 3293 | WARN_ON(i915_gem_object_set_to_gtt_domain(obj, false)); |
2c3d9984 | 3294 | } |
fa42331b | 3295 | |
fbb30a5c CW |
3296 | ggtt->base.closed = false; |
3297 | ||
275a991c | 3298 | if (INTEL_GEN(dev_priv) >= 8) { |
cc3f90f0 | 3299 | if (IS_CHERRYVIEW(dev_priv) || IS_GEN9_LP(dev_priv)) |
fa42331b DV |
3300 | chv_setup_private_ppat(dev_priv); |
3301 | else | |
3302 | bdw_setup_private_ppat(dev_priv); | |
3303 | ||
3304 | return; | |
3305 | } | |
3306 | ||
275a991c | 3307 | if (USES_PPGTT(dev_priv)) { |
72e96d64 JL |
3308 | struct i915_address_space *vm; |
3309 | ||
fa42331b DV |
3310 | list_for_each_entry(vm, &dev_priv->vm_list, global_link) { |
3311 | /* TODO: Perhaps it shouldn't be gen6 specific */ | |
3312 | ||
e5716f55 | 3313 | struct i915_hw_ppgtt *ppgtt; |
fa42331b | 3314 | |
2bfa996e | 3315 | if (i915_is_ggtt(vm)) |
fa42331b | 3316 | ppgtt = dev_priv->mm.aliasing_ppgtt; |
e5716f55 JL |
3317 | else |
3318 | ppgtt = i915_vm_to_ppgtt(vm); | |
fa42331b DV |
3319 | |
3320 | gen6_write_page_range(dev_priv, &ppgtt->pd, | |
3321 | 0, ppgtt->base.total); | |
3322 | } | |
3323 | } | |
3324 | ||
3325 | i915_ggtt_flush(dev_priv); | |
3326 | } | |
3327 | ||
6f65e29a | 3328 | struct i915_vma * |
058d88c4 CW |
3329 | i915_gem_obj_to_vma(struct drm_i915_gem_object *obj, |
3330 | struct i915_address_space *vm, | |
3331 | const struct i915_ggtt_view *view) | |
ec7adb6e | 3332 | { |
db6c2b41 | 3333 | struct rb_node *rb; |
ec7adb6e | 3334 | |
db6c2b41 CW |
3335 | rb = obj->vma_tree.rb_node; |
3336 | while (rb) { | |
3337 | struct i915_vma *vma = rb_entry(rb, struct i915_vma, obj_node); | |
3338 | long cmp; | |
3339 | ||
b42fe9ca | 3340 | cmp = i915_vma_compare(vma, vm, view); |
db6c2b41 | 3341 | if (cmp == 0) |
058d88c4 | 3342 | return vma; |
ec7adb6e | 3343 | |
db6c2b41 CW |
3344 | if (cmp < 0) |
3345 | rb = rb->rb_right; | |
3346 | else | |
3347 | rb = rb->rb_left; | |
3348 | } | |
3349 | ||
058d88c4 | 3350 | return NULL; |
ec7adb6e JL |
3351 | } |
3352 | ||
3353 | struct i915_vma * | |
058d88c4 CW |
3354 | i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj, |
3355 | struct i915_address_space *vm, | |
3356 | const struct i915_ggtt_view *view) | |
6f65e29a | 3357 | { |
058d88c4 | 3358 | struct i915_vma *vma; |
ec7adb6e | 3359 | |
4c7d62c6 | 3360 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
058d88c4 | 3361 | GEM_BUG_ON(view && !i915_is_ggtt(vm)); |
de895082 | 3362 | |
058d88c4 | 3363 | vma = i915_gem_obj_to_vma(obj, vm, view); |
db6c2b41 | 3364 | if (!vma) { |
b42fe9ca | 3365 | vma = i915_vma_create(obj, vm, view); |
db6c2b41 CW |
3366 | GEM_BUG_ON(vma != i915_gem_obj_to_vma(obj, vm, view)); |
3367 | } | |
6f65e29a | 3368 | |
3272db53 | 3369 | GEM_BUG_ON(i915_vma_is_closed(vma)); |
6f65e29a BW |
3370 | return vma; |
3371 | } | |
fe14d5f4 | 3372 | |
804beb4b | 3373 | static struct scatterlist * |
2d7f3bdb | 3374 | rotate_pages(const dma_addr_t *in, unsigned int offset, |
804beb4b | 3375 | unsigned int width, unsigned int height, |
87130255 | 3376 | unsigned int stride, |
804beb4b | 3377 | struct sg_table *st, struct scatterlist *sg) |
50470bb0 TU |
3378 | { |
3379 | unsigned int column, row; | |
3380 | unsigned int src_idx; | |
50470bb0 | 3381 | |
50470bb0 | 3382 | for (column = 0; column < width; column++) { |
87130255 | 3383 | src_idx = stride * (height - 1) + column; |
50470bb0 TU |
3384 | for (row = 0; row < height; row++) { |
3385 | st->nents++; | |
3386 | /* We don't need the pages, but need to initialize | |
3387 | * the entries so the sg list can be happily traversed. | |
3388 | * The only thing we need are DMA addresses. | |
3389 | */ | |
3390 | sg_set_page(sg, NULL, PAGE_SIZE, 0); | |
804beb4b | 3391 | sg_dma_address(sg) = in[offset + src_idx]; |
50470bb0 TU |
3392 | sg_dma_len(sg) = PAGE_SIZE; |
3393 | sg = sg_next(sg); | |
87130255 | 3394 | src_idx -= stride; |
50470bb0 TU |
3395 | } |
3396 | } | |
804beb4b TU |
3397 | |
3398 | return sg; | |
50470bb0 TU |
3399 | } |
3400 | ||
3401 | static struct sg_table * | |
6687c906 | 3402 | intel_rotate_fb_obj_pages(const struct intel_rotation_info *rot_info, |
50470bb0 TU |
3403 | struct drm_i915_gem_object *obj) |
3404 | { | |
85d1225e | 3405 | const size_t n_pages = obj->base.size / PAGE_SIZE; |
6687c906 | 3406 | unsigned int size = intel_rotation_info_size(rot_info); |
85d1225e DG |
3407 | struct sgt_iter sgt_iter; |
3408 | dma_addr_t dma_addr; | |
50470bb0 TU |
3409 | unsigned long i; |
3410 | dma_addr_t *page_addr_list; | |
3411 | struct sg_table *st; | |
89e3e142 | 3412 | struct scatterlist *sg; |
1d00dad5 | 3413 | int ret = -ENOMEM; |
50470bb0 | 3414 | |
50470bb0 | 3415 | /* Allocate a temporary list of source pages for random access. */ |
85d1225e | 3416 | page_addr_list = drm_malloc_gfp(n_pages, |
f2a85e19 CW |
3417 | sizeof(dma_addr_t), |
3418 | GFP_TEMPORARY); | |
50470bb0 TU |
3419 | if (!page_addr_list) |
3420 | return ERR_PTR(ret); | |
3421 | ||
3422 | /* Allocate target SG list. */ | |
3423 | st = kmalloc(sizeof(*st), GFP_KERNEL); | |
3424 | if (!st) | |
3425 | goto err_st_alloc; | |
3426 | ||
6687c906 | 3427 | ret = sg_alloc_table(st, size, GFP_KERNEL); |
50470bb0 TU |
3428 | if (ret) |
3429 | goto err_sg_alloc; | |
3430 | ||
3431 | /* Populate source page list from the object. */ | |
3432 | i = 0; | |
a4f5ea64 | 3433 | for_each_sgt_dma(dma_addr, sgt_iter, obj->mm.pages) |
85d1225e | 3434 | page_addr_list[i++] = dma_addr; |
50470bb0 | 3435 | |
85d1225e | 3436 | GEM_BUG_ON(i != n_pages); |
11f20322 VS |
3437 | st->nents = 0; |
3438 | sg = st->sgl; | |
3439 | ||
6687c906 VS |
3440 | for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++) { |
3441 | sg = rotate_pages(page_addr_list, rot_info->plane[i].offset, | |
3442 | rot_info->plane[i].width, rot_info->plane[i].height, | |
3443 | rot_info->plane[i].stride, st, sg); | |
89e3e142 TU |
3444 | } |
3445 | ||
6687c906 VS |
3446 | DRM_DEBUG_KMS("Created rotated page mapping for object size %zu (%ux%u tiles, %u pages)\n", |
3447 | obj->base.size, rot_info->plane[0].width, rot_info->plane[0].height, size); | |
50470bb0 TU |
3448 | |
3449 | drm_free_large(page_addr_list); | |
3450 | ||
3451 | return st; | |
3452 | ||
3453 | err_sg_alloc: | |
3454 | kfree(st); | |
3455 | err_st_alloc: | |
3456 | drm_free_large(page_addr_list); | |
3457 | ||
6687c906 VS |
3458 | DRM_DEBUG_KMS("Failed to create rotated mapping for object size %zu! (%ux%u tiles, %u pages)\n", |
3459 | obj->base.size, rot_info->plane[0].width, rot_info->plane[0].height, size); | |
3460 | ||
50470bb0 TU |
3461 | return ERR_PTR(ret); |
3462 | } | |
ec7adb6e | 3463 | |
8bd7ef16 JL |
3464 | static struct sg_table * |
3465 | intel_partial_pages(const struct i915_ggtt_view *view, | |
3466 | struct drm_i915_gem_object *obj) | |
3467 | { | |
3468 | struct sg_table *st; | |
d2a84a76 CW |
3469 | struct scatterlist *sg, *iter; |
3470 | unsigned int count = view->params.partial.size; | |
3471 | unsigned int offset; | |
8bd7ef16 JL |
3472 | int ret = -ENOMEM; |
3473 | ||
3474 | st = kmalloc(sizeof(*st), GFP_KERNEL); | |
3475 | if (!st) | |
3476 | goto err_st_alloc; | |
3477 | ||
d2a84a76 | 3478 | ret = sg_alloc_table(st, count, GFP_KERNEL); |
8bd7ef16 JL |
3479 | if (ret) |
3480 | goto err_sg_alloc; | |
3481 | ||
d2a84a76 CW |
3482 | iter = i915_gem_object_get_sg(obj, |
3483 | view->params.partial.offset, | |
3484 | &offset); | |
3485 | GEM_BUG_ON(!iter); | |
3486 | ||
8bd7ef16 JL |
3487 | sg = st->sgl; |
3488 | st->nents = 0; | |
d2a84a76 CW |
3489 | do { |
3490 | unsigned int len; | |
8bd7ef16 | 3491 | |
d2a84a76 CW |
3492 | len = min(iter->length - (offset << PAGE_SHIFT), |
3493 | count << PAGE_SHIFT); | |
3494 | sg_set_page(sg, NULL, len, 0); | |
3495 | sg_dma_address(sg) = | |
3496 | sg_dma_address(iter) + (offset << PAGE_SHIFT); | |
3497 | sg_dma_len(sg) = len; | |
8bd7ef16 | 3498 | |
8bd7ef16 | 3499 | st->nents++; |
d2a84a76 CW |
3500 | count -= len >> PAGE_SHIFT; |
3501 | if (count == 0) { | |
3502 | sg_mark_end(sg); | |
3503 | return st; | |
3504 | } | |
8bd7ef16 | 3505 | |
d2a84a76 CW |
3506 | sg = __sg_next(sg); |
3507 | iter = __sg_next(iter); | |
3508 | offset = 0; | |
3509 | } while (1); | |
8bd7ef16 JL |
3510 | |
3511 | err_sg_alloc: | |
3512 | kfree(st); | |
3513 | err_st_alloc: | |
3514 | return ERR_PTR(ret); | |
3515 | } | |
3516 | ||
70b9f6f8 | 3517 | static int |
50470bb0 | 3518 | i915_get_ggtt_vma_pages(struct i915_vma *vma) |
fe14d5f4 | 3519 | { |
50470bb0 TU |
3520 | int ret = 0; |
3521 | ||
2c3a3f44 CW |
3522 | /* The vma->pages are only valid within the lifespan of the borrowed |
3523 | * obj->mm.pages. When the obj->mm.pages sg_table is regenerated, so | |
3524 | * must be the vma->pages. A simple rule is that vma->pages must only | |
3525 | * be accessed when the obj->mm.pages are pinned. | |
3526 | */ | |
3527 | GEM_BUG_ON(!i915_gem_object_has_pinned_pages(vma->obj)); | |
3528 | ||
247177dd | 3529 | if (vma->pages) |
fe14d5f4 TU |
3530 | return 0; |
3531 | ||
3532 | if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) | |
a4f5ea64 | 3533 | vma->pages = vma->obj->mm.pages; |
50470bb0 | 3534 | else if (vma->ggtt_view.type == I915_GGTT_VIEW_ROTATED) |
247177dd | 3535 | vma->pages = |
11d23e6f | 3536 | intel_rotate_fb_obj_pages(&vma->ggtt_view.params.rotated, vma->obj); |
8bd7ef16 | 3537 | else if (vma->ggtt_view.type == I915_GGTT_VIEW_PARTIAL) |
247177dd | 3538 | vma->pages = intel_partial_pages(&vma->ggtt_view, vma->obj); |
fe14d5f4 TU |
3539 | else |
3540 | WARN_ONCE(1, "GGTT view %u not implemented!\n", | |
3541 | vma->ggtt_view.type); | |
3542 | ||
247177dd | 3543 | if (!vma->pages) { |
ec7adb6e | 3544 | DRM_ERROR("Failed to get pages for GGTT view type %u!\n", |
fe14d5f4 | 3545 | vma->ggtt_view.type); |
50470bb0 | 3546 | ret = -EINVAL; |
247177dd CW |
3547 | } else if (IS_ERR(vma->pages)) { |
3548 | ret = PTR_ERR(vma->pages); | |
3549 | vma->pages = NULL; | |
50470bb0 TU |
3550 | DRM_ERROR("Failed to get pages for VMA view type %u (%d)!\n", |
3551 | vma->ggtt_view.type, ret); | |
fe14d5f4 TU |
3552 | } |
3553 | ||
50470bb0 | 3554 | return ret; |
fe14d5f4 TU |
3555 | } |
3556 | ||
625d988a CW |
3557 | /** |
3558 | * i915_gem_gtt_reserve - reserve a node in an address_space (GTT) | |
3559 | * @vm - the &struct i915_address_space | |
3560 | * @node - the &struct drm_mm_node (typically i915_vma.mode) | |
3561 | * @size - how much space to allocate inside the GTT, | |
3562 | * must be #I915_GTT_PAGE_SIZE aligned | |
3563 | * @offset - where to insert inside the GTT, | |
3564 | * must be #I915_GTT_MIN_ALIGNMENT aligned, and the node | |
3565 | * (@offset + @size) must fit within the address space | |
3566 | * @color - color to apply to node, if this node is not from a VMA, | |
3567 | * color must be #I915_COLOR_UNEVICTABLE | |
3568 | * @flags - control search and eviction behaviour | |
3569 | * | |
3570 | * i915_gem_gtt_reserve() tries to insert the @node at the exact @offset inside | |
3571 | * the address space (using @size and @color). If the @node does not fit, it | |
3572 | * tries to evict any overlapping nodes from the GTT, including any | |
3573 | * neighbouring nodes if the colors do not match (to ensure guard pages between | |
3574 | * differing domains). See i915_gem_evict_for_node() for the gory details | |
3575 | * on the eviction algorithm. #PIN_NONBLOCK may used to prevent waiting on | |
3576 | * evicting active overlapping objects, and any overlapping node that is pinned | |
3577 | * or marked as unevictable will also result in failure. | |
3578 | * | |
3579 | * Returns: 0 on success, -ENOSPC if no suitable hole is found, -EINTR if | |
3580 | * asked to wait for eviction and interrupted. | |
3581 | */ | |
3582 | int i915_gem_gtt_reserve(struct i915_address_space *vm, | |
3583 | struct drm_mm_node *node, | |
3584 | u64 size, u64 offset, unsigned long color, | |
3585 | unsigned int flags) | |
3586 | { | |
3587 | int err; | |
3588 | ||
3589 | GEM_BUG_ON(!size); | |
3590 | GEM_BUG_ON(!IS_ALIGNED(size, I915_GTT_PAGE_SIZE)); | |
3591 | GEM_BUG_ON(!IS_ALIGNED(offset, I915_GTT_MIN_ALIGNMENT)); | |
3592 | GEM_BUG_ON(range_overflows(offset, size, vm->total)); | |
3593 | ||
3594 | node->size = size; | |
3595 | node->start = offset; | |
3596 | node->color = color; | |
3597 | ||
3598 | err = drm_mm_reserve_node(&vm->mm, node); | |
3599 | if (err != -ENOSPC) | |
3600 | return err; | |
3601 | ||
3602 | err = i915_gem_evict_for_node(vm, node, flags); | |
3603 | if (err == 0) | |
3604 | err = drm_mm_reserve_node(&vm->mm, node); | |
3605 | ||
3606 | return err; | |
3607 | } | |
3608 | ||
e007b19d CW |
3609 | /** |
3610 | * i915_gem_gtt_insert - insert a node into an address_space (GTT) | |
3611 | * @vm - the &struct i915_address_space | |
3612 | * @node - the &struct drm_mm_node (typically i915_vma.node) | |
3613 | * @size - how much space to allocate inside the GTT, | |
3614 | * must be #I915_GTT_PAGE_SIZE aligned | |
3615 | * @alignment - required alignment of starting offset, may be 0 but | |
3616 | * if specified, this must be a power-of-two and at least | |
3617 | * #I915_GTT_MIN_ALIGNMENT | |
3618 | * @color - color to apply to node | |
3619 | * @start - start of any range restriction inside GTT (0 for all), | |
3620 | * must be #I915_GTT_PAGE_SIZE aligned | |
3621 | * @end - end of any range restriction inside GTT (U64_MAX for all), | |
3622 | * must be #I915_GTT_PAGE_SIZE aligned if not U64_MAX | |
3623 | * @flags - control search and eviction behaviour | |
3624 | * | |
3625 | * i915_gem_gtt_insert() first searches for an available hole into which | |
3626 | * is can insert the node. The hole address is aligned to @alignment and | |
3627 | * its @size must then fit entirely within the [@start, @end] bounds. The | |
3628 | * nodes on either side of the hole must match @color, or else a guard page | |
3629 | * will be inserted between the two nodes (or the node evicted). If no | |
3630 | * suitable hole is found, then the LRU list of objects within the GTT | |
3631 | * is scanned to find the first set of replacement nodes to create the hole. | |
3632 | * Those old overlapping nodes are evicted from the GTT (and so must be | |
3633 | * rebound before any future use). Any node that is currently pinned cannot | |
3634 | * be evicted (see i915_vma_pin()). Similar if the node's VMA is currently | |
3635 | * active and #PIN_NONBLOCK is specified, that node is also skipped when | |
3636 | * searching for an eviction candidate. See i915_gem_evict_something() for | |
3637 | * the gory details on the eviction algorithm. | |
3638 | * | |
3639 | * Returns: 0 on success, -ENOSPC if no suitable hole is found, -EINTR if | |
3640 | * asked to wait for eviction and interrupted. | |
3641 | */ | |
3642 | int i915_gem_gtt_insert(struct i915_address_space *vm, | |
3643 | struct drm_mm_node *node, | |
3644 | u64 size, u64 alignment, unsigned long color, | |
3645 | u64 start, u64 end, unsigned int flags) | |
3646 | { | |
3647 | u32 search_flag, alloc_flag; | |
3648 | int err; | |
3649 | ||
3650 | lockdep_assert_held(&vm->i915->drm.struct_mutex); | |
3651 | GEM_BUG_ON(!size); | |
3652 | GEM_BUG_ON(!IS_ALIGNED(size, I915_GTT_PAGE_SIZE)); | |
3653 | GEM_BUG_ON(alignment && !is_power_of_2(alignment)); | |
3654 | GEM_BUG_ON(alignment && !IS_ALIGNED(alignment, I915_GTT_MIN_ALIGNMENT)); | |
3655 | GEM_BUG_ON(start >= end); | |
3656 | GEM_BUG_ON(start > 0 && !IS_ALIGNED(start, I915_GTT_PAGE_SIZE)); | |
3657 | GEM_BUG_ON(end < U64_MAX && !IS_ALIGNED(end, I915_GTT_PAGE_SIZE)); | |
3658 | ||
3659 | if (unlikely(range_overflows(start, size, end))) | |
3660 | return -ENOSPC; | |
3661 | ||
3662 | if (unlikely(round_up(start, alignment) > round_down(end - size, alignment))) | |
3663 | return -ENOSPC; | |
3664 | ||
3665 | if (flags & PIN_HIGH) { | |
3666 | search_flag = DRM_MM_SEARCH_BELOW; | |
3667 | alloc_flag = DRM_MM_CREATE_TOP; | |
3668 | } else { | |
3669 | search_flag = DRM_MM_SEARCH_DEFAULT; | |
3670 | alloc_flag = DRM_MM_CREATE_DEFAULT; | |
3671 | } | |
3672 | ||
3673 | /* We only allocate in PAGE_SIZE/GTT_PAGE_SIZE (4096) chunks, | |
3674 | * so we know that we always have a minimum alignment of 4096. | |
3675 | * The drm_mm range manager is optimised to return results | |
3676 | * with zero alignment, so where possible use the optimal | |
3677 | * path. | |
3678 | */ | |
3679 | BUILD_BUG_ON(I915_GTT_MIN_ALIGNMENT > I915_GTT_PAGE_SIZE); | |
3680 | if (alignment <= I915_GTT_MIN_ALIGNMENT) | |
3681 | alignment = 0; | |
3682 | ||
3683 | err = drm_mm_insert_node_in_range_generic(&vm->mm, node, | |
3684 | size, alignment, color, | |
3685 | start, end, | |
3686 | search_flag, alloc_flag); | |
3687 | if (err != -ENOSPC) | |
3688 | return err; | |
3689 | ||
3690 | err = i915_gem_evict_something(vm, size, alignment, color, | |
3691 | start, end, flags); | |
3692 | if (err) | |
3693 | return err; | |
3694 | ||
3695 | search_flag = DRM_MM_SEARCH_DEFAULT; | |
3696 | return drm_mm_insert_node_in_range_generic(&vm->mm, node, | |
3697 | size, alignment, color, | |
3698 | start, end, | |
3699 | search_flag, alloc_flag); | |
3700 | } |