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drm/i915/gen8: Add PML4 structure
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / i915_gem_gtt.c
CommitLineData
76aaf220
DV		 1/*
2 * Copyright © 2010 Daniel Vetter
c4ac524c 3 * Copyright © 2011-2014 Intel Corporation
76aaf220
DV		 4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 *
24 */
25
0e46ce2e 26#include <linux/seq_file.h>
760285e7
DH		 27#include <drm/drmP.h>
28#include <drm/i915_drm.h>
76aaf220 29#include "i915_drv.h"
5dda8fa3 30#include "i915_vgpu.h"
76aaf220
DV		 31#include "i915_trace.h"
32#include "intel_drv.h"
33
45f8f69a
TU		 34/**
35 * DOC: Global GTT views
36 *
37 * Background and previous state
38 *
39 * Historically objects could exists (be bound) in global GTT space only as
40 * singular instances with a view representing all of the object's backing pages
41 * in a linear fashion. This view will be called a normal view.
42 *
43 * To support multiple views of the same object, where the number of mapped
44 * pages is not equal to the backing store, or where the layout of the pages
45 * is not linear, concept of a GGTT view was added.
46 *
47 * One example of an alternative view is a stereo display driven by a single
48 * image. In this case we would have a framebuffer looking like this
49 * (2x2 pages):
50 *
51 * 12
52 * 34
53 *
54 * Above would represent a normal GGTT view as normally mapped for GPU or CPU
55 * rendering. In contrast, fed to the display engine would be an alternative
56 * view which could look something like this:
57 *
58 * 1212
59 * 3434
60 *
61 * In this example both the size and layout of pages in the alternative view is
62 * different from the normal view.
63 *
64 * Implementation and usage
65 *
66 * GGTT views are implemented using VMAs and are distinguished via enum
67 * i915_ggtt_view_type and struct i915_ggtt_view.
68 *
69 * A new flavour of core GEM functions which work with GGTT bound objects were
ec7adb6e
JL		 70 * added with the _ggtt_ infix, and sometimes with _view postfix to avoid
71 * renaming in large amounts of code. They take the struct i915_ggtt_view
72 * parameter encapsulating all metadata required to implement a view.
45f8f69a
TU		 73 *
74 * As a helper for callers which are only interested in the normal view,
75 * globally const i915_ggtt_view_normal singleton instance exists. All old core
76 * GEM API functions, the ones not taking the view parameter, are operating on,
77 * or with the normal GGTT view.
78 *
79 * Code wanting to add or use a new GGTT view needs to:
80 *
81 * 1. Add a new enum with a suitable name.
82 * 2. Extend the metadata in the i915_ggtt_view structure if required.
83 * 3. Add support to i915_get_vma_pages().
84 *
85 * New views are required to build a scatter-gather table from within the
86 * i915_get_vma_pages function. This table is stored in the vma.ggtt_view and
87 * exists for the lifetime of an VMA.
88 *
89 * Core API is designed to have copy semantics which means that passed in
90 * struct i915_ggtt_view does not need to be persistent (left around after
91 * calling the core API functions).
92 *
93 */
94
70b9f6f8
DV		 95static int
96i915_get_ggtt_vma_pages(struct i915_vma *vma);
97
fe14d5f4 98const struct i915_ggtt_view i915_ggtt_view_normal;
9abc4648
JL		 99const struct i915_ggtt_view i915_ggtt_view_rotated = {
100 .type = I915_GGTT_VIEW_ROTATED
101};
fe14d5f4 102
cfa7c862
DV		 103static int sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt)
104{
1893a71b
CW		 105 bool has_aliasing_ppgtt;
106 bool has_full_ppgtt;
107
108 has_aliasing_ppgtt = INTEL_INFO(dev)->gen >= 6;
109 has_full_ppgtt = INTEL_INFO(dev)->gen >= 7;
1893a71b 110
71ba2d64
YZ		 111 if (intel_vgpu_active(dev))
112 has_full_ppgtt = false; /* emulation is too hard */
113
70ee45e1
DL		 114 /*
115 * We don't allow disabling PPGTT for gen9+ as it's a requirement for
116 * execlists, the sole mechanism available to submit work.
117 */
118 if (INTEL_INFO(dev)->gen < 9 &&
119 (enable_ppgtt == 0 || !has_aliasing_ppgtt))
cfa7c862
DV		 120 return 0;
121
122 if (enable_ppgtt == 1)
123 return 1;
124
1893a71b 125 if (enable_ppgtt == 2 && has_full_ppgtt)
cfa7c862
DV		 126 return 2;
127
93a25a9e
DV		 128#ifdef CONFIG_INTEL_IOMMU
129 /* Disable ppgtt on SNB if VT-d is on. */
130 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) {
131 DRM_INFO("Disabling PPGTT because VT-d is on\n");
cfa7c862 132 return 0;
93a25a9e
DV		 133 }
134#endif
135
62942ed7 136 /* Early VLV doesn't have this */
ca2aed6c
VS		 137 if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
138 dev->pdev->revision < 0xb) {
62942ed7
JB		 139 DRM_DEBUG_DRIVER("disabling PPGTT on pre-B3 step VLV\n");
140 return 0;
141 }
142
2f82bbdf
MT		 143 if (INTEL_INFO(dev)->gen >= 8 && i915.enable_execlists)
144 return 2;
145 else
146 return has_aliasing_ppgtt ? 1 : 0;
93a25a9e
DV		 147}
148
70b9f6f8
DV		 149static int ppgtt_bind_vma(struct i915_vma *vma,
150 enum i915_cache_level cache_level,
151 u32 unused)
47552659
DV		 152{
153 u32 pte_flags = 0;
154
155 /* Currently applicable only to VLV */
156 if (vma->obj->gt_ro)
157 pte_flags |= PTE_READ_ONLY;
158
159 vma->vm->insert_entries(vma->vm, vma->obj->pages, vma->node.start,
160 cache_level, pte_flags);
70b9f6f8
DV		 161
162 return 0;
47552659
DV		 163}
164
165static void ppgtt_unbind_vma(struct i915_vma *vma)
166{
167 vma->vm->clear_range(vma->vm,
168 vma->node.start,
169 vma->obj->base.size,
170 true);
171}
6f65e29a 172
2c642b07
DV		 173static gen8_pte_t gen8_pte_encode(dma_addr_t addr,
174 enum i915_cache_level level,
175 bool valid)
94ec8f61 176{
07749ef3 177 gen8_pte_t pte = valid ? _PAGE_PRESENT | _PAGE_RW : 0;
94ec8f61 178 pte |= addr;
63c42e56
BW		 179
180 switch (level) {
181 case I915_CACHE_NONE:
fbe5d36e 182 pte |= PPAT_UNCACHED_INDEX;
63c42e56
BW		 183 break;
184 case I915_CACHE_WT:
185 pte |= PPAT_DISPLAY_ELLC_INDEX;
186 break;
187 default:
188 pte |= PPAT_CACHED_INDEX;
189 break;
190 }
191
94ec8f61
BW		 192 return pte;
193}
194
fe36f55d
MK		 195static gen8_pde_t gen8_pde_encode(const dma_addr_t addr,
196 const enum i915_cache_level level)
b1fe6673 197{
07749ef3 198 gen8_pde_t pde = _PAGE_PRESENT | _PAGE_RW;
b1fe6673
BW		 199 pde |= addr;
200 if (level != I915_CACHE_NONE)
201 pde |= PPAT_CACHED_PDE_INDEX;
202 else
203 pde |= PPAT_UNCACHED_INDEX;
204 return pde;
205}
206
07749ef3
MT		 207static gen6_pte_t snb_pte_encode(dma_addr_t addr,
208 enum i915_cache_level level,
209 bool valid, u32 unused)
54d12527 210{
07749ef3 211 gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
54d12527 212 pte |= GEN6_PTE_ADDR_ENCODE(addr);
e7210c3c
BW		 213
214 switch (level) {
350ec881
CW		 215 case I915_CACHE_L3_LLC:
216 case I915_CACHE_LLC:
217 pte |= GEN6_PTE_CACHE_LLC;
218 break;
219 case I915_CACHE_NONE:
220 pte |= GEN6_PTE_UNCACHED;
221 break;
222 default:
5f77eeb0 223 MISSING_CASE(level);
350ec881
CW		 224 }
225
226 return pte;
227}
228
07749ef3
MT		 229static gen6_pte_t ivb_pte_encode(dma_addr_t addr,
230 enum i915_cache_level level,
231 bool valid, u32 unused)
350ec881 232{
07749ef3 233 gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
350ec881
CW		 234 pte |= GEN6_PTE_ADDR_ENCODE(addr);
235
236 switch (level) {
237 case I915_CACHE_L3_LLC:
238 pte |= GEN7_PTE_CACHE_L3_LLC;
e7210c3c
BW		 239 break;
240 case I915_CACHE_LLC:
241 pte |= GEN6_PTE_CACHE_LLC;
242 break;
243 case I915_CACHE_NONE:
9119708c 244 pte |= GEN6_PTE_UNCACHED;
e7210c3c
BW		 245 break;
246 default:
5f77eeb0 247 MISSING_CASE(level);
e7210c3c
BW		 248 }
249
54d12527
BW		 250 return pte;
251}
252
07749ef3
MT		 253static gen6_pte_t byt_pte_encode(dma_addr_t addr,
254 enum i915_cache_level level,
255 bool valid, u32 flags)
93c34e70 256{
07749ef3 257 gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
93c34e70
KG		 258 pte |= GEN6_PTE_ADDR_ENCODE(addr);
259
24f3a8cf
AG		 260 if (!(flags & PTE_READ_ONLY))
261 pte |= BYT_PTE_WRITEABLE;
93c34e70
KG		 262
263 if (level != I915_CACHE_NONE)
264 pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES;
265
266 return pte;
267}
268
07749ef3
MT		 269static gen6_pte_t hsw_pte_encode(dma_addr_t addr,
270 enum i915_cache_level level,
271 bool valid, u32 unused)
9119708c 272{
07749ef3 273 gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
0d8ff15e 274 pte |= HSW_PTE_ADDR_ENCODE(addr);
9119708c
KG		 275
276 if (level != I915_CACHE_NONE)
87a6b688 277 pte |= HSW_WB_LLC_AGE3;
9119708c
KG		 278
279 return pte;
280}
281
07749ef3
MT		 282static gen6_pte_t iris_pte_encode(dma_addr_t addr,
283 enum i915_cache_level level,
284 bool valid, u32 unused)
4d15c145 285{
07749ef3 286 gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
4d15c145
BW		 287 pte |= HSW_PTE_ADDR_ENCODE(addr);
288
651d794f
CW		 289 switch (level) {
290 case I915_CACHE_NONE:
291 break;
292 case I915_CACHE_WT:
c51e9701 293 pte |= HSW_WT_ELLC_LLC_AGE3;
651d794f
CW		 294 break;
295 default:
c51e9701 296 pte |= HSW_WB_ELLC_LLC_AGE3;
651d794f
CW		 297 break;
298 }
4d15c145
BW		 299
300 return pte;
301}
302
c114f76a
MK		 303static int __setup_page_dma(struct drm_device *dev,
304 struct i915_page_dma *p, gfp_t flags)
678d96fb
BW		 305{
306 struct device *device = &dev->pdev->dev;
307
c114f76a 308 p->page = alloc_page(flags);
44159ddb
MK		 309 if (!p->page)
310 return -ENOMEM;
678d96fb 311
44159ddb
MK		 312 p->daddr = dma_map_page(device,
313 p->page, 0, 4096, PCI_DMA_BIDIRECTIONAL);
678d96fb 314
44159ddb
MK		 315 if (dma_mapping_error(device, p->daddr)) {
316 __free_page(p->page);
317 return -EINVAL;
318 }
1266cdb1
MT		 319
320 return 0;
678d96fb
BW		 321}
322
c114f76a
MK		 323static int setup_page_dma(struct drm_device *dev, struct i915_page_dma *p)
324{
325 return __setup_page_dma(dev, p, GFP_KERNEL);
326}
327
44159ddb 328static void cleanup_page_dma(struct drm_device *dev, struct i915_page_dma *p)
06fda602 329{
44159ddb 330 if (WARN_ON(!p->page))
06fda602 331 return;
678d96fb 332
44159ddb
MK		 333 dma_unmap_page(&dev->pdev->dev, p->daddr, 4096, PCI_DMA_BIDIRECTIONAL);
334 __free_page(p->page);
335 memset(p, 0, sizeof(*p));
336}
337
d1c54acd 338static void *kmap_page_dma(struct i915_page_dma *p)
73eeea53 339{
d1c54acd
MK		 340 return kmap_atomic(p->page);
341}
73eeea53 342
d1c54acd
MK		 343/* We use the flushing unmap only with ppgtt structures:
344 * page directories, page tables and scratch pages.
345 */
346static void kunmap_page_dma(struct drm_device *dev, void *vaddr)
347{
73eeea53
MK		 348 /* There are only few exceptions for gen >=6. chv and bxt.
349 * And we are not sure about the latter so play safe for now.
350 */
351 if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev))
352 drm_clflush_virt_range(vaddr, PAGE_SIZE);
353
354 kunmap_atomic(vaddr);
355}
356
567047be 357#define kmap_px(px) kmap_page_dma(px_base(px))
d1c54acd
MK		 358#define kunmap_px(ppgtt, vaddr) kunmap_page_dma((ppgtt)->base.dev, (vaddr))
359
567047be
MK		 360#define setup_px(dev, px) setup_page_dma((dev), px_base(px))
361#define cleanup_px(dev, px) cleanup_page_dma((dev), px_base(px))
362#define fill_px(dev, px, v) fill_page_dma((dev), px_base(px), (v))
363#define fill32_px(dev, px, v) fill_page_dma_32((dev), px_base(px), (v))
364
d1c54acd
MK		 365static void fill_page_dma(struct drm_device *dev, struct i915_page_dma *p,
366 const uint64_t val)
367{
368 int i;
369 uint64_t * const vaddr = kmap_page_dma(p);
370
371 for (i = 0; i < 512; i++)
372 vaddr[i] = val;
373
374 kunmap_page_dma(dev, vaddr);
375}
376
73eeea53
MK		 377static void fill_page_dma_32(struct drm_device *dev, struct i915_page_dma *p,
378 const uint32_t val32)
379{
380 uint64_t v = val32;
381
382 v = v << 32 | val32;
383
384 fill_page_dma(dev, p, v);
385}
386
4ad2af1e
MK		 387static struct i915_page_scratch *alloc_scratch_page(struct drm_device *dev)
388{
389 struct i915_page_scratch *sp;
390 int ret;
391
392 sp = kzalloc(sizeof(*sp), GFP_KERNEL);
393 if (sp == NULL)
394 return ERR_PTR(-ENOMEM);
395
396 ret = __setup_page_dma(dev, px_base(sp), GFP_DMA32 | __GFP_ZERO);
397 if (ret) {
398 kfree(sp);
399 return ERR_PTR(ret);
400 }
401
402 set_pages_uc(px_page(sp), 1);
403
404 return sp;
405}
406
407static void free_scratch_page(struct drm_device *dev,
408 struct i915_page_scratch *sp)
409{
410 set_pages_wb(px_page(sp), 1);
411
412 cleanup_px(dev, sp);
413 kfree(sp);
414}
415
8a1ebd74 416static struct i915_page_table *alloc_pt(struct drm_device *dev)
06fda602 417{
ec565b3c 418 struct i915_page_table *pt;
678d96fb
BW		 419 const size_t count = INTEL_INFO(dev)->gen >= 8 ?
420 GEN8_PTES : GEN6_PTES;
421 int ret = -ENOMEM;
06fda602
BW		 422
423 pt = kzalloc(sizeof(*pt), GFP_KERNEL);
424 if (!pt)
425 return ERR_PTR(-ENOMEM);
426
678d96fb
BW		 427 pt->used_ptes = kcalloc(BITS_TO_LONGS(count), sizeof(*pt->used_ptes),
428 GFP_KERNEL);
429
430 if (!pt->used_ptes)
431 goto fail_bitmap;
432
567047be 433 ret = setup_px(dev, pt);
678d96fb 434 if (ret)
44159ddb 435 goto fail_page_m;
06fda602
BW		 436
437 return pt;
678d96fb 438
44159ddb 439fail_page_m:
678d96fb
BW		 440 kfree(pt->used_ptes);
441fail_bitmap:
442 kfree(pt);
443
444 return ERR_PTR(ret);
06fda602
BW		 445}
446
2e906bea 447static void free_pt(struct drm_device *dev, struct i915_page_table *pt)
06fda602 448{
2e906bea
MK		 449 cleanup_px(dev, pt);
450 kfree(pt->used_ptes);
451 kfree(pt);
452}
453
454static void gen8_initialize_pt(struct i915_address_space *vm,
455 struct i915_page_table *pt)
456{
457 gen8_pte_t scratch_pte;
458
459 scratch_pte = gen8_pte_encode(px_dma(vm->scratch_page),
460 I915_CACHE_LLC, true);
461
462 fill_px(vm->dev, pt, scratch_pte);
463}
464
465static void gen6_initialize_pt(struct i915_address_space *vm,
466 struct i915_page_table *pt)
467{
468 gen6_pte_t scratch_pte;
469
470 WARN_ON(px_dma(vm->scratch_page) == 0);
471
472 scratch_pte = vm->pte_encode(px_dma(vm->scratch_page),
473 I915_CACHE_LLC, true, 0);
474
475 fill32_px(vm->dev, pt, scratch_pte);
06fda602
BW		 476}
477
8a1ebd74 478static struct i915_page_directory *alloc_pd(struct drm_device *dev)
06fda602 479{
ec565b3c 480 struct i915_page_directory *pd;
33c8819f 481 int ret = -ENOMEM;
06fda602
BW		 482
483 pd = kzalloc(sizeof(*pd), GFP_KERNEL);
484 if (!pd)
485 return ERR_PTR(-ENOMEM);
486
33c8819f
MT		 487 pd->used_pdes = kcalloc(BITS_TO_LONGS(I915_PDES),
488 sizeof(*pd->used_pdes), GFP_KERNEL);
489 if (!pd->used_pdes)
a08e111a 490 goto fail_bitmap;
33c8819f 491
567047be 492 ret = setup_px(dev, pd);
33c8819f 493 if (ret)
a08e111a 494 goto fail_page_m;
e5815a2e 495
06fda602 496 return pd;
33c8819f 497
a08e111a 498fail_page_m:
33c8819f 499 kfree(pd->used_pdes);
a08e111a 500fail_bitmap:
33c8819f
MT		 501 kfree(pd);
502
503 return ERR_PTR(ret);
06fda602
BW		 504}
505
2e906bea
MK		 506static void free_pd(struct drm_device *dev, struct i915_page_directory *pd)
507{
508 if (px_page(pd)) {
509 cleanup_px(dev, pd);
510 kfree(pd->used_pdes);
511 kfree(pd);
512 }
513}
514
515static void gen8_initialize_pd(struct i915_address_space *vm,
516 struct i915_page_directory *pd)
517{
518 gen8_pde_t scratch_pde;
519
520 scratch_pde = gen8_pde_encode(px_dma(vm->scratch_pt), I915_CACHE_LLC);
521
522 fill_px(vm->dev, pd, scratch_pde);
523}
524
6ac18502
MT		 525static int __pdp_init(struct drm_device *dev,
526 struct i915_page_directory_pointer *pdp)
527{
528 size_t pdpes = I915_PDPES_PER_PDP(dev);
529
530 pdp->used_pdpes = kcalloc(BITS_TO_LONGS(pdpes),
531 sizeof(unsigned long),
532 GFP_KERNEL);
533 if (!pdp->used_pdpes)
534 return -ENOMEM;
535
536 pdp->page_directory = kcalloc(pdpes, sizeof(*pdp->page_directory),
537 GFP_KERNEL);
538 if (!pdp->page_directory) {
539 kfree(pdp->used_pdpes);
540 /* the PDP might be the statically allocated top level. Keep it
541 * as clean as possible */
542 pdp->used_pdpes = NULL;
543 return -ENOMEM;
544 }
545
546 return 0;
547}
548
549static void __pdp_fini(struct i915_page_directory_pointer *pdp)
550{
551 kfree(pdp->used_pdpes);
552 kfree(pdp->page_directory);
553 pdp->page_directory = NULL;
554}
555
556static void free_pdp(struct drm_device *dev,
557 struct i915_page_directory_pointer *pdp)
558{
559 __pdp_fini(pdp);
560}
561
94e409c1 562/* Broadwell Page Directory Pointer Descriptors */
e85b26dc 563static int gen8_write_pdp(struct drm_i915_gem_request *req,
7cb6d7ac
MT		 564 unsigned entry,
565 dma_addr_t addr)
94e409c1 566{
e85b26dc 567 struct intel_engine_cs *ring = req->ring;
94e409c1
BW		 568 int ret;
569
570 BUG_ON(entry >= 4);
571
5fb9de1a 572 ret = intel_ring_begin(req, 6);
94e409c1
BW		 573 if (ret)
574 return ret;
575
576 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
577 intel_ring_emit(ring, GEN8_RING_PDP_UDW(ring, entry));
7cb6d7ac 578 intel_ring_emit(ring, upper_32_bits(addr));
94e409c1
BW		 579 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
580 intel_ring_emit(ring, GEN8_RING_PDP_LDW(ring, entry));
7cb6d7ac 581 intel_ring_emit(ring, lower_32_bits(addr));
94e409c1
BW		 582 intel_ring_advance(ring);
583
584 return 0;
585}
586
eeb9488e 587static int gen8_mm_switch(struct i915_hw_ppgtt *ppgtt,
e85b26dc 588 struct drm_i915_gem_request *req)
94e409c1 589{
eeb9488e 590 int i, ret;
94e409c1 591
7cb6d7ac 592 for (i = GEN8_LEGACY_PDPES - 1; i >= 0; i--) {
d852c7bf
MK		 593 const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i);
594
e85b26dc 595 ret = gen8_write_pdp(req, i, pd_daddr);
eeb9488e
BW		 596 if (ret)
597 return ret;
94e409c1 598 }
d595bd4b 599
eeb9488e 600 return 0;
94e409c1
BW		 601}
602
f9b5b782
MT		 603static void gen8_ppgtt_clear_pte_range(struct i915_address_space *vm,
604 struct i915_page_directory_pointer *pdp,
605 uint64_t start,
606 uint64_t length,
607 gen8_pte_t scratch_pte)
459108b8
BW		 608{
609 struct i915_hw_ppgtt *ppgtt =
610 container_of(vm, struct i915_hw_ppgtt, base);
f9b5b782 611 gen8_pte_t *pt_vaddr;
7ad47cf2
BW		 612 unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK;
613 unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK;
614 unsigned pte = start >> GEN8_PTE_SHIFT & GEN8_PTE_MASK;
782f1495 615 unsigned num_entries = length >> PAGE_SHIFT;
459108b8
BW		 616 unsigned last_pte, i;
617
f9b5b782
MT		 618 if (WARN_ON(!pdp))
619 return;
459108b8
BW		 620
621 while (num_entries) {
ec565b3c
MT		 622 struct i915_page_directory *pd;
623 struct i915_page_table *pt;
06fda602 624
d4ec9da0 625 if (WARN_ON(!pdp->page_directory[pdpe]))
00245266 626 break;
06fda602 627
d4ec9da0 628 pd = pdp->page_directory[pdpe];
06fda602
BW		 629
630 if (WARN_ON(!pd->page_table[pde]))
00245266 631 break;
06fda602
BW		 632
633 pt = pd->page_table[pde];
634
567047be 635 if (WARN_ON(!px_page(pt)))
00245266 636 break;
06fda602 637
7ad47cf2 638 last_pte = pte + num_entries;
07749ef3
MT		 639 if (last_pte > GEN8_PTES)
640 last_pte = GEN8_PTES;
459108b8 641
d1c54acd 642 pt_vaddr = kmap_px(pt);
459108b8 643
7ad47cf2 644 for (i = pte; i < last_pte; i++) {
459108b8 645 pt_vaddr[i] = scratch_pte;
7ad47cf2
BW		 646 num_entries--;
647 }
459108b8 648
d1c54acd 649 kunmap_px(ppgtt, pt);
459108b8 650
7ad47cf2 651 pte = 0;
07749ef3 652 if (++pde == I915_PDES) {
7ad47cf2
BW		 653 pdpe++;
654 pde = 0;
655 }
459108b8
BW		 656 }
657}
658
f9b5b782
MT		 659static void gen8_ppgtt_clear_range(struct i915_address_space *vm,
660 uint64_t start,
661 uint64_t length,
662 bool use_scratch)
9df15b49
BW		 663{
664 struct i915_hw_ppgtt *ppgtt =
665 container_of(vm, struct i915_hw_ppgtt, base);
d4ec9da0 666 struct i915_page_directory_pointer *pdp = &ppgtt->pdp; /* FIXME: 48b */
f9b5b782
MT		 667
668 gen8_pte_t scratch_pte = gen8_pte_encode(px_dma(vm->scratch_page),
669 I915_CACHE_LLC, use_scratch);
670
671 gen8_ppgtt_clear_pte_range(vm, pdp, start, length, scratch_pte);
672}
673
674static void
675gen8_ppgtt_insert_pte_entries(struct i915_address_space *vm,
676 struct i915_page_directory_pointer *pdp,
677 struct sg_table *pages,
678 uint64_t start,
679 enum i915_cache_level cache_level)
680{
681 struct i915_hw_ppgtt *ppgtt =
682 container_of(vm, struct i915_hw_ppgtt, base);
07749ef3 683 gen8_pte_t *pt_vaddr;
7ad47cf2
BW		 684 unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK;
685 unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK;
686 unsigned pte = start >> GEN8_PTE_SHIFT & GEN8_PTE_MASK;
9df15b49
BW		 687 struct sg_page_iter sg_iter;
688
6f1cc993 689 pt_vaddr = NULL;
7ad47cf2 690
9df15b49 691 for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) {
76643600 692 if (WARN_ON(pdpe >= GEN8_LEGACY_PDPES))
7ad47cf2
BW		 693 break;
694
d7b3de91 695 if (pt_vaddr == NULL) {
d4ec9da0 696 struct i915_page_directory *pd = pdp->page_directory[pdpe];
ec565b3c 697 struct i915_page_table *pt = pd->page_table[pde];
d1c54acd 698 pt_vaddr = kmap_px(pt);
d7b3de91 699 }
9df15b49 700
7ad47cf2 701 pt_vaddr[pte] =
6f1cc993
CW		 702 gen8_pte_encode(sg_page_iter_dma_address(&sg_iter),
703 cache_level, true);
07749ef3 704 if (++pte == GEN8_PTES) {
d1c54acd 705 kunmap_px(ppgtt, pt_vaddr);
6f1cc993 706 pt_vaddr = NULL;
07749ef3 707 if (++pde == I915_PDES) {
7ad47cf2
BW		 708 pdpe++;
709 pde = 0;
710 }
711 pte = 0;
9df15b49
BW		 712 }
713 }
d1c54acd
MK		 714
715 if (pt_vaddr)
716 kunmap_px(ppgtt, pt_vaddr);
9df15b49
BW		 717}
718
f9b5b782
MT		 719static void gen8_ppgtt_insert_entries(struct i915_address_space *vm,
720 struct sg_table *pages,
721 uint64_t start,
722 enum i915_cache_level cache_level,
723 u32 unused)
724{
725 struct i915_hw_ppgtt *ppgtt =
726 container_of(vm, struct i915_hw_ppgtt, base);
727 struct i915_page_directory_pointer *pdp = &ppgtt->pdp; /* FIXME: 48b */
728
729 gen8_ppgtt_insert_pte_entries(vm, pdp, pages, start, cache_level);
730}
731
f37c0505
MT		 732static void gen8_free_page_tables(struct drm_device *dev,
733 struct i915_page_directory *pd)
7ad47cf2
BW		 734{
735 int i;
736
567047be 737 if (!px_page(pd))
7ad47cf2
BW		 738 return;
739
33c8819f 740 for_each_set_bit(i, pd->used_pdes, I915_PDES) {
06fda602
BW		 741 if (WARN_ON(!pd->page_table[i]))
742 continue;
7ad47cf2 743
a08e111a 744 free_pt(dev, pd->page_table[i]);
06fda602
BW		 745 pd->page_table[i] = NULL;
746 }
d7b3de91
BW		 747}
748
8776f02b
MK		 749static int gen8_init_scratch(struct i915_address_space *vm)
750{
751 struct drm_device *dev = vm->dev;
752
753 vm->scratch_page = alloc_scratch_page(dev);
754 if (IS_ERR(vm->scratch_page))
755 return PTR_ERR(vm->scratch_page);
756
757 vm->scratch_pt = alloc_pt(dev);
758 if (IS_ERR(vm->scratch_pt)) {
759 free_scratch_page(dev, vm->scratch_page);
760 return PTR_ERR(vm->scratch_pt);
761 }
762
763 vm->scratch_pd = alloc_pd(dev);
764 if (IS_ERR(vm->scratch_pd)) {
765 free_pt(dev, vm->scratch_pt);
766 free_scratch_page(dev, vm->scratch_page);
767 return PTR_ERR(vm->scratch_pd);
768 }
769
770 gen8_initialize_pt(vm, vm->scratch_pt);
771 gen8_initialize_pd(vm, vm->scratch_pd);
772
773 return 0;
774}
775
776static void gen8_free_scratch(struct i915_address_space *vm)
777{
778 struct drm_device *dev = vm->dev;
779
780 free_pd(dev, vm->scratch_pd);
781 free_pt(dev, vm->scratch_pt);
782 free_scratch_page(dev, vm->scratch_page);
783}
784
061dd493 785static void gen8_ppgtt_cleanup(struct i915_address_space *vm)
b45a6715 786{
061dd493
DV		 787 struct i915_hw_ppgtt *ppgtt =
788 container_of(vm, struct i915_hw_ppgtt, base);
d4ec9da0
MT		 789 struct i915_page_directory_pointer *pdp = &ppgtt->pdp; /* FIXME: 48b */
790 struct drm_device *dev = ppgtt->base.dev;
b45a6715
BW		 791 int i;
792
d4ec9da0
MT		 793 for_each_set_bit(i, pdp->used_pdpes, I915_PDPES_PER_PDP(dev)) {
794 if (WARN_ON(!pdp->page_directory[i]))
06fda602
BW		 795 continue;
796
d4ec9da0
MT		 797 gen8_free_page_tables(dev, pdp->page_directory[i]);
798 free_pd(dev, pdp->page_directory[i]);
7ad47cf2 799 }
69876bed 800
d4ec9da0
MT		 801 free_pdp(dev, pdp);
802
8776f02b 803 gen8_free_scratch(vm);
b45a6715
BW		 804}
805
d7b2633d
MT		 806/**
807 * gen8_ppgtt_alloc_pagetabs() - Allocate page tables for VA range.
d4ec9da0
MT		 808 * @vm: Master vm structure.
809 * @pd: Page directory for this address range.
d7b2633d 810 * @start: Starting virtual address to begin allocations.
d4ec9da0 811 * @length: Size of the allocations.
d7b2633d
MT		 812 * @new_pts: Bitmap set by function with new allocations. Likely used by the
813 * caller to free on error.
814 *
815 * Allocate the required number of page tables. Extremely similar to
816 * gen8_ppgtt_alloc_page_directories(). The main difference is here we are limited by
817 * the page directory boundary (instead of the page directory pointer). That
818 * boundary is 1GB virtual. Therefore, unlike gen8_ppgtt_alloc_page_directories(), it is
819 * possible, and likely that the caller will need to use multiple calls of this
820 * function to achieve the appropriate allocation.
821 *
822 * Return: 0 if success; negative error code otherwise.
823 */
d4ec9da0 824static int gen8_ppgtt_alloc_pagetabs(struct i915_address_space *vm,
e5815a2e 825 struct i915_page_directory *pd,
5441f0cb 826 uint64_t start,
d7b2633d
MT		 827 uint64_t length,
828 unsigned long *new_pts)
bf2b4ed2 829{
d4ec9da0 830 struct drm_device *dev = vm->dev;
d7b2633d 831 struct i915_page_table *pt;
5441f0cb
MT		 832 uint64_t temp;
833 uint32_t pde;
bf2b4ed2 834
d7b2633d
MT		 835 gen8_for_each_pde(pt, pd, start, length, temp, pde) {
836 /* Don't reallocate page tables */
6ac18502 837 if (test_bit(pde, pd->used_pdes)) {
d7b2633d 838 /* Scratch is never allocated this way */
d4ec9da0 839 WARN_ON(pt == vm->scratch_pt);
d7b2633d
MT		 840 continue;
841 }
842
8a1ebd74 843 pt = alloc_pt(dev);
d7b2633d 844 if (IS_ERR(pt))
5441f0cb
MT		 845 goto unwind_out;
846
d4ec9da0 847 gen8_initialize_pt(vm, pt);
d7b2633d 848 pd->page_table[pde] = pt;
966082c9 849 __set_bit(pde, new_pts);
4c06ec8d 850 trace_i915_page_table_entry_alloc(vm, pde, start, GEN8_PDE_SHIFT);
7ad47cf2
BW		 851 }
852
bf2b4ed2 853 return 0;
7ad47cf2
BW		 854
855unwind_out:
d7b2633d 856 for_each_set_bit(pde, new_pts, I915_PDES)
a08e111a 857 free_pt(dev, pd->page_table[pde]);
7ad47cf2 858
d7b3de91 859 return -ENOMEM;
bf2b4ed2
BW		 860}
861
d7b2633d
MT		 862/**
863 * gen8_ppgtt_alloc_page_directories() - Allocate page directories for VA range.
d4ec9da0 864 * @vm: Master vm structure.
d7b2633d
MT		 865 * @pdp: Page directory pointer for this address range.
866 * @start: Starting virtual address to begin allocations.
d4ec9da0
MT		 867 * @length: Size of the allocations.
868 * @new_pds: Bitmap set by function with new allocations. Likely used by the
d7b2633d
MT		 869 * caller to free on error.
870 *
871 * Allocate the required number of page directories starting at the pde index of
872 * @start, and ending at the pde index @start + @length. This function will skip
873 * over already allocated page directories within the range, and only allocate
874 * new ones, setting the appropriate pointer within the pdp as well as the
875 * correct position in the bitmap @new_pds.
876 *
877 * The function will only allocate the pages within the range for a give page
878 * directory pointer. In other words, if @start + @length straddles a virtually
879 * addressed PDP boundary (512GB for 4k pages), there will be more allocations
880 * required by the caller, This is not currently possible, and the BUG in the
881 * code will prevent it.
882 *
883 * Return: 0 if success; negative error code otherwise.
884 */
d4ec9da0
MT		 885static int
886gen8_ppgtt_alloc_page_directories(struct i915_address_space *vm,
887 struct i915_page_directory_pointer *pdp,
888 uint64_t start,
889 uint64_t length,
890 unsigned long *new_pds)
bf2b4ed2 891{
d4ec9da0 892 struct drm_device *dev = vm->dev;
d7b2633d 893 struct i915_page_directory *pd;
69876bed
MT		 894 uint64_t temp;
895 uint32_t pdpe;
6ac18502 896 uint32_t pdpes = I915_PDPES_PER_PDP(dev);
69876bed 897
6ac18502 898 WARN_ON(!bitmap_empty(new_pds, pdpes));
d7b2633d 899
d7b2633d 900 gen8_for_each_pdpe(pd, pdp, start, length, temp, pdpe) {
6ac18502 901 if (test_bit(pdpe, pdp->used_pdpes))
d7b2633d 902 continue;
33c8819f 903
8a1ebd74 904 pd = alloc_pd(dev);
d7b2633d 905 if (IS_ERR(pd))
d7b3de91 906 goto unwind_out;
69876bed 907
d4ec9da0 908 gen8_initialize_pd(vm, pd);
d7b2633d 909 pdp->page_directory[pdpe] = pd;
966082c9 910 __set_bit(pdpe, new_pds);
4c06ec8d 911 trace_i915_page_directory_entry_alloc(vm, pdpe, start, GEN8_PDPE_SHIFT);
d7b3de91
BW		 912 }
913
bf2b4ed2 914 return 0;
d7b3de91
BW		 915
916unwind_out:
6ac18502 917 for_each_set_bit(pdpe, new_pds, pdpes)
a08e111a 918 free_pd(dev, pdp->page_directory[pdpe]);
d7b3de91
BW		 919
920 return -ENOMEM;
bf2b4ed2
BW		 921}
922
d7b2633d 923static void
6ac18502
MT		 924free_gen8_temp_bitmaps(unsigned long *new_pds, unsigned long **new_pts,
925 uint32_t pdpes)
d7b2633d
MT		 926{
927 int i;
928
6ac18502 929 for (i = 0; i < pdpes; i++)
d7b2633d
MT		 930 kfree(new_pts[i]);
931 kfree(new_pts);
932 kfree(new_pds);
933}
934
935/* Fills in the page directory bitmap, and the array of page tables bitmap. Both
936 * of these are based on the number of PDPEs in the system.
937 */
938static
939int __must_check alloc_gen8_temp_bitmaps(unsigned long **new_pds,
6ac18502
MT		 940 unsigned long ***new_pts,
941 uint32_t pdpes)
d7b2633d
MT		 942{
943 int i;
944 unsigned long *pds;
945 unsigned long **pts;
946
6ac18502 947 pds = kcalloc(BITS_TO_LONGS(pdpes), sizeof(unsigned long), GFP_KERNEL);
d7b2633d
MT		 948 if (!pds)
949 return -ENOMEM;
950
6ac18502 951 pts = kcalloc(pdpes, sizeof(unsigned long *), GFP_KERNEL);
d7b2633d
MT		 952 if (!pts) {
953 kfree(pds);
954 return -ENOMEM;
955 }
956
6ac18502 957 for (i = 0; i < pdpes; i++) {
d7b2633d
MT		 958 pts[i] = kcalloc(BITS_TO_LONGS(I915_PDES),
959 sizeof(unsigned long), GFP_KERNEL);
960 if (!pts[i])
961 goto err_out;
962 }
963
964 *new_pds = pds;
965 *new_pts = pts;
966
967 return 0;
968
969err_out:
6ac18502 970 free_gen8_temp_bitmaps(pds, pts, pdpes);
d7b2633d
MT		 971 return -ENOMEM;
972}
973
5b7e4c9c
MK		 974/* PDE TLBs are a pain to invalidate on GEN8+. When we modify
975 * the page table structures, we mark them dirty so that
976 * context switching/execlist queuing code takes extra steps
977 * to ensure that tlbs are flushed.
978 */
979static void mark_tlbs_dirty(struct i915_hw_ppgtt *ppgtt)
980{
981 ppgtt->pd_dirty_rings = INTEL_INFO(ppgtt->base.dev)->ring_mask;
982}
983
e5815a2e 984static int gen8_alloc_va_range(struct i915_address_space *vm,
d4ec9da0 985 uint64_t start, uint64_t length)
bf2b4ed2 986{
e5815a2e
MT		 987 struct i915_hw_ppgtt *ppgtt =
988 container_of(vm, struct i915_hw_ppgtt, base);
d7b2633d 989 unsigned long *new_page_dirs, **new_page_tables;
d4ec9da0
MT		 990 struct drm_device *dev = vm->dev;
991 struct i915_page_directory_pointer *pdp = &ppgtt->pdp; /* FIXME: 48b */
5441f0cb 992 struct i915_page_directory *pd;
33c8819f
MT		 993 const uint64_t orig_start = start;
994 const uint64_t orig_length = length;
5441f0cb
MT		 995 uint64_t temp;
996 uint32_t pdpe;
d4ec9da0 997 uint32_t pdpes = I915_PDPES_PER_PDP(dev);
bf2b4ed2
BW		 998 int ret;
999
d7b2633d
MT		 1000 /* Wrap is never okay since we can only represent 48b, and we don't
1001 * actually use the other side of the canonical address space.
1002 */
1003 if (WARN_ON(start + length < start))
a05d80ee
MK		 1004 return -ENODEV;
1005
d4ec9da0 1006 if (WARN_ON(start + length > vm->total))
a05d80ee 1007 return -ENODEV;
d7b2633d 1008
6ac18502 1009 ret = alloc_gen8_temp_bitmaps(&new_page_dirs, &new_page_tables, pdpes);
bf2b4ed2
BW		 1010 if (ret)
1011 return ret;
1012
d7b2633d 1013 /* Do the allocations first so we can easily bail out */
d4ec9da0
MT		 1014 ret = gen8_ppgtt_alloc_page_directories(vm, pdp, start, length,
1015 new_page_dirs);
d7b2633d 1016 if (ret) {
6ac18502 1017 free_gen8_temp_bitmaps(new_page_dirs, new_page_tables, pdpes);
d7b2633d
MT		 1018 return ret;
1019 }
1020
1021 /* For every page directory referenced, allocate page tables */
d4ec9da0
MT		 1022 gen8_for_each_pdpe(pd, pdp, start, length, temp, pdpe) {
1023 ret = gen8_ppgtt_alloc_pagetabs(vm, pd, start, length,
d7b2633d 1024 new_page_tables[pdpe]);
5441f0cb
MT		 1025 if (ret)
1026 goto err_out;
5441f0cb
MT		 1027 }
1028
33c8819f
MT		 1029 start = orig_start;
1030 length = orig_length;
1031
d7b2633d
MT		 1032 /* Allocations have completed successfully, so set the bitmaps, and do
1033 * the mappings. */
d4ec9da0 1034 gen8_for_each_pdpe(pd, pdp, start, length, temp, pdpe) {
d1c54acd 1035 gen8_pde_t *const page_directory = kmap_px(pd);
33c8819f 1036 struct i915_page_table *pt;
09120d4e 1037 uint64_t pd_len = length;
33c8819f
MT		 1038 uint64_t pd_start = start;
1039 uint32_t pde;
1040
d7b2633d
MT		 1041 /* Every pd should be allocated, we just did that above. */
1042 WARN_ON(!pd);
1043
1044 gen8_for_each_pde(pt, pd, pd_start, pd_len, temp, pde) {
1045 /* Same reasoning as pd */
1046 WARN_ON(!pt);
1047 WARN_ON(!pd_len);
1048 WARN_ON(!gen8_pte_count(pd_start, pd_len));
1049
1050 /* Set our used ptes within the page table */
1051 bitmap_set(pt->used_ptes,
1052 gen8_pte_index(pd_start),
1053 gen8_pte_count(pd_start, pd_len));
1054
1055 /* Our pde is now pointing to the pagetable, pt */
966082c9 1056 __set_bit(pde, pd->used_pdes);
d7b2633d
MT		 1057
1058 /* Map the PDE to the page table */
fe36f55d
MK		 1059 page_directory[pde] = gen8_pde_encode(px_dma(pt),
1060 I915_CACHE_LLC);
4c06ec8d
MT		 1061 trace_i915_page_table_entry_map(&ppgtt->base, pde, pt,
1062 gen8_pte_index(start),
1063 gen8_pte_count(start, length),
1064 GEN8_PTES);
d7b2633d
MT		 1065
1066 /* NB: We haven't yet mapped ptes to pages. At this
1067 * point we're still relying on insert_entries() */
33c8819f 1068 }
d7b2633d 1069
d1c54acd 1070 kunmap_px(ppgtt, page_directory);
d4ec9da0 1071 __set_bit(pdpe, pdp->used_pdpes);
33c8819f
MT		 1072 }
1073
6ac18502 1074 free_gen8_temp_bitmaps(new_page_dirs, new_page_tables, pdpes);
5b7e4c9c 1075 mark_tlbs_dirty(ppgtt);
d7b3de91 1076 return 0;
bf2b4ed2 1077
d7b3de91 1078err_out:
d7b2633d
MT		 1079 while (pdpe--) {
1080 for_each_set_bit(temp, new_page_tables[pdpe], I915_PDES)
d4ec9da0 1081 free_pt(dev, pdp->page_directory[pdpe]->page_table[temp]);
d7b2633d
MT		 1082 }
1083
6ac18502 1084 for_each_set_bit(pdpe, new_page_dirs, pdpes)
d4ec9da0 1085 free_pd(dev, pdp->page_directory[pdpe]);
d7b2633d 1086
6ac18502 1087 free_gen8_temp_bitmaps(new_page_dirs, new_page_tables, pdpes);
5b7e4c9c 1088 mark_tlbs_dirty(ppgtt);
bf2b4ed2
BW		 1089 return ret;
1090}
1091
eb0b44ad 1092/*
f3a964b9
BW		 1093 * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers
1094 * with a net effect resembling a 2-level page table in normal x86 terms. Each
1095 * PDP represents 1GB of memory 4 * 512 * 512 * 4096 = 4GB legacy 32b address
1096 * space.
37aca44a 1097 *
f3a964b9 1098 */
5c5f6457 1099static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
37aca44a 1100{
8776f02b 1101 int ret;
7cb6d7ac 1102
8776f02b
MK		 1103 ret = gen8_init_scratch(&ppgtt->base);
1104 if (ret)
1105 return ret;
69876bed 1106
d7b2633d 1107 ppgtt->base.start = 0;
d7b2633d 1108 ppgtt->base.cleanup = gen8_ppgtt_cleanup;
5c5f6457 1109 ppgtt->base.allocate_va_range = gen8_alloc_va_range;
d7b2633d 1110 ppgtt->base.insert_entries = gen8_ppgtt_insert_entries;
c7e16f22 1111 ppgtt->base.clear_range = gen8_ppgtt_clear_range;
777dc5bb
DV		 1112 ppgtt->base.unbind_vma = ppgtt_unbind_vma;
1113 ppgtt->base.bind_vma = ppgtt_bind_vma;
d7b2633d
MT		 1114
1115 ppgtt->switch_mm = gen8_mm_switch;
1116
81ba8aef
MT		 1117 if (!USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) {
1118 ret = __pdp_init(false, &ppgtt->pdp);
6ac18502 1119
81ba8aef
MT		 1120 if (ret)
1121 goto free_scratch;
1122
1123 ppgtt->base.total = 1ULL << 32;
1124 if (IS_ENABLED(CONFIG_X86_32))
1125 /* While we have a proliferation of size_t variables
1126 * we cannot represent the full ppgtt size on 32bit,
1127 * so limit it to the same size as the GGTT (currently
1128 * 2GiB).
1129 */
1130 ppgtt->base.total = to_i915(ppgtt->base.dev)->gtt.base.total;
1131 } else {
1132 ppgtt->base.total = 1ULL << 48;
1133 ret = -EPERM; /* Not yet implemented */
6ac18502 1134 goto free_scratch;
81ba8aef 1135 }
6ac18502 1136
d7b2633d 1137 return 0;
6ac18502
MT		 1138
1139free_scratch:
1140 gen8_free_scratch(&ppgtt->base);
1141 return ret;
d7b2633d
MT		 1142}
1143
87d60b63
BW		 1144static void gen6_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m)
1145{
87d60b63 1146 struct i915_address_space *vm = &ppgtt->base;
09942c65 1147 struct i915_page_table *unused;
07749ef3 1148 gen6_pte_t scratch_pte;
87d60b63 1149 uint32_t pd_entry;
09942c65
MT		 1150 uint32_t pte, pde, temp;
1151 uint32_t start = ppgtt->base.start, length = ppgtt->base.total;
87d60b63 1152
79ab9370
MK		 1153 scratch_pte = vm->pte_encode(px_dma(vm->scratch_page),
1154 I915_CACHE_LLC, true, 0);
87d60b63 1155
09942c65 1156 gen6_for_each_pde(unused, &ppgtt->pd, start, length, temp, pde) {
87d60b63 1157 u32 expected;
07749ef3 1158 gen6_pte_t *pt_vaddr;
567047be 1159 const dma_addr_t pt_addr = px_dma(ppgtt->pd.page_table[pde]);
09942c65 1160 pd_entry = readl(ppgtt->pd_addr + pde);
87d60b63
BW		 1161 expected = (GEN6_PDE_ADDR_ENCODE(pt_addr) | GEN6_PDE_VALID);
1162
1163 if (pd_entry != expected)
1164 seq_printf(m, "\tPDE #%d mismatch: Actual PDE: %x Expected PDE: %x\n",
1165 pde,
1166 pd_entry,
1167 expected);
1168 seq_printf(m, "\tPDE: %x\n", pd_entry);
1169
d1c54acd
MK		 1170 pt_vaddr = kmap_px(ppgtt->pd.page_table[pde]);
1171
07749ef3 1172 for (pte = 0; pte < GEN6_PTES; pte+=4) {
87d60b63 1173 unsigned long va =
07749ef3 1174 (pde * PAGE_SIZE * GEN6_PTES) +
87d60b63
BW		 1175 (pte * PAGE_SIZE);
1176 int i;
1177 bool found = false;
1178 for (i = 0; i < 4; i++)
1179 if (pt_vaddr[pte + i] != scratch_pte)
1180 found = true;
1181 if (!found)
1182 continue;
1183
1184 seq_printf(m, "\t\t0x%lx [%03d,%04d]: =", va, pde, pte);
1185 for (i = 0; i < 4; i++) {
1186 if (pt_vaddr[pte + i] != scratch_pte)
1187 seq_printf(m, " %08x", pt_vaddr[pte + i]);
1188 else
1189 seq_puts(m, " SCRATCH ");
1190 }
1191 seq_puts(m, "\n");
1192 }
d1c54acd 1193 kunmap_px(ppgtt, pt_vaddr);
87d60b63
BW		 1194 }
1195}
1196
678d96fb 1197/* Write pde (index) from the page directory @pd to the page table @pt */
ec565b3c
MT		 1198static void gen6_write_pde(struct i915_page_directory *pd,
1199 const int pde, struct i915_page_table *pt)
6197349b 1200{
678d96fb
BW		 1201 /* Caller needs to make sure the write completes if necessary */
1202 struct i915_hw_ppgtt *ppgtt =
1203 container_of(pd, struct i915_hw_ppgtt, pd);
1204 u32 pd_entry;
6197349b 1205
567047be 1206 pd_entry = GEN6_PDE_ADDR_ENCODE(px_dma(pt));
678d96fb 1207 pd_entry |= GEN6_PDE_VALID;
6197349b 1208
678d96fb
BW		 1209 writel(pd_entry, ppgtt->pd_addr + pde);
1210}
6197349b 1211
678d96fb
BW		 1212/* Write all the page tables found in the ppgtt structure to incrementing page
1213 * directories. */
1214static void gen6_write_page_range(struct drm_i915_private *dev_priv,
ec565b3c 1215 struct i915_page_directory *pd,
678d96fb
BW		 1216 uint32_t start, uint32_t length)
1217{
ec565b3c 1218 struct i915_page_table *pt;
678d96fb
BW		 1219 uint32_t pde, temp;
1220
1221 gen6_for_each_pde(pt, pd, start, length, temp, pde)
1222 gen6_write_pde(pd, pde, pt);
1223
1224 /* Make sure write is complete before other code can use this page
1225 * table. Also require for WC mapped PTEs */
1226 readl(dev_priv->gtt.gsm);
3e302542
BW		 1227}
1228
b4a74e3a 1229static uint32_t get_pd_offset(struct i915_hw_ppgtt *ppgtt)
3e302542 1230{
44159ddb 1231 BUG_ON(ppgtt->pd.base.ggtt_offset & 0x3f);
b4a74e3a 1232
44159ddb 1233 return (ppgtt->pd.base.ggtt_offset / 64) << 16;
b4a74e3a
BW		 1234}
1235
90252e5c 1236static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt,
e85b26dc 1237 struct drm_i915_gem_request *req)
90252e5c 1238{
e85b26dc 1239 struct intel_engine_cs *ring = req->ring;
90252e5c
BW		 1240 int ret;
1241
90252e5c 1242 /* NB: TLBs must be flushed and invalidated before a switch */
a84c3ae1 1243 ret = ring->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
90252e5c
BW		 1244 if (ret)
1245 return ret;
1246
5fb9de1a 1247 ret = intel_ring_begin(req, 6);
90252e5c
BW		 1248 if (ret)
1249 return ret;
1250
1251 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2));
1252 intel_ring_emit(ring, RING_PP_DIR_DCLV(ring));
1253 intel_ring_emit(ring, PP_DIR_DCLV_2G);
1254 intel_ring_emit(ring, RING_PP_DIR_BASE(ring));
1255 intel_ring_emit(ring, get_pd_offset(ppgtt));
1256 intel_ring_emit(ring, MI_NOOP);
1257 intel_ring_advance(ring);
1258
1259 return 0;
1260}
1261
71ba2d64 1262static int vgpu_mm_switch(struct i915_hw_ppgtt *ppgtt,
e85b26dc 1263 struct drm_i915_gem_request *req)
71ba2d64 1264{
e85b26dc 1265 struct intel_engine_cs *ring = req->ring;
71ba2d64
YZ		 1266 struct drm_i915_private *dev_priv = to_i915(ppgtt->base.dev);
1267
1268 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
1269 I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt));
1270 return 0;
1271}
1272
48a10389 1273static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt,
e85b26dc 1274 struct drm_i915_gem_request *req)
48a10389 1275{
e85b26dc 1276 struct intel_engine_cs *ring = req->ring;
48a10389
BW		 1277 int ret;
1278
48a10389 1279 /* NB: TLBs must be flushed and invalidated before a switch */
a84c3ae1 1280 ret = ring->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
48a10389
BW		 1281 if (ret)
1282 return ret;
1283
5fb9de1a 1284 ret = intel_ring_begin(req, 6);
48a10389
BW		 1285 if (ret)
1286 return ret;
1287
1288 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2));
1289 intel_ring_emit(ring, RING_PP_DIR_DCLV(ring));
1290 intel_ring_emit(ring, PP_DIR_DCLV_2G);
1291 intel_ring_emit(ring, RING_PP_DIR_BASE(ring));
1292 intel_ring_emit(ring, get_pd_offset(ppgtt));
1293 intel_ring_emit(ring, MI_NOOP);
1294 intel_ring_advance(ring);
1295
90252e5c
BW		 1296 /* XXX: RCS is the only one to auto invalidate the TLBs? */
1297 if (ring->id != RCS) {
a84c3ae1 1298 ret = ring->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
90252e5c
BW		 1299 if (ret)
1300 return ret;
1301 }
1302
48a10389
BW		 1303 return 0;
1304}
1305
eeb9488e 1306static int gen6_mm_switch(struct i915_hw_ppgtt *ppgtt,
e85b26dc 1307 struct drm_i915_gem_request *req)
eeb9488e 1308{
e85b26dc 1309 struct intel_engine_cs *ring = req->ring;
eeb9488e
BW		 1310 struct drm_device *dev = ppgtt->base.dev;
1311 struct drm_i915_private *dev_priv = dev->dev_private;
1312
48a10389 1313
eeb9488e
BW		 1314 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
1315 I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt));
1316
1317 POSTING_READ(RING_PP_DIR_DCLV(ring));
1318
1319 return 0;
1320}
1321
82460d97 1322static void gen8_ppgtt_enable(struct drm_device *dev)
eeb9488e 1323{
eeb9488e 1324 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 1325 struct intel_engine_cs *ring;
82460d97 1326 int j;
3e302542 1327
eeb9488e
BW		 1328 for_each_ring(ring, dev_priv, j) {
1329 I915_WRITE(RING_MODE_GEN7(ring),
1330 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
eeb9488e 1331 }
eeb9488e 1332}
6197349b 1333
82460d97 1334static void gen7_ppgtt_enable(struct drm_device *dev)
3e302542 1335{
50227e1c 1336 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 1337 struct intel_engine_cs *ring;
b4a74e3a 1338 uint32_t ecochk, ecobits;
3e302542 1339 int i;
6197349b 1340
b4a74e3a
BW		 1341 ecobits = I915_READ(GAC_ECO_BITS);
1342 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);
a65c2fcd 1343
b4a74e3a
BW		 1344 ecochk = I915_READ(GAM_ECOCHK);
1345 if (IS_HASWELL(dev)) {
1346 ecochk |= ECOCHK_PPGTT_WB_HSW;
1347 } else {
1348 ecochk |= ECOCHK_PPGTT_LLC_IVB;
1349 ecochk &= ~ECOCHK_PPGTT_GFDT_IVB;
1350 }
1351 I915_WRITE(GAM_ECOCHK, ecochk);
a65c2fcd 1352
b4a74e3a 1353 for_each_ring(ring, dev_priv, i) {
6197349b 1354 /* GFX_MODE is per-ring on gen7+ */
b4a74e3a
BW		 1355 I915_WRITE(RING_MODE_GEN7(ring),
1356 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
6197349b 1357 }
b4a74e3a 1358}
6197349b 1359
82460d97 1360static void gen6_ppgtt_enable(struct drm_device *dev)
b4a74e3a 1361{
50227e1c 1362 struct drm_i915_private *dev_priv = dev->dev_private;
b4a74e3a 1363 uint32_t ecochk, gab_ctl, ecobits;
a65c2fcd 1364
b4a74e3a
BW		 1365 ecobits = I915_READ(GAC_ECO_BITS);
1366 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT |
1367 ECOBITS_PPGTT_CACHE64B);
6197349b 1368
b4a74e3a
BW		 1369 gab_ctl = I915_READ(GAB_CTL);
1370 I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);
1371
1372 ecochk = I915_READ(GAM_ECOCHK);
1373 I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B);
1374
1375 I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
6197349b
BW		 1376}
1377
1d2a314c 1378/* PPGTT support for Sandybdrige/Gen6 and later */
853ba5d2 1379static void gen6_ppgtt_clear_range(struct i915_address_space *vm,
782f1495
BW		 1380 uint64_t start,
1381 uint64_t length,
828c7908 1382 bool use_scratch)
1d2a314c 1383{
853ba5d2
BW		 1384 struct i915_hw_ppgtt *ppgtt =
1385 container_of(vm, struct i915_hw_ppgtt, base);
07749ef3 1386 gen6_pte_t *pt_vaddr, scratch_pte;
782f1495
BW		 1387 unsigned first_entry = start >> PAGE_SHIFT;
1388 unsigned num_entries = length >> PAGE_SHIFT;
07749ef3
MT		 1389 unsigned act_pt = first_entry / GEN6_PTES;
1390 unsigned first_pte = first_entry % GEN6_PTES;
7bddb01f 1391 unsigned last_pte, i;
1d2a314c 1392
c114f76a
MK		 1393 scratch_pte = vm->pte_encode(px_dma(vm->scratch_page),
1394 I915_CACHE_LLC, true, 0);
1d2a314c 1395
7bddb01f
DV		 1396 while (num_entries) {
1397 last_pte = first_pte + num_entries;
07749ef3
MT		 1398 if (last_pte > GEN6_PTES)
1399 last_pte = GEN6_PTES;
7bddb01f 1400
d1c54acd 1401 pt_vaddr = kmap_px(ppgtt->pd.page_table[act_pt]);
1d2a314c 1402
7bddb01f
DV		 1403 for (i = first_pte; i < last_pte; i++)
1404 pt_vaddr[i] = scratch_pte;
1d2a314c 1405
d1c54acd 1406 kunmap_px(ppgtt, pt_vaddr);
1d2a314c 1407
7bddb01f
DV		 1408 num_entries -= last_pte - first_pte;
1409 first_pte = 0;
a15326a5 1410 act_pt++;
7bddb01f 1411 }
1d2a314c
DV		 1412}
1413
853ba5d2 1414static void gen6_ppgtt_insert_entries(struct i915_address_space *vm,
def886c3 1415 struct sg_table *pages,
782f1495 1416 uint64_t start,
24f3a8cf 1417 enum i915_cache_level cache_level, u32 flags)
def886c3 1418{
853ba5d2
BW		 1419 struct i915_hw_ppgtt *ppgtt =
1420 container_of(vm, struct i915_hw_ppgtt, base);
07749ef3 1421 gen6_pte_t *pt_vaddr;
782f1495 1422 unsigned first_entry = start >> PAGE_SHIFT;
07749ef3
MT		 1423 unsigned act_pt = first_entry / GEN6_PTES;
1424 unsigned act_pte = first_entry % GEN6_PTES;
6e995e23
ID		 1425 struct sg_page_iter sg_iter;
1426
cc79714f 1427 pt_vaddr = NULL;
6e995e23 1428 for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) {
cc79714f 1429 if (pt_vaddr == NULL)
d1c54acd 1430 pt_vaddr = kmap_px(ppgtt->pd.page_table[act_pt]);
6e995e23 1431
cc79714f
CW		 1432 pt_vaddr[act_pte] =
1433 vm->pte_encode(sg_page_iter_dma_address(&sg_iter),
24f3a8cf
AG		 1434 cache_level, true, flags);
1435
07749ef3 1436 if (++act_pte == GEN6_PTES) {
d1c54acd 1437 kunmap_px(ppgtt, pt_vaddr);
cc79714f 1438 pt_vaddr = NULL;
a15326a5 1439 act_pt++;
6e995e23 1440 act_pte = 0;
def886c3 1441 }
def886c3 1442 }
cc79714f 1443 if (pt_vaddr)
d1c54acd 1444 kunmap_px(ppgtt, pt_vaddr);
def886c3
DV		 1445}
1446
678d96fb 1447static int gen6_alloc_va_range(struct i915_address_space *vm,
a05d80ee 1448 uint64_t start_in, uint64_t length_in)
678d96fb 1449{
4933d519
MT		 1450 DECLARE_BITMAP(new_page_tables, I915_PDES);
1451 struct drm_device *dev = vm->dev;
1452 struct drm_i915_private *dev_priv = dev->dev_private;
678d96fb
BW		 1453 struct i915_hw_ppgtt *ppgtt =
1454 container_of(vm, struct i915_hw_ppgtt, base);
ec565b3c 1455 struct i915_page_table *pt;
a05d80ee 1456 uint32_t start, length, start_save, length_save;
678d96fb 1457 uint32_t pde, temp;
4933d519
MT		 1458 int ret;
1459
a05d80ee
MK		 1460 if (WARN_ON(start_in + length_in > ppgtt->base.total))
1461 return -ENODEV;
1462
1463 start = start_save = start_in;
1464 length = length_save = length_in;
4933d519
MT		 1465
1466 bitmap_zero(new_page_tables, I915_PDES);
1467
1468 /* The allocation is done in two stages so that we can bail out with
1469 * minimal amount of pain. The first stage finds new page tables that
1470 * need allocation. The second stage marks use ptes within the page
1471 * tables.
1472 */
1473 gen6_for_each_pde(pt, &ppgtt->pd, start, length, temp, pde) {
79ab9370 1474 if (pt != vm->scratch_pt) {
4933d519
MT		 1475 WARN_ON(bitmap_empty(pt->used_ptes, GEN6_PTES));
1476 continue;
1477 }
1478
1479 /* We've already allocated a page table */
1480 WARN_ON(!bitmap_empty(pt->used_ptes, GEN6_PTES));
1481
8a1ebd74 1482 pt = alloc_pt(dev);
4933d519
MT		 1483 if (IS_ERR(pt)) {
1484 ret = PTR_ERR(pt);
1485 goto unwind_out;
1486 }
1487
1488 gen6_initialize_pt(vm, pt);
1489
1490 ppgtt->pd.page_table[pde] = pt;
966082c9 1491 __set_bit(pde, new_page_tables);
72744cb1 1492 trace_i915_page_table_entry_alloc(vm, pde, start, GEN6_PDE_SHIFT);
4933d519
MT		 1493 }
1494
1495 start = start_save;
1496 length = length_save;
678d96fb
BW		 1497
1498 gen6_for_each_pde(pt, &ppgtt->pd, start, length, temp, pde) {
1499 DECLARE_BITMAP(tmp_bitmap, GEN6_PTES);
1500
1501 bitmap_zero(tmp_bitmap, GEN6_PTES);
1502 bitmap_set(tmp_bitmap, gen6_pte_index(start),
1503 gen6_pte_count(start, length));
1504
966082c9 1505 if (__test_and_clear_bit(pde, new_page_tables))
4933d519
MT		 1506 gen6_write_pde(&ppgtt->pd, pde, pt);
1507
72744cb1
MT		 1508 trace_i915_page_table_entry_map(vm, pde, pt,
1509 gen6_pte_index(start),
1510 gen6_pte_count(start, length),
1511 GEN6_PTES);
4933d519 1512 bitmap_or(pt->used_ptes, tmp_bitmap, pt->used_ptes,
678d96fb
BW		 1513 GEN6_PTES);
1514 }
1515
4933d519
MT		 1516 WARN_ON(!bitmap_empty(new_page_tables, I915_PDES));
1517
1518 /* Make sure write is complete before other code can use this page
1519 * table. Also require for WC mapped PTEs */
1520 readl(dev_priv->gtt.gsm);
1521
563222a7 1522 mark_tlbs_dirty(ppgtt);
678d96fb 1523 return 0;
4933d519
MT		 1524
1525unwind_out:
1526 for_each_set_bit(pde, new_page_tables, I915_PDES) {
ec565b3c 1527 struct i915_page_table *pt = ppgtt->pd.page_table[pde];
4933d519 1528
79ab9370 1529 ppgtt->pd.page_table[pde] = vm->scratch_pt;
a08e111a 1530 free_pt(vm->dev, pt);
4933d519
MT		 1531 }
1532
1533 mark_tlbs_dirty(ppgtt);
1534 return ret;
678d96fb
BW		 1535}
1536
8776f02b
MK		 1537static int gen6_init_scratch(struct i915_address_space *vm)
1538{
1539 struct drm_device *dev = vm->dev;
1540
1541 vm->scratch_page = alloc_scratch_page(dev);
1542 if (IS_ERR(vm->scratch_page))
1543 return PTR_ERR(vm->scratch_page);
1544
1545 vm->scratch_pt = alloc_pt(dev);
1546 if (IS_ERR(vm->scratch_pt)) {
1547 free_scratch_page(dev, vm->scratch_page);
1548 return PTR_ERR(vm->scratch_pt);
1549 }
1550
1551 gen6_initialize_pt(vm, vm->scratch_pt);
1552
1553 return 0;
1554}
1555
1556static void gen6_free_scratch(struct i915_address_space *vm)
1557{
1558 struct drm_device *dev = vm->dev;
1559
1560 free_pt(dev, vm->scratch_pt);
1561 free_scratch_page(dev, vm->scratch_page);
1562}
1563
061dd493 1564static void gen6_ppgtt_cleanup(struct i915_address_space *vm)
a00d825d 1565{
061dd493
DV		 1566 struct i915_hw_ppgtt *ppgtt =
1567 container_of(vm, struct i915_hw_ppgtt, base);
09942c65
MT		 1568 struct i915_page_table *pt;
1569 uint32_t pde;
4933d519 1570
061dd493
DV		 1571 drm_mm_remove_node(&ppgtt->node);
1572
09942c65 1573 gen6_for_all_pdes(pt, ppgtt, pde) {
79ab9370 1574 if (pt != vm->scratch_pt)
a08e111a 1575 free_pt(ppgtt->base.dev, pt);
4933d519 1576 }
06fda602 1577
8776f02b 1578 gen6_free_scratch(vm);
3440d265
DV		 1579}
1580
b146520f 1581static int gen6_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt)
3440d265 1582{
8776f02b 1583 struct i915_address_space *vm = &ppgtt->base;
853ba5d2 1584 struct drm_device *dev = ppgtt->base.dev;
1d2a314c 1585 struct drm_i915_private *dev_priv = dev->dev_private;
e3cc1995 1586 bool retried = false;
b146520f 1587 int ret;
1d2a314c 1588
c8d4c0d6
BW		 1589 /* PPGTT PDEs reside in the GGTT and consists of 512 entries. The
1590 * allocator works in address space sizes, so it's multiplied by page
1591 * size. We allocate at the top of the GTT to avoid fragmentation.
1592 */
1593 BUG_ON(!drm_mm_initialized(&dev_priv->gtt.base.mm));
4933d519 1594
8776f02b
MK		 1595 ret = gen6_init_scratch(vm);
1596 if (ret)
1597 return ret;
4933d519 1598
e3cc1995 1599alloc:
c8d4c0d6
BW		 1600 ret = drm_mm_insert_node_in_range_generic(&dev_priv->gtt.base.mm,
1601 &ppgtt->node, GEN6_PD_SIZE,
1602 GEN6_PD_ALIGN, 0,
1603 0, dev_priv->gtt.base.total,
3e8b5ae9 1604 DRM_MM_TOPDOWN);
e3cc1995
BW		 1605 if (ret == -ENOSPC && !retried) {
1606 ret = i915_gem_evict_something(dev, &dev_priv->gtt.base,
1607 GEN6_PD_SIZE, GEN6_PD_ALIGN,
d23db88c
CW		 1608 I915_CACHE_NONE,
1609 0, dev_priv->gtt.base.total,
1610 0);
e3cc1995 1611 if (ret)
678d96fb 1612 goto err_out;
e3cc1995
BW		 1613
1614 retried = true;
1615 goto alloc;
1616 }
c8d4c0d6 1617
c8c26622 1618 if (ret)
678d96fb
BW		 1619 goto err_out;
1620
c8c26622 1621
c8d4c0d6
BW		 1622 if (ppgtt->node.start < dev_priv->gtt.mappable_end)
1623 DRM_DEBUG("Forced to use aperture for PDEs\n");
1d2a314c 1624
c8c26622 1625 return 0;
678d96fb
BW		 1626
1627err_out:
8776f02b 1628 gen6_free_scratch(vm);
678d96fb 1629 return ret;
b146520f
BW		 1630}
1631
b146520f
BW		 1632static int gen6_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt)
1633{
2f2cf682 1634 return gen6_ppgtt_allocate_page_directories(ppgtt);
4933d519 1635}
06dc68d6 1636
4933d519
MT		 1637static void gen6_scratch_va_range(struct i915_hw_ppgtt *ppgtt,
1638 uint64_t start, uint64_t length)
1639{
ec565b3c 1640 struct i915_page_table *unused;
4933d519 1641 uint32_t pde, temp;
1d2a314c 1642
4933d519 1643 gen6_for_each_pde(unused, &ppgtt->pd, start, length, temp, pde)
79ab9370 1644 ppgtt->pd.page_table[pde] = ppgtt->base.scratch_pt;
b146520f
BW		 1645}
1646
5c5f6457 1647static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
b146520f
BW		 1648{
1649 struct drm_device *dev = ppgtt->base.dev;
1650 struct drm_i915_private *dev_priv = dev->dev_private;
1651 int ret;
1652
1653 ppgtt->base.pte_encode = dev_priv->gtt.base.pte_encode;
1654 if (IS_GEN6(dev)) {
b146520f
BW		 1655 ppgtt->switch_mm = gen6_mm_switch;
1656 } else if (IS_HASWELL(dev)) {
b146520f
BW		 1657 ppgtt->switch_mm = hsw_mm_switch;
1658 } else if (IS_GEN7(dev)) {
b146520f
BW		 1659 ppgtt->switch_mm = gen7_mm_switch;
1660 } else
1661 BUG();
1662
71ba2d64
YZ		 1663 if (intel_vgpu_active(dev))
1664 ppgtt->switch_mm = vgpu_mm_switch;
1665
b146520f
BW		 1666 ret = gen6_ppgtt_alloc(ppgtt);
1667 if (ret)
1668 return ret;
1669
5c5f6457 1670 ppgtt->base.allocate_va_range = gen6_alloc_va_range;
b146520f
BW		 1671 ppgtt->base.clear_range = gen6_ppgtt_clear_range;
1672 ppgtt->base.insert_entries = gen6_ppgtt_insert_entries;
777dc5bb
DV		 1673 ppgtt->base.unbind_vma = ppgtt_unbind_vma;
1674 ppgtt->base.bind_vma = ppgtt_bind_vma;
b146520f 1675 ppgtt->base.cleanup = gen6_ppgtt_cleanup;
b146520f 1676 ppgtt->base.start = 0;
09942c65 1677 ppgtt->base.total = I915_PDES * GEN6_PTES * PAGE_SIZE;
87d60b63 1678 ppgtt->debug_dump = gen6_dump_ppgtt;
1d2a314c 1679
44159ddb 1680 ppgtt->pd.base.ggtt_offset =
07749ef3 1681 ppgtt->node.start / PAGE_SIZE * sizeof(gen6_pte_t);
1d2a314c 1682
678d96fb 1683 ppgtt->pd_addr = (gen6_pte_t __iomem *)dev_priv->gtt.gsm +
44159ddb 1684 ppgtt->pd.base.ggtt_offset / sizeof(gen6_pte_t);
678d96fb 1685
5c5f6457 1686 gen6_scratch_va_range(ppgtt, 0, ppgtt->base.total);
1d2a314c 1687
678d96fb
BW		 1688 gen6_write_page_range(dev_priv, &ppgtt->pd, 0, ppgtt->base.total);
1689
440fd528 1690 DRM_DEBUG_DRIVER("Allocated pde space (%lldM) at GTT entry: %llx\n",
b146520f
BW		 1691 ppgtt->node.size >> 20,
1692 ppgtt->node.start / PAGE_SIZE);
3440d265 1693
fa76da34 1694 DRM_DEBUG("Adding PPGTT at offset %x\n",
44159ddb 1695 ppgtt->pd.base.ggtt_offset << 10);
fa76da34 1696
b146520f 1697 return 0;
3440d265
DV		 1698}
1699
5c5f6457 1700static int __hw_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt)
3440d265 1701{
853ba5d2 1702 ppgtt->base.dev = dev;
3440d265 1703
3ed124b2 1704 if (INTEL_INFO(dev)->gen < 8)
5c5f6457 1705 return gen6_ppgtt_init(ppgtt);
3ed124b2 1706 else
d7b2633d 1707 return gen8_ppgtt_init(ppgtt);
fa76da34 1708}
c114f76a 1709
fa76da34
DV		 1710int i915_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt)
1711{
1712 struct drm_i915_private *dev_priv = dev->dev_private;
1713 int ret = 0;
3ed124b2 1714
5c5f6457 1715 ret = __hw_ppgtt_init(dev, ppgtt);
fa76da34 1716 if (ret == 0) {
c7c48dfd 1717 kref_init(&ppgtt->ref);
93bd8649
BW		 1718 drm_mm_init(&ppgtt->base.mm, ppgtt->base.start,
1719 ppgtt->base.total);
7e0d96bc 1720 i915_init_vm(dev_priv, &ppgtt->base);
93bd8649 1721 }
1d2a314c
DV		 1722
1723 return ret;
1724}
1725
82460d97
DV		 1726int i915_ppgtt_init_hw(struct drm_device *dev)
1727{
671b5013
TD		 1728 /* In the case of execlists, PPGTT is enabled by the context descriptor
1729 * and the PDPs are contained within the context itself. We don't
1730 * need to do anything here. */
1731 if (i915.enable_execlists)
1732 return 0;
1733
82460d97
DV		 1734 if (!USES_PPGTT(dev))
1735 return 0;
1736
1737 if (IS_GEN6(dev))
1738 gen6_ppgtt_enable(dev);
1739 else if (IS_GEN7(dev))
1740 gen7_ppgtt_enable(dev);
1741 else if (INTEL_INFO(dev)->gen >= 8)
1742 gen8_ppgtt_enable(dev);
1743 else
5f77eeb0 1744 MISSING_CASE(INTEL_INFO(dev)->gen);
82460d97 1745
4ad2fd88
JH		 1746 return 0;
1747}
1d2a314c 1748
b3dd6b96 1749int i915_ppgtt_init_ring(struct drm_i915_gem_request *req)
4ad2fd88 1750{
b3dd6b96 1751 struct drm_i915_private *dev_priv = req->ring->dev->dev_private;
4ad2fd88
JH		 1752 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
1753
1754 if (i915.enable_execlists)
1755 return 0;
1756
1757 if (!ppgtt)
1758 return 0;
1759
e85b26dc 1760 return ppgtt->switch_mm(ppgtt, req);
1d2a314c 1761}
4ad2fd88 1762
4d884705
DV		 1763struct i915_hw_ppgtt *
1764i915_ppgtt_create(struct drm_device *dev, struct drm_i915_file_private *fpriv)
1765{
1766 struct i915_hw_ppgtt *ppgtt;
1767 int ret;
1768
1769 ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
1770 if (!ppgtt)
1771 return ERR_PTR(-ENOMEM);
1772
1773 ret = i915_ppgtt_init(dev, ppgtt);
1774 if (ret) {
1775 kfree(ppgtt);
1776 return ERR_PTR(ret);
1777 }
1778
1779 ppgtt->file_priv = fpriv;
1780
198c974d
DCS		 1781 trace_i915_ppgtt_create(&ppgtt->base);
1782
4d884705
DV		 1783 return ppgtt;
1784}
1785
ee960be7
DV		 1786void i915_ppgtt_release(struct kref *kref)
1787{
1788 struct i915_hw_ppgtt *ppgtt =
1789 container_of(kref, struct i915_hw_ppgtt, ref);
1790
198c974d
DCS		 1791 trace_i915_ppgtt_release(&ppgtt->base);
1792
ee960be7
DV		 1793 /* vmas should already be unbound */
1794 WARN_ON(!list_empty(&ppgtt->base.active_list));
1795 WARN_ON(!list_empty(&ppgtt->base.inactive_list));
1796
19dd120c
DV		 1797 list_del(&ppgtt->base.global_link);
1798 drm_mm_takedown(&ppgtt->base.mm);
1799
ee960be7
DV		 1800 ppgtt->base.cleanup(&ppgtt->base);
1801 kfree(ppgtt);
1802}
1d2a314c 1803
a81cc00c
BW		 1804extern int intel_iommu_gfx_mapped;
1805/* Certain Gen5 chipsets require require idling the GPU before
1806 * unmapping anything from the GTT when VT-d is enabled.
1807 */
2c642b07 1808static bool needs_idle_maps(struct drm_device *dev)
a81cc00c
BW		 1809{
1810#ifdef CONFIG_INTEL_IOMMU
1811 /* Query intel_iommu to see if we need the workaround. Presumably that
1812 * was loaded first.
1813 */
1814 if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped)
1815 return true;
1816#endif
1817 return false;
1818}
1819
5c042287
BW		 1820static bool do_idling(struct drm_i915_private *dev_priv)
1821{
1822 bool ret = dev_priv->mm.interruptible;
1823
a81cc00c 1824 if (unlikely(dev_priv->gtt.do_idle_maps)) {
5c042287 1825 dev_priv->mm.interruptible = false;
b2da9fe5 1826 if (i915_gpu_idle(dev_priv->dev)) {
5c042287
BW		 1827 DRM_ERROR("Couldn't idle GPU\n");
1828 /* Wait a bit, in hopes it avoids the hang */
1829 udelay(10);
1830 }
1831 }
1832
1833 return ret;
1834}
1835
1836static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible)
1837{
a81cc00c 1838 if (unlikely(dev_priv->gtt.do_idle_maps))
5c042287
BW		 1839 dev_priv->mm.interruptible = interruptible;
1840}
1841
828c7908
BW		 1842void i915_check_and_clear_faults(struct drm_device *dev)
1843{
1844 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 1845 struct intel_engine_cs *ring;
828c7908
BW		 1846 int i;
1847
1848 if (INTEL_INFO(dev)->gen < 6)
1849 return;
1850
1851 for_each_ring(ring, dev_priv, i) {
1852 u32 fault_reg;
1853 fault_reg = I915_READ(RING_FAULT_REG(ring));
1854 if (fault_reg & RING_FAULT_VALID) {
1855 DRM_DEBUG_DRIVER("Unexpected fault\n"
59a5d290 1856 "\tAddr: 0x%08lx\n"
828c7908
BW		 1857 "\tAddress space: %s\n"
1858 "\tSource ID: %d\n"
1859 "\tType: %d\n",
1860 fault_reg & PAGE_MASK,
1861 fault_reg & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT",
1862 RING_FAULT_SRCID(fault_reg),
1863 RING_FAULT_FAULT_TYPE(fault_reg));
1864 I915_WRITE(RING_FAULT_REG(ring),
1865 fault_reg & ~RING_FAULT_VALID);
1866 }
1867 }
1868 POSTING_READ(RING_FAULT_REG(&dev_priv->ring[RCS]));
1869}
1870
91e56499
CW		 1871static void i915_ggtt_flush(struct drm_i915_private *dev_priv)
1872{
1873 if (INTEL_INFO(dev_priv->dev)->gen < 6) {
1874 intel_gtt_chipset_flush();
1875 } else {
1876 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
1877 POSTING_READ(GFX_FLSH_CNTL_GEN6);
1878 }
1879}
1880
828c7908
BW		 1881void i915_gem_suspend_gtt_mappings(struct drm_device *dev)
1882{
1883 struct drm_i915_private *dev_priv = dev->dev_private;
1884
1885 /* Don't bother messing with faults pre GEN6 as we have little
1886 * documentation supporting that it's a good idea.
1887 */
1888 if (INTEL_INFO(dev)->gen < 6)
1889 return;
1890
1891 i915_check_and_clear_faults(dev);
1892
1893 dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
782f1495
BW		 1894 dev_priv->gtt.base.start,
1895 dev_priv->gtt.base.total,
e568af1c 1896 true);
91e56499
CW		 1897
1898 i915_ggtt_flush(dev_priv);
828c7908
BW		 1899}
1900
74163907 1901int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj)
7c2e6fdf 1902{
9da3da66
CW		 1903 if (!dma_map_sg(&obj->base.dev->pdev->dev,
1904 obj->pages->sgl, obj->pages->nents,
1905 PCI_DMA_BIDIRECTIONAL))
1906 return -ENOSPC;
1907
1908 return 0;
7c2e6fdf
DV		 1909}
1910
2c642b07 1911static void gen8_set_pte(void __iomem *addr, gen8_pte_t pte)
94ec8f61
BW		 1912{
1913#ifdef writeq
1914 writeq(pte, addr);
1915#else
1916 iowrite32((u32)pte, addr);
1917 iowrite32(pte >> 32, addr + 4);
1918#endif
1919}
1920
1921static void gen8_ggtt_insert_entries(struct i915_address_space *vm,
1922 struct sg_table *st,
782f1495 1923 uint64_t start,
24f3a8cf 1924 enum i915_cache_level level, u32 unused)
94ec8f61
BW		 1925{
1926 struct drm_i915_private *dev_priv = vm->dev->dev_private;
782f1495 1927 unsigned first_entry = start >> PAGE_SHIFT;
07749ef3
MT		 1928 gen8_pte_t __iomem *gtt_entries =
1929 (gen8_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
94ec8f61
BW		 1930 int i = 0;
1931 struct sg_page_iter sg_iter;
57007df7 1932 dma_addr_t addr = 0; /* shut up gcc */
94ec8f61
BW		 1933
1934 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
1935 addr = sg_dma_address(sg_iter.sg) +
1936 (sg_iter.sg_pgoffset << PAGE_SHIFT);
1937 gen8_set_pte(&gtt_entries[i],
1938 gen8_pte_encode(addr, level, true));
1939 i++;
1940 }
1941
1942 /*
1943 * XXX: This serves as a posting read to make sure that the PTE has
1944 * actually been updated. There is some concern that even though
1945 * registers and PTEs are within the same BAR that they are potentially
1946 * of NUMA access patterns. Therefore, even with the way we assume
1947 * hardware should work, we must keep this posting read for paranoia.
1948 */
1949 if (i != 0)
1950 WARN_ON(readq(&gtt_entries[i-1])
1951 != gen8_pte_encode(addr, level, true));
1952
94ec8f61
BW		 1953 /* This next bit makes the above posting read even more important. We
1954 * want to flush the TLBs only after we're certain all the PTE updates
1955 * have finished.
1956 */
1957 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
1958 POSTING_READ(GFX_FLSH_CNTL_GEN6);
94ec8f61
BW		 1959}
1960
e76e9aeb
BW		 1961/*
1962 * Binds an object into the global gtt with the specified cache level. The object
1963 * will be accessible to the GPU via commands whose operands reference offsets
1964 * within the global GTT as well as accessible by the GPU through the GMADR
1965 * mapped BAR (dev_priv->mm.gtt->gtt).
1966 */
853ba5d2 1967static void gen6_ggtt_insert_entries(struct i915_address_space *vm,
7faf1ab2 1968 struct sg_table *st,
782f1495 1969 uint64_t start,
24f3a8cf 1970 enum i915_cache_level level, u32 flags)
e76e9aeb 1971{
853ba5d2 1972 struct drm_i915_private *dev_priv = vm->dev->dev_private;
782f1495 1973 unsigned first_entry = start >> PAGE_SHIFT;
07749ef3
MT		 1974 gen6_pte_t __iomem *gtt_entries =
1975 (gen6_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
6e995e23
ID		 1976 int i = 0;
1977 struct sg_page_iter sg_iter;
57007df7 1978 dma_addr_t addr = 0;
e76e9aeb 1979
6e995e23 1980 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
2db76d7c 1981 addr = sg_page_iter_dma_address(&sg_iter);
24f3a8cf 1982 iowrite32(vm->pte_encode(addr, level, true, flags), &gtt_entries[i]);
6e995e23 1983 i++;
e76e9aeb
BW		 1984 }
1985
e76e9aeb
BW		 1986 /* XXX: This serves as a posting read to make sure that the PTE has
1987 * actually been updated. There is some concern that even though
1988 * registers and PTEs are within the same BAR that they are potentially
1989 * of NUMA access patterns. Therefore, even with the way we assume
1990 * hardware should work, we must keep this posting read for paranoia.
1991 */
57007df7
PM		 1992 if (i != 0) {
1993 unsigned long gtt = readl(&gtt_entries[i-1]);
1994 WARN_ON(gtt != vm->pte_encode(addr, level, true, flags));
1995 }
0f9b91c7
BW		 1996
1997 /* This next bit makes the above posting read even more important. We
1998 * want to flush the TLBs only after we're certain all the PTE updates
1999 * have finished.
2000 */
2001 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
2002 POSTING_READ(GFX_FLSH_CNTL_GEN6);
e76e9aeb
BW		 2003}
2004
94ec8f61 2005static void gen8_ggtt_clear_range(struct i915_address_space *vm,
782f1495
BW		 2006 uint64_t start,
2007 uint64_t length,
94ec8f61
BW		 2008 bool use_scratch)
2009{
2010 struct drm_i915_private *dev_priv = vm->dev->dev_private;
782f1495
BW		 2011 unsigned first_entry = start >> PAGE_SHIFT;
2012 unsigned num_entries = length >> PAGE_SHIFT;
07749ef3
MT		 2013 gen8_pte_t scratch_pte, __iomem *gtt_base =
2014 (gen8_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
94ec8f61
BW		 2015 const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry;
2016 int i;
2017
2018 if (WARN(num_entries > max_entries,
2019 "First entry = %d; Num entries = %d (max=%d)\n",
2020 first_entry, num_entries, max_entries))
2021 num_entries = max_entries;
2022
c114f76a 2023 scratch_pte = gen8_pte_encode(px_dma(vm->scratch_page),
94ec8f61
BW		 2024 I915_CACHE_LLC,
2025 use_scratch);
2026 for (i = 0; i < num_entries; i++)
2027 gen8_set_pte(&gtt_base[i], scratch_pte);
2028 readl(gtt_base);
2029}
2030
853ba5d2 2031static void gen6_ggtt_clear_range(struct i915_address_space *vm,
782f1495
BW		 2032 uint64_t start,
2033 uint64_t length,
828c7908 2034 bool use_scratch)
7faf1ab2 2035{
853ba5d2 2036 struct drm_i915_private *dev_priv = vm->dev->dev_private;
782f1495
BW		 2037 unsigned first_entry = start >> PAGE_SHIFT;
2038 unsigned num_entries = length >> PAGE_SHIFT;
07749ef3
MT		 2039 gen6_pte_t scratch_pte, __iomem *gtt_base =
2040 (gen6_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
a54c0c27 2041 const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry;
7faf1ab2
DV		 2042 int i;
2043
2044 if (WARN(num_entries > max_entries,
2045 "First entry = %d; Num entries = %d (max=%d)\n",
2046 first_entry, num_entries, max_entries))
2047 num_entries = max_entries;
2048
c114f76a
MK		 2049 scratch_pte = vm->pte_encode(px_dma(vm->scratch_page),
2050 I915_CACHE_LLC, use_scratch, 0);
828c7908 2051
7faf1ab2
DV		 2052 for (i = 0; i < num_entries; i++)
2053 iowrite32(scratch_pte, &gtt_base[i]);
2054 readl(gtt_base);
2055}
2056
d369d2d9
DV		 2057static void i915_ggtt_insert_entries(struct i915_address_space *vm,
2058 struct sg_table *pages,
2059 uint64_t start,
2060 enum i915_cache_level cache_level, u32 unused)
7faf1ab2
DV		 2061{
2062 unsigned int flags = (cache_level == I915_CACHE_NONE) ?
2063 AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
2064
d369d2d9 2065 intel_gtt_insert_sg_entries(pages, start >> PAGE_SHIFT, flags);
0875546c 2066
7faf1ab2
DV		 2067}
2068
853ba5d2 2069static void i915_ggtt_clear_range(struct i915_address_space *vm,
782f1495
BW		 2070 uint64_t start,
2071 uint64_t length,
828c7908 2072 bool unused)
7faf1ab2 2073{
782f1495
BW		 2074 unsigned first_entry = start >> PAGE_SHIFT;
2075 unsigned num_entries = length >> PAGE_SHIFT;
7faf1ab2
DV		 2076 intel_gtt_clear_range(first_entry, num_entries);
2077}
2078
70b9f6f8
DV		 2079static int ggtt_bind_vma(struct i915_vma *vma,
2080 enum i915_cache_level cache_level,
2081 u32 flags)
d5bd1449 2082{
6f65e29a 2083 struct drm_device *dev = vma->vm->dev;
7faf1ab2 2084 struct drm_i915_private *dev_priv = dev->dev_private;
6f65e29a 2085 struct drm_i915_gem_object *obj = vma->obj;
ec7adb6e 2086 struct sg_table *pages = obj->pages;
f329f5f6 2087 u32 pte_flags = 0;
70b9f6f8
DV		 2088 int ret;
2089
2090 ret = i915_get_ggtt_vma_pages(vma);
2091 if (ret)
2092 return ret;
2093 pages = vma->ggtt_view.pages;
7faf1ab2 2094
24f3a8cf
AG		 2095 /* Currently applicable only to VLV */
2096 if (obj->gt_ro)
f329f5f6 2097 pte_flags |= PTE_READ_ONLY;
24f3a8cf 2098
ec7adb6e 2099
6f65e29a 2100 if (!dev_priv->mm.aliasing_ppgtt || flags & GLOBAL_BIND) {
0875546c
DV		 2101 vma->vm->insert_entries(vma->vm, pages,
2102 vma->node.start,
2103 cache_level, pte_flags);
d0e30adc
CW		 2104
2105 /* Note the inconsistency here is due to absence of the
2106 * aliasing ppgtt on gen4 and earlier. Though we always
2107 * request PIN_USER for execbuffer (translated to LOCAL_BIND),
2108 * without the appgtt, we cannot honour that request and so
2109 * must substitute it with a global binding. Since we do this
2110 * behind the upper layers back, we need to explicitly set
2111 * the bound flag ourselves.
2112 */
2113 vma->bound |= GLOBAL_BIND;
2114
6f65e29a 2115 }
d5bd1449 2116
0875546c 2117 if (dev_priv->mm.aliasing_ppgtt && flags & LOCAL_BIND) {
6f65e29a 2118 struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt;
ec7adb6e 2119 appgtt->base.insert_entries(&appgtt->base, pages,
782f1495 2120 vma->node.start,
f329f5f6 2121 cache_level, pte_flags);
6f65e29a 2122 }
70b9f6f8
DV		 2123
2124 return 0;
d5bd1449
CW		 2125}
2126
6f65e29a 2127static void ggtt_unbind_vma(struct i915_vma *vma)
74163907 2128{
6f65e29a 2129 struct drm_device *dev = vma->vm->dev;
7faf1ab2 2130 struct drm_i915_private *dev_priv = dev->dev_private;
6f65e29a 2131 struct drm_i915_gem_object *obj = vma->obj;
06615ee5
JL		 2132 const uint64_t size = min_t(uint64_t,
2133 obj->base.size,
2134 vma->node.size);
6f65e29a 2135
aff43766 2136 if (vma->bound & GLOBAL_BIND) {
782f1495
BW		 2137 vma->vm->clear_range(vma->vm,
2138 vma->node.start,
06615ee5 2139 size,
6f65e29a 2140 true);
6f65e29a 2141 }
74898d7e 2142
0875546c 2143 if (dev_priv->mm.aliasing_ppgtt && vma->bound & LOCAL_BIND) {
6f65e29a 2144 struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt;
06615ee5 2145
6f65e29a 2146 appgtt->base.clear_range(&appgtt->base,
782f1495 2147 vma->node.start,
06615ee5 2148 size,
6f65e29a 2149 true);
6f65e29a 2150 }
74163907
DV		 2151}
2152
2153void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj)
7c2e6fdf 2154{
5c042287
BW		 2155 struct drm_device *dev = obj->base.dev;
2156 struct drm_i915_private *dev_priv = dev->dev_private;
2157 bool interruptible;
2158
2159 interruptible = do_idling(dev_priv);
2160
5ec5b516
ID		 2161 dma_unmap_sg(&dev->pdev->dev, obj->pages->sgl, obj->pages->nents,
2162 PCI_DMA_BIDIRECTIONAL);
5c042287
BW		 2163
2164 undo_idling(dev_priv, interruptible);
7c2e6fdf 2165}
644ec02b 2166
42d6ab48
CW		 2167static void i915_gtt_color_adjust(struct drm_mm_node *node,
2168 unsigned long color,
440fd528
TR		 2169 u64 *start,
2170 u64 *end)
42d6ab48
CW		 2171{
2172 if (node->color != color)
2173 *start += 4096;
2174
2175 if (!list_empty(&node->node_list)) {
2176 node = list_entry(node->node_list.next,
2177 struct drm_mm_node,
2178 node_list);
2179 if (node->allocated && node->color != color)
2180 *end -= 4096;
2181 }
2182}
fbe5d36e 2183
f548c0e9
DV		 2184static int i915_gem_setup_global_gtt(struct drm_device *dev,
2185 unsigned long start,
2186 unsigned long mappable_end,
2187 unsigned long end)
644ec02b 2188{
e78891ca
BW		 2189 /* Let GEM Manage all of the aperture.
2190 *
2191 * However, leave one page at the end still bound to the scratch page.
2192 * There are a number of places where the hardware apparently prefetches
2193 * past the end of the object, and we've seen multiple hangs with the
2194 * GPU head pointer stuck in a batchbuffer bound at the last page of the
2195 * aperture. One page should be enough to keep any prefetching inside
2196 * of the aperture.
2197 */
40d74980
BW		 2198 struct drm_i915_private *dev_priv = dev->dev_private;
2199 struct i915_address_space *ggtt_vm = &dev_priv->gtt.base;
ed2f3452
CW		 2200 struct drm_mm_node *entry;
2201 struct drm_i915_gem_object *obj;
2202 unsigned long hole_start, hole_end;
fa76da34 2203 int ret;
644ec02b 2204
35451cb6
BW		 2205 BUG_ON(mappable_end > end);
2206
ed2f3452 2207 /* Subtract the guard page ... */
40d74980 2208 drm_mm_init(&ggtt_vm->mm, start, end - start - PAGE_SIZE);
5dda8fa3
YZ		 2209
2210 dev_priv->gtt.base.start = start;
2211 dev_priv->gtt.base.total = end - start;
2212
2213 if (intel_vgpu_active(dev)) {
2214 ret = intel_vgt_balloon(dev);
2215 if (ret)
2216 return ret;
2217 }
2218
42d6ab48 2219 if (!HAS_LLC(dev))
93bd8649 2220 dev_priv->gtt.base.mm.color_adjust = i915_gtt_color_adjust;
644ec02b 2221
ed2f3452 2222 /* Mark any preallocated objects as occupied */
35c20a60 2223 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
40d74980 2224 struct i915_vma *vma = i915_gem_obj_to_vma(obj, ggtt_vm);
fa76da34 2225
edd41a87 2226 DRM_DEBUG_KMS("reserving preallocated space: %lx + %zx\n",
c6cfb325
BW		 2227 i915_gem_obj_ggtt_offset(obj), obj->base.size);
2228
2229 WARN_ON(i915_gem_obj_ggtt_bound(obj));
40d74980 2230 ret = drm_mm_reserve_node(&ggtt_vm->mm, &vma->node);
6c5566a8
DV		 2231 if (ret) {
2232 DRM_DEBUG_KMS("Reservation failed: %i\n", ret);
2233 return ret;
2234 }
aff43766 2235 vma->bound |= GLOBAL_BIND;
ed2f3452
CW		 2236 }
2237
ed2f3452 2238 /* Clear any non-preallocated blocks */
40d74980 2239 drm_mm_for_each_hole(entry, &ggtt_vm->mm, hole_start, hole_end) {
ed2f3452
CW		 2240 DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
2241 hole_start, hole_end);
782f1495
BW		 2242 ggtt_vm->clear_range(ggtt_vm, hole_start,
2243 hole_end - hole_start, true);
ed2f3452
CW		 2244 }
2245
2246 /* And finally clear the reserved guard page */
782f1495 2247 ggtt_vm->clear_range(ggtt_vm, end - PAGE_SIZE, PAGE_SIZE, true);
6c5566a8 2248
fa76da34
DV		 2249 if (USES_PPGTT(dev) && !USES_FULL_PPGTT(dev)) {
2250 struct i915_hw_ppgtt *ppgtt;
2251
2252 ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
2253 if (!ppgtt)
2254 return -ENOMEM;
2255
5c5f6457
DV		 2256 ret = __hw_ppgtt_init(dev, ppgtt);
2257 if (ret) {
2258 ppgtt->base.cleanup(&ppgtt->base);
2259 kfree(ppgtt);
2260 return ret;
2261 }
2262
2263 if (ppgtt->base.allocate_va_range)
2264 ret = ppgtt->base.allocate_va_range(&ppgtt->base, 0,
2265 ppgtt->base.total);
4933d519 2266 if (ret) {
061dd493 2267 ppgtt->base.cleanup(&ppgtt->base);
4933d519 2268 kfree(ppgtt);
fa76da34 2269 return ret;
4933d519 2270 }
fa76da34 2271
5c5f6457
DV		 2272 ppgtt->base.clear_range(&ppgtt->base,
2273 ppgtt->base.start,
2274 ppgtt->base.total,
2275 true);
2276
fa76da34
DV		 2277 dev_priv->mm.aliasing_ppgtt = ppgtt;
2278 }
2279
6c5566a8 2280 return 0;
e76e9aeb
BW		 2281}
2282
d7e5008f
BW		 2283void i915_gem_init_global_gtt(struct drm_device *dev)
2284{
2285 struct drm_i915_private *dev_priv = dev->dev_private;
c44ef60e 2286 u64 gtt_size, mappable_size;
d7e5008f 2287
853ba5d2 2288 gtt_size = dev_priv->gtt.base.total;
93d18799 2289 mappable_size = dev_priv->gtt.mappable_end;
d7e5008f 2290
e78891ca 2291 i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size);
e76e9aeb
BW		 2292}
2293
90d0a0e8
DV		 2294void i915_global_gtt_cleanup(struct drm_device *dev)
2295{
2296 struct drm_i915_private *dev_priv = dev->dev_private;
2297 struct i915_address_space *vm = &dev_priv->gtt.base;
2298
70e32544
DV		 2299 if (dev_priv->mm.aliasing_ppgtt) {
2300 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2301
2302 ppgtt->base.cleanup(&ppgtt->base);
2303 }
2304
90d0a0e8 2305 if (drm_mm_initialized(&vm->mm)) {
5dda8fa3
YZ		 2306 if (intel_vgpu_active(dev))
2307 intel_vgt_deballoon();
2308
90d0a0e8
DV		 2309 drm_mm_takedown(&vm->mm);
2310 list_del(&vm->global_link);
2311 }
2312
2313 vm->cleanup(vm);
2314}
70e32544 2315
2c642b07 2316static unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl)
e76e9aeb
BW		 2317{
2318 snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT;
2319 snb_gmch_ctl &= SNB_GMCH_GGMS_MASK;
2320 return snb_gmch_ctl << 20;
2321}
2322
2c642b07 2323static unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl)
9459d252
BW		 2324{
2325 bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT;
2326 bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK;
2327 if (bdw_gmch_ctl)
2328 bdw_gmch_ctl = 1 << bdw_gmch_ctl;
562d55d9
BW		 2329
2330#ifdef CONFIG_X86_32
2331 /* Limit 32b platforms to a 2GB GGTT: 4 << 20 / pte size * PAGE_SIZE */
2332 if (bdw_gmch_ctl > 4)
2333 bdw_gmch_ctl = 4;
2334#endif
2335
9459d252
BW		 2336 return bdw_gmch_ctl << 20;
2337}
2338
2c642b07 2339static unsigned int chv_get_total_gtt_size(u16 gmch_ctrl)
d7f25f23
DL		 2340{
2341 gmch_ctrl >>= SNB_GMCH_GGMS_SHIFT;
2342 gmch_ctrl &= SNB_GMCH_GGMS_MASK;
2343
2344 if (gmch_ctrl)
2345 return 1 << (20 + gmch_ctrl);
2346
2347 return 0;
2348}
2349
2c642b07 2350static size_t gen6_get_stolen_size(u16 snb_gmch_ctl)
e76e9aeb
BW		 2351{
2352 snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT;
2353 snb_gmch_ctl &= SNB_GMCH_GMS_MASK;
2354 return snb_gmch_ctl << 25; /* 32 MB units */
2355}
2356
2c642b07 2357static size_t gen8_get_stolen_size(u16 bdw_gmch_ctl)
9459d252
BW		 2358{
2359 bdw_gmch_ctl >>= BDW_GMCH_GMS_SHIFT;
2360 bdw_gmch_ctl &= BDW_GMCH_GMS_MASK;
2361 return bdw_gmch_ctl << 25; /* 32 MB units */
2362}
2363
d7f25f23
DL		 2364static size_t chv_get_stolen_size(u16 gmch_ctrl)
2365{
2366 gmch_ctrl >>= SNB_GMCH_GMS_SHIFT;
2367 gmch_ctrl &= SNB_GMCH_GMS_MASK;
2368
2369 /*
2370 * 0x0 to 0x10: 32MB increments starting at 0MB
2371 * 0x11 to 0x16: 4MB increments starting at 8MB
2372 * 0x17 to 0x1d: 4MB increments start at 36MB
2373 */
2374 if (gmch_ctrl < 0x11)
2375 return gmch_ctrl << 25;
2376 else if (gmch_ctrl < 0x17)
2377 return (gmch_ctrl - 0x11 + 2) << 22;
2378 else
2379 return (gmch_ctrl - 0x17 + 9) << 22;
2380}
2381
66375014
DL		 2382static size_t gen9_get_stolen_size(u16 gen9_gmch_ctl)
2383{
2384 gen9_gmch_ctl >>= BDW_GMCH_GMS_SHIFT;
2385 gen9_gmch_ctl &= BDW_GMCH_GMS_MASK;
2386
2387 if (gen9_gmch_ctl < 0xf0)
2388 return gen9_gmch_ctl << 25; /* 32 MB units */
2389 else
2390 /* 4MB increments starting at 0xf0 for 4MB */
2391 return (gen9_gmch_ctl - 0xf0 + 1) << 22;
2392}
2393
63340133
BW		 2394static int ggtt_probe_common(struct drm_device *dev,
2395 size_t gtt_size)
2396{
2397 struct drm_i915_private *dev_priv = dev->dev_private;
4ad2af1e 2398 struct i915_page_scratch *scratch_page;
21c34607 2399 phys_addr_t gtt_phys_addr;
63340133
BW		 2400
2401 /* For Modern GENs the PTEs and register space are split in the BAR */
21c34607 2402 gtt_phys_addr = pci_resource_start(dev->pdev, 0) +
63340133
BW		 2403 (pci_resource_len(dev->pdev, 0) / 2);
2404
2a073f89
ID		 2405 /*
2406 * On BXT writes larger than 64 bit to the GTT pagetable range will be
2407 * dropped. For WC mappings in general we have 64 byte burst writes
2408 * when the WC buffer is flushed, so we can't use it, but have to
2409 * resort to an uncached mapping. The WC issue is easily caught by the
2410 * readback check when writing GTT PTE entries.
2411 */
2412 if (IS_BROXTON(dev))
2413 dev_priv->gtt.gsm = ioremap_nocache(gtt_phys_addr, gtt_size);
2414 else
2415 dev_priv->gtt.gsm = ioremap_wc(gtt_phys_addr, gtt_size);
63340133
BW		 2416 if (!dev_priv->gtt.gsm) {
2417 DRM_ERROR("Failed to map the gtt page table\n");
2418 return -ENOMEM;
2419 }
2420
4ad2af1e
MK		 2421 scratch_page = alloc_scratch_page(dev);
2422 if (IS_ERR(scratch_page)) {
63340133
BW		 2423 DRM_ERROR("Scratch setup failed\n");
2424 /* iounmap will also get called at remove, but meh */
2425 iounmap(dev_priv->gtt.gsm);
4ad2af1e 2426 return PTR_ERR(scratch_page);
63340133
BW		 2427 }
2428
4ad2af1e
MK		 2429 dev_priv->gtt.base.scratch_page = scratch_page;
2430
2431 return 0;
63340133
BW		 2432}
2433
fbe5d36e
BW		 2434/* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability
2435 * bits. When using advanced contexts each context stores its own PAT, but
2436 * writing this data shouldn't be harmful even in those cases. */
ee0ce478 2437static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv)
fbe5d36e 2438{
fbe5d36e
BW		 2439 uint64_t pat;
2440
2441 pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC) | /* for normal objects, no eLLC */
2442 GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something pointing to ptes? */
2443 GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC) | /* for scanout with eLLC */
2444 GEN8_PPAT(3, GEN8_PPAT_UC) | /* Uncached objects, mostly for scanout */
2445 GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) |
2446 GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) |
2447 GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) |
2448 GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3));
2449
d6a8b72e
RV		 2450 if (!USES_PPGTT(dev_priv->dev))
2451 /* Spec: "For GGTT, there is NO pat_sel[2:0] from the entry,
2452 * so RTL will always use the value corresponding to
2453 * pat_sel = 000".
2454 * So let's disable cache for GGTT to avoid screen corruptions.
2455 * MOCS still can be used though.
2456 * - System agent ggtt writes (i.e. cpu gtt mmaps) already work
2457 * before this patch, i.e. the same uncached + snooping access
2458 * like on gen6/7 seems to be in effect.
2459 * - So this just fixes blitter/render access. Again it looks
2460 * like it's not just uncached access, but uncached + snooping.
2461 * So we can still hold onto all our assumptions wrt cpu
2462 * clflushing on LLC machines.
2463 */
2464 pat = GEN8_PPAT(0, GEN8_PPAT_UC);
2465
fbe5d36e
BW		 2466 /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b
2467 * write would work. */
2468 I915_WRITE(GEN8_PRIVATE_PAT, pat);
2469 I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32);
2470}
2471
ee0ce478
VS		 2472static void chv_setup_private_ppat(struct drm_i915_private *dev_priv)
2473{
2474 uint64_t pat;
2475
2476 /*
2477 * Map WB on BDW to snooped on CHV.
2478 *
2479 * Only the snoop bit has meaning for CHV, the rest is
2480 * ignored.
2481 *
cf3d262e
VS		 2482 * The hardware will never snoop for certain types of accesses:
2483 * - CPU GTT (GMADR->GGTT->no snoop->memory)
2484 * - PPGTT page tables
2485 * - some other special cycles
2486 *
2487 * As with BDW, we also need to consider the following for GT accesses:
2488 * "For GGTT, there is NO pat_sel[2:0] from the entry,
2489 * so RTL will always use the value corresponding to
2490 * pat_sel = 000".
2491 * Which means we must set the snoop bit in PAT entry 0
2492 * in order to keep the global status page working.
ee0ce478
VS		 2493 */
2494 pat = GEN8_PPAT(0, CHV_PPAT_SNOOP) |
2495 GEN8_PPAT(1, 0) |
2496 GEN8_PPAT(2, 0) |
2497 GEN8_PPAT(3, 0) |
2498 GEN8_PPAT(4, CHV_PPAT_SNOOP) |
2499 GEN8_PPAT(5, CHV_PPAT_SNOOP) |
2500 GEN8_PPAT(6, CHV_PPAT_SNOOP) |
2501 GEN8_PPAT(7, CHV_PPAT_SNOOP);
2502
2503 I915_WRITE(GEN8_PRIVATE_PAT, pat);
2504 I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32);
2505}
2506
63340133 2507static int gen8_gmch_probe(struct drm_device *dev,
c44ef60e 2508 u64 *gtt_total,
63340133
BW		 2509 size_t *stolen,
2510 phys_addr_t *mappable_base,
c44ef60e 2511 u64 *mappable_end)
63340133
BW		 2512{
2513 struct drm_i915_private *dev_priv = dev->dev_private;
c44ef60e 2514 u64 gtt_size;
63340133
BW		 2515 u16 snb_gmch_ctl;
2516 int ret;
2517
2518 /* TODO: We're not aware of mappable constraints on gen8 yet */
2519 *mappable_base = pci_resource_start(dev->pdev, 2);
2520 *mappable_end = pci_resource_len(dev->pdev, 2);
2521
2522 if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(39)))
2523 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(39));
2524
2525 pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
2526
66375014
DL		 2527 if (INTEL_INFO(dev)->gen >= 9) {
2528 *stolen = gen9_get_stolen_size(snb_gmch_ctl);
2529 gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl);
2530 } else if (IS_CHERRYVIEW(dev)) {
d7f25f23
DL		 2531 *stolen = chv_get_stolen_size(snb_gmch_ctl);
2532 gtt_size = chv_get_total_gtt_size(snb_gmch_ctl);
2533 } else {
2534 *stolen = gen8_get_stolen_size(snb_gmch_ctl);
2535 gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl);
2536 }
63340133 2537
07749ef3 2538 *gtt_total = (gtt_size / sizeof(gen8_pte_t)) << PAGE_SHIFT;
63340133 2539
5a4e33a3 2540 if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev))
ee0ce478
VS		 2541 chv_setup_private_ppat(dev_priv);
2542 else
2543 bdw_setup_private_ppat(dev_priv);
fbe5d36e 2544
63340133
BW		 2545 ret = ggtt_probe_common(dev, gtt_size);
2546
94ec8f61
BW		 2547 dev_priv->gtt.base.clear_range = gen8_ggtt_clear_range;
2548 dev_priv->gtt.base.insert_entries = gen8_ggtt_insert_entries;
777dc5bb
DV		 2549 dev_priv->gtt.base.bind_vma = ggtt_bind_vma;
2550 dev_priv->gtt.base.unbind_vma = ggtt_unbind_vma;
63340133
BW		 2551
2552 return ret;
2553}
2554
baa09f5f 2555static int gen6_gmch_probe(struct drm_device *dev,
c44ef60e 2556 u64 *gtt_total,
41907ddc
BW		 2557 size_t *stolen,
2558 phys_addr_t *mappable_base,
c44ef60e 2559 u64 *mappable_end)
e76e9aeb
BW		 2560{
2561 struct drm_i915_private *dev_priv = dev->dev_private;
baa09f5f 2562 unsigned int gtt_size;
e76e9aeb 2563 u16 snb_gmch_ctl;
e76e9aeb
BW		 2564 int ret;
2565
41907ddc
BW		 2566 *mappable_base = pci_resource_start(dev->pdev, 2);
2567 *mappable_end = pci_resource_len(dev->pdev, 2);
2568
baa09f5f
BW		 2569 /* 64/512MB is the current min/max we actually know of, but this is just
2570 * a coarse sanity check.
e76e9aeb 2571 */
41907ddc 2572 if ((*mappable_end < (64<<20) || (*mappable_end > (512<<20)))) {
c44ef60e 2573 DRM_ERROR("Unknown GMADR size (%llx)\n",
baa09f5f
BW		 2574 dev_priv->gtt.mappable_end);
2575 return -ENXIO;
e76e9aeb
BW		 2576 }
2577
e76e9aeb
BW		 2578 if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40)))
2579 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40));
e76e9aeb 2580 pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
e76e9aeb 2581
c4ae25ec 2582 *stolen = gen6_get_stolen_size(snb_gmch_ctl);
a93e4161 2583
63340133 2584 gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl);
07749ef3 2585 *gtt_total = (gtt_size / sizeof(gen6_pte_t)) << PAGE_SHIFT;
e76e9aeb 2586
63340133 2587 ret = ggtt_probe_common(dev, gtt_size);
e76e9aeb 2588
853ba5d2
BW		 2589 dev_priv->gtt.base.clear_range = gen6_ggtt_clear_range;
2590 dev_priv->gtt.base.insert_entries = gen6_ggtt_insert_entries;
777dc5bb
DV		 2591 dev_priv->gtt.base.bind_vma = ggtt_bind_vma;
2592 dev_priv->gtt.base.unbind_vma = ggtt_unbind_vma;
7faf1ab2 2593
e76e9aeb
BW		 2594 return ret;
2595}
2596
853ba5d2 2597static void gen6_gmch_remove(struct i915_address_space *vm)
e76e9aeb 2598{
853ba5d2
BW		 2599
2600 struct i915_gtt *gtt = container_of(vm, struct i915_gtt, base);
5ed16782 2601
853ba5d2 2602 iounmap(gtt->gsm);
4ad2af1e 2603 free_scratch_page(vm->dev, vm->scratch_page);
644ec02b 2604}
baa09f5f
BW		 2605
2606static int i915_gmch_probe(struct drm_device *dev,
c44ef60e 2607 u64 *gtt_total,
41907ddc
BW		 2608 size_t *stolen,
2609 phys_addr_t *mappable_base,
c44ef60e 2610 u64 *mappable_end)
baa09f5f
BW		 2611{
2612 struct drm_i915_private *dev_priv = dev->dev_private;
2613 int ret;
2614
baa09f5f
BW		 2615 ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->dev->pdev, NULL);
2616 if (!ret) {
2617 DRM_ERROR("failed to set up gmch\n");
2618 return -EIO;
2619 }
2620
41907ddc 2621 intel_gtt_get(gtt_total, stolen, mappable_base, mappable_end);
baa09f5f
BW		 2622
2623 dev_priv->gtt.do_idle_maps = needs_idle_maps(dev_priv->dev);
d369d2d9 2624 dev_priv->gtt.base.insert_entries = i915_ggtt_insert_entries;
853ba5d2 2625 dev_priv->gtt.base.clear_range = i915_ggtt_clear_range;
d369d2d9
DV		 2626 dev_priv->gtt.base.bind_vma = ggtt_bind_vma;
2627 dev_priv->gtt.base.unbind_vma = ggtt_unbind_vma;
baa09f5f 2628
c0a7f818
CW		 2629 if (unlikely(dev_priv->gtt.do_idle_maps))
2630 DRM_INFO("applying Ironlake quirks for intel_iommu\n");
2631
baa09f5f
BW		 2632 return 0;
2633}
2634
853ba5d2 2635static void i915_gmch_remove(struct i915_address_space *vm)
baa09f5f
BW		 2636{
2637 intel_gmch_remove();
2638}
2639
2640int i915_gem_gtt_init(struct drm_device *dev)
2641{
2642 struct drm_i915_private *dev_priv = dev->dev_private;
2643 struct i915_gtt *gtt = &dev_priv->gtt;
baa09f5f
BW		 2644 int ret;
2645
baa09f5f 2646 if (INTEL_INFO(dev)->gen <= 5) {
b2f21b4d 2647 gtt->gtt_probe = i915_gmch_probe;
853ba5d2 2648 gtt->base.cleanup = i915_gmch_remove;
63340133 2649 } else if (INTEL_INFO(dev)->gen < 8) {
b2f21b4d 2650 gtt->gtt_probe = gen6_gmch_probe;
853ba5d2 2651 gtt->base.cleanup = gen6_gmch_remove;
4d15c145 2652 if (IS_HASWELL(dev) && dev_priv->ellc_size)
853ba5d2 2653 gtt->base.pte_encode = iris_pte_encode;
4d15c145 2654 else if (IS_HASWELL(dev))
853ba5d2 2655 gtt->base.pte_encode = hsw_pte_encode;
b2f21b4d 2656 else if (IS_VALLEYVIEW(dev))
853ba5d2 2657 gtt->base.pte_encode = byt_pte_encode;
350ec881
CW		 2658 else if (INTEL_INFO(dev)->gen >= 7)
2659 gtt->base.pte_encode = ivb_pte_encode;
b2f21b4d 2660 else
350ec881 2661 gtt->base.pte_encode = snb_pte_encode;
63340133
BW		 2662 } else {
2663 dev_priv->gtt.gtt_probe = gen8_gmch_probe;
2664 dev_priv->gtt.base.cleanup = gen6_gmch_remove;
baa09f5f
BW		 2665 }
2666
c114f76a
MK		 2667 gtt->base.dev = dev;
2668
853ba5d2 2669 ret = gtt->gtt_probe(dev, &gtt->base.total, &gtt->stolen_size,
b2f21b4d 2670 &gtt->mappable_base, &gtt->mappable_end);
a54c0c27 2671 if (ret)
baa09f5f 2672 return ret;
baa09f5f 2673
baa09f5f 2674 /* GMADR is the PCI mmio aperture into the global GTT. */
c44ef60e 2675 DRM_INFO("Memory usable by graphics device = %lluM\n",
853ba5d2 2676 gtt->base.total >> 20);
c44ef60e 2677 DRM_DEBUG_DRIVER("GMADR size = %lldM\n", gtt->mappable_end >> 20);
b2f21b4d 2678 DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt->stolen_size >> 20);
5db6c735
DV		 2679#ifdef CONFIG_INTEL_IOMMU
2680 if (intel_iommu_gfx_mapped)
2681 DRM_INFO("VT-d active for gfx access\n");
2682#endif
cfa7c862
DV		 2683 /*
2684 * i915.enable_ppgtt is read-only, so do an early pass to validate the
2685 * user's requested state against the hardware/driver capabilities. We
2686 * do this now so that we can print out any log messages once rather
2687 * than every time we check intel_enable_ppgtt().
2688 */
2689 i915.enable_ppgtt = sanitize_enable_ppgtt(dev, i915.enable_ppgtt);
2690 DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915.enable_ppgtt);
baa09f5f
BW		 2691
2692 return 0;
2693}
6f65e29a 2694
fa42331b
DV		 2695void i915_gem_restore_gtt_mappings(struct drm_device *dev)
2696{
2697 struct drm_i915_private *dev_priv = dev->dev_private;
2698 struct drm_i915_gem_object *obj;
2699 struct i915_address_space *vm;
2c3d9984
TU		 2700 struct i915_vma *vma;
2701 bool flush;
fa42331b
DV		 2702
2703 i915_check_and_clear_faults(dev);
2704
2705 /* First fill our portion of the GTT with scratch pages */
2706 dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
2707 dev_priv->gtt.base.start,
2708 dev_priv->gtt.base.total,
2709 true);
2710
2c3d9984
TU		 2711 /* Cache flush objects bound into GGTT and rebind them. */
2712 vm = &dev_priv->gtt.base;
fa42331b 2713 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
2c3d9984
TU		 2714 flush = false;
2715 list_for_each_entry(vma, &obj->vma_list, vma_link) {
2716 if (vma->vm != vm)
2717 continue;
fa42331b 2718
2c3d9984
TU		 2719 WARN_ON(i915_vma_bind(vma, obj->cache_level,
2720 PIN_UPDATE));
fa42331b 2721
2c3d9984
TU		 2722 flush = true;
2723 }
2724
2725 if (flush)
2726 i915_gem_clflush_object(obj, obj->pin_display);
2727 }
fa42331b
DV		 2728
2729 if (INTEL_INFO(dev)->gen >= 8) {
2730 if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev))
2731 chv_setup_private_ppat(dev_priv);
2732 else
2733 bdw_setup_private_ppat(dev_priv);
2734
2735 return;
2736 }
2737
2738 if (USES_PPGTT(dev)) {
2739 list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
2740 /* TODO: Perhaps it shouldn't be gen6 specific */
2741
2742 struct i915_hw_ppgtt *ppgtt =
2743 container_of(vm, struct i915_hw_ppgtt,
2744 base);
2745
2746 if (i915_is_ggtt(vm))
2747 ppgtt = dev_priv->mm.aliasing_ppgtt;
2748
2749 gen6_write_page_range(dev_priv, &ppgtt->pd,
2750 0, ppgtt->base.total);
2751 }
2752 }
2753
2754 i915_ggtt_flush(dev_priv);
2755}
2756
ec7adb6e
JL		 2757static struct i915_vma *
2758__i915_gem_vma_create(struct drm_i915_gem_object *obj,
2759 struct i915_address_space *vm,
2760 const struct i915_ggtt_view *ggtt_view)
6f65e29a 2761{
dabde5c7 2762 struct i915_vma *vma;
6f65e29a 2763
ec7adb6e
JL		 2764 if (WARN_ON(i915_is_ggtt(vm) != !!ggtt_view))
2765 return ERR_PTR(-EINVAL);
e20d2ab7
CW		 2766
2767 vma = kmem_cache_zalloc(to_i915(obj->base.dev)->vmas, GFP_KERNEL);
dabde5c7
DC		 2768 if (vma == NULL)
2769 return ERR_PTR(-ENOMEM);
ec7adb6e 2770
6f65e29a
BW		 2771 INIT_LIST_HEAD(&vma->vma_link);
2772 INIT_LIST_HEAD(&vma->mm_list);
2773 INIT_LIST_HEAD(&vma->exec_list);
2774 vma->vm = vm;
2775 vma->obj = obj;
2776
777dc5bb 2777 if (i915_is_ggtt(vm))
ec7adb6e 2778 vma->ggtt_view = *ggtt_view;
6f65e29a 2779
f7635669
TU		 2780 list_add_tail(&vma->vma_link, &obj->vma_list);
2781 if (!i915_is_ggtt(vm))
e07f0552 2782 i915_ppgtt_get(i915_vm_to_ppgtt(vm));
6f65e29a
BW		 2783
2784 return vma;
2785}
2786
2787struct i915_vma *
ec7adb6e
JL		 2788i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
2789 struct i915_address_space *vm)
2790{
2791 struct i915_vma *vma;
2792
2793 vma = i915_gem_obj_to_vma(obj, vm);
2794 if (!vma)
2795 vma = __i915_gem_vma_create(obj, vm,
2796 i915_is_ggtt(vm) ? &i915_ggtt_view_normal : NULL);
2797
2798 return vma;
2799}
2800
2801struct i915_vma *
2802i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object *obj,
fe14d5f4 2803 const struct i915_ggtt_view *view)
6f65e29a 2804{
ec7adb6e 2805 struct i915_address_space *ggtt = i915_obj_to_ggtt(obj);
6f65e29a
BW		 2806 struct i915_vma *vma;
2807
ec7adb6e
JL		 2808 if (WARN_ON(!view))
2809 return ERR_PTR(-EINVAL);
2810
2811 vma = i915_gem_obj_to_ggtt_view(obj, view);
2812
2813 if (IS_ERR(vma))
2814 return vma;
2815
6f65e29a 2816 if (!vma)
ec7adb6e 2817 vma = __i915_gem_vma_create(obj, ggtt, view);
6f65e29a
BW		 2818
2819 return vma;
ec7adb6e 2820
6f65e29a 2821}
fe14d5f4 2822
50470bb0
TU		 2823static void
2824rotate_pages(dma_addr_t *in, unsigned int width, unsigned int height,
2825 struct sg_table *st)
2826{
2827 unsigned int column, row;
2828 unsigned int src_idx;
2829 struct scatterlist *sg = st->sgl;
2830
2831 st->nents = 0;
2832
2833 for (column = 0; column < width; column++) {
2834 src_idx = width * (height - 1) + column;
2835 for (row = 0; row < height; row++) {
2836 st->nents++;
2837 /* We don't need the pages, but need to initialize
2838 * the entries so the sg list can be happily traversed.
2839 * The only thing we need are DMA addresses.
2840 */
2841 sg_set_page(sg, NULL, PAGE_SIZE, 0);
2842 sg_dma_address(sg) = in[src_idx];
2843 sg_dma_len(sg) = PAGE_SIZE;
2844 sg = sg_next(sg);
2845 src_idx -= width;
2846 }
2847 }
2848}
2849
2850static struct sg_table *
2851intel_rotate_fb_obj_pages(struct i915_ggtt_view *ggtt_view,
2852 struct drm_i915_gem_object *obj)
2853{
50470bb0 2854 struct intel_rotation_info *rot_info = &ggtt_view->rotation_info;
84fe03f7 2855 unsigned int size_pages = rot_info->size >> PAGE_SHIFT;
50470bb0
TU		 2856 struct sg_page_iter sg_iter;
2857 unsigned long i;
2858 dma_addr_t *page_addr_list;
2859 struct sg_table *st;
1d00dad5 2860 int ret = -ENOMEM;
50470bb0 2861
50470bb0 2862 /* Allocate a temporary list of source pages for random access. */
84fe03f7
TU		 2863 page_addr_list = drm_malloc_ab(obj->base.size / PAGE_SIZE,
2864 sizeof(dma_addr_t));
50470bb0
TU		 2865 if (!page_addr_list)
2866 return ERR_PTR(ret);
2867
2868 /* Allocate target SG list. */
2869 st = kmalloc(sizeof(*st), GFP_KERNEL);
2870 if (!st)
2871 goto err_st_alloc;
2872
84fe03f7 2873 ret = sg_alloc_table(st, size_pages, GFP_KERNEL);
50470bb0
TU		 2874 if (ret)
2875 goto err_sg_alloc;
2876
2877 /* Populate source page list from the object. */
2878 i = 0;
2879 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
2880 page_addr_list[i] = sg_page_iter_dma_address(&sg_iter);
2881 i++;
2882 }
2883
2884 /* Rotate the pages. */
84fe03f7
TU		 2885 rotate_pages(page_addr_list,
2886 rot_info->width_pages, rot_info->height_pages,
2887 st);
50470bb0
TU		 2888
2889 DRM_DEBUG_KMS(
84fe03f7 2890 "Created rotated page mapping for object size %zu (pitch=%u, height=%u, pixel_format=0x%x, %ux%u tiles, %u pages).\n",
c9f8fd2d 2891 obj->base.size, rot_info->pitch, rot_info->height,
84fe03f7
TU		 2892 rot_info->pixel_format, rot_info->width_pages,
2893 rot_info->height_pages, size_pages);
50470bb0
TU		 2894
2895 drm_free_large(page_addr_list);
2896
2897 return st;
2898
2899err_sg_alloc:
2900 kfree(st);
2901err_st_alloc:
2902 drm_free_large(page_addr_list);
2903
2904 DRM_DEBUG_KMS(
84fe03f7 2905 "Failed to create rotated mapping for object size %zu! (%d) (pitch=%u, height=%u, pixel_format=0x%x, %ux%u tiles, %u pages)\n",
c9f8fd2d 2906 obj->base.size, ret, rot_info->pitch, rot_info->height,
84fe03f7
TU		 2907 rot_info->pixel_format, rot_info->width_pages,
2908 rot_info->height_pages, size_pages);
50470bb0
TU		 2909 return ERR_PTR(ret);
2910}
ec7adb6e 2911
8bd7ef16
JL		 2912static struct sg_table *
2913intel_partial_pages(const struct i915_ggtt_view *view,
2914 struct drm_i915_gem_object *obj)
2915{
2916 struct sg_table *st;
2917 struct scatterlist *sg;
2918 struct sg_page_iter obj_sg_iter;
2919 int ret = -ENOMEM;
2920
2921 st = kmalloc(sizeof(*st), GFP_KERNEL);
2922 if (!st)
2923 goto err_st_alloc;
2924
2925 ret = sg_alloc_table(st, view->params.partial.size, GFP_KERNEL);
2926 if (ret)
2927 goto err_sg_alloc;
2928
2929 sg = st->sgl;
2930 st->nents = 0;
2931 for_each_sg_page(obj->pages->sgl, &obj_sg_iter, obj->pages->nents,
2932 view->params.partial.offset)
2933 {
2934 if (st->nents >= view->params.partial.size)
2935 break;
2936
2937 sg_set_page(sg, NULL, PAGE_SIZE, 0);
2938 sg_dma_address(sg) = sg_page_iter_dma_address(&obj_sg_iter);
2939 sg_dma_len(sg) = PAGE_SIZE;
2940
2941 sg = sg_next(sg);
2942 st->nents++;
2943 }
2944
2945 return st;
2946
2947err_sg_alloc:
2948 kfree(st);
2949err_st_alloc:
2950 return ERR_PTR(ret);
2951}
2952
70b9f6f8 2953static int
50470bb0 2954i915_get_ggtt_vma_pages(struct i915_vma *vma)
fe14d5f4 2955{
50470bb0
TU		 2956 int ret = 0;
2957
fe14d5f4
TU		 2958 if (vma->ggtt_view.pages)
2959 return 0;
2960
2961 if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL)
2962 vma->ggtt_view.pages = vma->obj->pages;
50470bb0
TU		 2963 else if (vma->ggtt_view.type == I915_GGTT_VIEW_ROTATED)
2964 vma->ggtt_view.pages =
2965 intel_rotate_fb_obj_pages(&vma->ggtt_view, vma->obj);
8bd7ef16
JL		 2966 else if (vma->ggtt_view.type == I915_GGTT_VIEW_PARTIAL)
2967 vma->ggtt_view.pages =
2968 intel_partial_pages(&vma->ggtt_view, vma->obj);
fe14d5f4
TU		 2969 else
2970 WARN_ONCE(1, "GGTT view %u not implemented!\n",
2971 vma->ggtt_view.type);
2972
2973 if (!vma->ggtt_view.pages) {
ec7adb6e 2974 DRM_ERROR("Failed to get pages for GGTT view type %u!\n",
fe14d5f4 2975 vma->ggtt_view.type);
50470bb0
TU		 2976 ret = -EINVAL;
2977 } else if (IS_ERR(vma->ggtt_view.pages)) {
2978 ret = PTR_ERR(vma->ggtt_view.pages);
2979 vma->ggtt_view.pages = NULL;
2980 DRM_ERROR("Failed to get pages for VMA view type %u (%d)!\n",
2981 vma->ggtt_view.type, ret);
fe14d5f4
TU		 2982 }
2983
50470bb0 2984 return ret;
fe14d5f4
TU		 2985}
2986
2987/**
2988 * i915_vma_bind - Sets up PTEs for an VMA in it's corresponding address space.
2989 * @vma: VMA to map
2990 * @cache_level: mapping cache level
2991 * @flags: flags like global or local mapping
2992 *
2993 * DMA addresses are taken from the scatter-gather table of this object (or of
2994 * this VMA in case of non-default GGTT views) and PTE entries set up.
2995 * Note that DMA addresses are also the only part of the SG table we care about.
2996 */
2997int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level,
2998 u32 flags)
2999{
75d04a37
MK		 3000 int ret;
3001 u32 bind_flags;
1d335d1b 3002
75d04a37
MK		 3003 if (WARN_ON(flags == 0))
3004 return -EINVAL;
1d335d1b 3005
75d04a37 3006 bind_flags = 0;
0875546c
DV		 3007 if (flags & PIN_GLOBAL)
3008 bind_flags |= GLOBAL_BIND;
3009 if (flags & PIN_USER)
3010 bind_flags |= LOCAL_BIND;
3011
3012 if (flags & PIN_UPDATE)
3013 bind_flags |= vma->bound;
3014 else
3015 bind_flags &= ~vma->bound;
3016
75d04a37
MK		 3017 if (bind_flags == 0)
3018 return 0;
3019
3020 if (vma->bound == 0 && vma->vm->allocate_va_range) {
3021 trace_i915_va_alloc(vma->vm,
3022 vma->node.start,
3023 vma->node.size,
3024 VM_TO_TRACE_NAME(vma->vm));
3025
b2dd4511
MK		 3026 /* XXX: i915_vma_pin() will fix this +- hack */
3027 vma->pin_count++;
75d04a37
MK		 3028 ret = vma->vm->allocate_va_range(vma->vm,
3029 vma->node.start,
3030 vma->node.size);
b2dd4511 3031 vma->pin_count--;
75d04a37
MK		 3032 if (ret)
3033 return ret;
3034 }
3035
3036 ret = vma->vm->bind_vma(vma, cache_level, bind_flags);
70b9f6f8
DV		 3037 if (ret)
3038 return ret;
0875546c
DV		 3039
3040 vma->bound |= bind_flags;
fe14d5f4
TU		 3041
3042 return 0;
3043}
91e6711e
JL		 3044
3045/**
3046 * i915_ggtt_view_size - Get the size of a GGTT view.
3047 * @obj: Object the view is of.
3048 * @view: The view in question.
3049 *
3050 * @return The size of the GGTT view in bytes.
3051 */
3052size_t
3053i915_ggtt_view_size(struct drm_i915_gem_object *obj,
3054 const struct i915_ggtt_view *view)
3055{
9e759ff1 3056 if (view->type == I915_GGTT_VIEW_NORMAL) {
91e6711e 3057 return obj->base.size;
9e759ff1
TU		 3058 } else if (view->type == I915_GGTT_VIEW_ROTATED) {
3059 return view->rotation_info.size;
8bd7ef16
JL		 3060 } else if (view->type == I915_GGTT_VIEW_PARTIAL) {
3061 return view->params.partial.size << PAGE_SHIFT;
91e6711e
JL		 3062 } else {
3063 WARN_ONCE(1, "GGTT view %u not implemented!\n", view->type);
3064 return obj->base.size;
3065 }
3066}
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