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76aaf220 DV |
1 | /* |
2 | * Copyright © 2010 Daniel Vetter | |
c4ac524c | 3 | * Copyright © 2011-2014 Intel Corporation |
76aaf220 DV |
4 | * |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
22 | * IN THE SOFTWARE. | |
23 | * | |
24 | */ | |
25 | ||
0e46ce2e | 26 | #include <linux/seq_file.h> |
5bab6f60 | 27 | #include <linux/stop_machine.h> |
760285e7 DH |
28 | #include <drm/drmP.h> |
29 | #include <drm/i915_drm.h> | |
76aaf220 | 30 | #include "i915_drv.h" |
5dda8fa3 | 31 | #include "i915_vgpu.h" |
76aaf220 DV |
32 | #include "i915_trace.h" |
33 | #include "intel_drv.h" | |
d07f0e59 | 34 | #include "intel_frontbuffer.h" |
76aaf220 | 35 | |
bb8f9cff CW |
36 | #define I915_GFP_DMA (GFP_KERNEL | __GFP_HIGHMEM) |
37 | ||
45f8f69a TU |
38 | /** |
39 | * DOC: Global GTT views | |
40 | * | |
41 | * Background and previous state | |
42 | * | |
43 | * Historically objects could exists (be bound) in global GTT space only as | |
44 | * singular instances with a view representing all of the object's backing pages | |
45 | * in a linear fashion. This view will be called a normal view. | |
46 | * | |
47 | * To support multiple views of the same object, where the number of mapped | |
48 | * pages is not equal to the backing store, or where the layout of the pages | |
49 | * is not linear, concept of a GGTT view was added. | |
50 | * | |
51 | * One example of an alternative view is a stereo display driven by a single | |
52 | * image. In this case we would have a framebuffer looking like this | |
53 | * (2x2 pages): | |
54 | * | |
55 | * 12 | |
56 | * 34 | |
57 | * | |
58 | * Above would represent a normal GGTT view as normally mapped for GPU or CPU | |
59 | * rendering. In contrast, fed to the display engine would be an alternative | |
60 | * view which could look something like this: | |
61 | * | |
62 | * 1212 | |
63 | * 3434 | |
64 | * | |
65 | * In this example both the size and layout of pages in the alternative view is | |
66 | * different from the normal view. | |
67 | * | |
68 | * Implementation and usage | |
69 | * | |
70 | * GGTT views are implemented using VMAs and are distinguished via enum | |
71 | * i915_ggtt_view_type and struct i915_ggtt_view. | |
72 | * | |
73 | * A new flavour of core GEM functions which work with GGTT bound objects were | |
ec7adb6e JL |
74 | * added with the _ggtt_ infix, and sometimes with _view postfix to avoid |
75 | * renaming in large amounts of code. They take the struct i915_ggtt_view | |
76 | * parameter encapsulating all metadata required to implement a view. | |
45f8f69a TU |
77 | * |
78 | * As a helper for callers which are only interested in the normal view, | |
79 | * globally const i915_ggtt_view_normal singleton instance exists. All old core | |
80 | * GEM API functions, the ones not taking the view parameter, are operating on, | |
81 | * or with the normal GGTT view. | |
82 | * | |
83 | * Code wanting to add or use a new GGTT view needs to: | |
84 | * | |
85 | * 1. Add a new enum with a suitable name. | |
86 | * 2. Extend the metadata in the i915_ggtt_view structure if required. | |
87 | * 3. Add support to i915_get_vma_pages(). | |
88 | * | |
89 | * New views are required to build a scatter-gather table from within the | |
90 | * i915_get_vma_pages function. This table is stored in the vma.ggtt_view and | |
91 | * exists for the lifetime of an VMA. | |
92 | * | |
93 | * Core API is designed to have copy semantics which means that passed in | |
94 | * struct i915_ggtt_view does not need to be persistent (left around after | |
95 | * calling the core API functions). | |
96 | * | |
97 | */ | |
98 | ||
70b9f6f8 DV |
99 | static int |
100 | i915_get_ggtt_vma_pages(struct i915_vma *vma); | |
101 | ||
b5e16987 VS |
102 | const struct i915_ggtt_view i915_ggtt_view_normal = { |
103 | .type = I915_GGTT_VIEW_NORMAL, | |
104 | }; | |
9abc4648 | 105 | const struct i915_ggtt_view i915_ggtt_view_rotated = { |
b5e16987 | 106 | .type = I915_GGTT_VIEW_ROTATED, |
9abc4648 | 107 | }; |
fe14d5f4 | 108 | |
c033666a CW |
109 | int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv, |
110 | int enable_ppgtt) | |
cfa7c862 | 111 | { |
1893a71b CW |
112 | bool has_aliasing_ppgtt; |
113 | bool has_full_ppgtt; | |
1f9a99e0 | 114 | bool has_full_48bit_ppgtt; |
1893a71b | 115 | |
c033666a CW |
116 | has_aliasing_ppgtt = INTEL_GEN(dev_priv) >= 6; |
117 | has_full_ppgtt = INTEL_GEN(dev_priv) >= 7; | |
118 | has_full_48bit_ppgtt = | |
119 | IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9; | |
1893a71b | 120 | |
e320d400 ZW |
121 | if (intel_vgpu_active(dev_priv)) { |
122 | /* emulation is too hard */ | |
123 | has_full_ppgtt = false; | |
124 | has_full_48bit_ppgtt = false; | |
125 | } | |
71ba2d64 | 126 | |
0e4ca100 CW |
127 | if (!has_aliasing_ppgtt) |
128 | return 0; | |
129 | ||
70ee45e1 DL |
130 | /* |
131 | * We don't allow disabling PPGTT for gen9+ as it's a requirement for | |
132 | * execlists, the sole mechanism available to submit work. | |
133 | */ | |
c033666a | 134 | if (enable_ppgtt == 0 && INTEL_GEN(dev_priv) < 9) |
cfa7c862 DV |
135 | return 0; |
136 | ||
137 | if (enable_ppgtt == 1) | |
138 | return 1; | |
139 | ||
1893a71b | 140 | if (enable_ppgtt == 2 && has_full_ppgtt) |
cfa7c862 DV |
141 | return 2; |
142 | ||
1f9a99e0 MT |
143 | if (enable_ppgtt == 3 && has_full_48bit_ppgtt) |
144 | return 3; | |
145 | ||
93a25a9e DV |
146 | #ifdef CONFIG_INTEL_IOMMU |
147 | /* Disable ppgtt on SNB if VT-d is on. */ | |
c033666a | 148 | if (IS_GEN6(dev_priv) && intel_iommu_gfx_mapped) { |
93a25a9e | 149 | DRM_INFO("Disabling PPGTT because VT-d is on\n"); |
cfa7c862 | 150 | return 0; |
93a25a9e DV |
151 | } |
152 | #endif | |
153 | ||
62942ed7 | 154 | /* Early VLV doesn't have this */ |
91c8a326 | 155 | if (IS_VALLEYVIEW(dev_priv) && dev_priv->drm.pdev->revision < 0xb) { |
62942ed7 JB |
156 | DRM_DEBUG_DRIVER("disabling PPGTT on pre-B3 step VLV\n"); |
157 | return 0; | |
158 | } | |
159 | ||
e320d400 | 160 | if (INTEL_GEN(dev_priv) >= 8 && i915.enable_execlists && has_full_ppgtt) |
1f9a99e0 | 161 | return has_full_48bit_ppgtt ? 3 : 2; |
2f82bbdf MT |
162 | else |
163 | return has_aliasing_ppgtt ? 1 : 0; | |
93a25a9e DV |
164 | } |
165 | ||
70b9f6f8 DV |
166 | static int ppgtt_bind_vma(struct i915_vma *vma, |
167 | enum i915_cache_level cache_level, | |
168 | u32 unused) | |
47552659 DV |
169 | { |
170 | u32 pte_flags = 0; | |
171 | ||
a4f5ea64 | 172 | vma->pages = vma->obj->mm.pages; |
247177dd | 173 | |
47552659 DV |
174 | /* Currently applicable only to VLV */ |
175 | if (vma->obj->gt_ro) | |
176 | pte_flags |= PTE_READ_ONLY; | |
177 | ||
247177dd | 178 | vma->vm->insert_entries(vma->vm, vma->pages, vma->node.start, |
47552659 | 179 | cache_level, pte_flags); |
70b9f6f8 DV |
180 | |
181 | return 0; | |
47552659 DV |
182 | } |
183 | ||
184 | static void ppgtt_unbind_vma(struct i915_vma *vma) | |
185 | { | |
186 | vma->vm->clear_range(vma->vm, | |
187 | vma->node.start, | |
4fb84d99 | 188 | vma->size); |
47552659 | 189 | } |
6f65e29a | 190 | |
2c642b07 | 191 | static gen8_pte_t gen8_pte_encode(dma_addr_t addr, |
4fb84d99 | 192 | enum i915_cache_level level) |
94ec8f61 | 193 | { |
4fb84d99 | 194 | gen8_pte_t pte = _PAGE_PRESENT | _PAGE_RW; |
94ec8f61 | 195 | pte |= addr; |
63c42e56 BW |
196 | |
197 | switch (level) { | |
198 | case I915_CACHE_NONE: | |
fbe5d36e | 199 | pte |= PPAT_UNCACHED_INDEX; |
63c42e56 BW |
200 | break; |
201 | case I915_CACHE_WT: | |
202 | pte |= PPAT_DISPLAY_ELLC_INDEX; | |
203 | break; | |
204 | default: | |
205 | pte |= PPAT_CACHED_INDEX; | |
206 | break; | |
207 | } | |
208 | ||
94ec8f61 BW |
209 | return pte; |
210 | } | |
211 | ||
fe36f55d MK |
212 | static gen8_pde_t gen8_pde_encode(const dma_addr_t addr, |
213 | const enum i915_cache_level level) | |
b1fe6673 | 214 | { |
07749ef3 | 215 | gen8_pde_t pde = _PAGE_PRESENT | _PAGE_RW; |
b1fe6673 BW |
216 | pde |= addr; |
217 | if (level != I915_CACHE_NONE) | |
218 | pde |= PPAT_CACHED_PDE_INDEX; | |
219 | else | |
220 | pde |= PPAT_UNCACHED_INDEX; | |
221 | return pde; | |
222 | } | |
223 | ||
762d9936 MT |
224 | #define gen8_pdpe_encode gen8_pde_encode |
225 | #define gen8_pml4e_encode gen8_pde_encode | |
226 | ||
07749ef3 MT |
227 | static gen6_pte_t snb_pte_encode(dma_addr_t addr, |
228 | enum i915_cache_level level, | |
4fb84d99 | 229 | u32 unused) |
54d12527 | 230 | { |
4fb84d99 | 231 | gen6_pte_t pte = GEN6_PTE_VALID; |
54d12527 | 232 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
e7210c3c BW |
233 | |
234 | switch (level) { | |
350ec881 CW |
235 | case I915_CACHE_L3_LLC: |
236 | case I915_CACHE_LLC: | |
237 | pte |= GEN6_PTE_CACHE_LLC; | |
238 | break; | |
239 | case I915_CACHE_NONE: | |
240 | pte |= GEN6_PTE_UNCACHED; | |
241 | break; | |
242 | default: | |
5f77eeb0 | 243 | MISSING_CASE(level); |
350ec881 CW |
244 | } |
245 | ||
246 | return pte; | |
247 | } | |
248 | ||
07749ef3 MT |
249 | static gen6_pte_t ivb_pte_encode(dma_addr_t addr, |
250 | enum i915_cache_level level, | |
4fb84d99 | 251 | u32 unused) |
350ec881 | 252 | { |
4fb84d99 | 253 | gen6_pte_t pte = GEN6_PTE_VALID; |
350ec881 CW |
254 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
255 | ||
256 | switch (level) { | |
257 | case I915_CACHE_L3_LLC: | |
258 | pte |= GEN7_PTE_CACHE_L3_LLC; | |
e7210c3c BW |
259 | break; |
260 | case I915_CACHE_LLC: | |
261 | pte |= GEN6_PTE_CACHE_LLC; | |
262 | break; | |
263 | case I915_CACHE_NONE: | |
9119708c | 264 | pte |= GEN6_PTE_UNCACHED; |
e7210c3c BW |
265 | break; |
266 | default: | |
5f77eeb0 | 267 | MISSING_CASE(level); |
e7210c3c BW |
268 | } |
269 | ||
54d12527 BW |
270 | return pte; |
271 | } | |
272 | ||
07749ef3 MT |
273 | static gen6_pte_t byt_pte_encode(dma_addr_t addr, |
274 | enum i915_cache_level level, | |
4fb84d99 | 275 | u32 flags) |
93c34e70 | 276 | { |
4fb84d99 | 277 | gen6_pte_t pte = GEN6_PTE_VALID; |
93c34e70 KG |
278 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
279 | ||
24f3a8cf AG |
280 | if (!(flags & PTE_READ_ONLY)) |
281 | pte |= BYT_PTE_WRITEABLE; | |
93c34e70 KG |
282 | |
283 | if (level != I915_CACHE_NONE) | |
284 | pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES; | |
285 | ||
286 | return pte; | |
287 | } | |
288 | ||
07749ef3 MT |
289 | static gen6_pte_t hsw_pte_encode(dma_addr_t addr, |
290 | enum i915_cache_level level, | |
4fb84d99 | 291 | u32 unused) |
9119708c | 292 | { |
4fb84d99 | 293 | gen6_pte_t pte = GEN6_PTE_VALID; |
0d8ff15e | 294 | pte |= HSW_PTE_ADDR_ENCODE(addr); |
9119708c KG |
295 | |
296 | if (level != I915_CACHE_NONE) | |
87a6b688 | 297 | pte |= HSW_WB_LLC_AGE3; |
9119708c KG |
298 | |
299 | return pte; | |
300 | } | |
301 | ||
07749ef3 MT |
302 | static gen6_pte_t iris_pte_encode(dma_addr_t addr, |
303 | enum i915_cache_level level, | |
4fb84d99 | 304 | u32 unused) |
4d15c145 | 305 | { |
4fb84d99 | 306 | gen6_pte_t pte = GEN6_PTE_VALID; |
4d15c145 BW |
307 | pte |= HSW_PTE_ADDR_ENCODE(addr); |
308 | ||
651d794f CW |
309 | switch (level) { |
310 | case I915_CACHE_NONE: | |
311 | break; | |
312 | case I915_CACHE_WT: | |
c51e9701 | 313 | pte |= HSW_WT_ELLC_LLC_AGE3; |
651d794f CW |
314 | break; |
315 | default: | |
c51e9701 | 316 | pte |= HSW_WB_ELLC_LLC_AGE3; |
651d794f CW |
317 | break; |
318 | } | |
4d15c145 BW |
319 | |
320 | return pte; | |
321 | } | |
322 | ||
275a991c | 323 | static int __setup_page_dma(struct drm_i915_private *dev_priv, |
c114f76a | 324 | struct i915_page_dma *p, gfp_t flags) |
678d96fb | 325 | { |
275a991c | 326 | struct device *kdev = &dev_priv->drm.pdev->dev; |
678d96fb | 327 | |
c114f76a | 328 | p->page = alloc_page(flags); |
44159ddb MK |
329 | if (!p->page) |
330 | return -ENOMEM; | |
678d96fb | 331 | |
c49d13ee | 332 | p->daddr = dma_map_page(kdev, |
44159ddb | 333 | p->page, 0, 4096, PCI_DMA_BIDIRECTIONAL); |
678d96fb | 334 | |
c49d13ee | 335 | if (dma_mapping_error(kdev, p->daddr)) { |
44159ddb MK |
336 | __free_page(p->page); |
337 | return -EINVAL; | |
338 | } | |
1266cdb1 MT |
339 | |
340 | return 0; | |
678d96fb BW |
341 | } |
342 | ||
275a991c TU |
343 | static int setup_page_dma(struct drm_i915_private *dev_priv, |
344 | struct i915_page_dma *p) | |
c114f76a | 345 | { |
275a991c | 346 | return __setup_page_dma(dev_priv, p, I915_GFP_DMA); |
c114f76a MK |
347 | } |
348 | ||
275a991c TU |
349 | static void cleanup_page_dma(struct drm_i915_private *dev_priv, |
350 | struct i915_page_dma *p) | |
06fda602 | 351 | { |
275a991c | 352 | struct pci_dev *pdev = dev_priv->drm.pdev; |
52a05c30 | 353 | |
44159ddb | 354 | if (WARN_ON(!p->page)) |
06fda602 | 355 | return; |
678d96fb | 356 | |
52a05c30 | 357 | dma_unmap_page(&pdev->dev, p->daddr, 4096, PCI_DMA_BIDIRECTIONAL); |
44159ddb MK |
358 | __free_page(p->page); |
359 | memset(p, 0, sizeof(*p)); | |
360 | } | |
361 | ||
d1c54acd | 362 | static void *kmap_page_dma(struct i915_page_dma *p) |
73eeea53 | 363 | { |
d1c54acd MK |
364 | return kmap_atomic(p->page); |
365 | } | |
73eeea53 | 366 | |
d1c54acd MK |
367 | /* We use the flushing unmap only with ppgtt structures: |
368 | * page directories, page tables and scratch pages. | |
369 | */ | |
e2d214ae | 370 | static void kunmap_page_dma(struct drm_i915_private *dev_priv, void *vaddr) |
d1c54acd | 371 | { |
73eeea53 MK |
372 | /* There are only few exceptions for gen >=6. chv and bxt. |
373 | * And we are not sure about the latter so play safe for now. | |
374 | */ | |
e2d214ae | 375 | if (IS_CHERRYVIEW(dev_priv) || IS_BROXTON(dev_priv)) |
73eeea53 MK |
376 | drm_clflush_virt_range(vaddr, PAGE_SIZE); |
377 | ||
378 | kunmap_atomic(vaddr); | |
379 | } | |
380 | ||
567047be | 381 | #define kmap_px(px) kmap_page_dma(px_base(px)) |
e2d214ae | 382 | #define kunmap_px(ppgtt, vaddr) \ |
49d73912 | 383 | kunmap_page_dma((ppgtt)->base.i915, (vaddr)) |
d1c54acd | 384 | |
275a991c TU |
385 | #define setup_px(dev_priv, px) setup_page_dma((dev_priv), px_base(px)) |
386 | #define cleanup_px(dev_priv, px) cleanup_page_dma((dev_priv), px_base(px)) | |
e2d214ae TU |
387 | #define fill_px(dev_priv, px, v) fill_page_dma((dev_priv), px_base(px), (v)) |
388 | #define fill32_px(dev_priv, px, v) \ | |
389 | fill_page_dma_32((dev_priv), px_base(px), (v)) | |
567047be | 390 | |
e2d214ae TU |
391 | static void fill_page_dma(struct drm_i915_private *dev_priv, |
392 | struct i915_page_dma *p, const uint64_t val) | |
d1c54acd MK |
393 | { |
394 | int i; | |
395 | uint64_t * const vaddr = kmap_page_dma(p); | |
396 | ||
397 | for (i = 0; i < 512; i++) | |
398 | vaddr[i] = val; | |
399 | ||
e2d214ae | 400 | kunmap_page_dma(dev_priv, vaddr); |
d1c54acd MK |
401 | } |
402 | ||
e2d214ae TU |
403 | static void fill_page_dma_32(struct drm_i915_private *dev_priv, |
404 | struct i915_page_dma *p, const uint32_t val32) | |
73eeea53 MK |
405 | { |
406 | uint64_t v = val32; | |
407 | ||
408 | v = v << 32 | val32; | |
409 | ||
e2d214ae | 410 | fill_page_dma(dev_priv, p, v); |
73eeea53 MK |
411 | } |
412 | ||
8bcdd0f7 | 413 | static int |
275a991c | 414 | setup_scratch_page(struct drm_i915_private *dev_priv, |
bb8f9cff CW |
415 | struct i915_page_dma *scratch, |
416 | gfp_t gfp) | |
4ad2af1e | 417 | { |
275a991c | 418 | return __setup_page_dma(dev_priv, scratch, gfp | __GFP_ZERO); |
4ad2af1e MK |
419 | } |
420 | ||
275a991c | 421 | static void cleanup_scratch_page(struct drm_i915_private *dev_priv, |
8bcdd0f7 | 422 | struct i915_page_dma *scratch) |
4ad2af1e | 423 | { |
275a991c | 424 | cleanup_page_dma(dev_priv, scratch); |
4ad2af1e MK |
425 | } |
426 | ||
275a991c | 427 | static struct i915_page_table *alloc_pt(struct drm_i915_private *dev_priv) |
06fda602 | 428 | { |
ec565b3c | 429 | struct i915_page_table *pt; |
275a991c | 430 | const size_t count = INTEL_GEN(dev_priv) >= 8 ? GEN8_PTES : GEN6_PTES; |
678d96fb | 431 | int ret = -ENOMEM; |
06fda602 BW |
432 | |
433 | pt = kzalloc(sizeof(*pt), GFP_KERNEL); | |
434 | if (!pt) | |
435 | return ERR_PTR(-ENOMEM); | |
436 | ||
678d96fb BW |
437 | pt->used_ptes = kcalloc(BITS_TO_LONGS(count), sizeof(*pt->used_ptes), |
438 | GFP_KERNEL); | |
439 | ||
440 | if (!pt->used_ptes) | |
441 | goto fail_bitmap; | |
442 | ||
275a991c | 443 | ret = setup_px(dev_priv, pt); |
678d96fb | 444 | if (ret) |
44159ddb | 445 | goto fail_page_m; |
06fda602 BW |
446 | |
447 | return pt; | |
678d96fb | 448 | |
44159ddb | 449 | fail_page_m: |
678d96fb BW |
450 | kfree(pt->used_ptes); |
451 | fail_bitmap: | |
452 | kfree(pt); | |
453 | ||
454 | return ERR_PTR(ret); | |
06fda602 BW |
455 | } |
456 | ||
275a991c TU |
457 | static void free_pt(struct drm_i915_private *dev_priv, |
458 | struct i915_page_table *pt) | |
06fda602 | 459 | { |
275a991c | 460 | cleanup_px(dev_priv, pt); |
2e906bea MK |
461 | kfree(pt->used_ptes); |
462 | kfree(pt); | |
463 | } | |
464 | ||
465 | static void gen8_initialize_pt(struct i915_address_space *vm, | |
466 | struct i915_page_table *pt) | |
467 | { | |
468 | gen8_pte_t scratch_pte; | |
469 | ||
8bcdd0f7 | 470 | scratch_pte = gen8_pte_encode(vm->scratch_page.daddr, |
4fb84d99 | 471 | I915_CACHE_LLC); |
2e906bea | 472 | |
49d73912 | 473 | fill_px(vm->i915, pt, scratch_pte); |
2e906bea MK |
474 | } |
475 | ||
476 | static void gen6_initialize_pt(struct i915_address_space *vm, | |
477 | struct i915_page_table *pt) | |
478 | { | |
479 | gen6_pte_t scratch_pte; | |
480 | ||
8bcdd0f7 | 481 | WARN_ON(vm->scratch_page.daddr == 0); |
2e906bea | 482 | |
8bcdd0f7 | 483 | scratch_pte = vm->pte_encode(vm->scratch_page.daddr, |
4fb84d99 | 484 | I915_CACHE_LLC, 0); |
2e906bea | 485 | |
49d73912 | 486 | fill32_px(vm->i915, pt, scratch_pte); |
06fda602 BW |
487 | } |
488 | ||
275a991c | 489 | static struct i915_page_directory *alloc_pd(struct drm_i915_private *dev_priv) |
06fda602 | 490 | { |
ec565b3c | 491 | struct i915_page_directory *pd; |
33c8819f | 492 | int ret = -ENOMEM; |
06fda602 BW |
493 | |
494 | pd = kzalloc(sizeof(*pd), GFP_KERNEL); | |
495 | if (!pd) | |
496 | return ERR_PTR(-ENOMEM); | |
497 | ||
33c8819f MT |
498 | pd->used_pdes = kcalloc(BITS_TO_LONGS(I915_PDES), |
499 | sizeof(*pd->used_pdes), GFP_KERNEL); | |
500 | if (!pd->used_pdes) | |
a08e111a | 501 | goto fail_bitmap; |
33c8819f | 502 | |
275a991c | 503 | ret = setup_px(dev_priv, pd); |
33c8819f | 504 | if (ret) |
a08e111a | 505 | goto fail_page_m; |
e5815a2e | 506 | |
06fda602 | 507 | return pd; |
33c8819f | 508 | |
a08e111a | 509 | fail_page_m: |
33c8819f | 510 | kfree(pd->used_pdes); |
a08e111a | 511 | fail_bitmap: |
33c8819f MT |
512 | kfree(pd); |
513 | ||
514 | return ERR_PTR(ret); | |
06fda602 BW |
515 | } |
516 | ||
275a991c TU |
517 | static void free_pd(struct drm_i915_private *dev_priv, |
518 | struct i915_page_directory *pd) | |
2e906bea MK |
519 | { |
520 | if (px_page(pd)) { | |
275a991c | 521 | cleanup_px(dev_priv, pd); |
2e906bea MK |
522 | kfree(pd->used_pdes); |
523 | kfree(pd); | |
524 | } | |
525 | } | |
526 | ||
527 | static void gen8_initialize_pd(struct i915_address_space *vm, | |
528 | struct i915_page_directory *pd) | |
529 | { | |
530 | gen8_pde_t scratch_pde; | |
531 | ||
532 | scratch_pde = gen8_pde_encode(px_dma(vm->scratch_pt), I915_CACHE_LLC); | |
533 | ||
49d73912 | 534 | fill_px(vm->i915, pd, scratch_pde); |
2e906bea MK |
535 | } |
536 | ||
275a991c | 537 | static int __pdp_init(struct drm_i915_private *dev_priv, |
6ac18502 MT |
538 | struct i915_page_directory_pointer *pdp) |
539 | { | |
275a991c | 540 | size_t pdpes = I915_PDPES_PER_PDP(dev_priv); |
6ac18502 MT |
541 | |
542 | pdp->used_pdpes = kcalloc(BITS_TO_LONGS(pdpes), | |
543 | sizeof(unsigned long), | |
544 | GFP_KERNEL); | |
545 | if (!pdp->used_pdpes) | |
546 | return -ENOMEM; | |
547 | ||
548 | pdp->page_directory = kcalloc(pdpes, sizeof(*pdp->page_directory), | |
549 | GFP_KERNEL); | |
550 | if (!pdp->page_directory) { | |
551 | kfree(pdp->used_pdpes); | |
552 | /* the PDP might be the statically allocated top level. Keep it | |
553 | * as clean as possible */ | |
554 | pdp->used_pdpes = NULL; | |
555 | return -ENOMEM; | |
556 | } | |
557 | ||
558 | return 0; | |
559 | } | |
560 | ||
561 | static void __pdp_fini(struct i915_page_directory_pointer *pdp) | |
562 | { | |
563 | kfree(pdp->used_pdpes); | |
564 | kfree(pdp->page_directory); | |
565 | pdp->page_directory = NULL; | |
566 | } | |
567 | ||
762d9936 | 568 | static struct |
275a991c | 569 | i915_page_directory_pointer *alloc_pdp(struct drm_i915_private *dev_priv) |
762d9936 MT |
570 | { |
571 | struct i915_page_directory_pointer *pdp; | |
572 | int ret = -ENOMEM; | |
573 | ||
275a991c | 574 | WARN_ON(!USES_FULL_48BIT_PPGTT(dev_priv)); |
762d9936 MT |
575 | |
576 | pdp = kzalloc(sizeof(*pdp), GFP_KERNEL); | |
577 | if (!pdp) | |
578 | return ERR_PTR(-ENOMEM); | |
579 | ||
275a991c | 580 | ret = __pdp_init(dev_priv, pdp); |
762d9936 MT |
581 | if (ret) |
582 | goto fail_bitmap; | |
583 | ||
275a991c | 584 | ret = setup_px(dev_priv, pdp); |
762d9936 MT |
585 | if (ret) |
586 | goto fail_page_m; | |
587 | ||
588 | return pdp; | |
589 | ||
590 | fail_page_m: | |
591 | __pdp_fini(pdp); | |
592 | fail_bitmap: | |
593 | kfree(pdp); | |
594 | ||
595 | return ERR_PTR(ret); | |
596 | } | |
597 | ||
275a991c | 598 | static void free_pdp(struct drm_i915_private *dev_priv, |
6ac18502 MT |
599 | struct i915_page_directory_pointer *pdp) |
600 | { | |
601 | __pdp_fini(pdp); | |
275a991c TU |
602 | if (USES_FULL_48BIT_PPGTT(dev_priv)) { |
603 | cleanup_px(dev_priv, pdp); | |
762d9936 MT |
604 | kfree(pdp); |
605 | } | |
606 | } | |
607 | ||
69ab76fd MT |
608 | static void gen8_initialize_pdp(struct i915_address_space *vm, |
609 | struct i915_page_directory_pointer *pdp) | |
610 | { | |
611 | gen8_ppgtt_pdpe_t scratch_pdpe; | |
612 | ||
613 | scratch_pdpe = gen8_pdpe_encode(px_dma(vm->scratch_pd), I915_CACHE_LLC); | |
614 | ||
49d73912 | 615 | fill_px(vm->i915, pdp, scratch_pdpe); |
69ab76fd MT |
616 | } |
617 | ||
618 | static void gen8_initialize_pml4(struct i915_address_space *vm, | |
619 | struct i915_pml4 *pml4) | |
620 | { | |
621 | gen8_ppgtt_pml4e_t scratch_pml4e; | |
622 | ||
623 | scratch_pml4e = gen8_pml4e_encode(px_dma(vm->scratch_pdp), | |
624 | I915_CACHE_LLC); | |
625 | ||
49d73912 | 626 | fill_px(vm->i915, pml4, scratch_pml4e); |
69ab76fd MT |
627 | } |
628 | ||
762d9936 MT |
629 | static void |
630 | gen8_setup_page_directory(struct i915_hw_ppgtt *ppgtt, | |
631 | struct i915_page_directory_pointer *pdp, | |
632 | struct i915_page_directory *pd, | |
633 | int index) | |
634 | { | |
635 | gen8_ppgtt_pdpe_t *page_directorypo; | |
636 | ||
275a991c | 637 | if (!USES_FULL_48BIT_PPGTT(to_i915(ppgtt->base.dev))) |
762d9936 MT |
638 | return; |
639 | ||
640 | page_directorypo = kmap_px(pdp); | |
641 | page_directorypo[index] = gen8_pdpe_encode(px_dma(pd), I915_CACHE_LLC); | |
642 | kunmap_px(ppgtt, page_directorypo); | |
643 | } | |
644 | ||
645 | static void | |
646 | gen8_setup_page_directory_pointer(struct i915_hw_ppgtt *ppgtt, | |
647 | struct i915_pml4 *pml4, | |
648 | struct i915_page_directory_pointer *pdp, | |
649 | int index) | |
650 | { | |
651 | gen8_ppgtt_pml4e_t *pagemap = kmap_px(pml4); | |
652 | ||
275a991c | 653 | WARN_ON(!USES_FULL_48BIT_PPGTT(to_i915(ppgtt->base.dev))); |
762d9936 MT |
654 | pagemap[index] = gen8_pml4e_encode(px_dma(pdp), I915_CACHE_LLC); |
655 | kunmap_px(ppgtt, pagemap); | |
6ac18502 MT |
656 | } |
657 | ||
94e409c1 | 658 | /* Broadwell Page Directory Pointer Descriptors */ |
e85b26dc | 659 | static int gen8_write_pdp(struct drm_i915_gem_request *req, |
7cb6d7ac MT |
660 | unsigned entry, |
661 | dma_addr_t addr) | |
94e409c1 | 662 | { |
7e37f889 | 663 | struct intel_ring *ring = req->ring; |
4a570db5 | 664 | struct intel_engine_cs *engine = req->engine; |
94e409c1 BW |
665 | int ret; |
666 | ||
667 | BUG_ON(entry >= 4); | |
668 | ||
5fb9de1a | 669 | ret = intel_ring_begin(req, 6); |
94e409c1 BW |
670 | if (ret) |
671 | return ret; | |
672 | ||
b5321f30 CW |
673 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); |
674 | intel_ring_emit_reg(ring, GEN8_RING_PDP_UDW(engine, entry)); | |
675 | intel_ring_emit(ring, upper_32_bits(addr)); | |
676 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
677 | intel_ring_emit_reg(ring, GEN8_RING_PDP_LDW(engine, entry)); | |
678 | intel_ring_emit(ring, lower_32_bits(addr)); | |
679 | intel_ring_advance(ring); | |
94e409c1 BW |
680 | |
681 | return 0; | |
682 | } | |
683 | ||
2dba3239 MT |
684 | static int gen8_legacy_mm_switch(struct i915_hw_ppgtt *ppgtt, |
685 | struct drm_i915_gem_request *req) | |
94e409c1 | 686 | { |
eeb9488e | 687 | int i, ret; |
94e409c1 | 688 | |
7cb6d7ac | 689 | for (i = GEN8_LEGACY_PDPES - 1; i >= 0; i--) { |
d852c7bf MK |
690 | const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i); |
691 | ||
e85b26dc | 692 | ret = gen8_write_pdp(req, i, pd_daddr); |
eeb9488e BW |
693 | if (ret) |
694 | return ret; | |
94e409c1 | 695 | } |
d595bd4b | 696 | |
eeb9488e | 697 | return 0; |
94e409c1 BW |
698 | } |
699 | ||
2dba3239 MT |
700 | static int gen8_48b_mm_switch(struct i915_hw_ppgtt *ppgtt, |
701 | struct drm_i915_gem_request *req) | |
702 | { | |
703 | return gen8_write_pdp(req, 0, px_dma(&ppgtt->pml4)); | |
704 | } | |
705 | ||
fce93755 MK |
706 | /* PDE TLBs are a pain to invalidate on GEN8+. When we modify |
707 | * the page table structures, we mark them dirty so that | |
708 | * context switching/execlist queuing code takes extra steps | |
709 | * to ensure that tlbs are flushed. | |
710 | */ | |
711 | static void mark_tlbs_dirty(struct i915_hw_ppgtt *ppgtt) | |
712 | { | |
49d73912 | 713 | ppgtt->pd_dirty_rings = INTEL_INFO(ppgtt->base.i915)->ring_mask; |
fce93755 MK |
714 | } |
715 | ||
2ce5179f MW |
716 | /* Removes entries from a single page table, releasing it if it's empty. |
717 | * Caller can use the return value to update higher-level entries. | |
718 | */ | |
719 | static bool gen8_ppgtt_clear_pt(struct i915_address_space *vm, | |
d209b9c3 MW |
720 | struct i915_page_table *pt, |
721 | uint64_t start, | |
722 | uint64_t length) | |
459108b8 | 723 | { |
e5716f55 | 724 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
d209b9c3 | 725 | unsigned int num_entries = gen8_pte_count(start, length); |
37c63934 MK |
726 | unsigned int pte = gen8_pte_index(start); |
727 | unsigned int pte_end = pte + num_entries; | |
f9b5b782 | 728 | gen8_pte_t *pt_vaddr; |
d209b9c3 MW |
729 | gen8_pte_t scratch_pte = gen8_pte_encode(vm->scratch_page.daddr, |
730 | I915_CACHE_LLC); | |
459108b8 | 731 | |
d209b9c3 | 732 | if (WARN_ON(!px_page(pt))) |
2ce5179f | 733 | return false; |
459108b8 | 734 | |
37c63934 MK |
735 | GEM_BUG_ON(pte_end > GEN8_PTES); |
736 | ||
737 | bitmap_clear(pt->used_ptes, pte, num_entries); | |
06fda602 | 738 | |
a18dbba8 | 739 | if (bitmap_empty(pt->used_ptes, GEN8_PTES)) |
2ce5179f | 740 | return true; |
2ce5179f | 741 | |
d209b9c3 MW |
742 | pt_vaddr = kmap_px(pt); |
743 | ||
37c63934 MK |
744 | while (pte < pte_end) |
745 | pt_vaddr[pte++] = scratch_pte; | |
06fda602 | 746 | |
d209b9c3 | 747 | kunmap_px(ppgtt, pt_vaddr); |
2ce5179f MW |
748 | |
749 | return false; | |
d209b9c3 | 750 | } |
06fda602 | 751 | |
2ce5179f MW |
752 | /* Removes entries from a single page dir, releasing it if it's empty. |
753 | * Caller can use the return value to update higher-level entries | |
754 | */ | |
755 | static bool gen8_ppgtt_clear_pd(struct i915_address_space *vm, | |
d209b9c3 MW |
756 | struct i915_page_directory *pd, |
757 | uint64_t start, | |
758 | uint64_t length) | |
759 | { | |
2ce5179f | 760 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
d209b9c3 MW |
761 | struct i915_page_table *pt; |
762 | uint64_t pde; | |
2ce5179f MW |
763 | gen8_pde_t *pde_vaddr; |
764 | gen8_pde_t scratch_pde = gen8_pde_encode(px_dma(vm->scratch_pt), | |
765 | I915_CACHE_LLC); | |
d209b9c3 MW |
766 | |
767 | gen8_for_each_pde(pt, pd, start, length, pde) { | |
06fda602 | 768 | if (WARN_ON(!pd->page_table[pde])) |
00245266 | 769 | break; |
06fda602 | 770 | |
2ce5179f MW |
771 | if (gen8_ppgtt_clear_pt(vm, pt, start, length)) { |
772 | __clear_bit(pde, pd->used_pdes); | |
773 | pde_vaddr = kmap_px(pd); | |
774 | pde_vaddr[pde] = scratch_pde; | |
775 | kunmap_px(ppgtt, pde_vaddr); | |
49d73912 | 776 | free_pt(vm->i915, pt); |
2ce5179f MW |
777 | } |
778 | } | |
779 | ||
a18dbba8 | 780 | if (bitmap_empty(pd->used_pdes, I915_PDES)) |
2ce5179f | 781 | return true; |
2ce5179f MW |
782 | |
783 | return false; | |
d209b9c3 | 784 | } |
06fda602 | 785 | |
2ce5179f MW |
786 | /* Removes entries from a single page dir pointer, releasing it if it's empty. |
787 | * Caller can use the return value to update higher-level entries | |
788 | */ | |
789 | static bool gen8_ppgtt_clear_pdp(struct i915_address_space *vm, | |
d209b9c3 MW |
790 | struct i915_page_directory_pointer *pdp, |
791 | uint64_t start, | |
792 | uint64_t length) | |
793 | { | |
2ce5179f | 794 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
d209b9c3 MW |
795 | struct i915_page_directory *pd; |
796 | uint64_t pdpe; | |
2ce5179f MW |
797 | gen8_ppgtt_pdpe_t *pdpe_vaddr; |
798 | gen8_ppgtt_pdpe_t scratch_pdpe = | |
799 | gen8_pdpe_encode(px_dma(vm->scratch_pd), I915_CACHE_LLC); | |
06fda602 | 800 | |
d209b9c3 MW |
801 | gen8_for_each_pdpe(pd, pdp, start, length, pdpe) { |
802 | if (WARN_ON(!pdp->page_directory[pdpe])) | |
803 | break; | |
459108b8 | 804 | |
2ce5179f MW |
805 | if (gen8_ppgtt_clear_pd(vm, pd, start, length)) { |
806 | __clear_bit(pdpe, pdp->used_pdpes); | |
275a991c | 807 | if (USES_FULL_48BIT_PPGTT(dev_priv)) { |
2ce5179f MW |
808 | pdpe_vaddr = kmap_px(pdp); |
809 | pdpe_vaddr[pdpe] = scratch_pdpe; | |
810 | kunmap_px(ppgtt, pdpe_vaddr); | |
811 | } | |
49d73912 | 812 | free_pd(vm->i915, pd); |
2ce5179f MW |
813 | } |
814 | } | |
815 | ||
fce93755 MK |
816 | mark_tlbs_dirty(ppgtt); |
817 | ||
a18dbba8 | 818 | if (bitmap_empty(pdp->used_pdpes, I915_PDPES_PER_PDP(dev_priv))) |
2ce5179f | 819 | return true; |
2ce5179f MW |
820 | |
821 | return false; | |
d209b9c3 | 822 | } |
459108b8 | 823 | |
2ce5179f MW |
824 | /* Removes entries from a single pml4. |
825 | * This is the top-level structure in 4-level page tables used on gen8+. | |
826 | * Empty entries are always scratch pml4e. | |
827 | */ | |
d209b9c3 MW |
828 | static void gen8_ppgtt_clear_pml4(struct i915_address_space *vm, |
829 | struct i915_pml4 *pml4, | |
830 | uint64_t start, | |
831 | uint64_t length) | |
832 | { | |
2ce5179f | 833 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
d209b9c3 MW |
834 | struct i915_page_directory_pointer *pdp; |
835 | uint64_t pml4e; | |
2ce5179f MW |
836 | gen8_ppgtt_pml4e_t *pml4e_vaddr; |
837 | gen8_ppgtt_pml4e_t scratch_pml4e = | |
838 | gen8_pml4e_encode(px_dma(vm->scratch_pdp), I915_CACHE_LLC); | |
839 | ||
49d73912 | 840 | GEM_BUG_ON(!USES_FULL_48BIT_PPGTT(vm->i915)); |
459108b8 | 841 | |
d209b9c3 MW |
842 | gen8_for_each_pml4e(pdp, pml4, start, length, pml4e) { |
843 | if (WARN_ON(!pml4->pdps[pml4e])) | |
844 | break; | |
459108b8 | 845 | |
2ce5179f MW |
846 | if (gen8_ppgtt_clear_pdp(vm, pdp, start, length)) { |
847 | __clear_bit(pml4e, pml4->used_pml4es); | |
848 | pml4e_vaddr = kmap_px(pml4); | |
849 | pml4e_vaddr[pml4e] = scratch_pml4e; | |
850 | kunmap_px(ppgtt, pml4e_vaddr); | |
49d73912 | 851 | free_pdp(vm->i915, pdp); |
2ce5179f | 852 | } |
459108b8 BW |
853 | } |
854 | } | |
855 | ||
f9b5b782 | 856 | static void gen8_ppgtt_clear_range(struct i915_address_space *vm, |
4fb84d99 | 857 | uint64_t start, uint64_t length) |
9df15b49 | 858 | { |
e5716f55 | 859 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
f9b5b782 | 860 | |
c6385c94 | 861 | if (USES_FULL_48BIT_PPGTT(vm->i915)) |
d209b9c3 MW |
862 | gen8_ppgtt_clear_pml4(vm, &ppgtt->pml4, start, length); |
863 | else | |
864 | gen8_ppgtt_clear_pdp(vm, &ppgtt->pdp, start, length); | |
f9b5b782 MT |
865 | } |
866 | ||
867 | static void | |
868 | gen8_ppgtt_insert_pte_entries(struct i915_address_space *vm, | |
869 | struct i915_page_directory_pointer *pdp, | |
3387d433 | 870 | struct sg_page_iter *sg_iter, |
f9b5b782 MT |
871 | uint64_t start, |
872 | enum i915_cache_level cache_level) | |
873 | { | |
e5716f55 | 874 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
07749ef3 | 875 | gen8_pte_t *pt_vaddr; |
de5ba8eb MT |
876 | unsigned pdpe = gen8_pdpe_index(start); |
877 | unsigned pde = gen8_pde_index(start); | |
878 | unsigned pte = gen8_pte_index(start); | |
9df15b49 | 879 | |
6f1cc993 | 880 | pt_vaddr = NULL; |
7ad47cf2 | 881 | |
3387d433 | 882 | while (__sg_page_iter_next(sg_iter)) { |
d7b3de91 | 883 | if (pt_vaddr == NULL) { |
d4ec9da0 | 884 | struct i915_page_directory *pd = pdp->page_directory[pdpe]; |
ec565b3c | 885 | struct i915_page_table *pt = pd->page_table[pde]; |
d1c54acd | 886 | pt_vaddr = kmap_px(pt); |
d7b3de91 | 887 | } |
9df15b49 | 888 | |
7ad47cf2 | 889 | pt_vaddr[pte] = |
3387d433 | 890 | gen8_pte_encode(sg_page_iter_dma_address(sg_iter), |
4fb84d99 | 891 | cache_level); |
07749ef3 | 892 | if (++pte == GEN8_PTES) { |
d1c54acd | 893 | kunmap_px(ppgtt, pt_vaddr); |
6f1cc993 | 894 | pt_vaddr = NULL; |
07749ef3 | 895 | if (++pde == I915_PDES) { |
c6385c94 | 896 | if (++pdpe == I915_PDPES_PER_PDP(vm->i915)) |
de5ba8eb | 897 | break; |
7ad47cf2 BW |
898 | pde = 0; |
899 | } | |
900 | pte = 0; | |
9df15b49 BW |
901 | } |
902 | } | |
d1c54acd MK |
903 | |
904 | if (pt_vaddr) | |
905 | kunmap_px(ppgtt, pt_vaddr); | |
9df15b49 BW |
906 | } |
907 | ||
f9b5b782 MT |
908 | static void gen8_ppgtt_insert_entries(struct i915_address_space *vm, |
909 | struct sg_table *pages, | |
910 | uint64_t start, | |
911 | enum i915_cache_level cache_level, | |
912 | u32 unused) | |
913 | { | |
e5716f55 | 914 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
3387d433 | 915 | struct sg_page_iter sg_iter; |
f9b5b782 | 916 | |
3387d433 | 917 | __sg_page_iter_start(&sg_iter, pages->sgl, sg_nents(pages->sgl), 0); |
de5ba8eb | 918 | |
c6385c94 | 919 | if (!USES_FULL_48BIT_PPGTT(vm->i915)) { |
de5ba8eb MT |
920 | gen8_ppgtt_insert_pte_entries(vm, &ppgtt->pdp, &sg_iter, start, |
921 | cache_level); | |
922 | } else { | |
923 | struct i915_page_directory_pointer *pdp; | |
e8ebd8e2 | 924 | uint64_t pml4e; |
de5ba8eb MT |
925 | uint64_t length = (uint64_t)pages->orig_nents << PAGE_SHIFT; |
926 | ||
e8ebd8e2 | 927 | gen8_for_each_pml4e(pdp, &ppgtt->pml4, start, length, pml4e) { |
de5ba8eb MT |
928 | gen8_ppgtt_insert_pte_entries(vm, pdp, &sg_iter, |
929 | start, cache_level); | |
930 | } | |
931 | } | |
f9b5b782 MT |
932 | } |
933 | ||
275a991c | 934 | static void gen8_free_page_tables(struct drm_i915_private *dev_priv, |
f37c0505 | 935 | struct i915_page_directory *pd) |
7ad47cf2 BW |
936 | { |
937 | int i; | |
938 | ||
567047be | 939 | if (!px_page(pd)) |
7ad47cf2 BW |
940 | return; |
941 | ||
33c8819f | 942 | for_each_set_bit(i, pd->used_pdes, I915_PDES) { |
06fda602 BW |
943 | if (WARN_ON(!pd->page_table[i])) |
944 | continue; | |
7ad47cf2 | 945 | |
275a991c | 946 | free_pt(dev_priv, pd->page_table[i]); |
06fda602 BW |
947 | pd->page_table[i] = NULL; |
948 | } | |
d7b3de91 BW |
949 | } |
950 | ||
8776f02b MK |
951 | static int gen8_init_scratch(struct i915_address_space *vm) |
952 | { | |
49d73912 | 953 | struct drm_i915_private *dev_priv = vm->i915; |
64c050db | 954 | int ret; |
8776f02b | 955 | |
275a991c | 956 | ret = setup_scratch_page(dev_priv, &vm->scratch_page, I915_GFP_DMA); |
8bcdd0f7 CW |
957 | if (ret) |
958 | return ret; | |
8776f02b | 959 | |
275a991c | 960 | vm->scratch_pt = alloc_pt(dev_priv); |
8776f02b | 961 | if (IS_ERR(vm->scratch_pt)) { |
64c050db MA |
962 | ret = PTR_ERR(vm->scratch_pt); |
963 | goto free_scratch_page; | |
8776f02b MK |
964 | } |
965 | ||
275a991c | 966 | vm->scratch_pd = alloc_pd(dev_priv); |
8776f02b | 967 | if (IS_ERR(vm->scratch_pd)) { |
64c050db MA |
968 | ret = PTR_ERR(vm->scratch_pd); |
969 | goto free_pt; | |
8776f02b MK |
970 | } |
971 | ||
275a991c TU |
972 | if (USES_FULL_48BIT_PPGTT(dev_priv)) { |
973 | vm->scratch_pdp = alloc_pdp(dev_priv); | |
69ab76fd | 974 | if (IS_ERR(vm->scratch_pdp)) { |
64c050db MA |
975 | ret = PTR_ERR(vm->scratch_pdp); |
976 | goto free_pd; | |
69ab76fd MT |
977 | } |
978 | } | |
979 | ||
8776f02b MK |
980 | gen8_initialize_pt(vm, vm->scratch_pt); |
981 | gen8_initialize_pd(vm, vm->scratch_pd); | |
275a991c | 982 | if (USES_FULL_48BIT_PPGTT(dev_priv)) |
69ab76fd | 983 | gen8_initialize_pdp(vm, vm->scratch_pdp); |
8776f02b MK |
984 | |
985 | return 0; | |
64c050db MA |
986 | |
987 | free_pd: | |
275a991c | 988 | free_pd(dev_priv, vm->scratch_pd); |
64c050db | 989 | free_pt: |
275a991c | 990 | free_pt(dev_priv, vm->scratch_pt); |
64c050db | 991 | free_scratch_page: |
275a991c | 992 | cleanup_scratch_page(dev_priv, &vm->scratch_page); |
64c050db MA |
993 | |
994 | return ret; | |
8776f02b MK |
995 | } |
996 | ||
650da34c ZL |
997 | static int gen8_ppgtt_notify_vgt(struct i915_hw_ppgtt *ppgtt, bool create) |
998 | { | |
999 | enum vgt_g2v_type msg; | |
49d73912 | 1000 | struct drm_i915_private *dev_priv = ppgtt->base.i915; |
650da34c ZL |
1001 | int i; |
1002 | ||
df28564d | 1003 | if (USES_FULL_48BIT_PPGTT(dev_priv)) { |
650da34c ZL |
1004 | u64 daddr = px_dma(&ppgtt->pml4); |
1005 | ||
ab75bb5d VS |
1006 | I915_WRITE(vgtif_reg(pdp[0].lo), lower_32_bits(daddr)); |
1007 | I915_WRITE(vgtif_reg(pdp[0].hi), upper_32_bits(daddr)); | |
650da34c ZL |
1008 | |
1009 | msg = (create ? VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE : | |
1010 | VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY); | |
1011 | } else { | |
1012 | for (i = 0; i < GEN8_LEGACY_PDPES; i++) { | |
1013 | u64 daddr = i915_page_dir_dma_addr(ppgtt, i); | |
1014 | ||
ab75bb5d VS |
1015 | I915_WRITE(vgtif_reg(pdp[i].lo), lower_32_bits(daddr)); |
1016 | I915_WRITE(vgtif_reg(pdp[i].hi), upper_32_bits(daddr)); | |
650da34c ZL |
1017 | } |
1018 | ||
1019 | msg = (create ? VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE : | |
1020 | VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY); | |
1021 | } | |
1022 | ||
1023 | I915_WRITE(vgtif_reg(g2v_notify), msg); | |
1024 | ||
1025 | return 0; | |
1026 | } | |
1027 | ||
8776f02b MK |
1028 | static void gen8_free_scratch(struct i915_address_space *vm) |
1029 | { | |
49d73912 | 1030 | struct drm_i915_private *dev_priv = vm->i915; |
8776f02b | 1031 | |
275a991c TU |
1032 | if (USES_FULL_48BIT_PPGTT(dev_priv)) |
1033 | free_pdp(dev_priv, vm->scratch_pdp); | |
1034 | free_pd(dev_priv, vm->scratch_pd); | |
1035 | free_pt(dev_priv, vm->scratch_pt); | |
1036 | cleanup_scratch_page(dev_priv, &vm->scratch_page); | |
8776f02b MK |
1037 | } |
1038 | ||
275a991c | 1039 | static void gen8_ppgtt_cleanup_3lvl(struct drm_i915_private *dev_priv, |
762d9936 | 1040 | struct i915_page_directory_pointer *pdp) |
b45a6715 BW |
1041 | { |
1042 | int i; | |
1043 | ||
275a991c | 1044 | for_each_set_bit(i, pdp->used_pdpes, I915_PDPES_PER_PDP(dev_priv)) { |
d4ec9da0 | 1045 | if (WARN_ON(!pdp->page_directory[i])) |
06fda602 BW |
1046 | continue; |
1047 | ||
275a991c TU |
1048 | gen8_free_page_tables(dev_priv, pdp->page_directory[i]); |
1049 | free_pd(dev_priv, pdp->page_directory[i]); | |
7ad47cf2 | 1050 | } |
69876bed | 1051 | |
275a991c | 1052 | free_pdp(dev_priv, pdp); |
762d9936 MT |
1053 | } |
1054 | ||
1055 | static void gen8_ppgtt_cleanup_4lvl(struct i915_hw_ppgtt *ppgtt) | |
1056 | { | |
49d73912 | 1057 | struct drm_i915_private *dev_priv = ppgtt->base.i915; |
762d9936 MT |
1058 | int i; |
1059 | ||
1060 | for_each_set_bit(i, ppgtt->pml4.used_pml4es, GEN8_PML4ES_PER_PML4) { | |
1061 | if (WARN_ON(!ppgtt->pml4.pdps[i])) | |
1062 | continue; | |
1063 | ||
275a991c | 1064 | gen8_ppgtt_cleanup_3lvl(dev_priv, ppgtt->pml4.pdps[i]); |
762d9936 MT |
1065 | } |
1066 | ||
275a991c | 1067 | cleanup_px(dev_priv, &ppgtt->pml4); |
762d9936 MT |
1068 | } |
1069 | ||
1070 | static void gen8_ppgtt_cleanup(struct i915_address_space *vm) | |
1071 | { | |
49d73912 | 1072 | struct drm_i915_private *dev_priv = vm->i915; |
e5716f55 | 1073 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
762d9936 | 1074 | |
275a991c | 1075 | if (intel_vgpu_active(dev_priv)) |
650da34c ZL |
1076 | gen8_ppgtt_notify_vgt(ppgtt, false); |
1077 | ||
275a991c TU |
1078 | if (!USES_FULL_48BIT_PPGTT(dev_priv)) |
1079 | gen8_ppgtt_cleanup_3lvl(dev_priv, &ppgtt->pdp); | |
762d9936 MT |
1080 | else |
1081 | gen8_ppgtt_cleanup_4lvl(ppgtt); | |
d4ec9da0 | 1082 | |
8776f02b | 1083 | gen8_free_scratch(vm); |
b45a6715 BW |
1084 | } |
1085 | ||
d7b2633d MT |
1086 | /** |
1087 | * gen8_ppgtt_alloc_pagetabs() - Allocate page tables for VA range. | |
d4ec9da0 MT |
1088 | * @vm: Master vm structure. |
1089 | * @pd: Page directory for this address range. | |
d7b2633d | 1090 | * @start: Starting virtual address to begin allocations. |
d4ec9da0 | 1091 | * @length: Size of the allocations. |
d7b2633d MT |
1092 | * @new_pts: Bitmap set by function with new allocations. Likely used by the |
1093 | * caller to free on error. | |
1094 | * | |
1095 | * Allocate the required number of page tables. Extremely similar to | |
1096 | * gen8_ppgtt_alloc_page_directories(). The main difference is here we are limited by | |
1097 | * the page directory boundary (instead of the page directory pointer). That | |
1098 | * boundary is 1GB virtual. Therefore, unlike gen8_ppgtt_alloc_page_directories(), it is | |
1099 | * possible, and likely that the caller will need to use multiple calls of this | |
1100 | * function to achieve the appropriate allocation. | |
1101 | * | |
1102 | * Return: 0 if success; negative error code otherwise. | |
1103 | */ | |
d4ec9da0 | 1104 | static int gen8_ppgtt_alloc_pagetabs(struct i915_address_space *vm, |
e5815a2e | 1105 | struct i915_page_directory *pd, |
5441f0cb | 1106 | uint64_t start, |
d7b2633d MT |
1107 | uint64_t length, |
1108 | unsigned long *new_pts) | |
bf2b4ed2 | 1109 | { |
49d73912 | 1110 | struct drm_i915_private *dev_priv = vm->i915; |
d7b2633d | 1111 | struct i915_page_table *pt; |
5441f0cb | 1112 | uint32_t pde; |
bf2b4ed2 | 1113 | |
e8ebd8e2 | 1114 | gen8_for_each_pde(pt, pd, start, length, pde) { |
d7b2633d | 1115 | /* Don't reallocate page tables */ |
6ac18502 | 1116 | if (test_bit(pde, pd->used_pdes)) { |
d7b2633d | 1117 | /* Scratch is never allocated this way */ |
d4ec9da0 | 1118 | WARN_ON(pt == vm->scratch_pt); |
d7b2633d MT |
1119 | continue; |
1120 | } | |
1121 | ||
275a991c | 1122 | pt = alloc_pt(dev_priv); |
d7b2633d | 1123 | if (IS_ERR(pt)) |
5441f0cb MT |
1124 | goto unwind_out; |
1125 | ||
d4ec9da0 | 1126 | gen8_initialize_pt(vm, pt); |
d7b2633d | 1127 | pd->page_table[pde] = pt; |
966082c9 | 1128 | __set_bit(pde, new_pts); |
4c06ec8d | 1129 | trace_i915_page_table_entry_alloc(vm, pde, start, GEN8_PDE_SHIFT); |
7ad47cf2 BW |
1130 | } |
1131 | ||
bf2b4ed2 | 1132 | return 0; |
7ad47cf2 BW |
1133 | |
1134 | unwind_out: | |
d7b2633d | 1135 | for_each_set_bit(pde, new_pts, I915_PDES) |
275a991c | 1136 | free_pt(dev_priv, pd->page_table[pde]); |
7ad47cf2 | 1137 | |
d7b3de91 | 1138 | return -ENOMEM; |
bf2b4ed2 BW |
1139 | } |
1140 | ||
d7b2633d MT |
1141 | /** |
1142 | * gen8_ppgtt_alloc_page_directories() - Allocate page directories for VA range. | |
d4ec9da0 | 1143 | * @vm: Master vm structure. |
d7b2633d MT |
1144 | * @pdp: Page directory pointer for this address range. |
1145 | * @start: Starting virtual address to begin allocations. | |
d4ec9da0 MT |
1146 | * @length: Size of the allocations. |
1147 | * @new_pds: Bitmap set by function with new allocations. Likely used by the | |
d7b2633d MT |
1148 | * caller to free on error. |
1149 | * | |
1150 | * Allocate the required number of page directories starting at the pde index of | |
1151 | * @start, and ending at the pde index @start + @length. This function will skip | |
1152 | * over already allocated page directories within the range, and only allocate | |
1153 | * new ones, setting the appropriate pointer within the pdp as well as the | |
1154 | * correct position in the bitmap @new_pds. | |
1155 | * | |
1156 | * The function will only allocate the pages within the range for a give page | |
1157 | * directory pointer. In other words, if @start + @length straddles a virtually | |
1158 | * addressed PDP boundary (512GB for 4k pages), there will be more allocations | |
1159 | * required by the caller, This is not currently possible, and the BUG in the | |
1160 | * code will prevent it. | |
1161 | * | |
1162 | * Return: 0 if success; negative error code otherwise. | |
1163 | */ | |
d4ec9da0 MT |
1164 | static int |
1165 | gen8_ppgtt_alloc_page_directories(struct i915_address_space *vm, | |
1166 | struct i915_page_directory_pointer *pdp, | |
1167 | uint64_t start, | |
1168 | uint64_t length, | |
1169 | unsigned long *new_pds) | |
bf2b4ed2 | 1170 | { |
49d73912 | 1171 | struct drm_i915_private *dev_priv = vm->i915; |
d7b2633d | 1172 | struct i915_page_directory *pd; |
69876bed | 1173 | uint32_t pdpe; |
275a991c | 1174 | uint32_t pdpes = I915_PDPES_PER_PDP(dev_priv); |
69876bed | 1175 | |
6ac18502 | 1176 | WARN_ON(!bitmap_empty(new_pds, pdpes)); |
d7b2633d | 1177 | |
e8ebd8e2 | 1178 | gen8_for_each_pdpe(pd, pdp, start, length, pdpe) { |
6ac18502 | 1179 | if (test_bit(pdpe, pdp->used_pdpes)) |
d7b2633d | 1180 | continue; |
33c8819f | 1181 | |
275a991c | 1182 | pd = alloc_pd(dev_priv); |
d7b2633d | 1183 | if (IS_ERR(pd)) |
d7b3de91 | 1184 | goto unwind_out; |
69876bed | 1185 | |
d4ec9da0 | 1186 | gen8_initialize_pd(vm, pd); |
d7b2633d | 1187 | pdp->page_directory[pdpe] = pd; |
966082c9 | 1188 | __set_bit(pdpe, new_pds); |
4c06ec8d | 1189 | trace_i915_page_directory_entry_alloc(vm, pdpe, start, GEN8_PDPE_SHIFT); |
d7b3de91 BW |
1190 | } |
1191 | ||
bf2b4ed2 | 1192 | return 0; |
d7b3de91 BW |
1193 | |
1194 | unwind_out: | |
6ac18502 | 1195 | for_each_set_bit(pdpe, new_pds, pdpes) |
275a991c | 1196 | free_pd(dev_priv, pdp->page_directory[pdpe]); |
d7b3de91 BW |
1197 | |
1198 | return -ENOMEM; | |
bf2b4ed2 BW |
1199 | } |
1200 | ||
762d9936 MT |
1201 | /** |
1202 | * gen8_ppgtt_alloc_page_dirpointers() - Allocate pdps for VA range. | |
1203 | * @vm: Master vm structure. | |
1204 | * @pml4: Page map level 4 for this address range. | |
1205 | * @start: Starting virtual address to begin allocations. | |
1206 | * @length: Size of the allocations. | |
1207 | * @new_pdps: Bitmap set by function with new allocations. Likely used by the | |
1208 | * caller to free on error. | |
1209 | * | |
1210 | * Allocate the required number of page directory pointers. Extremely similar to | |
1211 | * gen8_ppgtt_alloc_page_directories() and gen8_ppgtt_alloc_pagetabs(). | |
1212 | * The main difference is here we are limited by the pml4 boundary (instead of | |
1213 | * the page directory pointer). | |
1214 | * | |
1215 | * Return: 0 if success; negative error code otherwise. | |
1216 | */ | |
1217 | static int | |
1218 | gen8_ppgtt_alloc_page_dirpointers(struct i915_address_space *vm, | |
1219 | struct i915_pml4 *pml4, | |
1220 | uint64_t start, | |
1221 | uint64_t length, | |
1222 | unsigned long *new_pdps) | |
1223 | { | |
49d73912 | 1224 | struct drm_i915_private *dev_priv = vm->i915; |
762d9936 | 1225 | struct i915_page_directory_pointer *pdp; |
762d9936 MT |
1226 | uint32_t pml4e; |
1227 | ||
1228 | WARN_ON(!bitmap_empty(new_pdps, GEN8_PML4ES_PER_PML4)); | |
1229 | ||
e8ebd8e2 | 1230 | gen8_for_each_pml4e(pdp, pml4, start, length, pml4e) { |
762d9936 | 1231 | if (!test_bit(pml4e, pml4->used_pml4es)) { |
275a991c | 1232 | pdp = alloc_pdp(dev_priv); |
762d9936 MT |
1233 | if (IS_ERR(pdp)) |
1234 | goto unwind_out; | |
1235 | ||
69ab76fd | 1236 | gen8_initialize_pdp(vm, pdp); |
762d9936 MT |
1237 | pml4->pdps[pml4e] = pdp; |
1238 | __set_bit(pml4e, new_pdps); | |
1239 | trace_i915_page_directory_pointer_entry_alloc(vm, | |
1240 | pml4e, | |
1241 | start, | |
1242 | GEN8_PML4E_SHIFT); | |
1243 | } | |
1244 | } | |
1245 | ||
1246 | return 0; | |
1247 | ||
1248 | unwind_out: | |
1249 | for_each_set_bit(pml4e, new_pdps, GEN8_PML4ES_PER_PML4) | |
275a991c | 1250 | free_pdp(dev_priv, pml4->pdps[pml4e]); |
762d9936 MT |
1251 | |
1252 | return -ENOMEM; | |
1253 | } | |
1254 | ||
d7b2633d | 1255 | static void |
3a41a05d | 1256 | free_gen8_temp_bitmaps(unsigned long *new_pds, unsigned long *new_pts) |
d7b2633d | 1257 | { |
d7b2633d MT |
1258 | kfree(new_pts); |
1259 | kfree(new_pds); | |
1260 | } | |
1261 | ||
1262 | /* Fills in the page directory bitmap, and the array of page tables bitmap. Both | |
1263 | * of these are based on the number of PDPEs in the system. | |
1264 | */ | |
1265 | static | |
1266 | int __must_check alloc_gen8_temp_bitmaps(unsigned long **new_pds, | |
3a41a05d | 1267 | unsigned long **new_pts, |
6ac18502 | 1268 | uint32_t pdpes) |
d7b2633d | 1269 | { |
d7b2633d | 1270 | unsigned long *pds; |
3a41a05d | 1271 | unsigned long *pts; |
d7b2633d | 1272 | |
3a41a05d | 1273 | pds = kcalloc(BITS_TO_LONGS(pdpes), sizeof(unsigned long), GFP_TEMPORARY); |
d7b2633d MT |
1274 | if (!pds) |
1275 | return -ENOMEM; | |
1276 | ||
3a41a05d MW |
1277 | pts = kcalloc(pdpes, BITS_TO_LONGS(I915_PDES) * sizeof(unsigned long), |
1278 | GFP_TEMPORARY); | |
1279 | if (!pts) | |
1280 | goto err_out; | |
d7b2633d MT |
1281 | |
1282 | *new_pds = pds; | |
1283 | *new_pts = pts; | |
1284 | ||
1285 | return 0; | |
1286 | ||
1287 | err_out: | |
3a41a05d | 1288 | free_gen8_temp_bitmaps(pds, pts); |
d7b2633d MT |
1289 | return -ENOMEM; |
1290 | } | |
1291 | ||
762d9936 MT |
1292 | static int gen8_alloc_va_range_3lvl(struct i915_address_space *vm, |
1293 | struct i915_page_directory_pointer *pdp, | |
1294 | uint64_t start, | |
1295 | uint64_t length) | |
bf2b4ed2 | 1296 | { |
e5716f55 | 1297 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
3a41a05d | 1298 | unsigned long *new_page_dirs, *new_page_tables; |
49d73912 | 1299 | struct drm_i915_private *dev_priv = vm->i915; |
5441f0cb | 1300 | struct i915_page_directory *pd; |
33c8819f MT |
1301 | const uint64_t orig_start = start; |
1302 | const uint64_t orig_length = length; | |
5441f0cb | 1303 | uint32_t pdpe; |
275a991c | 1304 | uint32_t pdpes = I915_PDPES_PER_PDP(dev_priv); |
bf2b4ed2 BW |
1305 | int ret; |
1306 | ||
d7b2633d MT |
1307 | /* Wrap is never okay since we can only represent 48b, and we don't |
1308 | * actually use the other side of the canonical address space. | |
1309 | */ | |
1310 | if (WARN_ON(start + length < start)) | |
a05d80ee MK |
1311 | return -ENODEV; |
1312 | ||
d4ec9da0 | 1313 | if (WARN_ON(start + length > vm->total)) |
a05d80ee | 1314 | return -ENODEV; |
d7b2633d | 1315 | |
6ac18502 | 1316 | ret = alloc_gen8_temp_bitmaps(&new_page_dirs, &new_page_tables, pdpes); |
bf2b4ed2 BW |
1317 | if (ret) |
1318 | return ret; | |
1319 | ||
d7b2633d | 1320 | /* Do the allocations first so we can easily bail out */ |
d4ec9da0 MT |
1321 | ret = gen8_ppgtt_alloc_page_directories(vm, pdp, start, length, |
1322 | new_page_dirs); | |
d7b2633d | 1323 | if (ret) { |
3a41a05d | 1324 | free_gen8_temp_bitmaps(new_page_dirs, new_page_tables); |
d7b2633d MT |
1325 | return ret; |
1326 | } | |
1327 | ||
1328 | /* For every page directory referenced, allocate page tables */ | |
e8ebd8e2 | 1329 | gen8_for_each_pdpe(pd, pdp, start, length, pdpe) { |
d4ec9da0 | 1330 | ret = gen8_ppgtt_alloc_pagetabs(vm, pd, start, length, |
3a41a05d | 1331 | new_page_tables + pdpe * BITS_TO_LONGS(I915_PDES)); |
5441f0cb MT |
1332 | if (ret) |
1333 | goto err_out; | |
5441f0cb MT |
1334 | } |
1335 | ||
33c8819f MT |
1336 | start = orig_start; |
1337 | length = orig_length; | |
1338 | ||
d7b2633d MT |
1339 | /* Allocations have completed successfully, so set the bitmaps, and do |
1340 | * the mappings. */ | |
e8ebd8e2 | 1341 | gen8_for_each_pdpe(pd, pdp, start, length, pdpe) { |
d1c54acd | 1342 | gen8_pde_t *const page_directory = kmap_px(pd); |
33c8819f | 1343 | struct i915_page_table *pt; |
09120d4e | 1344 | uint64_t pd_len = length; |
33c8819f MT |
1345 | uint64_t pd_start = start; |
1346 | uint32_t pde; | |
1347 | ||
d7b2633d MT |
1348 | /* Every pd should be allocated, we just did that above. */ |
1349 | WARN_ON(!pd); | |
1350 | ||
e8ebd8e2 | 1351 | gen8_for_each_pde(pt, pd, pd_start, pd_len, pde) { |
d7b2633d MT |
1352 | /* Same reasoning as pd */ |
1353 | WARN_ON(!pt); | |
1354 | WARN_ON(!pd_len); | |
1355 | WARN_ON(!gen8_pte_count(pd_start, pd_len)); | |
1356 | ||
1357 | /* Set our used ptes within the page table */ | |
1358 | bitmap_set(pt->used_ptes, | |
1359 | gen8_pte_index(pd_start), | |
1360 | gen8_pte_count(pd_start, pd_len)); | |
1361 | ||
1362 | /* Our pde is now pointing to the pagetable, pt */ | |
966082c9 | 1363 | __set_bit(pde, pd->used_pdes); |
d7b2633d MT |
1364 | |
1365 | /* Map the PDE to the page table */ | |
fe36f55d MK |
1366 | page_directory[pde] = gen8_pde_encode(px_dma(pt), |
1367 | I915_CACHE_LLC); | |
4c06ec8d MT |
1368 | trace_i915_page_table_entry_map(&ppgtt->base, pde, pt, |
1369 | gen8_pte_index(start), | |
1370 | gen8_pte_count(start, length), | |
1371 | GEN8_PTES); | |
d7b2633d MT |
1372 | |
1373 | /* NB: We haven't yet mapped ptes to pages. At this | |
1374 | * point we're still relying on insert_entries() */ | |
33c8819f | 1375 | } |
d7b2633d | 1376 | |
d1c54acd | 1377 | kunmap_px(ppgtt, page_directory); |
d4ec9da0 | 1378 | __set_bit(pdpe, pdp->used_pdpes); |
762d9936 | 1379 | gen8_setup_page_directory(ppgtt, pdp, pd, pdpe); |
33c8819f MT |
1380 | } |
1381 | ||
3a41a05d | 1382 | free_gen8_temp_bitmaps(new_page_dirs, new_page_tables); |
5b7e4c9c | 1383 | mark_tlbs_dirty(ppgtt); |
d7b3de91 | 1384 | return 0; |
bf2b4ed2 | 1385 | |
d7b3de91 | 1386 | err_out: |
d7b2633d | 1387 | while (pdpe--) { |
e8ebd8e2 DG |
1388 | unsigned long temp; |
1389 | ||
3a41a05d MW |
1390 | for_each_set_bit(temp, new_page_tables + pdpe * |
1391 | BITS_TO_LONGS(I915_PDES), I915_PDES) | |
275a991c TU |
1392 | free_pt(dev_priv, |
1393 | pdp->page_directory[pdpe]->page_table[temp]); | |
d7b2633d MT |
1394 | } |
1395 | ||
6ac18502 | 1396 | for_each_set_bit(pdpe, new_page_dirs, pdpes) |
275a991c | 1397 | free_pd(dev_priv, pdp->page_directory[pdpe]); |
d7b2633d | 1398 | |
3a41a05d | 1399 | free_gen8_temp_bitmaps(new_page_dirs, new_page_tables); |
5b7e4c9c | 1400 | mark_tlbs_dirty(ppgtt); |
bf2b4ed2 BW |
1401 | return ret; |
1402 | } | |
1403 | ||
762d9936 MT |
1404 | static int gen8_alloc_va_range_4lvl(struct i915_address_space *vm, |
1405 | struct i915_pml4 *pml4, | |
1406 | uint64_t start, | |
1407 | uint64_t length) | |
1408 | { | |
1409 | DECLARE_BITMAP(new_pdps, GEN8_PML4ES_PER_PML4); | |
e5716f55 | 1410 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
762d9936 | 1411 | struct i915_page_directory_pointer *pdp; |
e8ebd8e2 | 1412 | uint64_t pml4e; |
762d9936 MT |
1413 | int ret = 0; |
1414 | ||
1415 | /* Do the pml4 allocations first, so we don't need to track the newly | |
1416 | * allocated tables below the pdp */ | |
1417 | bitmap_zero(new_pdps, GEN8_PML4ES_PER_PML4); | |
1418 | ||
1419 | /* The pagedirectory and pagetable allocations are done in the shared 3 | |
1420 | * and 4 level code. Just allocate the pdps. | |
1421 | */ | |
1422 | ret = gen8_ppgtt_alloc_page_dirpointers(vm, pml4, start, length, | |
1423 | new_pdps); | |
1424 | if (ret) | |
1425 | return ret; | |
1426 | ||
1427 | WARN(bitmap_weight(new_pdps, GEN8_PML4ES_PER_PML4) > 2, | |
1428 | "The allocation has spanned more than 512GB. " | |
1429 | "It is highly likely this is incorrect."); | |
1430 | ||
e8ebd8e2 | 1431 | gen8_for_each_pml4e(pdp, pml4, start, length, pml4e) { |
762d9936 MT |
1432 | WARN_ON(!pdp); |
1433 | ||
1434 | ret = gen8_alloc_va_range_3lvl(vm, pdp, start, length); | |
1435 | if (ret) | |
1436 | goto err_out; | |
1437 | ||
1438 | gen8_setup_page_directory_pointer(ppgtt, pml4, pdp, pml4e); | |
1439 | } | |
1440 | ||
1441 | bitmap_or(pml4->used_pml4es, new_pdps, pml4->used_pml4es, | |
1442 | GEN8_PML4ES_PER_PML4); | |
1443 | ||
1444 | return 0; | |
1445 | ||
1446 | err_out: | |
1447 | for_each_set_bit(pml4e, new_pdps, GEN8_PML4ES_PER_PML4) | |
49d73912 | 1448 | gen8_ppgtt_cleanup_3lvl(vm->i915, pml4->pdps[pml4e]); |
762d9936 MT |
1449 | |
1450 | return ret; | |
1451 | } | |
1452 | ||
1453 | static int gen8_alloc_va_range(struct i915_address_space *vm, | |
1454 | uint64_t start, uint64_t length) | |
1455 | { | |
e5716f55 | 1456 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
762d9936 | 1457 | |
c6385c94 | 1458 | if (USES_FULL_48BIT_PPGTT(vm->i915)) |
762d9936 MT |
1459 | return gen8_alloc_va_range_4lvl(vm, &ppgtt->pml4, start, length); |
1460 | else | |
1461 | return gen8_alloc_va_range_3lvl(vm, &ppgtt->pdp, start, length); | |
1462 | } | |
1463 | ||
ea91e401 MT |
1464 | static void gen8_dump_pdp(struct i915_page_directory_pointer *pdp, |
1465 | uint64_t start, uint64_t length, | |
1466 | gen8_pte_t scratch_pte, | |
1467 | struct seq_file *m) | |
1468 | { | |
1469 | struct i915_page_directory *pd; | |
ea91e401 MT |
1470 | uint32_t pdpe; |
1471 | ||
e8ebd8e2 | 1472 | gen8_for_each_pdpe(pd, pdp, start, length, pdpe) { |
ea91e401 MT |
1473 | struct i915_page_table *pt; |
1474 | uint64_t pd_len = length; | |
1475 | uint64_t pd_start = start; | |
1476 | uint32_t pde; | |
1477 | ||
1478 | if (!test_bit(pdpe, pdp->used_pdpes)) | |
1479 | continue; | |
1480 | ||
1481 | seq_printf(m, "\tPDPE #%d\n", pdpe); | |
e8ebd8e2 | 1482 | gen8_for_each_pde(pt, pd, pd_start, pd_len, pde) { |
ea91e401 MT |
1483 | uint32_t pte; |
1484 | gen8_pte_t *pt_vaddr; | |
1485 | ||
1486 | if (!test_bit(pde, pd->used_pdes)) | |
1487 | continue; | |
1488 | ||
1489 | pt_vaddr = kmap_px(pt); | |
1490 | for (pte = 0; pte < GEN8_PTES; pte += 4) { | |
1491 | uint64_t va = | |
1492 | (pdpe << GEN8_PDPE_SHIFT) | | |
1493 | (pde << GEN8_PDE_SHIFT) | | |
1494 | (pte << GEN8_PTE_SHIFT); | |
1495 | int i; | |
1496 | bool found = false; | |
1497 | ||
1498 | for (i = 0; i < 4; i++) | |
1499 | if (pt_vaddr[pte + i] != scratch_pte) | |
1500 | found = true; | |
1501 | if (!found) | |
1502 | continue; | |
1503 | ||
1504 | seq_printf(m, "\t\t0x%llx [%03d,%03d,%04d]: =", va, pdpe, pde, pte); | |
1505 | for (i = 0; i < 4; i++) { | |
1506 | if (pt_vaddr[pte + i] != scratch_pte) | |
1507 | seq_printf(m, " %llx", pt_vaddr[pte + i]); | |
1508 | else | |
1509 | seq_puts(m, " SCRATCH "); | |
1510 | } | |
1511 | seq_puts(m, "\n"); | |
1512 | } | |
1513 | /* don't use kunmap_px, it could trigger | |
1514 | * an unnecessary flush. | |
1515 | */ | |
1516 | kunmap_atomic(pt_vaddr); | |
1517 | } | |
1518 | } | |
1519 | } | |
1520 | ||
1521 | static void gen8_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m) | |
1522 | { | |
1523 | struct i915_address_space *vm = &ppgtt->base; | |
1524 | uint64_t start = ppgtt->base.start; | |
1525 | uint64_t length = ppgtt->base.total; | |
8bcdd0f7 | 1526 | gen8_pte_t scratch_pte = gen8_pte_encode(vm->scratch_page.daddr, |
4fb84d99 | 1527 | I915_CACHE_LLC); |
ea91e401 | 1528 | |
c6385c94 | 1529 | if (!USES_FULL_48BIT_PPGTT(vm->i915)) { |
ea91e401 MT |
1530 | gen8_dump_pdp(&ppgtt->pdp, start, length, scratch_pte, m); |
1531 | } else { | |
e8ebd8e2 | 1532 | uint64_t pml4e; |
ea91e401 MT |
1533 | struct i915_pml4 *pml4 = &ppgtt->pml4; |
1534 | struct i915_page_directory_pointer *pdp; | |
1535 | ||
e8ebd8e2 | 1536 | gen8_for_each_pml4e(pdp, pml4, start, length, pml4e) { |
ea91e401 MT |
1537 | if (!test_bit(pml4e, pml4->used_pml4es)) |
1538 | continue; | |
1539 | ||
1540 | seq_printf(m, " PML4E #%llu\n", pml4e); | |
1541 | gen8_dump_pdp(pdp, start, length, scratch_pte, m); | |
1542 | } | |
1543 | } | |
1544 | } | |
1545 | ||
331f38e7 ZL |
1546 | static int gen8_preallocate_top_level_pdps(struct i915_hw_ppgtt *ppgtt) |
1547 | { | |
3a41a05d | 1548 | unsigned long *new_page_dirs, *new_page_tables; |
275a991c | 1549 | uint32_t pdpes = I915_PDPES_PER_PDP(to_i915(ppgtt->base.dev)); |
331f38e7 ZL |
1550 | int ret; |
1551 | ||
1552 | /* We allocate temp bitmap for page tables for no gain | |
1553 | * but as this is for init only, lets keep the things simple | |
1554 | */ | |
1555 | ret = alloc_gen8_temp_bitmaps(&new_page_dirs, &new_page_tables, pdpes); | |
1556 | if (ret) | |
1557 | return ret; | |
1558 | ||
1559 | /* Allocate for all pdps regardless of how the ppgtt | |
1560 | * was defined. | |
1561 | */ | |
1562 | ret = gen8_ppgtt_alloc_page_directories(&ppgtt->base, &ppgtt->pdp, | |
1563 | 0, 1ULL << 32, | |
1564 | new_page_dirs); | |
1565 | if (!ret) | |
1566 | *ppgtt->pdp.used_pdpes = *new_page_dirs; | |
1567 | ||
3a41a05d | 1568 | free_gen8_temp_bitmaps(new_page_dirs, new_page_tables); |
331f38e7 ZL |
1569 | |
1570 | return ret; | |
1571 | } | |
1572 | ||
eb0b44ad | 1573 | /* |
f3a964b9 BW |
1574 | * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers |
1575 | * with a net effect resembling a 2-level page table in normal x86 terms. Each | |
1576 | * PDP represents 1GB of memory 4 * 512 * 512 * 4096 = 4GB legacy 32b address | |
1577 | * space. | |
37aca44a | 1578 | * |
f3a964b9 | 1579 | */ |
5c5f6457 | 1580 | static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt) |
37aca44a | 1581 | { |
49d73912 | 1582 | struct drm_i915_private *dev_priv = ppgtt->base.i915; |
8776f02b | 1583 | int ret; |
7cb6d7ac | 1584 | |
8776f02b MK |
1585 | ret = gen8_init_scratch(&ppgtt->base); |
1586 | if (ret) | |
1587 | return ret; | |
69876bed | 1588 | |
d7b2633d | 1589 | ppgtt->base.start = 0; |
d7b2633d | 1590 | ppgtt->base.cleanup = gen8_ppgtt_cleanup; |
5c5f6457 | 1591 | ppgtt->base.allocate_va_range = gen8_alloc_va_range; |
d7b2633d | 1592 | ppgtt->base.insert_entries = gen8_ppgtt_insert_entries; |
c7e16f22 | 1593 | ppgtt->base.clear_range = gen8_ppgtt_clear_range; |
777dc5bb DV |
1594 | ppgtt->base.unbind_vma = ppgtt_unbind_vma; |
1595 | ppgtt->base.bind_vma = ppgtt_bind_vma; | |
ea91e401 | 1596 | ppgtt->debug_dump = gen8_dump_ppgtt; |
d7b2633d | 1597 | |
275a991c TU |
1598 | if (USES_FULL_48BIT_PPGTT(dev_priv)) { |
1599 | ret = setup_px(dev_priv, &ppgtt->pml4); | |
762d9936 MT |
1600 | if (ret) |
1601 | goto free_scratch; | |
6ac18502 | 1602 | |
69ab76fd MT |
1603 | gen8_initialize_pml4(&ppgtt->base, &ppgtt->pml4); |
1604 | ||
762d9936 | 1605 | ppgtt->base.total = 1ULL << 48; |
2dba3239 | 1606 | ppgtt->switch_mm = gen8_48b_mm_switch; |
762d9936 | 1607 | } else { |
275a991c | 1608 | ret = __pdp_init(dev_priv, &ppgtt->pdp); |
81ba8aef MT |
1609 | if (ret) |
1610 | goto free_scratch; | |
1611 | ||
1612 | ppgtt->base.total = 1ULL << 32; | |
2dba3239 | 1613 | ppgtt->switch_mm = gen8_legacy_mm_switch; |
762d9936 MT |
1614 | trace_i915_page_directory_pointer_entry_alloc(&ppgtt->base, |
1615 | 0, 0, | |
1616 | GEN8_PML4E_SHIFT); | |
331f38e7 | 1617 | |
275a991c | 1618 | if (intel_vgpu_active(dev_priv)) { |
331f38e7 ZL |
1619 | ret = gen8_preallocate_top_level_pdps(ppgtt); |
1620 | if (ret) | |
1621 | goto free_scratch; | |
1622 | } | |
81ba8aef | 1623 | } |
6ac18502 | 1624 | |
275a991c | 1625 | if (intel_vgpu_active(dev_priv)) |
650da34c ZL |
1626 | gen8_ppgtt_notify_vgt(ppgtt, true); |
1627 | ||
d7b2633d | 1628 | return 0; |
6ac18502 MT |
1629 | |
1630 | free_scratch: | |
1631 | gen8_free_scratch(&ppgtt->base); | |
1632 | return ret; | |
d7b2633d MT |
1633 | } |
1634 | ||
87d60b63 BW |
1635 | static void gen6_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m) |
1636 | { | |
87d60b63 | 1637 | struct i915_address_space *vm = &ppgtt->base; |
09942c65 | 1638 | struct i915_page_table *unused; |
07749ef3 | 1639 | gen6_pte_t scratch_pte; |
87d60b63 | 1640 | uint32_t pd_entry; |
731f74c5 | 1641 | uint32_t pte, pde; |
09942c65 | 1642 | uint32_t start = ppgtt->base.start, length = ppgtt->base.total; |
87d60b63 | 1643 | |
8bcdd0f7 | 1644 | scratch_pte = vm->pte_encode(vm->scratch_page.daddr, |
4fb84d99 | 1645 | I915_CACHE_LLC, 0); |
87d60b63 | 1646 | |
731f74c5 | 1647 | gen6_for_each_pde(unused, &ppgtt->pd, start, length, pde) { |
87d60b63 | 1648 | u32 expected; |
07749ef3 | 1649 | gen6_pte_t *pt_vaddr; |
567047be | 1650 | const dma_addr_t pt_addr = px_dma(ppgtt->pd.page_table[pde]); |
09942c65 | 1651 | pd_entry = readl(ppgtt->pd_addr + pde); |
87d60b63 BW |
1652 | expected = (GEN6_PDE_ADDR_ENCODE(pt_addr) | GEN6_PDE_VALID); |
1653 | ||
1654 | if (pd_entry != expected) | |
1655 | seq_printf(m, "\tPDE #%d mismatch: Actual PDE: %x Expected PDE: %x\n", | |
1656 | pde, | |
1657 | pd_entry, | |
1658 | expected); | |
1659 | seq_printf(m, "\tPDE: %x\n", pd_entry); | |
1660 | ||
d1c54acd MK |
1661 | pt_vaddr = kmap_px(ppgtt->pd.page_table[pde]); |
1662 | ||
07749ef3 | 1663 | for (pte = 0; pte < GEN6_PTES; pte+=4) { |
87d60b63 | 1664 | unsigned long va = |
07749ef3 | 1665 | (pde * PAGE_SIZE * GEN6_PTES) + |
87d60b63 BW |
1666 | (pte * PAGE_SIZE); |
1667 | int i; | |
1668 | bool found = false; | |
1669 | for (i = 0; i < 4; i++) | |
1670 | if (pt_vaddr[pte + i] != scratch_pte) | |
1671 | found = true; | |
1672 | if (!found) | |
1673 | continue; | |
1674 | ||
1675 | seq_printf(m, "\t\t0x%lx [%03d,%04d]: =", va, pde, pte); | |
1676 | for (i = 0; i < 4; i++) { | |
1677 | if (pt_vaddr[pte + i] != scratch_pte) | |
1678 | seq_printf(m, " %08x", pt_vaddr[pte + i]); | |
1679 | else | |
1680 | seq_puts(m, " SCRATCH "); | |
1681 | } | |
1682 | seq_puts(m, "\n"); | |
1683 | } | |
d1c54acd | 1684 | kunmap_px(ppgtt, pt_vaddr); |
87d60b63 BW |
1685 | } |
1686 | } | |
1687 | ||
678d96fb | 1688 | /* Write pde (index) from the page directory @pd to the page table @pt */ |
ec565b3c MT |
1689 | static void gen6_write_pde(struct i915_page_directory *pd, |
1690 | const int pde, struct i915_page_table *pt) | |
6197349b | 1691 | { |
678d96fb BW |
1692 | /* Caller needs to make sure the write completes if necessary */ |
1693 | struct i915_hw_ppgtt *ppgtt = | |
1694 | container_of(pd, struct i915_hw_ppgtt, pd); | |
1695 | u32 pd_entry; | |
6197349b | 1696 | |
567047be | 1697 | pd_entry = GEN6_PDE_ADDR_ENCODE(px_dma(pt)); |
678d96fb | 1698 | pd_entry |= GEN6_PDE_VALID; |
6197349b | 1699 | |
678d96fb BW |
1700 | writel(pd_entry, ppgtt->pd_addr + pde); |
1701 | } | |
6197349b | 1702 | |
678d96fb BW |
1703 | /* Write all the page tables found in the ppgtt structure to incrementing page |
1704 | * directories. */ | |
1705 | static void gen6_write_page_range(struct drm_i915_private *dev_priv, | |
ec565b3c | 1706 | struct i915_page_directory *pd, |
678d96fb BW |
1707 | uint32_t start, uint32_t length) |
1708 | { | |
72e96d64 | 1709 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
ec565b3c | 1710 | struct i915_page_table *pt; |
731f74c5 | 1711 | uint32_t pde; |
678d96fb | 1712 | |
731f74c5 | 1713 | gen6_for_each_pde(pt, pd, start, length, pde) |
678d96fb BW |
1714 | gen6_write_pde(pd, pde, pt); |
1715 | ||
1716 | /* Make sure write is complete before other code can use this page | |
1717 | * table. Also require for WC mapped PTEs */ | |
72e96d64 | 1718 | readl(ggtt->gsm); |
3e302542 BW |
1719 | } |
1720 | ||
b4a74e3a | 1721 | static uint32_t get_pd_offset(struct i915_hw_ppgtt *ppgtt) |
3e302542 | 1722 | { |
44159ddb | 1723 | BUG_ON(ppgtt->pd.base.ggtt_offset & 0x3f); |
b4a74e3a | 1724 | |
44159ddb | 1725 | return (ppgtt->pd.base.ggtt_offset / 64) << 16; |
b4a74e3a BW |
1726 | } |
1727 | ||
90252e5c | 1728 | static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt, |
e85b26dc | 1729 | struct drm_i915_gem_request *req) |
90252e5c | 1730 | { |
7e37f889 | 1731 | struct intel_ring *ring = req->ring; |
4a570db5 | 1732 | struct intel_engine_cs *engine = req->engine; |
90252e5c BW |
1733 | int ret; |
1734 | ||
90252e5c | 1735 | /* NB: TLBs must be flushed and invalidated before a switch */ |
7c9cf4e3 | 1736 | ret = engine->emit_flush(req, EMIT_INVALIDATE | EMIT_FLUSH); |
90252e5c BW |
1737 | if (ret) |
1738 | return ret; | |
1739 | ||
5fb9de1a | 1740 | ret = intel_ring_begin(req, 6); |
90252e5c BW |
1741 | if (ret) |
1742 | return ret; | |
1743 | ||
b5321f30 CW |
1744 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2)); |
1745 | intel_ring_emit_reg(ring, RING_PP_DIR_DCLV(engine)); | |
1746 | intel_ring_emit(ring, PP_DIR_DCLV_2G); | |
1747 | intel_ring_emit_reg(ring, RING_PP_DIR_BASE(engine)); | |
1748 | intel_ring_emit(ring, get_pd_offset(ppgtt)); | |
1749 | intel_ring_emit(ring, MI_NOOP); | |
1750 | intel_ring_advance(ring); | |
90252e5c BW |
1751 | |
1752 | return 0; | |
1753 | } | |
1754 | ||
48a10389 | 1755 | static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt, |
e85b26dc | 1756 | struct drm_i915_gem_request *req) |
48a10389 | 1757 | { |
7e37f889 | 1758 | struct intel_ring *ring = req->ring; |
4a570db5 | 1759 | struct intel_engine_cs *engine = req->engine; |
48a10389 BW |
1760 | int ret; |
1761 | ||
48a10389 | 1762 | /* NB: TLBs must be flushed and invalidated before a switch */ |
7c9cf4e3 | 1763 | ret = engine->emit_flush(req, EMIT_INVALIDATE | EMIT_FLUSH); |
48a10389 BW |
1764 | if (ret) |
1765 | return ret; | |
1766 | ||
5fb9de1a | 1767 | ret = intel_ring_begin(req, 6); |
48a10389 BW |
1768 | if (ret) |
1769 | return ret; | |
1770 | ||
b5321f30 CW |
1771 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2)); |
1772 | intel_ring_emit_reg(ring, RING_PP_DIR_DCLV(engine)); | |
1773 | intel_ring_emit(ring, PP_DIR_DCLV_2G); | |
1774 | intel_ring_emit_reg(ring, RING_PP_DIR_BASE(engine)); | |
1775 | intel_ring_emit(ring, get_pd_offset(ppgtt)); | |
1776 | intel_ring_emit(ring, MI_NOOP); | |
1777 | intel_ring_advance(ring); | |
48a10389 | 1778 | |
90252e5c | 1779 | /* XXX: RCS is the only one to auto invalidate the TLBs? */ |
e2f80391 | 1780 | if (engine->id != RCS) { |
7c9cf4e3 | 1781 | ret = engine->emit_flush(req, EMIT_INVALIDATE | EMIT_FLUSH); |
90252e5c BW |
1782 | if (ret) |
1783 | return ret; | |
1784 | } | |
1785 | ||
48a10389 BW |
1786 | return 0; |
1787 | } | |
1788 | ||
eeb9488e | 1789 | static int gen6_mm_switch(struct i915_hw_ppgtt *ppgtt, |
e85b26dc | 1790 | struct drm_i915_gem_request *req) |
eeb9488e | 1791 | { |
4a570db5 | 1792 | struct intel_engine_cs *engine = req->engine; |
8eb95204 | 1793 | struct drm_i915_private *dev_priv = req->i915; |
48a10389 | 1794 | |
e2f80391 TU |
1795 | I915_WRITE(RING_PP_DIR_DCLV(engine), PP_DIR_DCLV_2G); |
1796 | I915_WRITE(RING_PP_DIR_BASE(engine), get_pd_offset(ppgtt)); | |
eeb9488e BW |
1797 | return 0; |
1798 | } | |
1799 | ||
c6be607a | 1800 | static void gen8_ppgtt_enable(struct drm_i915_private *dev_priv) |
eeb9488e | 1801 | { |
e2f80391 | 1802 | struct intel_engine_cs *engine; |
3b3f1650 | 1803 | enum intel_engine_id id; |
3e302542 | 1804 | |
3b3f1650 | 1805 | for_each_engine(engine, dev_priv, id) { |
c6be607a TU |
1806 | u32 four_level = USES_FULL_48BIT_PPGTT(dev_priv) ? |
1807 | GEN8_GFX_PPGTT_48B : 0; | |
e2f80391 | 1808 | I915_WRITE(RING_MODE_GEN7(engine), |
2dba3239 | 1809 | _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE | four_level)); |
eeb9488e | 1810 | } |
eeb9488e | 1811 | } |
6197349b | 1812 | |
c6be607a | 1813 | static void gen7_ppgtt_enable(struct drm_i915_private *dev_priv) |
3e302542 | 1814 | { |
e2f80391 | 1815 | struct intel_engine_cs *engine; |
b4a74e3a | 1816 | uint32_t ecochk, ecobits; |
3b3f1650 | 1817 | enum intel_engine_id id; |
6197349b | 1818 | |
b4a74e3a BW |
1819 | ecobits = I915_READ(GAC_ECO_BITS); |
1820 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B); | |
a65c2fcd | 1821 | |
b4a74e3a | 1822 | ecochk = I915_READ(GAM_ECOCHK); |
772c2a51 | 1823 | if (IS_HASWELL(dev_priv)) { |
b4a74e3a BW |
1824 | ecochk |= ECOCHK_PPGTT_WB_HSW; |
1825 | } else { | |
1826 | ecochk |= ECOCHK_PPGTT_LLC_IVB; | |
1827 | ecochk &= ~ECOCHK_PPGTT_GFDT_IVB; | |
1828 | } | |
1829 | I915_WRITE(GAM_ECOCHK, ecochk); | |
a65c2fcd | 1830 | |
3b3f1650 | 1831 | for_each_engine(engine, dev_priv, id) { |
6197349b | 1832 | /* GFX_MODE is per-ring on gen7+ */ |
e2f80391 | 1833 | I915_WRITE(RING_MODE_GEN7(engine), |
b4a74e3a | 1834 | _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); |
6197349b | 1835 | } |
b4a74e3a | 1836 | } |
6197349b | 1837 | |
c6be607a | 1838 | static void gen6_ppgtt_enable(struct drm_i915_private *dev_priv) |
b4a74e3a | 1839 | { |
b4a74e3a | 1840 | uint32_t ecochk, gab_ctl, ecobits; |
a65c2fcd | 1841 | |
b4a74e3a BW |
1842 | ecobits = I915_READ(GAC_ECO_BITS); |
1843 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT | | |
1844 | ECOBITS_PPGTT_CACHE64B); | |
6197349b | 1845 | |
b4a74e3a BW |
1846 | gab_ctl = I915_READ(GAB_CTL); |
1847 | I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT); | |
1848 | ||
1849 | ecochk = I915_READ(GAM_ECOCHK); | |
1850 | I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B); | |
1851 | ||
1852 | I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
6197349b BW |
1853 | } |
1854 | ||
1d2a314c | 1855 | /* PPGTT support for Sandybdrige/Gen6 and later */ |
853ba5d2 | 1856 | static void gen6_ppgtt_clear_range(struct i915_address_space *vm, |
782f1495 | 1857 | uint64_t start, |
4fb84d99 | 1858 | uint64_t length) |
1d2a314c | 1859 | { |
e5716f55 | 1860 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
07749ef3 | 1861 | gen6_pte_t *pt_vaddr, scratch_pte; |
782f1495 BW |
1862 | unsigned first_entry = start >> PAGE_SHIFT; |
1863 | unsigned num_entries = length >> PAGE_SHIFT; | |
07749ef3 MT |
1864 | unsigned act_pt = first_entry / GEN6_PTES; |
1865 | unsigned first_pte = first_entry % GEN6_PTES; | |
7bddb01f | 1866 | unsigned last_pte, i; |
1d2a314c | 1867 | |
8bcdd0f7 | 1868 | scratch_pte = vm->pte_encode(vm->scratch_page.daddr, |
4fb84d99 | 1869 | I915_CACHE_LLC, 0); |
1d2a314c | 1870 | |
7bddb01f DV |
1871 | while (num_entries) { |
1872 | last_pte = first_pte + num_entries; | |
07749ef3 MT |
1873 | if (last_pte > GEN6_PTES) |
1874 | last_pte = GEN6_PTES; | |
7bddb01f | 1875 | |
d1c54acd | 1876 | pt_vaddr = kmap_px(ppgtt->pd.page_table[act_pt]); |
1d2a314c | 1877 | |
7bddb01f DV |
1878 | for (i = first_pte; i < last_pte; i++) |
1879 | pt_vaddr[i] = scratch_pte; | |
1d2a314c | 1880 | |
d1c54acd | 1881 | kunmap_px(ppgtt, pt_vaddr); |
1d2a314c | 1882 | |
7bddb01f DV |
1883 | num_entries -= last_pte - first_pte; |
1884 | first_pte = 0; | |
a15326a5 | 1885 | act_pt++; |
7bddb01f | 1886 | } |
1d2a314c DV |
1887 | } |
1888 | ||
853ba5d2 | 1889 | static void gen6_ppgtt_insert_entries(struct i915_address_space *vm, |
def886c3 | 1890 | struct sg_table *pages, |
782f1495 | 1891 | uint64_t start, |
24f3a8cf | 1892 | enum i915_cache_level cache_level, u32 flags) |
def886c3 | 1893 | { |
e5716f55 | 1894 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
782f1495 | 1895 | unsigned first_entry = start >> PAGE_SHIFT; |
07749ef3 MT |
1896 | unsigned act_pt = first_entry / GEN6_PTES; |
1897 | unsigned act_pte = first_entry % GEN6_PTES; | |
85d1225e DG |
1898 | gen6_pte_t *pt_vaddr = NULL; |
1899 | struct sgt_iter sgt_iter; | |
1900 | dma_addr_t addr; | |
6e995e23 | 1901 | |
85d1225e | 1902 | for_each_sgt_dma(addr, sgt_iter, pages) { |
cc79714f | 1903 | if (pt_vaddr == NULL) |
d1c54acd | 1904 | pt_vaddr = kmap_px(ppgtt->pd.page_table[act_pt]); |
6e995e23 | 1905 | |
cc79714f | 1906 | pt_vaddr[act_pte] = |
4fb84d99 | 1907 | vm->pte_encode(addr, cache_level, flags); |
24f3a8cf | 1908 | |
07749ef3 | 1909 | if (++act_pte == GEN6_PTES) { |
d1c54acd | 1910 | kunmap_px(ppgtt, pt_vaddr); |
cc79714f | 1911 | pt_vaddr = NULL; |
a15326a5 | 1912 | act_pt++; |
6e995e23 | 1913 | act_pte = 0; |
def886c3 | 1914 | } |
def886c3 | 1915 | } |
85d1225e | 1916 | |
cc79714f | 1917 | if (pt_vaddr) |
d1c54acd | 1918 | kunmap_px(ppgtt, pt_vaddr); |
def886c3 DV |
1919 | } |
1920 | ||
678d96fb | 1921 | static int gen6_alloc_va_range(struct i915_address_space *vm, |
a05d80ee | 1922 | uint64_t start_in, uint64_t length_in) |
678d96fb | 1923 | { |
4933d519 | 1924 | DECLARE_BITMAP(new_page_tables, I915_PDES); |
49d73912 | 1925 | struct drm_i915_private *dev_priv = vm->i915; |
72e96d64 | 1926 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
e5716f55 | 1927 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
ec565b3c | 1928 | struct i915_page_table *pt; |
a05d80ee | 1929 | uint32_t start, length, start_save, length_save; |
731f74c5 | 1930 | uint32_t pde; |
4933d519 MT |
1931 | int ret; |
1932 | ||
a05d80ee MK |
1933 | if (WARN_ON(start_in + length_in > ppgtt->base.total)) |
1934 | return -ENODEV; | |
1935 | ||
1936 | start = start_save = start_in; | |
1937 | length = length_save = length_in; | |
4933d519 MT |
1938 | |
1939 | bitmap_zero(new_page_tables, I915_PDES); | |
1940 | ||
1941 | /* The allocation is done in two stages so that we can bail out with | |
1942 | * minimal amount of pain. The first stage finds new page tables that | |
1943 | * need allocation. The second stage marks use ptes within the page | |
1944 | * tables. | |
1945 | */ | |
731f74c5 | 1946 | gen6_for_each_pde(pt, &ppgtt->pd, start, length, pde) { |
79ab9370 | 1947 | if (pt != vm->scratch_pt) { |
4933d519 MT |
1948 | WARN_ON(bitmap_empty(pt->used_ptes, GEN6_PTES)); |
1949 | continue; | |
1950 | } | |
1951 | ||
1952 | /* We've already allocated a page table */ | |
1953 | WARN_ON(!bitmap_empty(pt->used_ptes, GEN6_PTES)); | |
1954 | ||
275a991c | 1955 | pt = alloc_pt(dev_priv); |
4933d519 MT |
1956 | if (IS_ERR(pt)) { |
1957 | ret = PTR_ERR(pt); | |
1958 | goto unwind_out; | |
1959 | } | |
1960 | ||
1961 | gen6_initialize_pt(vm, pt); | |
1962 | ||
1963 | ppgtt->pd.page_table[pde] = pt; | |
966082c9 | 1964 | __set_bit(pde, new_page_tables); |
72744cb1 | 1965 | trace_i915_page_table_entry_alloc(vm, pde, start, GEN6_PDE_SHIFT); |
4933d519 MT |
1966 | } |
1967 | ||
1968 | start = start_save; | |
1969 | length = length_save; | |
678d96fb | 1970 | |
731f74c5 | 1971 | gen6_for_each_pde(pt, &ppgtt->pd, start, length, pde) { |
678d96fb BW |
1972 | DECLARE_BITMAP(tmp_bitmap, GEN6_PTES); |
1973 | ||
1974 | bitmap_zero(tmp_bitmap, GEN6_PTES); | |
1975 | bitmap_set(tmp_bitmap, gen6_pte_index(start), | |
1976 | gen6_pte_count(start, length)); | |
1977 | ||
966082c9 | 1978 | if (__test_and_clear_bit(pde, new_page_tables)) |
4933d519 MT |
1979 | gen6_write_pde(&ppgtt->pd, pde, pt); |
1980 | ||
72744cb1 MT |
1981 | trace_i915_page_table_entry_map(vm, pde, pt, |
1982 | gen6_pte_index(start), | |
1983 | gen6_pte_count(start, length), | |
1984 | GEN6_PTES); | |
4933d519 | 1985 | bitmap_or(pt->used_ptes, tmp_bitmap, pt->used_ptes, |
678d96fb BW |
1986 | GEN6_PTES); |
1987 | } | |
1988 | ||
4933d519 MT |
1989 | WARN_ON(!bitmap_empty(new_page_tables, I915_PDES)); |
1990 | ||
1991 | /* Make sure write is complete before other code can use this page | |
1992 | * table. Also require for WC mapped PTEs */ | |
72e96d64 | 1993 | readl(ggtt->gsm); |
4933d519 | 1994 | |
563222a7 | 1995 | mark_tlbs_dirty(ppgtt); |
678d96fb | 1996 | return 0; |
4933d519 MT |
1997 | |
1998 | unwind_out: | |
1999 | for_each_set_bit(pde, new_page_tables, I915_PDES) { | |
ec565b3c | 2000 | struct i915_page_table *pt = ppgtt->pd.page_table[pde]; |
4933d519 | 2001 | |
79ab9370 | 2002 | ppgtt->pd.page_table[pde] = vm->scratch_pt; |
275a991c | 2003 | free_pt(dev_priv, pt); |
4933d519 MT |
2004 | } |
2005 | ||
2006 | mark_tlbs_dirty(ppgtt); | |
2007 | return ret; | |
678d96fb BW |
2008 | } |
2009 | ||
8776f02b MK |
2010 | static int gen6_init_scratch(struct i915_address_space *vm) |
2011 | { | |
49d73912 | 2012 | struct drm_i915_private *dev_priv = vm->i915; |
8bcdd0f7 | 2013 | int ret; |
8776f02b | 2014 | |
275a991c | 2015 | ret = setup_scratch_page(dev_priv, &vm->scratch_page, I915_GFP_DMA); |
8bcdd0f7 CW |
2016 | if (ret) |
2017 | return ret; | |
8776f02b | 2018 | |
275a991c | 2019 | vm->scratch_pt = alloc_pt(dev_priv); |
8776f02b | 2020 | if (IS_ERR(vm->scratch_pt)) { |
275a991c | 2021 | cleanup_scratch_page(dev_priv, &vm->scratch_page); |
8776f02b MK |
2022 | return PTR_ERR(vm->scratch_pt); |
2023 | } | |
2024 | ||
2025 | gen6_initialize_pt(vm, vm->scratch_pt); | |
2026 | ||
2027 | return 0; | |
2028 | } | |
2029 | ||
2030 | static void gen6_free_scratch(struct i915_address_space *vm) | |
2031 | { | |
49d73912 | 2032 | struct drm_i915_private *dev_priv = vm->i915; |
8776f02b | 2033 | |
275a991c TU |
2034 | free_pt(dev_priv, vm->scratch_pt); |
2035 | cleanup_scratch_page(dev_priv, &vm->scratch_page); | |
8776f02b MK |
2036 | } |
2037 | ||
061dd493 | 2038 | static void gen6_ppgtt_cleanup(struct i915_address_space *vm) |
a00d825d | 2039 | { |
e5716f55 | 2040 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
731f74c5 | 2041 | struct i915_page_directory *pd = &ppgtt->pd; |
49d73912 | 2042 | struct drm_i915_private *dev_priv = vm->i915; |
09942c65 MT |
2043 | struct i915_page_table *pt; |
2044 | uint32_t pde; | |
4933d519 | 2045 | |
061dd493 DV |
2046 | drm_mm_remove_node(&ppgtt->node); |
2047 | ||
731f74c5 | 2048 | gen6_for_all_pdes(pt, pd, pde) |
79ab9370 | 2049 | if (pt != vm->scratch_pt) |
275a991c | 2050 | free_pt(dev_priv, pt); |
06fda602 | 2051 | |
8776f02b | 2052 | gen6_free_scratch(vm); |
3440d265 DV |
2053 | } |
2054 | ||
b146520f | 2055 | static int gen6_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt) |
3440d265 | 2056 | { |
8776f02b | 2057 | struct i915_address_space *vm = &ppgtt->base; |
49d73912 | 2058 | struct drm_i915_private *dev_priv = ppgtt->base.i915; |
72e96d64 | 2059 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
e3cc1995 | 2060 | bool retried = false; |
b146520f | 2061 | int ret; |
1d2a314c | 2062 | |
c8d4c0d6 BW |
2063 | /* PPGTT PDEs reside in the GGTT and consists of 512 entries. The |
2064 | * allocator works in address space sizes, so it's multiplied by page | |
2065 | * size. We allocate at the top of the GTT to avoid fragmentation. | |
2066 | */ | |
72e96d64 | 2067 | BUG_ON(!drm_mm_initialized(&ggtt->base.mm)); |
4933d519 | 2068 | |
8776f02b MK |
2069 | ret = gen6_init_scratch(vm); |
2070 | if (ret) | |
2071 | return ret; | |
4933d519 | 2072 | |
e3cc1995 | 2073 | alloc: |
72e96d64 | 2074 | ret = drm_mm_insert_node_in_range_generic(&ggtt->base.mm, |
c8d4c0d6 BW |
2075 | &ppgtt->node, GEN6_PD_SIZE, |
2076 | GEN6_PD_ALIGN, 0, | |
72e96d64 | 2077 | 0, ggtt->base.total, |
3e8b5ae9 | 2078 | DRM_MM_TOPDOWN); |
e3cc1995 | 2079 | if (ret == -ENOSPC && !retried) { |
e522ac23 | 2080 | ret = i915_gem_evict_something(&ggtt->base, |
e3cc1995 | 2081 | GEN6_PD_SIZE, GEN6_PD_ALIGN, |
d23db88c | 2082 | I915_CACHE_NONE, |
72e96d64 | 2083 | 0, ggtt->base.total, |
d23db88c | 2084 | 0); |
e3cc1995 | 2085 | if (ret) |
678d96fb | 2086 | goto err_out; |
e3cc1995 BW |
2087 | |
2088 | retried = true; | |
2089 | goto alloc; | |
2090 | } | |
c8d4c0d6 | 2091 | |
c8c26622 | 2092 | if (ret) |
678d96fb BW |
2093 | goto err_out; |
2094 | ||
c8c26622 | 2095 | |
72e96d64 | 2096 | if (ppgtt->node.start < ggtt->mappable_end) |
c8d4c0d6 | 2097 | DRM_DEBUG("Forced to use aperture for PDEs\n"); |
1d2a314c | 2098 | |
c8c26622 | 2099 | return 0; |
678d96fb BW |
2100 | |
2101 | err_out: | |
8776f02b | 2102 | gen6_free_scratch(vm); |
678d96fb | 2103 | return ret; |
b146520f BW |
2104 | } |
2105 | ||
b146520f BW |
2106 | static int gen6_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt) |
2107 | { | |
2f2cf682 | 2108 | return gen6_ppgtt_allocate_page_directories(ppgtt); |
4933d519 | 2109 | } |
06dc68d6 | 2110 | |
4933d519 MT |
2111 | static void gen6_scratch_va_range(struct i915_hw_ppgtt *ppgtt, |
2112 | uint64_t start, uint64_t length) | |
2113 | { | |
ec565b3c | 2114 | struct i915_page_table *unused; |
731f74c5 | 2115 | uint32_t pde; |
1d2a314c | 2116 | |
731f74c5 | 2117 | gen6_for_each_pde(unused, &ppgtt->pd, start, length, pde) |
79ab9370 | 2118 | ppgtt->pd.page_table[pde] = ppgtt->base.scratch_pt; |
b146520f BW |
2119 | } |
2120 | ||
5c5f6457 | 2121 | static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt) |
b146520f | 2122 | { |
49d73912 | 2123 | struct drm_i915_private *dev_priv = ppgtt->base.i915; |
72e96d64 | 2124 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
b146520f BW |
2125 | int ret; |
2126 | ||
72e96d64 | 2127 | ppgtt->base.pte_encode = ggtt->base.pte_encode; |
5db94019 | 2128 | if (intel_vgpu_active(dev_priv) || IS_GEN6(dev_priv)) |
b146520f | 2129 | ppgtt->switch_mm = gen6_mm_switch; |
772c2a51 | 2130 | else if (IS_HASWELL(dev_priv)) |
b146520f | 2131 | ppgtt->switch_mm = hsw_mm_switch; |
5db94019 | 2132 | else if (IS_GEN7(dev_priv)) |
b146520f | 2133 | ppgtt->switch_mm = gen7_mm_switch; |
8eb95204 | 2134 | else |
b146520f BW |
2135 | BUG(); |
2136 | ||
2137 | ret = gen6_ppgtt_alloc(ppgtt); | |
2138 | if (ret) | |
2139 | return ret; | |
2140 | ||
5c5f6457 | 2141 | ppgtt->base.allocate_va_range = gen6_alloc_va_range; |
b146520f BW |
2142 | ppgtt->base.clear_range = gen6_ppgtt_clear_range; |
2143 | ppgtt->base.insert_entries = gen6_ppgtt_insert_entries; | |
777dc5bb DV |
2144 | ppgtt->base.unbind_vma = ppgtt_unbind_vma; |
2145 | ppgtt->base.bind_vma = ppgtt_bind_vma; | |
b146520f | 2146 | ppgtt->base.cleanup = gen6_ppgtt_cleanup; |
b146520f | 2147 | ppgtt->base.start = 0; |
09942c65 | 2148 | ppgtt->base.total = I915_PDES * GEN6_PTES * PAGE_SIZE; |
87d60b63 | 2149 | ppgtt->debug_dump = gen6_dump_ppgtt; |
1d2a314c | 2150 | |
44159ddb | 2151 | ppgtt->pd.base.ggtt_offset = |
07749ef3 | 2152 | ppgtt->node.start / PAGE_SIZE * sizeof(gen6_pte_t); |
1d2a314c | 2153 | |
72e96d64 | 2154 | ppgtt->pd_addr = (gen6_pte_t __iomem *)ggtt->gsm + |
44159ddb | 2155 | ppgtt->pd.base.ggtt_offset / sizeof(gen6_pte_t); |
678d96fb | 2156 | |
5c5f6457 | 2157 | gen6_scratch_va_range(ppgtt, 0, ppgtt->base.total); |
1d2a314c | 2158 | |
678d96fb BW |
2159 | gen6_write_page_range(dev_priv, &ppgtt->pd, 0, ppgtt->base.total); |
2160 | ||
440fd528 | 2161 | DRM_DEBUG_DRIVER("Allocated pde space (%lldM) at GTT entry: %llx\n", |
b146520f BW |
2162 | ppgtt->node.size >> 20, |
2163 | ppgtt->node.start / PAGE_SIZE); | |
3440d265 | 2164 | |
fa76da34 | 2165 | DRM_DEBUG("Adding PPGTT at offset %x\n", |
44159ddb | 2166 | ppgtt->pd.base.ggtt_offset << 10); |
fa76da34 | 2167 | |
b146520f | 2168 | return 0; |
3440d265 DV |
2169 | } |
2170 | ||
2bfa996e CW |
2171 | static int __hw_ppgtt_init(struct i915_hw_ppgtt *ppgtt, |
2172 | struct drm_i915_private *dev_priv) | |
3440d265 | 2173 | { |
49d73912 | 2174 | ppgtt->base.i915 = dev_priv; |
3440d265 | 2175 | |
2bfa996e | 2176 | if (INTEL_INFO(dev_priv)->gen < 8) |
5c5f6457 | 2177 | return gen6_ppgtt_init(ppgtt); |
3ed124b2 | 2178 | else |
d7b2633d | 2179 | return gen8_ppgtt_init(ppgtt); |
fa76da34 | 2180 | } |
c114f76a | 2181 | |
a2cad9df | 2182 | static void i915_address_space_init(struct i915_address_space *vm, |
80b204bc CW |
2183 | struct drm_i915_private *dev_priv, |
2184 | const char *name) | |
a2cad9df | 2185 | { |
80b204bc | 2186 | i915_gem_timeline_init(dev_priv, &vm->timeline, name); |
a2cad9df | 2187 | drm_mm_init(&vm->mm, vm->start, vm->total); |
a2cad9df MW |
2188 | INIT_LIST_HEAD(&vm->active_list); |
2189 | INIT_LIST_HEAD(&vm->inactive_list); | |
50e046b6 | 2190 | INIT_LIST_HEAD(&vm->unbound_list); |
a2cad9df MW |
2191 | list_add_tail(&vm->global_link, &dev_priv->vm_list); |
2192 | } | |
2193 | ||
ed9724dd MA |
2194 | static void i915_address_space_fini(struct i915_address_space *vm) |
2195 | { | |
2196 | i915_gem_timeline_fini(&vm->timeline); | |
2197 | drm_mm_takedown(&vm->mm); | |
2198 | list_del(&vm->global_link); | |
2199 | } | |
2200 | ||
c6be607a | 2201 | static void gtt_write_workarounds(struct drm_i915_private *dev_priv) |
d5165ebd | 2202 | { |
d5165ebd TG |
2203 | /* This function is for gtt related workarounds. This function is |
2204 | * called on driver load and after a GPU reset, so you can place | |
2205 | * workarounds here even if they get overwritten by GPU reset. | |
2206 | */ | |
2207 | /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt */ | |
8652744b | 2208 | if (IS_BROADWELL(dev_priv)) |
d5165ebd | 2209 | I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW); |
920a14b2 | 2210 | else if (IS_CHERRYVIEW(dev_priv)) |
d5165ebd | 2211 | I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV); |
d9486e65 | 2212 | else if (IS_SKYLAKE(dev_priv)) |
d5165ebd | 2213 | I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL); |
e2d214ae | 2214 | else if (IS_BROXTON(dev_priv)) |
d5165ebd TG |
2215 | I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT); |
2216 | } | |
2217 | ||
2bfa996e CW |
2218 | static int i915_ppgtt_init(struct i915_hw_ppgtt *ppgtt, |
2219 | struct drm_i915_private *dev_priv, | |
80b204bc CW |
2220 | struct drm_i915_file_private *file_priv, |
2221 | const char *name) | |
fa76da34 | 2222 | { |
2bfa996e | 2223 | int ret; |
3ed124b2 | 2224 | |
2bfa996e | 2225 | ret = __hw_ppgtt_init(ppgtt, dev_priv); |
fa76da34 | 2226 | if (ret == 0) { |
c7c48dfd | 2227 | kref_init(&ppgtt->ref); |
80b204bc | 2228 | i915_address_space_init(&ppgtt->base, dev_priv, name); |
2bfa996e | 2229 | ppgtt->base.file = file_priv; |
93bd8649 | 2230 | } |
1d2a314c DV |
2231 | |
2232 | return ret; | |
2233 | } | |
2234 | ||
c6be607a | 2235 | int i915_ppgtt_init_hw(struct drm_i915_private *dev_priv) |
82460d97 | 2236 | { |
c6be607a | 2237 | gtt_write_workarounds(dev_priv); |
d5165ebd | 2238 | |
671b5013 TD |
2239 | /* In the case of execlists, PPGTT is enabled by the context descriptor |
2240 | * and the PDPs are contained within the context itself. We don't | |
2241 | * need to do anything here. */ | |
2242 | if (i915.enable_execlists) | |
2243 | return 0; | |
2244 | ||
c6be607a | 2245 | if (!USES_PPGTT(dev_priv)) |
82460d97 DV |
2246 | return 0; |
2247 | ||
5db94019 | 2248 | if (IS_GEN6(dev_priv)) |
c6be607a | 2249 | gen6_ppgtt_enable(dev_priv); |
5db94019 | 2250 | else if (IS_GEN7(dev_priv)) |
c6be607a TU |
2251 | gen7_ppgtt_enable(dev_priv); |
2252 | else if (INTEL_GEN(dev_priv) >= 8) | |
2253 | gen8_ppgtt_enable(dev_priv); | |
82460d97 | 2254 | else |
c6be607a | 2255 | MISSING_CASE(INTEL_GEN(dev_priv)); |
82460d97 | 2256 | |
4ad2fd88 JH |
2257 | return 0; |
2258 | } | |
1d2a314c | 2259 | |
4d884705 | 2260 | struct i915_hw_ppgtt * |
2bfa996e | 2261 | i915_ppgtt_create(struct drm_i915_private *dev_priv, |
80b204bc CW |
2262 | struct drm_i915_file_private *fpriv, |
2263 | const char *name) | |
4d884705 DV |
2264 | { |
2265 | struct i915_hw_ppgtt *ppgtt; | |
2266 | int ret; | |
2267 | ||
2268 | ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL); | |
2269 | if (!ppgtt) | |
2270 | return ERR_PTR(-ENOMEM); | |
2271 | ||
80b204bc | 2272 | ret = i915_ppgtt_init(ppgtt, dev_priv, fpriv, name); |
4d884705 DV |
2273 | if (ret) { |
2274 | kfree(ppgtt); | |
2275 | return ERR_PTR(ret); | |
2276 | } | |
2277 | ||
198c974d DCS |
2278 | trace_i915_ppgtt_create(&ppgtt->base); |
2279 | ||
4d884705 DV |
2280 | return ppgtt; |
2281 | } | |
2282 | ||
ed9724dd | 2283 | void i915_ppgtt_release(struct kref *kref) |
ee960be7 DV |
2284 | { |
2285 | struct i915_hw_ppgtt *ppgtt = | |
2286 | container_of(kref, struct i915_hw_ppgtt, ref); | |
2287 | ||
198c974d DCS |
2288 | trace_i915_ppgtt_release(&ppgtt->base); |
2289 | ||
50e046b6 | 2290 | /* vmas should already be unbound and destroyed */ |
ee960be7 DV |
2291 | WARN_ON(!list_empty(&ppgtt->base.active_list)); |
2292 | WARN_ON(!list_empty(&ppgtt->base.inactive_list)); | |
50e046b6 | 2293 | WARN_ON(!list_empty(&ppgtt->base.unbound_list)); |
ee960be7 | 2294 | |
ed9724dd | 2295 | i915_address_space_fini(&ppgtt->base); |
19dd120c | 2296 | |
ee960be7 DV |
2297 | ppgtt->base.cleanup(&ppgtt->base); |
2298 | kfree(ppgtt); | |
2299 | } | |
1d2a314c | 2300 | |
a81cc00c BW |
2301 | /* Certain Gen5 chipsets require require idling the GPU before |
2302 | * unmapping anything from the GTT when VT-d is enabled. | |
2303 | */ | |
97d6d7ab | 2304 | static bool needs_idle_maps(struct drm_i915_private *dev_priv) |
a81cc00c BW |
2305 | { |
2306 | #ifdef CONFIG_INTEL_IOMMU | |
2307 | /* Query intel_iommu to see if we need the workaround. Presumably that | |
2308 | * was loaded first. | |
2309 | */ | |
97d6d7ab | 2310 | if (IS_GEN5(dev_priv) && IS_MOBILE(dev_priv) && intel_iommu_gfx_mapped) |
a81cc00c BW |
2311 | return true; |
2312 | #endif | |
2313 | return false; | |
2314 | } | |
2315 | ||
dc97997a | 2316 | void i915_check_and_clear_faults(struct drm_i915_private *dev_priv) |
828c7908 | 2317 | { |
e2f80391 | 2318 | struct intel_engine_cs *engine; |
3b3f1650 | 2319 | enum intel_engine_id id; |
828c7908 | 2320 | |
dc97997a | 2321 | if (INTEL_INFO(dev_priv)->gen < 6) |
828c7908 BW |
2322 | return; |
2323 | ||
3b3f1650 | 2324 | for_each_engine(engine, dev_priv, id) { |
828c7908 | 2325 | u32 fault_reg; |
e2f80391 | 2326 | fault_reg = I915_READ(RING_FAULT_REG(engine)); |
828c7908 BW |
2327 | if (fault_reg & RING_FAULT_VALID) { |
2328 | DRM_DEBUG_DRIVER("Unexpected fault\n" | |
59a5d290 | 2329 | "\tAddr: 0x%08lx\n" |
828c7908 BW |
2330 | "\tAddress space: %s\n" |
2331 | "\tSource ID: %d\n" | |
2332 | "\tType: %d\n", | |
2333 | fault_reg & PAGE_MASK, | |
2334 | fault_reg & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT", | |
2335 | RING_FAULT_SRCID(fault_reg), | |
2336 | RING_FAULT_FAULT_TYPE(fault_reg)); | |
e2f80391 | 2337 | I915_WRITE(RING_FAULT_REG(engine), |
828c7908 BW |
2338 | fault_reg & ~RING_FAULT_VALID); |
2339 | } | |
2340 | } | |
3b3f1650 AG |
2341 | |
2342 | /* Engine specific init may not have been done till this point. */ | |
2343 | if (dev_priv->engine[RCS]) | |
2344 | POSTING_READ(RING_FAULT_REG(dev_priv->engine[RCS])); | |
828c7908 BW |
2345 | } |
2346 | ||
91e56499 CW |
2347 | static void i915_ggtt_flush(struct drm_i915_private *dev_priv) |
2348 | { | |
2d1fe073 | 2349 | if (INTEL_INFO(dev_priv)->gen < 6) { |
91e56499 CW |
2350 | intel_gtt_chipset_flush(); |
2351 | } else { | |
2352 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
2353 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
2354 | } | |
2355 | } | |
2356 | ||
275a991c | 2357 | void i915_gem_suspend_gtt_mappings(struct drm_i915_private *dev_priv) |
828c7908 | 2358 | { |
72e96d64 | 2359 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
828c7908 BW |
2360 | |
2361 | /* Don't bother messing with faults pre GEN6 as we have little | |
2362 | * documentation supporting that it's a good idea. | |
2363 | */ | |
275a991c | 2364 | if (INTEL_GEN(dev_priv) < 6) |
828c7908 BW |
2365 | return; |
2366 | ||
dc97997a | 2367 | i915_check_and_clear_faults(dev_priv); |
828c7908 | 2368 | |
4fb84d99 | 2369 | ggtt->base.clear_range(&ggtt->base, ggtt->base.start, ggtt->base.total); |
91e56499 CW |
2370 | |
2371 | i915_ggtt_flush(dev_priv); | |
828c7908 BW |
2372 | } |
2373 | ||
03ac84f1 CW |
2374 | int i915_gem_gtt_prepare_pages(struct drm_i915_gem_object *obj, |
2375 | struct sg_table *pages) | |
7c2e6fdf | 2376 | { |
03ac84f1 CW |
2377 | if (dma_map_sg(&obj->base.dev->pdev->dev, |
2378 | pages->sgl, pages->nents, | |
2379 | PCI_DMA_BIDIRECTIONAL)) | |
2380 | return 0; | |
9da3da66 | 2381 | |
03ac84f1 | 2382 | return -ENOSPC; |
7c2e6fdf DV |
2383 | } |
2384 | ||
2c642b07 | 2385 | static void gen8_set_pte(void __iomem *addr, gen8_pte_t pte) |
94ec8f61 | 2386 | { |
94ec8f61 | 2387 | writeq(pte, addr); |
94ec8f61 BW |
2388 | } |
2389 | ||
d6473f56 CW |
2390 | static void gen8_ggtt_insert_page(struct i915_address_space *vm, |
2391 | dma_addr_t addr, | |
2392 | uint64_t offset, | |
2393 | enum i915_cache_level level, | |
2394 | u32 unused) | |
2395 | { | |
49d73912 | 2396 | struct drm_i915_private *dev_priv = vm->i915; |
d6473f56 CW |
2397 | gen8_pte_t __iomem *pte = |
2398 | (gen8_pte_t __iomem *)dev_priv->ggtt.gsm + | |
2399 | (offset >> PAGE_SHIFT); | |
d6473f56 | 2400 | |
4fb84d99 | 2401 | gen8_set_pte(pte, gen8_pte_encode(addr, level)); |
d6473f56 CW |
2402 | |
2403 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
2404 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
d6473f56 CW |
2405 | } |
2406 | ||
94ec8f61 BW |
2407 | static void gen8_ggtt_insert_entries(struct i915_address_space *vm, |
2408 | struct sg_table *st, | |
782f1495 | 2409 | uint64_t start, |
24f3a8cf | 2410 | enum i915_cache_level level, u32 unused) |
94ec8f61 | 2411 | { |
49d73912 | 2412 | struct drm_i915_private *dev_priv = vm->i915; |
ce7fda2e | 2413 | struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm); |
85d1225e DG |
2414 | struct sgt_iter sgt_iter; |
2415 | gen8_pte_t __iomem *gtt_entries; | |
2416 | gen8_pte_t gtt_entry; | |
2417 | dma_addr_t addr; | |
85d1225e | 2418 | int i = 0; |
be69459a | 2419 | |
85d1225e DG |
2420 | gtt_entries = (gen8_pte_t __iomem *)ggtt->gsm + (start >> PAGE_SHIFT); |
2421 | ||
2422 | for_each_sgt_dma(addr, sgt_iter, st) { | |
4fb84d99 | 2423 | gtt_entry = gen8_pte_encode(addr, level); |
85d1225e | 2424 | gen8_set_pte(>t_entries[i++], gtt_entry); |
94ec8f61 BW |
2425 | } |
2426 | ||
2427 | /* | |
2428 | * XXX: This serves as a posting read to make sure that the PTE has | |
2429 | * actually been updated. There is some concern that even though | |
2430 | * registers and PTEs are within the same BAR that they are potentially | |
2431 | * of NUMA access patterns. Therefore, even with the way we assume | |
2432 | * hardware should work, we must keep this posting read for paranoia. | |
2433 | */ | |
2434 | if (i != 0) | |
85d1225e | 2435 | WARN_ON(readq(>t_entries[i-1]) != gtt_entry); |
94ec8f61 | 2436 | |
94ec8f61 BW |
2437 | /* This next bit makes the above posting read even more important. We |
2438 | * want to flush the TLBs only after we're certain all the PTE updates | |
2439 | * have finished. | |
2440 | */ | |
2441 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
2442 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
94ec8f61 BW |
2443 | } |
2444 | ||
c140330b CW |
2445 | struct insert_entries { |
2446 | struct i915_address_space *vm; | |
2447 | struct sg_table *st; | |
2448 | uint64_t start; | |
2449 | enum i915_cache_level level; | |
2450 | u32 flags; | |
2451 | }; | |
2452 | ||
2453 | static int gen8_ggtt_insert_entries__cb(void *_arg) | |
2454 | { | |
2455 | struct insert_entries *arg = _arg; | |
2456 | gen8_ggtt_insert_entries(arg->vm, arg->st, | |
2457 | arg->start, arg->level, arg->flags); | |
2458 | return 0; | |
2459 | } | |
2460 | ||
2461 | static void gen8_ggtt_insert_entries__BKL(struct i915_address_space *vm, | |
2462 | struct sg_table *st, | |
2463 | uint64_t start, | |
2464 | enum i915_cache_level level, | |
2465 | u32 flags) | |
2466 | { | |
2467 | struct insert_entries arg = { vm, st, start, level, flags }; | |
2468 | stop_machine(gen8_ggtt_insert_entries__cb, &arg, NULL); | |
2469 | } | |
2470 | ||
d6473f56 CW |
2471 | static void gen6_ggtt_insert_page(struct i915_address_space *vm, |
2472 | dma_addr_t addr, | |
2473 | uint64_t offset, | |
2474 | enum i915_cache_level level, | |
2475 | u32 flags) | |
2476 | { | |
49d73912 | 2477 | struct drm_i915_private *dev_priv = vm->i915; |
d6473f56 CW |
2478 | gen6_pte_t __iomem *pte = |
2479 | (gen6_pte_t __iomem *)dev_priv->ggtt.gsm + | |
2480 | (offset >> PAGE_SHIFT); | |
d6473f56 | 2481 | |
4fb84d99 | 2482 | iowrite32(vm->pte_encode(addr, level, flags), pte); |
d6473f56 CW |
2483 | |
2484 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
2485 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
d6473f56 CW |
2486 | } |
2487 | ||
e76e9aeb BW |
2488 | /* |
2489 | * Binds an object into the global gtt with the specified cache level. The object | |
2490 | * will be accessible to the GPU via commands whose operands reference offsets | |
2491 | * within the global GTT as well as accessible by the GPU through the GMADR | |
2492 | * mapped BAR (dev_priv->mm.gtt->gtt). | |
2493 | */ | |
853ba5d2 | 2494 | static void gen6_ggtt_insert_entries(struct i915_address_space *vm, |
7faf1ab2 | 2495 | struct sg_table *st, |
782f1495 | 2496 | uint64_t start, |
24f3a8cf | 2497 | enum i915_cache_level level, u32 flags) |
e76e9aeb | 2498 | { |
49d73912 | 2499 | struct drm_i915_private *dev_priv = vm->i915; |
ce7fda2e | 2500 | struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm); |
85d1225e DG |
2501 | struct sgt_iter sgt_iter; |
2502 | gen6_pte_t __iomem *gtt_entries; | |
2503 | gen6_pte_t gtt_entry; | |
2504 | dma_addr_t addr; | |
85d1225e | 2505 | int i = 0; |
be69459a | 2506 | |
85d1225e DG |
2507 | gtt_entries = (gen6_pte_t __iomem *)ggtt->gsm + (start >> PAGE_SHIFT); |
2508 | ||
2509 | for_each_sgt_dma(addr, sgt_iter, st) { | |
4fb84d99 | 2510 | gtt_entry = vm->pte_encode(addr, level, flags); |
85d1225e | 2511 | iowrite32(gtt_entry, >t_entries[i++]); |
e76e9aeb BW |
2512 | } |
2513 | ||
e76e9aeb BW |
2514 | /* XXX: This serves as a posting read to make sure that the PTE has |
2515 | * actually been updated. There is some concern that even though | |
2516 | * registers and PTEs are within the same BAR that they are potentially | |
2517 | * of NUMA access patterns. Therefore, even with the way we assume | |
2518 | * hardware should work, we must keep this posting read for paranoia. | |
2519 | */ | |
85d1225e DG |
2520 | if (i != 0) |
2521 | WARN_ON(readl(>t_entries[i-1]) != gtt_entry); | |
0f9b91c7 BW |
2522 | |
2523 | /* This next bit makes the above posting read even more important. We | |
2524 | * want to flush the TLBs only after we're certain all the PTE updates | |
2525 | * have finished. | |
2526 | */ | |
2527 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
2528 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
e76e9aeb BW |
2529 | } |
2530 | ||
f7770bfd | 2531 | static void nop_clear_range(struct i915_address_space *vm, |
4fb84d99 | 2532 | uint64_t start, uint64_t length) |
f7770bfd CW |
2533 | { |
2534 | } | |
2535 | ||
94ec8f61 | 2536 | static void gen8_ggtt_clear_range(struct i915_address_space *vm, |
4fb84d99 | 2537 | uint64_t start, uint64_t length) |
94ec8f61 | 2538 | { |
ce7fda2e | 2539 | struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm); |
782f1495 BW |
2540 | unsigned first_entry = start >> PAGE_SHIFT; |
2541 | unsigned num_entries = length >> PAGE_SHIFT; | |
07749ef3 | 2542 | gen8_pte_t scratch_pte, __iomem *gtt_base = |
72e96d64 JL |
2543 | (gen8_pte_t __iomem *)ggtt->gsm + first_entry; |
2544 | const int max_entries = ggtt_total_entries(ggtt) - first_entry; | |
94ec8f61 BW |
2545 | int i; |
2546 | ||
2547 | if (WARN(num_entries > max_entries, | |
2548 | "First entry = %d; Num entries = %d (max=%d)\n", | |
2549 | first_entry, num_entries, max_entries)) | |
2550 | num_entries = max_entries; | |
2551 | ||
8bcdd0f7 | 2552 | scratch_pte = gen8_pte_encode(vm->scratch_page.daddr, |
4fb84d99 | 2553 | I915_CACHE_LLC); |
94ec8f61 BW |
2554 | for (i = 0; i < num_entries; i++) |
2555 | gen8_set_pte(>t_base[i], scratch_pte); | |
2556 | readl(gtt_base); | |
2557 | } | |
2558 | ||
853ba5d2 | 2559 | static void gen6_ggtt_clear_range(struct i915_address_space *vm, |
782f1495 | 2560 | uint64_t start, |
4fb84d99 | 2561 | uint64_t length) |
7faf1ab2 | 2562 | { |
ce7fda2e | 2563 | struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm); |
782f1495 BW |
2564 | unsigned first_entry = start >> PAGE_SHIFT; |
2565 | unsigned num_entries = length >> PAGE_SHIFT; | |
07749ef3 | 2566 | gen6_pte_t scratch_pte, __iomem *gtt_base = |
72e96d64 JL |
2567 | (gen6_pte_t __iomem *)ggtt->gsm + first_entry; |
2568 | const int max_entries = ggtt_total_entries(ggtt) - first_entry; | |
7faf1ab2 DV |
2569 | int i; |
2570 | ||
2571 | if (WARN(num_entries > max_entries, | |
2572 | "First entry = %d; Num entries = %d (max=%d)\n", | |
2573 | first_entry, num_entries, max_entries)) | |
2574 | num_entries = max_entries; | |
2575 | ||
8bcdd0f7 | 2576 | scratch_pte = vm->pte_encode(vm->scratch_page.daddr, |
4fb84d99 | 2577 | I915_CACHE_LLC, 0); |
828c7908 | 2578 | |
7faf1ab2 DV |
2579 | for (i = 0; i < num_entries; i++) |
2580 | iowrite32(scratch_pte, >t_base[i]); | |
2581 | readl(gtt_base); | |
2582 | } | |
2583 | ||
d6473f56 CW |
2584 | static void i915_ggtt_insert_page(struct i915_address_space *vm, |
2585 | dma_addr_t addr, | |
2586 | uint64_t offset, | |
2587 | enum i915_cache_level cache_level, | |
2588 | u32 unused) | |
2589 | { | |
d6473f56 CW |
2590 | unsigned int flags = (cache_level == I915_CACHE_NONE) ? |
2591 | AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY; | |
d6473f56 CW |
2592 | |
2593 | intel_gtt_insert_page(addr, offset >> PAGE_SHIFT, flags); | |
d6473f56 CW |
2594 | } |
2595 | ||
d369d2d9 DV |
2596 | static void i915_ggtt_insert_entries(struct i915_address_space *vm, |
2597 | struct sg_table *pages, | |
2598 | uint64_t start, | |
2599 | enum i915_cache_level cache_level, u32 unused) | |
7faf1ab2 DV |
2600 | { |
2601 | unsigned int flags = (cache_level == I915_CACHE_NONE) ? | |
2602 | AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY; | |
2603 | ||
d369d2d9 | 2604 | intel_gtt_insert_sg_entries(pages, start >> PAGE_SHIFT, flags); |
0875546c | 2605 | |
7faf1ab2 DV |
2606 | } |
2607 | ||
853ba5d2 | 2608 | static void i915_ggtt_clear_range(struct i915_address_space *vm, |
782f1495 | 2609 | uint64_t start, |
4fb84d99 | 2610 | uint64_t length) |
7faf1ab2 | 2611 | { |
2eedfc7d | 2612 | intel_gtt_clear_range(start >> PAGE_SHIFT, length >> PAGE_SHIFT); |
7faf1ab2 DV |
2613 | } |
2614 | ||
70b9f6f8 DV |
2615 | static int ggtt_bind_vma(struct i915_vma *vma, |
2616 | enum i915_cache_level cache_level, | |
2617 | u32 flags) | |
0a878716 | 2618 | { |
49d73912 | 2619 | struct drm_i915_private *i915 = vma->vm->i915; |
0a878716 DV |
2620 | struct drm_i915_gem_object *obj = vma->obj; |
2621 | u32 pte_flags = 0; | |
2622 | int ret; | |
2623 | ||
2624 | ret = i915_get_ggtt_vma_pages(vma); | |
2625 | if (ret) | |
2626 | return ret; | |
2627 | ||
2628 | /* Currently applicable only to VLV */ | |
2629 | if (obj->gt_ro) | |
2630 | pte_flags |= PTE_READ_ONLY; | |
2631 | ||
9c870d03 | 2632 | intel_runtime_pm_get(i915); |
247177dd | 2633 | vma->vm->insert_entries(vma->vm, vma->pages, vma->node.start, |
0a878716 | 2634 | cache_level, pte_flags); |
9c870d03 | 2635 | intel_runtime_pm_put(i915); |
0a878716 DV |
2636 | |
2637 | /* | |
2638 | * Without aliasing PPGTT there's no difference between | |
2639 | * GLOBAL/LOCAL_BIND, it's all the same ptes. Hence unconditionally | |
2640 | * upgrade to both bound if we bind either to avoid double-binding. | |
2641 | */ | |
3272db53 | 2642 | vma->flags |= I915_VMA_GLOBAL_BIND | I915_VMA_LOCAL_BIND; |
0a878716 DV |
2643 | |
2644 | return 0; | |
2645 | } | |
2646 | ||
2647 | static int aliasing_gtt_bind_vma(struct i915_vma *vma, | |
2648 | enum i915_cache_level cache_level, | |
2649 | u32 flags) | |
d5bd1449 | 2650 | { |
49d73912 | 2651 | struct drm_i915_private *i915 = vma->vm->i915; |
321d178e | 2652 | u32 pte_flags; |
70b9f6f8 DV |
2653 | int ret; |
2654 | ||
2655 | ret = i915_get_ggtt_vma_pages(vma); | |
2656 | if (ret) | |
2657 | return ret; | |
7faf1ab2 | 2658 | |
24f3a8cf | 2659 | /* Currently applicable only to VLV */ |
321d178e CW |
2660 | pte_flags = 0; |
2661 | if (vma->obj->gt_ro) | |
f329f5f6 | 2662 | pte_flags |= PTE_READ_ONLY; |
24f3a8cf | 2663 | |
ec7adb6e | 2664 | |
3272db53 | 2665 | if (flags & I915_VMA_GLOBAL_BIND) { |
9c870d03 | 2666 | intel_runtime_pm_get(i915); |
321d178e | 2667 | vma->vm->insert_entries(vma->vm, |
247177dd | 2668 | vma->pages, vma->node.start, |
0875546c | 2669 | cache_level, pte_flags); |
9c870d03 | 2670 | intel_runtime_pm_put(i915); |
6f65e29a | 2671 | } |
d5bd1449 | 2672 | |
3272db53 | 2673 | if (flags & I915_VMA_LOCAL_BIND) { |
9c870d03 | 2674 | struct i915_hw_ppgtt *appgtt = i915->mm.aliasing_ppgtt; |
321d178e | 2675 | appgtt->base.insert_entries(&appgtt->base, |
247177dd | 2676 | vma->pages, vma->node.start, |
f329f5f6 | 2677 | cache_level, pte_flags); |
6f65e29a | 2678 | } |
70b9f6f8 DV |
2679 | |
2680 | return 0; | |
d5bd1449 CW |
2681 | } |
2682 | ||
6f65e29a | 2683 | static void ggtt_unbind_vma(struct i915_vma *vma) |
74163907 | 2684 | { |
49d73912 | 2685 | struct drm_i915_private *i915 = vma->vm->i915; |
9c870d03 | 2686 | struct i915_hw_ppgtt *appgtt = i915->mm.aliasing_ppgtt; |
de180033 | 2687 | const u64 size = min(vma->size, vma->node.size); |
6f65e29a | 2688 | |
9c870d03 CW |
2689 | if (vma->flags & I915_VMA_GLOBAL_BIND) { |
2690 | intel_runtime_pm_get(i915); | |
782f1495 | 2691 | vma->vm->clear_range(vma->vm, |
4fb84d99 | 2692 | vma->node.start, size); |
9c870d03 CW |
2693 | intel_runtime_pm_put(i915); |
2694 | } | |
06615ee5 | 2695 | |
3272db53 | 2696 | if (vma->flags & I915_VMA_LOCAL_BIND && appgtt) |
6f65e29a | 2697 | appgtt->base.clear_range(&appgtt->base, |
4fb84d99 | 2698 | vma->node.start, size); |
74163907 DV |
2699 | } |
2700 | ||
03ac84f1 CW |
2701 | void i915_gem_gtt_finish_pages(struct drm_i915_gem_object *obj, |
2702 | struct sg_table *pages) | |
7c2e6fdf | 2703 | { |
52a05c30 DW |
2704 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
2705 | struct device *kdev = &dev_priv->drm.pdev->dev; | |
307dc25b | 2706 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
5c042287 | 2707 | |
307dc25b | 2708 | if (unlikely(ggtt->do_idle_maps)) { |
22dd3bb9 | 2709 | if (i915_gem_wait_for_idle(dev_priv, I915_WAIT_LOCKED)) { |
307dc25b CW |
2710 | DRM_ERROR("Failed to wait for idle; VT'd may hang.\n"); |
2711 | /* Wait a bit, in hopes it avoids the hang */ | |
2712 | udelay(10); | |
2713 | } | |
2714 | } | |
5c042287 | 2715 | |
03ac84f1 | 2716 | dma_unmap_sg(kdev, pages->sgl, pages->nents, PCI_DMA_BIDIRECTIONAL); |
7c2e6fdf | 2717 | } |
644ec02b | 2718 | |
42d6ab48 CW |
2719 | static void i915_gtt_color_adjust(struct drm_mm_node *node, |
2720 | unsigned long color, | |
440fd528 TR |
2721 | u64 *start, |
2722 | u64 *end) | |
42d6ab48 CW |
2723 | { |
2724 | if (node->color != color) | |
2725 | *start += 4096; | |
2726 | ||
2a1d7752 CW |
2727 | node = list_first_entry_or_null(&node->node_list, |
2728 | struct drm_mm_node, | |
2729 | node_list); | |
2730 | if (node && node->allocated && node->color != color) | |
2731 | *end -= 4096; | |
42d6ab48 | 2732 | } |
fbe5d36e | 2733 | |
f6b9d5ca | 2734 | int i915_gem_init_ggtt(struct drm_i915_private *dev_priv) |
644ec02b | 2735 | { |
e78891ca BW |
2736 | /* Let GEM Manage all of the aperture. |
2737 | * | |
2738 | * However, leave one page at the end still bound to the scratch page. | |
2739 | * There are a number of places where the hardware apparently prefetches | |
2740 | * past the end of the object, and we've seen multiple hangs with the | |
2741 | * GPU head pointer stuck in a batchbuffer bound at the last page of the | |
2742 | * aperture. One page should be enough to keep any prefetching inside | |
2743 | * of the aperture. | |
2744 | */ | |
72e96d64 | 2745 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
ed2f3452 | 2746 | unsigned long hole_start, hole_end; |
95374d75 | 2747 | struct i915_hw_ppgtt *ppgtt; |
f6b9d5ca | 2748 | struct drm_mm_node *entry; |
fa76da34 | 2749 | int ret; |
644ec02b | 2750 | |
b02d22a3 ZW |
2751 | ret = intel_vgt_balloon(dev_priv); |
2752 | if (ret) | |
2753 | return ret; | |
5dda8fa3 | 2754 | |
95374d75 CW |
2755 | /* Reserve a mappable slot for our lockless error capture */ |
2756 | ret = drm_mm_insert_node_in_range_generic(&ggtt->base.mm, | |
2757 | &ggtt->error_capture, | |
2758 | 4096, 0, -1, | |
2759 | 0, ggtt->mappable_end, | |
2760 | 0, 0); | |
2761 | if (ret) | |
2762 | return ret; | |
2763 | ||
ed2f3452 | 2764 | /* Clear any non-preallocated blocks */ |
72e96d64 | 2765 | drm_mm_for_each_hole(entry, &ggtt->base.mm, hole_start, hole_end) { |
ed2f3452 CW |
2766 | DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n", |
2767 | hole_start, hole_end); | |
72e96d64 | 2768 | ggtt->base.clear_range(&ggtt->base, hole_start, |
4fb84d99 | 2769 | hole_end - hole_start); |
ed2f3452 CW |
2770 | } |
2771 | ||
2772 | /* And finally clear the reserved guard page */ | |
f6b9d5ca | 2773 | ggtt->base.clear_range(&ggtt->base, |
4fb84d99 | 2774 | ggtt->base.total - PAGE_SIZE, PAGE_SIZE); |
6c5566a8 | 2775 | |
97d6d7ab | 2776 | if (USES_PPGTT(dev_priv) && !USES_FULL_PPGTT(dev_priv)) { |
fa76da34 | 2777 | ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL); |
95374d75 CW |
2778 | if (!ppgtt) { |
2779 | ret = -ENOMEM; | |
2780 | goto err; | |
2781 | } | |
fa76da34 | 2782 | |
2bfa996e | 2783 | ret = __hw_ppgtt_init(ppgtt, dev_priv); |
95374d75 CW |
2784 | if (ret) |
2785 | goto err_ppgtt; | |
5c5f6457 | 2786 | |
95374d75 | 2787 | if (ppgtt->base.allocate_va_range) { |
5c5f6457 DV |
2788 | ret = ppgtt->base.allocate_va_range(&ppgtt->base, 0, |
2789 | ppgtt->base.total); | |
95374d75 CW |
2790 | if (ret) |
2791 | goto err_ppgtt_cleanup; | |
4933d519 | 2792 | } |
fa76da34 | 2793 | |
5c5f6457 DV |
2794 | ppgtt->base.clear_range(&ppgtt->base, |
2795 | ppgtt->base.start, | |
4fb84d99 | 2796 | ppgtt->base.total); |
5c5f6457 | 2797 | |
fa76da34 | 2798 | dev_priv->mm.aliasing_ppgtt = ppgtt; |
72e96d64 JL |
2799 | WARN_ON(ggtt->base.bind_vma != ggtt_bind_vma); |
2800 | ggtt->base.bind_vma = aliasing_gtt_bind_vma; | |
fa76da34 DV |
2801 | } |
2802 | ||
6c5566a8 | 2803 | return 0; |
95374d75 CW |
2804 | |
2805 | err_ppgtt_cleanup: | |
2806 | ppgtt->base.cleanup(&ppgtt->base); | |
2807 | err_ppgtt: | |
2808 | kfree(ppgtt); | |
2809 | err: | |
2810 | drm_mm_remove_node(&ggtt->error_capture); | |
2811 | return ret; | |
e76e9aeb BW |
2812 | } |
2813 | ||
d85489d3 JL |
2814 | /** |
2815 | * i915_ggtt_cleanup_hw - Clean up GGTT hardware initialization | |
97d6d7ab | 2816 | * @dev_priv: i915 device |
d85489d3 | 2817 | */ |
97d6d7ab | 2818 | void i915_ggtt_cleanup_hw(struct drm_i915_private *dev_priv) |
90d0a0e8 | 2819 | { |
72e96d64 | 2820 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
90d0a0e8 | 2821 | |
70e32544 DV |
2822 | if (dev_priv->mm.aliasing_ppgtt) { |
2823 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
70e32544 | 2824 | ppgtt->base.cleanup(&ppgtt->base); |
cb7f2760 | 2825 | kfree(ppgtt); |
70e32544 DV |
2826 | } |
2827 | ||
97d6d7ab | 2828 | i915_gem_cleanup_stolen(&dev_priv->drm); |
a4eba47b | 2829 | |
95374d75 CW |
2830 | if (drm_mm_node_allocated(&ggtt->error_capture)) |
2831 | drm_mm_remove_node(&ggtt->error_capture); | |
2832 | ||
72e96d64 | 2833 | if (drm_mm_initialized(&ggtt->base.mm)) { |
b02d22a3 | 2834 | intel_vgt_deballoon(dev_priv); |
5dda8fa3 | 2835 | |
ed9724dd MA |
2836 | mutex_lock(&dev_priv->drm.struct_mutex); |
2837 | i915_address_space_fini(&ggtt->base); | |
2838 | mutex_unlock(&dev_priv->drm.struct_mutex); | |
90d0a0e8 DV |
2839 | } |
2840 | ||
72e96d64 | 2841 | ggtt->base.cleanup(&ggtt->base); |
f6b9d5ca CW |
2842 | |
2843 | arch_phys_wc_del(ggtt->mtrr); | |
f7bbe788 | 2844 | io_mapping_fini(&ggtt->mappable); |
90d0a0e8 | 2845 | } |
70e32544 | 2846 | |
2c642b07 | 2847 | static unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl) |
e76e9aeb BW |
2848 | { |
2849 | snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT; | |
2850 | snb_gmch_ctl &= SNB_GMCH_GGMS_MASK; | |
2851 | return snb_gmch_ctl << 20; | |
2852 | } | |
2853 | ||
2c642b07 | 2854 | static unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl) |
9459d252 BW |
2855 | { |
2856 | bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT; | |
2857 | bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK; | |
2858 | if (bdw_gmch_ctl) | |
2859 | bdw_gmch_ctl = 1 << bdw_gmch_ctl; | |
562d55d9 BW |
2860 | |
2861 | #ifdef CONFIG_X86_32 | |
2862 | /* Limit 32b platforms to a 2GB GGTT: 4 << 20 / pte size * PAGE_SIZE */ | |
2863 | if (bdw_gmch_ctl > 4) | |
2864 | bdw_gmch_ctl = 4; | |
2865 | #endif | |
2866 | ||
9459d252 BW |
2867 | return bdw_gmch_ctl << 20; |
2868 | } | |
2869 | ||
2c642b07 | 2870 | static unsigned int chv_get_total_gtt_size(u16 gmch_ctrl) |
d7f25f23 DL |
2871 | { |
2872 | gmch_ctrl >>= SNB_GMCH_GGMS_SHIFT; | |
2873 | gmch_ctrl &= SNB_GMCH_GGMS_MASK; | |
2874 | ||
2875 | if (gmch_ctrl) | |
2876 | return 1 << (20 + gmch_ctrl); | |
2877 | ||
2878 | return 0; | |
2879 | } | |
2880 | ||
2c642b07 | 2881 | static size_t gen6_get_stolen_size(u16 snb_gmch_ctl) |
e76e9aeb BW |
2882 | { |
2883 | snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT; | |
2884 | snb_gmch_ctl &= SNB_GMCH_GMS_MASK; | |
2885 | return snb_gmch_ctl << 25; /* 32 MB units */ | |
2886 | } | |
2887 | ||
2c642b07 | 2888 | static size_t gen8_get_stolen_size(u16 bdw_gmch_ctl) |
9459d252 BW |
2889 | { |
2890 | bdw_gmch_ctl >>= BDW_GMCH_GMS_SHIFT; | |
2891 | bdw_gmch_ctl &= BDW_GMCH_GMS_MASK; | |
2892 | return bdw_gmch_ctl << 25; /* 32 MB units */ | |
2893 | } | |
2894 | ||
d7f25f23 DL |
2895 | static size_t chv_get_stolen_size(u16 gmch_ctrl) |
2896 | { | |
2897 | gmch_ctrl >>= SNB_GMCH_GMS_SHIFT; | |
2898 | gmch_ctrl &= SNB_GMCH_GMS_MASK; | |
2899 | ||
2900 | /* | |
2901 | * 0x0 to 0x10: 32MB increments starting at 0MB | |
2902 | * 0x11 to 0x16: 4MB increments starting at 8MB | |
2903 | * 0x17 to 0x1d: 4MB increments start at 36MB | |
2904 | */ | |
2905 | if (gmch_ctrl < 0x11) | |
2906 | return gmch_ctrl << 25; | |
2907 | else if (gmch_ctrl < 0x17) | |
2908 | return (gmch_ctrl - 0x11 + 2) << 22; | |
2909 | else | |
2910 | return (gmch_ctrl - 0x17 + 9) << 22; | |
2911 | } | |
2912 | ||
66375014 DL |
2913 | static size_t gen9_get_stolen_size(u16 gen9_gmch_ctl) |
2914 | { | |
2915 | gen9_gmch_ctl >>= BDW_GMCH_GMS_SHIFT; | |
2916 | gen9_gmch_ctl &= BDW_GMCH_GMS_MASK; | |
2917 | ||
2918 | if (gen9_gmch_ctl < 0xf0) | |
2919 | return gen9_gmch_ctl << 25; /* 32 MB units */ | |
2920 | else | |
2921 | /* 4MB increments starting at 0xf0 for 4MB */ | |
2922 | return (gen9_gmch_ctl - 0xf0 + 1) << 22; | |
2923 | } | |
2924 | ||
34c998b4 | 2925 | static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size) |
63340133 | 2926 | { |
49d73912 CW |
2927 | struct drm_i915_private *dev_priv = ggtt->base.i915; |
2928 | struct pci_dev *pdev = dev_priv->drm.pdev; | |
34c998b4 | 2929 | phys_addr_t phys_addr; |
8bcdd0f7 | 2930 | int ret; |
63340133 BW |
2931 | |
2932 | /* For Modern GENs the PTEs and register space are split in the BAR */ | |
34c998b4 | 2933 | phys_addr = pci_resource_start(pdev, 0) + pci_resource_len(pdev, 0) / 2; |
63340133 | 2934 | |
2a073f89 ID |
2935 | /* |
2936 | * On BXT writes larger than 64 bit to the GTT pagetable range will be | |
2937 | * dropped. For WC mappings in general we have 64 byte burst writes | |
2938 | * when the WC buffer is flushed, so we can't use it, but have to | |
2939 | * resort to an uncached mapping. The WC issue is easily caught by the | |
2940 | * readback check when writing GTT PTE entries. | |
2941 | */ | |
275a991c | 2942 | if (IS_BROXTON(dev_priv)) |
34c998b4 | 2943 | ggtt->gsm = ioremap_nocache(phys_addr, size); |
2a073f89 | 2944 | else |
34c998b4 | 2945 | ggtt->gsm = ioremap_wc(phys_addr, size); |
72e96d64 | 2946 | if (!ggtt->gsm) { |
34c998b4 | 2947 | DRM_ERROR("Failed to map the ggtt page table\n"); |
63340133 BW |
2948 | return -ENOMEM; |
2949 | } | |
2950 | ||
275a991c | 2951 | ret = setup_scratch_page(dev_priv, &ggtt->base.scratch_page, GFP_DMA32); |
8bcdd0f7 | 2952 | if (ret) { |
63340133 BW |
2953 | DRM_ERROR("Scratch setup failed\n"); |
2954 | /* iounmap will also get called at remove, but meh */ | |
72e96d64 | 2955 | iounmap(ggtt->gsm); |
8bcdd0f7 | 2956 | return ret; |
63340133 BW |
2957 | } |
2958 | ||
4ad2af1e | 2959 | return 0; |
63340133 BW |
2960 | } |
2961 | ||
fbe5d36e BW |
2962 | /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability |
2963 | * bits. When using advanced contexts each context stores its own PAT, but | |
2964 | * writing this data shouldn't be harmful even in those cases. */ | |
ee0ce478 | 2965 | static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv) |
fbe5d36e | 2966 | { |
fbe5d36e BW |
2967 | uint64_t pat; |
2968 | ||
2969 | pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC) | /* for normal objects, no eLLC */ | |
2970 | GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something pointing to ptes? */ | |
2971 | GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC) | /* for scanout with eLLC */ | |
2972 | GEN8_PPAT(3, GEN8_PPAT_UC) | /* Uncached objects, mostly for scanout */ | |
2973 | GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) | | |
2974 | GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) | | |
2975 | GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) | | |
2976 | GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3)); | |
2977 | ||
2d1fe073 | 2978 | if (!USES_PPGTT(dev_priv)) |
d6a8b72e RV |
2979 | /* Spec: "For GGTT, there is NO pat_sel[2:0] from the entry, |
2980 | * so RTL will always use the value corresponding to | |
2981 | * pat_sel = 000". | |
2982 | * So let's disable cache for GGTT to avoid screen corruptions. | |
2983 | * MOCS still can be used though. | |
2984 | * - System agent ggtt writes (i.e. cpu gtt mmaps) already work | |
2985 | * before this patch, i.e. the same uncached + snooping access | |
2986 | * like on gen6/7 seems to be in effect. | |
2987 | * - So this just fixes blitter/render access. Again it looks | |
2988 | * like it's not just uncached access, but uncached + snooping. | |
2989 | * So we can still hold onto all our assumptions wrt cpu | |
2990 | * clflushing on LLC machines. | |
2991 | */ | |
2992 | pat = GEN8_PPAT(0, GEN8_PPAT_UC); | |
2993 | ||
fbe5d36e BW |
2994 | /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b |
2995 | * write would work. */ | |
7e435ad2 VS |
2996 | I915_WRITE(GEN8_PRIVATE_PAT_LO, pat); |
2997 | I915_WRITE(GEN8_PRIVATE_PAT_HI, pat >> 32); | |
fbe5d36e BW |
2998 | } |
2999 | ||
ee0ce478 VS |
3000 | static void chv_setup_private_ppat(struct drm_i915_private *dev_priv) |
3001 | { | |
3002 | uint64_t pat; | |
3003 | ||
3004 | /* | |
3005 | * Map WB on BDW to snooped on CHV. | |
3006 | * | |
3007 | * Only the snoop bit has meaning for CHV, the rest is | |
3008 | * ignored. | |
3009 | * | |
cf3d262e VS |
3010 | * The hardware will never snoop for certain types of accesses: |
3011 | * - CPU GTT (GMADR->GGTT->no snoop->memory) | |
3012 | * - PPGTT page tables | |
3013 | * - some other special cycles | |
3014 | * | |
3015 | * As with BDW, we also need to consider the following for GT accesses: | |
3016 | * "For GGTT, there is NO pat_sel[2:0] from the entry, | |
3017 | * so RTL will always use the value corresponding to | |
3018 | * pat_sel = 000". | |
3019 | * Which means we must set the snoop bit in PAT entry 0 | |
3020 | * in order to keep the global status page working. | |
ee0ce478 VS |
3021 | */ |
3022 | pat = GEN8_PPAT(0, CHV_PPAT_SNOOP) | | |
3023 | GEN8_PPAT(1, 0) | | |
3024 | GEN8_PPAT(2, 0) | | |
3025 | GEN8_PPAT(3, 0) | | |
3026 | GEN8_PPAT(4, CHV_PPAT_SNOOP) | | |
3027 | GEN8_PPAT(5, CHV_PPAT_SNOOP) | | |
3028 | GEN8_PPAT(6, CHV_PPAT_SNOOP) | | |
3029 | GEN8_PPAT(7, CHV_PPAT_SNOOP); | |
3030 | ||
7e435ad2 VS |
3031 | I915_WRITE(GEN8_PRIVATE_PAT_LO, pat); |
3032 | I915_WRITE(GEN8_PRIVATE_PAT_HI, pat >> 32); | |
ee0ce478 VS |
3033 | } |
3034 | ||
34c998b4 CW |
3035 | static void gen6_gmch_remove(struct i915_address_space *vm) |
3036 | { | |
3037 | struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm); | |
3038 | ||
3039 | iounmap(ggtt->gsm); | |
49d73912 | 3040 | cleanup_scratch_page(vm->i915, &vm->scratch_page); |
34c998b4 CW |
3041 | } |
3042 | ||
d507d735 | 3043 | static int gen8_gmch_probe(struct i915_ggtt *ggtt) |
63340133 | 3044 | { |
49d73912 | 3045 | struct drm_i915_private *dev_priv = ggtt->base.i915; |
97d6d7ab | 3046 | struct pci_dev *pdev = dev_priv->drm.pdev; |
34c998b4 | 3047 | unsigned int size; |
63340133 | 3048 | u16 snb_gmch_ctl; |
63340133 BW |
3049 | |
3050 | /* TODO: We're not aware of mappable constraints on gen8 yet */ | |
97d6d7ab CW |
3051 | ggtt->mappable_base = pci_resource_start(pdev, 2); |
3052 | ggtt->mappable_end = pci_resource_len(pdev, 2); | |
63340133 | 3053 | |
97d6d7ab CW |
3054 | if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(39))) |
3055 | pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(39)); | |
63340133 | 3056 | |
97d6d7ab | 3057 | pci_read_config_word(pdev, SNB_GMCH_CTRL, &snb_gmch_ctl); |
63340133 | 3058 | |
97d6d7ab | 3059 | if (INTEL_GEN(dev_priv) >= 9) { |
d507d735 | 3060 | ggtt->stolen_size = gen9_get_stolen_size(snb_gmch_ctl); |
34c998b4 | 3061 | size = gen8_get_total_gtt_size(snb_gmch_ctl); |
97d6d7ab | 3062 | } else if (IS_CHERRYVIEW(dev_priv)) { |
d507d735 | 3063 | ggtt->stolen_size = chv_get_stolen_size(snb_gmch_ctl); |
34c998b4 | 3064 | size = chv_get_total_gtt_size(snb_gmch_ctl); |
d7f25f23 | 3065 | } else { |
d507d735 | 3066 | ggtt->stolen_size = gen8_get_stolen_size(snb_gmch_ctl); |
34c998b4 | 3067 | size = gen8_get_total_gtt_size(snb_gmch_ctl); |
d7f25f23 | 3068 | } |
63340133 | 3069 | |
34c998b4 | 3070 | ggtt->base.total = (size / sizeof(gen8_pte_t)) << PAGE_SHIFT; |
63340133 | 3071 | |
97d6d7ab | 3072 | if (IS_CHERRYVIEW(dev_priv) || IS_BROXTON(dev_priv)) |
ee0ce478 VS |
3073 | chv_setup_private_ppat(dev_priv); |
3074 | else | |
3075 | bdw_setup_private_ppat(dev_priv); | |
fbe5d36e | 3076 | |
34c998b4 | 3077 | ggtt->base.cleanup = gen6_gmch_remove; |
d507d735 JL |
3078 | ggtt->base.bind_vma = ggtt_bind_vma; |
3079 | ggtt->base.unbind_vma = ggtt_unbind_vma; | |
d6473f56 | 3080 | ggtt->base.insert_page = gen8_ggtt_insert_page; |
f7770bfd | 3081 | ggtt->base.clear_range = nop_clear_range; |
48f112fe | 3082 | if (!USES_FULL_PPGTT(dev_priv) || intel_scanout_needs_vtd_wa(dev_priv)) |
f7770bfd CW |
3083 | ggtt->base.clear_range = gen8_ggtt_clear_range; |
3084 | ||
3085 | ggtt->base.insert_entries = gen8_ggtt_insert_entries; | |
3086 | if (IS_CHERRYVIEW(dev_priv)) | |
3087 | ggtt->base.insert_entries = gen8_ggtt_insert_entries__BKL; | |
3088 | ||
34c998b4 | 3089 | return ggtt_probe_common(ggtt, size); |
63340133 BW |
3090 | } |
3091 | ||
d507d735 | 3092 | static int gen6_gmch_probe(struct i915_ggtt *ggtt) |
e76e9aeb | 3093 | { |
49d73912 | 3094 | struct drm_i915_private *dev_priv = ggtt->base.i915; |
97d6d7ab | 3095 | struct pci_dev *pdev = dev_priv->drm.pdev; |
34c998b4 | 3096 | unsigned int size; |
e76e9aeb | 3097 | u16 snb_gmch_ctl; |
e76e9aeb | 3098 | |
97d6d7ab CW |
3099 | ggtt->mappable_base = pci_resource_start(pdev, 2); |
3100 | ggtt->mappable_end = pci_resource_len(pdev, 2); | |
41907ddc | 3101 | |
baa09f5f BW |
3102 | /* 64/512MB is the current min/max we actually know of, but this is just |
3103 | * a coarse sanity check. | |
e76e9aeb | 3104 | */ |
34c998b4 | 3105 | if (ggtt->mappable_end < (64<<20) || ggtt->mappable_end > (512<<20)) { |
d507d735 | 3106 | DRM_ERROR("Unknown GMADR size (%llx)\n", ggtt->mappable_end); |
baa09f5f | 3107 | return -ENXIO; |
e76e9aeb BW |
3108 | } |
3109 | ||
97d6d7ab CW |
3110 | if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(40))) |
3111 | pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(40)); | |
3112 | pci_read_config_word(pdev, SNB_GMCH_CTRL, &snb_gmch_ctl); | |
e76e9aeb | 3113 | |
d507d735 | 3114 | ggtt->stolen_size = gen6_get_stolen_size(snb_gmch_ctl); |
e76e9aeb | 3115 | |
34c998b4 CW |
3116 | size = gen6_get_total_gtt_size(snb_gmch_ctl); |
3117 | ggtt->base.total = (size / sizeof(gen6_pte_t)) << PAGE_SHIFT; | |
e76e9aeb | 3118 | |
d507d735 | 3119 | ggtt->base.clear_range = gen6_ggtt_clear_range; |
d6473f56 | 3120 | ggtt->base.insert_page = gen6_ggtt_insert_page; |
d507d735 JL |
3121 | ggtt->base.insert_entries = gen6_ggtt_insert_entries; |
3122 | ggtt->base.bind_vma = ggtt_bind_vma; | |
3123 | ggtt->base.unbind_vma = ggtt_unbind_vma; | |
34c998b4 CW |
3124 | ggtt->base.cleanup = gen6_gmch_remove; |
3125 | ||
3126 | if (HAS_EDRAM(dev_priv)) | |
3127 | ggtt->base.pte_encode = iris_pte_encode; | |
3128 | else if (IS_HASWELL(dev_priv)) | |
3129 | ggtt->base.pte_encode = hsw_pte_encode; | |
3130 | else if (IS_VALLEYVIEW(dev_priv)) | |
3131 | ggtt->base.pte_encode = byt_pte_encode; | |
3132 | else if (INTEL_GEN(dev_priv) >= 7) | |
3133 | ggtt->base.pte_encode = ivb_pte_encode; | |
3134 | else | |
3135 | ggtt->base.pte_encode = snb_pte_encode; | |
7faf1ab2 | 3136 | |
34c998b4 | 3137 | return ggtt_probe_common(ggtt, size); |
e76e9aeb BW |
3138 | } |
3139 | ||
34c998b4 | 3140 | static void i915_gmch_remove(struct i915_address_space *vm) |
e76e9aeb | 3141 | { |
34c998b4 | 3142 | intel_gmch_remove(); |
644ec02b | 3143 | } |
baa09f5f | 3144 | |
d507d735 | 3145 | static int i915_gmch_probe(struct i915_ggtt *ggtt) |
baa09f5f | 3146 | { |
49d73912 | 3147 | struct drm_i915_private *dev_priv = ggtt->base.i915; |
baa09f5f BW |
3148 | int ret; |
3149 | ||
91c8a326 | 3150 | ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->drm.pdev, NULL); |
baa09f5f BW |
3151 | if (!ret) { |
3152 | DRM_ERROR("failed to set up gmch\n"); | |
3153 | return -EIO; | |
3154 | } | |
3155 | ||
d507d735 JL |
3156 | intel_gtt_get(&ggtt->base.total, &ggtt->stolen_size, |
3157 | &ggtt->mappable_base, &ggtt->mappable_end); | |
baa09f5f | 3158 | |
97d6d7ab | 3159 | ggtt->do_idle_maps = needs_idle_maps(dev_priv); |
d6473f56 | 3160 | ggtt->base.insert_page = i915_ggtt_insert_page; |
d507d735 JL |
3161 | ggtt->base.insert_entries = i915_ggtt_insert_entries; |
3162 | ggtt->base.clear_range = i915_ggtt_clear_range; | |
3163 | ggtt->base.bind_vma = ggtt_bind_vma; | |
3164 | ggtt->base.unbind_vma = ggtt_unbind_vma; | |
34c998b4 | 3165 | ggtt->base.cleanup = i915_gmch_remove; |
baa09f5f | 3166 | |
d507d735 | 3167 | if (unlikely(ggtt->do_idle_maps)) |
c0a7f818 CW |
3168 | DRM_INFO("applying Ironlake quirks for intel_iommu\n"); |
3169 | ||
baa09f5f BW |
3170 | return 0; |
3171 | } | |
3172 | ||
d85489d3 | 3173 | /** |
0088e522 | 3174 | * i915_ggtt_probe_hw - Probe GGTT hardware location |
97d6d7ab | 3175 | * @dev_priv: i915 device |
d85489d3 | 3176 | */ |
97d6d7ab | 3177 | int i915_ggtt_probe_hw(struct drm_i915_private *dev_priv) |
baa09f5f | 3178 | { |
62106b4f | 3179 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
baa09f5f BW |
3180 | int ret; |
3181 | ||
49d73912 | 3182 | ggtt->base.i915 = dev_priv; |
c114f76a | 3183 | |
34c998b4 CW |
3184 | if (INTEL_GEN(dev_priv) <= 5) |
3185 | ret = i915_gmch_probe(ggtt); | |
3186 | else if (INTEL_GEN(dev_priv) < 8) | |
3187 | ret = gen6_gmch_probe(ggtt); | |
3188 | else | |
3189 | ret = gen8_gmch_probe(ggtt); | |
a54c0c27 | 3190 | if (ret) |
baa09f5f | 3191 | return ret; |
baa09f5f | 3192 | |
c890e2d5 CW |
3193 | if ((ggtt->base.total - 1) >> 32) { |
3194 | DRM_ERROR("We never expected a Global GTT with more than 32bits" | |
f6b9d5ca | 3195 | " of address space! Found %lldM!\n", |
c890e2d5 CW |
3196 | ggtt->base.total >> 20); |
3197 | ggtt->base.total = 1ULL << 32; | |
3198 | ggtt->mappable_end = min(ggtt->mappable_end, ggtt->base.total); | |
3199 | } | |
3200 | ||
f6b9d5ca CW |
3201 | if (ggtt->mappable_end > ggtt->base.total) { |
3202 | DRM_ERROR("mappable aperture extends past end of GGTT," | |
3203 | " aperture=%llx, total=%llx\n", | |
3204 | ggtt->mappable_end, ggtt->base.total); | |
3205 | ggtt->mappable_end = ggtt->base.total; | |
3206 | } | |
3207 | ||
baa09f5f | 3208 | /* GMADR is the PCI mmio aperture into the global GTT. */ |
c44ef60e | 3209 | DRM_INFO("Memory usable by graphics device = %lluM\n", |
62106b4f JL |
3210 | ggtt->base.total >> 20); |
3211 | DRM_DEBUG_DRIVER("GMADR size = %lldM\n", ggtt->mappable_end >> 20); | |
3212 | DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", ggtt->stolen_size >> 20); | |
5db6c735 DV |
3213 | #ifdef CONFIG_INTEL_IOMMU |
3214 | if (intel_iommu_gfx_mapped) | |
3215 | DRM_INFO("VT-d active for gfx access\n"); | |
3216 | #endif | |
baa09f5f BW |
3217 | |
3218 | return 0; | |
0088e522 CW |
3219 | } |
3220 | ||
3221 | /** | |
3222 | * i915_ggtt_init_hw - Initialize GGTT hardware | |
97d6d7ab | 3223 | * @dev_priv: i915 device |
0088e522 | 3224 | */ |
97d6d7ab | 3225 | int i915_ggtt_init_hw(struct drm_i915_private *dev_priv) |
0088e522 | 3226 | { |
0088e522 CW |
3227 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
3228 | int ret; | |
3229 | ||
f6b9d5ca CW |
3230 | INIT_LIST_HEAD(&dev_priv->vm_list); |
3231 | ||
3232 | /* Subtract the guard page before address space initialization to | |
3233 | * shrink the range used by drm_mm. | |
3234 | */ | |
80b204bc | 3235 | mutex_lock(&dev_priv->drm.struct_mutex); |
f6b9d5ca | 3236 | ggtt->base.total -= PAGE_SIZE; |
80b204bc | 3237 | i915_address_space_init(&ggtt->base, dev_priv, "[global]"); |
f6b9d5ca CW |
3238 | ggtt->base.total += PAGE_SIZE; |
3239 | if (!HAS_LLC(dev_priv)) | |
3240 | ggtt->base.mm.color_adjust = i915_gtt_color_adjust; | |
80b204bc | 3241 | mutex_unlock(&dev_priv->drm.struct_mutex); |
f6b9d5ca | 3242 | |
f7bbe788 CW |
3243 | if (!io_mapping_init_wc(&dev_priv->ggtt.mappable, |
3244 | dev_priv->ggtt.mappable_base, | |
3245 | dev_priv->ggtt.mappable_end)) { | |
f6b9d5ca CW |
3246 | ret = -EIO; |
3247 | goto out_gtt_cleanup; | |
3248 | } | |
3249 | ||
3250 | ggtt->mtrr = arch_phys_wc_add(ggtt->mappable_base, ggtt->mappable_end); | |
3251 | ||
0088e522 CW |
3252 | /* |
3253 | * Initialise stolen early so that we may reserve preallocated | |
3254 | * objects for the BIOS to KMS transition. | |
3255 | */ | |
7ace3d30 | 3256 | ret = i915_gem_init_stolen(dev_priv); |
0088e522 CW |
3257 | if (ret) |
3258 | goto out_gtt_cleanup; | |
3259 | ||
3260 | return 0; | |
a4eba47b ID |
3261 | |
3262 | out_gtt_cleanup: | |
72e96d64 | 3263 | ggtt->base.cleanup(&ggtt->base); |
a4eba47b | 3264 | return ret; |
baa09f5f | 3265 | } |
6f65e29a | 3266 | |
97d6d7ab | 3267 | int i915_ggtt_enable_hw(struct drm_i915_private *dev_priv) |
ac840ae5 | 3268 | { |
97d6d7ab | 3269 | if (INTEL_GEN(dev_priv) < 6 && !intel_enable_gtt()) |
ac840ae5 VS |
3270 | return -EIO; |
3271 | ||
3272 | return 0; | |
3273 | } | |
3274 | ||
275a991c | 3275 | void i915_gem_restore_gtt_mappings(struct drm_i915_private *dev_priv) |
fa42331b | 3276 | { |
72e96d64 | 3277 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
fbb30a5c | 3278 | struct drm_i915_gem_object *obj, *on; |
fa42331b | 3279 | |
dc97997a | 3280 | i915_check_and_clear_faults(dev_priv); |
fa42331b DV |
3281 | |
3282 | /* First fill our portion of the GTT with scratch pages */ | |
4fb84d99 | 3283 | ggtt->base.clear_range(&ggtt->base, ggtt->base.start, ggtt->base.total); |
fa42331b | 3284 | |
fbb30a5c CW |
3285 | ggtt->base.closed = true; /* skip rewriting PTE on VMA unbind */ |
3286 | ||
3287 | /* clflush objects bound into the GGTT and rebind them. */ | |
3288 | list_for_each_entry_safe(obj, on, | |
56cea323 | 3289 | &dev_priv->mm.bound_list, global_link) { |
fbb30a5c CW |
3290 | bool ggtt_bound = false; |
3291 | struct i915_vma *vma; | |
3292 | ||
1c7f4bca | 3293 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
72e96d64 | 3294 | if (vma->vm != &ggtt->base) |
2c3d9984 | 3295 | continue; |
fa42331b | 3296 | |
fbb30a5c CW |
3297 | if (!i915_vma_unbind(vma)) |
3298 | continue; | |
3299 | ||
2c3d9984 TU |
3300 | WARN_ON(i915_vma_bind(vma, obj->cache_level, |
3301 | PIN_UPDATE)); | |
fbb30a5c | 3302 | ggtt_bound = true; |
2c3d9984 TU |
3303 | } |
3304 | ||
fbb30a5c | 3305 | if (ggtt_bound) |
975f7ff4 | 3306 | WARN_ON(i915_gem_object_set_to_gtt_domain(obj, false)); |
2c3d9984 | 3307 | } |
fa42331b | 3308 | |
fbb30a5c CW |
3309 | ggtt->base.closed = false; |
3310 | ||
275a991c | 3311 | if (INTEL_GEN(dev_priv) >= 8) { |
e2d214ae | 3312 | if (IS_CHERRYVIEW(dev_priv) || IS_BROXTON(dev_priv)) |
fa42331b DV |
3313 | chv_setup_private_ppat(dev_priv); |
3314 | else | |
3315 | bdw_setup_private_ppat(dev_priv); | |
3316 | ||
3317 | return; | |
3318 | } | |
3319 | ||
275a991c | 3320 | if (USES_PPGTT(dev_priv)) { |
72e96d64 JL |
3321 | struct i915_address_space *vm; |
3322 | ||
fa42331b DV |
3323 | list_for_each_entry(vm, &dev_priv->vm_list, global_link) { |
3324 | /* TODO: Perhaps it shouldn't be gen6 specific */ | |
3325 | ||
e5716f55 | 3326 | struct i915_hw_ppgtt *ppgtt; |
fa42331b | 3327 | |
2bfa996e | 3328 | if (i915_is_ggtt(vm)) |
fa42331b | 3329 | ppgtt = dev_priv->mm.aliasing_ppgtt; |
e5716f55 JL |
3330 | else |
3331 | ppgtt = i915_vm_to_ppgtt(vm); | |
fa42331b DV |
3332 | |
3333 | gen6_write_page_range(dev_priv, &ppgtt->pd, | |
3334 | 0, ppgtt->base.total); | |
3335 | } | |
3336 | } | |
3337 | ||
3338 | i915_ggtt_flush(dev_priv); | |
3339 | } | |
3340 | ||
6f65e29a | 3341 | struct i915_vma * |
058d88c4 CW |
3342 | i915_gem_obj_to_vma(struct drm_i915_gem_object *obj, |
3343 | struct i915_address_space *vm, | |
3344 | const struct i915_ggtt_view *view) | |
ec7adb6e | 3345 | { |
db6c2b41 | 3346 | struct rb_node *rb; |
ec7adb6e | 3347 | |
db6c2b41 CW |
3348 | rb = obj->vma_tree.rb_node; |
3349 | while (rb) { | |
3350 | struct i915_vma *vma = rb_entry(rb, struct i915_vma, obj_node); | |
3351 | long cmp; | |
3352 | ||
b42fe9ca | 3353 | cmp = i915_vma_compare(vma, vm, view); |
db6c2b41 | 3354 | if (cmp == 0) |
058d88c4 | 3355 | return vma; |
ec7adb6e | 3356 | |
db6c2b41 CW |
3357 | if (cmp < 0) |
3358 | rb = rb->rb_right; | |
3359 | else | |
3360 | rb = rb->rb_left; | |
3361 | } | |
3362 | ||
058d88c4 | 3363 | return NULL; |
ec7adb6e JL |
3364 | } |
3365 | ||
3366 | struct i915_vma * | |
058d88c4 CW |
3367 | i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj, |
3368 | struct i915_address_space *vm, | |
3369 | const struct i915_ggtt_view *view) | |
6f65e29a | 3370 | { |
058d88c4 | 3371 | struct i915_vma *vma; |
ec7adb6e | 3372 | |
4c7d62c6 | 3373 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
058d88c4 | 3374 | GEM_BUG_ON(view && !i915_is_ggtt(vm)); |
de895082 | 3375 | |
058d88c4 | 3376 | vma = i915_gem_obj_to_vma(obj, vm, view); |
db6c2b41 | 3377 | if (!vma) { |
b42fe9ca | 3378 | vma = i915_vma_create(obj, vm, view); |
db6c2b41 CW |
3379 | GEM_BUG_ON(vma != i915_gem_obj_to_vma(obj, vm, view)); |
3380 | } | |
6f65e29a | 3381 | |
3272db53 | 3382 | GEM_BUG_ON(i915_vma_is_closed(vma)); |
6f65e29a BW |
3383 | return vma; |
3384 | } | |
fe14d5f4 | 3385 | |
804beb4b | 3386 | static struct scatterlist * |
2d7f3bdb | 3387 | rotate_pages(const dma_addr_t *in, unsigned int offset, |
804beb4b | 3388 | unsigned int width, unsigned int height, |
87130255 | 3389 | unsigned int stride, |
804beb4b | 3390 | struct sg_table *st, struct scatterlist *sg) |
50470bb0 TU |
3391 | { |
3392 | unsigned int column, row; | |
3393 | unsigned int src_idx; | |
50470bb0 | 3394 | |
50470bb0 | 3395 | for (column = 0; column < width; column++) { |
87130255 | 3396 | src_idx = stride * (height - 1) + column; |
50470bb0 TU |
3397 | for (row = 0; row < height; row++) { |
3398 | st->nents++; | |
3399 | /* We don't need the pages, but need to initialize | |
3400 | * the entries so the sg list can be happily traversed. | |
3401 | * The only thing we need are DMA addresses. | |
3402 | */ | |
3403 | sg_set_page(sg, NULL, PAGE_SIZE, 0); | |
804beb4b | 3404 | sg_dma_address(sg) = in[offset + src_idx]; |
50470bb0 TU |
3405 | sg_dma_len(sg) = PAGE_SIZE; |
3406 | sg = sg_next(sg); | |
87130255 | 3407 | src_idx -= stride; |
50470bb0 TU |
3408 | } |
3409 | } | |
804beb4b TU |
3410 | |
3411 | return sg; | |
50470bb0 TU |
3412 | } |
3413 | ||
3414 | static struct sg_table * | |
6687c906 | 3415 | intel_rotate_fb_obj_pages(const struct intel_rotation_info *rot_info, |
50470bb0 TU |
3416 | struct drm_i915_gem_object *obj) |
3417 | { | |
85d1225e | 3418 | const size_t n_pages = obj->base.size / PAGE_SIZE; |
6687c906 | 3419 | unsigned int size = intel_rotation_info_size(rot_info); |
85d1225e DG |
3420 | struct sgt_iter sgt_iter; |
3421 | dma_addr_t dma_addr; | |
50470bb0 TU |
3422 | unsigned long i; |
3423 | dma_addr_t *page_addr_list; | |
3424 | struct sg_table *st; | |
89e3e142 | 3425 | struct scatterlist *sg; |
1d00dad5 | 3426 | int ret = -ENOMEM; |
50470bb0 | 3427 | |
50470bb0 | 3428 | /* Allocate a temporary list of source pages for random access. */ |
85d1225e | 3429 | page_addr_list = drm_malloc_gfp(n_pages, |
f2a85e19 CW |
3430 | sizeof(dma_addr_t), |
3431 | GFP_TEMPORARY); | |
50470bb0 TU |
3432 | if (!page_addr_list) |
3433 | return ERR_PTR(ret); | |
3434 | ||
3435 | /* Allocate target SG list. */ | |
3436 | st = kmalloc(sizeof(*st), GFP_KERNEL); | |
3437 | if (!st) | |
3438 | goto err_st_alloc; | |
3439 | ||
6687c906 | 3440 | ret = sg_alloc_table(st, size, GFP_KERNEL); |
50470bb0 TU |
3441 | if (ret) |
3442 | goto err_sg_alloc; | |
3443 | ||
3444 | /* Populate source page list from the object. */ | |
3445 | i = 0; | |
a4f5ea64 | 3446 | for_each_sgt_dma(dma_addr, sgt_iter, obj->mm.pages) |
85d1225e | 3447 | page_addr_list[i++] = dma_addr; |
50470bb0 | 3448 | |
85d1225e | 3449 | GEM_BUG_ON(i != n_pages); |
11f20322 VS |
3450 | st->nents = 0; |
3451 | sg = st->sgl; | |
3452 | ||
6687c906 VS |
3453 | for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++) { |
3454 | sg = rotate_pages(page_addr_list, rot_info->plane[i].offset, | |
3455 | rot_info->plane[i].width, rot_info->plane[i].height, | |
3456 | rot_info->plane[i].stride, st, sg); | |
89e3e142 TU |
3457 | } |
3458 | ||
6687c906 VS |
3459 | DRM_DEBUG_KMS("Created rotated page mapping for object size %zu (%ux%u tiles, %u pages)\n", |
3460 | obj->base.size, rot_info->plane[0].width, rot_info->plane[0].height, size); | |
50470bb0 TU |
3461 | |
3462 | drm_free_large(page_addr_list); | |
3463 | ||
3464 | return st; | |
3465 | ||
3466 | err_sg_alloc: | |
3467 | kfree(st); | |
3468 | err_st_alloc: | |
3469 | drm_free_large(page_addr_list); | |
3470 | ||
6687c906 VS |
3471 | DRM_DEBUG_KMS("Failed to create rotated mapping for object size %zu! (%ux%u tiles, %u pages)\n", |
3472 | obj->base.size, rot_info->plane[0].width, rot_info->plane[0].height, size); | |
3473 | ||
50470bb0 TU |
3474 | return ERR_PTR(ret); |
3475 | } | |
ec7adb6e | 3476 | |
8bd7ef16 JL |
3477 | static struct sg_table * |
3478 | intel_partial_pages(const struct i915_ggtt_view *view, | |
3479 | struct drm_i915_gem_object *obj) | |
3480 | { | |
3481 | struct sg_table *st; | |
d2a84a76 CW |
3482 | struct scatterlist *sg, *iter; |
3483 | unsigned int count = view->params.partial.size; | |
3484 | unsigned int offset; | |
8bd7ef16 JL |
3485 | int ret = -ENOMEM; |
3486 | ||
3487 | st = kmalloc(sizeof(*st), GFP_KERNEL); | |
3488 | if (!st) | |
3489 | goto err_st_alloc; | |
3490 | ||
d2a84a76 | 3491 | ret = sg_alloc_table(st, count, GFP_KERNEL); |
8bd7ef16 JL |
3492 | if (ret) |
3493 | goto err_sg_alloc; | |
3494 | ||
d2a84a76 CW |
3495 | iter = i915_gem_object_get_sg(obj, |
3496 | view->params.partial.offset, | |
3497 | &offset); | |
3498 | GEM_BUG_ON(!iter); | |
3499 | ||
8bd7ef16 JL |
3500 | sg = st->sgl; |
3501 | st->nents = 0; | |
d2a84a76 CW |
3502 | do { |
3503 | unsigned int len; | |
8bd7ef16 | 3504 | |
d2a84a76 CW |
3505 | len = min(iter->length - (offset << PAGE_SHIFT), |
3506 | count << PAGE_SHIFT); | |
3507 | sg_set_page(sg, NULL, len, 0); | |
3508 | sg_dma_address(sg) = | |
3509 | sg_dma_address(iter) + (offset << PAGE_SHIFT); | |
3510 | sg_dma_len(sg) = len; | |
8bd7ef16 | 3511 | |
8bd7ef16 | 3512 | st->nents++; |
d2a84a76 CW |
3513 | count -= len >> PAGE_SHIFT; |
3514 | if (count == 0) { | |
3515 | sg_mark_end(sg); | |
3516 | return st; | |
3517 | } | |
8bd7ef16 | 3518 | |
d2a84a76 CW |
3519 | sg = __sg_next(sg); |
3520 | iter = __sg_next(iter); | |
3521 | offset = 0; | |
3522 | } while (1); | |
8bd7ef16 JL |
3523 | |
3524 | err_sg_alloc: | |
3525 | kfree(st); | |
3526 | err_st_alloc: | |
3527 | return ERR_PTR(ret); | |
3528 | } | |
3529 | ||
70b9f6f8 | 3530 | static int |
50470bb0 | 3531 | i915_get_ggtt_vma_pages(struct i915_vma *vma) |
fe14d5f4 | 3532 | { |
50470bb0 TU |
3533 | int ret = 0; |
3534 | ||
2c3a3f44 CW |
3535 | /* The vma->pages are only valid within the lifespan of the borrowed |
3536 | * obj->mm.pages. When the obj->mm.pages sg_table is regenerated, so | |
3537 | * must be the vma->pages. A simple rule is that vma->pages must only | |
3538 | * be accessed when the obj->mm.pages are pinned. | |
3539 | */ | |
3540 | GEM_BUG_ON(!i915_gem_object_has_pinned_pages(vma->obj)); | |
3541 | ||
247177dd | 3542 | if (vma->pages) |
fe14d5f4 TU |
3543 | return 0; |
3544 | ||
3545 | if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) | |
a4f5ea64 | 3546 | vma->pages = vma->obj->mm.pages; |
50470bb0 | 3547 | else if (vma->ggtt_view.type == I915_GGTT_VIEW_ROTATED) |
247177dd | 3548 | vma->pages = |
11d23e6f | 3549 | intel_rotate_fb_obj_pages(&vma->ggtt_view.params.rotated, vma->obj); |
8bd7ef16 | 3550 | else if (vma->ggtt_view.type == I915_GGTT_VIEW_PARTIAL) |
247177dd | 3551 | vma->pages = intel_partial_pages(&vma->ggtt_view, vma->obj); |
fe14d5f4 TU |
3552 | else |
3553 | WARN_ONCE(1, "GGTT view %u not implemented!\n", | |
3554 | vma->ggtt_view.type); | |
3555 | ||
247177dd | 3556 | if (!vma->pages) { |
ec7adb6e | 3557 | DRM_ERROR("Failed to get pages for GGTT view type %u!\n", |
fe14d5f4 | 3558 | vma->ggtt_view.type); |
50470bb0 | 3559 | ret = -EINVAL; |
247177dd CW |
3560 | } else if (IS_ERR(vma->pages)) { |
3561 | ret = PTR_ERR(vma->pages); | |
3562 | vma->pages = NULL; | |
50470bb0 TU |
3563 | DRM_ERROR("Failed to get pages for VMA view type %u (%d)!\n", |
3564 | vma->ggtt_view.type, ret); | |
fe14d5f4 TU |
3565 | } |
3566 | ||
50470bb0 | 3567 | return ret; |
fe14d5f4 TU |
3568 | } |
3569 |