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drm/i915/dsi: add support for gpio elements on CHV
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / i915_gem_gtt.c
CommitLineData
76aaf220
DV		 1/*
2 * Copyright © 2010 Daniel Vetter
c4ac524c 3 * Copyright © 2011-2014 Intel Corporation
76aaf220
DV		 4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 *
24 */
25
0e46ce2e 26#include <linux/seq_file.h>
5bab6f60 27#include <linux/stop_machine.h>
760285e7
DH		 28#include <drm/drmP.h>
29#include <drm/i915_drm.h>
76aaf220 30#include "i915_drv.h"
5dda8fa3 31#include "i915_vgpu.h"
76aaf220
DV		 32#include "i915_trace.h"
33#include "intel_drv.h"
34
45f8f69a
TU		 35/**
36 * DOC: Global GTT views
37 *
38 * Background and previous state
39 *
40 * Historically objects could exists (be bound) in global GTT space only as
41 * singular instances with a view representing all of the object's backing pages
42 * in a linear fashion. This view will be called a normal view.
43 *
44 * To support multiple views of the same object, where the number of mapped
45 * pages is not equal to the backing store, or where the layout of the pages
46 * is not linear, concept of a GGTT view was added.
47 *
48 * One example of an alternative view is a stereo display driven by a single
49 * image. In this case we would have a framebuffer looking like this
50 * (2x2 pages):
51 *
52 * 12
53 * 34
54 *
55 * Above would represent a normal GGTT view as normally mapped for GPU or CPU
56 * rendering. In contrast, fed to the display engine would be an alternative
57 * view which could look something like this:
58 *
59 * 1212
60 * 3434
61 *
62 * In this example both the size and layout of pages in the alternative view is
63 * different from the normal view.
64 *
65 * Implementation and usage
66 *
67 * GGTT views are implemented using VMAs and are distinguished via enum
68 * i915_ggtt_view_type and struct i915_ggtt_view.
69 *
70 * A new flavour of core GEM functions which work with GGTT bound objects were
ec7adb6e
JL		 71 * added with the _ggtt_ infix, and sometimes with _view postfix to avoid
72 * renaming in large amounts of code. They take the struct i915_ggtt_view
73 * parameter encapsulating all metadata required to implement a view.
45f8f69a
TU		 74 *
75 * As a helper for callers which are only interested in the normal view,
76 * globally const i915_ggtt_view_normal singleton instance exists. All old core
77 * GEM API functions, the ones not taking the view parameter, are operating on,
78 * or with the normal GGTT view.
79 *
80 * Code wanting to add or use a new GGTT view needs to:
81 *
82 * 1. Add a new enum with a suitable name.
83 * 2. Extend the metadata in the i915_ggtt_view structure if required.
84 * 3. Add support to i915_get_vma_pages().
85 *
86 * New views are required to build a scatter-gather table from within the
87 * i915_get_vma_pages function. This table is stored in the vma.ggtt_view and
88 * exists for the lifetime of an VMA.
89 *
90 * Core API is designed to have copy semantics which means that passed in
91 * struct i915_ggtt_view does not need to be persistent (left around after
92 * calling the core API functions).
93 *
94 */
95
70b9f6f8
DV		 96static int
97i915_get_ggtt_vma_pages(struct i915_vma *vma);
98
b5e16987
VS		 99const struct i915_ggtt_view i915_ggtt_view_normal = {
100 .type = I915_GGTT_VIEW_NORMAL,
101};
9abc4648 102const struct i915_ggtt_view i915_ggtt_view_rotated = {
b5e16987 103 .type = I915_GGTT_VIEW_ROTATED,
9abc4648 104};
fe14d5f4 105
cfa7c862
DV		 106static int sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt)
107{
1893a71b
CW		 108 bool has_aliasing_ppgtt;
109 bool has_full_ppgtt;
1f9a99e0 110 bool has_full_48bit_ppgtt;
1893a71b
CW		 111
112 has_aliasing_ppgtt = INTEL_INFO(dev)->gen >= 6;
113 has_full_ppgtt = INTEL_INFO(dev)->gen >= 7;
1f9a99e0 114 has_full_48bit_ppgtt = IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9;
1893a71b 115
71ba2d64
YZ		 116 if (intel_vgpu_active(dev))
117 has_full_ppgtt = false; /* emulation is too hard */
118
70ee45e1
DL		 119 /*
120 * We don't allow disabling PPGTT for gen9+ as it's a requirement for
121 * execlists, the sole mechanism available to submit work.
122 */
123 if (INTEL_INFO(dev)->gen < 9 &&
124 (enable_ppgtt == 0 || !has_aliasing_ppgtt))
cfa7c862
DV		 125 return 0;
126
127 if (enable_ppgtt == 1)
128 return 1;
129
1893a71b 130 if (enable_ppgtt == 2 && has_full_ppgtt)
cfa7c862
DV		 131 return 2;
132
1f9a99e0
MT		 133 if (enable_ppgtt == 3 && has_full_48bit_ppgtt)
134 return 3;
135
93a25a9e
DV		 136#ifdef CONFIG_INTEL_IOMMU
137 /* Disable ppgtt on SNB if VT-d is on. */
138 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) {
139 DRM_INFO("Disabling PPGTT because VT-d is on\n");
cfa7c862 140 return 0;
93a25a9e
DV		 141 }
142#endif
143
62942ed7 144 /* Early VLV doesn't have this */
666a4537 145 if (IS_VALLEYVIEW(dev) && dev->pdev->revision < 0xb) {
62942ed7
JB		 146 DRM_DEBUG_DRIVER("disabling PPGTT on pre-B3 step VLV\n");
147 return 0;
148 }
149
2f82bbdf 150 if (INTEL_INFO(dev)->gen >= 8 && i915.enable_execlists)
1f9a99e0 151 return has_full_48bit_ppgtt ? 3 : 2;
2f82bbdf
MT		 152 else
153 return has_aliasing_ppgtt ? 1 : 0;
93a25a9e
DV		 154}
155
70b9f6f8
DV		 156static int ppgtt_bind_vma(struct i915_vma *vma,
157 enum i915_cache_level cache_level,
158 u32 unused)
47552659
DV		 159{
160 u32 pte_flags = 0;
161
162 /* Currently applicable only to VLV */
163 if (vma->obj->gt_ro)
164 pte_flags |= PTE_READ_ONLY;
165
166 vma->vm->insert_entries(vma->vm, vma->obj->pages, vma->node.start,
167 cache_level, pte_flags);
70b9f6f8
DV		 168
169 return 0;
47552659
DV		 170}
171
172static void ppgtt_unbind_vma(struct i915_vma *vma)
173{
174 vma->vm->clear_range(vma->vm,
175 vma->node.start,
176 vma->obj->base.size,
177 true);
178}
6f65e29a 179
2c642b07
DV		 180static gen8_pte_t gen8_pte_encode(dma_addr_t addr,
181 enum i915_cache_level level,
182 bool valid)
94ec8f61 183{
07749ef3 184 gen8_pte_t pte = valid ? _PAGE_PRESENT | _PAGE_RW : 0;
94ec8f61 185 pte |= addr;
63c42e56
BW		 186
187 switch (level) {
188 case I915_CACHE_NONE:
fbe5d36e 189 pte |= PPAT_UNCACHED_INDEX;
63c42e56
BW		 190 break;
191 case I915_CACHE_WT:
192 pte |= PPAT_DISPLAY_ELLC_INDEX;
193 break;
194 default:
195 pte |= PPAT_CACHED_INDEX;
196 break;
197 }
198
94ec8f61
BW		 199 return pte;
200}
201
fe36f55d
MK		 202static gen8_pde_t gen8_pde_encode(const dma_addr_t addr,
203 const enum i915_cache_level level)
b1fe6673 204{
07749ef3 205 gen8_pde_t pde = _PAGE_PRESENT | _PAGE_RW;
b1fe6673
BW		 206 pde |= addr;
207 if (level != I915_CACHE_NONE)
208 pde |= PPAT_CACHED_PDE_INDEX;
209 else
210 pde |= PPAT_UNCACHED_INDEX;
211 return pde;
212}
213
762d9936
MT		 214#define gen8_pdpe_encode gen8_pde_encode
215#define gen8_pml4e_encode gen8_pde_encode
216
07749ef3
MT		 217static gen6_pte_t snb_pte_encode(dma_addr_t addr,
218 enum i915_cache_level level,
219 bool valid, u32 unused)
54d12527 220{
07749ef3 221 gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
54d12527 222 pte |= GEN6_PTE_ADDR_ENCODE(addr);
e7210c3c
BW		 223
224 switch (level) {
350ec881
CW		 225 case I915_CACHE_L3_LLC:
226 case I915_CACHE_LLC:
227 pte |= GEN6_PTE_CACHE_LLC;
228 break;
229 case I915_CACHE_NONE:
230 pte |= GEN6_PTE_UNCACHED;
231 break;
232 default:
5f77eeb0 233 MISSING_CASE(level);
350ec881
CW		 234 }
235
236 return pte;
237}
238
07749ef3
MT		 239static gen6_pte_t ivb_pte_encode(dma_addr_t addr,
240 enum i915_cache_level level,
241 bool valid, u32 unused)
350ec881 242{
07749ef3 243 gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
350ec881
CW		 244 pte |= GEN6_PTE_ADDR_ENCODE(addr);
245
246 switch (level) {
247 case I915_CACHE_L3_LLC:
248 pte |= GEN7_PTE_CACHE_L3_LLC;
e7210c3c
BW		 249 break;
250 case I915_CACHE_LLC:
251 pte |= GEN6_PTE_CACHE_LLC;
252 break;
253 case I915_CACHE_NONE:
9119708c 254 pte |= GEN6_PTE_UNCACHED;
e7210c3c
BW		 255 break;
256 default:
5f77eeb0 257 MISSING_CASE(level);
e7210c3c
BW		 258 }
259
54d12527
BW		 260 return pte;
261}
262
07749ef3
MT		 263static gen6_pte_t byt_pte_encode(dma_addr_t addr,
264 enum i915_cache_level level,
265 bool valid, u32 flags)
93c34e70 266{
07749ef3 267 gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
93c34e70
KG		 268 pte |= GEN6_PTE_ADDR_ENCODE(addr);
269
24f3a8cf
AG		 270 if (!(flags & PTE_READ_ONLY))
271 pte |= BYT_PTE_WRITEABLE;
93c34e70
KG		 272
273 if (level != I915_CACHE_NONE)
274 pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES;
275
276 return pte;
277}
278
07749ef3
MT		 279static gen6_pte_t hsw_pte_encode(dma_addr_t addr,
280 enum i915_cache_level level,
281 bool valid, u32 unused)
9119708c 282{
07749ef3 283 gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
0d8ff15e 284 pte |= HSW_PTE_ADDR_ENCODE(addr);
9119708c
KG		 285
286 if (level != I915_CACHE_NONE)
87a6b688 287 pte |= HSW_WB_LLC_AGE3;
9119708c
KG		 288
289 return pte;
290}
291
07749ef3
MT		 292static gen6_pte_t iris_pte_encode(dma_addr_t addr,
293 enum i915_cache_level level,
294 bool valid, u32 unused)
4d15c145 295{
07749ef3 296 gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
4d15c145
BW		 297 pte |= HSW_PTE_ADDR_ENCODE(addr);
298
651d794f
CW		 299 switch (level) {
300 case I915_CACHE_NONE:
301 break;
302 case I915_CACHE_WT:
c51e9701 303 pte |= HSW_WT_ELLC_LLC_AGE3;
651d794f
CW		 304 break;
305 default:
c51e9701 306 pte |= HSW_WB_ELLC_LLC_AGE3;
651d794f
CW		 307 break;
308 }
4d15c145
BW		 309
310 return pte;
311}
312
c114f76a
MK		 313static int __setup_page_dma(struct drm_device *dev,
314 struct i915_page_dma *p, gfp_t flags)
678d96fb
BW		 315{
316 struct device *device = &dev->pdev->dev;
317
c114f76a 318 p->page = alloc_page(flags);
44159ddb
MK		 319 if (!p->page)
320 return -ENOMEM;
678d96fb 321
44159ddb
MK		 322 p->daddr = dma_map_page(device,
323 p->page, 0, 4096, PCI_DMA_BIDIRECTIONAL);
678d96fb 324
44159ddb
MK		 325 if (dma_mapping_error(device, p->daddr)) {
326 __free_page(p->page);
327 return -EINVAL;
328 }
1266cdb1
MT		 329
330 return 0;
678d96fb
BW		 331}
332
c114f76a
MK		 333static int setup_page_dma(struct drm_device *dev, struct i915_page_dma *p)
334{
335 return __setup_page_dma(dev, p, GFP_KERNEL);
336}
337
44159ddb 338static void cleanup_page_dma(struct drm_device *dev, struct i915_page_dma *p)
06fda602 339{
44159ddb 340 if (WARN_ON(!p->page))
06fda602 341 return;
678d96fb 342
44159ddb
MK		 343 dma_unmap_page(&dev->pdev->dev, p->daddr, 4096, PCI_DMA_BIDIRECTIONAL);
344 __free_page(p->page);
345 memset(p, 0, sizeof(*p));
346}
347
d1c54acd 348static void *kmap_page_dma(struct i915_page_dma *p)
73eeea53 349{
d1c54acd
MK		 350 return kmap_atomic(p->page);
351}
73eeea53 352
d1c54acd
MK		 353/* We use the flushing unmap only with ppgtt structures:
354 * page directories, page tables and scratch pages.
355 */
356static void kunmap_page_dma(struct drm_device *dev, void *vaddr)
357{
73eeea53
MK		 358 /* There are only few exceptions for gen >=6. chv and bxt.
359 * And we are not sure about the latter so play safe for now.
360 */
361 if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev))
362 drm_clflush_virt_range(vaddr, PAGE_SIZE);
363
364 kunmap_atomic(vaddr);
365}
366
567047be 367#define kmap_px(px) kmap_page_dma(px_base(px))
d1c54acd
MK		 368#define kunmap_px(ppgtt, vaddr) kunmap_page_dma((ppgtt)->base.dev, (vaddr))
369
567047be
MK		 370#define setup_px(dev, px) setup_page_dma((dev), px_base(px))
371#define cleanup_px(dev, px) cleanup_page_dma((dev), px_base(px))
372#define fill_px(dev, px, v) fill_page_dma((dev), px_base(px), (v))
373#define fill32_px(dev, px, v) fill_page_dma_32((dev), px_base(px), (v))
374
d1c54acd
MK		 375static void fill_page_dma(struct drm_device *dev, struct i915_page_dma *p,
376 const uint64_t val)
377{
378 int i;
379 uint64_t * const vaddr = kmap_page_dma(p);
380
381 for (i = 0; i < 512; i++)
382 vaddr[i] = val;
383
384 kunmap_page_dma(dev, vaddr);
385}
386
73eeea53
MK		 387static void fill_page_dma_32(struct drm_device *dev, struct i915_page_dma *p,
388 const uint32_t val32)
389{
390 uint64_t v = val32;
391
392 v = v << 32 | val32;
393
394 fill_page_dma(dev, p, v);
395}
396
4ad2af1e
MK		 397static struct i915_page_scratch *alloc_scratch_page(struct drm_device *dev)
398{
399 struct i915_page_scratch *sp;
400 int ret;
401
402 sp = kzalloc(sizeof(*sp), GFP_KERNEL);
403 if (sp == NULL)
404 return ERR_PTR(-ENOMEM);
405
406 ret = __setup_page_dma(dev, px_base(sp), GFP_DMA32 | __GFP_ZERO);
407 if (ret) {
408 kfree(sp);
409 return ERR_PTR(ret);
410 }
411
412 set_pages_uc(px_page(sp), 1);
413
414 return sp;
415}
416
417static void free_scratch_page(struct drm_device *dev,
418 struct i915_page_scratch *sp)
419{
420 set_pages_wb(px_page(sp), 1);
421
422 cleanup_px(dev, sp);
423 kfree(sp);
424}
425
8a1ebd74 426static struct i915_page_table *alloc_pt(struct drm_device *dev)
06fda602 427{
ec565b3c 428 struct i915_page_table *pt;
678d96fb
BW		 429 const size_t count = INTEL_INFO(dev)->gen >= 8 ?
430 GEN8_PTES : GEN6_PTES;
431 int ret = -ENOMEM;
06fda602
BW		 432
433 pt = kzalloc(sizeof(*pt), GFP_KERNEL);
434 if (!pt)
435 return ERR_PTR(-ENOMEM);
436
678d96fb
BW		 437 pt->used_ptes = kcalloc(BITS_TO_LONGS(count), sizeof(*pt->used_ptes),
438 GFP_KERNEL);
439
440 if (!pt->used_ptes)
441 goto fail_bitmap;
442
567047be 443 ret = setup_px(dev, pt);
678d96fb 444 if (ret)
44159ddb 445 goto fail_page_m;
06fda602
BW		 446
447 return pt;
678d96fb 448
44159ddb 449fail_page_m:
678d96fb
BW		 450 kfree(pt->used_ptes);
451fail_bitmap:
452 kfree(pt);
453
454 return ERR_PTR(ret);
06fda602
BW		 455}
456
2e906bea 457static void free_pt(struct drm_device *dev, struct i915_page_table *pt)
06fda602 458{
2e906bea
MK		 459 cleanup_px(dev, pt);
460 kfree(pt->used_ptes);
461 kfree(pt);
462}
463
464static void gen8_initialize_pt(struct i915_address_space *vm,
465 struct i915_page_table *pt)
466{
467 gen8_pte_t scratch_pte;
468
469 scratch_pte = gen8_pte_encode(px_dma(vm->scratch_page),
470 I915_CACHE_LLC, true);
471
472 fill_px(vm->dev, pt, scratch_pte);
473}
474
475static void gen6_initialize_pt(struct i915_address_space *vm,
476 struct i915_page_table *pt)
477{
478 gen6_pte_t scratch_pte;
479
480 WARN_ON(px_dma(vm->scratch_page) == 0);
481
482 scratch_pte = vm->pte_encode(px_dma(vm->scratch_page),
483 I915_CACHE_LLC, true, 0);
484
485 fill32_px(vm->dev, pt, scratch_pte);
06fda602
BW		 486}
487
8a1ebd74 488static struct i915_page_directory *alloc_pd(struct drm_device *dev)
06fda602 489{
ec565b3c 490 struct i915_page_directory *pd;
33c8819f 491 int ret = -ENOMEM;
06fda602
BW		 492
493 pd = kzalloc(sizeof(*pd), GFP_KERNEL);
494 if (!pd)
495 return ERR_PTR(-ENOMEM);
496
33c8819f
MT		 497 pd->used_pdes = kcalloc(BITS_TO_LONGS(I915_PDES),
498 sizeof(*pd->used_pdes), GFP_KERNEL);
499 if (!pd->used_pdes)
a08e111a 500 goto fail_bitmap;
33c8819f 501
567047be 502 ret = setup_px(dev, pd);
33c8819f 503 if (ret)
a08e111a 504 goto fail_page_m;
e5815a2e 505
06fda602 506 return pd;
33c8819f 507
a08e111a 508fail_page_m:
33c8819f 509 kfree(pd->used_pdes);
a08e111a 510fail_bitmap:
33c8819f
MT		 511 kfree(pd);
512
513 return ERR_PTR(ret);
06fda602
BW		 514}
515
2e906bea
MK		 516static void free_pd(struct drm_device *dev, struct i915_page_directory *pd)
517{
518 if (px_page(pd)) {
519 cleanup_px(dev, pd);
520 kfree(pd->used_pdes);
521 kfree(pd);
522 }
523}
524
525static void gen8_initialize_pd(struct i915_address_space *vm,
526 struct i915_page_directory *pd)
527{
528 gen8_pde_t scratch_pde;
529
530 scratch_pde = gen8_pde_encode(px_dma(vm->scratch_pt), I915_CACHE_LLC);
531
532 fill_px(vm->dev, pd, scratch_pde);
533}
534
6ac18502
MT		 535static int __pdp_init(struct drm_device *dev,
536 struct i915_page_directory_pointer *pdp)
537{
538 size_t pdpes = I915_PDPES_PER_PDP(dev);
539
540 pdp->used_pdpes = kcalloc(BITS_TO_LONGS(pdpes),
541 sizeof(unsigned long),
542 GFP_KERNEL);
543 if (!pdp->used_pdpes)
544 return -ENOMEM;
545
546 pdp->page_directory = kcalloc(pdpes, sizeof(*pdp->page_directory),
547 GFP_KERNEL);
548 if (!pdp->page_directory) {
549 kfree(pdp->used_pdpes);
550 /* the PDP might be the statically allocated top level. Keep it
551 * as clean as possible */
552 pdp->used_pdpes = NULL;
553 return -ENOMEM;
554 }
555
556 return 0;
557}
558
559static void __pdp_fini(struct i915_page_directory_pointer *pdp)
560{
561 kfree(pdp->used_pdpes);
562 kfree(pdp->page_directory);
563 pdp->page_directory = NULL;
564}
565
762d9936
MT		 566static struct
567i915_page_directory_pointer *alloc_pdp(struct drm_device *dev)
568{
569 struct i915_page_directory_pointer *pdp;
570 int ret = -ENOMEM;
571
572 WARN_ON(!USES_FULL_48BIT_PPGTT(dev));
573
574 pdp = kzalloc(sizeof(*pdp), GFP_KERNEL);
575 if (!pdp)
576 return ERR_PTR(-ENOMEM);
577
578 ret = __pdp_init(dev, pdp);
579 if (ret)
580 goto fail_bitmap;
581
582 ret = setup_px(dev, pdp);
583 if (ret)
584 goto fail_page_m;
585
586 return pdp;
587
588fail_page_m:
589 __pdp_fini(pdp);
590fail_bitmap:
591 kfree(pdp);
592
593 return ERR_PTR(ret);
594}
595
6ac18502
MT		 596static void free_pdp(struct drm_device *dev,
597 struct i915_page_directory_pointer *pdp)
598{
599 __pdp_fini(pdp);
762d9936
MT		 600 if (USES_FULL_48BIT_PPGTT(dev)) {
601 cleanup_px(dev, pdp);
602 kfree(pdp);
603 }
604}
605
69ab76fd
MT		 606static void gen8_initialize_pdp(struct i915_address_space *vm,
607 struct i915_page_directory_pointer *pdp)
608{
609 gen8_ppgtt_pdpe_t scratch_pdpe;
610
611 scratch_pdpe = gen8_pdpe_encode(px_dma(vm->scratch_pd), I915_CACHE_LLC);
612
613 fill_px(vm->dev, pdp, scratch_pdpe);
614}
615
616static void gen8_initialize_pml4(struct i915_address_space *vm,
617 struct i915_pml4 *pml4)
618{
619 gen8_ppgtt_pml4e_t scratch_pml4e;
620
621 scratch_pml4e = gen8_pml4e_encode(px_dma(vm->scratch_pdp),
622 I915_CACHE_LLC);
623
624 fill_px(vm->dev, pml4, scratch_pml4e);
625}
626
762d9936
MT		 627static void
628gen8_setup_page_directory(struct i915_hw_ppgtt *ppgtt,
629 struct i915_page_directory_pointer *pdp,
630 struct i915_page_directory *pd,
631 int index)
632{
633 gen8_ppgtt_pdpe_t *page_directorypo;
634
635 if (!USES_FULL_48BIT_PPGTT(ppgtt->base.dev))
636 return;
637
638 page_directorypo = kmap_px(pdp);
639 page_directorypo[index] = gen8_pdpe_encode(px_dma(pd), I915_CACHE_LLC);
640 kunmap_px(ppgtt, page_directorypo);
641}
642
643static void
644gen8_setup_page_directory_pointer(struct i915_hw_ppgtt *ppgtt,
645 struct i915_pml4 *pml4,
646 struct i915_page_directory_pointer *pdp,
647 int index)
648{
649 gen8_ppgtt_pml4e_t *pagemap = kmap_px(pml4);
650
651 WARN_ON(!USES_FULL_48BIT_PPGTT(ppgtt->base.dev));
652 pagemap[index] = gen8_pml4e_encode(px_dma(pdp), I915_CACHE_LLC);
653 kunmap_px(ppgtt, pagemap);
6ac18502
MT		 654}
655
94e409c1 656/* Broadwell Page Directory Pointer Descriptors */
e85b26dc 657static int gen8_write_pdp(struct drm_i915_gem_request *req,
7cb6d7ac
MT		 658 unsigned entry,
659 dma_addr_t addr)
94e409c1 660{
4a570db5 661 struct intel_engine_cs *engine = req->engine;
94e409c1
BW		 662 int ret;
663
664 BUG_ON(entry >= 4);
665
5fb9de1a 666 ret = intel_ring_begin(req, 6);
94e409c1
BW		 667 if (ret)
668 return ret;
669
e2f80391
TU		 670 intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(1));
671 intel_ring_emit_reg(engine, GEN8_RING_PDP_UDW(engine, entry));
672 intel_ring_emit(engine, upper_32_bits(addr));
673 intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(1));
674 intel_ring_emit_reg(engine, GEN8_RING_PDP_LDW(engine, entry));
675 intel_ring_emit(engine, lower_32_bits(addr));
676 intel_ring_advance(engine);
94e409c1
BW		 677
678 return 0;
679}
680
2dba3239
MT		 681static int gen8_legacy_mm_switch(struct i915_hw_ppgtt *ppgtt,
682 struct drm_i915_gem_request *req)
94e409c1 683{
eeb9488e 684 int i, ret;
94e409c1 685
7cb6d7ac 686 for (i = GEN8_LEGACY_PDPES - 1; i >= 0; i--) {
d852c7bf
MK		 687 const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i);
688
e85b26dc 689 ret = gen8_write_pdp(req, i, pd_daddr);
eeb9488e
BW		 690 if (ret)
691 return ret;
94e409c1 692 }
d595bd4b 693
eeb9488e 694 return 0;
94e409c1
BW		 695}
696
2dba3239
MT		 697static int gen8_48b_mm_switch(struct i915_hw_ppgtt *ppgtt,
698 struct drm_i915_gem_request *req)
699{
700 return gen8_write_pdp(req, 0, px_dma(&ppgtt->pml4));
701}
702
f9b5b782
MT		 703static void gen8_ppgtt_clear_pte_range(struct i915_address_space *vm,
704 struct i915_page_directory_pointer *pdp,
705 uint64_t start,
706 uint64_t length,
707 gen8_pte_t scratch_pte)
459108b8 708{
e5716f55 709 struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
f9b5b782 710 gen8_pte_t *pt_vaddr;
de5ba8eb
MT		 711 unsigned pdpe = gen8_pdpe_index(start);
712 unsigned pde = gen8_pde_index(start);
713 unsigned pte = gen8_pte_index(start);
782f1495 714 unsigned num_entries = length >> PAGE_SHIFT;
459108b8
BW		 715 unsigned last_pte, i;
716
f9b5b782
MT		 717 if (WARN_ON(!pdp))
718 return;
459108b8
BW		 719
720 while (num_entries) {
ec565b3c
MT		 721 struct i915_page_directory *pd;
722 struct i915_page_table *pt;
06fda602 723
d4ec9da0 724 if (WARN_ON(!pdp->page_directory[pdpe]))
00245266 725 break;
06fda602 726
d4ec9da0 727 pd = pdp->page_directory[pdpe];
06fda602
BW		 728
729 if (WARN_ON(!pd->page_table[pde]))
00245266 730 break;
06fda602
BW		 731
732 pt = pd->page_table[pde];
733
567047be 734 if (WARN_ON(!px_page(pt)))
00245266 735 break;
06fda602 736
7ad47cf2 737 last_pte = pte + num_entries;
07749ef3
MT		 738 if (last_pte > GEN8_PTES)
739 last_pte = GEN8_PTES;
459108b8 740
d1c54acd 741 pt_vaddr = kmap_px(pt);
459108b8 742
7ad47cf2 743 for (i = pte; i < last_pte; i++) {
459108b8 744 pt_vaddr[i] = scratch_pte;
7ad47cf2
BW		 745 num_entries--;
746 }
459108b8 747
44a71024 748 kunmap_px(ppgtt, pt_vaddr);
459108b8 749
7ad47cf2 750 pte = 0;
07749ef3 751 if (++pde == I915_PDES) {
de5ba8eb
MT		 752 if (++pdpe == I915_PDPES_PER_PDP(vm->dev))
753 break;
7ad47cf2
BW		 754 pde = 0;
755 }
459108b8
BW		 756 }
757}
758
f9b5b782
MT		 759static void gen8_ppgtt_clear_range(struct i915_address_space *vm,
760 uint64_t start,
761 uint64_t length,
762 bool use_scratch)
9df15b49 763{
e5716f55 764 struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
f9b5b782
MT		 765 gen8_pte_t scratch_pte = gen8_pte_encode(px_dma(vm->scratch_page),
766 I915_CACHE_LLC, use_scratch);
767
de5ba8eb
MT		 768 if (!USES_FULL_48BIT_PPGTT(vm->dev)) {
769 gen8_ppgtt_clear_pte_range(vm, &ppgtt->pdp, start, length,
770 scratch_pte);
771 } else {
e8ebd8e2 772 uint64_t pml4e;
de5ba8eb
MT		 773 struct i915_page_directory_pointer *pdp;
774
e8ebd8e2 775 gen8_for_each_pml4e(pdp, &ppgtt->pml4, start, length, pml4e) {
de5ba8eb
MT		 776 gen8_ppgtt_clear_pte_range(vm, pdp, start, length,
777 scratch_pte);
778 }
779 }
f9b5b782
MT		 780}
781
782static void
783gen8_ppgtt_insert_pte_entries(struct i915_address_space *vm,
784 struct i915_page_directory_pointer *pdp,
3387d433 785 struct sg_page_iter *sg_iter,
f9b5b782
MT		 786 uint64_t start,
787 enum i915_cache_level cache_level)
788{
e5716f55 789 struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
07749ef3 790 gen8_pte_t *pt_vaddr;
de5ba8eb
MT		 791 unsigned pdpe = gen8_pdpe_index(start);
792 unsigned pde = gen8_pde_index(start);
793 unsigned pte = gen8_pte_index(start);
9df15b49 794
6f1cc993 795 pt_vaddr = NULL;
7ad47cf2 796
3387d433 797 while (__sg_page_iter_next(sg_iter)) {
d7b3de91 798 if (pt_vaddr == NULL) {
d4ec9da0 799 struct i915_page_directory *pd = pdp->page_directory[pdpe];
ec565b3c 800 struct i915_page_table *pt = pd->page_table[pde];
d1c54acd 801 pt_vaddr = kmap_px(pt);
d7b3de91 802 }
9df15b49 803
7ad47cf2 804 pt_vaddr[pte] =
3387d433 805 gen8_pte_encode(sg_page_iter_dma_address(sg_iter),
6f1cc993 806 cache_level, true);
07749ef3 807 if (++pte == GEN8_PTES) {
d1c54acd 808 kunmap_px(ppgtt, pt_vaddr);
6f1cc993 809 pt_vaddr = NULL;
07749ef3 810 if (++pde == I915_PDES) {
de5ba8eb
MT		 811 if (++pdpe == I915_PDPES_PER_PDP(vm->dev))
812 break;
7ad47cf2
BW		 813 pde = 0;
814 }
815 pte = 0;
9df15b49
BW		 816 }
817 }
d1c54acd
MK		 818
819 if (pt_vaddr)
820 kunmap_px(ppgtt, pt_vaddr);
9df15b49
BW		 821}
822
f9b5b782
MT		 823static void gen8_ppgtt_insert_entries(struct i915_address_space *vm,
824 struct sg_table *pages,
825 uint64_t start,
826 enum i915_cache_level cache_level,
827 u32 unused)
828{
e5716f55 829 struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
3387d433 830 struct sg_page_iter sg_iter;
f9b5b782 831
3387d433 832 __sg_page_iter_start(&sg_iter, pages->sgl, sg_nents(pages->sgl), 0);
de5ba8eb
MT		 833
834 if (!USES_FULL_48BIT_PPGTT(vm->dev)) {
835 gen8_ppgtt_insert_pte_entries(vm, &ppgtt->pdp, &sg_iter, start,
836 cache_level);
837 } else {
838 struct i915_page_directory_pointer *pdp;
e8ebd8e2 839 uint64_t pml4e;
de5ba8eb
MT		 840 uint64_t length = (uint64_t)pages->orig_nents << PAGE_SHIFT;
841
e8ebd8e2 842 gen8_for_each_pml4e(pdp, &ppgtt->pml4, start, length, pml4e) {
de5ba8eb
MT		 843 gen8_ppgtt_insert_pte_entries(vm, pdp, &sg_iter,
844 start, cache_level);
845 }
846 }
f9b5b782
MT		 847}
848
f37c0505
MT		 849static void gen8_free_page_tables(struct drm_device *dev,
850 struct i915_page_directory *pd)
7ad47cf2
BW		 851{
852 int i;
853
567047be 854 if (!px_page(pd))
7ad47cf2
BW		 855 return;
856
33c8819f 857 for_each_set_bit(i, pd->used_pdes, I915_PDES) {
06fda602
BW		 858 if (WARN_ON(!pd->page_table[i]))
859 continue;
7ad47cf2 860
a08e111a 861 free_pt(dev, pd->page_table[i]);
06fda602
BW		 862 pd->page_table[i] = NULL;
863 }
d7b3de91
BW		 864}
865
8776f02b
MK		 866static int gen8_init_scratch(struct i915_address_space *vm)
867{
868 struct drm_device *dev = vm->dev;
869
870 vm->scratch_page = alloc_scratch_page(dev);
871 if (IS_ERR(vm->scratch_page))
872 return PTR_ERR(vm->scratch_page);
873
874 vm->scratch_pt = alloc_pt(dev);
875 if (IS_ERR(vm->scratch_pt)) {
876 free_scratch_page(dev, vm->scratch_page);
877 return PTR_ERR(vm->scratch_pt);
878 }
879
880 vm->scratch_pd = alloc_pd(dev);
881 if (IS_ERR(vm->scratch_pd)) {
882 free_pt(dev, vm->scratch_pt);
883 free_scratch_page(dev, vm->scratch_page);
884 return PTR_ERR(vm->scratch_pd);
885 }
886
69ab76fd
MT		 887 if (USES_FULL_48BIT_PPGTT(dev)) {
888 vm->scratch_pdp = alloc_pdp(dev);
889 if (IS_ERR(vm->scratch_pdp)) {
890 free_pd(dev, vm->scratch_pd);
891 free_pt(dev, vm->scratch_pt);
892 free_scratch_page(dev, vm->scratch_page);
893 return PTR_ERR(vm->scratch_pdp);
894 }
895 }
896
8776f02b
MK		 897 gen8_initialize_pt(vm, vm->scratch_pt);
898 gen8_initialize_pd(vm, vm->scratch_pd);
69ab76fd
MT		 899 if (USES_FULL_48BIT_PPGTT(dev))
900 gen8_initialize_pdp(vm, vm->scratch_pdp);
8776f02b
MK		 901
902 return 0;
903}
904
650da34c
ZL		 905static int gen8_ppgtt_notify_vgt(struct i915_hw_ppgtt *ppgtt, bool create)
906{
907 enum vgt_g2v_type msg;
df28564d 908 struct drm_i915_private *dev_priv = to_i915(ppgtt->base.dev);
650da34c
ZL		 909 int i;
910
df28564d 911 if (USES_FULL_48BIT_PPGTT(dev_priv)) {
650da34c
ZL		 912 u64 daddr = px_dma(&ppgtt->pml4);
913
ab75bb5d
VS		 914 I915_WRITE(vgtif_reg(pdp[0].lo), lower_32_bits(daddr));
915 I915_WRITE(vgtif_reg(pdp[0].hi), upper_32_bits(daddr));
650da34c
ZL		 916
917 msg = (create ? VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE :
918 VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY);
919 } else {
920 for (i = 0; i < GEN8_LEGACY_PDPES; i++) {
921 u64 daddr = i915_page_dir_dma_addr(ppgtt, i);
922
ab75bb5d
VS		 923 I915_WRITE(vgtif_reg(pdp[i].lo), lower_32_bits(daddr));
924 I915_WRITE(vgtif_reg(pdp[i].hi), upper_32_bits(daddr));
650da34c
ZL		 925 }
926
927 msg = (create ? VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE :
928 VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY);
929 }
930
931 I915_WRITE(vgtif_reg(g2v_notify), msg);
932
933 return 0;
934}
935
8776f02b
MK		 936static void gen8_free_scratch(struct i915_address_space *vm)
937{
938 struct drm_device *dev = vm->dev;
939
69ab76fd
MT		 940 if (USES_FULL_48BIT_PPGTT(dev))
941 free_pdp(dev, vm->scratch_pdp);
8776f02b
MK		 942 free_pd(dev, vm->scratch_pd);
943 free_pt(dev, vm->scratch_pt);
944 free_scratch_page(dev, vm->scratch_page);
945}
946
762d9936
MT		 947static void gen8_ppgtt_cleanup_3lvl(struct drm_device *dev,
948 struct i915_page_directory_pointer *pdp)
b45a6715
BW		 949{
950 int i;
951
d4ec9da0
MT		 952 for_each_set_bit(i, pdp->used_pdpes, I915_PDPES_PER_PDP(dev)) {
953 if (WARN_ON(!pdp->page_directory[i]))
06fda602
BW		 954 continue;
955
d4ec9da0
MT		 956 gen8_free_page_tables(dev, pdp->page_directory[i]);
957 free_pd(dev, pdp->page_directory[i]);
7ad47cf2 958 }
69876bed 959
d4ec9da0 960 free_pdp(dev, pdp);
762d9936
MT		 961}
962
963static void gen8_ppgtt_cleanup_4lvl(struct i915_hw_ppgtt *ppgtt)
964{
965 int i;
966
967 for_each_set_bit(i, ppgtt->pml4.used_pml4es, GEN8_PML4ES_PER_PML4) {
968 if (WARN_ON(!ppgtt->pml4.pdps[i]))
969 continue;
970
971 gen8_ppgtt_cleanup_3lvl(ppgtt->base.dev, ppgtt->pml4.pdps[i]);
972 }
973
974 cleanup_px(ppgtt->base.dev, &ppgtt->pml4);
975}
976
977static void gen8_ppgtt_cleanup(struct i915_address_space *vm)
978{
e5716f55 979 struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
762d9936 980
650da34c
ZL		 981 if (intel_vgpu_active(vm->dev))
982 gen8_ppgtt_notify_vgt(ppgtt, false);
983
762d9936
MT		 984 if (!USES_FULL_48BIT_PPGTT(ppgtt->base.dev))
985 gen8_ppgtt_cleanup_3lvl(ppgtt->base.dev, &ppgtt->pdp);
986 else
987 gen8_ppgtt_cleanup_4lvl(ppgtt);
d4ec9da0 988
8776f02b 989 gen8_free_scratch(vm);
b45a6715
BW		 990}
991
d7b2633d
MT		 992/**
993 * gen8_ppgtt_alloc_pagetabs() - Allocate page tables for VA range.
d4ec9da0
MT		 994 * @vm: Master vm structure.
995 * @pd: Page directory for this address range.
d7b2633d 996 * @start: Starting virtual address to begin allocations.
d4ec9da0 997 * @length: Size of the allocations.
d7b2633d
MT		 998 * @new_pts: Bitmap set by function with new allocations. Likely used by the
999 * caller to free on error.
1000 *
1001 * Allocate the required number of page tables. Extremely similar to
1002 * gen8_ppgtt_alloc_page_directories(). The main difference is here we are limited by
1003 * the page directory boundary (instead of the page directory pointer). That
1004 * boundary is 1GB virtual. Therefore, unlike gen8_ppgtt_alloc_page_directories(), it is
1005 * possible, and likely that the caller will need to use multiple calls of this
1006 * function to achieve the appropriate allocation.
1007 *
1008 * Return: 0 if success; negative error code otherwise.
1009 */
d4ec9da0 1010static int gen8_ppgtt_alloc_pagetabs(struct i915_address_space *vm,
e5815a2e 1011 struct i915_page_directory *pd,
5441f0cb 1012 uint64_t start,
d7b2633d
MT		 1013 uint64_t length,
1014 unsigned long *new_pts)
bf2b4ed2 1015{
d4ec9da0 1016 struct drm_device *dev = vm->dev;
d7b2633d 1017 struct i915_page_table *pt;
5441f0cb 1018 uint32_t pde;
bf2b4ed2 1019
e8ebd8e2 1020 gen8_for_each_pde(pt, pd, start, length, pde) {
d7b2633d 1021 /* Don't reallocate page tables */
6ac18502 1022 if (test_bit(pde, pd->used_pdes)) {
d7b2633d 1023 /* Scratch is never allocated this way */
d4ec9da0 1024 WARN_ON(pt == vm->scratch_pt);
d7b2633d
MT		 1025 continue;
1026 }
1027
8a1ebd74 1028 pt = alloc_pt(dev);
d7b2633d 1029 if (IS_ERR(pt))
5441f0cb
MT		 1030 goto unwind_out;
1031
d4ec9da0 1032 gen8_initialize_pt(vm, pt);
d7b2633d 1033 pd->page_table[pde] = pt;
966082c9 1034 __set_bit(pde, new_pts);
4c06ec8d 1035 trace_i915_page_table_entry_alloc(vm, pde, start, GEN8_PDE_SHIFT);
7ad47cf2
BW		 1036 }
1037
bf2b4ed2 1038 return 0;
7ad47cf2
BW		 1039
1040unwind_out:
d7b2633d 1041 for_each_set_bit(pde, new_pts, I915_PDES)
a08e111a 1042 free_pt(dev, pd->page_table[pde]);
7ad47cf2 1043
d7b3de91 1044 return -ENOMEM;
bf2b4ed2
BW		 1045}
1046
d7b2633d
MT		 1047/**
1048 * gen8_ppgtt_alloc_page_directories() - Allocate page directories for VA range.
d4ec9da0 1049 * @vm: Master vm structure.
d7b2633d
MT		 1050 * @pdp: Page directory pointer for this address range.
1051 * @start: Starting virtual address to begin allocations.
d4ec9da0
MT		 1052 * @length: Size of the allocations.
1053 * @new_pds: Bitmap set by function with new allocations. Likely used by the
d7b2633d
MT		 1054 * caller to free on error.
1055 *
1056 * Allocate the required number of page directories starting at the pde index of
1057 * @start, and ending at the pde index @start + @length. This function will skip
1058 * over already allocated page directories within the range, and only allocate
1059 * new ones, setting the appropriate pointer within the pdp as well as the
1060 * correct position in the bitmap @new_pds.
1061 *
1062 * The function will only allocate the pages within the range for a give page
1063 * directory pointer. In other words, if @start + @length straddles a virtually
1064 * addressed PDP boundary (512GB for 4k pages), there will be more allocations
1065 * required by the caller, This is not currently possible, and the BUG in the
1066 * code will prevent it.
1067 *
1068 * Return: 0 if success; negative error code otherwise.
1069 */
d4ec9da0
MT		 1070static int
1071gen8_ppgtt_alloc_page_directories(struct i915_address_space *vm,
1072 struct i915_page_directory_pointer *pdp,
1073 uint64_t start,
1074 uint64_t length,
1075 unsigned long *new_pds)
bf2b4ed2 1076{
d4ec9da0 1077 struct drm_device *dev = vm->dev;
d7b2633d 1078 struct i915_page_directory *pd;
69876bed 1079 uint32_t pdpe;
6ac18502 1080 uint32_t pdpes = I915_PDPES_PER_PDP(dev);
69876bed 1081
6ac18502 1082 WARN_ON(!bitmap_empty(new_pds, pdpes));
d7b2633d 1083
e8ebd8e2 1084 gen8_for_each_pdpe(pd, pdp, start, length, pdpe) {
6ac18502 1085 if (test_bit(pdpe, pdp->used_pdpes))
d7b2633d 1086 continue;
33c8819f 1087
8a1ebd74 1088 pd = alloc_pd(dev);
d7b2633d 1089 if (IS_ERR(pd))
d7b3de91 1090 goto unwind_out;
69876bed 1091
d4ec9da0 1092 gen8_initialize_pd(vm, pd);
d7b2633d 1093 pdp->page_directory[pdpe] = pd;
966082c9 1094 __set_bit(pdpe, new_pds);
4c06ec8d 1095 trace_i915_page_directory_entry_alloc(vm, pdpe, start, GEN8_PDPE_SHIFT);
d7b3de91
BW		 1096 }
1097
bf2b4ed2 1098 return 0;
d7b3de91
BW		 1099
1100unwind_out:
6ac18502 1101 for_each_set_bit(pdpe, new_pds, pdpes)
a08e111a 1102 free_pd(dev, pdp->page_directory[pdpe]);
d7b3de91
BW		 1103
1104 return -ENOMEM;
bf2b4ed2
BW		 1105}
1106
762d9936
MT		 1107/**
1108 * gen8_ppgtt_alloc_page_dirpointers() - Allocate pdps for VA range.
1109 * @vm: Master vm structure.
1110 * @pml4: Page map level 4 for this address range.
1111 * @start: Starting virtual address to begin allocations.
1112 * @length: Size of the allocations.
1113 * @new_pdps: Bitmap set by function with new allocations. Likely used by the
1114 * caller to free on error.
1115 *
1116 * Allocate the required number of page directory pointers. Extremely similar to
1117 * gen8_ppgtt_alloc_page_directories() and gen8_ppgtt_alloc_pagetabs().
1118 * The main difference is here we are limited by the pml4 boundary (instead of
1119 * the page directory pointer).
1120 *
1121 * Return: 0 if success; negative error code otherwise.
1122 */
1123static int
1124gen8_ppgtt_alloc_page_dirpointers(struct i915_address_space *vm,
1125 struct i915_pml4 *pml4,
1126 uint64_t start,
1127 uint64_t length,
1128 unsigned long *new_pdps)
1129{
1130 struct drm_device *dev = vm->dev;
1131 struct i915_page_directory_pointer *pdp;
762d9936
MT		 1132 uint32_t pml4e;
1133
1134 WARN_ON(!bitmap_empty(new_pdps, GEN8_PML4ES_PER_PML4));
1135
e8ebd8e2 1136 gen8_for_each_pml4e(pdp, pml4, start, length, pml4e) {
762d9936
MT		 1137 if (!test_bit(pml4e, pml4->used_pml4es)) {
1138 pdp = alloc_pdp(dev);
1139 if (IS_ERR(pdp))
1140 goto unwind_out;
1141
69ab76fd 1142 gen8_initialize_pdp(vm, pdp);
762d9936
MT		 1143 pml4->pdps[pml4e] = pdp;
1144 __set_bit(pml4e, new_pdps);
1145 trace_i915_page_directory_pointer_entry_alloc(vm,
1146 pml4e,
1147 start,
1148 GEN8_PML4E_SHIFT);
1149 }
1150 }
1151
1152 return 0;
1153
1154unwind_out:
1155 for_each_set_bit(pml4e, new_pdps, GEN8_PML4ES_PER_PML4)
1156 free_pdp(dev, pml4->pdps[pml4e]);
1157
1158 return -ENOMEM;
1159}
1160
d7b2633d 1161static void
3a41a05d 1162free_gen8_temp_bitmaps(unsigned long *new_pds, unsigned long *new_pts)
d7b2633d 1163{
d7b2633d
MT		 1164 kfree(new_pts);
1165 kfree(new_pds);
1166}
1167
1168/* Fills in the page directory bitmap, and the array of page tables bitmap. Both
1169 * of these are based on the number of PDPEs in the system.
1170 */
1171static
1172int __must_check alloc_gen8_temp_bitmaps(unsigned long **new_pds,
3a41a05d 1173 unsigned long **new_pts,
6ac18502 1174 uint32_t pdpes)
d7b2633d 1175{
d7b2633d 1176 unsigned long *pds;
3a41a05d 1177 unsigned long *pts;
d7b2633d 1178
3a41a05d 1179 pds = kcalloc(BITS_TO_LONGS(pdpes), sizeof(unsigned long), GFP_TEMPORARY);
d7b2633d
MT		 1180 if (!pds)
1181 return -ENOMEM;
1182
3a41a05d
MW		 1183 pts = kcalloc(pdpes, BITS_TO_LONGS(I915_PDES) * sizeof(unsigned long),
1184 GFP_TEMPORARY);
1185 if (!pts)
1186 goto err_out;
d7b2633d
MT		 1187
1188 *new_pds = pds;
1189 *new_pts = pts;
1190
1191 return 0;
1192
1193err_out:
3a41a05d 1194 free_gen8_temp_bitmaps(pds, pts);
d7b2633d
MT		 1195 return -ENOMEM;
1196}
1197
5b7e4c9c
MK		 1198/* PDE TLBs are a pain to invalidate on GEN8+. When we modify
1199 * the page table structures, we mark them dirty so that
1200 * context switching/execlist queuing code takes extra steps
1201 * to ensure that tlbs are flushed.
1202 */
1203static void mark_tlbs_dirty(struct i915_hw_ppgtt *ppgtt)
1204{
1205 ppgtt->pd_dirty_rings = INTEL_INFO(ppgtt->base.dev)->ring_mask;
1206}
1207
762d9936
MT		 1208static int gen8_alloc_va_range_3lvl(struct i915_address_space *vm,
1209 struct i915_page_directory_pointer *pdp,
1210 uint64_t start,
1211 uint64_t length)
bf2b4ed2 1212{
e5716f55 1213 struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
3a41a05d 1214 unsigned long *new_page_dirs, *new_page_tables;
d4ec9da0 1215 struct drm_device *dev = vm->dev;
5441f0cb 1216 struct i915_page_directory *pd;
33c8819f
MT		 1217 const uint64_t orig_start = start;
1218 const uint64_t orig_length = length;
5441f0cb 1219 uint32_t pdpe;
d4ec9da0 1220 uint32_t pdpes = I915_PDPES_PER_PDP(dev);
bf2b4ed2
BW		 1221 int ret;
1222
d7b2633d
MT		 1223 /* Wrap is never okay since we can only represent 48b, and we don't
1224 * actually use the other side of the canonical address space.
1225 */
1226 if (WARN_ON(start + length < start))
a05d80ee
MK		 1227 return -ENODEV;
1228
d4ec9da0 1229 if (WARN_ON(start + length > vm->total))
a05d80ee 1230 return -ENODEV;
d7b2633d 1231
6ac18502 1232 ret = alloc_gen8_temp_bitmaps(&new_page_dirs, &new_page_tables, pdpes);
bf2b4ed2
BW		 1233 if (ret)
1234 return ret;
1235
d7b2633d 1236 /* Do the allocations first so we can easily bail out */
d4ec9da0
MT		 1237 ret = gen8_ppgtt_alloc_page_directories(vm, pdp, start, length,
1238 new_page_dirs);
d7b2633d 1239 if (ret) {
3a41a05d 1240 free_gen8_temp_bitmaps(new_page_dirs, new_page_tables);
d7b2633d
MT		 1241 return ret;
1242 }
1243
1244 /* For every page directory referenced, allocate page tables */
e8ebd8e2 1245 gen8_for_each_pdpe(pd, pdp, start, length, pdpe) {
d4ec9da0 1246 ret = gen8_ppgtt_alloc_pagetabs(vm, pd, start, length,
3a41a05d 1247 new_page_tables + pdpe * BITS_TO_LONGS(I915_PDES));
5441f0cb
MT		 1248 if (ret)
1249 goto err_out;
5441f0cb
MT		 1250 }
1251
33c8819f
MT		 1252 start = orig_start;
1253 length = orig_length;
1254
d7b2633d
MT		 1255 /* Allocations have completed successfully, so set the bitmaps, and do
1256 * the mappings. */
e8ebd8e2 1257 gen8_for_each_pdpe(pd, pdp, start, length, pdpe) {
d1c54acd 1258 gen8_pde_t *const page_directory = kmap_px(pd);
33c8819f 1259 struct i915_page_table *pt;
09120d4e 1260 uint64_t pd_len = length;
33c8819f
MT		 1261 uint64_t pd_start = start;
1262 uint32_t pde;
1263
d7b2633d
MT		 1264 /* Every pd should be allocated, we just did that above. */
1265 WARN_ON(!pd);
1266
e8ebd8e2 1267 gen8_for_each_pde(pt, pd, pd_start, pd_len, pde) {
d7b2633d
MT		 1268 /* Same reasoning as pd */
1269 WARN_ON(!pt);
1270 WARN_ON(!pd_len);
1271 WARN_ON(!gen8_pte_count(pd_start, pd_len));
1272
1273 /* Set our used ptes within the page table */
1274 bitmap_set(pt->used_ptes,
1275 gen8_pte_index(pd_start),
1276 gen8_pte_count(pd_start, pd_len));
1277
1278 /* Our pde is now pointing to the pagetable, pt */
966082c9 1279 __set_bit(pde, pd->used_pdes);
d7b2633d
MT		 1280
1281 /* Map the PDE to the page table */
fe36f55d
MK		 1282 page_directory[pde] = gen8_pde_encode(px_dma(pt),
1283 I915_CACHE_LLC);
4c06ec8d
MT		 1284 trace_i915_page_table_entry_map(&ppgtt->base, pde, pt,
1285 gen8_pte_index(start),
1286 gen8_pte_count(start, length),
1287 GEN8_PTES);
d7b2633d
MT		 1288
1289 /* NB: We haven't yet mapped ptes to pages. At this
1290 * point we're still relying on insert_entries() */
33c8819f 1291 }
d7b2633d 1292
d1c54acd 1293 kunmap_px(ppgtt, page_directory);
d4ec9da0 1294 __set_bit(pdpe, pdp->used_pdpes);
762d9936 1295 gen8_setup_page_directory(ppgtt, pdp, pd, pdpe);
33c8819f
MT		 1296 }
1297
3a41a05d 1298 free_gen8_temp_bitmaps(new_page_dirs, new_page_tables);
5b7e4c9c 1299 mark_tlbs_dirty(ppgtt);
d7b3de91 1300 return 0;
bf2b4ed2 1301
d7b3de91 1302err_out:
d7b2633d 1303 while (pdpe--) {
e8ebd8e2
DG		 1304 unsigned long temp;
1305
3a41a05d
MW		 1306 for_each_set_bit(temp, new_page_tables + pdpe *
1307 BITS_TO_LONGS(I915_PDES), I915_PDES)
d4ec9da0 1308 free_pt(dev, pdp->page_directory[pdpe]->page_table[temp]);
d7b2633d
MT		 1309 }
1310
6ac18502 1311 for_each_set_bit(pdpe, new_page_dirs, pdpes)
d4ec9da0 1312 free_pd(dev, pdp->page_directory[pdpe]);
d7b2633d 1313
3a41a05d 1314 free_gen8_temp_bitmaps(new_page_dirs, new_page_tables);
5b7e4c9c 1315 mark_tlbs_dirty(ppgtt);
bf2b4ed2
BW		 1316 return ret;
1317}
1318
762d9936
MT		 1319static int gen8_alloc_va_range_4lvl(struct i915_address_space *vm,
1320 struct i915_pml4 *pml4,
1321 uint64_t start,
1322 uint64_t length)
1323{
1324 DECLARE_BITMAP(new_pdps, GEN8_PML4ES_PER_PML4);
e5716f55 1325 struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
762d9936 1326 struct i915_page_directory_pointer *pdp;
e8ebd8e2 1327 uint64_t pml4e;
762d9936
MT		 1328 int ret = 0;
1329
1330 /* Do the pml4 allocations first, so we don't need to track the newly
1331 * allocated tables below the pdp */
1332 bitmap_zero(new_pdps, GEN8_PML4ES_PER_PML4);
1333
1334 /* The pagedirectory and pagetable allocations are done in the shared 3
1335 * and 4 level code. Just allocate the pdps.
1336 */
1337 ret = gen8_ppgtt_alloc_page_dirpointers(vm, pml4, start, length,
1338 new_pdps);
1339 if (ret)
1340 return ret;
1341
1342 WARN(bitmap_weight(new_pdps, GEN8_PML4ES_PER_PML4) > 2,
1343 "The allocation has spanned more than 512GB. "
1344 "It is highly likely this is incorrect.");
1345
e8ebd8e2 1346 gen8_for_each_pml4e(pdp, pml4, start, length, pml4e) {
762d9936
MT		 1347 WARN_ON(!pdp);
1348
1349 ret = gen8_alloc_va_range_3lvl(vm, pdp, start, length);
1350 if (ret)
1351 goto err_out;
1352
1353 gen8_setup_page_directory_pointer(ppgtt, pml4, pdp, pml4e);
1354 }
1355
1356 bitmap_or(pml4->used_pml4es, new_pdps, pml4->used_pml4es,
1357 GEN8_PML4ES_PER_PML4);
1358
1359 return 0;
1360
1361err_out:
1362 for_each_set_bit(pml4e, new_pdps, GEN8_PML4ES_PER_PML4)
1363 gen8_ppgtt_cleanup_3lvl(vm->dev, pml4->pdps[pml4e]);
1364
1365 return ret;
1366}
1367
1368static int gen8_alloc_va_range(struct i915_address_space *vm,
1369 uint64_t start, uint64_t length)
1370{
e5716f55 1371 struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
762d9936
MT		 1372
1373 if (USES_FULL_48BIT_PPGTT(vm->dev))
1374 return gen8_alloc_va_range_4lvl(vm, &ppgtt->pml4, start, length);
1375 else
1376 return gen8_alloc_va_range_3lvl(vm, &ppgtt->pdp, start, length);
1377}
1378
ea91e401
MT		 1379static void gen8_dump_pdp(struct i915_page_directory_pointer *pdp,
1380 uint64_t start, uint64_t length,
1381 gen8_pte_t scratch_pte,
1382 struct seq_file *m)
1383{
1384 struct i915_page_directory *pd;
ea91e401
MT		 1385 uint32_t pdpe;
1386
e8ebd8e2 1387 gen8_for_each_pdpe(pd, pdp, start, length, pdpe) {
ea91e401
MT		 1388 struct i915_page_table *pt;
1389 uint64_t pd_len = length;
1390 uint64_t pd_start = start;
1391 uint32_t pde;
1392
1393 if (!test_bit(pdpe, pdp->used_pdpes))
1394 continue;
1395
1396 seq_printf(m, "\tPDPE #%d\n", pdpe);
e8ebd8e2 1397 gen8_for_each_pde(pt, pd, pd_start, pd_len, pde) {
ea91e401
MT		 1398 uint32_t pte;
1399 gen8_pte_t *pt_vaddr;
1400
1401 if (!test_bit(pde, pd->used_pdes))
1402 continue;
1403
1404 pt_vaddr = kmap_px(pt);
1405 for (pte = 0; pte < GEN8_PTES; pte += 4) {
1406 uint64_t va =
1407 (pdpe << GEN8_PDPE_SHIFT) |
1408 (pde << GEN8_PDE_SHIFT) |
1409 (pte << GEN8_PTE_SHIFT);
1410 int i;
1411 bool found = false;
1412
1413 for (i = 0; i < 4; i++)
1414 if (pt_vaddr[pte + i] != scratch_pte)
1415 found = true;
1416 if (!found)
1417 continue;
1418
1419 seq_printf(m, "\t\t0x%llx [%03d,%03d,%04d]: =", va, pdpe, pde, pte);
1420 for (i = 0; i < 4; i++) {
1421 if (pt_vaddr[pte + i] != scratch_pte)
1422 seq_printf(m, " %llx", pt_vaddr[pte + i]);
1423 else
1424 seq_puts(m, " SCRATCH ");
1425 }
1426 seq_puts(m, "\n");
1427 }
1428 /* don't use kunmap_px, it could trigger
1429 * an unnecessary flush.
1430 */
1431 kunmap_atomic(pt_vaddr);
1432 }
1433 }
1434}
1435
1436static void gen8_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m)
1437{
1438 struct i915_address_space *vm = &ppgtt->base;
1439 uint64_t start = ppgtt->base.start;
1440 uint64_t length = ppgtt->base.total;
1441 gen8_pte_t scratch_pte = gen8_pte_encode(px_dma(vm->scratch_page),
1442 I915_CACHE_LLC, true);
1443
1444 if (!USES_FULL_48BIT_PPGTT(vm->dev)) {
1445 gen8_dump_pdp(&ppgtt->pdp, start, length, scratch_pte, m);
1446 } else {
e8ebd8e2 1447 uint64_t pml4e;
ea91e401
MT		 1448 struct i915_pml4 *pml4 = &ppgtt->pml4;
1449 struct i915_page_directory_pointer *pdp;
1450
e8ebd8e2 1451 gen8_for_each_pml4e(pdp, pml4, start, length, pml4e) {
ea91e401
MT		 1452 if (!test_bit(pml4e, pml4->used_pml4es))
1453 continue;
1454
1455 seq_printf(m, " PML4E #%llu\n", pml4e);
1456 gen8_dump_pdp(pdp, start, length, scratch_pte, m);
1457 }
1458 }
1459}
1460
331f38e7
ZL		 1461static int gen8_preallocate_top_level_pdps(struct i915_hw_ppgtt *ppgtt)
1462{
3a41a05d 1463 unsigned long *new_page_dirs, *new_page_tables;
331f38e7
ZL		 1464 uint32_t pdpes = I915_PDPES_PER_PDP(dev);
1465 int ret;
1466
1467 /* We allocate temp bitmap for page tables for no gain
1468 * but as this is for init only, lets keep the things simple
1469 */
1470 ret = alloc_gen8_temp_bitmaps(&new_page_dirs, &new_page_tables, pdpes);
1471 if (ret)
1472 return ret;
1473
1474 /* Allocate for all pdps regardless of how the ppgtt
1475 * was defined.
1476 */
1477 ret = gen8_ppgtt_alloc_page_directories(&ppgtt->base, &ppgtt->pdp,
1478 0, 1ULL << 32,
1479 new_page_dirs);
1480 if (!ret)
1481 *ppgtt->pdp.used_pdpes = *new_page_dirs;
1482
3a41a05d 1483 free_gen8_temp_bitmaps(new_page_dirs, new_page_tables);
331f38e7
ZL		 1484
1485 return ret;
1486}
1487
eb0b44ad 1488/*
f3a964b9
BW		 1489 * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers
1490 * with a net effect resembling a 2-level page table in normal x86 terms. Each
1491 * PDP represents 1GB of memory 4 * 512 * 512 * 4096 = 4GB legacy 32b address
1492 * space.
37aca44a 1493 *
f3a964b9 1494 */
5c5f6457 1495static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
37aca44a 1496{
8776f02b 1497 int ret;
7cb6d7ac 1498
8776f02b
MK		 1499 ret = gen8_init_scratch(&ppgtt->base);
1500 if (ret)
1501 return ret;
69876bed 1502
d7b2633d 1503 ppgtt->base.start = 0;
d7b2633d 1504 ppgtt->base.cleanup = gen8_ppgtt_cleanup;
5c5f6457 1505 ppgtt->base.allocate_va_range = gen8_alloc_va_range;
d7b2633d 1506 ppgtt->base.insert_entries = gen8_ppgtt_insert_entries;
c7e16f22 1507 ppgtt->base.clear_range = gen8_ppgtt_clear_range;
777dc5bb
DV		 1508 ppgtt->base.unbind_vma = ppgtt_unbind_vma;
1509 ppgtt->base.bind_vma = ppgtt_bind_vma;
ea91e401 1510 ppgtt->debug_dump = gen8_dump_ppgtt;
d7b2633d 1511
762d9936
MT		 1512 if (USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) {
1513 ret = setup_px(ppgtt->base.dev, &ppgtt->pml4);
1514 if (ret)
1515 goto free_scratch;
6ac18502 1516
69ab76fd
MT		 1517 gen8_initialize_pml4(&ppgtt->base, &ppgtt->pml4);
1518
762d9936 1519 ppgtt->base.total = 1ULL << 48;
2dba3239 1520 ppgtt->switch_mm = gen8_48b_mm_switch;
762d9936 1521 } else {
25f50337 1522 ret = __pdp_init(ppgtt->base.dev, &ppgtt->pdp);
81ba8aef
MT		 1523 if (ret)
1524 goto free_scratch;
1525
1526 ppgtt->base.total = 1ULL << 32;
2dba3239 1527 ppgtt->switch_mm = gen8_legacy_mm_switch;
762d9936
MT		 1528 trace_i915_page_directory_pointer_entry_alloc(&ppgtt->base,
1529 0, 0,
1530 GEN8_PML4E_SHIFT);
331f38e7
ZL		 1531
1532 if (intel_vgpu_active(ppgtt->base.dev)) {
1533 ret = gen8_preallocate_top_level_pdps(ppgtt);
1534 if (ret)
1535 goto free_scratch;
1536 }
81ba8aef 1537 }
6ac18502 1538
650da34c
ZL		 1539 if (intel_vgpu_active(ppgtt->base.dev))
1540 gen8_ppgtt_notify_vgt(ppgtt, true);
1541
d7b2633d 1542 return 0;
6ac18502
MT		 1543
1544free_scratch:
1545 gen8_free_scratch(&ppgtt->base);
1546 return ret;
d7b2633d
MT		 1547}
1548
87d60b63
BW		 1549static void gen6_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m)
1550{
87d60b63 1551 struct i915_address_space *vm = &ppgtt->base;
09942c65 1552 struct i915_page_table *unused;
07749ef3 1553 gen6_pte_t scratch_pte;
87d60b63 1554 uint32_t pd_entry;
09942c65
MT		 1555 uint32_t pte, pde, temp;
1556 uint32_t start = ppgtt->base.start, length = ppgtt->base.total;
87d60b63 1557
79ab9370
MK		 1558 scratch_pte = vm->pte_encode(px_dma(vm->scratch_page),
1559 I915_CACHE_LLC, true, 0);
87d60b63 1560
09942c65 1561 gen6_for_each_pde(unused, &ppgtt->pd, start, length, temp, pde) {
87d60b63 1562 u32 expected;
07749ef3 1563 gen6_pte_t *pt_vaddr;
567047be 1564 const dma_addr_t pt_addr = px_dma(ppgtt->pd.page_table[pde]);
09942c65 1565 pd_entry = readl(ppgtt->pd_addr + pde);
87d60b63
BW		 1566 expected = (GEN6_PDE_ADDR_ENCODE(pt_addr) | GEN6_PDE_VALID);
1567
1568 if (pd_entry != expected)
1569 seq_printf(m, "\tPDE #%d mismatch: Actual PDE: %x Expected PDE: %x\n",
1570 pde,
1571 pd_entry,
1572 expected);
1573 seq_printf(m, "\tPDE: %x\n", pd_entry);
1574
d1c54acd
MK		 1575 pt_vaddr = kmap_px(ppgtt->pd.page_table[pde]);
1576
07749ef3 1577 for (pte = 0; pte < GEN6_PTES; pte+=4) {
87d60b63 1578 unsigned long va =
07749ef3 1579 (pde * PAGE_SIZE * GEN6_PTES) +
87d60b63
BW		 1580 (pte * PAGE_SIZE);
1581 int i;
1582 bool found = false;
1583 for (i = 0; i < 4; i++)
1584 if (pt_vaddr[pte + i] != scratch_pte)
1585 found = true;
1586 if (!found)
1587 continue;
1588
1589 seq_printf(m, "\t\t0x%lx [%03d,%04d]: =", va, pde, pte);
1590 for (i = 0; i < 4; i++) {
1591 if (pt_vaddr[pte + i] != scratch_pte)
1592 seq_printf(m, " %08x", pt_vaddr[pte + i]);
1593 else
1594 seq_puts(m, " SCRATCH ");
1595 }
1596 seq_puts(m, "\n");
1597 }
d1c54acd 1598 kunmap_px(ppgtt, pt_vaddr);
87d60b63
BW		 1599 }
1600}
1601
678d96fb 1602/* Write pde (index) from the page directory @pd to the page table @pt */
ec565b3c
MT		 1603static void gen6_write_pde(struct i915_page_directory *pd,
1604 const int pde, struct i915_page_table *pt)
6197349b 1605{
678d96fb
BW		 1606 /* Caller needs to make sure the write completes if necessary */
1607 struct i915_hw_ppgtt *ppgtt =
1608 container_of(pd, struct i915_hw_ppgtt, pd);
1609 u32 pd_entry;
6197349b 1610
567047be 1611 pd_entry = GEN6_PDE_ADDR_ENCODE(px_dma(pt));
678d96fb 1612 pd_entry |= GEN6_PDE_VALID;
6197349b 1613
678d96fb
BW		 1614 writel(pd_entry, ppgtt->pd_addr + pde);
1615}
6197349b 1616
678d96fb
BW		 1617/* Write all the page tables found in the ppgtt structure to incrementing page
1618 * directories. */
1619static void gen6_write_page_range(struct drm_i915_private *dev_priv,
ec565b3c 1620 struct i915_page_directory *pd,
678d96fb
BW		 1621 uint32_t start, uint32_t length)
1622{
72e96d64 1623 struct i915_ggtt *ggtt = &dev_priv->ggtt;
ec565b3c 1624 struct i915_page_table *pt;
678d96fb
BW		 1625 uint32_t pde, temp;
1626
1627 gen6_for_each_pde(pt, pd, start, length, temp, pde)
1628 gen6_write_pde(pd, pde, pt);
1629
1630 /* Make sure write is complete before other code can use this page
1631 * table. Also require for WC mapped PTEs */
72e96d64 1632 readl(ggtt->gsm);
3e302542
BW		 1633}
1634
b4a74e3a 1635static uint32_t get_pd_offset(struct i915_hw_ppgtt *ppgtt)
3e302542 1636{
44159ddb 1637 BUG_ON(ppgtt->pd.base.ggtt_offset & 0x3f);
b4a74e3a 1638
44159ddb 1639 return (ppgtt->pd.base.ggtt_offset / 64) << 16;
b4a74e3a
BW		 1640}
1641
90252e5c 1642static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt,
e85b26dc 1643 struct drm_i915_gem_request *req)
90252e5c 1644{
4a570db5 1645 struct intel_engine_cs *engine = req->engine;
90252e5c
BW		 1646 int ret;
1647
90252e5c 1648 /* NB: TLBs must be flushed and invalidated before a switch */
e2f80391 1649 ret = engine->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
90252e5c
BW		 1650 if (ret)
1651 return ret;
1652
5fb9de1a 1653 ret = intel_ring_begin(req, 6);
90252e5c
BW		 1654 if (ret)
1655 return ret;
1656
e2f80391
TU		 1657 intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(2));
1658 intel_ring_emit_reg(engine, RING_PP_DIR_DCLV(engine));
1659 intel_ring_emit(engine, PP_DIR_DCLV_2G);
1660 intel_ring_emit_reg(engine, RING_PP_DIR_BASE(engine));
1661 intel_ring_emit(engine, get_pd_offset(ppgtt));
1662 intel_ring_emit(engine, MI_NOOP);
1663 intel_ring_advance(engine);
90252e5c
BW		 1664
1665 return 0;
1666}
1667
71ba2d64 1668static int vgpu_mm_switch(struct i915_hw_ppgtt *ppgtt,
e85b26dc 1669 struct drm_i915_gem_request *req)
71ba2d64 1670{
4a570db5 1671 struct intel_engine_cs *engine = req->engine;
71ba2d64
YZ		 1672 struct drm_i915_private *dev_priv = to_i915(ppgtt->base.dev);
1673
e2f80391
TU		 1674 I915_WRITE(RING_PP_DIR_DCLV(engine), PP_DIR_DCLV_2G);
1675 I915_WRITE(RING_PP_DIR_BASE(engine), get_pd_offset(ppgtt));
71ba2d64
YZ		 1676 return 0;
1677}
1678
48a10389 1679static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt,
e85b26dc 1680 struct drm_i915_gem_request *req)
48a10389 1681{
4a570db5 1682 struct intel_engine_cs *engine = req->engine;
48a10389
BW		 1683 int ret;
1684
48a10389 1685 /* NB: TLBs must be flushed and invalidated before a switch */
e2f80391 1686 ret = engine->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
48a10389
BW		 1687 if (ret)
1688 return ret;
1689
5fb9de1a 1690 ret = intel_ring_begin(req, 6);
48a10389
BW		 1691 if (ret)
1692 return ret;
1693
e2f80391
TU		 1694 intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(2));
1695 intel_ring_emit_reg(engine, RING_PP_DIR_DCLV(engine));
1696 intel_ring_emit(engine, PP_DIR_DCLV_2G);
1697 intel_ring_emit_reg(engine, RING_PP_DIR_BASE(engine));
1698 intel_ring_emit(engine, get_pd_offset(ppgtt));
1699 intel_ring_emit(engine, MI_NOOP);
1700 intel_ring_advance(engine);
48a10389 1701
90252e5c 1702 /* XXX: RCS is the only one to auto invalidate the TLBs? */
e2f80391
TU		 1703 if (engine->id != RCS) {
1704 ret = engine->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
90252e5c
BW		 1705 if (ret)
1706 return ret;
1707 }
1708
48a10389
BW		 1709 return 0;
1710}
1711
eeb9488e 1712static int gen6_mm_switch(struct i915_hw_ppgtt *ppgtt,
e85b26dc 1713 struct drm_i915_gem_request *req)
eeb9488e 1714{
4a570db5 1715 struct intel_engine_cs *engine = req->engine;
eeb9488e
BW		 1716 struct drm_device *dev = ppgtt->base.dev;
1717 struct drm_i915_private *dev_priv = dev->dev_private;
1718
48a10389 1719
e2f80391
TU		 1720 I915_WRITE(RING_PP_DIR_DCLV(engine), PP_DIR_DCLV_2G);
1721 I915_WRITE(RING_PP_DIR_BASE(engine), get_pd_offset(ppgtt));
eeb9488e 1722
e2f80391 1723 POSTING_READ(RING_PP_DIR_DCLV(engine));
eeb9488e
BW		 1724
1725 return 0;
1726}
1727
82460d97 1728static void gen8_ppgtt_enable(struct drm_device *dev)
eeb9488e 1729{
eeb9488e 1730 struct drm_i915_private *dev_priv = dev->dev_private;
e2f80391 1731 struct intel_engine_cs *engine;
3e302542 1732
b4ac5afc 1733 for_each_engine(engine, dev_priv) {
2dba3239 1734 u32 four_level = USES_FULL_48BIT_PPGTT(dev) ? GEN8_GFX_PPGTT_48B : 0;
e2f80391 1735 I915_WRITE(RING_MODE_GEN7(engine),
2dba3239 1736 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE | four_level));
eeb9488e 1737 }
eeb9488e 1738}
6197349b 1739
82460d97 1740static void gen7_ppgtt_enable(struct drm_device *dev)
3e302542 1741{
50227e1c 1742 struct drm_i915_private *dev_priv = dev->dev_private;
e2f80391 1743 struct intel_engine_cs *engine;
b4a74e3a 1744 uint32_t ecochk, ecobits;
6197349b 1745
b4a74e3a
BW		 1746 ecobits = I915_READ(GAC_ECO_BITS);
1747 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);
a65c2fcd 1748
b4a74e3a
BW		 1749 ecochk = I915_READ(GAM_ECOCHK);
1750 if (IS_HASWELL(dev)) {
1751 ecochk |= ECOCHK_PPGTT_WB_HSW;
1752 } else {
1753 ecochk |= ECOCHK_PPGTT_LLC_IVB;
1754 ecochk &= ~ECOCHK_PPGTT_GFDT_IVB;
1755 }
1756 I915_WRITE(GAM_ECOCHK, ecochk);
a65c2fcd 1757
b4ac5afc 1758 for_each_engine(engine, dev_priv) {
6197349b 1759 /* GFX_MODE is per-ring on gen7+ */
e2f80391 1760 I915_WRITE(RING_MODE_GEN7(engine),
b4a74e3a 1761 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
6197349b 1762 }
b4a74e3a 1763}
6197349b 1764
82460d97 1765static void gen6_ppgtt_enable(struct drm_device *dev)
b4a74e3a 1766{
50227e1c 1767 struct drm_i915_private *dev_priv = dev->dev_private;
b4a74e3a 1768 uint32_t ecochk, gab_ctl, ecobits;
a65c2fcd 1769
b4a74e3a
BW		 1770 ecobits = I915_READ(GAC_ECO_BITS);
1771 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT |
1772 ECOBITS_PPGTT_CACHE64B);
6197349b 1773
b4a74e3a
BW		 1774 gab_ctl = I915_READ(GAB_CTL);
1775 I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);
1776
1777 ecochk = I915_READ(GAM_ECOCHK);
1778 I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B);
1779
1780 I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
6197349b
BW		 1781}
1782
1d2a314c 1783/* PPGTT support for Sandybdrige/Gen6 and later */
853ba5d2 1784static void gen6_ppgtt_clear_range(struct i915_address_space *vm,
782f1495
BW		 1785 uint64_t start,
1786 uint64_t length,
828c7908 1787 bool use_scratch)
1d2a314c 1788{
e5716f55 1789 struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
07749ef3 1790 gen6_pte_t *pt_vaddr, scratch_pte;
782f1495
BW		 1791 unsigned first_entry = start >> PAGE_SHIFT;
1792 unsigned num_entries = length >> PAGE_SHIFT;
07749ef3
MT		 1793 unsigned act_pt = first_entry / GEN6_PTES;
1794 unsigned first_pte = first_entry % GEN6_PTES;
7bddb01f 1795 unsigned last_pte, i;
1d2a314c 1796
c114f76a
MK		 1797 scratch_pte = vm->pte_encode(px_dma(vm->scratch_page),
1798 I915_CACHE_LLC, true, 0);
1d2a314c 1799
7bddb01f
DV		 1800 while (num_entries) {
1801 last_pte = first_pte + num_entries;
07749ef3
MT		 1802 if (last_pte > GEN6_PTES)
1803 last_pte = GEN6_PTES;
7bddb01f 1804
d1c54acd 1805 pt_vaddr = kmap_px(ppgtt->pd.page_table[act_pt]);
1d2a314c 1806
7bddb01f
DV		 1807 for (i = first_pte; i < last_pte; i++)
1808 pt_vaddr[i] = scratch_pte;
1d2a314c 1809
d1c54acd 1810 kunmap_px(ppgtt, pt_vaddr);
1d2a314c 1811
7bddb01f
DV		 1812 num_entries -= last_pte - first_pte;
1813 first_pte = 0;
a15326a5 1814 act_pt++;
7bddb01f 1815 }
1d2a314c
DV		 1816}
1817
853ba5d2 1818static void gen6_ppgtt_insert_entries(struct i915_address_space *vm,
def886c3 1819 struct sg_table *pages,
782f1495 1820 uint64_t start,
24f3a8cf 1821 enum i915_cache_level cache_level, u32 flags)
def886c3 1822{
e5716f55 1823 struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
07749ef3 1824 gen6_pte_t *pt_vaddr;
782f1495 1825 unsigned first_entry = start >> PAGE_SHIFT;
07749ef3
MT		 1826 unsigned act_pt = first_entry / GEN6_PTES;
1827 unsigned act_pte = first_entry % GEN6_PTES;
6e995e23
ID		 1828 struct sg_page_iter sg_iter;
1829
cc79714f 1830 pt_vaddr = NULL;
6e995e23 1831 for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) {
cc79714f 1832 if (pt_vaddr == NULL)
d1c54acd 1833 pt_vaddr = kmap_px(ppgtt->pd.page_table[act_pt]);
6e995e23 1834
cc79714f
CW		 1835 pt_vaddr[act_pte] =
1836 vm->pte_encode(sg_page_iter_dma_address(&sg_iter),
24f3a8cf
AG		 1837 cache_level, true, flags);
1838
07749ef3 1839 if (++act_pte == GEN6_PTES) {
d1c54acd 1840 kunmap_px(ppgtt, pt_vaddr);
cc79714f 1841 pt_vaddr = NULL;
a15326a5 1842 act_pt++;
6e995e23 1843 act_pte = 0;
def886c3 1844 }
def886c3 1845 }
cc79714f 1846 if (pt_vaddr)
d1c54acd 1847 kunmap_px(ppgtt, pt_vaddr);
def886c3
DV		 1848}
1849
678d96fb 1850static int gen6_alloc_va_range(struct i915_address_space *vm,
a05d80ee 1851 uint64_t start_in, uint64_t length_in)
678d96fb 1852{
4933d519
MT		 1853 DECLARE_BITMAP(new_page_tables, I915_PDES);
1854 struct drm_device *dev = vm->dev;
72e96d64
JL		 1855 struct drm_i915_private *dev_priv = to_i915(dev);
1856 struct i915_ggtt *ggtt = &dev_priv->ggtt;
e5716f55 1857 struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
ec565b3c 1858 struct i915_page_table *pt;
a05d80ee 1859 uint32_t start, length, start_save, length_save;
678d96fb 1860 uint32_t pde, temp;
4933d519
MT		 1861 int ret;
1862
a05d80ee
MK		 1863 if (WARN_ON(start_in + length_in > ppgtt->base.total))
1864 return -ENODEV;
1865
1866 start = start_save = start_in;
1867 length = length_save = length_in;
4933d519
MT		 1868
1869 bitmap_zero(new_page_tables, I915_PDES);
1870
1871 /* The allocation is done in two stages so that we can bail out with
1872 * minimal amount of pain. The first stage finds new page tables that
1873 * need allocation. The second stage marks use ptes within the page
1874 * tables.
1875 */
1876 gen6_for_each_pde(pt, &ppgtt->pd, start, length, temp, pde) {
79ab9370 1877 if (pt != vm->scratch_pt) {
4933d519
MT		 1878 WARN_ON(bitmap_empty(pt->used_ptes, GEN6_PTES));
1879 continue;
1880 }
1881
1882 /* We've already allocated a page table */
1883 WARN_ON(!bitmap_empty(pt->used_ptes, GEN6_PTES));
1884
8a1ebd74 1885 pt = alloc_pt(dev);
4933d519
MT		 1886 if (IS_ERR(pt)) {
1887 ret = PTR_ERR(pt);
1888 goto unwind_out;
1889 }
1890
1891 gen6_initialize_pt(vm, pt);
1892
1893 ppgtt->pd.page_table[pde] = pt;
966082c9 1894 __set_bit(pde, new_page_tables);
72744cb1 1895 trace_i915_page_table_entry_alloc(vm, pde, start, GEN6_PDE_SHIFT);
4933d519
MT		 1896 }
1897
1898 start = start_save;
1899 length = length_save;
678d96fb
BW		 1900
1901 gen6_for_each_pde(pt, &ppgtt->pd, start, length, temp, pde) {
1902 DECLARE_BITMAP(tmp_bitmap, GEN6_PTES);
1903
1904 bitmap_zero(tmp_bitmap, GEN6_PTES);
1905 bitmap_set(tmp_bitmap, gen6_pte_index(start),
1906 gen6_pte_count(start, length));
1907
966082c9 1908 if (__test_and_clear_bit(pde, new_page_tables))
4933d519
MT		 1909 gen6_write_pde(&ppgtt->pd, pde, pt);
1910
72744cb1
MT		 1911 trace_i915_page_table_entry_map(vm, pde, pt,
1912 gen6_pte_index(start),
1913 gen6_pte_count(start, length),
1914 GEN6_PTES);
4933d519 1915 bitmap_or(pt->used_ptes, tmp_bitmap, pt->used_ptes,
678d96fb
BW		 1916 GEN6_PTES);
1917 }
1918
4933d519
MT		 1919 WARN_ON(!bitmap_empty(new_page_tables, I915_PDES));
1920
1921 /* Make sure write is complete before other code can use this page
1922 * table. Also require for WC mapped PTEs */
72e96d64 1923 readl(ggtt->gsm);
4933d519 1924
563222a7 1925 mark_tlbs_dirty(ppgtt);
678d96fb 1926 return 0;
4933d519
MT		 1927
1928unwind_out:
1929 for_each_set_bit(pde, new_page_tables, I915_PDES) {
ec565b3c 1930 struct i915_page_table *pt = ppgtt->pd.page_table[pde];
4933d519 1931
79ab9370 1932 ppgtt->pd.page_table[pde] = vm->scratch_pt;
a08e111a 1933 free_pt(vm->dev, pt);
4933d519
MT		 1934 }
1935
1936 mark_tlbs_dirty(ppgtt);
1937 return ret;
678d96fb
BW		 1938}
1939
8776f02b
MK		 1940static int gen6_init_scratch(struct i915_address_space *vm)
1941{
1942 struct drm_device *dev = vm->dev;
1943
1944 vm->scratch_page = alloc_scratch_page(dev);
1945 if (IS_ERR(vm->scratch_page))
1946 return PTR_ERR(vm->scratch_page);
1947
1948 vm->scratch_pt = alloc_pt(dev);
1949 if (IS_ERR(vm->scratch_pt)) {
1950 free_scratch_page(dev, vm->scratch_page);
1951 return PTR_ERR(vm->scratch_pt);
1952 }
1953
1954 gen6_initialize_pt(vm, vm->scratch_pt);
1955
1956 return 0;
1957}
1958
1959static void gen6_free_scratch(struct i915_address_space *vm)
1960{
1961 struct drm_device *dev = vm->dev;
1962
1963 free_pt(dev, vm->scratch_pt);
1964 free_scratch_page(dev, vm->scratch_page);
1965}
1966
061dd493 1967static void gen6_ppgtt_cleanup(struct i915_address_space *vm)
a00d825d 1968{
e5716f55 1969 struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
09942c65
MT		 1970 struct i915_page_table *pt;
1971 uint32_t pde;
4933d519 1972
061dd493
DV		 1973 drm_mm_remove_node(&ppgtt->node);
1974
09942c65 1975 gen6_for_all_pdes(pt, ppgtt, pde) {
79ab9370 1976 if (pt != vm->scratch_pt)
a08e111a 1977 free_pt(ppgtt->base.dev, pt);
4933d519 1978 }
06fda602 1979
8776f02b 1980 gen6_free_scratch(vm);
3440d265
DV		 1981}
1982
b146520f 1983static int gen6_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt)
3440d265 1984{
8776f02b 1985 struct i915_address_space *vm = &ppgtt->base;
853ba5d2 1986 struct drm_device *dev = ppgtt->base.dev;
72e96d64
JL		 1987 struct drm_i915_private *dev_priv = to_i915(dev);
1988 struct i915_ggtt *ggtt = &dev_priv->ggtt;
e3cc1995 1989 bool retried = false;
b146520f 1990 int ret;
1d2a314c 1991
c8d4c0d6
BW		 1992 /* PPGTT PDEs reside in the GGTT and consists of 512 entries. The
1993 * allocator works in address space sizes, so it's multiplied by page
1994 * size. We allocate at the top of the GTT to avoid fragmentation.
1995 */
72e96d64 1996 BUG_ON(!drm_mm_initialized(&ggtt->base.mm));
4933d519 1997
8776f02b
MK		 1998 ret = gen6_init_scratch(vm);
1999 if (ret)
2000 return ret;
4933d519 2001
e3cc1995 2002alloc:
72e96d64 2003 ret = drm_mm_insert_node_in_range_generic(&ggtt->base.mm,
c8d4c0d6
BW		 2004 &ppgtt->node, GEN6_PD_SIZE,
2005 GEN6_PD_ALIGN, 0,
72e96d64 2006 0, ggtt->base.total,
3e8b5ae9 2007 DRM_MM_TOPDOWN);
e3cc1995 2008 if (ret == -ENOSPC && !retried) {
72e96d64 2009 ret = i915_gem_evict_something(dev, &ggtt->base,
e3cc1995 2010 GEN6_PD_SIZE, GEN6_PD_ALIGN,
d23db88c 2011 I915_CACHE_NONE,
72e96d64 2012 0, ggtt->base.total,
d23db88c 2013 0);
e3cc1995 2014 if (ret)
678d96fb 2015 goto err_out;
e3cc1995
BW		 2016
2017 retried = true;
2018 goto alloc;
2019 }
c8d4c0d6 2020
c8c26622 2021 if (ret)
678d96fb
BW		 2022 goto err_out;
2023
c8c26622 2024
72e96d64 2025 if (ppgtt->node.start < ggtt->mappable_end)
c8d4c0d6 2026 DRM_DEBUG("Forced to use aperture for PDEs\n");
1d2a314c 2027
c8c26622 2028 return 0;
678d96fb
BW		 2029
2030err_out:
8776f02b 2031 gen6_free_scratch(vm);
678d96fb 2032 return ret;
b146520f
BW		 2033}
2034
b146520f
BW		 2035static int gen6_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt)
2036{
2f2cf682 2037 return gen6_ppgtt_allocate_page_directories(ppgtt);
4933d519 2038}
06dc68d6 2039
4933d519
MT		 2040static void gen6_scratch_va_range(struct i915_hw_ppgtt *ppgtt,
2041 uint64_t start, uint64_t length)
2042{
ec565b3c 2043 struct i915_page_table *unused;
4933d519 2044 uint32_t pde, temp;
1d2a314c 2045
4933d519 2046 gen6_for_each_pde(unused, &ppgtt->pd, start, length, temp, pde)
79ab9370 2047 ppgtt->pd.page_table[pde] = ppgtt->base.scratch_pt;
b146520f
BW		 2048}
2049
5c5f6457 2050static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
b146520f
BW		 2051{
2052 struct drm_device *dev = ppgtt->base.dev;
72e96d64
JL		 2053 struct drm_i915_private *dev_priv = to_i915(dev);
2054 struct i915_ggtt *ggtt = &dev_priv->ggtt;
b146520f
BW		 2055 int ret;
2056
72e96d64 2057 ppgtt->base.pte_encode = ggtt->base.pte_encode;
b146520f 2058 if (IS_GEN6(dev)) {
b146520f
BW		 2059 ppgtt->switch_mm = gen6_mm_switch;
2060 } else if (IS_HASWELL(dev)) {
b146520f
BW		 2061 ppgtt->switch_mm = hsw_mm_switch;
2062 } else if (IS_GEN7(dev)) {
b146520f
BW		 2063 ppgtt->switch_mm = gen7_mm_switch;
2064 } else
2065 BUG();
2066
71ba2d64
YZ		 2067 if (intel_vgpu_active(dev))
2068 ppgtt->switch_mm = vgpu_mm_switch;
2069
b146520f
BW		 2070 ret = gen6_ppgtt_alloc(ppgtt);
2071 if (ret)
2072 return ret;
2073
5c5f6457 2074 ppgtt->base.allocate_va_range = gen6_alloc_va_range;
b146520f
BW		 2075 ppgtt->base.clear_range = gen6_ppgtt_clear_range;
2076 ppgtt->base.insert_entries = gen6_ppgtt_insert_entries;
777dc5bb
DV		 2077 ppgtt->base.unbind_vma = ppgtt_unbind_vma;
2078 ppgtt->base.bind_vma = ppgtt_bind_vma;
b146520f 2079 ppgtt->base.cleanup = gen6_ppgtt_cleanup;
b146520f 2080 ppgtt->base.start = 0;
09942c65 2081 ppgtt->base.total = I915_PDES * GEN6_PTES * PAGE_SIZE;
87d60b63 2082 ppgtt->debug_dump = gen6_dump_ppgtt;
1d2a314c 2083
44159ddb 2084 ppgtt->pd.base.ggtt_offset =
07749ef3 2085 ppgtt->node.start / PAGE_SIZE * sizeof(gen6_pte_t);
1d2a314c 2086
72e96d64 2087 ppgtt->pd_addr = (gen6_pte_t __iomem *)ggtt->gsm +
44159ddb 2088 ppgtt->pd.base.ggtt_offset / sizeof(gen6_pte_t);
678d96fb 2089
5c5f6457 2090 gen6_scratch_va_range(ppgtt, 0, ppgtt->base.total);
1d2a314c 2091
678d96fb
BW		 2092 gen6_write_page_range(dev_priv, &ppgtt->pd, 0, ppgtt->base.total);
2093
440fd528 2094 DRM_DEBUG_DRIVER("Allocated pde space (%lldM) at GTT entry: %llx\n",
b146520f
BW		 2095 ppgtt->node.size >> 20,
2096 ppgtt->node.start / PAGE_SIZE);
3440d265 2097
fa76da34 2098 DRM_DEBUG("Adding PPGTT at offset %x\n",
44159ddb 2099 ppgtt->pd.base.ggtt_offset << 10);
fa76da34 2100
b146520f 2101 return 0;
3440d265
DV		 2102}
2103
5c5f6457 2104static int __hw_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt)
3440d265 2105{
853ba5d2 2106 ppgtt->base.dev = dev;
3440d265 2107
3ed124b2 2108 if (INTEL_INFO(dev)->gen < 8)
5c5f6457 2109 return gen6_ppgtt_init(ppgtt);
3ed124b2 2110 else
d7b2633d 2111 return gen8_ppgtt_init(ppgtt);
fa76da34 2112}
c114f76a 2113
a2cad9df
MW		 2114static void i915_address_space_init(struct i915_address_space *vm,
2115 struct drm_i915_private *dev_priv)
2116{
2117 drm_mm_init(&vm->mm, vm->start, vm->total);
2118 vm->dev = dev_priv->dev;
2119 INIT_LIST_HEAD(&vm->active_list);
2120 INIT_LIST_HEAD(&vm->inactive_list);
2121 list_add_tail(&vm->global_link, &dev_priv->vm_list);
2122}
2123
d5165ebd
TG		 2124static void gtt_write_workarounds(struct drm_device *dev)
2125{
2126 struct drm_i915_private *dev_priv = dev->dev_private;
2127
2128 /* This function is for gtt related workarounds. This function is
2129 * called on driver load and after a GPU reset, so you can place
2130 * workarounds here even if they get overwritten by GPU reset.
2131 */
2132 /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt */
2133 if (IS_BROADWELL(dev))
2134 I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW);
2135 else if (IS_CHERRYVIEW(dev))
2136 I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV);
2137 else if (IS_SKYLAKE(dev))
2138 I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL);
2139 else if (IS_BROXTON(dev))
2140 I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT);
2141}
2142
fa76da34
DV		 2143int i915_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt)
2144{
2145 struct drm_i915_private *dev_priv = dev->dev_private;
2146 int ret = 0;
3ed124b2 2147
5c5f6457 2148 ret = __hw_ppgtt_init(dev, ppgtt);
fa76da34 2149 if (ret == 0) {
c7c48dfd 2150 kref_init(&ppgtt->ref);
a2cad9df 2151 i915_address_space_init(&ppgtt->base, dev_priv);
93bd8649 2152 }
1d2a314c
DV		 2153
2154 return ret;
2155}
2156
82460d97
DV		 2157int i915_ppgtt_init_hw(struct drm_device *dev)
2158{
d5165ebd
TG		 2159 gtt_write_workarounds(dev);
2160
671b5013
TD		 2161 /* In the case of execlists, PPGTT is enabled by the context descriptor
2162 * and the PDPs are contained within the context itself. We don't
2163 * need to do anything here. */
2164 if (i915.enable_execlists)
2165 return 0;
2166
82460d97
DV		 2167 if (!USES_PPGTT(dev))
2168 return 0;
2169
2170 if (IS_GEN6(dev))
2171 gen6_ppgtt_enable(dev);
2172 else if (IS_GEN7(dev))
2173 gen7_ppgtt_enable(dev);
2174 else if (INTEL_INFO(dev)->gen >= 8)
2175 gen8_ppgtt_enable(dev);
2176 else
5f77eeb0 2177 MISSING_CASE(INTEL_INFO(dev)->gen);
82460d97 2178
4ad2fd88
JH		 2179 return 0;
2180}
1d2a314c 2181
b3dd6b96 2182int i915_ppgtt_init_ring(struct drm_i915_gem_request *req)
4ad2fd88 2183{
39dabecd 2184 struct drm_i915_private *dev_priv = req->i915;
4ad2fd88
JH		 2185 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2186
2187 if (i915.enable_execlists)
2188 return 0;
2189
2190 if (!ppgtt)
2191 return 0;
2192
e85b26dc 2193 return ppgtt->switch_mm(ppgtt, req);
1d2a314c 2194}
4ad2fd88 2195
4d884705
DV		 2196struct i915_hw_ppgtt *
2197i915_ppgtt_create(struct drm_device *dev, struct drm_i915_file_private *fpriv)
2198{
2199 struct i915_hw_ppgtt *ppgtt;
2200 int ret;
2201
2202 ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
2203 if (!ppgtt)
2204 return ERR_PTR(-ENOMEM);
2205
2206 ret = i915_ppgtt_init(dev, ppgtt);
2207 if (ret) {
2208 kfree(ppgtt);
2209 return ERR_PTR(ret);
2210 }
2211
2212 ppgtt->file_priv = fpriv;
2213
198c974d
DCS		 2214 trace_i915_ppgtt_create(&ppgtt->base);
2215
4d884705
DV		 2216 return ppgtt;
2217}
2218
ee960be7
DV		 2219void i915_ppgtt_release(struct kref *kref)
2220{
2221 struct i915_hw_ppgtt *ppgtt =
2222 container_of(kref, struct i915_hw_ppgtt, ref);
2223
198c974d
DCS		 2224 trace_i915_ppgtt_release(&ppgtt->base);
2225
ee960be7
DV		 2226 /* vmas should already be unbound */
2227 WARN_ON(!list_empty(&ppgtt->base.active_list));
2228 WARN_ON(!list_empty(&ppgtt->base.inactive_list));
2229
19dd120c
DV		 2230 list_del(&ppgtt->base.global_link);
2231 drm_mm_takedown(&ppgtt->base.mm);
2232
ee960be7
DV		 2233 ppgtt->base.cleanup(&ppgtt->base);
2234 kfree(ppgtt);
2235}
1d2a314c 2236
a81cc00c
BW		 2237extern int intel_iommu_gfx_mapped;
2238/* Certain Gen5 chipsets require require idling the GPU before
2239 * unmapping anything from the GTT when VT-d is enabled.
2240 */
2c642b07 2241static bool needs_idle_maps(struct drm_device *dev)
a81cc00c
BW		 2242{
2243#ifdef CONFIG_INTEL_IOMMU
2244 /* Query intel_iommu to see if we need the workaround. Presumably that
2245 * was loaded first.
2246 */
2247 if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped)
2248 return true;
2249#endif
2250 return false;
2251}
2252
5c042287
BW		 2253static bool do_idling(struct drm_i915_private *dev_priv)
2254{
72e96d64 2255 struct i915_ggtt *ggtt = &dev_priv->ggtt;
5c042287
BW		 2256 bool ret = dev_priv->mm.interruptible;
2257
72e96d64 2258 if (unlikely(ggtt->do_idle_maps)) {
5c042287 2259 dev_priv->mm.interruptible = false;
b2da9fe5 2260 if (i915_gpu_idle(dev_priv->dev)) {
5c042287
BW		 2261 DRM_ERROR("Couldn't idle GPU\n");
2262 /* Wait a bit, in hopes it avoids the hang */
2263 udelay(10);
2264 }
2265 }
2266
2267 return ret;
2268}
2269
2270static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible)
2271{
72e96d64
JL		 2272 struct i915_ggtt *ggtt = &dev_priv->ggtt;
2273
2274 if (unlikely(ggtt->do_idle_maps))
5c042287
BW		 2275 dev_priv->mm.interruptible = interruptible;
2276}
2277
828c7908
BW		 2278void i915_check_and_clear_faults(struct drm_device *dev)
2279{
2280 struct drm_i915_private *dev_priv = dev->dev_private;
e2f80391 2281 struct intel_engine_cs *engine;
828c7908
BW		 2282
2283 if (INTEL_INFO(dev)->gen < 6)
2284 return;
2285
b4ac5afc 2286 for_each_engine(engine, dev_priv) {
828c7908 2287 u32 fault_reg;
e2f80391 2288 fault_reg = I915_READ(RING_FAULT_REG(engine));
828c7908
BW		 2289 if (fault_reg & RING_FAULT_VALID) {
2290 DRM_DEBUG_DRIVER("Unexpected fault\n"
59a5d290 2291 "\tAddr: 0x%08lx\n"
828c7908
BW		 2292 "\tAddress space: %s\n"
2293 "\tSource ID: %d\n"
2294 "\tType: %d\n",
2295 fault_reg & PAGE_MASK,
2296 fault_reg & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT",
2297 RING_FAULT_SRCID(fault_reg),
2298 RING_FAULT_FAULT_TYPE(fault_reg));
e2f80391 2299 I915_WRITE(RING_FAULT_REG(engine),
828c7908
BW		 2300 fault_reg & ~RING_FAULT_VALID);
2301 }
2302 }
4a570db5 2303 POSTING_READ(RING_FAULT_REG(&dev_priv->engine[RCS]));
828c7908
BW		 2304}
2305
91e56499
CW		 2306static void i915_ggtt_flush(struct drm_i915_private *dev_priv)
2307{
2d1fe073 2308 if (INTEL_INFO(dev_priv)->gen < 6) {
91e56499
CW		 2309 intel_gtt_chipset_flush();
2310 } else {
2311 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
2312 POSTING_READ(GFX_FLSH_CNTL_GEN6);
2313 }
2314}
2315
828c7908
BW		 2316void i915_gem_suspend_gtt_mappings(struct drm_device *dev)
2317{
72e96d64
JL		 2318 struct drm_i915_private *dev_priv = to_i915(dev);
2319 struct i915_ggtt *ggtt = &dev_priv->ggtt;
828c7908
BW		 2320
2321 /* Don't bother messing with faults pre GEN6 as we have little
2322 * documentation supporting that it's a good idea.
2323 */
2324 if (INTEL_INFO(dev)->gen < 6)
2325 return;
2326
2327 i915_check_and_clear_faults(dev);
2328
72e96d64
JL		 2329 ggtt->base.clear_range(&ggtt->base, ggtt->base.start, ggtt->base.total,
2330 true);
91e56499
CW		 2331
2332 i915_ggtt_flush(dev_priv);
828c7908
BW		 2333}
2334
74163907 2335int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj)
7c2e6fdf 2336{
9da3da66
CW		 2337 if (!dma_map_sg(&obj->base.dev->pdev->dev,
2338 obj->pages->sgl, obj->pages->nents,
2339 PCI_DMA_BIDIRECTIONAL))
2340 return -ENOSPC;
2341
2342 return 0;
7c2e6fdf
DV		 2343}
2344
2c642b07 2345static void gen8_set_pte(void __iomem *addr, gen8_pte_t pte)
94ec8f61
BW		 2346{
2347#ifdef writeq
2348 writeq(pte, addr);
2349#else
2350 iowrite32((u32)pte, addr);
2351 iowrite32(pte >> 32, addr + 4);
2352#endif
2353}
2354
2355static void gen8_ggtt_insert_entries(struct i915_address_space *vm,
2356 struct sg_table *st,
782f1495 2357 uint64_t start,
24f3a8cf 2358 enum i915_cache_level level, u32 unused)
94ec8f61 2359{
72e96d64
JL		 2360 struct drm_i915_private *dev_priv = to_i915(vm->dev);
2361 struct i915_ggtt *ggtt = &dev_priv->ggtt;
782f1495 2362 unsigned first_entry = start >> PAGE_SHIFT;
07749ef3 2363 gen8_pte_t __iomem *gtt_entries =
72e96d64 2364 (gen8_pte_t __iomem *)ggtt->gsm + first_entry;
94ec8f61
BW		 2365 int i = 0;
2366 struct sg_page_iter sg_iter;
57007df7 2367 dma_addr_t addr = 0; /* shut up gcc */
be69459a
ID		 2368 int rpm_atomic_seq;
2369
2370 rpm_atomic_seq = assert_rpm_atomic_begin(dev_priv);
94ec8f61
BW		 2371
2372 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
2373 addr = sg_dma_address(sg_iter.sg) +
2374 (sg_iter.sg_pgoffset << PAGE_SHIFT);
2375 gen8_set_pte(&gtt_entries[i],
2376 gen8_pte_encode(addr, level, true));
2377 i++;
2378 }
2379
2380 /*
2381 * XXX: This serves as a posting read to make sure that the PTE has
2382 * actually been updated. There is some concern that even though
2383 * registers and PTEs are within the same BAR that they are potentially
2384 * of NUMA access patterns. Therefore, even with the way we assume
2385 * hardware should work, we must keep this posting read for paranoia.
2386 */
2387 if (i != 0)
2388 WARN_ON(readq(&gtt_entries[i-1])
2389 != gen8_pte_encode(addr, level, true));
2390
94ec8f61
BW		 2391 /* This next bit makes the above posting read even more important. We
2392 * want to flush the TLBs only after we're certain all the PTE updates
2393 * have finished.
2394 */
2395 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
2396 POSTING_READ(GFX_FLSH_CNTL_GEN6);
be69459a
ID		 2397
2398 assert_rpm_atomic_end(dev_priv, rpm_atomic_seq);
94ec8f61
BW		 2399}
2400
c140330b
CW		 2401struct insert_entries {
2402 struct i915_address_space *vm;
2403 struct sg_table *st;
2404 uint64_t start;
2405 enum i915_cache_level level;
2406 u32 flags;
2407};
2408
2409static int gen8_ggtt_insert_entries__cb(void *_arg)
2410{
2411 struct insert_entries *arg = _arg;
2412 gen8_ggtt_insert_entries(arg->vm, arg->st,
2413 arg->start, arg->level, arg->flags);
2414 return 0;
2415}
2416
2417static void gen8_ggtt_insert_entries__BKL(struct i915_address_space *vm,
2418 struct sg_table *st,
2419 uint64_t start,
2420 enum i915_cache_level level,
2421 u32 flags)
2422{
2423 struct insert_entries arg = { vm, st, start, level, flags };
2424 stop_machine(gen8_ggtt_insert_entries__cb, &arg, NULL);
2425}
2426
e76e9aeb
BW		 2427/*
2428 * Binds an object into the global gtt with the specified cache level. The object
2429 * will be accessible to the GPU via commands whose operands reference offsets
2430 * within the global GTT as well as accessible by the GPU through the GMADR
2431 * mapped BAR (dev_priv->mm.gtt->gtt).
2432 */
853ba5d2 2433static void gen6_ggtt_insert_entries(struct i915_address_space *vm,
7faf1ab2 2434 struct sg_table *st,
782f1495 2435 uint64_t start,
24f3a8cf 2436 enum i915_cache_level level, u32 flags)
e76e9aeb 2437{
72e96d64
JL		 2438 struct drm_i915_private *dev_priv = to_i915(vm->dev);
2439 struct i915_ggtt *ggtt = &dev_priv->ggtt;
782f1495 2440 unsigned first_entry = start >> PAGE_SHIFT;
07749ef3 2441 gen6_pte_t __iomem *gtt_entries =
72e96d64 2442 (gen6_pte_t __iomem *)ggtt->gsm + first_entry;
6e995e23
ID		 2443 int i = 0;
2444 struct sg_page_iter sg_iter;
57007df7 2445 dma_addr_t addr = 0;
be69459a
ID		 2446 int rpm_atomic_seq;
2447
2448 rpm_atomic_seq = assert_rpm_atomic_begin(dev_priv);
e76e9aeb 2449
6e995e23 2450 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
2db76d7c 2451 addr = sg_page_iter_dma_address(&sg_iter);
24f3a8cf 2452 iowrite32(vm->pte_encode(addr, level, true, flags), &gtt_entries[i]);
6e995e23 2453 i++;
e76e9aeb
BW		 2454 }
2455
e76e9aeb
BW		 2456 /* XXX: This serves as a posting read to make sure that the PTE has
2457 * actually been updated. There is some concern that even though
2458 * registers and PTEs are within the same BAR that they are potentially
2459 * of NUMA access patterns. Therefore, even with the way we assume
2460 * hardware should work, we must keep this posting read for paranoia.
2461 */
57007df7
PM		 2462 if (i != 0) {
2463 unsigned long gtt = readl(&gtt_entries[i-1]);
2464 WARN_ON(gtt != vm->pte_encode(addr, level, true, flags));
2465 }
0f9b91c7
BW		 2466
2467 /* This next bit makes the above posting read even more important. We
2468 * want to flush the TLBs only after we're certain all the PTE updates
2469 * have finished.
2470 */
2471 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
2472 POSTING_READ(GFX_FLSH_CNTL_GEN6);
be69459a
ID		 2473
2474 assert_rpm_atomic_end(dev_priv, rpm_atomic_seq);
e76e9aeb
BW		 2475}
2476
94ec8f61 2477static void gen8_ggtt_clear_range(struct i915_address_space *vm,
782f1495
BW		 2478 uint64_t start,
2479 uint64_t length,
94ec8f61
BW		 2480 bool use_scratch)
2481{
72e96d64
JL		 2482 struct drm_i915_private *dev_priv = to_i915(vm->dev);
2483 struct i915_ggtt *ggtt = &dev_priv->ggtt;
782f1495
BW		 2484 unsigned first_entry = start >> PAGE_SHIFT;
2485 unsigned num_entries = length >> PAGE_SHIFT;
07749ef3 2486 gen8_pte_t scratch_pte, __iomem *gtt_base =
72e96d64
JL		 2487 (gen8_pte_t __iomem *)ggtt->gsm + first_entry;
2488 const int max_entries = ggtt_total_entries(ggtt) - first_entry;
94ec8f61 2489 int i;
be69459a
ID		 2490 int rpm_atomic_seq;
2491
2492 rpm_atomic_seq = assert_rpm_atomic_begin(dev_priv);
94ec8f61
BW		 2493
2494 if (WARN(num_entries > max_entries,
2495 "First entry = %d; Num entries = %d (max=%d)\n",
2496 first_entry, num_entries, max_entries))
2497 num_entries = max_entries;
2498
c114f76a 2499 scratch_pte = gen8_pte_encode(px_dma(vm->scratch_page),
94ec8f61
BW		 2500 I915_CACHE_LLC,
2501 use_scratch);
2502 for (i = 0; i < num_entries; i++)
2503 gen8_set_pte(&gtt_base[i], scratch_pte);
2504 readl(gtt_base);
be69459a
ID		 2505
2506 assert_rpm_atomic_end(dev_priv, rpm_atomic_seq);
94ec8f61
BW		 2507}
2508
853ba5d2 2509static void gen6_ggtt_clear_range(struct i915_address_space *vm,
782f1495
BW		 2510 uint64_t start,
2511 uint64_t length,
828c7908 2512 bool use_scratch)
7faf1ab2 2513{
72e96d64
JL		 2514 struct drm_i915_private *dev_priv = to_i915(vm->dev);
2515 struct i915_ggtt *ggtt = &dev_priv->ggtt;
782f1495
BW		 2516 unsigned first_entry = start >> PAGE_SHIFT;
2517 unsigned num_entries = length >> PAGE_SHIFT;
07749ef3 2518 gen6_pte_t scratch_pte, __iomem *gtt_base =
72e96d64
JL		 2519 (gen6_pte_t __iomem *)ggtt->gsm + first_entry;
2520 const int max_entries = ggtt_total_entries(ggtt) - first_entry;
7faf1ab2 2521 int i;
be69459a
ID		 2522 int rpm_atomic_seq;
2523
2524 rpm_atomic_seq = assert_rpm_atomic_begin(dev_priv);
7faf1ab2
DV		 2525
2526 if (WARN(num_entries > max_entries,
2527 "First entry = %d; Num entries = %d (max=%d)\n",
2528 first_entry, num_entries, max_entries))
2529 num_entries = max_entries;
2530
c114f76a
MK		 2531 scratch_pte = vm->pte_encode(px_dma(vm->scratch_page),
2532 I915_CACHE_LLC, use_scratch, 0);
828c7908 2533
7faf1ab2
DV		 2534 for (i = 0; i < num_entries; i++)
2535 iowrite32(scratch_pte, &gtt_base[i]);
2536 readl(gtt_base);
be69459a
ID		 2537
2538 assert_rpm_atomic_end(dev_priv, rpm_atomic_seq);
7faf1ab2
DV		 2539}
2540
d369d2d9
DV		 2541static void i915_ggtt_insert_entries(struct i915_address_space *vm,
2542 struct sg_table *pages,
2543 uint64_t start,
2544 enum i915_cache_level cache_level, u32 unused)
7faf1ab2 2545{
be69459a 2546 struct drm_i915_private *dev_priv = vm->dev->dev_private;
7faf1ab2
DV		 2547 unsigned int flags = (cache_level == I915_CACHE_NONE) ?
2548 AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
be69459a
ID		 2549 int rpm_atomic_seq;
2550
2551 rpm_atomic_seq = assert_rpm_atomic_begin(dev_priv);
7faf1ab2 2552
d369d2d9 2553 intel_gtt_insert_sg_entries(pages, start >> PAGE_SHIFT, flags);
0875546c 2554
be69459a
ID		 2555 assert_rpm_atomic_end(dev_priv, rpm_atomic_seq);
2556
7faf1ab2
DV		 2557}
2558
853ba5d2 2559static void i915_ggtt_clear_range(struct i915_address_space *vm,
782f1495
BW		 2560 uint64_t start,
2561 uint64_t length,
828c7908 2562 bool unused)
7faf1ab2 2563{
be69459a 2564 struct drm_i915_private *dev_priv = vm->dev->dev_private;
782f1495
BW		 2565 unsigned first_entry = start >> PAGE_SHIFT;
2566 unsigned num_entries = length >> PAGE_SHIFT;
be69459a
ID		 2567 int rpm_atomic_seq;
2568
2569 rpm_atomic_seq = assert_rpm_atomic_begin(dev_priv);
2570
7faf1ab2 2571 intel_gtt_clear_range(first_entry, num_entries);
be69459a
ID		 2572
2573 assert_rpm_atomic_end(dev_priv, rpm_atomic_seq);
7faf1ab2
DV		 2574}
2575
70b9f6f8
DV		 2576static int ggtt_bind_vma(struct i915_vma *vma,
2577 enum i915_cache_level cache_level,
2578 u32 flags)
0a878716
DV		 2579{
2580 struct drm_i915_gem_object *obj = vma->obj;
2581 u32 pte_flags = 0;
2582 int ret;
2583
2584 ret = i915_get_ggtt_vma_pages(vma);
2585 if (ret)
2586 return ret;
2587
2588 /* Currently applicable only to VLV */
2589 if (obj->gt_ro)
2590 pte_flags |= PTE_READ_ONLY;
2591
2592 vma->vm->insert_entries(vma->vm, vma->ggtt_view.pages,
2593 vma->node.start,
2594 cache_level, pte_flags);
2595
2596 /*
2597 * Without aliasing PPGTT there's no difference between
2598 * GLOBAL/LOCAL_BIND, it's all the same ptes. Hence unconditionally
2599 * upgrade to both bound if we bind either to avoid double-binding.
2600 */
2601 vma->bound |= GLOBAL_BIND | LOCAL_BIND;
2602
2603 return 0;
2604}
2605
2606static int aliasing_gtt_bind_vma(struct i915_vma *vma,
2607 enum i915_cache_level cache_level,
2608 u32 flags)
d5bd1449 2609{
321d178e 2610 u32 pte_flags;
70b9f6f8
DV		 2611 int ret;
2612
2613 ret = i915_get_ggtt_vma_pages(vma);
2614 if (ret)
2615 return ret;
7faf1ab2 2616
24f3a8cf 2617 /* Currently applicable only to VLV */
321d178e
CW		 2618 pte_flags = 0;
2619 if (vma->obj->gt_ro)
f329f5f6 2620 pte_flags |= PTE_READ_ONLY;
24f3a8cf 2621
ec7adb6e 2622
0a878716 2623 if (flags & GLOBAL_BIND) {
321d178e
CW		 2624 vma->vm->insert_entries(vma->vm,
2625 vma->ggtt_view.pages,
0875546c
DV		 2626 vma->node.start,
2627 cache_level, pte_flags);
6f65e29a 2628 }
d5bd1449 2629
0a878716 2630 if (flags & LOCAL_BIND) {
321d178e
CW		 2631 struct i915_hw_ppgtt *appgtt =
2632 to_i915(vma->vm->dev)->mm.aliasing_ppgtt;
2633 appgtt->base.insert_entries(&appgtt->base,
2634 vma->ggtt_view.pages,
782f1495 2635 vma->node.start,
f329f5f6 2636 cache_level, pte_flags);
6f65e29a 2637 }
70b9f6f8
DV		 2638
2639 return 0;
d5bd1449
CW		 2640}
2641
6f65e29a 2642static void ggtt_unbind_vma(struct i915_vma *vma)
74163907 2643{
6f65e29a 2644 struct drm_device *dev = vma->vm->dev;
7faf1ab2 2645 struct drm_i915_private *dev_priv = dev->dev_private;
6f65e29a 2646 struct drm_i915_gem_object *obj = vma->obj;
06615ee5
JL		 2647 const uint64_t size = min_t(uint64_t,
2648 obj->base.size,
2649 vma->node.size);
6f65e29a 2650
aff43766 2651 if (vma->bound & GLOBAL_BIND) {
782f1495
BW		 2652 vma->vm->clear_range(vma->vm,
2653 vma->node.start,
06615ee5 2654 size,
6f65e29a 2655 true);
6f65e29a 2656 }
74898d7e 2657
0875546c 2658 if (dev_priv->mm.aliasing_ppgtt && vma->bound & LOCAL_BIND) {
6f65e29a 2659 struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt;
06615ee5 2660
6f65e29a 2661 appgtt->base.clear_range(&appgtt->base,
782f1495 2662 vma->node.start,
06615ee5 2663 size,
6f65e29a 2664 true);
6f65e29a 2665 }
74163907
DV		 2666}
2667
2668void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj)
7c2e6fdf 2669{
5c042287
BW		 2670 struct drm_device *dev = obj->base.dev;
2671 struct drm_i915_private *dev_priv = dev->dev_private;
2672 bool interruptible;
2673
2674 interruptible = do_idling(dev_priv);
2675
5ec5b516
ID		 2676 dma_unmap_sg(&dev->pdev->dev, obj->pages->sgl, obj->pages->nents,
2677 PCI_DMA_BIDIRECTIONAL);
5c042287
BW		 2678
2679 undo_idling(dev_priv, interruptible);
7c2e6fdf 2680}
644ec02b 2681
42d6ab48
CW		 2682static void i915_gtt_color_adjust(struct drm_mm_node *node,
2683 unsigned long color,
440fd528
TR		 2684 u64 *start,
2685 u64 *end)
42d6ab48
CW		 2686{
2687 if (node->color != color)
2688 *start += 4096;
2689
2690 if (!list_empty(&node->node_list)) {
2691 node = list_entry(node->node_list.next,
2692 struct drm_mm_node,
2693 node_list);
2694 if (node->allocated && node->color != color)
2695 *end -= 4096;
2696 }
2697}
fbe5d36e 2698
f548c0e9 2699static int i915_gem_setup_global_gtt(struct drm_device *dev,
088e0df4
MT		 2700 u64 start,
2701 u64 mappable_end,
2702 u64 end)
644ec02b 2703{
e78891ca
BW		 2704 /* Let GEM Manage all of the aperture.
2705 *
2706 * However, leave one page at the end still bound to the scratch page.
2707 * There are a number of places where the hardware apparently prefetches
2708 * past the end of the object, and we've seen multiple hangs with the
2709 * GPU head pointer stuck in a batchbuffer bound at the last page of the
2710 * aperture. One page should be enough to keep any prefetching inside
2711 * of the aperture.
2712 */
72e96d64
JL		 2713 struct drm_i915_private *dev_priv = to_i915(dev);
2714 struct i915_ggtt *ggtt = &dev_priv->ggtt;
ed2f3452
CW		 2715 struct drm_mm_node *entry;
2716 struct drm_i915_gem_object *obj;
2717 unsigned long hole_start, hole_end;
fa76da34 2718 int ret;
644ec02b 2719
35451cb6
BW		 2720 BUG_ON(mappable_end > end);
2721
72e96d64 2722 ggtt->base.start = start;
5dda8fa3 2723
a2cad9df
MW		 2724 /* Subtract the guard page before address space initialization to
2725 * shrink the range used by drm_mm */
72e96d64
JL		 2726 ggtt->base.total = end - start - PAGE_SIZE;
2727 i915_address_space_init(&ggtt->base, dev_priv);
2728 ggtt->base.total += PAGE_SIZE;
5dda8fa3
YZ		 2729
2730 if (intel_vgpu_active(dev)) {
2731 ret = intel_vgt_balloon(dev);
2732 if (ret)
2733 return ret;
2734 }
2735
42d6ab48 2736 if (!HAS_LLC(dev))
72e96d64 2737 ggtt->base.mm.color_adjust = i915_gtt_color_adjust;
644ec02b 2738
ed2f3452 2739 /* Mark any preallocated objects as occupied */
35c20a60 2740 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
72e96d64 2741 struct i915_vma *vma = i915_gem_obj_to_vma(obj, &ggtt->base);
fa76da34 2742
088e0df4 2743 DRM_DEBUG_KMS("reserving preallocated space: %llx + %zx\n",
c6cfb325
BW		 2744 i915_gem_obj_ggtt_offset(obj), obj->base.size);
2745
2746 WARN_ON(i915_gem_obj_ggtt_bound(obj));
72e96d64 2747 ret = drm_mm_reserve_node(&ggtt->base.mm, &vma->node);
6c5566a8
DV		 2748 if (ret) {
2749 DRM_DEBUG_KMS("Reservation failed: %i\n", ret);
2750 return ret;
2751 }
aff43766 2752 vma->bound |= GLOBAL_BIND;
d0710abb 2753 __i915_vma_set_map_and_fenceable(vma);
72e96d64 2754 list_add_tail(&vma->vm_link, &ggtt->base.inactive_list);
ed2f3452
CW		 2755 }
2756
ed2f3452 2757 /* Clear any non-preallocated blocks */
72e96d64 2758 drm_mm_for_each_hole(entry, &ggtt->base.mm, hole_start, hole_end) {
ed2f3452
CW		 2759 DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
2760 hole_start, hole_end);
72e96d64 2761 ggtt->base.clear_range(&ggtt->base, hole_start,
782f1495 2762 hole_end - hole_start, true);
ed2f3452
CW		 2763 }
2764
2765 /* And finally clear the reserved guard page */
72e96d64 2766 ggtt->base.clear_range(&ggtt->base, end - PAGE_SIZE, PAGE_SIZE, true);
6c5566a8 2767
fa76da34
DV		 2768 if (USES_PPGTT(dev) && !USES_FULL_PPGTT(dev)) {
2769 struct i915_hw_ppgtt *ppgtt;
2770
2771 ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
2772 if (!ppgtt)
2773 return -ENOMEM;
2774
5c5f6457
DV		 2775 ret = __hw_ppgtt_init(dev, ppgtt);
2776 if (ret) {
2777 ppgtt->base.cleanup(&ppgtt->base);
2778 kfree(ppgtt);
2779 return ret;
2780 }
2781
2782 if (ppgtt->base.allocate_va_range)
2783 ret = ppgtt->base.allocate_va_range(&ppgtt->base, 0,
2784 ppgtt->base.total);
4933d519 2785 if (ret) {
061dd493 2786 ppgtt->base.cleanup(&ppgtt->base);
4933d519 2787 kfree(ppgtt);
fa76da34 2788 return ret;
4933d519 2789 }
fa76da34 2790
5c5f6457
DV		 2791 ppgtt->base.clear_range(&ppgtt->base,
2792 ppgtt->base.start,
2793 ppgtt->base.total,
2794 true);
2795
fa76da34 2796 dev_priv->mm.aliasing_ppgtt = ppgtt;
72e96d64
JL		 2797 WARN_ON(ggtt->base.bind_vma != ggtt_bind_vma);
2798 ggtt->base.bind_vma = aliasing_gtt_bind_vma;
fa76da34
DV		 2799 }
2800
6c5566a8 2801 return 0;
e76e9aeb
BW		 2802}
2803
d85489d3
JL		 2804/**
2805 * i915_gem_init_ggtt - Initialize GEM for Global GTT
2806 * @dev: DRM device
2807 */
2808void i915_gem_init_ggtt(struct drm_device *dev)
d7e5008f 2809{
72e96d64
JL		 2810 struct drm_i915_private *dev_priv = to_i915(dev);
2811 struct i915_ggtt *ggtt = &dev_priv->ggtt;
d7e5008f 2812
72e96d64 2813 i915_gem_setup_global_gtt(dev, 0, ggtt->mappable_end, ggtt->base.total);
e76e9aeb
BW		 2814}
2815
d85489d3
JL		 2816/**
2817 * i915_ggtt_cleanup_hw - Clean up GGTT hardware initialization
2818 * @dev: DRM device
2819 */
2820void i915_ggtt_cleanup_hw(struct drm_device *dev)
90d0a0e8 2821{
72e96d64
JL		 2822 struct drm_i915_private *dev_priv = to_i915(dev);
2823 struct i915_ggtt *ggtt = &dev_priv->ggtt;
90d0a0e8 2824
70e32544
DV		 2825 if (dev_priv->mm.aliasing_ppgtt) {
2826 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2827
2828 ppgtt->base.cleanup(&ppgtt->base);
2829 }
2830
a4eba47b
ID		 2831 i915_gem_cleanup_stolen(dev);
2832
72e96d64 2833 if (drm_mm_initialized(&ggtt->base.mm)) {
5dda8fa3
YZ		 2834 if (intel_vgpu_active(dev))
2835 intel_vgt_deballoon();
2836
72e96d64
JL		 2837 drm_mm_takedown(&ggtt->base.mm);
2838 list_del(&ggtt->base.global_link);
90d0a0e8
DV		 2839 }
2840
72e96d64 2841 ggtt->base.cleanup(&ggtt->base);
90d0a0e8 2842}
70e32544 2843
2c642b07 2844static unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl)
e76e9aeb
BW		 2845{
2846 snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT;
2847 snb_gmch_ctl &= SNB_GMCH_GGMS_MASK;
2848 return snb_gmch_ctl << 20;
2849}
2850
2c642b07 2851static unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl)
9459d252
BW		 2852{
2853 bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT;
2854 bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK;
2855 if (bdw_gmch_ctl)
2856 bdw_gmch_ctl = 1 << bdw_gmch_ctl;
562d55d9
BW		 2857
2858#ifdef CONFIG_X86_32
2859 /* Limit 32b platforms to a 2GB GGTT: 4 << 20 / pte size * PAGE_SIZE */
2860 if (bdw_gmch_ctl > 4)
2861 bdw_gmch_ctl = 4;
2862#endif
2863
9459d252
BW		 2864 return bdw_gmch_ctl << 20;
2865}
2866
2c642b07 2867static unsigned int chv_get_total_gtt_size(u16 gmch_ctrl)
d7f25f23
DL		 2868{
2869 gmch_ctrl >>= SNB_GMCH_GGMS_SHIFT;
2870 gmch_ctrl &= SNB_GMCH_GGMS_MASK;
2871
2872 if (gmch_ctrl)
2873 return 1 << (20 + gmch_ctrl);
2874
2875 return 0;
2876}
2877
2c642b07 2878static size_t gen6_get_stolen_size(u16 snb_gmch_ctl)
e76e9aeb
BW		 2879{
2880 snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT;
2881 snb_gmch_ctl &= SNB_GMCH_GMS_MASK;
2882 return snb_gmch_ctl << 25; /* 32 MB units */
2883}
2884
2c642b07 2885static size_t gen8_get_stolen_size(u16 bdw_gmch_ctl)
9459d252
BW		 2886{
2887 bdw_gmch_ctl >>= BDW_GMCH_GMS_SHIFT;
2888 bdw_gmch_ctl &= BDW_GMCH_GMS_MASK;
2889 return bdw_gmch_ctl << 25; /* 32 MB units */
2890}
2891
d7f25f23
DL		 2892static size_t chv_get_stolen_size(u16 gmch_ctrl)
2893{
2894 gmch_ctrl >>= SNB_GMCH_GMS_SHIFT;
2895 gmch_ctrl &= SNB_GMCH_GMS_MASK;
2896
2897 /*
2898 * 0x0 to 0x10: 32MB increments starting at 0MB
2899 * 0x11 to 0x16: 4MB increments starting at 8MB
2900 * 0x17 to 0x1d: 4MB increments start at 36MB
2901 */
2902 if (gmch_ctrl < 0x11)
2903 return gmch_ctrl << 25;
2904 else if (gmch_ctrl < 0x17)
2905 return (gmch_ctrl - 0x11 + 2) << 22;
2906 else
2907 return (gmch_ctrl - 0x17 + 9) << 22;
2908}
2909
66375014
DL		 2910static size_t gen9_get_stolen_size(u16 gen9_gmch_ctl)
2911{
2912 gen9_gmch_ctl >>= BDW_GMCH_GMS_SHIFT;
2913 gen9_gmch_ctl &= BDW_GMCH_GMS_MASK;
2914
2915 if (gen9_gmch_ctl < 0xf0)
2916 return gen9_gmch_ctl << 25; /* 32 MB units */
2917 else
2918 /* 4MB increments starting at 0xf0 for 4MB */
2919 return (gen9_gmch_ctl - 0xf0 + 1) << 22;
2920}
2921
63340133
BW		 2922static int ggtt_probe_common(struct drm_device *dev,
2923 size_t gtt_size)
2924{
72e96d64
JL		 2925 struct drm_i915_private *dev_priv = to_i915(dev);
2926 struct i915_ggtt *ggtt = &dev_priv->ggtt;
4ad2af1e 2927 struct i915_page_scratch *scratch_page;
72e96d64 2928 phys_addr_t ggtt_phys_addr;
63340133
BW		 2929
2930 /* For Modern GENs the PTEs and register space are split in the BAR */
72e96d64
JL		 2931 ggtt_phys_addr = pci_resource_start(dev->pdev, 0) +
2932 (pci_resource_len(dev->pdev, 0) / 2);
63340133 2933
2a073f89
ID		 2934 /*
2935 * On BXT writes larger than 64 bit to the GTT pagetable range will be
2936 * dropped. For WC mappings in general we have 64 byte burst writes
2937 * when the WC buffer is flushed, so we can't use it, but have to
2938 * resort to an uncached mapping. The WC issue is easily caught by the
2939 * readback check when writing GTT PTE entries.
2940 */
2941 if (IS_BROXTON(dev))
72e96d64 2942 ggtt->gsm = ioremap_nocache(ggtt_phys_addr, gtt_size);
2a073f89 2943 else
72e96d64
JL		 2944 ggtt->gsm = ioremap_wc(ggtt_phys_addr, gtt_size);
2945 if (!ggtt->gsm) {
63340133
BW		 2946 DRM_ERROR("Failed to map the gtt page table\n");
2947 return -ENOMEM;
2948 }
2949
4ad2af1e
MK		 2950 scratch_page = alloc_scratch_page(dev);
2951 if (IS_ERR(scratch_page)) {
63340133
BW		 2952 DRM_ERROR("Scratch setup failed\n");
2953 /* iounmap will also get called at remove, but meh */
72e96d64 2954 iounmap(ggtt->gsm);
4ad2af1e 2955 return PTR_ERR(scratch_page);
63340133
BW		 2956 }
2957
72e96d64 2958 ggtt->base.scratch_page = scratch_page;
4ad2af1e
MK		 2959
2960 return 0;
63340133
BW		 2961}
2962
fbe5d36e
BW		 2963/* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability
2964 * bits. When using advanced contexts each context stores its own PAT, but
2965 * writing this data shouldn't be harmful even in those cases. */
ee0ce478 2966static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv)
fbe5d36e 2967{
fbe5d36e
BW		 2968 uint64_t pat;
2969
2970 pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC) | /* for normal objects, no eLLC */
2971 GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something pointing to ptes? */
2972 GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC) | /* for scanout with eLLC */
2973 GEN8_PPAT(3, GEN8_PPAT_UC) | /* Uncached objects, mostly for scanout */
2974 GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) |
2975 GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) |
2976 GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) |
2977 GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3));
2978
2d1fe073 2979 if (!USES_PPGTT(dev_priv))
d6a8b72e
RV		 2980 /* Spec: "For GGTT, there is NO pat_sel[2:0] from the entry,
2981 * so RTL will always use the value corresponding to
2982 * pat_sel = 000".
2983 * So let's disable cache for GGTT to avoid screen corruptions.
2984 * MOCS still can be used though.
2985 * - System agent ggtt writes (i.e. cpu gtt mmaps) already work
2986 * before this patch, i.e. the same uncached + snooping access
2987 * like on gen6/7 seems to be in effect.
2988 * - So this just fixes blitter/render access. Again it looks
2989 * like it's not just uncached access, but uncached + snooping.
2990 * So we can still hold onto all our assumptions wrt cpu
2991 * clflushing on LLC machines.
2992 */
2993 pat = GEN8_PPAT(0, GEN8_PPAT_UC);
2994
fbe5d36e
BW		 2995 /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b
2996 * write would work. */
7e435ad2
VS		 2997 I915_WRITE(GEN8_PRIVATE_PAT_LO, pat);
2998 I915_WRITE(GEN8_PRIVATE_PAT_HI, pat >> 32);
fbe5d36e
BW		 2999}
3000
ee0ce478
VS		 3001static void chv_setup_private_ppat(struct drm_i915_private *dev_priv)
3002{
3003 uint64_t pat;
3004
3005 /*
3006 * Map WB on BDW to snooped on CHV.
3007 *
3008 * Only the snoop bit has meaning for CHV, the rest is
3009 * ignored.
3010 *
cf3d262e
VS		 3011 * The hardware will never snoop for certain types of accesses:
3012 * - CPU GTT (GMADR->GGTT->no snoop->memory)
3013 * - PPGTT page tables
3014 * - some other special cycles
3015 *
3016 * As with BDW, we also need to consider the following for GT accesses:
3017 * "For GGTT, there is NO pat_sel[2:0] from the entry,
3018 * so RTL will always use the value corresponding to
3019 * pat_sel = 000".
3020 * Which means we must set the snoop bit in PAT entry 0
3021 * in order to keep the global status page working.
ee0ce478
VS		 3022 */
3023 pat = GEN8_PPAT(0, CHV_PPAT_SNOOP) |
3024 GEN8_PPAT(1, 0) |
3025 GEN8_PPAT(2, 0) |
3026 GEN8_PPAT(3, 0) |
3027 GEN8_PPAT(4, CHV_PPAT_SNOOP) |
3028 GEN8_PPAT(5, CHV_PPAT_SNOOP) |
3029 GEN8_PPAT(6, CHV_PPAT_SNOOP) |
3030 GEN8_PPAT(7, CHV_PPAT_SNOOP);
3031
7e435ad2
VS		 3032 I915_WRITE(GEN8_PRIVATE_PAT_LO, pat);
3033 I915_WRITE(GEN8_PRIVATE_PAT_HI, pat >> 32);
ee0ce478
VS		 3034}
3035
d507d735 3036static int gen8_gmch_probe(struct i915_ggtt *ggtt)
63340133 3037{
d507d735 3038 struct drm_device *dev = ggtt->base.dev;
72e96d64 3039 struct drm_i915_private *dev_priv = to_i915(dev);
63340133
BW		 3040 u16 snb_gmch_ctl;
3041 int ret;
3042
3043 /* TODO: We're not aware of mappable constraints on gen8 yet */
d507d735
JL		 3044 ggtt->mappable_base = pci_resource_start(dev->pdev, 2);
3045 ggtt->mappable_end = pci_resource_len(dev->pdev, 2);
63340133
BW		 3046
3047 if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(39)))
3048 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(39));
3049
3050 pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
3051
66375014 3052 if (INTEL_INFO(dev)->gen >= 9) {
d507d735
JL		 3053 ggtt->stolen_size = gen9_get_stolen_size(snb_gmch_ctl);
3054 ggtt->size = gen8_get_total_gtt_size(snb_gmch_ctl);
66375014 3055 } else if (IS_CHERRYVIEW(dev)) {
d507d735
JL		 3056 ggtt->stolen_size = chv_get_stolen_size(snb_gmch_ctl);
3057 ggtt->size = chv_get_total_gtt_size(snb_gmch_ctl);
d7f25f23 3058 } else {
d507d735
JL		 3059 ggtt->stolen_size = gen8_get_stolen_size(snb_gmch_ctl);
3060 ggtt->size = gen8_get_total_gtt_size(snb_gmch_ctl);
d7f25f23 3061 }
63340133 3062
d507d735 3063 ggtt->base.total = (ggtt->size / sizeof(gen8_pte_t)) << PAGE_SHIFT;
63340133 3064
5a4e33a3 3065 if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev))
ee0ce478
VS		 3066 chv_setup_private_ppat(dev_priv);
3067 else
3068 bdw_setup_private_ppat(dev_priv);
fbe5d36e 3069
d507d735 3070 ret = ggtt_probe_common(dev, ggtt->size);
63340133 3071
d507d735 3072 ggtt->base.clear_range = gen8_ggtt_clear_range;
c140330b 3073 if (IS_CHERRYVIEW(dev_priv))
d507d735
JL		 3074 ggtt->base.insert_entries = gen8_ggtt_insert_entries__BKL;
3075 else
3076 ggtt->base.insert_entries = gen8_ggtt_insert_entries;
3077 ggtt->base.bind_vma = ggtt_bind_vma;
3078 ggtt->base.unbind_vma = ggtt_unbind_vma;
3079
63340133
BW		 3080 return ret;
3081}
3082
d507d735 3083static int gen6_gmch_probe(struct i915_ggtt *ggtt)
e76e9aeb 3084{
d507d735 3085 struct drm_device *dev = ggtt->base.dev;
e76e9aeb 3086 u16 snb_gmch_ctl;
e76e9aeb
BW		 3087 int ret;
3088
d507d735
JL		 3089 ggtt->mappable_base = pci_resource_start(dev->pdev, 2);
3090 ggtt->mappable_end = pci_resource_len(dev->pdev, 2);
41907ddc 3091
baa09f5f
BW		 3092 /* 64/512MB is the current min/max we actually know of, but this is just
3093 * a coarse sanity check.
e76e9aeb 3094 */
d507d735
JL		 3095 if ((ggtt->mappable_end < (64<<20) || (ggtt->mappable_end > (512<<20)))) {
3096 DRM_ERROR("Unknown GMADR size (%llx)\n", ggtt->mappable_end);
baa09f5f 3097 return -ENXIO;
e76e9aeb
BW		 3098 }
3099
e76e9aeb
BW		 3100 if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40)))
3101 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40));
e76e9aeb 3102 pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
e76e9aeb 3103
d507d735
JL		 3104 ggtt->stolen_size = gen6_get_stolen_size(snb_gmch_ctl);
3105 ggtt->size = gen6_get_total_gtt_size(snb_gmch_ctl);
3106 ggtt->base.total = (ggtt->size / sizeof(gen6_pte_t)) << PAGE_SHIFT;
e76e9aeb 3107
d507d735 3108 ret = ggtt_probe_common(dev, ggtt->size);
e76e9aeb 3109
d507d735
JL		 3110 ggtt->base.clear_range = gen6_ggtt_clear_range;
3111 ggtt->base.insert_entries = gen6_ggtt_insert_entries;
3112 ggtt->base.bind_vma = ggtt_bind_vma;
3113 ggtt->base.unbind_vma = ggtt_unbind_vma;
7faf1ab2 3114
e76e9aeb
BW		 3115 return ret;
3116}
3117
853ba5d2 3118static void gen6_gmch_remove(struct i915_address_space *vm)
e76e9aeb 3119{
62106b4f 3120 struct i915_ggtt *ggtt = container_of(vm, struct i915_ggtt, base);
853ba5d2 3121
62106b4f 3122 iounmap(ggtt->gsm);
4ad2af1e 3123 free_scratch_page(vm->dev, vm->scratch_page);
644ec02b 3124}
baa09f5f 3125
d507d735 3126static int i915_gmch_probe(struct i915_ggtt *ggtt)
baa09f5f 3127{
d507d735 3128 struct drm_device *dev = ggtt->base.dev;
72e96d64 3129 struct drm_i915_private *dev_priv = to_i915(dev);
baa09f5f
BW		 3130 int ret;
3131
baa09f5f
BW		 3132 ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->dev->pdev, NULL);
3133 if (!ret) {
3134 DRM_ERROR("failed to set up gmch\n");
3135 return -EIO;
3136 }
3137
d507d735
JL		 3138 intel_gtt_get(&ggtt->base.total, &ggtt->stolen_size,
3139 &ggtt->mappable_base, &ggtt->mappable_end);
baa09f5f 3140
d507d735
JL		 3141 ggtt->do_idle_maps = needs_idle_maps(dev_priv->dev);
3142 ggtt->base.insert_entries = i915_ggtt_insert_entries;
3143 ggtt->base.clear_range = i915_ggtt_clear_range;
3144 ggtt->base.bind_vma = ggtt_bind_vma;
3145 ggtt->base.unbind_vma = ggtt_unbind_vma;
baa09f5f 3146
d507d735 3147 if (unlikely(ggtt->do_idle_maps))
c0a7f818
CW		 3148 DRM_INFO("applying Ironlake quirks for intel_iommu\n");
3149
baa09f5f
BW		 3150 return 0;
3151}
3152
853ba5d2 3153static void i915_gmch_remove(struct i915_address_space *vm)
baa09f5f
BW		 3154{
3155 intel_gmch_remove();
3156}
3157
d85489d3
JL		 3158/**
3159 * i915_ggtt_init_hw - Initialize GGTT hardware
3160 * @dev: DRM device
3161 */
3162int i915_ggtt_init_hw(struct drm_device *dev)
baa09f5f 3163{
72e96d64 3164 struct drm_i915_private *dev_priv = to_i915(dev);
62106b4f 3165 struct i915_ggtt *ggtt = &dev_priv->ggtt;
baa09f5f
BW		 3166 int ret;
3167
baa09f5f 3168 if (INTEL_INFO(dev)->gen <= 5) {
62106b4f
JL		 3169 ggtt->probe = i915_gmch_probe;
3170 ggtt->base.cleanup = i915_gmch_remove;
63340133 3171 } else if (INTEL_INFO(dev)->gen < 8) {
62106b4f
JL		 3172 ggtt->probe = gen6_gmch_probe;
3173 ggtt->base.cleanup = gen6_gmch_remove;
3accaf7e
MK		 3174
3175 if (HAS_EDRAM(dev))
62106b4f 3176 ggtt->base.pte_encode = iris_pte_encode;
4d15c145 3177 else if (IS_HASWELL(dev))
62106b4f 3178 ggtt->base.pte_encode = hsw_pte_encode;
b2f21b4d 3179 else if (IS_VALLEYVIEW(dev))
62106b4f 3180 ggtt->base.pte_encode = byt_pte_encode;
350ec881 3181 else if (INTEL_INFO(dev)->gen >= 7)
62106b4f 3182 ggtt->base.pte_encode = ivb_pte_encode;
b2f21b4d 3183 else
62106b4f 3184 ggtt->base.pte_encode = snb_pte_encode;
63340133 3185 } else {
62106b4f
JL		 3186 ggtt->probe = gen8_gmch_probe;
3187 ggtt->base.cleanup = gen6_gmch_remove;
baa09f5f
BW		 3188 }
3189
62106b4f
JL		 3190 ggtt->base.dev = dev;
3191 ggtt->base.is_ggtt = true;
c114f76a 3192
d507d735 3193 ret = ggtt->probe(ggtt);
a54c0c27 3194 if (ret)
baa09f5f 3195 return ret;
baa09f5f 3196
c890e2d5
CW		 3197 if ((ggtt->base.total - 1) >> 32) {
3198 DRM_ERROR("We never expected a Global GTT with more than 32bits"
3199 "of address space! Found %lldM!\n",
3200 ggtt->base.total >> 20);
3201 ggtt->base.total = 1ULL << 32;
3202 ggtt->mappable_end = min(ggtt->mappable_end, ggtt->base.total);
3203 }
3204
a4eba47b
ID		 3205 /*
3206 * Initialise stolen early so that we may reserve preallocated
3207 * objects for the BIOS to KMS transition.
3208 */
3209 ret = i915_gem_init_stolen(dev);
3210 if (ret)
3211 goto out_gtt_cleanup;
3212
baa09f5f 3213 /* GMADR is the PCI mmio aperture into the global GTT. */
c44ef60e 3214 DRM_INFO("Memory usable by graphics device = %lluM\n",
62106b4f
JL		 3215 ggtt->base.total >> 20);
3216 DRM_DEBUG_DRIVER("GMADR size = %lldM\n", ggtt->mappable_end >> 20);
3217 DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", ggtt->stolen_size >> 20);
5db6c735
DV		 3218#ifdef CONFIG_INTEL_IOMMU
3219 if (intel_iommu_gfx_mapped)
3220 DRM_INFO("VT-d active for gfx access\n");
3221#endif
cfa7c862
DV		 3222 /*
3223 * i915.enable_ppgtt is read-only, so do an early pass to validate the
3224 * user's requested state against the hardware/driver capabilities. We
3225 * do this now so that we can print out any log messages once rather
3226 * than every time we check intel_enable_ppgtt().
3227 */
3228 i915.enable_ppgtt = sanitize_enable_ppgtt(dev, i915.enable_ppgtt);
3229 DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915.enable_ppgtt);
baa09f5f
BW		 3230
3231 return 0;
a4eba47b
ID		 3232
3233out_gtt_cleanup:
72e96d64 3234 ggtt->base.cleanup(&ggtt->base);
a4eba47b
ID		 3235
3236 return ret;
baa09f5f 3237}
6f65e29a 3238
fa42331b
DV		 3239void i915_gem_restore_gtt_mappings(struct drm_device *dev)
3240{
72e96d64
JL		 3241 struct drm_i915_private *dev_priv = to_i915(dev);
3242 struct i915_ggtt *ggtt = &dev_priv->ggtt;
fa42331b 3243 struct drm_i915_gem_object *obj;
2c3d9984
TU		 3244 struct i915_vma *vma;
3245 bool flush;
fa42331b
DV		 3246
3247 i915_check_and_clear_faults(dev);
3248
3249 /* First fill our portion of the GTT with scratch pages */
72e96d64
JL		 3250 ggtt->base.clear_range(&ggtt->base, ggtt->base.start, ggtt->base.total,
3251 true);
fa42331b 3252
2c3d9984 3253 /* Cache flush objects bound into GGTT and rebind them. */
fa42331b 3254 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
2c3d9984 3255 flush = false;
1c7f4bca 3256 list_for_each_entry(vma, &obj->vma_list, obj_link) {
72e96d64 3257 if (vma->vm != &ggtt->base)
2c3d9984 3258 continue;
fa42331b 3259
2c3d9984
TU		 3260 WARN_ON(i915_vma_bind(vma, obj->cache_level,
3261 PIN_UPDATE));
fa42331b 3262
2c3d9984
TU		 3263 flush = true;
3264 }
3265
3266 if (flush)
3267 i915_gem_clflush_object(obj, obj->pin_display);
3268 }
fa42331b
DV		 3269
3270 if (INTEL_INFO(dev)->gen >= 8) {
3271 if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev))
3272 chv_setup_private_ppat(dev_priv);
3273 else
3274 bdw_setup_private_ppat(dev_priv);
3275
3276 return;
3277 }
3278
3279 if (USES_PPGTT(dev)) {
72e96d64
JL		 3280 struct i915_address_space *vm;
3281
fa42331b
DV		 3282 list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
3283 /* TODO: Perhaps it shouldn't be gen6 specific */
3284
e5716f55 3285 struct i915_hw_ppgtt *ppgtt;
fa42331b 3286
e5716f55 3287 if (vm->is_ggtt)
fa42331b 3288 ppgtt = dev_priv->mm.aliasing_ppgtt;
e5716f55
JL		 3289 else
3290 ppgtt = i915_vm_to_ppgtt(vm);
fa42331b
DV		 3291
3292 gen6_write_page_range(dev_priv, &ppgtt->pd,
3293 0, ppgtt->base.total);
3294 }
3295 }
3296
3297 i915_ggtt_flush(dev_priv);
3298}
3299
ec7adb6e
JL		 3300static struct i915_vma *
3301__i915_gem_vma_create(struct drm_i915_gem_object *obj,
3302 struct i915_address_space *vm,
3303 const struct i915_ggtt_view *ggtt_view)
6f65e29a 3304{
dabde5c7 3305 struct i915_vma *vma;
6f65e29a 3306
ec7adb6e
JL		 3307 if (WARN_ON(i915_is_ggtt(vm) != !!ggtt_view))
3308 return ERR_PTR(-EINVAL);
e20d2ab7
CW		 3309
3310 vma = kmem_cache_zalloc(to_i915(obj->base.dev)->vmas, GFP_KERNEL);
dabde5c7
DC		 3311 if (vma == NULL)
3312 return ERR_PTR(-ENOMEM);
ec7adb6e 3313
1c7f4bca
CW		 3314 INIT_LIST_HEAD(&vma->vm_link);
3315 INIT_LIST_HEAD(&vma->obj_link);
6f65e29a
BW		 3316 INIT_LIST_HEAD(&vma->exec_list);
3317 vma->vm = vm;
3318 vma->obj = obj;
596c5923 3319 vma->is_ggtt = i915_is_ggtt(vm);
6f65e29a 3320
777dc5bb 3321 if (i915_is_ggtt(vm))
ec7adb6e 3322 vma->ggtt_view = *ggtt_view;
596c5923
CW		 3323 else
3324 i915_ppgtt_get(i915_vm_to_ppgtt(vm));
6f65e29a 3325
1c7f4bca 3326 list_add_tail(&vma->obj_link, &obj->vma_list);
6f65e29a
BW		 3327
3328 return vma;
3329}
3330
3331struct i915_vma *
ec7adb6e
JL		 3332i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
3333 struct i915_address_space *vm)
3334{
3335 struct i915_vma *vma;
3336
3337 vma = i915_gem_obj_to_vma(obj, vm);
3338 if (!vma)
3339 vma = __i915_gem_vma_create(obj, vm,
3340 i915_is_ggtt(vm) ? &i915_ggtt_view_normal : NULL);
3341
3342 return vma;
3343}
3344
3345struct i915_vma *
3346i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object *obj,
fe14d5f4 3347 const struct i915_ggtt_view *view)
6f65e29a 3348{
72e96d64
JL		 3349 struct drm_device *dev = obj->base.dev;
3350 struct drm_i915_private *dev_priv = to_i915(dev);
3351 struct i915_ggtt *ggtt = &dev_priv->ggtt;
ade7daa1 3352 struct i915_vma *vma = i915_gem_obj_to_ggtt_view(obj, view);
ec7adb6e 3353
6f65e29a 3354 if (!vma)
72e96d64 3355 vma = __i915_gem_vma_create(obj, &ggtt->base, view);
6f65e29a
BW		 3356
3357 return vma;
ec7adb6e 3358
6f65e29a 3359}
fe14d5f4 3360
804beb4b 3361static struct scatterlist *
2d7f3bdb 3362rotate_pages(const dma_addr_t *in, unsigned int offset,
804beb4b 3363 unsigned int width, unsigned int height,
87130255 3364 unsigned int stride,
804beb4b 3365 struct sg_table *st, struct scatterlist *sg)
50470bb0
TU		 3366{
3367 unsigned int column, row;
3368 unsigned int src_idx;
50470bb0 3369
50470bb0 3370 for (column = 0; column < width; column++) {
87130255 3371 src_idx = stride * (height - 1) + column;
50470bb0
TU		 3372 for (row = 0; row < height; row++) {
3373 st->nents++;
3374 /* We don't need the pages, but need to initialize
3375 * the entries so the sg list can be happily traversed.
3376 * The only thing we need are DMA addresses.
3377 */
3378 sg_set_page(sg, NULL, PAGE_SIZE, 0);
804beb4b 3379 sg_dma_address(sg) = in[offset + src_idx];
50470bb0
TU		 3380 sg_dma_len(sg) = PAGE_SIZE;
3381 sg = sg_next(sg);
87130255 3382 src_idx -= stride;
50470bb0
TU		 3383 }
3384 }
804beb4b
TU		 3385
3386 return sg;
50470bb0
TU		 3387}
3388
3389static struct sg_table *
11d23e6f 3390intel_rotate_fb_obj_pages(struct intel_rotation_info *rot_info,
50470bb0
TU		 3391 struct drm_i915_gem_object *obj)
3392{
1663b9d6 3393 unsigned int size_pages = rot_info->plane[0].width * rot_info->plane[0].height;
89e3e142 3394 unsigned int size_pages_uv;
50470bb0
TU		 3395 struct sg_page_iter sg_iter;
3396 unsigned long i;
3397 dma_addr_t *page_addr_list;
3398 struct sg_table *st;
89e3e142
TU		 3399 unsigned int uv_start_page;
3400 struct scatterlist *sg;
1d00dad5 3401 int ret = -ENOMEM;
50470bb0 3402
50470bb0 3403 /* Allocate a temporary list of source pages for random access. */
f2a85e19
CW		 3404 page_addr_list = drm_malloc_gfp(obj->base.size / PAGE_SIZE,
3405 sizeof(dma_addr_t),
3406 GFP_TEMPORARY);
50470bb0
TU		 3407 if (!page_addr_list)
3408 return ERR_PTR(ret);
3409
89e3e142
TU		 3410 /* Account for UV plane with NV12. */
3411 if (rot_info->pixel_format == DRM_FORMAT_NV12)
1663b9d6 3412 size_pages_uv = rot_info->plane[1].width * rot_info->plane[1].height;
89e3e142
TU		 3413 else
3414 size_pages_uv = 0;
3415
50470bb0
TU		 3416 /* Allocate target SG list. */
3417 st = kmalloc(sizeof(*st), GFP_KERNEL);
3418 if (!st)
3419 goto err_st_alloc;
3420
89e3e142 3421 ret = sg_alloc_table(st, size_pages + size_pages_uv, GFP_KERNEL);
50470bb0
TU		 3422 if (ret)
3423 goto err_sg_alloc;
3424
3425 /* Populate source page list from the object. */
3426 i = 0;
3427 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
3428 page_addr_list[i] = sg_page_iter_dma_address(&sg_iter);
3429 i++;
3430 }
3431
11f20322
VS		 3432 st->nents = 0;
3433 sg = st->sgl;
3434
50470bb0 3435 /* Rotate the pages. */
89e3e142 3436 sg = rotate_pages(page_addr_list, 0,
1663b9d6
VS		 3437 rot_info->plane[0].width, rot_info->plane[0].height,
3438 rot_info->plane[0].width,
11f20322 3439 st, sg);
50470bb0 3440
89e3e142
TU		 3441 /* Append the UV plane if NV12. */
3442 if (rot_info->pixel_format == DRM_FORMAT_NV12) {
3443 uv_start_page = size_pages;
3444
3445 /* Check for tile-row un-alignment. */
3446 if (offset_in_page(rot_info->uv_offset))
3447 uv_start_page--;
3448
dedf278c
TU		 3449 rot_info->uv_start_page = uv_start_page;
3450
11f20322
VS		 3451 sg = rotate_pages(page_addr_list, rot_info->uv_start_page,
3452 rot_info->plane[1].width, rot_info->plane[1].height,
3453 rot_info->plane[1].width,
3454 st, sg);
89e3e142
TU		 3455 }
3456
1663b9d6
VS		 3457 DRM_DEBUG_KMS("Created rotated page mapping for object size %zu (%ux%u tiles, %u pages (%u plane 0)).\n",
3458 obj->base.size, rot_info->plane[0].width,
3459 rot_info->plane[0].height, size_pages + size_pages_uv,
89e3e142 3460 size_pages);
50470bb0
TU		 3461
3462 drm_free_large(page_addr_list);
3463
3464 return st;
3465
3466err_sg_alloc:
3467 kfree(st);
3468err_st_alloc:
3469 drm_free_large(page_addr_list);
3470
1663b9d6
VS		 3471 DRM_DEBUG_KMS("Failed to create rotated mapping for object size %zu! (%d) (%ux%u tiles, %u pages (%u plane 0))\n",
3472 obj->base.size, ret, rot_info->plane[0].width,
3473 rot_info->plane[0].height, size_pages + size_pages_uv,
89e3e142 3474 size_pages);
50470bb0
TU		 3475 return ERR_PTR(ret);
3476}
ec7adb6e 3477
8bd7ef16
JL		 3478static struct sg_table *
3479intel_partial_pages(const struct i915_ggtt_view *view,
3480 struct drm_i915_gem_object *obj)
3481{
3482 struct sg_table *st;
3483 struct scatterlist *sg;
3484 struct sg_page_iter obj_sg_iter;
3485 int ret = -ENOMEM;
3486
3487 st = kmalloc(sizeof(*st), GFP_KERNEL);
3488 if (!st)
3489 goto err_st_alloc;
3490
3491 ret = sg_alloc_table(st, view->params.partial.size, GFP_KERNEL);
3492 if (ret)
3493 goto err_sg_alloc;
3494
3495 sg = st->sgl;
3496 st->nents = 0;
3497 for_each_sg_page(obj->pages->sgl, &obj_sg_iter, obj->pages->nents,
3498 view->params.partial.offset)
3499 {
3500 if (st->nents >= view->params.partial.size)
3501 break;
3502
3503 sg_set_page(sg, NULL, PAGE_SIZE, 0);
3504 sg_dma_address(sg) = sg_page_iter_dma_address(&obj_sg_iter);
3505 sg_dma_len(sg) = PAGE_SIZE;
3506
3507 sg = sg_next(sg);
3508 st->nents++;
3509 }
3510
3511 return st;
3512
3513err_sg_alloc:
3514 kfree(st);
3515err_st_alloc:
3516 return ERR_PTR(ret);
3517}
3518
70b9f6f8 3519static int
50470bb0 3520i915_get_ggtt_vma_pages(struct i915_vma *vma)
fe14d5f4 3521{
50470bb0
TU		 3522 int ret = 0;
3523
fe14d5f4
TU		 3524 if (vma->ggtt_view.pages)
3525 return 0;
3526
3527 if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL)
3528 vma->ggtt_view.pages = vma->obj->pages;
50470bb0
TU		 3529 else if (vma->ggtt_view.type == I915_GGTT_VIEW_ROTATED)
3530 vma->ggtt_view.pages =
11d23e6f 3531 intel_rotate_fb_obj_pages(&vma->ggtt_view.params.rotated, vma->obj);
8bd7ef16
JL		 3532 else if (vma->ggtt_view.type == I915_GGTT_VIEW_PARTIAL)
3533 vma->ggtt_view.pages =
3534 intel_partial_pages(&vma->ggtt_view, vma->obj);
fe14d5f4
TU		 3535 else
3536 WARN_ONCE(1, "GGTT view %u not implemented!\n",
3537 vma->ggtt_view.type);
3538
3539 if (!vma->ggtt_view.pages) {
ec7adb6e 3540 DRM_ERROR("Failed to get pages for GGTT view type %u!\n",
fe14d5f4 3541 vma->ggtt_view.type);
50470bb0
TU		 3542 ret = -EINVAL;
3543 } else if (IS_ERR(vma->ggtt_view.pages)) {
3544 ret = PTR_ERR(vma->ggtt_view.pages);
3545 vma->ggtt_view.pages = NULL;
3546 DRM_ERROR("Failed to get pages for VMA view type %u (%d)!\n",
3547 vma->ggtt_view.type, ret);
fe14d5f4
TU		 3548 }
3549
50470bb0 3550 return ret;
fe14d5f4
TU		 3551}
3552
3553/**
3554 * i915_vma_bind - Sets up PTEs for an VMA in it's corresponding address space.
3555 * @vma: VMA to map
3556 * @cache_level: mapping cache level
3557 * @flags: flags like global or local mapping
3558 *
3559 * DMA addresses are taken from the scatter-gather table of this object (or of
3560 * this VMA in case of non-default GGTT views) and PTE entries set up.
3561 * Note that DMA addresses are also the only part of the SG table we care about.
3562 */
3563int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level,
3564 u32 flags)
3565{
75d04a37
MK		 3566 int ret;
3567 u32 bind_flags;
1d335d1b 3568
75d04a37
MK		 3569 if (WARN_ON(flags == 0))
3570 return -EINVAL;
1d335d1b 3571
75d04a37 3572 bind_flags = 0;
0875546c
DV		 3573 if (flags & PIN_GLOBAL)
3574 bind_flags |= GLOBAL_BIND;
3575 if (flags & PIN_USER)
3576 bind_flags |= LOCAL_BIND;
3577
3578 if (flags & PIN_UPDATE)
3579 bind_flags |= vma->bound;
3580 else
3581 bind_flags &= ~vma->bound;
3582
75d04a37
MK		 3583 if (bind_flags == 0)
3584 return 0;
3585
3586 if (vma->bound == 0 && vma->vm->allocate_va_range) {
b2dd4511
MK		 3587 /* XXX: i915_vma_pin() will fix this +- hack */
3588 vma->pin_count++;
596c5923 3589 trace_i915_va_alloc(vma);
75d04a37
MK		 3590 ret = vma->vm->allocate_va_range(vma->vm,
3591 vma->node.start,
3592 vma->node.size);
b2dd4511 3593 vma->pin_count--;
75d04a37
MK		 3594 if (ret)
3595 return ret;
3596 }
3597
3598 ret = vma->vm->bind_vma(vma, cache_level, bind_flags);
70b9f6f8
DV		 3599 if (ret)
3600 return ret;
0875546c
DV		 3601
3602 vma->bound |= bind_flags;
fe14d5f4
TU		 3603
3604 return 0;
3605}
91e6711e
JL		 3606
3607/**
3608 * i915_ggtt_view_size - Get the size of a GGTT view.
3609 * @obj: Object the view is of.
3610 * @view: The view in question.
3611 *
3612 * @return The size of the GGTT view in bytes.
3613 */
3614size_t
3615i915_ggtt_view_size(struct drm_i915_gem_object *obj,
3616 const struct i915_ggtt_view *view)
3617{
9e759ff1 3618 if (view->type == I915_GGTT_VIEW_NORMAL) {
91e6711e 3619 return obj->base.size;
9e759ff1 3620 } else if (view->type == I915_GGTT_VIEW_ROTATED) {
1663b9d6 3621 return intel_rotation_info_size(&view->params.rotated) << PAGE_SHIFT;
8bd7ef16
JL		 3622 } else if (view->type == I915_GGTT_VIEW_PARTIAL) {
3623 return view->params.partial.size << PAGE_SHIFT;
91e6711e
JL		 3624 } else {
3625 WARN_ONCE(1, "GGTT view %u not implemented!\n", view->type);
3626 return obj->base.size;
3627 }
3628}
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