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76aaf220 DV |
1 | /* |
2 | * Copyright © 2010 Daniel Vetter | |
c4ac524c | 3 | * Copyright © 2011-2014 Intel Corporation |
76aaf220 DV |
4 | * |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
22 | * IN THE SOFTWARE. | |
23 | * | |
24 | */ | |
25 | ||
0e46ce2e | 26 | #include <linux/seq_file.h> |
5bab6f60 | 27 | #include <linux/stop_machine.h> |
760285e7 DH |
28 | #include <drm/drmP.h> |
29 | #include <drm/i915_drm.h> | |
76aaf220 | 30 | #include "i915_drv.h" |
5dda8fa3 | 31 | #include "i915_vgpu.h" |
76aaf220 DV |
32 | #include "i915_trace.h" |
33 | #include "intel_drv.h" | |
d07f0e59 | 34 | #include "intel_frontbuffer.h" |
76aaf220 | 35 | |
bb8f9cff CW |
36 | #define I915_GFP_DMA (GFP_KERNEL | __GFP_HIGHMEM) |
37 | ||
45f8f69a TU |
38 | /** |
39 | * DOC: Global GTT views | |
40 | * | |
41 | * Background and previous state | |
42 | * | |
43 | * Historically objects could exists (be bound) in global GTT space only as | |
44 | * singular instances with a view representing all of the object's backing pages | |
45 | * in a linear fashion. This view will be called a normal view. | |
46 | * | |
47 | * To support multiple views of the same object, where the number of mapped | |
48 | * pages is not equal to the backing store, or where the layout of the pages | |
49 | * is not linear, concept of a GGTT view was added. | |
50 | * | |
51 | * One example of an alternative view is a stereo display driven by a single | |
52 | * image. In this case we would have a framebuffer looking like this | |
53 | * (2x2 pages): | |
54 | * | |
55 | * 12 | |
56 | * 34 | |
57 | * | |
58 | * Above would represent a normal GGTT view as normally mapped for GPU or CPU | |
59 | * rendering. In contrast, fed to the display engine would be an alternative | |
60 | * view which could look something like this: | |
61 | * | |
62 | * 1212 | |
63 | * 3434 | |
64 | * | |
65 | * In this example both the size and layout of pages in the alternative view is | |
66 | * different from the normal view. | |
67 | * | |
68 | * Implementation and usage | |
69 | * | |
70 | * GGTT views are implemented using VMAs and are distinguished via enum | |
71 | * i915_ggtt_view_type and struct i915_ggtt_view. | |
72 | * | |
73 | * A new flavour of core GEM functions which work with GGTT bound objects were | |
ec7adb6e JL |
74 | * added with the _ggtt_ infix, and sometimes with _view postfix to avoid |
75 | * renaming in large amounts of code. They take the struct i915_ggtt_view | |
76 | * parameter encapsulating all metadata required to implement a view. | |
45f8f69a TU |
77 | * |
78 | * As a helper for callers which are only interested in the normal view, | |
79 | * globally const i915_ggtt_view_normal singleton instance exists. All old core | |
80 | * GEM API functions, the ones not taking the view parameter, are operating on, | |
81 | * or with the normal GGTT view. | |
82 | * | |
83 | * Code wanting to add or use a new GGTT view needs to: | |
84 | * | |
85 | * 1. Add a new enum with a suitable name. | |
86 | * 2. Extend the metadata in the i915_ggtt_view structure if required. | |
87 | * 3. Add support to i915_get_vma_pages(). | |
88 | * | |
89 | * New views are required to build a scatter-gather table from within the | |
90 | * i915_get_vma_pages function. This table is stored in the vma.ggtt_view and | |
91 | * exists for the lifetime of an VMA. | |
92 | * | |
93 | * Core API is designed to have copy semantics which means that passed in | |
94 | * struct i915_ggtt_view does not need to be persistent (left around after | |
95 | * calling the core API functions). | |
96 | * | |
97 | */ | |
98 | ||
70b9f6f8 DV |
99 | static int |
100 | i915_get_ggtt_vma_pages(struct i915_vma *vma); | |
101 | ||
b5e16987 VS |
102 | const struct i915_ggtt_view i915_ggtt_view_normal = { |
103 | .type = I915_GGTT_VIEW_NORMAL, | |
104 | }; | |
9abc4648 | 105 | const struct i915_ggtt_view i915_ggtt_view_rotated = { |
b5e16987 | 106 | .type = I915_GGTT_VIEW_ROTATED, |
9abc4648 | 107 | }; |
fe14d5f4 | 108 | |
c033666a CW |
109 | int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv, |
110 | int enable_ppgtt) | |
cfa7c862 | 111 | { |
1893a71b CW |
112 | bool has_aliasing_ppgtt; |
113 | bool has_full_ppgtt; | |
1f9a99e0 | 114 | bool has_full_48bit_ppgtt; |
1893a71b | 115 | |
9e1d0e60 MT |
116 | has_aliasing_ppgtt = dev_priv->info.has_aliasing_ppgtt; |
117 | has_full_ppgtt = dev_priv->info.has_full_ppgtt; | |
118 | has_full_48bit_ppgtt = dev_priv->info.has_full_48bit_ppgtt; | |
1893a71b | 119 | |
e320d400 ZW |
120 | if (intel_vgpu_active(dev_priv)) { |
121 | /* emulation is too hard */ | |
122 | has_full_ppgtt = false; | |
123 | has_full_48bit_ppgtt = false; | |
124 | } | |
71ba2d64 | 125 | |
0e4ca100 CW |
126 | if (!has_aliasing_ppgtt) |
127 | return 0; | |
128 | ||
70ee45e1 DL |
129 | /* |
130 | * We don't allow disabling PPGTT for gen9+ as it's a requirement for | |
131 | * execlists, the sole mechanism available to submit work. | |
132 | */ | |
c033666a | 133 | if (enable_ppgtt == 0 && INTEL_GEN(dev_priv) < 9) |
cfa7c862 DV |
134 | return 0; |
135 | ||
136 | if (enable_ppgtt == 1) | |
137 | return 1; | |
138 | ||
1893a71b | 139 | if (enable_ppgtt == 2 && has_full_ppgtt) |
cfa7c862 DV |
140 | return 2; |
141 | ||
1f9a99e0 MT |
142 | if (enable_ppgtt == 3 && has_full_48bit_ppgtt) |
143 | return 3; | |
144 | ||
93a25a9e DV |
145 | #ifdef CONFIG_INTEL_IOMMU |
146 | /* Disable ppgtt on SNB if VT-d is on. */ | |
c033666a | 147 | if (IS_GEN6(dev_priv) && intel_iommu_gfx_mapped) { |
93a25a9e | 148 | DRM_INFO("Disabling PPGTT because VT-d is on\n"); |
cfa7c862 | 149 | return 0; |
93a25a9e DV |
150 | } |
151 | #endif | |
152 | ||
62942ed7 | 153 | /* Early VLV doesn't have this */ |
91c8a326 | 154 | if (IS_VALLEYVIEW(dev_priv) && dev_priv->drm.pdev->revision < 0xb) { |
62942ed7 JB |
155 | DRM_DEBUG_DRIVER("disabling PPGTT on pre-B3 step VLV\n"); |
156 | return 0; | |
157 | } | |
158 | ||
e320d400 | 159 | if (INTEL_GEN(dev_priv) >= 8 && i915.enable_execlists && has_full_ppgtt) |
1f9a99e0 | 160 | return has_full_48bit_ppgtt ? 3 : 2; |
2f82bbdf MT |
161 | else |
162 | return has_aliasing_ppgtt ? 1 : 0; | |
93a25a9e DV |
163 | } |
164 | ||
70b9f6f8 DV |
165 | static int ppgtt_bind_vma(struct i915_vma *vma, |
166 | enum i915_cache_level cache_level, | |
167 | u32 unused) | |
47552659 DV |
168 | { |
169 | u32 pte_flags = 0; | |
170 | ||
a4f5ea64 | 171 | vma->pages = vma->obj->mm.pages; |
247177dd | 172 | |
47552659 DV |
173 | /* Currently applicable only to VLV */ |
174 | if (vma->obj->gt_ro) | |
175 | pte_flags |= PTE_READ_ONLY; | |
176 | ||
247177dd | 177 | vma->vm->insert_entries(vma->vm, vma->pages, vma->node.start, |
47552659 | 178 | cache_level, pte_flags); |
70b9f6f8 DV |
179 | |
180 | return 0; | |
47552659 DV |
181 | } |
182 | ||
183 | static void ppgtt_unbind_vma(struct i915_vma *vma) | |
184 | { | |
185 | vma->vm->clear_range(vma->vm, | |
186 | vma->node.start, | |
4fb84d99 | 187 | vma->size); |
47552659 | 188 | } |
6f65e29a | 189 | |
2c642b07 | 190 | static gen8_pte_t gen8_pte_encode(dma_addr_t addr, |
4fb84d99 | 191 | enum i915_cache_level level) |
94ec8f61 | 192 | { |
4fb84d99 | 193 | gen8_pte_t pte = _PAGE_PRESENT | _PAGE_RW; |
94ec8f61 | 194 | pte |= addr; |
63c42e56 BW |
195 | |
196 | switch (level) { | |
197 | case I915_CACHE_NONE: | |
fbe5d36e | 198 | pte |= PPAT_UNCACHED_INDEX; |
63c42e56 BW |
199 | break; |
200 | case I915_CACHE_WT: | |
201 | pte |= PPAT_DISPLAY_ELLC_INDEX; | |
202 | break; | |
203 | default: | |
204 | pte |= PPAT_CACHED_INDEX; | |
205 | break; | |
206 | } | |
207 | ||
94ec8f61 BW |
208 | return pte; |
209 | } | |
210 | ||
fe36f55d MK |
211 | static gen8_pde_t gen8_pde_encode(const dma_addr_t addr, |
212 | const enum i915_cache_level level) | |
b1fe6673 | 213 | { |
07749ef3 | 214 | gen8_pde_t pde = _PAGE_PRESENT | _PAGE_RW; |
b1fe6673 BW |
215 | pde |= addr; |
216 | if (level != I915_CACHE_NONE) | |
217 | pde |= PPAT_CACHED_PDE_INDEX; | |
218 | else | |
219 | pde |= PPAT_UNCACHED_INDEX; | |
220 | return pde; | |
221 | } | |
222 | ||
762d9936 MT |
223 | #define gen8_pdpe_encode gen8_pde_encode |
224 | #define gen8_pml4e_encode gen8_pde_encode | |
225 | ||
07749ef3 MT |
226 | static gen6_pte_t snb_pte_encode(dma_addr_t addr, |
227 | enum i915_cache_level level, | |
4fb84d99 | 228 | u32 unused) |
54d12527 | 229 | { |
4fb84d99 | 230 | gen6_pte_t pte = GEN6_PTE_VALID; |
54d12527 | 231 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
e7210c3c BW |
232 | |
233 | switch (level) { | |
350ec881 CW |
234 | case I915_CACHE_L3_LLC: |
235 | case I915_CACHE_LLC: | |
236 | pte |= GEN6_PTE_CACHE_LLC; | |
237 | break; | |
238 | case I915_CACHE_NONE: | |
239 | pte |= GEN6_PTE_UNCACHED; | |
240 | break; | |
241 | default: | |
5f77eeb0 | 242 | MISSING_CASE(level); |
350ec881 CW |
243 | } |
244 | ||
245 | return pte; | |
246 | } | |
247 | ||
07749ef3 MT |
248 | static gen6_pte_t ivb_pte_encode(dma_addr_t addr, |
249 | enum i915_cache_level level, | |
4fb84d99 | 250 | u32 unused) |
350ec881 | 251 | { |
4fb84d99 | 252 | gen6_pte_t pte = GEN6_PTE_VALID; |
350ec881 CW |
253 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
254 | ||
255 | switch (level) { | |
256 | case I915_CACHE_L3_LLC: | |
257 | pte |= GEN7_PTE_CACHE_L3_LLC; | |
e7210c3c BW |
258 | break; |
259 | case I915_CACHE_LLC: | |
260 | pte |= GEN6_PTE_CACHE_LLC; | |
261 | break; | |
262 | case I915_CACHE_NONE: | |
9119708c | 263 | pte |= GEN6_PTE_UNCACHED; |
e7210c3c BW |
264 | break; |
265 | default: | |
5f77eeb0 | 266 | MISSING_CASE(level); |
e7210c3c BW |
267 | } |
268 | ||
54d12527 BW |
269 | return pte; |
270 | } | |
271 | ||
07749ef3 MT |
272 | static gen6_pte_t byt_pte_encode(dma_addr_t addr, |
273 | enum i915_cache_level level, | |
4fb84d99 | 274 | u32 flags) |
93c34e70 | 275 | { |
4fb84d99 | 276 | gen6_pte_t pte = GEN6_PTE_VALID; |
93c34e70 KG |
277 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
278 | ||
24f3a8cf AG |
279 | if (!(flags & PTE_READ_ONLY)) |
280 | pte |= BYT_PTE_WRITEABLE; | |
93c34e70 KG |
281 | |
282 | if (level != I915_CACHE_NONE) | |
283 | pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES; | |
284 | ||
285 | return pte; | |
286 | } | |
287 | ||
07749ef3 MT |
288 | static gen6_pte_t hsw_pte_encode(dma_addr_t addr, |
289 | enum i915_cache_level level, | |
4fb84d99 | 290 | u32 unused) |
9119708c | 291 | { |
4fb84d99 | 292 | gen6_pte_t pte = GEN6_PTE_VALID; |
0d8ff15e | 293 | pte |= HSW_PTE_ADDR_ENCODE(addr); |
9119708c KG |
294 | |
295 | if (level != I915_CACHE_NONE) | |
87a6b688 | 296 | pte |= HSW_WB_LLC_AGE3; |
9119708c KG |
297 | |
298 | return pte; | |
299 | } | |
300 | ||
07749ef3 MT |
301 | static gen6_pte_t iris_pte_encode(dma_addr_t addr, |
302 | enum i915_cache_level level, | |
4fb84d99 | 303 | u32 unused) |
4d15c145 | 304 | { |
4fb84d99 | 305 | gen6_pte_t pte = GEN6_PTE_VALID; |
4d15c145 BW |
306 | pte |= HSW_PTE_ADDR_ENCODE(addr); |
307 | ||
651d794f CW |
308 | switch (level) { |
309 | case I915_CACHE_NONE: | |
310 | break; | |
311 | case I915_CACHE_WT: | |
c51e9701 | 312 | pte |= HSW_WT_ELLC_LLC_AGE3; |
651d794f CW |
313 | break; |
314 | default: | |
c51e9701 | 315 | pte |= HSW_WB_ELLC_LLC_AGE3; |
651d794f CW |
316 | break; |
317 | } | |
4d15c145 BW |
318 | |
319 | return pte; | |
320 | } | |
321 | ||
275a991c | 322 | static int __setup_page_dma(struct drm_i915_private *dev_priv, |
c114f76a | 323 | struct i915_page_dma *p, gfp_t flags) |
678d96fb | 324 | { |
275a991c | 325 | struct device *kdev = &dev_priv->drm.pdev->dev; |
678d96fb | 326 | |
c114f76a | 327 | p->page = alloc_page(flags); |
44159ddb MK |
328 | if (!p->page) |
329 | return -ENOMEM; | |
678d96fb | 330 | |
c49d13ee | 331 | p->daddr = dma_map_page(kdev, |
f51455d4 | 332 | p->page, 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); |
678d96fb | 333 | |
c49d13ee | 334 | if (dma_mapping_error(kdev, p->daddr)) { |
44159ddb MK |
335 | __free_page(p->page); |
336 | return -EINVAL; | |
337 | } | |
1266cdb1 MT |
338 | |
339 | return 0; | |
678d96fb BW |
340 | } |
341 | ||
275a991c TU |
342 | static int setup_page_dma(struct drm_i915_private *dev_priv, |
343 | struct i915_page_dma *p) | |
c114f76a | 344 | { |
275a991c | 345 | return __setup_page_dma(dev_priv, p, I915_GFP_DMA); |
c114f76a MK |
346 | } |
347 | ||
275a991c TU |
348 | static void cleanup_page_dma(struct drm_i915_private *dev_priv, |
349 | struct i915_page_dma *p) | |
06fda602 | 350 | { |
275a991c | 351 | struct pci_dev *pdev = dev_priv->drm.pdev; |
52a05c30 | 352 | |
44159ddb | 353 | if (WARN_ON(!p->page)) |
06fda602 | 354 | return; |
678d96fb | 355 | |
f51455d4 | 356 | dma_unmap_page(&pdev->dev, p->daddr, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); |
44159ddb MK |
357 | __free_page(p->page); |
358 | memset(p, 0, sizeof(*p)); | |
359 | } | |
360 | ||
d1c54acd | 361 | static void *kmap_page_dma(struct i915_page_dma *p) |
73eeea53 | 362 | { |
d1c54acd MK |
363 | return kmap_atomic(p->page); |
364 | } | |
73eeea53 | 365 | |
d1c54acd MK |
366 | /* We use the flushing unmap only with ppgtt structures: |
367 | * page directories, page tables and scratch pages. | |
368 | */ | |
e2d214ae | 369 | static void kunmap_page_dma(struct drm_i915_private *dev_priv, void *vaddr) |
d1c54acd | 370 | { |
73eeea53 MK |
371 | /* There are only few exceptions for gen >=6. chv and bxt. |
372 | * And we are not sure about the latter so play safe for now. | |
373 | */ | |
cc3f90f0 | 374 | if (IS_CHERRYVIEW(dev_priv) || IS_GEN9_LP(dev_priv)) |
73eeea53 MK |
375 | drm_clflush_virt_range(vaddr, PAGE_SIZE); |
376 | ||
377 | kunmap_atomic(vaddr); | |
378 | } | |
379 | ||
567047be | 380 | #define kmap_px(px) kmap_page_dma(px_base(px)) |
e2d214ae | 381 | #define kunmap_px(ppgtt, vaddr) \ |
49d73912 | 382 | kunmap_page_dma((ppgtt)->base.i915, (vaddr)) |
d1c54acd | 383 | |
275a991c TU |
384 | #define setup_px(dev_priv, px) setup_page_dma((dev_priv), px_base(px)) |
385 | #define cleanup_px(dev_priv, px) cleanup_page_dma((dev_priv), px_base(px)) | |
e2d214ae TU |
386 | #define fill_px(dev_priv, px, v) fill_page_dma((dev_priv), px_base(px), (v)) |
387 | #define fill32_px(dev_priv, px, v) \ | |
388 | fill_page_dma_32((dev_priv), px_base(px), (v)) | |
567047be | 389 | |
e2d214ae TU |
390 | static void fill_page_dma(struct drm_i915_private *dev_priv, |
391 | struct i915_page_dma *p, const uint64_t val) | |
d1c54acd MK |
392 | { |
393 | int i; | |
394 | uint64_t * const vaddr = kmap_page_dma(p); | |
395 | ||
396 | for (i = 0; i < 512; i++) | |
397 | vaddr[i] = val; | |
398 | ||
e2d214ae | 399 | kunmap_page_dma(dev_priv, vaddr); |
d1c54acd MK |
400 | } |
401 | ||
e2d214ae TU |
402 | static void fill_page_dma_32(struct drm_i915_private *dev_priv, |
403 | struct i915_page_dma *p, const uint32_t val32) | |
73eeea53 MK |
404 | { |
405 | uint64_t v = val32; | |
406 | ||
407 | v = v << 32 | val32; | |
408 | ||
e2d214ae | 409 | fill_page_dma(dev_priv, p, v); |
73eeea53 MK |
410 | } |
411 | ||
8bcdd0f7 | 412 | static int |
275a991c | 413 | setup_scratch_page(struct drm_i915_private *dev_priv, |
bb8f9cff CW |
414 | struct i915_page_dma *scratch, |
415 | gfp_t gfp) | |
4ad2af1e | 416 | { |
275a991c | 417 | return __setup_page_dma(dev_priv, scratch, gfp | __GFP_ZERO); |
4ad2af1e MK |
418 | } |
419 | ||
275a991c | 420 | static void cleanup_scratch_page(struct drm_i915_private *dev_priv, |
8bcdd0f7 | 421 | struct i915_page_dma *scratch) |
4ad2af1e | 422 | { |
275a991c | 423 | cleanup_page_dma(dev_priv, scratch); |
4ad2af1e MK |
424 | } |
425 | ||
275a991c | 426 | static struct i915_page_table *alloc_pt(struct drm_i915_private *dev_priv) |
06fda602 | 427 | { |
ec565b3c | 428 | struct i915_page_table *pt; |
275a991c | 429 | const size_t count = INTEL_GEN(dev_priv) >= 8 ? GEN8_PTES : GEN6_PTES; |
678d96fb | 430 | int ret = -ENOMEM; |
06fda602 BW |
431 | |
432 | pt = kzalloc(sizeof(*pt), GFP_KERNEL); | |
433 | if (!pt) | |
434 | return ERR_PTR(-ENOMEM); | |
435 | ||
678d96fb BW |
436 | pt->used_ptes = kcalloc(BITS_TO_LONGS(count), sizeof(*pt->used_ptes), |
437 | GFP_KERNEL); | |
438 | ||
439 | if (!pt->used_ptes) | |
440 | goto fail_bitmap; | |
441 | ||
275a991c | 442 | ret = setup_px(dev_priv, pt); |
678d96fb | 443 | if (ret) |
44159ddb | 444 | goto fail_page_m; |
06fda602 BW |
445 | |
446 | return pt; | |
678d96fb | 447 | |
44159ddb | 448 | fail_page_m: |
678d96fb BW |
449 | kfree(pt->used_ptes); |
450 | fail_bitmap: | |
451 | kfree(pt); | |
452 | ||
453 | return ERR_PTR(ret); | |
06fda602 BW |
454 | } |
455 | ||
275a991c TU |
456 | static void free_pt(struct drm_i915_private *dev_priv, |
457 | struct i915_page_table *pt) | |
06fda602 | 458 | { |
275a991c | 459 | cleanup_px(dev_priv, pt); |
2e906bea MK |
460 | kfree(pt->used_ptes); |
461 | kfree(pt); | |
462 | } | |
463 | ||
464 | static void gen8_initialize_pt(struct i915_address_space *vm, | |
465 | struct i915_page_table *pt) | |
466 | { | |
467 | gen8_pte_t scratch_pte; | |
468 | ||
8bcdd0f7 | 469 | scratch_pte = gen8_pte_encode(vm->scratch_page.daddr, |
4fb84d99 | 470 | I915_CACHE_LLC); |
2e906bea | 471 | |
49d73912 | 472 | fill_px(vm->i915, pt, scratch_pte); |
2e906bea MK |
473 | } |
474 | ||
475 | static void gen6_initialize_pt(struct i915_address_space *vm, | |
476 | struct i915_page_table *pt) | |
477 | { | |
478 | gen6_pte_t scratch_pte; | |
479 | ||
8bcdd0f7 | 480 | WARN_ON(vm->scratch_page.daddr == 0); |
2e906bea | 481 | |
8bcdd0f7 | 482 | scratch_pte = vm->pte_encode(vm->scratch_page.daddr, |
4fb84d99 | 483 | I915_CACHE_LLC, 0); |
2e906bea | 484 | |
49d73912 | 485 | fill32_px(vm->i915, pt, scratch_pte); |
06fda602 BW |
486 | } |
487 | ||
275a991c | 488 | static struct i915_page_directory *alloc_pd(struct drm_i915_private *dev_priv) |
06fda602 | 489 | { |
ec565b3c | 490 | struct i915_page_directory *pd; |
33c8819f | 491 | int ret = -ENOMEM; |
06fda602 BW |
492 | |
493 | pd = kzalloc(sizeof(*pd), GFP_KERNEL); | |
494 | if (!pd) | |
495 | return ERR_PTR(-ENOMEM); | |
496 | ||
33c8819f MT |
497 | pd->used_pdes = kcalloc(BITS_TO_LONGS(I915_PDES), |
498 | sizeof(*pd->used_pdes), GFP_KERNEL); | |
499 | if (!pd->used_pdes) | |
a08e111a | 500 | goto fail_bitmap; |
33c8819f | 501 | |
275a991c | 502 | ret = setup_px(dev_priv, pd); |
33c8819f | 503 | if (ret) |
a08e111a | 504 | goto fail_page_m; |
e5815a2e | 505 | |
06fda602 | 506 | return pd; |
33c8819f | 507 | |
a08e111a | 508 | fail_page_m: |
33c8819f | 509 | kfree(pd->used_pdes); |
a08e111a | 510 | fail_bitmap: |
33c8819f MT |
511 | kfree(pd); |
512 | ||
513 | return ERR_PTR(ret); | |
06fda602 BW |
514 | } |
515 | ||
275a991c TU |
516 | static void free_pd(struct drm_i915_private *dev_priv, |
517 | struct i915_page_directory *pd) | |
2e906bea MK |
518 | { |
519 | if (px_page(pd)) { | |
275a991c | 520 | cleanup_px(dev_priv, pd); |
2e906bea MK |
521 | kfree(pd->used_pdes); |
522 | kfree(pd); | |
523 | } | |
524 | } | |
525 | ||
526 | static void gen8_initialize_pd(struct i915_address_space *vm, | |
527 | struct i915_page_directory *pd) | |
528 | { | |
529 | gen8_pde_t scratch_pde; | |
530 | ||
531 | scratch_pde = gen8_pde_encode(px_dma(vm->scratch_pt), I915_CACHE_LLC); | |
532 | ||
49d73912 | 533 | fill_px(vm->i915, pd, scratch_pde); |
2e906bea MK |
534 | } |
535 | ||
275a991c | 536 | static int __pdp_init(struct drm_i915_private *dev_priv, |
6ac18502 MT |
537 | struct i915_page_directory_pointer *pdp) |
538 | { | |
275a991c | 539 | size_t pdpes = I915_PDPES_PER_PDP(dev_priv); |
6ac18502 MT |
540 | |
541 | pdp->used_pdpes = kcalloc(BITS_TO_LONGS(pdpes), | |
542 | sizeof(unsigned long), | |
543 | GFP_KERNEL); | |
544 | if (!pdp->used_pdpes) | |
545 | return -ENOMEM; | |
546 | ||
547 | pdp->page_directory = kcalloc(pdpes, sizeof(*pdp->page_directory), | |
548 | GFP_KERNEL); | |
549 | if (!pdp->page_directory) { | |
550 | kfree(pdp->used_pdpes); | |
551 | /* the PDP might be the statically allocated top level. Keep it | |
552 | * as clean as possible */ | |
553 | pdp->used_pdpes = NULL; | |
554 | return -ENOMEM; | |
555 | } | |
556 | ||
557 | return 0; | |
558 | } | |
559 | ||
560 | static void __pdp_fini(struct i915_page_directory_pointer *pdp) | |
561 | { | |
562 | kfree(pdp->used_pdpes); | |
563 | kfree(pdp->page_directory); | |
564 | pdp->page_directory = NULL; | |
565 | } | |
566 | ||
762d9936 | 567 | static struct |
275a991c | 568 | i915_page_directory_pointer *alloc_pdp(struct drm_i915_private *dev_priv) |
762d9936 MT |
569 | { |
570 | struct i915_page_directory_pointer *pdp; | |
571 | int ret = -ENOMEM; | |
572 | ||
275a991c | 573 | WARN_ON(!USES_FULL_48BIT_PPGTT(dev_priv)); |
762d9936 MT |
574 | |
575 | pdp = kzalloc(sizeof(*pdp), GFP_KERNEL); | |
576 | if (!pdp) | |
577 | return ERR_PTR(-ENOMEM); | |
578 | ||
275a991c | 579 | ret = __pdp_init(dev_priv, pdp); |
762d9936 MT |
580 | if (ret) |
581 | goto fail_bitmap; | |
582 | ||
275a991c | 583 | ret = setup_px(dev_priv, pdp); |
762d9936 MT |
584 | if (ret) |
585 | goto fail_page_m; | |
586 | ||
587 | return pdp; | |
588 | ||
589 | fail_page_m: | |
590 | __pdp_fini(pdp); | |
591 | fail_bitmap: | |
592 | kfree(pdp); | |
593 | ||
594 | return ERR_PTR(ret); | |
595 | } | |
596 | ||
275a991c | 597 | static void free_pdp(struct drm_i915_private *dev_priv, |
6ac18502 MT |
598 | struct i915_page_directory_pointer *pdp) |
599 | { | |
600 | __pdp_fini(pdp); | |
275a991c TU |
601 | if (USES_FULL_48BIT_PPGTT(dev_priv)) { |
602 | cleanup_px(dev_priv, pdp); | |
762d9936 MT |
603 | kfree(pdp); |
604 | } | |
605 | } | |
606 | ||
69ab76fd MT |
607 | static void gen8_initialize_pdp(struct i915_address_space *vm, |
608 | struct i915_page_directory_pointer *pdp) | |
609 | { | |
610 | gen8_ppgtt_pdpe_t scratch_pdpe; | |
611 | ||
612 | scratch_pdpe = gen8_pdpe_encode(px_dma(vm->scratch_pd), I915_CACHE_LLC); | |
613 | ||
49d73912 | 614 | fill_px(vm->i915, pdp, scratch_pdpe); |
69ab76fd MT |
615 | } |
616 | ||
617 | static void gen8_initialize_pml4(struct i915_address_space *vm, | |
618 | struct i915_pml4 *pml4) | |
619 | { | |
620 | gen8_ppgtt_pml4e_t scratch_pml4e; | |
621 | ||
622 | scratch_pml4e = gen8_pml4e_encode(px_dma(vm->scratch_pdp), | |
623 | I915_CACHE_LLC); | |
624 | ||
49d73912 | 625 | fill_px(vm->i915, pml4, scratch_pml4e); |
69ab76fd MT |
626 | } |
627 | ||
762d9936 | 628 | static void |
5c693b2b MA |
629 | gen8_setup_pdpe(struct i915_hw_ppgtt *ppgtt, |
630 | struct i915_page_directory_pointer *pdp, | |
631 | struct i915_page_directory *pd, | |
632 | int index) | |
762d9936 MT |
633 | { |
634 | gen8_ppgtt_pdpe_t *page_directorypo; | |
635 | ||
275a991c | 636 | if (!USES_FULL_48BIT_PPGTT(to_i915(ppgtt->base.dev))) |
762d9936 MT |
637 | return; |
638 | ||
639 | page_directorypo = kmap_px(pdp); | |
640 | page_directorypo[index] = gen8_pdpe_encode(px_dma(pd), I915_CACHE_LLC); | |
641 | kunmap_px(ppgtt, page_directorypo); | |
642 | } | |
643 | ||
644 | static void | |
56843107 MA |
645 | gen8_setup_pml4e(struct i915_hw_ppgtt *ppgtt, |
646 | struct i915_pml4 *pml4, | |
647 | struct i915_page_directory_pointer *pdp, | |
648 | int index) | |
762d9936 MT |
649 | { |
650 | gen8_ppgtt_pml4e_t *pagemap = kmap_px(pml4); | |
651 | ||
275a991c | 652 | WARN_ON(!USES_FULL_48BIT_PPGTT(to_i915(ppgtt->base.dev))); |
762d9936 MT |
653 | pagemap[index] = gen8_pml4e_encode(px_dma(pdp), I915_CACHE_LLC); |
654 | kunmap_px(ppgtt, pagemap); | |
6ac18502 MT |
655 | } |
656 | ||
94e409c1 | 657 | /* Broadwell Page Directory Pointer Descriptors */ |
e85b26dc | 658 | static int gen8_write_pdp(struct drm_i915_gem_request *req, |
7cb6d7ac MT |
659 | unsigned entry, |
660 | dma_addr_t addr) | |
94e409c1 | 661 | { |
7e37f889 | 662 | struct intel_ring *ring = req->ring; |
4a570db5 | 663 | struct intel_engine_cs *engine = req->engine; |
94e409c1 BW |
664 | int ret; |
665 | ||
666 | BUG_ON(entry >= 4); | |
667 | ||
5fb9de1a | 668 | ret = intel_ring_begin(req, 6); |
94e409c1 BW |
669 | if (ret) |
670 | return ret; | |
671 | ||
b5321f30 CW |
672 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); |
673 | intel_ring_emit_reg(ring, GEN8_RING_PDP_UDW(engine, entry)); | |
674 | intel_ring_emit(ring, upper_32_bits(addr)); | |
675 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
676 | intel_ring_emit_reg(ring, GEN8_RING_PDP_LDW(engine, entry)); | |
677 | intel_ring_emit(ring, lower_32_bits(addr)); | |
678 | intel_ring_advance(ring); | |
94e409c1 BW |
679 | |
680 | return 0; | |
681 | } | |
682 | ||
2dba3239 MT |
683 | static int gen8_legacy_mm_switch(struct i915_hw_ppgtt *ppgtt, |
684 | struct drm_i915_gem_request *req) | |
94e409c1 | 685 | { |
eeb9488e | 686 | int i, ret; |
94e409c1 | 687 | |
7cb6d7ac | 688 | for (i = GEN8_LEGACY_PDPES - 1; i >= 0; i--) { |
d852c7bf MK |
689 | const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i); |
690 | ||
e85b26dc | 691 | ret = gen8_write_pdp(req, i, pd_daddr); |
eeb9488e BW |
692 | if (ret) |
693 | return ret; | |
94e409c1 | 694 | } |
d595bd4b | 695 | |
eeb9488e | 696 | return 0; |
94e409c1 BW |
697 | } |
698 | ||
2dba3239 MT |
699 | static int gen8_48b_mm_switch(struct i915_hw_ppgtt *ppgtt, |
700 | struct drm_i915_gem_request *req) | |
701 | { | |
702 | return gen8_write_pdp(req, 0, px_dma(&ppgtt->pml4)); | |
703 | } | |
704 | ||
fce93755 MK |
705 | /* PDE TLBs are a pain to invalidate on GEN8+. When we modify |
706 | * the page table structures, we mark them dirty so that | |
707 | * context switching/execlist queuing code takes extra steps | |
708 | * to ensure that tlbs are flushed. | |
709 | */ | |
710 | static void mark_tlbs_dirty(struct i915_hw_ppgtt *ppgtt) | |
711 | { | |
49d73912 | 712 | ppgtt->pd_dirty_rings = INTEL_INFO(ppgtt->base.i915)->ring_mask; |
fce93755 MK |
713 | } |
714 | ||
2ce5179f MW |
715 | /* Removes entries from a single page table, releasing it if it's empty. |
716 | * Caller can use the return value to update higher-level entries. | |
717 | */ | |
718 | static bool gen8_ppgtt_clear_pt(struct i915_address_space *vm, | |
d209b9c3 MW |
719 | struct i915_page_table *pt, |
720 | uint64_t start, | |
721 | uint64_t length) | |
459108b8 | 722 | { |
e5716f55 | 723 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
d209b9c3 | 724 | unsigned int num_entries = gen8_pte_count(start, length); |
37c63934 MK |
725 | unsigned int pte = gen8_pte_index(start); |
726 | unsigned int pte_end = pte + num_entries; | |
f9b5b782 | 727 | gen8_pte_t *pt_vaddr; |
d209b9c3 MW |
728 | gen8_pte_t scratch_pte = gen8_pte_encode(vm->scratch_page.daddr, |
729 | I915_CACHE_LLC); | |
459108b8 | 730 | |
d209b9c3 | 731 | if (WARN_ON(!px_page(pt))) |
2ce5179f | 732 | return false; |
459108b8 | 733 | |
37c63934 MK |
734 | GEM_BUG_ON(pte_end > GEN8_PTES); |
735 | ||
736 | bitmap_clear(pt->used_ptes, pte, num_entries); | |
06fda602 | 737 | |
a18dbba8 | 738 | if (bitmap_empty(pt->used_ptes, GEN8_PTES)) |
2ce5179f | 739 | return true; |
2ce5179f | 740 | |
d209b9c3 MW |
741 | pt_vaddr = kmap_px(pt); |
742 | ||
37c63934 MK |
743 | while (pte < pte_end) |
744 | pt_vaddr[pte++] = scratch_pte; | |
06fda602 | 745 | |
d209b9c3 | 746 | kunmap_px(ppgtt, pt_vaddr); |
2ce5179f MW |
747 | |
748 | return false; | |
d209b9c3 | 749 | } |
06fda602 | 750 | |
2ce5179f MW |
751 | /* Removes entries from a single page dir, releasing it if it's empty. |
752 | * Caller can use the return value to update higher-level entries | |
753 | */ | |
754 | static bool gen8_ppgtt_clear_pd(struct i915_address_space *vm, | |
d209b9c3 MW |
755 | struct i915_page_directory *pd, |
756 | uint64_t start, | |
757 | uint64_t length) | |
758 | { | |
2ce5179f | 759 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
d209b9c3 MW |
760 | struct i915_page_table *pt; |
761 | uint64_t pde; | |
2ce5179f MW |
762 | gen8_pde_t *pde_vaddr; |
763 | gen8_pde_t scratch_pde = gen8_pde_encode(px_dma(vm->scratch_pt), | |
764 | I915_CACHE_LLC); | |
d209b9c3 MW |
765 | |
766 | gen8_for_each_pde(pt, pd, start, length, pde) { | |
06fda602 | 767 | if (WARN_ON(!pd->page_table[pde])) |
00245266 | 768 | break; |
06fda602 | 769 | |
2ce5179f MW |
770 | if (gen8_ppgtt_clear_pt(vm, pt, start, length)) { |
771 | __clear_bit(pde, pd->used_pdes); | |
772 | pde_vaddr = kmap_px(pd); | |
773 | pde_vaddr[pde] = scratch_pde; | |
774 | kunmap_px(ppgtt, pde_vaddr); | |
49d73912 | 775 | free_pt(vm->i915, pt); |
2ce5179f MW |
776 | } |
777 | } | |
778 | ||
a18dbba8 | 779 | if (bitmap_empty(pd->used_pdes, I915_PDES)) |
2ce5179f | 780 | return true; |
2ce5179f MW |
781 | |
782 | return false; | |
d209b9c3 | 783 | } |
06fda602 | 784 | |
2ce5179f MW |
785 | /* Removes entries from a single page dir pointer, releasing it if it's empty. |
786 | * Caller can use the return value to update higher-level entries | |
787 | */ | |
788 | static bool gen8_ppgtt_clear_pdp(struct i915_address_space *vm, | |
d209b9c3 MW |
789 | struct i915_page_directory_pointer *pdp, |
790 | uint64_t start, | |
791 | uint64_t length) | |
792 | { | |
2ce5179f | 793 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
d209b9c3 MW |
794 | struct i915_page_directory *pd; |
795 | uint64_t pdpe; | |
06fda602 | 796 | |
d209b9c3 MW |
797 | gen8_for_each_pdpe(pd, pdp, start, length, pdpe) { |
798 | if (WARN_ON(!pdp->page_directory[pdpe])) | |
799 | break; | |
459108b8 | 800 | |
2ce5179f MW |
801 | if (gen8_ppgtt_clear_pd(vm, pd, start, length)) { |
802 | __clear_bit(pdpe, pdp->used_pdpes); | |
9e65a378 | 803 | gen8_setup_pdpe(ppgtt, pdp, vm->scratch_pd, pdpe); |
49d73912 | 804 | free_pd(vm->i915, pd); |
2ce5179f MW |
805 | } |
806 | } | |
807 | ||
fce93755 MK |
808 | mark_tlbs_dirty(ppgtt); |
809 | ||
a18dbba8 | 810 | if (bitmap_empty(pdp->used_pdpes, I915_PDPES_PER_PDP(dev_priv))) |
2ce5179f | 811 | return true; |
2ce5179f MW |
812 | |
813 | return false; | |
d209b9c3 | 814 | } |
459108b8 | 815 | |
2ce5179f MW |
816 | /* Removes entries from a single pml4. |
817 | * This is the top-level structure in 4-level page tables used on gen8+. | |
818 | * Empty entries are always scratch pml4e. | |
819 | */ | |
d209b9c3 MW |
820 | static void gen8_ppgtt_clear_pml4(struct i915_address_space *vm, |
821 | struct i915_pml4 *pml4, | |
822 | uint64_t start, | |
823 | uint64_t length) | |
824 | { | |
2ce5179f | 825 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
d209b9c3 MW |
826 | struct i915_page_directory_pointer *pdp; |
827 | uint64_t pml4e; | |
2ce5179f | 828 | |
49d73912 | 829 | GEM_BUG_ON(!USES_FULL_48BIT_PPGTT(vm->i915)); |
459108b8 | 830 | |
d209b9c3 MW |
831 | gen8_for_each_pml4e(pdp, pml4, start, length, pml4e) { |
832 | if (WARN_ON(!pml4->pdps[pml4e])) | |
833 | break; | |
459108b8 | 834 | |
2ce5179f MW |
835 | if (gen8_ppgtt_clear_pdp(vm, pdp, start, length)) { |
836 | __clear_bit(pml4e, pml4->used_pml4es); | |
9e65a378 | 837 | gen8_setup_pml4e(ppgtt, pml4, vm->scratch_pdp, pml4e); |
49d73912 | 838 | free_pdp(vm->i915, pdp); |
2ce5179f | 839 | } |
459108b8 BW |
840 | } |
841 | } | |
842 | ||
f9b5b782 | 843 | static void gen8_ppgtt_clear_range(struct i915_address_space *vm, |
4fb84d99 | 844 | uint64_t start, uint64_t length) |
9df15b49 | 845 | { |
e5716f55 | 846 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
f9b5b782 | 847 | |
c6385c94 | 848 | if (USES_FULL_48BIT_PPGTT(vm->i915)) |
d209b9c3 MW |
849 | gen8_ppgtt_clear_pml4(vm, &ppgtt->pml4, start, length); |
850 | else | |
851 | gen8_ppgtt_clear_pdp(vm, &ppgtt->pdp, start, length); | |
f9b5b782 MT |
852 | } |
853 | ||
854 | static void | |
855 | gen8_ppgtt_insert_pte_entries(struct i915_address_space *vm, | |
856 | struct i915_page_directory_pointer *pdp, | |
3387d433 | 857 | struct sg_page_iter *sg_iter, |
f9b5b782 MT |
858 | uint64_t start, |
859 | enum i915_cache_level cache_level) | |
860 | { | |
e5716f55 | 861 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
07749ef3 | 862 | gen8_pte_t *pt_vaddr; |
de5ba8eb MT |
863 | unsigned pdpe = gen8_pdpe_index(start); |
864 | unsigned pde = gen8_pde_index(start); | |
865 | unsigned pte = gen8_pte_index(start); | |
9df15b49 | 866 | |
6f1cc993 | 867 | pt_vaddr = NULL; |
7ad47cf2 | 868 | |
3387d433 | 869 | while (__sg_page_iter_next(sg_iter)) { |
d7b3de91 | 870 | if (pt_vaddr == NULL) { |
d4ec9da0 | 871 | struct i915_page_directory *pd = pdp->page_directory[pdpe]; |
ec565b3c | 872 | struct i915_page_table *pt = pd->page_table[pde]; |
d1c54acd | 873 | pt_vaddr = kmap_px(pt); |
d7b3de91 | 874 | } |
9df15b49 | 875 | |
7ad47cf2 | 876 | pt_vaddr[pte] = |
3387d433 | 877 | gen8_pte_encode(sg_page_iter_dma_address(sg_iter), |
4fb84d99 | 878 | cache_level); |
07749ef3 | 879 | if (++pte == GEN8_PTES) { |
d1c54acd | 880 | kunmap_px(ppgtt, pt_vaddr); |
6f1cc993 | 881 | pt_vaddr = NULL; |
07749ef3 | 882 | if (++pde == I915_PDES) { |
c6385c94 | 883 | if (++pdpe == I915_PDPES_PER_PDP(vm->i915)) |
de5ba8eb | 884 | break; |
7ad47cf2 BW |
885 | pde = 0; |
886 | } | |
887 | pte = 0; | |
9df15b49 BW |
888 | } |
889 | } | |
d1c54acd MK |
890 | |
891 | if (pt_vaddr) | |
892 | kunmap_px(ppgtt, pt_vaddr); | |
9df15b49 BW |
893 | } |
894 | ||
f9b5b782 MT |
895 | static void gen8_ppgtt_insert_entries(struct i915_address_space *vm, |
896 | struct sg_table *pages, | |
897 | uint64_t start, | |
898 | enum i915_cache_level cache_level, | |
899 | u32 unused) | |
900 | { | |
e5716f55 | 901 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
3387d433 | 902 | struct sg_page_iter sg_iter; |
f9b5b782 | 903 | |
3387d433 | 904 | __sg_page_iter_start(&sg_iter, pages->sgl, sg_nents(pages->sgl), 0); |
de5ba8eb | 905 | |
c6385c94 | 906 | if (!USES_FULL_48BIT_PPGTT(vm->i915)) { |
de5ba8eb MT |
907 | gen8_ppgtt_insert_pte_entries(vm, &ppgtt->pdp, &sg_iter, start, |
908 | cache_level); | |
909 | } else { | |
910 | struct i915_page_directory_pointer *pdp; | |
e8ebd8e2 | 911 | uint64_t pml4e; |
de5ba8eb MT |
912 | uint64_t length = (uint64_t)pages->orig_nents << PAGE_SHIFT; |
913 | ||
e8ebd8e2 | 914 | gen8_for_each_pml4e(pdp, &ppgtt->pml4, start, length, pml4e) { |
de5ba8eb MT |
915 | gen8_ppgtt_insert_pte_entries(vm, pdp, &sg_iter, |
916 | start, cache_level); | |
917 | } | |
918 | } | |
f9b5b782 MT |
919 | } |
920 | ||
275a991c | 921 | static void gen8_free_page_tables(struct drm_i915_private *dev_priv, |
f37c0505 | 922 | struct i915_page_directory *pd) |
7ad47cf2 BW |
923 | { |
924 | int i; | |
925 | ||
567047be | 926 | if (!px_page(pd)) |
7ad47cf2 BW |
927 | return; |
928 | ||
33c8819f | 929 | for_each_set_bit(i, pd->used_pdes, I915_PDES) { |
06fda602 BW |
930 | if (WARN_ON(!pd->page_table[i])) |
931 | continue; | |
7ad47cf2 | 932 | |
275a991c | 933 | free_pt(dev_priv, pd->page_table[i]); |
06fda602 BW |
934 | pd->page_table[i] = NULL; |
935 | } | |
d7b3de91 BW |
936 | } |
937 | ||
8776f02b MK |
938 | static int gen8_init_scratch(struct i915_address_space *vm) |
939 | { | |
49d73912 | 940 | struct drm_i915_private *dev_priv = vm->i915; |
64c050db | 941 | int ret; |
8776f02b | 942 | |
275a991c | 943 | ret = setup_scratch_page(dev_priv, &vm->scratch_page, I915_GFP_DMA); |
8bcdd0f7 CW |
944 | if (ret) |
945 | return ret; | |
8776f02b | 946 | |
275a991c | 947 | vm->scratch_pt = alloc_pt(dev_priv); |
8776f02b | 948 | if (IS_ERR(vm->scratch_pt)) { |
64c050db MA |
949 | ret = PTR_ERR(vm->scratch_pt); |
950 | goto free_scratch_page; | |
8776f02b MK |
951 | } |
952 | ||
275a991c | 953 | vm->scratch_pd = alloc_pd(dev_priv); |
8776f02b | 954 | if (IS_ERR(vm->scratch_pd)) { |
64c050db MA |
955 | ret = PTR_ERR(vm->scratch_pd); |
956 | goto free_pt; | |
8776f02b MK |
957 | } |
958 | ||
275a991c TU |
959 | if (USES_FULL_48BIT_PPGTT(dev_priv)) { |
960 | vm->scratch_pdp = alloc_pdp(dev_priv); | |
69ab76fd | 961 | if (IS_ERR(vm->scratch_pdp)) { |
64c050db MA |
962 | ret = PTR_ERR(vm->scratch_pdp); |
963 | goto free_pd; | |
69ab76fd MT |
964 | } |
965 | } | |
966 | ||
8776f02b MK |
967 | gen8_initialize_pt(vm, vm->scratch_pt); |
968 | gen8_initialize_pd(vm, vm->scratch_pd); | |
275a991c | 969 | if (USES_FULL_48BIT_PPGTT(dev_priv)) |
69ab76fd | 970 | gen8_initialize_pdp(vm, vm->scratch_pdp); |
8776f02b MK |
971 | |
972 | return 0; | |
64c050db MA |
973 | |
974 | free_pd: | |
275a991c | 975 | free_pd(dev_priv, vm->scratch_pd); |
64c050db | 976 | free_pt: |
275a991c | 977 | free_pt(dev_priv, vm->scratch_pt); |
64c050db | 978 | free_scratch_page: |
275a991c | 979 | cleanup_scratch_page(dev_priv, &vm->scratch_page); |
64c050db MA |
980 | |
981 | return ret; | |
8776f02b MK |
982 | } |
983 | ||
650da34c ZL |
984 | static int gen8_ppgtt_notify_vgt(struct i915_hw_ppgtt *ppgtt, bool create) |
985 | { | |
986 | enum vgt_g2v_type msg; | |
49d73912 | 987 | struct drm_i915_private *dev_priv = ppgtt->base.i915; |
650da34c ZL |
988 | int i; |
989 | ||
df28564d | 990 | if (USES_FULL_48BIT_PPGTT(dev_priv)) { |
650da34c ZL |
991 | u64 daddr = px_dma(&ppgtt->pml4); |
992 | ||
ab75bb5d VS |
993 | I915_WRITE(vgtif_reg(pdp[0].lo), lower_32_bits(daddr)); |
994 | I915_WRITE(vgtif_reg(pdp[0].hi), upper_32_bits(daddr)); | |
650da34c ZL |
995 | |
996 | msg = (create ? VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE : | |
997 | VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY); | |
998 | } else { | |
999 | for (i = 0; i < GEN8_LEGACY_PDPES; i++) { | |
1000 | u64 daddr = i915_page_dir_dma_addr(ppgtt, i); | |
1001 | ||
ab75bb5d VS |
1002 | I915_WRITE(vgtif_reg(pdp[i].lo), lower_32_bits(daddr)); |
1003 | I915_WRITE(vgtif_reg(pdp[i].hi), upper_32_bits(daddr)); | |
650da34c ZL |
1004 | } |
1005 | ||
1006 | msg = (create ? VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE : | |
1007 | VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY); | |
1008 | } | |
1009 | ||
1010 | I915_WRITE(vgtif_reg(g2v_notify), msg); | |
1011 | ||
1012 | return 0; | |
1013 | } | |
1014 | ||
8776f02b MK |
1015 | static void gen8_free_scratch(struct i915_address_space *vm) |
1016 | { | |
49d73912 | 1017 | struct drm_i915_private *dev_priv = vm->i915; |
8776f02b | 1018 | |
275a991c TU |
1019 | if (USES_FULL_48BIT_PPGTT(dev_priv)) |
1020 | free_pdp(dev_priv, vm->scratch_pdp); | |
1021 | free_pd(dev_priv, vm->scratch_pd); | |
1022 | free_pt(dev_priv, vm->scratch_pt); | |
1023 | cleanup_scratch_page(dev_priv, &vm->scratch_page); | |
8776f02b MK |
1024 | } |
1025 | ||
275a991c | 1026 | static void gen8_ppgtt_cleanup_3lvl(struct drm_i915_private *dev_priv, |
762d9936 | 1027 | struct i915_page_directory_pointer *pdp) |
b45a6715 BW |
1028 | { |
1029 | int i; | |
1030 | ||
275a991c | 1031 | for_each_set_bit(i, pdp->used_pdpes, I915_PDPES_PER_PDP(dev_priv)) { |
d4ec9da0 | 1032 | if (WARN_ON(!pdp->page_directory[i])) |
06fda602 BW |
1033 | continue; |
1034 | ||
275a991c TU |
1035 | gen8_free_page_tables(dev_priv, pdp->page_directory[i]); |
1036 | free_pd(dev_priv, pdp->page_directory[i]); | |
7ad47cf2 | 1037 | } |
69876bed | 1038 | |
275a991c | 1039 | free_pdp(dev_priv, pdp); |
762d9936 MT |
1040 | } |
1041 | ||
1042 | static void gen8_ppgtt_cleanup_4lvl(struct i915_hw_ppgtt *ppgtt) | |
1043 | { | |
49d73912 | 1044 | struct drm_i915_private *dev_priv = ppgtt->base.i915; |
762d9936 MT |
1045 | int i; |
1046 | ||
1047 | for_each_set_bit(i, ppgtt->pml4.used_pml4es, GEN8_PML4ES_PER_PML4) { | |
1048 | if (WARN_ON(!ppgtt->pml4.pdps[i])) | |
1049 | continue; | |
1050 | ||
275a991c | 1051 | gen8_ppgtt_cleanup_3lvl(dev_priv, ppgtt->pml4.pdps[i]); |
762d9936 MT |
1052 | } |
1053 | ||
275a991c | 1054 | cleanup_px(dev_priv, &ppgtt->pml4); |
762d9936 MT |
1055 | } |
1056 | ||
1057 | static void gen8_ppgtt_cleanup(struct i915_address_space *vm) | |
1058 | { | |
49d73912 | 1059 | struct drm_i915_private *dev_priv = vm->i915; |
e5716f55 | 1060 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
762d9936 | 1061 | |
275a991c | 1062 | if (intel_vgpu_active(dev_priv)) |
650da34c ZL |
1063 | gen8_ppgtt_notify_vgt(ppgtt, false); |
1064 | ||
275a991c TU |
1065 | if (!USES_FULL_48BIT_PPGTT(dev_priv)) |
1066 | gen8_ppgtt_cleanup_3lvl(dev_priv, &ppgtt->pdp); | |
762d9936 MT |
1067 | else |
1068 | gen8_ppgtt_cleanup_4lvl(ppgtt); | |
d4ec9da0 | 1069 | |
8776f02b | 1070 | gen8_free_scratch(vm); |
b45a6715 BW |
1071 | } |
1072 | ||
d7b2633d MT |
1073 | /** |
1074 | * gen8_ppgtt_alloc_pagetabs() - Allocate page tables for VA range. | |
d4ec9da0 MT |
1075 | * @vm: Master vm structure. |
1076 | * @pd: Page directory for this address range. | |
d7b2633d | 1077 | * @start: Starting virtual address to begin allocations. |
d4ec9da0 | 1078 | * @length: Size of the allocations. |
d7b2633d MT |
1079 | * @new_pts: Bitmap set by function with new allocations. Likely used by the |
1080 | * caller to free on error. | |
1081 | * | |
1082 | * Allocate the required number of page tables. Extremely similar to | |
1083 | * gen8_ppgtt_alloc_page_directories(). The main difference is here we are limited by | |
1084 | * the page directory boundary (instead of the page directory pointer). That | |
1085 | * boundary is 1GB virtual. Therefore, unlike gen8_ppgtt_alloc_page_directories(), it is | |
1086 | * possible, and likely that the caller will need to use multiple calls of this | |
1087 | * function to achieve the appropriate allocation. | |
1088 | * | |
1089 | * Return: 0 if success; negative error code otherwise. | |
1090 | */ | |
d4ec9da0 | 1091 | static int gen8_ppgtt_alloc_pagetabs(struct i915_address_space *vm, |
e5815a2e | 1092 | struct i915_page_directory *pd, |
5441f0cb | 1093 | uint64_t start, |
d7b2633d MT |
1094 | uint64_t length, |
1095 | unsigned long *new_pts) | |
bf2b4ed2 | 1096 | { |
49d73912 | 1097 | struct drm_i915_private *dev_priv = vm->i915; |
d7b2633d | 1098 | struct i915_page_table *pt; |
5441f0cb | 1099 | uint32_t pde; |
bf2b4ed2 | 1100 | |
e8ebd8e2 | 1101 | gen8_for_each_pde(pt, pd, start, length, pde) { |
d7b2633d | 1102 | /* Don't reallocate page tables */ |
6ac18502 | 1103 | if (test_bit(pde, pd->used_pdes)) { |
d7b2633d | 1104 | /* Scratch is never allocated this way */ |
d4ec9da0 | 1105 | WARN_ON(pt == vm->scratch_pt); |
d7b2633d MT |
1106 | continue; |
1107 | } | |
1108 | ||
275a991c | 1109 | pt = alloc_pt(dev_priv); |
d7b2633d | 1110 | if (IS_ERR(pt)) |
5441f0cb MT |
1111 | goto unwind_out; |
1112 | ||
d4ec9da0 | 1113 | gen8_initialize_pt(vm, pt); |
d7b2633d | 1114 | pd->page_table[pde] = pt; |
966082c9 | 1115 | __set_bit(pde, new_pts); |
4c06ec8d | 1116 | trace_i915_page_table_entry_alloc(vm, pde, start, GEN8_PDE_SHIFT); |
7ad47cf2 BW |
1117 | } |
1118 | ||
bf2b4ed2 | 1119 | return 0; |
7ad47cf2 BW |
1120 | |
1121 | unwind_out: | |
d7b2633d | 1122 | for_each_set_bit(pde, new_pts, I915_PDES) |
275a991c | 1123 | free_pt(dev_priv, pd->page_table[pde]); |
7ad47cf2 | 1124 | |
d7b3de91 | 1125 | return -ENOMEM; |
bf2b4ed2 BW |
1126 | } |
1127 | ||
d7b2633d MT |
1128 | /** |
1129 | * gen8_ppgtt_alloc_page_directories() - Allocate page directories for VA range. | |
d4ec9da0 | 1130 | * @vm: Master vm structure. |
d7b2633d MT |
1131 | * @pdp: Page directory pointer for this address range. |
1132 | * @start: Starting virtual address to begin allocations. | |
d4ec9da0 MT |
1133 | * @length: Size of the allocations. |
1134 | * @new_pds: Bitmap set by function with new allocations. Likely used by the | |
d7b2633d MT |
1135 | * caller to free on error. |
1136 | * | |
1137 | * Allocate the required number of page directories starting at the pde index of | |
1138 | * @start, and ending at the pde index @start + @length. This function will skip | |
1139 | * over already allocated page directories within the range, and only allocate | |
1140 | * new ones, setting the appropriate pointer within the pdp as well as the | |
1141 | * correct position in the bitmap @new_pds. | |
1142 | * | |
1143 | * The function will only allocate the pages within the range for a give page | |
1144 | * directory pointer. In other words, if @start + @length straddles a virtually | |
1145 | * addressed PDP boundary (512GB for 4k pages), there will be more allocations | |
1146 | * required by the caller, This is not currently possible, and the BUG in the | |
1147 | * code will prevent it. | |
1148 | * | |
1149 | * Return: 0 if success; negative error code otherwise. | |
1150 | */ | |
d4ec9da0 MT |
1151 | static int |
1152 | gen8_ppgtt_alloc_page_directories(struct i915_address_space *vm, | |
1153 | struct i915_page_directory_pointer *pdp, | |
1154 | uint64_t start, | |
1155 | uint64_t length, | |
1156 | unsigned long *new_pds) | |
bf2b4ed2 | 1157 | { |
49d73912 | 1158 | struct drm_i915_private *dev_priv = vm->i915; |
d7b2633d | 1159 | struct i915_page_directory *pd; |
69876bed | 1160 | uint32_t pdpe; |
275a991c | 1161 | uint32_t pdpes = I915_PDPES_PER_PDP(dev_priv); |
69876bed | 1162 | |
6ac18502 | 1163 | WARN_ON(!bitmap_empty(new_pds, pdpes)); |
d7b2633d | 1164 | |
e8ebd8e2 | 1165 | gen8_for_each_pdpe(pd, pdp, start, length, pdpe) { |
6ac18502 | 1166 | if (test_bit(pdpe, pdp->used_pdpes)) |
d7b2633d | 1167 | continue; |
33c8819f | 1168 | |
275a991c | 1169 | pd = alloc_pd(dev_priv); |
d7b2633d | 1170 | if (IS_ERR(pd)) |
d7b3de91 | 1171 | goto unwind_out; |
69876bed | 1172 | |
d4ec9da0 | 1173 | gen8_initialize_pd(vm, pd); |
d7b2633d | 1174 | pdp->page_directory[pdpe] = pd; |
966082c9 | 1175 | __set_bit(pdpe, new_pds); |
4c06ec8d | 1176 | trace_i915_page_directory_entry_alloc(vm, pdpe, start, GEN8_PDPE_SHIFT); |
d7b3de91 BW |
1177 | } |
1178 | ||
bf2b4ed2 | 1179 | return 0; |
d7b3de91 BW |
1180 | |
1181 | unwind_out: | |
6ac18502 | 1182 | for_each_set_bit(pdpe, new_pds, pdpes) |
275a991c | 1183 | free_pd(dev_priv, pdp->page_directory[pdpe]); |
d7b3de91 BW |
1184 | |
1185 | return -ENOMEM; | |
bf2b4ed2 BW |
1186 | } |
1187 | ||
762d9936 MT |
1188 | /** |
1189 | * gen8_ppgtt_alloc_page_dirpointers() - Allocate pdps for VA range. | |
1190 | * @vm: Master vm structure. | |
1191 | * @pml4: Page map level 4 for this address range. | |
1192 | * @start: Starting virtual address to begin allocations. | |
1193 | * @length: Size of the allocations. | |
1194 | * @new_pdps: Bitmap set by function with new allocations. Likely used by the | |
1195 | * caller to free on error. | |
1196 | * | |
1197 | * Allocate the required number of page directory pointers. Extremely similar to | |
1198 | * gen8_ppgtt_alloc_page_directories() and gen8_ppgtt_alloc_pagetabs(). | |
1199 | * The main difference is here we are limited by the pml4 boundary (instead of | |
1200 | * the page directory pointer). | |
1201 | * | |
1202 | * Return: 0 if success; negative error code otherwise. | |
1203 | */ | |
1204 | static int | |
1205 | gen8_ppgtt_alloc_page_dirpointers(struct i915_address_space *vm, | |
1206 | struct i915_pml4 *pml4, | |
1207 | uint64_t start, | |
1208 | uint64_t length, | |
1209 | unsigned long *new_pdps) | |
1210 | { | |
49d73912 | 1211 | struct drm_i915_private *dev_priv = vm->i915; |
762d9936 | 1212 | struct i915_page_directory_pointer *pdp; |
762d9936 MT |
1213 | uint32_t pml4e; |
1214 | ||
1215 | WARN_ON(!bitmap_empty(new_pdps, GEN8_PML4ES_PER_PML4)); | |
1216 | ||
e8ebd8e2 | 1217 | gen8_for_each_pml4e(pdp, pml4, start, length, pml4e) { |
762d9936 | 1218 | if (!test_bit(pml4e, pml4->used_pml4es)) { |
275a991c | 1219 | pdp = alloc_pdp(dev_priv); |
762d9936 MT |
1220 | if (IS_ERR(pdp)) |
1221 | goto unwind_out; | |
1222 | ||
69ab76fd | 1223 | gen8_initialize_pdp(vm, pdp); |
762d9936 MT |
1224 | pml4->pdps[pml4e] = pdp; |
1225 | __set_bit(pml4e, new_pdps); | |
1226 | trace_i915_page_directory_pointer_entry_alloc(vm, | |
1227 | pml4e, | |
1228 | start, | |
1229 | GEN8_PML4E_SHIFT); | |
1230 | } | |
1231 | } | |
1232 | ||
1233 | return 0; | |
1234 | ||
1235 | unwind_out: | |
1236 | for_each_set_bit(pml4e, new_pdps, GEN8_PML4ES_PER_PML4) | |
275a991c | 1237 | free_pdp(dev_priv, pml4->pdps[pml4e]); |
762d9936 MT |
1238 | |
1239 | return -ENOMEM; | |
1240 | } | |
1241 | ||
d7b2633d | 1242 | static void |
3a41a05d | 1243 | free_gen8_temp_bitmaps(unsigned long *new_pds, unsigned long *new_pts) |
d7b2633d | 1244 | { |
d7b2633d MT |
1245 | kfree(new_pts); |
1246 | kfree(new_pds); | |
1247 | } | |
1248 | ||
1249 | /* Fills in the page directory bitmap, and the array of page tables bitmap. Both | |
1250 | * of these are based on the number of PDPEs in the system. | |
1251 | */ | |
1252 | static | |
1253 | int __must_check alloc_gen8_temp_bitmaps(unsigned long **new_pds, | |
3a41a05d | 1254 | unsigned long **new_pts, |
6ac18502 | 1255 | uint32_t pdpes) |
d7b2633d | 1256 | { |
d7b2633d | 1257 | unsigned long *pds; |
3a41a05d | 1258 | unsigned long *pts; |
d7b2633d | 1259 | |
3a41a05d | 1260 | pds = kcalloc(BITS_TO_LONGS(pdpes), sizeof(unsigned long), GFP_TEMPORARY); |
d7b2633d MT |
1261 | if (!pds) |
1262 | return -ENOMEM; | |
1263 | ||
3a41a05d MW |
1264 | pts = kcalloc(pdpes, BITS_TO_LONGS(I915_PDES) * sizeof(unsigned long), |
1265 | GFP_TEMPORARY); | |
1266 | if (!pts) | |
1267 | goto err_out; | |
d7b2633d MT |
1268 | |
1269 | *new_pds = pds; | |
1270 | *new_pts = pts; | |
1271 | ||
1272 | return 0; | |
1273 | ||
1274 | err_out: | |
3a41a05d | 1275 | free_gen8_temp_bitmaps(pds, pts); |
d7b2633d MT |
1276 | return -ENOMEM; |
1277 | } | |
1278 | ||
762d9936 MT |
1279 | static int gen8_alloc_va_range_3lvl(struct i915_address_space *vm, |
1280 | struct i915_page_directory_pointer *pdp, | |
1281 | uint64_t start, | |
1282 | uint64_t length) | |
bf2b4ed2 | 1283 | { |
e5716f55 | 1284 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
3a41a05d | 1285 | unsigned long *new_page_dirs, *new_page_tables; |
49d73912 | 1286 | struct drm_i915_private *dev_priv = vm->i915; |
5441f0cb | 1287 | struct i915_page_directory *pd; |
33c8819f MT |
1288 | const uint64_t orig_start = start; |
1289 | const uint64_t orig_length = length; | |
5441f0cb | 1290 | uint32_t pdpe; |
275a991c | 1291 | uint32_t pdpes = I915_PDPES_PER_PDP(dev_priv); |
bf2b4ed2 BW |
1292 | int ret; |
1293 | ||
6ac18502 | 1294 | ret = alloc_gen8_temp_bitmaps(&new_page_dirs, &new_page_tables, pdpes); |
bf2b4ed2 BW |
1295 | if (ret) |
1296 | return ret; | |
1297 | ||
d7b2633d | 1298 | /* Do the allocations first so we can easily bail out */ |
d4ec9da0 MT |
1299 | ret = gen8_ppgtt_alloc_page_directories(vm, pdp, start, length, |
1300 | new_page_dirs); | |
d7b2633d | 1301 | if (ret) { |
3a41a05d | 1302 | free_gen8_temp_bitmaps(new_page_dirs, new_page_tables); |
d7b2633d MT |
1303 | return ret; |
1304 | } | |
1305 | ||
1306 | /* For every page directory referenced, allocate page tables */ | |
e8ebd8e2 | 1307 | gen8_for_each_pdpe(pd, pdp, start, length, pdpe) { |
d4ec9da0 | 1308 | ret = gen8_ppgtt_alloc_pagetabs(vm, pd, start, length, |
3a41a05d | 1309 | new_page_tables + pdpe * BITS_TO_LONGS(I915_PDES)); |
5441f0cb MT |
1310 | if (ret) |
1311 | goto err_out; | |
5441f0cb MT |
1312 | } |
1313 | ||
33c8819f MT |
1314 | start = orig_start; |
1315 | length = orig_length; | |
1316 | ||
d7b2633d MT |
1317 | /* Allocations have completed successfully, so set the bitmaps, and do |
1318 | * the mappings. */ | |
e8ebd8e2 | 1319 | gen8_for_each_pdpe(pd, pdp, start, length, pdpe) { |
d1c54acd | 1320 | gen8_pde_t *const page_directory = kmap_px(pd); |
33c8819f | 1321 | struct i915_page_table *pt; |
09120d4e | 1322 | uint64_t pd_len = length; |
33c8819f MT |
1323 | uint64_t pd_start = start; |
1324 | uint32_t pde; | |
1325 | ||
d7b2633d MT |
1326 | /* Every pd should be allocated, we just did that above. */ |
1327 | WARN_ON(!pd); | |
1328 | ||
e8ebd8e2 | 1329 | gen8_for_each_pde(pt, pd, pd_start, pd_len, pde) { |
d7b2633d MT |
1330 | /* Same reasoning as pd */ |
1331 | WARN_ON(!pt); | |
1332 | WARN_ON(!pd_len); | |
1333 | WARN_ON(!gen8_pte_count(pd_start, pd_len)); | |
1334 | ||
1335 | /* Set our used ptes within the page table */ | |
1336 | bitmap_set(pt->used_ptes, | |
1337 | gen8_pte_index(pd_start), | |
1338 | gen8_pte_count(pd_start, pd_len)); | |
1339 | ||
1340 | /* Our pde is now pointing to the pagetable, pt */ | |
966082c9 | 1341 | __set_bit(pde, pd->used_pdes); |
d7b2633d MT |
1342 | |
1343 | /* Map the PDE to the page table */ | |
fe36f55d MK |
1344 | page_directory[pde] = gen8_pde_encode(px_dma(pt), |
1345 | I915_CACHE_LLC); | |
4c06ec8d MT |
1346 | trace_i915_page_table_entry_map(&ppgtt->base, pde, pt, |
1347 | gen8_pte_index(start), | |
1348 | gen8_pte_count(start, length), | |
1349 | GEN8_PTES); | |
d7b2633d MT |
1350 | |
1351 | /* NB: We haven't yet mapped ptes to pages. At this | |
1352 | * point we're still relying on insert_entries() */ | |
33c8819f | 1353 | } |
d7b2633d | 1354 | |
d1c54acd | 1355 | kunmap_px(ppgtt, page_directory); |
d4ec9da0 | 1356 | __set_bit(pdpe, pdp->used_pdpes); |
5c693b2b | 1357 | gen8_setup_pdpe(ppgtt, pdp, pd, pdpe); |
33c8819f MT |
1358 | } |
1359 | ||
3a41a05d | 1360 | free_gen8_temp_bitmaps(new_page_dirs, new_page_tables); |
5b7e4c9c | 1361 | mark_tlbs_dirty(ppgtt); |
d7b3de91 | 1362 | return 0; |
bf2b4ed2 | 1363 | |
d7b3de91 | 1364 | err_out: |
d7b2633d | 1365 | while (pdpe--) { |
e8ebd8e2 DG |
1366 | unsigned long temp; |
1367 | ||
3a41a05d MW |
1368 | for_each_set_bit(temp, new_page_tables + pdpe * |
1369 | BITS_TO_LONGS(I915_PDES), I915_PDES) | |
275a991c TU |
1370 | free_pt(dev_priv, |
1371 | pdp->page_directory[pdpe]->page_table[temp]); | |
d7b2633d MT |
1372 | } |
1373 | ||
6ac18502 | 1374 | for_each_set_bit(pdpe, new_page_dirs, pdpes) |
275a991c | 1375 | free_pd(dev_priv, pdp->page_directory[pdpe]); |
d7b2633d | 1376 | |
3a41a05d | 1377 | free_gen8_temp_bitmaps(new_page_dirs, new_page_tables); |
5b7e4c9c | 1378 | mark_tlbs_dirty(ppgtt); |
bf2b4ed2 BW |
1379 | return ret; |
1380 | } | |
1381 | ||
762d9936 MT |
1382 | static int gen8_alloc_va_range_4lvl(struct i915_address_space *vm, |
1383 | struct i915_pml4 *pml4, | |
1384 | uint64_t start, | |
1385 | uint64_t length) | |
1386 | { | |
1387 | DECLARE_BITMAP(new_pdps, GEN8_PML4ES_PER_PML4); | |
e5716f55 | 1388 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
762d9936 | 1389 | struct i915_page_directory_pointer *pdp; |
e8ebd8e2 | 1390 | uint64_t pml4e; |
762d9936 MT |
1391 | int ret = 0; |
1392 | ||
1393 | /* Do the pml4 allocations first, so we don't need to track the newly | |
1394 | * allocated tables below the pdp */ | |
1395 | bitmap_zero(new_pdps, GEN8_PML4ES_PER_PML4); | |
1396 | ||
1397 | /* The pagedirectory and pagetable allocations are done in the shared 3 | |
1398 | * and 4 level code. Just allocate the pdps. | |
1399 | */ | |
1400 | ret = gen8_ppgtt_alloc_page_dirpointers(vm, pml4, start, length, | |
1401 | new_pdps); | |
1402 | if (ret) | |
1403 | return ret; | |
1404 | ||
1405 | WARN(bitmap_weight(new_pdps, GEN8_PML4ES_PER_PML4) > 2, | |
1406 | "The allocation has spanned more than 512GB. " | |
1407 | "It is highly likely this is incorrect."); | |
1408 | ||
e8ebd8e2 | 1409 | gen8_for_each_pml4e(pdp, pml4, start, length, pml4e) { |
762d9936 MT |
1410 | WARN_ON(!pdp); |
1411 | ||
1412 | ret = gen8_alloc_va_range_3lvl(vm, pdp, start, length); | |
1413 | if (ret) | |
1414 | goto err_out; | |
1415 | ||
56843107 | 1416 | gen8_setup_pml4e(ppgtt, pml4, pdp, pml4e); |
762d9936 MT |
1417 | } |
1418 | ||
1419 | bitmap_or(pml4->used_pml4es, new_pdps, pml4->used_pml4es, | |
1420 | GEN8_PML4ES_PER_PML4); | |
1421 | ||
1422 | return 0; | |
1423 | ||
1424 | err_out: | |
1425 | for_each_set_bit(pml4e, new_pdps, GEN8_PML4ES_PER_PML4) | |
49d73912 | 1426 | gen8_ppgtt_cleanup_3lvl(vm->i915, pml4->pdps[pml4e]); |
762d9936 MT |
1427 | |
1428 | return ret; | |
1429 | } | |
1430 | ||
1431 | static int gen8_alloc_va_range(struct i915_address_space *vm, | |
1432 | uint64_t start, uint64_t length) | |
1433 | { | |
e5716f55 | 1434 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
762d9936 | 1435 | |
c6385c94 | 1436 | if (USES_FULL_48BIT_PPGTT(vm->i915)) |
762d9936 MT |
1437 | return gen8_alloc_va_range_4lvl(vm, &ppgtt->pml4, start, length); |
1438 | else | |
1439 | return gen8_alloc_va_range_3lvl(vm, &ppgtt->pdp, start, length); | |
1440 | } | |
1441 | ||
ea91e401 MT |
1442 | static void gen8_dump_pdp(struct i915_page_directory_pointer *pdp, |
1443 | uint64_t start, uint64_t length, | |
1444 | gen8_pte_t scratch_pte, | |
1445 | struct seq_file *m) | |
1446 | { | |
1447 | struct i915_page_directory *pd; | |
ea91e401 MT |
1448 | uint32_t pdpe; |
1449 | ||
e8ebd8e2 | 1450 | gen8_for_each_pdpe(pd, pdp, start, length, pdpe) { |
ea91e401 MT |
1451 | struct i915_page_table *pt; |
1452 | uint64_t pd_len = length; | |
1453 | uint64_t pd_start = start; | |
1454 | uint32_t pde; | |
1455 | ||
1456 | if (!test_bit(pdpe, pdp->used_pdpes)) | |
1457 | continue; | |
1458 | ||
1459 | seq_printf(m, "\tPDPE #%d\n", pdpe); | |
e8ebd8e2 | 1460 | gen8_for_each_pde(pt, pd, pd_start, pd_len, pde) { |
ea91e401 MT |
1461 | uint32_t pte; |
1462 | gen8_pte_t *pt_vaddr; | |
1463 | ||
1464 | if (!test_bit(pde, pd->used_pdes)) | |
1465 | continue; | |
1466 | ||
1467 | pt_vaddr = kmap_px(pt); | |
1468 | for (pte = 0; pte < GEN8_PTES; pte += 4) { | |
1469 | uint64_t va = | |
1470 | (pdpe << GEN8_PDPE_SHIFT) | | |
1471 | (pde << GEN8_PDE_SHIFT) | | |
1472 | (pte << GEN8_PTE_SHIFT); | |
1473 | int i; | |
1474 | bool found = false; | |
1475 | ||
1476 | for (i = 0; i < 4; i++) | |
1477 | if (pt_vaddr[pte + i] != scratch_pte) | |
1478 | found = true; | |
1479 | if (!found) | |
1480 | continue; | |
1481 | ||
1482 | seq_printf(m, "\t\t0x%llx [%03d,%03d,%04d]: =", va, pdpe, pde, pte); | |
1483 | for (i = 0; i < 4; i++) { | |
1484 | if (pt_vaddr[pte + i] != scratch_pte) | |
1485 | seq_printf(m, " %llx", pt_vaddr[pte + i]); | |
1486 | else | |
1487 | seq_puts(m, " SCRATCH "); | |
1488 | } | |
1489 | seq_puts(m, "\n"); | |
1490 | } | |
1491 | /* don't use kunmap_px, it could trigger | |
1492 | * an unnecessary flush. | |
1493 | */ | |
1494 | kunmap_atomic(pt_vaddr); | |
1495 | } | |
1496 | } | |
1497 | } | |
1498 | ||
1499 | static void gen8_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m) | |
1500 | { | |
1501 | struct i915_address_space *vm = &ppgtt->base; | |
1502 | uint64_t start = ppgtt->base.start; | |
1503 | uint64_t length = ppgtt->base.total; | |
8bcdd0f7 | 1504 | gen8_pte_t scratch_pte = gen8_pte_encode(vm->scratch_page.daddr, |
4fb84d99 | 1505 | I915_CACHE_LLC); |
ea91e401 | 1506 | |
c6385c94 | 1507 | if (!USES_FULL_48BIT_PPGTT(vm->i915)) { |
ea91e401 MT |
1508 | gen8_dump_pdp(&ppgtt->pdp, start, length, scratch_pte, m); |
1509 | } else { | |
e8ebd8e2 | 1510 | uint64_t pml4e; |
ea91e401 MT |
1511 | struct i915_pml4 *pml4 = &ppgtt->pml4; |
1512 | struct i915_page_directory_pointer *pdp; | |
1513 | ||
e8ebd8e2 | 1514 | gen8_for_each_pml4e(pdp, pml4, start, length, pml4e) { |
ea91e401 MT |
1515 | if (!test_bit(pml4e, pml4->used_pml4es)) |
1516 | continue; | |
1517 | ||
1518 | seq_printf(m, " PML4E #%llu\n", pml4e); | |
1519 | gen8_dump_pdp(pdp, start, length, scratch_pte, m); | |
1520 | } | |
1521 | } | |
1522 | } | |
1523 | ||
331f38e7 ZL |
1524 | static int gen8_preallocate_top_level_pdps(struct i915_hw_ppgtt *ppgtt) |
1525 | { | |
3a41a05d | 1526 | unsigned long *new_page_dirs, *new_page_tables; |
275a991c | 1527 | uint32_t pdpes = I915_PDPES_PER_PDP(to_i915(ppgtt->base.dev)); |
331f38e7 ZL |
1528 | int ret; |
1529 | ||
1530 | /* We allocate temp bitmap for page tables for no gain | |
1531 | * but as this is for init only, lets keep the things simple | |
1532 | */ | |
1533 | ret = alloc_gen8_temp_bitmaps(&new_page_dirs, &new_page_tables, pdpes); | |
1534 | if (ret) | |
1535 | return ret; | |
1536 | ||
1537 | /* Allocate for all pdps regardless of how the ppgtt | |
1538 | * was defined. | |
1539 | */ | |
1540 | ret = gen8_ppgtt_alloc_page_directories(&ppgtt->base, &ppgtt->pdp, | |
1541 | 0, 1ULL << 32, | |
1542 | new_page_dirs); | |
1543 | if (!ret) | |
1544 | *ppgtt->pdp.used_pdpes = *new_page_dirs; | |
1545 | ||
3a41a05d | 1546 | free_gen8_temp_bitmaps(new_page_dirs, new_page_tables); |
331f38e7 ZL |
1547 | |
1548 | return ret; | |
1549 | } | |
1550 | ||
eb0b44ad | 1551 | /* |
f3a964b9 BW |
1552 | * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers |
1553 | * with a net effect resembling a 2-level page table in normal x86 terms. Each | |
1554 | * PDP represents 1GB of memory 4 * 512 * 512 * 4096 = 4GB legacy 32b address | |
1555 | * space. | |
37aca44a | 1556 | * |
f3a964b9 | 1557 | */ |
5c5f6457 | 1558 | static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt) |
37aca44a | 1559 | { |
49d73912 | 1560 | struct drm_i915_private *dev_priv = ppgtt->base.i915; |
8776f02b | 1561 | int ret; |
7cb6d7ac | 1562 | |
8776f02b MK |
1563 | ret = gen8_init_scratch(&ppgtt->base); |
1564 | if (ret) | |
1565 | return ret; | |
69876bed | 1566 | |
d7b2633d | 1567 | ppgtt->base.start = 0; |
d7b2633d | 1568 | ppgtt->base.cleanup = gen8_ppgtt_cleanup; |
5c5f6457 | 1569 | ppgtt->base.allocate_va_range = gen8_alloc_va_range; |
d7b2633d | 1570 | ppgtt->base.insert_entries = gen8_ppgtt_insert_entries; |
c7e16f22 | 1571 | ppgtt->base.clear_range = gen8_ppgtt_clear_range; |
777dc5bb DV |
1572 | ppgtt->base.unbind_vma = ppgtt_unbind_vma; |
1573 | ppgtt->base.bind_vma = ppgtt_bind_vma; | |
ea91e401 | 1574 | ppgtt->debug_dump = gen8_dump_ppgtt; |
d7b2633d | 1575 | |
275a991c TU |
1576 | if (USES_FULL_48BIT_PPGTT(dev_priv)) { |
1577 | ret = setup_px(dev_priv, &ppgtt->pml4); | |
762d9936 MT |
1578 | if (ret) |
1579 | goto free_scratch; | |
6ac18502 | 1580 | |
69ab76fd MT |
1581 | gen8_initialize_pml4(&ppgtt->base, &ppgtt->pml4); |
1582 | ||
762d9936 | 1583 | ppgtt->base.total = 1ULL << 48; |
2dba3239 | 1584 | ppgtt->switch_mm = gen8_48b_mm_switch; |
762d9936 | 1585 | } else { |
275a991c | 1586 | ret = __pdp_init(dev_priv, &ppgtt->pdp); |
81ba8aef MT |
1587 | if (ret) |
1588 | goto free_scratch; | |
1589 | ||
1590 | ppgtt->base.total = 1ULL << 32; | |
2dba3239 | 1591 | ppgtt->switch_mm = gen8_legacy_mm_switch; |
762d9936 MT |
1592 | trace_i915_page_directory_pointer_entry_alloc(&ppgtt->base, |
1593 | 0, 0, | |
1594 | GEN8_PML4E_SHIFT); | |
331f38e7 | 1595 | |
275a991c | 1596 | if (intel_vgpu_active(dev_priv)) { |
331f38e7 ZL |
1597 | ret = gen8_preallocate_top_level_pdps(ppgtt); |
1598 | if (ret) | |
1599 | goto free_scratch; | |
1600 | } | |
81ba8aef | 1601 | } |
6ac18502 | 1602 | |
275a991c | 1603 | if (intel_vgpu_active(dev_priv)) |
650da34c ZL |
1604 | gen8_ppgtt_notify_vgt(ppgtt, true); |
1605 | ||
d7b2633d | 1606 | return 0; |
6ac18502 MT |
1607 | |
1608 | free_scratch: | |
1609 | gen8_free_scratch(&ppgtt->base); | |
1610 | return ret; | |
d7b2633d MT |
1611 | } |
1612 | ||
87d60b63 BW |
1613 | static void gen6_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m) |
1614 | { | |
87d60b63 | 1615 | struct i915_address_space *vm = &ppgtt->base; |
09942c65 | 1616 | struct i915_page_table *unused; |
07749ef3 | 1617 | gen6_pte_t scratch_pte; |
87d60b63 | 1618 | uint32_t pd_entry; |
731f74c5 | 1619 | uint32_t pte, pde; |
09942c65 | 1620 | uint32_t start = ppgtt->base.start, length = ppgtt->base.total; |
87d60b63 | 1621 | |
8bcdd0f7 | 1622 | scratch_pte = vm->pte_encode(vm->scratch_page.daddr, |
4fb84d99 | 1623 | I915_CACHE_LLC, 0); |
87d60b63 | 1624 | |
731f74c5 | 1625 | gen6_for_each_pde(unused, &ppgtt->pd, start, length, pde) { |
87d60b63 | 1626 | u32 expected; |
07749ef3 | 1627 | gen6_pte_t *pt_vaddr; |
567047be | 1628 | const dma_addr_t pt_addr = px_dma(ppgtt->pd.page_table[pde]); |
09942c65 | 1629 | pd_entry = readl(ppgtt->pd_addr + pde); |
87d60b63 BW |
1630 | expected = (GEN6_PDE_ADDR_ENCODE(pt_addr) | GEN6_PDE_VALID); |
1631 | ||
1632 | if (pd_entry != expected) | |
1633 | seq_printf(m, "\tPDE #%d mismatch: Actual PDE: %x Expected PDE: %x\n", | |
1634 | pde, | |
1635 | pd_entry, | |
1636 | expected); | |
1637 | seq_printf(m, "\tPDE: %x\n", pd_entry); | |
1638 | ||
d1c54acd MK |
1639 | pt_vaddr = kmap_px(ppgtt->pd.page_table[pde]); |
1640 | ||
07749ef3 | 1641 | for (pte = 0; pte < GEN6_PTES; pte+=4) { |
87d60b63 | 1642 | unsigned long va = |
07749ef3 | 1643 | (pde * PAGE_SIZE * GEN6_PTES) + |
87d60b63 BW |
1644 | (pte * PAGE_SIZE); |
1645 | int i; | |
1646 | bool found = false; | |
1647 | for (i = 0; i < 4; i++) | |
1648 | if (pt_vaddr[pte + i] != scratch_pte) | |
1649 | found = true; | |
1650 | if (!found) | |
1651 | continue; | |
1652 | ||
1653 | seq_printf(m, "\t\t0x%lx [%03d,%04d]: =", va, pde, pte); | |
1654 | for (i = 0; i < 4; i++) { | |
1655 | if (pt_vaddr[pte + i] != scratch_pte) | |
1656 | seq_printf(m, " %08x", pt_vaddr[pte + i]); | |
1657 | else | |
1658 | seq_puts(m, " SCRATCH "); | |
1659 | } | |
1660 | seq_puts(m, "\n"); | |
1661 | } | |
d1c54acd | 1662 | kunmap_px(ppgtt, pt_vaddr); |
87d60b63 BW |
1663 | } |
1664 | } | |
1665 | ||
678d96fb | 1666 | /* Write pde (index) from the page directory @pd to the page table @pt */ |
ec565b3c MT |
1667 | static void gen6_write_pde(struct i915_page_directory *pd, |
1668 | const int pde, struct i915_page_table *pt) | |
6197349b | 1669 | { |
678d96fb BW |
1670 | /* Caller needs to make sure the write completes if necessary */ |
1671 | struct i915_hw_ppgtt *ppgtt = | |
1672 | container_of(pd, struct i915_hw_ppgtt, pd); | |
1673 | u32 pd_entry; | |
6197349b | 1674 | |
567047be | 1675 | pd_entry = GEN6_PDE_ADDR_ENCODE(px_dma(pt)); |
678d96fb | 1676 | pd_entry |= GEN6_PDE_VALID; |
6197349b | 1677 | |
678d96fb BW |
1678 | writel(pd_entry, ppgtt->pd_addr + pde); |
1679 | } | |
6197349b | 1680 | |
678d96fb BW |
1681 | /* Write all the page tables found in the ppgtt structure to incrementing page |
1682 | * directories. */ | |
1683 | static void gen6_write_page_range(struct drm_i915_private *dev_priv, | |
ec565b3c | 1684 | struct i915_page_directory *pd, |
678d96fb BW |
1685 | uint32_t start, uint32_t length) |
1686 | { | |
72e96d64 | 1687 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
ec565b3c | 1688 | struct i915_page_table *pt; |
731f74c5 | 1689 | uint32_t pde; |
678d96fb | 1690 | |
731f74c5 | 1691 | gen6_for_each_pde(pt, pd, start, length, pde) |
678d96fb BW |
1692 | gen6_write_pde(pd, pde, pt); |
1693 | ||
1694 | /* Make sure write is complete before other code can use this page | |
1695 | * table. Also require for WC mapped PTEs */ | |
72e96d64 | 1696 | readl(ggtt->gsm); |
3e302542 BW |
1697 | } |
1698 | ||
b4a74e3a | 1699 | static uint32_t get_pd_offset(struct i915_hw_ppgtt *ppgtt) |
3e302542 | 1700 | { |
44159ddb | 1701 | BUG_ON(ppgtt->pd.base.ggtt_offset & 0x3f); |
b4a74e3a | 1702 | |
44159ddb | 1703 | return (ppgtt->pd.base.ggtt_offset / 64) << 16; |
b4a74e3a BW |
1704 | } |
1705 | ||
90252e5c | 1706 | static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt, |
e85b26dc | 1707 | struct drm_i915_gem_request *req) |
90252e5c | 1708 | { |
7e37f889 | 1709 | struct intel_ring *ring = req->ring; |
4a570db5 | 1710 | struct intel_engine_cs *engine = req->engine; |
90252e5c BW |
1711 | int ret; |
1712 | ||
90252e5c | 1713 | /* NB: TLBs must be flushed and invalidated before a switch */ |
7c9cf4e3 | 1714 | ret = engine->emit_flush(req, EMIT_INVALIDATE | EMIT_FLUSH); |
90252e5c BW |
1715 | if (ret) |
1716 | return ret; | |
1717 | ||
5fb9de1a | 1718 | ret = intel_ring_begin(req, 6); |
90252e5c BW |
1719 | if (ret) |
1720 | return ret; | |
1721 | ||
b5321f30 CW |
1722 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2)); |
1723 | intel_ring_emit_reg(ring, RING_PP_DIR_DCLV(engine)); | |
1724 | intel_ring_emit(ring, PP_DIR_DCLV_2G); | |
1725 | intel_ring_emit_reg(ring, RING_PP_DIR_BASE(engine)); | |
1726 | intel_ring_emit(ring, get_pd_offset(ppgtt)); | |
1727 | intel_ring_emit(ring, MI_NOOP); | |
1728 | intel_ring_advance(ring); | |
90252e5c BW |
1729 | |
1730 | return 0; | |
1731 | } | |
1732 | ||
48a10389 | 1733 | static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt, |
e85b26dc | 1734 | struct drm_i915_gem_request *req) |
48a10389 | 1735 | { |
7e37f889 | 1736 | struct intel_ring *ring = req->ring; |
4a570db5 | 1737 | struct intel_engine_cs *engine = req->engine; |
48a10389 BW |
1738 | int ret; |
1739 | ||
48a10389 | 1740 | /* NB: TLBs must be flushed and invalidated before a switch */ |
7c9cf4e3 | 1741 | ret = engine->emit_flush(req, EMIT_INVALIDATE | EMIT_FLUSH); |
48a10389 BW |
1742 | if (ret) |
1743 | return ret; | |
1744 | ||
5fb9de1a | 1745 | ret = intel_ring_begin(req, 6); |
48a10389 BW |
1746 | if (ret) |
1747 | return ret; | |
1748 | ||
b5321f30 CW |
1749 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2)); |
1750 | intel_ring_emit_reg(ring, RING_PP_DIR_DCLV(engine)); | |
1751 | intel_ring_emit(ring, PP_DIR_DCLV_2G); | |
1752 | intel_ring_emit_reg(ring, RING_PP_DIR_BASE(engine)); | |
1753 | intel_ring_emit(ring, get_pd_offset(ppgtt)); | |
1754 | intel_ring_emit(ring, MI_NOOP); | |
1755 | intel_ring_advance(ring); | |
48a10389 | 1756 | |
90252e5c | 1757 | /* XXX: RCS is the only one to auto invalidate the TLBs? */ |
e2f80391 | 1758 | if (engine->id != RCS) { |
7c9cf4e3 | 1759 | ret = engine->emit_flush(req, EMIT_INVALIDATE | EMIT_FLUSH); |
90252e5c BW |
1760 | if (ret) |
1761 | return ret; | |
1762 | } | |
1763 | ||
48a10389 BW |
1764 | return 0; |
1765 | } | |
1766 | ||
eeb9488e | 1767 | static int gen6_mm_switch(struct i915_hw_ppgtt *ppgtt, |
e85b26dc | 1768 | struct drm_i915_gem_request *req) |
eeb9488e | 1769 | { |
4a570db5 | 1770 | struct intel_engine_cs *engine = req->engine; |
8eb95204 | 1771 | struct drm_i915_private *dev_priv = req->i915; |
48a10389 | 1772 | |
e2f80391 TU |
1773 | I915_WRITE(RING_PP_DIR_DCLV(engine), PP_DIR_DCLV_2G); |
1774 | I915_WRITE(RING_PP_DIR_BASE(engine), get_pd_offset(ppgtt)); | |
eeb9488e BW |
1775 | return 0; |
1776 | } | |
1777 | ||
c6be607a | 1778 | static void gen8_ppgtt_enable(struct drm_i915_private *dev_priv) |
eeb9488e | 1779 | { |
e2f80391 | 1780 | struct intel_engine_cs *engine; |
3b3f1650 | 1781 | enum intel_engine_id id; |
3e302542 | 1782 | |
3b3f1650 | 1783 | for_each_engine(engine, dev_priv, id) { |
c6be607a TU |
1784 | u32 four_level = USES_FULL_48BIT_PPGTT(dev_priv) ? |
1785 | GEN8_GFX_PPGTT_48B : 0; | |
e2f80391 | 1786 | I915_WRITE(RING_MODE_GEN7(engine), |
2dba3239 | 1787 | _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE | four_level)); |
eeb9488e | 1788 | } |
eeb9488e | 1789 | } |
6197349b | 1790 | |
c6be607a | 1791 | static void gen7_ppgtt_enable(struct drm_i915_private *dev_priv) |
3e302542 | 1792 | { |
e2f80391 | 1793 | struct intel_engine_cs *engine; |
b4a74e3a | 1794 | uint32_t ecochk, ecobits; |
3b3f1650 | 1795 | enum intel_engine_id id; |
6197349b | 1796 | |
b4a74e3a BW |
1797 | ecobits = I915_READ(GAC_ECO_BITS); |
1798 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B); | |
a65c2fcd | 1799 | |
b4a74e3a | 1800 | ecochk = I915_READ(GAM_ECOCHK); |
772c2a51 | 1801 | if (IS_HASWELL(dev_priv)) { |
b4a74e3a BW |
1802 | ecochk |= ECOCHK_PPGTT_WB_HSW; |
1803 | } else { | |
1804 | ecochk |= ECOCHK_PPGTT_LLC_IVB; | |
1805 | ecochk &= ~ECOCHK_PPGTT_GFDT_IVB; | |
1806 | } | |
1807 | I915_WRITE(GAM_ECOCHK, ecochk); | |
a65c2fcd | 1808 | |
3b3f1650 | 1809 | for_each_engine(engine, dev_priv, id) { |
6197349b | 1810 | /* GFX_MODE is per-ring on gen7+ */ |
e2f80391 | 1811 | I915_WRITE(RING_MODE_GEN7(engine), |
b4a74e3a | 1812 | _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); |
6197349b | 1813 | } |
b4a74e3a | 1814 | } |
6197349b | 1815 | |
c6be607a | 1816 | static void gen6_ppgtt_enable(struct drm_i915_private *dev_priv) |
b4a74e3a | 1817 | { |
b4a74e3a | 1818 | uint32_t ecochk, gab_ctl, ecobits; |
a65c2fcd | 1819 | |
b4a74e3a BW |
1820 | ecobits = I915_READ(GAC_ECO_BITS); |
1821 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT | | |
1822 | ECOBITS_PPGTT_CACHE64B); | |
6197349b | 1823 | |
b4a74e3a BW |
1824 | gab_ctl = I915_READ(GAB_CTL); |
1825 | I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT); | |
1826 | ||
1827 | ecochk = I915_READ(GAM_ECOCHK); | |
1828 | I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B); | |
1829 | ||
1830 | I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
6197349b BW |
1831 | } |
1832 | ||
1d2a314c | 1833 | /* PPGTT support for Sandybdrige/Gen6 and later */ |
853ba5d2 | 1834 | static void gen6_ppgtt_clear_range(struct i915_address_space *vm, |
782f1495 | 1835 | uint64_t start, |
4fb84d99 | 1836 | uint64_t length) |
1d2a314c | 1837 | { |
e5716f55 | 1838 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
07749ef3 | 1839 | gen6_pte_t *pt_vaddr, scratch_pte; |
782f1495 BW |
1840 | unsigned first_entry = start >> PAGE_SHIFT; |
1841 | unsigned num_entries = length >> PAGE_SHIFT; | |
07749ef3 MT |
1842 | unsigned act_pt = first_entry / GEN6_PTES; |
1843 | unsigned first_pte = first_entry % GEN6_PTES; | |
7bddb01f | 1844 | unsigned last_pte, i; |
1d2a314c | 1845 | |
8bcdd0f7 | 1846 | scratch_pte = vm->pte_encode(vm->scratch_page.daddr, |
4fb84d99 | 1847 | I915_CACHE_LLC, 0); |
1d2a314c | 1848 | |
7bddb01f DV |
1849 | while (num_entries) { |
1850 | last_pte = first_pte + num_entries; | |
07749ef3 MT |
1851 | if (last_pte > GEN6_PTES) |
1852 | last_pte = GEN6_PTES; | |
7bddb01f | 1853 | |
d1c54acd | 1854 | pt_vaddr = kmap_px(ppgtt->pd.page_table[act_pt]); |
1d2a314c | 1855 | |
7bddb01f DV |
1856 | for (i = first_pte; i < last_pte; i++) |
1857 | pt_vaddr[i] = scratch_pte; | |
1d2a314c | 1858 | |
d1c54acd | 1859 | kunmap_px(ppgtt, pt_vaddr); |
1d2a314c | 1860 | |
7bddb01f DV |
1861 | num_entries -= last_pte - first_pte; |
1862 | first_pte = 0; | |
a15326a5 | 1863 | act_pt++; |
7bddb01f | 1864 | } |
1d2a314c DV |
1865 | } |
1866 | ||
853ba5d2 | 1867 | static void gen6_ppgtt_insert_entries(struct i915_address_space *vm, |
def886c3 | 1868 | struct sg_table *pages, |
782f1495 | 1869 | uint64_t start, |
24f3a8cf | 1870 | enum i915_cache_level cache_level, u32 flags) |
def886c3 | 1871 | { |
e5716f55 | 1872 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
782f1495 | 1873 | unsigned first_entry = start >> PAGE_SHIFT; |
07749ef3 MT |
1874 | unsigned act_pt = first_entry / GEN6_PTES; |
1875 | unsigned act_pte = first_entry % GEN6_PTES; | |
85d1225e DG |
1876 | gen6_pte_t *pt_vaddr = NULL; |
1877 | struct sgt_iter sgt_iter; | |
1878 | dma_addr_t addr; | |
6e995e23 | 1879 | |
85d1225e | 1880 | for_each_sgt_dma(addr, sgt_iter, pages) { |
cc79714f | 1881 | if (pt_vaddr == NULL) |
d1c54acd | 1882 | pt_vaddr = kmap_px(ppgtt->pd.page_table[act_pt]); |
6e995e23 | 1883 | |
cc79714f | 1884 | pt_vaddr[act_pte] = |
4fb84d99 | 1885 | vm->pte_encode(addr, cache_level, flags); |
24f3a8cf | 1886 | |
07749ef3 | 1887 | if (++act_pte == GEN6_PTES) { |
d1c54acd | 1888 | kunmap_px(ppgtt, pt_vaddr); |
cc79714f | 1889 | pt_vaddr = NULL; |
a15326a5 | 1890 | act_pt++; |
6e995e23 | 1891 | act_pte = 0; |
def886c3 | 1892 | } |
def886c3 | 1893 | } |
85d1225e | 1894 | |
cc79714f | 1895 | if (pt_vaddr) |
d1c54acd | 1896 | kunmap_px(ppgtt, pt_vaddr); |
def886c3 DV |
1897 | } |
1898 | ||
678d96fb | 1899 | static int gen6_alloc_va_range(struct i915_address_space *vm, |
a05d80ee | 1900 | uint64_t start_in, uint64_t length_in) |
678d96fb | 1901 | { |
4933d519 | 1902 | DECLARE_BITMAP(new_page_tables, I915_PDES); |
49d73912 | 1903 | struct drm_i915_private *dev_priv = vm->i915; |
72e96d64 | 1904 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
e5716f55 | 1905 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
ec565b3c | 1906 | struct i915_page_table *pt; |
a05d80ee | 1907 | uint32_t start, length, start_save, length_save; |
731f74c5 | 1908 | uint32_t pde; |
4933d519 MT |
1909 | int ret; |
1910 | ||
a05d80ee MK |
1911 | start = start_save = start_in; |
1912 | length = length_save = length_in; | |
4933d519 MT |
1913 | |
1914 | bitmap_zero(new_page_tables, I915_PDES); | |
1915 | ||
1916 | /* The allocation is done in two stages so that we can bail out with | |
1917 | * minimal amount of pain. The first stage finds new page tables that | |
1918 | * need allocation. The second stage marks use ptes within the page | |
1919 | * tables. | |
1920 | */ | |
731f74c5 | 1921 | gen6_for_each_pde(pt, &ppgtt->pd, start, length, pde) { |
79ab9370 | 1922 | if (pt != vm->scratch_pt) { |
4933d519 MT |
1923 | WARN_ON(bitmap_empty(pt->used_ptes, GEN6_PTES)); |
1924 | continue; | |
1925 | } | |
1926 | ||
1927 | /* We've already allocated a page table */ | |
1928 | WARN_ON(!bitmap_empty(pt->used_ptes, GEN6_PTES)); | |
1929 | ||
275a991c | 1930 | pt = alloc_pt(dev_priv); |
4933d519 MT |
1931 | if (IS_ERR(pt)) { |
1932 | ret = PTR_ERR(pt); | |
1933 | goto unwind_out; | |
1934 | } | |
1935 | ||
1936 | gen6_initialize_pt(vm, pt); | |
1937 | ||
1938 | ppgtt->pd.page_table[pde] = pt; | |
966082c9 | 1939 | __set_bit(pde, new_page_tables); |
72744cb1 | 1940 | trace_i915_page_table_entry_alloc(vm, pde, start, GEN6_PDE_SHIFT); |
4933d519 MT |
1941 | } |
1942 | ||
1943 | start = start_save; | |
1944 | length = length_save; | |
678d96fb | 1945 | |
731f74c5 | 1946 | gen6_for_each_pde(pt, &ppgtt->pd, start, length, pde) { |
678d96fb BW |
1947 | DECLARE_BITMAP(tmp_bitmap, GEN6_PTES); |
1948 | ||
1949 | bitmap_zero(tmp_bitmap, GEN6_PTES); | |
1950 | bitmap_set(tmp_bitmap, gen6_pte_index(start), | |
1951 | gen6_pte_count(start, length)); | |
1952 | ||
966082c9 | 1953 | if (__test_and_clear_bit(pde, new_page_tables)) |
4933d519 MT |
1954 | gen6_write_pde(&ppgtt->pd, pde, pt); |
1955 | ||
72744cb1 MT |
1956 | trace_i915_page_table_entry_map(vm, pde, pt, |
1957 | gen6_pte_index(start), | |
1958 | gen6_pte_count(start, length), | |
1959 | GEN6_PTES); | |
4933d519 | 1960 | bitmap_or(pt->used_ptes, tmp_bitmap, pt->used_ptes, |
678d96fb BW |
1961 | GEN6_PTES); |
1962 | } | |
1963 | ||
4933d519 MT |
1964 | WARN_ON(!bitmap_empty(new_page_tables, I915_PDES)); |
1965 | ||
1966 | /* Make sure write is complete before other code can use this page | |
1967 | * table. Also require for WC mapped PTEs */ | |
72e96d64 | 1968 | readl(ggtt->gsm); |
4933d519 | 1969 | |
563222a7 | 1970 | mark_tlbs_dirty(ppgtt); |
678d96fb | 1971 | return 0; |
4933d519 MT |
1972 | |
1973 | unwind_out: | |
1974 | for_each_set_bit(pde, new_page_tables, I915_PDES) { | |
ec565b3c | 1975 | struct i915_page_table *pt = ppgtt->pd.page_table[pde]; |
4933d519 | 1976 | |
79ab9370 | 1977 | ppgtt->pd.page_table[pde] = vm->scratch_pt; |
275a991c | 1978 | free_pt(dev_priv, pt); |
4933d519 MT |
1979 | } |
1980 | ||
1981 | mark_tlbs_dirty(ppgtt); | |
1982 | return ret; | |
678d96fb BW |
1983 | } |
1984 | ||
8776f02b MK |
1985 | static int gen6_init_scratch(struct i915_address_space *vm) |
1986 | { | |
49d73912 | 1987 | struct drm_i915_private *dev_priv = vm->i915; |
8bcdd0f7 | 1988 | int ret; |
8776f02b | 1989 | |
275a991c | 1990 | ret = setup_scratch_page(dev_priv, &vm->scratch_page, I915_GFP_DMA); |
8bcdd0f7 CW |
1991 | if (ret) |
1992 | return ret; | |
8776f02b | 1993 | |
275a991c | 1994 | vm->scratch_pt = alloc_pt(dev_priv); |
8776f02b | 1995 | if (IS_ERR(vm->scratch_pt)) { |
275a991c | 1996 | cleanup_scratch_page(dev_priv, &vm->scratch_page); |
8776f02b MK |
1997 | return PTR_ERR(vm->scratch_pt); |
1998 | } | |
1999 | ||
2000 | gen6_initialize_pt(vm, vm->scratch_pt); | |
2001 | ||
2002 | return 0; | |
2003 | } | |
2004 | ||
2005 | static void gen6_free_scratch(struct i915_address_space *vm) | |
2006 | { | |
49d73912 | 2007 | struct drm_i915_private *dev_priv = vm->i915; |
8776f02b | 2008 | |
275a991c TU |
2009 | free_pt(dev_priv, vm->scratch_pt); |
2010 | cleanup_scratch_page(dev_priv, &vm->scratch_page); | |
8776f02b MK |
2011 | } |
2012 | ||
061dd493 | 2013 | static void gen6_ppgtt_cleanup(struct i915_address_space *vm) |
a00d825d | 2014 | { |
e5716f55 | 2015 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
731f74c5 | 2016 | struct i915_page_directory *pd = &ppgtt->pd; |
49d73912 | 2017 | struct drm_i915_private *dev_priv = vm->i915; |
09942c65 MT |
2018 | struct i915_page_table *pt; |
2019 | uint32_t pde; | |
4933d519 | 2020 | |
061dd493 DV |
2021 | drm_mm_remove_node(&ppgtt->node); |
2022 | ||
731f74c5 | 2023 | gen6_for_all_pdes(pt, pd, pde) |
79ab9370 | 2024 | if (pt != vm->scratch_pt) |
275a991c | 2025 | free_pt(dev_priv, pt); |
06fda602 | 2026 | |
8776f02b | 2027 | gen6_free_scratch(vm); |
3440d265 DV |
2028 | } |
2029 | ||
b146520f | 2030 | static int gen6_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt) |
3440d265 | 2031 | { |
8776f02b | 2032 | struct i915_address_space *vm = &ppgtt->base; |
49d73912 | 2033 | struct drm_i915_private *dev_priv = ppgtt->base.i915; |
72e96d64 | 2034 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
e3cc1995 | 2035 | bool retried = false; |
b146520f | 2036 | int ret; |
1d2a314c | 2037 | |
c8d4c0d6 BW |
2038 | /* PPGTT PDEs reside in the GGTT and consists of 512 entries. The |
2039 | * allocator works in address space sizes, so it's multiplied by page | |
2040 | * size. We allocate at the top of the GTT to avoid fragmentation. | |
2041 | */ | |
72e96d64 | 2042 | BUG_ON(!drm_mm_initialized(&ggtt->base.mm)); |
4933d519 | 2043 | |
8776f02b MK |
2044 | ret = gen6_init_scratch(vm); |
2045 | if (ret) | |
2046 | return ret; | |
4933d519 | 2047 | |
e3cc1995 | 2048 | alloc: |
85fd4f58 CW |
2049 | ret = drm_mm_insert_node_in_range_generic(&ggtt->base.mm, &ppgtt->node, |
2050 | GEN6_PD_SIZE, GEN6_PD_ALIGN, | |
2051 | I915_COLOR_UNEVICTABLE, | |
72e96d64 | 2052 | 0, ggtt->base.total, |
3e8b5ae9 | 2053 | DRM_MM_TOPDOWN); |
e3cc1995 | 2054 | if (ret == -ENOSPC && !retried) { |
e522ac23 | 2055 | ret = i915_gem_evict_something(&ggtt->base, |
e3cc1995 | 2056 | GEN6_PD_SIZE, GEN6_PD_ALIGN, |
85fd4f58 | 2057 | I915_COLOR_UNEVICTABLE, |
72e96d64 | 2058 | 0, ggtt->base.total, |
d23db88c | 2059 | 0); |
e3cc1995 | 2060 | if (ret) |
678d96fb | 2061 | goto err_out; |
e3cc1995 BW |
2062 | |
2063 | retried = true; | |
2064 | goto alloc; | |
2065 | } | |
c8d4c0d6 | 2066 | |
c8c26622 | 2067 | if (ret) |
678d96fb BW |
2068 | goto err_out; |
2069 | ||
c8c26622 | 2070 | |
72e96d64 | 2071 | if (ppgtt->node.start < ggtt->mappable_end) |
c8d4c0d6 | 2072 | DRM_DEBUG("Forced to use aperture for PDEs\n"); |
1d2a314c | 2073 | |
c8c26622 | 2074 | return 0; |
678d96fb BW |
2075 | |
2076 | err_out: | |
8776f02b | 2077 | gen6_free_scratch(vm); |
678d96fb | 2078 | return ret; |
b146520f BW |
2079 | } |
2080 | ||
b146520f BW |
2081 | static int gen6_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt) |
2082 | { | |
2f2cf682 | 2083 | return gen6_ppgtt_allocate_page_directories(ppgtt); |
4933d519 | 2084 | } |
06dc68d6 | 2085 | |
4933d519 MT |
2086 | static void gen6_scratch_va_range(struct i915_hw_ppgtt *ppgtt, |
2087 | uint64_t start, uint64_t length) | |
2088 | { | |
ec565b3c | 2089 | struct i915_page_table *unused; |
731f74c5 | 2090 | uint32_t pde; |
1d2a314c | 2091 | |
731f74c5 | 2092 | gen6_for_each_pde(unused, &ppgtt->pd, start, length, pde) |
79ab9370 | 2093 | ppgtt->pd.page_table[pde] = ppgtt->base.scratch_pt; |
b146520f BW |
2094 | } |
2095 | ||
5c5f6457 | 2096 | static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt) |
b146520f | 2097 | { |
49d73912 | 2098 | struct drm_i915_private *dev_priv = ppgtt->base.i915; |
72e96d64 | 2099 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
b146520f BW |
2100 | int ret; |
2101 | ||
72e96d64 | 2102 | ppgtt->base.pte_encode = ggtt->base.pte_encode; |
5db94019 | 2103 | if (intel_vgpu_active(dev_priv) || IS_GEN6(dev_priv)) |
b146520f | 2104 | ppgtt->switch_mm = gen6_mm_switch; |
772c2a51 | 2105 | else if (IS_HASWELL(dev_priv)) |
b146520f | 2106 | ppgtt->switch_mm = hsw_mm_switch; |
5db94019 | 2107 | else if (IS_GEN7(dev_priv)) |
b146520f | 2108 | ppgtt->switch_mm = gen7_mm_switch; |
8eb95204 | 2109 | else |
b146520f BW |
2110 | BUG(); |
2111 | ||
2112 | ret = gen6_ppgtt_alloc(ppgtt); | |
2113 | if (ret) | |
2114 | return ret; | |
2115 | ||
5c5f6457 | 2116 | ppgtt->base.allocate_va_range = gen6_alloc_va_range; |
b146520f BW |
2117 | ppgtt->base.clear_range = gen6_ppgtt_clear_range; |
2118 | ppgtt->base.insert_entries = gen6_ppgtt_insert_entries; | |
777dc5bb DV |
2119 | ppgtt->base.unbind_vma = ppgtt_unbind_vma; |
2120 | ppgtt->base.bind_vma = ppgtt_bind_vma; | |
b146520f | 2121 | ppgtt->base.cleanup = gen6_ppgtt_cleanup; |
b146520f | 2122 | ppgtt->base.start = 0; |
09942c65 | 2123 | ppgtt->base.total = I915_PDES * GEN6_PTES * PAGE_SIZE; |
87d60b63 | 2124 | ppgtt->debug_dump = gen6_dump_ppgtt; |
1d2a314c | 2125 | |
44159ddb | 2126 | ppgtt->pd.base.ggtt_offset = |
07749ef3 | 2127 | ppgtt->node.start / PAGE_SIZE * sizeof(gen6_pte_t); |
1d2a314c | 2128 | |
72e96d64 | 2129 | ppgtt->pd_addr = (gen6_pte_t __iomem *)ggtt->gsm + |
44159ddb | 2130 | ppgtt->pd.base.ggtt_offset / sizeof(gen6_pte_t); |
678d96fb | 2131 | |
5c5f6457 | 2132 | gen6_scratch_va_range(ppgtt, 0, ppgtt->base.total); |
1d2a314c | 2133 | |
678d96fb BW |
2134 | gen6_write_page_range(dev_priv, &ppgtt->pd, 0, ppgtt->base.total); |
2135 | ||
440fd528 | 2136 | DRM_DEBUG_DRIVER("Allocated pde space (%lldM) at GTT entry: %llx\n", |
b146520f BW |
2137 | ppgtt->node.size >> 20, |
2138 | ppgtt->node.start / PAGE_SIZE); | |
3440d265 | 2139 | |
fa76da34 | 2140 | DRM_DEBUG("Adding PPGTT at offset %x\n", |
44159ddb | 2141 | ppgtt->pd.base.ggtt_offset << 10); |
fa76da34 | 2142 | |
b146520f | 2143 | return 0; |
3440d265 DV |
2144 | } |
2145 | ||
2bfa996e CW |
2146 | static int __hw_ppgtt_init(struct i915_hw_ppgtt *ppgtt, |
2147 | struct drm_i915_private *dev_priv) | |
3440d265 | 2148 | { |
49d73912 | 2149 | ppgtt->base.i915 = dev_priv; |
3440d265 | 2150 | |
2bfa996e | 2151 | if (INTEL_INFO(dev_priv)->gen < 8) |
5c5f6457 | 2152 | return gen6_ppgtt_init(ppgtt); |
3ed124b2 | 2153 | else |
d7b2633d | 2154 | return gen8_ppgtt_init(ppgtt); |
fa76da34 | 2155 | } |
c114f76a | 2156 | |
a2cad9df | 2157 | static void i915_address_space_init(struct i915_address_space *vm, |
80b204bc CW |
2158 | struct drm_i915_private *dev_priv, |
2159 | const char *name) | |
a2cad9df | 2160 | { |
80b204bc | 2161 | i915_gem_timeline_init(dev_priv, &vm->timeline, name); |
a2cad9df | 2162 | drm_mm_init(&vm->mm, vm->start, vm->total); |
a2cad9df MW |
2163 | INIT_LIST_HEAD(&vm->active_list); |
2164 | INIT_LIST_HEAD(&vm->inactive_list); | |
50e046b6 | 2165 | INIT_LIST_HEAD(&vm->unbound_list); |
a2cad9df MW |
2166 | list_add_tail(&vm->global_link, &dev_priv->vm_list); |
2167 | } | |
2168 | ||
ed9724dd MA |
2169 | static void i915_address_space_fini(struct i915_address_space *vm) |
2170 | { | |
2171 | i915_gem_timeline_fini(&vm->timeline); | |
2172 | drm_mm_takedown(&vm->mm); | |
2173 | list_del(&vm->global_link); | |
2174 | } | |
2175 | ||
c6be607a | 2176 | static void gtt_write_workarounds(struct drm_i915_private *dev_priv) |
d5165ebd | 2177 | { |
d5165ebd TG |
2178 | /* This function is for gtt related workarounds. This function is |
2179 | * called on driver load and after a GPU reset, so you can place | |
2180 | * workarounds here even if they get overwritten by GPU reset. | |
2181 | */ | |
2182 | /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt */ | |
8652744b | 2183 | if (IS_BROADWELL(dev_priv)) |
d5165ebd | 2184 | I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW); |
920a14b2 | 2185 | else if (IS_CHERRYVIEW(dev_priv)) |
d5165ebd | 2186 | I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV); |
d9486e65 | 2187 | else if (IS_SKYLAKE(dev_priv)) |
d5165ebd | 2188 | I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL); |
e2d214ae | 2189 | else if (IS_BROXTON(dev_priv)) |
d5165ebd TG |
2190 | I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT); |
2191 | } | |
2192 | ||
2bfa996e CW |
2193 | static int i915_ppgtt_init(struct i915_hw_ppgtt *ppgtt, |
2194 | struct drm_i915_private *dev_priv, | |
80b204bc CW |
2195 | struct drm_i915_file_private *file_priv, |
2196 | const char *name) | |
fa76da34 | 2197 | { |
2bfa996e | 2198 | int ret; |
3ed124b2 | 2199 | |
2bfa996e | 2200 | ret = __hw_ppgtt_init(ppgtt, dev_priv); |
fa76da34 | 2201 | if (ret == 0) { |
c7c48dfd | 2202 | kref_init(&ppgtt->ref); |
80b204bc | 2203 | i915_address_space_init(&ppgtt->base, dev_priv, name); |
2bfa996e | 2204 | ppgtt->base.file = file_priv; |
93bd8649 | 2205 | } |
1d2a314c DV |
2206 | |
2207 | return ret; | |
2208 | } | |
2209 | ||
c6be607a | 2210 | int i915_ppgtt_init_hw(struct drm_i915_private *dev_priv) |
82460d97 | 2211 | { |
c6be607a | 2212 | gtt_write_workarounds(dev_priv); |
d5165ebd | 2213 | |
671b5013 TD |
2214 | /* In the case of execlists, PPGTT is enabled by the context descriptor |
2215 | * and the PDPs are contained within the context itself. We don't | |
2216 | * need to do anything here. */ | |
2217 | if (i915.enable_execlists) | |
2218 | return 0; | |
2219 | ||
c6be607a | 2220 | if (!USES_PPGTT(dev_priv)) |
82460d97 DV |
2221 | return 0; |
2222 | ||
5db94019 | 2223 | if (IS_GEN6(dev_priv)) |
c6be607a | 2224 | gen6_ppgtt_enable(dev_priv); |
5db94019 | 2225 | else if (IS_GEN7(dev_priv)) |
c6be607a TU |
2226 | gen7_ppgtt_enable(dev_priv); |
2227 | else if (INTEL_GEN(dev_priv) >= 8) | |
2228 | gen8_ppgtt_enable(dev_priv); | |
82460d97 | 2229 | else |
c6be607a | 2230 | MISSING_CASE(INTEL_GEN(dev_priv)); |
82460d97 | 2231 | |
4ad2fd88 JH |
2232 | return 0; |
2233 | } | |
1d2a314c | 2234 | |
4d884705 | 2235 | struct i915_hw_ppgtt * |
2bfa996e | 2236 | i915_ppgtt_create(struct drm_i915_private *dev_priv, |
80b204bc CW |
2237 | struct drm_i915_file_private *fpriv, |
2238 | const char *name) | |
4d884705 DV |
2239 | { |
2240 | struct i915_hw_ppgtt *ppgtt; | |
2241 | int ret; | |
2242 | ||
2243 | ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL); | |
2244 | if (!ppgtt) | |
2245 | return ERR_PTR(-ENOMEM); | |
2246 | ||
80b204bc | 2247 | ret = i915_ppgtt_init(ppgtt, dev_priv, fpriv, name); |
4d884705 DV |
2248 | if (ret) { |
2249 | kfree(ppgtt); | |
2250 | return ERR_PTR(ret); | |
2251 | } | |
2252 | ||
198c974d DCS |
2253 | trace_i915_ppgtt_create(&ppgtt->base); |
2254 | ||
4d884705 DV |
2255 | return ppgtt; |
2256 | } | |
2257 | ||
ed9724dd | 2258 | void i915_ppgtt_release(struct kref *kref) |
ee960be7 DV |
2259 | { |
2260 | struct i915_hw_ppgtt *ppgtt = | |
2261 | container_of(kref, struct i915_hw_ppgtt, ref); | |
2262 | ||
198c974d DCS |
2263 | trace_i915_ppgtt_release(&ppgtt->base); |
2264 | ||
50e046b6 | 2265 | /* vmas should already be unbound and destroyed */ |
ee960be7 DV |
2266 | WARN_ON(!list_empty(&ppgtt->base.active_list)); |
2267 | WARN_ON(!list_empty(&ppgtt->base.inactive_list)); | |
50e046b6 | 2268 | WARN_ON(!list_empty(&ppgtt->base.unbound_list)); |
ee960be7 | 2269 | |
ed9724dd | 2270 | i915_address_space_fini(&ppgtt->base); |
19dd120c | 2271 | |
ee960be7 DV |
2272 | ppgtt->base.cleanup(&ppgtt->base); |
2273 | kfree(ppgtt); | |
2274 | } | |
1d2a314c | 2275 | |
a81cc00c BW |
2276 | /* Certain Gen5 chipsets require require idling the GPU before |
2277 | * unmapping anything from the GTT when VT-d is enabled. | |
2278 | */ | |
97d6d7ab | 2279 | static bool needs_idle_maps(struct drm_i915_private *dev_priv) |
a81cc00c BW |
2280 | { |
2281 | #ifdef CONFIG_INTEL_IOMMU | |
2282 | /* Query intel_iommu to see if we need the workaround. Presumably that | |
2283 | * was loaded first. | |
2284 | */ | |
97d6d7ab | 2285 | if (IS_GEN5(dev_priv) && IS_MOBILE(dev_priv) && intel_iommu_gfx_mapped) |
a81cc00c BW |
2286 | return true; |
2287 | #endif | |
2288 | return false; | |
2289 | } | |
2290 | ||
dc97997a | 2291 | void i915_check_and_clear_faults(struct drm_i915_private *dev_priv) |
828c7908 | 2292 | { |
e2f80391 | 2293 | struct intel_engine_cs *engine; |
3b3f1650 | 2294 | enum intel_engine_id id; |
828c7908 | 2295 | |
dc97997a | 2296 | if (INTEL_INFO(dev_priv)->gen < 6) |
828c7908 BW |
2297 | return; |
2298 | ||
3b3f1650 | 2299 | for_each_engine(engine, dev_priv, id) { |
828c7908 | 2300 | u32 fault_reg; |
e2f80391 | 2301 | fault_reg = I915_READ(RING_FAULT_REG(engine)); |
828c7908 BW |
2302 | if (fault_reg & RING_FAULT_VALID) { |
2303 | DRM_DEBUG_DRIVER("Unexpected fault\n" | |
59a5d290 | 2304 | "\tAddr: 0x%08lx\n" |
828c7908 BW |
2305 | "\tAddress space: %s\n" |
2306 | "\tSource ID: %d\n" | |
2307 | "\tType: %d\n", | |
2308 | fault_reg & PAGE_MASK, | |
2309 | fault_reg & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT", | |
2310 | RING_FAULT_SRCID(fault_reg), | |
2311 | RING_FAULT_FAULT_TYPE(fault_reg)); | |
e2f80391 | 2312 | I915_WRITE(RING_FAULT_REG(engine), |
828c7908 BW |
2313 | fault_reg & ~RING_FAULT_VALID); |
2314 | } | |
2315 | } | |
3b3f1650 AG |
2316 | |
2317 | /* Engine specific init may not have been done till this point. */ | |
2318 | if (dev_priv->engine[RCS]) | |
2319 | POSTING_READ(RING_FAULT_REG(dev_priv->engine[RCS])); | |
828c7908 BW |
2320 | } |
2321 | ||
91e56499 CW |
2322 | static void i915_ggtt_flush(struct drm_i915_private *dev_priv) |
2323 | { | |
2d1fe073 | 2324 | if (INTEL_INFO(dev_priv)->gen < 6) { |
91e56499 CW |
2325 | intel_gtt_chipset_flush(); |
2326 | } else { | |
2327 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
2328 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
2329 | } | |
2330 | } | |
2331 | ||
275a991c | 2332 | void i915_gem_suspend_gtt_mappings(struct drm_i915_private *dev_priv) |
828c7908 | 2333 | { |
72e96d64 | 2334 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
828c7908 BW |
2335 | |
2336 | /* Don't bother messing with faults pre GEN6 as we have little | |
2337 | * documentation supporting that it's a good idea. | |
2338 | */ | |
275a991c | 2339 | if (INTEL_GEN(dev_priv) < 6) |
828c7908 BW |
2340 | return; |
2341 | ||
dc97997a | 2342 | i915_check_and_clear_faults(dev_priv); |
828c7908 | 2343 | |
4fb84d99 | 2344 | ggtt->base.clear_range(&ggtt->base, ggtt->base.start, ggtt->base.total); |
91e56499 CW |
2345 | |
2346 | i915_ggtt_flush(dev_priv); | |
828c7908 BW |
2347 | } |
2348 | ||
03ac84f1 CW |
2349 | int i915_gem_gtt_prepare_pages(struct drm_i915_gem_object *obj, |
2350 | struct sg_table *pages) | |
7c2e6fdf | 2351 | { |
1a292fa5 CW |
2352 | do { |
2353 | if (dma_map_sg(&obj->base.dev->pdev->dev, | |
2354 | pages->sgl, pages->nents, | |
2355 | PCI_DMA_BIDIRECTIONAL)) | |
2356 | return 0; | |
2357 | ||
2358 | /* If the DMA remap fails, one cause can be that we have | |
2359 | * too many objects pinned in a small remapping table, | |
2360 | * such as swiotlb. Incrementally purge all other objects and | |
2361 | * try again - if there are no more pages to remove from | |
2362 | * the DMA remapper, i915_gem_shrink will return 0. | |
2363 | */ | |
2364 | GEM_BUG_ON(obj->mm.pages == pages); | |
2365 | } while (i915_gem_shrink(to_i915(obj->base.dev), | |
2366 | obj->base.size >> PAGE_SHIFT, | |
2367 | I915_SHRINK_BOUND | | |
2368 | I915_SHRINK_UNBOUND | | |
2369 | I915_SHRINK_ACTIVE)); | |
9da3da66 | 2370 | |
03ac84f1 | 2371 | return -ENOSPC; |
7c2e6fdf DV |
2372 | } |
2373 | ||
2c642b07 | 2374 | static void gen8_set_pte(void __iomem *addr, gen8_pte_t pte) |
94ec8f61 | 2375 | { |
94ec8f61 | 2376 | writeq(pte, addr); |
94ec8f61 BW |
2377 | } |
2378 | ||
d6473f56 CW |
2379 | static void gen8_ggtt_insert_page(struct i915_address_space *vm, |
2380 | dma_addr_t addr, | |
2381 | uint64_t offset, | |
2382 | enum i915_cache_level level, | |
2383 | u32 unused) | |
2384 | { | |
49d73912 | 2385 | struct drm_i915_private *dev_priv = vm->i915; |
d6473f56 CW |
2386 | gen8_pte_t __iomem *pte = |
2387 | (gen8_pte_t __iomem *)dev_priv->ggtt.gsm + | |
2388 | (offset >> PAGE_SHIFT); | |
d6473f56 | 2389 | |
4fb84d99 | 2390 | gen8_set_pte(pte, gen8_pte_encode(addr, level)); |
d6473f56 CW |
2391 | |
2392 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
2393 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
d6473f56 CW |
2394 | } |
2395 | ||
94ec8f61 BW |
2396 | static void gen8_ggtt_insert_entries(struct i915_address_space *vm, |
2397 | struct sg_table *st, | |
782f1495 | 2398 | uint64_t start, |
24f3a8cf | 2399 | enum i915_cache_level level, u32 unused) |
94ec8f61 | 2400 | { |
49d73912 | 2401 | struct drm_i915_private *dev_priv = vm->i915; |
ce7fda2e | 2402 | struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm); |
85d1225e DG |
2403 | struct sgt_iter sgt_iter; |
2404 | gen8_pte_t __iomem *gtt_entries; | |
2405 | gen8_pte_t gtt_entry; | |
2406 | dma_addr_t addr; | |
85d1225e | 2407 | int i = 0; |
be69459a | 2408 | |
85d1225e DG |
2409 | gtt_entries = (gen8_pte_t __iomem *)ggtt->gsm + (start >> PAGE_SHIFT); |
2410 | ||
2411 | for_each_sgt_dma(addr, sgt_iter, st) { | |
4fb84d99 | 2412 | gtt_entry = gen8_pte_encode(addr, level); |
85d1225e | 2413 | gen8_set_pte(>t_entries[i++], gtt_entry); |
94ec8f61 BW |
2414 | } |
2415 | ||
2416 | /* | |
2417 | * XXX: This serves as a posting read to make sure that the PTE has | |
2418 | * actually been updated. There is some concern that even though | |
2419 | * registers and PTEs are within the same BAR that they are potentially | |
2420 | * of NUMA access patterns. Therefore, even with the way we assume | |
2421 | * hardware should work, we must keep this posting read for paranoia. | |
2422 | */ | |
2423 | if (i != 0) | |
85d1225e | 2424 | WARN_ON(readq(>t_entries[i-1]) != gtt_entry); |
94ec8f61 | 2425 | |
94ec8f61 BW |
2426 | /* This next bit makes the above posting read even more important. We |
2427 | * want to flush the TLBs only after we're certain all the PTE updates | |
2428 | * have finished. | |
2429 | */ | |
2430 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
2431 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
94ec8f61 BW |
2432 | } |
2433 | ||
c140330b CW |
2434 | struct insert_entries { |
2435 | struct i915_address_space *vm; | |
2436 | struct sg_table *st; | |
2437 | uint64_t start; | |
2438 | enum i915_cache_level level; | |
2439 | u32 flags; | |
2440 | }; | |
2441 | ||
2442 | static int gen8_ggtt_insert_entries__cb(void *_arg) | |
2443 | { | |
2444 | struct insert_entries *arg = _arg; | |
2445 | gen8_ggtt_insert_entries(arg->vm, arg->st, | |
2446 | arg->start, arg->level, arg->flags); | |
2447 | return 0; | |
2448 | } | |
2449 | ||
2450 | static void gen8_ggtt_insert_entries__BKL(struct i915_address_space *vm, | |
2451 | struct sg_table *st, | |
2452 | uint64_t start, | |
2453 | enum i915_cache_level level, | |
2454 | u32 flags) | |
2455 | { | |
2456 | struct insert_entries arg = { vm, st, start, level, flags }; | |
2457 | stop_machine(gen8_ggtt_insert_entries__cb, &arg, NULL); | |
2458 | } | |
2459 | ||
d6473f56 CW |
2460 | static void gen6_ggtt_insert_page(struct i915_address_space *vm, |
2461 | dma_addr_t addr, | |
2462 | uint64_t offset, | |
2463 | enum i915_cache_level level, | |
2464 | u32 flags) | |
2465 | { | |
49d73912 | 2466 | struct drm_i915_private *dev_priv = vm->i915; |
d6473f56 CW |
2467 | gen6_pte_t __iomem *pte = |
2468 | (gen6_pte_t __iomem *)dev_priv->ggtt.gsm + | |
2469 | (offset >> PAGE_SHIFT); | |
d6473f56 | 2470 | |
4fb84d99 | 2471 | iowrite32(vm->pte_encode(addr, level, flags), pte); |
d6473f56 CW |
2472 | |
2473 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
2474 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
d6473f56 CW |
2475 | } |
2476 | ||
e76e9aeb BW |
2477 | /* |
2478 | * Binds an object into the global gtt with the specified cache level. The object | |
2479 | * will be accessible to the GPU via commands whose operands reference offsets | |
2480 | * within the global GTT as well as accessible by the GPU through the GMADR | |
2481 | * mapped BAR (dev_priv->mm.gtt->gtt). | |
2482 | */ | |
853ba5d2 | 2483 | static void gen6_ggtt_insert_entries(struct i915_address_space *vm, |
7faf1ab2 | 2484 | struct sg_table *st, |
782f1495 | 2485 | uint64_t start, |
24f3a8cf | 2486 | enum i915_cache_level level, u32 flags) |
e76e9aeb | 2487 | { |
49d73912 | 2488 | struct drm_i915_private *dev_priv = vm->i915; |
ce7fda2e | 2489 | struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm); |
85d1225e DG |
2490 | struct sgt_iter sgt_iter; |
2491 | gen6_pte_t __iomem *gtt_entries; | |
2492 | gen6_pte_t gtt_entry; | |
2493 | dma_addr_t addr; | |
85d1225e | 2494 | int i = 0; |
be69459a | 2495 | |
85d1225e DG |
2496 | gtt_entries = (gen6_pte_t __iomem *)ggtt->gsm + (start >> PAGE_SHIFT); |
2497 | ||
2498 | for_each_sgt_dma(addr, sgt_iter, st) { | |
4fb84d99 | 2499 | gtt_entry = vm->pte_encode(addr, level, flags); |
85d1225e | 2500 | iowrite32(gtt_entry, >t_entries[i++]); |
e76e9aeb BW |
2501 | } |
2502 | ||
e76e9aeb BW |
2503 | /* XXX: This serves as a posting read to make sure that the PTE has |
2504 | * actually been updated. There is some concern that even though | |
2505 | * registers and PTEs are within the same BAR that they are potentially | |
2506 | * of NUMA access patterns. Therefore, even with the way we assume | |
2507 | * hardware should work, we must keep this posting read for paranoia. | |
2508 | */ | |
85d1225e DG |
2509 | if (i != 0) |
2510 | WARN_ON(readl(>t_entries[i-1]) != gtt_entry); | |
0f9b91c7 BW |
2511 | |
2512 | /* This next bit makes the above posting read even more important. We | |
2513 | * want to flush the TLBs only after we're certain all the PTE updates | |
2514 | * have finished. | |
2515 | */ | |
2516 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
2517 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
e76e9aeb BW |
2518 | } |
2519 | ||
f7770bfd | 2520 | static void nop_clear_range(struct i915_address_space *vm, |
4fb84d99 | 2521 | uint64_t start, uint64_t length) |
f7770bfd CW |
2522 | { |
2523 | } | |
2524 | ||
94ec8f61 | 2525 | static void gen8_ggtt_clear_range(struct i915_address_space *vm, |
4fb84d99 | 2526 | uint64_t start, uint64_t length) |
94ec8f61 | 2527 | { |
ce7fda2e | 2528 | struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm); |
782f1495 BW |
2529 | unsigned first_entry = start >> PAGE_SHIFT; |
2530 | unsigned num_entries = length >> PAGE_SHIFT; | |
07749ef3 | 2531 | gen8_pte_t scratch_pte, __iomem *gtt_base = |
72e96d64 JL |
2532 | (gen8_pte_t __iomem *)ggtt->gsm + first_entry; |
2533 | const int max_entries = ggtt_total_entries(ggtt) - first_entry; | |
94ec8f61 BW |
2534 | int i; |
2535 | ||
2536 | if (WARN(num_entries > max_entries, | |
2537 | "First entry = %d; Num entries = %d (max=%d)\n", | |
2538 | first_entry, num_entries, max_entries)) | |
2539 | num_entries = max_entries; | |
2540 | ||
8bcdd0f7 | 2541 | scratch_pte = gen8_pte_encode(vm->scratch_page.daddr, |
4fb84d99 | 2542 | I915_CACHE_LLC); |
94ec8f61 BW |
2543 | for (i = 0; i < num_entries; i++) |
2544 | gen8_set_pte(>t_base[i], scratch_pte); | |
2545 | readl(gtt_base); | |
2546 | } | |
2547 | ||
853ba5d2 | 2548 | static void gen6_ggtt_clear_range(struct i915_address_space *vm, |
782f1495 | 2549 | uint64_t start, |
4fb84d99 | 2550 | uint64_t length) |
7faf1ab2 | 2551 | { |
ce7fda2e | 2552 | struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm); |
782f1495 BW |
2553 | unsigned first_entry = start >> PAGE_SHIFT; |
2554 | unsigned num_entries = length >> PAGE_SHIFT; | |
07749ef3 | 2555 | gen6_pte_t scratch_pte, __iomem *gtt_base = |
72e96d64 JL |
2556 | (gen6_pte_t __iomem *)ggtt->gsm + first_entry; |
2557 | const int max_entries = ggtt_total_entries(ggtt) - first_entry; | |
7faf1ab2 DV |
2558 | int i; |
2559 | ||
2560 | if (WARN(num_entries > max_entries, | |
2561 | "First entry = %d; Num entries = %d (max=%d)\n", | |
2562 | first_entry, num_entries, max_entries)) | |
2563 | num_entries = max_entries; | |
2564 | ||
8bcdd0f7 | 2565 | scratch_pte = vm->pte_encode(vm->scratch_page.daddr, |
4fb84d99 | 2566 | I915_CACHE_LLC, 0); |
828c7908 | 2567 | |
7faf1ab2 DV |
2568 | for (i = 0; i < num_entries; i++) |
2569 | iowrite32(scratch_pte, >t_base[i]); | |
2570 | readl(gtt_base); | |
2571 | } | |
2572 | ||
d6473f56 CW |
2573 | static void i915_ggtt_insert_page(struct i915_address_space *vm, |
2574 | dma_addr_t addr, | |
2575 | uint64_t offset, | |
2576 | enum i915_cache_level cache_level, | |
2577 | u32 unused) | |
2578 | { | |
d6473f56 CW |
2579 | unsigned int flags = (cache_level == I915_CACHE_NONE) ? |
2580 | AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY; | |
d6473f56 CW |
2581 | |
2582 | intel_gtt_insert_page(addr, offset >> PAGE_SHIFT, flags); | |
d6473f56 CW |
2583 | } |
2584 | ||
d369d2d9 DV |
2585 | static void i915_ggtt_insert_entries(struct i915_address_space *vm, |
2586 | struct sg_table *pages, | |
2587 | uint64_t start, | |
2588 | enum i915_cache_level cache_level, u32 unused) | |
7faf1ab2 DV |
2589 | { |
2590 | unsigned int flags = (cache_level == I915_CACHE_NONE) ? | |
2591 | AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY; | |
2592 | ||
d369d2d9 | 2593 | intel_gtt_insert_sg_entries(pages, start >> PAGE_SHIFT, flags); |
0875546c | 2594 | |
7faf1ab2 DV |
2595 | } |
2596 | ||
853ba5d2 | 2597 | static void i915_ggtt_clear_range(struct i915_address_space *vm, |
782f1495 | 2598 | uint64_t start, |
4fb84d99 | 2599 | uint64_t length) |
7faf1ab2 | 2600 | { |
2eedfc7d | 2601 | intel_gtt_clear_range(start >> PAGE_SHIFT, length >> PAGE_SHIFT); |
7faf1ab2 DV |
2602 | } |
2603 | ||
70b9f6f8 DV |
2604 | static int ggtt_bind_vma(struct i915_vma *vma, |
2605 | enum i915_cache_level cache_level, | |
2606 | u32 flags) | |
0a878716 | 2607 | { |
49d73912 | 2608 | struct drm_i915_private *i915 = vma->vm->i915; |
0a878716 DV |
2609 | struct drm_i915_gem_object *obj = vma->obj; |
2610 | u32 pte_flags = 0; | |
2611 | int ret; | |
2612 | ||
2613 | ret = i915_get_ggtt_vma_pages(vma); | |
2614 | if (ret) | |
2615 | return ret; | |
2616 | ||
2617 | /* Currently applicable only to VLV */ | |
2618 | if (obj->gt_ro) | |
2619 | pte_flags |= PTE_READ_ONLY; | |
2620 | ||
9c870d03 | 2621 | intel_runtime_pm_get(i915); |
247177dd | 2622 | vma->vm->insert_entries(vma->vm, vma->pages, vma->node.start, |
0a878716 | 2623 | cache_level, pte_flags); |
9c870d03 | 2624 | intel_runtime_pm_put(i915); |
0a878716 DV |
2625 | |
2626 | /* | |
2627 | * Without aliasing PPGTT there's no difference between | |
2628 | * GLOBAL/LOCAL_BIND, it's all the same ptes. Hence unconditionally | |
2629 | * upgrade to both bound if we bind either to avoid double-binding. | |
2630 | */ | |
3272db53 | 2631 | vma->flags |= I915_VMA_GLOBAL_BIND | I915_VMA_LOCAL_BIND; |
0a878716 DV |
2632 | |
2633 | return 0; | |
2634 | } | |
2635 | ||
2636 | static int aliasing_gtt_bind_vma(struct i915_vma *vma, | |
2637 | enum i915_cache_level cache_level, | |
2638 | u32 flags) | |
d5bd1449 | 2639 | { |
49d73912 | 2640 | struct drm_i915_private *i915 = vma->vm->i915; |
321d178e | 2641 | u32 pte_flags; |
70b9f6f8 DV |
2642 | int ret; |
2643 | ||
2644 | ret = i915_get_ggtt_vma_pages(vma); | |
2645 | if (ret) | |
2646 | return ret; | |
7faf1ab2 | 2647 | |
24f3a8cf | 2648 | /* Currently applicable only to VLV */ |
321d178e CW |
2649 | pte_flags = 0; |
2650 | if (vma->obj->gt_ro) | |
f329f5f6 | 2651 | pte_flags |= PTE_READ_ONLY; |
24f3a8cf | 2652 | |
ec7adb6e | 2653 | |
3272db53 | 2654 | if (flags & I915_VMA_GLOBAL_BIND) { |
9c870d03 | 2655 | intel_runtime_pm_get(i915); |
321d178e | 2656 | vma->vm->insert_entries(vma->vm, |
247177dd | 2657 | vma->pages, vma->node.start, |
0875546c | 2658 | cache_level, pte_flags); |
9c870d03 | 2659 | intel_runtime_pm_put(i915); |
6f65e29a | 2660 | } |
d5bd1449 | 2661 | |
3272db53 | 2662 | if (flags & I915_VMA_LOCAL_BIND) { |
9c870d03 | 2663 | struct i915_hw_ppgtt *appgtt = i915->mm.aliasing_ppgtt; |
321d178e | 2664 | appgtt->base.insert_entries(&appgtt->base, |
247177dd | 2665 | vma->pages, vma->node.start, |
f329f5f6 | 2666 | cache_level, pte_flags); |
6f65e29a | 2667 | } |
70b9f6f8 DV |
2668 | |
2669 | return 0; | |
d5bd1449 CW |
2670 | } |
2671 | ||
6f65e29a | 2672 | static void ggtt_unbind_vma(struct i915_vma *vma) |
74163907 | 2673 | { |
49d73912 | 2674 | struct drm_i915_private *i915 = vma->vm->i915; |
9c870d03 | 2675 | struct i915_hw_ppgtt *appgtt = i915->mm.aliasing_ppgtt; |
de180033 | 2676 | const u64 size = min(vma->size, vma->node.size); |
6f65e29a | 2677 | |
9c870d03 CW |
2678 | if (vma->flags & I915_VMA_GLOBAL_BIND) { |
2679 | intel_runtime_pm_get(i915); | |
782f1495 | 2680 | vma->vm->clear_range(vma->vm, |
4fb84d99 | 2681 | vma->node.start, size); |
9c870d03 CW |
2682 | intel_runtime_pm_put(i915); |
2683 | } | |
06615ee5 | 2684 | |
3272db53 | 2685 | if (vma->flags & I915_VMA_LOCAL_BIND && appgtt) |
6f65e29a | 2686 | appgtt->base.clear_range(&appgtt->base, |
4fb84d99 | 2687 | vma->node.start, size); |
74163907 DV |
2688 | } |
2689 | ||
03ac84f1 CW |
2690 | void i915_gem_gtt_finish_pages(struct drm_i915_gem_object *obj, |
2691 | struct sg_table *pages) | |
7c2e6fdf | 2692 | { |
52a05c30 DW |
2693 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
2694 | struct device *kdev = &dev_priv->drm.pdev->dev; | |
307dc25b | 2695 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
5c042287 | 2696 | |
307dc25b | 2697 | if (unlikely(ggtt->do_idle_maps)) { |
22dd3bb9 | 2698 | if (i915_gem_wait_for_idle(dev_priv, I915_WAIT_LOCKED)) { |
307dc25b CW |
2699 | DRM_ERROR("Failed to wait for idle; VT'd may hang.\n"); |
2700 | /* Wait a bit, in hopes it avoids the hang */ | |
2701 | udelay(10); | |
2702 | } | |
2703 | } | |
5c042287 | 2704 | |
03ac84f1 | 2705 | dma_unmap_sg(kdev, pages->sgl, pages->nents, PCI_DMA_BIDIRECTIONAL); |
7c2e6fdf | 2706 | } |
644ec02b | 2707 | |
45b186f1 | 2708 | static void i915_gtt_color_adjust(const struct drm_mm_node *node, |
42d6ab48 | 2709 | unsigned long color, |
440fd528 TR |
2710 | u64 *start, |
2711 | u64 *end) | |
42d6ab48 CW |
2712 | { |
2713 | if (node->color != color) | |
f51455d4 | 2714 | *start += I915_GTT_PAGE_SIZE; |
42d6ab48 | 2715 | |
b44f97fd CW |
2716 | node = list_next_entry(node, node_list); |
2717 | if (node->allocated && node->color != color) | |
f51455d4 | 2718 | *end -= I915_GTT_PAGE_SIZE; |
42d6ab48 | 2719 | } |
fbe5d36e | 2720 | |
f6b9d5ca | 2721 | int i915_gem_init_ggtt(struct drm_i915_private *dev_priv) |
644ec02b | 2722 | { |
e78891ca BW |
2723 | /* Let GEM Manage all of the aperture. |
2724 | * | |
2725 | * However, leave one page at the end still bound to the scratch page. | |
2726 | * There are a number of places where the hardware apparently prefetches | |
2727 | * past the end of the object, and we've seen multiple hangs with the | |
2728 | * GPU head pointer stuck in a batchbuffer bound at the last page of the | |
2729 | * aperture. One page should be enough to keep any prefetching inside | |
2730 | * of the aperture. | |
2731 | */ | |
72e96d64 | 2732 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
ed2f3452 | 2733 | unsigned long hole_start, hole_end; |
95374d75 | 2734 | struct i915_hw_ppgtt *ppgtt; |
f6b9d5ca | 2735 | struct drm_mm_node *entry; |
fa76da34 | 2736 | int ret; |
644ec02b | 2737 | |
b02d22a3 ZW |
2738 | ret = intel_vgt_balloon(dev_priv); |
2739 | if (ret) | |
2740 | return ret; | |
5dda8fa3 | 2741 | |
95374d75 CW |
2742 | /* Reserve a mappable slot for our lockless error capture */ |
2743 | ret = drm_mm_insert_node_in_range_generic(&ggtt->base.mm, | |
2744 | &ggtt->error_capture, | |
f51455d4 | 2745 | PAGE_SIZE, 0, |
85fd4f58 | 2746 | I915_COLOR_UNEVICTABLE, |
95374d75 CW |
2747 | 0, ggtt->mappable_end, |
2748 | 0, 0); | |
2749 | if (ret) | |
2750 | return ret; | |
2751 | ||
ed2f3452 | 2752 | /* Clear any non-preallocated blocks */ |
72e96d64 | 2753 | drm_mm_for_each_hole(entry, &ggtt->base.mm, hole_start, hole_end) { |
ed2f3452 CW |
2754 | DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n", |
2755 | hole_start, hole_end); | |
72e96d64 | 2756 | ggtt->base.clear_range(&ggtt->base, hole_start, |
4fb84d99 | 2757 | hole_end - hole_start); |
ed2f3452 CW |
2758 | } |
2759 | ||
2760 | /* And finally clear the reserved guard page */ | |
f6b9d5ca | 2761 | ggtt->base.clear_range(&ggtt->base, |
4fb84d99 | 2762 | ggtt->base.total - PAGE_SIZE, PAGE_SIZE); |
6c5566a8 | 2763 | |
97d6d7ab | 2764 | if (USES_PPGTT(dev_priv) && !USES_FULL_PPGTT(dev_priv)) { |
fa76da34 | 2765 | ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL); |
95374d75 CW |
2766 | if (!ppgtt) { |
2767 | ret = -ENOMEM; | |
2768 | goto err; | |
2769 | } | |
fa76da34 | 2770 | |
2bfa996e | 2771 | ret = __hw_ppgtt_init(ppgtt, dev_priv); |
95374d75 CW |
2772 | if (ret) |
2773 | goto err_ppgtt; | |
5c5f6457 | 2774 | |
95374d75 | 2775 | if (ppgtt->base.allocate_va_range) { |
5c5f6457 DV |
2776 | ret = ppgtt->base.allocate_va_range(&ppgtt->base, 0, |
2777 | ppgtt->base.total); | |
95374d75 CW |
2778 | if (ret) |
2779 | goto err_ppgtt_cleanup; | |
4933d519 | 2780 | } |
fa76da34 | 2781 | |
5c5f6457 DV |
2782 | ppgtt->base.clear_range(&ppgtt->base, |
2783 | ppgtt->base.start, | |
4fb84d99 | 2784 | ppgtt->base.total); |
5c5f6457 | 2785 | |
fa76da34 | 2786 | dev_priv->mm.aliasing_ppgtt = ppgtt; |
72e96d64 JL |
2787 | WARN_ON(ggtt->base.bind_vma != ggtt_bind_vma); |
2788 | ggtt->base.bind_vma = aliasing_gtt_bind_vma; | |
fa76da34 DV |
2789 | } |
2790 | ||
6c5566a8 | 2791 | return 0; |
95374d75 CW |
2792 | |
2793 | err_ppgtt_cleanup: | |
2794 | ppgtt->base.cleanup(&ppgtt->base); | |
2795 | err_ppgtt: | |
2796 | kfree(ppgtt); | |
2797 | err: | |
2798 | drm_mm_remove_node(&ggtt->error_capture); | |
2799 | return ret; | |
e76e9aeb BW |
2800 | } |
2801 | ||
d85489d3 JL |
2802 | /** |
2803 | * i915_ggtt_cleanup_hw - Clean up GGTT hardware initialization | |
97d6d7ab | 2804 | * @dev_priv: i915 device |
d85489d3 | 2805 | */ |
97d6d7ab | 2806 | void i915_ggtt_cleanup_hw(struct drm_i915_private *dev_priv) |
90d0a0e8 | 2807 | { |
72e96d64 | 2808 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
90d0a0e8 | 2809 | |
70e32544 DV |
2810 | if (dev_priv->mm.aliasing_ppgtt) { |
2811 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
70e32544 | 2812 | ppgtt->base.cleanup(&ppgtt->base); |
cb7f2760 | 2813 | kfree(ppgtt); |
70e32544 DV |
2814 | } |
2815 | ||
97d6d7ab | 2816 | i915_gem_cleanup_stolen(&dev_priv->drm); |
a4eba47b | 2817 | |
95374d75 CW |
2818 | if (drm_mm_node_allocated(&ggtt->error_capture)) |
2819 | drm_mm_remove_node(&ggtt->error_capture); | |
2820 | ||
72e96d64 | 2821 | if (drm_mm_initialized(&ggtt->base.mm)) { |
b02d22a3 | 2822 | intel_vgt_deballoon(dev_priv); |
5dda8fa3 | 2823 | |
ed9724dd MA |
2824 | mutex_lock(&dev_priv->drm.struct_mutex); |
2825 | i915_address_space_fini(&ggtt->base); | |
2826 | mutex_unlock(&dev_priv->drm.struct_mutex); | |
90d0a0e8 DV |
2827 | } |
2828 | ||
72e96d64 | 2829 | ggtt->base.cleanup(&ggtt->base); |
f6b9d5ca CW |
2830 | |
2831 | arch_phys_wc_del(ggtt->mtrr); | |
f7bbe788 | 2832 | io_mapping_fini(&ggtt->mappable); |
90d0a0e8 | 2833 | } |
70e32544 | 2834 | |
2c642b07 | 2835 | static unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl) |
e76e9aeb BW |
2836 | { |
2837 | snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT; | |
2838 | snb_gmch_ctl &= SNB_GMCH_GGMS_MASK; | |
2839 | return snb_gmch_ctl << 20; | |
2840 | } | |
2841 | ||
2c642b07 | 2842 | static unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl) |
9459d252 BW |
2843 | { |
2844 | bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT; | |
2845 | bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK; | |
2846 | if (bdw_gmch_ctl) | |
2847 | bdw_gmch_ctl = 1 << bdw_gmch_ctl; | |
562d55d9 BW |
2848 | |
2849 | #ifdef CONFIG_X86_32 | |
2850 | /* Limit 32b platforms to a 2GB GGTT: 4 << 20 / pte size * PAGE_SIZE */ | |
2851 | if (bdw_gmch_ctl > 4) | |
2852 | bdw_gmch_ctl = 4; | |
2853 | #endif | |
2854 | ||
9459d252 BW |
2855 | return bdw_gmch_ctl << 20; |
2856 | } | |
2857 | ||
2c642b07 | 2858 | static unsigned int chv_get_total_gtt_size(u16 gmch_ctrl) |
d7f25f23 DL |
2859 | { |
2860 | gmch_ctrl >>= SNB_GMCH_GGMS_SHIFT; | |
2861 | gmch_ctrl &= SNB_GMCH_GGMS_MASK; | |
2862 | ||
2863 | if (gmch_ctrl) | |
2864 | return 1 << (20 + gmch_ctrl); | |
2865 | ||
2866 | return 0; | |
2867 | } | |
2868 | ||
2c642b07 | 2869 | static size_t gen6_get_stolen_size(u16 snb_gmch_ctl) |
e76e9aeb BW |
2870 | { |
2871 | snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT; | |
2872 | snb_gmch_ctl &= SNB_GMCH_GMS_MASK; | |
2873 | return snb_gmch_ctl << 25; /* 32 MB units */ | |
2874 | } | |
2875 | ||
2c642b07 | 2876 | static size_t gen8_get_stolen_size(u16 bdw_gmch_ctl) |
9459d252 BW |
2877 | { |
2878 | bdw_gmch_ctl >>= BDW_GMCH_GMS_SHIFT; | |
2879 | bdw_gmch_ctl &= BDW_GMCH_GMS_MASK; | |
2880 | return bdw_gmch_ctl << 25; /* 32 MB units */ | |
2881 | } | |
2882 | ||
d7f25f23 DL |
2883 | static size_t chv_get_stolen_size(u16 gmch_ctrl) |
2884 | { | |
2885 | gmch_ctrl >>= SNB_GMCH_GMS_SHIFT; | |
2886 | gmch_ctrl &= SNB_GMCH_GMS_MASK; | |
2887 | ||
2888 | /* | |
2889 | * 0x0 to 0x10: 32MB increments starting at 0MB | |
2890 | * 0x11 to 0x16: 4MB increments starting at 8MB | |
2891 | * 0x17 to 0x1d: 4MB increments start at 36MB | |
2892 | */ | |
2893 | if (gmch_ctrl < 0x11) | |
2894 | return gmch_ctrl << 25; | |
2895 | else if (gmch_ctrl < 0x17) | |
2896 | return (gmch_ctrl - 0x11 + 2) << 22; | |
2897 | else | |
2898 | return (gmch_ctrl - 0x17 + 9) << 22; | |
2899 | } | |
2900 | ||
66375014 DL |
2901 | static size_t gen9_get_stolen_size(u16 gen9_gmch_ctl) |
2902 | { | |
2903 | gen9_gmch_ctl >>= BDW_GMCH_GMS_SHIFT; | |
2904 | gen9_gmch_ctl &= BDW_GMCH_GMS_MASK; | |
2905 | ||
2906 | if (gen9_gmch_ctl < 0xf0) | |
2907 | return gen9_gmch_ctl << 25; /* 32 MB units */ | |
2908 | else | |
2909 | /* 4MB increments starting at 0xf0 for 4MB */ | |
2910 | return (gen9_gmch_ctl - 0xf0 + 1) << 22; | |
2911 | } | |
2912 | ||
34c998b4 | 2913 | static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size) |
63340133 | 2914 | { |
49d73912 CW |
2915 | struct drm_i915_private *dev_priv = ggtt->base.i915; |
2916 | struct pci_dev *pdev = dev_priv->drm.pdev; | |
34c998b4 | 2917 | phys_addr_t phys_addr; |
8bcdd0f7 | 2918 | int ret; |
63340133 BW |
2919 | |
2920 | /* For Modern GENs the PTEs and register space are split in the BAR */ | |
34c998b4 | 2921 | phys_addr = pci_resource_start(pdev, 0) + pci_resource_len(pdev, 0) / 2; |
63340133 | 2922 | |
2a073f89 ID |
2923 | /* |
2924 | * On BXT writes larger than 64 bit to the GTT pagetable range will be | |
2925 | * dropped. For WC mappings in general we have 64 byte burst writes | |
2926 | * when the WC buffer is flushed, so we can't use it, but have to | |
2927 | * resort to an uncached mapping. The WC issue is easily caught by the | |
2928 | * readback check when writing GTT PTE entries. | |
2929 | */ | |
cc3f90f0 | 2930 | if (IS_GEN9_LP(dev_priv)) |
34c998b4 | 2931 | ggtt->gsm = ioremap_nocache(phys_addr, size); |
2a073f89 | 2932 | else |
34c998b4 | 2933 | ggtt->gsm = ioremap_wc(phys_addr, size); |
72e96d64 | 2934 | if (!ggtt->gsm) { |
34c998b4 | 2935 | DRM_ERROR("Failed to map the ggtt page table\n"); |
63340133 BW |
2936 | return -ENOMEM; |
2937 | } | |
2938 | ||
275a991c | 2939 | ret = setup_scratch_page(dev_priv, &ggtt->base.scratch_page, GFP_DMA32); |
8bcdd0f7 | 2940 | if (ret) { |
63340133 BW |
2941 | DRM_ERROR("Scratch setup failed\n"); |
2942 | /* iounmap will also get called at remove, but meh */ | |
72e96d64 | 2943 | iounmap(ggtt->gsm); |
8bcdd0f7 | 2944 | return ret; |
63340133 BW |
2945 | } |
2946 | ||
4ad2af1e | 2947 | return 0; |
63340133 BW |
2948 | } |
2949 | ||
fbe5d36e BW |
2950 | /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability |
2951 | * bits. When using advanced contexts each context stores its own PAT, but | |
2952 | * writing this data shouldn't be harmful even in those cases. */ | |
ee0ce478 | 2953 | static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv) |
fbe5d36e | 2954 | { |
fbe5d36e BW |
2955 | uint64_t pat; |
2956 | ||
2957 | pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC) | /* for normal objects, no eLLC */ | |
2958 | GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something pointing to ptes? */ | |
2959 | GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC) | /* for scanout with eLLC */ | |
2960 | GEN8_PPAT(3, GEN8_PPAT_UC) | /* Uncached objects, mostly for scanout */ | |
2961 | GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) | | |
2962 | GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) | | |
2963 | GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) | | |
2964 | GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3)); | |
2965 | ||
2d1fe073 | 2966 | if (!USES_PPGTT(dev_priv)) |
d6a8b72e RV |
2967 | /* Spec: "For GGTT, there is NO pat_sel[2:0] from the entry, |
2968 | * so RTL will always use the value corresponding to | |
2969 | * pat_sel = 000". | |
2970 | * So let's disable cache for GGTT to avoid screen corruptions. | |
2971 | * MOCS still can be used though. | |
2972 | * - System agent ggtt writes (i.e. cpu gtt mmaps) already work | |
2973 | * before this patch, i.e. the same uncached + snooping access | |
2974 | * like on gen6/7 seems to be in effect. | |
2975 | * - So this just fixes blitter/render access. Again it looks | |
2976 | * like it's not just uncached access, but uncached + snooping. | |
2977 | * So we can still hold onto all our assumptions wrt cpu | |
2978 | * clflushing on LLC machines. | |
2979 | */ | |
2980 | pat = GEN8_PPAT(0, GEN8_PPAT_UC); | |
2981 | ||
fbe5d36e BW |
2982 | /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b |
2983 | * write would work. */ | |
7e435ad2 VS |
2984 | I915_WRITE(GEN8_PRIVATE_PAT_LO, pat); |
2985 | I915_WRITE(GEN8_PRIVATE_PAT_HI, pat >> 32); | |
fbe5d36e BW |
2986 | } |
2987 | ||
ee0ce478 VS |
2988 | static void chv_setup_private_ppat(struct drm_i915_private *dev_priv) |
2989 | { | |
2990 | uint64_t pat; | |
2991 | ||
2992 | /* | |
2993 | * Map WB on BDW to snooped on CHV. | |
2994 | * | |
2995 | * Only the snoop bit has meaning for CHV, the rest is | |
2996 | * ignored. | |
2997 | * | |
cf3d262e VS |
2998 | * The hardware will never snoop for certain types of accesses: |
2999 | * - CPU GTT (GMADR->GGTT->no snoop->memory) | |
3000 | * - PPGTT page tables | |
3001 | * - some other special cycles | |
3002 | * | |
3003 | * As with BDW, we also need to consider the following for GT accesses: | |
3004 | * "For GGTT, there is NO pat_sel[2:0] from the entry, | |
3005 | * so RTL will always use the value corresponding to | |
3006 | * pat_sel = 000". | |
3007 | * Which means we must set the snoop bit in PAT entry 0 | |
3008 | * in order to keep the global status page working. | |
ee0ce478 VS |
3009 | */ |
3010 | pat = GEN8_PPAT(0, CHV_PPAT_SNOOP) | | |
3011 | GEN8_PPAT(1, 0) | | |
3012 | GEN8_PPAT(2, 0) | | |
3013 | GEN8_PPAT(3, 0) | | |
3014 | GEN8_PPAT(4, CHV_PPAT_SNOOP) | | |
3015 | GEN8_PPAT(5, CHV_PPAT_SNOOP) | | |
3016 | GEN8_PPAT(6, CHV_PPAT_SNOOP) | | |
3017 | GEN8_PPAT(7, CHV_PPAT_SNOOP); | |
3018 | ||
7e435ad2 VS |
3019 | I915_WRITE(GEN8_PRIVATE_PAT_LO, pat); |
3020 | I915_WRITE(GEN8_PRIVATE_PAT_HI, pat >> 32); | |
ee0ce478 VS |
3021 | } |
3022 | ||
34c998b4 CW |
3023 | static void gen6_gmch_remove(struct i915_address_space *vm) |
3024 | { | |
3025 | struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm); | |
3026 | ||
3027 | iounmap(ggtt->gsm); | |
49d73912 | 3028 | cleanup_scratch_page(vm->i915, &vm->scratch_page); |
34c998b4 CW |
3029 | } |
3030 | ||
d507d735 | 3031 | static int gen8_gmch_probe(struct i915_ggtt *ggtt) |
63340133 | 3032 | { |
49d73912 | 3033 | struct drm_i915_private *dev_priv = ggtt->base.i915; |
97d6d7ab | 3034 | struct pci_dev *pdev = dev_priv->drm.pdev; |
34c998b4 | 3035 | unsigned int size; |
63340133 | 3036 | u16 snb_gmch_ctl; |
63340133 BW |
3037 | |
3038 | /* TODO: We're not aware of mappable constraints on gen8 yet */ | |
97d6d7ab CW |
3039 | ggtt->mappable_base = pci_resource_start(pdev, 2); |
3040 | ggtt->mappable_end = pci_resource_len(pdev, 2); | |
63340133 | 3041 | |
97d6d7ab CW |
3042 | if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(39))) |
3043 | pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(39)); | |
63340133 | 3044 | |
97d6d7ab | 3045 | pci_read_config_word(pdev, SNB_GMCH_CTRL, &snb_gmch_ctl); |
63340133 | 3046 | |
97d6d7ab | 3047 | if (INTEL_GEN(dev_priv) >= 9) { |
d507d735 | 3048 | ggtt->stolen_size = gen9_get_stolen_size(snb_gmch_ctl); |
34c998b4 | 3049 | size = gen8_get_total_gtt_size(snb_gmch_ctl); |
97d6d7ab | 3050 | } else if (IS_CHERRYVIEW(dev_priv)) { |
d507d735 | 3051 | ggtt->stolen_size = chv_get_stolen_size(snb_gmch_ctl); |
34c998b4 | 3052 | size = chv_get_total_gtt_size(snb_gmch_ctl); |
d7f25f23 | 3053 | } else { |
d507d735 | 3054 | ggtt->stolen_size = gen8_get_stolen_size(snb_gmch_ctl); |
34c998b4 | 3055 | size = gen8_get_total_gtt_size(snb_gmch_ctl); |
d7f25f23 | 3056 | } |
63340133 | 3057 | |
34c998b4 | 3058 | ggtt->base.total = (size / sizeof(gen8_pte_t)) << PAGE_SHIFT; |
63340133 | 3059 | |
cc3f90f0 | 3060 | if (IS_CHERRYVIEW(dev_priv) || IS_GEN9_LP(dev_priv)) |
ee0ce478 VS |
3061 | chv_setup_private_ppat(dev_priv); |
3062 | else | |
3063 | bdw_setup_private_ppat(dev_priv); | |
fbe5d36e | 3064 | |
34c998b4 | 3065 | ggtt->base.cleanup = gen6_gmch_remove; |
d507d735 JL |
3066 | ggtt->base.bind_vma = ggtt_bind_vma; |
3067 | ggtt->base.unbind_vma = ggtt_unbind_vma; | |
d6473f56 | 3068 | ggtt->base.insert_page = gen8_ggtt_insert_page; |
f7770bfd | 3069 | ggtt->base.clear_range = nop_clear_range; |
48f112fe | 3070 | if (!USES_FULL_PPGTT(dev_priv) || intel_scanout_needs_vtd_wa(dev_priv)) |
f7770bfd CW |
3071 | ggtt->base.clear_range = gen8_ggtt_clear_range; |
3072 | ||
3073 | ggtt->base.insert_entries = gen8_ggtt_insert_entries; | |
3074 | if (IS_CHERRYVIEW(dev_priv)) | |
3075 | ggtt->base.insert_entries = gen8_ggtt_insert_entries__BKL; | |
3076 | ||
34c998b4 | 3077 | return ggtt_probe_common(ggtt, size); |
63340133 BW |
3078 | } |
3079 | ||
d507d735 | 3080 | static int gen6_gmch_probe(struct i915_ggtt *ggtt) |
e76e9aeb | 3081 | { |
49d73912 | 3082 | struct drm_i915_private *dev_priv = ggtt->base.i915; |
97d6d7ab | 3083 | struct pci_dev *pdev = dev_priv->drm.pdev; |
34c998b4 | 3084 | unsigned int size; |
e76e9aeb | 3085 | u16 snb_gmch_ctl; |
e76e9aeb | 3086 | |
97d6d7ab CW |
3087 | ggtt->mappable_base = pci_resource_start(pdev, 2); |
3088 | ggtt->mappable_end = pci_resource_len(pdev, 2); | |
41907ddc | 3089 | |
baa09f5f BW |
3090 | /* 64/512MB is the current min/max we actually know of, but this is just |
3091 | * a coarse sanity check. | |
e76e9aeb | 3092 | */ |
34c998b4 | 3093 | if (ggtt->mappable_end < (64<<20) || ggtt->mappable_end > (512<<20)) { |
d507d735 | 3094 | DRM_ERROR("Unknown GMADR size (%llx)\n", ggtt->mappable_end); |
baa09f5f | 3095 | return -ENXIO; |
e76e9aeb BW |
3096 | } |
3097 | ||
97d6d7ab CW |
3098 | if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(40))) |
3099 | pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(40)); | |
3100 | pci_read_config_word(pdev, SNB_GMCH_CTRL, &snb_gmch_ctl); | |
e76e9aeb | 3101 | |
d507d735 | 3102 | ggtt->stolen_size = gen6_get_stolen_size(snb_gmch_ctl); |
e76e9aeb | 3103 | |
34c998b4 CW |
3104 | size = gen6_get_total_gtt_size(snb_gmch_ctl); |
3105 | ggtt->base.total = (size / sizeof(gen6_pte_t)) << PAGE_SHIFT; | |
e76e9aeb | 3106 | |
d507d735 | 3107 | ggtt->base.clear_range = gen6_ggtt_clear_range; |
d6473f56 | 3108 | ggtt->base.insert_page = gen6_ggtt_insert_page; |
d507d735 JL |
3109 | ggtt->base.insert_entries = gen6_ggtt_insert_entries; |
3110 | ggtt->base.bind_vma = ggtt_bind_vma; | |
3111 | ggtt->base.unbind_vma = ggtt_unbind_vma; | |
34c998b4 CW |
3112 | ggtt->base.cleanup = gen6_gmch_remove; |
3113 | ||
3114 | if (HAS_EDRAM(dev_priv)) | |
3115 | ggtt->base.pte_encode = iris_pte_encode; | |
3116 | else if (IS_HASWELL(dev_priv)) | |
3117 | ggtt->base.pte_encode = hsw_pte_encode; | |
3118 | else if (IS_VALLEYVIEW(dev_priv)) | |
3119 | ggtt->base.pte_encode = byt_pte_encode; | |
3120 | else if (INTEL_GEN(dev_priv) >= 7) | |
3121 | ggtt->base.pte_encode = ivb_pte_encode; | |
3122 | else | |
3123 | ggtt->base.pte_encode = snb_pte_encode; | |
7faf1ab2 | 3124 | |
34c998b4 | 3125 | return ggtt_probe_common(ggtt, size); |
e76e9aeb BW |
3126 | } |
3127 | ||
34c998b4 | 3128 | static void i915_gmch_remove(struct i915_address_space *vm) |
e76e9aeb | 3129 | { |
34c998b4 | 3130 | intel_gmch_remove(); |
644ec02b | 3131 | } |
baa09f5f | 3132 | |
d507d735 | 3133 | static int i915_gmch_probe(struct i915_ggtt *ggtt) |
baa09f5f | 3134 | { |
49d73912 | 3135 | struct drm_i915_private *dev_priv = ggtt->base.i915; |
baa09f5f BW |
3136 | int ret; |
3137 | ||
91c8a326 | 3138 | ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->drm.pdev, NULL); |
baa09f5f BW |
3139 | if (!ret) { |
3140 | DRM_ERROR("failed to set up gmch\n"); | |
3141 | return -EIO; | |
3142 | } | |
3143 | ||
edd1f2fe CW |
3144 | intel_gtt_get(&ggtt->base.total, |
3145 | &ggtt->stolen_size, | |
3146 | &ggtt->mappable_base, | |
3147 | &ggtt->mappable_end); | |
baa09f5f | 3148 | |
97d6d7ab | 3149 | ggtt->do_idle_maps = needs_idle_maps(dev_priv); |
d6473f56 | 3150 | ggtt->base.insert_page = i915_ggtt_insert_page; |
d507d735 JL |
3151 | ggtt->base.insert_entries = i915_ggtt_insert_entries; |
3152 | ggtt->base.clear_range = i915_ggtt_clear_range; | |
3153 | ggtt->base.bind_vma = ggtt_bind_vma; | |
3154 | ggtt->base.unbind_vma = ggtt_unbind_vma; | |
34c998b4 | 3155 | ggtt->base.cleanup = i915_gmch_remove; |
baa09f5f | 3156 | |
d507d735 | 3157 | if (unlikely(ggtt->do_idle_maps)) |
c0a7f818 CW |
3158 | DRM_INFO("applying Ironlake quirks for intel_iommu\n"); |
3159 | ||
baa09f5f BW |
3160 | return 0; |
3161 | } | |
3162 | ||
d85489d3 | 3163 | /** |
0088e522 | 3164 | * i915_ggtt_probe_hw - Probe GGTT hardware location |
97d6d7ab | 3165 | * @dev_priv: i915 device |
d85489d3 | 3166 | */ |
97d6d7ab | 3167 | int i915_ggtt_probe_hw(struct drm_i915_private *dev_priv) |
baa09f5f | 3168 | { |
62106b4f | 3169 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
baa09f5f BW |
3170 | int ret; |
3171 | ||
49d73912 | 3172 | ggtt->base.i915 = dev_priv; |
c114f76a | 3173 | |
34c998b4 CW |
3174 | if (INTEL_GEN(dev_priv) <= 5) |
3175 | ret = i915_gmch_probe(ggtt); | |
3176 | else if (INTEL_GEN(dev_priv) < 8) | |
3177 | ret = gen6_gmch_probe(ggtt); | |
3178 | else | |
3179 | ret = gen8_gmch_probe(ggtt); | |
a54c0c27 | 3180 | if (ret) |
baa09f5f | 3181 | return ret; |
baa09f5f | 3182 | |
db9309a5 CW |
3183 | /* Trim the GGTT to fit the GuC mappable upper range (when enabled). |
3184 | * This is easier than doing range restriction on the fly, as we | |
3185 | * currently don't have any bits spare to pass in this upper | |
3186 | * restriction! | |
3187 | */ | |
3188 | if (HAS_GUC(dev_priv) && i915.enable_guc_loading) { | |
3189 | ggtt->base.total = min_t(u64, ggtt->base.total, GUC_GGTT_TOP); | |
3190 | ggtt->mappable_end = min(ggtt->mappable_end, ggtt->base.total); | |
3191 | } | |
3192 | ||
c890e2d5 CW |
3193 | if ((ggtt->base.total - 1) >> 32) { |
3194 | DRM_ERROR("We never expected a Global GTT with more than 32bits" | |
f6b9d5ca | 3195 | " of address space! Found %lldM!\n", |
c890e2d5 CW |
3196 | ggtt->base.total >> 20); |
3197 | ggtt->base.total = 1ULL << 32; | |
3198 | ggtt->mappable_end = min(ggtt->mappable_end, ggtt->base.total); | |
3199 | } | |
3200 | ||
f6b9d5ca CW |
3201 | if (ggtt->mappable_end > ggtt->base.total) { |
3202 | DRM_ERROR("mappable aperture extends past end of GGTT," | |
3203 | " aperture=%llx, total=%llx\n", | |
3204 | ggtt->mappable_end, ggtt->base.total); | |
3205 | ggtt->mappable_end = ggtt->base.total; | |
3206 | } | |
3207 | ||
baa09f5f | 3208 | /* GMADR is the PCI mmio aperture into the global GTT. */ |
c44ef60e | 3209 | DRM_INFO("Memory usable by graphics device = %lluM\n", |
62106b4f JL |
3210 | ggtt->base.total >> 20); |
3211 | DRM_DEBUG_DRIVER("GMADR size = %lldM\n", ggtt->mappable_end >> 20); | |
edd1f2fe | 3212 | DRM_DEBUG_DRIVER("GTT stolen size = %uM\n", ggtt->stolen_size >> 20); |
5db6c735 DV |
3213 | #ifdef CONFIG_INTEL_IOMMU |
3214 | if (intel_iommu_gfx_mapped) | |
3215 | DRM_INFO("VT-d active for gfx access\n"); | |
3216 | #endif | |
baa09f5f BW |
3217 | |
3218 | return 0; | |
0088e522 CW |
3219 | } |
3220 | ||
3221 | /** | |
3222 | * i915_ggtt_init_hw - Initialize GGTT hardware | |
97d6d7ab | 3223 | * @dev_priv: i915 device |
0088e522 | 3224 | */ |
97d6d7ab | 3225 | int i915_ggtt_init_hw(struct drm_i915_private *dev_priv) |
0088e522 | 3226 | { |
0088e522 CW |
3227 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
3228 | int ret; | |
3229 | ||
f6b9d5ca CW |
3230 | INIT_LIST_HEAD(&dev_priv->vm_list); |
3231 | ||
3232 | /* Subtract the guard page before address space initialization to | |
3233 | * shrink the range used by drm_mm. | |
3234 | */ | |
80b204bc | 3235 | mutex_lock(&dev_priv->drm.struct_mutex); |
f6b9d5ca | 3236 | ggtt->base.total -= PAGE_SIZE; |
80b204bc | 3237 | i915_address_space_init(&ggtt->base, dev_priv, "[global]"); |
f6b9d5ca CW |
3238 | ggtt->base.total += PAGE_SIZE; |
3239 | if (!HAS_LLC(dev_priv)) | |
3240 | ggtt->base.mm.color_adjust = i915_gtt_color_adjust; | |
80b204bc | 3241 | mutex_unlock(&dev_priv->drm.struct_mutex); |
f6b9d5ca | 3242 | |
f7bbe788 CW |
3243 | if (!io_mapping_init_wc(&dev_priv->ggtt.mappable, |
3244 | dev_priv->ggtt.mappable_base, | |
3245 | dev_priv->ggtt.mappable_end)) { | |
f6b9d5ca CW |
3246 | ret = -EIO; |
3247 | goto out_gtt_cleanup; | |
3248 | } | |
3249 | ||
3250 | ggtt->mtrr = arch_phys_wc_add(ggtt->mappable_base, ggtt->mappable_end); | |
3251 | ||
0088e522 CW |
3252 | /* |
3253 | * Initialise stolen early so that we may reserve preallocated | |
3254 | * objects for the BIOS to KMS transition. | |
3255 | */ | |
7ace3d30 | 3256 | ret = i915_gem_init_stolen(dev_priv); |
0088e522 CW |
3257 | if (ret) |
3258 | goto out_gtt_cleanup; | |
3259 | ||
3260 | return 0; | |
a4eba47b ID |
3261 | |
3262 | out_gtt_cleanup: | |
72e96d64 | 3263 | ggtt->base.cleanup(&ggtt->base); |
a4eba47b | 3264 | return ret; |
baa09f5f | 3265 | } |
6f65e29a | 3266 | |
97d6d7ab | 3267 | int i915_ggtt_enable_hw(struct drm_i915_private *dev_priv) |
ac840ae5 | 3268 | { |
97d6d7ab | 3269 | if (INTEL_GEN(dev_priv) < 6 && !intel_enable_gtt()) |
ac840ae5 VS |
3270 | return -EIO; |
3271 | ||
3272 | return 0; | |
3273 | } | |
3274 | ||
275a991c | 3275 | void i915_gem_restore_gtt_mappings(struct drm_i915_private *dev_priv) |
fa42331b | 3276 | { |
72e96d64 | 3277 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
fbb30a5c | 3278 | struct drm_i915_gem_object *obj, *on; |
fa42331b | 3279 | |
dc97997a | 3280 | i915_check_and_clear_faults(dev_priv); |
fa42331b DV |
3281 | |
3282 | /* First fill our portion of the GTT with scratch pages */ | |
4fb84d99 | 3283 | ggtt->base.clear_range(&ggtt->base, ggtt->base.start, ggtt->base.total); |
fa42331b | 3284 | |
fbb30a5c CW |
3285 | ggtt->base.closed = true; /* skip rewriting PTE on VMA unbind */ |
3286 | ||
3287 | /* clflush objects bound into the GGTT and rebind them. */ | |
3288 | list_for_each_entry_safe(obj, on, | |
56cea323 | 3289 | &dev_priv->mm.bound_list, global_link) { |
fbb30a5c CW |
3290 | bool ggtt_bound = false; |
3291 | struct i915_vma *vma; | |
3292 | ||
1c7f4bca | 3293 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
72e96d64 | 3294 | if (vma->vm != &ggtt->base) |
2c3d9984 | 3295 | continue; |
fa42331b | 3296 | |
fbb30a5c CW |
3297 | if (!i915_vma_unbind(vma)) |
3298 | continue; | |
3299 | ||
2c3d9984 TU |
3300 | WARN_ON(i915_vma_bind(vma, obj->cache_level, |
3301 | PIN_UPDATE)); | |
fbb30a5c | 3302 | ggtt_bound = true; |
2c3d9984 TU |
3303 | } |
3304 | ||
fbb30a5c | 3305 | if (ggtt_bound) |
975f7ff4 | 3306 | WARN_ON(i915_gem_object_set_to_gtt_domain(obj, false)); |
2c3d9984 | 3307 | } |
fa42331b | 3308 | |
fbb30a5c CW |
3309 | ggtt->base.closed = false; |
3310 | ||
275a991c | 3311 | if (INTEL_GEN(dev_priv) >= 8) { |
cc3f90f0 | 3312 | if (IS_CHERRYVIEW(dev_priv) || IS_GEN9_LP(dev_priv)) |
fa42331b DV |
3313 | chv_setup_private_ppat(dev_priv); |
3314 | else | |
3315 | bdw_setup_private_ppat(dev_priv); | |
3316 | ||
3317 | return; | |
3318 | } | |
3319 | ||
275a991c | 3320 | if (USES_PPGTT(dev_priv)) { |
72e96d64 JL |
3321 | struct i915_address_space *vm; |
3322 | ||
fa42331b DV |
3323 | list_for_each_entry(vm, &dev_priv->vm_list, global_link) { |
3324 | /* TODO: Perhaps it shouldn't be gen6 specific */ | |
3325 | ||
e5716f55 | 3326 | struct i915_hw_ppgtt *ppgtt; |
fa42331b | 3327 | |
2bfa996e | 3328 | if (i915_is_ggtt(vm)) |
fa42331b | 3329 | ppgtt = dev_priv->mm.aliasing_ppgtt; |
e5716f55 JL |
3330 | else |
3331 | ppgtt = i915_vm_to_ppgtt(vm); | |
fa42331b DV |
3332 | |
3333 | gen6_write_page_range(dev_priv, &ppgtt->pd, | |
3334 | 0, ppgtt->base.total); | |
3335 | } | |
3336 | } | |
3337 | ||
3338 | i915_ggtt_flush(dev_priv); | |
3339 | } | |
3340 | ||
6f65e29a | 3341 | struct i915_vma * |
058d88c4 CW |
3342 | i915_gem_obj_to_vma(struct drm_i915_gem_object *obj, |
3343 | struct i915_address_space *vm, | |
3344 | const struct i915_ggtt_view *view) | |
ec7adb6e | 3345 | { |
db6c2b41 | 3346 | struct rb_node *rb; |
ec7adb6e | 3347 | |
db6c2b41 CW |
3348 | rb = obj->vma_tree.rb_node; |
3349 | while (rb) { | |
3350 | struct i915_vma *vma = rb_entry(rb, struct i915_vma, obj_node); | |
3351 | long cmp; | |
3352 | ||
b42fe9ca | 3353 | cmp = i915_vma_compare(vma, vm, view); |
db6c2b41 | 3354 | if (cmp == 0) |
058d88c4 | 3355 | return vma; |
ec7adb6e | 3356 | |
db6c2b41 CW |
3357 | if (cmp < 0) |
3358 | rb = rb->rb_right; | |
3359 | else | |
3360 | rb = rb->rb_left; | |
3361 | } | |
3362 | ||
058d88c4 | 3363 | return NULL; |
ec7adb6e JL |
3364 | } |
3365 | ||
3366 | struct i915_vma * | |
058d88c4 CW |
3367 | i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj, |
3368 | struct i915_address_space *vm, | |
3369 | const struct i915_ggtt_view *view) | |
6f65e29a | 3370 | { |
058d88c4 | 3371 | struct i915_vma *vma; |
ec7adb6e | 3372 | |
4c7d62c6 | 3373 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
058d88c4 | 3374 | GEM_BUG_ON(view && !i915_is_ggtt(vm)); |
de895082 | 3375 | |
058d88c4 | 3376 | vma = i915_gem_obj_to_vma(obj, vm, view); |
db6c2b41 | 3377 | if (!vma) { |
b42fe9ca | 3378 | vma = i915_vma_create(obj, vm, view); |
db6c2b41 CW |
3379 | GEM_BUG_ON(vma != i915_gem_obj_to_vma(obj, vm, view)); |
3380 | } | |
6f65e29a | 3381 | |
3272db53 | 3382 | GEM_BUG_ON(i915_vma_is_closed(vma)); |
6f65e29a BW |
3383 | return vma; |
3384 | } | |
fe14d5f4 | 3385 | |
804beb4b | 3386 | static struct scatterlist * |
2d7f3bdb | 3387 | rotate_pages(const dma_addr_t *in, unsigned int offset, |
804beb4b | 3388 | unsigned int width, unsigned int height, |
87130255 | 3389 | unsigned int stride, |
804beb4b | 3390 | struct sg_table *st, struct scatterlist *sg) |
50470bb0 TU |
3391 | { |
3392 | unsigned int column, row; | |
3393 | unsigned int src_idx; | |
50470bb0 | 3394 | |
50470bb0 | 3395 | for (column = 0; column < width; column++) { |
87130255 | 3396 | src_idx = stride * (height - 1) + column; |
50470bb0 TU |
3397 | for (row = 0; row < height; row++) { |
3398 | st->nents++; | |
3399 | /* We don't need the pages, but need to initialize | |
3400 | * the entries so the sg list can be happily traversed. | |
3401 | * The only thing we need are DMA addresses. | |
3402 | */ | |
3403 | sg_set_page(sg, NULL, PAGE_SIZE, 0); | |
804beb4b | 3404 | sg_dma_address(sg) = in[offset + src_idx]; |
50470bb0 TU |
3405 | sg_dma_len(sg) = PAGE_SIZE; |
3406 | sg = sg_next(sg); | |
87130255 | 3407 | src_idx -= stride; |
50470bb0 TU |
3408 | } |
3409 | } | |
804beb4b TU |
3410 | |
3411 | return sg; | |
50470bb0 TU |
3412 | } |
3413 | ||
3414 | static struct sg_table * | |
6687c906 | 3415 | intel_rotate_fb_obj_pages(const struct intel_rotation_info *rot_info, |
50470bb0 TU |
3416 | struct drm_i915_gem_object *obj) |
3417 | { | |
85d1225e | 3418 | const size_t n_pages = obj->base.size / PAGE_SIZE; |
6687c906 | 3419 | unsigned int size = intel_rotation_info_size(rot_info); |
85d1225e DG |
3420 | struct sgt_iter sgt_iter; |
3421 | dma_addr_t dma_addr; | |
50470bb0 TU |
3422 | unsigned long i; |
3423 | dma_addr_t *page_addr_list; | |
3424 | struct sg_table *st; | |
89e3e142 | 3425 | struct scatterlist *sg; |
1d00dad5 | 3426 | int ret = -ENOMEM; |
50470bb0 | 3427 | |
50470bb0 | 3428 | /* Allocate a temporary list of source pages for random access. */ |
85d1225e | 3429 | page_addr_list = drm_malloc_gfp(n_pages, |
f2a85e19 CW |
3430 | sizeof(dma_addr_t), |
3431 | GFP_TEMPORARY); | |
50470bb0 TU |
3432 | if (!page_addr_list) |
3433 | return ERR_PTR(ret); | |
3434 | ||
3435 | /* Allocate target SG list. */ | |
3436 | st = kmalloc(sizeof(*st), GFP_KERNEL); | |
3437 | if (!st) | |
3438 | goto err_st_alloc; | |
3439 | ||
6687c906 | 3440 | ret = sg_alloc_table(st, size, GFP_KERNEL); |
50470bb0 TU |
3441 | if (ret) |
3442 | goto err_sg_alloc; | |
3443 | ||
3444 | /* Populate source page list from the object. */ | |
3445 | i = 0; | |
a4f5ea64 | 3446 | for_each_sgt_dma(dma_addr, sgt_iter, obj->mm.pages) |
85d1225e | 3447 | page_addr_list[i++] = dma_addr; |
50470bb0 | 3448 | |
85d1225e | 3449 | GEM_BUG_ON(i != n_pages); |
11f20322 VS |
3450 | st->nents = 0; |
3451 | sg = st->sgl; | |
3452 | ||
6687c906 VS |
3453 | for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++) { |
3454 | sg = rotate_pages(page_addr_list, rot_info->plane[i].offset, | |
3455 | rot_info->plane[i].width, rot_info->plane[i].height, | |
3456 | rot_info->plane[i].stride, st, sg); | |
89e3e142 TU |
3457 | } |
3458 | ||
6687c906 VS |
3459 | DRM_DEBUG_KMS("Created rotated page mapping for object size %zu (%ux%u tiles, %u pages)\n", |
3460 | obj->base.size, rot_info->plane[0].width, rot_info->plane[0].height, size); | |
50470bb0 TU |
3461 | |
3462 | drm_free_large(page_addr_list); | |
3463 | ||
3464 | return st; | |
3465 | ||
3466 | err_sg_alloc: | |
3467 | kfree(st); | |
3468 | err_st_alloc: | |
3469 | drm_free_large(page_addr_list); | |
3470 | ||
6687c906 VS |
3471 | DRM_DEBUG_KMS("Failed to create rotated mapping for object size %zu! (%ux%u tiles, %u pages)\n", |
3472 | obj->base.size, rot_info->plane[0].width, rot_info->plane[0].height, size); | |
3473 | ||
50470bb0 TU |
3474 | return ERR_PTR(ret); |
3475 | } | |
ec7adb6e | 3476 | |
8bd7ef16 JL |
3477 | static struct sg_table * |
3478 | intel_partial_pages(const struct i915_ggtt_view *view, | |
3479 | struct drm_i915_gem_object *obj) | |
3480 | { | |
3481 | struct sg_table *st; | |
d2a84a76 CW |
3482 | struct scatterlist *sg, *iter; |
3483 | unsigned int count = view->params.partial.size; | |
3484 | unsigned int offset; | |
8bd7ef16 JL |
3485 | int ret = -ENOMEM; |
3486 | ||
3487 | st = kmalloc(sizeof(*st), GFP_KERNEL); | |
3488 | if (!st) | |
3489 | goto err_st_alloc; | |
3490 | ||
d2a84a76 | 3491 | ret = sg_alloc_table(st, count, GFP_KERNEL); |
8bd7ef16 JL |
3492 | if (ret) |
3493 | goto err_sg_alloc; | |
3494 | ||
d2a84a76 CW |
3495 | iter = i915_gem_object_get_sg(obj, |
3496 | view->params.partial.offset, | |
3497 | &offset); | |
3498 | GEM_BUG_ON(!iter); | |
3499 | ||
8bd7ef16 JL |
3500 | sg = st->sgl; |
3501 | st->nents = 0; | |
d2a84a76 CW |
3502 | do { |
3503 | unsigned int len; | |
8bd7ef16 | 3504 | |
d2a84a76 CW |
3505 | len = min(iter->length - (offset << PAGE_SHIFT), |
3506 | count << PAGE_SHIFT); | |
3507 | sg_set_page(sg, NULL, len, 0); | |
3508 | sg_dma_address(sg) = | |
3509 | sg_dma_address(iter) + (offset << PAGE_SHIFT); | |
3510 | sg_dma_len(sg) = len; | |
8bd7ef16 | 3511 | |
8bd7ef16 | 3512 | st->nents++; |
d2a84a76 CW |
3513 | count -= len >> PAGE_SHIFT; |
3514 | if (count == 0) { | |
3515 | sg_mark_end(sg); | |
3516 | return st; | |
3517 | } | |
8bd7ef16 | 3518 | |
d2a84a76 CW |
3519 | sg = __sg_next(sg); |
3520 | iter = __sg_next(iter); | |
3521 | offset = 0; | |
3522 | } while (1); | |
8bd7ef16 JL |
3523 | |
3524 | err_sg_alloc: | |
3525 | kfree(st); | |
3526 | err_st_alloc: | |
3527 | return ERR_PTR(ret); | |
3528 | } | |
3529 | ||
70b9f6f8 | 3530 | static int |
50470bb0 | 3531 | i915_get_ggtt_vma_pages(struct i915_vma *vma) |
fe14d5f4 | 3532 | { |
50470bb0 TU |
3533 | int ret = 0; |
3534 | ||
2c3a3f44 CW |
3535 | /* The vma->pages are only valid within the lifespan of the borrowed |
3536 | * obj->mm.pages. When the obj->mm.pages sg_table is regenerated, so | |
3537 | * must be the vma->pages. A simple rule is that vma->pages must only | |
3538 | * be accessed when the obj->mm.pages are pinned. | |
3539 | */ | |
3540 | GEM_BUG_ON(!i915_gem_object_has_pinned_pages(vma->obj)); | |
3541 | ||
247177dd | 3542 | if (vma->pages) |
fe14d5f4 TU |
3543 | return 0; |
3544 | ||
3545 | if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) | |
a4f5ea64 | 3546 | vma->pages = vma->obj->mm.pages; |
50470bb0 | 3547 | else if (vma->ggtt_view.type == I915_GGTT_VIEW_ROTATED) |
247177dd | 3548 | vma->pages = |
11d23e6f | 3549 | intel_rotate_fb_obj_pages(&vma->ggtt_view.params.rotated, vma->obj); |
8bd7ef16 | 3550 | else if (vma->ggtt_view.type == I915_GGTT_VIEW_PARTIAL) |
247177dd | 3551 | vma->pages = intel_partial_pages(&vma->ggtt_view, vma->obj); |
fe14d5f4 TU |
3552 | else |
3553 | WARN_ONCE(1, "GGTT view %u not implemented!\n", | |
3554 | vma->ggtt_view.type); | |
3555 | ||
247177dd | 3556 | if (!vma->pages) { |
ec7adb6e | 3557 | DRM_ERROR("Failed to get pages for GGTT view type %u!\n", |
fe14d5f4 | 3558 | vma->ggtt_view.type); |
50470bb0 | 3559 | ret = -EINVAL; |
247177dd CW |
3560 | } else if (IS_ERR(vma->pages)) { |
3561 | ret = PTR_ERR(vma->pages); | |
3562 | vma->pages = NULL; | |
50470bb0 TU |
3563 | DRM_ERROR("Failed to get pages for VMA view type %u (%d)!\n", |
3564 | vma->ggtt_view.type, ret); | |
fe14d5f4 TU |
3565 | } |
3566 | ||
50470bb0 | 3567 | return ret; |
fe14d5f4 TU |
3568 | } |
3569 |