]>
Commit | Line | Data |
---|---|---|
76aaf220 DV |
1 | /* |
2 | * Copyright © 2010 Daniel Vetter | |
c4ac524c | 3 | * Copyright © 2011-2014 Intel Corporation |
76aaf220 DV |
4 | * |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
22 | * IN THE SOFTWARE. | |
23 | * | |
24 | */ | |
25 | ||
aae4a3d8 CW |
26 | #include <linux/slab.h> /* fault-inject.h is not standalone! */ |
27 | ||
28 | #include <linux/fault-inject.h> | |
e007b19d | 29 | #include <linux/log2.h> |
606fec95 | 30 | #include <linux/random.h> |
0e46ce2e | 31 | #include <linux/seq_file.h> |
5bab6f60 | 32 | #include <linux/stop_machine.h> |
e007b19d | 33 | |
ed3ba079 LA |
34 | #include <asm/set_memory.h> |
35 | ||
760285e7 DH |
36 | #include <drm/drmP.h> |
37 | #include <drm/i915_drm.h> | |
e007b19d | 38 | |
76aaf220 | 39 | #include "i915_drv.h" |
5dda8fa3 | 40 | #include "i915_vgpu.h" |
76aaf220 DV |
41 | #include "i915_trace.h" |
42 | #include "intel_drv.h" | |
d07f0e59 | 43 | #include "intel_frontbuffer.h" |
76aaf220 | 44 | |
bb8f9cff CW |
45 | #define I915_GFP_DMA (GFP_KERNEL | __GFP_HIGHMEM) |
46 | ||
45f8f69a TU |
47 | /** |
48 | * DOC: Global GTT views | |
49 | * | |
50 | * Background and previous state | |
51 | * | |
52 | * Historically objects could exists (be bound) in global GTT space only as | |
53 | * singular instances with a view representing all of the object's backing pages | |
54 | * in a linear fashion. This view will be called a normal view. | |
55 | * | |
56 | * To support multiple views of the same object, where the number of mapped | |
57 | * pages is not equal to the backing store, or where the layout of the pages | |
58 | * is not linear, concept of a GGTT view was added. | |
59 | * | |
60 | * One example of an alternative view is a stereo display driven by a single | |
61 | * image. In this case we would have a framebuffer looking like this | |
62 | * (2x2 pages): | |
63 | * | |
64 | * 12 | |
65 | * 34 | |
66 | * | |
67 | * Above would represent a normal GGTT view as normally mapped for GPU or CPU | |
68 | * rendering. In contrast, fed to the display engine would be an alternative | |
69 | * view which could look something like this: | |
70 | * | |
71 | * 1212 | |
72 | * 3434 | |
73 | * | |
74 | * In this example both the size and layout of pages in the alternative view is | |
75 | * different from the normal view. | |
76 | * | |
77 | * Implementation and usage | |
78 | * | |
79 | * GGTT views are implemented using VMAs and are distinguished via enum | |
80 | * i915_ggtt_view_type and struct i915_ggtt_view. | |
81 | * | |
82 | * A new flavour of core GEM functions which work with GGTT bound objects were | |
ec7adb6e JL |
83 | * added with the _ggtt_ infix, and sometimes with _view postfix to avoid |
84 | * renaming in large amounts of code. They take the struct i915_ggtt_view | |
85 | * parameter encapsulating all metadata required to implement a view. | |
45f8f69a TU |
86 | * |
87 | * As a helper for callers which are only interested in the normal view, | |
88 | * globally const i915_ggtt_view_normal singleton instance exists. All old core | |
89 | * GEM API functions, the ones not taking the view parameter, are operating on, | |
90 | * or with the normal GGTT view. | |
91 | * | |
92 | * Code wanting to add or use a new GGTT view needs to: | |
93 | * | |
94 | * 1. Add a new enum with a suitable name. | |
95 | * 2. Extend the metadata in the i915_ggtt_view structure if required. | |
96 | * 3. Add support to i915_get_vma_pages(). | |
97 | * | |
98 | * New views are required to build a scatter-gather table from within the | |
99 | * i915_get_vma_pages function. This table is stored in the vma.ggtt_view and | |
100 | * exists for the lifetime of an VMA. | |
101 | * | |
102 | * Core API is designed to have copy semantics which means that passed in | |
103 | * struct i915_ggtt_view does not need to be persistent (left around after | |
104 | * calling the core API functions). | |
105 | * | |
106 | */ | |
107 | ||
70b9f6f8 DV |
108 | static int |
109 | i915_get_ggtt_vma_pages(struct i915_vma *vma); | |
110 | ||
7c3f86b6 CW |
111 | static void gen6_ggtt_invalidate(struct drm_i915_private *dev_priv) |
112 | { | |
113 | /* Note that as an uncached mmio write, this should flush the | |
114 | * WCB of the writes into the GGTT before it triggers the invalidate. | |
115 | */ | |
116 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
117 | } | |
118 | ||
119 | static void guc_ggtt_invalidate(struct drm_i915_private *dev_priv) | |
120 | { | |
121 | gen6_ggtt_invalidate(dev_priv); | |
122 | I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE); | |
123 | } | |
124 | ||
125 | static void gmch_ggtt_invalidate(struct drm_i915_private *dev_priv) | |
126 | { | |
127 | intel_gtt_chipset_flush(); | |
128 | } | |
129 | ||
130 | static inline void i915_ggtt_invalidate(struct drm_i915_private *i915) | |
131 | { | |
132 | i915->ggtt.invalidate(i915); | |
133 | } | |
134 | ||
c033666a CW |
135 | int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv, |
136 | int enable_ppgtt) | |
cfa7c862 | 137 | { |
1893a71b | 138 | bool has_full_ppgtt; |
1f9a99e0 | 139 | bool has_full_48bit_ppgtt; |
1893a71b | 140 | |
612dde7e JL |
141 | if (!dev_priv->info.has_aliasing_ppgtt) |
142 | return 0; | |
143 | ||
9e1d0e60 MT |
144 | has_full_ppgtt = dev_priv->info.has_full_ppgtt; |
145 | has_full_48bit_ppgtt = dev_priv->info.has_full_48bit_ppgtt; | |
1893a71b | 146 | |
e320d400 | 147 | if (intel_vgpu_active(dev_priv)) { |
8a4ab66f | 148 | /* GVT-g has no support for 32bit ppgtt */ |
e320d400 | 149 | has_full_ppgtt = false; |
8a4ab66f | 150 | has_full_48bit_ppgtt = intel_vgpu_has_full_48bit_ppgtt(dev_priv); |
e320d400 | 151 | } |
71ba2d64 | 152 | |
70ee45e1 DL |
153 | /* |
154 | * We don't allow disabling PPGTT for gen9+ as it's a requirement for | |
155 | * execlists, the sole mechanism available to submit work. | |
156 | */ | |
c033666a | 157 | if (enable_ppgtt == 0 && INTEL_GEN(dev_priv) < 9) |
cfa7c862 DV |
158 | return 0; |
159 | ||
160 | if (enable_ppgtt == 1) | |
161 | return 1; | |
162 | ||
1893a71b | 163 | if (enable_ppgtt == 2 && has_full_ppgtt) |
cfa7c862 DV |
164 | return 2; |
165 | ||
1f9a99e0 MT |
166 | if (enable_ppgtt == 3 && has_full_48bit_ppgtt) |
167 | return 3; | |
168 | ||
93a25a9e | 169 | /* Disable ppgtt on SNB if VT-d is on. */ |
80debff8 | 170 | if (IS_GEN6(dev_priv) && intel_vtd_active()) { |
93a25a9e | 171 | DRM_INFO("Disabling PPGTT because VT-d is on\n"); |
cfa7c862 | 172 | return 0; |
93a25a9e | 173 | } |
93a25a9e | 174 | |
62942ed7 | 175 | /* Early VLV doesn't have this */ |
91c8a326 | 176 | if (IS_VALLEYVIEW(dev_priv) && dev_priv->drm.pdev->revision < 0xb) { |
62942ed7 JB |
177 | DRM_DEBUG_DRIVER("disabling PPGTT on pre-B3 step VLV\n"); |
178 | return 0; | |
179 | } | |
180 | ||
4f044a88 | 181 | if (INTEL_GEN(dev_priv) >= 8 && i915_modparams.enable_execlists) { |
4fc05063 JL |
182 | if (has_full_48bit_ppgtt) |
183 | return 3; | |
184 | ||
185 | if (has_full_ppgtt) | |
186 | return 2; | |
187 | } | |
188 | ||
612dde7e | 189 | return 1; |
93a25a9e DV |
190 | } |
191 | ||
70b9f6f8 DV |
192 | static int ppgtt_bind_vma(struct i915_vma *vma, |
193 | enum i915_cache_level cache_level, | |
194 | u32 unused) | |
47552659 | 195 | { |
ff685975 CW |
196 | u32 pte_flags; |
197 | int ret; | |
198 | ||
1f23475c MA |
199 | if (!(vma->flags & I915_VMA_LOCAL_BIND)) { |
200 | ret = vma->vm->allocate_va_range(vma->vm, vma->node.start, | |
201 | vma->size); | |
202 | if (ret) | |
203 | return ret; | |
204 | } | |
47552659 DV |
205 | |
206 | /* Currently applicable only to VLV */ | |
ff685975 | 207 | pte_flags = 0; |
47552659 DV |
208 | if (vma->obj->gt_ro) |
209 | pte_flags |= PTE_READ_ONLY; | |
210 | ||
4a234c5f | 211 | vma->vm->insert_entries(vma->vm, vma, cache_level, pte_flags); |
70b9f6f8 DV |
212 | |
213 | return 0; | |
47552659 DV |
214 | } |
215 | ||
216 | static void ppgtt_unbind_vma(struct i915_vma *vma) | |
217 | { | |
ff685975 | 218 | vma->vm->clear_range(vma->vm, vma->node.start, vma->size); |
47552659 | 219 | } |
6f65e29a | 220 | |
fa3f46af MA |
221 | static int ppgtt_set_pages(struct i915_vma *vma) |
222 | { | |
223 | GEM_BUG_ON(vma->pages); | |
224 | ||
225 | vma->pages = vma->obj->mm.pages; | |
226 | ||
7464284b MA |
227 | vma->page_sizes = vma->obj->mm.page_sizes; |
228 | ||
fa3f46af MA |
229 | return 0; |
230 | } | |
231 | ||
232 | static void clear_pages(struct i915_vma *vma) | |
233 | { | |
234 | GEM_BUG_ON(!vma->pages); | |
235 | ||
236 | if (vma->pages != vma->obj->mm.pages) { | |
237 | sg_free_table(vma->pages); | |
238 | kfree(vma->pages); | |
239 | } | |
240 | vma->pages = NULL; | |
7464284b MA |
241 | |
242 | memset(&vma->page_sizes, 0, sizeof(vma->page_sizes)); | |
fa3f46af MA |
243 | } |
244 | ||
2c642b07 | 245 | static gen8_pte_t gen8_pte_encode(dma_addr_t addr, |
b512e960 JB |
246 | enum i915_cache_level level, |
247 | u32 flags) | |
94ec8f61 | 248 | { |
b512e960 JB |
249 | gen8_pte_t pte = addr | _PAGE_PRESENT | _PAGE_RW; |
250 | ||
251 | if (unlikely(flags & PTE_READ_ONLY)) | |
252 | pte &= ~_PAGE_RW; | |
63c42e56 BW |
253 | |
254 | switch (level) { | |
255 | case I915_CACHE_NONE: | |
c095b97c | 256 | pte |= PPAT_UNCACHED; |
63c42e56 BW |
257 | break; |
258 | case I915_CACHE_WT: | |
c095b97c | 259 | pte |= PPAT_DISPLAY_ELLC; |
63c42e56 BW |
260 | break; |
261 | default: | |
c095b97c | 262 | pte |= PPAT_CACHED; |
63c42e56 BW |
263 | break; |
264 | } | |
265 | ||
94ec8f61 BW |
266 | return pte; |
267 | } | |
268 | ||
fe36f55d MK |
269 | static gen8_pde_t gen8_pde_encode(const dma_addr_t addr, |
270 | const enum i915_cache_level level) | |
b1fe6673 | 271 | { |
07749ef3 | 272 | gen8_pde_t pde = _PAGE_PRESENT | _PAGE_RW; |
b1fe6673 BW |
273 | pde |= addr; |
274 | if (level != I915_CACHE_NONE) | |
c095b97c | 275 | pde |= PPAT_CACHED_PDE; |
b1fe6673 | 276 | else |
c095b97c | 277 | pde |= PPAT_UNCACHED; |
b1fe6673 BW |
278 | return pde; |
279 | } | |
280 | ||
762d9936 MT |
281 | #define gen8_pdpe_encode gen8_pde_encode |
282 | #define gen8_pml4e_encode gen8_pde_encode | |
283 | ||
07749ef3 MT |
284 | static gen6_pte_t snb_pte_encode(dma_addr_t addr, |
285 | enum i915_cache_level level, | |
4fb84d99 | 286 | u32 unused) |
54d12527 | 287 | { |
4fb84d99 | 288 | gen6_pte_t pte = GEN6_PTE_VALID; |
54d12527 | 289 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
e7210c3c BW |
290 | |
291 | switch (level) { | |
350ec881 CW |
292 | case I915_CACHE_L3_LLC: |
293 | case I915_CACHE_LLC: | |
294 | pte |= GEN6_PTE_CACHE_LLC; | |
295 | break; | |
296 | case I915_CACHE_NONE: | |
297 | pte |= GEN6_PTE_UNCACHED; | |
298 | break; | |
299 | default: | |
5f77eeb0 | 300 | MISSING_CASE(level); |
350ec881 CW |
301 | } |
302 | ||
303 | return pte; | |
304 | } | |
305 | ||
07749ef3 MT |
306 | static gen6_pte_t ivb_pte_encode(dma_addr_t addr, |
307 | enum i915_cache_level level, | |
4fb84d99 | 308 | u32 unused) |
350ec881 | 309 | { |
4fb84d99 | 310 | gen6_pte_t pte = GEN6_PTE_VALID; |
350ec881 CW |
311 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
312 | ||
313 | switch (level) { | |
314 | case I915_CACHE_L3_LLC: | |
315 | pte |= GEN7_PTE_CACHE_L3_LLC; | |
e7210c3c BW |
316 | break; |
317 | case I915_CACHE_LLC: | |
318 | pte |= GEN6_PTE_CACHE_LLC; | |
319 | break; | |
320 | case I915_CACHE_NONE: | |
9119708c | 321 | pte |= GEN6_PTE_UNCACHED; |
e7210c3c BW |
322 | break; |
323 | default: | |
5f77eeb0 | 324 | MISSING_CASE(level); |
e7210c3c BW |
325 | } |
326 | ||
54d12527 BW |
327 | return pte; |
328 | } | |
329 | ||
07749ef3 MT |
330 | static gen6_pte_t byt_pte_encode(dma_addr_t addr, |
331 | enum i915_cache_level level, | |
4fb84d99 | 332 | u32 flags) |
93c34e70 | 333 | { |
4fb84d99 | 334 | gen6_pte_t pte = GEN6_PTE_VALID; |
93c34e70 KG |
335 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
336 | ||
24f3a8cf AG |
337 | if (!(flags & PTE_READ_ONLY)) |
338 | pte |= BYT_PTE_WRITEABLE; | |
93c34e70 KG |
339 | |
340 | if (level != I915_CACHE_NONE) | |
341 | pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES; | |
342 | ||
343 | return pte; | |
344 | } | |
345 | ||
07749ef3 MT |
346 | static gen6_pte_t hsw_pte_encode(dma_addr_t addr, |
347 | enum i915_cache_level level, | |
4fb84d99 | 348 | u32 unused) |
9119708c | 349 | { |
4fb84d99 | 350 | gen6_pte_t pte = GEN6_PTE_VALID; |
0d8ff15e | 351 | pte |= HSW_PTE_ADDR_ENCODE(addr); |
9119708c KG |
352 | |
353 | if (level != I915_CACHE_NONE) | |
87a6b688 | 354 | pte |= HSW_WB_LLC_AGE3; |
9119708c KG |
355 | |
356 | return pte; | |
357 | } | |
358 | ||
07749ef3 MT |
359 | static gen6_pte_t iris_pte_encode(dma_addr_t addr, |
360 | enum i915_cache_level level, | |
4fb84d99 | 361 | u32 unused) |
4d15c145 | 362 | { |
4fb84d99 | 363 | gen6_pte_t pte = GEN6_PTE_VALID; |
4d15c145 BW |
364 | pte |= HSW_PTE_ADDR_ENCODE(addr); |
365 | ||
651d794f CW |
366 | switch (level) { |
367 | case I915_CACHE_NONE: | |
368 | break; | |
369 | case I915_CACHE_WT: | |
c51e9701 | 370 | pte |= HSW_WT_ELLC_LLC_AGE3; |
651d794f CW |
371 | break; |
372 | default: | |
c51e9701 | 373 | pte |= HSW_WB_ELLC_LLC_AGE3; |
651d794f CW |
374 | break; |
375 | } | |
4d15c145 BW |
376 | |
377 | return pte; | |
378 | } | |
379 | ||
8448661d | 380 | static struct page *vm_alloc_page(struct i915_address_space *vm, gfp_t gfp) |
678d96fb | 381 | { |
66df1014 | 382 | struct pagevec *pvec = &vm->free_pages; |
678d96fb | 383 | |
8448661d CW |
384 | if (I915_SELFTEST_ONLY(should_fail(&vm->fault_attr, 1))) |
385 | i915_gem_shrink_all(vm->i915); | |
aae4a3d8 | 386 | |
66df1014 CW |
387 | if (likely(pvec->nr)) |
388 | return pvec->pages[--pvec->nr]; | |
389 | ||
390 | if (!vm->pt_kmap_wc) | |
391 | return alloc_page(gfp); | |
8448661d | 392 | |
66df1014 CW |
393 | /* A placeholder for a specific mutex to guard the WC stash */ |
394 | lockdep_assert_held(&vm->i915->drm.struct_mutex); | |
395 | ||
396 | /* Look in our global stash of WC pages... */ | |
397 | pvec = &vm->i915->mm.wc_stash; | |
398 | if (likely(pvec->nr)) | |
399 | return pvec->pages[--pvec->nr]; | |
400 | ||
401 | /* Otherwise batch allocate pages to amoritize cost of set_pages_wc. */ | |
402 | do { | |
403 | struct page *page; | |
8448661d | 404 | |
66df1014 CW |
405 | page = alloc_page(gfp); |
406 | if (unlikely(!page)) | |
407 | break; | |
408 | ||
409 | pvec->pages[pvec->nr++] = page; | |
410 | } while (pagevec_space(pvec)); | |
411 | ||
412 | if (unlikely(!pvec->nr)) | |
8448661d CW |
413 | return NULL; |
414 | ||
66df1014 | 415 | set_pages_array_wc(pvec->pages, pvec->nr); |
8448661d | 416 | |
66df1014 | 417 | return pvec->pages[--pvec->nr]; |
8448661d CW |
418 | } |
419 | ||
66df1014 CW |
420 | static void vm_free_pages_release(struct i915_address_space *vm, |
421 | bool immediate) | |
8448661d | 422 | { |
66df1014 CW |
423 | struct pagevec *pvec = &vm->free_pages; |
424 | ||
425 | GEM_BUG_ON(!pagevec_count(pvec)); | |
8448661d | 426 | |
66df1014 CW |
427 | if (vm->pt_kmap_wc) { |
428 | struct pagevec *stash = &vm->i915->mm.wc_stash; | |
8448661d | 429 | |
66df1014 CW |
430 | /* When we use WC, first fill up the global stash and then |
431 | * only if full immediately free the overflow. | |
432 | */ | |
8448661d | 433 | |
66df1014 CW |
434 | lockdep_assert_held(&vm->i915->drm.struct_mutex); |
435 | if (pagevec_space(stash)) { | |
436 | do { | |
437 | stash->pages[stash->nr++] = | |
438 | pvec->pages[--pvec->nr]; | |
439 | if (!pvec->nr) | |
440 | return; | |
441 | } while (pagevec_space(stash)); | |
442 | ||
443 | /* As we have made some room in the VM's free_pages, | |
444 | * we can wait for it to fill again. Unless we are | |
445 | * inside i915_address_space_fini() and must | |
446 | * immediately release the pages! | |
447 | */ | |
448 | if (!immediate) | |
449 | return; | |
450 | } | |
451 | ||
452 | set_pages_array_wb(pvec->pages, pvec->nr); | |
453 | } | |
454 | ||
455 | __pagevec_release(pvec); | |
8448661d CW |
456 | } |
457 | ||
458 | static void vm_free_page(struct i915_address_space *vm, struct page *page) | |
459 | { | |
460 | if (!pagevec_add(&vm->free_pages, page)) | |
66df1014 | 461 | vm_free_pages_release(vm, false); |
8448661d | 462 | } |
678d96fb | 463 | |
8448661d CW |
464 | static int __setup_page_dma(struct i915_address_space *vm, |
465 | struct i915_page_dma *p, | |
466 | gfp_t gfp) | |
467 | { | |
468 | p->page = vm_alloc_page(vm, gfp | __GFP_NOWARN | __GFP_NORETRY); | |
469 | if (unlikely(!p->page)) | |
470 | return -ENOMEM; | |
678d96fb | 471 | |
8448661d CW |
472 | p->daddr = dma_map_page(vm->dma, p->page, 0, PAGE_SIZE, |
473 | PCI_DMA_BIDIRECTIONAL); | |
474 | if (unlikely(dma_mapping_error(vm->dma, p->daddr))) { | |
475 | vm_free_page(vm, p->page); | |
476 | return -ENOMEM; | |
44159ddb | 477 | } |
1266cdb1 MT |
478 | |
479 | return 0; | |
678d96fb BW |
480 | } |
481 | ||
8448661d | 482 | static int setup_page_dma(struct i915_address_space *vm, |
275a991c | 483 | struct i915_page_dma *p) |
c114f76a | 484 | { |
8448661d | 485 | return __setup_page_dma(vm, p, I915_GFP_DMA); |
c114f76a MK |
486 | } |
487 | ||
8448661d | 488 | static void cleanup_page_dma(struct i915_address_space *vm, |
275a991c | 489 | struct i915_page_dma *p) |
06fda602 | 490 | { |
8448661d CW |
491 | dma_unmap_page(vm->dma, p->daddr, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); |
492 | vm_free_page(vm, p->page); | |
44159ddb MK |
493 | } |
494 | ||
9231da70 | 495 | #define kmap_atomic_px(px) kmap_atomic(px_base(px)->page) |
d1c54acd | 496 | |
8448661d CW |
497 | #define setup_px(vm, px) setup_page_dma((vm), px_base(px)) |
498 | #define cleanup_px(vm, px) cleanup_page_dma((vm), px_base(px)) | |
499 | #define fill_px(ppgtt, px, v) fill_page_dma((vm), px_base(px), (v)) | |
500 | #define fill32_px(ppgtt, px, v) fill_page_dma_32((vm), px_base(px), (v)) | |
567047be | 501 | |
8448661d CW |
502 | static void fill_page_dma(struct i915_address_space *vm, |
503 | struct i915_page_dma *p, | |
504 | const u64 val) | |
d1c54acd | 505 | { |
9231da70 | 506 | u64 * const vaddr = kmap_atomic(p->page); |
d1c54acd | 507 | |
4dd504f7 | 508 | memset64(vaddr, val, PAGE_SIZE / sizeof(val)); |
d1c54acd | 509 | |
9231da70 | 510 | kunmap_atomic(vaddr); |
d1c54acd MK |
511 | } |
512 | ||
8448661d CW |
513 | static void fill_page_dma_32(struct i915_address_space *vm, |
514 | struct i915_page_dma *p, | |
515 | const u32 v) | |
73eeea53 | 516 | { |
8448661d | 517 | fill_page_dma(vm, p, (u64)v << 32 | v); |
73eeea53 MK |
518 | } |
519 | ||
8bcdd0f7 | 520 | static int |
8448661d | 521 | setup_scratch_page(struct i915_address_space *vm, gfp_t gfp) |
4ad2af1e | 522 | { |
aa095871 | 523 | struct page *page = NULL; |
66df1014 | 524 | dma_addr_t addr; |
aa095871 | 525 | int order; |
66df1014 | 526 | |
aa095871 MA |
527 | /* |
528 | * In order to utilize 64K pages for an object with a size < 2M, we will | |
529 | * need to support a 64K scratch page, given that every 16th entry for a | |
530 | * page-table operating in 64K mode must point to a properly aligned 64K | |
531 | * region, including any PTEs which happen to point to scratch. | |
532 | * | |
533 | * This is only relevant for the 48b PPGTT where we support | |
534 | * huge-gtt-pages, see also i915_vma_insert(). | |
535 | * | |
536 | * TODO: we should really consider write-protecting the scratch-page and | |
537 | * sharing between ppgtt | |
538 | */ | |
539 | if (i915_vm_is_48bit(vm) && | |
540 | HAS_PAGE_SIZES(vm->i915, I915_GTT_PAGE_SIZE_64K)) { | |
541 | order = get_order(I915_GTT_PAGE_SIZE_64K); | |
06ea8c53 | 542 | page = alloc_pages(gfp | __GFP_ZERO | __GFP_NOWARN, order); |
aa095871 MA |
543 | if (page) { |
544 | addr = dma_map_page(vm->dma, page, 0, | |
545 | I915_GTT_PAGE_SIZE_64K, | |
546 | PCI_DMA_BIDIRECTIONAL); | |
547 | if (unlikely(dma_mapping_error(vm->dma, addr))) { | |
548 | __free_pages(page, order); | |
549 | page = NULL; | |
550 | } | |
551 | ||
552 | if (!IS_ALIGNED(addr, I915_GTT_PAGE_SIZE_64K)) { | |
553 | dma_unmap_page(vm->dma, addr, | |
554 | I915_GTT_PAGE_SIZE_64K, | |
555 | PCI_DMA_BIDIRECTIONAL); | |
556 | __free_pages(page, order); | |
557 | page = NULL; | |
558 | } | |
559 | } | |
560 | } | |
66df1014 | 561 | |
aa095871 MA |
562 | if (!page) { |
563 | order = 0; | |
564 | page = alloc_page(gfp | __GFP_ZERO); | |
565 | if (unlikely(!page)) | |
566 | return -ENOMEM; | |
567 | ||
568 | addr = dma_map_page(vm->dma, page, 0, PAGE_SIZE, | |
569 | PCI_DMA_BIDIRECTIONAL); | |
570 | if (unlikely(dma_mapping_error(vm->dma, addr))) { | |
571 | __free_page(page); | |
572 | return -ENOMEM; | |
573 | } | |
66df1014 CW |
574 | } |
575 | ||
576 | vm->scratch_page.page = page; | |
577 | vm->scratch_page.daddr = addr; | |
aa095871 MA |
578 | vm->scratch_page.order = order; |
579 | ||
66df1014 | 580 | return 0; |
4ad2af1e MK |
581 | } |
582 | ||
8448661d | 583 | static void cleanup_scratch_page(struct i915_address_space *vm) |
4ad2af1e | 584 | { |
66df1014 CW |
585 | struct i915_page_dma *p = &vm->scratch_page; |
586 | ||
aa095871 MA |
587 | dma_unmap_page(vm->dma, p->daddr, BIT(p->order) << PAGE_SHIFT, |
588 | PCI_DMA_BIDIRECTIONAL); | |
589 | __free_pages(p->page, p->order); | |
4ad2af1e MK |
590 | } |
591 | ||
8448661d | 592 | static struct i915_page_table *alloc_pt(struct i915_address_space *vm) |
06fda602 | 593 | { |
ec565b3c | 594 | struct i915_page_table *pt; |
06fda602 | 595 | |
dd19674b CW |
596 | pt = kmalloc(sizeof(*pt), GFP_KERNEL | __GFP_NOWARN); |
597 | if (unlikely(!pt)) | |
06fda602 BW |
598 | return ERR_PTR(-ENOMEM); |
599 | ||
dd19674b CW |
600 | if (unlikely(setup_px(vm, pt))) { |
601 | kfree(pt); | |
602 | return ERR_PTR(-ENOMEM); | |
603 | } | |
06fda602 | 604 | |
dd19674b | 605 | pt->used_ptes = 0; |
06fda602 BW |
606 | return pt; |
607 | } | |
608 | ||
8448661d | 609 | static void free_pt(struct i915_address_space *vm, struct i915_page_table *pt) |
06fda602 | 610 | { |
8448661d | 611 | cleanup_px(vm, pt); |
2e906bea MK |
612 | kfree(pt); |
613 | } | |
614 | ||
615 | static void gen8_initialize_pt(struct i915_address_space *vm, | |
616 | struct i915_page_table *pt) | |
617 | { | |
dd19674b | 618 | fill_px(vm, pt, |
b512e960 | 619 | gen8_pte_encode(vm->scratch_page.daddr, I915_CACHE_LLC, 0)); |
2e906bea MK |
620 | } |
621 | ||
622 | static void gen6_initialize_pt(struct i915_address_space *vm, | |
623 | struct i915_page_table *pt) | |
624 | { | |
dd19674b CW |
625 | fill32_px(vm, pt, |
626 | vm->pte_encode(vm->scratch_page.daddr, I915_CACHE_LLC, 0)); | |
06fda602 BW |
627 | } |
628 | ||
8448661d | 629 | static struct i915_page_directory *alloc_pd(struct i915_address_space *vm) |
06fda602 | 630 | { |
ec565b3c | 631 | struct i915_page_directory *pd; |
06fda602 | 632 | |
fe52e37f CW |
633 | pd = kzalloc(sizeof(*pd), GFP_KERNEL | __GFP_NOWARN); |
634 | if (unlikely(!pd)) | |
06fda602 BW |
635 | return ERR_PTR(-ENOMEM); |
636 | ||
fe52e37f CW |
637 | if (unlikely(setup_px(vm, pd))) { |
638 | kfree(pd); | |
639 | return ERR_PTR(-ENOMEM); | |
640 | } | |
e5815a2e | 641 | |
fe52e37f | 642 | pd->used_pdes = 0; |
06fda602 BW |
643 | return pd; |
644 | } | |
645 | ||
8448661d | 646 | static void free_pd(struct i915_address_space *vm, |
275a991c | 647 | struct i915_page_directory *pd) |
2e906bea | 648 | { |
fe52e37f CW |
649 | cleanup_px(vm, pd); |
650 | kfree(pd); | |
2e906bea MK |
651 | } |
652 | ||
653 | static void gen8_initialize_pd(struct i915_address_space *vm, | |
654 | struct i915_page_directory *pd) | |
655 | { | |
dd19674b | 656 | unsigned int i; |
2e906bea | 657 | |
dd19674b CW |
658 | fill_px(vm, pd, |
659 | gen8_pde_encode(px_dma(vm->scratch_pt), I915_CACHE_LLC)); | |
660 | for (i = 0; i < I915_PDES; i++) | |
661 | pd->page_table[i] = vm->scratch_pt; | |
2e906bea MK |
662 | } |
663 | ||
fe52e37f | 664 | static int __pdp_init(struct i915_address_space *vm, |
6ac18502 MT |
665 | struct i915_page_directory_pointer *pdp) |
666 | { | |
3e490042 | 667 | const unsigned int pdpes = i915_pdpes_per_pdp(vm); |
e2b763ca | 668 | unsigned int i; |
6ac18502 | 669 | |
fe52e37f | 670 | pdp->page_directory = kmalloc_array(pdpes, sizeof(*pdp->page_directory), |
e2b763ca CW |
671 | GFP_KERNEL | __GFP_NOWARN); |
672 | if (unlikely(!pdp->page_directory)) | |
6ac18502 | 673 | return -ENOMEM; |
6ac18502 | 674 | |
fe52e37f CW |
675 | for (i = 0; i < pdpes; i++) |
676 | pdp->page_directory[i] = vm->scratch_pd; | |
677 | ||
6ac18502 MT |
678 | return 0; |
679 | } | |
680 | ||
681 | static void __pdp_fini(struct i915_page_directory_pointer *pdp) | |
682 | { | |
6ac18502 MT |
683 | kfree(pdp->page_directory); |
684 | pdp->page_directory = NULL; | |
685 | } | |
686 | ||
1e6437b0 MK |
687 | static inline bool use_4lvl(const struct i915_address_space *vm) |
688 | { | |
689 | return i915_vm_is_48bit(vm); | |
690 | } | |
691 | ||
8448661d CW |
692 | static struct i915_page_directory_pointer * |
693 | alloc_pdp(struct i915_address_space *vm) | |
762d9936 MT |
694 | { |
695 | struct i915_page_directory_pointer *pdp; | |
696 | int ret = -ENOMEM; | |
697 | ||
1e6437b0 | 698 | WARN_ON(!use_4lvl(vm)); |
762d9936 MT |
699 | |
700 | pdp = kzalloc(sizeof(*pdp), GFP_KERNEL); | |
701 | if (!pdp) | |
702 | return ERR_PTR(-ENOMEM); | |
703 | ||
fe52e37f | 704 | ret = __pdp_init(vm, pdp); |
762d9936 MT |
705 | if (ret) |
706 | goto fail_bitmap; | |
707 | ||
8448661d | 708 | ret = setup_px(vm, pdp); |
762d9936 MT |
709 | if (ret) |
710 | goto fail_page_m; | |
711 | ||
712 | return pdp; | |
713 | ||
714 | fail_page_m: | |
715 | __pdp_fini(pdp); | |
716 | fail_bitmap: | |
717 | kfree(pdp); | |
718 | ||
719 | return ERR_PTR(ret); | |
720 | } | |
721 | ||
8448661d | 722 | static void free_pdp(struct i915_address_space *vm, |
6ac18502 MT |
723 | struct i915_page_directory_pointer *pdp) |
724 | { | |
725 | __pdp_fini(pdp); | |
1e6437b0 MK |
726 | |
727 | if (!use_4lvl(vm)) | |
728 | return; | |
729 | ||
730 | cleanup_px(vm, pdp); | |
731 | kfree(pdp); | |
762d9936 MT |
732 | } |
733 | ||
69ab76fd MT |
734 | static void gen8_initialize_pdp(struct i915_address_space *vm, |
735 | struct i915_page_directory_pointer *pdp) | |
736 | { | |
737 | gen8_ppgtt_pdpe_t scratch_pdpe; | |
738 | ||
739 | scratch_pdpe = gen8_pdpe_encode(px_dma(vm->scratch_pd), I915_CACHE_LLC); | |
740 | ||
8448661d | 741 | fill_px(vm, pdp, scratch_pdpe); |
69ab76fd MT |
742 | } |
743 | ||
744 | static void gen8_initialize_pml4(struct i915_address_space *vm, | |
745 | struct i915_pml4 *pml4) | |
746 | { | |
e2b763ca | 747 | unsigned int i; |
762d9936 | 748 | |
e2b763ca CW |
749 | fill_px(vm, pml4, |
750 | gen8_pml4e_encode(px_dma(vm->scratch_pdp), I915_CACHE_LLC)); | |
751 | for (i = 0; i < GEN8_PML4ES_PER_PML4; i++) | |
752 | pml4->pdps[i] = vm->scratch_pdp; | |
6ac18502 MT |
753 | } |
754 | ||
94e409c1 | 755 | /* Broadwell Page Directory Pointer Descriptors */ |
e85b26dc | 756 | static int gen8_write_pdp(struct drm_i915_gem_request *req, |
7cb6d7ac MT |
757 | unsigned entry, |
758 | dma_addr_t addr) | |
94e409c1 | 759 | { |
4a570db5 | 760 | struct intel_engine_cs *engine = req->engine; |
73dec95e | 761 | u32 *cs; |
94e409c1 BW |
762 | |
763 | BUG_ON(entry >= 4); | |
764 | ||
73dec95e TU |
765 | cs = intel_ring_begin(req, 6); |
766 | if (IS_ERR(cs)) | |
767 | return PTR_ERR(cs); | |
94e409c1 | 768 | |
73dec95e TU |
769 | *cs++ = MI_LOAD_REGISTER_IMM(1); |
770 | *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(engine, entry)); | |
771 | *cs++ = upper_32_bits(addr); | |
772 | *cs++ = MI_LOAD_REGISTER_IMM(1); | |
773 | *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(engine, entry)); | |
774 | *cs++ = lower_32_bits(addr); | |
775 | intel_ring_advance(req, cs); | |
94e409c1 BW |
776 | |
777 | return 0; | |
778 | } | |
779 | ||
e7167769 MK |
780 | static int gen8_mm_switch_3lvl(struct i915_hw_ppgtt *ppgtt, |
781 | struct drm_i915_gem_request *req) | |
94e409c1 | 782 | { |
eeb9488e | 783 | int i, ret; |
94e409c1 | 784 | |
e7167769 | 785 | for (i = GEN8_3LVL_PDPES - 1; i >= 0; i--) { |
d852c7bf MK |
786 | const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i); |
787 | ||
e85b26dc | 788 | ret = gen8_write_pdp(req, i, pd_daddr); |
eeb9488e BW |
789 | if (ret) |
790 | return ret; | |
94e409c1 | 791 | } |
d595bd4b | 792 | |
eeb9488e | 793 | return 0; |
94e409c1 BW |
794 | } |
795 | ||
e7167769 MK |
796 | static int gen8_mm_switch_4lvl(struct i915_hw_ppgtt *ppgtt, |
797 | struct drm_i915_gem_request *req) | |
2dba3239 MT |
798 | { |
799 | return gen8_write_pdp(req, 0, px_dma(&ppgtt->pml4)); | |
800 | } | |
801 | ||
fce93755 MK |
802 | /* PDE TLBs are a pain to invalidate on GEN8+. When we modify |
803 | * the page table structures, we mark them dirty so that | |
804 | * context switching/execlist queuing code takes extra steps | |
805 | * to ensure that tlbs are flushed. | |
806 | */ | |
807 | static void mark_tlbs_dirty(struct i915_hw_ppgtt *ppgtt) | |
808 | { | |
49d73912 | 809 | ppgtt->pd_dirty_rings = INTEL_INFO(ppgtt->base.i915)->ring_mask; |
fce93755 MK |
810 | } |
811 | ||
2ce5179f MW |
812 | /* Removes entries from a single page table, releasing it if it's empty. |
813 | * Caller can use the return value to update higher-level entries. | |
814 | */ | |
815 | static bool gen8_ppgtt_clear_pt(struct i915_address_space *vm, | |
d209b9c3 | 816 | struct i915_page_table *pt, |
dd19674b | 817 | u64 start, u64 length) |
459108b8 | 818 | { |
d209b9c3 | 819 | unsigned int num_entries = gen8_pte_count(start, length); |
37c63934 MK |
820 | unsigned int pte = gen8_pte_index(start); |
821 | unsigned int pte_end = pte + num_entries; | |
894ccebe | 822 | const gen8_pte_t scratch_pte = |
b512e960 | 823 | gen8_pte_encode(vm->scratch_page.daddr, I915_CACHE_LLC, 0); |
894ccebe | 824 | gen8_pte_t *vaddr; |
459108b8 | 825 | |
dd19674b | 826 | GEM_BUG_ON(num_entries > pt->used_ptes); |
37c63934 | 827 | |
dd19674b CW |
828 | pt->used_ptes -= num_entries; |
829 | if (!pt->used_ptes) | |
830 | return true; | |
2ce5179f | 831 | |
9231da70 | 832 | vaddr = kmap_atomic_px(pt); |
37c63934 | 833 | while (pte < pte_end) |
894ccebe | 834 | vaddr[pte++] = scratch_pte; |
9231da70 | 835 | kunmap_atomic(vaddr); |
2ce5179f MW |
836 | |
837 | return false; | |
d209b9c3 | 838 | } |
06fda602 | 839 | |
dd19674b CW |
840 | static void gen8_ppgtt_set_pde(struct i915_address_space *vm, |
841 | struct i915_page_directory *pd, | |
842 | struct i915_page_table *pt, | |
843 | unsigned int pde) | |
844 | { | |
845 | gen8_pde_t *vaddr; | |
846 | ||
847 | pd->page_table[pde] = pt; | |
848 | ||
849 | vaddr = kmap_atomic_px(pd); | |
850 | vaddr[pde] = gen8_pde_encode(px_dma(pt), I915_CACHE_LLC); | |
851 | kunmap_atomic(vaddr); | |
852 | } | |
853 | ||
2ce5179f | 854 | static bool gen8_ppgtt_clear_pd(struct i915_address_space *vm, |
d209b9c3 | 855 | struct i915_page_directory *pd, |
dd19674b | 856 | u64 start, u64 length) |
d209b9c3 MW |
857 | { |
858 | struct i915_page_table *pt; | |
dd19674b | 859 | u32 pde; |
d209b9c3 MW |
860 | |
861 | gen8_for_each_pde(pt, pd, start, length, pde) { | |
bf75d59e CW |
862 | GEM_BUG_ON(pt == vm->scratch_pt); |
863 | ||
dd19674b CW |
864 | if (!gen8_ppgtt_clear_pt(vm, pt, start, length)) |
865 | continue; | |
06fda602 | 866 | |
dd19674b | 867 | gen8_ppgtt_set_pde(vm, pd, vm->scratch_pt, pde); |
bf75d59e | 868 | GEM_BUG_ON(!pd->used_pdes); |
fe52e37f | 869 | pd->used_pdes--; |
dd19674b CW |
870 | |
871 | free_pt(vm, pt); | |
2ce5179f MW |
872 | } |
873 | ||
fe52e37f CW |
874 | return !pd->used_pdes; |
875 | } | |
2ce5179f | 876 | |
fe52e37f CW |
877 | static void gen8_ppgtt_set_pdpe(struct i915_address_space *vm, |
878 | struct i915_page_directory_pointer *pdp, | |
879 | struct i915_page_directory *pd, | |
880 | unsigned int pdpe) | |
881 | { | |
882 | gen8_ppgtt_pdpe_t *vaddr; | |
883 | ||
884 | pdp->page_directory[pdpe] = pd; | |
1e6437b0 | 885 | if (!use_4lvl(vm)) |
fe52e37f CW |
886 | return; |
887 | ||
888 | vaddr = kmap_atomic_px(pdp); | |
889 | vaddr[pdpe] = gen8_pdpe_encode(px_dma(pd), I915_CACHE_LLC); | |
890 | kunmap_atomic(vaddr); | |
d209b9c3 | 891 | } |
06fda602 | 892 | |
2ce5179f MW |
893 | /* Removes entries from a single page dir pointer, releasing it if it's empty. |
894 | * Caller can use the return value to update higher-level entries | |
895 | */ | |
896 | static bool gen8_ppgtt_clear_pdp(struct i915_address_space *vm, | |
d209b9c3 | 897 | struct i915_page_directory_pointer *pdp, |
fe52e37f | 898 | u64 start, u64 length) |
d209b9c3 MW |
899 | { |
900 | struct i915_page_directory *pd; | |
fe52e37f | 901 | unsigned int pdpe; |
06fda602 | 902 | |
d209b9c3 | 903 | gen8_for_each_pdpe(pd, pdp, start, length, pdpe) { |
bf75d59e CW |
904 | GEM_BUG_ON(pd == vm->scratch_pd); |
905 | ||
fe52e37f CW |
906 | if (!gen8_ppgtt_clear_pd(vm, pd, start, length)) |
907 | continue; | |
459108b8 | 908 | |
fe52e37f | 909 | gen8_ppgtt_set_pdpe(vm, pdp, vm->scratch_pd, pdpe); |
bf75d59e | 910 | GEM_BUG_ON(!pdp->used_pdpes); |
e2b763ca | 911 | pdp->used_pdpes--; |
2ce5179f | 912 | |
fe52e37f CW |
913 | free_pd(vm, pd); |
914 | } | |
fce93755 | 915 | |
e2b763ca | 916 | return !pdp->used_pdpes; |
d209b9c3 | 917 | } |
459108b8 | 918 | |
fe52e37f CW |
919 | static void gen8_ppgtt_clear_3lvl(struct i915_address_space *vm, |
920 | u64 start, u64 length) | |
921 | { | |
922 | gen8_ppgtt_clear_pdp(vm, &i915_vm_to_ppgtt(vm)->pdp, start, length); | |
923 | } | |
924 | ||
e2b763ca CW |
925 | static void gen8_ppgtt_set_pml4e(struct i915_pml4 *pml4, |
926 | struct i915_page_directory_pointer *pdp, | |
927 | unsigned int pml4e) | |
928 | { | |
929 | gen8_ppgtt_pml4e_t *vaddr; | |
930 | ||
931 | pml4->pdps[pml4e] = pdp; | |
932 | ||
933 | vaddr = kmap_atomic_px(pml4); | |
934 | vaddr[pml4e] = gen8_pml4e_encode(px_dma(pdp), I915_CACHE_LLC); | |
935 | kunmap_atomic(vaddr); | |
936 | } | |
937 | ||
2ce5179f MW |
938 | /* Removes entries from a single pml4. |
939 | * This is the top-level structure in 4-level page tables used on gen8+. | |
940 | * Empty entries are always scratch pml4e. | |
941 | */ | |
fe52e37f CW |
942 | static void gen8_ppgtt_clear_4lvl(struct i915_address_space *vm, |
943 | u64 start, u64 length) | |
d209b9c3 | 944 | { |
fe52e37f CW |
945 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
946 | struct i915_pml4 *pml4 = &ppgtt->pml4; | |
d209b9c3 | 947 | struct i915_page_directory_pointer *pdp; |
e2b763ca | 948 | unsigned int pml4e; |
2ce5179f | 949 | |
1e6437b0 | 950 | GEM_BUG_ON(!use_4lvl(vm)); |
459108b8 | 951 | |
d209b9c3 | 952 | gen8_for_each_pml4e(pdp, pml4, start, length, pml4e) { |
bf75d59e CW |
953 | GEM_BUG_ON(pdp == vm->scratch_pdp); |
954 | ||
e2b763ca CW |
955 | if (!gen8_ppgtt_clear_pdp(vm, pdp, start, length)) |
956 | continue; | |
459108b8 | 957 | |
e2b763ca | 958 | gen8_ppgtt_set_pml4e(pml4, vm->scratch_pdp, pml4e); |
e2b763ca CW |
959 | |
960 | free_pdp(vm, pdp); | |
459108b8 BW |
961 | } |
962 | } | |
963 | ||
423a8a94 | 964 | static inline struct sgt_dma { |
894ccebe CW |
965 | struct scatterlist *sg; |
966 | dma_addr_t dma, max; | |
423a8a94 CW |
967 | } sgt_dma(struct i915_vma *vma) { |
968 | struct scatterlist *sg = vma->pages->sgl; | |
969 | dma_addr_t addr = sg_dma_address(sg); | |
970 | return (struct sgt_dma) { sg, addr, addr + sg->length }; | |
971 | } | |
894ccebe | 972 | |
9e89f9ee CW |
973 | struct gen8_insert_pte { |
974 | u16 pml4e; | |
975 | u16 pdpe; | |
976 | u16 pde; | |
977 | u16 pte; | |
978 | }; | |
979 | ||
980 | static __always_inline struct gen8_insert_pte gen8_insert_pte(u64 start) | |
981 | { | |
982 | return (struct gen8_insert_pte) { | |
983 | gen8_pml4e_index(start), | |
984 | gen8_pdpe_index(start), | |
985 | gen8_pde_index(start), | |
986 | gen8_pte_index(start), | |
987 | }; | |
988 | } | |
989 | ||
894ccebe CW |
990 | static __always_inline bool |
991 | gen8_ppgtt_insert_pte_entries(struct i915_hw_ppgtt *ppgtt, | |
f9b5b782 | 992 | struct i915_page_directory_pointer *pdp, |
894ccebe | 993 | struct sgt_dma *iter, |
9e89f9ee | 994 | struct gen8_insert_pte *idx, |
f9b5b782 MT |
995 | enum i915_cache_level cache_level) |
996 | { | |
894ccebe | 997 | struct i915_page_directory *pd; |
b512e960 | 998 | const gen8_pte_t pte_encode = gen8_pte_encode(0, cache_level, 0); |
894ccebe CW |
999 | gen8_pte_t *vaddr; |
1000 | bool ret; | |
9df15b49 | 1001 | |
3e490042 | 1002 | GEM_BUG_ON(idx->pdpe >= i915_pdpes_per_pdp(&ppgtt->base)); |
9e89f9ee CW |
1003 | pd = pdp->page_directory[idx->pdpe]; |
1004 | vaddr = kmap_atomic_px(pd->page_table[idx->pde]); | |
894ccebe | 1005 | do { |
9e89f9ee CW |
1006 | vaddr[idx->pte] = pte_encode | iter->dma; |
1007 | ||
da1d95b6 | 1008 | iter->dma += I915_GTT_PAGE_SIZE; |
894ccebe CW |
1009 | if (iter->dma >= iter->max) { |
1010 | iter->sg = __sg_next(iter->sg); | |
1011 | if (!iter->sg) { | |
1012 | ret = false; | |
1013 | break; | |
1014 | } | |
7ad47cf2 | 1015 | |
894ccebe CW |
1016 | iter->dma = sg_dma_address(iter->sg); |
1017 | iter->max = iter->dma + iter->sg->length; | |
d7b3de91 | 1018 | } |
9df15b49 | 1019 | |
9e89f9ee CW |
1020 | if (++idx->pte == GEN8_PTES) { |
1021 | idx->pte = 0; | |
1022 | ||
1023 | if (++idx->pde == I915_PDES) { | |
1024 | idx->pde = 0; | |
1025 | ||
894ccebe | 1026 | /* Limited by sg length for 3lvl */ |
9e89f9ee CW |
1027 | if (++idx->pdpe == GEN8_PML4ES_PER_PML4) { |
1028 | idx->pdpe = 0; | |
894ccebe | 1029 | ret = true; |
de5ba8eb | 1030 | break; |
894ccebe CW |
1031 | } |
1032 | ||
3e490042 | 1033 | GEM_BUG_ON(idx->pdpe >= i915_pdpes_per_pdp(&ppgtt->base)); |
9e89f9ee | 1034 | pd = pdp->page_directory[idx->pdpe]; |
7ad47cf2 | 1035 | } |
894ccebe | 1036 | |
9231da70 | 1037 | kunmap_atomic(vaddr); |
9e89f9ee | 1038 | vaddr = kmap_atomic_px(pd->page_table[idx->pde]); |
9df15b49 | 1039 | } |
894ccebe | 1040 | } while (1); |
9231da70 | 1041 | kunmap_atomic(vaddr); |
d1c54acd | 1042 | |
894ccebe | 1043 | return ret; |
9df15b49 BW |
1044 | } |
1045 | ||
894ccebe | 1046 | static void gen8_ppgtt_insert_3lvl(struct i915_address_space *vm, |
4a234c5f | 1047 | struct i915_vma *vma, |
894ccebe CW |
1048 | enum i915_cache_level cache_level, |
1049 | u32 unused) | |
f9b5b782 | 1050 | { |
17369ba0 | 1051 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
423a8a94 | 1052 | struct sgt_dma iter = sgt_dma(vma); |
4a234c5f | 1053 | struct gen8_insert_pte idx = gen8_insert_pte(vma->node.start); |
f9b5b782 | 1054 | |
9e89f9ee CW |
1055 | gen8_ppgtt_insert_pte_entries(ppgtt, &ppgtt->pdp, &iter, &idx, |
1056 | cache_level); | |
d9ec12f8 MA |
1057 | |
1058 | vma->page_sizes.gtt = I915_GTT_PAGE_SIZE; | |
894ccebe | 1059 | } |
de5ba8eb | 1060 | |
0a03852e MA |
1061 | static void gen8_ppgtt_insert_huge_entries(struct i915_vma *vma, |
1062 | struct i915_page_directory_pointer **pdps, | |
1063 | struct sgt_dma *iter, | |
1064 | enum i915_cache_level cache_level) | |
1065 | { | |
b512e960 | 1066 | const gen8_pte_t pte_encode = gen8_pte_encode(0, cache_level, 0); |
0a03852e MA |
1067 | u64 start = vma->node.start; |
1068 | dma_addr_t rem = iter->sg->length; | |
1069 | ||
1070 | do { | |
1071 | struct gen8_insert_pte idx = gen8_insert_pte(start); | |
1072 | struct i915_page_directory_pointer *pdp = pdps[idx.pml4e]; | |
1073 | struct i915_page_directory *pd = pdp->page_directory[idx.pdpe]; | |
1074 | unsigned int page_size; | |
17a00cf7 | 1075 | bool maybe_64K = false; |
0a03852e MA |
1076 | gen8_pte_t encode = pte_encode; |
1077 | gen8_pte_t *vaddr; | |
1078 | u16 index, max; | |
1079 | ||
1080 | if (vma->page_sizes.sg & I915_GTT_PAGE_SIZE_2M && | |
1081 | IS_ALIGNED(iter->dma, I915_GTT_PAGE_SIZE_2M) && | |
1082 | rem >= I915_GTT_PAGE_SIZE_2M && !idx.pte) { | |
1083 | index = idx.pde; | |
1084 | max = I915_PDES; | |
1085 | page_size = I915_GTT_PAGE_SIZE_2M; | |
1086 | ||
1087 | encode |= GEN8_PDE_PS_2M; | |
1088 | ||
1089 | vaddr = kmap_atomic_px(pd); | |
1090 | } else { | |
1091 | struct i915_page_table *pt = pd->page_table[idx.pde]; | |
1092 | ||
1093 | index = idx.pte; | |
1094 | max = GEN8_PTES; | |
1095 | page_size = I915_GTT_PAGE_SIZE; | |
1096 | ||
17a00cf7 MA |
1097 | if (!index && |
1098 | vma->page_sizes.sg & I915_GTT_PAGE_SIZE_64K && | |
1099 | IS_ALIGNED(iter->dma, I915_GTT_PAGE_SIZE_64K) && | |
1100 | (IS_ALIGNED(rem, I915_GTT_PAGE_SIZE_64K) || | |
1101 | rem >= (max - index) << PAGE_SHIFT)) | |
1102 | maybe_64K = true; | |
1103 | ||
0a03852e MA |
1104 | vaddr = kmap_atomic_px(pt); |
1105 | } | |
1106 | ||
1107 | do { | |
1108 | GEM_BUG_ON(iter->sg->length < page_size); | |
1109 | vaddr[index++] = encode | iter->dma; | |
1110 | ||
1111 | start += page_size; | |
1112 | iter->dma += page_size; | |
1113 | rem -= page_size; | |
1114 | if (iter->dma >= iter->max) { | |
1115 | iter->sg = __sg_next(iter->sg); | |
1116 | if (!iter->sg) | |
1117 | break; | |
1118 | ||
1119 | rem = iter->sg->length; | |
1120 | iter->dma = sg_dma_address(iter->sg); | |
1121 | iter->max = iter->dma + rem; | |
1122 | ||
17a00cf7 MA |
1123 | if (maybe_64K && index < max && |
1124 | !(IS_ALIGNED(iter->dma, I915_GTT_PAGE_SIZE_64K) && | |
1125 | (IS_ALIGNED(rem, I915_GTT_PAGE_SIZE_64K) || | |
1126 | rem >= (max - index) << PAGE_SHIFT))) | |
1127 | maybe_64K = false; | |
1128 | ||
0a03852e MA |
1129 | if (unlikely(!IS_ALIGNED(iter->dma, page_size))) |
1130 | break; | |
1131 | } | |
1132 | } while (rem >= page_size && index < max); | |
1133 | ||
1134 | kunmap_atomic(vaddr); | |
17a00cf7 MA |
1135 | |
1136 | /* | |
1137 | * Is it safe to mark the 2M block as 64K? -- Either we have | |
1138 | * filled whole page-table with 64K entries, or filled part of | |
1139 | * it and have reached the end of the sg table and we have | |
1140 | * enough padding. | |
1141 | */ | |
1142 | if (maybe_64K && | |
1143 | (index == max || | |
1144 | (i915_vm_has_scratch_64K(vma->vm) && | |
1145 | !iter->sg && IS_ALIGNED(vma->node.start + | |
1146 | vma->node.size, | |
1147 | I915_GTT_PAGE_SIZE_2M)))) { | |
1148 | vaddr = kmap_atomic_px(pd); | |
1149 | vaddr[idx.pde] |= GEN8_PDE_IPS_64K; | |
1150 | kunmap_atomic(vaddr); | |
d9ec12f8 | 1151 | page_size = I915_GTT_PAGE_SIZE_64K; |
17a00cf7 | 1152 | } |
d9ec12f8 MA |
1153 | |
1154 | vma->page_sizes.gtt |= page_size; | |
0a03852e | 1155 | } while (iter->sg); |
894ccebe | 1156 | } |
de5ba8eb | 1157 | |
894ccebe | 1158 | static void gen8_ppgtt_insert_4lvl(struct i915_address_space *vm, |
4a234c5f | 1159 | struct i915_vma *vma, |
894ccebe CW |
1160 | enum i915_cache_level cache_level, |
1161 | u32 unused) | |
1162 | { | |
1163 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); | |
423a8a94 | 1164 | struct sgt_dma iter = sgt_dma(vma); |
894ccebe | 1165 | struct i915_page_directory_pointer **pdps = ppgtt->pml4.pdps; |
de5ba8eb | 1166 | |
0a03852e MA |
1167 | if (vma->page_sizes.sg > I915_GTT_PAGE_SIZE) { |
1168 | gen8_ppgtt_insert_huge_entries(vma, pdps, &iter, cache_level); | |
1169 | } else { | |
1170 | struct gen8_insert_pte idx = gen8_insert_pte(vma->node.start); | |
1171 | ||
1172 | while (gen8_ppgtt_insert_pte_entries(ppgtt, pdps[idx.pml4e++], | |
1173 | &iter, &idx, cache_level)) | |
1174 | GEM_BUG_ON(idx.pml4e >= GEN8_PML4ES_PER_PML4); | |
d9ec12f8 MA |
1175 | |
1176 | vma->page_sizes.gtt = I915_GTT_PAGE_SIZE; | |
0a03852e | 1177 | } |
f9b5b782 MT |
1178 | } |
1179 | ||
8448661d | 1180 | static void gen8_free_page_tables(struct i915_address_space *vm, |
f37c0505 | 1181 | struct i915_page_directory *pd) |
7ad47cf2 BW |
1182 | { |
1183 | int i; | |
1184 | ||
567047be | 1185 | if (!px_page(pd)) |
7ad47cf2 BW |
1186 | return; |
1187 | ||
fe52e37f CW |
1188 | for (i = 0; i < I915_PDES; i++) { |
1189 | if (pd->page_table[i] != vm->scratch_pt) | |
1190 | free_pt(vm, pd->page_table[i]); | |
06fda602 | 1191 | } |
d7b3de91 BW |
1192 | } |
1193 | ||
8776f02b MK |
1194 | static int gen8_init_scratch(struct i915_address_space *vm) |
1195 | { | |
64c050db | 1196 | int ret; |
8776f02b | 1197 | |
8448661d | 1198 | ret = setup_scratch_page(vm, I915_GFP_DMA); |
8bcdd0f7 CW |
1199 | if (ret) |
1200 | return ret; | |
8776f02b | 1201 | |
8448661d | 1202 | vm->scratch_pt = alloc_pt(vm); |
8776f02b | 1203 | if (IS_ERR(vm->scratch_pt)) { |
64c050db MA |
1204 | ret = PTR_ERR(vm->scratch_pt); |
1205 | goto free_scratch_page; | |
8776f02b MK |
1206 | } |
1207 | ||
8448661d | 1208 | vm->scratch_pd = alloc_pd(vm); |
8776f02b | 1209 | if (IS_ERR(vm->scratch_pd)) { |
64c050db MA |
1210 | ret = PTR_ERR(vm->scratch_pd); |
1211 | goto free_pt; | |
8776f02b MK |
1212 | } |
1213 | ||
1e6437b0 | 1214 | if (use_4lvl(vm)) { |
8448661d | 1215 | vm->scratch_pdp = alloc_pdp(vm); |
69ab76fd | 1216 | if (IS_ERR(vm->scratch_pdp)) { |
64c050db MA |
1217 | ret = PTR_ERR(vm->scratch_pdp); |
1218 | goto free_pd; | |
69ab76fd MT |
1219 | } |
1220 | } | |
1221 | ||
8776f02b MK |
1222 | gen8_initialize_pt(vm, vm->scratch_pt); |
1223 | gen8_initialize_pd(vm, vm->scratch_pd); | |
1e6437b0 | 1224 | if (use_4lvl(vm)) |
69ab76fd | 1225 | gen8_initialize_pdp(vm, vm->scratch_pdp); |
8776f02b MK |
1226 | |
1227 | return 0; | |
64c050db MA |
1228 | |
1229 | free_pd: | |
8448661d | 1230 | free_pd(vm, vm->scratch_pd); |
64c050db | 1231 | free_pt: |
8448661d | 1232 | free_pt(vm, vm->scratch_pt); |
64c050db | 1233 | free_scratch_page: |
8448661d | 1234 | cleanup_scratch_page(vm); |
64c050db MA |
1235 | |
1236 | return ret; | |
8776f02b MK |
1237 | } |
1238 | ||
650da34c ZL |
1239 | static int gen8_ppgtt_notify_vgt(struct i915_hw_ppgtt *ppgtt, bool create) |
1240 | { | |
1e6437b0 MK |
1241 | struct i915_address_space *vm = &ppgtt->base; |
1242 | struct drm_i915_private *dev_priv = vm->i915; | |
650da34c | 1243 | enum vgt_g2v_type msg; |
650da34c ZL |
1244 | int i; |
1245 | ||
1e6437b0 MK |
1246 | if (use_4lvl(vm)) { |
1247 | const u64 daddr = px_dma(&ppgtt->pml4); | |
650da34c | 1248 | |
ab75bb5d VS |
1249 | I915_WRITE(vgtif_reg(pdp[0].lo), lower_32_bits(daddr)); |
1250 | I915_WRITE(vgtif_reg(pdp[0].hi), upper_32_bits(daddr)); | |
650da34c ZL |
1251 | |
1252 | msg = (create ? VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE : | |
1253 | VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY); | |
1254 | } else { | |
e7167769 | 1255 | for (i = 0; i < GEN8_3LVL_PDPES; i++) { |
1e6437b0 | 1256 | const u64 daddr = i915_page_dir_dma_addr(ppgtt, i); |
650da34c | 1257 | |
ab75bb5d VS |
1258 | I915_WRITE(vgtif_reg(pdp[i].lo), lower_32_bits(daddr)); |
1259 | I915_WRITE(vgtif_reg(pdp[i].hi), upper_32_bits(daddr)); | |
650da34c ZL |
1260 | } |
1261 | ||
1262 | msg = (create ? VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE : | |
1263 | VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY); | |
1264 | } | |
1265 | ||
1266 | I915_WRITE(vgtif_reg(g2v_notify), msg); | |
1267 | ||
1268 | return 0; | |
1269 | } | |
1270 | ||
8776f02b MK |
1271 | static void gen8_free_scratch(struct i915_address_space *vm) |
1272 | { | |
1e6437b0 | 1273 | if (use_4lvl(vm)) |
8448661d CW |
1274 | free_pdp(vm, vm->scratch_pdp); |
1275 | free_pd(vm, vm->scratch_pd); | |
1276 | free_pt(vm, vm->scratch_pt); | |
1277 | cleanup_scratch_page(vm); | |
8776f02b MK |
1278 | } |
1279 | ||
8448661d | 1280 | static void gen8_ppgtt_cleanup_3lvl(struct i915_address_space *vm, |
762d9936 | 1281 | struct i915_page_directory_pointer *pdp) |
b45a6715 | 1282 | { |
3e490042 | 1283 | const unsigned int pdpes = i915_pdpes_per_pdp(vm); |
b45a6715 BW |
1284 | int i; |
1285 | ||
3e490042 | 1286 | for (i = 0; i < pdpes; i++) { |
fe52e37f | 1287 | if (pdp->page_directory[i] == vm->scratch_pd) |
06fda602 BW |
1288 | continue; |
1289 | ||
8448661d CW |
1290 | gen8_free_page_tables(vm, pdp->page_directory[i]); |
1291 | free_pd(vm, pdp->page_directory[i]); | |
7ad47cf2 | 1292 | } |
69876bed | 1293 | |
8448661d | 1294 | free_pdp(vm, pdp); |
762d9936 MT |
1295 | } |
1296 | ||
1297 | static void gen8_ppgtt_cleanup_4lvl(struct i915_hw_ppgtt *ppgtt) | |
1298 | { | |
1299 | int i; | |
1300 | ||
c5d092a4 CW |
1301 | for (i = 0; i < GEN8_PML4ES_PER_PML4; i++) { |
1302 | if (ppgtt->pml4.pdps[i] == ppgtt->base.scratch_pdp) | |
762d9936 MT |
1303 | continue; |
1304 | ||
8448661d | 1305 | gen8_ppgtt_cleanup_3lvl(&ppgtt->base, ppgtt->pml4.pdps[i]); |
762d9936 MT |
1306 | } |
1307 | ||
8448661d | 1308 | cleanup_px(&ppgtt->base, &ppgtt->pml4); |
762d9936 MT |
1309 | } |
1310 | ||
1311 | static void gen8_ppgtt_cleanup(struct i915_address_space *vm) | |
1312 | { | |
49d73912 | 1313 | struct drm_i915_private *dev_priv = vm->i915; |
e5716f55 | 1314 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
762d9936 | 1315 | |
275a991c | 1316 | if (intel_vgpu_active(dev_priv)) |
650da34c ZL |
1317 | gen8_ppgtt_notify_vgt(ppgtt, false); |
1318 | ||
1e6437b0 | 1319 | if (use_4lvl(vm)) |
762d9936 | 1320 | gen8_ppgtt_cleanup_4lvl(ppgtt); |
1e6437b0 MK |
1321 | else |
1322 | gen8_ppgtt_cleanup_3lvl(&ppgtt->base, &ppgtt->pdp); | |
d4ec9da0 | 1323 | |
8776f02b | 1324 | gen8_free_scratch(vm); |
b45a6715 BW |
1325 | } |
1326 | ||
fe52e37f CW |
1327 | static int gen8_ppgtt_alloc_pd(struct i915_address_space *vm, |
1328 | struct i915_page_directory *pd, | |
1329 | u64 start, u64 length) | |
bf2b4ed2 | 1330 | { |
d7b2633d | 1331 | struct i915_page_table *pt; |
dd19674b | 1332 | u64 from = start; |
fe52e37f | 1333 | unsigned int pde; |
bf2b4ed2 | 1334 | |
e8ebd8e2 | 1335 | gen8_for_each_pde(pt, pd, start, length, pde) { |
14826673 CW |
1336 | int count = gen8_pte_count(start, length); |
1337 | ||
fe52e37f | 1338 | if (pt == vm->scratch_pt) { |
dd19674b CW |
1339 | pt = alloc_pt(vm); |
1340 | if (IS_ERR(pt)) | |
1341 | goto unwind; | |
5441f0cb | 1342 | |
b58d4bef | 1343 | if (count < GEN8_PTES || intel_vgpu_active(vm->i915)) |
14826673 | 1344 | gen8_initialize_pt(vm, pt); |
fe52e37f CW |
1345 | |
1346 | gen8_ppgtt_set_pde(vm, pd, pt, pde); | |
1347 | pd->used_pdes++; | |
bf75d59e | 1348 | GEM_BUG_ON(pd->used_pdes > I915_PDES); |
dd19674b | 1349 | } |
fe52e37f | 1350 | |
14826673 | 1351 | pt->used_ptes += count; |
7ad47cf2 | 1352 | } |
bf2b4ed2 | 1353 | return 0; |
7ad47cf2 | 1354 | |
dd19674b CW |
1355 | unwind: |
1356 | gen8_ppgtt_clear_pd(vm, pd, from, start - from); | |
d7b3de91 | 1357 | return -ENOMEM; |
bf2b4ed2 BW |
1358 | } |
1359 | ||
c5d092a4 CW |
1360 | static int gen8_ppgtt_alloc_pdp(struct i915_address_space *vm, |
1361 | struct i915_page_directory_pointer *pdp, | |
1362 | u64 start, u64 length) | |
bf2b4ed2 | 1363 | { |
5441f0cb | 1364 | struct i915_page_directory *pd; |
e2b763ca CW |
1365 | u64 from = start; |
1366 | unsigned int pdpe; | |
bf2b4ed2 BW |
1367 | int ret; |
1368 | ||
e8ebd8e2 | 1369 | gen8_for_each_pdpe(pd, pdp, start, length, pdpe) { |
e2b763ca CW |
1370 | if (pd == vm->scratch_pd) { |
1371 | pd = alloc_pd(vm); | |
1372 | if (IS_ERR(pd)) | |
1373 | goto unwind; | |
5441f0cb | 1374 | |
e2b763ca | 1375 | gen8_initialize_pd(vm, pd); |
fe52e37f | 1376 | gen8_ppgtt_set_pdpe(vm, pdp, pd, pdpe); |
e2b763ca | 1377 | pdp->used_pdpes++; |
3e490042 | 1378 | GEM_BUG_ON(pdp->used_pdpes > i915_pdpes_per_pdp(vm)); |
75afcf72 CW |
1379 | |
1380 | mark_tlbs_dirty(i915_vm_to_ppgtt(vm)); | |
e2b763ca CW |
1381 | } |
1382 | ||
1383 | ret = gen8_ppgtt_alloc_pd(vm, pd, start, length); | |
bf75d59e CW |
1384 | if (unlikely(ret)) |
1385 | goto unwind_pd; | |
fe52e37f | 1386 | } |
33c8819f | 1387 | |
d7b3de91 | 1388 | return 0; |
bf2b4ed2 | 1389 | |
bf75d59e CW |
1390 | unwind_pd: |
1391 | if (!pd->used_pdes) { | |
1392 | gen8_ppgtt_set_pdpe(vm, pdp, vm->scratch_pd, pdpe); | |
1393 | GEM_BUG_ON(!pdp->used_pdpes); | |
1394 | pdp->used_pdpes--; | |
1395 | free_pd(vm, pd); | |
1396 | } | |
e2b763ca CW |
1397 | unwind: |
1398 | gen8_ppgtt_clear_pdp(vm, pdp, from, start - from); | |
1399 | return -ENOMEM; | |
bf2b4ed2 BW |
1400 | } |
1401 | ||
c5d092a4 CW |
1402 | static int gen8_ppgtt_alloc_3lvl(struct i915_address_space *vm, |
1403 | u64 start, u64 length) | |
762d9936 | 1404 | { |
c5d092a4 CW |
1405 | return gen8_ppgtt_alloc_pdp(vm, |
1406 | &i915_vm_to_ppgtt(vm)->pdp, start, length); | |
1407 | } | |
762d9936 | 1408 | |
c5d092a4 CW |
1409 | static int gen8_ppgtt_alloc_4lvl(struct i915_address_space *vm, |
1410 | u64 start, u64 length) | |
1411 | { | |
1412 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); | |
1413 | struct i915_pml4 *pml4 = &ppgtt->pml4; | |
1414 | struct i915_page_directory_pointer *pdp; | |
1415 | u64 from = start; | |
1416 | u32 pml4e; | |
1417 | int ret; | |
762d9936 | 1418 | |
e8ebd8e2 | 1419 | gen8_for_each_pml4e(pdp, pml4, start, length, pml4e) { |
c5d092a4 CW |
1420 | if (pml4->pdps[pml4e] == vm->scratch_pdp) { |
1421 | pdp = alloc_pdp(vm); | |
1422 | if (IS_ERR(pdp)) | |
1423 | goto unwind; | |
762d9936 | 1424 | |
c5d092a4 CW |
1425 | gen8_initialize_pdp(vm, pdp); |
1426 | gen8_ppgtt_set_pml4e(pml4, pdp, pml4e); | |
1427 | } | |
762d9936 | 1428 | |
c5d092a4 | 1429 | ret = gen8_ppgtt_alloc_pdp(vm, pdp, start, length); |
bf75d59e CW |
1430 | if (unlikely(ret)) |
1431 | goto unwind_pdp; | |
762d9936 MT |
1432 | } |
1433 | ||
762d9936 MT |
1434 | return 0; |
1435 | ||
bf75d59e CW |
1436 | unwind_pdp: |
1437 | if (!pdp->used_pdpes) { | |
1438 | gen8_ppgtt_set_pml4e(pml4, vm->scratch_pdp, pml4e); | |
1439 | free_pdp(vm, pdp); | |
1440 | } | |
c5d092a4 CW |
1441 | unwind: |
1442 | gen8_ppgtt_clear_4lvl(vm, from, start - from); | |
1443 | return -ENOMEM; | |
762d9936 MT |
1444 | } |
1445 | ||
8448661d CW |
1446 | static void gen8_dump_pdp(struct i915_hw_ppgtt *ppgtt, |
1447 | struct i915_page_directory_pointer *pdp, | |
75c7b0b8 | 1448 | u64 start, u64 length, |
ea91e401 MT |
1449 | gen8_pte_t scratch_pte, |
1450 | struct seq_file *m) | |
1451 | { | |
3e490042 | 1452 | struct i915_address_space *vm = &ppgtt->base; |
ea91e401 | 1453 | struct i915_page_directory *pd; |
75c7b0b8 | 1454 | u32 pdpe; |
ea91e401 | 1455 | |
e8ebd8e2 | 1456 | gen8_for_each_pdpe(pd, pdp, start, length, pdpe) { |
ea91e401 | 1457 | struct i915_page_table *pt; |
75c7b0b8 CW |
1458 | u64 pd_len = length; |
1459 | u64 pd_start = start; | |
1460 | u32 pde; | |
ea91e401 | 1461 | |
e2b763ca | 1462 | if (pdp->page_directory[pdpe] == ppgtt->base.scratch_pd) |
ea91e401 MT |
1463 | continue; |
1464 | ||
1465 | seq_printf(m, "\tPDPE #%d\n", pdpe); | |
e8ebd8e2 | 1466 | gen8_for_each_pde(pt, pd, pd_start, pd_len, pde) { |
75c7b0b8 | 1467 | u32 pte; |
ea91e401 MT |
1468 | gen8_pte_t *pt_vaddr; |
1469 | ||
fe52e37f | 1470 | if (pd->page_table[pde] == ppgtt->base.scratch_pt) |
ea91e401 MT |
1471 | continue; |
1472 | ||
9231da70 | 1473 | pt_vaddr = kmap_atomic_px(pt); |
ea91e401 | 1474 | for (pte = 0; pte < GEN8_PTES; pte += 4) { |
75c7b0b8 CW |
1475 | u64 va = (pdpe << GEN8_PDPE_SHIFT | |
1476 | pde << GEN8_PDE_SHIFT | | |
1477 | pte << GEN8_PTE_SHIFT); | |
ea91e401 MT |
1478 | int i; |
1479 | bool found = false; | |
1480 | ||
1481 | for (i = 0; i < 4; i++) | |
1482 | if (pt_vaddr[pte + i] != scratch_pte) | |
1483 | found = true; | |
1484 | if (!found) | |
1485 | continue; | |
1486 | ||
1487 | seq_printf(m, "\t\t0x%llx [%03d,%03d,%04d]: =", va, pdpe, pde, pte); | |
1488 | for (i = 0; i < 4; i++) { | |
1489 | if (pt_vaddr[pte + i] != scratch_pte) | |
1490 | seq_printf(m, " %llx", pt_vaddr[pte + i]); | |
1491 | else | |
1492 | seq_puts(m, " SCRATCH "); | |
1493 | } | |
1494 | seq_puts(m, "\n"); | |
1495 | } | |
ea91e401 MT |
1496 | kunmap_atomic(pt_vaddr); |
1497 | } | |
1498 | } | |
1499 | } | |
1500 | ||
1501 | static void gen8_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m) | |
1502 | { | |
1503 | struct i915_address_space *vm = &ppgtt->base; | |
894ccebe | 1504 | const gen8_pte_t scratch_pte = |
b512e960 | 1505 | gen8_pte_encode(vm->scratch_page.daddr, I915_CACHE_LLC, 0); |
381b943b | 1506 | u64 start = 0, length = ppgtt->base.total; |
ea91e401 | 1507 | |
1e6437b0 | 1508 | if (use_4lvl(vm)) { |
75c7b0b8 | 1509 | u64 pml4e; |
ea91e401 MT |
1510 | struct i915_pml4 *pml4 = &ppgtt->pml4; |
1511 | struct i915_page_directory_pointer *pdp; | |
1512 | ||
e8ebd8e2 | 1513 | gen8_for_each_pml4e(pdp, pml4, start, length, pml4e) { |
c5d092a4 | 1514 | if (pml4->pdps[pml4e] == ppgtt->base.scratch_pdp) |
ea91e401 MT |
1515 | continue; |
1516 | ||
1517 | seq_printf(m, " PML4E #%llu\n", pml4e); | |
8448661d | 1518 | gen8_dump_pdp(ppgtt, pdp, start, length, scratch_pte, m); |
ea91e401 | 1519 | } |
1e6437b0 MK |
1520 | } else { |
1521 | gen8_dump_pdp(ppgtt, &ppgtt->pdp, start, length, scratch_pte, m); | |
ea91e401 MT |
1522 | } |
1523 | } | |
1524 | ||
e2b763ca | 1525 | static int gen8_preallocate_top_level_pdp(struct i915_hw_ppgtt *ppgtt) |
331f38e7 | 1526 | { |
e2b763ca CW |
1527 | struct i915_address_space *vm = &ppgtt->base; |
1528 | struct i915_page_directory_pointer *pdp = &ppgtt->pdp; | |
1529 | struct i915_page_directory *pd; | |
1530 | u64 start = 0, length = ppgtt->base.total; | |
1531 | u64 from = start; | |
1532 | unsigned int pdpe; | |
331f38e7 | 1533 | |
e2b763ca CW |
1534 | gen8_for_each_pdpe(pd, pdp, start, length, pdpe) { |
1535 | pd = alloc_pd(vm); | |
1536 | if (IS_ERR(pd)) | |
1537 | goto unwind; | |
331f38e7 | 1538 | |
e2b763ca CW |
1539 | gen8_initialize_pd(vm, pd); |
1540 | gen8_ppgtt_set_pdpe(vm, pdp, pd, pdpe); | |
1541 | pdp->used_pdpes++; | |
1542 | } | |
331f38e7 | 1543 | |
e2b763ca CW |
1544 | pdp->used_pdpes++; /* never remove */ |
1545 | return 0; | |
331f38e7 | 1546 | |
e2b763ca CW |
1547 | unwind: |
1548 | start -= from; | |
1549 | gen8_for_each_pdpe(pd, pdp, from, start, pdpe) { | |
1550 | gen8_ppgtt_set_pdpe(vm, pdp, vm->scratch_pd, pdpe); | |
1551 | free_pd(vm, pd); | |
1552 | } | |
1553 | pdp->used_pdpes = 0; | |
1554 | return -ENOMEM; | |
331f38e7 ZL |
1555 | } |
1556 | ||
eb0b44ad | 1557 | /* |
f3a964b9 BW |
1558 | * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers |
1559 | * with a net effect resembling a 2-level page table in normal x86 terms. Each | |
1560 | * PDP represents 1GB of memory 4 * 512 * 512 * 4096 = 4GB legacy 32b address | |
1561 | * space. | |
37aca44a | 1562 | * |
f3a964b9 | 1563 | */ |
5c5f6457 | 1564 | static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt) |
37aca44a | 1565 | { |
1e6437b0 MK |
1566 | struct i915_address_space *vm = &ppgtt->base; |
1567 | struct drm_i915_private *dev_priv = vm->i915; | |
8776f02b | 1568 | int ret; |
7cb6d7ac | 1569 | |
1e6437b0 MK |
1570 | ppgtt->base.total = USES_FULL_48BIT_PPGTT(dev_priv) ? |
1571 | 1ULL << 48 : | |
1572 | 1ULL << 32; | |
1573 | ||
8448661d CW |
1574 | /* There are only few exceptions for gen >=6. chv and bxt. |
1575 | * And we are not sure about the latter so play safe for now. | |
1576 | */ | |
1577 | if (IS_CHERRYVIEW(dev_priv) || IS_BROXTON(dev_priv)) | |
1578 | ppgtt->base.pt_kmap_wc = true; | |
1579 | ||
66df1014 CW |
1580 | ret = gen8_init_scratch(&ppgtt->base); |
1581 | if (ret) { | |
1582 | ppgtt->base.total = 0; | |
1583 | return ret; | |
1584 | } | |
1585 | ||
1e6437b0 | 1586 | if (use_4lvl(vm)) { |
8448661d | 1587 | ret = setup_px(&ppgtt->base, &ppgtt->pml4); |
762d9936 MT |
1588 | if (ret) |
1589 | goto free_scratch; | |
6ac18502 | 1590 | |
69ab76fd MT |
1591 | gen8_initialize_pml4(&ppgtt->base, &ppgtt->pml4); |
1592 | ||
e7167769 | 1593 | ppgtt->switch_mm = gen8_mm_switch_4lvl; |
c5d092a4 | 1594 | ppgtt->base.allocate_va_range = gen8_ppgtt_alloc_4lvl; |
894ccebe | 1595 | ppgtt->base.insert_entries = gen8_ppgtt_insert_4lvl; |
fe52e37f | 1596 | ppgtt->base.clear_range = gen8_ppgtt_clear_4lvl; |
762d9936 | 1597 | } else { |
fe52e37f | 1598 | ret = __pdp_init(&ppgtt->base, &ppgtt->pdp); |
81ba8aef MT |
1599 | if (ret) |
1600 | goto free_scratch; | |
1601 | ||
275a991c | 1602 | if (intel_vgpu_active(dev_priv)) { |
e2b763ca CW |
1603 | ret = gen8_preallocate_top_level_pdp(ppgtt); |
1604 | if (ret) { | |
1605 | __pdp_fini(&ppgtt->pdp); | |
331f38e7 | 1606 | goto free_scratch; |
e2b763ca | 1607 | } |
331f38e7 | 1608 | } |
894ccebe | 1609 | |
e7167769 | 1610 | ppgtt->switch_mm = gen8_mm_switch_3lvl; |
c5d092a4 | 1611 | ppgtt->base.allocate_va_range = gen8_ppgtt_alloc_3lvl; |
894ccebe | 1612 | ppgtt->base.insert_entries = gen8_ppgtt_insert_3lvl; |
fe52e37f | 1613 | ppgtt->base.clear_range = gen8_ppgtt_clear_3lvl; |
81ba8aef | 1614 | } |
6ac18502 | 1615 | |
275a991c | 1616 | if (intel_vgpu_active(dev_priv)) |
650da34c ZL |
1617 | gen8_ppgtt_notify_vgt(ppgtt, true); |
1618 | ||
054b9acd MK |
1619 | ppgtt->base.cleanup = gen8_ppgtt_cleanup; |
1620 | ppgtt->base.unbind_vma = ppgtt_unbind_vma; | |
1621 | ppgtt->base.bind_vma = ppgtt_bind_vma; | |
fa3f46af MA |
1622 | ppgtt->base.set_pages = ppgtt_set_pages; |
1623 | ppgtt->base.clear_pages = clear_pages; | |
054b9acd MK |
1624 | ppgtt->debug_dump = gen8_dump_ppgtt; |
1625 | ||
d7b2633d | 1626 | return 0; |
6ac18502 MT |
1627 | |
1628 | free_scratch: | |
1629 | gen8_free_scratch(&ppgtt->base); | |
1630 | return ret; | |
d7b2633d MT |
1631 | } |
1632 | ||
87d60b63 BW |
1633 | static void gen6_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m) |
1634 | { | |
87d60b63 | 1635 | struct i915_address_space *vm = &ppgtt->base; |
09942c65 | 1636 | struct i915_page_table *unused; |
07749ef3 | 1637 | gen6_pte_t scratch_pte; |
381b943b CW |
1638 | u32 pd_entry, pte, pde; |
1639 | u32 start = 0, length = ppgtt->base.total; | |
87d60b63 | 1640 | |
8bcdd0f7 | 1641 | scratch_pte = vm->pte_encode(vm->scratch_page.daddr, |
4fb84d99 | 1642 | I915_CACHE_LLC, 0); |
87d60b63 | 1643 | |
731f74c5 | 1644 | gen6_for_each_pde(unused, &ppgtt->pd, start, length, pde) { |
87d60b63 | 1645 | u32 expected; |
07749ef3 | 1646 | gen6_pte_t *pt_vaddr; |
567047be | 1647 | const dma_addr_t pt_addr = px_dma(ppgtt->pd.page_table[pde]); |
09942c65 | 1648 | pd_entry = readl(ppgtt->pd_addr + pde); |
87d60b63 BW |
1649 | expected = (GEN6_PDE_ADDR_ENCODE(pt_addr) | GEN6_PDE_VALID); |
1650 | ||
1651 | if (pd_entry != expected) | |
1652 | seq_printf(m, "\tPDE #%d mismatch: Actual PDE: %x Expected PDE: %x\n", | |
1653 | pde, | |
1654 | pd_entry, | |
1655 | expected); | |
1656 | seq_printf(m, "\tPDE: %x\n", pd_entry); | |
1657 | ||
9231da70 | 1658 | pt_vaddr = kmap_atomic_px(ppgtt->pd.page_table[pde]); |
d1c54acd | 1659 | |
07749ef3 | 1660 | for (pte = 0; pte < GEN6_PTES; pte+=4) { |
87d60b63 | 1661 | unsigned long va = |
da1d95b6 VS |
1662 | (pde * I915_GTT_PAGE_SIZE * GEN6_PTES) + |
1663 | (pte * I915_GTT_PAGE_SIZE); | |
87d60b63 BW |
1664 | int i; |
1665 | bool found = false; | |
1666 | for (i = 0; i < 4; i++) | |
1667 | if (pt_vaddr[pte + i] != scratch_pte) | |
1668 | found = true; | |
1669 | if (!found) | |
1670 | continue; | |
1671 | ||
e8066911 | 1672 | seq_printf(m, "\t\t0x%lx [%03d,%04d]: =", va, pde, pte); |
87d60b63 BW |
1673 | for (i = 0; i < 4; i++) { |
1674 | if (pt_vaddr[pte + i] != scratch_pte) | |
1675 | seq_printf(m, " %08x", pt_vaddr[pte + i]); | |
1676 | else | |
1677 | seq_puts(m, " SCRATCH "); | |
1678 | } | |
1679 | seq_puts(m, "\n"); | |
1680 | } | |
9231da70 | 1681 | kunmap_atomic(pt_vaddr); |
87d60b63 BW |
1682 | } |
1683 | } | |
1684 | ||
678d96fb | 1685 | /* Write pde (index) from the page directory @pd to the page table @pt */ |
16a011c8 CW |
1686 | static inline void gen6_write_pde(const struct i915_hw_ppgtt *ppgtt, |
1687 | const unsigned int pde, | |
1688 | const struct i915_page_table *pt) | |
6197349b | 1689 | { |
678d96fb | 1690 | /* Caller needs to make sure the write completes if necessary */ |
16a011c8 CW |
1691 | writel_relaxed(GEN6_PDE_ADDR_ENCODE(px_dma(pt)) | GEN6_PDE_VALID, |
1692 | ppgtt->pd_addr + pde); | |
678d96fb | 1693 | } |
6197349b | 1694 | |
678d96fb BW |
1695 | /* Write all the page tables found in the ppgtt structure to incrementing page |
1696 | * directories. */ | |
16a011c8 | 1697 | static void gen6_write_page_range(struct i915_hw_ppgtt *ppgtt, |
75c7b0b8 | 1698 | u32 start, u32 length) |
678d96fb | 1699 | { |
ec565b3c | 1700 | struct i915_page_table *pt; |
16a011c8 | 1701 | unsigned int pde; |
678d96fb | 1702 | |
16a011c8 CW |
1703 | gen6_for_each_pde(pt, &ppgtt->pd, start, length, pde) |
1704 | gen6_write_pde(ppgtt, pde, pt); | |
678d96fb | 1705 | |
16a011c8 | 1706 | mark_tlbs_dirty(ppgtt); |
dd19674b | 1707 | wmb(); |
3e302542 BW |
1708 | } |
1709 | ||
75c7b0b8 | 1710 | static inline u32 get_pd_offset(struct i915_hw_ppgtt *ppgtt) |
3e302542 | 1711 | { |
dd19674b CW |
1712 | GEM_BUG_ON(ppgtt->pd.base.ggtt_offset & 0x3f); |
1713 | return ppgtt->pd.base.ggtt_offset << 10; | |
b4a74e3a BW |
1714 | } |
1715 | ||
90252e5c | 1716 | static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt, |
e85b26dc | 1717 | struct drm_i915_gem_request *req) |
90252e5c | 1718 | { |
4a570db5 | 1719 | struct intel_engine_cs *engine = req->engine; |
73dec95e | 1720 | u32 *cs; |
90252e5c | 1721 | |
90252e5c | 1722 | /* NB: TLBs must be flushed and invalidated before a switch */ |
73dec95e TU |
1723 | cs = intel_ring_begin(req, 6); |
1724 | if (IS_ERR(cs)) | |
1725 | return PTR_ERR(cs); | |
90252e5c | 1726 | |
73dec95e TU |
1727 | *cs++ = MI_LOAD_REGISTER_IMM(2); |
1728 | *cs++ = i915_mmio_reg_offset(RING_PP_DIR_DCLV(engine)); | |
1729 | *cs++ = PP_DIR_DCLV_2G; | |
1730 | *cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine)); | |
1731 | *cs++ = get_pd_offset(ppgtt); | |
1732 | *cs++ = MI_NOOP; | |
1733 | intel_ring_advance(req, cs); | |
90252e5c BW |
1734 | |
1735 | return 0; | |
1736 | } | |
1737 | ||
48a10389 | 1738 | static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt, |
e85b26dc | 1739 | struct drm_i915_gem_request *req) |
48a10389 | 1740 | { |
4a570db5 | 1741 | struct intel_engine_cs *engine = req->engine; |
73dec95e | 1742 | u32 *cs; |
48a10389 | 1743 | |
48a10389 | 1744 | /* NB: TLBs must be flushed and invalidated before a switch */ |
73dec95e TU |
1745 | cs = intel_ring_begin(req, 6); |
1746 | if (IS_ERR(cs)) | |
1747 | return PTR_ERR(cs); | |
1748 | ||
1749 | *cs++ = MI_LOAD_REGISTER_IMM(2); | |
1750 | *cs++ = i915_mmio_reg_offset(RING_PP_DIR_DCLV(engine)); | |
1751 | *cs++ = PP_DIR_DCLV_2G; | |
1752 | *cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine)); | |
1753 | *cs++ = get_pd_offset(ppgtt); | |
1754 | *cs++ = MI_NOOP; | |
1755 | intel_ring_advance(req, cs); | |
48a10389 BW |
1756 | |
1757 | return 0; | |
1758 | } | |
1759 | ||
eeb9488e | 1760 | static int gen6_mm_switch(struct i915_hw_ppgtt *ppgtt, |
e85b26dc | 1761 | struct drm_i915_gem_request *req) |
eeb9488e | 1762 | { |
4a570db5 | 1763 | struct intel_engine_cs *engine = req->engine; |
8eb95204 | 1764 | struct drm_i915_private *dev_priv = req->i915; |
48a10389 | 1765 | |
e2f80391 TU |
1766 | I915_WRITE(RING_PP_DIR_DCLV(engine), PP_DIR_DCLV_2G); |
1767 | I915_WRITE(RING_PP_DIR_BASE(engine), get_pd_offset(ppgtt)); | |
eeb9488e BW |
1768 | return 0; |
1769 | } | |
1770 | ||
c6be607a | 1771 | static void gen8_ppgtt_enable(struct drm_i915_private *dev_priv) |
eeb9488e | 1772 | { |
e2f80391 | 1773 | struct intel_engine_cs *engine; |
3b3f1650 | 1774 | enum intel_engine_id id; |
3e302542 | 1775 | |
3b3f1650 | 1776 | for_each_engine(engine, dev_priv, id) { |
c6be607a TU |
1777 | u32 four_level = USES_FULL_48BIT_PPGTT(dev_priv) ? |
1778 | GEN8_GFX_PPGTT_48B : 0; | |
e2f80391 | 1779 | I915_WRITE(RING_MODE_GEN7(engine), |
2dba3239 | 1780 | _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE | four_level)); |
eeb9488e | 1781 | } |
eeb9488e | 1782 | } |
6197349b | 1783 | |
c6be607a | 1784 | static void gen7_ppgtt_enable(struct drm_i915_private *dev_priv) |
3e302542 | 1785 | { |
e2f80391 | 1786 | struct intel_engine_cs *engine; |
75c7b0b8 | 1787 | u32 ecochk, ecobits; |
3b3f1650 | 1788 | enum intel_engine_id id; |
6197349b | 1789 | |
b4a74e3a BW |
1790 | ecobits = I915_READ(GAC_ECO_BITS); |
1791 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B); | |
a65c2fcd | 1792 | |
b4a74e3a | 1793 | ecochk = I915_READ(GAM_ECOCHK); |
772c2a51 | 1794 | if (IS_HASWELL(dev_priv)) { |
b4a74e3a BW |
1795 | ecochk |= ECOCHK_PPGTT_WB_HSW; |
1796 | } else { | |
1797 | ecochk |= ECOCHK_PPGTT_LLC_IVB; | |
1798 | ecochk &= ~ECOCHK_PPGTT_GFDT_IVB; | |
1799 | } | |
1800 | I915_WRITE(GAM_ECOCHK, ecochk); | |
a65c2fcd | 1801 | |
3b3f1650 | 1802 | for_each_engine(engine, dev_priv, id) { |
6197349b | 1803 | /* GFX_MODE is per-ring on gen7+ */ |
e2f80391 | 1804 | I915_WRITE(RING_MODE_GEN7(engine), |
b4a74e3a | 1805 | _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); |
6197349b | 1806 | } |
b4a74e3a | 1807 | } |
6197349b | 1808 | |
c6be607a | 1809 | static void gen6_ppgtt_enable(struct drm_i915_private *dev_priv) |
b4a74e3a | 1810 | { |
75c7b0b8 | 1811 | u32 ecochk, gab_ctl, ecobits; |
a65c2fcd | 1812 | |
b4a74e3a BW |
1813 | ecobits = I915_READ(GAC_ECO_BITS); |
1814 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT | | |
1815 | ECOBITS_PPGTT_CACHE64B); | |
6197349b | 1816 | |
b4a74e3a BW |
1817 | gab_ctl = I915_READ(GAB_CTL); |
1818 | I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT); | |
1819 | ||
1820 | ecochk = I915_READ(GAM_ECOCHK); | |
1821 | I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B); | |
1822 | ||
1823 | I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
6197349b BW |
1824 | } |
1825 | ||
1d2a314c | 1826 | /* PPGTT support for Sandybdrige/Gen6 and later */ |
853ba5d2 | 1827 | static void gen6_ppgtt_clear_range(struct i915_address_space *vm, |
dd19674b | 1828 | u64 start, u64 length) |
1d2a314c | 1829 | { |
e5716f55 | 1830 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
dd19674b CW |
1831 | unsigned int first_entry = start >> PAGE_SHIFT; |
1832 | unsigned int pde = first_entry / GEN6_PTES; | |
1833 | unsigned int pte = first_entry % GEN6_PTES; | |
1834 | unsigned int num_entries = length >> PAGE_SHIFT; | |
1835 | gen6_pte_t scratch_pte = | |
1836 | vm->pte_encode(vm->scratch_page.daddr, I915_CACHE_LLC, 0); | |
1d2a314c | 1837 | |
7bddb01f | 1838 | while (num_entries) { |
dd19674b CW |
1839 | struct i915_page_table *pt = ppgtt->pd.page_table[pde++]; |
1840 | unsigned int end = min(pte + num_entries, GEN6_PTES); | |
1841 | gen6_pte_t *vaddr; | |
7bddb01f | 1842 | |
dd19674b | 1843 | num_entries -= end - pte; |
1d2a314c | 1844 | |
dd19674b CW |
1845 | /* Note that the hw doesn't support removing PDE on the fly |
1846 | * (they are cached inside the context with no means to | |
1847 | * invalidate the cache), so we can only reset the PTE | |
1848 | * entries back to scratch. | |
1849 | */ | |
1d2a314c | 1850 | |
dd19674b CW |
1851 | vaddr = kmap_atomic_px(pt); |
1852 | do { | |
1853 | vaddr[pte++] = scratch_pte; | |
1854 | } while (pte < end); | |
1855 | kunmap_atomic(vaddr); | |
1d2a314c | 1856 | |
dd19674b | 1857 | pte = 0; |
7bddb01f | 1858 | } |
1d2a314c DV |
1859 | } |
1860 | ||
853ba5d2 | 1861 | static void gen6_ppgtt_insert_entries(struct i915_address_space *vm, |
4a234c5f | 1862 | struct i915_vma *vma, |
75c7b0b8 CW |
1863 | enum i915_cache_level cache_level, |
1864 | u32 flags) | |
def886c3 | 1865 | { |
e5716f55 | 1866 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
4a234c5f | 1867 | unsigned first_entry = vma->node.start >> PAGE_SHIFT; |
07749ef3 MT |
1868 | unsigned act_pt = first_entry / GEN6_PTES; |
1869 | unsigned act_pte = first_entry % GEN6_PTES; | |
b31144c0 | 1870 | const u32 pte_encode = vm->pte_encode(0, cache_level, flags); |
423a8a94 | 1871 | struct sgt_dma iter = sgt_dma(vma); |
b31144c0 CW |
1872 | gen6_pte_t *vaddr; |
1873 | ||
9231da70 | 1874 | vaddr = kmap_atomic_px(ppgtt->pd.page_table[act_pt]); |
b31144c0 CW |
1875 | do { |
1876 | vaddr[act_pte] = pte_encode | GEN6_PTE_ADDR_ENCODE(iter.dma); | |
6e995e23 | 1877 | |
da1d95b6 | 1878 | iter.dma += I915_GTT_PAGE_SIZE; |
b31144c0 CW |
1879 | if (iter.dma == iter.max) { |
1880 | iter.sg = __sg_next(iter.sg); | |
1881 | if (!iter.sg) | |
1882 | break; | |
6e995e23 | 1883 | |
b31144c0 CW |
1884 | iter.dma = sg_dma_address(iter.sg); |
1885 | iter.max = iter.dma + iter.sg->length; | |
1886 | } | |
24f3a8cf | 1887 | |
07749ef3 | 1888 | if (++act_pte == GEN6_PTES) { |
9231da70 CW |
1889 | kunmap_atomic(vaddr); |
1890 | vaddr = kmap_atomic_px(ppgtt->pd.page_table[++act_pt]); | |
6e995e23 | 1891 | act_pte = 0; |
def886c3 | 1892 | } |
b31144c0 | 1893 | } while (1); |
9231da70 | 1894 | kunmap_atomic(vaddr); |
d9ec12f8 MA |
1895 | |
1896 | vma->page_sizes.gtt = I915_GTT_PAGE_SIZE; | |
def886c3 DV |
1897 | } |
1898 | ||
678d96fb | 1899 | static int gen6_alloc_va_range(struct i915_address_space *vm, |
dd19674b | 1900 | u64 start, u64 length) |
678d96fb | 1901 | { |
e5716f55 | 1902 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
ec565b3c | 1903 | struct i915_page_table *pt; |
dd19674b CW |
1904 | u64 from = start; |
1905 | unsigned int pde; | |
1906 | bool flush = false; | |
4933d519 | 1907 | |
731f74c5 | 1908 | gen6_for_each_pde(pt, &ppgtt->pd, start, length, pde) { |
dd19674b CW |
1909 | if (pt == vm->scratch_pt) { |
1910 | pt = alloc_pt(vm); | |
1911 | if (IS_ERR(pt)) | |
1912 | goto unwind_out; | |
4933d519 | 1913 | |
dd19674b CW |
1914 | gen6_initialize_pt(vm, pt); |
1915 | ppgtt->pd.page_table[pde] = pt; | |
1916 | gen6_write_pde(ppgtt, pde, pt); | |
1917 | flush = true; | |
4933d519 | 1918 | } |
4933d519 MT |
1919 | } |
1920 | ||
dd19674b CW |
1921 | if (flush) { |
1922 | mark_tlbs_dirty(ppgtt); | |
1923 | wmb(); | |
678d96fb BW |
1924 | } |
1925 | ||
1926 | return 0; | |
4933d519 MT |
1927 | |
1928 | unwind_out: | |
dd19674b CW |
1929 | gen6_ppgtt_clear_range(vm, from, start); |
1930 | return -ENOMEM; | |
678d96fb BW |
1931 | } |
1932 | ||
8776f02b MK |
1933 | static int gen6_init_scratch(struct i915_address_space *vm) |
1934 | { | |
8bcdd0f7 | 1935 | int ret; |
8776f02b | 1936 | |
8448661d | 1937 | ret = setup_scratch_page(vm, I915_GFP_DMA); |
8bcdd0f7 CW |
1938 | if (ret) |
1939 | return ret; | |
8776f02b | 1940 | |
8448661d | 1941 | vm->scratch_pt = alloc_pt(vm); |
8776f02b | 1942 | if (IS_ERR(vm->scratch_pt)) { |
8448661d | 1943 | cleanup_scratch_page(vm); |
8776f02b MK |
1944 | return PTR_ERR(vm->scratch_pt); |
1945 | } | |
1946 | ||
1947 | gen6_initialize_pt(vm, vm->scratch_pt); | |
1948 | ||
1949 | return 0; | |
1950 | } | |
1951 | ||
1952 | static void gen6_free_scratch(struct i915_address_space *vm) | |
1953 | { | |
8448661d CW |
1954 | free_pt(vm, vm->scratch_pt); |
1955 | cleanup_scratch_page(vm); | |
8776f02b MK |
1956 | } |
1957 | ||
061dd493 | 1958 | static void gen6_ppgtt_cleanup(struct i915_address_space *vm) |
a00d825d | 1959 | { |
e5716f55 | 1960 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
731f74c5 | 1961 | struct i915_page_directory *pd = &ppgtt->pd; |
09942c65 | 1962 | struct i915_page_table *pt; |
75c7b0b8 | 1963 | u32 pde; |
4933d519 | 1964 | |
061dd493 DV |
1965 | drm_mm_remove_node(&ppgtt->node); |
1966 | ||
731f74c5 | 1967 | gen6_for_all_pdes(pt, pd, pde) |
79ab9370 | 1968 | if (pt != vm->scratch_pt) |
8448661d | 1969 | free_pt(vm, pt); |
06fda602 | 1970 | |
8776f02b | 1971 | gen6_free_scratch(vm); |
3440d265 DV |
1972 | } |
1973 | ||
b146520f | 1974 | static int gen6_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt) |
3440d265 | 1975 | { |
8776f02b | 1976 | struct i915_address_space *vm = &ppgtt->base; |
49d73912 | 1977 | struct drm_i915_private *dev_priv = ppgtt->base.i915; |
72e96d64 | 1978 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
b146520f | 1979 | int ret; |
1d2a314c | 1980 | |
c8d4c0d6 BW |
1981 | /* PPGTT PDEs reside in the GGTT and consists of 512 entries. The |
1982 | * allocator works in address space sizes, so it's multiplied by page | |
1983 | * size. We allocate at the top of the GTT to avoid fragmentation. | |
1984 | */ | |
72e96d64 | 1985 | BUG_ON(!drm_mm_initialized(&ggtt->base.mm)); |
4933d519 | 1986 | |
8776f02b MK |
1987 | ret = gen6_init_scratch(vm); |
1988 | if (ret) | |
1989 | return ret; | |
4933d519 | 1990 | |
e007b19d CW |
1991 | ret = i915_gem_gtt_insert(&ggtt->base, &ppgtt->node, |
1992 | GEN6_PD_SIZE, GEN6_PD_ALIGN, | |
1993 | I915_COLOR_UNEVICTABLE, | |
1994 | 0, ggtt->base.total, | |
1995 | PIN_HIGH); | |
c8c26622 | 1996 | if (ret) |
678d96fb BW |
1997 | goto err_out; |
1998 | ||
72e96d64 | 1999 | if (ppgtt->node.start < ggtt->mappable_end) |
c8d4c0d6 | 2000 | DRM_DEBUG("Forced to use aperture for PDEs\n"); |
1d2a314c | 2001 | |
52c126ee | 2002 | ppgtt->pd.base.ggtt_offset = |
da1d95b6 | 2003 | ppgtt->node.start / I915_GTT_PAGE_SIZE * sizeof(gen6_pte_t); |
52c126ee CW |
2004 | |
2005 | ppgtt->pd_addr = (gen6_pte_t __iomem *)ggtt->gsm + | |
2006 | ppgtt->pd.base.ggtt_offset / sizeof(gen6_pte_t); | |
2007 | ||
c8c26622 | 2008 | return 0; |
678d96fb BW |
2009 | |
2010 | err_out: | |
8776f02b | 2011 | gen6_free_scratch(vm); |
678d96fb | 2012 | return ret; |
b146520f BW |
2013 | } |
2014 | ||
b146520f BW |
2015 | static int gen6_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt) |
2016 | { | |
2f2cf682 | 2017 | return gen6_ppgtt_allocate_page_directories(ppgtt); |
4933d519 | 2018 | } |
06dc68d6 | 2019 | |
4933d519 | 2020 | static void gen6_scratch_va_range(struct i915_hw_ppgtt *ppgtt, |
75c7b0b8 | 2021 | u64 start, u64 length) |
4933d519 | 2022 | { |
ec565b3c | 2023 | struct i915_page_table *unused; |
75c7b0b8 | 2024 | u32 pde; |
1d2a314c | 2025 | |
731f74c5 | 2026 | gen6_for_each_pde(unused, &ppgtt->pd, start, length, pde) |
79ab9370 | 2027 | ppgtt->pd.page_table[pde] = ppgtt->base.scratch_pt; |
b146520f BW |
2028 | } |
2029 | ||
5c5f6457 | 2030 | static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt) |
b146520f | 2031 | { |
49d73912 | 2032 | struct drm_i915_private *dev_priv = ppgtt->base.i915; |
72e96d64 | 2033 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
b146520f BW |
2034 | int ret; |
2035 | ||
72e96d64 | 2036 | ppgtt->base.pte_encode = ggtt->base.pte_encode; |
5db94019 | 2037 | if (intel_vgpu_active(dev_priv) || IS_GEN6(dev_priv)) |
b146520f | 2038 | ppgtt->switch_mm = gen6_mm_switch; |
772c2a51 | 2039 | else if (IS_HASWELL(dev_priv)) |
b146520f | 2040 | ppgtt->switch_mm = hsw_mm_switch; |
5db94019 | 2041 | else if (IS_GEN7(dev_priv)) |
b146520f | 2042 | ppgtt->switch_mm = gen7_mm_switch; |
8eb95204 | 2043 | else |
b146520f BW |
2044 | BUG(); |
2045 | ||
2046 | ret = gen6_ppgtt_alloc(ppgtt); | |
2047 | if (ret) | |
2048 | return ret; | |
2049 | ||
da1d95b6 | 2050 | ppgtt->base.total = I915_PDES * GEN6_PTES * I915_GTT_PAGE_SIZE; |
1d2a314c | 2051 | |
5c5f6457 | 2052 | gen6_scratch_va_range(ppgtt, 0, ppgtt->base.total); |
16a011c8 | 2053 | gen6_write_page_range(ppgtt, 0, ppgtt->base.total); |
678d96fb | 2054 | |
52c126ee CW |
2055 | ret = gen6_alloc_va_range(&ppgtt->base, 0, ppgtt->base.total); |
2056 | if (ret) { | |
2057 | gen6_ppgtt_cleanup(&ppgtt->base); | |
2058 | return ret; | |
2059 | } | |
2060 | ||
054b9acd MK |
2061 | ppgtt->base.clear_range = gen6_ppgtt_clear_range; |
2062 | ppgtt->base.insert_entries = gen6_ppgtt_insert_entries; | |
2063 | ppgtt->base.unbind_vma = ppgtt_unbind_vma; | |
2064 | ppgtt->base.bind_vma = ppgtt_bind_vma; | |
fa3f46af MA |
2065 | ppgtt->base.set_pages = ppgtt_set_pages; |
2066 | ppgtt->base.clear_pages = clear_pages; | |
054b9acd MK |
2067 | ppgtt->base.cleanup = gen6_ppgtt_cleanup; |
2068 | ppgtt->debug_dump = gen6_dump_ppgtt; | |
2069 | ||
440fd528 | 2070 | DRM_DEBUG_DRIVER("Allocated pde space (%lldM) at GTT entry: %llx\n", |
b146520f | 2071 | ppgtt->node.size >> 20, |
da1d95b6 | 2072 | ppgtt->node.start / I915_GTT_PAGE_SIZE); |
3440d265 | 2073 | |
52c126ee CW |
2074 | DRM_DEBUG_DRIVER("Adding PPGTT at offset %x\n", |
2075 | ppgtt->pd.base.ggtt_offset << 10); | |
fa76da34 | 2076 | |
b146520f | 2077 | return 0; |
3440d265 DV |
2078 | } |
2079 | ||
2bfa996e CW |
2080 | static int __hw_ppgtt_init(struct i915_hw_ppgtt *ppgtt, |
2081 | struct drm_i915_private *dev_priv) | |
3440d265 | 2082 | { |
49d73912 | 2083 | ppgtt->base.i915 = dev_priv; |
8448661d | 2084 | ppgtt->base.dma = &dev_priv->drm.pdev->dev; |
3440d265 | 2085 | |
2bfa996e | 2086 | if (INTEL_INFO(dev_priv)->gen < 8) |
5c5f6457 | 2087 | return gen6_ppgtt_init(ppgtt); |
3ed124b2 | 2088 | else |
d7b2633d | 2089 | return gen8_ppgtt_init(ppgtt); |
fa76da34 | 2090 | } |
c114f76a | 2091 | |
a2cad9df | 2092 | static void i915_address_space_init(struct i915_address_space *vm, |
80b204bc CW |
2093 | struct drm_i915_private *dev_priv, |
2094 | const char *name) | |
a2cad9df | 2095 | { |
80b204bc | 2096 | i915_gem_timeline_init(dev_priv, &vm->timeline, name); |
47db922f | 2097 | |
381b943b | 2098 | drm_mm_init(&vm->mm, 0, vm->total); |
47db922f CW |
2099 | vm->mm.head_node.color = I915_COLOR_UNEVICTABLE; |
2100 | ||
a2cad9df MW |
2101 | INIT_LIST_HEAD(&vm->active_list); |
2102 | INIT_LIST_HEAD(&vm->inactive_list); | |
50e046b6 | 2103 | INIT_LIST_HEAD(&vm->unbound_list); |
47db922f | 2104 | |
a2cad9df | 2105 | list_add_tail(&vm->global_link, &dev_priv->vm_list); |
86679820 | 2106 | pagevec_init(&vm->free_pages); |
a2cad9df MW |
2107 | } |
2108 | ||
ed9724dd MA |
2109 | static void i915_address_space_fini(struct i915_address_space *vm) |
2110 | { | |
8448661d | 2111 | if (pagevec_count(&vm->free_pages)) |
66df1014 | 2112 | vm_free_pages_release(vm, true); |
8448661d | 2113 | |
ed9724dd MA |
2114 | i915_gem_timeline_fini(&vm->timeline); |
2115 | drm_mm_takedown(&vm->mm); | |
2116 | list_del(&vm->global_link); | |
2117 | } | |
2118 | ||
c6be607a | 2119 | static void gtt_write_workarounds(struct drm_i915_private *dev_priv) |
d5165ebd | 2120 | { |
d5165ebd TG |
2121 | /* This function is for gtt related workarounds. This function is |
2122 | * called on driver load and after a GPU reset, so you can place | |
2123 | * workarounds here even if they get overwritten by GPU reset. | |
2124 | */ | |
90007bca | 2125 | /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk,cfl,cnl */ |
8652744b | 2126 | if (IS_BROADWELL(dev_priv)) |
d5165ebd | 2127 | I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW); |
920a14b2 | 2128 | else if (IS_CHERRYVIEW(dev_priv)) |
d5165ebd | 2129 | I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV); |
90007bca | 2130 | else if (IS_GEN9_BC(dev_priv) || IS_GEN10(dev_priv)) |
d5165ebd | 2131 | I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL); |
9fb5026f | 2132 | else if (IS_GEN9_LP(dev_priv)) |
d5165ebd | 2133 | I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT); |
9a6330cf MA |
2134 | |
2135 | /* | |
2136 | * To support 64K PTEs we need to first enable the use of the | |
2137 | * Intermediate-Page-Size(IPS) bit of the PDE field via some magical | |
2138 | * mmio, otherwise the page-walker will simply ignore the IPS bit. This | |
2139 | * shouldn't be needed after GEN10. | |
2140 | * | |
2141 | * 64K pages were first introduced from BDW+, although technically they | |
2142 | * only *work* from gen9+. For pre-BDW we instead have the option for | |
2143 | * 32K pages, but we don't currently have any support for it in our | |
2144 | * driver. | |
2145 | */ | |
2146 | if (HAS_PAGE_SIZES(dev_priv, I915_GTT_PAGE_SIZE_64K) && | |
2147 | INTEL_GEN(dev_priv) <= 10) | |
2148 | I915_WRITE(GEN8_GAMW_ECO_DEV_RW_IA, | |
2149 | I915_READ(GEN8_GAMW_ECO_DEV_RW_IA) | | |
2150 | GAMW_ECO_ENABLE_64K_IPS_FIELD); | |
d5165ebd TG |
2151 | } |
2152 | ||
c6be607a | 2153 | int i915_ppgtt_init_hw(struct drm_i915_private *dev_priv) |
82460d97 | 2154 | { |
c6be607a | 2155 | gtt_write_workarounds(dev_priv); |
d5165ebd | 2156 | |
671b5013 TD |
2157 | /* In the case of execlists, PPGTT is enabled by the context descriptor |
2158 | * and the PDPs are contained within the context itself. We don't | |
2159 | * need to do anything here. */ | |
4f044a88 | 2160 | if (i915_modparams.enable_execlists) |
671b5013 TD |
2161 | return 0; |
2162 | ||
c6be607a | 2163 | if (!USES_PPGTT(dev_priv)) |
82460d97 DV |
2164 | return 0; |
2165 | ||
5db94019 | 2166 | if (IS_GEN6(dev_priv)) |
c6be607a | 2167 | gen6_ppgtt_enable(dev_priv); |
5db94019 | 2168 | else if (IS_GEN7(dev_priv)) |
c6be607a TU |
2169 | gen7_ppgtt_enable(dev_priv); |
2170 | else if (INTEL_GEN(dev_priv) >= 8) | |
2171 | gen8_ppgtt_enable(dev_priv); | |
82460d97 | 2172 | else |
c6be607a | 2173 | MISSING_CASE(INTEL_GEN(dev_priv)); |
82460d97 | 2174 | |
4ad2fd88 JH |
2175 | return 0; |
2176 | } | |
1d2a314c | 2177 | |
4d884705 | 2178 | struct i915_hw_ppgtt * |
2bfa996e | 2179 | i915_ppgtt_create(struct drm_i915_private *dev_priv, |
80b204bc CW |
2180 | struct drm_i915_file_private *fpriv, |
2181 | const char *name) | |
4d884705 DV |
2182 | { |
2183 | struct i915_hw_ppgtt *ppgtt; | |
2184 | int ret; | |
2185 | ||
2186 | ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL); | |
2187 | if (!ppgtt) | |
2188 | return ERR_PTR(-ENOMEM); | |
2189 | ||
1188bc66 | 2190 | ret = __hw_ppgtt_init(ppgtt, dev_priv); |
4d884705 DV |
2191 | if (ret) { |
2192 | kfree(ppgtt); | |
2193 | return ERR_PTR(ret); | |
2194 | } | |
2195 | ||
1188bc66 CW |
2196 | kref_init(&ppgtt->ref); |
2197 | i915_address_space_init(&ppgtt->base, dev_priv, name); | |
2198 | ppgtt->base.file = fpriv; | |
2199 | ||
198c974d DCS |
2200 | trace_i915_ppgtt_create(&ppgtt->base); |
2201 | ||
4d884705 DV |
2202 | return ppgtt; |
2203 | } | |
2204 | ||
0c7eeda1 CW |
2205 | void i915_ppgtt_close(struct i915_address_space *vm) |
2206 | { | |
2207 | struct list_head *phases[] = { | |
2208 | &vm->active_list, | |
2209 | &vm->inactive_list, | |
2210 | &vm->unbound_list, | |
2211 | NULL, | |
2212 | }, **phase; | |
2213 | ||
2214 | GEM_BUG_ON(vm->closed); | |
2215 | vm->closed = true; | |
2216 | ||
2217 | for (phase = phases; *phase; phase++) { | |
2218 | struct i915_vma *vma, *vn; | |
2219 | ||
2220 | list_for_each_entry_safe(vma, vn, *phase, vm_link) | |
2221 | if (!i915_vma_is_closed(vma)) | |
2222 | i915_vma_close(vma); | |
2223 | } | |
2224 | } | |
2225 | ||
ed9724dd | 2226 | void i915_ppgtt_release(struct kref *kref) |
ee960be7 DV |
2227 | { |
2228 | struct i915_hw_ppgtt *ppgtt = | |
2229 | container_of(kref, struct i915_hw_ppgtt, ref); | |
2230 | ||
198c974d DCS |
2231 | trace_i915_ppgtt_release(&ppgtt->base); |
2232 | ||
50e046b6 | 2233 | /* vmas should already be unbound and destroyed */ |
ee960be7 DV |
2234 | WARN_ON(!list_empty(&ppgtt->base.active_list)); |
2235 | WARN_ON(!list_empty(&ppgtt->base.inactive_list)); | |
50e046b6 | 2236 | WARN_ON(!list_empty(&ppgtt->base.unbound_list)); |
ee960be7 DV |
2237 | |
2238 | ppgtt->base.cleanup(&ppgtt->base); | |
8448661d | 2239 | i915_address_space_fini(&ppgtt->base); |
ee960be7 DV |
2240 | kfree(ppgtt); |
2241 | } | |
1d2a314c | 2242 | |
a81cc00c BW |
2243 | /* Certain Gen5 chipsets require require idling the GPU before |
2244 | * unmapping anything from the GTT when VT-d is enabled. | |
2245 | */ | |
97d6d7ab | 2246 | static bool needs_idle_maps(struct drm_i915_private *dev_priv) |
a81cc00c | 2247 | { |
a81cc00c BW |
2248 | /* Query intel_iommu to see if we need the workaround. Presumably that |
2249 | * was loaded first. | |
2250 | */ | |
80debff8 | 2251 | return IS_GEN5(dev_priv) && IS_MOBILE(dev_priv) && intel_vtd_active(); |
a81cc00c BW |
2252 | } |
2253 | ||
dc97997a | 2254 | void i915_check_and_clear_faults(struct drm_i915_private *dev_priv) |
828c7908 | 2255 | { |
e2f80391 | 2256 | struct intel_engine_cs *engine; |
3b3f1650 | 2257 | enum intel_engine_id id; |
828c7908 | 2258 | |
dc97997a | 2259 | if (INTEL_INFO(dev_priv)->gen < 6) |
828c7908 BW |
2260 | return; |
2261 | ||
3b3f1650 | 2262 | for_each_engine(engine, dev_priv, id) { |
828c7908 | 2263 | u32 fault_reg; |
e2f80391 | 2264 | fault_reg = I915_READ(RING_FAULT_REG(engine)); |
828c7908 BW |
2265 | if (fault_reg & RING_FAULT_VALID) { |
2266 | DRM_DEBUG_DRIVER("Unexpected fault\n" | |
59a5d290 | 2267 | "\tAddr: 0x%08lx\n" |
828c7908 BW |
2268 | "\tAddress space: %s\n" |
2269 | "\tSource ID: %d\n" | |
2270 | "\tType: %d\n", | |
2271 | fault_reg & PAGE_MASK, | |
2272 | fault_reg & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT", | |
2273 | RING_FAULT_SRCID(fault_reg), | |
2274 | RING_FAULT_FAULT_TYPE(fault_reg)); | |
e2f80391 | 2275 | I915_WRITE(RING_FAULT_REG(engine), |
828c7908 BW |
2276 | fault_reg & ~RING_FAULT_VALID); |
2277 | } | |
2278 | } | |
3b3f1650 AG |
2279 | |
2280 | /* Engine specific init may not have been done till this point. */ | |
2281 | if (dev_priv->engine[RCS]) | |
2282 | POSTING_READ(RING_FAULT_REG(dev_priv->engine[RCS])); | |
828c7908 BW |
2283 | } |
2284 | ||
275a991c | 2285 | void i915_gem_suspend_gtt_mappings(struct drm_i915_private *dev_priv) |
828c7908 | 2286 | { |
72e96d64 | 2287 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
828c7908 BW |
2288 | |
2289 | /* Don't bother messing with faults pre GEN6 as we have little | |
2290 | * documentation supporting that it's a good idea. | |
2291 | */ | |
275a991c | 2292 | if (INTEL_GEN(dev_priv) < 6) |
828c7908 BW |
2293 | return; |
2294 | ||
dc97997a | 2295 | i915_check_and_clear_faults(dev_priv); |
828c7908 | 2296 | |
381b943b | 2297 | ggtt->base.clear_range(&ggtt->base, 0, ggtt->base.total); |
91e56499 | 2298 | |
7c3f86b6 | 2299 | i915_ggtt_invalidate(dev_priv); |
828c7908 BW |
2300 | } |
2301 | ||
03ac84f1 CW |
2302 | int i915_gem_gtt_prepare_pages(struct drm_i915_gem_object *obj, |
2303 | struct sg_table *pages) | |
7c2e6fdf | 2304 | { |
1a292fa5 CW |
2305 | do { |
2306 | if (dma_map_sg(&obj->base.dev->pdev->dev, | |
2307 | pages->sgl, pages->nents, | |
2308 | PCI_DMA_BIDIRECTIONAL)) | |
2309 | return 0; | |
2310 | ||
2311 | /* If the DMA remap fails, one cause can be that we have | |
2312 | * too many objects pinned in a small remapping table, | |
2313 | * such as swiotlb. Incrementally purge all other objects and | |
2314 | * try again - if there are no more pages to remove from | |
2315 | * the DMA remapper, i915_gem_shrink will return 0. | |
2316 | */ | |
2317 | GEM_BUG_ON(obj->mm.pages == pages); | |
2318 | } while (i915_gem_shrink(to_i915(obj->base.dev), | |
912d572d | 2319 | obj->base.size >> PAGE_SHIFT, NULL, |
1a292fa5 CW |
2320 | I915_SHRINK_BOUND | |
2321 | I915_SHRINK_UNBOUND | | |
2322 | I915_SHRINK_ACTIVE)); | |
9da3da66 | 2323 | |
03ac84f1 | 2324 | return -ENOSPC; |
7c2e6fdf DV |
2325 | } |
2326 | ||
2c642b07 | 2327 | static void gen8_set_pte(void __iomem *addr, gen8_pte_t pte) |
94ec8f61 | 2328 | { |
94ec8f61 | 2329 | writeq(pte, addr); |
94ec8f61 BW |
2330 | } |
2331 | ||
d6473f56 CW |
2332 | static void gen8_ggtt_insert_page(struct i915_address_space *vm, |
2333 | dma_addr_t addr, | |
75c7b0b8 | 2334 | u64 offset, |
d6473f56 CW |
2335 | enum i915_cache_level level, |
2336 | u32 unused) | |
2337 | { | |
7c3f86b6 | 2338 | struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm); |
d6473f56 | 2339 | gen8_pte_t __iomem *pte = |
7c3f86b6 | 2340 | (gen8_pte_t __iomem *)ggtt->gsm + (offset >> PAGE_SHIFT); |
d6473f56 | 2341 | |
b512e960 | 2342 | gen8_set_pte(pte, gen8_pte_encode(addr, level, 0)); |
d6473f56 | 2343 | |
7c3f86b6 | 2344 | ggtt->invalidate(vm->i915); |
d6473f56 CW |
2345 | } |
2346 | ||
94ec8f61 | 2347 | static void gen8_ggtt_insert_entries(struct i915_address_space *vm, |
4a234c5f | 2348 | struct i915_vma *vma, |
75c7b0b8 CW |
2349 | enum i915_cache_level level, |
2350 | u32 unused) | |
94ec8f61 | 2351 | { |
ce7fda2e | 2352 | struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm); |
85d1225e DG |
2353 | struct sgt_iter sgt_iter; |
2354 | gen8_pte_t __iomem *gtt_entries; | |
b512e960 | 2355 | const gen8_pte_t pte_encode = gen8_pte_encode(0, level, 0); |
85d1225e | 2356 | dma_addr_t addr; |
be69459a | 2357 | |
894ccebe | 2358 | gtt_entries = (gen8_pte_t __iomem *)ggtt->gsm; |
4a234c5f MA |
2359 | gtt_entries += vma->node.start >> PAGE_SHIFT; |
2360 | for_each_sgt_dma(addr, sgt_iter, vma->pages) | |
894ccebe | 2361 | gen8_set_pte(gtt_entries++, pte_encode | addr); |
85d1225e | 2362 | |
894ccebe | 2363 | wmb(); |
94ec8f61 | 2364 | |
94ec8f61 BW |
2365 | /* This next bit makes the above posting read even more important. We |
2366 | * want to flush the TLBs only after we're certain all the PTE updates | |
2367 | * have finished. | |
2368 | */ | |
7c3f86b6 | 2369 | ggtt->invalidate(vm->i915); |
94ec8f61 BW |
2370 | } |
2371 | ||
d6473f56 CW |
2372 | static void gen6_ggtt_insert_page(struct i915_address_space *vm, |
2373 | dma_addr_t addr, | |
75c7b0b8 | 2374 | u64 offset, |
d6473f56 CW |
2375 | enum i915_cache_level level, |
2376 | u32 flags) | |
2377 | { | |
7c3f86b6 | 2378 | struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm); |
d6473f56 | 2379 | gen6_pte_t __iomem *pte = |
7c3f86b6 | 2380 | (gen6_pte_t __iomem *)ggtt->gsm + (offset >> PAGE_SHIFT); |
d6473f56 | 2381 | |
4fb84d99 | 2382 | iowrite32(vm->pte_encode(addr, level, flags), pte); |
d6473f56 | 2383 | |
7c3f86b6 | 2384 | ggtt->invalidate(vm->i915); |
d6473f56 CW |
2385 | } |
2386 | ||
e76e9aeb BW |
2387 | /* |
2388 | * Binds an object into the global gtt with the specified cache level. The object | |
2389 | * will be accessible to the GPU via commands whose operands reference offsets | |
2390 | * within the global GTT as well as accessible by the GPU through the GMADR | |
2391 | * mapped BAR (dev_priv->mm.gtt->gtt). | |
2392 | */ | |
853ba5d2 | 2393 | static void gen6_ggtt_insert_entries(struct i915_address_space *vm, |
4a234c5f | 2394 | struct i915_vma *vma, |
75c7b0b8 CW |
2395 | enum i915_cache_level level, |
2396 | u32 flags) | |
e76e9aeb | 2397 | { |
ce7fda2e | 2398 | struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm); |
b31144c0 | 2399 | gen6_pte_t __iomem *entries = (gen6_pte_t __iomem *)ggtt->gsm; |
4a234c5f | 2400 | unsigned int i = vma->node.start >> PAGE_SHIFT; |
b31144c0 | 2401 | struct sgt_iter iter; |
85d1225e | 2402 | dma_addr_t addr; |
4a234c5f | 2403 | for_each_sgt_dma(addr, iter, vma->pages) |
b31144c0 CW |
2404 | iowrite32(vm->pte_encode(addr, level, flags), &entries[i++]); |
2405 | wmb(); | |
0f9b91c7 BW |
2406 | |
2407 | /* This next bit makes the above posting read even more important. We | |
2408 | * want to flush the TLBs only after we're certain all the PTE updates | |
2409 | * have finished. | |
2410 | */ | |
7c3f86b6 | 2411 | ggtt->invalidate(vm->i915); |
e76e9aeb BW |
2412 | } |
2413 | ||
f7770bfd | 2414 | static void nop_clear_range(struct i915_address_space *vm, |
75c7b0b8 | 2415 | u64 start, u64 length) |
f7770bfd CW |
2416 | { |
2417 | } | |
2418 | ||
94ec8f61 | 2419 | static void gen8_ggtt_clear_range(struct i915_address_space *vm, |
75c7b0b8 | 2420 | u64 start, u64 length) |
94ec8f61 | 2421 | { |
ce7fda2e | 2422 | struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm); |
782f1495 BW |
2423 | unsigned first_entry = start >> PAGE_SHIFT; |
2424 | unsigned num_entries = length >> PAGE_SHIFT; | |
894ccebe | 2425 | const gen8_pte_t scratch_pte = |
b512e960 | 2426 | gen8_pte_encode(vm->scratch_page.daddr, I915_CACHE_LLC, 0); |
894ccebe | 2427 | gen8_pte_t __iomem *gtt_base = |
72e96d64 JL |
2428 | (gen8_pte_t __iomem *)ggtt->gsm + first_entry; |
2429 | const int max_entries = ggtt_total_entries(ggtt) - first_entry; | |
94ec8f61 BW |
2430 | int i; |
2431 | ||
2432 | if (WARN(num_entries > max_entries, | |
2433 | "First entry = %d; Num entries = %d (max=%d)\n", | |
2434 | first_entry, num_entries, max_entries)) | |
2435 | num_entries = max_entries; | |
2436 | ||
94ec8f61 BW |
2437 | for (i = 0; i < num_entries; i++) |
2438 | gen8_set_pte(>t_base[i], scratch_pte); | |
94ec8f61 BW |
2439 | } |
2440 | ||
0ef34ad6 JB |
2441 | static void bxt_vtd_ggtt_wa(struct i915_address_space *vm) |
2442 | { | |
2443 | struct drm_i915_private *dev_priv = vm->i915; | |
2444 | ||
2445 | /* | |
2446 | * Make sure the internal GAM fifo has been cleared of all GTT | |
2447 | * writes before exiting stop_machine(). This guarantees that | |
2448 | * any aperture accesses waiting to start in another process | |
2449 | * cannot back up behind the GTT writes causing a hang. | |
2450 | * The register can be any arbitrary GAM register. | |
2451 | */ | |
2452 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
2453 | } | |
2454 | ||
2455 | struct insert_page { | |
2456 | struct i915_address_space *vm; | |
2457 | dma_addr_t addr; | |
2458 | u64 offset; | |
2459 | enum i915_cache_level level; | |
2460 | }; | |
2461 | ||
2462 | static int bxt_vtd_ggtt_insert_page__cb(void *_arg) | |
2463 | { | |
2464 | struct insert_page *arg = _arg; | |
2465 | ||
2466 | gen8_ggtt_insert_page(arg->vm, arg->addr, arg->offset, arg->level, 0); | |
2467 | bxt_vtd_ggtt_wa(arg->vm); | |
2468 | ||
2469 | return 0; | |
2470 | } | |
2471 | ||
2472 | static void bxt_vtd_ggtt_insert_page__BKL(struct i915_address_space *vm, | |
2473 | dma_addr_t addr, | |
2474 | u64 offset, | |
2475 | enum i915_cache_level level, | |
2476 | u32 unused) | |
2477 | { | |
2478 | struct insert_page arg = { vm, addr, offset, level }; | |
2479 | ||
2480 | stop_machine(bxt_vtd_ggtt_insert_page__cb, &arg, NULL); | |
2481 | } | |
2482 | ||
2483 | struct insert_entries { | |
2484 | struct i915_address_space *vm; | |
4a234c5f | 2485 | struct i915_vma *vma; |
0ef34ad6 JB |
2486 | enum i915_cache_level level; |
2487 | }; | |
2488 | ||
2489 | static int bxt_vtd_ggtt_insert_entries__cb(void *_arg) | |
2490 | { | |
2491 | struct insert_entries *arg = _arg; | |
2492 | ||
4a234c5f | 2493 | gen8_ggtt_insert_entries(arg->vm, arg->vma, arg->level, 0); |
0ef34ad6 JB |
2494 | bxt_vtd_ggtt_wa(arg->vm); |
2495 | ||
2496 | return 0; | |
2497 | } | |
2498 | ||
2499 | static void bxt_vtd_ggtt_insert_entries__BKL(struct i915_address_space *vm, | |
4a234c5f | 2500 | struct i915_vma *vma, |
0ef34ad6 JB |
2501 | enum i915_cache_level level, |
2502 | u32 unused) | |
2503 | { | |
17369ba0 | 2504 | struct insert_entries arg = { vm, vma, level }; |
0ef34ad6 JB |
2505 | |
2506 | stop_machine(bxt_vtd_ggtt_insert_entries__cb, &arg, NULL); | |
2507 | } | |
2508 | ||
2509 | struct clear_range { | |
2510 | struct i915_address_space *vm; | |
2511 | u64 start; | |
2512 | u64 length; | |
2513 | }; | |
2514 | ||
2515 | static int bxt_vtd_ggtt_clear_range__cb(void *_arg) | |
2516 | { | |
2517 | struct clear_range *arg = _arg; | |
2518 | ||
2519 | gen8_ggtt_clear_range(arg->vm, arg->start, arg->length); | |
2520 | bxt_vtd_ggtt_wa(arg->vm); | |
2521 | ||
2522 | return 0; | |
2523 | } | |
2524 | ||
2525 | static void bxt_vtd_ggtt_clear_range__BKL(struct i915_address_space *vm, | |
2526 | u64 start, | |
2527 | u64 length) | |
2528 | { | |
2529 | struct clear_range arg = { vm, start, length }; | |
2530 | ||
2531 | stop_machine(bxt_vtd_ggtt_clear_range__cb, &arg, NULL); | |
2532 | } | |
2533 | ||
853ba5d2 | 2534 | static void gen6_ggtt_clear_range(struct i915_address_space *vm, |
75c7b0b8 | 2535 | u64 start, u64 length) |
7faf1ab2 | 2536 | { |
ce7fda2e | 2537 | struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm); |
782f1495 BW |
2538 | unsigned first_entry = start >> PAGE_SHIFT; |
2539 | unsigned num_entries = length >> PAGE_SHIFT; | |
07749ef3 | 2540 | gen6_pte_t scratch_pte, __iomem *gtt_base = |
72e96d64 JL |
2541 | (gen6_pte_t __iomem *)ggtt->gsm + first_entry; |
2542 | const int max_entries = ggtt_total_entries(ggtt) - first_entry; | |
7faf1ab2 DV |
2543 | int i; |
2544 | ||
2545 | if (WARN(num_entries > max_entries, | |
2546 | "First entry = %d; Num entries = %d (max=%d)\n", | |
2547 | first_entry, num_entries, max_entries)) | |
2548 | num_entries = max_entries; | |
2549 | ||
8bcdd0f7 | 2550 | scratch_pte = vm->pte_encode(vm->scratch_page.daddr, |
4fb84d99 | 2551 | I915_CACHE_LLC, 0); |
828c7908 | 2552 | |
7faf1ab2 DV |
2553 | for (i = 0; i < num_entries; i++) |
2554 | iowrite32(scratch_pte, >t_base[i]); | |
7faf1ab2 DV |
2555 | } |
2556 | ||
d6473f56 CW |
2557 | static void i915_ggtt_insert_page(struct i915_address_space *vm, |
2558 | dma_addr_t addr, | |
75c7b0b8 | 2559 | u64 offset, |
d6473f56 CW |
2560 | enum i915_cache_level cache_level, |
2561 | u32 unused) | |
2562 | { | |
d6473f56 CW |
2563 | unsigned int flags = (cache_level == I915_CACHE_NONE) ? |
2564 | AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY; | |
d6473f56 CW |
2565 | |
2566 | intel_gtt_insert_page(addr, offset >> PAGE_SHIFT, flags); | |
d6473f56 CW |
2567 | } |
2568 | ||
d369d2d9 | 2569 | static void i915_ggtt_insert_entries(struct i915_address_space *vm, |
4a234c5f | 2570 | struct i915_vma *vma, |
75c7b0b8 CW |
2571 | enum i915_cache_level cache_level, |
2572 | u32 unused) | |
7faf1ab2 DV |
2573 | { |
2574 | unsigned int flags = (cache_level == I915_CACHE_NONE) ? | |
2575 | AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY; | |
2576 | ||
4a234c5f MA |
2577 | intel_gtt_insert_sg_entries(vma->pages, vma->node.start >> PAGE_SHIFT, |
2578 | flags); | |
7faf1ab2 DV |
2579 | } |
2580 | ||
853ba5d2 | 2581 | static void i915_ggtt_clear_range(struct i915_address_space *vm, |
75c7b0b8 | 2582 | u64 start, u64 length) |
7faf1ab2 | 2583 | { |
2eedfc7d | 2584 | intel_gtt_clear_range(start >> PAGE_SHIFT, length >> PAGE_SHIFT); |
7faf1ab2 DV |
2585 | } |
2586 | ||
70b9f6f8 DV |
2587 | static int ggtt_bind_vma(struct i915_vma *vma, |
2588 | enum i915_cache_level cache_level, | |
2589 | u32 flags) | |
0a878716 | 2590 | { |
49d73912 | 2591 | struct drm_i915_private *i915 = vma->vm->i915; |
0a878716 | 2592 | struct drm_i915_gem_object *obj = vma->obj; |
ba7a5741 | 2593 | u32 pte_flags; |
0a878716 | 2594 | |
0a878716 | 2595 | /* Currently applicable only to VLV */ |
ba7a5741 | 2596 | pte_flags = 0; |
0a878716 DV |
2597 | if (obj->gt_ro) |
2598 | pte_flags |= PTE_READ_ONLY; | |
2599 | ||
9c870d03 | 2600 | intel_runtime_pm_get(i915); |
4a234c5f | 2601 | vma->vm->insert_entries(vma->vm, vma, cache_level, pte_flags); |
9c870d03 | 2602 | intel_runtime_pm_put(i915); |
0a878716 | 2603 | |
d9ec12f8 MA |
2604 | vma->page_sizes.gtt = I915_GTT_PAGE_SIZE; |
2605 | ||
0a878716 DV |
2606 | /* |
2607 | * Without aliasing PPGTT there's no difference between | |
2608 | * GLOBAL/LOCAL_BIND, it's all the same ptes. Hence unconditionally | |
2609 | * upgrade to both bound if we bind either to avoid double-binding. | |
2610 | */ | |
3272db53 | 2611 | vma->flags |= I915_VMA_GLOBAL_BIND | I915_VMA_LOCAL_BIND; |
0a878716 DV |
2612 | |
2613 | return 0; | |
2614 | } | |
2615 | ||
cbc4e9e6 CW |
2616 | static void ggtt_unbind_vma(struct i915_vma *vma) |
2617 | { | |
2618 | struct drm_i915_private *i915 = vma->vm->i915; | |
2619 | ||
2620 | intel_runtime_pm_get(i915); | |
2621 | vma->vm->clear_range(vma->vm, vma->node.start, vma->size); | |
2622 | intel_runtime_pm_put(i915); | |
2623 | } | |
2624 | ||
0a878716 DV |
2625 | static int aliasing_gtt_bind_vma(struct i915_vma *vma, |
2626 | enum i915_cache_level cache_level, | |
2627 | u32 flags) | |
d5bd1449 | 2628 | { |
49d73912 | 2629 | struct drm_i915_private *i915 = vma->vm->i915; |
321d178e | 2630 | u32 pte_flags; |
ff685975 | 2631 | int ret; |
70b9f6f8 | 2632 | |
24f3a8cf | 2633 | /* Currently applicable only to VLV */ |
321d178e CW |
2634 | pte_flags = 0; |
2635 | if (vma->obj->gt_ro) | |
f329f5f6 | 2636 | pte_flags |= PTE_READ_ONLY; |
24f3a8cf | 2637 | |
ff685975 CW |
2638 | if (flags & I915_VMA_LOCAL_BIND) { |
2639 | struct i915_hw_ppgtt *appgtt = i915->mm.aliasing_ppgtt; | |
2640 | ||
1f23475c MA |
2641 | if (!(vma->flags & I915_VMA_LOCAL_BIND) && |
2642 | appgtt->base.allocate_va_range) { | |
ff685975 CW |
2643 | ret = appgtt->base.allocate_va_range(&appgtt->base, |
2644 | vma->node.start, | |
d567232c | 2645 | vma->size); |
ff685975 | 2646 | if (ret) |
fa3f46af | 2647 | return ret; |
ff685975 CW |
2648 | } |
2649 | ||
4a234c5f MA |
2650 | appgtt->base.insert_entries(&appgtt->base, vma, cache_level, |
2651 | pte_flags); | |
ff685975 CW |
2652 | } |
2653 | ||
3272db53 | 2654 | if (flags & I915_VMA_GLOBAL_BIND) { |
9c870d03 | 2655 | intel_runtime_pm_get(i915); |
4a234c5f | 2656 | vma->vm->insert_entries(vma->vm, vma, cache_level, pte_flags); |
9c870d03 | 2657 | intel_runtime_pm_put(i915); |
6f65e29a | 2658 | } |
d5bd1449 | 2659 | |
70b9f6f8 | 2660 | return 0; |
d5bd1449 CW |
2661 | } |
2662 | ||
cbc4e9e6 | 2663 | static void aliasing_gtt_unbind_vma(struct i915_vma *vma) |
74163907 | 2664 | { |
49d73912 | 2665 | struct drm_i915_private *i915 = vma->vm->i915; |
6f65e29a | 2666 | |
9c870d03 CW |
2667 | if (vma->flags & I915_VMA_GLOBAL_BIND) { |
2668 | intel_runtime_pm_get(i915); | |
cbc4e9e6 | 2669 | vma->vm->clear_range(vma->vm, vma->node.start, vma->size); |
9c870d03 CW |
2670 | intel_runtime_pm_put(i915); |
2671 | } | |
06615ee5 | 2672 | |
cbc4e9e6 CW |
2673 | if (vma->flags & I915_VMA_LOCAL_BIND) { |
2674 | struct i915_address_space *vm = &i915->mm.aliasing_ppgtt->base; | |
2675 | ||
2676 | vm->clear_range(vm, vma->node.start, vma->size); | |
2677 | } | |
74163907 DV |
2678 | } |
2679 | ||
03ac84f1 CW |
2680 | void i915_gem_gtt_finish_pages(struct drm_i915_gem_object *obj, |
2681 | struct sg_table *pages) | |
7c2e6fdf | 2682 | { |
52a05c30 DW |
2683 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
2684 | struct device *kdev = &dev_priv->drm.pdev->dev; | |
307dc25b | 2685 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
5c042287 | 2686 | |
307dc25b | 2687 | if (unlikely(ggtt->do_idle_maps)) { |
228ec87c | 2688 | if (i915_gem_wait_for_idle(dev_priv, 0)) { |
307dc25b CW |
2689 | DRM_ERROR("Failed to wait for idle; VT'd may hang.\n"); |
2690 | /* Wait a bit, in hopes it avoids the hang */ | |
2691 | udelay(10); | |
2692 | } | |
2693 | } | |
5c042287 | 2694 | |
03ac84f1 | 2695 | dma_unmap_sg(kdev, pages->sgl, pages->nents, PCI_DMA_BIDIRECTIONAL); |
7c2e6fdf | 2696 | } |
644ec02b | 2697 | |
fa3f46af MA |
2698 | static int ggtt_set_pages(struct i915_vma *vma) |
2699 | { | |
2700 | int ret; | |
2701 | ||
2702 | GEM_BUG_ON(vma->pages); | |
2703 | ||
2704 | ret = i915_get_ggtt_vma_pages(vma); | |
2705 | if (ret) | |
2706 | return ret; | |
2707 | ||
7464284b MA |
2708 | vma->page_sizes = vma->obj->mm.page_sizes; |
2709 | ||
fa3f46af MA |
2710 | return 0; |
2711 | } | |
2712 | ||
45b186f1 | 2713 | static void i915_gtt_color_adjust(const struct drm_mm_node *node, |
42d6ab48 | 2714 | unsigned long color, |
440fd528 TR |
2715 | u64 *start, |
2716 | u64 *end) | |
42d6ab48 | 2717 | { |
a6508ded | 2718 | if (node->allocated && node->color != color) |
f51455d4 | 2719 | *start += I915_GTT_PAGE_SIZE; |
42d6ab48 | 2720 | |
a6508ded CW |
2721 | /* Also leave a space between the unallocated reserved node after the |
2722 | * GTT and any objects within the GTT, i.e. we use the color adjustment | |
2723 | * to insert a guard page to prevent prefetches crossing over the | |
2724 | * GTT boundary. | |
2725 | */ | |
b44f97fd | 2726 | node = list_next_entry(node, node_list); |
a6508ded | 2727 | if (node->color != color) |
f51455d4 | 2728 | *end -= I915_GTT_PAGE_SIZE; |
42d6ab48 | 2729 | } |
fbe5d36e | 2730 | |
6cde9a02 CW |
2731 | int i915_gem_init_aliasing_ppgtt(struct drm_i915_private *i915) |
2732 | { | |
2733 | struct i915_ggtt *ggtt = &i915->ggtt; | |
2734 | struct i915_hw_ppgtt *ppgtt; | |
2735 | int err; | |
2736 | ||
57202f47 | 2737 | ppgtt = i915_ppgtt_create(i915, ERR_PTR(-EPERM), "[alias]"); |
1188bc66 CW |
2738 | if (IS_ERR(ppgtt)) |
2739 | return PTR_ERR(ppgtt); | |
6cde9a02 | 2740 | |
e565ceb0 CW |
2741 | if (WARN_ON(ppgtt->base.total < ggtt->base.total)) { |
2742 | err = -ENODEV; | |
2743 | goto err_ppgtt; | |
2744 | } | |
2745 | ||
6cde9a02 | 2746 | if (ppgtt->base.allocate_va_range) { |
e565ceb0 CW |
2747 | /* Note we only pre-allocate as far as the end of the global |
2748 | * GTT. On 48b / 4-level page-tables, the difference is very, | |
2749 | * very significant! We have to preallocate as GVT/vgpu does | |
2750 | * not like the page directory disappearing. | |
2751 | */ | |
6cde9a02 | 2752 | err = ppgtt->base.allocate_va_range(&ppgtt->base, |
e565ceb0 | 2753 | 0, ggtt->base.total); |
6cde9a02 | 2754 | if (err) |
1188bc66 | 2755 | goto err_ppgtt; |
6cde9a02 CW |
2756 | } |
2757 | ||
6cde9a02 | 2758 | i915->mm.aliasing_ppgtt = ppgtt; |
cbc4e9e6 | 2759 | |
6cde9a02 CW |
2760 | WARN_ON(ggtt->base.bind_vma != ggtt_bind_vma); |
2761 | ggtt->base.bind_vma = aliasing_gtt_bind_vma; | |
2762 | ||
cbc4e9e6 CW |
2763 | WARN_ON(ggtt->base.unbind_vma != ggtt_unbind_vma); |
2764 | ggtt->base.unbind_vma = aliasing_gtt_unbind_vma; | |
2765 | ||
6cde9a02 CW |
2766 | return 0; |
2767 | ||
6cde9a02 | 2768 | err_ppgtt: |
1188bc66 | 2769 | i915_ppgtt_put(ppgtt); |
6cde9a02 CW |
2770 | return err; |
2771 | } | |
2772 | ||
2773 | void i915_gem_fini_aliasing_ppgtt(struct drm_i915_private *i915) | |
2774 | { | |
2775 | struct i915_ggtt *ggtt = &i915->ggtt; | |
2776 | struct i915_hw_ppgtt *ppgtt; | |
2777 | ||
2778 | ppgtt = fetch_and_zero(&i915->mm.aliasing_ppgtt); | |
2779 | if (!ppgtt) | |
2780 | return; | |
2781 | ||
1188bc66 | 2782 | i915_ppgtt_put(ppgtt); |
6cde9a02 CW |
2783 | |
2784 | ggtt->base.bind_vma = ggtt_bind_vma; | |
cbc4e9e6 | 2785 | ggtt->base.unbind_vma = ggtt_unbind_vma; |
6cde9a02 CW |
2786 | } |
2787 | ||
f6b9d5ca | 2788 | int i915_gem_init_ggtt(struct drm_i915_private *dev_priv) |
644ec02b | 2789 | { |
e78891ca BW |
2790 | /* Let GEM Manage all of the aperture. |
2791 | * | |
2792 | * However, leave one page at the end still bound to the scratch page. | |
2793 | * There are a number of places where the hardware apparently prefetches | |
2794 | * past the end of the object, and we've seen multiple hangs with the | |
2795 | * GPU head pointer stuck in a batchbuffer bound at the last page of the | |
2796 | * aperture. One page should be enough to keep any prefetching inside | |
2797 | * of the aperture. | |
2798 | */ | |
72e96d64 | 2799 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
ed2f3452 | 2800 | unsigned long hole_start, hole_end; |
f6b9d5ca | 2801 | struct drm_mm_node *entry; |
fa76da34 | 2802 | int ret; |
644ec02b | 2803 | |
b02d22a3 ZW |
2804 | ret = intel_vgt_balloon(dev_priv); |
2805 | if (ret) | |
2806 | return ret; | |
5dda8fa3 | 2807 | |
95374d75 | 2808 | /* Reserve a mappable slot for our lockless error capture */ |
4e64e553 CW |
2809 | ret = drm_mm_insert_node_in_range(&ggtt->base.mm, &ggtt->error_capture, |
2810 | PAGE_SIZE, 0, I915_COLOR_UNEVICTABLE, | |
2811 | 0, ggtt->mappable_end, | |
2812 | DRM_MM_INSERT_LOW); | |
95374d75 CW |
2813 | if (ret) |
2814 | return ret; | |
2815 | ||
ed2f3452 | 2816 | /* Clear any non-preallocated blocks */ |
72e96d64 | 2817 | drm_mm_for_each_hole(entry, &ggtt->base.mm, hole_start, hole_end) { |
ed2f3452 CW |
2818 | DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n", |
2819 | hole_start, hole_end); | |
72e96d64 | 2820 | ggtt->base.clear_range(&ggtt->base, hole_start, |
4fb84d99 | 2821 | hole_end - hole_start); |
ed2f3452 CW |
2822 | } |
2823 | ||
2824 | /* And finally clear the reserved guard page */ | |
f6b9d5ca | 2825 | ggtt->base.clear_range(&ggtt->base, |
4fb84d99 | 2826 | ggtt->base.total - PAGE_SIZE, PAGE_SIZE); |
6c5566a8 | 2827 | |
97d6d7ab | 2828 | if (USES_PPGTT(dev_priv) && !USES_FULL_PPGTT(dev_priv)) { |
6cde9a02 | 2829 | ret = i915_gem_init_aliasing_ppgtt(dev_priv); |
95374d75 | 2830 | if (ret) |
6cde9a02 | 2831 | goto err; |
fa76da34 DV |
2832 | } |
2833 | ||
6c5566a8 | 2834 | return 0; |
95374d75 | 2835 | |
95374d75 CW |
2836 | err: |
2837 | drm_mm_remove_node(&ggtt->error_capture); | |
2838 | return ret; | |
e76e9aeb BW |
2839 | } |
2840 | ||
d85489d3 JL |
2841 | /** |
2842 | * i915_ggtt_cleanup_hw - Clean up GGTT hardware initialization | |
97d6d7ab | 2843 | * @dev_priv: i915 device |
d85489d3 | 2844 | */ |
97d6d7ab | 2845 | void i915_ggtt_cleanup_hw(struct drm_i915_private *dev_priv) |
90d0a0e8 | 2846 | { |
72e96d64 | 2847 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
94d4a2a9 | 2848 | struct i915_vma *vma, *vn; |
66df1014 | 2849 | struct pagevec *pvec; |
94d4a2a9 CW |
2850 | |
2851 | ggtt->base.closed = true; | |
2852 | ||
2853 | mutex_lock(&dev_priv->drm.struct_mutex); | |
2854 | WARN_ON(!list_empty(&ggtt->base.active_list)); | |
2855 | list_for_each_entry_safe(vma, vn, &ggtt->base.inactive_list, vm_link) | |
2856 | WARN_ON(i915_vma_unbind(vma)); | |
2857 | mutex_unlock(&dev_priv->drm.struct_mutex); | |
90d0a0e8 | 2858 | |
97d6d7ab | 2859 | i915_gem_cleanup_stolen(&dev_priv->drm); |
a4eba47b | 2860 | |
1188bc66 CW |
2861 | mutex_lock(&dev_priv->drm.struct_mutex); |
2862 | i915_gem_fini_aliasing_ppgtt(dev_priv); | |
2863 | ||
95374d75 CW |
2864 | if (drm_mm_node_allocated(&ggtt->error_capture)) |
2865 | drm_mm_remove_node(&ggtt->error_capture); | |
2866 | ||
72e96d64 | 2867 | if (drm_mm_initialized(&ggtt->base.mm)) { |
b02d22a3 | 2868 | intel_vgt_deballoon(dev_priv); |
ed9724dd | 2869 | i915_address_space_fini(&ggtt->base); |
90d0a0e8 DV |
2870 | } |
2871 | ||
72e96d64 | 2872 | ggtt->base.cleanup(&ggtt->base); |
66df1014 CW |
2873 | |
2874 | pvec = &dev_priv->mm.wc_stash; | |
2875 | if (pvec->nr) { | |
2876 | set_pages_array_wb(pvec->pages, pvec->nr); | |
2877 | __pagevec_release(pvec); | |
2878 | } | |
2879 | ||
1188bc66 | 2880 | mutex_unlock(&dev_priv->drm.struct_mutex); |
f6b9d5ca CW |
2881 | |
2882 | arch_phys_wc_del(ggtt->mtrr); | |
b06f4c80 | 2883 | io_mapping_fini(&ggtt->iomap); |
90d0a0e8 | 2884 | } |
70e32544 | 2885 | |
2c642b07 | 2886 | static unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl) |
e76e9aeb BW |
2887 | { |
2888 | snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT; | |
2889 | snb_gmch_ctl &= SNB_GMCH_GGMS_MASK; | |
2890 | return snb_gmch_ctl << 20; | |
2891 | } | |
2892 | ||
2c642b07 | 2893 | static unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl) |
9459d252 BW |
2894 | { |
2895 | bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT; | |
2896 | bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK; | |
2897 | if (bdw_gmch_ctl) | |
2898 | bdw_gmch_ctl = 1 << bdw_gmch_ctl; | |
562d55d9 BW |
2899 | |
2900 | #ifdef CONFIG_X86_32 | |
da1d95b6 | 2901 | /* Limit 32b platforms to a 2GB GGTT: 4 << 20 / pte size * I915_GTT_PAGE_SIZE */ |
562d55d9 BW |
2902 | if (bdw_gmch_ctl > 4) |
2903 | bdw_gmch_ctl = 4; | |
2904 | #endif | |
2905 | ||
9459d252 BW |
2906 | return bdw_gmch_ctl << 20; |
2907 | } | |
2908 | ||
2c642b07 | 2909 | static unsigned int chv_get_total_gtt_size(u16 gmch_ctrl) |
d7f25f23 DL |
2910 | { |
2911 | gmch_ctrl >>= SNB_GMCH_GGMS_SHIFT; | |
2912 | gmch_ctrl &= SNB_GMCH_GGMS_MASK; | |
2913 | ||
2914 | if (gmch_ctrl) | |
2915 | return 1 << (20 + gmch_ctrl); | |
2916 | ||
2917 | return 0; | |
2918 | } | |
2919 | ||
2c642b07 | 2920 | static size_t gen6_get_stolen_size(u16 snb_gmch_ctl) |
e76e9aeb BW |
2921 | { |
2922 | snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT; | |
2923 | snb_gmch_ctl &= SNB_GMCH_GMS_MASK; | |
a92d1a91 | 2924 | return (size_t)snb_gmch_ctl << 25; /* 32 MB units */ |
e76e9aeb BW |
2925 | } |
2926 | ||
2c642b07 | 2927 | static size_t gen8_get_stolen_size(u16 bdw_gmch_ctl) |
9459d252 BW |
2928 | { |
2929 | bdw_gmch_ctl >>= BDW_GMCH_GMS_SHIFT; | |
2930 | bdw_gmch_ctl &= BDW_GMCH_GMS_MASK; | |
a92d1a91 | 2931 | return (size_t)bdw_gmch_ctl << 25; /* 32 MB units */ |
9459d252 BW |
2932 | } |
2933 | ||
d7f25f23 DL |
2934 | static size_t chv_get_stolen_size(u16 gmch_ctrl) |
2935 | { | |
2936 | gmch_ctrl >>= SNB_GMCH_GMS_SHIFT; | |
2937 | gmch_ctrl &= SNB_GMCH_GMS_MASK; | |
2938 | ||
2939 | /* | |
2940 | * 0x0 to 0x10: 32MB increments starting at 0MB | |
2941 | * 0x11 to 0x16: 4MB increments starting at 8MB | |
2942 | * 0x17 to 0x1d: 4MB increments start at 36MB | |
2943 | */ | |
2944 | if (gmch_ctrl < 0x11) | |
a92d1a91 | 2945 | return (size_t)gmch_ctrl << 25; |
d7f25f23 | 2946 | else if (gmch_ctrl < 0x17) |
a92d1a91 | 2947 | return (size_t)(gmch_ctrl - 0x11 + 2) << 22; |
d7f25f23 | 2948 | else |
a92d1a91 | 2949 | return (size_t)(gmch_ctrl - 0x17 + 9) << 22; |
d7f25f23 DL |
2950 | } |
2951 | ||
66375014 DL |
2952 | static size_t gen9_get_stolen_size(u16 gen9_gmch_ctl) |
2953 | { | |
2954 | gen9_gmch_ctl >>= BDW_GMCH_GMS_SHIFT; | |
2955 | gen9_gmch_ctl &= BDW_GMCH_GMS_MASK; | |
2956 | ||
2957 | if (gen9_gmch_ctl < 0xf0) | |
a92d1a91 | 2958 | return (size_t)gen9_gmch_ctl << 25; /* 32 MB units */ |
66375014 DL |
2959 | else |
2960 | /* 4MB increments starting at 0xf0 for 4MB */ | |
a92d1a91 | 2961 | return (size_t)(gen9_gmch_ctl - 0xf0 + 1) << 22; |
66375014 DL |
2962 | } |
2963 | ||
34c998b4 | 2964 | static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size) |
63340133 | 2965 | { |
49d73912 CW |
2966 | struct drm_i915_private *dev_priv = ggtt->base.i915; |
2967 | struct pci_dev *pdev = dev_priv->drm.pdev; | |
34c998b4 | 2968 | phys_addr_t phys_addr; |
8bcdd0f7 | 2969 | int ret; |
63340133 BW |
2970 | |
2971 | /* For Modern GENs the PTEs and register space are split in the BAR */ | |
34c998b4 | 2972 | phys_addr = pci_resource_start(pdev, 0) + pci_resource_len(pdev, 0) / 2; |
63340133 | 2973 | |
2a073f89 | 2974 | /* |
385db982 RV |
2975 | * On BXT+/CNL+ writes larger than 64 bit to the GTT pagetable range |
2976 | * will be dropped. For WC mappings in general we have 64 byte burst | |
2977 | * writes when the WC buffer is flushed, so we can't use it, but have to | |
2a073f89 ID |
2978 | * resort to an uncached mapping. The WC issue is easily caught by the |
2979 | * readback check when writing GTT PTE entries. | |
2980 | */ | |
385db982 | 2981 | if (IS_GEN9_LP(dev_priv) || INTEL_GEN(dev_priv) >= 10) |
34c998b4 | 2982 | ggtt->gsm = ioremap_nocache(phys_addr, size); |
2a073f89 | 2983 | else |
34c998b4 | 2984 | ggtt->gsm = ioremap_wc(phys_addr, size); |
72e96d64 | 2985 | if (!ggtt->gsm) { |
34c998b4 | 2986 | DRM_ERROR("Failed to map the ggtt page table\n"); |
63340133 BW |
2987 | return -ENOMEM; |
2988 | } | |
2989 | ||
8448661d | 2990 | ret = setup_scratch_page(&ggtt->base, GFP_DMA32); |
8bcdd0f7 | 2991 | if (ret) { |
63340133 BW |
2992 | DRM_ERROR("Scratch setup failed\n"); |
2993 | /* iounmap will also get called at remove, but meh */ | |
72e96d64 | 2994 | iounmap(ggtt->gsm); |
8bcdd0f7 | 2995 | return ret; |
63340133 BW |
2996 | } |
2997 | ||
4ad2af1e | 2998 | return 0; |
63340133 BW |
2999 | } |
3000 | ||
4395890a ZW |
3001 | static struct intel_ppat_entry * |
3002 | __alloc_ppat_entry(struct intel_ppat *ppat, unsigned int index, u8 value) | |
4e34935f | 3003 | { |
4395890a ZW |
3004 | struct intel_ppat_entry *entry = &ppat->entries[index]; |
3005 | ||
3006 | GEM_BUG_ON(index >= ppat->max_entries); | |
3007 | GEM_BUG_ON(test_bit(index, ppat->used)); | |
3008 | ||
3009 | entry->ppat = ppat; | |
3010 | entry->value = value; | |
3011 | kref_init(&entry->ref); | |
3012 | set_bit(index, ppat->used); | |
3013 | set_bit(index, ppat->dirty); | |
3014 | ||
3015 | return entry; | |
3016 | } | |
3017 | ||
3018 | static void __free_ppat_entry(struct intel_ppat_entry *entry) | |
4e34935f | 3019 | { |
4395890a ZW |
3020 | struct intel_ppat *ppat = entry->ppat; |
3021 | unsigned int index = entry - ppat->entries; | |
3022 | ||
3023 | GEM_BUG_ON(index >= ppat->max_entries); | |
3024 | GEM_BUG_ON(!test_bit(index, ppat->used)); | |
3025 | ||
3026 | entry->value = ppat->clear_value; | |
3027 | clear_bit(index, ppat->used); | |
3028 | set_bit(index, ppat->dirty); | |
3029 | } | |
3030 | ||
3031 | /** | |
3032 | * intel_ppat_get - get a usable PPAT entry | |
3033 | * @i915: i915 device instance | |
3034 | * @value: the PPAT value required by the caller | |
3035 | * | |
3036 | * The function tries to search if there is an existing PPAT entry which | |
3037 | * matches with the required value. If perfectly matched, the existing PPAT | |
3038 | * entry will be used. If only partially matched, it will try to check if | |
3039 | * there is any available PPAT index. If yes, it will allocate a new PPAT | |
3040 | * index for the required entry and update the HW. If not, the partially | |
3041 | * matched entry will be used. | |
3042 | */ | |
3043 | const struct intel_ppat_entry * | |
3044 | intel_ppat_get(struct drm_i915_private *i915, u8 value) | |
3045 | { | |
3046 | struct intel_ppat *ppat = &i915->ppat; | |
3047 | struct intel_ppat_entry *entry; | |
3048 | unsigned int scanned, best_score; | |
3049 | int i; | |
3050 | ||
3051 | GEM_BUG_ON(!ppat->max_entries); | |
3052 | ||
3053 | scanned = best_score = 0; | |
3054 | for_each_set_bit(i, ppat->used, ppat->max_entries) { | |
3055 | unsigned int score; | |
3056 | ||
3057 | score = ppat->match(ppat->entries[i].value, value); | |
3058 | if (score > best_score) { | |
3059 | entry = &ppat->entries[i]; | |
3060 | if (score == INTEL_PPAT_PERFECT_MATCH) { | |
3061 | kref_get(&entry->ref); | |
3062 | return entry; | |
3063 | } | |
3064 | best_score = score; | |
3065 | } | |
3066 | scanned++; | |
3067 | } | |
3068 | ||
3069 | if (scanned == ppat->max_entries) { | |
3070 | if (!best_score) | |
3071 | return ERR_PTR(-ENOSPC); | |
3072 | ||
3073 | kref_get(&entry->ref); | |
3074 | return entry; | |
3075 | } | |
3076 | ||
3077 | i = find_first_zero_bit(ppat->used, ppat->max_entries); | |
3078 | entry = __alloc_ppat_entry(ppat, i, value); | |
3079 | ppat->update_hw(i915); | |
3080 | return entry; | |
3081 | } | |
3082 | ||
3083 | static void release_ppat(struct kref *kref) | |
3084 | { | |
3085 | struct intel_ppat_entry *entry = | |
3086 | container_of(kref, struct intel_ppat_entry, ref); | |
3087 | struct drm_i915_private *i915 = entry->ppat->i915; | |
3088 | ||
3089 | __free_ppat_entry(entry); | |
3090 | entry->ppat->update_hw(i915); | |
3091 | } | |
3092 | ||
3093 | /** | |
3094 | * intel_ppat_put - put back the PPAT entry got from intel_ppat_get() | |
3095 | * @entry: an intel PPAT entry | |
3096 | * | |
3097 | * Put back the PPAT entry got from intel_ppat_get(). If the PPAT index of the | |
3098 | * entry is dynamically allocated, its reference count will be decreased. Once | |
3099 | * the reference count becomes into zero, the PPAT index becomes free again. | |
3100 | */ | |
3101 | void intel_ppat_put(const struct intel_ppat_entry *entry) | |
3102 | { | |
3103 | struct intel_ppat *ppat = entry->ppat; | |
3104 | unsigned int index = entry - ppat->entries; | |
3105 | ||
3106 | GEM_BUG_ON(!ppat->max_entries); | |
3107 | ||
3108 | kref_put(&ppat->entries[index].ref, release_ppat); | |
3109 | } | |
3110 | ||
3111 | static void cnl_private_pat_update_hw(struct drm_i915_private *dev_priv) | |
3112 | { | |
3113 | struct intel_ppat *ppat = &dev_priv->ppat; | |
3114 | int i; | |
3115 | ||
3116 | for_each_set_bit(i, ppat->dirty, ppat->max_entries) { | |
3117 | I915_WRITE(GEN10_PAT_INDEX(i), ppat->entries[i].value); | |
3118 | clear_bit(i, ppat->dirty); | |
3119 | } | |
3120 | } | |
3121 | ||
3122 | static void bdw_private_pat_update_hw(struct drm_i915_private *dev_priv) | |
3123 | { | |
3124 | struct intel_ppat *ppat = &dev_priv->ppat; | |
3125 | u64 pat = 0; | |
3126 | int i; | |
3127 | ||
3128 | for (i = 0; i < ppat->max_entries; i++) | |
3129 | pat |= GEN8_PPAT(i, ppat->entries[i].value); | |
3130 | ||
3131 | bitmap_clear(ppat->dirty, 0, ppat->max_entries); | |
3132 | ||
3133 | I915_WRITE(GEN8_PRIVATE_PAT_LO, lower_32_bits(pat)); | |
3134 | I915_WRITE(GEN8_PRIVATE_PAT_HI, upper_32_bits(pat)); | |
3135 | } | |
3136 | ||
3137 | static unsigned int bdw_private_pat_match(u8 src, u8 dst) | |
3138 | { | |
3139 | unsigned int score = 0; | |
3140 | enum { | |
3141 | AGE_MATCH = BIT(0), | |
3142 | TC_MATCH = BIT(1), | |
3143 | CA_MATCH = BIT(2), | |
3144 | }; | |
3145 | ||
3146 | /* Cache attribute has to be matched. */ | |
1298d51c | 3147 | if (GEN8_PPAT_GET_CA(src) != GEN8_PPAT_GET_CA(dst)) |
4395890a ZW |
3148 | return 0; |
3149 | ||
3150 | score |= CA_MATCH; | |
3151 | ||
3152 | if (GEN8_PPAT_GET_TC(src) == GEN8_PPAT_GET_TC(dst)) | |
3153 | score |= TC_MATCH; | |
3154 | ||
3155 | if (GEN8_PPAT_GET_AGE(src) == GEN8_PPAT_GET_AGE(dst)) | |
3156 | score |= AGE_MATCH; | |
3157 | ||
3158 | if (score == (AGE_MATCH | TC_MATCH | CA_MATCH)) | |
3159 | return INTEL_PPAT_PERFECT_MATCH; | |
3160 | ||
3161 | return score; | |
3162 | } | |
3163 | ||
3164 | static unsigned int chv_private_pat_match(u8 src, u8 dst) | |
3165 | { | |
3166 | return (CHV_PPAT_GET_SNOOP(src) == CHV_PPAT_GET_SNOOP(dst)) ? | |
3167 | INTEL_PPAT_PERFECT_MATCH : 0; | |
3168 | } | |
3169 | ||
3170 | static void cnl_setup_private_ppat(struct intel_ppat *ppat) | |
3171 | { | |
3172 | ppat->max_entries = 8; | |
3173 | ppat->update_hw = cnl_private_pat_update_hw; | |
3174 | ppat->match = bdw_private_pat_match; | |
3175 | ppat->clear_value = GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3); | |
3176 | ||
4e34935f | 3177 | /* XXX: spec is unclear if this is still needed for CNL+ */ |
4395890a ZW |
3178 | if (!USES_PPGTT(ppat->i915)) { |
3179 | __alloc_ppat_entry(ppat, 0, GEN8_PPAT_UC); | |
4e34935f RV |
3180 | return; |
3181 | } | |
3182 | ||
4395890a ZW |
3183 | __alloc_ppat_entry(ppat, 0, GEN8_PPAT_WB | GEN8_PPAT_LLC); |
3184 | __alloc_ppat_entry(ppat, 1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC); | |
3185 | __alloc_ppat_entry(ppat, 2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC); | |
3186 | __alloc_ppat_entry(ppat, 3, GEN8_PPAT_UC); | |
3187 | __alloc_ppat_entry(ppat, 4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)); | |
3188 | __alloc_ppat_entry(ppat, 5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)); | |
3189 | __alloc_ppat_entry(ppat, 6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)); | |
3190 | __alloc_ppat_entry(ppat, 7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3)); | |
4e34935f RV |
3191 | } |
3192 | ||
fbe5d36e BW |
3193 | /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability |
3194 | * bits. When using advanced contexts each context stores its own PAT, but | |
3195 | * writing this data shouldn't be harmful even in those cases. */ | |
4395890a | 3196 | static void bdw_setup_private_ppat(struct intel_ppat *ppat) |
fbe5d36e | 3197 | { |
4395890a ZW |
3198 | ppat->max_entries = 8; |
3199 | ppat->update_hw = bdw_private_pat_update_hw; | |
3200 | ppat->match = bdw_private_pat_match; | |
3201 | ppat->clear_value = GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3); | |
fbe5d36e | 3202 | |
4395890a | 3203 | if (!USES_PPGTT(ppat->i915)) { |
d6a8b72e RV |
3204 | /* Spec: "For GGTT, there is NO pat_sel[2:0] from the entry, |
3205 | * so RTL will always use the value corresponding to | |
3206 | * pat_sel = 000". | |
3207 | * So let's disable cache for GGTT to avoid screen corruptions. | |
3208 | * MOCS still can be used though. | |
3209 | * - System agent ggtt writes (i.e. cpu gtt mmaps) already work | |
3210 | * before this patch, i.e. the same uncached + snooping access | |
3211 | * like on gen6/7 seems to be in effect. | |
3212 | * - So this just fixes blitter/render access. Again it looks | |
3213 | * like it's not just uncached access, but uncached + snooping. | |
3214 | * So we can still hold onto all our assumptions wrt cpu | |
3215 | * clflushing on LLC machines. | |
3216 | */ | |
4395890a ZW |
3217 | __alloc_ppat_entry(ppat, 0, GEN8_PPAT_UC); |
3218 | return; | |
3219 | } | |
d6a8b72e | 3220 | |
4395890a ZW |
3221 | __alloc_ppat_entry(ppat, 0, GEN8_PPAT_WB | GEN8_PPAT_LLC); /* for normal objects, no eLLC */ |
3222 | __alloc_ppat_entry(ppat, 1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC); /* for something pointing to ptes? */ | |
3223 | __alloc_ppat_entry(ppat, 2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC); /* for scanout with eLLC */ | |
3224 | __alloc_ppat_entry(ppat, 3, GEN8_PPAT_UC); /* Uncached objects, mostly for scanout */ | |
3225 | __alloc_ppat_entry(ppat, 4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)); | |
3226 | __alloc_ppat_entry(ppat, 5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)); | |
3227 | __alloc_ppat_entry(ppat, 6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)); | |
3228 | __alloc_ppat_entry(ppat, 7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3)); | |
fbe5d36e BW |
3229 | } |
3230 | ||
4395890a | 3231 | static void chv_setup_private_ppat(struct intel_ppat *ppat) |
ee0ce478 | 3232 | { |
4395890a ZW |
3233 | ppat->max_entries = 8; |
3234 | ppat->update_hw = bdw_private_pat_update_hw; | |
3235 | ppat->match = chv_private_pat_match; | |
3236 | ppat->clear_value = CHV_PPAT_SNOOP; | |
ee0ce478 VS |
3237 | |
3238 | /* | |
3239 | * Map WB on BDW to snooped on CHV. | |
3240 | * | |
3241 | * Only the snoop bit has meaning for CHV, the rest is | |
3242 | * ignored. | |
3243 | * | |
cf3d262e VS |
3244 | * The hardware will never snoop for certain types of accesses: |
3245 | * - CPU GTT (GMADR->GGTT->no snoop->memory) | |
3246 | * - PPGTT page tables | |
3247 | * - some other special cycles | |
3248 | * | |
3249 | * As with BDW, we also need to consider the following for GT accesses: | |
3250 | * "For GGTT, there is NO pat_sel[2:0] from the entry, | |
3251 | * so RTL will always use the value corresponding to | |
3252 | * pat_sel = 000". | |
3253 | * Which means we must set the snoop bit in PAT entry 0 | |
3254 | * in order to keep the global status page working. | |
ee0ce478 | 3255 | */ |
ee0ce478 | 3256 | |
4395890a ZW |
3257 | __alloc_ppat_entry(ppat, 0, CHV_PPAT_SNOOP); |
3258 | __alloc_ppat_entry(ppat, 1, 0); | |
3259 | __alloc_ppat_entry(ppat, 2, 0); | |
3260 | __alloc_ppat_entry(ppat, 3, 0); | |
3261 | __alloc_ppat_entry(ppat, 4, CHV_PPAT_SNOOP); | |
3262 | __alloc_ppat_entry(ppat, 5, CHV_PPAT_SNOOP); | |
3263 | __alloc_ppat_entry(ppat, 6, CHV_PPAT_SNOOP); | |
3264 | __alloc_ppat_entry(ppat, 7, CHV_PPAT_SNOOP); | |
ee0ce478 VS |
3265 | } |
3266 | ||
34c998b4 CW |
3267 | static void gen6_gmch_remove(struct i915_address_space *vm) |
3268 | { | |
3269 | struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm); | |
3270 | ||
3271 | iounmap(ggtt->gsm); | |
8448661d | 3272 | cleanup_scratch_page(vm); |
34c998b4 CW |
3273 | } |
3274 | ||
36e16c49 ZW |
3275 | static void setup_private_pat(struct drm_i915_private *dev_priv) |
3276 | { | |
4395890a ZW |
3277 | struct intel_ppat *ppat = &dev_priv->ppat; |
3278 | int i; | |
3279 | ||
3280 | ppat->i915 = dev_priv; | |
3281 | ||
36e16c49 | 3282 | if (INTEL_GEN(dev_priv) >= 10) |
4395890a | 3283 | cnl_setup_private_ppat(ppat); |
36e16c49 | 3284 | else if (IS_CHERRYVIEW(dev_priv) || IS_GEN9_LP(dev_priv)) |
4395890a | 3285 | chv_setup_private_ppat(ppat); |
36e16c49 | 3286 | else |
4395890a ZW |
3287 | bdw_setup_private_ppat(ppat); |
3288 | ||
3289 | GEM_BUG_ON(ppat->max_entries > INTEL_MAX_PPAT_ENTRIES); | |
3290 | ||
3291 | for_each_clear_bit(i, ppat->used, ppat->max_entries) { | |
3292 | ppat->entries[i].value = ppat->clear_value; | |
3293 | ppat->entries[i].ppat = ppat; | |
3294 | set_bit(i, ppat->dirty); | |
3295 | } | |
3296 | ||
3297 | ppat->update_hw(dev_priv); | |
36e16c49 ZW |
3298 | } |
3299 | ||
d507d735 | 3300 | static int gen8_gmch_probe(struct i915_ggtt *ggtt) |
63340133 | 3301 | { |
49d73912 | 3302 | struct drm_i915_private *dev_priv = ggtt->base.i915; |
97d6d7ab | 3303 | struct pci_dev *pdev = dev_priv->drm.pdev; |
34c998b4 | 3304 | unsigned int size; |
63340133 | 3305 | u16 snb_gmch_ctl; |
4519290a | 3306 | int err; |
63340133 BW |
3307 | |
3308 | /* TODO: We're not aware of mappable constraints on gen8 yet */ | |
b06f4c80 MA |
3309 | ggtt->gmadr = |
3310 | (struct resource) DEFINE_RES_MEM(pci_resource_start(pdev, 2), | |
3311 | pci_resource_len(pdev, 2)); | |
3312 | ggtt->mappable_end = resource_size(&ggtt->gmadr); | |
63340133 | 3313 | |
4519290a ID |
3314 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(39)); |
3315 | if (!err) | |
3316 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(39)); | |
3317 | if (err) | |
3318 | DRM_ERROR("Can't set DMA mask/consistent mask (%d)\n", err); | |
63340133 | 3319 | |
97d6d7ab | 3320 | pci_read_config_word(pdev, SNB_GMCH_CTRL, &snb_gmch_ctl); |
63340133 | 3321 | |
97d6d7ab | 3322 | if (INTEL_GEN(dev_priv) >= 9) { |
d507d735 | 3323 | ggtt->stolen_size = gen9_get_stolen_size(snb_gmch_ctl); |
34c998b4 | 3324 | size = gen8_get_total_gtt_size(snb_gmch_ctl); |
97d6d7ab | 3325 | } else if (IS_CHERRYVIEW(dev_priv)) { |
d507d735 | 3326 | ggtt->stolen_size = chv_get_stolen_size(snb_gmch_ctl); |
34c998b4 | 3327 | size = chv_get_total_gtt_size(snb_gmch_ctl); |
d7f25f23 | 3328 | } else { |
d507d735 | 3329 | ggtt->stolen_size = gen8_get_stolen_size(snb_gmch_ctl); |
34c998b4 | 3330 | size = gen8_get_total_gtt_size(snb_gmch_ctl); |
d7f25f23 | 3331 | } |
63340133 | 3332 | |
34c998b4 | 3333 | ggtt->base.total = (size / sizeof(gen8_pte_t)) << PAGE_SHIFT; |
34c998b4 | 3334 | ggtt->base.cleanup = gen6_gmch_remove; |
d507d735 JL |
3335 | ggtt->base.bind_vma = ggtt_bind_vma; |
3336 | ggtt->base.unbind_vma = ggtt_unbind_vma; | |
fa3f46af MA |
3337 | ggtt->base.set_pages = ggtt_set_pages; |
3338 | ggtt->base.clear_pages = clear_pages; | |
d6473f56 | 3339 | ggtt->base.insert_page = gen8_ggtt_insert_page; |
f7770bfd | 3340 | ggtt->base.clear_range = nop_clear_range; |
48f112fe | 3341 | if (!USES_FULL_PPGTT(dev_priv) || intel_scanout_needs_vtd_wa(dev_priv)) |
f7770bfd CW |
3342 | ggtt->base.clear_range = gen8_ggtt_clear_range; |
3343 | ||
3344 | ggtt->base.insert_entries = gen8_ggtt_insert_entries; | |
f7770bfd | 3345 | |
0ef34ad6 JB |
3346 | /* Serialize GTT updates with aperture access on BXT if VT-d is on. */ |
3347 | if (intel_ggtt_update_needs_vtd_wa(dev_priv)) { | |
3348 | ggtt->base.insert_entries = bxt_vtd_ggtt_insert_entries__BKL; | |
3349 | ggtt->base.insert_page = bxt_vtd_ggtt_insert_page__BKL; | |
3350 | if (ggtt->base.clear_range != nop_clear_range) | |
3351 | ggtt->base.clear_range = bxt_vtd_ggtt_clear_range__BKL; | |
3352 | } | |
3353 | ||
7c3f86b6 CW |
3354 | ggtt->invalidate = gen6_ggtt_invalidate; |
3355 | ||
36e16c49 ZW |
3356 | setup_private_pat(dev_priv); |
3357 | ||
34c998b4 | 3358 | return ggtt_probe_common(ggtt, size); |
63340133 BW |
3359 | } |
3360 | ||
d507d735 | 3361 | static int gen6_gmch_probe(struct i915_ggtt *ggtt) |
e76e9aeb | 3362 | { |
49d73912 | 3363 | struct drm_i915_private *dev_priv = ggtt->base.i915; |
97d6d7ab | 3364 | struct pci_dev *pdev = dev_priv->drm.pdev; |
34c998b4 | 3365 | unsigned int size; |
e76e9aeb | 3366 | u16 snb_gmch_ctl; |
4519290a | 3367 | int err; |
e76e9aeb | 3368 | |
b06f4c80 MA |
3369 | ggtt->gmadr = |
3370 | (struct resource) DEFINE_RES_MEM(pci_resource_start(pdev, 2), | |
3371 | pci_resource_len(pdev, 2)); | |
3372 | ggtt->mappable_end = resource_size(&ggtt->gmadr); | |
41907ddc | 3373 | |
baa09f5f BW |
3374 | /* 64/512MB is the current min/max we actually know of, but this is just |
3375 | * a coarse sanity check. | |
e76e9aeb | 3376 | */ |
34c998b4 | 3377 | if (ggtt->mappable_end < (64<<20) || ggtt->mappable_end > (512<<20)) { |
d507d735 | 3378 | DRM_ERROR("Unknown GMADR size (%llx)\n", ggtt->mappable_end); |
baa09f5f | 3379 | return -ENXIO; |
e76e9aeb BW |
3380 | } |
3381 | ||
4519290a ID |
3382 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(40)); |
3383 | if (!err) | |
3384 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(40)); | |
3385 | if (err) | |
3386 | DRM_ERROR("Can't set DMA mask/consistent mask (%d)\n", err); | |
97d6d7ab | 3387 | pci_read_config_word(pdev, SNB_GMCH_CTRL, &snb_gmch_ctl); |
e76e9aeb | 3388 | |
d507d735 | 3389 | ggtt->stolen_size = gen6_get_stolen_size(snb_gmch_ctl); |
e76e9aeb | 3390 | |
34c998b4 CW |
3391 | size = gen6_get_total_gtt_size(snb_gmch_ctl); |
3392 | ggtt->base.total = (size / sizeof(gen6_pte_t)) << PAGE_SHIFT; | |
e76e9aeb | 3393 | |
d507d735 | 3394 | ggtt->base.clear_range = gen6_ggtt_clear_range; |
d6473f56 | 3395 | ggtt->base.insert_page = gen6_ggtt_insert_page; |
d507d735 JL |
3396 | ggtt->base.insert_entries = gen6_ggtt_insert_entries; |
3397 | ggtt->base.bind_vma = ggtt_bind_vma; | |
3398 | ggtt->base.unbind_vma = ggtt_unbind_vma; | |
fa3f46af MA |
3399 | ggtt->base.set_pages = ggtt_set_pages; |
3400 | ggtt->base.clear_pages = clear_pages; | |
34c998b4 CW |
3401 | ggtt->base.cleanup = gen6_gmch_remove; |
3402 | ||
7c3f86b6 CW |
3403 | ggtt->invalidate = gen6_ggtt_invalidate; |
3404 | ||
34c998b4 CW |
3405 | if (HAS_EDRAM(dev_priv)) |
3406 | ggtt->base.pte_encode = iris_pte_encode; | |
3407 | else if (IS_HASWELL(dev_priv)) | |
3408 | ggtt->base.pte_encode = hsw_pte_encode; | |
3409 | else if (IS_VALLEYVIEW(dev_priv)) | |
3410 | ggtt->base.pte_encode = byt_pte_encode; | |
3411 | else if (INTEL_GEN(dev_priv) >= 7) | |
3412 | ggtt->base.pte_encode = ivb_pte_encode; | |
3413 | else | |
3414 | ggtt->base.pte_encode = snb_pte_encode; | |
7faf1ab2 | 3415 | |
34c998b4 | 3416 | return ggtt_probe_common(ggtt, size); |
e76e9aeb BW |
3417 | } |
3418 | ||
34c998b4 | 3419 | static void i915_gmch_remove(struct i915_address_space *vm) |
e76e9aeb | 3420 | { |
34c998b4 | 3421 | intel_gmch_remove(); |
644ec02b | 3422 | } |
baa09f5f | 3423 | |
d507d735 | 3424 | static int i915_gmch_probe(struct i915_ggtt *ggtt) |
baa09f5f | 3425 | { |
49d73912 | 3426 | struct drm_i915_private *dev_priv = ggtt->base.i915; |
b06f4c80 | 3427 | phys_addr_t gmadr_base; |
baa09f5f BW |
3428 | int ret; |
3429 | ||
91c8a326 | 3430 | ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->drm.pdev, NULL); |
baa09f5f BW |
3431 | if (!ret) { |
3432 | DRM_ERROR("failed to set up gmch\n"); | |
3433 | return -EIO; | |
3434 | } | |
3435 | ||
edd1f2fe CW |
3436 | intel_gtt_get(&ggtt->base.total, |
3437 | &ggtt->stolen_size, | |
b06f4c80 | 3438 | &gmadr_base, |
edd1f2fe | 3439 | &ggtt->mappable_end); |
baa09f5f | 3440 | |
b06f4c80 MA |
3441 | ggtt->gmadr = |
3442 | (struct resource) DEFINE_RES_MEM(gmadr_base, | |
3443 | ggtt->mappable_end); | |
3444 | ||
97d6d7ab | 3445 | ggtt->do_idle_maps = needs_idle_maps(dev_priv); |
d6473f56 | 3446 | ggtt->base.insert_page = i915_ggtt_insert_page; |
d507d735 JL |
3447 | ggtt->base.insert_entries = i915_ggtt_insert_entries; |
3448 | ggtt->base.clear_range = i915_ggtt_clear_range; | |
3449 | ggtt->base.bind_vma = ggtt_bind_vma; | |
3450 | ggtt->base.unbind_vma = ggtt_unbind_vma; | |
fa3f46af MA |
3451 | ggtt->base.set_pages = ggtt_set_pages; |
3452 | ggtt->base.clear_pages = clear_pages; | |
34c998b4 | 3453 | ggtt->base.cleanup = i915_gmch_remove; |
baa09f5f | 3454 | |
7c3f86b6 CW |
3455 | ggtt->invalidate = gmch_ggtt_invalidate; |
3456 | ||
d507d735 | 3457 | if (unlikely(ggtt->do_idle_maps)) |
c0a7f818 CW |
3458 | DRM_INFO("applying Ironlake quirks for intel_iommu\n"); |
3459 | ||
baa09f5f BW |
3460 | return 0; |
3461 | } | |
3462 | ||
d85489d3 | 3463 | /** |
0088e522 | 3464 | * i915_ggtt_probe_hw - Probe GGTT hardware location |
97d6d7ab | 3465 | * @dev_priv: i915 device |
d85489d3 | 3466 | */ |
97d6d7ab | 3467 | int i915_ggtt_probe_hw(struct drm_i915_private *dev_priv) |
baa09f5f | 3468 | { |
62106b4f | 3469 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
baa09f5f BW |
3470 | int ret; |
3471 | ||
49d73912 | 3472 | ggtt->base.i915 = dev_priv; |
8448661d | 3473 | ggtt->base.dma = &dev_priv->drm.pdev->dev; |
c114f76a | 3474 | |
34c998b4 CW |
3475 | if (INTEL_GEN(dev_priv) <= 5) |
3476 | ret = i915_gmch_probe(ggtt); | |
3477 | else if (INTEL_GEN(dev_priv) < 8) | |
3478 | ret = gen6_gmch_probe(ggtt); | |
3479 | else | |
3480 | ret = gen8_gmch_probe(ggtt); | |
a54c0c27 | 3481 | if (ret) |
baa09f5f | 3482 | return ret; |
baa09f5f | 3483 | |
db9309a5 CW |
3484 | /* Trim the GGTT to fit the GuC mappable upper range (when enabled). |
3485 | * This is easier than doing range restriction on the fly, as we | |
3486 | * currently don't have any bits spare to pass in this upper | |
3487 | * restriction! | |
3488 | */ | |
4f044a88 | 3489 | if (HAS_GUC(dev_priv) && i915_modparams.enable_guc_loading) { |
db9309a5 CW |
3490 | ggtt->base.total = min_t(u64, ggtt->base.total, GUC_GGTT_TOP); |
3491 | ggtt->mappable_end = min(ggtt->mappable_end, ggtt->base.total); | |
3492 | } | |
3493 | ||
c890e2d5 CW |
3494 | if ((ggtt->base.total - 1) >> 32) { |
3495 | DRM_ERROR("We never expected a Global GTT with more than 32bits" | |
f6b9d5ca | 3496 | " of address space! Found %lldM!\n", |
c890e2d5 CW |
3497 | ggtt->base.total >> 20); |
3498 | ggtt->base.total = 1ULL << 32; | |
3499 | ggtt->mappable_end = min(ggtt->mappable_end, ggtt->base.total); | |
3500 | } | |
3501 | ||
f6b9d5ca CW |
3502 | if (ggtt->mappable_end > ggtt->base.total) { |
3503 | DRM_ERROR("mappable aperture extends past end of GGTT," | |
3504 | " aperture=%llx, total=%llx\n", | |
3505 | ggtt->mappable_end, ggtt->base.total); | |
3506 | ggtt->mappable_end = ggtt->base.total; | |
3507 | } | |
3508 | ||
baa09f5f | 3509 | /* GMADR is the PCI mmio aperture into the global GTT. */ |
c44ef60e | 3510 | DRM_INFO("Memory usable by graphics device = %lluM\n", |
62106b4f | 3511 | ggtt->base.total >> 20); |
b06f4c80 | 3512 | DRM_DEBUG_DRIVER("GMADR size = %lluM\n", (u64)ggtt->mappable_end >> 20); |
edd1f2fe | 3513 | DRM_DEBUG_DRIVER("GTT stolen size = %uM\n", ggtt->stolen_size >> 20); |
80debff8 | 3514 | if (intel_vtd_active()) |
5db6c735 | 3515 | DRM_INFO("VT-d active for gfx access\n"); |
baa09f5f BW |
3516 | |
3517 | return 0; | |
0088e522 CW |
3518 | } |
3519 | ||
3520 | /** | |
3521 | * i915_ggtt_init_hw - Initialize GGTT hardware | |
97d6d7ab | 3522 | * @dev_priv: i915 device |
0088e522 | 3523 | */ |
97d6d7ab | 3524 | int i915_ggtt_init_hw(struct drm_i915_private *dev_priv) |
0088e522 | 3525 | { |
0088e522 CW |
3526 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
3527 | int ret; | |
3528 | ||
f6b9d5ca CW |
3529 | INIT_LIST_HEAD(&dev_priv->vm_list); |
3530 | ||
a6508ded CW |
3531 | /* Note that we use page colouring to enforce a guard page at the |
3532 | * end of the address space. This is required as the CS may prefetch | |
3533 | * beyond the end of the batch buffer, across the page boundary, | |
3534 | * and beyond the end of the GTT if we do not provide a guard. | |
f6b9d5ca | 3535 | */ |
80b204bc | 3536 | mutex_lock(&dev_priv->drm.struct_mutex); |
80b204bc | 3537 | i915_address_space_init(&ggtt->base, dev_priv, "[global]"); |
a6508ded | 3538 | if (!HAS_LLC(dev_priv) && !USES_PPGTT(dev_priv)) |
f6b9d5ca | 3539 | ggtt->base.mm.color_adjust = i915_gtt_color_adjust; |
80b204bc | 3540 | mutex_unlock(&dev_priv->drm.struct_mutex); |
f6b9d5ca | 3541 | |
b06f4c80 MA |
3542 | if (!io_mapping_init_wc(&dev_priv->ggtt.iomap, |
3543 | dev_priv->ggtt.gmadr.start, | |
f7bbe788 | 3544 | dev_priv->ggtt.mappable_end)) { |
f6b9d5ca CW |
3545 | ret = -EIO; |
3546 | goto out_gtt_cleanup; | |
3547 | } | |
3548 | ||
b06f4c80 | 3549 | ggtt->mtrr = arch_phys_wc_add(ggtt->gmadr.start, ggtt->mappable_end); |
f6b9d5ca | 3550 | |
0088e522 CW |
3551 | /* |
3552 | * Initialise stolen early so that we may reserve preallocated | |
3553 | * objects for the BIOS to KMS transition. | |
3554 | */ | |
7ace3d30 | 3555 | ret = i915_gem_init_stolen(dev_priv); |
0088e522 CW |
3556 | if (ret) |
3557 | goto out_gtt_cleanup; | |
3558 | ||
3559 | return 0; | |
a4eba47b ID |
3560 | |
3561 | out_gtt_cleanup: | |
72e96d64 | 3562 | ggtt->base.cleanup(&ggtt->base); |
a4eba47b | 3563 | return ret; |
baa09f5f | 3564 | } |
6f65e29a | 3565 | |
97d6d7ab | 3566 | int i915_ggtt_enable_hw(struct drm_i915_private *dev_priv) |
ac840ae5 | 3567 | { |
97d6d7ab | 3568 | if (INTEL_GEN(dev_priv) < 6 && !intel_enable_gtt()) |
ac840ae5 VS |
3569 | return -EIO; |
3570 | ||
3571 | return 0; | |
3572 | } | |
3573 | ||
7c3f86b6 CW |
3574 | void i915_ggtt_enable_guc(struct drm_i915_private *i915) |
3575 | { | |
04f7b24e CW |
3576 | GEM_BUG_ON(i915->ggtt.invalidate != gen6_ggtt_invalidate); |
3577 | ||
7c3f86b6 CW |
3578 | i915->ggtt.invalidate = guc_ggtt_invalidate; |
3579 | } | |
3580 | ||
3581 | void i915_ggtt_disable_guc(struct drm_i915_private *i915) | |
3582 | { | |
04f7b24e CW |
3583 | /* We should only be called after i915_ggtt_enable_guc() */ |
3584 | GEM_BUG_ON(i915->ggtt.invalidate != guc_ggtt_invalidate); | |
3585 | ||
3586 | i915->ggtt.invalidate = gen6_ggtt_invalidate; | |
7c3f86b6 CW |
3587 | } |
3588 | ||
275a991c | 3589 | void i915_gem_restore_gtt_mappings(struct drm_i915_private *dev_priv) |
fa42331b | 3590 | { |
72e96d64 | 3591 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
fbb30a5c | 3592 | struct drm_i915_gem_object *obj, *on; |
fa42331b | 3593 | |
dc97997a | 3594 | i915_check_and_clear_faults(dev_priv); |
fa42331b DV |
3595 | |
3596 | /* First fill our portion of the GTT with scratch pages */ | |
381b943b | 3597 | ggtt->base.clear_range(&ggtt->base, 0, ggtt->base.total); |
fa42331b | 3598 | |
fbb30a5c CW |
3599 | ggtt->base.closed = true; /* skip rewriting PTE on VMA unbind */ |
3600 | ||
3601 | /* clflush objects bound into the GGTT and rebind them. */ | |
f2123818 | 3602 | list_for_each_entry_safe(obj, on, &dev_priv->mm.bound_list, mm.link) { |
fbb30a5c CW |
3603 | bool ggtt_bound = false; |
3604 | struct i915_vma *vma; | |
3605 | ||
1c7f4bca | 3606 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
72e96d64 | 3607 | if (vma->vm != &ggtt->base) |
2c3d9984 | 3608 | continue; |
fa42331b | 3609 | |
fbb30a5c CW |
3610 | if (!i915_vma_unbind(vma)) |
3611 | continue; | |
3612 | ||
2c3d9984 TU |
3613 | WARN_ON(i915_vma_bind(vma, obj->cache_level, |
3614 | PIN_UPDATE)); | |
fbb30a5c | 3615 | ggtt_bound = true; |
2c3d9984 TU |
3616 | } |
3617 | ||
fbb30a5c | 3618 | if (ggtt_bound) |
975f7ff4 | 3619 | WARN_ON(i915_gem_object_set_to_gtt_domain(obj, false)); |
2c3d9984 | 3620 | } |
fa42331b | 3621 | |
fbb30a5c CW |
3622 | ggtt->base.closed = false; |
3623 | ||
275a991c | 3624 | if (INTEL_GEN(dev_priv) >= 8) { |
4395890a | 3625 | struct intel_ppat *ppat = &dev_priv->ppat; |
fa42331b | 3626 | |
4395890a ZW |
3627 | bitmap_set(ppat->dirty, 0, ppat->max_entries); |
3628 | dev_priv->ppat.update_hw(dev_priv); | |
fa42331b DV |
3629 | return; |
3630 | } | |
3631 | ||
275a991c | 3632 | if (USES_PPGTT(dev_priv)) { |
72e96d64 JL |
3633 | struct i915_address_space *vm; |
3634 | ||
fa42331b | 3635 | list_for_each_entry(vm, &dev_priv->vm_list, global_link) { |
e5716f55 | 3636 | struct i915_hw_ppgtt *ppgtt; |
fa42331b | 3637 | |
2bfa996e | 3638 | if (i915_is_ggtt(vm)) |
fa42331b | 3639 | ppgtt = dev_priv->mm.aliasing_ppgtt; |
e5716f55 JL |
3640 | else |
3641 | ppgtt = i915_vm_to_ppgtt(vm); | |
fa42331b | 3642 | |
16a011c8 | 3643 | gen6_write_page_range(ppgtt, 0, ppgtt->base.total); |
fa42331b DV |
3644 | } |
3645 | } | |
3646 | ||
7c3f86b6 | 3647 | i915_ggtt_invalidate(dev_priv); |
fa42331b DV |
3648 | } |
3649 | ||
804beb4b | 3650 | static struct scatterlist * |
2d7f3bdb | 3651 | rotate_pages(const dma_addr_t *in, unsigned int offset, |
804beb4b | 3652 | unsigned int width, unsigned int height, |
87130255 | 3653 | unsigned int stride, |
804beb4b | 3654 | struct sg_table *st, struct scatterlist *sg) |
50470bb0 TU |
3655 | { |
3656 | unsigned int column, row; | |
3657 | unsigned int src_idx; | |
50470bb0 | 3658 | |
50470bb0 | 3659 | for (column = 0; column < width; column++) { |
87130255 | 3660 | src_idx = stride * (height - 1) + column; |
50470bb0 TU |
3661 | for (row = 0; row < height; row++) { |
3662 | st->nents++; | |
3663 | /* We don't need the pages, but need to initialize | |
3664 | * the entries so the sg list can be happily traversed. | |
3665 | * The only thing we need are DMA addresses. | |
3666 | */ | |
da1d95b6 | 3667 | sg_set_page(sg, NULL, I915_GTT_PAGE_SIZE, 0); |
804beb4b | 3668 | sg_dma_address(sg) = in[offset + src_idx]; |
da1d95b6 | 3669 | sg_dma_len(sg) = I915_GTT_PAGE_SIZE; |
50470bb0 | 3670 | sg = sg_next(sg); |
87130255 | 3671 | src_idx -= stride; |
50470bb0 TU |
3672 | } |
3673 | } | |
804beb4b TU |
3674 | |
3675 | return sg; | |
50470bb0 TU |
3676 | } |
3677 | ||
ba7a5741 CW |
3678 | static noinline struct sg_table * |
3679 | intel_rotate_pages(struct intel_rotation_info *rot_info, | |
3680 | struct drm_i915_gem_object *obj) | |
50470bb0 | 3681 | { |
da1d95b6 | 3682 | const unsigned long n_pages = obj->base.size / I915_GTT_PAGE_SIZE; |
6687c906 | 3683 | unsigned int size = intel_rotation_info_size(rot_info); |
85d1225e DG |
3684 | struct sgt_iter sgt_iter; |
3685 | dma_addr_t dma_addr; | |
50470bb0 TU |
3686 | unsigned long i; |
3687 | dma_addr_t *page_addr_list; | |
3688 | struct sg_table *st; | |
89e3e142 | 3689 | struct scatterlist *sg; |
1d00dad5 | 3690 | int ret = -ENOMEM; |
50470bb0 | 3691 | |
50470bb0 | 3692 | /* Allocate a temporary list of source pages for random access. */ |
2098105e | 3693 | page_addr_list = kvmalloc_array(n_pages, |
f2a85e19 | 3694 | sizeof(dma_addr_t), |
0ee931c4 | 3695 | GFP_KERNEL); |
50470bb0 TU |
3696 | if (!page_addr_list) |
3697 | return ERR_PTR(ret); | |
3698 | ||
3699 | /* Allocate target SG list. */ | |
3700 | st = kmalloc(sizeof(*st), GFP_KERNEL); | |
3701 | if (!st) | |
3702 | goto err_st_alloc; | |
3703 | ||
6687c906 | 3704 | ret = sg_alloc_table(st, size, GFP_KERNEL); |
50470bb0 TU |
3705 | if (ret) |
3706 | goto err_sg_alloc; | |
3707 | ||
3708 | /* Populate source page list from the object. */ | |
3709 | i = 0; | |
a4f5ea64 | 3710 | for_each_sgt_dma(dma_addr, sgt_iter, obj->mm.pages) |
85d1225e | 3711 | page_addr_list[i++] = dma_addr; |
50470bb0 | 3712 | |
85d1225e | 3713 | GEM_BUG_ON(i != n_pages); |
11f20322 VS |
3714 | st->nents = 0; |
3715 | sg = st->sgl; | |
3716 | ||
6687c906 VS |
3717 | for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++) { |
3718 | sg = rotate_pages(page_addr_list, rot_info->plane[i].offset, | |
3719 | rot_info->plane[i].width, rot_info->plane[i].height, | |
3720 | rot_info->plane[i].stride, st, sg); | |
89e3e142 TU |
3721 | } |
3722 | ||
6687c906 VS |
3723 | DRM_DEBUG_KMS("Created rotated page mapping for object size %zu (%ux%u tiles, %u pages)\n", |
3724 | obj->base.size, rot_info->plane[0].width, rot_info->plane[0].height, size); | |
50470bb0 | 3725 | |
2098105e | 3726 | kvfree(page_addr_list); |
50470bb0 TU |
3727 | |
3728 | return st; | |
3729 | ||
3730 | err_sg_alloc: | |
3731 | kfree(st); | |
3732 | err_st_alloc: | |
2098105e | 3733 | kvfree(page_addr_list); |
50470bb0 | 3734 | |
6687c906 VS |
3735 | DRM_DEBUG_KMS("Failed to create rotated mapping for object size %zu! (%ux%u tiles, %u pages)\n", |
3736 | obj->base.size, rot_info->plane[0].width, rot_info->plane[0].height, size); | |
3737 | ||
50470bb0 TU |
3738 | return ERR_PTR(ret); |
3739 | } | |
ec7adb6e | 3740 | |
ba7a5741 | 3741 | static noinline struct sg_table * |
8bd7ef16 JL |
3742 | intel_partial_pages(const struct i915_ggtt_view *view, |
3743 | struct drm_i915_gem_object *obj) | |
3744 | { | |
3745 | struct sg_table *st; | |
d2a84a76 | 3746 | struct scatterlist *sg, *iter; |
8bab1193 | 3747 | unsigned int count = view->partial.size; |
d2a84a76 | 3748 | unsigned int offset; |
8bd7ef16 JL |
3749 | int ret = -ENOMEM; |
3750 | ||
3751 | st = kmalloc(sizeof(*st), GFP_KERNEL); | |
3752 | if (!st) | |
3753 | goto err_st_alloc; | |
3754 | ||
d2a84a76 | 3755 | ret = sg_alloc_table(st, count, GFP_KERNEL); |
8bd7ef16 JL |
3756 | if (ret) |
3757 | goto err_sg_alloc; | |
3758 | ||
8bab1193 | 3759 | iter = i915_gem_object_get_sg(obj, view->partial.offset, &offset); |
d2a84a76 CW |
3760 | GEM_BUG_ON(!iter); |
3761 | ||
8bd7ef16 JL |
3762 | sg = st->sgl; |
3763 | st->nents = 0; | |
d2a84a76 CW |
3764 | do { |
3765 | unsigned int len; | |
8bd7ef16 | 3766 | |
d2a84a76 CW |
3767 | len = min(iter->length - (offset << PAGE_SHIFT), |
3768 | count << PAGE_SHIFT); | |
3769 | sg_set_page(sg, NULL, len, 0); | |
3770 | sg_dma_address(sg) = | |
3771 | sg_dma_address(iter) + (offset << PAGE_SHIFT); | |
3772 | sg_dma_len(sg) = len; | |
8bd7ef16 | 3773 | |
8bd7ef16 | 3774 | st->nents++; |
d2a84a76 CW |
3775 | count -= len >> PAGE_SHIFT; |
3776 | if (count == 0) { | |
3777 | sg_mark_end(sg); | |
3778 | return st; | |
3779 | } | |
8bd7ef16 | 3780 | |
d2a84a76 CW |
3781 | sg = __sg_next(sg); |
3782 | iter = __sg_next(iter); | |
3783 | offset = 0; | |
3784 | } while (1); | |
8bd7ef16 JL |
3785 | |
3786 | err_sg_alloc: | |
3787 | kfree(st); | |
3788 | err_st_alloc: | |
3789 | return ERR_PTR(ret); | |
3790 | } | |
3791 | ||
70b9f6f8 | 3792 | static int |
50470bb0 | 3793 | i915_get_ggtt_vma_pages(struct i915_vma *vma) |
fe14d5f4 | 3794 | { |
ba7a5741 | 3795 | int ret; |
50470bb0 | 3796 | |
2c3a3f44 CW |
3797 | /* The vma->pages are only valid within the lifespan of the borrowed |
3798 | * obj->mm.pages. When the obj->mm.pages sg_table is regenerated, so | |
3799 | * must be the vma->pages. A simple rule is that vma->pages must only | |
3800 | * be accessed when the obj->mm.pages are pinned. | |
3801 | */ | |
3802 | GEM_BUG_ON(!i915_gem_object_has_pinned_pages(vma->obj)); | |
3803 | ||
ba7a5741 CW |
3804 | switch (vma->ggtt_view.type) { |
3805 | case I915_GGTT_VIEW_NORMAL: | |
3806 | vma->pages = vma->obj->mm.pages; | |
fe14d5f4 TU |
3807 | return 0; |
3808 | ||
ba7a5741 | 3809 | case I915_GGTT_VIEW_ROTATED: |
247177dd | 3810 | vma->pages = |
ba7a5741 CW |
3811 | intel_rotate_pages(&vma->ggtt_view.rotated, vma->obj); |
3812 | break; | |
3813 | ||
3814 | case I915_GGTT_VIEW_PARTIAL: | |
247177dd | 3815 | vma->pages = intel_partial_pages(&vma->ggtt_view, vma->obj); |
ba7a5741 CW |
3816 | break; |
3817 | ||
3818 | default: | |
fe14d5f4 TU |
3819 | WARN_ONCE(1, "GGTT view %u not implemented!\n", |
3820 | vma->ggtt_view.type); | |
ba7a5741 CW |
3821 | return -EINVAL; |
3822 | } | |
fe14d5f4 | 3823 | |
ba7a5741 CW |
3824 | ret = 0; |
3825 | if (unlikely(IS_ERR(vma->pages))) { | |
247177dd CW |
3826 | ret = PTR_ERR(vma->pages); |
3827 | vma->pages = NULL; | |
50470bb0 TU |
3828 | DRM_ERROR("Failed to get pages for VMA view type %u (%d)!\n", |
3829 | vma->ggtt_view.type, ret); | |
fe14d5f4 | 3830 | } |
50470bb0 | 3831 | return ret; |
fe14d5f4 TU |
3832 | } |
3833 | ||
625d988a CW |
3834 | /** |
3835 | * i915_gem_gtt_reserve - reserve a node in an address_space (GTT) | |
a4dbf7cf CW |
3836 | * @vm: the &struct i915_address_space |
3837 | * @node: the &struct drm_mm_node (typically i915_vma.mode) | |
3838 | * @size: how much space to allocate inside the GTT, | |
3839 | * must be #I915_GTT_PAGE_SIZE aligned | |
3840 | * @offset: where to insert inside the GTT, | |
3841 | * must be #I915_GTT_MIN_ALIGNMENT aligned, and the node | |
3842 | * (@offset + @size) must fit within the address space | |
3843 | * @color: color to apply to node, if this node is not from a VMA, | |
3844 | * color must be #I915_COLOR_UNEVICTABLE | |
3845 | * @flags: control search and eviction behaviour | |
625d988a CW |
3846 | * |
3847 | * i915_gem_gtt_reserve() tries to insert the @node at the exact @offset inside | |
3848 | * the address space (using @size and @color). If the @node does not fit, it | |
3849 | * tries to evict any overlapping nodes from the GTT, including any | |
3850 | * neighbouring nodes if the colors do not match (to ensure guard pages between | |
3851 | * differing domains). See i915_gem_evict_for_node() for the gory details | |
3852 | * on the eviction algorithm. #PIN_NONBLOCK may used to prevent waiting on | |
3853 | * evicting active overlapping objects, and any overlapping node that is pinned | |
3854 | * or marked as unevictable will also result in failure. | |
3855 | * | |
3856 | * Returns: 0 on success, -ENOSPC if no suitable hole is found, -EINTR if | |
3857 | * asked to wait for eviction and interrupted. | |
3858 | */ | |
3859 | int i915_gem_gtt_reserve(struct i915_address_space *vm, | |
3860 | struct drm_mm_node *node, | |
3861 | u64 size, u64 offset, unsigned long color, | |
3862 | unsigned int flags) | |
3863 | { | |
3864 | int err; | |
3865 | ||
3866 | GEM_BUG_ON(!size); | |
3867 | GEM_BUG_ON(!IS_ALIGNED(size, I915_GTT_PAGE_SIZE)); | |
3868 | GEM_BUG_ON(!IS_ALIGNED(offset, I915_GTT_MIN_ALIGNMENT)); | |
3869 | GEM_BUG_ON(range_overflows(offset, size, vm->total)); | |
3fec7ec4 | 3870 | GEM_BUG_ON(vm == &vm->i915->mm.aliasing_ppgtt->base); |
9734ad13 | 3871 | GEM_BUG_ON(drm_mm_node_allocated(node)); |
625d988a CW |
3872 | |
3873 | node->size = size; | |
3874 | node->start = offset; | |
3875 | node->color = color; | |
3876 | ||
3877 | err = drm_mm_reserve_node(&vm->mm, node); | |
3878 | if (err != -ENOSPC) | |
3879 | return err; | |
3880 | ||
616d9cee CW |
3881 | if (flags & PIN_NOEVICT) |
3882 | return -ENOSPC; | |
3883 | ||
625d988a CW |
3884 | err = i915_gem_evict_for_node(vm, node, flags); |
3885 | if (err == 0) | |
3886 | err = drm_mm_reserve_node(&vm->mm, node); | |
3887 | ||
3888 | return err; | |
3889 | } | |
3890 | ||
606fec95 CW |
3891 | static u64 random_offset(u64 start, u64 end, u64 len, u64 align) |
3892 | { | |
3893 | u64 range, addr; | |
3894 | ||
3895 | GEM_BUG_ON(range_overflows(start, len, end)); | |
3896 | GEM_BUG_ON(round_up(start, align) > round_down(end - len, align)); | |
3897 | ||
3898 | range = round_down(end - len, align) - round_up(start, align); | |
3899 | if (range) { | |
3900 | if (sizeof(unsigned long) == sizeof(u64)) { | |
3901 | addr = get_random_long(); | |
3902 | } else { | |
3903 | addr = get_random_int(); | |
3904 | if (range > U32_MAX) { | |
3905 | addr <<= 32; | |
3906 | addr |= get_random_int(); | |
3907 | } | |
3908 | } | |
3909 | div64_u64_rem(addr, range, &addr); | |
3910 | start += addr; | |
3911 | } | |
3912 | ||
3913 | return round_up(start, align); | |
3914 | } | |
3915 | ||
e007b19d CW |
3916 | /** |
3917 | * i915_gem_gtt_insert - insert a node into an address_space (GTT) | |
a4dbf7cf CW |
3918 | * @vm: the &struct i915_address_space |
3919 | * @node: the &struct drm_mm_node (typically i915_vma.node) | |
3920 | * @size: how much space to allocate inside the GTT, | |
3921 | * must be #I915_GTT_PAGE_SIZE aligned | |
3922 | * @alignment: required alignment of starting offset, may be 0 but | |
3923 | * if specified, this must be a power-of-two and at least | |
3924 | * #I915_GTT_MIN_ALIGNMENT | |
3925 | * @color: color to apply to node | |
3926 | * @start: start of any range restriction inside GTT (0 for all), | |
e007b19d | 3927 | * must be #I915_GTT_PAGE_SIZE aligned |
a4dbf7cf CW |
3928 | * @end: end of any range restriction inside GTT (U64_MAX for all), |
3929 | * must be #I915_GTT_PAGE_SIZE aligned if not U64_MAX | |
3930 | * @flags: control search and eviction behaviour | |
e007b19d CW |
3931 | * |
3932 | * i915_gem_gtt_insert() first searches for an available hole into which | |
3933 | * is can insert the node. The hole address is aligned to @alignment and | |
3934 | * its @size must then fit entirely within the [@start, @end] bounds. The | |
3935 | * nodes on either side of the hole must match @color, or else a guard page | |
3936 | * will be inserted between the two nodes (or the node evicted). If no | |
606fec95 CW |
3937 | * suitable hole is found, first a victim is randomly selected and tested |
3938 | * for eviction, otherwise then the LRU list of objects within the GTT | |
e007b19d CW |
3939 | * is scanned to find the first set of replacement nodes to create the hole. |
3940 | * Those old overlapping nodes are evicted from the GTT (and so must be | |
3941 | * rebound before any future use). Any node that is currently pinned cannot | |
3942 | * be evicted (see i915_vma_pin()). Similar if the node's VMA is currently | |
3943 | * active and #PIN_NONBLOCK is specified, that node is also skipped when | |
3944 | * searching for an eviction candidate. See i915_gem_evict_something() for | |
3945 | * the gory details on the eviction algorithm. | |
3946 | * | |
3947 | * Returns: 0 on success, -ENOSPC if no suitable hole is found, -EINTR if | |
3948 | * asked to wait for eviction and interrupted. | |
3949 | */ | |
3950 | int i915_gem_gtt_insert(struct i915_address_space *vm, | |
3951 | struct drm_mm_node *node, | |
3952 | u64 size, u64 alignment, unsigned long color, | |
3953 | u64 start, u64 end, unsigned int flags) | |
3954 | { | |
4e64e553 | 3955 | enum drm_mm_insert_mode mode; |
606fec95 | 3956 | u64 offset; |
e007b19d CW |
3957 | int err; |
3958 | ||
3959 | lockdep_assert_held(&vm->i915->drm.struct_mutex); | |
3960 | GEM_BUG_ON(!size); | |
3961 | GEM_BUG_ON(!IS_ALIGNED(size, I915_GTT_PAGE_SIZE)); | |
3962 | GEM_BUG_ON(alignment && !is_power_of_2(alignment)); | |
3963 | GEM_BUG_ON(alignment && !IS_ALIGNED(alignment, I915_GTT_MIN_ALIGNMENT)); | |
3964 | GEM_BUG_ON(start >= end); | |
3965 | GEM_BUG_ON(start > 0 && !IS_ALIGNED(start, I915_GTT_PAGE_SIZE)); | |
3966 | GEM_BUG_ON(end < U64_MAX && !IS_ALIGNED(end, I915_GTT_PAGE_SIZE)); | |
3fec7ec4 | 3967 | GEM_BUG_ON(vm == &vm->i915->mm.aliasing_ppgtt->base); |
9734ad13 | 3968 | GEM_BUG_ON(drm_mm_node_allocated(node)); |
e007b19d CW |
3969 | |
3970 | if (unlikely(range_overflows(start, size, end))) | |
3971 | return -ENOSPC; | |
3972 | ||
3973 | if (unlikely(round_up(start, alignment) > round_down(end - size, alignment))) | |
3974 | return -ENOSPC; | |
3975 | ||
4e64e553 CW |
3976 | mode = DRM_MM_INSERT_BEST; |
3977 | if (flags & PIN_HIGH) | |
3978 | mode = DRM_MM_INSERT_HIGH; | |
3979 | if (flags & PIN_MAPPABLE) | |
3980 | mode = DRM_MM_INSERT_LOW; | |
e007b19d CW |
3981 | |
3982 | /* We only allocate in PAGE_SIZE/GTT_PAGE_SIZE (4096) chunks, | |
3983 | * so we know that we always have a minimum alignment of 4096. | |
3984 | * The drm_mm range manager is optimised to return results | |
3985 | * with zero alignment, so where possible use the optimal | |
3986 | * path. | |
3987 | */ | |
3988 | BUILD_BUG_ON(I915_GTT_MIN_ALIGNMENT > I915_GTT_PAGE_SIZE); | |
3989 | if (alignment <= I915_GTT_MIN_ALIGNMENT) | |
3990 | alignment = 0; | |
3991 | ||
4e64e553 CW |
3992 | err = drm_mm_insert_node_in_range(&vm->mm, node, |
3993 | size, alignment, color, | |
3994 | start, end, mode); | |
e007b19d CW |
3995 | if (err != -ENOSPC) |
3996 | return err; | |
3997 | ||
616d9cee CW |
3998 | if (flags & PIN_NOEVICT) |
3999 | return -ENOSPC; | |
4000 | ||
606fec95 CW |
4001 | /* No free space, pick a slot at random. |
4002 | * | |
4003 | * There is a pathological case here using a GTT shared between | |
4004 | * mmap and GPU (i.e. ggtt/aliasing_ppgtt but not full-ppgtt): | |
4005 | * | |
4006 | * |<-- 256 MiB aperture -->||<-- 1792 MiB unmappable -->| | |
4007 | * (64k objects) (448k objects) | |
4008 | * | |
4009 | * Now imagine that the eviction LRU is ordered top-down (just because | |
4010 | * pathology meets real life), and that we need to evict an object to | |
4011 | * make room inside the aperture. The eviction scan then has to walk | |
4012 | * the 448k list before it finds one within range. And now imagine that | |
4013 | * it has to search for a new hole between every byte inside the memcpy, | |
4014 | * for several simultaneous clients. | |
4015 | * | |
4016 | * On a full-ppgtt system, if we have run out of available space, there | |
4017 | * will be lots and lots of objects in the eviction list! Again, | |
4018 | * searching that LRU list may be slow if we are also applying any | |
4019 | * range restrictions (e.g. restriction to low 4GiB) and so, for | |
4020 | * simplicity and similarilty between different GTT, try the single | |
4021 | * random replacement first. | |
4022 | */ | |
4023 | offset = random_offset(start, end, | |
4024 | size, alignment ?: I915_GTT_MIN_ALIGNMENT); | |
4025 | err = i915_gem_gtt_reserve(vm, node, size, offset, color, flags); | |
4026 | if (err != -ENOSPC) | |
4027 | return err; | |
4028 | ||
4029 | /* Randomly selected placement is pinned, do a search */ | |
e007b19d CW |
4030 | err = i915_gem_evict_something(vm, size, alignment, color, |
4031 | start, end, flags); | |
4032 | if (err) | |
4033 | return err; | |
4034 | ||
4e64e553 CW |
4035 | return drm_mm_insert_node_in_range(&vm->mm, node, |
4036 | size, alignment, color, | |
4037 | start, end, DRM_MM_INSERT_EVICT); | |
e007b19d | 4038 | } |
3b5bb0a3 CW |
4039 | |
4040 | #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) | |
4041 | #include "selftests/mock_gtt.c" | |
1c42819a | 4042 | #include "selftests/i915_gem_gtt.c" |
3b5bb0a3 | 4043 | #endif |