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76aaf220 DV |
1 | /* |
2 | * Copyright © 2010 Daniel Vetter | |
c4ac524c | 3 | * Copyright © 2011-2014 Intel Corporation |
76aaf220 DV |
4 | * |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
22 | * IN THE SOFTWARE. | |
23 | * | |
24 | */ | |
25 | ||
e007b19d | 26 | #include <linux/log2.h> |
606fec95 | 27 | #include <linux/random.h> |
0e46ce2e | 28 | #include <linux/seq_file.h> |
5bab6f60 | 29 | #include <linux/stop_machine.h> |
e007b19d | 30 | |
760285e7 DH |
31 | #include <drm/drmP.h> |
32 | #include <drm/i915_drm.h> | |
e007b19d | 33 | |
76aaf220 | 34 | #include "i915_drv.h" |
5dda8fa3 | 35 | #include "i915_vgpu.h" |
76aaf220 DV |
36 | #include "i915_trace.h" |
37 | #include "intel_drv.h" | |
d07f0e59 | 38 | #include "intel_frontbuffer.h" |
76aaf220 | 39 | |
bb8f9cff CW |
40 | #define I915_GFP_DMA (GFP_KERNEL | __GFP_HIGHMEM) |
41 | ||
45f8f69a TU |
42 | /** |
43 | * DOC: Global GTT views | |
44 | * | |
45 | * Background and previous state | |
46 | * | |
47 | * Historically objects could exists (be bound) in global GTT space only as | |
48 | * singular instances with a view representing all of the object's backing pages | |
49 | * in a linear fashion. This view will be called a normal view. | |
50 | * | |
51 | * To support multiple views of the same object, where the number of mapped | |
52 | * pages is not equal to the backing store, or where the layout of the pages | |
53 | * is not linear, concept of a GGTT view was added. | |
54 | * | |
55 | * One example of an alternative view is a stereo display driven by a single | |
56 | * image. In this case we would have a framebuffer looking like this | |
57 | * (2x2 pages): | |
58 | * | |
59 | * 12 | |
60 | * 34 | |
61 | * | |
62 | * Above would represent a normal GGTT view as normally mapped for GPU or CPU | |
63 | * rendering. In contrast, fed to the display engine would be an alternative | |
64 | * view which could look something like this: | |
65 | * | |
66 | * 1212 | |
67 | * 3434 | |
68 | * | |
69 | * In this example both the size and layout of pages in the alternative view is | |
70 | * different from the normal view. | |
71 | * | |
72 | * Implementation and usage | |
73 | * | |
74 | * GGTT views are implemented using VMAs and are distinguished via enum | |
75 | * i915_ggtt_view_type and struct i915_ggtt_view. | |
76 | * | |
77 | * A new flavour of core GEM functions which work with GGTT bound objects were | |
ec7adb6e JL |
78 | * added with the _ggtt_ infix, and sometimes with _view postfix to avoid |
79 | * renaming in large amounts of code. They take the struct i915_ggtt_view | |
80 | * parameter encapsulating all metadata required to implement a view. | |
45f8f69a TU |
81 | * |
82 | * As a helper for callers which are only interested in the normal view, | |
83 | * globally const i915_ggtt_view_normal singleton instance exists. All old core | |
84 | * GEM API functions, the ones not taking the view parameter, are operating on, | |
85 | * or with the normal GGTT view. | |
86 | * | |
87 | * Code wanting to add or use a new GGTT view needs to: | |
88 | * | |
89 | * 1. Add a new enum with a suitable name. | |
90 | * 2. Extend the metadata in the i915_ggtt_view structure if required. | |
91 | * 3. Add support to i915_get_vma_pages(). | |
92 | * | |
93 | * New views are required to build a scatter-gather table from within the | |
94 | * i915_get_vma_pages function. This table is stored in the vma.ggtt_view and | |
95 | * exists for the lifetime of an VMA. | |
96 | * | |
97 | * Core API is designed to have copy semantics which means that passed in | |
98 | * struct i915_ggtt_view does not need to be persistent (left around after | |
99 | * calling the core API functions). | |
100 | * | |
101 | */ | |
102 | ||
70b9f6f8 DV |
103 | static int |
104 | i915_get_ggtt_vma_pages(struct i915_vma *vma); | |
105 | ||
7c3f86b6 CW |
106 | static void gen6_ggtt_invalidate(struct drm_i915_private *dev_priv) |
107 | { | |
108 | /* Note that as an uncached mmio write, this should flush the | |
109 | * WCB of the writes into the GGTT before it triggers the invalidate. | |
110 | */ | |
111 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
112 | } | |
113 | ||
114 | static void guc_ggtt_invalidate(struct drm_i915_private *dev_priv) | |
115 | { | |
116 | gen6_ggtt_invalidate(dev_priv); | |
117 | I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE); | |
118 | } | |
119 | ||
120 | static void gmch_ggtt_invalidate(struct drm_i915_private *dev_priv) | |
121 | { | |
122 | intel_gtt_chipset_flush(); | |
123 | } | |
124 | ||
125 | static inline void i915_ggtt_invalidate(struct drm_i915_private *i915) | |
126 | { | |
127 | i915->ggtt.invalidate(i915); | |
128 | } | |
129 | ||
c033666a CW |
130 | int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv, |
131 | int enable_ppgtt) | |
cfa7c862 | 132 | { |
1893a71b CW |
133 | bool has_aliasing_ppgtt; |
134 | bool has_full_ppgtt; | |
1f9a99e0 | 135 | bool has_full_48bit_ppgtt; |
1893a71b | 136 | |
9e1d0e60 MT |
137 | has_aliasing_ppgtt = dev_priv->info.has_aliasing_ppgtt; |
138 | has_full_ppgtt = dev_priv->info.has_full_ppgtt; | |
139 | has_full_48bit_ppgtt = dev_priv->info.has_full_48bit_ppgtt; | |
1893a71b | 140 | |
e320d400 ZW |
141 | if (intel_vgpu_active(dev_priv)) { |
142 | /* emulation is too hard */ | |
143 | has_full_ppgtt = false; | |
144 | has_full_48bit_ppgtt = false; | |
145 | } | |
71ba2d64 | 146 | |
0e4ca100 CW |
147 | if (!has_aliasing_ppgtt) |
148 | return 0; | |
149 | ||
70ee45e1 DL |
150 | /* |
151 | * We don't allow disabling PPGTT for gen9+ as it's a requirement for | |
152 | * execlists, the sole mechanism available to submit work. | |
153 | */ | |
c033666a | 154 | if (enable_ppgtt == 0 && INTEL_GEN(dev_priv) < 9) |
cfa7c862 DV |
155 | return 0; |
156 | ||
157 | if (enable_ppgtt == 1) | |
158 | return 1; | |
159 | ||
1893a71b | 160 | if (enable_ppgtt == 2 && has_full_ppgtt) |
cfa7c862 DV |
161 | return 2; |
162 | ||
1f9a99e0 MT |
163 | if (enable_ppgtt == 3 && has_full_48bit_ppgtt) |
164 | return 3; | |
165 | ||
93a25a9e DV |
166 | #ifdef CONFIG_INTEL_IOMMU |
167 | /* Disable ppgtt on SNB if VT-d is on. */ | |
c033666a | 168 | if (IS_GEN6(dev_priv) && intel_iommu_gfx_mapped) { |
93a25a9e | 169 | DRM_INFO("Disabling PPGTT because VT-d is on\n"); |
cfa7c862 | 170 | return 0; |
93a25a9e DV |
171 | } |
172 | #endif | |
173 | ||
62942ed7 | 174 | /* Early VLV doesn't have this */ |
91c8a326 | 175 | if (IS_VALLEYVIEW(dev_priv) && dev_priv->drm.pdev->revision < 0xb) { |
62942ed7 JB |
176 | DRM_DEBUG_DRIVER("disabling PPGTT on pre-B3 step VLV\n"); |
177 | return 0; | |
178 | } | |
179 | ||
e320d400 | 180 | if (INTEL_GEN(dev_priv) >= 8 && i915.enable_execlists && has_full_ppgtt) |
1f9a99e0 | 181 | return has_full_48bit_ppgtt ? 3 : 2; |
2f82bbdf MT |
182 | else |
183 | return has_aliasing_ppgtt ? 1 : 0; | |
93a25a9e DV |
184 | } |
185 | ||
70b9f6f8 DV |
186 | static int ppgtt_bind_vma(struct i915_vma *vma, |
187 | enum i915_cache_level cache_level, | |
188 | u32 unused) | |
47552659 DV |
189 | { |
190 | u32 pte_flags = 0; | |
191 | ||
a4f5ea64 | 192 | vma->pages = vma->obj->mm.pages; |
247177dd | 193 | |
47552659 DV |
194 | /* Currently applicable only to VLV */ |
195 | if (vma->obj->gt_ro) | |
196 | pte_flags |= PTE_READ_ONLY; | |
197 | ||
247177dd | 198 | vma->vm->insert_entries(vma->vm, vma->pages, vma->node.start, |
47552659 | 199 | cache_level, pte_flags); |
70b9f6f8 DV |
200 | |
201 | return 0; | |
47552659 DV |
202 | } |
203 | ||
204 | static void ppgtt_unbind_vma(struct i915_vma *vma) | |
205 | { | |
206 | vma->vm->clear_range(vma->vm, | |
207 | vma->node.start, | |
4fb84d99 | 208 | vma->size); |
47552659 | 209 | } |
6f65e29a | 210 | |
2c642b07 | 211 | static gen8_pte_t gen8_pte_encode(dma_addr_t addr, |
4fb84d99 | 212 | enum i915_cache_level level) |
94ec8f61 | 213 | { |
4fb84d99 | 214 | gen8_pte_t pte = _PAGE_PRESENT | _PAGE_RW; |
94ec8f61 | 215 | pte |= addr; |
63c42e56 BW |
216 | |
217 | switch (level) { | |
218 | case I915_CACHE_NONE: | |
fbe5d36e | 219 | pte |= PPAT_UNCACHED_INDEX; |
63c42e56 BW |
220 | break; |
221 | case I915_CACHE_WT: | |
222 | pte |= PPAT_DISPLAY_ELLC_INDEX; | |
223 | break; | |
224 | default: | |
225 | pte |= PPAT_CACHED_INDEX; | |
226 | break; | |
227 | } | |
228 | ||
94ec8f61 BW |
229 | return pte; |
230 | } | |
231 | ||
fe36f55d MK |
232 | static gen8_pde_t gen8_pde_encode(const dma_addr_t addr, |
233 | const enum i915_cache_level level) | |
b1fe6673 | 234 | { |
07749ef3 | 235 | gen8_pde_t pde = _PAGE_PRESENT | _PAGE_RW; |
b1fe6673 BW |
236 | pde |= addr; |
237 | if (level != I915_CACHE_NONE) | |
238 | pde |= PPAT_CACHED_PDE_INDEX; | |
239 | else | |
240 | pde |= PPAT_UNCACHED_INDEX; | |
241 | return pde; | |
242 | } | |
243 | ||
762d9936 MT |
244 | #define gen8_pdpe_encode gen8_pde_encode |
245 | #define gen8_pml4e_encode gen8_pde_encode | |
246 | ||
07749ef3 MT |
247 | static gen6_pte_t snb_pte_encode(dma_addr_t addr, |
248 | enum i915_cache_level level, | |
4fb84d99 | 249 | u32 unused) |
54d12527 | 250 | { |
4fb84d99 | 251 | gen6_pte_t pte = GEN6_PTE_VALID; |
54d12527 | 252 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
e7210c3c BW |
253 | |
254 | switch (level) { | |
350ec881 CW |
255 | case I915_CACHE_L3_LLC: |
256 | case I915_CACHE_LLC: | |
257 | pte |= GEN6_PTE_CACHE_LLC; | |
258 | break; | |
259 | case I915_CACHE_NONE: | |
260 | pte |= GEN6_PTE_UNCACHED; | |
261 | break; | |
262 | default: | |
5f77eeb0 | 263 | MISSING_CASE(level); |
350ec881 CW |
264 | } |
265 | ||
266 | return pte; | |
267 | } | |
268 | ||
07749ef3 MT |
269 | static gen6_pte_t ivb_pte_encode(dma_addr_t addr, |
270 | enum i915_cache_level level, | |
4fb84d99 | 271 | u32 unused) |
350ec881 | 272 | { |
4fb84d99 | 273 | gen6_pte_t pte = GEN6_PTE_VALID; |
350ec881 CW |
274 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
275 | ||
276 | switch (level) { | |
277 | case I915_CACHE_L3_LLC: | |
278 | pte |= GEN7_PTE_CACHE_L3_LLC; | |
e7210c3c BW |
279 | break; |
280 | case I915_CACHE_LLC: | |
281 | pte |= GEN6_PTE_CACHE_LLC; | |
282 | break; | |
283 | case I915_CACHE_NONE: | |
9119708c | 284 | pte |= GEN6_PTE_UNCACHED; |
e7210c3c BW |
285 | break; |
286 | default: | |
5f77eeb0 | 287 | MISSING_CASE(level); |
e7210c3c BW |
288 | } |
289 | ||
54d12527 BW |
290 | return pte; |
291 | } | |
292 | ||
07749ef3 MT |
293 | static gen6_pte_t byt_pte_encode(dma_addr_t addr, |
294 | enum i915_cache_level level, | |
4fb84d99 | 295 | u32 flags) |
93c34e70 | 296 | { |
4fb84d99 | 297 | gen6_pte_t pte = GEN6_PTE_VALID; |
93c34e70 KG |
298 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
299 | ||
24f3a8cf AG |
300 | if (!(flags & PTE_READ_ONLY)) |
301 | pte |= BYT_PTE_WRITEABLE; | |
93c34e70 KG |
302 | |
303 | if (level != I915_CACHE_NONE) | |
304 | pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES; | |
305 | ||
306 | return pte; | |
307 | } | |
308 | ||
07749ef3 MT |
309 | static gen6_pte_t hsw_pte_encode(dma_addr_t addr, |
310 | enum i915_cache_level level, | |
4fb84d99 | 311 | u32 unused) |
9119708c | 312 | { |
4fb84d99 | 313 | gen6_pte_t pte = GEN6_PTE_VALID; |
0d8ff15e | 314 | pte |= HSW_PTE_ADDR_ENCODE(addr); |
9119708c KG |
315 | |
316 | if (level != I915_CACHE_NONE) | |
87a6b688 | 317 | pte |= HSW_WB_LLC_AGE3; |
9119708c KG |
318 | |
319 | return pte; | |
320 | } | |
321 | ||
07749ef3 MT |
322 | static gen6_pte_t iris_pte_encode(dma_addr_t addr, |
323 | enum i915_cache_level level, | |
4fb84d99 | 324 | u32 unused) |
4d15c145 | 325 | { |
4fb84d99 | 326 | gen6_pte_t pte = GEN6_PTE_VALID; |
4d15c145 BW |
327 | pte |= HSW_PTE_ADDR_ENCODE(addr); |
328 | ||
651d794f CW |
329 | switch (level) { |
330 | case I915_CACHE_NONE: | |
331 | break; | |
332 | case I915_CACHE_WT: | |
c51e9701 | 333 | pte |= HSW_WT_ELLC_LLC_AGE3; |
651d794f CW |
334 | break; |
335 | default: | |
c51e9701 | 336 | pte |= HSW_WB_ELLC_LLC_AGE3; |
651d794f CW |
337 | break; |
338 | } | |
4d15c145 BW |
339 | |
340 | return pte; | |
341 | } | |
342 | ||
275a991c | 343 | static int __setup_page_dma(struct drm_i915_private *dev_priv, |
c114f76a | 344 | struct i915_page_dma *p, gfp_t flags) |
678d96fb | 345 | { |
275a991c | 346 | struct device *kdev = &dev_priv->drm.pdev->dev; |
678d96fb | 347 | |
c114f76a | 348 | p->page = alloc_page(flags); |
44159ddb MK |
349 | if (!p->page) |
350 | return -ENOMEM; | |
678d96fb | 351 | |
c49d13ee | 352 | p->daddr = dma_map_page(kdev, |
f51455d4 | 353 | p->page, 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); |
678d96fb | 354 | |
c49d13ee | 355 | if (dma_mapping_error(kdev, p->daddr)) { |
44159ddb MK |
356 | __free_page(p->page); |
357 | return -EINVAL; | |
358 | } | |
1266cdb1 MT |
359 | |
360 | return 0; | |
678d96fb BW |
361 | } |
362 | ||
275a991c TU |
363 | static int setup_page_dma(struct drm_i915_private *dev_priv, |
364 | struct i915_page_dma *p) | |
c114f76a | 365 | { |
275a991c | 366 | return __setup_page_dma(dev_priv, p, I915_GFP_DMA); |
c114f76a MK |
367 | } |
368 | ||
275a991c TU |
369 | static void cleanup_page_dma(struct drm_i915_private *dev_priv, |
370 | struct i915_page_dma *p) | |
06fda602 | 371 | { |
275a991c | 372 | struct pci_dev *pdev = dev_priv->drm.pdev; |
52a05c30 | 373 | |
44159ddb | 374 | if (WARN_ON(!p->page)) |
06fda602 | 375 | return; |
678d96fb | 376 | |
f51455d4 | 377 | dma_unmap_page(&pdev->dev, p->daddr, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); |
44159ddb MK |
378 | __free_page(p->page); |
379 | memset(p, 0, sizeof(*p)); | |
380 | } | |
381 | ||
d1c54acd | 382 | static void *kmap_page_dma(struct i915_page_dma *p) |
73eeea53 | 383 | { |
d1c54acd MK |
384 | return kmap_atomic(p->page); |
385 | } | |
73eeea53 | 386 | |
d1c54acd MK |
387 | /* We use the flushing unmap only with ppgtt structures: |
388 | * page directories, page tables and scratch pages. | |
389 | */ | |
e2d214ae | 390 | static void kunmap_page_dma(struct drm_i915_private *dev_priv, void *vaddr) |
d1c54acd | 391 | { |
73eeea53 MK |
392 | /* There are only few exceptions for gen >=6. chv and bxt. |
393 | * And we are not sure about the latter so play safe for now. | |
394 | */ | |
cc3f90f0 | 395 | if (IS_CHERRYVIEW(dev_priv) || IS_GEN9_LP(dev_priv)) |
73eeea53 MK |
396 | drm_clflush_virt_range(vaddr, PAGE_SIZE); |
397 | ||
398 | kunmap_atomic(vaddr); | |
399 | } | |
400 | ||
567047be | 401 | #define kmap_px(px) kmap_page_dma(px_base(px)) |
e2d214ae | 402 | #define kunmap_px(ppgtt, vaddr) \ |
49d73912 | 403 | kunmap_page_dma((ppgtt)->base.i915, (vaddr)) |
d1c54acd | 404 | |
275a991c TU |
405 | #define setup_px(dev_priv, px) setup_page_dma((dev_priv), px_base(px)) |
406 | #define cleanup_px(dev_priv, px) cleanup_page_dma((dev_priv), px_base(px)) | |
e2d214ae TU |
407 | #define fill_px(dev_priv, px, v) fill_page_dma((dev_priv), px_base(px), (v)) |
408 | #define fill32_px(dev_priv, px, v) \ | |
409 | fill_page_dma_32((dev_priv), px_base(px), (v)) | |
567047be | 410 | |
e2d214ae TU |
411 | static void fill_page_dma(struct drm_i915_private *dev_priv, |
412 | struct i915_page_dma *p, const uint64_t val) | |
d1c54acd MK |
413 | { |
414 | int i; | |
415 | uint64_t * const vaddr = kmap_page_dma(p); | |
416 | ||
417 | for (i = 0; i < 512; i++) | |
418 | vaddr[i] = val; | |
419 | ||
e2d214ae | 420 | kunmap_page_dma(dev_priv, vaddr); |
d1c54acd MK |
421 | } |
422 | ||
e2d214ae TU |
423 | static void fill_page_dma_32(struct drm_i915_private *dev_priv, |
424 | struct i915_page_dma *p, const uint32_t val32) | |
73eeea53 MK |
425 | { |
426 | uint64_t v = val32; | |
427 | ||
428 | v = v << 32 | val32; | |
429 | ||
e2d214ae | 430 | fill_page_dma(dev_priv, p, v); |
73eeea53 MK |
431 | } |
432 | ||
8bcdd0f7 | 433 | static int |
275a991c | 434 | setup_scratch_page(struct drm_i915_private *dev_priv, |
bb8f9cff CW |
435 | struct i915_page_dma *scratch, |
436 | gfp_t gfp) | |
4ad2af1e | 437 | { |
275a991c | 438 | return __setup_page_dma(dev_priv, scratch, gfp | __GFP_ZERO); |
4ad2af1e MK |
439 | } |
440 | ||
275a991c | 441 | static void cleanup_scratch_page(struct drm_i915_private *dev_priv, |
8bcdd0f7 | 442 | struct i915_page_dma *scratch) |
4ad2af1e | 443 | { |
275a991c | 444 | cleanup_page_dma(dev_priv, scratch); |
4ad2af1e MK |
445 | } |
446 | ||
275a991c | 447 | static struct i915_page_table *alloc_pt(struct drm_i915_private *dev_priv) |
06fda602 | 448 | { |
ec565b3c | 449 | struct i915_page_table *pt; |
275a991c | 450 | const size_t count = INTEL_GEN(dev_priv) >= 8 ? GEN8_PTES : GEN6_PTES; |
678d96fb | 451 | int ret = -ENOMEM; |
06fda602 BW |
452 | |
453 | pt = kzalloc(sizeof(*pt), GFP_KERNEL); | |
454 | if (!pt) | |
455 | return ERR_PTR(-ENOMEM); | |
456 | ||
678d96fb BW |
457 | pt->used_ptes = kcalloc(BITS_TO_LONGS(count), sizeof(*pt->used_ptes), |
458 | GFP_KERNEL); | |
459 | ||
460 | if (!pt->used_ptes) | |
461 | goto fail_bitmap; | |
462 | ||
275a991c | 463 | ret = setup_px(dev_priv, pt); |
678d96fb | 464 | if (ret) |
44159ddb | 465 | goto fail_page_m; |
06fda602 BW |
466 | |
467 | return pt; | |
678d96fb | 468 | |
44159ddb | 469 | fail_page_m: |
678d96fb BW |
470 | kfree(pt->used_ptes); |
471 | fail_bitmap: | |
472 | kfree(pt); | |
473 | ||
474 | return ERR_PTR(ret); | |
06fda602 BW |
475 | } |
476 | ||
275a991c TU |
477 | static void free_pt(struct drm_i915_private *dev_priv, |
478 | struct i915_page_table *pt) | |
06fda602 | 479 | { |
275a991c | 480 | cleanup_px(dev_priv, pt); |
2e906bea MK |
481 | kfree(pt->used_ptes); |
482 | kfree(pt); | |
483 | } | |
484 | ||
485 | static void gen8_initialize_pt(struct i915_address_space *vm, | |
486 | struct i915_page_table *pt) | |
487 | { | |
488 | gen8_pte_t scratch_pte; | |
489 | ||
8bcdd0f7 | 490 | scratch_pte = gen8_pte_encode(vm->scratch_page.daddr, |
4fb84d99 | 491 | I915_CACHE_LLC); |
2e906bea | 492 | |
49d73912 | 493 | fill_px(vm->i915, pt, scratch_pte); |
2e906bea MK |
494 | } |
495 | ||
496 | static void gen6_initialize_pt(struct i915_address_space *vm, | |
497 | struct i915_page_table *pt) | |
498 | { | |
499 | gen6_pte_t scratch_pte; | |
500 | ||
8bcdd0f7 | 501 | WARN_ON(vm->scratch_page.daddr == 0); |
2e906bea | 502 | |
8bcdd0f7 | 503 | scratch_pte = vm->pte_encode(vm->scratch_page.daddr, |
4fb84d99 | 504 | I915_CACHE_LLC, 0); |
2e906bea | 505 | |
49d73912 | 506 | fill32_px(vm->i915, pt, scratch_pte); |
06fda602 BW |
507 | } |
508 | ||
275a991c | 509 | static struct i915_page_directory *alloc_pd(struct drm_i915_private *dev_priv) |
06fda602 | 510 | { |
ec565b3c | 511 | struct i915_page_directory *pd; |
33c8819f | 512 | int ret = -ENOMEM; |
06fda602 BW |
513 | |
514 | pd = kzalloc(sizeof(*pd), GFP_KERNEL); | |
515 | if (!pd) | |
516 | return ERR_PTR(-ENOMEM); | |
517 | ||
33c8819f MT |
518 | pd->used_pdes = kcalloc(BITS_TO_LONGS(I915_PDES), |
519 | sizeof(*pd->used_pdes), GFP_KERNEL); | |
520 | if (!pd->used_pdes) | |
a08e111a | 521 | goto fail_bitmap; |
33c8819f | 522 | |
275a991c | 523 | ret = setup_px(dev_priv, pd); |
33c8819f | 524 | if (ret) |
a08e111a | 525 | goto fail_page_m; |
e5815a2e | 526 | |
06fda602 | 527 | return pd; |
33c8819f | 528 | |
a08e111a | 529 | fail_page_m: |
33c8819f | 530 | kfree(pd->used_pdes); |
a08e111a | 531 | fail_bitmap: |
33c8819f MT |
532 | kfree(pd); |
533 | ||
534 | return ERR_PTR(ret); | |
06fda602 BW |
535 | } |
536 | ||
275a991c TU |
537 | static void free_pd(struct drm_i915_private *dev_priv, |
538 | struct i915_page_directory *pd) | |
2e906bea MK |
539 | { |
540 | if (px_page(pd)) { | |
275a991c | 541 | cleanup_px(dev_priv, pd); |
2e906bea MK |
542 | kfree(pd->used_pdes); |
543 | kfree(pd); | |
544 | } | |
545 | } | |
546 | ||
547 | static void gen8_initialize_pd(struct i915_address_space *vm, | |
548 | struct i915_page_directory *pd) | |
549 | { | |
550 | gen8_pde_t scratch_pde; | |
551 | ||
552 | scratch_pde = gen8_pde_encode(px_dma(vm->scratch_pt), I915_CACHE_LLC); | |
553 | ||
49d73912 | 554 | fill_px(vm->i915, pd, scratch_pde); |
2e906bea MK |
555 | } |
556 | ||
275a991c | 557 | static int __pdp_init(struct drm_i915_private *dev_priv, |
6ac18502 MT |
558 | struct i915_page_directory_pointer *pdp) |
559 | { | |
275a991c | 560 | size_t pdpes = I915_PDPES_PER_PDP(dev_priv); |
6ac18502 MT |
561 | |
562 | pdp->used_pdpes = kcalloc(BITS_TO_LONGS(pdpes), | |
563 | sizeof(unsigned long), | |
564 | GFP_KERNEL); | |
565 | if (!pdp->used_pdpes) | |
566 | return -ENOMEM; | |
567 | ||
568 | pdp->page_directory = kcalloc(pdpes, sizeof(*pdp->page_directory), | |
569 | GFP_KERNEL); | |
570 | if (!pdp->page_directory) { | |
571 | kfree(pdp->used_pdpes); | |
572 | /* the PDP might be the statically allocated top level. Keep it | |
573 | * as clean as possible */ | |
574 | pdp->used_pdpes = NULL; | |
575 | return -ENOMEM; | |
576 | } | |
577 | ||
578 | return 0; | |
579 | } | |
580 | ||
581 | static void __pdp_fini(struct i915_page_directory_pointer *pdp) | |
582 | { | |
583 | kfree(pdp->used_pdpes); | |
584 | kfree(pdp->page_directory); | |
585 | pdp->page_directory = NULL; | |
586 | } | |
587 | ||
762d9936 | 588 | static struct |
275a991c | 589 | i915_page_directory_pointer *alloc_pdp(struct drm_i915_private *dev_priv) |
762d9936 MT |
590 | { |
591 | struct i915_page_directory_pointer *pdp; | |
592 | int ret = -ENOMEM; | |
593 | ||
275a991c | 594 | WARN_ON(!USES_FULL_48BIT_PPGTT(dev_priv)); |
762d9936 MT |
595 | |
596 | pdp = kzalloc(sizeof(*pdp), GFP_KERNEL); | |
597 | if (!pdp) | |
598 | return ERR_PTR(-ENOMEM); | |
599 | ||
275a991c | 600 | ret = __pdp_init(dev_priv, pdp); |
762d9936 MT |
601 | if (ret) |
602 | goto fail_bitmap; | |
603 | ||
275a991c | 604 | ret = setup_px(dev_priv, pdp); |
762d9936 MT |
605 | if (ret) |
606 | goto fail_page_m; | |
607 | ||
608 | return pdp; | |
609 | ||
610 | fail_page_m: | |
611 | __pdp_fini(pdp); | |
612 | fail_bitmap: | |
613 | kfree(pdp); | |
614 | ||
615 | return ERR_PTR(ret); | |
616 | } | |
617 | ||
275a991c | 618 | static void free_pdp(struct drm_i915_private *dev_priv, |
6ac18502 MT |
619 | struct i915_page_directory_pointer *pdp) |
620 | { | |
621 | __pdp_fini(pdp); | |
275a991c TU |
622 | if (USES_FULL_48BIT_PPGTT(dev_priv)) { |
623 | cleanup_px(dev_priv, pdp); | |
762d9936 MT |
624 | kfree(pdp); |
625 | } | |
626 | } | |
627 | ||
69ab76fd MT |
628 | static void gen8_initialize_pdp(struct i915_address_space *vm, |
629 | struct i915_page_directory_pointer *pdp) | |
630 | { | |
631 | gen8_ppgtt_pdpe_t scratch_pdpe; | |
632 | ||
633 | scratch_pdpe = gen8_pdpe_encode(px_dma(vm->scratch_pd), I915_CACHE_LLC); | |
634 | ||
49d73912 | 635 | fill_px(vm->i915, pdp, scratch_pdpe); |
69ab76fd MT |
636 | } |
637 | ||
638 | static void gen8_initialize_pml4(struct i915_address_space *vm, | |
639 | struct i915_pml4 *pml4) | |
640 | { | |
641 | gen8_ppgtt_pml4e_t scratch_pml4e; | |
642 | ||
643 | scratch_pml4e = gen8_pml4e_encode(px_dma(vm->scratch_pdp), | |
644 | I915_CACHE_LLC); | |
645 | ||
49d73912 | 646 | fill_px(vm->i915, pml4, scratch_pml4e); |
69ab76fd MT |
647 | } |
648 | ||
762d9936 | 649 | static void |
5c693b2b MA |
650 | gen8_setup_pdpe(struct i915_hw_ppgtt *ppgtt, |
651 | struct i915_page_directory_pointer *pdp, | |
652 | struct i915_page_directory *pd, | |
653 | int index) | |
762d9936 MT |
654 | { |
655 | gen8_ppgtt_pdpe_t *page_directorypo; | |
656 | ||
275a991c | 657 | if (!USES_FULL_48BIT_PPGTT(to_i915(ppgtt->base.dev))) |
762d9936 MT |
658 | return; |
659 | ||
660 | page_directorypo = kmap_px(pdp); | |
661 | page_directorypo[index] = gen8_pdpe_encode(px_dma(pd), I915_CACHE_LLC); | |
662 | kunmap_px(ppgtt, page_directorypo); | |
663 | } | |
664 | ||
665 | static void | |
56843107 MA |
666 | gen8_setup_pml4e(struct i915_hw_ppgtt *ppgtt, |
667 | struct i915_pml4 *pml4, | |
668 | struct i915_page_directory_pointer *pdp, | |
669 | int index) | |
762d9936 MT |
670 | { |
671 | gen8_ppgtt_pml4e_t *pagemap = kmap_px(pml4); | |
672 | ||
275a991c | 673 | WARN_ON(!USES_FULL_48BIT_PPGTT(to_i915(ppgtt->base.dev))); |
762d9936 MT |
674 | pagemap[index] = gen8_pml4e_encode(px_dma(pdp), I915_CACHE_LLC); |
675 | kunmap_px(ppgtt, pagemap); | |
6ac18502 MT |
676 | } |
677 | ||
94e409c1 | 678 | /* Broadwell Page Directory Pointer Descriptors */ |
e85b26dc | 679 | static int gen8_write_pdp(struct drm_i915_gem_request *req, |
7cb6d7ac MT |
680 | unsigned entry, |
681 | dma_addr_t addr) | |
94e409c1 | 682 | { |
7e37f889 | 683 | struct intel_ring *ring = req->ring; |
4a570db5 | 684 | struct intel_engine_cs *engine = req->engine; |
94e409c1 BW |
685 | int ret; |
686 | ||
687 | BUG_ON(entry >= 4); | |
688 | ||
5fb9de1a | 689 | ret = intel_ring_begin(req, 6); |
94e409c1 BW |
690 | if (ret) |
691 | return ret; | |
692 | ||
b5321f30 CW |
693 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); |
694 | intel_ring_emit_reg(ring, GEN8_RING_PDP_UDW(engine, entry)); | |
695 | intel_ring_emit(ring, upper_32_bits(addr)); | |
696 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
697 | intel_ring_emit_reg(ring, GEN8_RING_PDP_LDW(engine, entry)); | |
698 | intel_ring_emit(ring, lower_32_bits(addr)); | |
699 | intel_ring_advance(ring); | |
94e409c1 BW |
700 | |
701 | return 0; | |
702 | } | |
703 | ||
2dba3239 MT |
704 | static int gen8_legacy_mm_switch(struct i915_hw_ppgtt *ppgtt, |
705 | struct drm_i915_gem_request *req) | |
94e409c1 | 706 | { |
eeb9488e | 707 | int i, ret; |
94e409c1 | 708 | |
7cb6d7ac | 709 | for (i = GEN8_LEGACY_PDPES - 1; i >= 0; i--) { |
d852c7bf MK |
710 | const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i); |
711 | ||
e85b26dc | 712 | ret = gen8_write_pdp(req, i, pd_daddr); |
eeb9488e BW |
713 | if (ret) |
714 | return ret; | |
94e409c1 | 715 | } |
d595bd4b | 716 | |
eeb9488e | 717 | return 0; |
94e409c1 BW |
718 | } |
719 | ||
2dba3239 MT |
720 | static int gen8_48b_mm_switch(struct i915_hw_ppgtt *ppgtt, |
721 | struct drm_i915_gem_request *req) | |
722 | { | |
723 | return gen8_write_pdp(req, 0, px_dma(&ppgtt->pml4)); | |
724 | } | |
725 | ||
fce93755 MK |
726 | /* PDE TLBs are a pain to invalidate on GEN8+. When we modify |
727 | * the page table structures, we mark them dirty so that | |
728 | * context switching/execlist queuing code takes extra steps | |
729 | * to ensure that tlbs are flushed. | |
730 | */ | |
731 | static void mark_tlbs_dirty(struct i915_hw_ppgtt *ppgtt) | |
732 | { | |
49d73912 | 733 | ppgtt->pd_dirty_rings = INTEL_INFO(ppgtt->base.i915)->ring_mask; |
fce93755 MK |
734 | } |
735 | ||
2ce5179f MW |
736 | /* Removes entries from a single page table, releasing it if it's empty. |
737 | * Caller can use the return value to update higher-level entries. | |
738 | */ | |
739 | static bool gen8_ppgtt_clear_pt(struct i915_address_space *vm, | |
d209b9c3 MW |
740 | struct i915_page_table *pt, |
741 | uint64_t start, | |
742 | uint64_t length) | |
459108b8 | 743 | { |
e5716f55 | 744 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
d209b9c3 | 745 | unsigned int num_entries = gen8_pte_count(start, length); |
37c63934 MK |
746 | unsigned int pte = gen8_pte_index(start); |
747 | unsigned int pte_end = pte + num_entries; | |
f9b5b782 | 748 | gen8_pte_t *pt_vaddr; |
d209b9c3 MW |
749 | gen8_pte_t scratch_pte = gen8_pte_encode(vm->scratch_page.daddr, |
750 | I915_CACHE_LLC); | |
459108b8 | 751 | |
d209b9c3 | 752 | if (WARN_ON(!px_page(pt))) |
2ce5179f | 753 | return false; |
459108b8 | 754 | |
37c63934 MK |
755 | GEM_BUG_ON(pte_end > GEN8_PTES); |
756 | ||
757 | bitmap_clear(pt->used_ptes, pte, num_entries); | |
06fda602 | 758 | |
a18dbba8 | 759 | if (bitmap_empty(pt->used_ptes, GEN8_PTES)) |
2ce5179f | 760 | return true; |
2ce5179f | 761 | |
d209b9c3 MW |
762 | pt_vaddr = kmap_px(pt); |
763 | ||
37c63934 MK |
764 | while (pte < pte_end) |
765 | pt_vaddr[pte++] = scratch_pte; | |
06fda602 | 766 | |
d209b9c3 | 767 | kunmap_px(ppgtt, pt_vaddr); |
2ce5179f MW |
768 | |
769 | return false; | |
d209b9c3 | 770 | } |
06fda602 | 771 | |
2ce5179f MW |
772 | /* Removes entries from a single page dir, releasing it if it's empty. |
773 | * Caller can use the return value to update higher-level entries | |
774 | */ | |
775 | static bool gen8_ppgtt_clear_pd(struct i915_address_space *vm, | |
d209b9c3 MW |
776 | struct i915_page_directory *pd, |
777 | uint64_t start, | |
778 | uint64_t length) | |
779 | { | |
2ce5179f | 780 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
d209b9c3 MW |
781 | struct i915_page_table *pt; |
782 | uint64_t pde; | |
2ce5179f MW |
783 | gen8_pde_t *pde_vaddr; |
784 | gen8_pde_t scratch_pde = gen8_pde_encode(px_dma(vm->scratch_pt), | |
785 | I915_CACHE_LLC); | |
d209b9c3 MW |
786 | |
787 | gen8_for_each_pde(pt, pd, start, length, pde) { | |
06fda602 | 788 | if (WARN_ON(!pd->page_table[pde])) |
00245266 | 789 | break; |
06fda602 | 790 | |
2ce5179f MW |
791 | if (gen8_ppgtt_clear_pt(vm, pt, start, length)) { |
792 | __clear_bit(pde, pd->used_pdes); | |
793 | pde_vaddr = kmap_px(pd); | |
794 | pde_vaddr[pde] = scratch_pde; | |
795 | kunmap_px(ppgtt, pde_vaddr); | |
49d73912 | 796 | free_pt(vm->i915, pt); |
2ce5179f MW |
797 | } |
798 | } | |
799 | ||
a18dbba8 | 800 | if (bitmap_empty(pd->used_pdes, I915_PDES)) |
2ce5179f | 801 | return true; |
2ce5179f MW |
802 | |
803 | return false; | |
d209b9c3 | 804 | } |
06fda602 | 805 | |
2ce5179f MW |
806 | /* Removes entries from a single page dir pointer, releasing it if it's empty. |
807 | * Caller can use the return value to update higher-level entries | |
808 | */ | |
809 | static bool gen8_ppgtt_clear_pdp(struct i915_address_space *vm, | |
d209b9c3 MW |
810 | struct i915_page_directory_pointer *pdp, |
811 | uint64_t start, | |
812 | uint64_t length) | |
813 | { | |
2ce5179f | 814 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
d209b9c3 MW |
815 | struct i915_page_directory *pd; |
816 | uint64_t pdpe; | |
06fda602 | 817 | |
d209b9c3 MW |
818 | gen8_for_each_pdpe(pd, pdp, start, length, pdpe) { |
819 | if (WARN_ON(!pdp->page_directory[pdpe])) | |
820 | break; | |
459108b8 | 821 | |
2ce5179f MW |
822 | if (gen8_ppgtt_clear_pd(vm, pd, start, length)) { |
823 | __clear_bit(pdpe, pdp->used_pdpes); | |
9e65a378 | 824 | gen8_setup_pdpe(ppgtt, pdp, vm->scratch_pd, pdpe); |
49d73912 | 825 | free_pd(vm->i915, pd); |
2ce5179f MW |
826 | } |
827 | } | |
828 | ||
fce93755 MK |
829 | mark_tlbs_dirty(ppgtt); |
830 | ||
a18dbba8 | 831 | if (bitmap_empty(pdp->used_pdpes, I915_PDPES_PER_PDP(dev_priv))) |
2ce5179f | 832 | return true; |
2ce5179f MW |
833 | |
834 | return false; | |
d209b9c3 | 835 | } |
459108b8 | 836 | |
2ce5179f MW |
837 | /* Removes entries from a single pml4. |
838 | * This is the top-level structure in 4-level page tables used on gen8+. | |
839 | * Empty entries are always scratch pml4e. | |
840 | */ | |
d209b9c3 MW |
841 | static void gen8_ppgtt_clear_pml4(struct i915_address_space *vm, |
842 | struct i915_pml4 *pml4, | |
843 | uint64_t start, | |
844 | uint64_t length) | |
845 | { | |
2ce5179f | 846 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
d209b9c3 MW |
847 | struct i915_page_directory_pointer *pdp; |
848 | uint64_t pml4e; | |
2ce5179f | 849 | |
49d73912 | 850 | GEM_BUG_ON(!USES_FULL_48BIT_PPGTT(vm->i915)); |
459108b8 | 851 | |
d209b9c3 MW |
852 | gen8_for_each_pml4e(pdp, pml4, start, length, pml4e) { |
853 | if (WARN_ON(!pml4->pdps[pml4e])) | |
854 | break; | |
459108b8 | 855 | |
2ce5179f MW |
856 | if (gen8_ppgtt_clear_pdp(vm, pdp, start, length)) { |
857 | __clear_bit(pml4e, pml4->used_pml4es); | |
9e65a378 | 858 | gen8_setup_pml4e(ppgtt, pml4, vm->scratch_pdp, pml4e); |
49d73912 | 859 | free_pdp(vm->i915, pdp); |
2ce5179f | 860 | } |
459108b8 BW |
861 | } |
862 | } | |
863 | ||
f9b5b782 | 864 | static void gen8_ppgtt_clear_range(struct i915_address_space *vm, |
4fb84d99 | 865 | uint64_t start, uint64_t length) |
9df15b49 | 866 | { |
e5716f55 | 867 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
f9b5b782 | 868 | |
c6385c94 | 869 | if (USES_FULL_48BIT_PPGTT(vm->i915)) |
d209b9c3 MW |
870 | gen8_ppgtt_clear_pml4(vm, &ppgtt->pml4, start, length); |
871 | else | |
872 | gen8_ppgtt_clear_pdp(vm, &ppgtt->pdp, start, length); | |
f9b5b782 MT |
873 | } |
874 | ||
875 | static void | |
876 | gen8_ppgtt_insert_pte_entries(struct i915_address_space *vm, | |
877 | struct i915_page_directory_pointer *pdp, | |
3387d433 | 878 | struct sg_page_iter *sg_iter, |
f9b5b782 MT |
879 | uint64_t start, |
880 | enum i915_cache_level cache_level) | |
881 | { | |
e5716f55 | 882 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
07749ef3 | 883 | gen8_pte_t *pt_vaddr; |
de5ba8eb MT |
884 | unsigned pdpe = gen8_pdpe_index(start); |
885 | unsigned pde = gen8_pde_index(start); | |
886 | unsigned pte = gen8_pte_index(start); | |
9df15b49 | 887 | |
6f1cc993 | 888 | pt_vaddr = NULL; |
7ad47cf2 | 889 | |
3387d433 | 890 | while (__sg_page_iter_next(sg_iter)) { |
d7b3de91 | 891 | if (pt_vaddr == NULL) { |
d4ec9da0 | 892 | struct i915_page_directory *pd = pdp->page_directory[pdpe]; |
ec565b3c | 893 | struct i915_page_table *pt = pd->page_table[pde]; |
d1c54acd | 894 | pt_vaddr = kmap_px(pt); |
d7b3de91 | 895 | } |
9df15b49 | 896 | |
7ad47cf2 | 897 | pt_vaddr[pte] = |
3387d433 | 898 | gen8_pte_encode(sg_page_iter_dma_address(sg_iter), |
4fb84d99 | 899 | cache_level); |
07749ef3 | 900 | if (++pte == GEN8_PTES) { |
d1c54acd | 901 | kunmap_px(ppgtt, pt_vaddr); |
6f1cc993 | 902 | pt_vaddr = NULL; |
07749ef3 | 903 | if (++pde == I915_PDES) { |
c6385c94 | 904 | if (++pdpe == I915_PDPES_PER_PDP(vm->i915)) |
de5ba8eb | 905 | break; |
7ad47cf2 BW |
906 | pde = 0; |
907 | } | |
908 | pte = 0; | |
9df15b49 BW |
909 | } |
910 | } | |
d1c54acd MK |
911 | |
912 | if (pt_vaddr) | |
913 | kunmap_px(ppgtt, pt_vaddr); | |
9df15b49 BW |
914 | } |
915 | ||
f9b5b782 MT |
916 | static void gen8_ppgtt_insert_entries(struct i915_address_space *vm, |
917 | struct sg_table *pages, | |
918 | uint64_t start, | |
919 | enum i915_cache_level cache_level, | |
920 | u32 unused) | |
921 | { | |
e5716f55 | 922 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
3387d433 | 923 | struct sg_page_iter sg_iter; |
f9b5b782 | 924 | |
3387d433 | 925 | __sg_page_iter_start(&sg_iter, pages->sgl, sg_nents(pages->sgl), 0); |
de5ba8eb | 926 | |
c6385c94 | 927 | if (!USES_FULL_48BIT_PPGTT(vm->i915)) { |
de5ba8eb MT |
928 | gen8_ppgtt_insert_pte_entries(vm, &ppgtt->pdp, &sg_iter, start, |
929 | cache_level); | |
930 | } else { | |
931 | struct i915_page_directory_pointer *pdp; | |
e8ebd8e2 | 932 | uint64_t pml4e; |
de5ba8eb MT |
933 | uint64_t length = (uint64_t)pages->orig_nents << PAGE_SHIFT; |
934 | ||
e8ebd8e2 | 935 | gen8_for_each_pml4e(pdp, &ppgtt->pml4, start, length, pml4e) { |
de5ba8eb MT |
936 | gen8_ppgtt_insert_pte_entries(vm, pdp, &sg_iter, |
937 | start, cache_level); | |
938 | } | |
939 | } | |
f9b5b782 MT |
940 | } |
941 | ||
275a991c | 942 | static void gen8_free_page_tables(struct drm_i915_private *dev_priv, |
f37c0505 | 943 | struct i915_page_directory *pd) |
7ad47cf2 BW |
944 | { |
945 | int i; | |
946 | ||
567047be | 947 | if (!px_page(pd)) |
7ad47cf2 BW |
948 | return; |
949 | ||
33c8819f | 950 | for_each_set_bit(i, pd->used_pdes, I915_PDES) { |
06fda602 BW |
951 | if (WARN_ON(!pd->page_table[i])) |
952 | continue; | |
7ad47cf2 | 953 | |
275a991c | 954 | free_pt(dev_priv, pd->page_table[i]); |
06fda602 BW |
955 | pd->page_table[i] = NULL; |
956 | } | |
d7b3de91 BW |
957 | } |
958 | ||
8776f02b MK |
959 | static int gen8_init_scratch(struct i915_address_space *vm) |
960 | { | |
49d73912 | 961 | struct drm_i915_private *dev_priv = vm->i915; |
64c050db | 962 | int ret; |
8776f02b | 963 | |
275a991c | 964 | ret = setup_scratch_page(dev_priv, &vm->scratch_page, I915_GFP_DMA); |
8bcdd0f7 CW |
965 | if (ret) |
966 | return ret; | |
8776f02b | 967 | |
275a991c | 968 | vm->scratch_pt = alloc_pt(dev_priv); |
8776f02b | 969 | if (IS_ERR(vm->scratch_pt)) { |
64c050db MA |
970 | ret = PTR_ERR(vm->scratch_pt); |
971 | goto free_scratch_page; | |
8776f02b MK |
972 | } |
973 | ||
275a991c | 974 | vm->scratch_pd = alloc_pd(dev_priv); |
8776f02b | 975 | if (IS_ERR(vm->scratch_pd)) { |
64c050db MA |
976 | ret = PTR_ERR(vm->scratch_pd); |
977 | goto free_pt; | |
8776f02b MK |
978 | } |
979 | ||
275a991c TU |
980 | if (USES_FULL_48BIT_PPGTT(dev_priv)) { |
981 | vm->scratch_pdp = alloc_pdp(dev_priv); | |
69ab76fd | 982 | if (IS_ERR(vm->scratch_pdp)) { |
64c050db MA |
983 | ret = PTR_ERR(vm->scratch_pdp); |
984 | goto free_pd; | |
69ab76fd MT |
985 | } |
986 | } | |
987 | ||
8776f02b MK |
988 | gen8_initialize_pt(vm, vm->scratch_pt); |
989 | gen8_initialize_pd(vm, vm->scratch_pd); | |
275a991c | 990 | if (USES_FULL_48BIT_PPGTT(dev_priv)) |
69ab76fd | 991 | gen8_initialize_pdp(vm, vm->scratch_pdp); |
8776f02b MK |
992 | |
993 | return 0; | |
64c050db MA |
994 | |
995 | free_pd: | |
275a991c | 996 | free_pd(dev_priv, vm->scratch_pd); |
64c050db | 997 | free_pt: |
275a991c | 998 | free_pt(dev_priv, vm->scratch_pt); |
64c050db | 999 | free_scratch_page: |
275a991c | 1000 | cleanup_scratch_page(dev_priv, &vm->scratch_page); |
64c050db MA |
1001 | |
1002 | return ret; | |
8776f02b MK |
1003 | } |
1004 | ||
650da34c ZL |
1005 | static int gen8_ppgtt_notify_vgt(struct i915_hw_ppgtt *ppgtt, bool create) |
1006 | { | |
1007 | enum vgt_g2v_type msg; | |
49d73912 | 1008 | struct drm_i915_private *dev_priv = ppgtt->base.i915; |
650da34c ZL |
1009 | int i; |
1010 | ||
df28564d | 1011 | if (USES_FULL_48BIT_PPGTT(dev_priv)) { |
650da34c ZL |
1012 | u64 daddr = px_dma(&ppgtt->pml4); |
1013 | ||
ab75bb5d VS |
1014 | I915_WRITE(vgtif_reg(pdp[0].lo), lower_32_bits(daddr)); |
1015 | I915_WRITE(vgtif_reg(pdp[0].hi), upper_32_bits(daddr)); | |
650da34c ZL |
1016 | |
1017 | msg = (create ? VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE : | |
1018 | VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY); | |
1019 | } else { | |
1020 | for (i = 0; i < GEN8_LEGACY_PDPES; i++) { | |
1021 | u64 daddr = i915_page_dir_dma_addr(ppgtt, i); | |
1022 | ||
ab75bb5d VS |
1023 | I915_WRITE(vgtif_reg(pdp[i].lo), lower_32_bits(daddr)); |
1024 | I915_WRITE(vgtif_reg(pdp[i].hi), upper_32_bits(daddr)); | |
650da34c ZL |
1025 | } |
1026 | ||
1027 | msg = (create ? VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE : | |
1028 | VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY); | |
1029 | } | |
1030 | ||
1031 | I915_WRITE(vgtif_reg(g2v_notify), msg); | |
1032 | ||
1033 | return 0; | |
1034 | } | |
1035 | ||
8776f02b MK |
1036 | static void gen8_free_scratch(struct i915_address_space *vm) |
1037 | { | |
49d73912 | 1038 | struct drm_i915_private *dev_priv = vm->i915; |
8776f02b | 1039 | |
275a991c TU |
1040 | if (USES_FULL_48BIT_PPGTT(dev_priv)) |
1041 | free_pdp(dev_priv, vm->scratch_pdp); | |
1042 | free_pd(dev_priv, vm->scratch_pd); | |
1043 | free_pt(dev_priv, vm->scratch_pt); | |
1044 | cleanup_scratch_page(dev_priv, &vm->scratch_page); | |
8776f02b MK |
1045 | } |
1046 | ||
275a991c | 1047 | static void gen8_ppgtt_cleanup_3lvl(struct drm_i915_private *dev_priv, |
762d9936 | 1048 | struct i915_page_directory_pointer *pdp) |
b45a6715 BW |
1049 | { |
1050 | int i; | |
1051 | ||
275a991c | 1052 | for_each_set_bit(i, pdp->used_pdpes, I915_PDPES_PER_PDP(dev_priv)) { |
d4ec9da0 | 1053 | if (WARN_ON(!pdp->page_directory[i])) |
06fda602 BW |
1054 | continue; |
1055 | ||
275a991c TU |
1056 | gen8_free_page_tables(dev_priv, pdp->page_directory[i]); |
1057 | free_pd(dev_priv, pdp->page_directory[i]); | |
7ad47cf2 | 1058 | } |
69876bed | 1059 | |
275a991c | 1060 | free_pdp(dev_priv, pdp); |
762d9936 MT |
1061 | } |
1062 | ||
1063 | static void gen8_ppgtt_cleanup_4lvl(struct i915_hw_ppgtt *ppgtt) | |
1064 | { | |
49d73912 | 1065 | struct drm_i915_private *dev_priv = ppgtt->base.i915; |
762d9936 MT |
1066 | int i; |
1067 | ||
1068 | for_each_set_bit(i, ppgtt->pml4.used_pml4es, GEN8_PML4ES_PER_PML4) { | |
1069 | if (WARN_ON(!ppgtt->pml4.pdps[i])) | |
1070 | continue; | |
1071 | ||
275a991c | 1072 | gen8_ppgtt_cleanup_3lvl(dev_priv, ppgtt->pml4.pdps[i]); |
762d9936 MT |
1073 | } |
1074 | ||
275a991c | 1075 | cleanup_px(dev_priv, &ppgtt->pml4); |
762d9936 MT |
1076 | } |
1077 | ||
1078 | static void gen8_ppgtt_cleanup(struct i915_address_space *vm) | |
1079 | { | |
49d73912 | 1080 | struct drm_i915_private *dev_priv = vm->i915; |
e5716f55 | 1081 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
762d9936 | 1082 | |
275a991c | 1083 | if (intel_vgpu_active(dev_priv)) |
650da34c ZL |
1084 | gen8_ppgtt_notify_vgt(ppgtt, false); |
1085 | ||
275a991c TU |
1086 | if (!USES_FULL_48BIT_PPGTT(dev_priv)) |
1087 | gen8_ppgtt_cleanup_3lvl(dev_priv, &ppgtt->pdp); | |
762d9936 MT |
1088 | else |
1089 | gen8_ppgtt_cleanup_4lvl(ppgtt); | |
d4ec9da0 | 1090 | |
8776f02b | 1091 | gen8_free_scratch(vm); |
b45a6715 BW |
1092 | } |
1093 | ||
d7b2633d MT |
1094 | /** |
1095 | * gen8_ppgtt_alloc_pagetabs() - Allocate page tables for VA range. | |
d4ec9da0 MT |
1096 | * @vm: Master vm structure. |
1097 | * @pd: Page directory for this address range. | |
d7b2633d | 1098 | * @start: Starting virtual address to begin allocations. |
d4ec9da0 | 1099 | * @length: Size of the allocations. |
d7b2633d MT |
1100 | * @new_pts: Bitmap set by function with new allocations. Likely used by the |
1101 | * caller to free on error. | |
1102 | * | |
1103 | * Allocate the required number of page tables. Extremely similar to | |
1104 | * gen8_ppgtt_alloc_page_directories(). The main difference is here we are limited by | |
1105 | * the page directory boundary (instead of the page directory pointer). That | |
1106 | * boundary is 1GB virtual. Therefore, unlike gen8_ppgtt_alloc_page_directories(), it is | |
1107 | * possible, and likely that the caller will need to use multiple calls of this | |
1108 | * function to achieve the appropriate allocation. | |
1109 | * | |
1110 | * Return: 0 if success; negative error code otherwise. | |
1111 | */ | |
d4ec9da0 | 1112 | static int gen8_ppgtt_alloc_pagetabs(struct i915_address_space *vm, |
e5815a2e | 1113 | struct i915_page_directory *pd, |
5441f0cb | 1114 | uint64_t start, |
d7b2633d MT |
1115 | uint64_t length, |
1116 | unsigned long *new_pts) | |
bf2b4ed2 | 1117 | { |
49d73912 | 1118 | struct drm_i915_private *dev_priv = vm->i915; |
d7b2633d | 1119 | struct i915_page_table *pt; |
5441f0cb | 1120 | uint32_t pde; |
bf2b4ed2 | 1121 | |
e8ebd8e2 | 1122 | gen8_for_each_pde(pt, pd, start, length, pde) { |
d7b2633d | 1123 | /* Don't reallocate page tables */ |
6ac18502 | 1124 | if (test_bit(pde, pd->used_pdes)) { |
d7b2633d | 1125 | /* Scratch is never allocated this way */ |
d4ec9da0 | 1126 | WARN_ON(pt == vm->scratch_pt); |
d7b2633d MT |
1127 | continue; |
1128 | } | |
1129 | ||
275a991c | 1130 | pt = alloc_pt(dev_priv); |
d7b2633d | 1131 | if (IS_ERR(pt)) |
5441f0cb MT |
1132 | goto unwind_out; |
1133 | ||
d4ec9da0 | 1134 | gen8_initialize_pt(vm, pt); |
d7b2633d | 1135 | pd->page_table[pde] = pt; |
966082c9 | 1136 | __set_bit(pde, new_pts); |
4c06ec8d | 1137 | trace_i915_page_table_entry_alloc(vm, pde, start, GEN8_PDE_SHIFT); |
7ad47cf2 BW |
1138 | } |
1139 | ||
bf2b4ed2 | 1140 | return 0; |
7ad47cf2 BW |
1141 | |
1142 | unwind_out: | |
d7b2633d | 1143 | for_each_set_bit(pde, new_pts, I915_PDES) |
275a991c | 1144 | free_pt(dev_priv, pd->page_table[pde]); |
7ad47cf2 | 1145 | |
d7b3de91 | 1146 | return -ENOMEM; |
bf2b4ed2 BW |
1147 | } |
1148 | ||
d7b2633d MT |
1149 | /** |
1150 | * gen8_ppgtt_alloc_page_directories() - Allocate page directories for VA range. | |
d4ec9da0 | 1151 | * @vm: Master vm structure. |
d7b2633d MT |
1152 | * @pdp: Page directory pointer for this address range. |
1153 | * @start: Starting virtual address to begin allocations. | |
d4ec9da0 MT |
1154 | * @length: Size of the allocations. |
1155 | * @new_pds: Bitmap set by function with new allocations. Likely used by the | |
d7b2633d MT |
1156 | * caller to free on error. |
1157 | * | |
1158 | * Allocate the required number of page directories starting at the pde index of | |
1159 | * @start, and ending at the pde index @start + @length. This function will skip | |
1160 | * over already allocated page directories within the range, and only allocate | |
1161 | * new ones, setting the appropriate pointer within the pdp as well as the | |
1162 | * correct position in the bitmap @new_pds. | |
1163 | * | |
1164 | * The function will only allocate the pages within the range for a give page | |
1165 | * directory pointer. In other words, if @start + @length straddles a virtually | |
1166 | * addressed PDP boundary (512GB for 4k pages), there will be more allocations | |
1167 | * required by the caller, This is not currently possible, and the BUG in the | |
1168 | * code will prevent it. | |
1169 | * | |
1170 | * Return: 0 if success; negative error code otherwise. | |
1171 | */ | |
d4ec9da0 MT |
1172 | static int |
1173 | gen8_ppgtt_alloc_page_directories(struct i915_address_space *vm, | |
1174 | struct i915_page_directory_pointer *pdp, | |
1175 | uint64_t start, | |
1176 | uint64_t length, | |
1177 | unsigned long *new_pds) | |
bf2b4ed2 | 1178 | { |
49d73912 | 1179 | struct drm_i915_private *dev_priv = vm->i915; |
d7b2633d | 1180 | struct i915_page_directory *pd; |
69876bed | 1181 | uint32_t pdpe; |
275a991c | 1182 | uint32_t pdpes = I915_PDPES_PER_PDP(dev_priv); |
69876bed | 1183 | |
6ac18502 | 1184 | WARN_ON(!bitmap_empty(new_pds, pdpes)); |
d7b2633d | 1185 | |
e8ebd8e2 | 1186 | gen8_for_each_pdpe(pd, pdp, start, length, pdpe) { |
6ac18502 | 1187 | if (test_bit(pdpe, pdp->used_pdpes)) |
d7b2633d | 1188 | continue; |
33c8819f | 1189 | |
275a991c | 1190 | pd = alloc_pd(dev_priv); |
d7b2633d | 1191 | if (IS_ERR(pd)) |
d7b3de91 | 1192 | goto unwind_out; |
69876bed | 1193 | |
d4ec9da0 | 1194 | gen8_initialize_pd(vm, pd); |
d7b2633d | 1195 | pdp->page_directory[pdpe] = pd; |
966082c9 | 1196 | __set_bit(pdpe, new_pds); |
4c06ec8d | 1197 | trace_i915_page_directory_entry_alloc(vm, pdpe, start, GEN8_PDPE_SHIFT); |
d7b3de91 BW |
1198 | } |
1199 | ||
bf2b4ed2 | 1200 | return 0; |
d7b3de91 BW |
1201 | |
1202 | unwind_out: | |
6ac18502 | 1203 | for_each_set_bit(pdpe, new_pds, pdpes) |
275a991c | 1204 | free_pd(dev_priv, pdp->page_directory[pdpe]); |
d7b3de91 BW |
1205 | |
1206 | return -ENOMEM; | |
bf2b4ed2 BW |
1207 | } |
1208 | ||
762d9936 MT |
1209 | /** |
1210 | * gen8_ppgtt_alloc_page_dirpointers() - Allocate pdps for VA range. | |
1211 | * @vm: Master vm structure. | |
1212 | * @pml4: Page map level 4 for this address range. | |
1213 | * @start: Starting virtual address to begin allocations. | |
1214 | * @length: Size of the allocations. | |
1215 | * @new_pdps: Bitmap set by function with new allocations. Likely used by the | |
1216 | * caller to free on error. | |
1217 | * | |
1218 | * Allocate the required number of page directory pointers. Extremely similar to | |
1219 | * gen8_ppgtt_alloc_page_directories() and gen8_ppgtt_alloc_pagetabs(). | |
1220 | * The main difference is here we are limited by the pml4 boundary (instead of | |
1221 | * the page directory pointer). | |
1222 | * | |
1223 | * Return: 0 if success; negative error code otherwise. | |
1224 | */ | |
1225 | static int | |
1226 | gen8_ppgtt_alloc_page_dirpointers(struct i915_address_space *vm, | |
1227 | struct i915_pml4 *pml4, | |
1228 | uint64_t start, | |
1229 | uint64_t length, | |
1230 | unsigned long *new_pdps) | |
1231 | { | |
49d73912 | 1232 | struct drm_i915_private *dev_priv = vm->i915; |
762d9936 | 1233 | struct i915_page_directory_pointer *pdp; |
762d9936 MT |
1234 | uint32_t pml4e; |
1235 | ||
1236 | WARN_ON(!bitmap_empty(new_pdps, GEN8_PML4ES_PER_PML4)); | |
1237 | ||
e8ebd8e2 | 1238 | gen8_for_each_pml4e(pdp, pml4, start, length, pml4e) { |
762d9936 | 1239 | if (!test_bit(pml4e, pml4->used_pml4es)) { |
275a991c | 1240 | pdp = alloc_pdp(dev_priv); |
762d9936 MT |
1241 | if (IS_ERR(pdp)) |
1242 | goto unwind_out; | |
1243 | ||
69ab76fd | 1244 | gen8_initialize_pdp(vm, pdp); |
762d9936 MT |
1245 | pml4->pdps[pml4e] = pdp; |
1246 | __set_bit(pml4e, new_pdps); | |
1247 | trace_i915_page_directory_pointer_entry_alloc(vm, | |
1248 | pml4e, | |
1249 | start, | |
1250 | GEN8_PML4E_SHIFT); | |
1251 | } | |
1252 | } | |
1253 | ||
1254 | return 0; | |
1255 | ||
1256 | unwind_out: | |
1257 | for_each_set_bit(pml4e, new_pdps, GEN8_PML4ES_PER_PML4) | |
275a991c | 1258 | free_pdp(dev_priv, pml4->pdps[pml4e]); |
762d9936 MT |
1259 | |
1260 | return -ENOMEM; | |
1261 | } | |
1262 | ||
d7b2633d | 1263 | static void |
3a41a05d | 1264 | free_gen8_temp_bitmaps(unsigned long *new_pds, unsigned long *new_pts) |
d7b2633d | 1265 | { |
d7b2633d MT |
1266 | kfree(new_pts); |
1267 | kfree(new_pds); | |
1268 | } | |
1269 | ||
1270 | /* Fills in the page directory bitmap, and the array of page tables bitmap. Both | |
1271 | * of these are based on the number of PDPEs in the system. | |
1272 | */ | |
1273 | static | |
1274 | int __must_check alloc_gen8_temp_bitmaps(unsigned long **new_pds, | |
3a41a05d | 1275 | unsigned long **new_pts, |
6ac18502 | 1276 | uint32_t pdpes) |
d7b2633d | 1277 | { |
d7b2633d | 1278 | unsigned long *pds; |
3a41a05d | 1279 | unsigned long *pts; |
d7b2633d | 1280 | |
3a41a05d | 1281 | pds = kcalloc(BITS_TO_LONGS(pdpes), sizeof(unsigned long), GFP_TEMPORARY); |
d7b2633d MT |
1282 | if (!pds) |
1283 | return -ENOMEM; | |
1284 | ||
3a41a05d MW |
1285 | pts = kcalloc(pdpes, BITS_TO_LONGS(I915_PDES) * sizeof(unsigned long), |
1286 | GFP_TEMPORARY); | |
1287 | if (!pts) | |
1288 | goto err_out; | |
d7b2633d MT |
1289 | |
1290 | *new_pds = pds; | |
1291 | *new_pts = pts; | |
1292 | ||
1293 | return 0; | |
1294 | ||
1295 | err_out: | |
3a41a05d | 1296 | free_gen8_temp_bitmaps(pds, pts); |
d7b2633d MT |
1297 | return -ENOMEM; |
1298 | } | |
1299 | ||
762d9936 MT |
1300 | static int gen8_alloc_va_range_3lvl(struct i915_address_space *vm, |
1301 | struct i915_page_directory_pointer *pdp, | |
1302 | uint64_t start, | |
1303 | uint64_t length) | |
bf2b4ed2 | 1304 | { |
e5716f55 | 1305 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
3a41a05d | 1306 | unsigned long *new_page_dirs, *new_page_tables; |
49d73912 | 1307 | struct drm_i915_private *dev_priv = vm->i915; |
5441f0cb | 1308 | struct i915_page_directory *pd; |
33c8819f MT |
1309 | const uint64_t orig_start = start; |
1310 | const uint64_t orig_length = length; | |
5441f0cb | 1311 | uint32_t pdpe; |
275a991c | 1312 | uint32_t pdpes = I915_PDPES_PER_PDP(dev_priv); |
bf2b4ed2 BW |
1313 | int ret; |
1314 | ||
6ac18502 | 1315 | ret = alloc_gen8_temp_bitmaps(&new_page_dirs, &new_page_tables, pdpes); |
bf2b4ed2 BW |
1316 | if (ret) |
1317 | return ret; | |
1318 | ||
d7b2633d | 1319 | /* Do the allocations first so we can easily bail out */ |
d4ec9da0 MT |
1320 | ret = gen8_ppgtt_alloc_page_directories(vm, pdp, start, length, |
1321 | new_page_dirs); | |
d7b2633d | 1322 | if (ret) { |
3a41a05d | 1323 | free_gen8_temp_bitmaps(new_page_dirs, new_page_tables); |
d7b2633d MT |
1324 | return ret; |
1325 | } | |
1326 | ||
1327 | /* For every page directory referenced, allocate page tables */ | |
e8ebd8e2 | 1328 | gen8_for_each_pdpe(pd, pdp, start, length, pdpe) { |
d4ec9da0 | 1329 | ret = gen8_ppgtt_alloc_pagetabs(vm, pd, start, length, |
3a41a05d | 1330 | new_page_tables + pdpe * BITS_TO_LONGS(I915_PDES)); |
5441f0cb MT |
1331 | if (ret) |
1332 | goto err_out; | |
5441f0cb MT |
1333 | } |
1334 | ||
33c8819f MT |
1335 | start = orig_start; |
1336 | length = orig_length; | |
1337 | ||
d7b2633d MT |
1338 | /* Allocations have completed successfully, so set the bitmaps, and do |
1339 | * the mappings. */ | |
e8ebd8e2 | 1340 | gen8_for_each_pdpe(pd, pdp, start, length, pdpe) { |
d1c54acd | 1341 | gen8_pde_t *const page_directory = kmap_px(pd); |
33c8819f | 1342 | struct i915_page_table *pt; |
09120d4e | 1343 | uint64_t pd_len = length; |
33c8819f MT |
1344 | uint64_t pd_start = start; |
1345 | uint32_t pde; | |
1346 | ||
d7b2633d MT |
1347 | /* Every pd should be allocated, we just did that above. */ |
1348 | WARN_ON(!pd); | |
1349 | ||
e8ebd8e2 | 1350 | gen8_for_each_pde(pt, pd, pd_start, pd_len, pde) { |
d7b2633d MT |
1351 | /* Same reasoning as pd */ |
1352 | WARN_ON(!pt); | |
1353 | WARN_ON(!pd_len); | |
1354 | WARN_ON(!gen8_pte_count(pd_start, pd_len)); | |
1355 | ||
1356 | /* Set our used ptes within the page table */ | |
1357 | bitmap_set(pt->used_ptes, | |
1358 | gen8_pte_index(pd_start), | |
1359 | gen8_pte_count(pd_start, pd_len)); | |
1360 | ||
1361 | /* Our pde is now pointing to the pagetable, pt */ | |
966082c9 | 1362 | __set_bit(pde, pd->used_pdes); |
d7b2633d MT |
1363 | |
1364 | /* Map the PDE to the page table */ | |
fe36f55d MK |
1365 | page_directory[pde] = gen8_pde_encode(px_dma(pt), |
1366 | I915_CACHE_LLC); | |
4c06ec8d MT |
1367 | trace_i915_page_table_entry_map(&ppgtt->base, pde, pt, |
1368 | gen8_pte_index(start), | |
1369 | gen8_pte_count(start, length), | |
1370 | GEN8_PTES); | |
d7b2633d MT |
1371 | |
1372 | /* NB: We haven't yet mapped ptes to pages. At this | |
1373 | * point we're still relying on insert_entries() */ | |
33c8819f | 1374 | } |
d7b2633d | 1375 | |
d1c54acd | 1376 | kunmap_px(ppgtt, page_directory); |
d4ec9da0 | 1377 | __set_bit(pdpe, pdp->used_pdpes); |
5c693b2b | 1378 | gen8_setup_pdpe(ppgtt, pdp, pd, pdpe); |
33c8819f MT |
1379 | } |
1380 | ||
3a41a05d | 1381 | free_gen8_temp_bitmaps(new_page_dirs, new_page_tables); |
5b7e4c9c | 1382 | mark_tlbs_dirty(ppgtt); |
d7b3de91 | 1383 | return 0; |
bf2b4ed2 | 1384 | |
d7b3de91 | 1385 | err_out: |
d7b2633d | 1386 | while (pdpe--) { |
e8ebd8e2 DG |
1387 | unsigned long temp; |
1388 | ||
3a41a05d MW |
1389 | for_each_set_bit(temp, new_page_tables + pdpe * |
1390 | BITS_TO_LONGS(I915_PDES), I915_PDES) | |
275a991c TU |
1391 | free_pt(dev_priv, |
1392 | pdp->page_directory[pdpe]->page_table[temp]); | |
d7b2633d MT |
1393 | } |
1394 | ||
6ac18502 | 1395 | for_each_set_bit(pdpe, new_page_dirs, pdpes) |
275a991c | 1396 | free_pd(dev_priv, pdp->page_directory[pdpe]); |
d7b2633d | 1397 | |
3a41a05d | 1398 | free_gen8_temp_bitmaps(new_page_dirs, new_page_tables); |
5b7e4c9c | 1399 | mark_tlbs_dirty(ppgtt); |
bf2b4ed2 BW |
1400 | return ret; |
1401 | } | |
1402 | ||
762d9936 MT |
1403 | static int gen8_alloc_va_range_4lvl(struct i915_address_space *vm, |
1404 | struct i915_pml4 *pml4, | |
1405 | uint64_t start, | |
1406 | uint64_t length) | |
1407 | { | |
1408 | DECLARE_BITMAP(new_pdps, GEN8_PML4ES_PER_PML4); | |
e5716f55 | 1409 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
762d9936 | 1410 | struct i915_page_directory_pointer *pdp; |
e8ebd8e2 | 1411 | uint64_t pml4e; |
762d9936 MT |
1412 | int ret = 0; |
1413 | ||
1414 | /* Do the pml4 allocations first, so we don't need to track the newly | |
1415 | * allocated tables below the pdp */ | |
1416 | bitmap_zero(new_pdps, GEN8_PML4ES_PER_PML4); | |
1417 | ||
1418 | /* The pagedirectory and pagetable allocations are done in the shared 3 | |
1419 | * and 4 level code. Just allocate the pdps. | |
1420 | */ | |
1421 | ret = gen8_ppgtt_alloc_page_dirpointers(vm, pml4, start, length, | |
1422 | new_pdps); | |
1423 | if (ret) | |
1424 | return ret; | |
1425 | ||
e8ebd8e2 | 1426 | gen8_for_each_pml4e(pdp, pml4, start, length, pml4e) { |
762d9936 MT |
1427 | WARN_ON(!pdp); |
1428 | ||
1429 | ret = gen8_alloc_va_range_3lvl(vm, pdp, start, length); | |
1430 | if (ret) | |
1431 | goto err_out; | |
1432 | ||
56843107 | 1433 | gen8_setup_pml4e(ppgtt, pml4, pdp, pml4e); |
762d9936 MT |
1434 | } |
1435 | ||
1436 | bitmap_or(pml4->used_pml4es, new_pdps, pml4->used_pml4es, | |
1437 | GEN8_PML4ES_PER_PML4); | |
1438 | ||
1439 | return 0; | |
1440 | ||
1441 | err_out: | |
1442 | for_each_set_bit(pml4e, new_pdps, GEN8_PML4ES_PER_PML4) | |
49d73912 | 1443 | gen8_ppgtt_cleanup_3lvl(vm->i915, pml4->pdps[pml4e]); |
762d9936 MT |
1444 | |
1445 | return ret; | |
1446 | } | |
1447 | ||
1448 | static int gen8_alloc_va_range(struct i915_address_space *vm, | |
1449 | uint64_t start, uint64_t length) | |
1450 | { | |
e5716f55 | 1451 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
762d9936 | 1452 | |
c6385c94 | 1453 | if (USES_FULL_48BIT_PPGTT(vm->i915)) |
762d9936 MT |
1454 | return gen8_alloc_va_range_4lvl(vm, &ppgtt->pml4, start, length); |
1455 | else | |
1456 | return gen8_alloc_va_range_3lvl(vm, &ppgtt->pdp, start, length); | |
1457 | } | |
1458 | ||
ea91e401 MT |
1459 | static void gen8_dump_pdp(struct i915_page_directory_pointer *pdp, |
1460 | uint64_t start, uint64_t length, | |
1461 | gen8_pte_t scratch_pte, | |
1462 | struct seq_file *m) | |
1463 | { | |
1464 | struct i915_page_directory *pd; | |
ea91e401 MT |
1465 | uint32_t pdpe; |
1466 | ||
e8ebd8e2 | 1467 | gen8_for_each_pdpe(pd, pdp, start, length, pdpe) { |
ea91e401 MT |
1468 | struct i915_page_table *pt; |
1469 | uint64_t pd_len = length; | |
1470 | uint64_t pd_start = start; | |
1471 | uint32_t pde; | |
1472 | ||
1473 | if (!test_bit(pdpe, pdp->used_pdpes)) | |
1474 | continue; | |
1475 | ||
1476 | seq_printf(m, "\tPDPE #%d\n", pdpe); | |
e8ebd8e2 | 1477 | gen8_for_each_pde(pt, pd, pd_start, pd_len, pde) { |
ea91e401 MT |
1478 | uint32_t pte; |
1479 | gen8_pte_t *pt_vaddr; | |
1480 | ||
1481 | if (!test_bit(pde, pd->used_pdes)) | |
1482 | continue; | |
1483 | ||
1484 | pt_vaddr = kmap_px(pt); | |
1485 | for (pte = 0; pte < GEN8_PTES; pte += 4) { | |
1486 | uint64_t va = | |
1487 | (pdpe << GEN8_PDPE_SHIFT) | | |
1488 | (pde << GEN8_PDE_SHIFT) | | |
1489 | (pte << GEN8_PTE_SHIFT); | |
1490 | int i; | |
1491 | bool found = false; | |
1492 | ||
1493 | for (i = 0; i < 4; i++) | |
1494 | if (pt_vaddr[pte + i] != scratch_pte) | |
1495 | found = true; | |
1496 | if (!found) | |
1497 | continue; | |
1498 | ||
1499 | seq_printf(m, "\t\t0x%llx [%03d,%03d,%04d]: =", va, pdpe, pde, pte); | |
1500 | for (i = 0; i < 4; i++) { | |
1501 | if (pt_vaddr[pte + i] != scratch_pte) | |
1502 | seq_printf(m, " %llx", pt_vaddr[pte + i]); | |
1503 | else | |
1504 | seq_puts(m, " SCRATCH "); | |
1505 | } | |
1506 | seq_puts(m, "\n"); | |
1507 | } | |
1508 | /* don't use kunmap_px, it could trigger | |
1509 | * an unnecessary flush. | |
1510 | */ | |
1511 | kunmap_atomic(pt_vaddr); | |
1512 | } | |
1513 | } | |
1514 | } | |
1515 | ||
1516 | static void gen8_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m) | |
1517 | { | |
1518 | struct i915_address_space *vm = &ppgtt->base; | |
1519 | uint64_t start = ppgtt->base.start; | |
1520 | uint64_t length = ppgtt->base.total; | |
8bcdd0f7 | 1521 | gen8_pte_t scratch_pte = gen8_pte_encode(vm->scratch_page.daddr, |
4fb84d99 | 1522 | I915_CACHE_LLC); |
ea91e401 | 1523 | |
c6385c94 | 1524 | if (!USES_FULL_48BIT_PPGTT(vm->i915)) { |
ea91e401 MT |
1525 | gen8_dump_pdp(&ppgtt->pdp, start, length, scratch_pte, m); |
1526 | } else { | |
e8ebd8e2 | 1527 | uint64_t pml4e; |
ea91e401 MT |
1528 | struct i915_pml4 *pml4 = &ppgtt->pml4; |
1529 | struct i915_page_directory_pointer *pdp; | |
1530 | ||
e8ebd8e2 | 1531 | gen8_for_each_pml4e(pdp, pml4, start, length, pml4e) { |
ea91e401 MT |
1532 | if (!test_bit(pml4e, pml4->used_pml4es)) |
1533 | continue; | |
1534 | ||
1535 | seq_printf(m, " PML4E #%llu\n", pml4e); | |
1536 | gen8_dump_pdp(pdp, start, length, scratch_pte, m); | |
1537 | } | |
1538 | } | |
1539 | } | |
1540 | ||
331f38e7 ZL |
1541 | static int gen8_preallocate_top_level_pdps(struct i915_hw_ppgtt *ppgtt) |
1542 | { | |
3a41a05d | 1543 | unsigned long *new_page_dirs, *new_page_tables; |
275a991c | 1544 | uint32_t pdpes = I915_PDPES_PER_PDP(to_i915(ppgtt->base.dev)); |
331f38e7 ZL |
1545 | int ret; |
1546 | ||
1547 | /* We allocate temp bitmap for page tables for no gain | |
1548 | * but as this is for init only, lets keep the things simple | |
1549 | */ | |
1550 | ret = alloc_gen8_temp_bitmaps(&new_page_dirs, &new_page_tables, pdpes); | |
1551 | if (ret) | |
1552 | return ret; | |
1553 | ||
1554 | /* Allocate for all pdps regardless of how the ppgtt | |
1555 | * was defined. | |
1556 | */ | |
1557 | ret = gen8_ppgtt_alloc_page_directories(&ppgtt->base, &ppgtt->pdp, | |
1558 | 0, 1ULL << 32, | |
1559 | new_page_dirs); | |
1560 | if (!ret) | |
1561 | *ppgtt->pdp.used_pdpes = *new_page_dirs; | |
1562 | ||
3a41a05d | 1563 | free_gen8_temp_bitmaps(new_page_dirs, new_page_tables); |
331f38e7 ZL |
1564 | |
1565 | return ret; | |
1566 | } | |
1567 | ||
eb0b44ad | 1568 | /* |
f3a964b9 BW |
1569 | * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers |
1570 | * with a net effect resembling a 2-level page table in normal x86 terms. Each | |
1571 | * PDP represents 1GB of memory 4 * 512 * 512 * 4096 = 4GB legacy 32b address | |
1572 | * space. | |
37aca44a | 1573 | * |
f3a964b9 | 1574 | */ |
5c5f6457 | 1575 | static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt) |
37aca44a | 1576 | { |
49d73912 | 1577 | struct drm_i915_private *dev_priv = ppgtt->base.i915; |
8776f02b | 1578 | int ret; |
7cb6d7ac | 1579 | |
8776f02b MK |
1580 | ret = gen8_init_scratch(&ppgtt->base); |
1581 | if (ret) | |
1582 | return ret; | |
69876bed | 1583 | |
d7b2633d | 1584 | ppgtt->base.start = 0; |
d7b2633d | 1585 | ppgtt->base.cleanup = gen8_ppgtt_cleanup; |
5c5f6457 | 1586 | ppgtt->base.allocate_va_range = gen8_alloc_va_range; |
d7b2633d | 1587 | ppgtt->base.insert_entries = gen8_ppgtt_insert_entries; |
c7e16f22 | 1588 | ppgtt->base.clear_range = gen8_ppgtt_clear_range; |
777dc5bb DV |
1589 | ppgtt->base.unbind_vma = ppgtt_unbind_vma; |
1590 | ppgtt->base.bind_vma = ppgtt_bind_vma; | |
ea91e401 | 1591 | ppgtt->debug_dump = gen8_dump_ppgtt; |
d7b2633d | 1592 | |
275a991c TU |
1593 | if (USES_FULL_48BIT_PPGTT(dev_priv)) { |
1594 | ret = setup_px(dev_priv, &ppgtt->pml4); | |
762d9936 MT |
1595 | if (ret) |
1596 | goto free_scratch; | |
6ac18502 | 1597 | |
69ab76fd MT |
1598 | gen8_initialize_pml4(&ppgtt->base, &ppgtt->pml4); |
1599 | ||
762d9936 | 1600 | ppgtt->base.total = 1ULL << 48; |
2dba3239 | 1601 | ppgtt->switch_mm = gen8_48b_mm_switch; |
762d9936 | 1602 | } else { |
275a991c | 1603 | ret = __pdp_init(dev_priv, &ppgtt->pdp); |
81ba8aef MT |
1604 | if (ret) |
1605 | goto free_scratch; | |
1606 | ||
1607 | ppgtt->base.total = 1ULL << 32; | |
2dba3239 | 1608 | ppgtt->switch_mm = gen8_legacy_mm_switch; |
762d9936 MT |
1609 | trace_i915_page_directory_pointer_entry_alloc(&ppgtt->base, |
1610 | 0, 0, | |
1611 | GEN8_PML4E_SHIFT); | |
331f38e7 | 1612 | |
275a991c | 1613 | if (intel_vgpu_active(dev_priv)) { |
331f38e7 ZL |
1614 | ret = gen8_preallocate_top_level_pdps(ppgtt); |
1615 | if (ret) | |
1616 | goto free_scratch; | |
1617 | } | |
81ba8aef | 1618 | } |
6ac18502 | 1619 | |
275a991c | 1620 | if (intel_vgpu_active(dev_priv)) |
650da34c ZL |
1621 | gen8_ppgtt_notify_vgt(ppgtt, true); |
1622 | ||
d7b2633d | 1623 | return 0; |
6ac18502 MT |
1624 | |
1625 | free_scratch: | |
1626 | gen8_free_scratch(&ppgtt->base); | |
1627 | return ret; | |
d7b2633d MT |
1628 | } |
1629 | ||
87d60b63 BW |
1630 | static void gen6_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m) |
1631 | { | |
87d60b63 | 1632 | struct i915_address_space *vm = &ppgtt->base; |
09942c65 | 1633 | struct i915_page_table *unused; |
07749ef3 | 1634 | gen6_pte_t scratch_pte; |
87d60b63 | 1635 | uint32_t pd_entry; |
731f74c5 | 1636 | uint32_t pte, pde; |
09942c65 | 1637 | uint32_t start = ppgtt->base.start, length = ppgtt->base.total; |
87d60b63 | 1638 | |
8bcdd0f7 | 1639 | scratch_pte = vm->pte_encode(vm->scratch_page.daddr, |
4fb84d99 | 1640 | I915_CACHE_LLC, 0); |
87d60b63 | 1641 | |
731f74c5 | 1642 | gen6_for_each_pde(unused, &ppgtt->pd, start, length, pde) { |
87d60b63 | 1643 | u32 expected; |
07749ef3 | 1644 | gen6_pte_t *pt_vaddr; |
567047be | 1645 | const dma_addr_t pt_addr = px_dma(ppgtt->pd.page_table[pde]); |
09942c65 | 1646 | pd_entry = readl(ppgtt->pd_addr + pde); |
87d60b63 BW |
1647 | expected = (GEN6_PDE_ADDR_ENCODE(pt_addr) | GEN6_PDE_VALID); |
1648 | ||
1649 | if (pd_entry != expected) | |
1650 | seq_printf(m, "\tPDE #%d mismatch: Actual PDE: %x Expected PDE: %x\n", | |
1651 | pde, | |
1652 | pd_entry, | |
1653 | expected); | |
1654 | seq_printf(m, "\tPDE: %x\n", pd_entry); | |
1655 | ||
d1c54acd MK |
1656 | pt_vaddr = kmap_px(ppgtt->pd.page_table[pde]); |
1657 | ||
07749ef3 | 1658 | for (pte = 0; pte < GEN6_PTES; pte+=4) { |
87d60b63 | 1659 | unsigned long va = |
07749ef3 | 1660 | (pde * PAGE_SIZE * GEN6_PTES) + |
87d60b63 BW |
1661 | (pte * PAGE_SIZE); |
1662 | int i; | |
1663 | bool found = false; | |
1664 | for (i = 0; i < 4; i++) | |
1665 | if (pt_vaddr[pte + i] != scratch_pte) | |
1666 | found = true; | |
1667 | if (!found) | |
1668 | continue; | |
1669 | ||
1670 | seq_printf(m, "\t\t0x%lx [%03d,%04d]: =", va, pde, pte); | |
1671 | for (i = 0; i < 4; i++) { | |
1672 | if (pt_vaddr[pte + i] != scratch_pte) | |
1673 | seq_printf(m, " %08x", pt_vaddr[pte + i]); | |
1674 | else | |
1675 | seq_puts(m, " SCRATCH "); | |
1676 | } | |
1677 | seq_puts(m, "\n"); | |
1678 | } | |
d1c54acd | 1679 | kunmap_px(ppgtt, pt_vaddr); |
87d60b63 BW |
1680 | } |
1681 | } | |
1682 | ||
678d96fb | 1683 | /* Write pde (index) from the page directory @pd to the page table @pt */ |
ec565b3c MT |
1684 | static void gen6_write_pde(struct i915_page_directory *pd, |
1685 | const int pde, struct i915_page_table *pt) | |
6197349b | 1686 | { |
678d96fb BW |
1687 | /* Caller needs to make sure the write completes if necessary */ |
1688 | struct i915_hw_ppgtt *ppgtt = | |
1689 | container_of(pd, struct i915_hw_ppgtt, pd); | |
1690 | u32 pd_entry; | |
6197349b | 1691 | |
567047be | 1692 | pd_entry = GEN6_PDE_ADDR_ENCODE(px_dma(pt)); |
678d96fb | 1693 | pd_entry |= GEN6_PDE_VALID; |
6197349b | 1694 | |
678d96fb BW |
1695 | writel(pd_entry, ppgtt->pd_addr + pde); |
1696 | } | |
6197349b | 1697 | |
678d96fb BW |
1698 | /* Write all the page tables found in the ppgtt structure to incrementing page |
1699 | * directories. */ | |
1700 | static void gen6_write_page_range(struct drm_i915_private *dev_priv, | |
ec565b3c | 1701 | struct i915_page_directory *pd, |
678d96fb BW |
1702 | uint32_t start, uint32_t length) |
1703 | { | |
72e96d64 | 1704 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
ec565b3c | 1705 | struct i915_page_table *pt; |
731f74c5 | 1706 | uint32_t pde; |
678d96fb | 1707 | |
731f74c5 | 1708 | gen6_for_each_pde(pt, pd, start, length, pde) |
678d96fb BW |
1709 | gen6_write_pde(pd, pde, pt); |
1710 | ||
1711 | /* Make sure write is complete before other code can use this page | |
1712 | * table. Also require for WC mapped PTEs */ | |
72e96d64 | 1713 | readl(ggtt->gsm); |
3e302542 BW |
1714 | } |
1715 | ||
b4a74e3a | 1716 | static uint32_t get_pd_offset(struct i915_hw_ppgtt *ppgtt) |
3e302542 | 1717 | { |
44159ddb | 1718 | BUG_ON(ppgtt->pd.base.ggtt_offset & 0x3f); |
b4a74e3a | 1719 | |
44159ddb | 1720 | return (ppgtt->pd.base.ggtt_offset / 64) << 16; |
b4a74e3a BW |
1721 | } |
1722 | ||
90252e5c | 1723 | static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt, |
e85b26dc | 1724 | struct drm_i915_gem_request *req) |
90252e5c | 1725 | { |
7e37f889 | 1726 | struct intel_ring *ring = req->ring; |
4a570db5 | 1727 | struct intel_engine_cs *engine = req->engine; |
90252e5c BW |
1728 | int ret; |
1729 | ||
90252e5c | 1730 | /* NB: TLBs must be flushed and invalidated before a switch */ |
7c9cf4e3 | 1731 | ret = engine->emit_flush(req, EMIT_INVALIDATE | EMIT_FLUSH); |
90252e5c BW |
1732 | if (ret) |
1733 | return ret; | |
1734 | ||
5fb9de1a | 1735 | ret = intel_ring_begin(req, 6); |
90252e5c BW |
1736 | if (ret) |
1737 | return ret; | |
1738 | ||
b5321f30 CW |
1739 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2)); |
1740 | intel_ring_emit_reg(ring, RING_PP_DIR_DCLV(engine)); | |
1741 | intel_ring_emit(ring, PP_DIR_DCLV_2G); | |
1742 | intel_ring_emit_reg(ring, RING_PP_DIR_BASE(engine)); | |
1743 | intel_ring_emit(ring, get_pd_offset(ppgtt)); | |
1744 | intel_ring_emit(ring, MI_NOOP); | |
1745 | intel_ring_advance(ring); | |
90252e5c BW |
1746 | |
1747 | return 0; | |
1748 | } | |
1749 | ||
48a10389 | 1750 | static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt, |
e85b26dc | 1751 | struct drm_i915_gem_request *req) |
48a10389 | 1752 | { |
7e37f889 | 1753 | struct intel_ring *ring = req->ring; |
4a570db5 | 1754 | struct intel_engine_cs *engine = req->engine; |
48a10389 BW |
1755 | int ret; |
1756 | ||
48a10389 | 1757 | /* NB: TLBs must be flushed and invalidated before a switch */ |
7c9cf4e3 | 1758 | ret = engine->emit_flush(req, EMIT_INVALIDATE | EMIT_FLUSH); |
48a10389 BW |
1759 | if (ret) |
1760 | return ret; | |
1761 | ||
5fb9de1a | 1762 | ret = intel_ring_begin(req, 6); |
48a10389 BW |
1763 | if (ret) |
1764 | return ret; | |
1765 | ||
b5321f30 CW |
1766 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2)); |
1767 | intel_ring_emit_reg(ring, RING_PP_DIR_DCLV(engine)); | |
1768 | intel_ring_emit(ring, PP_DIR_DCLV_2G); | |
1769 | intel_ring_emit_reg(ring, RING_PP_DIR_BASE(engine)); | |
1770 | intel_ring_emit(ring, get_pd_offset(ppgtt)); | |
1771 | intel_ring_emit(ring, MI_NOOP); | |
1772 | intel_ring_advance(ring); | |
48a10389 | 1773 | |
90252e5c | 1774 | /* XXX: RCS is the only one to auto invalidate the TLBs? */ |
e2f80391 | 1775 | if (engine->id != RCS) { |
7c9cf4e3 | 1776 | ret = engine->emit_flush(req, EMIT_INVALIDATE | EMIT_FLUSH); |
90252e5c BW |
1777 | if (ret) |
1778 | return ret; | |
1779 | } | |
1780 | ||
48a10389 BW |
1781 | return 0; |
1782 | } | |
1783 | ||
eeb9488e | 1784 | static int gen6_mm_switch(struct i915_hw_ppgtt *ppgtt, |
e85b26dc | 1785 | struct drm_i915_gem_request *req) |
eeb9488e | 1786 | { |
4a570db5 | 1787 | struct intel_engine_cs *engine = req->engine; |
8eb95204 | 1788 | struct drm_i915_private *dev_priv = req->i915; |
48a10389 | 1789 | |
e2f80391 TU |
1790 | I915_WRITE(RING_PP_DIR_DCLV(engine), PP_DIR_DCLV_2G); |
1791 | I915_WRITE(RING_PP_DIR_BASE(engine), get_pd_offset(ppgtt)); | |
eeb9488e BW |
1792 | return 0; |
1793 | } | |
1794 | ||
c6be607a | 1795 | static void gen8_ppgtt_enable(struct drm_i915_private *dev_priv) |
eeb9488e | 1796 | { |
e2f80391 | 1797 | struct intel_engine_cs *engine; |
3b3f1650 | 1798 | enum intel_engine_id id; |
3e302542 | 1799 | |
3b3f1650 | 1800 | for_each_engine(engine, dev_priv, id) { |
c6be607a TU |
1801 | u32 four_level = USES_FULL_48BIT_PPGTT(dev_priv) ? |
1802 | GEN8_GFX_PPGTT_48B : 0; | |
e2f80391 | 1803 | I915_WRITE(RING_MODE_GEN7(engine), |
2dba3239 | 1804 | _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE | four_level)); |
eeb9488e | 1805 | } |
eeb9488e | 1806 | } |
6197349b | 1807 | |
c6be607a | 1808 | static void gen7_ppgtt_enable(struct drm_i915_private *dev_priv) |
3e302542 | 1809 | { |
e2f80391 | 1810 | struct intel_engine_cs *engine; |
b4a74e3a | 1811 | uint32_t ecochk, ecobits; |
3b3f1650 | 1812 | enum intel_engine_id id; |
6197349b | 1813 | |
b4a74e3a BW |
1814 | ecobits = I915_READ(GAC_ECO_BITS); |
1815 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B); | |
a65c2fcd | 1816 | |
b4a74e3a | 1817 | ecochk = I915_READ(GAM_ECOCHK); |
772c2a51 | 1818 | if (IS_HASWELL(dev_priv)) { |
b4a74e3a BW |
1819 | ecochk |= ECOCHK_PPGTT_WB_HSW; |
1820 | } else { | |
1821 | ecochk |= ECOCHK_PPGTT_LLC_IVB; | |
1822 | ecochk &= ~ECOCHK_PPGTT_GFDT_IVB; | |
1823 | } | |
1824 | I915_WRITE(GAM_ECOCHK, ecochk); | |
a65c2fcd | 1825 | |
3b3f1650 | 1826 | for_each_engine(engine, dev_priv, id) { |
6197349b | 1827 | /* GFX_MODE is per-ring on gen7+ */ |
e2f80391 | 1828 | I915_WRITE(RING_MODE_GEN7(engine), |
b4a74e3a | 1829 | _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); |
6197349b | 1830 | } |
b4a74e3a | 1831 | } |
6197349b | 1832 | |
c6be607a | 1833 | static void gen6_ppgtt_enable(struct drm_i915_private *dev_priv) |
b4a74e3a | 1834 | { |
b4a74e3a | 1835 | uint32_t ecochk, gab_ctl, ecobits; |
a65c2fcd | 1836 | |
b4a74e3a BW |
1837 | ecobits = I915_READ(GAC_ECO_BITS); |
1838 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT | | |
1839 | ECOBITS_PPGTT_CACHE64B); | |
6197349b | 1840 | |
b4a74e3a BW |
1841 | gab_ctl = I915_READ(GAB_CTL); |
1842 | I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT); | |
1843 | ||
1844 | ecochk = I915_READ(GAM_ECOCHK); | |
1845 | I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B); | |
1846 | ||
1847 | I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
6197349b BW |
1848 | } |
1849 | ||
1d2a314c | 1850 | /* PPGTT support for Sandybdrige/Gen6 and later */ |
853ba5d2 | 1851 | static void gen6_ppgtt_clear_range(struct i915_address_space *vm, |
782f1495 | 1852 | uint64_t start, |
4fb84d99 | 1853 | uint64_t length) |
1d2a314c | 1854 | { |
e5716f55 | 1855 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
07749ef3 | 1856 | gen6_pte_t *pt_vaddr, scratch_pte; |
782f1495 BW |
1857 | unsigned first_entry = start >> PAGE_SHIFT; |
1858 | unsigned num_entries = length >> PAGE_SHIFT; | |
07749ef3 MT |
1859 | unsigned act_pt = first_entry / GEN6_PTES; |
1860 | unsigned first_pte = first_entry % GEN6_PTES; | |
7bddb01f | 1861 | unsigned last_pte, i; |
1d2a314c | 1862 | |
8bcdd0f7 | 1863 | scratch_pte = vm->pte_encode(vm->scratch_page.daddr, |
4fb84d99 | 1864 | I915_CACHE_LLC, 0); |
1d2a314c | 1865 | |
7bddb01f DV |
1866 | while (num_entries) { |
1867 | last_pte = first_pte + num_entries; | |
07749ef3 MT |
1868 | if (last_pte > GEN6_PTES) |
1869 | last_pte = GEN6_PTES; | |
7bddb01f | 1870 | |
d1c54acd | 1871 | pt_vaddr = kmap_px(ppgtt->pd.page_table[act_pt]); |
1d2a314c | 1872 | |
7bddb01f DV |
1873 | for (i = first_pte; i < last_pte; i++) |
1874 | pt_vaddr[i] = scratch_pte; | |
1d2a314c | 1875 | |
d1c54acd | 1876 | kunmap_px(ppgtt, pt_vaddr); |
1d2a314c | 1877 | |
7bddb01f DV |
1878 | num_entries -= last_pte - first_pte; |
1879 | first_pte = 0; | |
a15326a5 | 1880 | act_pt++; |
7bddb01f | 1881 | } |
1d2a314c DV |
1882 | } |
1883 | ||
853ba5d2 | 1884 | static void gen6_ppgtt_insert_entries(struct i915_address_space *vm, |
def886c3 | 1885 | struct sg_table *pages, |
782f1495 | 1886 | uint64_t start, |
24f3a8cf | 1887 | enum i915_cache_level cache_level, u32 flags) |
def886c3 | 1888 | { |
e5716f55 | 1889 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
782f1495 | 1890 | unsigned first_entry = start >> PAGE_SHIFT; |
07749ef3 MT |
1891 | unsigned act_pt = first_entry / GEN6_PTES; |
1892 | unsigned act_pte = first_entry % GEN6_PTES; | |
85d1225e DG |
1893 | gen6_pte_t *pt_vaddr = NULL; |
1894 | struct sgt_iter sgt_iter; | |
1895 | dma_addr_t addr; | |
6e995e23 | 1896 | |
85d1225e | 1897 | for_each_sgt_dma(addr, sgt_iter, pages) { |
cc79714f | 1898 | if (pt_vaddr == NULL) |
d1c54acd | 1899 | pt_vaddr = kmap_px(ppgtt->pd.page_table[act_pt]); |
6e995e23 | 1900 | |
cc79714f | 1901 | pt_vaddr[act_pte] = |
4fb84d99 | 1902 | vm->pte_encode(addr, cache_level, flags); |
24f3a8cf | 1903 | |
07749ef3 | 1904 | if (++act_pte == GEN6_PTES) { |
d1c54acd | 1905 | kunmap_px(ppgtt, pt_vaddr); |
cc79714f | 1906 | pt_vaddr = NULL; |
a15326a5 | 1907 | act_pt++; |
6e995e23 | 1908 | act_pte = 0; |
def886c3 | 1909 | } |
def886c3 | 1910 | } |
85d1225e | 1911 | |
cc79714f | 1912 | if (pt_vaddr) |
d1c54acd | 1913 | kunmap_px(ppgtt, pt_vaddr); |
def886c3 DV |
1914 | } |
1915 | ||
678d96fb | 1916 | static int gen6_alloc_va_range(struct i915_address_space *vm, |
a05d80ee | 1917 | uint64_t start_in, uint64_t length_in) |
678d96fb | 1918 | { |
4933d519 | 1919 | DECLARE_BITMAP(new_page_tables, I915_PDES); |
49d73912 | 1920 | struct drm_i915_private *dev_priv = vm->i915; |
72e96d64 | 1921 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
e5716f55 | 1922 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
ec565b3c | 1923 | struct i915_page_table *pt; |
a05d80ee | 1924 | uint32_t start, length, start_save, length_save; |
731f74c5 | 1925 | uint32_t pde; |
4933d519 MT |
1926 | int ret; |
1927 | ||
a05d80ee MK |
1928 | start = start_save = start_in; |
1929 | length = length_save = length_in; | |
4933d519 MT |
1930 | |
1931 | bitmap_zero(new_page_tables, I915_PDES); | |
1932 | ||
1933 | /* The allocation is done in two stages so that we can bail out with | |
1934 | * minimal amount of pain. The first stage finds new page tables that | |
1935 | * need allocation. The second stage marks use ptes within the page | |
1936 | * tables. | |
1937 | */ | |
731f74c5 | 1938 | gen6_for_each_pde(pt, &ppgtt->pd, start, length, pde) { |
79ab9370 | 1939 | if (pt != vm->scratch_pt) { |
4933d519 MT |
1940 | WARN_ON(bitmap_empty(pt->used_ptes, GEN6_PTES)); |
1941 | continue; | |
1942 | } | |
1943 | ||
1944 | /* We've already allocated a page table */ | |
1945 | WARN_ON(!bitmap_empty(pt->used_ptes, GEN6_PTES)); | |
1946 | ||
275a991c | 1947 | pt = alloc_pt(dev_priv); |
4933d519 MT |
1948 | if (IS_ERR(pt)) { |
1949 | ret = PTR_ERR(pt); | |
1950 | goto unwind_out; | |
1951 | } | |
1952 | ||
1953 | gen6_initialize_pt(vm, pt); | |
1954 | ||
1955 | ppgtt->pd.page_table[pde] = pt; | |
966082c9 | 1956 | __set_bit(pde, new_page_tables); |
72744cb1 | 1957 | trace_i915_page_table_entry_alloc(vm, pde, start, GEN6_PDE_SHIFT); |
4933d519 MT |
1958 | } |
1959 | ||
1960 | start = start_save; | |
1961 | length = length_save; | |
678d96fb | 1962 | |
731f74c5 | 1963 | gen6_for_each_pde(pt, &ppgtt->pd, start, length, pde) { |
678d96fb BW |
1964 | DECLARE_BITMAP(tmp_bitmap, GEN6_PTES); |
1965 | ||
1966 | bitmap_zero(tmp_bitmap, GEN6_PTES); | |
1967 | bitmap_set(tmp_bitmap, gen6_pte_index(start), | |
1968 | gen6_pte_count(start, length)); | |
1969 | ||
966082c9 | 1970 | if (__test_and_clear_bit(pde, new_page_tables)) |
4933d519 MT |
1971 | gen6_write_pde(&ppgtt->pd, pde, pt); |
1972 | ||
72744cb1 MT |
1973 | trace_i915_page_table_entry_map(vm, pde, pt, |
1974 | gen6_pte_index(start), | |
1975 | gen6_pte_count(start, length), | |
1976 | GEN6_PTES); | |
4933d519 | 1977 | bitmap_or(pt->used_ptes, tmp_bitmap, pt->used_ptes, |
678d96fb BW |
1978 | GEN6_PTES); |
1979 | } | |
1980 | ||
4933d519 MT |
1981 | WARN_ON(!bitmap_empty(new_page_tables, I915_PDES)); |
1982 | ||
1983 | /* Make sure write is complete before other code can use this page | |
1984 | * table. Also require for WC mapped PTEs */ | |
72e96d64 | 1985 | readl(ggtt->gsm); |
4933d519 | 1986 | |
563222a7 | 1987 | mark_tlbs_dirty(ppgtt); |
678d96fb | 1988 | return 0; |
4933d519 MT |
1989 | |
1990 | unwind_out: | |
1991 | for_each_set_bit(pde, new_page_tables, I915_PDES) { | |
ec565b3c | 1992 | struct i915_page_table *pt = ppgtt->pd.page_table[pde]; |
4933d519 | 1993 | |
79ab9370 | 1994 | ppgtt->pd.page_table[pde] = vm->scratch_pt; |
275a991c | 1995 | free_pt(dev_priv, pt); |
4933d519 MT |
1996 | } |
1997 | ||
1998 | mark_tlbs_dirty(ppgtt); | |
1999 | return ret; | |
678d96fb BW |
2000 | } |
2001 | ||
8776f02b MK |
2002 | static int gen6_init_scratch(struct i915_address_space *vm) |
2003 | { | |
49d73912 | 2004 | struct drm_i915_private *dev_priv = vm->i915; |
8bcdd0f7 | 2005 | int ret; |
8776f02b | 2006 | |
275a991c | 2007 | ret = setup_scratch_page(dev_priv, &vm->scratch_page, I915_GFP_DMA); |
8bcdd0f7 CW |
2008 | if (ret) |
2009 | return ret; | |
8776f02b | 2010 | |
275a991c | 2011 | vm->scratch_pt = alloc_pt(dev_priv); |
8776f02b | 2012 | if (IS_ERR(vm->scratch_pt)) { |
275a991c | 2013 | cleanup_scratch_page(dev_priv, &vm->scratch_page); |
8776f02b MK |
2014 | return PTR_ERR(vm->scratch_pt); |
2015 | } | |
2016 | ||
2017 | gen6_initialize_pt(vm, vm->scratch_pt); | |
2018 | ||
2019 | return 0; | |
2020 | } | |
2021 | ||
2022 | static void gen6_free_scratch(struct i915_address_space *vm) | |
2023 | { | |
49d73912 | 2024 | struct drm_i915_private *dev_priv = vm->i915; |
8776f02b | 2025 | |
275a991c TU |
2026 | free_pt(dev_priv, vm->scratch_pt); |
2027 | cleanup_scratch_page(dev_priv, &vm->scratch_page); | |
8776f02b MK |
2028 | } |
2029 | ||
061dd493 | 2030 | static void gen6_ppgtt_cleanup(struct i915_address_space *vm) |
a00d825d | 2031 | { |
e5716f55 | 2032 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
731f74c5 | 2033 | struct i915_page_directory *pd = &ppgtt->pd; |
49d73912 | 2034 | struct drm_i915_private *dev_priv = vm->i915; |
09942c65 MT |
2035 | struct i915_page_table *pt; |
2036 | uint32_t pde; | |
4933d519 | 2037 | |
061dd493 DV |
2038 | drm_mm_remove_node(&ppgtt->node); |
2039 | ||
731f74c5 | 2040 | gen6_for_all_pdes(pt, pd, pde) |
79ab9370 | 2041 | if (pt != vm->scratch_pt) |
275a991c | 2042 | free_pt(dev_priv, pt); |
06fda602 | 2043 | |
8776f02b | 2044 | gen6_free_scratch(vm); |
3440d265 DV |
2045 | } |
2046 | ||
b146520f | 2047 | static int gen6_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt) |
3440d265 | 2048 | { |
8776f02b | 2049 | struct i915_address_space *vm = &ppgtt->base; |
49d73912 | 2050 | struct drm_i915_private *dev_priv = ppgtt->base.i915; |
72e96d64 | 2051 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
b146520f | 2052 | int ret; |
1d2a314c | 2053 | |
c8d4c0d6 BW |
2054 | /* PPGTT PDEs reside in the GGTT and consists of 512 entries. The |
2055 | * allocator works in address space sizes, so it's multiplied by page | |
2056 | * size. We allocate at the top of the GTT to avoid fragmentation. | |
2057 | */ | |
72e96d64 | 2058 | BUG_ON(!drm_mm_initialized(&ggtt->base.mm)); |
4933d519 | 2059 | |
8776f02b MK |
2060 | ret = gen6_init_scratch(vm); |
2061 | if (ret) | |
2062 | return ret; | |
4933d519 | 2063 | |
e007b19d CW |
2064 | ret = i915_gem_gtt_insert(&ggtt->base, &ppgtt->node, |
2065 | GEN6_PD_SIZE, GEN6_PD_ALIGN, | |
2066 | I915_COLOR_UNEVICTABLE, | |
2067 | 0, ggtt->base.total, | |
2068 | PIN_HIGH); | |
c8c26622 | 2069 | if (ret) |
678d96fb BW |
2070 | goto err_out; |
2071 | ||
72e96d64 | 2072 | if (ppgtt->node.start < ggtt->mappable_end) |
c8d4c0d6 | 2073 | DRM_DEBUG("Forced to use aperture for PDEs\n"); |
1d2a314c | 2074 | |
c8c26622 | 2075 | return 0; |
678d96fb BW |
2076 | |
2077 | err_out: | |
8776f02b | 2078 | gen6_free_scratch(vm); |
678d96fb | 2079 | return ret; |
b146520f BW |
2080 | } |
2081 | ||
b146520f BW |
2082 | static int gen6_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt) |
2083 | { | |
2f2cf682 | 2084 | return gen6_ppgtt_allocate_page_directories(ppgtt); |
4933d519 | 2085 | } |
06dc68d6 | 2086 | |
4933d519 MT |
2087 | static void gen6_scratch_va_range(struct i915_hw_ppgtt *ppgtt, |
2088 | uint64_t start, uint64_t length) | |
2089 | { | |
ec565b3c | 2090 | struct i915_page_table *unused; |
731f74c5 | 2091 | uint32_t pde; |
1d2a314c | 2092 | |
731f74c5 | 2093 | gen6_for_each_pde(unused, &ppgtt->pd, start, length, pde) |
79ab9370 | 2094 | ppgtt->pd.page_table[pde] = ppgtt->base.scratch_pt; |
b146520f BW |
2095 | } |
2096 | ||
5c5f6457 | 2097 | static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt) |
b146520f | 2098 | { |
49d73912 | 2099 | struct drm_i915_private *dev_priv = ppgtt->base.i915; |
72e96d64 | 2100 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
b146520f BW |
2101 | int ret; |
2102 | ||
72e96d64 | 2103 | ppgtt->base.pte_encode = ggtt->base.pte_encode; |
5db94019 | 2104 | if (intel_vgpu_active(dev_priv) || IS_GEN6(dev_priv)) |
b146520f | 2105 | ppgtt->switch_mm = gen6_mm_switch; |
772c2a51 | 2106 | else if (IS_HASWELL(dev_priv)) |
b146520f | 2107 | ppgtt->switch_mm = hsw_mm_switch; |
5db94019 | 2108 | else if (IS_GEN7(dev_priv)) |
b146520f | 2109 | ppgtt->switch_mm = gen7_mm_switch; |
8eb95204 | 2110 | else |
b146520f BW |
2111 | BUG(); |
2112 | ||
2113 | ret = gen6_ppgtt_alloc(ppgtt); | |
2114 | if (ret) | |
2115 | return ret; | |
2116 | ||
5c5f6457 | 2117 | ppgtt->base.allocate_va_range = gen6_alloc_va_range; |
b146520f BW |
2118 | ppgtt->base.clear_range = gen6_ppgtt_clear_range; |
2119 | ppgtt->base.insert_entries = gen6_ppgtt_insert_entries; | |
777dc5bb DV |
2120 | ppgtt->base.unbind_vma = ppgtt_unbind_vma; |
2121 | ppgtt->base.bind_vma = ppgtt_bind_vma; | |
b146520f | 2122 | ppgtt->base.cleanup = gen6_ppgtt_cleanup; |
b146520f | 2123 | ppgtt->base.start = 0; |
09942c65 | 2124 | ppgtt->base.total = I915_PDES * GEN6_PTES * PAGE_SIZE; |
87d60b63 | 2125 | ppgtt->debug_dump = gen6_dump_ppgtt; |
1d2a314c | 2126 | |
44159ddb | 2127 | ppgtt->pd.base.ggtt_offset = |
07749ef3 | 2128 | ppgtt->node.start / PAGE_SIZE * sizeof(gen6_pte_t); |
1d2a314c | 2129 | |
72e96d64 | 2130 | ppgtt->pd_addr = (gen6_pte_t __iomem *)ggtt->gsm + |
44159ddb | 2131 | ppgtt->pd.base.ggtt_offset / sizeof(gen6_pte_t); |
678d96fb | 2132 | |
5c5f6457 | 2133 | gen6_scratch_va_range(ppgtt, 0, ppgtt->base.total); |
1d2a314c | 2134 | |
678d96fb BW |
2135 | gen6_write_page_range(dev_priv, &ppgtt->pd, 0, ppgtt->base.total); |
2136 | ||
440fd528 | 2137 | DRM_DEBUG_DRIVER("Allocated pde space (%lldM) at GTT entry: %llx\n", |
b146520f BW |
2138 | ppgtt->node.size >> 20, |
2139 | ppgtt->node.start / PAGE_SIZE); | |
3440d265 | 2140 | |
fa76da34 | 2141 | DRM_DEBUG("Adding PPGTT at offset %x\n", |
44159ddb | 2142 | ppgtt->pd.base.ggtt_offset << 10); |
fa76da34 | 2143 | |
b146520f | 2144 | return 0; |
3440d265 DV |
2145 | } |
2146 | ||
2bfa996e CW |
2147 | static int __hw_ppgtt_init(struct i915_hw_ppgtt *ppgtt, |
2148 | struct drm_i915_private *dev_priv) | |
3440d265 | 2149 | { |
49d73912 | 2150 | ppgtt->base.i915 = dev_priv; |
3440d265 | 2151 | |
2bfa996e | 2152 | if (INTEL_INFO(dev_priv)->gen < 8) |
5c5f6457 | 2153 | return gen6_ppgtt_init(ppgtt); |
3ed124b2 | 2154 | else |
d7b2633d | 2155 | return gen8_ppgtt_init(ppgtt); |
fa76da34 | 2156 | } |
c114f76a | 2157 | |
a2cad9df | 2158 | static void i915_address_space_init(struct i915_address_space *vm, |
80b204bc CW |
2159 | struct drm_i915_private *dev_priv, |
2160 | const char *name) | |
a2cad9df | 2161 | { |
80b204bc | 2162 | i915_gem_timeline_init(dev_priv, &vm->timeline, name); |
47db922f | 2163 | |
a2cad9df | 2164 | drm_mm_init(&vm->mm, vm->start, vm->total); |
47db922f CW |
2165 | vm->mm.head_node.color = I915_COLOR_UNEVICTABLE; |
2166 | ||
a2cad9df MW |
2167 | INIT_LIST_HEAD(&vm->active_list); |
2168 | INIT_LIST_HEAD(&vm->inactive_list); | |
50e046b6 | 2169 | INIT_LIST_HEAD(&vm->unbound_list); |
47db922f | 2170 | |
a2cad9df MW |
2171 | list_add_tail(&vm->global_link, &dev_priv->vm_list); |
2172 | } | |
2173 | ||
ed9724dd MA |
2174 | static void i915_address_space_fini(struct i915_address_space *vm) |
2175 | { | |
2176 | i915_gem_timeline_fini(&vm->timeline); | |
2177 | drm_mm_takedown(&vm->mm); | |
2178 | list_del(&vm->global_link); | |
2179 | } | |
2180 | ||
c6be607a | 2181 | static void gtt_write_workarounds(struct drm_i915_private *dev_priv) |
d5165ebd | 2182 | { |
d5165ebd TG |
2183 | /* This function is for gtt related workarounds. This function is |
2184 | * called on driver load and after a GPU reset, so you can place | |
2185 | * workarounds here even if they get overwritten by GPU reset. | |
2186 | */ | |
9fb5026f | 2187 | /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk */ |
8652744b | 2188 | if (IS_BROADWELL(dev_priv)) |
d5165ebd | 2189 | I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW); |
920a14b2 | 2190 | else if (IS_CHERRYVIEW(dev_priv)) |
d5165ebd | 2191 | I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV); |
b976dc53 | 2192 | else if (IS_GEN9_BC(dev_priv)) |
d5165ebd | 2193 | I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL); |
9fb5026f | 2194 | else if (IS_GEN9_LP(dev_priv)) |
d5165ebd TG |
2195 | I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT); |
2196 | } | |
2197 | ||
2bfa996e CW |
2198 | static int i915_ppgtt_init(struct i915_hw_ppgtt *ppgtt, |
2199 | struct drm_i915_private *dev_priv, | |
80b204bc CW |
2200 | struct drm_i915_file_private *file_priv, |
2201 | const char *name) | |
fa76da34 | 2202 | { |
2bfa996e | 2203 | int ret; |
3ed124b2 | 2204 | |
2bfa996e | 2205 | ret = __hw_ppgtt_init(ppgtt, dev_priv); |
fa76da34 | 2206 | if (ret == 0) { |
c7c48dfd | 2207 | kref_init(&ppgtt->ref); |
80b204bc | 2208 | i915_address_space_init(&ppgtt->base, dev_priv, name); |
2bfa996e | 2209 | ppgtt->base.file = file_priv; |
93bd8649 | 2210 | } |
1d2a314c DV |
2211 | |
2212 | return ret; | |
2213 | } | |
2214 | ||
c6be607a | 2215 | int i915_ppgtt_init_hw(struct drm_i915_private *dev_priv) |
82460d97 | 2216 | { |
c6be607a | 2217 | gtt_write_workarounds(dev_priv); |
d5165ebd | 2218 | |
671b5013 TD |
2219 | /* In the case of execlists, PPGTT is enabled by the context descriptor |
2220 | * and the PDPs are contained within the context itself. We don't | |
2221 | * need to do anything here. */ | |
2222 | if (i915.enable_execlists) | |
2223 | return 0; | |
2224 | ||
c6be607a | 2225 | if (!USES_PPGTT(dev_priv)) |
82460d97 DV |
2226 | return 0; |
2227 | ||
5db94019 | 2228 | if (IS_GEN6(dev_priv)) |
c6be607a | 2229 | gen6_ppgtt_enable(dev_priv); |
5db94019 | 2230 | else if (IS_GEN7(dev_priv)) |
c6be607a TU |
2231 | gen7_ppgtt_enable(dev_priv); |
2232 | else if (INTEL_GEN(dev_priv) >= 8) | |
2233 | gen8_ppgtt_enable(dev_priv); | |
82460d97 | 2234 | else |
c6be607a | 2235 | MISSING_CASE(INTEL_GEN(dev_priv)); |
82460d97 | 2236 | |
4ad2fd88 JH |
2237 | return 0; |
2238 | } | |
1d2a314c | 2239 | |
4d884705 | 2240 | struct i915_hw_ppgtt * |
2bfa996e | 2241 | i915_ppgtt_create(struct drm_i915_private *dev_priv, |
80b204bc CW |
2242 | struct drm_i915_file_private *fpriv, |
2243 | const char *name) | |
4d884705 DV |
2244 | { |
2245 | struct i915_hw_ppgtt *ppgtt; | |
2246 | int ret; | |
2247 | ||
2248 | ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL); | |
2249 | if (!ppgtt) | |
2250 | return ERR_PTR(-ENOMEM); | |
2251 | ||
80b204bc | 2252 | ret = i915_ppgtt_init(ppgtt, dev_priv, fpriv, name); |
4d884705 DV |
2253 | if (ret) { |
2254 | kfree(ppgtt); | |
2255 | return ERR_PTR(ret); | |
2256 | } | |
2257 | ||
198c974d DCS |
2258 | trace_i915_ppgtt_create(&ppgtt->base); |
2259 | ||
4d884705 DV |
2260 | return ppgtt; |
2261 | } | |
2262 | ||
0c7eeda1 CW |
2263 | void i915_ppgtt_close(struct i915_address_space *vm) |
2264 | { | |
2265 | struct list_head *phases[] = { | |
2266 | &vm->active_list, | |
2267 | &vm->inactive_list, | |
2268 | &vm->unbound_list, | |
2269 | NULL, | |
2270 | }, **phase; | |
2271 | ||
2272 | GEM_BUG_ON(vm->closed); | |
2273 | vm->closed = true; | |
2274 | ||
2275 | for (phase = phases; *phase; phase++) { | |
2276 | struct i915_vma *vma, *vn; | |
2277 | ||
2278 | list_for_each_entry_safe(vma, vn, *phase, vm_link) | |
2279 | if (!i915_vma_is_closed(vma)) | |
2280 | i915_vma_close(vma); | |
2281 | } | |
2282 | } | |
2283 | ||
ed9724dd | 2284 | void i915_ppgtt_release(struct kref *kref) |
ee960be7 DV |
2285 | { |
2286 | struct i915_hw_ppgtt *ppgtt = | |
2287 | container_of(kref, struct i915_hw_ppgtt, ref); | |
2288 | ||
198c974d DCS |
2289 | trace_i915_ppgtt_release(&ppgtt->base); |
2290 | ||
50e046b6 | 2291 | /* vmas should already be unbound and destroyed */ |
ee960be7 DV |
2292 | WARN_ON(!list_empty(&ppgtt->base.active_list)); |
2293 | WARN_ON(!list_empty(&ppgtt->base.inactive_list)); | |
50e046b6 | 2294 | WARN_ON(!list_empty(&ppgtt->base.unbound_list)); |
ee960be7 | 2295 | |
ed9724dd | 2296 | i915_address_space_fini(&ppgtt->base); |
19dd120c | 2297 | |
ee960be7 DV |
2298 | ppgtt->base.cleanup(&ppgtt->base); |
2299 | kfree(ppgtt); | |
2300 | } | |
1d2a314c | 2301 | |
a81cc00c BW |
2302 | /* Certain Gen5 chipsets require require idling the GPU before |
2303 | * unmapping anything from the GTT when VT-d is enabled. | |
2304 | */ | |
97d6d7ab | 2305 | static bool needs_idle_maps(struct drm_i915_private *dev_priv) |
a81cc00c BW |
2306 | { |
2307 | #ifdef CONFIG_INTEL_IOMMU | |
2308 | /* Query intel_iommu to see if we need the workaround. Presumably that | |
2309 | * was loaded first. | |
2310 | */ | |
97d6d7ab | 2311 | if (IS_GEN5(dev_priv) && IS_MOBILE(dev_priv) && intel_iommu_gfx_mapped) |
a81cc00c BW |
2312 | return true; |
2313 | #endif | |
2314 | return false; | |
2315 | } | |
2316 | ||
dc97997a | 2317 | void i915_check_and_clear_faults(struct drm_i915_private *dev_priv) |
828c7908 | 2318 | { |
e2f80391 | 2319 | struct intel_engine_cs *engine; |
3b3f1650 | 2320 | enum intel_engine_id id; |
828c7908 | 2321 | |
dc97997a | 2322 | if (INTEL_INFO(dev_priv)->gen < 6) |
828c7908 BW |
2323 | return; |
2324 | ||
3b3f1650 | 2325 | for_each_engine(engine, dev_priv, id) { |
828c7908 | 2326 | u32 fault_reg; |
e2f80391 | 2327 | fault_reg = I915_READ(RING_FAULT_REG(engine)); |
828c7908 BW |
2328 | if (fault_reg & RING_FAULT_VALID) { |
2329 | DRM_DEBUG_DRIVER("Unexpected fault\n" | |
59a5d290 | 2330 | "\tAddr: 0x%08lx\n" |
828c7908 BW |
2331 | "\tAddress space: %s\n" |
2332 | "\tSource ID: %d\n" | |
2333 | "\tType: %d\n", | |
2334 | fault_reg & PAGE_MASK, | |
2335 | fault_reg & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT", | |
2336 | RING_FAULT_SRCID(fault_reg), | |
2337 | RING_FAULT_FAULT_TYPE(fault_reg)); | |
e2f80391 | 2338 | I915_WRITE(RING_FAULT_REG(engine), |
828c7908 BW |
2339 | fault_reg & ~RING_FAULT_VALID); |
2340 | } | |
2341 | } | |
3b3f1650 AG |
2342 | |
2343 | /* Engine specific init may not have been done till this point. */ | |
2344 | if (dev_priv->engine[RCS]) | |
2345 | POSTING_READ(RING_FAULT_REG(dev_priv->engine[RCS])); | |
828c7908 BW |
2346 | } |
2347 | ||
275a991c | 2348 | void i915_gem_suspend_gtt_mappings(struct drm_i915_private *dev_priv) |
828c7908 | 2349 | { |
72e96d64 | 2350 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
828c7908 BW |
2351 | |
2352 | /* Don't bother messing with faults pre GEN6 as we have little | |
2353 | * documentation supporting that it's a good idea. | |
2354 | */ | |
275a991c | 2355 | if (INTEL_GEN(dev_priv) < 6) |
828c7908 BW |
2356 | return; |
2357 | ||
dc97997a | 2358 | i915_check_and_clear_faults(dev_priv); |
828c7908 | 2359 | |
4fb84d99 | 2360 | ggtt->base.clear_range(&ggtt->base, ggtt->base.start, ggtt->base.total); |
91e56499 | 2361 | |
7c3f86b6 | 2362 | i915_ggtt_invalidate(dev_priv); |
828c7908 BW |
2363 | } |
2364 | ||
03ac84f1 CW |
2365 | int i915_gem_gtt_prepare_pages(struct drm_i915_gem_object *obj, |
2366 | struct sg_table *pages) | |
7c2e6fdf | 2367 | { |
1a292fa5 CW |
2368 | do { |
2369 | if (dma_map_sg(&obj->base.dev->pdev->dev, | |
2370 | pages->sgl, pages->nents, | |
2371 | PCI_DMA_BIDIRECTIONAL)) | |
2372 | return 0; | |
2373 | ||
2374 | /* If the DMA remap fails, one cause can be that we have | |
2375 | * too many objects pinned in a small remapping table, | |
2376 | * such as swiotlb. Incrementally purge all other objects and | |
2377 | * try again - if there are no more pages to remove from | |
2378 | * the DMA remapper, i915_gem_shrink will return 0. | |
2379 | */ | |
2380 | GEM_BUG_ON(obj->mm.pages == pages); | |
2381 | } while (i915_gem_shrink(to_i915(obj->base.dev), | |
2382 | obj->base.size >> PAGE_SHIFT, | |
2383 | I915_SHRINK_BOUND | | |
2384 | I915_SHRINK_UNBOUND | | |
2385 | I915_SHRINK_ACTIVE)); | |
9da3da66 | 2386 | |
03ac84f1 | 2387 | return -ENOSPC; |
7c2e6fdf DV |
2388 | } |
2389 | ||
2c642b07 | 2390 | static void gen8_set_pte(void __iomem *addr, gen8_pte_t pte) |
94ec8f61 | 2391 | { |
94ec8f61 | 2392 | writeq(pte, addr); |
94ec8f61 BW |
2393 | } |
2394 | ||
d6473f56 CW |
2395 | static void gen8_ggtt_insert_page(struct i915_address_space *vm, |
2396 | dma_addr_t addr, | |
2397 | uint64_t offset, | |
2398 | enum i915_cache_level level, | |
2399 | u32 unused) | |
2400 | { | |
7c3f86b6 | 2401 | struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm); |
d6473f56 | 2402 | gen8_pte_t __iomem *pte = |
7c3f86b6 | 2403 | (gen8_pte_t __iomem *)ggtt->gsm + (offset >> PAGE_SHIFT); |
d6473f56 | 2404 | |
4fb84d99 | 2405 | gen8_set_pte(pte, gen8_pte_encode(addr, level)); |
d6473f56 | 2406 | |
7c3f86b6 | 2407 | ggtt->invalidate(vm->i915); |
d6473f56 CW |
2408 | } |
2409 | ||
94ec8f61 BW |
2410 | static void gen8_ggtt_insert_entries(struct i915_address_space *vm, |
2411 | struct sg_table *st, | |
782f1495 | 2412 | uint64_t start, |
24f3a8cf | 2413 | enum i915_cache_level level, u32 unused) |
94ec8f61 | 2414 | { |
ce7fda2e | 2415 | struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm); |
85d1225e DG |
2416 | struct sgt_iter sgt_iter; |
2417 | gen8_pte_t __iomem *gtt_entries; | |
2418 | gen8_pte_t gtt_entry; | |
2419 | dma_addr_t addr; | |
85d1225e | 2420 | int i = 0; |
be69459a | 2421 | |
85d1225e DG |
2422 | gtt_entries = (gen8_pte_t __iomem *)ggtt->gsm + (start >> PAGE_SHIFT); |
2423 | ||
2424 | for_each_sgt_dma(addr, sgt_iter, st) { | |
4fb84d99 | 2425 | gtt_entry = gen8_pte_encode(addr, level); |
85d1225e | 2426 | gen8_set_pte(>t_entries[i++], gtt_entry); |
94ec8f61 BW |
2427 | } |
2428 | ||
2429 | /* | |
2430 | * XXX: This serves as a posting read to make sure that the PTE has | |
2431 | * actually been updated. There is some concern that even though | |
2432 | * registers and PTEs are within the same BAR that they are potentially | |
2433 | * of NUMA access patterns. Therefore, even with the way we assume | |
2434 | * hardware should work, we must keep this posting read for paranoia. | |
2435 | */ | |
2436 | if (i != 0) | |
85d1225e | 2437 | WARN_ON(readq(>t_entries[i-1]) != gtt_entry); |
94ec8f61 | 2438 | |
94ec8f61 BW |
2439 | /* This next bit makes the above posting read even more important. We |
2440 | * want to flush the TLBs only after we're certain all the PTE updates | |
2441 | * have finished. | |
2442 | */ | |
7c3f86b6 | 2443 | ggtt->invalidate(vm->i915); |
94ec8f61 BW |
2444 | } |
2445 | ||
c140330b CW |
2446 | struct insert_entries { |
2447 | struct i915_address_space *vm; | |
2448 | struct sg_table *st; | |
2449 | uint64_t start; | |
2450 | enum i915_cache_level level; | |
2451 | u32 flags; | |
2452 | }; | |
2453 | ||
2454 | static int gen8_ggtt_insert_entries__cb(void *_arg) | |
2455 | { | |
2456 | struct insert_entries *arg = _arg; | |
2457 | gen8_ggtt_insert_entries(arg->vm, arg->st, | |
2458 | arg->start, arg->level, arg->flags); | |
2459 | return 0; | |
2460 | } | |
2461 | ||
2462 | static void gen8_ggtt_insert_entries__BKL(struct i915_address_space *vm, | |
2463 | struct sg_table *st, | |
2464 | uint64_t start, | |
2465 | enum i915_cache_level level, | |
2466 | u32 flags) | |
2467 | { | |
2468 | struct insert_entries arg = { vm, st, start, level, flags }; | |
2469 | stop_machine(gen8_ggtt_insert_entries__cb, &arg, NULL); | |
2470 | } | |
2471 | ||
d6473f56 CW |
2472 | static void gen6_ggtt_insert_page(struct i915_address_space *vm, |
2473 | dma_addr_t addr, | |
2474 | uint64_t offset, | |
2475 | enum i915_cache_level level, | |
2476 | u32 flags) | |
2477 | { | |
7c3f86b6 | 2478 | struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm); |
d6473f56 | 2479 | gen6_pte_t __iomem *pte = |
7c3f86b6 | 2480 | (gen6_pte_t __iomem *)ggtt->gsm + (offset >> PAGE_SHIFT); |
d6473f56 | 2481 | |
4fb84d99 | 2482 | iowrite32(vm->pte_encode(addr, level, flags), pte); |
d6473f56 | 2483 | |
7c3f86b6 | 2484 | ggtt->invalidate(vm->i915); |
d6473f56 CW |
2485 | } |
2486 | ||
e76e9aeb BW |
2487 | /* |
2488 | * Binds an object into the global gtt with the specified cache level. The object | |
2489 | * will be accessible to the GPU via commands whose operands reference offsets | |
2490 | * within the global GTT as well as accessible by the GPU through the GMADR | |
2491 | * mapped BAR (dev_priv->mm.gtt->gtt). | |
2492 | */ | |
853ba5d2 | 2493 | static void gen6_ggtt_insert_entries(struct i915_address_space *vm, |
7faf1ab2 | 2494 | struct sg_table *st, |
782f1495 | 2495 | uint64_t start, |
24f3a8cf | 2496 | enum i915_cache_level level, u32 flags) |
e76e9aeb | 2497 | { |
ce7fda2e | 2498 | struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm); |
85d1225e DG |
2499 | struct sgt_iter sgt_iter; |
2500 | gen6_pte_t __iomem *gtt_entries; | |
2501 | gen6_pte_t gtt_entry; | |
2502 | dma_addr_t addr; | |
85d1225e | 2503 | int i = 0; |
be69459a | 2504 | |
85d1225e DG |
2505 | gtt_entries = (gen6_pte_t __iomem *)ggtt->gsm + (start >> PAGE_SHIFT); |
2506 | ||
2507 | for_each_sgt_dma(addr, sgt_iter, st) { | |
4fb84d99 | 2508 | gtt_entry = vm->pte_encode(addr, level, flags); |
85d1225e | 2509 | iowrite32(gtt_entry, >t_entries[i++]); |
e76e9aeb BW |
2510 | } |
2511 | ||
e76e9aeb BW |
2512 | /* XXX: This serves as a posting read to make sure that the PTE has |
2513 | * actually been updated. There is some concern that even though | |
2514 | * registers and PTEs are within the same BAR that they are potentially | |
2515 | * of NUMA access patterns. Therefore, even with the way we assume | |
2516 | * hardware should work, we must keep this posting read for paranoia. | |
2517 | */ | |
85d1225e DG |
2518 | if (i != 0) |
2519 | WARN_ON(readl(>t_entries[i-1]) != gtt_entry); | |
0f9b91c7 BW |
2520 | |
2521 | /* This next bit makes the above posting read even more important. We | |
2522 | * want to flush the TLBs only after we're certain all the PTE updates | |
2523 | * have finished. | |
2524 | */ | |
7c3f86b6 | 2525 | ggtt->invalidate(vm->i915); |
e76e9aeb BW |
2526 | } |
2527 | ||
f7770bfd | 2528 | static void nop_clear_range(struct i915_address_space *vm, |
4fb84d99 | 2529 | uint64_t start, uint64_t length) |
f7770bfd CW |
2530 | { |
2531 | } | |
2532 | ||
94ec8f61 | 2533 | static void gen8_ggtt_clear_range(struct i915_address_space *vm, |
4fb84d99 | 2534 | uint64_t start, uint64_t length) |
94ec8f61 | 2535 | { |
ce7fda2e | 2536 | struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm); |
782f1495 BW |
2537 | unsigned first_entry = start >> PAGE_SHIFT; |
2538 | unsigned num_entries = length >> PAGE_SHIFT; | |
07749ef3 | 2539 | gen8_pte_t scratch_pte, __iomem *gtt_base = |
72e96d64 JL |
2540 | (gen8_pte_t __iomem *)ggtt->gsm + first_entry; |
2541 | const int max_entries = ggtt_total_entries(ggtt) - first_entry; | |
94ec8f61 BW |
2542 | int i; |
2543 | ||
2544 | if (WARN(num_entries > max_entries, | |
2545 | "First entry = %d; Num entries = %d (max=%d)\n", | |
2546 | first_entry, num_entries, max_entries)) | |
2547 | num_entries = max_entries; | |
2548 | ||
8bcdd0f7 | 2549 | scratch_pte = gen8_pte_encode(vm->scratch_page.daddr, |
4fb84d99 | 2550 | I915_CACHE_LLC); |
94ec8f61 BW |
2551 | for (i = 0; i < num_entries; i++) |
2552 | gen8_set_pte(>t_base[i], scratch_pte); | |
2553 | readl(gtt_base); | |
2554 | } | |
2555 | ||
853ba5d2 | 2556 | static void gen6_ggtt_clear_range(struct i915_address_space *vm, |
782f1495 | 2557 | uint64_t start, |
4fb84d99 | 2558 | uint64_t length) |
7faf1ab2 | 2559 | { |
ce7fda2e | 2560 | struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm); |
782f1495 BW |
2561 | unsigned first_entry = start >> PAGE_SHIFT; |
2562 | unsigned num_entries = length >> PAGE_SHIFT; | |
07749ef3 | 2563 | gen6_pte_t scratch_pte, __iomem *gtt_base = |
72e96d64 JL |
2564 | (gen6_pte_t __iomem *)ggtt->gsm + first_entry; |
2565 | const int max_entries = ggtt_total_entries(ggtt) - first_entry; | |
7faf1ab2 DV |
2566 | int i; |
2567 | ||
2568 | if (WARN(num_entries > max_entries, | |
2569 | "First entry = %d; Num entries = %d (max=%d)\n", | |
2570 | first_entry, num_entries, max_entries)) | |
2571 | num_entries = max_entries; | |
2572 | ||
8bcdd0f7 | 2573 | scratch_pte = vm->pte_encode(vm->scratch_page.daddr, |
4fb84d99 | 2574 | I915_CACHE_LLC, 0); |
828c7908 | 2575 | |
7faf1ab2 DV |
2576 | for (i = 0; i < num_entries; i++) |
2577 | iowrite32(scratch_pte, >t_base[i]); | |
2578 | readl(gtt_base); | |
2579 | } | |
2580 | ||
d6473f56 CW |
2581 | static void i915_ggtt_insert_page(struct i915_address_space *vm, |
2582 | dma_addr_t addr, | |
2583 | uint64_t offset, | |
2584 | enum i915_cache_level cache_level, | |
2585 | u32 unused) | |
2586 | { | |
d6473f56 CW |
2587 | unsigned int flags = (cache_level == I915_CACHE_NONE) ? |
2588 | AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY; | |
d6473f56 CW |
2589 | |
2590 | intel_gtt_insert_page(addr, offset >> PAGE_SHIFT, flags); | |
d6473f56 CW |
2591 | } |
2592 | ||
d369d2d9 DV |
2593 | static void i915_ggtt_insert_entries(struct i915_address_space *vm, |
2594 | struct sg_table *pages, | |
2595 | uint64_t start, | |
2596 | enum i915_cache_level cache_level, u32 unused) | |
7faf1ab2 DV |
2597 | { |
2598 | unsigned int flags = (cache_level == I915_CACHE_NONE) ? | |
2599 | AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY; | |
2600 | ||
d369d2d9 | 2601 | intel_gtt_insert_sg_entries(pages, start >> PAGE_SHIFT, flags); |
0875546c | 2602 | |
7faf1ab2 DV |
2603 | } |
2604 | ||
853ba5d2 | 2605 | static void i915_ggtt_clear_range(struct i915_address_space *vm, |
782f1495 | 2606 | uint64_t start, |
4fb84d99 | 2607 | uint64_t length) |
7faf1ab2 | 2608 | { |
2eedfc7d | 2609 | intel_gtt_clear_range(start >> PAGE_SHIFT, length >> PAGE_SHIFT); |
7faf1ab2 DV |
2610 | } |
2611 | ||
70b9f6f8 DV |
2612 | static int ggtt_bind_vma(struct i915_vma *vma, |
2613 | enum i915_cache_level cache_level, | |
2614 | u32 flags) | |
0a878716 | 2615 | { |
49d73912 | 2616 | struct drm_i915_private *i915 = vma->vm->i915; |
0a878716 DV |
2617 | struct drm_i915_gem_object *obj = vma->obj; |
2618 | u32 pte_flags = 0; | |
2619 | int ret; | |
2620 | ||
2621 | ret = i915_get_ggtt_vma_pages(vma); | |
2622 | if (ret) | |
2623 | return ret; | |
2624 | ||
2625 | /* Currently applicable only to VLV */ | |
2626 | if (obj->gt_ro) | |
2627 | pte_flags |= PTE_READ_ONLY; | |
2628 | ||
9c870d03 | 2629 | intel_runtime_pm_get(i915); |
247177dd | 2630 | vma->vm->insert_entries(vma->vm, vma->pages, vma->node.start, |
0a878716 | 2631 | cache_level, pte_flags); |
9c870d03 | 2632 | intel_runtime_pm_put(i915); |
0a878716 DV |
2633 | |
2634 | /* | |
2635 | * Without aliasing PPGTT there's no difference between | |
2636 | * GLOBAL/LOCAL_BIND, it's all the same ptes. Hence unconditionally | |
2637 | * upgrade to both bound if we bind either to avoid double-binding. | |
2638 | */ | |
3272db53 | 2639 | vma->flags |= I915_VMA_GLOBAL_BIND | I915_VMA_LOCAL_BIND; |
0a878716 DV |
2640 | |
2641 | return 0; | |
2642 | } | |
2643 | ||
2644 | static int aliasing_gtt_bind_vma(struct i915_vma *vma, | |
2645 | enum i915_cache_level cache_level, | |
2646 | u32 flags) | |
d5bd1449 | 2647 | { |
49d73912 | 2648 | struct drm_i915_private *i915 = vma->vm->i915; |
321d178e | 2649 | u32 pte_flags; |
70b9f6f8 DV |
2650 | int ret; |
2651 | ||
2652 | ret = i915_get_ggtt_vma_pages(vma); | |
2653 | if (ret) | |
2654 | return ret; | |
7faf1ab2 | 2655 | |
24f3a8cf | 2656 | /* Currently applicable only to VLV */ |
321d178e CW |
2657 | pte_flags = 0; |
2658 | if (vma->obj->gt_ro) | |
f329f5f6 | 2659 | pte_flags |= PTE_READ_ONLY; |
24f3a8cf | 2660 | |
ec7adb6e | 2661 | |
3272db53 | 2662 | if (flags & I915_VMA_GLOBAL_BIND) { |
9c870d03 | 2663 | intel_runtime_pm_get(i915); |
321d178e | 2664 | vma->vm->insert_entries(vma->vm, |
247177dd | 2665 | vma->pages, vma->node.start, |
0875546c | 2666 | cache_level, pte_flags); |
9c870d03 | 2667 | intel_runtime_pm_put(i915); |
6f65e29a | 2668 | } |
d5bd1449 | 2669 | |
3272db53 | 2670 | if (flags & I915_VMA_LOCAL_BIND) { |
9c870d03 | 2671 | struct i915_hw_ppgtt *appgtt = i915->mm.aliasing_ppgtt; |
321d178e | 2672 | appgtt->base.insert_entries(&appgtt->base, |
247177dd | 2673 | vma->pages, vma->node.start, |
f329f5f6 | 2674 | cache_level, pte_flags); |
6f65e29a | 2675 | } |
70b9f6f8 DV |
2676 | |
2677 | return 0; | |
d5bd1449 CW |
2678 | } |
2679 | ||
6f65e29a | 2680 | static void ggtt_unbind_vma(struct i915_vma *vma) |
74163907 | 2681 | { |
49d73912 | 2682 | struct drm_i915_private *i915 = vma->vm->i915; |
9c870d03 | 2683 | struct i915_hw_ppgtt *appgtt = i915->mm.aliasing_ppgtt; |
de180033 | 2684 | const u64 size = min(vma->size, vma->node.size); |
6f65e29a | 2685 | |
9c870d03 CW |
2686 | if (vma->flags & I915_VMA_GLOBAL_BIND) { |
2687 | intel_runtime_pm_get(i915); | |
782f1495 | 2688 | vma->vm->clear_range(vma->vm, |
4fb84d99 | 2689 | vma->node.start, size); |
9c870d03 CW |
2690 | intel_runtime_pm_put(i915); |
2691 | } | |
06615ee5 | 2692 | |
3272db53 | 2693 | if (vma->flags & I915_VMA_LOCAL_BIND && appgtt) |
6f65e29a | 2694 | appgtt->base.clear_range(&appgtt->base, |
4fb84d99 | 2695 | vma->node.start, size); |
74163907 DV |
2696 | } |
2697 | ||
03ac84f1 CW |
2698 | void i915_gem_gtt_finish_pages(struct drm_i915_gem_object *obj, |
2699 | struct sg_table *pages) | |
7c2e6fdf | 2700 | { |
52a05c30 DW |
2701 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
2702 | struct device *kdev = &dev_priv->drm.pdev->dev; | |
307dc25b | 2703 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
5c042287 | 2704 | |
307dc25b | 2705 | if (unlikely(ggtt->do_idle_maps)) { |
22dd3bb9 | 2706 | if (i915_gem_wait_for_idle(dev_priv, I915_WAIT_LOCKED)) { |
307dc25b CW |
2707 | DRM_ERROR("Failed to wait for idle; VT'd may hang.\n"); |
2708 | /* Wait a bit, in hopes it avoids the hang */ | |
2709 | udelay(10); | |
2710 | } | |
2711 | } | |
5c042287 | 2712 | |
03ac84f1 | 2713 | dma_unmap_sg(kdev, pages->sgl, pages->nents, PCI_DMA_BIDIRECTIONAL); |
7c2e6fdf | 2714 | } |
644ec02b | 2715 | |
45b186f1 | 2716 | static void i915_gtt_color_adjust(const struct drm_mm_node *node, |
42d6ab48 | 2717 | unsigned long color, |
440fd528 TR |
2718 | u64 *start, |
2719 | u64 *end) | |
42d6ab48 | 2720 | { |
a6508ded | 2721 | if (node->allocated && node->color != color) |
f51455d4 | 2722 | *start += I915_GTT_PAGE_SIZE; |
42d6ab48 | 2723 | |
a6508ded CW |
2724 | /* Also leave a space between the unallocated reserved node after the |
2725 | * GTT and any objects within the GTT, i.e. we use the color adjustment | |
2726 | * to insert a guard page to prevent prefetches crossing over the | |
2727 | * GTT boundary. | |
2728 | */ | |
b44f97fd | 2729 | node = list_next_entry(node, node_list); |
a6508ded | 2730 | if (node->color != color) |
f51455d4 | 2731 | *end -= I915_GTT_PAGE_SIZE; |
42d6ab48 | 2732 | } |
fbe5d36e | 2733 | |
f6b9d5ca | 2734 | int i915_gem_init_ggtt(struct drm_i915_private *dev_priv) |
644ec02b | 2735 | { |
e78891ca BW |
2736 | /* Let GEM Manage all of the aperture. |
2737 | * | |
2738 | * However, leave one page at the end still bound to the scratch page. | |
2739 | * There are a number of places where the hardware apparently prefetches | |
2740 | * past the end of the object, and we've seen multiple hangs with the | |
2741 | * GPU head pointer stuck in a batchbuffer bound at the last page of the | |
2742 | * aperture. One page should be enough to keep any prefetching inside | |
2743 | * of the aperture. | |
2744 | */ | |
72e96d64 | 2745 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
ed2f3452 | 2746 | unsigned long hole_start, hole_end; |
95374d75 | 2747 | struct i915_hw_ppgtt *ppgtt; |
f6b9d5ca | 2748 | struct drm_mm_node *entry; |
fa76da34 | 2749 | int ret; |
644ec02b | 2750 | |
b02d22a3 ZW |
2751 | ret = intel_vgt_balloon(dev_priv); |
2752 | if (ret) | |
2753 | return ret; | |
5dda8fa3 | 2754 | |
95374d75 CW |
2755 | /* Reserve a mappable slot for our lockless error capture */ |
2756 | ret = drm_mm_insert_node_in_range_generic(&ggtt->base.mm, | |
2757 | &ggtt->error_capture, | |
f51455d4 | 2758 | PAGE_SIZE, 0, |
85fd4f58 | 2759 | I915_COLOR_UNEVICTABLE, |
95374d75 CW |
2760 | 0, ggtt->mappable_end, |
2761 | 0, 0); | |
2762 | if (ret) | |
2763 | return ret; | |
2764 | ||
ed2f3452 | 2765 | /* Clear any non-preallocated blocks */ |
72e96d64 | 2766 | drm_mm_for_each_hole(entry, &ggtt->base.mm, hole_start, hole_end) { |
ed2f3452 CW |
2767 | DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n", |
2768 | hole_start, hole_end); | |
72e96d64 | 2769 | ggtt->base.clear_range(&ggtt->base, hole_start, |
4fb84d99 | 2770 | hole_end - hole_start); |
ed2f3452 CW |
2771 | } |
2772 | ||
2773 | /* And finally clear the reserved guard page */ | |
f6b9d5ca | 2774 | ggtt->base.clear_range(&ggtt->base, |
4fb84d99 | 2775 | ggtt->base.total - PAGE_SIZE, PAGE_SIZE); |
6c5566a8 | 2776 | |
97d6d7ab | 2777 | if (USES_PPGTT(dev_priv) && !USES_FULL_PPGTT(dev_priv)) { |
fa76da34 | 2778 | ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL); |
95374d75 CW |
2779 | if (!ppgtt) { |
2780 | ret = -ENOMEM; | |
2781 | goto err; | |
2782 | } | |
fa76da34 | 2783 | |
2bfa996e | 2784 | ret = __hw_ppgtt_init(ppgtt, dev_priv); |
95374d75 CW |
2785 | if (ret) |
2786 | goto err_ppgtt; | |
5c5f6457 | 2787 | |
95374d75 | 2788 | if (ppgtt->base.allocate_va_range) { |
5c5f6457 DV |
2789 | ret = ppgtt->base.allocate_va_range(&ppgtt->base, 0, |
2790 | ppgtt->base.total); | |
95374d75 CW |
2791 | if (ret) |
2792 | goto err_ppgtt_cleanup; | |
4933d519 | 2793 | } |
fa76da34 | 2794 | |
5c5f6457 DV |
2795 | ppgtt->base.clear_range(&ppgtt->base, |
2796 | ppgtt->base.start, | |
4fb84d99 | 2797 | ppgtt->base.total); |
5c5f6457 | 2798 | |
fa76da34 | 2799 | dev_priv->mm.aliasing_ppgtt = ppgtt; |
72e96d64 JL |
2800 | WARN_ON(ggtt->base.bind_vma != ggtt_bind_vma); |
2801 | ggtt->base.bind_vma = aliasing_gtt_bind_vma; | |
fa76da34 DV |
2802 | } |
2803 | ||
6c5566a8 | 2804 | return 0; |
95374d75 CW |
2805 | |
2806 | err_ppgtt_cleanup: | |
2807 | ppgtt->base.cleanup(&ppgtt->base); | |
2808 | err_ppgtt: | |
2809 | kfree(ppgtt); | |
2810 | err: | |
2811 | drm_mm_remove_node(&ggtt->error_capture); | |
2812 | return ret; | |
e76e9aeb BW |
2813 | } |
2814 | ||
d85489d3 JL |
2815 | /** |
2816 | * i915_ggtt_cleanup_hw - Clean up GGTT hardware initialization | |
97d6d7ab | 2817 | * @dev_priv: i915 device |
d85489d3 | 2818 | */ |
97d6d7ab | 2819 | void i915_ggtt_cleanup_hw(struct drm_i915_private *dev_priv) |
90d0a0e8 | 2820 | { |
72e96d64 | 2821 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
90d0a0e8 | 2822 | |
70e32544 DV |
2823 | if (dev_priv->mm.aliasing_ppgtt) { |
2824 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
70e32544 | 2825 | ppgtt->base.cleanup(&ppgtt->base); |
cb7f2760 | 2826 | kfree(ppgtt); |
70e32544 DV |
2827 | } |
2828 | ||
97d6d7ab | 2829 | i915_gem_cleanup_stolen(&dev_priv->drm); |
a4eba47b | 2830 | |
95374d75 CW |
2831 | if (drm_mm_node_allocated(&ggtt->error_capture)) |
2832 | drm_mm_remove_node(&ggtt->error_capture); | |
2833 | ||
72e96d64 | 2834 | if (drm_mm_initialized(&ggtt->base.mm)) { |
b02d22a3 | 2835 | intel_vgt_deballoon(dev_priv); |
5dda8fa3 | 2836 | |
ed9724dd MA |
2837 | mutex_lock(&dev_priv->drm.struct_mutex); |
2838 | i915_address_space_fini(&ggtt->base); | |
2839 | mutex_unlock(&dev_priv->drm.struct_mutex); | |
90d0a0e8 DV |
2840 | } |
2841 | ||
72e96d64 | 2842 | ggtt->base.cleanup(&ggtt->base); |
f6b9d5ca CW |
2843 | |
2844 | arch_phys_wc_del(ggtt->mtrr); | |
f7bbe788 | 2845 | io_mapping_fini(&ggtt->mappable); |
90d0a0e8 | 2846 | } |
70e32544 | 2847 | |
2c642b07 | 2848 | static unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl) |
e76e9aeb BW |
2849 | { |
2850 | snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT; | |
2851 | snb_gmch_ctl &= SNB_GMCH_GGMS_MASK; | |
2852 | return snb_gmch_ctl << 20; | |
2853 | } | |
2854 | ||
2c642b07 | 2855 | static unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl) |
9459d252 BW |
2856 | { |
2857 | bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT; | |
2858 | bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK; | |
2859 | if (bdw_gmch_ctl) | |
2860 | bdw_gmch_ctl = 1 << bdw_gmch_ctl; | |
562d55d9 BW |
2861 | |
2862 | #ifdef CONFIG_X86_32 | |
2863 | /* Limit 32b platforms to a 2GB GGTT: 4 << 20 / pte size * PAGE_SIZE */ | |
2864 | if (bdw_gmch_ctl > 4) | |
2865 | bdw_gmch_ctl = 4; | |
2866 | #endif | |
2867 | ||
9459d252 BW |
2868 | return bdw_gmch_ctl << 20; |
2869 | } | |
2870 | ||
2c642b07 | 2871 | static unsigned int chv_get_total_gtt_size(u16 gmch_ctrl) |
d7f25f23 DL |
2872 | { |
2873 | gmch_ctrl >>= SNB_GMCH_GGMS_SHIFT; | |
2874 | gmch_ctrl &= SNB_GMCH_GGMS_MASK; | |
2875 | ||
2876 | if (gmch_ctrl) | |
2877 | return 1 << (20 + gmch_ctrl); | |
2878 | ||
2879 | return 0; | |
2880 | } | |
2881 | ||
2c642b07 | 2882 | static size_t gen6_get_stolen_size(u16 snb_gmch_ctl) |
e76e9aeb BW |
2883 | { |
2884 | snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT; | |
2885 | snb_gmch_ctl &= SNB_GMCH_GMS_MASK; | |
2886 | return snb_gmch_ctl << 25; /* 32 MB units */ | |
2887 | } | |
2888 | ||
2c642b07 | 2889 | static size_t gen8_get_stolen_size(u16 bdw_gmch_ctl) |
9459d252 BW |
2890 | { |
2891 | bdw_gmch_ctl >>= BDW_GMCH_GMS_SHIFT; | |
2892 | bdw_gmch_ctl &= BDW_GMCH_GMS_MASK; | |
2893 | return bdw_gmch_ctl << 25; /* 32 MB units */ | |
2894 | } | |
2895 | ||
d7f25f23 DL |
2896 | static size_t chv_get_stolen_size(u16 gmch_ctrl) |
2897 | { | |
2898 | gmch_ctrl >>= SNB_GMCH_GMS_SHIFT; | |
2899 | gmch_ctrl &= SNB_GMCH_GMS_MASK; | |
2900 | ||
2901 | /* | |
2902 | * 0x0 to 0x10: 32MB increments starting at 0MB | |
2903 | * 0x11 to 0x16: 4MB increments starting at 8MB | |
2904 | * 0x17 to 0x1d: 4MB increments start at 36MB | |
2905 | */ | |
2906 | if (gmch_ctrl < 0x11) | |
2907 | return gmch_ctrl << 25; | |
2908 | else if (gmch_ctrl < 0x17) | |
2909 | return (gmch_ctrl - 0x11 + 2) << 22; | |
2910 | else | |
2911 | return (gmch_ctrl - 0x17 + 9) << 22; | |
2912 | } | |
2913 | ||
66375014 DL |
2914 | static size_t gen9_get_stolen_size(u16 gen9_gmch_ctl) |
2915 | { | |
2916 | gen9_gmch_ctl >>= BDW_GMCH_GMS_SHIFT; | |
2917 | gen9_gmch_ctl &= BDW_GMCH_GMS_MASK; | |
2918 | ||
2919 | if (gen9_gmch_ctl < 0xf0) | |
2920 | return gen9_gmch_ctl << 25; /* 32 MB units */ | |
2921 | else | |
2922 | /* 4MB increments starting at 0xf0 for 4MB */ | |
2923 | return (gen9_gmch_ctl - 0xf0 + 1) << 22; | |
2924 | } | |
2925 | ||
34c998b4 | 2926 | static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size) |
63340133 | 2927 | { |
49d73912 CW |
2928 | struct drm_i915_private *dev_priv = ggtt->base.i915; |
2929 | struct pci_dev *pdev = dev_priv->drm.pdev; | |
34c998b4 | 2930 | phys_addr_t phys_addr; |
8bcdd0f7 | 2931 | int ret; |
63340133 BW |
2932 | |
2933 | /* For Modern GENs the PTEs and register space are split in the BAR */ | |
34c998b4 | 2934 | phys_addr = pci_resource_start(pdev, 0) + pci_resource_len(pdev, 0) / 2; |
63340133 | 2935 | |
2a073f89 ID |
2936 | /* |
2937 | * On BXT writes larger than 64 bit to the GTT pagetable range will be | |
2938 | * dropped. For WC mappings in general we have 64 byte burst writes | |
2939 | * when the WC buffer is flushed, so we can't use it, but have to | |
2940 | * resort to an uncached mapping. The WC issue is easily caught by the | |
2941 | * readback check when writing GTT PTE entries. | |
2942 | */ | |
cc3f90f0 | 2943 | if (IS_GEN9_LP(dev_priv)) |
34c998b4 | 2944 | ggtt->gsm = ioremap_nocache(phys_addr, size); |
2a073f89 | 2945 | else |
34c998b4 | 2946 | ggtt->gsm = ioremap_wc(phys_addr, size); |
72e96d64 | 2947 | if (!ggtt->gsm) { |
34c998b4 | 2948 | DRM_ERROR("Failed to map the ggtt page table\n"); |
63340133 BW |
2949 | return -ENOMEM; |
2950 | } | |
2951 | ||
275a991c | 2952 | ret = setup_scratch_page(dev_priv, &ggtt->base.scratch_page, GFP_DMA32); |
8bcdd0f7 | 2953 | if (ret) { |
63340133 BW |
2954 | DRM_ERROR("Scratch setup failed\n"); |
2955 | /* iounmap will also get called at remove, but meh */ | |
72e96d64 | 2956 | iounmap(ggtt->gsm); |
8bcdd0f7 | 2957 | return ret; |
63340133 BW |
2958 | } |
2959 | ||
4ad2af1e | 2960 | return 0; |
63340133 BW |
2961 | } |
2962 | ||
fbe5d36e BW |
2963 | /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability |
2964 | * bits. When using advanced contexts each context stores its own PAT, but | |
2965 | * writing this data shouldn't be harmful even in those cases. */ | |
ee0ce478 | 2966 | static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv) |
fbe5d36e | 2967 | { |
fbe5d36e BW |
2968 | uint64_t pat; |
2969 | ||
2970 | pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC) | /* for normal objects, no eLLC */ | |
2971 | GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something pointing to ptes? */ | |
2972 | GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC) | /* for scanout with eLLC */ | |
2973 | GEN8_PPAT(3, GEN8_PPAT_UC) | /* Uncached objects, mostly for scanout */ | |
2974 | GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) | | |
2975 | GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) | | |
2976 | GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) | | |
2977 | GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3)); | |
2978 | ||
2d1fe073 | 2979 | if (!USES_PPGTT(dev_priv)) |
d6a8b72e RV |
2980 | /* Spec: "For GGTT, there is NO pat_sel[2:0] from the entry, |
2981 | * so RTL will always use the value corresponding to | |
2982 | * pat_sel = 000". | |
2983 | * So let's disable cache for GGTT to avoid screen corruptions. | |
2984 | * MOCS still can be used though. | |
2985 | * - System agent ggtt writes (i.e. cpu gtt mmaps) already work | |
2986 | * before this patch, i.e. the same uncached + snooping access | |
2987 | * like on gen6/7 seems to be in effect. | |
2988 | * - So this just fixes blitter/render access. Again it looks | |
2989 | * like it's not just uncached access, but uncached + snooping. | |
2990 | * So we can still hold onto all our assumptions wrt cpu | |
2991 | * clflushing on LLC machines. | |
2992 | */ | |
2993 | pat = GEN8_PPAT(0, GEN8_PPAT_UC); | |
2994 | ||
fbe5d36e BW |
2995 | /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b |
2996 | * write would work. */ | |
7e435ad2 VS |
2997 | I915_WRITE(GEN8_PRIVATE_PAT_LO, pat); |
2998 | I915_WRITE(GEN8_PRIVATE_PAT_HI, pat >> 32); | |
fbe5d36e BW |
2999 | } |
3000 | ||
ee0ce478 VS |
3001 | static void chv_setup_private_ppat(struct drm_i915_private *dev_priv) |
3002 | { | |
3003 | uint64_t pat; | |
3004 | ||
3005 | /* | |
3006 | * Map WB on BDW to snooped on CHV. | |
3007 | * | |
3008 | * Only the snoop bit has meaning for CHV, the rest is | |
3009 | * ignored. | |
3010 | * | |
cf3d262e VS |
3011 | * The hardware will never snoop for certain types of accesses: |
3012 | * - CPU GTT (GMADR->GGTT->no snoop->memory) | |
3013 | * - PPGTT page tables | |
3014 | * - some other special cycles | |
3015 | * | |
3016 | * As with BDW, we also need to consider the following for GT accesses: | |
3017 | * "For GGTT, there is NO pat_sel[2:0] from the entry, | |
3018 | * so RTL will always use the value corresponding to | |
3019 | * pat_sel = 000". | |
3020 | * Which means we must set the snoop bit in PAT entry 0 | |
3021 | * in order to keep the global status page working. | |
ee0ce478 VS |
3022 | */ |
3023 | pat = GEN8_PPAT(0, CHV_PPAT_SNOOP) | | |
3024 | GEN8_PPAT(1, 0) | | |
3025 | GEN8_PPAT(2, 0) | | |
3026 | GEN8_PPAT(3, 0) | | |
3027 | GEN8_PPAT(4, CHV_PPAT_SNOOP) | | |
3028 | GEN8_PPAT(5, CHV_PPAT_SNOOP) | | |
3029 | GEN8_PPAT(6, CHV_PPAT_SNOOP) | | |
3030 | GEN8_PPAT(7, CHV_PPAT_SNOOP); | |
3031 | ||
7e435ad2 VS |
3032 | I915_WRITE(GEN8_PRIVATE_PAT_LO, pat); |
3033 | I915_WRITE(GEN8_PRIVATE_PAT_HI, pat >> 32); | |
ee0ce478 VS |
3034 | } |
3035 | ||
34c998b4 CW |
3036 | static void gen6_gmch_remove(struct i915_address_space *vm) |
3037 | { | |
3038 | struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm); | |
3039 | ||
3040 | iounmap(ggtt->gsm); | |
49d73912 | 3041 | cleanup_scratch_page(vm->i915, &vm->scratch_page); |
34c998b4 CW |
3042 | } |
3043 | ||
d507d735 | 3044 | static int gen8_gmch_probe(struct i915_ggtt *ggtt) |
63340133 | 3045 | { |
49d73912 | 3046 | struct drm_i915_private *dev_priv = ggtt->base.i915; |
97d6d7ab | 3047 | struct pci_dev *pdev = dev_priv->drm.pdev; |
34c998b4 | 3048 | unsigned int size; |
63340133 | 3049 | u16 snb_gmch_ctl; |
63340133 BW |
3050 | |
3051 | /* TODO: We're not aware of mappable constraints on gen8 yet */ | |
97d6d7ab CW |
3052 | ggtt->mappable_base = pci_resource_start(pdev, 2); |
3053 | ggtt->mappable_end = pci_resource_len(pdev, 2); | |
63340133 | 3054 | |
97d6d7ab CW |
3055 | if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(39))) |
3056 | pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(39)); | |
63340133 | 3057 | |
97d6d7ab | 3058 | pci_read_config_word(pdev, SNB_GMCH_CTRL, &snb_gmch_ctl); |
63340133 | 3059 | |
97d6d7ab | 3060 | if (INTEL_GEN(dev_priv) >= 9) { |
d507d735 | 3061 | ggtt->stolen_size = gen9_get_stolen_size(snb_gmch_ctl); |
34c998b4 | 3062 | size = gen8_get_total_gtt_size(snb_gmch_ctl); |
97d6d7ab | 3063 | } else if (IS_CHERRYVIEW(dev_priv)) { |
d507d735 | 3064 | ggtt->stolen_size = chv_get_stolen_size(snb_gmch_ctl); |
34c998b4 | 3065 | size = chv_get_total_gtt_size(snb_gmch_ctl); |
d7f25f23 | 3066 | } else { |
d507d735 | 3067 | ggtt->stolen_size = gen8_get_stolen_size(snb_gmch_ctl); |
34c998b4 | 3068 | size = gen8_get_total_gtt_size(snb_gmch_ctl); |
d7f25f23 | 3069 | } |
63340133 | 3070 | |
34c998b4 | 3071 | ggtt->base.total = (size / sizeof(gen8_pte_t)) << PAGE_SHIFT; |
63340133 | 3072 | |
cc3f90f0 | 3073 | if (IS_CHERRYVIEW(dev_priv) || IS_GEN9_LP(dev_priv)) |
ee0ce478 VS |
3074 | chv_setup_private_ppat(dev_priv); |
3075 | else | |
3076 | bdw_setup_private_ppat(dev_priv); | |
fbe5d36e | 3077 | |
34c998b4 | 3078 | ggtt->base.cleanup = gen6_gmch_remove; |
d507d735 JL |
3079 | ggtt->base.bind_vma = ggtt_bind_vma; |
3080 | ggtt->base.unbind_vma = ggtt_unbind_vma; | |
d6473f56 | 3081 | ggtt->base.insert_page = gen8_ggtt_insert_page; |
f7770bfd | 3082 | ggtt->base.clear_range = nop_clear_range; |
48f112fe | 3083 | if (!USES_FULL_PPGTT(dev_priv) || intel_scanout_needs_vtd_wa(dev_priv)) |
f7770bfd CW |
3084 | ggtt->base.clear_range = gen8_ggtt_clear_range; |
3085 | ||
3086 | ggtt->base.insert_entries = gen8_ggtt_insert_entries; | |
3087 | if (IS_CHERRYVIEW(dev_priv)) | |
3088 | ggtt->base.insert_entries = gen8_ggtt_insert_entries__BKL; | |
3089 | ||
7c3f86b6 CW |
3090 | ggtt->invalidate = gen6_ggtt_invalidate; |
3091 | ||
34c998b4 | 3092 | return ggtt_probe_common(ggtt, size); |
63340133 BW |
3093 | } |
3094 | ||
d507d735 | 3095 | static int gen6_gmch_probe(struct i915_ggtt *ggtt) |
e76e9aeb | 3096 | { |
49d73912 | 3097 | struct drm_i915_private *dev_priv = ggtt->base.i915; |
97d6d7ab | 3098 | struct pci_dev *pdev = dev_priv->drm.pdev; |
34c998b4 | 3099 | unsigned int size; |
e76e9aeb | 3100 | u16 snb_gmch_ctl; |
e76e9aeb | 3101 | |
97d6d7ab CW |
3102 | ggtt->mappable_base = pci_resource_start(pdev, 2); |
3103 | ggtt->mappable_end = pci_resource_len(pdev, 2); | |
41907ddc | 3104 | |
baa09f5f BW |
3105 | /* 64/512MB is the current min/max we actually know of, but this is just |
3106 | * a coarse sanity check. | |
e76e9aeb | 3107 | */ |
34c998b4 | 3108 | if (ggtt->mappable_end < (64<<20) || ggtt->mappable_end > (512<<20)) { |
d507d735 | 3109 | DRM_ERROR("Unknown GMADR size (%llx)\n", ggtt->mappable_end); |
baa09f5f | 3110 | return -ENXIO; |
e76e9aeb BW |
3111 | } |
3112 | ||
97d6d7ab CW |
3113 | if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(40))) |
3114 | pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(40)); | |
3115 | pci_read_config_word(pdev, SNB_GMCH_CTRL, &snb_gmch_ctl); | |
e76e9aeb | 3116 | |
d507d735 | 3117 | ggtt->stolen_size = gen6_get_stolen_size(snb_gmch_ctl); |
e76e9aeb | 3118 | |
34c998b4 CW |
3119 | size = gen6_get_total_gtt_size(snb_gmch_ctl); |
3120 | ggtt->base.total = (size / sizeof(gen6_pte_t)) << PAGE_SHIFT; | |
e76e9aeb | 3121 | |
d507d735 | 3122 | ggtt->base.clear_range = gen6_ggtt_clear_range; |
d6473f56 | 3123 | ggtt->base.insert_page = gen6_ggtt_insert_page; |
d507d735 JL |
3124 | ggtt->base.insert_entries = gen6_ggtt_insert_entries; |
3125 | ggtt->base.bind_vma = ggtt_bind_vma; | |
3126 | ggtt->base.unbind_vma = ggtt_unbind_vma; | |
34c998b4 CW |
3127 | ggtt->base.cleanup = gen6_gmch_remove; |
3128 | ||
7c3f86b6 CW |
3129 | ggtt->invalidate = gen6_ggtt_invalidate; |
3130 | ||
34c998b4 CW |
3131 | if (HAS_EDRAM(dev_priv)) |
3132 | ggtt->base.pte_encode = iris_pte_encode; | |
3133 | else if (IS_HASWELL(dev_priv)) | |
3134 | ggtt->base.pte_encode = hsw_pte_encode; | |
3135 | else if (IS_VALLEYVIEW(dev_priv)) | |
3136 | ggtt->base.pte_encode = byt_pte_encode; | |
3137 | else if (INTEL_GEN(dev_priv) >= 7) | |
3138 | ggtt->base.pte_encode = ivb_pte_encode; | |
3139 | else | |
3140 | ggtt->base.pte_encode = snb_pte_encode; | |
7faf1ab2 | 3141 | |
34c998b4 | 3142 | return ggtt_probe_common(ggtt, size); |
e76e9aeb BW |
3143 | } |
3144 | ||
34c998b4 | 3145 | static void i915_gmch_remove(struct i915_address_space *vm) |
e76e9aeb | 3146 | { |
34c998b4 | 3147 | intel_gmch_remove(); |
644ec02b | 3148 | } |
baa09f5f | 3149 | |
d507d735 | 3150 | static int i915_gmch_probe(struct i915_ggtt *ggtt) |
baa09f5f | 3151 | { |
49d73912 | 3152 | struct drm_i915_private *dev_priv = ggtt->base.i915; |
baa09f5f BW |
3153 | int ret; |
3154 | ||
91c8a326 | 3155 | ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->drm.pdev, NULL); |
baa09f5f BW |
3156 | if (!ret) { |
3157 | DRM_ERROR("failed to set up gmch\n"); | |
3158 | return -EIO; | |
3159 | } | |
3160 | ||
edd1f2fe CW |
3161 | intel_gtt_get(&ggtt->base.total, |
3162 | &ggtt->stolen_size, | |
3163 | &ggtt->mappable_base, | |
3164 | &ggtt->mappable_end); | |
baa09f5f | 3165 | |
97d6d7ab | 3166 | ggtt->do_idle_maps = needs_idle_maps(dev_priv); |
d6473f56 | 3167 | ggtt->base.insert_page = i915_ggtt_insert_page; |
d507d735 JL |
3168 | ggtt->base.insert_entries = i915_ggtt_insert_entries; |
3169 | ggtt->base.clear_range = i915_ggtt_clear_range; | |
3170 | ggtt->base.bind_vma = ggtt_bind_vma; | |
3171 | ggtt->base.unbind_vma = ggtt_unbind_vma; | |
34c998b4 | 3172 | ggtt->base.cleanup = i915_gmch_remove; |
baa09f5f | 3173 | |
7c3f86b6 CW |
3174 | ggtt->invalidate = gmch_ggtt_invalidate; |
3175 | ||
d507d735 | 3176 | if (unlikely(ggtt->do_idle_maps)) |
c0a7f818 CW |
3177 | DRM_INFO("applying Ironlake quirks for intel_iommu\n"); |
3178 | ||
baa09f5f BW |
3179 | return 0; |
3180 | } | |
3181 | ||
d85489d3 | 3182 | /** |
0088e522 | 3183 | * i915_ggtt_probe_hw - Probe GGTT hardware location |
97d6d7ab | 3184 | * @dev_priv: i915 device |
d85489d3 | 3185 | */ |
97d6d7ab | 3186 | int i915_ggtt_probe_hw(struct drm_i915_private *dev_priv) |
baa09f5f | 3187 | { |
62106b4f | 3188 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
baa09f5f BW |
3189 | int ret; |
3190 | ||
49d73912 | 3191 | ggtt->base.i915 = dev_priv; |
c114f76a | 3192 | |
34c998b4 CW |
3193 | if (INTEL_GEN(dev_priv) <= 5) |
3194 | ret = i915_gmch_probe(ggtt); | |
3195 | else if (INTEL_GEN(dev_priv) < 8) | |
3196 | ret = gen6_gmch_probe(ggtt); | |
3197 | else | |
3198 | ret = gen8_gmch_probe(ggtt); | |
a54c0c27 | 3199 | if (ret) |
baa09f5f | 3200 | return ret; |
baa09f5f | 3201 | |
db9309a5 CW |
3202 | /* Trim the GGTT to fit the GuC mappable upper range (when enabled). |
3203 | * This is easier than doing range restriction on the fly, as we | |
3204 | * currently don't have any bits spare to pass in this upper | |
3205 | * restriction! | |
3206 | */ | |
3207 | if (HAS_GUC(dev_priv) && i915.enable_guc_loading) { | |
3208 | ggtt->base.total = min_t(u64, ggtt->base.total, GUC_GGTT_TOP); | |
3209 | ggtt->mappable_end = min(ggtt->mappable_end, ggtt->base.total); | |
3210 | } | |
3211 | ||
c890e2d5 CW |
3212 | if ((ggtt->base.total - 1) >> 32) { |
3213 | DRM_ERROR("We never expected a Global GTT with more than 32bits" | |
f6b9d5ca | 3214 | " of address space! Found %lldM!\n", |
c890e2d5 CW |
3215 | ggtt->base.total >> 20); |
3216 | ggtt->base.total = 1ULL << 32; | |
3217 | ggtt->mappable_end = min(ggtt->mappable_end, ggtt->base.total); | |
3218 | } | |
3219 | ||
f6b9d5ca CW |
3220 | if (ggtt->mappable_end > ggtt->base.total) { |
3221 | DRM_ERROR("mappable aperture extends past end of GGTT," | |
3222 | " aperture=%llx, total=%llx\n", | |
3223 | ggtt->mappable_end, ggtt->base.total); | |
3224 | ggtt->mappable_end = ggtt->base.total; | |
3225 | } | |
3226 | ||
baa09f5f | 3227 | /* GMADR is the PCI mmio aperture into the global GTT. */ |
c44ef60e | 3228 | DRM_INFO("Memory usable by graphics device = %lluM\n", |
62106b4f JL |
3229 | ggtt->base.total >> 20); |
3230 | DRM_DEBUG_DRIVER("GMADR size = %lldM\n", ggtt->mappable_end >> 20); | |
edd1f2fe | 3231 | DRM_DEBUG_DRIVER("GTT stolen size = %uM\n", ggtt->stolen_size >> 20); |
5db6c735 DV |
3232 | #ifdef CONFIG_INTEL_IOMMU |
3233 | if (intel_iommu_gfx_mapped) | |
3234 | DRM_INFO("VT-d active for gfx access\n"); | |
3235 | #endif | |
baa09f5f BW |
3236 | |
3237 | return 0; | |
0088e522 CW |
3238 | } |
3239 | ||
3240 | /** | |
3241 | * i915_ggtt_init_hw - Initialize GGTT hardware | |
97d6d7ab | 3242 | * @dev_priv: i915 device |
0088e522 | 3243 | */ |
97d6d7ab | 3244 | int i915_ggtt_init_hw(struct drm_i915_private *dev_priv) |
0088e522 | 3245 | { |
0088e522 CW |
3246 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
3247 | int ret; | |
3248 | ||
f6b9d5ca CW |
3249 | INIT_LIST_HEAD(&dev_priv->vm_list); |
3250 | ||
a6508ded CW |
3251 | /* Note that we use page colouring to enforce a guard page at the |
3252 | * end of the address space. This is required as the CS may prefetch | |
3253 | * beyond the end of the batch buffer, across the page boundary, | |
3254 | * and beyond the end of the GTT if we do not provide a guard. | |
f6b9d5ca | 3255 | */ |
80b204bc | 3256 | mutex_lock(&dev_priv->drm.struct_mutex); |
80b204bc | 3257 | i915_address_space_init(&ggtt->base, dev_priv, "[global]"); |
a6508ded | 3258 | if (!HAS_LLC(dev_priv) && !USES_PPGTT(dev_priv)) |
f6b9d5ca | 3259 | ggtt->base.mm.color_adjust = i915_gtt_color_adjust; |
80b204bc | 3260 | mutex_unlock(&dev_priv->drm.struct_mutex); |
f6b9d5ca | 3261 | |
f7bbe788 CW |
3262 | if (!io_mapping_init_wc(&dev_priv->ggtt.mappable, |
3263 | dev_priv->ggtt.mappable_base, | |
3264 | dev_priv->ggtt.mappable_end)) { | |
f6b9d5ca CW |
3265 | ret = -EIO; |
3266 | goto out_gtt_cleanup; | |
3267 | } | |
3268 | ||
3269 | ggtt->mtrr = arch_phys_wc_add(ggtt->mappable_base, ggtt->mappable_end); | |
3270 | ||
0088e522 CW |
3271 | /* |
3272 | * Initialise stolen early so that we may reserve preallocated | |
3273 | * objects for the BIOS to KMS transition. | |
3274 | */ | |
7ace3d30 | 3275 | ret = i915_gem_init_stolen(dev_priv); |
0088e522 CW |
3276 | if (ret) |
3277 | goto out_gtt_cleanup; | |
3278 | ||
3279 | return 0; | |
a4eba47b ID |
3280 | |
3281 | out_gtt_cleanup: | |
72e96d64 | 3282 | ggtt->base.cleanup(&ggtt->base); |
a4eba47b | 3283 | return ret; |
baa09f5f | 3284 | } |
6f65e29a | 3285 | |
97d6d7ab | 3286 | int i915_ggtt_enable_hw(struct drm_i915_private *dev_priv) |
ac840ae5 | 3287 | { |
97d6d7ab | 3288 | if (INTEL_GEN(dev_priv) < 6 && !intel_enable_gtt()) |
ac840ae5 VS |
3289 | return -EIO; |
3290 | ||
3291 | return 0; | |
3292 | } | |
3293 | ||
7c3f86b6 CW |
3294 | void i915_ggtt_enable_guc(struct drm_i915_private *i915) |
3295 | { | |
3296 | i915->ggtt.invalidate = guc_ggtt_invalidate; | |
3297 | } | |
3298 | ||
3299 | void i915_ggtt_disable_guc(struct drm_i915_private *i915) | |
3300 | { | |
3301 | i915->ggtt.invalidate = gen6_ggtt_invalidate; | |
3302 | } | |
3303 | ||
275a991c | 3304 | void i915_gem_restore_gtt_mappings(struct drm_i915_private *dev_priv) |
fa42331b | 3305 | { |
72e96d64 | 3306 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
fbb30a5c | 3307 | struct drm_i915_gem_object *obj, *on; |
fa42331b | 3308 | |
dc97997a | 3309 | i915_check_and_clear_faults(dev_priv); |
fa42331b DV |
3310 | |
3311 | /* First fill our portion of the GTT with scratch pages */ | |
4fb84d99 | 3312 | ggtt->base.clear_range(&ggtt->base, ggtt->base.start, ggtt->base.total); |
fa42331b | 3313 | |
fbb30a5c CW |
3314 | ggtt->base.closed = true; /* skip rewriting PTE on VMA unbind */ |
3315 | ||
3316 | /* clflush objects bound into the GGTT and rebind them. */ | |
3317 | list_for_each_entry_safe(obj, on, | |
56cea323 | 3318 | &dev_priv->mm.bound_list, global_link) { |
fbb30a5c CW |
3319 | bool ggtt_bound = false; |
3320 | struct i915_vma *vma; | |
3321 | ||
1c7f4bca | 3322 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
72e96d64 | 3323 | if (vma->vm != &ggtt->base) |
2c3d9984 | 3324 | continue; |
fa42331b | 3325 | |
fbb30a5c CW |
3326 | if (!i915_vma_unbind(vma)) |
3327 | continue; | |
3328 | ||
2c3d9984 TU |
3329 | WARN_ON(i915_vma_bind(vma, obj->cache_level, |
3330 | PIN_UPDATE)); | |
fbb30a5c | 3331 | ggtt_bound = true; |
2c3d9984 TU |
3332 | } |
3333 | ||
fbb30a5c | 3334 | if (ggtt_bound) |
975f7ff4 | 3335 | WARN_ON(i915_gem_object_set_to_gtt_domain(obj, false)); |
2c3d9984 | 3336 | } |
fa42331b | 3337 | |
fbb30a5c CW |
3338 | ggtt->base.closed = false; |
3339 | ||
275a991c | 3340 | if (INTEL_GEN(dev_priv) >= 8) { |
cc3f90f0 | 3341 | if (IS_CHERRYVIEW(dev_priv) || IS_GEN9_LP(dev_priv)) |
fa42331b DV |
3342 | chv_setup_private_ppat(dev_priv); |
3343 | else | |
3344 | bdw_setup_private_ppat(dev_priv); | |
3345 | ||
3346 | return; | |
3347 | } | |
3348 | ||
275a991c | 3349 | if (USES_PPGTT(dev_priv)) { |
72e96d64 JL |
3350 | struct i915_address_space *vm; |
3351 | ||
fa42331b DV |
3352 | list_for_each_entry(vm, &dev_priv->vm_list, global_link) { |
3353 | /* TODO: Perhaps it shouldn't be gen6 specific */ | |
3354 | ||
e5716f55 | 3355 | struct i915_hw_ppgtt *ppgtt; |
fa42331b | 3356 | |
2bfa996e | 3357 | if (i915_is_ggtt(vm)) |
fa42331b | 3358 | ppgtt = dev_priv->mm.aliasing_ppgtt; |
e5716f55 JL |
3359 | else |
3360 | ppgtt = i915_vm_to_ppgtt(vm); | |
fa42331b DV |
3361 | |
3362 | gen6_write_page_range(dev_priv, &ppgtt->pd, | |
3363 | 0, ppgtt->base.total); | |
3364 | } | |
3365 | } | |
3366 | ||
7c3f86b6 | 3367 | i915_ggtt_invalidate(dev_priv); |
fa42331b DV |
3368 | } |
3369 | ||
804beb4b | 3370 | static struct scatterlist * |
2d7f3bdb | 3371 | rotate_pages(const dma_addr_t *in, unsigned int offset, |
804beb4b | 3372 | unsigned int width, unsigned int height, |
87130255 | 3373 | unsigned int stride, |
804beb4b | 3374 | struct sg_table *st, struct scatterlist *sg) |
50470bb0 TU |
3375 | { |
3376 | unsigned int column, row; | |
3377 | unsigned int src_idx; | |
50470bb0 | 3378 | |
50470bb0 | 3379 | for (column = 0; column < width; column++) { |
87130255 | 3380 | src_idx = stride * (height - 1) + column; |
50470bb0 TU |
3381 | for (row = 0; row < height; row++) { |
3382 | st->nents++; | |
3383 | /* We don't need the pages, but need to initialize | |
3384 | * the entries so the sg list can be happily traversed. | |
3385 | * The only thing we need are DMA addresses. | |
3386 | */ | |
3387 | sg_set_page(sg, NULL, PAGE_SIZE, 0); | |
804beb4b | 3388 | sg_dma_address(sg) = in[offset + src_idx]; |
50470bb0 TU |
3389 | sg_dma_len(sg) = PAGE_SIZE; |
3390 | sg = sg_next(sg); | |
87130255 | 3391 | src_idx -= stride; |
50470bb0 TU |
3392 | } |
3393 | } | |
804beb4b TU |
3394 | |
3395 | return sg; | |
50470bb0 TU |
3396 | } |
3397 | ||
3398 | static struct sg_table * | |
6687c906 | 3399 | intel_rotate_fb_obj_pages(const struct intel_rotation_info *rot_info, |
50470bb0 TU |
3400 | struct drm_i915_gem_object *obj) |
3401 | { | |
85d1225e | 3402 | const size_t n_pages = obj->base.size / PAGE_SIZE; |
6687c906 | 3403 | unsigned int size = intel_rotation_info_size(rot_info); |
85d1225e DG |
3404 | struct sgt_iter sgt_iter; |
3405 | dma_addr_t dma_addr; | |
50470bb0 TU |
3406 | unsigned long i; |
3407 | dma_addr_t *page_addr_list; | |
3408 | struct sg_table *st; | |
89e3e142 | 3409 | struct scatterlist *sg; |
1d00dad5 | 3410 | int ret = -ENOMEM; |
50470bb0 | 3411 | |
50470bb0 | 3412 | /* Allocate a temporary list of source pages for random access. */ |
85d1225e | 3413 | page_addr_list = drm_malloc_gfp(n_pages, |
f2a85e19 CW |
3414 | sizeof(dma_addr_t), |
3415 | GFP_TEMPORARY); | |
50470bb0 TU |
3416 | if (!page_addr_list) |
3417 | return ERR_PTR(ret); | |
3418 | ||
3419 | /* Allocate target SG list. */ | |
3420 | st = kmalloc(sizeof(*st), GFP_KERNEL); | |
3421 | if (!st) | |
3422 | goto err_st_alloc; | |
3423 | ||
6687c906 | 3424 | ret = sg_alloc_table(st, size, GFP_KERNEL); |
50470bb0 TU |
3425 | if (ret) |
3426 | goto err_sg_alloc; | |
3427 | ||
3428 | /* Populate source page list from the object. */ | |
3429 | i = 0; | |
a4f5ea64 | 3430 | for_each_sgt_dma(dma_addr, sgt_iter, obj->mm.pages) |
85d1225e | 3431 | page_addr_list[i++] = dma_addr; |
50470bb0 | 3432 | |
85d1225e | 3433 | GEM_BUG_ON(i != n_pages); |
11f20322 VS |
3434 | st->nents = 0; |
3435 | sg = st->sgl; | |
3436 | ||
6687c906 VS |
3437 | for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++) { |
3438 | sg = rotate_pages(page_addr_list, rot_info->plane[i].offset, | |
3439 | rot_info->plane[i].width, rot_info->plane[i].height, | |
3440 | rot_info->plane[i].stride, st, sg); | |
89e3e142 TU |
3441 | } |
3442 | ||
6687c906 VS |
3443 | DRM_DEBUG_KMS("Created rotated page mapping for object size %zu (%ux%u tiles, %u pages)\n", |
3444 | obj->base.size, rot_info->plane[0].width, rot_info->plane[0].height, size); | |
50470bb0 TU |
3445 | |
3446 | drm_free_large(page_addr_list); | |
3447 | ||
3448 | return st; | |
3449 | ||
3450 | err_sg_alloc: | |
3451 | kfree(st); | |
3452 | err_st_alloc: | |
3453 | drm_free_large(page_addr_list); | |
3454 | ||
6687c906 VS |
3455 | DRM_DEBUG_KMS("Failed to create rotated mapping for object size %zu! (%ux%u tiles, %u pages)\n", |
3456 | obj->base.size, rot_info->plane[0].width, rot_info->plane[0].height, size); | |
3457 | ||
50470bb0 TU |
3458 | return ERR_PTR(ret); |
3459 | } | |
ec7adb6e | 3460 | |
8bd7ef16 JL |
3461 | static struct sg_table * |
3462 | intel_partial_pages(const struct i915_ggtt_view *view, | |
3463 | struct drm_i915_gem_object *obj) | |
3464 | { | |
3465 | struct sg_table *st; | |
d2a84a76 | 3466 | struct scatterlist *sg, *iter; |
8bab1193 | 3467 | unsigned int count = view->partial.size; |
d2a84a76 | 3468 | unsigned int offset; |
8bd7ef16 JL |
3469 | int ret = -ENOMEM; |
3470 | ||
3471 | st = kmalloc(sizeof(*st), GFP_KERNEL); | |
3472 | if (!st) | |
3473 | goto err_st_alloc; | |
3474 | ||
d2a84a76 | 3475 | ret = sg_alloc_table(st, count, GFP_KERNEL); |
8bd7ef16 JL |
3476 | if (ret) |
3477 | goto err_sg_alloc; | |
3478 | ||
8bab1193 | 3479 | iter = i915_gem_object_get_sg(obj, view->partial.offset, &offset); |
d2a84a76 CW |
3480 | GEM_BUG_ON(!iter); |
3481 | ||
8bd7ef16 JL |
3482 | sg = st->sgl; |
3483 | st->nents = 0; | |
d2a84a76 CW |
3484 | do { |
3485 | unsigned int len; | |
8bd7ef16 | 3486 | |
d2a84a76 CW |
3487 | len = min(iter->length - (offset << PAGE_SHIFT), |
3488 | count << PAGE_SHIFT); | |
3489 | sg_set_page(sg, NULL, len, 0); | |
3490 | sg_dma_address(sg) = | |
3491 | sg_dma_address(iter) + (offset << PAGE_SHIFT); | |
3492 | sg_dma_len(sg) = len; | |
8bd7ef16 | 3493 | |
8bd7ef16 | 3494 | st->nents++; |
d2a84a76 CW |
3495 | count -= len >> PAGE_SHIFT; |
3496 | if (count == 0) { | |
3497 | sg_mark_end(sg); | |
3498 | return st; | |
3499 | } | |
8bd7ef16 | 3500 | |
d2a84a76 CW |
3501 | sg = __sg_next(sg); |
3502 | iter = __sg_next(iter); | |
3503 | offset = 0; | |
3504 | } while (1); | |
8bd7ef16 JL |
3505 | |
3506 | err_sg_alloc: | |
3507 | kfree(st); | |
3508 | err_st_alloc: | |
3509 | return ERR_PTR(ret); | |
3510 | } | |
3511 | ||
70b9f6f8 | 3512 | static int |
50470bb0 | 3513 | i915_get_ggtt_vma_pages(struct i915_vma *vma) |
fe14d5f4 | 3514 | { |
50470bb0 TU |
3515 | int ret = 0; |
3516 | ||
2c3a3f44 CW |
3517 | /* The vma->pages are only valid within the lifespan of the borrowed |
3518 | * obj->mm.pages. When the obj->mm.pages sg_table is regenerated, so | |
3519 | * must be the vma->pages. A simple rule is that vma->pages must only | |
3520 | * be accessed when the obj->mm.pages are pinned. | |
3521 | */ | |
3522 | GEM_BUG_ON(!i915_gem_object_has_pinned_pages(vma->obj)); | |
3523 | ||
247177dd | 3524 | if (vma->pages) |
fe14d5f4 TU |
3525 | return 0; |
3526 | ||
3527 | if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) | |
a4f5ea64 | 3528 | vma->pages = vma->obj->mm.pages; |
50470bb0 | 3529 | else if (vma->ggtt_view.type == I915_GGTT_VIEW_ROTATED) |
247177dd | 3530 | vma->pages = |
8bab1193 CW |
3531 | intel_rotate_fb_obj_pages(&vma->ggtt_view.rotated, |
3532 | vma->obj); | |
8bd7ef16 | 3533 | else if (vma->ggtt_view.type == I915_GGTT_VIEW_PARTIAL) |
247177dd | 3534 | vma->pages = intel_partial_pages(&vma->ggtt_view, vma->obj); |
fe14d5f4 TU |
3535 | else |
3536 | WARN_ONCE(1, "GGTT view %u not implemented!\n", | |
3537 | vma->ggtt_view.type); | |
3538 | ||
247177dd | 3539 | if (!vma->pages) { |
ec7adb6e | 3540 | DRM_ERROR("Failed to get pages for GGTT view type %u!\n", |
fe14d5f4 | 3541 | vma->ggtt_view.type); |
50470bb0 | 3542 | ret = -EINVAL; |
247177dd CW |
3543 | } else if (IS_ERR(vma->pages)) { |
3544 | ret = PTR_ERR(vma->pages); | |
3545 | vma->pages = NULL; | |
50470bb0 TU |
3546 | DRM_ERROR("Failed to get pages for VMA view type %u (%d)!\n", |
3547 | vma->ggtt_view.type, ret); | |
fe14d5f4 TU |
3548 | } |
3549 | ||
50470bb0 | 3550 | return ret; |
fe14d5f4 TU |
3551 | } |
3552 | ||
625d988a CW |
3553 | /** |
3554 | * i915_gem_gtt_reserve - reserve a node in an address_space (GTT) | |
a4dbf7cf CW |
3555 | * @vm: the &struct i915_address_space |
3556 | * @node: the &struct drm_mm_node (typically i915_vma.mode) | |
3557 | * @size: how much space to allocate inside the GTT, | |
3558 | * must be #I915_GTT_PAGE_SIZE aligned | |
3559 | * @offset: where to insert inside the GTT, | |
3560 | * must be #I915_GTT_MIN_ALIGNMENT aligned, and the node | |
3561 | * (@offset + @size) must fit within the address space | |
3562 | * @color: color to apply to node, if this node is not from a VMA, | |
3563 | * color must be #I915_COLOR_UNEVICTABLE | |
3564 | * @flags: control search and eviction behaviour | |
625d988a CW |
3565 | * |
3566 | * i915_gem_gtt_reserve() tries to insert the @node at the exact @offset inside | |
3567 | * the address space (using @size and @color). If the @node does not fit, it | |
3568 | * tries to evict any overlapping nodes from the GTT, including any | |
3569 | * neighbouring nodes if the colors do not match (to ensure guard pages between | |
3570 | * differing domains). See i915_gem_evict_for_node() for the gory details | |
3571 | * on the eviction algorithm. #PIN_NONBLOCK may used to prevent waiting on | |
3572 | * evicting active overlapping objects, and any overlapping node that is pinned | |
3573 | * or marked as unevictable will also result in failure. | |
3574 | * | |
3575 | * Returns: 0 on success, -ENOSPC if no suitable hole is found, -EINTR if | |
3576 | * asked to wait for eviction and interrupted. | |
3577 | */ | |
3578 | int i915_gem_gtt_reserve(struct i915_address_space *vm, | |
3579 | struct drm_mm_node *node, | |
3580 | u64 size, u64 offset, unsigned long color, | |
3581 | unsigned int flags) | |
3582 | { | |
3583 | int err; | |
3584 | ||
3585 | GEM_BUG_ON(!size); | |
3586 | GEM_BUG_ON(!IS_ALIGNED(size, I915_GTT_PAGE_SIZE)); | |
3587 | GEM_BUG_ON(!IS_ALIGNED(offset, I915_GTT_MIN_ALIGNMENT)); | |
3588 | GEM_BUG_ON(range_overflows(offset, size, vm->total)); | |
3fec7ec4 | 3589 | GEM_BUG_ON(vm == &vm->i915->mm.aliasing_ppgtt->base); |
9734ad13 | 3590 | GEM_BUG_ON(drm_mm_node_allocated(node)); |
625d988a CW |
3591 | |
3592 | node->size = size; | |
3593 | node->start = offset; | |
3594 | node->color = color; | |
3595 | ||
3596 | err = drm_mm_reserve_node(&vm->mm, node); | |
3597 | if (err != -ENOSPC) | |
3598 | return err; | |
3599 | ||
3600 | err = i915_gem_evict_for_node(vm, node, flags); | |
3601 | if (err == 0) | |
3602 | err = drm_mm_reserve_node(&vm->mm, node); | |
3603 | ||
3604 | return err; | |
3605 | } | |
3606 | ||
606fec95 CW |
3607 | static u64 random_offset(u64 start, u64 end, u64 len, u64 align) |
3608 | { | |
3609 | u64 range, addr; | |
3610 | ||
3611 | GEM_BUG_ON(range_overflows(start, len, end)); | |
3612 | GEM_BUG_ON(round_up(start, align) > round_down(end - len, align)); | |
3613 | ||
3614 | range = round_down(end - len, align) - round_up(start, align); | |
3615 | if (range) { | |
3616 | if (sizeof(unsigned long) == sizeof(u64)) { | |
3617 | addr = get_random_long(); | |
3618 | } else { | |
3619 | addr = get_random_int(); | |
3620 | if (range > U32_MAX) { | |
3621 | addr <<= 32; | |
3622 | addr |= get_random_int(); | |
3623 | } | |
3624 | } | |
3625 | div64_u64_rem(addr, range, &addr); | |
3626 | start += addr; | |
3627 | } | |
3628 | ||
3629 | return round_up(start, align); | |
3630 | } | |
3631 | ||
e007b19d CW |
3632 | /** |
3633 | * i915_gem_gtt_insert - insert a node into an address_space (GTT) | |
a4dbf7cf CW |
3634 | * @vm: the &struct i915_address_space |
3635 | * @node: the &struct drm_mm_node (typically i915_vma.node) | |
3636 | * @size: how much space to allocate inside the GTT, | |
3637 | * must be #I915_GTT_PAGE_SIZE aligned | |
3638 | * @alignment: required alignment of starting offset, may be 0 but | |
3639 | * if specified, this must be a power-of-two and at least | |
3640 | * #I915_GTT_MIN_ALIGNMENT | |
3641 | * @color: color to apply to node | |
3642 | * @start: start of any range restriction inside GTT (0 for all), | |
e007b19d | 3643 | * must be #I915_GTT_PAGE_SIZE aligned |
a4dbf7cf CW |
3644 | * @end: end of any range restriction inside GTT (U64_MAX for all), |
3645 | * must be #I915_GTT_PAGE_SIZE aligned if not U64_MAX | |
3646 | * @flags: control search and eviction behaviour | |
e007b19d CW |
3647 | * |
3648 | * i915_gem_gtt_insert() first searches for an available hole into which | |
3649 | * is can insert the node. The hole address is aligned to @alignment and | |
3650 | * its @size must then fit entirely within the [@start, @end] bounds. The | |
3651 | * nodes on either side of the hole must match @color, or else a guard page | |
3652 | * will be inserted between the two nodes (or the node evicted). If no | |
606fec95 CW |
3653 | * suitable hole is found, first a victim is randomly selected and tested |
3654 | * for eviction, otherwise then the LRU list of objects within the GTT | |
e007b19d CW |
3655 | * is scanned to find the first set of replacement nodes to create the hole. |
3656 | * Those old overlapping nodes are evicted from the GTT (and so must be | |
3657 | * rebound before any future use). Any node that is currently pinned cannot | |
3658 | * be evicted (see i915_vma_pin()). Similar if the node's VMA is currently | |
3659 | * active and #PIN_NONBLOCK is specified, that node is also skipped when | |
3660 | * searching for an eviction candidate. See i915_gem_evict_something() for | |
3661 | * the gory details on the eviction algorithm. | |
3662 | * | |
3663 | * Returns: 0 on success, -ENOSPC if no suitable hole is found, -EINTR if | |
3664 | * asked to wait for eviction and interrupted. | |
3665 | */ | |
3666 | int i915_gem_gtt_insert(struct i915_address_space *vm, | |
3667 | struct drm_mm_node *node, | |
3668 | u64 size, u64 alignment, unsigned long color, | |
3669 | u64 start, u64 end, unsigned int flags) | |
3670 | { | |
3671 | u32 search_flag, alloc_flag; | |
606fec95 | 3672 | u64 offset; |
e007b19d CW |
3673 | int err; |
3674 | ||
3675 | lockdep_assert_held(&vm->i915->drm.struct_mutex); | |
3676 | GEM_BUG_ON(!size); | |
3677 | GEM_BUG_ON(!IS_ALIGNED(size, I915_GTT_PAGE_SIZE)); | |
3678 | GEM_BUG_ON(alignment && !is_power_of_2(alignment)); | |
3679 | GEM_BUG_ON(alignment && !IS_ALIGNED(alignment, I915_GTT_MIN_ALIGNMENT)); | |
3680 | GEM_BUG_ON(start >= end); | |
3681 | GEM_BUG_ON(start > 0 && !IS_ALIGNED(start, I915_GTT_PAGE_SIZE)); | |
3682 | GEM_BUG_ON(end < U64_MAX && !IS_ALIGNED(end, I915_GTT_PAGE_SIZE)); | |
3fec7ec4 | 3683 | GEM_BUG_ON(vm == &vm->i915->mm.aliasing_ppgtt->base); |
9734ad13 | 3684 | GEM_BUG_ON(drm_mm_node_allocated(node)); |
e007b19d CW |
3685 | |
3686 | if (unlikely(range_overflows(start, size, end))) | |
3687 | return -ENOSPC; | |
3688 | ||
3689 | if (unlikely(round_up(start, alignment) > round_down(end - size, alignment))) | |
3690 | return -ENOSPC; | |
3691 | ||
3692 | if (flags & PIN_HIGH) { | |
3693 | search_flag = DRM_MM_SEARCH_BELOW; | |
3694 | alloc_flag = DRM_MM_CREATE_TOP; | |
3695 | } else { | |
3696 | search_flag = DRM_MM_SEARCH_DEFAULT; | |
3697 | alloc_flag = DRM_MM_CREATE_DEFAULT; | |
3698 | } | |
3699 | ||
3700 | /* We only allocate in PAGE_SIZE/GTT_PAGE_SIZE (4096) chunks, | |
3701 | * so we know that we always have a minimum alignment of 4096. | |
3702 | * The drm_mm range manager is optimised to return results | |
3703 | * with zero alignment, so where possible use the optimal | |
3704 | * path. | |
3705 | */ | |
3706 | BUILD_BUG_ON(I915_GTT_MIN_ALIGNMENT > I915_GTT_PAGE_SIZE); | |
3707 | if (alignment <= I915_GTT_MIN_ALIGNMENT) | |
3708 | alignment = 0; | |
3709 | ||
3710 | err = drm_mm_insert_node_in_range_generic(&vm->mm, node, | |
3711 | size, alignment, color, | |
3712 | start, end, | |
3713 | search_flag, alloc_flag); | |
3714 | if (err != -ENOSPC) | |
3715 | return err; | |
3716 | ||
606fec95 CW |
3717 | /* No free space, pick a slot at random. |
3718 | * | |
3719 | * There is a pathological case here using a GTT shared between | |
3720 | * mmap and GPU (i.e. ggtt/aliasing_ppgtt but not full-ppgtt): | |
3721 | * | |
3722 | * |<-- 256 MiB aperture -->||<-- 1792 MiB unmappable -->| | |
3723 | * (64k objects) (448k objects) | |
3724 | * | |
3725 | * Now imagine that the eviction LRU is ordered top-down (just because | |
3726 | * pathology meets real life), and that we need to evict an object to | |
3727 | * make room inside the aperture. The eviction scan then has to walk | |
3728 | * the 448k list before it finds one within range. And now imagine that | |
3729 | * it has to search for a new hole between every byte inside the memcpy, | |
3730 | * for several simultaneous clients. | |
3731 | * | |
3732 | * On a full-ppgtt system, if we have run out of available space, there | |
3733 | * will be lots and lots of objects in the eviction list! Again, | |
3734 | * searching that LRU list may be slow if we are also applying any | |
3735 | * range restrictions (e.g. restriction to low 4GiB) and so, for | |
3736 | * simplicity and similarilty between different GTT, try the single | |
3737 | * random replacement first. | |
3738 | */ | |
3739 | offset = random_offset(start, end, | |
3740 | size, alignment ?: I915_GTT_MIN_ALIGNMENT); | |
3741 | err = i915_gem_gtt_reserve(vm, node, size, offset, color, flags); | |
3742 | if (err != -ENOSPC) | |
3743 | return err; | |
3744 | ||
3745 | /* Randomly selected placement is pinned, do a search */ | |
e007b19d CW |
3746 | err = i915_gem_evict_something(vm, size, alignment, color, |
3747 | start, end, flags); | |
3748 | if (err) | |
3749 | return err; | |
3750 | ||
3751 | search_flag = DRM_MM_SEARCH_DEFAULT; | |
3752 | return drm_mm_insert_node_in_range_generic(&vm->mm, node, | |
3753 | size, alignment, color, | |
3754 | start, end, | |
3755 | search_flag, alloc_flag); | |
3756 | } |