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76aaf220 DV |
1 | /* |
2 | * Copyright © 2010 Daniel Vetter | |
c4ac524c | 3 | * Copyright © 2011-2014 Intel Corporation |
76aaf220 DV |
4 | * |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
22 | * IN THE SOFTWARE. | |
23 | * | |
24 | */ | |
25 | ||
aae4a3d8 CW |
26 | #include <linux/slab.h> /* fault-inject.h is not standalone! */ |
27 | ||
28 | #include <linux/fault-inject.h> | |
e007b19d | 29 | #include <linux/log2.h> |
606fec95 | 30 | #include <linux/random.h> |
0e46ce2e | 31 | #include <linux/seq_file.h> |
5bab6f60 | 32 | #include <linux/stop_machine.h> |
e007b19d | 33 | |
ed3ba079 LA |
34 | #include <asm/set_memory.h> |
35 | ||
760285e7 DH |
36 | #include <drm/drmP.h> |
37 | #include <drm/i915_drm.h> | |
e007b19d | 38 | |
76aaf220 | 39 | #include "i915_drv.h" |
5dda8fa3 | 40 | #include "i915_vgpu.h" |
76aaf220 DV |
41 | #include "i915_trace.h" |
42 | #include "intel_drv.h" | |
d07f0e59 | 43 | #include "intel_frontbuffer.h" |
76aaf220 | 44 | |
bb8f9cff CW |
45 | #define I915_GFP_DMA (GFP_KERNEL | __GFP_HIGHMEM) |
46 | ||
45f8f69a TU |
47 | /** |
48 | * DOC: Global GTT views | |
49 | * | |
50 | * Background and previous state | |
51 | * | |
52 | * Historically objects could exists (be bound) in global GTT space only as | |
53 | * singular instances with a view representing all of the object's backing pages | |
54 | * in a linear fashion. This view will be called a normal view. | |
55 | * | |
56 | * To support multiple views of the same object, where the number of mapped | |
57 | * pages is not equal to the backing store, or where the layout of the pages | |
58 | * is not linear, concept of a GGTT view was added. | |
59 | * | |
60 | * One example of an alternative view is a stereo display driven by a single | |
61 | * image. In this case we would have a framebuffer looking like this | |
62 | * (2x2 pages): | |
63 | * | |
64 | * 12 | |
65 | * 34 | |
66 | * | |
67 | * Above would represent a normal GGTT view as normally mapped for GPU or CPU | |
68 | * rendering. In contrast, fed to the display engine would be an alternative | |
69 | * view which could look something like this: | |
70 | * | |
71 | * 1212 | |
72 | * 3434 | |
73 | * | |
74 | * In this example both the size and layout of pages in the alternative view is | |
75 | * different from the normal view. | |
76 | * | |
77 | * Implementation and usage | |
78 | * | |
79 | * GGTT views are implemented using VMAs and are distinguished via enum | |
80 | * i915_ggtt_view_type and struct i915_ggtt_view. | |
81 | * | |
82 | * A new flavour of core GEM functions which work with GGTT bound objects were | |
ec7adb6e JL |
83 | * added with the _ggtt_ infix, and sometimes with _view postfix to avoid |
84 | * renaming in large amounts of code. They take the struct i915_ggtt_view | |
85 | * parameter encapsulating all metadata required to implement a view. | |
45f8f69a TU |
86 | * |
87 | * As a helper for callers which are only interested in the normal view, | |
88 | * globally const i915_ggtt_view_normal singleton instance exists. All old core | |
89 | * GEM API functions, the ones not taking the view parameter, are operating on, | |
90 | * or with the normal GGTT view. | |
91 | * | |
92 | * Code wanting to add or use a new GGTT view needs to: | |
93 | * | |
94 | * 1. Add a new enum with a suitable name. | |
95 | * 2. Extend the metadata in the i915_ggtt_view structure if required. | |
96 | * 3. Add support to i915_get_vma_pages(). | |
97 | * | |
98 | * New views are required to build a scatter-gather table from within the | |
99 | * i915_get_vma_pages function. This table is stored in the vma.ggtt_view and | |
100 | * exists for the lifetime of an VMA. | |
101 | * | |
102 | * Core API is designed to have copy semantics which means that passed in | |
103 | * struct i915_ggtt_view does not need to be persistent (left around after | |
104 | * calling the core API functions). | |
105 | * | |
106 | */ | |
107 | ||
70b9f6f8 DV |
108 | static int |
109 | i915_get_ggtt_vma_pages(struct i915_vma *vma); | |
110 | ||
7c3f86b6 CW |
111 | static void gen6_ggtt_invalidate(struct drm_i915_private *dev_priv) |
112 | { | |
113 | /* Note that as an uncached mmio write, this should flush the | |
114 | * WCB of the writes into the GGTT before it triggers the invalidate. | |
115 | */ | |
116 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
117 | } | |
118 | ||
119 | static void guc_ggtt_invalidate(struct drm_i915_private *dev_priv) | |
120 | { | |
121 | gen6_ggtt_invalidate(dev_priv); | |
122 | I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE); | |
123 | } | |
124 | ||
125 | static void gmch_ggtt_invalidate(struct drm_i915_private *dev_priv) | |
126 | { | |
127 | intel_gtt_chipset_flush(); | |
128 | } | |
129 | ||
130 | static inline void i915_ggtt_invalidate(struct drm_i915_private *i915) | |
131 | { | |
132 | i915->ggtt.invalidate(i915); | |
133 | } | |
134 | ||
c033666a CW |
135 | int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv, |
136 | int enable_ppgtt) | |
cfa7c862 | 137 | { |
1893a71b CW |
138 | bool has_aliasing_ppgtt; |
139 | bool has_full_ppgtt; | |
1f9a99e0 | 140 | bool has_full_48bit_ppgtt; |
1893a71b | 141 | |
9e1d0e60 MT |
142 | has_aliasing_ppgtt = dev_priv->info.has_aliasing_ppgtt; |
143 | has_full_ppgtt = dev_priv->info.has_full_ppgtt; | |
144 | has_full_48bit_ppgtt = dev_priv->info.has_full_48bit_ppgtt; | |
1893a71b | 145 | |
e320d400 | 146 | if (intel_vgpu_active(dev_priv)) { |
8a4ab66f | 147 | /* GVT-g has no support for 32bit ppgtt */ |
e320d400 | 148 | has_full_ppgtt = false; |
8a4ab66f | 149 | has_full_48bit_ppgtt = intel_vgpu_has_full_48bit_ppgtt(dev_priv); |
e320d400 | 150 | } |
71ba2d64 | 151 | |
0e4ca100 CW |
152 | if (!has_aliasing_ppgtt) |
153 | return 0; | |
154 | ||
70ee45e1 DL |
155 | /* |
156 | * We don't allow disabling PPGTT for gen9+ as it's a requirement for | |
157 | * execlists, the sole mechanism available to submit work. | |
158 | */ | |
c033666a | 159 | if (enable_ppgtt == 0 && INTEL_GEN(dev_priv) < 9) |
cfa7c862 DV |
160 | return 0; |
161 | ||
162 | if (enable_ppgtt == 1) | |
163 | return 1; | |
164 | ||
1893a71b | 165 | if (enable_ppgtt == 2 && has_full_ppgtt) |
cfa7c862 DV |
166 | return 2; |
167 | ||
1f9a99e0 MT |
168 | if (enable_ppgtt == 3 && has_full_48bit_ppgtt) |
169 | return 3; | |
170 | ||
93a25a9e | 171 | /* Disable ppgtt on SNB if VT-d is on. */ |
80debff8 | 172 | if (IS_GEN6(dev_priv) && intel_vtd_active()) { |
93a25a9e | 173 | DRM_INFO("Disabling PPGTT because VT-d is on\n"); |
cfa7c862 | 174 | return 0; |
93a25a9e | 175 | } |
93a25a9e | 176 | |
62942ed7 | 177 | /* Early VLV doesn't have this */ |
91c8a326 | 178 | if (IS_VALLEYVIEW(dev_priv) && dev_priv->drm.pdev->revision < 0xb) { |
62942ed7 JB |
179 | DRM_DEBUG_DRIVER("disabling PPGTT on pre-B3 step VLV\n"); |
180 | return 0; | |
181 | } | |
182 | ||
4fc05063 JL |
183 | if (INTEL_GEN(dev_priv) >= 8 && i915.enable_execlists) { |
184 | if (has_full_48bit_ppgtt) | |
185 | return 3; | |
186 | ||
187 | if (has_full_ppgtt) | |
188 | return 2; | |
189 | } | |
190 | ||
191 | return has_aliasing_ppgtt ? 1 : 0; | |
93a25a9e DV |
192 | } |
193 | ||
70b9f6f8 DV |
194 | static int ppgtt_bind_vma(struct i915_vma *vma, |
195 | enum i915_cache_level cache_level, | |
196 | u32 unused) | |
47552659 | 197 | { |
ff685975 CW |
198 | u32 pte_flags; |
199 | int ret; | |
200 | ||
1f23475c MA |
201 | if (!(vma->flags & I915_VMA_LOCAL_BIND)) { |
202 | ret = vma->vm->allocate_va_range(vma->vm, vma->node.start, | |
203 | vma->size); | |
204 | if (ret) | |
205 | return ret; | |
206 | } | |
47552659 | 207 | |
a4f5ea64 | 208 | vma->pages = vma->obj->mm.pages; |
247177dd | 209 | |
47552659 | 210 | /* Currently applicable only to VLV */ |
ff685975 | 211 | pte_flags = 0; |
47552659 DV |
212 | if (vma->obj->gt_ro) |
213 | pte_flags |= PTE_READ_ONLY; | |
214 | ||
4a234c5f | 215 | vma->vm->insert_entries(vma->vm, vma, cache_level, pte_flags); |
70b9f6f8 DV |
216 | |
217 | return 0; | |
47552659 DV |
218 | } |
219 | ||
220 | static void ppgtt_unbind_vma(struct i915_vma *vma) | |
221 | { | |
ff685975 | 222 | vma->vm->clear_range(vma->vm, vma->node.start, vma->size); |
47552659 | 223 | } |
6f65e29a | 224 | |
2c642b07 | 225 | static gen8_pte_t gen8_pte_encode(dma_addr_t addr, |
4fb84d99 | 226 | enum i915_cache_level level) |
94ec8f61 | 227 | { |
4fb84d99 | 228 | gen8_pte_t pte = _PAGE_PRESENT | _PAGE_RW; |
94ec8f61 | 229 | pte |= addr; |
63c42e56 BW |
230 | |
231 | switch (level) { | |
232 | case I915_CACHE_NONE: | |
fbe5d36e | 233 | pte |= PPAT_UNCACHED_INDEX; |
63c42e56 BW |
234 | break; |
235 | case I915_CACHE_WT: | |
236 | pte |= PPAT_DISPLAY_ELLC_INDEX; | |
237 | break; | |
238 | default: | |
239 | pte |= PPAT_CACHED_INDEX; | |
240 | break; | |
241 | } | |
242 | ||
94ec8f61 BW |
243 | return pte; |
244 | } | |
245 | ||
fe36f55d MK |
246 | static gen8_pde_t gen8_pde_encode(const dma_addr_t addr, |
247 | const enum i915_cache_level level) | |
b1fe6673 | 248 | { |
07749ef3 | 249 | gen8_pde_t pde = _PAGE_PRESENT | _PAGE_RW; |
b1fe6673 BW |
250 | pde |= addr; |
251 | if (level != I915_CACHE_NONE) | |
252 | pde |= PPAT_CACHED_PDE_INDEX; | |
253 | else | |
254 | pde |= PPAT_UNCACHED_INDEX; | |
255 | return pde; | |
256 | } | |
257 | ||
762d9936 MT |
258 | #define gen8_pdpe_encode gen8_pde_encode |
259 | #define gen8_pml4e_encode gen8_pde_encode | |
260 | ||
07749ef3 MT |
261 | static gen6_pte_t snb_pte_encode(dma_addr_t addr, |
262 | enum i915_cache_level level, | |
4fb84d99 | 263 | u32 unused) |
54d12527 | 264 | { |
4fb84d99 | 265 | gen6_pte_t pte = GEN6_PTE_VALID; |
54d12527 | 266 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
e7210c3c BW |
267 | |
268 | switch (level) { | |
350ec881 CW |
269 | case I915_CACHE_L3_LLC: |
270 | case I915_CACHE_LLC: | |
271 | pte |= GEN6_PTE_CACHE_LLC; | |
272 | break; | |
273 | case I915_CACHE_NONE: | |
274 | pte |= GEN6_PTE_UNCACHED; | |
275 | break; | |
276 | default: | |
5f77eeb0 | 277 | MISSING_CASE(level); |
350ec881 CW |
278 | } |
279 | ||
280 | return pte; | |
281 | } | |
282 | ||
07749ef3 MT |
283 | static gen6_pte_t ivb_pte_encode(dma_addr_t addr, |
284 | enum i915_cache_level level, | |
4fb84d99 | 285 | u32 unused) |
350ec881 | 286 | { |
4fb84d99 | 287 | gen6_pte_t pte = GEN6_PTE_VALID; |
350ec881 CW |
288 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
289 | ||
290 | switch (level) { | |
291 | case I915_CACHE_L3_LLC: | |
292 | pte |= GEN7_PTE_CACHE_L3_LLC; | |
e7210c3c BW |
293 | break; |
294 | case I915_CACHE_LLC: | |
295 | pte |= GEN6_PTE_CACHE_LLC; | |
296 | break; | |
297 | case I915_CACHE_NONE: | |
9119708c | 298 | pte |= GEN6_PTE_UNCACHED; |
e7210c3c BW |
299 | break; |
300 | default: | |
5f77eeb0 | 301 | MISSING_CASE(level); |
e7210c3c BW |
302 | } |
303 | ||
54d12527 BW |
304 | return pte; |
305 | } | |
306 | ||
07749ef3 MT |
307 | static gen6_pte_t byt_pte_encode(dma_addr_t addr, |
308 | enum i915_cache_level level, | |
4fb84d99 | 309 | u32 flags) |
93c34e70 | 310 | { |
4fb84d99 | 311 | gen6_pte_t pte = GEN6_PTE_VALID; |
93c34e70 KG |
312 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
313 | ||
24f3a8cf AG |
314 | if (!(flags & PTE_READ_ONLY)) |
315 | pte |= BYT_PTE_WRITEABLE; | |
93c34e70 KG |
316 | |
317 | if (level != I915_CACHE_NONE) | |
318 | pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES; | |
319 | ||
320 | return pte; | |
321 | } | |
322 | ||
07749ef3 MT |
323 | static gen6_pte_t hsw_pte_encode(dma_addr_t addr, |
324 | enum i915_cache_level level, | |
4fb84d99 | 325 | u32 unused) |
9119708c | 326 | { |
4fb84d99 | 327 | gen6_pte_t pte = GEN6_PTE_VALID; |
0d8ff15e | 328 | pte |= HSW_PTE_ADDR_ENCODE(addr); |
9119708c KG |
329 | |
330 | if (level != I915_CACHE_NONE) | |
87a6b688 | 331 | pte |= HSW_WB_LLC_AGE3; |
9119708c KG |
332 | |
333 | return pte; | |
334 | } | |
335 | ||
07749ef3 MT |
336 | static gen6_pte_t iris_pte_encode(dma_addr_t addr, |
337 | enum i915_cache_level level, | |
4fb84d99 | 338 | u32 unused) |
4d15c145 | 339 | { |
4fb84d99 | 340 | gen6_pte_t pte = GEN6_PTE_VALID; |
4d15c145 BW |
341 | pte |= HSW_PTE_ADDR_ENCODE(addr); |
342 | ||
651d794f CW |
343 | switch (level) { |
344 | case I915_CACHE_NONE: | |
345 | break; | |
346 | case I915_CACHE_WT: | |
c51e9701 | 347 | pte |= HSW_WT_ELLC_LLC_AGE3; |
651d794f CW |
348 | break; |
349 | default: | |
c51e9701 | 350 | pte |= HSW_WB_ELLC_LLC_AGE3; |
651d794f CW |
351 | break; |
352 | } | |
4d15c145 BW |
353 | |
354 | return pte; | |
355 | } | |
356 | ||
8448661d | 357 | static struct page *vm_alloc_page(struct i915_address_space *vm, gfp_t gfp) |
678d96fb | 358 | { |
66df1014 | 359 | struct pagevec *pvec = &vm->free_pages; |
678d96fb | 360 | |
8448661d CW |
361 | if (I915_SELFTEST_ONLY(should_fail(&vm->fault_attr, 1))) |
362 | i915_gem_shrink_all(vm->i915); | |
aae4a3d8 | 363 | |
66df1014 CW |
364 | if (likely(pvec->nr)) |
365 | return pvec->pages[--pvec->nr]; | |
366 | ||
367 | if (!vm->pt_kmap_wc) | |
368 | return alloc_page(gfp); | |
369 | ||
370 | /* A placeholder for a specific mutex to guard the WC stash */ | |
371 | lockdep_assert_held(&vm->i915->drm.struct_mutex); | |
372 | ||
373 | /* Look in our global stash of WC pages... */ | |
374 | pvec = &vm->i915->mm.wc_stash; | |
375 | if (likely(pvec->nr)) | |
376 | return pvec->pages[--pvec->nr]; | |
377 | ||
378 | /* Otherwise batch allocate pages to amoritize cost of set_pages_wc. */ | |
379 | do { | |
380 | struct page *page; | |
8448661d | 381 | |
66df1014 CW |
382 | page = alloc_page(gfp); |
383 | if (unlikely(!page)) | |
384 | break; | |
385 | ||
386 | pvec->pages[pvec->nr++] = page; | |
387 | } while (pagevec_space(pvec)); | |
388 | ||
389 | if (unlikely(!pvec->nr)) | |
8448661d CW |
390 | return NULL; |
391 | ||
66df1014 | 392 | set_pages_array_wc(pvec->pages, pvec->nr); |
8448661d | 393 | |
66df1014 | 394 | return pvec->pages[--pvec->nr]; |
8448661d CW |
395 | } |
396 | ||
66df1014 CW |
397 | static void vm_free_pages_release(struct i915_address_space *vm, |
398 | bool immediate) | |
8448661d | 399 | { |
66df1014 CW |
400 | struct pagevec *pvec = &vm->free_pages; |
401 | ||
402 | GEM_BUG_ON(!pagevec_count(pvec)); | |
8448661d | 403 | |
66df1014 CW |
404 | if (vm->pt_kmap_wc) { |
405 | struct pagevec *stash = &vm->i915->mm.wc_stash; | |
406 | ||
407 | /* When we use WC, first fill up the global stash and then | |
408 | * only if full immediately free the overflow. | |
409 | */ | |
8448661d | 410 | |
66df1014 CW |
411 | lockdep_assert_held(&vm->i915->drm.struct_mutex); |
412 | if (pagevec_space(stash)) { | |
413 | do { | |
414 | stash->pages[stash->nr++] = | |
415 | pvec->pages[--pvec->nr]; | |
416 | if (!pvec->nr) | |
417 | return; | |
418 | } while (pagevec_space(stash)); | |
419 | ||
420 | /* As we have made some room in the VM's free_pages, | |
421 | * we can wait for it to fill again. Unless we are | |
422 | * inside i915_address_space_fini() and must | |
423 | * immediately release the pages! | |
424 | */ | |
425 | if (!immediate) | |
426 | return; | |
427 | } | |
428 | ||
429 | set_pages_array_wb(pvec->pages, pvec->nr); | |
430 | } | |
431 | ||
432 | __pagevec_release(pvec); | |
8448661d CW |
433 | } |
434 | ||
435 | static void vm_free_page(struct i915_address_space *vm, struct page *page) | |
436 | { | |
437 | if (!pagevec_add(&vm->free_pages, page)) | |
66df1014 | 438 | vm_free_pages_release(vm, false); |
8448661d | 439 | } |
678d96fb | 440 | |
8448661d CW |
441 | static int __setup_page_dma(struct i915_address_space *vm, |
442 | struct i915_page_dma *p, | |
443 | gfp_t gfp) | |
444 | { | |
445 | p->page = vm_alloc_page(vm, gfp | __GFP_NOWARN | __GFP_NORETRY); | |
446 | if (unlikely(!p->page)) | |
447 | return -ENOMEM; | |
678d96fb | 448 | |
8448661d CW |
449 | p->daddr = dma_map_page(vm->dma, p->page, 0, PAGE_SIZE, |
450 | PCI_DMA_BIDIRECTIONAL); | |
451 | if (unlikely(dma_mapping_error(vm->dma, p->daddr))) { | |
452 | vm_free_page(vm, p->page); | |
453 | return -ENOMEM; | |
44159ddb | 454 | } |
1266cdb1 MT |
455 | |
456 | return 0; | |
678d96fb BW |
457 | } |
458 | ||
8448661d | 459 | static int setup_page_dma(struct i915_address_space *vm, |
275a991c | 460 | struct i915_page_dma *p) |
c114f76a | 461 | { |
8448661d | 462 | return __setup_page_dma(vm, p, I915_GFP_DMA); |
c114f76a MK |
463 | } |
464 | ||
8448661d | 465 | static void cleanup_page_dma(struct i915_address_space *vm, |
275a991c | 466 | struct i915_page_dma *p) |
06fda602 | 467 | { |
8448661d CW |
468 | dma_unmap_page(vm->dma, p->daddr, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); |
469 | vm_free_page(vm, p->page); | |
44159ddb MK |
470 | } |
471 | ||
9231da70 | 472 | #define kmap_atomic_px(px) kmap_atomic(px_base(px)->page) |
d1c54acd | 473 | |
8448661d CW |
474 | #define setup_px(vm, px) setup_page_dma((vm), px_base(px)) |
475 | #define cleanup_px(vm, px) cleanup_page_dma((vm), px_base(px)) | |
476 | #define fill_px(ppgtt, px, v) fill_page_dma((vm), px_base(px), (v)) | |
477 | #define fill32_px(ppgtt, px, v) fill_page_dma_32((vm), px_base(px), (v)) | |
567047be | 478 | |
8448661d CW |
479 | static void fill_page_dma(struct i915_address_space *vm, |
480 | struct i915_page_dma *p, | |
481 | const u64 val) | |
d1c54acd | 482 | { |
9231da70 | 483 | u64 * const vaddr = kmap_atomic(p->page); |
d1c54acd | 484 | int i; |
d1c54acd MK |
485 | |
486 | for (i = 0; i < 512; i++) | |
487 | vaddr[i] = val; | |
488 | ||
9231da70 | 489 | kunmap_atomic(vaddr); |
d1c54acd MK |
490 | } |
491 | ||
8448661d CW |
492 | static void fill_page_dma_32(struct i915_address_space *vm, |
493 | struct i915_page_dma *p, | |
494 | const u32 v) | |
73eeea53 | 495 | { |
8448661d | 496 | fill_page_dma(vm, p, (u64)v << 32 | v); |
73eeea53 MK |
497 | } |
498 | ||
8bcdd0f7 | 499 | static int |
8448661d | 500 | setup_scratch_page(struct i915_address_space *vm, gfp_t gfp) |
4ad2af1e | 501 | { |
66df1014 CW |
502 | struct page *page; |
503 | dma_addr_t addr; | |
504 | ||
505 | page = alloc_page(gfp | __GFP_ZERO); | |
506 | if (unlikely(!page)) | |
507 | return -ENOMEM; | |
508 | ||
509 | addr = dma_map_page(vm->dma, page, 0, PAGE_SIZE, | |
510 | PCI_DMA_BIDIRECTIONAL); | |
511 | if (unlikely(dma_mapping_error(vm->dma, addr))) { | |
512 | __free_page(page); | |
513 | return -ENOMEM; | |
514 | } | |
515 | ||
516 | vm->scratch_page.page = page; | |
517 | vm->scratch_page.daddr = addr; | |
518 | return 0; | |
4ad2af1e MK |
519 | } |
520 | ||
8448661d | 521 | static void cleanup_scratch_page(struct i915_address_space *vm) |
4ad2af1e | 522 | { |
66df1014 CW |
523 | struct i915_page_dma *p = &vm->scratch_page; |
524 | ||
525 | dma_unmap_page(vm->dma, p->daddr, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); | |
526 | __free_page(p->page); | |
4ad2af1e MK |
527 | } |
528 | ||
8448661d | 529 | static struct i915_page_table *alloc_pt(struct i915_address_space *vm) |
06fda602 | 530 | { |
ec565b3c | 531 | struct i915_page_table *pt; |
06fda602 | 532 | |
dd19674b CW |
533 | pt = kmalloc(sizeof(*pt), GFP_KERNEL | __GFP_NOWARN); |
534 | if (unlikely(!pt)) | |
06fda602 BW |
535 | return ERR_PTR(-ENOMEM); |
536 | ||
dd19674b CW |
537 | if (unlikely(setup_px(vm, pt))) { |
538 | kfree(pt); | |
539 | return ERR_PTR(-ENOMEM); | |
540 | } | |
06fda602 | 541 | |
dd19674b | 542 | pt->used_ptes = 0; |
06fda602 BW |
543 | return pt; |
544 | } | |
545 | ||
8448661d | 546 | static void free_pt(struct i915_address_space *vm, struct i915_page_table *pt) |
06fda602 | 547 | { |
8448661d | 548 | cleanup_px(vm, pt); |
2e906bea MK |
549 | kfree(pt); |
550 | } | |
551 | ||
552 | static void gen8_initialize_pt(struct i915_address_space *vm, | |
553 | struct i915_page_table *pt) | |
554 | { | |
dd19674b CW |
555 | fill_px(vm, pt, |
556 | gen8_pte_encode(vm->scratch_page.daddr, I915_CACHE_LLC)); | |
2e906bea MK |
557 | } |
558 | ||
559 | static void gen6_initialize_pt(struct i915_address_space *vm, | |
560 | struct i915_page_table *pt) | |
561 | { | |
dd19674b CW |
562 | fill32_px(vm, pt, |
563 | vm->pte_encode(vm->scratch_page.daddr, I915_CACHE_LLC, 0)); | |
06fda602 BW |
564 | } |
565 | ||
8448661d | 566 | static struct i915_page_directory *alloc_pd(struct i915_address_space *vm) |
06fda602 | 567 | { |
ec565b3c | 568 | struct i915_page_directory *pd; |
06fda602 | 569 | |
fe52e37f CW |
570 | pd = kzalloc(sizeof(*pd), GFP_KERNEL | __GFP_NOWARN); |
571 | if (unlikely(!pd)) | |
06fda602 BW |
572 | return ERR_PTR(-ENOMEM); |
573 | ||
fe52e37f CW |
574 | if (unlikely(setup_px(vm, pd))) { |
575 | kfree(pd); | |
576 | return ERR_PTR(-ENOMEM); | |
577 | } | |
e5815a2e | 578 | |
fe52e37f | 579 | pd->used_pdes = 0; |
06fda602 BW |
580 | return pd; |
581 | } | |
582 | ||
8448661d | 583 | static void free_pd(struct i915_address_space *vm, |
275a991c | 584 | struct i915_page_directory *pd) |
2e906bea | 585 | { |
fe52e37f CW |
586 | cleanup_px(vm, pd); |
587 | kfree(pd); | |
2e906bea MK |
588 | } |
589 | ||
590 | static void gen8_initialize_pd(struct i915_address_space *vm, | |
591 | struct i915_page_directory *pd) | |
592 | { | |
dd19674b | 593 | unsigned int i; |
2e906bea | 594 | |
dd19674b CW |
595 | fill_px(vm, pd, |
596 | gen8_pde_encode(px_dma(vm->scratch_pt), I915_CACHE_LLC)); | |
597 | for (i = 0; i < I915_PDES; i++) | |
598 | pd->page_table[i] = vm->scratch_pt; | |
2e906bea MK |
599 | } |
600 | ||
fe52e37f | 601 | static int __pdp_init(struct i915_address_space *vm, |
6ac18502 MT |
602 | struct i915_page_directory_pointer *pdp) |
603 | { | |
3e490042 | 604 | const unsigned int pdpes = i915_pdpes_per_pdp(vm); |
e2b763ca | 605 | unsigned int i; |
6ac18502 | 606 | |
fe52e37f | 607 | pdp->page_directory = kmalloc_array(pdpes, sizeof(*pdp->page_directory), |
e2b763ca CW |
608 | GFP_KERNEL | __GFP_NOWARN); |
609 | if (unlikely(!pdp->page_directory)) | |
6ac18502 | 610 | return -ENOMEM; |
6ac18502 | 611 | |
fe52e37f CW |
612 | for (i = 0; i < pdpes; i++) |
613 | pdp->page_directory[i] = vm->scratch_pd; | |
614 | ||
6ac18502 MT |
615 | return 0; |
616 | } | |
617 | ||
618 | static void __pdp_fini(struct i915_page_directory_pointer *pdp) | |
619 | { | |
6ac18502 MT |
620 | kfree(pdp->page_directory); |
621 | pdp->page_directory = NULL; | |
622 | } | |
623 | ||
1e6437b0 MK |
624 | static inline bool use_4lvl(const struct i915_address_space *vm) |
625 | { | |
626 | return i915_vm_is_48bit(vm); | |
627 | } | |
628 | ||
8448661d CW |
629 | static struct i915_page_directory_pointer * |
630 | alloc_pdp(struct i915_address_space *vm) | |
762d9936 MT |
631 | { |
632 | struct i915_page_directory_pointer *pdp; | |
633 | int ret = -ENOMEM; | |
634 | ||
1e6437b0 | 635 | WARN_ON(!use_4lvl(vm)); |
762d9936 MT |
636 | |
637 | pdp = kzalloc(sizeof(*pdp), GFP_KERNEL); | |
638 | if (!pdp) | |
639 | return ERR_PTR(-ENOMEM); | |
640 | ||
fe52e37f | 641 | ret = __pdp_init(vm, pdp); |
762d9936 MT |
642 | if (ret) |
643 | goto fail_bitmap; | |
644 | ||
8448661d | 645 | ret = setup_px(vm, pdp); |
762d9936 MT |
646 | if (ret) |
647 | goto fail_page_m; | |
648 | ||
649 | return pdp; | |
650 | ||
651 | fail_page_m: | |
652 | __pdp_fini(pdp); | |
653 | fail_bitmap: | |
654 | kfree(pdp); | |
655 | ||
656 | return ERR_PTR(ret); | |
657 | } | |
658 | ||
8448661d | 659 | static void free_pdp(struct i915_address_space *vm, |
6ac18502 MT |
660 | struct i915_page_directory_pointer *pdp) |
661 | { | |
662 | __pdp_fini(pdp); | |
1e6437b0 MK |
663 | |
664 | if (!use_4lvl(vm)) | |
665 | return; | |
666 | ||
667 | cleanup_px(vm, pdp); | |
668 | kfree(pdp); | |
762d9936 MT |
669 | } |
670 | ||
69ab76fd MT |
671 | static void gen8_initialize_pdp(struct i915_address_space *vm, |
672 | struct i915_page_directory_pointer *pdp) | |
673 | { | |
674 | gen8_ppgtt_pdpe_t scratch_pdpe; | |
675 | ||
676 | scratch_pdpe = gen8_pdpe_encode(px_dma(vm->scratch_pd), I915_CACHE_LLC); | |
677 | ||
8448661d | 678 | fill_px(vm, pdp, scratch_pdpe); |
69ab76fd MT |
679 | } |
680 | ||
681 | static void gen8_initialize_pml4(struct i915_address_space *vm, | |
682 | struct i915_pml4 *pml4) | |
683 | { | |
e2b763ca | 684 | unsigned int i; |
762d9936 | 685 | |
e2b763ca CW |
686 | fill_px(vm, pml4, |
687 | gen8_pml4e_encode(px_dma(vm->scratch_pdp), I915_CACHE_LLC)); | |
688 | for (i = 0; i < GEN8_PML4ES_PER_PML4; i++) | |
689 | pml4->pdps[i] = vm->scratch_pdp; | |
6ac18502 MT |
690 | } |
691 | ||
94e409c1 | 692 | /* Broadwell Page Directory Pointer Descriptors */ |
e85b26dc | 693 | static int gen8_write_pdp(struct drm_i915_gem_request *req, |
7cb6d7ac MT |
694 | unsigned entry, |
695 | dma_addr_t addr) | |
94e409c1 | 696 | { |
4a570db5 | 697 | struct intel_engine_cs *engine = req->engine; |
73dec95e | 698 | u32 *cs; |
94e409c1 BW |
699 | |
700 | BUG_ON(entry >= 4); | |
701 | ||
73dec95e TU |
702 | cs = intel_ring_begin(req, 6); |
703 | if (IS_ERR(cs)) | |
704 | return PTR_ERR(cs); | |
94e409c1 | 705 | |
73dec95e TU |
706 | *cs++ = MI_LOAD_REGISTER_IMM(1); |
707 | *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(engine, entry)); | |
708 | *cs++ = upper_32_bits(addr); | |
709 | *cs++ = MI_LOAD_REGISTER_IMM(1); | |
710 | *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(engine, entry)); | |
711 | *cs++ = lower_32_bits(addr); | |
712 | intel_ring_advance(req, cs); | |
94e409c1 BW |
713 | |
714 | return 0; | |
715 | } | |
716 | ||
e7167769 MK |
717 | static int gen8_mm_switch_3lvl(struct i915_hw_ppgtt *ppgtt, |
718 | struct drm_i915_gem_request *req) | |
94e409c1 | 719 | { |
eeb9488e | 720 | int i, ret; |
94e409c1 | 721 | |
e7167769 | 722 | for (i = GEN8_3LVL_PDPES - 1; i >= 0; i--) { |
d852c7bf MK |
723 | const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i); |
724 | ||
e85b26dc | 725 | ret = gen8_write_pdp(req, i, pd_daddr); |
eeb9488e BW |
726 | if (ret) |
727 | return ret; | |
94e409c1 | 728 | } |
d595bd4b | 729 | |
eeb9488e | 730 | return 0; |
94e409c1 BW |
731 | } |
732 | ||
e7167769 MK |
733 | static int gen8_mm_switch_4lvl(struct i915_hw_ppgtt *ppgtt, |
734 | struct drm_i915_gem_request *req) | |
2dba3239 MT |
735 | { |
736 | return gen8_write_pdp(req, 0, px_dma(&ppgtt->pml4)); | |
737 | } | |
738 | ||
fce93755 MK |
739 | /* PDE TLBs are a pain to invalidate on GEN8+. When we modify |
740 | * the page table structures, we mark them dirty so that | |
741 | * context switching/execlist queuing code takes extra steps | |
742 | * to ensure that tlbs are flushed. | |
743 | */ | |
744 | static void mark_tlbs_dirty(struct i915_hw_ppgtt *ppgtt) | |
745 | { | |
49d73912 | 746 | ppgtt->pd_dirty_rings = INTEL_INFO(ppgtt->base.i915)->ring_mask; |
fce93755 MK |
747 | } |
748 | ||
2ce5179f MW |
749 | /* Removes entries from a single page table, releasing it if it's empty. |
750 | * Caller can use the return value to update higher-level entries. | |
751 | */ | |
752 | static bool gen8_ppgtt_clear_pt(struct i915_address_space *vm, | |
d209b9c3 | 753 | struct i915_page_table *pt, |
dd19674b | 754 | u64 start, u64 length) |
459108b8 | 755 | { |
d209b9c3 | 756 | unsigned int num_entries = gen8_pte_count(start, length); |
37c63934 MK |
757 | unsigned int pte = gen8_pte_index(start); |
758 | unsigned int pte_end = pte + num_entries; | |
894ccebe CW |
759 | const gen8_pte_t scratch_pte = |
760 | gen8_pte_encode(vm->scratch_page.daddr, I915_CACHE_LLC); | |
761 | gen8_pte_t *vaddr; | |
459108b8 | 762 | |
dd19674b | 763 | GEM_BUG_ON(num_entries > pt->used_ptes); |
37c63934 | 764 | |
dd19674b CW |
765 | pt->used_ptes -= num_entries; |
766 | if (!pt->used_ptes) | |
767 | return true; | |
2ce5179f | 768 | |
9231da70 | 769 | vaddr = kmap_atomic_px(pt); |
37c63934 | 770 | while (pte < pte_end) |
894ccebe | 771 | vaddr[pte++] = scratch_pte; |
9231da70 | 772 | kunmap_atomic(vaddr); |
2ce5179f MW |
773 | |
774 | return false; | |
d209b9c3 | 775 | } |
06fda602 | 776 | |
dd19674b CW |
777 | static void gen8_ppgtt_set_pde(struct i915_address_space *vm, |
778 | struct i915_page_directory *pd, | |
779 | struct i915_page_table *pt, | |
780 | unsigned int pde) | |
781 | { | |
782 | gen8_pde_t *vaddr; | |
783 | ||
784 | pd->page_table[pde] = pt; | |
785 | ||
786 | vaddr = kmap_atomic_px(pd); | |
787 | vaddr[pde] = gen8_pde_encode(px_dma(pt), I915_CACHE_LLC); | |
788 | kunmap_atomic(vaddr); | |
789 | } | |
790 | ||
2ce5179f | 791 | static bool gen8_ppgtt_clear_pd(struct i915_address_space *vm, |
d209b9c3 | 792 | struct i915_page_directory *pd, |
dd19674b | 793 | u64 start, u64 length) |
d209b9c3 MW |
794 | { |
795 | struct i915_page_table *pt; | |
dd19674b | 796 | u32 pde; |
d209b9c3 MW |
797 | |
798 | gen8_for_each_pde(pt, pd, start, length, pde) { | |
bf75d59e CW |
799 | GEM_BUG_ON(pt == vm->scratch_pt); |
800 | ||
dd19674b CW |
801 | if (!gen8_ppgtt_clear_pt(vm, pt, start, length)) |
802 | continue; | |
06fda602 | 803 | |
dd19674b | 804 | gen8_ppgtt_set_pde(vm, pd, vm->scratch_pt, pde); |
bf75d59e | 805 | GEM_BUG_ON(!pd->used_pdes); |
fe52e37f | 806 | pd->used_pdes--; |
dd19674b CW |
807 | |
808 | free_pt(vm, pt); | |
2ce5179f MW |
809 | } |
810 | ||
fe52e37f CW |
811 | return !pd->used_pdes; |
812 | } | |
2ce5179f | 813 | |
fe52e37f CW |
814 | static void gen8_ppgtt_set_pdpe(struct i915_address_space *vm, |
815 | struct i915_page_directory_pointer *pdp, | |
816 | struct i915_page_directory *pd, | |
817 | unsigned int pdpe) | |
818 | { | |
819 | gen8_ppgtt_pdpe_t *vaddr; | |
820 | ||
821 | pdp->page_directory[pdpe] = pd; | |
1e6437b0 | 822 | if (!use_4lvl(vm)) |
fe52e37f CW |
823 | return; |
824 | ||
825 | vaddr = kmap_atomic_px(pdp); | |
826 | vaddr[pdpe] = gen8_pdpe_encode(px_dma(pd), I915_CACHE_LLC); | |
827 | kunmap_atomic(vaddr); | |
d209b9c3 | 828 | } |
06fda602 | 829 | |
2ce5179f MW |
830 | /* Removes entries from a single page dir pointer, releasing it if it's empty. |
831 | * Caller can use the return value to update higher-level entries | |
832 | */ | |
833 | static bool gen8_ppgtt_clear_pdp(struct i915_address_space *vm, | |
d209b9c3 | 834 | struct i915_page_directory_pointer *pdp, |
fe52e37f | 835 | u64 start, u64 length) |
d209b9c3 MW |
836 | { |
837 | struct i915_page_directory *pd; | |
fe52e37f | 838 | unsigned int pdpe; |
06fda602 | 839 | |
d209b9c3 | 840 | gen8_for_each_pdpe(pd, pdp, start, length, pdpe) { |
bf75d59e CW |
841 | GEM_BUG_ON(pd == vm->scratch_pd); |
842 | ||
fe52e37f CW |
843 | if (!gen8_ppgtt_clear_pd(vm, pd, start, length)) |
844 | continue; | |
459108b8 | 845 | |
fe52e37f | 846 | gen8_ppgtt_set_pdpe(vm, pdp, vm->scratch_pd, pdpe); |
bf75d59e | 847 | GEM_BUG_ON(!pdp->used_pdpes); |
e2b763ca | 848 | pdp->used_pdpes--; |
2ce5179f | 849 | |
fe52e37f CW |
850 | free_pd(vm, pd); |
851 | } | |
fce93755 | 852 | |
e2b763ca | 853 | return !pdp->used_pdpes; |
d209b9c3 | 854 | } |
459108b8 | 855 | |
fe52e37f CW |
856 | static void gen8_ppgtt_clear_3lvl(struct i915_address_space *vm, |
857 | u64 start, u64 length) | |
858 | { | |
859 | gen8_ppgtt_clear_pdp(vm, &i915_vm_to_ppgtt(vm)->pdp, start, length); | |
860 | } | |
861 | ||
e2b763ca CW |
862 | static void gen8_ppgtt_set_pml4e(struct i915_pml4 *pml4, |
863 | struct i915_page_directory_pointer *pdp, | |
864 | unsigned int pml4e) | |
865 | { | |
866 | gen8_ppgtt_pml4e_t *vaddr; | |
867 | ||
868 | pml4->pdps[pml4e] = pdp; | |
869 | ||
870 | vaddr = kmap_atomic_px(pml4); | |
871 | vaddr[pml4e] = gen8_pml4e_encode(px_dma(pdp), I915_CACHE_LLC); | |
872 | kunmap_atomic(vaddr); | |
873 | } | |
874 | ||
2ce5179f MW |
875 | /* Removes entries from a single pml4. |
876 | * This is the top-level structure in 4-level page tables used on gen8+. | |
877 | * Empty entries are always scratch pml4e. | |
878 | */ | |
fe52e37f CW |
879 | static void gen8_ppgtt_clear_4lvl(struct i915_address_space *vm, |
880 | u64 start, u64 length) | |
d209b9c3 | 881 | { |
fe52e37f CW |
882 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
883 | struct i915_pml4 *pml4 = &ppgtt->pml4; | |
d209b9c3 | 884 | struct i915_page_directory_pointer *pdp; |
e2b763ca | 885 | unsigned int pml4e; |
2ce5179f | 886 | |
1e6437b0 | 887 | GEM_BUG_ON(!use_4lvl(vm)); |
459108b8 | 888 | |
d209b9c3 | 889 | gen8_for_each_pml4e(pdp, pml4, start, length, pml4e) { |
bf75d59e CW |
890 | GEM_BUG_ON(pdp == vm->scratch_pdp); |
891 | ||
e2b763ca CW |
892 | if (!gen8_ppgtt_clear_pdp(vm, pdp, start, length)) |
893 | continue; | |
459108b8 | 894 | |
e2b763ca | 895 | gen8_ppgtt_set_pml4e(pml4, vm->scratch_pdp, pml4e); |
e2b763ca CW |
896 | |
897 | free_pdp(vm, pdp); | |
459108b8 BW |
898 | } |
899 | } | |
900 | ||
894ccebe CW |
901 | struct sgt_dma { |
902 | struct scatterlist *sg; | |
903 | dma_addr_t dma, max; | |
904 | }; | |
905 | ||
9e89f9ee CW |
906 | struct gen8_insert_pte { |
907 | u16 pml4e; | |
908 | u16 pdpe; | |
909 | u16 pde; | |
910 | u16 pte; | |
911 | }; | |
912 | ||
913 | static __always_inline struct gen8_insert_pte gen8_insert_pte(u64 start) | |
914 | { | |
915 | return (struct gen8_insert_pte) { | |
916 | gen8_pml4e_index(start), | |
917 | gen8_pdpe_index(start), | |
918 | gen8_pde_index(start), | |
919 | gen8_pte_index(start), | |
920 | }; | |
921 | } | |
922 | ||
894ccebe CW |
923 | static __always_inline bool |
924 | gen8_ppgtt_insert_pte_entries(struct i915_hw_ppgtt *ppgtt, | |
f9b5b782 | 925 | struct i915_page_directory_pointer *pdp, |
894ccebe | 926 | struct sgt_dma *iter, |
9e89f9ee | 927 | struct gen8_insert_pte *idx, |
f9b5b782 MT |
928 | enum i915_cache_level cache_level) |
929 | { | |
894ccebe CW |
930 | struct i915_page_directory *pd; |
931 | const gen8_pte_t pte_encode = gen8_pte_encode(0, cache_level); | |
932 | gen8_pte_t *vaddr; | |
933 | bool ret; | |
9df15b49 | 934 | |
3e490042 | 935 | GEM_BUG_ON(idx->pdpe >= i915_pdpes_per_pdp(&ppgtt->base)); |
9e89f9ee CW |
936 | pd = pdp->page_directory[idx->pdpe]; |
937 | vaddr = kmap_atomic_px(pd->page_table[idx->pde]); | |
894ccebe | 938 | do { |
9e89f9ee CW |
939 | vaddr[idx->pte] = pte_encode | iter->dma; |
940 | ||
894ccebe CW |
941 | iter->dma += PAGE_SIZE; |
942 | if (iter->dma >= iter->max) { | |
943 | iter->sg = __sg_next(iter->sg); | |
944 | if (!iter->sg) { | |
945 | ret = false; | |
946 | break; | |
947 | } | |
7ad47cf2 | 948 | |
894ccebe CW |
949 | iter->dma = sg_dma_address(iter->sg); |
950 | iter->max = iter->dma + iter->sg->length; | |
d7b3de91 | 951 | } |
9df15b49 | 952 | |
9e89f9ee CW |
953 | if (++idx->pte == GEN8_PTES) { |
954 | idx->pte = 0; | |
955 | ||
956 | if (++idx->pde == I915_PDES) { | |
957 | idx->pde = 0; | |
958 | ||
894ccebe | 959 | /* Limited by sg length for 3lvl */ |
9e89f9ee CW |
960 | if (++idx->pdpe == GEN8_PML4ES_PER_PML4) { |
961 | idx->pdpe = 0; | |
894ccebe | 962 | ret = true; |
de5ba8eb | 963 | break; |
894ccebe CW |
964 | } |
965 | ||
3e490042 | 966 | GEM_BUG_ON(idx->pdpe >= i915_pdpes_per_pdp(&ppgtt->base)); |
9e89f9ee | 967 | pd = pdp->page_directory[idx->pdpe]; |
7ad47cf2 | 968 | } |
894ccebe | 969 | |
9231da70 | 970 | kunmap_atomic(vaddr); |
9e89f9ee | 971 | vaddr = kmap_atomic_px(pd->page_table[idx->pde]); |
9df15b49 | 972 | } |
894ccebe | 973 | } while (1); |
9231da70 | 974 | kunmap_atomic(vaddr); |
d1c54acd | 975 | |
894ccebe | 976 | return ret; |
9df15b49 BW |
977 | } |
978 | ||
894ccebe | 979 | static void gen8_ppgtt_insert_3lvl(struct i915_address_space *vm, |
4a234c5f | 980 | struct i915_vma *vma, |
894ccebe CW |
981 | enum i915_cache_level cache_level, |
982 | u32 unused) | |
f9b5b782 | 983 | { |
17369ba0 | 984 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
894ccebe | 985 | struct sgt_dma iter = { |
4a234c5f | 986 | .sg = vma->pages->sgl, |
894ccebe CW |
987 | .dma = sg_dma_address(iter.sg), |
988 | .max = iter.dma + iter.sg->length, | |
989 | }; | |
4a234c5f | 990 | struct gen8_insert_pte idx = gen8_insert_pte(vma->node.start); |
f9b5b782 | 991 | |
9e89f9ee CW |
992 | gen8_ppgtt_insert_pte_entries(ppgtt, &ppgtt->pdp, &iter, &idx, |
993 | cache_level); | |
894ccebe | 994 | } |
de5ba8eb | 995 | |
894ccebe | 996 | static void gen8_ppgtt_insert_4lvl(struct i915_address_space *vm, |
4a234c5f | 997 | struct i915_vma *vma, |
894ccebe CW |
998 | enum i915_cache_level cache_level, |
999 | u32 unused) | |
1000 | { | |
1001 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); | |
1002 | struct sgt_dma iter = { | |
4a234c5f | 1003 | .sg = vma->pages->sgl, |
894ccebe CW |
1004 | .dma = sg_dma_address(iter.sg), |
1005 | .max = iter.dma + iter.sg->length, | |
1006 | }; | |
1007 | struct i915_page_directory_pointer **pdps = ppgtt->pml4.pdps; | |
4a234c5f | 1008 | struct gen8_insert_pte idx = gen8_insert_pte(vma->node.start); |
de5ba8eb | 1009 | |
9e89f9ee CW |
1010 | while (gen8_ppgtt_insert_pte_entries(ppgtt, pdps[idx.pml4e++], &iter, |
1011 | &idx, cache_level)) | |
1012 | GEM_BUG_ON(idx.pml4e >= GEN8_PML4ES_PER_PML4); | |
f9b5b782 MT |
1013 | } |
1014 | ||
8448661d | 1015 | static void gen8_free_page_tables(struct i915_address_space *vm, |
f37c0505 | 1016 | struct i915_page_directory *pd) |
7ad47cf2 BW |
1017 | { |
1018 | int i; | |
1019 | ||
567047be | 1020 | if (!px_page(pd)) |
7ad47cf2 BW |
1021 | return; |
1022 | ||
fe52e37f CW |
1023 | for (i = 0; i < I915_PDES; i++) { |
1024 | if (pd->page_table[i] != vm->scratch_pt) | |
1025 | free_pt(vm, pd->page_table[i]); | |
06fda602 | 1026 | } |
d7b3de91 BW |
1027 | } |
1028 | ||
8776f02b MK |
1029 | static int gen8_init_scratch(struct i915_address_space *vm) |
1030 | { | |
64c050db | 1031 | int ret; |
8776f02b | 1032 | |
8448661d | 1033 | ret = setup_scratch_page(vm, I915_GFP_DMA); |
8bcdd0f7 CW |
1034 | if (ret) |
1035 | return ret; | |
8776f02b | 1036 | |
8448661d | 1037 | vm->scratch_pt = alloc_pt(vm); |
8776f02b | 1038 | if (IS_ERR(vm->scratch_pt)) { |
64c050db MA |
1039 | ret = PTR_ERR(vm->scratch_pt); |
1040 | goto free_scratch_page; | |
8776f02b MK |
1041 | } |
1042 | ||
8448661d | 1043 | vm->scratch_pd = alloc_pd(vm); |
8776f02b | 1044 | if (IS_ERR(vm->scratch_pd)) { |
64c050db MA |
1045 | ret = PTR_ERR(vm->scratch_pd); |
1046 | goto free_pt; | |
8776f02b MK |
1047 | } |
1048 | ||
1e6437b0 | 1049 | if (use_4lvl(vm)) { |
8448661d | 1050 | vm->scratch_pdp = alloc_pdp(vm); |
69ab76fd | 1051 | if (IS_ERR(vm->scratch_pdp)) { |
64c050db MA |
1052 | ret = PTR_ERR(vm->scratch_pdp); |
1053 | goto free_pd; | |
69ab76fd MT |
1054 | } |
1055 | } | |
1056 | ||
8776f02b MK |
1057 | gen8_initialize_pt(vm, vm->scratch_pt); |
1058 | gen8_initialize_pd(vm, vm->scratch_pd); | |
1e6437b0 | 1059 | if (use_4lvl(vm)) |
69ab76fd | 1060 | gen8_initialize_pdp(vm, vm->scratch_pdp); |
8776f02b MK |
1061 | |
1062 | return 0; | |
64c050db MA |
1063 | |
1064 | free_pd: | |
8448661d | 1065 | free_pd(vm, vm->scratch_pd); |
64c050db | 1066 | free_pt: |
8448661d | 1067 | free_pt(vm, vm->scratch_pt); |
64c050db | 1068 | free_scratch_page: |
8448661d | 1069 | cleanup_scratch_page(vm); |
64c050db MA |
1070 | |
1071 | return ret; | |
8776f02b MK |
1072 | } |
1073 | ||
650da34c ZL |
1074 | static int gen8_ppgtt_notify_vgt(struct i915_hw_ppgtt *ppgtt, bool create) |
1075 | { | |
1e6437b0 MK |
1076 | struct i915_address_space *vm = &ppgtt->base; |
1077 | struct drm_i915_private *dev_priv = vm->i915; | |
650da34c | 1078 | enum vgt_g2v_type msg; |
650da34c ZL |
1079 | int i; |
1080 | ||
1e6437b0 MK |
1081 | if (use_4lvl(vm)) { |
1082 | const u64 daddr = px_dma(&ppgtt->pml4); | |
650da34c | 1083 | |
ab75bb5d VS |
1084 | I915_WRITE(vgtif_reg(pdp[0].lo), lower_32_bits(daddr)); |
1085 | I915_WRITE(vgtif_reg(pdp[0].hi), upper_32_bits(daddr)); | |
650da34c ZL |
1086 | |
1087 | msg = (create ? VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE : | |
1088 | VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY); | |
1089 | } else { | |
e7167769 | 1090 | for (i = 0; i < GEN8_3LVL_PDPES; i++) { |
1e6437b0 | 1091 | const u64 daddr = i915_page_dir_dma_addr(ppgtt, i); |
650da34c | 1092 | |
ab75bb5d VS |
1093 | I915_WRITE(vgtif_reg(pdp[i].lo), lower_32_bits(daddr)); |
1094 | I915_WRITE(vgtif_reg(pdp[i].hi), upper_32_bits(daddr)); | |
650da34c ZL |
1095 | } |
1096 | ||
1097 | msg = (create ? VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE : | |
1098 | VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY); | |
1099 | } | |
1100 | ||
1101 | I915_WRITE(vgtif_reg(g2v_notify), msg); | |
1102 | ||
1103 | return 0; | |
1104 | } | |
1105 | ||
8776f02b MK |
1106 | static void gen8_free_scratch(struct i915_address_space *vm) |
1107 | { | |
1e6437b0 | 1108 | if (use_4lvl(vm)) |
8448661d CW |
1109 | free_pdp(vm, vm->scratch_pdp); |
1110 | free_pd(vm, vm->scratch_pd); | |
1111 | free_pt(vm, vm->scratch_pt); | |
1112 | cleanup_scratch_page(vm); | |
8776f02b MK |
1113 | } |
1114 | ||
8448661d | 1115 | static void gen8_ppgtt_cleanup_3lvl(struct i915_address_space *vm, |
762d9936 | 1116 | struct i915_page_directory_pointer *pdp) |
b45a6715 | 1117 | { |
3e490042 | 1118 | const unsigned int pdpes = i915_pdpes_per_pdp(vm); |
b45a6715 BW |
1119 | int i; |
1120 | ||
3e490042 | 1121 | for (i = 0; i < pdpes; i++) { |
fe52e37f | 1122 | if (pdp->page_directory[i] == vm->scratch_pd) |
06fda602 BW |
1123 | continue; |
1124 | ||
8448661d CW |
1125 | gen8_free_page_tables(vm, pdp->page_directory[i]); |
1126 | free_pd(vm, pdp->page_directory[i]); | |
7ad47cf2 | 1127 | } |
69876bed | 1128 | |
8448661d | 1129 | free_pdp(vm, pdp); |
762d9936 MT |
1130 | } |
1131 | ||
1132 | static void gen8_ppgtt_cleanup_4lvl(struct i915_hw_ppgtt *ppgtt) | |
1133 | { | |
1134 | int i; | |
1135 | ||
c5d092a4 CW |
1136 | for (i = 0; i < GEN8_PML4ES_PER_PML4; i++) { |
1137 | if (ppgtt->pml4.pdps[i] == ppgtt->base.scratch_pdp) | |
762d9936 MT |
1138 | continue; |
1139 | ||
8448661d | 1140 | gen8_ppgtt_cleanup_3lvl(&ppgtt->base, ppgtt->pml4.pdps[i]); |
762d9936 MT |
1141 | } |
1142 | ||
8448661d | 1143 | cleanup_px(&ppgtt->base, &ppgtt->pml4); |
762d9936 MT |
1144 | } |
1145 | ||
1146 | static void gen8_ppgtt_cleanup(struct i915_address_space *vm) | |
1147 | { | |
49d73912 | 1148 | struct drm_i915_private *dev_priv = vm->i915; |
e5716f55 | 1149 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
762d9936 | 1150 | |
275a991c | 1151 | if (intel_vgpu_active(dev_priv)) |
650da34c ZL |
1152 | gen8_ppgtt_notify_vgt(ppgtt, false); |
1153 | ||
1e6437b0 | 1154 | if (use_4lvl(vm)) |
762d9936 | 1155 | gen8_ppgtt_cleanup_4lvl(ppgtt); |
1e6437b0 MK |
1156 | else |
1157 | gen8_ppgtt_cleanup_3lvl(&ppgtt->base, &ppgtt->pdp); | |
d4ec9da0 | 1158 | |
8776f02b | 1159 | gen8_free_scratch(vm); |
b45a6715 BW |
1160 | } |
1161 | ||
fe52e37f CW |
1162 | static int gen8_ppgtt_alloc_pd(struct i915_address_space *vm, |
1163 | struct i915_page_directory *pd, | |
1164 | u64 start, u64 length) | |
bf2b4ed2 | 1165 | { |
d7b2633d | 1166 | struct i915_page_table *pt; |
dd19674b | 1167 | u64 from = start; |
fe52e37f | 1168 | unsigned int pde; |
bf2b4ed2 | 1169 | |
e8ebd8e2 | 1170 | gen8_for_each_pde(pt, pd, start, length, pde) { |
14826673 CW |
1171 | int count = gen8_pte_count(start, length); |
1172 | ||
fe52e37f | 1173 | if (pt == vm->scratch_pt) { |
dd19674b CW |
1174 | pt = alloc_pt(vm); |
1175 | if (IS_ERR(pt)) | |
1176 | goto unwind; | |
5441f0cb | 1177 | |
14826673 CW |
1178 | if (count < GEN8_PTES) |
1179 | gen8_initialize_pt(vm, pt); | |
fe52e37f CW |
1180 | |
1181 | gen8_ppgtt_set_pde(vm, pd, pt, pde); | |
1182 | pd->used_pdes++; | |
bf75d59e | 1183 | GEM_BUG_ON(pd->used_pdes > I915_PDES); |
dd19674b | 1184 | } |
fe52e37f | 1185 | |
14826673 | 1186 | pt->used_ptes += count; |
7ad47cf2 | 1187 | } |
bf2b4ed2 | 1188 | return 0; |
7ad47cf2 | 1189 | |
dd19674b CW |
1190 | unwind: |
1191 | gen8_ppgtt_clear_pd(vm, pd, from, start - from); | |
d7b3de91 | 1192 | return -ENOMEM; |
bf2b4ed2 BW |
1193 | } |
1194 | ||
c5d092a4 CW |
1195 | static int gen8_ppgtt_alloc_pdp(struct i915_address_space *vm, |
1196 | struct i915_page_directory_pointer *pdp, | |
1197 | u64 start, u64 length) | |
bf2b4ed2 | 1198 | { |
5441f0cb | 1199 | struct i915_page_directory *pd; |
e2b763ca CW |
1200 | u64 from = start; |
1201 | unsigned int pdpe; | |
bf2b4ed2 BW |
1202 | int ret; |
1203 | ||
e8ebd8e2 | 1204 | gen8_for_each_pdpe(pd, pdp, start, length, pdpe) { |
e2b763ca CW |
1205 | if (pd == vm->scratch_pd) { |
1206 | pd = alloc_pd(vm); | |
1207 | if (IS_ERR(pd)) | |
1208 | goto unwind; | |
5441f0cb | 1209 | |
e2b763ca | 1210 | gen8_initialize_pd(vm, pd); |
fe52e37f | 1211 | gen8_ppgtt_set_pdpe(vm, pdp, pd, pdpe); |
e2b763ca | 1212 | pdp->used_pdpes++; |
3e490042 | 1213 | GEM_BUG_ON(pdp->used_pdpes > i915_pdpes_per_pdp(vm)); |
75afcf72 CW |
1214 | |
1215 | mark_tlbs_dirty(i915_vm_to_ppgtt(vm)); | |
e2b763ca CW |
1216 | } |
1217 | ||
1218 | ret = gen8_ppgtt_alloc_pd(vm, pd, start, length); | |
bf75d59e CW |
1219 | if (unlikely(ret)) |
1220 | goto unwind_pd; | |
fe52e37f | 1221 | } |
33c8819f | 1222 | |
d7b3de91 | 1223 | return 0; |
bf2b4ed2 | 1224 | |
bf75d59e CW |
1225 | unwind_pd: |
1226 | if (!pd->used_pdes) { | |
1227 | gen8_ppgtt_set_pdpe(vm, pdp, vm->scratch_pd, pdpe); | |
1228 | GEM_BUG_ON(!pdp->used_pdpes); | |
1229 | pdp->used_pdpes--; | |
1230 | free_pd(vm, pd); | |
1231 | } | |
e2b763ca CW |
1232 | unwind: |
1233 | gen8_ppgtt_clear_pdp(vm, pdp, from, start - from); | |
1234 | return -ENOMEM; | |
bf2b4ed2 BW |
1235 | } |
1236 | ||
c5d092a4 CW |
1237 | static int gen8_ppgtt_alloc_3lvl(struct i915_address_space *vm, |
1238 | u64 start, u64 length) | |
762d9936 | 1239 | { |
c5d092a4 CW |
1240 | return gen8_ppgtt_alloc_pdp(vm, |
1241 | &i915_vm_to_ppgtt(vm)->pdp, start, length); | |
1242 | } | |
762d9936 | 1243 | |
c5d092a4 CW |
1244 | static int gen8_ppgtt_alloc_4lvl(struct i915_address_space *vm, |
1245 | u64 start, u64 length) | |
1246 | { | |
1247 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); | |
1248 | struct i915_pml4 *pml4 = &ppgtt->pml4; | |
1249 | struct i915_page_directory_pointer *pdp; | |
1250 | u64 from = start; | |
1251 | u32 pml4e; | |
1252 | int ret; | |
762d9936 | 1253 | |
e8ebd8e2 | 1254 | gen8_for_each_pml4e(pdp, pml4, start, length, pml4e) { |
c5d092a4 CW |
1255 | if (pml4->pdps[pml4e] == vm->scratch_pdp) { |
1256 | pdp = alloc_pdp(vm); | |
1257 | if (IS_ERR(pdp)) | |
1258 | goto unwind; | |
762d9936 | 1259 | |
c5d092a4 CW |
1260 | gen8_initialize_pdp(vm, pdp); |
1261 | gen8_ppgtt_set_pml4e(pml4, pdp, pml4e); | |
1262 | } | |
762d9936 | 1263 | |
c5d092a4 | 1264 | ret = gen8_ppgtt_alloc_pdp(vm, pdp, start, length); |
bf75d59e CW |
1265 | if (unlikely(ret)) |
1266 | goto unwind_pdp; | |
762d9936 MT |
1267 | } |
1268 | ||
762d9936 MT |
1269 | return 0; |
1270 | ||
bf75d59e CW |
1271 | unwind_pdp: |
1272 | if (!pdp->used_pdpes) { | |
1273 | gen8_ppgtt_set_pml4e(pml4, vm->scratch_pdp, pml4e); | |
1274 | free_pdp(vm, pdp); | |
1275 | } | |
c5d092a4 CW |
1276 | unwind: |
1277 | gen8_ppgtt_clear_4lvl(vm, from, start - from); | |
1278 | return -ENOMEM; | |
762d9936 MT |
1279 | } |
1280 | ||
8448661d CW |
1281 | static void gen8_dump_pdp(struct i915_hw_ppgtt *ppgtt, |
1282 | struct i915_page_directory_pointer *pdp, | |
75c7b0b8 | 1283 | u64 start, u64 length, |
ea91e401 MT |
1284 | gen8_pte_t scratch_pte, |
1285 | struct seq_file *m) | |
1286 | { | |
3e490042 | 1287 | struct i915_address_space *vm = &ppgtt->base; |
ea91e401 | 1288 | struct i915_page_directory *pd; |
75c7b0b8 | 1289 | u32 pdpe; |
ea91e401 | 1290 | |
e8ebd8e2 | 1291 | gen8_for_each_pdpe(pd, pdp, start, length, pdpe) { |
ea91e401 | 1292 | struct i915_page_table *pt; |
75c7b0b8 CW |
1293 | u64 pd_len = length; |
1294 | u64 pd_start = start; | |
1295 | u32 pde; | |
ea91e401 | 1296 | |
e2b763ca | 1297 | if (pdp->page_directory[pdpe] == ppgtt->base.scratch_pd) |
ea91e401 MT |
1298 | continue; |
1299 | ||
1300 | seq_printf(m, "\tPDPE #%d\n", pdpe); | |
e8ebd8e2 | 1301 | gen8_for_each_pde(pt, pd, pd_start, pd_len, pde) { |
75c7b0b8 | 1302 | u32 pte; |
ea91e401 MT |
1303 | gen8_pte_t *pt_vaddr; |
1304 | ||
fe52e37f | 1305 | if (pd->page_table[pde] == ppgtt->base.scratch_pt) |
ea91e401 MT |
1306 | continue; |
1307 | ||
9231da70 | 1308 | pt_vaddr = kmap_atomic_px(pt); |
ea91e401 | 1309 | for (pte = 0; pte < GEN8_PTES; pte += 4) { |
75c7b0b8 CW |
1310 | u64 va = (pdpe << GEN8_PDPE_SHIFT | |
1311 | pde << GEN8_PDE_SHIFT | | |
1312 | pte << GEN8_PTE_SHIFT); | |
ea91e401 MT |
1313 | int i; |
1314 | bool found = false; | |
1315 | ||
1316 | for (i = 0; i < 4; i++) | |
1317 | if (pt_vaddr[pte + i] != scratch_pte) | |
1318 | found = true; | |
1319 | if (!found) | |
1320 | continue; | |
1321 | ||
1322 | seq_printf(m, "\t\t0x%llx [%03d,%03d,%04d]: =", va, pdpe, pde, pte); | |
1323 | for (i = 0; i < 4; i++) { | |
1324 | if (pt_vaddr[pte + i] != scratch_pte) | |
1325 | seq_printf(m, " %llx", pt_vaddr[pte + i]); | |
1326 | else | |
1327 | seq_puts(m, " SCRATCH "); | |
1328 | } | |
1329 | seq_puts(m, "\n"); | |
1330 | } | |
ea91e401 MT |
1331 | kunmap_atomic(pt_vaddr); |
1332 | } | |
1333 | } | |
1334 | } | |
1335 | ||
1336 | static void gen8_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m) | |
1337 | { | |
1338 | struct i915_address_space *vm = &ppgtt->base; | |
894ccebe CW |
1339 | const gen8_pte_t scratch_pte = |
1340 | gen8_pte_encode(vm->scratch_page.daddr, I915_CACHE_LLC); | |
381b943b | 1341 | u64 start = 0, length = ppgtt->base.total; |
ea91e401 | 1342 | |
1e6437b0 | 1343 | if (use_4lvl(vm)) { |
75c7b0b8 | 1344 | u64 pml4e; |
ea91e401 MT |
1345 | struct i915_pml4 *pml4 = &ppgtt->pml4; |
1346 | struct i915_page_directory_pointer *pdp; | |
1347 | ||
e8ebd8e2 | 1348 | gen8_for_each_pml4e(pdp, pml4, start, length, pml4e) { |
c5d092a4 | 1349 | if (pml4->pdps[pml4e] == ppgtt->base.scratch_pdp) |
ea91e401 MT |
1350 | continue; |
1351 | ||
1352 | seq_printf(m, " PML4E #%llu\n", pml4e); | |
8448661d | 1353 | gen8_dump_pdp(ppgtt, pdp, start, length, scratch_pte, m); |
ea91e401 | 1354 | } |
1e6437b0 MK |
1355 | } else { |
1356 | gen8_dump_pdp(ppgtt, &ppgtt->pdp, start, length, scratch_pte, m); | |
ea91e401 MT |
1357 | } |
1358 | } | |
1359 | ||
e2b763ca | 1360 | static int gen8_preallocate_top_level_pdp(struct i915_hw_ppgtt *ppgtt) |
331f38e7 | 1361 | { |
e2b763ca CW |
1362 | struct i915_address_space *vm = &ppgtt->base; |
1363 | struct i915_page_directory_pointer *pdp = &ppgtt->pdp; | |
1364 | struct i915_page_directory *pd; | |
1365 | u64 start = 0, length = ppgtt->base.total; | |
1366 | u64 from = start; | |
1367 | unsigned int pdpe; | |
331f38e7 | 1368 | |
e2b763ca CW |
1369 | gen8_for_each_pdpe(pd, pdp, start, length, pdpe) { |
1370 | pd = alloc_pd(vm); | |
1371 | if (IS_ERR(pd)) | |
1372 | goto unwind; | |
331f38e7 | 1373 | |
e2b763ca CW |
1374 | gen8_initialize_pd(vm, pd); |
1375 | gen8_ppgtt_set_pdpe(vm, pdp, pd, pdpe); | |
1376 | pdp->used_pdpes++; | |
1377 | } | |
331f38e7 | 1378 | |
e2b763ca CW |
1379 | pdp->used_pdpes++; /* never remove */ |
1380 | return 0; | |
331f38e7 | 1381 | |
e2b763ca CW |
1382 | unwind: |
1383 | start -= from; | |
1384 | gen8_for_each_pdpe(pd, pdp, from, start, pdpe) { | |
1385 | gen8_ppgtt_set_pdpe(vm, pdp, vm->scratch_pd, pdpe); | |
1386 | free_pd(vm, pd); | |
1387 | } | |
1388 | pdp->used_pdpes = 0; | |
1389 | return -ENOMEM; | |
331f38e7 ZL |
1390 | } |
1391 | ||
eb0b44ad | 1392 | /* |
f3a964b9 BW |
1393 | * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers |
1394 | * with a net effect resembling a 2-level page table in normal x86 terms. Each | |
1395 | * PDP represents 1GB of memory 4 * 512 * 512 * 4096 = 4GB legacy 32b address | |
1396 | * space. | |
37aca44a | 1397 | * |
f3a964b9 | 1398 | */ |
5c5f6457 | 1399 | static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt) |
37aca44a | 1400 | { |
1e6437b0 MK |
1401 | struct i915_address_space *vm = &ppgtt->base; |
1402 | struct drm_i915_private *dev_priv = vm->i915; | |
8776f02b | 1403 | int ret; |
7cb6d7ac | 1404 | |
1e6437b0 MK |
1405 | ppgtt->base.total = USES_FULL_48BIT_PPGTT(dev_priv) ? |
1406 | 1ULL << 48 : | |
1407 | 1ULL << 32; | |
1408 | ||
8448661d CW |
1409 | /* There are only few exceptions for gen >=6. chv and bxt. |
1410 | * And we are not sure about the latter so play safe for now. | |
1411 | */ | |
1412 | if (IS_CHERRYVIEW(dev_priv) || IS_BROXTON(dev_priv)) | |
1413 | ppgtt->base.pt_kmap_wc = true; | |
1414 | ||
66df1014 CW |
1415 | ret = gen8_init_scratch(&ppgtt->base); |
1416 | if (ret) { | |
1417 | ppgtt->base.total = 0; | |
1418 | return ret; | |
1419 | } | |
1420 | ||
1e6437b0 | 1421 | if (use_4lvl(vm)) { |
8448661d | 1422 | ret = setup_px(&ppgtt->base, &ppgtt->pml4); |
762d9936 MT |
1423 | if (ret) |
1424 | goto free_scratch; | |
6ac18502 | 1425 | |
69ab76fd MT |
1426 | gen8_initialize_pml4(&ppgtt->base, &ppgtt->pml4); |
1427 | ||
e7167769 | 1428 | ppgtt->switch_mm = gen8_mm_switch_4lvl; |
c5d092a4 | 1429 | ppgtt->base.allocate_va_range = gen8_ppgtt_alloc_4lvl; |
894ccebe | 1430 | ppgtt->base.insert_entries = gen8_ppgtt_insert_4lvl; |
fe52e37f | 1431 | ppgtt->base.clear_range = gen8_ppgtt_clear_4lvl; |
762d9936 | 1432 | } else { |
fe52e37f | 1433 | ret = __pdp_init(&ppgtt->base, &ppgtt->pdp); |
81ba8aef MT |
1434 | if (ret) |
1435 | goto free_scratch; | |
1436 | ||
275a991c | 1437 | if (intel_vgpu_active(dev_priv)) { |
e2b763ca CW |
1438 | ret = gen8_preallocate_top_level_pdp(ppgtt); |
1439 | if (ret) { | |
1440 | __pdp_fini(&ppgtt->pdp); | |
331f38e7 | 1441 | goto free_scratch; |
e2b763ca | 1442 | } |
331f38e7 | 1443 | } |
894ccebe | 1444 | |
e7167769 | 1445 | ppgtt->switch_mm = gen8_mm_switch_3lvl; |
c5d092a4 | 1446 | ppgtt->base.allocate_va_range = gen8_ppgtt_alloc_3lvl; |
894ccebe | 1447 | ppgtt->base.insert_entries = gen8_ppgtt_insert_3lvl; |
fe52e37f | 1448 | ppgtt->base.clear_range = gen8_ppgtt_clear_3lvl; |
81ba8aef | 1449 | } |
6ac18502 | 1450 | |
275a991c | 1451 | if (intel_vgpu_active(dev_priv)) |
650da34c ZL |
1452 | gen8_ppgtt_notify_vgt(ppgtt, true); |
1453 | ||
054b9acd MK |
1454 | ppgtt->base.cleanup = gen8_ppgtt_cleanup; |
1455 | ppgtt->base.unbind_vma = ppgtt_unbind_vma; | |
1456 | ppgtt->base.bind_vma = ppgtt_bind_vma; | |
1457 | ppgtt->debug_dump = gen8_dump_ppgtt; | |
1458 | ||
d7b2633d | 1459 | return 0; |
6ac18502 MT |
1460 | |
1461 | free_scratch: | |
1462 | gen8_free_scratch(&ppgtt->base); | |
1463 | return ret; | |
d7b2633d MT |
1464 | } |
1465 | ||
87d60b63 BW |
1466 | static void gen6_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m) |
1467 | { | |
87d60b63 | 1468 | struct i915_address_space *vm = &ppgtt->base; |
09942c65 | 1469 | struct i915_page_table *unused; |
07749ef3 | 1470 | gen6_pte_t scratch_pte; |
381b943b CW |
1471 | u32 pd_entry, pte, pde; |
1472 | u32 start = 0, length = ppgtt->base.total; | |
87d60b63 | 1473 | |
8bcdd0f7 | 1474 | scratch_pte = vm->pte_encode(vm->scratch_page.daddr, |
4fb84d99 | 1475 | I915_CACHE_LLC, 0); |
87d60b63 | 1476 | |
731f74c5 | 1477 | gen6_for_each_pde(unused, &ppgtt->pd, start, length, pde) { |
87d60b63 | 1478 | u32 expected; |
07749ef3 | 1479 | gen6_pte_t *pt_vaddr; |
567047be | 1480 | const dma_addr_t pt_addr = px_dma(ppgtt->pd.page_table[pde]); |
09942c65 | 1481 | pd_entry = readl(ppgtt->pd_addr + pde); |
87d60b63 BW |
1482 | expected = (GEN6_PDE_ADDR_ENCODE(pt_addr) | GEN6_PDE_VALID); |
1483 | ||
1484 | if (pd_entry != expected) | |
1485 | seq_printf(m, "\tPDE #%d mismatch: Actual PDE: %x Expected PDE: %x\n", | |
1486 | pde, | |
1487 | pd_entry, | |
1488 | expected); | |
1489 | seq_printf(m, "\tPDE: %x\n", pd_entry); | |
1490 | ||
9231da70 | 1491 | pt_vaddr = kmap_atomic_px(ppgtt->pd.page_table[pde]); |
d1c54acd | 1492 | |
07749ef3 | 1493 | for (pte = 0; pte < GEN6_PTES; pte+=4) { |
87d60b63 | 1494 | unsigned long va = |
07749ef3 | 1495 | (pde * PAGE_SIZE * GEN6_PTES) + |
87d60b63 BW |
1496 | (pte * PAGE_SIZE); |
1497 | int i; | |
1498 | bool found = false; | |
1499 | for (i = 0; i < 4; i++) | |
1500 | if (pt_vaddr[pte + i] != scratch_pte) | |
1501 | found = true; | |
1502 | if (!found) | |
1503 | continue; | |
1504 | ||
1505 | seq_printf(m, "\t\t0x%lx [%03d,%04d]: =", va, pde, pte); | |
1506 | for (i = 0; i < 4; i++) { | |
1507 | if (pt_vaddr[pte + i] != scratch_pte) | |
1508 | seq_printf(m, " %08x", pt_vaddr[pte + i]); | |
1509 | else | |
1510 | seq_puts(m, " SCRATCH "); | |
1511 | } | |
1512 | seq_puts(m, "\n"); | |
1513 | } | |
9231da70 | 1514 | kunmap_atomic(pt_vaddr); |
87d60b63 BW |
1515 | } |
1516 | } | |
1517 | ||
678d96fb | 1518 | /* Write pde (index) from the page directory @pd to the page table @pt */ |
16a011c8 CW |
1519 | static inline void gen6_write_pde(const struct i915_hw_ppgtt *ppgtt, |
1520 | const unsigned int pde, | |
1521 | const struct i915_page_table *pt) | |
6197349b | 1522 | { |
678d96fb | 1523 | /* Caller needs to make sure the write completes if necessary */ |
16a011c8 CW |
1524 | writel_relaxed(GEN6_PDE_ADDR_ENCODE(px_dma(pt)) | GEN6_PDE_VALID, |
1525 | ppgtt->pd_addr + pde); | |
678d96fb | 1526 | } |
6197349b | 1527 | |
678d96fb BW |
1528 | /* Write all the page tables found in the ppgtt structure to incrementing page |
1529 | * directories. */ | |
16a011c8 | 1530 | static void gen6_write_page_range(struct i915_hw_ppgtt *ppgtt, |
75c7b0b8 | 1531 | u32 start, u32 length) |
678d96fb | 1532 | { |
ec565b3c | 1533 | struct i915_page_table *pt; |
16a011c8 | 1534 | unsigned int pde; |
678d96fb | 1535 | |
16a011c8 CW |
1536 | gen6_for_each_pde(pt, &ppgtt->pd, start, length, pde) |
1537 | gen6_write_pde(ppgtt, pde, pt); | |
678d96fb | 1538 | |
16a011c8 | 1539 | mark_tlbs_dirty(ppgtt); |
dd19674b | 1540 | wmb(); |
3e302542 BW |
1541 | } |
1542 | ||
75c7b0b8 | 1543 | static inline u32 get_pd_offset(struct i915_hw_ppgtt *ppgtt) |
3e302542 | 1544 | { |
dd19674b CW |
1545 | GEM_BUG_ON(ppgtt->pd.base.ggtt_offset & 0x3f); |
1546 | return ppgtt->pd.base.ggtt_offset << 10; | |
b4a74e3a BW |
1547 | } |
1548 | ||
90252e5c | 1549 | static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt, |
e85b26dc | 1550 | struct drm_i915_gem_request *req) |
90252e5c | 1551 | { |
4a570db5 | 1552 | struct intel_engine_cs *engine = req->engine; |
73dec95e | 1553 | u32 *cs; |
90252e5c | 1554 | |
90252e5c | 1555 | /* NB: TLBs must be flushed and invalidated before a switch */ |
73dec95e TU |
1556 | cs = intel_ring_begin(req, 6); |
1557 | if (IS_ERR(cs)) | |
1558 | return PTR_ERR(cs); | |
90252e5c | 1559 | |
73dec95e TU |
1560 | *cs++ = MI_LOAD_REGISTER_IMM(2); |
1561 | *cs++ = i915_mmio_reg_offset(RING_PP_DIR_DCLV(engine)); | |
1562 | *cs++ = PP_DIR_DCLV_2G; | |
1563 | *cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine)); | |
1564 | *cs++ = get_pd_offset(ppgtt); | |
1565 | *cs++ = MI_NOOP; | |
1566 | intel_ring_advance(req, cs); | |
90252e5c BW |
1567 | |
1568 | return 0; | |
1569 | } | |
1570 | ||
48a10389 | 1571 | static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt, |
e85b26dc | 1572 | struct drm_i915_gem_request *req) |
48a10389 | 1573 | { |
4a570db5 | 1574 | struct intel_engine_cs *engine = req->engine; |
73dec95e | 1575 | u32 *cs; |
48a10389 | 1576 | |
48a10389 | 1577 | /* NB: TLBs must be flushed and invalidated before a switch */ |
73dec95e TU |
1578 | cs = intel_ring_begin(req, 6); |
1579 | if (IS_ERR(cs)) | |
1580 | return PTR_ERR(cs); | |
1581 | ||
1582 | *cs++ = MI_LOAD_REGISTER_IMM(2); | |
1583 | *cs++ = i915_mmio_reg_offset(RING_PP_DIR_DCLV(engine)); | |
1584 | *cs++ = PP_DIR_DCLV_2G; | |
1585 | *cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine)); | |
1586 | *cs++ = get_pd_offset(ppgtt); | |
1587 | *cs++ = MI_NOOP; | |
1588 | intel_ring_advance(req, cs); | |
48a10389 BW |
1589 | |
1590 | return 0; | |
1591 | } | |
1592 | ||
eeb9488e | 1593 | static int gen6_mm_switch(struct i915_hw_ppgtt *ppgtt, |
e85b26dc | 1594 | struct drm_i915_gem_request *req) |
eeb9488e | 1595 | { |
4a570db5 | 1596 | struct intel_engine_cs *engine = req->engine; |
8eb95204 | 1597 | struct drm_i915_private *dev_priv = req->i915; |
48a10389 | 1598 | |
e2f80391 TU |
1599 | I915_WRITE(RING_PP_DIR_DCLV(engine), PP_DIR_DCLV_2G); |
1600 | I915_WRITE(RING_PP_DIR_BASE(engine), get_pd_offset(ppgtt)); | |
eeb9488e BW |
1601 | return 0; |
1602 | } | |
1603 | ||
c6be607a | 1604 | static void gen8_ppgtt_enable(struct drm_i915_private *dev_priv) |
eeb9488e | 1605 | { |
e2f80391 | 1606 | struct intel_engine_cs *engine; |
3b3f1650 | 1607 | enum intel_engine_id id; |
3e302542 | 1608 | |
3b3f1650 | 1609 | for_each_engine(engine, dev_priv, id) { |
c6be607a TU |
1610 | u32 four_level = USES_FULL_48BIT_PPGTT(dev_priv) ? |
1611 | GEN8_GFX_PPGTT_48B : 0; | |
e2f80391 | 1612 | I915_WRITE(RING_MODE_GEN7(engine), |
2dba3239 | 1613 | _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE | four_level)); |
eeb9488e | 1614 | } |
eeb9488e | 1615 | } |
6197349b | 1616 | |
c6be607a | 1617 | static void gen7_ppgtt_enable(struct drm_i915_private *dev_priv) |
3e302542 | 1618 | { |
e2f80391 | 1619 | struct intel_engine_cs *engine; |
75c7b0b8 | 1620 | u32 ecochk, ecobits; |
3b3f1650 | 1621 | enum intel_engine_id id; |
6197349b | 1622 | |
b4a74e3a BW |
1623 | ecobits = I915_READ(GAC_ECO_BITS); |
1624 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B); | |
a65c2fcd | 1625 | |
b4a74e3a | 1626 | ecochk = I915_READ(GAM_ECOCHK); |
772c2a51 | 1627 | if (IS_HASWELL(dev_priv)) { |
b4a74e3a BW |
1628 | ecochk |= ECOCHK_PPGTT_WB_HSW; |
1629 | } else { | |
1630 | ecochk |= ECOCHK_PPGTT_LLC_IVB; | |
1631 | ecochk &= ~ECOCHK_PPGTT_GFDT_IVB; | |
1632 | } | |
1633 | I915_WRITE(GAM_ECOCHK, ecochk); | |
a65c2fcd | 1634 | |
3b3f1650 | 1635 | for_each_engine(engine, dev_priv, id) { |
6197349b | 1636 | /* GFX_MODE is per-ring on gen7+ */ |
e2f80391 | 1637 | I915_WRITE(RING_MODE_GEN7(engine), |
b4a74e3a | 1638 | _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); |
6197349b | 1639 | } |
b4a74e3a | 1640 | } |
6197349b | 1641 | |
c6be607a | 1642 | static void gen6_ppgtt_enable(struct drm_i915_private *dev_priv) |
b4a74e3a | 1643 | { |
75c7b0b8 | 1644 | u32 ecochk, gab_ctl, ecobits; |
a65c2fcd | 1645 | |
b4a74e3a BW |
1646 | ecobits = I915_READ(GAC_ECO_BITS); |
1647 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT | | |
1648 | ECOBITS_PPGTT_CACHE64B); | |
6197349b | 1649 | |
b4a74e3a BW |
1650 | gab_ctl = I915_READ(GAB_CTL); |
1651 | I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT); | |
1652 | ||
1653 | ecochk = I915_READ(GAM_ECOCHK); | |
1654 | I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B); | |
1655 | ||
1656 | I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
6197349b BW |
1657 | } |
1658 | ||
1d2a314c | 1659 | /* PPGTT support for Sandybdrige/Gen6 and later */ |
853ba5d2 | 1660 | static void gen6_ppgtt_clear_range(struct i915_address_space *vm, |
dd19674b | 1661 | u64 start, u64 length) |
1d2a314c | 1662 | { |
e5716f55 | 1663 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
dd19674b CW |
1664 | unsigned int first_entry = start >> PAGE_SHIFT; |
1665 | unsigned int pde = first_entry / GEN6_PTES; | |
1666 | unsigned int pte = first_entry % GEN6_PTES; | |
1667 | unsigned int num_entries = length >> PAGE_SHIFT; | |
1668 | gen6_pte_t scratch_pte = | |
1669 | vm->pte_encode(vm->scratch_page.daddr, I915_CACHE_LLC, 0); | |
1d2a314c | 1670 | |
7bddb01f | 1671 | while (num_entries) { |
dd19674b CW |
1672 | struct i915_page_table *pt = ppgtt->pd.page_table[pde++]; |
1673 | unsigned int end = min(pte + num_entries, GEN6_PTES); | |
1674 | gen6_pte_t *vaddr; | |
7bddb01f | 1675 | |
dd19674b | 1676 | num_entries -= end - pte; |
1d2a314c | 1677 | |
dd19674b CW |
1678 | /* Note that the hw doesn't support removing PDE on the fly |
1679 | * (they are cached inside the context with no means to | |
1680 | * invalidate the cache), so we can only reset the PTE | |
1681 | * entries back to scratch. | |
1682 | */ | |
1d2a314c | 1683 | |
dd19674b CW |
1684 | vaddr = kmap_atomic_px(pt); |
1685 | do { | |
1686 | vaddr[pte++] = scratch_pte; | |
1687 | } while (pte < end); | |
1688 | kunmap_atomic(vaddr); | |
1d2a314c | 1689 | |
dd19674b | 1690 | pte = 0; |
7bddb01f | 1691 | } |
1d2a314c DV |
1692 | } |
1693 | ||
853ba5d2 | 1694 | static void gen6_ppgtt_insert_entries(struct i915_address_space *vm, |
4a234c5f | 1695 | struct i915_vma *vma, |
75c7b0b8 CW |
1696 | enum i915_cache_level cache_level, |
1697 | u32 flags) | |
def886c3 | 1698 | { |
e5716f55 | 1699 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
4a234c5f | 1700 | unsigned first_entry = vma->node.start >> PAGE_SHIFT; |
07749ef3 MT |
1701 | unsigned act_pt = first_entry / GEN6_PTES; |
1702 | unsigned act_pte = first_entry % GEN6_PTES; | |
b31144c0 CW |
1703 | const u32 pte_encode = vm->pte_encode(0, cache_level, flags); |
1704 | struct sgt_dma iter; | |
1705 | gen6_pte_t *vaddr; | |
1706 | ||
9231da70 | 1707 | vaddr = kmap_atomic_px(ppgtt->pd.page_table[act_pt]); |
4a234c5f | 1708 | iter.sg = vma->pages->sgl; |
b31144c0 CW |
1709 | iter.dma = sg_dma_address(iter.sg); |
1710 | iter.max = iter.dma + iter.sg->length; | |
1711 | do { | |
1712 | vaddr[act_pte] = pte_encode | GEN6_PTE_ADDR_ENCODE(iter.dma); | |
6e995e23 | 1713 | |
b31144c0 CW |
1714 | iter.dma += PAGE_SIZE; |
1715 | if (iter.dma == iter.max) { | |
1716 | iter.sg = __sg_next(iter.sg); | |
1717 | if (!iter.sg) | |
1718 | break; | |
6e995e23 | 1719 | |
b31144c0 CW |
1720 | iter.dma = sg_dma_address(iter.sg); |
1721 | iter.max = iter.dma + iter.sg->length; | |
1722 | } | |
24f3a8cf | 1723 | |
07749ef3 | 1724 | if (++act_pte == GEN6_PTES) { |
9231da70 CW |
1725 | kunmap_atomic(vaddr); |
1726 | vaddr = kmap_atomic_px(ppgtt->pd.page_table[++act_pt]); | |
6e995e23 | 1727 | act_pte = 0; |
def886c3 | 1728 | } |
b31144c0 | 1729 | } while (1); |
9231da70 | 1730 | kunmap_atomic(vaddr); |
def886c3 DV |
1731 | } |
1732 | ||
678d96fb | 1733 | static int gen6_alloc_va_range(struct i915_address_space *vm, |
dd19674b | 1734 | u64 start, u64 length) |
678d96fb | 1735 | { |
e5716f55 | 1736 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
ec565b3c | 1737 | struct i915_page_table *pt; |
dd19674b CW |
1738 | u64 from = start; |
1739 | unsigned int pde; | |
1740 | bool flush = false; | |
4933d519 | 1741 | |
731f74c5 | 1742 | gen6_for_each_pde(pt, &ppgtt->pd, start, length, pde) { |
dd19674b CW |
1743 | if (pt == vm->scratch_pt) { |
1744 | pt = alloc_pt(vm); | |
1745 | if (IS_ERR(pt)) | |
1746 | goto unwind_out; | |
4933d519 | 1747 | |
dd19674b CW |
1748 | gen6_initialize_pt(vm, pt); |
1749 | ppgtt->pd.page_table[pde] = pt; | |
1750 | gen6_write_pde(ppgtt, pde, pt); | |
1751 | flush = true; | |
4933d519 | 1752 | } |
4933d519 MT |
1753 | } |
1754 | ||
dd19674b CW |
1755 | if (flush) { |
1756 | mark_tlbs_dirty(ppgtt); | |
1757 | wmb(); | |
678d96fb BW |
1758 | } |
1759 | ||
1760 | return 0; | |
4933d519 MT |
1761 | |
1762 | unwind_out: | |
dd19674b CW |
1763 | gen6_ppgtt_clear_range(vm, from, start); |
1764 | return -ENOMEM; | |
678d96fb BW |
1765 | } |
1766 | ||
8776f02b MK |
1767 | static int gen6_init_scratch(struct i915_address_space *vm) |
1768 | { | |
8bcdd0f7 | 1769 | int ret; |
8776f02b | 1770 | |
8448661d | 1771 | ret = setup_scratch_page(vm, I915_GFP_DMA); |
8bcdd0f7 CW |
1772 | if (ret) |
1773 | return ret; | |
8776f02b | 1774 | |
8448661d | 1775 | vm->scratch_pt = alloc_pt(vm); |
8776f02b | 1776 | if (IS_ERR(vm->scratch_pt)) { |
8448661d | 1777 | cleanup_scratch_page(vm); |
8776f02b MK |
1778 | return PTR_ERR(vm->scratch_pt); |
1779 | } | |
1780 | ||
1781 | gen6_initialize_pt(vm, vm->scratch_pt); | |
1782 | ||
1783 | return 0; | |
1784 | } | |
1785 | ||
1786 | static void gen6_free_scratch(struct i915_address_space *vm) | |
1787 | { | |
8448661d CW |
1788 | free_pt(vm, vm->scratch_pt); |
1789 | cleanup_scratch_page(vm); | |
8776f02b MK |
1790 | } |
1791 | ||
061dd493 | 1792 | static void gen6_ppgtt_cleanup(struct i915_address_space *vm) |
a00d825d | 1793 | { |
e5716f55 | 1794 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
731f74c5 | 1795 | struct i915_page_directory *pd = &ppgtt->pd; |
09942c65 | 1796 | struct i915_page_table *pt; |
75c7b0b8 | 1797 | u32 pde; |
4933d519 | 1798 | |
061dd493 DV |
1799 | drm_mm_remove_node(&ppgtt->node); |
1800 | ||
731f74c5 | 1801 | gen6_for_all_pdes(pt, pd, pde) |
79ab9370 | 1802 | if (pt != vm->scratch_pt) |
8448661d | 1803 | free_pt(vm, pt); |
06fda602 | 1804 | |
8776f02b | 1805 | gen6_free_scratch(vm); |
3440d265 DV |
1806 | } |
1807 | ||
b146520f | 1808 | static int gen6_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt) |
3440d265 | 1809 | { |
8776f02b | 1810 | struct i915_address_space *vm = &ppgtt->base; |
49d73912 | 1811 | struct drm_i915_private *dev_priv = ppgtt->base.i915; |
72e96d64 | 1812 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
b146520f | 1813 | int ret; |
1d2a314c | 1814 | |
c8d4c0d6 BW |
1815 | /* PPGTT PDEs reside in the GGTT and consists of 512 entries. The |
1816 | * allocator works in address space sizes, so it's multiplied by page | |
1817 | * size. We allocate at the top of the GTT to avoid fragmentation. | |
1818 | */ | |
72e96d64 | 1819 | BUG_ON(!drm_mm_initialized(&ggtt->base.mm)); |
4933d519 | 1820 | |
8776f02b MK |
1821 | ret = gen6_init_scratch(vm); |
1822 | if (ret) | |
1823 | return ret; | |
4933d519 | 1824 | |
e007b19d CW |
1825 | ret = i915_gem_gtt_insert(&ggtt->base, &ppgtt->node, |
1826 | GEN6_PD_SIZE, GEN6_PD_ALIGN, | |
1827 | I915_COLOR_UNEVICTABLE, | |
1828 | 0, ggtt->base.total, | |
1829 | PIN_HIGH); | |
c8c26622 | 1830 | if (ret) |
678d96fb BW |
1831 | goto err_out; |
1832 | ||
72e96d64 | 1833 | if (ppgtt->node.start < ggtt->mappable_end) |
c8d4c0d6 | 1834 | DRM_DEBUG("Forced to use aperture for PDEs\n"); |
1d2a314c | 1835 | |
52c126ee CW |
1836 | ppgtt->pd.base.ggtt_offset = |
1837 | ppgtt->node.start / PAGE_SIZE * sizeof(gen6_pte_t); | |
1838 | ||
1839 | ppgtt->pd_addr = (gen6_pte_t __iomem *)ggtt->gsm + | |
1840 | ppgtt->pd.base.ggtt_offset / sizeof(gen6_pte_t); | |
1841 | ||
c8c26622 | 1842 | return 0; |
678d96fb BW |
1843 | |
1844 | err_out: | |
8776f02b | 1845 | gen6_free_scratch(vm); |
678d96fb | 1846 | return ret; |
b146520f BW |
1847 | } |
1848 | ||
b146520f BW |
1849 | static int gen6_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt) |
1850 | { | |
2f2cf682 | 1851 | return gen6_ppgtt_allocate_page_directories(ppgtt); |
4933d519 | 1852 | } |
06dc68d6 | 1853 | |
4933d519 | 1854 | static void gen6_scratch_va_range(struct i915_hw_ppgtt *ppgtt, |
75c7b0b8 | 1855 | u64 start, u64 length) |
4933d519 | 1856 | { |
ec565b3c | 1857 | struct i915_page_table *unused; |
75c7b0b8 | 1858 | u32 pde; |
1d2a314c | 1859 | |
731f74c5 | 1860 | gen6_for_each_pde(unused, &ppgtt->pd, start, length, pde) |
79ab9370 | 1861 | ppgtt->pd.page_table[pde] = ppgtt->base.scratch_pt; |
b146520f BW |
1862 | } |
1863 | ||
5c5f6457 | 1864 | static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt) |
b146520f | 1865 | { |
49d73912 | 1866 | struct drm_i915_private *dev_priv = ppgtt->base.i915; |
72e96d64 | 1867 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
b146520f BW |
1868 | int ret; |
1869 | ||
72e96d64 | 1870 | ppgtt->base.pte_encode = ggtt->base.pte_encode; |
5db94019 | 1871 | if (intel_vgpu_active(dev_priv) || IS_GEN6(dev_priv)) |
b146520f | 1872 | ppgtt->switch_mm = gen6_mm_switch; |
772c2a51 | 1873 | else if (IS_HASWELL(dev_priv)) |
b146520f | 1874 | ppgtt->switch_mm = hsw_mm_switch; |
5db94019 | 1875 | else if (IS_GEN7(dev_priv)) |
b146520f | 1876 | ppgtt->switch_mm = gen7_mm_switch; |
8eb95204 | 1877 | else |
b146520f BW |
1878 | BUG(); |
1879 | ||
1880 | ret = gen6_ppgtt_alloc(ppgtt); | |
1881 | if (ret) | |
1882 | return ret; | |
1883 | ||
09942c65 | 1884 | ppgtt->base.total = I915_PDES * GEN6_PTES * PAGE_SIZE; |
1d2a314c | 1885 | |
5c5f6457 | 1886 | gen6_scratch_va_range(ppgtt, 0, ppgtt->base.total); |
16a011c8 | 1887 | gen6_write_page_range(ppgtt, 0, ppgtt->base.total); |
678d96fb | 1888 | |
52c126ee CW |
1889 | ret = gen6_alloc_va_range(&ppgtt->base, 0, ppgtt->base.total); |
1890 | if (ret) { | |
1891 | gen6_ppgtt_cleanup(&ppgtt->base); | |
1892 | return ret; | |
1893 | } | |
1894 | ||
054b9acd MK |
1895 | ppgtt->base.clear_range = gen6_ppgtt_clear_range; |
1896 | ppgtt->base.insert_entries = gen6_ppgtt_insert_entries; | |
1897 | ppgtt->base.unbind_vma = ppgtt_unbind_vma; | |
1898 | ppgtt->base.bind_vma = ppgtt_bind_vma; | |
1899 | ppgtt->base.cleanup = gen6_ppgtt_cleanup; | |
1900 | ppgtt->debug_dump = gen6_dump_ppgtt; | |
1901 | ||
440fd528 | 1902 | DRM_DEBUG_DRIVER("Allocated pde space (%lldM) at GTT entry: %llx\n", |
b146520f BW |
1903 | ppgtt->node.size >> 20, |
1904 | ppgtt->node.start / PAGE_SIZE); | |
3440d265 | 1905 | |
52c126ee CW |
1906 | DRM_DEBUG_DRIVER("Adding PPGTT at offset %x\n", |
1907 | ppgtt->pd.base.ggtt_offset << 10); | |
fa76da34 | 1908 | |
b146520f | 1909 | return 0; |
3440d265 DV |
1910 | } |
1911 | ||
2bfa996e CW |
1912 | static int __hw_ppgtt_init(struct i915_hw_ppgtt *ppgtt, |
1913 | struct drm_i915_private *dev_priv) | |
3440d265 | 1914 | { |
49d73912 | 1915 | ppgtt->base.i915 = dev_priv; |
8448661d | 1916 | ppgtt->base.dma = &dev_priv->drm.pdev->dev; |
3440d265 | 1917 | |
2bfa996e | 1918 | if (INTEL_INFO(dev_priv)->gen < 8) |
5c5f6457 | 1919 | return gen6_ppgtt_init(ppgtt); |
3ed124b2 | 1920 | else |
d7b2633d | 1921 | return gen8_ppgtt_init(ppgtt); |
fa76da34 | 1922 | } |
c114f76a | 1923 | |
a2cad9df | 1924 | static void i915_address_space_init(struct i915_address_space *vm, |
80b204bc CW |
1925 | struct drm_i915_private *dev_priv, |
1926 | const char *name) | |
a2cad9df | 1927 | { |
80b204bc | 1928 | i915_gem_timeline_init(dev_priv, &vm->timeline, name); |
47db922f | 1929 | |
381b943b | 1930 | drm_mm_init(&vm->mm, 0, vm->total); |
47db922f CW |
1931 | vm->mm.head_node.color = I915_COLOR_UNEVICTABLE; |
1932 | ||
a2cad9df MW |
1933 | INIT_LIST_HEAD(&vm->active_list); |
1934 | INIT_LIST_HEAD(&vm->inactive_list); | |
50e046b6 | 1935 | INIT_LIST_HEAD(&vm->unbound_list); |
47db922f | 1936 | |
a2cad9df | 1937 | list_add_tail(&vm->global_link, &dev_priv->vm_list); |
8448661d | 1938 | pagevec_init(&vm->free_pages, false); |
a2cad9df MW |
1939 | } |
1940 | ||
ed9724dd MA |
1941 | static void i915_address_space_fini(struct i915_address_space *vm) |
1942 | { | |
8448661d | 1943 | if (pagevec_count(&vm->free_pages)) |
66df1014 | 1944 | vm_free_pages_release(vm, true); |
8448661d | 1945 | |
ed9724dd MA |
1946 | i915_gem_timeline_fini(&vm->timeline); |
1947 | drm_mm_takedown(&vm->mm); | |
1948 | list_del(&vm->global_link); | |
1949 | } | |
1950 | ||
c6be607a | 1951 | static void gtt_write_workarounds(struct drm_i915_private *dev_priv) |
d5165ebd | 1952 | { |
d5165ebd TG |
1953 | /* This function is for gtt related workarounds. This function is |
1954 | * called on driver load and after a GPU reset, so you can place | |
1955 | * workarounds here even if they get overwritten by GPU reset. | |
1956 | */ | |
90007bca | 1957 | /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk,cfl,cnl */ |
8652744b | 1958 | if (IS_BROADWELL(dev_priv)) |
d5165ebd | 1959 | I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW); |
920a14b2 | 1960 | else if (IS_CHERRYVIEW(dev_priv)) |
d5165ebd | 1961 | I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV); |
90007bca | 1962 | else if (IS_GEN9_BC(dev_priv) || IS_GEN10(dev_priv)) |
d5165ebd | 1963 | I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL); |
9fb5026f | 1964 | else if (IS_GEN9_LP(dev_priv)) |
d5165ebd TG |
1965 | I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT); |
1966 | } | |
1967 | ||
c6be607a | 1968 | int i915_ppgtt_init_hw(struct drm_i915_private *dev_priv) |
82460d97 | 1969 | { |
c6be607a | 1970 | gtt_write_workarounds(dev_priv); |
d5165ebd | 1971 | |
671b5013 TD |
1972 | /* In the case of execlists, PPGTT is enabled by the context descriptor |
1973 | * and the PDPs are contained within the context itself. We don't | |
1974 | * need to do anything here. */ | |
1975 | if (i915.enable_execlists) | |
1976 | return 0; | |
1977 | ||
c6be607a | 1978 | if (!USES_PPGTT(dev_priv)) |
82460d97 DV |
1979 | return 0; |
1980 | ||
5db94019 | 1981 | if (IS_GEN6(dev_priv)) |
c6be607a | 1982 | gen6_ppgtt_enable(dev_priv); |
5db94019 | 1983 | else if (IS_GEN7(dev_priv)) |
c6be607a TU |
1984 | gen7_ppgtt_enable(dev_priv); |
1985 | else if (INTEL_GEN(dev_priv) >= 8) | |
1986 | gen8_ppgtt_enable(dev_priv); | |
82460d97 | 1987 | else |
c6be607a | 1988 | MISSING_CASE(INTEL_GEN(dev_priv)); |
82460d97 | 1989 | |
4ad2fd88 JH |
1990 | return 0; |
1991 | } | |
1d2a314c | 1992 | |
4d884705 | 1993 | struct i915_hw_ppgtt * |
2bfa996e | 1994 | i915_ppgtt_create(struct drm_i915_private *dev_priv, |
80b204bc CW |
1995 | struct drm_i915_file_private *fpriv, |
1996 | const char *name) | |
4d884705 DV |
1997 | { |
1998 | struct i915_hw_ppgtt *ppgtt; | |
1999 | int ret; | |
2000 | ||
2001 | ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL); | |
2002 | if (!ppgtt) | |
2003 | return ERR_PTR(-ENOMEM); | |
2004 | ||
1188bc66 | 2005 | ret = __hw_ppgtt_init(ppgtt, dev_priv); |
4d884705 DV |
2006 | if (ret) { |
2007 | kfree(ppgtt); | |
2008 | return ERR_PTR(ret); | |
2009 | } | |
2010 | ||
1188bc66 CW |
2011 | kref_init(&ppgtt->ref); |
2012 | i915_address_space_init(&ppgtt->base, dev_priv, name); | |
2013 | ppgtt->base.file = fpriv; | |
2014 | ||
198c974d DCS |
2015 | trace_i915_ppgtt_create(&ppgtt->base); |
2016 | ||
4d884705 DV |
2017 | return ppgtt; |
2018 | } | |
2019 | ||
0c7eeda1 CW |
2020 | void i915_ppgtt_close(struct i915_address_space *vm) |
2021 | { | |
2022 | struct list_head *phases[] = { | |
2023 | &vm->active_list, | |
2024 | &vm->inactive_list, | |
2025 | &vm->unbound_list, | |
2026 | NULL, | |
2027 | }, **phase; | |
2028 | ||
2029 | GEM_BUG_ON(vm->closed); | |
2030 | vm->closed = true; | |
2031 | ||
2032 | for (phase = phases; *phase; phase++) { | |
2033 | struct i915_vma *vma, *vn; | |
2034 | ||
2035 | list_for_each_entry_safe(vma, vn, *phase, vm_link) | |
2036 | if (!i915_vma_is_closed(vma)) | |
2037 | i915_vma_close(vma); | |
2038 | } | |
2039 | } | |
2040 | ||
ed9724dd | 2041 | void i915_ppgtt_release(struct kref *kref) |
ee960be7 DV |
2042 | { |
2043 | struct i915_hw_ppgtt *ppgtt = | |
2044 | container_of(kref, struct i915_hw_ppgtt, ref); | |
2045 | ||
198c974d DCS |
2046 | trace_i915_ppgtt_release(&ppgtt->base); |
2047 | ||
50e046b6 | 2048 | /* vmas should already be unbound and destroyed */ |
ee960be7 DV |
2049 | WARN_ON(!list_empty(&ppgtt->base.active_list)); |
2050 | WARN_ON(!list_empty(&ppgtt->base.inactive_list)); | |
50e046b6 | 2051 | WARN_ON(!list_empty(&ppgtt->base.unbound_list)); |
ee960be7 DV |
2052 | |
2053 | ppgtt->base.cleanup(&ppgtt->base); | |
8448661d | 2054 | i915_address_space_fini(&ppgtt->base); |
ee960be7 DV |
2055 | kfree(ppgtt); |
2056 | } | |
1d2a314c | 2057 | |
a81cc00c BW |
2058 | /* Certain Gen5 chipsets require require idling the GPU before |
2059 | * unmapping anything from the GTT when VT-d is enabled. | |
2060 | */ | |
97d6d7ab | 2061 | static bool needs_idle_maps(struct drm_i915_private *dev_priv) |
a81cc00c | 2062 | { |
a81cc00c BW |
2063 | /* Query intel_iommu to see if we need the workaround. Presumably that |
2064 | * was loaded first. | |
2065 | */ | |
80debff8 | 2066 | return IS_GEN5(dev_priv) && IS_MOBILE(dev_priv) && intel_vtd_active(); |
a81cc00c BW |
2067 | } |
2068 | ||
dc97997a | 2069 | void i915_check_and_clear_faults(struct drm_i915_private *dev_priv) |
828c7908 | 2070 | { |
e2f80391 | 2071 | struct intel_engine_cs *engine; |
3b3f1650 | 2072 | enum intel_engine_id id; |
828c7908 | 2073 | |
dc97997a | 2074 | if (INTEL_INFO(dev_priv)->gen < 6) |
828c7908 BW |
2075 | return; |
2076 | ||
3b3f1650 | 2077 | for_each_engine(engine, dev_priv, id) { |
828c7908 | 2078 | u32 fault_reg; |
e2f80391 | 2079 | fault_reg = I915_READ(RING_FAULT_REG(engine)); |
828c7908 BW |
2080 | if (fault_reg & RING_FAULT_VALID) { |
2081 | DRM_DEBUG_DRIVER("Unexpected fault\n" | |
59a5d290 | 2082 | "\tAddr: 0x%08lx\n" |
828c7908 BW |
2083 | "\tAddress space: %s\n" |
2084 | "\tSource ID: %d\n" | |
2085 | "\tType: %d\n", | |
2086 | fault_reg & PAGE_MASK, | |
2087 | fault_reg & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT", | |
2088 | RING_FAULT_SRCID(fault_reg), | |
2089 | RING_FAULT_FAULT_TYPE(fault_reg)); | |
e2f80391 | 2090 | I915_WRITE(RING_FAULT_REG(engine), |
828c7908 BW |
2091 | fault_reg & ~RING_FAULT_VALID); |
2092 | } | |
2093 | } | |
3b3f1650 AG |
2094 | |
2095 | /* Engine specific init may not have been done till this point. */ | |
2096 | if (dev_priv->engine[RCS]) | |
2097 | POSTING_READ(RING_FAULT_REG(dev_priv->engine[RCS])); | |
828c7908 BW |
2098 | } |
2099 | ||
275a991c | 2100 | void i915_gem_suspend_gtt_mappings(struct drm_i915_private *dev_priv) |
828c7908 | 2101 | { |
72e96d64 | 2102 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
828c7908 BW |
2103 | |
2104 | /* Don't bother messing with faults pre GEN6 as we have little | |
2105 | * documentation supporting that it's a good idea. | |
2106 | */ | |
275a991c | 2107 | if (INTEL_GEN(dev_priv) < 6) |
828c7908 BW |
2108 | return; |
2109 | ||
dc97997a | 2110 | i915_check_and_clear_faults(dev_priv); |
828c7908 | 2111 | |
381b943b | 2112 | ggtt->base.clear_range(&ggtt->base, 0, ggtt->base.total); |
91e56499 | 2113 | |
7c3f86b6 | 2114 | i915_ggtt_invalidate(dev_priv); |
828c7908 BW |
2115 | } |
2116 | ||
03ac84f1 CW |
2117 | int i915_gem_gtt_prepare_pages(struct drm_i915_gem_object *obj, |
2118 | struct sg_table *pages) | |
7c2e6fdf | 2119 | { |
1a292fa5 CW |
2120 | do { |
2121 | if (dma_map_sg(&obj->base.dev->pdev->dev, | |
2122 | pages->sgl, pages->nents, | |
2123 | PCI_DMA_BIDIRECTIONAL)) | |
2124 | return 0; | |
2125 | ||
2126 | /* If the DMA remap fails, one cause can be that we have | |
2127 | * too many objects pinned in a small remapping table, | |
2128 | * such as swiotlb. Incrementally purge all other objects and | |
2129 | * try again - if there are no more pages to remove from | |
2130 | * the DMA remapper, i915_gem_shrink will return 0. | |
2131 | */ | |
2132 | GEM_BUG_ON(obj->mm.pages == pages); | |
2133 | } while (i915_gem_shrink(to_i915(obj->base.dev), | |
2134 | obj->base.size >> PAGE_SHIFT, | |
2135 | I915_SHRINK_BOUND | | |
2136 | I915_SHRINK_UNBOUND | | |
2137 | I915_SHRINK_ACTIVE)); | |
9da3da66 | 2138 | |
03ac84f1 | 2139 | return -ENOSPC; |
7c2e6fdf DV |
2140 | } |
2141 | ||
2c642b07 | 2142 | static void gen8_set_pte(void __iomem *addr, gen8_pte_t pte) |
94ec8f61 | 2143 | { |
94ec8f61 | 2144 | writeq(pte, addr); |
94ec8f61 BW |
2145 | } |
2146 | ||
d6473f56 CW |
2147 | static void gen8_ggtt_insert_page(struct i915_address_space *vm, |
2148 | dma_addr_t addr, | |
75c7b0b8 | 2149 | u64 offset, |
d6473f56 CW |
2150 | enum i915_cache_level level, |
2151 | u32 unused) | |
2152 | { | |
7c3f86b6 | 2153 | struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm); |
d6473f56 | 2154 | gen8_pte_t __iomem *pte = |
7c3f86b6 | 2155 | (gen8_pte_t __iomem *)ggtt->gsm + (offset >> PAGE_SHIFT); |
d6473f56 | 2156 | |
4fb84d99 | 2157 | gen8_set_pte(pte, gen8_pte_encode(addr, level)); |
d6473f56 | 2158 | |
7c3f86b6 | 2159 | ggtt->invalidate(vm->i915); |
d6473f56 CW |
2160 | } |
2161 | ||
94ec8f61 | 2162 | static void gen8_ggtt_insert_entries(struct i915_address_space *vm, |
4a234c5f | 2163 | struct i915_vma *vma, |
75c7b0b8 CW |
2164 | enum i915_cache_level level, |
2165 | u32 unused) | |
94ec8f61 | 2166 | { |
ce7fda2e | 2167 | struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm); |
85d1225e DG |
2168 | struct sgt_iter sgt_iter; |
2169 | gen8_pte_t __iomem *gtt_entries; | |
894ccebe | 2170 | const gen8_pte_t pte_encode = gen8_pte_encode(0, level); |
85d1225e | 2171 | dma_addr_t addr; |
be69459a | 2172 | |
894ccebe | 2173 | gtt_entries = (gen8_pte_t __iomem *)ggtt->gsm; |
4a234c5f MA |
2174 | gtt_entries += vma->node.start >> PAGE_SHIFT; |
2175 | for_each_sgt_dma(addr, sgt_iter, vma->pages) | |
894ccebe | 2176 | gen8_set_pte(gtt_entries++, pte_encode | addr); |
85d1225e | 2177 | |
894ccebe | 2178 | wmb(); |
94ec8f61 | 2179 | |
94ec8f61 BW |
2180 | /* This next bit makes the above posting read even more important. We |
2181 | * want to flush the TLBs only after we're certain all the PTE updates | |
2182 | * have finished. | |
2183 | */ | |
7c3f86b6 | 2184 | ggtt->invalidate(vm->i915); |
94ec8f61 BW |
2185 | } |
2186 | ||
d6473f56 CW |
2187 | static void gen6_ggtt_insert_page(struct i915_address_space *vm, |
2188 | dma_addr_t addr, | |
75c7b0b8 | 2189 | u64 offset, |
d6473f56 CW |
2190 | enum i915_cache_level level, |
2191 | u32 flags) | |
2192 | { | |
7c3f86b6 | 2193 | struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm); |
d6473f56 | 2194 | gen6_pte_t __iomem *pte = |
7c3f86b6 | 2195 | (gen6_pte_t __iomem *)ggtt->gsm + (offset >> PAGE_SHIFT); |
d6473f56 | 2196 | |
4fb84d99 | 2197 | iowrite32(vm->pte_encode(addr, level, flags), pte); |
d6473f56 | 2198 | |
7c3f86b6 | 2199 | ggtt->invalidate(vm->i915); |
d6473f56 CW |
2200 | } |
2201 | ||
e76e9aeb BW |
2202 | /* |
2203 | * Binds an object into the global gtt with the specified cache level. The object | |
2204 | * will be accessible to the GPU via commands whose operands reference offsets | |
2205 | * within the global GTT as well as accessible by the GPU through the GMADR | |
2206 | * mapped BAR (dev_priv->mm.gtt->gtt). | |
2207 | */ | |
853ba5d2 | 2208 | static void gen6_ggtt_insert_entries(struct i915_address_space *vm, |
4a234c5f | 2209 | struct i915_vma *vma, |
75c7b0b8 CW |
2210 | enum i915_cache_level level, |
2211 | u32 flags) | |
e76e9aeb | 2212 | { |
ce7fda2e | 2213 | struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm); |
b31144c0 | 2214 | gen6_pte_t __iomem *entries = (gen6_pte_t __iomem *)ggtt->gsm; |
4a234c5f | 2215 | unsigned int i = vma->node.start >> PAGE_SHIFT; |
b31144c0 | 2216 | struct sgt_iter iter; |
85d1225e | 2217 | dma_addr_t addr; |
4a234c5f | 2218 | for_each_sgt_dma(addr, iter, vma->pages) |
b31144c0 CW |
2219 | iowrite32(vm->pte_encode(addr, level, flags), &entries[i++]); |
2220 | wmb(); | |
0f9b91c7 BW |
2221 | |
2222 | /* This next bit makes the above posting read even more important. We | |
2223 | * want to flush the TLBs only after we're certain all the PTE updates | |
2224 | * have finished. | |
2225 | */ | |
7c3f86b6 | 2226 | ggtt->invalidate(vm->i915); |
e76e9aeb BW |
2227 | } |
2228 | ||
f7770bfd | 2229 | static void nop_clear_range(struct i915_address_space *vm, |
75c7b0b8 | 2230 | u64 start, u64 length) |
f7770bfd CW |
2231 | { |
2232 | } | |
2233 | ||
94ec8f61 | 2234 | static void gen8_ggtt_clear_range(struct i915_address_space *vm, |
75c7b0b8 | 2235 | u64 start, u64 length) |
94ec8f61 | 2236 | { |
ce7fda2e | 2237 | struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm); |
782f1495 BW |
2238 | unsigned first_entry = start >> PAGE_SHIFT; |
2239 | unsigned num_entries = length >> PAGE_SHIFT; | |
894ccebe CW |
2240 | const gen8_pte_t scratch_pte = |
2241 | gen8_pte_encode(vm->scratch_page.daddr, I915_CACHE_LLC); | |
2242 | gen8_pte_t __iomem *gtt_base = | |
72e96d64 JL |
2243 | (gen8_pte_t __iomem *)ggtt->gsm + first_entry; |
2244 | const int max_entries = ggtt_total_entries(ggtt) - first_entry; | |
94ec8f61 BW |
2245 | int i; |
2246 | ||
2247 | if (WARN(num_entries > max_entries, | |
2248 | "First entry = %d; Num entries = %d (max=%d)\n", | |
2249 | first_entry, num_entries, max_entries)) | |
2250 | num_entries = max_entries; | |
2251 | ||
94ec8f61 BW |
2252 | for (i = 0; i < num_entries; i++) |
2253 | gen8_set_pte(>t_base[i], scratch_pte); | |
94ec8f61 BW |
2254 | } |
2255 | ||
0ef34ad6 JB |
2256 | static void bxt_vtd_ggtt_wa(struct i915_address_space *vm) |
2257 | { | |
2258 | struct drm_i915_private *dev_priv = vm->i915; | |
2259 | ||
2260 | /* | |
2261 | * Make sure the internal GAM fifo has been cleared of all GTT | |
2262 | * writes before exiting stop_machine(). This guarantees that | |
2263 | * any aperture accesses waiting to start in another process | |
2264 | * cannot back up behind the GTT writes causing a hang. | |
2265 | * The register can be any arbitrary GAM register. | |
2266 | */ | |
2267 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
2268 | } | |
2269 | ||
2270 | struct insert_page { | |
2271 | struct i915_address_space *vm; | |
2272 | dma_addr_t addr; | |
2273 | u64 offset; | |
2274 | enum i915_cache_level level; | |
2275 | }; | |
2276 | ||
2277 | static int bxt_vtd_ggtt_insert_page__cb(void *_arg) | |
2278 | { | |
2279 | struct insert_page *arg = _arg; | |
2280 | ||
2281 | gen8_ggtt_insert_page(arg->vm, arg->addr, arg->offset, arg->level, 0); | |
2282 | bxt_vtd_ggtt_wa(arg->vm); | |
2283 | ||
2284 | return 0; | |
2285 | } | |
2286 | ||
2287 | static void bxt_vtd_ggtt_insert_page__BKL(struct i915_address_space *vm, | |
2288 | dma_addr_t addr, | |
2289 | u64 offset, | |
2290 | enum i915_cache_level level, | |
2291 | u32 unused) | |
2292 | { | |
2293 | struct insert_page arg = { vm, addr, offset, level }; | |
2294 | ||
2295 | stop_machine(bxt_vtd_ggtt_insert_page__cb, &arg, NULL); | |
2296 | } | |
2297 | ||
2298 | struct insert_entries { | |
2299 | struct i915_address_space *vm; | |
4a234c5f | 2300 | struct i915_vma *vma; |
0ef34ad6 JB |
2301 | enum i915_cache_level level; |
2302 | }; | |
2303 | ||
2304 | static int bxt_vtd_ggtt_insert_entries__cb(void *_arg) | |
2305 | { | |
2306 | struct insert_entries *arg = _arg; | |
2307 | ||
4a234c5f | 2308 | gen8_ggtt_insert_entries(arg->vm, arg->vma, arg->level, 0); |
0ef34ad6 JB |
2309 | bxt_vtd_ggtt_wa(arg->vm); |
2310 | ||
2311 | return 0; | |
2312 | } | |
2313 | ||
2314 | static void bxt_vtd_ggtt_insert_entries__BKL(struct i915_address_space *vm, | |
4a234c5f | 2315 | struct i915_vma *vma, |
0ef34ad6 JB |
2316 | enum i915_cache_level level, |
2317 | u32 unused) | |
2318 | { | |
17369ba0 | 2319 | struct insert_entries arg = { vm, vma, level }; |
0ef34ad6 JB |
2320 | |
2321 | stop_machine(bxt_vtd_ggtt_insert_entries__cb, &arg, NULL); | |
2322 | } | |
2323 | ||
2324 | struct clear_range { | |
2325 | struct i915_address_space *vm; | |
2326 | u64 start; | |
2327 | u64 length; | |
2328 | }; | |
2329 | ||
2330 | static int bxt_vtd_ggtt_clear_range__cb(void *_arg) | |
2331 | { | |
2332 | struct clear_range *arg = _arg; | |
2333 | ||
2334 | gen8_ggtt_clear_range(arg->vm, arg->start, arg->length); | |
2335 | bxt_vtd_ggtt_wa(arg->vm); | |
2336 | ||
2337 | return 0; | |
2338 | } | |
2339 | ||
2340 | static void bxt_vtd_ggtt_clear_range__BKL(struct i915_address_space *vm, | |
2341 | u64 start, | |
2342 | u64 length) | |
2343 | { | |
2344 | struct clear_range arg = { vm, start, length }; | |
2345 | ||
2346 | stop_machine(bxt_vtd_ggtt_clear_range__cb, &arg, NULL); | |
2347 | } | |
2348 | ||
853ba5d2 | 2349 | static void gen6_ggtt_clear_range(struct i915_address_space *vm, |
75c7b0b8 | 2350 | u64 start, u64 length) |
7faf1ab2 | 2351 | { |
ce7fda2e | 2352 | struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm); |
782f1495 BW |
2353 | unsigned first_entry = start >> PAGE_SHIFT; |
2354 | unsigned num_entries = length >> PAGE_SHIFT; | |
07749ef3 | 2355 | gen6_pte_t scratch_pte, __iomem *gtt_base = |
72e96d64 JL |
2356 | (gen6_pte_t __iomem *)ggtt->gsm + first_entry; |
2357 | const int max_entries = ggtt_total_entries(ggtt) - first_entry; | |
7faf1ab2 DV |
2358 | int i; |
2359 | ||
2360 | if (WARN(num_entries > max_entries, | |
2361 | "First entry = %d; Num entries = %d (max=%d)\n", | |
2362 | first_entry, num_entries, max_entries)) | |
2363 | num_entries = max_entries; | |
2364 | ||
8bcdd0f7 | 2365 | scratch_pte = vm->pte_encode(vm->scratch_page.daddr, |
4fb84d99 | 2366 | I915_CACHE_LLC, 0); |
828c7908 | 2367 | |
7faf1ab2 DV |
2368 | for (i = 0; i < num_entries; i++) |
2369 | iowrite32(scratch_pte, >t_base[i]); | |
7faf1ab2 DV |
2370 | } |
2371 | ||
d6473f56 CW |
2372 | static void i915_ggtt_insert_page(struct i915_address_space *vm, |
2373 | dma_addr_t addr, | |
75c7b0b8 | 2374 | u64 offset, |
d6473f56 CW |
2375 | enum i915_cache_level cache_level, |
2376 | u32 unused) | |
2377 | { | |
d6473f56 CW |
2378 | unsigned int flags = (cache_level == I915_CACHE_NONE) ? |
2379 | AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY; | |
d6473f56 CW |
2380 | |
2381 | intel_gtt_insert_page(addr, offset >> PAGE_SHIFT, flags); | |
d6473f56 CW |
2382 | } |
2383 | ||
d369d2d9 | 2384 | static void i915_ggtt_insert_entries(struct i915_address_space *vm, |
4a234c5f | 2385 | struct i915_vma *vma, |
75c7b0b8 CW |
2386 | enum i915_cache_level cache_level, |
2387 | u32 unused) | |
7faf1ab2 DV |
2388 | { |
2389 | unsigned int flags = (cache_level == I915_CACHE_NONE) ? | |
2390 | AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY; | |
2391 | ||
4a234c5f MA |
2392 | intel_gtt_insert_sg_entries(vma->pages, vma->node.start >> PAGE_SHIFT, |
2393 | flags); | |
7faf1ab2 DV |
2394 | } |
2395 | ||
853ba5d2 | 2396 | static void i915_ggtt_clear_range(struct i915_address_space *vm, |
75c7b0b8 | 2397 | u64 start, u64 length) |
7faf1ab2 | 2398 | { |
2eedfc7d | 2399 | intel_gtt_clear_range(start >> PAGE_SHIFT, length >> PAGE_SHIFT); |
7faf1ab2 DV |
2400 | } |
2401 | ||
70b9f6f8 DV |
2402 | static int ggtt_bind_vma(struct i915_vma *vma, |
2403 | enum i915_cache_level cache_level, | |
2404 | u32 flags) | |
0a878716 | 2405 | { |
49d73912 | 2406 | struct drm_i915_private *i915 = vma->vm->i915; |
0a878716 | 2407 | struct drm_i915_gem_object *obj = vma->obj; |
ba7a5741 | 2408 | u32 pte_flags; |
0a878716 | 2409 | |
ba7a5741 CW |
2410 | if (unlikely(!vma->pages)) { |
2411 | int ret = i915_get_ggtt_vma_pages(vma); | |
2412 | if (ret) | |
2413 | return ret; | |
2414 | } | |
0a878716 DV |
2415 | |
2416 | /* Currently applicable only to VLV */ | |
ba7a5741 | 2417 | pte_flags = 0; |
0a878716 DV |
2418 | if (obj->gt_ro) |
2419 | pte_flags |= PTE_READ_ONLY; | |
2420 | ||
9c870d03 | 2421 | intel_runtime_pm_get(i915); |
4a234c5f | 2422 | vma->vm->insert_entries(vma->vm, vma, cache_level, pte_flags); |
9c870d03 | 2423 | intel_runtime_pm_put(i915); |
0a878716 DV |
2424 | |
2425 | /* | |
2426 | * Without aliasing PPGTT there's no difference between | |
2427 | * GLOBAL/LOCAL_BIND, it's all the same ptes. Hence unconditionally | |
2428 | * upgrade to both bound if we bind either to avoid double-binding. | |
2429 | */ | |
3272db53 | 2430 | vma->flags |= I915_VMA_GLOBAL_BIND | I915_VMA_LOCAL_BIND; |
0a878716 DV |
2431 | |
2432 | return 0; | |
2433 | } | |
2434 | ||
cbc4e9e6 CW |
2435 | static void ggtt_unbind_vma(struct i915_vma *vma) |
2436 | { | |
2437 | struct drm_i915_private *i915 = vma->vm->i915; | |
2438 | ||
2439 | intel_runtime_pm_get(i915); | |
2440 | vma->vm->clear_range(vma->vm, vma->node.start, vma->size); | |
2441 | intel_runtime_pm_put(i915); | |
2442 | } | |
2443 | ||
0a878716 DV |
2444 | static int aliasing_gtt_bind_vma(struct i915_vma *vma, |
2445 | enum i915_cache_level cache_level, | |
2446 | u32 flags) | |
d5bd1449 | 2447 | { |
49d73912 | 2448 | struct drm_i915_private *i915 = vma->vm->i915; |
321d178e | 2449 | u32 pte_flags; |
ff685975 | 2450 | int ret; |
70b9f6f8 | 2451 | |
ba7a5741 | 2452 | if (unlikely(!vma->pages)) { |
ff685975 | 2453 | ret = i915_get_ggtt_vma_pages(vma); |
ba7a5741 CW |
2454 | if (ret) |
2455 | return ret; | |
2456 | } | |
7faf1ab2 | 2457 | |
24f3a8cf | 2458 | /* Currently applicable only to VLV */ |
321d178e CW |
2459 | pte_flags = 0; |
2460 | if (vma->obj->gt_ro) | |
f329f5f6 | 2461 | pte_flags |= PTE_READ_ONLY; |
24f3a8cf | 2462 | |
ff685975 CW |
2463 | if (flags & I915_VMA_LOCAL_BIND) { |
2464 | struct i915_hw_ppgtt *appgtt = i915->mm.aliasing_ppgtt; | |
2465 | ||
1f23475c MA |
2466 | if (!(vma->flags & I915_VMA_LOCAL_BIND) && |
2467 | appgtt->base.allocate_va_range) { | |
ff685975 CW |
2468 | ret = appgtt->base.allocate_va_range(&appgtt->base, |
2469 | vma->node.start, | |
d567232c | 2470 | vma->size); |
ff685975 | 2471 | if (ret) |
2f7399af | 2472 | goto err_pages; |
ff685975 CW |
2473 | } |
2474 | ||
4a234c5f MA |
2475 | appgtt->base.insert_entries(&appgtt->base, vma, cache_level, |
2476 | pte_flags); | |
ff685975 CW |
2477 | } |
2478 | ||
3272db53 | 2479 | if (flags & I915_VMA_GLOBAL_BIND) { |
9c870d03 | 2480 | intel_runtime_pm_get(i915); |
4a234c5f | 2481 | vma->vm->insert_entries(vma->vm, vma, cache_level, pte_flags); |
9c870d03 | 2482 | intel_runtime_pm_put(i915); |
6f65e29a | 2483 | } |
d5bd1449 | 2484 | |
70b9f6f8 | 2485 | return 0; |
2f7399af CW |
2486 | |
2487 | err_pages: | |
2488 | if (!(vma->flags & (I915_VMA_GLOBAL_BIND | I915_VMA_LOCAL_BIND))) { | |
2489 | if (vma->pages != vma->obj->mm.pages) { | |
2490 | GEM_BUG_ON(!vma->pages); | |
2491 | sg_free_table(vma->pages); | |
2492 | kfree(vma->pages); | |
2493 | } | |
2494 | vma->pages = NULL; | |
2495 | } | |
2496 | return ret; | |
d5bd1449 CW |
2497 | } |
2498 | ||
cbc4e9e6 | 2499 | static void aliasing_gtt_unbind_vma(struct i915_vma *vma) |
74163907 | 2500 | { |
49d73912 | 2501 | struct drm_i915_private *i915 = vma->vm->i915; |
6f65e29a | 2502 | |
9c870d03 CW |
2503 | if (vma->flags & I915_VMA_GLOBAL_BIND) { |
2504 | intel_runtime_pm_get(i915); | |
cbc4e9e6 | 2505 | vma->vm->clear_range(vma->vm, vma->node.start, vma->size); |
9c870d03 CW |
2506 | intel_runtime_pm_put(i915); |
2507 | } | |
06615ee5 | 2508 | |
cbc4e9e6 CW |
2509 | if (vma->flags & I915_VMA_LOCAL_BIND) { |
2510 | struct i915_address_space *vm = &i915->mm.aliasing_ppgtt->base; | |
2511 | ||
2512 | vm->clear_range(vm, vma->node.start, vma->size); | |
2513 | } | |
74163907 DV |
2514 | } |
2515 | ||
03ac84f1 CW |
2516 | void i915_gem_gtt_finish_pages(struct drm_i915_gem_object *obj, |
2517 | struct sg_table *pages) | |
7c2e6fdf | 2518 | { |
52a05c30 DW |
2519 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
2520 | struct device *kdev = &dev_priv->drm.pdev->dev; | |
307dc25b | 2521 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
5c042287 | 2522 | |
307dc25b | 2523 | if (unlikely(ggtt->do_idle_maps)) { |
228ec87c | 2524 | if (i915_gem_wait_for_idle(dev_priv, 0)) { |
307dc25b CW |
2525 | DRM_ERROR("Failed to wait for idle; VT'd may hang.\n"); |
2526 | /* Wait a bit, in hopes it avoids the hang */ | |
2527 | udelay(10); | |
2528 | } | |
2529 | } | |
5c042287 | 2530 | |
03ac84f1 | 2531 | dma_unmap_sg(kdev, pages->sgl, pages->nents, PCI_DMA_BIDIRECTIONAL); |
7c2e6fdf | 2532 | } |
644ec02b | 2533 | |
45b186f1 | 2534 | static void i915_gtt_color_adjust(const struct drm_mm_node *node, |
42d6ab48 | 2535 | unsigned long color, |
440fd528 TR |
2536 | u64 *start, |
2537 | u64 *end) | |
42d6ab48 | 2538 | { |
a6508ded | 2539 | if (node->allocated && node->color != color) |
f51455d4 | 2540 | *start += I915_GTT_PAGE_SIZE; |
42d6ab48 | 2541 | |
a6508ded CW |
2542 | /* Also leave a space between the unallocated reserved node after the |
2543 | * GTT and any objects within the GTT, i.e. we use the color adjustment | |
2544 | * to insert a guard page to prevent prefetches crossing over the | |
2545 | * GTT boundary. | |
2546 | */ | |
b44f97fd | 2547 | node = list_next_entry(node, node_list); |
a6508ded | 2548 | if (node->color != color) |
f51455d4 | 2549 | *end -= I915_GTT_PAGE_SIZE; |
42d6ab48 | 2550 | } |
fbe5d36e | 2551 | |
6cde9a02 CW |
2552 | int i915_gem_init_aliasing_ppgtt(struct drm_i915_private *i915) |
2553 | { | |
2554 | struct i915_ggtt *ggtt = &i915->ggtt; | |
2555 | struct i915_hw_ppgtt *ppgtt; | |
2556 | int err; | |
2557 | ||
57202f47 | 2558 | ppgtt = i915_ppgtt_create(i915, ERR_PTR(-EPERM), "[alias]"); |
1188bc66 CW |
2559 | if (IS_ERR(ppgtt)) |
2560 | return PTR_ERR(ppgtt); | |
6cde9a02 | 2561 | |
e565ceb0 CW |
2562 | if (WARN_ON(ppgtt->base.total < ggtt->base.total)) { |
2563 | err = -ENODEV; | |
2564 | goto err_ppgtt; | |
2565 | } | |
2566 | ||
6cde9a02 | 2567 | if (ppgtt->base.allocate_va_range) { |
e565ceb0 CW |
2568 | /* Note we only pre-allocate as far as the end of the global |
2569 | * GTT. On 48b / 4-level page-tables, the difference is very, | |
2570 | * very significant! We have to preallocate as GVT/vgpu does | |
2571 | * not like the page directory disappearing. | |
2572 | */ | |
6cde9a02 | 2573 | err = ppgtt->base.allocate_va_range(&ppgtt->base, |
e565ceb0 | 2574 | 0, ggtt->base.total); |
6cde9a02 | 2575 | if (err) |
1188bc66 | 2576 | goto err_ppgtt; |
6cde9a02 CW |
2577 | } |
2578 | ||
6cde9a02 | 2579 | i915->mm.aliasing_ppgtt = ppgtt; |
cbc4e9e6 | 2580 | |
6cde9a02 CW |
2581 | WARN_ON(ggtt->base.bind_vma != ggtt_bind_vma); |
2582 | ggtt->base.bind_vma = aliasing_gtt_bind_vma; | |
2583 | ||
cbc4e9e6 CW |
2584 | WARN_ON(ggtt->base.unbind_vma != ggtt_unbind_vma); |
2585 | ggtt->base.unbind_vma = aliasing_gtt_unbind_vma; | |
2586 | ||
6cde9a02 CW |
2587 | return 0; |
2588 | ||
6cde9a02 | 2589 | err_ppgtt: |
1188bc66 | 2590 | i915_ppgtt_put(ppgtt); |
6cde9a02 CW |
2591 | return err; |
2592 | } | |
2593 | ||
2594 | void i915_gem_fini_aliasing_ppgtt(struct drm_i915_private *i915) | |
2595 | { | |
2596 | struct i915_ggtt *ggtt = &i915->ggtt; | |
2597 | struct i915_hw_ppgtt *ppgtt; | |
2598 | ||
2599 | ppgtt = fetch_and_zero(&i915->mm.aliasing_ppgtt); | |
2600 | if (!ppgtt) | |
2601 | return; | |
2602 | ||
1188bc66 | 2603 | i915_ppgtt_put(ppgtt); |
6cde9a02 CW |
2604 | |
2605 | ggtt->base.bind_vma = ggtt_bind_vma; | |
cbc4e9e6 | 2606 | ggtt->base.unbind_vma = ggtt_unbind_vma; |
6cde9a02 CW |
2607 | } |
2608 | ||
f6b9d5ca | 2609 | int i915_gem_init_ggtt(struct drm_i915_private *dev_priv) |
644ec02b | 2610 | { |
e78891ca BW |
2611 | /* Let GEM Manage all of the aperture. |
2612 | * | |
2613 | * However, leave one page at the end still bound to the scratch page. | |
2614 | * There are a number of places where the hardware apparently prefetches | |
2615 | * past the end of the object, and we've seen multiple hangs with the | |
2616 | * GPU head pointer stuck in a batchbuffer bound at the last page of the | |
2617 | * aperture. One page should be enough to keep any prefetching inside | |
2618 | * of the aperture. | |
2619 | */ | |
72e96d64 | 2620 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
ed2f3452 | 2621 | unsigned long hole_start, hole_end; |
f6b9d5ca | 2622 | struct drm_mm_node *entry; |
fa76da34 | 2623 | int ret; |
644ec02b | 2624 | |
b02d22a3 ZW |
2625 | ret = intel_vgt_balloon(dev_priv); |
2626 | if (ret) | |
2627 | return ret; | |
5dda8fa3 | 2628 | |
95374d75 | 2629 | /* Reserve a mappable slot for our lockless error capture */ |
4e64e553 CW |
2630 | ret = drm_mm_insert_node_in_range(&ggtt->base.mm, &ggtt->error_capture, |
2631 | PAGE_SIZE, 0, I915_COLOR_UNEVICTABLE, | |
2632 | 0, ggtt->mappable_end, | |
2633 | DRM_MM_INSERT_LOW); | |
95374d75 CW |
2634 | if (ret) |
2635 | return ret; | |
2636 | ||
ed2f3452 | 2637 | /* Clear any non-preallocated blocks */ |
72e96d64 | 2638 | drm_mm_for_each_hole(entry, &ggtt->base.mm, hole_start, hole_end) { |
ed2f3452 CW |
2639 | DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n", |
2640 | hole_start, hole_end); | |
72e96d64 | 2641 | ggtt->base.clear_range(&ggtt->base, hole_start, |
4fb84d99 | 2642 | hole_end - hole_start); |
ed2f3452 CW |
2643 | } |
2644 | ||
2645 | /* And finally clear the reserved guard page */ | |
f6b9d5ca | 2646 | ggtt->base.clear_range(&ggtt->base, |
4fb84d99 | 2647 | ggtt->base.total - PAGE_SIZE, PAGE_SIZE); |
6c5566a8 | 2648 | |
97d6d7ab | 2649 | if (USES_PPGTT(dev_priv) && !USES_FULL_PPGTT(dev_priv)) { |
6cde9a02 | 2650 | ret = i915_gem_init_aliasing_ppgtt(dev_priv); |
95374d75 | 2651 | if (ret) |
6cde9a02 | 2652 | goto err; |
fa76da34 DV |
2653 | } |
2654 | ||
6c5566a8 | 2655 | return 0; |
95374d75 | 2656 | |
95374d75 CW |
2657 | err: |
2658 | drm_mm_remove_node(&ggtt->error_capture); | |
2659 | return ret; | |
e76e9aeb BW |
2660 | } |
2661 | ||
d85489d3 JL |
2662 | /** |
2663 | * i915_ggtt_cleanup_hw - Clean up GGTT hardware initialization | |
97d6d7ab | 2664 | * @dev_priv: i915 device |
d85489d3 | 2665 | */ |
97d6d7ab | 2666 | void i915_ggtt_cleanup_hw(struct drm_i915_private *dev_priv) |
90d0a0e8 | 2667 | { |
72e96d64 | 2668 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
94d4a2a9 | 2669 | struct i915_vma *vma, *vn; |
66df1014 | 2670 | struct pagevec *pvec; |
94d4a2a9 CW |
2671 | |
2672 | ggtt->base.closed = true; | |
2673 | ||
2674 | mutex_lock(&dev_priv->drm.struct_mutex); | |
2675 | WARN_ON(!list_empty(&ggtt->base.active_list)); | |
2676 | list_for_each_entry_safe(vma, vn, &ggtt->base.inactive_list, vm_link) | |
2677 | WARN_ON(i915_vma_unbind(vma)); | |
2678 | mutex_unlock(&dev_priv->drm.struct_mutex); | |
90d0a0e8 | 2679 | |
97d6d7ab | 2680 | i915_gem_cleanup_stolen(&dev_priv->drm); |
a4eba47b | 2681 | |
1188bc66 CW |
2682 | mutex_lock(&dev_priv->drm.struct_mutex); |
2683 | i915_gem_fini_aliasing_ppgtt(dev_priv); | |
2684 | ||
95374d75 CW |
2685 | if (drm_mm_node_allocated(&ggtt->error_capture)) |
2686 | drm_mm_remove_node(&ggtt->error_capture); | |
2687 | ||
72e96d64 | 2688 | if (drm_mm_initialized(&ggtt->base.mm)) { |
b02d22a3 | 2689 | intel_vgt_deballoon(dev_priv); |
ed9724dd | 2690 | i915_address_space_fini(&ggtt->base); |
90d0a0e8 DV |
2691 | } |
2692 | ||
72e96d64 | 2693 | ggtt->base.cleanup(&ggtt->base); |
66df1014 CW |
2694 | |
2695 | pvec = &dev_priv->mm.wc_stash; | |
2696 | if (pvec->nr) { | |
2697 | set_pages_array_wb(pvec->pages, pvec->nr); | |
2698 | __pagevec_release(pvec); | |
2699 | } | |
2700 | ||
1188bc66 | 2701 | mutex_unlock(&dev_priv->drm.struct_mutex); |
f6b9d5ca CW |
2702 | |
2703 | arch_phys_wc_del(ggtt->mtrr); | |
f7bbe788 | 2704 | io_mapping_fini(&ggtt->mappable); |
90d0a0e8 | 2705 | } |
70e32544 | 2706 | |
2c642b07 | 2707 | static unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl) |
e76e9aeb BW |
2708 | { |
2709 | snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT; | |
2710 | snb_gmch_ctl &= SNB_GMCH_GGMS_MASK; | |
2711 | return snb_gmch_ctl << 20; | |
2712 | } | |
2713 | ||
2c642b07 | 2714 | static unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl) |
9459d252 BW |
2715 | { |
2716 | bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT; | |
2717 | bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK; | |
2718 | if (bdw_gmch_ctl) | |
2719 | bdw_gmch_ctl = 1 << bdw_gmch_ctl; | |
562d55d9 BW |
2720 | |
2721 | #ifdef CONFIG_X86_32 | |
2722 | /* Limit 32b platforms to a 2GB GGTT: 4 << 20 / pte size * PAGE_SIZE */ | |
2723 | if (bdw_gmch_ctl > 4) | |
2724 | bdw_gmch_ctl = 4; | |
2725 | #endif | |
2726 | ||
9459d252 BW |
2727 | return bdw_gmch_ctl << 20; |
2728 | } | |
2729 | ||
2c642b07 | 2730 | static unsigned int chv_get_total_gtt_size(u16 gmch_ctrl) |
d7f25f23 DL |
2731 | { |
2732 | gmch_ctrl >>= SNB_GMCH_GGMS_SHIFT; | |
2733 | gmch_ctrl &= SNB_GMCH_GGMS_MASK; | |
2734 | ||
2735 | if (gmch_ctrl) | |
2736 | return 1 << (20 + gmch_ctrl); | |
2737 | ||
2738 | return 0; | |
2739 | } | |
2740 | ||
2c642b07 | 2741 | static size_t gen6_get_stolen_size(u16 snb_gmch_ctl) |
e76e9aeb BW |
2742 | { |
2743 | snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT; | |
2744 | snb_gmch_ctl &= SNB_GMCH_GMS_MASK; | |
a92d1a91 | 2745 | return (size_t)snb_gmch_ctl << 25; /* 32 MB units */ |
e76e9aeb BW |
2746 | } |
2747 | ||
2c642b07 | 2748 | static size_t gen8_get_stolen_size(u16 bdw_gmch_ctl) |
9459d252 BW |
2749 | { |
2750 | bdw_gmch_ctl >>= BDW_GMCH_GMS_SHIFT; | |
2751 | bdw_gmch_ctl &= BDW_GMCH_GMS_MASK; | |
a92d1a91 | 2752 | return (size_t)bdw_gmch_ctl << 25; /* 32 MB units */ |
9459d252 BW |
2753 | } |
2754 | ||
d7f25f23 DL |
2755 | static size_t chv_get_stolen_size(u16 gmch_ctrl) |
2756 | { | |
2757 | gmch_ctrl >>= SNB_GMCH_GMS_SHIFT; | |
2758 | gmch_ctrl &= SNB_GMCH_GMS_MASK; | |
2759 | ||
2760 | /* | |
2761 | * 0x0 to 0x10: 32MB increments starting at 0MB | |
2762 | * 0x11 to 0x16: 4MB increments starting at 8MB | |
2763 | * 0x17 to 0x1d: 4MB increments start at 36MB | |
2764 | */ | |
2765 | if (gmch_ctrl < 0x11) | |
a92d1a91 | 2766 | return (size_t)gmch_ctrl << 25; |
d7f25f23 | 2767 | else if (gmch_ctrl < 0x17) |
a92d1a91 | 2768 | return (size_t)(gmch_ctrl - 0x11 + 2) << 22; |
d7f25f23 | 2769 | else |
a92d1a91 | 2770 | return (size_t)(gmch_ctrl - 0x17 + 9) << 22; |
d7f25f23 DL |
2771 | } |
2772 | ||
66375014 DL |
2773 | static size_t gen9_get_stolen_size(u16 gen9_gmch_ctl) |
2774 | { | |
2775 | gen9_gmch_ctl >>= BDW_GMCH_GMS_SHIFT; | |
2776 | gen9_gmch_ctl &= BDW_GMCH_GMS_MASK; | |
2777 | ||
2778 | if (gen9_gmch_ctl < 0xf0) | |
a92d1a91 | 2779 | return (size_t)gen9_gmch_ctl << 25; /* 32 MB units */ |
66375014 DL |
2780 | else |
2781 | /* 4MB increments starting at 0xf0 for 4MB */ | |
a92d1a91 | 2782 | return (size_t)(gen9_gmch_ctl - 0xf0 + 1) << 22; |
66375014 DL |
2783 | } |
2784 | ||
34c998b4 | 2785 | static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size) |
63340133 | 2786 | { |
49d73912 CW |
2787 | struct drm_i915_private *dev_priv = ggtt->base.i915; |
2788 | struct pci_dev *pdev = dev_priv->drm.pdev; | |
34c998b4 | 2789 | phys_addr_t phys_addr; |
8bcdd0f7 | 2790 | int ret; |
63340133 BW |
2791 | |
2792 | /* For Modern GENs the PTEs and register space are split in the BAR */ | |
34c998b4 | 2793 | phys_addr = pci_resource_start(pdev, 0) + pci_resource_len(pdev, 0) / 2; |
63340133 | 2794 | |
2a073f89 | 2795 | /* |
385db982 RV |
2796 | * On BXT+/CNL+ writes larger than 64 bit to the GTT pagetable range |
2797 | * will be dropped. For WC mappings in general we have 64 byte burst | |
2798 | * writes when the WC buffer is flushed, so we can't use it, but have to | |
2a073f89 ID |
2799 | * resort to an uncached mapping. The WC issue is easily caught by the |
2800 | * readback check when writing GTT PTE entries. | |
2801 | */ | |
385db982 | 2802 | if (IS_GEN9_LP(dev_priv) || INTEL_GEN(dev_priv) >= 10) |
34c998b4 | 2803 | ggtt->gsm = ioremap_nocache(phys_addr, size); |
2a073f89 | 2804 | else |
34c998b4 | 2805 | ggtt->gsm = ioremap_wc(phys_addr, size); |
72e96d64 | 2806 | if (!ggtt->gsm) { |
34c998b4 | 2807 | DRM_ERROR("Failed to map the ggtt page table\n"); |
63340133 BW |
2808 | return -ENOMEM; |
2809 | } | |
2810 | ||
8448661d | 2811 | ret = setup_scratch_page(&ggtt->base, GFP_DMA32); |
8bcdd0f7 | 2812 | if (ret) { |
63340133 BW |
2813 | DRM_ERROR("Scratch setup failed\n"); |
2814 | /* iounmap will also get called at remove, but meh */ | |
72e96d64 | 2815 | iounmap(ggtt->gsm); |
8bcdd0f7 | 2816 | return ret; |
63340133 BW |
2817 | } |
2818 | ||
4ad2af1e | 2819 | return 0; |
63340133 BW |
2820 | } |
2821 | ||
4e34935f RV |
2822 | static void cnl_setup_private_ppat(struct drm_i915_private *dev_priv) |
2823 | { | |
2824 | /* XXX: spec is unclear if this is still needed for CNL+ */ | |
2825 | if (!USES_PPGTT(dev_priv)) { | |
2826 | I915_WRITE(GEN10_PAT_INDEX(0), GEN8_PPAT_UC); | |
2827 | return; | |
2828 | } | |
2829 | ||
2830 | I915_WRITE(GEN10_PAT_INDEX(0), GEN8_PPAT_WB | GEN8_PPAT_LLC); | |
2831 | I915_WRITE(GEN10_PAT_INDEX(1), GEN8_PPAT_WC | GEN8_PPAT_LLCELLC); | |
2832 | I915_WRITE(GEN10_PAT_INDEX(2), GEN8_PPAT_WT | GEN8_PPAT_LLCELLC); | |
2833 | I915_WRITE(GEN10_PAT_INDEX(3), GEN8_PPAT_UC); | |
6e31cdcf ZW |
2834 | I915_WRITE(GEN10_PAT_INDEX(4), GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)); |
2835 | I915_WRITE(GEN10_PAT_INDEX(5), GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)); | |
2836 | I915_WRITE(GEN10_PAT_INDEX(6), GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)); | |
2837 | I915_WRITE(GEN10_PAT_INDEX(7), GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3)); | |
4e34935f RV |
2838 | } |
2839 | ||
fbe5d36e BW |
2840 | /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability |
2841 | * bits. When using advanced contexts each context stores its own PAT, but | |
2842 | * writing this data shouldn't be harmful even in those cases. */ | |
ee0ce478 | 2843 | static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv) |
fbe5d36e | 2844 | { |
75c7b0b8 | 2845 | u64 pat; |
fbe5d36e BW |
2846 | |
2847 | pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC) | /* for normal objects, no eLLC */ | |
2848 | GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something pointing to ptes? */ | |
2849 | GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC) | /* for scanout with eLLC */ | |
2850 | GEN8_PPAT(3, GEN8_PPAT_UC) | /* Uncached objects, mostly for scanout */ | |
2851 | GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) | | |
2852 | GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) | | |
2853 | GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) | | |
2854 | GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3)); | |
2855 | ||
2d1fe073 | 2856 | if (!USES_PPGTT(dev_priv)) |
d6a8b72e RV |
2857 | /* Spec: "For GGTT, there is NO pat_sel[2:0] from the entry, |
2858 | * so RTL will always use the value corresponding to | |
2859 | * pat_sel = 000". | |
2860 | * So let's disable cache for GGTT to avoid screen corruptions. | |
2861 | * MOCS still can be used though. | |
2862 | * - System agent ggtt writes (i.e. cpu gtt mmaps) already work | |
2863 | * before this patch, i.e. the same uncached + snooping access | |
2864 | * like on gen6/7 seems to be in effect. | |
2865 | * - So this just fixes blitter/render access. Again it looks | |
2866 | * like it's not just uncached access, but uncached + snooping. | |
2867 | * So we can still hold onto all our assumptions wrt cpu | |
2868 | * clflushing on LLC machines. | |
2869 | */ | |
2870 | pat = GEN8_PPAT(0, GEN8_PPAT_UC); | |
2871 | ||
fbe5d36e BW |
2872 | /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b |
2873 | * write would work. */ | |
7e435ad2 VS |
2874 | I915_WRITE(GEN8_PRIVATE_PAT_LO, pat); |
2875 | I915_WRITE(GEN8_PRIVATE_PAT_HI, pat >> 32); | |
fbe5d36e BW |
2876 | } |
2877 | ||
ee0ce478 VS |
2878 | static void chv_setup_private_ppat(struct drm_i915_private *dev_priv) |
2879 | { | |
75c7b0b8 | 2880 | u64 pat; |
ee0ce478 VS |
2881 | |
2882 | /* | |
2883 | * Map WB on BDW to snooped on CHV. | |
2884 | * | |
2885 | * Only the snoop bit has meaning for CHV, the rest is | |
2886 | * ignored. | |
2887 | * | |
cf3d262e VS |
2888 | * The hardware will never snoop for certain types of accesses: |
2889 | * - CPU GTT (GMADR->GGTT->no snoop->memory) | |
2890 | * - PPGTT page tables | |
2891 | * - some other special cycles | |
2892 | * | |
2893 | * As with BDW, we also need to consider the following for GT accesses: | |
2894 | * "For GGTT, there is NO pat_sel[2:0] from the entry, | |
2895 | * so RTL will always use the value corresponding to | |
2896 | * pat_sel = 000". | |
2897 | * Which means we must set the snoop bit in PAT entry 0 | |
2898 | * in order to keep the global status page working. | |
ee0ce478 VS |
2899 | */ |
2900 | pat = GEN8_PPAT(0, CHV_PPAT_SNOOP) | | |
2901 | GEN8_PPAT(1, 0) | | |
2902 | GEN8_PPAT(2, 0) | | |
2903 | GEN8_PPAT(3, 0) | | |
2904 | GEN8_PPAT(4, CHV_PPAT_SNOOP) | | |
2905 | GEN8_PPAT(5, CHV_PPAT_SNOOP) | | |
2906 | GEN8_PPAT(6, CHV_PPAT_SNOOP) | | |
2907 | GEN8_PPAT(7, CHV_PPAT_SNOOP); | |
2908 | ||
7e435ad2 VS |
2909 | I915_WRITE(GEN8_PRIVATE_PAT_LO, pat); |
2910 | I915_WRITE(GEN8_PRIVATE_PAT_HI, pat >> 32); | |
ee0ce478 VS |
2911 | } |
2912 | ||
34c998b4 CW |
2913 | static void gen6_gmch_remove(struct i915_address_space *vm) |
2914 | { | |
2915 | struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm); | |
2916 | ||
2917 | iounmap(ggtt->gsm); | |
8448661d | 2918 | cleanup_scratch_page(vm); |
34c998b4 CW |
2919 | } |
2920 | ||
d507d735 | 2921 | static int gen8_gmch_probe(struct i915_ggtt *ggtt) |
63340133 | 2922 | { |
49d73912 | 2923 | struct drm_i915_private *dev_priv = ggtt->base.i915; |
97d6d7ab | 2924 | struct pci_dev *pdev = dev_priv->drm.pdev; |
34c998b4 | 2925 | unsigned int size; |
63340133 | 2926 | u16 snb_gmch_ctl; |
4519290a | 2927 | int err; |
63340133 BW |
2928 | |
2929 | /* TODO: We're not aware of mappable constraints on gen8 yet */ | |
97d6d7ab CW |
2930 | ggtt->mappable_base = pci_resource_start(pdev, 2); |
2931 | ggtt->mappable_end = pci_resource_len(pdev, 2); | |
63340133 | 2932 | |
4519290a ID |
2933 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(39)); |
2934 | if (!err) | |
2935 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(39)); | |
2936 | if (err) | |
2937 | DRM_ERROR("Can't set DMA mask/consistent mask (%d)\n", err); | |
63340133 | 2938 | |
97d6d7ab | 2939 | pci_read_config_word(pdev, SNB_GMCH_CTRL, &snb_gmch_ctl); |
63340133 | 2940 | |
97d6d7ab | 2941 | if (INTEL_GEN(dev_priv) >= 9) { |
d507d735 | 2942 | ggtt->stolen_size = gen9_get_stolen_size(snb_gmch_ctl); |
34c998b4 | 2943 | size = gen8_get_total_gtt_size(snb_gmch_ctl); |
97d6d7ab | 2944 | } else if (IS_CHERRYVIEW(dev_priv)) { |
d507d735 | 2945 | ggtt->stolen_size = chv_get_stolen_size(snb_gmch_ctl); |
34c998b4 | 2946 | size = chv_get_total_gtt_size(snb_gmch_ctl); |
d7f25f23 | 2947 | } else { |
d507d735 | 2948 | ggtt->stolen_size = gen8_get_stolen_size(snb_gmch_ctl); |
34c998b4 | 2949 | size = gen8_get_total_gtt_size(snb_gmch_ctl); |
d7f25f23 | 2950 | } |
63340133 | 2951 | |
34c998b4 | 2952 | ggtt->base.total = (size / sizeof(gen8_pte_t)) << PAGE_SHIFT; |
63340133 | 2953 | |
4e34935f RV |
2954 | if (INTEL_GEN(dev_priv) >= 10) |
2955 | cnl_setup_private_ppat(dev_priv); | |
2956 | else if (IS_CHERRYVIEW(dev_priv) || IS_GEN9_LP(dev_priv)) | |
ee0ce478 VS |
2957 | chv_setup_private_ppat(dev_priv); |
2958 | else | |
2959 | bdw_setup_private_ppat(dev_priv); | |
fbe5d36e | 2960 | |
34c998b4 | 2961 | ggtt->base.cleanup = gen6_gmch_remove; |
d507d735 JL |
2962 | ggtt->base.bind_vma = ggtt_bind_vma; |
2963 | ggtt->base.unbind_vma = ggtt_unbind_vma; | |
d6473f56 | 2964 | ggtt->base.insert_page = gen8_ggtt_insert_page; |
f7770bfd | 2965 | ggtt->base.clear_range = nop_clear_range; |
48f112fe | 2966 | if (!USES_FULL_PPGTT(dev_priv) || intel_scanout_needs_vtd_wa(dev_priv)) |
f7770bfd CW |
2967 | ggtt->base.clear_range = gen8_ggtt_clear_range; |
2968 | ||
2969 | ggtt->base.insert_entries = gen8_ggtt_insert_entries; | |
f7770bfd | 2970 | |
0ef34ad6 JB |
2971 | /* Serialize GTT updates with aperture access on BXT if VT-d is on. */ |
2972 | if (intel_ggtt_update_needs_vtd_wa(dev_priv)) { | |
2973 | ggtt->base.insert_entries = bxt_vtd_ggtt_insert_entries__BKL; | |
2974 | ggtt->base.insert_page = bxt_vtd_ggtt_insert_page__BKL; | |
2975 | if (ggtt->base.clear_range != nop_clear_range) | |
2976 | ggtt->base.clear_range = bxt_vtd_ggtt_clear_range__BKL; | |
2977 | } | |
2978 | ||
7c3f86b6 CW |
2979 | ggtt->invalidate = gen6_ggtt_invalidate; |
2980 | ||
34c998b4 | 2981 | return ggtt_probe_common(ggtt, size); |
63340133 BW |
2982 | } |
2983 | ||
d507d735 | 2984 | static int gen6_gmch_probe(struct i915_ggtt *ggtt) |
e76e9aeb | 2985 | { |
49d73912 | 2986 | struct drm_i915_private *dev_priv = ggtt->base.i915; |
97d6d7ab | 2987 | struct pci_dev *pdev = dev_priv->drm.pdev; |
34c998b4 | 2988 | unsigned int size; |
e76e9aeb | 2989 | u16 snb_gmch_ctl; |
4519290a | 2990 | int err; |
e76e9aeb | 2991 | |
97d6d7ab CW |
2992 | ggtt->mappable_base = pci_resource_start(pdev, 2); |
2993 | ggtt->mappable_end = pci_resource_len(pdev, 2); | |
41907ddc | 2994 | |
baa09f5f BW |
2995 | /* 64/512MB is the current min/max we actually know of, but this is just |
2996 | * a coarse sanity check. | |
e76e9aeb | 2997 | */ |
34c998b4 | 2998 | if (ggtt->mappable_end < (64<<20) || ggtt->mappable_end > (512<<20)) { |
d507d735 | 2999 | DRM_ERROR("Unknown GMADR size (%llx)\n", ggtt->mappable_end); |
baa09f5f | 3000 | return -ENXIO; |
e76e9aeb BW |
3001 | } |
3002 | ||
4519290a ID |
3003 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(40)); |
3004 | if (!err) | |
3005 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(40)); | |
3006 | if (err) | |
3007 | DRM_ERROR("Can't set DMA mask/consistent mask (%d)\n", err); | |
97d6d7ab | 3008 | pci_read_config_word(pdev, SNB_GMCH_CTRL, &snb_gmch_ctl); |
e76e9aeb | 3009 | |
d507d735 | 3010 | ggtt->stolen_size = gen6_get_stolen_size(snb_gmch_ctl); |
e76e9aeb | 3011 | |
34c998b4 CW |
3012 | size = gen6_get_total_gtt_size(snb_gmch_ctl); |
3013 | ggtt->base.total = (size / sizeof(gen6_pte_t)) << PAGE_SHIFT; | |
e76e9aeb | 3014 | |
d507d735 | 3015 | ggtt->base.clear_range = gen6_ggtt_clear_range; |
d6473f56 | 3016 | ggtt->base.insert_page = gen6_ggtt_insert_page; |
d507d735 JL |
3017 | ggtt->base.insert_entries = gen6_ggtt_insert_entries; |
3018 | ggtt->base.bind_vma = ggtt_bind_vma; | |
3019 | ggtt->base.unbind_vma = ggtt_unbind_vma; | |
34c998b4 CW |
3020 | ggtt->base.cleanup = gen6_gmch_remove; |
3021 | ||
7c3f86b6 CW |
3022 | ggtt->invalidate = gen6_ggtt_invalidate; |
3023 | ||
34c998b4 CW |
3024 | if (HAS_EDRAM(dev_priv)) |
3025 | ggtt->base.pte_encode = iris_pte_encode; | |
3026 | else if (IS_HASWELL(dev_priv)) | |
3027 | ggtt->base.pte_encode = hsw_pte_encode; | |
3028 | else if (IS_VALLEYVIEW(dev_priv)) | |
3029 | ggtt->base.pte_encode = byt_pte_encode; | |
3030 | else if (INTEL_GEN(dev_priv) >= 7) | |
3031 | ggtt->base.pte_encode = ivb_pte_encode; | |
3032 | else | |
3033 | ggtt->base.pte_encode = snb_pte_encode; | |
7faf1ab2 | 3034 | |
34c998b4 | 3035 | return ggtt_probe_common(ggtt, size); |
e76e9aeb BW |
3036 | } |
3037 | ||
34c998b4 | 3038 | static void i915_gmch_remove(struct i915_address_space *vm) |
e76e9aeb | 3039 | { |
34c998b4 | 3040 | intel_gmch_remove(); |
644ec02b | 3041 | } |
baa09f5f | 3042 | |
d507d735 | 3043 | static int i915_gmch_probe(struct i915_ggtt *ggtt) |
baa09f5f | 3044 | { |
49d73912 | 3045 | struct drm_i915_private *dev_priv = ggtt->base.i915; |
baa09f5f BW |
3046 | int ret; |
3047 | ||
91c8a326 | 3048 | ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->drm.pdev, NULL); |
baa09f5f BW |
3049 | if (!ret) { |
3050 | DRM_ERROR("failed to set up gmch\n"); | |
3051 | return -EIO; | |
3052 | } | |
3053 | ||
edd1f2fe CW |
3054 | intel_gtt_get(&ggtt->base.total, |
3055 | &ggtt->stolen_size, | |
3056 | &ggtt->mappable_base, | |
3057 | &ggtt->mappable_end); | |
baa09f5f | 3058 | |
97d6d7ab | 3059 | ggtt->do_idle_maps = needs_idle_maps(dev_priv); |
d6473f56 | 3060 | ggtt->base.insert_page = i915_ggtt_insert_page; |
d507d735 JL |
3061 | ggtt->base.insert_entries = i915_ggtt_insert_entries; |
3062 | ggtt->base.clear_range = i915_ggtt_clear_range; | |
3063 | ggtt->base.bind_vma = ggtt_bind_vma; | |
3064 | ggtt->base.unbind_vma = ggtt_unbind_vma; | |
34c998b4 | 3065 | ggtt->base.cleanup = i915_gmch_remove; |
baa09f5f | 3066 | |
7c3f86b6 CW |
3067 | ggtt->invalidate = gmch_ggtt_invalidate; |
3068 | ||
d507d735 | 3069 | if (unlikely(ggtt->do_idle_maps)) |
c0a7f818 CW |
3070 | DRM_INFO("applying Ironlake quirks for intel_iommu\n"); |
3071 | ||
baa09f5f BW |
3072 | return 0; |
3073 | } | |
3074 | ||
d85489d3 | 3075 | /** |
0088e522 | 3076 | * i915_ggtt_probe_hw - Probe GGTT hardware location |
97d6d7ab | 3077 | * @dev_priv: i915 device |
d85489d3 | 3078 | */ |
97d6d7ab | 3079 | int i915_ggtt_probe_hw(struct drm_i915_private *dev_priv) |
baa09f5f | 3080 | { |
62106b4f | 3081 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
baa09f5f BW |
3082 | int ret; |
3083 | ||
49d73912 | 3084 | ggtt->base.i915 = dev_priv; |
8448661d | 3085 | ggtt->base.dma = &dev_priv->drm.pdev->dev; |
c114f76a | 3086 | |
34c998b4 CW |
3087 | if (INTEL_GEN(dev_priv) <= 5) |
3088 | ret = i915_gmch_probe(ggtt); | |
3089 | else if (INTEL_GEN(dev_priv) < 8) | |
3090 | ret = gen6_gmch_probe(ggtt); | |
3091 | else | |
3092 | ret = gen8_gmch_probe(ggtt); | |
a54c0c27 | 3093 | if (ret) |
baa09f5f | 3094 | return ret; |
baa09f5f | 3095 | |
db9309a5 CW |
3096 | /* Trim the GGTT to fit the GuC mappable upper range (when enabled). |
3097 | * This is easier than doing range restriction on the fly, as we | |
3098 | * currently don't have any bits spare to pass in this upper | |
3099 | * restriction! | |
3100 | */ | |
3101 | if (HAS_GUC(dev_priv) && i915.enable_guc_loading) { | |
3102 | ggtt->base.total = min_t(u64, ggtt->base.total, GUC_GGTT_TOP); | |
3103 | ggtt->mappable_end = min(ggtt->mappable_end, ggtt->base.total); | |
3104 | } | |
3105 | ||
c890e2d5 CW |
3106 | if ((ggtt->base.total - 1) >> 32) { |
3107 | DRM_ERROR("We never expected a Global GTT with more than 32bits" | |
f6b9d5ca | 3108 | " of address space! Found %lldM!\n", |
c890e2d5 CW |
3109 | ggtt->base.total >> 20); |
3110 | ggtt->base.total = 1ULL << 32; | |
3111 | ggtt->mappable_end = min(ggtt->mappable_end, ggtt->base.total); | |
3112 | } | |
3113 | ||
f6b9d5ca CW |
3114 | if (ggtt->mappable_end > ggtt->base.total) { |
3115 | DRM_ERROR("mappable aperture extends past end of GGTT," | |
3116 | " aperture=%llx, total=%llx\n", | |
3117 | ggtt->mappable_end, ggtt->base.total); | |
3118 | ggtt->mappable_end = ggtt->base.total; | |
3119 | } | |
3120 | ||
baa09f5f | 3121 | /* GMADR is the PCI mmio aperture into the global GTT. */ |
c44ef60e | 3122 | DRM_INFO("Memory usable by graphics device = %lluM\n", |
62106b4f JL |
3123 | ggtt->base.total >> 20); |
3124 | DRM_DEBUG_DRIVER("GMADR size = %lldM\n", ggtt->mappable_end >> 20); | |
edd1f2fe | 3125 | DRM_DEBUG_DRIVER("GTT stolen size = %uM\n", ggtt->stolen_size >> 20); |
80debff8 | 3126 | if (intel_vtd_active()) |
5db6c735 | 3127 | DRM_INFO("VT-d active for gfx access\n"); |
baa09f5f BW |
3128 | |
3129 | return 0; | |
0088e522 CW |
3130 | } |
3131 | ||
3132 | /** | |
3133 | * i915_ggtt_init_hw - Initialize GGTT hardware | |
97d6d7ab | 3134 | * @dev_priv: i915 device |
0088e522 | 3135 | */ |
97d6d7ab | 3136 | int i915_ggtt_init_hw(struct drm_i915_private *dev_priv) |
0088e522 | 3137 | { |
0088e522 CW |
3138 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
3139 | int ret; | |
3140 | ||
f6b9d5ca CW |
3141 | INIT_LIST_HEAD(&dev_priv->vm_list); |
3142 | ||
a6508ded CW |
3143 | /* Note that we use page colouring to enforce a guard page at the |
3144 | * end of the address space. This is required as the CS may prefetch | |
3145 | * beyond the end of the batch buffer, across the page boundary, | |
3146 | * and beyond the end of the GTT if we do not provide a guard. | |
f6b9d5ca | 3147 | */ |
80b204bc | 3148 | mutex_lock(&dev_priv->drm.struct_mutex); |
80b204bc | 3149 | i915_address_space_init(&ggtt->base, dev_priv, "[global]"); |
a6508ded | 3150 | if (!HAS_LLC(dev_priv) && !USES_PPGTT(dev_priv)) |
f6b9d5ca | 3151 | ggtt->base.mm.color_adjust = i915_gtt_color_adjust; |
80b204bc | 3152 | mutex_unlock(&dev_priv->drm.struct_mutex); |
f6b9d5ca | 3153 | |
f7bbe788 CW |
3154 | if (!io_mapping_init_wc(&dev_priv->ggtt.mappable, |
3155 | dev_priv->ggtt.mappable_base, | |
3156 | dev_priv->ggtt.mappable_end)) { | |
f6b9d5ca CW |
3157 | ret = -EIO; |
3158 | goto out_gtt_cleanup; | |
3159 | } | |
3160 | ||
3161 | ggtt->mtrr = arch_phys_wc_add(ggtt->mappable_base, ggtt->mappable_end); | |
3162 | ||
0088e522 CW |
3163 | /* |
3164 | * Initialise stolen early so that we may reserve preallocated | |
3165 | * objects for the BIOS to KMS transition. | |
3166 | */ | |
7ace3d30 | 3167 | ret = i915_gem_init_stolen(dev_priv); |
0088e522 CW |
3168 | if (ret) |
3169 | goto out_gtt_cleanup; | |
3170 | ||
3171 | return 0; | |
a4eba47b ID |
3172 | |
3173 | out_gtt_cleanup: | |
72e96d64 | 3174 | ggtt->base.cleanup(&ggtt->base); |
a4eba47b | 3175 | return ret; |
baa09f5f | 3176 | } |
6f65e29a | 3177 | |
97d6d7ab | 3178 | int i915_ggtt_enable_hw(struct drm_i915_private *dev_priv) |
ac840ae5 | 3179 | { |
97d6d7ab | 3180 | if (INTEL_GEN(dev_priv) < 6 && !intel_enable_gtt()) |
ac840ae5 VS |
3181 | return -EIO; |
3182 | ||
3183 | return 0; | |
3184 | } | |
3185 | ||
7c3f86b6 CW |
3186 | void i915_ggtt_enable_guc(struct drm_i915_private *i915) |
3187 | { | |
04f7b24e CW |
3188 | GEM_BUG_ON(i915->ggtt.invalidate != gen6_ggtt_invalidate); |
3189 | ||
7c3f86b6 CW |
3190 | i915->ggtt.invalidate = guc_ggtt_invalidate; |
3191 | } | |
3192 | ||
3193 | void i915_ggtt_disable_guc(struct drm_i915_private *i915) | |
3194 | { | |
04f7b24e CW |
3195 | /* We should only be called after i915_ggtt_enable_guc() */ |
3196 | GEM_BUG_ON(i915->ggtt.invalidate != guc_ggtt_invalidate); | |
3197 | ||
3198 | i915->ggtt.invalidate = gen6_ggtt_invalidate; | |
7c3f86b6 CW |
3199 | } |
3200 | ||
275a991c | 3201 | void i915_gem_restore_gtt_mappings(struct drm_i915_private *dev_priv) |
fa42331b | 3202 | { |
72e96d64 | 3203 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
fbb30a5c | 3204 | struct drm_i915_gem_object *obj, *on; |
fa42331b | 3205 | |
dc97997a | 3206 | i915_check_and_clear_faults(dev_priv); |
fa42331b DV |
3207 | |
3208 | /* First fill our portion of the GTT with scratch pages */ | |
381b943b | 3209 | ggtt->base.clear_range(&ggtt->base, 0, ggtt->base.total); |
fa42331b | 3210 | |
fbb30a5c CW |
3211 | ggtt->base.closed = true; /* skip rewriting PTE on VMA unbind */ |
3212 | ||
3213 | /* clflush objects bound into the GGTT and rebind them. */ | |
3214 | list_for_each_entry_safe(obj, on, | |
56cea323 | 3215 | &dev_priv->mm.bound_list, global_link) { |
fbb30a5c CW |
3216 | bool ggtt_bound = false; |
3217 | struct i915_vma *vma; | |
3218 | ||
1c7f4bca | 3219 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
72e96d64 | 3220 | if (vma->vm != &ggtt->base) |
2c3d9984 | 3221 | continue; |
fa42331b | 3222 | |
fbb30a5c CW |
3223 | if (!i915_vma_unbind(vma)) |
3224 | continue; | |
3225 | ||
2c3d9984 TU |
3226 | WARN_ON(i915_vma_bind(vma, obj->cache_level, |
3227 | PIN_UPDATE)); | |
fbb30a5c | 3228 | ggtt_bound = true; |
2c3d9984 TU |
3229 | } |
3230 | ||
fbb30a5c | 3231 | if (ggtt_bound) |
975f7ff4 | 3232 | WARN_ON(i915_gem_object_set_to_gtt_domain(obj, false)); |
2c3d9984 | 3233 | } |
fa42331b | 3234 | |
fbb30a5c CW |
3235 | ggtt->base.closed = false; |
3236 | ||
275a991c | 3237 | if (INTEL_GEN(dev_priv) >= 8) { |
4e34935f RV |
3238 | if (INTEL_GEN(dev_priv) >= 10) |
3239 | cnl_setup_private_ppat(dev_priv); | |
3240 | else if (IS_CHERRYVIEW(dev_priv) || IS_GEN9_LP(dev_priv)) | |
fa42331b DV |
3241 | chv_setup_private_ppat(dev_priv); |
3242 | else | |
3243 | bdw_setup_private_ppat(dev_priv); | |
3244 | ||
3245 | return; | |
3246 | } | |
3247 | ||
275a991c | 3248 | if (USES_PPGTT(dev_priv)) { |
72e96d64 JL |
3249 | struct i915_address_space *vm; |
3250 | ||
fa42331b | 3251 | list_for_each_entry(vm, &dev_priv->vm_list, global_link) { |
e5716f55 | 3252 | struct i915_hw_ppgtt *ppgtt; |
fa42331b | 3253 | |
2bfa996e | 3254 | if (i915_is_ggtt(vm)) |
fa42331b | 3255 | ppgtt = dev_priv->mm.aliasing_ppgtt; |
e5716f55 JL |
3256 | else |
3257 | ppgtt = i915_vm_to_ppgtt(vm); | |
fa42331b | 3258 | |
16a011c8 | 3259 | gen6_write_page_range(ppgtt, 0, ppgtt->base.total); |
fa42331b DV |
3260 | } |
3261 | } | |
3262 | ||
7c3f86b6 | 3263 | i915_ggtt_invalidate(dev_priv); |
fa42331b DV |
3264 | } |
3265 | ||
804beb4b | 3266 | static struct scatterlist * |
2d7f3bdb | 3267 | rotate_pages(const dma_addr_t *in, unsigned int offset, |
804beb4b | 3268 | unsigned int width, unsigned int height, |
87130255 | 3269 | unsigned int stride, |
804beb4b | 3270 | struct sg_table *st, struct scatterlist *sg) |
50470bb0 TU |
3271 | { |
3272 | unsigned int column, row; | |
3273 | unsigned int src_idx; | |
50470bb0 | 3274 | |
50470bb0 | 3275 | for (column = 0; column < width; column++) { |
87130255 | 3276 | src_idx = stride * (height - 1) + column; |
50470bb0 TU |
3277 | for (row = 0; row < height; row++) { |
3278 | st->nents++; | |
3279 | /* We don't need the pages, but need to initialize | |
3280 | * the entries so the sg list can be happily traversed. | |
3281 | * The only thing we need are DMA addresses. | |
3282 | */ | |
3283 | sg_set_page(sg, NULL, PAGE_SIZE, 0); | |
804beb4b | 3284 | sg_dma_address(sg) = in[offset + src_idx]; |
50470bb0 TU |
3285 | sg_dma_len(sg) = PAGE_SIZE; |
3286 | sg = sg_next(sg); | |
87130255 | 3287 | src_idx -= stride; |
50470bb0 TU |
3288 | } |
3289 | } | |
804beb4b TU |
3290 | |
3291 | return sg; | |
50470bb0 TU |
3292 | } |
3293 | ||
ba7a5741 CW |
3294 | static noinline struct sg_table * |
3295 | intel_rotate_pages(struct intel_rotation_info *rot_info, | |
3296 | struct drm_i915_gem_object *obj) | |
50470bb0 | 3297 | { |
75c7b0b8 | 3298 | const unsigned long n_pages = obj->base.size / PAGE_SIZE; |
6687c906 | 3299 | unsigned int size = intel_rotation_info_size(rot_info); |
85d1225e DG |
3300 | struct sgt_iter sgt_iter; |
3301 | dma_addr_t dma_addr; | |
50470bb0 TU |
3302 | unsigned long i; |
3303 | dma_addr_t *page_addr_list; | |
3304 | struct sg_table *st; | |
89e3e142 | 3305 | struct scatterlist *sg; |
1d00dad5 | 3306 | int ret = -ENOMEM; |
50470bb0 | 3307 | |
50470bb0 | 3308 | /* Allocate a temporary list of source pages for random access. */ |
2098105e | 3309 | page_addr_list = kvmalloc_array(n_pages, |
f2a85e19 CW |
3310 | sizeof(dma_addr_t), |
3311 | GFP_TEMPORARY); | |
50470bb0 TU |
3312 | if (!page_addr_list) |
3313 | return ERR_PTR(ret); | |
3314 | ||
3315 | /* Allocate target SG list. */ | |
3316 | st = kmalloc(sizeof(*st), GFP_KERNEL); | |
3317 | if (!st) | |
3318 | goto err_st_alloc; | |
3319 | ||
6687c906 | 3320 | ret = sg_alloc_table(st, size, GFP_KERNEL); |
50470bb0 TU |
3321 | if (ret) |
3322 | goto err_sg_alloc; | |
3323 | ||
3324 | /* Populate source page list from the object. */ | |
3325 | i = 0; | |
a4f5ea64 | 3326 | for_each_sgt_dma(dma_addr, sgt_iter, obj->mm.pages) |
85d1225e | 3327 | page_addr_list[i++] = dma_addr; |
50470bb0 | 3328 | |
85d1225e | 3329 | GEM_BUG_ON(i != n_pages); |
11f20322 VS |
3330 | st->nents = 0; |
3331 | sg = st->sgl; | |
3332 | ||
6687c906 VS |
3333 | for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++) { |
3334 | sg = rotate_pages(page_addr_list, rot_info->plane[i].offset, | |
3335 | rot_info->plane[i].width, rot_info->plane[i].height, | |
3336 | rot_info->plane[i].stride, st, sg); | |
89e3e142 TU |
3337 | } |
3338 | ||
6687c906 VS |
3339 | DRM_DEBUG_KMS("Created rotated page mapping for object size %zu (%ux%u tiles, %u pages)\n", |
3340 | obj->base.size, rot_info->plane[0].width, rot_info->plane[0].height, size); | |
50470bb0 | 3341 | |
2098105e | 3342 | kvfree(page_addr_list); |
50470bb0 TU |
3343 | |
3344 | return st; | |
3345 | ||
3346 | err_sg_alloc: | |
3347 | kfree(st); | |
3348 | err_st_alloc: | |
2098105e | 3349 | kvfree(page_addr_list); |
50470bb0 | 3350 | |
6687c906 VS |
3351 | DRM_DEBUG_KMS("Failed to create rotated mapping for object size %zu! (%ux%u tiles, %u pages)\n", |
3352 | obj->base.size, rot_info->plane[0].width, rot_info->plane[0].height, size); | |
3353 | ||
50470bb0 TU |
3354 | return ERR_PTR(ret); |
3355 | } | |
ec7adb6e | 3356 | |
ba7a5741 | 3357 | static noinline struct sg_table * |
8bd7ef16 JL |
3358 | intel_partial_pages(const struct i915_ggtt_view *view, |
3359 | struct drm_i915_gem_object *obj) | |
3360 | { | |
3361 | struct sg_table *st; | |
d2a84a76 | 3362 | struct scatterlist *sg, *iter; |
8bab1193 | 3363 | unsigned int count = view->partial.size; |
d2a84a76 | 3364 | unsigned int offset; |
8bd7ef16 JL |
3365 | int ret = -ENOMEM; |
3366 | ||
3367 | st = kmalloc(sizeof(*st), GFP_KERNEL); | |
3368 | if (!st) | |
3369 | goto err_st_alloc; | |
3370 | ||
d2a84a76 | 3371 | ret = sg_alloc_table(st, count, GFP_KERNEL); |
8bd7ef16 JL |
3372 | if (ret) |
3373 | goto err_sg_alloc; | |
3374 | ||
8bab1193 | 3375 | iter = i915_gem_object_get_sg(obj, view->partial.offset, &offset); |
d2a84a76 CW |
3376 | GEM_BUG_ON(!iter); |
3377 | ||
8bd7ef16 JL |
3378 | sg = st->sgl; |
3379 | st->nents = 0; | |
d2a84a76 CW |
3380 | do { |
3381 | unsigned int len; | |
8bd7ef16 | 3382 | |
d2a84a76 CW |
3383 | len = min(iter->length - (offset << PAGE_SHIFT), |
3384 | count << PAGE_SHIFT); | |
3385 | sg_set_page(sg, NULL, len, 0); | |
3386 | sg_dma_address(sg) = | |
3387 | sg_dma_address(iter) + (offset << PAGE_SHIFT); | |
3388 | sg_dma_len(sg) = len; | |
8bd7ef16 | 3389 | |
8bd7ef16 | 3390 | st->nents++; |
d2a84a76 CW |
3391 | count -= len >> PAGE_SHIFT; |
3392 | if (count == 0) { | |
3393 | sg_mark_end(sg); | |
3394 | return st; | |
3395 | } | |
8bd7ef16 | 3396 | |
d2a84a76 CW |
3397 | sg = __sg_next(sg); |
3398 | iter = __sg_next(iter); | |
3399 | offset = 0; | |
3400 | } while (1); | |
8bd7ef16 JL |
3401 | |
3402 | err_sg_alloc: | |
3403 | kfree(st); | |
3404 | err_st_alloc: | |
3405 | return ERR_PTR(ret); | |
3406 | } | |
3407 | ||
70b9f6f8 | 3408 | static int |
50470bb0 | 3409 | i915_get_ggtt_vma_pages(struct i915_vma *vma) |
fe14d5f4 | 3410 | { |
ba7a5741 | 3411 | int ret; |
50470bb0 | 3412 | |
2c3a3f44 CW |
3413 | /* The vma->pages are only valid within the lifespan of the borrowed |
3414 | * obj->mm.pages. When the obj->mm.pages sg_table is regenerated, so | |
3415 | * must be the vma->pages. A simple rule is that vma->pages must only | |
3416 | * be accessed when the obj->mm.pages are pinned. | |
3417 | */ | |
3418 | GEM_BUG_ON(!i915_gem_object_has_pinned_pages(vma->obj)); | |
3419 | ||
ba7a5741 CW |
3420 | switch (vma->ggtt_view.type) { |
3421 | case I915_GGTT_VIEW_NORMAL: | |
3422 | vma->pages = vma->obj->mm.pages; | |
fe14d5f4 TU |
3423 | return 0; |
3424 | ||
ba7a5741 | 3425 | case I915_GGTT_VIEW_ROTATED: |
247177dd | 3426 | vma->pages = |
ba7a5741 CW |
3427 | intel_rotate_pages(&vma->ggtt_view.rotated, vma->obj); |
3428 | break; | |
3429 | ||
3430 | case I915_GGTT_VIEW_PARTIAL: | |
247177dd | 3431 | vma->pages = intel_partial_pages(&vma->ggtt_view, vma->obj); |
ba7a5741 CW |
3432 | break; |
3433 | ||
3434 | default: | |
fe14d5f4 TU |
3435 | WARN_ONCE(1, "GGTT view %u not implemented!\n", |
3436 | vma->ggtt_view.type); | |
ba7a5741 CW |
3437 | return -EINVAL; |
3438 | } | |
fe14d5f4 | 3439 | |
ba7a5741 CW |
3440 | ret = 0; |
3441 | if (unlikely(IS_ERR(vma->pages))) { | |
247177dd CW |
3442 | ret = PTR_ERR(vma->pages); |
3443 | vma->pages = NULL; | |
50470bb0 TU |
3444 | DRM_ERROR("Failed to get pages for VMA view type %u (%d)!\n", |
3445 | vma->ggtt_view.type, ret); | |
fe14d5f4 | 3446 | } |
50470bb0 | 3447 | return ret; |
fe14d5f4 TU |
3448 | } |
3449 | ||
625d988a CW |
3450 | /** |
3451 | * i915_gem_gtt_reserve - reserve a node in an address_space (GTT) | |
a4dbf7cf CW |
3452 | * @vm: the &struct i915_address_space |
3453 | * @node: the &struct drm_mm_node (typically i915_vma.mode) | |
3454 | * @size: how much space to allocate inside the GTT, | |
3455 | * must be #I915_GTT_PAGE_SIZE aligned | |
3456 | * @offset: where to insert inside the GTT, | |
3457 | * must be #I915_GTT_MIN_ALIGNMENT aligned, and the node | |
3458 | * (@offset + @size) must fit within the address space | |
3459 | * @color: color to apply to node, if this node is not from a VMA, | |
3460 | * color must be #I915_COLOR_UNEVICTABLE | |
3461 | * @flags: control search and eviction behaviour | |
625d988a CW |
3462 | * |
3463 | * i915_gem_gtt_reserve() tries to insert the @node at the exact @offset inside | |
3464 | * the address space (using @size and @color). If the @node does not fit, it | |
3465 | * tries to evict any overlapping nodes from the GTT, including any | |
3466 | * neighbouring nodes if the colors do not match (to ensure guard pages between | |
3467 | * differing domains). See i915_gem_evict_for_node() for the gory details | |
3468 | * on the eviction algorithm. #PIN_NONBLOCK may used to prevent waiting on | |
3469 | * evicting active overlapping objects, and any overlapping node that is pinned | |
3470 | * or marked as unevictable will also result in failure. | |
3471 | * | |
3472 | * Returns: 0 on success, -ENOSPC if no suitable hole is found, -EINTR if | |
3473 | * asked to wait for eviction and interrupted. | |
3474 | */ | |
3475 | int i915_gem_gtt_reserve(struct i915_address_space *vm, | |
3476 | struct drm_mm_node *node, | |
3477 | u64 size, u64 offset, unsigned long color, | |
3478 | unsigned int flags) | |
3479 | { | |
3480 | int err; | |
3481 | ||
3482 | GEM_BUG_ON(!size); | |
3483 | GEM_BUG_ON(!IS_ALIGNED(size, I915_GTT_PAGE_SIZE)); | |
3484 | GEM_BUG_ON(!IS_ALIGNED(offset, I915_GTT_MIN_ALIGNMENT)); | |
3485 | GEM_BUG_ON(range_overflows(offset, size, vm->total)); | |
3fec7ec4 | 3486 | GEM_BUG_ON(vm == &vm->i915->mm.aliasing_ppgtt->base); |
9734ad13 | 3487 | GEM_BUG_ON(drm_mm_node_allocated(node)); |
625d988a CW |
3488 | |
3489 | node->size = size; | |
3490 | node->start = offset; | |
3491 | node->color = color; | |
3492 | ||
3493 | err = drm_mm_reserve_node(&vm->mm, node); | |
3494 | if (err != -ENOSPC) | |
3495 | return err; | |
3496 | ||
616d9cee CW |
3497 | if (flags & PIN_NOEVICT) |
3498 | return -ENOSPC; | |
3499 | ||
625d988a CW |
3500 | err = i915_gem_evict_for_node(vm, node, flags); |
3501 | if (err == 0) | |
3502 | err = drm_mm_reserve_node(&vm->mm, node); | |
3503 | ||
3504 | return err; | |
3505 | } | |
3506 | ||
606fec95 CW |
3507 | static u64 random_offset(u64 start, u64 end, u64 len, u64 align) |
3508 | { | |
3509 | u64 range, addr; | |
3510 | ||
3511 | GEM_BUG_ON(range_overflows(start, len, end)); | |
3512 | GEM_BUG_ON(round_up(start, align) > round_down(end - len, align)); | |
3513 | ||
3514 | range = round_down(end - len, align) - round_up(start, align); | |
3515 | if (range) { | |
3516 | if (sizeof(unsigned long) == sizeof(u64)) { | |
3517 | addr = get_random_long(); | |
3518 | } else { | |
3519 | addr = get_random_int(); | |
3520 | if (range > U32_MAX) { | |
3521 | addr <<= 32; | |
3522 | addr |= get_random_int(); | |
3523 | } | |
3524 | } | |
3525 | div64_u64_rem(addr, range, &addr); | |
3526 | start += addr; | |
3527 | } | |
3528 | ||
3529 | return round_up(start, align); | |
3530 | } | |
3531 | ||
e007b19d CW |
3532 | /** |
3533 | * i915_gem_gtt_insert - insert a node into an address_space (GTT) | |
a4dbf7cf CW |
3534 | * @vm: the &struct i915_address_space |
3535 | * @node: the &struct drm_mm_node (typically i915_vma.node) | |
3536 | * @size: how much space to allocate inside the GTT, | |
3537 | * must be #I915_GTT_PAGE_SIZE aligned | |
3538 | * @alignment: required alignment of starting offset, may be 0 but | |
3539 | * if specified, this must be a power-of-two and at least | |
3540 | * #I915_GTT_MIN_ALIGNMENT | |
3541 | * @color: color to apply to node | |
3542 | * @start: start of any range restriction inside GTT (0 for all), | |
e007b19d | 3543 | * must be #I915_GTT_PAGE_SIZE aligned |
a4dbf7cf CW |
3544 | * @end: end of any range restriction inside GTT (U64_MAX for all), |
3545 | * must be #I915_GTT_PAGE_SIZE aligned if not U64_MAX | |
3546 | * @flags: control search and eviction behaviour | |
e007b19d CW |
3547 | * |
3548 | * i915_gem_gtt_insert() first searches for an available hole into which | |
3549 | * is can insert the node. The hole address is aligned to @alignment and | |
3550 | * its @size must then fit entirely within the [@start, @end] bounds. The | |
3551 | * nodes on either side of the hole must match @color, or else a guard page | |
3552 | * will be inserted between the two nodes (or the node evicted). If no | |
606fec95 CW |
3553 | * suitable hole is found, first a victim is randomly selected and tested |
3554 | * for eviction, otherwise then the LRU list of objects within the GTT | |
e007b19d CW |
3555 | * is scanned to find the first set of replacement nodes to create the hole. |
3556 | * Those old overlapping nodes are evicted from the GTT (and so must be | |
3557 | * rebound before any future use). Any node that is currently pinned cannot | |
3558 | * be evicted (see i915_vma_pin()). Similar if the node's VMA is currently | |
3559 | * active and #PIN_NONBLOCK is specified, that node is also skipped when | |
3560 | * searching for an eviction candidate. See i915_gem_evict_something() for | |
3561 | * the gory details on the eviction algorithm. | |
3562 | * | |
3563 | * Returns: 0 on success, -ENOSPC if no suitable hole is found, -EINTR if | |
3564 | * asked to wait for eviction and interrupted. | |
3565 | */ | |
3566 | int i915_gem_gtt_insert(struct i915_address_space *vm, | |
3567 | struct drm_mm_node *node, | |
3568 | u64 size, u64 alignment, unsigned long color, | |
3569 | u64 start, u64 end, unsigned int flags) | |
3570 | { | |
4e64e553 | 3571 | enum drm_mm_insert_mode mode; |
606fec95 | 3572 | u64 offset; |
e007b19d CW |
3573 | int err; |
3574 | ||
3575 | lockdep_assert_held(&vm->i915->drm.struct_mutex); | |
3576 | GEM_BUG_ON(!size); | |
3577 | GEM_BUG_ON(!IS_ALIGNED(size, I915_GTT_PAGE_SIZE)); | |
3578 | GEM_BUG_ON(alignment && !is_power_of_2(alignment)); | |
3579 | GEM_BUG_ON(alignment && !IS_ALIGNED(alignment, I915_GTT_MIN_ALIGNMENT)); | |
3580 | GEM_BUG_ON(start >= end); | |
3581 | GEM_BUG_ON(start > 0 && !IS_ALIGNED(start, I915_GTT_PAGE_SIZE)); | |
3582 | GEM_BUG_ON(end < U64_MAX && !IS_ALIGNED(end, I915_GTT_PAGE_SIZE)); | |
3fec7ec4 | 3583 | GEM_BUG_ON(vm == &vm->i915->mm.aliasing_ppgtt->base); |
9734ad13 | 3584 | GEM_BUG_ON(drm_mm_node_allocated(node)); |
e007b19d CW |
3585 | |
3586 | if (unlikely(range_overflows(start, size, end))) | |
3587 | return -ENOSPC; | |
3588 | ||
3589 | if (unlikely(round_up(start, alignment) > round_down(end - size, alignment))) | |
3590 | return -ENOSPC; | |
3591 | ||
4e64e553 CW |
3592 | mode = DRM_MM_INSERT_BEST; |
3593 | if (flags & PIN_HIGH) | |
3594 | mode = DRM_MM_INSERT_HIGH; | |
3595 | if (flags & PIN_MAPPABLE) | |
3596 | mode = DRM_MM_INSERT_LOW; | |
e007b19d CW |
3597 | |
3598 | /* We only allocate in PAGE_SIZE/GTT_PAGE_SIZE (4096) chunks, | |
3599 | * so we know that we always have a minimum alignment of 4096. | |
3600 | * The drm_mm range manager is optimised to return results | |
3601 | * with zero alignment, so where possible use the optimal | |
3602 | * path. | |
3603 | */ | |
3604 | BUILD_BUG_ON(I915_GTT_MIN_ALIGNMENT > I915_GTT_PAGE_SIZE); | |
3605 | if (alignment <= I915_GTT_MIN_ALIGNMENT) | |
3606 | alignment = 0; | |
3607 | ||
4e64e553 CW |
3608 | err = drm_mm_insert_node_in_range(&vm->mm, node, |
3609 | size, alignment, color, | |
3610 | start, end, mode); | |
e007b19d CW |
3611 | if (err != -ENOSPC) |
3612 | return err; | |
3613 | ||
616d9cee CW |
3614 | if (flags & PIN_NOEVICT) |
3615 | return -ENOSPC; | |
3616 | ||
606fec95 CW |
3617 | /* No free space, pick a slot at random. |
3618 | * | |
3619 | * There is a pathological case here using a GTT shared between | |
3620 | * mmap and GPU (i.e. ggtt/aliasing_ppgtt but not full-ppgtt): | |
3621 | * | |
3622 | * |<-- 256 MiB aperture -->||<-- 1792 MiB unmappable -->| | |
3623 | * (64k objects) (448k objects) | |
3624 | * | |
3625 | * Now imagine that the eviction LRU is ordered top-down (just because | |
3626 | * pathology meets real life), and that we need to evict an object to | |
3627 | * make room inside the aperture. The eviction scan then has to walk | |
3628 | * the 448k list before it finds one within range. And now imagine that | |
3629 | * it has to search for a new hole between every byte inside the memcpy, | |
3630 | * for several simultaneous clients. | |
3631 | * | |
3632 | * On a full-ppgtt system, if we have run out of available space, there | |
3633 | * will be lots and lots of objects in the eviction list! Again, | |
3634 | * searching that LRU list may be slow if we are also applying any | |
3635 | * range restrictions (e.g. restriction to low 4GiB) and so, for | |
3636 | * simplicity and similarilty between different GTT, try the single | |
3637 | * random replacement first. | |
3638 | */ | |
3639 | offset = random_offset(start, end, | |
3640 | size, alignment ?: I915_GTT_MIN_ALIGNMENT); | |
3641 | err = i915_gem_gtt_reserve(vm, node, size, offset, color, flags); | |
3642 | if (err != -ENOSPC) | |
3643 | return err; | |
3644 | ||
3645 | /* Randomly selected placement is pinned, do a search */ | |
e007b19d CW |
3646 | err = i915_gem_evict_something(vm, size, alignment, color, |
3647 | start, end, flags); | |
3648 | if (err) | |
3649 | return err; | |
3650 | ||
4e64e553 CW |
3651 | return drm_mm_insert_node_in_range(&vm->mm, node, |
3652 | size, alignment, color, | |
3653 | start, end, DRM_MM_INSERT_EVICT); | |
e007b19d | 3654 | } |
3b5bb0a3 CW |
3655 | |
3656 | #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) | |
3657 | #include "selftests/mock_gtt.c" | |
1c42819a | 3658 | #include "selftests/i915_gem_gtt.c" |
3b5bb0a3 | 3659 | #endif |