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76aaf220 DV |
1 | /* |
2 | * Copyright © 2010 Daniel Vetter | |
c4ac524c | 3 | * Copyright © 2011-2014 Intel Corporation |
76aaf220 DV |
4 | * |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
22 | * IN THE SOFTWARE. | |
23 | * | |
24 | */ | |
25 | ||
0e46ce2e | 26 | #include <linux/seq_file.h> |
5bab6f60 | 27 | #include <linux/stop_machine.h> |
760285e7 DH |
28 | #include <drm/drmP.h> |
29 | #include <drm/i915_drm.h> | |
76aaf220 | 30 | #include "i915_drv.h" |
5dda8fa3 | 31 | #include "i915_vgpu.h" |
76aaf220 DV |
32 | #include "i915_trace.h" |
33 | #include "intel_drv.h" | |
34 | ||
45f8f69a TU |
35 | /** |
36 | * DOC: Global GTT views | |
37 | * | |
38 | * Background and previous state | |
39 | * | |
40 | * Historically objects could exists (be bound) in global GTT space only as | |
41 | * singular instances with a view representing all of the object's backing pages | |
42 | * in a linear fashion. This view will be called a normal view. | |
43 | * | |
44 | * To support multiple views of the same object, where the number of mapped | |
45 | * pages is not equal to the backing store, or where the layout of the pages | |
46 | * is not linear, concept of a GGTT view was added. | |
47 | * | |
48 | * One example of an alternative view is a stereo display driven by a single | |
49 | * image. In this case we would have a framebuffer looking like this | |
50 | * (2x2 pages): | |
51 | * | |
52 | * 12 | |
53 | * 34 | |
54 | * | |
55 | * Above would represent a normal GGTT view as normally mapped for GPU or CPU | |
56 | * rendering. In contrast, fed to the display engine would be an alternative | |
57 | * view which could look something like this: | |
58 | * | |
59 | * 1212 | |
60 | * 3434 | |
61 | * | |
62 | * In this example both the size and layout of pages in the alternative view is | |
63 | * different from the normal view. | |
64 | * | |
65 | * Implementation and usage | |
66 | * | |
67 | * GGTT views are implemented using VMAs and are distinguished via enum | |
68 | * i915_ggtt_view_type and struct i915_ggtt_view. | |
69 | * | |
70 | * A new flavour of core GEM functions which work with GGTT bound objects were | |
ec7adb6e JL |
71 | * added with the _ggtt_ infix, and sometimes with _view postfix to avoid |
72 | * renaming in large amounts of code. They take the struct i915_ggtt_view | |
73 | * parameter encapsulating all metadata required to implement a view. | |
45f8f69a TU |
74 | * |
75 | * As a helper for callers which are only interested in the normal view, | |
76 | * globally const i915_ggtt_view_normal singleton instance exists. All old core | |
77 | * GEM API functions, the ones not taking the view parameter, are operating on, | |
78 | * or with the normal GGTT view. | |
79 | * | |
80 | * Code wanting to add or use a new GGTT view needs to: | |
81 | * | |
82 | * 1. Add a new enum with a suitable name. | |
83 | * 2. Extend the metadata in the i915_ggtt_view structure if required. | |
84 | * 3. Add support to i915_get_vma_pages(). | |
85 | * | |
86 | * New views are required to build a scatter-gather table from within the | |
87 | * i915_get_vma_pages function. This table is stored in the vma.ggtt_view and | |
88 | * exists for the lifetime of an VMA. | |
89 | * | |
90 | * Core API is designed to have copy semantics which means that passed in | |
91 | * struct i915_ggtt_view does not need to be persistent (left around after | |
92 | * calling the core API functions). | |
93 | * | |
94 | */ | |
95 | ||
ce7fda2e CW |
96 | static inline struct i915_ggtt * |
97 | i915_vm_to_ggtt(struct i915_address_space *vm) | |
98 | { | |
99 | GEM_BUG_ON(!i915_is_ggtt(vm)); | |
100 | return container_of(vm, struct i915_ggtt, base); | |
101 | } | |
102 | ||
70b9f6f8 DV |
103 | static int |
104 | i915_get_ggtt_vma_pages(struct i915_vma *vma); | |
105 | ||
b5e16987 VS |
106 | const struct i915_ggtt_view i915_ggtt_view_normal = { |
107 | .type = I915_GGTT_VIEW_NORMAL, | |
108 | }; | |
9abc4648 | 109 | const struct i915_ggtt_view i915_ggtt_view_rotated = { |
b5e16987 | 110 | .type = I915_GGTT_VIEW_ROTATED, |
9abc4648 | 111 | }; |
fe14d5f4 | 112 | |
c033666a CW |
113 | int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv, |
114 | int enable_ppgtt) | |
cfa7c862 | 115 | { |
1893a71b CW |
116 | bool has_aliasing_ppgtt; |
117 | bool has_full_ppgtt; | |
1f9a99e0 | 118 | bool has_full_48bit_ppgtt; |
1893a71b | 119 | |
c033666a CW |
120 | has_aliasing_ppgtt = INTEL_GEN(dev_priv) >= 6; |
121 | has_full_ppgtt = INTEL_GEN(dev_priv) >= 7; | |
122 | has_full_48bit_ppgtt = | |
123 | IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9; | |
1893a71b | 124 | |
c033666a | 125 | if (intel_vgpu_active(dev_priv)) |
71ba2d64 YZ |
126 | has_full_ppgtt = false; /* emulation is too hard */ |
127 | ||
0e4ca100 CW |
128 | if (!has_aliasing_ppgtt) |
129 | return 0; | |
130 | ||
70ee45e1 DL |
131 | /* |
132 | * We don't allow disabling PPGTT for gen9+ as it's a requirement for | |
133 | * execlists, the sole mechanism available to submit work. | |
134 | */ | |
c033666a | 135 | if (enable_ppgtt == 0 && INTEL_GEN(dev_priv) < 9) |
cfa7c862 DV |
136 | return 0; |
137 | ||
138 | if (enable_ppgtt == 1) | |
139 | return 1; | |
140 | ||
1893a71b | 141 | if (enable_ppgtt == 2 && has_full_ppgtt) |
cfa7c862 DV |
142 | return 2; |
143 | ||
1f9a99e0 MT |
144 | if (enable_ppgtt == 3 && has_full_48bit_ppgtt) |
145 | return 3; | |
146 | ||
93a25a9e DV |
147 | #ifdef CONFIG_INTEL_IOMMU |
148 | /* Disable ppgtt on SNB if VT-d is on. */ | |
c033666a | 149 | if (IS_GEN6(dev_priv) && intel_iommu_gfx_mapped) { |
93a25a9e | 150 | DRM_INFO("Disabling PPGTT because VT-d is on\n"); |
cfa7c862 | 151 | return 0; |
93a25a9e DV |
152 | } |
153 | #endif | |
154 | ||
62942ed7 | 155 | /* Early VLV doesn't have this */ |
91c8a326 | 156 | if (IS_VALLEYVIEW(dev_priv) && dev_priv->drm.pdev->revision < 0xb) { |
62942ed7 JB |
157 | DRM_DEBUG_DRIVER("disabling PPGTT on pre-B3 step VLV\n"); |
158 | return 0; | |
159 | } | |
160 | ||
c033666a | 161 | if (INTEL_GEN(dev_priv) >= 8 && i915.enable_execlists) |
1f9a99e0 | 162 | return has_full_48bit_ppgtt ? 3 : 2; |
2f82bbdf MT |
163 | else |
164 | return has_aliasing_ppgtt ? 1 : 0; | |
93a25a9e DV |
165 | } |
166 | ||
70b9f6f8 DV |
167 | static int ppgtt_bind_vma(struct i915_vma *vma, |
168 | enum i915_cache_level cache_level, | |
169 | u32 unused) | |
47552659 DV |
170 | { |
171 | u32 pte_flags = 0; | |
172 | ||
247177dd CW |
173 | vma->pages = vma->obj->pages; |
174 | ||
47552659 DV |
175 | /* Currently applicable only to VLV */ |
176 | if (vma->obj->gt_ro) | |
177 | pte_flags |= PTE_READ_ONLY; | |
178 | ||
247177dd | 179 | vma->vm->insert_entries(vma->vm, vma->pages, vma->node.start, |
47552659 | 180 | cache_level, pte_flags); |
70b9f6f8 DV |
181 | |
182 | return 0; | |
47552659 DV |
183 | } |
184 | ||
185 | static void ppgtt_unbind_vma(struct i915_vma *vma) | |
186 | { | |
187 | vma->vm->clear_range(vma->vm, | |
188 | vma->node.start, | |
de180033 | 189 | vma->size, |
47552659 DV |
190 | true); |
191 | } | |
6f65e29a | 192 | |
2c642b07 DV |
193 | static gen8_pte_t gen8_pte_encode(dma_addr_t addr, |
194 | enum i915_cache_level level, | |
195 | bool valid) | |
94ec8f61 | 196 | { |
07749ef3 | 197 | gen8_pte_t pte = valid ? _PAGE_PRESENT | _PAGE_RW : 0; |
94ec8f61 | 198 | pte |= addr; |
63c42e56 BW |
199 | |
200 | switch (level) { | |
201 | case I915_CACHE_NONE: | |
fbe5d36e | 202 | pte |= PPAT_UNCACHED_INDEX; |
63c42e56 BW |
203 | break; |
204 | case I915_CACHE_WT: | |
205 | pte |= PPAT_DISPLAY_ELLC_INDEX; | |
206 | break; | |
207 | default: | |
208 | pte |= PPAT_CACHED_INDEX; | |
209 | break; | |
210 | } | |
211 | ||
94ec8f61 BW |
212 | return pte; |
213 | } | |
214 | ||
fe36f55d MK |
215 | static gen8_pde_t gen8_pde_encode(const dma_addr_t addr, |
216 | const enum i915_cache_level level) | |
b1fe6673 | 217 | { |
07749ef3 | 218 | gen8_pde_t pde = _PAGE_PRESENT | _PAGE_RW; |
b1fe6673 BW |
219 | pde |= addr; |
220 | if (level != I915_CACHE_NONE) | |
221 | pde |= PPAT_CACHED_PDE_INDEX; | |
222 | else | |
223 | pde |= PPAT_UNCACHED_INDEX; | |
224 | return pde; | |
225 | } | |
226 | ||
762d9936 MT |
227 | #define gen8_pdpe_encode gen8_pde_encode |
228 | #define gen8_pml4e_encode gen8_pde_encode | |
229 | ||
07749ef3 MT |
230 | static gen6_pte_t snb_pte_encode(dma_addr_t addr, |
231 | enum i915_cache_level level, | |
232 | bool valid, u32 unused) | |
54d12527 | 233 | { |
07749ef3 | 234 | gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
54d12527 | 235 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
e7210c3c BW |
236 | |
237 | switch (level) { | |
350ec881 CW |
238 | case I915_CACHE_L3_LLC: |
239 | case I915_CACHE_LLC: | |
240 | pte |= GEN6_PTE_CACHE_LLC; | |
241 | break; | |
242 | case I915_CACHE_NONE: | |
243 | pte |= GEN6_PTE_UNCACHED; | |
244 | break; | |
245 | default: | |
5f77eeb0 | 246 | MISSING_CASE(level); |
350ec881 CW |
247 | } |
248 | ||
249 | return pte; | |
250 | } | |
251 | ||
07749ef3 MT |
252 | static gen6_pte_t ivb_pte_encode(dma_addr_t addr, |
253 | enum i915_cache_level level, | |
254 | bool valid, u32 unused) | |
350ec881 | 255 | { |
07749ef3 | 256 | gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
350ec881 CW |
257 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
258 | ||
259 | switch (level) { | |
260 | case I915_CACHE_L3_LLC: | |
261 | pte |= GEN7_PTE_CACHE_L3_LLC; | |
e7210c3c BW |
262 | break; |
263 | case I915_CACHE_LLC: | |
264 | pte |= GEN6_PTE_CACHE_LLC; | |
265 | break; | |
266 | case I915_CACHE_NONE: | |
9119708c | 267 | pte |= GEN6_PTE_UNCACHED; |
e7210c3c BW |
268 | break; |
269 | default: | |
5f77eeb0 | 270 | MISSING_CASE(level); |
e7210c3c BW |
271 | } |
272 | ||
54d12527 BW |
273 | return pte; |
274 | } | |
275 | ||
07749ef3 MT |
276 | static gen6_pte_t byt_pte_encode(dma_addr_t addr, |
277 | enum i915_cache_level level, | |
278 | bool valid, u32 flags) | |
93c34e70 | 279 | { |
07749ef3 | 280 | gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
93c34e70 KG |
281 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
282 | ||
24f3a8cf AG |
283 | if (!(flags & PTE_READ_ONLY)) |
284 | pte |= BYT_PTE_WRITEABLE; | |
93c34e70 KG |
285 | |
286 | if (level != I915_CACHE_NONE) | |
287 | pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES; | |
288 | ||
289 | return pte; | |
290 | } | |
291 | ||
07749ef3 MT |
292 | static gen6_pte_t hsw_pte_encode(dma_addr_t addr, |
293 | enum i915_cache_level level, | |
294 | bool valid, u32 unused) | |
9119708c | 295 | { |
07749ef3 | 296 | gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
0d8ff15e | 297 | pte |= HSW_PTE_ADDR_ENCODE(addr); |
9119708c KG |
298 | |
299 | if (level != I915_CACHE_NONE) | |
87a6b688 | 300 | pte |= HSW_WB_LLC_AGE3; |
9119708c KG |
301 | |
302 | return pte; | |
303 | } | |
304 | ||
07749ef3 MT |
305 | static gen6_pte_t iris_pte_encode(dma_addr_t addr, |
306 | enum i915_cache_level level, | |
307 | bool valid, u32 unused) | |
4d15c145 | 308 | { |
07749ef3 | 309 | gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
4d15c145 BW |
310 | pte |= HSW_PTE_ADDR_ENCODE(addr); |
311 | ||
651d794f CW |
312 | switch (level) { |
313 | case I915_CACHE_NONE: | |
314 | break; | |
315 | case I915_CACHE_WT: | |
c51e9701 | 316 | pte |= HSW_WT_ELLC_LLC_AGE3; |
651d794f CW |
317 | break; |
318 | default: | |
c51e9701 | 319 | pte |= HSW_WB_ELLC_LLC_AGE3; |
651d794f CW |
320 | break; |
321 | } | |
4d15c145 BW |
322 | |
323 | return pte; | |
324 | } | |
325 | ||
c114f76a MK |
326 | static int __setup_page_dma(struct drm_device *dev, |
327 | struct i915_page_dma *p, gfp_t flags) | |
678d96fb BW |
328 | { |
329 | struct device *device = &dev->pdev->dev; | |
330 | ||
c114f76a | 331 | p->page = alloc_page(flags); |
44159ddb MK |
332 | if (!p->page) |
333 | return -ENOMEM; | |
678d96fb | 334 | |
44159ddb MK |
335 | p->daddr = dma_map_page(device, |
336 | p->page, 0, 4096, PCI_DMA_BIDIRECTIONAL); | |
678d96fb | 337 | |
44159ddb MK |
338 | if (dma_mapping_error(device, p->daddr)) { |
339 | __free_page(p->page); | |
340 | return -EINVAL; | |
341 | } | |
1266cdb1 MT |
342 | |
343 | return 0; | |
678d96fb BW |
344 | } |
345 | ||
c114f76a MK |
346 | static int setup_page_dma(struct drm_device *dev, struct i915_page_dma *p) |
347 | { | |
348 | return __setup_page_dma(dev, p, GFP_KERNEL); | |
349 | } | |
350 | ||
44159ddb | 351 | static void cleanup_page_dma(struct drm_device *dev, struct i915_page_dma *p) |
06fda602 | 352 | { |
44159ddb | 353 | if (WARN_ON(!p->page)) |
06fda602 | 354 | return; |
678d96fb | 355 | |
44159ddb MK |
356 | dma_unmap_page(&dev->pdev->dev, p->daddr, 4096, PCI_DMA_BIDIRECTIONAL); |
357 | __free_page(p->page); | |
358 | memset(p, 0, sizeof(*p)); | |
359 | } | |
360 | ||
d1c54acd | 361 | static void *kmap_page_dma(struct i915_page_dma *p) |
73eeea53 | 362 | { |
d1c54acd MK |
363 | return kmap_atomic(p->page); |
364 | } | |
73eeea53 | 365 | |
d1c54acd MK |
366 | /* We use the flushing unmap only with ppgtt structures: |
367 | * page directories, page tables and scratch pages. | |
368 | */ | |
369 | static void kunmap_page_dma(struct drm_device *dev, void *vaddr) | |
370 | { | |
73eeea53 MK |
371 | /* There are only few exceptions for gen >=6. chv and bxt. |
372 | * And we are not sure about the latter so play safe for now. | |
373 | */ | |
374 | if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev)) | |
375 | drm_clflush_virt_range(vaddr, PAGE_SIZE); | |
376 | ||
377 | kunmap_atomic(vaddr); | |
378 | } | |
379 | ||
567047be | 380 | #define kmap_px(px) kmap_page_dma(px_base(px)) |
d1c54acd MK |
381 | #define kunmap_px(ppgtt, vaddr) kunmap_page_dma((ppgtt)->base.dev, (vaddr)) |
382 | ||
567047be MK |
383 | #define setup_px(dev, px) setup_page_dma((dev), px_base(px)) |
384 | #define cleanup_px(dev, px) cleanup_page_dma((dev), px_base(px)) | |
385 | #define fill_px(dev, px, v) fill_page_dma((dev), px_base(px), (v)) | |
386 | #define fill32_px(dev, px, v) fill_page_dma_32((dev), px_base(px), (v)) | |
387 | ||
d1c54acd MK |
388 | static void fill_page_dma(struct drm_device *dev, struct i915_page_dma *p, |
389 | const uint64_t val) | |
390 | { | |
391 | int i; | |
392 | uint64_t * const vaddr = kmap_page_dma(p); | |
393 | ||
394 | for (i = 0; i < 512; i++) | |
395 | vaddr[i] = val; | |
396 | ||
397 | kunmap_page_dma(dev, vaddr); | |
398 | } | |
399 | ||
73eeea53 MK |
400 | static void fill_page_dma_32(struct drm_device *dev, struct i915_page_dma *p, |
401 | const uint32_t val32) | |
402 | { | |
403 | uint64_t v = val32; | |
404 | ||
405 | v = v << 32 | val32; | |
406 | ||
407 | fill_page_dma(dev, p, v); | |
408 | } | |
409 | ||
4ad2af1e MK |
410 | static struct i915_page_scratch *alloc_scratch_page(struct drm_device *dev) |
411 | { | |
412 | struct i915_page_scratch *sp; | |
413 | int ret; | |
414 | ||
415 | sp = kzalloc(sizeof(*sp), GFP_KERNEL); | |
416 | if (sp == NULL) | |
417 | return ERR_PTR(-ENOMEM); | |
418 | ||
419 | ret = __setup_page_dma(dev, px_base(sp), GFP_DMA32 | __GFP_ZERO); | |
420 | if (ret) { | |
421 | kfree(sp); | |
422 | return ERR_PTR(ret); | |
423 | } | |
424 | ||
425 | set_pages_uc(px_page(sp), 1); | |
426 | ||
427 | return sp; | |
428 | } | |
429 | ||
430 | static void free_scratch_page(struct drm_device *dev, | |
431 | struct i915_page_scratch *sp) | |
432 | { | |
433 | set_pages_wb(px_page(sp), 1); | |
434 | ||
435 | cleanup_px(dev, sp); | |
436 | kfree(sp); | |
437 | } | |
438 | ||
8a1ebd74 | 439 | static struct i915_page_table *alloc_pt(struct drm_device *dev) |
06fda602 | 440 | { |
ec565b3c | 441 | struct i915_page_table *pt; |
678d96fb BW |
442 | const size_t count = INTEL_INFO(dev)->gen >= 8 ? |
443 | GEN8_PTES : GEN6_PTES; | |
444 | int ret = -ENOMEM; | |
06fda602 BW |
445 | |
446 | pt = kzalloc(sizeof(*pt), GFP_KERNEL); | |
447 | if (!pt) | |
448 | return ERR_PTR(-ENOMEM); | |
449 | ||
678d96fb BW |
450 | pt->used_ptes = kcalloc(BITS_TO_LONGS(count), sizeof(*pt->used_ptes), |
451 | GFP_KERNEL); | |
452 | ||
453 | if (!pt->used_ptes) | |
454 | goto fail_bitmap; | |
455 | ||
567047be | 456 | ret = setup_px(dev, pt); |
678d96fb | 457 | if (ret) |
44159ddb | 458 | goto fail_page_m; |
06fda602 BW |
459 | |
460 | return pt; | |
678d96fb | 461 | |
44159ddb | 462 | fail_page_m: |
678d96fb BW |
463 | kfree(pt->used_ptes); |
464 | fail_bitmap: | |
465 | kfree(pt); | |
466 | ||
467 | return ERR_PTR(ret); | |
06fda602 BW |
468 | } |
469 | ||
2e906bea | 470 | static void free_pt(struct drm_device *dev, struct i915_page_table *pt) |
06fda602 | 471 | { |
2e906bea MK |
472 | cleanup_px(dev, pt); |
473 | kfree(pt->used_ptes); | |
474 | kfree(pt); | |
475 | } | |
476 | ||
477 | static void gen8_initialize_pt(struct i915_address_space *vm, | |
478 | struct i915_page_table *pt) | |
479 | { | |
480 | gen8_pte_t scratch_pte; | |
481 | ||
482 | scratch_pte = gen8_pte_encode(px_dma(vm->scratch_page), | |
483 | I915_CACHE_LLC, true); | |
484 | ||
485 | fill_px(vm->dev, pt, scratch_pte); | |
486 | } | |
487 | ||
488 | static void gen6_initialize_pt(struct i915_address_space *vm, | |
489 | struct i915_page_table *pt) | |
490 | { | |
491 | gen6_pte_t scratch_pte; | |
492 | ||
493 | WARN_ON(px_dma(vm->scratch_page) == 0); | |
494 | ||
495 | scratch_pte = vm->pte_encode(px_dma(vm->scratch_page), | |
496 | I915_CACHE_LLC, true, 0); | |
497 | ||
498 | fill32_px(vm->dev, pt, scratch_pte); | |
06fda602 BW |
499 | } |
500 | ||
8a1ebd74 | 501 | static struct i915_page_directory *alloc_pd(struct drm_device *dev) |
06fda602 | 502 | { |
ec565b3c | 503 | struct i915_page_directory *pd; |
33c8819f | 504 | int ret = -ENOMEM; |
06fda602 BW |
505 | |
506 | pd = kzalloc(sizeof(*pd), GFP_KERNEL); | |
507 | if (!pd) | |
508 | return ERR_PTR(-ENOMEM); | |
509 | ||
33c8819f MT |
510 | pd->used_pdes = kcalloc(BITS_TO_LONGS(I915_PDES), |
511 | sizeof(*pd->used_pdes), GFP_KERNEL); | |
512 | if (!pd->used_pdes) | |
a08e111a | 513 | goto fail_bitmap; |
33c8819f | 514 | |
567047be | 515 | ret = setup_px(dev, pd); |
33c8819f | 516 | if (ret) |
a08e111a | 517 | goto fail_page_m; |
e5815a2e | 518 | |
06fda602 | 519 | return pd; |
33c8819f | 520 | |
a08e111a | 521 | fail_page_m: |
33c8819f | 522 | kfree(pd->used_pdes); |
a08e111a | 523 | fail_bitmap: |
33c8819f MT |
524 | kfree(pd); |
525 | ||
526 | return ERR_PTR(ret); | |
06fda602 BW |
527 | } |
528 | ||
2e906bea MK |
529 | static void free_pd(struct drm_device *dev, struct i915_page_directory *pd) |
530 | { | |
531 | if (px_page(pd)) { | |
532 | cleanup_px(dev, pd); | |
533 | kfree(pd->used_pdes); | |
534 | kfree(pd); | |
535 | } | |
536 | } | |
537 | ||
538 | static void gen8_initialize_pd(struct i915_address_space *vm, | |
539 | struct i915_page_directory *pd) | |
540 | { | |
541 | gen8_pde_t scratch_pde; | |
542 | ||
543 | scratch_pde = gen8_pde_encode(px_dma(vm->scratch_pt), I915_CACHE_LLC); | |
544 | ||
545 | fill_px(vm->dev, pd, scratch_pde); | |
546 | } | |
547 | ||
6ac18502 MT |
548 | static int __pdp_init(struct drm_device *dev, |
549 | struct i915_page_directory_pointer *pdp) | |
550 | { | |
551 | size_t pdpes = I915_PDPES_PER_PDP(dev); | |
552 | ||
553 | pdp->used_pdpes = kcalloc(BITS_TO_LONGS(pdpes), | |
554 | sizeof(unsigned long), | |
555 | GFP_KERNEL); | |
556 | if (!pdp->used_pdpes) | |
557 | return -ENOMEM; | |
558 | ||
559 | pdp->page_directory = kcalloc(pdpes, sizeof(*pdp->page_directory), | |
560 | GFP_KERNEL); | |
561 | if (!pdp->page_directory) { | |
562 | kfree(pdp->used_pdpes); | |
563 | /* the PDP might be the statically allocated top level. Keep it | |
564 | * as clean as possible */ | |
565 | pdp->used_pdpes = NULL; | |
566 | return -ENOMEM; | |
567 | } | |
568 | ||
569 | return 0; | |
570 | } | |
571 | ||
572 | static void __pdp_fini(struct i915_page_directory_pointer *pdp) | |
573 | { | |
574 | kfree(pdp->used_pdpes); | |
575 | kfree(pdp->page_directory); | |
576 | pdp->page_directory = NULL; | |
577 | } | |
578 | ||
762d9936 MT |
579 | static struct |
580 | i915_page_directory_pointer *alloc_pdp(struct drm_device *dev) | |
581 | { | |
582 | struct i915_page_directory_pointer *pdp; | |
583 | int ret = -ENOMEM; | |
584 | ||
585 | WARN_ON(!USES_FULL_48BIT_PPGTT(dev)); | |
586 | ||
587 | pdp = kzalloc(sizeof(*pdp), GFP_KERNEL); | |
588 | if (!pdp) | |
589 | return ERR_PTR(-ENOMEM); | |
590 | ||
591 | ret = __pdp_init(dev, pdp); | |
592 | if (ret) | |
593 | goto fail_bitmap; | |
594 | ||
595 | ret = setup_px(dev, pdp); | |
596 | if (ret) | |
597 | goto fail_page_m; | |
598 | ||
599 | return pdp; | |
600 | ||
601 | fail_page_m: | |
602 | __pdp_fini(pdp); | |
603 | fail_bitmap: | |
604 | kfree(pdp); | |
605 | ||
606 | return ERR_PTR(ret); | |
607 | } | |
608 | ||
6ac18502 MT |
609 | static void free_pdp(struct drm_device *dev, |
610 | struct i915_page_directory_pointer *pdp) | |
611 | { | |
612 | __pdp_fini(pdp); | |
762d9936 MT |
613 | if (USES_FULL_48BIT_PPGTT(dev)) { |
614 | cleanup_px(dev, pdp); | |
615 | kfree(pdp); | |
616 | } | |
617 | } | |
618 | ||
69ab76fd MT |
619 | static void gen8_initialize_pdp(struct i915_address_space *vm, |
620 | struct i915_page_directory_pointer *pdp) | |
621 | { | |
622 | gen8_ppgtt_pdpe_t scratch_pdpe; | |
623 | ||
624 | scratch_pdpe = gen8_pdpe_encode(px_dma(vm->scratch_pd), I915_CACHE_LLC); | |
625 | ||
626 | fill_px(vm->dev, pdp, scratch_pdpe); | |
627 | } | |
628 | ||
629 | static void gen8_initialize_pml4(struct i915_address_space *vm, | |
630 | struct i915_pml4 *pml4) | |
631 | { | |
632 | gen8_ppgtt_pml4e_t scratch_pml4e; | |
633 | ||
634 | scratch_pml4e = gen8_pml4e_encode(px_dma(vm->scratch_pdp), | |
635 | I915_CACHE_LLC); | |
636 | ||
637 | fill_px(vm->dev, pml4, scratch_pml4e); | |
638 | } | |
639 | ||
762d9936 MT |
640 | static void |
641 | gen8_setup_page_directory(struct i915_hw_ppgtt *ppgtt, | |
642 | struct i915_page_directory_pointer *pdp, | |
643 | struct i915_page_directory *pd, | |
644 | int index) | |
645 | { | |
646 | gen8_ppgtt_pdpe_t *page_directorypo; | |
647 | ||
648 | if (!USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) | |
649 | return; | |
650 | ||
651 | page_directorypo = kmap_px(pdp); | |
652 | page_directorypo[index] = gen8_pdpe_encode(px_dma(pd), I915_CACHE_LLC); | |
653 | kunmap_px(ppgtt, page_directorypo); | |
654 | } | |
655 | ||
656 | static void | |
657 | gen8_setup_page_directory_pointer(struct i915_hw_ppgtt *ppgtt, | |
658 | struct i915_pml4 *pml4, | |
659 | struct i915_page_directory_pointer *pdp, | |
660 | int index) | |
661 | { | |
662 | gen8_ppgtt_pml4e_t *pagemap = kmap_px(pml4); | |
663 | ||
664 | WARN_ON(!USES_FULL_48BIT_PPGTT(ppgtt->base.dev)); | |
665 | pagemap[index] = gen8_pml4e_encode(px_dma(pdp), I915_CACHE_LLC); | |
666 | kunmap_px(ppgtt, pagemap); | |
6ac18502 MT |
667 | } |
668 | ||
94e409c1 | 669 | /* Broadwell Page Directory Pointer Descriptors */ |
e85b26dc | 670 | static int gen8_write_pdp(struct drm_i915_gem_request *req, |
7cb6d7ac MT |
671 | unsigned entry, |
672 | dma_addr_t addr) | |
94e409c1 | 673 | { |
7e37f889 | 674 | struct intel_ring *ring = req->ring; |
4a570db5 | 675 | struct intel_engine_cs *engine = req->engine; |
94e409c1 BW |
676 | int ret; |
677 | ||
678 | BUG_ON(entry >= 4); | |
679 | ||
5fb9de1a | 680 | ret = intel_ring_begin(req, 6); |
94e409c1 BW |
681 | if (ret) |
682 | return ret; | |
683 | ||
b5321f30 CW |
684 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); |
685 | intel_ring_emit_reg(ring, GEN8_RING_PDP_UDW(engine, entry)); | |
686 | intel_ring_emit(ring, upper_32_bits(addr)); | |
687 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
688 | intel_ring_emit_reg(ring, GEN8_RING_PDP_LDW(engine, entry)); | |
689 | intel_ring_emit(ring, lower_32_bits(addr)); | |
690 | intel_ring_advance(ring); | |
94e409c1 BW |
691 | |
692 | return 0; | |
693 | } | |
694 | ||
2dba3239 MT |
695 | static int gen8_legacy_mm_switch(struct i915_hw_ppgtt *ppgtt, |
696 | struct drm_i915_gem_request *req) | |
94e409c1 | 697 | { |
eeb9488e | 698 | int i, ret; |
94e409c1 | 699 | |
7cb6d7ac | 700 | for (i = GEN8_LEGACY_PDPES - 1; i >= 0; i--) { |
d852c7bf MK |
701 | const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i); |
702 | ||
e85b26dc | 703 | ret = gen8_write_pdp(req, i, pd_daddr); |
eeb9488e BW |
704 | if (ret) |
705 | return ret; | |
94e409c1 | 706 | } |
d595bd4b | 707 | |
eeb9488e | 708 | return 0; |
94e409c1 BW |
709 | } |
710 | ||
2dba3239 MT |
711 | static int gen8_48b_mm_switch(struct i915_hw_ppgtt *ppgtt, |
712 | struct drm_i915_gem_request *req) | |
713 | { | |
714 | return gen8_write_pdp(req, 0, px_dma(&ppgtt->pml4)); | |
715 | } | |
716 | ||
f9b5b782 MT |
717 | static void gen8_ppgtt_clear_pte_range(struct i915_address_space *vm, |
718 | struct i915_page_directory_pointer *pdp, | |
719 | uint64_t start, | |
720 | uint64_t length, | |
721 | gen8_pte_t scratch_pte) | |
459108b8 | 722 | { |
e5716f55 | 723 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
f9b5b782 | 724 | gen8_pte_t *pt_vaddr; |
de5ba8eb MT |
725 | unsigned pdpe = gen8_pdpe_index(start); |
726 | unsigned pde = gen8_pde_index(start); | |
727 | unsigned pte = gen8_pte_index(start); | |
782f1495 | 728 | unsigned num_entries = length >> PAGE_SHIFT; |
459108b8 BW |
729 | unsigned last_pte, i; |
730 | ||
f9b5b782 MT |
731 | if (WARN_ON(!pdp)) |
732 | return; | |
459108b8 BW |
733 | |
734 | while (num_entries) { | |
ec565b3c MT |
735 | struct i915_page_directory *pd; |
736 | struct i915_page_table *pt; | |
06fda602 | 737 | |
d4ec9da0 | 738 | if (WARN_ON(!pdp->page_directory[pdpe])) |
00245266 | 739 | break; |
06fda602 | 740 | |
d4ec9da0 | 741 | pd = pdp->page_directory[pdpe]; |
06fda602 BW |
742 | |
743 | if (WARN_ON(!pd->page_table[pde])) | |
00245266 | 744 | break; |
06fda602 BW |
745 | |
746 | pt = pd->page_table[pde]; | |
747 | ||
567047be | 748 | if (WARN_ON(!px_page(pt))) |
00245266 | 749 | break; |
06fda602 | 750 | |
7ad47cf2 | 751 | last_pte = pte + num_entries; |
07749ef3 MT |
752 | if (last_pte > GEN8_PTES) |
753 | last_pte = GEN8_PTES; | |
459108b8 | 754 | |
d1c54acd | 755 | pt_vaddr = kmap_px(pt); |
459108b8 | 756 | |
7ad47cf2 | 757 | for (i = pte; i < last_pte; i++) { |
459108b8 | 758 | pt_vaddr[i] = scratch_pte; |
7ad47cf2 BW |
759 | num_entries--; |
760 | } | |
459108b8 | 761 | |
44a71024 | 762 | kunmap_px(ppgtt, pt_vaddr); |
459108b8 | 763 | |
7ad47cf2 | 764 | pte = 0; |
07749ef3 | 765 | if (++pde == I915_PDES) { |
de5ba8eb MT |
766 | if (++pdpe == I915_PDPES_PER_PDP(vm->dev)) |
767 | break; | |
7ad47cf2 BW |
768 | pde = 0; |
769 | } | |
459108b8 BW |
770 | } |
771 | } | |
772 | ||
f9b5b782 MT |
773 | static void gen8_ppgtt_clear_range(struct i915_address_space *vm, |
774 | uint64_t start, | |
775 | uint64_t length, | |
776 | bool use_scratch) | |
9df15b49 | 777 | { |
e5716f55 | 778 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
f9b5b782 MT |
779 | gen8_pte_t scratch_pte = gen8_pte_encode(px_dma(vm->scratch_page), |
780 | I915_CACHE_LLC, use_scratch); | |
781 | ||
de5ba8eb MT |
782 | if (!USES_FULL_48BIT_PPGTT(vm->dev)) { |
783 | gen8_ppgtt_clear_pte_range(vm, &ppgtt->pdp, start, length, | |
784 | scratch_pte); | |
785 | } else { | |
e8ebd8e2 | 786 | uint64_t pml4e; |
de5ba8eb MT |
787 | struct i915_page_directory_pointer *pdp; |
788 | ||
e8ebd8e2 | 789 | gen8_for_each_pml4e(pdp, &ppgtt->pml4, start, length, pml4e) { |
de5ba8eb MT |
790 | gen8_ppgtt_clear_pte_range(vm, pdp, start, length, |
791 | scratch_pte); | |
792 | } | |
793 | } | |
f9b5b782 MT |
794 | } |
795 | ||
796 | static void | |
797 | gen8_ppgtt_insert_pte_entries(struct i915_address_space *vm, | |
798 | struct i915_page_directory_pointer *pdp, | |
3387d433 | 799 | struct sg_page_iter *sg_iter, |
f9b5b782 MT |
800 | uint64_t start, |
801 | enum i915_cache_level cache_level) | |
802 | { | |
e5716f55 | 803 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
07749ef3 | 804 | gen8_pte_t *pt_vaddr; |
de5ba8eb MT |
805 | unsigned pdpe = gen8_pdpe_index(start); |
806 | unsigned pde = gen8_pde_index(start); | |
807 | unsigned pte = gen8_pte_index(start); | |
9df15b49 | 808 | |
6f1cc993 | 809 | pt_vaddr = NULL; |
7ad47cf2 | 810 | |
3387d433 | 811 | while (__sg_page_iter_next(sg_iter)) { |
d7b3de91 | 812 | if (pt_vaddr == NULL) { |
d4ec9da0 | 813 | struct i915_page_directory *pd = pdp->page_directory[pdpe]; |
ec565b3c | 814 | struct i915_page_table *pt = pd->page_table[pde]; |
d1c54acd | 815 | pt_vaddr = kmap_px(pt); |
d7b3de91 | 816 | } |
9df15b49 | 817 | |
7ad47cf2 | 818 | pt_vaddr[pte] = |
3387d433 | 819 | gen8_pte_encode(sg_page_iter_dma_address(sg_iter), |
6f1cc993 | 820 | cache_level, true); |
07749ef3 | 821 | if (++pte == GEN8_PTES) { |
d1c54acd | 822 | kunmap_px(ppgtt, pt_vaddr); |
6f1cc993 | 823 | pt_vaddr = NULL; |
07749ef3 | 824 | if (++pde == I915_PDES) { |
de5ba8eb MT |
825 | if (++pdpe == I915_PDPES_PER_PDP(vm->dev)) |
826 | break; | |
7ad47cf2 BW |
827 | pde = 0; |
828 | } | |
829 | pte = 0; | |
9df15b49 BW |
830 | } |
831 | } | |
d1c54acd MK |
832 | |
833 | if (pt_vaddr) | |
834 | kunmap_px(ppgtt, pt_vaddr); | |
9df15b49 BW |
835 | } |
836 | ||
f9b5b782 MT |
837 | static void gen8_ppgtt_insert_entries(struct i915_address_space *vm, |
838 | struct sg_table *pages, | |
839 | uint64_t start, | |
840 | enum i915_cache_level cache_level, | |
841 | u32 unused) | |
842 | { | |
e5716f55 | 843 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
3387d433 | 844 | struct sg_page_iter sg_iter; |
f9b5b782 | 845 | |
3387d433 | 846 | __sg_page_iter_start(&sg_iter, pages->sgl, sg_nents(pages->sgl), 0); |
de5ba8eb MT |
847 | |
848 | if (!USES_FULL_48BIT_PPGTT(vm->dev)) { | |
849 | gen8_ppgtt_insert_pte_entries(vm, &ppgtt->pdp, &sg_iter, start, | |
850 | cache_level); | |
851 | } else { | |
852 | struct i915_page_directory_pointer *pdp; | |
e8ebd8e2 | 853 | uint64_t pml4e; |
de5ba8eb MT |
854 | uint64_t length = (uint64_t)pages->orig_nents << PAGE_SHIFT; |
855 | ||
e8ebd8e2 | 856 | gen8_for_each_pml4e(pdp, &ppgtt->pml4, start, length, pml4e) { |
de5ba8eb MT |
857 | gen8_ppgtt_insert_pte_entries(vm, pdp, &sg_iter, |
858 | start, cache_level); | |
859 | } | |
860 | } | |
f9b5b782 MT |
861 | } |
862 | ||
f37c0505 MT |
863 | static void gen8_free_page_tables(struct drm_device *dev, |
864 | struct i915_page_directory *pd) | |
7ad47cf2 BW |
865 | { |
866 | int i; | |
867 | ||
567047be | 868 | if (!px_page(pd)) |
7ad47cf2 BW |
869 | return; |
870 | ||
33c8819f | 871 | for_each_set_bit(i, pd->used_pdes, I915_PDES) { |
06fda602 BW |
872 | if (WARN_ON(!pd->page_table[i])) |
873 | continue; | |
7ad47cf2 | 874 | |
a08e111a | 875 | free_pt(dev, pd->page_table[i]); |
06fda602 BW |
876 | pd->page_table[i] = NULL; |
877 | } | |
d7b3de91 BW |
878 | } |
879 | ||
8776f02b MK |
880 | static int gen8_init_scratch(struct i915_address_space *vm) |
881 | { | |
882 | struct drm_device *dev = vm->dev; | |
64c050db | 883 | int ret; |
8776f02b MK |
884 | |
885 | vm->scratch_page = alloc_scratch_page(dev); | |
886 | if (IS_ERR(vm->scratch_page)) | |
887 | return PTR_ERR(vm->scratch_page); | |
888 | ||
889 | vm->scratch_pt = alloc_pt(dev); | |
890 | if (IS_ERR(vm->scratch_pt)) { | |
64c050db MA |
891 | ret = PTR_ERR(vm->scratch_pt); |
892 | goto free_scratch_page; | |
8776f02b MK |
893 | } |
894 | ||
895 | vm->scratch_pd = alloc_pd(dev); | |
896 | if (IS_ERR(vm->scratch_pd)) { | |
64c050db MA |
897 | ret = PTR_ERR(vm->scratch_pd); |
898 | goto free_pt; | |
8776f02b MK |
899 | } |
900 | ||
69ab76fd MT |
901 | if (USES_FULL_48BIT_PPGTT(dev)) { |
902 | vm->scratch_pdp = alloc_pdp(dev); | |
903 | if (IS_ERR(vm->scratch_pdp)) { | |
64c050db MA |
904 | ret = PTR_ERR(vm->scratch_pdp); |
905 | goto free_pd; | |
69ab76fd MT |
906 | } |
907 | } | |
908 | ||
8776f02b MK |
909 | gen8_initialize_pt(vm, vm->scratch_pt); |
910 | gen8_initialize_pd(vm, vm->scratch_pd); | |
69ab76fd MT |
911 | if (USES_FULL_48BIT_PPGTT(dev)) |
912 | gen8_initialize_pdp(vm, vm->scratch_pdp); | |
8776f02b MK |
913 | |
914 | return 0; | |
64c050db MA |
915 | |
916 | free_pd: | |
917 | free_pd(dev, vm->scratch_pd); | |
918 | free_pt: | |
919 | free_pt(dev, vm->scratch_pt); | |
920 | free_scratch_page: | |
921 | free_scratch_page(dev, vm->scratch_page); | |
922 | ||
923 | return ret; | |
8776f02b MK |
924 | } |
925 | ||
650da34c ZL |
926 | static int gen8_ppgtt_notify_vgt(struct i915_hw_ppgtt *ppgtt, bool create) |
927 | { | |
928 | enum vgt_g2v_type msg; | |
df28564d | 929 | struct drm_i915_private *dev_priv = to_i915(ppgtt->base.dev); |
650da34c ZL |
930 | int i; |
931 | ||
df28564d | 932 | if (USES_FULL_48BIT_PPGTT(dev_priv)) { |
650da34c ZL |
933 | u64 daddr = px_dma(&ppgtt->pml4); |
934 | ||
ab75bb5d VS |
935 | I915_WRITE(vgtif_reg(pdp[0].lo), lower_32_bits(daddr)); |
936 | I915_WRITE(vgtif_reg(pdp[0].hi), upper_32_bits(daddr)); | |
650da34c ZL |
937 | |
938 | msg = (create ? VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE : | |
939 | VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY); | |
940 | } else { | |
941 | for (i = 0; i < GEN8_LEGACY_PDPES; i++) { | |
942 | u64 daddr = i915_page_dir_dma_addr(ppgtt, i); | |
943 | ||
ab75bb5d VS |
944 | I915_WRITE(vgtif_reg(pdp[i].lo), lower_32_bits(daddr)); |
945 | I915_WRITE(vgtif_reg(pdp[i].hi), upper_32_bits(daddr)); | |
650da34c ZL |
946 | } |
947 | ||
948 | msg = (create ? VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE : | |
949 | VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY); | |
950 | } | |
951 | ||
952 | I915_WRITE(vgtif_reg(g2v_notify), msg); | |
953 | ||
954 | return 0; | |
955 | } | |
956 | ||
8776f02b MK |
957 | static void gen8_free_scratch(struct i915_address_space *vm) |
958 | { | |
959 | struct drm_device *dev = vm->dev; | |
960 | ||
69ab76fd MT |
961 | if (USES_FULL_48BIT_PPGTT(dev)) |
962 | free_pdp(dev, vm->scratch_pdp); | |
8776f02b MK |
963 | free_pd(dev, vm->scratch_pd); |
964 | free_pt(dev, vm->scratch_pt); | |
965 | free_scratch_page(dev, vm->scratch_page); | |
966 | } | |
967 | ||
762d9936 MT |
968 | static void gen8_ppgtt_cleanup_3lvl(struct drm_device *dev, |
969 | struct i915_page_directory_pointer *pdp) | |
b45a6715 BW |
970 | { |
971 | int i; | |
972 | ||
d4ec9da0 MT |
973 | for_each_set_bit(i, pdp->used_pdpes, I915_PDPES_PER_PDP(dev)) { |
974 | if (WARN_ON(!pdp->page_directory[i])) | |
06fda602 BW |
975 | continue; |
976 | ||
d4ec9da0 MT |
977 | gen8_free_page_tables(dev, pdp->page_directory[i]); |
978 | free_pd(dev, pdp->page_directory[i]); | |
7ad47cf2 | 979 | } |
69876bed | 980 | |
d4ec9da0 | 981 | free_pdp(dev, pdp); |
762d9936 MT |
982 | } |
983 | ||
984 | static void gen8_ppgtt_cleanup_4lvl(struct i915_hw_ppgtt *ppgtt) | |
985 | { | |
986 | int i; | |
987 | ||
988 | for_each_set_bit(i, ppgtt->pml4.used_pml4es, GEN8_PML4ES_PER_PML4) { | |
989 | if (WARN_ON(!ppgtt->pml4.pdps[i])) | |
990 | continue; | |
991 | ||
992 | gen8_ppgtt_cleanup_3lvl(ppgtt->base.dev, ppgtt->pml4.pdps[i]); | |
993 | } | |
994 | ||
995 | cleanup_px(ppgtt->base.dev, &ppgtt->pml4); | |
996 | } | |
997 | ||
998 | static void gen8_ppgtt_cleanup(struct i915_address_space *vm) | |
999 | { | |
e5716f55 | 1000 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
762d9936 | 1001 | |
c033666a | 1002 | if (intel_vgpu_active(to_i915(vm->dev))) |
650da34c ZL |
1003 | gen8_ppgtt_notify_vgt(ppgtt, false); |
1004 | ||
762d9936 MT |
1005 | if (!USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) |
1006 | gen8_ppgtt_cleanup_3lvl(ppgtt->base.dev, &ppgtt->pdp); | |
1007 | else | |
1008 | gen8_ppgtt_cleanup_4lvl(ppgtt); | |
d4ec9da0 | 1009 | |
8776f02b | 1010 | gen8_free_scratch(vm); |
b45a6715 BW |
1011 | } |
1012 | ||
d7b2633d MT |
1013 | /** |
1014 | * gen8_ppgtt_alloc_pagetabs() - Allocate page tables for VA range. | |
d4ec9da0 MT |
1015 | * @vm: Master vm structure. |
1016 | * @pd: Page directory for this address range. | |
d7b2633d | 1017 | * @start: Starting virtual address to begin allocations. |
d4ec9da0 | 1018 | * @length: Size of the allocations. |
d7b2633d MT |
1019 | * @new_pts: Bitmap set by function with new allocations. Likely used by the |
1020 | * caller to free on error. | |
1021 | * | |
1022 | * Allocate the required number of page tables. Extremely similar to | |
1023 | * gen8_ppgtt_alloc_page_directories(). The main difference is here we are limited by | |
1024 | * the page directory boundary (instead of the page directory pointer). That | |
1025 | * boundary is 1GB virtual. Therefore, unlike gen8_ppgtt_alloc_page_directories(), it is | |
1026 | * possible, and likely that the caller will need to use multiple calls of this | |
1027 | * function to achieve the appropriate allocation. | |
1028 | * | |
1029 | * Return: 0 if success; negative error code otherwise. | |
1030 | */ | |
d4ec9da0 | 1031 | static int gen8_ppgtt_alloc_pagetabs(struct i915_address_space *vm, |
e5815a2e | 1032 | struct i915_page_directory *pd, |
5441f0cb | 1033 | uint64_t start, |
d7b2633d MT |
1034 | uint64_t length, |
1035 | unsigned long *new_pts) | |
bf2b4ed2 | 1036 | { |
d4ec9da0 | 1037 | struct drm_device *dev = vm->dev; |
d7b2633d | 1038 | struct i915_page_table *pt; |
5441f0cb | 1039 | uint32_t pde; |
bf2b4ed2 | 1040 | |
e8ebd8e2 | 1041 | gen8_for_each_pde(pt, pd, start, length, pde) { |
d7b2633d | 1042 | /* Don't reallocate page tables */ |
6ac18502 | 1043 | if (test_bit(pde, pd->used_pdes)) { |
d7b2633d | 1044 | /* Scratch is never allocated this way */ |
d4ec9da0 | 1045 | WARN_ON(pt == vm->scratch_pt); |
d7b2633d MT |
1046 | continue; |
1047 | } | |
1048 | ||
8a1ebd74 | 1049 | pt = alloc_pt(dev); |
d7b2633d | 1050 | if (IS_ERR(pt)) |
5441f0cb MT |
1051 | goto unwind_out; |
1052 | ||
d4ec9da0 | 1053 | gen8_initialize_pt(vm, pt); |
d7b2633d | 1054 | pd->page_table[pde] = pt; |
966082c9 | 1055 | __set_bit(pde, new_pts); |
4c06ec8d | 1056 | trace_i915_page_table_entry_alloc(vm, pde, start, GEN8_PDE_SHIFT); |
7ad47cf2 BW |
1057 | } |
1058 | ||
bf2b4ed2 | 1059 | return 0; |
7ad47cf2 BW |
1060 | |
1061 | unwind_out: | |
d7b2633d | 1062 | for_each_set_bit(pde, new_pts, I915_PDES) |
a08e111a | 1063 | free_pt(dev, pd->page_table[pde]); |
7ad47cf2 | 1064 | |
d7b3de91 | 1065 | return -ENOMEM; |
bf2b4ed2 BW |
1066 | } |
1067 | ||
d7b2633d MT |
1068 | /** |
1069 | * gen8_ppgtt_alloc_page_directories() - Allocate page directories for VA range. | |
d4ec9da0 | 1070 | * @vm: Master vm structure. |
d7b2633d MT |
1071 | * @pdp: Page directory pointer for this address range. |
1072 | * @start: Starting virtual address to begin allocations. | |
d4ec9da0 MT |
1073 | * @length: Size of the allocations. |
1074 | * @new_pds: Bitmap set by function with new allocations. Likely used by the | |
d7b2633d MT |
1075 | * caller to free on error. |
1076 | * | |
1077 | * Allocate the required number of page directories starting at the pde index of | |
1078 | * @start, and ending at the pde index @start + @length. This function will skip | |
1079 | * over already allocated page directories within the range, and only allocate | |
1080 | * new ones, setting the appropriate pointer within the pdp as well as the | |
1081 | * correct position in the bitmap @new_pds. | |
1082 | * | |
1083 | * The function will only allocate the pages within the range for a give page | |
1084 | * directory pointer. In other words, if @start + @length straddles a virtually | |
1085 | * addressed PDP boundary (512GB for 4k pages), there will be more allocations | |
1086 | * required by the caller, This is not currently possible, and the BUG in the | |
1087 | * code will prevent it. | |
1088 | * | |
1089 | * Return: 0 if success; negative error code otherwise. | |
1090 | */ | |
d4ec9da0 MT |
1091 | static int |
1092 | gen8_ppgtt_alloc_page_directories(struct i915_address_space *vm, | |
1093 | struct i915_page_directory_pointer *pdp, | |
1094 | uint64_t start, | |
1095 | uint64_t length, | |
1096 | unsigned long *new_pds) | |
bf2b4ed2 | 1097 | { |
d4ec9da0 | 1098 | struct drm_device *dev = vm->dev; |
d7b2633d | 1099 | struct i915_page_directory *pd; |
69876bed | 1100 | uint32_t pdpe; |
6ac18502 | 1101 | uint32_t pdpes = I915_PDPES_PER_PDP(dev); |
69876bed | 1102 | |
6ac18502 | 1103 | WARN_ON(!bitmap_empty(new_pds, pdpes)); |
d7b2633d | 1104 | |
e8ebd8e2 | 1105 | gen8_for_each_pdpe(pd, pdp, start, length, pdpe) { |
6ac18502 | 1106 | if (test_bit(pdpe, pdp->used_pdpes)) |
d7b2633d | 1107 | continue; |
33c8819f | 1108 | |
8a1ebd74 | 1109 | pd = alloc_pd(dev); |
d7b2633d | 1110 | if (IS_ERR(pd)) |
d7b3de91 | 1111 | goto unwind_out; |
69876bed | 1112 | |
d4ec9da0 | 1113 | gen8_initialize_pd(vm, pd); |
d7b2633d | 1114 | pdp->page_directory[pdpe] = pd; |
966082c9 | 1115 | __set_bit(pdpe, new_pds); |
4c06ec8d | 1116 | trace_i915_page_directory_entry_alloc(vm, pdpe, start, GEN8_PDPE_SHIFT); |
d7b3de91 BW |
1117 | } |
1118 | ||
bf2b4ed2 | 1119 | return 0; |
d7b3de91 BW |
1120 | |
1121 | unwind_out: | |
6ac18502 | 1122 | for_each_set_bit(pdpe, new_pds, pdpes) |
a08e111a | 1123 | free_pd(dev, pdp->page_directory[pdpe]); |
d7b3de91 BW |
1124 | |
1125 | return -ENOMEM; | |
bf2b4ed2 BW |
1126 | } |
1127 | ||
762d9936 MT |
1128 | /** |
1129 | * gen8_ppgtt_alloc_page_dirpointers() - Allocate pdps for VA range. | |
1130 | * @vm: Master vm structure. | |
1131 | * @pml4: Page map level 4 for this address range. | |
1132 | * @start: Starting virtual address to begin allocations. | |
1133 | * @length: Size of the allocations. | |
1134 | * @new_pdps: Bitmap set by function with new allocations. Likely used by the | |
1135 | * caller to free on error. | |
1136 | * | |
1137 | * Allocate the required number of page directory pointers. Extremely similar to | |
1138 | * gen8_ppgtt_alloc_page_directories() and gen8_ppgtt_alloc_pagetabs(). | |
1139 | * The main difference is here we are limited by the pml4 boundary (instead of | |
1140 | * the page directory pointer). | |
1141 | * | |
1142 | * Return: 0 if success; negative error code otherwise. | |
1143 | */ | |
1144 | static int | |
1145 | gen8_ppgtt_alloc_page_dirpointers(struct i915_address_space *vm, | |
1146 | struct i915_pml4 *pml4, | |
1147 | uint64_t start, | |
1148 | uint64_t length, | |
1149 | unsigned long *new_pdps) | |
1150 | { | |
1151 | struct drm_device *dev = vm->dev; | |
1152 | struct i915_page_directory_pointer *pdp; | |
762d9936 MT |
1153 | uint32_t pml4e; |
1154 | ||
1155 | WARN_ON(!bitmap_empty(new_pdps, GEN8_PML4ES_PER_PML4)); | |
1156 | ||
e8ebd8e2 | 1157 | gen8_for_each_pml4e(pdp, pml4, start, length, pml4e) { |
762d9936 MT |
1158 | if (!test_bit(pml4e, pml4->used_pml4es)) { |
1159 | pdp = alloc_pdp(dev); | |
1160 | if (IS_ERR(pdp)) | |
1161 | goto unwind_out; | |
1162 | ||
69ab76fd | 1163 | gen8_initialize_pdp(vm, pdp); |
762d9936 MT |
1164 | pml4->pdps[pml4e] = pdp; |
1165 | __set_bit(pml4e, new_pdps); | |
1166 | trace_i915_page_directory_pointer_entry_alloc(vm, | |
1167 | pml4e, | |
1168 | start, | |
1169 | GEN8_PML4E_SHIFT); | |
1170 | } | |
1171 | } | |
1172 | ||
1173 | return 0; | |
1174 | ||
1175 | unwind_out: | |
1176 | for_each_set_bit(pml4e, new_pdps, GEN8_PML4ES_PER_PML4) | |
1177 | free_pdp(dev, pml4->pdps[pml4e]); | |
1178 | ||
1179 | return -ENOMEM; | |
1180 | } | |
1181 | ||
d7b2633d | 1182 | static void |
3a41a05d | 1183 | free_gen8_temp_bitmaps(unsigned long *new_pds, unsigned long *new_pts) |
d7b2633d | 1184 | { |
d7b2633d MT |
1185 | kfree(new_pts); |
1186 | kfree(new_pds); | |
1187 | } | |
1188 | ||
1189 | /* Fills in the page directory bitmap, and the array of page tables bitmap. Both | |
1190 | * of these are based on the number of PDPEs in the system. | |
1191 | */ | |
1192 | static | |
1193 | int __must_check alloc_gen8_temp_bitmaps(unsigned long **new_pds, | |
3a41a05d | 1194 | unsigned long **new_pts, |
6ac18502 | 1195 | uint32_t pdpes) |
d7b2633d | 1196 | { |
d7b2633d | 1197 | unsigned long *pds; |
3a41a05d | 1198 | unsigned long *pts; |
d7b2633d | 1199 | |
3a41a05d | 1200 | pds = kcalloc(BITS_TO_LONGS(pdpes), sizeof(unsigned long), GFP_TEMPORARY); |
d7b2633d MT |
1201 | if (!pds) |
1202 | return -ENOMEM; | |
1203 | ||
3a41a05d MW |
1204 | pts = kcalloc(pdpes, BITS_TO_LONGS(I915_PDES) * sizeof(unsigned long), |
1205 | GFP_TEMPORARY); | |
1206 | if (!pts) | |
1207 | goto err_out; | |
d7b2633d MT |
1208 | |
1209 | *new_pds = pds; | |
1210 | *new_pts = pts; | |
1211 | ||
1212 | return 0; | |
1213 | ||
1214 | err_out: | |
3a41a05d | 1215 | free_gen8_temp_bitmaps(pds, pts); |
d7b2633d MT |
1216 | return -ENOMEM; |
1217 | } | |
1218 | ||
5b7e4c9c MK |
1219 | /* PDE TLBs are a pain to invalidate on GEN8+. When we modify |
1220 | * the page table structures, we mark them dirty so that | |
1221 | * context switching/execlist queuing code takes extra steps | |
1222 | * to ensure that tlbs are flushed. | |
1223 | */ | |
1224 | static void mark_tlbs_dirty(struct i915_hw_ppgtt *ppgtt) | |
1225 | { | |
1226 | ppgtt->pd_dirty_rings = INTEL_INFO(ppgtt->base.dev)->ring_mask; | |
1227 | } | |
1228 | ||
762d9936 MT |
1229 | static int gen8_alloc_va_range_3lvl(struct i915_address_space *vm, |
1230 | struct i915_page_directory_pointer *pdp, | |
1231 | uint64_t start, | |
1232 | uint64_t length) | |
bf2b4ed2 | 1233 | { |
e5716f55 | 1234 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
3a41a05d | 1235 | unsigned long *new_page_dirs, *new_page_tables; |
d4ec9da0 | 1236 | struct drm_device *dev = vm->dev; |
5441f0cb | 1237 | struct i915_page_directory *pd; |
33c8819f MT |
1238 | const uint64_t orig_start = start; |
1239 | const uint64_t orig_length = length; | |
5441f0cb | 1240 | uint32_t pdpe; |
d4ec9da0 | 1241 | uint32_t pdpes = I915_PDPES_PER_PDP(dev); |
bf2b4ed2 BW |
1242 | int ret; |
1243 | ||
d7b2633d MT |
1244 | /* Wrap is never okay since we can only represent 48b, and we don't |
1245 | * actually use the other side of the canonical address space. | |
1246 | */ | |
1247 | if (WARN_ON(start + length < start)) | |
a05d80ee MK |
1248 | return -ENODEV; |
1249 | ||
d4ec9da0 | 1250 | if (WARN_ON(start + length > vm->total)) |
a05d80ee | 1251 | return -ENODEV; |
d7b2633d | 1252 | |
6ac18502 | 1253 | ret = alloc_gen8_temp_bitmaps(&new_page_dirs, &new_page_tables, pdpes); |
bf2b4ed2 BW |
1254 | if (ret) |
1255 | return ret; | |
1256 | ||
d7b2633d | 1257 | /* Do the allocations first so we can easily bail out */ |
d4ec9da0 MT |
1258 | ret = gen8_ppgtt_alloc_page_directories(vm, pdp, start, length, |
1259 | new_page_dirs); | |
d7b2633d | 1260 | if (ret) { |
3a41a05d | 1261 | free_gen8_temp_bitmaps(new_page_dirs, new_page_tables); |
d7b2633d MT |
1262 | return ret; |
1263 | } | |
1264 | ||
1265 | /* For every page directory referenced, allocate page tables */ | |
e8ebd8e2 | 1266 | gen8_for_each_pdpe(pd, pdp, start, length, pdpe) { |
d4ec9da0 | 1267 | ret = gen8_ppgtt_alloc_pagetabs(vm, pd, start, length, |
3a41a05d | 1268 | new_page_tables + pdpe * BITS_TO_LONGS(I915_PDES)); |
5441f0cb MT |
1269 | if (ret) |
1270 | goto err_out; | |
5441f0cb MT |
1271 | } |
1272 | ||
33c8819f MT |
1273 | start = orig_start; |
1274 | length = orig_length; | |
1275 | ||
d7b2633d MT |
1276 | /* Allocations have completed successfully, so set the bitmaps, and do |
1277 | * the mappings. */ | |
e8ebd8e2 | 1278 | gen8_for_each_pdpe(pd, pdp, start, length, pdpe) { |
d1c54acd | 1279 | gen8_pde_t *const page_directory = kmap_px(pd); |
33c8819f | 1280 | struct i915_page_table *pt; |
09120d4e | 1281 | uint64_t pd_len = length; |
33c8819f MT |
1282 | uint64_t pd_start = start; |
1283 | uint32_t pde; | |
1284 | ||
d7b2633d MT |
1285 | /* Every pd should be allocated, we just did that above. */ |
1286 | WARN_ON(!pd); | |
1287 | ||
e8ebd8e2 | 1288 | gen8_for_each_pde(pt, pd, pd_start, pd_len, pde) { |
d7b2633d MT |
1289 | /* Same reasoning as pd */ |
1290 | WARN_ON(!pt); | |
1291 | WARN_ON(!pd_len); | |
1292 | WARN_ON(!gen8_pte_count(pd_start, pd_len)); | |
1293 | ||
1294 | /* Set our used ptes within the page table */ | |
1295 | bitmap_set(pt->used_ptes, | |
1296 | gen8_pte_index(pd_start), | |
1297 | gen8_pte_count(pd_start, pd_len)); | |
1298 | ||
1299 | /* Our pde is now pointing to the pagetable, pt */ | |
966082c9 | 1300 | __set_bit(pde, pd->used_pdes); |
d7b2633d MT |
1301 | |
1302 | /* Map the PDE to the page table */ | |
fe36f55d MK |
1303 | page_directory[pde] = gen8_pde_encode(px_dma(pt), |
1304 | I915_CACHE_LLC); | |
4c06ec8d MT |
1305 | trace_i915_page_table_entry_map(&ppgtt->base, pde, pt, |
1306 | gen8_pte_index(start), | |
1307 | gen8_pte_count(start, length), | |
1308 | GEN8_PTES); | |
d7b2633d MT |
1309 | |
1310 | /* NB: We haven't yet mapped ptes to pages. At this | |
1311 | * point we're still relying on insert_entries() */ | |
33c8819f | 1312 | } |
d7b2633d | 1313 | |
d1c54acd | 1314 | kunmap_px(ppgtt, page_directory); |
d4ec9da0 | 1315 | __set_bit(pdpe, pdp->used_pdpes); |
762d9936 | 1316 | gen8_setup_page_directory(ppgtt, pdp, pd, pdpe); |
33c8819f MT |
1317 | } |
1318 | ||
3a41a05d | 1319 | free_gen8_temp_bitmaps(new_page_dirs, new_page_tables); |
5b7e4c9c | 1320 | mark_tlbs_dirty(ppgtt); |
d7b3de91 | 1321 | return 0; |
bf2b4ed2 | 1322 | |
d7b3de91 | 1323 | err_out: |
d7b2633d | 1324 | while (pdpe--) { |
e8ebd8e2 DG |
1325 | unsigned long temp; |
1326 | ||
3a41a05d MW |
1327 | for_each_set_bit(temp, new_page_tables + pdpe * |
1328 | BITS_TO_LONGS(I915_PDES), I915_PDES) | |
d4ec9da0 | 1329 | free_pt(dev, pdp->page_directory[pdpe]->page_table[temp]); |
d7b2633d MT |
1330 | } |
1331 | ||
6ac18502 | 1332 | for_each_set_bit(pdpe, new_page_dirs, pdpes) |
d4ec9da0 | 1333 | free_pd(dev, pdp->page_directory[pdpe]); |
d7b2633d | 1334 | |
3a41a05d | 1335 | free_gen8_temp_bitmaps(new_page_dirs, new_page_tables); |
5b7e4c9c | 1336 | mark_tlbs_dirty(ppgtt); |
bf2b4ed2 BW |
1337 | return ret; |
1338 | } | |
1339 | ||
762d9936 MT |
1340 | static int gen8_alloc_va_range_4lvl(struct i915_address_space *vm, |
1341 | struct i915_pml4 *pml4, | |
1342 | uint64_t start, | |
1343 | uint64_t length) | |
1344 | { | |
1345 | DECLARE_BITMAP(new_pdps, GEN8_PML4ES_PER_PML4); | |
e5716f55 | 1346 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
762d9936 | 1347 | struct i915_page_directory_pointer *pdp; |
e8ebd8e2 | 1348 | uint64_t pml4e; |
762d9936 MT |
1349 | int ret = 0; |
1350 | ||
1351 | /* Do the pml4 allocations first, so we don't need to track the newly | |
1352 | * allocated tables below the pdp */ | |
1353 | bitmap_zero(new_pdps, GEN8_PML4ES_PER_PML4); | |
1354 | ||
1355 | /* The pagedirectory and pagetable allocations are done in the shared 3 | |
1356 | * and 4 level code. Just allocate the pdps. | |
1357 | */ | |
1358 | ret = gen8_ppgtt_alloc_page_dirpointers(vm, pml4, start, length, | |
1359 | new_pdps); | |
1360 | if (ret) | |
1361 | return ret; | |
1362 | ||
1363 | WARN(bitmap_weight(new_pdps, GEN8_PML4ES_PER_PML4) > 2, | |
1364 | "The allocation has spanned more than 512GB. " | |
1365 | "It is highly likely this is incorrect."); | |
1366 | ||
e8ebd8e2 | 1367 | gen8_for_each_pml4e(pdp, pml4, start, length, pml4e) { |
762d9936 MT |
1368 | WARN_ON(!pdp); |
1369 | ||
1370 | ret = gen8_alloc_va_range_3lvl(vm, pdp, start, length); | |
1371 | if (ret) | |
1372 | goto err_out; | |
1373 | ||
1374 | gen8_setup_page_directory_pointer(ppgtt, pml4, pdp, pml4e); | |
1375 | } | |
1376 | ||
1377 | bitmap_or(pml4->used_pml4es, new_pdps, pml4->used_pml4es, | |
1378 | GEN8_PML4ES_PER_PML4); | |
1379 | ||
1380 | return 0; | |
1381 | ||
1382 | err_out: | |
1383 | for_each_set_bit(pml4e, new_pdps, GEN8_PML4ES_PER_PML4) | |
1384 | gen8_ppgtt_cleanup_3lvl(vm->dev, pml4->pdps[pml4e]); | |
1385 | ||
1386 | return ret; | |
1387 | } | |
1388 | ||
1389 | static int gen8_alloc_va_range(struct i915_address_space *vm, | |
1390 | uint64_t start, uint64_t length) | |
1391 | { | |
e5716f55 | 1392 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
762d9936 MT |
1393 | |
1394 | if (USES_FULL_48BIT_PPGTT(vm->dev)) | |
1395 | return gen8_alloc_va_range_4lvl(vm, &ppgtt->pml4, start, length); | |
1396 | else | |
1397 | return gen8_alloc_va_range_3lvl(vm, &ppgtt->pdp, start, length); | |
1398 | } | |
1399 | ||
ea91e401 MT |
1400 | static void gen8_dump_pdp(struct i915_page_directory_pointer *pdp, |
1401 | uint64_t start, uint64_t length, | |
1402 | gen8_pte_t scratch_pte, | |
1403 | struct seq_file *m) | |
1404 | { | |
1405 | struct i915_page_directory *pd; | |
ea91e401 MT |
1406 | uint32_t pdpe; |
1407 | ||
e8ebd8e2 | 1408 | gen8_for_each_pdpe(pd, pdp, start, length, pdpe) { |
ea91e401 MT |
1409 | struct i915_page_table *pt; |
1410 | uint64_t pd_len = length; | |
1411 | uint64_t pd_start = start; | |
1412 | uint32_t pde; | |
1413 | ||
1414 | if (!test_bit(pdpe, pdp->used_pdpes)) | |
1415 | continue; | |
1416 | ||
1417 | seq_printf(m, "\tPDPE #%d\n", pdpe); | |
e8ebd8e2 | 1418 | gen8_for_each_pde(pt, pd, pd_start, pd_len, pde) { |
ea91e401 MT |
1419 | uint32_t pte; |
1420 | gen8_pte_t *pt_vaddr; | |
1421 | ||
1422 | if (!test_bit(pde, pd->used_pdes)) | |
1423 | continue; | |
1424 | ||
1425 | pt_vaddr = kmap_px(pt); | |
1426 | for (pte = 0; pte < GEN8_PTES; pte += 4) { | |
1427 | uint64_t va = | |
1428 | (pdpe << GEN8_PDPE_SHIFT) | | |
1429 | (pde << GEN8_PDE_SHIFT) | | |
1430 | (pte << GEN8_PTE_SHIFT); | |
1431 | int i; | |
1432 | bool found = false; | |
1433 | ||
1434 | for (i = 0; i < 4; i++) | |
1435 | if (pt_vaddr[pte + i] != scratch_pte) | |
1436 | found = true; | |
1437 | if (!found) | |
1438 | continue; | |
1439 | ||
1440 | seq_printf(m, "\t\t0x%llx [%03d,%03d,%04d]: =", va, pdpe, pde, pte); | |
1441 | for (i = 0; i < 4; i++) { | |
1442 | if (pt_vaddr[pte + i] != scratch_pte) | |
1443 | seq_printf(m, " %llx", pt_vaddr[pte + i]); | |
1444 | else | |
1445 | seq_puts(m, " SCRATCH "); | |
1446 | } | |
1447 | seq_puts(m, "\n"); | |
1448 | } | |
1449 | /* don't use kunmap_px, it could trigger | |
1450 | * an unnecessary flush. | |
1451 | */ | |
1452 | kunmap_atomic(pt_vaddr); | |
1453 | } | |
1454 | } | |
1455 | } | |
1456 | ||
1457 | static void gen8_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m) | |
1458 | { | |
1459 | struct i915_address_space *vm = &ppgtt->base; | |
1460 | uint64_t start = ppgtt->base.start; | |
1461 | uint64_t length = ppgtt->base.total; | |
1462 | gen8_pte_t scratch_pte = gen8_pte_encode(px_dma(vm->scratch_page), | |
1463 | I915_CACHE_LLC, true); | |
1464 | ||
1465 | if (!USES_FULL_48BIT_PPGTT(vm->dev)) { | |
1466 | gen8_dump_pdp(&ppgtt->pdp, start, length, scratch_pte, m); | |
1467 | } else { | |
e8ebd8e2 | 1468 | uint64_t pml4e; |
ea91e401 MT |
1469 | struct i915_pml4 *pml4 = &ppgtt->pml4; |
1470 | struct i915_page_directory_pointer *pdp; | |
1471 | ||
e8ebd8e2 | 1472 | gen8_for_each_pml4e(pdp, pml4, start, length, pml4e) { |
ea91e401 MT |
1473 | if (!test_bit(pml4e, pml4->used_pml4es)) |
1474 | continue; | |
1475 | ||
1476 | seq_printf(m, " PML4E #%llu\n", pml4e); | |
1477 | gen8_dump_pdp(pdp, start, length, scratch_pte, m); | |
1478 | } | |
1479 | } | |
1480 | } | |
1481 | ||
331f38e7 ZL |
1482 | static int gen8_preallocate_top_level_pdps(struct i915_hw_ppgtt *ppgtt) |
1483 | { | |
3a41a05d | 1484 | unsigned long *new_page_dirs, *new_page_tables; |
331f38e7 ZL |
1485 | uint32_t pdpes = I915_PDPES_PER_PDP(dev); |
1486 | int ret; | |
1487 | ||
1488 | /* We allocate temp bitmap for page tables for no gain | |
1489 | * but as this is for init only, lets keep the things simple | |
1490 | */ | |
1491 | ret = alloc_gen8_temp_bitmaps(&new_page_dirs, &new_page_tables, pdpes); | |
1492 | if (ret) | |
1493 | return ret; | |
1494 | ||
1495 | /* Allocate for all pdps regardless of how the ppgtt | |
1496 | * was defined. | |
1497 | */ | |
1498 | ret = gen8_ppgtt_alloc_page_directories(&ppgtt->base, &ppgtt->pdp, | |
1499 | 0, 1ULL << 32, | |
1500 | new_page_dirs); | |
1501 | if (!ret) | |
1502 | *ppgtt->pdp.used_pdpes = *new_page_dirs; | |
1503 | ||
3a41a05d | 1504 | free_gen8_temp_bitmaps(new_page_dirs, new_page_tables); |
331f38e7 ZL |
1505 | |
1506 | return ret; | |
1507 | } | |
1508 | ||
eb0b44ad | 1509 | /* |
f3a964b9 BW |
1510 | * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers |
1511 | * with a net effect resembling a 2-level page table in normal x86 terms. Each | |
1512 | * PDP represents 1GB of memory 4 * 512 * 512 * 4096 = 4GB legacy 32b address | |
1513 | * space. | |
37aca44a | 1514 | * |
f3a964b9 | 1515 | */ |
5c5f6457 | 1516 | static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt) |
37aca44a | 1517 | { |
8776f02b | 1518 | int ret; |
7cb6d7ac | 1519 | |
8776f02b MK |
1520 | ret = gen8_init_scratch(&ppgtt->base); |
1521 | if (ret) | |
1522 | return ret; | |
69876bed | 1523 | |
d7b2633d | 1524 | ppgtt->base.start = 0; |
d7b2633d | 1525 | ppgtt->base.cleanup = gen8_ppgtt_cleanup; |
5c5f6457 | 1526 | ppgtt->base.allocate_va_range = gen8_alloc_va_range; |
d7b2633d | 1527 | ppgtt->base.insert_entries = gen8_ppgtt_insert_entries; |
c7e16f22 | 1528 | ppgtt->base.clear_range = gen8_ppgtt_clear_range; |
777dc5bb DV |
1529 | ppgtt->base.unbind_vma = ppgtt_unbind_vma; |
1530 | ppgtt->base.bind_vma = ppgtt_bind_vma; | |
ea91e401 | 1531 | ppgtt->debug_dump = gen8_dump_ppgtt; |
d7b2633d | 1532 | |
762d9936 MT |
1533 | if (USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) { |
1534 | ret = setup_px(ppgtt->base.dev, &ppgtt->pml4); | |
1535 | if (ret) | |
1536 | goto free_scratch; | |
6ac18502 | 1537 | |
69ab76fd MT |
1538 | gen8_initialize_pml4(&ppgtt->base, &ppgtt->pml4); |
1539 | ||
762d9936 | 1540 | ppgtt->base.total = 1ULL << 48; |
2dba3239 | 1541 | ppgtt->switch_mm = gen8_48b_mm_switch; |
762d9936 | 1542 | } else { |
25f50337 | 1543 | ret = __pdp_init(ppgtt->base.dev, &ppgtt->pdp); |
81ba8aef MT |
1544 | if (ret) |
1545 | goto free_scratch; | |
1546 | ||
1547 | ppgtt->base.total = 1ULL << 32; | |
2dba3239 | 1548 | ppgtt->switch_mm = gen8_legacy_mm_switch; |
762d9936 MT |
1549 | trace_i915_page_directory_pointer_entry_alloc(&ppgtt->base, |
1550 | 0, 0, | |
1551 | GEN8_PML4E_SHIFT); | |
331f38e7 | 1552 | |
c033666a | 1553 | if (intel_vgpu_active(to_i915(ppgtt->base.dev))) { |
331f38e7 ZL |
1554 | ret = gen8_preallocate_top_level_pdps(ppgtt); |
1555 | if (ret) | |
1556 | goto free_scratch; | |
1557 | } | |
81ba8aef | 1558 | } |
6ac18502 | 1559 | |
c033666a | 1560 | if (intel_vgpu_active(to_i915(ppgtt->base.dev))) |
650da34c ZL |
1561 | gen8_ppgtt_notify_vgt(ppgtt, true); |
1562 | ||
d7b2633d | 1563 | return 0; |
6ac18502 MT |
1564 | |
1565 | free_scratch: | |
1566 | gen8_free_scratch(&ppgtt->base); | |
1567 | return ret; | |
d7b2633d MT |
1568 | } |
1569 | ||
87d60b63 BW |
1570 | static void gen6_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m) |
1571 | { | |
87d60b63 | 1572 | struct i915_address_space *vm = &ppgtt->base; |
09942c65 | 1573 | struct i915_page_table *unused; |
07749ef3 | 1574 | gen6_pte_t scratch_pte; |
87d60b63 | 1575 | uint32_t pd_entry; |
731f74c5 | 1576 | uint32_t pte, pde; |
09942c65 | 1577 | uint32_t start = ppgtt->base.start, length = ppgtt->base.total; |
87d60b63 | 1578 | |
79ab9370 MK |
1579 | scratch_pte = vm->pte_encode(px_dma(vm->scratch_page), |
1580 | I915_CACHE_LLC, true, 0); | |
87d60b63 | 1581 | |
731f74c5 | 1582 | gen6_for_each_pde(unused, &ppgtt->pd, start, length, pde) { |
87d60b63 | 1583 | u32 expected; |
07749ef3 | 1584 | gen6_pte_t *pt_vaddr; |
567047be | 1585 | const dma_addr_t pt_addr = px_dma(ppgtt->pd.page_table[pde]); |
09942c65 | 1586 | pd_entry = readl(ppgtt->pd_addr + pde); |
87d60b63 BW |
1587 | expected = (GEN6_PDE_ADDR_ENCODE(pt_addr) | GEN6_PDE_VALID); |
1588 | ||
1589 | if (pd_entry != expected) | |
1590 | seq_printf(m, "\tPDE #%d mismatch: Actual PDE: %x Expected PDE: %x\n", | |
1591 | pde, | |
1592 | pd_entry, | |
1593 | expected); | |
1594 | seq_printf(m, "\tPDE: %x\n", pd_entry); | |
1595 | ||
d1c54acd MK |
1596 | pt_vaddr = kmap_px(ppgtt->pd.page_table[pde]); |
1597 | ||
07749ef3 | 1598 | for (pte = 0; pte < GEN6_PTES; pte+=4) { |
87d60b63 | 1599 | unsigned long va = |
07749ef3 | 1600 | (pde * PAGE_SIZE * GEN6_PTES) + |
87d60b63 BW |
1601 | (pte * PAGE_SIZE); |
1602 | int i; | |
1603 | bool found = false; | |
1604 | for (i = 0; i < 4; i++) | |
1605 | if (pt_vaddr[pte + i] != scratch_pte) | |
1606 | found = true; | |
1607 | if (!found) | |
1608 | continue; | |
1609 | ||
1610 | seq_printf(m, "\t\t0x%lx [%03d,%04d]: =", va, pde, pte); | |
1611 | for (i = 0; i < 4; i++) { | |
1612 | if (pt_vaddr[pte + i] != scratch_pte) | |
1613 | seq_printf(m, " %08x", pt_vaddr[pte + i]); | |
1614 | else | |
1615 | seq_puts(m, " SCRATCH "); | |
1616 | } | |
1617 | seq_puts(m, "\n"); | |
1618 | } | |
d1c54acd | 1619 | kunmap_px(ppgtt, pt_vaddr); |
87d60b63 BW |
1620 | } |
1621 | } | |
1622 | ||
678d96fb | 1623 | /* Write pde (index) from the page directory @pd to the page table @pt */ |
ec565b3c MT |
1624 | static void gen6_write_pde(struct i915_page_directory *pd, |
1625 | const int pde, struct i915_page_table *pt) | |
6197349b | 1626 | { |
678d96fb BW |
1627 | /* Caller needs to make sure the write completes if necessary */ |
1628 | struct i915_hw_ppgtt *ppgtt = | |
1629 | container_of(pd, struct i915_hw_ppgtt, pd); | |
1630 | u32 pd_entry; | |
6197349b | 1631 | |
567047be | 1632 | pd_entry = GEN6_PDE_ADDR_ENCODE(px_dma(pt)); |
678d96fb | 1633 | pd_entry |= GEN6_PDE_VALID; |
6197349b | 1634 | |
678d96fb BW |
1635 | writel(pd_entry, ppgtt->pd_addr + pde); |
1636 | } | |
6197349b | 1637 | |
678d96fb BW |
1638 | /* Write all the page tables found in the ppgtt structure to incrementing page |
1639 | * directories. */ | |
1640 | static void gen6_write_page_range(struct drm_i915_private *dev_priv, | |
ec565b3c | 1641 | struct i915_page_directory *pd, |
678d96fb BW |
1642 | uint32_t start, uint32_t length) |
1643 | { | |
72e96d64 | 1644 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
ec565b3c | 1645 | struct i915_page_table *pt; |
731f74c5 | 1646 | uint32_t pde; |
678d96fb | 1647 | |
731f74c5 | 1648 | gen6_for_each_pde(pt, pd, start, length, pde) |
678d96fb BW |
1649 | gen6_write_pde(pd, pde, pt); |
1650 | ||
1651 | /* Make sure write is complete before other code can use this page | |
1652 | * table. Also require for WC mapped PTEs */ | |
72e96d64 | 1653 | readl(ggtt->gsm); |
3e302542 BW |
1654 | } |
1655 | ||
b4a74e3a | 1656 | static uint32_t get_pd_offset(struct i915_hw_ppgtt *ppgtt) |
3e302542 | 1657 | { |
44159ddb | 1658 | BUG_ON(ppgtt->pd.base.ggtt_offset & 0x3f); |
b4a74e3a | 1659 | |
44159ddb | 1660 | return (ppgtt->pd.base.ggtt_offset / 64) << 16; |
b4a74e3a BW |
1661 | } |
1662 | ||
90252e5c | 1663 | static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt, |
e85b26dc | 1664 | struct drm_i915_gem_request *req) |
90252e5c | 1665 | { |
7e37f889 | 1666 | struct intel_ring *ring = req->ring; |
4a570db5 | 1667 | struct intel_engine_cs *engine = req->engine; |
90252e5c BW |
1668 | int ret; |
1669 | ||
90252e5c | 1670 | /* NB: TLBs must be flushed and invalidated before a switch */ |
7c9cf4e3 | 1671 | ret = engine->emit_flush(req, EMIT_INVALIDATE | EMIT_FLUSH); |
90252e5c BW |
1672 | if (ret) |
1673 | return ret; | |
1674 | ||
5fb9de1a | 1675 | ret = intel_ring_begin(req, 6); |
90252e5c BW |
1676 | if (ret) |
1677 | return ret; | |
1678 | ||
b5321f30 CW |
1679 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2)); |
1680 | intel_ring_emit_reg(ring, RING_PP_DIR_DCLV(engine)); | |
1681 | intel_ring_emit(ring, PP_DIR_DCLV_2G); | |
1682 | intel_ring_emit_reg(ring, RING_PP_DIR_BASE(engine)); | |
1683 | intel_ring_emit(ring, get_pd_offset(ppgtt)); | |
1684 | intel_ring_emit(ring, MI_NOOP); | |
1685 | intel_ring_advance(ring); | |
90252e5c BW |
1686 | |
1687 | return 0; | |
1688 | } | |
1689 | ||
48a10389 | 1690 | static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt, |
e85b26dc | 1691 | struct drm_i915_gem_request *req) |
48a10389 | 1692 | { |
7e37f889 | 1693 | struct intel_ring *ring = req->ring; |
4a570db5 | 1694 | struct intel_engine_cs *engine = req->engine; |
48a10389 BW |
1695 | int ret; |
1696 | ||
48a10389 | 1697 | /* NB: TLBs must be flushed and invalidated before a switch */ |
7c9cf4e3 | 1698 | ret = engine->emit_flush(req, EMIT_INVALIDATE | EMIT_FLUSH); |
48a10389 BW |
1699 | if (ret) |
1700 | return ret; | |
1701 | ||
5fb9de1a | 1702 | ret = intel_ring_begin(req, 6); |
48a10389 BW |
1703 | if (ret) |
1704 | return ret; | |
1705 | ||
b5321f30 CW |
1706 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2)); |
1707 | intel_ring_emit_reg(ring, RING_PP_DIR_DCLV(engine)); | |
1708 | intel_ring_emit(ring, PP_DIR_DCLV_2G); | |
1709 | intel_ring_emit_reg(ring, RING_PP_DIR_BASE(engine)); | |
1710 | intel_ring_emit(ring, get_pd_offset(ppgtt)); | |
1711 | intel_ring_emit(ring, MI_NOOP); | |
1712 | intel_ring_advance(ring); | |
48a10389 | 1713 | |
90252e5c | 1714 | /* XXX: RCS is the only one to auto invalidate the TLBs? */ |
e2f80391 | 1715 | if (engine->id != RCS) { |
7c9cf4e3 | 1716 | ret = engine->emit_flush(req, EMIT_INVALIDATE | EMIT_FLUSH); |
90252e5c BW |
1717 | if (ret) |
1718 | return ret; | |
1719 | } | |
1720 | ||
48a10389 BW |
1721 | return 0; |
1722 | } | |
1723 | ||
eeb9488e | 1724 | static int gen6_mm_switch(struct i915_hw_ppgtt *ppgtt, |
e85b26dc | 1725 | struct drm_i915_gem_request *req) |
eeb9488e | 1726 | { |
4a570db5 | 1727 | struct intel_engine_cs *engine = req->engine; |
8eb95204 | 1728 | struct drm_i915_private *dev_priv = req->i915; |
48a10389 | 1729 | |
e2f80391 TU |
1730 | I915_WRITE(RING_PP_DIR_DCLV(engine), PP_DIR_DCLV_2G); |
1731 | I915_WRITE(RING_PP_DIR_BASE(engine), get_pd_offset(ppgtt)); | |
eeb9488e BW |
1732 | return 0; |
1733 | } | |
1734 | ||
82460d97 | 1735 | static void gen8_ppgtt_enable(struct drm_device *dev) |
eeb9488e | 1736 | { |
fac5e23e | 1737 | struct drm_i915_private *dev_priv = to_i915(dev); |
e2f80391 | 1738 | struct intel_engine_cs *engine; |
3e302542 | 1739 | |
b4ac5afc | 1740 | for_each_engine(engine, dev_priv) { |
2dba3239 | 1741 | u32 four_level = USES_FULL_48BIT_PPGTT(dev) ? GEN8_GFX_PPGTT_48B : 0; |
e2f80391 | 1742 | I915_WRITE(RING_MODE_GEN7(engine), |
2dba3239 | 1743 | _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE | four_level)); |
eeb9488e | 1744 | } |
eeb9488e | 1745 | } |
6197349b | 1746 | |
82460d97 | 1747 | static void gen7_ppgtt_enable(struct drm_device *dev) |
3e302542 | 1748 | { |
fac5e23e | 1749 | struct drm_i915_private *dev_priv = to_i915(dev); |
e2f80391 | 1750 | struct intel_engine_cs *engine; |
b4a74e3a | 1751 | uint32_t ecochk, ecobits; |
6197349b | 1752 | |
b4a74e3a BW |
1753 | ecobits = I915_READ(GAC_ECO_BITS); |
1754 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B); | |
a65c2fcd | 1755 | |
b4a74e3a BW |
1756 | ecochk = I915_READ(GAM_ECOCHK); |
1757 | if (IS_HASWELL(dev)) { | |
1758 | ecochk |= ECOCHK_PPGTT_WB_HSW; | |
1759 | } else { | |
1760 | ecochk |= ECOCHK_PPGTT_LLC_IVB; | |
1761 | ecochk &= ~ECOCHK_PPGTT_GFDT_IVB; | |
1762 | } | |
1763 | I915_WRITE(GAM_ECOCHK, ecochk); | |
a65c2fcd | 1764 | |
b4ac5afc | 1765 | for_each_engine(engine, dev_priv) { |
6197349b | 1766 | /* GFX_MODE is per-ring on gen7+ */ |
e2f80391 | 1767 | I915_WRITE(RING_MODE_GEN7(engine), |
b4a74e3a | 1768 | _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); |
6197349b | 1769 | } |
b4a74e3a | 1770 | } |
6197349b | 1771 | |
82460d97 | 1772 | static void gen6_ppgtt_enable(struct drm_device *dev) |
b4a74e3a | 1773 | { |
fac5e23e | 1774 | struct drm_i915_private *dev_priv = to_i915(dev); |
b4a74e3a | 1775 | uint32_t ecochk, gab_ctl, ecobits; |
a65c2fcd | 1776 | |
b4a74e3a BW |
1777 | ecobits = I915_READ(GAC_ECO_BITS); |
1778 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT | | |
1779 | ECOBITS_PPGTT_CACHE64B); | |
6197349b | 1780 | |
b4a74e3a BW |
1781 | gab_ctl = I915_READ(GAB_CTL); |
1782 | I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT); | |
1783 | ||
1784 | ecochk = I915_READ(GAM_ECOCHK); | |
1785 | I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B); | |
1786 | ||
1787 | I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
6197349b BW |
1788 | } |
1789 | ||
1d2a314c | 1790 | /* PPGTT support for Sandybdrige/Gen6 and later */ |
853ba5d2 | 1791 | static void gen6_ppgtt_clear_range(struct i915_address_space *vm, |
782f1495 BW |
1792 | uint64_t start, |
1793 | uint64_t length, | |
828c7908 | 1794 | bool use_scratch) |
1d2a314c | 1795 | { |
e5716f55 | 1796 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
07749ef3 | 1797 | gen6_pte_t *pt_vaddr, scratch_pte; |
782f1495 BW |
1798 | unsigned first_entry = start >> PAGE_SHIFT; |
1799 | unsigned num_entries = length >> PAGE_SHIFT; | |
07749ef3 MT |
1800 | unsigned act_pt = first_entry / GEN6_PTES; |
1801 | unsigned first_pte = first_entry % GEN6_PTES; | |
7bddb01f | 1802 | unsigned last_pte, i; |
1d2a314c | 1803 | |
c114f76a MK |
1804 | scratch_pte = vm->pte_encode(px_dma(vm->scratch_page), |
1805 | I915_CACHE_LLC, true, 0); | |
1d2a314c | 1806 | |
7bddb01f DV |
1807 | while (num_entries) { |
1808 | last_pte = first_pte + num_entries; | |
07749ef3 MT |
1809 | if (last_pte > GEN6_PTES) |
1810 | last_pte = GEN6_PTES; | |
7bddb01f | 1811 | |
d1c54acd | 1812 | pt_vaddr = kmap_px(ppgtt->pd.page_table[act_pt]); |
1d2a314c | 1813 | |
7bddb01f DV |
1814 | for (i = first_pte; i < last_pte; i++) |
1815 | pt_vaddr[i] = scratch_pte; | |
1d2a314c | 1816 | |
d1c54acd | 1817 | kunmap_px(ppgtt, pt_vaddr); |
1d2a314c | 1818 | |
7bddb01f DV |
1819 | num_entries -= last_pte - first_pte; |
1820 | first_pte = 0; | |
a15326a5 | 1821 | act_pt++; |
7bddb01f | 1822 | } |
1d2a314c DV |
1823 | } |
1824 | ||
853ba5d2 | 1825 | static void gen6_ppgtt_insert_entries(struct i915_address_space *vm, |
def886c3 | 1826 | struct sg_table *pages, |
782f1495 | 1827 | uint64_t start, |
24f3a8cf | 1828 | enum i915_cache_level cache_level, u32 flags) |
def886c3 | 1829 | { |
e5716f55 | 1830 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
782f1495 | 1831 | unsigned first_entry = start >> PAGE_SHIFT; |
07749ef3 MT |
1832 | unsigned act_pt = first_entry / GEN6_PTES; |
1833 | unsigned act_pte = first_entry % GEN6_PTES; | |
85d1225e DG |
1834 | gen6_pte_t *pt_vaddr = NULL; |
1835 | struct sgt_iter sgt_iter; | |
1836 | dma_addr_t addr; | |
6e995e23 | 1837 | |
85d1225e | 1838 | for_each_sgt_dma(addr, sgt_iter, pages) { |
cc79714f | 1839 | if (pt_vaddr == NULL) |
d1c54acd | 1840 | pt_vaddr = kmap_px(ppgtt->pd.page_table[act_pt]); |
6e995e23 | 1841 | |
cc79714f | 1842 | pt_vaddr[act_pte] = |
85d1225e | 1843 | vm->pte_encode(addr, cache_level, true, flags); |
24f3a8cf | 1844 | |
07749ef3 | 1845 | if (++act_pte == GEN6_PTES) { |
d1c54acd | 1846 | kunmap_px(ppgtt, pt_vaddr); |
cc79714f | 1847 | pt_vaddr = NULL; |
a15326a5 | 1848 | act_pt++; |
6e995e23 | 1849 | act_pte = 0; |
def886c3 | 1850 | } |
def886c3 | 1851 | } |
85d1225e | 1852 | |
cc79714f | 1853 | if (pt_vaddr) |
d1c54acd | 1854 | kunmap_px(ppgtt, pt_vaddr); |
def886c3 DV |
1855 | } |
1856 | ||
678d96fb | 1857 | static int gen6_alloc_va_range(struct i915_address_space *vm, |
a05d80ee | 1858 | uint64_t start_in, uint64_t length_in) |
678d96fb | 1859 | { |
4933d519 MT |
1860 | DECLARE_BITMAP(new_page_tables, I915_PDES); |
1861 | struct drm_device *dev = vm->dev; | |
72e96d64 JL |
1862 | struct drm_i915_private *dev_priv = to_i915(dev); |
1863 | struct i915_ggtt *ggtt = &dev_priv->ggtt; | |
e5716f55 | 1864 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
ec565b3c | 1865 | struct i915_page_table *pt; |
a05d80ee | 1866 | uint32_t start, length, start_save, length_save; |
731f74c5 | 1867 | uint32_t pde; |
4933d519 MT |
1868 | int ret; |
1869 | ||
a05d80ee MK |
1870 | if (WARN_ON(start_in + length_in > ppgtt->base.total)) |
1871 | return -ENODEV; | |
1872 | ||
1873 | start = start_save = start_in; | |
1874 | length = length_save = length_in; | |
4933d519 MT |
1875 | |
1876 | bitmap_zero(new_page_tables, I915_PDES); | |
1877 | ||
1878 | /* The allocation is done in two stages so that we can bail out with | |
1879 | * minimal amount of pain. The first stage finds new page tables that | |
1880 | * need allocation. The second stage marks use ptes within the page | |
1881 | * tables. | |
1882 | */ | |
731f74c5 | 1883 | gen6_for_each_pde(pt, &ppgtt->pd, start, length, pde) { |
79ab9370 | 1884 | if (pt != vm->scratch_pt) { |
4933d519 MT |
1885 | WARN_ON(bitmap_empty(pt->used_ptes, GEN6_PTES)); |
1886 | continue; | |
1887 | } | |
1888 | ||
1889 | /* We've already allocated a page table */ | |
1890 | WARN_ON(!bitmap_empty(pt->used_ptes, GEN6_PTES)); | |
1891 | ||
8a1ebd74 | 1892 | pt = alloc_pt(dev); |
4933d519 MT |
1893 | if (IS_ERR(pt)) { |
1894 | ret = PTR_ERR(pt); | |
1895 | goto unwind_out; | |
1896 | } | |
1897 | ||
1898 | gen6_initialize_pt(vm, pt); | |
1899 | ||
1900 | ppgtt->pd.page_table[pde] = pt; | |
966082c9 | 1901 | __set_bit(pde, new_page_tables); |
72744cb1 | 1902 | trace_i915_page_table_entry_alloc(vm, pde, start, GEN6_PDE_SHIFT); |
4933d519 MT |
1903 | } |
1904 | ||
1905 | start = start_save; | |
1906 | length = length_save; | |
678d96fb | 1907 | |
731f74c5 | 1908 | gen6_for_each_pde(pt, &ppgtt->pd, start, length, pde) { |
678d96fb BW |
1909 | DECLARE_BITMAP(tmp_bitmap, GEN6_PTES); |
1910 | ||
1911 | bitmap_zero(tmp_bitmap, GEN6_PTES); | |
1912 | bitmap_set(tmp_bitmap, gen6_pte_index(start), | |
1913 | gen6_pte_count(start, length)); | |
1914 | ||
966082c9 | 1915 | if (__test_and_clear_bit(pde, new_page_tables)) |
4933d519 MT |
1916 | gen6_write_pde(&ppgtt->pd, pde, pt); |
1917 | ||
72744cb1 MT |
1918 | trace_i915_page_table_entry_map(vm, pde, pt, |
1919 | gen6_pte_index(start), | |
1920 | gen6_pte_count(start, length), | |
1921 | GEN6_PTES); | |
4933d519 | 1922 | bitmap_or(pt->used_ptes, tmp_bitmap, pt->used_ptes, |
678d96fb BW |
1923 | GEN6_PTES); |
1924 | } | |
1925 | ||
4933d519 MT |
1926 | WARN_ON(!bitmap_empty(new_page_tables, I915_PDES)); |
1927 | ||
1928 | /* Make sure write is complete before other code can use this page | |
1929 | * table. Also require for WC mapped PTEs */ | |
72e96d64 | 1930 | readl(ggtt->gsm); |
4933d519 | 1931 | |
563222a7 | 1932 | mark_tlbs_dirty(ppgtt); |
678d96fb | 1933 | return 0; |
4933d519 MT |
1934 | |
1935 | unwind_out: | |
1936 | for_each_set_bit(pde, new_page_tables, I915_PDES) { | |
ec565b3c | 1937 | struct i915_page_table *pt = ppgtt->pd.page_table[pde]; |
4933d519 | 1938 | |
79ab9370 | 1939 | ppgtt->pd.page_table[pde] = vm->scratch_pt; |
a08e111a | 1940 | free_pt(vm->dev, pt); |
4933d519 MT |
1941 | } |
1942 | ||
1943 | mark_tlbs_dirty(ppgtt); | |
1944 | return ret; | |
678d96fb BW |
1945 | } |
1946 | ||
8776f02b MK |
1947 | static int gen6_init_scratch(struct i915_address_space *vm) |
1948 | { | |
1949 | struct drm_device *dev = vm->dev; | |
1950 | ||
1951 | vm->scratch_page = alloc_scratch_page(dev); | |
1952 | if (IS_ERR(vm->scratch_page)) | |
1953 | return PTR_ERR(vm->scratch_page); | |
1954 | ||
1955 | vm->scratch_pt = alloc_pt(dev); | |
1956 | if (IS_ERR(vm->scratch_pt)) { | |
1957 | free_scratch_page(dev, vm->scratch_page); | |
1958 | return PTR_ERR(vm->scratch_pt); | |
1959 | } | |
1960 | ||
1961 | gen6_initialize_pt(vm, vm->scratch_pt); | |
1962 | ||
1963 | return 0; | |
1964 | } | |
1965 | ||
1966 | static void gen6_free_scratch(struct i915_address_space *vm) | |
1967 | { | |
1968 | struct drm_device *dev = vm->dev; | |
1969 | ||
1970 | free_pt(dev, vm->scratch_pt); | |
1971 | free_scratch_page(dev, vm->scratch_page); | |
1972 | } | |
1973 | ||
061dd493 | 1974 | static void gen6_ppgtt_cleanup(struct i915_address_space *vm) |
a00d825d | 1975 | { |
e5716f55 | 1976 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
731f74c5 DG |
1977 | struct i915_page_directory *pd = &ppgtt->pd; |
1978 | struct drm_device *dev = vm->dev; | |
09942c65 MT |
1979 | struct i915_page_table *pt; |
1980 | uint32_t pde; | |
4933d519 | 1981 | |
061dd493 DV |
1982 | drm_mm_remove_node(&ppgtt->node); |
1983 | ||
731f74c5 | 1984 | gen6_for_all_pdes(pt, pd, pde) |
79ab9370 | 1985 | if (pt != vm->scratch_pt) |
731f74c5 | 1986 | free_pt(dev, pt); |
06fda602 | 1987 | |
8776f02b | 1988 | gen6_free_scratch(vm); |
3440d265 DV |
1989 | } |
1990 | ||
b146520f | 1991 | static int gen6_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt) |
3440d265 | 1992 | { |
8776f02b | 1993 | struct i915_address_space *vm = &ppgtt->base; |
853ba5d2 | 1994 | struct drm_device *dev = ppgtt->base.dev; |
72e96d64 JL |
1995 | struct drm_i915_private *dev_priv = to_i915(dev); |
1996 | struct i915_ggtt *ggtt = &dev_priv->ggtt; | |
e3cc1995 | 1997 | bool retried = false; |
b146520f | 1998 | int ret; |
1d2a314c | 1999 | |
c8d4c0d6 BW |
2000 | /* PPGTT PDEs reside in the GGTT and consists of 512 entries. The |
2001 | * allocator works in address space sizes, so it's multiplied by page | |
2002 | * size. We allocate at the top of the GTT to avoid fragmentation. | |
2003 | */ | |
72e96d64 | 2004 | BUG_ON(!drm_mm_initialized(&ggtt->base.mm)); |
4933d519 | 2005 | |
8776f02b MK |
2006 | ret = gen6_init_scratch(vm); |
2007 | if (ret) | |
2008 | return ret; | |
4933d519 | 2009 | |
e3cc1995 | 2010 | alloc: |
72e96d64 | 2011 | ret = drm_mm_insert_node_in_range_generic(&ggtt->base.mm, |
c8d4c0d6 BW |
2012 | &ppgtt->node, GEN6_PD_SIZE, |
2013 | GEN6_PD_ALIGN, 0, | |
72e96d64 | 2014 | 0, ggtt->base.total, |
3e8b5ae9 | 2015 | DRM_MM_TOPDOWN); |
e3cc1995 | 2016 | if (ret == -ENOSPC && !retried) { |
e522ac23 | 2017 | ret = i915_gem_evict_something(&ggtt->base, |
e3cc1995 | 2018 | GEN6_PD_SIZE, GEN6_PD_ALIGN, |
d23db88c | 2019 | I915_CACHE_NONE, |
72e96d64 | 2020 | 0, ggtt->base.total, |
d23db88c | 2021 | 0); |
e3cc1995 | 2022 | if (ret) |
678d96fb | 2023 | goto err_out; |
e3cc1995 BW |
2024 | |
2025 | retried = true; | |
2026 | goto alloc; | |
2027 | } | |
c8d4c0d6 | 2028 | |
c8c26622 | 2029 | if (ret) |
678d96fb BW |
2030 | goto err_out; |
2031 | ||
c8c26622 | 2032 | |
72e96d64 | 2033 | if (ppgtt->node.start < ggtt->mappable_end) |
c8d4c0d6 | 2034 | DRM_DEBUG("Forced to use aperture for PDEs\n"); |
1d2a314c | 2035 | |
c8c26622 | 2036 | return 0; |
678d96fb BW |
2037 | |
2038 | err_out: | |
8776f02b | 2039 | gen6_free_scratch(vm); |
678d96fb | 2040 | return ret; |
b146520f BW |
2041 | } |
2042 | ||
b146520f BW |
2043 | static int gen6_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt) |
2044 | { | |
2f2cf682 | 2045 | return gen6_ppgtt_allocate_page_directories(ppgtt); |
4933d519 | 2046 | } |
06dc68d6 | 2047 | |
4933d519 MT |
2048 | static void gen6_scratch_va_range(struct i915_hw_ppgtt *ppgtt, |
2049 | uint64_t start, uint64_t length) | |
2050 | { | |
ec565b3c | 2051 | struct i915_page_table *unused; |
731f74c5 | 2052 | uint32_t pde; |
1d2a314c | 2053 | |
731f74c5 | 2054 | gen6_for_each_pde(unused, &ppgtt->pd, start, length, pde) |
79ab9370 | 2055 | ppgtt->pd.page_table[pde] = ppgtt->base.scratch_pt; |
b146520f BW |
2056 | } |
2057 | ||
5c5f6457 | 2058 | static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt) |
b146520f BW |
2059 | { |
2060 | struct drm_device *dev = ppgtt->base.dev; | |
72e96d64 JL |
2061 | struct drm_i915_private *dev_priv = to_i915(dev); |
2062 | struct i915_ggtt *ggtt = &dev_priv->ggtt; | |
b146520f BW |
2063 | int ret; |
2064 | ||
72e96d64 | 2065 | ppgtt->base.pte_encode = ggtt->base.pte_encode; |
8eb95204 | 2066 | if (intel_vgpu_active(dev_priv) || IS_GEN6(dev)) |
b146520f | 2067 | ppgtt->switch_mm = gen6_mm_switch; |
8eb95204 | 2068 | else if (IS_HASWELL(dev)) |
b146520f | 2069 | ppgtt->switch_mm = hsw_mm_switch; |
8eb95204 | 2070 | else if (IS_GEN7(dev)) |
b146520f | 2071 | ppgtt->switch_mm = gen7_mm_switch; |
8eb95204 | 2072 | else |
b146520f BW |
2073 | BUG(); |
2074 | ||
2075 | ret = gen6_ppgtt_alloc(ppgtt); | |
2076 | if (ret) | |
2077 | return ret; | |
2078 | ||
5c5f6457 | 2079 | ppgtt->base.allocate_va_range = gen6_alloc_va_range; |
b146520f BW |
2080 | ppgtt->base.clear_range = gen6_ppgtt_clear_range; |
2081 | ppgtt->base.insert_entries = gen6_ppgtt_insert_entries; | |
777dc5bb DV |
2082 | ppgtt->base.unbind_vma = ppgtt_unbind_vma; |
2083 | ppgtt->base.bind_vma = ppgtt_bind_vma; | |
b146520f | 2084 | ppgtt->base.cleanup = gen6_ppgtt_cleanup; |
b146520f | 2085 | ppgtt->base.start = 0; |
09942c65 | 2086 | ppgtt->base.total = I915_PDES * GEN6_PTES * PAGE_SIZE; |
87d60b63 | 2087 | ppgtt->debug_dump = gen6_dump_ppgtt; |
1d2a314c | 2088 | |
44159ddb | 2089 | ppgtt->pd.base.ggtt_offset = |
07749ef3 | 2090 | ppgtt->node.start / PAGE_SIZE * sizeof(gen6_pte_t); |
1d2a314c | 2091 | |
72e96d64 | 2092 | ppgtt->pd_addr = (gen6_pte_t __iomem *)ggtt->gsm + |
44159ddb | 2093 | ppgtt->pd.base.ggtt_offset / sizeof(gen6_pte_t); |
678d96fb | 2094 | |
5c5f6457 | 2095 | gen6_scratch_va_range(ppgtt, 0, ppgtt->base.total); |
1d2a314c | 2096 | |
678d96fb BW |
2097 | gen6_write_page_range(dev_priv, &ppgtt->pd, 0, ppgtt->base.total); |
2098 | ||
440fd528 | 2099 | DRM_DEBUG_DRIVER("Allocated pde space (%lldM) at GTT entry: %llx\n", |
b146520f BW |
2100 | ppgtt->node.size >> 20, |
2101 | ppgtt->node.start / PAGE_SIZE); | |
3440d265 | 2102 | |
fa76da34 | 2103 | DRM_DEBUG("Adding PPGTT at offset %x\n", |
44159ddb | 2104 | ppgtt->pd.base.ggtt_offset << 10); |
fa76da34 | 2105 | |
b146520f | 2106 | return 0; |
3440d265 DV |
2107 | } |
2108 | ||
2bfa996e CW |
2109 | static int __hw_ppgtt_init(struct i915_hw_ppgtt *ppgtt, |
2110 | struct drm_i915_private *dev_priv) | |
3440d265 | 2111 | { |
2bfa996e | 2112 | ppgtt->base.dev = &dev_priv->drm; |
3440d265 | 2113 | |
2bfa996e | 2114 | if (INTEL_INFO(dev_priv)->gen < 8) |
5c5f6457 | 2115 | return gen6_ppgtt_init(ppgtt); |
3ed124b2 | 2116 | else |
d7b2633d | 2117 | return gen8_ppgtt_init(ppgtt); |
fa76da34 | 2118 | } |
c114f76a | 2119 | |
a2cad9df MW |
2120 | static void i915_address_space_init(struct i915_address_space *vm, |
2121 | struct drm_i915_private *dev_priv) | |
2122 | { | |
2123 | drm_mm_init(&vm->mm, vm->start, vm->total); | |
a2cad9df MW |
2124 | INIT_LIST_HEAD(&vm->active_list); |
2125 | INIT_LIST_HEAD(&vm->inactive_list); | |
50e046b6 | 2126 | INIT_LIST_HEAD(&vm->unbound_list); |
a2cad9df MW |
2127 | list_add_tail(&vm->global_link, &dev_priv->vm_list); |
2128 | } | |
2129 | ||
d5165ebd TG |
2130 | static void gtt_write_workarounds(struct drm_device *dev) |
2131 | { | |
fac5e23e | 2132 | struct drm_i915_private *dev_priv = to_i915(dev); |
d5165ebd TG |
2133 | |
2134 | /* This function is for gtt related workarounds. This function is | |
2135 | * called on driver load and after a GPU reset, so you can place | |
2136 | * workarounds here even if they get overwritten by GPU reset. | |
2137 | */ | |
2138 | /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt */ | |
2139 | if (IS_BROADWELL(dev)) | |
2140 | I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW); | |
2141 | else if (IS_CHERRYVIEW(dev)) | |
2142 | I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV); | |
2143 | else if (IS_SKYLAKE(dev)) | |
2144 | I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL); | |
2145 | else if (IS_BROXTON(dev)) | |
2146 | I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT); | |
2147 | } | |
2148 | ||
2bfa996e CW |
2149 | static int i915_ppgtt_init(struct i915_hw_ppgtt *ppgtt, |
2150 | struct drm_i915_private *dev_priv, | |
2151 | struct drm_i915_file_private *file_priv) | |
fa76da34 | 2152 | { |
2bfa996e | 2153 | int ret; |
3ed124b2 | 2154 | |
2bfa996e | 2155 | ret = __hw_ppgtt_init(ppgtt, dev_priv); |
fa76da34 | 2156 | if (ret == 0) { |
c7c48dfd | 2157 | kref_init(&ppgtt->ref); |
a2cad9df | 2158 | i915_address_space_init(&ppgtt->base, dev_priv); |
2bfa996e | 2159 | ppgtt->base.file = file_priv; |
93bd8649 | 2160 | } |
1d2a314c DV |
2161 | |
2162 | return ret; | |
2163 | } | |
2164 | ||
82460d97 DV |
2165 | int i915_ppgtt_init_hw(struct drm_device *dev) |
2166 | { | |
d5165ebd TG |
2167 | gtt_write_workarounds(dev); |
2168 | ||
671b5013 TD |
2169 | /* In the case of execlists, PPGTT is enabled by the context descriptor |
2170 | * and the PDPs are contained within the context itself. We don't | |
2171 | * need to do anything here. */ | |
2172 | if (i915.enable_execlists) | |
2173 | return 0; | |
2174 | ||
82460d97 DV |
2175 | if (!USES_PPGTT(dev)) |
2176 | return 0; | |
2177 | ||
2178 | if (IS_GEN6(dev)) | |
2179 | gen6_ppgtt_enable(dev); | |
2180 | else if (IS_GEN7(dev)) | |
2181 | gen7_ppgtt_enable(dev); | |
2182 | else if (INTEL_INFO(dev)->gen >= 8) | |
2183 | gen8_ppgtt_enable(dev); | |
2184 | else | |
5f77eeb0 | 2185 | MISSING_CASE(INTEL_INFO(dev)->gen); |
82460d97 | 2186 | |
4ad2fd88 JH |
2187 | return 0; |
2188 | } | |
1d2a314c | 2189 | |
4d884705 | 2190 | struct i915_hw_ppgtt * |
2bfa996e CW |
2191 | i915_ppgtt_create(struct drm_i915_private *dev_priv, |
2192 | struct drm_i915_file_private *fpriv) | |
4d884705 DV |
2193 | { |
2194 | struct i915_hw_ppgtt *ppgtt; | |
2195 | int ret; | |
2196 | ||
2197 | ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL); | |
2198 | if (!ppgtt) | |
2199 | return ERR_PTR(-ENOMEM); | |
2200 | ||
2bfa996e | 2201 | ret = i915_ppgtt_init(ppgtt, dev_priv, fpriv); |
4d884705 DV |
2202 | if (ret) { |
2203 | kfree(ppgtt); | |
2204 | return ERR_PTR(ret); | |
2205 | } | |
2206 | ||
198c974d DCS |
2207 | trace_i915_ppgtt_create(&ppgtt->base); |
2208 | ||
4d884705 DV |
2209 | return ppgtt; |
2210 | } | |
2211 | ||
ee960be7 DV |
2212 | void i915_ppgtt_release(struct kref *kref) |
2213 | { | |
2214 | struct i915_hw_ppgtt *ppgtt = | |
2215 | container_of(kref, struct i915_hw_ppgtt, ref); | |
2216 | ||
198c974d DCS |
2217 | trace_i915_ppgtt_release(&ppgtt->base); |
2218 | ||
50e046b6 | 2219 | /* vmas should already be unbound and destroyed */ |
ee960be7 DV |
2220 | WARN_ON(!list_empty(&ppgtt->base.active_list)); |
2221 | WARN_ON(!list_empty(&ppgtt->base.inactive_list)); | |
50e046b6 | 2222 | WARN_ON(!list_empty(&ppgtt->base.unbound_list)); |
ee960be7 | 2223 | |
19dd120c DV |
2224 | list_del(&ppgtt->base.global_link); |
2225 | drm_mm_takedown(&ppgtt->base.mm); | |
2226 | ||
ee960be7 DV |
2227 | ppgtt->base.cleanup(&ppgtt->base); |
2228 | kfree(ppgtt); | |
2229 | } | |
1d2a314c | 2230 | |
a81cc00c BW |
2231 | /* Certain Gen5 chipsets require require idling the GPU before |
2232 | * unmapping anything from the GTT when VT-d is enabled. | |
2233 | */ | |
97d6d7ab | 2234 | static bool needs_idle_maps(struct drm_i915_private *dev_priv) |
a81cc00c BW |
2235 | { |
2236 | #ifdef CONFIG_INTEL_IOMMU | |
2237 | /* Query intel_iommu to see if we need the workaround. Presumably that | |
2238 | * was loaded first. | |
2239 | */ | |
97d6d7ab | 2240 | if (IS_GEN5(dev_priv) && IS_MOBILE(dev_priv) && intel_iommu_gfx_mapped) |
a81cc00c BW |
2241 | return true; |
2242 | #endif | |
2243 | return false; | |
2244 | } | |
2245 | ||
dc97997a | 2246 | void i915_check_and_clear_faults(struct drm_i915_private *dev_priv) |
828c7908 | 2247 | { |
e2f80391 | 2248 | struct intel_engine_cs *engine; |
828c7908 | 2249 | |
dc97997a | 2250 | if (INTEL_INFO(dev_priv)->gen < 6) |
828c7908 BW |
2251 | return; |
2252 | ||
b4ac5afc | 2253 | for_each_engine(engine, dev_priv) { |
828c7908 | 2254 | u32 fault_reg; |
e2f80391 | 2255 | fault_reg = I915_READ(RING_FAULT_REG(engine)); |
828c7908 BW |
2256 | if (fault_reg & RING_FAULT_VALID) { |
2257 | DRM_DEBUG_DRIVER("Unexpected fault\n" | |
59a5d290 | 2258 | "\tAddr: 0x%08lx\n" |
828c7908 BW |
2259 | "\tAddress space: %s\n" |
2260 | "\tSource ID: %d\n" | |
2261 | "\tType: %d\n", | |
2262 | fault_reg & PAGE_MASK, | |
2263 | fault_reg & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT", | |
2264 | RING_FAULT_SRCID(fault_reg), | |
2265 | RING_FAULT_FAULT_TYPE(fault_reg)); | |
e2f80391 | 2266 | I915_WRITE(RING_FAULT_REG(engine), |
828c7908 BW |
2267 | fault_reg & ~RING_FAULT_VALID); |
2268 | } | |
2269 | } | |
4a570db5 | 2270 | POSTING_READ(RING_FAULT_REG(&dev_priv->engine[RCS])); |
828c7908 BW |
2271 | } |
2272 | ||
91e56499 CW |
2273 | static void i915_ggtt_flush(struct drm_i915_private *dev_priv) |
2274 | { | |
2d1fe073 | 2275 | if (INTEL_INFO(dev_priv)->gen < 6) { |
91e56499 CW |
2276 | intel_gtt_chipset_flush(); |
2277 | } else { | |
2278 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
2279 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
2280 | } | |
2281 | } | |
2282 | ||
828c7908 BW |
2283 | void i915_gem_suspend_gtt_mappings(struct drm_device *dev) |
2284 | { | |
72e96d64 JL |
2285 | struct drm_i915_private *dev_priv = to_i915(dev); |
2286 | struct i915_ggtt *ggtt = &dev_priv->ggtt; | |
828c7908 BW |
2287 | |
2288 | /* Don't bother messing with faults pre GEN6 as we have little | |
2289 | * documentation supporting that it's a good idea. | |
2290 | */ | |
2291 | if (INTEL_INFO(dev)->gen < 6) | |
2292 | return; | |
2293 | ||
dc97997a | 2294 | i915_check_and_clear_faults(dev_priv); |
828c7908 | 2295 | |
72e96d64 JL |
2296 | ggtt->base.clear_range(&ggtt->base, ggtt->base.start, ggtt->base.total, |
2297 | true); | |
91e56499 CW |
2298 | |
2299 | i915_ggtt_flush(dev_priv); | |
828c7908 BW |
2300 | } |
2301 | ||
74163907 | 2302 | int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj) |
7c2e6fdf | 2303 | { |
9da3da66 CW |
2304 | if (!dma_map_sg(&obj->base.dev->pdev->dev, |
2305 | obj->pages->sgl, obj->pages->nents, | |
2306 | PCI_DMA_BIDIRECTIONAL)) | |
2307 | return -ENOSPC; | |
2308 | ||
2309 | return 0; | |
7c2e6fdf DV |
2310 | } |
2311 | ||
2c642b07 | 2312 | static void gen8_set_pte(void __iomem *addr, gen8_pte_t pte) |
94ec8f61 BW |
2313 | { |
2314 | #ifdef writeq | |
2315 | writeq(pte, addr); | |
2316 | #else | |
2317 | iowrite32((u32)pte, addr); | |
2318 | iowrite32(pte >> 32, addr + 4); | |
2319 | #endif | |
2320 | } | |
2321 | ||
d6473f56 CW |
2322 | static void gen8_ggtt_insert_page(struct i915_address_space *vm, |
2323 | dma_addr_t addr, | |
2324 | uint64_t offset, | |
2325 | enum i915_cache_level level, | |
2326 | u32 unused) | |
2327 | { | |
2328 | struct drm_i915_private *dev_priv = to_i915(vm->dev); | |
2329 | gen8_pte_t __iomem *pte = | |
2330 | (gen8_pte_t __iomem *)dev_priv->ggtt.gsm + | |
2331 | (offset >> PAGE_SHIFT); | |
2332 | int rpm_atomic_seq; | |
2333 | ||
2334 | rpm_atomic_seq = assert_rpm_atomic_begin(dev_priv); | |
2335 | ||
2336 | gen8_set_pte(pte, gen8_pte_encode(addr, level, true)); | |
2337 | ||
2338 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
2339 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
2340 | ||
2341 | assert_rpm_atomic_end(dev_priv, rpm_atomic_seq); | |
2342 | } | |
2343 | ||
94ec8f61 BW |
2344 | static void gen8_ggtt_insert_entries(struct i915_address_space *vm, |
2345 | struct sg_table *st, | |
782f1495 | 2346 | uint64_t start, |
24f3a8cf | 2347 | enum i915_cache_level level, u32 unused) |
94ec8f61 | 2348 | { |
72e96d64 | 2349 | struct drm_i915_private *dev_priv = to_i915(vm->dev); |
ce7fda2e | 2350 | struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm); |
85d1225e DG |
2351 | struct sgt_iter sgt_iter; |
2352 | gen8_pte_t __iomem *gtt_entries; | |
2353 | gen8_pte_t gtt_entry; | |
2354 | dma_addr_t addr; | |
be69459a | 2355 | int rpm_atomic_seq; |
85d1225e | 2356 | int i = 0; |
be69459a ID |
2357 | |
2358 | rpm_atomic_seq = assert_rpm_atomic_begin(dev_priv); | |
94ec8f61 | 2359 | |
85d1225e DG |
2360 | gtt_entries = (gen8_pte_t __iomem *)ggtt->gsm + (start >> PAGE_SHIFT); |
2361 | ||
2362 | for_each_sgt_dma(addr, sgt_iter, st) { | |
2363 | gtt_entry = gen8_pte_encode(addr, level, true); | |
2364 | gen8_set_pte(>t_entries[i++], gtt_entry); | |
94ec8f61 BW |
2365 | } |
2366 | ||
2367 | /* | |
2368 | * XXX: This serves as a posting read to make sure that the PTE has | |
2369 | * actually been updated. There is some concern that even though | |
2370 | * registers and PTEs are within the same BAR that they are potentially | |
2371 | * of NUMA access patterns. Therefore, even with the way we assume | |
2372 | * hardware should work, we must keep this posting read for paranoia. | |
2373 | */ | |
2374 | if (i != 0) | |
85d1225e | 2375 | WARN_ON(readq(>t_entries[i-1]) != gtt_entry); |
94ec8f61 | 2376 | |
94ec8f61 BW |
2377 | /* This next bit makes the above posting read even more important. We |
2378 | * want to flush the TLBs only after we're certain all the PTE updates | |
2379 | * have finished. | |
2380 | */ | |
2381 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
2382 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
be69459a ID |
2383 | |
2384 | assert_rpm_atomic_end(dev_priv, rpm_atomic_seq); | |
94ec8f61 BW |
2385 | } |
2386 | ||
c140330b CW |
2387 | struct insert_entries { |
2388 | struct i915_address_space *vm; | |
2389 | struct sg_table *st; | |
2390 | uint64_t start; | |
2391 | enum i915_cache_level level; | |
2392 | u32 flags; | |
2393 | }; | |
2394 | ||
2395 | static int gen8_ggtt_insert_entries__cb(void *_arg) | |
2396 | { | |
2397 | struct insert_entries *arg = _arg; | |
2398 | gen8_ggtt_insert_entries(arg->vm, arg->st, | |
2399 | arg->start, arg->level, arg->flags); | |
2400 | return 0; | |
2401 | } | |
2402 | ||
2403 | static void gen8_ggtt_insert_entries__BKL(struct i915_address_space *vm, | |
2404 | struct sg_table *st, | |
2405 | uint64_t start, | |
2406 | enum i915_cache_level level, | |
2407 | u32 flags) | |
2408 | { | |
2409 | struct insert_entries arg = { vm, st, start, level, flags }; | |
2410 | stop_machine(gen8_ggtt_insert_entries__cb, &arg, NULL); | |
2411 | } | |
2412 | ||
d6473f56 CW |
2413 | static void gen6_ggtt_insert_page(struct i915_address_space *vm, |
2414 | dma_addr_t addr, | |
2415 | uint64_t offset, | |
2416 | enum i915_cache_level level, | |
2417 | u32 flags) | |
2418 | { | |
2419 | struct drm_i915_private *dev_priv = to_i915(vm->dev); | |
2420 | gen6_pte_t __iomem *pte = | |
2421 | (gen6_pte_t __iomem *)dev_priv->ggtt.gsm + | |
2422 | (offset >> PAGE_SHIFT); | |
2423 | int rpm_atomic_seq; | |
2424 | ||
2425 | rpm_atomic_seq = assert_rpm_atomic_begin(dev_priv); | |
2426 | ||
2427 | iowrite32(vm->pte_encode(addr, level, true, flags), pte); | |
2428 | ||
2429 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
2430 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
2431 | ||
2432 | assert_rpm_atomic_end(dev_priv, rpm_atomic_seq); | |
2433 | } | |
2434 | ||
e76e9aeb BW |
2435 | /* |
2436 | * Binds an object into the global gtt with the specified cache level. The object | |
2437 | * will be accessible to the GPU via commands whose operands reference offsets | |
2438 | * within the global GTT as well as accessible by the GPU through the GMADR | |
2439 | * mapped BAR (dev_priv->mm.gtt->gtt). | |
2440 | */ | |
853ba5d2 | 2441 | static void gen6_ggtt_insert_entries(struct i915_address_space *vm, |
7faf1ab2 | 2442 | struct sg_table *st, |
782f1495 | 2443 | uint64_t start, |
24f3a8cf | 2444 | enum i915_cache_level level, u32 flags) |
e76e9aeb | 2445 | { |
72e96d64 | 2446 | struct drm_i915_private *dev_priv = to_i915(vm->dev); |
ce7fda2e | 2447 | struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm); |
85d1225e DG |
2448 | struct sgt_iter sgt_iter; |
2449 | gen6_pte_t __iomem *gtt_entries; | |
2450 | gen6_pte_t gtt_entry; | |
2451 | dma_addr_t addr; | |
be69459a | 2452 | int rpm_atomic_seq; |
85d1225e | 2453 | int i = 0; |
be69459a ID |
2454 | |
2455 | rpm_atomic_seq = assert_rpm_atomic_begin(dev_priv); | |
e76e9aeb | 2456 | |
85d1225e DG |
2457 | gtt_entries = (gen6_pte_t __iomem *)ggtt->gsm + (start >> PAGE_SHIFT); |
2458 | ||
2459 | for_each_sgt_dma(addr, sgt_iter, st) { | |
2460 | gtt_entry = vm->pte_encode(addr, level, true, flags); | |
2461 | iowrite32(gtt_entry, >t_entries[i++]); | |
e76e9aeb BW |
2462 | } |
2463 | ||
e76e9aeb BW |
2464 | /* XXX: This serves as a posting read to make sure that the PTE has |
2465 | * actually been updated. There is some concern that even though | |
2466 | * registers and PTEs are within the same BAR that they are potentially | |
2467 | * of NUMA access patterns. Therefore, even with the way we assume | |
2468 | * hardware should work, we must keep this posting read for paranoia. | |
2469 | */ | |
85d1225e DG |
2470 | if (i != 0) |
2471 | WARN_ON(readl(>t_entries[i-1]) != gtt_entry); | |
0f9b91c7 BW |
2472 | |
2473 | /* This next bit makes the above posting read even more important. We | |
2474 | * want to flush the TLBs only after we're certain all the PTE updates | |
2475 | * have finished. | |
2476 | */ | |
2477 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
2478 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
be69459a ID |
2479 | |
2480 | assert_rpm_atomic_end(dev_priv, rpm_atomic_seq); | |
e76e9aeb BW |
2481 | } |
2482 | ||
f7770bfd CW |
2483 | static void nop_clear_range(struct i915_address_space *vm, |
2484 | uint64_t start, | |
2485 | uint64_t length, | |
2486 | bool use_scratch) | |
2487 | { | |
2488 | } | |
2489 | ||
94ec8f61 | 2490 | static void gen8_ggtt_clear_range(struct i915_address_space *vm, |
782f1495 BW |
2491 | uint64_t start, |
2492 | uint64_t length, | |
94ec8f61 BW |
2493 | bool use_scratch) |
2494 | { | |
72e96d64 | 2495 | struct drm_i915_private *dev_priv = to_i915(vm->dev); |
ce7fda2e | 2496 | struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm); |
782f1495 BW |
2497 | unsigned first_entry = start >> PAGE_SHIFT; |
2498 | unsigned num_entries = length >> PAGE_SHIFT; | |
07749ef3 | 2499 | gen8_pte_t scratch_pte, __iomem *gtt_base = |
72e96d64 JL |
2500 | (gen8_pte_t __iomem *)ggtt->gsm + first_entry; |
2501 | const int max_entries = ggtt_total_entries(ggtt) - first_entry; | |
94ec8f61 | 2502 | int i; |
be69459a ID |
2503 | int rpm_atomic_seq; |
2504 | ||
2505 | rpm_atomic_seq = assert_rpm_atomic_begin(dev_priv); | |
94ec8f61 BW |
2506 | |
2507 | if (WARN(num_entries > max_entries, | |
2508 | "First entry = %d; Num entries = %d (max=%d)\n", | |
2509 | first_entry, num_entries, max_entries)) | |
2510 | num_entries = max_entries; | |
2511 | ||
c114f76a | 2512 | scratch_pte = gen8_pte_encode(px_dma(vm->scratch_page), |
94ec8f61 BW |
2513 | I915_CACHE_LLC, |
2514 | use_scratch); | |
2515 | for (i = 0; i < num_entries; i++) | |
2516 | gen8_set_pte(>t_base[i], scratch_pte); | |
2517 | readl(gtt_base); | |
be69459a ID |
2518 | |
2519 | assert_rpm_atomic_end(dev_priv, rpm_atomic_seq); | |
94ec8f61 BW |
2520 | } |
2521 | ||
853ba5d2 | 2522 | static void gen6_ggtt_clear_range(struct i915_address_space *vm, |
782f1495 BW |
2523 | uint64_t start, |
2524 | uint64_t length, | |
828c7908 | 2525 | bool use_scratch) |
7faf1ab2 | 2526 | { |
72e96d64 | 2527 | struct drm_i915_private *dev_priv = to_i915(vm->dev); |
ce7fda2e | 2528 | struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm); |
782f1495 BW |
2529 | unsigned first_entry = start >> PAGE_SHIFT; |
2530 | unsigned num_entries = length >> PAGE_SHIFT; | |
07749ef3 | 2531 | gen6_pte_t scratch_pte, __iomem *gtt_base = |
72e96d64 JL |
2532 | (gen6_pte_t __iomem *)ggtt->gsm + first_entry; |
2533 | const int max_entries = ggtt_total_entries(ggtt) - first_entry; | |
7faf1ab2 | 2534 | int i; |
be69459a ID |
2535 | int rpm_atomic_seq; |
2536 | ||
2537 | rpm_atomic_seq = assert_rpm_atomic_begin(dev_priv); | |
7faf1ab2 DV |
2538 | |
2539 | if (WARN(num_entries > max_entries, | |
2540 | "First entry = %d; Num entries = %d (max=%d)\n", | |
2541 | first_entry, num_entries, max_entries)) | |
2542 | num_entries = max_entries; | |
2543 | ||
c114f76a MK |
2544 | scratch_pte = vm->pte_encode(px_dma(vm->scratch_page), |
2545 | I915_CACHE_LLC, use_scratch, 0); | |
828c7908 | 2546 | |
7faf1ab2 DV |
2547 | for (i = 0; i < num_entries; i++) |
2548 | iowrite32(scratch_pte, >t_base[i]); | |
2549 | readl(gtt_base); | |
be69459a ID |
2550 | |
2551 | assert_rpm_atomic_end(dev_priv, rpm_atomic_seq); | |
7faf1ab2 DV |
2552 | } |
2553 | ||
d6473f56 CW |
2554 | static void i915_ggtt_insert_page(struct i915_address_space *vm, |
2555 | dma_addr_t addr, | |
2556 | uint64_t offset, | |
2557 | enum i915_cache_level cache_level, | |
2558 | u32 unused) | |
2559 | { | |
2560 | struct drm_i915_private *dev_priv = to_i915(vm->dev); | |
2561 | unsigned int flags = (cache_level == I915_CACHE_NONE) ? | |
2562 | AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY; | |
2563 | int rpm_atomic_seq; | |
2564 | ||
2565 | rpm_atomic_seq = assert_rpm_atomic_begin(dev_priv); | |
2566 | ||
2567 | intel_gtt_insert_page(addr, offset >> PAGE_SHIFT, flags); | |
2568 | ||
2569 | assert_rpm_atomic_end(dev_priv, rpm_atomic_seq); | |
2570 | } | |
2571 | ||
d369d2d9 DV |
2572 | static void i915_ggtt_insert_entries(struct i915_address_space *vm, |
2573 | struct sg_table *pages, | |
2574 | uint64_t start, | |
2575 | enum i915_cache_level cache_level, u32 unused) | |
7faf1ab2 | 2576 | { |
fac5e23e | 2577 | struct drm_i915_private *dev_priv = to_i915(vm->dev); |
7faf1ab2 DV |
2578 | unsigned int flags = (cache_level == I915_CACHE_NONE) ? |
2579 | AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY; | |
be69459a ID |
2580 | int rpm_atomic_seq; |
2581 | ||
2582 | rpm_atomic_seq = assert_rpm_atomic_begin(dev_priv); | |
7faf1ab2 | 2583 | |
d369d2d9 | 2584 | intel_gtt_insert_sg_entries(pages, start >> PAGE_SHIFT, flags); |
0875546c | 2585 | |
be69459a ID |
2586 | assert_rpm_atomic_end(dev_priv, rpm_atomic_seq); |
2587 | ||
7faf1ab2 DV |
2588 | } |
2589 | ||
853ba5d2 | 2590 | static void i915_ggtt_clear_range(struct i915_address_space *vm, |
782f1495 BW |
2591 | uint64_t start, |
2592 | uint64_t length, | |
828c7908 | 2593 | bool unused) |
7faf1ab2 | 2594 | { |
fac5e23e | 2595 | struct drm_i915_private *dev_priv = to_i915(vm->dev); |
782f1495 BW |
2596 | unsigned first_entry = start >> PAGE_SHIFT; |
2597 | unsigned num_entries = length >> PAGE_SHIFT; | |
be69459a ID |
2598 | int rpm_atomic_seq; |
2599 | ||
2600 | rpm_atomic_seq = assert_rpm_atomic_begin(dev_priv); | |
2601 | ||
7faf1ab2 | 2602 | intel_gtt_clear_range(first_entry, num_entries); |
be69459a ID |
2603 | |
2604 | assert_rpm_atomic_end(dev_priv, rpm_atomic_seq); | |
7faf1ab2 DV |
2605 | } |
2606 | ||
70b9f6f8 DV |
2607 | static int ggtt_bind_vma(struct i915_vma *vma, |
2608 | enum i915_cache_level cache_level, | |
2609 | u32 flags) | |
0a878716 DV |
2610 | { |
2611 | struct drm_i915_gem_object *obj = vma->obj; | |
2612 | u32 pte_flags = 0; | |
2613 | int ret; | |
2614 | ||
2615 | ret = i915_get_ggtt_vma_pages(vma); | |
2616 | if (ret) | |
2617 | return ret; | |
2618 | ||
2619 | /* Currently applicable only to VLV */ | |
2620 | if (obj->gt_ro) | |
2621 | pte_flags |= PTE_READ_ONLY; | |
2622 | ||
247177dd | 2623 | vma->vm->insert_entries(vma->vm, vma->pages, vma->node.start, |
0a878716 DV |
2624 | cache_level, pte_flags); |
2625 | ||
2626 | /* | |
2627 | * Without aliasing PPGTT there's no difference between | |
2628 | * GLOBAL/LOCAL_BIND, it's all the same ptes. Hence unconditionally | |
2629 | * upgrade to both bound if we bind either to avoid double-binding. | |
2630 | */ | |
3272db53 | 2631 | vma->flags |= I915_VMA_GLOBAL_BIND | I915_VMA_LOCAL_BIND; |
0a878716 DV |
2632 | |
2633 | return 0; | |
2634 | } | |
2635 | ||
2636 | static int aliasing_gtt_bind_vma(struct i915_vma *vma, | |
2637 | enum i915_cache_level cache_level, | |
2638 | u32 flags) | |
d5bd1449 | 2639 | { |
321d178e | 2640 | u32 pte_flags; |
70b9f6f8 DV |
2641 | int ret; |
2642 | ||
2643 | ret = i915_get_ggtt_vma_pages(vma); | |
2644 | if (ret) | |
2645 | return ret; | |
7faf1ab2 | 2646 | |
24f3a8cf | 2647 | /* Currently applicable only to VLV */ |
321d178e CW |
2648 | pte_flags = 0; |
2649 | if (vma->obj->gt_ro) | |
f329f5f6 | 2650 | pte_flags |= PTE_READ_ONLY; |
24f3a8cf | 2651 | |
ec7adb6e | 2652 | |
3272db53 | 2653 | if (flags & I915_VMA_GLOBAL_BIND) { |
321d178e | 2654 | vma->vm->insert_entries(vma->vm, |
247177dd | 2655 | vma->pages, vma->node.start, |
0875546c | 2656 | cache_level, pte_flags); |
6f65e29a | 2657 | } |
d5bd1449 | 2658 | |
3272db53 | 2659 | if (flags & I915_VMA_LOCAL_BIND) { |
321d178e CW |
2660 | struct i915_hw_ppgtt *appgtt = |
2661 | to_i915(vma->vm->dev)->mm.aliasing_ppgtt; | |
2662 | appgtt->base.insert_entries(&appgtt->base, | |
247177dd | 2663 | vma->pages, vma->node.start, |
f329f5f6 | 2664 | cache_level, pte_flags); |
6f65e29a | 2665 | } |
70b9f6f8 DV |
2666 | |
2667 | return 0; | |
d5bd1449 CW |
2668 | } |
2669 | ||
6f65e29a | 2670 | static void ggtt_unbind_vma(struct i915_vma *vma) |
74163907 | 2671 | { |
de180033 CW |
2672 | struct i915_hw_ppgtt *appgtt = to_i915(vma->vm->dev)->mm.aliasing_ppgtt; |
2673 | const u64 size = min(vma->size, vma->node.size); | |
6f65e29a | 2674 | |
3272db53 | 2675 | if (vma->flags & I915_VMA_GLOBAL_BIND) |
782f1495 | 2676 | vma->vm->clear_range(vma->vm, |
de180033 | 2677 | vma->node.start, size, |
6f65e29a | 2678 | true); |
06615ee5 | 2679 | |
3272db53 | 2680 | if (vma->flags & I915_VMA_LOCAL_BIND && appgtt) |
6f65e29a | 2681 | appgtt->base.clear_range(&appgtt->base, |
de180033 | 2682 | vma->node.start, size, |
6f65e29a | 2683 | true); |
74163907 DV |
2684 | } |
2685 | ||
2686 | void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj) | |
7c2e6fdf | 2687 | { |
5c042287 | 2688 | struct drm_device *dev = obj->base.dev; |
fac5e23e | 2689 | struct drm_i915_private *dev_priv = to_i915(dev); |
307dc25b | 2690 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
5c042287 | 2691 | |
307dc25b CW |
2692 | if (unlikely(ggtt->do_idle_maps)) { |
2693 | if (i915_gem_wait_for_idle(dev_priv, false)) { | |
2694 | DRM_ERROR("Failed to wait for idle; VT'd may hang.\n"); | |
2695 | /* Wait a bit, in hopes it avoids the hang */ | |
2696 | udelay(10); | |
2697 | } | |
2698 | } | |
5c042287 | 2699 | |
5ec5b516 ID |
2700 | dma_unmap_sg(&dev->pdev->dev, obj->pages->sgl, obj->pages->nents, |
2701 | PCI_DMA_BIDIRECTIONAL); | |
7c2e6fdf | 2702 | } |
644ec02b | 2703 | |
42d6ab48 CW |
2704 | static void i915_gtt_color_adjust(struct drm_mm_node *node, |
2705 | unsigned long color, | |
440fd528 TR |
2706 | u64 *start, |
2707 | u64 *end) | |
42d6ab48 CW |
2708 | { |
2709 | if (node->color != color) | |
2710 | *start += 4096; | |
2711 | ||
2a1d7752 CW |
2712 | node = list_first_entry_or_null(&node->node_list, |
2713 | struct drm_mm_node, | |
2714 | node_list); | |
2715 | if (node && node->allocated && node->color != color) | |
2716 | *end -= 4096; | |
42d6ab48 | 2717 | } |
fbe5d36e | 2718 | |
f6b9d5ca | 2719 | int i915_gem_init_ggtt(struct drm_i915_private *dev_priv) |
644ec02b | 2720 | { |
e78891ca BW |
2721 | /* Let GEM Manage all of the aperture. |
2722 | * | |
2723 | * However, leave one page at the end still bound to the scratch page. | |
2724 | * There are a number of places where the hardware apparently prefetches | |
2725 | * past the end of the object, and we've seen multiple hangs with the | |
2726 | * GPU head pointer stuck in a batchbuffer bound at the last page of the | |
2727 | * aperture. One page should be enough to keep any prefetching inside | |
2728 | * of the aperture. | |
2729 | */ | |
72e96d64 | 2730 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
ed2f3452 | 2731 | unsigned long hole_start, hole_end; |
f6b9d5ca | 2732 | struct drm_mm_node *entry; |
fa76da34 | 2733 | int ret; |
644ec02b | 2734 | |
b02d22a3 ZW |
2735 | ret = intel_vgt_balloon(dev_priv); |
2736 | if (ret) | |
2737 | return ret; | |
5dda8fa3 | 2738 | |
ed2f3452 | 2739 | /* Clear any non-preallocated blocks */ |
72e96d64 | 2740 | drm_mm_for_each_hole(entry, &ggtt->base.mm, hole_start, hole_end) { |
ed2f3452 CW |
2741 | DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n", |
2742 | hole_start, hole_end); | |
72e96d64 | 2743 | ggtt->base.clear_range(&ggtt->base, hole_start, |
782f1495 | 2744 | hole_end - hole_start, true); |
ed2f3452 CW |
2745 | } |
2746 | ||
2747 | /* And finally clear the reserved guard page */ | |
f6b9d5ca CW |
2748 | ggtt->base.clear_range(&ggtt->base, |
2749 | ggtt->base.total - PAGE_SIZE, PAGE_SIZE, | |
2750 | true); | |
6c5566a8 | 2751 | |
97d6d7ab | 2752 | if (USES_PPGTT(dev_priv) && !USES_FULL_PPGTT(dev_priv)) { |
fa76da34 DV |
2753 | struct i915_hw_ppgtt *ppgtt; |
2754 | ||
2755 | ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL); | |
2756 | if (!ppgtt) | |
2757 | return -ENOMEM; | |
2758 | ||
2bfa996e | 2759 | ret = __hw_ppgtt_init(ppgtt, dev_priv); |
5c5f6457 | 2760 | if (ret) { |
5c5f6457 DV |
2761 | kfree(ppgtt); |
2762 | return ret; | |
2763 | } | |
2764 | ||
2765 | if (ppgtt->base.allocate_va_range) | |
2766 | ret = ppgtt->base.allocate_va_range(&ppgtt->base, 0, | |
2767 | ppgtt->base.total); | |
4933d519 | 2768 | if (ret) { |
061dd493 | 2769 | ppgtt->base.cleanup(&ppgtt->base); |
4933d519 | 2770 | kfree(ppgtt); |
fa76da34 | 2771 | return ret; |
4933d519 | 2772 | } |
fa76da34 | 2773 | |
5c5f6457 DV |
2774 | ppgtt->base.clear_range(&ppgtt->base, |
2775 | ppgtt->base.start, | |
2776 | ppgtt->base.total, | |
2777 | true); | |
2778 | ||
fa76da34 | 2779 | dev_priv->mm.aliasing_ppgtt = ppgtt; |
72e96d64 JL |
2780 | WARN_ON(ggtt->base.bind_vma != ggtt_bind_vma); |
2781 | ggtt->base.bind_vma = aliasing_gtt_bind_vma; | |
fa76da34 DV |
2782 | } |
2783 | ||
6c5566a8 | 2784 | return 0; |
e76e9aeb BW |
2785 | } |
2786 | ||
d85489d3 JL |
2787 | /** |
2788 | * i915_ggtt_cleanup_hw - Clean up GGTT hardware initialization | |
97d6d7ab | 2789 | * @dev_priv: i915 device |
d85489d3 | 2790 | */ |
97d6d7ab | 2791 | void i915_ggtt_cleanup_hw(struct drm_i915_private *dev_priv) |
90d0a0e8 | 2792 | { |
72e96d64 | 2793 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
90d0a0e8 | 2794 | |
70e32544 DV |
2795 | if (dev_priv->mm.aliasing_ppgtt) { |
2796 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
2797 | ||
2798 | ppgtt->base.cleanup(&ppgtt->base); | |
cb7f2760 | 2799 | kfree(ppgtt); |
70e32544 DV |
2800 | } |
2801 | ||
97d6d7ab | 2802 | i915_gem_cleanup_stolen(&dev_priv->drm); |
a4eba47b | 2803 | |
72e96d64 | 2804 | if (drm_mm_initialized(&ggtt->base.mm)) { |
b02d22a3 | 2805 | intel_vgt_deballoon(dev_priv); |
5dda8fa3 | 2806 | |
72e96d64 JL |
2807 | drm_mm_takedown(&ggtt->base.mm); |
2808 | list_del(&ggtt->base.global_link); | |
90d0a0e8 DV |
2809 | } |
2810 | ||
72e96d64 | 2811 | ggtt->base.cleanup(&ggtt->base); |
f6b9d5ca CW |
2812 | |
2813 | arch_phys_wc_del(ggtt->mtrr); | |
2814 | io_mapping_free(ggtt->mappable); | |
90d0a0e8 | 2815 | } |
70e32544 | 2816 | |
2c642b07 | 2817 | static unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl) |
e76e9aeb BW |
2818 | { |
2819 | snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT; | |
2820 | snb_gmch_ctl &= SNB_GMCH_GGMS_MASK; | |
2821 | return snb_gmch_ctl << 20; | |
2822 | } | |
2823 | ||
2c642b07 | 2824 | static unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl) |
9459d252 BW |
2825 | { |
2826 | bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT; | |
2827 | bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK; | |
2828 | if (bdw_gmch_ctl) | |
2829 | bdw_gmch_ctl = 1 << bdw_gmch_ctl; | |
562d55d9 BW |
2830 | |
2831 | #ifdef CONFIG_X86_32 | |
2832 | /* Limit 32b platforms to a 2GB GGTT: 4 << 20 / pte size * PAGE_SIZE */ | |
2833 | if (bdw_gmch_ctl > 4) | |
2834 | bdw_gmch_ctl = 4; | |
2835 | #endif | |
2836 | ||
9459d252 BW |
2837 | return bdw_gmch_ctl << 20; |
2838 | } | |
2839 | ||
2c642b07 | 2840 | static unsigned int chv_get_total_gtt_size(u16 gmch_ctrl) |
d7f25f23 DL |
2841 | { |
2842 | gmch_ctrl >>= SNB_GMCH_GGMS_SHIFT; | |
2843 | gmch_ctrl &= SNB_GMCH_GGMS_MASK; | |
2844 | ||
2845 | if (gmch_ctrl) | |
2846 | return 1 << (20 + gmch_ctrl); | |
2847 | ||
2848 | return 0; | |
2849 | } | |
2850 | ||
2c642b07 | 2851 | static size_t gen6_get_stolen_size(u16 snb_gmch_ctl) |
e76e9aeb BW |
2852 | { |
2853 | snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT; | |
2854 | snb_gmch_ctl &= SNB_GMCH_GMS_MASK; | |
2855 | return snb_gmch_ctl << 25; /* 32 MB units */ | |
2856 | } | |
2857 | ||
2c642b07 | 2858 | static size_t gen8_get_stolen_size(u16 bdw_gmch_ctl) |
9459d252 BW |
2859 | { |
2860 | bdw_gmch_ctl >>= BDW_GMCH_GMS_SHIFT; | |
2861 | bdw_gmch_ctl &= BDW_GMCH_GMS_MASK; | |
2862 | return bdw_gmch_ctl << 25; /* 32 MB units */ | |
2863 | } | |
2864 | ||
d7f25f23 DL |
2865 | static size_t chv_get_stolen_size(u16 gmch_ctrl) |
2866 | { | |
2867 | gmch_ctrl >>= SNB_GMCH_GMS_SHIFT; | |
2868 | gmch_ctrl &= SNB_GMCH_GMS_MASK; | |
2869 | ||
2870 | /* | |
2871 | * 0x0 to 0x10: 32MB increments starting at 0MB | |
2872 | * 0x11 to 0x16: 4MB increments starting at 8MB | |
2873 | * 0x17 to 0x1d: 4MB increments start at 36MB | |
2874 | */ | |
2875 | if (gmch_ctrl < 0x11) | |
2876 | return gmch_ctrl << 25; | |
2877 | else if (gmch_ctrl < 0x17) | |
2878 | return (gmch_ctrl - 0x11 + 2) << 22; | |
2879 | else | |
2880 | return (gmch_ctrl - 0x17 + 9) << 22; | |
2881 | } | |
2882 | ||
66375014 DL |
2883 | static size_t gen9_get_stolen_size(u16 gen9_gmch_ctl) |
2884 | { | |
2885 | gen9_gmch_ctl >>= BDW_GMCH_GMS_SHIFT; | |
2886 | gen9_gmch_ctl &= BDW_GMCH_GMS_MASK; | |
2887 | ||
2888 | if (gen9_gmch_ctl < 0xf0) | |
2889 | return gen9_gmch_ctl << 25; /* 32 MB units */ | |
2890 | else | |
2891 | /* 4MB increments starting at 0xf0 for 4MB */ | |
2892 | return (gen9_gmch_ctl - 0xf0 + 1) << 22; | |
2893 | } | |
2894 | ||
34c998b4 | 2895 | static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size) |
63340133 | 2896 | { |
34c998b4 | 2897 | struct pci_dev *pdev = ggtt->base.dev->pdev; |
4ad2af1e | 2898 | struct i915_page_scratch *scratch_page; |
34c998b4 | 2899 | phys_addr_t phys_addr; |
63340133 BW |
2900 | |
2901 | /* For Modern GENs the PTEs and register space are split in the BAR */ | |
34c998b4 | 2902 | phys_addr = pci_resource_start(pdev, 0) + pci_resource_len(pdev, 0) / 2; |
63340133 | 2903 | |
2a073f89 ID |
2904 | /* |
2905 | * On BXT writes larger than 64 bit to the GTT pagetable range will be | |
2906 | * dropped. For WC mappings in general we have 64 byte burst writes | |
2907 | * when the WC buffer is flushed, so we can't use it, but have to | |
2908 | * resort to an uncached mapping. The WC issue is easily caught by the | |
2909 | * readback check when writing GTT PTE entries. | |
2910 | */ | |
34c998b4 CW |
2911 | if (IS_BROXTON(ggtt->base.dev)) |
2912 | ggtt->gsm = ioremap_nocache(phys_addr, size); | |
2a073f89 | 2913 | else |
34c998b4 | 2914 | ggtt->gsm = ioremap_wc(phys_addr, size); |
72e96d64 | 2915 | if (!ggtt->gsm) { |
34c998b4 | 2916 | DRM_ERROR("Failed to map the ggtt page table\n"); |
63340133 BW |
2917 | return -ENOMEM; |
2918 | } | |
2919 | ||
34c998b4 | 2920 | scratch_page = alloc_scratch_page(ggtt->base.dev); |
4ad2af1e | 2921 | if (IS_ERR(scratch_page)) { |
63340133 BW |
2922 | DRM_ERROR("Scratch setup failed\n"); |
2923 | /* iounmap will also get called at remove, but meh */ | |
72e96d64 | 2924 | iounmap(ggtt->gsm); |
4ad2af1e | 2925 | return PTR_ERR(scratch_page); |
63340133 BW |
2926 | } |
2927 | ||
72e96d64 | 2928 | ggtt->base.scratch_page = scratch_page; |
4ad2af1e MK |
2929 | |
2930 | return 0; | |
63340133 BW |
2931 | } |
2932 | ||
fbe5d36e BW |
2933 | /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability |
2934 | * bits. When using advanced contexts each context stores its own PAT, but | |
2935 | * writing this data shouldn't be harmful even in those cases. */ | |
ee0ce478 | 2936 | static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv) |
fbe5d36e | 2937 | { |
fbe5d36e BW |
2938 | uint64_t pat; |
2939 | ||
2940 | pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC) | /* for normal objects, no eLLC */ | |
2941 | GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something pointing to ptes? */ | |
2942 | GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC) | /* for scanout with eLLC */ | |
2943 | GEN8_PPAT(3, GEN8_PPAT_UC) | /* Uncached objects, mostly for scanout */ | |
2944 | GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) | | |
2945 | GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) | | |
2946 | GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) | | |
2947 | GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3)); | |
2948 | ||
2d1fe073 | 2949 | if (!USES_PPGTT(dev_priv)) |
d6a8b72e RV |
2950 | /* Spec: "For GGTT, there is NO pat_sel[2:0] from the entry, |
2951 | * so RTL will always use the value corresponding to | |
2952 | * pat_sel = 000". | |
2953 | * So let's disable cache for GGTT to avoid screen corruptions. | |
2954 | * MOCS still can be used though. | |
2955 | * - System agent ggtt writes (i.e. cpu gtt mmaps) already work | |
2956 | * before this patch, i.e. the same uncached + snooping access | |
2957 | * like on gen6/7 seems to be in effect. | |
2958 | * - So this just fixes blitter/render access. Again it looks | |
2959 | * like it's not just uncached access, but uncached + snooping. | |
2960 | * So we can still hold onto all our assumptions wrt cpu | |
2961 | * clflushing on LLC machines. | |
2962 | */ | |
2963 | pat = GEN8_PPAT(0, GEN8_PPAT_UC); | |
2964 | ||
fbe5d36e BW |
2965 | /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b |
2966 | * write would work. */ | |
7e435ad2 VS |
2967 | I915_WRITE(GEN8_PRIVATE_PAT_LO, pat); |
2968 | I915_WRITE(GEN8_PRIVATE_PAT_HI, pat >> 32); | |
fbe5d36e BW |
2969 | } |
2970 | ||
ee0ce478 VS |
2971 | static void chv_setup_private_ppat(struct drm_i915_private *dev_priv) |
2972 | { | |
2973 | uint64_t pat; | |
2974 | ||
2975 | /* | |
2976 | * Map WB on BDW to snooped on CHV. | |
2977 | * | |
2978 | * Only the snoop bit has meaning for CHV, the rest is | |
2979 | * ignored. | |
2980 | * | |
cf3d262e VS |
2981 | * The hardware will never snoop for certain types of accesses: |
2982 | * - CPU GTT (GMADR->GGTT->no snoop->memory) | |
2983 | * - PPGTT page tables | |
2984 | * - some other special cycles | |
2985 | * | |
2986 | * As with BDW, we also need to consider the following for GT accesses: | |
2987 | * "For GGTT, there is NO pat_sel[2:0] from the entry, | |
2988 | * so RTL will always use the value corresponding to | |
2989 | * pat_sel = 000". | |
2990 | * Which means we must set the snoop bit in PAT entry 0 | |
2991 | * in order to keep the global status page working. | |
ee0ce478 VS |
2992 | */ |
2993 | pat = GEN8_PPAT(0, CHV_PPAT_SNOOP) | | |
2994 | GEN8_PPAT(1, 0) | | |
2995 | GEN8_PPAT(2, 0) | | |
2996 | GEN8_PPAT(3, 0) | | |
2997 | GEN8_PPAT(4, CHV_PPAT_SNOOP) | | |
2998 | GEN8_PPAT(5, CHV_PPAT_SNOOP) | | |
2999 | GEN8_PPAT(6, CHV_PPAT_SNOOP) | | |
3000 | GEN8_PPAT(7, CHV_PPAT_SNOOP); | |
3001 | ||
7e435ad2 VS |
3002 | I915_WRITE(GEN8_PRIVATE_PAT_LO, pat); |
3003 | I915_WRITE(GEN8_PRIVATE_PAT_HI, pat >> 32); | |
ee0ce478 VS |
3004 | } |
3005 | ||
34c998b4 CW |
3006 | static void gen6_gmch_remove(struct i915_address_space *vm) |
3007 | { | |
3008 | struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm); | |
3009 | ||
3010 | iounmap(ggtt->gsm); | |
3011 | free_scratch_page(vm->dev, vm->scratch_page); | |
3012 | } | |
3013 | ||
d507d735 | 3014 | static int gen8_gmch_probe(struct i915_ggtt *ggtt) |
63340133 | 3015 | { |
97d6d7ab CW |
3016 | struct drm_i915_private *dev_priv = to_i915(ggtt->base.dev); |
3017 | struct pci_dev *pdev = dev_priv->drm.pdev; | |
34c998b4 | 3018 | unsigned int size; |
63340133 | 3019 | u16 snb_gmch_ctl; |
63340133 BW |
3020 | |
3021 | /* TODO: We're not aware of mappable constraints on gen8 yet */ | |
97d6d7ab CW |
3022 | ggtt->mappable_base = pci_resource_start(pdev, 2); |
3023 | ggtt->mappable_end = pci_resource_len(pdev, 2); | |
63340133 | 3024 | |
97d6d7ab CW |
3025 | if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(39))) |
3026 | pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(39)); | |
63340133 | 3027 | |
97d6d7ab | 3028 | pci_read_config_word(pdev, SNB_GMCH_CTRL, &snb_gmch_ctl); |
63340133 | 3029 | |
97d6d7ab | 3030 | if (INTEL_GEN(dev_priv) >= 9) { |
d507d735 | 3031 | ggtt->stolen_size = gen9_get_stolen_size(snb_gmch_ctl); |
34c998b4 | 3032 | size = gen8_get_total_gtt_size(snb_gmch_ctl); |
97d6d7ab | 3033 | } else if (IS_CHERRYVIEW(dev_priv)) { |
d507d735 | 3034 | ggtt->stolen_size = chv_get_stolen_size(snb_gmch_ctl); |
34c998b4 | 3035 | size = chv_get_total_gtt_size(snb_gmch_ctl); |
d7f25f23 | 3036 | } else { |
d507d735 | 3037 | ggtt->stolen_size = gen8_get_stolen_size(snb_gmch_ctl); |
34c998b4 | 3038 | size = gen8_get_total_gtt_size(snb_gmch_ctl); |
d7f25f23 | 3039 | } |
63340133 | 3040 | |
34c998b4 | 3041 | ggtt->base.total = (size / sizeof(gen8_pte_t)) << PAGE_SHIFT; |
63340133 | 3042 | |
97d6d7ab | 3043 | if (IS_CHERRYVIEW(dev_priv) || IS_BROXTON(dev_priv)) |
ee0ce478 VS |
3044 | chv_setup_private_ppat(dev_priv); |
3045 | else | |
3046 | bdw_setup_private_ppat(dev_priv); | |
fbe5d36e | 3047 | |
34c998b4 | 3048 | ggtt->base.cleanup = gen6_gmch_remove; |
d507d735 JL |
3049 | ggtt->base.bind_vma = ggtt_bind_vma; |
3050 | ggtt->base.unbind_vma = ggtt_unbind_vma; | |
d6473f56 | 3051 | ggtt->base.insert_page = gen8_ggtt_insert_page; |
f7770bfd | 3052 | ggtt->base.clear_range = nop_clear_range; |
48f112fe | 3053 | if (!USES_FULL_PPGTT(dev_priv) || intel_scanout_needs_vtd_wa(dev_priv)) |
f7770bfd CW |
3054 | ggtt->base.clear_range = gen8_ggtt_clear_range; |
3055 | ||
3056 | ggtt->base.insert_entries = gen8_ggtt_insert_entries; | |
3057 | if (IS_CHERRYVIEW(dev_priv)) | |
3058 | ggtt->base.insert_entries = gen8_ggtt_insert_entries__BKL; | |
3059 | ||
34c998b4 | 3060 | return ggtt_probe_common(ggtt, size); |
63340133 BW |
3061 | } |
3062 | ||
d507d735 | 3063 | static int gen6_gmch_probe(struct i915_ggtt *ggtt) |
e76e9aeb | 3064 | { |
97d6d7ab CW |
3065 | struct drm_i915_private *dev_priv = to_i915(ggtt->base.dev); |
3066 | struct pci_dev *pdev = dev_priv->drm.pdev; | |
34c998b4 | 3067 | unsigned int size; |
e76e9aeb | 3068 | u16 snb_gmch_ctl; |
e76e9aeb | 3069 | |
97d6d7ab CW |
3070 | ggtt->mappable_base = pci_resource_start(pdev, 2); |
3071 | ggtt->mappable_end = pci_resource_len(pdev, 2); | |
41907ddc | 3072 | |
baa09f5f BW |
3073 | /* 64/512MB is the current min/max we actually know of, but this is just |
3074 | * a coarse sanity check. | |
e76e9aeb | 3075 | */ |
34c998b4 | 3076 | if (ggtt->mappable_end < (64<<20) || ggtt->mappable_end > (512<<20)) { |
d507d735 | 3077 | DRM_ERROR("Unknown GMADR size (%llx)\n", ggtt->mappable_end); |
baa09f5f | 3078 | return -ENXIO; |
e76e9aeb BW |
3079 | } |
3080 | ||
97d6d7ab CW |
3081 | if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(40))) |
3082 | pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(40)); | |
3083 | pci_read_config_word(pdev, SNB_GMCH_CTRL, &snb_gmch_ctl); | |
e76e9aeb | 3084 | |
d507d735 | 3085 | ggtt->stolen_size = gen6_get_stolen_size(snb_gmch_ctl); |
e76e9aeb | 3086 | |
34c998b4 CW |
3087 | size = gen6_get_total_gtt_size(snb_gmch_ctl); |
3088 | ggtt->base.total = (size / sizeof(gen6_pte_t)) << PAGE_SHIFT; | |
e76e9aeb | 3089 | |
d507d735 | 3090 | ggtt->base.clear_range = gen6_ggtt_clear_range; |
d6473f56 | 3091 | ggtt->base.insert_page = gen6_ggtt_insert_page; |
d507d735 JL |
3092 | ggtt->base.insert_entries = gen6_ggtt_insert_entries; |
3093 | ggtt->base.bind_vma = ggtt_bind_vma; | |
3094 | ggtt->base.unbind_vma = ggtt_unbind_vma; | |
34c998b4 CW |
3095 | ggtt->base.cleanup = gen6_gmch_remove; |
3096 | ||
3097 | if (HAS_EDRAM(dev_priv)) | |
3098 | ggtt->base.pte_encode = iris_pte_encode; | |
3099 | else if (IS_HASWELL(dev_priv)) | |
3100 | ggtt->base.pte_encode = hsw_pte_encode; | |
3101 | else if (IS_VALLEYVIEW(dev_priv)) | |
3102 | ggtt->base.pte_encode = byt_pte_encode; | |
3103 | else if (INTEL_GEN(dev_priv) >= 7) | |
3104 | ggtt->base.pte_encode = ivb_pte_encode; | |
3105 | else | |
3106 | ggtt->base.pte_encode = snb_pte_encode; | |
7faf1ab2 | 3107 | |
34c998b4 | 3108 | return ggtt_probe_common(ggtt, size); |
e76e9aeb BW |
3109 | } |
3110 | ||
34c998b4 | 3111 | static void i915_gmch_remove(struct i915_address_space *vm) |
e76e9aeb | 3112 | { |
34c998b4 | 3113 | intel_gmch_remove(); |
644ec02b | 3114 | } |
baa09f5f | 3115 | |
d507d735 | 3116 | static int i915_gmch_probe(struct i915_ggtt *ggtt) |
baa09f5f | 3117 | { |
97d6d7ab | 3118 | struct drm_i915_private *dev_priv = to_i915(ggtt->base.dev); |
baa09f5f BW |
3119 | int ret; |
3120 | ||
91c8a326 | 3121 | ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->drm.pdev, NULL); |
baa09f5f BW |
3122 | if (!ret) { |
3123 | DRM_ERROR("failed to set up gmch\n"); | |
3124 | return -EIO; | |
3125 | } | |
3126 | ||
d507d735 JL |
3127 | intel_gtt_get(&ggtt->base.total, &ggtt->stolen_size, |
3128 | &ggtt->mappable_base, &ggtt->mappable_end); | |
baa09f5f | 3129 | |
97d6d7ab | 3130 | ggtt->do_idle_maps = needs_idle_maps(dev_priv); |
d6473f56 | 3131 | ggtt->base.insert_page = i915_ggtt_insert_page; |
d507d735 JL |
3132 | ggtt->base.insert_entries = i915_ggtt_insert_entries; |
3133 | ggtt->base.clear_range = i915_ggtt_clear_range; | |
3134 | ggtt->base.bind_vma = ggtt_bind_vma; | |
3135 | ggtt->base.unbind_vma = ggtt_unbind_vma; | |
34c998b4 | 3136 | ggtt->base.cleanup = i915_gmch_remove; |
baa09f5f | 3137 | |
d507d735 | 3138 | if (unlikely(ggtt->do_idle_maps)) |
c0a7f818 CW |
3139 | DRM_INFO("applying Ironlake quirks for intel_iommu\n"); |
3140 | ||
baa09f5f BW |
3141 | return 0; |
3142 | } | |
3143 | ||
d85489d3 | 3144 | /** |
0088e522 | 3145 | * i915_ggtt_probe_hw - Probe GGTT hardware location |
97d6d7ab | 3146 | * @dev_priv: i915 device |
d85489d3 | 3147 | */ |
97d6d7ab | 3148 | int i915_ggtt_probe_hw(struct drm_i915_private *dev_priv) |
baa09f5f | 3149 | { |
62106b4f | 3150 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
baa09f5f BW |
3151 | int ret; |
3152 | ||
97d6d7ab | 3153 | ggtt->base.dev = &dev_priv->drm; |
c114f76a | 3154 | |
34c998b4 CW |
3155 | if (INTEL_GEN(dev_priv) <= 5) |
3156 | ret = i915_gmch_probe(ggtt); | |
3157 | else if (INTEL_GEN(dev_priv) < 8) | |
3158 | ret = gen6_gmch_probe(ggtt); | |
3159 | else | |
3160 | ret = gen8_gmch_probe(ggtt); | |
a54c0c27 | 3161 | if (ret) |
baa09f5f | 3162 | return ret; |
baa09f5f | 3163 | |
c890e2d5 CW |
3164 | if ((ggtt->base.total - 1) >> 32) { |
3165 | DRM_ERROR("We never expected a Global GTT with more than 32bits" | |
f6b9d5ca | 3166 | " of address space! Found %lldM!\n", |
c890e2d5 CW |
3167 | ggtt->base.total >> 20); |
3168 | ggtt->base.total = 1ULL << 32; | |
3169 | ggtt->mappable_end = min(ggtt->mappable_end, ggtt->base.total); | |
3170 | } | |
3171 | ||
f6b9d5ca CW |
3172 | if (ggtt->mappable_end > ggtt->base.total) { |
3173 | DRM_ERROR("mappable aperture extends past end of GGTT," | |
3174 | " aperture=%llx, total=%llx\n", | |
3175 | ggtt->mappable_end, ggtt->base.total); | |
3176 | ggtt->mappable_end = ggtt->base.total; | |
3177 | } | |
3178 | ||
baa09f5f | 3179 | /* GMADR is the PCI mmio aperture into the global GTT. */ |
c44ef60e | 3180 | DRM_INFO("Memory usable by graphics device = %lluM\n", |
62106b4f JL |
3181 | ggtt->base.total >> 20); |
3182 | DRM_DEBUG_DRIVER("GMADR size = %lldM\n", ggtt->mappable_end >> 20); | |
3183 | DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", ggtt->stolen_size >> 20); | |
5db6c735 DV |
3184 | #ifdef CONFIG_INTEL_IOMMU |
3185 | if (intel_iommu_gfx_mapped) | |
3186 | DRM_INFO("VT-d active for gfx access\n"); | |
3187 | #endif | |
baa09f5f BW |
3188 | |
3189 | return 0; | |
0088e522 CW |
3190 | } |
3191 | ||
3192 | /** | |
3193 | * i915_ggtt_init_hw - Initialize GGTT hardware | |
97d6d7ab | 3194 | * @dev_priv: i915 device |
0088e522 | 3195 | */ |
97d6d7ab | 3196 | int i915_ggtt_init_hw(struct drm_i915_private *dev_priv) |
0088e522 | 3197 | { |
0088e522 CW |
3198 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
3199 | int ret; | |
3200 | ||
f6b9d5ca CW |
3201 | INIT_LIST_HEAD(&dev_priv->vm_list); |
3202 | ||
3203 | /* Subtract the guard page before address space initialization to | |
3204 | * shrink the range used by drm_mm. | |
3205 | */ | |
3206 | ggtt->base.total -= PAGE_SIZE; | |
3207 | i915_address_space_init(&ggtt->base, dev_priv); | |
3208 | ggtt->base.total += PAGE_SIZE; | |
3209 | if (!HAS_LLC(dev_priv)) | |
3210 | ggtt->base.mm.color_adjust = i915_gtt_color_adjust; | |
3211 | ||
3212 | ggtt->mappable = | |
3213 | io_mapping_create_wc(ggtt->mappable_base, ggtt->mappable_end); | |
3214 | if (!ggtt->mappable) { | |
3215 | ret = -EIO; | |
3216 | goto out_gtt_cleanup; | |
3217 | } | |
3218 | ||
3219 | ggtt->mtrr = arch_phys_wc_add(ggtt->mappable_base, ggtt->mappable_end); | |
3220 | ||
0088e522 CW |
3221 | /* |
3222 | * Initialise stolen early so that we may reserve preallocated | |
3223 | * objects for the BIOS to KMS transition. | |
3224 | */ | |
97d6d7ab | 3225 | ret = i915_gem_init_stolen(&dev_priv->drm); |
0088e522 CW |
3226 | if (ret) |
3227 | goto out_gtt_cleanup; | |
3228 | ||
3229 | return 0; | |
a4eba47b ID |
3230 | |
3231 | out_gtt_cleanup: | |
72e96d64 | 3232 | ggtt->base.cleanup(&ggtt->base); |
a4eba47b | 3233 | return ret; |
baa09f5f | 3234 | } |
6f65e29a | 3235 | |
97d6d7ab | 3236 | int i915_ggtt_enable_hw(struct drm_i915_private *dev_priv) |
ac840ae5 | 3237 | { |
97d6d7ab | 3238 | if (INTEL_GEN(dev_priv) < 6 && !intel_enable_gtt()) |
ac840ae5 VS |
3239 | return -EIO; |
3240 | ||
3241 | return 0; | |
3242 | } | |
3243 | ||
fa42331b DV |
3244 | void i915_gem_restore_gtt_mappings(struct drm_device *dev) |
3245 | { | |
72e96d64 JL |
3246 | struct drm_i915_private *dev_priv = to_i915(dev); |
3247 | struct i915_ggtt *ggtt = &dev_priv->ggtt; | |
fa42331b | 3248 | struct drm_i915_gem_object *obj; |
2c3d9984 | 3249 | struct i915_vma *vma; |
fa42331b | 3250 | |
dc97997a | 3251 | i915_check_and_clear_faults(dev_priv); |
fa42331b DV |
3252 | |
3253 | /* First fill our portion of the GTT with scratch pages */ | |
72e96d64 JL |
3254 | ggtt->base.clear_range(&ggtt->base, ggtt->base.start, ggtt->base.total, |
3255 | true); | |
fa42331b | 3256 | |
2c3d9984 | 3257 | /* Cache flush objects bound into GGTT and rebind them. */ |
fa42331b | 3258 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
1c7f4bca | 3259 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
72e96d64 | 3260 | if (vma->vm != &ggtt->base) |
2c3d9984 | 3261 | continue; |
fa42331b | 3262 | |
2c3d9984 TU |
3263 | WARN_ON(i915_vma_bind(vma, obj->cache_level, |
3264 | PIN_UPDATE)); | |
2c3d9984 TU |
3265 | } |
3266 | ||
975f7ff4 CW |
3267 | if (obj->pin_display) |
3268 | WARN_ON(i915_gem_object_set_to_gtt_domain(obj, false)); | |
2c3d9984 | 3269 | } |
fa42331b DV |
3270 | |
3271 | if (INTEL_INFO(dev)->gen >= 8) { | |
3272 | if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev)) | |
3273 | chv_setup_private_ppat(dev_priv); | |
3274 | else | |
3275 | bdw_setup_private_ppat(dev_priv); | |
3276 | ||
3277 | return; | |
3278 | } | |
3279 | ||
3280 | if (USES_PPGTT(dev)) { | |
72e96d64 JL |
3281 | struct i915_address_space *vm; |
3282 | ||
fa42331b DV |
3283 | list_for_each_entry(vm, &dev_priv->vm_list, global_link) { |
3284 | /* TODO: Perhaps it shouldn't be gen6 specific */ | |
3285 | ||
e5716f55 | 3286 | struct i915_hw_ppgtt *ppgtt; |
fa42331b | 3287 | |
2bfa996e | 3288 | if (i915_is_ggtt(vm)) |
fa42331b | 3289 | ppgtt = dev_priv->mm.aliasing_ppgtt; |
e5716f55 JL |
3290 | else |
3291 | ppgtt = i915_vm_to_ppgtt(vm); | |
fa42331b DV |
3292 | |
3293 | gen6_write_page_range(dev_priv, &ppgtt->pd, | |
3294 | 0, ppgtt->base.total); | |
3295 | } | |
3296 | } | |
3297 | ||
3298 | i915_ggtt_flush(dev_priv); | |
3299 | } | |
3300 | ||
b0decaf7 CW |
3301 | static void |
3302 | i915_vma_retire(struct i915_gem_active *active, | |
3303 | struct drm_i915_gem_request *rq) | |
3304 | { | |
3305 | const unsigned int idx = rq->engine->id; | |
3306 | struct i915_vma *vma = | |
3307 | container_of(active, struct i915_vma, last_read[idx]); | |
3308 | ||
3309 | GEM_BUG_ON(!i915_vma_has_active_engine(vma, idx)); | |
3310 | ||
3311 | i915_vma_clear_active(vma, idx); | |
3312 | if (i915_vma_is_active(vma)) | |
3313 | return; | |
3314 | ||
3315 | list_move_tail(&vma->vm_link, &vma->vm->inactive_list); | |
3272db53 | 3316 | if (unlikely(i915_vma_is_closed(vma) && !i915_vma_is_pinned(vma))) |
b1f788c6 CW |
3317 | WARN_ON(i915_vma_unbind(vma)); |
3318 | } | |
3319 | ||
3320 | void i915_vma_destroy(struct i915_vma *vma) | |
3321 | { | |
3322 | GEM_BUG_ON(vma->node.allocated); | |
3323 | GEM_BUG_ON(i915_vma_is_active(vma)); | |
3272db53 | 3324 | GEM_BUG_ON(!i915_vma_is_closed(vma)); |
49ef5294 | 3325 | GEM_BUG_ON(vma->fence); |
b1f788c6 CW |
3326 | |
3327 | list_del(&vma->vm_link); | |
3272db53 | 3328 | if (!i915_vma_is_ggtt(vma)) |
b1f788c6 CW |
3329 | i915_ppgtt_put(i915_vm_to_ppgtt(vma->vm)); |
3330 | ||
3331 | kmem_cache_free(to_i915(vma->obj->base.dev)->vmas, vma); | |
3332 | } | |
3333 | ||
3334 | void i915_vma_close(struct i915_vma *vma) | |
3335 | { | |
3272db53 CW |
3336 | GEM_BUG_ON(i915_vma_is_closed(vma)); |
3337 | vma->flags |= I915_VMA_CLOSED; | |
b1f788c6 CW |
3338 | |
3339 | list_del_init(&vma->obj_link); | |
20dfbde4 | 3340 | if (!i915_vma_is_active(vma) && !i915_vma_is_pinned(vma)) |
df0e9a28 | 3341 | WARN_ON(i915_vma_unbind(vma)); |
b0decaf7 CW |
3342 | } |
3343 | ||
ec7adb6e | 3344 | static struct i915_vma * |
058d88c4 CW |
3345 | __i915_vma_create(struct drm_i915_gem_object *obj, |
3346 | struct i915_address_space *vm, | |
3347 | const struct i915_ggtt_view *view) | |
6f65e29a | 3348 | { |
dabde5c7 | 3349 | struct i915_vma *vma; |
b0decaf7 | 3350 | int i; |
6f65e29a | 3351 | |
50e046b6 CW |
3352 | GEM_BUG_ON(vm->closed); |
3353 | ||
e20d2ab7 | 3354 | vma = kmem_cache_zalloc(to_i915(obj->base.dev)->vmas, GFP_KERNEL); |
dabde5c7 DC |
3355 | if (vma == NULL) |
3356 | return ERR_PTR(-ENOMEM); | |
ec7adb6e | 3357 | |
6f65e29a | 3358 | INIT_LIST_HEAD(&vma->exec_list); |
b0decaf7 CW |
3359 | for (i = 0; i < ARRAY_SIZE(vma->last_read); i++) |
3360 | init_request_active(&vma->last_read[i], i915_vma_retire); | |
49ef5294 | 3361 | init_request_active(&vma->last_fence, NULL); |
50e046b6 | 3362 | list_add(&vma->vm_link, &vm->unbound_list); |
6f65e29a BW |
3363 | vma->vm = vm; |
3364 | vma->obj = obj; | |
de180033 | 3365 | vma->size = obj->base.size; |
6f65e29a | 3366 | |
058d88c4 | 3367 | if (view) { |
de180033 CW |
3368 | vma->ggtt_view = *view; |
3369 | if (view->type == I915_GGTT_VIEW_PARTIAL) { | |
3370 | vma->size = view->params.partial.size; | |
3371 | vma->size <<= PAGE_SHIFT; | |
3372 | } else if (view->type == I915_GGTT_VIEW_ROTATED) { | |
3373 | vma->size = | |
3374 | intel_rotation_info_size(&view->params.rotated); | |
3375 | vma->size <<= PAGE_SHIFT; | |
3376 | } | |
058d88c4 CW |
3377 | } |
3378 | ||
3379 | if (i915_is_ggtt(vm)) { | |
3380 | vma->flags |= I915_VMA_GGTT; | |
de180033 | 3381 | } else { |
596c5923 | 3382 | i915_ppgtt_get(i915_vm_to_ppgtt(vm)); |
de180033 | 3383 | } |
6f65e29a | 3384 | |
1c7f4bca | 3385 | list_add_tail(&vma->obj_link, &obj->vma_list); |
6f65e29a BW |
3386 | return vma; |
3387 | } | |
3388 | ||
058d88c4 CW |
3389 | static inline bool vma_matches(struct i915_vma *vma, |
3390 | struct i915_address_space *vm, | |
3391 | const struct i915_ggtt_view *view) | |
3392 | { | |
3393 | if (vma->vm != vm) | |
3394 | return false; | |
3395 | ||
3396 | if (!i915_vma_is_ggtt(vma)) | |
3397 | return true; | |
3398 | ||
3399 | if (!view) | |
3400 | return vma->ggtt_view.type == 0; | |
3401 | ||
3402 | if (vma->ggtt_view.type != view->type) | |
3403 | return false; | |
3404 | ||
3405 | return memcmp(&vma->ggtt_view.params, | |
3406 | &view->params, | |
3407 | sizeof(view->params)) == 0; | |
3408 | } | |
3409 | ||
81a8aa4a CW |
3410 | struct i915_vma * |
3411 | i915_vma_create(struct drm_i915_gem_object *obj, | |
3412 | struct i915_address_space *vm, | |
3413 | const struct i915_ggtt_view *view) | |
3414 | { | |
3415 | GEM_BUG_ON(view && !i915_is_ggtt(vm)); | |
058d88c4 | 3416 | GEM_BUG_ON(i915_gem_obj_to_vma(obj, vm, view)); |
81a8aa4a | 3417 | |
058d88c4 | 3418 | return __i915_vma_create(obj, vm, view); |
81a8aa4a CW |
3419 | } |
3420 | ||
6f65e29a | 3421 | struct i915_vma * |
058d88c4 CW |
3422 | i915_gem_obj_to_vma(struct drm_i915_gem_object *obj, |
3423 | struct i915_address_space *vm, | |
3424 | const struct i915_ggtt_view *view) | |
ec7adb6e JL |
3425 | { |
3426 | struct i915_vma *vma; | |
3427 | ||
058d88c4 CW |
3428 | list_for_each_entry_reverse(vma, &obj->vma_list, obj_link) |
3429 | if (vma_matches(vma, vm, view)) | |
3430 | return vma; | |
ec7adb6e | 3431 | |
058d88c4 | 3432 | return NULL; |
ec7adb6e JL |
3433 | } |
3434 | ||
3435 | struct i915_vma * | |
058d88c4 CW |
3436 | i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj, |
3437 | struct i915_address_space *vm, | |
3438 | const struct i915_ggtt_view *view) | |
6f65e29a | 3439 | { |
058d88c4 | 3440 | struct i915_vma *vma; |
ec7adb6e | 3441 | |
058d88c4 | 3442 | GEM_BUG_ON(view && !i915_is_ggtt(vm)); |
de895082 | 3443 | |
058d88c4 | 3444 | vma = i915_gem_obj_to_vma(obj, vm, view); |
6f65e29a | 3445 | if (!vma) |
058d88c4 | 3446 | vma = __i915_vma_create(obj, vm, view); |
6f65e29a | 3447 | |
3272db53 | 3448 | GEM_BUG_ON(i915_vma_is_closed(vma)); |
6f65e29a BW |
3449 | return vma; |
3450 | } | |
fe14d5f4 | 3451 | |
804beb4b | 3452 | static struct scatterlist * |
2d7f3bdb | 3453 | rotate_pages(const dma_addr_t *in, unsigned int offset, |
804beb4b | 3454 | unsigned int width, unsigned int height, |
87130255 | 3455 | unsigned int stride, |
804beb4b | 3456 | struct sg_table *st, struct scatterlist *sg) |
50470bb0 TU |
3457 | { |
3458 | unsigned int column, row; | |
3459 | unsigned int src_idx; | |
50470bb0 | 3460 | |
50470bb0 | 3461 | for (column = 0; column < width; column++) { |
87130255 | 3462 | src_idx = stride * (height - 1) + column; |
50470bb0 TU |
3463 | for (row = 0; row < height; row++) { |
3464 | st->nents++; | |
3465 | /* We don't need the pages, but need to initialize | |
3466 | * the entries so the sg list can be happily traversed. | |
3467 | * The only thing we need are DMA addresses. | |
3468 | */ | |
3469 | sg_set_page(sg, NULL, PAGE_SIZE, 0); | |
804beb4b | 3470 | sg_dma_address(sg) = in[offset + src_idx]; |
50470bb0 TU |
3471 | sg_dma_len(sg) = PAGE_SIZE; |
3472 | sg = sg_next(sg); | |
87130255 | 3473 | src_idx -= stride; |
50470bb0 TU |
3474 | } |
3475 | } | |
804beb4b TU |
3476 | |
3477 | return sg; | |
50470bb0 TU |
3478 | } |
3479 | ||
3480 | static struct sg_table * | |
6687c906 | 3481 | intel_rotate_fb_obj_pages(const struct intel_rotation_info *rot_info, |
50470bb0 TU |
3482 | struct drm_i915_gem_object *obj) |
3483 | { | |
85d1225e | 3484 | const size_t n_pages = obj->base.size / PAGE_SIZE; |
6687c906 | 3485 | unsigned int size = intel_rotation_info_size(rot_info); |
85d1225e DG |
3486 | struct sgt_iter sgt_iter; |
3487 | dma_addr_t dma_addr; | |
50470bb0 TU |
3488 | unsigned long i; |
3489 | dma_addr_t *page_addr_list; | |
3490 | struct sg_table *st; | |
89e3e142 | 3491 | struct scatterlist *sg; |
1d00dad5 | 3492 | int ret = -ENOMEM; |
50470bb0 | 3493 | |
50470bb0 | 3494 | /* Allocate a temporary list of source pages for random access. */ |
85d1225e | 3495 | page_addr_list = drm_malloc_gfp(n_pages, |
f2a85e19 CW |
3496 | sizeof(dma_addr_t), |
3497 | GFP_TEMPORARY); | |
50470bb0 TU |
3498 | if (!page_addr_list) |
3499 | return ERR_PTR(ret); | |
3500 | ||
3501 | /* Allocate target SG list. */ | |
3502 | st = kmalloc(sizeof(*st), GFP_KERNEL); | |
3503 | if (!st) | |
3504 | goto err_st_alloc; | |
3505 | ||
6687c906 | 3506 | ret = sg_alloc_table(st, size, GFP_KERNEL); |
50470bb0 TU |
3507 | if (ret) |
3508 | goto err_sg_alloc; | |
3509 | ||
3510 | /* Populate source page list from the object. */ | |
3511 | i = 0; | |
85d1225e DG |
3512 | for_each_sgt_dma(dma_addr, sgt_iter, obj->pages) |
3513 | page_addr_list[i++] = dma_addr; | |
50470bb0 | 3514 | |
85d1225e | 3515 | GEM_BUG_ON(i != n_pages); |
11f20322 VS |
3516 | st->nents = 0; |
3517 | sg = st->sgl; | |
3518 | ||
6687c906 VS |
3519 | for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++) { |
3520 | sg = rotate_pages(page_addr_list, rot_info->plane[i].offset, | |
3521 | rot_info->plane[i].width, rot_info->plane[i].height, | |
3522 | rot_info->plane[i].stride, st, sg); | |
89e3e142 TU |
3523 | } |
3524 | ||
6687c906 VS |
3525 | DRM_DEBUG_KMS("Created rotated page mapping for object size %zu (%ux%u tiles, %u pages)\n", |
3526 | obj->base.size, rot_info->plane[0].width, rot_info->plane[0].height, size); | |
50470bb0 TU |
3527 | |
3528 | drm_free_large(page_addr_list); | |
3529 | ||
3530 | return st; | |
3531 | ||
3532 | err_sg_alloc: | |
3533 | kfree(st); | |
3534 | err_st_alloc: | |
3535 | drm_free_large(page_addr_list); | |
3536 | ||
6687c906 VS |
3537 | DRM_DEBUG_KMS("Failed to create rotated mapping for object size %zu! (%ux%u tiles, %u pages)\n", |
3538 | obj->base.size, rot_info->plane[0].width, rot_info->plane[0].height, size); | |
3539 | ||
50470bb0 TU |
3540 | return ERR_PTR(ret); |
3541 | } | |
ec7adb6e | 3542 | |
8bd7ef16 JL |
3543 | static struct sg_table * |
3544 | intel_partial_pages(const struct i915_ggtt_view *view, | |
3545 | struct drm_i915_gem_object *obj) | |
3546 | { | |
3547 | struct sg_table *st; | |
3548 | struct scatterlist *sg; | |
3549 | struct sg_page_iter obj_sg_iter; | |
3550 | int ret = -ENOMEM; | |
3551 | ||
3552 | st = kmalloc(sizeof(*st), GFP_KERNEL); | |
3553 | if (!st) | |
3554 | goto err_st_alloc; | |
3555 | ||
3556 | ret = sg_alloc_table(st, view->params.partial.size, GFP_KERNEL); | |
3557 | if (ret) | |
3558 | goto err_sg_alloc; | |
3559 | ||
3560 | sg = st->sgl; | |
3561 | st->nents = 0; | |
3562 | for_each_sg_page(obj->pages->sgl, &obj_sg_iter, obj->pages->nents, | |
3563 | view->params.partial.offset) | |
3564 | { | |
3565 | if (st->nents >= view->params.partial.size) | |
3566 | break; | |
3567 | ||
3568 | sg_set_page(sg, NULL, PAGE_SIZE, 0); | |
3569 | sg_dma_address(sg) = sg_page_iter_dma_address(&obj_sg_iter); | |
3570 | sg_dma_len(sg) = PAGE_SIZE; | |
3571 | ||
3572 | sg = sg_next(sg); | |
3573 | st->nents++; | |
3574 | } | |
3575 | ||
3576 | return st; | |
3577 | ||
3578 | err_sg_alloc: | |
3579 | kfree(st); | |
3580 | err_st_alloc: | |
3581 | return ERR_PTR(ret); | |
3582 | } | |
3583 | ||
70b9f6f8 | 3584 | static int |
50470bb0 | 3585 | i915_get_ggtt_vma_pages(struct i915_vma *vma) |
fe14d5f4 | 3586 | { |
50470bb0 TU |
3587 | int ret = 0; |
3588 | ||
247177dd | 3589 | if (vma->pages) |
fe14d5f4 TU |
3590 | return 0; |
3591 | ||
3592 | if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) | |
247177dd | 3593 | vma->pages = vma->obj->pages; |
50470bb0 | 3594 | else if (vma->ggtt_view.type == I915_GGTT_VIEW_ROTATED) |
247177dd | 3595 | vma->pages = |
11d23e6f | 3596 | intel_rotate_fb_obj_pages(&vma->ggtt_view.params.rotated, vma->obj); |
8bd7ef16 | 3597 | else if (vma->ggtt_view.type == I915_GGTT_VIEW_PARTIAL) |
247177dd | 3598 | vma->pages = intel_partial_pages(&vma->ggtt_view, vma->obj); |
fe14d5f4 TU |
3599 | else |
3600 | WARN_ONCE(1, "GGTT view %u not implemented!\n", | |
3601 | vma->ggtt_view.type); | |
3602 | ||
247177dd | 3603 | if (!vma->pages) { |
ec7adb6e | 3604 | DRM_ERROR("Failed to get pages for GGTT view type %u!\n", |
fe14d5f4 | 3605 | vma->ggtt_view.type); |
50470bb0 | 3606 | ret = -EINVAL; |
247177dd CW |
3607 | } else if (IS_ERR(vma->pages)) { |
3608 | ret = PTR_ERR(vma->pages); | |
3609 | vma->pages = NULL; | |
50470bb0 TU |
3610 | DRM_ERROR("Failed to get pages for VMA view type %u (%d)!\n", |
3611 | vma->ggtt_view.type, ret); | |
fe14d5f4 TU |
3612 | } |
3613 | ||
50470bb0 | 3614 | return ret; |
fe14d5f4 TU |
3615 | } |
3616 | ||
3617 | /** | |
3618 | * i915_vma_bind - Sets up PTEs for an VMA in it's corresponding address space. | |
3619 | * @vma: VMA to map | |
3620 | * @cache_level: mapping cache level | |
3621 | * @flags: flags like global or local mapping | |
3622 | * | |
3623 | * DMA addresses are taken from the scatter-gather table of this object (or of | |
3624 | * this VMA in case of non-default GGTT views) and PTE entries set up. | |
3625 | * Note that DMA addresses are also the only part of the SG table we care about. | |
3626 | */ | |
3627 | int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level, | |
3628 | u32 flags) | |
3629 | { | |
75d04a37 | 3630 | u32 bind_flags; |
3272db53 CW |
3631 | u32 vma_flags; |
3632 | int ret; | |
1d335d1b | 3633 | |
75d04a37 MK |
3634 | if (WARN_ON(flags == 0)) |
3635 | return -EINVAL; | |
1d335d1b | 3636 | |
75d04a37 | 3637 | bind_flags = 0; |
0875546c | 3638 | if (flags & PIN_GLOBAL) |
3272db53 | 3639 | bind_flags |= I915_VMA_GLOBAL_BIND; |
0875546c | 3640 | if (flags & PIN_USER) |
3272db53 | 3641 | bind_flags |= I915_VMA_LOCAL_BIND; |
0875546c | 3642 | |
3272db53 | 3643 | vma_flags = vma->flags & (I915_VMA_GLOBAL_BIND | I915_VMA_LOCAL_BIND); |
0875546c | 3644 | if (flags & PIN_UPDATE) |
3272db53 | 3645 | bind_flags |= vma_flags; |
0875546c | 3646 | else |
3272db53 | 3647 | bind_flags &= ~vma_flags; |
75d04a37 MK |
3648 | if (bind_flags == 0) |
3649 | return 0; | |
3650 | ||
3272db53 | 3651 | if (vma_flags == 0 && vma->vm->allocate_va_range) { |
596c5923 | 3652 | trace_i915_va_alloc(vma); |
75d04a37 MK |
3653 | ret = vma->vm->allocate_va_range(vma->vm, |
3654 | vma->node.start, | |
3655 | vma->node.size); | |
3656 | if (ret) | |
3657 | return ret; | |
3658 | } | |
3659 | ||
3660 | ret = vma->vm->bind_vma(vma, cache_level, bind_flags); | |
70b9f6f8 DV |
3661 | if (ret) |
3662 | return ret; | |
0875546c | 3663 | |
3272db53 | 3664 | vma->flags |= bind_flags; |
fe14d5f4 TU |
3665 | return 0; |
3666 | } | |
91e6711e | 3667 | |
8ef8561f CW |
3668 | void __iomem *i915_vma_pin_iomap(struct i915_vma *vma) |
3669 | { | |
3670 | void __iomem *ptr; | |
3671 | ||
e5cdb22b CW |
3672 | /* Access through the GTT requires the device to be awake. */ |
3673 | assert_rpm_wakelock_held(to_i915(vma->vm->dev)); | |
3674 | ||
8ef8561f | 3675 | lockdep_assert_held(&vma->vm->dev->struct_mutex); |
05a20d09 | 3676 | if (WARN_ON(!i915_vma_is_map_and_fenceable(vma))) |
406ea8d2 | 3677 | return IO_ERR_PTR(-ENODEV); |
8ef8561f | 3678 | |
3272db53 CW |
3679 | GEM_BUG_ON(!i915_vma_is_ggtt(vma)); |
3680 | GEM_BUG_ON((vma->flags & I915_VMA_GLOBAL_BIND) == 0); | |
8ef8561f CW |
3681 | |
3682 | ptr = vma->iomap; | |
3683 | if (ptr == NULL) { | |
3684 | ptr = io_mapping_map_wc(i915_vm_to_ggtt(vma->vm)->mappable, | |
3685 | vma->node.start, | |
3686 | vma->node.size); | |
3687 | if (ptr == NULL) | |
406ea8d2 | 3688 | return IO_ERR_PTR(-ENOMEM); |
8ef8561f CW |
3689 | |
3690 | vma->iomap = ptr; | |
3691 | } | |
3692 | ||
20dfbde4 | 3693 | __i915_vma_pin(vma); |
8ef8561f CW |
3694 | return ptr; |
3695 | } | |
19880c4a CW |
3696 | |
3697 | void i915_vma_unpin_and_release(struct i915_vma **p_vma) | |
3698 | { | |
3699 | struct i915_vma *vma; | |
3700 | ||
3701 | vma = fetch_and_zero(p_vma); | |
3702 | if (!vma) | |
3703 | return; | |
3704 | ||
3705 | i915_vma_unpin(vma); | |
3706 | i915_vma_put(vma); | |
3707 | } |