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76aaf220 DV |
1 | /* |
2 | * Copyright © 2010 Daniel Vetter | |
c4ac524c | 3 | * Copyright © 2011-2014 Intel Corporation |
76aaf220 DV |
4 | * |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
22 | * IN THE SOFTWARE. | |
23 | * | |
24 | */ | |
25 | ||
0e46ce2e | 26 | #include <linux/seq_file.h> |
5bab6f60 | 27 | #include <linux/stop_machine.h> |
760285e7 DH |
28 | #include <drm/drmP.h> |
29 | #include <drm/i915_drm.h> | |
76aaf220 | 30 | #include "i915_drv.h" |
5dda8fa3 | 31 | #include "i915_vgpu.h" |
76aaf220 DV |
32 | #include "i915_trace.h" |
33 | #include "intel_drv.h" | |
34 | ||
45f8f69a TU |
35 | /** |
36 | * DOC: Global GTT views | |
37 | * | |
38 | * Background and previous state | |
39 | * | |
40 | * Historically objects could exists (be bound) in global GTT space only as | |
41 | * singular instances with a view representing all of the object's backing pages | |
42 | * in a linear fashion. This view will be called a normal view. | |
43 | * | |
44 | * To support multiple views of the same object, where the number of mapped | |
45 | * pages is not equal to the backing store, or where the layout of the pages | |
46 | * is not linear, concept of a GGTT view was added. | |
47 | * | |
48 | * One example of an alternative view is a stereo display driven by a single | |
49 | * image. In this case we would have a framebuffer looking like this | |
50 | * (2x2 pages): | |
51 | * | |
52 | * 12 | |
53 | * 34 | |
54 | * | |
55 | * Above would represent a normal GGTT view as normally mapped for GPU or CPU | |
56 | * rendering. In contrast, fed to the display engine would be an alternative | |
57 | * view which could look something like this: | |
58 | * | |
59 | * 1212 | |
60 | * 3434 | |
61 | * | |
62 | * In this example both the size and layout of pages in the alternative view is | |
63 | * different from the normal view. | |
64 | * | |
65 | * Implementation and usage | |
66 | * | |
67 | * GGTT views are implemented using VMAs and are distinguished via enum | |
68 | * i915_ggtt_view_type and struct i915_ggtt_view. | |
69 | * | |
70 | * A new flavour of core GEM functions which work with GGTT bound objects were | |
ec7adb6e JL |
71 | * added with the _ggtt_ infix, and sometimes with _view postfix to avoid |
72 | * renaming in large amounts of code. They take the struct i915_ggtt_view | |
73 | * parameter encapsulating all metadata required to implement a view. | |
45f8f69a TU |
74 | * |
75 | * As a helper for callers which are only interested in the normal view, | |
76 | * globally const i915_ggtt_view_normal singleton instance exists. All old core | |
77 | * GEM API functions, the ones not taking the view parameter, are operating on, | |
78 | * or with the normal GGTT view. | |
79 | * | |
80 | * Code wanting to add or use a new GGTT view needs to: | |
81 | * | |
82 | * 1. Add a new enum with a suitable name. | |
83 | * 2. Extend the metadata in the i915_ggtt_view structure if required. | |
84 | * 3. Add support to i915_get_vma_pages(). | |
85 | * | |
86 | * New views are required to build a scatter-gather table from within the | |
87 | * i915_get_vma_pages function. This table is stored in the vma.ggtt_view and | |
88 | * exists for the lifetime of an VMA. | |
89 | * | |
90 | * Core API is designed to have copy semantics which means that passed in | |
91 | * struct i915_ggtt_view does not need to be persistent (left around after | |
92 | * calling the core API functions). | |
93 | * | |
94 | */ | |
95 | ||
ce7fda2e CW |
96 | static inline struct i915_ggtt * |
97 | i915_vm_to_ggtt(struct i915_address_space *vm) | |
98 | { | |
99 | GEM_BUG_ON(!i915_is_ggtt(vm)); | |
100 | return container_of(vm, struct i915_ggtt, base); | |
101 | } | |
102 | ||
70b9f6f8 DV |
103 | static int |
104 | i915_get_ggtt_vma_pages(struct i915_vma *vma); | |
105 | ||
b5e16987 VS |
106 | const struct i915_ggtt_view i915_ggtt_view_normal = { |
107 | .type = I915_GGTT_VIEW_NORMAL, | |
108 | }; | |
9abc4648 | 109 | const struct i915_ggtt_view i915_ggtt_view_rotated = { |
b5e16987 | 110 | .type = I915_GGTT_VIEW_ROTATED, |
9abc4648 | 111 | }; |
fe14d5f4 | 112 | |
0e4ca100 | 113 | int intel_sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt) |
cfa7c862 | 114 | { |
1893a71b CW |
115 | bool has_aliasing_ppgtt; |
116 | bool has_full_ppgtt; | |
1f9a99e0 | 117 | bool has_full_48bit_ppgtt; |
1893a71b CW |
118 | |
119 | has_aliasing_ppgtt = INTEL_INFO(dev)->gen >= 6; | |
120 | has_full_ppgtt = INTEL_INFO(dev)->gen >= 7; | |
1f9a99e0 | 121 | has_full_48bit_ppgtt = IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9; |
1893a71b | 122 | |
71ba2d64 YZ |
123 | if (intel_vgpu_active(dev)) |
124 | has_full_ppgtt = false; /* emulation is too hard */ | |
125 | ||
0e4ca100 CW |
126 | if (!has_aliasing_ppgtt) |
127 | return 0; | |
128 | ||
70ee45e1 DL |
129 | /* |
130 | * We don't allow disabling PPGTT for gen9+ as it's a requirement for | |
131 | * execlists, the sole mechanism available to submit work. | |
132 | */ | |
0e4ca100 | 133 | if (enable_ppgtt == 0 && INTEL_INFO(dev)->gen < 9) |
cfa7c862 DV |
134 | return 0; |
135 | ||
136 | if (enable_ppgtt == 1) | |
137 | return 1; | |
138 | ||
1893a71b | 139 | if (enable_ppgtt == 2 && has_full_ppgtt) |
cfa7c862 DV |
140 | return 2; |
141 | ||
1f9a99e0 MT |
142 | if (enable_ppgtt == 3 && has_full_48bit_ppgtt) |
143 | return 3; | |
144 | ||
93a25a9e DV |
145 | #ifdef CONFIG_INTEL_IOMMU |
146 | /* Disable ppgtt on SNB if VT-d is on. */ | |
147 | if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) { | |
148 | DRM_INFO("Disabling PPGTT because VT-d is on\n"); | |
cfa7c862 | 149 | return 0; |
93a25a9e DV |
150 | } |
151 | #endif | |
152 | ||
62942ed7 | 153 | /* Early VLV doesn't have this */ |
666a4537 | 154 | if (IS_VALLEYVIEW(dev) && dev->pdev->revision < 0xb) { |
62942ed7 JB |
155 | DRM_DEBUG_DRIVER("disabling PPGTT on pre-B3 step VLV\n"); |
156 | return 0; | |
157 | } | |
158 | ||
2f82bbdf | 159 | if (INTEL_INFO(dev)->gen >= 8 && i915.enable_execlists) |
1f9a99e0 | 160 | return has_full_48bit_ppgtt ? 3 : 2; |
2f82bbdf MT |
161 | else |
162 | return has_aliasing_ppgtt ? 1 : 0; | |
93a25a9e DV |
163 | } |
164 | ||
70b9f6f8 DV |
165 | static int ppgtt_bind_vma(struct i915_vma *vma, |
166 | enum i915_cache_level cache_level, | |
167 | u32 unused) | |
47552659 DV |
168 | { |
169 | u32 pte_flags = 0; | |
170 | ||
171 | /* Currently applicable only to VLV */ | |
172 | if (vma->obj->gt_ro) | |
173 | pte_flags |= PTE_READ_ONLY; | |
174 | ||
175 | vma->vm->insert_entries(vma->vm, vma->obj->pages, vma->node.start, | |
176 | cache_level, pte_flags); | |
70b9f6f8 DV |
177 | |
178 | return 0; | |
47552659 DV |
179 | } |
180 | ||
181 | static void ppgtt_unbind_vma(struct i915_vma *vma) | |
182 | { | |
183 | vma->vm->clear_range(vma->vm, | |
184 | vma->node.start, | |
185 | vma->obj->base.size, | |
186 | true); | |
187 | } | |
6f65e29a | 188 | |
2c642b07 DV |
189 | static gen8_pte_t gen8_pte_encode(dma_addr_t addr, |
190 | enum i915_cache_level level, | |
191 | bool valid) | |
94ec8f61 | 192 | { |
07749ef3 | 193 | gen8_pte_t pte = valid ? _PAGE_PRESENT | _PAGE_RW : 0; |
94ec8f61 | 194 | pte |= addr; |
63c42e56 BW |
195 | |
196 | switch (level) { | |
197 | case I915_CACHE_NONE: | |
fbe5d36e | 198 | pte |= PPAT_UNCACHED_INDEX; |
63c42e56 BW |
199 | break; |
200 | case I915_CACHE_WT: | |
201 | pte |= PPAT_DISPLAY_ELLC_INDEX; | |
202 | break; | |
203 | default: | |
204 | pte |= PPAT_CACHED_INDEX; | |
205 | break; | |
206 | } | |
207 | ||
94ec8f61 BW |
208 | return pte; |
209 | } | |
210 | ||
fe36f55d MK |
211 | static gen8_pde_t gen8_pde_encode(const dma_addr_t addr, |
212 | const enum i915_cache_level level) | |
b1fe6673 | 213 | { |
07749ef3 | 214 | gen8_pde_t pde = _PAGE_PRESENT | _PAGE_RW; |
b1fe6673 BW |
215 | pde |= addr; |
216 | if (level != I915_CACHE_NONE) | |
217 | pde |= PPAT_CACHED_PDE_INDEX; | |
218 | else | |
219 | pde |= PPAT_UNCACHED_INDEX; | |
220 | return pde; | |
221 | } | |
222 | ||
762d9936 MT |
223 | #define gen8_pdpe_encode gen8_pde_encode |
224 | #define gen8_pml4e_encode gen8_pde_encode | |
225 | ||
07749ef3 MT |
226 | static gen6_pte_t snb_pte_encode(dma_addr_t addr, |
227 | enum i915_cache_level level, | |
228 | bool valid, u32 unused) | |
54d12527 | 229 | { |
07749ef3 | 230 | gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
54d12527 | 231 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
e7210c3c BW |
232 | |
233 | switch (level) { | |
350ec881 CW |
234 | case I915_CACHE_L3_LLC: |
235 | case I915_CACHE_LLC: | |
236 | pte |= GEN6_PTE_CACHE_LLC; | |
237 | break; | |
238 | case I915_CACHE_NONE: | |
239 | pte |= GEN6_PTE_UNCACHED; | |
240 | break; | |
241 | default: | |
5f77eeb0 | 242 | MISSING_CASE(level); |
350ec881 CW |
243 | } |
244 | ||
245 | return pte; | |
246 | } | |
247 | ||
07749ef3 MT |
248 | static gen6_pte_t ivb_pte_encode(dma_addr_t addr, |
249 | enum i915_cache_level level, | |
250 | bool valid, u32 unused) | |
350ec881 | 251 | { |
07749ef3 | 252 | gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
350ec881 CW |
253 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
254 | ||
255 | switch (level) { | |
256 | case I915_CACHE_L3_LLC: | |
257 | pte |= GEN7_PTE_CACHE_L3_LLC; | |
e7210c3c BW |
258 | break; |
259 | case I915_CACHE_LLC: | |
260 | pte |= GEN6_PTE_CACHE_LLC; | |
261 | break; | |
262 | case I915_CACHE_NONE: | |
9119708c | 263 | pte |= GEN6_PTE_UNCACHED; |
e7210c3c BW |
264 | break; |
265 | default: | |
5f77eeb0 | 266 | MISSING_CASE(level); |
e7210c3c BW |
267 | } |
268 | ||
54d12527 BW |
269 | return pte; |
270 | } | |
271 | ||
07749ef3 MT |
272 | static gen6_pte_t byt_pte_encode(dma_addr_t addr, |
273 | enum i915_cache_level level, | |
274 | bool valid, u32 flags) | |
93c34e70 | 275 | { |
07749ef3 | 276 | gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
93c34e70 KG |
277 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
278 | ||
24f3a8cf AG |
279 | if (!(flags & PTE_READ_ONLY)) |
280 | pte |= BYT_PTE_WRITEABLE; | |
93c34e70 KG |
281 | |
282 | if (level != I915_CACHE_NONE) | |
283 | pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES; | |
284 | ||
285 | return pte; | |
286 | } | |
287 | ||
07749ef3 MT |
288 | static gen6_pte_t hsw_pte_encode(dma_addr_t addr, |
289 | enum i915_cache_level level, | |
290 | bool valid, u32 unused) | |
9119708c | 291 | { |
07749ef3 | 292 | gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
0d8ff15e | 293 | pte |= HSW_PTE_ADDR_ENCODE(addr); |
9119708c KG |
294 | |
295 | if (level != I915_CACHE_NONE) | |
87a6b688 | 296 | pte |= HSW_WB_LLC_AGE3; |
9119708c KG |
297 | |
298 | return pte; | |
299 | } | |
300 | ||
07749ef3 MT |
301 | static gen6_pte_t iris_pte_encode(dma_addr_t addr, |
302 | enum i915_cache_level level, | |
303 | bool valid, u32 unused) | |
4d15c145 | 304 | { |
07749ef3 | 305 | gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
4d15c145 BW |
306 | pte |= HSW_PTE_ADDR_ENCODE(addr); |
307 | ||
651d794f CW |
308 | switch (level) { |
309 | case I915_CACHE_NONE: | |
310 | break; | |
311 | case I915_CACHE_WT: | |
c51e9701 | 312 | pte |= HSW_WT_ELLC_LLC_AGE3; |
651d794f CW |
313 | break; |
314 | default: | |
c51e9701 | 315 | pte |= HSW_WB_ELLC_LLC_AGE3; |
651d794f CW |
316 | break; |
317 | } | |
4d15c145 BW |
318 | |
319 | return pte; | |
320 | } | |
321 | ||
c114f76a MK |
322 | static int __setup_page_dma(struct drm_device *dev, |
323 | struct i915_page_dma *p, gfp_t flags) | |
678d96fb BW |
324 | { |
325 | struct device *device = &dev->pdev->dev; | |
326 | ||
c114f76a | 327 | p->page = alloc_page(flags); |
44159ddb MK |
328 | if (!p->page) |
329 | return -ENOMEM; | |
678d96fb | 330 | |
44159ddb MK |
331 | p->daddr = dma_map_page(device, |
332 | p->page, 0, 4096, PCI_DMA_BIDIRECTIONAL); | |
678d96fb | 333 | |
44159ddb MK |
334 | if (dma_mapping_error(device, p->daddr)) { |
335 | __free_page(p->page); | |
336 | return -EINVAL; | |
337 | } | |
1266cdb1 MT |
338 | |
339 | return 0; | |
678d96fb BW |
340 | } |
341 | ||
c114f76a MK |
342 | static int setup_page_dma(struct drm_device *dev, struct i915_page_dma *p) |
343 | { | |
344 | return __setup_page_dma(dev, p, GFP_KERNEL); | |
345 | } | |
346 | ||
44159ddb | 347 | static void cleanup_page_dma(struct drm_device *dev, struct i915_page_dma *p) |
06fda602 | 348 | { |
44159ddb | 349 | if (WARN_ON(!p->page)) |
06fda602 | 350 | return; |
678d96fb | 351 | |
44159ddb MK |
352 | dma_unmap_page(&dev->pdev->dev, p->daddr, 4096, PCI_DMA_BIDIRECTIONAL); |
353 | __free_page(p->page); | |
354 | memset(p, 0, sizeof(*p)); | |
355 | } | |
356 | ||
d1c54acd | 357 | static void *kmap_page_dma(struct i915_page_dma *p) |
73eeea53 | 358 | { |
d1c54acd MK |
359 | return kmap_atomic(p->page); |
360 | } | |
73eeea53 | 361 | |
d1c54acd MK |
362 | /* We use the flushing unmap only with ppgtt structures: |
363 | * page directories, page tables and scratch pages. | |
364 | */ | |
365 | static void kunmap_page_dma(struct drm_device *dev, void *vaddr) | |
366 | { | |
73eeea53 MK |
367 | /* There are only few exceptions for gen >=6. chv and bxt. |
368 | * And we are not sure about the latter so play safe for now. | |
369 | */ | |
370 | if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev)) | |
371 | drm_clflush_virt_range(vaddr, PAGE_SIZE); | |
372 | ||
373 | kunmap_atomic(vaddr); | |
374 | } | |
375 | ||
567047be | 376 | #define kmap_px(px) kmap_page_dma(px_base(px)) |
d1c54acd MK |
377 | #define kunmap_px(ppgtt, vaddr) kunmap_page_dma((ppgtt)->base.dev, (vaddr)) |
378 | ||
567047be MK |
379 | #define setup_px(dev, px) setup_page_dma((dev), px_base(px)) |
380 | #define cleanup_px(dev, px) cleanup_page_dma((dev), px_base(px)) | |
381 | #define fill_px(dev, px, v) fill_page_dma((dev), px_base(px), (v)) | |
382 | #define fill32_px(dev, px, v) fill_page_dma_32((dev), px_base(px), (v)) | |
383 | ||
d1c54acd MK |
384 | static void fill_page_dma(struct drm_device *dev, struct i915_page_dma *p, |
385 | const uint64_t val) | |
386 | { | |
387 | int i; | |
388 | uint64_t * const vaddr = kmap_page_dma(p); | |
389 | ||
390 | for (i = 0; i < 512; i++) | |
391 | vaddr[i] = val; | |
392 | ||
393 | kunmap_page_dma(dev, vaddr); | |
394 | } | |
395 | ||
73eeea53 MK |
396 | static void fill_page_dma_32(struct drm_device *dev, struct i915_page_dma *p, |
397 | const uint32_t val32) | |
398 | { | |
399 | uint64_t v = val32; | |
400 | ||
401 | v = v << 32 | val32; | |
402 | ||
403 | fill_page_dma(dev, p, v); | |
404 | } | |
405 | ||
4ad2af1e MK |
406 | static struct i915_page_scratch *alloc_scratch_page(struct drm_device *dev) |
407 | { | |
408 | struct i915_page_scratch *sp; | |
409 | int ret; | |
410 | ||
411 | sp = kzalloc(sizeof(*sp), GFP_KERNEL); | |
412 | if (sp == NULL) | |
413 | return ERR_PTR(-ENOMEM); | |
414 | ||
415 | ret = __setup_page_dma(dev, px_base(sp), GFP_DMA32 | __GFP_ZERO); | |
416 | if (ret) { | |
417 | kfree(sp); | |
418 | return ERR_PTR(ret); | |
419 | } | |
420 | ||
421 | set_pages_uc(px_page(sp), 1); | |
422 | ||
423 | return sp; | |
424 | } | |
425 | ||
426 | static void free_scratch_page(struct drm_device *dev, | |
427 | struct i915_page_scratch *sp) | |
428 | { | |
429 | set_pages_wb(px_page(sp), 1); | |
430 | ||
431 | cleanup_px(dev, sp); | |
432 | kfree(sp); | |
433 | } | |
434 | ||
8a1ebd74 | 435 | static struct i915_page_table *alloc_pt(struct drm_device *dev) |
06fda602 | 436 | { |
ec565b3c | 437 | struct i915_page_table *pt; |
678d96fb BW |
438 | const size_t count = INTEL_INFO(dev)->gen >= 8 ? |
439 | GEN8_PTES : GEN6_PTES; | |
440 | int ret = -ENOMEM; | |
06fda602 BW |
441 | |
442 | pt = kzalloc(sizeof(*pt), GFP_KERNEL); | |
443 | if (!pt) | |
444 | return ERR_PTR(-ENOMEM); | |
445 | ||
678d96fb BW |
446 | pt->used_ptes = kcalloc(BITS_TO_LONGS(count), sizeof(*pt->used_ptes), |
447 | GFP_KERNEL); | |
448 | ||
449 | if (!pt->used_ptes) | |
450 | goto fail_bitmap; | |
451 | ||
567047be | 452 | ret = setup_px(dev, pt); |
678d96fb | 453 | if (ret) |
44159ddb | 454 | goto fail_page_m; |
06fda602 BW |
455 | |
456 | return pt; | |
678d96fb | 457 | |
44159ddb | 458 | fail_page_m: |
678d96fb BW |
459 | kfree(pt->used_ptes); |
460 | fail_bitmap: | |
461 | kfree(pt); | |
462 | ||
463 | return ERR_PTR(ret); | |
06fda602 BW |
464 | } |
465 | ||
2e906bea | 466 | static void free_pt(struct drm_device *dev, struct i915_page_table *pt) |
06fda602 | 467 | { |
2e906bea MK |
468 | cleanup_px(dev, pt); |
469 | kfree(pt->used_ptes); | |
470 | kfree(pt); | |
471 | } | |
472 | ||
473 | static void gen8_initialize_pt(struct i915_address_space *vm, | |
474 | struct i915_page_table *pt) | |
475 | { | |
476 | gen8_pte_t scratch_pte; | |
477 | ||
478 | scratch_pte = gen8_pte_encode(px_dma(vm->scratch_page), | |
479 | I915_CACHE_LLC, true); | |
480 | ||
481 | fill_px(vm->dev, pt, scratch_pte); | |
482 | } | |
483 | ||
484 | static void gen6_initialize_pt(struct i915_address_space *vm, | |
485 | struct i915_page_table *pt) | |
486 | { | |
487 | gen6_pte_t scratch_pte; | |
488 | ||
489 | WARN_ON(px_dma(vm->scratch_page) == 0); | |
490 | ||
491 | scratch_pte = vm->pte_encode(px_dma(vm->scratch_page), | |
492 | I915_CACHE_LLC, true, 0); | |
493 | ||
494 | fill32_px(vm->dev, pt, scratch_pte); | |
06fda602 BW |
495 | } |
496 | ||
8a1ebd74 | 497 | static struct i915_page_directory *alloc_pd(struct drm_device *dev) |
06fda602 | 498 | { |
ec565b3c | 499 | struct i915_page_directory *pd; |
33c8819f | 500 | int ret = -ENOMEM; |
06fda602 BW |
501 | |
502 | pd = kzalloc(sizeof(*pd), GFP_KERNEL); | |
503 | if (!pd) | |
504 | return ERR_PTR(-ENOMEM); | |
505 | ||
33c8819f MT |
506 | pd->used_pdes = kcalloc(BITS_TO_LONGS(I915_PDES), |
507 | sizeof(*pd->used_pdes), GFP_KERNEL); | |
508 | if (!pd->used_pdes) | |
a08e111a | 509 | goto fail_bitmap; |
33c8819f | 510 | |
567047be | 511 | ret = setup_px(dev, pd); |
33c8819f | 512 | if (ret) |
a08e111a | 513 | goto fail_page_m; |
e5815a2e | 514 | |
06fda602 | 515 | return pd; |
33c8819f | 516 | |
a08e111a | 517 | fail_page_m: |
33c8819f | 518 | kfree(pd->used_pdes); |
a08e111a | 519 | fail_bitmap: |
33c8819f MT |
520 | kfree(pd); |
521 | ||
522 | return ERR_PTR(ret); | |
06fda602 BW |
523 | } |
524 | ||
2e906bea MK |
525 | static void free_pd(struct drm_device *dev, struct i915_page_directory *pd) |
526 | { | |
527 | if (px_page(pd)) { | |
528 | cleanup_px(dev, pd); | |
529 | kfree(pd->used_pdes); | |
530 | kfree(pd); | |
531 | } | |
532 | } | |
533 | ||
534 | static void gen8_initialize_pd(struct i915_address_space *vm, | |
535 | struct i915_page_directory *pd) | |
536 | { | |
537 | gen8_pde_t scratch_pde; | |
538 | ||
539 | scratch_pde = gen8_pde_encode(px_dma(vm->scratch_pt), I915_CACHE_LLC); | |
540 | ||
541 | fill_px(vm->dev, pd, scratch_pde); | |
542 | } | |
543 | ||
6ac18502 MT |
544 | static int __pdp_init(struct drm_device *dev, |
545 | struct i915_page_directory_pointer *pdp) | |
546 | { | |
547 | size_t pdpes = I915_PDPES_PER_PDP(dev); | |
548 | ||
549 | pdp->used_pdpes = kcalloc(BITS_TO_LONGS(pdpes), | |
550 | sizeof(unsigned long), | |
551 | GFP_KERNEL); | |
552 | if (!pdp->used_pdpes) | |
553 | return -ENOMEM; | |
554 | ||
555 | pdp->page_directory = kcalloc(pdpes, sizeof(*pdp->page_directory), | |
556 | GFP_KERNEL); | |
557 | if (!pdp->page_directory) { | |
558 | kfree(pdp->used_pdpes); | |
559 | /* the PDP might be the statically allocated top level. Keep it | |
560 | * as clean as possible */ | |
561 | pdp->used_pdpes = NULL; | |
562 | return -ENOMEM; | |
563 | } | |
564 | ||
565 | return 0; | |
566 | } | |
567 | ||
568 | static void __pdp_fini(struct i915_page_directory_pointer *pdp) | |
569 | { | |
570 | kfree(pdp->used_pdpes); | |
571 | kfree(pdp->page_directory); | |
572 | pdp->page_directory = NULL; | |
573 | } | |
574 | ||
762d9936 MT |
575 | static struct |
576 | i915_page_directory_pointer *alloc_pdp(struct drm_device *dev) | |
577 | { | |
578 | struct i915_page_directory_pointer *pdp; | |
579 | int ret = -ENOMEM; | |
580 | ||
581 | WARN_ON(!USES_FULL_48BIT_PPGTT(dev)); | |
582 | ||
583 | pdp = kzalloc(sizeof(*pdp), GFP_KERNEL); | |
584 | if (!pdp) | |
585 | return ERR_PTR(-ENOMEM); | |
586 | ||
587 | ret = __pdp_init(dev, pdp); | |
588 | if (ret) | |
589 | goto fail_bitmap; | |
590 | ||
591 | ret = setup_px(dev, pdp); | |
592 | if (ret) | |
593 | goto fail_page_m; | |
594 | ||
595 | return pdp; | |
596 | ||
597 | fail_page_m: | |
598 | __pdp_fini(pdp); | |
599 | fail_bitmap: | |
600 | kfree(pdp); | |
601 | ||
602 | return ERR_PTR(ret); | |
603 | } | |
604 | ||
6ac18502 MT |
605 | static void free_pdp(struct drm_device *dev, |
606 | struct i915_page_directory_pointer *pdp) | |
607 | { | |
608 | __pdp_fini(pdp); | |
762d9936 MT |
609 | if (USES_FULL_48BIT_PPGTT(dev)) { |
610 | cleanup_px(dev, pdp); | |
611 | kfree(pdp); | |
612 | } | |
613 | } | |
614 | ||
69ab76fd MT |
615 | static void gen8_initialize_pdp(struct i915_address_space *vm, |
616 | struct i915_page_directory_pointer *pdp) | |
617 | { | |
618 | gen8_ppgtt_pdpe_t scratch_pdpe; | |
619 | ||
620 | scratch_pdpe = gen8_pdpe_encode(px_dma(vm->scratch_pd), I915_CACHE_LLC); | |
621 | ||
622 | fill_px(vm->dev, pdp, scratch_pdpe); | |
623 | } | |
624 | ||
625 | static void gen8_initialize_pml4(struct i915_address_space *vm, | |
626 | struct i915_pml4 *pml4) | |
627 | { | |
628 | gen8_ppgtt_pml4e_t scratch_pml4e; | |
629 | ||
630 | scratch_pml4e = gen8_pml4e_encode(px_dma(vm->scratch_pdp), | |
631 | I915_CACHE_LLC); | |
632 | ||
633 | fill_px(vm->dev, pml4, scratch_pml4e); | |
634 | } | |
635 | ||
762d9936 MT |
636 | static void |
637 | gen8_setup_page_directory(struct i915_hw_ppgtt *ppgtt, | |
638 | struct i915_page_directory_pointer *pdp, | |
639 | struct i915_page_directory *pd, | |
640 | int index) | |
641 | { | |
642 | gen8_ppgtt_pdpe_t *page_directorypo; | |
643 | ||
644 | if (!USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) | |
645 | return; | |
646 | ||
647 | page_directorypo = kmap_px(pdp); | |
648 | page_directorypo[index] = gen8_pdpe_encode(px_dma(pd), I915_CACHE_LLC); | |
649 | kunmap_px(ppgtt, page_directorypo); | |
650 | } | |
651 | ||
652 | static void | |
653 | gen8_setup_page_directory_pointer(struct i915_hw_ppgtt *ppgtt, | |
654 | struct i915_pml4 *pml4, | |
655 | struct i915_page_directory_pointer *pdp, | |
656 | int index) | |
657 | { | |
658 | gen8_ppgtt_pml4e_t *pagemap = kmap_px(pml4); | |
659 | ||
660 | WARN_ON(!USES_FULL_48BIT_PPGTT(ppgtt->base.dev)); | |
661 | pagemap[index] = gen8_pml4e_encode(px_dma(pdp), I915_CACHE_LLC); | |
662 | kunmap_px(ppgtt, pagemap); | |
6ac18502 MT |
663 | } |
664 | ||
94e409c1 | 665 | /* Broadwell Page Directory Pointer Descriptors */ |
e85b26dc | 666 | static int gen8_write_pdp(struct drm_i915_gem_request *req, |
7cb6d7ac MT |
667 | unsigned entry, |
668 | dma_addr_t addr) | |
94e409c1 | 669 | { |
4a570db5 | 670 | struct intel_engine_cs *engine = req->engine; |
94e409c1 BW |
671 | int ret; |
672 | ||
673 | BUG_ON(entry >= 4); | |
674 | ||
5fb9de1a | 675 | ret = intel_ring_begin(req, 6); |
94e409c1 BW |
676 | if (ret) |
677 | return ret; | |
678 | ||
e2f80391 TU |
679 | intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(1)); |
680 | intel_ring_emit_reg(engine, GEN8_RING_PDP_UDW(engine, entry)); | |
681 | intel_ring_emit(engine, upper_32_bits(addr)); | |
682 | intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(1)); | |
683 | intel_ring_emit_reg(engine, GEN8_RING_PDP_LDW(engine, entry)); | |
684 | intel_ring_emit(engine, lower_32_bits(addr)); | |
685 | intel_ring_advance(engine); | |
94e409c1 BW |
686 | |
687 | return 0; | |
688 | } | |
689 | ||
2dba3239 MT |
690 | static int gen8_legacy_mm_switch(struct i915_hw_ppgtt *ppgtt, |
691 | struct drm_i915_gem_request *req) | |
94e409c1 | 692 | { |
eeb9488e | 693 | int i, ret; |
94e409c1 | 694 | |
7cb6d7ac | 695 | for (i = GEN8_LEGACY_PDPES - 1; i >= 0; i--) { |
d852c7bf MK |
696 | const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i); |
697 | ||
e85b26dc | 698 | ret = gen8_write_pdp(req, i, pd_daddr); |
eeb9488e BW |
699 | if (ret) |
700 | return ret; | |
94e409c1 | 701 | } |
d595bd4b | 702 | |
eeb9488e | 703 | return 0; |
94e409c1 BW |
704 | } |
705 | ||
2dba3239 MT |
706 | static int gen8_48b_mm_switch(struct i915_hw_ppgtt *ppgtt, |
707 | struct drm_i915_gem_request *req) | |
708 | { | |
709 | return gen8_write_pdp(req, 0, px_dma(&ppgtt->pml4)); | |
710 | } | |
711 | ||
f9b5b782 MT |
712 | static void gen8_ppgtt_clear_pte_range(struct i915_address_space *vm, |
713 | struct i915_page_directory_pointer *pdp, | |
714 | uint64_t start, | |
715 | uint64_t length, | |
716 | gen8_pte_t scratch_pte) | |
459108b8 | 717 | { |
e5716f55 | 718 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
f9b5b782 | 719 | gen8_pte_t *pt_vaddr; |
de5ba8eb MT |
720 | unsigned pdpe = gen8_pdpe_index(start); |
721 | unsigned pde = gen8_pde_index(start); | |
722 | unsigned pte = gen8_pte_index(start); | |
782f1495 | 723 | unsigned num_entries = length >> PAGE_SHIFT; |
459108b8 BW |
724 | unsigned last_pte, i; |
725 | ||
f9b5b782 MT |
726 | if (WARN_ON(!pdp)) |
727 | return; | |
459108b8 BW |
728 | |
729 | while (num_entries) { | |
ec565b3c MT |
730 | struct i915_page_directory *pd; |
731 | struct i915_page_table *pt; | |
06fda602 | 732 | |
d4ec9da0 | 733 | if (WARN_ON(!pdp->page_directory[pdpe])) |
00245266 | 734 | break; |
06fda602 | 735 | |
d4ec9da0 | 736 | pd = pdp->page_directory[pdpe]; |
06fda602 BW |
737 | |
738 | if (WARN_ON(!pd->page_table[pde])) | |
00245266 | 739 | break; |
06fda602 BW |
740 | |
741 | pt = pd->page_table[pde]; | |
742 | ||
567047be | 743 | if (WARN_ON(!px_page(pt))) |
00245266 | 744 | break; |
06fda602 | 745 | |
7ad47cf2 | 746 | last_pte = pte + num_entries; |
07749ef3 MT |
747 | if (last_pte > GEN8_PTES) |
748 | last_pte = GEN8_PTES; | |
459108b8 | 749 | |
d1c54acd | 750 | pt_vaddr = kmap_px(pt); |
459108b8 | 751 | |
7ad47cf2 | 752 | for (i = pte; i < last_pte; i++) { |
459108b8 | 753 | pt_vaddr[i] = scratch_pte; |
7ad47cf2 BW |
754 | num_entries--; |
755 | } | |
459108b8 | 756 | |
44a71024 | 757 | kunmap_px(ppgtt, pt_vaddr); |
459108b8 | 758 | |
7ad47cf2 | 759 | pte = 0; |
07749ef3 | 760 | if (++pde == I915_PDES) { |
de5ba8eb MT |
761 | if (++pdpe == I915_PDPES_PER_PDP(vm->dev)) |
762 | break; | |
7ad47cf2 BW |
763 | pde = 0; |
764 | } | |
459108b8 BW |
765 | } |
766 | } | |
767 | ||
f9b5b782 MT |
768 | static void gen8_ppgtt_clear_range(struct i915_address_space *vm, |
769 | uint64_t start, | |
770 | uint64_t length, | |
771 | bool use_scratch) | |
9df15b49 | 772 | { |
e5716f55 | 773 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
f9b5b782 MT |
774 | gen8_pte_t scratch_pte = gen8_pte_encode(px_dma(vm->scratch_page), |
775 | I915_CACHE_LLC, use_scratch); | |
776 | ||
de5ba8eb MT |
777 | if (!USES_FULL_48BIT_PPGTT(vm->dev)) { |
778 | gen8_ppgtt_clear_pte_range(vm, &ppgtt->pdp, start, length, | |
779 | scratch_pte); | |
780 | } else { | |
e8ebd8e2 | 781 | uint64_t pml4e; |
de5ba8eb MT |
782 | struct i915_page_directory_pointer *pdp; |
783 | ||
e8ebd8e2 | 784 | gen8_for_each_pml4e(pdp, &ppgtt->pml4, start, length, pml4e) { |
de5ba8eb MT |
785 | gen8_ppgtt_clear_pte_range(vm, pdp, start, length, |
786 | scratch_pte); | |
787 | } | |
788 | } | |
f9b5b782 MT |
789 | } |
790 | ||
791 | static void | |
792 | gen8_ppgtt_insert_pte_entries(struct i915_address_space *vm, | |
793 | struct i915_page_directory_pointer *pdp, | |
3387d433 | 794 | struct sg_page_iter *sg_iter, |
f9b5b782 MT |
795 | uint64_t start, |
796 | enum i915_cache_level cache_level) | |
797 | { | |
e5716f55 | 798 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
07749ef3 | 799 | gen8_pte_t *pt_vaddr; |
de5ba8eb MT |
800 | unsigned pdpe = gen8_pdpe_index(start); |
801 | unsigned pde = gen8_pde_index(start); | |
802 | unsigned pte = gen8_pte_index(start); | |
9df15b49 | 803 | |
6f1cc993 | 804 | pt_vaddr = NULL; |
7ad47cf2 | 805 | |
3387d433 | 806 | while (__sg_page_iter_next(sg_iter)) { |
d7b3de91 | 807 | if (pt_vaddr == NULL) { |
d4ec9da0 | 808 | struct i915_page_directory *pd = pdp->page_directory[pdpe]; |
ec565b3c | 809 | struct i915_page_table *pt = pd->page_table[pde]; |
d1c54acd | 810 | pt_vaddr = kmap_px(pt); |
d7b3de91 | 811 | } |
9df15b49 | 812 | |
7ad47cf2 | 813 | pt_vaddr[pte] = |
3387d433 | 814 | gen8_pte_encode(sg_page_iter_dma_address(sg_iter), |
6f1cc993 | 815 | cache_level, true); |
07749ef3 | 816 | if (++pte == GEN8_PTES) { |
d1c54acd | 817 | kunmap_px(ppgtt, pt_vaddr); |
6f1cc993 | 818 | pt_vaddr = NULL; |
07749ef3 | 819 | if (++pde == I915_PDES) { |
de5ba8eb MT |
820 | if (++pdpe == I915_PDPES_PER_PDP(vm->dev)) |
821 | break; | |
7ad47cf2 BW |
822 | pde = 0; |
823 | } | |
824 | pte = 0; | |
9df15b49 BW |
825 | } |
826 | } | |
d1c54acd MK |
827 | |
828 | if (pt_vaddr) | |
829 | kunmap_px(ppgtt, pt_vaddr); | |
9df15b49 BW |
830 | } |
831 | ||
f9b5b782 MT |
832 | static void gen8_ppgtt_insert_entries(struct i915_address_space *vm, |
833 | struct sg_table *pages, | |
834 | uint64_t start, | |
835 | enum i915_cache_level cache_level, | |
836 | u32 unused) | |
837 | { | |
e5716f55 | 838 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
3387d433 | 839 | struct sg_page_iter sg_iter; |
f9b5b782 | 840 | |
3387d433 | 841 | __sg_page_iter_start(&sg_iter, pages->sgl, sg_nents(pages->sgl), 0); |
de5ba8eb MT |
842 | |
843 | if (!USES_FULL_48BIT_PPGTT(vm->dev)) { | |
844 | gen8_ppgtt_insert_pte_entries(vm, &ppgtt->pdp, &sg_iter, start, | |
845 | cache_level); | |
846 | } else { | |
847 | struct i915_page_directory_pointer *pdp; | |
e8ebd8e2 | 848 | uint64_t pml4e; |
de5ba8eb MT |
849 | uint64_t length = (uint64_t)pages->orig_nents << PAGE_SHIFT; |
850 | ||
e8ebd8e2 | 851 | gen8_for_each_pml4e(pdp, &ppgtt->pml4, start, length, pml4e) { |
de5ba8eb MT |
852 | gen8_ppgtt_insert_pte_entries(vm, pdp, &sg_iter, |
853 | start, cache_level); | |
854 | } | |
855 | } | |
f9b5b782 MT |
856 | } |
857 | ||
f37c0505 MT |
858 | static void gen8_free_page_tables(struct drm_device *dev, |
859 | struct i915_page_directory *pd) | |
7ad47cf2 BW |
860 | { |
861 | int i; | |
862 | ||
567047be | 863 | if (!px_page(pd)) |
7ad47cf2 BW |
864 | return; |
865 | ||
33c8819f | 866 | for_each_set_bit(i, pd->used_pdes, I915_PDES) { |
06fda602 BW |
867 | if (WARN_ON(!pd->page_table[i])) |
868 | continue; | |
7ad47cf2 | 869 | |
a08e111a | 870 | free_pt(dev, pd->page_table[i]); |
06fda602 BW |
871 | pd->page_table[i] = NULL; |
872 | } | |
d7b3de91 BW |
873 | } |
874 | ||
8776f02b MK |
875 | static int gen8_init_scratch(struct i915_address_space *vm) |
876 | { | |
877 | struct drm_device *dev = vm->dev; | |
64c050db | 878 | int ret; |
8776f02b MK |
879 | |
880 | vm->scratch_page = alloc_scratch_page(dev); | |
881 | if (IS_ERR(vm->scratch_page)) | |
882 | return PTR_ERR(vm->scratch_page); | |
883 | ||
884 | vm->scratch_pt = alloc_pt(dev); | |
885 | if (IS_ERR(vm->scratch_pt)) { | |
64c050db MA |
886 | ret = PTR_ERR(vm->scratch_pt); |
887 | goto free_scratch_page; | |
8776f02b MK |
888 | } |
889 | ||
890 | vm->scratch_pd = alloc_pd(dev); | |
891 | if (IS_ERR(vm->scratch_pd)) { | |
64c050db MA |
892 | ret = PTR_ERR(vm->scratch_pd); |
893 | goto free_pt; | |
8776f02b MK |
894 | } |
895 | ||
69ab76fd MT |
896 | if (USES_FULL_48BIT_PPGTT(dev)) { |
897 | vm->scratch_pdp = alloc_pdp(dev); | |
898 | if (IS_ERR(vm->scratch_pdp)) { | |
64c050db MA |
899 | ret = PTR_ERR(vm->scratch_pdp); |
900 | goto free_pd; | |
69ab76fd MT |
901 | } |
902 | } | |
903 | ||
8776f02b MK |
904 | gen8_initialize_pt(vm, vm->scratch_pt); |
905 | gen8_initialize_pd(vm, vm->scratch_pd); | |
69ab76fd MT |
906 | if (USES_FULL_48BIT_PPGTT(dev)) |
907 | gen8_initialize_pdp(vm, vm->scratch_pdp); | |
8776f02b MK |
908 | |
909 | return 0; | |
64c050db MA |
910 | |
911 | free_pd: | |
912 | free_pd(dev, vm->scratch_pd); | |
913 | free_pt: | |
914 | free_pt(dev, vm->scratch_pt); | |
915 | free_scratch_page: | |
916 | free_scratch_page(dev, vm->scratch_page); | |
917 | ||
918 | return ret; | |
8776f02b MK |
919 | } |
920 | ||
650da34c ZL |
921 | static int gen8_ppgtt_notify_vgt(struct i915_hw_ppgtt *ppgtt, bool create) |
922 | { | |
923 | enum vgt_g2v_type msg; | |
df28564d | 924 | struct drm_i915_private *dev_priv = to_i915(ppgtt->base.dev); |
650da34c ZL |
925 | int i; |
926 | ||
df28564d | 927 | if (USES_FULL_48BIT_PPGTT(dev_priv)) { |
650da34c ZL |
928 | u64 daddr = px_dma(&ppgtt->pml4); |
929 | ||
ab75bb5d VS |
930 | I915_WRITE(vgtif_reg(pdp[0].lo), lower_32_bits(daddr)); |
931 | I915_WRITE(vgtif_reg(pdp[0].hi), upper_32_bits(daddr)); | |
650da34c ZL |
932 | |
933 | msg = (create ? VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE : | |
934 | VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY); | |
935 | } else { | |
936 | for (i = 0; i < GEN8_LEGACY_PDPES; i++) { | |
937 | u64 daddr = i915_page_dir_dma_addr(ppgtt, i); | |
938 | ||
ab75bb5d VS |
939 | I915_WRITE(vgtif_reg(pdp[i].lo), lower_32_bits(daddr)); |
940 | I915_WRITE(vgtif_reg(pdp[i].hi), upper_32_bits(daddr)); | |
650da34c ZL |
941 | } |
942 | ||
943 | msg = (create ? VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE : | |
944 | VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY); | |
945 | } | |
946 | ||
947 | I915_WRITE(vgtif_reg(g2v_notify), msg); | |
948 | ||
949 | return 0; | |
950 | } | |
951 | ||
8776f02b MK |
952 | static void gen8_free_scratch(struct i915_address_space *vm) |
953 | { | |
954 | struct drm_device *dev = vm->dev; | |
955 | ||
69ab76fd MT |
956 | if (USES_FULL_48BIT_PPGTT(dev)) |
957 | free_pdp(dev, vm->scratch_pdp); | |
8776f02b MK |
958 | free_pd(dev, vm->scratch_pd); |
959 | free_pt(dev, vm->scratch_pt); | |
960 | free_scratch_page(dev, vm->scratch_page); | |
961 | } | |
962 | ||
762d9936 MT |
963 | static void gen8_ppgtt_cleanup_3lvl(struct drm_device *dev, |
964 | struct i915_page_directory_pointer *pdp) | |
b45a6715 BW |
965 | { |
966 | int i; | |
967 | ||
d4ec9da0 MT |
968 | for_each_set_bit(i, pdp->used_pdpes, I915_PDPES_PER_PDP(dev)) { |
969 | if (WARN_ON(!pdp->page_directory[i])) | |
06fda602 BW |
970 | continue; |
971 | ||
d4ec9da0 MT |
972 | gen8_free_page_tables(dev, pdp->page_directory[i]); |
973 | free_pd(dev, pdp->page_directory[i]); | |
7ad47cf2 | 974 | } |
69876bed | 975 | |
d4ec9da0 | 976 | free_pdp(dev, pdp); |
762d9936 MT |
977 | } |
978 | ||
979 | static void gen8_ppgtt_cleanup_4lvl(struct i915_hw_ppgtt *ppgtt) | |
980 | { | |
981 | int i; | |
982 | ||
983 | for_each_set_bit(i, ppgtt->pml4.used_pml4es, GEN8_PML4ES_PER_PML4) { | |
984 | if (WARN_ON(!ppgtt->pml4.pdps[i])) | |
985 | continue; | |
986 | ||
987 | gen8_ppgtt_cleanup_3lvl(ppgtt->base.dev, ppgtt->pml4.pdps[i]); | |
988 | } | |
989 | ||
990 | cleanup_px(ppgtt->base.dev, &ppgtt->pml4); | |
991 | } | |
992 | ||
993 | static void gen8_ppgtt_cleanup(struct i915_address_space *vm) | |
994 | { | |
e5716f55 | 995 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
762d9936 | 996 | |
650da34c ZL |
997 | if (intel_vgpu_active(vm->dev)) |
998 | gen8_ppgtt_notify_vgt(ppgtt, false); | |
999 | ||
762d9936 MT |
1000 | if (!USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) |
1001 | gen8_ppgtt_cleanup_3lvl(ppgtt->base.dev, &ppgtt->pdp); | |
1002 | else | |
1003 | gen8_ppgtt_cleanup_4lvl(ppgtt); | |
d4ec9da0 | 1004 | |
8776f02b | 1005 | gen8_free_scratch(vm); |
b45a6715 BW |
1006 | } |
1007 | ||
d7b2633d MT |
1008 | /** |
1009 | * gen8_ppgtt_alloc_pagetabs() - Allocate page tables for VA range. | |
d4ec9da0 MT |
1010 | * @vm: Master vm structure. |
1011 | * @pd: Page directory for this address range. | |
d7b2633d | 1012 | * @start: Starting virtual address to begin allocations. |
d4ec9da0 | 1013 | * @length: Size of the allocations. |
d7b2633d MT |
1014 | * @new_pts: Bitmap set by function with new allocations. Likely used by the |
1015 | * caller to free on error. | |
1016 | * | |
1017 | * Allocate the required number of page tables. Extremely similar to | |
1018 | * gen8_ppgtt_alloc_page_directories(). The main difference is here we are limited by | |
1019 | * the page directory boundary (instead of the page directory pointer). That | |
1020 | * boundary is 1GB virtual. Therefore, unlike gen8_ppgtt_alloc_page_directories(), it is | |
1021 | * possible, and likely that the caller will need to use multiple calls of this | |
1022 | * function to achieve the appropriate allocation. | |
1023 | * | |
1024 | * Return: 0 if success; negative error code otherwise. | |
1025 | */ | |
d4ec9da0 | 1026 | static int gen8_ppgtt_alloc_pagetabs(struct i915_address_space *vm, |
e5815a2e | 1027 | struct i915_page_directory *pd, |
5441f0cb | 1028 | uint64_t start, |
d7b2633d MT |
1029 | uint64_t length, |
1030 | unsigned long *new_pts) | |
bf2b4ed2 | 1031 | { |
d4ec9da0 | 1032 | struct drm_device *dev = vm->dev; |
d7b2633d | 1033 | struct i915_page_table *pt; |
5441f0cb | 1034 | uint32_t pde; |
bf2b4ed2 | 1035 | |
e8ebd8e2 | 1036 | gen8_for_each_pde(pt, pd, start, length, pde) { |
d7b2633d | 1037 | /* Don't reallocate page tables */ |
6ac18502 | 1038 | if (test_bit(pde, pd->used_pdes)) { |
d7b2633d | 1039 | /* Scratch is never allocated this way */ |
d4ec9da0 | 1040 | WARN_ON(pt == vm->scratch_pt); |
d7b2633d MT |
1041 | continue; |
1042 | } | |
1043 | ||
8a1ebd74 | 1044 | pt = alloc_pt(dev); |
d7b2633d | 1045 | if (IS_ERR(pt)) |
5441f0cb MT |
1046 | goto unwind_out; |
1047 | ||
d4ec9da0 | 1048 | gen8_initialize_pt(vm, pt); |
d7b2633d | 1049 | pd->page_table[pde] = pt; |
966082c9 | 1050 | __set_bit(pde, new_pts); |
4c06ec8d | 1051 | trace_i915_page_table_entry_alloc(vm, pde, start, GEN8_PDE_SHIFT); |
7ad47cf2 BW |
1052 | } |
1053 | ||
bf2b4ed2 | 1054 | return 0; |
7ad47cf2 BW |
1055 | |
1056 | unwind_out: | |
d7b2633d | 1057 | for_each_set_bit(pde, new_pts, I915_PDES) |
a08e111a | 1058 | free_pt(dev, pd->page_table[pde]); |
7ad47cf2 | 1059 | |
d7b3de91 | 1060 | return -ENOMEM; |
bf2b4ed2 BW |
1061 | } |
1062 | ||
d7b2633d MT |
1063 | /** |
1064 | * gen8_ppgtt_alloc_page_directories() - Allocate page directories for VA range. | |
d4ec9da0 | 1065 | * @vm: Master vm structure. |
d7b2633d MT |
1066 | * @pdp: Page directory pointer for this address range. |
1067 | * @start: Starting virtual address to begin allocations. | |
d4ec9da0 MT |
1068 | * @length: Size of the allocations. |
1069 | * @new_pds: Bitmap set by function with new allocations. Likely used by the | |
d7b2633d MT |
1070 | * caller to free on error. |
1071 | * | |
1072 | * Allocate the required number of page directories starting at the pde index of | |
1073 | * @start, and ending at the pde index @start + @length. This function will skip | |
1074 | * over already allocated page directories within the range, and only allocate | |
1075 | * new ones, setting the appropriate pointer within the pdp as well as the | |
1076 | * correct position in the bitmap @new_pds. | |
1077 | * | |
1078 | * The function will only allocate the pages within the range for a give page | |
1079 | * directory pointer. In other words, if @start + @length straddles a virtually | |
1080 | * addressed PDP boundary (512GB for 4k pages), there will be more allocations | |
1081 | * required by the caller, This is not currently possible, and the BUG in the | |
1082 | * code will prevent it. | |
1083 | * | |
1084 | * Return: 0 if success; negative error code otherwise. | |
1085 | */ | |
d4ec9da0 MT |
1086 | static int |
1087 | gen8_ppgtt_alloc_page_directories(struct i915_address_space *vm, | |
1088 | struct i915_page_directory_pointer *pdp, | |
1089 | uint64_t start, | |
1090 | uint64_t length, | |
1091 | unsigned long *new_pds) | |
bf2b4ed2 | 1092 | { |
d4ec9da0 | 1093 | struct drm_device *dev = vm->dev; |
d7b2633d | 1094 | struct i915_page_directory *pd; |
69876bed | 1095 | uint32_t pdpe; |
6ac18502 | 1096 | uint32_t pdpes = I915_PDPES_PER_PDP(dev); |
69876bed | 1097 | |
6ac18502 | 1098 | WARN_ON(!bitmap_empty(new_pds, pdpes)); |
d7b2633d | 1099 | |
e8ebd8e2 | 1100 | gen8_for_each_pdpe(pd, pdp, start, length, pdpe) { |
6ac18502 | 1101 | if (test_bit(pdpe, pdp->used_pdpes)) |
d7b2633d | 1102 | continue; |
33c8819f | 1103 | |
8a1ebd74 | 1104 | pd = alloc_pd(dev); |
d7b2633d | 1105 | if (IS_ERR(pd)) |
d7b3de91 | 1106 | goto unwind_out; |
69876bed | 1107 | |
d4ec9da0 | 1108 | gen8_initialize_pd(vm, pd); |
d7b2633d | 1109 | pdp->page_directory[pdpe] = pd; |
966082c9 | 1110 | __set_bit(pdpe, new_pds); |
4c06ec8d | 1111 | trace_i915_page_directory_entry_alloc(vm, pdpe, start, GEN8_PDPE_SHIFT); |
d7b3de91 BW |
1112 | } |
1113 | ||
bf2b4ed2 | 1114 | return 0; |
d7b3de91 BW |
1115 | |
1116 | unwind_out: | |
6ac18502 | 1117 | for_each_set_bit(pdpe, new_pds, pdpes) |
a08e111a | 1118 | free_pd(dev, pdp->page_directory[pdpe]); |
d7b3de91 BW |
1119 | |
1120 | return -ENOMEM; | |
bf2b4ed2 BW |
1121 | } |
1122 | ||
762d9936 MT |
1123 | /** |
1124 | * gen8_ppgtt_alloc_page_dirpointers() - Allocate pdps for VA range. | |
1125 | * @vm: Master vm structure. | |
1126 | * @pml4: Page map level 4 for this address range. | |
1127 | * @start: Starting virtual address to begin allocations. | |
1128 | * @length: Size of the allocations. | |
1129 | * @new_pdps: Bitmap set by function with new allocations. Likely used by the | |
1130 | * caller to free on error. | |
1131 | * | |
1132 | * Allocate the required number of page directory pointers. Extremely similar to | |
1133 | * gen8_ppgtt_alloc_page_directories() and gen8_ppgtt_alloc_pagetabs(). | |
1134 | * The main difference is here we are limited by the pml4 boundary (instead of | |
1135 | * the page directory pointer). | |
1136 | * | |
1137 | * Return: 0 if success; negative error code otherwise. | |
1138 | */ | |
1139 | static int | |
1140 | gen8_ppgtt_alloc_page_dirpointers(struct i915_address_space *vm, | |
1141 | struct i915_pml4 *pml4, | |
1142 | uint64_t start, | |
1143 | uint64_t length, | |
1144 | unsigned long *new_pdps) | |
1145 | { | |
1146 | struct drm_device *dev = vm->dev; | |
1147 | struct i915_page_directory_pointer *pdp; | |
762d9936 MT |
1148 | uint32_t pml4e; |
1149 | ||
1150 | WARN_ON(!bitmap_empty(new_pdps, GEN8_PML4ES_PER_PML4)); | |
1151 | ||
e8ebd8e2 | 1152 | gen8_for_each_pml4e(pdp, pml4, start, length, pml4e) { |
762d9936 MT |
1153 | if (!test_bit(pml4e, pml4->used_pml4es)) { |
1154 | pdp = alloc_pdp(dev); | |
1155 | if (IS_ERR(pdp)) | |
1156 | goto unwind_out; | |
1157 | ||
69ab76fd | 1158 | gen8_initialize_pdp(vm, pdp); |
762d9936 MT |
1159 | pml4->pdps[pml4e] = pdp; |
1160 | __set_bit(pml4e, new_pdps); | |
1161 | trace_i915_page_directory_pointer_entry_alloc(vm, | |
1162 | pml4e, | |
1163 | start, | |
1164 | GEN8_PML4E_SHIFT); | |
1165 | } | |
1166 | } | |
1167 | ||
1168 | return 0; | |
1169 | ||
1170 | unwind_out: | |
1171 | for_each_set_bit(pml4e, new_pdps, GEN8_PML4ES_PER_PML4) | |
1172 | free_pdp(dev, pml4->pdps[pml4e]); | |
1173 | ||
1174 | return -ENOMEM; | |
1175 | } | |
1176 | ||
d7b2633d | 1177 | static void |
3a41a05d | 1178 | free_gen8_temp_bitmaps(unsigned long *new_pds, unsigned long *new_pts) |
d7b2633d | 1179 | { |
d7b2633d MT |
1180 | kfree(new_pts); |
1181 | kfree(new_pds); | |
1182 | } | |
1183 | ||
1184 | /* Fills in the page directory bitmap, and the array of page tables bitmap. Both | |
1185 | * of these are based on the number of PDPEs in the system. | |
1186 | */ | |
1187 | static | |
1188 | int __must_check alloc_gen8_temp_bitmaps(unsigned long **new_pds, | |
3a41a05d | 1189 | unsigned long **new_pts, |
6ac18502 | 1190 | uint32_t pdpes) |
d7b2633d | 1191 | { |
d7b2633d | 1192 | unsigned long *pds; |
3a41a05d | 1193 | unsigned long *pts; |
d7b2633d | 1194 | |
3a41a05d | 1195 | pds = kcalloc(BITS_TO_LONGS(pdpes), sizeof(unsigned long), GFP_TEMPORARY); |
d7b2633d MT |
1196 | if (!pds) |
1197 | return -ENOMEM; | |
1198 | ||
3a41a05d MW |
1199 | pts = kcalloc(pdpes, BITS_TO_LONGS(I915_PDES) * sizeof(unsigned long), |
1200 | GFP_TEMPORARY); | |
1201 | if (!pts) | |
1202 | goto err_out; | |
d7b2633d MT |
1203 | |
1204 | *new_pds = pds; | |
1205 | *new_pts = pts; | |
1206 | ||
1207 | return 0; | |
1208 | ||
1209 | err_out: | |
3a41a05d | 1210 | free_gen8_temp_bitmaps(pds, pts); |
d7b2633d MT |
1211 | return -ENOMEM; |
1212 | } | |
1213 | ||
5b7e4c9c MK |
1214 | /* PDE TLBs are a pain to invalidate on GEN8+. When we modify |
1215 | * the page table structures, we mark them dirty so that | |
1216 | * context switching/execlist queuing code takes extra steps | |
1217 | * to ensure that tlbs are flushed. | |
1218 | */ | |
1219 | static void mark_tlbs_dirty(struct i915_hw_ppgtt *ppgtt) | |
1220 | { | |
1221 | ppgtt->pd_dirty_rings = INTEL_INFO(ppgtt->base.dev)->ring_mask; | |
1222 | } | |
1223 | ||
762d9936 MT |
1224 | static int gen8_alloc_va_range_3lvl(struct i915_address_space *vm, |
1225 | struct i915_page_directory_pointer *pdp, | |
1226 | uint64_t start, | |
1227 | uint64_t length) | |
bf2b4ed2 | 1228 | { |
e5716f55 | 1229 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
3a41a05d | 1230 | unsigned long *new_page_dirs, *new_page_tables; |
d4ec9da0 | 1231 | struct drm_device *dev = vm->dev; |
5441f0cb | 1232 | struct i915_page_directory *pd; |
33c8819f MT |
1233 | const uint64_t orig_start = start; |
1234 | const uint64_t orig_length = length; | |
5441f0cb | 1235 | uint32_t pdpe; |
d4ec9da0 | 1236 | uint32_t pdpes = I915_PDPES_PER_PDP(dev); |
bf2b4ed2 BW |
1237 | int ret; |
1238 | ||
d7b2633d MT |
1239 | /* Wrap is never okay since we can only represent 48b, and we don't |
1240 | * actually use the other side of the canonical address space. | |
1241 | */ | |
1242 | if (WARN_ON(start + length < start)) | |
a05d80ee MK |
1243 | return -ENODEV; |
1244 | ||
d4ec9da0 | 1245 | if (WARN_ON(start + length > vm->total)) |
a05d80ee | 1246 | return -ENODEV; |
d7b2633d | 1247 | |
6ac18502 | 1248 | ret = alloc_gen8_temp_bitmaps(&new_page_dirs, &new_page_tables, pdpes); |
bf2b4ed2 BW |
1249 | if (ret) |
1250 | return ret; | |
1251 | ||
d7b2633d | 1252 | /* Do the allocations first so we can easily bail out */ |
d4ec9da0 MT |
1253 | ret = gen8_ppgtt_alloc_page_directories(vm, pdp, start, length, |
1254 | new_page_dirs); | |
d7b2633d | 1255 | if (ret) { |
3a41a05d | 1256 | free_gen8_temp_bitmaps(new_page_dirs, new_page_tables); |
d7b2633d MT |
1257 | return ret; |
1258 | } | |
1259 | ||
1260 | /* For every page directory referenced, allocate page tables */ | |
e8ebd8e2 | 1261 | gen8_for_each_pdpe(pd, pdp, start, length, pdpe) { |
d4ec9da0 | 1262 | ret = gen8_ppgtt_alloc_pagetabs(vm, pd, start, length, |
3a41a05d | 1263 | new_page_tables + pdpe * BITS_TO_LONGS(I915_PDES)); |
5441f0cb MT |
1264 | if (ret) |
1265 | goto err_out; | |
5441f0cb MT |
1266 | } |
1267 | ||
33c8819f MT |
1268 | start = orig_start; |
1269 | length = orig_length; | |
1270 | ||
d7b2633d MT |
1271 | /* Allocations have completed successfully, so set the bitmaps, and do |
1272 | * the mappings. */ | |
e8ebd8e2 | 1273 | gen8_for_each_pdpe(pd, pdp, start, length, pdpe) { |
d1c54acd | 1274 | gen8_pde_t *const page_directory = kmap_px(pd); |
33c8819f | 1275 | struct i915_page_table *pt; |
09120d4e | 1276 | uint64_t pd_len = length; |
33c8819f MT |
1277 | uint64_t pd_start = start; |
1278 | uint32_t pde; | |
1279 | ||
d7b2633d MT |
1280 | /* Every pd should be allocated, we just did that above. */ |
1281 | WARN_ON(!pd); | |
1282 | ||
e8ebd8e2 | 1283 | gen8_for_each_pde(pt, pd, pd_start, pd_len, pde) { |
d7b2633d MT |
1284 | /* Same reasoning as pd */ |
1285 | WARN_ON(!pt); | |
1286 | WARN_ON(!pd_len); | |
1287 | WARN_ON(!gen8_pte_count(pd_start, pd_len)); | |
1288 | ||
1289 | /* Set our used ptes within the page table */ | |
1290 | bitmap_set(pt->used_ptes, | |
1291 | gen8_pte_index(pd_start), | |
1292 | gen8_pte_count(pd_start, pd_len)); | |
1293 | ||
1294 | /* Our pde is now pointing to the pagetable, pt */ | |
966082c9 | 1295 | __set_bit(pde, pd->used_pdes); |
d7b2633d MT |
1296 | |
1297 | /* Map the PDE to the page table */ | |
fe36f55d MK |
1298 | page_directory[pde] = gen8_pde_encode(px_dma(pt), |
1299 | I915_CACHE_LLC); | |
4c06ec8d MT |
1300 | trace_i915_page_table_entry_map(&ppgtt->base, pde, pt, |
1301 | gen8_pte_index(start), | |
1302 | gen8_pte_count(start, length), | |
1303 | GEN8_PTES); | |
d7b2633d MT |
1304 | |
1305 | /* NB: We haven't yet mapped ptes to pages. At this | |
1306 | * point we're still relying on insert_entries() */ | |
33c8819f | 1307 | } |
d7b2633d | 1308 | |
d1c54acd | 1309 | kunmap_px(ppgtt, page_directory); |
d4ec9da0 | 1310 | __set_bit(pdpe, pdp->used_pdpes); |
762d9936 | 1311 | gen8_setup_page_directory(ppgtt, pdp, pd, pdpe); |
33c8819f MT |
1312 | } |
1313 | ||
3a41a05d | 1314 | free_gen8_temp_bitmaps(new_page_dirs, new_page_tables); |
5b7e4c9c | 1315 | mark_tlbs_dirty(ppgtt); |
d7b3de91 | 1316 | return 0; |
bf2b4ed2 | 1317 | |
d7b3de91 | 1318 | err_out: |
d7b2633d | 1319 | while (pdpe--) { |
e8ebd8e2 DG |
1320 | unsigned long temp; |
1321 | ||
3a41a05d MW |
1322 | for_each_set_bit(temp, new_page_tables + pdpe * |
1323 | BITS_TO_LONGS(I915_PDES), I915_PDES) | |
d4ec9da0 | 1324 | free_pt(dev, pdp->page_directory[pdpe]->page_table[temp]); |
d7b2633d MT |
1325 | } |
1326 | ||
6ac18502 | 1327 | for_each_set_bit(pdpe, new_page_dirs, pdpes) |
d4ec9da0 | 1328 | free_pd(dev, pdp->page_directory[pdpe]); |
d7b2633d | 1329 | |
3a41a05d | 1330 | free_gen8_temp_bitmaps(new_page_dirs, new_page_tables); |
5b7e4c9c | 1331 | mark_tlbs_dirty(ppgtt); |
bf2b4ed2 BW |
1332 | return ret; |
1333 | } | |
1334 | ||
762d9936 MT |
1335 | static int gen8_alloc_va_range_4lvl(struct i915_address_space *vm, |
1336 | struct i915_pml4 *pml4, | |
1337 | uint64_t start, | |
1338 | uint64_t length) | |
1339 | { | |
1340 | DECLARE_BITMAP(new_pdps, GEN8_PML4ES_PER_PML4); | |
e5716f55 | 1341 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
762d9936 | 1342 | struct i915_page_directory_pointer *pdp; |
e8ebd8e2 | 1343 | uint64_t pml4e; |
762d9936 MT |
1344 | int ret = 0; |
1345 | ||
1346 | /* Do the pml4 allocations first, so we don't need to track the newly | |
1347 | * allocated tables below the pdp */ | |
1348 | bitmap_zero(new_pdps, GEN8_PML4ES_PER_PML4); | |
1349 | ||
1350 | /* The pagedirectory and pagetable allocations are done in the shared 3 | |
1351 | * and 4 level code. Just allocate the pdps. | |
1352 | */ | |
1353 | ret = gen8_ppgtt_alloc_page_dirpointers(vm, pml4, start, length, | |
1354 | new_pdps); | |
1355 | if (ret) | |
1356 | return ret; | |
1357 | ||
1358 | WARN(bitmap_weight(new_pdps, GEN8_PML4ES_PER_PML4) > 2, | |
1359 | "The allocation has spanned more than 512GB. " | |
1360 | "It is highly likely this is incorrect."); | |
1361 | ||
e8ebd8e2 | 1362 | gen8_for_each_pml4e(pdp, pml4, start, length, pml4e) { |
762d9936 MT |
1363 | WARN_ON(!pdp); |
1364 | ||
1365 | ret = gen8_alloc_va_range_3lvl(vm, pdp, start, length); | |
1366 | if (ret) | |
1367 | goto err_out; | |
1368 | ||
1369 | gen8_setup_page_directory_pointer(ppgtt, pml4, pdp, pml4e); | |
1370 | } | |
1371 | ||
1372 | bitmap_or(pml4->used_pml4es, new_pdps, pml4->used_pml4es, | |
1373 | GEN8_PML4ES_PER_PML4); | |
1374 | ||
1375 | return 0; | |
1376 | ||
1377 | err_out: | |
1378 | for_each_set_bit(pml4e, new_pdps, GEN8_PML4ES_PER_PML4) | |
1379 | gen8_ppgtt_cleanup_3lvl(vm->dev, pml4->pdps[pml4e]); | |
1380 | ||
1381 | return ret; | |
1382 | } | |
1383 | ||
1384 | static int gen8_alloc_va_range(struct i915_address_space *vm, | |
1385 | uint64_t start, uint64_t length) | |
1386 | { | |
e5716f55 | 1387 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
762d9936 MT |
1388 | |
1389 | if (USES_FULL_48BIT_PPGTT(vm->dev)) | |
1390 | return gen8_alloc_va_range_4lvl(vm, &ppgtt->pml4, start, length); | |
1391 | else | |
1392 | return gen8_alloc_va_range_3lvl(vm, &ppgtt->pdp, start, length); | |
1393 | } | |
1394 | ||
ea91e401 MT |
1395 | static void gen8_dump_pdp(struct i915_page_directory_pointer *pdp, |
1396 | uint64_t start, uint64_t length, | |
1397 | gen8_pte_t scratch_pte, | |
1398 | struct seq_file *m) | |
1399 | { | |
1400 | struct i915_page_directory *pd; | |
ea91e401 MT |
1401 | uint32_t pdpe; |
1402 | ||
e8ebd8e2 | 1403 | gen8_for_each_pdpe(pd, pdp, start, length, pdpe) { |
ea91e401 MT |
1404 | struct i915_page_table *pt; |
1405 | uint64_t pd_len = length; | |
1406 | uint64_t pd_start = start; | |
1407 | uint32_t pde; | |
1408 | ||
1409 | if (!test_bit(pdpe, pdp->used_pdpes)) | |
1410 | continue; | |
1411 | ||
1412 | seq_printf(m, "\tPDPE #%d\n", pdpe); | |
e8ebd8e2 | 1413 | gen8_for_each_pde(pt, pd, pd_start, pd_len, pde) { |
ea91e401 MT |
1414 | uint32_t pte; |
1415 | gen8_pte_t *pt_vaddr; | |
1416 | ||
1417 | if (!test_bit(pde, pd->used_pdes)) | |
1418 | continue; | |
1419 | ||
1420 | pt_vaddr = kmap_px(pt); | |
1421 | for (pte = 0; pte < GEN8_PTES; pte += 4) { | |
1422 | uint64_t va = | |
1423 | (pdpe << GEN8_PDPE_SHIFT) | | |
1424 | (pde << GEN8_PDE_SHIFT) | | |
1425 | (pte << GEN8_PTE_SHIFT); | |
1426 | int i; | |
1427 | bool found = false; | |
1428 | ||
1429 | for (i = 0; i < 4; i++) | |
1430 | if (pt_vaddr[pte + i] != scratch_pte) | |
1431 | found = true; | |
1432 | if (!found) | |
1433 | continue; | |
1434 | ||
1435 | seq_printf(m, "\t\t0x%llx [%03d,%03d,%04d]: =", va, pdpe, pde, pte); | |
1436 | for (i = 0; i < 4; i++) { | |
1437 | if (pt_vaddr[pte + i] != scratch_pte) | |
1438 | seq_printf(m, " %llx", pt_vaddr[pte + i]); | |
1439 | else | |
1440 | seq_puts(m, " SCRATCH "); | |
1441 | } | |
1442 | seq_puts(m, "\n"); | |
1443 | } | |
1444 | /* don't use kunmap_px, it could trigger | |
1445 | * an unnecessary flush. | |
1446 | */ | |
1447 | kunmap_atomic(pt_vaddr); | |
1448 | } | |
1449 | } | |
1450 | } | |
1451 | ||
1452 | static void gen8_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m) | |
1453 | { | |
1454 | struct i915_address_space *vm = &ppgtt->base; | |
1455 | uint64_t start = ppgtt->base.start; | |
1456 | uint64_t length = ppgtt->base.total; | |
1457 | gen8_pte_t scratch_pte = gen8_pte_encode(px_dma(vm->scratch_page), | |
1458 | I915_CACHE_LLC, true); | |
1459 | ||
1460 | if (!USES_FULL_48BIT_PPGTT(vm->dev)) { | |
1461 | gen8_dump_pdp(&ppgtt->pdp, start, length, scratch_pte, m); | |
1462 | } else { | |
e8ebd8e2 | 1463 | uint64_t pml4e; |
ea91e401 MT |
1464 | struct i915_pml4 *pml4 = &ppgtt->pml4; |
1465 | struct i915_page_directory_pointer *pdp; | |
1466 | ||
e8ebd8e2 | 1467 | gen8_for_each_pml4e(pdp, pml4, start, length, pml4e) { |
ea91e401 MT |
1468 | if (!test_bit(pml4e, pml4->used_pml4es)) |
1469 | continue; | |
1470 | ||
1471 | seq_printf(m, " PML4E #%llu\n", pml4e); | |
1472 | gen8_dump_pdp(pdp, start, length, scratch_pte, m); | |
1473 | } | |
1474 | } | |
1475 | } | |
1476 | ||
331f38e7 ZL |
1477 | static int gen8_preallocate_top_level_pdps(struct i915_hw_ppgtt *ppgtt) |
1478 | { | |
3a41a05d | 1479 | unsigned long *new_page_dirs, *new_page_tables; |
331f38e7 ZL |
1480 | uint32_t pdpes = I915_PDPES_PER_PDP(dev); |
1481 | int ret; | |
1482 | ||
1483 | /* We allocate temp bitmap for page tables for no gain | |
1484 | * but as this is for init only, lets keep the things simple | |
1485 | */ | |
1486 | ret = alloc_gen8_temp_bitmaps(&new_page_dirs, &new_page_tables, pdpes); | |
1487 | if (ret) | |
1488 | return ret; | |
1489 | ||
1490 | /* Allocate for all pdps regardless of how the ppgtt | |
1491 | * was defined. | |
1492 | */ | |
1493 | ret = gen8_ppgtt_alloc_page_directories(&ppgtt->base, &ppgtt->pdp, | |
1494 | 0, 1ULL << 32, | |
1495 | new_page_dirs); | |
1496 | if (!ret) | |
1497 | *ppgtt->pdp.used_pdpes = *new_page_dirs; | |
1498 | ||
3a41a05d | 1499 | free_gen8_temp_bitmaps(new_page_dirs, new_page_tables); |
331f38e7 ZL |
1500 | |
1501 | return ret; | |
1502 | } | |
1503 | ||
eb0b44ad | 1504 | /* |
f3a964b9 BW |
1505 | * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers |
1506 | * with a net effect resembling a 2-level page table in normal x86 terms. Each | |
1507 | * PDP represents 1GB of memory 4 * 512 * 512 * 4096 = 4GB legacy 32b address | |
1508 | * space. | |
37aca44a | 1509 | * |
f3a964b9 | 1510 | */ |
5c5f6457 | 1511 | static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt) |
37aca44a | 1512 | { |
8776f02b | 1513 | int ret; |
7cb6d7ac | 1514 | |
8776f02b MK |
1515 | ret = gen8_init_scratch(&ppgtt->base); |
1516 | if (ret) | |
1517 | return ret; | |
69876bed | 1518 | |
d7b2633d | 1519 | ppgtt->base.start = 0; |
d7b2633d | 1520 | ppgtt->base.cleanup = gen8_ppgtt_cleanup; |
5c5f6457 | 1521 | ppgtt->base.allocate_va_range = gen8_alloc_va_range; |
d7b2633d | 1522 | ppgtt->base.insert_entries = gen8_ppgtt_insert_entries; |
c7e16f22 | 1523 | ppgtt->base.clear_range = gen8_ppgtt_clear_range; |
777dc5bb DV |
1524 | ppgtt->base.unbind_vma = ppgtt_unbind_vma; |
1525 | ppgtt->base.bind_vma = ppgtt_bind_vma; | |
ea91e401 | 1526 | ppgtt->debug_dump = gen8_dump_ppgtt; |
d7b2633d | 1527 | |
762d9936 MT |
1528 | if (USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) { |
1529 | ret = setup_px(ppgtt->base.dev, &ppgtt->pml4); | |
1530 | if (ret) | |
1531 | goto free_scratch; | |
6ac18502 | 1532 | |
69ab76fd MT |
1533 | gen8_initialize_pml4(&ppgtt->base, &ppgtt->pml4); |
1534 | ||
762d9936 | 1535 | ppgtt->base.total = 1ULL << 48; |
2dba3239 | 1536 | ppgtt->switch_mm = gen8_48b_mm_switch; |
762d9936 | 1537 | } else { |
25f50337 | 1538 | ret = __pdp_init(ppgtt->base.dev, &ppgtt->pdp); |
81ba8aef MT |
1539 | if (ret) |
1540 | goto free_scratch; | |
1541 | ||
1542 | ppgtt->base.total = 1ULL << 32; | |
2dba3239 | 1543 | ppgtt->switch_mm = gen8_legacy_mm_switch; |
762d9936 MT |
1544 | trace_i915_page_directory_pointer_entry_alloc(&ppgtt->base, |
1545 | 0, 0, | |
1546 | GEN8_PML4E_SHIFT); | |
331f38e7 ZL |
1547 | |
1548 | if (intel_vgpu_active(ppgtt->base.dev)) { | |
1549 | ret = gen8_preallocate_top_level_pdps(ppgtt); | |
1550 | if (ret) | |
1551 | goto free_scratch; | |
1552 | } | |
81ba8aef | 1553 | } |
6ac18502 | 1554 | |
650da34c ZL |
1555 | if (intel_vgpu_active(ppgtt->base.dev)) |
1556 | gen8_ppgtt_notify_vgt(ppgtt, true); | |
1557 | ||
d7b2633d | 1558 | return 0; |
6ac18502 MT |
1559 | |
1560 | free_scratch: | |
1561 | gen8_free_scratch(&ppgtt->base); | |
1562 | return ret; | |
d7b2633d MT |
1563 | } |
1564 | ||
87d60b63 BW |
1565 | static void gen6_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m) |
1566 | { | |
87d60b63 | 1567 | struct i915_address_space *vm = &ppgtt->base; |
09942c65 | 1568 | struct i915_page_table *unused; |
07749ef3 | 1569 | gen6_pte_t scratch_pte; |
87d60b63 | 1570 | uint32_t pd_entry; |
09942c65 MT |
1571 | uint32_t pte, pde, temp; |
1572 | uint32_t start = ppgtt->base.start, length = ppgtt->base.total; | |
87d60b63 | 1573 | |
79ab9370 MK |
1574 | scratch_pte = vm->pte_encode(px_dma(vm->scratch_page), |
1575 | I915_CACHE_LLC, true, 0); | |
87d60b63 | 1576 | |
09942c65 | 1577 | gen6_for_each_pde(unused, &ppgtt->pd, start, length, temp, pde) { |
87d60b63 | 1578 | u32 expected; |
07749ef3 | 1579 | gen6_pte_t *pt_vaddr; |
567047be | 1580 | const dma_addr_t pt_addr = px_dma(ppgtt->pd.page_table[pde]); |
09942c65 | 1581 | pd_entry = readl(ppgtt->pd_addr + pde); |
87d60b63 BW |
1582 | expected = (GEN6_PDE_ADDR_ENCODE(pt_addr) | GEN6_PDE_VALID); |
1583 | ||
1584 | if (pd_entry != expected) | |
1585 | seq_printf(m, "\tPDE #%d mismatch: Actual PDE: %x Expected PDE: %x\n", | |
1586 | pde, | |
1587 | pd_entry, | |
1588 | expected); | |
1589 | seq_printf(m, "\tPDE: %x\n", pd_entry); | |
1590 | ||
d1c54acd MK |
1591 | pt_vaddr = kmap_px(ppgtt->pd.page_table[pde]); |
1592 | ||
07749ef3 | 1593 | for (pte = 0; pte < GEN6_PTES; pte+=4) { |
87d60b63 | 1594 | unsigned long va = |
07749ef3 | 1595 | (pde * PAGE_SIZE * GEN6_PTES) + |
87d60b63 BW |
1596 | (pte * PAGE_SIZE); |
1597 | int i; | |
1598 | bool found = false; | |
1599 | for (i = 0; i < 4; i++) | |
1600 | if (pt_vaddr[pte + i] != scratch_pte) | |
1601 | found = true; | |
1602 | if (!found) | |
1603 | continue; | |
1604 | ||
1605 | seq_printf(m, "\t\t0x%lx [%03d,%04d]: =", va, pde, pte); | |
1606 | for (i = 0; i < 4; i++) { | |
1607 | if (pt_vaddr[pte + i] != scratch_pte) | |
1608 | seq_printf(m, " %08x", pt_vaddr[pte + i]); | |
1609 | else | |
1610 | seq_puts(m, " SCRATCH "); | |
1611 | } | |
1612 | seq_puts(m, "\n"); | |
1613 | } | |
d1c54acd | 1614 | kunmap_px(ppgtt, pt_vaddr); |
87d60b63 BW |
1615 | } |
1616 | } | |
1617 | ||
678d96fb | 1618 | /* Write pde (index) from the page directory @pd to the page table @pt */ |
ec565b3c MT |
1619 | static void gen6_write_pde(struct i915_page_directory *pd, |
1620 | const int pde, struct i915_page_table *pt) | |
6197349b | 1621 | { |
678d96fb BW |
1622 | /* Caller needs to make sure the write completes if necessary */ |
1623 | struct i915_hw_ppgtt *ppgtt = | |
1624 | container_of(pd, struct i915_hw_ppgtt, pd); | |
1625 | u32 pd_entry; | |
6197349b | 1626 | |
567047be | 1627 | pd_entry = GEN6_PDE_ADDR_ENCODE(px_dma(pt)); |
678d96fb | 1628 | pd_entry |= GEN6_PDE_VALID; |
6197349b | 1629 | |
678d96fb BW |
1630 | writel(pd_entry, ppgtt->pd_addr + pde); |
1631 | } | |
6197349b | 1632 | |
678d96fb BW |
1633 | /* Write all the page tables found in the ppgtt structure to incrementing page |
1634 | * directories. */ | |
1635 | static void gen6_write_page_range(struct drm_i915_private *dev_priv, | |
ec565b3c | 1636 | struct i915_page_directory *pd, |
678d96fb BW |
1637 | uint32_t start, uint32_t length) |
1638 | { | |
72e96d64 | 1639 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
ec565b3c | 1640 | struct i915_page_table *pt; |
678d96fb BW |
1641 | uint32_t pde, temp; |
1642 | ||
1643 | gen6_for_each_pde(pt, pd, start, length, temp, pde) | |
1644 | gen6_write_pde(pd, pde, pt); | |
1645 | ||
1646 | /* Make sure write is complete before other code can use this page | |
1647 | * table. Also require for WC mapped PTEs */ | |
72e96d64 | 1648 | readl(ggtt->gsm); |
3e302542 BW |
1649 | } |
1650 | ||
b4a74e3a | 1651 | static uint32_t get_pd_offset(struct i915_hw_ppgtt *ppgtt) |
3e302542 | 1652 | { |
44159ddb | 1653 | BUG_ON(ppgtt->pd.base.ggtt_offset & 0x3f); |
b4a74e3a | 1654 | |
44159ddb | 1655 | return (ppgtt->pd.base.ggtt_offset / 64) << 16; |
b4a74e3a BW |
1656 | } |
1657 | ||
90252e5c | 1658 | static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt, |
e85b26dc | 1659 | struct drm_i915_gem_request *req) |
90252e5c | 1660 | { |
4a570db5 | 1661 | struct intel_engine_cs *engine = req->engine; |
90252e5c BW |
1662 | int ret; |
1663 | ||
90252e5c | 1664 | /* NB: TLBs must be flushed and invalidated before a switch */ |
e2f80391 | 1665 | ret = engine->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); |
90252e5c BW |
1666 | if (ret) |
1667 | return ret; | |
1668 | ||
5fb9de1a | 1669 | ret = intel_ring_begin(req, 6); |
90252e5c BW |
1670 | if (ret) |
1671 | return ret; | |
1672 | ||
e2f80391 TU |
1673 | intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(2)); |
1674 | intel_ring_emit_reg(engine, RING_PP_DIR_DCLV(engine)); | |
1675 | intel_ring_emit(engine, PP_DIR_DCLV_2G); | |
1676 | intel_ring_emit_reg(engine, RING_PP_DIR_BASE(engine)); | |
1677 | intel_ring_emit(engine, get_pd_offset(ppgtt)); | |
1678 | intel_ring_emit(engine, MI_NOOP); | |
1679 | intel_ring_advance(engine); | |
90252e5c BW |
1680 | |
1681 | return 0; | |
1682 | } | |
1683 | ||
71ba2d64 | 1684 | static int vgpu_mm_switch(struct i915_hw_ppgtt *ppgtt, |
e85b26dc | 1685 | struct drm_i915_gem_request *req) |
71ba2d64 | 1686 | { |
4a570db5 | 1687 | struct intel_engine_cs *engine = req->engine; |
71ba2d64 YZ |
1688 | struct drm_i915_private *dev_priv = to_i915(ppgtt->base.dev); |
1689 | ||
e2f80391 TU |
1690 | I915_WRITE(RING_PP_DIR_DCLV(engine), PP_DIR_DCLV_2G); |
1691 | I915_WRITE(RING_PP_DIR_BASE(engine), get_pd_offset(ppgtt)); | |
71ba2d64 YZ |
1692 | return 0; |
1693 | } | |
1694 | ||
48a10389 | 1695 | static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt, |
e85b26dc | 1696 | struct drm_i915_gem_request *req) |
48a10389 | 1697 | { |
4a570db5 | 1698 | struct intel_engine_cs *engine = req->engine; |
48a10389 BW |
1699 | int ret; |
1700 | ||
48a10389 | 1701 | /* NB: TLBs must be flushed and invalidated before a switch */ |
e2f80391 | 1702 | ret = engine->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); |
48a10389 BW |
1703 | if (ret) |
1704 | return ret; | |
1705 | ||
5fb9de1a | 1706 | ret = intel_ring_begin(req, 6); |
48a10389 BW |
1707 | if (ret) |
1708 | return ret; | |
1709 | ||
e2f80391 TU |
1710 | intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(2)); |
1711 | intel_ring_emit_reg(engine, RING_PP_DIR_DCLV(engine)); | |
1712 | intel_ring_emit(engine, PP_DIR_DCLV_2G); | |
1713 | intel_ring_emit_reg(engine, RING_PP_DIR_BASE(engine)); | |
1714 | intel_ring_emit(engine, get_pd_offset(ppgtt)); | |
1715 | intel_ring_emit(engine, MI_NOOP); | |
1716 | intel_ring_advance(engine); | |
48a10389 | 1717 | |
90252e5c | 1718 | /* XXX: RCS is the only one to auto invalidate the TLBs? */ |
e2f80391 TU |
1719 | if (engine->id != RCS) { |
1720 | ret = engine->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); | |
90252e5c BW |
1721 | if (ret) |
1722 | return ret; | |
1723 | } | |
1724 | ||
48a10389 BW |
1725 | return 0; |
1726 | } | |
1727 | ||
eeb9488e | 1728 | static int gen6_mm_switch(struct i915_hw_ppgtt *ppgtt, |
e85b26dc | 1729 | struct drm_i915_gem_request *req) |
eeb9488e | 1730 | { |
4a570db5 | 1731 | struct intel_engine_cs *engine = req->engine; |
eeb9488e BW |
1732 | struct drm_device *dev = ppgtt->base.dev; |
1733 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1734 | ||
48a10389 | 1735 | |
e2f80391 TU |
1736 | I915_WRITE(RING_PP_DIR_DCLV(engine), PP_DIR_DCLV_2G); |
1737 | I915_WRITE(RING_PP_DIR_BASE(engine), get_pd_offset(ppgtt)); | |
eeb9488e | 1738 | |
e2f80391 | 1739 | POSTING_READ(RING_PP_DIR_DCLV(engine)); |
eeb9488e BW |
1740 | |
1741 | return 0; | |
1742 | } | |
1743 | ||
82460d97 | 1744 | static void gen8_ppgtt_enable(struct drm_device *dev) |
eeb9488e | 1745 | { |
eeb9488e | 1746 | struct drm_i915_private *dev_priv = dev->dev_private; |
e2f80391 | 1747 | struct intel_engine_cs *engine; |
3e302542 | 1748 | |
b4ac5afc | 1749 | for_each_engine(engine, dev_priv) { |
2dba3239 | 1750 | u32 four_level = USES_FULL_48BIT_PPGTT(dev) ? GEN8_GFX_PPGTT_48B : 0; |
e2f80391 | 1751 | I915_WRITE(RING_MODE_GEN7(engine), |
2dba3239 | 1752 | _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE | four_level)); |
eeb9488e | 1753 | } |
eeb9488e | 1754 | } |
6197349b | 1755 | |
82460d97 | 1756 | static void gen7_ppgtt_enable(struct drm_device *dev) |
3e302542 | 1757 | { |
50227e1c | 1758 | struct drm_i915_private *dev_priv = dev->dev_private; |
e2f80391 | 1759 | struct intel_engine_cs *engine; |
b4a74e3a | 1760 | uint32_t ecochk, ecobits; |
6197349b | 1761 | |
b4a74e3a BW |
1762 | ecobits = I915_READ(GAC_ECO_BITS); |
1763 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B); | |
a65c2fcd | 1764 | |
b4a74e3a BW |
1765 | ecochk = I915_READ(GAM_ECOCHK); |
1766 | if (IS_HASWELL(dev)) { | |
1767 | ecochk |= ECOCHK_PPGTT_WB_HSW; | |
1768 | } else { | |
1769 | ecochk |= ECOCHK_PPGTT_LLC_IVB; | |
1770 | ecochk &= ~ECOCHK_PPGTT_GFDT_IVB; | |
1771 | } | |
1772 | I915_WRITE(GAM_ECOCHK, ecochk); | |
a65c2fcd | 1773 | |
b4ac5afc | 1774 | for_each_engine(engine, dev_priv) { |
6197349b | 1775 | /* GFX_MODE is per-ring on gen7+ */ |
e2f80391 | 1776 | I915_WRITE(RING_MODE_GEN7(engine), |
b4a74e3a | 1777 | _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); |
6197349b | 1778 | } |
b4a74e3a | 1779 | } |
6197349b | 1780 | |
82460d97 | 1781 | static void gen6_ppgtt_enable(struct drm_device *dev) |
b4a74e3a | 1782 | { |
50227e1c | 1783 | struct drm_i915_private *dev_priv = dev->dev_private; |
b4a74e3a | 1784 | uint32_t ecochk, gab_ctl, ecobits; |
a65c2fcd | 1785 | |
b4a74e3a BW |
1786 | ecobits = I915_READ(GAC_ECO_BITS); |
1787 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT | | |
1788 | ECOBITS_PPGTT_CACHE64B); | |
6197349b | 1789 | |
b4a74e3a BW |
1790 | gab_ctl = I915_READ(GAB_CTL); |
1791 | I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT); | |
1792 | ||
1793 | ecochk = I915_READ(GAM_ECOCHK); | |
1794 | I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B); | |
1795 | ||
1796 | I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
6197349b BW |
1797 | } |
1798 | ||
1d2a314c | 1799 | /* PPGTT support for Sandybdrige/Gen6 and later */ |
853ba5d2 | 1800 | static void gen6_ppgtt_clear_range(struct i915_address_space *vm, |
782f1495 BW |
1801 | uint64_t start, |
1802 | uint64_t length, | |
828c7908 | 1803 | bool use_scratch) |
1d2a314c | 1804 | { |
e5716f55 | 1805 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
07749ef3 | 1806 | gen6_pte_t *pt_vaddr, scratch_pte; |
782f1495 BW |
1807 | unsigned first_entry = start >> PAGE_SHIFT; |
1808 | unsigned num_entries = length >> PAGE_SHIFT; | |
07749ef3 MT |
1809 | unsigned act_pt = first_entry / GEN6_PTES; |
1810 | unsigned first_pte = first_entry % GEN6_PTES; | |
7bddb01f | 1811 | unsigned last_pte, i; |
1d2a314c | 1812 | |
c114f76a MK |
1813 | scratch_pte = vm->pte_encode(px_dma(vm->scratch_page), |
1814 | I915_CACHE_LLC, true, 0); | |
1d2a314c | 1815 | |
7bddb01f DV |
1816 | while (num_entries) { |
1817 | last_pte = first_pte + num_entries; | |
07749ef3 MT |
1818 | if (last_pte > GEN6_PTES) |
1819 | last_pte = GEN6_PTES; | |
7bddb01f | 1820 | |
d1c54acd | 1821 | pt_vaddr = kmap_px(ppgtt->pd.page_table[act_pt]); |
1d2a314c | 1822 | |
7bddb01f DV |
1823 | for (i = first_pte; i < last_pte; i++) |
1824 | pt_vaddr[i] = scratch_pte; | |
1d2a314c | 1825 | |
d1c54acd | 1826 | kunmap_px(ppgtt, pt_vaddr); |
1d2a314c | 1827 | |
7bddb01f DV |
1828 | num_entries -= last_pte - first_pte; |
1829 | first_pte = 0; | |
a15326a5 | 1830 | act_pt++; |
7bddb01f | 1831 | } |
1d2a314c DV |
1832 | } |
1833 | ||
853ba5d2 | 1834 | static void gen6_ppgtt_insert_entries(struct i915_address_space *vm, |
def886c3 | 1835 | struct sg_table *pages, |
782f1495 | 1836 | uint64_t start, |
24f3a8cf | 1837 | enum i915_cache_level cache_level, u32 flags) |
def886c3 | 1838 | { |
e5716f55 | 1839 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
07749ef3 | 1840 | gen6_pte_t *pt_vaddr; |
782f1495 | 1841 | unsigned first_entry = start >> PAGE_SHIFT; |
07749ef3 MT |
1842 | unsigned act_pt = first_entry / GEN6_PTES; |
1843 | unsigned act_pte = first_entry % GEN6_PTES; | |
6e995e23 ID |
1844 | struct sg_page_iter sg_iter; |
1845 | ||
cc79714f | 1846 | pt_vaddr = NULL; |
6e995e23 | 1847 | for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) { |
cc79714f | 1848 | if (pt_vaddr == NULL) |
d1c54acd | 1849 | pt_vaddr = kmap_px(ppgtt->pd.page_table[act_pt]); |
6e995e23 | 1850 | |
cc79714f CW |
1851 | pt_vaddr[act_pte] = |
1852 | vm->pte_encode(sg_page_iter_dma_address(&sg_iter), | |
24f3a8cf AG |
1853 | cache_level, true, flags); |
1854 | ||
07749ef3 | 1855 | if (++act_pte == GEN6_PTES) { |
d1c54acd | 1856 | kunmap_px(ppgtt, pt_vaddr); |
cc79714f | 1857 | pt_vaddr = NULL; |
a15326a5 | 1858 | act_pt++; |
6e995e23 | 1859 | act_pte = 0; |
def886c3 | 1860 | } |
def886c3 | 1861 | } |
cc79714f | 1862 | if (pt_vaddr) |
d1c54acd | 1863 | kunmap_px(ppgtt, pt_vaddr); |
def886c3 DV |
1864 | } |
1865 | ||
678d96fb | 1866 | static int gen6_alloc_va_range(struct i915_address_space *vm, |
a05d80ee | 1867 | uint64_t start_in, uint64_t length_in) |
678d96fb | 1868 | { |
4933d519 MT |
1869 | DECLARE_BITMAP(new_page_tables, I915_PDES); |
1870 | struct drm_device *dev = vm->dev; | |
72e96d64 JL |
1871 | struct drm_i915_private *dev_priv = to_i915(dev); |
1872 | struct i915_ggtt *ggtt = &dev_priv->ggtt; | |
e5716f55 | 1873 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
ec565b3c | 1874 | struct i915_page_table *pt; |
a05d80ee | 1875 | uint32_t start, length, start_save, length_save; |
678d96fb | 1876 | uint32_t pde, temp; |
4933d519 MT |
1877 | int ret; |
1878 | ||
a05d80ee MK |
1879 | if (WARN_ON(start_in + length_in > ppgtt->base.total)) |
1880 | return -ENODEV; | |
1881 | ||
1882 | start = start_save = start_in; | |
1883 | length = length_save = length_in; | |
4933d519 MT |
1884 | |
1885 | bitmap_zero(new_page_tables, I915_PDES); | |
1886 | ||
1887 | /* The allocation is done in two stages so that we can bail out with | |
1888 | * minimal amount of pain. The first stage finds new page tables that | |
1889 | * need allocation. The second stage marks use ptes within the page | |
1890 | * tables. | |
1891 | */ | |
1892 | gen6_for_each_pde(pt, &ppgtt->pd, start, length, temp, pde) { | |
79ab9370 | 1893 | if (pt != vm->scratch_pt) { |
4933d519 MT |
1894 | WARN_ON(bitmap_empty(pt->used_ptes, GEN6_PTES)); |
1895 | continue; | |
1896 | } | |
1897 | ||
1898 | /* We've already allocated a page table */ | |
1899 | WARN_ON(!bitmap_empty(pt->used_ptes, GEN6_PTES)); | |
1900 | ||
8a1ebd74 | 1901 | pt = alloc_pt(dev); |
4933d519 MT |
1902 | if (IS_ERR(pt)) { |
1903 | ret = PTR_ERR(pt); | |
1904 | goto unwind_out; | |
1905 | } | |
1906 | ||
1907 | gen6_initialize_pt(vm, pt); | |
1908 | ||
1909 | ppgtt->pd.page_table[pde] = pt; | |
966082c9 | 1910 | __set_bit(pde, new_page_tables); |
72744cb1 | 1911 | trace_i915_page_table_entry_alloc(vm, pde, start, GEN6_PDE_SHIFT); |
4933d519 MT |
1912 | } |
1913 | ||
1914 | start = start_save; | |
1915 | length = length_save; | |
678d96fb BW |
1916 | |
1917 | gen6_for_each_pde(pt, &ppgtt->pd, start, length, temp, pde) { | |
1918 | DECLARE_BITMAP(tmp_bitmap, GEN6_PTES); | |
1919 | ||
1920 | bitmap_zero(tmp_bitmap, GEN6_PTES); | |
1921 | bitmap_set(tmp_bitmap, gen6_pte_index(start), | |
1922 | gen6_pte_count(start, length)); | |
1923 | ||
966082c9 | 1924 | if (__test_and_clear_bit(pde, new_page_tables)) |
4933d519 MT |
1925 | gen6_write_pde(&ppgtt->pd, pde, pt); |
1926 | ||
72744cb1 MT |
1927 | trace_i915_page_table_entry_map(vm, pde, pt, |
1928 | gen6_pte_index(start), | |
1929 | gen6_pte_count(start, length), | |
1930 | GEN6_PTES); | |
4933d519 | 1931 | bitmap_or(pt->used_ptes, tmp_bitmap, pt->used_ptes, |
678d96fb BW |
1932 | GEN6_PTES); |
1933 | } | |
1934 | ||
4933d519 MT |
1935 | WARN_ON(!bitmap_empty(new_page_tables, I915_PDES)); |
1936 | ||
1937 | /* Make sure write is complete before other code can use this page | |
1938 | * table. Also require for WC mapped PTEs */ | |
72e96d64 | 1939 | readl(ggtt->gsm); |
4933d519 | 1940 | |
563222a7 | 1941 | mark_tlbs_dirty(ppgtt); |
678d96fb | 1942 | return 0; |
4933d519 MT |
1943 | |
1944 | unwind_out: | |
1945 | for_each_set_bit(pde, new_page_tables, I915_PDES) { | |
ec565b3c | 1946 | struct i915_page_table *pt = ppgtt->pd.page_table[pde]; |
4933d519 | 1947 | |
79ab9370 | 1948 | ppgtt->pd.page_table[pde] = vm->scratch_pt; |
a08e111a | 1949 | free_pt(vm->dev, pt); |
4933d519 MT |
1950 | } |
1951 | ||
1952 | mark_tlbs_dirty(ppgtt); | |
1953 | return ret; | |
678d96fb BW |
1954 | } |
1955 | ||
8776f02b MK |
1956 | static int gen6_init_scratch(struct i915_address_space *vm) |
1957 | { | |
1958 | struct drm_device *dev = vm->dev; | |
1959 | ||
1960 | vm->scratch_page = alloc_scratch_page(dev); | |
1961 | if (IS_ERR(vm->scratch_page)) | |
1962 | return PTR_ERR(vm->scratch_page); | |
1963 | ||
1964 | vm->scratch_pt = alloc_pt(dev); | |
1965 | if (IS_ERR(vm->scratch_pt)) { | |
1966 | free_scratch_page(dev, vm->scratch_page); | |
1967 | return PTR_ERR(vm->scratch_pt); | |
1968 | } | |
1969 | ||
1970 | gen6_initialize_pt(vm, vm->scratch_pt); | |
1971 | ||
1972 | return 0; | |
1973 | } | |
1974 | ||
1975 | static void gen6_free_scratch(struct i915_address_space *vm) | |
1976 | { | |
1977 | struct drm_device *dev = vm->dev; | |
1978 | ||
1979 | free_pt(dev, vm->scratch_pt); | |
1980 | free_scratch_page(dev, vm->scratch_page); | |
1981 | } | |
1982 | ||
061dd493 | 1983 | static void gen6_ppgtt_cleanup(struct i915_address_space *vm) |
a00d825d | 1984 | { |
e5716f55 | 1985 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
09942c65 MT |
1986 | struct i915_page_table *pt; |
1987 | uint32_t pde; | |
4933d519 | 1988 | |
061dd493 DV |
1989 | drm_mm_remove_node(&ppgtt->node); |
1990 | ||
09942c65 | 1991 | gen6_for_all_pdes(pt, ppgtt, pde) { |
79ab9370 | 1992 | if (pt != vm->scratch_pt) |
a08e111a | 1993 | free_pt(ppgtt->base.dev, pt); |
4933d519 | 1994 | } |
06fda602 | 1995 | |
8776f02b | 1996 | gen6_free_scratch(vm); |
3440d265 DV |
1997 | } |
1998 | ||
b146520f | 1999 | static int gen6_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt) |
3440d265 | 2000 | { |
8776f02b | 2001 | struct i915_address_space *vm = &ppgtt->base; |
853ba5d2 | 2002 | struct drm_device *dev = ppgtt->base.dev; |
72e96d64 JL |
2003 | struct drm_i915_private *dev_priv = to_i915(dev); |
2004 | struct i915_ggtt *ggtt = &dev_priv->ggtt; | |
e3cc1995 | 2005 | bool retried = false; |
b146520f | 2006 | int ret; |
1d2a314c | 2007 | |
c8d4c0d6 BW |
2008 | /* PPGTT PDEs reside in the GGTT and consists of 512 entries. The |
2009 | * allocator works in address space sizes, so it's multiplied by page | |
2010 | * size. We allocate at the top of the GTT to avoid fragmentation. | |
2011 | */ | |
72e96d64 | 2012 | BUG_ON(!drm_mm_initialized(&ggtt->base.mm)); |
4933d519 | 2013 | |
8776f02b MK |
2014 | ret = gen6_init_scratch(vm); |
2015 | if (ret) | |
2016 | return ret; | |
4933d519 | 2017 | |
e3cc1995 | 2018 | alloc: |
72e96d64 | 2019 | ret = drm_mm_insert_node_in_range_generic(&ggtt->base.mm, |
c8d4c0d6 BW |
2020 | &ppgtt->node, GEN6_PD_SIZE, |
2021 | GEN6_PD_ALIGN, 0, | |
72e96d64 | 2022 | 0, ggtt->base.total, |
3e8b5ae9 | 2023 | DRM_MM_TOPDOWN); |
e3cc1995 | 2024 | if (ret == -ENOSPC && !retried) { |
72e96d64 | 2025 | ret = i915_gem_evict_something(dev, &ggtt->base, |
e3cc1995 | 2026 | GEN6_PD_SIZE, GEN6_PD_ALIGN, |
d23db88c | 2027 | I915_CACHE_NONE, |
72e96d64 | 2028 | 0, ggtt->base.total, |
d23db88c | 2029 | 0); |
e3cc1995 | 2030 | if (ret) |
678d96fb | 2031 | goto err_out; |
e3cc1995 BW |
2032 | |
2033 | retried = true; | |
2034 | goto alloc; | |
2035 | } | |
c8d4c0d6 | 2036 | |
c8c26622 | 2037 | if (ret) |
678d96fb BW |
2038 | goto err_out; |
2039 | ||
c8c26622 | 2040 | |
72e96d64 | 2041 | if (ppgtt->node.start < ggtt->mappable_end) |
c8d4c0d6 | 2042 | DRM_DEBUG("Forced to use aperture for PDEs\n"); |
1d2a314c | 2043 | |
c8c26622 | 2044 | return 0; |
678d96fb BW |
2045 | |
2046 | err_out: | |
8776f02b | 2047 | gen6_free_scratch(vm); |
678d96fb | 2048 | return ret; |
b146520f BW |
2049 | } |
2050 | ||
b146520f BW |
2051 | static int gen6_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt) |
2052 | { | |
2f2cf682 | 2053 | return gen6_ppgtt_allocate_page_directories(ppgtt); |
4933d519 | 2054 | } |
06dc68d6 | 2055 | |
4933d519 MT |
2056 | static void gen6_scratch_va_range(struct i915_hw_ppgtt *ppgtt, |
2057 | uint64_t start, uint64_t length) | |
2058 | { | |
ec565b3c | 2059 | struct i915_page_table *unused; |
4933d519 | 2060 | uint32_t pde, temp; |
1d2a314c | 2061 | |
4933d519 | 2062 | gen6_for_each_pde(unused, &ppgtt->pd, start, length, temp, pde) |
79ab9370 | 2063 | ppgtt->pd.page_table[pde] = ppgtt->base.scratch_pt; |
b146520f BW |
2064 | } |
2065 | ||
5c5f6457 | 2066 | static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt) |
b146520f BW |
2067 | { |
2068 | struct drm_device *dev = ppgtt->base.dev; | |
72e96d64 JL |
2069 | struct drm_i915_private *dev_priv = to_i915(dev); |
2070 | struct i915_ggtt *ggtt = &dev_priv->ggtt; | |
b146520f BW |
2071 | int ret; |
2072 | ||
72e96d64 | 2073 | ppgtt->base.pte_encode = ggtt->base.pte_encode; |
b146520f | 2074 | if (IS_GEN6(dev)) { |
b146520f BW |
2075 | ppgtt->switch_mm = gen6_mm_switch; |
2076 | } else if (IS_HASWELL(dev)) { | |
b146520f BW |
2077 | ppgtt->switch_mm = hsw_mm_switch; |
2078 | } else if (IS_GEN7(dev)) { | |
b146520f BW |
2079 | ppgtt->switch_mm = gen7_mm_switch; |
2080 | } else | |
2081 | BUG(); | |
2082 | ||
71ba2d64 YZ |
2083 | if (intel_vgpu_active(dev)) |
2084 | ppgtt->switch_mm = vgpu_mm_switch; | |
2085 | ||
b146520f BW |
2086 | ret = gen6_ppgtt_alloc(ppgtt); |
2087 | if (ret) | |
2088 | return ret; | |
2089 | ||
5c5f6457 | 2090 | ppgtt->base.allocate_va_range = gen6_alloc_va_range; |
b146520f BW |
2091 | ppgtt->base.clear_range = gen6_ppgtt_clear_range; |
2092 | ppgtt->base.insert_entries = gen6_ppgtt_insert_entries; | |
777dc5bb DV |
2093 | ppgtt->base.unbind_vma = ppgtt_unbind_vma; |
2094 | ppgtt->base.bind_vma = ppgtt_bind_vma; | |
b146520f | 2095 | ppgtt->base.cleanup = gen6_ppgtt_cleanup; |
b146520f | 2096 | ppgtt->base.start = 0; |
09942c65 | 2097 | ppgtt->base.total = I915_PDES * GEN6_PTES * PAGE_SIZE; |
87d60b63 | 2098 | ppgtt->debug_dump = gen6_dump_ppgtt; |
1d2a314c | 2099 | |
44159ddb | 2100 | ppgtt->pd.base.ggtt_offset = |
07749ef3 | 2101 | ppgtt->node.start / PAGE_SIZE * sizeof(gen6_pte_t); |
1d2a314c | 2102 | |
72e96d64 | 2103 | ppgtt->pd_addr = (gen6_pte_t __iomem *)ggtt->gsm + |
44159ddb | 2104 | ppgtt->pd.base.ggtt_offset / sizeof(gen6_pte_t); |
678d96fb | 2105 | |
5c5f6457 | 2106 | gen6_scratch_va_range(ppgtt, 0, ppgtt->base.total); |
1d2a314c | 2107 | |
678d96fb BW |
2108 | gen6_write_page_range(dev_priv, &ppgtt->pd, 0, ppgtt->base.total); |
2109 | ||
440fd528 | 2110 | DRM_DEBUG_DRIVER("Allocated pde space (%lldM) at GTT entry: %llx\n", |
b146520f BW |
2111 | ppgtt->node.size >> 20, |
2112 | ppgtt->node.start / PAGE_SIZE); | |
3440d265 | 2113 | |
fa76da34 | 2114 | DRM_DEBUG("Adding PPGTT at offset %x\n", |
44159ddb | 2115 | ppgtt->pd.base.ggtt_offset << 10); |
fa76da34 | 2116 | |
b146520f | 2117 | return 0; |
3440d265 DV |
2118 | } |
2119 | ||
5c5f6457 | 2120 | static int __hw_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt) |
3440d265 | 2121 | { |
853ba5d2 | 2122 | ppgtt->base.dev = dev; |
3440d265 | 2123 | |
3ed124b2 | 2124 | if (INTEL_INFO(dev)->gen < 8) |
5c5f6457 | 2125 | return gen6_ppgtt_init(ppgtt); |
3ed124b2 | 2126 | else |
d7b2633d | 2127 | return gen8_ppgtt_init(ppgtt); |
fa76da34 | 2128 | } |
c114f76a | 2129 | |
a2cad9df MW |
2130 | static void i915_address_space_init(struct i915_address_space *vm, |
2131 | struct drm_i915_private *dev_priv) | |
2132 | { | |
2133 | drm_mm_init(&vm->mm, vm->start, vm->total); | |
2134 | vm->dev = dev_priv->dev; | |
2135 | INIT_LIST_HEAD(&vm->active_list); | |
2136 | INIT_LIST_HEAD(&vm->inactive_list); | |
2137 | list_add_tail(&vm->global_link, &dev_priv->vm_list); | |
2138 | } | |
2139 | ||
d5165ebd TG |
2140 | static void gtt_write_workarounds(struct drm_device *dev) |
2141 | { | |
2142 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2143 | ||
2144 | /* This function is for gtt related workarounds. This function is | |
2145 | * called on driver load and after a GPU reset, so you can place | |
2146 | * workarounds here even if they get overwritten by GPU reset. | |
2147 | */ | |
2148 | /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt */ | |
2149 | if (IS_BROADWELL(dev)) | |
2150 | I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW); | |
2151 | else if (IS_CHERRYVIEW(dev)) | |
2152 | I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV); | |
2153 | else if (IS_SKYLAKE(dev)) | |
2154 | I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL); | |
2155 | else if (IS_BROXTON(dev)) | |
2156 | I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT); | |
2157 | } | |
2158 | ||
cba6dba4 | 2159 | static int i915_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt) |
fa76da34 DV |
2160 | { |
2161 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2162 | int ret = 0; | |
3ed124b2 | 2163 | |
5c5f6457 | 2164 | ret = __hw_ppgtt_init(dev, ppgtt); |
fa76da34 | 2165 | if (ret == 0) { |
c7c48dfd | 2166 | kref_init(&ppgtt->ref); |
a2cad9df | 2167 | i915_address_space_init(&ppgtt->base, dev_priv); |
93bd8649 | 2168 | } |
1d2a314c DV |
2169 | |
2170 | return ret; | |
2171 | } | |
2172 | ||
82460d97 DV |
2173 | int i915_ppgtt_init_hw(struct drm_device *dev) |
2174 | { | |
d5165ebd TG |
2175 | gtt_write_workarounds(dev); |
2176 | ||
671b5013 TD |
2177 | /* In the case of execlists, PPGTT is enabled by the context descriptor |
2178 | * and the PDPs are contained within the context itself. We don't | |
2179 | * need to do anything here. */ | |
2180 | if (i915.enable_execlists) | |
2181 | return 0; | |
2182 | ||
82460d97 DV |
2183 | if (!USES_PPGTT(dev)) |
2184 | return 0; | |
2185 | ||
2186 | if (IS_GEN6(dev)) | |
2187 | gen6_ppgtt_enable(dev); | |
2188 | else if (IS_GEN7(dev)) | |
2189 | gen7_ppgtt_enable(dev); | |
2190 | else if (INTEL_INFO(dev)->gen >= 8) | |
2191 | gen8_ppgtt_enable(dev); | |
2192 | else | |
5f77eeb0 | 2193 | MISSING_CASE(INTEL_INFO(dev)->gen); |
82460d97 | 2194 | |
4ad2fd88 JH |
2195 | return 0; |
2196 | } | |
1d2a314c | 2197 | |
4d884705 DV |
2198 | struct i915_hw_ppgtt * |
2199 | i915_ppgtt_create(struct drm_device *dev, struct drm_i915_file_private *fpriv) | |
2200 | { | |
2201 | struct i915_hw_ppgtt *ppgtt; | |
2202 | int ret; | |
2203 | ||
2204 | ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL); | |
2205 | if (!ppgtt) | |
2206 | return ERR_PTR(-ENOMEM); | |
2207 | ||
2208 | ret = i915_ppgtt_init(dev, ppgtt); | |
2209 | if (ret) { | |
2210 | kfree(ppgtt); | |
2211 | return ERR_PTR(ret); | |
2212 | } | |
2213 | ||
2214 | ppgtt->file_priv = fpriv; | |
2215 | ||
198c974d DCS |
2216 | trace_i915_ppgtt_create(&ppgtt->base); |
2217 | ||
4d884705 DV |
2218 | return ppgtt; |
2219 | } | |
2220 | ||
ee960be7 DV |
2221 | void i915_ppgtt_release(struct kref *kref) |
2222 | { | |
2223 | struct i915_hw_ppgtt *ppgtt = | |
2224 | container_of(kref, struct i915_hw_ppgtt, ref); | |
2225 | ||
198c974d DCS |
2226 | trace_i915_ppgtt_release(&ppgtt->base); |
2227 | ||
ee960be7 DV |
2228 | /* vmas should already be unbound */ |
2229 | WARN_ON(!list_empty(&ppgtt->base.active_list)); | |
2230 | WARN_ON(!list_empty(&ppgtt->base.inactive_list)); | |
2231 | ||
19dd120c DV |
2232 | list_del(&ppgtt->base.global_link); |
2233 | drm_mm_takedown(&ppgtt->base.mm); | |
2234 | ||
ee960be7 DV |
2235 | ppgtt->base.cleanup(&ppgtt->base); |
2236 | kfree(ppgtt); | |
2237 | } | |
1d2a314c | 2238 | |
a81cc00c BW |
2239 | extern int intel_iommu_gfx_mapped; |
2240 | /* Certain Gen5 chipsets require require idling the GPU before | |
2241 | * unmapping anything from the GTT when VT-d is enabled. | |
2242 | */ | |
2c642b07 | 2243 | static bool needs_idle_maps(struct drm_device *dev) |
a81cc00c BW |
2244 | { |
2245 | #ifdef CONFIG_INTEL_IOMMU | |
2246 | /* Query intel_iommu to see if we need the workaround. Presumably that | |
2247 | * was loaded first. | |
2248 | */ | |
2249 | if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped) | |
2250 | return true; | |
2251 | #endif | |
2252 | return false; | |
2253 | } | |
2254 | ||
5c042287 BW |
2255 | static bool do_idling(struct drm_i915_private *dev_priv) |
2256 | { | |
72e96d64 | 2257 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
5c042287 BW |
2258 | bool ret = dev_priv->mm.interruptible; |
2259 | ||
72e96d64 | 2260 | if (unlikely(ggtt->do_idle_maps)) { |
5c042287 | 2261 | dev_priv->mm.interruptible = false; |
b2da9fe5 | 2262 | if (i915_gpu_idle(dev_priv->dev)) { |
5c042287 BW |
2263 | DRM_ERROR("Couldn't idle GPU\n"); |
2264 | /* Wait a bit, in hopes it avoids the hang */ | |
2265 | udelay(10); | |
2266 | } | |
2267 | } | |
2268 | ||
2269 | return ret; | |
2270 | } | |
2271 | ||
2272 | static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible) | |
2273 | { | |
72e96d64 JL |
2274 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
2275 | ||
2276 | if (unlikely(ggtt->do_idle_maps)) | |
5c042287 BW |
2277 | dev_priv->mm.interruptible = interruptible; |
2278 | } | |
2279 | ||
828c7908 BW |
2280 | void i915_check_and_clear_faults(struct drm_device *dev) |
2281 | { | |
2282 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2f80391 | 2283 | struct intel_engine_cs *engine; |
828c7908 BW |
2284 | |
2285 | if (INTEL_INFO(dev)->gen < 6) | |
2286 | return; | |
2287 | ||
b4ac5afc | 2288 | for_each_engine(engine, dev_priv) { |
828c7908 | 2289 | u32 fault_reg; |
e2f80391 | 2290 | fault_reg = I915_READ(RING_FAULT_REG(engine)); |
828c7908 BW |
2291 | if (fault_reg & RING_FAULT_VALID) { |
2292 | DRM_DEBUG_DRIVER("Unexpected fault\n" | |
59a5d290 | 2293 | "\tAddr: 0x%08lx\n" |
828c7908 BW |
2294 | "\tAddress space: %s\n" |
2295 | "\tSource ID: %d\n" | |
2296 | "\tType: %d\n", | |
2297 | fault_reg & PAGE_MASK, | |
2298 | fault_reg & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT", | |
2299 | RING_FAULT_SRCID(fault_reg), | |
2300 | RING_FAULT_FAULT_TYPE(fault_reg)); | |
e2f80391 | 2301 | I915_WRITE(RING_FAULT_REG(engine), |
828c7908 BW |
2302 | fault_reg & ~RING_FAULT_VALID); |
2303 | } | |
2304 | } | |
4a570db5 | 2305 | POSTING_READ(RING_FAULT_REG(&dev_priv->engine[RCS])); |
828c7908 BW |
2306 | } |
2307 | ||
91e56499 CW |
2308 | static void i915_ggtt_flush(struct drm_i915_private *dev_priv) |
2309 | { | |
2d1fe073 | 2310 | if (INTEL_INFO(dev_priv)->gen < 6) { |
91e56499 CW |
2311 | intel_gtt_chipset_flush(); |
2312 | } else { | |
2313 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
2314 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
2315 | } | |
2316 | } | |
2317 | ||
828c7908 BW |
2318 | void i915_gem_suspend_gtt_mappings(struct drm_device *dev) |
2319 | { | |
72e96d64 JL |
2320 | struct drm_i915_private *dev_priv = to_i915(dev); |
2321 | struct i915_ggtt *ggtt = &dev_priv->ggtt; | |
828c7908 BW |
2322 | |
2323 | /* Don't bother messing with faults pre GEN6 as we have little | |
2324 | * documentation supporting that it's a good idea. | |
2325 | */ | |
2326 | if (INTEL_INFO(dev)->gen < 6) | |
2327 | return; | |
2328 | ||
2329 | i915_check_and_clear_faults(dev); | |
2330 | ||
72e96d64 JL |
2331 | ggtt->base.clear_range(&ggtt->base, ggtt->base.start, ggtt->base.total, |
2332 | true); | |
91e56499 CW |
2333 | |
2334 | i915_ggtt_flush(dev_priv); | |
828c7908 BW |
2335 | } |
2336 | ||
74163907 | 2337 | int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj) |
7c2e6fdf | 2338 | { |
9da3da66 CW |
2339 | if (!dma_map_sg(&obj->base.dev->pdev->dev, |
2340 | obj->pages->sgl, obj->pages->nents, | |
2341 | PCI_DMA_BIDIRECTIONAL)) | |
2342 | return -ENOSPC; | |
2343 | ||
2344 | return 0; | |
7c2e6fdf DV |
2345 | } |
2346 | ||
2c642b07 | 2347 | static void gen8_set_pte(void __iomem *addr, gen8_pte_t pte) |
94ec8f61 BW |
2348 | { |
2349 | #ifdef writeq | |
2350 | writeq(pte, addr); | |
2351 | #else | |
2352 | iowrite32((u32)pte, addr); | |
2353 | iowrite32(pte >> 32, addr + 4); | |
2354 | #endif | |
2355 | } | |
2356 | ||
2357 | static void gen8_ggtt_insert_entries(struct i915_address_space *vm, | |
2358 | struct sg_table *st, | |
782f1495 | 2359 | uint64_t start, |
24f3a8cf | 2360 | enum i915_cache_level level, u32 unused) |
94ec8f61 | 2361 | { |
72e96d64 | 2362 | struct drm_i915_private *dev_priv = to_i915(vm->dev); |
ce7fda2e | 2363 | struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm); |
782f1495 | 2364 | unsigned first_entry = start >> PAGE_SHIFT; |
07749ef3 | 2365 | gen8_pte_t __iomem *gtt_entries = |
72e96d64 | 2366 | (gen8_pte_t __iomem *)ggtt->gsm + first_entry; |
94ec8f61 BW |
2367 | int i = 0; |
2368 | struct sg_page_iter sg_iter; | |
57007df7 | 2369 | dma_addr_t addr = 0; /* shut up gcc */ |
be69459a ID |
2370 | int rpm_atomic_seq; |
2371 | ||
2372 | rpm_atomic_seq = assert_rpm_atomic_begin(dev_priv); | |
94ec8f61 BW |
2373 | |
2374 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) { | |
2375 | addr = sg_dma_address(sg_iter.sg) + | |
2376 | (sg_iter.sg_pgoffset << PAGE_SHIFT); | |
2377 | gen8_set_pte(>t_entries[i], | |
2378 | gen8_pte_encode(addr, level, true)); | |
2379 | i++; | |
2380 | } | |
2381 | ||
2382 | /* | |
2383 | * XXX: This serves as a posting read to make sure that the PTE has | |
2384 | * actually been updated. There is some concern that even though | |
2385 | * registers and PTEs are within the same BAR that they are potentially | |
2386 | * of NUMA access patterns. Therefore, even with the way we assume | |
2387 | * hardware should work, we must keep this posting read for paranoia. | |
2388 | */ | |
2389 | if (i != 0) | |
2390 | WARN_ON(readq(>t_entries[i-1]) | |
2391 | != gen8_pte_encode(addr, level, true)); | |
2392 | ||
94ec8f61 BW |
2393 | /* This next bit makes the above posting read even more important. We |
2394 | * want to flush the TLBs only after we're certain all the PTE updates | |
2395 | * have finished. | |
2396 | */ | |
2397 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
2398 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
be69459a ID |
2399 | |
2400 | assert_rpm_atomic_end(dev_priv, rpm_atomic_seq); | |
94ec8f61 BW |
2401 | } |
2402 | ||
c140330b CW |
2403 | struct insert_entries { |
2404 | struct i915_address_space *vm; | |
2405 | struct sg_table *st; | |
2406 | uint64_t start; | |
2407 | enum i915_cache_level level; | |
2408 | u32 flags; | |
2409 | }; | |
2410 | ||
2411 | static int gen8_ggtt_insert_entries__cb(void *_arg) | |
2412 | { | |
2413 | struct insert_entries *arg = _arg; | |
2414 | gen8_ggtt_insert_entries(arg->vm, arg->st, | |
2415 | arg->start, arg->level, arg->flags); | |
2416 | return 0; | |
2417 | } | |
2418 | ||
2419 | static void gen8_ggtt_insert_entries__BKL(struct i915_address_space *vm, | |
2420 | struct sg_table *st, | |
2421 | uint64_t start, | |
2422 | enum i915_cache_level level, | |
2423 | u32 flags) | |
2424 | { | |
2425 | struct insert_entries arg = { vm, st, start, level, flags }; | |
2426 | stop_machine(gen8_ggtt_insert_entries__cb, &arg, NULL); | |
2427 | } | |
2428 | ||
e76e9aeb BW |
2429 | /* |
2430 | * Binds an object into the global gtt with the specified cache level. The object | |
2431 | * will be accessible to the GPU via commands whose operands reference offsets | |
2432 | * within the global GTT as well as accessible by the GPU through the GMADR | |
2433 | * mapped BAR (dev_priv->mm.gtt->gtt). | |
2434 | */ | |
853ba5d2 | 2435 | static void gen6_ggtt_insert_entries(struct i915_address_space *vm, |
7faf1ab2 | 2436 | struct sg_table *st, |
782f1495 | 2437 | uint64_t start, |
24f3a8cf | 2438 | enum i915_cache_level level, u32 flags) |
e76e9aeb | 2439 | { |
72e96d64 | 2440 | struct drm_i915_private *dev_priv = to_i915(vm->dev); |
ce7fda2e | 2441 | struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm); |
782f1495 | 2442 | unsigned first_entry = start >> PAGE_SHIFT; |
07749ef3 | 2443 | gen6_pte_t __iomem *gtt_entries = |
72e96d64 | 2444 | (gen6_pte_t __iomem *)ggtt->gsm + first_entry; |
6e995e23 ID |
2445 | int i = 0; |
2446 | struct sg_page_iter sg_iter; | |
57007df7 | 2447 | dma_addr_t addr = 0; |
be69459a ID |
2448 | int rpm_atomic_seq; |
2449 | ||
2450 | rpm_atomic_seq = assert_rpm_atomic_begin(dev_priv); | |
e76e9aeb | 2451 | |
6e995e23 | 2452 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) { |
2db76d7c | 2453 | addr = sg_page_iter_dma_address(&sg_iter); |
24f3a8cf | 2454 | iowrite32(vm->pte_encode(addr, level, true, flags), >t_entries[i]); |
6e995e23 | 2455 | i++; |
e76e9aeb BW |
2456 | } |
2457 | ||
e76e9aeb BW |
2458 | /* XXX: This serves as a posting read to make sure that the PTE has |
2459 | * actually been updated. There is some concern that even though | |
2460 | * registers and PTEs are within the same BAR that they are potentially | |
2461 | * of NUMA access patterns. Therefore, even with the way we assume | |
2462 | * hardware should work, we must keep this posting read for paranoia. | |
2463 | */ | |
57007df7 PM |
2464 | if (i != 0) { |
2465 | unsigned long gtt = readl(>t_entries[i-1]); | |
2466 | WARN_ON(gtt != vm->pte_encode(addr, level, true, flags)); | |
2467 | } | |
0f9b91c7 BW |
2468 | |
2469 | /* This next bit makes the above posting read even more important. We | |
2470 | * want to flush the TLBs only after we're certain all the PTE updates | |
2471 | * have finished. | |
2472 | */ | |
2473 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
2474 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
be69459a ID |
2475 | |
2476 | assert_rpm_atomic_end(dev_priv, rpm_atomic_seq); | |
e76e9aeb BW |
2477 | } |
2478 | ||
94ec8f61 | 2479 | static void gen8_ggtt_clear_range(struct i915_address_space *vm, |
782f1495 BW |
2480 | uint64_t start, |
2481 | uint64_t length, | |
94ec8f61 BW |
2482 | bool use_scratch) |
2483 | { | |
72e96d64 | 2484 | struct drm_i915_private *dev_priv = to_i915(vm->dev); |
ce7fda2e | 2485 | struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm); |
782f1495 BW |
2486 | unsigned first_entry = start >> PAGE_SHIFT; |
2487 | unsigned num_entries = length >> PAGE_SHIFT; | |
07749ef3 | 2488 | gen8_pte_t scratch_pte, __iomem *gtt_base = |
72e96d64 JL |
2489 | (gen8_pte_t __iomem *)ggtt->gsm + first_entry; |
2490 | const int max_entries = ggtt_total_entries(ggtt) - first_entry; | |
94ec8f61 | 2491 | int i; |
be69459a ID |
2492 | int rpm_atomic_seq; |
2493 | ||
2494 | rpm_atomic_seq = assert_rpm_atomic_begin(dev_priv); | |
94ec8f61 BW |
2495 | |
2496 | if (WARN(num_entries > max_entries, | |
2497 | "First entry = %d; Num entries = %d (max=%d)\n", | |
2498 | first_entry, num_entries, max_entries)) | |
2499 | num_entries = max_entries; | |
2500 | ||
c114f76a | 2501 | scratch_pte = gen8_pte_encode(px_dma(vm->scratch_page), |
94ec8f61 BW |
2502 | I915_CACHE_LLC, |
2503 | use_scratch); | |
2504 | for (i = 0; i < num_entries; i++) | |
2505 | gen8_set_pte(>t_base[i], scratch_pte); | |
2506 | readl(gtt_base); | |
be69459a ID |
2507 | |
2508 | assert_rpm_atomic_end(dev_priv, rpm_atomic_seq); | |
94ec8f61 BW |
2509 | } |
2510 | ||
853ba5d2 | 2511 | static void gen6_ggtt_clear_range(struct i915_address_space *vm, |
782f1495 BW |
2512 | uint64_t start, |
2513 | uint64_t length, | |
828c7908 | 2514 | bool use_scratch) |
7faf1ab2 | 2515 | { |
72e96d64 | 2516 | struct drm_i915_private *dev_priv = to_i915(vm->dev); |
ce7fda2e | 2517 | struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm); |
782f1495 BW |
2518 | unsigned first_entry = start >> PAGE_SHIFT; |
2519 | unsigned num_entries = length >> PAGE_SHIFT; | |
07749ef3 | 2520 | gen6_pte_t scratch_pte, __iomem *gtt_base = |
72e96d64 JL |
2521 | (gen6_pte_t __iomem *)ggtt->gsm + first_entry; |
2522 | const int max_entries = ggtt_total_entries(ggtt) - first_entry; | |
7faf1ab2 | 2523 | int i; |
be69459a ID |
2524 | int rpm_atomic_seq; |
2525 | ||
2526 | rpm_atomic_seq = assert_rpm_atomic_begin(dev_priv); | |
7faf1ab2 DV |
2527 | |
2528 | if (WARN(num_entries > max_entries, | |
2529 | "First entry = %d; Num entries = %d (max=%d)\n", | |
2530 | first_entry, num_entries, max_entries)) | |
2531 | num_entries = max_entries; | |
2532 | ||
c114f76a MK |
2533 | scratch_pte = vm->pte_encode(px_dma(vm->scratch_page), |
2534 | I915_CACHE_LLC, use_scratch, 0); | |
828c7908 | 2535 | |
7faf1ab2 DV |
2536 | for (i = 0; i < num_entries; i++) |
2537 | iowrite32(scratch_pte, >t_base[i]); | |
2538 | readl(gtt_base); | |
be69459a ID |
2539 | |
2540 | assert_rpm_atomic_end(dev_priv, rpm_atomic_seq); | |
7faf1ab2 DV |
2541 | } |
2542 | ||
d369d2d9 DV |
2543 | static void i915_ggtt_insert_entries(struct i915_address_space *vm, |
2544 | struct sg_table *pages, | |
2545 | uint64_t start, | |
2546 | enum i915_cache_level cache_level, u32 unused) | |
7faf1ab2 | 2547 | { |
be69459a | 2548 | struct drm_i915_private *dev_priv = vm->dev->dev_private; |
7faf1ab2 DV |
2549 | unsigned int flags = (cache_level == I915_CACHE_NONE) ? |
2550 | AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY; | |
be69459a ID |
2551 | int rpm_atomic_seq; |
2552 | ||
2553 | rpm_atomic_seq = assert_rpm_atomic_begin(dev_priv); | |
7faf1ab2 | 2554 | |
d369d2d9 | 2555 | intel_gtt_insert_sg_entries(pages, start >> PAGE_SHIFT, flags); |
0875546c | 2556 | |
be69459a ID |
2557 | assert_rpm_atomic_end(dev_priv, rpm_atomic_seq); |
2558 | ||
7faf1ab2 DV |
2559 | } |
2560 | ||
853ba5d2 | 2561 | static void i915_ggtt_clear_range(struct i915_address_space *vm, |
782f1495 BW |
2562 | uint64_t start, |
2563 | uint64_t length, | |
828c7908 | 2564 | bool unused) |
7faf1ab2 | 2565 | { |
be69459a | 2566 | struct drm_i915_private *dev_priv = vm->dev->dev_private; |
782f1495 BW |
2567 | unsigned first_entry = start >> PAGE_SHIFT; |
2568 | unsigned num_entries = length >> PAGE_SHIFT; | |
be69459a ID |
2569 | int rpm_atomic_seq; |
2570 | ||
2571 | rpm_atomic_seq = assert_rpm_atomic_begin(dev_priv); | |
2572 | ||
7faf1ab2 | 2573 | intel_gtt_clear_range(first_entry, num_entries); |
be69459a ID |
2574 | |
2575 | assert_rpm_atomic_end(dev_priv, rpm_atomic_seq); | |
7faf1ab2 DV |
2576 | } |
2577 | ||
70b9f6f8 DV |
2578 | static int ggtt_bind_vma(struct i915_vma *vma, |
2579 | enum i915_cache_level cache_level, | |
2580 | u32 flags) | |
0a878716 DV |
2581 | { |
2582 | struct drm_i915_gem_object *obj = vma->obj; | |
2583 | u32 pte_flags = 0; | |
2584 | int ret; | |
2585 | ||
2586 | ret = i915_get_ggtt_vma_pages(vma); | |
2587 | if (ret) | |
2588 | return ret; | |
2589 | ||
2590 | /* Currently applicable only to VLV */ | |
2591 | if (obj->gt_ro) | |
2592 | pte_flags |= PTE_READ_ONLY; | |
2593 | ||
2594 | vma->vm->insert_entries(vma->vm, vma->ggtt_view.pages, | |
2595 | vma->node.start, | |
2596 | cache_level, pte_flags); | |
2597 | ||
2598 | /* | |
2599 | * Without aliasing PPGTT there's no difference between | |
2600 | * GLOBAL/LOCAL_BIND, it's all the same ptes. Hence unconditionally | |
2601 | * upgrade to both bound if we bind either to avoid double-binding. | |
2602 | */ | |
2603 | vma->bound |= GLOBAL_BIND | LOCAL_BIND; | |
2604 | ||
2605 | return 0; | |
2606 | } | |
2607 | ||
2608 | static int aliasing_gtt_bind_vma(struct i915_vma *vma, | |
2609 | enum i915_cache_level cache_level, | |
2610 | u32 flags) | |
d5bd1449 | 2611 | { |
321d178e | 2612 | u32 pte_flags; |
70b9f6f8 DV |
2613 | int ret; |
2614 | ||
2615 | ret = i915_get_ggtt_vma_pages(vma); | |
2616 | if (ret) | |
2617 | return ret; | |
7faf1ab2 | 2618 | |
24f3a8cf | 2619 | /* Currently applicable only to VLV */ |
321d178e CW |
2620 | pte_flags = 0; |
2621 | if (vma->obj->gt_ro) | |
f329f5f6 | 2622 | pte_flags |= PTE_READ_ONLY; |
24f3a8cf | 2623 | |
ec7adb6e | 2624 | |
0a878716 | 2625 | if (flags & GLOBAL_BIND) { |
321d178e CW |
2626 | vma->vm->insert_entries(vma->vm, |
2627 | vma->ggtt_view.pages, | |
0875546c DV |
2628 | vma->node.start, |
2629 | cache_level, pte_flags); | |
6f65e29a | 2630 | } |
d5bd1449 | 2631 | |
0a878716 | 2632 | if (flags & LOCAL_BIND) { |
321d178e CW |
2633 | struct i915_hw_ppgtt *appgtt = |
2634 | to_i915(vma->vm->dev)->mm.aliasing_ppgtt; | |
2635 | appgtt->base.insert_entries(&appgtt->base, | |
2636 | vma->ggtt_view.pages, | |
782f1495 | 2637 | vma->node.start, |
f329f5f6 | 2638 | cache_level, pte_flags); |
6f65e29a | 2639 | } |
70b9f6f8 DV |
2640 | |
2641 | return 0; | |
d5bd1449 CW |
2642 | } |
2643 | ||
6f65e29a | 2644 | static void ggtt_unbind_vma(struct i915_vma *vma) |
74163907 | 2645 | { |
6f65e29a | 2646 | struct drm_device *dev = vma->vm->dev; |
7faf1ab2 | 2647 | struct drm_i915_private *dev_priv = dev->dev_private; |
6f65e29a | 2648 | struct drm_i915_gem_object *obj = vma->obj; |
06615ee5 JL |
2649 | const uint64_t size = min_t(uint64_t, |
2650 | obj->base.size, | |
2651 | vma->node.size); | |
6f65e29a | 2652 | |
aff43766 | 2653 | if (vma->bound & GLOBAL_BIND) { |
782f1495 BW |
2654 | vma->vm->clear_range(vma->vm, |
2655 | vma->node.start, | |
06615ee5 | 2656 | size, |
6f65e29a | 2657 | true); |
6f65e29a | 2658 | } |
74898d7e | 2659 | |
0875546c | 2660 | if (dev_priv->mm.aliasing_ppgtt && vma->bound & LOCAL_BIND) { |
6f65e29a | 2661 | struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt; |
06615ee5 | 2662 | |
6f65e29a | 2663 | appgtt->base.clear_range(&appgtt->base, |
782f1495 | 2664 | vma->node.start, |
06615ee5 | 2665 | size, |
6f65e29a | 2666 | true); |
6f65e29a | 2667 | } |
74163907 DV |
2668 | } |
2669 | ||
2670 | void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj) | |
7c2e6fdf | 2671 | { |
5c042287 BW |
2672 | struct drm_device *dev = obj->base.dev; |
2673 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2674 | bool interruptible; | |
2675 | ||
2676 | interruptible = do_idling(dev_priv); | |
2677 | ||
5ec5b516 ID |
2678 | dma_unmap_sg(&dev->pdev->dev, obj->pages->sgl, obj->pages->nents, |
2679 | PCI_DMA_BIDIRECTIONAL); | |
5c042287 BW |
2680 | |
2681 | undo_idling(dev_priv, interruptible); | |
7c2e6fdf | 2682 | } |
644ec02b | 2683 | |
42d6ab48 CW |
2684 | static void i915_gtt_color_adjust(struct drm_mm_node *node, |
2685 | unsigned long color, | |
440fd528 TR |
2686 | u64 *start, |
2687 | u64 *end) | |
42d6ab48 CW |
2688 | { |
2689 | if (node->color != color) | |
2690 | *start += 4096; | |
2691 | ||
2692 | if (!list_empty(&node->node_list)) { | |
2693 | node = list_entry(node->node_list.next, | |
2694 | struct drm_mm_node, | |
2695 | node_list); | |
2696 | if (node->allocated && node->color != color) | |
2697 | *end -= 4096; | |
2698 | } | |
2699 | } | |
fbe5d36e | 2700 | |
f548c0e9 | 2701 | static int i915_gem_setup_global_gtt(struct drm_device *dev, |
088e0df4 MT |
2702 | u64 start, |
2703 | u64 mappable_end, | |
2704 | u64 end) | |
644ec02b | 2705 | { |
e78891ca BW |
2706 | /* Let GEM Manage all of the aperture. |
2707 | * | |
2708 | * However, leave one page at the end still bound to the scratch page. | |
2709 | * There are a number of places where the hardware apparently prefetches | |
2710 | * past the end of the object, and we've seen multiple hangs with the | |
2711 | * GPU head pointer stuck in a batchbuffer bound at the last page of the | |
2712 | * aperture. One page should be enough to keep any prefetching inside | |
2713 | * of the aperture. | |
2714 | */ | |
72e96d64 JL |
2715 | struct drm_i915_private *dev_priv = to_i915(dev); |
2716 | struct i915_ggtt *ggtt = &dev_priv->ggtt; | |
ed2f3452 CW |
2717 | struct drm_mm_node *entry; |
2718 | struct drm_i915_gem_object *obj; | |
2719 | unsigned long hole_start, hole_end; | |
fa76da34 | 2720 | int ret; |
644ec02b | 2721 | |
35451cb6 BW |
2722 | BUG_ON(mappable_end > end); |
2723 | ||
72e96d64 | 2724 | ggtt->base.start = start; |
5dda8fa3 | 2725 | |
a2cad9df MW |
2726 | /* Subtract the guard page before address space initialization to |
2727 | * shrink the range used by drm_mm */ | |
72e96d64 JL |
2728 | ggtt->base.total = end - start - PAGE_SIZE; |
2729 | i915_address_space_init(&ggtt->base, dev_priv); | |
2730 | ggtt->base.total += PAGE_SIZE; | |
5dda8fa3 YZ |
2731 | |
2732 | if (intel_vgpu_active(dev)) { | |
2733 | ret = intel_vgt_balloon(dev); | |
2734 | if (ret) | |
2735 | return ret; | |
2736 | } | |
2737 | ||
42d6ab48 | 2738 | if (!HAS_LLC(dev)) |
72e96d64 | 2739 | ggtt->base.mm.color_adjust = i915_gtt_color_adjust; |
644ec02b | 2740 | |
ed2f3452 | 2741 | /* Mark any preallocated objects as occupied */ |
35c20a60 | 2742 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
72e96d64 | 2743 | struct i915_vma *vma = i915_gem_obj_to_vma(obj, &ggtt->base); |
fa76da34 | 2744 | |
088e0df4 | 2745 | DRM_DEBUG_KMS("reserving preallocated space: %llx + %zx\n", |
c6cfb325 BW |
2746 | i915_gem_obj_ggtt_offset(obj), obj->base.size); |
2747 | ||
2748 | WARN_ON(i915_gem_obj_ggtt_bound(obj)); | |
72e96d64 | 2749 | ret = drm_mm_reserve_node(&ggtt->base.mm, &vma->node); |
6c5566a8 DV |
2750 | if (ret) { |
2751 | DRM_DEBUG_KMS("Reservation failed: %i\n", ret); | |
2752 | return ret; | |
2753 | } | |
aff43766 | 2754 | vma->bound |= GLOBAL_BIND; |
d0710abb | 2755 | __i915_vma_set_map_and_fenceable(vma); |
72e96d64 | 2756 | list_add_tail(&vma->vm_link, &ggtt->base.inactive_list); |
ed2f3452 CW |
2757 | } |
2758 | ||
ed2f3452 | 2759 | /* Clear any non-preallocated blocks */ |
72e96d64 | 2760 | drm_mm_for_each_hole(entry, &ggtt->base.mm, hole_start, hole_end) { |
ed2f3452 CW |
2761 | DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n", |
2762 | hole_start, hole_end); | |
72e96d64 | 2763 | ggtt->base.clear_range(&ggtt->base, hole_start, |
782f1495 | 2764 | hole_end - hole_start, true); |
ed2f3452 CW |
2765 | } |
2766 | ||
2767 | /* And finally clear the reserved guard page */ | |
72e96d64 | 2768 | ggtt->base.clear_range(&ggtt->base, end - PAGE_SIZE, PAGE_SIZE, true); |
6c5566a8 | 2769 | |
fa76da34 DV |
2770 | if (USES_PPGTT(dev) && !USES_FULL_PPGTT(dev)) { |
2771 | struct i915_hw_ppgtt *ppgtt; | |
2772 | ||
2773 | ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL); | |
2774 | if (!ppgtt) | |
2775 | return -ENOMEM; | |
2776 | ||
5c5f6457 DV |
2777 | ret = __hw_ppgtt_init(dev, ppgtt); |
2778 | if (ret) { | |
2779 | ppgtt->base.cleanup(&ppgtt->base); | |
2780 | kfree(ppgtt); | |
2781 | return ret; | |
2782 | } | |
2783 | ||
2784 | if (ppgtt->base.allocate_va_range) | |
2785 | ret = ppgtt->base.allocate_va_range(&ppgtt->base, 0, | |
2786 | ppgtt->base.total); | |
4933d519 | 2787 | if (ret) { |
061dd493 | 2788 | ppgtt->base.cleanup(&ppgtt->base); |
4933d519 | 2789 | kfree(ppgtt); |
fa76da34 | 2790 | return ret; |
4933d519 | 2791 | } |
fa76da34 | 2792 | |
5c5f6457 DV |
2793 | ppgtt->base.clear_range(&ppgtt->base, |
2794 | ppgtt->base.start, | |
2795 | ppgtt->base.total, | |
2796 | true); | |
2797 | ||
fa76da34 | 2798 | dev_priv->mm.aliasing_ppgtt = ppgtt; |
72e96d64 JL |
2799 | WARN_ON(ggtt->base.bind_vma != ggtt_bind_vma); |
2800 | ggtt->base.bind_vma = aliasing_gtt_bind_vma; | |
fa76da34 DV |
2801 | } |
2802 | ||
6c5566a8 | 2803 | return 0; |
e76e9aeb BW |
2804 | } |
2805 | ||
d85489d3 JL |
2806 | /** |
2807 | * i915_gem_init_ggtt - Initialize GEM for Global GTT | |
2808 | * @dev: DRM device | |
2809 | */ | |
2810 | void i915_gem_init_ggtt(struct drm_device *dev) | |
d7e5008f | 2811 | { |
72e96d64 JL |
2812 | struct drm_i915_private *dev_priv = to_i915(dev); |
2813 | struct i915_ggtt *ggtt = &dev_priv->ggtt; | |
d7e5008f | 2814 | |
72e96d64 | 2815 | i915_gem_setup_global_gtt(dev, 0, ggtt->mappable_end, ggtt->base.total); |
e76e9aeb BW |
2816 | } |
2817 | ||
d85489d3 JL |
2818 | /** |
2819 | * i915_ggtt_cleanup_hw - Clean up GGTT hardware initialization | |
2820 | * @dev: DRM device | |
2821 | */ | |
2822 | void i915_ggtt_cleanup_hw(struct drm_device *dev) | |
90d0a0e8 | 2823 | { |
72e96d64 JL |
2824 | struct drm_i915_private *dev_priv = to_i915(dev); |
2825 | struct i915_ggtt *ggtt = &dev_priv->ggtt; | |
90d0a0e8 | 2826 | |
70e32544 DV |
2827 | if (dev_priv->mm.aliasing_ppgtt) { |
2828 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
2829 | ||
2830 | ppgtt->base.cleanup(&ppgtt->base); | |
2831 | } | |
2832 | ||
a4eba47b ID |
2833 | i915_gem_cleanup_stolen(dev); |
2834 | ||
72e96d64 | 2835 | if (drm_mm_initialized(&ggtt->base.mm)) { |
5dda8fa3 YZ |
2836 | if (intel_vgpu_active(dev)) |
2837 | intel_vgt_deballoon(); | |
2838 | ||
72e96d64 JL |
2839 | drm_mm_takedown(&ggtt->base.mm); |
2840 | list_del(&ggtt->base.global_link); | |
90d0a0e8 DV |
2841 | } |
2842 | ||
72e96d64 | 2843 | ggtt->base.cleanup(&ggtt->base); |
90d0a0e8 | 2844 | } |
70e32544 | 2845 | |
2c642b07 | 2846 | static unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl) |
e76e9aeb BW |
2847 | { |
2848 | snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT; | |
2849 | snb_gmch_ctl &= SNB_GMCH_GGMS_MASK; | |
2850 | return snb_gmch_ctl << 20; | |
2851 | } | |
2852 | ||
2c642b07 | 2853 | static unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl) |
9459d252 BW |
2854 | { |
2855 | bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT; | |
2856 | bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK; | |
2857 | if (bdw_gmch_ctl) | |
2858 | bdw_gmch_ctl = 1 << bdw_gmch_ctl; | |
562d55d9 BW |
2859 | |
2860 | #ifdef CONFIG_X86_32 | |
2861 | /* Limit 32b platforms to a 2GB GGTT: 4 << 20 / pte size * PAGE_SIZE */ | |
2862 | if (bdw_gmch_ctl > 4) | |
2863 | bdw_gmch_ctl = 4; | |
2864 | #endif | |
2865 | ||
9459d252 BW |
2866 | return bdw_gmch_ctl << 20; |
2867 | } | |
2868 | ||
2c642b07 | 2869 | static unsigned int chv_get_total_gtt_size(u16 gmch_ctrl) |
d7f25f23 DL |
2870 | { |
2871 | gmch_ctrl >>= SNB_GMCH_GGMS_SHIFT; | |
2872 | gmch_ctrl &= SNB_GMCH_GGMS_MASK; | |
2873 | ||
2874 | if (gmch_ctrl) | |
2875 | return 1 << (20 + gmch_ctrl); | |
2876 | ||
2877 | return 0; | |
2878 | } | |
2879 | ||
2c642b07 | 2880 | static size_t gen6_get_stolen_size(u16 snb_gmch_ctl) |
e76e9aeb BW |
2881 | { |
2882 | snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT; | |
2883 | snb_gmch_ctl &= SNB_GMCH_GMS_MASK; | |
2884 | return snb_gmch_ctl << 25; /* 32 MB units */ | |
2885 | } | |
2886 | ||
2c642b07 | 2887 | static size_t gen8_get_stolen_size(u16 bdw_gmch_ctl) |
9459d252 BW |
2888 | { |
2889 | bdw_gmch_ctl >>= BDW_GMCH_GMS_SHIFT; | |
2890 | bdw_gmch_ctl &= BDW_GMCH_GMS_MASK; | |
2891 | return bdw_gmch_ctl << 25; /* 32 MB units */ | |
2892 | } | |
2893 | ||
d7f25f23 DL |
2894 | static size_t chv_get_stolen_size(u16 gmch_ctrl) |
2895 | { | |
2896 | gmch_ctrl >>= SNB_GMCH_GMS_SHIFT; | |
2897 | gmch_ctrl &= SNB_GMCH_GMS_MASK; | |
2898 | ||
2899 | /* | |
2900 | * 0x0 to 0x10: 32MB increments starting at 0MB | |
2901 | * 0x11 to 0x16: 4MB increments starting at 8MB | |
2902 | * 0x17 to 0x1d: 4MB increments start at 36MB | |
2903 | */ | |
2904 | if (gmch_ctrl < 0x11) | |
2905 | return gmch_ctrl << 25; | |
2906 | else if (gmch_ctrl < 0x17) | |
2907 | return (gmch_ctrl - 0x11 + 2) << 22; | |
2908 | else | |
2909 | return (gmch_ctrl - 0x17 + 9) << 22; | |
2910 | } | |
2911 | ||
66375014 DL |
2912 | static size_t gen9_get_stolen_size(u16 gen9_gmch_ctl) |
2913 | { | |
2914 | gen9_gmch_ctl >>= BDW_GMCH_GMS_SHIFT; | |
2915 | gen9_gmch_ctl &= BDW_GMCH_GMS_MASK; | |
2916 | ||
2917 | if (gen9_gmch_ctl < 0xf0) | |
2918 | return gen9_gmch_ctl << 25; /* 32 MB units */ | |
2919 | else | |
2920 | /* 4MB increments starting at 0xf0 for 4MB */ | |
2921 | return (gen9_gmch_ctl - 0xf0 + 1) << 22; | |
2922 | } | |
2923 | ||
63340133 BW |
2924 | static int ggtt_probe_common(struct drm_device *dev, |
2925 | size_t gtt_size) | |
2926 | { | |
72e96d64 JL |
2927 | struct drm_i915_private *dev_priv = to_i915(dev); |
2928 | struct i915_ggtt *ggtt = &dev_priv->ggtt; | |
4ad2af1e | 2929 | struct i915_page_scratch *scratch_page; |
72e96d64 | 2930 | phys_addr_t ggtt_phys_addr; |
63340133 BW |
2931 | |
2932 | /* For Modern GENs the PTEs and register space are split in the BAR */ | |
72e96d64 JL |
2933 | ggtt_phys_addr = pci_resource_start(dev->pdev, 0) + |
2934 | (pci_resource_len(dev->pdev, 0) / 2); | |
63340133 | 2935 | |
2a073f89 ID |
2936 | /* |
2937 | * On BXT writes larger than 64 bit to the GTT pagetable range will be | |
2938 | * dropped. For WC mappings in general we have 64 byte burst writes | |
2939 | * when the WC buffer is flushed, so we can't use it, but have to | |
2940 | * resort to an uncached mapping. The WC issue is easily caught by the | |
2941 | * readback check when writing GTT PTE entries. | |
2942 | */ | |
2943 | if (IS_BROXTON(dev)) | |
72e96d64 | 2944 | ggtt->gsm = ioremap_nocache(ggtt_phys_addr, gtt_size); |
2a073f89 | 2945 | else |
72e96d64 JL |
2946 | ggtt->gsm = ioremap_wc(ggtt_phys_addr, gtt_size); |
2947 | if (!ggtt->gsm) { | |
63340133 BW |
2948 | DRM_ERROR("Failed to map the gtt page table\n"); |
2949 | return -ENOMEM; | |
2950 | } | |
2951 | ||
4ad2af1e MK |
2952 | scratch_page = alloc_scratch_page(dev); |
2953 | if (IS_ERR(scratch_page)) { | |
63340133 BW |
2954 | DRM_ERROR("Scratch setup failed\n"); |
2955 | /* iounmap will also get called at remove, but meh */ | |
72e96d64 | 2956 | iounmap(ggtt->gsm); |
4ad2af1e | 2957 | return PTR_ERR(scratch_page); |
63340133 BW |
2958 | } |
2959 | ||
72e96d64 | 2960 | ggtt->base.scratch_page = scratch_page; |
4ad2af1e MK |
2961 | |
2962 | return 0; | |
63340133 BW |
2963 | } |
2964 | ||
fbe5d36e BW |
2965 | /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability |
2966 | * bits. When using advanced contexts each context stores its own PAT, but | |
2967 | * writing this data shouldn't be harmful even in those cases. */ | |
ee0ce478 | 2968 | static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv) |
fbe5d36e | 2969 | { |
fbe5d36e BW |
2970 | uint64_t pat; |
2971 | ||
2972 | pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC) | /* for normal objects, no eLLC */ | |
2973 | GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something pointing to ptes? */ | |
2974 | GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC) | /* for scanout with eLLC */ | |
2975 | GEN8_PPAT(3, GEN8_PPAT_UC) | /* Uncached objects, mostly for scanout */ | |
2976 | GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) | | |
2977 | GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) | | |
2978 | GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) | | |
2979 | GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3)); | |
2980 | ||
2d1fe073 | 2981 | if (!USES_PPGTT(dev_priv)) |
d6a8b72e RV |
2982 | /* Spec: "For GGTT, there is NO pat_sel[2:0] from the entry, |
2983 | * so RTL will always use the value corresponding to | |
2984 | * pat_sel = 000". | |
2985 | * So let's disable cache for GGTT to avoid screen corruptions. | |
2986 | * MOCS still can be used though. | |
2987 | * - System agent ggtt writes (i.e. cpu gtt mmaps) already work | |
2988 | * before this patch, i.e. the same uncached + snooping access | |
2989 | * like on gen6/7 seems to be in effect. | |
2990 | * - So this just fixes blitter/render access. Again it looks | |
2991 | * like it's not just uncached access, but uncached + snooping. | |
2992 | * So we can still hold onto all our assumptions wrt cpu | |
2993 | * clflushing on LLC machines. | |
2994 | */ | |
2995 | pat = GEN8_PPAT(0, GEN8_PPAT_UC); | |
2996 | ||
fbe5d36e BW |
2997 | /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b |
2998 | * write would work. */ | |
7e435ad2 VS |
2999 | I915_WRITE(GEN8_PRIVATE_PAT_LO, pat); |
3000 | I915_WRITE(GEN8_PRIVATE_PAT_HI, pat >> 32); | |
fbe5d36e BW |
3001 | } |
3002 | ||
ee0ce478 VS |
3003 | static void chv_setup_private_ppat(struct drm_i915_private *dev_priv) |
3004 | { | |
3005 | uint64_t pat; | |
3006 | ||
3007 | /* | |
3008 | * Map WB on BDW to snooped on CHV. | |
3009 | * | |
3010 | * Only the snoop bit has meaning for CHV, the rest is | |
3011 | * ignored. | |
3012 | * | |
cf3d262e VS |
3013 | * The hardware will never snoop for certain types of accesses: |
3014 | * - CPU GTT (GMADR->GGTT->no snoop->memory) | |
3015 | * - PPGTT page tables | |
3016 | * - some other special cycles | |
3017 | * | |
3018 | * As with BDW, we also need to consider the following for GT accesses: | |
3019 | * "For GGTT, there is NO pat_sel[2:0] from the entry, | |
3020 | * so RTL will always use the value corresponding to | |
3021 | * pat_sel = 000". | |
3022 | * Which means we must set the snoop bit in PAT entry 0 | |
3023 | * in order to keep the global status page working. | |
ee0ce478 VS |
3024 | */ |
3025 | pat = GEN8_PPAT(0, CHV_PPAT_SNOOP) | | |
3026 | GEN8_PPAT(1, 0) | | |
3027 | GEN8_PPAT(2, 0) | | |
3028 | GEN8_PPAT(3, 0) | | |
3029 | GEN8_PPAT(4, CHV_PPAT_SNOOP) | | |
3030 | GEN8_PPAT(5, CHV_PPAT_SNOOP) | | |
3031 | GEN8_PPAT(6, CHV_PPAT_SNOOP) | | |
3032 | GEN8_PPAT(7, CHV_PPAT_SNOOP); | |
3033 | ||
7e435ad2 VS |
3034 | I915_WRITE(GEN8_PRIVATE_PAT_LO, pat); |
3035 | I915_WRITE(GEN8_PRIVATE_PAT_HI, pat >> 32); | |
ee0ce478 VS |
3036 | } |
3037 | ||
d507d735 | 3038 | static int gen8_gmch_probe(struct i915_ggtt *ggtt) |
63340133 | 3039 | { |
d507d735 | 3040 | struct drm_device *dev = ggtt->base.dev; |
72e96d64 | 3041 | struct drm_i915_private *dev_priv = to_i915(dev); |
63340133 BW |
3042 | u16 snb_gmch_ctl; |
3043 | int ret; | |
3044 | ||
3045 | /* TODO: We're not aware of mappable constraints on gen8 yet */ | |
d507d735 JL |
3046 | ggtt->mappable_base = pci_resource_start(dev->pdev, 2); |
3047 | ggtt->mappable_end = pci_resource_len(dev->pdev, 2); | |
63340133 BW |
3048 | |
3049 | if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(39))) | |
3050 | pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(39)); | |
3051 | ||
3052 | pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl); | |
3053 | ||
66375014 | 3054 | if (INTEL_INFO(dev)->gen >= 9) { |
d507d735 JL |
3055 | ggtt->stolen_size = gen9_get_stolen_size(snb_gmch_ctl); |
3056 | ggtt->size = gen8_get_total_gtt_size(snb_gmch_ctl); | |
66375014 | 3057 | } else if (IS_CHERRYVIEW(dev)) { |
d507d735 JL |
3058 | ggtt->stolen_size = chv_get_stolen_size(snb_gmch_ctl); |
3059 | ggtt->size = chv_get_total_gtt_size(snb_gmch_ctl); | |
d7f25f23 | 3060 | } else { |
d507d735 JL |
3061 | ggtt->stolen_size = gen8_get_stolen_size(snb_gmch_ctl); |
3062 | ggtt->size = gen8_get_total_gtt_size(snb_gmch_ctl); | |
d7f25f23 | 3063 | } |
63340133 | 3064 | |
d507d735 | 3065 | ggtt->base.total = (ggtt->size / sizeof(gen8_pte_t)) << PAGE_SHIFT; |
63340133 | 3066 | |
5a4e33a3 | 3067 | if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev)) |
ee0ce478 VS |
3068 | chv_setup_private_ppat(dev_priv); |
3069 | else | |
3070 | bdw_setup_private_ppat(dev_priv); | |
fbe5d36e | 3071 | |
d507d735 | 3072 | ret = ggtt_probe_common(dev, ggtt->size); |
63340133 | 3073 | |
d507d735 | 3074 | ggtt->base.clear_range = gen8_ggtt_clear_range; |
c140330b | 3075 | if (IS_CHERRYVIEW(dev_priv)) |
d507d735 JL |
3076 | ggtt->base.insert_entries = gen8_ggtt_insert_entries__BKL; |
3077 | else | |
3078 | ggtt->base.insert_entries = gen8_ggtt_insert_entries; | |
3079 | ggtt->base.bind_vma = ggtt_bind_vma; | |
3080 | ggtt->base.unbind_vma = ggtt_unbind_vma; | |
3081 | ||
63340133 BW |
3082 | return ret; |
3083 | } | |
3084 | ||
d507d735 | 3085 | static int gen6_gmch_probe(struct i915_ggtt *ggtt) |
e76e9aeb | 3086 | { |
d507d735 | 3087 | struct drm_device *dev = ggtt->base.dev; |
e76e9aeb | 3088 | u16 snb_gmch_ctl; |
e76e9aeb BW |
3089 | int ret; |
3090 | ||
d507d735 JL |
3091 | ggtt->mappable_base = pci_resource_start(dev->pdev, 2); |
3092 | ggtt->mappable_end = pci_resource_len(dev->pdev, 2); | |
41907ddc | 3093 | |
baa09f5f BW |
3094 | /* 64/512MB is the current min/max we actually know of, but this is just |
3095 | * a coarse sanity check. | |
e76e9aeb | 3096 | */ |
d507d735 JL |
3097 | if ((ggtt->mappable_end < (64<<20) || (ggtt->mappable_end > (512<<20)))) { |
3098 | DRM_ERROR("Unknown GMADR size (%llx)\n", ggtt->mappable_end); | |
baa09f5f | 3099 | return -ENXIO; |
e76e9aeb BW |
3100 | } |
3101 | ||
e76e9aeb BW |
3102 | if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40))) |
3103 | pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40)); | |
e76e9aeb | 3104 | pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl); |
e76e9aeb | 3105 | |
d507d735 JL |
3106 | ggtt->stolen_size = gen6_get_stolen_size(snb_gmch_ctl); |
3107 | ggtt->size = gen6_get_total_gtt_size(snb_gmch_ctl); | |
3108 | ggtt->base.total = (ggtt->size / sizeof(gen6_pte_t)) << PAGE_SHIFT; | |
e76e9aeb | 3109 | |
d507d735 | 3110 | ret = ggtt_probe_common(dev, ggtt->size); |
e76e9aeb | 3111 | |
d507d735 JL |
3112 | ggtt->base.clear_range = gen6_ggtt_clear_range; |
3113 | ggtt->base.insert_entries = gen6_ggtt_insert_entries; | |
3114 | ggtt->base.bind_vma = ggtt_bind_vma; | |
3115 | ggtt->base.unbind_vma = ggtt_unbind_vma; | |
7faf1ab2 | 3116 | |
e76e9aeb BW |
3117 | return ret; |
3118 | } | |
3119 | ||
853ba5d2 | 3120 | static void gen6_gmch_remove(struct i915_address_space *vm) |
e76e9aeb | 3121 | { |
62106b4f | 3122 | struct i915_ggtt *ggtt = container_of(vm, struct i915_ggtt, base); |
853ba5d2 | 3123 | |
62106b4f | 3124 | iounmap(ggtt->gsm); |
4ad2af1e | 3125 | free_scratch_page(vm->dev, vm->scratch_page); |
644ec02b | 3126 | } |
baa09f5f | 3127 | |
d507d735 | 3128 | static int i915_gmch_probe(struct i915_ggtt *ggtt) |
baa09f5f | 3129 | { |
d507d735 | 3130 | struct drm_device *dev = ggtt->base.dev; |
72e96d64 | 3131 | struct drm_i915_private *dev_priv = to_i915(dev); |
baa09f5f BW |
3132 | int ret; |
3133 | ||
baa09f5f BW |
3134 | ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->dev->pdev, NULL); |
3135 | if (!ret) { | |
3136 | DRM_ERROR("failed to set up gmch\n"); | |
3137 | return -EIO; | |
3138 | } | |
3139 | ||
d507d735 JL |
3140 | intel_gtt_get(&ggtt->base.total, &ggtt->stolen_size, |
3141 | &ggtt->mappable_base, &ggtt->mappable_end); | |
baa09f5f | 3142 | |
d507d735 JL |
3143 | ggtt->do_idle_maps = needs_idle_maps(dev_priv->dev); |
3144 | ggtt->base.insert_entries = i915_ggtt_insert_entries; | |
3145 | ggtt->base.clear_range = i915_ggtt_clear_range; | |
3146 | ggtt->base.bind_vma = ggtt_bind_vma; | |
3147 | ggtt->base.unbind_vma = ggtt_unbind_vma; | |
baa09f5f | 3148 | |
d507d735 | 3149 | if (unlikely(ggtt->do_idle_maps)) |
c0a7f818 CW |
3150 | DRM_INFO("applying Ironlake quirks for intel_iommu\n"); |
3151 | ||
baa09f5f BW |
3152 | return 0; |
3153 | } | |
3154 | ||
853ba5d2 | 3155 | static void i915_gmch_remove(struct i915_address_space *vm) |
baa09f5f BW |
3156 | { |
3157 | intel_gmch_remove(); | |
3158 | } | |
3159 | ||
d85489d3 JL |
3160 | /** |
3161 | * i915_ggtt_init_hw - Initialize GGTT hardware | |
3162 | * @dev: DRM device | |
3163 | */ | |
3164 | int i915_ggtt_init_hw(struct drm_device *dev) | |
baa09f5f | 3165 | { |
72e96d64 | 3166 | struct drm_i915_private *dev_priv = to_i915(dev); |
62106b4f | 3167 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
baa09f5f BW |
3168 | int ret; |
3169 | ||
baa09f5f | 3170 | if (INTEL_INFO(dev)->gen <= 5) { |
62106b4f JL |
3171 | ggtt->probe = i915_gmch_probe; |
3172 | ggtt->base.cleanup = i915_gmch_remove; | |
63340133 | 3173 | } else if (INTEL_INFO(dev)->gen < 8) { |
62106b4f JL |
3174 | ggtt->probe = gen6_gmch_probe; |
3175 | ggtt->base.cleanup = gen6_gmch_remove; | |
3accaf7e MK |
3176 | |
3177 | if (HAS_EDRAM(dev)) | |
62106b4f | 3178 | ggtt->base.pte_encode = iris_pte_encode; |
4d15c145 | 3179 | else if (IS_HASWELL(dev)) |
62106b4f | 3180 | ggtt->base.pte_encode = hsw_pte_encode; |
b2f21b4d | 3181 | else if (IS_VALLEYVIEW(dev)) |
62106b4f | 3182 | ggtt->base.pte_encode = byt_pte_encode; |
350ec881 | 3183 | else if (INTEL_INFO(dev)->gen >= 7) |
62106b4f | 3184 | ggtt->base.pte_encode = ivb_pte_encode; |
b2f21b4d | 3185 | else |
62106b4f | 3186 | ggtt->base.pte_encode = snb_pte_encode; |
63340133 | 3187 | } else { |
62106b4f JL |
3188 | ggtt->probe = gen8_gmch_probe; |
3189 | ggtt->base.cleanup = gen6_gmch_remove; | |
baa09f5f BW |
3190 | } |
3191 | ||
62106b4f JL |
3192 | ggtt->base.dev = dev; |
3193 | ggtt->base.is_ggtt = true; | |
c114f76a | 3194 | |
d507d735 | 3195 | ret = ggtt->probe(ggtt); |
a54c0c27 | 3196 | if (ret) |
baa09f5f | 3197 | return ret; |
baa09f5f | 3198 | |
c890e2d5 CW |
3199 | if ((ggtt->base.total - 1) >> 32) { |
3200 | DRM_ERROR("We never expected a Global GTT with more than 32bits" | |
3201 | "of address space! Found %lldM!\n", | |
3202 | ggtt->base.total >> 20); | |
3203 | ggtt->base.total = 1ULL << 32; | |
3204 | ggtt->mappable_end = min(ggtt->mappable_end, ggtt->base.total); | |
3205 | } | |
3206 | ||
a4eba47b ID |
3207 | /* |
3208 | * Initialise stolen early so that we may reserve preallocated | |
3209 | * objects for the BIOS to KMS transition. | |
3210 | */ | |
3211 | ret = i915_gem_init_stolen(dev); | |
3212 | if (ret) | |
3213 | goto out_gtt_cleanup; | |
3214 | ||
baa09f5f | 3215 | /* GMADR is the PCI mmio aperture into the global GTT. */ |
c44ef60e | 3216 | DRM_INFO("Memory usable by graphics device = %lluM\n", |
62106b4f JL |
3217 | ggtt->base.total >> 20); |
3218 | DRM_DEBUG_DRIVER("GMADR size = %lldM\n", ggtt->mappable_end >> 20); | |
3219 | DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", ggtt->stolen_size >> 20); | |
5db6c735 DV |
3220 | #ifdef CONFIG_INTEL_IOMMU |
3221 | if (intel_iommu_gfx_mapped) | |
3222 | DRM_INFO("VT-d active for gfx access\n"); | |
3223 | #endif | |
baa09f5f BW |
3224 | |
3225 | return 0; | |
a4eba47b ID |
3226 | |
3227 | out_gtt_cleanup: | |
72e96d64 | 3228 | ggtt->base.cleanup(&ggtt->base); |
a4eba47b ID |
3229 | |
3230 | return ret; | |
baa09f5f | 3231 | } |
6f65e29a | 3232 | |
fa42331b DV |
3233 | void i915_gem_restore_gtt_mappings(struct drm_device *dev) |
3234 | { | |
72e96d64 JL |
3235 | struct drm_i915_private *dev_priv = to_i915(dev); |
3236 | struct i915_ggtt *ggtt = &dev_priv->ggtt; | |
fa42331b | 3237 | struct drm_i915_gem_object *obj; |
2c3d9984 TU |
3238 | struct i915_vma *vma; |
3239 | bool flush; | |
fa42331b DV |
3240 | |
3241 | i915_check_and_clear_faults(dev); | |
3242 | ||
3243 | /* First fill our portion of the GTT with scratch pages */ | |
72e96d64 JL |
3244 | ggtt->base.clear_range(&ggtt->base, ggtt->base.start, ggtt->base.total, |
3245 | true); | |
fa42331b | 3246 | |
2c3d9984 | 3247 | /* Cache flush objects bound into GGTT and rebind them. */ |
fa42331b | 3248 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
2c3d9984 | 3249 | flush = false; |
1c7f4bca | 3250 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
72e96d64 | 3251 | if (vma->vm != &ggtt->base) |
2c3d9984 | 3252 | continue; |
fa42331b | 3253 | |
2c3d9984 TU |
3254 | WARN_ON(i915_vma_bind(vma, obj->cache_level, |
3255 | PIN_UPDATE)); | |
fa42331b | 3256 | |
2c3d9984 TU |
3257 | flush = true; |
3258 | } | |
3259 | ||
3260 | if (flush) | |
3261 | i915_gem_clflush_object(obj, obj->pin_display); | |
3262 | } | |
fa42331b DV |
3263 | |
3264 | if (INTEL_INFO(dev)->gen >= 8) { | |
3265 | if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev)) | |
3266 | chv_setup_private_ppat(dev_priv); | |
3267 | else | |
3268 | bdw_setup_private_ppat(dev_priv); | |
3269 | ||
3270 | return; | |
3271 | } | |
3272 | ||
3273 | if (USES_PPGTT(dev)) { | |
72e96d64 JL |
3274 | struct i915_address_space *vm; |
3275 | ||
fa42331b DV |
3276 | list_for_each_entry(vm, &dev_priv->vm_list, global_link) { |
3277 | /* TODO: Perhaps it shouldn't be gen6 specific */ | |
3278 | ||
e5716f55 | 3279 | struct i915_hw_ppgtt *ppgtt; |
fa42331b | 3280 | |
e5716f55 | 3281 | if (vm->is_ggtt) |
fa42331b | 3282 | ppgtt = dev_priv->mm.aliasing_ppgtt; |
e5716f55 JL |
3283 | else |
3284 | ppgtt = i915_vm_to_ppgtt(vm); | |
fa42331b DV |
3285 | |
3286 | gen6_write_page_range(dev_priv, &ppgtt->pd, | |
3287 | 0, ppgtt->base.total); | |
3288 | } | |
3289 | } | |
3290 | ||
3291 | i915_ggtt_flush(dev_priv); | |
3292 | } | |
3293 | ||
ec7adb6e JL |
3294 | static struct i915_vma * |
3295 | __i915_gem_vma_create(struct drm_i915_gem_object *obj, | |
3296 | struct i915_address_space *vm, | |
3297 | const struct i915_ggtt_view *ggtt_view) | |
6f65e29a | 3298 | { |
dabde5c7 | 3299 | struct i915_vma *vma; |
6f65e29a | 3300 | |
ec7adb6e JL |
3301 | if (WARN_ON(i915_is_ggtt(vm) != !!ggtt_view)) |
3302 | return ERR_PTR(-EINVAL); | |
e20d2ab7 CW |
3303 | |
3304 | vma = kmem_cache_zalloc(to_i915(obj->base.dev)->vmas, GFP_KERNEL); | |
dabde5c7 DC |
3305 | if (vma == NULL) |
3306 | return ERR_PTR(-ENOMEM); | |
ec7adb6e | 3307 | |
1c7f4bca CW |
3308 | INIT_LIST_HEAD(&vma->vm_link); |
3309 | INIT_LIST_HEAD(&vma->obj_link); | |
6f65e29a BW |
3310 | INIT_LIST_HEAD(&vma->exec_list); |
3311 | vma->vm = vm; | |
3312 | vma->obj = obj; | |
596c5923 | 3313 | vma->is_ggtt = i915_is_ggtt(vm); |
6f65e29a | 3314 | |
777dc5bb | 3315 | if (i915_is_ggtt(vm)) |
ec7adb6e | 3316 | vma->ggtt_view = *ggtt_view; |
596c5923 CW |
3317 | else |
3318 | i915_ppgtt_get(i915_vm_to_ppgtt(vm)); | |
6f65e29a | 3319 | |
1c7f4bca | 3320 | list_add_tail(&vma->obj_link, &obj->vma_list); |
6f65e29a BW |
3321 | |
3322 | return vma; | |
3323 | } | |
3324 | ||
3325 | struct i915_vma * | |
ec7adb6e JL |
3326 | i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj, |
3327 | struct i915_address_space *vm) | |
3328 | { | |
3329 | struct i915_vma *vma; | |
3330 | ||
3331 | vma = i915_gem_obj_to_vma(obj, vm); | |
3332 | if (!vma) | |
3333 | vma = __i915_gem_vma_create(obj, vm, | |
3334 | i915_is_ggtt(vm) ? &i915_ggtt_view_normal : NULL); | |
3335 | ||
3336 | return vma; | |
3337 | } | |
3338 | ||
3339 | struct i915_vma * | |
3340 | i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object *obj, | |
fe14d5f4 | 3341 | const struct i915_ggtt_view *view) |
6f65e29a | 3342 | { |
72e96d64 JL |
3343 | struct drm_device *dev = obj->base.dev; |
3344 | struct drm_i915_private *dev_priv = to_i915(dev); | |
3345 | struct i915_ggtt *ggtt = &dev_priv->ggtt; | |
ade7daa1 | 3346 | struct i915_vma *vma = i915_gem_obj_to_ggtt_view(obj, view); |
ec7adb6e | 3347 | |
6f65e29a | 3348 | if (!vma) |
72e96d64 | 3349 | vma = __i915_gem_vma_create(obj, &ggtt->base, view); |
6f65e29a BW |
3350 | |
3351 | return vma; | |
ec7adb6e | 3352 | |
6f65e29a | 3353 | } |
fe14d5f4 | 3354 | |
804beb4b | 3355 | static struct scatterlist * |
2d7f3bdb | 3356 | rotate_pages(const dma_addr_t *in, unsigned int offset, |
804beb4b | 3357 | unsigned int width, unsigned int height, |
87130255 | 3358 | unsigned int stride, |
804beb4b | 3359 | struct sg_table *st, struct scatterlist *sg) |
50470bb0 TU |
3360 | { |
3361 | unsigned int column, row; | |
3362 | unsigned int src_idx; | |
50470bb0 | 3363 | |
50470bb0 | 3364 | for (column = 0; column < width; column++) { |
87130255 | 3365 | src_idx = stride * (height - 1) + column; |
50470bb0 TU |
3366 | for (row = 0; row < height; row++) { |
3367 | st->nents++; | |
3368 | /* We don't need the pages, but need to initialize | |
3369 | * the entries so the sg list can be happily traversed. | |
3370 | * The only thing we need are DMA addresses. | |
3371 | */ | |
3372 | sg_set_page(sg, NULL, PAGE_SIZE, 0); | |
804beb4b | 3373 | sg_dma_address(sg) = in[offset + src_idx]; |
50470bb0 TU |
3374 | sg_dma_len(sg) = PAGE_SIZE; |
3375 | sg = sg_next(sg); | |
87130255 | 3376 | src_idx -= stride; |
50470bb0 TU |
3377 | } |
3378 | } | |
804beb4b TU |
3379 | |
3380 | return sg; | |
50470bb0 TU |
3381 | } |
3382 | ||
3383 | static struct sg_table * | |
11d23e6f | 3384 | intel_rotate_fb_obj_pages(struct intel_rotation_info *rot_info, |
50470bb0 TU |
3385 | struct drm_i915_gem_object *obj) |
3386 | { | |
1663b9d6 | 3387 | unsigned int size_pages = rot_info->plane[0].width * rot_info->plane[0].height; |
89e3e142 | 3388 | unsigned int size_pages_uv; |
50470bb0 TU |
3389 | struct sg_page_iter sg_iter; |
3390 | unsigned long i; | |
3391 | dma_addr_t *page_addr_list; | |
3392 | struct sg_table *st; | |
89e3e142 TU |
3393 | unsigned int uv_start_page; |
3394 | struct scatterlist *sg; | |
1d00dad5 | 3395 | int ret = -ENOMEM; |
50470bb0 | 3396 | |
50470bb0 | 3397 | /* Allocate a temporary list of source pages for random access. */ |
f2a85e19 CW |
3398 | page_addr_list = drm_malloc_gfp(obj->base.size / PAGE_SIZE, |
3399 | sizeof(dma_addr_t), | |
3400 | GFP_TEMPORARY); | |
50470bb0 TU |
3401 | if (!page_addr_list) |
3402 | return ERR_PTR(ret); | |
3403 | ||
89e3e142 TU |
3404 | /* Account for UV plane with NV12. */ |
3405 | if (rot_info->pixel_format == DRM_FORMAT_NV12) | |
1663b9d6 | 3406 | size_pages_uv = rot_info->plane[1].width * rot_info->plane[1].height; |
89e3e142 TU |
3407 | else |
3408 | size_pages_uv = 0; | |
3409 | ||
50470bb0 TU |
3410 | /* Allocate target SG list. */ |
3411 | st = kmalloc(sizeof(*st), GFP_KERNEL); | |
3412 | if (!st) | |
3413 | goto err_st_alloc; | |
3414 | ||
89e3e142 | 3415 | ret = sg_alloc_table(st, size_pages + size_pages_uv, GFP_KERNEL); |
50470bb0 TU |
3416 | if (ret) |
3417 | goto err_sg_alloc; | |
3418 | ||
3419 | /* Populate source page list from the object. */ | |
3420 | i = 0; | |
3421 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) { | |
3422 | page_addr_list[i] = sg_page_iter_dma_address(&sg_iter); | |
3423 | i++; | |
3424 | } | |
3425 | ||
11f20322 VS |
3426 | st->nents = 0; |
3427 | sg = st->sgl; | |
3428 | ||
50470bb0 | 3429 | /* Rotate the pages. */ |
89e3e142 | 3430 | sg = rotate_pages(page_addr_list, 0, |
1663b9d6 VS |
3431 | rot_info->plane[0].width, rot_info->plane[0].height, |
3432 | rot_info->plane[0].width, | |
11f20322 | 3433 | st, sg); |
50470bb0 | 3434 | |
89e3e142 TU |
3435 | /* Append the UV plane if NV12. */ |
3436 | if (rot_info->pixel_format == DRM_FORMAT_NV12) { | |
3437 | uv_start_page = size_pages; | |
3438 | ||
3439 | /* Check for tile-row un-alignment. */ | |
3440 | if (offset_in_page(rot_info->uv_offset)) | |
3441 | uv_start_page--; | |
3442 | ||
dedf278c TU |
3443 | rot_info->uv_start_page = uv_start_page; |
3444 | ||
11f20322 VS |
3445 | sg = rotate_pages(page_addr_list, rot_info->uv_start_page, |
3446 | rot_info->plane[1].width, rot_info->plane[1].height, | |
3447 | rot_info->plane[1].width, | |
3448 | st, sg); | |
89e3e142 TU |
3449 | } |
3450 | ||
1663b9d6 VS |
3451 | DRM_DEBUG_KMS("Created rotated page mapping for object size %zu (%ux%u tiles, %u pages (%u plane 0)).\n", |
3452 | obj->base.size, rot_info->plane[0].width, | |
3453 | rot_info->plane[0].height, size_pages + size_pages_uv, | |
89e3e142 | 3454 | size_pages); |
50470bb0 TU |
3455 | |
3456 | drm_free_large(page_addr_list); | |
3457 | ||
3458 | return st; | |
3459 | ||
3460 | err_sg_alloc: | |
3461 | kfree(st); | |
3462 | err_st_alloc: | |
3463 | drm_free_large(page_addr_list); | |
3464 | ||
1663b9d6 VS |
3465 | DRM_DEBUG_KMS("Failed to create rotated mapping for object size %zu! (%d) (%ux%u tiles, %u pages (%u plane 0))\n", |
3466 | obj->base.size, ret, rot_info->plane[0].width, | |
3467 | rot_info->plane[0].height, size_pages + size_pages_uv, | |
89e3e142 | 3468 | size_pages); |
50470bb0 TU |
3469 | return ERR_PTR(ret); |
3470 | } | |
ec7adb6e | 3471 | |
8bd7ef16 JL |
3472 | static struct sg_table * |
3473 | intel_partial_pages(const struct i915_ggtt_view *view, | |
3474 | struct drm_i915_gem_object *obj) | |
3475 | { | |
3476 | struct sg_table *st; | |
3477 | struct scatterlist *sg; | |
3478 | struct sg_page_iter obj_sg_iter; | |
3479 | int ret = -ENOMEM; | |
3480 | ||
3481 | st = kmalloc(sizeof(*st), GFP_KERNEL); | |
3482 | if (!st) | |
3483 | goto err_st_alloc; | |
3484 | ||
3485 | ret = sg_alloc_table(st, view->params.partial.size, GFP_KERNEL); | |
3486 | if (ret) | |
3487 | goto err_sg_alloc; | |
3488 | ||
3489 | sg = st->sgl; | |
3490 | st->nents = 0; | |
3491 | for_each_sg_page(obj->pages->sgl, &obj_sg_iter, obj->pages->nents, | |
3492 | view->params.partial.offset) | |
3493 | { | |
3494 | if (st->nents >= view->params.partial.size) | |
3495 | break; | |
3496 | ||
3497 | sg_set_page(sg, NULL, PAGE_SIZE, 0); | |
3498 | sg_dma_address(sg) = sg_page_iter_dma_address(&obj_sg_iter); | |
3499 | sg_dma_len(sg) = PAGE_SIZE; | |
3500 | ||
3501 | sg = sg_next(sg); | |
3502 | st->nents++; | |
3503 | } | |
3504 | ||
3505 | return st; | |
3506 | ||
3507 | err_sg_alloc: | |
3508 | kfree(st); | |
3509 | err_st_alloc: | |
3510 | return ERR_PTR(ret); | |
3511 | } | |
3512 | ||
70b9f6f8 | 3513 | static int |
50470bb0 | 3514 | i915_get_ggtt_vma_pages(struct i915_vma *vma) |
fe14d5f4 | 3515 | { |
50470bb0 TU |
3516 | int ret = 0; |
3517 | ||
fe14d5f4 TU |
3518 | if (vma->ggtt_view.pages) |
3519 | return 0; | |
3520 | ||
3521 | if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) | |
3522 | vma->ggtt_view.pages = vma->obj->pages; | |
50470bb0 TU |
3523 | else if (vma->ggtt_view.type == I915_GGTT_VIEW_ROTATED) |
3524 | vma->ggtt_view.pages = | |
11d23e6f | 3525 | intel_rotate_fb_obj_pages(&vma->ggtt_view.params.rotated, vma->obj); |
8bd7ef16 JL |
3526 | else if (vma->ggtt_view.type == I915_GGTT_VIEW_PARTIAL) |
3527 | vma->ggtt_view.pages = | |
3528 | intel_partial_pages(&vma->ggtt_view, vma->obj); | |
fe14d5f4 TU |
3529 | else |
3530 | WARN_ONCE(1, "GGTT view %u not implemented!\n", | |
3531 | vma->ggtt_view.type); | |
3532 | ||
3533 | if (!vma->ggtt_view.pages) { | |
ec7adb6e | 3534 | DRM_ERROR("Failed to get pages for GGTT view type %u!\n", |
fe14d5f4 | 3535 | vma->ggtt_view.type); |
50470bb0 TU |
3536 | ret = -EINVAL; |
3537 | } else if (IS_ERR(vma->ggtt_view.pages)) { | |
3538 | ret = PTR_ERR(vma->ggtt_view.pages); | |
3539 | vma->ggtt_view.pages = NULL; | |
3540 | DRM_ERROR("Failed to get pages for VMA view type %u (%d)!\n", | |
3541 | vma->ggtt_view.type, ret); | |
fe14d5f4 TU |
3542 | } |
3543 | ||
50470bb0 | 3544 | return ret; |
fe14d5f4 TU |
3545 | } |
3546 | ||
3547 | /** | |
3548 | * i915_vma_bind - Sets up PTEs for an VMA in it's corresponding address space. | |
3549 | * @vma: VMA to map | |
3550 | * @cache_level: mapping cache level | |
3551 | * @flags: flags like global or local mapping | |
3552 | * | |
3553 | * DMA addresses are taken from the scatter-gather table of this object (or of | |
3554 | * this VMA in case of non-default GGTT views) and PTE entries set up. | |
3555 | * Note that DMA addresses are also the only part of the SG table we care about. | |
3556 | */ | |
3557 | int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level, | |
3558 | u32 flags) | |
3559 | { | |
75d04a37 MK |
3560 | int ret; |
3561 | u32 bind_flags; | |
1d335d1b | 3562 | |
75d04a37 MK |
3563 | if (WARN_ON(flags == 0)) |
3564 | return -EINVAL; | |
1d335d1b | 3565 | |
75d04a37 | 3566 | bind_flags = 0; |
0875546c DV |
3567 | if (flags & PIN_GLOBAL) |
3568 | bind_flags |= GLOBAL_BIND; | |
3569 | if (flags & PIN_USER) | |
3570 | bind_flags |= LOCAL_BIND; | |
3571 | ||
3572 | if (flags & PIN_UPDATE) | |
3573 | bind_flags |= vma->bound; | |
3574 | else | |
3575 | bind_flags &= ~vma->bound; | |
3576 | ||
75d04a37 MK |
3577 | if (bind_flags == 0) |
3578 | return 0; | |
3579 | ||
3580 | if (vma->bound == 0 && vma->vm->allocate_va_range) { | |
b2dd4511 MK |
3581 | /* XXX: i915_vma_pin() will fix this +- hack */ |
3582 | vma->pin_count++; | |
596c5923 | 3583 | trace_i915_va_alloc(vma); |
75d04a37 MK |
3584 | ret = vma->vm->allocate_va_range(vma->vm, |
3585 | vma->node.start, | |
3586 | vma->node.size); | |
b2dd4511 | 3587 | vma->pin_count--; |
75d04a37 MK |
3588 | if (ret) |
3589 | return ret; | |
3590 | } | |
3591 | ||
3592 | ret = vma->vm->bind_vma(vma, cache_level, bind_flags); | |
70b9f6f8 DV |
3593 | if (ret) |
3594 | return ret; | |
0875546c DV |
3595 | |
3596 | vma->bound |= bind_flags; | |
fe14d5f4 TU |
3597 | |
3598 | return 0; | |
3599 | } | |
91e6711e JL |
3600 | |
3601 | /** | |
3602 | * i915_ggtt_view_size - Get the size of a GGTT view. | |
3603 | * @obj: Object the view is of. | |
3604 | * @view: The view in question. | |
3605 | * | |
3606 | * @return The size of the GGTT view in bytes. | |
3607 | */ | |
3608 | size_t | |
3609 | i915_ggtt_view_size(struct drm_i915_gem_object *obj, | |
3610 | const struct i915_ggtt_view *view) | |
3611 | { | |
9e759ff1 | 3612 | if (view->type == I915_GGTT_VIEW_NORMAL) { |
91e6711e | 3613 | return obj->base.size; |
9e759ff1 | 3614 | } else if (view->type == I915_GGTT_VIEW_ROTATED) { |
1663b9d6 | 3615 | return intel_rotation_info_size(&view->params.rotated) << PAGE_SHIFT; |
8bd7ef16 JL |
3616 | } else if (view->type == I915_GGTT_VIEW_PARTIAL) { |
3617 | return view->params.partial.size << PAGE_SHIFT; | |
91e6711e JL |
3618 | } else { |
3619 | WARN_ONCE(1, "GGTT view %u not implemented!\n", view->type); | |
3620 | return obj->base.size; | |
3621 | } | |
3622 | } | |
8ef8561f CW |
3623 | |
3624 | void __iomem *i915_vma_pin_iomap(struct i915_vma *vma) | |
3625 | { | |
3626 | void __iomem *ptr; | |
3627 | ||
3628 | lockdep_assert_held(&vma->vm->dev->struct_mutex); | |
3629 | if (WARN_ON(!vma->obj->map_and_fenceable)) | |
3630 | return ERR_PTR(-ENODEV); | |
3631 | ||
3632 | GEM_BUG_ON(!vma->is_ggtt); | |
3633 | GEM_BUG_ON((vma->bound & GLOBAL_BIND) == 0); | |
3634 | ||
3635 | ptr = vma->iomap; | |
3636 | if (ptr == NULL) { | |
3637 | ptr = io_mapping_map_wc(i915_vm_to_ggtt(vma->vm)->mappable, | |
3638 | vma->node.start, | |
3639 | vma->node.size); | |
3640 | if (ptr == NULL) | |
3641 | return ERR_PTR(-ENOMEM); | |
3642 | ||
3643 | vma->iomap = ptr; | |
3644 | } | |
3645 | ||
3646 | vma->pin_count++; | |
3647 | return ptr; | |
3648 | } |