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drm/i915: Disable CRT port after pipe on PCH platforms
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
319c1d42 40#include <drm/drm_atomic.h>
c196e1d6 41#include <drm/drm_atomic_helper.h>
760285e7
DH		 42#include <drm/drm_dp_helper.h>
43#include <drm/drm_crtc_helper.h>
465c120c
MR		 44#include <drm/drm_plane_helper.h>
45#include <drm/drm_rect.h>
c0f372b3 46#include <linux/dma_remapping.h>
79e53945 47
465c120c 48/* Primary plane formats for gen <= 3 */
568db4f2 49static const uint32_t i8xx_primary_formats[] = {
67fe7dc5
DL		 50 DRM_FORMAT_C8,
51 DRM_FORMAT_RGB565,
465c120c 52 DRM_FORMAT_XRGB1555,
67fe7dc5 53 DRM_FORMAT_XRGB8888,
465c120c
MR		 54};
55
56/* Primary plane formats for gen >= 4 */
568db4f2 57static const uint32_t i965_primary_formats[] = {
6c0fd451
DL		 58 DRM_FORMAT_C8,
59 DRM_FORMAT_RGB565,
60 DRM_FORMAT_XRGB8888,
61 DRM_FORMAT_XBGR8888,
62 DRM_FORMAT_XRGB2101010,
63 DRM_FORMAT_XBGR2101010,
64};
65
66static const uint32_t skl_primary_formats[] = {
67fe7dc5
DL		 67 DRM_FORMAT_C8,
68 DRM_FORMAT_RGB565,
69 DRM_FORMAT_XRGB8888,
465c120c 70 DRM_FORMAT_XBGR8888,
67fe7dc5 71 DRM_FORMAT_ARGB8888,
465c120c
MR		 72 DRM_FORMAT_ABGR8888,
73 DRM_FORMAT_XRGB2101010,
465c120c 74 DRM_FORMAT_XBGR2101010,
465c120c
MR		 75};
76
3d7d6510
MR		 77/* Cursor formats */
78static const uint32_t intel_cursor_formats[] = {
79 DRM_FORMAT_ARGB8888,
80};
81
6b383a7f 82static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 83
f1f644dc 84static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 85 struct intel_crtc_state *pipe_config);
18442d08 86static void ironlake_pch_clock_get(struct intel_crtc *crtc,
5cec258b 87 struct intel_crtc_state *pipe_config);
f1f644dc 88
8c7b5ccb 89static int intel_set_mode(struct drm_crtc *crtc,
83a57153 90 struct drm_atomic_state *state);
eb1bfe80
JB		 91static int intel_framebuffer_init(struct drm_device *dev,
92 struct intel_framebuffer *ifb,
93 struct drm_mode_fb_cmd2 *mode_cmd,
94 struct drm_i915_gem_object *obj);
5b18e57c
DV		 95static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
96static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
29407aab 97static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
f769cd24
VK		 98 struct intel_link_m_n *m_n,
99 struct intel_link_m_n *m2_n2);
29407aab 100static void ironlake_set_pipeconf(struct drm_crtc *crtc);
229fca97
DV		 101static void haswell_set_pipeconf(struct drm_crtc *crtc);
102static void intel_set_pipe_csc(struct drm_crtc *crtc);
d288f65f 103static void vlv_prepare_pll(struct intel_crtc *crtc,
5cec258b 104 const struct intel_crtc_state *pipe_config);
d288f65f 105static void chv_prepare_pll(struct intel_crtc *crtc,
5cec258b 106 const struct intel_crtc_state *pipe_config);
ea2c67bb
MR		 107static void intel_begin_crtc_commit(struct drm_crtc *crtc);
108static void intel_finish_crtc_commit(struct drm_crtc *crtc);
549e2bfb
CK		 109static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
110 struct intel_crtc_state *crtc_state);
5ab7b0b7
ID		 111static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
112 int num_connectors);
ce22dba9
ML		 113static void intel_crtc_enable_planes(struct drm_crtc *crtc);
114static void intel_crtc_disable_planes(struct drm_crtc *crtc);
e7457a9a 115
0e32b39c
DA		 116static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
117{
118 if (!connector->mst_port)
119 return connector->encoder;
120 else
121 return &connector->mst_port->mst_encoders[pipe]->base;
122}
123
79e53945 124typedef struct {
0206e353 125 int min, max;
79e53945
JB		 126} intel_range_t;
127
128typedef struct {
0206e353
AJ		 129 int dot_limit;
130 int p2_slow, p2_fast;
79e53945
JB		 131} intel_p2_t;
132
d4906093
ML		 133typedef struct intel_limit intel_limit_t;
134struct intel_limit {
0206e353
AJ		 135 intel_range_t dot, vco, n, m, m1, m2, p, p1;
136 intel_p2_t p2;
d4906093 137};
79e53945 138
d2acd215
DV		 139int
140intel_pch_rawclk(struct drm_device *dev)
141{
142 struct drm_i915_private *dev_priv = dev->dev_private;
143
144 WARN_ON(!HAS_PCH_SPLIT(dev));
145
146 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
147}
148
021357ac
CW		 149static inline u32 /* units of 100MHz */
150intel_fdi_link_freq(struct drm_device *dev)
151{
8b99e68c
CW		 152 if (IS_GEN5(dev)) {
153 struct drm_i915_private *dev_priv = dev->dev_private;
154 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
155 } else
156 return 27;
021357ac
CW		 157}
158
5d536e28 159static const intel_limit_t intel_limits_i8xx_dac = {
0206e353 160 .dot = { .min = 25000, .max = 350000 },
9c333719 161 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 162 .n = { .min = 2, .max = 16 },
0206e353
AJ		 163 .m = { .min = 96, .max = 140 },
164 .m1 = { .min = 18, .max = 26 },
165 .m2 = { .min = 6, .max = 16 },
166 .p = { .min = 4, .max = 128 },
167 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 168 .p2 = { .dot_limit = 165000,
169 .p2_slow = 4, .p2_fast = 2 },
e4b36699
KP		 170};
171
5d536e28
DV		 172static const intel_limit_t intel_limits_i8xx_dvo = {
173 .dot = { .min = 25000, .max = 350000 },
9c333719 174 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 175 .n = { .min = 2, .max = 16 },
5d536e28
DV		 176 .m = { .min = 96, .max = 140 },
177 .m1 = { .min = 18, .max = 26 },
178 .m2 = { .min = 6, .max = 16 },
179 .p = { .min = 4, .max = 128 },
180 .p1 = { .min = 2, .max = 33 },
181 .p2 = { .dot_limit = 165000,
182 .p2_slow = 4, .p2_fast = 4 },
183};
184
e4b36699 185static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353 186 .dot = { .min = 25000, .max = 350000 },
9c333719 187 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 188 .n = { .min = 2, .max = 16 },
0206e353
AJ		 189 .m = { .min = 96, .max = 140 },
190 .m1 = { .min = 18, .max = 26 },
191 .m2 = { .min = 6, .max = 16 },
192 .p = { .min = 4, .max = 128 },
193 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 194 .p2 = { .dot_limit = 165000,
195 .p2_slow = 14, .p2_fast = 7 },
e4b36699 196};
273e27ca 197
e4b36699 198static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 199 .dot = { .min = 20000, .max = 400000 },
200 .vco = { .min = 1400000, .max = 2800000 },
201 .n = { .min = 1, .max = 6 },
202 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 203 .m1 = { .min = 8, .max = 18 },
204 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 205 .p = { .min = 5, .max = 80 },
206 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 207 .p2 = { .dot_limit = 200000,
208 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 209};
210
211static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 212 .dot = { .min = 20000, .max = 400000 },
213 .vco = { .min = 1400000, .max = 2800000 },
214 .n = { .min = 1, .max = 6 },
215 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 216 .m1 = { .min = 8, .max = 18 },
217 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 218 .p = { .min = 7, .max = 98 },
219 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 220 .p2 = { .dot_limit = 112000,
221 .p2_slow = 14, .p2_fast = 7 },
e4b36699
KP		 222};
223
273e27ca 224
e4b36699 225static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 226 .dot = { .min = 25000, .max = 270000 },
227 .vco = { .min = 1750000, .max = 3500000},
228 .n = { .min = 1, .max = 4 },
229 .m = { .min = 104, .max = 138 },
230 .m1 = { .min = 17, .max = 23 },
231 .m2 = { .min = 5, .max = 11 },
232 .p = { .min = 10, .max = 30 },
233 .p1 = { .min = 1, .max = 3},
234 .p2 = { .dot_limit = 270000,
235 .p2_slow = 10,
236 .p2_fast = 10
044c7c41 237 },
e4b36699
KP		 238};
239
240static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 241 .dot = { .min = 22000, .max = 400000 },
242 .vco = { .min = 1750000, .max = 3500000},
243 .n = { .min = 1, .max = 4 },
244 .m = { .min = 104, .max = 138 },
245 .m1 = { .min = 16, .max = 23 },
246 .m2 = { .min = 5, .max = 11 },
247 .p = { .min = 5, .max = 80 },
248 .p1 = { .min = 1, .max = 8},
249 .p2 = { .dot_limit = 165000,
250 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 251};
252
253static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 254 .dot = { .min = 20000, .max = 115000 },
255 .vco = { .min = 1750000, .max = 3500000 },
256 .n = { .min = 1, .max = 3 },
257 .m = { .min = 104, .max = 138 },
258 .m1 = { .min = 17, .max = 23 },
259 .m2 = { .min = 5, .max = 11 },
260 .p = { .min = 28, .max = 112 },
261 .p1 = { .min = 2, .max = 8 },
262 .p2 = { .dot_limit = 0,
263 .p2_slow = 14, .p2_fast = 14
044c7c41 264 },
e4b36699
KP		 265};
266
267static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 268 .dot = { .min = 80000, .max = 224000 },
269 .vco = { .min = 1750000, .max = 3500000 },
270 .n = { .min = 1, .max = 3 },
271 .m = { .min = 104, .max = 138 },
272 .m1 = { .min = 17, .max = 23 },
273 .m2 = { .min = 5, .max = 11 },
274 .p = { .min = 14, .max = 42 },
275 .p1 = { .min = 2, .max = 6 },
276 .p2 = { .dot_limit = 0,
277 .p2_slow = 7, .p2_fast = 7
044c7c41 278 },
e4b36699
KP		 279};
280
f2b115e6 281static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 282 .dot = { .min = 20000, .max = 400000},
283 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 284 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 285 .n = { .min = 3, .max = 6 },
286 .m = { .min = 2, .max = 256 },
273e27ca 287 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 288 .m1 = { .min = 0, .max = 0 },
289 .m2 = { .min = 0, .max = 254 },
290 .p = { .min = 5, .max = 80 },
291 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 292 .p2 = { .dot_limit = 200000,
293 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 294};
295
f2b115e6 296static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 297 .dot = { .min = 20000, .max = 400000 },
298 .vco = { .min = 1700000, .max = 3500000 },
299 .n = { .min = 3, .max = 6 },
300 .m = { .min = 2, .max = 256 },
301 .m1 = { .min = 0, .max = 0 },
302 .m2 = { .min = 0, .max = 254 },
303 .p = { .min = 7, .max = 112 },
304 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 305 .p2 = { .dot_limit = 112000,
306 .p2_slow = 14, .p2_fast = 14 },
e4b36699
KP		 307};
308
273e27ca
EA		 309/* Ironlake / Sandybridge
310 *
311 * We calculate clock using (register_value + 2) for N/M1/M2, so here
312 * the range value for them is (actual_value - 2).
313 */
b91ad0ec 314static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 315 .dot = { .min = 25000, .max = 350000 },
316 .vco = { .min = 1760000, .max = 3510000 },
317 .n = { .min = 1, .max = 5 },
318 .m = { .min = 79, .max = 127 },
319 .m1 = { .min = 12, .max = 22 },
320 .m2 = { .min = 5, .max = 9 },
321 .p = { .min = 5, .max = 80 },
322 .p1 = { .min = 1, .max = 8 },
323 .p2 = { .dot_limit = 225000,
324 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 325};
326
b91ad0ec 327static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 328 .dot = { .min = 25000, .max = 350000 },
329 .vco = { .min = 1760000, .max = 3510000 },
330 .n = { .min = 1, .max = 3 },
331 .m = { .min = 79, .max = 118 },
332 .m1 = { .min = 12, .max = 22 },
333 .m2 = { .min = 5, .max = 9 },
334 .p = { .min = 28, .max = 112 },
335 .p1 = { .min = 2, .max = 8 },
336 .p2 = { .dot_limit = 225000,
337 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 338};
339
340static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 341 .dot = { .min = 25000, .max = 350000 },
342 .vco = { .min = 1760000, .max = 3510000 },
343 .n = { .min = 1, .max = 3 },
344 .m = { .min = 79, .max = 127 },
345 .m1 = { .min = 12, .max = 22 },
346 .m2 = { .min = 5, .max = 9 },
347 .p = { .min = 14, .max = 56 },
348 .p1 = { .min = 2, .max = 8 },
349 .p2 = { .dot_limit = 225000,
350 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 351};
352
273e27ca 353/* LVDS 100mhz refclk limits. */
b91ad0ec 354static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 355 .dot = { .min = 25000, .max = 350000 },
356 .vco = { .min = 1760000, .max = 3510000 },
357 .n = { .min = 1, .max = 2 },
358 .m = { .min = 79, .max = 126 },
359 .m1 = { .min = 12, .max = 22 },
360 .m2 = { .min = 5, .max = 9 },
361 .p = { .min = 28, .max = 112 },
0206e353 362 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 363 .p2 = { .dot_limit = 225000,
364 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 365};
366
367static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 368 .dot = { .min = 25000, .max = 350000 },
369 .vco = { .min = 1760000, .max = 3510000 },
370 .n = { .min = 1, .max = 3 },
371 .m = { .min = 79, .max = 126 },
372 .m1 = { .min = 12, .max = 22 },
373 .m2 = { .min = 5, .max = 9 },
374 .p = { .min = 14, .max = 42 },
0206e353 375 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 376 .p2 = { .dot_limit = 225000,
377 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 378};
379
dc730512 380static const intel_limit_t intel_limits_vlv = {
f01b7962
VS		 381 /*
382 * These are the data rate limits (measured in fast clocks)
383 * since those are the strictest limits we have. The fast
384 * clock and actual rate limits are more relaxed, so checking
385 * them would make no difference.
386 */
387 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
75e53986 388 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 389 .n = { .min = 1, .max = 7 },
a0c4da24
JB		 390 .m1 = { .min = 2, .max = 3 },
391 .m2 = { .min = 11, .max = 156 },
b99ab663 392 .p1 = { .min = 2, .max = 3 },
5fdc9c49 393 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
a0c4da24
JB		 394};
395
ef9348c8
CML		 396static const intel_limit_t intel_limits_chv = {
397 /*
398 * These are the data rate limits (measured in fast clocks)
399 * since those are the strictest limits we have. The fast
400 * clock and actual rate limits are more relaxed, so checking
401 * them would make no difference.
402 */
403 .dot = { .min = 25000 * 5, .max = 540000 * 5},
17fe1021 404 .vco = { .min = 4800000, .max = 6480000 },
ef9348c8
CML		 405 .n = { .min = 1, .max = 1 },
406 .m1 = { .min = 2, .max = 2 },
407 .m2 = { .min = 24 << 22, .max = 175 << 22 },
408 .p1 = { .min = 2, .max = 4 },
409 .p2 = { .p2_slow = 1, .p2_fast = 14 },
410};
411
5ab7b0b7
ID		 412static const intel_limit_t intel_limits_bxt = {
413 /* FIXME: find real dot limits */
414 .dot = { .min = 0, .max = INT_MAX },
415 .vco = { .min = 4800000, .max = 6480000 },
416 .n = { .min = 1, .max = 1 },
417 .m1 = { .min = 2, .max = 2 },
418 /* FIXME: find real m2 limits */
419 .m2 = { .min = 2 << 22, .max = 255 << 22 },
420 .p1 = { .min = 2, .max = 4 },
421 .p2 = { .p2_slow = 1, .p2_fast = 20 },
422};
423
6b4bf1c4
VS		 424static void vlv_clock(int refclk, intel_clock_t *clock)
425{
426 clock->m = clock->m1 * clock->m2;
427 clock->p = clock->p1 * clock->p2;
ed5ca77e
VS		 428 if (WARN_ON(clock->n == 0 || clock->p == 0))
429 return;
fb03ac01
VS		 430 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
431 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
6b4bf1c4
VS		 432}
433
e0638cdf
PZ		 434/**
435 * Returns whether any output on the specified pipe is of the specified type
436 */
4093561b 437bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
e0638cdf 438{
409ee761 439 struct drm_device *dev = crtc->base.dev;
e0638cdf
PZ		 440 struct intel_encoder *encoder;
441
409ee761 442 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
e0638cdf
PZ		 443 if (encoder->type == type)
444 return true;
445
446 return false;
447}
448
d0737e1d
ACO		 449/**
450 * Returns whether any output on the specified pipe will have the specified
451 * type after a staged modeset is complete, i.e., the same as
452 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
453 * encoder->crtc.
454 */
a93e255f
ACO		 455static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
456 int type)
d0737e1d 457{
a93e255f 458 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 459 struct drm_connector *connector;
a93e255f 460 struct drm_connector_state *connector_state;
d0737e1d 461 struct intel_encoder *encoder;
a93e255f
ACO		 462 int i, num_connectors = 0;
463
da3ced29 464 for_each_connector_in_state(state, connector, connector_state, i) {
a93e255f
ACO		 465 if (connector_state->crtc != crtc_state->base.crtc)
466 continue;
467
468 num_connectors++;
d0737e1d 469
a93e255f
ACO		 470 encoder = to_intel_encoder(connector_state->best_encoder);
471 if (encoder->type == type)
d0737e1d 472 return true;
a93e255f
ACO		 473 }
474
475 WARN_ON(num_connectors == 0);
d0737e1d
ACO		 476
477 return false;
478}
479
a93e255f
ACO		 480static const intel_limit_t *
481intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
2c07245f 482{
a93e255f 483 struct drm_device *dev = crtc_state->base.crtc->dev;
2c07245f 484 const intel_limit_t *limit;
b91ad0ec 485
a93e255f 486 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 487 if (intel_is_dual_link_lvds(dev)) {
1b894b59 488 if (refclk == 100000)
b91ad0ec
ZW		 489 limit = &intel_limits_ironlake_dual_lvds_100m;
490 else
491 limit = &intel_limits_ironlake_dual_lvds;
492 } else {
1b894b59 493 if (refclk == 100000)
b91ad0ec
ZW		 494 limit = &intel_limits_ironlake_single_lvds_100m;
495 else
496 limit = &intel_limits_ironlake_single_lvds;
497 }
c6bb3538 498 } else
b91ad0ec 499 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 500
501 return limit;
502}
503
a93e255f
ACO		 504static const intel_limit_t *
505intel_g4x_limit(struct intel_crtc_state *crtc_state)
044c7c41 506{
a93e255f 507 struct drm_device *dev = crtc_state->base.crtc->dev;
044c7c41
ML		 508 const intel_limit_t *limit;
509
a93e255f 510 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 511 if (intel_is_dual_link_lvds(dev))
e4b36699 512 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 513 else
e4b36699 514 limit = &intel_limits_g4x_single_channel_lvds;
a93e255f
ACO		 515 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
516 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
e4b36699 517 limit = &intel_limits_g4x_hdmi;
a93e255f 518 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
e4b36699 519 limit = &intel_limits_g4x_sdvo;
044c7c41 520 } else /* The option is for other outputs */
e4b36699 521 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 522
523 return limit;
524}
525
a93e255f
ACO		 526static const intel_limit_t *
527intel_limit(struct intel_crtc_state *crtc_state, int refclk)
79e53945 528{
a93e255f 529 struct drm_device *dev = crtc_state->base.crtc->dev;
79e53945
JB		 530 const intel_limit_t *limit;
531
5ab7b0b7
ID		 532 if (IS_BROXTON(dev))
533 limit = &intel_limits_bxt;
534 else if (HAS_PCH_SPLIT(dev))
a93e255f 535 limit = intel_ironlake_limit(crtc_state, refclk);
2c07245f 536 else if (IS_G4X(dev)) {
a93e255f 537 limit = intel_g4x_limit(crtc_state);
f2b115e6 538 } else if (IS_PINEVIEW(dev)) {
a93e255f 539 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
f2b115e6 540 limit = &intel_limits_pineview_lvds;
2177832f 541 else
f2b115e6 542 limit = &intel_limits_pineview_sdvo;
ef9348c8
CML		 543 } else if (IS_CHERRYVIEW(dev)) {
544 limit = &intel_limits_chv;
a0c4da24 545 } else if (IS_VALLEYVIEW(dev)) {
dc730512 546 limit = &intel_limits_vlv;
a6c45cf0 547 } else if (!IS_GEN2(dev)) {
a93e255f 548 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
a6c45cf0
CW		 549 limit = &intel_limits_i9xx_lvds;
550 else
551 limit = &intel_limits_i9xx_sdvo;
79e53945 552 } else {
a93e255f 553 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
e4b36699 554 limit = &intel_limits_i8xx_lvds;
a93e255f 555 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
e4b36699 556 limit = &intel_limits_i8xx_dvo;
5d536e28
DV		 557 else
558 limit = &intel_limits_i8xx_dac;
79e53945
JB		 559 }
560 return limit;
561}
562
f2b115e6
AJ		 563/* m1 is reserved as 0 in Pineview, n is a ring counter */
564static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 565{
2177832f
SL		 566 clock->m = clock->m2 + 2;
567 clock->p = clock->p1 * clock->p2;
ed5ca77e
VS		 568 if (WARN_ON(clock->n == 0 || clock->p == 0))
569 return;
fb03ac01
VS		 570 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
571 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
2177832f
SL		 572}
573
7429e9d4
DV		 574static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
575{
576 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
577}
578
ac58c3f0 579static void i9xx_clock(int refclk, intel_clock_t *clock)
2177832f 580{
7429e9d4 581 clock->m = i9xx_dpll_compute_m(clock);
79e53945 582 clock->p = clock->p1 * clock->p2;
ed5ca77e
VS		 583 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
584 return;
fb03ac01
VS		 585 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
586 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
79e53945
JB		 587}
588
ef9348c8
CML		 589static void chv_clock(int refclk, intel_clock_t *clock)
590{
591 clock->m = clock->m1 * clock->m2;
592 clock->p = clock->p1 * clock->p2;
593 if (WARN_ON(clock->n == 0 || clock->p == 0))
594 return;
595 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
596 clock->n << 22);
597 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
598}
599
7c04d1d9 600#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 601/**
602 * Returns whether the given set of divisors are valid for a given refclk with
603 * the given connectors.
604 */
605
1b894b59
CW		 606static bool intel_PLL_is_valid(struct drm_device *dev,
607 const intel_limit_t *limit,
608 const intel_clock_t *clock)
79e53945 609{
f01b7962
VS		 610 if (clock->n < limit->n.min || limit->n.max < clock->n)
611 INTELPllInvalid("n out of range\n");
79e53945 612 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 613 INTELPllInvalid("p1 out of range\n");
79e53945 614 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 615 INTELPllInvalid("m2 out of range\n");
79e53945 616 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 617 INTELPllInvalid("m1 out of range\n");
f01b7962 618
5ab7b0b7 619 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
f01b7962
VS		 620 if (clock->m1 <= clock->m2)
621 INTELPllInvalid("m1 <= m2\n");
622
5ab7b0b7 623 if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
f01b7962
VS		 624 if (clock->p < limit->p.min || limit->p.max < clock->p)
625 INTELPllInvalid("p out of range\n");
626 if (clock->m < limit->m.min || limit->m.max < clock->m)
627 INTELPllInvalid("m out of range\n");
628 }
629
79e53945 630 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 631 INTELPllInvalid("vco out of range\n");
79e53945
JB		 632 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
633 * connector, etc., rather than just a single range.
634 */
635 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 636 INTELPllInvalid("dot out of range\n");
79e53945
JB		 637
638 return true;
639}
640
d4906093 641static bool
a93e255f
ACO		 642i9xx_find_best_dpll(const intel_limit_t *limit,
643 struct intel_crtc_state *crtc_state,
cec2f356
SP		 644 int target, int refclk, intel_clock_t *match_clock,
645 intel_clock_t *best_clock)
79e53945 646{
a93e255f 647 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 648 struct drm_device *dev = crtc->base.dev;
79e53945 649 intel_clock_t clock;
79e53945
JB		 650 int err = target;
651
a93e255f 652 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
79e53945 653 /*
a210b028
DV		 654 * For LVDS just rely on its current settings for dual-channel.
655 * We haven't figured out how to reliably set up different
656 * single/dual channel state, if we even can.
79e53945 657 */
1974cad0 658 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 659 clock.p2 = limit->p2.p2_fast;
660 else
661 clock.p2 = limit->p2.p2_slow;
662 } else {
663 if (target < limit->p2.dot_limit)
664 clock.p2 = limit->p2.p2_slow;
665 else
666 clock.p2 = limit->p2.p2_fast;
667 }
668
0206e353 669 memset(best_clock, 0, sizeof(*best_clock));
79e53945 670
42158660
ZY		 671 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
672 clock.m1++) {
673 for (clock.m2 = limit->m2.min;
674 clock.m2 <= limit->m2.max; clock.m2++) {
c0efc387 675 if (clock.m2 >= clock.m1)
42158660
ZY		 676 break;
677 for (clock.n = limit->n.min;
678 clock.n <= limit->n.max; clock.n++) {
679 for (clock.p1 = limit->p1.min;
680 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 681 int this_err;
682
ac58c3f0
DV		 683 i9xx_clock(refclk, &clock);
684 if (!intel_PLL_is_valid(dev, limit,
685 &clock))
686 continue;
687 if (match_clock &&
688 clock.p != match_clock->p)
689 continue;
690
691 this_err = abs(clock.dot - target);
692 if (this_err < err) {
693 *best_clock = clock;
694 err = this_err;
695 }
696 }
697 }
698 }
699 }
700
701 return (err != target);
702}
703
704static bool
a93e255f
ACO		 705pnv_find_best_dpll(const intel_limit_t *limit,
706 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 707 int target, int refclk, intel_clock_t *match_clock,
708 intel_clock_t *best_clock)
79e53945 709{
a93e255f 710 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 711 struct drm_device *dev = crtc->base.dev;
79e53945 712 intel_clock_t clock;
79e53945
JB		 713 int err = target;
714
a93e255f 715 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
79e53945 716 /*
a210b028
DV		 717 * For LVDS just rely on its current settings for dual-channel.
718 * We haven't figured out how to reliably set up different
719 * single/dual channel state, if we even can.
79e53945 720 */
1974cad0 721 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 722 clock.p2 = limit->p2.p2_fast;
723 else
724 clock.p2 = limit->p2.p2_slow;
725 } else {
726 if (target < limit->p2.dot_limit)
727 clock.p2 = limit->p2.p2_slow;
728 else
729 clock.p2 = limit->p2.p2_fast;
730 }
731
0206e353 732 memset(best_clock, 0, sizeof(*best_clock));
79e53945 733
42158660
ZY		 734 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
735 clock.m1++) {
736 for (clock.m2 = limit->m2.min;
737 clock.m2 <= limit->m2.max; clock.m2++) {
42158660
ZY		 738 for (clock.n = limit->n.min;
739 clock.n <= limit->n.max; clock.n++) {
740 for (clock.p1 = limit->p1.min;
741 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 742 int this_err;
743
ac58c3f0 744 pineview_clock(refclk, &clock);
1b894b59
CW		 745 if (!intel_PLL_is_valid(dev, limit,
746 &clock))
79e53945 747 continue;
cec2f356
SP		 748 if (match_clock &&
749 clock.p != match_clock->p)
750 continue;
79e53945
JB		 751
752 this_err = abs(clock.dot - target);
753 if (this_err < err) {
754 *best_clock = clock;
755 err = this_err;
756 }
757 }
758 }
759 }
760 }
761
762 return (err != target);
763}
764
d4906093 765static bool
a93e255f
ACO		 766g4x_find_best_dpll(const intel_limit_t *limit,
767 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 768 int target, int refclk, intel_clock_t *match_clock,
769 intel_clock_t *best_clock)
d4906093 770{
a93e255f 771 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 772 struct drm_device *dev = crtc->base.dev;
d4906093
ML		 773 intel_clock_t clock;
774 int max_n;
775 bool found;
6ba770dc
AJ		 776 /* approximately equals target * 0.00585 */
777 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 778 found = false;
779
a93e255f 780 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 781 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 782 clock.p2 = limit->p2.p2_fast;
783 else
784 clock.p2 = limit->p2.p2_slow;
785 } else {
786 if (target < limit->p2.dot_limit)
787 clock.p2 = limit->p2.p2_slow;
788 else
789 clock.p2 = limit->p2.p2_fast;
790 }
791
792 memset(best_clock, 0, sizeof(*best_clock));
793 max_n = limit->n.max;
f77f13e2 794 /* based on hardware requirement, prefer smaller n to precision */
d4906093 795 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 796 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 797 for (clock.m1 = limit->m1.max;
798 clock.m1 >= limit->m1.min; clock.m1--) {
799 for (clock.m2 = limit->m2.max;
800 clock.m2 >= limit->m2.min; clock.m2--) {
801 for (clock.p1 = limit->p1.max;
802 clock.p1 >= limit->p1.min; clock.p1--) {
803 int this_err;
804
ac58c3f0 805 i9xx_clock(refclk, &clock);
1b894b59
CW		 806 if (!intel_PLL_is_valid(dev, limit,
807 &clock))
d4906093 808 continue;
1b894b59
CW		 809
810 this_err = abs(clock.dot - target);
d4906093
ML		 811 if (this_err < err_most) {
812 *best_clock = clock;
813 err_most = this_err;
814 max_n = clock.n;
815 found = true;
816 }
817 }
818 }
819 }
820 }
2c07245f
ZW		 821 return found;
822}
823
d5dd62bd
ID		 824/*
825 * Check if the calculated PLL configuration is more optimal compared to the
826 * best configuration and error found so far. Return the calculated error.
827 */
828static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
829 const intel_clock_t *calculated_clock,
830 const intel_clock_t *best_clock,
831 unsigned int best_error_ppm,
832 unsigned int *error_ppm)
833{
9ca3ba01
ID		 834 /*
835 * For CHV ignore the error and consider only the P value.
836 * Prefer a bigger P value based on HW requirements.
837 */
838 if (IS_CHERRYVIEW(dev)) {
839 *error_ppm = 0;
840
841 return calculated_clock->p > best_clock->p;
842 }
843
24be4e46
ID		 844 if (WARN_ON_ONCE(!target_freq))
845 return false;
846
d5dd62bd
ID		 847 *error_ppm = div_u64(1000000ULL *
848 abs(target_freq - calculated_clock->dot),
849 target_freq);
850 /*
851 * Prefer a better P value over a better (smaller) error if the error
852 * is small. Ensure this preference for future configurations too by
853 * setting the error to 0.
854 */
855 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
856 *error_ppm = 0;
857
858 return true;
859 }
860
861 return *error_ppm + 10 < best_error_ppm;
862}
863
a0c4da24 864static bool
a93e255f
ACO		 865vlv_find_best_dpll(const intel_limit_t *limit,
866 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 867 int target, int refclk, intel_clock_t *match_clock,
868 intel_clock_t *best_clock)
a0c4da24 869{
a93e255f 870 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 871 struct drm_device *dev = crtc->base.dev;
6b4bf1c4 872 intel_clock_t clock;
69e4f900 873 unsigned int bestppm = 1000000;
27e639bf
VS		 874 /* min update 19.2 MHz */
875 int max_n = min(limit->n.max, refclk / 19200);
49e497ef 876 bool found = false;
a0c4da24 877
6b4bf1c4
VS		 878 target *= 5; /* fast clock */
879
880 memset(best_clock, 0, sizeof(*best_clock));
a0c4da24
JB		 881
882 /* based on hardware requirement, prefer smaller n to precision */
27e639bf 883 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
811bbf05 884 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
889059d8 885 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
c1a9ae43 886 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
6b4bf1c4 887 clock.p = clock.p1 * clock.p2;
a0c4da24 888 /* based on hardware requirement, prefer bigger m1,m2 values */
6b4bf1c4 889 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
d5dd62bd 890 unsigned int ppm;
69e4f900 891
6b4bf1c4
VS		 892 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
893 refclk * clock.m1);
894
895 vlv_clock(refclk, &clock);
43b0ac53 896
f01b7962
VS		 897 if (!intel_PLL_is_valid(dev, limit,
898 &clock))
43b0ac53
VS		 899 continue;
900
d5dd62bd
ID		 901 if (!vlv_PLL_is_optimal(dev, target,
902 &clock,
903 best_clock,
904 bestppm, &ppm))
905 continue;
6b4bf1c4 906
d5dd62bd
ID		 907 *best_clock = clock;
908 bestppm = ppm;
909 found = true;
a0c4da24
JB		 910 }
911 }
912 }
913 }
a0c4da24 914
49e497ef 915 return found;
a0c4da24 916}
a4fc5ed6 917
ef9348c8 918static bool
a93e255f
ACO		 919chv_find_best_dpll(const intel_limit_t *limit,
920 struct intel_crtc_state *crtc_state,
ef9348c8
CML		 921 int target, int refclk, intel_clock_t *match_clock,
922 intel_clock_t *best_clock)
923{
a93e255f 924 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 925 struct drm_device *dev = crtc->base.dev;
9ca3ba01 926 unsigned int best_error_ppm;
ef9348c8
CML		 927 intel_clock_t clock;
928 uint64_t m2;
929 int found = false;
930
931 memset(best_clock, 0, sizeof(*best_clock));
9ca3ba01 932 best_error_ppm = 1000000;
ef9348c8
CML		 933
934 /*
935 * Based on hardware doc, the n always set to 1, and m1 always
936 * set to 2. If requires to support 200Mhz refclk, we need to
937 * revisit this because n may not 1 anymore.
938 */
939 clock.n = 1, clock.m1 = 2;
940 target *= 5; /* fast clock */
941
942 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
943 for (clock.p2 = limit->p2.p2_fast;
944 clock.p2 >= limit->p2.p2_slow;
945 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
9ca3ba01 946 unsigned int error_ppm;
ef9348c8
CML		 947
948 clock.p = clock.p1 * clock.p2;
949
950 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
951 clock.n) << 22, refclk * clock.m1);
952
953 if (m2 > INT_MAX/clock.m1)
954 continue;
955
956 clock.m2 = m2;
957
958 chv_clock(refclk, &clock);
959
960 if (!intel_PLL_is_valid(dev, limit, &clock))
961 continue;
962
9ca3ba01
ID		 963 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
964 best_error_ppm, &error_ppm))
965 continue;
966
967 *best_clock = clock;
968 best_error_ppm = error_ppm;
969 found = true;
ef9348c8
CML		 970 }
971 }
972
973 return found;
974}
975
5ab7b0b7
ID		 976bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
977 intel_clock_t *best_clock)
978{
979 int refclk = i9xx_get_refclk(crtc_state, 0);
980
981 return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
982 target_clock, refclk, NULL, best_clock);
983}
984
20ddf665
VS		 985bool intel_crtc_active(struct drm_crtc *crtc)
986{
987 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
988
989 /* Be paranoid as we can arrive here with only partial
990 * state retrieved from the hardware during setup.
991 *
241bfc38 992 * We can ditch the adjusted_mode.crtc_clock check as soon
20ddf665
VS		 993 * as Haswell has gained clock readout/fastboot support.
994 *
66e514c1 995 * We can ditch the crtc->primary->fb check as soon as we can
20ddf665 996 * properly reconstruct framebuffers.
c3d1f436
MR		 997 *
998 * FIXME: The intel_crtc->active here should be switched to
999 * crtc->state->active once we have proper CRTC states wired up
1000 * for atomic.
20ddf665 1001 */
c3d1f436 1002 return intel_crtc->active && crtc->primary->state->fb &&
6e3c9717 1003 intel_crtc->config->base.adjusted_mode.crtc_clock;
20ddf665
VS		 1004}
1005
a5c961d1
PZ		 1006enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1007 enum pipe pipe)
1008{
1009 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1010 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1011
6e3c9717 1012 return intel_crtc->config->cpu_transcoder;
a5c961d1
PZ		 1013}
1014
fbf49ea2
VS		 1015static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1016{
1017 struct drm_i915_private *dev_priv = dev->dev_private;
1018 u32 reg = PIPEDSL(pipe);
1019 u32 line1, line2;
1020 u32 line_mask;
1021
1022 if (IS_GEN2(dev))
1023 line_mask = DSL_LINEMASK_GEN2;
1024 else
1025 line_mask = DSL_LINEMASK_GEN3;
1026
1027 line1 = I915_READ(reg) & line_mask;
1028 mdelay(5);
1029 line2 = I915_READ(reg) & line_mask;
1030
1031 return line1 == line2;
1032}
1033
ab7ad7f6
KP		 1034/*
1035 * intel_wait_for_pipe_off - wait for pipe to turn off
575f7ab7 1036 * @crtc: crtc whose pipe to wait for
9d0498a2
JB		 1037 *
1038 * After disabling a pipe, we can't wait for vblank in the usual way,
1039 * spinning on the vblank interrupt status bit, since we won't actually
1040 * see an interrupt when the pipe is disabled.
1041 *
ab7ad7f6
KP		 1042 * On Gen4 and above:
1043 * wait for the pipe register state bit to turn off
1044 *
1045 * Otherwise:
1046 * wait for the display line value to settle (it usually
1047 * ends up stopping at the start of the next frame).
58e10eb9 1048 *
9d0498a2 1049 */
575f7ab7 1050static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
9d0498a2 1051{
575f7ab7 1052 struct drm_device *dev = crtc->base.dev;
9d0498a2 1053 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 1054 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
575f7ab7 1055 enum pipe pipe = crtc->pipe;
ab7ad7f6
KP		 1056
1057 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 1058 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 1059
1060 /* Wait for the Pipe State to go off */
58e10eb9
CW		 1061 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1062 100))
284637d9 1063 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1064 } else {
ab7ad7f6 1065 /* Wait for the display line to settle */
fbf49ea2 1066 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
284637d9 1067 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1068 }
79e53945
JB		 1069}
1070
b0ea7d37
DL		 1071/*
1072 * ibx_digital_port_connected - is the specified port connected?
1073 * @dev_priv: i915 private structure
1074 * @port: the port to test
1075 *
1076 * Returns true if @port is connected, false otherwise.
1077 */
1078bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1079 struct intel_digital_port *port)
1080{
1081 u32 bit;
1082
c36346e3 1083 if (HAS_PCH_IBX(dev_priv->dev)) {
eba905b2 1084 switch (port->port) {
c36346e3
DL		 1085 case PORT_B:
1086 bit = SDE_PORTB_HOTPLUG;
1087 break;
1088 case PORT_C:
1089 bit = SDE_PORTC_HOTPLUG;
1090 break;
1091 case PORT_D:
1092 bit = SDE_PORTD_HOTPLUG;
1093 break;
1094 default:
1095 return true;
1096 }
1097 } else {
eba905b2 1098 switch (port->port) {
c36346e3
DL		 1099 case PORT_B:
1100 bit = SDE_PORTB_HOTPLUG_CPT;
1101 break;
1102 case PORT_C:
1103 bit = SDE_PORTC_HOTPLUG_CPT;
1104 break;
1105 case PORT_D:
1106 bit = SDE_PORTD_HOTPLUG_CPT;
1107 break;
1108 default:
1109 return true;
1110 }
b0ea7d37
DL		 1111 }
1112
1113 return I915_READ(SDEISR) & bit;
1114}
1115
b24e7179
JB		 1116static const char *state_string(bool enabled)
1117{
1118 return enabled ? "on" : "off";
1119}
1120
1121/* Only for pre-ILK configs */
55607e8a
DV		 1122void assert_pll(struct drm_i915_private *dev_priv,
1123 enum pipe pipe, bool state)
b24e7179
JB		 1124{
1125 int reg;
1126 u32 val;
1127 bool cur_state;
1128
1129 reg = DPLL(pipe);
1130 val = I915_READ(reg);
1131 cur_state = !!(val & DPLL_VCO_ENABLE);
e2c719b7 1132 I915_STATE_WARN(cur_state != state,
b24e7179
JB		 1133 "PLL state assertion failure (expected %s, current %s)\n",
1134 state_string(state), state_string(cur_state));
1135}
b24e7179 1136
23538ef1
JN		 1137/* XXX: the dsi pll is shared between MIPI DSI ports */
1138static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1139{
1140 u32 val;
1141 bool cur_state;
1142
1143 mutex_lock(&dev_priv->dpio_lock);
1144 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1145 mutex_unlock(&dev_priv->dpio_lock);
1146
1147 cur_state = val & DSI_PLL_VCO_EN;
e2c719b7 1148 I915_STATE_WARN(cur_state != state,
23538ef1
JN		 1149 "DSI PLL state assertion failure (expected %s, current %s)\n",
1150 state_string(state), state_string(cur_state));
1151}
1152#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1153#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1154
55607e8a 1155struct intel_shared_dpll *
e2b78267
DV		 1156intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1157{
1158 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1159
6e3c9717 1160 if (crtc->config->shared_dpll < 0)
e2b78267
DV		 1161 return NULL;
1162
6e3c9717 1163 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
e2b78267
DV		 1164}
1165
040484af 1166/* For ILK+ */
55607e8a
DV		 1167void assert_shared_dpll(struct drm_i915_private *dev_priv,
1168 struct intel_shared_dpll *pll,
1169 bool state)
040484af 1170{
040484af 1171 bool cur_state;
5358901f 1172 struct intel_dpll_hw_state hw_state;
040484af 1173
92b27b08 1174 if (WARN (!pll,
46edb027 1175 "asserting DPLL %s with no DPLL\n", state_string(state)))
ee7b9f93 1176 return;
ee7b9f93 1177
5358901f 1178 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
e2c719b7 1179 I915_STATE_WARN(cur_state != state,
5358901f
DV		 1180 "%s assertion failure (expected %s, current %s)\n",
1181 pll->name, state_string(state), state_string(cur_state));
040484af 1182}
040484af
JB		 1183
1184static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1185 enum pipe pipe, bool state)
1186{
1187 int reg;
1188 u32 val;
1189 bool cur_state;
ad80a810
PZ		 1190 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1191 pipe);
040484af 1192
affa9354
PZ		 1193 if (HAS_DDI(dev_priv->dev)) {
1194 /* DDI does not have a specific FDI_TX register */
ad80a810 1195 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 1196 val = I915_READ(reg);
ad80a810 1197 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 1198 } else {
1199 reg = FDI_TX_CTL(pipe);
1200 val = I915_READ(reg);
1201 cur_state = !!(val & FDI_TX_ENABLE);
1202 }
e2c719b7 1203 I915_STATE_WARN(cur_state != state,
040484af
JB		 1204 "FDI TX state assertion failure (expected %s, current %s)\n",
1205 state_string(state), state_string(cur_state));
1206}
1207#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1208#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1209
1210static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1211 enum pipe pipe, bool state)
1212{
1213 int reg;
1214 u32 val;
1215 bool cur_state;
1216
d63fa0dc
PZ		 1217 reg = FDI_RX_CTL(pipe);
1218 val = I915_READ(reg);
1219 cur_state = !!(val & FDI_RX_ENABLE);
e2c719b7 1220 I915_STATE_WARN(cur_state != state,
040484af
JB		 1221 "FDI RX state assertion failure (expected %s, current %s)\n",
1222 state_string(state), state_string(cur_state));
1223}
1224#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1225#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1226
1227static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1228 enum pipe pipe)
1229{
1230 int reg;
1231 u32 val;
1232
1233 /* ILK FDI PLL is always enabled */
3d13ef2e 1234 if (INTEL_INFO(dev_priv->dev)->gen == 5)
040484af
JB		 1235 return;
1236
bf507ef7 1237 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1238 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1239 return;
1240
040484af
JB		 1241 reg = FDI_TX_CTL(pipe);
1242 val = I915_READ(reg);
e2c719b7 1243 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
040484af
JB		 1244}
1245
55607e8a
DV		 1246void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1247 enum pipe pipe, bool state)
040484af
JB		 1248{
1249 int reg;
1250 u32 val;
55607e8a 1251 bool cur_state;
040484af
JB		 1252
1253 reg = FDI_RX_CTL(pipe);
1254 val = I915_READ(reg);
55607e8a 1255 cur_state = !!(val & FDI_RX_PLL_ENABLE);
e2c719b7 1256 I915_STATE_WARN(cur_state != state,
55607e8a
DV		 1257 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1258 state_string(state), state_string(cur_state));
040484af
JB		 1259}
1260
b680c37a
DV		 1261void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1262 enum pipe pipe)
ea0760cf 1263{
bedd4dba
JN		 1264 struct drm_device *dev = dev_priv->dev;
1265 int pp_reg;
ea0760cf
JB		 1266 u32 val;
1267 enum pipe panel_pipe = PIPE_A;
0de3b485 1268 bool locked = true;
ea0760cf 1269
bedd4dba
JN		 1270 if (WARN_ON(HAS_DDI(dev)))
1271 return;
1272
1273 if (HAS_PCH_SPLIT(dev)) {
1274 u32 port_sel;
1275
ea0760cf 1276 pp_reg = PCH_PP_CONTROL;
bedd4dba
JN		 1277 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1278
1279 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1280 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1281 panel_pipe = PIPE_B;
1282 /* XXX: else fix for eDP */
1283 } else if (IS_VALLEYVIEW(dev)) {
1284 /* presumably write lock depends on pipe, not port select */
1285 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1286 panel_pipe = pipe;
ea0760cf
JB		 1287 } else {
1288 pp_reg = PP_CONTROL;
bedd4dba
JN		 1289 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1290 panel_pipe = PIPE_B;
ea0760cf
JB		 1291 }
1292
1293 val = I915_READ(pp_reg);
1294 if (!(val & PANEL_POWER_ON) ||
ec49ba2d 1295 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
ea0760cf
JB		 1296 locked = false;
1297
e2c719b7 1298 I915_STATE_WARN(panel_pipe == pipe && locked,
ea0760cf 1299 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1300 pipe_name(pipe));
ea0760cf
JB		 1301}
1302
93ce0ba6
JN		 1303static void assert_cursor(struct drm_i915_private *dev_priv,
1304 enum pipe pipe, bool state)
1305{
1306 struct drm_device *dev = dev_priv->dev;
1307 bool cur_state;
1308
d9d82081 1309 if (IS_845G(dev) || IS_I865G(dev))
93ce0ba6 1310 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
d9d82081 1311 else
5efb3e28 1312 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
93ce0ba6 1313
e2c719b7 1314 I915_STATE_WARN(cur_state != state,
93ce0ba6
JN		 1315 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1316 pipe_name(pipe), state_string(state), state_string(cur_state));
1317}
1318#define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1319#define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1320
b840d907
JB		 1321void assert_pipe(struct drm_i915_private *dev_priv,
1322 enum pipe pipe, bool state)
b24e7179
JB		 1323{
1324 int reg;
1325 u32 val;
63d7bbe9 1326 bool cur_state;
702e7a56
PZ		 1327 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1328 pipe);
b24e7179 1329
b6b5d049
VS		 1330 /* if we need the pipe quirk it must be always on */
1331 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1332 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
8e636784
DV		 1333 state = true;
1334
f458ebbc 1335 if (!intel_display_power_is_enabled(dev_priv,
b97186f0 1336 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
69310161
PZ		 1337 cur_state = false;
1338 } else {
1339 reg = PIPECONF(cpu_transcoder);
1340 val = I915_READ(reg);
1341 cur_state = !!(val & PIPECONF_ENABLE);
1342 }
1343
e2c719b7 1344 I915_STATE_WARN(cur_state != state,
63d7bbe9 1345 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1346 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1347}
1348
931872fc
CW		 1349static void assert_plane(struct drm_i915_private *dev_priv,
1350 enum plane plane, bool state)
b24e7179
JB		 1351{
1352 int reg;
1353 u32 val;
931872fc 1354 bool cur_state;
b24e7179
JB		 1355
1356 reg = DSPCNTR(plane);
1357 val = I915_READ(reg);
931872fc 1358 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
e2c719b7 1359 I915_STATE_WARN(cur_state != state,
931872fc
CW		 1360 "plane %c assertion failure (expected %s, current %s)\n",
1361 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1362}
1363
931872fc
CW		 1364#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1365#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1366
b24e7179
JB		 1367static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1368 enum pipe pipe)
1369{
653e1026 1370 struct drm_device *dev = dev_priv->dev;
b24e7179
JB		 1371 int reg, i;
1372 u32 val;
1373 int cur_pipe;
1374
653e1026
VS		 1375 /* Primary planes are fixed to pipes on gen4+ */
1376 if (INTEL_INFO(dev)->gen >= 4) {
28c05794
AJ		 1377 reg = DSPCNTR(pipe);
1378 val = I915_READ(reg);
e2c719b7 1379 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
28c05794
AJ		 1380 "plane %c assertion failure, should be disabled but not\n",
1381 plane_name(pipe));
19ec1358 1382 return;
28c05794 1383 }
19ec1358 1384
b24e7179 1385 /* Need to check both planes against the pipe */
055e393f 1386 for_each_pipe(dev_priv, i) {
b24e7179
JB		 1387 reg = DSPCNTR(i);
1388 val = I915_READ(reg);
1389 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1390 DISPPLANE_SEL_PIPE_SHIFT;
e2c719b7 1391 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1392 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1393 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1394 }
1395}
1396
19332d7a
JB		 1397static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1398 enum pipe pipe)
1399{
20674eef 1400 struct drm_device *dev = dev_priv->dev;
1fe47785 1401 int reg, sprite;
19332d7a
JB		 1402 u32 val;
1403
7feb8b88 1404 if (INTEL_INFO(dev)->gen >= 9) {
3bdcfc0c 1405 for_each_sprite(dev_priv, pipe, sprite) {
7feb8b88 1406 val = I915_READ(PLANE_CTL(pipe, sprite));
e2c719b7 1407 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
7feb8b88
DL		 1408 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1409 sprite, pipe_name(pipe));
1410 }
1411 } else if (IS_VALLEYVIEW(dev)) {
3bdcfc0c 1412 for_each_sprite(dev_priv, pipe, sprite) {
1fe47785 1413 reg = SPCNTR(pipe, sprite);
20674eef 1414 val = I915_READ(reg);
e2c719b7 1415 I915_STATE_WARN(val & SP_ENABLE,
20674eef 1416 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1fe47785 1417 sprite_name(pipe, sprite), pipe_name(pipe));
20674eef
VS		 1418 }
1419 } else if (INTEL_INFO(dev)->gen >= 7) {
1420 reg = SPRCTL(pipe);
19332d7a 1421 val = I915_READ(reg);
e2c719b7 1422 I915_STATE_WARN(val & SPRITE_ENABLE,
06da8da2 1423 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef
VS		 1424 plane_name(pipe), pipe_name(pipe));
1425 } else if (INTEL_INFO(dev)->gen >= 5) {
1426 reg = DVSCNTR(pipe);
19332d7a 1427 val = I915_READ(reg);
e2c719b7 1428 I915_STATE_WARN(val & DVS_ENABLE,
06da8da2 1429 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef 1430 plane_name(pipe), pipe_name(pipe));
19332d7a
JB		 1431 }
1432}
1433
08c71e5e
VS		 1434static void assert_vblank_disabled(struct drm_crtc *crtc)
1435{
e2c719b7 1436 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
08c71e5e
VS		 1437 drm_crtc_vblank_put(crtc);
1438}
1439
89eff4be 1440static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
92f2584a
JB		 1441{
1442 u32 val;
1443 bool enabled;
1444
e2c719b7 1445 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
9d82aa17 1446
92f2584a
JB		 1447 val = I915_READ(PCH_DREF_CONTROL);
1448 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1449 DREF_SUPERSPREAD_SOURCE_MASK));
e2c719b7 1450 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
92f2584a
JB		 1451}
1452
ab9412ba
DV		 1453static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1454 enum pipe pipe)
92f2584a
JB		 1455{
1456 int reg;
1457 u32 val;
1458 bool enabled;
1459
ab9412ba 1460 reg = PCH_TRANSCONF(pipe);
92f2584a
JB		 1461 val = I915_READ(reg);
1462 enabled = !!(val & TRANS_ENABLE);
e2c719b7 1463 I915_STATE_WARN(enabled,
9db4a9c7
JB		 1464 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1465 pipe_name(pipe));
92f2584a
JB		 1466}
1467
4e634389
KP		 1468static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1469 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1470{
1471 if ((val & DP_PORT_EN) == 0)
1472 return false;
1473
1474 if (HAS_PCH_CPT(dev_priv->dev)) {
1475 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1476 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1477 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1478 return false;
44f37d1f
CML		 1479 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1480 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1481 return false;
f0575e92
KP		 1482 } else {
1483 if ((val & DP_PIPE_MASK) != (pipe << 30))
1484 return false;
1485 }
1486 return true;
1487}
1488
1519b995
KP		 1489static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1490 enum pipe pipe, u32 val)
1491{
dc0fa718 1492 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1493 return false;
1494
1495 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1496 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995 1497 return false;
44f37d1f
CML		 1498 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1499 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1500 return false;
1519b995 1501 } else {
dc0fa718 1502 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1503 return false;
1504 }
1505 return true;
1506}
1507
1508static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1509 enum pipe pipe, u32 val)
1510{
1511 if ((val & LVDS_PORT_EN) == 0)
1512 return false;
1513
1514 if (HAS_PCH_CPT(dev_priv->dev)) {
1515 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1516 return false;
1517 } else {
1518 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1519 return false;
1520 }
1521 return true;
1522}
1523
1524static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1525 enum pipe pipe, u32 val)
1526{
1527 if ((val & ADPA_DAC_ENABLE) == 0)
1528 return false;
1529 if (HAS_PCH_CPT(dev_priv->dev)) {
1530 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1531 return false;
1532 } else {
1533 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1534 return false;
1535 }
1536 return true;
1537}
1538
291906f1 1539static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1540 enum pipe pipe, int reg, u32 port_sel)
291906f1 1541{
47a05eca 1542 u32 val = I915_READ(reg);
e2c719b7 1543 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1544 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1545 reg, pipe_name(pipe));
de9a35ab 1546
e2c719b7 1547 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
75c5da27 1548 && (val & DP_PIPEB_SELECT),
de9a35ab 1549 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1550}
1551
1552static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1553 enum pipe pipe, int reg)
1554{
47a05eca 1555 u32 val = I915_READ(reg);
e2c719b7 1556 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1557 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1558 reg, pipe_name(pipe));
de9a35ab 1559
e2c719b7 1560 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1561 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1562 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1563}
1564
1565static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1566 enum pipe pipe)
1567{
1568 int reg;
1569 u32 val;
291906f1 1570
f0575e92
KP		 1571 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1572 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1573 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1574
1575 reg = PCH_ADPA;
1576 val = I915_READ(reg);
e2c719b7 1577 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1578 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1579 pipe_name(pipe));
291906f1
JB		 1580
1581 reg = PCH_LVDS;
1582 val = I915_READ(reg);
e2c719b7 1583 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1584 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1585 pipe_name(pipe));
291906f1 1586
e2debe91
PZ		 1587 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1588 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1589 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1590}
1591
40e9cf64
JB		 1592static void intel_init_dpio(struct drm_device *dev)
1593{
1594 struct drm_i915_private *dev_priv = dev->dev_private;
1595
1596 if (!IS_VALLEYVIEW(dev))
1597 return;
1598
a09caddd
CML		 1599 /*
1600 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1601 * CHV x1 PHY (DP/HDMI D)
1602 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1603 */
1604 if (IS_CHERRYVIEW(dev)) {
1605 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1606 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1607 } else {
1608 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1609 }
5382f5f3
JB		 1610}
1611
d288f65f 1612static void vlv_enable_pll(struct intel_crtc *crtc,
5cec258b 1613 const struct intel_crtc_state *pipe_config)
87442f73 1614{
426115cf
DV		 1615 struct drm_device *dev = crtc->base.dev;
1616 struct drm_i915_private *dev_priv = dev->dev_private;
1617 int reg = DPLL(crtc->pipe);
d288f65f 1618 u32 dpll = pipe_config->dpll_hw_state.dpll;
87442f73 1619
426115cf 1620 assert_pipe_disabled(dev_priv, crtc->pipe);
87442f73
DV		 1621
1622 /* No really, not for ILK+ */
1623 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1624
1625 /* PLL is protected by panel, make sure we can write it */
6a9e7363 1626 if (IS_MOBILE(dev_priv->dev))
426115cf 1627 assert_panel_unlocked(dev_priv, crtc->pipe);
87442f73 1628
426115cf
DV		 1629 I915_WRITE(reg, dpll);
1630 POSTING_READ(reg);
1631 udelay(150);
1632
1633 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1634 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1635
d288f65f 1636 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
426115cf 1637 POSTING_READ(DPLL_MD(crtc->pipe));
87442f73
DV		 1638
1639 /* We do this three times for luck */
426115cf 1640 I915_WRITE(reg, dpll);
87442f73
DV		 1641 POSTING_READ(reg);
1642 udelay(150); /* wait for warmup */
426115cf 1643 I915_WRITE(reg, dpll);
87442f73
DV		 1644 POSTING_READ(reg);
1645 udelay(150); /* wait for warmup */
426115cf 1646 I915_WRITE(reg, dpll);
87442f73
DV		 1647 POSTING_READ(reg);
1648 udelay(150); /* wait for warmup */
1649}
1650
d288f65f 1651static void chv_enable_pll(struct intel_crtc *crtc,
5cec258b 1652 const struct intel_crtc_state *pipe_config)
9d556c99
CML		 1653{
1654 struct drm_device *dev = crtc->base.dev;
1655 struct drm_i915_private *dev_priv = dev->dev_private;
1656 int pipe = crtc->pipe;
1657 enum dpio_channel port = vlv_pipe_to_channel(pipe);
9d556c99
CML		 1658 u32 tmp;
1659
1660 assert_pipe_disabled(dev_priv, crtc->pipe);
1661
1662 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1663
1664 mutex_lock(&dev_priv->dpio_lock);
1665
1666 /* Enable back the 10bit clock to display controller */
1667 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1668 tmp |= DPIO_DCLKP_EN;
1669 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1670
1671 /*
1672 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1673 */
1674 udelay(1);
1675
1676 /* Enable PLL */
d288f65f 1677 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
9d556c99
CML		 1678
1679 /* Check PLL is locked */
a11b0703 1680 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
9d556c99
CML		 1681 DRM_ERROR("PLL %d failed to lock\n", pipe);
1682
a11b0703 1683 /* not sure when this should be written */
d288f65f 1684 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
a11b0703
VS		 1685 POSTING_READ(DPLL_MD(pipe));
1686
9d556c99
CML		 1687 mutex_unlock(&dev_priv->dpio_lock);
1688}
1689
1c4e0274
VS		 1690static int intel_num_dvo_pipes(struct drm_device *dev)
1691{
1692 struct intel_crtc *crtc;
1693 int count = 0;
1694
1695 for_each_intel_crtc(dev, crtc)
1696 count += crtc->active &&
409ee761 1697 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1c4e0274
VS		 1698
1699 return count;
1700}
1701
66e3d5c0 1702static void i9xx_enable_pll(struct intel_crtc *crtc)
63d7bbe9 1703{
66e3d5c0
DV		 1704 struct drm_device *dev = crtc->base.dev;
1705 struct drm_i915_private *dev_priv = dev->dev_private;
1706 int reg = DPLL(crtc->pipe);
6e3c9717 1707 u32 dpll = crtc->config->dpll_hw_state.dpll;
63d7bbe9 1708
66e3d5c0 1709 assert_pipe_disabled(dev_priv, crtc->pipe);
58c6eaa2 1710
63d7bbe9 1711 /* No really, not for ILK+ */
3d13ef2e 1712 BUG_ON(INTEL_INFO(dev)->gen >= 5);
63d7bbe9
JB		 1713
1714 /* PLL is protected by panel, make sure we can write it */
66e3d5c0
DV		 1715 if (IS_MOBILE(dev) && !IS_I830(dev))
1716 assert_panel_unlocked(dev_priv, crtc->pipe);
63d7bbe9 1717
1c4e0274
VS		 1718 /* Enable DVO 2x clock on both PLLs if necessary */
1719 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1720 /*
1721 * It appears to be important that we don't enable this
1722 * for the current pipe before otherwise configuring the
1723 * PLL. No idea how this should be handled if multiple
1724 * DVO outputs are enabled simultaneosly.
1725 */
1726 dpll |= DPLL_DVO_2X_MODE;
1727 I915_WRITE(DPLL(!crtc->pipe),
1728 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1729 }
66e3d5c0
DV		 1730
1731 /* Wait for the clocks to stabilize. */
1732 POSTING_READ(reg);
1733 udelay(150);
1734
1735 if (INTEL_INFO(dev)->gen >= 4) {
1736 I915_WRITE(DPLL_MD(crtc->pipe),
6e3c9717 1737 crtc->config->dpll_hw_state.dpll_md);
66e3d5c0
DV		 1738 } else {
1739 /* The pixel multiplier can only be updated once the
1740 * DPLL is enabled and the clocks are stable.
1741 *
1742 * So write it again.
1743 */
1744 I915_WRITE(reg, dpll);
1745 }
63d7bbe9
JB		 1746
1747 /* We do this three times for luck */
66e3d5c0 1748 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1749 POSTING_READ(reg);
1750 udelay(150); /* wait for warmup */
66e3d5c0 1751 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1752 POSTING_READ(reg);
1753 udelay(150); /* wait for warmup */
66e3d5c0 1754 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1755 POSTING_READ(reg);
1756 udelay(150); /* wait for warmup */
1757}
1758
1759/**
50b44a44 1760 * i9xx_disable_pll - disable a PLL
63d7bbe9
JB		 1761 * @dev_priv: i915 private structure
1762 * @pipe: pipe PLL to disable
1763 *
1764 * Disable the PLL for @pipe, making sure the pipe is off first.
1765 *
1766 * Note! This is for pre-ILK only.
1767 */
1c4e0274 1768static void i9xx_disable_pll(struct intel_crtc *crtc)
63d7bbe9 1769{
1c4e0274
VS		 1770 struct drm_device *dev = crtc->base.dev;
1771 struct drm_i915_private *dev_priv = dev->dev_private;
1772 enum pipe pipe = crtc->pipe;
1773
1774 /* Disable DVO 2x clock on both PLLs if necessary */
1775 if (IS_I830(dev) &&
409ee761 1776 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1c4e0274
VS		 1777 intel_num_dvo_pipes(dev) == 1) {
1778 I915_WRITE(DPLL(PIPE_B),
1779 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1780 I915_WRITE(DPLL(PIPE_A),
1781 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1782 }
1783
b6b5d049
VS		 1784 /* Don't disable pipe or pipe PLLs if needed */
1785 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1786 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
63d7bbe9
JB		 1787 return;
1788
1789 /* Make sure the pipe isn't still relying on us */
1790 assert_pipe_disabled(dev_priv, pipe);
1791
50b44a44
DV		 1792 I915_WRITE(DPLL(pipe), 0);
1793 POSTING_READ(DPLL(pipe));
63d7bbe9
JB		 1794}
1795
f6071166
JB		 1796static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1797{
1798 u32 val = 0;
1799
1800 /* Make sure the pipe isn't still relying on us */
1801 assert_pipe_disabled(dev_priv, pipe);
1802
e5cbfbfb
ID		 1803 /*
1804 * Leave integrated clock source and reference clock enabled for pipe B.
1805 * The latter is needed for VGA hotplug / manual detection.
1806 */
f6071166 1807 if (pipe == PIPE_B)
e5cbfbfb 1808 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
f6071166
JB		 1809 I915_WRITE(DPLL(pipe), val);
1810 POSTING_READ(DPLL(pipe));
076ed3b2
CML		 1811
1812}
1813
1814static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1815{
d752048d 1816 enum dpio_channel port = vlv_pipe_to_channel(pipe);
076ed3b2
CML		 1817 u32 val;
1818
a11b0703
VS		 1819 /* Make sure the pipe isn't still relying on us */
1820 assert_pipe_disabled(dev_priv, pipe);
076ed3b2 1821
a11b0703 1822 /* Set PLL en = 0 */
d17ec4ce 1823 val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
a11b0703
VS		 1824 if (pipe != PIPE_A)
1825 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1826 I915_WRITE(DPLL(pipe), val);
1827 POSTING_READ(DPLL(pipe));
d752048d
VS		 1828
1829 mutex_lock(&dev_priv->dpio_lock);
1830
1831 /* Disable 10bit clock to display controller */
1832 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1833 val &= ~DPIO_DCLKP_EN;
1834 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1835
61407f6d
VS		 1836 /* disable left/right clock distribution */
1837 if (pipe != PIPE_B) {
1838 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1839 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1840 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1841 } else {
1842 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1843 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1844 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1845 }
1846
d752048d 1847 mutex_unlock(&dev_priv->dpio_lock);
f6071166
JB		 1848}
1849
e4607fcf 1850void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
9b6de0a1
VS		 1851 struct intel_digital_port *dport,
1852 unsigned int expected_mask)
89b667f8
JB		 1853{
1854 u32 port_mask;
00fc31b7 1855 int dpll_reg;
89b667f8 1856
e4607fcf
CML		 1857 switch (dport->port) {
1858 case PORT_B:
89b667f8 1859 port_mask = DPLL_PORTB_READY_MASK;
00fc31b7 1860 dpll_reg = DPLL(0);
e4607fcf
CML		 1861 break;
1862 case PORT_C:
89b667f8 1863 port_mask = DPLL_PORTC_READY_MASK;
00fc31b7 1864 dpll_reg = DPLL(0);
9b6de0a1 1865 expected_mask <<= 4;
00fc31b7
CML		 1866 break;
1867 case PORT_D:
1868 port_mask = DPLL_PORTD_READY_MASK;
1869 dpll_reg = DPIO_PHY_STATUS;
e4607fcf
CML		 1870 break;
1871 default:
1872 BUG();
1873 }
89b667f8 1874
9b6de0a1
VS		 1875 if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1876 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1877 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
89b667f8
JB		 1878}
1879
b14b1055
DV		 1880static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1881{
1882 struct drm_device *dev = crtc->base.dev;
1883 struct drm_i915_private *dev_priv = dev->dev_private;
1884 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1885
be19f0ff
CW		 1886 if (WARN_ON(pll == NULL))
1887 return;
1888
3e369b76 1889 WARN_ON(!pll->config.crtc_mask);
b14b1055
DV		 1890 if (pll->active == 0) {
1891 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1892 WARN_ON(pll->on);
1893 assert_shared_dpll_disabled(dev_priv, pll);
1894
1895 pll->mode_set(dev_priv, pll);
1896 }
1897}
1898
92f2584a 1899/**
85b3894f 1900 * intel_enable_shared_dpll - enable PCH PLL
92f2584a
JB		 1901 * @dev_priv: i915 private structure
1902 * @pipe: pipe PLL to enable
1903 *
1904 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1905 * drives the transcoder clock.
1906 */
85b3894f 1907static void intel_enable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1908{
3d13ef2e
DL		 1909 struct drm_device *dev = crtc->base.dev;
1910 struct drm_i915_private *dev_priv = dev->dev_private;
e2b78267 1911 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
92f2584a 1912
87a875bb 1913 if (WARN_ON(pll == NULL))
48da64a8
CW		 1914 return;
1915
3e369b76 1916 if (WARN_ON(pll->config.crtc_mask == 0))
48da64a8 1917 return;
ee7b9f93 1918
74dd6928 1919 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
46edb027 1920 pll->name, pll->active, pll->on,
e2b78267 1921 crtc->base.base.id);
92f2584a 1922
cdbd2316
DV		 1923 if (pll->active++) {
1924 WARN_ON(!pll->on);
e9d6944e 1925 assert_shared_dpll_enabled(dev_priv, pll);
ee7b9f93
JB		 1926 return;
1927 }
f4a091c7 1928 WARN_ON(pll->on);
ee7b9f93 1929
bd2bb1b9
PZ		 1930 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1931
46edb027 1932 DRM_DEBUG_KMS("enabling %s\n", pll->name);
e7b903d2 1933 pll->enable(dev_priv, pll);
ee7b9f93 1934 pll->on = true;
92f2584a
JB		 1935}
1936
f6daaec2 1937static void intel_disable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1938{
3d13ef2e
DL		 1939 struct drm_device *dev = crtc->base.dev;
1940 struct drm_i915_private *dev_priv = dev->dev_private;
e2b78267 1941 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4c609cb8 1942
92f2584a 1943 /* PCH only available on ILK+ */
3d13ef2e 1944 BUG_ON(INTEL_INFO(dev)->gen < 5);
87a875bb 1945 if (WARN_ON(pll == NULL))
ee7b9f93 1946 return;
92f2584a 1947
3e369b76 1948 if (WARN_ON(pll->config.crtc_mask == 0))
48da64a8 1949 return;
7a419866 1950
46edb027
DV		 1951 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1952 pll->name, pll->active, pll->on,
e2b78267 1953 crtc->base.base.id);
7a419866 1954
48da64a8 1955 if (WARN_ON(pll->active == 0)) {
e9d6944e 1956 assert_shared_dpll_disabled(dev_priv, pll);
48da64a8
CW		 1957 return;
1958 }
1959
e9d6944e 1960 assert_shared_dpll_enabled(dev_priv, pll);
f4a091c7 1961 WARN_ON(!pll->on);
cdbd2316 1962 if (--pll->active)
7a419866 1963 return;
ee7b9f93 1964
46edb027 1965 DRM_DEBUG_KMS("disabling %s\n", pll->name);
e7b903d2 1966 pll->disable(dev_priv, pll);
ee7b9f93 1967 pll->on = false;
bd2bb1b9
PZ		 1968
1969 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
92f2584a
JB		 1970}
1971
b8a4f404
PZ		 1972static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1973 enum pipe pipe)
040484af 1974{
23670b32 1975 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1976 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
e2b78267 1977 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
23670b32 1978 uint32_t reg, val, pipeconf_val;
040484af
JB		 1979
1980 /* PCH only available on ILK+ */
55522f37 1981 BUG_ON(!HAS_PCH_SPLIT(dev));
040484af
JB		 1982
1983 /* Make sure PCH DPLL is enabled */
e72f9fbf 1984 assert_shared_dpll_enabled(dev_priv,
e9d6944e 1985 intel_crtc_to_shared_dpll(intel_crtc));
040484af
JB		 1986
1987 /* FDI must be feeding us bits for PCH ports */
1988 assert_fdi_tx_enabled(dev_priv, pipe);
1989 assert_fdi_rx_enabled(dev_priv, pipe);
1990
23670b32
DV		 1991 if (HAS_PCH_CPT(dev)) {
1992 /* Workaround: Set the timing override bit before enabling the
1993 * pch transcoder. */
1994 reg = TRANS_CHICKEN2(pipe);
1995 val = I915_READ(reg);
1996 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1997 I915_WRITE(reg, val);
59c859d6 1998 }
23670b32 1999
ab9412ba 2000 reg = PCH_TRANSCONF(pipe);
040484af 2001 val = I915_READ(reg);
5f7f726d 2002 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 2003
2004 if (HAS_PCH_IBX(dev_priv->dev)) {
2005 /*
2006 * make the BPC in transcoder be consistent with
2007 * that in pipeconf reg.
2008 */
dfd07d72
DV		 2009 val &= ~PIPECONF_BPC_MASK;
2010 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 2011 }
5f7f726d
PZ		 2012
2013 val &= ~TRANS_INTERLACE_MASK;
2014 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6 2015 if (HAS_PCH_IBX(dev_priv->dev) &&
409ee761 2016 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7c26e5c6
PZ		 2017 val |= TRANS_LEGACY_INTERLACED_ILK;
2018 else
2019 val |= TRANS_INTERLACED;
5f7f726d
PZ		 2020 else
2021 val |= TRANS_PROGRESSIVE;
2022
040484af
JB		 2023 I915_WRITE(reg, val | TRANS_ENABLE);
2024 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 2025 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 2026}
2027
8fb033d7 2028static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 2029 enum transcoder cpu_transcoder)
040484af 2030{
8fb033d7 2031 u32 val, pipeconf_val;
8fb033d7
PZ		 2032
2033 /* PCH only available on ILK+ */
55522f37 2034 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
8fb033d7 2035
8fb033d7 2036 /* FDI must be feeding us bits for PCH ports */
1a240d4d 2037 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 2038 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 2039
223a6fdf
PZ		 2040 /* Workaround: set timing override bit. */
2041 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 2042 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 2043 I915_WRITE(_TRANSA_CHICKEN2, val);
2044
25f3ef11 2045 val = TRANS_ENABLE;
937bb610 2046 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 2047
9a76b1c6
PZ		 2048 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2049 PIPECONF_INTERLACED_ILK)
a35f2679 2050 val |= TRANS_INTERLACED;
8fb033d7
PZ		 2051 else
2052 val |= TRANS_PROGRESSIVE;
2053
ab9412ba
DV		 2054 I915_WRITE(LPT_TRANSCONF, val);
2055 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
937bb610 2056 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 2057}
2058
b8a4f404
PZ		 2059static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2060 enum pipe pipe)
040484af 2061{
23670b32
DV		 2062 struct drm_device *dev = dev_priv->dev;
2063 uint32_t reg, val;
040484af
JB		 2064
2065 /* FDI relies on the transcoder */
2066 assert_fdi_tx_disabled(dev_priv, pipe);
2067 assert_fdi_rx_disabled(dev_priv, pipe);
2068
291906f1
JB		 2069 /* Ports must be off as well */
2070 assert_pch_ports_disabled(dev_priv, pipe);
2071
ab9412ba 2072 reg = PCH_TRANSCONF(pipe);
040484af
JB		 2073 val = I915_READ(reg);
2074 val &= ~TRANS_ENABLE;
2075 I915_WRITE(reg, val);
2076 /* wait for PCH transcoder off, transcoder state */
2077 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 2078 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV		 2079
2080 if (!HAS_PCH_IBX(dev)) {
2081 /* Workaround: Clear the timing override chicken bit again. */
2082 reg = TRANS_CHICKEN2(pipe);
2083 val = I915_READ(reg);
2084 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2085 I915_WRITE(reg, val);
2086 }
040484af
JB		 2087}
2088
ab4d966c 2089static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 2090{
8fb033d7
PZ		 2091 u32 val;
2092
ab9412ba 2093 val = I915_READ(LPT_TRANSCONF);
8fb033d7 2094 val &= ~TRANS_ENABLE;
ab9412ba 2095 I915_WRITE(LPT_TRANSCONF, val);
8fb033d7 2096 /* wait for PCH transcoder off, transcoder state */
ab9412ba 2097 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
8a52fd9f 2098 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 2099
2100 /* Workaround: clear timing override bit. */
2101 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 2102 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 2103 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 2104}
2105
b24e7179 2106/**
309cfea8 2107 * intel_enable_pipe - enable a pipe, asserting requirements
0372264a 2108 * @crtc: crtc responsible for the pipe
b24e7179 2109 *
0372264a 2110 * Enable @crtc's pipe, making sure that various hardware specific requirements
b24e7179 2111 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
b24e7179 2112 */
e1fdc473 2113static void intel_enable_pipe(struct intel_crtc *crtc)
b24e7179 2114{
0372264a
PZ		 2115 struct drm_device *dev = crtc->base.dev;
2116 struct drm_i915_private *dev_priv = dev->dev_private;
2117 enum pipe pipe = crtc->pipe;
702e7a56
PZ		 2118 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2119 pipe);
1a240d4d 2120 enum pipe pch_transcoder;
b24e7179
JB		 2121 int reg;
2122 u32 val;
2123
58c6eaa2 2124 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 2125 assert_cursor_disabled(dev_priv, pipe);
58c6eaa2
DV		 2126 assert_sprites_disabled(dev_priv, pipe);
2127
681e5811 2128 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 2129 pch_transcoder = TRANSCODER_A;
2130 else
2131 pch_transcoder = pipe;
2132
b24e7179
JB		 2133 /*
2134 * A pipe without a PLL won't actually be able to drive bits from
2135 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2136 * need the check.
2137 */
50360403 2138 if (HAS_GMCH_DISPLAY(dev_priv->dev))
409ee761 2139 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
23538ef1
JN		 2140 assert_dsi_pll_enabled(dev_priv);
2141 else
2142 assert_pll_enabled(dev_priv, pipe);
040484af 2143 else {
6e3c9717 2144 if (crtc->config->has_pch_encoder) {
040484af 2145 /* if driving the PCH, we need FDI enabled */
cc391bbb 2146 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 2147 assert_fdi_tx_pll_enabled(dev_priv,
2148 (enum pipe) cpu_transcoder);
040484af
JB		 2149 }
2150 /* FIXME: assert CPU port conditions for SNB+ */
2151 }
b24e7179 2152
702e7a56 2153 reg = PIPECONF(cpu_transcoder);
b24e7179 2154 val = I915_READ(reg);
7ad25d48 2155 if (val & PIPECONF_ENABLE) {
b6b5d049
VS		 2156 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2157 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
00d70b15 2158 return;
7ad25d48 2159 }
00d70b15
CW		 2160
2161 I915_WRITE(reg, val | PIPECONF_ENABLE);
851855d8 2162 POSTING_READ(reg);
b24e7179
JB		 2163}
2164
2165/**
309cfea8 2166 * intel_disable_pipe - disable a pipe, asserting requirements
575f7ab7 2167 * @crtc: crtc whose pipes is to be disabled
b24e7179 2168 *
575f7ab7
VS		 2169 * Disable the pipe of @crtc, making sure that various hardware
2170 * specific requirements are met, if applicable, e.g. plane
2171 * disabled, panel fitter off, etc.
b24e7179
JB		 2172 *
2173 * Will wait until the pipe has shut down before returning.
2174 */
575f7ab7 2175static void intel_disable_pipe(struct intel_crtc *crtc)
b24e7179 2176{
575f7ab7 2177 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
6e3c9717 2178 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
575f7ab7 2179 enum pipe pipe = crtc->pipe;
b24e7179
JB		 2180 int reg;
2181 u32 val;
2182
2183 /*
2184 * Make sure planes won't keep trying to pump pixels to us,
2185 * or we might hang the display.
2186 */
2187 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 2188 assert_cursor_disabled(dev_priv, pipe);
19332d7a 2189 assert_sprites_disabled(dev_priv, pipe);
b24e7179 2190
702e7a56 2191 reg = PIPECONF(cpu_transcoder);
b24e7179 2192 val = I915_READ(reg);
00d70b15
CW		 2193 if ((val & PIPECONF_ENABLE) == 0)
2194 return;
2195
67adc644
VS		 2196 /*
2197 * Double wide has implications for planes
2198 * so best keep it disabled when not needed.
2199 */
6e3c9717 2200 if (crtc->config->double_wide)
67adc644
VS		 2201 val &= ~PIPECONF_DOUBLE_WIDE;
2202
2203 /* Don't disable pipe or pipe PLLs if needed */
b6b5d049
VS		 2204 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2205 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
67adc644
VS		 2206 val &= ~PIPECONF_ENABLE;
2207
2208 I915_WRITE(reg, val);
2209 if ((val & PIPECONF_ENABLE) == 0)
2210 intel_wait_for_pipe_off(crtc);
b24e7179
JB		 2211}
2212
d74362c9
KP		 2213/*
2214 * Plane regs are double buffered, going from enabled->disabled needs a
2215 * trigger in order to latch. The display address reg provides this.
2216 */
1dba99f4
VS		 2217void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2218 enum plane plane)
d74362c9 2219{
3d13ef2e
DL		 2220 struct drm_device *dev = dev_priv->dev;
2221 u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
1dba99f4
VS		 2222
2223 I915_WRITE(reg, I915_READ(reg));
2224 POSTING_READ(reg);
d74362c9
KP		 2225}
2226
b24e7179 2227/**
262ca2b0 2228 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
fdd508a6
VS		 2229 * @plane: plane to be enabled
2230 * @crtc: crtc for the plane
b24e7179 2231 *
fdd508a6 2232 * Enable @plane on @crtc, making sure that the pipe is running first.
b24e7179 2233 */
fdd508a6
VS		 2234static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2235 struct drm_crtc *crtc)
b24e7179 2236{
fdd508a6
VS		 2237 struct drm_device *dev = plane->dev;
2238 struct drm_i915_private *dev_priv = dev->dev_private;
2239 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b24e7179
JB		 2240
2241 /* If the pipe isn't enabled, we can't pump pixels and may hang */
fdd508a6 2242 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
b70709a6 2243 to_intel_plane_state(plane->state)->visible = true;
939c2fe8 2244
fdd508a6
VS		 2245 dev_priv->display.update_primary_plane(crtc, plane->fb,
2246 crtc->x, crtc->y);
b24e7179
JB		 2247}
2248
693db184
CW		 2249static bool need_vtd_wa(struct drm_device *dev)
2250{
2251#ifdef CONFIG_INTEL_IOMMU
2252 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2253 return true;
2254#endif
2255 return false;
2256}
2257
50470bb0 2258unsigned int
6761dd31
TU		 2259intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2260 uint64_t fb_format_modifier)
a57ce0b2 2261{
6761dd31
TU		 2262 unsigned int tile_height;
2263 uint32_t pixel_bytes;
a57ce0b2 2264
b5d0e9bf
DL		 2265 switch (fb_format_modifier) {
2266 case DRM_FORMAT_MOD_NONE:
2267 tile_height = 1;
2268 break;
2269 case I915_FORMAT_MOD_X_TILED:
2270 tile_height = IS_GEN2(dev) ? 16 : 8;
2271 break;
2272 case I915_FORMAT_MOD_Y_TILED:
2273 tile_height = 32;
2274 break;
2275 case I915_FORMAT_MOD_Yf_TILED:
6761dd31
TU		 2276 pixel_bytes = drm_format_plane_cpp(pixel_format, 0);
2277 switch (pixel_bytes) {
b5d0e9bf 2278 default:
6761dd31 2279 case 1:
b5d0e9bf
DL		 2280 tile_height = 64;
2281 break;
6761dd31
TU		 2282 case 2:
2283 case 4:
b5d0e9bf
DL		 2284 tile_height = 32;
2285 break;
6761dd31 2286 case 8:
b5d0e9bf
DL		 2287 tile_height = 16;
2288 break;
6761dd31 2289 case 16:
b5d0e9bf
DL		 2290 WARN_ONCE(1,
2291 "128-bit pixels are not supported for display!");
2292 tile_height = 16;
2293 break;
2294 }
2295 break;
2296 default:
2297 MISSING_CASE(fb_format_modifier);
2298 tile_height = 1;
2299 break;
2300 }
091df6cb 2301
6761dd31
TU		 2302 return tile_height;
2303}
2304
2305unsigned int
2306intel_fb_align_height(struct drm_device *dev, unsigned int height,
2307 uint32_t pixel_format, uint64_t fb_format_modifier)
2308{
2309 return ALIGN(height, intel_tile_height(dev, pixel_format,
2310 fb_format_modifier));
a57ce0b2
JB		 2311}
2312
f64b98cd
TU		 2313static int
2314intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2315 const struct drm_plane_state *plane_state)
2316{
50470bb0 2317 struct intel_rotation_info *info = &view->rotation_info;
50470bb0 2318
f64b98cd
TU		 2319 *view = i915_ggtt_view_normal;
2320
50470bb0
TU		 2321 if (!plane_state)
2322 return 0;
2323
121920fa 2324 if (!intel_rotation_90_or_270(plane_state->rotation))
50470bb0
TU		 2325 return 0;
2326
9abc4648 2327 *view = i915_ggtt_view_rotated;
50470bb0
TU		 2328
2329 info->height = fb->height;
2330 info->pixel_format = fb->pixel_format;
2331 info->pitch = fb->pitches[0];
2332 info->fb_modifier = fb->modifier[0];
2333
f64b98cd
TU		 2334 return 0;
2335}
2336
127bd2ac 2337int
850c4cdc
TU		 2338intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2339 struct drm_framebuffer *fb,
82bc3b2d 2340 const struct drm_plane_state *plane_state,
a4872ba6 2341 struct intel_engine_cs *pipelined)
6b95a207 2342{
850c4cdc 2343 struct drm_device *dev = fb->dev;
ce453d81 2344 struct drm_i915_private *dev_priv = dev->dev_private;
850c4cdc 2345 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
f64b98cd 2346 struct i915_ggtt_view view;
6b95a207
KH		 2347 u32 alignment;
2348 int ret;
2349
ebcdd39e
MR		 2350 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2351
7b911adc
TU		 2352 switch (fb->modifier[0]) {
2353 case DRM_FORMAT_MOD_NONE:
1fada4cc
DL		 2354 if (INTEL_INFO(dev)->gen >= 9)
2355 alignment = 256 * 1024;
2356 else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
534843da 2357 alignment = 128 * 1024;
a6c45cf0 2358 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 2359 alignment = 4 * 1024;
2360 else
2361 alignment = 64 * 1024;
6b95a207 2362 break;
7b911adc 2363 case I915_FORMAT_MOD_X_TILED:
1fada4cc
DL		 2364 if (INTEL_INFO(dev)->gen >= 9)
2365 alignment = 256 * 1024;
2366 else {
2367 /* pin() will align the object as required by fence */
2368 alignment = 0;
2369 }
6b95a207 2370 break;
7b911adc 2371 case I915_FORMAT_MOD_Y_TILED:
1327b9a1
DL		 2372 case I915_FORMAT_MOD_Yf_TILED:
2373 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2374 "Y tiling bo slipped through, driver bug!\n"))
2375 return -EINVAL;
2376 alignment = 1 * 1024 * 1024;
2377 break;
6b95a207 2378 default:
7b911adc
TU		 2379 MISSING_CASE(fb->modifier[0]);
2380 return -EINVAL;
6b95a207
KH		 2381 }
2382
f64b98cd
TU		 2383 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2384 if (ret)
2385 return ret;
2386
693db184
CW		 2387 /* Note that the w/a also requires 64 PTE of padding following the
2388 * bo. We currently fill all unused PTE with the shadow page and so
2389 * we should always have valid PTE following the scanout preventing
2390 * the VT-d warning.
2391 */
2392 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2393 alignment = 256 * 1024;
2394
d6dd6843
PZ		 2395 /*
2396 * Global gtt pte registers are special registers which actually forward
2397 * writes to a chunk of system memory. Which means that there is no risk
2398 * that the register values disappear as soon as we call
2399 * intel_runtime_pm_put(), so it is correct to wrap only the
2400 * pin/unpin/fence and not more.
2401 */
2402 intel_runtime_pm_get(dev_priv);
2403
ce453d81 2404 dev_priv->mm.interruptible = false;
e6617330 2405 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
f64b98cd 2406 &view);
48b956c5 2407 if (ret)
ce453d81 2408 goto err_interruptible;
6b95a207
KH		 2409
2410 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2411 * fence, whereas 965+ only requires a fence if using
2412 * framebuffer compression. For simplicity, we always install
2413 * a fence as the cost is not that onerous.
2414 */
06d98131 2415 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 2416 if (ret)
2417 goto err_unpin;
1690e1eb 2418
9a5a53b3 2419 i915_gem_object_pin_fence(obj);
6b95a207 2420
ce453d81 2421 dev_priv->mm.interruptible = true;
d6dd6843 2422 intel_runtime_pm_put(dev_priv);
6b95a207 2423 return 0;
48b956c5
CW		 2424
2425err_unpin:
f64b98cd 2426 i915_gem_object_unpin_from_display_plane(obj, &view);
ce453d81
CW		 2427err_interruptible:
2428 dev_priv->mm.interruptible = true;
d6dd6843 2429 intel_runtime_pm_put(dev_priv);
48b956c5 2430 return ret;
6b95a207
KH		 2431}
2432
82bc3b2d
TU		 2433static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2434 const struct drm_plane_state *plane_state)
1690e1eb 2435{
82bc3b2d 2436 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
f64b98cd
TU		 2437 struct i915_ggtt_view view;
2438 int ret;
82bc3b2d 2439
ebcdd39e
MR		 2440 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2441
f64b98cd
TU		 2442 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2443 WARN_ONCE(ret, "Couldn't get view from plane state!");
2444
1690e1eb 2445 i915_gem_object_unpin_fence(obj);
f64b98cd 2446 i915_gem_object_unpin_from_display_plane(obj, &view);
1690e1eb
CW		 2447}
2448
c2c75131
DV		 2449/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2450 * is assumed to be a power-of-two. */
bc752862
CW		 2451unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2452 unsigned int tiling_mode,
2453 unsigned int cpp,
2454 unsigned int pitch)
c2c75131 2455{
bc752862
CW		 2456 if (tiling_mode != I915_TILING_NONE) {
2457 unsigned int tile_rows, tiles;
c2c75131 2458
bc752862
CW		 2459 tile_rows = *y / 8;
2460 *y %= 8;
c2c75131 2461
bc752862
CW		 2462 tiles = *x / (512/cpp);
2463 *x %= 512/cpp;
2464
2465 return tile_rows * pitch * 8 + tiles * 4096;
2466 } else {
2467 unsigned int offset;
2468
2469 offset = *y * pitch + *x * cpp;
2470 *y = 0;
2471 *x = (offset & 4095) / cpp;
2472 return offset & -4096;
2473 }
c2c75131
DV		 2474}
2475
b35d63fa 2476static int i9xx_format_to_fourcc(int format)
46f297fb
JB		 2477{
2478 switch (format) {
2479 case DISPPLANE_8BPP:
2480 return DRM_FORMAT_C8;
2481 case DISPPLANE_BGRX555:
2482 return DRM_FORMAT_XRGB1555;
2483 case DISPPLANE_BGRX565:
2484 return DRM_FORMAT_RGB565;
2485 default:
2486 case DISPPLANE_BGRX888:
2487 return DRM_FORMAT_XRGB8888;
2488 case DISPPLANE_RGBX888:
2489 return DRM_FORMAT_XBGR8888;
2490 case DISPPLANE_BGRX101010:
2491 return DRM_FORMAT_XRGB2101010;
2492 case DISPPLANE_RGBX101010:
2493 return DRM_FORMAT_XBGR2101010;
2494 }
2495}
2496
bc8d7dff
DL		 2497static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2498{
2499 switch (format) {
2500 case PLANE_CTL_FORMAT_RGB_565:
2501 return DRM_FORMAT_RGB565;
2502 default:
2503 case PLANE_CTL_FORMAT_XRGB_8888:
2504 if (rgb_order) {
2505 if (alpha)
2506 return DRM_FORMAT_ABGR8888;
2507 else
2508 return DRM_FORMAT_XBGR8888;
2509 } else {
2510 if (alpha)
2511 return DRM_FORMAT_ARGB8888;
2512 else
2513 return DRM_FORMAT_XRGB8888;
2514 }
2515 case PLANE_CTL_FORMAT_XRGB_2101010:
2516 if (rgb_order)
2517 return DRM_FORMAT_XBGR2101010;
2518 else
2519 return DRM_FORMAT_XRGB2101010;
2520 }
2521}
2522
5724dbd1 2523static bool
f6936e29
DV		 2524intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2525 struct intel_initial_plane_config *plane_config)
46f297fb
JB		 2526{
2527 struct drm_device *dev = crtc->base.dev;
2528 struct drm_i915_gem_object *obj = NULL;
2529 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2d14030b 2530 struct drm_framebuffer *fb = &plane_config->fb->base;
f37b5c2b
DV		 2531 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2532 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2533 PAGE_SIZE);
2534
2535 size_aligned -= base_aligned;
46f297fb 2536
ff2652ea
CW		 2537 if (plane_config->size == 0)
2538 return false;
2539
f37b5c2b
DV		 2540 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2541 base_aligned,
2542 base_aligned,
2543 size_aligned);
46f297fb 2544 if (!obj)
484b41dd 2545 return false;
46f297fb 2546
49af449b
DL		 2547 obj->tiling_mode = plane_config->tiling;
2548 if (obj->tiling_mode == I915_TILING_X)
6bf129df 2549 obj->stride = fb->pitches[0];
46f297fb 2550
6bf129df
DL		 2551 mode_cmd.pixel_format = fb->pixel_format;
2552 mode_cmd.width = fb->width;
2553 mode_cmd.height = fb->height;
2554 mode_cmd.pitches[0] = fb->pitches[0];
18c5247e
DV		 2555 mode_cmd.modifier[0] = fb->modifier[0];
2556 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
46f297fb
JB		 2557
2558 mutex_lock(&dev->struct_mutex);
6bf129df 2559 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
484b41dd 2560 &mode_cmd, obj)) {
46f297fb
JB		 2561 DRM_DEBUG_KMS("intel fb init failed\n");
2562 goto out_unref_obj;
2563 }
46f297fb 2564 mutex_unlock(&dev->struct_mutex);
484b41dd 2565
f6936e29 2566 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
484b41dd 2567 return true;
46f297fb
JB		 2568
2569out_unref_obj:
2570 drm_gem_object_unreference(&obj->base);
2571 mutex_unlock(&dev->struct_mutex);
484b41dd
JB		 2572 return false;
2573}
2574
afd65eb4
MR		 2575/* Update plane->state->fb to match plane->fb after driver-internal updates */
2576static void
2577update_state_fb(struct drm_plane *plane)
2578{
2579 if (plane->fb == plane->state->fb)
2580 return;
2581
2582 if (plane->state->fb)
2583 drm_framebuffer_unreference(plane->state->fb);
2584 plane->state->fb = plane->fb;
2585 if (plane->state->fb)
2586 drm_framebuffer_reference(plane->state->fb);
2587}
2588
5724dbd1 2589static void
f6936e29
DV		 2590intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2591 struct intel_initial_plane_config *plane_config)
484b41dd
JB		 2592{
2593 struct drm_device *dev = intel_crtc->base.dev;
d9ceb816 2594 struct drm_i915_private *dev_priv = dev->dev_private;
484b41dd
JB		 2595 struct drm_crtc *c;
2596 struct intel_crtc *i;
2ff8fde1 2597 struct drm_i915_gem_object *obj;
88595ac9
DV		 2598 struct drm_plane *primary = intel_crtc->base.primary;
2599 struct drm_framebuffer *fb;
484b41dd 2600
2d14030b 2601 if (!plane_config->fb)
484b41dd
JB		 2602 return;
2603
f6936e29 2604 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
88595ac9
DV		 2605 fb = &plane_config->fb->base;
2606 goto valid_fb;
f55548b5 2607 }
484b41dd 2608
2d14030b 2609 kfree(plane_config->fb);
484b41dd
JB		 2610
2611 /*
2612 * Failed to alloc the obj, check to see if we should share
2613 * an fb with another CRTC instead
2614 */
70e1e0ec 2615 for_each_crtc(dev, c) {
484b41dd
JB		 2616 i = to_intel_crtc(c);
2617
2618 if (c == &intel_crtc->base)
2619 continue;
2620
2ff8fde1
MR		 2621 if (!i->active)
2622 continue;
2623
88595ac9
DV		 2624 fb = c->primary->fb;
2625 if (!fb)
484b41dd
JB		 2626 continue;
2627
88595ac9 2628 obj = intel_fb_obj(fb);
2ff8fde1 2629 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
88595ac9
DV		 2630 drm_framebuffer_reference(fb);
2631 goto valid_fb;
484b41dd
JB		 2632 }
2633 }
88595ac9
DV		 2634
2635 return;
2636
2637valid_fb:
2638 obj = intel_fb_obj(fb);
2639 if (obj->tiling_mode != I915_TILING_NONE)
2640 dev_priv->preserve_bios_swizzle = true;
2641
2642 primary->fb = fb;
2643 primary->state->crtc = &intel_crtc->base;
2644 primary->crtc = &intel_crtc->base;
2645 update_state_fb(primary);
2646 obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
46f297fb
JB		 2647}
2648
29b9bde6
DV		 2649static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2650 struct drm_framebuffer *fb,
2651 int x, int y)
81255565
JB		 2652{
2653 struct drm_device *dev = crtc->dev;
2654 struct drm_i915_private *dev_priv = dev->dev_private;
2655 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML		 2656 struct drm_plane *primary = crtc->primary;
2657 bool visible = to_intel_plane_state(primary->state)->visible;
c9ba6fad 2658 struct drm_i915_gem_object *obj;
81255565 2659 int plane = intel_crtc->plane;
e506a0c6 2660 unsigned long linear_offset;
81255565 2661 u32 dspcntr;
f45651ba 2662 u32 reg = DSPCNTR(plane);
48404c1e 2663 int pixel_size;
f45651ba 2664
b70709a6 2665 if (!visible || !fb) {
fdd508a6
VS		 2666 I915_WRITE(reg, 0);
2667 if (INTEL_INFO(dev)->gen >= 4)
2668 I915_WRITE(DSPSURF(plane), 0);
2669 else
2670 I915_WRITE(DSPADDR(plane), 0);
2671 POSTING_READ(reg);
2672 return;
2673 }
2674
c9ba6fad
VS		 2675 obj = intel_fb_obj(fb);
2676 if (WARN_ON(obj == NULL))
2677 return;
2678
2679 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2680
f45651ba
VS		 2681 dspcntr = DISPPLANE_GAMMA_ENABLE;
2682
fdd508a6 2683 dspcntr |= DISPLAY_PLANE_ENABLE;
f45651ba
VS		 2684
2685 if (INTEL_INFO(dev)->gen < 4) {
2686 if (intel_crtc->pipe == PIPE_B)
2687 dspcntr |= DISPPLANE_SEL_PIPE_B;
2688
2689 /* pipesrc and dspsize control the size that is scaled from,
2690 * which should always be the user's requested size.
2691 */
2692 I915_WRITE(DSPSIZE(plane),
6e3c9717
ACO		 2693 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2694 (intel_crtc->config->pipe_src_w - 1));
f45651ba 2695 I915_WRITE(DSPPOS(plane), 0);
c14b0485
VS		 2696 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2697 I915_WRITE(PRIMSIZE(plane),
6e3c9717
ACO		 2698 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2699 (intel_crtc->config->pipe_src_w - 1));
c14b0485
VS		 2700 I915_WRITE(PRIMPOS(plane), 0);
2701 I915_WRITE(PRIMCNSTALPHA(plane), 0);
f45651ba 2702 }
81255565 2703
57779d06
VS		 2704 switch (fb->pixel_format) {
2705 case DRM_FORMAT_C8:
81255565
JB		 2706 dspcntr |= DISPPLANE_8BPP;
2707 break;
57779d06 2708 case DRM_FORMAT_XRGB1555:
57779d06 2709 dspcntr |= DISPPLANE_BGRX555;
81255565 2710 break;
57779d06
VS		 2711 case DRM_FORMAT_RGB565:
2712 dspcntr |= DISPPLANE_BGRX565;
2713 break;
2714 case DRM_FORMAT_XRGB8888:
57779d06
VS		 2715 dspcntr |= DISPPLANE_BGRX888;
2716 break;
2717 case DRM_FORMAT_XBGR8888:
57779d06
VS		 2718 dspcntr |= DISPPLANE_RGBX888;
2719 break;
2720 case DRM_FORMAT_XRGB2101010:
57779d06
VS		 2721 dspcntr |= DISPPLANE_BGRX101010;
2722 break;
2723 case DRM_FORMAT_XBGR2101010:
57779d06 2724 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2725 break;
2726 default:
baba133a 2727 BUG();
81255565 2728 }
57779d06 2729
f45651ba
VS		 2730 if (INTEL_INFO(dev)->gen >= 4 &&
2731 obj->tiling_mode != I915_TILING_NONE)
2732 dspcntr |= DISPPLANE_TILED;
81255565 2733
de1aa629
VS		 2734 if (IS_G4X(dev))
2735 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2736
b9897127 2737 linear_offset = y * fb->pitches[0] + x * pixel_size;
81255565 2738
c2c75131
DV		 2739 if (INTEL_INFO(dev)->gen >= 4) {
2740 intel_crtc->dspaddr_offset =
bc752862 2741 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
b9897127 2742 pixel_size,
bc752862 2743 fb->pitches[0]);
c2c75131
DV		 2744 linear_offset -= intel_crtc->dspaddr_offset;
2745 } else {
e506a0c6 2746 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2747 }
e506a0c6 2748
8e7d688b 2749 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
48404c1e
SJ		 2750 dspcntr |= DISPPLANE_ROTATE_180;
2751
6e3c9717
ACO		 2752 x += (intel_crtc->config->pipe_src_w - 1);
2753 y += (intel_crtc->config->pipe_src_h - 1);
48404c1e
SJ		 2754
2755 /* Finding the last pixel of the last line of the display
2756 data and adding to linear_offset*/
2757 linear_offset +=
6e3c9717
ACO		 2758 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2759 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
48404c1e
SJ		 2760 }
2761
2762 I915_WRITE(reg, dspcntr);
2763
01f2c773 2764 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2765 if (INTEL_INFO(dev)->gen >= 4) {
85ba7b7d
DV		 2766 I915_WRITE(DSPSURF(plane),
2767 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
5eddb70b 2768 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2769 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2770 } else
f343c5f6 2771 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
5eddb70b 2772 POSTING_READ(reg);
17638cd6
JB		 2773}
2774
29b9bde6
DV		 2775static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2776 struct drm_framebuffer *fb,
2777 int x, int y)
17638cd6
JB		 2778{
2779 struct drm_device *dev = crtc->dev;
2780 struct drm_i915_private *dev_priv = dev->dev_private;
2781 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML		 2782 struct drm_plane *primary = crtc->primary;
2783 bool visible = to_intel_plane_state(primary->state)->visible;
c9ba6fad 2784 struct drm_i915_gem_object *obj;
17638cd6 2785 int plane = intel_crtc->plane;
e506a0c6 2786 unsigned long linear_offset;
17638cd6 2787 u32 dspcntr;
f45651ba 2788 u32 reg = DSPCNTR(plane);
48404c1e 2789 int pixel_size;
f45651ba 2790
b70709a6 2791 if (!visible || !fb) {
fdd508a6
VS		 2792 I915_WRITE(reg, 0);
2793 I915_WRITE(DSPSURF(plane), 0);
2794 POSTING_READ(reg);
2795 return;
2796 }
2797
c9ba6fad
VS		 2798 obj = intel_fb_obj(fb);
2799 if (WARN_ON(obj == NULL))
2800 return;
2801
2802 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2803
f45651ba
VS		 2804 dspcntr = DISPPLANE_GAMMA_ENABLE;
2805
fdd508a6 2806 dspcntr |= DISPLAY_PLANE_ENABLE;
f45651ba
VS		 2807
2808 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2809 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
17638cd6 2810
57779d06
VS		 2811 switch (fb->pixel_format) {
2812 case DRM_FORMAT_C8:
17638cd6
JB		 2813 dspcntr |= DISPPLANE_8BPP;
2814 break;
57779d06
VS		 2815 case DRM_FORMAT_RGB565:
2816 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2817 break;
57779d06 2818 case DRM_FORMAT_XRGB8888:
57779d06
VS		 2819 dspcntr |= DISPPLANE_BGRX888;
2820 break;
2821 case DRM_FORMAT_XBGR8888:
57779d06
VS		 2822 dspcntr |= DISPPLANE_RGBX888;
2823 break;
2824 case DRM_FORMAT_XRGB2101010:
57779d06
VS		 2825 dspcntr |= DISPPLANE_BGRX101010;
2826 break;
2827 case DRM_FORMAT_XBGR2101010:
57779d06 2828 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2829 break;
2830 default:
baba133a 2831 BUG();
17638cd6
JB		 2832 }
2833
2834 if (obj->tiling_mode != I915_TILING_NONE)
2835 dspcntr |= DISPPLANE_TILED;
17638cd6 2836
f45651ba 2837 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
1f5d76db 2838 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
17638cd6 2839
b9897127 2840 linear_offset = y * fb->pitches[0] + x * pixel_size;
c2c75131 2841 intel_crtc->dspaddr_offset =
bc752862 2842 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
b9897127 2843 pixel_size,
bc752862 2844 fb->pitches[0]);
c2c75131 2845 linear_offset -= intel_crtc->dspaddr_offset;
8e7d688b 2846 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
48404c1e
SJ		 2847 dspcntr |= DISPPLANE_ROTATE_180;
2848
2849 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
6e3c9717
ACO		 2850 x += (intel_crtc->config->pipe_src_w - 1);
2851 y += (intel_crtc->config->pipe_src_h - 1);
48404c1e
SJ		 2852
2853 /* Finding the last pixel of the last line of the display
2854 data and adding to linear_offset*/
2855 linear_offset +=
6e3c9717
ACO		 2856 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2857 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
48404c1e
SJ		 2858 }
2859 }
2860
2861 I915_WRITE(reg, dspcntr);
17638cd6 2862
01f2c773 2863 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
85ba7b7d
DV		 2864 I915_WRITE(DSPSURF(plane),
2865 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
b3dc685e 2866 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
bc1c91eb
DL		 2867 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2868 } else {
2869 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2870 I915_WRITE(DSPLINOFF(plane), linear_offset);
2871 }
17638cd6 2872 POSTING_READ(reg);
17638cd6
JB		 2873}
2874
b321803d
DL		 2875u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2876 uint32_t pixel_format)
2877{
2878 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2879
2880 /*
2881 * The stride is either expressed as a multiple of 64 bytes
2882 * chunks for linear buffers or in number of tiles for tiled
2883 * buffers.
2884 */
2885 switch (fb_modifier) {
2886 case DRM_FORMAT_MOD_NONE:
2887 return 64;
2888 case I915_FORMAT_MOD_X_TILED:
2889 if (INTEL_INFO(dev)->gen == 2)
2890 return 128;
2891 return 512;
2892 case I915_FORMAT_MOD_Y_TILED:
2893 /* No need to check for old gens and Y tiling since this is
2894 * about the display engine and those will be blocked before
2895 * we get here.
2896 */
2897 return 128;
2898 case I915_FORMAT_MOD_Yf_TILED:
2899 if (bits_per_pixel == 8)
2900 return 64;
2901 else
2902 return 128;
2903 default:
2904 MISSING_CASE(fb_modifier);
2905 return 64;
2906 }
2907}
2908
121920fa
TU		 2909unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
2910 struct drm_i915_gem_object *obj)
2911{
9abc4648 2912 const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
121920fa
TU		 2913
2914 if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
9abc4648 2915 view = &i915_ggtt_view_rotated;
121920fa
TU		 2916
2917 return i915_gem_obj_ggtt_offset_view(obj, view);
2918}
2919
a1b2278e
CK		 2920/*
2921 * This function detaches (aka. unbinds) unused scalers in hardware
2922 */
2923void skl_detach_scalers(struct intel_crtc *intel_crtc)
2924{
2925 struct drm_device *dev;
2926 struct drm_i915_private *dev_priv;
2927 struct intel_crtc_scaler_state *scaler_state;
2928 int i;
2929
2930 if (!intel_crtc || !intel_crtc->config)
2931 return;
2932
2933 dev = intel_crtc->base.dev;
2934 dev_priv = dev->dev_private;
2935 scaler_state = &intel_crtc->config->scaler_state;
2936
2937 /* loop through and disable scalers that aren't in use */
2938 for (i = 0; i < intel_crtc->num_scalers; i++) {
2939 if (!scaler_state->scalers[i].in_use) {
2940 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, i), 0);
2941 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, i), 0);
2942 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, i), 0);
2943 DRM_DEBUG_KMS("CRTC:%d Disabled scaler id %u.%u\n",
2944 intel_crtc->base.base.id, intel_crtc->pipe, i);
2945 }
2946 }
2947}
2948
6156a456 2949u32 skl_plane_ctl_format(uint32_t pixel_format)
70d21f0e 2950{
6156a456 2951 switch (pixel_format) {
d161cf7a 2952 case DRM_FORMAT_C8:
c34ce3d1 2953 return PLANE_CTL_FORMAT_INDEXED;
70d21f0e 2954 case DRM_FORMAT_RGB565:
c34ce3d1 2955 return PLANE_CTL_FORMAT_RGB_565;
70d21f0e 2956 case DRM_FORMAT_XBGR8888:
c34ce3d1 2957 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
6156a456 2958 case DRM_FORMAT_XRGB8888:
c34ce3d1 2959 return PLANE_CTL_FORMAT_XRGB_8888;
6156a456
CK		 2960 /*
2961 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2962 * to be already pre-multiplied. We need to add a knob (or a different
2963 * DRM_FORMAT) for user-space to configure that.
2964 */
f75fb42a 2965 case DRM_FORMAT_ABGR8888:
c34ce3d1 2966 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
6156a456 2967 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
6156a456 2968 case DRM_FORMAT_ARGB8888:
c34ce3d1 2969 return PLANE_CTL_FORMAT_XRGB_8888 |
6156a456 2970 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
70d21f0e 2971 case DRM_FORMAT_XRGB2101010:
c34ce3d1 2972 return PLANE_CTL_FORMAT_XRGB_2101010;
70d21f0e 2973 case DRM_FORMAT_XBGR2101010:
c34ce3d1 2974 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
6156a456 2975 case DRM_FORMAT_YUYV:
c34ce3d1 2976 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
6156a456 2977 case DRM_FORMAT_YVYU:
c34ce3d1 2978 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
6156a456 2979 case DRM_FORMAT_UYVY:
c34ce3d1 2980 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
6156a456 2981 case DRM_FORMAT_VYUY:
c34ce3d1 2982 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
70d21f0e 2983 default:
4249eeef 2984 MISSING_CASE(pixel_format);
70d21f0e 2985 }
8cfcba41 2986
c34ce3d1 2987 return 0;
6156a456 2988}
70d21f0e 2989
6156a456
CK		 2990u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
2991{
6156a456 2992 switch (fb_modifier) {
30af77c4 2993 case DRM_FORMAT_MOD_NONE:
70d21f0e 2994 break;
30af77c4 2995 case I915_FORMAT_MOD_X_TILED:
c34ce3d1 2996 return PLANE_CTL_TILED_X;
b321803d 2997 case I915_FORMAT_MOD_Y_TILED:
c34ce3d1 2998 return PLANE_CTL_TILED_Y;
b321803d 2999 case I915_FORMAT_MOD_Yf_TILED:
c34ce3d1 3000 return PLANE_CTL_TILED_YF;
70d21f0e 3001 default:
6156a456 3002 MISSING_CASE(fb_modifier);
70d21f0e 3003 }
8cfcba41 3004
c34ce3d1 3005 return 0;
6156a456 3006}
70d21f0e 3007
6156a456
CK		 3008u32 skl_plane_ctl_rotation(unsigned int rotation)
3009{
3b7a5119 3010 switch (rotation) {
6156a456
CK		 3011 case BIT(DRM_ROTATE_0):
3012 break;
1e8df167
SJ		 3013 /*
3014 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3015 * while i915 HW rotation is clockwise, thats why this swapping.
3016 */
3b7a5119 3017 case BIT(DRM_ROTATE_90):
1e8df167 3018 return PLANE_CTL_ROTATE_270;
3b7a5119 3019 case BIT(DRM_ROTATE_180):
c34ce3d1 3020 return PLANE_CTL_ROTATE_180;
3b7a5119 3021 case BIT(DRM_ROTATE_270):
1e8df167 3022 return PLANE_CTL_ROTATE_90;
6156a456
CK		 3023 default:
3024 MISSING_CASE(rotation);
3025 }
3026
c34ce3d1 3027 return 0;
6156a456
CK		 3028}
3029
3030static void skylake_update_primary_plane(struct drm_crtc *crtc,
3031 struct drm_framebuffer *fb,
3032 int x, int y)
3033{
3034 struct drm_device *dev = crtc->dev;
3035 struct drm_i915_private *dev_priv = dev->dev_private;
3036 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML		 3037 struct drm_plane *plane = crtc->primary;
3038 bool visible = to_intel_plane_state(plane->state)->visible;
6156a456
CK		 3039 struct drm_i915_gem_object *obj;
3040 int pipe = intel_crtc->pipe;
3041 u32 plane_ctl, stride_div, stride;
3042 u32 tile_height, plane_offset, plane_size;
3043 unsigned int rotation;
3044 int x_offset, y_offset;
3045 unsigned long surf_addr;
6156a456
CK		 3046 struct intel_crtc_state *crtc_state = intel_crtc->config;
3047 struct intel_plane_state *plane_state;
3048 int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3049 int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3050 int scaler_id = -1;
3051
6156a456
CK		 3052 plane_state = to_intel_plane_state(plane->state);
3053
b70709a6 3054 if (!visible || !fb) {
6156a456
CK		 3055 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3056 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3057 POSTING_READ(PLANE_CTL(pipe, 0));
3058 return;
3b7a5119 3059 }
70d21f0e 3060
6156a456
CK		 3061 plane_ctl = PLANE_CTL_ENABLE |
3062 PLANE_CTL_PIPE_GAMMA_ENABLE |
3063 PLANE_CTL_PIPE_CSC_ENABLE;
3064
3065 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3066 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3067 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3068
3069 rotation = plane->state->rotation;
3070 plane_ctl |= skl_plane_ctl_rotation(rotation);
3071
b321803d
DL		 3072 obj = intel_fb_obj(fb);
3073 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3074 fb->pixel_format);
3b7a5119
SJ		 3075 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj);
3076
6156a456
CK		 3077 /*
3078 * FIXME: intel_plane_state->src, dst aren't set when transitional
3079 * update_plane helpers are called from legacy paths.
3080 * Once full atomic crtc is available, below check can be avoided.
3081 */
3082 if (drm_rect_width(&plane_state->src)) {
3083 scaler_id = plane_state->scaler_id;
3084 src_x = plane_state->src.x1 >> 16;
3085 src_y = plane_state->src.y1 >> 16;
3086 src_w = drm_rect_width(&plane_state->src) >> 16;
3087 src_h = drm_rect_height(&plane_state->src) >> 16;
3088 dst_x = plane_state->dst.x1;
3089 dst_y = plane_state->dst.y1;
3090 dst_w = drm_rect_width(&plane_state->dst);
3091 dst_h = drm_rect_height(&plane_state->dst);
3092
3093 WARN_ON(x != src_x || y != src_y);
3094 } else {
3095 src_w = intel_crtc->config->pipe_src_w;
3096 src_h = intel_crtc->config->pipe_src_h;
3097 }
3098
3b7a5119
SJ		 3099 if (intel_rotation_90_or_270(rotation)) {
3100 /* stride = Surface height in tiles */
2614f17d 3101 tile_height = intel_tile_height(dev, fb->pixel_format,
3b7a5119
SJ		 3102 fb->modifier[0]);
3103 stride = DIV_ROUND_UP(fb->height, tile_height);
6156a456 3104 x_offset = stride * tile_height - y - src_h;
3b7a5119 3105 y_offset = x;
6156a456 3106 plane_size = (src_w - 1) << 16 | (src_h - 1);
3b7a5119
SJ		 3107 } else {
3108 stride = fb->pitches[0] / stride_div;
3109 x_offset = x;
3110 y_offset = y;
6156a456 3111 plane_size = (src_h - 1) << 16 | (src_w - 1);
3b7a5119
SJ		 3112 }
3113 plane_offset = y_offset << 16 | x_offset;
b321803d 3114
70d21f0e 3115 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3b7a5119
SJ		 3116 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3117 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3118 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
6156a456
CK		 3119
3120 if (scaler_id >= 0) {
3121 uint32_t ps_ctrl = 0;
3122
3123 WARN_ON(!dst_w || !dst_h);
3124 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3125 crtc_state->scaler_state.scalers[scaler_id].mode;
3126 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3127 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3128 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3129 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3130 I915_WRITE(PLANE_POS(pipe, 0), 0);
3131 } else {
3132 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3133 }
3134
121920fa 3135 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
70d21f0e
DL		 3136
3137 POSTING_READ(PLANE_SURF(pipe, 0));
3138}
3139
17638cd6
JB		 3140/* Assume fb object is pinned & idle & fenced and just update base pointers */
3141static int
3142intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3143 int x, int y, enum mode_set_atomic state)
3144{
3145 struct drm_device *dev = crtc->dev;
3146 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 3147
6b8e6ed0
CW		 3148 if (dev_priv->display.disable_fbc)
3149 dev_priv->display.disable_fbc(dev);
81255565 3150
29b9bde6
DV		 3151 dev_priv->display.update_primary_plane(crtc, fb, x, y);
3152
3153 return 0;
81255565
JB		 3154}
3155
7514747d 3156static void intel_complete_page_flips(struct drm_device *dev)
96a02917 3157{
96a02917
VS		 3158 struct drm_crtc *crtc;
3159
70e1e0ec 3160 for_each_crtc(dev, crtc) {
96a02917
VS		 3161 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3162 enum plane plane = intel_crtc->plane;
3163
3164 intel_prepare_page_flip(dev, plane);
3165 intel_finish_page_flip_plane(dev, plane);
3166 }
7514747d
VS		 3167}
3168
3169static void intel_update_primary_planes(struct drm_device *dev)
3170{
3171 struct drm_i915_private *dev_priv = dev->dev_private;
3172 struct drm_crtc *crtc;
96a02917 3173
70e1e0ec 3174 for_each_crtc(dev, crtc) {
96a02917
VS		 3175 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3176
51fd371b 3177 drm_modeset_lock(&crtc->mutex, NULL);
947fdaad
CW		 3178 /*
3179 * FIXME: Once we have proper support for primary planes (and
3180 * disabling them without disabling the entire crtc) allow again
66e514c1 3181 * a NULL crtc->primary->fb.
947fdaad 3182 */
f4510a27 3183 if (intel_crtc->active && crtc->primary->fb)
262ca2b0 3184 dev_priv->display.update_primary_plane(crtc,
66e514c1 3185 crtc->primary->fb,
262ca2b0
MR		 3186 crtc->x,
3187 crtc->y);
51fd371b 3188 drm_modeset_unlock(&crtc->mutex);
96a02917
VS		 3189 }
3190}
3191
ce22dba9
ML		 3192void intel_crtc_reset(struct intel_crtc *crtc)
3193{
3194 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3195
3196 if (!crtc->active)
3197 return;
3198
3199 intel_crtc_disable_planes(&crtc->base);
3200 dev_priv->display.crtc_disable(&crtc->base);
3201 dev_priv->display.crtc_enable(&crtc->base);
3202 intel_crtc_enable_planes(&crtc->base);
3203}
3204
7514747d
VS		 3205void intel_prepare_reset(struct drm_device *dev)
3206{
f98ce92f
VS		 3207 struct drm_i915_private *dev_priv = to_i915(dev);
3208 struct intel_crtc *crtc;
3209
7514747d
VS		 3210 /* no reset support for gen2 */
3211 if (IS_GEN2(dev))
3212 return;
3213
3214 /* reset doesn't touch the display */
3215 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3216 return;
3217
3218 drm_modeset_lock_all(dev);
f98ce92f
VS		 3219
3220 /*
3221 * Disabling the crtcs gracefully seems nicer. Also the
3222 * g33 docs say we should at least disable all the planes.
3223 */
3224 for_each_intel_crtc(dev, crtc) {
ce22dba9
ML		 3225 if (!crtc->active)
3226 continue;
3227
3228 intel_crtc_disable_planes(&crtc->base);
3229 dev_priv->display.crtc_disable(&crtc->base);
f98ce92f 3230 }
7514747d
VS		 3231}
3232
3233void intel_finish_reset(struct drm_device *dev)
3234{
3235 struct drm_i915_private *dev_priv = to_i915(dev);
3236
3237 /*
3238 * Flips in the rings will be nuked by the reset,
3239 * so complete all pending flips so that user space
3240 * will get its events and not get stuck.
3241 */
3242 intel_complete_page_flips(dev);
3243
3244 /* no reset support for gen2 */
3245 if (IS_GEN2(dev))
3246 return;
3247
3248 /* reset doesn't touch the display */
3249 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3250 /*
3251 * Flips in the rings have been nuked by the reset,
3252 * so update the base address of all primary
3253 * planes to the the last fb to make sure we're
3254 * showing the correct fb after a reset.
3255 */
3256 intel_update_primary_planes(dev);
3257 return;
3258 }
3259
3260 /*
3261 * The display has been reset as well,
3262 * so need a full re-initialization.
3263 */
3264 intel_runtime_pm_disable_interrupts(dev_priv);
3265 intel_runtime_pm_enable_interrupts(dev_priv);
3266
3267 intel_modeset_init_hw(dev);
3268
3269 spin_lock_irq(&dev_priv->irq_lock);
3270 if (dev_priv->display.hpd_irq_setup)
3271 dev_priv->display.hpd_irq_setup(dev);
3272 spin_unlock_irq(&dev_priv->irq_lock);
3273
3274 intel_modeset_setup_hw_state(dev, true);
3275
3276 intel_hpd_init(dev_priv);
3277
3278 drm_modeset_unlock_all(dev);
3279}
3280
2e2f351d 3281static void
14667a4b
CW		 3282intel_finish_fb(struct drm_framebuffer *old_fb)
3283{
2ff8fde1 3284 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
2e2f351d 3285 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
14667a4b
CW		 3286 bool was_interruptible = dev_priv->mm.interruptible;
3287 int ret;
3288
14667a4b
CW		 3289 /* Big Hammer, we also need to ensure that any pending
3290 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3291 * current scanout is retired before unpinning the old
2e2f351d
CW		 3292 * framebuffer. Note that we rely on userspace rendering
3293 * into the buffer attached to the pipe they are waiting
3294 * on. If not, userspace generates a GPU hang with IPEHR
3295 * point to the MI_WAIT_FOR_EVENT.
14667a4b
CW		 3296 *
3297 * This should only fail upon a hung GPU, in which case we
3298 * can safely continue.
3299 */
3300 dev_priv->mm.interruptible = false;
2e2f351d 3301 ret = i915_gem_object_wait_rendering(obj, true);
14667a4b
CW		 3302 dev_priv->mm.interruptible = was_interruptible;
3303
2e2f351d 3304 WARN_ON(ret);
14667a4b
CW		 3305}
3306
7d5e3799
CW		 3307static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3308{
3309 struct drm_device *dev = crtc->dev;
3310 struct drm_i915_private *dev_priv = dev->dev_private;
3311 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7d5e3799
CW		 3312 bool pending;
3313
3314 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3315 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3316 return false;
3317
5e2d7afc 3318 spin_lock_irq(&dev->event_lock);
7d5e3799 3319 pending = to_intel_crtc(crtc)->unpin_work != NULL;
5e2d7afc 3320 spin_unlock_irq(&dev->event_lock);
7d5e3799
CW		 3321
3322 return pending;
3323}
3324
e30e8f75
GP		 3325static void intel_update_pipe_size(struct intel_crtc *crtc)
3326{
3327 struct drm_device *dev = crtc->base.dev;
3328 struct drm_i915_private *dev_priv = dev->dev_private;
3329 const struct drm_display_mode *adjusted_mode;
3330
3331 if (!i915.fastboot)
3332 return;
3333
3334 /*
3335 * Update pipe size and adjust fitter if needed: the reason for this is
3336 * that in compute_mode_changes we check the native mode (not the pfit
3337 * mode) to see if we can flip rather than do a full mode set. In the
3338 * fastboot case, we'll flip, but if we don't update the pipesrc and
3339 * pfit state, we'll end up with a big fb scanned out into the wrong
3340 * sized surface.
3341 *
3342 * To fix this properly, we need to hoist the checks up into
3343 * compute_mode_changes (or above), check the actual pfit state and
3344 * whether the platform allows pfit disable with pipe active, and only
3345 * then update the pipesrc and pfit state, even on the flip path.
3346 */
3347
6e3c9717 3348 adjusted_mode = &crtc->config->base.adjusted_mode;
e30e8f75
GP		 3349
3350 I915_WRITE(PIPESRC(crtc->pipe),
3351 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3352 (adjusted_mode->crtc_vdisplay - 1));
6e3c9717 3353 if (!crtc->config->pch_pfit.enabled &&
409ee761
ACO		 3354 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3355 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
e30e8f75
GP		 3356 I915_WRITE(PF_CTL(crtc->pipe), 0);
3357 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3358 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3359 }
6e3c9717
ACO		 3360 crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3361 crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
e30e8f75
GP		 3362}
3363
5e84e1a4
ZW		 3364static void intel_fdi_normal_train(struct drm_crtc *crtc)
3365{
3366 struct drm_device *dev = crtc->dev;
3367 struct drm_i915_private *dev_priv = dev->dev_private;
3368 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3369 int pipe = intel_crtc->pipe;
3370 u32 reg, temp;
3371
3372 /* enable normal train */
3373 reg = FDI_TX_CTL(pipe);
3374 temp = I915_READ(reg);
61e499bf 3375 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 3376 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3377 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 3378 } else {
3379 temp &= ~FDI_LINK_TRAIN_NONE;
3380 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 3381 }
5e84e1a4
ZW		 3382 I915_WRITE(reg, temp);
3383
3384 reg = FDI_RX_CTL(pipe);
3385 temp = I915_READ(reg);
3386 if (HAS_PCH_CPT(dev)) {
3387 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3388 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3389 } else {
3390 temp &= ~FDI_LINK_TRAIN_NONE;
3391 temp |= FDI_LINK_TRAIN_NONE;
3392 }
3393 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3394
3395 /* wait one idle pattern time */
3396 POSTING_READ(reg);
3397 udelay(1000);
357555c0
JB		 3398
3399 /* IVB wants error correction enabled */
3400 if (IS_IVYBRIDGE(dev))
3401 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3402 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 3403}
3404
8db9d77b
ZW		 3405/* The FDI link training functions for ILK/Ibexpeak. */
3406static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3407{
3408 struct drm_device *dev = crtc->dev;
3409 struct drm_i915_private *dev_priv = dev->dev_private;
3410 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3411 int pipe = intel_crtc->pipe;
5eddb70b 3412 u32 reg, temp, tries;
8db9d77b 3413
1c8562f6 3414 /* FDI needs bits from pipe first */
0fc932b8 3415 assert_pipe_enabled(dev_priv, pipe);
0fc932b8 3416
e1a44743
AJ		 3417 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3418 for train result */
5eddb70b
CW		 3419 reg = FDI_RX_IMR(pipe);
3420 temp = I915_READ(reg);
e1a44743
AJ		 3421 temp &= ~FDI_RX_SYMBOL_LOCK;
3422 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 3423 I915_WRITE(reg, temp);
3424 I915_READ(reg);
e1a44743
AJ		 3425 udelay(150);
3426
8db9d77b 3427 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 3428 reg = FDI_TX_CTL(pipe);
3429 temp = I915_READ(reg);
627eb5a3 3430 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3431 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
8db9d77b
ZW		 3432 temp &= ~FDI_LINK_TRAIN_NONE;
3433 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 3434 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 3435
5eddb70b
CW		 3436 reg = FDI_RX_CTL(pipe);
3437 temp = I915_READ(reg);
8db9d77b
ZW		 3438 temp &= ~FDI_LINK_TRAIN_NONE;
3439 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 3440 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3441
3442 POSTING_READ(reg);
8db9d77b
ZW		 3443 udelay(150);
3444
5b2adf89 3445 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 3446 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3447 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3448 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 3449
5eddb70b 3450 reg = FDI_RX_IIR(pipe);
e1a44743 3451 for (tries = 0; tries < 5; tries++) {
5eddb70b 3452 temp = I915_READ(reg);
8db9d77b
ZW		 3453 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3454
3455 if ((temp & FDI_RX_BIT_LOCK)) {
3456 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 3457 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 3458 break;
3459 }
8db9d77b 3460 }
e1a44743 3461 if (tries == 5)
5eddb70b 3462 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 3463
3464 /* Train 2 */
5eddb70b
CW		 3465 reg = FDI_TX_CTL(pipe);
3466 temp = I915_READ(reg);
8db9d77b
ZW		 3467 temp &= ~FDI_LINK_TRAIN_NONE;
3468 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 3469 I915_WRITE(reg, temp);
8db9d77b 3470
5eddb70b
CW		 3471 reg = FDI_RX_CTL(pipe);
3472 temp = I915_READ(reg);
8db9d77b
ZW		 3473 temp &= ~FDI_LINK_TRAIN_NONE;
3474 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 3475 I915_WRITE(reg, temp);
8db9d77b 3476
5eddb70b
CW		 3477 POSTING_READ(reg);
3478 udelay(150);
8db9d77b 3479
5eddb70b 3480 reg = FDI_RX_IIR(pipe);
e1a44743 3481 for (tries = 0; tries < 5; tries++) {
5eddb70b 3482 temp = I915_READ(reg);
8db9d77b
ZW		 3483 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3484
3485 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 3486 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 3487 DRM_DEBUG_KMS("FDI train 2 done.\n");
3488 break;
3489 }
8db9d77b 3490 }
e1a44743 3491 if (tries == 5)
5eddb70b 3492 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 3493
3494 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 3495
8db9d77b
ZW		 3496}
3497
0206e353 3498static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 3499 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3500 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3501 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3502 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3503};
3504
3505/* The FDI link training functions for SNB/Cougarpoint. */
3506static void gen6_fdi_link_train(struct drm_crtc *crtc)
3507{
3508 struct drm_device *dev = crtc->dev;
3509 struct drm_i915_private *dev_priv = dev->dev_private;
3510 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3511 int pipe = intel_crtc->pipe;
fa37d39e 3512 u32 reg, temp, i, retry;
8db9d77b 3513
e1a44743
AJ		 3514 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3515 for train result */
5eddb70b
CW		 3516 reg = FDI_RX_IMR(pipe);
3517 temp = I915_READ(reg);
e1a44743
AJ		 3518 temp &= ~FDI_RX_SYMBOL_LOCK;
3519 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 3520 I915_WRITE(reg, temp);
3521
3522 POSTING_READ(reg);
e1a44743
AJ		 3523 udelay(150);
3524
8db9d77b 3525 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 3526 reg = FDI_TX_CTL(pipe);
3527 temp = I915_READ(reg);
627eb5a3 3528 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3529 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
8db9d77b
ZW		 3530 temp &= ~FDI_LINK_TRAIN_NONE;
3531 temp |= FDI_LINK_TRAIN_PATTERN_1;
3532 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3533 /* SNB-B */
3534 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 3535 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 3536
d74cf324
DV		 3537 I915_WRITE(FDI_RX_MISC(pipe),
3538 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3539
5eddb70b
CW		 3540 reg = FDI_RX_CTL(pipe);
3541 temp = I915_READ(reg);
8db9d77b
ZW		 3542 if (HAS_PCH_CPT(dev)) {
3543 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3544 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3545 } else {
3546 temp &= ~FDI_LINK_TRAIN_NONE;
3547 temp |= FDI_LINK_TRAIN_PATTERN_1;
3548 }
5eddb70b
CW		 3549 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3550
3551 POSTING_READ(reg);
8db9d77b
ZW		 3552 udelay(150);
3553
0206e353 3554 for (i = 0; i < 4; i++) {
5eddb70b
CW		 3555 reg = FDI_TX_CTL(pipe);
3556 temp = I915_READ(reg);
8db9d77b
ZW		 3557 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3558 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 3559 I915_WRITE(reg, temp);
3560
3561 POSTING_READ(reg);
8db9d77b
ZW		 3562 udelay(500);
3563
fa37d39e
SP		 3564 for (retry = 0; retry < 5; retry++) {
3565 reg = FDI_RX_IIR(pipe);
3566 temp = I915_READ(reg);
3567 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3568 if (temp & FDI_RX_BIT_LOCK) {
3569 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3570 DRM_DEBUG_KMS("FDI train 1 done.\n");
3571 break;
3572 }
3573 udelay(50);
8db9d77b 3574 }
fa37d39e
SP		 3575 if (retry < 5)
3576 break;
8db9d77b
ZW		 3577 }
3578 if (i == 4)
5eddb70b 3579 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 3580
3581 /* Train 2 */
5eddb70b
CW		 3582 reg = FDI_TX_CTL(pipe);
3583 temp = I915_READ(reg);
8db9d77b
ZW		 3584 temp &= ~FDI_LINK_TRAIN_NONE;
3585 temp |= FDI_LINK_TRAIN_PATTERN_2;
3586 if (IS_GEN6(dev)) {
3587 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3588 /* SNB-B */
3589 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3590 }
5eddb70b 3591 I915_WRITE(reg, temp);
8db9d77b 3592
5eddb70b
CW		 3593 reg = FDI_RX_CTL(pipe);
3594 temp = I915_READ(reg);
8db9d77b
ZW		 3595 if (HAS_PCH_CPT(dev)) {
3596 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3597 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3598 } else {
3599 temp &= ~FDI_LINK_TRAIN_NONE;
3600 temp |= FDI_LINK_TRAIN_PATTERN_2;
3601 }
5eddb70b
CW		 3602 I915_WRITE(reg, temp);
3603
3604 POSTING_READ(reg);
8db9d77b
ZW		 3605 udelay(150);
3606
0206e353 3607 for (i = 0; i < 4; i++) {
5eddb70b
CW		 3608 reg = FDI_TX_CTL(pipe);
3609 temp = I915_READ(reg);
8db9d77b
ZW		 3610 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3611 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 3612 I915_WRITE(reg, temp);
3613
3614 POSTING_READ(reg);
8db9d77b
ZW		 3615 udelay(500);
3616
fa37d39e
SP		 3617 for (retry = 0; retry < 5; retry++) {
3618 reg = FDI_RX_IIR(pipe);
3619 temp = I915_READ(reg);
3620 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3621 if (temp & FDI_RX_SYMBOL_LOCK) {
3622 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3623 DRM_DEBUG_KMS("FDI train 2 done.\n");
3624 break;
3625 }
3626 udelay(50);
8db9d77b 3627 }
fa37d39e
SP		 3628 if (retry < 5)
3629 break;
8db9d77b
ZW		 3630 }
3631 if (i == 4)
5eddb70b 3632 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 3633
3634 DRM_DEBUG_KMS("FDI train done.\n");
3635}
3636
357555c0
JB		 3637/* Manual link training for Ivy Bridge A0 parts */
3638static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3639{
3640 struct drm_device *dev = crtc->dev;
3641 struct drm_i915_private *dev_priv = dev->dev_private;
3642 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3643 int pipe = intel_crtc->pipe;
139ccd3f 3644 u32 reg, temp, i, j;
357555c0
JB		 3645
3646 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3647 for train result */
3648 reg = FDI_RX_IMR(pipe);
3649 temp = I915_READ(reg);
3650 temp &= ~FDI_RX_SYMBOL_LOCK;
3651 temp &= ~FDI_RX_BIT_LOCK;
3652 I915_WRITE(reg, temp);
3653
3654 POSTING_READ(reg);
3655 udelay(150);
3656
01a415fd
DV		 3657 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3658 I915_READ(FDI_RX_IIR(pipe)));
3659
139ccd3f
JB		 3660 /* Try each vswing and preemphasis setting twice before moving on */
3661 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3662 /* disable first in case we need to retry */
3663 reg = FDI_TX_CTL(pipe);
3664 temp = I915_READ(reg);
3665 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3666 temp &= ~FDI_TX_ENABLE;
3667 I915_WRITE(reg, temp);
357555c0 3668
139ccd3f
JB		 3669 reg = FDI_RX_CTL(pipe);
3670 temp = I915_READ(reg);
3671 temp &= ~FDI_LINK_TRAIN_AUTO;
3672 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3673 temp &= ~FDI_RX_ENABLE;
3674 I915_WRITE(reg, temp);
357555c0 3675
139ccd3f 3676 /* enable CPU FDI TX and PCH FDI RX */
357555c0
JB		 3677 reg = FDI_TX_CTL(pipe);
3678 temp = I915_READ(reg);
139ccd3f 3679 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3680 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
139ccd3f 3681 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
357555c0 3682 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
139ccd3f
JB		 3683 temp |= snb_b_fdi_train_param[j/2];
3684 temp |= FDI_COMPOSITE_SYNC;
3685 I915_WRITE(reg, temp | FDI_TX_ENABLE);
357555c0 3686
139ccd3f
JB		 3687 I915_WRITE(FDI_RX_MISC(pipe),
3688 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
357555c0 3689
139ccd3f 3690 reg = FDI_RX_CTL(pipe);
357555c0 3691 temp = I915_READ(reg);
139ccd3f
JB		 3692 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3693 temp |= FDI_COMPOSITE_SYNC;
3694 I915_WRITE(reg, temp | FDI_RX_ENABLE);
357555c0 3695
139ccd3f
JB		 3696 POSTING_READ(reg);
3697 udelay(1); /* should be 0.5us */
357555c0 3698
139ccd3f
JB		 3699 for (i = 0; i < 4; i++) {
3700 reg = FDI_RX_IIR(pipe);
3701 temp = I915_READ(reg);
3702 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 3703
139ccd3f
JB		 3704 if (temp & FDI_RX_BIT_LOCK ||
3705 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3706 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3707 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3708 i);
3709 break;
3710 }
3711 udelay(1); /* should be 0.5us */
3712 }
3713 if (i == 4) {
3714 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3715 continue;
3716 }
357555c0 3717
139ccd3f 3718 /* Train 2 */
357555c0
JB		 3719 reg = FDI_TX_CTL(pipe);
3720 temp = I915_READ(reg);
139ccd3f
JB		 3721 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3722 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3723 I915_WRITE(reg, temp);
3724
3725 reg = FDI_RX_CTL(pipe);
3726 temp = I915_READ(reg);
3727 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3728 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
357555c0
JB		 3729 I915_WRITE(reg, temp);
3730
3731 POSTING_READ(reg);
139ccd3f 3732 udelay(2); /* should be 1.5us */
357555c0 3733
139ccd3f
JB		 3734 for (i = 0; i < 4; i++) {
3735 reg = FDI_RX_IIR(pipe);
3736 temp = I915_READ(reg);
3737 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 3738
139ccd3f
JB		 3739 if (temp & FDI_RX_SYMBOL_LOCK ||
3740 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3741 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3742 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3743 i);
3744 goto train_done;
3745 }
3746 udelay(2); /* should be 1.5us */
357555c0 3747 }
139ccd3f
JB		 3748 if (i == 4)
3749 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
357555c0 3750 }
357555c0 3751
139ccd3f 3752train_done:
357555c0
JB		 3753 DRM_DEBUG_KMS("FDI train done.\n");
3754}
3755
88cefb6c 3756static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 3757{
88cefb6c 3758 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 3759 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 3760 int pipe = intel_crtc->pipe;
5eddb70b 3761 u32 reg, temp;
79e53945 3762
c64e311e 3763
c98e9dcf 3764 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 3765 reg = FDI_RX_CTL(pipe);
3766 temp = I915_READ(reg);
627eb5a3 3767 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
6e3c9717 3768 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
dfd07d72 3769 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 3770 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3771
3772 POSTING_READ(reg);
c98e9dcf
JB		 3773 udelay(200);
3774
3775 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 3776 temp = I915_READ(reg);
3777 I915_WRITE(reg, temp | FDI_PCDCLK);
3778
3779 POSTING_READ(reg);
c98e9dcf
JB		 3780 udelay(200);
3781
20749730
PZ		 3782 /* Enable CPU FDI TX PLL, always on for Ironlake */
3783 reg = FDI_TX_CTL(pipe);
3784 temp = I915_READ(reg);
3785 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3786 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 3787
20749730
PZ		 3788 POSTING_READ(reg);
3789 udelay(100);
6be4a607 3790 }
0e23b99d
JB		 3791}
3792
88cefb6c
DV		 3793static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3794{
3795 struct drm_device *dev = intel_crtc->base.dev;
3796 struct drm_i915_private *dev_priv = dev->dev_private;
3797 int pipe = intel_crtc->pipe;
3798 u32 reg, temp;
3799
3800 /* Switch from PCDclk to Rawclk */
3801 reg = FDI_RX_CTL(pipe);
3802 temp = I915_READ(reg);
3803 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3804
3805 /* Disable CPU FDI TX PLL */
3806 reg = FDI_TX_CTL(pipe);
3807 temp = I915_READ(reg);
3808 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3809
3810 POSTING_READ(reg);
3811 udelay(100);
3812
3813 reg = FDI_RX_CTL(pipe);
3814 temp = I915_READ(reg);
3815 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3816
3817 /* Wait for the clocks to turn off. */
3818 POSTING_READ(reg);
3819 udelay(100);
3820}
3821
0fc932b8
JB		 3822static void ironlake_fdi_disable(struct drm_crtc *crtc)
3823{
3824 struct drm_device *dev = crtc->dev;
3825 struct drm_i915_private *dev_priv = dev->dev_private;
3826 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3827 int pipe = intel_crtc->pipe;
3828 u32 reg, temp;
3829
3830 /* disable CPU FDI tx and PCH FDI rx */
3831 reg = FDI_TX_CTL(pipe);
3832 temp = I915_READ(reg);
3833 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3834 POSTING_READ(reg);
3835
3836 reg = FDI_RX_CTL(pipe);
3837 temp = I915_READ(reg);
3838 temp &= ~(0x7 << 16);
dfd07d72 3839 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 3840 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3841
3842 POSTING_READ(reg);
3843 udelay(100);
3844
3845 /* Ironlake workaround, disable clock pointer after downing FDI */
eba905b2 3846 if (HAS_PCH_IBX(dev))
6f06ce18 3847 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
0fc932b8
JB		 3848
3849 /* still set train pattern 1 */
3850 reg = FDI_TX_CTL(pipe);
3851 temp = I915_READ(reg);
3852 temp &= ~FDI_LINK_TRAIN_NONE;
3853 temp |= FDI_LINK_TRAIN_PATTERN_1;
3854 I915_WRITE(reg, temp);
3855
3856 reg = FDI_RX_CTL(pipe);
3857 temp = I915_READ(reg);
3858 if (HAS_PCH_CPT(dev)) {
3859 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3860 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3861 } else {
3862 temp &= ~FDI_LINK_TRAIN_NONE;
3863 temp |= FDI_LINK_TRAIN_PATTERN_1;
3864 }
3865 /* BPC in FDI rx is consistent with that in PIPECONF */
3866 temp &= ~(0x07 << 16);
dfd07d72 3867 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 3868 I915_WRITE(reg, temp);
3869
3870 POSTING_READ(reg);
3871 udelay(100);
3872}
3873
5dce5b93
CW		 3874bool intel_has_pending_fb_unpin(struct drm_device *dev)
3875{
3876 struct intel_crtc *crtc;
3877
3878 /* Note that we don't need to be called with mode_config.lock here
3879 * as our list of CRTC objects is static for the lifetime of the
3880 * device and so cannot disappear as we iterate. Similarly, we can
3881 * happily treat the predicates as racy, atomic checks as userspace
3882 * cannot claim and pin a new fb without at least acquring the
3883 * struct_mutex and so serialising with us.
3884 */
d3fcc808 3885 for_each_intel_crtc(dev, crtc) {
5dce5b93
CW		 3886 if (atomic_read(&crtc->unpin_work_count) == 0)
3887 continue;
3888
3889 if (crtc->unpin_work)
3890 intel_wait_for_vblank(dev, crtc->pipe);
3891
3892 return true;
3893 }
3894
3895 return false;
3896}
3897
d6bbafa1
CW		 3898static void page_flip_completed(struct intel_crtc *intel_crtc)
3899{
3900 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3901 struct intel_unpin_work *work = intel_crtc->unpin_work;
3902
3903 /* ensure that the unpin work is consistent wrt ->pending. */
3904 smp_rmb();
3905 intel_crtc->unpin_work = NULL;
3906
3907 if (work->event)
3908 drm_send_vblank_event(intel_crtc->base.dev,
3909 intel_crtc->pipe,
3910 work->event);
3911
3912 drm_crtc_vblank_put(&intel_crtc->base);
3913
3914 wake_up_all(&dev_priv->pending_flip_queue);
3915 queue_work(dev_priv->wq, &work->work);
3916
3917 trace_i915_flip_complete(intel_crtc->plane,
3918 work->pending_flip_obj);
3919}
3920
46a55d30 3921void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
e6c3a2a6 3922{
0f91128d 3923 struct drm_device *dev = crtc->dev;
5bb61643 3924 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6 3925
2c10d571 3926 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
9c787942
CW		 3927 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3928 !intel_crtc_has_pending_flip(crtc),
3929 60*HZ) == 0)) {
3930 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2c10d571 3931
5e2d7afc 3932 spin_lock_irq(&dev->event_lock);
9c787942
CW		 3933 if (intel_crtc->unpin_work) {
3934 WARN_ONCE(1, "Removing stuck page flip\n");
3935 page_flip_completed(intel_crtc);
3936 }
5e2d7afc 3937 spin_unlock_irq(&dev->event_lock);
9c787942 3938 }
5bb61643 3939
975d568a
CW		 3940 if (crtc->primary->fb) {
3941 mutex_lock(&dev->struct_mutex);
3942 intel_finish_fb(crtc->primary->fb);
3943 mutex_unlock(&dev->struct_mutex);
3944 }
e6c3a2a6
CW		 3945}
3946
e615efe4
ED		 3947/* Program iCLKIP clock to the desired frequency */
3948static void lpt_program_iclkip(struct drm_crtc *crtc)
3949{
3950 struct drm_device *dev = crtc->dev;
3951 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 3952 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
e615efe4
ED		 3953 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3954 u32 temp;
3955
09153000
DV		 3956 mutex_lock(&dev_priv->dpio_lock);
3957
e615efe4
ED		 3958 /* It is necessary to ungate the pixclk gate prior to programming
3959 * the divisors, and gate it back when it is done.
3960 */
3961 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3962
3963 /* Disable SSCCTL */
3964 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 3965 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3966 SBI_SSCCTL_DISABLE,
3967 SBI_ICLK);
e615efe4
ED		 3968
3969 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
12d7ceed 3970 if (clock == 20000) {
e615efe4
ED		 3971 auxdiv = 1;
3972 divsel = 0x41;
3973 phaseinc = 0x20;
3974 } else {
3975 /* The iCLK virtual clock root frequency is in MHz,
241bfc38
DL		 3976 * but the adjusted_mode->crtc_clock in in KHz. To get the
3977 * divisors, it is necessary to divide one by another, so we
e615efe4
ED		 3978 * convert the virtual clock precision to KHz here for higher
3979 * precision.
3980 */
3981 u32 iclk_virtual_root_freq = 172800 * 1000;
3982 u32 iclk_pi_range = 64;
3983 u32 desired_divisor, msb_divisor_value, pi_value;
3984
12d7ceed 3985 desired_divisor = (iclk_virtual_root_freq / clock);
e615efe4
ED		 3986 msb_divisor_value = desired_divisor / iclk_pi_range;
3987 pi_value = desired_divisor % iclk_pi_range;
3988
3989 auxdiv = 0;
3990 divsel = msb_divisor_value - 2;
3991 phaseinc = pi_value;
3992 }
3993
3994 /* This should not happen with any sane values */
3995 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3996 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3997 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3998 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3999
4000 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
12d7ceed 4001 clock,
e615efe4
ED		 4002 auxdiv,
4003 divsel,
4004 phasedir,
4005 phaseinc);
4006
4007 /* Program SSCDIVINTPHASE6 */
988d6ee8 4008 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 4009 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4010 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4011 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4012 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4013 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4014 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 4015 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 4016
4017 /* Program SSCAUXDIV */
988d6ee8 4018 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 4019 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4020 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 4021 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 4022
4023 /* Enable modulator and associated divider */
988d6ee8 4024 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 4025 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 4026 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 4027
4028 /* Wait for initialization time */
4029 udelay(24);
4030
4031 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000
DV		 4032
4033 mutex_unlock(&dev_priv->dpio_lock);
e615efe4
ED		 4034}
4035
275f01b2
DV		 4036static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4037 enum pipe pch_transcoder)
4038{
4039 struct drm_device *dev = crtc->base.dev;
4040 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 4041 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
275f01b2
DV		 4042
4043 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4044 I915_READ(HTOTAL(cpu_transcoder)));
4045 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4046 I915_READ(HBLANK(cpu_transcoder)));
4047 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4048 I915_READ(HSYNC(cpu_transcoder)));
4049
4050 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4051 I915_READ(VTOTAL(cpu_transcoder)));
4052 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4053 I915_READ(VBLANK(cpu_transcoder)));
4054 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4055 I915_READ(VSYNC(cpu_transcoder)));
4056 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4057 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4058}
4059
003632d9 4060static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
1fbc0d78
DV		 4061{
4062 struct drm_i915_private *dev_priv = dev->dev_private;
4063 uint32_t temp;
4064
4065 temp = I915_READ(SOUTH_CHICKEN1);
003632d9 4066 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
1fbc0d78
DV		 4067 return;
4068
4069 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4070 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4071
003632d9
ACO		 4072 temp &= ~FDI_BC_BIFURCATION_SELECT;
4073 if (enable)
4074 temp |= FDI_BC_BIFURCATION_SELECT;
4075
4076 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
1fbc0d78
DV		 4077 I915_WRITE(SOUTH_CHICKEN1, temp);
4078 POSTING_READ(SOUTH_CHICKEN1);
4079}
4080
4081static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4082{
4083 struct drm_device *dev = intel_crtc->base.dev;
1fbc0d78
DV		 4084
4085 switch (intel_crtc->pipe) {
4086 case PIPE_A:
4087 break;
4088 case PIPE_B:
6e3c9717 4089 if (intel_crtc->config->fdi_lanes > 2)
003632d9 4090 cpt_set_fdi_bc_bifurcation(dev, false);
1fbc0d78 4091 else
003632d9 4092 cpt_set_fdi_bc_bifurcation(dev, true);
1fbc0d78
DV		 4093
4094 break;
4095 case PIPE_C:
003632d9 4096 cpt_set_fdi_bc_bifurcation(dev, true);
1fbc0d78
DV		 4097
4098 break;
4099 default:
4100 BUG();
4101 }
4102}
4103
f67a559d
JB		 4104/*
4105 * Enable PCH resources required for PCH ports:
4106 * - PCH PLLs
4107 * - FDI training & RX/TX
4108 * - update transcoder timings
4109 * - DP transcoding bits
4110 * - transcoder
4111 */
4112static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 4113{
4114 struct drm_device *dev = crtc->dev;
4115 struct drm_i915_private *dev_priv = dev->dev_private;
4116 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4117 int pipe = intel_crtc->pipe;
ee7b9f93 4118 u32 reg, temp;
2c07245f 4119
ab9412ba 4120 assert_pch_transcoder_disabled(dev_priv, pipe);
e7e164db 4121
1fbc0d78
DV		 4122 if (IS_IVYBRIDGE(dev))
4123 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4124
cd986abb
DV		 4125 /* Write the TU size bits before fdi link training, so that error
4126 * detection works. */
4127 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4128 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4129
c98e9dcf 4130 /* For PCH output, training FDI link */
674cf967 4131 dev_priv->display.fdi_link_train(crtc);
2c07245f 4132
3ad8a208
DV		 4133 /* We need to program the right clock selection before writing the pixel
4134 * mutliplier into the DPLL. */
303b81e0 4135 if (HAS_PCH_CPT(dev)) {
ee7b9f93 4136 u32 sel;
4b645f14 4137
c98e9dcf 4138 temp = I915_READ(PCH_DPLL_SEL);
11887397
DV		 4139 temp |= TRANS_DPLL_ENABLE(pipe);
4140 sel = TRANS_DPLLB_SEL(pipe);
6e3c9717 4141 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
ee7b9f93
JB		 4142 temp |= sel;
4143 else
4144 temp &= ~sel;
c98e9dcf 4145 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 4146 }
5eddb70b 4147
3ad8a208
DV		 4148 /* XXX: pch pll's can be enabled any time before we enable the PCH
4149 * transcoder, and we actually should do this to not upset any PCH
4150 * transcoder that already use the clock when we share it.
4151 *
4152 * Note that enable_shared_dpll tries to do the right thing, but
4153 * get_shared_dpll unconditionally resets the pll - we need that to have
4154 * the right LVDS enable sequence. */
85b3894f 4155 intel_enable_shared_dpll(intel_crtc);
3ad8a208 4156
d9b6cb56
JB		 4157 /* set transcoder timing, panel must allow it */
4158 assert_panel_unlocked(dev_priv, pipe);
275f01b2 4159 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
8db9d77b 4160
303b81e0 4161 intel_fdi_normal_train(crtc);
5e84e1a4 4162
c98e9dcf 4163 /* For PCH DP, enable TRANS_DP_CTL */
6e3c9717 4164 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
dfd07d72 4165 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 4166 reg = TRANS_DP_CTL(pipe);
4167 temp = I915_READ(reg);
4168 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 4169 TRANS_DP_SYNC_MASK |
4170 TRANS_DP_BPC_MASK);
e3ef4479 4171 temp |= TRANS_DP_OUTPUT_ENABLE;
9325c9f0 4172 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 4173
4174 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 4175 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 4176 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 4177 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 4178
4179 switch (intel_trans_dp_port_sel(crtc)) {
4180 case PCH_DP_B:
5eddb70b 4181 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 4182 break;
4183 case PCH_DP_C:
5eddb70b 4184 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 4185 break;
4186 case PCH_DP_D:
5eddb70b 4187 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 4188 break;
4189 default:
e95d41e1 4190 BUG();
32f9d658 4191 }
2c07245f 4192
5eddb70b 4193 I915_WRITE(reg, temp);
6be4a607 4194 }
b52eb4dc 4195
b8a4f404 4196 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 4197}
4198
1507e5bd
PZ		 4199static void lpt_pch_enable(struct drm_crtc *crtc)
4200{
4201 struct drm_device *dev = crtc->dev;
4202 struct drm_i915_private *dev_priv = dev->dev_private;
4203 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 4204 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1507e5bd 4205
ab9412ba 4206 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 4207
8c52b5e8 4208 lpt_program_iclkip(crtc);
1507e5bd 4209
0540e488 4210 /* Set transcoder timing. */
275f01b2 4211 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
1507e5bd 4212
937bb610 4213 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 4214}
4215
716c2e55 4216void intel_put_shared_dpll(struct intel_crtc *crtc)
ee7b9f93 4217{
e2b78267 4218 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
ee7b9f93
JB		 4219
4220 if (pll == NULL)
4221 return;
4222
3e369b76 4223 if (!(pll->config.crtc_mask & (1 << crtc->pipe))) {
1e6f2ddc 4224 WARN(1, "bad %s crtc mask\n", pll->name);
ee7b9f93
JB		 4225 return;
4226 }
4227
3e369b76
ACO		 4228 pll->config.crtc_mask &= ~(1 << crtc->pipe);
4229 if (pll->config.crtc_mask == 0) {
f4a091c7
DV		 4230 WARN_ON(pll->on);
4231 WARN_ON(pll->active);
4232 }
4233
6e3c9717 4234 crtc->config->shared_dpll = DPLL_ID_PRIVATE;
ee7b9f93
JB		 4235}
4236
190f68c5
ACO		 4237struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4238 struct intel_crtc_state *crtc_state)
ee7b9f93 4239{
e2b78267 4240 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8bd31e67 4241 struct intel_shared_dpll *pll;
e2b78267 4242 enum intel_dpll_id i;
ee7b9f93 4243
98b6bd99
DV		 4244 if (HAS_PCH_IBX(dev_priv->dev)) {
4245 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
d94ab068 4246 i = (enum intel_dpll_id) crtc->pipe;
e72f9fbf 4247 pll = &dev_priv->shared_dplls[i];
98b6bd99 4248
46edb027
DV		 4249 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4250 crtc->base.base.id, pll->name);
98b6bd99 4251
8bd31e67 4252 WARN_ON(pll->new_config->crtc_mask);
f2a69f44 4253
98b6bd99
DV		 4254 goto found;
4255 }
4256
bcddf610
S		 4257 if (IS_BROXTON(dev_priv->dev)) {
4258 /* PLL is attached to port in bxt */
4259 struct intel_encoder *encoder;
4260 struct intel_digital_port *intel_dig_port;
4261
4262 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4263 if (WARN_ON(!encoder))
4264 return NULL;
4265
4266 intel_dig_port = enc_to_dig_port(&encoder->base);
4267 /* 1:1 mapping between ports and PLLs */
4268 i = (enum intel_dpll_id)intel_dig_port->port;
4269 pll = &dev_priv->shared_dplls[i];
4270 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4271 crtc->base.base.id, pll->name);
4272 WARN_ON(pll->new_config->crtc_mask);
4273
4274 goto found;
4275 }
4276
e72f9fbf
DV		 4277 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4278 pll = &dev_priv->shared_dplls[i];
ee7b9f93
JB		 4279
4280 /* Only want to check enabled timings first */
8bd31e67 4281 if (pll->new_config->crtc_mask == 0)
ee7b9f93
JB		 4282 continue;
4283
190f68c5 4284 if (memcmp(&crtc_state->dpll_hw_state,
8bd31e67
ACO		 4285 &pll->new_config->hw_state,
4286 sizeof(pll->new_config->hw_state)) == 0) {
4287 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
1e6f2ddc 4288 crtc->base.base.id, pll->name,
8bd31e67
ACO		 4289 pll->new_config->crtc_mask,
4290 pll->active);
ee7b9f93
JB		 4291 goto found;
4292 }
4293 }
4294
4295 /* Ok no matching timings, maybe there's a free one? */
e72f9fbf
DV		 4296 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4297 pll = &dev_priv->shared_dplls[i];
8bd31e67 4298 if (pll->new_config->crtc_mask == 0) {
46edb027
DV		 4299 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4300 crtc->base.base.id, pll->name);
ee7b9f93
JB		 4301 goto found;
4302 }
4303 }
4304
4305 return NULL;
4306
4307found:
8bd31e67 4308 if (pll->new_config->crtc_mask == 0)
190f68c5 4309 pll->new_config->hw_state = crtc_state->dpll_hw_state;
f2a69f44 4310
190f68c5 4311 crtc_state->shared_dpll = i;
46edb027
DV		 4312 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4313 pipe_name(crtc->pipe));
ee7b9f93 4314
8bd31e67 4315 pll->new_config->crtc_mask |= 1 << crtc->pipe;
e04c7350 4316
ee7b9f93
JB		 4317 return pll;
4318}
4319
8bd31e67
ACO		 4320/**
4321 * intel_shared_dpll_start_config - start a new PLL staged config
4322 * @dev_priv: DRM device
4323 * @clear_pipes: mask of pipes that will have their PLLs freed
4324 *
4325 * Starts a new PLL staged config, copying the current config but
4326 * releasing the references of pipes specified in clear_pipes.
4327 */
4328static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv,
4329 unsigned clear_pipes)
4330{
4331 struct intel_shared_dpll *pll;
4332 enum intel_dpll_id i;
4333
4334 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4335 pll = &dev_priv->shared_dplls[i];
4336
4337 pll->new_config = kmemdup(&pll->config, sizeof pll->config,
4338 GFP_KERNEL);
4339 if (!pll->new_config)
4340 goto cleanup;
4341
4342 pll->new_config->crtc_mask &= ~clear_pipes;
4343 }
4344
4345 return 0;
4346
4347cleanup:
4348 while (--i >= 0) {
4349 pll = &dev_priv->shared_dplls[i];
f354d733 4350 kfree(pll->new_config);
8bd31e67
ACO		 4351 pll->new_config = NULL;
4352 }
4353
4354 return -ENOMEM;
4355}
4356
4357static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv)
4358{
4359 struct intel_shared_dpll *pll;
4360 enum intel_dpll_id i;
4361
4362 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4363 pll = &dev_priv->shared_dplls[i];
4364
4365 WARN_ON(pll->new_config == &pll->config);
4366
4367 pll->config = *pll->new_config;
4368 kfree(pll->new_config);
4369 pll->new_config = NULL;
4370 }
4371}
4372
4373static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv)
4374{
4375 struct intel_shared_dpll *pll;
4376 enum intel_dpll_id i;
4377
4378 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4379 pll = &dev_priv->shared_dplls[i];
4380
4381 WARN_ON(pll->new_config == &pll->config);
4382
4383 kfree(pll->new_config);
4384 pll->new_config = NULL;
4385 }
4386}
4387
a1520318 4388static void cpt_verify_modeset(struct drm_device *dev, int pipe)
d4270e57
JB		 4389{
4390 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 4391 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 4392 u32 temp;
4393
4394 temp = I915_READ(dslreg);
4395 udelay(500);
4396 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 4397 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 4398 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 4399 }
4400}
4401
a1b2278e
CK		 4402/**
4403 * skl_update_scaler_users - Stages update to crtc's scaler state
4404 * @intel_crtc: crtc
4405 * @crtc_state: crtc_state
4406 * @plane: plane (NULL indicates crtc is requesting update)
4407 * @plane_state: plane's state
4408 * @force_detach: request unconditional detachment of scaler
4409 *
4410 * This function updates scaler state for requested plane or crtc.
4411 * To request scaler usage update for a plane, caller shall pass plane pointer.
4412 * To request scaler usage update for crtc, caller shall pass plane pointer
4413 * as NULL.
4414 *
4415 * Return
4416 * 0 - scaler_usage updated successfully
4417 * error - requested scaling cannot be supported or other error condition
4418 */
4419int
4420skl_update_scaler_users(
4421 struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state,
4422 struct intel_plane *intel_plane, struct intel_plane_state *plane_state,
4423 int force_detach)
4424{
4425 int need_scaling;
4426 int idx;
4427 int src_w, src_h, dst_w, dst_h;
4428 int *scaler_id;
4429 struct drm_framebuffer *fb;
4430 struct intel_crtc_scaler_state *scaler_state;
6156a456 4431 unsigned int rotation;
a1b2278e
CK		 4432
4433 if (!intel_crtc || !crtc_state)
4434 return 0;
4435
4436 scaler_state = &crtc_state->scaler_state;
4437
4438 idx = intel_plane ? drm_plane_index(&intel_plane->base) : SKL_CRTC_INDEX;
4439 fb = intel_plane ? plane_state->base.fb : NULL;
4440
4441 if (intel_plane) {
4442 src_w = drm_rect_width(&plane_state->src) >> 16;
4443 src_h = drm_rect_height(&plane_state->src) >> 16;
4444 dst_w = drm_rect_width(&plane_state->dst);
4445 dst_h = drm_rect_height(&plane_state->dst);
4446 scaler_id = &plane_state->scaler_id;
6156a456 4447 rotation = plane_state->base.rotation;
a1b2278e
CK		 4448 } else {
4449 struct drm_display_mode *adjusted_mode =
4450 &crtc_state->base.adjusted_mode;
4451 src_w = crtc_state->pipe_src_w;
4452 src_h = crtc_state->pipe_src_h;
4453 dst_w = adjusted_mode->hdisplay;
4454 dst_h = adjusted_mode->vdisplay;
4455 scaler_id = &scaler_state->scaler_id;
6156a456 4456 rotation = DRM_ROTATE_0;
a1b2278e 4457 }
6156a456
CK		 4458
4459 need_scaling = intel_rotation_90_or_270(rotation) ?
4460 (src_h != dst_w || src_w != dst_h):
4461 (src_w != dst_w || src_h != dst_h);
a1b2278e
CK		 4462
4463 /*
4464 * if plane is being disabled or scaler is no more required or force detach
4465 * - free scaler binded to this plane/crtc
4466 * - in order to do this, update crtc->scaler_usage
4467 *
4468 * Here scaler state in crtc_state is set free so that
4469 * scaler can be assigned to other user. Actual register
4470 * update to free the scaler is done in plane/panel-fit programming.
4471 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4472 */
4473 if (force_detach || !need_scaling || (intel_plane &&
4474 (!fb || !plane_state->visible))) {
4475 if (*scaler_id >= 0) {
4476 scaler_state->scaler_users &= ~(1 << idx);
4477 scaler_state->scalers[*scaler_id].in_use = 0;
4478
4479 DRM_DEBUG_KMS("Staged freeing scaler id %d.%d from %s:%d "
4480 "crtc_state = %p scaler_users = 0x%x\n",
4481 intel_crtc->pipe, *scaler_id, intel_plane ? "PLANE" : "CRTC",
4482 intel_plane ? intel_plane->base.base.id :
4483 intel_crtc->base.base.id, crtc_state,
4484 scaler_state->scaler_users);
4485 *scaler_id = -1;
4486 }
4487 return 0;
4488 }
4489
4490 /* range checks */
4491 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4492 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4493
4494 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4495 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4496 DRM_DEBUG_KMS("%s:%d scaler_user index %u.%u: src %ux%u dst %ux%u "
4497 "size is out of scaler range\n",
4498 intel_plane ? "PLANE" : "CRTC",
4499 intel_plane ? intel_plane->base.base.id : intel_crtc->base.base.id,
4500 intel_crtc->pipe, idx, src_w, src_h, dst_w, dst_h);
4501 return -EINVAL;
4502 }
4503
4504 /* check colorkey */
4505 if (intel_plane && intel_plane->ckey.flags != I915_SET_COLORKEY_NONE) {
4506 DRM_DEBUG_KMS("PLANE:%d scaling with color key not allowed",
4507 intel_plane->base.base.id);
4508 return -EINVAL;
4509 }
4510
4511 /* Check src format */
4512 if (intel_plane) {
4513 switch (fb->pixel_format) {
4514 case DRM_FORMAT_RGB565:
4515 case DRM_FORMAT_XBGR8888:
4516 case DRM_FORMAT_XRGB8888:
4517 case DRM_FORMAT_ABGR8888:
4518 case DRM_FORMAT_ARGB8888:
4519 case DRM_FORMAT_XRGB2101010:
a1b2278e 4520 case DRM_FORMAT_XBGR2101010:
a1b2278e
CK		 4521 case DRM_FORMAT_YUYV:
4522 case DRM_FORMAT_YVYU:
4523 case DRM_FORMAT_UYVY:
4524 case DRM_FORMAT_VYUY:
4525 break;
4526 default:
4527 DRM_DEBUG_KMS("PLANE:%d FB:%d unsupported scaling format 0x%x\n",
4528 intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4529 return -EINVAL;
4530 }
4531 }
4532
4533 /* mark this plane as a scaler user in crtc_state */
4534 scaler_state->scaler_users |= (1 << idx);
4535 DRM_DEBUG_KMS("%s:%d staged scaling request for %ux%u->%ux%u "
4536 "crtc_state = %p scaler_users = 0x%x\n",
4537 intel_plane ? "PLANE" : "CRTC",
4538 intel_plane ? intel_plane->base.base.id : intel_crtc->base.base.id,
4539 src_w, src_h, dst_w, dst_h, crtc_state, scaler_state->scaler_users);
4540 return 0;
4541}
4542
4543static void skylake_pfit_update(struct intel_crtc *crtc, int enable)
bd2e244f
JB		 4544{
4545 struct drm_device *dev = crtc->base.dev;
4546 struct drm_i915_private *dev_priv = dev->dev_private;
4547 int pipe = crtc->pipe;
a1b2278e
CK		 4548 struct intel_crtc_scaler_state *scaler_state =
4549 &crtc->config->scaler_state;
4550
4551 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4552
4553 /* To update pfit, first update scaler state */
4554 skl_update_scaler_users(crtc, crtc->config, NULL, NULL, !enable);
4555 intel_atomic_setup_scalers(crtc->base.dev, crtc, crtc->config);
4556 skl_detach_scalers(crtc);
4557 if (!enable)
4558 return;
bd2e244f 4559
6e3c9717 4560 if (crtc->config->pch_pfit.enabled) {
a1b2278e
CK		 4561 int id;
4562
4563 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4564 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4565 return;
4566 }
4567
4568 id = scaler_state->scaler_id;
4569 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4570 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4571 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4572 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4573
4574 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
bd2e244f
JB		 4575 }
4576}
4577
b074cec8
JB		 4578static void ironlake_pfit_enable(struct intel_crtc *crtc)
4579{
4580 struct drm_device *dev = crtc->base.dev;
4581 struct drm_i915_private *dev_priv = dev->dev_private;
4582 int pipe = crtc->pipe;
4583
6e3c9717 4584 if (crtc->config->pch_pfit.enabled) {
b074cec8
JB		 4585 /* Force use of hard-coded filter coefficients
4586 * as some pre-programmed values are broken,
4587 * e.g. x201.
4588 */
4589 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4590 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4591 PF_PIPE_SEL_IVB(pipe));
4592 else
4593 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
6e3c9717
ACO		 4594 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4595 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
d4270e57
JB		 4596 }
4597}
4598
4a3b8769 4599static void intel_enable_sprite_planes(struct drm_crtc *crtc)
bb53d4ae
VS		 4600{
4601 struct drm_device *dev = crtc->dev;
4602 enum pipe pipe = to_intel_crtc(crtc)->pipe;
af2b653b 4603 struct drm_plane *plane;
bb53d4ae
VS		 4604 struct intel_plane *intel_plane;
4605
af2b653b
MR		 4606 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4607 intel_plane = to_intel_plane(plane);
bb53d4ae
VS		 4608 if (intel_plane->pipe == pipe)
4609 intel_plane_restore(&intel_plane->base);
af2b653b 4610 }
bb53d4ae
VS		 4611}
4612
20bc8673 4613void hsw_enable_ips(struct intel_crtc *crtc)
d77e4531 4614{
cea165c3
VS		 4615 struct drm_device *dev = crtc->base.dev;
4616 struct drm_i915_private *dev_priv = dev->dev_private;
d77e4531 4617
6e3c9717 4618 if (!crtc->config->ips_enabled)
d77e4531
PZ		 4619 return;
4620
cea165c3
VS		 4621 /* We can only enable IPS after we enable a plane and wait for a vblank */
4622 intel_wait_for_vblank(dev, crtc->pipe);
4623
d77e4531 4624 assert_plane_enabled(dev_priv, crtc->plane);
cea165c3 4625 if (IS_BROADWELL(dev)) {
2a114cc1
BW		 4626 mutex_lock(&dev_priv->rps.hw_lock);
4627 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4628 mutex_unlock(&dev_priv->rps.hw_lock);
4629 /* Quoting Art Runyan: "its not safe to expect any particular
4630 * value in IPS_CTL bit 31 after enabling IPS through the
e59150dc
JB		 4631 * mailbox." Moreover, the mailbox may return a bogus state,
4632 * so we need to just enable it and continue on.
2a114cc1
BW		 4633 */
4634 } else {
4635 I915_WRITE(IPS_CTL, IPS_ENABLE);
4636 /* The bit only becomes 1 in the next vblank, so this wait here
4637 * is essentially intel_wait_for_vblank. If we don't have this
4638 * and don't wait for vblanks until the end of crtc_enable, then
4639 * the HW state readout code will complain that the expected
4640 * IPS_CTL value is not the one we read. */
4641 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4642 DRM_ERROR("Timed out waiting for IPS enable\n");
4643 }
d77e4531
PZ		 4644}
4645
20bc8673 4646void hsw_disable_ips(struct intel_crtc *crtc)
d77e4531
PZ		 4647{
4648 struct drm_device *dev = crtc->base.dev;
4649 struct drm_i915_private *dev_priv = dev->dev_private;
4650
6e3c9717 4651 if (!crtc->config->ips_enabled)
d77e4531
PZ		 4652 return;
4653
4654 assert_plane_enabled(dev_priv, crtc->plane);
23d0b130 4655 if (IS_BROADWELL(dev)) {
2a114cc1
BW		 4656 mutex_lock(&dev_priv->rps.hw_lock);
4657 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4658 mutex_unlock(&dev_priv->rps.hw_lock);
23d0b130
BW		 4659 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4660 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4661 DRM_ERROR("Timed out waiting for IPS disable\n");
e59150dc 4662 } else {
2a114cc1 4663 I915_WRITE(IPS_CTL, 0);
e59150dc
JB		 4664 POSTING_READ(IPS_CTL);
4665 }
d77e4531
PZ		 4666
4667 /* We need to wait for a vblank before we can disable the plane. */
4668 intel_wait_for_vblank(dev, crtc->pipe);
4669}
4670
4671/** Loads the palette/gamma unit for the CRTC with the prepared values */
4672static void intel_crtc_load_lut(struct drm_crtc *crtc)
4673{
4674 struct drm_device *dev = crtc->dev;
4675 struct drm_i915_private *dev_priv = dev->dev_private;
4676 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4677 enum pipe pipe = intel_crtc->pipe;
4678 int palreg = PALETTE(pipe);
4679 int i;
4680 bool reenable_ips = false;
4681
4682 /* The clocks have to be on to load the palette. */
83d65738 4683 if (!crtc->state->enable || !intel_crtc->active)
d77e4531
PZ		 4684 return;
4685
50360403 4686 if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
409ee761 4687 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
d77e4531
PZ		 4688 assert_dsi_pll_enabled(dev_priv);
4689 else
4690 assert_pll_enabled(dev_priv, pipe);
4691 }
4692
4693 /* use legacy palette for Ironlake */
7a1db49a 4694 if (!HAS_GMCH_DISPLAY(dev))
d77e4531
PZ		 4695 palreg = LGC_PALETTE(pipe);
4696
4697 /* Workaround : Do not read or write the pipe palette/gamma data while
4698 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4699 */
6e3c9717 4700 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
d77e4531
PZ		 4701 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4702 GAMMA_MODE_MODE_SPLIT)) {
4703 hsw_disable_ips(intel_crtc);
4704 reenable_ips = true;
4705 }
4706
4707 for (i = 0; i < 256; i++) {
4708 I915_WRITE(palreg + 4 * i,
4709 (intel_crtc->lut_r[i] << 16) |
4710 (intel_crtc->lut_g[i] << 8) |
4711 intel_crtc->lut_b[i]);
4712 }
4713
4714 if (reenable_ips)
4715 hsw_enable_ips(intel_crtc);
4716}
4717
7cac945f 4718static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
d3eedb1a 4719{
7cac945f 4720 if (intel_crtc->overlay) {
d3eedb1a
VS		 4721 struct drm_device *dev = intel_crtc->base.dev;
4722 struct drm_i915_private *dev_priv = dev->dev_private;
4723
4724 mutex_lock(&dev->struct_mutex);
4725 dev_priv->mm.interruptible = false;
4726 (void) intel_overlay_switch_off(intel_crtc->overlay);
4727 dev_priv->mm.interruptible = true;
4728 mutex_unlock(&dev->struct_mutex);
4729 }
4730
4731 /* Let userspace switch the overlay on again. In most cases userspace
4732 * has to recompute where to put it anyway.
4733 */
4734}
4735
87d4300a
ML		 4736/**
4737 * intel_post_enable_primary - Perform operations after enabling primary plane
4738 * @crtc: the CRTC whose primary plane was just enabled
4739 *
4740 * Performs potentially sleeping operations that must be done after the primary
4741 * plane is enabled, such as updating FBC and IPS. Note that this may be
4742 * called due to an explicit primary plane update, or due to an implicit
4743 * re-enable that is caused when a sprite plane is updated to no longer
4744 * completely hide the primary plane.
4745 */
4746static void
4747intel_post_enable_primary(struct drm_crtc *crtc)
a5c4d7bc
VS		 4748{
4749 struct drm_device *dev = crtc->dev;
87d4300a 4750 struct drm_i915_private *dev_priv = dev->dev_private;
a5c4d7bc
VS		 4751 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4752 int pipe = intel_crtc->pipe;
a5c4d7bc 4753
87d4300a
ML		 4754 /*
4755 * BDW signals flip done immediately if the plane
4756 * is disabled, even if the plane enable is already
4757 * armed to occur at the next vblank :(
4758 */
4759 if (IS_BROADWELL(dev))
4760 intel_wait_for_vblank(dev, pipe);
a5c4d7bc 4761
87d4300a
ML		 4762 /*
4763 * FIXME IPS should be fine as long as one plane is
4764 * enabled, but in practice it seems to have problems
4765 * when going from primary only to sprite only and vice
4766 * versa.
4767 */
a5c4d7bc
VS		 4768 hsw_enable_ips(intel_crtc);
4769
4770 mutex_lock(&dev->struct_mutex);
7ff0ebcc 4771 intel_fbc_update(dev);
a5c4d7bc 4772 mutex_unlock(&dev->struct_mutex);
f99d7069
DV		 4773
4774 /*
87d4300a
ML		 4775 * Gen2 reports pipe underruns whenever all planes are disabled.
4776 * So don't enable underrun reporting before at least some planes
4777 * are enabled.
4778 * FIXME: Need to fix the logic to work when we turn off all planes
4779 * but leave the pipe running.
f99d7069 4780 */
87d4300a
ML		 4781 if (IS_GEN2(dev))
4782 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4783
4784 /* Underruns don't raise interrupts, so check manually. */
4785 if (HAS_GMCH_DISPLAY(dev))
4786 i9xx_check_fifo_underruns(dev_priv);
a5c4d7bc
VS		 4787}
4788
87d4300a
ML		 4789/**
4790 * intel_pre_disable_primary - Perform operations before disabling primary plane
4791 * @crtc: the CRTC whose primary plane is to be disabled
4792 *
4793 * Performs potentially sleeping operations that must be done before the
4794 * primary plane is disabled, such as updating FBC and IPS. Note that this may
4795 * be called due to an explicit primary plane update, or due to an implicit
4796 * disable that is caused when a sprite plane completely hides the primary
4797 * plane.
4798 */
4799static void
4800intel_pre_disable_primary(struct drm_crtc *crtc)
a5c4d7bc
VS		 4801{
4802 struct drm_device *dev = crtc->dev;
4803 struct drm_i915_private *dev_priv = dev->dev_private;
4804 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4805 int pipe = intel_crtc->pipe;
a5c4d7bc 4806
87d4300a
ML		 4807 /*
4808 * Gen2 reports pipe underruns whenever all planes are disabled.
4809 * So diasble underrun reporting before all the planes get disabled.
4810 * FIXME: Need to fix the logic to work when we turn off all planes
4811 * but leave the pipe running.
4812 */
4813 if (IS_GEN2(dev))
4814 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
a5c4d7bc 4815
87d4300a
ML		 4816 /*
4817 * Vblank time updates from the shadow to live plane control register
4818 * are blocked if the memory self-refresh mode is active at that
4819 * moment. So to make sure the plane gets truly disabled, disable
4820 * first the self-refresh mode. The self-refresh enable bit in turn
4821 * will be checked/applied by the HW only at the next frame start
4822 * event which is after the vblank start event, so we need to have a
4823 * wait-for-vblank between disabling the plane and the pipe.
4824 */
4825 if (HAS_GMCH_DISPLAY(dev))
4826 intel_set_memory_cxsr(dev_priv, false);
4827
4828 mutex_lock(&dev->struct_mutex);
e35fef21 4829 if (dev_priv->fbc.crtc == intel_crtc)
7ff0ebcc 4830 intel_fbc_disable(dev);
87d4300a 4831 mutex_unlock(&dev->struct_mutex);
a5c4d7bc 4832
87d4300a
ML		 4833 /*
4834 * FIXME IPS should be fine as long as one plane is
4835 * enabled, but in practice it seems to have problems
4836 * when going from primary only to sprite only and vice
4837 * versa.
4838 */
a5c4d7bc 4839 hsw_disable_ips(intel_crtc);
87d4300a
ML		 4840}
4841
4842static void intel_crtc_enable_planes(struct drm_crtc *crtc)
4843{
87d4300a
ML		 4844 intel_enable_primary_hw_plane(crtc->primary, crtc);
4845 intel_enable_sprite_planes(crtc);
4846 intel_crtc_update_cursor(crtc, true);
87d4300a
ML		 4847
4848 intel_post_enable_primary(crtc);
4849}
4850
4851static void intel_crtc_disable_planes(struct drm_crtc *crtc)
4852{
4853 struct drm_device *dev = crtc->dev;
4854 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4855 struct intel_plane *intel_plane;
4856 int pipe = intel_crtc->pipe;
4857
4858 intel_crtc_wait_for_pending_flips(crtc);
4859
4860 intel_pre_disable_primary(crtc);
a5c4d7bc 4861
7cac945f 4862 intel_crtc_dpms_overlay_disable(intel_crtc);
27321ae8
ML		 4863 for_each_intel_plane(dev, intel_plane) {
4864 if (intel_plane->pipe == pipe) {
4865 struct drm_crtc *from = intel_plane->base.crtc;
4866
4867 intel_plane->disable_plane(&intel_plane->base,
4868 from ?: crtc, true);
4869 }
4870 }
f98551ae 4871
f99d7069
DV		 4872 /*
4873 * FIXME: Once we grow proper nuclear flip support out of this we need
4874 * to compute the mask of flip planes precisely. For the time being
4875 * consider this a flip to a NULL plane.
4876 */
4877 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
a5c4d7bc
VS		 4878}
4879
f67a559d
JB		 4880static void ironlake_crtc_enable(struct drm_crtc *crtc)
4881{
4882 struct drm_device *dev = crtc->dev;
4883 struct drm_i915_private *dev_priv = dev->dev_private;
4884 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 4885 struct intel_encoder *encoder;
f67a559d 4886 int pipe = intel_crtc->pipe;
f67a559d 4887
83d65738 4888 WARN_ON(!crtc->state->enable);
08a48469 4889
f67a559d
JB		 4890 if (intel_crtc->active)
4891 return;
4892
6e3c9717 4893 if (intel_crtc->config->has_pch_encoder)
b14b1055
DV		 4894 intel_prepare_shared_dpll(intel_crtc);
4895
6e3c9717 4896 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 4897 intel_dp_set_m_n(intel_crtc, M1_N1);
29407aab
DV		 4898
4899 intel_set_pipe_timings(intel_crtc);
4900
6e3c9717 4901 if (intel_crtc->config->has_pch_encoder) {
29407aab 4902 intel_cpu_transcoder_set_m_n(intel_crtc,
6e3c9717 4903 &intel_crtc->config->fdi_m_n, NULL);
29407aab
DV		 4904 }
4905
4906 ironlake_set_pipeconf(crtc);
4907
f67a559d 4908 intel_crtc->active = true;
8664281b 4909
a72e4c9f
DV		 4910 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4911 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
8664281b 4912
f6736a1a 4913 for_each_encoder_on_crtc(dev, crtc, encoder)
952735ee
DV		 4914 if (encoder->pre_enable)
4915 encoder->pre_enable(encoder);
f67a559d 4916
6e3c9717 4917 if (intel_crtc->config->has_pch_encoder) {
fff367c7
DV		 4918 /* Note: FDI PLL enabling _must_ be done before we enable the
4919 * cpu pipes, hence this is separate from all the other fdi/pch
4920 * enabling. */
88cefb6c 4921 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 4922 } else {
4923 assert_fdi_tx_disabled(dev_priv, pipe);
4924 assert_fdi_rx_disabled(dev_priv, pipe);
4925 }
f67a559d 4926
b074cec8 4927 ironlake_pfit_enable(intel_crtc);
f67a559d 4928
9c54c0dd
JB		 4929 /*
4930 * On ILK+ LUT must be loaded before the pipe is running but with
4931 * clocks enabled
4932 */
4933 intel_crtc_load_lut(crtc);
4934
f37fcc2a 4935 intel_update_watermarks(crtc);
e1fdc473 4936 intel_enable_pipe(intel_crtc);
f67a559d 4937
6e3c9717 4938 if (intel_crtc->config->has_pch_encoder)
f67a559d 4939 ironlake_pch_enable(crtc);
c98e9dcf 4940
f9b61ff6
DV		 4941 assert_vblank_disabled(crtc);
4942 drm_crtc_vblank_on(crtc);
4943
fa5c73b1
DV		 4944 for_each_encoder_on_crtc(dev, crtc, encoder)
4945 encoder->enable(encoder);
61b77ddd
DV		 4946
4947 if (HAS_PCH_CPT(dev))
a1520318 4948 cpt_verify_modeset(dev, intel_crtc->pipe);
6be4a607
JB		 4949}
4950
42db64ef
PZ		 4951/* IPS only exists on ULT machines and is tied to pipe A. */
4952static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4953{
f5adf94e 4954 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
42db64ef
PZ		 4955}
4956
e4916946
PZ		 4957/*
4958 * This implements the workaround described in the "notes" section of the mode
4959 * set sequence documentation. When going from no pipes or single pipe to
4960 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4961 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4962 */
4963static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4964{
4965 struct drm_device *dev = crtc->base.dev;
4966 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4967
4968 /* We want to get the other_active_crtc only if there's only 1 other
4969 * active crtc. */
d3fcc808 4970 for_each_intel_crtc(dev, crtc_it) {
e4916946
PZ		 4971 if (!crtc_it->active || crtc_it == crtc)
4972 continue;
4973
4974 if (other_active_crtc)
4975 return;
4976
4977 other_active_crtc = crtc_it;
4978 }
4979 if (!other_active_crtc)
4980 return;
4981
4982 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4983 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4984}
4985
4f771f10
PZ		 4986static void haswell_crtc_enable(struct drm_crtc *crtc)
4987{
4988 struct drm_device *dev = crtc->dev;
4989 struct drm_i915_private *dev_priv = dev->dev_private;
4990 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4991 struct intel_encoder *encoder;
4992 int pipe = intel_crtc->pipe;
4f771f10 4993
83d65738 4994 WARN_ON(!crtc->state->enable);
4f771f10
PZ		 4995
4996 if (intel_crtc->active)
4997 return;
4998
df8ad70c
DV		 4999 if (intel_crtc_to_shared_dpll(intel_crtc))
5000 intel_enable_shared_dpll(intel_crtc);
5001
6e3c9717 5002 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 5003 intel_dp_set_m_n(intel_crtc, M1_N1);
229fca97
DV		 5004
5005 intel_set_pipe_timings(intel_crtc);
5006
6e3c9717
ACO		 5007 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
5008 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
5009 intel_crtc->config->pixel_multiplier - 1);
ebb69c95
CT		 5010 }
5011
6e3c9717 5012 if (intel_crtc->config->has_pch_encoder) {
229fca97 5013 intel_cpu_transcoder_set_m_n(intel_crtc,
6e3c9717 5014 &intel_crtc->config->fdi_m_n, NULL);
229fca97
DV		 5015 }
5016
5017 haswell_set_pipeconf(crtc);
5018
5019 intel_set_pipe_csc(crtc);
5020
4f771f10 5021 intel_crtc->active = true;
8664281b 5022
a72e4c9f 5023 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4f771f10
PZ		 5024 for_each_encoder_on_crtc(dev, crtc, encoder)
5025 if (encoder->pre_enable)
5026 encoder->pre_enable(encoder);
5027
6e3c9717 5028 if (intel_crtc->config->has_pch_encoder) {
a72e4c9f
DV		 5029 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5030 true);
4fe9467d
ID		 5031 dev_priv->display.fdi_link_train(crtc);
5032 }
5033
1f544388 5034 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 5035
ff6d9f55 5036 if (INTEL_INFO(dev)->gen == 9)
a1b2278e 5037 skylake_pfit_update(intel_crtc, 1);
ff6d9f55 5038 else if (INTEL_INFO(dev)->gen < 9)
bd2e244f 5039 ironlake_pfit_enable(intel_crtc);
ff6d9f55
JB		 5040 else
5041 MISSING_CASE(INTEL_INFO(dev)->gen);
4f771f10
PZ		 5042
5043 /*
5044 * On ILK+ LUT must be loaded before the pipe is running but with
5045 * clocks enabled
5046 */
5047 intel_crtc_load_lut(crtc);
5048
1f544388 5049 intel_ddi_set_pipe_settings(crtc);
8228c251 5050 intel_ddi_enable_transcoder_func(crtc);
4f771f10 5051
f37fcc2a 5052 intel_update_watermarks(crtc);
e1fdc473 5053 intel_enable_pipe(intel_crtc);
42db64ef 5054
6e3c9717 5055 if (intel_crtc->config->has_pch_encoder)
1507e5bd 5056 lpt_pch_enable(crtc);
4f771f10 5057
6e3c9717 5058 if (intel_crtc->config->dp_encoder_is_mst)
0e32b39c
DA		 5059 intel_ddi_set_vc_payload_alloc(crtc, true);
5060
f9b61ff6
DV		 5061 assert_vblank_disabled(crtc);
5062 drm_crtc_vblank_on(crtc);
5063
8807e55b 5064 for_each_encoder_on_crtc(dev, crtc, encoder) {
4f771f10 5065 encoder->enable(encoder);
8807e55b
JN		 5066 intel_opregion_notify_encoder(encoder, true);
5067 }
4f771f10 5068
e4916946
PZ		 5069 /* If we change the relative order between pipe/planes enabling, we need
5070 * to change the workaround. */
5071 haswell_mode_set_planes_workaround(intel_crtc);
4f771f10
PZ		 5072}
5073
3f8dce3a
DV		 5074static void ironlake_pfit_disable(struct intel_crtc *crtc)
5075{
5076 struct drm_device *dev = crtc->base.dev;
5077 struct drm_i915_private *dev_priv = dev->dev_private;
5078 int pipe = crtc->pipe;
5079
5080 /* To avoid upsetting the power well on haswell only disable the pfit if
5081 * it's in use. The hw state code will make sure we get this right. */
6e3c9717 5082 if (crtc->config->pch_pfit.enabled) {
3f8dce3a
DV		 5083 I915_WRITE(PF_CTL(pipe), 0);
5084 I915_WRITE(PF_WIN_POS(pipe), 0);
5085 I915_WRITE(PF_WIN_SZ(pipe), 0);
5086 }
5087}
5088
6be4a607
JB		 5089static void ironlake_crtc_disable(struct drm_crtc *crtc)
5090{
5091 struct drm_device *dev = crtc->dev;
5092 struct drm_i915_private *dev_priv = dev->dev_private;
5093 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 5094 struct intel_encoder *encoder;
6be4a607 5095 int pipe = intel_crtc->pipe;
5eddb70b 5096 u32 reg, temp;
b52eb4dc 5097
f7abfe8b
CW		 5098 if (!intel_crtc->active)
5099 return;
5100
ea9d758d
DV		 5101 for_each_encoder_on_crtc(dev, crtc, encoder)
5102 encoder->disable(encoder);
5103
f9b61ff6
DV		 5104 drm_crtc_vblank_off(crtc);
5105 assert_vblank_disabled(crtc);
5106
6e3c9717 5107 if (intel_crtc->config->has_pch_encoder)
a72e4c9f 5108 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
d925c59a 5109
575f7ab7 5110 intel_disable_pipe(intel_crtc);
32f9d658 5111
3f8dce3a 5112 ironlake_pfit_disable(intel_crtc);
2c07245f 5113
bf49ec8c
DV		 5114 for_each_encoder_on_crtc(dev, crtc, encoder)
5115 if (encoder->post_disable)
5116 encoder->post_disable(encoder);
2c07245f 5117
6e3c9717 5118 if (intel_crtc->config->has_pch_encoder) {
d925c59a 5119 ironlake_fdi_disable(crtc);
913d8d11 5120
d925c59a 5121 ironlake_disable_pch_transcoder(dev_priv, pipe);
6be4a607 5122
d925c59a
DV		 5123 if (HAS_PCH_CPT(dev)) {
5124 /* disable TRANS_DP_CTL */
5125 reg = TRANS_DP_CTL(pipe);
5126 temp = I915_READ(reg);
5127 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5128 TRANS_DP_PORT_SEL_MASK);
5129 temp |= TRANS_DP_PORT_SEL_NONE;
5130 I915_WRITE(reg, temp);
5131
5132 /* disable DPLL_SEL */
5133 temp = I915_READ(PCH_DPLL_SEL);
11887397 5134 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
d925c59a 5135 I915_WRITE(PCH_DPLL_SEL, temp);
9db4a9c7 5136 }
e3421a18 5137
d925c59a 5138 /* disable PCH DPLL */
e72f9fbf 5139 intel_disable_shared_dpll(intel_crtc);
8db9d77b 5140
d925c59a
DV		 5141 ironlake_fdi_pll_disable(intel_crtc);
5142 }
6b383a7f 5143
f7abfe8b 5144 intel_crtc->active = false;
46ba614c 5145 intel_update_watermarks(crtc);
d1ebd816
BW		 5146
5147 mutex_lock(&dev->struct_mutex);
7ff0ebcc 5148 intel_fbc_update(dev);
d1ebd816 5149 mutex_unlock(&dev->struct_mutex);
6be4a607 5150}
1b3c7a47 5151
4f771f10 5152static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 5153{
4f771f10
PZ		 5154 struct drm_device *dev = crtc->dev;
5155 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 5156 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10 5157 struct intel_encoder *encoder;
6e3c9717 5158 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
ee7b9f93 5159
4f771f10
PZ		 5160 if (!intel_crtc->active)
5161 return;
5162
8807e55b
JN		 5163 for_each_encoder_on_crtc(dev, crtc, encoder) {
5164 intel_opregion_notify_encoder(encoder, false);
4f771f10 5165 encoder->disable(encoder);
8807e55b 5166 }
4f771f10 5167
f9b61ff6
DV		 5168 drm_crtc_vblank_off(crtc);
5169 assert_vblank_disabled(crtc);
5170
6e3c9717 5171 if (intel_crtc->config->has_pch_encoder)
a72e4c9f
DV		 5172 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5173 false);
575f7ab7 5174 intel_disable_pipe(intel_crtc);
4f771f10 5175
6e3c9717 5176 if (intel_crtc->config->dp_encoder_is_mst)
a4bf214f
VS		 5177 intel_ddi_set_vc_payload_alloc(crtc, false);
5178
ad80a810 5179 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 5180
ff6d9f55 5181 if (INTEL_INFO(dev)->gen == 9)
a1b2278e 5182 skylake_pfit_update(intel_crtc, 0);
ff6d9f55 5183 else if (INTEL_INFO(dev)->gen < 9)
bd2e244f 5184 ironlake_pfit_disable(intel_crtc);
ff6d9f55
JB		 5185 else
5186 MISSING_CASE(INTEL_INFO(dev)->gen);
4f771f10 5187
1f544388 5188 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10 5189
6e3c9717 5190 if (intel_crtc->config->has_pch_encoder) {
ab4d966c 5191 lpt_disable_pch_transcoder(dev_priv);
1ad960f2 5192 intel_ddi_fdi_disable(crtc);
83616634 5193 }
4f771f10 5194
97b040aa
ID		 5195 for_each_encoder_on_crtc(dev, crtc, encoder)
5196 if (encoder->post_disable)
5197 encoder->post_disable(encoder);
5198
4f771f10 5199 intel_crtc->active = false;
46ba614c 5200 intel_update_watermarks(crtc);
4f771f10
PZ		 5201
5202 mutex_lock(&dev->struct_mutex);
7ff0ebcc 5203 intel_fbc_update(dev);
4f771f10 5204 mutex_unlock(&dev->struct_mutex);
df8ad70c
DV		 5205
5206 if (intel_crtc_to_shared_dpll(intel_crtc))
5207 intel_disable_shared_dpll(intel_crtc);
4f771f10
PZ		 5208}
5209
ee7b9f93
JB		 5210static void ironlake_crtc_off(struct drm_crtc *crtc)
5211{
5212 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
e72f9fbf 5213 intel_put_shared_dpll(intel_crtc);
ee7b9f93
JB		 5214}
5215
6441ab5f 5216
2dd24552
JB		 5217static void i9xx_pfit_enable(struct intel_crtc *crtc)
5218{
5219 struct drm_device *dev = crtc->base.dev;
5220 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 5221 struct intel_crtc_state *pipe_config = crtc->config;
2dd24552 5222
681a8504 5223 if (!pipe_config->gmch_pfit.control)
2dd24552
JB		 5224 return;
5225
2dd24552 5226 /*
c0b03411
DV		 5227 * The panel fitter should only be adjusted whilst the pipe is disabled,
5228 * according to register description and PRM.
2dd24552 5229 */
c0b03411
DV		 5230 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5231 assert_pipe_disabled(dev_priv, crtc->pipe);
2dd24552 5232
b074cec8
JB		 5233 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5234 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5a80c45c
DV		 5235
5236 /* Border color in case we don't scale up to the full screen. Black by
5237 * default, change to something else for debugging. */
5238 I915_WRITE(BCLRPAT(crtc->pipe), 0);
2dd24552
JB		 5239}
5240
d05410f9
DA		 5241static enum intel_display_power_domain port_to_power_domain(enum port port)
5242{
5243 switch (port) {
5244 case PORT_A:
5245 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
5246 case PORT_B:
5247 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
5248 case PORT_C:
5249 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
5250 case PORT_D:
5251 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
5252 default:
5253 WARN_ON_ONCE(1);
5254 return POWER_DOMAIN_PORT_OTHER;
5255 }
5256}
5257
77d22dca
ID		 5258#define for_each_power_domain(domain, mask) \
5259 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
5260 if ((1 << (domain)) & (mask))
5261
319be8ae
ID		 5262enum intel_display_power_domain
5263intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5264{
5265 struct drm_device *dev = intel_encoder->base.dev;
5266 struct intel_digital_port *intel_dig_port;
5267
5268 switch (intel_encoder->type) {
5269 case INTEL_OUTPUT_UNKNOWN:
5270 /* Only DDI platforms should ever use this output type */
5271 WARN_ON_ONCE(!HAS_DDI(dev));
5272 case INTEL_OUTPUT_DISPLAYPORT:
5273 case INTEL_OUTPUT_HDMI:
5274 case INTEL_OUTPUT_EDP:
5275 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
d05410f9 5276 return port_to_power_domain(intel_dig_port->port);
0e32b39c
DA		 5277 case INTEL_OUTPUT_DP_MST:
5278 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5279 return port_to_power_domain(intel_dig_port->port);
319be8ae
ID		 5280 case INTEL_OUTPUT_ANALOG:
5281 return POWER_DOMAIN_PORT_CRT;
5282 case INTEL_OUTPUT_DSI:
5283 return POWER_DOMAIN_PORT_DSI;
5284 default:
5285 return POWER_DOMAIN_PORT_OTHER;
5286 }
5287}
5288
5289static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
77d22dca 5290{
319be8ae
ID		 5291 struct drm_device *dev = crtc->dev;
5292 struct intel_encoder *intel_encoder;
5293 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5294 enum pipe pipe = intel_crtc->pipe;
77d22dca
ID		 5295 unsigned long mask;
5296 enum transcoder transcoder;
5297
5298 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
5299
5300 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5301 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
6e3c9717
ACO		 5302 if (intel_crtc->config->pch_pfit.enabled ||
5303 intel_crtc->config->pch_pfit.force_thru)
77d22dca
ID		 5304 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5305
319be8ae
ID		 5306 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5307 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5308
77d22dca
ID		 5309 return mask;
5310}
5311
679dacd4 5312static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
77d22dca 5313{
679dacd4 5314 struct drm_device *dev = state->dev;
77d22dca
ID		 5315 struct drm_i915_private *dev_priv = dev->dev_private;
5316 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
5317 struct intel_crtc *crtc;
5318
5319 /*
5320 * First get all needed power domains, then put all unneeded, to avoid
5321 * any unnecessary toggling of the power wells.
5322 */
d3fcc808 5323 for_each_intel_crtc(dev, crtc) {
77d22dca
ID		 5324 enum intel_display_power_domain domain;
5325
83d65738 5326 if (!crtc->base.state->enable)
77d22dca
ID		 5327 continue;
5328
319be8ae 5329 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
77d22dca
ID		 5330
5331 for_each_power_domain(domain, pipe_domains[crtc->pipe])
5332 intel_display_power_get(dev_priv, domain);
5333 }
5334
50f6e502 5335 if (dev_priv->display.modeset_global_resources)
679dacd4 5336 dev_priv->display.modeset_global_resources(state);
50f6e502 5337
d3fcc808 5338 for_each_intel_crtc(dev, crtc) {
77d22dca
ID		 5339 enum intel_display_power_domain domain;
5340
5341 for_each_power_domain(domain, crtc->enabled_power_domains)
5342 intel_display_power_put(dev_priv, domain);
5343
5344 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
5345 }
5346
5347 intel_display_set_init_power(dev_priv, false);
5348}
5349
f8437dd1
VK		 5350void broxton_set_cdclk(struct drm_device *dev, int frequency)
5351{
5352 struct drm_i915_private *dev_priv = dev->dev_private;
5353 uint32_t divider;
5354 uint32_t ratio;
5355 uint32_t current_freq;
5356 int ret;
5357
5358 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5359 switch (frequency) {
5360 case 144000:
5361 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5362 ratio = BXT_DE_PLL_RATIO(60);
5363 break;
5364 case 288000:
5365 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5366 ratio = BXT_DE_PLL_RATIO(60);
5367 break;
5368 case 384000:
5369 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5370 ratio = BXT_DE_PLL_RATIO(60);
5371 break;
5372 case 576000:
5373 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5374 ratio = BXT_DE_PLL_RATIO(60);
5375 break;
5376 case 624000:
5377 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5378 ratio = BXT_DE_PLL_RATIO(65);
5379 break;
5380 case 19200:
5381 /*
5382 * Bypass frequency with DE PLL disabled. Init ratio, divider
5383 * to suppress GCC warning.
5384 */
5385 ratio = 0;
5386 divider = 0;
5387 break;
5388 default:
5389 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5390
5391 return;
5392 }
5393
5394 mutex_lock(&dev_priv->rps.hw_lock);
5395 /* Inform power controller of upcoming frequency change */
5396 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5397 0x80000000);
5398 mutex_unlock(&dev_priv->rps.hw_lock);
5399
5400 if (ret) {
5401 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5402 ret, frequency);
5403 return;
5404 }
5405
5406 current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5407 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5408 current_freq = current_freq * 500 + 1000;
5409
5410 /*
5411 * DE PLL has to be disabled when
5412 * - setting to 19.2MHz (bypass, PLL isn't used)
5413 * - before setting to 624MHz (PLL needs toggling)
5414 * - before setting to any frequency from 624MHz (PLL needs toggling)
5415 */
5416 if (frequency == 19200 || frequency == 624000 ||
5417 current_freq == 624000) {
5418 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5419 /* Timeout 200us */
5420 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5421 1))
5422 DRM_ERROR("timout waiting for DE PLL unlock\n");
5423 }
5424
5425 if (frequency != 19200) {
5426 uint32_t val;
5427
5428 val = I915_READ(BXT_DE_PLL_CTL);
5429 val &= ~BXT_DE_PLL_RATIO_MASK;
5430 val |= ratio;
5431 I915_WRITE(BXT_DE_PLL_CTL, val);
5432
5433 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5434 /* Timeout 200us */
5435 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5436 DRM_ERROR("timeout waiting for DE PLL lock\n");
5437
5438 val = I915_READ(CDCLK_CTL);
5439 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5440 val |= divider;
5441 /*
5442 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5443 * enable otherwise.
5444 */
5445 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5446 if (frequency >= 500000)
5447 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5448
5449 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5450 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5451 val |= (frequency - 1000) / 500;
5452 I915_WRITE(CDCLK_CTL, val);
5453 }
5454
5455 mutex_lock(&dev_priv->rps.hw_lock);
5456 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5457 DIV_ROUND_UP(frequency, 25000));
5458 mutex_unlock(&dev_priv->rps.hw_lock);
5459
5460 if (ret) {
5461 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5462 ret, frequency);
5463 return;
5464 }
5465
5466 dev_priv->cdclk_freq = frequency;
5467}
5468
5469void broxton_init_cdclk(struct drm_device *dev)
5470{
5471 struct drm_i915_private *dev_priv = dev->dev_private;
5472 uint32_t val;
5473
5474 /*
5475 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5476 * or else the reset will hang because there is no PCH to respond.
5477 * Move the handshake programming to initialization sequence.
5478 * Previously was left up to BIOS.
5479 */
5480 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5481 val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5482 I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5483
5484 /* Enable PG1 for cdclk */
5485 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5486
5487 /* check if cd clock is enabled */
5488 if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5489 DRM_DEBUG_KMS("Display already initialized\n");
5490 return;
5491 }
5492
5493 /*
5494 * FIXME:
5495 * - The initial CDCLK needs to be read from VBT.
5496 * Need to make this change after VBT has changes for BXT.
5497 * - check if setting the max (or any) cdclk freq is really necessary
5498 * here, it belongs to modeset time
5499 */
5500 broxton_set_cdclk(dev, 624000);
5501
5502 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
22e02c0b
VS		 5503 POSTING_READ(DBUF_CTL);
5504
f8437dd1
VK		 5505 udelay(10);
5506
5507 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5508 DRM_ERROR("DBuf power enable timeout!\n");
5509}
5510
5511void broxton_uninit_cdclk(struct drm_device *dev)
5512{
5513 struct drm_i915_private *dev_priv = dev->dev_private;
5514
5515 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
22e02c0b
VS		 5516 POSTING_READ(DBUF_CTL);
5517
f8437dd1
VK		 5518 udelay(10);
5519
5520 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5521 DRM_ERROR("DBuf power disable timeout!\n");
5522
5523 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5524 broxton_set_cdclk(dev, 19200);
5525
5526 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5527}
5528
5d96d8af
DL		 5529static const struct skl_cdclk_entry {
5530 unsigned int freq;
5531 unsigned int vco;
5532} skl_cdclk_frequencies[] = {
5533 { .freq = 308570, .vco = 8640 },
5534 { .freq = 337500, .vco = 8100 },
5535 { .freq = 432000, .vco = 8640 },
5536 { .freq = 450000, .vco = 8100 },
5537 { .freq = 540000, .vco = 8100 },
5538 { .freq = 617140, .vco = 8640 },
5539 { .freq = 675000, .vco = 8100 },
5540};
5541
5542static unsigned int skl_cdclk_decimal(unsigned int freq)
5543{
5544 return (freq - 1000) / 500;
5545}
5546
5547static unsigned int skl_cdclk_get_vco(unsigned int freq)
5548{
5549 unsigned int i;
5550
5551 for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5552 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5553
5554 if (e->freq == freq)
5555 return e->vco;
5556 }
5557
5558 return 8100;
5559}
5560
5561static void
5562skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5563{
5564 unsigned int min_freq;
5565 u32 val;
5566
5567 /* select the minimum CDCLK before enabling DPLL 0 */
5568 val = I915_READ(CDCLK_CTL);
5569 val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5570 val |= CDCLK_FREQ_337_308;
5571
5572 if (required_vco == 8640)
5573 min_freq = 308570;
5574 else
5575 min_freq = 337500;
5576
5577 val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5578
5579 I915_WRITE(CDCLK_CTL, val);
5580 POSTING_READ(CDCLK_CTL);
5581
5582 /*
5583 * We always enable DPLL0 with the lowest link rate possible, but still
5584 * taking into account the VCO required to operate the eDP panel at the
5585 * desired frequency. The usual DP link rates operate with a VCO of
5586 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5587 * The modeset code is responsible for the selection of the exact link
5588 * rate later on, with the constraint of choosing a frequency that
5589 * works with required_vco.
5590 */
5591 val = I915_READ(DPLL_CTRL1);
5592
5593 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5594 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5595 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5596 if (required_vco == 8640)
5597 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5598 SKL_DPLL0);
5599 else
5600 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5601 SKL_DPLL0);
5602
5603 I915_WRITE(DPLL_CTRL1, val);
5604 POSTING_READ(DPLL_CTRL1);
5605
5606 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5607
5608 if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5609 DRM_ERROR("DPLL0 not locked\n");
5610}
5611
5612static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5613{
5614 int ret;
5615 u32 val;
5616
5617 /* inform PCU we want to change CDCLK */
5618 val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5619 mutex_lock(&dev_priv->rps.hw_lock);
5620 ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5621 mutex_unlock(&dev_priv->rps.hw_lock);
5622
5623 return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5624}
5625
5626static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5627{
5628 unsigned int i;
5629
5630 for (i = 0; i < 15; i++) {
5631 if (skl_cdclk_pcu_ready(dev_priv))
5632 return true;
5633 udelay(10);
5634 }
5635
5636 return false;
5637}
5638
5639static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5640{
5641 u32 freq_select, pcu_ack;
5642
5643 DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5644
5645 if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5646 DRM_ERROR("failed to inform PCU about cdclk change\n");
5647 return;
5648 }
5649
5650 /* set CDCLK_CTL */
5651 switch(freq) {
5652 case 450000:
5653 case 432000:
5654 freq_select = CDCLK_FREQ_450_432;
5655 pcu_ack = 1;
5656 break;
5657 case 540000:
5658 freq_select = CDCLK_FREQ_540;
5659 pcu_ack = 2;
5660 break;
5661 case 308570:
5662 case 337500:
5663 default:
5664 freq_select = CDCLK_FREQ_337_308;
5665 pcu_ack = 0;
5666 break;
5667 case 617140:
5668 case 675000:
5669 freq_select = CDCLK_FREQ_675_617;
5670 pcu_ack = 3;
5671 break;
5672 }
5673
5674 I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5675 POSTING_READ(CDCLK_CTL);
5676
5677 /* inform PCU of the change */
5678 mutex_lock(&dev_priv->rps.hw_lock);
5679 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5680 mutex_unlock(&dev_priv->rps.hw_lock);
5681}
5682
5683void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5684{
5685 /* disable DBUF power */
5686 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5687 POSTING_READ(DBUF_CTL);
5688
5689 udelay(10);
5690
5691 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5692 DRM_ERROR("DBuf power disable timeout\n");
5693
5694 /* disable DPLL0 */
5695 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5696 if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5697 DRM_ERROR("Couldn't disable DPLL0\n");
5698
5699 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5700}
5701
5702void skl_init_cdclk(struct drm_i915_private *dev_priv)
5703{
5704 u32 val;
5705 unsigned int required_vco;
5706
5707 /* enable PCH reset handshake */
5708 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5709 I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
5710
5711 /* enable PG1 and Misc I/O */
5712 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5713
5714 /* DPLL0 already enabed !? */
5715 if (I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE) {
5716 DRM_DEBUG_DRIVER("DPLL0 already running\n");
5717 return;
5718 }
5719
5720 /* enable DPLL0 */
5721 required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5722 skl_dpll0_enable(dev_priv, required_vco);
5723
5724 /* set CDCLK to the frequency the BIOS chose */
5725 skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5726
5727 /* enable DBUF power */
5728 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5729 POSTING_READ(DBUF_CTL);
5730
5731 udelay(10);
5732
5733 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5734 DRM_ERROR("DBuf power enable timeout\n");
5735}
5736
dfcab17e 5737/* returns HPLL frequency in kHz */
f8bf63fd 5738static int valleyview_get_vco(struct drm_i915_private *dev_priv)
30a970c6 5739{
586f49dc 5740 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
30a970c6 5741
586f49dc
JB		 5742 /* Obtain SKU information */
5743 mutex_lock(&dev_priv->dpio_lock);
5744 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
5745 CCK_FUSE_HPLL_FREQ_MASK;
5746 mutex_unlock(&dev_priv->dpio_lock);
30a970c6 5747
dfcab17e 5748 return vco_freq[hpll_freq] * 1000;
30a970c6
JB		 5749}
5750
f8bf63fd
VS		 5751static void vlv_update_cdclk(struct drm_device *dev)
5752{
5753 struct drm_i915_private *dev_priv = dev->dev_private;
5754
164dfd28 5755 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
43dc52c3 5756 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
164dfd28 5757 dev_priv->cdclk_freq);
f8bf63fd
VS		 5758
5759 /*
5760 * Program the gmbus_freq based on the cdclk frequency.
5761 * BSpec erroneously claims we should aim for 4MHz, but
5762 * in fact 1MHz is the correct frequency.
5763 */
164dfd28 5764 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
f8bf63fd
VS		 5765}
5766
30a970c6
JB		 5767/* Adjust CDclk dividers to allow high res or save power if possible */
5768static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5769{
5770 struct drm_i915_private *dev_priv = dev->dev_private;
5771 u32 val, cmd;
5772
164dfd28
VK		 5773 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5774 != dev_priv->cdclk_freq);
d60c4473 5775
dfcab17e 5776 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
30a970c6 5777 cmd = 2;
dfcab17e 5778 else if (cdclk == 266667)
30a970c6
JB		 5779 cmd = 1;
5780 else
5781 cmd = 0;
5782
5783 mutex_lock(&dev_priv->rps.hw_lock);
5784 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5785 val &= ~DSPFREQGUAR_MASK;
5786 val |= (cmd << DSPFREQGUAR_SHIFT);
5787 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5788 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5789 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5790 50)) {
5791 DRM_ERROR("timed out waiting for CDclk change\n");
5792 }
5793 mutex_unlock(&dev_priv->rps.hw_lock);
5794
dfcab17e 5795 if (cdclk == 400000) {
6bcda4f0 5796 u32 divider;
30a970c6 5797
6bcda4f0 5798 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
30a970c6
JB		 5799
5800 mutex_lock(&dev_priv->dpio_lock);
5801 /* adjust cdclk divider */
5802 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
9cf33db5 5803 val &= ~DISPLAY_FREQUENCY_VALUES;
30a970c6
JB		 5804 val |= divider;
5805 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
a877e801
VS		 5806
5807 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5808 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5809 50))
5810 DRM_ERROR("timed out waiting for CDclk change\n");
30a970c6
JB		 5811 mutex_unlock(&dev_priv->dpio_lock);
5812 }
5813
5814 mutex_lock(&dev_priv->dpio_lock);
5815 /* adjust self-refresh exit latency value */
5816 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5817 val &= ~0x7f;
5818
5819 /*
5820 * For high bandwidth configs, we set a higher latency in the bunit
5821 * so that the core display fetch happens in time to avoid underruns.
5822 */
dfcab17e 5823 if (cdclk == 400000)
30a970c6
JB		 5824 val |= 4500 / 250; /* 4.5 usec */
5825 else
5826 val |= 3000 / 250; /* 3.0 usec */
5827 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5828 mutex_unlock(&dev_priv->dpio_lock);
5829
f8bf63fd 5830 vlv_update_cdclk(dev);
30a970c6
JB		 5831}
5832
383c5a6a
VS		 5833static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5834{
5835 struct drm_i915_private *dev_priv = dev->dev_private;
5836 u32 val, cmd;
5837
164dfd28
VK		 5838 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5839 != dev_priv->cdclk_freq);
383c5a6a
VS		 5840
5841 switch (cdclk) {
383c5a6a
VS		 5842 case 333333:
5843 case 320000:
383c5a6a 5844 case 266667:
383c5a6a 5845 case 200000:
383c5a6a
VS		 5846 break;
5847 default:
5f77eeb0 5848 MISSING_CASE(cdclk);
383c5a6a
VS		 5849 return;
5850 }
5851
9d0d3fda
VS		 5852 /*
5853 * Specs are full of misinformation, but testing on actual
5854 * hardware has shown that we just need to write the desired
5855 * CCK divider into the Punit register.
5856 */
5857 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5858
383c5a6a
VS		 5859 mutex_lock(&dev_priv->rps.hw_lock);
5860 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5861 val &= ~DSPFREQGUAR_MASK_CHV;
5862 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5863 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5864 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5865 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5866 50)) {
5867 DRM_ERROR("timed out waiting for CDclk change\n");
5868 }
5869 mutex_unlock(&dev_priv->rps.hw_lock);
5870
5871 vlv_update_cdclk(dev);
5872}
5873
30a970c6
JB		 5874static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5875 int max_pixclk)
5876{
6bcda4f0 5877 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
6cca3195 5878 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
29dc7ef3 5879
30a970c6
JB		 5880 /*
5881 * Really only a few cases to deal with, as only 4 CDclks are supported:
5882 * 200MHz
5883 * 267MHz
29dc7ef3 5884 * 320/333MHz (depends on HPLL freq)
6cca3195
VS		 5885 * 400MHz (VLV only)
5886 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5887 * of the lower bin and adjust if needed.
e37c67a1
VS		 5888 *
5889 * We seem to get an unstable or solid color picture at 200MHz.
5890 * Not sure what's wrong. For now use 200MHz only when all pipes
5891 * are off.
30a970c6 5892 */
6cca3195
VS		 5893 if (!IS_CHERRYVIEW(dev_priv) &&
5894 max_pixclk > freq_320*limit/100)
dfcab17e 5895 return 400000;
6cca3195 5896 else if (max_pixclk > 266667*limit/100)
29dc7ef3 5897 return freq_320;
e37c67a1 5898 else if (max_pixclk > 0)
dfcab17e 5899 return 266667;
e37c67a1
VS		 5900 else
5901 return 200000;
30a970c6
JB		 5902}
5903
f8437dd1
VK		 5904static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5905 int max_pixclk)
5906{
5907 /*
5908 * FIXME:
5909 * - remove the guardband, it's not needed on BXT
5910 * - set 19.2MHz bypass frequency if there are no active pipes
5911 */
5912 if (max_pixclk > 576000*9/10)
5913 return 624000;
5914 else if (max_pixclk > 384000*9/10)
5915 return 576000;
5916 else if (max_pixclk > 288000*9/10)
5917 return 384000;
5918 else if (max_pixclk > 144000*9/10)
5919 return 288000;
5920 else
5921 return 144000;
5922}
5923
a821fc46
ACO		 5924/* Compute the max pixel clock for new configuration. Uses atomic state if
5925 * that's non-NULL, look at current state otherwise. */
5926static int intel_mode_max_pixclk(struct drm_device *dev,
5927 struct drm_atomic_state *state)
30a970c6 5928{
30a970c6 5929 struct intel_crtc *intel_crtc;
304603f4 5930 struct intel_crtc_state *crtc_state;
30a970c6
JB		 5931 int max_pixclk = 0;
5932
d3fcc808 5933 for_each_intel_crtc(dev, intel_crtc) {
a821fc46
ACO		 5934 if (state)
5935 crtc_state =
5936 intel_atomic_get_crtc_state(state, intel_crtc);
5937 else
5938 crtc_state = intel_crtc->config;
304603f4
ACO		 5939 if (IS_ERR(crtc_state))
5940 return PTR_ERR(crtc_state);
5941
5942 if (!crtc_state->base.enable)
5943 continue;
5944
5945 max_pixclk = max(max_pixclk,
5946 crtc_state->base.adjusted_mode.crtc_clock);
30a970c6
JB		 5947 }
5948
5949 return max_pixclk;
5950}
5951
0a9ab303 5952static int valleyview_modeset_global_pipes(struct drm_atomic_state *state)
30a970c6 5953{
304603f4 5954 struct drm_i915_private *dev_priv = to_i915(state->dev);
0a9ab303
ACO		 5955 struct drm_crtc *crtc;
5956 struct drm_crtc_state *crtc_state;
a821fc46 5957 int max_pixclk = intel_mode_max_pixclk(state->dev, state);
0a9ab303 5958 int cdclk, i;
30a970c6 5959
304603f4
ACO		 5960 if (max_pixclk < 0)
5961 return max_pixclk;
30a970c6 5962
f8437dd1
VK		 5963 if (IS_VALLEYVIEW(dev_priv))
5964 cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
5965 else
5966 cdclk = broxton_calc_cdclk(dev_priv, max_pixclk);
5967
5968 if (cdclk == dev_priv->cdclk_freq)
304603f4 5969 return 0;
30a970c6 5970
0a9ab303
ACO		 5971 /* add all active pipes to the state */
5972 for_each_crtc(state->dev, crtc) {
5973 if (!crtc->state->enable)
5974 continue;
5975
5976 crtc_state = drm_atomic_get_crtc_state(state, crtc);
5977 if (IS_ERR(crtc_state))
5978 return PTR_ERR(crtc_state);
5979 }
5980
2f2d7aa1 5981 /* disable/enable all currently active pipes while we change cdclk */
0a9ab303
ACO		 5982 for_each_crtc_in_state(state, crtc, crtc_state, i)
5983 if (crtc_state->enable)
5984 crtc_state->mode_changed = true;
304603f4
ACO		 5985
5986 return 0;
30a970c6
JB		 5987}
5988
1e69cd74
VS		 5989static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5990{
5991 unsigned int credits, default_credits;
5992
5993 if (IS_CHERRYVIEW(dev_priv))
5994 default_credits = PFI_CREDIT(12);
5995 else
5996 default_credits = PFI_CREDIT(8);
5997
164dfd28 5998 if (DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
1e69cd74
VS		 5999 /* CHV suggested value is 31 or 63 */
6000 if (IS_CHERRYVIEW(dev_priv))
6001 credits = PFI_CREDIT_31;
6002 else
6003 credits = PFI_CREDIT(15);
6004 } else {
6005 credits = default_credits;
6006 }
6007
6008 /*
6009 * WA - write default credits before re-programming
6010 * FIXME: should we also set the resend bit here?
6011 */
6012 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6013 default_credits);
6014
6015 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6016 credits | PFI_CREDIT_RESEND);
6017
6018 /*
6019 * FIXME is this guaranteed to clear
6020 * immediately or should we poll for it?
6021 */
6022 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6023}
6024
a821fc46 6025static void valleyview_modeset_global_resources(struct drm_atomic_state *old_state)
30a970c6 6026{
a821fc46 6027 struct drm_device *dev = old_state->dev;
30a970c6 6028 struct drm_i915_private *dev_priv = dev->dev_private;
a821fc46 6029 int max_pixclk = intel_mode_max_pixclk(dev, NULL);
304603f4
ACO		 6030 int req_cdclk;
6031
a821fc46
ACO		 6032 /* The path in intel_mode_max_pixclk() with a NULL atomic state should
6033 * never fail. */
304603f4
ACO		 6034 if (WARN_ON(max_pixclk < 0))
6035 return;
30a970c6 6036
304603f4 6037 req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
30a970c6 6038
164dfd28 6039 if (req_cdclk != dev_priv->cdclk_freq) {
738c05c0
ID		 6040 /*
6041 * FIXME: We can end up here with all power domains off, yet
6042 * with a CDCLK frequency other than the minimum. To account
6043 * for this take the PIPE-A power domain, which covers the HW
6044 * blocks needed for the following programming. This can be
6045 * removed once it's guaranteed that we get here either with
6046 * the minimum CDCLK set, or the required power domains
6047 * enabled.
6048 */
6049 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6050
383c5a6a
VS		 6051 if (IS_CHERRYVIEW(dev))
6052 cherryview_set_cdclk(dev, req_cdclk);
6053 else
6054 valleyview_set_cdclk(dev, req_cdclk);
738c05c0 6055
1e69cd74
VS		 6056 vlv_program_pfi_credits(dev_priv);
6057
738c05c0 6058 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
383c5a6a 6059 }
30a970c6
JB		 6060}
6061
89b667f8
JB		 6062static void valleyview_crtc_enable(struct drm_crtc *crtc)
6063{
6064 struct drm_device *dev = crtc->dev;
a72e4c9f 6065 struct drm_i915_private *dev_priv = to_i915(dev);
89b667f8
JB		 6066 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6067 struct intel_encoder *encoder;
6068 int pipe = intel_crtc->pipe;
23538ef1 6069 bool is_dsi;
89b667f8 6070
83d65738 6071 WARN_ON(!crtc->state->enable);
89b667f8
JB		 6072
6073 if (intel_crtc->active)
6074 return;
6075
409ee761 6076 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
8525a235 6077
1ae0d137
VS		 6078 if (!is_dsi) {
6079 if (IS_CHERRYVIEW(dev))
6e3c9717 6080 chv_prepare_pll(intel_crtc, intel_crtc->config);
1ae0d137 6081 else
6e3c9717 6082 vlv_prepare_pll(intel_crtc, intel_crtc->config);
1ae0d137 6083 }
5b18e57c 6084
6e3c9717 6085 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 6086 intel_dp_set_m_n(intel_crtc, M1_N1);
5b18e57c
DV		 6087
6088 intel_set_pipe_timings(intel_crtc);
6089
c14b0485
VS		 6090 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6091 struct drm_i915_private *dev_priv = dev->dev_private;
6092
6093 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6094 I915_WRITE(CHV_CANVAS(pipe), 0);
6095 }
6096
5b18e57c
DV		 6097 i9xx_set_pipeconf(intel_crtc);
6098
89b667f8 6099 intel_crtc->active = true;
89b667f8 6100
a72e4c9f 6101 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 6102
89b667f8
JB		 6103 for_each_encoder_on_crtc(dev, crtc, encoder)
6104 if (encoder->pre_pll_enable)
6105 encoder->pre_pll_enable(encoder);
6106
9d556c99
CML		 6107 if (!is_dsi) {
6108 if (IS_CHERRYVIEW(dev))
6e3c9717 6109 chv_enable_pll(intel_crtc, intel_crtc->config);
9d556c99 6110 else
6e3c9717 6111 vlv_enable_pll(intel_crtc, intel_crtc->config);
9d556c99 6112 }
89b667f8
JB		 6113
6114 for_each_encoder_on_crtc(dev, crtc, encoder)
6115 if (encoder->pre_enable)
6116 encoder->pre_enable(encoder);
6117
2dd24552
JB		 6118 i9xx_pfit_enable(intel_crtc);
6119
63cbb074
VS		 6120 intel_crtc_load_lut(crtc);
6121
f37fcc2a 6122 intel_update_watermarks(crtc);
e1fdc473 6123 intel_enable_pipe(intel_crtc);
be6a6f8e 6124
4b3a9526
VS		 6125 assert_vblank_disabled(crtc);
6126 drm_crtc_vblank_on(crtc);
6127
f9b61ff6
DV		 6128 for_each_encoder_on_crtc(dev, crtc, encoder)
6129 encoder->enable(encoder);
89b667f8
JB		 6130}
6131
f13c2ef3
DV		 6132static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6133{
6134 struct drm_device *dev = crtc->base.dev;
6135 struct drm_i915_private *dev_priv = dev->dev_private;
6136
6e3c9717
ACO		 6137 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6138 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
f13c2ef3
DV		 6139}
6140
0b8765c6 6141static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 6142{
6143 struct drm_device *dev = crtc->dev;
a72e4c9f 6144 struct drm_i915_private *dev_priv = to_i915(dev);
79e53945 6145 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 6146 struct intel_encoder *encoder;
79e53945 6147 int pipe = intel_crtc->pipe;
79e53945 6148
83d65738 6149 WARN_ON(!crtc->state->enable);
08a48469 6150
f7abfe8b
CW		 6151 if (intel_crtc->active)
6152 return;
6153
f13c2ef3
DV		 6154 i9xx_set_pll_dividers(intel_crtc);
6155
6e3c9717 6156 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 6157 intel_dp_set_m_n(intel_crtc, M1_N1);
5b18e57c
DV		 6158
6159 intel_set_pipe_timings(intel_crtc);
6160
5b18e57c
DV		 6161 i9xx_set_pipeconf(intel_crtc);
6162
f7abfe8b 6163 intel_crtc->active = true;
6b383a7f 6164
4a3436e8 6165 if (!IS_GEN2(dev))
a72e4c9f 6166 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 6167
9d6d9f19
MK		 6168 for_each_encoder_on_crtc(dev, crtc, encoder)
6169 if (encoder->pre_enable)
6170 encoder->pre_enable(encoder);
6171
f6736a1a
DV		 6172 i9xx_enable_pll(intel_crtc);
6173
2dd24552
JB		 6174 i9xx_pfit_enable(intel_crtc);
6175
63cbb074
VS		 6176 intel_crtc_load_lut(crtc);
6177
f37fcc2a 6178 intel_update_watermarks(crtc);
e1fdc473 6179 intel_enable_pipe(intel_crtc);
be6a6f8e 6180
4b3a9526
VS		 6181 assert_vblank_disabled(crtc);
6182 drm_crtc_vblank_on(crtc);
6183
f9b61ff6
DV		 6184 for_each_encoder_on_crtc(dev, crtc, encoder)
6185 encoder->enable(encoder);
0b8765c6 6186}
79e53945 6187
87476d63
DV		 6188static void i9xx_pfit_disable(struct intel_crtc *crtc)
6189{
6190 struct drm_device *dev = crtc->base.dev;
6191 struct drm_i915_private *dev_priv = dev->dev_private;
87476d63 6192
6e3c9717 6193 if (!crtc->config->gmch_pfit.control)
328d8e82 6194 return;
87476d63 6195
328d8e82 6196 assert_pipe_disabled(dev_priv, crtc->pipe);
87476d63 6197
328d8e82
DV		 6198 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6199 I915_READ(PFIT_CONTROL));
6200 I915_WRITE(PFIT_CONTROL, 0);
87476d63
DV		 6201}
6202
0b8765c6
JB		 6203static void i9xx_crtc_disable(struct drm_crtc *crtc)
6204{
6205 struct drm_device *dev = crtc->dev;
6206 struct drm_i915_private *dev_priv = dev->dev_private;
6207 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 6208 struct intel_encoder *encoder;
0b8765c6 6209 int pipe = intel_crtc->pipe;
ef9c3aee 6210
f7abfe8b
CW		 6211 if (!intel_crtc->active)
6212 return;
6213
6304cd91
VS		 6214 /*
6215 * On gen2 planes are double buffered but the pipe isn't, so we must
6216 * wait for planes to fully turn off before disabling the pipe.
564ed191
ID		 6217 * We also need to wait on all gmch platforms because of the
6218 * self-refresh mode constraint explained above.
6304cd91 6219 */
564ed191 6220 intel_wait_for_vblank(dev, pipe);
6304cd91 6221
4b3a9526
VS		 6222 for_each_encoder_on_crtc(dev, crtc, encoder)
6223 encoder->disable(encoder);
6224
f9b61ff6
DV		 6225 drm_crtc_vblank_off(crtc);
6226 assert_vblank_disabled(crtc);
6227
575f7ab7 6228 intel_disable_pipe(intel_crtc);
24a1f16d 6229
87476d63 6230 i9xx_pfit_disable(intel_crtc);
24a1f16d 6231
89b667f8
JB		 6232 for_each_encoder_on_crtc(dev, crtc, encoder)
6233 if (encoder->post_disable)
6234 encoder->post_disable(encoder);
6235
409ee761 6236 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
076ed3b2
CML		 6237 if (IS_CHERRYVIEW(dev))
6238 chv_disable_pll(dev_priv, pipe);
6239 else if (IS_VALLEYVIEW(dev))
6240 vlv_disable_pll(dev_priv, pipe);
6241 else
1c4e0274 6242 i9xx_disable_pll(intel_crtc);
076ed3b2 6243 }
0b8765c6 6244
4a3436e8 6245 if (!IS_GEN2(dev))
a72e4c9f 6246 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4a3436e8 6247
f7abfe8b 6248 intel_crtc->active = false;
46ba614c 6249 intel_update_watermarks(crtc);
f37fcc2a 6250
efa9624e 6251 mutex_lock(&dev->struct_mutex);
7ff0ebcc 6252 intel_fbc_update(dev);
efa9624e 6253 mutex_unlock(&dev->struct_mutex);
0b8765c6
JB		 6254}
6255
ee7b9f93
JB		 6256static void i9xx_crtc_off(struct drm_crtc *crtc)
6257{
6258}
6259
b04c5bd6
BF		 6260/* Master function to enable/disable CRTC and corresponding power wells */
6261void intel_crtc_control(struct drm_crtc *crtc, bool enable)
976f8a20
DV		 6262{
6263 struct drm_device *dev = crtc->dev;
6264 struct drm_i915_private *dev_priv = dev->dev_private;
0e572fe7 6265 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
0e572fe7
DV		 6266 enum intel_display_power_domain domain;
6267 unsigned long domains;
976f8a20 6268
0e572fe7
DV		 6269 if (enable) {
6270 if (!intel_crtc->active) {
e1e9fb84
DV		 6271 domains = get_crtc_power_domains(crtc);
6272 for_each_power_domain(domain, domains)
6273 intel_display_power_get(dev_priv, domain);
6274 intel_crtc->enabled_power_domains = domains;
0e572fe7
DV		 6275
6276 dev_priv->display.crtc_enable(crtc);
ce22dba9 6277 intel_crtc_enable_planes(crtc);
0e572fe7
DV		 6278 }
6279 } else {
6280 if (intel_crtc->active) {
ce22dba9 6281 intel_crtc_disable_planes(crtc);
0e572fe7
DV		 6282 dev_priv->display.crtc_disable(crtc);
6283
e1e9fb84
DV		 6284 domains = intel_crtc->enabled_power_domains;
6285 for_each_power_domain(domain, domains)
6286 intel_display_power_put(dev_priv, domain);
6287 intel_crtc->enabled_power_domains = 0;
0e572fe7
DV		 6288 }
6289 }
b04c5bd6
BF		 6290}
6291
6292/**
6293 * Sets the power management mode of the pipe and plane.
6294 */
6295void intel_crtc_update_dpms(struct drm_crtc *crtc)
6296{
6297 struct drm_device *dev = crtc->dev;
6298 struct intel_encoder *intel_encoder;
6299 bool enable = false;
6300
6301 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
6302 enable |= intel_encoder->connectors_active;
6303
6304 intel_crtc_control(crtc, enable);
0f63cca2
ACO		 6305
6306 crtc->state->active = enable;
976f8a20
DV		 6307}
6308
cdd59983
CW		 6309static void intel_crtc_disable(struct drm_crtc *crtc)
6310{
cdd59983 6311 struct drm_device *dev = crtc->dev;
976f8a20 6312 struct drm_connector *connector;
ee7b9f93 6313 struct drm_i915_private *dev_priv = dev->dev_private;
cdd59983 6314
976f8a20 6315 /* crtc should still be enabled when we disable it. */
83d65738 6316 WARN_ON(!crtc->state->enable);
976f8a20 6317
ce22dba9 6318 intel_crtc_disable_planes(crtc);
976f8a20 6319 dev_priv->display.crtc_disable(crtc);
ee7b9f93
JB		 6320 dev_priv->display.off(crtc);
6321
70a101f8 6322 drm_plane_helper_disable(crtc->primary);
976f8a20
DV		 6323
6324 /* Update computed state. */
6325 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
6326 if (!connector->encoder || !connector->encoder->crtc)
6327 continue;
6328
6329 if (connector->encoder->crtc != crtc)
6330 continue;
6331
6332 connector->dpms = DRM_MODE_DPMS_OFF;
6333 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 6334 }
6335}
6336
ea5b213a 6337void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 6338{
4ef69c7a 6339 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 6340
ea5b213a
CW		 6341 drm_encoder_cleanup(encoder);
6342 kfree(intel_encoder);
7e7d76c3
JB		 6343}
6344
9237329d 6345/* Simple dpms helper for encoders with just one connector, no cloning and only
5ab432ef
DV		 6346 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
6347 * state of the entire output pipe. */
9237329d 6348static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 6349{
5ab432ef
DV		 6350 if (mode == DRM_MODE_DPMS_ON) {
6351 encoder->connectors_active = true;
6352
b2cabb0e 6353 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 6354 } else {
6355 encoder->connectors_active = false;
6356
b2cabb0e 6357 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 6358 }
79e53945
JB		 6359}
6360
0a91ca29
DV		 6361/* Cross check the actual hw state with our own modeset state tracking (and it's
6362 * internal consistency). */
b980514c 6363static void intel_connector_check_state(struct intel_connector *connector)
79e53945 6364{
0a91ca29
DV		 6365 if (connector->get_hw_state(connector)) {
6366 struct intel_encoder *encoder = connector->encoder;
6367 struct drm_crtc *crtc;
6368 bool encoder_enabled;
6369 enum pipe pipe;
6370
6371 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6372 connector->base.base.id,
c23cc417 6373 connector->base.name);
0a91ca29 6374
0e32b39c
DA		 6375 /* there is no real hw state for MST connectors */
6376 if (connector->mst_port)
6377 return;
6378
e2c719b7 6379 I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
0a91ca29 6380 "wrong connector dpms state\n");
e2c719b7 6381 I915_STATE_WARN(connector->base.encoder != &encoder->base,
0a91ca29 6382 "active connector not linked to encoder\n");
0a91ca29 6383
36cd7444 6384 if (encoder) {
e2c719b7 6385 I915_STATE_WARN(!encoder->connectors_active,
36cd7444
DA		 6386 "encoder->connectors_active not set\n");
6387
6388 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
e2c719b7
RC		 6389 I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n");
6390 if (I915_STATE_WARN_ON(!encoder->base.crtc))
36cd7444 6391 return;
0a91ca29 6392
36cd7444 6393 crtc = encoder->base.crtc;
0a91ca29 6394
83d65738
MR		 6395 I915_STATE_WARN(!crtc->state->enable,
6396 "crtc not enabled\n");
e2c719b7
RC		 6397 I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
6398 I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe,
36cd7444
DA		 6399 "encoder active on the wrong pipe\n");
6400 }
0a91ca29 6401 }
79e53945
JB		 6402}
6403
08d9bc92
ACO		 6404int intel_connector_init(struct intel_connector *connector)
6405{
6406 struct drm_connector_state *connector_state;
6407
6408 connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6409 if (!connector_state)
6410 return -ENOMEM;
6411
6412 connector->base.state = connector_state;
6413 return 0;
6414}
6415
6416struct intel_connector *intel_connector_alloc(void)
6417{
6418 struct intel_connector *connector;
6419
6420 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6421 if (!connector)
6422 return NULL;
6423
6424 if (intel_connector_init(connector) < 0) {
6425 kfree(connector);
6426 return NULL;
6427 }
6428
6429 return connector;
6430}
6431
5ab432ef
DV		 6432/* Even simpler default implementation, if there's really no special case to
6433 * consider. */
6434void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 6435{
5ab432ef
DV		 6436 /* All the simple cases only support two dpms states. */
6437 if (mode != DRM_MODE_DPMS_ON)
6438 mode = DRM_MODE_DPMS_OFF;
d4270e57 6439
5ab432ef
DV		 6440 if (mode == connector->dpms)
6441 return;
6442
6443 connector->dpms = mode;
6444
6445 /* Only need to change hw state when actually enabled */
c9976dcf
CW		 6446 if (connector->encoder)
6447 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
0a91ca29 6448
b980514c 6449 intel_modeset_check_state(connector->dev);
79e53945
JB		 6450}
6451
f0947c37
DV		 6452/* Simple connector->get_hw_state implementation for encoders that support only
6453 * one connector and no cloning and hence the encoder state determines the state
6454 * of the connector. */
6455bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 6456{
24929352 6457 enum pipe pipe = 0;
f0947c37 6458 struct intel_encoder *encoder = connector->encoder;
ea5b213a 6459
f0947c37 6460 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 6461}
6462
6d293983 6463static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
d272ddfa 6464{
6d293983
ACO		 6465 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6466 return crtc_state->fdi_lanes;
d272ddfa
VS		 6467
6468 return 0;
6469}
6470
6d293983 6471static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5cec258b 6472 struct intel_crtc_state *pipe_config)
1857e1da 6473{
6d293983
ACO		 6474 struct drm_atomic_state *state = pipe_config->base.state;
6475 struct intel_crtc *other_crtc;
6476 struct intel_crtc_state *other_crtc_state;
6477
1857e1da
DV		 6478 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6479 pipe_name(pipe), pipe_config->fdi_lanes);
6480 if (pipe_config->fdi_lanes > 4) {
6481 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6482 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6483 return -EINVAL;
1857e1da
DV		 6484 }
6485
bafb6553 6486 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
1857e1da
DV		 6487 if (pipe_config->fdi_lanes > 2) {
6488 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6489 pipe_config->fdi_lanes);
6d293983 6490 return -EINVAL;
1857e1da 6491 } else {
6d293983 6492 return 0;
1857e1da
DV		 6493 }
6494 }
6495
6496 if (INTEL_INFO(dev)->num_pipes == 2)
6d293983 6497 return 0;
1857e1da
DV		 6498
6499 /* Ivybridge 3 pipe is really complicated */
6500 switch (pipe) {
6501 case PIPE_A:
6d293983 6502 return 0;
1857e1da 6503 case PIPE_B:
6d293983
ACO		 6504 if (pipe_config->fdi_lanes <= 2)
6505 return 0;
6506
6507 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6508 other_crtc_state =
6509 intel_atomic_get_crtc_state(state, other_crtc);
6510 if (IS_ERR(other_crtc_state))
6511 return PTR_ERR(other_crtc_state);
6512
6513 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
1857e1da
DV		 6514 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6515 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6516 return -EINVAL;
1857e1da 6517 }
6d293983 6518 return 0;
1857e1da 6519 case PIPE_C:
251cc67c
VS		 6520 if (pipe_config->fdi_lanes > 2) {
6521 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6522 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6523 return -EINVAL;
251cc67c 6524 }
6d293983
ACO		 6525
6526 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6527 other_crtc_state =
6528 intel_atomic_get_crtc_state(state, other_crtc);
6529 if (IS_ERR(other_crtc_state))
6530 return PTR_ERR(other_crtc_state);
6531
6532 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
1857e1da 6533 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6d293983 6534 return -EINVAL;
1857e1da 6535 }
6d293983 6536 return 0;
1857e1da
DV		 6537 default:
6538 BUG();
6539 }
6540}
6541
e29c22c0
DV		 6542#define RETRY 1
6543static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5cec258b 6544 struct intel_crtc_state *pipe_config)
877d48d5 6545{
1857e1da 6546 struct drm_device *dev = intel_crtc->base.dev;
2d112de7 6547 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6d293983
ACO		 6548 int lane, link_bw, fdi_dotclock, ret;
6549 bool needs_recompute = false;
877d48d5 6550
e29c22c0 6551retry:
877d48d5
DV		 6552 /* FDI is a binary signal running at ~2.7GHz, encoding
6553 * each output octet as 10 bits. The actual frequency
6554 * is stored as a divider into a 100MHz clock, and the
6555 * mode pixel clock is stored in units of 1KHz.
6556 * Hence the bw of each lane in terms of the mode signal
6557 * is:
6558 */
6559 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6560
241bfc38 6561 fdi_dotclock = adjusted_mode->crtc_clock;
877d48d5 6562
2bd89a07 6563 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
877d48d5
DV		 6564 pipe_config->pipe_bpp);
6565
6566 pipe_config->fdi_lanes = lane;
6567
2bd89a07 6568 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
877d48d5 6569 link_bw, &pipe_config->fdi_m_n);
1857e1da 6570
6d293983
ACO		 6571 ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6572 intel_crtc->pipe, pipe_config);
6573 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
e29c22c0
DV		 6574 pipe_config->pipe_bpp -= 2*3;
6575 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6576 pipe_config->pipe_bpp);
6577 needs_recompute = true;
6578 pipe_config->bw_constrained = true;
6579
6580 goto retry;
6581 }
6582
6583 if (needs_recompute)
6584 return RETRY;
6585
6d293983 6586 return ret;
877d48d5
DV		 6587}
6588
42db64ef 6589static void hsw_compute_ips_config(struct intel_crtc *crtc,
5cec258b 6590 struct intel_crtc_state *pipe_config)
42db64ef 6591{
d330a953 6592 pipe_config->ips_enabled = i915.enable_ips &&
3c4ca58c 6593 hsw_crtc_supports_ips(crtc) &&
b6dfdc9b 6594 pipe_config->pipe_bpp <= 24;
42db64ef
PZ		 6595}
6596
a43f6e0f 6597static int intel_crtc_compute_config(struct intel_crtc *crtc,
5cec258b 6598 struct intel_crtc_state *pipe_config)
79e53945 6599{
a43f6e0f 6600 struct drm_device *dev = crtc->base.dev;
8bd31e67 6601 struct drm_i915_private *dev_priv = dev->dev_private;
2d112de7 6602 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
d03c93d4 6603 int ret;
89749350 6604
ad3a4479 6605 /* FIXME should check pixel clock limits on all platforms */
cf532bb2 6606 if (INTEL_INFO(dev)->gen < 4) {
cf532bb2
VS		 6607 int clock_limit =
6608 dev_priv->display.get_display_clock_speed(dev);
6609
6610 /*
6611 * Enable pixel doubling when the dot clock
6612 * is > 90% of the (display) core speed.
6613 *
b397c96b
VS		 6614 * GDG double wide on either pipe,
6615 * otherwise pipe A only.
cf532bb2 6616 */
b397c96b 6617 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
241bfc38 6618 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
ad3a4479 6619 clock_limit *= 2;
cf532bb2 6620 pipe_config->double_wide = true;
ad3a4479
VS		 6621 }
6622
241bfc38 6623 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
e29c22c0 6624 return -EINVAL;
2c07245f 6625 }
89749350 6626
1d1d0e27
VS		 6627 /*
6628 * Pipe horizontal size must be even in:
6629 * - DVO ganged mode
6630 * - LVDS dual channel mode
6631 * - Double wide pipe
6632 */
a93e255f 6633 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
1d1d0e27
VS		 6634 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6635 pipe_config->pipe_src_w &= ~1;
6636
8693a824
DL		 6637 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6638 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
44f46b42
CW		 6639 */
6640 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6641 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
e29c22c0 6642 return -EINVAL;
44f46b42 6643
f5adf94e 6644 if (HAS_IPS(dev))
a43f6e0f
DV		 6645 hsw_compute_ips_config(crtc, pipe_config);
6646
877d48d5 6647 if (pipe_config->has_pch_encoder)
a43f6e0f 6648 return ironlake_fdi_compute_config(crtc, pipe_config);
877d48d5 6649
d03c93d4
CK		 6650 /* FIXME: remove below call once atomic mode set is place and all crtc
6651 * related checks called from atomic_crtc_check function */
6652 ret = 0;
6653 DRM_DEBUG_KMS("intel_crtc = %p drm_state (pipe_config->base.state) = %p\n",
6654 crtc, pipe_config->base.state);
6655 ret = intel_atomic_setup_scalers(dev, crtc, pipe_config);
6656
6657 return ret;
79e53945
JB		 6658}
6659
1652d19e
VS		 6660static int skylake_get_display_clock_speed(struct drm_device *dev)
6661{
6662 struct drm_i915_private *dev_priv = to_i915(dev);
6663 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6664 uint32_t cdctl = I915_READ(CDCLK_CTL);
6665 uint32_t linkrate;
6666
6667 if (!(lcpll1 & LCPLL_PLL_ENABLE)) {
6668 WARN(1, "LCPLL1 not enabled\n");
6669 return 24000; /* 24MHz is the cd freq with NSSC ref */
6670 }
6671
6672 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6673 return 540000;
6674
6675 linkrate = (I915_READ(DPLL_CTRL1) &
71cd8423 6676 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
1652d19e 6677
71cd8423
DL		 6678 if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6679 linkrate == DPLL_CTRL1_LINK_RATE_1080) {
1652d19e
VS		 6680 /* vco 8640 */
6681 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6682 case CDCLK_FREQ_450_432:
6683 return 432000;
6684 case CDCLK_FREQ_337_308:
6685 return 308570;
6686 case CDCLK_FREQ_675_617:
6687 return 617140;
6688 default:
6689 WARN(1, "Unknown cd freq selection\n");
6690 }
6691 } else {
6692 /* vco 8100 */
6693 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6694 case CDCLK_FREQ_450_432:
6695 return 450000;
6696 case CDCLK_FREQ_337_308:
6697 return 337500;
6698 case CDCLK_FREQ_675_617:
6699 return 675000;
6700 default:
6701 WARN(1, "Unknown cd freq selection\n");
6702 }
6703 }
6704
6705 /* error case, do as if DPLL0 isn't enabled */
6706 return 24000;
6707}
6708
6709static int broadwell_get_display_clock_speed(struct drm_device *dev)
6710{
6711 struct drm_i915_private *dev_priv = dev->dev_private;
6712 uint32_t lcpll = I915_READ(LCPLL_CTL);
6713 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6714
6715 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6716 return 800000;
6717 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6718 return 450000;
6719 else if (freq == LCPLL_CLK_FREQ_450)
6720 return 450000;
6721 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6722 return 540000;
6723 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6724 return 337500;
6725 else
6726 return 675000;
6727}
6728
6729static int haswell_get_display_clock_speed(struct drm_device *dev)
6730{
6731 struct drm_i915_private *dev_priv = dev->dev_private;
6732 uint32_t lcpll = I915_READ(LCPLL_CTL);
6733 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6734
6735 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6736 return 800000;
6737 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6738 return 450000;
6739 else if (freq == LCPLL_CLK_FREQ_450)
6740 return 450000;
6741 else if (IS_HSW_ULT(dev))
6742 return 337500;
6743 else
6744 return 540000;
79e53945
JB		 6745}
6746
25eb05fc
JB		 6747static int valleyview_get_display_clock_speed(struct drm_device *dev)
6748{
d197b7d3 6749 struct drm_i915_private *dev_priv = dev->dev_private;
d197b7d3
VS		 6750 u32 val;
6751 int divider;
6752
6bcda4f0
VS		 6753 if (dev_priv->hpll_freq == 0)
6754 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
6755
d197b7d3
VS		 6756 mutex_lock(&dev_priv->dpio_lock);
6757 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
6758 mutex_unlock(&dev_priv->dpio_lock);
6759
6760 divider = val & DISPLAY_FREQUENCY_VALUES;
6761
7d007f40
VS		 6762 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
6763 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
6764 "cdclk change in progress\n");
6765
6bcda4f0 6766 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
25eb05fc
JB		 6767}
6768
b37a6434
VS		 6769static int ilk_get_display_clock_speed(struct drm_device *dev)
6770{
6771 return 450000;
6772}
6773
e70236a8
JB		 6774static int i945_get_display_clock_speed(struct drm_device *dev)
6775{
6776 return 400000;
6777}
79e53945 6778
e70236a8 6779static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 6780{
e907f170 6781 return 333333;
e70236a8 6782}
79e53945 6783
e70236a8
JB		 6784static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6785{
6786 return 200000;
6787}
79e53945 6788
257a7ffc
DV		 6789static int pnv_get_display_clock_speed(struct drm_device *dev)
6790{
6791 u16 gcfgc = 0;
6792
6793 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6794
6795 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6796 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
e907f170 6797 return 266667;
257a7ffc 6798 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
e907f170 6799 return 333333;
257a7ffc 6800 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
e907f170 6801 return 444444;
257a7ffc
DV		 6802 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6803 return 200000;
6804 default:
6805 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6806 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
e907f170 6807 return 133333;
257a7ffc 6808 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
e907f170 6809 return 166667;
257a7ffc
DV		 6810 }
6811}
6812
e70236a8
JB		 6813static int i915gm_get_display_clock_speed(struct drm_device *dev)
6814{
6815 u16 gcfgc = 0;
79e53945 6816
e70236a8
JB		 6817 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6818
6819 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
e907f170 6820 return 133333;
e70236a8
JB		 6821 else {
6822 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6823 case GC_DISPLAY_CLOCK_333_MHZ:
e907f170 6824 return 333333;
e70236a8
JB		 6825 default:
6826 case GC_DISPLAY_CLOCK_190_200_MHZ:
6827 return 190000;
79e53945 6828 }
e70236a8
JB		 6829 }
6830}
6831
6832static int i865_get_display_clock_speed(struct drm_device *dev)
6833{
e907f170 6834 return 266667;
e70236a8
JB		 6835}
6836
6837static int i855_get_display_clock_speed(struct drm_device *dev)
6838{
6839 u16 hpllcc = 0;
6840 /* Assume that the hardware is in the high speed state. This
6841 * should be the default.
6842 */
6843 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6844 case GC_CLOCK_133_200:
6845 case GC_CLOCK_100_200:
6846 return 200000;
6847 case GC_CLOCK_166_250:
6848 return 250000;
6849 case GC_CLOCK_100_133:
e907f170 6850 return 133333;
e70236a8 6851 }
79e53945 6852
e70236a8
JB		 6853 /* Shouldn't happen */
6854 return 0;
6855}
79e53945 6856
e70236a8
JB		 6857static int i830_get_display_clock_speed(struct drm_device *dev)
6858{
e907f170 6859 return 133333;
79e53945
JB		 6860}
6861
2c07245f 6862static void
a65851af 6863intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
2c07245f 6864{
a65851af
VS		 6865 while (*num > DATA_LINK_M_N_MASK ||
6866 *den > DATA_LINK_M_N_MASK) {
2c07245f
ZW		 6867 *num >>= 1;
6868 *den >>= 1;
6869 }
6870}
6871
a65851af
VS		 6872static void compute_m_n(unsigned int m, unsigned int n,
6873 uint32_t *ret_m, uint32_t *ret_n)
6874{
6875 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
6876 *ret_m = div_u64((uint64_t) m * *ret_n, n);
6877 intel_reduce_m_n_ratio(ret_m, ret_n);
6878}
6879
e69d0bc1
DV		 6880void
6881intel_link_compute_m_n(int bits_per_pixel, int nlanes,
6882 int pixel_clock, int link_clock,
6883 struct intel_link_m_n *m_n)
2c07245f 6884{
e69d0bc1 6885 m_n->tu = 64;
a65851af
VS		 6886
6887 compute_m_n(bits_per_pixel * pixel_clock,
6888 link_clock * nlanes * 8,
6889 &m_n->gmch_m, &m_n->gmch_n);
6890
6891 compute_m_n(pixel_clock, link_clock,
6892 &m_n->link_m, &m_n->link_n);
2c07245f
ZW		 6893}
6894
a7615030
CW		 6895static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
6896{
d330a953
JN		 6897 if (i915.panel_use_ssc >= 0)
6898 return i915.panel_use_ssc != 0;
41aa3448 6899 return dev_priv->vbt.lvds_use_ssc
435793df 6900 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 6901}
6902
a93e255f
ACO		 6903static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
6904 int num_connectors)
c65d77d8 6905{
a93e255f 6906 struct drm_device *dev = crtc_state->base.crtc->dev;
c65d77d8
JB		 6907 struct drm_i915_private *dev_priv = dev->dev_private;
6908 int refclk;
6909
a93e255f
ACO		 6910 WARN_ON(!crtc_state->base.state);
6911
5ab7b0b7 6912 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
9a0ea498 6913 refclk = 100000;
a93e255f 6914 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
c65d77d8 6915 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
e91e941b
VS		 6916 refclk = dev_priv->vbt.lvds_ssc_freq;
6917 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
c65d77d8
JB		 6918 } else if (!IS_GEN2(dev)) {
6919 refclk = 96000;
6920 } else {
6921 refclk = 48000;
6922 }
6923
6924 return refclk;
6925}
6926
7429e9d4 6927static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
c65d77d8 6928{
7df00d7a 6929 return (1 << dpll->n) << 16 | dpll->m2;
7429e9d4 6930}
f47709a9 6931
7429e9d4
DV		 6932static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
6933{
6934 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
c65d77d8
JB		 6935}
6936
f47709a9 6937static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
190f68c5 6938 struct intel_crtc_state *crtc_state,
a7516a05
JB		 6939 intel_clock_t *reduced_clock)
6940{
f47709a9 6941 struct drm_device *dev = crtc->base.dev;
a7516a05
JB		 6942 u32 fp, fp2 = 0;
6943
6944 if (IS_PINEVIEW(dev)) {
190f68c5 6945 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
a7516a05 6946 if (reduced_clock)
7429e9d4 6947 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 6948 } else {
190f68c5 6949 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
a7516a05 6950 if (reduced_clock)
7429e9d4 6951 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB		 6952 }
6953
190f68c5 6954 crtc_state->dpll_hw_state.fp0 = fp;
a7516a05 6955
f47709a9 6956 crtc->lowfreq_avail = false;
a93e255f 6957 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
ab585dea 6958 reduced_clock) {
190f68c5 6959 crtc_state->dpll_hw_state.fp1 = fp2;
f47709a9 6960 crtc->lowfreq_avail = true;
a7516a05 6961 } else {
190f68c5 6962 crtc_state->dpll_hw_state.fp1 = fp;
a7516a05
JB		 6963 }
6964}
6965
5e69f97f
CML		 6966static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
6967 pipe)
89b667f8
JB		 6968{
6969 u32 reg_val;
6970
6971 /*
6972 * PLLB opamp always calibrates to max value of 0x3f, force enable it
6973 * and set it to a reasonable value instead.
6974 */
ab3c759a 6975 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
89b667f8
JB		 6976 reg_val &= 0xffffff00;
6977 reg_val |= 0x00000030;
ab3c759a 6978 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
89b667f8 6979
ab3c759a 6980 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
89b667f8
JB		 6981 reg_val &= 0x8cffffff;
6982 reg_val = 0x8c000000;
ab3c759a 6983 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
89b667f8 6984
ab3c759a 6985 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
89b667f8 6986 reg_val &= 0xffffff00;
ab3c759a 6987 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
89b667f8 6988
ab3c759a 6989 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
89b667f8
JB		 6990 reg_val &= 0x00ffffff;
6991 reg_val |= 0xb0000000;
ab3c759a 6992 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
89b667f8
JB		 6993}
6994
b551842d
DV		 6995static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
6996 struct intel_link_m_n *m_n)
6997{
6998 struct drm_device *dev = crtc->base.dev;
6999 struct drm_i915_private *dev_priv = dev->dev_private;
7000 int pipe = crtc->pipe;
7001
e3b95f1e
DV		 7002 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7003 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7004 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7005 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
b551842d
DV		 7006}
7007
7008static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
f769cd24
VK		 7009 struct intel_link_m_n *m_n,
7010 struct intel_link_m_n *m2_n2)
b551842d
DV		 7011{
7012 struct drm_device *dev = crtc->base.dev;
7013 struct drm_i915_private *dev_priv = dev->dev_private;
7014 int pipe = crtc->pipe;
6e3c9717 7015 enum transcoder transcoder = crtc->config->cpu_transcoder;
b551842d
DV		 7016
7017 if (INTEL_INFO(dev)->gen >= 5) {
7018 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7019 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7020 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7021 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
f769cd24
VK		 7022 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7023 * for gen < 8) and if DRRS is supported (to make sure the
7024 * registers are not unnecessarily accessed).
7025 */
44395bfe 7026 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
6e3c9717 7027 crtc->config->has_drrs) {
f769cd24
VK		 7028 I915_WRITE(PIPE_DATA_M2(transcoder),
7029 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7030 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7031 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7032 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7033 }
b551842d 7034 } else {
e3b95f1e
DV		 7035 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7036 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7037 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7038 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
b551842d
DV		 7039 }
7040}
7041
fe3cd48d 7042void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
03afc4a2 7043{
fe3cd48d
R		 7044 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7045
7046 if (m_n == M1_N1) {
7047 dp_m_n = &crtc->config->dp_m_n;
7048 dp_m2_n2 = &crtc->config->dp_m2_n2;
7049 } else if (m_n == M2_N2) {
7050
7051 /*
7052 * M2_N2 registers are not supported. Hence m2_n2 divider value
7053 * needs to be programmed into M1_N1.
7054 */
7055 dp_m_n = &crtc->config->dp_m2_n2;
7056 } else {
7057 DRM_ERROR("Unsupported divider value\n");
7058 return;
7059 }
7060
6e3c9717
ACO		 7061 if (crtc->config->has_pch_encoder)
7062 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
03afc4a2 7063 else
fe3cd48d 7064 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
03afc4a2
DV		 7065}
7066
d288f65f 7067static void vlv_update_pll(struct intel_crtc *crtc,
5cec258b 7068 struct intel_crtc_state *pipe_config)
bdd4b6a6
DV		 7069{
7070 u32 dpll, dpll_md;
7071
7072 /*
7073 * Enable DPIO clock input. We should never disable the reference
7074 * clock for pipe B, since VGA hotplug / manual detection depends
7075 * on it.
7076 */
7077 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
7078 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
7079 /* We should never disable this, set it here for state tracking */
7080 if (crtc->pipe == PIPE_B)
7081 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7082 dpll |= DPLL_VCO_ENABLE;
d288f65f 7083 pipe_config->dpll_hw_state.dpll = dpll;
bdd4b6a6 7084
d288f65f 7085 dpll_md = (pipe_config->pixel_multiplier - 1)
bdd4b6a6 7086 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
d288f65f 7087 pipe_config->dpll_hw_state.dpll_md = dpll_md;
bdd4b6a6
DV		 7088}
7089
d288f65f 7090static void vlv_prepare_pll(struct intel_crtc *crtc,
5cec258b 7091 const struct intel_crtc_state *pipe_config)
a0c4da24 7092{
f47709a9 7093 struct drm_device *dev = crtc->base.dev;
a0c4da24 7094 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 7095 int pipe = crtc->pipe;
bdd4b6a6 7096 u32 mdiv;
a0c4da24 7097 u32 bestn, bestm1, bestm2, bestp1, bestp2;
bdd4b6a6 7098 u32 coreclk, reg_val;
a0c4da24 7099
09153000
DV		 7100 mutex_lock(&dev_priv->dpio_lock);
7101
d288f65f
VS		 7102 bestn = pipe_config->dpll.n;
7103 bestm1 = pipe_config->dpll.m1;
7104 bestm2 = pipe_config->dpll.m2;
7105 bestp1 = pipe_config->dpll.p1;
7106 bestp2 = pipe_config->dpll.p2;
a0c4da24 7107
89b667f8
JB		 7108 /* See eDP HDMI DPIO driver vbios notes doc */
7109
7110 /* PLL B needs special handling */
bdd4b6a6 7111 if (pipe == PIPE_B)
5e69f97f 7112 vlv_pllb_recal_opamp(dev_priv, pipe);
89b667f8
JB		 7113
7114 /* Set up Tx target for periodic Rcomp update */
ab3c759a 7115 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
89b667f8
JB		 7116
7117 /* Disable target IRef on PLL */
ab3c759a 7118 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
89b667f8 7119 reg_val &= 0x00ffffff;
ab3c759a 7120 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
89b667f8
JB		 7121
7122 /* Disable fast lock */
ab3c759a 7123 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
89b667f8
JB		 7124
7125 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 7126 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7127 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7128 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 7129 mdiv |= (1 << DPIO_K_SHIFT);
7df5080b
JB		 7130
7131 /*
7132 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7133 * but we don't support that).
7134 * Note: don't use the DAC post divider as it seems unstable.
7135 */
7136 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
ab3c759a 7137 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
a0c4da24 7138
a0c4da24 7139 mdiv |= DPIO_ENABLE_CALIBRATION;
ab3c759a 7140 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
a0c4da24 7141
89b667f8 7142 /* Set HBR and RBR LPF coefficients */
d288f65f 7143 if (pipe_config->port_clock == 162000 ||
409ee761
ACO		 7144 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7145 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
ab3c759a 7146 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
885b0120 7147 0x009f0003);
89b667f8 7148 else
ab3c759a 7149 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
89b667f8
JB		 7150 0x00d0000f);
7151
681a8504 7152 if (pipe_config->has_dp_encoder) {
89b667f8 7153 /* Use SSC source */
bdd4b6a6 7154 if (pipe == PIPE_A)
ab3c759a 7155 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7156 0x0df40000);
7157 else
ab3c759a 7158 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7159 0x0df70000);
7160 } else { /* HDMI or VGA */
7161 /* Use bend source */
bdd4b6a6 7162 if (pipe == PIPE_A)
ab3c759a 7163 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7164 0x0df70000);
7165 else
ab3c759a 7166 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7167 0x0df40000);
7168 }
a0c4da24 7169
ab3c759a 7170 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
89b667f8 7171 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
409ee761
ACO		 7172 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7173 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
89b667f8 7174 coreclk |= 0x01000000;
ab3c759a 7175 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
a0c4da24 7176
ab3c759a 7177 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
09153000 7178 mutex_unlock(&dev_priv->dpio_lock);
a0c4da24
JB		 7179}
7180
d288f65f 7181static void chv_update_pll(struct intel_crtc *crtc,
5cec258b 7182 struct intel_crtc_state *pipe_config)
1ae0d137 7183{
d288f65f 7184 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
1ae0d137
VS		 7185 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
7186 DPLL_VCO_ENABLE;
7187 if (crtc->pipe != PIPE_A)
d288f65f 7188 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
1ae0d137 7189
d288f65f
VS		 7190 pipe_config->dpll_hw_state.dpll_md =
7191 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
1ae0d137
VS		 7192}
7193
d288f65f 7194static void chv_prepare_pll(struct intel_crtc *crtc,
5cec258b 7195 const struct intel_crtc_state *pipe_config)
9d556c99
CML		 7196{
7197 struct drm_device *dev = crtc->base.dev;
7198 struct drm_i915_private *dev_priv = dev->dev_private;
7199 int pipe = crtc->pipe;
7200 int dpll_reg = DPLL(crtc->pipe);
7201 enum dpio_channel port = vlv_pipe_to_channel(pipe);
9cbe40c1 7202 u32 loopfilter, tribuf_calcntr;
9d556c99 7203 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
a945ce7e 7204 u32 dpio_val;
9cbe40c1 7205 int vco;
9d556c99 7206
d288f65f
VS		 7207 bestn = pipe_config->dpll.n;
7208 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7209 bestm1 = pipe_config->dpll.m1;
7210 bestm2 = pipe_config->dpll.m2 >> 22;
7211 bestp1 = pipe_config->dpll.p1;
7212 bestp2 = pipe_config->dpll.p2;
9cbe40c1 7213 vco = pipe_config->dpll.vco;
a945ce7e 7214 dpio_val = 0;
9cbe40c1 7215 loopfilter = 0;
9d556c99
CML		 7216
7217 /*
7218 * Enable Refclk and SSC
7219 */
a11b0703 7220 I915_WRITE(dpll_reg,
d288f65f 7221 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
a11b0703
VS		 7222
7223 mutex_lock(&dev_priv->dpio_lock);
9d556c99 7224
9d556c99
CML		 7225 /* p1 and p2 divider */
7226 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7227 5 << DPIO_CHV_S1_DIV_SHIFT |
7228 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7229 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7230 1 << DPIO_CHV_K_DIV_SHIFT);
7231
7232 /* Feedback post-divider - m2 */
7233 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7234
7235 /* Feedback refclk divider - n and m1 */
7236 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7237 DPIO_CHV_M1_DIV_BY_2 |
7238 1 << DPIO_CHV_N_DIV_SHIFT);
7239
7240 /* M2 fraction division */
a945ce7e
VP		 7241 if (bestm2_frac)
7242 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
9d556c99
CML		 7243
7244 /* M2 fraction division enable */
a945ce7e
VP		 7245 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7246 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7247 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7248 if (bestm2_frac)
7249 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7250 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
9d556c99 7251
de3a0fde
VP		 7252 /* Program digital lock detect threshold */
7253 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7254 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7255 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7256 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7257 if (!bestm2_frac)
7258 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7259 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7260
9d556c99 7261 /* Loop filter */
9cbe40c1
VP		 7262 if (vco == 5400000) {
7263 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7264 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7265 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7266 tribuf_calcntr = 0x9;
7267 } else if (vco <= 6200000) {
7268 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7269 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7270 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7271 tribuf_calcntr = 0x9;
7272 } else if (vco <= 6480000) {
7273 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7274 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7275 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7276 tribuf_calcntr = 0x8;
7277 } else {
7278 /* Not supported. Apply the same limits as in the max case */
7279 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7280 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7281 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7282 tribuf_calcntr = 0;
7283 }
9d556c99
CML		 7284 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7285
968040b2 7286 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
9cbe40c1
VP		 7287 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7288 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7289 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7290
9d556c99
CML		 7291 /* AFC Recal */
7292 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7293 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7294 DPIO_AFC_RECAL);
7295
7296 mutex_unlock(&dev_priv->dpio_lock);
7297}
7298
d288f65f
VS		 7299/**
7300 * vlv_force_pll_on - forcibly enable just the PLL
7301 * @dev_priv: i915 private structure
7302 * @pipe: pipe PLL to enable
7303 * @dpll: PLL configuration
7304 *
7305 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7306 * in cases where we need the PLL enabled even when @pipe is not going to
7307 * be enabled.
7308 */
7309void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7310 const struct dpll *dpll)
7311{
7312 struct intel_crtc *crtc =
7313 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
5cec258b 7314 struct intel_crtc_state pipe_config = {
a93e255f 7315 .base.crtc = &crtc->base,
d288f65f
VS		 7316 .pixel_multiplier = 1,
7317 .dpll = *dpll,
7318 };
7319
7320 if (IS_CHERRYVIEW(dev)) {
7321 chv_update_pll(crtc, &pipe_config);
7322 chv_prepare_pll(crtc, &pipe_config);
7323 chv_enable_pll(crtc, &pipe_config);
7324 } else {
7325 vlv_update_pll(crtc, &pipe_config);
7326 vlv_prepare_pll(crtc, &pipe_config);
7327 vlv_enable_pll(crtc, &pipe_config);
7328 }
7329}
7330
7331/**
7332 * vlv_force_pll_off - forcibly disable just the PLL
7333 * @dev_priv: i915 private structure
7334 * @pipe: pipe PLL to disable
7335 *
7336 * Disable the PLL for @pipe. To be used in cases where we need
7337 * the PLL enabled even when @pipe is not going to be enabled.
7338 */
7339void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7340{
7341 if (IS_CHERRYVIEW(dev))
7342 chv_disable_pll(to_i915(dev), pipe);
7343 else
7344 vlv_disable_pll(to_i915(dev), pipe);
7345}
7346
f47709a9 7347static void i9xx_update_pll(struct intel_crtc *crtc,
190f68c5 7348 struct intel_crtc_state *crtc_state,
f47709a9 7349 intel_clock_t *reduced_clock,
eb1cbe48
DV		 7350 int num_connectors)
7351{
f47709a9 7352 struct drm_device *dev = crtc->base.dev;
eb1cbe48 7353 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48
DV		 7354 u32 dpll;
7355 bool is_sdvo;
190f68c5 7356 struct dpll *clock = &crtc_state->dpll;
eb1cbe48 7357
190f68c5 7358 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
2a8f64ca 7359
a93e255f
ACO		 7360 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7361 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 7362
7363 dpll = DPLL_VGA_MODE_DIS;
7364
a93e255f 7365 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 7366 dpll |= DPLLB_MODE_LVDS;
7367 else
7368 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 7369
ef1b460d 7370 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
190f68c5 7371 dpll |= (crtc_state->pixel_multiplier - 1)
198a037f 7372 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 7373 }
198a037f
DV		 7374
7375 if (is_sdvo)
4a33e48d 7376 dpll |= DPLL_SDVO_HIGH_SPEED;
198a037f 7377
190f68c5 7378 if (crtc_state->has_dp_encoder)
4a33e48d 7379 dpll |= DPLL_SDVO_HIGH_SPEED;
eb1cbe48
DV		 7380
7381 /* compute bitmask from p1 value */
7382 if (IS_PINEVIEW(dev))
7383 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7384 else {
7385 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7386 if (IS_G4X(dev) && reduced_clock)
7387 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7388 }
7389 switch (clock->p2) {
7390 case 5:
7391 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7392 break;
7393 case 7:
7394 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7395 break;
7396 case 10:
7397 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7398 break;
7399 case 14:
7400 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7401 break;
7402 }
7403 if (INTEL_INFO(dev)->gen >= 4)
7404 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7405
190f68c5 7406 if (crtc_state->sdvo_tv_clock)
eb1cbe48 7407 dpll |= PLL_REF_INPUT_TVCLKINBC;
a93e255f 7408 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 7409 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7410 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7411 else
7412 dpll |= PLL_REF_INPUT_DREFCLK;
7413
7414 dpll |= DPLL_VCO_ENABLE;
190f68c5 7415 crtc_state->dpll_hw_state.dpll = dpll;
8bcc2795 7416
eb1cbe48 7417 if (INTEL_INFO(dev)->gen >= 4) {
190f68c5 7418 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
ef1b460d 7419 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
190f68c5 7420 crtc_state->dpll_hw_state.dpll_md = dpll_md;
eb1cbe48
DV		 7421 }
7422}
7423
f47709a9 7424static void i8xx_update_pll(struct intel_crtc *crtc,
190f68c5 7425 struct intel_crtc_state *crtc_state,
f47709a9 7426 intel_clock_t *reduced_clock,
eb1cbe48
DV		 7427 int num_connectors)
7428{
f47709a9 7429 struct drm_device *dev = crtc->base.dev;
eb1cbe48 7430 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48 7431 u32 dpll;
190f68c5 7432 struct dpll *clock = &crtc_state->dpll;
eb1cbe48 7433
190f68c5 7434 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
2a8f64ca 7435
eb1cbe48
DV		 7436 dpll = DPLL_VGA_MODE_DIS;
7437
a93e255f 7438 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 7439 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7440 } else {
7441 if (clock->p1 == 2)
7442 dpll |= PLL_P1_DIVIDE_BY_TWO;
7443 else
7444 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7445 if (clock->p2 == 4)
7446 dpll |= PLL_P2_DIVIDE_BY_4;
7447 }
7448
a93e255f 7449 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
4a33e48d
DV		 7450 dpll |= DPLL_DVO_2X_MODE;
7451
a93e255f 7452 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 7453 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7454 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7455 else
7456 dpll |= PLL_REF_INPUT_DREFCLK;
7457
7458 dpll |= DPLL_VCO_ENABLE;
190f68c5 7459 crtc_state->dpll_hw_state.dpll = dpll;
eb1cbe48
DV		 7460}
7461
8a654f3b 7462static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
b0e77b9c
PZ		 7463{
7464 struct drm_device *dev = intel_crtc->base.dev;
7465 struct drm_i915_private *dev_priv = dev->dev_private;
7466 enum pipe pipe = intel_crtc->pipe;
6e3c9717 7467 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8a654f3b 7468 struct drm_display_mode *adjusted_mode =
6e3c9717 7469 &intel_crtc->config->base.adjusted_mode;
1caea6e9
VS		 7470 uint32_t crtc_vtotal, crtc_vblank_end;
7471 int vsyncshift = 0;
4d8a62ea
DV		 7472
7473 /* We need to be careful not to changed the adjusted mode, for otherwise
7474 * the hw state checker will get angry at the mismatch. */
7475 crtc_vtotal = adjusted_mode->crtc_vtotal;
7476 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
b0e77b9c 7477
609aeaca 7478 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
b0e77b9c 7479 /* the chip adds 2 halflines automatically */
4d8a62ea
DV		 7480 crtc_vtotal -= 1;
7481 crtc_vblank_end -= 1;
609aeaca 7482
409ee761 7483 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
609aeaca
VS		 7484 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7485 else
7486 vsyncshift = adjusted_mode->crtc_hsync_start -
7487 adjusted_mode->crtc_htotal / 2;
1caea6e9
VS		 7488 if (vsyncshift < 0)
7489 vsyncshift += adjusted_mode->crtc_htotal;
b0e77b9c
PZ		 7490 }
7491
7492 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 7493 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 7494
fe2b8f9d 7495 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 7496 (adjusted_mode->crtc_hdisplay - 1) |
7497 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 7498 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 7499 (adjusted_mode->crtc_hblank_start - 1) |
7500 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 7501 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 7502 (adjusted_mode->crtc_hsync_start - 1) |
7503 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7504
fe2b8f9d 7505 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c 7506 (adjusted_mode->crtc_vdisplay - 1) |
4d8a62ea 7507 ((crtc_vtotal - 1) << 16));
fe2b8f9d 7508 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c 7509 (adjusted_mode->crtc_vblank_start - 1) |
4d8a62ea 7510 ((crtc_vblank_end - 1) << 16));
fe2b8f9d 7511 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 7512 (adjusted_mode->crtc_vsync_start - 1) |
7513 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7514
b5e508d4
PZ		 7515 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7516 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7517 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7518 * bits. */
7519 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7520 (pipe == PIPE_B || pipe == PIPE_C))
7521 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7522
b0e77b9c
PZ		 7523 /* pipesrc controls the size that is scaled from, which should
7524 * always be the user's requested size.
7525 */
7526 I915_WRITE(PIPESRC(pipe),
6e3c9717
ACO		 7527 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7528 (intel_crtc->config->pipe_src_h - 1));
b0e77b9c
PZ		 7529}
7530
1bd1bd80 7531static void intel_get_pipe_timings(struct intel_crtc *crtc,
5cec258b 7532 struct intel_crtc_state *pipe_config)
1bd1bd80
DV		 7533{
7534 struct drm_device *dev = crtc->base.dev;
7535 struct drm_i915_private *dev_priv = dev->dev_private;
7536 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7537 uint32_t tmp;
7538
7539 tmp = I915_READ(HTOTAL(cpu_transcoder));
2d112de7
ACO		 7540 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7541 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7542 tmp = I915_READ(HBLANK(cpu_transcoder));
2d112de7
ACO		 7543 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7544 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7545 tmp = I915_READ(HSYNC(cpu_transcoder));
2d112de7
ACO		 7546 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7547 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80
DV		 7548
7549 tmp = I915_READ(VTOTAL(cpu_transcoder));
2d112de7
ACO		 7550 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7551 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7552 tmp = I915_READ(VBLANK(cpu_transcoder));
2d112de7
ACO		 7553 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7554 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7555 tmp = I915_READ(VSYNC(cpu_transcoder));
2d112de7
ACO		 7556 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7557 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80
DV		 7558
7559 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
2d112de7
ACO		 7560 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7561 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7562 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
1bd1bd80
DV		 7563 }
7564
7565 tmp = I915_READ(PIPESRC(crtc->pipe));
37327abd
VS		 7566 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7567 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7568
2d112de7
ACO		 7569 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7570 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
1bd1bd80
DV		 7571}
7572
f6a83288 7573void intel_mode_from_pipe_config(struct drm_display_mode *mode,
5cec258b 7574 struct intel_crtc_state *pipe_config)
babea61d 7575{
2d112de7
ACO		 7576 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7577 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7578 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7579 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
babea61d 7580
2d112de7
ACO		 7581 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7582 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7583 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7584 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
babea61d 7585
2d112de7 7586 mode->flags = pipe_config->base.adjusted_mode.flags;
babea61d 7587
2d112de7
ACO		 7588 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7589 mode->flags |= pipe_config->base.adjusted_mode.flags;
babea61d
JB		 7590}
7591
84b046f3
DV		 7592static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7593{
7594 struct drm_device *dev = intel_crtc->base.dev;
7595 struct drm_i915_private *dev_priv = dev->dev_private;
7596 uint32_t pipeconf;
7597
9f11a9e4 7598 pipeconf = 0;
84b046f3 7599
b6b5d049
VS		 7600 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7601 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7602 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
67c72a12 7603
6e3c9717 7604 if (intel_crtc->config->double_wide)
cf532bb2 7605 pipeconf |= PIPECONF_DOUBLE_WIDE;
84b046f3 7606
ff9ce46e
DV		 7607 /* only g4x and later have fancy bpc/dither controls */
7608 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
ff9ce46e 7609 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6e3c9717 7610 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
ff9ce46e 7611 pipeconf |= PIPECONF_DITHER_EN |
84b046f3 7612 PIPECONF_DITHER_TYPE_SP;
84b046f3 7613
6e3c9717 7614 switch (intel_crtc->config->pipe_bpp) {
ff9ce46e
DV		 7615 case 18:
7616 pipeconf |= PIPECONF_6BPC;
7617 break;
7618 case 24:
7619 pipeconf |= PIPECONF_8BPC;
7620 break;
7621 case 30:
7622 pipeconf |= PIPECONF_10BPC;
7623 break;
7624 default:
7625 /* Case prevented by intel_choose_pipe_bpp_dither. */
7626 BUG();
84b046f3
DV		 7627 }
7628 }
7629
7630 if (HAS_PIPE_CXSR(dev)) {
7631 if (intel_crtc->lowfreq_avail) {
7632 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7633 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7634 } else {
7635 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
84b046f3
DV		 7636 }
7637 }
7638
6e3c9717 7639 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
efc2cfff 7640 if (INTEL_INFO(dev)->gen < 4 ||
409ee761 7641 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
efc2cfff
VS		 7642 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7643 else
7644 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7645 } else
84b046f3
DV		 7646 pipeconf |= PIPECONF_PROGRESSIVE;
7647
6e3c9717 7648 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
9f11a9e4 7649 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
9c8e09b7 7650
84b046f3
DV		 7651 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7652 POSTING_READ(PIPECONF(intel_crtc->pipe));
7653}
7654
190f68c5
ACO		 7655static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7656 struct intel_crtc_state *crtc_state)
79e53945 7657{
c7653199 7658 struct drm_device *dev = crtc->base.dev;
79e53945 7659 struct drm_i915_private *dev_priv = dev->dev_private;
c751ce4f 7660 int refclk, num_connectors = 0;
652c393a 7661 intel_clock_t clock, reduced_clock;
a16af721 7662 bool ok, has_reduced_clock = false;
e9fd1c02 7663 bool is_lvds = false, is_dsi = false;
5eddb70b 7664 struct intel_encoder *encoder;
d4906093 7665 const intel_limit_t *limit;
55bb9992 7666 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 7667 struct drm_connector *connector;
55bb9992
ACO		 7668 struct drm_connector_state *connector_state;
7669 int i;
79e53945 7670
dd3cd74a
ACO		 7671 memset(&crtc_state->dpll_hw_state, 0,
7672 sizeof(crtc_state->dpll_hw_state));
7673
da3ced29 7674 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO		 7675 if (connector_state->crtc != &crtc->base)
7676 continue;
7677
7678 encoder = to_intel_encoder(connector_state->best_encoder);
7679
5eddb70b 7680 switch (encoder->type) {
79e53945
JB		 7681 case INTEL_OUTPUT_LVDS:
7682 is_lvds = true;
7683 break;
e9fd1c02
JN		 7684 case INTEL_OUTPUT_DSI:
7685 is_dsi = true;
7686 break;
6847d71b
PZ		 7687 default:
7688 break;
79e53945 7689 }
43565a06 7690
c751ce4f 7691 num_connectors++;
79e53945
JB		 7692 }
7693
f2335330 7694 if (is_dsi)
5b18e57c 7695 return 0;
f2335330 7696
190f68c5 7697 if (!crtc_state->clock_set) {
a93e255f 7698 refclk = i9xx_get_refclk(crtc_state, num_connectors);
79e53945 7699
e9fd1c02
JN		 7700 /*
7701 * Returns a set of divisors for the desired target clock with
7702 * the given refclk, or FALSE. The returned values represent
7703 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7704 * 2) / p1 / p2.
7705 */
a93e255f
ACO		 7706 limit = intel_limit(crtc_state, refclk);
7707 ok = dev_priv->display.find_dpll(limit, crtc_state,
190f68c5 7708 crtc_state->port_clock,
e9fd1c02 7709 refclk, NULL, &clock);
f2335330 7710 if (!ok) {
e9fd1c02
JN		 7711 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7712 return -EINVAL;
7713 }
79e53945 7714
f2335330
JN		 7715 if (is_lvds && dev_priv->lvds_downclock_avail) {
7716 /*
7717 * Ensure we match the reduced clock's P to the target
7718 * clock. If the clocks don't match, we can't switch
7719 * the display clock by using the FP0/FP1. In such case
7720 * we will disable the LVDS downclock feature.
7721 */
7722 has_reduced_clock =
a93e255f 7723 dev_priv->display.find_dpll(limit, crtc_state,
f2335330
JN		 7724 dev_priv->lvds_downclock,
7725 refclk, &clock,
7726 &reduced_clock);
7727 }
7728 /* Compat-code for transition, will disappear. */
190f68c5
ACO		 7729 crtc_state->dpll.n = clock.n;
7730 crtc_state->dpll.m1 = clock.m1;
7731 crtc_state->dpll.m2 = clock.m2;
7732 crtc_state->dpll.p1 = clock.p1;
7733 crtc_state->dpll.p2 = clock.p2;
f47709a9 7734 }
7026d4ac 7735
e9fd1c02 7736 if (IS_GEN2(dev)) {
190f68c5 7737 i8xx_update_pll(crtc, crtc_state,
2a8f64ca
VP		 7738 has_reduced_clock ? &reduced_clock : NULL,
7739 num_connectors);
9d556c99 7740 } else if (IS_CHERRYVIEW(dev)) {
190f68c5 7741 chv_update_pll(crtc, crtc_state);
e9fd1c02 7742 } else if (IS_VALLEYVIEW(dev)) {
190f68c5 7743 vlv_update_pll(crtc, crtc_state);
e9fd1c02 7744 } else {
190f68c5 7745 i9xx_update_pll(crtc, crtc_state,
eb1cbe48 7746 has_reduced_clock ? &reduced_clock : NULL,
eba905b2 7747 num_connectors);
e9fd1c02 7748 }
79e53945 7749
c8f7a0db 7750 return 0;
f564048e
EA		 7751}
7752
2fa2fe9a 7753static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5cec258b 7754 struct intel_crtc_state *pipe_config)
2fa2fe9a
DV		 7755{
7756 struct drm_device *dev = crtc->base.dev;
7757 struct drm_i915_private *dev_priv = dev->dev_private;
7758 uint32_t tmp;
7759
dc9e7dec
VS		 7760 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7761 return;
7762
2fa2fe9a 7763 tmp = I915_READ(PFIT_CONTROL);
06922821
DV		 7764 if (!(tmp & PFIT_ENABLE))
7765 return;
2fa2fe9a 7766
06922821 7767 /* Check whether the pfit is attached to our pipe. */
2fa2fe9a
DV		 7768 if (INTEL_INFO(dev)->gen < 4) {
7769 if (crtc->pipe != PIPE_B)
7770 return;
2fa2fe9a
DV		 7771 } else {
7772 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7773 return;
7774 }
7775
06922821 7776 pipe_config->gmch_pfit.control = tmp;
2fa2fe9a
DV		 7777 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7778 if (INTEL_INFO(dev)->gen < 5)
7779 pipe_config->gmch_pfit.lvds_border_bits =
7780 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7781}
7782
acbec814 7783static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 7784 struct intel_crtc_state *pipe_config)
acbec814
JB		 7785{
7786 struct drm_device *dev = crtc->base.dev;
7787 struct drm_i915_private *dev_priv = dev->dev_private;
7788 int pipe = pipe_config->cpu_transcoder;
7789 intel_clock_t clock;
7790 u32 mdiv;
662c6ecb 7791 int refclk = 100000;
acbec814 7792
f573de5a
SK		 7793 /* In case of MIPI DPLL will not even be used */
7794 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
7795 return;
7796
acbec814 7797 mutex_lock(&dev_priv->dpio_lock);
ab3c759a 7798 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
acbec814
JB		 7799 mutex_unlock(&dev_priv->dpio_lock);
7800
7801 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7802 clock.m2 = mdiv & DPIO_M2DIV_MASK;
7803 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7804 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7805 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7806
f646628b 7807 vlv_clock(refclk, &clock);
acbec814 7808
f646628b
VS		 7809 /* clock.dot is the fast clock */
7810 pipe_config->port_clock = clock.dot / 5;
acbec814
JB		 7811}
7812
5724dbd1
DL		 7813static void
7814i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7815 struct intel_initial_plane_config *plane_config)
1ad292b5
JB		 7816{
7817 struct drm_device *dev = crtc->base.dev;
7818 struct drm_i915_private *dev_priv = dev->dev_private;
7819 u32 val, base, offset;
7820 int pipe = crtc->pipe, plane = crtc->plane;
7821 int fourcc, pixel_format;
6761dd31 7822 unsigned int aligned_height;
b113d5ee 7823 struct drm_framebuffer *fb;
1b842c89 7824 struct intel_framebuffer *intel_fb;
1ad292b5 7825
42a7b088
DL		 7826 val = I915_READ(DSPCNTR(plane));
7827 if (!(val & DISPLAY_PLANE_ENABLE))
7828 return;
7829
d9806c9f 7830 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 7831 if (!intel_fb) {
1ad292b5
JB		 7832 DRM_DEBUG_KMS("failed to alloc fb\n");
7833 return;
7834 }
7835
1b842c89
DL		 7836 fb = &intel_fb->base;
7837
18c5247e
DV		 7838 if (INTEL_INFO(dev)->gen >= 4) {
7839 if (val & DISPPLANE_TILED) {
49af449b 7840 plane_config->tiling = I915_TILING_X;
18c5247e
DV		 7841 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7842 }
7843 }
1ad292b5
JB		 7844
7845 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
b35d63fa 7846 fourcc = i9xx_format_to_fourcc(pixel_format);
b113d5ee
DL		 7847 fb->pixel_format = fourcc;
7848 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
1ad292b5
JB		 7849
7850 if (INTEL_INFO(dev)->gen >= 4) {
49af449b 7851 if (plane_config->tiling)
1ad292b5
JB		 7852 offset = I915_READ(DSPTILEOFF(plane));
7853 else
7854 offset = I915_READ(DSPLINOFF(plane));
7855 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7856 } else {
7857 base = I915_READ(DSPADDR(plane));
7858 }
7859 plane_config->base = base;
7860
7861 val = I915_READ(PIPESRC(pipe));
b113d5ee
DL		 7862 fb->width = ((val >> 16) & 0xfff) + 1;
7863 fb->height = ((val >> 0) & 0xfff) + 1;
1ad292b5
JB		 7864
7865 val = I915_READ(DSPSTRIDE(pipe));
b113d5ee 7866 fb->pitches[0] = val & 0xffffffc0;
1ad292b5 7867
b113d5ee 7868 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 7869 fb->pixel_format,
7870 fb->modifier[0]);
1ad292b5 7871
f37b5c2b 7872 plane_config->size = fb->pitches[0] * aligned_height;
1ad292b5 7873
2844a921
DL		 7874 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7875 pipe_name(pipe), plane, fb->width, fb->height,
7876 fb->bits_per_pixel, base, fb->pitches[0],
7877 plane_config->size);
1ad292b5 7878
2d14030b 7879 plane_config->fb = intel_fb;
1ad292b5
JB		 7880}
7881
70b23a98 7882static void chv_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 7883 struct intel_crtc_state *pipe_config)
70b23a98
VS		 7884{
7885 struct drm_device *dev = crtc->base.dev;
7886 struct drm_i915_private *dev_priv = dev->dev_private;
7887 int pipe = pipe_config->cpu_transcoder;
7888 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7889 intel_clock_t clock;
7890 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
7891 int refclk = 100000;
7892
7893 mutex_lock(&dev_priv->dpio_lock);
7894 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
7895 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
7896 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
7897 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
7898 mutex_unlock(&dev_priv->dpio_lock);
7899
7900 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
7901 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
7902 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
7903 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
7904 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
7905
7906 chv_clock(refclk, &clock);
7907
7908 /* clock.dot is the fast clock */
7909 pipe_config->port_clock = clock.dot / 5;
7910}
7911
0e8ffe1b 7912static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5cec258b 7913 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 7914{
7915 struct drm_device *dev = crtc->base.dev;
7916 struct drm_i915_private *dev_priv = dev->dev_private;
7917 uint32_t tmp;
7918
f458ebbc
DV		 7919 if (!intel_display_power_is_enabled(dev_priv,
7920 POWER_DOMAIN_PIPE(crtc->pipe)))
b5482bd0
ID		 7921 return false;
7922
e143a21c 7923 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 7924 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 7925
0e8ffe1b
DV		 7926 tmp = I915_READ(PIPECONF(crtc->pipe));
7927 if (!(tmp & PIPECONF_ENABLE))
7928 return false;
7929
42571aef
VS		 7930 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
7931 switch (tmp & PIPECONF_BPC_MASK) {
7932 case PIPECONF_6BPC:
7933 pipe_config->pipe_bpp = 18;
7934 break;
7935 case PIPECONF_8BPC:
7936 pipe_config->pipe_bpp = 24;
7937 break;
7938 case PIPECONF_10BPC:
7939 pipe_config->pipe_bpp = 30;
7940 break;
7941 default:
7942 break;
7943 }
7944 }
7945
b5a9fa09
DV		 7946 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
7947 pipe_config->limited_color_range = true;
7948
282740f7
VS		 7949 if (INTEL_INFO(dev)->gen < 4)
7950 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
7951
1bd1bd80
DV		 7952 intel_get_pipe_timings(crtc, pipe_config);
7953
2fa2fe9a
DV		 7954 i9xx_get_pfit_config(crtc, pipe_config);
7955
6c49f241
DV		 7956 if (INTEL_INFO(dev)->gen >= 4) {
7957 tmp = I915_READ(DPLL_MD(crtc->pipe));
7958 pipe_config->pixel_multiplier =
7959 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
7960 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8bcc2795 7961 pipe_config->dpll_hw_state.dpll_md = tmp;
6c49f241
DV		 7962 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7963 tmp = I915_READ(DPLL(crtc->pipe));
7964 pipe_config->pixel_multiplier =
7965 ((tmp & SDVO_MULTIPLIER_MASK)
7966 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
7967 } else {
7968 /* Note that on i915G/GM the pixel multiplier is in the sdvo
7969 * port and will be fixed up in the encoder->get_config
7970 * function. */
7971 pipe_config->pixel_multiplier = 1;
7972 }
8bcc2795
DV		 7973 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
7974 if (!IS_VALLEYVIEW(dev)) {
1c4e0274
VS		 7975 /*
7976 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
7977 * on 830. Filter it out here so that we don't
7978 * report errors due to that.
7979 */
7980 if (IS_I830(dev))
7981 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
7982
8bcc2795
DV		 7983 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
7984 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
165e901c
VS		 7985 } else {
7986 /* Mask out read-only status bits. */
7987 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
7988 DPLL_PORTC_READY_MASK |
7989 DPLL_PORTB_READY_MASK);
8bcc2795 7990 }
6c49f241 7991
70b23a98
VS		 7992 if (IS_CHERRYVIEW(dev))
7993 chv_crtc_clock_get(crtc, pipe_config);
7994 else if (IS_VALLEYVIEW(dev))
acbec814
JB		 7995 vlv_crtc_clock_get(crtc, pipe_config);
7996 else
7997 i9xx_crtc_clock_get(crtc, pipe_config);
18442d08 7998
0e8ffe1b
DV		 7999 return true;
8000}
8001
dde86e2d 8002static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 8003{
8004 struct drm_i915_private *dev_priv = dev->dev_private;
13d83a67 8005 struct intel_encoder *encoder;
74cfd7ac 8006 u32 val, final;
13d83a67 8007 bool has_lvds = false;
199e5d79 8008 bool has_cpu_edp = false;
199e5d79 8009 bool has_panel = false;
99eb6a01
KP		 8010 bool has_ck505 = false;
8011 bool can_ssc = false;
13d83a67
JB		 8012
8013 /* We need to take the global config into account */
b2784e15 8014 for_each_intel_encoder(dev, encoder) {
199e5d79
KP		 8015 switch (encoder->type) {
8016 case INTEL_OUTPUT_LVDS:
8017 has_panel = true;
8018 has_lvds = true;
8019 break;
8020 case INTEL_OUTPUT_EDP:
8021 has_panel = true;
2de6905f 8022 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
199e5d79
KP		 8023 has_cpu_edp = true;
8024 break;
6847d71b
PZ		 8025 default:
8026 break;
13d83a67
JB		 8027 }
8028 }
8029
99eb6a01 8030 if (HAS_PCH_IBX(dev)) {
41aa3448 8031 has_ck505 = dev_priv->vbt.display_clock_mode;
99eb6a01
KP		 8032 can_ssc = has_ck505;
8033 } else {
8034 has_ck505 = false;
8035 can_ssc = true;
8036 }
8037
2de6905f
ID		 8038 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8039 has_panel, has_lvds, has_ck505);
13d83a67
JB		 8040
8041 /* Ironlake: try to setup display ref clock before DPLL
8042 * enabling. This is only under driver's control after
8043 * PCH B stepping, previous chipset stepping should be
8044 * ignoring this setting.
8045 */
74cfd7ac
CW		 8046 val = I915_READ(PCH_DREF_CONTROL);
8047
8048 /* As we must carefully and slowly disable/enable each source in turn,
8049 * compute the final state we want first and check if we need to
8050 * make any changes at all.
8051 */
8052 final = val;
8053 final &= ~DREF_NONSPREAD_SOURCE_MASK;
8054 if (has_ck505)
8055 final |= DREF_NONSPREAD_CK505_ENABLE;
8056 else
8057 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8058
8059 final &= ~DREF_SSC_SOURCE_MASK;
8060 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8061 final &= ~DREF_SSC1_ENABLE;
8062
8063 if (has_panel) {
8064 final |= DREF_SSC_SOURCE_ENABLE;
8065
8066 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8067 final |= DREF_SSC1_ENABLE;
8068
8069 if (has_cpu_edp) {
8070 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8071 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8072 else
8073 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8074 } else
8075 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8076 } else {
8077 final |= DREF_SSC_SOURCE_DISABLE;
8078 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8079 }
8080
8081 if (final == val)
8082 return;
8083
13d83a67 8084 /* Always enable nonspread source */
74cfd7ac 8085 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 8086
99eb6a01 8087 if (has_ck505)
74cfd7ac 8088 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 8089 else
74cfd7ac 8090 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 8091
199e5d79 8092 if (has_panel) {
74cfd7ac
CW		 8093 val &= ~DREF_SSC_SOURCE_MASK;
8094 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 8095
199e5d79 8096 /* SSC must be turned on before enabling the CPU output */
99eb6a01 8097 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 8098 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 8099 val |= DREF_SSC1_ENABLE;
e77166b5 8100 } else
74cfd7ac 8101 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 8102
8103 /* Get SSC going before enabling the outputs */
74cfd7ac 8104 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 8105 POSTING_READ(PCH_DREF_CONTROL);
8106 udelay(200);
8107
74cfd7ac 8108 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 8109
8110 /* Enable CPU source on CPU attached eDP */
199e5d79 8111 if (has_cpu_edp) {
99eb6a01 8112 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 8113 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 8114 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
eba905b2 8115 } else
74cfd7ac 8116 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 8117 } else
74cfd7ac 8118 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 8119
74cfd7ac 8120 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 8121 POSTING_READ(PCH_DREF_CONTROL);
8122 udelay(200);
8123 } else {
8124 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8125
74cfd7ac 8126 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 8127
8128 /* Turn off CPU output */
74cfd7ac 8129 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 8130
74cfd7ac 8131 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 8132 POSTING_READ(PCH_DREF_CONTROL);
8133 udelay(200);
8134
8135 /* Turn off the SSC source */
74cfd7ac
CW		 8136 val &= ~DREF_SSC_SOURCE_MASK;
8137 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 8138
8139 /* Turn off SSC1 */
74cfd7ac 8140 val &= ~DREF_SSC1_ENABLE;
199e5d79 8141
74cfd7ac 8142 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 8143 POSTING_READ(PCH_DREF_CONTROL);
8144 udelay(200);
8145 }
74cfd7ac
CW		 8146
8147 BUG_ON(val != final);
13d83a67
JB		 8148}
8149
f31f2d55 8150static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
dde86e2d 8151{
f31f2d55 8152 uint32_t tmp;
dde86e2d 8153
0ff066a9
PZ		 8154 tmp = I915_READ(SOUTH_CHICKEN2);
8155 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8156 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 8157
0ff066a9
PZ		 8158 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8159 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8160 DRM_ERROR("FDI mPHY reset assert timeout\n");
dde86e2d 8161
0ff066a9
PZ		 8162 tmp = I915_READ(SOUTH_CHICKEN2);
8163 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8164 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 8165
0ff066a9
PZ		 8166 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8167 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8168 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
f31f2d55
PZ		 8169}
8170
8171/* WaMPhyProgramming:hsw */
8172static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8173{
8174 uint32_t tmp;
dde86e2d
PZ		 8175
8176 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8177 tmp &= ~(0xFF << 24);
8178 tmp |= (0x12 << 24);
8179 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8180
dde86e2d
PZ		 8181 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8182 tmp |= (1 << 11);
8183 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8184
8185 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8186 tmp |= (1 << 11);
8187 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8188
dde86e2d
PZ		 8189 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8190 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8191 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8192
8193 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8194 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8195 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8196
0ff066a9
PZ		 8197 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8198 tmp &= ~(7 << 13);
8199 tmp |= (5 << 13);
8200 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
dde86e2d 8201
0ff066a9
PZ		 8202 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8203 tmp &= ~(7 << 13);
8204 tmp |= (5 << 13);
8205 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
dde86e2d
PZ		 8206
8207 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8208 tmp &= ~0xFF;
8209 tmp |= 0x1C;
8210 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8211
8212 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8213 tmp &= ~0xFF;
8214 tmp |= 0x1C;
8215 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8216
8217 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8218 tmp &= ~(0xFF << 16);
8219 tmp |= (0x1C << 16);
8220 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8221
8222 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8223 tmp &= ~(0xFF << 16);
8224 tmp |= (0x1C << 16);
8225 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8226
0ff066a9
PZ		 8227 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8228 tmp |= (1 << 27);
8229 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
dde86e2d 8230
0ff066a9
PZ		 8231 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8232 tmp |= (1 << 27);
8233 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
dde86e2d 8234
0ff066a9
PZ		 8235 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8236 tmp &= ~(0xF << 28);
8237 tmp |= (4 << 28);
8238 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
dde86e2d 8239
0ff066a9
PZ		 8240 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8241 tmp &= ~(0xF << 28);
8242 tmp |= (4 << 28);
8243 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
f31f2d55
PZ		 8244}
8245
2fa86a1f
PZ		 8246/* Implements 3 different sequences from BSpec chapter "Display iCLK
8247 * Programming" based on the parameters passed:
8248 * - Sequence to enable CLKOUT_DP
8249 * - Sequence to enable CLKOUT_DP without spread
8250 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8251 */
8252static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8253 bool with_fdi)
f31f2d55
PZ		 8254{
8255 struct drm_i915_private *dev_priv = dev->dev_private;
2fa86a1f
PZ		 8256 uint32_t reg, tmp;
8257
8258 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8259 with_spread = true;
8260 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
8261 with_fdi, "LP PCH doesn't have FDI\n"))
8262 with_fdi = false;
f31f2d55
PZ		 8263
8264 mutex_lock(&dev_priv->dpio_lock);
8265
8266 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8267 tmp &= ~SBI_SSCCTL_DISABLE;
8268 tmp |= SBI_SSCCTL_PATHALT;
8269 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8270
8271 udelay(24);
8272
2fa86a1f
PZ		 8273 if (with_spread) {
8274 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8275 tmp &= ~SBI_SSCCTL_PATHALT;
8276 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
f31f2d55 8277
2fa86a1f
PZ		 8278 if (with_fdi) {
8279 lpt_reset_fdi_mphy(dev_priv);
8280 lpt_program_fdi_mphy(dev_priv);
8281 }
8282 }
dde86e2d 8283
2fa86a1f
PZ		 8284 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8285 SBI_GEN0 : SBI_DBUFF0;
8286 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8287 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8288 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
c00db246
DV		 8289
8290 mutex_unlock(&dev_priv->dpio_lock);
dde86e2d
PZ		 8291}
8292
47701c3b
PZ		 8293/* Sequence to disable CLKOUT_DP */
8294static void lpt_disable_clkout_dp(struct drm_device *dev)
8295{
8296 struct drm_i915_private *dev_priv = dev->dev_private;
8297 uint32_t reg, tmp;
8298
8299 mutex_lock(&dev_priv->dpio_lock);
8300
8301 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8302 SBI_GEN0 : SBI_DBUFF0;
8303 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8304 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8305 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8306
8307 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8308 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8309 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8310 tmp |= SBI_SSCCTL_PATHALT;
8311 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8312 udelay(32);
8313 }
8314 tmp |= SBI_SSCCTL_DISABLE;
8315 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8316 }
8317
8318 mutex_unlock(&dev_priv->dpio_lock);
8319}
8320
bf8fa3d3
PZ		 8321static void lpt_init_pch_refclk(struct drm_device *dev)
8322{
bf8fa3d3
PZ		 8323 struct intel_encoder *encoder;
8324 bool has_vga = false;
8325
b2784e15 8326 for_each_intel_encoder(dev, encoder) {
bf8fa3d3
PZ		 8327 switch (encoder->type) {
8328 case INTEL_OUTPUT_ANALOG:
8329 has_vga = true;
8330 break;
6847d71b
PZ		 8331 default:
8332 break;
bf8fa3d3
PZ		 8333 }
8334 }
8335
47701c3b
PZ		 8336 if (has_vga)
8337 lpt_enable_clkout_dp(dev, true, true);
8338 else
8339 lpt_disable_clkout_dp(dev);
bf8fa3d3
PZ		 8340}
8341
dde86e2d
PZ		 8342/*
8343 * Initialize reference clocks when the driver loads
8344 */
8345void intel_init_pch_refclk(struct drm_device *dev)
8346{
8347 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8348 ironlake_init_pch_refclk(dev);
8349 else if (HAS_PCH_LPT(dev))
8350 lpt_init_pch_refclk(dev);
8351}
8352
55bb9992 8353static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
d9d444cb 8354{
55bb9992 8355 struct drm_device *dev = crtc_state->base.crtc->dev;
d9d444cb 8356 struct drm_i915_private *dev_priv = dev->dev_private;
55bb9992 8357 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 8358 struct drm_connector *connector;
55bb9992 8359 struct drm_connector_state *connector_state;
d9d444cb 8360 struct intel_encoder *encoder;
55bb9992 8361 int num_connectors = 0, i;
d9d444cb
JB		 8362 bool is_lvds = false;
8363
da3ced29 8364 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO		 8365 if (connector_state->crtc != crtc_state->base.crtc)
8366 continue;
8367
8368 encoder = to_intel_encoder(connector_state->best_encoder);
8369
d9d444cb
JB		 8370 switch (encoder->type) {
8371 case INTEL_OUTPUT_LVDS:
8372 is_lvds = true;
8373 break;
6847d71b
PZ		 8374 default:
8375 break;
d9d444cb
JB		 8376 }
8377 num_connectors++;
8378 }
8379
8380 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
e91e941b 8381 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
41aa3448 8382 dev_priv->vbt.lvds_ssc_freq);
e91e941b 8383 return dev_priv->vbt.lvds_ssc_freq;
d9d444cb
JB		 8384 }
8385
8386 return 120000;
8387}
8388
6ff93609 8389static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 8390{
c8203565 8391 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 8392 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8393 int pipe = intel_crtc->pipe;
c8203565
PZ		 8394 uint32_t val;
8395
78114071 8396 val = 0;
c8203565 8397
6e3c9717 8398 switch (intel_crtc->config->pipe_bpp) {
c8203565 8399 case 18:
dfd07d72 8400 val |= PIPECONF_6BPC;
c8203565
PZ		 8401 break;
8402 case 24:
dfd07d72 8403 val |= PIPECONF_8BPC;
c8203565
PZ		 8404 break;
8405 case 30:
dfd07d72 8406 val |= PIPECONF_10BPC;
c8203565
PZ		 8407 break;
8408 case 36:
dfd07d72 8409 val |= PIPECONF_12BPC;
c8203565
PZ		 8410 break;
8411 default:
cc769b62
PZ		 8412 /* Case prevented by intel_choose_pipe_bpp_dither. */
8413 BUG();
c8203565
PZ		 8414 }
8415
6e3c9717 8416 if (intel_crtc->config->dither)
c8203565
PZ		 8417 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8418
6e3c9717 8419 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ		 8420 val |= PIPECONF_INTERLACED_ILK;
8421 else
8422 val |= PIPECONF_PROGRESSIVE;
8423
6e3c9717 8424 if (intel_crtc->config->limited_color_range)
3685a8f3 8425 val |= PIPECONF_COLOR_RANGE_SELECT;
3685a8f3 8426
c8203565
PZ		 8427 I915_WRITE(PIPECONF(pipe), val);
8428 POSTING_READ(PIPECONF(pipe));
8429}
8430
86d3efce
VS		 8431/*
8432 * Set up the pipe CSC unit.
8433 *
8434 * Currently only full range RGB to limited range RGB conversion
8435 * is supported, but eventually this should handle various
8436 * RGB<->YCbCr scenarios as well.
8437 */
50f3b016 8438static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 8439{
8440 struct drm_device *dev = crtc->dev;
8441 struct drm_i915_private *dev_priv = dev->dev_private;
8442 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8443 int pipe = intel_crtc->pipe;
8444 uint16_t coeff = 0x7800; /* 1.0 */
8445
8446 /*
8447 * TODO: Check what kind of values actually come out of the pipe
8448 * with these coeff/postoff values and adjust to get the best
8449 * accuracy. Perhaps we even need to take the bpc value into
8450 * consideration.
8451 */
8452
6e3c9717 8453 if (intel_crtc->config->limited_color_range)
86d3efce
VS		 8454 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8455
8456 /*
8457 * GY/GU and RY/RU should be the other way around according
8458 * to BSpec, but reality doesn't agree. Just set them up in
8459 * a way that results in the correct picture.
8460 */
8461 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8462 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8463
8464 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8465 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8466
8467 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8468 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8469
8470 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8471 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8472 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8473
8474 if (INTEL_INFO(dev)->gen > 6) {
8475 uint16_t postoff = 0;
8476
6e3c9717 8477 if (intel_crtc->config->limited_color_range)
32cf0cb0 8478 postoff = (16 * (1 << 12) / 255) & 0x1fff;
86d3efce
VS		 8479
8480 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8481 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8482 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8483
8484 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8485 } else {
8486 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8487
6e3c9717 8488 if (intel_crtc->config->limited_color_range)
86d3efce
VS		 8489 mode |= CSC_BLACK_SCREEN_OFFSET;
8490
8491 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8492 }
8493}
8494
6ff93609 8495static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38 8496{
756f85cf
PZ		 8497 struct drm_device *dev = crtc->dev;
8498 struct drm_i915_private *dev_priv = dev->dev_private;
ee2b0b38 8499 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
756f85cf 8500 enum pipe pipe = intel_crtc->pipe;
6e3c9717 8501 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
ee2b0b38
PZ		 8502 uint32_t val;
8503
3eff4faa 8504 val = 0;
ee2b0b38 8505
6e3c9717 8506 if (IS_HASWELL(dev) && intel_crtc->config->dither)
ee2b0b38
PZ		 8507 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8508
6e3c9717 8509 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ		 8510 val |= PIPECONF_INTERLACED_ILK;
8511 else
8512 val |= PIPECONF_PROGRESSIVE;
8513
702e7a56
PZ		 8514 I915_WRITE(PIPECONF(cpu_transcoder), val);
8515 POSTING_READ(PIPECONF(cpu_transcoder));
3eff4faa
DV		 8516
8517 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8518 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
756f85cf 8519
3cdf122c 8520 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
756f85cf
PZ		 8521 val = 0;
8522
6e3c9717 8523 switch (intel_crtc->config->pipe_bpp) {
756f85cf
PZ		 8524 case 18:
8525 val |= PIPEMISC_DITHER_6_BPC;
8526 break;
8527 case 24:
8528 val |= PIPEMISC_DITHER_8_BPC;
8529 break;
8530 case 30:
8531 val |= PIPEMISC_DITHER_10_BPC;
8532 break;
8533 case 36:
8534 val |= PIPEMISC_DITHER_12_BPC;
8535 break;
8536 default:
8537 /* Case prevented by pipe_config_set_bpp. */
8538 BUG();
8539 }
8540
6e3c9717 8541 if (intel_crtc->config->dither)
756f85cf
PZ		 8542 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8543
8544 I915_WRITE(PIPEMISC(pipe), val);
8545 }
ee2b0b38
PZ		 8546}
8547
6591c6e4 8548static bool ironlake_compute_clocks(struct drm_crtc *crtc,
190f68c5 8549 struct intel_crtc_state *crtc_state,
6591c6e4
PZ		 8550 intel_clock_t *clock,
8551 bool *has_reduced_clock,
8552 intel_clock_t *reduced_clock)
8553{
8554 struct drm_device *dev = crtc->dev;
8555 struct drm_i915_private *dev_priv = dev->dev_private;
6591c6e4 8556 int refclk;
d4906093 8557 const intel_limit_t *limit;
a16af721 8558 bool ret, is_lvds = false;
79e53945 8559
a93e255f 8560 is_lvds = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS);
79e53945 8561
55bb9992 8562 refclk = ironlake_get_refclk(crtc_state);
79e53945 8563
d4906093
ML		 8564 /*
8565 * Returns a set of divisors for the desired target clock with the given
8566 * refclk, or FALSE. The returned values represent the clock equation:
8567 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8568 */
a93e255f
ACO		 8569 limit = intel_limit(crtc_state, refclk);
8570 ret = dev_priv->display.find_dpll(limit, crtc_state,
190f68c5 8571 crtc_state->port_clock,
ee9300bb 8572 refclk, NULL, clock);
6591c6e4
PZ		 8573 if (!ret)
8574 return false;
cda4b7d3 8575
ddc9003c 8576 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 8577 /*
8578 * Ensure we match the reduced clock's P to the target clock.
8579 * If the clocks don't match, we can't switch the display clock
8580 * by using the FP0/FP1. In such case we will disable the LVDS
8581 * downclock feature.
8582 */
ee9300bb 8583 *has_reduced_clock =
a93e255f 8584 dev_priv->display.find_dpll(limit, crtc_state,
ee9300bb
DV		 8585 dev_priv->lvds_downclock,
8586 refclk, clock,
8587 reduced_clock);
652c393a 8588 }
61e9653f 8589
6591c6e4
PZ		 8590 return true;
8591}
8592
d4b1931c
PZ		 8593int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8594{
8595 /*
8596 * Account for spread spectrum to avoid
8597 * oversubscribing the link. Max center spread
8598 * is 2.5%; use 5% for safety's sake.
8599 */
8600 u32 bps = target_clock * bpp * 21 / 20;
619d4d04 8601 return DIV_ROUND_UP(bps, link_bw * 8);
d4b1931c
PZ		 8602}
8603
7429e9d4 8604static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6cf86a5e 8605{
7429e9d4 8606 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
f48d8f23
PZ		 8607}
8608
de13a2e3 8609static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
190f68c5 8610 struct intel_crtc_state *crtc_state,
7429e9d4 8611 u32 *fp,
9a7c7890 8612 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 8613{
de13a2e3 8614 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 8615 struct drm_device *dev = crtc->dev;
8616 struct drm_i915_private *dev_priv = dev->dev_private;
55bb9992 8617 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 8618 struct drm_connector *connector;
55bb9992
ACO		 8619 struct drm_connector_state *connector_state;
8620 struct intel_encoder *encoder;
de13a2e3 8621 uint32_t dpll;
55bb9992 8622 int factor, num_connectors = 0, i;
09ede541 8623 bool is_lvds = false, is_sdvo = false;
79e53945 8624
da3ced29 8625 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO		 8626 if (connector_state->crtc != crtc_state->base.crtc)
8627 continue;
8628
8629 encoder = to_intel_encoder(connector_state->best_encoder);
8630
8631 switch (encoder->type) {
79e53945
JB		 8632 case INTEL_OUTPUT_LVDS:
8633 is_lvds = true;
8634 break;
8635 case INTEL_OUTPUT_SDVO:
7d57382e 8636 case INTEL_OUTPUT_HDMI:
79e53945 8637 is_sdvo = true;
79e53945 8638 break;
6847d71b
PZ		 8639 default:
8640 break;
79e53945 8641 }
43565a06 8642
c751ce4f 8643 num_connectors++;
79e53945 8644 }
79e53945 8645
c1858123 8646 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 8647 factor = 21;
8648 if (is_lvds) {
8649 if ((intel_panel_use_ssc(dev_priv) &&
e91e941b 8650 dev_priv->vbt.lvds_ssc_freq == 100000) ||
f0b44056 8651 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297 8652 factor = 25;
190f68c5 8653 } else if (crtc_state->sdvo_tv_clock)
8febb297 8654 factor = 20;
c1858123 8655
190f68c5 8656 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
7d0ac5b7 8657 *fp |= FP_CB_TUNE;
2c07245f 8658
9a7c7890
DV		 8659 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8660 *fp2 |= FP_CB_TUNE;
8661
5eddb70b 8662 dpll = 0;
2c07245f 8663
a07d6787
EA		 8664 if (is_lvds)
8665 dpll |= DPLLB_MODE_LVDS;
8666 else
8667 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f 8668
190f68c5 8669 dpll |= (crtc_state->pixel_multiplier - 1)
ef1b460d 8670 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
198a037f
DV		 8671
8672 if (is_sdvo)
4a33e48d 8673 dpll |= DPLL_SDVO_HIGH_SPEED;
190f68c5 8674 if (crtc_state->has_dp_encoder)
4a33e48d 8675 dpll |= DPLL_SDVO_HIGH_SPEED;
79e53945 8676
a07d6787 8677 /* compute bitmask from p1 value */
190f68c5 8678 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 8679 /* also FPA1 */
190f68c5 8680 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 8681
190f68c5 8682 switch (crtc_state->dpll.p2) {
a07d6787
EA		 8683 case 5:
8684 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8685 break;
8686 case 7:
8687 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8688 break;
8689 case 10:
8690 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8691 break;
8692 case 14:
8693 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8694 break;
79e53945
JB		 8695 }
8696
b4c09f3b 8697 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 8698 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 8699 else
8700 dpll |= PLL_REF_INPUT_DREFCLK;
8701
959e16d6 8702 return dpll | DPLL_VCO_ENABLE;
de13a2e3
PZ		 8703}
8704
190f68c5
ACO		 8705static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8706 struct intel_crtc_state *crtc_state)
de13a2e3 8707{
c7653199 8708 struct drm_device *dev = crtc->base.dev;
de13a2e3 8709 intel_clock_t clock, reduced_clock;
cbbab5bd 8710 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 8711 bool ok, has_reduced_clock = false;
8b47047b 8712 bool is_lvds = false;
e2b78267 8713 struct intel_shared_dpll *pll;
de13a2e3 8714
dd3cd74a
ACO		 8715 memset(&crtc_state->dpll_hw_state, 0,
8716 sizeof(crtc_state->dpll_hw_state));
8717
409ee761 8718 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
79e53945 8719
5dc5298b
PZ		 8720 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8721 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 8722
190f68c5 8723 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
de13a2e3 8724 &has_reduced_clock, &reduced_clock);
190f68c5 8725 if (!ok && !crtc_state->clock_set) {
de13a2e3
PZ		 8726 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8727 return -EINVAL;
79e53945 8728 }
f47709a9 8729 /* Compat-code for transition, will disappear. */
190f68c5
ACO		 8730 if (!crtc_state->clock_set) {
8731 crtc_state->dpll.n = clock.n;
8732 crtc_state->dpll.m1 = clock.m1;
8733 crtc_state->dpll.m2 = clock.m2;
8734 crtc_state->dpll.p1 = clock.p1;
8735 crtc_state->dpll.p2 = clock.p2;
f47709a9 8736 }
79e53945 8737
5dc5298b 8738 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
190f68c5
ACO		 8739 if (crtc_state->has_pch_encoder) {
8740 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
cbbab5bd 8741 if (has_reduced_clock)
7429e9d4 8742 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 8743
190f68c5 8744 dpll = ironlake_compute_dpll(crtc, crtc_state,
cbbab5bd
DV		 8745 &fp, &reduced_clock,
8746 has_reduced_clock ? &fp2 : NULL);
8747
190f68c5
ACO		 8748 crtc_state->dpll_hw_state.dpll = dpll;
8749 crtc_state->dpll_hw_state.fp0 = fp;
66e985c0 8750 if (has_reduced_clock)
190f68c5 8751 crtc_state->dpll_hw_state.fp1 = fp2;
66e985c0 8752 else
190f68c5 8753 crtc_state->dpll_hw_state.fp1 = fp;
66e985c0 8754
190f68c5 8755 pll = intel_get_shared_dpll(crtc, crtc_state);
ee7b9f93 8756 if (pll == NULL) {
84f44ce7 8757 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
c7653199 8758 pipe_name(crtc->pipe));
4b645f14
JB		 8759 return -EINVAL;
8760 }
3fb37703 8761 }
79e53945 8762
ab585dea 8763 if (is_lvds && has_reduced_clock)
c7653199 8764 crtc->lowfreq_avail = true;
bcd644e0 8765 else
c7653199 8766 crtc->lowfreq_avail = false;
e2b78267 8767
c8f7a0db 8768 return 0;
79e53945
JB		 8769}
8770
eb14cb74
VS		 8771static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8772 struct intel_link_m_n *m_n)
8773{
8774 struct drm_device *dev = crtc->base.dev;
8775 struct drm_i915_private *dev_priv = dev->dev_private;
8776 enum pipe pipe = crtc->pipe;
8777
8778 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8779 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8780 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8781 & ~TU_SIZE_MASK;
8782 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8783 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8784 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8785}
8786
8787static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8788 enum transcoder transcoder,
b95af8be
VK		 8789 struct intel_link_m_n *m_n,
8790 struct intel_link_m_n *m2_n2)
72419203
DV		 8791{
8792 struct drm_device *dev = crtc->base.dev;
8793 struct drm_i915_private *dev_priv = dev->dev_private;
eb14cb74 8794 enum pipe pipe = crtc->pipe;
72419203 8795
eb14cb74
VS		 8796 if (INTEL_INFO(dev)->gen >= 5) {
8797 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8798 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8799 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8800 & ~TU_SIZE_MASK;
8801 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8802 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8803 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
b95af8be
VK		 8804 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8805 * gen < 8) and if DRRS is supported (to make sure the
8806 * registers are not unnecessarily read).
8807 */
8808 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
6e3c9717 8809 crtc->config->has_drrs) {
b95af8be
VK		 8810 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8811 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8812 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8813 & ~TU_SIZE_MASK;
8814 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8815 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8816 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8817 }
eb14cb74
VS		 8818 } else {
8819 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8820 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8821 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8822 & ~TU_SIZE_MASK;
8823 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8824 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8825 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8826 }
8827}
8828
8829void intel_dp_get_m_n(struct intel_crtc *crtc,
5cec258b 8830 struct intel_crtc_state *pipe_config)
eb14cb74 8831{
681a8504 8832 if (pipe_config->has_pch_encoder)
eb14cb74
VS		 8833 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8834 else
8835 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
b95af8be
VK		 8836 &pipe_config->dp_m_n,
8837 &pipe_config->dp_m2_n2);
eb14cb74 8838}
72419203 8839
eb14cb74 8840static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5cec258b 8841 struct intel_crtc_state *pipe_config)
eb14cb74
VS		 8842{
8843 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
b95af8be 8844 &pipe_config->fdi_m_n, NULL);
72419203
DV		 8845}
8846
bd2e244f 8847static void skylake_get_pfit_config(struct intel_crtc *crtc,
5cec258b 8848 struct intel_crtc_state *pipe_config)
bd2e244f
JB		 8849{
8850 struct drm_device *dev = crtc->base.dev;
8851 struct drm_i915_private *dev_priv = dev->dev_private;
a1b2278e
CK		 8852 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8853 uint32_t ps_ctrl = 0;
8854 int id = -1;
8855 int i;
bd2e244f 8856
a1b2278e
CK		 8857 /* find scaler attached to this pipe */
8858 for (i = 0; i < crtc->num_scalers; i++) {
8859 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
8860 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
8861 id = i;
8862 pipe_config->pch_pfit.enabled = true;
8863 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
8864 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
8865 break;
8866 }
8867 }
bd2e244f 8868
a1b2278e
CK		 8869 scaler_state->scaler_id = id;
8870 if (id >= 0) {
8871 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
8872 } else {
8873 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
bd2e244f
JB		 8874 }
8875}
8876
5724dbd1
DL		 8877static void
8878skylake_get_initial_plane_config(struct intel_crtc *crtc,
8879 struct intel_initial_plane_config *plane_config)
bc8d7dff
DL		 8880{
8881 struct drm_device *dev = crtc->base.dev;
8882 struct drm_i915_private *dev_priv = dev->dev_private;
40f46283 8883 u32 val, base, offset, stride_mult, tiling;
bc8d7dff
DL		 8884 int pipe = crtc->pipe;
8885 int fourcc, pixel_format;
6761dd31 8886 unsigned int aligned_height;
bc8d7dff 8887 struct drm_framebuffer *fb;
1b842c89 8888 struct intel_framebuffer *intel_fb;
bc8d7dff 8889
d9806c9f 8890 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 8891 if (!intel_fb) {
bc8d7dff
DL		 8892 DRM_DEBUG_KMS("failed to alloc fb\n");
8893 return;
8894 }
8895
1b842c89
DL		 8896 fb = &intel_fb->base;
8897
bc8d7dff 8898 val = I915_READ(PLANE_CTL(pipe, 0));
42a7b088
DL		 8899 if (!(val & PLANE_CTL_ENABLE))
8900 goto error;
8901
bc8d7dff
DL		 8902 pixel_format = val & PLANE_CTL_FORMAT_MASK;
8903 fourcc = skl_format_to_fourcc(pixel_format,
8904 val & PLANE_CTL_ORDER_RGBX,
8905 val & PLANE_CTL_ALPHA_MASK);
8906 fb->pixel_format = fourcc;
8907 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8908
40f46283
DL		 8909 tiling = val & PLANE_CTL_TILED_MASK;
8910 switch (tiling) {
8911 case PLANE_CTL_TILED_LINEAR:
8912 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
8913 break;
8914 case PLANE_CTL_TILED_X:
8915 plane_config->tiling = I915_TILING_X;
8916 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8917 break;
8918 case PLANE_CTL_TILED_Y:
8919 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
8920 break;
8921 case PLANE_CTL_TILED_YF:
8922 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
8923 break;
8924 default:
8925 MISSING_CASE(tiling);
8926 goto error;
8927 }
8928
bc8d7dff
DL		 8929 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
8930 plane_config->base = base;
8931
8932 offset = I915_READ(PLANE_OFFSET(pipe, 0));
8933
8934 val = I915_READ(PLANE_SIZE(pipe, 0));
8935 fb->height = ((val >> 16) & 0xfff) + 1;
8936 fb->width = ((val >> 0) & 0x1fff) + 1;
8937
8938 val = I915_READ(PLANE_STRIDE(pipe, 0));
40f46283
DL		 8939 stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
8940 fb->pixel_format);
bc8d7dff
DL		 8941 fb->pitches[0] = (val & 0x3ff) * stride_mult;
8942
8943 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 8944 fb->pixel_format,
8945 fb->modifier[0]);
bc8d7dff 8946
f37b5c2b 8947 plane_config->size = fb->pitches[0] * aligned_height;
bc8d7dff
DL		 8948
8949 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8950 pipe_name(pipe), fb->width, fb->height,
8951 fb->bits_per_pixel, base, fb->pitches[0],
8952 plane_config->size);
8953
2d14030b 8954 plane_config->fb = intel_fb;
bc8d7dff
DL		 8955 return;
8956
8957error:
8958 kfree(fb);
8959}
8960
2fa2fe9a 8961static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5cec258b 8962 struct intel_crtc_state *pipe_config)
2fa2fe9a
DV		 8963{
8964 struct drm_device *dev = crtc->base.dev;
8965 struct drm_i915_private *dev_priv = dev->dev_private;
8966 uint32_t tmp;
8967
8968 tmp = I915_READ(PF_CTL(crtc->pipe));
8969
8970 if (tmp & PF_ENABLE) {
fd4daa9c 8971 pipe_config->pch_pfit.enabled = true;
2fa2fe9a
DV		 8972 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
8973 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
cb8b2a30
DV		 8974
8975 /* We currently do not free assignements of panel fitters on
8976 * ivb/hsw (since we don't use the higher upscaling modes which
8977 * differentiates them) so just WARN about this case for now. */
8978 if (IS_GEN7(dev)) {
8979 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
8980 PF_PIPE_SEL_IVB(crtc->pipe));
8981 }
2fa2fe9a 8982 }
79e53945
JB		 8983}
8984
5724dbd1
DL		 8985static void
8986ironlake_get_initial_plane_config(struct intel_crtc *crtc,
8987 struct intel_initial_plane_config *plane_config)
4c6baa59
JB		 8988{
8989 struct drm_device *dev = crtc->base.dev;
8990 struct drm_i915_private *dev_priv = dev->dev_private;
8991 u32 val, base, offset;
aeee5a49 8992 int pipe = crtc->pipe;
4c6baa59 8993 int fourcc, pixel_format;
6761dd31 8994 unsigned int aligned_height;
b113d5ee 8995 struct drm_framebuffer *fb;
1b842c89 8996 struct intel_framebuffer *intel_fb;
4c6baa59 8997
42a7b088
DL		 8998 val = I915_READ(DSPCNTR(pipe));
8999 if (!(val & DISPLAY_PLANE_ENABLE))
9000 return;
9001
d9806c9f 9002 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 9003 if (!intel_fb) {
4c6baa59
JB		 9004 DRM_DEBUG_KMS("failed to alloc fb\n");
9005 return;
9006 }
9007
1b842c89
DL		 9008 fb = &intel_fb->base;
9009
18c5247e
DV		 9010 if (INTEL_INFO(dev)->gen >= 4) {
9011 if (val & DISPPLANE_TILED) {
49af449b 9012 plane_config->tiling = I915_TILING_X;
18c5247e
DV		 9013 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9014 }
9015 }
4c6baa59
JB		 9016
9017 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
b35d63fa 9018 fourcc = i9xx_format_to_fourcc(pixel_format);
b113d5ee
DL		 9019 fb->pixel_format = fourcc;
9020 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
4c6baa59 9021
aeee5a49 9022 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
4c6baa59 9023 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
aeee5a49 9024 offset = I915_READ(DSPOFFSET(pipe));
4c6baa59 9025 } else {
49af449b 9026 if (plane_config->tiling)
aeee5a49 9027 offset = I915_READ(DSPTILEOFF(pipe));
4c6baa59 9028 else
aeee5a49 9029 offset = I915_READ(DSPLINOFF(pipe));
4c6baa59
JB		 9030 }
9031 plane_config->base = base;
9032
9033 val = I915_READ(PIPESRC(pipe));
b113d5ee
DL		 9034 fb->width = ((val >> 16) & 0xfff) + 1;
9035 fb->height = ((val >> 0) & 0xfff) + 1;
4c6baa59
JB		 9036
9037 val = I915_READ(DSPSTRIDE(pipe));
b113d5ee 9038 fb->pitches[0] = val & 0xffffffc0;
4c6baa59 9039
b113d5ee 9040 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 9041 fb->pixel_format,
9042 fb->modifier[0]);
4c6baa59 9043
f37b5c2b 9044 plane_config->size = fb->pitches[0] * aligned_height;
4c6baa59 9045
2844a921
DL		 9046 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9047 pipe_name(pipe), fb->width, fb->height,
9048 fb->bits_per_pixel, base, fb->pitches[0],
9049 plane_config->size);
b113d5ee 9050
2d14030b 9051 plane_config->fb = intel_fb;
4c6baa59
JB		 9052}
9053
0e8ffe1b 9054static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5cec258b 9055 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 9056{
9057 struct drm_device *dev = crtc->base.dev;
9058 struct drm_i915_private *dev_priv = dev->dev_private;
9059 uint32_t tmp;
9060
f458ebbc
DV		 9061 if (!intel_display_power_is_enabled(dev_priv,
9062 POWER_DOMAIN_PIPE(crtc->pipe)))
930e8c9e
PZ		 9063 return false;
9064
e143a21c 9065 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 9066 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 9067
0e8ffe1b
DV		 9068 tmp = I915_READ(PIPECONF(crtc->pipe));
9069 if (!(tmp & PIPECONF_ENABLE))
9070 return false;
9071
42571aef
VS		 9072 switch (tmp & PIPECONF_BPC_MASK) {
9073 case PIPECONF_6BPC:
9074 pipe_config->pipe_bpp = 18;
9075 break;
9076 case PIPECONF_8BPC:
9077 pipe_config->pipe_bpp = 24;
9078 break;
9079 case PIPECONF_10BPC:
9080 pipe_config->pipe_bpp = 30;
9081 break;
9082 case PIPECONF_12BPC:
9083 pipe_config->pipe_bpp = 36;
9084 break;
9085 default:
9086 break;
9087 }
9088
b5a9fa09
DV		 9089 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9090 pipe_config->limited_color_range = true;
9091
ab9412ba 9092 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
66e985c0
DV		 9093 struct intel_shared_dpll *pll;
9094
88adfff1
DV		 9095 pipe_config->has_pch_encoder = true;
9096
627eb5a3
DV		 9097 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9098 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9099 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 9100
9101 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6c49f241 9102
c0d43d62 9103 if (HAS_PCH_IBX(dev_priv->dev)) {
d94ab068
DV		 9104 pipe_config->shared_dpll =
9105 (enum intel_dpll_id) crtc->pipe;
c0d43d62
DV		 9106 } else {
9107 tmp = I915_READ(PCH_DPLL_SEL);
9108 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9109 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
9110 else
9111 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
9112 }
66e985c0
DV		 9113
9114 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9115
9116 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9117 &pipe_config->dpll_hw_state));
c93f54cf
DV		 9118
9119 tmp = pipe_config->dpll_hw_state.dpll;
9120 pipe_config->pixel_multiplier =
9121 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9122 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
18442d08
VS		 9123
9124 ironlake_pch_clock_get(crtc, pipe_config);
6c49f241
DV		 9125 } else {
9126 pipe_config->pixel_multiplier = 1;
627eb5a3
DV		 9127 }
9128
1bd1bd80
DV		 9129 intel_get_pipe_timings(crtc, pipe_config);
9130
2fa2fe9a
DV		 9131 ironlake_get_pfit_config(crtc, pipe_config);
9132
0e8ffe1b
DV		 9133 return true;
9134}
9135
be256dc7
PZ		 9136static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9137{
9138 struct drm_device *dev = dev_priv->dev;
be256dc7 9139 struct intel_crtc *crtc;
be256dc7 9140
d3fcc808 9141 for_each_intel_crtc(dev, crtc)
e2c719b7 9142 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
be256dc7
PZ		 9143 pipe_name(crtc->pipe));
9144
e2c719b7
RC		 9145 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9146 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9147 I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9148 I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9149 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9150 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
be256dc7 9151 "CPU PWM1 enabled\n");
c5107b87 9152 if (IS_HASWELL(dev))
e2c719b7 9153 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
c5107b87 9154 "CPU PWM2 enabled\n");
e2c719b7 9155 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
be256dc7 9156 "PCH PWM1 enabled\n");
e2c719b7 9157 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
be256dc7 9158 "Utility pin enabled\n");
e2c719b7 9159 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
be256dc7 9160
9926ada1
PZ		 9161 /*
9162 * In theory we can still leave IRQs enabled, as long as only the HPD
9163 * interrupts remain enabled. We used to check for that, but since it's
9164 * gen-specific and since we only disable LCPLL after we fully disable
9165 * the interrupts, the check below should be enough.
9166 */
e2c719b7 9167 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
be256dc7
PZ		 9168}
9169
9ccd5aeb
PZ		 9170static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9171{
9172 struct drm_device *dev = dev_priv->dev;
9173
9174 if (IS_HASWELL(dev))
9175 return I915_READ(D_COMP_HSW);
9176 else
9177 return I915_READ(D_COMP_BDW);
9178}
9179
3c4c9b81
PZ		 9180static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9181{
9182 struct drm_device *dev = dev_priv->dev;
9183
9184 if (IS_HASWELL(dev)) {
9185 mutex_lock(&dev_priv->rps.hw_lock);
9186 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9187 val))
f475dadf 9188 DRM_ERROR("Failed to write to D_COMP\n");
3c4c9b81
PZ		 9189 mutex_unlock(&dev_priv->rps.hw_lock);
9190 } else {
9ccd5aeb
PZ		 9191 I915_WRITE(D_COMP_BDW, val);
9192 POSTING_READ(D_COMP_BDW);
3c4c9b81 9193 }
be256dc7
PZ		 9194}
9195
9196/*
9197 * This function implements pieces of two sequences from BSpec:
9198 * - Sequence for display software to disable LCPLL
9199 * - Sequence for display software to allow package C8+
9200 * The steps implemented here are just the steps that actually touch the LCPLL
9201 * register. Callers should take care of disabling all the display engine
9202 * functions, doing the mode unset, fixing interrupts, etc.
9203 */
6ff58d53
PZ		 9204static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9205 bool switch_to_fclk, bool allow_power_down)
be256dc7
PZ		 9206{
9207 uint32_t val;
9208
9209 assert_can_disable_lcpll(dev_priv);
9210
9211 val = I915_READ(LCPLL_CTL);
9212
9213 if (switch_to_fclk) {
9214 val |= LCPLL_CD_SOURCE_FCLK;
9215 I915_WRITE(LCPLL_CTL, val);
9216
9217 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9218 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9219 DRM_ERROR("Switching to FCLK failed\n");
9220
9221 val = I915_READ(LCPLL_CTL);
9222 }
9223
9224 val |= LCPLL_PLL_DISABLE;
9225 I915_WRITE(LCPLL_CTL, val);
9226 POSTING_READ(LCPLL_CTL);
9227
9228 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9229 DRM_ERROR("LCPLL still locked\n");
9230
9ccd5aeb 9231 val = hsw_read_dcomp(dev_priv);
be256dc7 9232 val |= D_COMP_COMP_DISABLE;
3c4c9b81 9233 hsw_write_dcomp(dev_priv, val);
be256dc7
PZ		 9234 ndelay(100);
9235
9ccd5aeb
PZ		 9236 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9237 1))
be256dc7
PZ		 9238 DRM_ERROR("D_COMP RCOMP still in progress\n");
9239
9240 if (allow_power_down) {
9241 val = I915_READ(LCPLL_CTL);
9242 val |= LCPLL_POWER_DOWN_ALLOW;
9243 I915_WRITE(LCPLL_CTL, val);
9244 POSTING_READ(LCPLL_CTL);
9245 }
9246}
9247
9248/*
9249 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9250 * source.
9251 */
6ff58d53 9252static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
be256dc7
PZ		 9253{
9254 uint32_t val;
9255
9256 val = I915_READ(LCPLL_CTL);
9257
9258 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9259 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9260 return;
9261
a8a8bd54
PZ		 9262 /*
9263 * Make sure we're not on PC8 state before disabling PC8, otherwise
9264 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
a8a8bd54 9265 */
59bad947 9266 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
215733fa 9267
be256dc7
PZ		 9268 if (val & LCPLL_POWER_DOWN_ALLOW) {
9269 val &= ~LCPLL_POWER_DOWN_ALLOW;
9270 I915_WRITE(LCPLL_CTL, val);
35d8f2eb 9271 POSTING_READ(LCPLL_CTL);
be256dc7
PZ		 9272 }
9273
9ccd5aeb 9274 val = hsw_read_dcomp(dev_priv);
be256dc7
PZ		 9275 val |= D_COMP_COMP_FORCE;
9276 val &= ~D_COMP_COMP_DISABLE;
3c4c9b81 9277 hsw_write_dcomp(dev_priv, val);
be256dc7
PZ		 9278
9279 val = I915_READ(LCPLL_CTL);
9280 val &= ~LCPLL_PLL_DISABLE;
9281 I915_WRITE(LCPLL_CTL, val);
9282
9283 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9284 DRM_ERROR("LCPLL not locked yet\n");
9285
9286 if (val & LCPLL_CD_SOURCE_FCLK) {
9287 val = I915_READ(LCPLL_CTL);
9288 val &= ~LCPLL_CD_SOURCE_FCLK;
9289 I915_WRITE(LCPLL_CTL, val);
9290
9291 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9292 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9293 DRM_ERROR("Switching back to LCPLL failed\n");
9294 }
215733fa 9295
59bad947 9296 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
be256dc7
PZ		 9297}
9298
765dab67
PZ		 9299/*
9300 * Package states C8 and deeper are really deep PC states that can only be
9301 * reached when all the devices on the system allow it, so even if the graphics
9302 * device allows PC8+, it doesn't mean the system will actually get to these
9303 * states. Our driver only allows PC8+ when going into runtime PM.
9304 *
9305 * The requirements for PC8+ are that all the outputs are disabled, the power
9306 * well is disabled and most interrupts are disabled, and these are also
9307 * requirements for runtime PM. When these conditions are met, we manually do
9308 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9309 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9310 * hang the machine.
9311 *
9312 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9313 * the state of some registers, so when we come back from PC8+ we need to
9314 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9315 * need to take care of the registers kept by RC6. Notice that this happens even
9316 * if we don't put the device in PCI D3 state (which is what currently happens
9317 * because of the runtime PM support).
9318 *
9319 * For more, read "Display Sequences for Package C8" on the hardware
9320 * documentation.
9321 */
a14cb6fc 9322void hsw_enable_pc8(struct drm_i915_private *dev_priv)
c67a470b 9323{
c67a470b
PZ		 9324 struct drm_device *dev = dev_priv->dev;
9325 uint32_t val;
9326
c67a470b
PZ		 9327 DRM_DEBUG_KMS("Enabling package C8+\n");
9328
c67a470b
PZ		 9329 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9330 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9331 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9332 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9333 }
9334
9335 lpt_disable_clkout_dp(dev);
c67a470b
PZ		 9336 hsw_disable_lcpll(dev_priv, true, true);
9337}
9338
a14cb6fc 9339void hsw_disable_pc8(struct drm_i915_private *dev_priv)
c67a470b
PZ		 9340{
9341 struct drm_device *dev = dev_priv->dev;
9342 uint32_t val;
9343
c67a470b
PZ		 9344 DRM_DEBUG_KMS("Disabling package C8+\n");
9345
9346 hsw_restore_lcpll(dev_priv);
c67a470b
PZ		 9347 lpt_init_pch_refclk(dev);
9348
9349 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9350 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9351 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9352 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9353 }
9354
9355 intel_prepare_ddi(dev);
c67a470b
PZ		 9356}
9357
a821fc46 9358static void broxton_modeset_global_resources(struct drm_atomic_state *old_state)
f8437dd1 9359{
a821fc46 9360 struct drm_device *dev = old_state->dev;
f8437dd1 9361 struct drm_i915_private *dev_priv = dev->dev_private;
a821fc46 9362 int max_pixclk = intel_mode_max_pixclk(dev, NULL);
f8437dd1
VK		 9363 int req_cdclk;
9364
9365 /* see the comment in valleyview_modeset_global_resources */
9366 if (WARN_ON(max_pixclk < 0))
9367 return;
9368
9369 req_cdclk = broxton_calc_cdclk(dev_priv, max_pixclk);
9370
9371 if (req_cdclk != dev_priv->cdclk_freq)
9372 broxton_set_cdclk(dev, req_cdclk);
9373}
9374
190f68c5
ACO		 9375static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9376 struct intel_crtc_state *crtc_state)
09b4ddf9 9377{
190f68c5 9378 if (!intel_ddi_pll_select(crtc, crtc_state))
6441ab5f 9379 return -EINVAL;
716c2e55 9380
c7653199 9381 crtc->lowfreq_avail = false;
644cef34 9382
c8f7a0db 9383 return 0;
79e53945
JB		 9384}
9385
3760b59c
S		 9386static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9387 enum port port,
9388 struct intel_crtc_state *pipe_config)
9389{
9390 switch (port) {
9391 case PORT_A:
9392 pipe_config->ddi_pll_sel = SKL_DPLL0;
9393 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9394 break;
9395 case PORT_B:
9396 pipe_config->ddi_pll_sel = SKL_DPLL1;
9397 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9398 break;
9399 case PORT_C:
9400 pipe_config->ddi_pll_sel = SKL_DPLL2;
9401 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9402 break;
9403 default:
9404 DRM_ERROR("Incorrect port type\n");
9405 }
9406}
9407
96b7dfb7
S		 9408static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9409 enum port port,
5cec258b 9410 struct intel_crtc_state *pipe_config)
96b7dfb7 9411{
3148ade7 9412 u32 temp, dpll_ctl1;
96b7dfb7
S		 9413
9414 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9415 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9416
9417 switch (pipe_config->ddi_pll_sel) {
3148ade7
DL		 9418 case SKL_DPLL0:
9419 /*
9420 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9421 * of the shared DPLL framework and thus needs to be read out
9422 * separately
9423 */
9424 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9425 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9426 break;
96b7dfb7
S		 9427 case SKL_DPLL1:
9428 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9429 break;
9430 case SKL_DPLL2:
9431 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9432 break;
9433 case SKL_DPLL3:
9434 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9435 break;
96b7dfb7
S		 9436 }
9437}
9438
7d2c8175
DL		 9439static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9440 enum port port,
5cec258b 9441 struct intel_crtc_state *pipe_config)
7d2c8175
DL		 9442{
9443 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9444
9445 switch (pipe_config->ddi_pll_sel) {
9446 case PORT_CLK_SEL_WRPLL1:
9447 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9448 break;
9449 case PORT_CLK_SEL_WRPLL2:
9450 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9451 break;
9452 }
9453}
9454
26804afd 9455static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
5cec258b 9456 struct intel_crtc_state *pipe_config)
26804afd
DV		 9457{
9458 struct drm_device *dev = crtc->base.dev;
9459 struct drm_i915_private *dev_priv = dev->dev_private;
d452c5b6 9460 struct intel_shared_dpll *pll;
26804afd
DV		 9461 enum port port;
9462 uint32_t tmp;
9463
9464 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9465
9466 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9467
96b7dfb7
S		 9468 if (IS_SKYLAKE(dev))
9469 skylake_get_ddi_pll(dev_priv, port, pipe_config);
3760b59c
S		 9470 else if (IS_BROXTON(dev))
9471 bxt_get_ddi_pll(dev_priv, port, pipe_config);
96b7dfb7
S		 9472 else
9473 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9cd86933 9474
d452c5b6
DV		 9475 if (pipe_config->shared_dpll >= 0) {
9476 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9477
9478 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9479 &pipe_config->dpll_hw_state));
9480 }
9481
26804afd
DV		 9482 /*
9483 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9484 * DDI E. So just check whether this pipe is wired to DDI E and whether
9485 * the PCH transcoder is on.
9486 */
ca370455
DL		 9487 if (INTEL_INFO(dev)->gen < 9 &&
9488 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
26804afd
DV		 9489 pipe_config->has_pch_encoder = true;
9490
9491 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9492 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9493 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9494
9495 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9496 }
9497}
9498
0e8ffe1b 9499static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5cec258b 9500 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 9501{
9502 struct drm_device *dev = crtc->base.dev;
9503 struct drm_i915_private *dev_priv = dev->dev_private;
2fa2fe9a 9504 enum intel_display_power_domain pfit_domain;
0e8ffe1b
DV		 9505 uint32_t tmp;
9506
f458ebbc 9507 if (!intel_display_power_is_enabled(dev_priv,
b5482bd0
ID		 9508 POWER_DOMAIN_PIPE(crtc->pipe)))
9509 return false;
9510
e143a21c 9511 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62
DV		 9512 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9513
eccb140b
DV		 9514 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9515 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9516 enum pipe trans_edp_pipe;
9517 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9518 default:
9519 WARN(1, "unknown pipe linked to edp transcoder\n");
9520 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9521 case TRANS_DDI_EDP_INPUT_A_ON:
9522 trans_edp_pipe = PIPE_A;
9523 break;
9524 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9525 trans_edp_pipe = PIPE_B;
9526 break;
9527 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9528 trans_edp_pipe = PIPE_C;
9529 break;
9530 }
9531
9532 if (trans_edp_pipe == crtc->pipe)
9533 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9534 }
9535
f458ebbc 9536 if (!intel_display_power_is_enabled(dev_priv,
eccb140b 9537 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
2bfce950
PZ		 9538 return false;
9539
eccb140b 9540 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
0e8ffe1b
DV		 9541 if (!(tmp & PIPECONF_ENABLE))
9542 return false;
9543
26804afd 9544 haswell_get_ddi_port_state(crtc, pipe_config);
627eb5a3 9545
1bd1bd80
DV		 9546 intel_get_pipe_timings(crtc, pipe_config);
9547
a1b2278e
CK		 9548 if (INTEL_INFO(dev)->gen >= 9) {
9549 skl_init_scalers(dev, crtc, pipe_config);
9550 }
9551
2fa2fe9a 9552 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
af99ceda
CK		 9553
9554 if (INTEL_INFO(dev)->gen >= 9) {
9555 pipe_config->scaler_state.scaler_id = -1;
9556 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9557 }
9558
bd2e244f 9559 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
ff6d9f55 9560 if (INTEL_INFO(dev)->gen == 9)
bd2e244f 9561 skylake_get_pfit_config(crtc, pipe_config);
ff6d9f55 9562 else if (INTEL_INFO(dev)->gen < 9)
bd2e244f 9563 ironlake_get_pfit_config(crtc, pipe_config);
ff6d9f55
JB		 9564 else
9565 MISSING_CASE(INTEL_INFO(dev)->gen);
bd2e244f 9566 }
88adfff1 9567
e59150dc
JB		 9568 if (IS_HASWELL(dev))
9569 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9570 (I915_READ(IPS_CTL) & IPS_ENABLE);
42db64ef 9571
ebb69c95
CT		 9572 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
9573 pipe_config->pixel_multiplier =
9574 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9575 } else {
9576 pipe_config->pixel_multiplier = 1;
9577 }
6c49f241 9578
0e8ffe1b
DV		 9579 return true;
9580}
9581
560b85bb
CW		 9582static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
9583{
9584 struct drm_device *dev = crtc->dev;
9585 struct drm_i915_private *dev_priv = dev->dev_private;
9586 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
dc41c154 9587 uint32_t cntl = 0, size = 0;
560b85bb 9588
dc41c154 9589 if (base) {
3dd512fb
MR		 9590 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
9591 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
dc41c154
VS		 9592 unsigned int stride = roundup_pow_of_two(width) * 4;
9593
9594 switch (stride) {
9595 default:
9596 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9597 width, stride);
9598 stride = 256;
9599 /* fallthrough */
9600 case 256:
9601 case 512:
9602 case 1024:
9603 case 2048:
9604 break;
4b0e333e
CW		 9605 }
9606
dc41c154
VS		 9607 cntl |= CURSOR_ENABLE |
9608 CURSOR_GAMMA_ENABLE |
9609 CURSOR_FORMAT_ARGB |
9610 CURSOR_STRIDE(stride);
9611
9612 size = (height << 12) | width;
4b0e333e 9613 }
560b85bb 9614
dc41c154
VS		 9615 if (intel_crtc->cursor_cntl != 0 &&
9616 (intel_crtc->cursor_base != base ||
9617 intel_crtc->cursor_size != size ||
9618 intel_crtc->cursor_cntl != cntl)) {
9619 /* On these chipsets we can only modify the base/size/stride
9620 * whilst the cursor is disabled.
9621 */
9622 I915_WRITE(_CURACNTR, 0);
4b0e333e 9623 POSTING_READ(_CURACNTR);
dc41c154 9624 intel_crtc->cursor_cntl = 0;
4b0e333e 9625 }
560b85bb 9626
99d1f387 9627 if (intel_crtc->cursor_base != base) {
9db4a9c7 9628 I915_WRITE(_CURABASE, base);
99d1f387
VS		 9629 intel_crtc->cursor_base = base;
9630 }
4726e0b0 9631
dc41c154
VS		 9632 if (intel_crtc->cursor_size != size) {
9633 I915_WRITE(CURSIZE, size);
9634 intel_crtc->cursor_size = size;
4b0e333e 9635 }
560b85bb 9636
4b0e333e 9637 if (intel_crtc->cursor_cntl != cntl) {
4b0e333e
CW		 9638 I915_WRITE(_CURACNTR, cntl);
9639 POSTING_READ(_CURACNTR);
4b0e333e 9640 intel_crtc->cursor_cntl = cntl;
560b85bb 9641 }
560b85bb
CW		 9642}
9643
560b85bb 9644static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
65a21cd6
JB		 9645{
9646 struct drm_device *dev = crtc->dev;
9647 struct drm_i915_private *dev_priv = dev->dev_private;
9648 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9649 int pipe = intel_crtc->pipe;
4b0e333e
CW		 9650 uint32_t cntl;
9651
9652 cntl = 0;
9653 if (base) {
9654 cntl = MCURSOR_GAMMA_ENABLE;
3dd512fb 9655 switch (intel_crtc->base.cursor->state->crtc_w) {
4726e0b0
SK		 9656 case 64:
9657 cntl |= CURSOR_MODE_64_ARGB_AX;
9658 break;
9659 case 128:
9660 cntl |= CURSOR_MODE_128_ARGB_AX;
9661 break;
9662 case 256:
9663 cntl |= CURSOR_MODE_256_ARGB_AX;
9664 break;
9665 default:
3dd512fb 9666 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
4726e0b0 9667 return;
65a21cd6 9668 }
4b0e333e 9669 cntl |= pipe << 28; /* Connect to correct pipe */
47bf17a7
VS		 9670
9671 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
9672 cntl |= CURSOR_PIPE_CSC_ENABLE;
4b0e333e 9673 }
65a21cd6 9674
8e7d688b 9675 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
4398ad45
VS		 9676 cntl |= CURSOR_ROTATE_180;
9677
4b0e333e
CW		 9678 if (intel_crtc->cursor_cntl != cntl) {
9679 I915_WRITE(CURCNTR(pipe), cntl);
9680 POSTING_READ(CURCNTR(pipe));
9681 intel_crtc->cursor_cntl = cntl;
65a21cd6 9682 }
4b0e333e 9683
65a21cd6 9684 /* and commit changes on next vblank */
5efb3e28
VS		 9685 I915_WRITE(CURBASE(pipe), base);
9686 POSTING_READ(CURBASE(pipe));
99d1f387
VS		 9687
9688 intel_crtc->cursor_base = base;
65a21cd6
JB		 9689}
9690
cda4b7d3 9691/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 9692static void intel_crtc_update_cursor(struct drm_crtc *crtc,
9693 bool on)
cda4b7d3
CW		 9694{
9695 struct drm_device *dev = crtc->dev;
9696 struct drm_i915_private *dev_priv = dev->dev_private;
9697 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9698 int pipe = intel_crtc->pipe;
3d7d6510
MR		 9699 int x = crtc->cursor_x;
9700 int y = crtc->cursor_y;
d6e4db15 9701 u32 base = 0, pos = 0;
cda4b7d3 9702
d6e4db15 9703 if (on)
cda4b7d3 9704 base = intel_crtc->cursor_addr;
cda4b7d3 9705
6e3c9717 9706 if (x >= intel_crtc->config->pipe_src_w)
d6e4db15
VS		 9707 base = 0;
9708
6e3c9717 9709 if (y >= intel_crtc->config->pipe_src_h)
cda4b7d3
CW		 9710 base = 0;
9711
9712 if (x < 0) {
3dd512fb 9713 if (x + intel_crtc->base.cursor->state->crtc_w <= 0)
cda4b7d3
CW		 9714 base = 0;
9715
9716 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9717 x = -x;
9718 }
9719 pos |= x << CURSOR_X_SHIFT;
9720
9721 if (y < 0) {
3dd512fb 9722 if (y + intel_crtc->base.cursor->state->crtc_h <= 0)
cda4b7d3
CW		 9723 base = 0;
9724
9725 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
9726 y = -y;
9727 }
9728 pos |= y << CURSOR_Y_SHIFT;
9729
4b0e333e 9730 if (base == 0 && intel_crtc->cursor_base == 0)
cda4b7d3
CW		 9731 return;
9732
5efb3e28
VS		 9733 I915_WRITE(CURPOS(pipe), pos);
9734
4398ad45
VS		 9735 /* ILK+ do this automagically */
9736 if (HAS_GMCH_DISPLAY(dev) &&
8e7d688b 9737 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
3dd512fb
MR		 9738 base += (intel_crtc->base.cursor->state->crtc_h *
9739 intel_crtc->base.cursor->state->crtc_w - 1) * 4;
4398ad45
VS		 9740 }
9741
8ac54669 9742 if (IS_845G(dev) || IS_I865G(dev))
5efb3e28
VS		 9743 i845_update_cursor(crtc, base);
9744 else
9745 i9xx_update_cursor(crtc, base);
cda4b7d3
CW		 9746}
9747
dc41c154
VS		 9748static bool cursor_size_ok(struct drm_device *dev,
9749 uint32_t width, uint32_t height)
9750{
9751 if (width == 0 || height == 0)
9752 return false;
9753
9754 /*
9755 * 845g/865g are special in that they are only limited by
9756 * the width of their cursors, the height is arbitrary up to
9757 * the precision of the register. Everything else requires
9758 * square cursors, limited to a few power-of-two sizes.
9759 */
9760 if (IS_845G(dev) || IS_I865G(dev)) {
9761 if ((width & 63) != 0)
9762 return false;
9763
9764 if (width > (IS_845G(dev) ? 64 : 512))
9765 return false;
9766
9767 if (height > 1023)
9768 return false;
9769 } else {
9770 switch (width | height) {
9771 case 256:
9772 case 128:
9773 if (IS_GEN2(dev))
9774 return false;
9775 case 64:
9776 break;
9777 default:
9778 return false;
9779 }
9780 }
9781
9782 return true;
9783}
9784
79e53945 9785static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 9786 u16 *blue, uint32_t start, uint32_t size)
79e53945 9787{
7203425a 9788 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 9789 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 9790
7203425a 9791 for (i = start; i < end; i++) {
79e53945
JB		 9792 intel_crtc->lut_r[i] = red[i] >> 8;
9793 intel_crtc->lut_g[i] = green[i] >> 8;
9794 intel_crtc->lut_b[i] = blue[i] >> 8;
9795 }
9796
9797 intel_crtc_load_lut(crtc);
9798}
9799
79e53945
JB		 9800/* VESA 640x480x72Hz mode to set on the pipe */
9801static struct drm_display_mode load_detect_mode = {
9802 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
9803 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
9804};
9805
a8bb6818
DV		 9806struct drm_framebuffer *
9807__intel_framebuffer_create(struct drm_device *dev,
9808 struct drm_mode_fb_cmd2 *mode_cmd,
9809 struct drm_i915_gem_object *obj)
d2dff872
CW		 9810{
9811 struct intel_framebuffer *intel_fb;
9812 int ret;
9813
9814 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9815 if (!intel_fb) {
6ccb81f2 9816 drm_gem_object_unreference(&obj->base);
d2dff872
CW		 9817 return ERR_PTR(-ENOMEM);
9818 }
9819
9820 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
dd4916c5
DV		 9821 if (ret)
9822 goto err;
d2dff872
CW		 9823
9824 return &intel_fb->base;
dd4916c5 9825err:
6ccb81f2 9826 drm_gem_object_unreference(&obj->base);
dd4916c5
DV		 9827 kfree(intel_fb);
9828
9829 return ERR_PTR(ret);
d2dff872
CW		 9830}
9831
b5ea642a 9832static struct drm_framebuffer *
a8bb6818
DV		 9833intel_framebuffer_create(struct drm_device *dev,
9834 struct drm_mode_fb_cmd2 *mode_cmd,
9835 struct drm_i915_gem_object *obj)
9836{
9837 struct drm_framebuffer *fb;
9838 int ret;
9839
9840 ret = i915_mutex_lock_interruptible(dev);
9841 if (ret)
9842 return ERR_PTR(ret);
9843 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
9844 mutex_unlock(&dev->struct_mutex);
9845
9846 return fb;
9847}
9848
d2dff872
CW		 9849static u32
9850intel_framebuffer_pitch_for_width(int width, int bpp)
9851{
9852 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
9853 return ALIGN(pitch, 64);
9854}
9855
9856static u32
9857intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
9858{
9859 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
1267a26b 9860 return PAGE_ALIGN(pitch * mode->vdisplay);
d2dff872
CW		 9861}
9862
9863static struct drm_framebuffer *
9864intel_framebuffer_create_for_mode(struct drm_device *dev,
9865 struct drm_display_mode *mode,
9866 int depth, int bpp)
9867{
9868 struct drm_i915_gem_object *obj;
0fed39bd 9869 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 9870
9871 obj = i915_gem_alloc_object(dev,
9872 intel_framebuffer_size_for_mode(mode, bpp));
9873 if (obj == NULL)
9874 return ERR_PTR(-ENOMEM);
9875
9876 mode_cmd.width = mode->hdisplay;
9877 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 9878 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
9879 bpp);
5ca0c34a 9880 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 9881
9882 return intel_framebuffer_create(dev, &mode_cmd, obj);
9883}
9884
9885static struct drm_framebuffer *
9886mode_fits_in_fbdev(struct drm_device *dev,
9887 struct drm_display_mode *mode)
9888{
4520f53a 9889#ifdef CONFIG_DRM_I915_FBDEV
d2dff872
CW		 9890 struct drm_i915_private *dev_priv = dev->dev_private;
9891 struct drm_i915_gem_object *obj;
9892 struct drm_framebuffer *fb;
9893
4c0e5528 9894 if (!dev_priv->fbdev)
d2dff872
CW		 9895 return NULL;
9896
4c0e5528 9897 if (!dev_priv->fbdev->fb)
d2dff872
CW		 9898 return NULL;
9899
4c0e5528
DV		 9900 obj = dev_priv->fbdev->fb->obj;
9901 BUG_ON(!obj);
9902
8bcd4553 9903 fb = &dev_priv->fbdev->fb->base;
01f2c773
VS		 9904 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
9905 fb->bits_per_pixel))
d2dff872
CW		 9906 return NULL;
9907
01f2c773 9908 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 9909 return NULL;
9910
9911 return fb;
4520f53a
DV		 9912#else
9913 return NULL;
9914#endif
d2dff872
CW		 9915}
9916
d3a40d1b
ACO		 9917static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
9918 struct drm_crtc *crtc,
9919 struct drm_display_mode *mode,
9920 struct drm_framebuffer *fb,
9921 int x, int y)
9922{
9923 struct drm_plane_state *plane_state;
9924 int hdisplay, vdisplay;
9925 int ret;
9926
9927 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
9928 if (IS_ERR(plane_state))
9929 return PTR_ERR(plane_state);
9930
9931 if (mode)
9932 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
9933 else
9934 hdisplay = vdisplay = 0;
9935
9936 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
9937 if (ret)
9938 return ret;
9939 drm_atomic_set_fb_for_plane(plane_state, fb);
9940 plane_state->crtc_x = 0;
9941 plane_state->crtc_y = 0;
9942 plane_state->crtc_w = hdisplay;
9943 plane_state->crtc_h = vdisplay;
9944 plane_state->src_x = x << 16;
9945 plane_state->src_y = y << 16;
9946 plane_state->src_w = hdisplay << 16;
9947 plane_state->src_h = vdisplay << 16;
9948
9949 return 0;
9950}
9951
d2434ab7 9952bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 9953 struct drm_display_mode *mode,
51fd371b
RC		 9954 struct intel_load_detect_pipe *old,
9955 struct drm_modeset_acquire_ctx *ctx)
79e53945
JB		 9956{
9957 struct intel_crtc *intel_crtc;
d2434ab7
DV		 9958 struct intel_encoder *intel_encoder =
9959 intel_attached_encoder(connector);
79e53945 9960 struct drm_crtc *possible_crtc;
4ef69c7a 9961 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 9962 struct drm_crtc *crtc = NULL;
9963 struct drm_device *dev = encoder->dev;
94352cf9 9964 struct drm_framebuffer *fb;
51fd371b 9965 struct drm_mode_config *config = &dev->mode_config;
83a57153 9966 struct drm_atomic_state *state = NULL;
944b0c76 9967 struct drm_connector_state *connector_state;
4be07317 9968 struct intel_crtc_state *crtc_state;
51fd371b 9969 int ret, i = -1;
79e53945 9970
d2dff872 9971 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
c23cc417 9972 connector->base.id, connector->name,
8e329a03 9973 encoder->base.id, encoder->name);
d2dff872 9974
51fd371b
RC		 9975retry:
9976 ret = drm_modeset_lock(&config->connection_mutex, ctx);
9977 if (ret)
9978 goto fail_unlock;
6e9f798d 9979
79e53945
JB		 9980 /*
9981 * Algorithm gets a little messy:
7a5e4805 9982 *
79e53945
JB		 9983 * - if the connector already has an assigned crtc, use it (but make
9984 * sure it's on first)
7a5e4805 9985 *
79e53945
JB		 9986 * - try to find the first unused crtc that can drive this connector,
9987 * and use that if we find one
79e53945
JB		 9988 */
9989
9990 /* See if we already have a CRTC for this connector */
9991 if (encoder->crtc) {
9992 crtc = encoder->crtc;
8261b191 9993
51fd371b 9994 ret = drm_modeset_lock(&crtc->mutex, ctx);
4d02e2de
DV		 9995 if (ret)
9996 goto fail_unlock;
9997 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
51fd371b
RC		 9998 if (ret)
9999 goto fail_unlock;
7b24056b 10000
24218aac 10001 old->dpms_mode = connector->dpms;
8261b191
CW		 10002 old->load_detect_temp = false;
10003
10004 /* Make sure the crtc and connector are running */
24218aac
DV		 10005 if (connector->dpms != DRM_MODE_DPMS_ON)
10006 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 10007
7173188d 10008 return true;
79e53945
JB		 10009 }
10010
10011 /* Find an unused one (if possible) */
70e1e0ec 10012 for_each_crtc(dev, possible_crtc) {
79e53945
JB		 10013 i++;
10014 if (!(encoder->possible_crtcs & (1 << i)))
10015 continue;
83d65738 10016 if (possible_crtc->state->enable)
a459249c
VS		 10017 continue;
10018 /* This can occur when applying the pipe A quirk on resume. */
10019 if (to_intel_crtc(possible_crtc)->new_enabled)
10020 continue;
10021
10022 crtc = possible_crtc;
10023 break;
79e53945
JB		 10024 }
10025
10026 /*
10027 * If we didn't find an unused CRTC, don't use any.
10028 */
10029 if (!crtc) {
7173188d 10030 DRM_DEBUG_KMS("no pipe available for load-detect\n");
51fd371b 10031 goto fail_unlock;
79e53945
JB		 10032 }
10033
51fd371b
RC		 10034 ret = drm_modeset_lock(&crtc->mutex, ctx);
10035 if (ret)
4d02e2de
DV		 10036 goto fail_unlock;
10037 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10038 if (ret)
51fd371b 10039 goto fail_unlock;
fc303101
DV		 10040 intel_encoder->new_crtc = to_intel_crtc(crtc);
10041 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 10042
10043 intel_crtc = to_intel_crtc(crtc);
412b61d8 10044 intel_crtc->new_enabled = true;
24218aac 10045 old->dpms_mode = connector->dpms;
8261b191 10046 old->load_detect_temp = true;
d2dff872 10047 old->release_fb = NULL;
79e53945 10048
83a57153
ACO		 10049 state = drm_atomic_state_alloc(dev);
10050 if (!state)
10051 return false;
10052
10053 state->acquire_ctx = ctx;
10054
944b0c76
ACO		 10055 connector_state = drm_atomic_get_connector_state(state, connector);
10056 if (IS_ERR(connector_state)) {
10057 ret = PTR_ERR(connector_state);
10058 goto fail;
10059 }
10060
10061 connector_state->crtc = crtc;
10062 connector_state->best_encoder = &intel_encoder->base;
10063
4be07317
ACO		 10064 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10065 if (IS_ERR(crtc_state)) {
10066 ret = PTR_ERR(crtc_state);
10067 goto fail;
10068 }
10069
49d6fa21 10070 crtc_state->base.active = crtc_state->base.enable = true;
4be07317 10071
6492711d
CW		 10072 if (!mode)
10073 mode = &load_detect_mode;
79e53945 10074
d2dff872
CW		 10075 /* We need a framebuffer large enough to accommodate all accesses
10076 * that the plane may generate whilst we perform load detection.
10077 * We can not rely on the fbcon either being present (we get called
10078 * during its initialisation to detect all boot displays, or it may
10079 * not even exist) or that it is large enough to satisfy the
10080 * requested mode.
10081 */
94352cf9
DV		 10082 fb = mode_fits_in_fbdev(dev, mode);
10083 if (fb == NULL) {
d2dff872 10084 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 10085 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10086 old->release_fb = fb;
d2dff872
CW		 10087 } else
10088 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 10089 if (IS_ERR(fb)) {
d2dff872 10090 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
412b61d8 10091 goto fail;
79e53945 10092 }
79e53945 10093
d3a40d1b
ACO		 10094 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10095 if (ret)
10096 goto fail;
10097
8c7b5ccb
ACO		 10098 drm_mode_copy(&crtc_state->base.mode, mode);
10099
10100 if (intel_set_mode(crtc, state)) {
6492711d 10101 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 10102 if (old->release_fb)
10103 old->release_fb->funcs->destroy(old->release_fb);
412b61d8 10104 goto fail;
79e53945 10105 }
9128b040 10106 crtc->primary->crtc = crtc;
7173188d 10107
79e53945 10108 /* let the connector get through one full cycle before testing */
9d0498a2 10109 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 10110 return true;
412b61d8
VS		 10111
10112 fail:
83d65738 10113 intel_crtc->new_enabled = crtc->state->enable;
51fd371b 10114fail_unlock:
e5d958ef
ACO		 10115 drm_atomic_state_free(state);
10116 state = NULL;
83a57153 10117
51fd371b
RC		 10118 if (ret == -EDEADLK) {
10119 drm_modeset_backoff(ctx);
10120 goto retry;
10121 }
10122
412b61d8 10123 return false;
79e53945
JB		 10124}
10125
d2434ab7 10126void intel_release_load_detect_pipe(struct drm_connector *connector,
49172fee
ACO		 10127 struct intel_load_detect_pipe *old,
10128 struct drm_modeset_acquire_ctx *ctx)
79e53945 10129{
83a57153 10130 struct drm_device *dev = connector->dev;
d2434ab7
DV		 10131 struct intel_encoder *intel_encoder =
10132 intel_attached_encoder(connector);
4ef69c7a 10133 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 10134 struct drm_crtc *crtc = encoder->crtc;
412b61d8 10135 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83a57153 10136 struct drm_atomic_state *state;
944b0c76 10137 struct drm_connector_state *connector_state;
4be07317 10138 struct intel_crtc_state *crtc_state;
d3a40d1b 10139 int ret;
79e53945 10140
d2dff872 10141 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
c23cc417 10142 connector->base.id, connector->name,
8e329a03 10143 encoder->base.id, encoder->name);
d2dff872 10144
8261b191 10145 if (old->load_detect_temp) {
83a57153 10146 state = drm_atomic_state_alloc(dev);
944b0c76
ACO		 10147 if (!state)
10148 goto fail;
83a57153
ACO		 10149
10150 state->acquire_ctx = ctx;
10151
944b0c76
ACO		 10152 connector_state = drm_atomic_get_connector_state(state, connector);
10153 if (IS_ERR(connector_state))
10154 goto fail;
10155
4be07317
ACO		 10156 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10157 if (IS_ERR(crtc_state))
10158 goto fail;
10159
fc303101
DV		 10160 to_intel_connector(connector)->new_encoder = NULL;
10161 intel_encoder->new_crtc = NULL;
412b61d8 10162 intel_crtc->new_enabled = false;
944b0c76
ACO		 10163
10164 connector_state->best_encoder = NULL;
10165 connector_state->crtc = NULL;
10166
49d6fa21 10167 crtc_state->base.enable = crtc_state->base.active = false;
4be07317 10168
d3a40d1b
ACO		 10169 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
10170 0, 0);
10171 if (ret)
10172 goto fail;
10173
2bfb4627
ACO		 10174 ret = intel_set_mode(crtc, state);
10175 if (ret)
10176 goto fail;
d2dff872 10177
36206361
DV		 10178 if (old->release_fb) {
10179 drm_framebuffer_unregister_private(old->release_fb);
10180 drm_framebuffer_unreference(old->release_fb);
10181 }
d2dff872 10182
0622a53c 10183 return;
79e53945
JB		 10184 }
10185
c751ce4f 10186 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 10187 if (old->dpms_mode != DRM_MODE_DPMS_ON)
10188 connector->funcs->dpms(connector, old->dpms_mode);
944b0c76
ACO		 10189
10190 return;
10191fail:
10192 DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
10193 drm_atomic_state_free(state);
79e53945
JB		 10194}
10195
da4a1efa 10196static int i9xx_pll_refclk(struct drm_device *dev,
5cec258b 10197 const struct intel_crtc_state *pipe_config)
da4a1efa
VS		 10198{
10199 struct drm_i915_private *dev_priv = dev->dev_private;
10200 u32 dpll = pipe_config->dpll_hw_state.dpll;
10201
10202 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
e91e941b 10203 return dev_priv->vbt.lvds_ssc_freq;
da4a1efa
VS		 10204 else if (HAS_PCH_SPLIT(dev))
10205 return 120000;
10206 else if (!IS_GEN2(dev))
10207 return 96000;
10208 else
10209 return 48000;
10210}
10211
79e53945 10212/* Returns the clock of the currently programmed mode of the given pipe. */
f1f644dc 10213static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 10214 struct intel_crtc_state *pipe_config)
79e53945 10215{
f1f644dc 10216 struct drm_device *dev = crtc->base.dev;
79e53945 10217 struct drm_i915_private *dev_priv = dev->dev_private;
f1f644dc 10218 int pipe = pipe_config->cpu_transcoder;
293623f7 10219 u32 dpll = pipe_config->dpll_hw_state.dpll;
79e53945
JB		 10220 u32 fp;
10221 intel_clock_t clock;
da4a1efa 10222 int refclk = i9xx_pll_refclk(dev, pipe_config);
79e53945
JB		 10223
10224 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
293623f7 10225 fp = pipe_config->dpll_hw_state.fp0;
79e53945 10226 else
293623f7 10227 fp = pipe_config->dpll_hw_state.fp1;
79e53945
JB		 10228
10229 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 10230 if (IS_PINEVIEW(dev)) {
10231 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10232 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 10233 } else {
10234 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10235 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10236 }
10237
a6c45cf0 10238 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 10239 if (IS_PINEVIEW(dev))
10240 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10241 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 10242 else
10243 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 10244 DPLL_FPA01_P1_POST_DIV_SHIFT);
10245
10246 switch (dpll & DPLL_MODE_MASK) {
10247 case DPLLB_MODE_DAC_SERIAL:
10248 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10249 5 : 10;
10250 break;
10251 case DPLLB_MODE_LVDS:
10252 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10253 7 : 14;
10254 break;
10255 default:
28c97730 10256 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945 10257 "mode\n", (int)(dpll & DPLL_MODE_MASK));
f1f644dc 10258 return;
79e53945
JB		 10259 }
10260
ac58c3f0 10261 if (IS_PINEVIEW(dev))
da4a1efa 10262 pineview_clock(refclk, &clock);
ac58c3f0 10263 else
da4a1efa 10264 i9xx_clock(refclk, &clock);
79e53945 10265 } else {
0fb58223 10266 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
b1c560d1 10267 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
79e53945
JB		 10268
10269 if (is_lvds) {
10270 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10271 DPLL_FPA01_P1_POST_DIV_SHIFT);
b1c560d1
VS		 10272
10273 if (lvds & LVDS_CLKB_POWER_UP)
10274 clock.p2 = 7;
10275 else
10276 clock.p2 = 14;
79e53945
JB		 10277 } else {
10278 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10279 clock.p1 = 2;
10280 else {
10281 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10282 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10283 }
10284 if (dpll & PLL_P2_DIVIDE_BY_4)
10285 clock.p2 = 4;
10286 else
10287 clock.p2 = 2;
79e53945 10288 }
da4a1efa
VS		 10289
10290 i9xx_clock(refclk, &clock);
79e53945
JB		 10291 }
10292
18442d08
VS		 10293 /*
10294 * This value includes pixel_multiplier. We will use
241bfc38 10295 * port_clock to compute adjusted_mode.crtc_clock in the
18442d08
VS		 10296 * encoder's get_config() function.
10297 */
10298 pipe_config->port_clock = clock.dot;
f1f644dc
JB		 10299}
10300
6878da05
VS		 10301int intel_dotclock_calculate(int link_freq,
10302 const struct intel_link_m_n *m_n)
f1f644dc 10303{
f1f644dc
JB		 10304 /*
10305 * The calculation for the data clock is:
1041a02f 10306 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
f1f644dc 10307 * But we want to avoid losing precison if possible, so:
1041a02f 10308 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
f1f644dc
JB		 10309 *
10310 * and the link clock is simpler:
1041a02f 10311 * link_clock = (m * link_clock) / n
f1f644dc
JB		 10312 */
10313
6878da05
VS		 10314 if (!m_n->link_n)
10315 return 0;
f1f644dc 10316
6878da05
VS		 10317 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10318}
f1f644dc 10319
18442d08 10320static void ironlake_pch_clock_get(struct intel_crtc *crtc,
5cec258b 10321 struct intel_crtc_state *pipe_config)
6878da05
VS		 10322{
10323 struct drm_device *dev = crtc->base.dev;
79e53945 10324
18442d08
VS		 10325 /* read out port_clock from the DPLL */
10326 i9xx_crtc_clock_get(crtc, pipe_config);
f1f644dc 10327
f1f644dc 10328 /*
18442d08 10329 * This value does not include pixel_multiplier.
241bfc38 10330 * We will check that port_clock and adjusted_mode.crtc_clock
18442d08
VS		 10331 * agree once we know their relationship in the encoder's
10332 * get_config() function.
79e53945 10333 */
2d112de7 10334 pipe_config->base.adjusted_mode.crtc_clock =
18442d08
VS		 10335 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10336 &pipe_config->fdi_m_n);
79e53945
JB		 10337}
10338
10339/** Returns the currently programmed mode of the given pipe. */
10340struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10341 struct drm_crtc *crtc)
10342{
548f245b 10343 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 10344 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 10345 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
79e53945 10346 struct drm_display_mode *mode;
5cec258b 10347 struct intel_crtc_state pipe_config;
fe2b8f9d
PZ		 10348 int htot = I915_READ(HTOTAL(cpu_transcoder));
10349 int hsync = I915_READ(HSYNC(cpu_transcoder));
10350 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10351 int vsync = I915_READ(VSYNC(cpu_transcoder));
293623f7 10352 enum pipe pipe = intel_crtc->pipe;
79e53945
JB		 10353
10354 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10355 if (!mode)
10356 return NULL;
10357
f1f644dc
JB		 10358 /*
10359 * Construct a pipe_config sufficient for getting the clock info
10360 * back out of crtc_clock_get.
10361 *
10362 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10363 * to use a real value here instead.
10364 */
293623f7 10365 pipe_config.cpu_transcoder = (enum transcoder) pipe;
f1f644dc 10366 pipe_config.pixel_multiplier = 1;
293623f7
VS		 10367 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10368 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10369 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
f1f644dc
JB		 10370 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10371
773ae034 10372 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
79e53945
JB		 10373 mode->hdisplay = (htot & 0xffff) + 1;
10374 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10375 mode->hsync_start = (hsync & 0xffff) + 1;
10376 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10377 mode->vdisplay = (vtot & 0xffff) + 1;
10378 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10379 mode->vsync_start = (vsync & 0xffff) + 1;
10380 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10381
10382 drm_mode_set_name(mode);
79e53945
JB		 10383
10384 return mode;
10385}
10386
652c393a
JB		 10387static void intel_decrease_pllclock(struct drm_crtc *crtc)
10388{
10389 struct drm_device *dev = crtc->dev;
fbee40df 10390 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 10391 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 10392
baff296c 10393 if (!HAS_GMCH_DISPLAY(dev))
652c393a
JB		 10394 return;
10395
10396 if (!dev_priv->lvds_downclock_avail)
10397 return;
10398
10399 /*
10400 * Since this is called by a timer, we should never get here in
10401 * the manual case.
10402 */
10403 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 10404 int pipe = intel_crtc->pipe;
10405 int dpll_reg = DPLL(pipe);
10406 int dpll;
f6e5b160 10407
44d98a61 10408 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 10409
8ac5a6d5 10410 assert_panel_unlocked(dev_priv, pipe);
652c393a 10411
dc257cf1 10412 dpll = I915_READ(dpll_reg);
652c393a
JB		 10413 dpll |= DISPLAY_RATE_SELECT_FPA1;
10414 I915_WRITE(dpll_reg, dpll);
9d0498a2 10415 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 10416 dpll = I915_READ(dpll_reg);
10417 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 10418 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 10419 }
10420
10421}
10422
f047e395
CW		 10423void intel_mark_busy(struct drm_device *dev)
10424{
c67a470b
PZ		 10425 struct drm_i915_private *dev_priv = dev->dev_private;
10426
f62a0076
CW		 10427 if (dev_priv->mm.busy)
10428 return;
10429
43694d69 10430 intel_runtime_pm_get(dev_priv);
c67a470b 10431 i915_update_gfx_val(dev_priv);
43cf3bf0
CW		 10432 if (INTEL_INFO(dev)->gen >= 6)
10433 gen6_rps_busy(dev_priv);
f62a0076 10434 dev_priv->mm.busy = true;
f047e395
CW		 10435}
10436
10437void intel_mark_idle(struct drm_device *dev)
652c393a 10438{
c67a470b 10439 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 10440 struct drm_crtc *crtc;
652c393a 10441
f62a0076
CW		 10442 if (!dev_priv->mm.busy)
10443 return;
10444
10445 dev_priv->mm.busy = false;
10446
70e1e0ec 10447 for_each_crtc(dev, crtc) {
f4510a27 10448 if (!crtc->primary->fb)
652c393a
JB		 10449 continue;
10450
725a5b54 10451 intel_decrease_pllclock(crtc);
652c393a 10452 }
b29c19b6 10453
3d13ef2e 10454 if (INTEL_INFO(dev)->gen >= 6)
b29c19b6 10455 gen6_rps_idle(dev->dev_private);
bb4cdd53 10456
43694d69 10457 intel_runtime_pm_put(dev_priv);
652c393a
JB		 10458}
10459
79e53945
JB		 10460static void intel_crtc_destroy(struct drm_crtc *crtc)
10461{
10462 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 10463 struct drm_device *dev = crtc->dev;
10464 struct intel_unpin_work *work;
67e77c5a 10465
5e2d7afc 10466 spin_lock_irq(&dev->event_lock);
67e77c5a
DV		 10467 work = intel_crtc->unpin_work;
10468 intel_crtc->unpin_work = NULL;
5e2d7afc 10469 spin_unlock_irq(&dev->event_lock);
67e77c5a
DV		 10470
10471 if (work) {
10472 cancel_work_sync(&work->work);
10473 kfree(work);
10474 }
79e53945
JB		 10475
10476 drm_crtc_cleanup(crtc);
67e77c5a 10477
79e53945
JB		 10478 kfree(intel_crtc);
10479}
10480
6b95a207
KH		 10481static void intel_unpin_work_fn(struct work_struct *__work)
10482{
10483 struct intel_unpin_work *work =
10484 container_of(__work, struct intel_unpin_work, work);
b4a98e57 10485 struct drm_device *dev = work->crtc->dev;
f99d7069 10486 enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
6b95a207 10487
b4a98e57 10488 mutex_lock(&dev->struct_mutex);
82bc3b2d 10489 intel_unpin_fb_obj(work->old_fb, work->crtc->primary->state);
05394f39 10490 drm_gem_object_unreference(&work->pending_flip_obj->base);
d9e86c0e 10491
7ff0ebcc 10492 intel_fbc_update(dev);
f06cc1b9
JH		 10493
10494 if (work->flip_queued_req)
146d84f0 10495 i915_gem_request_assign(&work->flip_queued_req, NULL);
b4a98e57
CW		 10496 mutex_unlock(&dev->struct_mutex);
10497
f99d7069 10498 intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
89ed88ba 10499 drm_framebuffer_unreference(work->old_fb);
f99d7069 10500
b4a98e57
CW		 10501 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
10502 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
10503
6b95a207
KH		 10504 kfree(work);
10505}
10506
1afe3e9d 10507static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 10508 struct drm_crtc *crtc)
6b95a207 10509{
6b95a207
KH		 10510 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10511 struct intel_unpin_work *work;
6b95a207
KH		 10512 unsigned long flags;
10513
10514 /* Ignore early vblank irqs */
10515 if (intel_crtc == NULL)
10516 return;
10517
f326038a
DV		 10518 /*
10519 * This is called both by irq handlers and the reset code (to complete
10520 * lost pageflips) so needs the full irqsave spinlocks.
10521 */
6b95a207
KH		 10522 spin_lock_irqsave(&dev->event_lock, flags);
10523 work = intel_crtc->unpin_work;
e7d841ca
CW		 10524
10525 /* Ensure we don't miss a work->pending update ... */
10526 smp_rmb();
10527
10528 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 10529 spin_unlock_irqrestore(&dev->event_lock, flags);
10530 return;
10531 }
10532
d6bbafa1 10533 page_flip_completed(intel_crtc);
0af7e4df 10534
6b95a207 10535 spin_unlock_irqrestore(&dev->event_lock, flags);
6b95a207
KH		 10536}
10537
1afe3e9d
JB		 10538void intel_finish_page_flip(struct drm_device *dev, int pipe)
10539{
fbee40df 10540 struct drm_i915_private *dev_priv = dev->dev_private;
1afe3e9d
JB		 10541 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10542
49b14a5c 10543 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 10544}
10545
10546void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10547{
fbee40df 10548 struct drm_i915_private *dev_priv = dev->dev_private;
1afe3e9d
JB		 10549 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10550
49b14a5c 10551 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 10552}
10553
75f7f3ec
VS		 10554/* Is 'a' after or equal to 'b'? */
10555static bool g4x_flip_count_after_eq(u32 a, u32 b)
10556{
10557 return !((a - b) & 0x80000000);
10558}
10559
10560static bool page_flip_finished(struct intel_crtc *crtc)
10561{
10562 struct drm_device *dev = crtc->base.dev;
10563 struct drm_i915_private *dev_priv = dev->dev_private;
10564
bdfa7542
VS		 10565 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10566 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10567 return true;
10568
75f7f3ec
VS		 10569 /*
10570 * The relevant registers doen't exist on pre-ctg.
10571 * As the flip done interrupt doesn't trigger for mmio
10572 * flips on gmch platforms, a flip count check isn't
10573 * really needed there. But since ctg has the registers,
10574 * include it in the check anyway.
10575 */
10576 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10577 return true;
10578
10579 /*
10580 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10581 * used the same base address. In that case the mmio flip might
10582 * have completed, but the CS hasn't even executed the flip yet.
10583 *
10584 * A flip count check isn't enough as the CS might have updated
10585 * the base address just after start of vblank, but before we
10586 * managed to process the interrupt. This means we'd complete the
10587 * CS flip too soon.
10588 *
10589 * Combining both checks should get us a good enough result. It may
10590 * still happen that the CS flip has been executed, but has not
10591 * yet actually completed. But in case the base address is the same
10592 * anyway, we don't really care.
10593 */
10594 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10595 crtc->unpin_work->gtt_offset &&
10596 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
10597 crtc->unpin_work->flip_count);
10598}
10599
6b95a207
KH		 10600void intel_prepare_page_flip(struct drm_device *dev, int plane)
10601{
fbee40df 10602 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 10603 struct intel_crtc *intel_crtc =
10604 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10605 unsigned long flags;
10606
f326038a
DV		 10607
10608 /*
10609 * This is called both by irq handlers and the reset code (to complete
10610 * lost pageflips) so needs the full irqsave spinlocks.
10611 *
10612 * NB: An MMIO update of the plane base pointer will also
e7d841ca
CW		 10613 * generate a page-flip completion irq, i.e. every modeset
10614 * is also accompanied by a spurious intel_prepare_page_flip().
10615 */
6b95a207 10616 spin_lock_irqsave(&dev->event_lock, flags);
75f7f3ec 10617 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
e7d841ca 10618 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 10619 spin_unlock_irqrestore(&dev->event_lock, flags);
10620}
10621
eba905b2 10622static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
e7d841ca
CW		 10623{
10624 /* Ensure that the work item is consistent when activating it ... */
10625 smp_wmb();
10626 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
10627 /* and that it is marked active as soon as the irq could fire. */
10628 smp_wmb();
10629}
10630
8c9f3aaf
JB		 10631static int intel_gen2_queue_flip(struct drm_device *dev,
10632 struct drm_crtc *crtc,
10633 struct drm_framebuffer *fb,
ed8d1975 10634 struct drm_i915_gem_object *obj,
a4872ba6 10635 struct intel_engine_cs *ring,
ed8d1975 10636 uint32_t flags)
8c9f3aaf 10637{
8c9f3aaf 10638 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf
JB		 10639 u32 flip_mask;
10640 int ret;
10641
6d90c952 10642 ret = intel_ring_begin(ring, 6);
8c9f3aaf 10643 if (ret)
4fa62c89 10644 return ret;
8c9f3aaf
JB		 10645
10646 /* Can't queue multiple flips, so wait for the previous
10647 * one to finish before executing the next.
10648 */
10649 if (intel_crtc->plane)
10650 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10651 else
10652 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 10653 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10654 intel_ring_emit(ring, MI_NOOP);
10655 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10656 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10657 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 10658 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
6d90c952 10659 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 10660
10661 intel_mark_page_flip_active(intel_crtc);
09246732 10662 __intel_ring_advance(ring);
83d4092b 10663 return 0;
8c9f3aaf
JB		 10664}
10665
10666static int intel_gen3_queue_flip(struct drm_device *dev,
10667 struct drm_crtc *crtc,
10668 struct drm_framebuffer *fb,
ed8d1975 10669 struct drm_i915_gem_object *obj,
a4872ba6 10670 struct intel_engine_cs *ring,
ed8d1975 10671 uint32_t flags)
8c9f3aaf 10672{
8c9f3aaf 10673 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf
JB		 10674 u32 flip_mask;
10675 int ret;
10676
6d90c952 10677 ret = intel_ring_begin(ring, 6);
8c9f3aaf 10678 if (ret)
4fa62c89 10679 return ret;
8c9f3aaf
JB		 10680
10681 if (intel_crtc->plane)
10682 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10683 else
10684 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 10685 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10686 intel_ring_emit(ring, MI_NOOP);
10687 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
10688 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10689 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 10690 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
6d90c952
DV		 10691 intel_ring_emit(ring, MI_NOOP);
10692
e7d841ca 10693 intel_mark_page_flip_active(intel_crtc);
09246732 10694 __intel_ring_advance(ring);
83d4092b 10695 return 0;
8c9f3aaf
JB		 10696}
10697
10698static int intel_gen4_queue_flip(struct drm_device *dev,
10699 struct drm_crtc *crtc,
10700 struct drm_framebuffer *fb,
ed8d1975 10701 struct drm_i915_gem_object *obj,
a4872ba6 10702 struct intel_engine_cs *ring,
ed8d1975 10703 uint32_t flags)
8c9f3aaf
JB		 10704{
10705 struct drm_i915_private *dev_priv = dev->dev_private;
10706 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10707 uint32_t pf, pipesrc;
10708 int ret;
10709
6d90c952 10710 ret = intel_ring_begin(ring, 4);
8c9f3aaf 10711 if (ret)
4fa62c89 10712 return ret;
8c9f3aaf
JB		 10713
10714 /* i965+ uses the linear or tiled offsets from the
10715 * Display Registers (which do not change across a page-flip)
10716 * so we need only reprogram the base address.
10717 */
6d90c952
DV		 10718 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10719 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10720 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 10721 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
c2c75131 10722 obj->tiling_mode);
8c9f3aaf
JB		 10723
10724 /* XXX Enabling the panel-fitter across page-flip is so far
10725 * untested on non-native modes, so ignore it for now.
10726 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
10727 */
10728 pf = 0;
10729 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 10730 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 10731
10732 intel_mark_page_flip_active(intel_crtc);
09246732 10733 __intel_ring_advance(ring);
83d4092b 10734 return 0;
8c9f3aaf
JB		 10735}
10736
10737static int intel_gen6_queue_flip(struct drm_device *dev,
10738 struct drm_crtc *crtc,
10739 struct drm_framebuffer *fb,
ed8d1975 10740 struct drm_i915_gem_object *obj,
a4872ba6 10741 struct intel_engine_cs *ring,
ed8d1975 10742 uint32_t flags)
8c9f3aaf
JB		 10743{
10744 struct drm_i915_private *dev_priv = dev->dev_private;
10745 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10746 uint32_t pf, pipesrc;
10747 int ret;
10748
6d90c952 10749 ret = intel_ring_begin(ring, 4);
8c9f3aaf 10750 if (ret)
4fa62c89 10751 return ret;
8c9f3aaf 10752
6d90c952
DV		 10753 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10754 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10755 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
75f7f3ec 10756 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
8c9f3aaf 10757
dc257cf1
DV		 10758 /* Contrary to the suggestions in the documentation,
10759 * "Enable Panel Fitter" does not seem to be required when page
10760 * flipping with a non-native mode, and worse causes a normal
10761 * modeset to fail.
10762 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
10763 */
10764 pf = 0;
8c9f3aaf 10765 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 10766 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 10767
10768 intel_mark_page_flip_active(intel_crtc);
09246732 10769 __intel_ring_advance(ring);
83d4092b 10770 return 0;
8c9f3aaf
JB		 10771}
10772
7c9017e5
JB		 10773static int intel_gen7_queue_flip(struct drm_device *dev,
10774 struct drm_crtc *crtc,
10775 struct drm_framebuffer *fb,
ed8d1975 10776 struct drm_i915_gem_object *obj,
a4872ba6 10777 struct intel_engine_cs *ring,
ed8d1975 10778 uint32_t flags)
7c9017e5 10779{
7c9017e5 10780 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cb05d8de 10781 uint32_t plane_bit = 0;
ffe74d75
CW		 10782 int len, ret;
10783
eba905b2 10784 switch (intel_crtc->plane) {
cb05d8de
DV		 10785 case PLANE_A:
10786 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
10787 break;
10788 case PLANE_B:
10789 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
10790 break;
10791 case PLANE_C:
10792 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
10793 break;
10794 default:
10795 WARN_ONCE(1, "unknown plane in flip command\n");
4fa62c89 10796 return -ENODEV;
cb05d8de
DV		 10797 }
10798
ffe74d75 10799 len = 4;
f476828a 10800 if (ring->id == RCS) {
ffe74d75 10801 len += 6;
f476828a
DL		 10802 /*
10803 * On Gen 8, SRM is now taking an extra dword to accommodate
10804 * 48bits addresses, and we need a NOOP for the batch size to
10805 * stay even.
10806 */
10807 if (IS_GEN8(dev))
10808 len += 2;
10809 }
ffe74d75 10810
f66fab8e
VS		 10811 /*
10812 * BSpec MI_DISPLAY_FLIP for IVB:
10813 * "The full packet must be contained within the same cache line."
10814 *
10815 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
10816 * cacheline, if we ever start emitting more commands before
10817 * the MI_DISPLAY_FLIP we may need to first emit everything else,
10818 * then do the cacheline alignment, and finally emit the
10819 * MI_DISPLAY_FLIP.
10820 */
10821 ret = intel_ring_cacheline_align(ring);
10822 if (ret)
4fa62c89 10823 return ret;
f66fab8e 10824
ffe74d75 10825 ret = intel_ring_begin(ring, len);
7c9017e5 10826 if (ret)
4fa62c89 10827 return ret;
7c9017e5 10828
ffe74d75
CW		 10829 /* Unmask the flip-done completion message. Note that the bspec says that
10830 * we should do this for both the BCS and RCS, and that we must not unmask
10831 * more than one flip event at any time (or ensure that one flip message
10832 * can be sent by waiting for flip-done prior to queueing new flips).
10833 * Experimentation says that BCS works despite DERRMR masking all
10834 * flip-done completion events and that unmasking all planes at once
10835 * for the RCS also doesn't appear to drop events. Setting the DERRMR
10836 * to zero does lead to lockups within MI_DISPLAY_FLIP.
10837 */
10838 if (ring->id == RCS) {
10839 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
10840 intel_ring_emit(ring, DERRMR);
10841 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
10842 DERRMR_PIPEB_PRI_FLIP_DONE |
10843 DERRMR_PIPEC_PRI_FLIP_DONE));
f476828a
DL		 10844 if (IS_GEN8(dev))
10845 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
10846 MI_SRM_LRM_GLOBAL_GTT);
10847 else
10848 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
10849 MI_SRM_LRM_GLOBAL_GTT);
ffe74d75
CW		 10850 intel_ring_emit(ring, DERRMR);
10851 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
f476828a
DL		 10852 if (IS_GEN8(dev)) {
10853 intel_ring_emit(ring, 0);
10854 intel_ring_emit(ring, MI_NOOP);
10855 }
ffe74d75
CW		 10856 }
10857
cb05d8de 10858 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 10859 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
75f7f3ec 10860 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
7c9017e5 10861 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 10862
10863 intel_mark_page_flip_active(intel_crtc);
09246732 10864 __intel_ring_advance(ring);
83d4092b 10865 return 0;
7c9017e5
JB		 10866}
10867
84c33a64
SG		 10868static bool use_mmio_flip(struct intel_engine_cs *ring,
10869 struct drm_i915_gem_object *obj)
10870{
10871 /*
10872 * This is not being used for older platforms, because
10873 * non-availability of flip done interrupt forces us to use
10874 * CS flips. Older platforms derive flip done using some clever
10875 * tricks involving the flip_pending status bits and vblank irqs.
10876 * So using MMIO flips there would disrupt this mechanism.
10877 */
10878
8e09bf83
CW		 10879 if (ring == NULL)
10880 return true;
10881
84c33a64
SG		 10882 if (INTEL_INFO(ring->dev)->gen < 5)
10883 return false;
10884
10885 if (i915.use_mmio_flip < 0)
10886 return false;
10887 else if (i915.use_mmio_flip > 0)
10888 return true;
14bf993e
OM		 10889 else if (i915.enable_execlists)
10890 return true;
84c33a64 10891 else
b4716185 10892 return ring != i915_gem_request_get_ring(obj->last_write_req);
84c33a64
SG		 10893}
10894
ff944564
DL		 10895static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
10896{
10897 struct drm_device *dev = intel_crtc->base.dev;
10898 struct drm_i915_private *dev_priv = dev->dev_private;
10899 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
ff944564
DL		 10900 const enum pipe pipe = intel_crtc->pipe;
10901 u32 ctl, stride;
10902
10903 ctl = I915_READ(PLANE_CTL(pipe, 0));
10904 ctl &= ~PLANE_CTL_TILED_MASK;
2ebef630
TU		 10905 switch (fb->modifier[0]) {
10906 case DRM_FORMAT_MOD_NONE:
10907 break;
10908 case I915_FORMAT_MOD_X_TILED:
ff944564 10909 ctl |= PLANE_CTL_TILED_X;
2ebef630
TU		 10910 break;
10911 case I915_FORMAT_MOD_Y_TILED:
10912 ctl |= PLANE_CTL_TILED_Y;
10913 break;
10914 case I915_FORMAT_MOD_Yf_TILED:
10915 ctl |= PLANE_CTL_TILED_YF;
10916 break;
10917 default:
10918 MISSING_CASE(fb->modifier[0]);
10919 }
ff944564
DL		 10920
10921 /*
10922 * The stride is either expressed as a multiple of 64 bytes chunks for
10923 * linear buffers or in number of tiles for tiled buffers.
10924 */
2ebef630
TU		 10925 stride = fb->pitches[0] /
10926 intel_fb_stride_alignment(dev, fb->modifier[0],
10927 fb->pixel_format);
ff944564
DL		 10928
10929 /*
10930 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
10931 * PLANE_SURF updates, the update is then guaranteed to be atomic.
10932 */
10933 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
10934 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
10935
10936 I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
10937 POSTING_READ(PLANE_SURF(pipe, 0));
10938}
10939
10940static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
84c33a64
SG		 10941{
10942 struct drm_device *dev = intel_crtc->base.dev;
10943 struct drm_i915_private *dev_priv = dev->dev_private;
10944 struct intel_framebuffer *intel_fb =
10945 to_intel_framebuffer(intel_crtc->base.primary->fb);
10946 struct drm_i915_gem_object *obj = intel_fb->obj;
10947 u32 dspcntr;
10948 u32 reg;
10949
84c33a64
SG		 10950 reg = DSPCNTR(intel_crtc->plane);
10951 dspcntr = I915_READ(reg);
10952
c5d97472
DL		 10953 if (obj->tiling_mode != I915_TILING_NONE)
10954 dspcntr |= DISPPLANE_TILED;
10955 else
10956 dspcntr &= ~DISPPLANE_TILED;
10957
84c33a64
SG		 10958 I915_WRITE(reg, dspcntr);
10959
10960 I915_WRITE(DSPSURF(intel_crtc->plane),
10961 intel_crtc->unpin_work->gtt_offset);
10962 POSTING_READ(DSPSURF(intel_crtc->plane));
84c33a64 10963
ff944564
DL		 10964}
10965
10966/*
10967 * XXX: This is the temporary way to update the plane registers until we get
10968 * around to using the usual plane update functions for MMIO flips
10969 */
10970static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
10971{
10972 struct drm_device *dev = intel_crtc->base.dev;
10973 bool atomic_update;
10974 u32 start_vbl_count;
10975
10976 intel_mark_page_flip_active(intel_crtc);
10977
10978 atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
10979
10980 if (INTEL_INFO(dev)->gen >= 9)
10981 skl_do_mmio_flip(intel_crtc);
10982 else
10983 /* use_mmio_flip() retricts MMIO flips to ilk+ */
10984 ilk_do_mmio_flip(intel_crtc);
10985
9362c7c5
ACO		 10986 if (atomic_update)
10987 intel_pipe_update_end(intel_crtc, start_vbl_count);
84c33a64
SG		 10988}
10989
9362c7c5 10990static void intel_mmio_flip_work_func(struct work_struct *work)
84c33a64 10991{
b2cfe0ab
CW		 10992 struct intel_mmio_flip *mmio_flip =
10993 container_of(work, struct intel_mmio_flip, work);
84c33a64 10994
eed29a5b
DV		 10995 if (mmio_flip->req)
10996 WARN_ON(__i915_wait_request(mmio_flip->req,
b2cfe0ab 10997 mmio_flip->crtc->reset_counter,
bcafc4e3
CW		 10998 false, NULL,
10999 &mmio_flip->i915->rps.mmioflips));
84c33a64 11000
b2cfe0ab
CW		 11001 intel_do_mmio_flip(mmio_flip->crtc);
11002
eed29a5b 11003 i915_gem_request_unreference__unlocked(mmio_flip->req);
b2cfe0ab 11004 kfree(mmio_flip);
84c33a64
SG		 11005}
11006
11007static int intel_queue_mmio_flip(struct drm_device *dev,
11008 struct drm_crtc *crtc,
11009 struct drm_framebuffer *fb,
11010 struct drm_i915_gem_object *obj,
11011 struct intel_engine_cs *ring,
11012 uint32_t flags)
11013{
b2cfe0ab
CW		 11014 struct intel_mmio_flip *mmio_flip;
11015
11016 mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11017 if (mmio_flip == NULL)
11018 return -ENOMEM;
84c33a64 11019
bcafc4e3 11020 mmio_flip->i915 = to_i915(dev);
eed29a5b 11021 mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
b2cfe0ab 11022 mmio_flip->crtc = to_intel_crtc(crtc);
536f5b5e 11023
b2cfe0ab
CW		 11024 INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11025 schedule_work(&mmio_flip->work);
84c33a64 11026
84c33a64
SG		 11027 return 0;
11028}
11029
8c9f3aaf
JB		 11030static int intel_default_queue_flip(struct drm_device *dev,
11031 struct drm_crtc *crtc,
11032 struct drm_framebuffer *fb,
ed8d1975 11033 struct drm_i915_gem_object *obj,
a4872ba6 11034 struct intel_engine_cs *ring,
ed8d1975 11035 uint32_t flags)
8c9f3aaf
JB		 11036{
11037 return -ENODEV;
11038}
11039
d6bbafa1
CW		 11040static bool __intel_pageflip_stall_check(struct drm_device *dev,
11041 struct drm_crtc *crtc)
11042{
11043 struct drm_i915_private *dev_priv = dev->dev_private;
11044 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11045 struct intel_unpin_work *work = intel_crtc->unpin_work;
11046 u32 addr;
11047
11048 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11049 return true;
11050
11051 if (!work->enable_stall_check)
11052 return false;
11053
11054 if (work->flip_ready_vblank == 0) {
3a8a946e
DV		 11055 if (work->flip_queued_req &&
11056 !i915_gem_request_completed(work->flip_queued_req, true))
d6bbafa1
CW		 11057 return false;
11058
1e3feefd 11059 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
d6bbafa1
CW		 11060 }
11061
1e3feefd 11062 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
d6bbafa1
CW		 11063 return false;
11064
11065 /* Potential stall - if we see that the flip has happened,
11066 * assume a missed interrupt. */
11067 if (INTEL_INFO(dev)->gen >= 4)
11068 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11069 else
11070 addr = I915_READ(DSPADDR(intel_crtc->plane));
11071
11072 /* There is a potential issue here with a false positive after a flip
11073 * to the same address. We could address this by checking for a
11074 * non-incrementing frame counter.
11075 */
11076 return addr == work->gtt_offset;
11077}
11078
11079void intel_check_page_flip(struct drm_device *dev, int pipe)
11080{
11081 struct drm_i915_private *dev_priv = dev->dev_private;
11082 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11083 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6ad790c0 11084 struct intel_unpin_work *work;
f326038a 11085
6c51d46f 11086 WARN_ON(!in_interrupt());
d6bbafa1
CW		 11087
11088 if (crtc == NULL)
11089 return;
11090
f326038a 11091 spin_lock(&dev->event_lock);
6ad790c0
CW		 11092 work = intel_crtc->unpin_work;
11093 if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
d6bbafa1 11094 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
6ad790c0 11095 work->flip_queued_vblank, drm_vblank_count(dev, pipe));
d6bbafa1 11096 page_flip_completed(intel_crtc);
6ad790c0 11097 work = NULL;
d6bbafa1 11098 }
6ad790c0
CW		 11099 if (work != NULL &&
11100 drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11101 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
f326038a 11102 spin_unlock(&dev->event_lock);
d6bbafa1
CW		 11103}
11104
6b95a207
KH		 11105static int intel_crtc_page_flip(struct drm_crtc *crtc,
11106 struct drm_framebuffer *fb,
ed8d1975
KP		 11107 struct drm_pending_vblank_event *event,
11108 uint32_t page_flip_flags)
6b95a207
KH		 11109{
11110 struct drm_device *dev = crtc->dev;
11111 struct drm_i915_private *dev_priv = dev->dev_private;
f4510a27 11112 struct drm_framebuffer *old_fb = crtc->primary->fb;
2ff8fde1 11113 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
6b95a207 11114 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
455a6808 11115 struct drm_plane *primary = crtc->primary;
a071fa00 11116 enum pipe pipe = intel_crtc->pipe;
6b95a207 11117 struct intel_unpin_work *work;
a4872ba6 11118 struct intel_engine_cs *ring;
cf5d8a46 11119 bool mmio_flip;
52e68630 11120 int ret;
6b95a207 11121
2ff8fde1
MR		 11122 /*
11123 * drm_mode_page_flip_ioctl() should already catch this, but double
11124 * check to be safe. In the future we may enable pageflipping from
11125 * a disabled primary plane.
11126 */
11127 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11128 return -EBUSY;
11129
e6a595d2 11130 /* Can't change pixel format via MI display flips. */
f4510a27 11131 if (fb->pixel_format != crtc->primary->fb->pixel_format)
e6a595d2
VS		 11132 return -EINVAL;
11133
11134 /*
11135 * TILEOFF/LINOFF registers can't be changed via MI display flips.
11136 * Note that pitch changes could also affect these register.
11137 */
11138 if (INTEL_INFO(dev)->gen > 3 &&
f4510a27
MR		 11139 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11140 fb->pitches[0] != crtc->primary->fb->pitches[0]))
e6a595d2
VS		 11141 return -EINVAL;
11142
f900db47
CW		 11143 if (i915_terminally_wedged(&dev_priv->gpu_error))
11144 goto out_hang;
11145
b14c5679 11146 work = kzalloc(sizeof(*work), GFP_KERNEL);
6b95a207
KH		 11147 if (work == NULL)
11148 return -ENOMEM;
11149
6b95a207 11150 work->event = event;
b4a98e57 11151 work->crtc = crtc;
ab8d6675 11152 work->old_fb = old_fb;
6b95a207
KH		 11153 INIT_WORK(&work->work, intel_unpin_work_fn);
11154
87b6b101 11155 ret = drm_crtc_vblank_get(crtc);
7317c75e
JB		 11156 if (ret)
11157 goto free_work;
11158
6b95a207 11159 /* We borrow the event spin lock for protecting unpin_work */
5e2d7afc 11160 spin_lock_irq(&dev->event_lock);
6b95a207 11161 if (intel_crtc->unpin_work) {
d6bbafa1
CW		 11162 /* Before declaring the flip queue wedged, check if
11163 * the hardware completed the operation behind our backs.
11164 */
11165 if (__intel_pageflip_stall_check(dev, crtc)) {
11166 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11167 page_flip_completed(intel_crtc);
11168 } else {
11169 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
5e2d7afc 11170 spin_unlock_irq(&dev->event_lock);
468f0b44 11171
d6bbafa1
CW		 11172 drm_crtc_vblank_put(crtc);
11173 kfree(work);
11174 return -EBUSY;
11175 }
6b95a207
KH		 11176 }
11177 intel_crtc->unpin_work = work;
5e2d7afc 11178 spin_unlock_irq(&dev->event_lock);
6b95a207 11179
b4a98e57
CW		 11180 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11181 flush_workqueue(dev_priv->wq);
11182
75dfca80 11183 /* Reference the objects for the scheduled work. */
ab8d6675 11184 drm_framebuffer_reference(work->old_fb);
05394f39 11185 drm_gem_object_reference(&obj->base);
6b95a207 11186
f4510a27 11187 crtc->primary->fb = fb;
afd65eb4 11188 update_state_fb(crtc->primary);
1ed1f968 11189
e1f99ce6 11190 work->pending_flip_obj = obj;
e1f99ce6 11191
89ed88ba
CW		 11192 ret = i915_mutex_lock_interruptible(dev);
11193 if (ret)
11194 goto cleanup;
11195
b4a98e57 11196 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 11197 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 11198
75f7f3ec 11199 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
a071fa00 11200 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
75f7f3ec 11201
4fa62c89
VS		 11202 if (IS_VALLEYVIEW(dev)) {
11203 ring = &dev_priv->ring[BCS];
ab8d6675 11204 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
8e09bf83
CW		 11205 /* vlv: DISPLAY_FLIP fails to change tiling */
11206 ring = NULL;
48bf5b2d 11207 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
2a92d5bc 11208 ring = &dev_priv->ring[BCS];
4fa62c89 11209 } else if (INTEL_INFO(dev)->gen >= 7) {
b4716185 11210 ring = i915_gem_request_get_ring(obj->last_write_req);
4fa62c89
VS		 11211 if (ring == NULL || ring->id != RCS)
11212 ring = &dev_priv->ring[BCS];
11213 } else {
11214 ring = &dev_priv->ring[RCS];
11215 }
11216
cf5d8a46
CW		 11217 mmio_flip = use_mmio_flip(ring, obj);
11218
11219 /* When using CS flips, we want to emit semaphores between rings.
11220 * However, when using mmio flips we will create a task to do the
11221 * synchronisation, so all we want here is to pin the framebuffer
11222 * into the display plane and skip any waits.
11223 */
82bc3b2d 11224 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
cf5d8a46 11225 crtc->primary->state,
b4716185 11226 mmio_flip ? i915_gem_request_get_ring(obj->last_write_req) : ring);
8c9f3aaf
JB		 11227 if (ret)
11228 goto cleanup_pending;
6b95a207 11229
121920fa
TU		 11230 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj)
11231 + intel_crtc->dspaddr_offset;
4fa62c89 11232
cf5d8a46 11233 if (mmio_flip) {
84c33a64
SG		 11234 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
11235 page_flip_flags);
d6bbafa1
CW		 11236 if (ret)
11237 goto cleanup_unpin;
11238
f06cc1b9
JH		 11239 i915_gem_request_assign(&work->flip_queued_req,
11240 obj->last_write_req);
d6bbafa1 11241 } else {
d94b5030
CW		 11242 if (obj->last_write_req) {
11243 ret = i915_gem_check_olr(obj->last_write_req);
11244 if (ret)
11245 goto cleanup_unpin;
11246 }
11247
84c33a64 11248 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
d6bbafa1
CW		 11249 page_flip_flags);
11250 if (ret)
11251 goto cleanup_unpin;
11252
f06cc1b9
JH		 11253 i915_gem_request_assign(&work->flip_queued_req,
11254 intel_ring_get_request(ring));
d6bbafa1
CW		 11255 }
11256
1e3feefd 11257 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
d6bbafa1 11258 work->enable_stall_check = true;
4fa62c89 11259
ab8d6675 11260 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
a071fa00
DV		 11261 INTEL_FRONTBUFFER_PRIMARY(pipe));
11262
7ff0ebcc 11263 intel_fbc_disable(dev);
f99d7069 11264 intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
6b95a207
KH		 11265 mutex_unlock(&dev->struct_mutex);
11266
e5510fac
JB		 11267 trace_i915_flip_request(intel_crtc->plane, obj);
11268
6b95a207 11269 return 0;
96b099fd 11270
4fa62c89 11271cleanup_unpin:
82bc3b2d 11272 intel_unpin_fb_obj(fb, crtc->primary->state);
8c9f3aaf 11273cleanup_pending:
b4a98e57 11274 atomic_dec(&intel_crtc->unpin_work_count);
89ed88ba
CW		 11275 mutex_unlock(&dev->struct_mutex);
11276cleanup:
f4510a27 11277 crtc->primary->fb = old_fb;
afd65eb4 11278 update_state_fb(crtc->primary);
89ed88ba
CW		 11279
11280 drm_gem_object_unreference_unlocked(&obj->base);
ab8d6675 11281 drm_framebuffer_unreference(work->old_fb);
96b099fd 11282
5e2d7afc 11283 spin_lock_irq(&dev->event_lock);
96b099fd 11284 intel_crtc->unpin_work = NULL;
5e2d7afc 11285 spin_unlock_irq(&dev->event_lock);
96b099fd 11286
87b6b101 11287 drm_crtc_vblank_put(crtc);
7317c75e 11288free_work:
96b099fd
CW		 11289 kfree(work);
11290
f900db47
CW		 11291 if (ret == -EIO) {
11292out_hang:
53a366b9 11293 ret = intel_plane_restore(primary);
f0d3dad3 11294 if (ret == 0 && event) {
5e2d7afc 11295 spin_lock_irq(&dev->event_lock);
a071fa00 11296 drm_send_vblank_event(dev, pipe, event);
5e2d7afc 11297 spin_unlock_irq(&dev->event_lock);
f0d3dad3 11298 }
f900db47 11299 }
96b099fd 11300 return ret;
6b95a207
KH		 11301}
11302
65b38e0d 11303static const struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 11304 .mode_set_base_atomic = intel_pipe_set_base_atomic,
11305 .load_lut = intel_crtc_load_lut,
ea2c67bb
MR		 11306 .atomic_begin = intel_begin_crtc_commit,
11307 .atomic_flush = intel_finish_crtc_commit,
f6e5b160
CW		 11308};
11309
9a935856
DV		 11310/**
11311 * intel_modeset_update_staged_output_state
11312 *
11313 * Updates the staged output configuration state, e.g. after we've read out the
11314 * current hw state.
11315 */
11316static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 11317{
7668851f 11318 struct intel_crtc *crtc;
9a935856
DV		 11319 struct intel_encoder *encoder;
11320 struct intel_connector *connector;
f6e5b160 11321
3a3371ff 11322 for_each_intel_connector(dev, connector) {
9a935856
DV		 11323 connector->new_encoder =
11324 to_intel_encoder(connector->base.encoder);
11325 }
f6e5b160 11326
b2784e15 11327 for_each_intel_encoder(dev, encoder) {
9a935856
DV		 11328 encoder->new_crtc =
11329 to_intel_crtc(encoder->base.crtc);
11330 }
7668851f 11331
d3fcc808 11332 for_each_intel_crtc(dev, crtc) {
83d65738 11333 crtc->new_enabled = crtc->base.state->enable;
7668851f 11334 }
f6e5b160
CW		 11335}
11336
d29b2f9d
ACO		 11337/* Transitional helper to copy current connector/encoder state to
11338 * connector->state. This is needed so that code that is partially
11339 * converted to atomic does the right thing.
11340 */
11341static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11342{
11343 struct intel_connector *connector;
11344
11345 for_each_intel_connector(dev, connector) {
11346 if (connector->base.encoder) {
11347 connector->base.state->best_encoder =
11348 connector->base.encoder;
11349 connector->base.state->crtc =
11350 connector->base.encoder->crtc;
11351 } else {
11352 connector->base.state->best_encoder = NULL;
11353 connector->base.state->crtc = NULL;
11354 }
11355 }
11356}
11357
a821fc46 11358/* Fixup legacy state after an atomic state swap.
9a935856 11359 */
a821fc46 11360static void intel_modeset_fixup_state(struct drm_atomic_state *state)
9a935856 11361{
a821fc46 11362 struct intel_crtc *crtc;
9a935856 11363 struct intel_encoder *encoder;
a821fc46 11364 struct intel_connector *connector;
d5432a9d 11365
a821fc46
ACO		 11366 for_each_intel_connector(state->dev, connector) {
11367 connector->base.encoder = connector->base.state->best_encoder;
11368 if (connector->base.encoder)
11369 connector->base.encoder->crtc =
11370 connector->base.state->crtc;
9a935856 11371 }
f6e5b160 11372
d5432a9d
ACO		 11373 /* Update crtc of disabled encoders */
11374 for_each_intel_encoder(state->dev, encoder) {
11375 int num_connectors = 0;
11376
a821fc46
ACO		 11377 for_each_intel_connector(state->dev, connector)
11378 if (connector->base.encoder == &encoder->base)
d5432a9d
ACO		 11379 num_connectors++;
11380
11381 if (num_connectors == 0)
11382 encoder->base.crtc = NULL;
9a935856 11383 }
7668851f 11384
a821fc46
ACO		 11385 for_each_intel_crtc(state->dev, crtc) {
11386 crtc->base.enabled = crtc->base.state->enable;
11387 crtc->config = to_intel_crtc_state(crtc->base.state);
7668851f 11388 }
d29b2f9d 11389
d5432a9d
ACO		 11390 /* Copy the new configuration to the staged state, to keep the few
11391 * pieces of code that haven't been converted yet happy */
11392 intel_modeset_update_staged_output_state(state->dev);
9a935856
DV		 11393}
11394
050f7aeb 11395static void
eba905b2 11396connected_sink_compute_bpp(struct intel_connector *connector,
5cec258b 11397 struct intel_crtc_state *pipe_config)
050f7aeb
DV		 11398{
11399 int bpp = pipe_config->pipe_bpp;
11400
11401 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11402 connector->base.base.id,
c23cc417 11403 connector->base.name);
050f7aeb
DV		 11404
11405 /* Don't use an invalid EDID bpc value */
11406 if (connector->base.display_info.bpc &&
11407 connector->base.display_info.bpc * 3 < bpp) {
11408 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11409 bpp, connector->base.display_info.bpc*3);
11410 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11411 }
11412
11413 /* Clamp bpp to 8 on screens without EDID 1.4 */
11414 if (connector->base.display_info.bpc == 0 && bpp > 24) {
11415 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11416 bpp);
11417 pipe_config->pipe_bpp = 24;
11418 }
11419}
11420
4e53c2e0 11421static int
050f7aeb 11422compute_baseline_pipe_bpp(struct intel_crtc *crtc,
5cec258b 11423 struct intel_crtc_state *pipe_config)
4e53c2e0 11424{
050f7aeb 11425 struct drm_device *dev = crtc->base.dev;
1486017f 11426 struct drm_atomic_state *state;
da3ced29
ACO		 11427 struct drm_connector *connector;
11428 struct drm_connector_state *connector_state;
1486017f 11429 int bpp, i;
4e53c2e0 11430
d328c9d7 11431 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
4e53c2e0 11432 bpp = 10*3;
d328c9d7
DV		 11433 else if (INTEL_INFO(dev)->gen >= 5)
11434 bpp = 12*3;
11435 else
11436 bpp = 8*3;
11437
4e53c2e0 11438
4e53c2e0
DV		 11439 pipe_config->pipe_bpp = bpp;
11440
1486017f
ACO		 11441 state = pipe_config->base.state;
11442
4e53c2e0 11443 /* Clamp display bpp to EDID value */
da3ced29
ACO		 11444 for_each_connector_in_state(state, connector, connector_state, i) {
11445 if (connector_state->crtc != &crtc->base)
4e53c2e0
DV		 11446 continue;
11447
da3ced29
ACO		 11448 connected_sink_compute_bpp(to_intel_connector(connector),
11449 pipe_config);
4e53c2e0
DV		 11450 }
11451
11452 return bpp;
11453}
11454
644db711
DV		 11455static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11456{
11457 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11458 "type: 0x%x flags: 0x%x\n",
1342830c 11459 mode->crtc_clock,
644db711
DV		 11460 mode->crtc_hdisplay, mode->crtc_hsync_start,
11461 mode->crtc_hsync_end, mode->crtc_htotal,
11462 mode->crtc_vdisplay, mode->crtc_vsync_start,
11463 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11464}
11465
c0b03411 11466static void intel_dump_pipe_config(struct intel_crtc *crtc,
5cec258b 11467 struct intel_crtc_state *pipe_config,
c0b03411
DV		 11468 const char *context)
11469{
6a60cd87
CK		 11470 struct drm_device *dev = crtc->base.dev;
11471 struct drm_plane *plane;
11472 struct intel_plane *intel_plane;
11473 struct intel_plane_state *state;
11474 struct drm_framebuffer *fb;
11475
11476 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
11477 context, pipe_config, pipe_name(crtc->pipe));
c0b03411
DV		 11478
11479 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
11480 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
11481 pipe_config->pipe_bpp, pipe_config->dither);
11482 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11483 pipe_config->has_pch_encoder,
11484 pipe_config->fdi_lanes,
11485 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
11486 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
11487 pipe_config->fdi_m_n.tu);
eb14cb74
VS		 11488 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11489 pipe_config->has_dp_encoder,
11490 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
11491 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
11492 pipe_config->dp_m_n.tu);
b95af8be
VK		 11493
11494 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
11495 pipe_config->has_dp_encoder,
11496 pipe_config->dp_m2_n2.gmch_m,
11497 pipe_config->dp_m2_n2.gmch_n,
11498 pipe_config->dp_m2_n2.link_m,
11499 pipe_config->dp_m2_n2.link_n,
11500 pipe_config->dp_m2_n2.tu);
11501
55072d19
DV		 11502 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11503 pipe_config->has_audio,
11504 pipe_config->has_infoframe);
11505
c0b03411 11506 DRM_DEBUG_KMS("requested mode:\n");
2d112de7 11507 drm_mode_debug_printmodeline(&pipe_config->base.mode);
c0b03411 11508 DRM_DEBUG_KMS("adjusted mode:\n");
2d112de7
ACO		 11509 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
11510 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
d71b8d4a 11511 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
37327abd
VS		 11512 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
11513 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
0ec463d3
TU		 11514 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
11515 crtc->num_scalers,
11516 pipe_config->scaler_state.scaler_users,
11517 pipe_config->scaler_state.scaler_id);
c0b03411
DV		 11518 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11519 pipe_config->gmch_pfit.control,
11520 pipe_config->gmch_pfit.pgm_ratios,
11521 pipe_config->gmch_pfit.lvds_border_bits);
fd4daa9c 11522 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
c0b03411 11523 pipe_config->pch_pfit.pos,
fd4daa9c
CW		 11524 pipe_config->pch_pfit.size,
11525 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
42db64ef 11526 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
cf532bb2 11527 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
6a60cd87 11528
415ff0f6
TU		 11529 if (IS_BROXTON(dev)) {
11530 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, "
11531 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
11532 "pll6: 0x%x, pll8: 0x%x, pcsdw12: 0x%x\n",
11533 pipe_config->ddi_pll_sel,
11534 pipe_config->dpll_hw_state.ebb0,
11535 pipe_config->dpll_hw_state.pll0,
11536 pipe_config->dpll_hw_state.pll1,
11537 pipe_config->dpll_hw_state.pll2,
11538 pipe_config->dpll_hw_state.pll3,
11539 pipe_config->dpll_hw_state.pll6,
11540 pipe_config->dpll_hw_state.pll8,
11541 pipe_config->dpll_hw_state.pcsdw12);
11542 } else if (IS_SKYLAKE(dev)) {
11543 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
11544 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
11545 pipe_config->ddi_pll_sel,
11546 pipe_config->dpll_hw_state.ctrl1,
11547 pipe_config->dpll_hw_state.cfgcr1,
11548 pipe_config->dpll_hw_state.cfgcr2);
11549 } else if (HAS_DDI(dev)) {
11550 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x\n",
11551 pipe_config->ddi_pll_sel,
11552 pipe_config->dpll_hw_state.wrpll);
11553 } else {
11554 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
11555 "fp0: 0x%x, fp1: 0x%x\n",
11556 pipe_config->dpll_hw_state.dpll,
11557 pipe_config->dpll_hw_state.dpll_md,
11558 pipe_config->dpll_hw_state.fp0,
11559 pipe_config->dpll_hw_state.fp1);
11560 }
11561
6a60cd87
CK		 11562 DRM_DEBUG_KMS("planes on this crtc\n");
11563 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
11564 intel_plane = to_intel_plane(plane);
11565 if (intel_plane->pipe != crtc->pipe)
11566 continue;
11567
11568 state = to_intel_plane_state(plane->state);
11569 fb = state->base.fb;
11570 if (!fb) {
11571 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
11572 "disabled, scaler_id = %d\n",
11573 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
11574 plane->base.id, intel_plane->pipe,
11575 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
11576 drm_plane_index(plane), state->scaler_id);
11577 continue;
11578 }
11579
11580 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
11581 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
11582 plane->base.id, intel_plane->pipe,
11583 crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
11584 drm_plane_index(plane));
11585 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
11586 fb->base.id, fb->width, fb->height, fb->pixel_format);
11587 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
11588 state->scaler_id,
11589 state->src.x1 >> 16, state->src.y1 >> 16,
11590 drm_rect_width(&state->src) >> 16,
11591 drm_rect_height(&state->src) >> 16,
11592 state->dst.x1, state->dst.y1,
11593 drm_rect_width(&state->dst), drm_rect_height(&state->dst));
11594 }
c0b03411
DV		 11595}
11596
bc079e8b
VS		 11597static bool encoders_cloneable(const struct intel_encoder *a,
11598 const struct intel_encoder *b)
accfc0c5 11599{
bc079e8b
VS		 11600 /* masks could be asymmetric, so check both ways */
11601 return a == b || (a->cloneable & (1 << b->type) &&
11602 b->cloneable & (1 << a->type));
11603}
11604
98a221da
ACO		 11605static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11606 struct intel_crtc *crtc,
bc079e8b
VS		 11607 struct intel_encoder *encoder)
11608{
bc079e8b 11609 struct intel_encoder *source_encoder;
da3ced29 11610 struct drm_connector *connector;
98a221da
ACO		 11611 struct drm_connector_state *connector_state;
11612 int i;
bc079e8b 11613
da3ced29 11614 for_each_connector_in_state(state, connector, connector_state, i) {
98a221da 11615 if (connector_state->crtc != &crtc->base)
bc079e8b
VS		 11616 continue;
11617
98a221da
ACO		 11618 source_encoder =
11619 to_intel_encoder(connector_state->best_encoder);
bc079e8b
VS		 11620 if (!encoders_cloneable(encoder, source_encoder))
11621 return false;
11622 }
11623
11624 return true;
11625}
11626
98a221da
ACO		 11627static bool check_encoder_cloning(struct drm_atomic_state *state,
11628 struct intel_crtc *crtc)
bc079e8b 11629{
accfc0c5 11630 struct intel_encoder *encoder;
da3ced29 11631 struct drm_connector *connector;
98a221da
ACO		 11632 struct drm_connector_state *connector_state;
11633 int i;
accfc0c5 11634
da3ced29 11635 for_each_connector_in_state(state, connector, connector_state, i) {
98a221da
ACO		 11636 if (connector_state->crtc != &crtc->base)
11637 continue;
11638
11639 encoder = to_intel_encoder(connector_state->best_encoder);
11640 if (!check_single_encoder_cloning(state, crtc, encoder))
bc079e8b 11641 return false;
accfc0c5
DV		 11642 }
11643
bc079e8b 11644 return true;
accfc0c5
DV		 11645}
11646
5448a00d 11647static bool check_digital_port_conflicts(struct drm_atomic_state *state)
00f0b378 11648{
5448a00d
ACO		 11649 struct drm_device *dev = state->dev;
11650 struct intel_encoder *encoder;
da3ced29 11651 struct drm_connector *connector;
5448a00d 11652 struct drm_connector_state *connector_state;
00f0b378 11653 unsigned int used_ports = 0;
5448a00d 11654 int i;
00f0b378
VS		 11655
11656 /*
11657 * Walk the connector list instead of the encoder
11658 * list to detect the problem on ddi platforms
11659 * where there's just one encoder per digital port.
11660 */
da3ced29 11661 for_each_connector_in_state(state, connector, connector_state, i) {
5448a00d 11662 if (!connector_state->best_encoder)
00f0b378
VS		 11663 continue;
11664
5448a00d
ACO		 11665 encoder = to_intel_encoder(connector_state->best_encoder);
11666
11667 WARN_ON(!connector_state->crtc);
00f0b378
VS		 11668
11669 switch (encoder->type) {
11670 unsigned int port_mask;
11671 case INTEL_OUTPUT_UNKNOWN:
11672 if (WARN_ON(!HAS_DDI(dev)))
11673 break;
11674 case INTEL_OUTPUT_DISPLAYPORT:
11675 case INTEL_OUTPUT_HDMI:
11676 case INTEL_OUTPUT_EDP:
11677 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
11678
11679 /* the same port mustn't appear more than once */
11680 if (used_ports & port_mask)
11681 return false;
11682
11683 used_ports |= port_mask;
11684 default:
11685 break;
11686 }
11687 }
11688
11689 return true;
11690}
11691
83a57153
ACO		 11692static void
11693clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
11694{
11695 struct drm_crtc_state tmp_state;
663a3640 11696 struct intel_crtc_scaler_state scaler_state;
4978cc93
ACO		 11697 struct intel_dpll_hw_state dpll_hw_state;
11698 enum intel_dpll_id shared_dpll;
8504c74c 11699 uint32_t ddi_pll_sel;
83a57153 11700
7546a384
ACO		 11701 /* FIXME: before the switch to atomic started, a new pipe_config was
11702 * kzalloc'd. Code that depends on any field being zero should be
11703 * fixed, so that the crtc_state can be safely duplicated. For now,
11704 * only fields that are know to not cause problems are preserved. */
11705
83a57153 11706 tmp_state = crtc_state->base;
663a3640 11707 scaler_state = crtc_state->scaler_state;
4978cc93
ACO		 11708 shared_dpll = crtc_state->shared_dpll;
11709 dpll_hw_state = crtc_state->dpll_hw_state;
8504c74c 11710 ddi_pll_sel = crtc_state->ddi_pll_sel;
4978cc93 11711
83a57153 11712 memset(crtc_state, 0, sizeof *crtc_state);
4978cc93 11713
83a57153 11714 crtc_state->base = tmp_state;
663a3640 11715 crtc_state->scaler_state = scaler_state;
4978cc93
ACO		 11716 crtc_state->shared_dpll = shared_dpll;
11717 crtc_state->dpll_hw_state = dpll_hw_state;
8504c74c 11718 crtc_state->ddi_pll_sel = ddi_pll_sel;
83a57153
ACO		 11719}
11720
548ee15b 11721static int
b8cecdf5 11722intel_modeset_pipe_config(struct drm_crtc *crtc,
548ee15b
ACO		 11723 struct drm_atomic_state *state,
11724 struct intel_crtc_state *pipe_config)
ee7b9f93 11725{
7758a113 11726 struct intel_encoder *encoder;
da3ced29 11727 struct drm_connector *connector;
0b901879 11728 struct drm_connector_state *connector_state;
d328c9d7 11729 int base_bpp, ret = -EINVAL;
0b901879 11730 int i;
e29c22c0 11731 bool retry = true;
ee7b9f93 11732
98a221da 11733 if (!check_encoder_cloning(state, to_intel_crtc(crtc))) {
accfc0c5 11734 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
548ee15b 11735 return -EINVAL;
accfc0c5
DV		 11736 }
11737
5448a00d 11738 if (!check_digital_port_conflicts(state)) {
00f0b378 11739 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
548ee15b 11740 return -EINVAL;
00f0b378
VS		 11741 }
11742
83a57153 11743 clear_intel_crtc_state(pipe_config);
7758a113 11744
e143a21c
DV		 11745 pipe_config->cpu_transcoder =
11746 (enum transcoder) to_intel_crtc(crtc)->pipe;
b8cecdf5 11747
2960bc9c
ID		 11748 /*
11749 * Sanitize sync polarity flags based on requested ones. If neither
11750 * positive or negative polarity is requested, treat this as meaning
11751 * negative polarity.
11752 */
2d112de7 11753 if (!(pipe_config->base.adjusted_mode.flags &
2960bc9c 11754 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
2d112de7 11755 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
2960bc9c 11756
2d112de7 11757 if (!(pipe_config->base.adjusted_mode.flags &
2960bc9c 11758 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
2d112de7 11759 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
2960bc9c 11760
050f7aeb
DV		 11761 /* Compute a starting value for pipe_config->pipe_bpp taking the source
11762 * plane pixel format and any sink constraints into account. Returns the
11763 * source plane bpp so that dithering can be selected on mismatches
11764 * after encoders and crtc also have had their say. */
d328c9d7
DV		 11765 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
11766 pipe_config);
11767 if (base_bpp < 0)
4e53c2e0
DV		 11768 goto fail;
11769
e41a56be
VS		 11770 /*
11771 * Determine the real pipe dimensions. Note that stereo modes can
11772 * increase the actual pipe size due to the frame doubling and
11773 * insertion of additional space for blanks between the frame. This
11774 * is stored in the crtc timings. We use the requested mode to do this
11775 * computation to clearly distinguish it from the adjusted mode, which
11776 * can be changed by the connectors in the below retry loop.
11777 */
2d112de7 11778 drm_crtc_get_hv_timing(&pipe_config->base.mode,
ecb7e16b
GP		 11779 &pipe_config->pipe_src_w,
11780 &pipe_config->pipe_src_h);
e41a56be 11781
e29c22c0 11782encoder_retry:
ef1b460d 11783 /* Ensure the port clock defaults are reset when retrying. */
ff9a6750 11784 pipe_config->port_clock = 0;
ef1b460d 11785 pipe_config->pixel_multiplier = 1;
ff9a6750 11786
135c81b8 11787 /* Fill in default crtc timings, allow encoders to overwrite them. */
2d112de7
ACO		 11788 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
11789 CRTC_STEREO_DOUBLE);
135c81b8 11790
7758a113
DV		 11791 /* Pass our mode to the connectors and the CRTC to give them a chance to
11792 * adjust it according to limitations or connector properties, and also
11793 * a chance to reject the mode entirely.
47f1c6c9 11794 */
da3ced29 11795 for_each_connector_in_state(state, connector, connector_state, i) {
0b901879 11796 if (connector_state->crtc != crtc)
7758a113 11797 continue;
7ae89233 11798
0b901879
ACO		 11799 encoder = to_intel_encoder(connector_state->best_encoder);
11800
efea6e8e
DV		 11801 if (!(encoder->compute_config(encoder, pipe_config))) {
11802 DRM_DEBUG_KMS("Encoder config failure\n");
7758a113
DV		 11803 goto fail;
11804 }
ee7b9f93 11805 }
47f1c6c9 11806
ff9a6750
DV		 11807 /* Set default port clock if not overwritten by the encoder. Needs to be
11808 * done afterwards in case the encoder adjusts the mode. */
11809 if (!pipe_config->port_clock)
2d112de7 11810 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
241bfc38 11811 * pipe_config->pixel_multiplier;
ff9a6750 11812
a43f6e0f 11813 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
e29c22c0 11814 if (ret < 0) {
7758a113
DV		 11815 DRM_DEBUG_KMS("CRTC fixup failed\n");
11816 goto fail;
ee7b9f93 11817 }
e29c22c0
DV		 11818
11819 if (ret == RETRY) {
11820 if (WARN(!retry, "loop in pipe configuration computation\n")) {
11821 ret = -EINVAL;
11822 goto fail;
11823 }
11824
11825 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
11826 retry = false;
11827 goto encoder_retry;
11828 }
11829
d328c9d7 11830 pipe_config->dither = pipe_config->pipe_bpp != base_bpp;
4e53c2e0 11831 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
d328c9d7 11832 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
4e53c2e0 11833
548ee15b 11834 return 0;
7758a113 11835fail:
548ee15b 11836 return ret;
ee7b9f93 11837}
47f1c6c9 11838
ea9d758d 11839static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 11840{
ea9d758d 11841 struct drm_encoder *encoder;
f6e5b160 11842 struct drm_device *dev = crtc->dev;
f6e5b160 11843
ea9d758d
DV		 11844 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
11845 if (encoder->crtc == crtc)
11846 return true;
11847
11848 return false;
11849}
11850
0a9ab303
ACO		 11851static bool
11852needs_modeset(struct drm_crtc_state *state)
11853{
11854 return state->mode_changed || state->active_changed;
11855}
11856
ea9d758d 11857static void
0a9ab303 11858intel_modeset_update_state(struct drm_atomic_state *state)
ea9d758d 11859{
0a9ab303 11860 struct drm_device *dev = state->dev;
ba41c0de 11861 struct drm_i915_private *dev_priv = dev->dev_private;
ea9d758d 11862 struct intel_encoder *intel_encoder;
0a9ab303
ACO		 11863 struct drm_crtc *crtc;
11864 struct drm_crtc_state *crtc_state;
ea9d758d 11865 struct drm_connector *connector;
0a9ab303 11866 int i;
ea9d758d 11867
ba41c0de
DV		 11868 intel_shared_dpll_commit(dev_priv);
11869
b2784e15 11870 for_each_intel_encoder(dev, intel_encoder) {
ea9d758d
DV		 11871 if (!intel_encoder->base.crtc)
11872 continue;
11873
0a9ab303
ACO		 11874 for_each_crtc_in_state(state, crtc, crtc_state, i)
11875 if (crtc == intel_encoder->base.crtc)
11876 break;
11877
11878 if (crtc != intel_encoder->base.crtc)
11879 continue;
ea9d758d 11880
0a9ab303 11881 if (crtc_state->enable && needs_modeset(crtc_state))
ea9d758d
DV		 11882 intel_encoder->connectors_active = false;
11883 }
11884
a821fc46
ACO		 11885 drm_atomic_helper_swap_state(state->dev, state);
11886 intel_modeset_fixup_state(state);
ea9d758d 11887
7668851f 11888 /* Double check state. */
0a9ab303
ACO		 11889 for_each_crtc(dev, crtc) {
11890 WARN_ON(crtc->state->enable != intel_crtc_in_use(crtc));
ea9d758d
DV		 11891 }
11892
11893 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11894 if (!connector->encoder || !connector->encoder->crtc)
11895 continue;
11896
0a9ab303
ACO		 11897 for_each_crtc_in_state(state, crtc, crtc_state, i)
11898 if (crtc == connector->encoder->crtc)
11899 break;
11900
11901 if (crtc != connector->encoder->crtc)
11902 continue;
ea9d758d 11903
a821fc46 11904 if (crtc->state->enable && needs_modeset(crtc->state)) {
68d34720
DV		 11905 struct drm_property *dpms_property =
11906 dev->mode_config.dpms_property;
11907
ea9d758d 11908 connector->dpms = DRM_MODE_DPMS_ON;
662595df 11909 drm_object_property_set_value(&connector->base,
68d34720
DV		 11910 dpms_property,
11911 DRM_MODE_DPMS_ON);
ea9d758d
DV		 11912
11913 intel_encoder = to_intel_encoder(connector->encoder);
11914 intel_encoder->connectors_active = true;
11915 }
11916 }
11917
11918}
11919
3bd26263 11920static bool intel_fuzzy_clock_check(int clock1, int clock2)
f1f644dc 11921{
3bd26263 11922 int diff;
f1f644dc
JB		 11923
11924 if (clock1 == clock2)
11925 return true;
11926
11927 if (!clock1 || !clock2)
11928 return false;
11929
11930 diff = abs(clock1 - clock2);
11931
11932 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
11933 return true;
11934
11935 return false;
11936}
11937
25c5b266
DV		 11938#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
11939 list_for_each_entry((intel_crtc), \
11940 &(dev)->mode_config.crtc_list, \
11941 base.head) \
0973f18f 11942 if (mask & (1 <<(intel_crtc)->pipe))
25c5b266 11943
0e8ffe1b 11944static bool
2fa2fe9a 11945intel_pipe_config_compare(struct drm_device *dev,
5cec258b
ACO		 11946 struct intel_crtc_state *current_config,
11947 struct intel_crtc_state *pipe_config)
0e8ffe1b 11948{
66e985c0
DV		 11949#define PIPE_CONF_CHECK_X(name) \
11950 if (current_config->name != pipe_config->name) { \
11951 DRM_ERROR("mismatch in " #name " " \
11952 "(expected 0x%08x, found 0x%08x)\n", \
11953 current_config->name, \
11954 pipe_config->name); \
11955 return false; \
11956 }
11957
08a24034
DV		 11958#define PIPE_CONF_CHECK_I(name) \
11959 if (current_config->name != pipe_config->name) { \
11960 DRM_ERROR("mismatch in " #name " " \
11961 "(expected %i, found %i)\n", \
11962 current_config->name, \
11963 pipe_config->name); \
11964 return false; \
88adfff1
DV		 11965 }
11966
b95af8be
VK		 11967/* This is required for BDW+ where there is only one set of registers for
11968 * switching between high and low RR.
11969 * This macro can be used whenever a comparison has to be made between one
11970 * hw state and multiple sw state variables.
11971 */
11972#define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
11973 if ((current_config->name != pipe_config->name) && \
11974 (current_config->alt_name != pipe_config->name)) { \
11975 DRM_ERROR("mismatch in " #name " " \
11976 "(expected %i or %i, found %i)\n", \
11977 current_config->name, \
11978 current_config->alt_name, \
11979 pipe_config->name); \
11980 return false; \
11981 }
11982
1bd1bd80
DV		 11983#define PIPE_CONF_CHECK_FLAGS(name, mask) \
11984 if ((current_config->name ^ pipe_config->name) & (mask)) { \
6f02488e 11985 DRM_ERROR("mismatch in " #name "(" #mask ") " \
1bd1bd80
DV		 11986 "(expected %i, found %i)\n", \
11987 current_config->name & (mask), \
11988 pipe_config->name & (mask)); \
11989 return false; \
11990 }
11991
5e550656
VS		 11992#define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
11993 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
11994 DRM_ERROR("mismatch in " #name " " \
11995 "(expected %i, found %i)\n", \
11996 current_config->name, \
11997 pipe_config->name); \
11998 return false; \
11999 }
12000
bb760063
DV		 12001#define PIPE_CONF_QUIRK(quirk) \
12002 ((current_config->quirks | pipe_config->quirks) & (quirk))
12003
eccb140b
DV		 12004 PIPE_CONF_CHECK_I(cpu_transcoder);
12005
08a24034
DV		 12006 PIPE_CONF_CHECK_I(has_pch_encoder);
12007 PIPE_CONF_CHECK_I(fdi_lanes);
72419203
DV		 12008 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
12009 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
12010 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
12011 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
12012 PIPE_CONF_CHECK_I(fdi_m_n.tu);
08a24034 12013
eb14cb74 12014 PIPE_CONF_CHECK_I(has_dp_encoder);
b95af8be
VK		 12015
12016 if (INTEL_INFO(dev)->gen < 8) {
12017 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
12018 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
12019 PIPE_CONF_CHECK_I(dp_m_n.link_m);
12020 PIPE_CONF_CHECK_I(dp_m_n.link_n);
12021 PIPE_CONF_CHECK_I(dp_m_n.tu);
12022
12023 if (current_config->has_drrs) {
12024 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
12025 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
12026 PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
12027 PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
12028 PIPE_CONF_CHECK_I(dp_m2_n2.tu);
12029 }
12030 } else {
12031 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
12032 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
12033 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
12034 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
12035 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
12036 }
eb14cb74 12037
2d112de7
ACO		 12038 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12039 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12040 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12041 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12042 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12043 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
1bd1bd80 12044
2d112de7
ACO		 12045 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12046 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12047 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12048 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12049 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12050 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
1bd1bd80 12051
c93f54cf 12052 PIPE_CONF_CHECK_I(pixel_multiplier);
6897b4b5 12053 PIPE_CONF_CHECK_I(has_hdmi_sink);
b5a9fa09
DV		 12054 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12055 IS_VALLEYVIEW(dev))
12056 PIPE_CONF_CHECK_I(limited_color_range);
e43823ec 12057 PIPE_CONF_CHECK_I(has_infoframe);
6c49f241 12058
9ed109a7
DV		 12059 PIPE_CONF_CHECK_I(has_audio);
12060
2d112de7 12061 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
1bd1bd80
DV		 12062 DRM_MODE_FLAG_INTERLACE);
12063
bb760063 12064 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
2d112de7 12065 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 12066 DRM_MODE_FLAG_PHSYNC);
2d112de7 12067 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 12068 DRM_MODE_FLAG_NHSYNC);
2d112de7 12069 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 12070 DRM_MODE_FLAG_PVSYNC);
2d112de7 12071 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063
DV		 12072 DRM_MODE_FLAG_NVSYNC);
12073 }
045ac3b5 12074
37327abd
VS		 12075 PIPE_CONF_CHECK_I(pipe_src_w);
12076 PIPE_CONF_CHECK_I(pipe_src_h);
1bd1bd80 12077
9953599b
DV		 12078 /*
12079 * FIXME: BIOS likes to set up a cloned config with lvds+external
12080 * screen. Since we don't yet re-compute the pipe config when moving
12081 * just the lvds port away to another pipe the sw tracking won't match.
12082 *
12083 * Proper atomic modesets with recomputed global state will fix this.
12084 * Until then just don't check gmch state for inherited modes.
12085 */
12086 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
12087 PIPE_CONF_CHECK_I(gmch_pfit.control);
12088 /* pfit ratios are autocomputed by the hw on gen4+ */
12089 if (INTEL_INFO(dev)->gen < 4)
12090 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
12091 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
12092 }
12093
fd4daa9c
CW		 12094 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12095 if (current_config->pch_pfit.enabled) {
12096 PIPE_CONF_CHECK_I(pch_pfit.pos);
12097 PIPE_CONF_CHECK_I(pch_pfit.size);
12098 }
2fa2fe9a 12099
a1b2278e
CK		 12100 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12101
e59150dc
JB		 12102 /* BDW+ don't expose a synchronous way to read the state */
12103 if (IS_HASWELL(dev))
12104 PIPE_CONF_CHECK_I(ips_enabled);
42db64ef 12105
282740f7
VS		 12106 PIPE_CONF_CHECK_I(double_wide);
12107
26804afd
DV		 12108 PIPE_CONF_CHECK_X(ddi_pll_sel);
12109
c0d43d62 12110 PIPE_CONF_CHECK_I(shared_dpll);
66e985c0 12111 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8bcc2795 12112 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
66e985c0
DV		 12113 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12114 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
d452c5b6 12115 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
3f4cd19f
DL		 12116 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12117 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12118 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
c0d43d62 12119
42571aef
VS		 12120 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12121 PIPE_CONF_CHECK_I(pipe_bpp);
12122
2d112de7 12123 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
a9a7e98a 12124 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
5e550656 12125
66e985c0 12126#undef PIPE_CONF_CHECK_X
08a24034 12127#undef PIPE_CONF_CHECK_I
b95af8be 12128#undef PIPE_CONF_CHECK_I_ALT
1bd1bd80 12129#undef PIPE_CONF_CHECK_FLAGS
5e550656 12130#undef PIPE_CONF_CHECK_CLOCK_FUZZY
bb760063 12131#undef PIPE_CONF_QUIRK
88adfff1 12132
0e8ffe1b
DV		 12133 return true;
12134}
12135
08db6652
DL		 12136static void check_wm_state(struct drm_device *dev)
12137{
12138 struct drm_i915_private *dev_priv = dev->dev_private;
12139 struct skl_ddb_allocation hw_ddb, *sw_ddb;
12140 struct intel_crtc *intel_crtc;
12141 int plane;
12142
12143 if (INTEL_INFO(dev)->gen < 9)
12144 return;
12145
12146 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12147 sw_ddb = &dev_priv->wm.skl_hw.ddb;
12148
12149 for_each_intel_crtc(dev, intel_crtc) {
12150 struct skl_ddb_entry *hw_entry, *sw_entry;
12151 const enum pipe pipe = intel_crtc->pipe;
12152
12153 if (!intel_crtc->active)
12154 continue;
12155
12156 /* planes */
dd740780 12157 for_each_plane(dev_priv, pipe, plane) {
08db6652
DL		 12158 hw_entry = &hw_ddb.plane[pipe][plane];
12159 sw_entry = &sw_ddb->plane[pipe][plane];
12160
12161 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12162 continue;
12163
12164 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12165 "(expected (%u,%u), found (%u,%u))\n",
12166 pipe_name(pipe), plane + 1,
12167 sw_entry->start, sw_entry->end,
12168 hw_entry->start, hw_entry->end);
12169 }
12170
12171 /* cursor */
12172 hw_entry = &hw_ddb.cursor[pipe];
12173 sw_entry = &sw_ddb->cursor[pipe];
12174
12175 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12176 continue;
12177
12178 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12179 "(expected (%u,%u), found (%u,%u))\n",
12180 pipe_name(pipe),
12181 sw_entry->start, sw_entry->end,
12182 hw_entry->start, hw_entry->end);
12183 }
12184}
12185
91d1b4bd
DV		 12186static void
12187check_connector_state(struct drm_device *dev)
8af6cf88 12188{
8af6cf88
DV		 12189 struct intel_connector *connector;
12190
3a3371ff 12191 for_each_intel_connector(dev, connector) {
8af6cf88
DV		 12192 /* This also checks the encoder/connector hw state with the
12193 * ->get_hw_state callbacks. */
12194 intel_connector_check_state(connector);
12195
e2c719b7 12196 I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder,
8af6cf88
DV		 12197 "connector's staged encoder doesn't match current encoder\n");
12198 }
91d1b4bd
DV		 12199}
12200
12201static void
12202check_encoder_state(struct drm_device *dev)
12203{
12204 struct intel_encoder *encoder;
12205 struct intel_connector *connector;
8af6cf88 12206
b2784e15 12207 for_each_intel_encoder(dev, encoder) {
8af6cf88
DV		 12208 bool enabled = false;
12209 bool active = false;
12210 enum pipe pipe, tracked_pipe;
12211
12212 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12213 encoder->base.base.id,
8e329a03 12214 encoder->base.name);
8af6cf88 12215
e2c719b7 12216 I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc,
8af6cf88 12217 "encoder's stage crtc doesn't match current crtc\n");
e2c719b7 12218 I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc,
8af6cf88
DV		 12219 "encoder's active_connectors set, but no crtc\n");
12220
3a3371ff 12221 for_each_intel_connector(dev, connector) {
8af6cf88
DV		 12222 if (connector->base.encoder != &encoder->base)
12223 continue;
12224 enabled = true;
12225 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
12226 active = true;
12227 }
0e32b39c
DA		 12228 /*
12229 * for MST connectors if we unplug the connector is gone
12230 * away but the encoder is still connected to a crtc
12231 * until a modeset happens in response to the hotplug.
12232 */
12233 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
12234 continue;
12235
e2c719b7 12236 I915_STATE_WARN(!!encoder->base.crtc != enabled,
8af6cf88
DV		 12237 "encoder's enabled state mismatch "
12238 "(expected %i, found %i)\n",
12239 !!encoder->base.crtc, enabled);
e2c719b7 12240 I915_STATE_WARN(active && !encoder->base.crtc,
8af6cf88
DV		 12241 "active encoder with no crtc\n");
12242
e2c719b7 12243 I915_STATE_WARN(encoder->connectors_active != active,
8af6cf88
DV		 12244 "encoder's computed active state doesn't match tracked active state "
12245 "(expected %i, found %i)\n", active, encoder->connectors_active);
12246
12247 active = encoder->get_hw_state(encoder, &pipe);
e2c719b7 12248 I915_STATE_WARN(active != encoder->connectors_active,
8af6cf88
DV		 12249 "encoder's hw state doesn't match sw tracking "
12250 "(expected %i, found %i)\n",
12251 encoder->connectors_active, active);
12252
12253 if (!encoder->base.crtc)
12254 continue;
12255
12256 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
e2c719b7 12257 I915_STATE_WARN(active && pipe != tracked_pipe,
8af6cf88
DV		 12258 "active encoder's pipe doesn't match"
12259 "(expected %i, found %i)\n",
12260 tracked_pipe, pipe);
12261
12262 }
91d1b4bd
DV		 12263}
12264
12265static void
12266check_crtc_state(struct drm_device *dev)
12267{
fbee40df 12268 struct drm_i915_private *dev_priv = dev->dev_private;
91d1b4bd
DV		 12269 struct intel_crtc *crtc;
12270 struct intel_encoder *encoder;
5cec258b 12271 struct intel_crtc_state pipe_config;
8af6cf88 12272
d3fcc808 12273 for_each_intel_crtc(dev, crtc) {
8af6cf88
DV		 12274 bool enabled = false;
12275 bool active = false;
12276
045ac3b5
JB		 12277 memset(&pipe_config, 0, sizeof(pipe_config));
12278
8af6cf88
DV		 12279 DRM_DEBUG_KMS("[CRTC:%d]\n",
12280 crtc->base.base.id);
12281
83d65738 12282 I915_STATE_WARN(crtc->active && !crtc->base.state->enable,
8af6cf88
DV		 12283 "active crtc, but not enabled in sw tracking\n");
12284
b2784e15 12285 for_each_intel_encoder(dev, encoder) {
8af6cf88
DV		 12286 if (encoder->base.crtc != &crtc->base)
12287 continue;
12288 enabled = true;
12289 if (encoder->connectors_active)
12290 active = true;
12291 }
6c49f241 12292
e2c719b7 12293 I915_STATE_WARN(active != crtc->active,
8af6cf88
DV		 12294 "crtc's computed active state doesn't match tracked active state "
12295 "(expected %i, found %i)\n", active, crtc->active);
83d65738 12296 I915_STATE_WARN(enabled != crtc->base.state->enable,
8af6cf88 12297 "crtc's computed enabled state doesn't match tracked enabled state "
83d65738
MR		 12298 "(expected %i, found %i)\n", enabled,
12299 crtc->base.state->enable);
8af6cf88 12300
0e8ffe1b
DV		 12301 active = dev_priv->display.get_pipe_config(crtc,
12302 &pipe_config);
d62cf62a 12303
b6b5d049
VS		 12304 /* hw state is inconsistent with the pipe quirk */
12305 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12306 (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
d62cf62a
DV		 12307 active = crtc->active;
12308
b2784e15 12309 for_each_intel_encoder(dev, encoder) {
3eaba51c 12310 enum pipe pipe;
6c49f241
DV		 12311 if (encoder->base.crtc != &crtc->base)
12312 continue;
1d37b689 12313 if (encoder->get_hw_state(encoder, &pipe))
6c49f241
DV		 12314 encoder->get_config(encoder, &pipe_config);
12315 }
12316
e2c719b7 12317 I915_STATE_WARN(crtc->active != active,
0e8ffe1b
DV		 12318 "crtc active state doesn't match with hw state "
12319 "(expected %i, found %i)\n", crtc->active, active);
12320
c0b03411 12321 if (active &&
6e3c9717 12322 !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) {
e2c719b7 12323 I915_STATE_WARN(1, "pipe state doesn't match!\n");
c0b03411
DV		 12324 intel_dump_pipe_config(crtc, &pipe_config,
12325 "[hw state]");
6e3c9717 12326 intel_dump_pipe_config(crtc, crtc->config,
c0b03411
DV		 12327 "[sw state]");
12328 }
8af6cf88
DV		 12329 }
12330}
12331
91d1b4bd
DV		 12332static void
12333check_shared_dpll_state(struct drm_device *dev)
12334{
fbee40df 12335 struct drm_i915_private *dev_priv = dev->dev_private;
91d1b4bd
DV		 12336 struct intel_crtc *crtc;
12337 struct intel_dpll_hw_state dpll_hw_state;
12338 int i;
5358901f
DV		 12339
12340 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12341 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12342 int enabled_crtcs = 0, active_crtcs = 0;
12343 bool active;
12344
12345 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12346
12347 DRM_DEBUG_KMS("%s\n", pll->name);
12348
12349 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
12350
e2c719b7 12351 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
5358901f 12352 "more active pll users than references: %i vs %i\n",
3e369b76 12353 pll->active, hweight32(pll->config.crtc_mask));
e2c719b7 12354 I915_STATE_WARN(pll->active && !pll->on,
5358901f 12355 "pll in active use but not on in sw tracking\n");
e2c719b7 12356 I915_STATE_WARN(pll->on && !pll->active,
35c95375 12357 "pll in on but not on in use in sw tracking\n");
e2c719b7 12358 I915_STATE_WARN(pll->on != active,
5358901f
DV		 12359 "pll on state mismatch (expected %i, found %i)\n",
12360 pll->on, active);
12361
d3fcc808 12362 for_each_intel_crtc(dev, crtc) {
83d65738 12363 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
5358901f
DV		 12364 enabled_crtcs++;
12365 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12366 active_crtcs++;
12367 }
e2c719b7 12368 I915_STATE_WARN(pll->active != active_crtcs,
5358901f
DV		 12369 "pll active crtcs mismatch (expected %i, found %i)\n",
12370 pll->active, active_crtcs);
e2c719b7 12371 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
5358901f 12372 "pll enabled crtcs mismatch (expected %i, found %i)\n",
3e369b76 12373 hweight32(pll->config.crtc_mask), enabled_crtcs);
66e985c0 12374
e2c719b7 12375 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
66e985c0
DV		 12376 sizeof(dpll_hw_state)),
12377 "pll hw state mismatch\n");
5358901f 12378 }
8af6cf88
DV		 12379}
12380
91d1b4bd
DV		 12381void
12382intel_modeset_check_state(struct drm_device *dev)
12383{
08db6652 12384 check_wm_state(dev);
91d1b4bd
DV		 12385 check_connector_state(dev);
12386 check_encoder_state(dev);
12387 check_crtc_state(dev);
12388 check_shared_dpll_state(dev);
12389}
12390
5cec258b 12391void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
18442d08
VS		 12392 int dotclock)
12393{
12394 /*
12395 * FDI already provided one idea for the dotclock.
12396 * Yell if the encoder disagrees.
12397 */
2d112de7 12398 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
18442d08 12399 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
2d112de7 12400 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
18442d08
VS		 12401}
12402
80715b2f
VS		 12403static void update_scanline_offset(struct intel_crtc *crtc)
12404{
12405 struct drm_device *dev = crtc->base.dev;
12406
12407 /*
12408 * The scanline counter increments at the leading edge of hsync.
12409 *
12410 * On most platforms it starts counting from vtotal-1 on the
12411 * first active line. That means the scanline counter value is
12412 * always one less than what we would expect. Ie. just after
12413 * start of vblank, which also occurs at start of hsync (on the
12414 * last active line), the scanline counter will read vblank_start-1.
12415 *
12416 * On gen2 the scanline counter starts counting from 1 instead
12417 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12418 * to keep the value positive), instead of adding one.
12419 *
12420 * On HSW+ the behaviour of the scanline counter depends on the output
12421 * type. For DP ports it behaves like most other platforms, but on HDMI
12422 * there's an extra 1 line difference. So we need to add two instead of
12423 * one to the value.
12424 */
12425 if (IS_GEN2(dev)) {
6e3c9717 12426 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
80715b2f
VS		 12427 int vtotal;
12428
12429 vtotal = mode->crtc_vtotal;
12430 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
12431 vtotal /= 2;
12432
12433 crtc->scanline_offset = vtotal - 1;
12434 } else if (HAS_DDI(dev) &&
409ee761 12435 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
80715b2f
VS		 12436 crtc->scanline_offset = 2;
12437 } else
12438 crtc->scanline_offset = 1;
12439}
12440
5cec258b 12441static struct intel_crtc_state *
7f27126e 12442intel_modeset_compute_config(struct drm_crtc *crtc,
0a9ab303 12443 struct drm_atomic_state *state)
7f27126e 12444{
548ee15b 12445 struct intel_crtc_state *pipe_config;
0b901879
ACO		 12446 int ret = 0;
12447
12448 ret = drm_atomic_add_affected_connectors(state, crtc);
12449 if (ret)
12450 return ERR_PTR(ret);
7f27126e 12451
8c7b5ccb
ACO		 12452 ret = drm_atomic_helper_check_modeset(state->dev, state);
12453 if (ret)
12454 return ERR_PTR(ret);
7f27126e 12455
7f27126e
JB		 12456 /*
12457 * Note this needs changes when we start tracking multiple modes
12458 * and crtcs. At that point we'll need to compute the whole config
12459 * (i.e. one pipe_config for each crtc) rather than just the one
12460 * for this crtc.
12461 */
548ee15b
ACO		 12462 pipe_config = intel_atomic_get_crtc_state(state, to_intel_crtc(crtc));
12463 if (IS_ERR(pipe_config))
12464 return pipe_config;
83a57153 12465
4fed33f6 12466 if (!pipe_config->base.enable)
548ee15b 12467 return pipe_config;
7f27126e 12468
8c7b5ccb 12469 ret = intel_modeset_pipe_config(crtc, state, pipe_config);
548ee15b
ACO		 12470 if (ret)
12471 return ERR_PTR(ret);
12472
8d8c9b51
ACO		 12473 /* Check things that can only be changed through modeset */
12474 if (pipe_config->has_audio !=
12475 to_intel_crtc(crtc)->config->has_audio)
12476 pipe_config->base.mode_changed = true;
12477
12478 /*
12479 * Note we have an issue here with infoframes: current code
12480 * only updates them on the full mode set path per hw
12481 * requirements. So here we should be checking for any
12482 * required changes and forcing a mode set.
12483 */
12484
548ee15b 12485 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,"[modeset]");
db7542dd 12486
8c7b5ccb
ACO		 12487 ret = drm_atomic_helper_check_planes(state->dev, state);
12488 if (ret)
12489 return ERR_PTR(ret);
12490
548ee15b 12491 return pipe_config;
7f27126e
JB		 12492}
12493
0a9ab303 12494static int __intel_set_mode_setup_plls(struct drm_atomic_state *state)
ed6739ef 12495{
225da59b 12496 struct drm_device *dev = state->dev;
ed6739ef 12497 struct drm_i915_private *dev_priv = to_i915(dev);
0a9ab303 12498 unsigned clear_pipes = 0;
ed6739ef 12499 struct intel_crtc *intel_crtc;
0a9ab303
ACO		 12500 struct intel_crtc_state *intel_crtc_state;
12501 struct drm_crtc *crtc;
12502 struct drm_crtc_state *crtc_state;
ed6739ef 12503 int ret = 0;
0a9ab303 12504 int i;
ed6739ef
ACO		 12505
12506 if (!dev_priv->display.crtc_compute_clock)
12507 return 0;
12508
0a9ab303
ACO		 12509 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12510 intel_crtc = to_intel_crtc(crtc);
4978cc93 12511 intel_crtc_state = to_intel_crtc_state(crtc_state);
0a9ab303 12512
4978cc93 12513 if (needs_modeset(crtc_state)) {
0a9ab303 12514 clear_pipes |= 1 << intel_crtc->pipe;
4978cc93 12515 intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
4978cc93 12516 }
0a9ab303
ACO		 12517 }
12518
ed6739ef
ACO		 12519 ret = intel_shared_dpll_start_config(dev_priv, clear_pipes);
12520 if (ret)
12521 goto done;
12522
0a9ab303
ACO		 12523 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12524 if (!needs_modeset(crtc_state) || !crtc_state->enable)
225da59b
ACO		 12525 continue;
12526
0a9ab303
ACO		 12527 intel_crtc = to_intel_crtc(crtc);
12528 intel_crtc_state = to_intel_crtc_state(crtc_state);
12529
ed6739ef 12530 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
0a9ab303 12531 intel_crtc_state);
ed6739ef
ACO		 12532 if (ret) {
12533 intel_shared_dpll_abort_config(dev_priv);
12534 goto done;
12535 }
12536 }
12537
12538done:
12539 return ret;
12540}
12541
054518dd
ACO		 12542/* Code that should eventually be part of atomic_check() */
12543static int __intel_set_mode_checks(struct drm_atomic_state *state)
12544{
12545 struct drm_device *dev = state->dev;
12546 int ret;
12547
12548 /*
12549 * See if the config requires any additional preparation, e.g.
12550 * to adjust global state with pipes off. We need to do this
12551 * here so we can get the modeset_pipe updated config for the new
12552 * mode set on this crtc. For other crtcs we need to use the
12553 * adjusted_mode bits in the crtc directly.
12554 */
12555 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
12556 ret = valleyview_modeset_global_pipes(state);
12557 if (ret)
12558 return ret;
12559 }
12560
12561 ret = __intel_set_mode_setup_plls(state);
12562 if (ret)
12563 return ret;
12564
12565 return 0;
12566}
12567
0a9ab303 12568static int __intel_set_mode(struct drm_crtc *modeset_crtc,
0a9ab303 12569 struct intel_crtc_state *pipe_config)
a6778b3c 12570{
0a9ab303 12571 struct drm_device *dev = modeset_crtc->dev;
fbee40df 12572 struct drm_i915_private *dev_priv = dev->dev_private;
304603f4 12573 struct drm_atomic_state *state = pipe_config->base.state;
0a9ab303
ACO		 12574 struct drm_crtc *crtc;
12575 struct drm_crtc_state *crtc_state;
c0c36b94 12576 int ret = 0;
0a9ab303 12577 int i;
a6778b3c 12578
054518dd
ACO		 12579 ret = __intel_set_mode_checks(state);
12580 if (ret < 0)
12581 return ret;
12582
d4afb8cc
ACO		 12583 ret = drm_atomic_helper_prepare_planes(dev, state);
12584 if (ret)
12585 return ret;
12586
0a9ab303
ACO		 12587 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12588 if (!needs_modeset(crtc_state))
12589 continue;
460da916 12590
0a9ab303
ACO		 12591 if (!crtc_state->enable) {
12592 intel_crtc_disable(crtc);
12593 } else if (crtc->state->enable) {
12594 intel_crtc_disable_planes(crtc);
12595 dev_priv->display.crtc_disable(crtc);
ce22dba9 12596 }
ea9d758d 12597 }
a6778b3c 12598
6c4c86f5
DV		 12599 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
12600 * to set it here already despite that we pass it down the callchain.
7f27126e
JB		 12601 *
12602 * Note we'll need to fix this up when we start tracking multiple
12603 * pipes; here we assume a single modeset_pipe and only track the
12604 * single crtc and mode.
f6e5b160 12605 */
0a9ab303 12606 if (pipe_config->base.enable && needs_modeset(&pipe_config->base)) {
8c7b5ccb 12607 modeset_crtc->mode = pipe_config->base.mode;
c326c0a9
VS		 12608
12609 /*
12610 * Calculate and store various constants which
12611 * are later needed by vblank and swap-completion
12612 * timestamping. They are derived from true hwmode.
12613 */
0a9ab303 12614 drm_calc_timestamping_constants(modeset_crtc,
2d112de7 12615 &pipe_config->base.adjusted_mode);
b8cecdf5 12616 }
7758a113 12617
ea9d758d
DV		 12618 /* Only after disabling all output pipelines that will be changed can we
12619 * update the the output configuration. */
0a9ab303 12620 intel_modeset_update_state(state);
f6e5b160 12621
a821fc46
ACO		 12622 /* The state has been swaped above, so state actually contains the
12623 * old state now. */
12624
304603f4 12625 modeset_update_crtc_power_domains(state);
47fab737 12626
d4afb8cc 12627 drm_atomic_helper_commit_planes(dev, state);
a6778b3c
DV		 12628
12629 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
0a9ab303 12630 for_each_crtc_in_state(state, crtc, crtc_state, i) {
a821fc46 12631 if (!needs_modeset(crtc->state) || !crtc->state->enable)
0a9ab303
ACO		 12632 continue;
12633
12634 update_scanline_offset(to_intel_crtc(crtc));
80715b2f 12635
0a9ab303
ACO		 12636 dev_priv->display.crtc_enable(crtc);
12637 intel_crtc_enable_planes(crtc);
80715b2f 12638 }
a6778b3c 12639
a6778b3c 12640 /* FIXME: add subpixel order */
83a57153 12641
d4afb8cc
ACO		 12642 drm_atomic_helper_cleanup_planes(dev, state);
12643
2bfb4627
ACO		 12644 drm_atomic_state_free(state);
12645
9eb45f22 12646 return 0;
f6e5b160
CW		 12647}
12648
0a9ab303 12649static int intel_set_mode_with_config(struct drm_crtc *crtc,
0a9ab303 12650 struct intel_crtc_state *pipe_config)
f30da187
DV		 12651{
12652 int ret;
12653
8c7b5ccb 12654 ret = __intel_set_mode(crtc, pipe_config);
f30da187
DV		 12655
12656 if (ret == 0)
12657 intel_modeset_check_state(crtc->dev);
12658
12659 return ret;
12660}
12661
7f27126e 12662static int intel_set_mode(struct drm_crtc *crtc,
83a57153 12663 struct drm_atomic_state *state)
7f27126e 12664{
5cec258b 12665 struct intel_crtc_state *pipe_config;
83a57153 12666 int ret = 0;
7f27126e 12667
8c7b5ccb 12668 pipe_config = intel_modeset_compute_config(crtc, state);
83a57153
ACO		 12669 if (IS_ERR(pipe_config)) {
12670 ret = PTR_ERR(pipe_config);
12671 goto out;
12672 }
12673
8c7b5ccb 12674 ret = intel_set_mode_with_config(crtc, pipe_config);
83a57153
ACO		 12675 if (ret)
12676 goto out;
7f27126e 12677
83a57153
ACO		 12678out:
12679 return ret;
7f27126e
JB		 12680}
12681
c0c36b94
CW		 12682void intel_crtc_restore_mode(struct drm_crtc *crtc)
12683{
83a57153
ACO		 12684 struct drm_device *dev = crtc->dev;
12685 struct drm_atomic_state *state;
4be07317 12686 struct intel_crtc *intel_crtc;
83a57153
ACO		 12687 struct intel_encoder *encoder;
12688 struct intel_connector *connector;
12689 struct drm_connector_state *connector_state;
4be07317 12690 struct intel_crtc_state *crtc_state;
2bfb4627 12691 int ret;
83a57153
ACO		 12692
12693 state = drm_atomic_state_alloc(dev);
12694 if (!state) {
12695 DRM_DEBUG_KMS("[CRTC:%d] mode restore failed, out of memory",
12696 crtc->base.id);
12697 return;
12698 }
12699
12700 state->acquire_ctx = dev->mode_config.acquire_ctx;
12701
12702 /* The force restore path in the HW readout code relies on the staged
12703 * config still keeping the user requested config while the actual
12704 * state has been overwritten by the configuration read from HW. We
12705 * need to copy the staged config to the atomic state, otherwise the
12706 * mode set will just reapply the state the HW is already in. */
12707 for_each_intel_encoder(dev, encoder) {
12708 if (&encoder->new_crtc->base != crtc)
12709 continue;
12710
12711 for_each_intel_connector(dev, connector) {
12712 if (connector->new_encoder != encoder)
12713 continue;
12714
12715 connector_state = drm_atomic_get_connector_state(state, &connector->base);
12716 if (IS_ERR(connector_state)) {
12717 DRM_DEBUG_KMS("Failed to add [CONNECTOR:%d:%s] to state: %ld\n",
12718 connector->base.base.id,
12719 connector->base.name,
12720 PTR_ERR(connector_state));
12721 continue;
12722 }
12723
12724 connector_state->crtc = crtc;
12725 connector_state->best_encoder = &encoder->base;
12726 }
12727 }
12728
4be07317
ACO		 12729 for_each_intel_crtc(dev, intel_crtc) {
12730 if (intel_crtc->new_enabled == intel_crtc->base.enabled)
12731 continue;
12732
12733 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
12734 if (IS_ERR(crtc_state)) {
12735 DRM_DEBUG_KMS("Failed to add [CRTC:%d] to state: %ld\n",
12736 intel_crtc->base.base.id,
12737 PTR_ERR(crtc_state));
12738 continue;
12739 }
12740
49d6fa21
ML		 12741 crtc_state->base.active = crtc_state->base.enable =
12742 intel_crtc->new_enabled;
8c7b5ccb
ACO		 12743
12744 if (&intel_crtc->base == crtc)
12745 drm_mode_copy(&crtc_state->base.mode, &crtc->mode);
4be07317
ACO		 12746 }
12747
d3a40d1b
ACO		 12748 intel_modeset_setup_plane_state(state, crtc, &crtc->mode,
12749 crtc->primary->fb, crtc->x, crtc->y);
12750
2bfb4627
ACO		 12751 ret = intel_set_mode(crtc, state);
12752 if (ret)
12753 drm_atomic_state_free(state);
c0c36b94
CW		 12754}
12755
25c5b266
DV		 12756#undef for_each_intel_crtc_masked
12757
b7885264
ACO		 12758static bool intel_connector_in_mode_set(struct intel_connector *connector,
12759 struct drm_mode_set *set)
12760{
12761 int ro;
12762
12763 for (ro = 0; ro < set->num_connectors; ro++)
12764 if (set->connectors[ro] == &connector->base)
12765 return true;
12766
12767 return false;
12768}
12769
2e431051 12770static int
9a935856
DV		 12771intel_modeset_stage_output_state(struct drm_device *dev,
12772 struct drm_mode_set *set,
944b0c76 12773 struct drm_atomic_state *state)
50f56119 12774{
9a935856 12775 struct intel_connector *connector;
d5432a9d 12776 struct drm_connector *drm_connector;
944b0c76 12777 struct drm_connector_state *connector_state;
d5432a9d
ACO		 12778 struct drm_crtc *crtc;
12779 struct drm_crtc_state *crtc_state;
12780 int i, ret;
50f56119 12781
9abdda74 12782 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 12783 * of connectors. For paranoia, double-check this. */
12784 WARN_ON(!set->fb && (set->num_connectors != 0));
12785 WARN_ON(set->fb && (set->num_connectors == 0));
12786
3a3371ff 12787 for_each_intel_connector(dev, connector) {
b7885264
ACO		 12788 bool in_mode_set = intel_connector_in_mode_set(connector, set);
12789
d5432a9d
ACO		 12790 if (!in_mode_set && connector->base.state->crtc != set->crtc)
12791 continue;
12792
12793 connector_state =
12794 drm_atomic_get_connector_state(state, &connector->base);
12795 if (IS_ERR(connector_state))
12796 return PTR_ERR(connector_state);
12797
b7885264
ACO		 12798 if (in_mode_set) {
12799 int pipe = to_intel_crtc(set->crtc)->pipe;
d5432a9d
ACO		 12800 connector_state->best_encoder =
12801 &intel_find_encoder(connector, pipe)->base;
50f56119
DV		 12802 }
12803
d5432a9d 12804 if (connector->base.state->crtc != set->crtc)
b7885264
ACO		 12805 continue;
12806
9a935856
DV		 12807 /* If we disable the crtc, disable all its connectors. Also, if
12808 * the connector is on the changing crtc but not on the new
12809 * connector list, disable it. */
b7885264 12810 if (!set->fb || !in_mode_set) {
d5432a9d 12811 connector_state->best_encoder = NULL;
9a935856
DV		 12812
12813 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
12814 connector->base.base.id,
c23cc417 12815 connector->base.name);
9a935856 12816 }
50f56119 12817 }
9a935856 12818 /* connector->new_encoder is now updated for all connectors. */
50f56119 12819
d5432a9d
ACO		 12820 for_each_connector_in_state(state, drm_connector, connector_state, i) {
12821 connector = to_intel_connector(drm_connector);
12822
12823 if (!connector_state->best_encoder) {
12824 ret = drm_atomic_set_crtc_for_connector(connector_state,
12825 NULL);
12826 if (ret)
12827 return ret;
7668851f 12828
50f56119 12829 continue;
d5432a9d 12830 }
50f56119 12831
d5432a9d
ACO		 12832 if (intel_connector_in_mode_set(connector, set)) {
12833 struct drm_crtc *crtc = connector->base.state->crtc;
12834
12835 /* If this connector was in a previous crtc, add it
12836 * to the state. We might need to disable it. */
12837 if (crtc) {
12838 crtc_state =
12839 drm_atomic_get_crtc_state(state, crtc);
12840 if (IS_ERR(crtc_state))
12841 return PTR_ERR(crtc_state);
12842 }
12843
12844 ret = drm_atomic_set_crtc_for_connector(connector_state,
12845 set->crtc);
12846 if (ret)
12847 return ret;
12848 }
50f56119
DV		 12849
12850 /* Make sure the new CRTC will work with the encoder */
d5432a9d
ACO		 12851 if (!drm_encoder_crtc_ok(connector_state->best_encoder,
12852 connector_state->crtc)) {
5e2b584e 12853 return -EINVAL;
50f56119 12854 }
944b0c76 12855
9a935856
DV		 12856 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
12857 connector->base.base.id,
c23cc417 12858 connector->base.name,
d5432a9d 12859 connector_state->crtc->base.id);
944b0c76 12860
d5432a9d
ACO		 12861 if (connector_state->best_encoder != &connector->encoder->base)
12862 connector->encoder =
12863 to_intel_encoder(connector_state->best_encoder);
0e32b39c 12864 }
7668851f 12865
d5432a9d 12866 for_each_crtc_in_state(state, crtc, crtc_state, i) {
49d6fa21
ML		 12867 bool has_connectors;
12868
d5432a9d
ACO		 12869 ret = drm_atomic_add_affected_connectors(state, crtc);
12870 if (ret)
12871 return ret;
4be07317 12872
49d6fa21
ML		 12873 has_connectors = !!drm_atomic_connectors_for_crtc(state, crtc);
12874 if (has_connectors != crtc_state->enable)
12875 crtc_state->enable =
12876 crtc_state->active = has_connectors;
7668851f
VS		 12877 }
12878
8c7b5ccb
ACO		 12879 ret = intel_modeset_setup_plane_state(state, set->crtc, set->mode,
12880 set->fb, set->x, set->y);
12881 if (ret)
12882 return ret;
12883
12884 crtc_state = drm_atomic_get_crtc_state(state, set->crtc);
12885 if (IS_ERR(crtc_state))
12886 return PTR_ERR(crtc_state);
12887
12888 if (set->mode)
12889 drm_mode_copy(&crtc_state->mode, set->mode);
12890
12891 if (set->num_connectors)
12892 crtc_state->active = true;
12893
2e431051
DV		 12894 return 0;
12895}
12896
bb546623
ACO		 12897static bool primary_plane_visible(struct drm_crtc *crtc)
12898{
12899 struct intel_plane_state *plane_state =
12900 to_intel_plane_state(crtc->primary->state);
12901
12902 return plane_state->visible;
12903}
12904
2e431051
DV		 12905static int intel_crtc_set_config(struct drm_mode_set *set)
12906{
12907 struct drm_device *dev;
83a57153 12908 struct drm_atomic_state *state = NULL;
5cec258b 12909 struct intel_crtc_state *pipe_config;
bb546623 12910 bool primary_plane_was_visible;
2e431051 12911 int ret;
2e431051 12912
8d3e375e
DV		 12913 BUG_ON(!set);
12914 BUG_ON(!set->crtc);
12915 BUG_ON(!set->crtc->helper_private);
2e431051 12916
7e53f3a4
DV		 12917 /* Enforce sane interface api - has been abused by the fb helper. */
12918 BUG_ON(!set->mode && set->fb);
12919 BUG_ON(set->fb && set->num_connectors == 0);
431e50f7 12920
2e431051
DV		 12921 if (set->fb) {
12922 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
12923 set->crtc->base.id, set->fb->base.id,
12924 (int)set->num_connectors, set->x, set->y);
12925 } else {
12926 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 12927 }
12928
12929 dev = set->crtc->dev;
12930
83a57153 12931 state = drm_atomic_state_alloc(dev);
7cbf41d6
ACO		 12932 if (!state)
12933 return -ENOMEM;
83a57153
ACO		 12934
12935 state->acquire_ctx = dev->mode_config.acquire_ctx;
12936
462a425a 12937 ret = intel_modeset_stage_output_state(dev, set, state);
2e431051 12938 if (ret)
7cbf41d6 12939 goto out;
2e431051 12940
8c7b5ccb 12941 pipe_config = intel_modeset_compute_config(set->crtc, state);
20664591 12942 if (IS_ERR(pipe_config)) {
6ac0483b 12943 ret = PTR_ERR(pipe_config);
7cbf41d6 12944 goto out;
20664591 12945 }
50f52756 12946
1f9954d0
JB		 12947 intel_update_pipe_size(to_intel_crtc(set->crtc));
12948
bb546623
ACO		 12949 primary_plane_was_visible = primary_plane_visible(set->crtc);
12950
8c7b5ccb 12951 ret = intel_set_mode_with_config(set->crtc, pipe_config);
bb546623
ACO		 12952
12953 if (ret == 0 &&
12954 pipe_config->base.enable &&
12955 pipe_config->base.planes_changed &&
12956 !needs_modeset(&pipe_config->base)) {
3b150f08 12957 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
3b150f08
MR		 12958
12959 /*
12960 * We need to make sure the primary plane is re-enabled if it
12961 * has previously been turned off.
12962 */
bb546623
ACO		 12963 if (ret == 0 && !primary_plane_was_visible &&
12964 primary_plane_visible(set->crtc)) {
3b150f08 12965 WARN_ON(!intel_crtc->active);
87d4300a 12966 intel_post_enable_primary(set->crtc);
3b150f08
MR		 12967 }
12968
7ca51a3a
JB		 12969 /*
12970 * In the fastboot case this may be our only check of the
12971 * state after boot. It would be better to only do it on
12972 * the first update, but we don't have a nice way of doing that
12973 * (and really, set_config isn't used much for high freq page
12974 * flipping, so increasing its cost here shouldn't be a big
12975 * deal).
12976 */
d330a953 12977 if (i915.fastboot && ret == 0)
7ca51a3a 12978 intel_modeset_check_state(set->crtc->dev);
50f56119
DV		 12979 }
12980
2d05eae1 12981 if (ret) {
bf67dfeb
DV		 12982 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
12983 set->crtc->base.id, ret);
2d05eae1 12984 }
50f56119 12985
7cbf41d6 12986out:
2bfb4627
ACO		 12987 if (ret)
12988 drm_atomic_state_free(state);
50f56119
DV		 12989 return ret;
12990}
f6e5b160
CW		 12991
12992static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160 12993 .gamma_set = intel_crtc_gamma_set,
50f56119 12994 .set_config = intel_crtc_set_config,
f6e5b160
CW		 12995 .destroy = intel_crtc_destroy,
12996 .page_flip = intel_crtc_page_flip,
1356837e
MR		 12997 .atomic_duplicate_state = intel_crtc_duplicate_state,
12998 .atomic_destroy_state = intel_crtc_destroy_state,
f6e5b160
CW		 12999};
13000
5358901f
DV		 13001static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
13002 struct intel_shared_dpll *pll,
13003 struct intel_dpll_hw_state *hw_state)
ee7b9f93 13004{
5358901f 13005 uint32_t val;
ee7b9f93 13006
f458ebbc 13007 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
bd2bb1b9
PZ		 13008 return false;
13009
5358901f 13010 val = I915_READ(PCH_DPLL(pll->id));
66e985c0
DV		 13011 hw_state->dpll = val;
13012 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
13013 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
5358901f
DV		 13014
13015 return val & DPLL_VCO_ENABLE;
13016}
13017
15bdd4cf
DV		 13018static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
13019 struct intel_shared_dpll *pll)
13020{
3e369b76
ACO		 13021 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
13022 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
15bdd4cf
DV		 13023}
13024
e7b903d2
DV		 13025static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
13026 struct intel_shared_dpll *pll)
13027{
e7b903d2 13028 /* PCH refclock must be enabled first */
89eff4be 13029 ibx_assert_pch_refclk_enabled(dev_priv);
e7b903d2 13030
3e369b76 13031 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
15bdd4cf
DV		 13032
13033 /* Wait for the clocks to stabilize. */
13034 POSTING_READ(PCH_DPLL(pll->id));
13035 udelay(150);
13036
13037 /* The pixel multiplier can only be updated once the
13038 * DPLL is enabled and the clocks are stable.
13039 *
13040 * So write it again.
13041 */
3e369b76 13042 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
15bdd4cf 13043 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 13044 udelay(200);
13045}
13046
13047static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
13048 struct intel_shared_dpll *pll)
13049{
13050 struct drm_device *dev = dev_priv->dev;
13051 struct intel_crtc *crtc;
e7b903d2
DV		 13052
13053 /* Make sure no transcoder isn't still depending on us. */
d3fcc808 13054 for_each_intel_crtc(dev, crtc) {
e7b903d2
DV		 13055 if (intel_crtc_to_shared_dpll(crtc) == pll)
13056 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
ee7b9f93
JB		 13057 }
13058
15bdd4cf
DV		 13059 I915_WRITE(PCH_DPLL(pll->id), 0);
13060 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 13061 udelay(200);
13062}
13063
46edb027
DV		 13064static char *ibx_pch_dpll_names[] = {
13065 "PCH DPLL A",
13066 "PCH DPLL B",
13067};
13068
7c74ade1 13069static void ibx_pch_dpll_init(struct drm_device *dev)
ee7b9f93 13070{
e7b903d2 13071 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93
JB		 13072 int i;
13073
7c74ade1 13074 dev_priv->num_shared_dpll = 2;
ee7b9f93 13075
e72f9fbf 13076 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
46edb027
DV		 13077 dev_priv->shared_dplls[i].id = i;
13078 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
15bdd4cf 13079 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
e7b903d2
DV		 13080 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
13081 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
5358901f
DV		 13082 dev_priv->shared_dplls[i].get_hw_state =
13083 ibx_pch_dpll_get_hw_state;
ee7b9f93
JB		 13084 }
13085}
13086
7c74ade1
DV		 13087static void intel_shared_dpll_init(struct drm_device *dev)
13088{
e7b903d2 13089 struct drm_i915_private *dev_priv = dev->dev_private;
7c74ade1 13090
9cd86933
DV		 13091 if (HAS_DDI(dev))
13092 intel_ddi_pll_init(dev);
13093 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7c74ade1
DV		 13094 ibx_pch_dpll_init(dev);
13095 else
13096 dev_priv->num_shared_dpll = 0;
13097
13098 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
7c74ade1
DV		 13099}
13100
1fc0a8f7
TU		 13101/**
13102 * intel_wm_need_update - Check whether watermarks need updating
13103 * @plane: drm plane
13104 * @state: new plane state
13105 *
13106 * Check current plane state versus the new one to determine whether
13107 * watermarks need to be recalculated.
13108 *
13109 * Returns true or false.
13110 */
13111bool intel_wm_need_update(struct drm_plane *plane,
13112 struct drm_plane_state *state)
13113{
13114 /* Update watermarks on tiling changes. */
13115 if (!plane->state->fb || !state->fb ||
13116 plane->state->fb->modifier[0] != state->fb->modifier[0] ||
13117 plane->state->rotation != state->rotation)
13118 return true;
13119
13120 return false;
13121}
13122
6beb8c23
MR		 13123/**
13124 * intel_prepare_plane_fb - Prepare fb for usage on plane
13125 * @plane: drm plane to prepare for
13126 * @fb: framebuffer to prepare for presentation
13127 *
13128 * Prepares a framebuffer for usage on a display plane. Generally this
13129 * involves pinning the underlying object and updating the frontbuffer tracking
13130 * bits. Some older platforms need special physical address handling for
13131 * cursor planes.
13132 *
13133 * Returns 0 on success, negative error code on failure.
13134 */
13135int
13136intel_prepare_plane_fb(struct drm_plane *plane,
d136dfee
TU		 13137 struct drm_framebuffer *fb,
13138 const struct drm_plane_state *new_state)
465c120c
MR		 13139{
13140 struct drm_device *dev = plane->dev;
6beb8c23
MR		 13141 struct intel_plane *intel_plane = to_intel_plane(plane);
13142 enum pipe pipe = intel_plane->pipe;
13143 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13144 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
13145 unsigned frontbuffer_bits = 0;
13146 int ret = 0;
465c120c 13147
ea2c67bb 13148 if (!obj)
465c120c
MR		 13149 return 0;
13150
6beb8c23
MR		 13151 switch (plane->type) {
13152 case DRM_PLANE_TYPE_PRIMARY:
13153 frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(pipe);
13154 break;
13155 case DRM_PLANE_TYPE_CURSOR:
13156 frontbuffer_bits = INTEL_FRONTBUFFER_CURSOR(pipe);
13157 break;
13158 case DRM_PLANE_TYPE_OVERLAY:
13159 frontbuffer_bits = INTEL_FRONTBUFFER_SPRITE(pipe);
13160 break;
13161 }
465c120c 13162
6beb8c23 13163 mutex_lock(&dev->struct_mutex);
465c120c 13164
6beb8c23
MR		 13165 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13166 INTEL_INFO(dev)->cursor_needs_physical) {
13167 int align = IS_I830(dev) ? 16 * 1024 : 256;
13168 ret = i915_gem_object_attach_phys(obj, align);
13169 if (ret)
13170 DRM_DEBUG_KMS("failed to attach phys object\n");
13171 } else {
82bc3b2d 13172 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL);
6beb8c23 13173 }
465c120c 13174
6beb8c23
MR		 13175 if (ret == 0)
13176 i915_gem_track_fb(old_obj, obj, frontbuffer_bits);
fdd508a6 13177
4c34574f 13178 mutex_unlock(&dev->struct_mutex);
465c120c 13179
6beb8c23
MR		 13180 return ret;
13181}
13182
38f3ce3a
MR		 13183/**
13184 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13185 * @plane: drm plane to clean up for
13186 * @fb: old framebuffer that was on plane
13187 *
13188 * Cleans up a framebuffer that has just been removed from a plane.
13189 */
13190void
13191intel_cleanup_plane_fb(struct drm_plane *plane,
d136dfee
TU		 13192 struct drm_framebuffer *fb,
13193 const struct drm_plane_state *old_state)
38f3ce3a
MR		 13194{
13195 struct drm_device *dev = plane->dev;
13196 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13197
13198 if (WARN_ON(!obj))
13199 return;
13200
13201 if (plane->type != DRM_PLANE_TYPE_CURSOR ||
13202 !INTEL_INFO(dev)->cursor_needs_physical) {
13203 mutex_lock(&dev->struct_mutex);
82bc3b2d 13204 intel_unpin_fb_obj(fb, old_state);
38f3ce3a
MR		 13205 mutex_unlock(&dev->struct_mutex);
13206 }
465c120c
MR		 13207}
13208
6156a456
CK		 13209int
13210skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13211{
13212 int max_scale;
13213 struct drm_device *dev;
13214 struct drm_i915_private *dev_priv;
13215 int crtc_clock, cdclk;
13216
13217 if (!intel_crtc || !crtc_state)
13218 return DRM_PLANE_HELPER_NO_SCALING;
13219
13220 dev = intel_crtc->base.dev;
13221 dev_priv = dev->dev_private;
13222 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13223 cdclk = dev_priv->display.get_display_clock_speed(dev);
13224
13225 if (!crtc_clock || !cdclk)
13226 return DRM_PLANE_HELPER_NO_SCALING;
13227
13228 /*
13229 * skl max scale is lower of:
13230 * close to 3 but not 3, -1 is for that purpose
13231 * or
13232 * cdclk/crtc_clock
13233 */
13234 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13235
13236 return max_scale;
13237}
13238
465c120c 13239static int
3c692a41
GP		 13240intel_check_primary_plane(struct drm_plane *plane,
13241 struct intel_plane_state *state)
13242{
32b7eeec
MR		 13243 struct drm_device *dev = plane->dev;
13244 struct drm_i915_private *dev_priv = dev->dev_private;
2b875c22 13245 struct drm_crtc *crtc = state->base.crtc;
ea2c67bb 13246 struct intel_crtc *intel_crtc;
6156a456 13247 struct intel_crtc_state *crtc_state;
2b875c22 13248 struct drm_framebuffer *fb = state->base.fb;
3c692a41
GP		 13249 struct drm_rect *dest = &state->dst;
13250 struct drm_rect *src = &state->src;
13251 const struct drm_rect *clip = &state->clip;
d8106366 13252 bool can_position = false;
6156a456
CK		 13253 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13254 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
465c120c
MR		 13255 int ret;
13256
ea2c67bb
MR		 13257 crtc = crtc ? crtc : plane->crtc;
13258 intel_crtc = to_intel_crtc(crtc);
6156a456
CK		 13259 crtc_state = state->base.state ?
13260 intel_atomic_get_crtc_state(state->base.state, intel_crtc) : NULL;
ea2c67bb 13261
6156a456
CK		 13262 if (INTEL_INFO(dev)->gen >= 9) {
13263 min_scale = 1;
13264 max_scale = skl_max_scale(intel_crtc, crtc_state);
d8106366 13265 can_position = true;
6156a456 13266 }
d8106366 13267
c59cb179
MR		 13268 ret = drm_plane_helper_check_update(plane, crtc, fb,
13269 src, dest, clip,
6156a456
CK		 13270 min_scale,
13271 max_scale,
d8106366
SJ		 13272 can_position, true,
13273 &state->visible);
c59cb179
MR		 13274 if (ret)
13275 return ret;
465c120c 13276
32b7eeec 13277 if (intel_crtc->active) {
b70709a6
ML		 13278 struct intel_plane_state *old_state =
13279 to_intel_plane_state(plane->state);
13280
32b7eeec
MR		 13281 intel_crtc->atomic.wait_for_flips = true;
13282
13283 /*
13284 * FBC does not work on some platforms for rotated
13285 * planes, so disable it when rotation is not 0 and
13286 * update it when rotation is set back to 0.
13287 *
13288 * FIXME: This is redundant with the fbc update done in
13289 * the primary plane enable function except that that
13290 * one is done too late. We eventually need to unify
13291 * this.
13292 */
b70709a6 13293 if (state->visible &&
32b7eeec 13294 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
e35fef21 13295 dev_priv->fbc.crtc == intel_crtc &&
8e7d688b 13296 state->base.rotation != BIT(DRM_ROTATE_0)) {
32b7eeec
MR		 13297 intel_crtc->atomic.disable_fbc = true;
13298 }
13299
b70709a6 13300 if (state->visible && !old_state->visible) {
32b7eeec
MR		 13301 /*
13302 * BDW signals flip done immediately if the plane
13303 * is disabled, even if the plane enable is already
13304 * armed to occur at the next vblank :(
13305 */
b70709a6 13306 if (IS_BROADWELL(dev))
32b7eeec
MR		 13307 intel_crtc->atomic.wait_vblank = true;
13308 }
13309
13310 intel_crtc->atomic.fb_bits |=
13311 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
13312
13313 intel_crtc->atomic.update_fbc = true;
0fda6568 13314
1fc0a8f7 13315 if (intel_wm_need_update(plane, &state->base))
0fda6568 13316 intel_crtc->atomic.update_wm = true;
ccc759dc
GP		 13317 }
13318
6156a456
CK		 13319 if (INTEL_INFO(dev)->gen >= 9) {
13320 ret = skl_update_scaler_users(intel_crtc, crtc_state,
13321 to_intel_plane(plane), state, 0);
13322 if (ret)
13323 return ret;
13324 }
13325
14af293f
GP		 13326 return 0;
13327}
13328
13329static void
13330intel_commit_primary_plane(struct drm_plane *plane,
13331 struct intel_plane_state *state)
13332{
2b875c22
MR		 13333 struct drm_crtc *crtc = state->base.crtc;
13334 struct drm_framebuffer *fb = state->base.fb;
13335 struct drm_device *dev = plane->dev;
14af293f 13336 struct drm_i915_private *dev_priv = dev->dev_private;
ea2c67bb 13337 struct intel_crtc *intel_crtc;
14af293f
GP		 13338 struct drm_rect *src = &state->src;
13339
ea2c67bb
MR		 13340 crtc = crtc ? crtc : plane->crtc;
13341 intel_crtc = to_intel_crtc(crtc);
cf4c7c12
MR		 13342
13343 plane->fb = fb;
9dc806fc
MR		 13344 crtc->x = src->x1 >> 16;
13345 crtc->y = src->y1 >> 16;
ccc759dc 13346
ccc759dc 13347 if (intel_crtc->active) {
27321ae8 13348 if (state->visible)
ccc759dc
GP		 13349 /* FIXME: kill this fastboot hack */
13350 intel_update_pipe_size(intel_crtc);
465c120c 13351
27321ae8
ML		 13352 dev_priv->display.update_primary_plane(crtc, plane->fb,
13353 crtc->x, crtc->y);
ccc759dc 13354 }
465c120c
MR		 13355}
13356
a8ad0d8e
ML		 13357static void
13358intel_disable_primary_plane(struct drm_plane *plane,
13359 struct drm_crtc *crtc,
13360 bool force)
13361{
13362 struct drm_device *dev = plane->dev;
13363 struct drm_i915_private *dev_priv = dev->dev_private;
13364
a8ad0d8e
ML		 13365 dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
13366}
13367
32b7eeec 13368static void intel_begin_crtc_commit(struct drm_crtc *crtc)
3c692a41 13369{
32b7eeec 13370 struct drm_device *dev = crtc->dev;
140fd38d 13371 struct drm_i915_private *dev_priv = dev->dev_private;
3c692a41 13372 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ea2c67bb
MR		 13373 struct intel_plane *intel_plane;
13374 struct drm_plane *p;
13375 unsigned fb_bits = 0;
13376
13377 /* Track fb's for any planes being disabled */
13378 list_for_each_entry(p, &dev->mode_config.plane_list, head) {
13379 intel_plane = to_intel_plane(p);
13380
13381 if (intel_crtc->atomic.disabled_planes &
13382 (1 << drm_plane_index(p))) {
13383 switch (p->type) {
13384 case DRM_PLANE_TYPE_PRIMARY:
13385 fb_bits = INTEL_FRONTBUFFER_PRIMARY(intel_plane->pipe);
13386 break;
13387 case DRM_PLANE_TYPE_CURSOR:
13388 fb_bits = INTEL_FRONTBUFFER_CURSOR(intel_plane->pipe);
13389 break;
13390 case DRM_PLANE_TYPE_OVERLAY:
13391 fb_bits = INTEL_FRONTBUFFER_SPRITE(intel_plane->pipe);
13392 break;
13393 }
3c692a41 13394
ea2c67bb
MR		 13395 mutex_lock(&dev->struct_mutex);
13396 i915_gem_track_fb(intel_fb_obj(p->fb), NULL, fb_bits);
13397 mutex_unlock(&dev->struct_mutex);
13398 }
13399 }
3c692a41 13400
32b7eeec
MR		 13401 if (intel_crtc->atomic.wait_for_flips)
13402 intel_crtc_wait_for_pending_flips(crtc);
3c692a41 13403
32b7eeec
MR		 13404 if (intel_crtc->atomic.disable_fbc)
13405 intel_fbc_disable(dev);
3c692a41 13406
32b7eeec
MR		 13407 if (intel_crtc->atomic.pre_disable_primary)
13408 intel_pre_disable_primary(crtc);
3c692a41 13409
32b7eeec
MR		 13410 if (intel_crtc->atomic.update_wm)
13411 intel_update_watermarks(crtc);
3c692a41 13412
32b7eeec 13413 intel_runtime_pm_get(dev_priv);
3c692a41 13414
c34c9ee4
MR		 13415 /* Perform vblank evasion around commit operation */
13416 if (intel_crtc->active)
13417 intel_crtc->atomic.evade =
13418 intel_pipe_update_start(intel_crtc,
13419 &intel_crtc->atomic.start_vbl_count);
32b7eeec
MR		 13420}
13421
13422static void intel_finish_crtc_commit(struct drm_crtc *crtc)
13423{
13424 struct drm_device *dev = crtc->dev;
13425 struct drm_i915_private *dev_priv = dev->dev_private;
13426 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13427 struct drm_plane *p;
13428
c34c9ee4
MR		 13429 if (intel_crtc->atomic.evade)
13430 intel_pipe_update_end(intel_crtc,
13431 intel_crtc->atomic.start_vbl_count);
3c692a41 13432
140fd38d 13433 intel_runtime_pm_put(dev_priv);
3c692a41 13434
32b7eeec
MR		 13435 if (intel_crtc->atomic.wait_vblank)
13436 intel_wait_for_vblank(dev, intel_crtc->pipe);
13437
13438 intel_frontbuffer_flip(dev, intel_crtc->atomic.fb_bits);
13439
13440 if (intel_crtc->atomic.update_fbc) {
ccc759dc 13441 mutex_lock(&dev->struct_mutex);
7ff0ebcc 13442 intel_fbc_update(dev);
ccc759dc 13443 mutex_unlock(&dev->struct_mutex);
38f3ce3a 13444 }
3c692a41 13445
32b7eeec
MR		 13446 if (intel_crtc->atomic.post_enable_primary)
13447 intel_post_enable_primary(crtc);
3c692a41 13448
32b7eeec
MR		 13449 drm_for_each_legacy_plane(p, &dev->mode_config.plane_list)
13450 if (intel_crtc->atomic.update_sprite_watermarks & drm_plane_index(p))
13451 intel_update_sprite_watermarks(p, crtc, 0, 0, 0,
13452 false, false);
13453
13454 memset(&intel_crtc->atomic, 0, sizeof(intel_crtc->atomic));
3c692a41
GP		 13455}
13456
cf4c7c12 13457/**
4a3b8769
MR		 13458 * intel_plane_destroy - destroy a plane
13459 * @plane: plane to destroy
cf4c7c12 13460 *
4a3b8769
MR		 13461 * Common destruction function for all types of planes (primary, cursor,
13462 * sprite).
cf4c7c12 13463 */
4a3b8769 13464void intel_plane_destroy(struct drm_plane *plane)
465c120c
MR		 13465{
13466 struct intel_plane *intel_plane = to_intel_plane(plane);
13467 drm_plane_cleanup(plane);
13468 kfree(intel_plane);
13469}
13470
65a3fea0 13471const struct drm_plane_funcs intel_plane_funcs = {
70a101f8
MR		 13472 .update_plane = drm_atomic_helper_update_plane,
13473 .disable_plane = drm_atomic_helper_disable_plane,
3d7d6510 13474 .destroy = intel_plane_destroy,
c196e1d6 13475 .set_property = drm_atomic_helper_plane_set_property,
a98b3431
MR		 13476 .atomic_get_property = intel_plane_atomic_get_property,
13477 .atomic_set_property = intel_plane_atomic_set_property,
ea2c67bb
MR		 13478 .atomic_duplicate_state = intel_plane_duplicate_state,
13479 .atomic_destroy_state = intel_plane_destroy_state,
13480
465c120c
MR		 13481};
13482
13483static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13484 int pipe)
13485{
13486 struct intel_plane *primary;
8e7d688b 13487 struct intel_plane_state *state;
465c120c
MR		 13488 const uint32_t *intel_primary_formats;
13489 int num_formats;
13490
13491 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13492 if (primary == NULL)
13493 return NULL;
13494
8e7d688b
MR		 13495 state = intel_create_plane_state(&primary->base);
13496 if (!state) {
ea2c67bb
MR		 13497 kfree(primary);
13498 return NULL;
13499 }
8e7d688b 13500 primary->base.state = &state->base;
ea2c67bb 13501
465c120c
MR		 13502 primary->can_scale = false;
13503 primary->max_downscale = 1;
6156a456
CK		 13504 if (INTEL_INFO(dev)->gen >= 9) {
13505 primary->can_scale = true;
af99ceda 13506 state->scaler_id = -1;
6156a456 13507 }
465c120c
MR		 13508 primary->pipe = pipe;
13509 primary->plane = pipe;
c59cb179
MR		 13510 primary->check_plane = intel_check_primary_plane;
13511 primary->commit_plane = intel_commit_primary_plane;
a8ad0d8e 13512 primary->disable_plane = intel_disable_primary_plane;
08e221fb 13513 primary->ckey.flags = I915_SET_COLORKEY_NONE;
465c120c
MR		 13514 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13515 primary->plane = !pipe;
13516
6c0fd451
DL		 13517 if (INTEL_INFO(dev)->gen >= 9) {
13518 intel_primary_formats = skl_primary_formats;
13519 num_formats = ARRAY_SIZE(skl_primary_formats);
13520 } else if (INTEL_INFO(dev)->gen >= 4) {
568db4f2
DL		 13521 intel_primary_formats = i965_primary_formats;
13522 num_formats = ARRAY_SIZE(i965_primary_formats);
6c0fd451
DL		 13523 } else {
13524 intel_primary_formats = i8xx_primary_formats;
13525 num_formats = ARRAY_SIZE(i8xx_primary_formats);
465c120c
MR		 13526 }
13527
13528 drm_universal_plane_init(dev, &primary->base, 0,
65a3fea0 13529 &intel_plane_funcs,
465c120c
MR		 13530 intel_primary_formats, num_formats,
13531 DRM_PLANE_TYPE_PRIMARY);
48404c1e 13532
3b7a5119
SJ		 13533 if (INTEL_INFO(dev)->gen >= 4)
13534 intel_create_rotation_property(dev, primary);
48404c1e 13535
ea2c67bb
MR		 13536 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13537
465c120c
MR		 13538 return &primary->base;
13539}
13540
3b7a5119
SJ		 13541void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13542{
13543 if (!dev->mode_config.rotation_property) {
13544 unsigned long flags = BIT(DRM_ROTATE_0) |
13545 BIT(DRM_ROTATE_180);
13546
13547 if (INTEL_INFO(dev)->gen >= 9)
13548 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13549
13550 dev->mode_config.rotation_property =
13551 drm_mode_create_rotation_property(dev, flags);
13552 }
13553 if (dev->mode_config.rotation_property)
13554 drm_object_attach_property(&plane->base.base,
13555 dev->mode_config.rotation_property,
13556 plane->base.state->rotation);
13557}
13558
3d7d6510 13559static int
852e787c
GP		 13560intel_check_cursor_plane(struct drm_plane *plane,
13561 struct intel_plane_state *state)
3d7d6510 13562{
2b875c22 13563 struct drm_crtc *crtc = state->base.crtc;
ea2c67bb 13564 struct drm_device *dev = plane->dev;
2b875c22 13565 struct drm_framebuffer *fb = state->base.fb;
852e787c
GP		 13566 struct drm_rect *dest = &state->dst;
13567 struct drm_rect *src = &state->src;
13568 const struct drm_rect *clip = &state->clip;
757f9a3e 13569 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
ea2c67bb 13570 struct intel_crtc *intel_crtc;
757f9a3e
GP		 13571 unsigned stride;
13572 int ret;
3d7d6510 13573
ea2c67bb
MR		 13574 crtc = crtc ? crtc : plane->crtc;
13575 intel_crtc = to_intel_crtc(crtc);
13576
757f9a3e 13577 ret = drm_plane_helper_check_update(plane, crtc, fb,
852e787c 13578 src, dest, clip,
3d7d6510
MR		 13579 DRM_PLANE_HELPER_NO_SCALING,
13580 DRM_PLANE_HELPER_NO_SCALING,
852e787c 13581 true, true, &state->visible);
757f9a3e
GP		 13582 if (ret)
13583 return ret;
13584
13585
13586 /* if we want to turn off the cursor ignore width and height */
13587 if (!obj)
32b7eeec 13588 goto finish;
757f9a3e 13589
757f9a3e 13590 /* Check for which cursor types we support */
ea2c67bb
MR		 13591 if (!cursor_size_ok(dev, state->base.crtc_w, state->base.crtc_h)) {
13592 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13593 state->base.crtc_w, state->base.crtc_h);
757f9a3e
GP		 13594 return -EINVAL;
13595 }
13596
ea2c67bb
MR		 13597 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13598 if (obj->base.size < stride * state->base.crtc_h) {
757f9a3e
GP		 13599 DRM_DEBUG_KMS("buffer is too small\n");
13600 return -ENOMEM;
13601 }
13602
3a656b54 13603 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
757f9a3e
GP		 13604 DRM_DEBUG_KMS("cursor cannot be tiled\n");
13605 ret = -EINVAL;
13606 }
757f9a3e 13607
32b7eeec
MR		 13608finish:
13609 if (intel_crtc->active) {
3749f463 13610 if (plane->state->crtc_w != state->base.crtc_w)
32b7eeec
MR		 13611 intel_crtc->atomic.update_wm = true;
13612
13613 intel_crtc->atomic.fb_bits |=
13614 INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe);
13615 }
13616
757f9a3e 13617 return ret;
852e787c 13618}
3d7d6510 13619
a8ad0d8e
ML		 13620static void
13621intel_disable_cursor_plane(struct drm_plane *plane,
13622 struct drm_crtc *crtc,
13623 bool force)
13624{
13625 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13626
13627 if (!force) {
13628 plane->fb = NULL;
13629 intel_crtc->cursor_bo = NULL;
13630 intel_crtc->cursor_addr = 0;
13631 }
13632
13633 intel_crtc_update_cursor(crtc, false);
13634}
13635
f4a2cf29 13636static void
852e787c
GP		 13637intel_commit_cursor_plane(struct drm_plane *plane,
13638 struct intel_plane_state *state)
13639{
2b875c22 13640 struct drm_crtc *crtc = state->base.crtc;
ea2c67bb
MR		 13641 struct drm_device *dev = plane->dev;
13642 struct intel_crtc *intel_crtc;
2b875c22 13643 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
a912f12f 13644 uint32_t addr;
852e787c 13645
ea2c67bb
MR		 13646 crtc = crtc ? crtc : plane->crtc;
13647 intel_crtc = to_intel_crtc(crtc);
13648
2b875c22 13649 plane->fb = state->base.fb;
ea2c67bb
MR		 13650 crtc->cursor_x = state->base.crtc_x;
13651 crtc->cursor_y = state->base.crtc_y;
13652
a912f12f
GP		 13653 if (intel_crtc->cursor_bo == obj)
13654 goto update;
4ed91096 13655
f4a2cf29 13656 if (!obj)
a912f12f 13657 addr = 0;
f4a2cf29 13658 else if (!INTEL_INFO(dev)->cursor_needs_physical)
a912f12f 13659 addr = i915_gem_obj_ggtt_offset(obj);
f4a2cf29 13660 else
a912f12f 13661 addr = obj->phys_handle->busaddr;
852e787c 13662
a912f12f
GP		 13663 intel_crtc->cursor_addr = addr;
13664 intel_crtc->cursor_bo = obj;
13665update:
852e787c 13666
32b7eeec 13667 if (intel_crtc->active)
a912f12f 13668 intel_crtc_update_cursor(crtc, state->visible);
852e787c
GP		 13669}
13670
3d7d6510
MR		 13671static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
13672 int pipe)
13673{
13674 struct intel_plane *cursor;
8e7d688b 13675 struct intel_plane_state *state;
3d7d6510
MR		 13676
13677 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13678 if (cursor == NULL)
13679 return NULL;
13680
8e7d688b
MR		 13681 state = intel_create_plane_state(&cursor->base);
13682 if (!state) {
ea2c67bb
MR		 13683 kfree(cursor);
13684 return NULL;
13685 }
8e7d688b 13686 cursor->base.state = &state->base;
ea2c67bb 13687
3d7d6510
MR		 13688 cursor->can_scale = false;
13689 cursor->max_downscale = 1;
13690 cursor->pipe = pipe;
13691 cursor->plane = pipe;
c59cb179
MR		 13692 cursor->check_plane = intel_check_cursor_plane;
13693 cursor->commit_plane = intel_commit_cursor_plane;
a8ad0d8e 13694 cursor->disable_plane = intel_disable_cursor_plane;
3d7d6510
MR		 13695
13696 drm_universal_plane_init(dev, &cursor->base, 0,
65a3fea0 13697 &intel_plane_funcs,
3d7d6510
MR		 13698 intel_cursor_formats,
13699 ARRAY_SIZE(intel_cursor_formats),
13700 DRM_PLANE_TYPE_CURSOR);
4398ad45
VS		 13701
13702 if (INTEL_INFO(dev)->gen >= 4) {
13703 if (!dev->mode_config.rotation_property)
13704 dev->mode_config.rotation_property =
13705 drm_mode_create_rotation_property(dev,
13706 BIT(DRM_ROTATE_0) |
13707 BIT(DRM_ROTATE_180));
13708 if (dev->mode_config.rotation_property)
13709 drm_object_attach_property(&cursor->base.base,
13710 dev->mode_config.rotation_property,
8e7d688b 13711 state->base.rotation);
4398ad45
VS		 13712 }
13713
af99ceda
CK		 13714 if (INTEL_INFO(dev)->gen >=9)
13715 state->scaler_id = -1;
13716
ea2c67bb
MR		 13717 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13718
3d7d6510
MR		 13719 return &cursor->base;
13720}
13721
549e2bfb
CK		 13722static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
13723 struct intel_crtc_state *crtc_state)
13724{
13725 int i;
13726 struct intel_scaler *intel_scaler;
13727 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
13728
13729 for (i = 0; i < intel_crtc->num_scalers; i++) {
13730 intel_scaler = &scaler_state->scalers[i];
13731 intel_scaler->in_use = 0;
13732 intel_scaler->id = i;
13733
13734 intel_scaler->mode = PS_SCALER_MODE_DYN;
13735 }
13736
13737 scaler_state->scaler_id = -1;
13738}
13739
b358d0a6 13740static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 13741{
fbee40df 13742 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 13743 struct intel_crtc *intel_crtc;
f5de6e07 13744 struct intel_crtc_state *crtc_state = NULL;
3d7d6510
MR		 13745 struct drm_plane *primary = NULL;
13746 struct drm_plane *cursor = NULL;
465c120c 13747 int i, ret;
79e53945 13748
955382f3 13749 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
79e53945
JB		 13750 if (intel_crtc == NULL)
13751 return;
13752
f5de6e07
ACO		 13753 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13754 if (!crtc_state)
13755 goto fail;
550acefd
ACO		 13756 intel_crtc->config = crtc_state;
13757 intel_crtc->base.state = &crtc_state->base;
07878248 13758 crtc_state->base.crtc = &intel_crtc->base;
f5de6e07 13759
549e2bfb
CK		 13760 /* initialize shared scalers */
13761 if (INTEL_INFO(dev)->gen >= 9) {
13762 if (pipe == PIPE_C)
13763 intel_crtc->num_scalers = 1;
13764 else
13765 intel_crtc->num_scalers = SKL_NUM_SCALERS;
13766
13767 skl_init_scalers(dev, intel_crtc, crtc_state);
13768 }
13769
465c120c 13770 primary = intel_primary_plane_create(dev, pipe);
3d7d6510
MR		 13771 if (!primary)
13772 goto fail;
13773
13774 cursor = intel_cursor_plane_create(dev, pipe);
13775 if (!cursor)
13776 goto fail;
13777
465c120c 13778 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
3d7d6510
MR		 13779 cursor, &intel_crtc_funcs);
13780 if (ret)
13781 goto fail;
79e53945
JB		 13782
13783 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 13784 for (i = 0; i < 256; i++) {
13785 intel_crtc->lut_r[i] = i;
13786 intel_crtc->lut_g[i] = i;
13787 intel_crtc->lut_b[i] = i;
13788 }
13789
1f1c2e24
VS		 13790 /*
13791 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
8c0f92e1 13792 * is hooked to pipe B. Hence we want plane A feeding pipe B.
1f1c2e24 13793 */
80824003
JB		 13794 intel_crtc->pipe = pipe;
13795 intel_crtc->plane = pipe;
3a77c4c4 13796 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
28c97730 13797 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 13798 intel_crtc->plane = !pipe;
80824003
JB		 13799 }
13800
4b0e333e
CW		 13801 intel_crtc->cursor_base = ~0;
13802 intel_crtc->cursor_cntl = ~0;
dc41c154 13803 intel_crtc->cursor_size = ~0;
8d7849db 13804
22fd0fab
JB		 13805 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
13806 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
13807 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
13808 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
13809
79e53945 13810 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
87b6b101
DV		 13811
13812 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
3d7d6510
MR		 13813 return;
13814
13815fail:
13816 if (primary)
13817 drm_plane_cleanup(primary);
13818 if (cursor)
13819 drm_plane_cleanup(cursor);
f5de6e07 13820 kfree(crtc_state);
3d7d6510 13821 kfree(intel_crtc);
79e53945
JB		 13822}
13823
752aa88a
JB		 13824enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
13825{
13826 struct drm_encoder *encoder = connector->base.encoder;
6e9f798d 13827 struct drm_device *dev = connector->base.dev;
752aa88a 13828
51fd371b 13829 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
752aa88a 13830
d3babd3f 13831 if (!encoder || WARN_ON(!encoder->crtc))
752aa88a
JB		 13832 return INVALID_PIPE;
13833
13834 return to_intel_crtc(encoder->crtc)->pipe;
13835}
13836
08d7b3d1 13837int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 13838 struct drm_file *file)
08d7b3d1 13839{
08d7b3d1 13840 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7707e653 13841 struct drm_crtc *drmmode_crtc;
c05422d5 13842 struct intel_crtc *crtc;
08d7b3d1 13843
7707e653 13844 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
08d7b3d1 13845
7707e653 13846 if (!drmmode_crtc) {
08d7b3d1 13847 DRM_ERROR("no such CRTC id\n");
3f2c2057 13848 return -ENOENT;
08d7b3d1
CW		 13849 }
13850
7707e653 13851 crtc = to_intel_crtc(drmmode_crtc);
c05422d5 13852 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 13853
c05422d5 13854 return 0;
08d7b3d1
CW		 13855}
13856
66a9278e 13857static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 13858{
66a9278e
DV		 13859 struct drm_device *dev = encoder->base.dev;
13860 struct intel_encoder *source_encoder;
79e53945 13861 int index_mask = 0;
79e53945
JB		 13862 int entry = 0;
13863
b2784e15 13864 for_each_intel_encoder(dev, source_encoder) {
bc079e8b 13865 if (encoders_cloneable(encoder, source_encoder))
66a9278e
DV		 13866 index_mask |= (1 << entry);
13867
79e53945
JB		 13868 entry++;
13869 }
4ef69c7a 13870
79e53945
JB		 13871 return index_mask;
13872}
13873
4d302442
CW		 13874static bool has_edp_a(struct drm_device *dev)
13875{
13876 struct drm_i915_private *dev_priv = dev->dev_private;
13877
13878 if (!IS_MOBILE(dev))
13879 return false;
13880
13881 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
13882 return false;
13883
e3589908 13884 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
4d302442
CW		 13885 return false;
13886
13887 return true;
13888}
13889
84b4e042
JB		 13890static bool intel_crt_present(struct drm_device *dev)
13891{
13892 struct drm_i915_private *dev_priv = dev->dev_private;
13893
884497ed
DL		 13894 if (INTEL_INFO(dev)->gen >= 9)
13895 return false;
13896
cf404ce4 13897 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
84b4e042
JB		 13898 return false;
13899
13900 if (IS_CHERRYVIEW(dev))
13901 return false;
13902
13903 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
13904 return false;
13905
13906 return true;
13907}
13908
79e53945
JB		 13909static void intel_setup_outputs(struct drm_device *dev)
13910{
725e30ad 13911 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 13912 struct intel_encoder *encoder;
cb0953d7 13913 bool dpd_is_edp = false;
79e53945 13914
c9093354 13915 intel_lvds_init(dev);
79e53945 13916
84b4e042 13917 if (intel_crt_present(dev))
79935fca 13918 intel_crt_init(dev);
cb0953d7 13919
c776eb2e
VK		 13920 if (IS_BROXTON(dev)) {
13921 /*
13922 * FIXME: Broxton doesn't support port detection via the
13923 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
13924 * detect the ports.
13925 */
13926 intel_ddi_init(dev, PORT_A);
13927 intel_ddi_init(dev, PORT_B);
13928 intel_ddi_init(dev, PORT_C);
13929 } else if (HAS_DDI(dev)) {
0e72a5b5
ED		 13930 int found;
13931
de31facd
JB		 13932 /*
13933 * Haswell uses DDI functions to detect digital outputs.
13934 * On SKL pre-D0 the strap isn't connected, so we assume
13935 * it's there.
13936 */
0e72a5b5 13937 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
de31facd
JB		 13938 /* WaIgnoreDDIAStrap: skl */
13939 if (found ||
13940 (IS_SKYLAKE(dev) && INTEL_REVID(dev) < SKL_REVID_D0))
0e72a5b5
ED		 13941 intel_ddi_init(dev, PORT_A);
13942
13943 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
13944 * register */
13945 found = I915_READ(SFUSE_STRAP);
13946
13947 if (found & SFUSE_STRAP_DDIB_DETECTED)
13948 intel_ddi_init(dev, PORT_B);
13949 if (found & SFUSE_STRAP_DDIC_DETECTED)
13950 intel_ddi_init(dev, PORT_C);
13951 if (found & SFUSE_STRAP_DDID_DETECTED)
13952 intel_ddi_init(dev, PORT_D);
13953 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 13954 int found;
5d8a7752 13955 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
270b3042
DV		 13956
13957 if (has_edp_a(dev))
13958 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 13959
dc0fa718 13960 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 13961 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 13962 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 13963 if (!found)
e2debe91 13964 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 13965 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 13966 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 13967 }
13968
dc0fa718 13969 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 13970 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 13971
dc0fa718 13972 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 13973 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 13974
5eb08b69 13975 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 13976 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 13977
270b3042 13978 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 13979 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 13980 } else if (IS_VALLEYVIEW(dev)) {
e17ac6db
VS		 13981 /*
13982 * The DP_DETECTED bit is the latched state of the DDC
13983 * SDA pin at boot. However since eDP doesn't require DDC
13984 * (no way to plug in a DP->HDMI dongle) the DDC pins for
13985 * eDP ports may have been muxed to an alternate function.
13986 * Thus we can't rely on the DP_DETECTED bit alone to detect
13987 * eDP ports. Consult the VBT as well as DP_DETECTED to
13988 * detect eDP ports.
13989 */
d2182a66
VS		 13990 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
13991 !intel_dp_is_edp(dev, PORT_B))
585a94b8
AB		 13992 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
13993 PORT_B);
e17ac6db
VS		 13994 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
13995 intel_dp_is_edp(dev, PORT_B))
13996 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
585a94b8 13997
d2182a66
VS		 13998 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
13999 !intel_dp_is_edp(dev, PORT_C))
6f6005a5
JB		 14000 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
14001 PORT_C);
e17ac6db
VS		 14002 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
14003 intel_dp_is_edp(dev, PORT_C))
14004 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
19c03924 14005
9418c1f1 14006 if (IS_CHERRYVIEW(dev)) {
e17ac6db 14007 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
9418c1f1
VS		 14008 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
14009 PORT_D);
e17ac6db
VS		 14010 /* eDP not supported on port D, so don't check VBT */
14011 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
14012 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
9418c1f1
VS		 14013 }
14014
3cfca973 14015 intel_dsi_init(dev);
103a196f 14016 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 14017 bool found = false;
7d57382e 14018
e2debe91 14019 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 14020 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 14021 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
b01f2c3a
JB		 14022 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
14023 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 14024 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 14025 }
27185ae1 14026
e7281eab 14027 if (!found && SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 14028 intel_dp_init(dev, DP_B, PORT_B);
725e30ad 14029 }
13520b05
KH		 14030
14031 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 14032
e2debe91 14033 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 14034 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 14035 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 14036 }
27185ae1 14037
e2debe91 14038 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 14039
b01f2c3a
JB		 14040 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
14041 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 14042 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a 14043 }
e7281eab 14044 if (SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 14045 intel_dp_init(dev, DP_C, PORT_C);
725e30ad 14046 }
27185ae1 14047
b01f2c3a 14048 if (SUPPORTS_INTEGRATED_DP(dev) &&
e7281eab 14049 (I915_READ(DP_D) & DP_DETECTED))
ab9d7c30 14050 intel_dp_init(dev, DP_D, PORT_D);
bad720ff 14051 } else if (IS_GEN2(dev))
79e53945
JB		 14052 intel_dvo_init(dev);
14053
103a196f 14054 if (SUPPORTS_TV(dev))
79e53945
JB		 14055 intel_tv_init(dev);
14056
0bc12bcb 14057 intel_psr_init(dev);
7c8f8a70 14058
b2784e15 14059 for_each_intel_encoder(dev, encoder) {
4ef69c7a
CW		 14060 encoder->base.possible_crtcs = encoder->crtc_mask;
14061 encoder->base.possible_clones =
66a9278e 14062 intel_encoder_clones(encoder);
79e53945 14063 }
47356eb6 14064
dde86e2d 14065 intel_init_pch_refclk(dev);
270b3042
DV		 14066
14067 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 14068}
14069
14070static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14071{
60a5ca01 14072 struct drm_device *dev = fb->dev;
79e53945 14073 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945 14074
ef2d633e 14075 drm_framebuffer_cleanup(fb);
60a5ca01 14076 mutex_lock(&dev->struct_mutex);
ef2d633e 14077 WARN_ON(!intel_fb->obj->framebuffer_references--);
60a5ca01
VS		 14078 drm_gem_object_unreference(&intel_fb->obj->base);
14079 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 14080 kfree(intel_fb);
14081}
14082
14083static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 14084 struct drm_file *file,
79e53945
JB		 14085 unsigned int *handle)
14086{
14087 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 14088 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 14089
05394f39 14090 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 14091}
14092
14093static const struct drm_framebuffer_funcs intel_fb_funcs = {
14094 .destroy = intel_user_framebuffer_destroy,
14095 .create_handle = intel_user_framebuffer_create_handle,
14096};
14097
b321803d
DL		 14098static
14099u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14100 uint32_t pixel_format)
14101{
14102 u32 gen = INTEL_INFO(dev)->gen;
14103
14104 if (gen >= 9) {
14105 /* "The stride in bytes must not exceed the of the size of 8K
14106 * pixels and 32K bytes."
14107 */
14108 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
14109 } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
14110 return 32*1024;
14111 } else if (gen >= 4) {
14112 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14113 return 16*1024;
14114 else
14115 return 32*1024;
14116 } else if (gen >= 3) {
14117 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14118 return 8*1024;
14119 else
14120 return 16*1024;
14121 } else {
14122 /* XXX DSPC is limited to 4k tiled */
14123 return 8*1024;
14124 }
14125}
14126
b5ea642a
DV		 14127static int intel_framebuffer_init(struct drm_device *dev,
14128 struct intel_framebuffer *intel_fb,
14129 struct drm_mode_fb_cmd2 *mode_cmd,
14130 struct drm_i915_gem_object *obj)
79e53945 14131{
6761dd31 14132 unsigned int aligned_height;
79e53945 14133 int ret;
b321803d 14134 u32 pitch_limit, stride_alignment;
79e53945 14135
dd4916c5
DV		 14136 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14137
2a80eada
DV		 14138 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14139 /* Enforce that fb modifier and tiling mode match, but only for
14140 * X-tiled. This is needed for FBC. */
14141 if (!!(obj->tiling_mode == I915_TILING_X) !=
14142 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14143 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14144 return -EINVAL;
14145 }
14146 } else {
14147 if (obj->tiling_mode == I915_TILING_X)
14148 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14149 else if (obj->tiling_mode == I915_TILING_Y) {
14150 DRM_DEBUG("No Y tiling for legacy addfb\n");
14151 return -EINVAL;
14152 }
14153 }
14154
9a8f0a12
TU		 14155 /* Passed in modifier sanity checking. */
14156 switch (mode_cmd->modifier[0]) {
14157 case I915_FORMAT_MOD_Y_TILED:
14158 case I915_FORMAT_MOD_Yf_TILED:
14159 if (INTEL_INFO(dev)->gen < 9) {
14160 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14161 mode_cmd->modifier[0]);
14162 return -EINVAL;
14163 }
14164 case DRM_FORMAT_MOD_NONE:
14165 case I915_FORMAT_MOD_X_TILED:
14166 break;
14167 default:
c0f40428
JB		 14168 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14169 mode_cmd->modifier[0]);
57cd6508 14170 return -EINVAL;
c16ed4be 14171 }
57cd6508 14172
b321803d
DL		 14173 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
14174 mode_cmd->pixel_format);
14175 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14176 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14177 mode_cmd->pitches[0], stride_alignment);
57cd6508 14178 return -EINVAL;
c16ed4be 14179 }
57cd6508 14180
b321803d
DL		 14181 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14182 mode_cmd->pixel_format);
a35cdaa0 14183 if (mode_cmd->pitches[0] > pitch_limit) {
b321803d
DL		 14184 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14185 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
2a80eada 14186 "tiled" : "linear",
a35cdaa0 14187 mode_cmd->pitches[0], pitch_limit);
5d7bd705 14188 return -EINVAL;
c16ed4be 14189 }
5d7bd705 14190
2a80eada 14191 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
c16ed4be
CW		 14192 mode_cmd->pitches[0] != obj->stride) {
14193 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14194 mode_cmd->pitches[0], obj->stride);
5d7bd705 14195 return -EINVAL;
c16ed4be 14196 }
5d7bd705 14197
57779d06 14198 /* Reject formats not supported by any plane early. */
308e5bcb 14199 switch (mode_cmd->pixel_format) {
57779d06 14200 case DRM_FORMAT_C8:
04b3924d
VS		 14201 case DRM_FORMAT_RGB565:
14202 case DRM_FORMAT_XRGB8888:
14203 case DRM_FORMAT_ARGB8888:
57779d06
VS		 14204 break;
14205 case DRM_FORMAT_XRGB1555:
c16ed4be 14206 if (INTEL_INFO(dev)->gen > 3) {
4ee62c76
VS		 14207 DRM_DEBUG("unsupported pixel format: %s\n",
14208 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14209 return -EINVAL;
c16ed4be 14210 }
57779d06 14211 break;
57779d06 14212 case DRM_FORMAT_ABGR8888:
6c0fd451
DL		 14213 if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) {
14214 DRM_DEBUG("unsupported pixel format: %s\n",
14215 drm_get_format_name(mode_cmd->pixel_format));
14216 return -EINVAL;
14217 }
14218 break;
14219 case DRM_FORMAT_XBGR8888:
04b3924d 14220 case DRM_FORMAT_XRGB2101010:
57779d06 14221 case DRM_FORMAT_XBGR2101010:
c16ed4be 14222 if (INTEL_INFO(dev)->gen < 4) {
4ee62c76
VS		 14223 DRM_DEBUG("unsupported pixel format: %s\n",
14224 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14225 return -EINVAL;
c16ed4be 14226 }
b5626747 14227 break;
7531208b
DL		 14228 case DRM_FORMAT_ABGR2101010:
14229 if (!IS_VALLEYVIEW(dev)) {
14230 DRM_DEBUG("unsupported pixel format: %s\n",
14231 drm_get_format_name(mode_cmd->pixel_format));
14232 return -EINVAL;
14233 }
14234 break;
04b3924d
VS		 14235 case DRM_FORMAT_YUYV:
14236 case DRM_FORMAT_UYVY:
14237 case DRM_FORMAT_YVYU:
14238 case DRM_FORMAT_VYUY:
c16ed4be 14239 if (INTEL_INFO(dev)->gen < 5) {
4ee62c76
VS		 14240 DRM_DEBUG("unsupported pixel format: %s\n",
14241 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14242 return -EINVAL;
c16ed4be 14243 }
57cd6508
CW		 14244 break;
14245 default:
4ee62c76
VS		 14246 DRM_DEBUG("unsupported pixel format: %s\n",
14247 drm_get_format_name(mode_cmd->pixel_format));
57cd6508
CW		 14248 return -EINVAL;
14249 }
14250
90f9a336
VS		 14251 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14252 if (mode_cmd->offsets[0] != 0)
14253 return -EINVAL;
14254
ec2c981e 14255 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
091df6cb
DV		 14256 mode_cmd->pixel_format,
14257 mode_cmd->modifier[0]);
53155c0a
DV		 14258 /* FIXME drm helper for size checks (especially planar formats)? */
14259 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14260 return -EINVAL;
14261
c7d73f6a
DV		 14262 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14263 intel_fb->obj = obj;
80075d49 14264 intel_fb->obj->framebuffer_references++;
c7d73f6a 14265
79e53945
JB		 14266 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14267 if (ret) {
14268 DRM_ERROR("framebuffer init failed %d\n", ret);
14269 return ret;
14270 }
14271
79e53945
JB		 14272 return 0;
14273}
14274
79e53945
JB		 14275static struct drm_framebuffer *
14276intel_user_framebuffer_create(struct drm_device *dev,
14277 struct drm_file *filp,
308e5bcb 14278 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 14279{
05394f39 14280 struct drm_i915_gem_object *obj;
79e53945 14281
308e5bcb
JB		 14282 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14283 mode_cmd->handles[0]));
c8725226 14284 if (&obj->base == NULL)
cce13ff7 14285 return ERR_PTR(-ENOENT);
79e53945 14286
d2dff872 14287 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 14288}
14289
4520f53a 14290#ifndef CONFIG_DRM_I915_FBDEV
0632fef6 14291static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
4520f53a
DV		 14292{
14293}
14294#endif
14295
79e53945 14296static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 14297 .fb_create = intel_user_framebuffer_create,
0632fef6 14298 .output_poll_changed = intel_fbdev_output_poll_changed,
5ee67f1c
MR		 14299 .atomic_check = intel_atomic_check,
14300 .atomic_commit = intel_atomic_commit,
79e53945
JB		 14301};
14302
e70236a8
JB		 14303/* Set up chip specific display functions */
14304static void intel_init_display(struct drm_device *dev)
14305{
14306 struct drm_i915_private *dev_priv = dev->dev_private;
14307
ee9300bb
DV		 14308 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14309 dev_priv->display.find_dpll = g4x_find_best_dpll;
ef9348c8
CML		 14310 else if (IS_CHERRYVIEW(dev))
14311 dev_priv->display.find_dpll = chv_find_best_dpll;
ee9300bb
DV		 14312 else if (IS_VALLEYVIEW(dev))
14313 dev_priv->display.find_dpll = vlv_find_best_dpll;
14314 else if (IS_PINEVIEW(dev))
14315 dev_priv->display.find_dpll = pnv_find_best_dpll;
14316 else
14317 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14318
bc8d7dff
DL		 14319 if (INTEL_INFO(dev)->gen >= 9) {
14320 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
5724dbd1
DL		 14321 dev_priv->display.get_initial_plane_config =
14322 skylake_get_initial_plane_config;
bc8d7dff
DL		 14323 dev_priv->display.crtc_compute_clock =
14324 haswell_crtc_compute_clock;
14325 dev_priv->display.crtc_enable = haswell_crtc_enable;
14326 dev_priv->display.crtc_disable = haswell_crtc_disable;
14327 dev_priv->display.off = ironlake_crtc_off;
14328 dev_priv->display.update_primary_plane =
14329 skylake_update_primary_plane;
14330 } else if (HAS_DDI(dev)) {
0e8ffe1b 14331 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
5724dbd1
DL		 14332 dev_priv->display.get_initial_plane_config =
14333 ironlake_get_initial_plane_config;
797d0259
ACO		 14334 dev_priv->display.crtc_compute_clock =
14335 haswell_crtc_compute_clock;
4f771f10
PZ		 14336 dev_priv->display.crtc_enable = haswell_crtc_enable;
14337 dev_priv->display.crtc_disable = haswell_crtc_disable;
df8ad70c 14338 dev_priv->display.off = ironlake_crtc_off;
bc8d7dff
DL		 14339 dev_priv->display.update_primary_plane =
14340 ironlake_update_primary_plane;
09b4ddf9 14341 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 14342 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
5724dbd1
DL		 14343 dev_priv->display.get_initial_plane_config =
14344 ironlake_get_initial_plane_config;
3fb37703
ACO		 14345 dev_priv->display.crtc_compute_clock =
14346 ironlake_crtc_compute_clock;
76e5a89c
DV		 14347 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14348 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 14349 dev_priv->display.off = ironlake_crtc_off;
262ca2b0
MR		 14350 dev_priv->display.update_primary_plane =
14351 ironlake_update_primary_plane;
89b667f8
JB		 14352 } else if (IS_VALLEYVIEW(dev)) {
14353 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
5724dbd1
DL		 14354 dev_priv->display.get_initial_plane_config =
14355 i9xx_get_initial_plane_config;
d6dfee7a 14356 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
89b667f8
JB		 14357 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14358 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14359 dev_priv->display.off = i9xx_crtc_off;
262ca2b0
MR		 14360 dev_priv->display.update_primary_plane =
14361 i9xx_update_primary_plane;
f564048e 14362 } else {
0e8ffe1b 14363 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
5724dbd1
DL		 14364 dev_priv->display.get_initial_plane_config =
14365 i9xx_get_initial_plane_config;
d6dfee7a 14366 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
76e5a89c
DV		 14367 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14368 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 14369 dev_priv->display.off = i9xx_crtc_off;
262ca2b0
MR		 14370 dev_priv->display.update_primary_plane =
14371 i9xx_update_primary_plane;
f564048e 14372 }
e70236a8 14373
e70236a8 14374 /* Returns the core display clock speed */
1652d19e
VS		 14375 if (IS_SKYLAKE(dev))
14376 dev_priv->display.get_display_clock_speed =
14377 skylake_get_display_clock_speed;
14378 else if (IS_BROADWELL(dev))
14379 dev_priv->display.get_display_clock_speed =
14380 broadwell_get_display_clock_speed;
14381 else if (IS_HASWELL(dev))
14382 dev_priv->display.get_display_clock_speed =
14383 haswell_get_display_clock_speed;
14384 else if (IS_VALLEYVIEW(dev))
25eb05fc
JB		 14385 dev_priv->display.get_display_clock_speed =
14386 valleyview_get_display_clock_speed;
b37a6434
VS		 14387 else if (IS_GEN5(dev))
14388 dev_priv->display.get_display_clock_speed =
14389 ilk_get_display_clock_speed;
a7c66cd8
VS		 14390 else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
14391 IS_GEN6(dev) || IS_IVYBRIDGE(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 14392 dev_priv->display.get_display_clock_speed =
14393 i945_get_display_clock_speed;
14394 else if (IS_I915G(dev))
14395 dev_priv->display.get_display_clock_speed =
14396 i915_get_display_clock_speed;
257a7ffc 14397 else if (IS_I945GM(dev) || IS_845G(dev))
e70236a8
JB		 14398 dev_priv->display.get_display_clock_speed =
14399 i9xx_misc_get_display_clock_speed;
257a7ffc
DV		 14400 else if (IS_PINEVIEW(dev))
14401 dev_priv->display.get_display_clock_speed =
14402 pnv_get_display_clock_speed;
e70236a8
JB		 14403 else if (IS_I915GM(dev))
14404 dev_priv->display.get_display_clock_speed =
14405 i915gm_get_display_clock_speed;
14406 else if (IS_I865G(dev))
14407 dev_priv->display.get_display_clock_speed =
14408 i865_get_display_clock_speed;
f0f8a9ce 14409 else if (IS_I85X(dev))
e70236a8
JB		 14410 dev_priv->display.get_display_clock_speed =
14411 i855_get_display_clock_speed;
14412 else /* 852, 830 */
14413 dev_priv->display.get_display_clock_speed =
14414 i830_get_display_clock_speed;
14415
7c10a2b5 14416 if (IS_GEN5(dev)) {
3bb11b53 14417 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
3bb11b53
SJ		 14418 } else if (IS_GEN6(dev)) {
14419 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
3bb11b53
SJ		 14420 } else if (IS_IVYBRIDGE(dev)) {
14421 /* FIXME: detect B0+ stepping and use auto training */
14422 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
059b2fe9 14423 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
3bb11b53 14424 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
30a970c6
JB		 14425 } else if (IS_VALLEYVIEW(dev)) {
14426 dev_priv->display.modeset_global_resources =
14427 valleyview_modeset_global_resources;
f8437dd1
VK		 14428 } else if (IS_BROXTON(dev)) {
14429 dev_priv->display.modeset_global_resources =
14430 broxton_modeset_global_resources;
e70236a8 14431 }
8c9f3aaf 14432
8c9f3aaf
JB		 14433 switch (INTEL_INFO(dev)->gen) {
14434 case 2:
14435 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14436 break;
14437
14438 case 3:
14439 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14440 break;
14441
14442 case 4:
14443 case 5:
14444 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14445 break;
14446
14447 case 6:
14448 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14449 break;
7c9017e5 14450 case 7:
4e0bbc31 14451 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
7c9017e5
JB		 14452 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14453 break;
830c81db 14454 case 9:
ba343e02
TU		 14455 /* Drop through - unsupported since execlist only. */
14456 default:
14457 /* Default just returns -ENODEV to indicate unsupported */
14458 dev_priv->display.queue_flip = intel_default_queue_flip;
8c9f3aaf 14459 }
7bd688cd
JN		 14460
14461 intel_panel_init_backlight_funcs(dev);
e39b999a
VS		 14462
14463 mutex_init(&dev_priv->pps_mutex);
e70236a8
JB		 14464}
14465
b690e96c
JB		 14466/*
14467 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14468 * resume, or other times. This quirk makes sure that's the case for
14469 * affected systems.
14470 */
0206e353 14471static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 14472{
14473 struct drm_i915_private *dev_priv = dev->dev_private;
14474
14475 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 14476 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 14477}
14478
b6b5d049
VS		 14479static void quirk_pipeb_force(struct drm_device *dev)
14480{
14481 struct drm_i915_private *dev_priv = dev->dev_private;
14482
14483 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14484 DRM_INFO("applying pipe b force quirk\n");
14485}
14486
435793df
KP		 14487/*
14488 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14489 */
14490static void quirk_ssc_force_disable(struct drm_device *dev)
14491{
14492 struct drm_i915_private *dev_priv = dev->dev_private;
14493 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 14494 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 14495}
14496
4dca20ef 14497/*
5a15ab5b
CE		 14498 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14499 * brightness value
4dca20ef
CE		 14500 */
14501static void quirk_invert_brightness(struct drm_device *dev)
14502{
14503 struct drm_i915_private *dev_priv = dev->dev_private;
14504 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 14505 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 14506}
14507
9c72cc6f
SD		 14508/* Some VBT's incorrectly indicate no backlight is present */
14509static void quirk_backlight_present(struct drm_device *dev)
14510{
14511 struct drm_i915_private *dev_priv = dev->dev_private;
14512 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14513 DRM_INFO("applying backlight present quirk\n");
14514}
14515
b690e96c
JB		 14516struct intel_quirk {
14517 int device;
14518 int subsystem_vendor;
14519 int subsystem_device;
14520 void (*hook)(struct drm_device *dev);
14521};
14522
5f85f176
EE		 14523/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14524struct intel_dmi_quirk {
14525 void (*hook)(struct drm_device *dev);
14526 const struct dmi_system_id (*dmi_id_list)[];
14527};
14528
14529static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14530{
14531 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14532 return 1;
14533}
14534
14535static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14536 {
14537 .dmi_id_list = &(const struct dmi_system_id[]) {
14538 {
14539 .callback = intel_dmi_reverse_brightness,
14540 .ident = "NCR Corporation",
14541 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14542 DMI_MATCH(DMI_PRODUCT_NAME, ""),
14543 },
14544 },
14545 { } /* terminating entry */
14546 },
14547 .hook = quirk_invert_brightness,
14548 },
14549};
14550
c43b5634 14551static struct intel_quirk intel_quirks[] = {
b690e96c
JB		 14552 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14553 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14554
b690e96c
JB		 14555 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14556 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14557
5f080c0f
VS		 14558 /* 830 needs to leave pipe A & dpll A up */
14559 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14560
b6b5d049
VS		 14561 /* 830 needs to leave pipe B & dpll B up */
14562 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14563
435793df
KP		 14564 /* Lenovo U160 cannot use SSC on LVDS */
14565 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 14566
14567 /* Sony Vaio Y cannot use SSC on LVDS */
14568 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b 14569
be505f64
AH		 14570 /* Acer Aspire 5734Z must invert backlight brightness */
14571 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14572
14573 /* Acer/eMachines G725 */
14574 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14575
14576 /* Acer/eMachines e725 */
14577 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14578
14579 /* Acer/Packard Bell NCL20 */
14580 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14581
14582 /* Acer Aspire 4736Z */
14583 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
0f540c3a
JN		 14584
14585 /* Acer Aspire 5336 */
14586 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
2e93a1aa
SD		 14587
14588 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14589 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
d4967d8c 14590
dfb3d47b
SD		 14591 /* Acer C720 Chromebook (Core i3 4005U) */
14592 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14593
b2a9601c 14594 /* Apple Macbook 2,1 (Core 2 T7400) */
14595 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14596
d4967d8c
SD		 14597 /* Toshiba CB35 Chromebook (Celeron 2955U) */
14598 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
724cb06f
SD		 14599
14600 /* HP Chromebook 14 (Celeron 2955U) */
14601 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
cf6f0af9
JN		 14602
14603 /* Dell Chromebook 11 */
14604 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
b690e96c
JB		 14605};
14606
14607static void intel_init_quirks(struct drm_device *dev)
14608{
14609 struct pci_dev *d = dev->pdev;
14610 int i;
14611
14612 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14613 struct intel_quirk *q = &intel_quirks[i];
14614
14615 if (d->device == q->device &&
14616 (d->subsystem_vendor == q->subsystem_vendor ||
14617 q->subsystem_vendor == PCI_ANY_ID) &&
14618 (d->subsystem_device == q->subsystem_device ||
14619 q->subsystem_device == PCI_ANY_ID))
14620 q->hook(dev);
14621 }
5f85f176
EE		 14622 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14623 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14624 intel_dmi_quirks[i].hook(dev);
14625 }
b690e96c
JB		 14626}
14627
9cce37f4
JB		 14628/* Disable the VGA plane that we never use */
14629static void i915_disable_vga(struct drm_device *dev)
14630{
14631 struct drm_i915_private *dev_priv = dev->dev_private;
14632 u8 sr1;
766aa1c4 14633 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4 14634
2b37c616 14635 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
9cce37f4 14636 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 14637 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 14638 sr1 = inb(VGA_SR_DATA);
14639 outb(sr1 | 1<<5, VGA_SR_DATA);
14640 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
14641 udelay(300);
14642
01f5a626 14643 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9cce37f4
JB		 14644 POSTING_READ(vga_reg);
14645}
14646
f817586c
DV		 14647void intel_modeset_init_hw(struct drm_device *dev)
14648{
a8f78b58
ED		 14649 intel_prepare_ddi(dev);
14650
f8bf63fd
VS		 14651 if (IS_VALLEYVIEW(dev))
14652 vlv_update_cdclk(dev);
14653
f817586c
DV		 14654 intel_init_clock_gating(dev);
14655
8090c6b9 14656 intel_enable_gt_powersave(dev);
f817586c
DV		 14657}
14658
79e53945
JB		 14659void intel_modeset_init(struct drm_device *dev)
14660{
652c393a 14661 struct drm_i915_private *dev_priv = dev->dev_private;
1fe47785 14662 int sprite, ret;
8cc87b75 14663 enum pipe pipe;
46f297fb 14664 struct intel_crtc *crtc;
79e53945
JB		 14665
14666 drm_mode_config_init(dev);
14667
14668 dev->mode_config.min_width = 0;
14669 dev->mode_config.min_height = 0;
14670
019d96cb
DA		 14671 dev->mode_config.preferred_depth = 24;
14672 dev->mode_config.prefer_shadow = 1;
14673
25bab385
TU		 14674 dev->mode_config.allow_fb_modifiers = true;
14675
e6ecefaa 14676 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 14677
b690e96c
JB		 14678 intel_init_quirks(dev);
14679
1fa61106
ED		 14680 intel_init_pm(dev);
14681
e3c74757
BW		 14682 if (INTEL_INFO(dev)->num_pipes == 0)
14683 return;
14684
e70236a8 14685 intel_init_display(dev);
7c10a2b5 14686 intel_init_audio(dev);
e70236a8 14687
a6c45cf0
CW		 14688 if (IS_GEN2(dev)) {
14689 dev->mode_config.max_width = 2048;
14690 dev->mode_config.max_height = 2048;
14691 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 14692 dev->mode_config.max_width = 4096;
14693 dev->mode_config.max_height = 4096;
79e53945 14694 } else {
a6c45cf0
CW		 14695 dev->mode_config.max_width = 8192;
14696 dev->mode_config.max_height = 8192;
79e53945 14697 }
068be561 14698
dc41c154
VS		 14699 if (IS_845G(dev) || IS_I865G(dev)) {
14700 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
14701 dev->mode_config.cursor_height = 1023;
14702 } else if (IS_GEN2(dev)) {
068be561
DL		 14703 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
14704 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
14705 } else {
14706 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
14707 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
14708 }
14709
5d4545ae 14710 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 14711
28c97730 14712 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 14713 INTEL_INFO(dev)->num_pipes,
14714 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 14715
055e393f 14716 for_each_pipe(dev_priv, pipe) {
8cc87b75 14717 intel_crtc_init(dev, pipe);
3bdcfc0c 14718 for_each_sprite(dev_priv, pipe, sprite) {
1fe47785 14719 ret = intel_plane_init(dev, pipe, sprite);
7f1f3851 14720 if (ret)
06da8da2 14721 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
1fe47785 14722 pipe_name(pipe), sprite_name(pipe, sprite), ret);
7f1f3851 14723 }
79e53945
JB		 14724 }
14725
f42bb70d
JB		 14726 intel_init_dpio(dev);
14727
e72f9fbf 14728 intel_shared_dpll_init(dev);
ee7b9f93 14729
9cce37f4
JB		 14730 /* Just disable it once at startup */
14731 i915_disable_vga(dev);
79e53945 14732 intel_setup_outputs(dev);
11be49eb
CW		 14733
14734 /* Just in case the BIOS is doing something questionable. */
7ff0ebcc 14735 intel_fbc_disable(dev);
fa9fa083 14736
6e9f798d 14737 drm_modeset_lock_all(dev);
fa9fa083 14738 intel_modeset_setup_hw_state(dev, false);
6e9f798d 14739 drm_modeset_unlock_all(dev);
46f297fb 14740
d3fcc808 14741 for_each_intel_crtc(dev, crtc) {
46f297fb
JB		 14742 if (!crtc->active)
14743 continue;
14744
46f297fb 14745 /*
46f297fb
JB		 14746 * Note that reserving the BIOS fb up front prevents us
14747 * from stuffing other stolen allocations like the ring
14748 * on top. This prevents some ugliness at boot time, and
14749 * can even allow for smooth boot transitions if the BIOS
14750 * fb is large enough for the active pipe configuration.
14751 */
5724dbd1
DL		 14752 if (dev_priv->display.get_initial_plane_config) {
14753 dev_priv->display.get_initial_plane_config(crtc,
46f297fb
JB		 14754 &crtc->plane_config);
14755 /*
14756 * If the fb is shared between multiple heads, we'll
14757 * just get the first one.
14758 */
f6936e29 14759 intel_find_initial_plane_obj(crtc, &crtc->plane_config);
46f297fb 14760 }
46f297fb 14761 }
2c7111db
CW		 14762}
14763
7fad798e
DV		 14764static void intel_enable_pipe_a(struct drm_device *dev)
14765{
14766 struct intel_connector *connector;
14767 struct drm_connector *crt = NULL;
14768 struct intel_load_detect_pipe load_detect_temp;
208bf9fd 14769 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
7fad798e
DV		 14770
14771 /* We can't just switch on the pipe A, we need to set things up with a
14772 * proper mode and output configuration. As a gross hack, enable pipe A
14773 * by enabling the load detect pipe once. */
3a3371ff 14774 for_each_intel_connector(dev, connector) {
7fad798e
DV		 14775 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
14776 crt = &connector->base;
14777 break;
14778 }
14779 }
14780
14781 if (!crt)
14782 return;
14783
208bf9fd 14784 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
49172fee 14785 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
7fad798e
DV		 14786}
14787
fa555837
DV		 14788static bool
14789intel_check_plane_mapping(struct intel_crtc *crtc)
14790{
7eb552ae
BW		 14791 struct drm_device *dev = crtc->base.dev;
14792 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 14793 u32 reg, val;
14794
7eb552ae 14795 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 14796 return true;
14797
14798 reg = DSPCNTR(!crtc->plane);
14799 val = I915_READ(reg);
14800
14801 if ((val & DISPLAY_PLANE_ENABLE) &&
14802 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
14803 return false;
14804
14805 return true;
14806}
14807
24929352
DV		 14808static void intel_sanitize_crtc(struct intel_crtc *crtc)
14809{
14810 struct drm_device *dev = crtc->base.dev;
14811 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 14812 u32 reg;
24929352 14813
24929352 14814 /* Clear any frame start delays used for debugging left by the BIOS */
6e3c9717 14815 reg = PIPECONF(crtc->config->cpu_transcoder);
24929352
DV		 14816 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
14817
d3eaf884 14818 /* restore vblank interrupts to correct state */
9625604c 14819 drm_crtc_vblank_reset(&crtc->base);
d297e103
VS		 14820 if (crtc->active) {
14821 update_scanline_offset(crtc);
9625604c
DV		 14822 drm_crtc_vblank_on(&crtc->base);
14823 }
d3eaf884 14824
24929352 14825 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 14826 * disable the crtc (and hence change the state) if it is wrong. Note
14827 * that gen4+ has a fixed plane -> pipe mapping. */
14828 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 14829 struct intel_connector *connector;
14830 bool plane;
14831
24929352
DV		 14832 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
14833 crtc->base.base.id);
14834
14835 /* Pipe has the wrong plane attached and the plane is active.
14836 * Temporarily change the plane mapping and disable everything
14837 * ... */
14838 plane = crtc->plane;
b70709a6 14839 to_intel_plane_state(crtc->base.primary->state)->visible = true;
24929352 14840 crtc->plane = !plane;
ce22dba9 14841 intel_crtc_disable_planes(&crtc->base);
24929352
DV		 14842 dev_priv->display.crtc_disable(&crtc->base);
14843 crtc->plane = plane;
14844
14845 /* ... and break all links. */
3a3371ff 14846 for_each_intel_connector(dev, connector) {
24929352
DV		 14847 if (connector->encoder->base.crtc != &crtc->base)
14848 continue;
14849
7f1950fb
EE		 14850 connector->base.dpms = DRM_MODE_DPMS_OFF;
14851 connector->base.encoder = NULL;
24929352 14852 }
7f1950fb
EE		 14853 /* multiple connectors may have the same encoder:
14854 * handle them and break crtc link separately */
3a3371ff 14855 for_each_intel_connector(dev, connector)
7f1950fb
EE		 14856 if (connector->encoder->base.crtc == &crtc->base) {
14857 connector->encoder->base.crtc = NULL;
14858 connector->encoder->connectors_active = false;
14859 }
24929352
DV		 14860
14861 WARN_ON(crtc->active);
83d65738 14862 crtc->base.state->enable = false;
49d6fa21 14863 crtc->base.state->active = false;
24929352
DV		 14864 crtc->base.enabled = false;
14865 }
24929352 14866
7fad798e
DV		 14867 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
14868 crtc->pipe == PIPE_A && !crtc->active) {
14869 /* BIOS forgot to enable pipe A, this mostly happens after
14870 * resume. Force-enable the pipe to fix this, the update_dpms
14871 * call below we restore the pipe to the right state, but leave
14872 * the required bits on. */
14873 intel_enable_pipe_a(dev);
14874 }
14875
24929352
DV		 14876 /* Adjust the state of the output pipe according to whether we
14877 * have active connectors/encoders. */
14878 intel_crtc_update_dpms(&crtc->base);
14879
83d65738 14880 if (crtc->active != crtc->base.state->enable) {
24929352
DV		 14881 struct intel_encoder *encoder;
14882
14883 /* This can happen either due to bugs in the get_hw_state
14884 * functions or because the pipe is force-enabled due to the
14885 * pipe A quirk. */
14886 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
14887 crtc->base.base.id,
83d65738 14888 crtc->base.state->enable ? "enabled" : "disabled",
24929352
DV		 14889 crtc->active ? "enabled" : "disabled");
14890
83d65738 14891 crtc->base.state->enable = crtc->active;
49d6fa21 14892 crtc->base.state->active = crtc->active;
24929352
DV		 14893 crtc->base.enabled = crtc->active;
14894
14895 /* Because we only establish the connector -> encoder ->
14896 * crtc links if something is active, this means the
14897 * crtc is now deactivated. Break the links. connector
14898 * -> encoder links are only establish when things are
14899 * actually up, hence no need to break them. */
14900 WARN_ON(crtc->active);
14901
14902 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
14903 WARN_ON(encoder->connectors_active);
14904 encoder->base.crtc = NULL;
14905 }
14906 }
c5ab3bc0 14907
a3ed6aad 14908 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
4cc31489
DV		 14909 /*
14910 * We start out with underrun reporting disabled to avoid races.
14911 * For correct bookkeeping mark this on active crtcs.
14912 *
c5ab3bc0
DV		 14913 * Also on gmch platforms we dont have any hardware bits to
14914 * disable the underrun reporting. Which means we need to start
14915 * out with underrun reporting disabled also on inactive pipes,
14916 * since otherwise we'll complain about the garbage we read when
14917 * e.g. coming up after runtime pm.
14918 *
4cc31489
DV		 14919 * No protection against concurrent access is required - at
14920 * worst a fifo underrun happens which also sets this to false.
14921 */
14922 crtc->cpu_fifo_underrun_disabled = true;
14923 crtc->pch_fifo_underrun_disabled = true;
14924 }
24929352
DV		 14925}
14926
14927static void intel_sanitize_encoder(struct intel_encoder *encoder)
14928{
14929 struct intel_connector *connector;
14930 struct drm_device *dev = encoder->base.dev;
14931
14932 /* We need to check both for a crtc link (meaning that the
14933 * encoder is active and trying to read from a pipe) and the
14934 * pipe itself being active. */
14935 bool has_active_crtc = encoder->base.crtc &&
14936 to_intel_crtc(encoder->base.crtc)->active;
14937
14938 if (encoder->connectors_active && !has_active_crtc) {
14939 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
14940 encoder->base.base.id,
8e329a03 14941 encoder->base.name);
24929352
DV		 14942
14943 /* Connector is active, but has no active pipe. This is
14944 * fallout from our resume register restoring. Disable
14945 * the encoder manually again. */
14946 if (encoder->base.crtc) {
14947 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
14948 encoder->base.base.id,
8e329a03 14949 encoder->base.name);
24929352 14950 encoder->disable(encoder);
a62d1497
VS		 14951 if (encoder->post_disable)
14952 encoder->post_disable(encoder);
24929352 14953 }
7f1950fb
EE		 14954 encoder->base.crtc = NULL;
14955 encoder->connectors_active = false;
24929352
DV		 14956
14957 /* Inconsistent output/port/pipe state happens presumably due to
14958 * a bug in one of the get_hw_state functions. Or someplace else
14959 * in our code, like the register restore mess on resume. Clamp
14960 * things to off as a safer default. */
3a3371ff 14961 for_each_intel_connector(dev, connector) {
24929352
DV		 14962 if (connector->encoder != encoder)
14963 continue;
7f1950fb
EE		 14964 connector->base.dpms = DRM_MODE_DPMS_OFF;
14965 connector->base.encoder = NULL;
24929352
DV		 14966 }
14967 }
14968 /* Enabled encoders without active connectors will be fixed in
14969 * the crtc fixup. */
14970}
14971
04098753 14972void i915_redisable_vga_power_on(struct drm_device *dev)
0fde901f
KM		 14973{
14974 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 14975 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f 14976
04098753
ID		 14977 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
14978 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
14979 i915_disable_vga(dev);
14980 }
14981}
14982
14983void i915_redisable_vga(struct drm_device *dev)
14984{
14985 struct drm_i915_private *dev_priv = dev->dev_private;
14986
8dc8a27c
PZ		 14987 /* This function can be called both from intel_modeset_setup_hw_state or
14988 * at a very early point in our resume sequence, where the power well
14989 * structures are not yet restored. Since this function is at a very
14990 * paranoid "someone might have enabled VGA while we were not looking"
14991 * level, just check if the power well is enabled instead of trying to
14992 * follow the "don't touch the power well if we don't need it" policy
14993 * the rest of the driver uses. */
f458ebbc 14994 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
8dc8a27c
PZ		 14995 return;
14996
04098753 14997 i915_redisable_vga_power_on(dev);
0fde901f
KM		 14998}
14999
98ec7739
VS		 15000static bool primary_get_hw_state(struct intel_crtc *crtc)
15001{
15002 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
15003
15004 if (!crtc->active)
15005 return false;
15006
15007 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
15008}
15009
30e984df 15010static void intel_modeset_readout_hw_state(struct drm_device *dev)
24929352
DV		 15011{
15012 struct drm_i915_private *dev_priv = dev->dev_private;
15013 enum pipe pipe;
24929352
DV		 15014 struct intel_crtc *crtc;
15015 struct intel_encoder *encoder;
15016 struct intel_connector *connector;
5358901f 15017 int i;
24929352 15018
d3fcc808 15019 for_each_intel_crtc(dev, crtc) {
b70709a6
ML		 15020 struct drm_plane *primary = crtc->base.primary;
15021 struct intel_plane_state *plane_state;
15022
6e3c9717 15023 memset(crtc->config, 0, sizeof(*crtc->config));
3b117c8f 15024
6e3c9717 15025 crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
9953599b 15026
0e8ffe1b 15027 crtc->active = dev_priv->display.get_pipe_config(crtc,
6e3c9717 15028 crtc->config);
24929352 15029
83d65738 15030 crtc->base.state->enable = crtc->active;
49d6fa21 15031 crtc->base.state->active = crtc->active;
24929352 15032 crtc->base.enabled = crtc->active;
b70709a6
ML		 15033
15034 plane_state = to_intel_plane_state(primary->state);
15035 plane_state->visible = primary_get_hw_state(crtc);
24929352
DV		 15036
15037 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15038 crtc->base.base.id,
15039 crtc->active ? "enabled" : "disabled");
15040 }
15041
5358901f
DV		 15042 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15043 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15044
3e369b76
ACO		 15045 pll->on = pll->get_hw_state(dev_priv, pll,
15046 &pll->config.hw_state);
5358901f 15047 pll->active = 0;
3e369b76 15048 pll->config.crtc_mask = 0;
d3fcc808 15049 for_each_intel_crtc(dev, crtc) {
1e6f2ddc 15050 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
5358901f 15051 pll->active++;
3e369b76 15052 pll->config.crtc_mask |= 1 << crtc->pipe;
1e6f2ddc 15053 }
5358901f 15054 }
5358901f 15055
1e6f2ddc 15056 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
3e369b76 15057 pll->name, pll->config.crtc_mask, pll->on);
bd2bb1b9 15058
3e369b76 15059 if (pll->config.crtc_mask)
bd2bb1b9 15060 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5358901f
DV		 15061 }
15062
b2784e15 15063 for_each_intel_encoder(dev, encoder) {
24929352
DV		 15064 pipe = 0;
15065
15066 if (encoder->get_hw_state(encoder, &pipe)) {
045ac3b5
JB		 15067 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15068 encoder->base.crtc = &crtc->base;
6e3c9717 15069 encoder->get_config(encoder, crtc->config);
24929352
DV		 15070 } else {
15071 encoder->base.crtc = NULL;
15072 }
15073
15074 encoder->connectors_active = false;
6f2bcceb 15075 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
24929352 15076 encoder->base.base.id,
8e329a03 15077 encoder->base.name,
24929352 15078 encoder->base.crtc ? "enabled" : "disabled",
6f2bcceb 15079 pipe_name(pipe));
24929352
DV		 15080 }
15081
3a3371ff 15082 for_each_intel_connector(dev, connector) {
24929352
DV		 15083 if (connector->get_hw_state(connector)) {
15084 connector->base.dpms = DRM_MODE_DPMS_ON;
15085 connector->encoder->connectors_active = true;
15086 connector->base.encoder = &connector->encoder->base;
15087 } else {
15088 connector->base.dpms = DRM_MODE_DPMS_OFF;
15089 connector->base.encoder = NULL;
15090 }
15091 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15092 connector->base.base.id,
c23cc417 15093 connector->base.name,
24929352
DV		 15094 connector->base.encoder ? "enabled" : "disabled");
15095 }
30e984df
DV		 15096}
15097
15098/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
15099 * and i915 state tracking structures. */
15100void intel_modeset_setup_hw_state(struct drm_device *dev,
15101 bool force_restore)
15102{
15103 struct drm_i915_private *dev_priv = dev->dev_private;
15104 enum pipe pipe;
30e984df
DV		 15105 struct intel_crtc *crtc;
15106 struct intel_encoder *encoder;
35c95375 15107 int i;
30e984df
DV		 15108
15109 intel_modeset_readout_hw_state(dev);
24929352 15110
babea61d
JB		 15111 /*
15112 * Now that we have the config, copy it to each CRTC struct
15113 * Note that this could go away if we move to using crtc_config
15114 * checking everywhere.
15115 */
d3fcc808 15116 for_each_intel_crtc(dev, crtc) {
d330a953 15117 if (crtc->active && i915.fastboot) {
6e3c9717
ACO		 15118 intel_mode_from_pipe_config(&crtc->base.mode,
15119 crtc->config);
babea61d
JB		 15120 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
15121 crtc->base.base.id);
15122 drm_mode_debug_printmodeline(&crtc->base.mode);
15123 }
15124 }
15125
24929352 15126 /* HW state is read out, now we need to sanitize this mess. */
b2784e15 15127 for_each_intel_encoder(dev, encoder) {
24929352
DV		 15128 intel_sanitize_encoder(encoder);
15129 }
15130
055e393f 15131 for_each_pipe(dev_priv, pipe) {
24929352
DV		 15132 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15133 intel_sanitize_crtc(crtc);
6e3c9717
ACO		 15134 intel_dump_pipe_config(crtc, crtc->config,
15135 "[setup_hw_state]");
24929352 15136 }
9a935856 15137
d29b2f9d
ACO		 15138 intel_modeset_update_connector_atomic_state(dev);
15139
35c95375
DV		 15140 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15141 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15142
15143 if (!pll->on || pll->active)
15144 continue;
15145
15146 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15147
15148 pll->disable(dev_priv, pll);
15149 pll->on = false;
15150 }
15151
3078999f
PB		 15152 if (IS_GEN9(dev))
15153 skl_wm_get_hw_state(dev);
15154 else if (HAS_PCH_SPLIT(dev))
243e6a44
VS		 15155 ilk_wm_get_hw_state(dev);
15156
45e2b5f6 15157 if (force_restore) {
7d0bc1ea
VS		 15158 i915_redisable_vga(dev);
15159
f30da187
DV		 15160 /*
15161 * We need to use raw interfaces for restoring state to avoid
15162 * checking (bogus) intermediate states.
15163 */
055e393f 15164 for_each_pipe(dev_priv, pipe) {
b5644d05
JB		 15165 struct drm_crtc *crtc =
15166 dev_priv->pipe_to_crtc_mapping[pipe];
f30da187 15167
83a57153 15168 intel_crtc_restore_mode(crtc);
45e2b5f6
DV		 15169 }
15170 } else {
15171 intel_modeset_update_staged_output_state(dev);
15172 }
8af6cf88
DV		 15173
15174 intel_modeset_check_state(dev);
2c7111db
CW		 15175}
15176
15177void intel_modeset_gem_init(struct drm_device *dev)
15178{
92122789 15179 struct drm_i915_private *dev_priv = dev->dev_private;
484b41dd 15180 struct drm_crtc *c;
2ff8fde1 15181 struct drm_i915_gem_object *obj;
e0d6149b 15182 int ret;
484b41dd 15183
ae48434c
ID		 15184 mutex_lock(&dev->struct_mutex);
15185 intel_init_gt_powersave(dev);
15186 mutex_unlock(&dev->struct_mutex);
15187
92122789
JB		 15188 /*
15189 * There may be no VBT; and if the BIOS enabled SSC we can
15190 * just keep using it to avoid unnecessary flicker. Whereas if the
15191 * BIOS isn't using it, don't assume it will work even if the VBT
15192 * indicates as much.
15193 */
15194 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
15195 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15196 DREF_SSC1_ENABLE);
15197
1833b134 15198 intel_modeset_init_hw(dev);
02e792fb
DV		 15199
15200 intel_setup_overlay(dev);
484b41dd
JB		 15201
15202 /*
15203 * Make sure any fbs we allocated at startup are properly
15204 * pinned & fenced. When we do the allocation it's too early
15205 * for this.
15206 */
70e1e0ec 15207 for_each_crtc(dev, c) {
2ff8fde1
MR		 15208 obj = intel_fb_obj(c->primary->fb);
15209 if (obj == NULL)
484b41dd
JB		 15210 continue;
15211
e0d6149b
TU		 15212 mutex_lock(&dev->struct_mutex);
15213 ret = intel_pin_and_fence_fb_obj(c->primary,
15214 c->primary->fb,
15215 c->primary->state,
15216 NULL);
15217 mutex_unlock(&dev->struct_mutex);
15218 if (ret) {
484b41dd
JB		 15219 DRM_ERROR("failed to pin boot fb on pipe %d\n",
15220 to_intel_crtc(c)->pipe);
66e514c1
DA		 15221 drm_framebuffer_unreference(c->primary->fb);
15222 c->primary->fb = NULL;
afd65eb4 15223 update_state_fb(c->primary);
484b41dd
JB		 15224 }
15225 }
0962c3c9
VS		 15226
15227 intel_backlight_register(dev);
79e53945
JB		 15228}
15229
4932e2c3
ID		 15230void intel_connector_unregister(struct intel_connector *intel_connector)
15231{
15232 struct drm_connector *connector = &intel_connector->base;
15233
15234 intel_panel_destroy_backlight(connector);
34ea3d38 15235 drm_connector_unregister(connector);
4932e2c3
ID		 15236}
15237
79e53945
JB		 15238void intel_modeset_cleanup(struct drm_device *dev)
15239{
652c393a 15240 struct drm_i915_private *dev_priv = dev->dev_private;
d9255d57 15241 struct drm_connector *connector;
652c393a 15242
2eb5252e
ID		 15243 intel_disable_gt_powersave(dev);
15244
0962c3c9
VS		 15245 intel_backlight_unregister(dev);
15246
fd0c0642
DV		 15247 /*
15248 * Interrupts and polling as the first thing to avoid creating havoc.
2eb5252e 15249 * Too much stuff here (turning of connectors, ...) would
fd0c0642
DV		 15250 * experience fancy races otherwise.
15251 */
2aeb7d3a 15252 intel_irq_uninstall(dev_priv);
eb21b92b 15253
fd0c0642
DV		 15254 /*
15255 * Due to the hpd irq storm handling the hotplug work can re-arm the
15256 * poll handlers. Hence disable polling after hpd handling is shut down.
15257 */
f87ea761 15258 drm_kms_helper_poll_fini(dev);
fd0c0642 15259
652c393a
JB		 15260 mutex_lock(&dev->struct_mutex);
15261
723bfd70
JB		 15262 intel_unregister_dsm_handler();
15263
7ff0ebcc 15264 intel_fbc_disable(dev);
e70236a8 15265
69341a5e
KH		 15266 mutex_unlock(&dev->struct_mutex);
15267
1630fe75
CW		 15268 /* flush any delayed tasks or pending work */
15269 flush_scheduled_work();
15270
db31af1d
JN		 15271 /* destroy the backlight and sysfs files before encoders/connectors */
15272 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4932e2c3
ID		 15273 struct intel_connector *intel_connector;
15274
15275 intel_connector = to_intel_connector(connector);
15276 intel_connector->unregister(intel_connector);
db31af1d 15277 }
d9255d57 15278
79e53945 15279 drm_mode_config_cleanup(dev);
4d7bb011
DV		 15280
15281 intel_cleanup_overlay(dev);
ae48434c
ID		 15282
15283 mutex_lock(&dev->struct_mutex);
15284 intel_cleanup_gt_powersave(dev);
15285 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 15286}
15287
f1c79df3
ZW		 15288/*
15289 * Return which encoder is currently attached for connector.
15290 */
df0e9248 15291struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 15292{
df0e9248
CW		 15293 return &intel_attached_encoder(connector)->base;
15294}
f1c79df3 15295
df0e9248
CW		 15296void intel_connector_attach_encoder(struct intel_connector *connector,
15297 struct intel_encoder *encoder)
15298{
15299 connector->encoder = encoder;
15300 drm_mode_connector_attach_encoder(&connector->base,
15301 &encoder->base);
79e53945 15302}
28d52043
DA		 15303
15304/*
15305 * set vga decode state - true == enable VGA decode
15306 */
15307int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15308{
15309 struct drm_i915_private *dev_priv = dev->dev_private;
a885b3cc 15310 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
28d52043
DA		 15311 u16 gmch_ctrl;
15312
75fa041d
CW		 15313 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15314 DRM_ERROR("failed to read control word\n");
15315 return -EIO;
15316 }
15317
c0cc8a55
CW		 15318 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15319 return 0;
15320
28d52043
DA		 15321 if (state)
15322 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15323 else
15324 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
75fa041d
CW		 15325
15326 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15327 DRM_ERROR("failed to write control word\n");
15328 return -EIO;
15329 }
15330
28d52043
DA		 15331 return 0;
15332}
c4a1d9e4 15333
c4a1d9e4 15334struct intel_display_error_state {
ff57f1b0
PZ		 15335
15336 u32 power_well_driver;
15337
63b66e5b
CW		 15338 int num_transcoders;
15339
c4a1d9e4
CW		 15340 struct intel_cursor_error_state {
15341 u32 control;
15342 u32 position;
15343 u32 base;
15344 u32 size;
52331309 15345 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 15346
15347 struct intel_pipe_error_state {
ddf9c536 15348 bool power_domain_on;
c4a1d9e4 15349 u32 source;
f301b1e1 15350 u32 stat;
52331309 15351 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 15352
15353 struct intel_plane_error_state {
15354 u32 control;
15355 u32 stride;
15356 u32 size;
15357 u32 pos;
15358 u32 addr;
15359 u32 surface;
15360 u32 tile_offset;
52331309 15361 } plane[I915_MAX_PIPES];
63b66e5b
CW		 15362
15363 struct intel_transcoder_error_state {
ddf9c536 15364 bool power_domain_on;
63b66e5b
CW		 15365 enum transcoder cpu_transcoder;
15366
15367 u32 conf;
15368
15369 u32 htotal;
15370 u32 hblank;
15371 u32 hsync;
15372 u32 vtotal;
15373 u32 vblank;
15374 u32 vsync;
15375 } transcoder[4];
c4a1d9e4
CW		 15376};
15377
15378struct intel_display_error_state *
15379intel_display_capture_error_state(struct drm_device *dev)
15380{
fbee40df 15381 struct drm_i915_private *dev_priv = dev->dev_private;
c4a1d9e4 15382 struct intel_display_error_state *error;
63b66e5b
CW		 15383 int transcoders[] = {
15384 TRANSCODER_A,
15385 TRANSCODER_B,
15386 TRANSCODER_C,
15387 TRANSCODER_EDP,
15388 };
c4a1d9e4
CW		 15389 int i;
15390
63b66e5b
CW		 15391 if (INTEL_INFO(dev)->num_pipes == 0)
15392 return NULL;
15393
9d1cb914 15394 error = kzalloc(sizeof(*error), GFP_ATOMIC);
c4a1d9e4
CW		 15395 if (error == NULL)
15396 return NULL;
15397
190be112 15398 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ff57f1b0
PZ		 15399 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15400
055e393f 15401 for_each_pipe(dev_priv, i) {
ddf9c536 15402 error->pipe[i].power_domain_on =
f458ebbc
DV		 15403 __intel_display_power_is_enabled(dev_priv,
15404 POWER_DOMAIN_PIPE(i));
ddf9c536 15405 if (!error->pipe[i].power_domain_on)
9d1cb914
PZ		 15406 continue;
15407
5efb3e28
VS		 15408 error->cursor[i].control = I915_READ(CURCNTR(i));
15409 error->cursor[i].position = I915_READ(CURPOS(i));
15410 error->cursor[i].base = I915_READ(CURBASE(i));
c4a1d9e4
CW		 15411
15412 error->plane[i].control = I915_READ(DSPCNTR(i));
15413 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 15414 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 15415 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 15416 error->plane[i].pos = I915_READ(DSPPOS(i));
15417 }
ca291363
PZ		 15418 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15419 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 15420 if (INTEL_INFO(dev)->gen >= 4) {
15421 error->plane[i].surface = I915_READ(DSPSURF(i));
15422 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15423 }
15424
c4a1d9e4 15425 error->pipe[i].source = I915_READ(PIPESRC(i));
f301b1e1 15426
3abfce77 15427 if (HAS_GMCH_DISPLAY(dev))
f301b1e1 15428 error->pipe[i].stat = I915_READ(PIPESTAT(i));
63b66e5b
CW		 15429 }
15430
15431 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
15432 if (HAS_DDI(dev_priv->dev))
15433 error->num_transcoders++; /* Account for eDP. */
15434
15435 for (i = 0; i < error->num_transcoders; i++) {
15436 enum transcoder cpu_transcoder = transcoders[i];
15437
ddf9c536 15438 error->transcoder[i].power_domain_on =
f458ebbc 15439 __intel_display_power_is_enabled(dev_priv,
38cc1daf 15440 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
ddf9c536 15441 if (!error->transcoder[i].power_domain_on)
9d1cb914
PZ		 15442 continue;
15443
63b66e5b
CW		 15444 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15445
15446 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15447 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15448 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15449 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15450 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15451 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15452 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 15453 }
15454
15455 return error;
15456}
15457
edc3d884
MK		 15458#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15459
c4a1d9e4 15460void
edc3d884 15461intel_display_print_error_state(struct drm_i915_error_state_buf *m,
c4a1d9e4
CW		 15462 struct drm_device *dev,
15463 struct intel_display_error_state *error)
15464{
055e393f 15465 struct drm_i915_private *dev_priv = dev->dev_private;
c4a1d9e4
CW		 15466 int i;
15467
63b66e5b
CW		 15468 if (!error)
15469 return;
15470
edc3d884 15471 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
190be112 15472 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
edc3d884 15473 err_printf(m, "PWR_WELL_CTL2: %08x\n",
ff57f1b0 15474 error->power_well_driver);
055e393f 15475 for_each_pipe(dev_priv, i) {
edc3d884 15476 err_printf(m, "Pipe [%d]:\n", i);
ddf9c536
ID		 15477 err_printf(m, " Power: %s\n",
15478 error->pipe[i].power_domain_on ? "on" : "off");
edc3d884 15479 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
f301b1e1 15480 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
edc3d884
MK		 15481
15482 err_printf(m, "Plane [%d]:\n", i);
15483 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
15484 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 15485 if (INTEL_INFO(dev)->gen <= 3) {
edc3d884
MK		 15486 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
15487 err_printf(m, " POS: %08x\n", error->plane[i].pos);
80ca378b 15488 }
4b71a570 15489 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
edc3d884 15490 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4 15491 if (INTEL_INFO(dev)->gen >= 4) {
edc3d884
MK		 15492 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
15493 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
c4a1d9e4
CW		 15494 }
15495
edc3d884
MK		 15496 err_printf(m, "Cursor [%d]:\n", i);
15497 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
15498 err_printf(m, " POS: %08x\n", error->cursor[i].position);
15499 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
c4a1d9e4 15500 }
63b66e5b
CW		 15501
15502 for (i = 0; i < error->num_transcoders; i++) {
1cf84bb6 15503 err_printf(m, "CPU transcoder: %c\n",
63b66e5b 15504 transcoder_name(error->transcoder[i].cpu_transcoder));
ddf9c536
ID		 15505 err_printf(m, " Power: %s\n",
15506 error->transcoder[i].power_domain_on ? "on" : "off");
63b66e5b
CW		 15507 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
15508 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
15509 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
15510 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
15511 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
15512 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
15513 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
15514 }
c4a1d9e4 15515}
e2fcdaa9
VS		 15516
15517void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
15518{
15519 struct intel_crtc *crtc;
15520
15521 for_each_intel_crtc(dev, crtc) {
15522 struct intel_unpin_work *work;
e2fcdaa9 15523
5e2d7afc 15524 spin_lock_irq(&dev->event_lock);
e2fcdaa9
VS		 15525
15526 work = crtc->unpin_work;
15527
15528 if (work && work->event &&
15529 work->event->base.file_priv == file) {
15530 kfree(work->event);
15531 work->event = NULL;
15532 }
15533
5e2d7afc 15534 spin_unlock_irq(&dev->event_lock);
e2fcdaa9
VS		 15535 }
15536}
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