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drm/i915: Check live status before reading edid
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
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79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
319c1d42 40#include <drm/drm_atomic.h>
c196e1d6 41#include <drm/drm_atomic_helper.h>
760285e7
DH		 42#include <drm/drm_dp_helper.h>
43#include <drm/drm_crtc_helper.h>
465c120c
MR		 44#include <drm/drm_plane_helper.h>
45#include <drm/drm_rect.h>
c0f372b3 46#include <linux/dma_remapping.h>
79e53945 47
465c120c 48/* Primary plane formats for gen <= 3 */
568db4f2 49static const uint32_t i8xx_primary_formats[] = {
67fe7dc5
DL		 50 DRM_FORMAT_C8,
51 DRM_FORMAT_RGB565,
465c120c 52 DRM_FORMAT_XRGB1555,
67fe7dc5 53 DRM_FORMAT_XRGB8888,
465c120c
MR		 54};
55
56/* Primary plane formats for gen >= 4 */
568db4f2 57static const uint32_t i965_primary_formats[] = {
6c0fd451
DL		 58 DRM_FORMAT_C8,
59 DRM_FORMAT_RGB565,
60 DRM_FORMAT_XRGB8888,
61 DRM_FORMAT_XBGR8888,
62 DRM_FORMAT_XRGB2101010,
63 DRM_FORMAT_XBGR2101010,
64};
65
66static const uint32_t skl_primary_formats[] = {
67fe7dc5
DL		 67 DRM_FORMAT_C8,
68 DRM_FORMAT_RGB565,
69 DRM_FORMAT_XRGB8888,
465c120c 70 DRM_FORMAT_XBGR8888,
67fe7dc5 71 DRM_FORMAT_ARGB8888,
465c120c
MR		 72 DRM_FORMAT_ABGR8888,
73 DRM_FORMAT_XRGB2101010,
465c120c 74 DRM_FORMAT_XBGR2101010,
ea916ea0
KM		 75 DRM_FORMAT_YUYV,
76 DRM_FORMAT_YVYU,
77 DRM_FORMAT_UYVY,
78 DRM_FORMAT_VYUY,
465c120c
MR		 79};
80
3d7d6510
MR		 81/* Cursor formats */
82static const uint32_t intel_cursor_formats[] = {
83 DRM_FORMAT_ARGB8888,
84};
85
6b383a7f 86static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 87
f1f644dc 88static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 89 struct intel_crtc_state *pipe_config);
18442d08 90static void ironlake_pch_clock_get(struct intel_crtc *crtc,
5cec258b 91 struct intel_crtc_state *pipe_config);
f1f644dc 92
eb1bfe80
JB		 93static int intel_framebuffer_init(struct drm_device *dev,
94 struct intel_framebuffer *ifb,
95 struct drm_mode_fb_cmd2 *mode_cmd,
96 struct drm_i915_gem_object *obj);
5b18e57c
DV		 97static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
98static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
29407aab 99static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
f769cd24
VK		 100 struct intel_link_m_n *m_n,
101 struct intel_link_m_n *m2_n2);
29407aab 102static void ironlake_set_pipeconf(struct drm_crtc *crtc);
229fca97
DV		 103static void haswell_set_pipeconf(struct drm_crtc *crtc);
104static void intel_set_pipe_csc(struct drm_crtc *crtc);
d288f65f 105static void vlv_prepare_pll(struct intel_crtc *crtc,
5cec258b 106 const struct intel_crtc_state *pipe_config);
d288f65f 107static void chv_prepare_pll(struct intel_crtc *crtc,
5cec258b 108 const struct intel_crtc_state *pipe_config);
613d2b27
ML		 109static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
110static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
549e2bfb
CK		 111static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
112 struct intel_crtc_state *crtc_state);
5ab7b0b7
ID		 113static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
114 int num_connectors);
bfd16b2a
ML		 115static void skylake_pfit_enable(struct intel_crtc *crtc);
116static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
117static void ironlake_pfit_enable(struct intel_crtc *crtc);
043e9bda 118static void intel_modeset_setup_hw_state(struct drm_device *dev);
e7457a9a 119
79e53945 120typedef struct {
0206e353 121 int min, max;
79e53945
JB		 122} intel_range_t;
123
124typedef struct {
0206e353
AJ		 125 int dot_limit;
126 int p2_slow, p2_fast;
79e53945
JB		 127} intel_p2_t;
128
d4906093
ML		 129typedef struct intel_limit intel_limit_t;
130struct intel_limit {
0206e353
AJ		 131 intel_range_t dot, vco, n, m, m1, m2, p, p1;
132 intel_p2_t p2;
d4906093 133};
79e53945 134
d2acd215
DV		 135int
136intel_pch_rawclk(struct drm_device *dev)
137{
138 struct drm_i915_private *dev_priv = dev->dev_private;
139
140 WARN_ON(!HAS_PCH_SPLIT(dev));
141
142 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
143}
144
79e50a4f
JN		 145/* hrawclock is 1/4 the FSB frequency */
146int intel_hrawclk(struct drm_device *dev)
147{
148 struct drm_i915_private *dev_priv = dev->dev_private;
149 uint32_t clkcfg;
150
151 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
152 if (IS_VALLEYVIEW(dev))
153 return 200;
154
155 clkcfg = I915_READ(CLKCFG);
156 switch (clkcfg & CLKCFG_FSB_MASK) {
157 case CLKCFG_FSB_400:
158 return 100;
159 case CLKCFG_FSB_533:
160 return 133;
161 case CLKCFG_FSB_667:
162 return 166;
163 case CLKCFG_FSB_800:
164 return 200;
165 case CLKCFG_FSB_1067:
166 return 266;
167 case CLKCFG_FSB_1333:
168 return 333;
169 /* these two are just a guess; one of them might be right */
170 case CLKCFG_FSB_1600:
171 case CLKCFG_FSB_1600_ALT:
172 return 400;
173 default:
174 return 133;
175 }
176}
177
021357ac
CW		 178static inline u32 /* units of 100MHz */
179intel_fdi_link_freq(struct drm_device *dev)
180{
8b99e68c
CW		 181 if (IS_GEN5(dev)) {
182 struct drm_i915_private *dev_priv = dev->dev_private;
183 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
184 } else
185 return 27;
021357ac
CW		 186}
187
5d536e28 188static const intel_limit_t intel_limits_i8xx_dac = {
0206e353 189 .dot = { .min = 25000, .max = 350000 },
9c333719 190 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 191 .n = { .min = 2, .max = 16 },
0206e353
AJ		 192 .m = { .min = 96, .max = 140 },
193 .m1 = { .min = 18, .max = 26 },
194 .m2 = { .min = 6, .max = 16 },
195 .p = { .min = 4, .max = 128 },
196 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 197 .p2 = { .dot_limit = 165000,
198 .p2_slow = 4, .p2_fast = 2 },
e4b36699
KP		 199};
200
5d536e28
DV		 201static const intel_limit_t intel_limits_i8xx_dvo = {
202 .dot = { .min = 25000, .max = 350000 },
9c333719 203 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 204 .n = { .min = 2, .max = 16 },
5d536e28
DV		 205 .m = { .min = 96, .max = 140 },
206 .m1 = { .min = 18, .max = 26 },
207 .m2 = { .min = 6, .max = 16 },
208 .p = { .min = 4, .max = 128 },
209 .p1 = { .min = 2, .max = 33 },
210 .p2 = { .dot_limit = 165000,
211 .p2_slow = 4, .p2_fast = 4 },
212};
213
e4b36699 214static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353 215 .dot = { .min = 25000, .max = 350000 },
9c333719 216 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 217 .n = { .min = 2, .max = 16 },
0206e353
AJ		 218 .m = { .min = 96, .max = 140 },
219 .m1 = { .min = 18, .max = 26 },
220 .m2 = { .min = 6, .max = 16 },
221 .p = { .min = 4, .max = 128 },
222 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 223 .p2 = { .dot_limit = 165000,
224 .p2_slow = 14, .p2_fast = 7 },
e4b36699 225};
273e27ca 226
e4b36699 227static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 228 .dot = { .min = 20000, .max = 400000 },
229 .vco = { .min = 1400000, .max = 2800000 },
230 .n = { .min = 1, .max = 6 },
231 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 232 .m1 = { .min = 8, .max = 18 },
233 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 234 .p = { .min = 5, .max = 80 },
235 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 236 .p2 = { .dot_limit = 200000,
237 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 238};
239
240static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 241 .dot = { .min = 20000, .max = 400000 },
242 .vco = { .min = 1400000, .max = 2800000 },
243 .n = { .min = 1, .max = 6 },
244 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 245 .m1 = { .min = 8, .max = 18 },
246 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 247 .p = { .min = 7, .max = 98 },
248 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 249 .p2 = { .dot_limit = 112000,
250 .p2_slow = 14, .p2_fast = 7 },
e4b36699
KP		 251};
252
273e27ca 253
e4b36699 254static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 255 .dot = { .min = 25000, .max = 270000 },
256 .vco = { .min = 1750000, .max = 3500000},
257 .n = { .min = 1, .max = 4 },
258 .m = { .min = 104, .max = 138 },
259 .m1 = { .min = 17, .max = 23 },
260 .m2 = { .min = 5, .max = 11 },
261 .p = { .min = 10, .max = 30 },
262 .p1 = { .min = 1, .max = 3},
263 .p2 = { .dot_limit = 270000,
264 .p2_slow = 10,
265 .p2_fast = 10
044c7c41 266 },
e4b36699
KP		 267};
268
269static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 270 .dot = { .min = 22000, .max = 400000 },
271 .vco = { .min = 1750000, .max = 3500000},
272 .n = { .min = 1, .max = 4 },
273 .m = { .min = 104, .max = 138 },
274 .m1 = { .min = 16, .max = 23 },
275 .m2 = { .min = 5, .max = 11 },
276 .p = { .min = 5, .max = 80 },
277 .p1 = { .min = 1, .max = 8},
278 .p2 = { .dot_limit = 165000,
279 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 280};
281
282static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 283 .dot = { .min = 20000, .max = 115000 },
284 .vco = { .min = 1750000, .max = 3500000 },
285 .n = { .min = 1, .max = 3 },
286 .m = { .min = 104, .max = 138 },
287 .m1 = { .min = 17, .max = 23 },
288 .m2 = { .min = 5, .max = 11 },
289 .p = { .min = 28, .max = 112 },
290 .p1 = { .min = 2, .max = 8 },
291 .p2 = { .dot_limit = 0,
292 .p2_slow = 14, .p2_fast = 14
044c7c41 293 },
e4b36699
KP		 294};
295
296static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 297 .dot = { .min = 80000, .max = 224000 },
298 .vco = { .min = 1750000, .max = 3500000 },
299 .n = { .min = 1, .max = 3 },
300 .m = { .min = 104, .max = 138 },
301 .m1 = { .min = 17, .max = 23 },
302 .m2 = { .min = 5, .max = 11 },
303 .p = { .min = 14, .max = 42 },
304 .p1 = { .min = 2, .max = 6 },
305 .p2 = { .dot_limit = 0,
306 .p2_slow = 7, .p2_fast = 7
044c7c41 307 },
e4b36699
KP		 308};
309
f2b115e6 310static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 311 .dot = { .min = 20000, .max = 400000},
312 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 313 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 314 .n = { .min = 3, .max = 6 },
315 .m = { .min = 2, .max = 256 },
273e27ca 316 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 317 .m1 = { .min = 0, .max = 0 },
318 .m2 = { .min = 0, .max = 254 },
319 .p = { .min = 5, .max = 80 },
320 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 321 .p2 = { .dot_limit = 200000,
322 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 323};
324
f2b115e6 325static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 326 .dot = { .min = 20000, .max = 400000 },
327 .vco = { .min = 1700000, .max = 3500000 },
328 .n = { .min = 3, .max = 6 },
329 .m = { .min = 2, .max = 256 },
330 .m1 = { .min = 0, .max = 0 },
331 .m2 = { .min = 0, .max = 254 },
332 .p = { .min = 7, .max = 112 },
333 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 334 .p2 = { .dot_limit = 112000,
335 .p2_slow = 14, .p2_fast = 14 },
e4b36699
KP		 336};
337
273e27ca
EA		 338/* Ironlake / Sandybridge
339 *
340 * We calculate clock using (register_value + 2) for N/M1/M2, so here
341 * the range value for them is (actual_value - 2).
342 */
b91ad0ec 343static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 344 .dot = { .min = 25000, .max = 350000 },
345 .vco = { .min = 1760000, .max = 3510000 },
346 .n = { .min = 1, .max = 5 },
347 .m = { .min = 79, .max = 127 },
348 .m1 = { .min = 12, .max = 22 },
349 .m2 = { .min = 5, .max = 9 },
350 .p = { .min = 5, .max = 80 },
351 .p1 = { .min = 1, .max = 8 },
352 .p2 = { .dot_limit = 225000,
353 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 354};
355
b91ad0ec 356static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 357 .dot = { .min = 25000, .max = 350000 },
358 .vco = { .min = 1760000, .max = 3510000 },
359 .n = { .min = 1, .max = 3 },
360 .m = { .min = 79, .max = 118 },
361 .m1 = { .min = 12, .max = 22 },
362 .m2 = { .min = 5, .max = 9 },
363 .p = { .min = 28, .max = 112 },
364 .p1 = { .min = 2, .max = 8 },
365 .p2 = { .dot_limit = 225000,
366 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 367};
368
369static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 370 .dot = { .min = 25000, .max = 350000 },
371 .vco = { .min = 1760000, .max = 3510000 },
372 .n = { .min = 1, .max = 3 },
373 .m = { .min = 79, .max = 127 },
374 .m1 = { .min = 12, .max = 22 },
375 .m2 = { .min = 5, .max = 9 },
376 .p = { .min = 14, .max = 56 },
377 .p1 = { .min = 2, .max = 8 },
378 .p2 = { .dot_limit = 225000,
379 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 380};
381
273e27ca 382/* LVDS 100mhz refclk limits. */
b91ad0ec 383static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 384 .dot = { .min = 25000, .max = 350000 },
385 .vco = { .min = 1760000, .max = 3510000 },
386 .n = { .min = 1, .max = 2 },
387 .m = { .min = 79, .max = 126 },
388 .m1 = { .min = 12, .max = 22 },
389 .m2 = { .min = 5, .max = 9 },
390 .p = { .min = 28, .max = 112 },
0206e353 391 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 392 .p2 = { .dot_limit = 225000,
393 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 394};
395
396static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 397 .dot = { .min = 25000, .max = 350000 },
398 .vco = { .min = 1760000, .max = 3510000 },
399 .n = { .min = 1, .max = 3 },
400 .m = { .min = 79, .max = 126 },
401 .m1 = { .min = 12, .max = 22 },
402 .m2 = { .min = 5, .max = 9 },
403 .p = { .min = 14, .max = 42 },
0206e353 404 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 405 .p2 = { .dot_limit = 225000,
406 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 407};
408
dc730512 409static const intel_limit_t intel_limits_vlv = {
f01b7962
VS		 410 /*
411 * These are the data rate limits (measured in fast clocks)
412 * since those are the strictest limits we have. The fast
413 * clock and actual rate limits are more relaxed, so checking
414 * them would make no difference.
415 */
416 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
75e53986 417 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 418 .n = { .min = 1, .max = 7 },
a0c4da24
JB		 419 .m1 = { .min = 2, .max = 3 },
420 .m2 = { .min = 11, .max = 156 },
b99ab663 421 .p1 = { .min = 2, .max = 3 },
5fdc9c49 422 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
a0c4da24
JB		 423};
424
ef9348c8
CML		 425static const intel_limit_t intel_limits_chv = {
426 /*
427 * These are the data rate limits (measured in fast clocks)
428 * since those are the strictest limits we have. The fast
429 * clock and actual rate limits are more relaxed, so checking
430 * them would make no difference.
431 */
432 .dot = { .min = 25000 * 5, .max = 540000 * 5},
17fe1021 433 .vco = { .min = 4800000, .max = 6480000 },
ef9348c8
CML		 434 .n = { .min = 1, .max = 1 },
435 .m1 = { .min = 2, .max = 2 },
436 .m2 = { .min = 24 << 22, .max = 175 << 22 },
437 .p1 = { .min = 2, .max = 4 },
438 .p2 = { .p2_slow = 1, .p2_fast = 14 },
439};
440
5ab7b0b7
ID		 441static const intel_limit_t intel_limits_bxt = {
442 /* FIXME: find real dot limits */
443 .dot = { .min = 0, .max = INT_MAX },
e6292556 444 .vco = { .min = 4800000, .max = 6700000 },
5ab7b0b7
ID		 445 .n = { .min = 1, .max = 1 },
446 .m1 = { .min = 2, .max = 2 },
447 /* FIXME: find real m2 limits */
448 .m2 = { .min = 2 << 22, .max = 255 << 22 },
449 .p1 = { .min = 2, .max = 4 },
450 .p2 = { .p2_slow = 1, .p2_fast = 20 },
451};
452
cdba954e
ACO		 453static bool
454needs_modeset(struct drm_crtc_state *state)
455{
fc596660 456 return drm_atomic_crtc_needs_modeset(state);
cdba954e
ACO		 457}
458
e0638cdf
PZ		 459/**
460 * Returns whether any output on the specified pipe is of the specified type
461 */
4093561b 462bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
e0638cdf 463{
409ee761 464 struct drm_device *dev = crtc->base.dev;
e0638cdf
PZ		 465 struct intel_encoder *encoder;
466
409ee761 467 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
e0638cdf
PZ		 468 if (encoder->type == type)
469 return true;
470
471 return false;
472}
473
d0737e1d
ACO		 474/**
475 * Returns whether any output on the specified pipe will have the specified
476 * type after a staged modeset is complete, i.e., the same as
477 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
478 * encoder->crtc.
479 */
a93e255f
ACO		 480static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
481 int type)
d0737e1d 482{
a93e255f 483 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 484 struct drm_connector *connector;
a93e255f 485 struct drm_connector_state *connector_state;
d0737e1d 486 struct intel_encoder *encoder;
a93e255f
ACO		 487 int i, num_connectors = 0;
488
da3ced29 489 for_each_connector_in_state(state, connector, connector_state, i) {
a93e255f
ACO		 490 if (connector_state->crtc != crtc_state->base.crtc)
491 continue;
492
493 num_connectors++;
d0737e1d 494
a93e255f
ACO		 495 encoder = to_intel_encoder(connector_state->best_encoder);
496 if (encoder->type == type)
d0737e1d 497 return true;
a93e255f
ACO		 498 }
499
500 WARN_ON(num_connectors == 0);
d0737e1d
ACO		 501
502 return false;
503}
504
a93e255f
ACO		 505static const intel_limit_t *
506intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
2c07245f 507{
a93e255f 508 struct drm_device *dev = crtc_state->base.crtc->dev;
2c07245f 509 const intel_limit_t *limit;
b91ad0ec 510
a93e255f 511 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 512 if (intel_is_dual_link_lvds(dev)) {
1b894b59 513 if (refclk == 100000)
b91ad0ec
ZW		 514 limit = &intel_limits_ironlake_dual_lvds_100m;
515 else
516 limit = &intel_limits_ironlake_dual_lvds;
517 } else {
1b894b59 518 if (refclk == 100000)
b91ad0ec
ZW		 519 limit = &intel_limits_ironlake_single_lvds_100m;
520 else
521 limit = &intel_limits_ironlake_single_lvds;
522 }
c6bb3538 523 } else
b91ad0ec 524 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 525
526 return limit;
527}
528
a93e255f
ACO		 529static const intel_limit_t *
530intel_g4x_limit(struct intel_crtc_state *crtc_state)
044c7c41 531{
a93e255f 532 struct drm_device *dev = crtc_state->base.crtc->dev;
044c7c41
ML		 533 const intel_limit_t *limit;
534
a93e255f 535 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 536 if (intel_is_dual_link_lvds(dev))
e4b36699 537 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 538 else
e4b36699 539 limit = &intel_limits_g4x_single_channel_lvds;
a93e255f
ACO		 540 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
541 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
e4b36699 542 limit = &intel_limits_g4x_hdmi;
a93e255f 543 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
e4b36699 544 limit = &intel_limits_g4x_sdvo;
044c7c41 545 } else /* The option is for other outputs */
e4b36699 546 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 547
548 return limit;
549}
550
a93e255f
ACO		 551static const intel_limit_t *
552intel_limit(struct intel_crtc_state *crtc_state, int refclk)
79e53945 553{
a93e255f 554 struct drm_device *dev = crtc_state->base.crtc->dev;
79e53945
JB		 555 const intel_limit_t *limit;
556
5ab7b0b7
ID		 557 if (IS_BROXTON(dev))
558 limit = &intel_limits_bxt;
559 else if (HAS_PCH_SPLIT(dev))
a93e255f 560 limit = intel_ironlake_limit(crtc_state, refclk);
2c07245f 561 else if (IS_G4X(dev)) {
a93e255f 562 limit = intel_g4x_limit(crtc_state);
f2b115e6 563 } else if (IS_PINEVIEW(dev)) {
a93e255f 564 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
f2b115e6 565 limit = &intel_limits_pineview_lvds;
2177832f 566 else
f2b115e6 567 limit = &intel_limits_pineview_sdvo;
ef9348c8
CML		 568 } else if (IS_CHERRYVIEW(dev)) {
569 limit = &intel_limits_chv;
a0c4da24 570 } else if (IS_VALLEYVIEW(dev)) {
dc730512 571 limit = &intel_limits_vlv;
a6c45cf0 572 } else if (!IS_GEN2(dev)) {
a93e255f 573 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
a6c45cf0
CW		 574 limit = &intel_limits_i9xx_lvds;
575 else
576 limit = &intel_limits_i9xx_sdvo;
79e53945 577 } else {
a93e255f 578 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
e4b36699 579 limit = &intel_limits_i8xx_lvds;
a93e255f 580 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
e4b36699 581 limit = &intel_limits_i8xx_dvo;
5d536e28
DV		 582 else
583 limit = &intel_limits_i8xx_dac;
79e53945
JB		 584 }
585 return limit;
586}
587
dccbea3b
ID		 588/*
589 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
590 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
591 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
592 * The helpers' return value is the rate of the clock that is fed to the
593 * display engine's pipe which can be the above fast dot clock rate or a
594 * divided-down version of it.
595 */
f2b115e6 596/* m1 is reserved as 0 in Pineview, n is a ring counter */
dccbea3b 597static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock)
79e53945 598{
2177832f
SL		 599 clock->m = clock->m2 + 2;
600 clock->p = clock->p1 * clock->p2;
ed5ca77e 601 if (WARN_ON(clock->n == 0 || clock->p == 0))
dccbea3b 602 return 0;
fb03ac01
VS		 603 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
604 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
dccbea3b
ID		 605
606 return clock->dot;
2177832f
SL		 607}
608
7429e9d4
DV		 609static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
610{
611 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
612}
613
dccbea3b 614static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock)
2177832f 615{
7429e9d4 616 clock->m = i9xx_dpll_compute_m(clock);
79e53945 617 clock->p = clock->p1 * clock->p2;
ed5ca77e 618 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
dccbea3b 619 return 0;
fb03ac01
VS		 620 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
621 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
dccbea3b
ID		 622
623 return clock->dot;
79e53945
JB		 624}
625
dccbea3b 626static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock)
589eca67
ID		 627{
628 clock->m = clock->m1 * clock->m2;
629 clock->p = clock->p1 * clock->p2;
630 if (WARN_ON(clock->n == 0 || clock->p == 0))
dccbea3b 631 return 0;
589eca67
ID		 632 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
633 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
dccbea3b
ID		 634
635 return clock->dot / 5;
589eca67
ID		 636}
637
dccbea3b 638int chv_calc_dpll_params(int refclk, intel_clock_t *clock)
ef9348c8
CML		 639{
640 clock->m = clock->m1 * clock->m2;
641 clock->p = clock->p1 * clock->p2;
642 if (WARN_ON(clock->n == 0 || clock->p == 0))
dccbea3b 643 return 0;
ef9348c8
CML		 644 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
645 clock->n << 22);
646 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
dccbea3b
ID		 647
648 return clock->dot / 5;
ef9348c8
CML		 649}
650
7c04d1d9 651#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 652/**
653 * Returns whether the given set of divisors are valid for a given refclk with
654 * the given connectors.
655 */
656
1b894b59
CW		 657static bool intel_PLL_is_valid(struct drm_device *dev,
658 const intel_limit_t *limit,
659 const intel_clock_t *clock)
79e53945 660{
f01b7962
VS		 661 if (clock->n < limit->n.min || limit->n.max < clock->n)
662 INTELPllInvalid("n out of range\n");
79e53945 663 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 664 INTELPllInvalid("p1 out of range\n");
79e53945 665 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 666 INTELPllInvalid("m2 out of range\n");
79e53945 667 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 668 INTELPllInvalid("m1 out of range\n");
f01b7962 669
5ab7b0b7 670 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
f01b7962
VS		 671 if (clock->m1 <= clock->m2)
672 INTELPllInvalid("m1 <= m2\n");
673
5ab7b0b7 674 if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
f01b7962
VS		 675 if (clock->p < limit->p.min || limit->p.max < clock->p)
676 INTELPllInvalid("p out of range\n");
677 if (clock->m < limit->m.min || limit->m.max < clock->m)
678 INTELPllInvalid("m out of range\n");
679 }
680
79e53945 681 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 682 INTELPllInvalid("vco out of range\n");
79e53945
JB		 683 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
684 * connector, etc., rather than just a single range.
685 */
686 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 687 INTELPllInvalid("dot out of range\n");
79e53945
JB		 688
689 return true;
690}
691
3b1429d9
VS		 692static int
693i9xx_select_p2_div(const intel_limit_t *limit,
694 const struct intel_crtc_state *crtc_state,
695 int target)
79e53945 696{
3b1429d9 697 struct drm_device *dev = crtc_state->base.crtc->dev;
79e53945 698
a93e255f 699 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
79e53945 700 /*
a210b028
DV		 701 * For LVDS just rely on its current settings for dual-channel.
702 * We haven't figured out how to reliably set up different
703 * single/dual channel state, if we even can.
79e53945 704 */
1974cad0 705 if (intel_is_dual_link_lvds(dev))
3b1429d9 706 return limit->p2.p2_fast;
79e53945 707 else
3b1429d9 708 return limit->p2.p2_slow;
79e53945
JB		 709 } else {
710 if (target < limit->p2.dot_limit)
3b1429d9 711 return limit->p2.p2_slow;
79e53945 712 else
3b1429d9 713 return limit->p2.p2_fast;
79e53945 714 }
3b1429d9
VS		 715}
716
717static bool
718i9xx_find_best_dpll(const intel_limit_t *limit,
719 struct intel_crtc_state *crtc_state,
720 int target, int refclk, intel_clock_t *match_clock,
721 intel_clock_t *best_clock)
722{
723 struct drm_device *dev = crtc_state->base.crtc->dev;
724 intel_clock_t clock;
725 int err = target;
79e53945 726
0206e353 727 memset(best_clock, 0, sizeof(*best_clock));
79e53945 728
3b1429d9
VS		 729 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
730
42158660
ZY		 731 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
732 clock.m1++) {
733 for (clock.m2 = limit->m2.min;
734 clock.m2 <= limit->m2.max; clock.m2++) {
c0efc387 735 if (clock.m2 >= clock.m1)
42158660
ZY		 736 break;
737 for (clock.n = limit->n.min;
738 clock.n <= limit->n.max; clock.n++) {
739 for (clock.p1 = limit->p1.min;
740 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 741 int this_err;
742
dccbea3b 743 i9xx_calc_dpll_params(refclk, &clock);
ac58c3f0
DV		 744 if (!intel_PLL_is_valid(dev, limit,
745 &clock))
746 continue;
747 if (match_clock &&
748 clock.p != match_clock->p)
749 continue;
750
751 this_err = abs(clock.dot - target);
752 if (this_err < err) {
753 *best_clock = clock;
754 err = this_err;
755 }
756 }
757 }
758 }
759 }
760
761 return (err != target);
762}
763
764static bool
a93e255f
ACO		 765pnv_find_best_dpll(const intel_limit_t *limit,
766 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 767 int target, int refclk, intel_clock_t *match_clock,
768 intel_clock_t *best_clock)
79e53945 769{
3b1429d9 770 struct drm_device *dev = crtc_state->base.crtc->dev;
79e53945 771 intel_clock_t clock;
79e53945
JB		 772 int err = target;
773
0206e353 774 memset(best_clock, 0, sizeof(*best_clock));
79e53945 775
3b1429d9
VS		 776 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
777
42158660
ZY		 778 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
779 clock.m1++) {
780 for (clock.m2 = limit->m2.min;
781 clock.m2 <= limit->m2.max; clock.m2++) {
42158660
ZY		 782 for (clock.n = limit->n.min;
783 clock.n <= limit->n.max; clock.n++) {
784 for (clock.p1 = limit->p1.min;
785 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 786 int this_err;
787
dccbea3b 788 pnv_calc_dpll_params(refclk, &clock);
1b894b59
CW		 789 if (!intel_PLL_is_valid(dev, limit,
790 &clock))
79e53945 791 continue;
cec2f356
SP		 792 if (match_clock &&
793 clock.p != match_clock->p)
794 continue;
79e53945
JB		 795
796 this_err = abs(clock.dot - target);
797 if (this_err < err) {
798 *best_clock = clock;
799 err = this_err;
800 }
801 }
802 }
803 }
804 }
805
806 return (err != target);
807}
808
d4906093 809static bool
a93e255f
ACO		 810g4x_find_best_dpll(const intel_limit_t *limit,
811 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 812 int target, int refclk, intel_clock_t *match_clock,
813 intel_clock_t *best_clock)
d4906093 814{
3b1429d9 815 struct drm_device *dev = crtc_state->base.crtc->dev;
d4906093
ML		 816 intel_clock_t clock;
817 int max_n;
3b1429d9 818 bool found = false;
6ba770dc
AJ		 819 /* approximately equals target * 0.00585 */
820 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 821
822 memset(best_clock, 0, sizeof(*best_clock));
3b1429d9
VS		 823
824 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
825
d4906093 826 max_n = limit->n.max;
f77f13e2 827 /* based on hardware requirement, prefer smaller n to precision */
d4906093 828 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 829 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 830 for (clock.m1 = limit->m1.max;
831 clock.m1 >= limit->m1.min; clock.m1--) {
832 for (clock.m2 = limit->m2.max;
833 clock.m2 >= limit->m2.min; clock.m2--) {
834 for (clock.p1 = limit->p1.max;
835 clock.p1 >= limit->p1.min; clock.p1--) {
836 int this_err;
837
dccbea3b 838 i9xx_calc_dpll_params(refclk, &clock);
1b894b59
CW		 839 if (!intel_PLL_is_valid(dev, limit,
840 &clock))
d4906093 841 continue;
1b894b59
CW		 842
843 this_err = abs(clock.dot - target);
d4906093
ML		 844 if (this_err < err_most) {
845 *best_clock = clock;
846 err_most = this_err;
847 max_n = clock.n;
848 found = true;
849 }
850 }
851 }
852 }
853 }
2c07245f
ZW		 854 return found;
855}
856
d5dd62bd
ID		 857/*
858 * Check if the calculated PLL configuration is more optimal compared to the
859 * best configuration and error found so far. Return the calculated error.
860 */
861static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
862 const intel_clock_t *calculated_clock,
863 const intel_clock_t *best_clock,
864 unsigned int best_error_ppm,
865 unsigned int *error_ppm)
866{
9ca3ba01
ID		 867 /*
868 * For CHV ignore the error and consider only the P value.
869 * Prefer a bigger P value based on HW requirements.
870 */
871 if (IS_CHERRYVIEW(dev)) {
872 *error_ppm = 0;
873
874 return calculated_clock->p > best_clock->p;
875 }
876
24be4e46
ID		 877 if (WARN_ON_ONCE(!target_freq))
878 return false;
879
d5dd62bd
ID		 880 *error_ppm = div_u64(1000000ULL *
881 abs(target_freq - calculated_clock->dot),
882 target_freq);
883 /*
884 * Prefer a better P value over a better (smaller) error if the error
885 * is small. Ensure this preference for future configurations too by
886 * setting the error to 0.
887 */
888 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
889 *error_ppm = 0;
890
891 return true;
892 }
893
894 return *error_ppm + 10 < best_error_ppm;
895}
896
a0c4da24 897static bool
a93e255f
ACO		 898vlv_find_best_dpll(const intel_limit_t *limit,
899 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 900 int target, int refclk, intel_clock_t *match_clock,
901 intel_clock_t *best_clock)
a0c4da24 902{
a93e255f 903 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 904 struct drm_device *dev = crtc->base.dev;
6b4bf1c4 905 intel_clock_t clock;
69e4f900 906 unsigned int bestppm = 1000000;
27e639bf
VS		 907 /* min update 19.2 MHz */
908 int max_n = min(limit->n.max, refclk / 19200);
49e497ef 909 bool found = false;
a0c4da24 910
6b4bf1c4
VS		 911 target *= 5; /* fast clock */
912
913 memset(best_clock, 0, sizeof(*best_clock));
a0c4da24
JB		 914
915 /* based on hardware requirement, prefer smaller n to precision */
27e639bf 916 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
811bbf05 917 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
889059d8 918 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
c1a9ae43 919 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
6b4bf1c4 920 clock.p = clock.p1 * clock.p2;
a0c4da24 921 /* based on hardware requirement, prefer bigger m1,m2 values */
6b4bf1c4 922 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
d5dd62bd 923 unsigned int ppm;
69e4f900 924
6b4bf1c4
VS		 925 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
926 refclk * clock.m1);
927
dccbea3b 928 vlv_calc_dpll_params(refclk, &clock);
43b0ac53 929
f01b7962
VS		 930 if (!intel_PLL_is_valid(dev, limit,
931 &clock))
43b0ac53
VS		 932 continue;
933
d5dd62bd
ID		 934 if (!vlv_PLL_is_optimal(dev, target,
935 &clock,
936 best_clock,
937 bestppm, &ppm))
938 continue;
6b4bf1c4 939
d5dd62bd
ID		 940 *best_clock = clock;
941 bestppm = ppm;
942 found = true;
a0c4da24
JB		 943 }
944 }
945 }
946 }
a0c4da24 947
49e497ef 948 return found;
a0c4da24 949}
a4fc5ed6 950
ef9348c8 951static bool
a93e255f
ACO		 952chv_find_best_dpll(const intel_limit_t *limit,
953 struct intel_crtc_state *crtc_state,
ef9348c8
CML		 954 int target, int refclk, intel_clock_t *match_clock,
955 intel_clock_t *best_clock)
956{
a93e255f 957 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 958 struct drm_device *dev = crtc->base.dev;
9ca3ba01 959 unsigned int best_error_ppm;
ef9348c8
CML		 960 intel_clock_t clock;
961 uint64_t m2;
962 int found = false;
963
964 memset(best_clock, 0, sizeof(*best_clock));
9ca3ba01 965 best_error_ppm = 1000000;
ef9348c8
CML		 966
967 /*
968 * Based on hardware doc, the n always set to 1, and m1 always
969 * set to 2. If requires to support 200Mhz refclk, we need to
970 * revisit this because n may not 1 anymore.
971 */
972 clock.n = 1, clock.m1 = 2;
973 target *= 5; /* fast clock */
974
975 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
976 for (clock.p2 = limit->p2.p2_fast;
977 clock.p2 >= limit->p2.p2_slow;
978 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
9ca3ba01 979 unsigned int error_ppm;
ef9348c8
CML		 980
981 clock.p = clock.p1 * clock.p2;
982
983 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
984 clock.n) << 22, refclk * clock.m1);
985
986 if (m2 > INT_MAX/clock.m1)
987 continue;
988
989 clock.m2 = m2;
990
dccbea3b 991 chv_calc_dpll_params(refclk, &clock);
ef9348c8
CML		 992
993 if (!intel_PLL_is_valid(dev, limit, &clock))
994 continue;
995
9ca3ba01
ID		 996 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
997 best_error_ppm, &error_ppm))
998 continue;
999
1000 *best_clock = clock;
1001 best_error_ppm = error_ppm;
1002 found = true;
ef9348c8
CML		 1003 }
1004 }
1005
1006 return found;
1007}
1008
5ab7b0b7
ID		 1009bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1010 intel_clock_t *best_clock)
1011{
1012 int refclk = i9xx_get_refclk(crtc_state, 0);
1013
1014 return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
1015 target_clock, refclk, NULL, best_clock);
1016}
1017
20ddf665
VS		 1018bool intel_crtc_active(struct drm_crtc *crtc)
1019{
1020 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1021
1022 /* Be paranoid as we can arrive here with only partial
1023 * state retrieved from the hardware during setup.
1024 *
241bfc38 1025 * We can ditch the adjusted_mode.crtc_clock check as soon
20ddf665
VS		 1026 * as Haswell has gained clock readout/fastboot support.
1027 *
66e514c1 1028 * We can ditch the crtc->primary->fb check as soon as we can
20ddf665 1029 * properly reconstruct framebuffers.
c3d1f436
MR		 1030 *
1031 * FIXME: The intel_crtc->active here should be switched to
1032 * crtc->state->active once we have proper CRTC states wired up
1033 * for atomic.
20ddf665 1034 */
c3d1f436 1035 return intel_crtc->active && crtc->primary->state->fb &&
6e3c9717 1036 intel_crtc->config->base.adjusted_mode.crtc_clock;
20ddf665
VS		 1037}
1038
a5c961d1
PZ		 1039enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1040 enum pipe pipe)
1041{
1042 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1043 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1044
6e3c9717 1045 return intel_crtc->config->cpu_transcoder;
a5c961d1
PZ		 1046}
1047
fbf49ea2
VS		 1048static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1049{
1050 struct drm_i915_private *dev_priv = dev->dev_private;
1051 u32 reg = PIPEDSL(pipe);
1052 u32 line1, line2;
1053 u32 line_mask;
1054
1055 if (IS_GEN2(dev))
1056 line_mask = DSL_LINEMASK_GEN2;
1057 else
1058 line_mask = DSL_LINEMASK_GEN3;
1059
1060 line1 = I915_READ(reg) & line_mask;
6adfb1ef 1061 msleep(5);
fbf49ea2
VS		 1062 line2 = I915_READ(reg) & line_mask;
1063
1064 return line1 == line2;
1065}
1066
ab7ad7f6
KP		 1067/*
1068 * intel_wait_for_pipe_off - wait for pipe to turn off
575f7ab7 1069 * @crtc: crtc whose pipe to wait for
9d0498a2
JB		 1070 *
1071 * After disabling a pipe, we can't wait for vblank in the usual way,
1072 * spinning on the vblank interrupt status bit, since we won't actually
1073 * see an interrupt when the pipe is disabled.
1074 *
ab7ad7f6
KP		 1075 * On Gen4 and above:
1076 * wait for the pipe register state bit to turn off
1077 *
1078 * Otherwise:
1079 * wait for the display line value to settle (it usually
1080 * ends up stopping at the start of the next frame).
58e10eb9 1081 *
9d0498a2 1082 */
575f7ab7 1083static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
9d0498a2 1084{
575f7ab7 1085 struct drm_device *dev = crtc->base.dev;
9d0498a2 1086 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 1087 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
575f7ab7 1088 enum pipe pipe = crtc->pipe;
ab7ad7f6
KP		 1089
1090 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 1091 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 1092
1093 /* Wait for the Pipe State to go off */
58e10eb9
CW		 1094 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1095 100))
284637d9 1096 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1097 } else {
ab7ad7f6 1098 /* Wait for the display line to settle */
fbf49ea2 1099 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
284637d9 1100 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1101 }
79e53945
JB		 1102}
1103
b24e7179
JB		 1104static const char *state_string(bool enabled)
1105{
1106 return enabled ? "on" : "off";
1107}
1108
1109/* Only for pre-ILK configs */
55607e8a
DV		 1110void assert_pll(struct drm_i915_private *dev_priv,
1111 enum pipe pipe, bool state)
b24e7179
JB		 1112{
1113 int reg;
1114 u32 val;
1115 bool cur_state;
1116
1117 reg = DPLL(pipe);
1118 val = I915_READ(reg);
1119 cur_state = !!(val & DPLL_VCO_ENABLE);
e2c719b7 1120 I915_STATE_WARN(cur_state != state,
b24e7179
JB		 1121 "PLL state assertion failure (expected %s, current %s)\n",
1122 state_string(state), state_string(cur_state));
1123}
b24e7179 1124
23538ef1
JN		 1125/* XXX: the dsi pll is shared between MIPI DSI ports */
1126static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1127{
1128 u32 val;
1129 bool cur_state;
1130
a580516d 1131 mutex_lock(&dev_priv->sb_lock);
23538ef1 1132 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
a580516d 1133 mutex_unlock(&dev_priv->sb_lock);
23538ef1
JN		 1134
1135 cur_state = val & DSI_PLL_VCO_EN;
e2c719b7 1136 I915_STATE_WARN(cur_state != state,
23538ef1
JN		 1137 "DSI PLL state assertion failure (expected %s, current %s)\n",
1138 state_string(state), state_string(cur_state));
1139}
1140#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1141#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1142
55607e8a 1143struct intel_shared_dpll *
e2b78267
DV		 1144intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1145{
1146 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1147
6e3c9717 1148 if (crtc->config->shared_dpll < 0)
e2b78267
DV		 1149 return NULL;
1150
6e3c9717 1151 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
e2b78267
DV		 1152}
1153
040484af 1154/* For ILK+ */
55607e8a
DV		 1155void assert_shared_dpll(struct drm_i915_private *dev_priv,
1156 struct intel_shared_dpll *pll,
1157 bool state)
040484af 1158{
040484af 1159 bool cur_state;
5358901f 1160 struct intel_dpll_hw_state hw_state;
040484af 1161
92b27b08 1162 if (WARN (!pll,
46edb027 1163 "asserting DPLL %s with no DPLL\n", state_string(state)))
ee7b9f93 1164 return;
ee7b9f93 1165
5358901f 1166 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
e2c719b7 1167 I915_STATE_WARN(cur_state != state,
5358901f
DV		 1168 "%s assertion failure (expected %s, current %s)\n",
1169 pll->name, state_string(state), state_string(cur_state));
040484af 1170}
040484af
JB		 1171
1172static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1173 enum pipe pipe, bool state)
1174{
1175 int reg;
1176 u32 val;
1177 bool cur_state;
ad80a810
PZ		 1178 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1179 pipe);
040484af 1180
affa9354
PZ		 1181 if (HAS_DDI(dev_priv->dev)) {
1182 /* DDI does not have a specific FDI_TX register */
ad80a810 1183 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 1184 val = I915_READ(reg);
ad80a810 1185 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 1186 } else {
1187 reg = FDI_TX_CTL(pipe);
1188 val = I915_READ(reg);
1189 cur_state = !!(val & FDI_TX_ENABLE);
1190 }
e2c719b7 1191 I915_STATE_WARN(cur_state != state,
040484af
JB		 1192 "FDI TX state assertion failure (expected %s, current %s)\n",
1193 state_string(state), state_string(cur_state));
1194}
1195#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1196#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1197
1198static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1199 enum pipe pipe, bool state)
1200{
1201 int reg;
1202 u32 val;
1203 bool cur_state;
1204
d63fa0dc
PZ		 1205 reg = FDI_RX_CTL(pipe);
1206 val = I915_READ(reg);
1207 cur_state = !!(val & FDI_RX_ENABLE);
e2c719b7 1208 I915_STATE_WARN(cur_state != state,
040484af
JB		 1209 "FDI RX state assertion failure (expected %s, current %s)\n",
1210 state_string(state), state_string(cur_state));
1211}
1212#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1213#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1214
1215static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1216 enum pipe pipe)
1217{
1218 int reg;
1219 u32 val;
1220
1221 /* ILK FDI PLL is always enabled */
3d13ef2e 1222 if (INTEL_INFO(dev_priv->dev)->gen == 5)
040484af
JB		 1223 return;
1224
bf507ef7 1225 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1226 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1227 return;
1228
040484af
JB		 1229 reg = FDI_TX_CTL(pipe);
1230 val = I915_READ(reg);
e2c719b7 1231 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
040484af
JB		 1232}
1233
55607e8a
DV		 1234void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1235 enum pipe pipe, bool state)
040484af
JB		 1236{
1237 int reg;
1238 u32 val;
55607e8a 1239 bool cur_state;
040484af
JB		 1240
1241 reg = FDI_RX_CTL(pipe);
1242 val = I915_READ(reg);
55607e8a 1243 cur_state = !!(val & FDI_RX_PLL_ENABLE);
e2c719b7 1244 I915_STATE_WARN(cur_state != state,
55607e8a
DV		 1245 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1246 state_string(state), state_string(cur_state));
040484af
JB		 1247}
1248
b680c37a
DV		 1249void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1250 enum pipe pipe)
ea0760cf 1251{
bedd4dba
JN		 1252 struct drm_device *dev = dev_priv->dev;
1253 int pp_reg;
ea0760cf
JB		 1254 u32 val;
1255 enum pipe panel_pipe = PIPE_A;
0de3b485 1256 bool locked = true;
ea0760cf 1257
bedd4dba
JN		 1258 if (WARN_ON(HAS_DDI(dev)))
1259 return;
1260
1261 if (HAS_PCH_SPLIT(dev)) {
1262 u32 port_sel;
1263
ea0760cf 1264 pp_reg = PCH_PP_CONTROL;
bedd4dba
JN		 1265 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1266
1267 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1268 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1269 panel_pipe = PIPE_B;
1270 /* XXX: else fix for eDP */
1271 } else if (IS_VALLEYVIEW(dev)) {
1272 /* presumably write lock depends on pipe, not port select */
1273 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1274 panel_pipe = pipe;
ea0760cf
JB		 1275 } else {
1276 pp_reg = PP_CONTROL;
bedd4dba
JN		 1277 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1278 panel_pipe = PIPE_B;
ea0760cf
JB		 1279 }
1280
1281 val = I915_READ(pp_reg);
1282 if (!(val & PANEL_POWER_ON) ||
ec49ba2d 1283 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
ea0760cf
JB		 1284 locked = false;
1285
e2c719b7 1286 I915_STATE_WARN(panel_pipe == pipe && locked,
ea0760cf 1287 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1288 pipe_name(pipe));
ea0760cf
JB		 1289}
1290
93ce0ba6
JN		 1291static void assert_cursor(struct drm_i915_private *dev_priv,
1292 enum pipe pipe, bool state)
1293{
1294 struct drm_device *dev = dev_priv->dev;
1295 bool cur_state;
1296
d9d82081 1297 if (IS_845G(dev) || IS_I865G(dev))
93ce0ba6 1298 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
d9d82081 1299 else
5efb3e28 1300 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
93ce0ba6 1301
e2c719b7 1302 I915_STATE_WARN(cur_state != state,
93ce0ba6
JN		 1303 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1304 pipe_name(pipe), state_string(state), state_string(cur_state));
1305}
1306#define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1307#define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1308
b840d907
JB		 1309void assert_pipe(struct drm_i915_private *dev_priv,
1310 enum pipe pipe, bool state)
b24e7179
JB		 1311{
1312 int reg;
1313 u32 val;
63d7bbe9 1314 bool cur_state;
702e7a56
PZ		 1315 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1316 pipe);
b24e7179 1317
b6b5d049
VS		 1318 /* if we need the pipe quirk it must be always on */
1319 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1320 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
8e636784
DV		 1321 state = true;
1322
f458ebbc 1323 if (!intel_display_power_is_enabled(dev_priv,
b97186f0 1324 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
69310161
PZ		 1325 cur_state = false;
1326 } else {
1327 reg = PIPECONF(cpu_transcoder);
1328 val = I915_READ(reg);
1329 cur_state = !!(val & PIPECONF_ENABLE);
1330 }
1331
e2c719b7 1332 I915_STATE_WARN(cur_state != state,
63d7bbe9 1333 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1334 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1335}
1336
931872fc
CW		 1337static void assert_plane(struct drm_i915_private *dev_priv,
1338 enum plane plane, bool state)
b24e7179
JB		 1339{
1340 int reg;
1341 u32 val;
931872fc 1342 bool cur_state;
b24e7179
JB		 1343
1344 reg = DSPCNTR(plane);
1345 val = I915_READ(reg);
931872fc 1346 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
e2c719b7 1347 I915_STATE_WARN(cur_state != state,
931872fc
CW		 1348 "plane %c assertion failure (expected %s, current %s)\n",
1349 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1350}
1351
931872fc
CW		 1352#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1353#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1354
b24e7179
JB		 1355static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1356 enum pipe pipe)
1357{
653e1026 1358 struct drm_device *dev = dev_priv->dev;
b24e7179
JB		 1359 int reg, i;
1360 u32 val;
1361 int cur_pipe;
1362
653e1026
VS		 1363 /* Primary planes are fixed to pipes on gen4+ */
1364 if (INTEL_INFO(dev)->gen >= 4) {
28c05794
AJ		 1365 reg = DSPCNTR(pipe);
1366 val = I915_READ(reg);
e2c719b7 1367 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
28c05794
AJ		 1368 "plane %c assertion failure, should be disabled but not\n",
1369 plane_name(pipe));
19ec1358 1370 return;
28c05794 1371 }
19ec1358 1372
b24e7179 1373 /* Need to check both planes against the pipe */
055e393f 1374 for_each_pipe(dev_priv, i) {
b24e7179
JB		 1375 reg = DSPCNTR(i);
1376 val = I915_READ(reg);
1377 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1378 DISPPLANE_SEL_PIPE_SHIFT;
e2c719b7 1379 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1380 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1381 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1382 }
1383}
1384
19332d7a
JB		 1385static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1386 enum pipe pipe)
1387{
20674eef 1388 struct drm_device *dev = dev_priv->dev;
1fe47785 1389 int reg, sprite;
19332d7a
JB		 1390 u32 val;
1391
7feb8b88 1392 if (INTEL_INFO(dev)->gen >= 9) {
3bdcfc0c 1393 for_each_sprite(dev_priv, pipe, sprite) {
7feb8b88 1394 val = I915_READ(PLANE_CTL(pipe, sprite));
e2c719b7 1395 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
7feb8b88
DL		 1396 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1397 sprite, pipe_name(pipe));
1398 }
1399 } else if (IS_VALLEYVIEW(dev)) {
3bdcfc0c 1400 for_each_sprite(dev_priv, pipe, sprite) {
1fe47785 1401 reg = SPCNTR(pipe, sprite);
20674eef 1402 val = I915_READ(reg);
e2c719b7 1403 I915_STATE_WARN(val & SP_ENABLE,
20674eef 1404 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1fe47785 1405 sprite_name(pipe, sprite), pipe_name(pipe));
20674eef
VS		 1406 }
1407 } else if (INTEL_INFO(dev)->gen >= 7) {
1408 reg = SPRCTL(pipe);
19332d7a 1409 val = I915_READ(reg);
e2c719b7 1410 I915_STATE_WARN(val & SPRITE_ENABLE,
06da8da2 1411 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef
VS		 1412 plane_name(pipe), pipe_name(pipe));
1413 } else if (INTEL_INFO(dev)->gen >= 5) {
1414 reg = DVSCNTR(pipe);
19332d7a 1415 val = I915_READ(reg);
e2c719b7 1416 I915_STATE_WARN(val & DVS_ENABLE,
06da8da2 1417 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef 1418 plane_name(pipe), pipe_name(pipe));
19332d7a
JB		 1419 }
1420}
1421
08c71e5e
VS		 1422static void assert_vblank_disabled(struct drm_crtc *crtc)
1423{
e2c719b7 1424 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
08c71e5e
VS		 1425 drm_crtc_vblank_put(crtc);
1426}
1427
89eff4be 1428static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
92f2584a
JB		 1429{
1430 u32 val;
1431 bool enabled;
1432
e2c719b7 1433 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
9d82aa17 1434
92f2584a
JB		 1435 val = I915_READ(PCH_DREF_CONTROL);
1436 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1437 DREF_SUPERSPREAD_SOURCE_MASK));
e2c719b7 1438 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
92f2584a
JB		 1439}
1440
ab9412ba
DV		 1441static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1442 enum pipe pipe)
92f2584a
JB		 1443{
1444 int reg;
1445 u32 val;
1446 bool enabled;
1447
ab9412ba 1448 reg = PCH_TRANSCONF(pipe);
92f2584a
JB		 1449 val = I915_READ(reg);
1450 enabled = !!(val & TRANS_ENABLE);
e2c719b7 1451 I915_STATE_WARN(enabled,
9db4a9c7
JB		 1452 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1453 pipe_name(pipe));
92f2584a
JB		 1454}
1455
4e634389
KP		 1456static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1457 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1458{
1459 if ((val & DP_PORT_EN) == 0)
1460 return false;
1461
1462 if (HAS_PCH_CPT(dev_priv->dev)) {
1463 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1464 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1465 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1466 return false;
44f37d1f
CML		 1467 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1468 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1469 return false;
f0575e92
KP		 1470 } else {
1471 if ((val & DP_PIPE_MASK) != (pipe << 30))
1472 return false;
1473 }
1474 return true;
1475}
1476
1519b995
KP		 1477static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1478 enum pipe pipe, u32 val)
1479{
dc0fa718 1480 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1481 return false;
1482
1483 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1484 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995 1485 return false;
44f37d1f
CML		 1486 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1487 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1488 return false;
1519b995 1489 } else {
dc0fa718 1490 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1491 return false;
1492 }
1493 return true;
1494}
1495
1496static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1497 enum pipe pipe, u32 val)
1498{
1499 if ((val & LVDS_PORT_EN) == 0)
1500 return false;
1501
1502 if (HAS_PCH_CPT(dev_priv->dev)) {
1503 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1504 return false;
1505 } else {
1506 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1507 return false;
1508 }
1509 return true;
1510}
1511
1512static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1513 enum pipe pipe, u32 val)
1514{
1515 if ((val & ADPA_DAC_ENABLE) == 0)
1516 return false;
1517 if (HAS_PCH_CPT(dev_priv->dev)) {
1518 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1519 return false;
1520 } else {
1521 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1522 return false;
1523 }
1524 return true;
1525}
1526
291906f1 1527static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1528 enum pipe pipe, int reg, u32 port_sel)
291906f1 1529{
47a05eca 1530 u32 val = I915_READ(reg);
e2c719b7 1531 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1532 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1533 reg, pipe_name(pipe));
de9a35ab 1534
e2c719b7 1535 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
75c5da27 1536 && (val & DP_PIPEB_SELECT),
de9a35ab 1537 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1538}
1539
1540static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1541 enum pipe pipe, int reg)
1542{
47a05eca 1543 u32 val = I915_READ(reg);
e2c719b7 1544 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1545 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1546 reg, pipe_name(pipe));
de9a35ab 1547
e2c719b7 1548 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1549 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1550 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1551}
1552
1553static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1554 enum pipe pipe)
1555{
1556 int reg;
1557 u32 val;
291906f1 1558
f0575e92
KP		 1559 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1560 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1561 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1562
1563 reg = PCH_ADPA;
1564 val = I915_READ(reg);
e2c719b7 1565 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1566 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1567 pipe_name(pipe));
291906f1
JB		 1568
1569 reg = PCH_LVDS;
1570 val = I915_READ(reg);
e2c719b7 1571 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1572 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1573 pipe_name(pipe));
291906f1 1574
e2debe91
PZ		 1575 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1576 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1577 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1578}
1579
d288f65f 1580static void vlv_enable_pll(struct intel_crtc *crtc,
5cec258b 1581 const struct intel_crtc_state *pipe_config)
87442f73 1582{
426115cf
DV		 1583 struct drm_device *dev = crtc->base.dev;
1584 struct drm_i915_private *dev_priv = dev->dev_private;
1585 int reg = DPLL(crtc->pipe);
d288f65f 1586 u32 dpll = pipe_config->dpll_hw_state.dpll;
87442f73 1587
426115cf 1588 assert_pipe_disabled(dev_priv, crtc->pipe);
87442f73
DV		 1589
1590 /* No really, not for ILK+ */
1591 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1592
1593 /* PLL is protected by panel, make sure we can write it */
6a9e7363 1594 if (IS_MOBILE(dev_priv->dev))
426115cf 1595 assert_panel_unlocked(dev_priv, crtc->pipe);
87442f73 1596
426115cf
DV		 1597 I915_WRITE(reg, dpll);
1598 POSTING_READ(reg);
1599 udelay(150);
1600
1601 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1602 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1603
d288f65f 1604 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
426115cf 1605 POSTING_READ(DPLL_MD(crtc->pipe));
87442f73
DV		 1606
1607 /* We do this three times for luck */
426115cf 1608 I915_WRITE(reg, dpll);
87442f73
DV		 1609 POSTING_READ(reg);
1610 udelay(150); /* wait for warmup */
426115cf 1611 I915_WRITE(reg, dpll);
87442f73
DV		 1612 POSTING_READ(reg);
1613 udelay(150); /* wait for warmup */
426115cf 1614 I915_WRITE(reg, dpll);
87442f73
DV		 1615 POSTING_READ(reg);
1616 udelay(150); /* wait for warmup */
1617}
1618
d288f65f 1619static void chv_enable_pll(struct intel_crtc *crtc,
5cec258b 1620 const struct intel_crtc_state *pipe_config)
9d556c99
CML		 1621{
1622 struct drm_device *dev = crtc->base.dev;
1623 struct drm_i915_private *dev_priv = dev->dev_private;
1624 int pipe = crtc->pipe;
1625 enum dpio_channel port = vlv_pipe_to_channel(pipe);
9d556c99
CML		 1626 u32 tmp;
1627
1628 assert_pipe_disabled(dev_priv, crtc->pipe);
1629
1630 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1631
a580516d 1632 mutex_lock(&dev_priv->sb_lock);
9d556c99
CML		 1633
1634 /* Enable back the 10bit clock to display controller */
1635 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1636 tmp |= DPIO_DCLKP_EN;
1637 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1638
54433e91
VS		 1639 mutex_unlock(&dev_priv->sb_lock);
1640
9d556c99
CML		 1641 /*
1642 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1643 */
1644 udelay(1);
1645
1646 /* Enable PLL */
d288f65f 1647 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
9d556c99
CML		 1648
1649 /* Check PLL is locked */
a11b0703 1650 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
9d556c99
CML		 1651 DRM_ERROR("PLL %d failed to lock\n", pipe);
1652
a11b0703 1653 /* not sure when this should be written */
d288f65f 1654 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
a11b0703 1655 POSTING_READ(DPLL_MD(pipe));
9d556c99
CML		 1656}
1657
1c4e0274
VS		 1658static int intel_num_dvo_pipes(struct drm_device *dev)
1659{
1660 struct intel_crtc *crtc;
1661 int count = 0;
1662
1663 for_each_intel_crtc(dev, crtc)
3538b9df 1664 count += crtc->base.state->active &&
409ee761 1665 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1c4e0274
VS		 1666
1667 return count;
1668}
1669
66e3d5c0 1670static void i9xx_enable_pll(struct intel_crtc *crtc)
63d7bbe9 1671{
66e3d5c0
DV		 1672 struct drm_device *dev = crtc->base.dev;
1673 struct drm_i915_private *dev_priv = dev->dev_private;
1674 int reg = DPLL(crtc->pipe);
6e3c9717 1675 u32 dpll = crtc->config->dpll_hw_state.dpll;
63d7bbe9 1676
66e3d5c0 1677 assert_pipe_disabled(dev_priv, crtc->pipe);
58c6eaa2 1678
63d7bbe9 1679 /* No really, not for ILK+ */
3d13ef2e 1680 BUG_ON(INTEL_INFO(dev)->gen >= 5);
63d7bbe9
JB		 1681
1682 /* PLL is protected by panel, make sure we can write it */
66e3d5c0
DV		 1683 if (IS_MOBILE(dev) && !IS_I830(dev))
1684 assert_panel_unlocked(dev_priv, crtc->pipe);
63d7bbe9 1685
1c4e0274
VS		 1686 /* Enable DVO 2x clock on both PLLs if necessary */
1687 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1688 /*
1689 * It appears to be important that we don't enable this
1690 * for the current pipe before otherwise configuring the
1691 * PLL. No idea how this should be handled if multiple
1692 * DVO outputs are enabled simultaneosly.
1693 */
1694 dpll |= DPLL_DVO_2X_MODE;
1695 I915_WRITE(DPLL(!crtc->pipe),
1696 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1697 }
66e3d5c0
DV		 1698
1699 /* Wait for the clocks to stabilize. */
1700 POSTING_READ(reg);
1701 udelay(150);
1702
1703 if (INTEL_INFO(dev)->gen >= 4) {
1704 I915_WRITE(DPLL_MD(crtc->pipe),
6e3c9717 1705 crtc->config->dpll_hw_state.dpll_md);
66e3d5c0
DV		 1706 } else {
1707 /* The pixel multiplier can only be updated once the
1708 * DPLL is enabled and the clocks are stable.
1709 *
1710 * So write it again.
1711 */
1712 I915_WRITE(reg, dpll);
1713 }
63d7bbe9
JB		 1714
1715 /* We do this three times for luck */
66e3d5c0 1716 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1717 POSTING_READ(reg);
1718 udelay(150); /* wait for warmup */
66e3d5c0 1719 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1720 POSTING_READ(reg);
1721 udelay(150); /* wait for warmup */
66e3d5c0 1722 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1723 POSTING_READ(reg);
1724 udelay(150); /* wait for warmup */
1725}
1726
1727/**
50b44a44 1728 * i9xx_disable_pll - disable a PLL
63d7bbe9
JB		 1729 * @dev_priv: i915 private structure
1730 * @pipe: pipe PLL to disable
1731 *
1732 * Disable the PLL for @pipe, making sure the pipe is off first.
1733 *
1734 * Note! This is for pre-ILK only.
1735 */
1c4e0274 1736static void i9xx_disable_pll(struct intel_crtc *crtc)
63d7bbe9 1737{
1c4e0274
VS		 1738 struct drm_device *dev = crtc->base.dev;
1739 struct drm_i915_private *dev_priv = dev->dev_private;
1740 enum pipe pipe = crtc->pipe;
1741
1742 /* Disable DVO 2x clock on both PLLs if necessary */
1743 if (IS_I830(dev) &&
409ee761 1744 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
3538b9df 1745 !intel_num_dvo_pipes(dev)) {
1c4e0274
VS		 1746 I915_WRITE(DPLL(PIPE_B),
1747 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1748 I915_WRITE(DPLL(PIPE_A),
1749 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1750 }
1751
b6b5d049
VS		 1752 /* Don't disable pipe or pipe PLLs if needed */
1753 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1754 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
63d7bbe9
JB		 1755 return;
1756
1757 /* Make sure the pipe isn't still relying on us */
1758 assert_pipe_disabled(dev_priv, pipe);
1759
b8afb911 1760 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
50b44a44 1761 POSTING_READ(DPLL(pipe));
63d7bbe9
JB		 1762}
1763
f6071166
JB		 1764static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1765{
b8afb911 1766 u32 val;
f6071166
JB		 1767
1768 /* Make sure the pipe isn't still relying on us */
1769 assert_pipe_disabled(dev_priv, pipe);
1770
e5cbfbfb
ID		 1771 /*
1772 * Leave integrated clock source and reference clock enabled for pipe B.
1773 * The latter is needed for VGA hotplug / manual detection.
1774 */
b8afb911 1775 val = DPLL_VGA_MODE_DIS;
f6071166 1776 if (pipe == PIPE_B)
60bfe44f 1777 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REF_CLK_ENABLE_VLV;
f6071166
JB		 1778 I915_WRITE(DPLL(pipe), val);
1779 POSTING_READ(DPLL(pipe));
076ed3b2
CML		 1780
1781}
1782
1783static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1784{
d752048d 1785 enum dpio_channel port = vlv_pipe_to_channel(pipe);
076ed3b2
CML		 1786 u32 val;
1787
a11b0703
VS		 1788 /* Make sure the pipe isn't still relying on us */
1789 assert_pipe_disabled(dev_priv, pipe);
076ed3b2 1790
a11b0703 1791 /* Set PLL en = 0 */
60bfe44f
VS		 1792 val = DPLL_SSC_REF_CLK_CHV |
1793 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
a11b0703
VS		 1794 if (pipe != PIPE_A)
1795 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1796 I915_WRITE(DPLL(pipe), val);
1797 POSTING_READ(DPLL(pipe));
d752048d 1798
a580516d 1799 mutex_lock(&dev_priv->sb_lock);
d752048d
VS		 1800
1801 /* Disable 10bit clock to display controller */
1802 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1803 val &= ~DPIO_DCLKP_EN;
1804 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1805
a580516d 1806 mutex_unlock(&dev_priv->sb_lock);
f6071166
JB		 1807}
1808
e4607fcf 1809void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
9b6de0a1
VS		 1810 struct intel_digital_port *dport,
1811 unsigned int expected_mask)
89b667f8
JB		 1812{
1813 u32 port_mask;
00fc31b7 1814 int dpll_reg;
89b667f8 1815
e4607fcf
CML		 1816 switch (dport->port) {
1817 case PORT_B:
89b667f8 1818 port_mask = DPLL_PORTB_READY_MASK;
00fc31b7 1819 dpll_reg = DPLL(0);
e4607fcf
CML		 1820 break;
1821 case PORT_C:
89b667f8 1822 port_mask = DPLL_PORTC_READY_MASK;
00fc31b7 1823 dpll_reg = DPLL(0);
9b6de0a1 1824 expected_mask <<= 4;
00fc31b7
CML		 1825 break;
1826 case PORT_D:
1827 port_mask = DPLL_PORTD_READY_MASK;
1828 dpll_reg = DPIO_PHY_STATUS;
e4607fcf
CML		 1829 break;
1830 default:
1831 BUG();
1832 }
89b667f8 1833
9b6de0a1
VS		 1834 if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1835 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1836 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
89b667f8
JB		 1837}
1838
b14b1055
DV		 1839static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1840{
1841 struct drm_device *dev = crtc->base.dev;
1842 struct drm_i915_private *dev_priv = dev->dev_private;
1843 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1844
be19f0ff
CW		 1845 if (WARN_ON(pll == NULL))
1846 return;
1847
3e369b76 1848 WARN_ON(!pll->config.crtc_mask);
b14b1055
DV		 1849 if (pll->active == 0) {
1850 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1851 WARN_ON(pll->on);
1852 assert_shared_dpll_disabled(dev_priv, pll);
1853
1854 pll->mode_set(dev_priv, pll);
1855 }
1856}
1857
92f2584a 1858/**
85b3894f 1859 * intel_enable_shared_dpll - enable PCH PLL
92f2584a
JB		 1860 * @dev_priv: i915 private structure
1861 * @pipe: pipe PLL to enable
1862 *
1863 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1864 * drives the transcoder clock.
1865 */
85b3894f 1866static void intel_enable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1867{
3d13ef2e
DL		 1868 struct drm_device *dev = crtc->base.dev;
1869 struct drm_i915_private *dev_priv = dev->dev_private;
e2b78267 1870 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
92f2584a 1871
87a875bb 1872 if (WARN_ON(pll == NULL))
48da64a8
CW		 1873 return;
1874
3e369b76 1875 if (WARN_ON(pll->config.crtc_mask == 0))
48da64a8 1876 return;
ee7b9f93 1877
74dd6928 1878 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
46edb027 1879 pll->name, pll->active, pll->on,
e2b78267 1880 crtc->base.base.id);
92f2584a 1881
cdbd2316
DV		 1882 if (pll->active++) {
1883 WARN_ON(!pll->on);
e9d6944e 1884 assert_shared_dpll_enabled(dev_priv, pll);
ee7b9f93
JB		 1885 return;
1886 }
f4a091c7 1887 WARN_ON(pll->on);
ee7b9f93 1888
bd2bb1b9
PZ		 1889 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1890
46edb027 1891 DRM_DEBUG_KMS("enabling %s\n", pll->name);
e7b903d2 1892 pll->enable(dev_priv, pll);
ee7b9f93 1893 pll->on = true;
92f2584a
JB		 1894}
1895
f6daaec2 1896static void intel_disable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1897{
3d13ef2e
DL		 1898 struct drm_device *dev = crtc->base.dev;
1899 struct drm_i915_private *dev_priv = dev->dev_private;
e2b78267 1900 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4c609cb8 1901
92f2584a 1902 /* PCH only available on ILK+ */
80aa9312
JB		 1903 if (INTEL_INFO(dev)->gen < 5)
1904 return;
1905
eddfcbcd
ML		 1906 if (pll == NULL)
1907 return;
92f2584a 1908
eddfcbcd 1909 if (WARN_ON(!(pll->config.crtc_mask & (1 << drm_crtc_index(&crtc->base)))))
48da64a8 1910 return;
7a419866 1911
46edb027
DV		 1912 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1913 pll->name, pll->active, pll->on,
e2b78267 1914 crtc->base.base.id);
7a419866 1915
48da64a8 1916 if (WARN_ON(pll->active == 0)) {
e9d6944e 1917 assert_shared_dpll_disabled(dev_priv, pll);
48da64a8
CW		 1918 return;
1919 }
1920
e9d6944e 1921 assert_shared_dpll_enabled(dev_priv, pll);
f4a091c7 1922 WARN_ON(!pll->on);
cdbd2316 1923 if (--pll->active)
7a419866 1924 return;
ee7b9f93 1925
46edb027 1926 DRM_DEBUG_KMS("disabling %s\n", pll->name);
e7b903d2 1927 pll->disable(dev_priv, pll);
ee7b9f93 1928 pll->on = false;
bd2bb1b9
PZ		 1929
1930 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
92f2584a
JB		 1931}
1932
b8a4f404
PZ		 1933static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1934 enum pipe pipe)
040484af 1935{
23670b32 1936 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1937 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
e2b78267 1938 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
23670b32 1939 uint32_t reg, val, pipeconf_val;
040484af
JB		 1940
1941 /* PCH only available on ILK+ */
55522f37 1942 BUG_ON(!HAS_PCH_SPLIT(dev));
040484af
JB		 1943
1944 /* Make sure PCH DPLL is enabled */
e72f9fbf 1945 assert_shared_dpll_enabled(dev_priv,
e9d6944e 1946 intel_crtc_to_shared_dpll(intel_crtc));
040484af
JB		 1947
1948 /* FDI must be feeding us bits for PCH ports */
1949 assert_fdi_tx_enabled(dev_priv, pipe);
1950 assert_fdi_rx_enabled(dev_priv, pipe);
1951
23670b32
DV		 1952 if (HAS_PCH_CPT(dev)) {
1953 /* Workaround: Set the timing override bit before enabling the
1954 * pch transcoder. */
1955 reg = TRANS_CHICKEN2(pipe);
1956 val = I915_READ(reg);
1957 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1958 I915_WRITE(reg, val);
59c859d6 1959 }
23670b32 1960
ab9412ba 1961 reg = PCH_TRANSCONF(pipe);
040484af 1962 val = I915_READ(reg);
5f7f726d 1963 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1964
1965 if (HAS_PCH_IBX(dev_priv->dev)) {
1966 /*
c5de7c6f
VS		 1967 * Make the BPC in transcoder be consistent with
1968 * that in pipeconf reg. For HDMI we must use 8bpc
1969 * here for both 8bpc and 12bpc.
e9bcff5c 1970 */
dfd07d72 1971 val &= ~PIPECONF_BPC_MASK;
c5de7c6f
VS		 1972 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
1973 val |= PIPECONF_8BPC;
1974 else
1975 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 1976 }
5f7f726d
PZ		 1977
1978 val &= ~TRANS_INTERLACE_MASK;
1979 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6 1980 if (HAS_PCH_IBX(dev_priv->dev) &&
409ee761 1981 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7c26e5c6
PZ		 1982 val |= TRANS_LEGACY_INTERLACED_ILK;
1983 else
1984 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1985 else
1986 val |= TRANS_PROGRESSIVE;
1987
040484af
JB		 1988 I915_WRITE(reg, val | TRANS_ENABLE);
1989 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 1990 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 1991}
1992
8fb033d7 1993static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 1994 enum transcoder cpu_transcoder)
040484af 1995{
8fb033d7 1996 u32 val, pipeconf_val;
8fb033d7
PZ		 1997
1998 /* PCH only available on ILK+ */
55522f37 1999 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
8fb033d7 2000
8fb033d7 2001 /* FDI must be feeding us bits for PCH ports */
1a240d4d 2002 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 2003 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 2004
223a6fdf
PZ		 2005 /* Workaround: set timing override bit. */
2006 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 2007 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 2008 I915_WRITE(_TRANSA_CHICKEN2, val);
2009
25f3ef11 2010 val = TRANS_ENABLE;
937bb610 2011 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 2012
9a76b1c6
PZ		 2013 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2014 PIPECONF_INTERLACED_ILK)
a35f2679 2015 val |= TRANS_INTERLACED;
8fb033d7
PZ		 2016 else
2017 val |= TRANS_PROGRESSIVE;
2018
ab9412ba
DV		 2019 I915_WRITE(LPT_TRANSCONF, val);
2020 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
937bb610 2021 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 2022}
2023
b8a4f404
PZ		 2024static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2025 enum pipe pipe)
040484af 2026{
23670b32
DV		 2027 struct drm_device *dev = dev_priv->dev;
2028 uint32_t reg, val;
040484af
JB		 2029
2030 /* FDI relies on the transcoder */
2031 assert_fdi_tx_disabled(dev_priv, pipe);
2032 assert_fdi_rx_disabled(dev_priv, pipe);
2033
291906f1
JB		 2034 /* Ports must be off as well */
2035 assert_pch_ports_disabled(dev_priv, pipe);
2036
ab9412ba 2037 reg = PCH_TRANSCONF(pipe);
040484af
JB		 2038 val = I915_READ(reg);
2039 val &= ~TRANS_ENABLE;
2040 I915_WRITE(reg, val);
2041 /* wait for PCH transcoder off, transcoder state */
2042 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 2043 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV		 2044
2045 if (!HAS_PCH_IBX(dev)) {
2046 /* Workaround: Clear the timing override chicken bit again. */
2047 reg = TRANS_CHICKEN2(pipe);
2048 val = I915_READ(reg);
2049 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2050 I915_WRITE(reg, val);
2051 }
040484af
JB		 2052}
2053
ab4d966c 2054static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 2055{
8fb033d7
PZ		 2056 u32 val;
2057
ab9412ba 2058 val = I915_READ(LPT_TRANSCONF);
8fb033d7 2059 val &= ~TRANS_ENABLE;
ab9412ba 2060 I915_WRITE(LPT_TRANSCONF, val);
8fb033d7 2061 /* wait for PCH transcoder off, transcoder state */
ab9412ba 2062 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
8a52fd9f 2063 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 2064
2065 /* Workaround: clear timing override bit. */
2066 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 2067 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 2068 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 2069}
2070
b24e7179 2071/**
309cfea8 2072 * intel_enable_pipe - enable a pipe, asserting requirements
0372264a 2073 * @crtc: crtc responsible for the pipe
b24e7179 2074 *
0372264a 2075 * Enable @crtc's pipe, making sure that various hardware specific requirements
b24e7179 2076 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
b24e7179 2077 */
e1fdc473 2078static void intel_enable_pipe(struct intel_crtc *crtc)
b24e7179 2079{
0372264a
PZ		 2080 struct drm_device *dev = crtc->base.dev;
2081 struct drm_i915_private *dev_priv = dev->dev_private;
2082 enum pipe pipe = crtc->pipe;
702e7a56
PZ		 2083 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2084 pipe);
1a240d4d 2085 enum pipe pch_transcoder;
b24e7179
JB		 2086 int reg;
2087 u32 val;
2088
9e2ee2dd
VS		 2089 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
2090
58c6eaa2 2091 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 2092 assert_cursor_disabled(dev_priv, pipe);
58c6eaa2
DV		 2093 assert_sprites_disabled(dev_priv, pipe);
2094
681e5811 2095 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 2096 pch_transcoder = TRANSCODER_A;
2097 else
2098 pch_transcoder = pipe;
2099
b24e7179
JB		 2100 /*
2101 * A pipe without a PLL won't actually be able to drive bits from
2102 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2103 * need the check.
2104 */
50360403 2105 if (HAS_GMCH_DISPLAY(dev_priv->dev))
409ee761 2106 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
23538ef1
JN		 2107 assert_dsi_pll_enabled(dev_priv);
2108 else
2109 assert_pll_enabled(dev_priv, pipe);
040484af 2110 else {
6e3c9717 2111 if (crtc->config->has_pch_encoder) {
040484af 2112 /* if driving the PCH, we need FDI enabled */
cc391bbb 2113 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 2114 assert_fdi_tx_pll_enabled(dev_priv,
2115 (enum pipe) cpu_transcoder);
040484af
JB		 2116 }
2117 /* FIXME: assert CPU port conditions for SNB+ */
2118 }
b24e7179 2119
702e7a56 2120 reg = PIPECONF(cpu_transcoder);
b24e7179 2121 val = I915_READ(reg);
7ad25d48 2122 if (val & PIPECONF_ENABLE) {
b6b5d049
VS		 2123 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2124 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
00d70b15 2125 return;
7ad25d48 2126 }
00d70b15
CW		 2127
2128 I915_WRITE(reg, val | PIPECONF_ENABLE);
851855d8 2129 POSTING_READ(reg);
b24e7179
JB		 2130}
2131
2132/**
309cfea8 2133 * intel_disable_pipe - disable a pipe, asserting requirements
575f7ab7 2134 * @crtc: crtc whose pipes is to be disabled
b24e7179 2135 *
575f7ab7
VS		 2136 * Disable the pipe of @crtc, making sure that various hardware
2137 * specific requirements are met, if applicable, e.g. plane
2138 * disabled, panel fitter off, etc.
b24e7179
JB		 2139 *
2140 * Will wait until the pipe has shut down before returning.
2141 */
575f7ab7 2142static void intel_disable_pipe(struct intel_crtc *crtc)
b24e7179 2143{
575f7ab7 2144 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
6e3c9717 2145 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
575f7ab7 2146 enum pipe pipe = crtc->pipe;
b24e7179
JB		 2147 int reg;
2148 u32 val;
2149
9e2ee2dd
VS		 2150 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2151
b24e7179
JB		 2152 /*
2153 * Make sure planes won't keep trying to pump pixels to us,
2154 * or we might hang the display.
2155 */
2156 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 2157 assert_cursor_disabled(dev_priv, pipe);
19332d7a 2158 assert_sprites_disabled(dev_priv, pipe);
b24e7179 2159
702e7a56 2160 reg = PIPECONF(cpu_transcoder);
b24e7179 2161 val = I915_READ(reg);
00d70b15
CW		 2162 if ((val & PIPECONF_ENABLE) == 0)
2163 return;
2164
67adc644
VS		 2165 /*
2166 * Double wide has implications for planes
2167 * so best keep it disabled when not needed.
2168 */
6e3c9717 2169 if (crtc->config->double_wide)
67adc644
VS		 2170 val &= ~PIPECONF_DOUBLE_WIDE;
2171
2172 /* Don't disable pipe or pipe PLLs if needed */
b6b5d049
VS		 2173 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2174 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
67adc644
VS		 2175 val &= ~PIPECONF_ENABLE;
2176
2177 I915_WRITE(reg, val);
2178 if ((val & PIPECONF_ENABLE) == 0)
2179 intel_wait_for_pipe_off(crtc);
b24e7179
JB		 2180}
2181
693db184
CW		 2182static bool need_vtd_wa(struct drm_device *dev)
2183{
2184#ifdef CONFIG_INTEL_IOMMU
2185 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2186 return true;
2187#endif
2188 return false;
2189}
2190
50470bb0 2191unsigned int
6761dd31
TU		 2192intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2193 uint64_t fb_format_modifier)
a57ce0b2 2194{
6761dd31
TU		 2195 unsigned int tile_height;
2196 uint32_t pixel_bytes;
a57ce0b2 2197
b5d0e9bf
DL		 2198 switch (fb_format_modifier) {
2199 case DRM_FORMAT_MOD_NONE:
2200 tile_height = 1;
2201 break;
2202 case I915_FORMAT_MOD_X_TILED:
2203 tile_height = IS_GEN2(dev) ? 16 : 8;
2204 break;
2205 case I915_FORMAT_MOD_Y_TILED:
2206 tile_height = 32;
2207 break;
2208 case I915_FORMAT_MOD_Yf_TILED:
6761dd31
TU		 2209 pixel_bytes = drm_format_plane_cpp(pixel_format, 0);
2210 switch (pixel_bytes) {
b5d0e9bf 2211 default:
6761dd31 2212 case 1:
b5d0e9bf
DL		 2213 tile_height = 64;
2214 break;
6761dd31
TU		 2215 case 2:
2216 case 4:
b5d0e9bf
DL		 2217 tile_height = 32;
2218 break;
6761dd31 2219 case 8:
b5d0e9bf
DL		 2220 tile_height = 16;
2221 break;
6761dd31 2222 case 16:
b5d0e9bf
DL		 2223 WARN_ONCE(1,
2224 "128-bit pixels are not supported for display!");
2225 tile_height = 16;
2226 break;
2227 }
2228 break;
2229 default:
2230 MISSING_CASE(fb_format_modifier);
2231 tile_height = 1;
2232 break;
2233 }
091df6cb 2234
6761dd31
TU		 2235 return tile_height;
2236}
2237
2238unsigned int
2239intel_fb_align_height(struct drm_device *dev, unsigned int height,
2240 uint32_t pixel_format, uint64_t fb_format_modifier)
2241{
2242 return ALIGN(height, intel_tile_height(dev, pixel_format,
2243 fb_format_modifier));
a57ce0b2
JB		 2244}
2245
f64b98cd
TU		 2246static int
2247intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2248 const struct drm_plane_state *plane_state)
2249{
50470bb0 2250 struct intel_rotation_info *info = &view->rotation_info;
84fe03f7 2251 unsigned int tile_height, tile_pitch;
50470bb0 2252
f64b98cd
TU		 2253 *view = i915_ggtt_view_normal;
2254
50470bb0
TU		 2255 if (!plane_state)
2256 return 0;
2257
121920fa 2258 if (!intel_rotation_90_or_270(plane_state->rotation))
50470bb0
TU		 2259 return 0;
2260
9abc4648 2261 *view = i915_ggtt_view_rotated;
50470bb0
TU		 2262
2263 info->height = fb->height;
2264 info->pixel_format = fb->pixel_format;
2265 info->pitch = fb->pitches[0];
2266 info->fb_modifier = fb->modifier[0];
2267
84fe03f7
TU		 2268 tile_height = intel_tile_height(fb->dev, fb->pixel_format,
2269 fb->modifier[0]);
2270 tile_pitch = PAGE_SIZE / tile_height;
2271 info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2272 info->height_pages = DIV_ROUND_UP(fb->height, tile_height);
2273 info->size = info->width_pages * info->height_pages * PAGE_SIZE;
2274
f64b98cd
TU		 2275 return 0;
2276}
2277
4e9a86b6
VS		 2278static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv)
2279{
2280 if (INTEL_INFO(dev_priv)->gen >= 9)
2281 return 256 * 1024;
985b8bb4
VS		 2282 else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2283 IS_VALLEYVIEW(dev_priv))
4e9a86b6
VS		 2284 return 128 * 1024;
2285 else if (INTEL_INFO(dev_priv)->gen >= 4)
2286 return 4 * 1024;
2287 else
44c5905e 2288 return 0;
4e9a86b6
VS		 2289}
2290
127bd2ac 2291int
850c4cdc
TU		 2292intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2293 struct drm_framebuffer *fb,
82bc3b2d 2294 const struct drm_plane_state *plane_state,
91af127f
JH		 2295 struct intel_engine_cs *pipelined,
2296 struct drm_i915_gem_request **pipelined_request)
6b95a207 2297{
850c4cdc 2298 struct drm_device *dev = fb->dev;
ce453d81 2299 struct drm_i915_private *dev_priv = dev->dev_private;
850c4cdc 2300 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
f64b98cd 2301 struct i915_ggtt_view view;
6b95a207
KH		 2302 u32 alignment;
2303 int ret;
2304
ebcdd39e
MR		 2305 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2306
7b911adc
TU		 2307 switch (fb->modifier[0]) {
2308 case DRM_FORMAT_MOD_NONE:
4e9a86b6 2309 alignment = intel_linear_alignment(dev_priv);
6b95a207 2310 break;
7b911adc 2311 case I915_FORMAT_MOD_X_TILED:
1fada4cc
DL		 2312 if (INTEL_INFO(dev)->gen >= 9)
2313 alignment = 256 * 1024;
2314 else {
2315 /* pin() will align the object as required by fence */
2316 alignment = 0;
2317 }
6b95a207 2318 break;
7b911adc 2319 case I915_FORMAT_MOD_Y_TILED:
1327b9a1
DL		 2320 case I915_FORMAT_MOD_Yf_TILED:
2321 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2322 "Y tiling bo slipped through, driver bug!\n"))
2323 return -EINVAL;
2324 alignment = 1 * 1024 * 1024;
2325 break;
6b95a207 2326 default:
7b911adc
TU		 2327 MISSING_CASE(fb->modifier[0]);
2328 return -EINVAL;
6b95a207
KH		 2329 }
2330
f64b98cd
TU		 2331 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2332 if (ret)
2333 return ret;
2334
693db184
CW		 2335 /* Note that the w/a also requires 64 PTE of padding following the
2336 * bo. We currently fill all unused PTE with the shadow page and so
2337 * we should always have valid PTE following the scanout preventing
2338 * the VT-d warning.
2339 */
2340 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2341 alignment = 256 * 1024;
2342
d6dd6843
PZ		 2343 /*
2344 * Global gtt pte registers are special registers which actually forward
2345 * writes to a chunk of system memory. Which means that there is no risk
2346 * that the register values disappear as soon as we call
2347 * intel_runtime_pm_put(), so it is correct to wrap only the
2348 * pin/unpin/fence and not more.
2349 */
2350 intel_runtime_pm_get(dev_priv);
2351
ce453d81 2352 dev_priv->mm.interruptible = false;
e6617330 2353 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
91af127f 2354 pipelined_request, &view);
48b956c5 2355 if (ret)
ce453d81 2356 goto err_interruptible;
6b95a207
KH		 2357
2358 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2359 * fence, whereas 965+ only requires a fence if using
2360 * framebuffer compression. For simplicity, we always install
2361 * a fence as the cost is not that onerous.
2362 */
06d98131 2363 ret = i915_gem_object_get_fence(obj);
842315ee
ML		 2364 if (ret == -EDEADLK) {
2365 /*
2366 * -EDEADLK means there are no free fences
2367 * no pending flips.
2368 *
2369 * This is propagated to atomic, but it uses
2370 * -EDEADLK to force a locking recovery, so
2371 * change the returned error to -EBUSY.
2372 */
2373 ret = -EBUSY;
2374 goto err_unpin;
2375 } else if (ret)
9a5a53b3 2376 goto err_unpin;
1690e1eb 2377
9a5a53b3 2378 i915_gem_object_pin_fence(obj);
6b95a207 2379
ce453d81 2380 dev_priv->mm.interruptible = true;
d6dd6843 2381 intel_runtime_pm_put(dev_priv);
6b95a207 2382 return 0;
48b956c5
CW		 2383
2384err_unpin:
f64b98cd 2385 i915_gem_object_unpin_from_display_plane(obj, &view);
ce453d81
CW		 2386err_interruptible:
2387 dev_priv->mm.interruptible = true;
d6dd6843 2388 intel_runtime_pm_put(dev_priv);
48b956c5 2389 return ret;
6b95a207
KH		 2390}
2391
82bc3b2d
TU		 2392static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2393 const struct drm_plane_state *plane_state)
1690e1eb 2394{
82bc3b2d 2395 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
f64b98cd
TU		 2396 struct i915_ggtt_view view;
2397 int ret;
82bc3b2d 2398
ebcdd39e
MR		 2399 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2400
f64b98cd
TU		 2401 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2402 WARN_ONCE(ret, "Couldn't get view from plane state!");
2403
1690e1eb 2404 i915_gem_object_unpin_fence(obj);
f64b98cd 2405 i915_gem_object_unpin_from_display_plane(obj, &view);
1690e1eb
CW		 2406}
2407
c2c75131
DV		 2408/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2409 * is assumed to be a power-of-two. */
4e9a86b6
VS		 2410unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
2411 int *x, int *y,
bc752862
CW		 2412 unsigned int tiling_mode,
2413 unsigned int cpp,
2414 unsigned int pitch)
c2c75131 2415{
bc752862
CW		 2416 if (tiling_mode != I915_TILING_NONE) {
2417 unsigned int tile_rows, tiles;
c2c75131 2418
bc752862
CW		 2419 tile_rows = *y / 8;
2420 *y %= 8;
c2c75131 2421
bc752862
CW		 2422 tiles = *x / (512/cpp);
2423 *x %= 512/cpp;
2424
2425 return tile_rows * pitch * 8 + tiles * 4096;
2426 } else {
4e9a86b6 2427 unsigned int alignment = intel_linear_alignment(dev_priv) - 1;
bc752862
CW		 2428 unsigned int offset;
2429
2430 offset = *y * pitch + *x * cpp;
4e9a86b6
VS		 2431 *y = (offset & alignment) / pitch;
2432 *x = ((offset & alignment) - *y * pitch) / cpp;
2433 return offset & ~alignment;
bc752862 2434 }
c2c75131
DV		 2435}
2436
b35d63fa 2437static int i9xx_format_to_fourcc(int format)
46f297fb
JB		 2438{
2439 switch (format) {
2440 case DISPPLANE_8BPP:
2441 return DRM_FORMAT_C8;
2442 case DISPPLANE_BGRX555:
2443 return DRM_FORMAT_XRGB1555;
2444 case DISPPLANE_BGRX565:
2445 return DRM_FORMAT_RGB565;
2446 default:
2447 case DISPPLANE_BGRX888:
2448 return DRM_FORMAT_XRGB8888;
2449 case DISPPLANE_RGBX888:
2450 return DRM_FORMAT_XBGR8888;
2451 case DISPPLANE_BGRX101010:
2452 return DRM_FORMAT_XRGB2101010;
2453 case DISPPLANE_RGBX101010:
2454 return DRM_FORMAT_XBGR2101010;
2455 }
2456}
2457
bc8d7dff
DL		 2458static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2459{
2460 switch (format) {
2461 case PLANE_CTL_FORMAT_RGB_565:
2462 return DRM_FORMAT_RGB565;
2463 default:
2464 case PLANE_CTL_FORMAT_XRGB_8888:
2465 if (rgb_order) {
2466 if (alpha)
2467 return DRM_FORMAT_ABGR8888;
2468 else
2469 return DRM_FORMAT_XBGR8888;
2470 } else {
2471 if (alpha)
2472 return DRM_FORMAT_ARGB8888;
2473 else
2474 return DRM_FORMAT_XRGB8888;
2475 }
2476 case PLANE_CTL_FORMAT_XRGB_2101010:
2477 if (rgb_order)
2478 return DRM_FORMAT_XBGR2101010;
2479 else
2480 return DRM_FORMAT_XRGB2101010;
2481 }
2482}
2483
5724dbd1 2484static bool
f6936e29
DV		 2485intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2486 struct intel_initial_plane_config *plane_config)
46f297fb
JB		 2487{
2488 struct drm_device *dev = crtc->base.dev;
2489 struct drm_i915_gem_object *obj = NULL;
2490 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2d14030b 2491 struct drm_framebuffer *fb = &plane_config->fb->base;
f37b5c2b
DV		 2492 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2493 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2494 PAGE_SIZE);
2495
2496 size_aligned -= base_aligned;
46f297fb 2497
ff2652ea
CW		 2498 if (plane_config->size == 0)
2499 return false;
2500
f37b5c2b
DV		 2501 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2502 base_aligned,
2503 base_aligned,
2504 size_aligned);
46f297fb 2505 if (!obj)
484b41dd 2506 return false;
46f297fb 2507
49af449b
DL		 2508 obj->tiling_mode = plane_config->tiling;
2509 if (obj->tiling_mode == I915_TILING_X)
6bf129df 2510 obj->stride = fb->pitches[0];
46f297fb 2511
6bf129df
DL		 2512 mode_cmd.pixel_format = fb->pixel_format;
2513 mode_cmd.width = fb->width;
2514 mode_cmd.height = fb->height;
2515 mode_cmd.pitches[0] = fb->pitches[0];
18c5247e
DV		 2516 mode_cmd.modifier[0] = fb->modifier[0];
2517 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
46f297fb
JB		 2518
2519 mutex_lock(&dev->struct_mutex);
6bf129df 2520 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
484b41dd 2521 &mode_cmd, obj)) {
46f297fb
JB		 2522 DRM_DEBUG_KMS("intel fb init failed\n");
2523 goto out_unref_obj;
2524 }
46f297fb 2525 mutex_unlock(&dev->struct_mutex);
484b41dd 2526
f6936e29 2527 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
484b41dd 2528 return true;
46f297fb
JB		 2529
2530out_unref_obj:
2531 drm_gem_object_unreference(&obj->base);
2532 mutex_unlock(&dev->struct_mutex);
484b41dd
JB		 2533 return false;
2534}
2535
afd65eb4
MR		 2536/* Update plane->state->fb to match plane->fb after driver-internal updates */
2537static void
2538update_state_fb(struct drm_plane *plane)
2539{
2540 if (plane->fb == plane->state->fb)
2541 return;
2542
2543 if (plane->state->fb)
2544 drm_framebuffer_unreference(plane->state->fb);
2545 plane->state->fb = plane->fb;
2546 if (plane->state->fb)
2547 drm_framebuffer_reference(plane->state->fb);
2548}
2549
5724dbd1 2550static void
f6936e29
DV		 2551intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2552 struct intel_initial_plane_config *plane_config)
484b41dd
JB		 2553{
2554 struct drm_device *dev = intel_crtc->base.dev;
d9ceb816 2555 struct drm_i915_private *dev_priv = dev->dev_private;
484b41dd
JB		 2556 struct drm_crtc *c;
2557 struct intel_crtc *i;
2ff8fde1 2558 struct drm_i915_gem_object *obj;
88595ac9 2559 struct drm_plane *primary = intel_crtc->base.primary;
be5651f2 2560 struct drm_plane_state *plane_state = primary->state;
88595ac9 2561 struct drm_framebuffer *fb;
484b41dd 2562
2d14030b 2563 if (!plane_config->fb)
484b41dd
JB		 2564 return;
2565
f6936e29 2566 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
88595ac9
DV		 2567 fb = &plane_config->fb->base;
2568 goto valid_fb;
f55548b5 2569 }
484b41dd 2570
2d14030b 2571 kfree(plane_config->fb);
484b41dd
JB		 2572
2573 /*
2574 * Failed to alloc the obj, check to see if we should share
2575 * an fb with another CRTC instead
2576 */
70e1e0ec 2577 for_each_crtc(dev, c) {
484b41dd
JB		 2578 i = to_intel_crtc(c);
2579
2580 if (c == &intel_crtc->base)
2581 continue;
2582
2ff8fde1
MR		 2583 if (!i->active)
2584 continue;
2585
88595ac9
DV		 2586 fb = c->primary->fb;
2587 if (!fb)
484b41dd
JB		 2588 continue;
2589
88595ac9 2590 obj = intel_fb_obj(fb);
2ff8fde1 2591 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
88595ac9
DV		 2592 drm_framebuffer_reference(fb);
2593 goto valid_fb;
484b41dd
JB		 2594 }
2595 }
88595ac9
DV		 2596
2597 return;
2598
2599valid_fb:
be5651f2
ML		 2600 plane_state->src_x = plane_state->src_y = 0;
2601 plane_state->src_w = fb->width << 16;
2602 plane_state->src_h = fb->height << 16;
2603
2604 plane_state->crtc_x = plane_state->src_y = 0;
2605 plane_state->crtc_w = fb->width;
2606 plane_state->crtc_h = fb->height;
2607
88595ac9
DV		 2608 obj = intel_fb_obj(fb);
2609 if (obj->tiling_mode != I915_TILING_NONE)
2610 dev_priv->preserve_bios_swizzle = true;
2611
be5651f2
ML		 2612 drm_framebuffer_reference(fb);
2613 primary->fb = primary->state->fb = fb;
36750f28 2614 primary->crtc = primary->state->crtc = &intel_crtc->base;
36750f28 2615 intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
a9ff8714 2616 obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
46f297fb
JB		 2617}
2618
29b9bde6
DV		 2619static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2620 struct drm_framebuffer *fb,
2621 int x, int y)
81255565
JB		 2622{
2623 struct drm_device *dev = crtc->dev;
2624 struct drm_i915_private *dev_priv = dev->dev_private;
2625 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML		 2626 struct drm_plane *primary = crtc->primary;
2627 bool visible = to_intel_plane_state(primary->state)->visible;
c9ba6fad 2628 struct drm_i915_gem_object *obj;
81255565 2629 int plane = intel_crtc->plane;
e506a0c6 2630 unsigned long linear_offset;
81255565 2631 u32 dspcntr;
f45651ba 2632 u32 reg = DSPCNTR(plane);
48404c1e 2633 int pixel_size;
f45651ba 2634
b70709a6 2635 if (!visible || !fb) {
fdd508a6
VS		 2636 I915_WRITE(reg, 0);
2637 if (INTEL_INFO(dev)->gen >= 4)
2638 I915_WRITE(DSPSURF(plane), 0);
2639 else
2640 I915_WRITE(DSPADDR(plane), 0);
2641 POSTING_READ(reg);
2642 return;
2643 }
2644
c9ba6fad
VS		 2645 obj = intel_fb_obj(fb);
2646 if (WARN_ON(obj == NULL))
2647 return;
2648
2649 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2650
f45651ba
VS		 2651 dspcntr = DISPPLANE_GAMMA_ENABLE;
2652
fdd508a6 2653 dspcntr |= DISPLAY_PLANE_ENABLE;
f45651ba
VS		 2654
2655 if (INTEL_INFO(dev)->gen < 4) {
2656 if (intel_crtc->pipe == PIPE_B)
2657 dspcntr |= DISPPLANE_SEL_PIPE_B;
2658
2659 /* pipesrc and dspsize control the size that is scaled from,
2660 * which should always be the user's requested size.
2661 */
2662 I915_WRITE(DSPSIZE(plane),
6e3c9717
ACO		 2663 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2664 (intel_crtc->config->pipe_src_w - 1));
f45651ba 2665 I915_WRITE(DSPPOS(plane), 0);
c14b0485
VS		 2666 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2667 I915_WRITE(PRIMSIZE(plane),
6e3c9717
ACO		 2668 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2669 (intel_crtc->config->pipe_src_w - 1));
c14b0485
VS		 2670 I915_WRITE(PRIMPOS(plane), 0);
2671 I915_WRITE(PRIMCNSTALPHA(plane), 0);
f45651ba 2672 }
81255565 2673
57779d06
VS		 2674 switch (fb->pixel_format) {
2675 case DRM_FORMAT_C8:
81255565
JB		 2676 dspcntr |= DISPPLANE_8BPP;
2677 break;
57779d06 2678 case DRM_FORMAT_XRGB1555:
57779d06 2679 dspcntr |= DISPPLANE_BGRX555;
81255565 2680 break;
57779d06
VS		 2681 case DRM_FORMAT_RGB565:
2682 dspcntr |= DISPPLANE_BGRX565;
2683 break;
2684 case DRM_FORMAT_XRGB8888:
57779d06
VS		 2685 dspcntr |= DISPPLANE_BGRX888;
2686 break;
2687 case DRM_FORMAT_XBGR8888:
57779d06
VS		 2688 dspcntr |= DISPPLANE_RGBX888;
2689 break;
2690 case DRM_FORMAT_XRGB2101010:
57779d06
VS		 2691 dspcntr |= DISPPLANE_BGRX101010;
2692 break;
2693 case DRM_FORMAT_XBGR2101010:
57779d06 2694 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2695 break;
2696 default:
baba133a 2697 BUG();
81255565 2698 }
57779d06 2699
f45651ba
VS		 2700 if (INTEL_INFO(dev)->gen >= 4 &&
2701 obj->tiling_mode != I915_TILING_NONE)
2702 dspcntr |= DISPPLANE_TILED;
81255565 2703
de1aa629
VS		 2704 if (IS_G4X(dev))
2705 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2706
b9897127 2707 linear_offset = y * fb->pitches[0] + x * pixel_size;
81255565 2708
c2c75131
DV		 2709 if (INTEL_INFO(dev)->gen >= 4) {
2710 intel_crtc->dspaddr_offset =
4e9a86b6
VS		 2711 intel_gen4_compute_page_offset(dev_priv,
2712 &x, &y, obj->tiling_mode,
b9897127 2713 pixel_size,
bc752862 2714 fb->pitches[0]);
c2c75131
DV		 2715 linear_offset -= intel_crtc->dspaddr_offset;
2716 } else {
e506a0c6 2717 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2718 }
e506a0c6 2719
8e7d688b 2720 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
48404c1e
SJ		 2721 dspcntr |= DISPPLANE_ROTATE_180;
2722
6e3c9717
ACO		 2723 x += (intel_crtc->config->pipe_src_w - 1);
2724 y += (intel_crtc->config->pipe_src_h - 1);
48404c1e
SJ		 2725
2726 /* Finding the last pixel of the last line of the display
2727 data and adding to linear_offset*/
2728 linear_offset +=
6e3c9717
ACO		 2729 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2730 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
48404c1e
SJ		 2731 }
2732
2733 I915_WRITE(reg, dspcntr);
2734
01f2c773 2735 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2736 if (INTEL_INFO(dev)->gen >= 4) {
85ba7b7d
DV		 2737 I915_WRITE(DSPSURF(plane),
2738 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
5eddb70b 2739 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2740 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2741 } else
f343c5f6 2742 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
5eddb70b 2743 POSTING_READ(reg);
17638cd6
JB		 2744}
2745
29b9bde6
DV		 2746static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2747 struct drm_framebuffer *fb,
2748 int x, int y)
17638cd6
JB		 2749{
2750 struct drm_device *dev = crtc->dev;
2751 struct drm_i915_private *dev_priv = dev->dev_private;
2752 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML		 2753 struct drm_plane *primary = crtc->primary;
2754 bool visible = to_intel_plane_state(primary->state)->visible;
c9ba6fad 2755 struct drm_i915_gem_object *obj;
17638cd6 2756 int plane = intel_crtc->plane;
e506a0c6 2757 unsigned long linear_offset;
17638cd6 2758 u32 dspcntr;
f45651ba 2759 u32 reg = DSPCNTR(plane);
48404c1e 2760 int pixel_size;
f45651ba 2761
b70709a6 2762 if (!visible || !fb) {
fdd508a6
VS		 2763 I915_WRITE(reg, 0);
2764 I915_WRITE(DSPSURF(plane), 0);
2765 POSTING_READ(reg);
2766 return;
2767 }
2768
c9ba6fad
VS		 2769 obj = intel_fb_obj(fb);
2770 if (WARN_ON(obj == NULL))
2771 return;
2772
2773 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2774
f45651ba
VS		 2775 dspcntr = DISPPLANE_GAMMA_ENABLE;
2776
fdd508a6 2777 dspcntr |= DISPLAY_PLANE_ENABLE;
f45651ba
VS		 2778
2779 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2780 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
17638cd6 2781
57779d06
VS		 2782 switch (fb->pixel_format) {
2783 case DRM_FORMAT_C8:
17638cd6
JB		 2784 dspcntr |= DISPPLANE_8BPP;
2785 break;
57779d06
VS		 2786 case DRM_FORMAT_RGB565:
2787 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2788 break;
57779d06 2789 case DRM_FORMAT_XRGB8888:
57779d06
VS		 2790 dspcntr |= DISPPLANE_BGRX888;
2791 break;
2792 case DRM_FORMAT_XBGR8888:
57779d06
VS		 2793 dspcntr |= DISPPLANE_RGBX888;
2794 break;
2795 case DRM_FORMAT_XRGB2101010:
57779d06
VS		 2796 dspcntr |= DISPPLANE_BGRX101010;
2797 break;
2798 case DRM_FORMAT_XBGR2101010:
57779d06 2799 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2800 break;
2801 default:
baba133a 2802 BUG();
17638cd6
JB		 2803 }
2804
2805 if (obj->tiling_mode != I915_TILING_NONE)
2806 dspcntr |= DISPPLANE_TILED;
17638cd6 2807
f45651ba 2808 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
1f5d76db 2809 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
17638cd6 2810
b9897127 2811 linear_offset = y * fb->pitches[0] + x * pixel_size;
c2c75131 2812 intel_crtc->dspaddr_offset =
4e9a86b6
VS		 2813 intel_gen4_compute_page_offset(dev_priv,
2814 &x, &y, obj->tiling_mode,
b9897127 2815 pixel_size,
bc752862 2816 fb->pitches[0]);
c2c75131 2817 linear_offset -= intel_crtc->dspaddr_offset;
8e7d688b 2818 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
48404c1e
SJ		 2819 dspcntr |= DISPPLANE_ROTATE_180;
2820
2821 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
6e3c9717
ACO		 2822 x += (intel_crtc->config->pipe_src_w - 1);
2823 y += (intel_crtc->config->pipe_src_h - 1);
48404c1e
SJ		 2824
2825 /* Finding the last pixel of the last line of the display
2826 data and adding to linear_offset*/
2827 linear_offset +=
6e3c9717
ACO		 2828 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2829 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
48404c1e
SJ		 2830 }
2831 }
2832
2833 I915_WRITE(reg, dspcntr);
17638cd6 2834
01f2c773 2835 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
85ba7b7d
DV		 2836 I915_WRITE(DSPSURF(plane),
2837 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
b3dc685e 2838 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
bc1c91eb
DL		 2839 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2840 } else {
2841 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2842 I915_WRITE(DSPLINOFF(plane), linear_offset);
2843 }
17638cd6 2844 POSTING_READ(reg);
17638cd6
JB		 2845}
2846
b321803d
DL		 2847u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2848 uint32_t pixel_format)
2849{
2850 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2851
2852 /*
2853 * The stride is either expressed as a multiple of 64 bytes
2854 * chunks for linear buffers or in number of tiles for tiled
2855 * buffers.
2856 */
2857 switch (fb_modifier) {
2858 case DRM_FORMAT_MOD_NONE:
2859 return 64;
2860 case I915_FORMAT_MOD_X_TILED:
2861 if (INTEL_INFO(dev)->gen == 2)
2862 return 128;
2863 return 512;
2864 case I915_FORMAT_MOD_Y_TILED:
2865 /* No need to check for old gens and Y tiling since this is
2866 * about the display engine and those will be blocked before
2867 * we get here.
2868 */
2869 return 128;
2870 case I915_FORMAT_MOD_Yf_TILED:
2871 if (bits_per_pixel == 8)
2872 return 64;
2873 else
2874 return 128;
2875 default:
2876 MISSING_CASE(fb_modifier);
2877 return 64;
2878 }
2879}
2880
121920fa
TU		 2881unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
2882 struct drm_i915_gem_object *obj)
2883{
9abc4648 2884 const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
121920fa
TU		 2885
2886 if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
9abc4648 2887 view = &i915_ggtt_view_rotated;
121920fa
TU		 2888
2889 return i915_gem_obj_ggtt_offset_view(obj, view);
2890}
2891
e435d6e5
ML		 2892static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
2893{
2894 struct drm_device *dev = intel_crtc->base.dev;
2895 struct drm_i915_private *dev_priv = dev->dev_private;
2896
2897 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
2898 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
2899 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
e435d6e5
ML		 2900}
2901
a1b2278e
CK		 2902/*
2903 * This function detaches (aka. unbinds) unused scalers in hardware
2904 */
0583236e 2905static void skl_detach_scalers(struct intel_crtc *intel_crtc)
a1b2278e 2906{
a1b2278e
CK		 2907 struct intel_crtc_scaler_state *scaler_state;
2908 int i;
2909
a1b2278e
CK		 2910 scaler_state = &intel_crtc->config->scaler_state;
2911
2912 /* loop through and disable scalers that aren't in use */
2913 for (i = 0; i < intel_crtc->num_scalers; i++) {
e435d6e5
ML		 2914 if (!scaler_state->scalers[i].in_use)
2915 skl_detach_scaler(intel_crtc, i);
a1b2278e
CK		 2916 }
2917}
2918
6156a456 2919u32 skl_plane_ctl_format(uint32_t pixel_format)
70d21f0e 2920{
6156a456 2921 switch (pixel_format) {
d161cf7a 2922 case DRM_FORMAT_C8:
c34ce3d1 2923 return PLANE_CTL_FORMAT_INDEXED;
70d21f0e 2924 case DRM_FORMAT_RGB565:
c34ce3d1 2925 return PLANE_CTL_FORMAT_RGB_565;
70d21f0e 2926 case DRM_FORMAT_XBGR8888:
c34ce3d1 2927 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
6156a456 2928 case DRM_FORMAT_XRGB8888:
c34ce3d1 2929 return PLANE_CTL_FORMAT_XRGB_8888;
6156a456
CK		 2930 /*
2931 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2932 * to be already pre-multiplied. We need to add a knob (or a different
2933 * DRM_FORMAT) for user-space to configure that.
2934 */
f75fb42a 2935 case DRM_FORMAT_ABGR8888:
c34ce3d1 2936 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
6156a456 2937 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
6156a456 2938 case DRM_FORMAT_ARGB8888:
c34ce3d1 2939 return PLANE_CTL_FORMAT_XRGB_8888 |
6156a456 2940 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
70d21f0e 2941 case DRM_FORMAT_XRGB2101010:
c34ce3d1 2942 return PLANE_CTL_FORMAT_XRGB_2101010;
70d21f0e 2943 case DRM_FORMAT_XBGR2101010:
c34ce3d1 2944 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
6156a456 2945 case DRM_FORMAT_YUYV:
c34ce3d1 2946 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
6156a456 2947 case DRM_FORMAT_YVYU:
c34ce3d1 2948 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
6156a456 2949 case DRM_FORMAT_UYVY:
c34ce3d1 2950 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
6156a456 2951 case DRM_FORMAT_VYUY:
c34ce3d1 2952 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
70d21f0e 2953 default:
4249eeef 2954 MISSING_CASE(pixel_format);
70d21f0e 2955 }
8cfcba41 2956
c34ce3d1 2957 return 0;
6156a456 2958}
70d21f0e 2959
6156a456
CK		 2960u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
2961{
6156a456 2962 switch (fb_modifier) {
30af77c4 2963 case DRM_FORMAT_MOD_NONE:
70d21f0e 2964 break;
30af77c4 2965 case I915_FORMAT_MOD_X_TILED:
c34ce3d1 2966 return PLANE_CTL_TILED_X;
b321803d 2967 case I915_FORMAT_MOD_Y_TILED:
c34ce3d1 2968 return PLANE_CTL_TILED_Y;
b321803d 2969 case I915_FORMAT_MOD_Yf_TILED:
c34ce3d1 2970 return PLANE_CTL_TILED_YF;
70d21f0e 2971 default:
6156a456 2972 MISSING_CASE(fb_modifier);
70d21f0e 2973 }
8cfcba41 2974
c34ce3d1 2975 return 0;
6156a456 2976}
70d21f0e 2977
6156a456
CK		 2978u32 skl_plane_ctl_rotation(unsigned int rotation)
2979{
3b7a5119 2980 switch (rotation) {
6156a456
CK		 2981 case BIT(DRM_ROTATE_0):
2982 break;
1e8df167
SJ		 2983 /*
2984 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
2985 * while i915 HW rotation is clockwise, thats why this swapping.
2986 */
3b7a5119 2987 case BIT(DRM_ROTATE_90):
1e8df167 2988 return PLANE_CTL_ROTATE_270;
3b7a5119 2989 case BIT(DRM_ROTATE_180):
c34ce3d1 2990 return PLANE_CTL_ROTATE_180;
3b7a5119 2991 case BIT(DRM_ROTATE_270):
1e8df167 2992 return PLANE_CTL_ROTATE_90;
6156a456
CK		 2993 default:
2994 MISSING_CASE(rotation);
2995 }
2996
c34ce3d1 2997 return 0;
6156a456
CK		 2998}
2999
3000static void skylake_update_primary_plane(struct drm_crtc *crtc,
3001 struct drm_framebuffer *fb,
3002 int x, int y)
3003{
3004 struct drm_device *dev = crtc->dev;
3005 struct drm_i915_private *dev_priv = dev->dev_private;
3006 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML		 3007 struct drm_plane *plane = crtc->primary;
3008 bool visible = to_intel_plane_state(plane->state)->visible;
6156a456
CK		 3009 struct drm_i915_gem_object *obj;
3010 int pipe = intel_crtc->pipe;
3011 u32 plane_ctl, stride_div, stride;
3012 u32 tile_height, plane_offset, plane_size;
3013 unsigned int rotation;
3014 int x_offset, y_offset;
3015 unsigned long surf_addr;
6156a456
CK		 3016 struct intel_crtc_state *crtc_state = intel_crtc->config;
3017 struct intel_plane_state *plane_state;
3018 int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3019 int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3020 int scaler_id = -1;
3021
6156a456
CK		 3022 plane_state = to_intel_plane_state(plane->state);
3023
b70709a6 3024 if (!visible || !fb) {
6156a456
CK		 3025 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3026 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3027 POSTING_READ(PLANE_CTL(pipe, 0));
3028 return;
3b7a5119 3029 }
70d21f0e 3030
6156a456
CK		 3031 plane_ctl = PLANE_CTL_ENABLE |
3032 PLANE_CTL_PIPE_GAMMA_ENABLE |
3033 PLANE_CTL_PIPE_CSC_ENABLE;
3034
3035 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3036 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3037 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3038
3039 rotation = plane->state->rotation;
3040 plane_ctl |= skl_plane_ctl_rotation(rotation);
3041
b321803d
DL		 3042 obj = intel_fb_obj(fb);
3043 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3044 fb->pixel_format);
3b7a5119
SJ		 3045 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj);
3046
6156a456
CK		 3047 /*
3048 * FIXME: intel_plane_state->src, dst aren't set when transitional
3049 * update_plane helpers are called from legacy paths.
3050 * Once full atomic crtc is available, below check can be avoided.
3051 */
3052 if (drm_rect_width(&plane_state->src)) {
3053 scaler_id = plane_state->scaler_id;
3054 src_x = plane_state->src.x1 >> 16;
3055 src_y = plane_state->src.y1 >> 16;
3056 src_w = drm_rect_width(&plane_state->src) >> 16;
3057 src_h = drm_rect_height(&plane_state->src) >> 16;
3058 dst_x = plane_state->dst.x1;
3059 dst_y = plane_state->dst.y1;
3060 dst_w = drm_rect_width(&plane_state->dst);
3061 dst_h = drm_rect_height(&plane_state->dst);
3062
3063 WARN_ON(x != src_x || y != src_y);
3064 } else {
3065 src_w = intel_crtc->config->pipe_src_w;
3066 src_h = intel_crtc->config->pipe_src_h;
3067 }
3068
3b7a5119
SJ		 3069 if (intel_rotation_90_or_270(rotation)) {
3070 /* stride = Surface height in tiles */
2614f17d 3071 tile_height = intel_tile_height(dev, fb->pixel_format,
3b7a5119
SJ		 3072 fb->modifier[0]);
3073 stride = DIV_ROUND_UP(fb->height, tile_height);
6156a456 3074 x_offset = stride * tile_height - y - src_h;
3b7a5119 3075 y_offset = x;
6156a456 3076 plane_size = (src_w - 1) << 16 | (src_h - 1);
3b7a5119
SJ		 3077 } else {
3078 stride = fb->pitches[0] / stride_div;
3079 x_offset = x;
3080 y_offset = y;
6156a456 3081 plane_size = (src_h - 1) << 16 | (src_w - 1);
3b7a5119
SJ		 3082 }
3083 plane_offset = y_offset << 16 | x_offset;
b321803d 3084
70d21f0e 3085 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3b7a5119
SJ		 3086 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3087 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3088 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
6156a456
CK		 3089
3090 if (scaler_id >= 0) {
3091 uint32_t ps_ctrl = 0;
3092
3093 WARN_ON(!dst_w || !dst_h);
3094 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3095 crtc_state->scaler_state.scalers[scaler_id].mode;
3096 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3097 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3098 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3099 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3100 I915_WRITE(PLANE_POS(pipe, 0), 0);
3101 } else {
3102 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3103 }
3104
121920fa 3105 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
70d21f0e
DL		 3106
3107 POSTING_READ(PLANE_SURF(pipe, 0));
3108}
3109
17638cd6
JB		 3110/* Assume fb object is pinned & idle & fenced and just update base pointers */
3111static int
3112intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3113 int x, int y, enum mode_set_atomic state)
3114{
3115 struct drm_device *dev = crtc->dev;
3116 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 3117
ff2a3117 3118 if (dev_priv->fbc.disable_fbc)
7733b49b 3119 dev_priv->fbc.disable_fbc(dev_priv);
81255565 3120
29b9bde6
DV		 3121 dev_priv->display.update_primary_plane(crtc, fb, x, y);
3122
3123 return 0;
81255565
JB		 3124}
3125
7514747d 3126static void intel_complete_page_flips(struct drm_device *dev)
96a02917 3127{
96a02917
VS		 3128 struct drm_crtc *crtc;
3129
70e1e0ec 3130 for_each_crtc(dev, crtc) {
96a02917
VS		 3131 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3132 enum plane plane = intel_crtc->plane;
3133
3134 intel_prepare_page_flip(dev, plane);
3135 intel_finish_page_flip_plane(dev, plane);
3136 }
7514747d
VS		 3137}
3138
3139static void intel_update_primary_planes(struct drm_device *dev)
3140{
7514747d 3141 struct drm_crtc *crtc;
96a02917 3142
70e1e0ec 3143 for_each_crtc(dev, crtc) {
11c22da6
ML		 3144 struct intel_plane *plane = to_intel_plane(crtc->primary);
3145 struct intel_plane_state *plane_state;
96a02917 3146
11c22da6
ML		 3147 drm_modeset_lock_crtc(crtc, &plane->base);
3148
3149 plane_state = to_intel_plane_state(plane->base.state);
3150
3151 if (plane_state->base.fb)
3152 plane->commit_plane(&plane->base, plane_state);
3153
3154 drm_modeset_unlock_crtc(crtc);
96a02917
VS		 3155 }
3156}
3157
7514747d
VS		 3158void intel_prepare_reset(struct drm_device *dev)
3159{
3160 /* no reset support for gen2 */
3161 if (IS_GEN2(dev))
3162 return;
3163
3164 /* reset doesn't touch the display */
3165 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3166 return;
3167
3168 drm_modeset_lock_all(dev);
f98ce92f
VS		 3169 /*
3170 * Disabling the crtcs gracefully seems nicer. Also the
3171 * g33 docs say we should at least disable all the planes.
3172 */
6b72d486 3173 intel_display_suspend(dev);
7514747d
VS		 3174}
3175
3176void intel_finish_reset(struct drm_device *dev)
3177{
3178 struct drm_i915_private *dev_priv = to_i915(dev);
3179
3180 /*
3181 * Flips in the rings will be nuked by the reset,
3182 * so complete all pending flips so that user space
3183 * will get its events and not get stuck.
3184 */
3185 intel_complete_page_flips(dev);
3186
3187 /* no reset support for gen2 */
3188 if (IS_GEN2(dev))
3189 return;
3190
3191 /* reset doesn't touch the display */
3192 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3193 /*
3194 * Flips in the rings have been nuked by the reset,
3195 * so update the base address of all primary
3196 * planes to the the last fb to make sure we're
3197 * showing the correct fb after a reset.
11c22da6
ML		 3198 *
3199 * FIXME: Atomic will make this obsolete since we won't schedule
3200 * CS-based flips (which might get lost in gpu resets) any more.
7514747d
VS		 3201 */
3202 intel_update_primary_planes(dev);
3203 return;
3204 }
3205
3206 /*
3207 * The display has been reset as well,
3208 * so need a full re-initialization.
3209 */
3210 intel_runtime_pm_disable_interrupts(dev_priv);
3211 intel_runtime_pm_enable_interrupts(dev_priv);
3212
3213 intel_modeset_init_hw(dev);
3214
3215 spin_lock_irq(&dev_priv->irq_lock);
3216 if (dev_priv->display.hpd_irq_setup)
3217 dev_priv->display.hpd_irq_setup(dev);
3218 spin_unlock_irq(&dev_priv->irq_lock);
3219
043e9bda 3220 intel_display_resume(dev);
7514747d
VS		 3221
3222 intel_hpd_init(dev_priv);
3223
3224 drm_modeset_unlock_all(dev);
3225}
3226
2e2f351d 3227static void
14667a4b
CW		 3228intel_finish_fb(struct drm_framebuffer *old_fb)
3229{
2ff8fde1 3230 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
2e2f351d 3231 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
14667a4b
CW		 3232 bool was_interruptible = dev_priv->mm.interruptible;
3233 int ret;
3234
14667a4b
CW		 3235 /* Big Hammer, we also need to ensure that any pending
3236 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3237 * current scanout is retired before unpinning the old
2e2f351d
CW		 3238 * framebuffer. Note that we rely on userspace rendering
3239 * into the buffer attached to the pipe they are waiting
3240 * on. If not, userspace generates a GPU hang with IPEHR
3241 * point to the MI_WAIT_FOR_EVENT.
14667a4b
CW		 3242 *
3243 * This should only fail upon a hung GPU, in which case we
3244 * can safely continue.
3245 */
3246 dev_priv->mm.interruptible = false;
2e2f351d 3247 ret = i915_gem_object_wait_rendering(obj, true);
14667a4b
CW		 3248 dev_priv->mm.interruptible = was_interruptible;
3249
2e2f351d 3250 WARN_ON(ret);
14667a4b
CW		 3251}
3252
7d5e3799
CW		 3253static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3254{
3255 struct drm_device *dev = crtc->dev;
3256 struct drm_i915_private *dev_priv = dev->dev_private;
3257 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7d5e3799
CW		 3258 bool pending;
3259
3260 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3261 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3262 return false;
3263
5e2d7afc 3264 spin_lock_irq(&dev->event_lock);
7d5e3799 3265 pending = to_intel_crtc(crtc)->unpin_work != NULL;
5e2d7afc 3266 spin_unlock_irq(&dev->event_lock);
7d5e3799
CW		 3267
3268 return pending;
3269}
3270
bfd16b2a
ML		 3271static void intel_update_pipe_config(struct intel_crtc *crtc,
3272 struct intel_crtc_state *old_crtc_state)
e30e8f75
GP		 3273{
3274 struct drm_device *dev = crtc->base.dev;
3275 struct drm_i915_private *dev_priv = dev->dev_private;
bfd16b2a
ML		 3276 struct intel_crtc_state *pipe_config =
3277 to_intel_crtc_state(crtc->base.state);
e30e8f75 3278
bfd16b2a
ML		 3279 /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3280 crtc->base.mode = crtc->base.state->mode;
3281
3282 DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3283 old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h,
3284 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
e30e8f75 3285
44522d85
ML		 3286 if (HAS_DDI(dev))
3287 intel_set_pipe_csc(&crtc->base);
3288
e30e8f75
GP		 3289 /*
3290 * Update pipe size and adjust fitter if needed: the reason for this is
3291 * that in compute_mode_changes we check the native mode (not the pfit
3292 * mode) to see if we can flip rather than do a full mode set. In the
3293 * fastboot case, we'll flip, but if we don't update the pipesrc and
3294 * pfit state, we'll end up with a big fb scanned out into the wrong
3295 * sized surface.
e30e8f75
GP		 3296 */
3297
e30e8f75 3298 I915_WRITE(PIPESRC(crtc->pipe),
bfd16b2a
ML		 3299 ((pipe_config->pipe_src_w - 1) << 16) |
3300 (pipe_config->pipe_src_h - 1));
3301
3302 /* on skylake this is done by detaching scalers */
3303 if (INTEL_INFO(dev)->gen >= 9) {
3304 skl_detach_scalers(crtc);
3305
3306 if (pipe_config->pch_pfit.enabled)
3307 skylake_pfit_enable(crtc);
3308 } else if (HAS_PCH_SPLIT(dev)) {
3309 if (pipe_config->pch_pfit.enabled)
3310 ironlake_pfit_enable(crtc);
3311 else if (old_crtc_state->pch_pfit.enabled)
3312 ironlake_pfit_disable(crtc, true);
e30e8f75 3313 }
e30e8f75
GP		 3314}
3315
5e84e1a4
ZW		 3316static void intel_fdi_normal_train(struct drm_crtc *crtc)
3317{
3318 struct drm_device *dev = crtc->dev;
3319 struct drm_i915_private *dev_priv = dev->dev_private;
3320 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3321 int pipe = intel_crtc->pipe;
3322 u32 reg, temp;
3323
3324 /* enable normal train */
3325 reg = FDI_TX_CTL(pipe);
3326 temp = I915_READ(reg);
61e499bf 3327 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 3328 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3329 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 3330 } else {
3331 temp &= ~FDI_LINK_TRAIN_NONE;
3332 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 3333 }
5e84e1a4
ZW		 3334 I915_WRITE(reg, temp);
3335
3336 reg = FDI_RX_CTL(pipe);
3337 temp = I915_READ(reg);
3338 if (HAS_PCH_CPT(dev)) {
3339 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3340 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3341 } else {
3342 temp &= ~FDI_LINK_TRAIN_NONE;
3343 temp |= FDI_LINK_TRAIN_NONE;
3344 }
3345 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3346
3347 /* wait one idle pattern time */
3348 POSTING_READ(reg);
3349 udelay(1000);
357555c0
JB		 3350
3351 /* IVB wants error correction enabled */
3352 if (IS_IVYBRIDGE(dev))
3353 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3354 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 3355}
3356
8db9d77b
ZW		 3357/* The FDI link training functions for ILK/Ibexpeak. */
3358static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3359{
3360 struct drm_device *dev = crtc->dev;
3361 struct drm_i915_private *dev_priv = dev->dev_private;
3362 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3363 int pipe = intel_crtc->pipe;
5eddb70b 3364 u32 reg, temp, tries;
8db9d77b 3365
1c8562f6 3366 /* FDI needs bits from pipe first */
0fc932b8 3367 assert_pipe_enabled(dev_priv, pipe);
0fc932b8 3368
e1a44743
AJ		 3369 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3370 for train result */
5eddb70b
CW		 3371 reg = FDI_RX_IMR(pipe);
3372 temp = I915_READ(reg);
e1a44743
AJ		 3373 temp &= ~FDI_RX_SYMBOL_LOCK;
3374 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 3375 I915_WRITE(reg, temp);
3376 I915_READ(reg);
e1a44743
AJ		 3377 udelay(150);
3378
8db9d77b 3379 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 3380 reg = FDI_TX_CTL(pipe);
3381 temp = I915_READ(reg);
627eb5a3 3382 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3383 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
8db9d77b
ZW		 3384 temp &= ~FDI_LINK_TRAIN_NONE;
3385 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 3386 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 3387
5eddb70b
CW		 3388 reg = FDI_RX_CTL(pipe);
3389 temp = I915_READ(reg);
8db9d77b
ZW		 3390 temp &= ~FDI_LINK_TRAIN_NONE;
3391 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 3392 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3393
3394 POSTING_READ(reg);
8db9d77b
ZW		 3395 udelay(150);
3396
5b2adf89 3397 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 3398 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3399 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3400 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 3401
5eddb70b 3402 reg = FDI_RX_IIR(pipe);
e1a44743 3403 for (tries = 0; tries < 5; tries++) {
5eddb70b 3404 temp = I915_READ(reg);
8db9d77b
ZW		 3405 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3406
3407 if ((temp & FDI_RX_BIT_LOCK)) {
3408 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 3409 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 3410 break;
3411 }
8db9d77b 3412 }
e1a44743 3413 if (tries == 5)
5eddb70b 3414 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 3415
3416 /* Train 2 */
5eddb70b
CW		 3417 reg = FDI_TX_CTL(pipe);
3418 temp = I915_READ(reg);
8db9d77b
ZW		 3419 temp &= ~FDI_LINK_TRAIN_NONE;
3420 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 3421 I915_WRITE(reg, temp);
8db9d77b 3422
5eddb70b
CW		 3423 reg = FDI_RX_CTL(pipe);
3424 temp = I915_READ(reg);
8db9d77b
ZW		 3425 temp &= ~FDI_LINK_TRAIN_NONE;
3426 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 3427 I915_WRITE(reg, temp);
8db9d77b 3428
5eddb70b
CW		 3429 POSTING_READ(reg);
3430 udelay(150);
8db9d77b 3431
5eddb70b 3432 reg = FDI_RX_IIR(pipe);
e1a44743 3433 for (tries = 0; tries < 5; tries++) {
5eddb70b 3434 temp = I915_READ(reg);
8db9d77b
ZW		 3435 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3436
3437 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 3438 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 3439 DRM_DEBUG_KMS("FDI train 2 done.\n");
3440 break;
3441 }
8db9d77b 3442 }
e1a44743 3443 if (tries == 5)
5eddb70b 3444 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 3445
3446 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 3447
8db9d77b
ZW		 3448}
3449
0206e353 3450static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 3451 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3452 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3453 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3454 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3455};
3456
3457/* The FDI link training functions for SNB/Cougarpoint. */
3458static void gen6_fdi_link_train(struct drm_crtc *crtc)
3459{
3460 struct drm_device *dev = crtc->dev;
3461 struct drm_i915_private *dev_priv = dev->dev_private;
3462 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3463 int pipe = intel_crtc->pipe;
fa37d39e 3464 u32 reg, temp, i, retry;
8db9d77b 3465
e1a44743
AJ		 3466 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3467 for train result */
5eddb70b
CW		 3468 reg = FDI_RX_IMR(pipe);
3469 temp = I915_READ(reg);
e1a44743
AJ		 3470 temp &= ~FDI_RX_SYMBOL_LOCK;
3471 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 3472 I915_WRITE(reg, temp);
3473
3474 POSTING_READ(reg);
e1a44743
AJ		 3475 udelay(150);
3476
8db9d77b 3477 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 3478 reg = FDI_TX_CTL(pipe);
3479 temp = I915_READ(reg);
627eb5a3 3480 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3481 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
8db9d77b
ZW		 3482 temp &= ~FDI_LINK_TRAIN_NONE;
3483 temp |= FDI_LINK_TRAIN_PATTERN_1;
3484 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3485 /* SNB-B */
3486 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 3487 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 3488
d74cf324
DV		 3489 I915_WRITE(FDI_RX_MISC(pipe),
3490 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3491
5eddb70b
CW		 3492 reg = FDI_RX_CTL(pipe);
3493 temp = I915_READ(reg);
8db9d77b
ZW		 3494 if (HAS_PCH_CPT(dev)) {
3495 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3496 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3497 } else {
3498 temp &= ~FDI_LINK_TRAIN_NONE;
3499 temp |= FDI_LINK_TRAIN_PATTERN_1;
3500 }
5eddb70b
CW		 3501 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3502
3503 POSTING_READ(reg);
8db9d77b
ZW		 3504 udelay(150);
3505
0206e353 3506 for (i = 0; i < 4; i++) {
5eddb70b
CW		 3507 reg = FDI_TX_CTL(pipe);
3508 temp = I915_READ(reg);
8db9d77b
ZW		 3509 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3510 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 3511 I915_WRITE(reg, temp);
3512
3513 POSTING_READ(reg);
8db9d77b
ZW		 3514 udelay(500);
3515
fa37d39e
SP		 3516 for (retry = 0; retry < 5; retry++) {
3517 reg = FDI_RX_IIR(pipe);
3518 temp = I915_READ(reg);
3519 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3520 if (temp & FDI_RX_BIT_LOCK) {
3521 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3522 DRM_DEBUG_KMS("FDI train 1 done.\n");
3523 break;
3524 }
3525 udelay(50);
8db9d77b 3526 }
fa37d39e
SP		 3527 if (retry < 5)
3528 break;
8db9d77b
ZW		 3529 }
3530 if (i == 4)
5eddb70b 3531 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 3532
3533 /* Train 2 */
5eddb70b
CW		 3534 reg = FDI_TX_CTL(pipe);
3535 temp = I915_READ(reg);
8db9d77b
ZW		 3536 temp &= ~FDI_LINK_TRAIN_NONE;
3537 temp |= FDI_LINK_TRAIN_PATTERN_2;
3538 if (IS_GEN6(dev)) {
3539 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3540 /* SNB-B */
3541 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3542 }
5eddb70b 3543 I915_WRITE(reg, temp);
8db9d77b 3544
5eddb70b
CW		 3545 reg = FDI_RX_CTL(pipe);
3546 temp = I915_READ(reg);
8db9d77b
ZW		 3547 if (HAS_PCH_CPT(dev)) {
3548 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3549 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3550 } else {
3551 temp &= ~FDI_LINK_TRAIN_NONE;
3552 temp |= FDI_LINK_TRAIN_PATTERN_2;
3553 }
5eddb70b
CW		 3554 I915_WRITE(reg, temp);
3555
3556 POSTING_READ(reg);
8db9d77b
ZW		 3557 udelay(150);
3558
0206e353 3559 for (i = 0; i < 4; i++) {
5eddb70b
CW		 3560 reg = FDI_TX_CTL(pipe);
3561 temp = I915_READ(reg);
8db9d77b
ZW		 3562 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3563 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 3564 I915_WRITE(reg, temp);
3565
3566 POSTING_READ(reg);
8db9d77b
ZW		 3567 udelay(500);
3568
fa37d39e
SP		 3569 for (retry = 0; retry < 5; retry++) {
3570 reg = FDI_RX_IIR(pipe);
3571 temp = I915_READ(reg);
3572 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3573 if (temp & FDI_RX_SYMBOL_LOCK) {
3574 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3575 DRM_DEBUG_KMS("FDI train 2 done.\n");
3576 break;
3577 }
3578 udelay(50);
8db9d77b 3579 }
fa37d39e
SP		 3580 if (retry < 5)
3581 break;
8db9d77b
ZW		 3582 }
3583 if (i == 4)
5eddb70b 3584 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 3585
3586 DRM_DEBUG_KMS("FDI train done.\n");
3587}
3588
357555c0
JB		 3589/* Manual link training for Ivy Bridge A0 parts */
3590static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3591{
3592 struct drm_device *dev = crtc->dev;
3593 struct drm_i915_private *dev_priv = dev->dev_private;
3594 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3595 int pipe = intel_crtc->pipe;
139ccd3f 3596 u32 reg, temp, i, j;
357555c0
JB		 3597
3598 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3599 for train result */
3600 reg = FDI_RX_IMR(pipe);
3601 temp = I915_READ(reg);
3602 temp &= ~FDI_RX_SYMBOL_LOCK;
3603 temp &= ~FDI_RX_BIT_LOCK;
3604 I915_WRITE(reg, temp);
3605
3606 POSTING_READ(reg);
3607 udelay(150);
3608
01a415fd
DV		 3609 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3610 I915_READ(FDI_RX_IIR(pipe)));
3611
139ccd3f
JB		 3612 /* Try each vswing and preemphasis setting twice before moving on */
3613 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3614 /* disable first in case we need to retry */
3615 reg = FDI_TX_CTL(pipe);
3616 temp = I915_READ(reg);
3617 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3618 temp &= ~FDI_TX_ENABLE;
3619 I915_WRITE(reg, temp);
357555c0 3620
139ccd3f
JB		 3621 reg = FDI_RX_CTL(pipe);
3622 temp = I915_READ(reg);
3623 temp &= ~FDI_LINK_TRAIN_AUTO;
3624 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3625 temp &= ~FDI_RX_ENABLE;
3626 I915_WRITE(reg, temp);
357555c0 3627
139ccd3f 3628 /* enable CPU FDI TX and PCH FDI RX */
357555c0
JB		 3629 reg = FDI_TX_CTL(pipe);
3630 temp = I915_READ(reg);
139ccd3f 3631 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3632 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
139ccd3f 3633 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
357555c0 3634 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
139ccd3f
JB		 3635 temp |= snb_b_fdi_train_param[j/2];
3636 temp |= FDI_COMPOSITE_SYNC;
3637 I915_WRITE(reg, temp | FDI_TX_ENABLE);
357555c0 3638
139ccd3f
JB		 3639 I915_WRITE(FDI_RX_MISC(pipe),
3640 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
357555c0 3641
139ccd3f 3642 reg = FDI_RX_CTL(pipe);
357555c0 3643 temp = I915_READ(reg);
139ccd3f
JB		 3644 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3645 temp |= FDI_COMPOSITE_SYNC;
3646 I915_WRITE(reg, temp | FDI_RX_ENABLE);
357555c0 3647
139ccd3f
JB		 3648 POSTING_READ(reg);
3649 udelay(1); /* should be 0.5us */
357555c0 3650
139ccd3f
JB		 3651 for (i = 0; i < 4; i++) {
3652 reg = FDI_RX_IIR(pipe);
3653 temp = I915_READ(reg);
3654 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 3655
139ccd3f
JB		 3656 if (temp & FDI_RX_BIT_LOCK ||
3657 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3658 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3659 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3660 i);
3661 break;
3662 }
3663 udelay(1); /* should be 0.5us */
3664 }
3665 if (i == 4) {
3666 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3667 continue;
3668 }
357555c0 3669
139ccd3f 3670 /* Train 2 */
357555c0
JB		 3671 reg = FDI_TX_CTL(pipe);
3672 temp = I915_READ(reg);
139ccd3f
JB		 3673 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3674 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3675 I915_WRITE(reg, temp);
3676
3677 reg = FDI_RX_CTL(pipe);
3678 temp = I915_READ(reg);
3679 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3680 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
357555c0
JB		 3681 I915_WRITE(reg, temp);
3682
3683 POSTING_READ(reg);
139ccd3f 3684 udelay(2); /* should be 1.5us */
357555c0 3685
139ccd3f
JB		 3686 for (i = 0; i < 4; i++) {
3687 reg = FDI_RX_IIR(pipe);
3688 temp = I915_READ(reg);
3689 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 3690
139ccd3f
JB		 3691 if (temp & FDI_RX_SYMBOL_LOCK ||
3692 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3693 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3694 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3695 i);
3696 goto train_done;
3697 }
3698 udelay(2); /* should be 1.5us */
357555c0 3699 }
139ccd3f
JB		 3700 if (i == 4)
3701 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
357555c0 3702 }
357555c0 3703
139ccd3f 3704train_done:
357555c0
JB		 3705 DRM_DEBUG_KMS("FDI train done.\n");
3706}
3707
88cefb6c 3708static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 3709{
88cefb6c 3710 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 3711 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 3712 int pipe = intel_crtc->pipe;
5eddb70b 3713 u32 reg, temp;
79e53945 3714
c64e311e 3715
c98e9dcf 3716 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 3717 reg = FDI_RX_CTL(pipe);
3718 temp = I915_READ(reg);
627eb5a3 3719 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
6e3c9717 3720 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
dfd07d72 3721 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 3722 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3723
3724 POSTING_READ(reg);
c98e9dcf
JB		 3725 udelay(200);
3726
3727 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 3728 temp = I915_READ(reg);
3729 I915_WRITE(reg, temp | FDI_PCDCLK);
3730
3731 POSTING_READ(reg);
c98e9dcf
JB		 3732 udelay(200);
3733
20749730
PZ		 3734 /* Enable CPU FDI TX PLL, always on for Ironlake */
3735 reg = FDI_TX_CTL(pipe);
3736 temp = I915_READ(reg);
3737 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3738 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 3739
20749730
PZ		 3740 POSTING_READ(reg);
3741 udelay(100);
6be4a607 3742 }
0e23b99d
JB		 3743}
3744
88cefb6c
DV		 3745static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3746{
3747 struct drm_device *dev = intel_crtc->base.dev;
3748 struct drm_i915_private *dev_priv = dev->dev_private;
3749 int pipe = intel_crtc->pipe;
3750 u32 reg, temp;
3751
3752 /* Switch from PCDclk to Rawclk */
3753 reg = FDI_RX_CTL(pipe);
3754 temp = I915_READ(reg);
3755 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3756
3757 /* Disable CPU FDI TX PLL */
3758 reg = FDI_TX_CTL(pipe);
3759 temp = I915_READ(reg);
3760 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3761
3762 POSTING_READ(reg);
3763 udelay(100);
3764
3765 reg = FDI_RX_CTL(pipe);
3766 temp = I915_READ(reg);
3767 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3768
3769 /* Wait for the clocks to turn off. */
3770 POSTING_READ(reg);
3771 udelay(100);
3772}
3773
0fc932b8
JB		 3774static void ironlake_fdi_disable(struct drm_crtc *crtc)
3775{
3776 struct drm_device *dev = crtc->dev;
3777 struct drm_i915_private *dev_priv = dev->dev_private;
3778 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3779 int pipe = intel_crtc->pipe;
3780 u32 reg, temp;
3781
3782 /* disable CPU FDI tx and PCH FDI rx */
3783 reg = FDI_TX_CTL(pipe);
3784 temp = I915_READ(reg);
3785 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3786 POSTING_READ(reg);
3787
3788 reg = FDI_RX_CTL(pipe);
3789 temp = I915_READ(reg);
3790 temp &= ~(0x7 << 16);
dfd07d72 3791 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 3792 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3793
3794 POSTING_READ(reg);
3795 udelay(100);
3796
3797 /* Ironlake workaround, disable clock pointer after downing FDI */
eba905b2 3798 if (HAS_PCH_IBX(dev))
6f06ce18 3799 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
0fc932b8
JB		 3800
3801 /* still set train pattern 1 */
3802 reg = FDI_TX_CTL(pipe);
3803 temp = I915_READ(reg);
3804 temp &= ~FDI_LINK_TRAIN_NONE;
3805 temp |= FDI_LINK_TRAIN_PATTERN_1;
3806 I915_WRITE(reg, temp);
3807
3808 reg = FDI_RX_CTL(pipe);
3809 temp = I915_READ(reg);
3810 if (HAS_PCH_CPT(dev)) {
3811 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3812 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3813 } else {
3814 temp &= ~FDI_LINK_TRAIN_NONE;
3815 temp |= FDI_LINK_TRAIN_PATTERN_1;
3816 }
3817 /* BPC in FDI rx is consistent with that in PIPECONF */
3818 temp &= ~(0x07 << 16);
dfd07d72 3819 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 3820 I915_WRITE(reg, temp);
3821
3822 POSTING_READ(reg);
3823 udelay(100);
3824}
3825
5dce5b93
CW		 3826bool intel_has_pending_fb_unpin(struct drm_device *dev)
3827{
3828 struct intel_crtc *crtc;
3829
3830 /* Note that we don't need to be called with mode_config.lock here
3831 * as our list of CRTC objects is static for the lifetime of the
3832 * device and so cannot disappear as we iterate. Similarly, we can
3833 * happily treat the predicates as racy, atomic checks as userspace
3834 * cannot claim and pin a new fb without at least acquring the
3835 * struct_mutex and so serialising with us.
3836 */
d3fcc808 3837 for_each_intel_crtc(dev, crtc) {
5dce5b93
CW		 3838 if (atomic_read(&crtc->unpin_work_count) == 0)
3839 continue;
3840
3841 if (crtc->unpin_work)
3842 intel_wait_for_vblank(dev, crtc->pipe);
3843
3844 return true;
3845 }
3846
3847 return false;
3848}
3849
d6bbafa1
CW		 3850static void page_flip_completed(struct intel_crtc *intel_crtc)
3851{
3852 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3853 struct intel_unpin_work *work = intel_crtc->unpin_work;
3854
3855 /* ensure that the unpin work is consistent wrt ->pending. */
3856 smp_rmb();
3857 intel_crtc->unpin_work = NULL;
3858
3859 if (work->event)
3860 drm_send_vblank_event(intel_crtc->base.dev,
3861 intel_crtc->pipe,
3862 work->event);
3863
3864 drm_crtc_vblank_put(&intel_crtc->base);
3865
3866 wake_up_all(&dev_priv->pending_flip_queue);
3867 queue_work(dev_priv->wq, &work->work);
3868
3869 trace_i915_flip_complete(intel_crtc->plane,
3870 work->pending_flip_obj);
3871}
3872
46a55d30 3873void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
e6c3a2a6 3874{
0f91128d 3875 struct drm_device *dev = crtc->dev;
5bb61643 3876 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6 3877
2c10d571 3878 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
9c787942
CW		 3879 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3880 !intel_crtc_has_pending_flip(crtc),
3881 60*HZ) == 0)) {
3882 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2c10d571 3883
5e2d7afc 3884 spin_lock_irq(&dev->event_lock);
9c787942
CW		 3885 if (intel_crtc->unpin_work) {
3886 WARN_ONCE(1, "Removing stuck page flip\n");
3887 page_flip_completed(intel_crtc);
3888 }
5e2d7afc 3889 spin_unlock_irq(&dev->event_lock);
9c787942 3890 }
5bb61643 3891
975d568a
CW		 3892 if (crtc->primary->fb) {
3893 mutex_lock(&dev->struct_mutex);
3894 intel_finish_fb(crtc->primary->fb);
3895 mutex_unlock(&dev->struct_mutex);
3896 }
e6c3a2a6
CW		 3897}
3898
e615efe4
ED		 3899/* Program iCLKIP clock to the desired frequency */
3900static void lpt_program_iclkip(struct drm_crtc *crtc)
3901{
3902 struct drm_device *dev = crtc->dev;
3903 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 3904 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
e615efe4
ED		 3905 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3906 u32 temp;
3907
a580516d 3908 mutex_lock(&dev_priv->sb_lock);
09153000 3909
e615efe4
ED		 3910 /* It is necessary to ungate the pixclk gate prior to programming
3911 * the divisors, and gate it back when it is done.
3912 */
3913 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3914
3915 /* Disable SSCCTL */
3916 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 3917 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3918 SBI_SSCCTL_DISABLE,
3919 SBI_ICLK);
e615efe4
ED		 3920
3921 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
12d7ceed 3922 if (clock == 20000) {
e615efe4
ED		 3923 auxdiv = 1;
3924 divsel = 0x41;
3925 phaseinc = 0x20;
3926 } else {
3927 /* The iCLK virtual clock root frequency is in MHz,
241bfc38
DL		 3928 * but the adjusted_mode->crtc_clock in in KHz. To get the
3929 * divisors, it is necessary to divide one by another, so we
e615efe4
ED		 3930 * convert the virtual clock precision to KHz here for higher
3931 * precision.
3932 */
3933 u32 iclk_virtual_root_freq = 172800 * 1000;
3934 u32 iclk_pi_range = 64;
3935 u32 desired_divisor, msb_divisor_value, pi_value;
3936
12d7ceed 3937 desired_divisor = (iclk_virtual_root_freq / clock);
e615efe4
ED		 3938 msb_divisor_value = desired_divisor / iclk_pi_range;
3939 pi_value = desired_divisor % iclk_pi_range;
3940
3941 auxdiv = 0;
3942 divsel = msb_divisor_value - 2;
3943 phaseinc = pi_value;
3944 }
3945
3946 /* This should not happen with any sane values */
3947 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3948 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3949 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3950 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3951
3952 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
12d7ceed 3953 clock,
e615efe4
ED		 3954 auxdiv,
3955 divsel,
3956 phasedir,
3957 phaseinc);
3958
3959 /* Program SSCDIVINTPHASE6 */
988d6ee8 3960 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 3961 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3962 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3963 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3964 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3965 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3966 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 3967 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 3968
3969 /* Program SSCAUXDIV */
988d6ee8 3970 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 3971 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3972 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 3973 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 3974
3975 /* Enable modulator and associated divider */
988d6ee8 3976 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 3977 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 3978 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 3979
3980 /* Wait for initialization time */
3981 udelay(24);
3982
3983 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000 3984
a580516d 3985 mutex_unlock(&dev_priv->sb_lock);
e615efe4
ED		 3986}
3987
275f01b2
DV		 3988static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3989 enum pipe pch_transcoder)
3990{
3991 struct drm_device *dev = crtc->base.dev;
3992 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 3993 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
275f01b2
DV		 3994
3995 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3996 I915_READ(HTOTAL(cpu_transcoder)));
3997 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3998 I915_READ(HBLANK(cpu_transcoder)));
3999 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4000 I915_READ(HSYNC(cpu_transcoder)));
4001
4002 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4003 I915_READ(VTOTAL(cpu_transcoder)));
4004 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4005 I915_READ(VBLANK(cpu_transcoder)));
4006 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4007 I915_READ(VSYNC(cpu_transcoder)));
4008 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4009 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4010}
4011
003632d9 4012static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
1fbc0d78
DV		 4013{
4014 struct drm_i915_private *dev_priv = dev->dev_private;
4015 uint32_t temp;
4016
4017 temp = I915_READ(SOUTH_CHICKEN1);
003632d9 4018 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
1fbc0d78
DV		 4019 return;
4020
4021 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4022 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4023
003632d9
ACO		 4024 temp &= ~FDI_BC_BIFURCATION_SELECT;
4025 if (enable)
4026 temp |= FDI_BC_BIFURCATION_SELECT;
4027
4028 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
1fbc0d78
DV		 4029 I915_WRITE(SOUTH_CHICKEN1, temp);
4030 POSTING_READ(SOUTH_CHICKEN1);
4031}
4032
4033static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4034{
4035 struct drm_device *dev = intel_crtc->base.dev;
1fbc0d78
DV		 4036
4037 switch (intel_crtc->pipe) {
4038 case PIPE_A:
4039 break;
4040 case PIPE_B:
6e3c9717 4041 if (intel_crtc->config->fdi_lanes > 2)
003632d9 4042 cpt_set_fdi_bc_bifurcation(dev, false);
1fbc0d78 4043 else
003632d9 4044 cpt_set_fdi_bc_bifurcation(dev, true);
1fbc0d78
DV		 4045
4046 break;
4047 case PIPE_C:
003632d9 4048 cpt_set_fdi_bc_bifurcation(dev, true);
1fbc0d78
DV		 4049
4050 break;
4051 default:
4052 BUG();
4053 }
4054}
4055
f67a559d
JB		 4056/*
4057 * Enable PCH resources required for PCH ports:
4058 * - PCH PLLs
4059 * - FDI training & RX/TX
4060 * - update transcoder timings
4061 * - DP transcoding bits
4062 * - transcoder
4063 */
4064static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 4065{
4066 struct drm_device *dev = crtc->dev;
4067 struct drm_i915_private *dev_priv = dev->dev_private;
4068 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4069 int pipe = intel_crtc->pipe;
ee7b9f93 4070 u32 reg, temp;
2c07245f 4071
ab9412ba 4072 assert_pch_transcoder_disabled(dev_priv, pipe);
e7e164db 4073
1fbc0d78
DV		 4074 if (IS_IVYBRIDGE(dev))
4075 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4076
cd986abb
DV		 4077 /* Write the TU size bits before fdi link training, so that error
4078 * detection works. */
4079 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4080 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4081
c98e9dcf 4082 /* For PCH output, training FDI link */
674cf967 4083 dev_priv->display.fdi_link_train(crtc);
2c07245f 4084
3ad8a208
DV		 4085 /* We need to program the right clock selection before writing the pixel
4086 * mutliplier into the DPLL. */
303b81e0 4087 if (HAS_PCH_CPT(dev)) {
ee7b9f93 4088 u32 sel;
4b645f14 4089
c98e9dcf 4090 temp = I915_READ(PCH_DPLL_SEL);
11887397
DV		 4091 temp |= TRANS_DPLL_ENABLE(pipe);
4092 sel = TRANS_DPLLB_SEL(pipe);
6e3c9717 4093 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
ee7b9f93
JB		 4094 temp |= sel;
4095 else
4096 temp &= ~sel;
c98e9dcf 4097 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 4098 }
5eddb70b 4099
3ad8a208
DV		 4100 /* XXX: pch pll's can be enabled any time before we enable the PCH
4101 * transcoder, and we actually should do this to not upset any PCH
4102 * transcoder that already use the clock when we share it.
4103 *
4104 * Note that enable_shared_dpll tries to do the right thing, but
4105 * get_shared_dpll unconditionally resets the pll - we need that to have
4106 * the right LVDS enable sequence. */
85b3894f 4107 intel_enable_shared_dpll(intel_crtc);
3ad8a208 4108
d9b6cb56
JB		 4109 /* set transcoder timing, panel must allow it */
4110 assert_panel_unlocked(dev_priv, pipe);
275f01b2 4111 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
8db9d77b 4112
303b81e0 4113 intel_fdi_normal_train(crtc);
5e84e1a4 4114
c98e9dcf 4115 /* For PCH DP, enable TRANS_DP_CTL */
6e3c9717 4116 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
dfd07d72 4117 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 4118 reg = TRANS_DP_CTL(pipe);
4119 temp = I915_READ(reg);
4120 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 4121 TRANS_DP_SYNC_MASK |
4122 TRANS_DP_BPC_MASK);
e3ef4479 4123 temp |= TRANS_DP_OUTPUT_ENABLE;
9325c9f0 4124 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 4125
4126 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 4127 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 4128 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 4129 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 4130
4131 switch (intel_trans_dp_port_sel(crtc)) {
4132 case PCH_DP_B:
5eddb70b 4133 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 4134 break;
4135 case PCH_DP_C:
5eddb70b 4136 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 4137 break;
4138 case PCH_DP_D:
5eddb70b 4139 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 4140 break;
4141 default:
e95d41e1 4142 BUG();
32f9d658 4143 }
2c07245f 4144
5eddb70b 4145 I915_WRITE(reg, temp);
6be4a607 4146 }
b52eb4dc 4147
b8a4f404 4148 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 4149}
4150
1507e5bd
PZ		 4151static void lpt_pch_enable(struct drm_crtc *crtc)
4152{
4153 struct drm_device *dev = crtc->dev;
4154 struct drm_i915_private *dev_priv = dev->dev_private;
4155 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 4156 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1507e5bd 4157
ab9412ba 4158 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 4159
8c52b5e8 4160 lpt_program_iclkip(crtc);
1507e5bd 4161
0540e488 4162 /* Set transcoder timing. */
275f01b2 4163 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
1507e5bd 4164
937bb610 4165 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 4166}
4167
190f68c5
ACO		 4168struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4169 struct intel_crtc_state *crtc_state)
ee7b9f93 4170{
e2b78267 4171 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8bd31e67 4172 struct intel_shared_dpll *pll;
de419ab6 4173 struct intel_shared_dpll_config *shared_dpll;
e2b78267 4174 enum intel_dpll_id i;
ee7b9f93 4175
de419ab6
ML		 4176 shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);
4177
98b6bd99
DV		 4178 if (HAS_PCH_IBX(dev_priv->dev)) {
4179 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
d94ab068 4180 i = (enum intel_dpll_id) crtc->pipe;
e72f9fbf 4181 pll = &dev_priv->shared_dplls[i];
98b6bd99 4182
46edb027
DV		 4183 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4184 crtc->base.base.id, pll->name);
98b6bd99 4185
de419ab6 4186 WARN_ON(shared_dpll[i].crtc_mask);
f2a69f44 4187
98b6bd99
DV		 4188 goto found;
4189 }
4190
bcddf610
S		 4191 if (IS_BROXTON(dev_priv->dev)) {
4192 /* PLL is attached to port in bxt */
4193 struct intel_encoder *encoder;
4194 struct intel_digital_port *intel_dig_port;
4195
4196 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4197 if (WARN_ON(!encoder))
4198 return NULL;
4199
4200 intel_dig_port = enc_to_dig_port(&encoder->base);
4201 /* 1:1 mapping between ports and PLLs */
4202 i = (enum intel_dpll_id)intel_dig_port->port;
4203 pll = &dev_priv->shared_dplls[i];
4204 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4205 crtc->base.base.id, pll->name);
de419ab6 4206 WARN_ON(shared_dpll[i].crtc_mask);
bcddf610
S		 4207
4208 goto found;
4209 }
4210
e72f9fbf
DV		 4211 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4212 pll = &dev_priv->shared_dplls[i];
ee7b9f93
JB		 4213
4214 /* Only want to check enabled timings first */
de419ab6 4215 if (shared_dpll[i].crtc_mask == 0)
ee7b9f93
JB		 4216 continue;
4217
190f68c5 4218 if (memcmp(&crtc_state->dpll_hw_state,
de419ab6
ML		 4219 &shared_dpll[i].hw_state,
4220 sizeof(crtc_state->dpll_hw_state)) == 0) {
8bd31e67 4221 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
1e6f2ddc 4222 crtc->base.base.id, pll->name,
de419ab6 4223 shared_dpll[i].crtc_mask,
8bd31e67 4224 pll->active);
ee7b9f93
JB		 4225 goto found;
4226 }
4227 }
4228
4229 /* Ok no matching timings, maybe there's a free one? */
e72f9fbf
DV		 4230 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4231 pll = &dev_priv->shared_dplls[i];
de419ab6 4232 if (shared_dpll[i].crtc_mask == 0) {
46edb027
DV		 4233 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4234 crtc->base.base.id, pll->name);
ee7b9f93
JB		 4235 goto found;
4236 }
4237 }
4238
4239 return NULL;
4240
4241found:
de419ab6
ML		 4242 if (shared_dpll[i].crtc_mask == 0)
4243 shared_dpll[i].hw_state =
4244 crtc_state->dpll_hw_state;
f2a69f44 4245
190f68c5 4246 crtc_state->shared_dpll = i;
46edb027
DV		 4247 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4248 pipe_name(crtc->pipe));
ee7b9f93 4249
de419ab6 4250 shared_dpll[i].crtc_mask |= 1 << crtc->pipe;
e04c7350 4251
ee7b9f93
JB		 4252 return pll;
4253}
4254
de419ab6 4255static void intel_shared_dpll_commit(struct drm_atomic_state *state)
8bd31e67 4256{
de419ab6
ML		 4257 struct drm_i915_private *dev_priv = to_i915(state->dev);
4258 struct intel_shared_dpll_config *shared_dpll;
8bd31e67
ACO		 4259 struct intel_shared_dpll *pll;
4260 enum intel_dpll_id i;
4261
de419ab6
ML		 4262 if (!to_intel_atomic_state(state)->dpll_set)
4263 return;
8bd31e67 4264
de419ab6 4265 shared_dpll = to_intel_atomic_state(state)->shared_dpll;
8bd31e67
ACO		 4266 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4267 pll = &dev_priv->shared_dplls[i];
de419ab6 4268 pll->config = shared_dpll[i];
8bd31e67
ACO		 4269 }
4270}
4271
a1520318 4272static void cpt_verify_modeset(struct drm_device *dev, int pipe)
d4270e57
JB		 4273{
4274 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 4275 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 4276 u32 temp;
4277
4278 temp = I915_READ(dslreg);
4279 udelay(500);
4280 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 4281 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 4282 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 4283 }
4284}
4285
86adf9d7
ML		 4286static int
4287skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4288 unsigned scaler_user, int *scaler_id, unsigned int rotation,
4289 int src_w, int src_h, int dst_w, int dst_h)
a1b2278e 4290{
86adf9d7
ML		 4291 struct intel_crtc_scaler_state *scaler_state =
4292 &crtc_state->scaler_state;
4293 struct intel_crtc *intel_crtc =
4294 to_intel_crtc(crtc_state->base.crtc);
a1b2278e 4295 int need_scaling;
6156a456
CK		 4296
4297 need_scaling = intel_rotation_90_or_270(rotation) ?
4298 (src_h != dst_w || src_w != dst_h):
4299 (src_w != dst_w || src_h != dst_h);
a1b2278e
CK		 4300
4301 /*
4302 * if plane is being disabled or scaler is no more required or force detach
4303 * - free scaler binded to this plane/crtc
4304 * - in order to do this, update crtc->scaler_usage
4305 *
4306 * Here scaler state in crtc_state is set free so that
4307 * scaler can be assigned to other user. Actual register
4308 * update to free the scaler is done in plane/panel-fit programming.
4309 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4310 */
86adf9d7 4311 if (force_detach || !need_scaling) {
a1b2278e 4312 if (*scaler_id >= 0) {
86adf9d7 4313 scaler_state->scaler_users &= ~(1 << scaler_user);
a1b2278e
CK		 4314 scaler_state->scalers[*scaler_id].in_use = 0;
4315
86adf9d7
ML		 4316 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4317 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4318 intel_crtc->pipe, scaler_user, *scaler_id,
a1b2278e
CK		 4319 scaler_state->scaler_users);
4320 *scaler_id = -1;
4321 }
4322 return 0;
4323 }
4324
4325 /* range checks */
4326 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4327 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4328
4329 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4330 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
86adf9d7 4331 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
a1b2278e 4332 "size is out of scaler range\n",
86adf9d7 4333 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
a1b2278e
CK		 4334 return -EINVAL;
4335 }
4336
86adf9d7
ML		 4337 /* mark this plane as a scaler user in crtc_state */
4338 scaler_state->scaler_users |= (1 << scaler_user);
4339 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4340 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4341 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4342 scaler_state->scaler_users);
4343
4344 return 0;
4345}
4346
4347/**
4348 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4349 *
4350 * @state: crtc's scaler state
86adf9d7
ML		 4351 *
4352 * Return
4353 * 0 - scaler_usage updated successfully
4354 * error - requested scaling cannot be supported or other error condition
4355 */
e435d6e5 4356int skl_update_scaler_crtc(struct intel_crtc_state *state)
86adf9d7
ML		 4357{
4358 struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4359 struct drm_display_mode *adjusted_mode =
4360 &state->base.adjusted_mode;
4361
4362 DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
4363 intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX);
4364
e435d6e5 4365 return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
86adf9d7
ML		 4366 &state->scaler_state.scaler_id, DRM_ROTATE_0,
4367 state->pipe_src_w, state->pipe_src_h,
8c6cda29 4368 adjusted_mode->hdisplay, adjusted_mode->vdisplay);
86adf9d7
ML		 4369}
4370
4371/**
4372 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4373 *
4374 * @state: crtc's scaler state
86adf9d7
ML		 4375 * @plane_state: atomic plane state to update
4376 *
4377 * Return
4378 * 0 - scaler_usage updated successfully
4379 * error - requested scaling cannot be supported or other error condition
4380 */
da20eabd
ML		 4381static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4382 struct intel_plane_state *plane_state)
86adf9d7
ML		 4383{
4384
4385 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
da20eabd
ML		 4386 struct intel_plane *intel_plane =
4387 to_intel_plane(plane_state->base.plane);
86adf9d7
ML		 4388 struct drm_framebuffer *fb = plane_state->base.fb;
4389 int ret;
4390
4391 bool force_detach = !fb || !plane_state->visible;
4392
4393 DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
4394 intel_plane->base.base.id, intel_crtc->pipe,
4395 drm_plane_index(&intel_plane->base));
4396
4397 ret = skl_update_scaler(crtc_state, force_detach,
4398 drm_plane_index(&intel_plane->base),
4399 &plane_state->scaler_id,
4400 plane_state->base.rotation,
4401 drm_rect_width(&plane_state->src) >> 16,
4402 drm_rect_height(&plane_state->src) >> 16,
4403 drm_rect_width(&plane_state->dst),
4404 drm_rect_height(&plane_state->dst));
4405
4406 if (ret || plane_state->scaler_id < 0)
4407 return ret;
4408
a1b2278e 4409 /* check colorkey */
818ed961 4410 if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
86adf9d7 4411 DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
818ed961 4412 intel_plane->base.base.id);
a1b2278e
CK		 4413 return -EINVAL;
4414 }
4415
4416 /* Check src format */
86adf9d7
ML		 4417 switch (fb->pixel_format) {
4418 case DRM_FORMAT_RGB565:
4419 case DRM_FORMAT_XBGR8888:
4420 case DRM_FORMAT_XRGB8888:
4421 case DRM_FORMAT_ABGR8888:
4422 case DRM_FORMAT_ARGB8888:
4423 case DRM_FORMAT_XRGB2101010:
4424 case DRM_FORMAT_XBGR2101010:
4425 case DRM_FORMAT_YUYV:
4426 case DRM_FORMAT_YVYU:
4427 case DRM_FORMAT_UYVY:
4428 case DRM_FORMAT_VYUY:
4429 break;
4430 default:
4431 DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
4432 intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4433 return -EINVAL;
a1b2278e
CK		 4434 }
4435
a1b2278e
CK		 4436 return 0;
4437}
4438
e435d6e5
ML		 4439static void skylake_scaler_disable(struct intel_crtc *crtc)
4440{
4441 int i;
4442
4443 for (i = 0; i < crtc->num_scalers; i++)
4444 skl_detach_scaler(crtc, i);
4445}
4446
4447static void skylake_pfit_enable(struct intel_crtc *crtc)
bd2e244f
JB		 4448{
4449 struct drm_device *dev = crtc->base.dev;
4450 struct drm_i915_private *dev_priv = dev->dev_private;
4451 int pipe = crtc->pipe;
a1b2278e
CK		 4452 struct intel_crtc_scaler_state *scaler_state =
4453 &crtc->config->scaler_state;
4454
4455 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4456
6e3c9717 4457 if (crtc->config->pch_pfit.enabled) {
a1b2278e
CK		 4458 int id;
4459
4460 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4461 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4462 return;
4463 }
4464
4465 id = scaler_state->scaler_id;
4466 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4467 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4468 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4469 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4470
4471 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
bd2e244f
JB		 4472 }
4473}
4474
b074cec8
JB		 4475static void ironlake_pfit_enable(struct intel_crtc *crtc)
4476{
4477 struct drm_device *dev = crtc->base.dev;
4478 struct drm_i915_private *dev_priv = dev->dev_private;
4479 int pipe = crtc->pipe;
4480
6e3c9717 4481 if (crtc->config->pch_pfit.enabled) {
b074cec8
JB		 4482 /* Force use of hard-coded filter coefficients
4483 * as some pre-programmed values are broken,
4484 * e.g. x201.
4485 */
4486 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4487 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4488 PF_PIPE_SEL_IVB(pipe));
4489 else
4490 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
6e3c9717
ACO		 4491 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4492 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
d4270e57
JB		 4493 }
4494}
4495
20bc8673 4496void hsw_enable_ips(struct intel_crtc *crtc)
d77e4531 4497{
cea165c3
VS		 4498 struct drm_device *dev = crtc->base.dev;
4499 struct drm_i915_private *dev_priv = dev->dev_private;
d77e4531 4500
6e3c9717 4501 if (!crtc->config->ips_enabled)
d77e4531
PZ		 4502 return;
4503
cea165c3
VS		 4504 /* We can only enable IPS after we enable a plane and wait for a vblank */
4505 intel_wait_for_vblank(dev, crtc->pipe);
4506
d77e4531 4507 assert_plane_enabled(dev_priv, crtc->plane);
cea165c3 4508 if (IS_BROADWELL(dev)) {
2a114cc1
BW		 4509 mutex_lock(&dev_priv->rps.hw_lock);
4510 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4511 mutex_unlock(&dev_priv->rps.hw_lock);
4512 /* Quoting Art Runyan: "its not safe to expect any particular
4513 * value in IPS_CTL bit 31 after enabling IPS through the
e59150dc
JB		 4514 * mailbox." Moreover, the mailbox may return a bogus state,
4515 * so we need to just enable it and continue on.
2a114cc1
BW		 4516 */
4517 } else {
4518 I915_WRITE(IPS_CTL, IPS_ENABLE);
4519 /* The bit only becomes 1 in the next vblank, so this wait here
4520 * is essentially intel_wait_for_vblank. If we don't have this
4521 * and don't wait for vblanks until the end of crtc_enable, then
4522 * the HW state readout code will complain that the expected
4523 * IPS_CTL value is not the one we read. */
4524 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4525 DRM_ERROR("Timed out waiting for IPS enable\n");
4526 }
d77e4531
PZ		 4527}
4528
20bc8673 4529void hsw_disable_ips(struct intel_crtc *crtc)
d77e4531
PZ		 4530{
4531 struct drm_device *dev = crtc->base.dev;
4532 struct drm_i915_private *dev_priv = dev->dev_private;
4533
6e3c9717 4534 if (!crtc->config->ips_enabled)
d77e4531
PZ		 4535 return;
4536
4537 assert_plane_enabled(dev_priv, crtc->plane);
23d0b130 4538 if (IS_BROADWELL(dev)) {
2a114cc1
BW		 4539 mutex_lock(&dev_priv->rps.hw_lock);
4540 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4541 mutex_unlock(&dev_priv->rps.hw_lock);
23d0b130
BW		 4542 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4543 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4544 DRM_ERROR("Timed out waiting for IPS disable\n");
e59150dc 4545 } else {
2a114cc1 4546 I915_WRITE(IPS_CTL, 0);
e59150dc
JB		 4547 POSTING_READ(IPS_CTL);
4548 }
d77e4531
PZ		 4549
4550 /* We need to wait for a vblank before we can disable the plane. */
4551 intel_wait_for_vblank(dev, crtc->pipe);
4552}
4553
4554/** Loads the palette/gamma unit for the CRTC with the prepared values */
4555static void intel_crtc_load_lut(struct drm_crtc *crtc)
4556{
4557 struct drm_device *dev = crtc->dev;
4558 struct drm_i915_private *dev_priv = dev->dev_private;
4559 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4560 enum pipe pipe = intel_crtc->pipe;
4561 int palreg = PALETTE(pipe);
4562 int i;
4563 bool reenable_ips = false;
4564
4565 /* The clocks have to be on to load the palette. */
53d9f4e9 4566 if (!crtc->state->active)
d77e4531
PZ		 4567 return;
4568
50360403 4569 if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
409ee761 4570 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
d77e4531
PZ		 4571 assert_dsi_pll_enabled(dev_priv);
4572 else
4573 assert_pll_enabled(dev_priv, pipe);
4574 }
4575
4576 /* use legacy palette for Ironlake */
7a1db49a 4577 if (!HAS_GMCH_DISPLAY(dev))
d77e4531
PZ		 4578 palreg = LGC_PALETTE(pipe);
4579
4580 /* Workaround : Do not read or write the pipe palette/gamma data while
4581 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4582 */
6e3c9717 4583 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
d77e4531
PZ		 4584 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4585 GAMMA_MODE_MODE_SPLIT)) {
4586 hsw_disable_ips(intel_crtc);
4587 reenable_ips = true;
4588 }
4589
4590 for (i = 0; i < 256; i++) {
4591 I915_WRITE(palreg + 4 * i,
4592 (intel_crtc->lut_r[i] << 16) |
4593 (intel_crtc->lut_g[i] << 8) |
4594 intel_crtc->lut_b[i]);
4595 }
4596
4597 if (reenable_ips)
4598 hsw_enable_ips(intel_crtc);
4599}
4600
7cac945f 4601static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
d3eedb1a 4602{
7cac945f 4603 if (intel_crtc->overlay) {
d3eedb1a
VS		 4604 struct drm_device *dev = intel_crtc->base.dev;
4605 struct drm_i915_private *dev_priv = dev->dev_private;
4606
4607 mutex_lock(&dev->struct_mutex);
4608 dev_priv->mm.interruptible = false;
4609 (void) intel_overlay_switch_off(intel_crtc->overlay);
4610 dev_priv->mm.interruptible = true;
4611 mutex_unlock(&dev->struct_mutex);
4612 }
4613
4614 /* Let userspace switch the overlay on again. In most cases userspace
4615 * has to recompute where to put it anyway.
4616 */
4617}
4618
87d4300a
ML		 4619/**
4620 * intel_post_enable_primary - Perform operations after enabling primary plane
4621 * @crtc: the CRTC whose primary plane was just enabled
4622 *
4623 * Performs potentially sleeping operations that must be done after the primary
4624 * plane is enabled, such as updating FBC and IPS. Note that this may be
4625 * called due to an explicit primary plane update, or due to an implicit
4626 * re-enable that is caused when a sprite plane is updated to no longer
4627 * completely hide the primary plane.
4628 */
4629static void
4630intel_post_enable_primary(struct drm_crtc *crtc)
a5c4d7bc
VS		 4631{
4632 struct drm_device *dev = crtc->dev;
87d4300a 4633 struct drm_i915_private *dev_priv = dev->dev_private;
a5c4d7bc
VS		 4634 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4635 int pipe = intel_crtc->pipe;
a5c4d7bc 4636
87d4300a
ML		 4637 /*
4638 * BDW signals flip done immediately if the plane
4639 * is disabled, even if the plane enable is already
4640 * armed to occur at the next vblank :(
4641 */
4642 if (IS_BROADWELL(dev))
4643 intel_wait_for_vblank(dev, pipe);
a5c4d7bc 4644
87d4300a
ML		 4645 /*
4646 * FIXME IPS should be fine as long as one plane is
4647 * enabled, but in practice it seems to have problems
4648 * when going from primary only to sprite only and vice
4649 * versa.
4650 */
a5c4d7bc
VS		 4651 hsw_enable_ips(intel_crtc);
4652
f99d7069 4653 /*
87d4300a
ML		 4654 * Gen2 reports pipe underruns whenever all planes are disabled.
4655 * So don't enable underrun reporting before at least some planes
4656 * are enabled.
4657 * FIXME: Need to fix the logic to work when we turn off all planes
4658 * but leave the pipe running.
f99d7069 4659 */
87d4300a
ML		 4660 if (IS_GEN2(dev))
4661 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4662
4663 /* Underruns don't raise interrupts, so check manually. */
4664 if (HAS_GMCH_DISPLAY(dev))
4665 i9xx_check_fifo_underruns(dev_priv);
a5c4d7bc
VS		 4666}
4667
87d4300a
ML		 4668/**
4669 * intel_pre_disable_primary - Perform operations before disabling primary plane
4670 * @crtc: the CRTC whose primary plane is to be disabled
4671 *
4672 * Performs potentially sleeping operations that must be done before the
4673 * primary plane is disabled, such as updating FBC and IPS. Note that this may
4674 * be called due to an explicit primary plane update, or due to an implicit
4675 * disable that is caused when a sprite plane completely hides the primary
4676 * plane.
4677 */
4678static void
4679intel_pre_disable_primary(struct drm_crtc *crtc)
a5c4d7bc
VS		 4680{
4681 struct drm_device *dev = crtc->dev;
4682 struct drm_i915_private *dev_priv = dev->dev_private;
4683 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4684 int pipe = intel_crtc->pipe;
a5c4d7bc 4685
87d4300a
ML		 4686 /*
4687 * Gen2 reports pipe underruns whenever all planes are disabled.
4688 * So diasble underrun reporting before all the planes get disabled.
4689 * FIXME: Need to fix the logic to work when we turn off all planes
4690 * but leave the pipe running.
4691 */
4692 if (IS_GEN2(dev))
4693 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
a5c4d7bc 4694
87d4300a
ML		 4695 /*
4696 * Vblank time updates from the shadow to live plane control register
4697 * are blocked if the memory self-refresh mode is active at that
4698 * moment. So to make sure the plane gets truly disabled, disable
4699 * first the self-refresh mode. The self-refresh enable bit in turn
4700 * will be checked/applied by the HW only at the next frame start
4701 * event which is after the vblank start event, so we need to have a
4702 * wait-for-vblank between disabling the plane and the pipe.
4703 */
262cd2e1 4704 if (HAS_GMCH_DISPLAY(dev)) {
87d4300a 4705 intel_set_memory_cxsr(dev_priv, false);
262cd2e1
VS		 4706 dev_priv->wm.vlv.cxsr = false;
4707 intel_wait_for_vblank(dev, pipe);
4708 }
87d4300a 4709
87d4300a
ML		 4710 /*
4711 * FIXME IPS should be fine as long as one plane is
4712 * enabled, but in practice it seems to have problems
4713 * when going from primary only to sprite only and vice
4714 * versa.
4715 */
a5c4d7bc 4716 hsw_disable_ips(intel_crtc);
87d4300a
ML		 4717}
4718
ac21b225
ML		 4719static void intel_post_plane_update(struct intel_crtc *crtc)
4720{
4721 struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4722 struct drm_device *dev = crtc->base.dev;
7733b49b 4723 struct drm_i915_private *dev_priv = dev->dev_private;
ac21b225
ML		 4724 struct drm_plane *plane;
4725
4726 if (atomic->wait_vblank)
4727 intel_wait_for_vblank(dev, crtc->pipe);
4728
4729 intel_frontbuffer_flip(dev, atomic->fb_bits);
4730
852eb00d
VS		 4731 if (atomic->disable_cxsr)
4732 crtc->wm.cxsr_allowed = true;
4733
f015c551
VS		 4734 if (crtc->atomic.update_wm_post)
4735 intel_update_watermarks(&crtc->base);
4736
c80ac854 4737 if (atomic->update_fbc)
7733b49b 4738 intel_fbc_update(dev_priv);
ac21b225
ML		 4739
4740 if (atomic->post_enable_primary)
4741 intel_post_enable_primary(&crtc->base);
4742
4743 drm_for_each_plane_mask(plane, dev, atomic->update_sprite_watermarks)
4744 intel_update_sprite_watermarks(plane, &crtc->base,
4745 0, 0, 0, false, false);
4746
4747 memset(atomic, 0, sizeof(*atomic));
4748}
4749
4750static void intel_pre_plane_update(struct intel_crtc *crtc)
4751{
4752 struct drm_device *dev = crtc->base.dev;
eddfcbcd 4753 struct drm_i915_private *dev_priv = dev->dev_private;
ac21b225
ML		 4754 struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4755 struct drm_plane *p;
4756
4757 /* Track fb's for any planes being disabled */
ac21b225
ML		 4758 drm_for_each_plane_mask(p, dev, atomic->disabled_planes) {
4759 struct intel_plane *plane = to_intel_plane(p);
ac21b225
ML		 4760
4761 mutex_lock(&dev->struct_mutex);
a9ff8714
VS		 4762 i915_gem_track_fb(intel_fb_obj(plane->base.fb), NULL,
4763 plane->frontbuffer_bit);
ac21b225
ML		 4764 mutex_unlock(&dev->struct_mutex);
4765 }
4766
4767 if (atomic->wait_for_flips)
4768 intel_crtc_wait_for_pending_flips(&crtc->base);
4769
c80ac854 4770 if (atomic->disable_fbc)
25ad93fd 4771 intel_fbc_disable_crtc(crtc);
ac21b225 4772
066cf55b
RV		 4773 if (crtc->atomic.disable_ips)
4774 hsw_disable_ips(crtc);
4775
ac21b225
ML		 4776 if (atomic->pre_disable_primary)
4777 intel_pre_disable_primary(&crtc->base);
852eb00d
VS		 4778
4779 if (atomic->disable_cxsr) {
4780 crtc->wm.cxsr_allowed = false;
4781 intel_set_memory_cxsr(dev_priv, false);
4782 }
ac21b225
ML		 4783}
4784
d032ffa0 4785static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
87d4300a
ML		 4786{
4787 struct drm_device *dev = crtc->dev;
4788 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
d032ffa0 4789 struct drm_plane *p;
87d4300a
ML		 4790 int pipe = intel_crtc->pipe;
4791
7cac945f 4792 intel_crtc_dpms_overlay_disable(intel_crtc);
27321ae8 4793
d032ffa0
ML		 4794 drm_for_each_plane_mask(p, dev, plane_mask)
4795 to_intel_plane(p)->disable_plane(p, crtc);
f98551ae 4796
f99d7069
DV		 4797 /*
4798 * FIXME: Once we grow proper nuclear flip support out of this we need
4799 * to compute the mask of flip planes precisely. For the time being
4800 * consider this a flip to a NULL plane.
4801 */
4802 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
a5c4d7bc
VS		 4803}
4804
f67a559d
JB		 4805static void ironlake_crtc_enable(struct drm_crtc *crtc)
4806{
4807 struct drm_device *dev = crtc->dev;
4808 struct drm_i915_private *dev_priv = dev->dev_private;
4809 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 4810 struct intel_encoder *encoder;
f67a559d 4811 int pipe = intel_crtc->pipe;
f67a559d 4812
53d9f4e9 4813 if (WARN_ON(intel_crtc->active))
f67a559d
JB		 4814 return;
4815
6e3c9717 4816 if (intel_crtc->config->has_pch_encoder)
b14b1055
DV		 4817 intel_prepare_shared_dpll(intel_crtc);
4818
6e3c9717 4819 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 4820 intel_dp_set_m_n(intel_crtc, M1_N1);
29407aab
DV		 4821
4822 intel_set_pipe_timings(intel_crtc);
4823
6e3c9717 4824 if (intel_crtc->config->has_pch_encoder) {
29407aab 4825 intel_cpu_transcoder_set_m_n(intel_crtc,
6e3c9717 4826 &intel_crtc->config->fdi_m_n, NULL);
29407aab
DV		 4827 }
4828
4829 ironlake_set_pipeconf(crtc);
4830
f67a559d 4831 intel_crtc->active = true;
8664281b 4832
a72e4c9f
DV		 4833 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4834 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
8664281b 4835
f6736a1a 4836 for_each_encoder_on_crtc(dev, crtc, encoder)
952735ee
DV		 4837 if (encoder->pre_enable)
4838 encoder->pre_enable(encoder);
f67a559d 4839
6e3c9717 4840 if (intel_crtc->config->has_pch_encoder) {
fff367c7
DV		 4841 /* Note: FDI PLL enabling _must_ be done before we enable the
4842 * cpu pipes, hence this is separate from all the other fdi/pch
4843 * enabling. */
88cefb6c 4844 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 4845 } else {
4846 assert_fdi_tx_disabled(dev_priv, pipe);
4847 assert_fdi_rx_disabled(dev_priv, pipe);
4848 }
f67a559d 4849
b074cec8 4850 ironlake_pfit_enable(intel_crtc);
f67a559d 4851
9c54c0dd
JB		 4852 /*
4853 * On ILK+ LUT must be loaded before the pipe is running but with
4854 * clocks enabled
4855 */
4856 intel_crtc_load_lut(crtc);
4857
f37fcc2a 4858 intel_update_watermarks(crtc);
e1fdc473 4859 intel_enable_pipe(intel_crtc);
f67a559d 4860
6e3c9717 4861 if (intel_crtc->config->has_pch_encoder)
f67a559d 4862 ironlake_pch_enable(crtc);
c98e9dcf 4863
f9b61ff6
DV		 4864 assert_vblank_disabled(crtc);
4865 drm_crtc_vblank_on(crtc);
4866
fa5c73b1
DV		 4867 for_each_encoder_on_crtc(dev, crtc, encoder)
4868 encoder->enable(encoder);
61b77ddd
DV		 4869
4870 if (HAS_PCH_CPT(dev))
a1520318 4871 cpt_verify_modeset(dev, intel_crtc->pipe);
6be4a607
JB		 4872}
4873
42db64ef
PZ		 4874/* IPS only exists on ULT machines and is tied to pipe A. */
4875static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4876{
f5adf94e 4877 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
42db64ef
PZ		 4878}
4879
4f771f10
PZ		 4880static void haswell_crtc_enable(struct drm_crtc *crtc)
4881{
4882 struct drm_device *dev = crtc->dev;
4883 struct drm_i915_private *dev_priv = dev->dev_private;
4884 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4885 struct intel_encoder *encoder;
99d736a2
ML		 4886 int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4887 struct intel_crtc_state *pipe_config =
4888 to_intel_crtc_state(crtc->state);
4f771f10 4889
53d9f4e9 4890 if (WARN_ON(intel_crtc->active))
4f771f10
PZ		 4891 return;
4892
df8ad70c
DV		 4893 if (intel_crtc_to_shared_dpll(intel_crtc))
4894 intel_enable_shared_dpll(intel_crtc);
4895
6e3c9717 4896 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 4897 intel_dp_set_m_n(intel_crtc, M1_N1);
229fca97
DV		 4898
4899 intel_set_pipe_timings(intel_crtc);
4900
6e3c9717
ACO		 4901 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4902 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4903 intel_crtc->config->pixel_multiplier - 1);
ebb69c95
CT		 4904 }
4905
6e3c9717 4906 if (intel_crtc->config->has_pch_encoder) {
229fca97 4907 intel_cpu_transcoder_set_m_n(intel_crtc,
6e3c9717 4908 &intel_crtc->config->fdi_m_n, NULL);
229fca97
DV		 4909 }
4910
4911 haswell_set_pipeconf(crtc);
4912
4913 intel_set_pipe_csc(crtc);
4914
4f771f10 4915 intel_crtc->active = true;
8664281b 4916
a72e4c9f 4917 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4f771f10
PZ		 4918 for_each_encoder_on_crtc(dev, crtc, encoder)
4919 if (encoder->pre_enable)
4920 encoder->pre_enable(encoder);
4921
6e3c9717 4922 if (intel_crtc->config->has_pch_encoder) {
a72e4c9f
DV		 4923 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4924 true);
4fe9467d
ID		 4925 dev_priv->display.fdi_link_train(crtc);
4926 }
4927
1f544388 4928 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 4929
1c132b44 4930 if (INTEL_INFO(dev)->gen >= 9)
e435d6e5 4931 skylake_pfit_enable(intel_crtc);
ff6d9f55 4932 else
1c132b44 4933 ironlake_pfit_enable(intel_crtc);
4f771f10
PZ		 4934
4935 /*
4936 * On ILK+ LUT must be loaded before the pipe is running but with
4937 * clocks enabled
4938 */
4939 intel_crtc_load_lut(crtc);
4940
1f544388 4941 intel_ddi_set_pipe_settings(crtc);
8228c251 4942 intel_ddi_enable_transcoder_func(crtc);
4f771f10 4943
f37fcc2a 4944 intel_update_watermarks(crtc);
e1fdc473 4945 intel_enable_pipe(intel_crtc);
42db64ef 4946
6e3c9717 4947 if (intel_crtc->config->has_pch_encoder)
1507e5bd 4948 lpt_pch_enable(crtc);
4f771f10 4949
6e3c9717 4950 if (intel_crtc->config->dp_encoder_is_mst)
0e32b39c
DA		 4951 intel_ddi_set_vc_payload_alloc(crtc, true);
4952
f9b61ff6
DV		 4953 assert_vblank_disabled(crtc);
4954 drm_crtc_vblank_on(crtc);
4955
8807e55b 4956 for_each_encoder_on_crtc(dev, crtc, encoder) {
4f771f10 4957 encoder->enable(encoder);
8807e55b
JN		 4958 intel_opregion_notify_encoder(encoder, true);
4959 }
4f771f10 4960
e4916946
PZ		 4961 /* If we change the relative order between pipe/planes enabling, we need
4962 * to change the workaround. */
99d736a2
ML		 4963 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
4964 if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
4965 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4966 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4967 }
4f771f10
PZ		 4968}
4969
bfd16b2a 4970static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
3f8dce3a
DV		 4971{
4972 struct drm_device *dev = crtc->base.dev;
4973 struct drm_i915_private *dev_priv = dev->dev_private;
4974 int pipe = crtc->pipe;
4975
4976 /* To avoid upsetting the power well on haswell only disable the pfit if
4977 * it's in use. The hw state code will make sure we get this right. */
bfd16b2a 4978 if (force || crtc->config->pch_pfit.enabled) {
3f8dce3a
DV		 4979 I915_WRITE(PF_CTL(pipe), 0);
4980 I915_WRITE(PF_WIN_POS(pipe), 0);
4981 I915_WRITE(PF_WIN_SZ(pipe), 0);
4982 }
4983}
4984
6be4a607
JB		 4985static void ironlake_crtc_disable(struct drm_crtc *crtc)
4986{
4987 struct drm_device *dev = crtc->dev;
4988 struct drm_i915_private *dev_priv = dev->dev_private;
4989 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 4990 struct intel_encoder *encoder;
6be4a607 4991 int pipe = intel_crtc->pipe;
5eddb70b 4992 u32 reg, temp;
b52eb4dc 4993
ea9d758d
DV		 4994 for_each_encoder_on_crtc(dev, crtc, encoder)
4995 encoder->disable(encoder);
4996
f9b61ff6
DV		 4997 drm_crtc_vblank_off(crtc);
4998 assert_vblank_disabled(crtc);
4999
6e3c9717 5000 if (intel_crtc->config->has_pch_encoder)
a72e4c9f 5001 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
d925c59a 5002
575f7ab7 5003 intel_disable_pipe(intel_crtc);
32f9d658 5004
bfd16b2a 5005 ironlake_pfit_disable(intel_crtc, false);
2c07245f 5006
5a74f70a
VS		 5007 if (intel_crtc->config->has_pch_encoder)
5008 ironlake_fdi_disable(crtc);
5009
bf49ec8c
DV		 5010 for_each_encoder_on_crtc(dev, crtc, encoder)
5011 if (encoder->post_disable)
5012 encoder->post_disable(encoder);
2c07245f 5013
6e3c9717 5014 if (intel_crtc->config->has_pch_encoder) {
d925c59a 5015 ironlake_disable_pch_transcoder(dev_priv, pipe);
6be4a607 5016
d925c59a
DV		 5017 if (HAS_PCH_CPT(dev)) {
5018 /* disable TRANS_DP_CTL */
5019 reg = TRANS_DP_CTL(pipe);
5020 temp = I915_READ(reg);
5021 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5022 TRANS_DP_PORT_SEL_MASK);
5023 temp |= TRANS_DP_PORT_SEL_NONE;
5024 I915_WRITE(reg, temp);
5025
5026 /* disable DPLL_SEL */
5027 temp = I915_READ(PCH_DPLL_SEL);
11887397 5028 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
d925c59a 5029 I915_WRITE(PCH_DPLL_SEL, temp);
9db4a9c7 5030 }
e3421a18 5031
d925c59a
DV		 5032 ironlake_fdi_pll_disable(intel_crtc);
5033 }
e4ca0612
PJ		 5034
5035 intel_crtc->active = false;
5036 intel_update_watermarks(crtc);
6be4a607 5037}
1b3c7a47 5038
4f771f10 5039static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 5040{
4f771f10
PZ		 5041 struct drm_device *dev = crtc->dev;
5042 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 5043 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10 5044 struct intel_encoder *encoder;
6e3c9717 5045 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
ee7b9f93 5046
8807e55b
JN		 5047 for_each_encoder_on_crtc(dev, crtc, encoder) {
5048 intel_opregion_notify_encoder(encoder, false);
4f771f10 5049 encoder->disable(encoder);
8807e55b 5050 }
4f771f10 5051
f9b61ff6
DV		 5052 drm_crtc_vblank_off(crtc);
5053 assert_vblank_disabled(crtc);
5054
6e3c9717 5055 if (intel_crtc->config->has_pch_encoder)
a72e4c9f
DV		 5056 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5057 false);
575f7ab7 5058 intel_disable_pipe(intel_crtc);
4f771f10 5059
6e3c9717 5060 if (intel_crtc->config->dp_encoder_is_mst)
a4bf214f
VS		 5061 intel_ddi_set_vc_payload_alloc(crtc, false);
5062
ad80a810 5063 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 5064
1c132b44 5065 if (INTEL_INFO(dev)->gen >= 9)
e435d6e5 5066 skylake_scaler_disable(intel_crtc);
ff6d9f55 5067 else
bfd16b2a 5068 ironlake_pfit_disable(intel_crtc, false);
4f771f10 5069
1f544388 5070 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10 5071
6e3c9717 5072 if (intel_crtc->config->has_pch_encoder) {
ab4d966c 5073 lpt_disable_pch_transcoder(dev_priv);
1ad960f2 5074 intel_ddi_fdi_disable(crtc);
83616634 5075 }
4f771f10 5076
97b040aa
ID		 5077 for_each_encoder_on_crtc(dev, crtc, encoder)
5078 if (encoder->post_disable)
5079 encoder->post_disable(encoder);
e4ca0612
PJ		 5080
5081 intel_crtc->active = false;
5082 intel_update_watermarks(crtc);
4f771f10
PZ		 5083}
5084
2dd24552
JB		 5085static void i9xx_pfit_enable(struct intel_crtc *crtc)
5086{
5087 struct drm_device *dev = crtc->base.dev;
5088 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 5089 struct intel_crtc_state *pipe_config = crtc->config;
2dd24552 5090
681a8504 5091 if (!pipe_config->gmch_pfit.control)
2dd24552
JB		 5092 return;
5093
2dd24552 5094 /*
c0b03411
DV		 5095 * The panel fitter should only be adjusted whilst the pipe is disabled,
5096 * according to register description and PRM.
2dd24552 5097 */
c0b03411
DV		 5098 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5099 assert_pipe_disabled(dev_priv, crtc->pipe);
2dd24552 5100
b074cec8
JB		 5101 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5102 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5a80c45c
DV		 5103
5104 /* Border color in case we don't scale up to the full screen. Black by
5105 * default, change to something else for debugging. */
5106 I915_WRITE(BCLRPAT(crtc->pipe), 0);
2dd24552
JB		 5107}
5108
d05410f9
DA		 5109static enum intel_display_power_domain port_to_power_domain(enum port port)
5110{
5111 switch (port) {
5112 case PORT_A:
5113 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
5114 case PORT_B:
5115 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
5116 case PORT_C:
5117 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
5118 case PORT_D:
5119 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
d8e19f99
XZ		 5120 case PORT_E:
5121 return POWER_DOMAIN_PORT_DDI_E_2_LANES;
d05410f9
DA		 5122 default:
5123 WARN_ON_ONCE(1);
5124 return POWER_DOMAIN_PORT_OTHER;
5125 }
5126}
5127
77d22dca
ID		 5128#define for_each_power_domain(domain, mask) \
5129 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
5130 if ((1 << (domain)) & (mask))
5131
319be8ae
ID		 5132enum intel_display_power_domain
5133intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5134{
5135 struct drm_device *dev = intel_encoder->base.dev;
5136 struct intel_digital_port *intel_dig_port;
5137
5138 switch (intel_encoder->type) {
5139 case INTEL_OUTPUT_UNKNOWN:
5140 /* Only DDI platforms should ever use this output type */
5141 WARN_ON_ONCE(!HAS_DDI(dev));
5142 case INTEL_OUTPUT_DISPLAYPORT:
5143 case INTEL_OUTPUT_HDMI:
5144 case INTEL_OUTPUT_EDP:
5145 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
d05410f9 5146 return port_to_power_domain(intel_dig_port->port);
0e32b39c
DA		 5147 case INTEL_OUTPUT_DP_MST:
5148 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5149 return port_to_power_domain(intel_dig_port->port);
319be8ae
ID		 5150 case INTEL_OUTPUT_ANALOG:
5151 return POWER_DOMAIN_PORT_CRT;
5152 case INTEL_OUTPUT_DSI:
5153 return POWER_DOMAIN_PORT_DSI;
5154 default:
5155 return POWER_DOMAIN_PORT_OTHER;
5156 }
5157}
5158
5159static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
77d22dca 5160{
319be8ae
ID		 5161 struct drm_device *dev = crtc->dev;
5162 struct intel_encoder *intel_encoder;
5163 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5164 enum pipe pipe = intel_crtc->pipe;
77d22dca
ID		 5165 unsigned long mask;
5166 enum transcoder transcoder;
5167
292b990e
ML		 5168 if (!crtc->state->active)
5169 return 0;
5170
77d22dca
ID		 5171 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
5172
5173 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5174 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
6e3c9717
ACO		 5175 if (intel_crtc->config->pch_pfit.enabled ||
5176 intel_crtc->config->pch_pfit.force_thru)
77d22dca
ID		 5177 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5178
319be8ae
ID		 5179 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5180 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5181
77d22dca
ID		 5182 return mask;
5183}
5184
292b990e 5185static unsigned long modeset_get_crtc_power_domains(struct drm_crtc *crtc)
77d22dca 5186{
292b990e
ML		 5187 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5188 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5189 enum intel_display_power_domain domain;
5190 unsigned long domains, new_domains, old_domains;
77d22dca 5191
292b990e
ML		 5192 old_domains = intel_crtc->enabled_power_domains;
5193 intel_crtc->enabled_power_domains = new_domains = get_crtc_power_domains(crtc);
77d22dca 5194
292b990e
ML		 5195 domains = new_domains & ~old_domains;
5196
5197 for_each_power_domain(domain, domains)
5198 intel_display_power_get(dev_priv, domain);
5199
5200 return old_domains & ~new_domains;
5201}
5202
5203static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5204 unsigned long domains)
5205{
5206 enum intel_display_power_domain domain;
5207
5208 for_each_power_domain(domain, domains)
5209 intel_display_power_put(dev_priv, domain);
5210}
77d22dca 5211
292b990e
ML		 5212static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
5213{
5214 struct drm_device *dev = state->dev;
5215 struct drm_i915_private *dev_priv = dev->dev_private;
5216 unsigned long put_domains[I915_MAX_PIPES] = {};
5217 struct drm_crtc_state *crtc_state;
5218 struct drm_crtc *crtc;
5219 int i;
77d22dca 5220
292b990e
ML		 5221 for_each_crtc_in_state(state, crtc, crtc_state, i) {
5222 if (needs_modeset(crtc->state))
5223 put_domains[to_intel_crtc(crtc)->pipe] =
5224 modeset_get_crtc_power_domains(crtc);
77d22dca
ID		 5225 }
5226
27c329ed
ML		 5227 if (dev_priv->display.modeset_commit_cdclk) {
5228 unsigned int cdclk = to_intel_atomic_state(state)->cdclk;
5229
5230 if (cdclk != dev_priv->cdclk_freq &&
5231 !WARN_ON(!state->allow_modeset))
5232 dev_priv->display.modeset_commit_cdclk(state);
5233 }
50f6e502 5234
292b990e
ML		 5235 for (i = 0; i < I915_MAX_PIPES; i++)
5236 if (put_domains[i])
5237 modeset_put_power_domains(dev_priv, put_domains[i]);
77d22dca
ID		 5238}
5239
adafdc6f
MK		 5240static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
5241{
5242 int max_cdclk_freq = dev_priv->max_cdclk_freq;
5243
5244 if (INTEL_INFO(dev_priv)->gen >= 9 ||
5245 IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5246 return max_cdclk_freq;
5247 else if (IS_CHERRYVIEW(dev_priv))
5248 return max_cdclk_freq*95/100;
5249 else if (INTEL_INFO(dev_priv)->gen < 4)
5250 return 2*max_cdclk_freq*90/100;
5251 else
5252 return max_cdclk_freq*90/100;
5253}
5254
560a7ae4
DL		 5255static void intel_update_max_cdclk(struct drm_device *dev)
5256{
5257 struct drm_i915_private *dev_priv = dev->dev_private;
5258
5259 if (IS_SKYLAKE(dev)) {
5260 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5261
5262 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5263 dev_priv->max_cdclk_freq = 675000;
5264 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5265 dev_priv->max_cdclk_freq = 540000;
5266 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5267 dev_priv->max_cdclk_freq = 450000;
5268 else
5269 dev_priv->max_cdclk_freq = 337500;
5270 } else if (IS_BROADWELL(dev)) {
5271 /*
5272 * FIXME with extra cooling we can allow
5273 * 540 MHz for ULX and 675 Mhz for ULT.
5274 * How can we know if extra cooling is
5275 * available? PCI ID, VTB, something else?
5276 */
5277 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5278 dev_priv->max_cdclk_freq = 450000;
5279 else if (IS_BDW_ULX(dev))
5280 dev_priv->max_cdclk_freq = 450000;
5281 else if (IS_BDW_ULT(dev))
5282 dev_priv->max_cdclk_freq = 540000;
5283 else
5284 dev_priv->max_cdclk_freq = 675000;
0904deaf
MK		 5285 } else if (IS_CHERRYVIEW(dev)) {
5286 dev_priv->max_cdclk_freq = 320000;
560a7ae4
DL		 5287 } else if (IS_VALLEYVIEW(dev)) {
5288 dev_priv->max_cdclk_freq = 400000;
5289 } else {
5290 /* otherwise assume cdclk is fixed */
5291 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5292 }
5293
adafdc6f
MK		 5294 dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
5295
560a7ae4
DL		 5296 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5297 dev_priv->max_cdclk_freq);
adafdc6f
MK		 5298
5299 DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5300 dev_priv->max_dotclk_freq);
560a7ae4
DL		 5301}
5302
5303static void intel_update_cdclk(struct drm_device *dev)
5304{
5305 struct drm_i915_private *dev_priv = dev->dev_private;
5306
5307 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5308 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5309 dev_priv->cdclk_freq);
5310
5311 /*
5312 * Program the gmbus_freq based on the cdclk frequency.
5313 * BSpec erroneously claims we should aim for 4MHz, but
5314 * in fact 1MHz is the correct frequency.
5315 */
5316 if (IS_VALLEYVIEW(dev)) {
5317 /*
5318 * Program the gmbus_freq based on the cdclk frequency.
5319 * BSpec erroneously claims we should aim for 4MHz, but
5320 * in fact 1MHz is the correct frequency.
5321 */
5322 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5323 }
5324
5325 if (dev_priv->max_cdclk_freq == 0)
5326 intel_update_max_cdclk(dev);
5327}
5328
70d0c574 5329static void broxton_set_cdclk(struct drm_device *dev, int frequency)
f8437dd1
VK		 5330{
5331 struct drm_i915_private *dev_priv = dev->dev_private;
5332 uint32_t divider;
5333 uint32_t ratio;
5334 uint32_t current_freq;
5335 int ret;
5336
5337 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5338 switch (frequency) {
5339 case 144000:
5340 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5341 ratio = BXT_DE_PLL_RATIO(60);
5342 break;
5343 case 288000:
5344 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5345 ratio = BXT_DE_PLL_RATIO(60);
5346 break;
5347 case 384000:
5348 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5349 ratio = BXT_DE_PLL_RATIO(60);
5350 break;
5351 case 576000:
5352 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5353 ratio = BXT_DE_PLL_RATIO(60);
5354 break;
5355 case 624000:
5356 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5357 ratio = BXT_DE_PLL_RATIO(65);
5358 break;
5359 case 19200:
5360 /*
5361 * Bypass frequency with DE PLL disabled. Init ratio, divider
5362 * to suppress GCC warning.
5363 */
5364 ratio = 0;
5365 divider = 0;
5366 break;
5367 default:
5368 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5369
5370 return;
5371 }
5372
5373 mutex_lock(&dev_priv->rps.hw_lock);
5374 /* Inform power controller of upcoming frequency change */
5375 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5376 0x80000000);
5377 mutex_unlock(&dev_priv->rps.hw_lock);
5378
5379 if (ret) {
5380 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5381 ret, frequency);
5382 return;
5383 }
5384
5385 current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5386 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5387 current_freq = current_freq * 500 + 1000;
5388
5389 /*
5390 * DE PLL has to be disabled when
5391 * - setting to 19.2MHz (bypass, PLL isn't used)
5392 * - before setting to 624MHz (PLL needs toggling)
5393 * - before setting to any frequency from 624MHz (PLL needs toggling)
5394 */
5395 if (frequency == 19200 || frequency == 624000 ||
5396 current_freq == 624000) {
5397 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5398 /* Timeout 200us */
5399 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5400 1))
5401 DRM_ERROR("timout waiting for DE PLL unlock\n");
5402 }
5403
5404 if (frequency != 19200) {
5405 uint32_t val;
5406
5407 val = I915_READ(BXT_DE_PLL_CTL);
5408 val &= ~BXT_DE_PLL_RATIO_MASK;
5409 val |= ratio;
5410 I915_WRITE(BXT_DE_PLL_CTL, val);
5411
5412 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5413 /* Timeout 200us */
5414 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5415 DRM_ERROR("timeout waiting for DE PLL lock\n");
5416
5417 val = I915_READ(CDCLK_CTL);
5418 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5419 val |= divider;
5420 /*
5421 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5422 * enable otherwise.
5423 */
5424 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5425 if (frequency >= 500000)
5426 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5427
5428 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5429 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5430 val |= (frequency - 1000) / 500;
5431 I915_WRITE(CDCLK_CTL, val);
5432 }
5433
5434 mutex_lock(&dev_priv->rps.hw_lock);
5435 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5436 DIV_ROUND_UP(frequency, 25000));
5437 mutex_unlock(&dev_priv->rps.hw_lock);
5438
5439 if (ret) {
5440 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5441 ret, frequency);
5442 return;
5443 }
5444
a47871bd 5445 intel_update_cdclk(dev);
f8437dd1
VK		 5446}
5447
5448void broxton_init_cdclk(struct drm_device *dev)
5449{
5450 struct drm_i915_private *dev_priv = dev->dev_private;
5451 uint32_t val;
5452
5453 /*
5454 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5455 * or else the reset will hang because there is no PCH to respond.
5456 * Move the handshake programming to initialization sequence.
5457 * Previously was left up to BIOS.
5458 */
5459 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5460 val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5461 I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5462
5463 /* Enable PG1 for cdclk */
5464 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5465
5466 /* check if cd clock is enabled */
5467 if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5468 DRM_DEBUG_KMS("Display already initialized\n");
5469 return;
5470 }
5471
5472 /*
5473 * FIXME:
5474 * - The initial CDCLK needs to be read from VBT.
5475 * Need to make this change after VBT has changes for BXT.
5476 * - check if setting the max (or any) cdclk freq is really necessary
5477 * here, it belongs to modeset time
5478 */
5479 broxton_set_cdclk(dev, 624000);
5480
5481 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
22e02c0b
VS		 5482 POSTING_READ(DBUF_CTL);
5483
f8437dd1
VK		 5484 udelay(10);
5485
5486 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5487 DRM_ERROR("DBuf power enable timeout!\n");
5488}
5489
5490void broxton_uninit_cdclk(struct drm_device *dev)
5491{
5492 struct drm_i915_private *dev_priv = dev->dev_private;
5493
5494 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
22e02c0b
VS		 5495 POSTING_READ(DBUF_CTL);
5496
f8437dd1
VK		 5497 udelay(10);
5498
5499 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5500 DRM_ERROR("DBuf power disable timeout!\n");
5501
5502 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5503 broxton_set_cdclk(dev, 19200);
5504
5505 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5506}
5507
5d96d8af
DL		 5508static const struct skl_cdclk_entry {
5509 unsigned int freq;
5510 unsigned int vco;
5511} skl_cdclk_frequencies[] = {
5512 { .freq = 308570, .vco = 8640 },
5513 { .freq = 337500, .vco = 8100 },
5514 { .freq = 432000, .vco = 8640 },
5515 { .freq = 450000, .vco = 8100 },
5516 { .freq = 540000, .vco = 8100 },
5517 { .freq = 617140, .vco = 8640 },
5518 { .freq = 675000, .vco = 8100 },
5519};
5520
5521static unsigned int skl_cdclk_decimal(unsigned int freq)
5522{
5523 return (freq - 1000) / 500;
5524}
5525
5526static unsigned int skl_cdclk_get_vco(unsigned int freq)
5527{
5528 unsigned int i;
5529
5530 for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5531 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5532
5533 if (e->freq == freq)
5534 return e->vco;
5535 }
5536
5537 return 8100;
5538}
5539
5540static void
5541skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5542{
5543 unsigned int min_freq;
5544 u32 val;
5545
5546 /* select the minimum CDCLK before enabling DPLL 0 */
5547 val = I915_READ(CDCLK_CTL);
5548 val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5549 val |= CDCLK_FREQ_337_308;
5550
5551 if (required_vco == 8640)
5552 min_freq = 308570;
5553 else
5554 min_freq = 337500;
5555
5556 val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5557
5558 I915_WRITE(CDCLK_CTL, val);
5559 POSTING_READ(CDCLK_CTL);
5560
5561 /*
5562 * We always enable DPLL0 with the lowest link rate possible, but still
5563 * taking into account the VCO required to operate the eDP panel at the
5564 * desired frequency. The usual DP link rates operate with a VCO of
5565 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5566 * The modeset code is responsible for the selection of the exact link
5567 * rate later on, with the constraint of choosing a frequency that
5568 * works with required_vco.
5569 */
5570 val = I915_READ(DPLL_CTRL1);
5571
5572 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5573 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5574 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5575 if (required_vco == 8640)
5576 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5577 SKL_DPLL0);
5578 else
5579 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5580 SKL_DPLL0);
5581
5582 I915_WRITE(DPLL_CTRL1, val);
5583 POSTING_READ(DPLL_CTRL1);
5584
5585 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5586
5587 if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5588 DRM_ERROR("DPLL0 not locked\n");
5589}
5590
5591static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5592{
5593 int ret;
5594 u32 val;
5595
5596 /* inform PCU we want to change CDCLK */
5597 val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5598 mutex_lock(&dev_priv->rps.hw_lock);
5599 ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5600 mutex_unlock(&dev_priv->rps.hw_lock);
5601
5602 return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5603}
5604
5605static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5606{
5607 unsigned int i;
5608
5609 for (i = 0; i < 15; i++) {
5610 if (skl_cdclk_pcu_ready(dev_priv))
5611 return true;
5612 udelay(10);
5613 }
5614
5615 return false;
5616}
5617
5618static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5619{
560a7ae4 5620 struct drm_device *dev = dev_priv->dev;
5d96d8af
DL		 5621 u32 freq_select, pcu_ack;
5622
5623 DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5624
5625 if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5626 DRM_ERROR("failed to inform PCU about cdclk change\n");
5627 return;
5628 }
5629
5630 /* set CDCLK_CTL */
5631 switch(freq) {
5632 case 450000:
5633 case 432000:
5634 freq_select = CDCLK_FREQ_450_432;
5635 pcu_ack = 1;
5636 break;
5637 case 540000:
5638 freq_select = CDCLK_FREQ_540;
5639 pcu_ack = 2;
5640 break;
5641 case 308570:
5642 case 337500:
5643 default:
5644 freq_select = CDCLK_FREQ_337_308;
5645 pcu_ack = 0;
5646 break;
5647 case 617140:
5648 case 675000:
5649 freq_select = CDCLK_FREQ_675_617;
5650 pcu_ack = 3;
5651 break;
5652 }
5653
5654 I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5655 POSTING_READ(CDCLK_CTL);
5656
5657 /* inform PCU of the change */
5658 mutex_lock(&dev_priv->rps.hw_lock);
5659 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5660 mutex_unlock(&dev_priv->rps.hw_lock);
560a7ae4
DL		 5661
5662 intel_update_cdclk(dev);
5d96d8af
DL		 5663}
5664
5665void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5666{
5667 /* disable DBUF power */
5668 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5669 POSTING_READ(DBUF_CTL);
5670
5671 udelay(10);
5672
5673 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5674 DRM_ERROR("DBuf power disable timeout\n");
5675
5676 /* disable DPLL0 */
5677 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5678 if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5679 DRM_ERROR("Couldn't disable DPLL0\n");
5680
5681 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5682}
5683
5684void skl_init_cdclk(struct drm_i915_private *dev_priv)
5685{
5686 u32 val;
5687 unsigned int required_vco;
5688
5689 /* enable PCH reset handshake */
5690 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5691 I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
5692
5693 /* enable PG1 and Misc I/O */
5694 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5695
39d9b85a
GW		 5696 /* DPLL0 not enabled (happens on early BIOS versions) */
5697 if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
5698 /* enable DPLL0 */
5699 required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5700 skl_dpll0_enable(dev_priv, required_vco);
5d96d8af
DL		 5701 }
5702
5d96d8af
DL		 5703 /* set CDCLK to the frequency the BIOS chose */
5704 skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5705
5706 /* enable DBUF power */
5707 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5708 POSTING_READ(DBUF_CTL);
5709
5710 udelay(10);
5711
5712 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5713 DRM_ERROR("DBuf power enable timeout\n");
5714}
5715
dfcab17e 5716/* returns HPLL frequency in kHz */
f8bf63fd 5717static int valleyview_get_vco(struct drm_i915_private *dev_priv)
30a970c6 5718{
586f49dc 5719 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
30a970c6 5720
586f49dc 5721 /* Obtain SKU information */
a580516d 5722 mutex_lock(&dev_priv->sb_lock);
586f49dc
JB		 5723 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
5724 CCK_FUSE_HPLL_FREQ_MASK;
a580516d 5725 mutex_unlock(&dev_priv->sb_lock);
30a970c6 5726
dfcab17e 5727 return vco_freq[hpll_freq] * 1000;
30a970c6
JB		 5728}
5729
5730/* Adjust CDclk dividers to allow high res or save power if possible */
5731static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5732{
5733 struct drm_i915_private *dev_priv = dev->dev_private;
5734 u32 val, cmd;
5735
164dfd28
VK		 5736 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5737 != dev_priv->cdclk_freq);
d60c4473 5738
dfcab17e 5739 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
30a970c6 5740 cmd = 2;
dfcab17e 5741 else if (cdclk == 266667)
30a970c6
JB		 5742 cmd = 1;
5743 else
5744 cmd = 0;
5745
5746 mutex_lock(&dev_priv->rps.hw_lock);
5747 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5748 val &= ~DSPFREQGUAR_MASK;
5749 val |= (cmd << DSPFREQGUAR_SHIFT);
5750 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5751 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5752 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5753 50)) {
5754 DRM_ERROR("timed out waiting for CDclk change\n");
5755 }
5756 mutex_unlock(&dev_priv->rps.hw_lock);
5757
54433e91
VS		 5758 mutex_lock(&dev_priv->sb_lock);
5759
dfcab17e 5760 if (cdclk == 400000) {
6bcda4f0 5761 u32 divider;
30a970c6 5762
6bcda4f0 5763 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
30a970c6 5764
30a970c6
JB		 5765 /* adjust cdclk divider */
5766 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
9cf33db5 5767 val &= ~DISPLAY_FREQUENCY_VALUES;
30a970c6
JB		 5768 val |= divider;
5769 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
a877e801
VS		 5770
5771 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5772 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5773 50))
5774 DRM_ERROR("timed out waiting for CDclk change\n");
30a970c6
JB		 5775 }
5776
30a970c6
JB		 5777 /* adjust self-refresh exit latency value */
5778 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5779 val &= ~0x7f;
5780
5781 /*
5782 * For high bandwidth configs, we set a higher latency in the bunit
5783 * so that the core display fetch happens in time to avoid underruns.
5784 */
dfcab17e 5785 if (cdclk == 400000)
30a970c6
JB		 5786 val |= 4500 / 250; /* 4.5 usec */
5787 else
5788 val |= 3000 / 250; /* 3.0 usec */
5789 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
54433e91 5790
a580516d 5791 mutex_unlock(&dev_priv->sb_lock);
30a970c6 5792
b6283055 5793 intel_update_cdclk(dev);
30a970c6
JB		 5794}
5795
383c5a6a
VS		 5796static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5797{
5798 struct drm_i915_private *dev_priv = dev->dev_private;
5799 u32 val, cmd;
5800
164dfd28
VK		 5801 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5802 != dev_priv->cdclk_freq);
383c5a6a
VS		 5803
5804 switch (cdclk) {
383c5a6a
VS		 5805 case 333333:
5806 case 320000:
383c5a6a 5807 case 266667:
383c5a6a 5808 case 200000:
383c5a6a
VS		 5809 break;
5810 default:
5f77eeb0 5811 MISSING_CASE(cdclk);
383c5a6a
VS		 5812 return;
5813 }
5814
9d0d3fda
VS		 5815 /*
5816 * Specs are full of misinformation, but testing on actual
5817 * hardware has shown that we just need to write the desired
5818 * CCK divider into the Punit register.
5819 */
5820 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5821
383c5a6a
VS		 5822 mutex_lock(&dev_priv->rps.hw_lock);
5823 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5824 val &= ~DSPFREQGUAR_MASK_CHV;
5825 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5826 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5827 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5828 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5829 50)) {
5830 DRM_ERROR("timed out waiting for CDclk change\n");
5831 }
5832 mutex_unlock(&dev_priv->rps.hw_lock);
5833
b6283055 5834 intel_update_cdclk(dev);
383c5a6a
VS		 5835}
5836
30a970c6
JB		 5837static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5838 int max_pixclk)
5839{
6bcda4f0 5840 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
6cca3195 5841 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
29dc7ef3 5842
30a970c6
JB		 5843 /*
5844 * Really only a few cases to deal with, as only 4 CDclks are supported:
5845 * 200MHz
5846 * 267MHz
29dc7ef3 5847 * 320/333MHz (depends on HPLL freq)
6cca3195
VS		 5848 * 400MHz (VLV only)
5849 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5850 * of the lower bin and adjust if needed.
e37c67a1
VS		 5851 *
5852 * We seem to get an unstable or solid color picture at 200MHz.
5853 * Not sure what's wrong. For now use 200MHz only when all pipes
5854 * are off.
30a970c6 5855 */
6cca3195
VS		 5856 if (!IS_CHERRYVIEW(dev_priv) &&
5857 max_pixclk > freq_320*limit/100)
dfcab17e 5858 return 400000;
6cca3195 5859 else if (max_pixclk > 266667*limit/100)
29dc7ef3 5860 return freq_320;
e37c67a1 5861 else if (max_pixclk > 0)
dfcab17e 5862 return 266667;
e37c67a1
VS		 5863 else
5864 return 200000;
30a970c6
JB		 5865}
5866
f8437dd1
VK		 5867static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5868 int max_pixclk)
5869{
5870 /*
5871 * FIXME:
5872 * - remove the guardband, it's not needed on BXT
5873 * - set 19.2MHz bypass frequency if there are no active pipes
5874 */
5875 if (max_pixclk > 576000*9/10)
5876 return 624000;
5877 else if (max_pixclk > 384000*9/10)
5878 return 576000;
5879 else if (max_pixclk > 288000*9/10)
5880 return 384000;
5881 else if (max_pixclk > 144000*9/10)
5882 return 288000;
5883 else
5884 return 144000;
5885}
5886
a821fc46
ACO		 5887/* Compute the max pixel clock for new configuration. Uses atomic state if
5888 * that's non-NULL, look at current state otherwise. */
5889static int intel_mode_max_pixclk(struct drm_device *dev,
5890 struct drm_atomic_state *state)
30a970c6 5891{
30a970c6 5892 struct intel_crtc *intel_crtc;
304603f4 5893 struct intel_crtc_state *crtc_state;
30a970c6
JB		 5894 int max_pixclk = 0;
5895
d3fcc808 5896 for_each_intel_crtc(dev, intel_crtc) {
27c329ed 5897 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
304603f4
ACO		 5898 if (IS_ERR(crtc_state))
5899 return PTR_ERR(crtc_state);
5900
5901 if (!crtc_state->base.enable)
5902 continue;
5903
5904 max_pixclk = max(max_pixclk,
5905 crtc_state->base.adjusted_mode.crtc_clock);
30a970c6
JB		 5906 }
5907
5908 return max_pixclk;
5909}
5910
27c329ed 5911static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
30a970c6 5912{
27c329ed
ML		 5913 struct drm_device *dev = state->dev;
5914 struct drm_i915_private *dev_priv = dev->dev_private;
5915 int max_pixclk = intel_mode_max_pixclk(dev, state);
30a970c6 5916
304603f4
ACO		 5917 if (max_pixclk < 0)
5918 return max_pixclk;
30a970c6 5919
27c329ed
ML		 5920 to_intel_atomic_state(state)->cdclk =
5921 valleyview_calc_cdclk(dev_priv, max_pixclk);
0a9ab303 5922
27c329ed
ML		 5923 return 0;
5924}
304603f4 5925
27c329ed
ML		 5926static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state)
5927{
5928 struct drm_device *dev = state->dev;
5929 struct drm_i915_private *dev_priv = dev->dev_private;
5930 int max_pixclk = intel_mode_max_pixclk(dev, state);
85a96e7a 5931
27c329ed
ML		 5932 if (max_pixclk < 0)
5933 return max_pixclk;
85a96e7a 5934
27c329ed
ML		 5935 to_intel_atomic_state(state)->cdclk =
5936 broxton_calc_cdclk(dev_priv, max_pixclk);
85a96e7a 5937
27c329ed 5938 return 0;
30a970c6
JB		 5939}
5940
1e69cd74
VS		 5941static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5942{
5943 unsigned int credits, default_credits;
5944
5945 if (IS_CHERRYVIEW(dev_priv))
5946 default_credits = PFI_CREDIT(12);
5947 else
5948 default_credits = PFI_CREDIT(8);
5949
164dfd28 5950 if (DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
1e69cd74
VS		 5951 /* CHV suggested value is 31 or 63 */
5952 if (IS_CHERRYVIEW(dev_priv))
fcc0008f 5953 credits = PFI_CREDIT_63;
1e69cd74
VS		 5954 else
5955 credits = PFI_CREDIT(15);
5956 } else {
5957 credits = default_credits;
5958 }
5959
5960 /*
5961 * WA - write default credits before re-programming
5962 * FIXME: should we also set the resend bit here?
5963 */
5964 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5965 default_credits);
5966
5967 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5968 credits | PFI_CREDIT_RESEND);
5969
5970 /*
5971 * FIXME is this guaranteed to clear
5972 * immediately or should we poll for it?
5973 */
5974 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
5975}
5976
27c329ed 5977static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
30a970c6 5978{
a821fc46 5979 struct drm_device *dev = old_state->dev;
27c329ed 5980 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
30a970c6 5981 struct drm_i915_private *dev_priv = dev->dev_private;
30a970c6 5982
27c329ed
ML		 5983 /*
5984 * FIXME: We can end up here with all power domains off, yet
5985 * with a CDCLK frequency other than the minimum. To account
5986 * for this take the PIPE-A power domain, which covers the HW
5987 * blocks needed for the following programming. This can be
5988 * removed once it's guaranteed that we get here either with
5989 * the minimum CDCLK set, or the required power domains
5990 * enabled.
5991 */
5992 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
738c05c0 5993
27c329ed
ML		 5994 if (IS_CHERRYVIEW(dev))
5995 cherryview_set_cdclk(dev, req_cdclk);
5996 else
5997 valleyview_set_cdclk(dev, req_cdclk);
738c05c0 5998
27c329ed 5999 vlv_program_pfi_credits(dev_priv);
1e69cd74 6000
27c329ed 6001 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
30a970c6
JB		 6002}
6003
89b667f8
JB		 6004static void valleyview_crtc_enable(struct drm_crtc *crtc)
6005{
6006 struct drm_device *dev = crtc->dev;
a72e4c9f 6007 struct drm_i915_private *dev_priv = to_i915(dev);
89b667f8
JB		 6008 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6009 struct intel_encoder *encoder;
6010 int pipe = intel_crtc->pipe;
23538ef1 6011 bool is_dsi;
89b667f8 6012
53d9f4e9 6013 if (WARN_ON(intel_crtc->active))
89b667f8
JB		 6014 return;
6015
409ee761 6016 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
8525a235 6017
6e3c9717 6018 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 6019 intel_dp_set_m_n(intel_crtc, M1_N1);
5b18e57c
DV		 6020
6021 intel_set_pipe_timings(intel_crtc);
6022
c14b0485
VS		 6023 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6024 struct drm_i915_private *dev_priv = dev->dev_private;
6025
6026 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6027 I915_WRITE(CHV_CANVAS(pipe), 0);
6028 }
6029
5b18e57c
DV		 6030 i9xx_set_pipeconf(intel_crtc);
6031
89b667f8 6032 intel_crtc->active = true;
89b667f8 6033
a72e4c9f 6034 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 6035
89b667f8
JB		 6036 for_each_encoder_on_crtc(dev, crtc, encoder)
6037 if (encoder->pre_pll_enable)
6038 encoder->pre_pll_enable(encoder);
6039
9d556c99 6040 if (!is_dsi) {
c0b4c660
VS		 6041 if (IS_CHERRYVIEW(dev)) {
6042 chv_prepare_pll(intel_crtc, intel_crtc->config);
6e3c9717 6043 chv_enable_pll(intel_crtc, intel_crtc->config);
c0b4c660
VS		 6044 } else {
6045 vlv_prepare_pll(intel_crtc, intel_crtc->config);
6e3c9717 6046 vlv_enable_pll(intel_crtc, intel_crtc->config);
c0b4c660 6047 }
9d556c99 6048 }
89b667f8
JB		 6049
6050 for_each_encoder_on_crtc(dev, crtc, encoder)
6051 if (encoder->pre_enable)
6052 encoder->pre_enable(encoder);
6053
2dd24552
JB		 6054 i9xx_pfit_enable(intel_crtc);
6055
63cbb074
VS		 6056 intel_crtc_load_lut(crtc);
6057
e1fdc473 6058 intel_enable_pipe(intel_crtc);
be6a6f8e 6059
4b3a9526
VS		 6060 assert_vblank_disabled(crtc);
6061 drm_crtc_vblank_on(crtc);
6062
f9b61ff6
DV		 6063 for_each_encoder_on_crtc(dev, crtc, encoder)
6064 encoder->enable(encoder);
89b667f8
JB		 6065}
6066
f13c2ef3
DV		 6067static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6068{
6069 struct drm_device *dev = crtc->base.dev;
6070 struct drm_i915_private *dev_priv = dev->dev_private;
6071
6e3c9717
ACO		 6072 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6073 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
f13c2ef3
DV		 6074}
6075
0b8765c6 6076static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 6077{
6078 struct drm_device *dev = crtc->dev;
a72e4c9f 6079 struct drm_i915_private *dev_priv = to_i915(dev);
79e53945 6080 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 6081 struct intel_encoder *encoder;
79e53945 6082 int pipe = intel_crtc->pipe;
79e53945 6083
53d9f4e9 6084 if (WARN_ON(intel_crtc->active))
f7abfe8b
CW		 6085 return;
6086
f13c2ef3
DV		 6087 i9xx_set_pll_dividers(intel_crtc);
6088
6e3c9717 6089 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 6090 intel_dp_set_m_n(intel_crtc, M1_N1);
5b18e57c
DV		 6091
6092 intel_set_pipe_timings(intel_crtc);
6093
5b18e57c
DV		 6094 i9xx_set_pipeconf(intel_crtc);
6095
f7abfe8b 6096 intel_crtc->active = true;
6b383a7f 6097
4a3436e8 6098 if (!IS_GEN2(dev))
a72e4c9f 6099 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 6100
9d6d9f19
MK		 6101 for_each_encoder_on_crtc(dev, crtc, encoder)
6102 if (encoder->pre_enable)
6103 encoder->pre_enable(encoder);
6104
f6736a1a
DV		 6105 i9xx_enable_pll(intel_crtc);
6106
2dd24552
JB		 6107 i9xx_pfit_enable(intel_crtc);
6108
63cbb074
VS		 6109 intel_crtc_load_lut(crtc);
6110
f37fcc2a 6111 intel_update_watermarks(crtc);
e1fdc473 6112 intel_enable_pipe(intel_crtc);
be6a6f8e 6113
4b3a9526
VS		 6114 assert_vblank_disabled(crtc);
6115 drm_crtc_vblank_on(crtc);
6116
f9b61ff6
DV		 6117 for_each_encoder_on_crtc(dev, crtc, encoder)
6118 encoder->enable(encoder);
0b8765c6 6119}
79e53945 6120
87476d63
DV		 6121static void i9xx_pfit_disable(struct intel_crtc *crtc)
6122{
6123 struct drm_device *dev = crtc->base.dev;
6124 struct drm_i915_private *dev_priv = dev->dev_private;
87476d63 6125
6e3c9717 6126 if (!crtc->config->gmch_pfit.control)
328d8e82 6127 return;
87476d63 6128
328d8e82 6129 assert_pipe_disabled(dev_priv, crtc->pipe);
87476d63 6130
328d8e82
DV		 6131 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6132 I915_READ(PFIT_CONTROL));
6133 I915_WRITE(PFIT_CONTROL, 0);
87476d63
DV		 6134}
6135
0b8765c6
JB		 6136static void i9xx_crtc_disable(struct drm_crtc *crtc)
6137{
6138 struct drm_device *dev = crtc->dev;
6139 struct drm_i915_private *dev_priv = dev->dev_private;
6140 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 6141 struct intel_encoder *encoder;
0b8765c6 6142 int pipe = intel_crtc->pipe;
ef9c3aee 6143
6304cd91
VS		 6144 /*
6145 * On gen2 planes are double buffered but the pipe isn't, so we must
6146 * wait for planes to fully turn off before disabling the pipe.
564ed191
ID		 6147 * We also need to wait on all gmch platforms because of the
6148 * self-refresh mode constraint explained above.
6304cd91 6149 */
564ed191 6150 intel_wait_for_vblank(dev, pipe);
6304cd91 6151
4b3a9526
VS		 6152 for_each_encoder_on_crtc(dev, crtc, encoder)
6153 encoder->disable(encoder);
6154
f9b61ff6
DV		 6155 drm_crtc_vblank_off(crtc);
6156 assert_vblank_disabled(crtc);
6157
575f7ab7 6158 intel_disable_pipe(intel_crtc);
24a1f16d 6159
87476d63 6160 i9xx_pfit_disable(intel_crtc);
24a1f16d 6161
89b667f8
JB		 6162 for_each_encoder_on_crtc(dev, crtc, encoder)
6163 if (encoder->post_disable)
6164 encoder->post_disable(encoder);
6165
409ee761 6166 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
076ed3b2
CML		 6167 if (IS_CHERRYVIEW(dev))
6168 chv_disable_pll(dev_priv, pipe);
6169 else if (IS_VALLEYVIEW(dev))
6170 vlv_disable_pll(dev_priv, pipe);
6171 else
1c4e0274 6172 i9xx_disable_pll(intel_crtc);
076ed3b2 6173 }
0b8765c6 6174
d6db995f
VS		 6175 for_each_encoder_on_crtc(dev, crtc, encoder)
6176 if (encoder->post_pll_disable)
6177 encoder->post_pll_disable(encoder);
6178
4a3436e8 6179 if (!IS_GEN2(dev))
a72e4c9f 6180 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
e4ca0612
PJ		 6181
6182 intel_crtc->active = false;
6183 intel_update_watermarks(crtc);
0b8765c6
JB		 6184}
6185
b17d48e2
ML		 6186static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6187{
6188 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6189 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6190 enum intel_display_power_domain domain;
6191 unsigned long domains;
6192
6193 if (!intel_crtc->active)
6194 return;
6195
a539205a
ML		 6196 if (to_intel_plane_state(crtc->primary->state)->visible) {
6197 intel_crtc_wait_for_pending_flips(crtc);
6198 intel_pre_disable_primary(crtc);
6199 }
6200
d032ffa0 6201 intel_crtc_disable_planes(crtc, crtc->state->plane_mask);
b17d48e2 6202 dev_priv->display.crtc_disable(crtc);
1f7457b1 6203 intel_disable_shared_dpll(intel_crtc);
b17d48e2
ML		 6204
6205 domains = intel_crtc->enabled_power_domains;
6206 for_each_power_domain(domain, domains)
6207 intel_display_power_put(dev_priv, domain);
6208 intel_crtc->enabled_power_domains = 0;
6209}
6210
6b72d486
ML		 6211/*
6212 * turn all crtc's off, but do not adjust state
6213 * This has to be paired with a call to intel_modeset_setup_hw_state.
6214 */
70e0bd74 6215int intel_display_suspend(struct drm_device *dev)
ee7b9f93 6216{
70e0bd74
ML		 6217 struct drm_mode_config *config = &dev->mode_config;
6218 struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx;
6219 struct drm_atomic_state *state;
6b72d486 6220 struct drm_crtc *crtc;
70e0bd74
ML		 6221 unsigned crtc_mask = 0;
6222 int ret = 0;
6223
6224 if (WARN_ON(!ctx))
6225 return 0;
6226
6227 lockdep_assert_held(&ctx->ww_ctx);
6228 state = drm_atomic_state_alloc(dev);
6229 if (WARN_ON(!state))
6230 return -ENOMEM;
6231
6232 state->acquire_ctx = ctx;
6233 state->allow_modeset = true;
6234
6235 for_each_crtc(dev, crtc) {
6236 struct drm_crtc_state *crtc_state =
6237 drm_atomic_get_crtc_state(state, crtc);
6b72d486 6238
70e0bd74
ML		 6239 ret = PTR_ERR_OR_ZERO(crtc_state);
6240 if (ret)
6241 goto free;
6242
6243 if (!crtc_state->active)
6244 continue;
6245
6246 crtc_state->active = false;
6247 crtc_mask |= 1 << drm_crtc_index(crtc);
6248 }
6249
6250 if (crtc_mask) {
74c090b1 6251 ret = drm_atomic_commit(state);
70e0bd74
ML		 6252
6253 if (!ret) {
6254 for_each_crtc(dev, crtc)
6255 if (crtc_mask & (1 << drm_crtc_index(crtc)))
6256 crtc->state->active = true;
6257
6258 return ret;
6259 }
6260 }
6261
6262free:
6263 if (ret)
6264 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6265 drm_atomic_state_free(state);
6266 return ret;
ee7b9f93
JB		 6267}
6268
ea5b213a 6269void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 6270{
4ef69c7a 6271 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 6272
ea5b213a
CW		 6273 drm_encoder_cleanup(encoder);
6274 kfree(intel_encoder);
7e7d76c3
JB		 6275}
6276
0a91ca29
DV		 6277/* Cross check the actual hw state with our own modeset state tracking (and it's
6278 * internal consistency). */
b980514c 6279static void intel_connector_check_state(struct intel_connector *connector)
79e53945 6280{
35dd3c64
ML		 6281 struct drm_crtc *crtc = connector->base.state->crtc;
6282
6283 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6284 connector->base.base.id,
6285 connector->base.name);
6286
0a91ca29 6287 if (connector->get_hw_state(connector)) {
35dd3c64
ML		 6288 struct drm_encoder *encoder = &connector->encoder->base;
6289 struct drm_connector_state *conn_state = connector->base.state;
0a91ca29 6290
35dd3c64
ML		 6291 I915_STATE_WARN(!crtc,
6292 "connector enabled without attached crtc\n");
0a91ca29 6293
35dd3c64
ML		 6294 if (!crtc)
6295 return;
6296
6297 I915_STATE_WARN(!crtc->state->active,
6298 "connector is active, but attached crtc isn't\n");
6299
6300 if (!encoder)
6301 return;
6302
6303 I915_STATE_WARN(conn_state->best_encoder != encoder,
6304 "atomic encoder doesn't match attached encoder\n");
6305
6306 I915_STATE_WARN(conn_state->crtc != encoder->crtc,
6307 "attached encoder crtc differs from connector crtc\n");
6308 } else {
4d688a2a
ML		 6309 I915_STATE_WARN(crtc && crtc->state->active,
6310 "attached crtc is active, but connector isn't\n");
35dd3c64
ML		 6311 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
6312 "best encoder set without crtc!\n");
0a91ca29 6313 }
79e53945
JB		 6314}
6315
08d9bc92
ACO		 6316int intel_connector_init(struct intel_connector *connector)
6317{
6318 struct drm_connector_state *connector_state;
6319
6320 connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6321 if (!connector_state)
6322 return -ENOMEM;
6323
6324 connector->base.state = connector_state;
6325 return 0;
6326}
6327
6328struct intel_connector *intel_connector_alloc(void)
6329{
6330 struct intel_connector *connector;
6331
6332 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6333 if (!connector)
6334 return NULL;
6335
6336 if (intel_connector_init(connector) < 0) {
6337 kfree(connector);
6338 return NULL;
6339 }
6340
6341 return connector;
6342}
6343
f0947c37
DV		 6344/* Simple connector->get_hw_state implementation for encoders that support only
6345 * one connector and no cloning and hence the encoder state determines the state
6346 * of the connector. */
6347bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 6348{
24929352 6349 enum pipe pipe = 0;
f0947c37 6350 struct intel_encoder *encoder = connector->encoder;
ea5b213a 6351
f0947c37 6352 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 6353}
6354
6d293983 6355static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
d272ddfa 6356{
6d293983
ACO		 6357 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6358 return crtc_state->fdi_lanes;
d272ddfa
VS		 6359
6360 return 0;
6361}
6362
6d293983 6363static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5cec258b 6364 struct intel_crtc_state *pipe_config)
1857e1da 6365{
6d293983
ACO		 6366 struct drm_atomic_state *state = pipe_config->base.state;
6367 struct intel_crtc *other_crtc;
6368 struct intel_crtc_state *other_crtc_state;
6369
1857e1da
DV		 6370 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6371 pipe_name(pipe), pipe_config->fdi_lanes);
6372 if (pipe_config->fdi_lanes > 4) {
6373 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6374 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6375 return -EINVAL;
1857e1da
DV		 6376 }
6377
bafb6553 6378 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
1857e1da
DV		 6379 if (pipe_config->fdi_lanes > 2) {
6380 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6381 pipe_config->fdi_lanes);
6d293983 6382 return -EINVAL;
1857e1da 6383 } else {
6d293983 6384 return 0;
1857e1da
DV		 6385 }
6386 }
6387
6388 if (INTEL_INFO(dev)->num_pipes == 2)
6d293983 6389 return 0;
1857e1da
DV		 6390
6391 /* Ivybridge 3 pipe is really complicated */
6392 switch (pipe) {
6393 case PIPE_A:
6d293983 6394 return 0;
1857e1da 6395 case PIPE_B:
6d293983
ACO		 6396 if (pipe_config->fdi_lanes <= 2)
6397 return 0;
6398
6399 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6400 other_crtc_state =
6401 intel_atomic_get_crtc_state(state, other_crtc);
6402 if (IS_ERR(other_crtc_state))
6403 return PTR_ERR(other_crtc_state);
6404
6405 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
1857e1da
DV		 6406 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6407 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6408 return -EINVAL;
1857e1da 6409 }
6d293983 6410 return 0;
1857e1da 6411 case PIPE_C:
251cc67c
VS		 6412 if (pipe_config->fdi_lanes > 2) {
6413 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6414 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6415 return -EINVAL;
251cc67c 6416 }
6d293983
ACO		 6417
6418 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6419 other_crtc_state =
6420 intel_atomic_get_crtc_state(state, other_crtc);
6421 if (IS_ERR(other_crtc_state))
6422 return PTR_ERR(other_crtc_state);
6423
6424 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
1857e1da 6425 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6d293983 6426 return -EINVAL;
1857e1da 6427 }
6d293983 6428 return 0;
1857e1da
DV		 6429 default:
6430 BUG();
6431 }
6432}
6433
e29c22c0
DV		 6434#define RETRY 1
6435static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5cec258b 6436 struct intel_crtc_state *pipe_config)
877d48d5 6437{
1857e1da 6438 struct drm_device *dev = intel_crtc->base.dev;
2d112de7 6439 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6d293983
ACO		 6440 int lane, link_bw, fdi_dotclock, ret;
6441 bool needs_recompute = false;
877d48d5 6442
e29c22c0 6443retry:
877d48d5
DV		 6444 /* FDI is a binary signal running at ~2.7GHz, encoding
6445 * each output octet as 10 bits. The actual frequency
6446 * is stored as a divider into a 100MHz clock, and the
6447 * mode pixel clock is stored in units of 1KHz.
6448 * Hence the bw of each lane in terms of the mode signal
6449 * is:
6450 */
6451 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6452
241bfc38 6453 fdi_dotclock = adjusted_mode->crtc_clock;
877d48d5 6454
2bd89a07 6455 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
877d48d5
DV		 6456 pipe_config->pipe_bpp);
6457
6458 pipe_config->fdi_lanes = lane;
6459
2bd89a07 6460 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
877d48d5 6461 link_bw, &pipe_config->fdi_m_n);
1857e1da 6462
6d293983
ACO		 6463 ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6464 intel_crtc->pipe, pipe_config);
6465 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
e29c22c0
DV		 6466 pipe_config->pipe_bpp -= 2*3;
6467 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6468 pipe_config->pipe_bpp);
6469 needs_recompute = true;
6470 pipe_config->bw_constrained = true;
6471
6472 goto retry;
6473 }
6474
6475 if (needs_recompute)
6476 return RETRY;
6477
6d293983 6478 return ret;
877d48d5
DV		 6479}
6480
8cfb3407
VS		 6481static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6482 struct intel_crtc_state *pipe_config)
6483{
6484 if (pipe_config->pipe_bpp > 24)
6485 return false;
6486
6487 /* HSW can handle pixel rate up to cdclk? */
6488 if (IS_HASWELL(dev_priv->dev))
6489 return true;
6490
6491 /*
b432e5cf
VS		 6492 * We compare against max which means we must take
6493 * the increased cdclk requirement into account when
6494 * calculating the new cdclk.
6495 *
6496 * Should measure whether using a lower cdclk w/o IPS
8cfb3407
VS		 6497 */
6498 return ilk_pipe_pixel_rate(pipe_config) <=
6499 dev_priv->max_cdclk_freq * 95 / 100;
6500}
6501
42db64ef 6502static void hsw_compute_ips_config(struct intel_crtc *crtc,
5cec258b 6503 struct intel_crtc_state *pipe_config)
42db64ef 6504{
8cfb3407
VS		 6505 struct drm_device *dev = crtc->base.dev;
6506 struct drm_i915_private *dev_priv = dev->dev_private;
6507
d330a953 6508 pipe_config->ips_enabled = i915.enable_ips &&
8cfb3407
VS		 6509 hsw_crtc_supports_ips(crtc) &&
6510 pipe_config_supports_ips(dev_priv, pipe_config);
42db64ef
PZ		 6511}
6512
a43f6e0f 6513static int intel_crtc_compute_config(struct intel_crtc *crtc,
5cec258b 6514 struct intel_crtc_state *pipe_config)
79e53945 6515{
a43f6e0f 6516 struct drm_device *dev = crtc->base.dev;
8bd31e67 6517 struct drm_i915_private *dev_priv = dev->dev_private;
2d112de7 6518 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
89749350 6519
ad3a4479 6520 /* FIXME should check pixel clock limits on all platforms */
cf532bb2 6521 if (INTEL_INFO(dev)->gen < 4) {
44913155 6522 int clock_limit = dev_priv->max_cdclk_freq;
cf532bb2
VS		 6523
6524 /*
6525 * Enable pixel doubling when the dot clock
6526 * is > 90% of the (display) core speed.
6527 *
b397c96b
VS		 6528 * GDG double wide on either pipe,
6529 * otherwise pipe A only.
cf532bb2 6530 */
b397c96b 6531 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
241bfc38 6532 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
ad3a4479 6533 clock_limit *= 2;
cf532bb2 6534 pipe_config->double_wide = true;
ad3a4479
VS		 6535 }
6536
241bfc38 6537 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
e29c22c0 6538 return -EINVAL;
2c07245f 6539 }
89749350 6540
1d1d0e27
VS		 6541 /*
6542 * Pipe horizontal size must be even in:
6543 * - DVO ganged mode
6544 * - LVDS dual channel mode
6545 * - Double wide pipe
6546 */
a93e255f 6547 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
1d1d0e27
VS		 6548 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6549 pipe_config->pipe_src_w &= ~1;
6550
8693a824
DL		 6551 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6552 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
44f46b42
CW		 6553 */
6554 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6555 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
e29c22c0 6556 return -EINVAL;
44f46b42 6557
f5adf94e 6558 if (HAS_IPS(dev))
a43f6e0f
DV		 6559 hsw_compute_ips_config(crtc, pipe_config);
6560
877d48d5 6561 if (pipe_config->has_pch_encoder)
a43f6e0f 6562 return ironlake_fdi_compute_config(crtc, pipe_config);
877d48d5 6563
cf5a15be 6564 return 0;
79e53945
JB		 6565}
6566
1652d19e
VS		 6567static int skylake_get_display_clock_speed(struct drm_device *dev)
6568{
6569 struct drm_i915_private *dev_priv = to_i915(dev);
6570 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6571 uint32_t cdctl = I915_READ(CDCLK_CTL);
6572 uint32_t linkrate;
6573
414355a7 6574 if (!(lcpll1 & LCPLL_PLL_ENABLE))
1652d19e 6575 return 24000; /* 24MHz is the cd freq with NSSC ref */
1652d19e
VS		 6576
6577 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6578 return 540000;
6579
6580 linkrate = (I915_READ(DPLL_CTRL1) &
71cd8423 6581 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
1652d19e 6582
71cd8423
DL		 6583 if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6584 linkrate == DPLL_CTRL1_LINK_RATE_1080) {
1652d19e
VS		 6585 /* vco 8640 */
6586 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6587 case CDCLK_FREQ_450_432:
6588 return 432000;
6589 case CDCLK_FREQ_337_308:
6590 return 308570;
6591 case CDCLK_FREQ_675_617:
6592 return 617140;
6593 default:
6594 WARN(1, "Unknown cd freq selection\n");
6595 }
6596 } else {
6597 /* vco 8100 */
6598 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6599 case CDCLK_FREQ_450_432:
6600 return 450000;
6601 case CDCLK_FREQ_337_308:
6602 return 337500;
6603 case CDCLK_FREQ_675_617:
6604 return 675000;
6605 default:
6606 WARN(1, "Unknown cd freq selection\n");
6607 }
6608 }
6609
6610 /* error case, do as if DPLL0 isn't enabled */
6611 return 24000;
6612}
6613
acd3f3d3
BP		 6614static int broxton_get_display_clock_speed(struct drm_device *dev)
6615{
6616 struct drm_i915_private *dev_priv = to_i915(dev);
6617 uint32_t cdctl = I915_READ(CDCLK_CTL);
6618 uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
6619 uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE);
6620 int cdclk;
6621
6622 if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE))
6623 return 19200;
6624
6625 cdclk = 19200 * pll_ratio / 2;
6626
6627 switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
6628 case BXT_CDCLK_CD2X_DIV_SEL_1:
6629 return cdclk; /* 576MHz or 624MHz */
6630 case BXT_CDCLK_CD2X_DIV_SEL_1_5:
6631 return cdclk * 2 / 3; /* 384MHz */
6632 case BXT_CDCLK_CD2X_DIV_SEL_2:
6633 return cdclk / 2; /* 288MHz */
6634 case BXT_CDCLK_CD2X_DIV_SEL_4:
6635 return cdclk / 4; /* 144MHz */
6636 }
6637
6638 /* error case, do as if DE PLL isn't enabled */
6639 return 19200;
6640}
6641
1652d19e
VS		 6642static int broadwell_get_display_clock_speed(struct drm_device *dev)
6643{
6644 struct drm_i915_private *dev_priv = dev->dev_private;
6645 uint32_t lcpll = I915_READ(LCPLL_CTL);
6646 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6647
6648 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6649 return 800000;
6650 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6651 return 450000;
6652 else if (freq == LCPLL_CLK_FREQ_450)
6653 return 450000;
6654 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6655 return 540000;
6656 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6657 return 337500;
6658 else
6659 return 675000;
6660}
6661
6662static int haswell_get_display_clock_speed(struct drm_device *dev)
6663{
6664 struct drm_i915_private *dev_priv = dev->dev_private;
6665 uint32_t lcpll = I915_READ(LCPLL_CTL);
6666 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6667
6668 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6669 return 800000;
6670 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6671 return 450000;
6672 else if (freq == LCPLL_CLK_FREQ_450)
6673 return 450000;
6674 else if (IS_HSW_ULT(dev))
6675 return 337500;
6676 else
6677 return 540000;
79e53945
JB		 6678}
6679
25eb05fc
JB		 6680static int valleyview_get_display_clock_speed(struct drm_device *dev)
6681{
d197b7d3 6682 struct drm_i915_private *dev_priv = dev->dev_private;
d197b7d3
VS		 6683 u32 val;
6684 int divider;
6685
6bcda4f0
VS		 6686 if (dev_priv->hpll_freq == 0)
6687 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
6688
a580516d 6689 mutex_lock(&dev_priv->sb_lock);
d197b7d3 6690 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
a580516d 6691 mutex_unlock(&dev_priv->sb_lock);
d197b7d3
VS		 6692
6693 divider = val & DISPLAY_FREQUENCY_VALUES;
6694
7d007f40
VS		 6695 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
6696 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
6697 "cdclk change in progress\n");
6698
6bcda4f0 6699 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
25eb05fc
JB		 6700}
6701
b37a6434
VS		 6702static int ilk_get_display_clock_speed(struct drm_device *dev)
6703{
6704 return 450000;
6705}
6706
e70236a8
JB		 6707static int i945_get_display_clock_speed(struct drm_device *dev)
6708{
6709 return 400000;
6710}
79e53945 6711
e70236a8 6712static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 6713{
e907f170 6714 return 333333;
e70236a8 6715}
79e53945 6716
e70236a8
JB		 6717static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6718{
6719 return 200000;
6720}
79e53945 6721
257a7ffc
DV		 6722static int pnv_get_display_clock_speed(struct drm_device *dev)
6723{
6724 u16 gcfgc = 0;
6725
6726 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6727
6728 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6729 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
e907f170 6730 return 266667;
257a7ffc 6731 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
e907f170 6732 return 333333;
257a7ffc 6733 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
e907f170 6734 return 444444;
257a7ffc
DV		 6735 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6736 return 200000;
6737 default:
6738 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6739 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
e907f170 6740 return 133333;
257a7ffc 6741 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
e907f170 6742 return 166667;
257a7ffc
DV		 6743 }
6744}
6745
e70236a8
JB		 6746static int i915gm_get_display_clock_speed(struct drm_device *dev)
6747{
6748 u16 gcfgc = 0;
79e53945 6749
e70236a8
JB		 6750 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6751
6752 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
e907f170 6753 return 133333;
e70236a8
JB		 6754 else {
6755 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6756 case GC_DISPLAY_CLOCK_333_MHZ:
e907f170 6757 return 333333;
e70236a8
JB		 6758 default:
6759 case GC_DISPLAY_CLOCK_190_200_MHZ:
6760 return 190000;
79e53945 6761 }
e70236a8
JB		 6762 }
6763}
6764
6765static int i865_get_display_clock_speed(struct drm_device *dev)
6766{
e907f170 6767 return 266667;
e70236a8
JB		 6768}
6769
1b1d2716 6770static int i85x_get_display_clock_speed(struct drm_device *dev)
e70236a8
JB		 6771{
6772 u16 hpllcc = 0;
1b1d2716 6773
65cd2b3f
VS		 6774 /*
6775 * 852GM/852GMV only supports 133 MHz and the HPLLCC
6776 * encoding is different :(
6777 * FIXME is this the right way to detect 852GM/852GMV?
6778 */
6779 if (dev->pdev->revision == 0x1)
6780 return 133333;
6781
1b1d2716
VS		 6782 pci_bus_read_config_word(dev->pdev->bus,
6783 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6784
e70236a8
JB		 6785 /* Assume that the hardware is in the high speed state. This
6786 * should be the default.
6787 */
6788 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6789 case GC_CLOCK_133_200:
1b1d2716 6790 case GC_CLOCK_133_200_2:
e70236a8
JB		 6791 case GC_CLOCK_100_200:
6792 return 200000;
6793 case GC_CLOCK_166_250:
6794 return 250000;
6795 case GC_CLOCK_100_133:
e907f170 6796 return 133333;
1b1d2716
VS		 6797 case GC_CLOCK_133_266:
6798 case GC_CLOCK_133_266_2:
6799 case GC_CLOCK_166_266:
6800 return 266667;
e70236a8 6801 }
79e53945 6802
e70236a8
JB		 6803 /* Shouldn't happen */
6804 return 0;
6805}
79e53945 6806
e70236a8
JB		 6807static int i830_get_display_clock_speed(struct drm_device *dev)
6808{
e907f170 6809 return 133333;
79e53945
JB		 6810}
6811
34edce2f
VS		 6812static unsigned int intel_hpll_vco(struct drm_device *dev)
6813{
6814 struct drm_i915_private *dev_priv = dev->dev_private;
6815 static const unsigned int blb_vco[8] = {
6816 [0] = 3200000,
6817 [1] = 4000000,
6818 [2] = 5333333,
6819 [3] = 4800000,
6820 [4] = 6400000,
6821 };
6822 static const unsigned int pnv_vco[8] = {
6823 [0] = 3200000,
6824 [1] = 4000000,
6825 [2] = 5333333,
6826 [3] = 4800000,
6827 [4] = 2666667,
6828 };
6829 static const unsigned int cl_vco[8] = {
6830 [0] = 3200000,
6831 [1] = 4000000,
6832 [2] = 5333333,
6833 [3] = 6400000,
6834 [4] = 3333333,
6835 [5] = 3566667,
6836 [6] = 4266667,
6837 };
6838 static const unsigned int elk_vco[8] = {
6839 [0] = 3200000,
6840 [1] = 4000000,
6841 [2] = 5333333,
6842 [3] = 4800000,
6843 };
6844 static const unsigned int ctg_vco[8] = {
6845 [0] = 3200000,
6846 [1] = 4000000,
6847 [2] = 5333333,
6848 [3] = 6400000,
6849 [4] = 2666667,
6850 [5] = 4266667,
6851 };
6852 const unsigned int *vco_table;
6853 unsigned int vco;
6854 uint8_t tmp = 0;
6855
6856 /* FIXME other chipsets? */
6857 if (IS_GM45(dev))
6858 vco_table = ctg_vco;
6859 else if (IS_G4X(dev))
6860 vco_table = elk_vco;
6861 else if (IS_CRESTLINE(dev))
6862 vco_table = cl_vco;
6863 else if (IS_PINEVIEW(dev))
6864 vco_table = pnv_vco;
6865 else if (IS_G33(dev))
6866 vco_table = blb_vco;
6867 else
6868 return 0;
6869
6870 tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
6871
6872 vco = vco_table[tmp & 0x7];
6873 if (vco == 0)
6874 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
6875 else
6876 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
6877
6878 return vco;
6879}
6880
6881static int gm45_get_display_clock_speed(struct drm_device *dev)
6882{
6883 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6884 uint16_t tmp = 0;
6885
6886 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6887
6888 cdclk_sel = (tmp >> 12) & 0x1;
6889
6890 switch (vco) {
6891 case 2666667:
6892 case 4000000:
6893 case 5333333:
6894 return cdclk_sel ? 333333 : 222222;
6895 case 3200000:
6896 return cdclk_sel ? 320000 : 228571;
6897 default:
6898 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
6899 return 222222;
6900 }
6901}
6902
6903static int i965gm_get_display_clock_speed(struct drm_device *dev)
6904{
6905 static const uint8_t div_3200[] = { 16, 10, 8 };
6906 static const uint8_t div_4000[] = { 20, 12, 10 };
6907 static const uint8_t div_5333[] = { 24, 16, 14 };
6908 const uint8_t *div_table;
6909 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6910 uint16_t tmp = 0;
6911
6912 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6913
6914 cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
6915
6916 if (cdclk_sel >= ARRAY_SIZE(div_3200))
6917 goto fail;
6918
6919 switch (vco) {
6920 case 3200000:
6921 div_table = div_3200;
6922 break;
6923 case 4000000:
6924 div_table = div_4000;
6925 break;
6926 case 5333333:
6927 div_table = div_5333;
6928 break;
6929 default:
6930 goto fail;
6931 }
6932
6933 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6934
caf4e252 6935fail:
34edce2f
VS		 6936 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
6937 return 200000;
6938}
6939
6940static int g33_get_display_clock_speed(struct drm_device *dev)
6941{
6942 static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 };
6943 static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 };
6944 static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
6945 static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
6946 const uint8_t *div_table;
6947 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6948 uint16_t tmp = 0;
6949
6950 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6951
6952 cdclk_sel = (tmp >> 4) & 0x7;
6953
6954 if (cdclk_sel >= ARRAY_SIZE(div_3200))
6955 goto fail;
6956
6957 switch (vco) {
6958 case 3200000:
6959 div_table = div_3200;
6960 break;
6961 case 4000000:
6962 div_table = div_4000;
6963 break;
6964 case 4800000:
6965 div_table = div_4800;
6966 break;
6967 case 5333333:
6968 div_table = div_5333;
6969 break;
6970 default:
6971 goto fail;
6972 }
6973
6974 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6975
caf4e252 6976fail:
34edce2f
VS		 6977 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
6978 return 190476;
6979}
6980
2c07245f 6981static void
a65851af 6982intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
2c07245f 6983{
a65851af
VS		 6984 while (*num > DATA_LINK_M_N_MASK ||
6985 *den > DATA_LINK_M_N_MASK) {
2c07245f
ZW		 6986 *num >>= 1;
6987 *den >>= 1;
6988 }
6989}
6990
a65851af
VS		 6991static void compute_m_n(unsigned int m, unsigned int n,
6992 uint32_t *ret_m, uint32_t *ret_n)
6993{
6994 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
6995 *ret_m = div_u64((uint64_t) m * *ret_n, n);
6996 intel_reduce_m_n_ratio(ret_m, ret_n);
6997}
6998
e69d0bc1
DV		 6999void
7000intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7001 int pixel_clock, int link_clock,
7002 struct intel_link_m_n *m_n)
2c07245f 7003{
e69d0bc1 7004 m_n->tu = 64;
a65851af
VS		 7005
7006 compute_m_n(bits_per_pixel * pixel_clock,
7007 link_clock * nlanes * 8,
7008 &m_n->gmch_m, &m_n->gmch_n);
7009
7010 compute_m_n(pixel_clock, link_clock,
7011 &m_n->link_m, &m_n->link_n);
2c07245f
ZW		 7012}
7013
a7615030
CW		 7014static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7015{
d330a953
JN		 7016 if (i915.panel_use_ssc >= 0)
7017 return i915.panel_use_ssc != 0;
41aa3448 7018 return dev_priv->vbt.lvds_use_ssc
435793df 7019 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 7020}
7021
a93e255f
ACO		 7022static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
7023 int num_connectors)
c65d77d8 7024{
a93e255f 7025 struct drm_device *dev = crtc_state->base.crtc->dev;
c65d77d8
JB		 7026 struct drm_i915_private *dev_priv = dev->dev_private;
7027 int refclk;
7028
a93e255f
ACO		 7029 WARN_ON(!crtc_state->base.state);
7030
5ab7b0b7 7031 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
9a0ea498 7032 refclk = 100000;
a93e255f 7033 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
c65d77d8 7034 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
e91e941b
VS		 7035 refclk = dev_priv->vbt.lvds_ssc_freq;
7036 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
c65d77d8
JB		 7037 } else if (!IS_GEN2(dev)) {
7038 refclk = 96000;
7039 } else {
7040 refclk = 48000;
7041 }
7042
7043 return refclk;
7044}
7045
7429e9d4 7046static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
c65d77d8 7047{
7df00d7a 7048 return (1 << dpll->n) << 16 | dpll->m2;
7429e9d4 7049}
f47709a9 7050
7429e9d4
DV		 7051static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7052{
7053 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
c65d77d8
JB		 7054}
7055
f47709a9 7056static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
190f68c5 7057 struct intel_crtc_state *crtc_state,
a7516a05
JB		 7058 intel_clock_t *reduced_clock)
7059{
f47709a9 7060 struct drm_device *dev = crtc->base.dev;
a7516a05
JB		 7061 u32 fp, fp2 = 0;
7062
7063 if (IS_PINEVIEW(dev)) {
190f68c5 7064 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
a7516a05 7065 if (reduced_clock)
7429e9d4 7066 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 7067 } else {
190f68c5 7068 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
a7516a05 7069 if (reduced_clock)
7429e9d4 7070 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB		 7071 }
7072
190f68c5 7073 crtc_state->dpll_hw_state.fp0 = fp;
a7516a05 7074
f47709a9 7075 crtc->lowfreq_avail = false;
a93e255f 7076 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
ab585dea 7077 reduced_clock) {
190f68c5 7078 crtc_state->dpll_hw_state.fp1 = fp2;
f47709a9 7079 crtc->lowfreq_avail = true;
a7516a05 7080 } else {
190f68c5 7081 crtc_state->dpll_hw_state.fp1 = fp;
a7516a05
JB		 7082 }
7083}
7084
5e69f97f
CML		 7085static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7086 pipe)
89b667f8
JB		 7087{
7088 u32 reg_val;
7089
7090 /*
7091 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7092 * and set it to a reasonable value instead.
7093 */
ab3c759a 7094 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
89b667f8
JB		 7095 reg_val &= 0xffffff00;
7096 reg_val |= 0x00000030;
ab3c759a 7097 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
89b667f8 7098
ab3c759a 7099 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
89b667f8
JB		 7100 reg_val &= 0x8cffffff;
7101 reg_val = 0x8c000000;
ab3c759a 7102 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
89b667f8 7103
ab3c759a 7104 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
89b667f8 7105 reg_val &= 0xffffff00;
ab3c759a 7106 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
89b667f8 7107
ab3c759a 7108 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
89b667f8
JB		 7109 reg_val &= 0x00ffffff;
7110 reg_val |= 0xb0000000;
ab3c759a 7111 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
89b667f8
JB		 7112}
7113
b551842d
DV		 7114static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7115 struct intel_link_m_n *m_n)
7116{
7117 struct drm_device *dev = crtc->base.dev;
7118 struct drm_i915_private *dev_priv = dev->dev_private;
7119 int pipe = crtc->pipe;
7120
e3b95f1e
DV		 7121 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7122 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7123 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7124 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
b551842d
DV		 7125}
7126
7127static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
f769cd24
VK		 7128 struct intel_link_m_n *m_n,
7129 struct intel_link_m_n *m2_n2)
b551842d
DV		 7130{
7131 struct drm_device *dev = crtc->base.dev;
7132 struct drm_i915_private *dev_priv = dev->dev_private;
7133 int pipe = crtc->pipe;
6e3c9717 7134 enum transcoder transcoder = crtc->config->cpu_transcoder;
b551842d
DV		 7135
7136 if (INTEL_INFO(dev)->gen >= 5) {
7137 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7138 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7139 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7140 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
f769cd24
VK		 7141 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7142 * for gen < 8) and if DRRS is supported (to make sure the
7143 * registers are not unnecessarily accessed).
7144 */
44395bfe 7145 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
6e3c9717 7146 crtc->config->has_drrs) {
f769cd24
VK		 7147 I915_WRITE(PIPE_DATA_M2(transcoder),
7148 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7149 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7150 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7151 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7152 }
b551842d 7153 } else {
e3b95f1e
DV		 7154 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7155 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7156 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7157 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
b551842d
DV		 7158 }
7159}
7160
fe3cd48d 7161void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
03afc4a2 7162{
fe3cd48d
R		 7163 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7164
7165 if (m_n == M1_N1) {
7166 dp_m_n = &crtc->config->dp_m_n;
7167 dp_m2_n2 = &crtc->config->dp_m2_n2;
7168 } else if (m_n == M2_N2) {
7169
7170 /*
7171 * M2_N2 registers are not supported. Hence m2_n2 divider value
7172 * needs to be programmed into M1_N1.
7173 */
7174 dp_m_n = &crtc->config->dp_m2_n2;
7175 } else {
7176 DRM_ERROR("Unsupported divider value\n");
7177 return;
7178 }
7179
6e3c9717
ACO		 7180 if (crtc->config->has_pch_encoder)
7181 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
03afc4a2 7182 else
fe3cd48d 7183 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
03afc4a2
DV		 7184}
7185
251ac862
DV		 7186static void vlv_compute_dpll(struct intel_crtc *crtc,
7187 struct intel_crtc_state *pipe_config)
bdd4b6a6
DV		 7188{
7189 u32 dpll, dpll_md;
7190
7191 /*
7192 * Enable DPIO clock input. We should never disable the reference
7193 * clock for pipe B, since VGA hotplug / manual detection depends
7194 * on it.
7195 */
60bfe44f
VS		 7196 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REF_CLK_ENABLE_VLV |
7197 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_REF_CLK_VLV;
bdd4b6a6
DV		 7198 /* We should never disable this, set it here for state tracking */
7199 if (crtc->pipe == PIPE_B)
7200 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7201 dpll |= DPLL_VCO_ENABLE;
d288f65f 7202 pipe_config->dpll_hw_state.dpll = dpll;
bdd4b6a6 7203
d288f65f 7204 dpll_md = (pipe_config->pixel_multiplier - 1)
bdd4b6a6 7205 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
d288f65f 7206 pipe_config->dpll_hw_state.dpll_md = dpll_md;
bdd4b6a6
DV		 7207}
7208
d288f65f 7209static void vlv_prepare_pll(struct intel_crtc *crtc,
5cec258b 7210 const struct intel_crtc_state *pipe_config)
a0c4da24 7211{
f47709a9 7212 struct drm_device *dev = crtc->base.dev;
a0c4da24 7213 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 7214 int pipe = crtc->pipe;
bdd4b6a6 7215 u32 mdiv;
a0c4da24 7216 u32 bestn, bestm1, bestm2, bestp1, bestp2;
bdd4b6a6 7217 u32 coreclk, reg_val;
a0c4da24 7218
a580516d 7219 mutex_lock(&dev_priv->sb_lock);
09153000 7220
d288f65f
VS		 7221 bestn = pipe_config->dpll.n;
7222 bestm1 = pipe_config->dpll.m1;
7223 bestm2 = pipe_config->dpll.m2;
7224 bestp1 = pipe_config->dpll.p1;
7225 bestp2 = pipe_config->dpll.p2;
a0c4da24 7226
89b667f8
JB		 7227 /* See eDP HDMI DPIO driver vbios notes doc */
7228
7229 /* PLL B needs special handling */
bdd4b6a6 7230 if (pipe == PIPE_B)
5e69f97f 7231 vlv_pllb_recal_opamp(dev_priv, pipe);
89b667f8
JB		 7232
7233 /* Set up Tx target for periodic Rcomp update */
ab3c759a 7234 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
89b667f8
JB		 7235
7236 /* Disable target IRef on PLL */
ab3c759a 7237 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
89b667f8 7238 reg_val &= 0x00ffffff;
ab3c759a 7239 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
89b667f8
JB		 7240
7241 /* Disable fast lock */
ab3c759a 7242 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
89b667f8
JB		 7243
7244 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 7245 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7246 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7247 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 7248 mdiv |= (1 << DPIO_K_SHIFT);
7df5080b
JB		 7249
7250 /*
7251 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7252 * but we don't support that).
7253 * Note: don't use the DAC post divider as it seems unstable.
7254 */
7255 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
ab3c759a 7256 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
a0c4da24 7257
a0c4da24 7258 mdiv |= DPIO_ENABLE_CALIBRATION;
ab3c759a 7259 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
a0c4da24 7260
89b667f8 7261 /* Set HBR and RBR LPF coefficients */
d288f65f 7262 if (pipe_config->port_clock == 162000 ||
409ee761
ACO		 7263 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7264 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
ab3c759a 7265 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
885b0120 7266 0x009f0003);
89b667f8 7267 else
ab3c759a 7268 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
89b667f8
JB		 7269 0x00d0000f);
7270
681a8504 7271 if (pipe_config->has_dp_encoder) {
89b667f8 7272 /* Use SSC source */
bdd4b6a6 7273 if (pipe == PIPE_A)
ab3c759a 7274 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7275 0x0df40000);
7276 else
ab3c759a 7277 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7278 0x0df70000);
7279 } else { /* HDMI or VGA */
7280 /* Use bend source */
bdd4b6a6 7281 if (pipe == PIPE_A)
ab3c759a 7282 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7283 0x0df70000);
7284 else
ab3c759a 7285 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7286 0x0df40000);
7287 }
a0c4da24 7288
ab3c759a 7289 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
89b667f8 7290 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
409ee761
ACO		 7291 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7292 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
89b667f8 7293 coreclk |= 0x01000000;
ab3c759a 7294 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
a0c4da24 7295
ab3c759a 7296 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
a580516d 7297 mutex_unlock(&dev_priv->sb_lock);
a0c4da24
JB		 7298}
7299
251ac862
DV		 7300static void chv_compute_dpll(struct intel_crtc *crtc,
7301 struct intel_crtc_state *pipe_config)
1ae0d137 7302{
60bfe44f
VS		 7303 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7304 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
1ae0d137
VS		 7305 DPLL_VCO_ENABLE;
7306 if (crtc->pipe != PIPE_A)
d288f65f 7307 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
1ae0d137 7308
d288f65f
VS		 7309 pipe_config->dpll_hw_state.dpll_md =
7310 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
1ae0d137
VS		 7311}
7312
d288f65f 7313static void chv_prepare_pll(struct intel_crtc *crtc,
5cec258b 7314 const struct intel_crtc_state *pipe_config)
9d556c99
CML		 7315{
7316 struct drm_device *dev = crtc->base.dev;
7317 struct drm_i915_private *dev_priv = dev->dev_private;
7318 int pipe = crtc->pipe;
7319 int dpll_reg = DPLL(crtc->pipe);
7320 enum dpio_channel port = vlv_pipe_to_channel(pipe);
9cbe40c1 7321 u32 loopfilter, tribuf_calcntr;
9d556c99 7322 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
a945ce7e 7323 u32 dpio_val;
9cbe40c1 7324 int vco;
9d556c99 7325
d288f65f
VS		 7326 bestn = pipe_config->dpll.n;
7327 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7328 bestm1 = pipe_config->dpll.m1;
7329 bestm2 = pipe_config->dpll.m2 >> 22;
7330 bestp1 = pipe_config->dpll.p1;
7331 bestp2 = pipe_config->dpll.p2;
9cbe40c1 7332 vco = pipe_config->dpll.vco;
a945ce7e 7333 dpio_val = 0;
9cbe40c1 7334 loopfilter = 0;
9d556c99
CML		 7335
7336 /*
7337 * Enable Refclk and SSC
7338 */
a11b0703 7339 I915_WRITE(dpll_reg,
d288f65f 7340 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
a11b0703 7341
a580516d 7342 mutex_lock(&dev_priv->sb_lock);
9d556c99 7343
9d556c99
CML		 7344 /* p1 and p2 divider */
7345 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7346 5 << DPIO_CHV_S1_DIV_SHIFT |
7347 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7348 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7349 1 << DPIO_CHV_K_DIV_SHIFT);
7350
7351 /* Feedback post-divider - m2 */
7352 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7353
7354 /* Feedback refclk divider - n and m1 */
7355 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7356 DPIO_CHV_M1_DIV_BY_2 |
7357 1 << DPIO_CHV_N_DIV_SHIFT);
7358
7359 /* M2 fraction division */
25a25dfc 7360 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
9d556c99
CML		 7361
7362 /* M2 fraction division enable */
a945ce7e
VP		 7363 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7364 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7365 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7366 if (bestm2_frac)
7367 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7368 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
9d556c99 7369
de3a0fde
VP		 7370 /* Program digital lock detect threshold */
7371 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7372 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7373 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7374 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7375 if (!bestm2_frac)
7376 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7377 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7378
9d556c99 7379 /* Loop filter */
9cbe40c1
VP		 7380 if (vco == 5400000) {
7381 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7382 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7383 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7384 tribuf_calcntr = 0x9;
7385 } else if (vco <= 6200000) {
7386 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7387 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7388 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7389 tribuf_calcntr = 0x9;
7390 } else if (vco <= 6480000) {
7391 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7392 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7393 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7394 tribuf_calcntr = 0x8;
7395 } else {
7396 /* Not supported. Apply the same limits as in the max case */
7397 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7398 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7399 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7400 tribuf_calcntr = 0;
7401 }
9d556c99
CML		 7402 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7403
968040b2 7404 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
9cbe40c1
VP		 7405 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7406 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7407 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7408
9d556c99
CML		 7409 /* AFC Recal */
7410 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7411 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7412 DPIO_AFC_RECAL);
7413
a580516d 7414 mutex_unlock(&dev_priv->sb_lock);
9d556c99
CML		 7415}
7416
d288f65f
VS		 7417/**
7418 * vlv_force_pll_on - forcibly enable just the PLL
7419 * @dev_priv: i915 private structure
7420 * @pipe: pipe PLL to enable
7421 * @dpll: PLL configuration
7422 *
7423 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7424 * in cases where we need the PLL enabled even when @pipe is not going to
7425 * be enabled.
7426 */
7427void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7428 const struct dpll *dpll)
7429{
7430 struct intel_crtc *crtc =
7431 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
5cec258b 7432 struct intel_crtc_state pipe_config = {
a93e255f 7433 .base.crtc = &crtc->base,
d288f65f
VS		 7434 .pixel_multiplier = 1,
7435 .dpll = *dpll,
7436 };
7437
7438 if (IS_CHERRYVIEW(dev)) {
251ac862 7439 chv_compute_dpll(crtc, &pipe_config);
d288f65f
VS		 7440 chv_prepare_pll(crtc, &pipe_config);
7441 chv_enable_pll(crtc, &pipe_config);
7442 } else {
251ac862 7443 vlv_compute_dpll(crtc, &pipe_config);
d288f65f
VS		 7444 vlv_prepare_pll(crtc, &pipe_config);
7445 vlv_enable_pll(crtc, &pipe_config);
7446 }
7447}
7448
7449/**
7450 * vlv_force_pll_off - forcibly disable just the PLL
7451 * @dev_priv: i915 private structure
7452 * @pipe: pipe PLL to disable
7453 *
7454 * Disable the PLL for @pipe. To be used in cases where we need
7455 * the PLL enabled even when @pipe is not going to be enabled.
7456 */
7457void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7458{
7459 if (IS_CHERRYVIEW(dev))
7460 chv_disable_pll(to_i915(dev), pipe);
7461 else
7462 vlv_disable_pll(to_i915(dev), pipe);
7463}
7464
251ac862
DV		 7465static void i9xx_compute_dpll(struct intel_crtc *crtc,
7466 struct intel_crtc_state *crtc_state,
7467 intel_clock_t *reduced_clock,
7468 int num_connectors)
eb1cbe48 7469{
f47709a9 7470 struct drm_device *dev = crtc->base.dev;
eb1cbe48 7471 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48
DV		 7472 u32 dpll;
7473 bool is_sdvo;
190f68c5 7474 struct dpll *clock = &crtc_state->dpll;
eb1cbe48 7475
190f68c5 7476 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
2a8f64ca 7477
a93e255f
ACO		 7478 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7479 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 7480
7481 dpll = DPLL_VGA_MODE_DIS;
7482
a93e255f 7483 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 7484 dpll |= DPLLB_MODE_LVDS;
7485 else
7486 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 7487
ef1b460d 7488 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
190f68c5 7489 dpll |= (crtc_state->pixel_multiplier - 1)
198a037f 7490 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 7491 }
198a037f
DV		 7492
7493 if (is_sdvo)
4a33e48d 7494 dpll |= DPLL_SDVO_HIGH_SPEED;
198a037f 7495
190f68c5 7496 if (crtc_state->has_dp_encoder)
4a33e48d 7497 dpll |= DPLL_SDVO_HIGH_SPEED;
eb1cbe48
DV		 7498
7499 /* compute bitmask from p1 value */
7500 if (IS_PINEVIEW(dev))
7501 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7502 else {
7503 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7504 if (IS_G4X(dev) && reduced_clock)
7505 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7506 }
7507 switch (clock->p2) {
7508 case 5:
7509 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7510 break;
7511 case 7:
7512 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7513 break;
7514 case 10:
7515 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7516 break;
7517 case 14:
7518 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7519 break;
7520 }
7521 if (INTEL_INFO(dev)->gen >= 4)
7522 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7523
190f68c5 7524 if (crtc_state->sdvo_tv_clock)
eb1cbe48 7525 dpll |= PLL_REF_INPUT_TVCLKINBC;
a93e255f 7526 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 7527 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7528 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7529 else
7530 dpll |= PLL_REF_INPUT_DREFCLK;
7531
7532 dpll |= DPLL_VCO_ENABLE;
190f68c5 7533 crtc_state->dpll_hw_state.dpll = dpll;
8bcc2795 7534
eb1cbe48 7535 if (INTEL_INFO(dev)->gen >= 4) {
190f68c5 7536 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
ef1b460d 7537 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
190f68c5 7538 crtc_state->dpll_hw_state.dpll_md = dpll_md;
eb1cbe48
DV		 7539 }
7540}
7541
251ac862
DV		 7542static void i8xx_compute_dpll(struct intel_crtc *crtc,
7543 struct intel_crtc_state *crtc_state,
7544 intel_clock_t *reduced_clock,
7545 int num_connectors)
eb1cbe48 7546{
f47709a9 7547 struct drm_device *dev = crtc->base.dev;
eb1cbe48 7548 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48 7549 u32 dpll;
190f68c5 7550 struct dpll *clock = &crtc_state->dpll;
eb1cbe48 7551
190f68c5 7552 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
2a8f64ca 7553
eb1cbe48
DV		 7554 dpll = DPLL_VGA_MODE_DIS;
7555
a93e255f 7556 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 7557 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7558 } else {
7559 if (clock->p1 == 2)
7560 dpll |= PLL_P1_DIVIDE_BY_TWO;
7561 else
7562 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7563 if (clock->p2 == 4)
7564 dpll |= PLL_P2_DIVIDE_BY_4;
7565 }
7566
a93e255f 7567 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
4a33e48d
DV		 7568 dpll |= DPLL_DVO_2X_MODE;
7569
a93e255f 7570 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 7571 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7572 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7573 else
7574 dpll |= PLL_REF_INPUT_DREFCLK;
7575
7576 dpll |= DPLL_VCO_ENABLE;
190f68c5 7577 crtc_state->dpll_hw_state.dpll = dpll;
eb1cbe48
DV		 7578}
7579
8a654f3b 7580static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
b0e77b9c
PZ		 7581{
7582 struct drm_device *dev = intel_crtc->base.dev;
7583 struct drm_i915_private *dev_priv = dev->dev_private;
7584 enum pipe pipe = intel_crtc->pipe;
6e3c9717 7585 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8a654f3b 7586 struct drm_display_mode *adjusted_mode =
6e3c9717 7587 &intel_crtc->config->base.adjusted_mode;
1caea6e9
VS		 7588 uint32_t crtc_vtotal, crtc_vblank_end;
7589 int vsyncshift = 0;
4d8a62ea
DV		 7590
7591 /* We need to be careful not to changed the adjusted mode, for otherwise
7592 * the hw state checker will get angry at the mismatch. */
7593 crtc_vtotal = adjusted_mode->crtc_vtotal;
7594 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
b0e77b9c 7595
609aeaca 7596 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
b0e77b9c 7597 /* the chip adds 2 halflines automatically */
4d8a62ea
DV		 7598 crtc_vtotal -= 1;
7599 crtc_vblank_end -= 1;
609aeaca 7600
409ee761 7601 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
609aeaca
VS		 7602 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7603 else
7604 vsyncshift = adjusted_mode->crtc_hsync_start -
7605 adjusted_mode->crtc_htotal / 2;
1caea6e9
VS		 7606 if (vsyncshift < 0)
7607 vsyncshift += adjusted_mode->crtc_htotal;
b0e77b9c
PZ		 7608 }
7609
7610 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 7611 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 7612
fe2b8f9d 7613 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 7614 (adjusted_mode->crtc_hdisplay - 1) |
7615 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 7616 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 7617 (adjusted_mode->crtc_hblank_start - 1) |
7618 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 7619 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 7620 (adjusted_mode->crtc_hsync_start - 1) |
7621 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7622
fe2b8f9d 7623 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c 7624 (adjusted_mode->crtc_vdisplay - 1) |
4d8a62ea 7625 ((crtc_vtotal - 1) << 16));
fe2b8f9d 7626 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c 7627 (adjusted_mode->crtc_vblank_start - 1) |
4d8a62ea 7628 ((crtc_vblank_end - 1) << 16));
fe2b8f9d 7629 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 7630 (adjusted_mode->crtc_vsync_start - 1) |
7631 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7632
b5e508d4
PZ		 7633 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7634 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7635 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7636 * bits. */
7637 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7638 (pipe == PIPE_B || pipe == PIPE_C))
7639 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7640
b0e77b9c
PZ		 7641 /* pipesrc controls the size that is scaled from, which should
7642 * always be the user's requested size.
7643 */
7644 I915_WRITE(PIPESRC(pipe),
6e3c9717
ACO		 7645 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7646 (intel_crtc->config->pipe_src_h - 1));
b0e77b9c
PZ		 7647}
7648
1bd1bd80 7649static void intel_get_pipe_timings(struct intel_crtc *crtc,
5cec258b 7650 struct intel_crtc_state *pipe_config)
1bd1bd80
DV		 7651{
7652 struct drm_device *dev = crtc->base.dev;
7653 struct drm_i915_private *dev_priv = dev->dev_private;
7654 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7655 uint32_t tmp;
7656
7657 tmp = I915_READ(HTOTAL(cpu_transcoder));
2d112de7
ACO		 7658 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7659 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7660 tmp = I915_READ(HBLANK(cpu_transcoder));
2d112de7
ACO		 7661 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7662 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7663 tmp = I915_READ(HSYNC(cpu_transcoder));
2d112de7
ACO		 7664 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7665 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80
DV		 7666
7667 tmp = I915_READ(VTOTAL(cpu_transcoder));
2d112de7
ACO		 7668 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7669 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7670 tmp = I915_READ(VBLANK(cpu_transcoder));
2d112de7
ACO		 7671 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7672 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7673 tmp = I915_READ(VSYNC(cpu_transcoder));
2d112de7
ACO		 7674 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7675 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80
DV		 7676
7677 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
2d112de7
ACO		 7678 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7679 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7680 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
1bd1bd80
DV		 7681 }
7682
7683 tmp = I915_READ(PIPESRC(crtc->pipe));
37327abd
VS		 7684 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7685 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7686
2d112de7
ACO		 7687 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7688 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
1bd1bd80
DV		 7689}
7690
f6a83288 7691void intel_mode_from_pipe_config(struct drm_display_mode *mode,
5cec258b 7692 struct intel_crtc_state *pipe_config)
babea61d 7693{
2d112de7
ACO		 7694 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7695 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7696 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7697 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
babea61d 7698
2d112de7
ACO		 7699 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7700 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7701 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7702 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
babea61d 7703
2d112de7 7704 mode->flags = pipe_config->base.adjusted_mode.flags;
cd13f5ab 7705 mode->type = DRM_MODE_TYPE_DRIVER;
babea61d 7706
2d112de7
ACO		 7707 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7708 mode->flags |= pipe_config->base.adjusted_mode.flags;
cd13f5ab
ML		 7709
7710 mode->hsync = drm_mode_hsync(mode);
7711 mode->vrefresh = drm_mode_vrefresh(mode);
7712 drm_mode_set_name(mode);
babea61d
JB		 7713}
7714
84b046f3
DV		 7715static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7716{
7717 struct drm_device *dev = intel_crtc->base.dev;
7718 struct drm_i915_private *dev_priv = dev->dev_private;
7719 uint32_t pipeconf;
7720
9f11a9e4 7721 pipeconf = 0;
84b046f3 7722
b6b5d049
VS		 7723 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7724 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7725 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
67c72a12 7726
6e3c9717 7727 if (intel_crtc->config->double_wide)
cf532bb2 7728 pipeconf |= PIPECONF_DOUBLE_WIDE;
84b046f3 7729
ff9ce46e
DV		 7730 /* only g4x and later have fancy bpc/dither controls */
7731 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
ff9ce46e 7732 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6e3c9717 7733 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
ff9ce46e 7734 pipeconf |= PIPECONF_DITHER_EN |
84b046f3 7735 PIPECONF_DITHER_TYPE_SP;
84b046f3 7736
6e3c9717 7737 switch (intel_crtc->config->pipe_bpp) {
ff9ce46e
DV		 7738 case 18:
7739 pipeconf |= PIPECONF_6BPC;
7740 break;
7741 case 24:
7742 pipeconf |= PIPECONF_8BPC;
7743 break;
7744 case 30:
7745 pipeconf |= PIPECONF_10BPC;
7746 break;
7747 default:
7748 /* Case prevented by intel_choose_pipe_bpp_dither. */
7749 BUG();
84b046f3
DV		 7750 }
7751 }
7752
7753 if (HAS_PIPE_CXSR(dev)) {
7754 if (intel_crtc->lowfreq_avail) {
7755 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7756 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7757 } else {
7758 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
84b046f3
DV		 7759 }
7760 }
7761
6e3c9717 7762 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
efc2cfff 7763 if (INTEL_INFO(dev)->gen < 4 ||
409ee761 7764 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
efc2cfff
VS		 7765 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7766 else
7767 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7768 } else
84b046f3
DV		 7769 pipeconf |= PIPECONF_PROGRESSIVE;
7770
6e3c9717 7771 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
9f11a9e4 7772 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
9c8e09b7 7773
84b046f3
DV		 7774 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7775 POSTING_READ(PIPECONF(intel_crtc->pipe));
7776}
7777
190f68c5
ACO		 7778static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7779 struct intel_crtc_state *crtc_state)
79e53945 7780{
c7653199 7781 struct drm_device *dev = crtc->base.dev;
79e53945 7782 struct drm_i915_private *dev_priv = dev->dev_private;
c751ce4f 7783 int refclk, num_connectors = 0;
c329a4ec
DV		 7784 intel_clock_t clock;
7785 bool ok;
7786 bool is_dsi = false;
5eddb70b 7787 struct intel_encoder *encoder;
d4906093 7788 const intel_limit_t *limit;
55bb9992 7789 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 7790 struct drm_connector *connector;
55bb9992
ACO		 7791 struct drm_connector_state *connector_state;
7792 int i;
79e53945 7793
dd3cd74a
ACO		 7794 memset(&crtc_state->dpll_hw_state, 0,
7795 sizeof(crtc_state->dpll_hw_state));
7796
da3ced29 7797 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO		 7798 if (connector_state->crtc != &crtc->base)
7799 continue;
7800
7801 encoder = to_intel_encoder(connector_state->best_encoder);
7802
5eddb70b 7803 switch (encoder->type) {
e9fd1c02
JN		 7804 case INTEL_OUTPUT_DSI:
7805 is_dsi = true;
7806 break;
6847d71b
PZ		 7807 default:
7808 break;
79e53945 7809 }
43565a06 7810
c751ce4f 7811 num_connectors++;
79e53945
JB		 7812 }
7813
f2335330 7814 if (is_dsi)
5b18e57c 7815 return 0;
f2335330 7816
190f68c5 7817 if (!crtc_state->clock_set) {
a93e255f 7818 refclk = i9xx_get_refclk(crtc_state, num_connectors);
79e53945 7819
e9fd1c02
JN		 7820 /*
7821 * Returns a set of divisors for the desired target clock with
7822 * the given refclk, or FALSE. The returned values represent
7823 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7824 * 2) / p1 / p2.
7825 */
a93e255f
ACO		 7826 limit = intel_limit(crtc_state, refclk);
7827 ok = dev_priv->display.find_dpll(limit, crtc_state,
190f68c5 7828 crtc_state->port_clock,
e9fd1c02 7829 refclk, NULL, &clock);
f2335330 7830 if (!ok) {
e9fd1c02
JN		 7831 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7832 return -EINVAL;
7833 }
79e53945 7834
f2335330 7835 /* Compat-code for transition, will disappear. */
190f68c5
ACO		 7836 crtc_state->dpll.n = clock.n;
7837 crtc_state->dpll.m1 = clock.m1;
7838 crtc_state->dpll.m2 = clock.m2;
7839 crtc_state->dpll.p1 = clock.p1;
7840 crtc_state->dpll.p2 = clock.p2;
f47709a9 7841 }
7026d4ac 7842
e9fd1c02 7843 if (IS_GEN2(dev)) {
c329a4ec 7844 i8xx_compute_dpll(crtc, crtc_state, NULL,
251ac862 7845 num_connectors);
9d556c99 7846 } else if (IS_CHERRYVIEW(dev)) {
251ac862 7847 chv_compute_dpll(crtc, crtc_state);
e9fd1c02 7848 } else if (IS_VALLEYVIEW(dev)) {
251ac862 7849 vlv_compute_dpll(crtc, crtc_state);
e9fd1c02 7850 } else {
c329a4ec 7851 i9xx_compute_dpll(crtc, crtc_state, NULL,
251ac862 7852 num_connectors);
e9fd1c02 7853 }
79e53945 7854
c8f7a0db 7855 return 0;
f564048e
EA		 7856}
7857
2fa2fe9a 7858static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5cec258b 7859 struct intel_crtc_state *pipe_config)
2fa2fe9a
DV		 7860{
7861 struct drm_device *dev = crtc->base.dev;
7862 struct drm_i915_private *dev_priv = dev->dev_private;
7863 uint32_t tmp;
7864
dc9e7dec
VS		 7865 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7866 return;
7867
2fa2fe9a 7868 tmp = I915_READ(PFIT_CONTROL);
06922821
DV		 7869 if (!(tmp & PFIT_ENABLE))
7870 return;
2fa2fe9a 7871
06922821 7872 /* Check whether the pfit is attached to our pipe. */
2fa2fe9a
DV		 7873 if (INTEL_INFO(dev)->gen < 4) {
7874 if (crtc->pipe != PIPE_B)
7875 return;
2fa2fe9a
DV		 7876 } else {
7877 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7878 return;
7879 }
7880
06922821 7881 pipe_config->gmch_pfit.control = tmp;
2fa2fe9a
DV		 7882 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7883 if (INTEL_INFO(dev)->gen < 5)
7884 pipe_config->gmch_pfit.lvds_border_bits =
7885 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7886}
7887
acbec814 7888static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 7889 struct intel_crtc_state *pipe_config)
acbec814
JB		 7890{
7891 struct drm_device *dev = crtc->base.dev;
7892 struct drm_i915_private *dev_priv = dev->dev_private;
7893 int pipe = pipe_config->cpu_transcoder;
7894 intel_clock_t clock;
7895 u32 mdiv;
662c6ecb 7896 int refclk = 100000;
acbec814 7897
f573de5a
SK		 7898 /* In case of MIPI DPLL will not even be used */
7899 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
7900 return;
7901
a580516d 7902 mutex_lock(&dev_priv->sb_lock);
ab3c759a 7903 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
a580516d 7904 mutex_unlock(&dev_priv->sb_lock);
acbec814
JB		 7905
7906 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7907 clock.m2 = mdiv & DPIO_M2DIV_MASK;
7908 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7909 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7910 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7911
dccbea3b 7912 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
acbec814
JB		 7913}
7914
5724dbd1
DL		 7915static void
7916i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7917 struct intel_initial_plane_config *plane_config)
1ad292b5
JB		 7918{
7919 struct drm_device *dev = crtc->base.dev;
7920 struct drm_i915_private *dev_priv = dev->dev_private;
7921 u32 val, base, offset;
7922 int pipe = crtc->pipe, plane = crtc->plane;
7923 int fourcc, pixel_format;
6761dd31 7924 unsigned int aligned_height;
b113d5ee 7925 struct drm_framebuffer *fb;
1b842c89 7926 struct intel_framebuffer *intel_fb;
1ad292b5 7927
42a7b088
DL		 7928 val = I915_READ(DSPCNTR(plane));
7929 if (!(val & DISPLAY_PLANE_ENABLE))
7930 return;
7931
d9806c9f 7932 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 7933 if (!intel_fb) {
1ad292b5
JB		 7934 DRM_DEBUG_KMS("failed to alloc fb\n");
7935 return;
7936 }
7937
1b842c89
DL		 7938 fb = &intel_fb->base;
7939
18c5247e
DV		 7940 if (INTEL_INFO(dev)->gen >= 4) {
7941 if (val & DISPPLANE_TILED) {
49af449b 7942 plane_config->tiling = I915_TILING_X;
18c5247e
DV		 7943 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7944 }
7945 }
1ad292b5
JB		 7946
7947 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
b35d63fa 7948 fourcc = i9xx_format_to_fourcc(pixel_format);
b113d5ee
DL		 7949 fb->pixel_format = fourcc;
7950 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
1ad292b5
JB		 7951
7952 if (INTEL_INFO(dev)->gen >= 4) {
49af449b 7953 if (plane_config->tiling)
1ad292b5
JB		 7954 offset = I915_READ(DSPTILEOFF(plane));
7955 else
7956 offset = I915_READ(DSPLINOFF(plane));
7957 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7958 } else {
7959 base = I915_READ(DSPADDR(plane));
7960 }
7961 plane_config->base = base;
7962
7963 val = I915_READ(PIPESRC(pipe));
b113d5ee
DL		 7964 fb->width = ((val >> 16) & 0xfff) + 1;
7965 fb->height = ((val >> 0) & 0xfff) + 1;
1ad292b5
JB		 7966
7967 val = I915_READ(DSPSTRIDE(pipe));
b113d5ee 7968 fb->pitches[0] = val & 0xffffffc0;
1ad292b5 7969
b113d5ee 7970 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 7971 fb->pixel_format,
7972 fb->modifier[0]);
1ad292b5 7973
f37b5c2b 7974 plane_config->size = fb->pitches[0] * aligned_height;
1ad292b5 7975
2844a921
DL		 7976 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7977 pipe_name(pipe), plane, fb->width, fb->height,
7978 fb->bits_per_pixel, base, fb->pitches[0],
7979 plane_config->size);
1ad292b5 7980
2d14030b 7981 plane_config->fb = intel_fb;
1ad292b5
JB		 7982}
7983
70b23a98 7984static void chv_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 7985 struct intel_crtc_state *pipe_config)
70b23a98
VS		 7986{
7987 struct drm_device *dev = crtc->base.dev;
7988 struct drm_i915_private *dev_priv = dev->dev_private;
7989 int pipe = pipe_config->cpu_transcoder;
7990 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7991 intel_clock_t clock;
0d7b6b11 7992 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
70b23a98
VS		 7993 int refclk = 100000;
7994
a580516d 7995 mutex_lock(&dev_priv->sb_lock);
70b23a98
VS		 7996 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
7997 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
7998 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
7999 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
0d7b6b11 8000 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
a580516d 8001 mutex_unlock(&dev_priv->sb_lock);
70b23a98
VS		 8002
8003 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
0d7b6b11
ID		 8004 clock.m2 = (pll_dw0 & 0xff) << 22;
8005 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8006 clock.m2 |= pll_dw2 & 0x3fffff;
70b23a98
VS		 8007 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8008 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8009 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8010
dccbea3b 8011 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
70b23a98
VS		 8012}
8013
0e8ffe1b 8014static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5cec258b 8015 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 8016{
8017 struct drm_device *dev = crtc->base.dev;
8018 struct drm_i915_private *dev_priv = dev->dev_private;
8019 uint32_t tmp;
8020
f458ebbc
DV		 8021 if (!intel_display_power_is_enabled(dev_priv,
8022 POWER_DOMAIN_PIPE(crtc->pipe)))
b5482bd0
ID		 8023 return false;
8024
e143a21c 8025 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 8026 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 8027
0e8ffe1b
DV		 8028 tmp = I915_READ(PIPECONF(crtc->pipe));
8029 if (!(tmp & PIPECONF_ENABLE))
8030 return false;
8031
42571aef
VS		 8032 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
8033 switch (tmp & PIPECONF_BPC_MASK) {
8034 case PIPECONF_6BPC:
8035 pipe_config->pipe_bpp = 18;
8036 break;
8037 case PIPECONF_8BPC:
8038 pipe_config->pipe_bpp = 24;
8039 break;
8040 case PIPECONF_10BPC:
8041 pipe_config->pipe_bpp = 30;
8042 break;
8043 default:
8044 break;
8045 }
8046 }
8047
b5a9fa09
DV		 8048 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
8049 pipe_config->limited_color_range = true;
8050
282740f7
VS		 8051 if (INTEL_INFO(dev)->gen < 4)
8052 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8053
1bd1bd80
DV		 8054 intel_get_pipe_timings(crtc, pipe_config);
8055
2fa2fe9a
DV		 8056 i9xx_get_pfit_config(crtc, pipe_config);
8057
6c49f241
DV		 8058 if (INTEL_INFO(dev)->gen >= 4) {
8059 tmp = I915_READ(DPLL_MD(crtc->pipe));
8060 pipe_config->pixel_multiplier =
8061 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8062 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8bcc2795 8063 pipe_config->dpll_hw_state.dpll_md = tmp;
6c49f241
DV		 8064 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8065 tmp = I915_READ(DPLL(crtc->pipe));
8066 pipe_config->pixel_multiplier =
8067 ((tmp & SDVO_MULTIPLIER_MASK)
8068 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8069 } else {
8070 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8071 * port and will be fixed up in the encoder->get_config
8072 * function. */
8073 pipe_config->pixel_multiplier = 1;
8074 }
8bcc2795
DV		 8075 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8076 if (!IS_VALLEYVIEW(dev)) {
1c4e0274
VS		 8077 /*
8078 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8079 * on 830. Filter it out here so that we don't
8080 * report errors due to that.
8081 */
8082 if (IS_I830(dev))
8083 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8084
8bcc2795
DV		 8085 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8086 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
165e901c
VS		 8087 } else {
8088 /* Mask out read-only status bits. */
8089 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8090 DPLL_PORTC_READY_MASK |
8091 DPLL_PORTB_READY_MASK);
8bcc2795 8092 }
6c49f241 8093
70b23a98
VS		 8094 if (IS_CHERRYVIEW(dev))
8095 chv_crtc_clock_get(crtc, pipe_config);
8096 else if (IS_VALLEYVIEW(dev))
acbec814
JB		 8097 vlv_crtc_clock_get(crtc, pipe_config);
8098 else
8099 i9xx_crtc_clock_get(crtc, pipe_config);
18442d08 8100
0f64614d
VS		 8101 /*
8102 * Normally the dotclock is filled in by the encoder .get_config()
8103 * but in case the pipe is enabled w/o any ports we need a sane
8104 * default.
8105 */
8106 pipe_config->base.adjusted_mode.crtc_clock =
8107 pipe_config->port_clock / pipe_config->pixel_multiplier;
8108
0e8ffe1b
DV		 8109 return true;
8110}
8111
dde86e2d 8112static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 8113{
8114 struct drm_i915_private *dev_priv = dev->dev_private;
13d83a67 8115 struct intel_encoder *encoder;
74cfd7ac 8116 u32 val, final;
13d83a67 8117 bool has_lvds = false;
199e5d79 8118 bool has_cpu_edp = false;
199e5d79 8119 bool has_panel = false;
99eb6a01
KP		 8120 bool has_ck505 = false;
8121 bool can_ssc = false;
13d83a67
JB		 8122
8123 /* We need to take the global config into account */
b2784e15 8124 for_each_intel_encoder(dev, encoder) {
199e5d79
KP		 8125 switch (encoder->type) {
8126 case INTEL_OUTPUT_LVDS:
8127 has_panel = true;
8128 has_lvds = true;
8129 break;
8130 case INTEL_OUTPUT_EDP:
8131 has_panel = true;
2de6905f 8132 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
199e5d79
KP		 8133 has_cpu_edp = true;
8134 break;
6847d71b
PZ		 8135 default:
8136 break;
13d83a67
JB		 8137 }
8138 }
8139
99eb6a01 8140 if (HAS_PCH_IBX(dev)) {
41aa3448 8141 has_ck505 = dev_priv->vbt.display_clock_mode;
99eb6a01
KP		 8142 can_ssc = has_ck505;
8143 } else {
8144 has_ck505 = false;
8145 can_ssc = true;
8146 }
8147
2de6905f
ID		 8148 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8149 has_panel, has_lvds, has_ck505);
13d83a67
JB		 8150
8151 /* Ironlake: try to setup display ref clock before DPLL
8152 * enabling. This is only under driver's control after
8153 * PCH B stepping, previous chipset stepping should be
8154 * ignoring this setting.
8155 */
74cfd7ac
CW		 8156 val = I915_READ(PCH_DREF_CONTROL);
8157
8158 /* As we must carefully and slowly disable/enable each source in turn,
8159 * compute the final state we want first and check if we need to
8160 * make any changes at all.
8161 */
8162 final = val;
8163 final &= ~DREF_NONSPREAD_SOURCE_MASK;
8164 if (has_ck505)
8165 final |= DREF_NONSPREAD_CK505_ENABLE;
8166 else
8167 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8168
8169 final &= ~DREF_SSC_SOURCE_MASK;
8170 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8171 final &= ~DREF_SSC1_ENABLE;
8172
8173 if (has_panel) {
8174 final |= DREF_SSC_SOURCE_ENABLE;
8175
8176 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8177 final |= DREF_SSC1_ENABLE;
8178
8179 if (has_cpu_edp) {
8180 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8181 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8182 else
8183 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8184 } else
8185 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8186 } else {
8187 final |= DREF_SSC_SOURCE_DISABLE;
8188 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8189 }
8190
8191 if (final == val)
8192 return;
8193
13d83a67 8194 /* Always enable nonspread source */
74cfd7ac 8195 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 8196
99eb6a01 8197 if (has_ck505)
74cfd7ac 8198 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 8199 else
74cfd7ac 8200 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 8201
199e5d79 8202 if (has_panel) {
74cfd7ac
CW		 8203 val &= ~DREF_SSC_SOURCE_MASK;
8204 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 8205
199e5d79 8206 /* SSC must be turned on before enabling the CPU output */
99eb6a01 8207 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 8208 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 8209 val |= DREF_SSC1_ENABLE;
e77166b5 8210 } else
74cfd7ac 8211 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 8212
8213 /* Get SSC going before enabling the outputs */
74cfd7ac 8214 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 8215 POSTING_READ(PCH_DREF_CONTROL);
8216 udelay(200);
8217
74cfd7ac 8218 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 8219
8220 /* Enable CPU source on CPU attached eDP */
199e5d79 8221 if (has_cpu_edp) {
99eb6a01 8222 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 8223 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 8224 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
eba905b2 8225 } else
74cfd7ac 8226 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 8227 } else
74cfd7ac 8228 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 8229
74cfd7ac 8230 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 8231 POSTING_READ(PCH_DREF_CONTROL);
8232 udelay(200);
8233 } else {
8234 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8235
74cfd7ac 8236 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 8237
8238 /* Turn off CPU output */
74cfd7ac 8239 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 8240
74cfd7ac 8241 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 8242 POSTING_READ(PCH_DREF_CONTROL);
8243 udelay(200);
8244
8245 /* Turn off the SSC source */
74cfd7ac
CW		 8246 val &= ~DREF_SSC_SOURCE_MASK;
8247 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 8248
8249 /* Turn off SSC1 */
74cfd7ac 8250 val &= ~DREF_SSC1_ENABLE;
199e5d79 8251
74cfd7ac 8252 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 8253 POSTING_READ(PCH_DREF_CONTROL);
8254 udelay(200);
8255 }
74cfd7ac
CW		 8256
8257 BUG_ON(val != final);
13d83a67
JB		 8258}
8259
f31f2d55 8260static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
dde86e2d 8261{
f31f2d55 8262 uint32_t tmp;
dde86e2d 8263
0ff066a9
PZ		 8264 tmp = I915_READ(SOUTH_CHICKEN2);
8265 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8266 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 8267
0ff066a9
PZ		 8268 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8269 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8270 DRM_ERROR("FDI mPHY reset assert timeout\n");
dde86e2d 8271
0ff066a9
PZ		 8272 tmp = I915_READ(SOUTH_CHICKEN2);
8273 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8274 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 8275
0ff066a9
PZ		 8276 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8277 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8278 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
f31f2d55
PZ		 8279}
8280
8281/* WaMPhyProgramming:hsw */
8282static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8283{
8284 uint32_t tmp;
dde86e2d
PZ		 8285
8286 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8287 tmp &= ~(0xFF << 24);
8288 tmp |= (0x12 << 24);
8289 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8290
dde86e2d
PZ		 8291 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8292 tmp |= (1 << 11);
8293 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8294
8295 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8296 tmp |= (1 << 11);
8297 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8298
dde86e2d
PZ		 8299 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8300 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8301 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8302
8303 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8304 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8305 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8306
0ff066a9
PZ		 8307 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8308 tmp &= ~(7 << 13);
8309 tmp |= (5 << 13);
8310 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
dde86e2d 8311
0ff066a9
PZ		 8312 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8313 tmp &= ~(7 << 13);
8314 tmp |= (5 << 13);
8315 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
dde86e2d
PZ		 8316
8317 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8318 tmp &= ~0xFF;
8319 tmp |= 0x1C;
8320 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8321
8322 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8323 tmp &= ~0xFF;
8324 tmp |= 0x1C;
8325 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8326
8327 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8328 tmp &= ~(0xFF << 16);
8329 tmp |= (0x1C << 16);
8330 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8331
8332 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8333 tmp &= ~(0xFF << 16);
8334 tmp |= (0x1C << 16);
8335 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8336
0ff066a9
PZ		 8337 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8338 tmp |= (1 << 27);
8339 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
dde86e2d 8340
0ff066a9
PZ		 8341 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8342 tmp |= (1 << 27);
8343 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
dde86e2d 8344
0ff066a9
PZ		 8345 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8346 tmp &= ~(0xF << 28);
8347 tmp |= (4 << 28);
8348 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
dde86e2d 8349
0ff066a9
PZ		 8350 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8351 tmp &= ~(0xF << 28);
8352 tmp |= (4 << 28);
8353 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
f31f2d55
PZ		 8354}
8355
2fa86a1f
PZ		 8356/* Implements 3 different sequences from BSpec chapter "Display iCLK
8357 * Programming" based on the parameters passed:
8358 * - Sequence to enable CLKOUT_DP
8359 * - Sequence to enable CLKOUT_DP without spread
8360 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8361 */
8362static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8363 bool with_fdi)
f31f2d55
PZ		 8364{
8365 struct drm_i915_private *dev_priv = dev->dev_private;
2fa86a1f
PZ		 8366 uint32_t reg, tmp;
8367
8368 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8369 with_spread = true;
c2699524 8370 if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n"))
2fa86a1f 8371 with_fdi = false;
f31f2d55 8372
a580516d 8373 mutex_lock(&dev_priv->sb_lock);
f31f2d55
PZ		 8374
8375 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8376 tmp &= ~SBI_SSCCTL_DISABLE;
8377 tmp |= SBI_SSCCTL_PATHALT;
8378 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8379
8380 udelay(24);
8381
2fa86a1f
PZ		 8382 if (with_spread) {
8383 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8384 tmp &= ~SBI_SSCCTL_PATHALT;
8385 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
f31f2d55 8386
2fa86a1f
PZ		 8387 if (with_fdi) {
8388 lpt_reset_fdi_mphy(dev_priv);
8389 lpt_program_fdi_mphy(dev_priv);
8390 }
8391 }
dde86e2d 8392
c2699524 8393 reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
2fa86a1f
PZ		 8394 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8395 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8396 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
c00db246 8397
a580516d 8398 mutex_unlock(&dev_priv->sb_lock);
dde86e2d
PZ		 8399}
8400
47701c3b
PZ		 8401/* Sequence to disable CLKOUT_DP */
8402static void lpt_disable_clkout_dp(struct drm_device *dev)
8403{
8404 struct drm_i915_private *dev_priv = dev->dev_private;
8405 uint32_t reg, tmp;
8406
a580516d 8407 mutex_lock(&dev_priv->sb_lock);
47701c3b 8408
c2699524 8409 reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
47701c3b
PZ		 8410 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8411 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8412 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8413
8414 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8415 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8416 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8417 tmp |= SBI_SSCCTL_PATHALT;
8418 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8419 udelay(32);
8420 }
8421 tmp |= SBI_SSCCTL_DISABLE;
8422 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8423 }
8424
a580516d 8425 mutex_unlock(&dev_priv->sb_lock);
47701c3b
PZ		 8426}
8427
bf8fa3d3
PZ		 8428static void lpt_init_pch_refclk(struct drm_device *dev)
8429{
bf8fa3d3
PZ		 8430 struct intel_encoder *encoder;
8431 bool has_vga = false;
8432
b2784e15 8433 for_each_intel_encoder(dev, encoder) {
bf8fa3d3
PZ		 8434 switch (encoder->type) {
8435 case INTEL_OUTPUT_ANALOG:
8436 has_vga = true;
8437 break;
6847d71b
PZ		 8438 default:
8439 break;
bf8fa3d3
PZ		 8440 }
8441 }
8442
47701c3b
PZ		 8443 if (has_vga)
8444 lpt_enable_clkout_dp(dev, true, true);
8445 else
8446 lpt_disable_clkout_dp(dev);
bf8fa3d3
PZ		 8447}
8448
dde86e2d
PZ		 8449/*
8450 * Initialize reference clocks when the driver loads
8451 */
8452void intel_init_pch_refclk(struct drm_device *dev)
8453{
8454 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8455 ironlake_init_pch_refclk(dev);
8456 else if (HAS_PCH_LPT(dev))
8457 lpt_init_pch_refclk(dev);
8458}
8459
55bb9992 8460static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
d9d444cb 8461{
55bb9992 8462 struct drm_device *dev = crtc_state->base.crtc->dev;
d9d444cb 8463 struct drm_i915_private *dev_priv = dev->dev_private;
55bb9992 8464 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 8465 struct drm_connector *connector;
55bb9992 8466 struct drm_connector_state *connector_state;
d9d444cb 8467 struct intel_encoder *encoder;
55bb9992 8468 int num_connectors = 0, i;
d9d444cb
JB		 8469 bool is_lvds = false;
8470
da3ced29 8471 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO		 8472 if (connector_state->crtc != crtc_state->base.crtc)
8473 continue;
8474
8475 encoder = to_intel_encoder(connector_state->best_encoder);
8476
d9d444cb
JB		 8477 switch (encoder->type) {
8478 case INTEL_OUTPUT_LVDS:
8479 is_lvds = true;
8480 break;
6847d71b
PZ		 8481 default:
8482 break;
d9d444cb
JB		 8483 }
8484 num_connectors++;
8485 }
8486
8487 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
e91e941b 8488 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
41aa3448 8489 dev_priv->vbt.lvds_ssc_freq);
e91e941b 8490 return dev_priv->vbt.lvds_ssc_freq;
d9d444cb
JB		 8491 }
8492
8493 return 120000;
8494}
8495
6ff93609 8496static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 8497{
c8203565 8498 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 8499 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8500 int pipe = intel_crtc->pipe;
c8203565
PZ		 8501 uint32_t val;
8502
78114071 8503 val = 0;
c8203565 8504
6e3c9717 8505 switch (intel_crtc->config->pipe_bpp) {
c8203565 8506 case 18:
dfd07d72 8507 val |= PIPECONF_6BPC;
c8203565
PZ		 8508 break;
8509 case 24:
dfd07d72 8510 val |= PIPECONF_8BPC;
c8203565
PZ		 8511 break;
8512 case 30:
dfd07d72 8513 val |= PIPECONF_10BPC;
c8203565
PZ		 8514 break;
8515 case 36:
dfd07d72 8516 val |= PIPECONF_12BPC;
c8203565
PZ		 8517 break;
8518 default:
cc769b62
PZ		 8519 /* Case prevented by intel_choose_pipe_bpp_dither. */
8520 BUG();
c8203565
PZ		 8521 }
8522
6e3c9717 8523 if (intel_crtc->config->dither)
c8203565
PZ		 8524 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8525
6e3c9717 8526 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ		 8527 val |= PIPECONF_INTERLACED_ILK;
8528 else
8529 val |= PIPECONF_PROGRESSIVE;
8530
6e3c9717 8531 if (intel_crtc->config->limited_color_range)
3685a8f3 8532 val |= PIPECONF_COLOR_RANGE_SELECT;
3685a8f3 8533
c8203565
PZ		 8534 I915_WRITE(PIPECONF(pipe), val);
8535 POSTING_READ(PIPECONF(pipe));
8536}
8537
86d3efce
VS		 8538/*
8539 * Set up the pipe CSC unit.
8540 *
8541 * Currently only full range RGB to limited range RGB conversion
8542 * is supported, but eventually this should handle various
8543 * RGB<->YCbCr scenarios as well.
8544 */
50f3b016 8545static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 8546{
8547 struct drm_device *dev = crtc->dev;
8548 struct drm_i915_private *dev_priv = dev->dev_private;
8549 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8550 int pipe = intel_crtc->pipe;
8551 uint16_t coeff = 0x7800; /* 1.0 */
8552
8553 /*
8554 * TODO: Check what kind of values actually come out of the pipe
8555 * with these coeff/postoff values and adjust to get the best
8556 * accuracy. Perhaps we even need to take the bpc value into
8557 * consideration.
8558 */
8559
6e3c9717 8560 if (intel_crtc->config->limited_color_range)
86d3efce
VS		 8561 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8562
8563 /*
8564 * GY/GU and RY/RU should be the other way around according
8565 * to BSpec, but reality doesn't agree. Just set them up in
8566 * a way that results in the correct picture.
8567 */
8568 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8569 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8570
8571 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8572 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8573
8574 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8575 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8576
8577 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8578 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8579 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8580
8581 if (INTEL_INFO(dev)->gen > 6) {
8582 uint16_t postoff = 0;
8583
6e3c9717 8584 if (intel_crtc->config->limited_color_range)
32cf0cb0 8585 postoff = (16 * (1 << 12) / 255) & 0x1fff;
86d3efce
VS		 8586
8587 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8588 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8589 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8590
8591 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8592 } else {
8593 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8594
6e3c9717 8595 if (intel_crtc->config->limited_color_range)
86d3efce
VS		 8596 mode |= CSC_BLACK_SCREEN_OFFSET;
8597
8598 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8599 }
8600}
8601
6ff93609 8602static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38 8603{
756f85cf
PZ		 8604 struct drm_device *dev = crtc->dev;
8605 struct drm_i915_private *dev_priv = dev->dev_private;
ee2b0b38 8606 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
756f85cf 8607 enum pipe pipe = intel_crtc->pipe;
6e3c9717 8608 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
ee2b0b38
PZ		 8609 uint32_t val;
8610
3eff4faa 8611 val = 0;
ee2b0b38 8612
6e3c9717 8613 if (IS_HASWELL(dev) && intel_crtc->config->dither)
ee2b0b38
PZ		 8614 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8615
6e3c9717 8616 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ		 8617 val |= PIPECONF_INTERLACED_ILK;
8618 else
8619 val |= PIPECONF_PROGRESSIVE;
8620
702e7a56
PZ		 8621 I915_WRITE(PIPECONF(cpu_transcoder), val);
8622 POSTING_READ(PIPECONF(cpu_transcoder));
3eff4faa
DV		 8623
8624 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8625 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
756f85cf 8626
3cdf122c 8627 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
756f85cf
PZ		 8628 val = 0;
8629
6e3c9717 8630 switch (intel_crtc->config->pipe_bpp) {
756f85cf
PZ		 8631 case 18:
8632 val |= PIPEMISC_DITHER_6_BPC;
8633 break;
8634 case 24:
8635 val |= PIPEMISC_DITHER_8_BPC;
8636 break;
8637 case 30:
8638 val |= PIPEMISC_DITHER_10_BPC;
8639 break;
8640 case 36:
8641 val |= PIPEMISC_DITHER_12_BPC;
8642 break;
8643 default:
8644 /* Case prevented by pipe_config_set_bpp. */
8645 BUG();
8646 }
8647
6e3c9717 8648 if (intel_crtc->config->dither)
756f85cf
PZ		 8649 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8650
8651 I915_WRITE(PIPEMISC(pipe), val);
8652 }
ee2b0b38
PZ		 8653}
8654
6591c6e4 8655static bool ironlake_compute_clocks(struct drm_crtc *crtc,
190f68c5 8656 struct intel_crtc_state *crtc_state,
6591c6e4
PZ		 8657 intel_clock_t *clock,
8658 bool *has_reduced_clock,
8659 intel_clock_t *reduced_clock)
8660{
8661 struct drm_device *dev = crtc->dev;
8662 struct drm_i915_private *dev_priv = dev->dev_private;
6591c6e4 8663 int refclk;
d4906093 8664 const intel_limit_t *limit;
c329a4ec 8665 bool ret;
79e53945 8666
55bb9992 8667 refclk = ironlake_get_refclk(crtc_state);
79e53945 8668
d4906093
ML		 8669 /*
8670 * Returns a set of divisors for the desired target clock with the given
8671 * refclk, or FALSE. The returned values represent the clock equation:
8672 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8673 */
a93e255f
ACO		 8674 limit = intel_limit(crtc_state, refclk);
8675 ret = dev_priv->display.find_dpll(limit, crtc_state,
190f68c5 8676 crtc_state->port_clock,
ee9300bb 8677 refclk, NULL, clock);
6591c6e4
PZ		 8678 if (!ret)
8679 return false;
cda4b7d3 8680
6591c6e4
PZ		 8681 return true;
8682}
8683
d4b1931c
PZ		 8684int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8685{
8686 /*
8687 * Account for spread spectrum to avoid
8688 * oversubscribing the link. Max center spread
8689 * is 2.5%; use 5% for safety's sake.
8690 */
8691 u32 bps = target_clock * bpp * 21 / 20;
619d4d04 8692 return DIV_ROUND_UP(bps, link_bw * 8);
d4b1931c
PZ		 8693}
8694
7429e9d4 8695static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6cf86a5e 8696{
7429e9d4 8697 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
f48d8f23
PZ		 8698}
8699
de13a2e3 8700static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
190f68c5 8701 struct intel_crtc_state *crtc_state,
7429e9d4 8702 u32 *fp,
9a7c7890 8703 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 8704{
de13a2e3 8705 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 8706 struct drm_device *dev = crtc->dev;
8707 struct drm_i915_private *dev_priv = dev->dev_private;
55bb9992 8708 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 8709 struct drm_connector *connector;
55bb9992
ACO		 8710 struct drm_connector_state *connector_state;
8711 struct intel_encoder *encoder;
de13a2e3 8712 uint32_t dpll;
55bb9992 8713 int factor, num_connectors = 0, i;
09ede541 8714 bool is_lvds = false, is_sdvo = false;
79e53945 8715
da3ced29 8716 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO		 8717 if (connector_state->crtc != crtc_state->base.crtc)
8718 continue;
8719
8720 encoder = to_intel_encoder(connector_state->best_encoder);
8721
8722 switch (encoder->type) {
79e53945
JB		 8723 case INTEL_OUTPUT_LVDS:
8724 is_lvds = true;
8725 break;
8726 case INTEL_OUTPUT_SDVO:
7d57382e 8727 case INTEL_OUTPUT_HDMI:
79e53945 8728 is_sdvo = true;
79e53945 8729 break;
6847d71b
PZ		 8730 default:
8731 break;
79e53945 8732 }
43565a06 8733
c751ce4f 8734 num_connectors++;
79e53945 8735 }
79e53945 8736
c1858123 8737 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 8738 factor = 21;
8739 if (is_lvds) {
8740 if ((intel_panel_use_ssc(dev_priv) &&
e91e941b 8741 dev_priv->vbt.lvds_ssc_freq == 100000) ||
f0b44056 8742 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297 8743 factor = 25;
190f68c5 8744 } else if (crtc_state->sdvo_tv_clock)
8febb297 8745 factor = 20;
c1858123 8746
190f68c5 8747 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
7d0ac5b7 8748 *fp |= FP_CB_TUNE;
2c07245f 8749
9a7c7890
DV		 8750 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8751 *fp2 |= FP_CB_TUNE;
8752
5eddb70b 8753 dpll = 0;
2c07245f 8754
a07d6787
EA		 8755 if (is_lvds)
8756 dpll |= DPLLB_MODE_LVDS;
8757 else
8758 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f 8759
190f68c5 8760 dpll |= (crtc_state->pixel_multiplier - 1)
ef1b460d 8761 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
198a037f
DV		 8762
8763 if (is_sdvo)
4a33e48d 8764 dpll |= DPLL_SDVO_HIGH_SPEED;
190f68c5 8765 if (crtc_state->has_dp_encoder)
4a33e48d 8766 dpll |= DPLL_SDVO_HIGH_SPEED;
79e53945 8767
a07d6787 8768 /* compute bitmask from p1 value */
190f68c5 8769 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 8770 /* also FPA1 */
190f68c5 8771 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 8772
190f68c5 8773 switch (crtc_state->dpll.p2) {
a07d6787
EA		 8774 case 5:
8775 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8776 break;
8777 case 7:
8778 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8779 break;
8780 case 10:
8781 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8782 break;
8783 case 14:
8784 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8785 break;
79e53945
JB		 8786 }
8787
b4c09f3b 8788 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 8789 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 8790 else
8791 dpll |= PLL_REF_INPUT_DREFCLK;
8792
959e16d6 8793 return dpll | DPLL_VCO_ENABLE;
de13a2e3
PZ		 8794}
8795
190f68c5
ACO		 8796static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8797 struct intel_crtc_state *crtc_state)
de13a2e3 8798{
c7653199 8799 struct drm_device *dev = crtc->base.dev;
de13a2e3 8800 intel_clock_t clock, reduced_clock;
cbbab5bd 8801 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 8802 bool ok, has_reduced_clock = false;
8b47047b 8803 bool is_lvds = false;
e2b78267 8804 struct intel_shared_dpll *pll;
de13a2e3 8805
dd3cd74a
ACO		 8806 memset(&crtc_state->dpll_hw_state, 0,
8807 sizeof(crtc_state->dpll_hw_state));
8808
409ee761 8809 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
79e53945 8810
5dc5298b
PZ		 8811 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8812 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 8813
190f68c5 8814 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
de13a2e3 8815 &has_reduced_clock, &reduced_clock);
190f68c5 8816 if (!ok && !crtc_state->clock_set) {
de13a2e3
PZ		 8817 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8818 return -EINVAL;
79e53945 8819 }
f47709a9 8820 /* Compat-code for transition, will disappear. */
190f68c5
ACO		 8821 if (!crtc_state->clock_set) {
8822 crtc_state->dpll.n = clock.n;
8823 crtc_state->dpll.m1 = clock.m1;
8824 crtc_state->dpll.m2 = clock.m2;
8825 crtc_state->dpll.p1 = clock.p1;
8826 crtc_state->dpll.p2 = clock.p2;
f47709a9 8827 }
79e53945 8828
5dc5298b 8829 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
190f68c5
ACO		 8830 if (crtc_state->has_pch_encoder) {
8831 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
cbbab5bd 8832 if (has_reduced_clock)
7429e9d4 8833 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 8834
190f68c5 8835 dpll = ironlake_compute_dpll(crtc, crtc_state,
cbbab5bd
DV		 8836 &fp, &reduced_clock,
8837 has_reduced_clock ? &fp2 : NULL);
8838
190f68c5
ACO		 8839 crtc_state->dpll_hw_state.dpll = dpll;
8840 crtc_state->dpll_hw_state.fp0 = fp;
66e985c0 8841 if (has_reduced_clock)
190f68c5 8842 crtc_state->dpll_hw_state.fp1 = fp2;
66e985c0 8843 else
190f68c5 8844 crtc_state->dpll_hw_state.fp1 = fp;
66e985c0 8845
190f68c5 8846 pll = intel_get_shared_dpll(crtc, crtc_state);
ee7b9f93 8847 if (pll == NULL) {
84f44ce7 8848 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
c7653199 8849 pipe_name(crtc->pipe));
4b645f14
JB		 8850 return -EINVAL;
8851 }
3fb37703 8852 }
79e53945 8853
ab585dea 8854 if (is_lvds && has_reduced_clock)
c7653199 8855 crtc->lowfreq_avail = true;
bcd644e0 8856 else
c7653199 8857 crtc->lowfreq_avail = false;
e2b78267 8858
c8f7a0db 8859 return 0;
79e53945
JB		 8860}
8861
eb14cb74
VS		 8862static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8863 struct intel_link_m_n *m_n)
8864{
8865 struct drm_device *dev = crtc->base.dev;
8866 struct drm_i915_private *dev_priv = dev->dev_private;
8867 enum pipe pipe = crtc->pipe;
8868
8869 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8870 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8871 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8872 & ~TU_SIZE_MASK;
8873 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8874 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8875 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8876}
8877
8878static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8879 enum transcoder transcoder,
b95af8be
VK		 8880 struct intel_link_m_n *m_n,
8881 struct intel_link_m_n *m2_n2)
72419203
DV		 8882{
8883 struct drm_device *dev = crtc->base.dev;
8884 struct drm_i915_private *dev_priv = dev->dev_private;
eb14cb74 8885 enum pipe pipe = crtc->pipe;
72419203 8886
eb14cb74
VS		 8887 if (INTEL_INFO(dev)->gen >= 5) {
8888 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8889 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8890 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8891 & ~TU_SIZE_MASK;
8892 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8893 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8894 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
b95af8be
VK		 8895 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8896 * gen < 8) and if DRRS is supported (to make sure the
8897 * registers are not unnecessarily read).
8898 */
8899 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
6e3c9717 8900 crtc->config->has_drrs) {
b95af8be
VK		 8901 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8902 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8903 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8904 & ~TU_SIZE_MASK;
8905 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8906 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8907 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8908 }
eb14cb74
VS		 8909 } else {
8910 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8911 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8912 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8913 & ~TU_SIZE_MASK;
8914 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8915 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8916 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8917 }
8918}
8919
8920void intel_dp_get_m_n(struct intel_crtc *crtc,
5cec258b 8921 struct intel_crtc_state *pipe_config)
eb14cb74 8922{
681a8504 8923 if (pipe_config->has_pch_encoder)
eb14cb74
VS		 8924 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8925 else
8926 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
b95af8be
VK		 8927 &pipe_config->dp_m_n,
8928 &pipe_config->dp_m2_n2);
eb14cb74 8929}
72419203 8930
eb14cb74 8931static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5cec258b 8932 struct intel_crtc_state *pipe_config)
eb14cb74
VS		 8933{
8934 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
b95af8be 8935 &pipe_config->fdi_m_n, NULL);
72419203
DV		 8936}
8937
bd2e244f 8938static void skylake_get_pfit_config(struct intel_crtc *crtc,
5cec258b 8939 struct intel_crtc_state *pipe_config)
bd2e244f
JB		 8940{
8941 struct drm_device *dev = crtc->base.dev;
8942 struct drm_i915_private *dev_priv = dev->dev_private;
a1b2278e
CK		 8943 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8944 uint32_t ps_ctrl = 0;
8945 int id = -1;
8946 int i;
bd2e244f 8947
a1b2278e
CK		 8948 /* find scaler attached to this pipe */
8949 for (i = 0; i < crtc->num_scalers; i++) {
8950 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
8951 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
8952 id = i;
8953 pipe_config->pch_pfit.enabled = true;
8954 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
8955 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
8956 break;
8957 }
8958 }
bd2e244f 8959
a1b2278e
CK		 8960 scaler_state->scaler_id = id;
8961 if (id >= 0) {
8962 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
8963 } else {
8964 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
bd2e244f
JB		 8965 }
8966}
8967
5724dbd1
DL		 8968static void
8969skylake_get_initial_plane_config(struct intel_crtc *crtc,
8970 struct intel_initial_plane_config *plane_config)
bc8d7dff
DL		 8971{
8972 struct drm_device *dev = crtc->base.dev;
8973 struct drm_i915_private *dev_priv = dev->dev_private;
40f46283 8974 u32 val, base, offset, stride_mult, tiling;
bc8d7dff
DL		 8975 int pipe = crtc->pipe;
8976 int fourcc, pixel_format;
6761dd31 8977 unsigned int aligned_height;
bc8d7dff 8978 struct drm_framebuffer *fb;
1b842c89 8979 struct intel_framebuffer *intel_fb;
bc8d7dff 8980
d9806c9f 8981 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 8982 if (!intel_fb) {
bc8d7dff
DL		 8983 DRM_DEBUG_KMS("failed to alloc fb\n");
8984 return;
8985 }
8986
1b842c89
DL		 8987 fb = &intel_fb->base;
8988
bc8d7dff 8989 val = I915_READ(PLANE_CTL(pipe, 0));
42a7b088
DL		 8990 if (!(val & PLANE_CTL_ENABLE))
8991 goto error;
8992
bc8d7dff
DL		 8993 pixel_format = val & PLANE_CTL_FORMAT_MASK;
8994 fourcc = skl_format_to_fourcc(pixel_format,
8995 val & PLANE_CTL_ORDER_RGBX,
8996 val & PLANE_CTL_ALPHA_MASK);
8997 fb->pixel_format = fourcc;
8998 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8999
40f46283
DL		 9000 tiling = val & PLANE_CTL_TILED_MASK;
9001 switch (tiling) {
9002 case PLANE_CTL_TILED_LINEAR:
9003 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9004 break;
9005 case PLANE_CTL_TILED_X:
9006 plane_config->tiling = I915_TILING_X;
9007 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9008 break;
9009 case PLANE_CTL_TILED_Y:
9010 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9011 break;
9012 case PLANE_CTL_TILED_YF:
9013 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9014 break;
9015 default:
9016 MISSING_CASE(tiling);
9017 goto error;
9018 }
9019
bc8d7dff
DL		 9020 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9021 plane_config->base = base;
9022
9023 offset = I915_READ(PLANE_OFFSET(pipe, 0));
9024
9025 val = I915_READ(PLANE_SIZE(pipe, 0));
9026 fb->height = ((val >> 16) & 0xfff) + 1;
9027 fb->width = ((val >> 0) & 0x1fff) + 1;
9028
9029 val = I915_READ(PLANE_STRIDE(pipe, 0));
40f46283
DL		 9030 stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
9031 fb->pixel_format);
bc8d7dff
DL		 9032 fb->pitches[0] = (val & 0x3ff) * stride_mult;
9033
9034 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 9035 fb->pixel_format,
9036 fb->modifier[0]);
bc8d7dff 9037
f37b5c2b 9038 plane_config->size = fb->pitches[0] * aligned_height;
bc8d7dff
DL		 9039
9040 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9041 pipe_name(pipe), fb->width, fb->height,
9042 fb->bits_per_pixel, base, fb->pitches[0],
9043 plane_config->size);
9044
2d14030b 9045 plane_config->fb = intel_fb;
bc8d7dff
DL		 9046 return;
9047
9048error:
9049 kfree(fb);
9050}
9051
2fa2fe9a 9052static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5cec258b 9053 struct intel_crtc_state *pipe_config)
2fa2fe9a
DV		 9054{
9055 struct drm_device *dev = crtc->base.dev;
9056 struct drm_i915_private *dev_priv = dev->dev_private;
9057 uint32_t tmp;
9058
9059 tmp = I915_READ(PF_CTL(crtc->pipe));
9060
9061 if (tmp & PF_ENABLE) {
fd4daa9c 9062 pipe_config->pch_pfit.enabled = true;
2fa2fe9a
DV		 9063 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9064 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
cb8b2a30
DV		 9065
9066 /* We currently do not free assignements of panel fitters on
9067 * ivb/hsw (since we don't use the higher upscaling modes which
9068 * differentiates them) so just WARN about this case for now. */
9069 if (IS_GEN7(dev)) {
9070 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9071 PF_PIPE_SEL_IVB(crtc->pipe));
9072 }
2fa2fe9a 9073 }
79e53945
JB		 9074}
9075
5724dbd1
DL		 9076static void
9077ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9078 struct intel_initial_plane_config *plane_config)
4c6baa59
JB		 9079{
9080 struct drm_device *dev = crtc->base.dev;
9081 struct drm_i915_private *dev_priv = dev->dev_private;
9082 u32 val, base, offset;
aeee5a49 9083 int pipe = crtc->pipe;
4c6baa59 9084 int fourcc, pixel_format;
6761dd31 9085 unsigned int aligned_height;
b113d5ee 9086 struct drm_framebuffer *fb;
1b842c89 9087 struct intel_framebuffer *intel_fb;
4c6baa59 9088
42a7b088
DL		 9089 val = I915_READ(DSPCNTR(pipe));
9090 if (!(val & DISPLAY_PLANE_ENABLE))
9091 return;
9092
d9806c9f 9093 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 9094 if (!intel_fb) {
4c6baa59
JB		 9095 DRM_DEBUG_KMS("failed to alloc fb\n");
9096 return;
9097 }
9098
1b842c89
DL		 9099 fb = &intel_fb->base;
9100
18c5247e
DV		 9101 if (INTEL_INFO(dev)->gen >= 4) {
9102 if (val & DISPPLANE_TILED) {
49af449b 9103 plane_config->tiling = I915_TILING_X;
18c5247e
DV		 9104 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9105 }
9106 }
4c6baa59
JB		 9107
9108 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
b35d63fa 9109 fourcc = i9xx_format_to_fourcc(pixel_format);
b113d5ee
DL		 9110 fb->pixel_format = fourcc;
9111 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
4c6baa59 9112
aeee5a49 9113 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
4c6baa59 9114 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
aeee5a49 9115 offset = I915_READ(DSPOFFSET(pipe));
4c6baa59 9116 } else {
49af449b 9117 if (plane_config->tiling)
aeee5a49 9118 offset = I915_READ(DSPTILEOFF(pipe));
4c6baa59 9119 else
aeee5a49 9120 offset = I915_READ(DSPLINOFF(pipe));
4c6baa59
JB		 9121 }
9122 plane_config->base = base;
9123
9124 val = I915_READ(PIPESRC(pipe));
b113d5ee
DL		 9125 fb->width = ((val >> 16) & 0xfff) + 1;
9126 fb->height = ((val >> 0) & 0xfff) + 1;
4c6baa59
JB		 9127
9128 val = I915_READ(DSPSTRIDE(pipe));
b113d5ee 9129 fb->pitches[0] = val & 0xffffffc0;
4c6baa59 9130
b113d5ee 9131 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 9132 fb->pixel_format,
9133 fb->modifier[0]);
4c6baa59 9134
f37b5c2b 9135 plane_config->size = fb->pitches[0] * aligned_height;
4c6baa59 9136
2844a921
DL		 9137 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9138 pipe_name(pipe), fb->width, fb->height,
9139 fb->bits_per_pixel, base, fb->pitches[0],
9140 plane_config->size);
b113d5ee 9141
2d14030b 9142 plane_config->fb = intel_fb;
4c6baa59
JB		 9143}
9144
0e8ffe1b 9145static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5cec258b 9146 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 9147{
9148 struct drm_device *dev = crtc->base.dev;
9149 struct drm_i915_private *dev_priv = dev->dev_private;
9150 uint32_t tmp;
9151
f458ebbc
DV		 9152 if (!intel_display_power_is_enabled(dev_priv,
9153 POWER_DOMAIN_PIPE(crtc->pipe)))
930e8c9e
PZ		 9154 return false;
9155
e143a21c 9156 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 9157 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 9158
0e8ffe1b
DV		 9159 tmp = I915_READ(PIPECONF(crtc->pipe));
9160 if (!(tmp & PIPECONF_ENABLE))
9161 return false;
9162
42571aef
VS		 9163 switch (tmp & PIPECONF_BPC_MASK) {
9164 case PIPECONF_6BPC:
9165 pipe_config->pipe_bpp = 18;
9166 break;
9167 case PIPECONF_8BPC:
9168 pipe_config->pipe_bpp = 24;
9169 break;
9170 case PIPECONF_10BPC:
9171 pipe_config->pipe_bpp = 30;
9172 break;
9173 case PIPECONF_12BPC:
9174 pipe_config->pipe_bpp = 36;
9175 break;
9176 default:
9177 break;
9178 }
9179
b5a9fa09
DV		 9180 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9181 pipe_config->limited_color_range = true;
9182
ab9412ba 9183 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
66e985c0
DV		 9184 struct intel_shared_dpll *pll;
9185
88adfff1
DV		 9186 pipe_config->has_pch_encoder = true;
9187
627eb5a3
DV		 9188 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9189 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9190 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 9191
9192 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6c49f241 9193
c0d43d62 9194 if (HAS_PCH_IBX(dev_priv->dev)) {
d94ab068
DV		 9195 pipe_config->shared_dpll =
9196 (enum intel_dpll_id) crtc->pipe;
c0d43d62
DV		 9197 } else {
9198 tmp = I915_READ(PCH_DPLL_SEL);
9199 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9200 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
9201 else
9202 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
9203 }
66e985c0
DV		 9204
9205 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9206
9207 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9208 &pipe_config->dpll_hw_state));
c93f54cf
DV		 9209
9210 tmp = pipe_config->dpll_hw_state.dpll;
9211 pipe_config->pixel_multiplier =
9212 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9213 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
18442d08
VS		 9214
9215 ironlake_pch_clock_get(crtc, pipe_config);
6c49f241
DV		 9216 } else {
9217 pipe_config->pixel_multiplier = 1;
627eb5a3
DV		 9218 }
9219
1bd1bd80
DV		 9220 intel_get_pipe_timings(crtc, pipe_config);
9221
2fa2fe9a
DV		 9222 ironlake_get_pfit_config(crtc, pipe_config);
9223
0e8ffe1b
DV		 9224 return true;
9225}
9226
be256dc7
PZ		 9227static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9228{
9229 struct drm_device *dev = dev_priv->dev;
be256dc7 9230 struct intel_crtc *crtc;
be256dc7 9231
d3fcc808 9232 for_each_intel_crtc(dev, crtc)
e2c719b7 9233 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
be256dc7
PZ		 9234 pipe_name(crtc->pipe));
9235
e2c719b7
RC		 9236 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9237 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9238 I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9239 I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9240 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9241 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
be256dc7 9242 "CPU PWM1 enabled\n");
c5107b87 9243 if (IS_HASWELL(dev))
e2c719b7 9244 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
c5107b87 9245 "CPU PWM2 enabled\n");
e2c719b7 9246 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
be256dc7 9247 "PCH PWM1 enabled\n");
e2c719b7 9248 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
be256dc7 9249 "Utility pin enabled\n");
e2c719b7 9250 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
be256dc7 9251
9926ada1
PZ		 9252 /*
9253 * In theory we can still leave IRQs enabled, as long as only the HPD
9254 * interrupts remain enabled. We used to check for that, but since it's
9255 * gen-specific and since we only disable LCPLL after we fully disable
9256 * the interrupts, the check below should be enough.
9257 */
e2c719b7 9258 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
be256dc7
PZ		 9259}
9260
9ccd5aeb
PZ		 9261static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9262{
9263 struct drm_device *dev = dev_priv->dev;
9264
9265 if (IS_HASWELL(dev))
9266 return I915_READ(D_COMP_HSW);
9267 else
9268 return I915_READ(D_COMP_BDW);
9269}
9270
3c4c9b81
PZ		 9271static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9272{
9273 struct drm_device *dev = dev_priv->dev;
9274
9275 if (IS_HASWELL(dev)) {
9276 mutex_lock(&dev_priv->rps.hw_lock);
9277 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9278 val))
f475dadf 9279 DRM_ERROR("Failed to write to D_COMP\n");
3c4c9b81
PZ		 9280 mutex_unlock(&dev_priv->rps.hw_lock);
9281 } else {
9ccd5aeb
PZ		 9282 I915_WRITE(D_COMP_BDW, val);
9283 POSTING_READ(D_COMP_BDW);
3c4c9b81 9284 }
be256dc7
PZ		 9285}
9286
9287/*
9288 * This function implements pieces of two sequences from BSpec:
9289 * - Sequence for display software to disable LCPLL
9290 * - Sequence for display software to allow package C8+
9291 * The steps implemented here are just the steps that actually touch the LCPLL
9292 * register. Callers should take care of disabling all the display engine
9293 * functions, doing the mode unset, fixing interrupts, etc.
9294 */
6ff58d53
PZ		 9295static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9296 bool switch_to_fclk, bool allow_power_down)
be256dc7
PZ		 9297{
9298 uint32_t val;
9299
9300 assert_can_disable_lcpll(dev_priv);
9301
9302 val = I915_READ(LCPLL_CTL);
9303
9304 if (switch_to_fclk) {
9305 val |= LCPLL_CD_SOURCE_FCLK;
9306 I915_WRITE(LCPLL_CTL, val);
9307
9308 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9309 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9310 DRM_ERROR("Switching to FCLK failed\n");
9311
9312 val = I915_READ(LCPLL_CTL);
9313 }
9314
9315 val |= LCPLL_PLL_DISABLE;
9316 I915_WRITE(LCPLL_CTL, val);
9317 POSTING_READ(LCPLL_CTL);
9318
9319 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9320 DRM_ERROR("LCPLL still locked\n");
9321
9ccd5aeb 9322 val = hsw_read_dcomp(dev_priv);
be256dc7 9323 val |= D_COMP_COMP_DISABLE;
3c4c9b81 9324 hsw_write_dcomp(dev_priv, val);
be256dc7
PZ		 9325 ndelay(100);
9326
9ccd5aeb
PZ		 9327 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9328 1))
be256dc7
PZ		 9329 DRM_ERROR("D_COMP RCOMP still in progress\n");
9330
9331 if (allow_power_down) {
9332 val = I915_READ(LCPLL_CTL);
9333 val |= LCPLL_POWER_DOWN_ALLOW;
9334 I915_WRITE(LCPLL_CTL, val);
9335 POSTING_READ(LCPLL_CTL);
9336 }
9337}
9338
9339/*
9340 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9341 * source.
9342 */
6ff58d53 9343static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
be256dc7
PZ		 9344{
9345 uint32_t val;
9346
9347 val = I915_READ(LCPLL_CTL);
9348
9349 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9350 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9351 return;
9352
a8a8bd54
PZ		 9353 /*
9354 * Make sure we're not on PC8 state before disabling PC8, otherwise
9355 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
a8a8bd54 9356 */
59bad947 9357 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
215733fa 9358
be256dc7
PZ		 9359 if (val & LCPLL_POWER_DOWN_ALLOW) {
9360 val &= ~LCPLL_POWER_DOWN_ALLOW;
9361 I915_WRITE(LCPLL_CTL, val);
35d8f2eb 9362 POSTING_READ(LCPLL_CTL);
be256dc7
PZ		 9363 }
9364
9ccd5aeb 9365 val = hsw_read_dcomp(dev_priv);
be256dc7
PZ		 9366 val |= D_COMP_COMP_FORCE;
9367 val &= ~D_COMP_COMP_DISABLE;
3c4c9b81 9368 hsw_write_dcomp(dev_priv, val);
be256dc7
PZ		 9369
9370 val = I915_READ(LCPLL_CTL);
9371 val &= ~LCPLL_PLL_DISABLE;
9372 I915_WRITE(LCPLL_CTL, val);
9373
9374 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9375 DRM_ERROR("LCPLL not locked yet\n");
9376
9377 if (val & LCPLL_CD_SOURCE_FCLK) {
9378 val = I915_READ(LCPLL_CTL);
9379 val &= ~LCPLL_CD_SOURCE_FCLK;
9380 I915_WRITE(LCPLL_CTL, val);
9381
9382 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9383 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9384 DRM_ERROR("Switching back to LCPLL failed\n");
9385 }
215733fa 9386
59bad947 9387 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
b6283055 9388 intel_update_cdclk(dev_priv->dev);
be256dc7
PZ		 9389}
9390
765dab67
PZ		 9391/*
9392 * Package states C8 and deeper are really deep PC states that can only be
9393 * reached when all the devices on the system allow it, so even if the graphics
9394 * device allows PC8+, it doesn't mean the system will actually get to these
9395 * states. Our driver only allows PC8+ when going into runtime PM.
9396 *
9397 * The requirements for PC8+ are that all the outputs are disabled, the power
9398 * well is disabled and most interrupts are disabled, and these are also
9399 * requirements for runtime PM. When these conditions are met, we manually do
9400 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9401 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9402 * hang the machine.
9403 *
9404 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9405 * the state of some registers, so when we come back from PC8+ we need to
9406 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9407 * need to take care of the registers kept by RC6. Notice that this happens even
9408 * if we don't put the device in PCI D3 state (which is what currently happens
9409 * because of the runtime PM support).
9410 *
9411 * For more, read "Display Sequences for Package C8" on the hardware
9412 * documentation.
9413 */
a14cb6fc 9414void hsw_enable_pc8(struct drm_i915_private *dev_priv)
c67a470b 9415{
c67a470b
PZ		 9416 struct drm_device *dev = dev_priv->dev;
9417 uint32_t val;
9418
c67a470b
PZ		 9419 DRM_DEBUG_KMS("Enabling package C8+\n");
9420
c2699524 9421 if (HAS_PCH_LPT_LP(dev)) {
c67a470b
PZ		 9422 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9423 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9424 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9425 }
9426
9427 lpt_disable_clkout_dp(dev);
c67a470b
PZ		 9428 hsw_disable_lcpll(dev_priv, true, true);
9429}
9430
a14cb6fc 9431void hsw_disable_pc8(struct drm_i915_private *dev_priv)
c67a470b
PZ		 9432{
9433 struct drm_device *dev = dev_priv->dev;
9434 uint32_t val;
9435
c67a470b
PZ		 9436 DRM_DEBUG_KMS("Disabling package C8+\n");
9437
9438 hsw_restore_lcpll(dev_priv);
c67a470b
PZ		 9439 lpt_init_pch_refclk(dev);
9440
c2699524 9441 if (HAS_PCH_LPT_LP(dev)) {
c67a470b
PZ		 9442 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9443 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9444 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9445 }
9446
9447 intel_prepare_ddi(dev);
c67a470b
PZ		 9448}
9449
27c329ed 9450static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state)
f8437dd1 9451{
a821fc46 9452 struct drm_device *dev = old_state->dev;
27c329ed 9453 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
f8437dd1 9454
27c329ed 9455 broxton_set_cdclk(dev, req_cdclk);
f8437dd1
VK		 9456}
9457
b432e5cf 9458/* compute the max rate for new configuration */
27c329ed 9459static int ilk_max_pixel_rate(struct drm_atomic_state *state)
b432e5cf 9460{
b432e5cf 9461 struct intel_crtc *intel_crtc;
27c329ed 9462 struct intel_crtc_state *crtc_state;
b432e5cf 9463 int max_pixel_rate = 0;
b432e5cf 9464
27c329ed
ML		 9465 for_each_intel_crtc(state->dev, intel_crtc) {
9466 int pixel_rate;
9467
9468 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9469 if (IS_ERR(crtc_state))
9470 return PTR_ERR(crtc_state);
9471
9472 if (!crtc_state->base.enable)
b432e5cf
VS		 9473 continue;
9474
27c329ed 9475 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
b432e5cf
VS		 9476
9477 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
27c329ed 9478 if (IS_BROADWELL(state->dev) && crtc_state->ips_enabled)
b432e5cf
VS		 9479 pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9480
9481 max_pixel_rate = max(max_pixel_rate, pixel_rate);
9482 }
9483
9484 return max_pixel_rate;
9485}
9486
9487static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9488{
9489 struct drm_i915_private *dev_priv = dev->dev_private;
9490 uint32_t val, data;
9491 int ret;
9492
9493 if (WARN((I915_READ(LCPLL_CTL) &
9494 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9495 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9496 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9497 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9498 "trying to change cdclk frequency with cdclk not enabled\n"))
9499 return;
9500
9501 mutex_lock(&dev_priv->rps.hw_lock);
9502 ret = sandybridge_pcode_write(dev_priv,
9503 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9504 mutex_unlock(&dev_priv->rps.hw_lock);
9505 if (ret) {
9506 DRM_ERROR("failed to inform pcode about cdclk change\n");
9507 return;
9508 }
9509
9510 val = I915_READ(LCPLL_CTL);
9511 val |= LCPLL_CD_SOURCE_FCLK;
9512 I915_WRITE(LCPLL_CTL, val);
9513
9514 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9515 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9516 DRM_ERROR("Switching to FCLK failed\n");
9517
9518 val = I915_READ(LCPLL_CTL);
9519 val &= ~LCPLL_CLK_FREQ_MASK;
9520
9521 switch (cdclk) {
9522 case 450000:
9523 val |= LCPLL_CLK_FREQ_450;
9524 data = 0;
9525 break;
9526 case 540000:
9527 val |= LCPLL_CLK_FREQ_54O_BDW;
9528 data = 1;
9529 break;
9530 case 337500:
9531 val |= LCPLL_CLK_FREQ_337_5_BDW;
9532 data = 2;
9533 break;
9534 case 675000:
9535 val |= LCPLL_CLK_FREQ_675_BDW;
9536 data = 3;
9537 break;
9538 default:
9539 WARN(1, "invalid cdclk frequency\n");
9540 return;
9541 }
9542
9543 I915_WRITE(LCPLL_CTL, val);
9544
9545 val = I915_READ(LCPLL_CTL);
9546 val &= ~LCPLL_CD_SOURCE_FCLK;
9547 I915_WRITE(LCPLL_CTL, val);
9548
9549 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9550 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9551 DRM_ERROR("Switching back to LCPLL failed\n");
9552
9553 mutex_lock(&dev_priv->rps.hw_lock);
9554 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9555 mutex_unlock(&dev_priv->rps.hw_lock);
9556
9557 intel_update_cdclk(dev);
9558
9559 WARN(cdclk != dev_priv->cdclk_freq,
9560 "cdclk requested %d kHz but got %d kHz\n",
9561 cdclk, dev_priv->cdclk_freq);
9562}
9563
27c329ed 9564static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
b432e5cf 9565{
27c329ed
ML		 9566 struct drm_i915_private *dev_priv = to_i915(state->dev);
9567 int max_pixclk = ilk_max_pixel_rate(state);
b432e5cf
VS		 9568 int cdclk;
9569
9570 /*
9571 * FIXME should also account for plane ratio
9572 * once 64bpp pixel formats are supported.
9573 */
27c329ed 9574 if (max_pixclk > 540000)
b432e5cf 9575 cdclk = 675000;
27c329ed 9576 else if (max_pixclk > 450000)
b432e5cf 9577 cdclk = 540000;
27c329ed 9578 else if (max_pixclk > 337500)
b432e5cf
VS		 9579 cdclk = 450000;
9580 else
9581 cdclk = 337500;
9582
9583 /*
9584 * FIXME move the cdclk caclulation to
9585 * compute_config() so we can fail gracegully.
9586 */
9587 if (cdclk > dev_priv->max_cdclk_freq) {
9588 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9589 cdclk, dev_priv->max_cdclk_freq);
9590 cdclk = dev_priv->max_cdclk_freq;
9591 }
9592
27c329ed 9593 to_intel_atomic_state(state)->cdclk = cdclk;
b432e5cf
VS		 9594
9595 return 0;
9596}
9597
27c329ed 9598static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
b432e5cf 9599{
27c329ed
ML		 9600 struct drm_device *dev = old_state->dev;
9601 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
b432e5cf 9602
27c329ed 9603 broadwell_set_cdclk(dev, req_cdclk);
b432e5cf
VS		 9604}
9605
190f68c5
ACO		 9606static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9607 struct intel_crtc_state *crtc_state)
09b4ddf9 9608{
190f68c5 9609 if (!intel_ddi_pll_select(crtc, crtc_state))
6441ab5f 9610 return -EINVAL;
716c2e55 9611
c7653199 9612 crtc->lowfreq_avail = false;
644cef34 9613
c8f7a0db 9614 return 0;
79e53945
JB		 9615}
9616
3760b59c
S		 9617static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9618 enum port port,
9619 struct intel_crtc_state *pipe_config)
9620{
9621 switch (port) {
9622 case PORT_A:
9623 pipe_config->ddi_pll_sel = SKL_DPLL0;
9624 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9625 break;
9626 case PORT_B:
9627 pipe_config->ddi_pll_sel = SKL_DPLL1;
9628 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9629 break;
9630 case PORT_C:
9631 pipe_config->ddi_pll_sel = SKL_DPLL2;
9632 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9633 break;
9634 default:
9635 DRM_ERROR("Incorrect port type\n");
9636 }
9637}
9638
96b7dfb7
S		 9639static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9640 enum port port,
5cec258b 9641 struct intel_crtc_state *pipe_config)
96b7dfb7 9642{
3148ade7 9643 u32 temp, dpll_ctl1;
96b7dfb7
S		 9644
9645 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9646 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9647
9648 switch (pipe_config->ddi_pll_sel) {
3148ade7
DL		 9649 case SKL_DPLL0:
9650 /*
9651 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9652 * of the shared DPLL framework and thus needs to be read out
9653 * separately
9654 */
9655 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9656 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9657 break;
96b7dfb7
S		 9658 case SKL_DPLL1:
9659 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9660 break;
9661 case SKL_DPLL2:
9662 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9663 break;
9664 case SKL_DPLL3:
9665 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9666 break;
96b7dfb7
S		 9667 }
9668}
9669
7d2c8175
DL		 9670static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9671 enum port port,
5cec258b 9672 struct intel_crtc_state *pipe_config)
7d2c8175
DL		 9673{
9674 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9675
9676 switch (pipe_config->ddi_pll_sel) {
9677 case PORT_CLK_SEL_WRPLL1:
9678 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9679 break;
9680 case PORT_CLK_SEL_WRPLL2:
9681 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9682 break;
9683 }
9684}
9685
26804afd 9686static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
5cec258b 9687 struct intel_crtc_state *pipe_config)
26804afd
DV		 9688{
9689 struct drm_device *dev = crtc->base.dev;
9690 struct drm_i915_private *dev_priv = dev->dev_private;
d452c5b6 9691 struct intel_shared_dpll *pll;
26804afd
DV		 9692 enum port port;
9693 uint32_t tmp;
9694
9695 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9696
9697 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9698
96b7dfb7
S		 9699 if (IS_SKYLAKE(dev))
9700 skylake_get_ddi_pll(dev_priv, port, pipe_config);
3760b59c
S		 9701 else if (IS_BROXTON(dev))
9702 bxt_get_ddi_pll(dev_priv, port, pipe_config);
96b7dfb7
S		 9703 else
9704 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9cd86933 9705
d452c5b6
DV		 9706 if (pipe_config->shared_dpll >= 0) {
9707 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9708
9709 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9710 &pipe_config->dpll_hw_state));
9711 }
9712
26804afd
DV		 9713 /*
9714 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9715 * DDI E. So just check whether this pipe is wired to DDI E and whether
9716 * the PCH transcoder is on.
9717 */
ca370455
DL		 9718 if (INTEL_INFO(dev)->gen < 9 &&
9719 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
26804afd
DV		 9720 pipe_config->has_pch_encoder = true;
9721
9722 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9723 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9724 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9725
9726 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9727 }
9728}
9729
0e8ffe1b 9730static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5cec258b 9731 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 9732{
9733 struct drm_device *dev = crtc->base.dev;
9734 struct drm_i915_private *dev_priv = dev->dev_private;
2fa2fe9a 9735 enum intel_display_power_domain pfit_domain;
0e8ffe1b
DV		 9736 uint32_t tmp;
9737
f458ebbc 9738 if (!intel_display_power_is_enabled(dev_priv,
b5482bd0
ID		 9739 POWER_DOMAIN_PIPE(crtc->pipe)))
9740 return false;
9741
e143a21c 9742 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62
DV		 9743 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9744
eccb140b
DV		 9745 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9746 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9747 enum pipe trans_edp_pipe;
9748 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9749 default:
9750 WARN(1, "unknown pipe linked to edp transcoder\n");
9751 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9752 case TRANS_DDI_EDP_INPUT_A_ON:
9753 trans_edp_pipe = PIPE_A;
9754 break;
9755 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9756 trans_edp_pipe = PIPE_B;
9757 break;
9758 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9759 trans_edp_pipe = PIPE_C;
9760 break;
9761 }
9762
9763 if (trans_edp_pipe == crtc->pipe)
9764 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9765 }
9766
f458ebbc 9767 if (!intel_display_power_is_enabled(dev_priv,
eccb140b 9768 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
2bfce950
PZ		 9769 return false;
9770
eccb140b 9771 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
0e8ffe1b
DV		 9772 if (!(tmp & PIPECONF_ENABLE))
9773 return false;
9774
26804afd 9775 haswell_get_ddi_port_state(crtc, pipe_config);
627eb5a3 9776
1bd1bd80
DV		 9777 intel_get_pipe_timings(crtc, pipe_config);
9778
a1b2278e
CK		 9779 if (INTEL_INFO(dev)->gen >= 9) {
9780 skl_init_scalers(dev, crtc, pipe_config);
9781 }
9782
2fa2fe9a 9783 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
af99ceda
CK		 9784
9785 if (INTEL_INFO(dev)->gen >= 9) {
9786 pipe_config->scaler_state.scaler_id = -1;
9787 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9788 }
9789
bd2e244f 9790 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
1c132b44 9791 if (INTEL_INFO(dev)->gen >= 9)
bd2e244f 9792 skylake_get_pfit_config(crtc, pipe_config);
ff6d9f55 9793 else
1c132b44 9794 ironlake_get_pfit_config(crtc, pipe_config);
bd2e244f 9795 }
88adfff1 9796
e59150dc
JB		 9797 if (IS_HASWELL(dev))
9798 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9799 (I915_READ(IPS_CTL) & IPS_ENABLE);
42db64ef 9800
ebb69c95
CT		 9801 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
9802 pipe_config->pixel_multiplier =
9803 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9804 } else {
9805 pipe_config->pixel_multiplier = 1;
9806 }
6c49f241 9807
0e8ffe1b
DV		 9808 return true;
9809}
9810
560b85bb
CW		 9811static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
9812{
9813 struct drm_device *dev = crtc->dev;
9814 struct drm_i915_private *dev_priv = dev->dev_private;
9815 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
dc41c154 9816 uint32_t cntl = 0, size = 0;
560b85bb 9817
dc41c154 9818 if (base) {
3dd512fb
MR		 9819 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
9820 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
dc41c154
VS		 9821 unsigned int stride = roundup_pow_of_two(width) * 4;
9822
9823 switch (stride) {
9824 default:
9825 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9826 width, stride);
9827 stride = 256;
9828 /* fallthrough */
9829 case 256:
9830 case 512:
9831 case 1024:
9832 case 2048:
9833 break;
4b0e333e
CW		 9834 }
9835
dc41c154
VS		 9836 cntl |= CURSOR_ENABLE |
9837 CURSOR_GAMMA_ENABLE |
9838 CURSOR_FORMAT_ARGB |
9839 CURSOR_STRIDE(stride);
9840
9841 size = (height << 12) | width;
4b0e333e 9842 }
560b85bb 9843
dc41c154
VS		 9844 if (intel_crtc->cursor_cntl != 0 &&
9845 (intel_crtc->cursor_base != base ||
9846 intel_crtc->cursor_size != size ||
9847 intel_crtc->cursor_cntl != cntl)) {
9848 /* On these chipsets we can only modify the base/size/stride
9849 * whilst the cursor is disabled.
9850 */
9851 I915_WRITE(_CURACNTR, 0);
4b0e333e 9852 POSTING_READ(_CURACNTR);
dc41c154 9853 intel_crtc->cursor_cntl = 0;
4b0e333e 9854 }
560b85bb 9855
99d1f387 9856 if (intel_crtc->cursor_base != base) {
9db4a9c7 9857 I915_WRITE(_CURABASE, base);
99d1f387
VS		 9858 intel_crtc->cursor_base = base;
9859 }
4726e0b0 9860
dc41c154
VS		 9861 if (intel_crtc->cursor_size != size) {
9862 I915_WRITE(CURSIZE, size);
9863 intel_crtc->cursor_size = size;
4b0e333e 9864 }
560b85bb 9865
4b0e333e 9866 if (intel_crtc->cursor_cntl != cntl) {
4b0e333e
CW		 9867 I915_WRITE(_CURACNTR, cntl);
9868 POSTING_READ(_CURACNTR);
4b0e333e 9869 intel_crtc->cursor_cntl = cntl;
560b85bb 9870 }
560b85bb
CW		 9871}
9872
560b85bb 9873static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
65a21cd6
JB		 9874{
9875 struct drm_device *dev = crtc->dev;
9876 struct drm_i915_private *dev_priv = dev->dev_private;
9877 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9878 int pipe = intel_crtc->pipe;
4b0e333e
CW		 9879 uint32_t cntl;
9880
9881 cntl = 0;
9882 if (base) {
9883 cntl = MCURSOR_GAMMA_ENABLE;
3dd512fb 9884 switch (intel_crtc->base.cursor->state->crtc_w) {
4726e0b0
SK		 9885 case 64:
9886 cntl |= CURSOR_MODE_64_ARGB_AX;
9887 break;
9888 case 128:
9889 cntl |= CURSOR_MODE_128_ARGB_AX;
9890 break;
9891 case 256:
9892 cntl |= CURSOR_MODE_256_ARGB_AX;
9893 break;
9894 default:
3dd512fb 9895 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
4726e0b0 9896 return;
65a21cd6 9897 }
4b0e333e 9898 cntl |= pipe << 28; /* Connect to correct pipe */
47bf17a7
VS		 9899
9900 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
9901 cntl |= CURSOR_PIPE_CSC_ENABLE;
4b0e333e 9902 }
65a21cd6 9903
8e7d688b 9904 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
4398ad45
VS		 9905 cntl |= CURSOR_ROTATE_180;
9906
4b0e333e
CW		 9907 if (intel_crtc->cursor_cntl != cntl) {
9908 I915_WRITE(CURCNTR(pipe), cntl);
9909 POSTING_READ(CURCNTR(pipe));
9910 intel_crtc->cursor_cntl = cntl;
65a21cd6 9911 }
4b0e333e 9912
65a21cd6 9913 /* and commit changes on next vblank */
5efb3e28
VS		 9914 I915_WRITE(CURBASE(pipe), base);
9915 POSTING_READ(CURBASE(pipe));
99d1f387
VS		 9916
9917 intel_crtc->cursor_base = base;
65a21cd6
JB		 9918}
9919
cda4b7d3 9920/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 9921static void intel_crtc_update_cursor(struct drm_crtc *crtc,
9922 bool on)
cda4b7d3
CW		 9923{
9924 struct drm_device *dev = crtc->dev;
9925 struct drm_i915_private *dev_priv = dev->dev_private;
9926 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9927 int pipe = intel_crtc->pipe;
9b4101be
ML		 9928 struct drm_plane_state *cursor_state = crtc->cursor->state;
9929 int x = cursor_state->crtc_x;
9930 int y = cursor_state->crtc_y;
d6e4db15 9931 u32 base = 0, pos = 0;
cda4b7d3 9932
d6e4db15 9933 if (on)
cda4b7d3 9934 base = intel_crtc->cursor_addr;
cda4b7d3 9935
6e3c9717 9936 if (x >= intel_crtc->config->pipe_src_w)
d6e4db15
VS		 9937 base = 0;
9938
6e3c9717 9939 if (y >= intel_crtc->config->pipe_src_h)
cda4b7d3
CW		 9940 base = 0;
9941
9942 if (x < 0) {
9b4101be 9943 if (x + cursor_state->crtc_w <= 0)
cda4b7d3
CW		 9944 base = 0;
9945
9946 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9947 x = -x;
9948 }
9949 pos |= x << CURSOR_X_SHIFT;
9950
9951 if (y < 0) {
9b4101be 9952 if (y + cursor_state->crtc_h <= 0)
cda4b7d3
CW		 9953 base = 0;
9954
9955 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
9956 y = -y;
9957 }
9958 pos |= y << CURSOR_Y_SHIFT;
9959
4b0e333e 9960 if (base == 0 && intel_crtc->cursor_base == 0)
cda4b7d3
CW		 9961 return;
9962
5efb3e28
VS		 9963 I915_WRITE(CURPOS(pipe), pos);
9964
4398ad45
VS		 9965 /* ILK+ do this automagically */
9966 if (HAS_GMCH_DISPLAY(dev) &&
8e7d688b 9967 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
9b4101be
ML		 9968 base += (cursor_state->crtc_h *
9969 cursor_state->crtc_w - 1) * 4;
4398ad45
VS		 9970 }
9971
8ac54669 9972 if (IS_845G(dev) || IS_I865G(dev))
5efb3e28
VS		 9973 i845_update_cursor(crtc, base);
9974 else
9975 i9xx_update_cursor(crtc, base);
cda4b7d3
CW		 9976}
9977
dc41c154
VS		 9978static bool cursor_size_ok(struct drm_device *dev,
9979 uint32_t width, uint32_t height)
9980{
9981 if (width == 0 || height == 0)
9982 return false;
9983
9984 /*
9985 * 845g/865g are special in that they are only limited by
9986 * the width of their cursors, the height is arbitrary up to
9987 * the precision of the register. Everything else requires
9988 * square cursors, limited to a few power-of-two sizes.
9989 */
9990 if (IS_845G(dev) || IS_I865G(dev)) {
9991 if ((width & 63) != 0)
9992 return false;
9993
9994 if (width > (IS_845G(dev) ? 64 : 512))
9995 return false;
9996
9997 if (height > 1023)
9998 return false;
9999 } else {
10000 switch (width | height) {
10001 case 256:
10002 case 128:
10003 if (IS_GEN2(dev))
10004 return false;
10005 case 64:
10006 break;
10007 default:
10008 return false;
10009 }
10010 }
10011
10012 return true;
10013}
10014
79e53945 10015static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 10016 u16 *blue, uint32_t start, uint32_t size)
79e53945 10017{
7203425a 10018 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 10019 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 10020
7203425a 10021 for (i = start; i < end; i++) {
79e53945
JB		 10022 intel_crtc->lut_r[i] = red[i] >> 8;
10023 intel_crtc->lut_g[i] = green[i] >> 8;
10024 intel_crtc->lut_b[i] = blue[i] >> 8;
10025 }
10026
10027 intel_crtc_load_lut(crtc);
10028}
10029
79e53945
JB		 10030/* VESA 640x480x72Hz mode to set on the pipe */
10031static struct drm_display_mode load_detect_mode = {
10032 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10033 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10034};
10035
a8bb6818
DV		 10036struct drm_framebuffer *
10037__intel_framebuffer_create(struct drm_device *dev,
10038 struct drm_mode_fb_cmd2 *mode_cmd,
10039 struct drm_i915_gem_object *obj)
d2dff872
CW		 10040{
10041 struct intel_framebuffer *intel_fb;
10042 int ret;
10043
10044 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10045 if (!intel_fb) {
6ccb81f2 10046 drm_gem_object_unreference(&obj->base);
d2dff872
CW		 10047 return ERR_PTR(-ENOMEM);
10048 }
10049
10050 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
dd4916c5
DV		 10051 if (ret)
10052 goto err;
d2dff872
CW		 10053
10054 return &intel_fb->base;
dd4916c5 10055err:
6ccb81f2 10056 drm_gem_object_unreference(&obj->base);
dd4916c5
DV		 10057 kfree(intel_fb);
10058
10059 return ERR_PTR(ret);
d2dff872
CW		 10060}
10061
b5ea642a 10062static struct drm_framebuffer *
a8bb6818
DV		 10063intel_framebuffer_create(struct drm_device *dev,
10064 struct drm_mode_fb_cmd2 *mode_cmd,
10065 struct drm_i915_gem_object *obj)
10066{
10067 struct drm_framebuffer *fb;
10068 int ret;
10069
10070 ret = i915_mutex_lock_interruptible(dev);
10071 if (ret)
10072 return ERR_PTR(ret);
10073 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10074 mutex_unlock(&dev->struct_mutex);
10075
10076 return fb;
10077}
10078
d2dff872
CW		 10079static u32
10080intel_framebuffer_pitch_for_width(int width, int bpp)
10081{
10082 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10083 return ALIGN(pitch, 64);
10084}
10085
10086static u32
10087intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10088{
10089 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
1267a26b 10090 return PAGE_ALIGN(pitch * mode->vdisplay);
d2dff872
CW		 10091}
10092
10093static struct drm_framebuffer *
10094intel_framebuffer_create_for_mode(struct drm_device *dev,
10095 struct drm_display_mode *mode,
10096 int depth, int bpp)
10097{
10098 struct drm_i915_gem_object *obj;
0fed39bd 10099 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 10100
10101 obj = i915_gem_alloc_object(dev,
10102 intel_framebuffer_size_for_mode(mode, bpp));
10103 if (obj == NULL)
10104 return ERR_PTR(-ENOMEM);
10105
10106 mode_cmd.width = mode->hdisplay;
10107 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 10108 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10109 bpp);
5ca0c34a 10110 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 10111
10112 return intel_framebuffer_create(dev, &mode_cmd, obj);
10113}
10114
10115static struct drm_framebuffer *
10116mode_fits_in_fbdev(struct drm_device *dev,
10117 struct drm_display_mode *mode)
10118{
0695726e 10119#ifdef CONFIG_DRM_FBDEV_EMULATION
d2dff872
CW		 10120 struct drm_i915_private *dev_priv = dev->dev_private;
10121 struct drm_i915_gem_object *obj;
10122 struct drm_framebuffer *fb;
10123
4c0e5528 10124 if (!dev_priv->fbdev)
d2dff872
CW		 10125 return NULL;
10126
4c0e5528 10127 if (!dev_priv->fbdev->fb)
d2dff872
CW		 10128 return NULL;
10129
4c0e5528
DV		 10130 obj = dev_priv->fbdev->fb->obj;
10131 BUG_ON(!obj);
10132
8bcd4553 10133 fb = &dev_priv->fbdev->fb->base;
01f2c773
VS		 10134 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10135 fb->bits_per_pixel))
d2dff872
CW		 10136 return NULL;
10137
01f2c773 10138 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 10139 return NULL;
10140
10141 return fb;
4520f53a
DV		 10142#else
10143 return NULL;
10144#endif
d2dff872
CW		 10145}
10146
d3a40d1b
ACO		 10147static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10148 struct drm_crtc *crtc,
10149 struct drm_display_mode *mode,
10150 struct drm_framebuffer *fb,
10151 int x, int y)
10152{
10153 struct drm_plane_state *plane_state;
10154 int hdisplay, vdisplay;
10155 int ret;
10156
10157 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10158 if (IS_ERR(plane_state))
10159 return PTR_ERR(plane_state);
10160
10161 if (mode)
10162 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10163 else
10164 hdisplay = vdisplay = 0;
10165
10166 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10167 if (ret)
10168 return ret;
10169 drm_atomic_set_fb_for_plane(plane_state, fb);
10170 plane_state->crtc_x = 0;
10171 plane_state->crtc_y = 0;
10172 plane_state->crtc_w = hdisplay;
10173 plane_state->crtc_h = vdisplay;
10174 plane_state->src_x = x << 16;
10175 plane_state->src_y = y << 16;
10176 plane_state->src_w = hdisplay << 16;
10177 plane_state->src_h = vdisplay << 16;
10178
10179 return 0;
10180}
10181
d2434ab7 10182bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 10183 struct drm_display_mode *mode,
51fd371b
RC		 10184 struct intel_load_detect_pipe *old,
10185 struct drm_modeset_acquire_ctx *ctx)
79e53945
JB		 10186{
10187 struct intel_crtc *intel_crtc;
d2434ab7
DV		 10188 struct intel_encoder *intel_encoder =
10189 intel_attached_encoder(connector);
79e53945 10190 struct drm_crtc *possible_crtc;
4ef69c7a 10191 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 10192 struct drm_crtc *crtc = NULL;
10193 struct drm_device *dev = encoder->dev;
94352cf9 10194 struct drm_framebuffer *fb;
51fd371b 10195 struct drm_mode_config *config = &dev->mode_config;
83a57153 10196 struct drm_atomic_state *state = NULL;
944b0c76 10197 struct drm_connector_state *connector_state;
4be07317 10198 struct intel_crtc_state *crtc_state;
51fd371b 10199 int ret, i = -1;
79e53945 10200
d2dff872 10201 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
c23cc417 10202 connector->base.id, connector->name,
8e329a03 10203 encoder->base.id, encoder->name);
d2dff872 10204
51fd371b
RC		 10205retry:
10206 ret = drm_modeset_lock(&config->connection_mutex, ctx);
10207 if (ret)
ad3c558f 10208 goto fail;
6e9f798d 10209
79e53945
JB		 10210 /*
10211 * Algorithm gets a little messy:
7a5e4805 10212 *
79e53945
JB		 10213 * - if the connector already has an assigned crtc, use it (but make
10214 * sure it's on first)
7a5e4805 10215 *
79e53945
JB		 10216 * - try to find the first unused crtc that can drive this connector,
10217 * and use that if we find one
79e53945
JB		 10218 */
10219
10220 /* See if we already have a CRTC for this connector */
10221 if (encoder->crtc) {
10222 crtc = encoder->crtc;
8261b191 10223
51fd371b 10224 ret = drm_modeset_lock(&crtc->mutex, ctx);
4d02e2de 10225 if (ret)
ad3c558f 10226 goto fail;
4d02e2de 10227 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
51fd371b 10228 if (ret)
ad3c558f 10229 goto fail;
7b24056b 10230
24218aac 10231 old->dpms_mode = connector->dpms;
8261b191
CW		 10232 old->load_detect_temp = false;
10233
10234 /* Make sure the crtc and connector are running */
24218aac
DV		 10235 if (connector->dpms != DRM_MODE_DPMS_ON)
10236 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 10237
7173188d 10238 return true;
79e53945
JB		 10239 }
10240
10241 /* Find an unused one (if possible) */
70e1e0ec 10242 for_each_crtc(dev, possible_crtc) {
79e53945
JB		 10243 i++;
10244 if (!(encoder->possible_crtcs & (1 << i)))
10245 continue;
83d65738 10246 if (possible_crtc->state->enable)
a459249c 10247 continue;
a459249c
VS		 10248
10249 crtc = possible_crtc;
10250 break;
79e53945
JB		 10251 }
10252
10253 /*
10254 * If we didn't find an unused CRTC, don't use any.
10255 */
10256 if (!crtc) {
7173188d 10257 DRM_DEBUG_KMS("no pipe available for load-detect\n");
ad3c558f 10258 goto fail;
79e53945
JB		 10259 }
10260
51fd371b
RC		 10261 ret = drm_modeset_lock(&crtc->mutex, ctx);
10262 if (ret)
ad3c558f 10263 goto fail;
4d02e2de
DV		 10264 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10265 if (ret)
ad3c558f 10266 goto fail;
79e53945
JB		 10267
10268 intel_crtc = to_intel_crtc(crtc);
24218aac 10269 old->dpms_mode = connector->dpms;
8261b191 10270 old->load_detect_temp = true;
d2dff872 10271 old->release_fb = NULL;
79e53945 10272
83a57153
ACO		 10273 state = drm_atomic_state_alloc(dev);
10274 if (!state)
10275 return false;
10276
10277 state->acquire_ctx = ctx;
10278
944b0c76
ACO		 10279 connector_state = drm_atomic_get_connector_state(state, connector);
10280 if (IS_ERR(connector_state)) {
10281 ret = PTR_ERR(connector_state);
10282 goto fail;
10283 }
10284
10285 connector_state->crtc = crtc;
10286 connector_state->best_encoder = &intel_encoder->base;
10287
4be07317
ACO		 10288 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10289 if (IS_ERR(crtc_state)) {
10290 ret = PTR_ERR(crtc_state);
10291 goto fail;
10292 }
10293
49d6fa21 10294 crtc_state->base.active = crtc_state->base.enable = true;
4be07317 10295
6492711d
CW		 10296 if (!mode)
10297 mode = &load_detect_mode;
79e53945 10298
d2dff872
CW		 10299 /* We need a framebuffer large enough to accommodate all accesses
10300 * that the plane may generate whilst we perform load detection.
10301 * We can not rely on the fbcon either being present (we get called
10302 * during its initialisation to detect all boot displays, or it may
10303 * not even exist) or that it is large enough to satisfy the
10304 * requested mode.
10305 */
94352cf9
DV		 10306 fb = mode_fits_in_fbdev(dev, mode);
10307 if (fb == NULL) {
d2dff872 10308 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 10309 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10310 old->release_fb = fb;
d2dff872
CW		 10311 } else
10312 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 10313 if (IS_ERR(fb)) {
d2dff872 10314 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
412b61d8 10315 goto fail;
79e53945 10316 }
79e53945 10317
d3a40d1b
ACO		 10318 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10319 if (ret)
10320 goto fail;
10321
8c7b5ccb
ACO		 10322 drm_mode_copy(&crtc_state->base.mode, mode);
10323
74c090b1 10324 if (drm_atomic_commit(state)) {
6492711d 10325 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 10326 if (old->release_fb)
10327 old->release_fb->funcs->destroy(old->release_fb);
412b61d8 10328 goto fail;
79e53945 10329 }
9128b040 10330 crtc->primary->crtc = crtc;
7173188d 10331
79e53945 10332 /* let the connector get through one full cycle before testing */
9d0498a2 10333 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 10334 return true;
412b61d8 10335
ad3c558f 10336fail:
e5d958ef
ACO		 10337 drm_atomic_state_free(state);
10338 state = NULL;
83a57153 10339
51fd371b
RC		 10340 if (ret == -EDEADLK) {
10341 drm_modeset_backoff(ctx);
10342 goto retry;
10343 }
10344
412b61d8 10345 return false;
79e53945
JB		 10346}
10347
d2434ab7 10348void intel_release_load_detect_pipe(struct drm_connector *connector,
49172fee
ACO		 10349 struct intel_load_detect_pipe *old,
10350 struct drm_modeset_acquire_ctx *ctx)
79e53945 10351{
83a57153 10352 struct drm_device *dev = connector->dev;
d2434ab7
DV		 10353 struct intel_encoder *intel_encoder =
10354 intel_attached_encoder(connector);
4ef69c7a 10355 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 10356 struct drm_crtc *crtc = encoder->crtc;
412b61d8 10357 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83a57153 10358 struct drm_atomic_state *state;
944b0c76 10359 struct drm_connector_state *connector_state;
4be07317 10360 struct intel_crtc_state *crtc_state;
d3a40d1b 10361 int ret;
79e53945 10362
d2dff872 10363 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
c23cc417 10364 connector->base.id, connector->name,
8e329a03 10365 encoder->base.id, encoder->name);
d2dff872 10366
8261b191 10367 if (old->load_detect_temp) {
83a57153 10368 state = drm_atomic_state_alloc(dev);
944b0c76
ACO		 10369 if (!state)
10370 goto fail;
83a57153
ACO		 10371
10372 state->acquire_ctx = ctx;
10373
944b0c76
ACO		 10374 connector_state = drm_atomic_get_connector_state(state, connector);
10375 if (IS_ERR(connector_state))
10376 goto fail;
10377
4be07317
ACO		 10378 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10379 if (IS_ERR(crtc_state))
10380 goto fail;
10381
944b0c76
ACO		 10382 connector_state->best_encoder = NULL;
10383 connector_state->crtc = NULL;
10384
49d6fa21 10385 crtc_state->base.enable = crtc_state->base.active = false;
4be07317 10386
d3a40d1b
ACO		 10387 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
10388 0, 0);
10389 if (ret)
10390 goto fail;
10391
74c090b1 10392 ret = drm_atomic_commit(state);
2bfb4627
ACO		 10393 if (ret)
10394 goto fail;
d2dff872 10395
36206361
DV		 10396 if (old->release_fb) {
10397 drm_framebuffer_unregister_private(old->release_fb);
10398 drm_framebuffer_unreference(old->release_fb);
10399 }
d2dff872 10400
0622a53c 10401 return;
79e53945
JB		 10402 }
10403
c751ce4f 10404 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 10405 if (old->dpms_mode != DRM_MODE_DPMS_ON)
10406 connector->funcs->dpms(connector, old->dpms_mode);
944b0c76
ACO		 10407
10408 return;
10409fail:
10410 DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
10411 drm_atomic_state_free(state);
79e53945
JB		 10412}
10413
da4a1efa 10414static int i9xx_pll_refclk(struct drm_device *dev,
5cec258b 10415 const struct intel_crtc_state *pipe_config)
da4a1efa
VS		 10416{
10417 struct drm_i915_private *dev_priv = dev->dev_private;
10418 u32 dpll = pipe_config->dpll_hw_state.dpll;
10419
10420 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
e91e941b 10421 return dev_priv->vbt.lvds_ssc_freq;
da4a1efa
VS		 10422 else if (HAS_PCH_SPLIT(dev))
10423 return 120000;
10424 else if (!IS_GEN2(dev))
10425 return 96000;
10426 else
10427 return 48000;
10428}
10429
79e53945 10430/* Returns the clock of the currently programmed mode of the given pipe. */
f1f644dc 10431static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 10432 struct intel_crtc_state *pipe_config)
79e53945 10433{
f1f644dc 10434 struct drm_device *dev = crtc->base.dev;
79e53945 10435 struct drm_i915_private *dev_priv = dev->dev_private;
f1f644dc 10436 int pipe = pipe_config->cpu_transcoder;
293623f7 10437 u32 dpll = pipe_config->dpll_hw_state.dpll;
79e53945
JB		 10438 u32 fp;
10439 intel_clock_t clock;
dccbea3b 10440 int port_clock;
da4a1efa 10441 int refclk = i9xx_pll_refclk(dev, pipe_config);
79e53945
JB		 10442
10443 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
293623f7 10444 fp = pipe_config->dpll_hw_state.fp0;
79e53945 10445 else
293623f7 10446 fp = pipe_config->dpll_hw_state.fp1;
79e53945
JB		 10447
10448 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 10449 if (IS_PINEVIEW(dev)) {
10450 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10451 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 10452 } else {
10453 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10454 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10455 }
10456
a6c45cf0 10457 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 10458 if (IS_PINEVIEW(dev))
10459 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10460 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 10461 else
10462 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 10463 DPLL_FPA01_P1_POST_DIV_SHIFT);
10464
10465 switch (dpll & DPLL_MODE_MASK) {
10466 case DPLLB_MODE_DAC_SERIAL:
10467 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10468 5 : 10;
10469 break;
10470 case DPLLB_MODE_LVDS:
10471 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10472 7 : 14;
10473 break;
10474 default:
28c97730 10475 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945 10476 "mode\n", (int)(dpll & DPLL_MODE_MASK));
f1f644dc 10477 return;
79e53945
JB		 10478 }
10479
ac58c3f0 10480 if (IS_PINEVIEW(dev))
dccbea3b 10481 port_clock = pnv_calc_dpll_params(refclk, &clock);
ac58c3f0 10482 else
dccbea3b 10483 port_clock = i9xx_calc_dpll_params(refclk, &clock);
79e53945 10484 } else {
0fb58223 10485 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
b1c560d1 10486 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
79e53945
JB		 10487
10488 if (is_lvds) {
10489 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10490 DPLL_FPA01_P1_POST_DIV_SHIFT);
b1c560d1
VS		 10491
10492 if (lvds & LVDS_CLKB_POWER_UP)
10493 clock.p2 = 7;
10494 else
10495 clock.p2 = 14;
79e53945
JB		 10496 } else {
10497 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10498 clock.p1 = 2;
10499 else {
10500 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10501 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10502 }
10503 if (dpll & PLL_P2_DIVIDE_BY_4)
10504 clock.p2 = 4;
10505 else
10506 clock.p2 = 2;
79e53945 10507 }
da4a1efa 10508
dccbea3b 10509 port_clock = i9xx_calc_dpll_params(refclk, &clock);
79e53945
JB		 10510 }
10511
18442d08
VS		 10512 /*
10513 * This value includes pixel_multiplier. We will use
241bfc38 10514 * port_clock to compute adjusted_mode.crtc_clock in the
18442d08
VS		 10515 * encoder's get_config() function.
10516 */
dccbea3b 10517 pipe_config->port_clock = port_clock;
f1f644dc
JB		 10518}
10519
6878da05
VS		 10520int intel_dotclock_calculate(int link_freq,
10521 const struct intel_link_m_n *m_n)
f1f644dc 10522{
f1f644dc
JB		 10523 /*
10524 * The calculation for the data clock is:
1041a02f 10525 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
f1f644dc 10526 * But we want to avoid losing precison if possible, so:
1041a02f 10527 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
f1f644dc
JB		 10528 *
10529 * and the link clock is simpler:
1041a02f 10530 * link_clock = (m * link_clock) / n
f1f644dc
JB		 10531 */
10532
6878da05
VS		 10533 if (!m_n->link_n)
10534 return 0;
f1f644dc 10535
6878da05
VS		 10536 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10537}
f1f644dc 10538
18442d08 10539static void ironlake_pch_clock_get(struct intel_crtc *crtc,
5cec258b 10540 struct intel_crtc_state *pipe_config)
6878da05
VS		 10541{
10542 struct drm_device *dev = crtc->base.dev;
79e53945 10543
18442d08
VS		 10544 /* read out port_clock from the DPLL */
10545 i9xx_crtc_clock_get(crtc, pipe_config);
f1f644dc 10546
f1f644dc 10547 /*
18442d08 10548 * This value does not include pixel_multiplier.
241bfc38 10549 * We will check that port_clock and adjusted_mode.crtc_clock
18442d08
VS		 10550 * agree once we know their relationship in the encoder's
10551 * get_config() function.
79e53945 10552 */
2d112de7 10553 pipe_config->base.adjusted_mode.crtc_clock =
18442d08
VS		 10554 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10555 &pipe_config->fdi_m_n);
79e53945
JB		 10556}
10557
10558/** Returns the currently programmed mode of the given pipe. */
10559struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10560 struct drm_crtc *crtc)
10561{
548f245b 10562 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 10563 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 10564 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
79e53945 10565 struct drm_display_mode *mode;
5cec258b 10566 struct intel_crtc_state pipe_config;
fe2b8f9d
PZ		 10567 int htot = I915_READ(HTOTAL(cpu_transcoder));
10568 int hsync = I915_READ(HSYNC(cpu_transcoder));
10569 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10570 int vsync = I915_READ(VSYNC(cpu_transcoder));
293623f7 10571 enum pipe pipe = intel_crtc->pipe;
79e53945
JB		 10572
10573 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10574 if (!mode)
10575 return NULL;
10576
f1f644dc
JB		 10577 /*
10578 * Construct a pipe_config sufficient for getting the clock info
10579 * back out of crtc_clock_get.
10580 *
10581 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10582 * to use a real value here instead.
10583 */
293623f7 10584 pipe_config.cpu_transcoder = (enum transcoder) pipe;
f1f644dc 10585 pipe_config.pixel_multiplier = 1;
293623f7
VS		 10586 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10587 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10588 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
f1f644dc
JB		 10589 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10590
773ae034 10591 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
79e53945
JB		 10592 mode->hdisplay = (htot & 0xffff) + 1;
10593 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10594 mode->hsync_start = (hsync & 0xffff) + 1;
10595 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10596 mode->vdisplay = (vtot & 0xffff) + 1;
10597 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10598 mode->vsync_start = (vsync & 0xffff) + 1;
10599 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10600
10601 drm_mode_set_name(mode);
79e53945
JB		 10602
10603 return mode;
10604}
10605
f047e395
CW		 10606void intel_mark_busy(struct drm_device *dev)
10607{
c67a470b
PZ		 10608 struct drm_i915_private *dev_priv = dev->dev_private;
10609
f62a0076
CW		 10610 if (dev_priv->mm.busy)
10611 return;
10612
43694d69 10613 intel_runtime_pm_get(dev_priv);
c67a470b 10614 i915_update_gfx_val(dev_priv);
43cf3bf0
CW		 10615 if (INTEL_INFO(dev)->gen >= 6)
10616 gen6_rps_busy(dev_priv);
f62a0076 10617 dev_priv->mm.busy = true;
f047e395
CW		 10618}
10619
10620void intel_mark_idle(struct drm_device *dev)
652c393a 10621{
c67a470b 10622 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 10623
f62a0076
CW		 10624 if (!dev_priv->mm.busy)
10625 return;
10626
10627 dev_priv->mm.busy = false;
10628
3d13ef2e 10629 if (INTEL_INFO(dev)->gen >= 6)
b29c19b6 10630 gen6_rps_idle(dev->dev_private);
bb4cdd53 10631
43694d69 10632 intel_runtime_pm_put(dev_priv);
652c393a
JB		 10633}
10634
79e53945
JB		 10635static void intel_crtc_destroy(struct drm_crtc *crtc)
10636{
10637 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 10638 struct drm_device *dev = crtc->dev;
10639 struct intel_unpin_work *work;
67e77c5a 10640
5e2d7afc 10641 spin_lock_irq(&dev->event_lock);
67e77c5a
DV		 10642 work = intel_crtc->unpin_work;
10643 intel_crtc->unpin_work = NULL;
5e2d7afc 10644 spin_unlock_irq(&dev->event_lock);
67e77c5a
DV		 10645
10646 if (work) {
10647 cancel_work_sync(&work->work);
10648 kfree(work);
10649 }
79e53945
JB		 10650
10651 drm_crtc_cleanup(crtc);
67e77c5a 10652
79e53945
JB		 10653 kfree(intel_crtc);
10654}
10655
6b95a207
KH		 10656static void intel_unpin_work_fn(struct work_struct *__work)
10657{
10658 struct intel_unpin_work *work =
10659 container_of(__work, struct intel_unpin_work, work);
a9ff8714
VS		 10660 struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10661 struct drm_device *dev = crtc->base.dev;
10662 struct drm_plane *primary = crtc->base.primary;
6b95a207 10663
b4a98e57 10664 mutex_lock(&dev->struct_mutex);
a9ff8714 10665 intel_unpin_fb_obj(work->old_fb, primary->state);
05394f39 10666 drm_gem_object_unreference(&work->pending_flip_obj->base);
d9e86c0e 10667
f06cc1b9 10668 if (work->flip_queued_req)
146d84f0 10669 i915_gem_request_assign(&work->flip_queued_req, NULL);
b4a98e57
CW		 10670 mutex_unlock(&dev->struct_mutex);
10671
a9ff8714 10672 intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit);
89ed88ba 10673 drm_framebuffer_unreference(work->old_fb);
f99d7069 10674
a9ff8714
VS		 10675 BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
10676 atomic_dec(&crtc->unpin_work_count);
b4a98e57 10677
6b95a207
KH		 10678 kfree(work);
10679}
10680
1afe3e9d 10681static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 10682 struct drm_crtc *crtc)
6b95a207 10683{
6b95a207
KH		 10684 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10685 struct intel_unpin_work *work;
6b95a207
KH		 10686 unsigned long flags;
10687
10688 /* Ignore early vblank irqs */
10689 if (intel_crtc == NULL)
10690 return;
10691
f326038a
DV		 10692 /*
10693 * This is called both by irq handlers and the reset code (to complete
10694 * lost pageflips) so needs the full irqsave spinlocks.
10695 */
6b95a207
KH		 10696 spin_lock_irqsave(&dev->event_lock, flags);
10697 work = intel_crtc->unpin_work;
e7d841ca
CW		 10698
10699 /* Ensure we don't miss a work->pending update ... */
10700 smp_rmb();
10701
10702 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 10703 spin_unlock_irqrestore(&dev->event_lock, flags);
10704 return;
10705 }
10706
d6bbafa1 10707 page_flip_completed(intel_crtc);
0af7e4df 10708
6b95a207 10709 spin_unlock_irqrestore(&dev->event_lock, flags);
6b95a207
KH		 10710}
10711
1afe3e9d
JB		 10712void intel_finish_page_flip(struct drm_device *dev, int pipe)
10713{
fbee40df 10714 struct drm_i915_private *dev_priv = dev->dev_private;
1afe3e9d
JB		 10715 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10716
49b14a5c 10717 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 10718}
10719
10720void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10721{
fbee40df 10722 struct drm_i915_private *dev_priv = dev->dev_private;
1afe3e9d
JB		 10723 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10724
49b14a5c 10725 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 10726}
10727
75f7f3ec
VS		 10728/* Is 'a' after or equal to 'b'? */
10729static bool g4x_flip_count_after_eq(u32 a, u32 b)
10730{
10731 return !((a - b) & 0x80000000);
10732}
10733
10734static bool page_flip_finished(struct intel_crtc *crtc)
10735{
10736 struct drm_device *dev = crtc->base.dev;
10737 struct drm_i915_private *dev_priv = dev->dev_private;
10738
bdfa7542
VS		 10739 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10740 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10741 return true;
10742
75f7f3ec
VS		 10743 /*
10744 * The relevant registers doen't exist on pre-ctg.
10745 * As the flip done interrupt doesn't trigger for mmio
10746 * flips on gmch platforms, a flip count check isn't
10747 * really needed there. But since ctg has the registers,
10748 * include it in the check anyway.
10749 */
10750 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10751 return true;
10752
10753 /*
10754 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10755 * used the same base address. In that case the mmio flip might
10756 * have completed, but the CS hasn't even executed the flip yet.
10757 *
10758 * A flip count check isn't enough as the CS might have updated
10759 * the base address just after start of vblank, but before we
10760 * managed to process the interrupt. This means we'd complete the
10761 * CS flip too soon.
10762 *
10763 * Combining both checks should get us a good enough result. It may
10764 * still happen that the CS flip has been executed, but has not
10765 * yet actually completed. But in case the base address is the same
10766 * anyway, we don't really care.
10767 */
10768 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10769 crtc->unpin_work->gtt_offset &&
10770 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
10771 crtc->unpin_work->flip_count);
10772}
10773
6b95a207
KH		 10774void intel_prepare_page_flip(struct drm_device *dev, int plane)
10775{
fbee40df 10776 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 10777 struct intel_crtc *intel_crtc =
10778 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10779 unsigned long flags;
10780
f326038a
DV		 10781
10782 /*
10783 * This is called both by irq handlers and the reset code (to complete
10784 * lost pageflips) so needs the full irqsave spinlocks.
10785 *
10786 * NB: An MMIO update of the plane base pointer will also
e7d841ca
CW		 10787 * generate a page-flip completion irq, i.e. every modeset
10788 * is also accompanied by a spurious intel_prepare_page_flip().
10789 */
6b95a207 10790 spin_lock_irqsave(&dev->event_lock, flags);
75f7f3ec 10791 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
e7d841ca 10792 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 10793 spin_unlock_irqrestore(&dev->event_lock, flags);
10794}
10795
eba905b2 10796static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
e7d841ca
CW		 10797{
10798 /* Ensure that the work item is consistent when activating it ... */
10799 smp_wmb();
10800 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
10801 /* and that it is marked active as soon as the irq could fire. */
10802 smp_wmb();
10803}
10804
8c9f3aaf
JB		 10805static int intel_gen2_queue_flip(struct drm_device *dev,
10806 struct drm_crtc *crtc,
10807 struct drm_framebuffer *fb,
ed8d1975 10808 struct drm_i915_gem_object *obj,
6258fbe2 10809 struct drm_i915_gem_request *req,
ed8d1975 10810 uint32_t flags)
8c9f3aaf 10811{
6258fbe2 10812 struct intel_engine_cs *ring = req->ring;
8c9f3aaf 10813 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf
JB		 10814 u32 flip_mask;
10815 int ret;
10816
5fb9de1a 10817 ret = intel_ring_begin(req, 6);
8c9f3aaf 10818 if (ret)
4fa62c89 10819 return ret;
8c9f3aaf
JB		 10820
10821 /* Can't queue multiple flips, so wait for the previous
10822 * one to finish before executing the next.
10823 */
10824 if (intel_crtc->plane)
10825 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10826 else
10827 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 10828 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10829 intel_ring_emit(ring, MI_NOOP);
10830 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10831 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10832 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 10833 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
6d90c952 10834 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 10835
10836 intel_mark_page_flip_active(intel_crtc);
83d4092b 10837 return 0;
8c9f3aaf
JB		 10838}
10839
10840static int intel_gen3_queue_flip(struct drm_device *dev,
10841 struct drm_crtc *crtc,
10842 struct drm_framebuffer *fb,
ed8d1975 10843 struct drm_i915_gem_object *obj,
6258fbe2 10844 struct drm_i915_gem_request *req,
ed8d1975 10845 uint32_t flags)
8c9f3aaf 10846{
6258fbe2 10847 struct intel_engine_cs *ring = req->ring;
8c9f3aaf 10848 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf
JB		 10849 u32 flip_mask;
10850 int ret;
10851
5fb9de1a 10852 ret = intel_ring_begin(req, 6);
8c9f3aaf 10853 if (ret)
4fa62c89 10854 return ret;
8c9f3aaf
JB		 10855
10856 if (intel_crtc->plane)
10857 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10858 else
10859 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 10860 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10861 intel_ring_emit(ring, MI_NOOP);
10862 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
10863 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10864 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 10865 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
6d90c952
DV		 10866 intel_ring_emit(ring, MI_NOOP);
10867
e7d841ca 10868 intel_mark_page_flip_active(intel_crtc);
83d4092b 10869 return 0;
8c9f3aaf
JB		 10870}
10871
10872static int intel_gen4_queue_flip(struct drm_device *dev,
10873 struct drm_crtc *crtc,
10874 struct drm_framebuffer *fb,
ed8d1975 10875 struct drm_i915_gem_object *obj,
6258fbe2 10876 struct drm_i915_gem_request *req,
ed8d1975 10877 uint32_t flags)
8c9f3aaf 10878{
6258fbe2 10879 struct intel_engine_cs *ring = req->ring;
8c9f3aaf
JB		 10880 struct drm_i915_private *dev_priv = dev->dev_private;
10881 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10882 uint32_t pf, pipesrc;
10883 int ret;
10884
5fb9de1a 10885 ret = intel_ring_begin(req, 4);
8c9f3aaf 10886 if (ret)
4fa62c89 10887 return ret;
8c9f3aaf
JB		 10888
10889 /* i965+ uses the linear or tiled offsets from the
10890 * Display Registers (which do not change across a page-flip)
10891 * so we need only reprogram the base address.
10892 */
6d90c952
DV		 10893 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10894 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10895 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 10896 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
c2c75131 10897 obj->tiling_mode);
8c9f3aaf
JB		 10898
10899 /* XXX Enabling the panel-fitter across page-flip is so far
10900 * untested on non-native modes, so ignore it for now.
10901 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
10902 */
10903 pf = 0;
10904 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 10905 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 10906
10907 intel_mark_page_flip_active(intel_crtc);
83d4092b 10908 return 0;
8c9f3aaf
JB		 10909}
10910
10911static int intel_gen6_queue_flip(struct drm_device *dev,
10912 struct drm_crtc *crtc,
10913 struct drm_framebuffer *fb,
ed8d1975 10914 struct drm_i915_gem_object *obj,
6258fbe2 10915 struct drm_i915_gem_request *req,
ed8d1975 10916 uint32_t flags)
8c9f3aaf 10917{
6258fbe2 10918 struct intel_engine_cs *ring = req->ring;
8c9f3aaf
JB		 10919 struct drm_i915_private *dev_priv = dev->dev_private;
10920 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10921 uint32_t pf, pipesrc;
10922 int ret;
10923
5fb9de1a 10924 ret = intel_ring_begin(req, 4);
8c9f3aaf 10925 if (ret)
4fa62c89 10926 return ret;
8c9f3aaf 10927
6d90c952
DV		 10928 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10929 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10930 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
75f7f3ec 10931 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
8c9f3aaf 10932
dc257cf1
DV		 10933 /* Contrary to the suggestions in the documentation,
10934 * "Enable Panel Fitter" does not seem to be required when page
10935 * flipping with a non-native mode, and worse causes a normal
10936 * modeset to fail.
10937 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
10938 */
10939 pf = 0;
8c9f3aaf 10940 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 10941 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 10942
10943 intel_mark_page_flip_active(intel_crtc);
83d4092b 10944 return 0;
8c9f3aaf
JB		 10945}
10946
7c9017e5
JB		 10947static int intel_gen7_queue_flip(struct drm_device *dev,
10948 struct drm_crtc *crtc,
10949 struct drm_framebuffer *fb,
ed8d1975 10950 struct drm_i915_gem_object *obj,
6258fbe2 10951 struct drm_i915_gem_request *req,
ed8d1975 10952 uint32_t flags)
7c9017e5 10953{
6258fbe2 10954 struct intel_engine_cs *ring = req->ring;
7c9017e5 10955 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cb05d8de 10956 uint32_t plane_bit = 0;
ffe74d75
CW		 10957 int len, ret;
10958
eba905b2 10959 switch (intel_crtc->plane) {
cb05d8de
DV		 10960 case PLANE_A:
10961 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
10962 break;
10963 case PLANE_B:
10964 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
10965 break;
10966 case PLANE_C:
10967 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
10968 break;
10969 default:
10970 WARN_ONCE(1, "unknown plane in flip command\n");
4fa62c89 10971 return -ENODEV;
cb05d8de
DV		 10972 }
10973
ffe74d75 10974 len = 4;
f476828a 10975 if (ring->id == RCS) {
ffe74d75 10976 len += 6;
f476828a
DL		 10977 /*
10978 * On Gen 8, SRM is now taking an extra dword to accommodate
10979 * 48bits addresses, and we need a NOOP for the batch size to
10980 * stay even.
10981 */
10982 if (IS_GEN8(dev))
10983 len += 2;
10984 }
ffe74d75 10985
f66fab8e
VS		 10986 /*
10987 * BSpec MI_DISPLAY_FLIP for IVB:
10988 * "The full packet must be contained within the same cache line."
10989 *
10990 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
10991 * cacheline, if we ever start emitting more commands before
10992 * the MI_DISPLAY_FLIP we may need to first emit everything else,
10993 * then do the cacheline alignment, and finally emit the
10994 * MI_DISPLAY_FLIP.
10995 */
bba09b12 10996 ret = intel_ring_cacheline_align(req);
f66fab8e 10997 if (ret)
4fa62c89 10998 return ret;
f66fab8e 10999
5fb9de1a 11000 ret = intel_ring_begin(req, len);
7c9017e5 11001 if (ret)
4fa62c89 11002 return ret;
7c9017e5 11003
ffe74d75
CW		 11004 /* Unmask the flip-done completion message. Note that the bspec says that
11005 * we should do this for both the BCS and RCS, and that we must not unmask
11006 * more than one flip event at any time (or ensure that one flip message
11007 * can be sent by waiting for flip-done prior to queueing new flips).
11008 * Experimentation says that BCS works despite DERRMR masking all
11009 * flip-done completion events and that unmasking all planes at once
11010 * for the RCS also doesn't appear to drop events. Setting the DERRMR
11011 * to zero does lead to lockups within MI_DISPLAY_FLIP.
11012 */
11013 if (ring->id == RCS) {
11014 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11015 intel_ring_emit(ring, DERRMR);
11016 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11017 DERRMR_PIPEB_PRI_FLIP_DONE |
11018 DERRMR_PIPEC_PRI_FLIP_DONE));
f476828a 11019 if (IS_GEN8(dev))
f1afe24f 11020 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 |
f476828a
DL		 11021 MI_SRM_LRM_GLOBAL_GTT);
11022 else
f1afe24f 11023 intel_ring_emit(ring, MI_STORE_REGISTER_MEM |
f476828a 11024 MI_SRM_LRM_GLOBAL_GTT);
ffe74d75
CW		 11025 intel_ring_emit(ring, DERRMR);
11026 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
f476828a
DL		 11027 if (IS_GEN8(dev)) {
11028 intel_ring_emit(ring, 0);
11029 intel_ring_emit(ring, MI_NOOP);
11030 }
ffe74d75
CW		 11031 }
11032
cb05d8de 11033 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 11034 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
75f7f3ec 11035 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
7c9017e5 11036 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 11037
11038 intel_mark_page_flip_active(intel_crtc);
83d4092b 11039 return 0;
7c9017e5
JB		 11040}
11041
84c33a64
SG		 11042static bool use_mmio_flip(struct intel_engine_cs *ring,
11043 struct drm_i915_gem_object *obj)
11044{
11045 /*
11046 * This is not being used for older platforms, because
11047 * non-availability of flip done interrupt forces us to use
11048 * CS flips. Older platforms derive flip done using some clever
11049 * tricks involving the flip_pending status bits and vblank irqs.
11050 * So using MMIO flips there would disrupt this mechanism.
11051 */
11052
8e09bf83
CW		 11053 if (ring == NULL)
11054 return true;
11055
84c33a64
SG		 11056 if (INTEL_INFO(ring->dev)->gen < 5)
11057 return false;
11058
11059 if (i915.use_mmio_flip < 0)
11060 return false;
11061 else if (i915.use_mmio_flip > 0)
11062 return true;
14bf993e
OM		 11063 else if (i915.enable_execlists)
11064 return true;
84c33a64 11065 else
b4716185 11066 return ring != i915_gem_request_get_ring(obj->last_write_req);
84c33a64
SG		 11067}
11068
ff944564
DL		 11069static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
11070{
11071 struct drm_device *dev = intel_crtc->base.dev;
11072 struct drm_i915_private *dev_priv = dev->dev_private;
11073 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
ff944564
DL		 11074 const enum pipe pipe = intel_crtc->pipe;
11075 u32 ctl, stride;
11076
11077 ctl = I915_READ(PLANE_CTL(pipe, 0));
11078 ctl &= ~PLANE_CTL_TILED_MASK;
2ebef630
TU		 11079 switch (fb->modifier[0]) {
11080 case DRM_FORMAT_MOD_NONE:
11081 break;
11082 case I915_FORMAT_MOD_X_TILED:
ff944564 11083 ctl |= PLANE_CTL_TILED_X;
2ebef630
TU		 11084 break;
11085 case I915_FORMAT_MOD_Y_TILED:
11086 ctl |= PLANE_CTL_TILED_Y;
11087 break;
11088 case I915_FORMAT_MOD_Yf_TILED:
11089 ctl |= PLANE_CTL_TILED_YF;
11090 break;
11091 default:
11092 MISSING_CASE(fb->modifier[0]);
11093 }
ff944564
DL		 11094
11095 /*
11096 * The stride is either expressed as a multiple of 64 bytes chunks for
11097 * linear buffers or in number of tiles for tiled buffers.
11098 */
2ebef630
TU		 11099 stride = fb->pitches[0] /
11100 intel_fb_stride_alignment(dev, fb->modifier[0],
11101 fb->pixel_format);
ff944564
DL		 11102
11103 /*
11104 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11105 * PLANE_SURF updates, the update is then guaranteed to be atomic.
11106 */
11107 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11108 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11109
11110 I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
11111 POSTING_READ(PLANE_SURF(pipe, 0));
11112}
11113
11114static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
84c33a64
SG		 11115{
11116 struct drm_device *dev = intel_crtc->base.dev;
11117 struct drm_i915_private *dev_priv = dev->dev_private;
11118 struct intel_framebuffer *intel_fb =
11119 to_intel_framebuffer(intel_crtc->base.primary->fb);
11120 struct drm_i915_gem_object *obj = intel_fb->obj;
11121 u32 dspcntr;
11122 u32 reg;
11123
84c33a64
SG		 11124 reg = DSPCNTR(intel_crtc->plane);
11125 dspcntr = I915_READ(reg);
11126
c5d97472
DL		 11127 if (obj->tiling_mode != I915_TILING_NONE)
11128 dspcntr |= DISPPLANE_TILED;
11129 else
11130 dspcntr &= ~DISPPLANE_TILED;
11131
84c33a64
SG		 11132 I915_WRITE(reg, dspcntr);
11133
11134 I915_WRITE(DSPSURF(intel_crtc->plane),
11135 intel_crtc->unpin_work->gtt_offset);
11136 POSTING_READ(DSPSURF(intel_crtc->plane));
84c33a64 11137
ff944564
DL		 11138}
11139
11140/*
11141 * XXX: This is the temporary way to update the plane registers until we get
11142 * around to using the usual plane update functions for MMIO flips
11143 */
11144static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
11145{
11146 struct drm_device *dev = intel_crtc->base.dev;
ff944564
DL		 11147
11148 intel_mark_page_flip_active(intel_crtc);
11149
34e0adbb 11150 intel_pipe_update_start(intel_crtc);
ff944564
DL		 11151
11152 if (INTEL_INFO(dev)->gen >= 9)
11153 skl_do_mmio_flip(intel_crtc);
11154 else
11155 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11156 ilk_do_mmio_flip(intel_crtc);
11157
34e0adbb 11158 intel_pipe_update_end(intel_crtc);
84c33a64
SG		 11159}
11160
9362c7c5 11161static void intel_mmio_flip_work_func(struct work_struct *work)
84c33a64 11162{
b2cfe0ab
CW		 11163 struct intel_mmio_flip *mmio_flip =
11164 container_of(work, struct intel_mmio_flip, work);
84c33a64 11165
eed29a5b
DV		 11166 if (mmio_flip->req)
11167 WARN_ON(__i915_wait_request(mmio_flip->req,
b2cfe0ab 11168 mmio_flip->crtc->reset_counter,
bcafc4e3
CW		 11169 false, NULL,
11170 &mmio_flip->i915->rps.mmioflips));
84c33a64 11171
b2cfe0ab
CW		 11172 intel_do_mmio_flip(mmio_flip->crtc);
11173
eed29a5b 11174 i915_gem_request_unreference__unlocked(mmio_flip->req);
b2cfe0ab 11175 kfree(mmio_flip);
84c33a64
SG		 11176}
11177
11178static int intel_queue_mmio_flip(struct drm_device *dev,
11179 struct drm_crtc *crtc,
11180 struct drm_framebuffer *fb,
11181 struct drm_i915_gem_object *obj,
11182 struct intel_engine_cs *ring,
11183 uint32_t flags)
11184{
b2cfe0ab
CW		 11185 struct intel_mmio_flip *mmio_flip;
11186
11187 mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11188 if (mmio_flip == NULL)
11189 return -ENOMEM;
84c33a64 11190
bcafc4e3 11191 mmio_flip->i915 = to_i915(dev);
eed29a5b 11192 mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
b2cfe0ab 11193 mmio_flip->crtc = to_intel_crtc(crtc);
536f5b5e 11194
b2cfe0ab
CW		 11195 INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11196 schedule_work(&mmio_flip->work);
84c33a64 11197
84c33a64
SG		 11198 return 0;
11199}
11200
8c9f3aaf
JB		 11201static int intel_default_queue_flip(struct drm_device *dev,
11202 struct drm_crtc *crtc,
11203 struct drm_framebuffer *fb,
ed8d1975 11204 struct drm_i915_gem_object *obj,
6258fbe2 11205 struct drm_i915_gem_request *req,
ed8d1975 11206 uint32_t flags)
8c9f3aaf
JB		 11207{
11208 return -ENODEV;
11209}
11210
d6bbafa1
CW		 11211static bool __intel_pageflip_stall_check(struct drm_device *dev,
11212 struct drm_crtc *crtc)
11213{
11214 struct drm_i915_private *dev_priv = dev->dev_private;
11215 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11216 struct intel_unpin_work *work = intel_crtc->unpin_work;
11217 u32 addr;
11218
11219 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11220 return true;
11221
908565c2
CW		 11222 if (atomic_read(&work->pending) < INTEL_FLIP_PENDING)
11223 return false;
11224
d6bbafa1
CW		 11225 if (!work->enable_stall_check)
11226 return false;
11227
11228 if (work->flip_ready_vblank == 0) {
3a8a946e
DV		 11229 if (work->flip_queued_req &&
11230 !i915_gem_request_completed(work->flip_queued_req, true))
d6bbafa1
CW		 11231 return false;
11232
1e3feefd 11233 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
d6bbafa1
CW		 11234 }
11235
1e3feefd 11236 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
d6bbafa1
CW		 11237 return false;
11238
11239 /* Potential stall - if we see that the flip has happened,
11240 * assume a missed interrupt. */
11241 if (INTEL_INFO(dev)->gen >= 4)
11242 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11243 else
11244 addr = I915_READ(DSPADDR(intel_crtc->plane));
11245
11246 /* There is a potential issue here with a false positive after a flip
11247 * to the same address. We could address this by checking for a
11248 * non-incrementing frame counter.
11249 */
11250 return addr == work->gtt_offset;
11251}
11252
11253void intel_check_page_flip(struct drm_device *dev, int pipe)
11254{
11255 struct drm_i915_private *dev_priv = dev->dev_private;
11256 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11257 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6ad790c0 11258 struct intel_unpin_work *work;
f326038a 11259
6c51d46f 11260 WARN_ON(!in_interrupt());
d6bbafa1
CW		 11261
11262 if (crtc == NULL)
11263 return;
11264
f326038a 11265 spin_lock(&dev->event_lock);
6ad790c0
CW		 11266 work = intel_crtc->unpin_work;
11267 if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
d6bbafa1 11268 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
6ad790c0 11269 work->flip_queued_vblank, drm_vblank_count(dev, pipe));
d6bbafa1 11270 page_flip_completed(intel_crtc);
6ad790c0 11271 work = NULL;
d6bbafa1 11272 }
6ad790c0
CW		 11273 if (work != NULL &&
11274 drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11275 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
f326038a 11276 spin_unlock(&dev->event_lock);
d6bbafa1
CW		 11277}
11278
6b95a207
KH		 11279static int intel_crtc_page_flip(struct drm_crtc *crtc,
11280 struct drm_framebuffer *fb,
ed8d1975
KP		 11281 struct drm_pending_vblank_event *event,
11282 uint32_t page_flip_flags)
6b95a207
KH		 11283{
11284 struct drm_device *dev = crtc->dev;
11285 struct drm_i915_private *dev_priv = dev->dev_private;
f4510a27 11286 struct drm_framebuffer *old_fb = crtc->primary->fb;
2ff8fde1 11287 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
6b95a207 11288 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
455a6808 11289 struct drm_plane *primary = crtc->primary;
a071fa00 11290 enum pipe pipe = intel_crtc->pipe;
6b95a207 11291 struct intel_unpin_work *work;
a4872ba6 11292 struct intel_engine_cs *ring;
cf5d8a46 11293 bool mmio_flip;
91af127f 11294 struct drm_i915_gem_request *request = NULL;
52e68630 11295 int ret;
6b95a207 11296
2ff8fde1
MR		 11297 /*
11298 * drm_mode_page_flip_ioctl() should already catch this, but double
11299 * check to be safe. In the future we may enable pageflipping from
11300 * a disabled primary plane.
11301 */
11302 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11303 return -EBUSY;
11304
e6a595d2 11305 /* Can't change pixel format via MI display flips. */
f4510a27 11306 if (fb->pixel_format != crtc->primary->fb->pixel_format)
e6a595d2
VS		 11307 return -EINVAL;
11308
11309 /*
11310 * TILEOFF/LINOFF registers can't be changed via MI display flips.
11311 * Note that pitch changes could also affect these register.
11312 */
11313 if (INTEL_INFO(dev)->gen > 3 &&
f4510a27
MR		 11314 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11315 fb->pitches[0] != crtc->primary->fb->pitches[0]))
e6a595d2
VS		 11316 return -EINVAL;
11317
f900db47
CW		 11318 if (i915_terminally_wedged(&dev_priv->gpu_error))
11319 goto out_hang;
11320
b14c5679 11321 work = kzalloc(sizeof(*work), GFP_KERNEL);
6b95a207
KH		 11322 if (work == NULL)
11323 return -ENOMEM;
11324
6b95a207 11325 work->event = event;
b4a98e57 11326 work->crtc = crtc;
ab8d6675 11327 work->old_fb = old_fb;
6b95a207
KH		 11328 INIT_WORK(&work->work, intel_unpin_work_fn);
11329
87b6b101 11330 ret = drm_crtc_vblank_get(crtc);
7317c75e
JB		 11331 if (ret)
11332 goto free_work;
11333
6b95a207 11334 /* We borrow the event spin lock for protecting unpin_work */
5e2d7afc 11335 spin_lock_irq(&dev->event_lock);
6b95a207 11336 if (intel_crtc->unpin_work) {
d6bbafa1
CW		 11337 /* Before declaring the flip queue wedged, check if
11338 * the hardware completed the operation behind our backs.
11339 */
11340 if (__intel_pageflip_stall_check(dev, crtc)) {
11341 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11342 page_flip_completed(intel_crtc);
11343 } else {
11344 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
5e2d7afc 11345 spin_unlock_irq(&dev->event_lock);
468f0b44 11346
d6bbafa1
CW		 11347 drm_crtc_vblank_put(crtc);
11348 kfree(work);
11349 return -EBUSY;
11350 }
6b95a207
KH		 11351 }
11352 intel_crtc->unpin_work = work;
5e2d7afc 11353 spin_unlock_irq(&dev->event_lock);
6b95a207 11354
b4a98e57
CW		 11355 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11356 flush_workqueue(dev_priv->wq);
11357
75dfca80 11358 /* Reference the objects for the scheduled work. */
ab8d6675 11359 drm_framebuffer_reference(work->old_fb);
05394f39 11360 drm_gem_object_reference(&obj->base);
6b95a207 11361
f4510a27 11362 crtc->primary->fb = fb;
afd65eb4 11363 update_state_fb(crtc->primary);
1ed1f968 11364
e1f99ce6 11365 work->pending_flip_obj = obj;
e1f99ce6 11366
89ed88ba
CW		 11367 ret = i915_mutex_lock_interruptible(dev);
11368 if (ret)
11369 goto cleanup;
11370
b4a98e57 11371 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 11372 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 11373
75f7f3ec 11374 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
a071fa00 11375 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
75f7f3ec 11376
4fa62c89
VS		 11377 if (IS_VALLEYVIEW(dev)) {
11378 ring = &dev_priv->ring[BCS];
ab8d6675 11379 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
8e09bf83
CW		 11380 /* vlv: DISPLAY_FLIP fails to change tiling */
11381 ring = NULL;
48bf5b2d 11382 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
2a92d5bc 11383 ring = &dev_priv->ring[BCS];
4fa62c89 11384 } else if (INTEL_INFO(dev)->gen >= 7) {
b4716185 11385 ring = i915_gem_request_get_ring(obj->last_write_req);
4fa62c89
VS		 11386 if (ring == NULL || ring->id != RCS)
11387 ring = &dev_priv->ring[BCS];
11388 } else {
11389 ring = &dev_priv->ring[RCS];
11390 }
11391
cf5d8a46
CW		 11392 mmio_flip = use_mmio_flip(ring, obj);
11393
11394 /* When using CS flips, we want to emit semaphores between rings.
11395 * However, when using mmio flips we will create a task to do the
11396 * synchronisation, so all we want here is to pin the framebuffer
11397 * into the display plane and skip any waits.
11398 */
82bc3b2d 11399 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
cf5d8a46 11400 crtc->primary->state,
91af127f 11401 mmio_flip ? i915_gem_request_get_ring(obj->last_write_req) : ring, &request);
8c9f3aaf
JB		 11402 if (ret)
11403 goto cleanup_pending;
6b95a207 11404
121920fa
TU		 11405 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj)
11406 + intel_crtc->dspaddr_offset;
4fa62c89 11407
cf5d8a46 11408 if (mmio_flip) {
84c33a64
SG		 11409 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
11410 page_flip_flags);
d6bbafa1
CW		 11411 if (ret)
11412 goto cleanup_unpin;
11413
f06cc1b9
JH		 11414 i915_gem_request_assign(&work->flip_queued_req,
11415 obj->last_write_req);
d6bbafa1 11416 } else {
6258fbe2
JH		 11417 if (!request) {
11418 ret = i915_gem_request_alloc(ring, ring->default_context, &request);
11419 if (ret)
11420 goto cleanup_unpin;
11421 }
11422
11423 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
d6bbafa1
CW		 11424 page_flip_flags);
11425 if (ret)
11426 goto cleanup_unpin;
11427
6258fbe2 11428 i915_gem_request_assign(&work->flip_queued_req, request);
d6bbafa1
CW		 11429 }
11430
91af127f 11431 if (request)
75289874 11432 i915_add_request_no_flush(request);
91af127f 11433
1e3feefd 11434 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
d6bbafa1 11435 work->enable_stall_check = true;
4fa62c89 11436
ab8d6675 11437 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
a9ff8714 11438 to_intel_plane(primary)->frontbuffer_bit);
c80ac854 11439 mutex_unlock(&dev->struct_mutex);
a071fa00 11440
4e1e26f1 11441 intel_fbc_disable_crtc(intel_crtc);
a9ff8714
VS		 11442 intel_frontbuffer_flip_prepare(dev,
11443 to_intel_plane(primary)->frontbuffer_bit);
6b95a207 11444
e5510fac
JB		 11445 trace_i915_flip_request(intel_crtc->plane, obj);
11446
6b95a207 11447 return 0;
96b099fd 11448
4fa62c89 11449cleanup_unpin:
82bc3b2d 11450 intel_unpin_fb_obj(fb, crtc->primary->state);
8c9f3aaf 11451cleanup_pending:
91af127f
JH		 11452 if (request)
11453 i915_gem_request_cancel(request);
b4a98e57 11454 atomic_dec(&intel_crtc->unpin_work_count);
89ed88ba
CW		 11455 mutex_unlock(&dev->struct_mutex);
11456cleanup:
f4510a27 11457 crtc->primary->fb = old_fb;
afd65eb4 11458 update_state_fb(crtc->primary);
89ed88ba
CW		 11459
11460 drm_gem_object_unreference_unlocked(&obj->base);
ab8d6675 11461 drm_framebuffer_unreference(work->old_fb);
96b099fd 11462
5e2d7afc 11463 spin_lock_irq(&dev->event_lock);
96b099fd 11464 intel_crtc->unpin_work = NULL;
5e2d7afc 11465 spin_unlock_irq(&dev->event_lock);
96b099fd 11466
87b6b101 11467 drm_crtc_vblank_put(crtc);
7317c75e 11468free_work:
96b099fd
CW		 11469 kfree(work);
11470
f900db47 11471 if (ret == -EIO) {
02e0efb5
ML		 11472 struct drm_atomic_state *state;
11473 struct drm_plane_state *plane_state;
11474
f900db47 11475out_hang:
02e0efb5
ML		 11476 state = drm_atomic_state_alloc(dev);
11477 if (!state)
11478 return -ENOMEM;
11479 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
11480
11481retry:
11482 plane_state = drm_atomic_get_plane_state(state, primary);
11483 ret = PTR_ERR_OR_ZERO(plane_state);
11484 if (!ret) {
11485 drm_atomic_set_fb_for_plane(plane_state, fb);
11486
11487 ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
11488 if (!ret)
11489 ret = drm_atomic_commit(state);
11490 }
11491
11492 if (ret == -EDEADLK) {
11493 drm_modeset_backoff(state->acquire_ctx);
11494 drm_atomic_state_clear(state);
11495 goto retry;
11496 }
11497
11498 if (ret)
11499 drm_atomic_state_free(state);
11500
f0d3dad3 11501 if (ret == 0 && event) {
5e2d7afc 11502 spin_lock_irq(&dev->event_lock);
a071fa00 11503 drm_send_vblank_event(dev, pipe, event);
5e2d7afc 11504 spin_unlock_irq(&dev->event_lock);
f0d3dad3 11505 }
f900db47 11506 }
96b099fd 11507 return ret;
6b95a207
KH		 11508}
11509
da20eabd
ML		 11510
11511/**
11512 * intel_wm_need_update - Check whether watermarks need updating
11513 * @plane: drm plane
11514 * @state: new plane state
11515 *
11516 * Check current plane state versus the new one to determine whether
11517 * watermarks need to be recalculated.
11518 *
11519 * Returns true or false.
11520 */
11521static bool intel_wm_need_update(struct drm_plane *plane,
11522 struct drm_plane_state *state)
11523{
11524 /* Update watermarks on tiling changes. */
11525 if (!plane->state->fb || !state->fb ||
11526 plane->state->fb->modifier[0] != state->fb->modifier[0] ||
11527 plane->state->rotation != state->rotation)
11528 return true;
11529
11530 if (plane->state->crtc_w != state->crtc_w)
11531 return true;
11532
11533 return false;
11534}
11535
11536int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11537 struct drm_plane_state *plane_state)
11538{
11539 struct drm_crtc *crtc = crtc_state->crtc;
11540 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11541 struct drm_plane *plane = plane_state->plane;
11542 struct drm_device *dev = crtc->dev;
11543 struct drm_i915_private *dev_priv = dev->dev_private;
11544 struct intel_plane_state *old_plane_state =
11545 to_intel_plane_state(plane->state);
11546 int idx = intel_crtc->base.base.id, ret;
11547 int i = drm_plane_index(plane);
11548 bool mode_changed = needs_modeset(crtc_state);
11549 bool was_crtc_enabled = crtc->state->active;
11550 bool is_crtc_enabled = crtc_state->active;
11551
11552 bool turn_off, turn_on, visible, was_visible;
11553 struct drm_framebuffer *fb = plane_state->fb;
11554
11555 if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
11556 plane->type != DRM_PLANE_TYPE_CURSOR) {
11557 ret = skl_update_scaler_plane(
11558 to_intel_crtc_state(crtc_state),
11559 to_intel_plane_state(plane_state));
11560 if (ret)
11561 return ret;
11562 }
11563
11564 /*
11565 * Disabling a plane is always okay; we just need to update
11566 * fb tracking in a special way since cleanup_fb() won't
11567 * get called by the plane helpers.
11568 */
11569 if (old_plane_state->base.fb && !fb)
11570 intel_crtc->atomic.disabled_planes |= 1 << i;
11571
da20eabd
ML		 11572 was_visible = old_plane_state->visible;
11573 visible = to_intel_plane_state(plane_state)->visible;
11574
11575 if (!was_crtc_enabled && WARN_ON(was_visible))
11576 was_visible = false;
11577
11578 if (!is_crtc_enabled && WARN_ON(visible))
11579 visible = false;
11580
11581 if (!was_visible && !visible)
11582 return 0;
11583
11584 turn_off = was_visible && (!visible || mode_changed);
11585 turn_on = visible && (!was_visible || mode_changed);
11586
11587 DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx,
11588 plane->base.id, fb ? fb->base.id : -1);
11589
11590 DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n",
11591 plane->base.id, was_visible, visible,
11592 turn_off, turn_on, mode_changed);
11593
852eb00d 11594 if (turn_on) {
f015c551 11595 intel_crtc->atomic.update_wm_pre = true;
852eb00d
VS		 11596 /* must disable cxsr around plane enable/disable */
11597 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11598 intel_crtc->atomic.disable_cxsr = true;
11599 /* to potentially re-enable cxsr */
11600 intel_crtc->atomic.wait_vblank = true;
11601 intel_crtc->atomic.update_wm_post = true;
11602 }
11603 } else if (turn_off) {
f015c551 11604 intel_crtc->atomic.update_wm_post = true;
852eb00d
VS		 11605 /* must disable cxsr around plane enable/disable */
11606 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11607 if (is_crtc_enabled)
11608 intel_crtc->atomic.wait_vblank = true;
11609 intel_crtc->atomic.disable_cxsr = true;
11610 }
11611 } else if (intel_wm_need_update(plane, plane_state)) {
f015c551 11612 intel_crtc->atomic.update_wm_pre = true;
852eb00d 11613 }
da20eabd 11614
8be6ca85 11615 if (visible || was_visible)
a9ff8714
VS		 11616 intel_crtc->atomic.fb_bits |=
11617 to_intel_plane(plane)->frontbuffer_bit;
11618
da20eabd
ML		 11619 switch (plane->type) {
11620 case DRM_PLANE_TYPE_PRIMARY:
da20eabd
ML		 11621 intel_crtc->atomic.wait_for_flips = true;
11622 intel_crtc->atomic.pre_disable_primary = turn_off;
11623 intel_crtc->atomic.post_enable_primary = turn_on;
11624
066cf55b
RV		 11625 if (turn_off) {
11626 /*
11627 * FIXME: Actually if we will still have any other
11628 * plane enabled on the pipe we could let IPS enabled
11629 * still, but for now lets consider that when we make
11630 * primary invisible by setting DSPCNTR to 0 on
11631 * update_primary_plane function IPS needs to be
11632 * disable.
11633 */
11634 intel_crtc->atomic.disable_ips = true;
11635
da20eabd 11636 intel_crtc->atomic.disable_fbc = true;
066cf55b 11637 }
da20eabd
ML		 11638
11639 /*
11640 * FBC does not work on some platforms for rotated
11641 * planes, so disable it when rotation is not 0 and
11642 * update it when rotation is set back to 0.
11643 *
11644 * FIXME: This is redundant with the fbc update done in
11645 * the primary plane enable function except that that
11646 * one is done too late. We eventually need to unify
11647 * this.
11648 */
11649
11650 if (visible &&
11651 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11652 dev_priv->fbc.crtc == intel_crtc &&
11653 plane_state->rotation != BIT(DRM_ROTATE_0))
11654 intel_crtc->atomic.disable_fbc = true;
11655
11656 /*
11657 * BDW signals flip done immediately if the plane
11658 * is disabled, even if the plane enable is already
11659 * armed to occur at the next vblank :(
11660 */
11661 if (turn_on && IS_BROADWELL(dev))
11662 intel_crtc->atomic.wait_vblank = true;
11663
11664 intel_crtc->atomic.update_fbc |= visible || mode_changed;
11665 break;
11666 case DRM_PLANE_TYPE_CURSOR:
da20eabd
ML		 11667 break;
11668 case DRM_PLANE_TYPE_OVERLAY:
d032ffa0 11669 if (turn_off && !mode_changed) {
da20eabd
ML		 11670 intel_crtc->atomic.wait_vblank = true;
11671 intel_crtc->atomic.update_sprite_watermarks |=
11672 1 << i;
11673 }
da20eabd
ML		 11674 }
11675 return 0;
11676}
11677
6d3a1ce7
ML		 11678static bool encoders_cloneable(const struct intel_encoder *a,
11679 const struct intel_encoder *b)
11680{
11681 /* masks could be asymmetric, so check both ways */
11682 return a == b || (a->cloneable & (1 << b->type) &&
11683 b->cloneable & (1 << a->type));
11684}
11685
11686static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11687 struct intel_crtc *crtc,
11688 struct intel_encoder *encoder)
11689{
11690 struct intel_encoder *source_encoder;
11691 struct drm_connector *connector;
11692 struct drm_connector_state *connector_state;
11693 int i;
11694
11695 for_each_connector_in_state(state, connector, connector_state, i) {
11696 if (connector_state->crtc != &crtc->base)
11697 continue;
11698
11699 source_encoder =
11700 to_intel_encoder(connector_state->best_encoder);
11701 if (!encoders_cloneable(encoder, source_encoder))
11702 return false;
11703 }
11704
11705 return true;
11706}
11707
11708static bool check_encoder_cloning(struct drm_atomic_state *state,
11709 struct intel_crtc *crtc)
11710{
11711 struct intel_encoder *encoder;
11712 struct drm_connector *connector;
11713 struct drm_connector_state *connector_state;
11714 int i;
11715
11716 for_each_connector_in_state(state, connector, connector_state, i) {
11717 if (connector_state->crtc != &crtc->base)
11718 continue;
11719
11720 encoder = to_intel_encoder(connector_state->best_encoder);
11721 if (!check_single_encoder_cloning(state, crtc, encoder))
11722 return false;
11723 }
11724
11725 return true;
11726}
11727
11728static int intel_crtc_atomic_check(struct drm_crtc *crtc,
11729 struct drm_crtc_state *crtc_state)
11730{
cf5a15be 11731 struct drm_device *dev = crtc->dev;
ad421372 11732 struct drm_i915_private *dev_priv = dev->dev_private;
6d3a1ce7 11733 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cf5a15be
ML		 11734 struct intel_crtc_state *pipe_config =
11735 to_intel_crtc_state(crtc_state);
6d3a1ce7 11736 struct drm_atomic_state *state = crtc_state->state;
4d20cd86 11737 int ret;
6d3a1ce7
ML		 11738 bool mode_changed = needs_modeset(crtc_state);
11739
11740 if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
11741 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11742 return -EINVAL;
11743 }
11744
852eb00d
VS		 11745 if (mode_changed && !crtc_state->active)
11746 intel_crtc->atomic.update_wm_post = true;
eddfcbcd 11747
ad421372
ML		 11748 if (mode_changed && crtc_state->enable &&
11749 dev_priv->display.crtc_compute_clock &&
11750 !WARN_ON(pipe_config->shared_dpll != DPLL_ID_PRIVATE)) {
11751 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11752 pipe_config);
11753 if (ret)
11754 return ret;
11755 }
11756
e435d6e5
ML		 11757 ret = 0;
11758 if (INTEL_INFO(dev)->gen >= 9) {
11759 if (mode_changed)
11760 ret = skl_update_scaler_crtc(pipe_config);
11761
11762 if (!ret)
11763 ret = intel_atomic_setup_scalers(dev, intel_crtc,
11764 pipe_config);
11765 }
11766
11767 return ret;
6d3a1ce7
ML		 11768}
11769
65b38e0d 11770static const struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 11771 .mode_set_base_atomic = intel_pipe_set_base_atomic,
11772 .load_lut = intel_crtc_load_lut,
ea2c67bb
MR		 11773 .atomic_begin = intel_begin_crtc_commit,
11774 .atomic_flush = intel_finish_crtc_commit,
6d3a1ce7 11775 .atomic_check = intel_crtc_atomic_check,
f6e5b160
CW		 11776};
11777
d29b2f9d
ACO		 11778static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11779{
11780 struct intel_connector *connector;
11781
11782 for_each_intel_connector(dev, connector) {
11783 if (connector->base.encoder) {
11784 connector->base.state->best_encoder =
11785 connector->base.encoder;
11786 connector->base.state->crtc =
11787 connector->base.encoder->crtc;
11788 } else {
11789 connector->base.state->best_encoder = NULL;
11790 connector->base.state->crtc = NULL;
11791 }
11792 }
11793}
11794
050f7aeb 11795static void
eba905b2 11796connected_sink_compute_bpp(struct intel_connector *connector,
5cec258b 11797 struct intel_crtc_state *pipe_config)
050f7aeb
DV		 11798{
11799 int bpp = pipe_config->pipe_bpp;
11800
11801 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11802 connector->base.base.id,
c23cc417 11803 connector->base.name);
050f7aeb
DV		 11804
11805 /* Don't use an invalid EDID bpc value */
11806 if (connector->base.display_info.bpc &&
11807 connector->base.display_info.bpc * 3 < bpp) {
11808 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11809 bpp, connector->base.display_info.bpc*3);
11810 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11811 }
11812
11813 /* Clamp bpp to 8 on screens without EDID 1.4 */
11814 if (connector->base.display_info.bpc == 0 && bpp > 24) {
11815 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11816 bpp);
11817 pipe_config->pipe_bpp = 24;
11818 }
11819}
11820
4e53c2e0 11821static int
050f7aeb 11822compute_baseline_pipe_bpp(struct intel_crtc *crtc,
5cec258b 11823 struct intel_crtc_state *pipe_config)
4e53c2e0 11824{
050f7aeb 11825 struct drm_device *dev = crtc->base.dev;
1486017f 11826 struct drm_atomic_state *state;
da3ced29
ACO		 11827 struct drm_connector *connector;
11828 struct drm_connector_state *connector_state;
1486017f 11829 int bpp, i;
4e53c2e0 11830
d328c9d7 11831 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
4e53c2e0 11832 bpp = 10*3;
d328c9d7
DV		 11833 else if (INTEL_INFO(dev)->gen >= 5)
11834 bpp = 12*3;
11835 else
11836 bpp = 8*3;
11837
4e53c2e0 11838
4e53c2e0
DV		 11839 pipe_config->pipe_bpp = bpp;
11840
1486017f
ACO		 11841 state = pipe_config->base.state;
11842
4e53c2e0 11843 /* Clamp display bpp to EDID value */
da3ced29
ACO		 11844 for_each_connector_in_state(state, connector, connector_state, i) {
11845 if (connector_state->crtc != &crtc->base)
4e53c2e0
DV		 11846 continue;
11847
da3ced29
ACO		 11848 connected_sink_compute_bpp(to_intel_connector(connector),
11849 pipe_config);
4e53c2e0
DV		 11850 }
11851
11852 return bpp;
11853}
11854
644db711
DV		 11855static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11856{
11857 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11858 "type: 0x%x flags: 0x%x\n",
1342830c 11859 mode->crtc_clock,
644db711
DV		 11860 mode->crtc_hdisplay, mode->crtc_hsync_start,
11861 mode->crtc_hsync_end, mode->crtc_htotal,
11862 mode->crtc_vdisplay, mode->crtc_vsync_start,
11863 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11864}
11865
c0b03411 11866static void intel_dump_pipe_config(struct intel_crtc *crtc,
5cec258b 11867 struct intel_crtc_state *pipe_config,
c0b03411
DV		 11868 const char *context)
11869{
6a60cd87
CK		 11870 struct drm_device *dev = crtc->base.dev;
11871 struct drm_plane *plane;
11872 struct intel_plane *intel_plane;
11873 struct intel_plane_state *state;
11874 struct drm_framebuffer *fb;
11875
11876 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
11877 context, pipe_config, pipe_name(crtc->pipe));
c0b03411
DV		 11878
11879 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
11880 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
11881 pipe_config->pipe_bpp, pipe_config->dither);
11882 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11883 pipe_config->has_pch_encoder,
11884 pipe_config->fdi_lanes,
11885 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
11886 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
11887 pipe_config->fdi_m_n.tu);
90a6b7b0 11888 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
eb14cb74 11889 pipe_config->has_dp_encoder,
90a6b7b0 11890 pipe_config->lane_count,
eb14cb74
VS		 11891 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
11892 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
11893 pipe_config->dp_m_n.tu);
b95af8be 11894
90a6b7b0 11895 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
b95af8be 11896 pipe_config->has_dp_encoder,
90a6b7b0 11897 pipe_config->lane_count,
b95af8be
VK		 11898 pipe_config->dp_m2_n2.gmch_m,
11899 pipe_config->dp_m2_n2.gmch_n,
11900 pipe_config->dp_m2_n2.link_m,
11901 pipe_config->dp_m2_n2.link_n,
11902 pipe_config->dp_m2_n2.tu);
11903
55072d19
DV		 11904 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11905 pipe_config->has_audio,
11906 pipe_config->has_infoframe);
11907
c0b03411 11908 DRM_DEBUG_KMS("requested mode:\n");
2d112de7 11909 drm_mode_debug_printmodeline(&pipe_config->base.mode);
c0b03411 11910 DRM_DEBUG_KMS("adjusted mode:\n");
2d112de7
ACO		 11911 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
11912 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
d71b8d4a 11913 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
37327abd
VS		 11914 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
11915 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
0ec463d3
TU		 11916 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
11917 crtc->num_scalers,
11918 pipe_config->scaler_state.scaler_users,
11919 pipe_config->scaler_state.scaler_id);
c0b03411
DV		 11920 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11921 pipe_config->gmch_pfit.control,
11922 pipe_config->gmch_pfit.pgm_ratios,
11923 pipe_config->gmch_pfit.lvds_border_bits);
fd4daa9c 11924 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
c0b03411 11925 pipe_config->pch_pfit.pos,
fd4daa9c
CW		 11926 pipe_config->pch_pfit.size,
11927 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
42db64ef 11928 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
cf532bb2 11929 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
6a60cd87 11930
415ff0f6 11931 if (IS_BROXTON(dev)) {
05712c15 11932 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
415ff0f6 11933 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
c8453338 11934 "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
415ff0f6
TU		 11935 pipe_config->ddi_pll_sel,
11936 pipe_config->dpll_hw_state.ebb0,
05712c15 11937 pipe_config->dpll_hw_state.ebb4,
415ff0f6
TU		 11938 pipe_config->dpll_hw_state.pll0,
11939 pipe_config->dpll_hw_state.pll1,
11940 pipe_config->dpll_hw_state.pll2,
11941 pipe_config->dpll_hw_state.pll3,
11942 pipe_config->dpll_hw_state.pll6,
11943 pipe_config->dpll_hw_state.pll8,
05712c15 11944 pipe_config->dpll_hw_state.pll9,
c8453338 11945 pipe_config->dpll_hw_state.pll10,
415ff0f6
TU		 11946 pipe_config->dpll_hw_state.pcsdw12);
11947 } else if (IS_SKYLAKE(dev)) {
11948 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
11949 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
11950 pipe_config->ddi_pll_sel,
11951 pipe_config->dpll_hw_state.ctrl1,
11952 pipe_config->dpll_hw_state.cfgcr1,
11953 pipe_config->dpll_hw_state.cfgcr2);
11954 } else if (HAS_DDI(dev)) {
11955 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x\n",
11956 pipe_config->ddi_pll_sel,
11957 pipe_config->dpll_hw_state.wrpll);
11958 } else {
11959 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
11960 "fp0: 0x%x, fp1: 0x%x\n",
11961 pipe_config->dpll_hw_state.dpll,
11962 pipe_config->dpll_hw_state.dpll_md,
11963 pipe_config->dpll_hw_state.fp0,
11964 pipe_config->dpll_hw_state.fp1);
11965 }
11966
6a60cd87
CK		 11967 DRM_DEBUG_KMS("planes on this crtc\n");
11968 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
11969 intel_plane = to_intel_plane(plane);
11970 if (intel_plane->pipe != crtc->pipe)
11971 continue;
11972
11973 state = to_intel_plane_state(plane->state);
11974 fb = state->base.fb;
11975 if (!fb) {
11976 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
11977 "disabled, scaler_id = %d\n",
11978 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
11979 plane->base.id, intel_plane->pipe,
11980 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
11981 drm_plane_index(plane), state->scaler_id);
11982 continue;
11983 }
11984
11985 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
11986 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
11987 plane->base.id, intel_plane->pipe,
11988 crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
11989 drm_plane_index(plane));
11990 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
11991 fb->base.id, fb->width, fb->height, fb->pixel_format);
11992 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
11993 state->scaler_id,
11994 state->src.x1 >> 16, state->src.y1 >> 16,
11995 drm_rect_width(&state->src) >> 16,
11996 drm_rect_height(&state->src) >> 16,
11997 state->dst.x1, state->dst.y1,
11998 drm_rect_width(&state->dst), drm_rect_height(&state->dst));
11999 }
c0b03411
DV		 12000}
12001
5448a00d 12002static bool check_digital_port_conflicts(struct drm_atomic_state *state)
00f0b378 12003{
5448a00d
ACO		 12004 struct drm_device *dev = state->dev;
12005 struct intel_encoder *encoder;
da3ced29 12006 struct drm_connector *connector;
5448a00d 12007 struct drm_connector_state *connector_state;
00f0b378 12008 unsigned int used_ports = 0;
5448a00d 12009 int i;
00f0b378
VS		 12010
12011 /*
12012 * Walk the connector list instead of the encoder
12013 * list to detect the problem on ddi platforms
12014 * where there's just one encoder per digital port.
12015 */
da3ced29 12016 for_each_connector_in_state(state, connector, connector_state, i) {
5448a00d 12017 if (!connector_state->best_encoder)
00f0b378
VS		 12018 continue;
12019
5448a00d
ACO		 12020 encoder = to_intel_encoder(connector_state->best_encoder);
12021
12022 WARN_ON(!connector_state->crtc);
00f0b378
VS		 12023
12024 switch (encoder->type) {
12025 unsigned int port_mask;
12026 case INTEL_OUTPUT_UNKNOWN:
12027 if (WARN_ON(!HAS_DDI(dev)))
12028 break;
12029 case INTEL_OUTPUT_DISPLAYPORT:
12030 case INTEL_OUTPUT_HDMI:
12031 case INTEL_OUTPUT_EDP:
12032 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12033
12034 /* the same port mustn't appear more than once */
12035 if (used_ports & port_mask)
12036 return false;
12037
12038 used_ports |= port_mask;
12039 default:
12040 break;
12041 }
12042 }
12043
12044 return true;
12045}
12046
83a57153
ACO		 12047static void
12048clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12049{
12050 struct drm_crtc_state tmp_state;
663a3640 12051 struct intel_crtc_scaler_state scaler_state;
4978cc93
ACO		 12052 struct intel_dpll_hw_state dpll_hw_state;
12053 enum intel_dpll_id shared_dpll;
8504c74c 12054 uint32_t ddi_pll_sel;
c4e2d043 12055 bool force_thru;
83a57153 12056
7546a384
ACO		 12057 /* FIXME: before the switch to atomic started, a new pipe_config was
12058 * kzalloc'd. Code that depends on any field being zero should be
12059 * fixed, so that the crtc_state can be safely duplicated. For now,
12060 * only fields that are know to not cause problems are preserved. */
12061
83a57153 12062 tmp_state = crtc_state->base;
663a3640 12063 scaler_state = crtc_state->scaler_state;
4978cc93
ACO		 12064 shared_dpll = crtc_state->shared_dpll;
12065 dpll_hw_state = crtc_state->dpll_hw_state;
8504c74c 12066 ddi_pll_sel = crtc_state->ddi_pll_sel;
c4e2d043 12067 force_thru = crtc_state->pch_pfit.force_thru;
4978cc93 12068
83a57153 12069 memset(crtc_state, 0, sizeof *crtc_state);
4978cc93 12070
83a57153 12071 crtc_state->base = tmp_state;
663a3640 12072 crtc_state->scaler_state = scaler_state;
4978cc93
ACO		 12073 crtc_state->shared_dpll = shared_dpll;
12074 crtc_state->dpll_hw_state = dpll_hw_state;
8504c74c 12075 crtc_state->ddi_pll_sel = ddi_pll_sel;
c4e2d043 12076 crtc_state->pch_pfit.force_thru = force_thru;
83a57153
ACO		 12077}
12078
548ee15b 12079static int
b8cecdf5 12080intel_modeset_pipe_config(struct drm_crtc *crtc,
b359283a 12081 struct intel_crtc_state *pipe_config)
ee7b9f93 12082{
b359283a 12083 struct drm_atomic_state *state = pipe_config->base.state;
7758a113 12084 struct intel_encoder *encoder;
da3ced29 12085 struct drm_connector *connector;
0b901879 12086 struct drm_connector_state *connector_state;
d328c9d7 12087 int base_bpp, ret = -EINVAL;
0b901879 12088 int i;
e29c22c0 12089 bool retry = true;
ee7b9f93 12090
83a57153 12091 clear_intel_crtc_state(pipe_config);
7758a113 12092
e143a21c
DV		 12093 pipe_config->cpu_transcoder =
12094 (enum transcoder) to_intel_crtc(crtc)->pipe;
b8cecdf5 12095
2960bc9c
ID		 12096 /*
12097 * Sanitize sync polarity flags based on requested ones. If neither
12098 * positive or negative polarity is requested, treat this as meaning
12099 * negative polarity.
12100 */
2d112de7 12101 if (!(pipe_config->base.adjusted_mode.flags &
2960bc9c 12102 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
2d112de7 12103 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
2960bc9c 12104
2d112de7 12105 if (!(pipe_config->base.adjusted_mode.flags &
2960bc9c 12106 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
2d112de7 12107 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
2960bc9c 12108
d328c9d7
DV		 12109 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12110 pipe_config);
12111 if (base_bpp < 0)
4e53c2e0
DV		 12112 goto fail;
12113
e41a56be
VS		 12114 /*
12115 * Determine the real pipe dimensions. Note that stereo modes can
12116 * increase the actual pipe size due to the frame doubling and
12117 * insertion of additional space for blanks between the frame. This
12118 * is stored in the crtc timings. We use the requested mode to do this
12119 * computation to clearly distinguish it from the adjusted mode, which
12120 * can be changed by the connectors in the below retry loop.
12121 */
2d112de7 12122 drm_crtc_get_hv_timing(&pipe_config->base.mode,
ecb7e16b
GP		 12123 &pipe_config->pipe_src_w,
12124 &pipe_config->pipe_src_h);
e41a56be 12125
e29c22c0 12126encoder_retry:
ef1b460d 12127 /* Ensure the port clock defaults are reset when retrying. */
ff9a6750 12128 pipe_config->port_clock = 0;
ef1b460d 12129 pipe_config->pixel_multiplier = 1;
ff9a6750 12130
135c81b8 12131 /* Fill in default crtc timings, allow encoders to overwrite them. */
2d112de7
ACO		 12132 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12133 CRTC_STEREO_DOUBLE);
135c81b8 12134
7758a113
DV		 12135 /* Pass our mode to the connectors and the CRTC to give them a chance to
12136 * adjust it according to limitations or connector properties, and also
12137 * a chance to reject the mode entirely.
47f1c6c9 12138 */
da3ced29 12139 for_each_connector_in_state(state, connector, connector_state, i) {
0b901879 12140 if (connector_state->crtc != crtc)
7758a113 12141 continue;
7ae89233 12142
0b901879
ACO		 12143 encoder = to_intel_encoder(connector_state->best_encoder);
12144
efea6e8e
DV		 12145 if (!(encoder->compute_config(encoder, pipe_config))) {
12146 DRM_DEBUG_KMS("Encoder config failure\n");
7758a113
DV		 12147 goto fail;
12148 }
ee7b9f93 12149 }
47f1c6c9 12150
ff9a6750
DV		 12151 /* Set default port clock if not overwritten by the encoder. Needs to be
12152 * done afterwards in case the encoder adjusts the mode. */
12153 if (!pipe_config->port_clock)
2d112de7 12154 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
241bfc38 12155 * pipe_config->pixel_multiplier;
ff9a6750 12156
a43f6e0f 12157 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
e29c22c0 12158 if (ret < 0) {
7758a113
DV		 12159 DRM_DEBUG_KMS("CRTC fixup failed\n");
12160 goto fail;
ee7b9f93 12161 }
e29c22c0
DV		 12162
12163 if (ret == RETRY) {
12164 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12165 ret = -EINVAL;
12166 goto fail;
12167 }
12168
12169 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12170 retry = false;
12171 goto encoder_retry;
12172 }
12173
e8fa4270
DV		 12174 /* Dithering seems to not pass-through bits correctly when it should, so
12175 * only enable it on 6bpc panels. */
12176 pipe_config->dither = pipe_config->pipe_bpp == 6*3;
62f0ace5 12177 DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
d328c9d7 12178 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
4e53c2e0 12179
7758a113 12180fail:
548ee15b 12181 return ret;
ee7b9f93 12182}
47f1c6c9 12183
ea9d758d 12184static void
4740b0f2 12185intel_modeset_update_crtc_state(struct drm_atomic_state *state)
ea9d758d 12186{
0a9ab303
ACO		 12187 struct drm_crtc *crtc;
12188 struct drm_crtc_state *crtc_state;
8a75d157 12189 int i;
ea9d758d 12190
7668851f 12191 /* Double check state. */
8a75d157 12192 for_each_crtc_in_state(state, crtc, crtc_state, i) {
3cb480bc 12193 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
fc467a22
ML		 12194
12195 /* Update hwmode for vblank functions */
12196 if (crtc->state->active)
12197 crtc->hwmode = crtc->state->adjusted_mode;
12198 else
12199 crtc->hwmode.crtc_clock = 0;
ea9d758d 12200 }
ea9d758d
DV		 12201}
12202
3bd26263 12203static bool intel_fuzzy_clock_check(int clock1, int clock2)
f1f644dc 12204{
3bd26263 12205 int diff;
f1f644dc
JB		 12206
12207 if (clock1 == clock2)
12208 return true;
12209
12210 if (!clock1 || !clock2)
12211 return false;
12212
12213 diff = abs(clock1 - clock2);
12214
12215 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12216 return true;
12217
12218 return false;
12219}
12220
25c5b266
DV		 12221#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12222 list_for_each_entry((intel_crtc), \
12223 &(dev)->mode_config.crtc_list, \
12224 base.head) \
0973f18f 12225 if (mask & (1 <<(intel_crtc)->pipe))
25c5b266 12226
cfb23ed6
ML		 12227static bool
12228intel_compare_m_n(unsigned int m, unsigned int n,
12229 unsigned int m2, unsigned int n2,
12230 bool exact)
12231{
12232 if (m == m2 && n == n2)
12233 return true;
12234
12235 if (exact || !m || !n || !m2 || !n2)
12236 return false;
12237
12238 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
12239
12240 if (m > m2) {
12241 while (m > m2) {
12242 m2 <<= 1;
12243 n2 <<= 1;
12244 }
12245 } else if (m < m2) {
12246 while (m < m2) {
12247 m <<= 1;
12248 n <<= 1;
12249 }
12250 }
12251
12252 return m == m2 && n == n2;
12253}
12254
12255static bool
12256intel_compare_link_m_n(const struct intel_link_m_n *m_n,
12257 struct intel_link_m_n *m2_n2,
12258 bool adjust)
12259{
12260 if (m_n->tu == m2_n2->tu &&
12261 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
12262 m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
12263 intel_compare_m_n(m_n->link_m, m_n->link_n,
12264 m2_n2->link_m, m2_n2->link_n, !adjust)) {
12265 if (adjust)
12266 *m2_n2 = *m_n;
12267
12268 return true;
12269 }
12270
12271 return false;
12272}
12273
0e8ffe1b 12274static bool
2fa2fe9a 12275intel_pipe_config_compare(struct drm_device *dev,
5cec258b 12276 struct intel_crtc_state *current_config,
cfb23ed6
ML		 12277 struct intel_crtc_state *pipe_config,
12278 bool adjust)
0e8ffe1b 12279{
cfb23ed6
ML		 12280 bool ret = true;
12281
12282#define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
12283 do { \
12284 if (!adjust) \
12285 DRM_ERROR(fmt, ##__VA_ARGS__); \
12286 else \
12287 DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
12288 } while (0)
12289
66e985c0
DV		 12290#define PIPE_CONF_CHECK_X(name) \
12291 if (current_config->name != pipe_config->name) { \
cfb23ed6 12292 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
66e985c0
DV		 12293 "(expected 0x%08x, found 0x%08x)\n", \
12294 current_config->name, \
12295 pipe_config->name); \
cfb23ed6 12296 ret = false; \
66e985c0
DV		 12297 }
12298
08a24034
DV		 12299#define PIPE_CONF_CHECK_I(name) \
12300 if (current_config->name != pipe_config->name) { \
cfb23ed6 12301 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
08a24034
DV		 12302 "(expected %i, found %i)\n", \
12303 current_config->name, \
12304 pipe_config->name); \
cfb23ed6
ML		 12305 ret = false; \
12306 }
12307
12308#define PIPE_CONF_CHECK_M_N(name) \
12309 if (!intel_compare_link_m_n(&current_config->name, \
12310 &pipe_config->name,\
12311 adjust)) { \
12312 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12313 "(expected tu %i gmch %i/%i link %i/%i, " \
12314 "found tu %i, gmch %i/%i link %i/%i)\n", \
12315 current_config->name.tu, \
12316 current_config->name.gmch_m, \
12317 current_config->name.gmch_n, \
12318 current_config->name.link_m, \
12319 current_config->name.link_n, \
12320 pipe_config->name.tu, \
12321 pipe_config->name.gmch_m, \
12322 pipe_config->name.gmch_n, \
12323 pipe_config->name.link_m, \
12324 pipe_config->name.link_n); \
12325 ret = false; \
12326 }
12327
12328#define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
12329 if (!intel_compare_link_m_n(&current_config->name, \
12330 &pipe_config->name, adjust) && \
12331 !intel_compare_link_m_n(&current_config->alt_name, \
12332 &pipe_config->name, adjust)) { \
12333 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12334 "(expected tu %i gmch %i/%i link %i/%i, " \
12335 "or tu %i gmch %i/%i link %i/%i, " \
12336 "found tu %i, gmch %i/%i link %i/%i)\n", \
12337 current_config->name.tu, \
12338 current_config->name.gmch_m, \
12339 current_config->name.gmch_n, \
12340 current_config->name.link_m, \
12341 current_config->name.link_n, \
12342 current_config->alt_name.tu, \
12343 current_config->alt_name.gmch_m, \
12344 current_config->alt_name.gmch_n, \
12345 current_config->alt_name.link_m, \
12346 current_config->alt_name.link_n, \
12347 pipe_config->name.tu, \
12348 pipe_config->name.gmch_m, \
12349 pipe_config->name.gmch_n, \
12350 pipe_config->name.link_m, \
12351 pipe_config->name.link_n); \
12352 ret = false; \
88adfff1
DV		 12353 }
12354
b95af8be
VK		 12355/* This is required for BDW+ where there is only one set of registers for
12356 * switching between high and low RR.
12357 * This macro can be used whenever a comparison has to be made between one
12358 * hw state and multiple sw state variables.
12359 */
12360#define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
12361 if ((current_config->name != pipe_config->name) && \
12362 (current_config->alt_name != pipe_config->name)) { \
cfb23ed6 12363 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
b95af8be
VK		 12364 "(expected %i or %i, found %i)\n", \
12365 current_config->name, \
12366 current_config->alt_name, \
12367 pipe_config->name); \
cfb23ed6 12368 ret = false; \
b95af8be
VK		 12369 }
12370
1bd1bd80
DV		 12371#define PIPE_CONF_CHECK_FLAGS(name, mask) \
12372 if ((current_config->name ^ pipe_config->name) & (mask)) { \
cfb23ed6 12373 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
1bd1bd80
DV		 12374 "(expected %i, found %i)\n", \
12375 current_config->name & (mask), \
12376 pipe_config->name & (mask)); \
cfb23ed6 12377 ret = false; \
1bd1bd80
DV		 12378 }
12379
5e550656
VS		 12380#define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12381 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
cfb23ed6 12382 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
5e550656
VS		 12383 "(expected %i, found %i)\n", \
12384 current_config->name, \
12385 pipe_config->name); \
cfb23ed6 12386 ret = false; \
5e550656
VS		 12387 }
12388
bb760063
DV		 12389#define PIPE_CONF_QUIRK(quirk) \
12390 ((current_config->quirks | pipe_config->quirks) & (quirk))
12391
eccb140b
DV		 12392 PIPE_CONF_CHECK_I(cpu_transcoder);
12393
08a24034
DV		 12394 PIPE_CONF_CHECK_I(has_pch_encoder);
12395 PIPE_CONF_CHECK_I(fdi_lanes);
cfb23ed6 12396 PIPE_CONF_CHECK_M_N(fdi_m_n);
08a24034 12397
eb14cb74 12398 PIPE_CONF_CHECK_I(has_dp_encoder);
90a6b7b0 12399 PIPE_CONF_CHECK_I(lane_count);
b95af8be
VK		 12400
12401 if (INTEL_INFO(dev)->gen < 8) {
cfb23ed6
ML		 12402 PIPE_CONF_CHECK_M_N(dp_m_n);
12403
12404 PIPE_CONF_CHECK_I(has_drrs);
12405 if (current_config->has_drrs)
12406 PIPE_CONF_CHECK_M_N(dp_m2_n2);
12407 } else
12408 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
eb14cb74 12409
2d112de7
ACO		 12410 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12411 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12412 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12413 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12414 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12415 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
1bd1bd80 12416
2d112de7
ACO		 12417 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12418 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12419 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12420 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12421 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12422 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
1bd1bd80 12423
c93f54cf 12424 PIPE_CONF_CHECK_I(pixel_multiplier);
6897b4b5 12425 PIPE_CONF_CHECK_I(has_hdmi_sink);
b5a9fa09
DV		 12426 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12427 IS_VALLEYVIEW(dev))
12428 PIPE_CONF_CHECK_I(limited_color_range);
e43823ec 12429 PIPE_CONF_CHECK_I(has_infoframe);
6c49f241 12430
9ed109a7
DV		 12431 PIPE_CONF_CHECK_I(has_audio);
12432
2d112de7 12433 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
1bd1bd80
DV		 12434 DRM_MODE_FLAG_INTERLACE);
12435
bb760063 12436 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
2d112de7 12437 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 12438 DRM_MODE_FLAG_PHSYNC);
2d112de7 12439 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 12440 DRM_MODE_FLAG_NHSYNC);
2d112de7 12441 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 12442 DRM_MODE_FLAG_PVSYNC);
2d112de7 12443 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063
DV		 12444 DRM_MODE_FLAG_NVSYNC);
12445 }
045ac3b5 12446
333b8ca8 12447 PIPE_CONF_CHECK_X(gmch_pfit.control);
e2ff2d4a
DV		 12448 /* pfit ratios are autocomputed by the hw on gen4+ */
12449 if (INTEL_INFO(dev)->gen < 4)
12450 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
333b8ca8 12451 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
9953599b 12452
bfd16b2a
ML		 12453 if (!adjust) {
12454 PIPE_CONF_CHECK_I(pipe_src_w);
12455 PIPE_CONF_CHECK_I(pipe_src_h);
12456
12457 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12458 if (current_config->pch_pfit.enabled) {
12459 PIPE_CONF_CHECK_X(pch_pfit.pos);
12460 PIPE_CONF_CHECK_X(pch_pfit.size);
12461 }
fd4daa9c 12462 }
2fa2fe9a 12463
a1b2278e
CK		 12464 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12465
e59150dc
JB		 12466 /* BDW+ don't expose a synchronous way to read the state */
12467 if (IS_HASWELL(dev))
12468 PIPE_CONF_CHECK_I(ips_enabled);
42db64ef 12469
282740f7
VS		 12470 PIPE_CONF_CHECK_I(double_wide);
12471
26804afd
DV		 12472 PIPE_CONF_CHECK_X(ddi_pll_sel);
12473
c0d43d62 12474 PIPE_CONF_CHECK_I(shared_dpll);
66e985c0 12475 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8bcc2795 12476 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
66e985c0
DV		 12477 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12478 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
d452c5b6 12479 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
3f4cd19f
DL		 12480 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12481 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12482 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
c0d43d62 12483
42571aef
VS		 12484 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12485 PIPE_CONF_CHECK_I(pipe_bpp);
12486
2d112de7 12487 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
a9a7e98a 12488 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
5e550656 12489
66e985c0 12490#undef PIPE_CONF_CHECK_X
08a24034 12491#undef PIPE_CONF_CHECK_I
b95af8be 12492#undef PIPE_CONF_CHECK_I_ALT
1bd1bd80 12493#undef PIPE_CONF_CHECK_FLAGS
5e550656 12494#undef PIPE_CONF_CHECK_CLOCK_FUZZY
bb760063 12495#undef PIPE_CONF_QUIRK
cfb23ed6 12496#undef INTEL_ERR_OR_DBG_KMS
88adfff1 12497
cfb23ed6 12498 return ret;
0e8ffe1b
DV		 12499}
12500
08db6652
DL		 12501static void check_wm_state(struct drm_device *dev)
12502{
12503 struct drm_i915_private *dev_priv = dev->dev_private;
12504 struct skl_ddb_allocation hw_ddb, *sw_ddb;
12505 struct intel_crtc *intel_crtc;
12506 int plane;
12507
12508 if (INTEL_INFO(dev)->gen < 9)
12509 return;
12510
12511 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12512 sw_ddb = &dev_priv->wm.skl_hw.ddb;
12513
12514 for_each_intel_crtc(dev, intel_crtc) {
12515 struct skl_ddb_entry *hw_entry, *sw_entry;
12516 const enum pipe pipe = intel_crtc->pipe;
12517
12518 if (!intel_crtc->active)
12519 continue;
12520
12521 /* planes */
dd740780 12522 for_each_plane(dev_priv, pipe, plane) {
08db6652
DL		 12523 hw_entry = &hw_ddb.plane[pipe][plane];
12524 sw_entry = &sw_ddb->plane[pipe][plane];
12525
12526 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12527 continue;
12528
12529 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12530 "(expected (%u,%u), found (%u,%u))\n",
12531 pipe_name(pipe), plane + 1,
12532 sw_entry->start, sw_entry->end,
12533 hw_entry->start, hw_entry->end);
12534 }
12535
12536 /* cursor */
12537 hw_entry = &hw_ddb.cursor[pipe];
12538 sw_entry = &sw_ddb->cursor[pipe];
12539
12540 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12541 continue;
12542
12543 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12544 "(expected (%u,%u), found (%u,%u))\n",
12545 pipe_name(pipe),
12546 sw_entry->start, sw_entry->end,
12547 hw_entry->start, hw_entry->end);
12548 }
12549}
12550
91d1b4bd 12551static void
35dd3c64
ML		 12552check_connector_state(struct drm_device *dev,
12553 struct drm_atomic_state *old_state)
8af6cf88 12554{
35dd3c64
ML		 12555 struct drm_connector_state *old_conn_state;
12556 struct drm_connector *connector;
12557 int i;
8af6cf88 12558
35dd3c64
ML		 12559 for_each_connector_in_state(old_state, connector, old_conn_state, i) {
12560 struct drm_encoder *encoder = connector->encoder;
12561 struct drm_connector_state *state = connector->state;
ad3c558f 12562
8af6cf88
DV		 12563 /* This also checks the encoder/connector hw state with the
12564 * ->get_hw_state callbacks. */
35dd3c64 12565 intel_connector_check_state(to_intel_connector(connector));
8af6cf88 12566
ad3c558f 12567 I915_STATE_WARN(state->best_encoder != encoder,
35dd3c64 12568 "connector's atomic encoder doesn't match legacy encoder\n");
8af6cf88 12569 }
91d1b4bd
DV		 12570}
12571
12572static void
12573check_encoder_state(struct drm_device *dev)
12574{
12575 struct intel_encoder *encoder;
12576 struct intel_connector *connector;
8af6cf88 12577
b2784e15 12578 for_each_intel_encoder(dev, encoder) {
8af6cf88 12579 bool enabled = false;
4d20cd86 12580 enum pipe pipe;
8af6cf88
DV		 12581
12582 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12583 encoder->base.base.id,
8e329a03 12584 encoder->base.name);
8af6cf88 12585
3a3371ff 12586 for_each_intel_connector(dev, connector) {
4d20cd86 12587 if (connector->base.state->best_encoder != &encoder->base)
8af6cf88
DV		 12588 continue;
12589 enabled = true;
ad3c558f
ML		 12590
12591 I915_STATE_WARN(connector->base.state->crtc !=
12592 encoder->base.crtc,
12593 "connector's crtc doesn't match encoder crtc\n");
8af6cf88 12594 }
0e32b39c 12595
e2c719b7 12596 I915_STATE_WARN(!!encoder->base.crtc != enabled,
8af6cf88
DV		 12597 "encoder's enabled state mismatch "
12598 "(expected %i, found %i)\n",
12599 !!encoder->base.crtc, enabled);
7c60d198
ML		 12600
12601 if (!encoder->base.crtc) {
4d20cd86 12602 bool active;
7c60d198 12603
4d20cd86
ML		 12604 active = encoder->get_hw_state(encoder, &pipe);
12605 I915_STATE_WARN(active,
12606 "encoder detached but still enabled on pipe %c.\n",
12607 pipe_name(pipe));
7c60d198 12608 }
8af6cf88 12609 }
91d1b4bd
DV		 12610}
12611
12612static void
4d20cd86 12613check_crtc_state(struct drm_device *dev, struct drm_atomic_state *old_state)
91d1b4bd 12614{
fbee40df 12615 struct drm_i915_private *dev_priv = dev->dev_private;
91d1b4bd 12616 struct intel_encoder *encoder;
4d20cd86
ML		 12617 struct drm_crtc_state *old_crtc_state;
12618 struct drm_crtc *crtc;
12619 int i;
8af6cf88 12620
4d20cd86
ML		 12621 for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) {
12622 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12623 struct intel_crtc_state *pipe_config, *sw_config;
7b89b8de 12624 bool active;
8af6cf88 12625
bfd16b2a
ML		 12626 if (!needs_modeset(crtc->state) &&
12627 !to_intel_crtc_state(crtc->state)->update_pipe)
4d20cd86 12628 continue;
045ac3b5 12629
4d20cd86
ML		 12630 __drm_atomic_helper_crtc_destroy_state(crtc, old_crtc_state);
12631 pipe_config = to_intel_crtc_state(old_crtc_state);
12632 memset(pipe_config, 0, sizeof(*pipe_config));
12633 pipe_config->base.crtc = crtc;
12634 pipe_config->base.state = old_state;
8af6cf88 12635
4d20cd86
ML		 12636 DRM_DEBUG_KMS("[CRTC:%d]\n",
12637 crtc->base.id);
8af6cf88 12638
4d20cd86
ML		 12639 active = dev_priv->display.get_pipe_config(intel_crtc,
12640 pipe_config);
d62cf62a 12641
b6b5d049 12642 /* hw state is inconsistent with the pipe quirk */
4d20cd86
ML		 12643 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12644 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12645 active = crtc->state->active;
6c49f241 12646
4d20cd86 12647 I915_STATE_WARN(crtc->state->active != active,
0e8ffe1b 12648 "crtc active state doesn't match with hw state "
4d20cd86 12649 "(expected %i, found %i)\n", crtc->state->active, active);
0e8ffe1b 12650
4d20cd86 12651 I915_STATE_WARN(intel_crtc->active != crtc->state->active,
53d9f4e9 12652 "transitional active state does not match atomic hw state "
4d20cd86
ML		 12653 "(expected %i, found %i)\n", crtc->state->active, intel_crtc->active);
12654
12655 for_each_encoder_on_crtc(dev, crtc, encoder) {
12656 enum pipe pipe;
12657
12658 active = encoder->get_hw_state(encoder, &pipe);
12659 I915_STATE_WARN(active != crtc->state->active,
12660 "[ENCODER:%i] active %i with crtc active %i\n",
12661 encoder->base.base.id, active, crtc->state->active);
12662
12663 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
12664 "Encoder connected to wrong pipe %c\n",
12665 pipe_name(pipe));
12666
12667 if (active)
12668 encoder->get_config(encoder, pipe_config);
12669 }
53d9f4e9 12670
4d20cd86 12671 if (!crtc->state->active)
cfb23ed6
ML		 12672 continue;
12673
4d20cd86
ML		 12674 sw_config = to_intel_crtc_state(crtc->state);
12675 if (!intel_pipe_config_compare(dev, sw_config,
12676 pipe_config, false)) {
e2c719b7 12677 I915_STATE_WARN(1, "pipe state doesn't match!\n");
4d20cd86 12678 intel_dump_pipe_config(intel_crtc, pipe_config,
c0b03411 12679 "[hw state]");
4d20cd86 12680 intel_dump_pipe_config(intel_crtc, sw_config,
c0b03411
DV		 12681 "[sw state]");
12682 }
8af6cf88
DV		 12683 }
12684}
12685
91d1b4bd
DV		 12686static void
12687check_shared_dpll_state(struct drm_device *dev)
12688{
fbee40df 12689 struct drm_i915_private *dev_priv = dev->dev_private;
91d1b4bd
DV		 12690 struct intel_crtc *crtc;
12691 struct intel_dpll_hw_state dpll_hw_state;
12692 int i;
5358901f
DV		 12693
12694 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12695 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12696 int enabled_crtcs = 0, active_crtcs = 0;
12697 bool active;
12698
12699 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12700
12701 DRM_DEBUG_KMS("%s\n", pll->name);
12702
12703 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
12704
e2c719b7 12705 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
5358901f 12706 "more active pll users than references: %i vs %i\n",
3e369b76 12707 pll->active, hweight32(pll->config.crtc_mask));
e2c719b7 12708 I915_STATE_WARN(pll->active && !pll->on,
5358901f 12709 "pll in active use but not on in sw tracking\n");
e2c719b7 12710 I915_STATE_WARN(pll->on && !pll->active,
35c95375 12711 "pll in on but not on in use in sw tracking\n");
e2c719b7 12712 I915_STATE_WARN(pll->on != active,
5358901f
DV		 12713 "pll on state mismatch (expected %i, found %i)\n",
12714 pll->on, active);
12715
d3fcc808 12716 for_each_intel_crtc(dev, crtc) {
83d65738 12717 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
5358901f
DV		 12718 enabled_crtcs++;
12719 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12720 active_crtcs++;
12721 }
e2c719b7 12722 I915_STATE_WARN(pll->active != active_crtcs,
5358901f
DV		 12723 "pll active crtcs mismatch (expected %i, found %i)\n",
12724 pll->active, active_crtcs);
e2c719b7 12725 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
5358901f 12726 "pll enabled crtcs mismatch (expected %i, found %i)\n",
3e369b76 12727 hweight32(pll->config.crtc_mask), enabled_crtcs);
66e985c0 12728
e2c719b7 12729 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
66e985c0
DV		 12730 sizeof(dpll_hw_state)),
12731 "pll hw state mismatch\n");
5358901f 12732 }
8af6cf88
DV		 12733}
12734
ee165b1a
ML		 12735static void
12736intel_modeset_check_state(struct drm_device *dev,
12737 struct drm_atomic_state *old_state)
91d1b4bd 12738{
08db6652 12739 check_wm_state(dev);
35dd3c64 12740 check_connector_state(dev, old_state);
91d1b4bd 12741 check_encoder_state(dev);
4d20cd86 12742 check_crtc_state(dev, old_state);
91d1b4bd
DV		 12743 check_shared_dpll_state(dev);
12744}
12745
5cec258b 12746void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
18442d08
VS		 12747 int dotclock)
12748{
12749 /*
12750 * FDI already provided one idea for the dotclock.
12751 * Yell if the encoder disagrees.
12752 */
2d112de7 12753 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
18442d08 12754 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
2d112de7 12755 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
18442d08
VS		 12756}
12757
80715b2f
VS		 12758static void update_scanline_offset(struct intel_crtc *crtc)
12759{
12760 struct drm_device *dev = crtc->base.dev;
12761
12762 /*
12763 * The scanline counter increments at the leading edge of hsync.
12764 *
12765 * On most platforms it starts counting from vtotal-1 on the
12766 * first active line. That means the scanline counter value is
12767 * always one less than what we would expect. Ie. just after
12768 * start of vblank, which also occurs at start of hsync (on the
12769 * last active line), the scanline counter will read vblank_start-1.
12770 *
12771 * On gen2 the scanline counter starts counting from 1 instead
12772 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12773 * to keep the value positive), instead of adding one.
12774 *
12775 * On HSW+ the behaviour of the scanline counter depends on the output
12776 * type. For DP ports it behaves like most other platforms, but on HDMI
12777 * there's an extra 1 line difference. So we need to add two instead of
12778 * one to the value.
12779 */
12780 if (IS_GEN2(dev)) {
6e3c9717 12781 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
80715b2f
VS		 12782 int vtotal;
12783
12784 vtotal = mode->crtc_vtotal;
12785 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
12786 vtotal /= 2;
12787
12788 crtc->scanline_offset = vtotal - 1;
12789 } else if (HAS_DDI(dev) &&
409ee761 12790 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
80715b2f
VS		 12791 crtc->scanline_offset = 2;
12792 } else
12793 crtc->scanline_offset = 1;
12794}
12795
ad421372 12796static void intel_modeset_clear_plls(struct drm_atomic_state *state)
ed6739ef 12797{
225da59b 12798 struct drm_device *dev = state->dev;
ed6739ef 12799 struct drm_i915_private *dev_priv = to_i915(dev);
ad421372 12800 struct intel_shared_dpll_config *shared_dpll = NULL;
ed6739ef 12801 struct intel_crtc *intel_crtc;
0a9ab303
ACO		 12802 struct intel_crtc_state *intel_crtc_state;
12803 struct drm_crtc *crtc;
12804 struct drm_crtc_state *crtc_state;
0a9ab303 12805 int i;
ed6739ef
ACO		 12806
12807 if (!dev_priv->display.crtc_compute_clock)
ad421372 12808 return;
ed6739ef 12809
0a9ab303 12810 for_each_crtc_in_state(state, crtc, crtc_state, i) {
ad421372
ML		 12811 int dpll;
12812
0a9ab303 12813 intel_crtc = to_intel_crtc(crtc);
4978cc93 12814 intel_crtc_state = to_intel_crtc_state(crtc_state);
ad421372 12815 dpll = intel_crtc_state->shared_dpll;
0a9ab303 12816
ad421372 12817 if (!needs_modeset(crtc_state) || dpll == DPLL_ID_PRIVATE)
225da59b
ACO		 12818 continue;
12819
ad421372 12820 intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
0a9ab303 12821
ad421372
ML		 12822 if (!shared_dpll)
12823 shared_dpll = intel_atomic_get_shared_dpll_state(state);
ed6739ef 12824
ad421372
ML		 12825 shared_dpll[dpll].crtc_mask &= ~(1 << intel_crtc->pipe);
12826 }
ed6739ef
ACO		 12827}
12828
99d736a2
ML		 12829/*
12830 * This implements the workaround described in the "notes" section of the mode
12831 * set sequence documentation. When going from no pipes or single pipe to
12832 * multiple pipes, and planes are enabled after the pipe, we need to wait at
12833 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
12834 */
12835static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
12836{
12837 struct drm_crtc_state *crtc_state;
12838 struct intel_crtc *intel_crtc;
12839 struct drm_crtc *crtc;
12840 struct intel_crtc_state *first_crtc_state = NULL;
12841 struct intel_crtc_state *other_crtc_state = NULL;
12842 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
12843 int i;
12844
12845 /* look at all crtc's that are going to be enabled in during modeset */
12846 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12847 intel_crtc = to_intel_crtc(crtc);
12848
12849 if (!crtc_state->active || !needs_modeset(crtc_state))
12850 continue;
12851
12852 if (first_crtc_state) {
12853 other_crtc_state = to_intel_crtc_state(crtc_state);
12854 break;
12855 } else {
12856 first_crtc_state = to_intel_crtc_state(crtc_state);
12857 first_pipe = intel_crtc->pipe;
12858 }
12859 }
12860
12861 /* No workaround needed? */
12862 if (!first_crtc_state)
12863 return 0;
12864
12865 /* w/a possibly needed, check how many crtc's are already enabled. */
12866 for_each_intel_crtc(state->dev, intel_crtc) {
12867 struct intel_crtc_state *pipe_config;
12868
12869 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
12870 if (IS_ERR(pipe_config))
12871 return PTR_ERR(pipe_config);
12872
12873 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
12874
12875 if (!pipe_config->base.active ||
12876 needs_modeset(&pipe_config->base))
12877 continue;
12878
12879 /* 2 or more enabled crtcs means no need for w/a */
12880 if (enabled_pipe != INVALID_PIPE)
12881 return 0;
12882
12883 enabled_pipe = intel_crtc->pipe;
12884 }
12885
12886 if (enabled_pipe != INVALID_PIPE)
12887 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
12888 else if (other_crtc_state)
12889 other_crtc_state->hsw_workaround_pipe = first_pipe;
12890
12891 return 0;
12892}
12893
27c329ed
ML		 12894static int intel_modeset_all_pipes(struct drm_atomic_state *state)
12895{
12896 struct drm_crtc *crtc;
12897 struct drm_crtc_state *crtc_state;
12898 int ret = 0;
12899
12900 /* add all active pipes to the state */
12901 for_each_crtc(state->dev, crtc) {
12902 crtc_state = drm_atomic_get_crtc_state(state, crtc);
12903 if (IS_ERR(crtc_state))
12904 return PTR_ERR(crtc_state);
12905
12906 if (!crtc_state->active || needs_modeset(crtc_state))
12907 continue;
12908
12909 crtc_state->mode_changed = true;
12910
12911 ret = drm_atomic_add_affected_connectors(state, crtc);
12912 if (ret)
12913 break;
12914
12915 ret = drm_atomic_add_affected_planes(state, crtc);
12916 if (ret)
12917 break;
12918 }
12919
12920 return ret;
12921}
12922
c347a676 12923static int intel_modeset_checks(struct drm_atomic_state *state)
054518dd
ACO		 12924{
12925 struct drm_device *dev = state->dev;
27c329ed 12926 struct drm_i915_private *dev_priv = dev->dev_private;
054518dd
ACO		 12927 int ret;
12928
b359283a
ML		 12929 if (!check_digital_port_conflicts(state)) {
12930 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
12931 return -EINVAL;
12932 }
12933
054518dd
ACO		 12934 /*
12935 * See if the config requires any additional preparation, e.g.
12936 * to adjust global state with pipes off. We need to do this
12937 * here so we can get the modeset_pipe updated config for the new
12938 * mode set on this crtc. For other crtcs we need to use the
12939 * adjusted_mode bits in the crtc directly.
12940 */
27c329ed
ML		 12941 if (dev_priv->display.modeset_calc_cdclk) {
12942 unsigned int cdclk;
b432e5cf 12943
27c329ed
ML		 12944 ret = dev_priv->display.modeset_calc_cdclk(state);
12945
12946 cdclk = to_intel_atomic_state(state)->cdclk;
12947 if (!ret && cdclk != dev_priv->cdclk_freq)
12948 ret = intel_modeset_all_pipes(state);
12949
12950 if (ret < 0)
054518dd 12951 return ret;
27c329ed
ML		 12952 } else
12953 to_intel_atomic_state(state)->cdclk = dev_priv->cdclk_freq;
054518dd 12954
ad421372 12955 intel_modeset_clear_plls(state);
054518dd 12956
99d736a2 12957 if (IS_HASWELL(dev))
ad421372 12958 return haswell_mode_set_planes_workaround(state);
99d736a2 12959
ad421372 12960 return 0;
c347a676
ACO		 12961}
12962
74c090b1
ML		 12963/**
12964 * intel_atomic_check - validate state object
12965 * @dev: drm device
12966 * @state: state to validate
12967 */
12968static int intel_atomic_check(struct drm_device *dev,
12969 struct drm_atomic_state *state)
c347a676
ACO		 12970{
12971 struct drm_crtc *crtc;
12972 struct drm_crtc_state *crtc_state;
12973 int ret, i;
61333b60 12974 bool any_ms = false;
c347a676 12975
74c090b1 12976 ret = drm_atomic_helper_check_modeset(dev, state);
054518dd
ACO		 12977 if (ret)
12978 return ret;
12979
c347a676 12980 for_each_crtc_in_state(state, crtc, crtc_state, i) {
cfb23ed6
ML		 12981 struct intel_crtc_state *pipe_config =
12982 to_intel_crtc_state(crtc_state);
1ed51de9
DV		 12983
12984 /* Catch I915_MODE_FLAG_INHERITED */
12985 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
12986 crtc_state->mode_changed = true;
cfb23ed6 12987
61333b60
ML		 12988 if (!crtc_state->enable) {
12989 if (needs_modeset(crtc_state))
12990 any_ms = true;
c347a676 12991 continue;
61333b60 12992 }
c347a676 12993
26495481 12994 if (!needs_modeset(crtc_state))
cfb23ed6
ML		 12995 continue;
12996
26495481
DV		 12997 /* FIXME: For only active_changed we shouldn't need to do any
12998 * state recomputation at all. */
12999
1ed51de9
DV		 13000 ret = drm_atomic_add_affected_connectors(state, crtc);
13001 if (ret)
13002 return ret;
b359283a 13003
cfb23ed6 13004 ret = intel_modeset_pipe_config(crtc, pipe_config);
c347a676
ACO		 13005 if (ret)
13006 return ret;
13007
6764e9f8 13008 if (intel_pipe_config_compare(state->dev,
cfb23ed6 13009 to_intel_crtc_state(crtc->state),
1ed51de9 13010 pipe_config, true)) {
26495481 13011 crtc_state->mode_changed = false;
bfd16b2a 13012 to_intel_crtc_state(crtc_state)->update_pipe = true;
26495481
DV		 13013 }
13014
13015 if (needs_modeset(crtc_state)) {
13016 any_ms = true;
cfb23ed6
ML		 13017
13018 ret = drm_atomic_add_affected_planes(state, crtc);
13019 if (ret)
13020 return ret;
13021 }
61333b60 13022
26495481
DV		 13023 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
13024 needs_modeset(crtc_state) ?
13025 "[modeset]" : "[fastset]");
c347a676
ACO		 13026 }
13027
61333b60
ML		 13028 if (any_ms) {
13029 ret = intel_modeset_checks(state);
13030
13031 if (ret)
13032 return ret;
27c329ed
ML		 13033 } else
13034 to_intel_atomic_state(state)->cdclk =
13035 to_i915(state->dev)->cdclk_freq;
c347a676
ACO		 13036
13037 return drm_atomic_helper_check_planes(state->dev, state);
054518dd
ACO		 13038}
13039
74c090b1
ML		 13040/**
13041 * intel_atomic_commit - commit validated state object
13042 * @dev: DRM device
13043 * @state: the top-level driver state object
13044 * @async: asynchronous commit
13045 *
13046 * This function commits a top-level state object that has been validated
13047 * with drm_atomic_helper_check().
13048 *
13049 * FIXME: Atomic modeset support for i915 is not yet complete. At the moment
13050 * we can only handle plane-related operations and do not yet support
13051 * asynchronous commit.
13052 *
13053 * RETURNS
13054 * Zero for success or -errno.
13055 */
13056static int intel_atomic_commit(struct drm_device *dev,
13057 struct drm_atomic_state *state,
13058 bool async)
a6778b3c 13059{
fbee40df 13060 struct drm_i915_private *dev_priv = dev->dev_private;
0a9ab303
ACO		 13061 struct drm_crtc *crtc;
13062 struct drm_crtc_state *crtc_state;
c0c36b94 13063 int ret = 0;
0a9ab303 13064 int i;
61333b60 13065 bool any_ms = false;
a6778b3c 13066
74c090b1
ML		 13067 if (async) {
13068 DRM_DEBUG_KMS("i915 does not yet support async commit\n");
13069 return -EINVAL;
13070 }
13071
d4afb8cc
ACO		 13072 ret = drm_atomic_helper_prepare_planes(dev, state);
13073 if (ret)
13074 return ret;
13075
1c5e19f8
ML		 13076 drm_atomic_helper_swap_state(dev, state);
13077
0a9ab303 13078 for_each_crtc_in_state(state, crtc, crtc_state, i) {
a539205a
ML		 13079 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13080
61333b60
ML		 13081 if (!needs_modeset(crtc->state))
13082 continue;
13083
13084 any_ms = true;
a539205a 13085 intel_pre_plane_update(intel_crtc);
460da916 13086
a539205a
ML		 13087 if (crtc_state->active) {
13088 intel_crtc_disable_planes(crtc, crtc_state->plane_mask);
13089 dev_priv->display.crtc_disable(crtc);
eddfcbcd
ML		 13090 intel_crtc->active = false;
13091 intel_disable_shared_dpll(intel_crtc);
a539205a 13092 }
b8cecdf5 13093 }
7758a113 13094
ea9d758d
DV		 13095 /* Only after disabling all output pipelines that will be changed can we
13096 * update the the output configuration. */
4740b0f2 13097 intel_modeset_update_crtc_state(state);
f6e5b160 13098
4740b0f2
ML		 13099 if (any_ms) {
13100 intel_shared_dpll_commit(state);
13101
13102 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
61333b60 13103 modeset_update_crtc_power_domains(state);
4740b0f2 13104 }
47fab737 13105
a6778b3c 13106 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
0a9ab303 13107 for_each_crtc_in_state(state, crtc, crtc_state, i) {
f6ac4b2a
ML		 13108 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13109 bool modeset = needs_modeset(crtc->state);
bfd16b2a
ML		 13110 bool update_pipe = !modeset &&
13111 to_intel_crtc_state(crtc->state)->update_pipe;
13112 unsigned long put_domains = 0;
f6ac4b2a
ML		 13113
13114 if (modeset && crtc->state->active) {
a539205a
ML		 13115 update_scanline_offset(to_intel_crtc(crtc));
13116 dev_priv->display.crtc_enable(crtc);
13117 }
80715b2f 13118
bfd16b2a
ML		 13119 if (update_pipe) {
13120 put_domains = modeset_get_crtc_power_domains(crtc);
13121
13122 /* make sure intel_modeset_check_state runs */
13123 any_ms = true;
13124 }
13125
f6ac4b2a
ML		 13126 if (!modeset)
13127 intel_pre_plane_update(intel_crtc);
13128
a539205a 13129 drm_atomic_helper_commit_planes_on_crtc(crtc_state);
bfd16b2a
ML		 13130
13131 if (put_domains)
13132 modeset_put_power_domains(dev_priv, put_domains);
13133
f6ac4b2a 13134 intel_post_plane_update(intel_crtc);
80715b2f 13135 }
a6778b3c 13136
a6778b3c 13137 /* FIXME: add subpixel order */
83a57153 13138
74c090b1 13139 drm_atomic_helper_wait_for_vblanks(dev, state);
d4afb8cc 13140 drm_atomic_helper_cleanup_planes(dev, state);
2bfb4627 13141
74c090b1 13142 if (any_ms)
ee165b1a
ML		 13143 intel_modeset_check_state(dev, state);
13144
13145 drm_atomic_state_free(state);
f30da187 13146
74c090b1 13147 return 0;
7f27126e
JB		 13148}
13149
c0c36b94
CW		 13150void intel_crtc_restore_mode(struct drm_crtc *crtc)
13151{
83a57153
ACO		 13152 struct drm_device *dev = crtc->dev;
13153 struct drm_atomic_state *state;
e694eb02 13154 struct drm_crtc_state *crtc_state;
2bfb4627 13155 int ret;
83a57153
ACO		 13156
13157 state = drm_atomic_state_alloc(dev);
13158 if (!state) {
e694eb02 13159 DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory",
83a57153
ACO		 13160 crtc->base.id);
13161 return;
13162 }
13163
e694eb02 13164 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
83a57153 13165
e694eb02
ML		 13166retry:
13167 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13168 ret = PTR_ERR_OR_ZERO(crtc_state);
13169 if (!ret) {
13170 if (!crtc_state->active)
13171 goto out;
83a57153 13172
e694eb02 13173 crtc_state->mode_changed = true;
74c090b1 13174 ret = drm_atomic_commit(state);
83a57153
ACO		 13175 }
13176
e694eb02
ML		 13177 if (ret == -EDEADLK) {
13178 drm_atomic_state_clear(state);
13179 drm_modeset_backoff(state->acquire_ctx);
13180 goto retry;
4ed9fb37 13181 }
4be07317 13182
2bfb4627 13183 if (ret)
e694eb02 13184out:
2bfb4627 13185 drm_atomic_state_free(state);
c0c36b94
CW		 13186}
13187
25c5b266
DV		 13188#undef for_each_intel_crtc_masked
13189
f6e5b160 13190static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160 13191 .gamma_set = intel_crtc_gamma_set,
74c090b1 13192 .set_config = drm_atomic_helper_set_config,
f6e5b160
CW		 13193 .destroy = intel_crtc_destroy,
13194 .page_flip = intel_crtc_page_flip,
1356837e
MR		 13195 .atomic_duplicate_state = intel_crtc_duplicate_state,
13196 .atomic_destroy_state = intel_crtc_destroy_state,
f6e5b160
CW		 13197};
13198
5358901f
DV		 13199static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
13200 struct intel_shared_dpll *pll,
13201 struct intel_dpll_hw_state *hw_state)
ee7b9f93 13202{
5358901f 13203 uint32_t val;
ee7b9f93 13204
f458ebbc 13205 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
bd2bb1b9
PZ		 13206 return false;
13207
5358901f 13208 val = I915_READ(PCH_DPLL(pll->id));
66e985c0
DV		 13209 hw_state->dpll = val;
13210 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
13211 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
5358901f
DV		 13212
13213 return val & DPLL_VCO_ENABLE;
13214}
13215
15bdd4cf
DV		 13216static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
13217 struct intel_shared_dpll *pll)
13218{
3e369b76
ACO		 13219 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
13220 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
15bdd4cf
DV		 13221}
13222
e7b903d2
DV		 13223static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
13224 struct intel_shared_dpll *pll)
13225{
e7b903d2 13226 /* PCH refclock must be enabled first */
89eff4be 13227 ibx_assert_pch_refclk_enabled(dev_priv);
e7b903d2 13228
3e369b76 13229 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
15bdd4cf
DV		 13230
13231 /* Wait for the clocks to stabilize. */
13232 POSTING_READ(PCH_DPLL(pll->id));
13233 udelay(150);
13234
13235 /* The pixel multiplier can only be updated once the
13236 * DPLL is enabled and the clocks are stable.
13237 *
13238 * So write it again.
13239 */
3e369b76 13240 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
15bdd4cf 13241 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 13242 udelay(200);
13243}
13244
13245static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
13246 struct intel_shared_dpll *pll)
13247{
13248 struct drm_device *dev = dev_priv->dev;
13249 struct intel_crtc *crtc;
e7b903d2
DV		 13250
13251 /* Make sure no transcoder isn't still depending on us. */
d3fcc808 13252 for_each_intel_crtc(dev, crtc) {
e7b903d2
DV		 13253 if (intel_crtc_to_shared_dpll(crtc) == pll)
13254 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
ee7b9f93
JB		 13255 }
13256
15bdd4cf
DV		 13257 I915_WRITE(PCH_DPLL(pll->id), 0);
13258 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 13259 udelay(200);
13260}
13261
46edb027
DV		 13262static char *ibx_pch_dpll_names[] = {
13263 "PCH DPLL A",
13264 "PCH DPLL B",
13265};
13266
7c74ade1 13267static void ibx_pch_dpll_init(struct drm_device *dev)
ee7b9f93 13268{
e7b903d2 13269 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93
JB		 13270 int i;
13271
7c74ade1 13272 dev_priv->num_shared_dpll = 2;
ee7b9f93 13273
e72f9fbf 13274 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
46edb027
DV		 13275 dev_priv->shared_dplls[i].id = i;
13276 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
15bdd4cf 13277 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
e7b903d2
DV		 13278 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
13279 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
5358901f
DV		 13280 dev_priv->shared_dplls[i].get_hw_state =
13281 ibx_pch_dpll_get_hw_state;
ee7b9f93
JB		 13282 }
13283}
13284
7c74ade1
DV		 13285static void intel_shared_dpll_init(struct drm_device *dev)
13286{
e7b903d2 13287 struct drm_i915_private *dev_priv = dev->dev_private;
7c74ade1 13288
b6283055
VS		 13289 intel_update_cdclk(dev);
13290
9cd86933
DV		 13291 if (HAS_DDI(dev))
13292 intel_ddi_pll_init(dev);
13293 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7c74ade1
DV		 13294 ibx_pch_dpll_init(dev);
13295 else
13296 dev_priv->num_shared_dpll = 0;
13297
13298 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
7c74ade1
DV		 13299}
13300
6beb8c23
MR		 13301/**
13302 * intel_prepare_plane_fb - Prepare fb for usage on plane
13303 * @plane: drm plane to prepare for
13304 * @fb: framebuffer to prepare for presentation
13305 *
13306 * Prepares a framebuffer for usage on a display plane. Generally this
13307 * involves pinning the underlying object and updating the frontbuffer tracking
13308 * bits. Some older platforms need special physical address handling for
13309 * cursor planes.
13310 *
13311 * Returns 0 on success, negative error code on failure.
13312 */
13313int
13314intel_prepare_plane_fb(struct drm_plane *plane,
d136dfee
TU		 13315 struct drm_framebuffer *fb,
13316 const struct drm_plane_state *new_state)
465c120c
MR		 13317{
13318 struct drm_device *dev = plane->dev;
6beb8c23 13319 struct intel_plane *intel_plane = to_intel_plane(plane);
6beb8c23
MR		 13320 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13321 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
6beb8c23 13322 int ret = 0;
465c120c 13323
ea2c67bb 13324 if (!obj)
465c120c
MR		 13325 return 0;
13326
6beb8c23 13327 mutex_lock(&dev->struct_mutex);
465c120c 13328
6beb8c23
MR		 13329 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13330 INTEL_INFO(dev)->cursor_needs_physical) {
13331 int align = IS_I830(dev) ? 16 * 1024 : 256;
13332 ret = i915_gem_object_attach_phys(obj, align);
13333 if (ret)
13334 DRM_DEBUG_KMS("failed to attach phys object\n");
13335 } else {
91af127f 13336 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL, NULL);
6beb8c23 13337 }
465c120c 13338
6beb8c23 13339 if (ret == 0)
a9ff8714 13340 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
fdd508a6 13341
4c34574f 13342 mutex_unlock(&dev->struct_mutex);
465c120c 13343
6beb8c23
MR		 13344 return ret;
13345}
13346
38f3ce3a
MR		 13347/**
13348 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13349 * @plane: drm plane to clean up for
13350 * @fb: old framebuffer that was on plane
13351 *
13352 * Cleans up a framebuffer that has just been removed from a plane.
13353 */
13354void
13355intel_cleanup_plane_fb(struct drm_plane *plane,
d136dfee
TU		 13356 struct drm_framebuffer *fb,
13357 const struct drm_plane_state *old_state)
38f3ce3a
MR		 13358{
13359 struct drm_device *dev = plane->dev;
13360 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13361
13362 if (WARN_ON(!obj))
13363 return;
13364
13365 if (plane->type != DRM_PLANE_TYPE_CURSOR ||
13366 !INTEL_INFO(dev)->cursor_needs_physical) {
13367 mutex_lock(&dev->struct_mutex);
82bc3b2d 13368 intel_unpin_fb_obj(fb, old_state);
38f3ce3a
MR		 13369 mutex_unlock(&dev->struct_mutex);
13370 }
465c120c
MR		 13371}
13372
6156a456
CK		 13373int
13374skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13375{
13376 int max_scale;
13377 struct drm_device *dev;
13378 struct drm_i915_private *dev_priv;
13379 int crtc_clock, cdclk;
13380
13381 if (!intel_crtc || !crtc_state)
13382 return DRM_PLANE_HELPER_NO_SCALING;
13383
13384 dev = intel_crtc->base.dev;
13385 dev_priv = dev->dev_private;
13386 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
27c329ed 13387 cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
6156a456
CK		 13388
13389 if (!crtc_clock || !cdclk)
13390 return DRM_PLANE_HELPER_NO_SCALING;
13391
13392 /*
13393 * skl max scale is lower of:
13394 * close to 3 but not 3, -1 is for that purpose
13395 * or
13396 * cdclk/crtc_clock
13397 */
13398 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13399
13400 return max_scale;
13401}
13402
465c120c 13403static int
3c692a41 13404intel_check_primary_plane(struct drm_plane *plane,
061e4b8d 13405 struct intel_crtc_state *crtc_state,
3c692a41
GP		 13406 struct intel_plane_state *state)
13407{
2b875c22
MR		 13408 struct drm_crtc *crtc = state->base.crtc;
13409 struct drm_framebuffer *fb = state->base.fb;
6156a456 13410 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
061e4b8d
ML		 13411 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13412 bool can_position = false;
465c120c 13413
061e4b8d
ML		 13414 /* use scaler when colorkey is not required */
13415 if (INTEL_INFO(plane->dev)->gen >= 9 &&
818ed961 13416 state->ckey.flags == I915_SET_COLORKEY_NONE) {
061e4b8d
ML		 13417 min_scale = 1;
13418 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
d8106366 13419 can_position = true;
6156a456 13420 }
d8106366 13421
061e4b8d
ML		 13422 return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13423 &state->dst, &state->clip,
da20eabd
ML		 13424 min_scale, max_scale,
13425 can_position, true,
13426 &state->visible);
14af293f
GP		 13427}
13428
13429static void
13430intel_commit_primary_plane(struct drm_plane *plane,
13431 struct intel_plane_state *state)
13432{
2b875c22
MR		 13433 struct drm_crtc *crtc = state->base.crtc;
13434 struct drm_framebuffer *fb = state->base.fb;
13435 struct drm_device *dev = plane->dev;
14af293f 13436 struct drm_i915_private *dev_priv = dev->dev_private;
ea2c67bb 13437 struct intel_crtc *intel_crtc;
14af293f
GP		 13438 struct drm_rect *src = &state->src;
13439
ea2c67bb
MR		 13440 crtc = crtc ? crtc : plane->crtc;
13441 intel_crtc = to_intel_crtc(crtc);
cf4c7c12
MR		 13442
13443 plane->fb = fb;
9dc806fc
MR		 13444 crtc->x = src->x1 >> 16;
13445 crtc->y = src->y1 >> 16;
ccc759dc 13446
a539205a 13447 if (!crtc->state->active)
302d19ac 13448 return;
465c120c 13449
d4b08630
ML		 13450 dev_priv->display.update_primary_plane(crtc, fb,
13451 state->src.x1 >> 16,
13452 state->src.y1 >> 16);
465c120c
MR		 13453}
13454
a8ad0d8e
ML		 13455static void
13456intel_disable_primary_plane(struct drm_plane *plane,
7fabf5ef 13457 struct drm_crtc *crtc)
a8ad0d8e
ML		 13458{
13459 struct drm_device *dev = plane->dev;
13460 struct drm_i915_private *dev_priv = dev->dev_private;
13461
a8ad0d8e
ML		 13462 dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
13463}
13464
613d2b27
ML		 13465static void intel_begin_crtc_commit(struct drm_crtc *crtc,
13466 struct drm_crtc_state *old_crtc_state)
3c692a41 13467{
32b7eeec 13468 struct drm_device *dev = crtc->dev;
3c692a41 13469 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
bfd16b2a
ML		 13470 struct intel_crtc_state *old_intel_state =
13471 to_intel_crtc_state(old_crtc_state);
13472 bool modeset = needs_modeset(crtc->state);
3c692a41 13473
f015c551 13474 if (intel_crtc->atomic.update_wm_pre)
32b7eeec 13475 intel_update_watermarks(crtc);
3c692a41 13476
c34c9ee4 13477 /* Perform vblank evasion around commit operation */
a539205a 13478 if (crtc->state->active)
34e0adbb 13479 intel_pipe_update_start(intel_crtc);
0583236e 13480
bfd16b2a
ML		 13481 if (modeset)
13482 return;
13483
13484 if (to_intel_crtc_state(crtc->state)->update_pipe)
13485 intel_update_pipe_config(intel_crtc, old_intel_state);
13486 else if (INTEL_INFO(dev)->gen >= 9)
0583236e 13487 skl_detach_scalers(intel_crtc);
32b7eeec
MR		 13488}
13489
613d2b27
ML		 13490static void intel_finish_crtc_commit(struct drm_crtc *crtc,
13491 struct drm_crtc_state *old_crtc_state)
32b7eeec 13492{
32b7eeec 13493 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
32b7eeec 13494
8f539a83 13495 if (crtc->state->active)
34e0adbb 13496 intel_pipe_update_end(intel_crtc);
3c692a41
GP		 13497}
13498
cf4c7c12 13499/**
4a3b8769
MR		 13500 * intel_plane_destroy - destroy a plane
13501 * @plane: plane to destroy
cf4c7c12 13502 *
4a3b8769
MR		 13503 * Common destruction function for all types of planes (primary, cursor,
13504 * sprite).
cf4c7c12 13505 */
4a3b8769 13506void intel_plane_destroy(struct drm_plane *plane)
465c120c
MR		 13507{
13508 struct intel_plane *intel_plane = to_intel_plane(plane);
13509 drm_plane_cleanup(plane);
13510 kfree(intel_plane);
13511}
13512
65a3fea0 13513const struct drm_plane_funcs intel_plane_funcs = {
70a101f8
MR		 13514 .update_plane = drm_atomic_helper_update_plane,
13515 .disable_plane = drm_atomic_helper_disable_plane,
3d7d6510 13516 .destroy = intel_plane_destroy,
c196e1d6 13517 .set_property = drm_atomic_helper_plane_set_property,
a98b3431
MR		 13518 .atomic_get_property = intel_plane_atomic_get_property,
13519 .atomic_set_property = intel_plane_atomic_set_property,
ea2c67bb
MR		 13520 .atomic_duplicate_state = intel_plane_duplicate_state,
13521 .atomic_destroy_state = intel_plane_destroy_state,
13522
465c120c
MR		 13523};
13524
13525static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13526 int pipe)
13527{
13528 struct intel_plane *primary;
8e7d688b 13529 struct intel_plane_state *state;
465c120c 13530 const uint32_t *intel_primary_formats;
45e3743a 13531 unsigned int num_formats;
465c120c
MR		 13532
13533 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13534 if (primary == NULL)
13535 return NULL;
13536
8e7d688b
MR		 13537 state = intel_create_plane_state(&primary->base);
13538 if (!state) {
ea2c67bb
MR		 13539 kfree(primary);
13540 return NULL;
13541 }
8e7d688b 13542 primary->base.state = &state->base;
ea2c67bb 13543
465c120c
MR		 13544 primary->can_scale = false;
13545 primary->max_downscale = 1;
6156a456
CK		 13546 if (INTEL_INFO(dev)->gen >= 9) {
13547 primary->can_scale = true;
af99ceda 13548 state->scaler_id = -1;
6156a456 13549 }
465c120c
MR		 13550 primary->pipe = pipe;
13551 primary->plane = pipe;
a9ff8714 13552 primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
c59cb179
MR		 13553 primary->check_plane = intel_check_primary_plane;
13554 primary->commit_plane = intel_commit_primary_plane;
a8ad0d8e 13555 primary->disable_plane = intel_disable_primary_plane;
465c120c
MR		 13556 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13557 primary->plane = !pipe;
13558
6c0fd451
DL		 13559 if (INTEL_INFO(dev)->gen >= 9) {
13560 intel_primary_formats = skl_primary_formats;
13561 num_formats = ARRAY_SIZE(skl_primary_formats);
13562 } else if (INTEL_INFO(dev)->gen >= 4) {
568db4f2
DL		 13563 intel_primary_formats = i965_primary_formats;
13564 num_formats = ARRAY_SIZE(i965_primary_formats);
6c0fd451
DL		 13565 } else {
13566 intel_primary_formats = i8xx_primary_formats;
13567 num_formats = ARRAY_SIZE(i8xx_primary_formats);
465c120c
MR		 13568 }
13569
13570 drm_universal_plane_init(dev, &primary->base, 0,
65a3fea0 13571 &intel_plane_funcs,
465c120c
MR		 13572 intel_primary_formats, num_formats,
13573 DRM_PLANE_TYPE_PRIMARY);
48404c1e 13574
3b7a5119
SJ		 13575 if (INTEL_INFO(dev)->gen >= 4)
13576 intel_create_rotation_property(dev, primary);
48404c1e 13577
ea2c67bb
MR		 13578 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13579
465c120c
MR		 13580 return &primary->base;
13581}
13582
3b7a5119
SJ		 13583void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13584{
13585 if (!dev->mode_config.rotation_property) {
13586 unsigned long flags = BIT(DRM_ROTATE_0) |
13587 BIT(DRM_ROTATE_180);
13588
13589 if (INTEL_INFO(dev)->gen >= 9)
13590 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13591
13592 dev->mode_config.rotation_property =
13593 drm_mode_create_rotation_property(dev, flags);
13594 }
13595 if (dev->mode_config.rotation_property)
13596 drm_object_attach_property(&plane->base.base,
13597 dev->mode_config.rotation_property,
13598 plane->base.state->rotation);
13599}
13600
3d7d6510 13601static int
852e787c 13602intel_check_cursor_plane(struct drm_plane *plane,
061e4b8d 13603 struct intel_crtc_state *crtc_state,
852e787c 13604 struct intel_plane_state *state)
3d7d6510 13605{
061e4b8d 13606 struct drm_crtc *crtc = crtc_state->base.crtc;
2b875c22 13607 struct drm_framebuffer *fb = state->base.fb;
757f9a3e 13608 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
757f9a3e
GP		 13609 unsigned stride;
13610 int ret;
3d7d6510 13611
061e4b8d
ML		 13612 ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13613 &state->dst, &state->clip,
3d7d6510
MR		 13614 DRM_PLANE_HELPER_NO_SCALING,
13615 DRM_PLANE_HELPER_NO_SCALING,
852e787c 13616 true, true, &state->visible);
757f9a3e
GP		 13617 if (ret)
13618 return ret;
13619
757f9a3e
GP		 13620 /* if we want to turn off the cursor ignore width and height */
13621 if (!obj)
da20eabd 13622 return 0;
757f9a3e 13623
757f9a3e 13624 /* Check for which cursor types we support */
061e4b8d 13625 if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
ea2c67bb
MR		 13626 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13627 state->base.crtc_w, state->base.crtc_h);
757f9a3e
GP		 13628 return -EINVAL;
13629 }
13630
ea2c67bb
MR		 13631 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13632 if (obj->base.size < stride * state->base.crtc_h) {
757f9a3e
GP		 13633 DRM_DEBUG_KMS("buffer is too small\n");
13634 return -ENOMEM;
13635 }
13636
3a656b54 13637 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
757f9a3e 13638 DRM_DEBUG_KMS("cursor cannot be tiled\n");
da20eabd 13639 return -EINVAL;
32b7eeec
MR		 13640 }
13641
da20eabd 13642 return 0;
852e787c 13643}
3d7d6510 13644
a8ad0d8e
ML		 13645static void
13646intel_disable_cursor_plane(struct drm_plane *plane,
7fabf5ef 13647 struct drm_crtc *crtc)
a8ad0d8e 13648{
a8ad0d8e
ML		 13649 intel_crtc_update_cursor(crtc, false);
13650}
13651
f4a2cf29 13652static void
852e787c
GP		 13653intel_commit_cursor_plane(struct drm_plane *plane,
13654 struct intel_plane_state *state)
13655{
2b875c22 13656 struct drm_crtc *crtc = state->base.crtc;
ea2c67bb
MR		 13657 struct drm_device *dev = plane->dev;
13658 struct intel_crtc *intel_crtc;
2b875c22 13659 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
a912f12f 13660 uint32_t addr;
852e787c 13661
ea2c67bb
MR		 13662 crtc = crtc ? crtc : plane->crtc;
13663 intel_crtc = to_intel_crtc(crtc);
13664
a912f12f
GP		 13665 if (intel_crtc->cursor_bo == obj)
13666 goto update;
4ed91096 13667
f4a2cf29 13668 if (!obj)
a912f12f 13669 addr = 0;
f4a2cf29 13670 else if (!INTEL_INFO(dev)->cursor_needs_physical)
a912f12f 13671 addr = i915_gem_obj_ggtt_offset(obj);
f4a2cf29 13672 else
a912f12f 13673 addr = obj->phys_handle->busaddr;
852e787c 13674
a912f12f
GP		 13675 intel_crtc->cursor_addr = addr;
13676 intel_crtc->cursor_bo = obj;
852e787c 13677
302d19ac 13678update:
a539205a 13679 if (crtc->state->active)
a912f12f 13680 intel_crtc_update_cursor(crtc, state->visible);
852e787c
GP		 13681}
13682
3d7d6510
MR		 13683static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
13684 int pipe)
13685{
13686 struct intel_plane *cursor;
8e7d688b 13687 struct intel_plane_state *state;
3d7d6510
MR		 13688
13689 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13690 if (cursor == NULL)
13691 return NULL;
13692
8e7d688b
MR		 13693 state = intel_create_plane_state(&cursor->base);
13694 if (!state) {
ea2c67bb
MR		 13695 kfree(cursor);
13696 return NULL;
13697 }
8e7d688b 13698 cursor->base.state = &state->base;
ea2c67bb 13699
3d7d6510
MR		 13700 cursor->can_scale = false;
13701 cursor->max_downscale = 1;
13702 cursor->pipe = pipe;
13703 cursor->plane = pipe;
a9ff8714 13704 cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
c59cb179
MR		 13705 cursor->check_plane = intel_check_cursor_plane;
13706 cursor->commit_plane = intel_commit_cursor_plane;
a8ad0d8e 13707 cursor->disable_plane = intel_disable_cursor_plane;
3d7d6510
MR		 13708
13709 drm_universal_plane_init(dev, &cursor->base, 0,
65a3fea0 13710 &intel_plane_funcs,
3d7d6510
MR		 13711 intel_cursor_formats,
13712 ARRAY_SIZE(intel_cursor_formats),
13713 DRM_PLANE_TYPE_CURSOR);
4398ad45
VS		 13714
13715 if (INTEL_INFO(dev)->gen >= 4) {
13716 if (!dev->mode_config.rotation_property)
13717 dev->mode_config.rotation_property =
13718 drm_mode_create_rotation_property(dev,
13719 BIT(DRM_ROTATE_0) |
13720 BIT(DRM_ROTATE_180));
13721 if (dev->mode_config.rotation_property)
13722 drm_object_attach_property(&cursor->base.base,
13723 dev->mode_config.rotation_property,
8e7d688b 13724 state->base.rotation);
4398ad45
VS		 13725 }
13726
af99ceda
CK		 13727 if (INTEL_INFO(dev)->gen >=9)
13728 state->scaler_id = -1;
13729
ea2c67bb
MR		 13730 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13731
3d7d6510
MR		 13732 return &cursor->base;
13733}
13734
549e2bfb
CK		 13735static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
13736 struct intel_crtc_state *crtc_state)
13737{
13738 int i;
13739 struct intel_scaler *intel_scaler;
13740 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
13741
13742 for (i = 0; i < intel_crtc->num_scalers; i++) {
13743 intel_scaler = &scaler_state->scalers[i];
13744 intel_scaler->in_use = 0;
549e2bfb
CK		 13745 intel_scaler->mode = PS_SCALER_MODE_DYN;
13746 }
13747
13748 scaler_state->scaler_id = -1;
13749}
13750
b358d0a6 13751static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 13752{
fbee40df 13753 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 13754 struct intel_crtc *intel_crtc;
f5de6e07 13755 struct intel_crtc_state *crtc_state = NULL;
3d7d6510
MR		 13756 struct drm_plane *primary = NULL;
13757 struct drm_plane *cursor = NULL;
465c120c 13758 int i, ret;
79e53945 13759
955382f3 13760 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
79e53945
JB		 13761 if (intel_crtc == NULL)
13762 return;
13763
f5de6e07
ACO		 13764 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13765 if (!crtc_state)
13766 goto fail;
550acefd
ACO		 13767 intel_crtc->config = crtc_state;
13768 intel_crtc->base.state = &crtc_state->base;
07878248 13769 crtc_state->base.crtc = &intel_crtc->base;
f5de6e07 13770
549e2bfb
CK		 13771 /* initialize shared scalers */
13772 if (INTEL_INFO(dev)->gen >= 9) {
13773 if (pipe == PIPE_C)
13774 intel_crtc->num_scalers = 1;
13775 else
13776 intel_crtc->num_scalers = SKL_NUM_SCALERS;
13777
13778 skl_init_scalers(dev, intel_crtc, crtc_state);
13779 }
13780
465c120c 13781 primary = intel_primary_plane_create(dev, pipe);
3d7d6510
MR		 13782 if (!primary)
13783 goto fail;
13784
13785 cursor = intel_cursor_plane_create(dev, pipe);
13786 if (!cursor)
13787 goto fail;
13788
465c120c 13789 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
3d7d6510
MR		 13790 cursor, &intel_crtc_funcs);
13791 if (ret)
13792 goto fail;
79e53945
JB		 13793
13794 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 13795 for (i = 0; i < 256; i++) {
13796 intel_crtc->lut_r[i] = i;
13797 intel_crtc->lut_g[i] = i;
13798 intel_crtc->lut_b[i] = i;
13799 }
13800
1f1c2e24
VS		 13801 /*
13802 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
8c0f92e1 13803 * is hooked to pipe B. Hence we want plane A feeding pipe B.
1f1c2e24 13804 */
80824003
JB		 13805 intel_crtc->pipe = pipe;
13806 intel_crtc->plane = pipe;
3a77c4c4 13807 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
28c97730 13808 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 13809 intel_crtc->plane = !pipe;
80824003
JB		 13810 }
13811
4b0e333e
CW		 13812 intel_crtc->cursor_base = ~0;
13813 intel_crtc->cursor_cntl = ~0;
dc41c154 13814 intel_crtc->cursor_size = ~0;
8d7849db 13815
852eb00d
VS		 13816 intel_crtc->wm.cxsr_allowed = true;
13817
22fd0fab
JB		 13818 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
13819 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
13820 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
13821 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
13822
79e53945 13823 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
87b6b101
DV		 13824
13825 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
3d7d6510
MR		 13826 return;
13827
13828fail:
13829 if (primary)
13830 drm_plane_cleanup(primary);
13831 if (cursor)
13832 drm_plane_cleanup(cursor);
f5de6e07 13833 kfree(crtc_state);
3d7d6510 13834 kfree(intel_crtc);
79e53945
JB		 13835}
13836
752aa88a
JB		 13837enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
13838{
13839 struct drm_encoder *encoder = connector->base.encoder;
6e9f798d 13840 struct drm_device *dev = connector->base.dev;
752aa88a 13841
51fd371b 13842 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
752aa88a 13843
d3babd3f 13844 if (!encoder || WARN_ON(!encoder->crtc))
752aa88a
JB		 13845 return INVALID_PIPE;
13846
13847 return to_intel_crtc(encoder->crtc)->pipe;
13848}
13849
08d7b3d1 13850int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 13851 struct drm_file *file)
08d7b3d1 13852{
08d7b3d1 13853 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7707e653 13854 struct drm_crtc *drmmode_crtc;
c05422d5 13855 struct intel_crtc *crtc;
08d7b3d1 13856
7707e653 13857 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
08d7b3d1 13858
7707e653 13859 if (!drmmode_crtc) {
08d7b3d1 13860 DRM_ERROR("no such CRTC id\n");
3f2c2057 13861 return -ENOENT;
08d7b3d1
CW		 13862 }
13863
7707e653 13864 crtc = to_intel_crtc(drmmode_crtc);
c05422d5 13865 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 13866
c05422d5 13867 return 0;
08d7b3d1
CW		 13868}
13869
66a9278e 13870static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 13871{
66a9278e
DV		 13872 struct drm_device *dev = encoder->base.dev;
13873 struct intel_encoder *source_encoder;
79e53945 13874 int index_mask = 0;
79e53945
JB		 13875 int entry = 0;
13876
b2784e15 13877 for_each_intel_encoder(dev, source_encoder) {
bc079e8b 13878 if (encoders_cloneable(encoder, source_encoder))
66a9278e
DV		 13879 index_mask |= (1 << entry);
13880
79e53945
JB		 13881 entry++;
13882 }
4ef69c7a 13883
79e53945
JB		 13884 return index_mask;
13885}
13886
4d302442
CW		 13887static bool has_edp_a(struct drm_device *dev)
13888{
13889 struct drm_i915_private *dev_priv = dev->dev_private;
13890
13891 if (!IS_MOBILE(dev))
13892 return false;
13893
13894 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
13895 return false;
13896
e3589908 13897 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
4d302442
CW		 13898 return false;
13899
13900 return true;
13901}
13902
84b4e042
JB		 13903static bool intel_crt_present(struct drm_device *dev)
13904{
13905 struct drm_i915_private *dev_priv = dev->dev_private;
13906
884497ed
DL		 13907 if (INTEL_INFO(dev)->gen >= 9)
13908 return false;
13909
cf404ce4 13910 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
84b4e042
JB		 13911 return false;
13912
13913 if (IS_CHERRYVIEW(dev))
13914 return false;
13915
13916 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
13917 return false;
13918
13919 return true;
13920}
13921
79e53945
JB		 13922static void intel_setup_outputs(struct drm_device *dev)
13923{
725e30ad 13924 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 13925 struct intel_encoder *encoder;
cb0953d7 13926 bool dpd_is_edp = false;
79e53945 13927
c9093354 13928 intel_lvds_init(dev);
79e53945 13929
84b4e042 13930 if (intel_crt_present(dev))
79935fca 13931 intel_crt_init(dev);
cb0953d7 13932
c776eb2e
VK		 13933 if (IS_BROXTON(dev)) {
13934 /*
13935 * FIXME: Broxton doesn't support port detection via the
13936 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
13937 * detect the ports.
13938 */
13939 intel_ddi_init(dev, PORT_A);
13940 intel_ddi_init(dev, PORT_B);
13941 intel_ddi_init(dev, PORT_C);
13942 } else if (HAS_DDI(dev)) {
0e72a5b5
ED		 13943 int found;
13944
de31facd
JB		 13945 /*
13946 * Haswell uses DDI functions to detect digital outputs.
13947 * On SKL pre-D0 the strap isn't connected, so we assume
13948 * it's there.
13949 */
0e72a5b5 13950 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
de31facd 13951 /* WaIgnoreDDIAStrap: skl */
5a2376d1 13952 if (found || IS_SKYLAKE(dev))
0e72a5b5
ED		 13953 intel_ddi_init(dev, PORT_A);
13954
13955 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
13956 * register */
13957 found = I915_READ(SFUSE_STRAP);
13958
13959 if (found & SFUSE_STRAP_DDIB_DETECTED)
13960 intel_ddi_init(dev, PORT_B);
13961 if (found & SFUSE_STRAP_DDIC_DETECTED)
13962 intel_ddi_init(dev, PORT_C);
13963 if (found & SFUSE_STRAP_DDID_DETECTED)
13964 intel_ddi_init(dev, PORT_D);
2800e4c2
RV		 13965 /*
13966 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
13967 */
13968 if (IS_SKYLAKE(dev) &&
13969 (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
13970 dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
13971 dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
13972 intel_ddi_init(dev, PORT_E);
13973
0e72a5b5 13974 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 13975 int found;
5d8a7752 13976 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
270b3042
DV		 13977
13978 if (has_edp_a(dev))
13979 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 13980
dc0fa718 13981 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 13982 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 13983 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 13984 if (!found)
e2debe91 13985 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 13986 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 13987 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 13988 }
13989
dc0fa718 13990 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 13991 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 13992
dc0fa718 13993 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 13994 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 13995
5eb08b69 13996 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 13997 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 13998
270b3042 13999 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 14000 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 14001 } else if (IS_VALLEYVIEW(dev)) {
e17ac6db
VS		 14002 /*
14003 * The DP_DETECTED bit is the latched state of the DDC
14004 * SDA pin at boot. However since eDP doesn't require DDC
14005 * (no way to plug in a DP->HDMI dongle) the DDC pins for
14006 * eDP ports may have been muxed to an alternate function.
14007 * Thus we can't rely on the DP_DETECTED bit alone to detect
14008 * eDP ports. Consult the VBT as well as DP_DETECTED to
14009 * detect eDP ports.
14010 */
d2182a66
VS		 14011 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
14012 !intel_dp_is_edp(dev, PORT_B))
585a94b8
AB		 14013 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
14014 PORT_B);
e17ac6db
VS		 14015 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
14016 intel_dp_is_edp(dev, PORT_B))
14017 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
585a94b8 14018
d2182a66
VS		 14019 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
14020 !intel_dp_is_edp(dev, PORT_C))
6f6005a5
JB		 14021 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
14022 PORT_C);
e17ac6db
VS		 14023 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
14024 intel_dp_is_edp(dev, PORT_C))
14025 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
19c03924 14026
9418c1f1 14027 if (IS_CHERRYVIEW(dev)) {
e17ac6db 14028 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
9418c1f1
VS		 14029 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
14030 PORT_D);
e17ac6db
VS		 14031 /* eDP not supported on port D, so don't check VBT */
14032 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
14033 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
9418c1f1
VS		 14034 }
14035
3cfca973 14036 intel_dsi_init(dev);
09da55dc 14037 } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
27185ae1 14038 bool found = false;
7d57382e 14039
e2debe91 14040 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 14041 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 14042 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
3fec3d2f 14043 if (!found && IS_G4X(dev)) {
b01f2c3a 14044 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 14045 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 14046 }
27185ae1 14047
3fec3d2f 14048 if (!found && IS_G4X(dev))
ab9d7c30 14049 intel_dp_init(dev, DP_B, PORT_B);
725e30ad 14050 }
13520b05
KH		 14051
14052 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 14053
e2debe91 14054 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 14055 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 14056 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 14057 }
27185ae1 14058
e2debe91 14059 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 14060
3fec3d2f 14061 if (IS_G4X(dev)) {
b01f2c3a 14062 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 14063 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a 14064 }
3fec3d2f 14065 if (IS_G4X(dev))
ab9d7c30 14066 intel_dp_init(dev, DP_C, PORT_C);
725e30ad 14067 }
27185ae1 14068
3fec3d2f 14069 if (IS_G4X(dev) &&
e7281eab 14070 (I915_READ(DP_D) & DP_DETECTED))
ab9d7c30 14071 intel_dp_init(dev, DP_D, PORT_D);
bad720ff 14072 } else if (IS_GEN2(dev))
79e53945
JB		 14073 intel_dvo_init(dev);
14074
103a196f 14075 if (SUPPORTS_TV(dev))
79e53945
JB		 14076 intel_tv_init(dev);
14077
0bc12bcb 14078 intel_psr_init(dev);
7c8f8a70 14079
b2784e15 14080 for_each_intel_encoder(dev, encoder) {
4ef69c7a
CW		 14081 encoder->base.possible_crtcs = encoder->crtc_mask;
14082 encoder->base.possible_clones =
66a9278e 14083 intel_encoder_clones(encoder);
79e53945 14084 }
47356eb6 14085
dde86e2d 14086 intel_init_pch_refclk(dev);
270b3042
DV		 14087
14088 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 14089}
14090
14091static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14092{
60a5ca01 14093 struct drm_device *dev = fb->dev;
79e53945 14094 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945 14095
ef2d633e 14096 drm_framebuffer_cleanup(fb);
60a5ca01 14097 mutex_lock(&dev->struct_mutex);
ef2d633e 14098 WARN_ON(!intel_fb->obj->framebuffer_references--);
60a5ca01
VS		 14099 drm_gem_object_unreference(&intel_fb->obj->base);
14100 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 14101 kfree(intel_fb);
14102}
14103
14104static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 14105 struct drm_file *file,
79e53945
JB		 14106 unsigned int *handle)
14107{
14108 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 14109 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 14110
05394f39 14111 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 14112}
14113
86c98588
RV		 14114static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14115 struct drm_file *file,
14116 unsigned flags, unsigned color,
14117 struct drm_clip_rect *clips,
14118 unsigned num_clips)
14119{
14120 struct drm_device *dev = fb->dev;
14121 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14122 struct drm_i915_gem_object *obj = intel_fb->obj;
14123
14124 mutex_lock(&dev->struct_mutex);
74b4ea1e 14125 intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
86c98588
RV		 14126 mutex_unlock(&dev->struct_mutex);
14127
14128 return 0;
14129}
14130
79e53945
JB		 14131static const struct drm_framebuffer_funcs intel_fb_funcs = {
14132 .destroy = intel_user_framebuffer_destroy,
14133 .create_handle = intel_user_framebuffer_create_handle,
86c98588 14134 .dirty = intel_user_framebuffer_dirty,
79e53945
JB		 14135};
14136
b321803d
DL		 14137static
14138u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14139 uint32_t pixel_format)
14140{
14141 u32 gen = INTEL_INFO(dev)->gen;
14142
14143 if (gen >= 9) {
14144 /* "The stride in bytes must not exceed the of the size of 8K
14145 * pixels and 32K bytes."
14146 */
14147 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
14148 } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
14149 return 32*1024;
14150 } else if (gen >= 4) {
14151 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14152 return 16*1024;
14153 else
14154 return 32*1024;
14155 } else if (gen >= 3) {
14156 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14157 return 8*1024;
14158 else
14159 return 16*1024;
14160 } else {
14161 /* XXX DSPC is limited to 4k tiled */
14162 return 8*1024;
14163 }
14164}
14165
b5ea642a
DV		 14166static int intel_framebuffer_init(struct drm_device *dev,
14167 struct intel_framebuffer *intel_fb,
14168 struct drm_mode_fb_cmd2 *mode_cmd,
14169 struct drm_i915_gem_object *obj)
79e53945 14170{
6761dd31 14171 unsigned int aligned_height;
79e53945 14172 int ret;
b321803d 14173 u32 pitch_limit, stride_alignment;
79e53945 14174
dd4916c5
DV		 14175 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14176
2a80eada
DV		 14177 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14178 /* Enforce that fb modifier and tiling mode match, but only for
14179 * X-tiled. This is needed for FBC. */
14180 if (!!(obj->tiling_mode == I915_TILING_X) !=
14181 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14182 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14183 return -EINVAL;
14184 }
14185 } else {
14186 if (obj->tiling_mode == I915_TILING_X)
14187 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14188 else if (obj->tiling_mode == I915_TILING_Y) {
14189 DRM_DEBUG("No Y tiling for legacy addfb\n");
14190 return -EINVAL;
14191 }
14192 }
14193
9a8f0a12
TU		 14194 /* Passed in modifier sanity checking. */
14195 switch (mode_cmd->modifier[0]) {
14196 case I915_FORMAT_MOD_Y_TILED:
14197 case I915_FORMAT_MOD_Yf_TILED:
14198 if (INTEL_INFO(dev)->gen < 9) {
14199 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14200 mode_cmd->modifier[0]);
14201 return -EINVAL;
14202 }
14203 case DRM_FORMAT_MOD_NONE:
14204 case I915_FORMAT_MOD_X_TILED:
14205 break;
14206 default:
c0f40428
JB		 14207 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14208 mode_cmd->modifier[0]);
57cd6508 14209 return -EINVAL;
c16ed4be 14210 }
57cd6508 14211
b321803d
DL		 14212 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
14213 mode_cmd->pixel_format);
14214 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14215 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14216 mode_cmd->pitches[0], stride_alignment);
57cd6508 14217 return -EINVAL;
c16ed4be 14218 }
57cd6508 14219
b321803d
DL		 14220 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14221 mode_cmd->pixel_format);
a35cdaa0 14222 if (mode_cmd->pitches[0] > pitch_limit) {
b321803d
DL		 14223 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14224 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
2a80eada 14225 "tiled" : "linear",
a35cdaa0 14226 mode_cmd->pitches[0], pitch_limit);
5d7bd705 14227 return -EINVAL;
c16ed4be 14228 }
5d7bd705 14229
2a80eada 14230 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
c16ed4be
CW		 14231 mode_cmd->pitches[0] != obj->stride) {
14232 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14233 mode_cmd->pitches[0], obj->stride);
5d7bd705 14234 return -EINVAL;
c16ed4be 14235 }
5d7bd705 14236
57779d06 14237 /* Reject formats not supported by any plane early. */
308e5bcb 14238 switch (mode_cmd->pixel_format) {
57779d06 14239 case DRM_FORMAT_C8:
04b3924d
VS		 14240 case DRM_FORMAT_RGB565:
14241 case DRM_FORMAT_XRGB8888:
14242 case DRM_FORMAT_ARGB8888:
57779d06
VS		 14243 break;
14244 case DRM_FORMAT_XRGB1555:
c16ed4be 14245 if (INTEL_INFO(dev)->gen > 3) {
4ee62c76
VS		 14246 DRM_DEBUG("unsupported pixel format: %s\n",
14247 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14248 return -EINVAL;
c16ed4be 14249 }
57779d06 14250 break;
57779d06 14251 case DRM_FORMAT_ABGR8888:
6c0fd451
DL		 14252 if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) {
14253 DRM_DEBUG("unsupported pixel format: %s\n",
14254 drm_get_format_name(mode_cmd->pixel_format));
14255 return -EINVAL;
14256 }
14257 break;
14258 case DRM_FORMAT_XBGR8888:
04b3924d 14259 case DRM_FORMAT_XRGB2101010:
57779d06 14260 case DRM_FORMAT_XBGR2101010:
c16ed4be 14261 if (INTEL_INFO(dev)->gen < 4) {
4ee62c76
VS		 14262 DRM_DEBUG("unsupported pixel format: %s\n",
14263 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14264 return -EINVAL;
c16ed4be 14265 }
b5626747 14266 break;
7531208b
DL		 14267 case DRM_FORMAT_ABGR2101010:
14268 if (!IS_VALLEYVIEW(dev)) {
14269 DRM_DEBUG("unsupported pixel format: %s\n",
14270 drm_get_format_name(mode_cmd->pixel_format));
14271 return -EINVAL;
14272 }
14273 break;
04b3924d
VS		 14274 case DRM_FORMAT_YUYV:
14275 case DRM_FORMAT_UYVY:
14276 case DRM_FORMAT_YVYU:
14277 case DRM_FORMAT_VYUY:
c16ed4be 14278 if (INTEL_INFO(dev)->gen < 5) {
4ee62c76
VS		 14279 DRM_DEBUG("unsupported pixel format: %s\n",
14280 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14281 return -EINVAL;
c16ed4be 14282 }
57cd6508
CW		 14283 break;
14284 default:
4ee62c76
VS		 14285 DRM_DEBUG("unsupported pixel format: %s\n",
14286 drm_get_format_name(mode_cmd->pixel_format));
57cd6508
CW		 14287 return -EINVAL;
14288 }
14289
90f9a336
VS		 14290 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14291 if (mode_cmd->offsets[0] != 0)
14292 return -EINVAL;
14293
ec2c981e 14294 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
091df6cb
DV		 14295 mode_cmd->pixel_format,
14296 mode_cmd->modifier[0]);
53155c0a
DV		 14297 /* FIXME drm helper for size checks (especially planar formats)? */
14298 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14299 return -EINVAL;
14300
c7d73f6a
DV		 14301 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14302 intel_fb->obj = obj;
80075d49 14303 intel_fb->obj->framebuffer_references++;
c7d73f6a 14304
79e53945
JB		 14305 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14306 if (ret) {
14307 DRM_ERROR("framebuffer init failed %d\n", ret);
14308 return ret;
14309 }
14310
79e53945
JB		 14311 return 0;
14312}
14313
79e53945
JB		 14314static struct drm_framebuffer *
14315intel_user_framebuffer_create(struct drm_device *dev,
14316 struct drm_file *filp,
308e5bcb 14317 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 14318{
05394f39 14319 struct drm_i915_gem_object *obj;
79e53945 14320
308e5bcb
JB		 14321 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14322 mode_cmd->handles[0]));
c8725226 14323 if (&obj->base == NULL)
cce13ff7 14324 return ERR_PTR(-ENOENT);
79e53945 14325
d2dff872 14326 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 14327}
14328
0695726e 14329#ifndef CONFIG_DRM_FBDEV_EMULATION
0632fef6 14330static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
4520f53a
DV		 14331{
14332}
14333#endif
14334
79e53945 14335static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 14336 .fb_create = intel_user_framebuffer_create,
0632fef6 14337 .output_poll_changed = intel_fbdev_output_poll_changed,
5ee67f1c
MR		 14338 .atomic_check = intel_atomic_check,
14339 .atomic_commit = intel_atomic_commit,
de419ab6
ML		 14340 .atomic_state_alloc = intel_atomic_state_alloc,
14341 .atomic_state_clear = intel_atomic_state_clear,
79e53945
JB		 14342};
14343
e70236a8
JB		 14344/* Set up chip specific display functions */
14345static void intel_init_display(struct drm_device *dev)
14346{
14347 struct drm_i915_private *dev_priv = dev->dev_private;
14348
ee9300bb
DV		 14349 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14350 dev_priv->display.find_dpll = g4x_find_best_dpll;
ef9348c8
CML		 14351 else if (IS_CHERRYVIEW(dev))
14352 dev_priv->display.find_dpll = chv_find_best_dpll;
ee9300bb
DV		 14353 else if (IS_VALLEYVIEW(dev))
14354 dev_priv->display.find_dpll = vlv_find_best_dpll;
14355 else if (IS_PINEVIEW(dev))
14356 dev_priv->display.find_dpll = pnv_find_best_dpll;
14357 else
14358 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14359
bc8d7dff
DL		 14360 if (INTEL_INFO(dev)->gen >= 9) {
14361 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
5724dbd1
DL		 14362 dev_priv->display.get_initial_plane_config =
14363 skylake_get_initial_plane_config;
bc8d7dff
DL		 14364 dev_priv->display.crtc_compute_clock =
14365 haswell_crtc_compute_clock;
14366 dev_priv->display.crtc_enable = haswell_crtc_enable;
14367 dev_priv->display.crtc_disable = haswell_crtc_disable;
bc8d7dff
DL		 14368 dev_priv->display.update_primary_plane =
14369 skylake_update_primary_plane;
14370 } else if (HAS_DDI(dev)) {
0e8ffe1b 14371 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
5724dbd1
DL		 14372 dev_priv->display.get_initial_plane_config =
14373 ironlake_get_initial_plane_config;
797d0259
ACO		 14374 dev_priv->display.crtc_compute_clock =
14375 haswell_crtc_compute_clock;
4f771f10
PZ		 14376 dev_priv->display.crtc_enable = haswell_crtc_enable;
14377 dev_priv->display.crtc_disable = haswell_crtc_disable;
bc8d7dff
DL		 14378 dev_priv->display.update_primary_plane =
14379 ironlake_update_primary_plane;
09b4ddf9 14380 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 14381 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
5724dbd1
DL		 14382 dev_priv->display.get_initial_plane_config =
14383 ironlake_get_initial_plane_config;
3fb37703
ACO		 14384 dev_priv->display.crtc_compute_clock =
14385 ironlake_crtc_compute_clock;
76e5a89c
DV		 14386 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14387 dev_priv->display.crtc_disable = ironlake_crtc_disable;
262ca2b0
MR		 14388 dev_priv->display.update_primary_plane =
14389 ironlake_update_primary_plane;
89b667f8
JB		 14390 } else if (IS_VALLEYVIEW(dev)) {
14391 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
5724dbd1
DL		 14392 dev_priv->display.get_initial_plane_config =
14393 i9xx_get_initial_plane_config;
d6dfee7a 14394 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
89b667f8
JB		 14395 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14396 dev_priv->display.crtc_disable = i9xx_crtc_disable;
262ca2b0
MR		 14397 dev_priv->display.update_primary_plane =
14398 i9xx_update_primary_plane;
f564048e 14399 } else {
0e8ffe1b 14400 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
5724dbd1
DL		 14401 dev_priv->display.get_initial_plane_config =
14402 i9xx_get_initial_plane_config;
d6dfee7a 14403 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
76e5a89c
DV		 14404 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14405 dev_priv->display.crtc_disable = i9xx_crtc_disable;
262ca2b0
MR		 14406 dev_priv->display.update_primary_plane =
14407 i9xx_update_primary_plane;
f564048e 14408 }
e70236a8 14409
e70236a8 14410 /* Returns the core display clock speed */
1652d19e
VS		 14411 if (IS_SKYLAKE(dev))
14412 dev_priv->display.get_display_clock_speed =
14413 skylake_get_display_clock_speed;
acd3f3d3
BP		 14414 else if (IS_BROXTON(dev))
14415 dev_priv->display.get_display_clock_speed =
14416 broxton_get_display_clock_speed;
1652d19e
VS		 14417 else if (IS_BROADWELL(dev))
14418 dev_priv->display.get_display_clock_speed =
14419 broadwell_get_display_clock_speed;
14420 else if (IS_HASWELL(dev))
14421 dev_priv->display.get_display_clock_speed =
14422 haswell_get_display_clock_speed;
14423 else if (IS_VALLEYVIEW(dev))
25eb05fc
JB		 14424 dev_priv->display.get_display_clock_speed =
14425 valleyview_get_display_clock_speed;
b37a6434
VS		 14426 else if (IS_GEN5(dev))
14427 dev_priv->display.get_display_clock_speed =
14428 ilk_get_display_clock_speed;
a7c66cd8 14429 else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
34edce2f 14430 IS_GEN6(dev) || IS_IVYBRIDGE(dev))
e70236a8
JB		 14431 dev_priv->display.get_display_clock_speed =
14432 i945_get_display_clock_speed;
34edce2f
VS		 14433 else if (IS_GM45(dev))
14434 dev_priv->display.get_display_clock_speed =
14435 gm45_get_display_clock_speed;
14436 else if (IS_CRESTLINE(dev))
14437 dev_priv->display.get_display_clock_speed =
14438 i965gm_get_display_clock_speed;
14439 else if (IS_PINEVIEW(dev))
14440 dev_priv->display.get_display_clock_speed =
14441 pnv_get_display_clock_speed;
14442 else if (IS_G33(dev) || IS_G4X(dev))
14443 dev_priv->display.get_display_clock_speed =
14444 g33_get_display_clock_speed;
e70236a8
JB		 14445 else if (IS_I915G(dev))
14446 dev_priv->display.get_display_clock_speed =
14447 i915_get_display_clock_speed;
257a7ffc 14448 else if (IS_I945GM(dev) || IS_845G(dev))
e70236a8
JB		 14449 dev_priv->display.get_display_clock_speed =
14450 i9xx_misc_get_display_clock_speed;
257a7ffc
DV		 14451 else if (IS_PINEVIEW(dev))
14452 dev_priv->display.get_display_clock_speed =
14453 pnv_get_display_clock_speed;
e70236a8
JB		 14454 else if (IS_I915GM(dev))
14455 dev_priv->display.get_display_clock_speed =
14456 i915gm_get_display_clock_speed;
14457 else if (IS_I865G(dev))
14458 dev_priv->display.get_display_clock_speed =
14459 i865_get_display_clock_speed;
f0f8a9ce 14460 else if (IS_I85X(dev))
e70236a8 14461 dev_priv->display.get_display_clock_speed =
1b1d2716 14462 i85x_get_display_clock_speed;
623e01e5
VS		 14463 else { /* 830 */
14464 WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n");
e70236a8
JB		 14465 dev_priv->display.get_display_clock_speed =
14466 i830_get_display_clock_speed;
623e01e5 14467 }
e70236a8 14468
7c10a2b5 14469 if (IS_GEN5(dev)) {
3bb11b53 14470 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
3bb11b53
SJ		 14471 } else if (IS_GEN6(dev)) {
14472 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
3bb11b53
SJ		 14473 } else if (IS_IVYBRIDGE(dev)) {
14474 /* FIXME: detect B0+ stepping and use auto training */
14475 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
059b2fe9 14476 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
3bb11b53 14477 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
27c329ed
ML		 14478 if (IS_BROADWELL(dev)) {
14479 dev_priv->display.modeset_commit_cdclk =
14480 broadwell_modeset_commit_cdclk;
14481 dev_priv->display.modeset_calc_cdclk =
14482 broadwell_modeset_calc_cdclk;
14483 }
30a970c6 14484 } else if (IS_VALLEYVIEW(dev)) {
27c329ed
ML		 14485 dev_priv->display.modeset_commit_cdclk =
14486 valleyview_modeset_commit_cdclk;
14487 dev_priv->display.modeset_calc_cdclk =
14488 valleyview_modeset_calc_cdclk;
f8437dd1 14489 } else if (IS_BROXTON(dev)) {
27c329ed
ML		 14490 dev_priv->display.modeset_commit_cdclk =
14491 broxton_modeset_commit_cdclk;
14492 dev_priv->display.modeset_calc_cdclk =
14493 broxton_modeset_calc_cdclk;
e70236a8 14494 }
8c9f3aaf 14495
8c9f3aaf
JB		 14496 switch (INTEL_INFO(dev)->gen) {
14497 case 2:
14498 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14499 break;
14500
14501 case 3:
14502 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14503 break;
14504
14505 case 4:
14506 case 5:
14507 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14508 break;
14509
14510 case 6:
14511 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14512 break;
7c9017e5 14513 case 7:
4e0bbc31 14514 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
7c9017e5
JB		 14515 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14516 break;
830c81db 14517 case 9:
ba343e02
TU		 14518 /* Drop through - unsupported since execlist only. */
14519 default:
14520 /* Default just returns -ENODEV to indicate unsupported */
14521 dev_priv->display.queue_flip = intel_default_queue_flip;
8c9f3aaf 14522 }
7bd688cd
JN		 14523
14524 intel_panel_init_backlight_funcs(dev);
e39b999a
VS		 14525
14526 mutex_init(&dev_priv->pps_mutex);
e70236a8
JB		 14527}
14528
b690e96c
JB		 14529/*
14530 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14531 * resume, or other times. This quirk makes sure that's the case for
14532 * affected systems.
14533 */
0206e353 14534static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 14535{
14536 struct drm_i915_private *dev_priv = dev->dev_private;
14537
14538 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 14539 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 14540}
14541
b6b5d049
VS		 14542static void quirk_pipeb_force(struct drm_device *dev)
14543{
14544 struct drm_i915_private *dev_priv = dev->dev_private;
14545
14546 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14547 DRM_INFO("applying pipe b force quirk\n");
14548}
14549
435793df
KP		 14550/*
14551 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14552 */
14553static void quirk_ssc_force_disable(struct drm_device *dev)
14554{
14555 struct drm_i915_private *dev_priv = dev->dev_private;
14556 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 14557 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 14558}
14559
4dca20ef 14560/*
5a15ab5b
CE		 14561 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14562 * brightness value
4dca20ef
CE		 14563 */
14564static void quirk_invert_brightness(struct drm_device *dev)
14565{
14566 struct drm_i915_private *dev_priv = dev->dev_private;
14567 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 14568 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 14569}
14570
9c72cc6f
SD		 14571/* Some VBT's incorrectly indicate no backlight is present */
14572static void quirk_backlight_present(struct drm_device *dev)
14573{
14574 struct drm_i915_private *dev_priv = dev->dev_private;
14575 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14576 DRM_INFO("applying backlight present quirk\n");
14577}
14578
b690e96c
JB		 14579struct intel_quirk {
14580 int device;
14581 int subsystem_vendor;
14582 int subsystem_device;
14583 void (*hook)(struct drm_device *dev);
14584};
14585
5f85f176
EE		 14586/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14587struct intel_dmi_quirk {
14588 void (*hook)(struct drm_device *dev);
14589 const struct dmi_system_id (*dmi_id_list)[];
14590};
14591
14592static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14593{
14594 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14595 return 1;
14596}
14597
14598static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14599 {
14600 .dmi_id_list = &(const struct dmi_system_id[]) {
14601 {
14602 .callback = intel_dmi_reverse_brightness,
14603 .ident = "NCR Corporation",
14604 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14605 DMI_MATCH(DMI_PRODUCT_NAME, ""),
14606 },
14607 },
14608 { } /* terminating entry */
14609 },
14610 .hook = quirk_invert_brightness,
14611 },
14612};
14613
c43b5634 14614static struct intel_quirk intel_quirks[] = {
b690e96c
JB		 14615 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14616 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14617
b690e96c
JB		 14618 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14619 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14620
5f080c0f
VS		 14621 /* 830 needs to leave pipe A & dpll A up */
14622 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14623
b6b5d049
VS		 14624 /* 830 needs to leave pipe B & dpll B up */
14625 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14626
435793df
KP		 14627 /* Lenovo U160 cannot use SSC on LVDS */
14628 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 14629
14630 /* Sony Vaio Y cannot use SSC on LVDS */
14631 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b 14632
be505f64
AH		 14633 /* Acer Aspire 5734Z must invert backlight brightness */
14634 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14635
14636 /* Acer/eMachines G725 */
14637 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14638
14639 /* Acer/eMachines e725 */
14640 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14641
14642 /* Acer/Packard Bell NCL20 */
14643 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14644
14645 /* Acer Aspire 4736Z */
14646 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
0f540c3a
JN		 14647
14648 /* Acer Aspire 5336 */
14649 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
2e93a1aa
SD		 14650
14651 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14652 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
d4967d8c 14653
dfb3d47b
SD		 14654 /* Acer C720 Chromebook (Core i3 4005U) */
14655 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14656
b2a9601c 14657 /* Apple Macbook 2,1 (Core 2 T7400) */
14658 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14659
d4967d8c
SD		 14660 /* Toshiba CB35 Chromebook (Celeron 2955U) */
14661 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
724cb06f
SD		 14662
14663 /* HP Chromebook 14 (Celeron 2955U) */
14664 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
cf6f0af9
JN		 14665
14666 /* Dell Chromebook 11 */
14667 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
b690e96c
JB		 14668};
14669
14670static void intel_init_quirks(struct drm_device *dev)
14671{
14672 struct pci_dev *d = dev->pdev;
14673 int i;
14674
14675 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14676 struct intel_quirk *q = &intel_quirks[i];
14677
14678 if (d->device == q->device &&
14679 (d->subsystem_vendor == q->subsystem_vendor ||
14680 q->subsystem_vendor == PCI_ANY_ID) &&
14681 (d->subsystem_device == q->subsystem_device ||
14682 q->subsystem_device == PCI_ANY_ID))
14683 q->hook(dev);
14684 }
5f85f176
EE		 14685 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14686 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14687 intel_dmi_quirks[i].hook(dev);
14688 }
b690e96c
JB		 14689}
14690
9cce37f4
JB		 14691/* Disable the VGA plane that we never use */
14692static void i915_disable_vga(struct drm_device *dev)
14693{
14694 struct drm_i915_private *dev_priv = dev->dev_private;
14695 u8 sr1;
766aa1c4 14696 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4 14697
2b37c616 14698 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
9cce37f4 14699 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 14700 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 14701 sr1 = inb(VGA_SR_DATA);
14702 outb(sr1 | 1<<5, VGA_SR_DATA);
14703 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
14704 udelay(300);
14705
01f5a626 14706 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9cce37f4
JB		 14707 POSTING_READ(vga_reg);
14708}
14709
f817586c
DV		 14710void intel_modeset_init_hw(struct drm_device *dev)
14711{
b6283055 14712 intel_update_cdclk(dev);
a8f78b58 14713 intel_prepare_ddi(dev);
f817586c 14714 intel_init_clock_gating(dev);
8090c6b9 14715 intel_enable_gt_powersave(dev);
f817586c
DV		 14716}
14717
79e53945
JB		 14718void intel_modeset_init(struct drm_device *dev)
14719{
652c393a 14720 struct drm_i915_private *dev_priv = dev->dev_private;
1fe47785 14721 int sprite, ret;
8cc87b75 14722 enum pipe pipe;
46f297fb 14723 struct intel_crtc *crtc;
79e53945
JB		 14724
14725 drm_mode_config_init(dev);
14726
14727 dev->mode_config.min_width = 0;
14728 dev->mode_config.min_height = 0;
14729
019d96cb
DA		 14730 dev->mode_config.preferred_depth = 24;
14731 dev->mode_config.prefer_shadow = 1;
14732
25bab385
TU		 14733 dev->mode_config.allow_fb_modifiers = true;
14734
e6ecefaa 14735 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 14736
b690e96c
JB		 14737 intel_init_quirks(dev);
14738
1fa61106
ED		 14739 intel_init_pm(dev);
14740
e3c74757
BW		 14741 if (INTEL_INFO(dev)->num_pipes == 0)
14742 return;
14743
69f92f67
LW		 14744 /*
14745 * There may be no VBT; and if the BIOS enabled SSC we can
14746 * just keep using it to avoid unnecessary flicker. Whereas if the
14747 * BIOS isn't using it, don't assume it will work even if the VBT
14748 * indicates as much.
14749 */
14750 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
14751 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
14752 DREF_SSC1_ENABLE);
14753
14754 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
14755 DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
14756 bios_lvds_use_ssc ? "en" : "dis",
14757 dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
14758 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
14759 }
14760 }
14761
e70236a8 14762 intel_init_display(dev);
7c10a2b5 14763 intel_init_audio(dev);
e70236a8 14764
a6c45cf0
CW		 14765 if (IS_GEN2(dev)) {
14766 dev->mode_config.max_width = 2048;
14767 dev->mode_config.max_height = 2048;
14768 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 14769 dev->mode_config.max_width = 4096;
14770 dev->mode_config.max_height = 4096;
79e53945 14771 } else {
a6c45cf0
CW		 14772 dev->mode_config.max_width = 8192;
14773 dev->mode_config.max_height = 8192;
79e53945 14774 }
068be561 14775
dc41c154
VS		 14776 if (IS_845G(dev) || IS_I865G(dev)) {
14777 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
14778 dev->mode_config.cursor_height = 1023;
14779 } else if (IS_GEN2(dev)) {
068be561
DL		 14780 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
14781 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
14782 } else {
14783 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
14784 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
14785 }
14786
5d4545ae 14787 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 14788
28c97730 14789 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 14790 INTEL_INFO(dev)->num_pipes,
14791 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 14792
055e393f 14793 for_each_pipe(dev_priv, pipe) {
8cc87b75 14794 intel_crtc_init(dev, pipe);
3bdcfc0c 14795 for_each_sprite(dev_priv, pipe, sprite) {
1fe47785 14796 ret = intel_plane_init(dev, pipe, sprite);
7f1f3851 14797 if (ret)
06da8da2 14798 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
1fe47785 14799 pipe_name(pipe), sprite_name(pipe, sprite), ret);
7f1f3851 14800 }
79e53945
JB		 14801 }
14802
e72f9fbf 14803 intel_shared_dpll_init(dev);
ee7b9f93 14804
9cce37f4
JB		 14805 /* Just disable it once at startup */
14806 i915_disable_vga(dev);
79e53945 14807 intel_setup_outputs(dev);
11be49eb
CW		 14808
14809 /* Just in case the BIOS is doing something questionable. */
7733b49b 14810 intel_fbc_disable(dev_priv);
fa9fa083 14811
6e9f798d 14812 drm_modeset_lock_all(dev);
043e9bda 14813 intel_modeset_setup_hw_state(dev);
6e9f798d 14814 drm_modeset_unlock_all(dev);
46f297fb 14815
d3fcc808 14816 for_each_intel_crtc(dev, crtc) {
eeebeac5
ML		 14817 struct intel_initial_plane_config plane_config = {};
14818
46f297fb
JB		 14819 if (!crtc->active)
14820 continue;
14821
46f297fb 14822 /*
46f297fb
JB		 14823 * Note that reserving the BIOS fb up front prevents us
14824 * from stuffing other stolen allocations like the ring
14825 * on top. This prevents some ugliness at boot time, and
14826 * can even allow for smooth boot transitions if the BIOS
14827 * fb is large enough for the active pipe configuration.
14828 */
eeebeac5
ML		 14829 dev_priv->display.get_initial_plane_config(crtc,
14830 &plane_config);
14831
14832 /*
14833 * If the fb is shared between multiple heads, we'll
14834 * just get the first one.
14835 */
14836 intel_find_initial_plane_obj(crtc, &plane_config);
46f297fb 14837 }
2c7111db
CW		 14838}
14839
7fad798e
DV		 14840static void intel_enable_pipe_a(struct drm_device *dev)
14841{
14842 struct intel_connector *connector;
14843 struct drm_connector *crt = NULL;
14844 struct intel_load_detect_pipe load_detect_temp;
208bf9fd 14845 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
7fad798e
DV		 14846
14847 /* We can't just switch on the pipe A, we need to set things up with a
14848 * proper mode and output configuration. As a gross hack, enable pipe A
14849 * by enabling the load detect pipe once. */
3a3371ff 14850 for_each_intel_connector(dev, connector) {
7fad798e
DV		 14851 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
14852 crt = &connector->base;
14853 break;
14854 }
14855 }
14856
14857 if (!crt)
14858 return;
14859
208bf9fd 14860 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
49172fee 14861 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
7fad798e
DV		 14862}
14863
fa555837
DV		 14864static bool
14865intel_check_plane_mapping(struct intel_crtc *crtc)
14866{
7eb552ae
BW		 14867 struct drm_device *dev = crtc->base.dev;
14868 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 14869 u32 reg, val;
14870
7eb552ae 14871 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 14872 return true;
14873
14874 reg = DSPCNTR(!crtc->plane);
14875 val = I915_READ(reg);
14876
14877 if ((val & DISPLAY_PLANE_ENABLE) &&
14878 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
14879 return false;
14880
14881 return true;
14882}
14883
02e93c35
VS		 14884static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
14885{
14886 struct drm_device *dev = crtc->base.dev;
14887 struct intel_encoder *encoder;
14888
14889 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
14890 return true;
14891
14892 return false;
14893}
14894
24929352
DV		 14895static void intel_sanitize_crtc(struct intel_crtc *crtc)
14896{
14897 struct drm_device *dev = crtc->base.dev;
14898 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 14899 u32 reg;
24929352 14900
24929352 14901 /* Clear any frame start delays used for debugging left by the BIOS */
6e3c9717 14902 reg = PIPECONF(crtc->config->cpu_transcoder);
24929352
DV		 14903 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
14904
d3eaf884 14905 /* restore vblank interrupts to correct state */
9625604c 14906 drm_crtc_vblank_reset(&crtc->base);
d297e103 14907 if (crtc->active) {
3a03dfb0 14908 drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
d297e103 14909 update_scanline_offset(crtc);
9625604c
DV		 14910 drm_crtc_vblank_on(&crtc->base);
14911 }
d3eaf884 14912
24929352 14913 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 14914 * disable the crtc (and hence change the state) if it is wrong. Note
14915 * that gen4+ has a fixed plane -> pipe mapping. */
14916 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 14917 bool plane;
14918
24929352
DV		 14919 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
14920 crtc->base.base.id);
14921
14922 /* Pipe has the wrong plane attached and the plane is active.
14923 * Temporarily change the plane mapping and disable everything
14924 * ... */
14925 plane = crtc->plane;
b70709a6 14926 to_intel_plane_state(crtc->base.primary->state)->visible = true;
24929352 14927 crtc->plane = !plane;
b17d48e2 14928 intel_crtc_disable_noatomic(&crtc->base);
24929352 14929 crtc->plane = plane;
24929352 14930 }
24929352 14931
7fad798e
DV		 14932 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
14933 crtc->pipe == PIPE_A && !crtc->active) {
14934 /* BIOS forgot to enable pipe A, this mostly happens after
14935 * resume. Force-enable the pipe to fix this, the update_dpms
14936 * call below we restore the pipe to the right state, but leave
14937 * the required bits on. */
14938 intel_enable_pipe_a(dev);
14939 }
14940
24929352
DV		 14941 /* Adjust the state of the output pipe according to whether we
14942 * have active connectors/encoders. */
02e93c35 14943 if (!intel_crtc_has_encoders(crtc))
b17d48e2 14944 intel_crtc_disable_noatomic(&crtc->base);
24929352 14945
53d9f4e9 14946 if (crtc->active != crtc->base.state->active) {
02e93c35 14947 struct intel_encoder *encoder;
24929352
DV		 14948
14949 /* This can happen either due to bugs in the get_hw_state
b17d48e2
ML		 14950 * functions or because of calls to intel_crtc_disable_noatomic,
14951 * or because the pipe is force-enabled due to the
24929352
DV		 14952 * pipe A quirk. */
14953 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
14954 crtc->base.base.id,
83d65738 14955 crtc->base.state->enable ? "enabled" : "disabled",
24929352
DV		 14956 crtc->active ? "enabled" : "disabled");
14957
4be40c98 14958 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, NULL) < 0);
49d6fa21 14959 crtc->base.state->active = crtc->active;
24929352
DV		 14960 crtc->base.enabled = crtc->active;
14961
14962 /* Because we only establish the connector -> encoder ->
14963 * crtc links if something is active, this means the
14964 * crtc is now deactivated. Break the links. connector
14965 * -> encoder links are only establish when things are
14966 * actually up, hence no need to break them. */
14967 WARN_ON(crtc->active);
14968
2d406bb0 14969 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
24929352 14970 encoder->base.crtc = NULL;
24929352 14971 }
c5ab3bc0 14972
a3ed6aad 14973 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
4cc31489
DV		 14974 /*
14975 * We start out with underrun reporting disabled to avoid races.
14976 * For correct bookkeeping mark this on active crtcs.
14977 *
c5ab3bc0
DV		 14978 * Also on gmch platforms we dont have any hardware bits to
14979 * disable the underrun reporting. Which means we need to start
14980 * out with underrun reporting disabled also on inactive pipes,
14981 * since otherwise we'll complain about the garbage we read when
14982 * e.g. coming up after runtime pm.
14983 *
4cc31489
DV		 14984 * No protection against concurrent access is required - at
14985 * worst a fifo underrun happens which also sets this to false.
14986 */
14987 crtc->cpu_fifo_underrun_disabled = true;
14988 crtc->pch_fifo_underrun_disabled = true;
14989 }
24929352
DV		 14990}
14991
14992static void intel_sanitize_encoder(struct intel_encoder *encoder)
14993{
14994 struct intel_connector *connector;
14995 struct drm_device *dev = encoder->base.dev;
873ffe69 14996 bool active = false;
24929352
DV		 14997
14998 /* We need to check both for a crtc link (meaning that the
14999 * encoder is active and trying to read from a pipe) and the
15000 * pipe itself being active. */
15001 bool has_active_crtc = encoder->base.crtc &&
15002 to_intel_crtc(encoder->base.crtc)->active;
15003
873ffe69
ML		 15004 for_each_intel_connector(dev, connector) {
15005 if (connector->base.encoder != &encoder->base)
15006 continue;
15007
15008 active = true;
15009 break;
15010 }
15011
15012 if (active && !has_active_crtc) {
24929352
DV		 15013 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15014 encoder->base.base.id,
8e329a03 15015 encoder->base.name);
24929352
DV		 15016
15017 /* Connector is active, but has no active pipe. This is
15018 * fallout from our resume register restoring. Disable
15019 * the encoder manually again. */
15020 if (encoder->base.crtc) {
15021 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15022 encoder->base.base.id,
8e329a03 15023 encoder->base.name);
24929352 15024 encoder->disable(encoder);
a62d1497
VS		 15025 if (encoder->post_disable)
15026 encoder->post_disable(encoder);
24929352 15027 }
7f1950fb 15028 encoder->base.crtc = NULL;
24929352
DV		 15029
15030 /* Inconsistent output/port/pipe state happens presumably due to
15031 * a bug in one of the get_hw_state functions. Or someplace else
15032 * in our code, like the register restore mess on resume. Clamp
15033 * things to off as a safer default. */
3a3371ff 15034 for_each_intel_connector(dev, connector) {
24929352
DV		 15035 if (connector->encoder != encoder)
15036 continue;
7f1950fb
EE		 15037 connector->base.dpms = DRM_MODE_DPMS_OFF;
15038 connector->base.encoder = NULL;
24929352
DV		 15039 }
15040 }
15041 /* Enabled encoders without active connectors will be fixed in
15042 * the crtc fixup. */
15043}
15044
04098753 15045void i915_redisable_vga_power_on(struct drm_device *dev)
0fde901f
KM		 15046{
15047 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 15048 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f 15049
04098753
ID		 15050 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15051 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15052 i915_disable_vga(dev);
15053 }
15054}
15055
15056void i915_redisable_vga(struct drm_device *dev)
15057{
15058 struct drm_i915_private *dev_priv = dev->dev_private;
15059
8dc8a27c
PZ		 15060 /* This function can be called both from intel_modeset_setup_hw_state or
15061 * at a very early point in our resume sequence, where the power well
15062 * structures are not yet restored. Since this function is at a very
15063 * paranoid "someone might have enabled VGA while we were not looking"
15064 * level, just check if the power well is enabled instead of trying to
15065 * follow the "don't touch the power well if we don't need it" policy
15066 * the rest of the driver uses. */
f458ebbc 15067 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
8dc8a27c
PZ		 15068 return;
15069
04098753 15070 i915_redisable_vga_power_on(dev);
0fde901f
KM		 15071}
15072
98ec7739
VS		 15073static bool primary_get_hw_state(struct intel_crtc *crtc)
15074{
15075 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
15076
d032ffa0
ML		 15077 return !!(I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE);
15078}
15079
15080static void readout_plane_state(struct intel_crtc *crtc,
15081 struct intel_crtc_state *crtc_state)
15082{
15083 struct intel_plane *p;
4cf0ebbd 15084 struct intel_plane_state *plane_state;
d032ffa0
ML		 15085 bool active = crtc_state->base.active;
15086
d032ffa0 15087 for_each_intel_plane(crtc->base.dev, p) {
d032ffa0
ML		 15088 if (crtc->pipe != p->pipe)
15089 continue;
15090
4cf0ebbd 15091 plane_state = to_intel_plane_state(p->base.state);
e435d6e5 15092
4cf0ebbd
ML		 15093 if (p->base.type == DRM_PLANE_TYPE_PRIMARY)
15094 plane_state->visible = primary_get_hw_state(crtc);
15095 else {
15096 if (active)
15097 p->disable_plane(&p->base, &crtc->base);
d032ffa0 15098
4cf0ebbd 15099 plane_state->visible = false;
d032ffa0
ML		 15100 }
15101 }
98ec7739
VS		 15102}
15103
30e984df 15104static void intel_modeset_readout_hw_state(struct drm_device *dev)
24929352
DV		 15105{
15106 struct drm_i915_private *dev_priv = dev->dev_private;
15107 enum pipe pipe;
24929352
DV		 15108 struct intel_crtc *crtc;
15109 struct intel_encoder *encoder;
15110 struct intel_connector *connector;
5358901f 15111 int i;
24929352 15112
d3fcc808 15113 for_each_intel_crtc(dev, crtc) {
b06f8b0d 15114 __drm_atomic_helper_crtc_destroy_state(&crtc->base, crtc->base.state);
6e3c9717 15115 memset(crtc->config, 0, sizeof(*crtc->config));
f7217905 15116 crtc->config->base.crtc = &crtc->base;
3b117c8f 15117
0e8ffe1b 15118 crtc->active = dev_priv->display.get_pipe_config(crtc,
6e3c9717 15119 crtc->config);
24929352 15120
49d6fa21 15121 crtc->base.state->active = crtc->active;
24929352 15122 crtc->base.enabled = crtc->active;
b70709a6 15123
5c1e3426
ML		 15124 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15125 if (crtc->base.state->active) {
15126 intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
15127 intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
15128 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15129
15130 /*
15131 * The initial mode needs to be set in order to keep
15132 * the atomic core happy. It wants a valid mode if the
15133 * crtc's enabled, so we do the above call.
15134 *
15135 * At this point some state updated by the connectors
15136 * in their ->detect() callback has not run yet, so
15137 * no recalculation can be done yet.
15138 *
15139 * Even if we could do a recalculation and modeset
15140 * right now it would cause a double modeset if
15141 * fbdev or userspace chooses a different initial mode.
15142 *
5c1e3426
ML		 15143 * If that happens, someone indicated they wanted a
15144 * mode change, which means it's safe to do a full
15145 * recalculation.
15146 */
1ed51de9 15147 crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
5c1e3426
ML		 15148 }
15149
15150 crtc->base.hwmode = crtc->config->base.adjusted_mode;
d032ffa0 15151 readout_plane_state(crtc, to_intel_crtc_state(crtc->base.state));
24929352
DV		 15152
15153 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15154 crtc->base.base.id,
15155 crtc->active ? "enabled" : "disabled");
15156 }
15157
5358901f
DV		 15158 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15159 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15160
3e369b76
ACO		 15161 pll->on = pll->get_hw_state(dev_priv, pll,
15162 &pll->config.hw_state);
5358901f 15163 pll->active = 0;
3e369b76 15164 pll->config.crtc_mask = 0;
d3fcc808 15165 for_each_intel_crtc(dev, crtc) {
1e6f2ddc 15166 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
5358901f 15167 pll->active++;
3e369b76 15168 pll->config.crtc_mask |= 1 << crtc->pipe;
1e6f2ddc 15169 }
5358901f 15170 }
5358901f 15171
1e6f2ddc 15172 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
3e369b76 15173 pll->name, pll->config.crtc_mask, pll->on);
bd2bb1b9 15174
3e369b76 15175 if (pll->config.crtc_mask)
bd2bb1b9 15176 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5358901f
DV		 15177 }
15178
b2784e15 15179 for_each_intel_encoder(dev, encoder) {
24929352
DV		 15180 pipe = 0;
15181
15182 if (encoder->get_hw_state(encoder, &pipe)) {
045ac3b5
JB		 15183 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15184 encoder->base.crtc = &crtc->base;
6e3c9717 15185 encoder->get_config(encoder, crtc->config);
24929352
DV		 15186 } else {
15187 encoder->base.crtc = NULL;
15188 }
15189
6f2bcceb 15190 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
24929352 15191 encoder->base.base.id,
8e329a03 15192 encoder->base.name,
24929352 15193 encoder->base.crtc ? "enabled" : "disabled",
6f2bcceb 15194 pipe_name(pipe));
24929352
DV		 15195 }
15196
3a3371ff 15197 for_each_intel_connector(dev, connector) {
24929352
DV		 15198 if (connector->get_hw_state(connector)) {
15199 connector->base.dpms = DRM_MODE_DPMS_ON;
24929352
DV		 15200 connector->base.encoder = &connector->encoder->base;
15201 } else {
15202 connector->base.dpms = DRM_MODE_DPMS_OFF;
15203 connector->base.encoder = NULL;
15204 }
15205 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15206 connector->base.base.id,
c23cc417 15207 connector->base.name,
24929352
DV		 15208 connector->base.encoder ? "enabled" : "disabled");
15209 }
30e984df
DV		 15210}
15211
043e9bda
ML		 15212/* Scan out the current hw modeset state,
15213 * and sanitizes it to the current state
15214 */
15215static void
15216intel_modeset_setup_hw_state(struct drm_device *dev)
30e984df
DV		 15217{
15218 struct drm_i915_private *dev_priv = dev->dev_private;
15219 enum pipe pipe;
30e984df
DV		 15220 struct intel_crtc *crtc;
15221 struct intel_encoder *encoder;
35c95375 15222 int i;
30e984df
DV		 15223
15224 intel_modeset_readout_hw_state(dev);
24929352
DV		 15225
15226 /* HW state is read out, now we need to sanitize this mess. */
b2784e15 15227 for_each_intel_encoder(dev, encoder) {
24929352
DV		 15228 intel_sanitize_encoder(encoder);
15229 }
15230
055e393f 15231 for_each_pipe(dev_priv, pipe) {
24929352
DV		 15232 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15233 intel_sanitize_crtc(crtc);
6e3c9717
ACO		 15234 intel_dump_pipe_config(crtc, crtc->config,
15235 "[setup_hw_state]");
24929352 15236 }
9a935856 15237
d29b2f9d
ACO		 15238 intel_modeset_update_connector_atomic_state(dev);
15239
35c95375
DV		 15240 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15241 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15242
15243 if (!pll->on || pll->active)
15244 continue;
15245
15246 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15247
15248 pll->disable(dev_priv, pll);
15249 pll->on = false;
15250 }
15251
26e1fe4f 15252 if (IS_VALLEYVIEW(dev))
6eb1a681
VS		 15253 vlv_wm_get_hw_state(dev);
15254 else if (IS_GEN9(dev))
3078999f
PB		 15255 skl_wm_get_hw_state(dev);
15256 else if (HAS_PCH_SPLIT(dev))
243e6a44 15257 ilk_wm_get_hw_state(dev);
292b990e
ML		 15258
15259 for_each_intel_crtc(dev, crtc) {
15260 unsigned long put_domains;
15261
15262 put_domains = modeset_get_crtc_power_domains(&crtc->base);
15263 if (WARN_ON(put_domains))
15264 modeset_put_power_domains(dev_priv, put_domains);
15265 }
15266 intel_display_set_init_power(dev_priv, false);
043e9bda 15267}
7d0bc1ea 15268
043e9bda
ML		 15269void intel_display_resume(struct drm_device *dev)
15270{
15271 struct drm_atomic_state *state = drm_atomic_state_alloc(dev);
15272 struct intel_connector *conn;
15273 struct intel_plane *plane;
15274 struct drm_crtc *crtc;
15275 int ret;
f30da187 15276
043e9bda
ML		 15277 if (!state)
15278 return;
15279
15280 state->acquire_ctx = dev->mode_config.acquire_ctx;
15281
15282 /* preserve complete old state, including dpll */
15283 intel_atomic_get_shared_dpll_state(state);
15284
15285 for_each_crtc(dev, crtc) {
15286 struct drm_crtc_state *crtc_state =
15287 drm_atomic_get_crtc_state(state, crtc);
15288
15289 ret = PTR_ERR_OR_ZERO(crtc_state);
15290 if (ret)
15291 goto err;
15292
15293 /* force a restore */
15294 crtc_state->mode_changed = true;
45e2b5f6 15295 }
8af6cf88 15296
043e9bda
ML		 15297 for_each_intel_plane(dev, plane) {
15298 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(state, &plane->base));
15299 if (ret)
15300 goto err;
15301 }
15302
15303 for_each_intel_connector(dev, conn) {
15304 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(state, &conn->base));
15305 if (ret)
15306 goto err;
15307 }
15308
15309 intel_modeset_setup_hw_state(dev);
15310
15311 i915_redisable_vga(dev);
74c090b1 15312 ret = drm_atomic_commit(state);
043e9bda
ML		 15313 if (!ret)
15314 return;
15315
15316err:
15317 DRM_ERROR("Restoring old state failed with %i\n", ret);
15318 drm_atomic_state_free(state);
2c7111db
CW		 15319}
15320
15321void intel_modeset_gem_init(struct drm_device *dev)
15322{
484b41dd 15323 struct drm_crtc *c;
2ff8fde1 15324 struct drm_i915_gem_object *obj;
e0d6149b 15325 int ret;
484b41dd 15326
ae48434c
ID		 15327 mutex_lock(&dev->struct_mutex);
15328 intel_init_gt_powersave(dev);
15329 mutex_unlock(&dev->struct_mutex);
15330
1833b134 15331 intel_modeset_init_hw(dev);
02e792fb
DV		 15332
15333 intel_setup_overlay(dev);
484b41dd
JB		 15334
15335 /*
15336 * Make sure any fbs we allocated at startup are properly
15337 * pinned & fenced. When we do the allocation it's too early
15338 * for this.
15339 */
70e1e0ec 15340 for_each_crtc(dev, c) {
2ff8fde1
MR		 15341 obj = intel_fb_obj(c->primary->fb);
15342 if (obj == NULL)
484b41dd
JB		 15343 continue;
15344
e0d6149b
TU		 15345 mutex_lock(&dev->struct_mutex);
15346 ret = intel_pin_and_fence_fb_obj(c->primary,
15347 c->primary->fb,
15348 c->primary->state,
91af127f 15349 NULL, NULL);
e0d6149b
TU		 15350 mutex_unlock(&dev->struct_mutex);
15351 if (ret) {
484b41dd
JB		 15352 DRM_ERROR("failed to pin boot fb on pipe %d\n",
15353 to_intel_crtc(c)->pipe);
66e514c1
DA		 15354 drm_framebuffer_unreference(c->primary->fb);
15355 c->primary->fb = NULL;
36750f28 15356 c->primary->crtc = c->primary->state->crtc = NULL;
afd65eb4 15357 update_state_fb(c->primary);
36750f28 15358 c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
484b41dd
JB		 15359 }
15360 }
0962c3c9
VS		 15361
15362 intel_backlight_register(dev);
79e53945
JB		 15363}
15364
4932e2c3
ID		 15365void intel_connector_unregister(struct intel_connector *intel_connector)
15366{
15367 struct drm_connector *connector = &intel_connector->base;
15368
15369 intel_panel_destroy_backlight(connector);
34ea3d38 15370 drm_connector_unregister(connector);
4932e2c3
ID		 15371}
15372
79e53945
JB		 15373void intel_modeset_cleanup(struct drm_device *dev)
15374{
652c393a 15375 struct drm_i915_private *dev_priv = dev->dev_private;
d9255d57 15376 struct drm_connector *connector;
652c393a 15377
2eb5252e
ID		 15378 intel_disable_gt_powersave(dev);
15379
0962c3c9
VS		 15380 intel_backlight_unregister(dev);
15381
fd0c0642
DV		 15382 /*
15383 * Interrupts and polling as the first thing to avoid creating havoc.
2eb5252e 15384 * Too much stuff here (turning of connectors, ...) would
fd0c0642
DV		 15385 * experience fancy races otherwise.
15386 */
2aeb7d3a 15387 intel_irq_uninstall(dev_priv);
eb21b92b 15388
fd0c0642
DV		 15389 /*
15390 * Due to the hpd irq storm handling the hotplug work can re-arm the
15391 * poll handlers. Hence disable polling after hpd handling is shut down.
15392 */
f87ea761 15393 drm_kms_helper_poll_fini(dev);
fd0c0642 15394
723bfd70
JB		 15395 intel_unregister_dsm_handler();
15396
7733b49b 15397 intel_fbc_disable(dev_priv);
69341a5e 15398
1630fe75
CW		 15399 /* flush any delayed tasks or pending work */
15400 flush_scheduled_work();
15401
db31af1d
JN		 15402 /* destroy the backlight and sysfs files before encoders/connectors */
15403 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4932e2c3
ID		 15404 struct intel_connector *intel_connector;
15405
15406 intel_connector = to_intel_connector(connector);
15407 intel_connector->unregister(intel_connector);
db31af1d 15408 }
d9255d57 15409
79e53945 15410 drm_mode_config_cleanup(dev);
4d7bb011
DV		 15411
15412 intel_cleanup_overlay(dev);
ae48434c
ID		 15413
15414 mutex_lock(&dev->struct_mutex);
15415 intel_cleanup_gt_powersave(dev);
15416 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 15417}
15418
f1c79df3
ZW		 15419/*
15420 * Return which encoder is currently attached for connector.
15421 */
df0e9248 15422struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 15423{
df0e9248
CW		 15424 return &intel_attached_encoder(connector)->base;
15425}
f1c79df3 15426
df0e9248
CW		 15427void intel_connector_attach_encoder(struct intel_connector *connector,
15428 struct intel_encoder *encoder)
15429{
15430 connector->encoder = encoder;
15431 drm_mode_connector_attach_encoder(&connector->base,
15432 &encoder->base);
79e53945 15433}
28d52043
DA		 15434
15435/*
15436 * set vga decode state - true == enable VGA decode
15437 */
15438int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15439{
15440 struct drm_i915_private *dev_priv = dev->dev_private;
a885b3cc 15441 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
28d52043
DA		 15442 u16 gmch_ctrl;
15443
75fa041d
CW		 15444 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15445 DRM_ERROR("failed to read control word\n");
15446 return -EIO;
15447 }
15448
c0cc8a55
CW		 15449 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15450 return 0;
15451
28d52043
DA		 15452 if (state)
15453 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15454 else
15455 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
75fa041d
CW		 15456
15457 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15458 DRM_ERROR("failed to write control word\n");
15459 return -EIO;
15460 }
15461
28d52043
DA		 15462 return 0;
15463}
c4a1d9e4 15464
c4a1d9e4 15465struct intel_display_error_state {
ff57f1b0
PZ		 15466
15467 u32 power_well_driver;
15468
63b66e5b
CW		 15469 int num_transcoders;
15470
c4a1d9e4
CW		 15471 struct intel_cursor_error_state {
15472 u32 control;
15473 u32 position;
15474 u32 base;
15475 u32 size;
52331309 15476 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 15477
15478 struct intel_pipe_error_state {
ddf9c536 15479 bool power_domain_on;
c4a1d9e4 15480 u32 source;
f301b1e1 15481 u32 stat;
52331309 15482 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 15483
15484 struct intel_plane_error_state {
15485 u32 control;
15486 u32 stride;
15487 u32 size;
15488 u32 pos;
15489 u32 addr;
15490 u32 surface;
15491 u32 tile_offset;
52331309 15492 } plane[I915_MAX_PIPES];
63b66e5b
CW		 15493
15494 struct intel_transcoder_error_state {
ddf9c536 15495 bool power_domain_on;
63b66e5b
CW		 15496 enum transcoder cpu_transcoder;
15497
15498 u32 conf;
15499
15500 u32 htotal;
15501 u32 hblank;
15502 u32 hsync;
15503 u32 vtotal;
15504 u32 vblank;
15505 u32 vsync;
15506 } transcoder[4];
c4a1d9e4
CW		 15507};
15508
15509struct intel_display_error_state *
15510intel_display_capture_error_state(struct drm_device *dev)
15511{
fbee40df 15512 struct drm_i915_private *dev_priv = dev->dev_private;
c4a1d9e4 15513 struct intel_display_error_state *error;
63b66e5b
CW		 15514 int transcoders[] = {
15515 TRANSCODER_A,
15516 TRANSCODER_B,
15517 TRANSCODER_C,
15518 TRANSCODER_EDP,
15519 };
c4a1d9e4
CW		 15520 int i;
15521
63b66e5b
CW		 15522 if (INTEL_INFO(dev)->num_pipes == 0)
15523 return NULL;
15524
9d1cb914 15525 error = kzalloc(sizeof(*error), GFP_ATOMIC);
c4a1d9e4
CW		 15526 if (error == NULL)
15527 return NULL;
15528
190be112 15529 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ff57f1b0
PZ		 15530 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15531
055e393f 15532 for_each_pipe(dev_priv, i) {
ddf9c536 15533 error->pipe[i].power_domain_on =
f458ebbc
DV		 15534 __intel_display_power_is_enabled(dev_priv,
15535 POWER_DOMAIN_PIPE(i));
ddf9c536 15536 if (!error->pipe[i].power_domain_on)
9d1cb914
PZ		 15537 continue;
15538
5efb3e28
VS		 15539 error->cursor[i].control = I915_READ(CURCNTR(i));
15540 error->cursor[i].position = I915_READ(CURPOS(i));
15541 error->cursor[i].base = I915_READ(CURBASE(i));
c4a1d9e4
CW		 15542
15543 error->plane[i].control = I915_READ(DSPCNTR(i));
15544 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 15545 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 15546 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 15547 error->plane[i].pos = I915_READ(DSPPOS(i));
15548 }
ca291363
PZ		 15549 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15550 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 15551 if (INTEL_INFO(dev)->gen >= 4) {
15552 error->plane[i].surface = I915_READ(DSPSURF(i));
15553 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15554 }
15555
c4a1d9e4 15556 error->pipe[i].source = I915_READ(PIPESRC(i));
f301b1e1 15557
3abfce77 15558 if (HAS_GMCH_DISPLAY(dev))
f301b1e1 15559 error->pipe[i].stat = I915_READ(PIPESTAT(i));
63b66e5b
CW		 15560 }
15561
15562 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
15563 if (HAS_DDI(dev_priv->dev))
15564 error->num_transcoders++; /* Account for eDP. */
15565
15566 for (i = 0; i < error->num_transcoders; i++) {
15567 enum transcoder cpu_transcoder = transcoders[i];
15568
ddf9c536 15569 error->transcoder[i].power_domain_on =
f458ebbc 15570 __intel_display_power_is_enabled(dev_priv,
38cc1daf 15571 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
ddf9c536 15572 if (!error->transcoder[i].power_domain_on)
9d1cb914
PZ		 15573 continue;
15574
63b66e5b
CW		 15575 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15576
15577 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15578 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15579 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15580 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15581 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15582 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15583 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 15584 }
15585
15586 return error;
15587}
15588
edc3d884
MK		 15589#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15590
c4a1d9e4 15591void
edc3d884 15592intel_display_print_error_state(struct drm_i915_error_state_buf *m,
c4a1d9e4
CW		 15593 struct drm_device *dev,
15594 struct intel_display_error_state *error)
15595{
055e393f 15596 struct drm_i915_private *dev_priv = dev->dev_private;
c4a1d9e4
CW		 15597 int i;
15598
63b66e5b
CW		 15599 if (!error)
15600 return;
15601
edc3d884 15602 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
190be112 15603 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
edc3d884 15604 err_printf(m, "PWR_WELL_CTL2: %08x\n",
ff57f1b0 15605 error->power_well_driver);
055e393f 15606 for_each_pipe(dev_priv, i) {
edc3d884 15607 err_printf(m, "Pipe [%d]:\n", i);
ddf9c536
ID		 15608 err_printf(m, " Power: %s\n",
15609 error->pipe[i].power_domain_on ? "on" : "off");
edc3d884 15610 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
f301b1e1 15611 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
edc3d884
MK		 15612
15613 err_printf(m, "Plane [%d]:\n", i);
15614 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
15615 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 15616 if (INTEL_INFO(dev)->gen <= 3) {
edc3d884
MK		 15617 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
15618 err_printf(m, " POS: %08x\n", error->plane[i].pos);
80ca378b 15619 }
4b71a570 15620 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
edc3d884 15621 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4 15622 if (INTEL_INFO(dev)->gen >= 4) {
edc3d884
MK		 15623 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
15624 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
c4a1d9e4
CW		 15625 }
15626
edc3d884
MK		 15627 err_printf(m, "Cursor [%d]:\n", i);
15628 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
15629 err_printf(m, " POS: %08x\n", error->cursor[i].position);
15630 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
c4a1d9e4 15631 }
63b66e5b
CW		 15632
15633 for (i = 0; i < error->num_transcoders; i++) {
1cf84bb6 15634 err_printf(m, "CPU transcoder: %c\n",
63b66e5b 15635 transcoder_name(error->transcoder[i].cpu_transcoder));
ddf9c536
ID		 15636 err_printf(m, " Power: %s\n",
15637 error->transcoder[i].power_domain_on ? "on" : "off");
63b66e5b
CW		 15638 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
15639 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
15640 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
15641 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
15642 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
15643 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
15644 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
15645 }
c4a1d9e4 15646}
e2fcdaa9
VS		 15647
15648void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
15649{
15650 struct intel_crtc *crtc;
15651
15652 for_each_intel_crtc(dev, crtc) {
15653 struct intel_unpin_work *work;
e2fcdaa9 15654
5e2d7afc 15655 spin_lock_irq(&dev->event_lock);
e2fcdaa9
VS		 15656
15657 work = crtc->unpin_work;
15658
15659 if (work && work->event &&
15660 work->event->base.file_priv == file) {
15661 kfree(work->event);
15662 work->event = NULL;
15663 }
15664
5e2d7afc 15665 spin_unlock_irq(&dev->event_lock);
e2fcdaa9
VS		 15666 }
15667}
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