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drm/i915: disable IPS while getting the sink CRCs
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
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79e53945
JB
1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB
28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
319c1d42 40#include <drm/drm_atomic.h>
c196e1d6 41#include <drm/drm_atomic_helper.h>
760285e7
DH
42#include <drm/drm_dp_helper.h>
43#include <drm/drm_crtc_helper.h>
465c120c
MR
44#include <drm/drm_plane_helper.h>
45#include <drm/drm_rect.h>
c0f372b3 46#include <linux/dma_remapping.h>
79e53945 47
465c120c 48/* Primary plane formats for gen <= 3 */
568db4f2 49static const uint32_t i8xx_primary_formats[] = {
67fe7dc5
DL
50 DRM_FORMAT_C8,
51 DRM_FORMAT_RGB565,
465c120c 52 DRM_FORMAT_XRGB1555,
67fe7dc5 53 DRM_FORMAT_XRGB8888,
465c120c
MR
54};
55
56/* Primary plane formats for gen >= 4 */
568db4f2 57static const uint32_t i965_primary_formats[] = {
6c0fd451
DL
58 DRM_FORMAT_C8,
59 DRM_FORMAT_RGB565,
60 DRM_FORMAT_XRGB8888,
61 DRM_FORMAT_XBGR8888,
62 DRM_FORMAT_XRGB2101010,
63 DRM_FORMAT_XBGR2101010,
64};
65
66static const uint32_t skl_primary_formats[] = {
67fe7dc5
DL
67 DRM_FORMAT_C8,
68 DRM_FORMAT_RGB565,
69 DRM_FORMAT_XRGB8888,
465c120c 70 DRM_FORMAT_XBGR8888,
67fe7dc5 71 DRM_FORMAT_ARGB8888,
465c120c
MR
72 DRM_FORMAT_ABGR8888,
73 DRM_FORMAT_XRGB2101010,
465c120c 74 DRM_FORMAT_XBGR2101010,
465c120c
MR
75};
76
3d7d6510
MR
77/* Cursor formats */
78static const uint32_t intel_cursor_formats[] = {
79 DRM_FORMAT_ARGB8888,
80};
81
6b383a7f 82static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 83
f1f644dc 84static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 85 struct intel_crtc_state *pipe_config);
18442d08 86static void ironlake_pch_clock_get(struct intel_crtc *crtc,
5cec258b 87 struct intel_crtc_state *pipe_config);
f1f644dc 88
8c7b5ccb 89static int intel_set_mode(struct drm_crtc *crtc,
83a57153 90 struct drm_atomic_state *state);
eb1bfe80
JB
91static int intel_framebuffer_init(struct drm_device *dev,
92 struct intel_framebuffer *ifb,
93 struct drm_mode_fb_cmd2 *mode_cmd,
94 struct drm_i915_gem_object *obj);
5b18e57c
DV
95static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
96static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
29407aab 97static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
f769cd24
VK
98 struct intel_link_m_n *m_n,
99 struct intel_link_m_n *m2_n2);
29407aab 100static void ironlake_set_pipeconf(struct drm_crtc *crtc);
229fca97
DV
101static void haswell_set_pipeconf(struct drm_crtc *crtc);
102static void intel_set_pipe_csc(struct drm_crtc *crtc);
d288f65f 103static void vlv_prepare_pll(struct intel_crtc *crtc,
5cec258b 104 const struct intel_crtc_state *pipe_config);
d288f65f 105static void chv_prepare_pll(struct intel_crtc *crtc,
5cec258b 106 const struct intel_crtc_state *pipe_config);
ea2c67bb
MR
107static void intel_begin_crtc_commit(struct drm_crtc *crtc);
108static void intel_finish_crtc_commit(struct drm_crtc *crtc);
549e2bfb
CK
109static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
110 struct intel_crtc_state *crtc_state);
5ab7b0b7
ID
111static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
112 int num_connectors);
ce22dba9
ML
113static void intel_crtc_enable_planes(struct drm_crtc *crtc);
114static void intel_crtc_disable_planes(struct drm_crtc *crtc);
e7457a9a 115
0e32b39c
DA
116static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
117{
118 if (!connector->mst_port)
119 return connector->encoder;
120 else
121 return &connector->mst_port->mst_encoders[pipe]->base;
122}
123
79e53945 124typedef struct {
0206e353 125 int min, max;
79e53945
JB
126} intel_range_t;
127
128typedef struct {
0206e353
AJ
129 int dot_limit;
130 int p2_slow, p2_fast;
79e53945
JB
131} intel_p2_t;
132
d4906093
ML
133typedef struct intel_limit intel_limit_t;
134struct intel_limit {
0206e353
AJ
135 intel_range_t dot, vco, n, m, m1, m2, p, p1;
136 intel_p2_t p2;
d4906093 137};
79e53945 138
d2acd215
DV
139int
140intel_pch_rawclk(struct drm_device *dev)
141{
142 struct drm_i915_private *dev_priv = dev->dev_private;
143
144 WARN_ON(!HAS_PCH_SPLIT(dev));
145
146 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
147}
148
021357ac
CW
149static inline u32 /* units of 100MHz */
150intel_fdi_link_freq(struct drm_device *dev)
151{
8b99e68c
CW
152 if (IS_GEN5(dev)) {
153 struct drm_i915_private *dev_priv = dev->dev_private;
154 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
155 } else
156 return 27;
021357ac
CW
157}
158
5d536e28 159static const intel_limit_t intel_limits_i8xx_dac = {
0206e353 160 .dot = { .min = 25000, .max = 350000 },
9c333719 161 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 162 .n = { .min = 2, .max = 16 },
0206e353
AJ
163 .m = { .min = 96, .max = 140 },
164 .m1 = { .min = 18, .max = 26 },
165 .m2 = { .min = 6, .max = 16 },
166 .p = { .min = 4, .max = 128 },
167 .p1 = { .min = 2, .max = 33 },
273e27ca
EA
168 .p2 = { .dot_limit = 165000,
169 .p2_slow = 4, .p2_fast = 2 },
e4b36699
KP
170};
171
5d536e28
DV
172static const intel_limit_t intel_limits_i8xx_dvo = {
173 .dot = { .min = 25000, .max = 350000 },
9c333719 174 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 175 .n = { .min = 2, .max = 16 },
5d536e28
DV
176 .m = { .min = 96, .max = 140 },
177 .m1 = { .min = 18, .max = 26 },
178 .m2 = { .min = 6, .max = 16 },
179 .p = { .min = 4, .max = 128 },
180 .p1 = { .min = 2, .max = 33 },
181 .p2 = { .dot_limit = 165000,
182 .p2_slow = 4, .p2_fast = 4 },
183};
184
e4b36699 185static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353 186 .dot = { .min = 25000, .max = 350000 },
9c333719 187 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 188 .n = { .min = 2, .max = 16 },
0206e353
AJ
189 .m = { .min = 96, .max = 140 },
190 .m1 = { .min = 18, .max = 26 },
191 .m2 = { .min = 6, .max = 16 },
192 .p = { .min = 4, .max = 128 },
193 .p1 = { .min = 1, .max = 6 },
273e27ca
EA
194 .p2 = { .dot_limit = 165000,
195 .p2_slow = 14, .p2_fast = 7 },
e4b36699 196};
273e27ca 197
e4b36699 198static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ
199 .dot = { .min = 20000, .max = 400000 },
200 .vco = { .min = 1400000, .max = 2800000 },
201 .n = { .min = 1, .max = 6 },
202 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ
203 .m1 = { .min = 8, .max = 18 },
204 .m2 = { .min = 3, .max = 7 },
0206e353
AJ
205 .p = { .min = 5, .max = 80 },
206 .p1 = { .min = 1, .max = 8 },
273e27ca
EA
207 .p2 = { .dot_limit = 200000,
208 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP
209};
210
211static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ
212 .dot = { .min = 20000, .max = 400000 },
213 .vco = { .min = 1400000, .max = 2800000 },
214 .n = { .min = 1, .max = 6 },
215 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ
216 .m1 = { .min = 8, .max = 18 },
217 .m2 = { .min = 3, .max = 7 },
0206e353
AJ
218 .p = { .min = 7, .max = 98 },
219 .p1 = { .min = 1, .max = 8 },
273e27ca
EA
220 .p2 = { .dot_limit = 112000,
221 .p2_slow = 14, .p2_fast = 7 },
e4b36699
KP
222};
223
273e27ca 224
e4b36699 225static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA
226 .dot = { .min = 25000, .max = 270000 },
227 .vco = { .min = 1750000, .max = 3500000},
228 .n = { .min = 1, .max = 4 },
229 .m = { .min = 104, .max = 138 },
230 .m1 = { .min = 17, .max = 23 },
231 .m2 = { .min = 5, .max = 11 },
232 .p = { .min = 10, .max = 30 },
233 .p1 = { .min = 1, .max = 3},
234 .p2 = { .dot_limit = 270000,
235 .p2_slow = 10,
236 .p2_fast = 10
044c7c41 237 },
e4b36699
KP
238};
239
240static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA
241 .dot = { .min = 22000, .max = 400000 },
242 .vco = { .min = 1750000, .max = 3500000},
243 .n = { .min = 1, .max = 4 },
244 .m = { .min = 104, .max = 138 },
245 .m1 = { .min = 16, .max = 23 },
246 .m2 = { .min = 5, .max = 11 },
247 .p = { .min = 5, .max = 80 },
248 .p1 = { .min = 1, .max = 8},
249 .p2 = { .dot_limit = 165000,
250 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP
251};
252
253static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA
254 .dot = { .min = 20000, .max = 115000 },
255 .vco = { .min = 1750000, .max = 3500000 },
256 .n = { .min = 1, .max = 3 },
257 .m = { .min = 104, .max = 138 },
258 .m1 = { .min = 17, .max = 23 },
259 .m2 = { .min = 5, .max = 11 },
260 .p = { .min = 28, .max = 112 },
261 .p1 = { .min = 2, .max = 8 },
262 .p2 = { .dot_limit = 0,
263 .p2_slow = 14, .p2_fast = 14
044c7c41 264 },
e4b36699
KP
265};
266
267static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA
268 .dot = { .min = 80000, .max = 224000 },
269 .vco = { .min = 1750000, .max = 3500000 },
270 .n = { .min = 1, .max = 3 },
271 .m = { .min = 104, .max = 138 },
272 .m1 = { .min = 17, .max = 23 },
273 .m2 = { .min = 5, .max = 11 },
274 .p = { .min = 14, .max = 42 },
275 .p1 = { .min = 2, .max = 6 },
276 .p2 = { .dot_limit = 0,
277 .p2_slow = 7, .p2_fast = 7
044c7c41 278 },
e4b36699
KP
279};
280
f2b115e6 281static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ
282 .dot = { .min = 20000, .max = 400000},
283 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 284 /* Pineview's Ncounter is a ring counter */
0206e353
AJ
285 .n = { .min = 3, .max = 6 },
286 .m = { .min = 2, .max = 256 },
273e27ca 287 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ
288 .m1 = { .min = 0, .max = 0 },
289 .m2 = { .min = 0, .max = 254 },
290 .p = { .min = 5, .max = 80 },
291 .p1 = { .min = 1, .max = 8 },
273e27ca
EA
292 .p2 = { .dot_limit = 200000,
293 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP
294};
295
f2b115e6 296static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ
297 .dot = { .min = 20000, .max = 400000 },
298 .vco = { .min = 1700000, .max = 3500000 },
299 .n = { .min = 3, .max = 6 },
300 .m = { .min = 2, .max = 256 },
301 .m1 = { .min = 0, .max = 0 },
302 .m2 = { .min = 0, .max = 254 },
303 .p = { .min = 7, .max = 112 },
304 .p1 = { .min = 1, .max = 8 },
273e27ca
EA
305 .p2 = { .dot_limit = 112000,
306 .p2_slow = 14, .p2_fast = 14 },
e4b36699
KP
307};
308
273e27ca
EA
309/* Ironlake / Sandybridge
310 *
311 * We calculate clock using (register_value + 2) for N/M1/M2, so here
312 * the range value for them is (actual_value - 2).
313 */
b91ad0ec 314static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA
315 .dot = { .min = 25000, .max = 350000 },
316 .vco = { .min = 1760000, .max = 3510000 },
317 .n = { .min = 1, .max = 5 },
318 .m = { .min = 79, .max = 127 },
319 .m1 = { .min = 12, .max = 22 },
320 .m2 = { .min = 5, .max = 9 },
321 .p = { .min = 5, .max = 80 },
322 .p1 = { .min = 1, .max = 8 },
323 .p2 = { .dot_limit = 225000,
324 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP
325};
326
b91ad0ec 327static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA
328 .dot = { .min = 25000, .max = 350000 },
329 .vco = { .min = 1760000, .max = 3510000 },
330 .n = { .min = 1, .max = 3 },
331 .m = { .min = 79, .max = 118 },
332 .m1 = { .min = 12, .max = 22 },
333 .m2 = { .min = 5, .max = 9 },
334 .p = { .min = 28, .max = 112 },
335 .p1 = { .min = 2, .max = 8 },
336 .p2 = { .dot_limit = 225000,
337 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW
338};
339
340static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA
341 .dot = { .min = 25000, .max = 350000 },
342 .vco = { .min = 1760000, .max = 3510000 },
343 .n = { .min = 1, .max = 3 },
344 .m = { .min = 79, .max = 127 },
345 .m1 = { .min = 12, .max = 22 },
346 .m2 = { .min = 5, .max = 9 },
347 .p = { .min = 14, .max = 56 },
348 .p1 = { .min = 2, .max = 8 },
349 .p2 = { .dot_limit = 225000,
350 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW
351};
352
273e27ca 353/* LVDS 100mhz refclk limits. */
b91ad0ec 354static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA
355 .dot = { .min = 25000, .max = 350000 },
356 .vco = { .min = 1760000, .max = 3510000 },
357 .n = { .min = 1, .max = 2 },
358 .m = { .min = 79, .max = 126 },
359 .m1 = { .min = 12, .max = 22 },
360 .m2 = { .min = 5, .max = 9 },
361 .p = { .min = 28, .max = 112 },
0206e353 362 .p1 = { .min = 2, .max = 8 },
273e27ca
EA
363 .p2 = { .dot_limit = 225000,
364 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW
365};
366
367static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA
368 .dot = { .min = 25000, .max = 350000 },
369 .vco = { .min = 1760000, .max = 3510000 },
370 .n = { .min = 1, .max = 3 },
371 .m = { .min = 79, .max = 126 },
372 .m1 = { .min = 12, .max = 22 },
373 .m2 = { .min = 5, .max = 9 },
374 .p = { .min = 14, .max = 42 },
0206e353 375 .p1 = { .min = 2, .max = 6 },
273e27ca
EA
376 .p2 = { .dot_limit = 225000,
377 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY
378};
379
dc730512 380static const intel_limit_t intel_limits_vlv = {
f01b7962
VS
381 /*
382 * These are the data rate limits (measured in fast clocks)
383 * since those are the strictest limits we have. The fast
384 * clock and actual rate limits are more relaxed, so checking
385 * them would make no difference.
386 */
387 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
75e53986 388 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 389 .n = { .min = 1, .max = 7 },
a0c4da24
JB
390 .m1 = { .min = 2, .max = 3 },
391 .m2 = { .min = 11, .max = 156 },
b99ab663 392 .p1 = { .min = 2, .max = 3 },
5fdc9c49 393 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
a0c4da24
JB
394};
395
ef9348c8
CML
396static const intel_limit_t intel_limits_chv = {
397 /*
398 * These are the data rate limits (measured in fast clocks)
399 * since those are the strictest limits we have. The fast
400 * clock and actual rate limits are more relaxed, so checking
401 * them would make no difference.
402 */
403 .dot = { .min = 25000 * 5, .max = 540000 * 5},
17fe1021 404 .vco = { .min = 4800000, .max = 6480000 },
ef9348c8
CML
405 .n = { .min = 1, .max = 1 },
406 .m1 = { .min = 2, .max = 2 },
407 .m2 = { .min = 24 << 22, .max = 175 << 22 },
408 .p1 = { .min = 2, .max = 4 },
409 .p2 = { .p2_slow = 1, .p2_fast = 14 },
410};
411
5ab7b0b7
ID
412static const intel_limit_t intel_limits_bxt = {
413 /* FIXME: find real dot limits */
414 .dot = { .min = 0, .max = INT_MAX },
415 .vco = { .min = 4800000, .max = 6480000 },
416 .n = { .min = 1, .max = 1 },
417 .m1 = { .min = 2, .max = 2 },
418 /* FIXME: find real m2 limits */
419 .m2 = { .min = 2 << 22, .max = 255 << 22 },
420 .p1 = { .min = 2, .max = 4 },
421 .p2 = { .p2_slow = 1, .p2_fast = 20 },
422};
423
6b4bf1c4
VS
424static void vlv_clock(int refclk, intel_clock_t *clock)
425{
426 clock->m = clock->m1 * clock->m2;
427 clock->p = clock->p1 * clock->p2;
ed5ca77e
VS
428 if (WARN_ON(clock->n == 0 || clock->p == 0))
429 return;
fb03ac01
VS
430 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
431 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
6b4bf1c4
VS
432}
433
e0638cdf
PZ
434/**
435 * Returns whether any output on the specified pipe is of the specified type
436 */
4093561b 437bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
e0638cdf 438{
409ee761 439 struct drm_device *dev = crtc->base.dev;
e0638cdf
PZ
440 struct intel_encoder *encoder;
441
409ee761 442 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
e0638cdf
PZ
443 if (encoder->type == type)
444 return true;
445
446 return false;
447}
448
d0737e1d
ACO
449/**
450 * Returns whether any output on the specified pipe will have the specified
451 * type after a staged modeset is complete, i.e., the same as
452 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
453 * encoder->crtc.
454 */
a93e255f
ACO
455static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
456 int type)
d0737e1d 457{
a93e255f 458 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 459 struct drm_connector *connector;
a93e255f 460 struct drm_connector_state *connector_state;
d0737e1d 461 struct intel_encoder *encoder;
a93e255f
ACO
462 int i, num_connectors = 0;
463
da3ced29 464 for_each_connector_in_state(state, connector, connector_state, i) {
a93e255f
ACO
465 if (connector_state->crtc != crtc_state->base.crtc)
466 continue;
467
468 num_connectors++;
d0737e1d 469
a93e255f
ACO
470 encoder = to_intel_encoder(connector_state->best_encoder);
471 if (encoder->type == type)
d0737e1d 472 return true;
a93e255f
ACO
473 }
474
475 WARN_ON(num_connectors == 0);
d0737e1d
ACO
476
477 return false;
478}
479
a93e255f
ACO
480static const intel_limit_t *
481intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
2c07245f 482{
a93e255f 483 struct drm_device *dev = crtc_state->base.crtc->dev;
2c07245f 484 const intel_limit_t *limit;
b91ad0ec 485
a93e255f 486 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 487 if (intel_is_dual_link_lvds(dev)) {
1b894b59 488 if (refclk == 100000)
b91ad0ec
ZW
489 limit = &intel_limits_ironlake_dual_lvds_100m;
490 else
491 limit = &intel_limits_ironlake_dual_lvds;
492 } else {
1b894b59 493 if (refclk == 100000)
b91ad0ec
ZW
494 limit = &intel_limits_ironlake_single_lvds_100m;
495 else
496 limit = &intel_limits_ironlake_single_lvds;
497 }
c6bb3538 498 } else
b91ad0ec 499 limit = &intel_limits_ironlake_dac;
2c07245f
ZW
500
501 return limit;
502}
503
a93e255f
ACO
504static const intel_limit_t *
505intel_g4x_limit(struct intel_crtc_state *crtc_state)
044c7c41 506{
a93e255f 507 struct drm_device *dev = crtc_state->base.crtc->dev;
044c7c41
ML
508 const intel_limit_t *limit;
509
a93e255f 510 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 511 if (intel_is_dual_link_lvds(dev))
e4b36699 512 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 513 else
e4b36699 514 limit = &intel_limits_g4x_single_channel_lvds;
a93e255f
ACO
515 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
516 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
e4b36699 517 limit = &intel_limits_g4x_hdmi;
a93e255f 518 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
e4b36699 519 limit = &intel_limits_g4x_sdvo;
044c7c41 520 } else /* The option is for other outputs */
e4b36699 521 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML
522
523 return limit;
524}
525
a93e255f
ACO
526static const intel_limit_t *
527intel_limit(struct intel_crtc_state *crtc_state, int refclk)
79e53945 528{
a93e255f 529 struct drm_device *dev = crtc_state->base.crtc->dev;
79e53945
JB
530 const intel_limit_t *limit;
531
5ab7b0b7
ID
532 if (IS_BROXTON(dev))
533 limit = &intel_limits_bxt;
534 else if (HAS_PCH_SPLIT(dev))
a93e255f 535 limit = intel_ironlake_limit(crtc_state, refclk);
2c07245f 536 else if (IS_G4X(dev)) {
a93e255f 537 limit = intel_g4x_limit(crtc_state);
f2b115e6 538 } else if (IS_PINEVIEW(dev)) {
a93e255f 539 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
f2b115e6 540 limit = &intel_limits_pineview_lvds;
2177832f 541 else
f2b115e6 542 limit = &intel_limits_pineview_sdvo;
ef9348c8
CML
543 } else if (IS_CHERRYVIEW(dev)) {
544 limit = &intel_limits_chv;
a0c4da24 545 } else if (IS_VALLEYVIEW(dev)) {
dc730512 546 limit = &intel_limits_vlv;
a6c45cf0 547 } else if (!IS_GEN2(dev)) {
a93e255f 548 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
a6c45cf0
CW
549 limit = &intel_limits_i9xx_lvds;
550 else
551 limit = &intel_limits_i9xx_sdvo;
79e53945 552 } else {
a93e255f 553 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
e4b36699 554 limit = &intel_limits_i8xx_lvds;
a93e255f 555 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
e4b36699 556 limit = &intel_limits_i8xx_dvo;
5d536e28
DV
557 else
558 limit = &intel_limits_i8xx_dac;
79e53945
JB
559 }
560 return limit;
561}
562
f2b115e6
AJ
563/* m1 is reserved as 0 in Pineview, n is a ring counter */
564static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 565{
2177832f
SL
566 clock->m = clock->m2 + 2;
567 clock->p = clock->p1 * clock->p2;
ed5ca77e
VS
568 if (WARN_ON(clock->n == 0 || clock->p == 0))
569 return;
fb03ac01
VS
570 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
571 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
2177832f
SL
572}
573
7429e9d4
DV
574static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
575{
576 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
577}
578
ac58c3f0 579static void i9xx_clock(int refclk, intel_clock_t *clock)
2177832f 580{
7429e9d4 581 clock->m = i9xx_dpll_compute_m(clock);
79e53945 582 clock->p = clock->p1 * clock->p2;
ed5ca77e
VS
583 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
584 return;
fb03ac01
VS
585 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
586 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
79e53945
JB
587}
588
ef9348c8
CML
589static void chv_clock(int refclk, intel_clock_t *clock)
590{
591 clock->m = clock->m1 * clock->m2;
592 clock->p = clock->p1 * clock->p2;
593 if (WARN_ON(clock->n == 0 || clock->p == 0))
594 return;
595 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
596 clock->n << 22);
597 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
598}
599
7c04d1d9 600#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB
601/**
602 * Returns whether the given set of divisors are valid for a given refclk with
603 * the given connectors.
604 */
605
1b894b59
CW
606static bool intel_PLL_is_valid(struct drm_device *dev,
607 const intel_limit_t *limit,
608 const intel_clock_t *clock)
79e53945 609{
f01b7962
VS
610 if (clock->n < limit->n.min || limit->n.max < clock->n)
611 INTELPllInvalid("n out of range\n");
79e53945 612 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 613 INTELPllInvalid("p1 out of range\n");
79e53945 614 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 615 INTELPllInvalid("m2 out of range\n");
79e53945 616 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 617 INTELPllInvalid("m1 out of range\n");
f01b7962 618
5ab7b0b7 619 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
f01b7962
VS
620 if (clock->m1 <= clock->m2)
621 INTELPllInvalid("m1 <= m2\n");
622
5ab7b0b7 623 if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
f01b7962
VS
624 if (clock->p < limit->p.min || limit->p.max < clock->p)
625 INTELPllInvalid("p out of range\n");
626 if (clock->m < limit->m.min || limit->m.max < clock->m)
627 INTELPllInvalid("m out of range\n");
628 }
629
79e53945 630 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 631 INTELPllInvalid("vco out of range\n");
79e53945
JB
632 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
633 * connector, etc., rather than just a single range.
634 */
635 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 636 INTELPllInvalid("dot out of range\n");
79e53945
JB
637
638 return true;
639}
640
d4906093 641static bool
a93e255f
ACO
642i9xx_find_best_dpll(const intel_limit_t *limit,
643 struct intel_crtc_state *crtc_state,
cec2f356
SP
644 int target, int refclk, intel_clock_t *match_clock,
645 intel_clock_t *best_clock)
79e53945 646{
a93e255f 647 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 648 struct drm_device *dev = crtc->base.dev;
79e53945 649 intel_clock_t clock;
79e53945
JB
650 int err = target;
651
a93e255f 652 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
79e53945 653 /*
a210b028
DV
654 * For LVDS just rely on its current settings for dual-channel.
655 * We haven't figured out how to reliably set up different
656 * single/dual channel state, if we even can.
79e53945 657 */
1974cad0 658 if (intel_is_dual_link_lvds(dev))
79e53945
JB
659 clock.p2 = limit->p2.p2_fast;
660 else
661 clock.p2 = limit->p2.p2_slow;
662 } else {
663 if (target < limit->p2.dot_limit)
664 clock.p2 = limit->p2.p2_slow;
665 else
666 clock.p2 = limit->p2.p2_fast;
667 }
668
0206e353 669 memset(best_clock, 0, sizeof(*best_clock));
79e53945 670
42158660
ZY
671 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
672 clock.m1++) {
673 for (clock.m2 = limit->m2.min;
674 clock.m2 <= limit->m2.max; clock.m2++) {
c0efc387 675 if (clock.m2 >= clock.m1)
42158660
ZY
676 break;
677 for (clock.n = limit->n.min;
678 clock.n <= limit->n.max; clock.n++) {
679 for (clock.p1 = limit->p1.min;
680 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB
681 int this_err;
682
ac58c3f0
DV
683 i9xx_clock(refclk, &clock);
684 if (!intel_PLL_is_valid(dev, limit,
685 &clock))
686 continue;
687 if (match_clock &&
688 clock.p != match_clock->p)
689 continue;
690
691 this_err = abs(clock.dot - target);
692 if (this_err < err) {
693 *best_clock = clock;
694 err = this_err;
695 }
696 }
697 }
698 }
699 }
700
701 return (err != target);
702}
703
704static bool
a93e255f
ACO
705pnv_find_best_dpll(const intel_limit_t *limit,
706 struct intel_crtc_state *crtc_state,
ee9300bb
DV
707 int target, int refclk, intel_clock_t *match_clock,
708 intel_clock_t *best_clock)
79e53945 709{
a93e255f 710 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 711 struct drm_device *dev = crtc->base.dev;
79e53945 712 intel_clock_t clock;
79e53945
JB
713 int err = target;
714
a93e255f 715 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
79e53945 716 /*
a210b028
DV
717 * For LVDS just rely on its current settings for dual-channel.
718 * We haven't figured out how to reliably set up different
719 * single/dual channel state, if we even can.
79e53945 720 */
1974cad0 721 if (intel_is_dual_link_lvds(dev))
79e53945
JB
722 clock.p2 = limit->p2.p2_fast;
723 else
724 clock.p2 = limit->p2.p2_slow;
725 } else {
726 if (target < limit->p2.dot_limit)
727 clock.p2 = limit->p2.p2_slow;
728 else
729 clock.p2 = limit->p2.p2_fast;
730 }
731
0206e353 732 memset(best_clock, 0, sizeof(*best_clock));
79e53945 733
42158660
ZY
734 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
735 clock.m1++) {
736 for (clock.m2 = limit->m2.min;
737 clock.m2 <= limit->m2.max; clock.m2++) {
42158660
ZY
738 for (clock.n = limit->n.min;
739 clock.n <= limit->n.max; clock.n++) {
740 for (clock.p1 = limit->p1.min;
741 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB
742 int this_err;
743
ac58c3f0 744 pineview_clock(refclk, &clock);
1b894b59
CW
745 if (!intel_PLL_is_valid(dev, limit,
746 &clock))
79e53945 747 continue;
cec2f356
SP
748 if (match_clock &&
749 clock.p != match_clock->p)
750 continue;
79e53945
JB
751
752 this_err = abs(clock.dot - target);
753 if (this_err < err) {
754 *best_clock = clock;
755 err = this_err;
756 }
757 }
758 }
759 }
760 }
761
762 return (err != target);
763}
764
d4906093 765static bool
a93e255f
ACO
766g4x_find_best_dpll(const intel_limit_t *limit,
767 struct intel_crtc_state *crtc_state,
ee9300bb
DV
768 int target, int refclk, intel_clock_t *match_clock,
769 intel_clock_t *best_clock)
d4906093 770{
a93e255f 771 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 772 struct drm_device *dev = crtc->base.dev;
d4906093
ML
773 intel_clock_t clock;
774 int max_n;
775 bool found;
6ba770dc
AJ
776 /* approximately equals target * 0.00585 */
777 int err_most = (target >> 8) + (target >> 9);
d4906093
ML
778 found = false;
779
a93e255f 780 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 781 if (intel_is_dual_link_lvds(dev))
d4906093
ML
782 clock.p2 = limit->p2.p2_fast;
783 else
784 clock.p2 = limit->p2.p2_slow;
785 } else {
786 if (target < limit->p2.dot_limit)
787 clock.p2 = limit->p2.p2_slow;
788 else
789 clock.p2 = limit->p2.p2_fast;
790 }
791
792 memset(best_clock, 0, sizeof(*best_clock));
793 max_n = limit->n.max;
f77f13e2 794 /* based on hardware requirement, prefer smaller n to precision */
d4906093 795 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 796 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML
797 for (clock.m1 = limit->m1.max;
798 clock.m1 >= limit->m1.min; clock.m1--) {
799 for (clock.m2 = limit->m2.max;
800 clock.m2 >= limit->m2.min; clock.m2--) {
801 for (clock.p1 = limit->p1.max;
802 clock.p1 >= limit->p1.min; clock.p1--) {
803 int this_err;
804
ac58c3f0 805 i9xx_clock(refclk, &clock);
1b894b59
CW
806 if (!intel_PLL_is_valid(dev, limit,
807 &clock))
d4906093 808 continue;
1b894b59
CW
809
810 this_err = abs(clock.dot - target);
d4906093
ML
811 if (this_err < err_most) {
812 *best_clock = clock;
813 err_most = this_err;
814 max_n = clock.n;
815 found = true;
816 }
817 }
818 }
819 }
820 }
2c07245f
ZW
821 return found;
822}
823
d5dd62bd
ID
824/*
825 * Check if the calculated PLL configuration is more optimal compared to the
826 * best configuration and error found so far. Return the calculated error.
827 */
828static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
829 const intel_clock_t *calculated_clock,
830 const intel_clock_t *best_clock,
831 unsigned int best_error_ppm,
832 unsigned int *error_ppm)
833{
9ca3ba01
ID
834 /*
835 * For CHV ignore the error and consider only the P value.
836 * Prefer a bigger P value based on HW requirements.
837 */
838 if (IS_CHERRYVIEW(dev)) {
839 *error_ppm = 0;
840
841 return calculated_clock->p > best_clock->p;
842 }
843
24be4e46
ID
844 if (WARN_ON_ONCE(!target_freq))
845 return false;
846
d5dd62bd
ID
847 *error_ppm = div_u64(1000000ULL *
848 abs(target_freq - calculated_clock->dot),
849 target_freq);
850 /*
851 * Prefer a better P value over a better (smaller) error if the error
852 * is small. Ensure this preference for future configurations too by
853 * setting the error to 0.
854 */
855 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
856 *error_ppm = 0;
857
858 return true;
859 }
860
861 return *error_ppm + 10 < best_error_ppm;
862}
863
a0c4da24 864static bool
a93e255f
ACO
865vlv_find_best_dpll(const intel_limit_t *limit,
866 struct intel_crtc_state *crtc_state,
ee9300bb
DV
867 int target, int refclk, intel_clock_t *match_clock,
868 intel_clock_t *best_clock)
a0c4da24 869{
a93e255f 870 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 871 struct drm_device *dev = crtc->base.dev;
6b4bf1c4 872 intel_clock_t clock;
69e4f900 873 unsigned int bestppm = 1000000;
27e639bf
VS
874 /* min update 19.2 MHz */
875 int max_n = min(limit->n.max, refclk / 19200);
49e497ef 876 bool found = false;
a0c4da24 877
6b4bf1c4
VS
878 target *= 5; /* fast clock */
879
880 memset(best_clock, 0, sizeof(*best_clock));
a0c4da24
JB
881
882 /* based on hardware requirement, prefer smaller n to precision */
27e639bf 883 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
811bbf05 884 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
889059d8 885 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
c1a9ae43 886 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
6b4bf1c4 887 clock.p = clock.p1 * clock.p2;
a0c4da24 888 /* based on hardware requirement, prefer bigger m1,m2 values */
6b4bf1c4 889 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
d5dd62bd 890 unsigned int ppm;
69e4f900 891
6b4bf1c4
VS
892 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
893 refclk * clock.m1);
894
895 vlv_clock(refclk, &clock);
43b0ac53 896
f01b7962
VS
897 if (!intel_PLL_is_valid(dev, limit,
898 &clock))
43b0ac53
VS
899 continue;
900
d5dd62bd
ID
901 if (!vlv_PLL_is_optimal(dev, target,
902 &clock,
903 best_clock,
904 bestppm, &ppm))
905 continue;
6b4bf1c4 906
d5dd62bd
ID
907 *best_clock = clock;
908 bestppm = ppm;
909 found = true;
a0c4da24
JB
910 }
911 }
912 }
913 }
a0c4da24 914
49e497ef 915 return found;
a0c4da24 916}
a4fc5ed6 917
ef9348c8 918static bool
a93e255f
ACO
919chv_find_best_dpll(const intel_limit_t *limit,
920 struct intel_crtc_state *crtc_state,
ef9348c8
CML
921 int target, int refclk, intel_clock_t *match_clock,
922 intel_clock_t *best_clock)
923{
a93e255f 924 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 925 struct drm_device *dev = crtc->base.dev;
9ca3ba01 926 unsigned int best_error_ppm;
ef9348c8
CML
927 intel_clock_t clock;
928 uint64_t m2;
929 int found = false;
930
931 memset(best_clock, 0, sizeof(*best_clock));
9ca3ba01 932 best_error_ppm = 1000000;
ef9348c8
CML
933
934 /*
935 * Based on hardware doc, the n always set to 1, and m1 always
936 * set to 2. If requires to support 200Mhz refclk, we need to
937 * revisit this because n may not 1 anymore.
938 */
939 clock.n = 1, clock.m1 = 2;
940 target *= 5; /* fast clock */
941
942 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
943 for (clock.p2 = limit->p2.p2_fast;
944 clock.p2 >= limit->p2.p2_slow;
945 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
9ca3ba01 946 unsigned int error_ppm;
ef9348c8
CML
947
948 clock.p = clock.p1 * clock.p2;
949
950 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
951 clock.n) << 22, refclk * clock.m1);
952
953 if (m2 > INT_MAX/clock.m1)
954 continue;
955
956 clock.m2 = m2;
957
958 chv_clock(refclk, &clock);
959
960 if (!intel_PLL_is_valid(dev, limit, &clock))
961 continue;
962
9ca3ba01
ID
963 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
964 best_error_ppm, &error_ppm))
965 continue;
966
967 *best_clock = clock;
968 best_error_ppm = error_ppm;
969 found = true;
ef9348c8
CML
970 }
971 }
972
973 return found;
974}
975
5ab7b0b7
ID
976bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
977 intel_clock_t *best_clock)
978{
979 int refclk = i9xx_get_refclk(crtc_state, 0);
980
981 return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
982 target_clock, refclk, NULL, best_clock);
983}
984
20ddf665
VS
985bool intel_crtc_active(struct drm_crtc *crtc)
986{
987 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
988
989 /* Be paranoid as we can arrive here with only partial
990 * state retrieved from the hardware during setup.
991 *
241bfc38 992 * We can ditch the adjusted_mode.crtc_clock check as soon
20ddf665
VS
993 * as Haswell has gained clock readout/fastboot support.
994 *
66e514c1 995 * We can ditch the crtc->primary->fb check as soon as we can
20ddf665 996 * properly reconstruct framebuffers.
c3d1f436
MR
997 *
998 * FIXME: The intel_crtc->active here should be switched to
999 * crtc->state->active once we have proper CRTC states wired up
1000 * for atomic.
20ddf665 1001 */
c3d1f436 1002 return intel_crtc->active && crtc->primary->state->fb &&
6e3c9717 1003 intel_crtc->config->base.adjusted_mode.crtc_clock;
20ddf665
VS
1004}
1005
a5c961d1
PZ
1006enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1007 enum pipe pipe)
1008{
1009 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1010 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1011
6e3c9717 1012 return intel_crtc->config->cpu_transcoder;
a5c961d1
PZ
1013}
1014
fbf49ea2
VS
1015static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1016{
1017 struct drm_i915_private *dev_priv = dev->dev_private;
1018 u32 reg = PIPEDSL(pipe);
1019 u32 line1, line2;
1020 u32 line_mask;
1021
1022 if (IS_GEN2(dev))
1023 line_mask = DSL_LINEMASK_GEN2;
1024 else
1025 line_mask = DSL_LINEMASK_GEN3;
1026
1027 line1 = I915_READ(reg) & line_mask;
1028 mdelay(5);
1029 line2 = I915_READ(reg) & line_mask;
1030
1031 return line1 == line2;
1032}
1033
ab7ad7f6
KP
1034/*
1035 * intel_wait_for_pipe_off - wait for pipe to turn off
575f7ab7 1036 * @crtc: crtc whose pipe to wait for
9d0498a2
JB
1037 *
1038 * After disabling a pipe, we can't wait for vblank in the usual way,
1039 * spinning on the vblank interrupt status bit, since we won't actually
1040 * see an interrupt when the pipe is disabled.
1041 *
ab7ad7f6
KP
1042 * On Gen4 and above:
1043 * wait for the pipe register state bit to turn off
1044 *
1045 * Otherwise:
1046 * wait for the display line value to settle (it usually
1047 * ends up stopping at the start of the next frame).
58e10eb9 1048 *
9d0498a2 1049 */
575f7ab7 1050static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
9d0498a2 1051{
575f7ab7 1052 struct drm_device *dev = crtc->base.dev;
9d0498a2 1053 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 1054 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
575f7ab7 1055 enum pipe pipe = crtc->pipe;
ab7ad7f6
KP
1056
1057 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 1058 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP
1059
1060 /* Wait for the Pipe State to go off */
58e10eb9
CW
1061 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1062 100))
284637d9 1063 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1064 } else {
ab7ad7f6 1065 /* Wait for the display line to settle */
fbf49ea2 1066 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
284637d9 1067 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1068 }
79e53945
JB
1069}
1070
b0ea7d37
DL
1071/*
1072 * ibx_digital_port_connected - is the specified port connected?
1073 * @dev_priv: i915 private structure
1074 * @port: the port to test
1075 *
1076 * Returns true if @port is connected, false otherwise.
1077 */
1078bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1079 struct intel_digital_port *port)
1080{
1081 u32 bit;
1082
c36346e3 1083 if (HAS_PCH_IBX(dev_priv->dev)) {
eba905b2 1084 switch (port->port) {
c36346e3
DL
1085 case PORT_B:
1086 bit = SDE_PORTB_HOTPLUG;
1087 break;
1088 case PORT_C:
1089 bit = SDE_PORTC_HOTPLUG;
1090 break;
1091 case PORT_D:
1092 bit = SDE_PORTD_HOTPLUG;
1093 break;
1094 default:
1095 return true;
1096 }
1097 } else {
eba905b2 1098 switch (port->port) {
c36346e3
DL
1099 case PORT_B:
1100 bit = SDE_PORTB_HOTPLUG_CPT;
1101 break;
1102 case PORT_C:
1103 bit = SDE_PORTC_HOTPLUG_CPT;
1104 break;
1105 case PORT_D:
1106 bit = SDE_PORTD_HOTPLUG_CPT;
1107 break;
1108 default:
1109 return true;
1110 }
b0ea7d37
DL
1111 }
1112
1113 return I915_READ(SDEISR) & bit;
1114}
1115
b24e7179
JB
1116static const char *state_string(bool enabled)
1117{
1118 return enabled ? "on" : "off";
1119}
1120
1121/* Only for pre-ILK configs */
55607e8a
DV
1122void assert_pll(struct drm_i915_private *dev_priv,
1123 enum pipe pipe, bool state)
b24e7179
JB
1124{
1125 int reg;
1126 u32 val;
1127 bool cur_state;
1128
1129 reg = DPLL(pipe);
1130 val = I915_READ(reg);
1131 cur_state = !!(val & DPLL_VCO_ENABLE);
e2c719b7 1132 I915_STATE_WARN(cur_state != state,
b24e7179
JB
1133 "PLL state assertion failure (expected %s, current %s)\n",
1134 state_string(state), state_string(cur_state));
1135}
b24e7179 1136
23538ef1
JN
1137/* XXX: the dsi pll is shared between MIPI DSI ports */
1138static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1139{
1140 u32 val;
1141 bool cur_state;
1142
a580516d 1143 mutex_lock(&dev_priv->sb_lock);
23538ef1 1144 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
a580516d 1145 mutex_unlock(&dev_priv->sb_lock);
23538ef1
JN
1146
1147 cur_state = val & DSI_PLL_VCO_EN;
e2c719b7 1148 I915_STATE_WARN(cur_state != state,
23538ef1
JN
1149 "DSI PLL state assertion failure (expected %s, current %s)\n",
1150 state_string(state), state_string(cur_state));
1151}
1152#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1153#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1154
55607e8a 1155struct intel_shared_dpll *
e2b78267
DV
1156intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1157{
1158 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1159
6e3c9717 1160 if (crtc->config->shared_dpll < 0)
e2b78267
DV
1161 return NULL;
1162
6e3c9717 1163 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
e2b78267
DV
1164}
1165
040484af 1166/* For ILK+ */
55607e8a
DV
1167void assert_shared_dpll(struct drm_i915_private *dev_priv,
1168 struct intel_shared_dpll *pll,
1169 bool state)
040484af 1170{
040484af 1171 bool cur_state;
5358901f 1172 struct intel_dpll_hw_state hw_state;
040484af 1173
92b27b08 1174 if (WARN (!pll,
46edb027 1175 "asserting DPLL %s with no DPLL\n", state_string(state)))
ee7b9f93 1176 return;
ee7b9f93 1177
5358901f 1178 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
e2c719b7 1179 I915_STATE_WARN(cur_state != state,
5358901f
DV
1180 "%s assertion failure (expected %s, current %s)\n",
1181 pll->name, state_string(state), state_string(cur_state));
040484af 1182}
040484af
JB
1183
1184static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1185 enum pipe pipe, bool state)
1186{
1187 int reg;
1188 u32 val;
1189 bool cur_state;
ad80a810
PZ
1190 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1191 pipe);
040484af 1192
affa9354
PZ
1193 if (HAS_DDI(dev_priv->dev)) {
1194 /* DDI does not have a specific FDI_TX register */
ad80a810 1195 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 1196 val = I915_READ(reg);
ad80a810 1197 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED
1198 } else {
1199 reg = FDI_TX_CTL(pipe);
1200 val = I915_READ(reg);
1201 cur_state = !!(val & FDI_TX_ENABLE);
1202 }
e2c719b7 1203 I915_STATE_WARN(cur_state != state,
040484af
JB
1204 "FDI TX state assertion failure (expected %s, current %s)\n",
1205 state_string(state), state_string(cur_state));
1206}
1207#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1208#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1209
1210static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1211 enum pipe pipe, bool state)
1212{
1213 int reg;
1214 u32 val;
1215 bool cur_state;
1216
d63fa0dc
PZ
1217 reg = FDI_RX_CTL(pipe);
1218 val = I915_READ(reg);
1219 cur_state = !!(val & FDI_RX_ENABLE);
e2c719b7 1220 I915_STATE_WARN(cur_state != state,
040484af
JB
1221 "FDI RX state assertion failure (expected %s, current %s)\n",
1222 state_string(state), state_string(cur_state));
1223}
1224#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1225#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1226
1227static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1228 enum pipe pipe)
1229{
1230 int reg;
1231 u32 val;
1232
1233 /* ILK FDI PLL is always enabled */
3d13ef2e 1234 if (INTEL_INFO(dev_priv->dev)->gen == 5)
040484af
JB
1235 return;
1236
bf507ef7 1237 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1238 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED
1239 return;
1240
040484af
JB
1241 reg = FDI_TX_CTL(pipe);
1242 val = I915_READ(reg);
e2c719b7 1243 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
040484af
JB
1244}
1245
55607e8a
DV
1246void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1247 enum pipe pipe, bool state)
040484af
JB
1248{
1249 int reg;
1250 u32 val;
55607e8a 1251 bool cur_state;
040484af
JB
1252
1253 reg = FDI_RX_CTL(pipe);
1254 val = I915_READ(reg);
55607e8a 1255 cur_state = !!(val & FDI_RX_PLL_ENABLE);
e2c719b7 1256 I915_STATE_WARN(cur_state != state,
55607e8a
DV
1257 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1258 state_string(state), state_string(cur_state));
040484af
JB
1259}
1260
b680c37a
DV
1261void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1262 enum pipe pipe)
ea0760cf 1263{
bedd4dba
JN
1264 struct drm_device *dev = dev_priv->dev;
1265 int pp_reg;
ea0760cf
JB
1266 u32 val;
1267 enum pipe panel_pipe = PIPE_A;
0de3b485 1268 bool locked = true;
ea0760cf 1269
bedd4dba
JN
1270 if (WARN_ON(HAS_DDI(dev)))
1271 return;
1272
1273 if (HAS_PCH_SPLIT(dev)) {
1274 u32 port_sel;
1275
ea0760cf 1276 pp_reg = PCH_PP_CONTROL;
bedd4dba
JN
1277 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1278
1279 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1280 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1281 panel_pipe = PIPE_B;
1282 /* XXX: else fix for eDP */
1283 } else if (IS_VALLEYVIEW(dev)) {
1284 /* presumably write lock depends on pipe, not port select */
1285 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1286 panel_pipe = pipe;
ea0760cf
JB
1287 } else {
1288 pp_reg = PP_CONTROL;
bedd4dba
JN
1289 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1290 panel_pipe = PIPE_B;
ea0760cf
JB
1291 }
1292
1293 val = I915_READ(pp_reg);
1294 if (!(val & PANEL_POWER_ON) ||
ec49ba2d 1295 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
ea0760cf
JB
1296 locked = false;
1297
e2c719b7 1298 I915_STATE_WARN(panel_pipe == pipe && locked,
ea0760cf 1299 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1300 pipe_name(pipe));
ea0760cf
JB
1301}
1302
93ce0ba6
JN
1303static void assert_cursor(struct drm_i915_private *dev_priv,
1304 enum pipe pipe, bool state)
1305{
1306 struct drm_device *dev = dev_priv->dev;
1307 bool cur_state;
1308
d9d82081 1309 if (IS_845G(dev) || IS_I865G(dev))
93ce0ba6 1310 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
d9d82081 1311 else
5efb3e28 1312 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
93ce0ba6 1313
e2c719b7 1314 I915_STATE_WARN(cur_state != state,
93ce0ba6
JN
1315 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1316 pipe_name(pipe), state_string(state), state_string(cur_state));
1317}
1318#define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1319#define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1320
b840d907
JB
1321void assert_pipe(struct drm_i915_private *dev_priv,
1322 enum pipe pipe, bool state)
b24e7179
JB
1323{
1324 int reg;
1325 u32 val;
63d7bbe9 1326 bool cur_state;
702e7a56
PZ
1327 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1328 pipe);
b24e7179 1329
b6b5d049
VS
1330 /* if we need the pipe quirk it must be always on */
1331 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1332 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
8e636784
DV
1333 state = true;
1334
f458ebbc 1335 if (!intel_display_power_is_enabled(dev_priv,
b97186f0 1336 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
69310161
PZ
1337 cur_state = false;
1338 } else {
1339 reg = PIPECONF(cpu_transcoder);
1340 val = I915_READ(reg);
1341 cur_state = !!(val & PIPECONF_ENABLE);
1342 }
1343
e2c719b7 1344 I915_STATE_WARN(cur_state != state,
63d7bbe9 1345 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1346 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB
1347}
1348
931872fc
CW
1349static void assert_plane(struct drm_i915_private *dev_priv,
1350 enum plane plane, bool state)
b24e7179
JB
1351{
1352 int reg;
1353 u32 val;
931872fc 1354 bool cur_state;
b24e7179
JB
1355
1356 reg = DSPCNTR(plane);
1357 val = I915_READ(reg);
931872fc 1358 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
e2c719b7 1359 I915_STATE_WARN(cur_state != state,
931872fc
CW
1360 "plane %c assertion failure (expected %s, current %s)\n",
1361 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB
1362}
1363
931872fc
CW
1364#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1365#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1366
b24e7179
JB
1367static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1368 enum pipe pipe)
1369{
653e1026 1370 struct drm_device *dev = dev_priv->dev;
b24e7179
JB
1371 int reg, i;
1372 u32 val;
1373 int cur_pipe;
1374
653e1026
VS
1375 /* Primary planes are fixed to pipes on gen4+ */
1376 if (INTEL_INFO(dev)->gen >= 4) {
28c05794
AJ
1377 reg = DSPCNTR(pipe);
1378 val = I915_READ(reg);
e2c719b7 1379 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
28c05794
AJ
1380 "plane %c assertion failure, should be disabled but not\n",
1381 plane_name(pipe));
19ec1358 1382 return;
28c05794 1383 }
19ec1358 1384
b24e7179 1385 /* Need to check both planes against the pipe */
055e393f 1386 for_each_pipe(dev_priv, i) {
b24e7179
JB
1387 reg = DSPCNTR(i);
1388 val = I915_READ(reg);
1389 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1390 DISPPLANE_SEL_PIPE_SHIFT;
e2c719b7 1391 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB
1392 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1393 plane_name(i), pipe_name(pipe));
b24e7179
JB
1394 }
1395}
1396
19332d7a
JB
1397static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1398 enum pipe pipe)
1399{
20674eef 1400 struct drm_device *dev = dev_priv->dev;
1fe47785 1401 int reg, sprite;
19332d7a
JB
1402 u32 val;
1403
7feb8b88 1404 if (INTEL_INFO(dev)->gen >= 9) {
3bdcfc0c 1405 for_each_sprite(dev_priv, pipe, sprite) {
7feb8b88 1406 val = I915_READ(PLANE_CTL(pipe, sprite));
e2c719b7 1407 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
7feb8b88
DL
1408 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1409 sprite, pipe_name(pipe));
1410 }
1411 } else if (IS_VALLEYVIEW(dev)) {
3bdcfc0c 1412 for_each_sprite(dev_priv, pipe, sprite) {
1fe47785 1413 reg = SPCNTR(pipe, sprite);
20674eef 1414 val = I915_READ(reg);
e2c719b7 1415 I915_STATE_WARN(val & SP_ENABLE,
20674eef 1416 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1fe47785 1417 sprite_name(pipe, sprite), pipe_name(pipe));
20674eef
VS
1418 }
1419 } else if (INTEL_INFO(dev)->gen >= 7) {
1420 reg = SPRCTL(pipe);
19332d7a 1421 val = I915_READ(reg);
e2c719b7 1422 I915_STATE_WARN(val & SPRITE_ENABLE,
06da8da2 1423 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef
VS
1424 plane_name(pipe), pipe_name(pipe));
1425 } else if (INTEL_INFO(dev)->gen >= 5) {
1426 reg = DVSCNTR(pipe);
19332d7a 1427 val = I915_READ(reg);
e2c719b7 1428 I915_STATE_WARN(val & DVS_ENABLE,
06da8da2 1429 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef 1430 plane_name(pipe), pipe_name(pipe));
19332d7a
JB
1431 }
1432}
1433
08c71e5e
VS
1434static void assert_vblank_disabled(struct drm_crtc *crtc)
1435{
e2c719b7 1436 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
08c71e5e
VS
1437 drm_crtc_vblank_put(crtc);
1438}
1439
89eff4be 1440static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
92f2584a
JB
1441{
1442 u32 val;
1443 bool enabled;
1444
e2c719b7 1445 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
9d82aa17 1446
92f2584a
JB
1447 val = I915_READ(PCH_DREF_CONTROL);
1448 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1449 DREF_SUPERSPREAD_SOURCE_MASK));
e2c719b7 1450 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
92f2584a
JB
1451}
1452
ab9412ba
DV
1453static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1454 enum pipe pipe)
92f2584a
JB
1455{
1456 int reg;
1457 u32 val;
1458 bool enabled;
1459
ab9412ba 1460 reg = PCH_TRANSCONF(pipe);
92f2584a
JB
1461 val = I915_READ(reg);
1462 enabled = !!(val & TRANS_ENABLE);
e2c719b7 1463 I915_STATE_WARN(enabled,
9db4a9c7
JB
1464 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1465 pipe_name(pipe));
92f2584a
JB
1466}
1467
4e634389
KP
1468static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1469 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP
1470{
1471 if ((val & DP_PORT_EN) == 0)
1472 return false;
1473
1474 if (HAS_PCH_CPT(dev_priv->dev)) {
1475 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1476 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1477 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1478 return false;
44f37d1f
CML
1479 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1480 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1481 return false;
f0575e92
KP
1482 } else {
1483 if ((val & DP_PIPE_MASK) != (pipe << 30))
1484 return false;
1485 }
1486 return true;
1487}
1488
1519b995
KP
1489static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1490 enum pipe pipe, u32 val)
1491{
dc0fa718 1492 if ((val & SDVO_ENABLE) == 0)
1519b995
KP
1493 return false;
1494
1495 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1496 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995 1497 return false;
44f37d1f
CML
1498 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1499 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1500 return false;
1519b995 1501 } else {
dc0fa718 1502 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP
1503 return false;
1504 }
1505 return true;
1506}
1507
1508static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1509 enum pipe pipe, u32 val)
1510{
1511 if ((val & LVDS_PORT_EN) == 0)
1512 return false;
1513
1514 if (HAS_PCH_CPT(dev_priv->dev)) {
1515 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1516 return false;
1517 } else {
1518 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1519 return false;
1520 }
1521 return true;
1522}
1523
1524static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1525 enum pipe pipe, u32 val)
1526{
1527 if ((val & ADPA_DAC_ENABLE) == 0)
1528 return false;
1529 if (HAS_PCH_CPT(dev_priv->dev)) {
1530 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1531 return false;
1532 } else {
1533 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1534 return false;
1535 }
1536 return true;
1537}
1538
291906f1 1539static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1540 enum pipe pipe, int reg, u32 port_sel)
291906f1 1541{
47a05eca 1542 u32 val = I915_READ(reg);
e2c719b7 1543 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1544 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1545 reg, pipe_name(pipe));
de9a35ab 1546
e2c719b7 1547 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
75c5da27 1548 && (val & DP_PIPEB_SELECT),
de9a35ab 1549 "IBX PCH dp port still using transcoder B\n");
291906f1
JB
1550}
1551
1552static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1553 enum pipe pipe, int reg)
1554{
47a05eca 1555 u32 val = I915_READ(reg);
e2c719b7 1556 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1557 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1558 reg, pipe_name(pipe));
de9a35ab 1559
e2c719b7 1560 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1561 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1562 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB
1563}
1564
1565static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1566 enum pipe pipe)
1567{
1568 int reg;
1569 u32 val;
291906f1 1570
f0575e92
KP
1571 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1572 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1573 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB
1574
1575 reg = PCH_ADPA;
1576 val = I915_READ(reg);
e2c719b7 1577 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1578 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1579 pipe_name(pipe));
291906f1
JB
1580
1581 reg = PCH_LVDS;
1582 val = I915_READ(reg);
e2c719b7 1583 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1584 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1585 pipe_name(pipe));
291906f1 1586
e2debe91
PZ
1587 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1588 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1589 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB
1590}
1591
40e9cf64
JB
1592static void intel_init_dpio(struct drm_device *dev)
1593{
1594 struct drm_i915_private *dev_priv = dev->dev_private;
1595
1596 if (!IS_VALLEYVIEW(dev))
1597 return;
1598
a09caddd
CML
1599 /*
1600 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1601 * CHV x1 PHY (DP/HDMI D)
1602 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1603 */
1604 if (IS_CHERRYVIEW(dev)) {
1605 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1606 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1607 } else {
1608 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1609 }
5382f5f3
JB
1610}
1611
d288f65f 1612static void vlv_enable_pll(struct intel_crtc *crtc,
5cec258b 1613 const struct intel_crtc_state *pipe_config)
87442f73 1614{
426115cf
DV
1615 struct drm_device *dev = crtc->base.dev;
1616 struct drm_i915_private *dev_priv = dev->dev_private;
1617 int reg = DPLL(crtc->pipe);
d288f65f 1618 u32 dpll = pipe_config->dpll_hw_state.dpll;
87442f73 1619
426115cf 1620 assert_pipe_disabled(dev_priv, crtc->pipe);
87442f73
DV
1621
1622 /* No really, not for ILK+ */
1623 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1624
1625 /* PLL is protected by panel, make sure we can write it */
6a9e7363 1626 if (IS_MOBILE(dev_priv->dev))
426115cf 1627 assert_panel_unlocked(dev_priv, crtc->pipe);
87442f73 1628
426115cf
DV
1629 I915_WRITE(reg, dpll);
1630 POSTING_READ(reg);
1631 udelay(150);
1632
1633 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1634 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1635
d288f65f 1636 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
426115cf 1637 POSTING_READ(DPLL_MD(crtc->pipe));
87442f73
DV
1638
1639 /* We do this three times for luck */
426115cf 1640 I915_WRITE(reg, dpll);
87442f73
DV
1641 POSTING_READ(reg);
1642 udelay(150); /* wait for warmup */
426115cf 1643 I915_WRITE(reg, dpll);
87442f73
DV
1644 POSTING_READ(reg);
1645 udelay(150); /* wait for warmup */
426115cf 1646 I915_WRITE(reg, dpll);
87442f73
DV
1647 POSTING_READ(reg);
1648 udelay(150); /* wait for warmup */
1649}
1650
d288f65f 1651static void chv_enable_pll(struct intel_crtc *crtc,
5cec258b 1652 const struct intel_crtc_state *pipe_config)
9d556c99
CML
1653{
1654 struct drm_device *dev = crtc->base.dev;
1655 struct drm_i915_private *dev_priv = dev->dev_private;
1656 int pipe = crtc->pipe;
1657 enum dpio_channel port = vlv_pipe_to_channel(pipe);
9d556c99
CML
1658 u32 tmp;
1659
1660 assert_pipe_disabled(dev_priv, crtc->pipe);
1661
1662 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1663
a580516d 1664 mutex_lock(&dev_priv->sb_lock);
9d556c99
CML
1665
1666 /* Enable back the 10bit clock to display controller */
1667 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1668 tmp |= DPIO_DCLKP_EN;
1669 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1670
54433e91
VS
1671 mutex_unlock(&dev_priv->sb_lock);
1672
9d556c99
CML
1673 /*
1674 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1675 */
1676 udelay(1);
1677
1678 /* Enable PLL */
d288f65f 1679 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
9d556c99
CML
1680
1681 /* Check PLL is locked */
a11b0703 1682 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
9d556c99
CML
1683 DRM_ERROR("PLL %d failed to lock\n", pipe);
1684
a11b0703 1685 /* not sure when this should be written */
d288f65f 1686 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
a11b0703 1687 POSTING_READ(DPLL_MD(pipe));
9d556c99
CML
1688}
1689
1c4e0274
VS
1690static int intel_num_dvo_pipes(struct drm_device *dev)
1691{
1692 struct intel_crtc *crtc;
1693 int count = 0;
1694
1695 for_each_intel_crtc(dev, crtc)
1696 count += crtc->active &&
409ee761 1697 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1c4e0274
VS
1698
1699 return count;
1700}
1701
66e3d5c0 1702static void i9xx_enable_pll(struct intel_crtc *crtc)
63d7bbe9 1703{
66e3d5c0
DV
1704 struct drm_device *dev = crtc->base.dev;
1705 struct drm_i915_private *dev_priv = dev->dev_private;
1706 int reg = DPLL(crtc->pipe);
6e3c9717 1707 u32 dpll = crtc->config->dpll_hw_state.dpll;
63d7bbe9 1708
66e3d5c0 1709 assert_pipe_disabled(dev_priv, crtc->pipe);
58c6eaa2 1710
63d7bbe9 1711 /* No really, not for ILK+ */
3d13ef2e 1712 BUG_ON(INTEL_INFO(dev)->gen >= 5);
63d7bbe9
JB
1713
1714 /* PLL is protected by panel, make sure we can write it */
66e3d5c0
DV
1715 if (IS_MOBILE(dev) && !IS_I830(dev))
1716 assert_panel_unlocked(dev_priv, crtc->pipe);
63d7bbe9 1717
1c4e0274
VS
1718 /* Enable DVO 2x clock on both PLLs if necessary */
1719 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1720 /*
1721 * It appears to be important that we don't enable this
1722 * for the current pipe before otherwise configuring the
1723 * PLL. No idea how this should be handled if multiple
1724 * DVO outputs are enabled simultaneosly.
1725 */
1726 dpll |= DPLL_DVO_2X_MODE;
1727 I915_WRITE(DPLL(!crtc->pipe),
1728 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1729 }
66e3d5c0
DV
1730
1731 /* Wait for the clocks to stabilize. */
1732 POSTING_READ(reg);
1733 udelay(150);
1734
1735 if (INTEL_INFO(dev)->gen >= 4) {
1736 I915_WRITE(DPLL_MD(crtc->pipe),
6e3c9717 1737 crtc->config->dpll_hw_state.dpll_md);
66e3d5c0
DV
1738 } else {
1739 /* The pixel multiplier can only be updated once the
1740 * DPLL is enabled and the clocks are stable.
1741 *
1742 * So write it again.
1743 */
1744 I915_WRITE(reg, dpll);
1745 }
63d7bbe9
JB
1746
1747 /* We do this three times for luck */
66e3d5c0 1748 I915_WRITE(reg, dpll);
63d7bbe9
JB
1749 POSTING_READ(reg);
1750 udelay(150); /* wait for warmup */
66e3d5c0 1751 I915_WRITE(reg, dpll);
63d7bbe9
JB
1752 POSTING_READ(reg);
1753 udelay(150); /* wait for warmup */
66e3d5c0 1754 I915_WRITE(reg, dpll);
63d7bbe9
JB
1755 POSTING_READ(reg);
1756 udelay(150); /* wait for warmup */
1757}
1758
1759/**
50b44a44 1760 * i9xx_disable_pll - disable a PLL
63d7bbe9
JB
1761 * @dev_priv: i915 private structure
1762 * @pipe: pipe PLL to disable
1763 *
1764 * Disable the PLL for @pipe, making sure the pipe is off first.
1765 *
1766 * Note! This is for pre-ILK only.
1767 */
1c4e0274 1768static void i9xx_disable_pll(struct intel_crtc *crtc)
63d7bbe9 1769{
1c4e0274
VS
1770 struct drm_device *dev = crtc->base.dev;
1771 struct drm_i915_private *dev_priv = dev->dev_private;
1772 enum pipe pipe = crtc->pipe;
1773
1774 /* Disable DVO 2x clock on both PLLs if necessary */
1775 if (IS_I830(dev) &&
409ee761 1776 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1c4e0274
VS
1777 intel_num_dvo_pipes(dev) == 1) {
1778 I915_WRITE(DPLL(PIPE_B),
1779 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1780 I915_WRITE(DPLL(PIPE_A),
1781 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1782 }
1783
b6b5d049
VS
1784 /* Don't disable pipe or pipe PLLs if needed */
1785 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1786 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
63d7bbe9
JB
1787 return;
1788
1789 /* Make sure the pipe isn't still relying on us */
1790 assert_pipe_disabled(dev_priv, pipe);
1791
50b44a44
DV
1792 I915_WRITE(DPLL(pipe), 0);
1793 POSTING_READ(DPLL(pipe));
63d7bbe9
JB
1794}
1795
f6071166
JB
1796static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1797{
1798 u32 val = 0;
1799
1800 /* Make sure the pipe isn't still relying on us */
1801 assert_pipe_disabled(dev_priv, pipe);
1802
e5cbfbfb
ID
1803 /*
1804 * Leave integrated clock source and reference clock enabled for pipe B.
1805 * The latter is needed for VGA hotplug / manual detection.
1806 */
f6071166 1807 if (pipe == PIPE_B)
e5cbfbfb 1808 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
f6071166
JB
1809 I915_WRITE(DPLL(pipe), val);
1810 POSTING_READ(DPLL(pipe));
076ed3b2
CML
1811
1812}
1813
1814static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1815{
d752048d 1816 enum dpio_channel port = vlv_pipe_to_channel(pipe);
076ed3b2
CML
1817 u32 val;
1818
a11b0703
VS
1819 /* Make sure the pipe isn't still relying on us */
1820 assert_pipe_disabled(dev_priv, pipe);
076ed3b2 1821
a11b0703 1822 /* Set PLL en = 0 */
d17ec4ce 1823 val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
a11b0703
VS
1824 if (pipe != PIPE_A)
1825 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1826 I915_WRITE(DPLL(pipe), val);
1827 POSTING_READ(DPLL(pipe));
d752048d 1828
a580516d 1829 mutex_lock(&dev_priv->sb_lock);
d752048d
VS
1830
1831 /* Disable 10bit clock to display controller */
1832 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1833 val &= ~DPIO_DCLKP_EN;
1834 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1835
61407f6d
VS
1836 /* disable left/right clock distribution */
1837 if (pipe != PIPE_B) {
1838 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1839 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1840 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1841 } else {
1842 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1843 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1844 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1845 }
1846
a580516d 1847 mutex_unlock(&dev_priv->sb_lock);
f6071166
JB
1848}
1849
e4607fcf 1850void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
9b6de0a1
VS
1851 struct intel_digital_port *dport,
1852 unsigned int expected_mask)
89b667f8
JB
1853{
1854 u32 port_mask;
00fc31b7 1855 int dpll_reg;
89b667f8 1856
e4607fcf
CML
1857 switch (dport->port) {
1858 case PORT_B:
89b667f8 1859 port_mask = DPLL_PORTB_READY_MASK;
00fc31b7 1860 dpll_reg = DPLL(0);
e4607fcf
CML
1861 break;
1862 case PORT_C:
89b667f8 1863 port_mask = DPLL_PORTC_READY_MASK;
00fc31b7 1864 dpll_reg = DPLL(0);
9b6de0a1 1865 expected_mask <<= 4;
00fc31b7
CML
1866 break;
1867 case PORT_D:
1868 port_mask = DPLL_PORTD_READY_MASK;
1869 dpll_reg = DPIO_PHY_STATUS;
e4607fcf
CML
1870 break;
1871 default:
1872 BUG();
1873 }
89b667f8 1874
9b6de0a1
VS
1875 if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1876 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1877 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
89b667f8
JB
1878}
1879
b14b1055
DV
1880static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1881{
1882 struct drm_device *dev = crtc->base.dev;
1883 struct drm_i915_private *dev_priv = dev->dev_private;
1884 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1885
be19f0ff
CW
1886 if (WARN_ON(pll == NULL))
1887 return;
1888
3e369b76 1889 WARN_ON(!pll->config.crtc_mask);
b14b1055
DV
1890 if (pll->active == 0) {
1891 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1892 WARN_ON(pll->on);
1893 assert_shared_dpll_disabled(dev_priv, pll);
1894
1895 pll->mode_set(dev_priv, pll);
1896 }
1897}
1898
92f2584a 1899/**
85b3894f 1900 * intel_enable_shared_dpll - enable PCH PLL
92f2584a
JB
1901 * @dev_priv: i915 private structure
1902 * @pipe: pipe PLL to enable
1903 *
1904 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1905 * drives the transcoder clock.
1906 */
85b3894f 1907static void intel_enable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1908{
3d13ef2e
DL
1909 struct drm_device *dev = crtc->base.dev;
1910 struct drm_i915_private *dev_priv = dev->dev_private;
e2b78267 1911 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
92f2584a 1912
87a875bb 1913 if (WARN_ON(pll == NULL))
48da64a8
CW
1914 return;
1915
3e369b76 1916 if (WARN_ON(pll->config.crtc_mask == 0))
48da64a8 1917 return;
ee7b9f93 1918
74dd6928 1919 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
46edb027 1920 pll->name, pll->active, pll->on,
e2b78267 1921 crtc->base.base.id);
92f2584a 1922
cdbd2316
DV
1923 if (pll->active++) {
1924 WARN_ON(!pll->on);
e9d6944e 1925 assert_shared_dpll_enabled(dev_priv, pll);
ee7b9f93
JB
1926 return;
1927 }
f4a091c7 1928 WARN_ON(pll->on);
ee7b9f93 1929
bd2bb1b9
PZ
1930 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1931
46edb027 1932 DRM_DEBUG_KMS("enabling %s\n", pll->name);
e7b903d2 1933 pll->enable(dev_priv, pll);
ee7b9f93 1934 pll->on = true;
92f2584a
JB
1935}
1936
f6daaec2 1937static void intel_disable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1938{
3d13ef2e
DL
1939 struct drm_device *dev = crtc->base.dev;
1940 struct drm_i915_private *dev_priv = dev->dev_private;
e2b78267 1941 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4c609cb8 1942
92f2584a 1943 /* PCH only available on ILK+ */
3d13ef2e 1944 BUG_ON(INTEL_INFO(dev)->gen < 5);
87a875bb 1945 if (WARN_ON(pll == NULL))
ee7b9f93 1946 return;
92f2584a 1947
3e369b76 1948 if (WARN_ON(pll->config.crtc_mask == 0))
48da64a8 1949 return;
7a419866 1950
46edb027
DV
1951 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1952 pll->name, pll->active, pll->on,
e2b78267 1953 crtc->base.base.id);
7a419866 1954
48da64a8 1955 if (WARN_ON(pll->active == 0)) {
e9d6944e 1956 assert_shared_dpll_disabled(dev_priv, pll);
48da64a8
CW
1957 return;
1958 }
1959
e9d6944e 1960 assert_shared_dpll_enabled(dev_priv, pll);
f4a091c7 1961 WARN_ON(!pll->on);
cdbd2316 1962 if (--pll->active)
7a419866 1963 return;
ee7b9f93 1964
46edb027 1965 DRM_DEBUG_KMS("disabling %s\n", pll->name);
e7b903d2 1966 pll->disable(dev_priv, pll);
ee7b9f93 1967 pll->on = false;
bd2bb1b9
PZ
1968
1969 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
92f2584a
JB
1970}
1971
b8a4f404
PZ
1972static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1973 enum pipe pipe)
040484af 1974{
23670b32 1975 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1976 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
e2b78267 1977 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
23670b32 1978 uint32_t reg, val, pipeconf_val;
040484af
JB
1979
1980 /* PCH only available on ILK+ */
55522f37 1981 BUG_ON(!HAS_PCH_SPLIT(dev));
040484af
JB
1982
1983 /* Make sure PCH DPLL is enabled */
e72f9fbf 1984 assert_shared_dpll_enabled(dev_priv,
e9d6944e 1985 intel_crtc_to_shared_dpll(intel_crtc));
040484af
JB
1986
1987 /* FDI must be feeding us bits for PCH ports */
1988 assert_fdi_tx_enabled(dev_priv, pipe);
1989 assert_fdi_rx_enabled(dev_priv, pipe);
1990
23670b32
DV
1991 if (HAS_PCH_CPT(dev)) {
1992 /* Workaround: Set the timing override bit before enabling the
1993 * pch transcoder. */
1994 reg = TRANS_CHICKEN2(pipe);
1995 val = I915_READ(reg);
1996 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1997 I915_WRITE(reg, val);
59c859d6 1998 }
23670b32 1999
ab9412ba 2000 reg = PCH_TRANSCONF(pipe);
040484af 2001 val = I915_READ(reg);
5f7f726d 2002 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB
2003
2004 if (HAS_PCH_IBX(dev_priv->dev)) {
2005 /*
2006 * make the BPC in transcoder be consistent with
2007 * that in pipeconf reg.
2008 */
dfd07d72
DV
2009 val &= ~PIPECONF_BPC_MASK;
2010 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 2011 }
5f7f726d
PZ
2012
2013 val &= ~TRANS_INTERLACE_MASK;
2014 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6 2015 if (HAS_PCH_IBX(dev_priv->dev) &&
409ee761 2016 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7c26e5c6
PZ
2017 val |= TRANS_LEGACY_INTERLACED_ILK;
2018 else
2019 val |= TRANS_INTERLACED;
5f7f726d
PZ
2020 else
2021 val |= TRANS_PROGRESSIVE;
2022
040484af
JB
2023 I915_WRITE(reg, val | TRANS_ENABLE);
2024 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 2025 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB
2026}
2027
8fb033d7 2028static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 2029 enum transcoder cpu_transcoder)
040484af 2030{
8fb033d7 2031 u32 val, pipeconf_val;
8fb033d7
PZ
2032
2033 /* PCH only available on ILK+ */
55522f37 2034 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
8fb033d7 2035
8fb033d7 2036 /* FDI must be feeding us bits for PCH ports */
1a240d4d 2037 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 2038 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 2039
223a6fdf
PZ
2040 /* Workaround: set timing override bit. */
2041 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 2042 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ
2043 I915_WRITE(_TRANSA_CHICKEN2, val);
2044
25f3ef11 2045 val = TRANS_ENABLE;
937bb610 2046 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 2047
9a76b1c6
PZ
2048 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2049 PIPECONF_INTERLACED_ILK)
a35f2679 2050 val |= TRANS_INTERLACED;
8fb033d7
PZ
2051 else
2052 val |= TRANS_PROGRESSIVE;
2053
ab9412ba
DV
2054 I915_WRITE(LPT_TRANSCONF, val);
2055 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
937bb610 2056 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ
2057}
2058
b8a4f404
PZ
2059static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2060 enum pipe pipe)
040484af 2061{
23670b32
DV
2062 struct drm_device *dev = dev_priv->dev;
2063 uint32_t reg, val;
040484af
JB
2064
2065 /* FDI relies on the transcoder */
2066 assert_fdi_tx_disabled(dev_priv, pipe);
2067 assert_fdi_rx_disabled(dev_priv, pipe);
2068
291906f1
JB
2069 /* Ports must be off as well */
2070 assert_pch_ports_disabled(dev_priv, pipe);
2071
ab9412ba 2072 reg = PCH_TRANSCONF(pipe);
040484af
JB
2073 val = I915_READ(reg);
2074 val &= ~TRANS_ENABLE;
2075 I915_WRITE(reg, val);
2076 /* wait for PCH transcoder off, transcoder state */
2077 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 2078 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV
2079
2080 if (!HAS_PCH_IBX(dev)) {
2081 /* Workaround: Clear the timing override chicken bit again. */
2082 reg = TRANS_CHICKEN2(pipe);
2083 val = I915_READ(reg);
2084 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2085 I915_WRITE(reg, val);
2086 }
040484af
JB
2087}
2088
ab4d966c 2089static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 2090{
8fb033d7
PZ
2091 u32 val;
2092
ab9412ba 2093 val = I915_READ(LPT_TRANSCONF);
8fb033d7 2094 val &= ~TRANS_ENABLE;
ab9412ba 2095 I915_WRITE(LPT_TRANSCONF, val);
8fb033d7 2096 /* wait for PCH transcoder off, transcoder state */
ab9412ba 2097 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
8a52fd9f 2098 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ
2099
2100 /* Workaround: clear timing override bit. */
2101 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 2102 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 2103 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB
2104}
2105
b24e7179 2106/**
309cfea8 2107 * intel_enable_pipe - enable a pipe, asserting requirements
0372264a 2108 * @crtc: crtc responsible for the pipe
b24e7179 2109 *
0372264a 2110 * Enable @crtc's pipe, making sure that various hardware specific requirements
b24e7179 2111 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
b24e7179 2112 */
e1fdc473 2113static void intel_enable_pipe(struct intel_crtc *crtc)
b24e7179 2114{
0372264a
PZ
2115 struct drm_device *dev = crtc->base.dev;
2116 struct drm_i915_private *dev_priv = dev->dev_private;
2117 enum pipe pipe = crtc->pipe;
702e7a56
PZ
2118 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2119 pipe);
1a240d4d 2120 enum pipe pch_transcoder;
b24e7179
JB
2121 int reg;
2122 u32 val;
2123
58c6eaa2 2124 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 2125 assert_cursor_disabled(dev_priv, pipe);
58c6eaa2
DV
2126 assert_sprites_disabled(dev_priv, pipe);
2127
681e5811 2128 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ
2129 pch_transcoder = TRANSCODER_A;
2130 else
2131 pch_transcoder = pipe;
2132
b24e7179
JB
2133 /*
2134 * A pipe without a PLL won't actually be able to drive bits from
2135 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2136 * need the check.
2137 */
50360403 2138 if (HAS_GMCH_DISPLAY(dev_priv->dev))
409ee761 2139 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
23538ef1
JN
2140 assert_dsi_pll_enabled(dev_priv);
2141 else
2142 assert_pll_enabled(dev_priv, pipe);
040484af 2143 else {
6e3c9717 2144 if (crtc->config->has_pch_encoder) {
040484af 2145 /* if driving the PCH, we need FDI enabled */
cc391bbb 2146 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV
2147 assert_fdi_tx_pll_enabled(dev_priv,
2148 (enum pipe) cpu_transcoder);
040484af
JB
2149 }
2150 /* FIXME: assert CPU port conditions for SNB+ */
2151 }
b24e7179 2152
702e7a56 2153 reg = PIPECONF(cpu_transcoder);
b24e7179 2154 val = I915_READ(reg);
7ad25d48 2155 if (val & PIPECONF_ENABLE) {
b6b5d049
VS
2156 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2157 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
00d70b15 2158 return;
7ad25d48 2159 }
00d70b15
CW
2160
2161 I915_WRITE(reg, val | PIPECONF_ENABLE);
851855d8 2162 POSTING_READ(reg);
b24e7179
JB
2163}
2164
2165/**
309cfea8 2166 * intel_disable_pipe - disable a pipe, asserting requirements
575f7ab7 2167 * @crtc: crtc whose pipes is to be disabled
b24e7179 2168 *
575f7ab7
VS
2169 * Disable the pipe of @crtc, making sure that various hardware
2170 * specific requirements are met, if applicable, e.g. plane
2171 * disabled, panel fitter off, etc.
b24e7179
JB
2172 *
2173 * Will wait until the pipe has shut down before returning.
2174 */
575f7ab7 2175static void intel_disable_pipe(struct intel_crtc *crtc)
b24e7179 2176{
575f7ab7 2177 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
6e3c9717 2178 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
575f7ab7 2179 enum pipe pipe = crtc->pipe;
b24e7179
JB
2180 int reg;
2181 u32 val;
2182
2183 /*
2184 * Make sure planes won't keep trying to pump pixels to us,
2185 * or we might hang the display.
2186 */
2187 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 2188 assert_cursor_disabled(dev_priv, pipe);
19332d7a 2189 assert_sprites_disabled(dev_priv, pipe);
b24e7179 2190
702e7a56 2191 reg = PIPECONF(cpu_transcoder);
b24e7179 2192 val = I915_READ(reg);
00d70b15
CW
2193 if ((val & PIPECONF_ENABLE) == 0)
2194 return;
2195
67adc644
VS
2196 /*
2197 * Double wide has implications for planes
2198 * so best keep it disabled when not needed.
2199 */
6e3c9717 2200 if (crtc->config->double_wide)
67adc644
VS
2201 val &= ~PIPECONF_DOUBLE_WIDE;
2202
2203 /* Don't disable pipe or pipe PLLs if needed */
b6b5d049
VS
2204 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2205 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
67adc644
VS
2206 val &= ~PIPECONF_ENABLE;
2207
2208 I915_WRITE(reg, val);
2209 if ((val & PIPECONF_ENABLE) == 0)
2210 intel_wait_for_pipe_off(crtc);
b24e7179
JB
2211}
2212
2213/**
262ca2b0 2214 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
fdd508a6
VS
2215 * @plane: plane to be enabled
2216 * @crtc: crtc for the plane
b24e7179 2217 *
fdd508a6 2218 * Enable @plane on @crtc, making sure that the pipe is running first.
b24e7179 2219 */
fdd508a6
VS
2220static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2221 struct drm_crtc *crtc)
b24e7179 2222{
fdd508a6
VS
2223 struct drm_device *dev = plane->dev;
2224 struct drm_i915_private *dev_priv = dev->dev_private;
2225 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b24e7179
JB
2226
2227 /* If the pipe isn't enabled, we can't pump pixels and may hang */
fdd508a6 2228 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
b70709a6 2229 to_intel_plane_state(plane->state)->visible = true;
939c2fe8 2230
fdd508a6
VS
2231 dev_priv->display.update_primary_plane(crtc, plane->fb,
2232 crtc->x, crtc->y);
b24e7179
JB
2233}
2234
693db184
CW
2235static bool need_vtd_wa(struct drm_device *dev)
2236{
2237#ifdef CONFIG_INTEL_IOMMU
2238 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2239 return true;
2240#endif
2241 return false;
2242}
2243
50470bb0 2244unsigned int
6761dd31
TU
2245intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2246 uint64_t fb_format_modifier)
a57ce0b2 2247{
6761dd31
TU
2248 unsigned int tile_height;
2249 uint32_t pixel_bytes;
a57ce0b2 2250
b5d0e9bf
DL
2251 switch (fb_format_modifier) {
2252 case DRM_FORMAT_MOD_NONE:
2253 tile_height = 1;
2254 break;
2255 case I915_FORMAT_MOD_X_TILED:
2256 tile_height = IS_GEN2(dev) ? 16 : 8;
2257 break;
2258 case I915_FORMAT_MOD_Y_TILED:
2259 tile_height = 32;
2260 break;
2261 case I915_FORMAT_MOD_Yf_TILED:
6761dd31
TU
2262 pixel_bytes = drm_format_plane_cpp(pixel_format, 0);
2263 switch (pixel_bytes) {
b5d0e9bf 2264 default:
6761dd31 2265 case 1:
b5d0e9bf
DL
2266 tile_height = 64;
2267 break;
6761dd31
TU
2268 case 2:
2269 case 4:
b5d0e9bf
DL
2270 tile_height = 32;
2271 break;
6761dd31 2272 case 8:
b5d0e9bf
DL
2273 tile_height = 16;
2274 break;
6761dd31 2275 case 16:
b5d0e9bf
DL
2276 WARN_ONCE(1,
2277 "128-bit pixels are not supported for display!");
2278 tile_height = 16;
2279 break;
2280 }
2281 break;
2282 default:
2283 MISSING_CASE(fb_format_modifier);
2284 tile_height = 1;
2285 break;
2286 }
091df6cb 2287
6761dd31
TU
2288 return tile_height;
2289}
2290
2291unsigned int
2292intel_fb_align_height(struct drm_device *dev, unsigned int height,
2293 uint32_t pixel_format, uint64_t fb_format_modifier)
2294{
2295 return ALIGN(height, intel_tile_height(dev, pixel_format,
2296 fb_format_modifier));
a57ce0b2
JB
2297}
2298
f64b98cd
TU
2299static int
2300intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2301 const struct drm_plane_state *plane_state)
2302{
50470bb0 2303 struct intel_rotation_info *info = &view->rotation_info;
50470bb0 2304
f64b98cd
TU
2305 *view = i915_ggtt_view_normal;
2306
50470bb0
TU
2307 if (!plane_state)
2308 return 0;
2309
121920fa 2310 if (!intel_rotation_90_or_270(plane_state->rotation))
50470bb0
TU
2311 return 0;
2312
9abc4648 2313 *view = i915_ggtt_view_rotated;
50470bb0
TU
2314
2315 info->height = fb->height;
2316 info->pixel_format = fb->pixel_format;
2317 info->pitch = fb->pitches[0];
2318 info->fb_modifier = fb->modifier[0];
2319
f64b98cd
TU
2320 return 0;
2321}
2322
127bd2ac 2323int
850c4cdc
TU
2324intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2325 struct drm_framebuffer *fb,
82bc3b2d 2326 const struct drm_plane_state *plane_state,
a4872ba6 2327 struct intel_engine_cs *pipelined)
6b95a207 2328{
850c4cdc 2329 struct drm_device *dev = fb->dev;
ce453d81 2330 struct drm_i915_private *dev_priv = dev->dev_private;
850c4cdc 2331 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
f64b98cd 2332 struct i915_ggtt_view view;
6b95a207
KH
2333 u32 alignment;
2334 int ret;
2335
ebcdd39e
MR
2336 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2337
7b911adc
TU
2338 switch (fb->modifier[0]) {
2339 case DRM_FORMAT_MOD_NONE:
1fada4cc
DL
2340 if (INTEL_INFO(dev)->gen >= 9)
2341 alignment = 256 * 1024;
2342 else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
534843da 2343 alignment = 128 * 1024;
a6c45cf0 2344 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW
2345 alignment = 4 * 1024;
2346 else
2347 alignment = 64 * 1024;
6b95a207 2348 break;
7b911adc 2349 case I915_FORMAT_MOD_X_TILED:
1fada4cc
DL
2350 if (INTEL_INFO(dev)->gen >= 9)
2351 alignment = 256 * 1024;
2352 else {
2353 /* pin() will align the object as required by fence */
2354 alignment = 0;
2355 }
6b95a207 2356 break;
7b911adc 2357 case I915_FORMAT_MOD_Y_TILED:
1327b9a1
DL
2358 case I915_FORMAT_MOD_Yf_TILED:
2359 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2360 "Y tiling bo slipped through, driver bug!\n"))
2361 return -EINVAL;
2362 alignment = 1 * 1024 * 1024;
2363 break;
6b95a207 2364 default:
7b911adc
TU
2365 MISSING_CASE(fb->modifier[0]);
2366 return -EINVAL;
6b95a207
KH
2367 }
2368
f64b98cd
TU
2369 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2370 if (ret)
2371 return ret;
2372
693db184
CW
2373 /* Note that the w/a also requires 64 PTE of padding following the
2374 * bo. We currently fill all unused PTE with the shadow page and so
2375 * we should always have valid PTE following the scanout preventing
2376 * the VT-d warning.
2377 */
2378 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2379 alignment = 256 * 1024;
2380
d6dd6843
PZ
2381 /*
2382 * Global gtt pte registers are special registers which actually forward
2383 * writes to a chunk of system memory. Which means that there is no risk
2384 * that the register values disappear as soon as we call
2385 * intel_runtime_pm_put(), so it is correct to wrap only the
2386 * pin/unpin/fence and not more.
2387 */
2388 intel_runtime_pm_get(dev_priv);
2389
ce453d81 2390 dev_priv->mm.interruptible = false;
e6617330 2391 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
f64b98cd 2392 &view);
48b956c5 2393 if (ret)
ce453d81 2394 goto err_interruptible;
6b95a207
KH
2395
2396 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2397 * fence, whereas 965+ only requires a fence if using
2398 * framebuffer compression. For simplicity, we always install
2399 * a fence as the cost is not that onerous.
2400 */
06d98131 2401 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW
2402 if (ret)
2403 goto err_unpin;
1690e1eb 2404
9a5a53b3 2405 i915_gem_object_pin_fence(obj);
6b95a207 2406
ce453d81 2407 dev_priv->mm.interruptible = true;
d6dd6843 2408 intel_runtime_pm_put(dev_priv);
6b95a207 2409 return 0;
48b956c5
CW
2410
2411err_unpin:
f64b98cd 2412 i915_gem_object_unpin_from_display_plane(obj, &view);
ce453d81
CW
2413err_interruptible:
2414 dev_priv->mm.interruptible = true;
d6dd6843 2415 intel_runtime_pm_put(dev_priv);
48b956c5 2416 return ret;
6b95a207
KH
2417}
2418
82bc3b2d
TU
2419static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2420 const struct drm_plane_state *plane_state)
1690e1eb 2421{
82bc3b2d 2422 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
f64b98cd
TU
2423 struct i915_ggtt_view view;
2424 int ret;
82bc3b2d 2425
ebcdd39e
MR
2426 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2427
f64b98cd
TU
2428 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2429 WARN_ONCE(ret, "Couldn't get view from plane state!");
2430
1690e1eb 2431 i915_gem_object_unpin_fence(obj);
f64b98cd 2432 i915_gem_object_unpin_from_display_plane(obj, &view);
1690e1eb
CW
2433}
2434
c2c75131
DV
2435/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2436 * is assumed to be a power-of-two. */
bc752862
CW
2437unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2438 unsigned int tiling_mode,
2439 unsigned int cpp,
2440 unsigned int pitch)
c2c75131 2441{
bc752862
CW
2442 if (tiling_mode != I915_TILING_NONE) {
2443 unsigned int tile_rows, tiles;
c2c75131 2444
bc752862
CW
2445 tile_rows = *y / 8;
2446 *y %= 8;
c2c75131 2447
bc752862
CW
2448 tiles = *x / (512/cpp);
2449 *x %= 512/cpp;
2450
2451 return tile_rows * pitch * 8 + tiles * 4096;
2452 } else {
2453 unsigned int offset;
2454
2455 offset = *y * pitch + *x * cpp;
2456 *y = 0;
2457 *x = (offset & 4095) / cpp;
2458 return offset & -4096;
2459 }
c2c75131
DV
2460}
2461
b35d63fa 2462static int i9xx_format_to_fourcc(int format)
46f297fb
JB
2463{
2464 switch (format) {
2465 case DISPPLANE_8BPP:
2466 return DRM_FORMAT_C8;
2467 case DISPPLANE_BGRX555:
2468 return DRM_FORMAT_XRGB1555;
2469 case DISPPLANE_BGRX565:
2470 return DRM_FORMAT_RGB565;
2471 default:
2472 case DISPPLANE_BGRX888:
2473 return DRM_FORMAT_XRGB8888;
2474 case DISPPLANE_RGBX888:
2475 return DRM_FORMAT_XBGR8888;
2476 case DISPPLANE_BGRX101010:
2477 return DRM_FORMAT_XRGB2101010;
2478 case DISPPLANE_RGBX101010:
2479 return DRM_FORMAT_XBGR2101010;
2480 }
2481}
2482
bc8d7dff
DL
2483static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2484{
2485 switch (format) {
2486 case PLANE_CTL_FORMAT_RGB_565:
2487 return DRM_FORMAT_RGB565;
2488 default:
2489 case PLANE_CTL_FORMAT_XRGB_8888:
2490 if (rgb_order) {
2491 if (alpha)
2492 return DRM_FORMAT_ABGR8888;
2493 else
2494 return DRM_FORMAT_XBGR8888;
2495 } else {
2496 if (alpha)
2497 return DRM_FORMAT_ARGB8888;
2498 else
2499 return DRM_FORMAT_XRGB8888;
2500 }
2501 case PLANE_CTL_FORMAT_XRGB_2101010:
2502 if (rgb_order)
2503 return DRM_FORMAT_XBGR2101010;
2504 else
2505 return DRM_FORMAT_XRGB2101010;
2506 }
2507}
2508
5724dbd1 2509static bool
f6936e29
DV
2510intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2511 struct intel_initial_plane_config *plane_config)
46f297fb
JB
2512{
2513 struct drm_device *dev = crtc->base.dev;
2514 struct drm_i915_gem_object *obj = NULL;
2515 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2d14030b 2516 struct drm_framebuffer *fb = &plane_config->fb->base;
f37b5c2b
DV
2517 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2518 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2519 PAGE_SIZE);
2520
2521 size_aligned -= base_aligned;
46f297fb 2522
ff2652ea
CW
2523 if (plane_config->size == 0)
2524 return false;
2525
f37b5c2b
DV
2526 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2527 base_aligned,
2528 base_aligned,
2529 size_aligned);
46f297fb 2530 if (!obj)
484b41dd 2531 return false;
46f297fb 2532
49af449b
DL
2533 obj->tiling_mode = plane_config->tiling;
2534 if (obj->tiling_mode == I915_TILING_X)
6bf129df 2535 obj->stride = fb->pitches[0];
46f297fb 2536
6bf129df
DL
2537 mode_cmd.pixel_format = fb->pixel_format;
2538 mode_cmd.width = fb->width;
2539 mode_cmd.height = fb->height;
2540 mode_cmd.pitches[0] = fb->pitches[0];
18c5247e
DV
2541 mode_cmd.modifier[0] = fb->modifier[0];
2542 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
46f297fb
JB
2543
2544 mutex_lock(&dev->struct_mutex);
6bf129df 2545 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
484b41dd 2546 &mode_cmd, obj)) {
46f297fb
JB
2547 DRM_DEBUG_KMS("intel fb init failed\n");
2548 goto out_unref_obj;
2549 }
46f297fb 2550 mutex_unlock(&dev->struct_mutex);
484b41dd 2551
f6936e29 2552 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
484b41dd 2553 return true;
46f297fb
JB
2554
2555out_unref_obj:
2556 drm_gem_object_unreference(&obj->base);
2557 mutex_unlock(&dev->struct_mutex);
484b41dd
JB
2558 return false;
2559}
2560
afd65eb4
MR
2561/* Update plane->state->fb to match plane->fb after driver-internal updates */
2562static void
2563update_state_fb(struct drm_plane *plane)
2564{
2565 if (plane->fb == plane->state->fb)
2566 return;
2567
2568 if (plane->state->fb)
2569 drm_framebuffer_unreference(plane->state->fb);
2570 plane->state->fb = plane->fb;
2571 if (plane->state->fb)
2572 drm_framebuffer_reference(plane->state->fb);
2573}
2574
5724dbd1 2575static void
f6936e29
DV
2576intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2577 struct intel_initial_plane_config *plane_config)
484b41dd
JB
2578{
2579 struct drm_device *dev = intel_crtc->base.dev;
d9ceb816 2580 struct drm_i915_private *dev_priv = dev->dev_private;
484b41dd
JB
2581 struct drm_crtc *c;
2582 struct intel_crtc *i;
2ff8fde1 2583 struct drm_i915_gem_object *obj;
88595ac9
DV
2584 struct drm_plane *primary = intel_crtc->base.primary;
2585 struct drm_framebuffer *fb;
484b41dd 2586
2d14030b 2587 if (!plane_config->fb)
484b41dd
JB
2588 return;
2589
f6936e29 2590 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
88595ac9
DV
2591 fb = &plane_config->fb->base;
2592 goto valid_fb;
f55548b5 2593 }
484b41dd 2594
2d14030b 2595 kfree(plane_config->fb);
484b41dd
JB
2596
2597 /*
2598 * Failed to alloc the obj, check to see if we should share
2599 * an fb with another CRTC instead
2600 */
70e1e0ec 2601 for_each_crtc(dev, c) {
484b41dd
JB
2602 i = to_intel_crtc(c);
2603
2604 if (c == &intel_crtc->base)
2605 continue;
2606
2ff8fde1
MR
2607 if (!i->active)
2608 continue;
2609
88595ac9
DV
2610 fb = c->primary->fb;
2611 if (!fb)
484b41dd
JB
2612 continue;
2613
88595ac9 2614 obj = intel_fb_obj(fb);
2ff8fde1 2615 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
88595ac9
DV
2616 drm_framebuffer_reference(fb);
2617 goto valid_fb;
484b41dd
JB
2618 }
2619 }
88595ac9
DV
2620
2621 return;
2622
2623valid_fb:
2624 obj = intel_fb_obj(fb);
2625 if (obj->tiling_mode != I915_TILING_NONE)
2626 dev_priv->preserve_bios_swizzle = true;
2627
2628 primary->fb = fb;
2629 primary->state->crtc = &intel_crtc->base;
2630 primary->crtc = &intel_crtc->base;
2631 update_state_fb(primary);
2632 obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
46f297fb
JB
2633}
2634
29b9bde6
DV
2635static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2636 struct drm_framebuffer *fb,
2637 int x, int y)
81255565
JB
2638{
2639 struct drm_device *dev = crtc->dev;
2640 struct drm_i915_private *dev_priv = dev->dev_private;
2641 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML
2642 struct drm_plane *primary = crtc->primary;
2643 bool visible = to_intel_plane_state(primary->state)->visible;
c9ba6fad 2644 struct drm_i915_gem_object *obj;
81255565 2645 int plane = intel_crtc->plane;
e506a0c6 2646 unsigned long linear_offset;
81255565 2647 u32 dspcntr;
f45651ba 2648 u32 reg = DSPCNTR(plane);
48404c1e 2649 int pixel_size;
f45651ba 2650
b70709a6 2651 if (!visible || !fb) {
fdd508a6
VS
2652 I915_WRITE(reg, 0);
2653 if (INTEL_INFO(dev)->gen >= 4)
2654 I915_WRITE(DSPSURF(plane), 0);
2655 else
2656 I915_WRITE(DSPADDR(plane), 0);
2657 POSTING_READ(reg);
2658 return;
2659 }
2660
c9ba6fad
VS
2661 obj = intel_fb_obj(fb);
2662 if (WARN_ON(obj == NULL))
2663 return;
2664
2665 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2666
f45651ba
VS
2667 dspcntr = DISPPLANE_GAMMA_ENABLE;
2668
fdd508a6 2669 dspcntr |= DISPLAY_PLANE_ENABLE;
f45651ba
VS
2670
2671 if (INTEL_INFO(dev)->gen < 4) {
2672 if (intel_crtc->pipe == PIPE_B)
2673 dspcntr |= DISPPLANE_SEL_PIPE_B;
2674
2675 /* pipesrc and dspsize control the size that is scaled from,
2676 * which should always be the user's requested size.
2677 */
2678 I915_WRITE(DSPSIZE(plane),
6e3c9717
ACO
2679 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2680 (intel_crtc->config->pipe_src_w - 1));
f45651ba 2681 I915_WRITE(DSPPOS(plane), 0);
c14b0485
VS
2682 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2683 I915_WRITE(PRIMSIZE(plane),
6e3c9717
ACO
2684 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2685 (intel_crtc->config->pipe_src_w - 1));
c14b0485
VS
2686 I915_WRITE(PRIMPOS(plane), 0);
2687 I915_WRITE(PRIMCNSTALPHA(plane), 0);
f45651ba 2688 }
81255565 2689
57779d06
VS
2690 switch (fb->pixel_format) {
2691 case DRM_FORMAT_C8:
81255565
JB
2692 dspcntr |= DISPPLANE_8BPP;
2693 break;
57779d06 2694 case DRM_FORMAT_XRGB1555:
57779d06 2695 dspcntr |= DISPPLANE_BGRX555;
81255565 2696 break;
57779d06
VS
2697 case DRM_FORMAT_RGB565:
2698 dspcntr |= DISPPLANE_BGRX565;
2699 break;
2700 case DRM_FORMAT_XRGB8888:
57779d06
VS
2701 dspcntr |= DISPPLANE_BGRX888;
2702 break;
2703 case DRM_FORMAT_XBGR8888:
57779d06
VS
2704 dspcntr |= DISPPLANE_RGBX888;
2705 break;
2706 case DRM_FORMAT_XRGB2101010:
57779d06
VS
2707 dspcntr |= DISPPLANE_BGRX101010;
2708 break;
2709 case DRM_FORMAT_XBGR2101010:
57779d06 2710 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB
2711 break;
2712 default:
baba133a 2713 BUG();
81255565 2714 }
57779d06 2715
f45651ba
VS
2716 if (INTEL_INFO(dev)->gen >= 4 &&
2717 obj->tiling_mode != I915_TILING_NONE)
2718 dspcntr |= DISPPLANE_TILED;
81255565 2719
de1aa629
VS
2720 if (IS_G4X(dev))
2721 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2722
b9897127 2723 linear_offset = y * fb->pitches[0] + x * pixel_size;
81255565 2724
c2c75131
DV
2725 if (INTEL_INFO(dev)->gen >= 4) {
2726 intel_crtc->dspaddr_offset =
bc752862 2727 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
b9897127 2728 pixel_size,
bc752862 2729 fb->pitches[0]);
c2c75131
DV
2730 linear_offset -= intel_crtc->dspaddr_offset;
2731 } else {
e506a0c6 2732 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2733 }
e506a0c6 2734
8e7d688b 2735 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
48404c1e
SJ
2736 dspcntr |= DISPPLANE_ROTATE_180;
2737
6e3c9717
ACO
2738 x += (intel_crtc->config->pipe_src_w - 1);
2739 y += (intel_crtc->config->pipe_src_h - 1);
48404c1e
SJ
2740
2741 /* Finding the last pixel of the last line of the display
2742 data and adding to linear_offset*/
2743 linear_offset +=
6e3c9717
ACO
2744 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2745 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
48404c1e
SJ
2746 }
2747
2748 I915_WRITE(reg, dspcntr);
2749
01f2c773 2750 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2751 if (INTEL_INFO(dev)->gen >= 4) {
85ba7b7d
DV
2752 I915_WRITE(DSPSURF(plane),
2753 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
5eddb70b 2754 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2755 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2756 } else
f343c5f6 2757 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
5eddb70b 2758 POSTING_READ(reg);
17638cd6
JB
2759}
2760
29b9bde6
DV
2761static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2762 struct drm_framebuffer *fb,
2763 int x, int y)
17638cd6
JB
2764{
2765 struct drm_device *dev = crtc->dev;
2766 struct drm_i915_private *dev_priv = dev->dev_private;
2767 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML
2768 struct drm_plane *primary = crtc->primary;
2769 bool visible = to_intel_plane_state(primary->state)->visible;
c9ba6fad 2770 struct drm_i915_gem_object *obj;
17638cd6 2771 int plane = intel_crtc->plane;
e506a0c6 2772 unsigned long linear_offset;
17638cd6 2773 u32 dspcntr;
f45651ba 2774 u32 reg = DSPCNTR(plane);
48404c1e 2775 int pixel_size;
f45651ba 2776
b70709a6 2777 if (!visible || !fb) {
fdd508a6
VS
2778 I915_WRITE(reg, 0);
2779 I915_WRITE(DSPSURF(plane), 0);
2780 POSTING_READ(reg);
2781 return;
2782 }
2783
c9ba6fad
VS
2784 obj = intel_fb_obj(fb);
2785 if (WARN_ON(obj == NULL))
2786 return;
2787
2788 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2789
f45651ba
VS
2790 dspcntr = DISPPLANE_GAMMA_ENABLE;
2791
fdd508a6 2792 dspcntr |= DISPLAY_PLANE_ENABLE;
f45651ba
VS
2793
2794 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2795 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
17638cd6 2796
57779d06
VS
2797 switch (fb->pixel_format) {
2798 case DRM_FORMAT_C8:
17638cd6
JB
2799 dspcntr |= DISPPLANE_8BPP;
2800 break;
57779d06
VS
2801 case DRM_FORMAT_RGB565:
2802 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2803 break;
57779d06 2804 case DRM_FORMAT_XRGB8888:
57779d06
VS
2805 dspcntr |= DISPPLANE_BGRX888;
2806 break;
2807 case DRM_FORMAT_XBGR8888:
57779d06
VS
2808 dspcntr |= DISPPLANE_RGBX888;
2809 break;
2810 case DRM_FORMAT_XRGB2101010:
57779d06
VS
2811 dspcntr |= DISPPLANE_BGRX101010;
2812 break;
2813 case DRM_FORMAT_XBGR2101010:
57779d06 2814 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB
2815 break;
2816 default:
baba133a 2817 BUG();
17638cd6
JB
2818 }
2819
2820 if (obj->tiling_mode != I915_TILING_NONE)
2821 dspcntr |= DISPPLANE_TILED;
17638cd6 2822
f45651ba 2823 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
1f5d76db 2824 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
17638cd6 2825
b9897127 2826 linear_offset = y * fb->pitches[0] + x * pixel_size;
c2c75131 2827 intel_crtc->dspaddr_offset =
bc752862 2828 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
b9897127 2829 pixel_size,
bc752862 2830 fb->pitches[0]);
c2c75131 2831 linear_offset -= intel_crtc->dspaddr_offset;
8e7d688b 2832 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
48404c1e
SJ
2833 dspcntr |= DISPPLANE_ROTATE_180;
2834
2835 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
6e3c9717
ACO
2836 x += (intel_crtc->config->pipe_src_w - 1);
2837 y += (intel_crtc->config->pipe_src_h - 1);
48404c1e
SJ
2838
2839 /* Finding the last pixel of the last line of the display
2840 data and adding to linear_offset*/
2841 linear_offset +=
6e3c9717
ACO
2842 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2843 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
48404c1e
SJ
2844 }
2845 }
2846
2847 I915_WRITE(reg, dspcntr);
17638cd6 2848
01f2c773 2849 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
85ba7b7d
DV
2850 I915_WRITE(DSPSURF(plane),
2851 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
b3dc685e 2852 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
bc1c91eb
DL
2853 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2854 } else {
2855 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2856 I915_WRITE(DSPLINOFF(plane), linear_offset);
2857 }
17638cd6 2858 POSTING_READ(reg);
17638cd6
JB
2859}
2860
b321803d
DL
2861u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2862 uint32_t pixel_format)
2863{
2864 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2865
2866 /*
2867 * The stride is either expressed as a multiple of 64 bytes
2868 * chunks for linear buffers or in number of tiles for tiled
2869 * buffers.
2870 */
2871 switch (fb_modifier) {
2872 case DRM_FORMAT_MOD_NONE:
2873 return 64;
2874 case I915_FORMAT_MOD_X_TILED:
2875 if (INTEL_INFO(dev)->gen == 2)
2876 return 128;
2877 return 512;
2878 case I915_FORMAT_MOD_Y_TILED:
2879 /* No need to check for old gens and Y tiling since this is
2880 * about the display engine and those will be blocked before
2881 * we get here.
2882 */
2883 return 128;
2884 case I915_FORMAT_MOD_Yf_TILED:
2885 if (bits_per_pixel == 8)
2886 return 64;
2887 else
2888 return 128;
2889 default:
2890 MISSING_CASE(fb_modifier);
2891 return 64;
2892 }
2893}
2894
121920fa
TU
2895unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
2896 struct drm_i915_gem_object *obj)
2897{
9abc4648 2898 const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
121920fa
TU
2899
2900 if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
9abc4648 2901 view = &i915_ggtt_view_rotated;
121920fa
TU
2902
2903 return i915_gem_obj_ggtt_offset_view(obj, view);
2904}
2905
a1b2278e
CK
2906/*
2907 * This function detaches (aka. unbinds) unused scalers in hardware
2908 */
2909void skl_detach_scalers(struct intel_crtc *intel_crtc)
2910{
2911 struct drm_device *dev;
2912 struct drm_i915_private *dev_priv;
2913 struct intel_crtc_scaler_state *scaler_state;
2914 int i;
2915
2916 if (!intel_crtc || !intel_crtc->config)
2917 return;
2918
2919 dev = intel_crtc->base.dev;
2920 dev_priv = dev->dev_private;
2921 scaler_state = &intel_crtc->config->scaler_state;
2922
2923 /* loop through and disable scalers that aren't in use */
2924 for (i = 0; i < intel_crtc->num_scalers; i++) {
2925 if (!scaler_state->scalers[i].in_use) {
2926 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, i), 0);
2927 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, i), 0);
2928 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, i), 0);
2929 DRM_DEBUG_KMS("CRTC:%d Disabled scaler id %u.%u\n",
2930 intel_crtc->base.base.id, intel_crtc->pipe, i);
2931 }
2932 }
2933}
2934
6156a456 2935u32 skl_plane_ctl_format(uint32_t pixel_format)
70d21f0e 2936{
6156a456 2937 switch (pixel_format) {
d161cf7a 2938 case DRM_FORMAT_C8:
c34ce3d1 2939 return PLANE_CTL_FORMAT_INDEXED;
70d21f0e 2940 case DRM_FORMAT_RGB565:
c34ce3d1 2941 return PLANE_CTL_FORMAT_RGB_565;
70d21f0e 2942 case DRM_FORMAT_XBGR8888:
c34ce3d1 2943 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
6156a456 2944 case DRM_FORMAT_XRGB8888:
c34ce3d1 2945 return PLANE_CTL_FORMAT_XRGB_8888;
6156a456
CK
2946 /*
2947 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2948 * to be already pre-multiplied. We need to add a knob (or a different
2949 * DRM_FORMAT) for user-space to configure that.
2950 */
f75fb42a 2951 case DRM_FORMAT_ABGR8888:
c34ce3d1 2952 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
6156a456 2953 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
6156a456 2954 case DRM_FORMAT_ARGB8888:
c34ce3d1 2955 return PLANE_CTL_FORMAT_XRGB_8888 |
6156a456 2956 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
70d21f0e 2957 case DRM_FORMAT_XRGB2101010:
c34ce3d1 2958 return PLANE_CTL_FORMAT_XRGB_2101010;
70d21f0e 2959 case DRM_FORMAT_XBGR2101010:
c34ce3d1 2960 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
6156a456 2961 case DRM_FORMAT_YUYV:
c34ce3d1 2962 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
6156a456 2963 case DRM_FORMAT_YVYU:
c34ce3d1 2964 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
6156a456 2965 case DRM_FORMAT_UYVY:
c34ce3d1 2966 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
6156a456 2967 case DRM_FORMAT_VYUY:
c34ce3d1 2968 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
70d21f0e 2969 default:
4249eeef 2970 MISSING_CASE(pixel_format);
70d21f0e 2971 }
8cfcba41 2972
c34ce3d1 2973 return 0;
6156a456 2974}
70d21f0e 2975
6156a456
CK
2976u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
2977{
6156a456 2978 switch (fb_modifier) {
30af77c4 2979 case DRM_FORMAT_MOD_NONE:
70d21f0e 2980 break;
30af77c4 2981 case I915_FORMAT_MOD_X_TILED:
c34ce3d1 2982 return PLANE_CTL_TILED_X;
b321803d 2983 case I915_FORMAT_MOD_Y_TILED:
c34ce3d1 2984 return PLANE_CTL_TILED_Y;
b321803d 2985 case I915_FORMAT_MOD_Yf_TILED:
c34ce3d1 2986 return PLANE_CTL_TILED_YF;
70d21f0e 2987 default:
6156a456 2988 MISSING_CASE(fb_modifier);
70d21f0e 2989 }
8cfcba41 2990
c34ce3d1 2991 return 0;
6156a456 2992}
70d21f0e 2993
6156a456
CK
2994u32 skl_plane_ctl_rotation(unsigned int rotation)
2995{
3b7a5119 2996 switch (rotation) {
6156a456
CK
2997 case BIT(DRM_ROTATE_0):
2998 break;
1e8df167
SJ
2999 /*
3000 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3001 * while i915 HW rotation is clockwise, thats why this swapping.
3002 */
3b7a5119 3003 case BIT(DRM_ROTATE_90):
1e8df167 3004 return PLANE_CTL_ROTATE_270;
3b7a5119 3005 case BIT(DRM_ROTATE_180):
c34ce3d1 3006 return PLANE_CTL_ROTATE_180;
3b7a5119 3007 case BIT(DRM_ROTATE_270):
1e8df167 3008 return PLANE_CTL_ROTATE_90;
6156a456
CK
3009 default:
3010 MISSING_CASE(rotation);
3011 }
3012
c34ce3d1 3013 return 0;
6156a456
CK
3014}
3015
3016static void skylake_update_primary_plane(struct drm_crtc *crtc,
3017 struct drm_framebuffer *fb,
3018 int x, int y)
3019{
3020 struct drm_device *dev = crtc->dev;
3021 struct drm_i915_private *dev_priv = dev->dev_private;
3022 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML
3023 struct drm_plane *plane = crtc->primary;
3024 bool visible = to_intel_plane_state(plane->state)->visible;
6156a456
CK
3025 struct drm_i915_gem_object *obj;
3026 int pipe = intel_crtc->pipe;
3027 u32 plane_ctl, stride_div, stride;
3028 u32 tile_height, plane_offset, plane_size;
3029 unsigned int rotation;
3030 int x_offset, y_offset;
3031 unsigned long surf_addr;
6156a456
CK
3032 struct intel_crtc_state *crtc_state = intel_crtc->config;
3033 struct intel_plane_state *plane_state;
3034 int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3035 int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3036 int scaler_id = -1;
3037
6156a456
CK
3038 plane_state = to_intel_plane_state(plane->state);
3039
b70709a6 3040 if (!visible || !fb) {
6156a456
CK
3041 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3042 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3043 POSTING_READ(PLANE_CTL(pipe, 0));
3044 return;
3b7a5119 3045 }
70d21f0e 3046
6156a456
CK
3047 plane_ctl = PLANE_CTL_ENABLE |
3048 PLANE_CTL_PIPE_GAMMA_ENABLE |
3049 PLANE_CTL_PIPE_CSC_ENABLE;
3050
3051 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3052 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3053 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3054
3055 rotation = plane->state->rotation;
3056 plane_ctl |= skl_plane_ctl_rotation(rotation);
3057
b321803d
DL
3058 obj = intel_fb_obj(fb);
3059 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3060 fb->pixel_format);
3b7a5119
SJ
3061 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj);
3062
6156a456
CK
3063 /*
3064 * FIXME: intel_plane_state->src, dst aren't set when transitional
3065 * update_plane helpers are called from legacy paths.
3066 * Once full atomic crtc is available, below check can be avoided.
3067 */
3068 if (drm_rect_width(&plane_state->src)) {
3069 scaler_id = plane_state->scaler_id;
3070 src_x = plane_state->src.x1 >> 16;
3071 src_y = plane_state->src.y1 >> 16;
3072 src_w = drm_rect_width(&plane_state->src) >> 16;
3073 src_h = drm_rect_height(&plane_state->src) >> 16;
3074 dst_x = plane_state->dst.x1;
3075 dst_y = plane_state->dst.y1;
3076 dst_w = drm_rect_width(&plane_state->dst);
3077 dst_h = drm_rect_height(&plane_state->dst);
3078
3079 WARN_ON(x != src_x || y != src_y);
3080 } else {
3081 src_w = intel_crtc->config->pipe_src_w;
3082 src_h = intel_crtc->config->pipe_src_h;
3083 }
3084
3b7a5119
SJ
3085 if (intel_rotation_90_or_270(rotation)) {
3086 /* stride = Surface height in tiles */
2614f17d 3087 tile_height = intel_tile_height(dev, fb->pixel_format,
3b7a5119
SJ
3088 fb->modifier[0]);
3089 stride = DIV_ROUND_UP(fb->height, tile_height);
6156a456 3090 x_offset = stride * tile_height - y - src_h;
3b7a5119 3091 y_offset = x;
6156a456 3092 plane_size = (src_w - 1) << 16 | (src_h - 1);
3b7a5119
SJ
3093 } else {
3094 stride = fb->pitches[0] / stride_div;
3095 x_offset = x;
3096 y_offset = y;
6156a456 3097 plane_size = (src_h - 1) << 16 | (src_w - 1);
3b7a5119
SJ
3098 }
3099 plane_offset = y_offset << 16 | x_offset;
b321803d 3100
70d21f0e 3101 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3b7a5119
SJ
3102 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3103 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3104 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
6156a456
CK
3105
3106 if (scaler_id >= 0) {
3107 uint32_t ps_ctrl = 0;
3108
3109 WARN_ON(!dst_w || !dst_h);
3110 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3111 crtc_state->scaler_state.scalers[scaler_id].mode;
3112 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3113 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3114 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3115 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3116 I915_WRITE(PLANE_POS(pipe, 0), 0);
3117 } else {
3118 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3119 }
3120
121920fa 3121 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
70d21f0e
DL
3122
3123 POSTING_READ(PLANE_SURF(pipe, 0));
3124}
3125
17638cd6
JB
3126/* Assume fb object is pinned & idle & fenced and just update base pointers */
3127static int
3128intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3129 int x, int y, enum mode_set_atomic state)
3130{
3131 struct drm_device *dev = crtc->dev;
3132 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 3133
6b8e6ed0
CW
3134 if (dev_priv->display.disable_fbc)
3135 dev_priv->display.disable_fbc(dev);
81255565 3136
29b9bde6
DV
3137 dev_priv->display.update_primary_plane(crtc, fb, x, y);
3138
3139 return 0;
81255565
JB
3140}
3141
7514747d 3142static void intel_complete_page_flips(struct drm_device *dev)
96a02917 3143{
96a02917
VS
3144 struct drm_crtc *crtc;
3145
70e1e0ec 3146 for_each_crtc(dev, crtc) {
96a02917
VS
3147 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3148 enum plane plane = intel_crtc->plane;
3149
3150 intel_prepare_page_flip(dev, plane);
3151 intel_finish_page_flip_plane(dev, plane);
3152 }
7514747d
VS
3153}
3154
3155static void intel_update_primary_planes(struct drm_device *dev)
3156{
3157 struct drm_i915_private *dev_priv = dev->dev_private;
3158 struct drm_crtc *crtc;
96a02917 3159
70e1e0ec 3160 for_each_crtc(dev, crtc) {
96a02917
VS
3161 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3162
51fd371b 3163 drm_modeset_lock(&crtc->mutex, NULL);
947fdaad
CW
3164 /*
3165 * FIXME: Once we have proper support for primary planes (and
3166 * disabling them without disabling the entire crtc) allow again
66e514c1 3167 * a NULL crtc->primary->fb.
947fdaad 3168 */
f4510a27 3169 if (intel_crtc->active && crtc->primary->fb)
262ca2b0 3170 dev_priv->display.update_primary_plane(crtc,
66e514c1 3171 crtc->primary->fb,
262ca2b0
MR
3172 crtc->x,
3173 crtc->y);
51fd371b 3174 drm_modeset_unlock(&crtc->mutex);
96a02917
VS
3175 }
3176}
3177
ce22dba9
ML
3178void intel_crtc_reset(struct intel_crtc *crtc)
3179{
3180 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3181
3182 if (!crtc->active)
3183 return;
3184
3185 intel_crtc_disable_planes(&crtc->base);
3186 dev_priv->display.crtc_disable(&crtc->base);
3187 dev_priv->display.crtc_enable(&crtc->base);
3188 intel_crtc_enable_planes(&crtc->base);
3189}
3190
7514747d
VS
3191void intel_prepare_reset(struct drm_device *dev)
3192{
f98ce92f
VS
3193 struct drm_i915_private *dev_priv = to_i915(dev);
3194 struct intel_crtc *crtc;
3195
7514747d
VS
3196 /* no reset support for gen2 */
3197 if (IS_GEN2(dev))
3198 return;
3199
3200 /* reset doesn't touch the display */
3201 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3202 return;
3203
3204 drm_modeset_lock_all(dev);
f98ce92f
VS
3205
3206 /*
3207 * Disabling the crtcs gracefully seems nicer. Also the
3208 * g33 docs say we should at least disable all the planes.
3209 */
3210 for_each_intel_crtc(dev, crtc) {
ce22dba9
ML
3211 if (!crtc->active)
3212 continue;
3213
3214 intel_crtc_disable_planes(&crtc->base);
3215 dev_priv->display.crtc_disable(&crtc->base);
f98ce92f 3216 }
7514747d
VS
3217}
3218
3219void intel_finish_reset(struct drm_device *dev)
3220{
3221 struct drm_i915_private *dev_priv = to_i915(dev);
3222
3223 /*
3224 * Flips in the rings will be nuked by the reset,
3225 * so complete all pending flips so that user space
3226 * will get its events and not get stuck.
3227 */
3228 intel_complete_page_flips(dev);
3229
3230 /* no reset support for gen2 */
3231 if (IS_GEN2(dev))
3232 return;
3233
3234 /* reset doesn't touch the display */
3235 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3236 /*
3237 * Flips in the rings have been nuked by the reset,
3238 * so update the base address of all primary
3239 * planes to the the last fb to make sure we're
3240 * showing the correct fb after a reset.
3241 */
3242 intel_update_primary_planes(dev);
3243 return;
3244 }
3245
3246 /*
3247 * The display has been reset as well,
3248 * so need a full re-initialization.
3249 */
3250 intel_runtime_pm_disable_interrupts(dev_priv);
3251 intel_runtime_pm_enable_interrupts(dev_priv);
3252
3253 intel_modeset_init_hw(dev);
3254
3255 spin_lock_irq(&dev_priv->irq_lock);
3256 if (dev_priv->display.hpd_irq_setup)
3257 dev_priv->display.hpd_irq_setup(dev);
3258 spin_unlock_irq(&dev_priv->irq_lock);
3259
3260 intel_modeset_setup_hw_state(dev, true);
3261
3262 intel_hpd_init(dev_priv);
3263
3264 drm_modeset_unlock_all(dev);
3265}
3266
2e2f351d 3267static void
14667a4b
CW
3268intel_finish_fb(struct drm_framebuffer *old_fb)
3269{
2ff8fde1 3270 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
2e2f351d 3271 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
14667a4b
CW
3272 bool was_interruptible = dev_priv->mm.interruptible;
3273 int ret;
3274
14667a4b
CW
3275 /* Big Hammer, we also need to ensure that any pending
3276 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3277 * current scanout is retired before unpinning the old
2e2f351d
CW
3278 * framebuffer. Note that we rely on userspace rendering
3279 * into the buffer attached to the pipe they are waiting
3280 * on. If not, userspace generates a GPU hang with IPEHR
3281 * point to the MI_WAIT_FOR_EVENT.
14667a4b
CW
3282 *
3283 * This should only fail upon a hung GPU, in which case we
3284 * can safely continue.
3285 */
3286 dev_priv->mm.interruptible = false;
2e2f351d 3287 ret = i915_gem_object_wait_rendering(obj, true);
14667a4b
CW
3288 dev_priv->mm.interruptible = was_interruptible;
3289
2e2f351d 3290 WARN_ON(ret);
14667a4b
CW
3291}
3292
7d5e3799
CW
3293static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3294{
3295 struct drm_device *dev = crtc->dev;
3296 struct drm_i915_private *dev_priv = dev->dev_private;
3297 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7d5e3799
CW
3298 bool pending;
3299
3300 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3301 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3302 return false;
3303
5e2d7afc 3304 spin_lock_irq(&dev->event_lock);
7d5e3799 3305 pending = to_intel_crtc(crtc)->unpin_work != NULL;
5e2d7afc 3306 spin_unlock_irq(&dev->event_lock);
7d5e3799
CW
3307
3308 return pending;
3309}
3310
e30e8f75
GP
3311static void intel_update_pipe_size(struct intel_crtc *crtc)
3312{
3313 struct drm_device *dev = crtc->base.dev;
3314 struct drm_i915_private *dev_priv = dev->dev_private;
3315 const struct drm_display_mode *adjusted_mode;
3316
3317 if (!i915.fastboot)
3318 return;
3319
3320 /*
3321 * Update pipe size and adjust fitter if needed: the reason for this is
3322 * that in compute_mode_changes we check the native mode (not the pfit
3323 * mode) to see if we can flip rather than do a full mode set. In the
3324 * fastboot case, we'll flip, but if we don't update the pipesrc and
3325 * pfit state, we'll end up with a big fb scanned out into the wrong
3326 * sized surface.
3327 *
3328 * To fix this properly, we need to hoist the checks up into
3329 * compute_mode_changes (or above), check the actual pfit state and
3330 * whether the platform allows pfit disable with pipe active, and only
3331 * then update the pipesrc and pfit state, even on the flip path.
3332 */
3333
6e3c9717 3334 adjusted_mode = &crtc->config->base.adjusted_mode;
e30e8f75
GP
3335
3336 I915_WRITE(PIPESRC(crtc->pipe),
3337 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3338 (adjusted_mode->crtc_vdisplay - 1));
6e3c9717 3339 if (!crtc->config->pch_pfit.enabled &&
409ee761
ACO
3340 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3341 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
e30e8f75
GP
3342 I915_WRITE(PF_CTL(crtc->pipe), 0);
3343 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3344 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3345 }
6e3c9717
ACO
3346 crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3347 crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
e30e8f75
GP
3348}
3349
5e84e1a4
ZW
3350static void intel_fdi_normal_train(struct drm_crtc *crtc)
3351{
3352 struct drm_device *dev = crtc->dev;
3353 struct drm_i915_private *dev_priv = dev->dev_private;
3354 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3355 int pipe = intel_crtc->pipe;
3356 u32 reg, temp;
3357
3358 /* enable normal train */
3359 reg = FDI_TX_CTL(pipe);
3360 temp = I915_READ(reg);
61e499bf 3361 if (IS_IVYBRIDGE(dev)) {
357555c0
JB
3362 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3363 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP
3364 } else {
3365 temp &= ~FDI_LINK_TRAIN_NONE;
3366 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 3367 }
5e84e1a4
ZW
3368 I915_WRITE(reg, temp);
3369
3370 reg = FDI_RX_CTL(pipe);
3371 temp = I915_READ(reg);
3372 if (HAS_PCH_CPT(dev)) {
3373 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3374 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3375 } else {
3376 temp &= ~FDI_LINK_TRAIN_NONE;
3377 temp |= FDI_LINK_TRAIN_NONE;
3378 }
3379 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3380
3381 /* wait one idle pattern time */
3382 POSTING_READ(reg);
3383 udelay(1000);
357555c0
JB
3384
3385 /* IVB wants error correction enabled */
3386 if (IS_IVYBRIDGE(dev))
3387 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3388 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW
3389}
3390
8db9d77b
ZW
3391/* The FDI link training functions for ILK/Ibexpeak. */
3392static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3393{
3394 struct drm_device *dev = crtc->dev;
3395 struct drm_i915_private *dev_priv = dev->dev_private;
3396 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3397 int pipe = intel_crtc->pipe;
5eddb70b 3398 u32 reg, temp, tries;
8db9d77b 3399
1c8562f6 3400 /* FDI needs bits from pipe first */
0fc932b8 3401 assert_pipe_enabled(dev_priv, pipe);
0fc932b8 3402
e1a44743
AJ
3403 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3404 for train result */
5eddb70b
CW
3405 reg = FDI_RX_IMR(pipe);
3406 temp = I915_READ(reg);
e1a44743
AJ
3407 temp &= ~FDI_RX_SYMBOL_LOCK;
3408 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW
3409 I915_WRITE(reg, temp);
3410 I915_READ(reg);
e1a44743
AJ
3411 udelay(150);
3412
8db9d77b 3413 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW
3414 reg = FDI_TX_CTL(pipe);
3415 temp = I915_READ(reg);
627eb5a3 3416 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3417 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
8db9d77b
ZW
3418 temp &= ~FDI_LINK_TRAIN_NONE;
3419 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 3420 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 3421
5eddb70b
CW
3422 reg = FDI_RX_CTL(pipe);
3423 temp = I915_READ(reg);
8db9d77b
ZW
3424 temp &= ~FDI_LINK_TRAIN_NONE;
3425 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW
3426 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3427
3428 POSTING_READ(reg);
8db9d77b
ZW
3429 udelay(150);
3430
5b2adf89 3431 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV
3432 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3433 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3434 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 3435
5eddb70b 3436 reg = FDI_RX_IIR(pipe);
e1a44743 3437 for (tries = 0; tries < 5; tries++) {
5eddb70b 3438 temp = I915_READ(reg);
8db9d77b
ZW
3439 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3440
3441 if ((temp & FDI_RX_BIT_LOCK)) {
3442 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 3443 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW
3444 break;
3445 }
8db9d77b 3446 }
e1a44743 3447 if (tries == 5)
5eddb70b 3448 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW
3449
3450 /* Train 2 */
5eddb70b
CW
3451 reg = FDI_TX_CTL(pipe);
3452 temp = I915_READ(reg);
8db9d77b
ZW
3453 temp &= ~FDI_LINK_TRAIN_NONE;
3454 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 3455 I915_WRITE(reg, temp);
8db9d77b 3456
5eddb70b
CW
3457 reg = FDI_RX_CTL(pipe);
3458 temp = I915_READ(reg);
8db9d77b
ZW
3459 temp &= ~FDI_LINK_TRAIN_NONE;
3460 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 3461 I915_WRITE(reg, temp);
8db9d77b 3462
5eddb70b
CW
3463 POSTING_READ(reg);
3464 udelay(150);
8db9d77b 3465
5eddb70b 3466 reg = FDI_RX_IIR(pipe);
e1a44743 3467 for (tries = 0; tries < 5; tries++) {
5eddb70b 3468 temp = I915_READ(reg);
8db9d77b
ZW
3469 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3470
3471 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 3472 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW
3473 DRM_DEBUG_KMS("FDI train 2 done.\n");
3474 break;
3475 }
8db9d77b 3476 }
e1a44743 3477 if (tries == 5)
5eddb70b 3478 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW
3479
3480 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 3481
8db9d77b
ZW
3482}
3483
0206e353 3484static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW
3485 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3486 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3487 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3488 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3489};
3490
3491/* The FDI link training functions for SNB/Cougarpoint. */
3492static void gen6_fdi_link_train(struct drm_crtc *crtc)
3493{
3494 struct drm_device *dev = crtc->dev;
3495 struct drm_i915_private *dev_priv = dev->dev_private;
3496 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3497 int pipe = intel_crtc->pipe;
fa37d39e 3498 u32 reg, temp, i, retry;
8db9d77b 3499
e1a44743
AJ
3500 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3501 for train result */
5eddb70b
CW
3502 reg = FDI_RX_IMR(pipe);
3503 temp = I915_READ(reg);
e1a44743
AJ
3504 temp &= ~FDI_RX_SYMBOL_LOCK;
3505 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW
3506 I915_WRITE(reg, temp);
3507
3508 POSTING_READ(reg);
e1a44743
AJ
3509 udelay(150);
3510
8db9d77b 3511 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW
3512 reg = FDI_TX_CTL(pipe);
3513 temp = I915_READ(reg);
627eb5a3 3514 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3515 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
8db9d77b
ZW
3516 temp &= ~FDI_LINK_TRAIN_NONE;
3517 temp |= FDI_LINK_TRAIN_PATTERN_1;
3518 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3519 /* SNB-B */
3520 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 3521 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 3522
d74cf324
DV
3523 I915_WRITE(FDI_RX_MISC(pipe),
3524 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3525
5eddb70b
CW
3526 reg = FDI_RX_CTL(pipe);
3527 temp = I915_READ(reg);
8db9d77b
ZW
3528 if (HAS_PCH_CPT(dev)) {
3529 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3530 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3531 } else {
3532 temp &= ~FDI_LINK_TRAIN_NONE;
3533 temp |= FDI_LINK_TRAIN_PATTERN_1;
3534 }
5eddb70b
CW
3535 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3536
3537 POSTING_READ(reg);
8db9d77b
ZW
3538 udelay(150);
3539
0206e353 3540 for (i = 0; i < 4; i++) {
5eddb70b
CW
3541 reg = FDI_TX_CTL(pipe);
3542 temp = I915_READ(reg);
8db9d77b
ZW
3543 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3544 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW
3545 I915_WRITE(reg, temp);
3546
3547 POSTING_READ(reg);
8db9d77b
ZW
3548 udelay(500);
3549
fa37d39e
SP
3550 for (retry = 0; retry < 5; retry++) {
3551 reg = FDI_RX_IIR(pipe);
3552 temp = I915_READ(reg);
3553 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3554 if (temp & FDI_RX_BIT_LOCK) {
3555 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3556 DRM_DEBUG_KMS("FDI train 1 done.\n");
3557 break;
3558 }
3559 udelay(50);
8db9d77b 3560 }
fa37d39e
SP
3561 if (retry < 5)
3562 break;
8db9d77b
ZW
3563 }
3564 if (i == 4)
5eddb70b 3565 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW
3566
3567 /* Train 2 */
5eddb70b
CW
3568 reg = FDI_TX_CTL(pipe);
3569 temp = I915_READ(reg);
8db9d77b
ZW
3570 temp &= ~FDI_LINK_TRAIN_NONE;
3571 temp |= FDI_LINK_TRAIN_PATTERN_2;
3572 if (IS_GEN6(dev)) {
3573 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3574 /* SNB-B */
3575 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3576 }
5eddb70b 3577 I915_WRITE(reg, temp);
8db9d77b 3578
5eddb70b
CW
3579 reg = FDI_RX_CTL(pipe);
3580 temp = I915_READ(reg);
8db9d77b
ZW
3581 if (HAS_PCH_CPT(dev)) {
3582 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3583 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3584 } else {
3585 temp &= ~FDI_LINK_TRAIN_NONE;
3586 temp |= FDI_LINK_TRAIN_PATTERN_2;
3587 }
5eddb70b
CW
3588 I915_WRITE(reg, temp);
3589
3590 POSTING_READ(reg);
8db9d77b
ZW
3591 udelay(150);
3592
0206e353 3593 for (i = 0; i < 4; i++) {
5eddb70b
CW
3594 reg = FDI_TX_CTL(pipe);
3595 temp = I915_READ(reg);
8db9d77b
ZW
3596 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3597 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW
3598 I915_WRITE(reg, temp);
3599
3600 POSTING_READ(reg);
8db9d77b
ZW
3601 udelay(500);
3602
fa37d39e
SP
3603 for (retry = 0; retry < 5; retry++) {
3604 reg = FDI_RX_IIR(pipe);
3605 temp = I915_READ(reg);
3606 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3607 if (temp & FDI_RX_SYMBOL_LOCK) {
3608 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3609 DRM_DEBUG_KMS("FDI train 2 done.\n");
3610 break;
3611 }
3612 udelay(50);
8db9d77b 3613 }
fa37d39e
SP
3614 if (retry < 5)
3615 break;
8db9d77b
ZW
3616 }
3617 if (i == 4)
5eddb70b 3618 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW
3619
3620 DRM_DEBUG_KMS("FDI train done.\n");
3621}
3622
357555c0
JB
3623/* Manual link training for Ivy Bridge A0 parts */
3624static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3625{
3626 struct drm_device *dev = crtc->dev;
3627 struct drm_i915_private *dev_priv = dev->dev_private;
3628 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3629 int pipe = intel_crtc->pipe;
139ccd3f 3630 u32 reg, temp, i, j;
357555c0
JB
3631
3632 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3633 for train result */
3634 reg = FDI_RX_IMR(pipe);
3635 temp = I915_READ(reg);
3636 temp &= ~FDI_RX_SYMBOL_LOCK;
3637 temp &= ~FDI_RX_BIT_LOCK;
3638 I915_WRITE(reg, temp);
3639
3640 POSTING_READ(reg);
3641 udelay(150);
3642
01a415fd
DV
3643 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3644 I915_READ(FDI_RX_IIR(pipe)));
3645
139ccd3f
JB
3646 /* Try each vswing and preemphasis setting twice before moving on */
3647 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3648 /* disable first in case we need to retry */
3649 reg = FDI_TX_CTL(pipe);
3650 temp = I915_READ(reg);
3651 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3652 temp &= ~FDI_TX_ENABLE;
3653 I915_WRITE(reg, temp);
357555c0 3654
139ccd3f
JB
3655 reg = FDI_RX_CTL(pipe);
3656 temp = I915_READ(reg);
3657 temp &= ~FDI_LINK_TRAIN_AUTO;
3658 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3659 temp &= ~FDI_RX_ENABLE;
3660 I915_WRITE(reg, temp);
357555c0 3661
139ccd3f 3662 /* enable CPU FDI TX and PCH FDI RX */
357555c0
JB
3663 reg = FDI_TX_CTL(pipe);
3664 temp = I915_READ(reg);
139ccd3f 3665 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3666 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
139ccd3f 3667 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
357555c0 3668 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
139ccd3f
JB
3669 temp |= snb_b_fdi_train_param[j/2];
3670 temp |= FDI_COMPOSITE_SYNC;
3671 I915_WRITE(reg, temp | FDI_TX_ENABLE);
357555c0 3672
139ccd3f
JB
3673 I915_WRITE(FDI_RX_MISC(pipe),
3674 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
357555c0 3675
139ccd3f 3676 reg = FDI_RX_CTL(pipe);
357555c0 3677 temp = I915_READ(reg);
139ccd3f
JB
3678 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3679 temp |= FDI_COMPOSITE_SYNC;
3680 I915_WRITE(reg, temp | FDI_RX_ENABLE);
357555c0 3681
139ccd3f
JB
3682 POSTING_READ(reg);
3683 udelay(1); /* should be 0.5us */
357555c0 3684
139ccd3f
JB
3685 for (i = 0; i < 4; i++) {
3686 reg = FDI_RX_IIR(pipe);
3687 temp = I915_READ(reg);
3688 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 3689
139ccd3f
JB
3690 if (temp & FDI_RX_BIT_LOCK ||
3691 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3692 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3693 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3694 i);
3695 break;
3696 }
3697 udelay(1); /* should be 0.5us */
3698 }
3699 if (i == 4) {
3700 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3701 continue;
3702 }
357555c0 3703
139ccd3f 3704 /* Train 2 */
357555c0
JB
3705 reg = FDI_TX_CTL(pipe);
3706 temp = I915_READ(reg);
139ccd3f
JB
3707 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3708 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3709 I915_WRITE(reg, temp);
3710
3711 reg = FDI_RX_CTL(pipe);
3712 temp = I915_READ(reg);
3713 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3714 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
357555c0
JB
3715 I915_WRITE(reg, temp);
3716
3717 POSTING_READ(reg);
139ccd3f 3718 udelay(2); /* should be 1.5us */
357555c0 3719
139ccd3f
JB
3720 for (i = 0; i < 4; i++) {
3721 reg = FDI_RX_IIR(pipe);
3722 temp = I915_READ(reg);
3723 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 3724
139ccd3f
JB
3725 if (temp & FDI_RX_SYMBOL_LOCK ||
3726 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3727 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3728 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3729 i);
3730 goto train_done;
3731 }
3732 udelay(2); /* should be 1.5us */
357555c0 3733 }
139ccd3f
JB
3734 if (i == 4)
3735 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
357555c0 3736 }
357555c0 3737
139ccd3f 3738train_done:
357555c0
JB
3739 DRM_DEBUG_KMS("FDI train done.\n");
3740}
3741
88cefb6c 3742static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 3743{
88cefb6c 3744 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 3745 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 3746 int pipe = intel_crtc->pipe;
5eddb70b 3747 u32 reg, temp;
79e53945 3748
c64e311e 3749
c98e9dcf 3750 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW
3751 reg = FDI_RX_CTL(pipe);
3752 temp = I915_READ(reg);
627eb5a3 3753 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
6e3c9717 3754 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
dfd07d72 3755 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW
3756 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3757
3758 POSTING_READ(reg);
c98e9dcf
JB
3759 udelay(200);
3760
3761 /* Switch from Rawclk to PCDclk */
5eddb70b
CW
3762 temp = I915_READ(reg);
3763 I915_WRITE(reg, temp | FDI_PCDCLK);
3764
3765 POSTING_READ(reg);
c98e9dcf
JB
3766 udelay(200);
3767
20749730
PZ
3768 /* Enable CPU FDI TX PLL, always on for Ironlake */
3769 reg = FDI_TX_CTL(pipe);
3770 temp = I915_READ(reg);
3771 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3772 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 3773
20749730
PZ
3774 POSTING_READ(reg);
3775 udelay(100);
6be4a607 3776 }
0e23b99d
JB
3777}
3778
88cefb6c
DV
3779static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3780{
3781 struct drm_device *dev = intel_crtc->base.dev;
3782 struct drm_i915_private *dev_priv = dev->dev_private;
3783 int pipe = intel_crtc->pipe;
3784 u32 reg, temp;
3785
3786 /* Switch from PCDclk to Rawclk */
3787 reg = FDI_RX_CTL(pipe);
3788 temp = I915_READ(reg);
3789 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3790
3791 /* Disable CPU FDI TX PLL */
3792 reg = FDI_TX_CTL(pipe);
3793 temp = I915_READ(reg);
3794 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3795
3796 POSTING_READ(reg);
3797 udelay(100);
3798
3799 reg = FDI_RX_CTL(pipe);
3800 temp = I915_READ(reg);
3801 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3802
3803 /* Wait for the clocks to turn off. */
3804 POSTING_READ(reg);
3805 udelay(100);
3806}
3807
0fc932b8
JB
3808static void ironlake_fdi_disable(struct drm_crtc *crtc)
3809{
3810 struct drm_device *dev = crtc->dev;
3811 struct drm_i915_private *dev_priv = dev->dev_private;
3812 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3813 int pipe = intel_crtc->pipe;
3814 u32 reg, temp;
3815
3816 /* disable CPU FDI tx and PCH FDI rx */
3817 reg = FDI_TX_CTL(pipe);
3818 temp = I915_READ(reg);
3819 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3820 POSTING_READ(reg);
3821
3822 reg = FDI_RX_CTL(pipe);
3823 temp = I915_READ(reg);
3824 temp &= ~(0x7 << 16);
dfd07d72 3825 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB
3826 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3827
3828 POSTING_READ(reg);
3829 udelay(100);
3830
3831 /* Ironlake workaround, disable clock pointer after downing FDI */
eba905b2 3832 if (HAS_PCH_IBX(dev))
6f06ce18 3833 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
0fc932b8
JB
3834
3835 /* still set train pattern 1 */
3836 reg = FDI_TX_CTL(pipe);
3837 temp = I915_READ(reg);
3838 temp &= ~FDI_LINK_TRAIN_NONE;
3839 temp |= FDI_LINK_TRAIN_PATTERN_1;
3840 I915_WRITE(reg, temp);
3841
3842 reg = FDI_RX_CTL(pipe);
3843 temp = I915_READ(reg);
3844 if (HAS_PCH_CPT(dev)) {
3845 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3846 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3847 } else {
3848 temp &= ~FDI_LINK_TRAIN_NONE;
3849 temp |= FDI_LINK_TRAIN_PATTERN_1;
3850 }
3851 /* BPC in FDI rx is consistent with that in PIPECONF */
3852 temp &= ~(0x07 << 16);
dfd07d72 3853 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB
3854 I915_WRITE(reg, temp);
3855
3856 POSTING_READ(reg);
3857 udelay(100);
3858}
3859
5dce5b93
CW
3860bool intel_has_pending_fb_unpin(struct drm_device *dev)
3861{
3862 struct intel_crtc *crtc;
3863
3864 /* Note that we don't need to be called with mode_config.lock here
3865 * as our list of CRTC objects is static for the lifetime of the
3866 * device and so cannot disappear as we iterate. Similarly, we can
3867 * happily treat the predicates as racy, atomic checks as userspace
3868 * cannot claim and pin a new fb without at least acquring the
3869 * struct_mutex and so serialising with us.
3870 */
d3fcc808 3871 for_each_intel_crtc(dev, crtc) {
5dce5b93
CW
3872 if (atomic_read(&crtc->unpin_work_count) == 0)
3873 continue;
3874
3875 if (crtc->unpin_work)
3876 intel_wait_for_vblank(dev, crtc->pipe);
3877
3878 return true;
3879 }
3880
3881 return false;
3882}
3883
d6bbafa1
CW
3884static void page_flip_completed(struct intel_crtc *intel_crtc)
3885{
3886 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3887 struct intel_unpin_work *work = intel_crtc->unpin_work;
3888
3889 /* ensure that the unpin work is consistent wrt ->pending. */
3890 smp_rmb();
3891 intel_crtc->unpin_work = NULL;
3892
3893 if (work->event)
3894 drm_send_vblank_event(intel_crtc->base.dev,
3895 intel_crtc->pipe,
3896 work->event);
3897
3898 drm_crtc_vblank_put(&intel_crtc->base);
3899
3900 wake_up_all(&dev_priv->pending_flip_queue);
3901 queue_work(dev_priv->wq, &work->work);
3902
3903 trace_i915_flip_complete(intel_crtc->plane,
3904 work->pending_flip_obj);
3905}
3906
46a55d30 3907void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
e6c3a2a6 3908{
0f91128d 3909 struct drm_device *dev = crtc->dev;
5bb61643 3910 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6 3911
2c10d571 3912 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
9c787942
CW
3913 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3914 !intel_crtc_has_pending_flip(crtc),
3915 60*HZ) == 0)) {
3916 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2c10d571 3917
5e2d7afc 3918 spin_lock_irq(&dev->event_lock);
9c787942
CW
3919 if (intel_crtc->unpin_work) {
3920 WARN_ONCE(1, "Removing stuck page flip\n");
3921 page_flip_completed(intel_crtc);
3922 }
5e2d7afc 3923 spin_unlock_irq(&dev->event_lock);
9c787942 3924 }
5bb61643 3925
975d568a
CW
3926 if (crtc->primary->fb) {
3927 mutex_lock(&dev->struct_mutex);
3928 intel_finish_fb(crtc->primary->fb);
3929 mutex_unlock(&dev->struct_mutex);
3930 }
e6c3a2a6
CW
3931}
3932
e615efe4
ED
3933/* Program iCLKIP clock to the desired frequency */
3934static void lpt_program_iclkip(struct drm_crtc *crtc)
3935{
3936 struct drm_device *dev = crtc->dev;
3937 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 3938 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
e615efe4
ED
3939 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3940 u32 temp;
3941
a580516d 3942 mutex_lock(&dev_priv->sb_lock);
09153000 3943
e615efe4
ED
3944 /* It is necessary to ungate the pixclk gate prior to programming
3945 * the divisors, and gate it back when it is done.
3946 */
3947 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3948
3949 /* Disable SSCCTL */
3950 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ
3951 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3952 SBI_SSCCTL_DISABLE,
3953 SBI_ICLK);
e615efe4
ED
3954
3955 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
12d7ceed 3956 if (clock == 20000) {
e615efe4
ED
3957 auxdiv = 1;
3958 divsel = 0x41;
3959 phaseinc = 0x20;
3960 } else {
3961 /* The iCLK virtual clock root frequency is in MHz,
241bfc38
DL
3962 * but the adjusted_mode->crtc_clock in in KHz. To get the
3963 * divisors, it is necessary to divide one by another, so we
e615efe4
ED
3964 * convert the virtual clock precision to KHz here for higher
3965 * precision.
3966 */
3967 u32 iclk_virtual_root_freq = 172800 * 1000;
3968 u32 iclk_pi_range = 64;
3969 u32 desired_divisor, msb_divisor_value, pi_value;
3970
12d7ceed 3971 desired_divisor = (iclk_virtual_root_freq / clock);
e615efe4
ED
3972 msb_divisor_value = desired_divisor / iclk_pi_range;
3973 pi_value = desired_divisor % iclk_pi_range;
3974
3975 auxdiv = 0;
3976 divsel = msb_divisor_value - 2;
3977 phaseinc = pi_value;
3978 }
3979
3980 /* This should not happen with any sane values */
3981 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3982 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3983 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3984 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3985
3986 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
12d7ceed 3987 clock,
e615efe4
ED
3988 auxdiv,
3989 divsel,
3990 phasedir,
3991 phaseinc);
3992
3993 /* Program SSCDIVINTPHASE6 */
988d6ee8 3994 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED
3995 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3996 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3997 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3998 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3999 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4000 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 4001 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED
4002
4003 /* Program SSCAUXDIV */
988d6ee8 4004 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED
4005 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4006 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 4007 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED
4008
4009 /* Enable modulator and associated divider */
988d6ee8 4010 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 4011 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 4012 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED
4013
4014 /* Wait for initialization time */
4015 udelay(24);
4016
4017 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000 4018
a580516d 4019 mutex_unlock(&dev_priv->sb_lock);
e615efe4
ED
4020}
4021
275f01b2
DV
4022static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4023 enum pipe pch_transcoder)
4024{
4025 struct drm_device *dev = crtc->base.dev;
4026 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 4027 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
275f01b2
DV
4028
4029 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4030 I915_READ(HTOTAL(cpu_transcoder)));
4031 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4032 I915_READ(HBLANK(cpu_transcoder)));
4033 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4034 I915_READ(HSYNC(cpu_transcoder)));
4035
4036 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4037 I915_READ(VTOTAL(cpu_transcoder)));
4038 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4039 I915_READ(VBLANK(cpu_transcoder)));
4040 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4041 I915_READ(VSYNC(cpu_transcoder)));
4042 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4043 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4044}
4045
003632d9 4046static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
1fbc0d78
DV
4047{
4048 struct drm_i915_private *dev_priv = dev->dev_private;
4049 uint32_t temp;
4050
4051 temp = I915_READ(SOUTH_CHICKEN1);
003632d9 4052 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
1fbc0d78
DV
4053 return;
4054
4055 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4056 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4057
003632d9
ACO
4058 temp &= ~FDI_BC_BIFURCATION_SELECT;
4059 if (enable)
4060 temp |= FDI_BC_BIFURCATION_SELECT;
4061
4062 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
1fbc0d78
DV
4063 I915_WRITE(SOUTH_CHICKEN1, temp);
4064 POSTING_READ(SOUTH_CHICKEN1);
4065}
4066
4067static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4068{
4069 struct drm_device *dev = intel_crtc->base.dev;
1fbc0d78
DV
4070
4071 switch (intel_crtc->pipe) {
4072 case PIPE_A:
4073 break;
4074 case PIPE_B:
6e3c9717 4075 if (intel_crtc->config->fdi_lanes > 2)
003632d9 4076 cpt_set_fdi_bc_bifurcation(dev, false);
1fbc0d78 4077 else
003632d9 4078 cpt_set_fdi_bc_bifurcation(dev, true);
1fbc0d78
DV
4079
4080 break;
4081 case PIPE_C:
003632d9 4082 cpt_set_fdi_bc_bifurcation(dev, true);
1fbc0d78
DV
4083
4084 break;
4085 default:
4086 BUG();
4087 }
4088}
4089
f67a559d
JB
4090/*
4091 * Enable PCH resources required for PCH ports:
4092 * - PCH PLLs
4093 * - FDI training & RX/TX
4094 * - update transcoder timings
4095 * - DP transcoding bits
4096 * - transcoder
4097 */
4098static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB
4099{
4100 struct drm_device *dev = crtc->dev;
4101 struct drm_i915_private *dev_priv = dev->dev_private;
4102 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4103 int pipe = intel_crtc->pipe;
ee7b9f93 4104 u32 reg, temp;
2c07245f 4105
ab9412ba 4106 assert_pch_transcoder_disabled(dev_priv, pipe);
e7e164db 4107
1fbc0d78
DV
4108 if (IS_IVYBRIDGE(dev))
4109 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4110
cd986abb
DV
4111 /* Write the TU size bits before fdi link training, so that error
4112 * detection works. */
4113 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4114 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4115
c98e9dcf 4116 /* For PCH output, training FDI link */
674cf967 4117 dev_priv->display.fdi_link_train(crtc);
2c07245f 4118
3ad8a208
DV
4119 /* We need to program the right clock selection before writing the pixel
4120 * mutliplier into the DPLL. */
303b81e0 4121 if (HAS_PCH_CPT(dev)) {
ee7b9f93 4122 u32 sel;
4b645f14 4123
c98e9dcf 4124 temp = I915_READ(PCH_DPLL_SEL);
11887397
DV
4125 temp |= TRANS_DPLL_ENABLE(pipe);
4126 sel = TRANS_DPLLB_SEL(pipe);
6e3c9717 4127 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
ee7b9f93
JB
4128 temp |= sel;
4129 else
4130 temp &= ~sel;
c98e9dcf 4131 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 4132 }
5eddb70b 4133
3ad8a208
DV
4134 /* XXX: pch pll's can be enabled any time before we enable the PCH
4135 * transcoder, and we actually should do this to not upset any PCH
4136 * transcoder that already use the clock when we share it.
4137 *
4138 * Note that enable_shared_dpll tries to do the right thing, but
4139 * get_shared_dpll unconditionally resets the pll - we need that to have
4140 * the right LVDS enable sequence. */
85b3894f 4141 intel_enable_shared_dpll(intel_crtc);
3ad8a208 4142
d9b6cb56
JB
4143 /* set transcoder timing, panel must allow it */
4144 assert_panel_unlocked(dev_priv, pipe);
275f01b2 4145 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
8db9d77b 4146
303b81e0 4147 intel_fdi_normal_train(crtc);
5e84e1a4 4148
c98e9dcf 4149 /* For PCH DP, enable TRANS_DP_CTL */
6e3c9717 4150 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
dfd07d72 4151 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW
4152 reg = TRANS_DP_CTL(pipe);
4153 temp = I915_READ(reg);
4154 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA
4155 TRANS_DP_SYNC_MASK |
4156 TRANS_DP_BPC_MASK);
e3ef4479 4157 temp |= TRANS_DP_OUTPUT_ENABLE;
9325c9f0 4158 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB
4159
4160 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 4161 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 4162 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 4163 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB
4164
4165 switch (intel_trans_dp_port_sel(crtc)) {
4166 case PCH_DP_B:
5eddb70b 4167 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB
4168 break;
4169 case PCH_DP_C:
5eddb70b 4170 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB
4171 break;
4172 case PCH_DP_D:
5eddb70b 4173 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB
4174 break;
4175 default:
e95d41e1 4176 BUG();
32f9d658 4177 }
2c07245f 4178
5eddb70b 4179 I915_WRITE(reg, temp);
6be4a607 4180 }
b52eb4dc 4181
b8a4f404 4182 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB
4183}
4184
1507e5bd
PZ
4185static void lpt_pch_enable(struct drm_crtc *crtc)
4186{
4187 struct drm_device *dev = crtc->dev;
4188 struct drm_i915_private *dev_priv = dev->dev_private;
4189 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 4190 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1507e5bd 4191
ab9412ba 4192 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 4193
8c52b5e8 4194 lpt_program_iclkip(crtc);
1507e5bd 4195
0540e488 4196 /* Set transcoder timing. */
275f01b2 4197 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
1507e5bd 4198
937bb610 4199 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB
4200}
4201
716c2e55 4202void intel_put_shared_dpll(struct intel_crtc *crtc)
ee7b9f93 4203{
e2b78267 4204 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
ee7b9f93
JB
4205
4206 if (pll == NULL)
4207 return;
4208
3e369b76 4209 if (!(pll->config.crtc_mask & (1 << crtc->pipe))) {
1e6f2ddc 4210 WARN(1, "bad %s crtc mask\n", pll->name);
ee7b9f93
JB
4211 return;
4212 }
4213
3e369b76
ACO
4214 pll->config.crtc_mask &= ~(1 << crtc->pipe);
4215 if (pll->config.crtc_mask == 0) {
f4a091c7
DV
4216 WARN_ON(pll->on);
4217 WARN_ON(pll->active);
4218 }
4219
6e3c9717 4220 crtc->config->shared_dpll = DPLL_ID_PRIVATE;
ee7b9f93
JB
4221}
4222
190f68c5
ACO
4223struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4224 struct intel_crtc_state *crtc_state)
ee7b9f93 4225{
e2b78267 4226 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8bd31e67 4227 struct intel_shared_dpll *pll;
e2b78267 4228 enum intel_dpll_id i;
ee7b9f93 4229
98b6bd99
DV
4230 if (HAS_PCH_IBX(dev_priv->dev)) {
4231 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
d94ab068 4232 i = (enum intel_dpll_id) crtc->pipe;
e72f9fbf 4233 pll = &dev_priv->shared_dplls[i];
98b6bd99 4234
46edb027
DV
4235 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4236 crtc->base.base.id, pll->name);
98b6bd99 4237
8bd31e67 4238 WARN_ON(pll->new_config->crtc_mask);
f2a69f44 4239
98b6bd99
DV
4240 goto found;
4241 }
4242
bcddf610
S
4243 if (IS_BROXTON(dev_priv->dev)) {
4244 /* PLL is attached to port in bxt */
4245 struct intel_encoder *encoder;
4246 struct intel_digital_port *intel_dig_port;
4247
4248 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4249 if (WARN_ON(!encoder))
4250 return NULL;
4251
4252 intel_dig_port = enc_to_dig_port(&encoder->base);
4253 /* 1:1 mapping between ports and PLLs */
4254 i = (enum intel_dpll_id)intel_dig_port->port;
4255 pll = &dev_priv->shared_dplls[i];
4256 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4257 crtc->base.base.id, pll->name);
4258 WARN_ON(pll->new_config->crtc_mask);
4259
4260 goto found;
4261 }
4262
e72f9fbf
DV
4263 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4264 pll = &dev_priv->shared_dplls[i];
ee7b9f93
JB
4265
4266 /* Only want to check enabled timings first */
8bd31e67 4267 if (pll->new_config->crtc_mask == 0)
ee7b9f93
JB
4268 continue;
4269
190f68c5 4270 if (memcmp(&crtc_state->dpll_hw_state,
8bd31e67
ACO
4271 &pll->new_config->hw_state,
4272 sizeof(pll->new_config->hw_state)) == 0) {
4273 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
1e6f2ddc 4274 crtc->base.base.id, pll->name,
8bd31e67
ACO
4275 pll->new_config->crtc_mask,
4276 pll->active);
ee7b9f93
JB
4277 goto found;
4278 }
4279 }
4280
4281 /* Ok no matching timings, maybe there's a free one? */
e72f9fbf
DV
4282 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4283 pll = &dev_priv->shared_dplls[i];
8bd31e67 4284 if (pll->new_config->crtc_mask == 0) {
46edb027
DV
4285 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4286 crtc->base.base.id, pll->name);
ee7b9f93
JB
4287 goto found;
4288 }
4289 }
4290
4291 return NULL;
4292
4293found:
8bd31e67 4294 if (pll->new_config->crtc_mask == 0)
190f68c5 4295 pll->new_config->hw_state = crtc_state->dpll_hw_state;
f2a69f44 4296
190f68c5 4297 crtc_state->shared_dpll = i;
46edb027
DV
4298 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4299 pipe_name(crtc->pipe));
ee7b9f93 4300
8bd31e67 4301 pll->new_config->crtc_mask |= 1 << crtc->pipe;
e04c7350 4302
ee7b9f93
JB
4303 return pll;
4304}
4305
8bd31e67
ACO
4306/**
4307 * intel_shared_dpll_start_config - start a new PLL staged config
4308 * @dev_priv: DRM device
4309 * @clear_pipes: mask of pipes that will have their PLLs freed
4310 *
4311 * Starts a new PLL staged config, copying the current config but
4312 * releasing the references of pipes specified in clear_pipes.
4313 */
4314static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv,
4315 unsigned clear_pipes)
4316{
4317 struct intel_shared_dpll *pll;
4318 enum intel_dpll_id i;
4319
4320 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4321 pll = &dev_priv->shared_dplls[i];
4322
4323 pll->new_config = kmemdup(&pll->config, sizeof pll->config,
4324 GFP_KERNEL);
4325 if (!pll->new_config)
4326 goto cleanup;
4327
4328 pll->new_config->crtc_mask &= ~clear_pipes;
4329 }
4330
4331 return 0;
4332
4333cleanup:
4334 while (--i >= 0) {
4335 pll = &dev_priv->shared_dplls[i];
f354d733 4336 kfree(pll->new_config);
8bd31e67
ACO
4337 pll->new_config = NULL;
4338 }
4339
4340 return -ENOMEM;
4341}
4342
4343static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv)
4344{
4345 struct intel_shared_dpll *pll;
4346 enum intel_dpll_id i;
4347
4348 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4349 pll = &dev_priv->shared_dplls[i];
4350
4351 WARN_ON(pll->new_config == &pll->config);
4352
4353 pll->config = *pll->new_config;
4354 kfree(pll->new_config);
4355 pll->new_config = NULL;
4356 }
4357}
4358
4359static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv)
4360{
4361 struct intel_shared_dpll *pll;
4362 enum intel_dpll_id i;
4363
4364 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4365 pll = &dev_priv->shared_dplls[i];
4366
4367 WARN_ON(pll->new_config == &pll->config);
4368
4369 kfree(pll->new_config);
4370 pll->new_config = NULL;
4371 }
4372}
4373
a1520318 4374static void cpt_verify_modeset(struct drm_device *dev, int pipe)
d4270e57
JB
4375{
4376 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 4377 int dslreg = PIPEDSL(pipe);
d4270e57
JB
4378 u32 temp;
4379
4380 temp = I915_READ(dslreg);
4381 udelay(500);
4382 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 4383 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 4384 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB
4385 }
4386}
4387
a1b2278e
CK
4388/**
4389 * skl_update_scaler_users - Stages update to crtc's scaler state
4390 * @intel_crtc: crtc
4391 * @crtc_state: crtc_state
4392 * @plane: plane (NULL indicates crtc is requesting update)
4393 * @plane_state: plane's state
4394 * @force_detach: request unconditional detachment of scaler
4395 *
4396 * This function updates scaler state for requested plane or crtc.
4397 * To request scaler usage update for a plane, caller shall pass plane pointer.
4398 * To request scaler usage update for crtc, caller shall pass plane pointer
4399 * as NULL.
4400 *
4401 * Return
4402 * 0 - scaler_usage updated successfully
4403 * error - requested scaling cannot be supported or other error condition
4404 */
4405int
4406skl_update_scaler_users(
4407 struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state,
4408 struct intel_plane *intel_plane, struct intel_plane_state *plane_state,
4409 int force_detach)
4410{
4411 int need_scaling;
4412 int idx;
4413 int src_w, src_h, dst_w, dst_h;
4414 int *scaler_id;
4415 struct drm_framebuffer *fb;
4416 struct intel_crtc_scaler_state *scaler_state;
6156a456 4417 unsigned int rotation;
a1b2278e
CK
4418
4419 if (!intel_crtc || !crtc_state)
4420 return 0;
4421
4422 scaler_state = &crtc_state->scaler_state;
4423
4424 idx = intel_plane ? drm_plane_index(&intel_plane->base) : SKL_CRTC_INDEX;
4425 fb = intel_plane ? plane_state->base.fb : NULL;
4426
4427 if (intel_plane) {
4428 src_w = drm_rect_width(&plane_state->src) >> 16;
4429 src_h = drm_rect_height(&plane_state->src) >> 16;
4430 dst_w = drm_rect_width(&plane_state->dst);
4431 dst_h = drm_rect_height(&plane_state->dst);
4432 scaler_id = &plane_state->scaler_id;
6156a456 4433 rotation = plane_state->base.rotation;
a1b2278e
CK
4434 } else {
4435 struct drm_display_mode *adjusted_mode =
4436 &crtc_state->base.adjusted_mode;
4437 src_w = crtc_state->pipe_src_w;
4438 src_h = crtc_state->pipe_src_h;
4439 dst_w = adjusted_mode->hdisplay;
4440 dst_h = adjusted_mode->vdisplay;
4441 scaler_id = &scaler_state->scaler_id;
6156a456 4442 rotation = DRM_ROTATE_0;
a1b2278e 4443 }
6156a456
CK
4444
4445 need_scaling = intel_rotation_90_or_270(rotation) ?
4446 (src_h != dst_w || src_w != dst_h):
4447 (src_w != dst_w || src_h != dst_h);
a1b2278e
CK
4448
4449 /*
4450 * if plane is being disabled or scaler is no more required or force detach
4451 * - free scaler binded to this plane/crtc
4452 * - in order to do this, update crtc->scaler_usage
4453 *
4454 * Here scaler state in crtc_state is set free so that
4455 * scaler can be assigned to other user. Actual register
4456 * update to free the scaler is done in plane/panel-fit programming.
4457 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4458 */
4459 if (force_detach || !need_scaling || (intel_plane &&
4460 (!fb || !plane_state->visible))) {
4461 if (*scaler_id >= 0) {
4462 scaler_state->scaler_users &= ~(1 << idx);
4463 scaler_state->scalers[*scaler_id].in_use = 0;
4464
4465 DRM_DEBUG_KMS("Staged freeing scaler id %d.%d from %s:%d "
4466 "crtc_state = %p scaler_users = 0x%x\n",
4467 intel_crtc->pipe, *scaler_id, intel_plane ? "PLANE" : "CRTC",
4468 intel_plane ? intel_plane->base.base.id :
4469 intel_crtc->base.base.id, crtc_state,
4470 scaler_state->scaler_users);
4471 *scaler_id = -1;
4472 }
4473 return 0;
4474 }
4475
4476 /* range checks */
4477 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4478 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4479
4480 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4481 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4482 DRM_DEBUG_KMS("%s:%d scaler_user index %u.%u: src %ux%u dst %ux%u "
4483 "size is out of scaler range\n",
4484 intel_plane ? "PLANE" : "CRTC",
4485 intel_plane ? intel_plane->base.base.id : intel_crtc->base.base.id,
4486 intel_crtc->pipe, idx, src_w, src_h, dst_w, dst_h);
4487 return -EINVAL;
4488 }
4489
4490 /* check colorkey */
225c228a
CK
4491 if (WARN_ON(intel_plane &&
4492 intel_plane->ckey.flags != I915_SET_COLORKEY_NONE)) {
4493 DRM_DEBUG_KMS("PLANE:%d scaling %ux%u->%ux%u not allowed with colorkey",
4494 intel_plane->base.base.id, src_w, src_h, dst_w, dst_h);
a1b2278e
CK
4495 return -EINVAL;
4496 }
4497
4498 /* Check src format */
4499 if (intel_plane) {
4500 switch (fb->pixel_format) {
4501 case DRM_FORMAT_RGB565:
4502 case DRM_FORMAT_XBGR8888:
4503 case DRM_FORMAT_XRGB8888:
4504 case DRM_FORMAT_ABGR8888:
4505 case DRM_FORMAT_ARGB8888:
4506 case DRM_FORMAT_XRGB2101010:
a1b2278e 4507 case DRM_FORMAT_XBGR2101010:
a1b2278e
CK
4508 case DRM_FORMAT_YUYV:
4509 case DRM_FORMAT_YVYU:
4510 case DRM_FORMAT_UYVY:
4511 case DRM_FORMAT_VYUY:
4512 break;
4513 default:
4514 DRM_DEBUG_KMS("PLANE:%d FB:%d unsupported scaling format 0x%x\n",
4515 intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4516 return -EINVAL;
4517 }
4518 }
4519
4520 /* mark this plane as a scaler user in crtc_state */
4521 scaler_state->scaler_users |= (1 << idx);
4522 DRM_DEBUG_KMS("%s:%d staged scaling request for %ux%u->%ux%u "
4523 "crtc_state = %p scaler_users = 0x%x\n",
4524 intel_plane ? "PLANE" : "CRTC",
4525 intel_plane ? intel_plane->base.base.id : intel_crtc->base.base.id,
4526 src_w, src_h, dst_w, dst_h, crtc_state, scaler_state->scaler_users);
4527 return 0;
4528}
4529
4530static void skylake_pfit_update(struct intel_crtc *crtc, int enable)
bd2e244f
JB
4531{
4532 struct drm_device *dev = crtc->base.dev;
4533 struct drm_i915_private *dev_priv = dev->dev_private;
4534 int pipe = crtc->pipe;
a1b2278e
CK
4535 struct intel_crtc_scaler_state *scaler_state =
4536 &crtc->config->scaler_state;
4537
4538 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4539
4540 /* To update pfit, first update scaler state */
4541 skl_update_scaler_users(crtc, crtc->config, NULL, NULL, !enable);
4542 intel_atomic_setup_scalers(crtc->base.dev, crtc, crtc->config);
4543 skl_detach_scalers(crtc);
4544 if (!enable)
4545 return;
bd2e244f 4546
6e3c9717 4547 if (crtc->config->pch_pfit.enabled) {
a1b2278e
CK
4548 int id;
4549
4550 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4551 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4552 return;
4553 }
4554
4555 id = scaler_state->scaler_id;
4556 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4557 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4558 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4559 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4560
4561 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
bd2e244f
JB
4562 }
4563}
4564
b074cec8
JB
4565static void ironlake_pfit_enable(struct intel_crtc *crtc)
4566{
4567 struct drm_device *dev = crtc->base.dev;
4568 struct drm_i915_private *dev_priv = dev->dev_private;
4569 int pipe = crtc->pipe;
4570
6e3c9717 4571 if (crtc->config->pch_pfit.enabled) {
b074cec8
JB
4572 /* Force use of hard-coded filter coefficients
4573 * as some pre-programmed values are broken,
4574 * e.g. x201.
4575 */
4576 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4577 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4578 PF_PIPE_SEL_IVB(pipe));
4579 else
4580 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
6e3c9717
ACO
4581 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4582 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
d4270e57
JB
4583 }
4584}
4585
4a3b8769 4586static void intel_enable_sprite_planes(struct drm_crtc *crtc)
bb53d4ae
VS
4587{
4588 struct drm_device *dev = crtc->dev;
4589 enum pipe pipe = to_intel_crtc(crtc)->pipe;
af2b653b 4590 struct drm_plane *plane;
bb53d4ae
VS
4591 struct intel_plane *intel_plane;
4592
af2b653b
MR
4593 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4594 intel_plane = to_intel_plane(plane);
bb53d4ae
VS
4595 if (intel_plane->pipe == pipe)
4596 intel_plane_restore(&intel_plane->base);
af2b653b 4597 }
bb53d4ae
VS
4598}
4599
20bc8673 4600void hsw_enable_ips(struct intel_crtc *crtc)
d77e4531 4601{
cea165c3
VS
4602 struct drm_device *dev = crtc->base.dev;
4603 struct drm_i915_private *dev_priv = dev->dev_private;
d77e4531 4604
6e3c9717 4605 if (!crtc->config->ips_enabled)
d77e4531
PZ
4606 return;
4607
cea165c3
VS
4608 /* We can only enable IPS after we enable a plane and wait for a vblank */
4609 intel_wait_for_vblank(dev, crtc->pipe);
4610
d77e4531 4611 assert_plane_enabled(dev_priv, crtc->plane);
cea165c3 4612 if (IS_BROADWELL(dev)) {
2a114cc1
BW
4613 mutex_lock(&dev_priv->rps.hw_lock);
4614 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4615 mutex_unlock(&dev_priv->rps.hw_lock);
4616 /* Quoting Art Runyan: "its not safe to expect any particular
4617 * value in IPS_CTL bit 31 after enabling IPS through the
e59150dc
JB
4618 * mailbox." Moreover, the mailbox may return a bogus state,
4619 * so we need to just enable it and continue on.
2a114cc1
BW
4620 */
4621 } else {
4622 I915_WRITE(IPS_CTL, IPS_ENABLE);
4623 /* The bit only becomes 1 in the next vblank, so this wait here
4624 * is essentially intel_wait_for_vblank. If we don't have this
4625 * and don't wait for vblanks until the end of crtc_enable, then
4626 * the HW state readout code will complain that the expected
4627 * IPS_CTL value is not the one we read. */
4628 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4629 DRM_ERROR("Timed out waiting for IPS enable\n");
4630 }
d77e4531
PZ
4631}
4632
20bc8673 4633void hsw_disable_ips(struct intel_crtc *crtc)
d77e4531
PZ
4634{
4635 struct drm_device *dev = crtc->base.dev;
4636 struct drm_i915_private *dev_priv = dev->dev_private;
4637
6e3c9717 4638 if (!crtc->config->ips_enabled)
d77e4531
PZ
4639 return;
4640
4641 assert_plane_enabled(dev_priv, crtc->plane);
23d0b130 4642 if (IS_BROADWELL(dev)) {
2a114cc1
BW
4643 mutex_lock(&dev_priv->rps.hw_lock);
4644 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4645 mutex_unlock(&dev_priv->rps.hw_lock);
23d0b130
BW
4646 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4647 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4648 DRM_ERROR("Timed out waiting for IPS disable\n");
e59150dc 4649 } else {
2a114cc1 4650 I915_WRITE(IPS_CTL, 0);
e59150dc
JB
4651 POSTING_READ(IPS_CTL);
4652 }
d77e4531
PZ
4653
4654 /* We need to wait for a vblank before we can disable the plane. */
4655 intel_wait_for_vblank(dev, crtc->pipe);
4656}
4657
4658/** Loads the palette/gamma unit for the CRTC with the prepared values */
4659static void intel_crtc_load_lut(struct drm_crtc *crtc)
4660{
4661 struct drm_device *dev = crtc->dev;
4662 struct drm_i915_private *dev_priv = dev->dev_private;
4663 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4664 enum pipe pipe = intel_crtc->pipe;
4665 int palreg = PALETTE(pipe);
4666 int i;
4667 bool reenable_ips = false;
4668
4669 /* The clocks have to be on to load the palette. */
83d65738 4670 if (!crtc->state->enable || !intel_crtc->active)
d77e4531
PZ
4671 return;
4672
50360403 4673 if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
409ee761 4674 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
d77e4531
PZ
4675 assert_dsi_pll_enabled(dev_priv);
4676 else
4677 assert_pll_enabled(dev_priv, pipe);
4678 }
4679
4680 /* use legacy palette for Ironlake */
7a1db49a 4681 if (!HAS_GMCH_DISPLAY(dev))
d77e4531
PZ
4682 palreg = LGC_PALETTE(pipe);
4683
4684 /* Workaround : Do not read or write the pipe palette/gamma data while
4685 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4686 */
6e3c9717 4687 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
d77e4531
PZ
4688 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4689 GAMMA_MODE_MODE_SPLIT)) {
4690 hsw_disable_ips(intel_crtc);
4691 reenable_ips = true;
4692 }
4693
4694 for (i = 0; i < 256; i++) {
4695 I915_WRITE(palreg + 4 * i,
4696 (intel_crtc->lut_r[i] << 16) |
4697 (intel_crtc->lut_g[i] << 8) |
4698 intel_crtc->lut_b[i]);
4699 }
4700
4701 if (reenable_ips)
4702 hsw_enable_ips(intel_crtc);
4703}
4704
7cac945f 4705static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
d3eedb1a 4706{
7cac945f 4707 if (intel_crtc->overlay) {
d3eedb1a
VS
4708 struct drm_device *dev = intel_crtc->base.dev;
4709 struct drm_i915_private *dev_priv = dev->dev_private;
4710
4711 mutex_lock(&dev->struct_mutex);
4712 dev_priv->mm.interruptible = false;
4713 (void) intel_overlay_switch_off(intel_crtc->overlay);
4714 dev_priv->mm.interruptible = true;
4715 mutex_unlock(&dev->struct_mutex);
4716 }
4717
4718 /* Let userspace switch the overlay on again. In most cases userspace
4719 * has to recompute where to put it anyway.
4720 */
4721}
4722
87d4300a
ML
4723/**
4724 * intel_post_enable_primary - Perform operations after enabling primary plane
4725 * @crtc: the CRTC whose primary plane was just enabled
4726 *
4727 * Performs potentially sleeping operations that must be done after the primary
4728 * plane is enabled, such as updating FBC and IPS. Note that this may be
4729 * called due to an explicit primary plane update, or due to an implicit
4730 * re-enable that is caused when a sprite plane is updated to no longer
4731 * completely hide the primary plane.
4732 */
4733static void
4734intel_post_enable_primary(struct drm_crtc *crtc)
a5c4d7bc
VS
4735{
4736 struct drm_device *dev = crtc->dev;
87d4300a 4737 struct drm_i915_private *dev_priv = dev->dev_private;
a5c4d7bc
VS
4738 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4739 int pipe = intel_crtc->pipe;
a5c4d7bc 4740
87d4300a
ML
4741 /*
4742 * BDW signals flip done immediately if the plane
4743 * is disabled, even if the plane enable is already
4744 * armed to occur at the next vblank :(
4745 */
4746 if (IS_BROADWELL(dev))
4747 intel_wait_for_vblank(dev, pipe);
a5c4d7bc 4748
87d4300a
ML
4749 /*
4750 * FIXME IPS should be fine as long as one plane is
4751 * enabled, but in practice it seems to have problems
4752 * when going from primary only to sprite only and vice
4753 * versa.
4754 */
a5c4d7bc
VS
4755 hsw_enable_ips(intel_crtc);
4756
4757 mutex_lock(&dev->struct_mutex);
7ff0ebcc 4758 intel_fbc_update(dev);
a5c4d7bc 4759 mutex_unlock(&dev->struct_mutex);
f99d7069
DV
4760
4761 /*
87d4300a
ML
4762 * Gen2 reports pipe underruns whenever all planes are disabled.
4763 * So don't enable underrun reporting before at least some planes
4764 * are enabled.
4765 * FIXME: Need to fix the logic to work when we turn off all planes
4766 * but leave the pipe running.
f99d7069 4767 */
87d4300a
ML
4768 if (IS_GEN2(dev))
4769 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4770
4771 /* Underruns don't raise interrupts, so check manually. */
4772 if (HAS_GMCH_DISPLAY(dev))
4773 i9xx_check_fifo_underruns(dev_priv);
a5c4d7bc
VS
4774}
4775
87d4300a
ML
4776/**
4777 * intel_pre_disable_primary - Perform operations before disabling primary plane
4778 * @crtc: the CRTC whose primary plane is to be disabled
4779 *
4780 * Performs potentially sleeping operations that must be done before the
4781 * primary plane is disabled, such as updating FBC and IPS. Note that this may
4782 * be called due to an explicit primary plane update, or due to an implicit
4783 * disable that is caused when a sprite plane completely hides the primary
4784 * plane.
4785 */
4786static void
4787intel_pre_disable_primary(struct drm_crtc *crtc)
a5c4d7bc
VS
4788{
4789 struct drm_device *dev = crtc->dev;
4790 struct drm_i915_private *dev_priv = dev->dev_private;
4791 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4792 int pipe = intel_crtc->pipe;
a5c4d7bc 4793
87d4300a
ML
4794 /*
4795 * Gen2 reports pipe underruns whenever all planes are disabled.
4796 * So diasble underrun reporting before all the planes get disabled.
4797 * FIXME: Need to fix the logic to work when we turn off all planes
4798 * but leave the pipe running.
4799 */
4800 if (IS_GEN2(dev))
4801 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
a5c4d7bc 4802
87d4300a
ML
4803 /*
4804 * Vblank time updates from the shadow to live plane control register
4805 * are blocked if the memory self-refresh mode is active at that
4806 * moment. So to make sure the plane gets truly disabled, disable
4807 * first the self-refresh mode. The self-refresh enable bit in turn
4808 * will be checked/applied by the HW only at the next frame start
4809 * event which is after the vblank start event, so we need to have a
4810 * wait-for-vblank between disabling the plane and the pipe.
4811 */
4812 if (HAS_GMCH_DISPLAY(dev))
4813 intel_set_memory_cxsr(dev_priv, false);
4814
4815 mutex_lock(&dev->struct_mutex);
e35fef21 4816 if (dev_priv->fbc.crtc == intel_crtc)
7ff0ebcc 4817 intel_fbc_disable(dev);
87d4300a 4818 mutex_unlock(&dev->struct_mutex);
a5c4d7bc 4819
87d4300a
ML
4820 /*
4821 * FIXME IPS should be fine as long as one plane is
4822 * enabled, but in practice it seems to have problems
4823 * when going from primary only to sprite only and vice
4824 * versa.
4825 */
a5c4d7bc 4826 hsw_disable_ips(intel_crtc);
87d4300a
ML
4827}
4828
4829static void intel_crtc_enable_planes(struct drm_crtc *crtc)
4830{
87d4300a
ML
4831 intel_enable_primary_hw_plane(crtc->primary, crtc);
4832 intel_enable_sprite_planes(crtc);
4833 intel_crtc_update_cursor(crtc, true);
87d4300a
ML
4834
4835 intel_post_enable_primary(crtc);
4836}
4837
4838static void intel_crtc_disable_planes(struct drm_crtc *crtc)
4839{
4840 struct drm_device *dev = crtc->dev;
4841 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4842 struct intel_plane *intel_plane;
4843 int pipe = intel_crtc->pipe;
4844
4845 intel_crtc_wait_for_pending_flips(crtc);
4846
4847 intel_pre_disable_primary(crtc);
a5c4d7bc 4848
7cac945f 4849 intel_crtc_dpms_overlay_disable(intel_crtc);
27321ae8
ML
4850 for_each_intel_plane(dev, intel_plane) {
4851 if (intel_plane->pipe == pipe) {
4852 struct drm_crtc *from = intel_plane->base.crtc;
4853
4854 intel_plane->disable_plane(&intel_plane->base,
4855 from ?: crtc, true);
4856 }
4857 }
f98551ae 4858
f99d7069
DV
4859 /*
4860 * FIXME: Once we grow proper nuclear flip support out of this we need
4861 * to compute the mask of flip planes precisely. For the time being
4862 * consider this a flip to a NULL plane.
4863 */
4864 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
a5c4d7bc
VS
4865}
4866
f67a559d
JB
4867static void ironlake_crtc_enable(struct drm_crtc *crtc)
4868{
4869 struct drm_device *dev = crtc->dev;
4870 struct drm_i915_private *dev_priv = dev->dev_private;
4871 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 4872 struct intel_encoder *encoder;
f67a559d 4873 int pipe = intel_crtc->pipe;
f67a559d 4874
83d65738 4875 WARN_ON(!crtc->state->enable);
08a48469 4876
f67a559d
JB
4877 if (intel_crtc->active)
4878 return;
4879
6e3c9717 4880 if (intel_crtc->config->has_pch_encoder)
b14b1055
DV
4881 intel_prepare_shared_dpll(intel_crtc);
4882
6e3c9717 4883 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 4884 intel_dp_set_m_n(intel_crtc, M1_N1);
29407aab
DV
4885
4886 intel_set_pipe_timings(intel_crtc);
4887
6e3c9717 4888 if (intel_crtc->config->has_pch_encoder) {
29407aab 4889 intel_cpu_transcoder_set_m_n(intel_crtc,
6e3c9717 4890 &intel_crtc->config->fdi_m_n, NULL);
29407aab
DV
4891 }
4892
4893 ironlake_set_pipeconf(crtc);
4894
f67a559d 4895 intel_crtc->active = true;
8664281b 4896
a72e4c9f
DV
4897 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4898 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
8664281b 4899
f6736a1a 4900 for_each_encoder_on_crtc(dev, crtc, encoder)
952735ee
DV
4901 if (encoder->pre_enable)
4902 encoder->pre_enable(encoder);
f67a559d 4903
6e3c9717 4904 if (intel_crtc->config->has_pch_encoder) {
fff367c7
DV
4905 /* Note: FDI PLL enabling _must_ be done before we enable the
4906 * cpu pipes, hence this is separate from all the other fdi/pch
4907 * enabling. */
88cefb6c 4908 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV
4909 } else {
4910 assert_fdi_tx_disabled(dev_priv, pipe);
4911 assert_fdi_rx_disabled(dev_priv, pipe);
4912 }
f67a559d 4913
b074cec8 4914 ironlake_pfit_enable(intel_crtc);
f67a559d 4915
9c54c0dd
JB
4916 /*
4917 * On ILK+ LUT must be loaded before the pipe is running but with
4918 * clocks enabled
4919 */
4920 intel_crtc_load_lut(crtc);
4921
f37fcc2a 4922 intel_update_watermarks(crtc);
e1fdc473 4923 intel_enable_pipe(intel_crtc);
f67a559d 4924
6e3c9717 4925 if (intel_crtc->config->has_pch_encoder)
f67a559d 4926 ironlake_pch_enable(crtc);
c98e9dcf 4927
f9b61ff6
DV
4928 assert_vblank_disabled(crtc);
4929 drm_crtc_vblank_on(crtc);
4930
fa5c73b1
DV
4931 for_each_encoder_on_crtc(dev, crtc, encoder)
4932 encoder->enable(encoder);
61b77ddd
DV
4933
4934 if (HAS_PCH_CPT(dev))
a1520318 4935 cpt_verify_modeset(dev, intel_crtc->pipe);
6be4a607
JB
4936}
4937
42db64ef
PZ
4938/* IPS only exists on ULT machines and is tied to pipe A. */
4939static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4940{
f5adf94e 4941 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
42db64ef
PZ
4942}
4943
e4916946
PZ
4944/*
4945 * This implements the workaround described in the "notes" section of the mode
4946 * set sequence documentation. When going from no pipes or single pipe to
4947 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4948 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4949 */
4950static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4951{
4952 struct drm_device *dev = crtc->base.dev;
4953 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4954
4955 /* We want to get the other_active_crtc only if there's only 1 other
4956 * active crtc. */
d3fcc808 4957 for_each_intel_crtc(dev, crtc_it) {
e4916946
PZ
4958 if (!crtc_it->active || crtc_it == crtc)
4959 continue;
4960
4961 if (other_active_crtc)
4962 return;
4963
4964 other_active_crtc = crtc_it;
4965 }
4966 if (!other_active_crtc)
4967 return;
4968
4969 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4970 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4971}
4972
4f771f10
PZ
4973static void haswell_crtc_enable(struct drm_crtc *crtc)
4974{
4975 struct drm_device *dev = crtc->dev;
4976 struct drm_i915_private *dev_priv = dev->dev_private;
4977 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4978 struct intel_encoder *encoder;
4979 int pipe = intel_crtc->pipe;
4f771f10 4980
83d65738 4981 WARN_ON(!crtc->state->enable);
4f771f10
PZ
4982
4983 if (intel_crtc->active)
4984 return;
4985
df8ad70c
DV
4986 if (intel_crtc_to_shared_dpll(intel_crtc))
4987 intel_enable_shared_dpll(intel_crtc);
4988
6e3c9717 4989 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 4990 intel_dp_set_m_n(intel_crtc, M1_N1);
229fca97
DV
4991
4992 intel_set_pipe_timings(intel_crtc);
4993
6e3c9717
ACO
4994 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4995 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4996 intel_crtc->config->pixel_multiplier - 1);
ebb69c95
CT
4997 }
4998
6e3c9717 4999 if (intel_crtc->config->has_pch_encoder) {
229fca97 5000 intel_cpu_transcoder_set_m_n(intel_crtc,
6e3c9717 5001 &intel_crtc->config->fdi_m_n, NULL);
229fca97
DV
5002 }
5003
5004 haswell_set_pipeconf(crtc);
5005
5006 intel_set_pipe_csc(crtc);
5007
4f771f10 5008 intel_crtc->active = true;
8664281b 5009
a72e4c9f 5010 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4f771f10
PZ
5011 for_each_encoder_on_crtc(dev, crtc, encoder)
5012 if (encoder->pre_enable)
5013 encoder->pre_enable(encoder);
5014
6e3c9717 5015 if (intel_crtc->config->has_pch_encoder) {
a72e4c9f
DV
5016 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5017 true);
4fe9467d
ID
5018 dev_priv->display.fdi_link_train(crtc);
5019 }
5020
1f544388 5021 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 5022
ff6d9f55 5023 if (INTEL_INFO(dev)->gen == 9)
a1b2278e 5024 skylake_pfit_update(intel_crtc, 1);
ff6d9f55 5025 else if (INTEL_INFO(dev)->gen < 9)
bd2e244f 5026 ironlake_pfit_enable(intel_crtc);
ff6d9f55
JB
5027 else
5028 MISSING_CASE(INTEL_INFO(dev)->gen);
4f771f10
PZ
5029
5030 /*
5031 * On ILK+ LUT must be loaded before the pipe is running but with
5032 * clocks enabled
5033 */
5034 intel_crtc_load_lut(crtc);
5035
1f544388 5036 intel_ddi_set_pipe_settings(crtc);
8228c251 5037 intel_ddi_enable_transcoder_func(crtc);
4f771f10 5038
f37fcc2a 5039 intel_update_watermarks(crtc);
e1fdc473 5040 intel_enable_pipe(intel_crtc);
42db64ef 5041
6e3c9717 5042 if (intel_crtc->config->has_pch_encoder)
1507e5bd 5043 lpt_pch_enable(crtc);
4f771f10 5044
6e3c9717 5045 if (intel_crtc->config->dp_encoder_is_mst)
0e32b39c
DA
5046 intel_ddi_set_vc_payload_alloc(crtc, true);
5047
f9b61ff6
DV
5048 assert_vblank_disabled(crtc);
5049 drm_crtc_vblank_on(crtc);
5050
8807e55b 5051 for_each_encoder_on_crtc(dev, crtc, encoder) {
4f771f10 5052 encoder->enable(encoder);
8807e55b
JN
5053 intel_opregion_notify_encoder(encoder, true);
5054 }
4f771f10 5055
e4916946
PZ
5056 /* If we change the relative order between pipe/planes enabling, we need
5057 * to change the workaround. */
5058 haswell_mode_set_planes_workaround(intel_crtc);
4f771f10
PZ
5059}
5060
3f8dce3a
DV
5061static void ironlake_pfit_disable(struct intel_crtc *crtc)
5062{
5063 struct drm_device *dev = crtc->base.dev;
5064 struct drm_i915_private *dev_priv = dev->dev_private;
5065 int pipe = crtc->pipe;
5066
5067 /* To avoid upsetting the power well on haswell only disable the pfit if
5068 * it's in use. The hw state code will make sure we get this right. */
6e3c9717 5069 if (crtc->config->pch_pfit.enabled) {
3f8dce3a
DV
5070 I915_WRITE(PF_CTL(pipe), 0);
5071 I915_WRITE(PF_WIN_POS(pipe), 0);
5072 I915_WRITE(PF_WIN_SZ(pipe), 0);
5073 }
5074}
5075
6be4a607
JB
5076static void ironlake_crtc_disable(struct drm_crtc *crtc)
5077{
5078 struct drm_device *dev = crtc->dev;
5079 struct drm_i915_private *dev_priv = dev->dev_private;
5080 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 5081 struct intel_encoder *encoder;
6be4a607 5082 int pipe = intel_crtc->pipe;
5eddb70b 5083 u32 reg, temp;
b52eb4dc 5084
f7abfe8b
CW
5085 if (!intel_crtc->active)
5086 return;
5087
ea9d758d
DV
5088 for_each_encoder_on_crtc(dev, crtc, encoder)
5089 encoder->disable(encoder);
5090
f9b61ff6
DV
5091 drm_crtc_vblank_off(crtc);
5092 assert_vblank_disabled(crtc);
5093
6e3c9717 5094 if (intel_crtc->config->has_pch_encoder)
a72e4c9f 5095 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
d925c59a 5096
575f7ab7 5097 intel_disable_pipe(intel_crtc);
32f9d658 5098
3f8dce3a 5099 ironlake_pfit_disable(intel_crtc);
2c07245f 5100
5a74f70a
VS
5101 if (intel_crtc->config->has_pch_encoder)
5102 ironlake_fdi_disable(crtc);
5103
bf49ec8c
DV
5104 for_each_encoder_on_crtc(dev, crtc, encoder)
5105 if (encoder->post_disable)
5106 encoder->post_disable(encoder);
2c07245f 5107
6e3c9717 5108 if (intel_crtc->config->has_pch_encoder) {
d925c59a 5109 ironlake_disable_pch_transcoder(dev_priv, pipe);
6be4a607 5110
d925c59a
DV
5111 if (HAS_PCH_CPT(dev)) {
5112 /* disable TRANS_DP_CTL */
5113 reg = TRANS_DP_CTL(pipe);
5114 temp = I915_READ(reg);
5115 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5116 TRANS_DP_PORT_SEL_MASK);
5117 temp |= TRANS_DP_PORT_SEL_NONE;
5118 I915_WRITE(reg, temp);
5119
5120 /* disable DPLL_SEL */
5121 temp = I915_READ(PCH_DPLL_SEL);
11887397 5122 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
d925c59a 5123 I915_WRITE(PCH_DPLL_SEL, temp);
9db4a9c7 5124 }
e3421a18 5125
d925c59a 5126 /* disable PCH DPLL */
e72f9fbf 5127 intel_disable_shared_dpll(intel_crtc);
8db9d77b 5128
d925c59a
DV
5129 ironlake_fdi_pll_disable(intel_crtc);
5130 }
6b383a7f 5131
f7abfe8b 5132 intel_crtc->active = false;
46ba614c 5133 intel_update_watermarks(crtc);
d1ebd816
BW
5134
5135 mutex_lock(&dev->struct_mutex);
7ff0ebcc 5136 intel_fbc_update(dev);
d1ebd816 5137 mutex_unlock(&dev->struct_mutex);
6be4a607 5138}
1b3c7a47 5139
4f771f10 5140static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 5141{
4f771f10
PZ
5142 struct drm_device *dev = crtc->dev;
5143 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 5144 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10 5145 struct intel_encoder *encoder;
6e3c9717 5146 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
ee7b9f93 5147
4f771f10
PZ
5148 if (!intel_crtc->active)
5149 return;
5150
8807e55b
JN
5151 for_each_encoder_on_crtc(dev, crtc, encoder) {
5152 intel_opregion_notify_encoder(encoder, false);
4f771f10 5153 encoder->disable(encoder);
8807e55b 5154 }
4f771f10 5155
f9b61ff6
DV
5156 drm_crtc_vblank_off(crtc);
5157 assert_vblank_disabled(crtc);
5158
6e3c9717 5159 if (intel_crtc->config->has_pch_encoder)
a72e4c9f
DV
5160 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5161 false);
575f7ab7 5162 intel_disable_pipe(intel_crtc);
4f771f10 5163
6e3c9717 5164 if (intel_crtc->config->dp_encoder_is_mst)
a4bf214f
VS
5165 intel_ddi_set_vc_payload_alloc(crtc, false);
5166
ad80a810 5167 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 5168
ff6d9f55 5169 if (INTEL_INFO(dev)->gen == 9)
a1b2278e 5170 skylake_pfit_update(intel_crtc, 0);
ff6d9f55 5171 else if (INTEL_INFO(dev)->gen < 9)
bd2e244f 5172 ironlake_pfit_disable(intel_crtc);
ff6d9f55
JB
5173 else
5174 MISSING_CASE(INTEL_INFO(dev)->gen);
4f771f10 5175
1f544388 5176 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10 5177
6e3c9717 5178 if (intel_crtc->config->has_pch_encoder) {
ab4d966c 5179 lpt_disable_pch_transcoder(dev_priv);
1ad960f2 5180 intel_ddi_fdi_disable(crtc);
83616634 5181 }
4f771f10 5182
97b040aa
ID
5183 for_each_encoder_on_crtc(dev, crtc, encoder)
5184 if (encoder->post_disable)
5185 encoder->post_disable(encoder);
5186
4f771f10 5187 intel_crtc->active = false;
46ba614c 5188 intel_update_watermarks(crtc);
4f771f10
PZ
5189
5190 mutex_lock(&dev->struct_mutex);
7ff0ebcc 5191 intel_fbc_update(dev);
4f771f10 5192 mutex_unlock(&dev->struct_mutex);
df8ad70c
DV
5193
5194 if (intel_crtc_to_shared_dpll(intel_crtc))
5195 intel_disable_shared_dpll(intel_crtc);
4f771f10
PZ
5196}
5197
ee7b9f93
JB
5198static void ironlake_crtc_off(struct drm_crtc *crtc)
5199{
5200 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
e72f9fbf 5201 intel_put_shared_dpll(intel_crtc);
ee7b9f93
JB
5202}
5203
6441ab5f 5204
2dd24552
JB
5205static void i9xx_pfit_enable(struct intel_crtc *crtc)
5206{
5207 struct drm_device *dev = crtc->base.dev;
5208 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 5209 struct intel_crtc_state *pipe_config = crtc->config;
2dd24552 5210
681a8504 5211 if (!pipe_config->gmch_pfit.control)
2dd24552
JB
5212 return;
5213
2dd24552 5214 /*
c0b03411
DV
5215 * The panel fitter should only be adjusted whilst the pipe is disabled,
5216 * according to register description and PRM.
2dd24552 5217 */
c0b03411
DV
5218 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5219 assert_pipe_disabled(dev_priv, crtc->pipe);
2dd24552 5220
b074cec8
JB
5221 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5222 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5a80c45c
DV
5223
5224 /* Border color in case we don't scale up to the full screen. Black by
5225 * default, change to something else for debugging. */
5226 I915_WRITE(BCLRPAT(crtc->pipe), 0);
2dd24552
JB
5227}
5228
d05410f9
DA
5229static enum intel_display_power_domain port_to_power_domain(enum port port)
5230{
5231 switch (port) {
5232 case PORT_A:
5233 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
5234 case PORT_B:
5235 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
5236 case PORT_C:
5237 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
5238 case PORT_D:
5239 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
5240 default:
5241 WARN_ON_ONCE(1);
5242 return POWER_DOMAIN_PORT_OTHER;
5243 }
5244}
5245
77d22dca
ID
5246#define for_each_power_domain(domain, mask) \
5247 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
5248 if ((1 << (domain)) & (mask))
5249
319be8ae
ID
5250enum intel_display_power_domain
5251intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5252{
5253 struct drm_device *dev = intel_encoder->base.dev;
5254 struct intel_digital_port *intel_dig_port;
5255
5256 switch (intel_encoder->type) {
5257 case INTEL_OUTPUT_UNKNOWN:
5258 /* Only DDI platforms should ever use this output type */
5259 WARN_ON_ONCE(!HAS_DDI(dev));
5260 case INTEL_OUTPUT_DISPLAYPORT:
5261 case INTEL_OUTPUT_HDMI:
5262 case INTEL_OUTPUT_EDP:
5263 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
d05410f9 5264 return port_to_power_domain(intel_dig_port->port);
0e32b39c
DA
5265 case INTEL_OUTPUT_DP_MST:
5266 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5267 return port_to_power_domain(intel_dig_port->port);
319be8ae
ID
5268 case INTEL_OUTPUT_ANALOG:
5269 return POWER_DOMAIN_PORT_CRT;
5270 case INTEL_OUTPUT_DSI:
5271 return POWER_DOMAIN_PORT_DSI;
5272 default:
5273 return POWER_DOMAIN_PORT_OTHER;
5274 }
5275}
5276
5277static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
77d22dca 5278{
319be8ae
ID
5279 struct drm_device *dev = crtc->dev;
5280 struct intel_encoder *intel_encoder;
5281 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5282 enum pipe pipe = intel_crtc->pipe;
77d22dca
ID
5283 unsigned long mask;
5284 enum transcoder transcoder;
5285
5286 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
5287
5288 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5289 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
6e3c9717
ACO
5290 if (intel_crtc->config->pch_pfit.enabled ||
5291 intel_crtc->config->pch_pfit.force_thru)
77d22dca
ID
5292 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5293
319be8ae
ID
5294 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5295 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5296
77d22dca
ID
5297 return mask;
5298}
5299
679dacd4 5300static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
77d22dca 5301{
679dacd4 5302 struct drm_device *dev = state->dev;
77d22dca
ID
5303 struct drm_i915_private *dev_priv = dev->dev_private;
5304 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
5305 struct intel_crtc *crtc;
5306
5307 /*
5308 * First get all needed power domains, then put all unneeded, to avoid
5309 * any unnecessary toggling of the power wells.
5310 */
d3fcc808 5311 for_each_intel_crtc(dev, crtc) {
77d22dca
ID
5312 enum intel_display_power_domain domain;
5313
83d65738 5314 if (!crtc->base.state->enable)
77d22dca
ID
5315 continue;
5316
319be8ae 5317 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
77d22dca
ID
5318
5319 for_each_power_domain(domain, pipe_domains[crtc->pipe])
5320 intel_display_power_get(dev_priv, domain);
5321 }
5322
50f6e502 5323 if (dev_priv->display.modeset_global_resources)
679dacd4 5324 dev_priv->display.modeset_global_resources(state);
50f6e502 5325
d3fcc808 5326 for_each_intel_crtc(dev, crtc) {
77d22dca
ID
5327 enum intel_display_power_domain domain;
5328
5329 for_each_power_domain(domain, crtc->enabled_power_domains)
5330 intel_display_power_put(dev_priv, domain);
5331
5332 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
5333 }
5334
5335 intel_display_set_init_power(dev_priv, false);
5336}
5337
f8437dd1
VK
5338void broxton_set_cdclk(struct drm_device *dev, int frequency)
5339{
5340 struct drm_i915_private *dev_priv = dev->dev_private;
5341 uint32_t divider;
5342 uint32_t ratio;
5343 uint32_t current_freq;
5344 int ret;
5345
5346 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5347 switch (frequency) {
5348 case 144000:
5349 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5350 ratio = BXT_DE_PLL_RATIO(60);
5351 break;
5352 case 288000:
5353 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5354 ratio = BXT_DE_PLL_RATIO(60);
5355 break;
5356 case 384000:
5357 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5358 ratio = BXT_DE_PLL_RATIO(60);
5359 break;
5360 case 576000:
5361 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5362 ratio = BXT_DE_PLL_RATIO(60);
5363 break;
5364 case 624000:
5365 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5366 ratio = BXT_DE_PLL_RATIO(65);
5367 break;
5368 case 19200:
5369 /*
5370 * Bypass frequency with DE PLL disabled. Init ratio, divider
5371 * to suppress GCC warning.
5372 */
5373 ratio = 0;
5374 divider = 0;
5375 break;
5376 default:
5377 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5378
5379 return;
5380 }
5381
5382 mutex_lock(&dev_priv->rps.hw_lock);
5383 /* Inform power controller of upcoming frequency change */
5384 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5385 0x80000000);
5386 mutex_unlock(&dev_priv->rps.hw_lock);
5387
5388 if (ret) {
5389 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5390 ret, frequency);
5391 return;
5392 }
5393
5394 current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5395 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5396 current_freq = current_freq * 500 + 1000;
5397
5398 /*
5399 * DE PLL has to be disabled when
5400 * - setting to 19.2MHz (bypass, PLL isn't used)
5401 * - before setting to 624MHz (PLL needs toggling)
5402 * - before setting to any frequency from 624MHz (PLL needs toggling)
5403 */
5404 if (frequency == 19200 || frequency == 624000 ||
5405 current_freq == 624000) {
5406 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5407 /* Timeout 200us */
5408 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5409 1))
5410 DRM_ERROR("timout waiting for DE PLL unlock\n");
5411 }
5412
5413 if (frequency != 19200) {
5414 uint32_t val;
5415
5416 val = I915_READ(BXT_DE_PLL_CTL);
5417 val &= ~BXT_DE_PLL_RATIO_MASK;
5418 val |= ratio;
5419 I915_WRITE(BXT_DE_PLL_CTL, val);
5420
5421 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5422 /* Timeout 200us */
5423 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5424 DRM_ERROR("timeout waiting for DE PLL lock\n");
5425
5426 val = I915_READ(CDCLK_CTL);
5427 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5428 val |= divider;
5429 /*
5430 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5431 * enable otherwise.
5432 */
5433 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5434 if (frequency >= 500000)
5435 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5436
5437 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5438 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5439 val |= (frequency - 1000) / 500;
5440 I915_WRITE(CDCLK_CTL, val);
5441 }
5442
5443 mutex_lock(&dev_priv->rps.hw_lock);
5444 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5445 DIV_ROUND_UP(frequency, 25000));
5446 mutex_unlock(&dev_priv->rps.hw_lock);
5447
5448 if (ret) {
5449 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5450 ret, frequency);
5451 return;
5452 }
5453
5454 dev_priv->cdclk_freq = frequency;
5455}
5456
5457void broxton_init_cdclk(struct drm_device *dev)
5458{
5459 struct drm_i915_private *dev_priv = dev->dev_private;
5460 uint32_t val;
5461
5462 /*
5463 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5464 * or else the reset will hang because there is no PCH to respond.
5465 * Move the handshake programming to initialization sequence.
5466 * Previously was left up to BIOS.
5467 */
5468 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5469 val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5470 I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5471
5472 /* Enable PG1 for cdclk */
5473 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5474
5475 /* check if cd clock is enabled */
5476 if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5477 DRM_DEBUG_KMS("Display already initialized\n");
5478 return;
5479 }
5480
5481 /*
5482 * FIXME:
5483 * - The initial CDCLK needs to be read from VBT.
5484 * Need to make this change after VBT has changes for BXT.
5485 * - check if setting the max (or any) cdclk freq is really necessary
5486 * here, it belongs to modeset time
5487 */
5488 broxton_set_cdclk(dev, 624000);
5489
5490 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
22e02c0b
VS
5491 POSTING_READ(DBUF_CTL);
5492
f8437dd1
VK
5493 udelay(10);
5494
5495 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5496 DRM_ERROR("DBuf power enable timeout!\n");
5497}
5498
5499void broxton_uninit_cdclk(struct drm_device *dev)
5500{
5501 struct drm_i915_private *dev_priv = dev->dev_private;
5502
5503 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
22e02c0b
VS
5504 POSTING_READ(DBUF_CTL);
5505
f8437dd1
VK
5506 udelay(10);
5507
5508 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5509 DRM_ERROR("DBuf power disable timeout!\n");
5510
5511 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5512 broxton_set_cdclk(dev, 19200);
5513
5514 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5515}
5516
5d96d8af
DL
5517static const struct skl_cdclk_entry {
5518 unsigned int freq;
5519 unsigned int vco;
5520} skl_cdclk_frequencies[] = {
5521 { .freq = 308570, .vco = 8640 },
5522 { .freq = 337500, .vco = 8100 },
5523 { .freq = 432000, .vco = 8640 },
5524 { .freq = 450000, .vco = 8100 },
5525 { .freq = 540000, .vco = 8100 },
5526 { .freq = 617140, .vco = 8640 },
5527 { .freq = 675000, .vco = 8100 },
5528};
5529
5530static unsigned int skl_cdclk_decimal(unsigned int freq)
5531{
5532 return (freq - 1000) / 500;
5533}
5534
5535static unsigned int skl_cdclk_get_vco(unsigned int freq)
5536{
5537 unsigned int i;
5538
5539 for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5540 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5541
5542 if (e->freq == freq)
5543 return e->vco;
5544 }
5545
5546 return 8100;
5547}
5548
5549static void
5550skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5551{
5552 unsigned int min_freq;
5553 u32 val;
5554
5555 /* select the minimum CDCLK before enabling DPLL 0 */
5556 val = I915_READ(CDCLK_CTL);
5557 val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5558 val |= CDCLK_FREQ_337_308;
5559
5560 if (required_vco == 8640)
5561 min_freq = 308570;
5562 else
5563 min_freq = 337500;
5564
5565 val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5566
5567 I915_WRITE(CDCLK_CTL, val);
5568 POSTING_READ(CDCLK_CTL);
5569
5570 /*
5571 * We always enable DPLL0 with the lowest link rate possible, but still
5572 * taking into account the VCO required to operate the eDP panel at the
5573 * desired frequency. The usual DP link rates operate with a VCO of
5574 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5575 * The modeset code is responsible for the selection of the exact link
5576 * rate later on, with the constraint of choosing a frequency that
5577 * works with required_vco.
5578 */
5579 val = I915_READ(DPLL_CTRL1);
5580
5581 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5582 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5583 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5584 if (required_vco == 8640)
5585 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5586 SKL_DPLL0);
5587 else
5588 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5589 SKL_DPLL0);
5590
5591 I915_WRITE(DPLL_CTRL1, val);
5592 POSTING_READ(DPLL_CTRL1);
5593
5594 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5595
5596 if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5597 DRM_ERROR("DPLL0 not locked\n");
5598}
5599
5600static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5601{
5602 int ret;
5603 u32 val;
5604
5605 /* inform PCU we want to change CDCLK */
5606 val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5607 mutex_lock(&dev_priv->rps.hw_lock);
5608 ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5609 mutex_unlock(&dev_priv->rps.hw_lock);
5610
5611 return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5612}
5613
5614static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5615{
5616 unsigned int i;
5617
5618 for (i = 0; i < 15; i++) {
5619 if (skl_cdclk_pcu_ready(dev_priv))
5620 return true;
5621 udelay(10);
5622 }
5623
5624 return false;
5625}
5626
5627static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5628{
5629 u32 freq_select, pcu_ack;
5630
5631 DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5632
5633 if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5634 DRM_ERROR("failed to inform PCU about cdclk change\n");
5635 return;
5636 }
5637
5638 /* set CDCLK_CTL */
5639 switch(freq) {
5640 case 450000:
5641 case 432000:
5642 freq_select = CDCLK_FREQ_450_432;
5643 pcu_ack = 1;
5644 break;
5645 case 540000:
5646 freq_select = CDCLK_FREQ_540;
5647 pcu_ack = 2;
5648 break;
5649 case 308570:
5650 case 337500:
5651 default:
5652 freq_select = CDCLK_FREQ_337_308;
5653 pcu_ack = 0;
5654 break;
5655 case 617140:
5656 case 675000:
5657 freq_select = CDCLK_FREQ_675_617;
5658 pcu_ack = 3;
5659 break;
5660 }
5661
5662 I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5663 POSTING_READ(CDCLK_CTL);
5664
5665 /* inform PCU of the change */
5666 mutex_lock(&dev_priv->rps.hw_lock);
5667 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5668 mutex_unlock(&dev_priv->rps.hw_lock);
5669}
5670
5671void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5672{
5673 /* disable DBUF power */
5674 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5675 POSTING_READ(DBUF_CTL);
5676
5677 udelay(10);
5678
5679 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5680 DRM_ERROR("DBuf power disable timeout\n");
5681
5682 /* disable DPLL0 */
5683 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5684 if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5685 DRM_ERROR("Couldn't disable DPLL0\n");
5686
5687 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5688}
5689
5690void skl_init_cdclk(struct drm_i915_private *dev_priv)
5691{
5692 u32 val;
5693 unsigned int required_vco;
5694
5695 /* enable PCH reset handshake */
5696 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5697 I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
5698
5699 /* enable PG1 and Misc I/O */
5700 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5701
5702 /* DPLL0 already enabed !? */
5703 if (I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE) {
5704 DRM_DEBUG_DRIVER("DPLL0 already running\n");
5705 return;
5706 }
5707
5708 /* enable DPLL0 */
5709 required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5710 skl_dpll0_enable(dev_priv, required_vco);
5711
5712 /* set CDCLK to the frequency the BIOS chose */
5713 skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5714
5715 /* enable DBUF power */
5716 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5717 POSTING_READ(DBUF_CTL);
5718
5719 udelay(10);
5720
5721 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5722 DRM_ERROR("DBuf power enable timeout\n");
5723}
5724
dfcab17e 5725/* returns HPLL frequency in kHz */
f8bf63fd 5726static int valleyview_get_vco(struct drm_i915_private *dev_priv)
30a970c6 5727{
586f49dc 5728 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
30a970c6 5729
586f49dc 5730 /* Obtain SKU information */
a580516d 5731 mutex_lock(&dev_priv->sb_lock);
586f49dc
JB
5732 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
5733 CCK_FUSE_HPLL_FREQ_MASK;
a580516d 5734 mutex_unlock(&dev_priv->sb_lock);
30a970c6 5735
dfcab17e 5736 return vco_freq[hpll_freq] * 1000;
30a970c6
JB
5737}
5738
f8bf63fd
VS
5739static void vlv_update_cdclk(struct drm_device *dev)
5740{
5741 struct drm_i915_private *dev_priv = dev->dev_private;
5742
164dfd28 5743 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
43dc52c3 5744 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
164dfd28 5745 dev_priv->cdclk_freq);
f8bf63fd
VS
5746
5747 /*
5748 * Program the gmbus_freq based on the cdclk frequency.
5749 * BSpec erroneously claims we should aim for 4MHz, but
5750 * in fact 1MHz is the correct frequency.
5751 */
164dfd28 5752 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
f8bf63fd
VS
5753}
5754
30a970c6
JB
5755/* Adjust CDclk dividers to allow high res or save power if possible */
5756static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5757{
5758 struct drm_i915_private *dev_priv = dev->dev_private;
5759 u32 val, cmd;
5760
164dfd28
VK
5761 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5762 != dev_priv->cdclk_freq);
d60c4473 5763
dfcab17e 5764 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
30a970c6 5765 cmd = 2;
dfcab17e 5766 else if (cdclk == 266667)
30a970c6
JB
5767 cmd = 1;
5768 else
5769 cmd = 0;
5770
5771 mutex_lock(&dev_priv->rps.hw_lock);
5772 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5773 val &= ~DSPFREQGUAR_MASK;
5774 val |= (cmd << DSPFREQGUAR_SHIFT);
5775 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5776 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5777 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5778 50)) {
5779 DRM_ERROR("timed out waiting for CDclk change\n");
5780 }
5781 mutex_unlock(&dev_priv->rps.hw_lock);
5782
54433e91
VS
5783 mutex_lock(&dev_priv->sb_lock);
5784
dfcab17e 5785 if (cdclk == 400000) {
6bcda4f0 5786 u32 divider;
30a970c6 5787
6bcda4f0 5788 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
30a970c6 5789
30a970c6
JB
5790 /* adjust cdclk divider */
5791 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
9cf33db5 5792 val &= ~DISPLAY_FREQUENCY_VALUES;
30a970c6
JB
5793 val |= divider;
5794 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
a877e801
VS
5795
5796 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5797 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5798 50))
5799 DRM_ERROR("timed out waiting for CDclk change\n");
30a970c6
JB
5800 }
5801
30a970c6
JB
5802 /* adjust self-refresh exit latency value */
5803 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5804 val &= ~0x7f;
5805
5806 /*
5807 * For high bandwidth configs, we set a higher latency in the bunit
5808 * so that the core display fetch happens in time to avoid underruns.
5809 */
dfcab17e 5810 if (cdclk == 400000)
30a970c6
JB
5811 val |= 4500 / 250; /* 4.5 usec */
5812 else
5813 val |= 3000 / 250; /* 3.0 usec */
5814 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
54433e91 5815
a580516d 5816 mutex_unlock(&dev_priv->sb_lock);
30a970c6 5817
f8bf63fd 5818 vlv_update_cdclk(dev);
30a970c6
JB
5819}
5820
383c5a6a
VS
5821static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5822{
5823 struct drm_i915_private *dev_priv = dev->dev_private;
5824 u32 val, cmd;
5825
164dfd28
VK
5826 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5827 != dev_priv->cdclk_freq);
383c5a6a
VS
5828
5829 switch (cdclk) {
383c5a6a
VS
5830 case 333333:
5831 case 320000:
383c5a6a 5832 case 266667:
383c5a6a 5833 case 200000:
383c5a6a
VS
5834 break;
5835 default:
5f77eeb0 5836 MISSING_CASE(cdclk);
383c5a6a
VS
5837 return;
5838 }
5839
9d0d3fda
VS
5840 /*
5841 * Specs are full of misinformation, but testing on actual
5842 * hardware has shown that we just need to write the desired
5843 * CCK divider into the Punit register.
5844 */
5845 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5846
383c5a6a
VS
5847 mutex_lock(&dev_priv->rps.hw_lock);
5848 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5849 val &= ~DSPFREQGUAR_MASK_CHV;
5850 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5851 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5852 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5853 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5854 50)) {
5855 DRM_ERROR("timed out waiting for CDclk change\n");
5856 }
5857 mutex_unlock(&dev_priv->rps.hw_lock);
5858
5859 vlv_update_cdclk(dev);
5860}
5861
30a970c6
JB
5862static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5863 int max_pixclk)
5864{
6bcda4f0 5865 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
6cca3195 5866 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
29dc7ef3 5867
30a970c6
JB
5868 /*
5869 * Really only a few cases to deal with, as only 4 CDclks are supported:
5870 * 200MHz
5871 * 267MHz
29dc7ef3 5872 * 320/333MHz (depends on HPLL freq)
6cca3195
VS
5873 * 400MHz (VLV only)
5874 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5875 * of the lower bin and adjust if needed.
e37c67a1
VS
5876 *
5877 * We seem to get an unstable or solid color picture at 200MHz.
5878 * Not sure what's wrong. For now use 200MHz only when all pipes
5879 * are off.
30a970c6 5880 */
6cca3195
VS
5881 if (!IS_CHERRYVIEW(dev_priv) &&
5882 max_pixclk > freq_320*limit/100)
dfcab17e 5883 return 400000;
6cca3195 5884 else if (max_pixclk > 266667*limit/100)
29dc7ef3 5885 return freq_320;
e37c67a1 5886 else if (max_pixclk > 0)
dfcab17e 5887 return 266667;
e37c67a1
VS
5888 else
5889 return 200000;
30a970c6
JB
5890}
5891
f8437dd1
VK
5892static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5893 int max_pixclk)
5894{
5895 /*
5896 * FIXME:
5897 * - remove the guardband, it's not needed on BXT
5898 * - set 19.2MHz bypass frequency if there are no active pipes
5899 */
5900 if (max_pixclk > 576000*9/10)
5901 return 624000;
5902 else if (max_pixclk > 384000*9/10)
5903 return 576000;
5904 else if (max_pixclk > 288000*9/10)
5905 return 384000;
5906 else if (max_pixclk > 144000*9/10)
5907 return 288000;
5908 else
5909 return 144000;
5910}
5911
a821fc46
ACO
5912/* Compute the max pixel clock for new configuration. Uses atomic state if
5913 * that's non-NULL, look at current state otherwise. */
5914static int intel_mode_max_pixclk(struct drm_device *dev,
5915 struct drm_atomic_state *state)
30a970c6 5916{
30a970c6 5917 struct intel_crtc *intel_crtc;
304603f4 5918 struct intel_crtc_state *crtc_state;
30a970c6
JB
5919 int max_pixclk = 0;
5920
d3fcc808 5921 for_each_intel_crtc(dev, intel_crtc) {
a821fc46
ACO
5922 if (state)
5923 crtc_state =
5924 intel_atomic_get_crtc_state(state, intel_crtc);
5925 else
5926 crtc_state = intel_crtc->config;
304603f4
ACO
5927 if (IS_ERR(crtc_state))
5928 return PTR_ERR(crtc_state);
5929
5930 if (!crtc_state->base.enable)
5931 continue;
5932
5933 max_pixclk = max(max_pixclk,
5934 crtc_state->base.adjusted_mode.crtc_clock);
30a970c6
JB
5935 }
5936
5937 return max_pixclk;
5938}
5939
0a9ab303 5940static int valleyview_modeset_global_pipes(struct drm_atomic_state *state)
30a970c6 5941{
304603f4 5942 struct drm_i915_private *dev_priv = to_i915(state->dev);
0a9ab303
ACO
5943 struct drm_crtc *crtc;
5944 struct drm_crtc_state *crtc_state;
a821fc46 5945 int max_pixclk = intel_mode_max_pixclk(state->dev, state);
0a9ab303 5946 int cdclk, i;
30a970c6 5947
304603f4
ACO
5948 if (max_pixclk < 0)
5949 return max_pixclk;
30a970c6 5950
f8437dd1
VK
5951 if (IS_VALLEYVIEW(dev_priv))
5952 cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
5953 else
5954 cdclk = broxton_calc_cdclk(dev_priv, max_pixclk);
5955
5956 if (cdclk == dev_priv->cdclk_freq)
304603f4 5957 return 0;
30a970c6 5958
0a9ab303
ACO
5959 /* add all active pipes to the state */
5960 for_each_crtc(state->dev, crtc) {
5961 if (!crtc->state->enable)
5962 continue;
5963
5964 crtc_state = drm_atomic_get_crtc_state(state, crtc);
5965 if (IS_ERR(crtc_state))
5966 return PTR_ERR(crtc_state);
5967 }
5968
2f2d7aa1 5969 /* disable/enable all currently active pipes while we change cdclk */
0a9ab303
ACO
5970 for_each_crtc_in_state(state, crtc, crtc_state, i)
5971 if (crtc_state->enable)
5972 crtc_state->mode_changed = true;
304603f4
ACO
5973
5974 return 0;
30a970c6
JB
5975}
5976
1e69cd74
VS
5977static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5978{
5979 unsigned int credits, default_credits;
5980
5981 if (IS_CHERRYVIEW(dev_priv))
5982 default_credits = PFI_CREDIT(12);
5983 else
5984 default_credits = PFI_CREDIT(8);
5985
164dfd28 5986 if (DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
1e69cd74
VS
5987 /* CHV suggested value is 31 or 63 */
5988 if (IS_CHERRYVIEW(dev_priv))
5989 credits = PFI_CREDIT_31;
5990 else
5991 credits = PFI_CREDIT(15);
5992 } else {
5993 credits = default_credits;
5994 }
5995
5996 /*
5997 * WA - write default credits before re-programming
5998 * FIXME: should we also set the resend bit here?
5999 */
6000 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6001 default_credits);
6002
6003 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6004 credits | PFI_CREDIT_RESEND);
6005
6006 /*
6007 * FIXME is this guaranteed to clear
6008 * immediately or should we poll for it?
6009 */
6010 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6011}
6012
a821fc46 6013static void valleyview_modeset_global_resources(struct drm_atomic_state *old_state)
30a970c6 6014{
a821fc46 6015 struct drm_device *dev = old_state->dev;
30a970c6 6016 struct drm_i915_private *dev_priv = dev->dev_private;
a821fc46 6017 int max_pixclk = intel_mode_max_pixclk(dev, NULL);
304603f4
ACO
6018 int req_cdclk;
6019
a821fc46
ACO
6020 /* The path in intel_mode_max_pixclk() with a NULL atomic state should
6021 * never fail. */
304603f4
ACO
6022 if (WARN_ON(max_pixclk < 0))
6023 return;
30a970c6 6024
304603f4 6025 req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
30a970c6 6026
164dfd28 6027 if (req_cdclk != dev_priv->cdclk_freq) {
738c05c0
ID
6028 /*
6029 * FIXME: We can end up here with all power domains off, yet
6030 * with a CDCLK frequency other than the minimum. To account
6031 * for this take the PIPE-A power domain, which covers the HW
6032 * blocks needed for the following programming. This can be
6033 * removed once it's guaranteed that we get here either with
6034 * the minimum CDCLK set, or the required power domains
6035 * enabled.
6036 */
6037 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6038
383c5a6a
VS
6039 if (IS_CHERRYVIEW(dev))
6040 cherryview_set_cdclk(dev, req_cdclk);
6041 else
6042 valleyview_set_cdclk(dev, req_cdclk);
738c05c0 6043
1e69cd74
VS
6044 vlv_program_pfi_credits(dev_priv);
6045
738c05c0 6046 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
383c5a6a 6047 }
30a970c6
JB
6048}
6049
89b667f8
JB
6050static void valleyview_crtc_enable(struct drm_crtc *crtc)
6051{
6052 struct drm_device *dev = crtc->dev;
a72e4c9f 6053 struct drm_i915_private *dev_priv = to_i915(dev);
89b667f8
JB
6054 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6055 struct intel_encoder *encoder;
6056 int pipe = intel_crtc->pipe;
23538ef1 6057 bool is_dsi;
89b667f8 6058
83d65738 6059 WARN_ON(!crtc->state->enable);
89b667f8
JB
6060
6061 if (intel_crtc->active)
6062 return;
6063
409ee761 6064 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
8525a235 6065
1ae0d137
VS
6066 if (!is_dsi) {
6067 if (IS_CHERRYVIEW(dev))
6e3c9717 6068 chv_prepare_pll(intel_crtc, intel_crtc->config);
1ae0d137 6069 else
6e3c9717 6070 vlv_prepare_pll(intel_crtc, intel_crtc->config);
1ae0d137 6071 }
5b18e57c 6072
6e3c9717 6073 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 6074 intel_dp_set_m_n(intel_crtc, M1_N1);
5b18e57c
DV
6075
6076 intel_set_pipe_timings(intel_crtc);
6077
c14b0485
VS
6078 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6079 struct drm_i915_private *dev_priv = dev->dev_private;
6080
6081 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6082 I915_WRITE(CHV_CANVAS(pipe), 0);
6083 }
6084
5b18e57c
DV
6085 i9xx_set_pipeconf(intel_crtc);
6086
89b667f8 6087 intel_crtc->active = true;
89b667f8 6088
a72e4c9f 6089 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 6090
89b667f8
JB
6091 for_each_encoder_on_crtc(dev, crtc, encoder)
6092 if (encoder->pre_pll_enable)
6093 encoder->pre_pll_enable(encoder);
6094
9d556c99
CML
6095 if (!is_dsi) {
6096 if (IS_CHERRYVIEW(dev))
6e3c9717 6097 chv_enable_pll(intel_crtc, intel_crtc->config);
9d556c99 6098 else
6e3c9717 6099 vlv_enable_pll(intel_crtc, intel_crtc->config);
9d556c99 6100 }
89b667f8
JB
6101
6102 for_each_encoder_on_crtc(dev, crtc, encoder)
6103 if (encoder->pre_enable)
6104 encoder->pre_enable(encoder);
6105
2dd24552
JB
6106 i9xx_pfit_enable(intel_crtc);
6107
63cbb074
VS
6108 intel_crtc_load_lut(crtc);
6109
f37fcc2a 6110 intel_update_watermarks(crtc);
e1fdc473 6111 intel_enable_pipe(intel_crtc);
be6a6f8e 6112
4b3a9526
VS
6113 assert_vblank_disabled(crtc);
6114 drm_crtc_vblank_on(crtc);
6115
f9b61ff6
DV
6116 for_each_encoder_on_crtc(dev, crtc, encoder)
6117 encoder->enable(encoder);
89b667f8
JB
6118}
6119
f13c2ef3
DV
6120static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6121{
6122 struct drm_device *dev = crtc->base.dev;
6123 struct drm_i915_private *dev_priv = dev->dev_private;
6124
6e3c9717
ACO
6125 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6126 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
f13c2ef3
DV
6127}
6128
0b8765c6 6129static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB
6130{
6131 struct drm_device *dev = crtc->dev;
a72e4c9f 6132 struct drm_i915_private *dev_priv = to_i915(dev);
79e53945 6133 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 6134 struct intel_encoder *encoder;
79e53945 6135 int pipe = intel_crtc->pipe;
79e53945 6136
83d65738 6137 WARN_ON(!crtc->state->enable);
08a48469 6138
f7abfe8b
CW
6139 if (intel_crtc->active)
6140 return;
6141
f13c2ef3
DV
6142 i9xx_set_pll_dividers(intel_crtc);
6143
6e3c9717 6144 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 6145 intel_dp_set_m_n(intel_crtc, M1_N1);
5b18e57c
DV
6146
6147 intel_set_pipe_timings(intel_crtc);
6148
5b18e57c
DV
6149 i9xx_set_pipeconf(intel_crtc);
6150
f7abfe8b 6151 intel_crtc->active = true;
6b383a7f 6152
4a3436e8 6153 if (!IS_GEN2(dev))
a72e4c9f 6154 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 6155
9d6d9f19
MK
6156 for_each_encoder_on_crtc(dev, crtc, encoder)
6157 if (encoder->pre_enable)
6158 encoder->pre_enable(encoder);
6159
f6736a1a
DV
6160 i9xx_enable_pll(intel_crtc);
6161
2dd24552
JB
6162 i9xx_pfit_enable(intel_crtc);
6163
63cbb074
VS
6164 intel_crtc_load_lut(crtc);
6165
f37fcc2a 6166 intel_update_watermarks(crtc);
e1fdc473 6167 intel_enable_pipe(intel_crtc);
be6a6f8e 6168
4b3a9526
VS
6169 assert_vblank_disabled(crtc);
6170 drm_crtc_vblank_on(crtc);
6171
f9b61ff6
DV
6172 for_each_encoder_on_crtc(dev, crtc, encoder)
6173 encoder->enable(encoder);
0b8765c6 6174}
79e53945 6175
87476d63
DV
6176static void i9xx_pfit_disable(struct intel_crtc *crtc)
6177{
6178 struct drm_device *dev = crtc->base.dev;
6179 struct drm_i915_private *dev_priv = dev->dev_private;
87476d63 6180
6e3c9717 6181 if (!crtc->config->gmch_pfit.control)
328d8e82 6182 return;
87476d63 6183
328d8e82 6184 assert_pipe_disabled(dev_priv, crtc->pipe);
87476d63 6185
328d8e82
DV
6186 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6187 I915_READ(PFIT_CONTROL));
6188 I915_WRITE(PFIT_CONTROL, 0);
87476d63
DV
6189}
6190
0b8765c6
JB
6191static void i9xx_crtc_disable(struct drm_crtc *crtc)
6192{
6193 struct drm_device *dev = crtc->dev;
6194 struct drm_i915_private *dev_priv = dev->dev_private;
6195 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 6196 struct intel_encoder *encoder;
0b8765c6 6197 int pipe = intel_crtc->pipe;
ef9c3aee 6198
f7abfe8b
CW
6199 if (!intel_crtc->active)
6200 return;
6201
6304cd91
VS
6202 /*
6203 * On gen2 planes are double buffered but the pipe isn't, so we must
6204 * wait for planes to fully turn off before disabling the pipe.
564ed191
ID
6205 * We also need to wait on all gmch platforms because of the
6206 * self-refresh mode constraint explained above.
6304cd91 6207 */
564ed191 6208 intel_wait_for_vblank(dev, pipe);
6304cd91 6209
4b3a9526
VS
6210 for_each_encoder_on_crtc(dev, crtc, encoder)
6211 encoder->disable(encoder);
6212
f9b61ff6
DV
6213 drm_crtc_vblank_off(crtc);
6214 assert_vblank_disabled(crtc);
6215
575f7ab7 6216 intel_disable_pipe(intel_crtc);
24a1f16d 6217
87476d63 6218 i9xx_pfit_disable(intel_crtc);
24a1f16d 6219
89b667f8
JB
6220 for_each_encoder_on_crtc(dev, crtc, encoder)
6221 if (encoder->post_disable)
6222 encoder->post_disable(encoder);
6223
409ee761 6224 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
076ed3b2
CML
6225 if (IS_CHERRYVIEW(dev))
6226 chv_disable_pll(dev_priv, pipe);
6227 else if (IS_VALLEYVIEW(dev))
6228 vlv_disable_pll(dev_priv, pipe);
6229 else
1c4e0274 6230 i9xx_disable_pll(intel_crtc);
076ed3b2 6231 }
0b8765c6 6232
4a3436e8 6233 if (!IS_GEN2(dev))
a72e4c9f 6234 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4a3436e8 6235
f7abfe8b 6236 intel_crtc->active = false;
46ba614c 6237 intel_update_watermarks(crtc);
f37fcc2a 6238
efa9624e 6239 mutex_lock(&dev->struct_mutex);
7ff0ebcc 6240 intel_fbc_update(dev);
efa9624e 6241 mutex_unlock(&dev->struct_mutex);
0b8765c6
JB
6242}
6243
ee7b9f93
JB
6244static void i9xx_crtc_off(struct drm_crtc *crtc)
6245{
6246}
6247
b04c5bd6
BF
6248/* Master function to enable/disable CRTC and corresponding power wells */
6249void intel_crtc_control(struct drm_crtc *crtc, bool enable)
976f8a20
DV
6250{
6251 struct drm_device *dev = crtc->dev;
6252 struct drm_i915_private *dev_priv = dev->dev_private;
0e572fe7 6253 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
0e572fe7
DV
6254 enum intel_display_power_domain domain;
6255 unsigned long domains;
976f8a20 6256
0e572fe7
DV
6257 if (enable) {
6258 if (!intel_crtc->active) {
e1e9fb84
DV
6259 domains = get_crtc_power_domains(crtc);
6260 for_each_power_domain(domain, domains)
6261 intel_display_power_get(dev_priv, domain);
6262 intel_crtc->enabled_power_domains = domains;
0e572fe7
DV
6263
6264 dev_priv->display.crtc_enable(crtc);
ce22dba9 6265 intel_crtc_enable_planes(crtc);
0e572fe7
DV
6266 }
6267 } else {
6268 if (intel_crtc->active) {
ce22dba9 6269 intel_crtc_disable_planes(crtc);
0e572fe7
DV
6270 dev_priv->display.crtc_disable(crtc);
6271
e1e9fb84
DV
6272 domains = intel_crtc->enabled_power_domains;
6273 for_each_power_domain(domain, domains)
6274 intel_display_power_put(dev_priv, domain);
6275 intel_crtc->enabled_power_domains = 0;
0e572fe7
DV
6276 }
6277 }
b04c5bd6
BF
6278}
6279
6280/**
6281 * Sets the power management mode of the pipe and plane.
6282 */
6283void intel_crtc_update_dpms(struct drm_crtc *crtc)
6284{
6285 struct drm_device *dev = crtc->dev;
6286 struct intel_encoder *intel_encoder;
6287 bool enable = false;
6288
6289 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
6290 enable |= intel_encoder->connectors_active;
6291
6292 intel_crtc_control(crtc, enable);
0f63cca2
ACO
6293
6294 crtc->state->active = enable;
976f8a20
DV
6295}
6296
cdd59983
CW
6297static void intel_crtc_disable(struct drm_crtc *crtc)
6298{
cdd59983 6299 struct drm_device *dev = crtc->dev;
976f8a20 6300 struct drm_connector *connector;
ee7b9f93 6301 struct drm_i915_private *dev_priv = dev->dev_private;
cdd59983 6302
976f8a20 6303 /* crtc should still be enabled when we disable it. */
83d65738 6304 WARN_ON(!crtc->state->enable);
976f8a20 6305
ce22dba9 6306 intel_crtc_disable_planes(crtc);
976f8a20 6307 dev_priv->display.crtc_disable(crtc);
ee7b9f93
JB
6308 dev_priv->display.off(crtc);
6309
70a101f8 6310 drm_plane_helper_disable(crtc->primary);
976f8a20
DV
6311
6312 /* Update computed state. */
6313 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
6314 if (!connector->encoder || !connector->encoder->crtc)
6315 continue;
6316
6317 if (connector->encoder->crtc != crtc)
6318 continue;
6319
6320 connector->dpms = DRM_MODE_DPMS_OFF;
6321 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW
6322 }
6323}
6324
ea5b213a 6325void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 6326{
4ef69c7a 6327 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 6328
ea5b213a
CW
6329 drm_encoder_cleanup(encoder);
6330 kfree(intel_encoder);
7e7d76c3
JB
6331}
6332
9237329d 6333/* Simple dpms helper for encoders with just one connector, no cloning and only
5ab432ef
DV
6334 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
6335 * state of the entire output pipe. */
9237329d 6336static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 6337{
5ab432ef
DV
6338 if (mode == DRM_MODE_DPMS_ON) {
6339 encoder->connectors_active = true;
6340
b2cabb0e 6341 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV
6342 } else {
6343 encoder->connectors_active = false;
6344
b2cabb0e 6345 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 6346 }
79e53945
JB
6347}
6348
0a91ca29
DV
6349/* Cross check the actual hw state with our own modeset state tracking (and it's
6350 * internal consistency). */
b980514c 6351static void intel_connector_check_state(struct intel_connector *connector)
79e53945 6352{
0a91ca29
DV
6353 if (connector->get_hw_state(connector)) {
6354 struct intel_encoder *encoder = connector->encoder;
6355 struct drm_crtc *crtc;
6356 bool encoder_enabled;
6357 enum pipe pipe;
6358
6359 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6360 connector->base.base.id,
c23cc417 6361 connector->base.name);
0a91ca29 6362
0e32b39c
DA
6363 /* there is no real hw state for MST connectors */
6364 if (connector->mst_port)
6365 return;
6366
e2c719b7 6367 I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
0a91ca29 6368 "wrong connector dpms state\n");
e2c719b7 6369 I915_STATE_WARN(connector->base.encoder != &encoder->base,
0a91ca29 6370 "active connector not linked to encoder\n");
0a91ca29 6371
36cd7444 6372 if (encoder) {
e2c719b7 6373 I915_STATE_WARN(!encoder->connectors_active,
36cd7444
DA
6374 "encoder->connectors_active not set\n");
6375
6376 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
e2c719b7
RC
6377 I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n");
6378 if (I915_STATE_WARN_ON(!encoder->base.crtc))
36cd7444 6379 return;
0a91ca29 6380
36cd7444 6381 crtc = encoder->base.crtc;
0a91ca29 6382
83d65738
MR
6383 I915_STATE_WARN(!crtc->state->enable,
6384 "crtc not enabled\n");
e2c719b7
RC
6385 I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
6386 I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe,
36cd7444
DA
6387 "encoder active on the wrong pipe\n");
6388 }
0a91ca29 6389 }
79e53945
JB
6390}
6391
08d9bc92
ACO
6392int intel_connector_init(struct intel_connector *connector)
6393{
6394 struct drm_connector_state *connector_state;
6395
6396 connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6397 if (!connector_state)
6398 return -ENOMEM;
6399
6400 connector->base.state = connector_state;
6401 return 0;
6402}
6403
6404struct intel_connector *intel_connector_alloc(void)
6405{
6406 struct intel_connector *connector;
6407
6408 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6409 if (!connector)
6410 return NULL;
6411
6412 if (intel_connector_init(connector) < 0) {
6413 kfree(connector);
6414 return NULL;
6415 }
6416
6417 return connector;
6418}
6419
5ab432ef
DV
6420/* Even simpler default implementation, if there's really no special case to
6421 * consider. */
6422void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 6423{
5ab432ef
DV
6424 /* All the simple cases only support two dpms states. */
6425 if (mode != DRM_MODE_DPMS_ON)
6426 mode = DRM_MODE_DPMS_OFF;
d4270e57 6427
5ab432ef
DV
6428 if (mode == connector->dpms)
6429 return;
6430
6431 connector->dpms = mode;
6432
6433 /* Only need to change hw state when actually enabled */
c9976dcf
CW
6434 if (connector->encoder)
6435 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
0a91ca29 6436
b980514c 6437 intel_modeset_check_state(connector->dev);
79e53945
JB
6438}
6439
f0947c37
DV
6440/* Simple connector->get_hw_state implementation for encoders that support only
6441 * one connector and no cloning and hence the encoder state determines the state
6442 * of the connector. */
6443bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 6444{
24929352 6445 enum pipe pipe = 0;
f0947c37 6446 struct intel_encoder *encoder = connector->encoder;
ea5b213a 6447
f0947c37 6448 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW
6449}
6450
6d293983 6451static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
d272ddfa 6452{
6d293983
ACO
6453 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6454 return crtc_state->fdi_lanes;
d272ddfa
VS
6455
6456 return 0;
6457}
6458
6d293983 6459static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5cec258b 6460 struct intel_crtc_state *pipe_config)
1857e1da 6461{
6d293983
ACO
6462 struct drm_atomic_state *state = pipe_config->base.state;
6463 struct intel_crtc *other_crtc;
6464 struct intel_crtc_state *other_crtc_state;
6465
1857e1da
DV
6466 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6467 pipe_name(pipe), pipe_config->fdi_lanes);
6468 if (pipe_config->fdi_lanes > 4) {
6469 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6470 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6471 return -EINVAL;
1857e1da
DV
6472 }
6473
bafb6553 6474 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
1857e1da
DV
6475 if (pipe_config->fdi_lanes > 2) {
6476 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6477 pipe_config->fdi_lanes);
6d293983 6478 return -EINVAL;
1857e1da 6479 } else {
6d293983 6480 return 0;
1857e1da
DV
6481 }
6482 }
6483
6484 if (INTEL_INFO(dev)->num_pipes == 2)
6d293983 6485 return 0;
1857e1da
DV
6486
6487 /* Ivybridge 3 pipe is really complicated */
6488 switch (pipe) {
6489 case PIPE_A:
6d293983 6490 return 0;
1857e1da 6491 case PIPE_B:
6d293983
ACO
6492 if (pipe_config->fdi_lanes <= 2)
6493 return 0;
6494
6495 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6496 other_crtc_state =
6497 intel_atomic_get_crtc_state(state, other_crtc);
6498 if (IS_ERR(other_crtc_state))
6499 return PTR_ERR(other_crtc_state);
6500
6501 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
1857e1da
DV
6502 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6503 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6504 return -EINVAL;
1857e1da 6505 }
6d293983 6506 return 0;
1857e1da 6507 case PIPE_C:
251cc67c
VS
6508 if (pipe_config->fdi_lanes > 2) {
6509 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6510 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6511 return -EINVAL;
251cc67c 6512 }
6d293983
ACO
6513
6514 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6515 other_crtc_state =
6516 intel_atomic_get_crtc_state(state, other_crtc);
6517 if (IS_ERR(other_crtc_state))
6518 return PTR_ERR(other_crtc_state);
6519
6520 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
1857e1da 6521 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6d293983 6522 return -EINVAL;
1857e1da 6523 }
6d293983 6524 return 0;
1857e1da
DV
6525 default:
6526 BUG();
6527 }
6528}
6529
e29c22c0
DV
6530#define RETRY 1
6531static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5cec258b 6532 struct intel_crtc_state *pipe_config)
877d48d5 6533{
1857e1da 6534 struct drm_device *dev = intel_crtc->base.dev;
2d112de7 6535 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6d293983
ACO
6536 int lane, link_bw, fdi_dotclock, ret;
6537 bool needs_recompute = false;
877d48d5 6538
e29c22c0 6539retry:
877d48d5
DV
6540 /* FDI is a binary signal running at ~2.7GHz, encoding
6541 * each output octet as 10 bits. The actual frequency
6542 * is stored as a divider into a 100MHz clock, and the
6543 * mode pixel clock is stored in units of 1KHz.
6544 * Hence the bw of each lane in terms of the mode signal
6545 * is:
6546 */
6547 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6548
241bfc38 6549 fdi_dotclock = adjusted_mode->crtc_clock;
877d48d5 6550
2bd89a07 6551 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
877d48d5
DV
6552 pipe_config->pipe_bpp);
6553
6554 pipe_config->fdi_lanes = lane;
6555
2bd89a07 6556 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
877d48d5 6557 link_bw, &pipe_config->fdi_m_n);
1857e1da 6558
6d293983
ACO
6559 ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6560 intel_crtc->pipe, pipe_config);
6561 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
e29c22c0
DV
6562 pipe_config->pipe_bpp -= 2*3;
6563 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6564 pipe_config->pipe_bpp);
6565 needs_recompute = true;
6566 pipe_config->bw_constrained = true;
6567
6568 goto retry;
6569 }
6570
6571 if (needs_recompute)
6572 return RETRY;
6573
6d293983 6574 return ret;
877d48d5
DV
6575}
6576
42db64ef 6577static void hsw_compute_ips_config(struct intel_crtc *crtc,
5cec258b 6578 struct intel_crtc_state *pipe_config)
42db64ef 6579{
d330a953 6580 pipe_config->ips_enabled = i915.enable_ips &&
3c4ca58c 6581 hsw_crtc_supports_ips(crtc) &&
b6dfdc9b 6582 pipe_config->pipe_bpp <= 24;
42db64ef
PZ
6583}
6584
a43f6e0f 6585static int intel_crtc_compute_config(struct intel_crtc *crtc,
5cec258b 6586 struct intel_crtc_state *pipe_config)
79e53945 6587{
a43f6e0f 6588 struct drm_device *dev = crtc->base.dev;
8bd31e67 6589 struct drm_i915_private *dev_priv = dev->dev_private;
2d112de7 6590 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
d03c93d4 6591 int ret;
89749350 6592
ad3a4479 6593 /* FIXME should check pixel clock limits on all platforms */
cf532bb2 6594 if (INTEL_INFO(dev)->gen < 4) {
cf532bb2
VS
6595 int clock_limit =
6596 dev_priv->display.get_display_clock_speed(dev);
6597
6598 /*
6599 * Enable pixel doubling when the dot clock
6600 * is > 90% of the (display) core speed.
6601 *
b397c96b
VS
6602 * GDG double wide on either pipe,
6603 * otherwise pipe A only.
cf532bb2 6604 */
b397c96b 6605 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
241bfc38 6606 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
ad3a4479 6607 clock_limit *= 2;
cf532bb2 6608 pipe_config->double_wide = true;
ad3a4479
VS
6609 }
6610
241bfc38 6611 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
e29c22c0 6612 return -EINVAL;
2c07245f 6613 }
89749350 6614
1d1d0e27
VS
6615 /*
6616 * Pipe horizontal size must be even in:
6617 * - DVO ganged mode
6618 * - LVDS dual channel mode
6619 * - Double wide pipe
6620 */
a93e255f 6621 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
1d1d0e27
VS
6622 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6623 pipe_config->pipe_src_w &= ~1;
6624
8693a824
DL
6625 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6626 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
44f46b42
CW
6627 */
6628 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6629 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
e29c22c0 6630 return -EINVAL;
44f46b42 6631
f5adf94e 6632 if (HAS_IPS(dev))
a43f6e0f
DV
6633 hsw_compute_ips_config(crtc, pipe_config);
6634
877d48d5 6635 if (pipe_config->has_pch_encoder)
a43f6e0f 6636 return ironlake_fdi_compute_config(crtc, pipe_config);
877d48d5 6637
d03c93d4
CK
6638 /* FIXME: remove below call once atomic mode set is place and all crtc
6639 * related checks called from atomic_crtc_check function */
6640 ret = 0;
6641 DRM_DEBUG_KMS("intel_crtc = %p drm_state (pipe_config->base.state) = %p\n",
6642 crtc, pipe_config->base.state);
6643 ret = intel_atomic_setup_scalers(dev, crtc, pipe_config);
6644
6645 return ret;
79e53945
JB
6646}
6647
1652d19e
VS
6648static int skylake_get_display_clock_speed(struct drm_device *dev)
6649{
6650 struct drm_i915_private *dev_priv = to_i915(dev);
6651 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6652 uint32_t cdctl = I915_READ(CDCLK_CTL);
6653 uint32_t linkrate;
6654
6655 if (!(lcpll1 & LCPLL_PLL_ENABLE)) {
6656 WARN(1, "LCPLL1 not enabled\n");
6657 return 24000; /* 24MHz is the cd freq with NSSC ref */
6658 }
6659
6660 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6661 return 540000;
6662
6663 linkrate = (I915_READ(DPLL_CTRL1) &
71cd8423 6664 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
1652d19e 6665
71cd8423
DL
6666 if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6667 linkrate == DPLL_CTRL1_LINK_RATE_1080) {
1652d19e
VS
6668 /* vco 8640 */
6669 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6670 case CDCLK_FREQ_450_432:
6671 return 432000;
6672 case CDCLK_FREQ_337_308:
6673 return 308570;
6674 case CDCLK_FREQ_675_617:
6675 return 617140;
6676 default:
6677 WARN(1, "Unknown cd freq selection\n");
6678 }
6679 } else {
6680 /* vco 8100 */
6681 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6682 case CDCLK_FREQ_450_432:
6683 return 450000;
6684 case CDCLK_FREQ_337_308:
6685 return 337500;
6686 case CDCLK_FREQ_675_617:
6687 return 675000;
6688 default:
6689 WARN(1, "Unknown cd freq selection\n");
6690 }
6691 }
6692
6693 /* error case, do as if DPLL0 isn't enabled */
6694 return 24000;
6695}
6696
6697static int broadwell_get_display_clock_speed(struct drm_device *dev)
6698{
6699 struct drm_i915_private *dev_priv = dev->dev_private;
6700 uint32_t lcpll = I915_READ(LCPLL_CTL);
6701 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6702
6703 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6704 return 800000;
6705 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6706 return 450000;
6707 else if (freq == LCPLL_CLK_FREQ_450)
6708 return 450000;
6709 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6710 return 540000;
6711 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6712 return 337500;
6713 else
6714 return 675000;
6715}
6716
6717static int haswell_get_display_clock_speed(struct drm_device *dev)
6718{
6719 struct drm_i915_private *dev_priv = dev->dev_private;
6720 uint32_t lcpll = I915_READ(LCPLL_CTL);
6721 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6722
6723 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6724 return 800000;
6725 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6726 return 450000;
6727 else if (freq == LCPLL_CLK_FREQ_450)
6728 return 450000;
6729 else if (IS_HSW_ULT(dev))
6730 return 337500;
6731 else
6732 return 540000;
79e53945
JB
6733}
6734
25eb05fc
JB
6735static int valleyview_get_display_clock_speed(struct drm_device *dev)
6736{
d197b7d3 6737 struct drm_i915_private *dev_priv = dev->dev_private;
d197b7d3
VS
6738 u32 val;
6739 int divider;
6740
6bcda4f0
VS
6741 if (dev_priv->hpll_freq == 0)
6742 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
6743
a580516d 6744 mutex_lock(&dev_priv->sb_lock);
d197b7d3 6745 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
a580516d 6746 mutex_unlock(&dev_priv->sb_lock);
d197b7d3
VS
6747
6748 divider = val & DISPLAY_FREQUENCY_VALUES;
6749
7d007f40
VS
6750 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
6751 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
6752 "cdclk change in progress\n");
6753
6bcda4f0 6754 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
25eb05fc
JB
6755}
6756
b37a6434
VS
6757static int ilk_get_display_clock_speed(struct drm_device *dev)
6758{
6759 return 450000;
6760}
6761
e70236a8
JB
6762static int i945_get_display_clock_speed(struct drm_device *dev)
6763{
6764 return 400000;
6765}
79e53945 6766
e70236a8 6767static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 6768{
e907f170 6769 return 333333;
e70236a8 6770}
79e53945 6771
e70236a8
JB
6772static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6773{
6774 return 200000;
6775}
79e53945 6776
257a7ffc
DV
6777static int pnv_get_display_clock_speed(struct drm_device *dev)
6778{
6779 u16 gcfgc = 0;
6780
6781 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6782
6783 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6784 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
e907f170 6785 return 266667;
257a7ffc 6786 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
e907f170 6787 return 333333;
257a7ffc 6788 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
e907f170 6789 return 444444;
257a7ffc
DV
6790 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6791 return 200000;
6792 default:
6793 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6794 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
e907f170 6795 return 133333;
257a7ffc 6796 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
e907f170 6797 return 166667;
257a7ffc
DV
6798 }
6799}
6800
e70236a8
JB
6801static int i915gm_get_display_clock_speed(struct drm_device *dev)
6802{
6803 u16 gcfgc = 0;
79e53945 6804
e70236a8
JB
6805 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6806
6807 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
e907f170 6808 return 133333;
e70236a8
JB
6809 else {
6810 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6811 case GC_DISPLAY_CLOCK_333_MHZ:
e907f170 6812 return 333333;
e70236a8
JB
6813 default:
6814 case GC_DISPLAY_CLOCK_190_200_MHZ:
6815 return 190000;
79e53945 6816 }
e70236a8
JB
6817 }
6818}
6819
6820static int i865_get_display_clock_speed(struct drm_device *dev)
6821{
e907f170 6822 return 266667;
e70236a8
JB
6823}
6824
6825static int i855_get_display_clock_speed(struct drm_device *dev)
6826{
6827 u16 hpllcc = 0;
6828 /* Assume that the hardware is in the high speed state. This
6829 * should be the default.
6830 */
6831 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6832 case GC_CLOCK_133_200:
6833 case GC_CLOCK_100_200:
6834 return 200000;
6835 case GC_CLOCK_166_250:
6836 return 250000;
6837 case GC_CLOCK_100_133:
e907f170 6838 return 133333;
e70236a8 6839 }
79e53945 6840
e70236a8
JB
6841 /* Shouldn't happen */
6842 return 0;
6843}
79e53945 6844
e70236a8
JB
6845static int i830_get_display_clock_speed(struct drm_device *dev)
6846{
e907f170 6847 return 133333;
79e53945
JB
6848}
6849
2c07245f 6850static void
a65851af 6851intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
2c07245f 6852{
a65851af
VS
6853 while (*num > DATA_LINK_M_N_MASK ||
6854 *den > DATA_LINK_M_N_MASK) {
2c07245f
ZW
6855 *num >>= 1;
6856 *den >>= 1;
6857 }
6858}
6859
a65851af
VS
6860static void compute_m_n(unsigned int m, unsigned int n,
6861 uint32_t *ret_m, uint32_t *ret_n)
6862{
6863 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
6864 *ret_m = div_u64((uint64_t) m * *ret_n, n);
6865 intel_reduce_m_n_ratio(ret_m, ret_n);
6866}
6867
e69d0bc1
DV
6868void
6869intel_link_compute_m_n(int bits_per_pixel, int nlanes,
6870 int pixel_clock, int link_clock,
6871 struct intel_link_m_n *m_n)
2c07245f 6872{
e69d0bc1 6873 m_n->tu = 64;
a65851af
VS
6874
6875 compute_m_n(bits_per_pixel * pixel_clock,
6876 link_clock * nlanes * 8,
6877 &m_n->gmch_m, &m_n->gmch_n);
6878
6879 compute_m_n(pixel_clock, link_clock,
6880 &m_n->link_m, &m_n->link_n);
2c07245f
ZW
6881}
6882
a7615030
CW
6883static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
6884{
d330a953
JN
6885 if (i915.panel_use_ssc >= 0)
6886 return i915.panel_use_ssc != 0;
41aa3448 6887 return dev_priv->vbt.lvds_use_ssc
435793df 6888 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW
6889}
6890
a93e255f
ACO
6891static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
6892 int num_connectors)
c65d77d8 6893{
a93e255f 6894 struct drm_device *dev = crtc_state->base.crtc->dev;
c65d77d8
JB
6895 struct drm_i915_private *dev_priv = dev->dev_private;
6896 int refclk;
6897
a93e255f
ACO
6898 WARN_ON(!crtc_state->base.state);
6899
5ab7b0b7 6900 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
9a0ea498 6901 refclk = 100000;
a93e255f 6902 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
c65d77d8 6903 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
e91e941b
VS
6904 refclk = dev_priv->vbt.lvds_ssc_freq;
6905 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
c65d77d8
JB
6906 } else if (!IS_GEN2(dev)) {
6907 refclk = 96000;
6908 } else {
6909 refclk = 48000;
6910 }
6911
6912 return refclk;
6913}
6914
7429e9d4 6915static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
c65d77d8 6916{
7df00d7a 6917 return (1 << dpll->n) << 16 | dpll->m2;
7429e9d4 6918}
f47709a9 6919
7429e9d4
DV
6920static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
6921{
6922 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
c65d77d8
JB
6923}
6924
f47709a9 6925static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
190f68c5 6926 struct intel_crtc_state *crtc_state,
a7516a05
JB
6927 intel_clock_t *reduced_clock)
6928{
f47709a9 6929 struct drm_device *dev = crtc->base.dev;
a7516a05
JB
6930 u32 fp, fp2 = 0;
6931
6932 if (IS_PINEVIEW(dev)) {
190f68c5 6933 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
a7516a05 6934 if (reduced_clock)
7429e9d4 6935 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 6936 } else {
190f68c5 6937 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
a7516a05 6938 if (reduced_clock)
7429e9d4 6939 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB
6940 }
6941
190f68c5 6942 crtc_state->dpll_hw_state.fp0 = fp;
a7516a05 6943
f47709a9 6944 crtc->lowfreq_avail = false;
a93e255f 6945 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
ab585dea 6946 reduced_clock) {
190f68c5 6947 crtc_state->dpll_hw_state.fp1 = fp2;
f47709a9 6948 crtc->lowfreq_avail = true;
a7516a05 6949 } else {
190f68c5 6950 crtc_state->dpll_hw_state.fp1 = fp;
a7516a05
JB
6951 }
6952}
6953
5e69f97f
CML
6954static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
6955 pipe)
89b667f8
JB
6956{
6957 u32 reg_val;
6958
6959 /*
6960 * PLLB opamp always calibrates to max value of 0x3f, force enable it
6961 * and set it to a reasonable value instead.
6962 */
ab3c759a 6963 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
89b667f8
JB
6964 reg_val &= 0xffffff00;
6965 reg_val |= 0x00000030;
ab3c759a 6966 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
89b667f8 6967
ab3c759a 6968 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
89b667f8
JB
6969 reg_val &= 0x8cffffff;
6970 reg_val = 0x8c000000;
ab3c759a 6971 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
89b667f8 6972
ab3c759a 6973 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
89b667f8 6974 reg_val &= 0xffffff00;
ab3c759a 6975 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
89b667f8 6976
ab3c759a 6977 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
89b667f8
JB
6978 reg_val &= 0x00ffffff;
6979 reg_val |= 0xb0000000;
ab3c759a 6980 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
89b667f8
JB
6981}
6982
b551842d
DV
6983static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
6984 struct intel_link_m_n *m_n)
6985{
6986 struct drm_device *dev = crtc->base.dev;
6987 struct drm_i915_private *dev_priv = dev->dev_private;
6988 int pipe = crtc->pipe;
6989
e3b95f1e
DV
6990 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6991 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
6992 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
6993 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
b551842d
DV
6994}
6995
6996static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
f769cd24
VK
6997 struct intel_link_m_n *m_n,
6998 struct intel_link_m_n *m2_n2)
b551842d
DV
6999{
7000 struct drm_device *dev = crtc->base.dev;
7001 struct drm_i915_private *dev_priv = dev->dev_private;
7002 int pipe = crtc->pipe;
6e3c9717 7003 enum transcoder transcoder = crtc->config->cpu_transcoder;
b551842d
DV
7004
7005 if (INTEL_INFO(dev)->gen >= 5) {
7006 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7007 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7008 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7009 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
f769cd24
VK
7010 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7011 * for gen < 8) and if DRRS is supported (to make sure the
7012 * registers are not unnecessarily accessed).
7013 */
44395bfe 7014 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
6e3c9717 7015 crtc->config->has_drrs) {
f769cd24
VK
7016 I915_WRITE(PIPE_DATA_M2(transcoder),
7017 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7018 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7019 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7020 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7021 }
b551842d 7022 } else {
e3b95f1e
DV
7023 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7024 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7025 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7026 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
b551842d
DV
7027 }
7028}
7029
fe3cd48d 7030void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
03afc4a2 7031{
fe3cd48d
R
7032 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7033
7034 if (m_n == M1_N1) {
7035 dp_m_n = &crtc->config->dp_m_n;
7036 dp_m2_n2 = &crtc->config->dp_m2_n2;
7037 } else if (m_n == M2_N2) {
7038
7039 /*
7040 * M2_N2 registers are not supported. Hence m2_n2 divider value
7041 * needs to be programmed into M1_N1.
7042 */
7043 dp_m_n = &crtc->config->dp_m2_n2;
7044 } else {
7045 DRM_ERROR("Unsupported divider value\n");
7046 return;
7047 }
7048
6e3c9717
ACO
7049 if (crtc->config->has_pch_encoder)
7050 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
03afc4a2 7051 else
fe3cd48d 7052 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
03afc4a2
DV
7053}
7054
d288f65f 7055static void vlv_update_pll(struct intel_crtc *crtc,
5cec258b 7056 struct intel_crtc_state *pipe_config)
bdd4b6a6
DV
7057{
7058 u32 dpll, dpll_md;
7059
7060 /*
7061 * Enable DPIO clock input. We should never disable the reference
7062 * clock for pipe B, since VGA hotplug / manual detection depends
7063 * on it.
7064 */
7065 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
7066 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
7067 /* We should never disable this, set it here for state tracking */
7068 if (crtc->pipe == PIPE_B)
7069 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7070 dpll |= DPLL_VCO_ENABLE;
d288f65f 7071 pipe_config->dpll_hw_state.dpll = dpll;
bdd4b6a6 7072
d288f65f 7073 dpll_md = (pipe_config->pixel_multiplier - 1)
bdd4b6a6 7074 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
d288f65f 7075 pipe_config->dpll_hw_state.dpll_md = dpll_md;
bdd4b6a6
DV
7076}
7077
d288f65f 7078static void vlv_prepare_pll(struct intel_crtc *crtc,
5cec258b 7079 const struct intel_crtc_state *pipe_config)
a0c4da24 7080{
f47709a9 7081 struct drm_device *dev = crtc->base.dev;
a0c4da24 7082 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 7083 int pipe = crtc->pipe;
bdd4b6a6 7084 u32 mdiv;
a0c4da24 7085 u32 bestn, bestm1, bestm2, bestp1, bestp2;
bdd4b6a6 7086 u32 coreclk, reg_val;
a0c4da24 7087
a580516d 7088 mutex_lock(&dev_priv->sb_lock);
09153000 7089
d288f65f
VS
7090 bestn = pipe_config->dpll.n;
7091 bestm1 = pipe_config->dpll.m1;
7092 bestm2 = pipe_config->dpll.m2;
7093 bestp1 = pipe_config->dpll.p1;
7094 bestp2 = pipe_config->dpll.p2;
a0c4da24 7095
89b667f8
JB
7096 /* See eDP HDMI DPIO driver vbios notes doc */
7097
7098 /* PLL B needs special handling */
bdd4b6a6 7099 if (pipe == PIPE_B)
5e69f97f 7100 vlv_pllb_recal_opamp(dev_priv, pipe);
89b667f8
JB
7101
7102 /* Set up Tx target for periodic Rcomp update */
ab3c759a 7103 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
89b667f8
JB
7104
7105 /* Disable target IRef on PLL */
ab3c759a 7106 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
89b667f8 7107 reg_val &= 0x00ffffff;
ab3c759a 7108 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
89b667f8
JB
7109
7110 /* Disable fast lock */
ab3c759a 7111 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
89b667f8
JB
7112
7113 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB
7114 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7115 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7116 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 7117 mdiv |= (1 << DPIO_K_SHIFT);
7df5080b
JB
7118
7119 /*
7120 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7121 * but we don't support that).
7122 * Note: don't use the DAC post divider as it seems unstable.
7123 */
7124 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
ab3c759a 7125 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
a0c4da24 7126
a0c4da24 7127 mdiv |= DPIO_ENABLE_CALIBRATION;
ab3c759a 7128 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
a0c4da24 7129
89b667f8 7130 /* Set HBR and RBR LPF coefficients */
d288f65f 7131 if (pipe_config->port_clock == 162000 ||
409ee761
ACO
7132 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7133 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
ab3c759a 7134 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
885b0120 7135 0x009f0003);
89b667f8 7136 else
ab3c759a 7137 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
89b667f8
JB
7138 0x00d0000f);
7139
681a8504 7140 if (pipe_config->has_dp_encoder) {
89b667f8 7141 /* Use SSC source */
bdd4b6a6 7142 if (pipe == PIPE_A)
ab3c759a 7143 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB
7144 0x0df40000);
7145 else
ab3c759a 7146 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB
7147 0x0df70000);
7148 } else { /* HDMI or VGA */
7149 /* Use bend source */
bdd4b6a6 7150 if (pipe == PIPE_A)
ab3c759a 7151 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB
7152 0x0df70000);
7153 else
ab3c759a 7154 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB
7155 0x0df40000);
7156 }
a0c4da24 7157
ab3c759a 7158 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
89b667f8 7159 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
409ee761
ACO
7160 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7161 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
89b667f8 7162 coreclk |= 0x01000000;
ab3c759a 7163 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
a0c4da24 7164
ab3c759a 7165 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
a580516d 7166 mutex_unlock(&dev_priv->sb_lock);
a0c4da24
JB
7167}
7168
d288f65f 7169static void chv_update_pll(struct intel_crtc *crtc,
5cec258b 7170 struct intel_crtc_state *pipe_config)
1ae0d137 7171{
d288f65f 7172 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
1ae0d137
VS
7173 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
7174 DPLL_VCO_ENABLE;
7175 if (crtc->pipe != PIPE_A)
d288f65f 7176 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
1ae0d137 7177
d288f65f
VS
7178 pipe_config->dpll_hw_state.dpll_md =
7179 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
1ae0d137
VS
7180}
7181
d288f65f 7182static void chv_prepare_pll(struct intel_crtc *crtc,
5cec258b 7183 const struct intel_crtc_state *pipe_config)
9d556c99
CML
7184{
7185 struct drm_device *dev = crtc->base.dev;
7186 struct drm_i915_private *dev_priv = dev->dev_private;
7187 int pipe = crtc->pipe;
7188 int dpll_reg = DPLL(crtc->pipe);
7189 enum dpio_channel port = vlv_pipe_to_channel(pipe);
9cbe40c1 7190 u32 loopfilter, tribuf_calcntr;
9d556c99 7191 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
a945ce7e 7192 u32 dpio_val;
9cbe40c1 7193 int vco;
9d556c99 7194
d288f65f
VS
7195 bestn = pipe_config->dpll.n;
7196 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7197 bestm1 = pipe_config->dpll.m1;
7198 bestm2 = pipe_config->dpll.m2 >> 22;
7199 bestp1 = pipe_config->dpll.p1;
7200 bestp2 = pipe_config->dpll.p2;
9cbe40c1 7201 vco = pipe_config->dpll.vco;
a945ce7e 7202 dpio_val = 0;
9cbe40c1 7203 loopfilter = 0;
9d556c99
CML
7204
7205 /*
7206 * Enable Refclk and SSC
7207 */
a11b0703 7208 I915_WRITE(dpll_reg,
d288f65f 7209 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
a11b0703 7210
a580516d 7211 mutex_lock(&dev_priv->sb_lock);
9d556c99 7212
9d556c99
CML
7213 /* p1 and p2 divider */
7214 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7215 5 << DPIO_CHV_S1_DIV_SHIFT |
7216 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7217 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7218 1 << DPIO_CHV_K_DIV_SHIFT);
7219
7220 /* Feedback post-divider - m2 */
7221 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7222
7223 /* Feedback refclk divider - n and m1 */
7224 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7225 DPIO_CHV_M1_DIV_BY_2 |
7226 1 << DPIO_CHV_N_DIV_SHIFT);
7227
7228 /* M2 fraction division */
a945ce7e
VP
7229 if (bestm2_frac)
7230 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
9d556c99
CML
7231
7232 /* M2 fraction division enable */
a945ce7e
VP
7233 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7234 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7235 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7236 if (bestm2_frac)
7237 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7238 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
9d556c99 7239
de3a0fde
VP
7240 /* Program digital lock detect threshold */
7241 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7242 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7243 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7244 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7245 if (!bestm2_frac)
7246 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7247 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7248
9d556c99 7249 /* Loop filter */
9cbe40c1
VP
7250 if (vco == 5400000) {
7251 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7252 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7253 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7254 tribuf_calcntr = 0x9;
7255 } else if (vco <= 6200000) {
7256 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7257 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7258 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7259 tribuf_calcntr = 0x9;
7260 } else if (vco <= 6480000) {
7261 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7262 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7263 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7264 tribuf_calcntr = 0x8;
7265 } else {
7266 /* Not supported. Apply the same limits as in the max case */
7267 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7268 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7269 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7270 tribuf_calcntr = 0;
7271 }
9d556c99
CML
7272 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7273
968040b2 7274 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
9cbe40c1
VP
7275 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7276 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7277 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7278
9d556c99
CML
7279 /* AFC Recal */
7280 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7281 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7282 DPIO_AFC_RECAL);
7283
a580516d 7284 mutex_unlock(&dev_priv->sb_lock);
9d556c99
CML
7285}
7286
d288f65f
VS
7287/**
7288 * vlv_force_pll_on - forcibly enable just the PLL
7289 * @dev_priv: i915 private structure
7290 * @pipe: pipe PLL to enable
7291 * @dpll: PLL configuration
7292 *
7293 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7294 * in cases where we need the PLL enabled even when @pipe is not going to
7295 * be enabled.
7296 */
7297void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7298 const struct dpll *dpll)
7299{
7300 struct intel_crtc *crtc =
7301 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
5cec258b 7302 struct intel_crtc_state pipe_config = {
a93e255f 7303 .base.crtc = &crtc->base,
d288f65f
VS
7304 .pixel_multiplier = 1,
7305 .dpll = *dpll,
7306 };
7307
7308 if (IS_CHERRYVIEW(dev)) {
7309 chv_update_pll(crtc, &pipe_config);
7310 chv_prepare_pll(crtc, &pipe_config);
7311 chv_enable_pll(crtc, &pipe_config);
7312 } else {
7313 vlv_update_pll(crtc, &pipe_config);
7314 vlv_prepare_pll(crtc, &pipe_config);
7315 vlv_enable_pll(crtc, &pipe_config);
7316 }
7317}
7318
7319/**
7320 * vlv_force_pll_off - forcibly disable just the PLL
7321 * @dev_priv: i915 private structure
7322 * @pipe: pipe PLL to disable
7323 *
7324 * Disable the PLL for @pipe. To be used in cases where we need
7325 * the PLL enabled even when @pipe is not going to be enabled.
7326 */
7327void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7328{
7329 if (IS_CHERRYVIEW(dev))
7330 chv_disable_pll(to_i915(dev), pipe);
7331 else
7332 vlv_disable_pll(to_i915(dev), pipe);
7333}
7334
f47709a9 7335static void i9xx_update_pll(struct intel_crtc *crtc,
190f68c5 7336 struct intel_crtc_state *crtc_state,
f47709a9 7337 intel_clock_t *reduced_clock,
eb1cbe48
DV
7338 int num_connectors)
7339{
f47709a9 7340 struct drm_device *dev = crtc->base.dev;
eb1cbe48 7341 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48
DV
7342 u32 dpll;
7343 bool is_sdvo;
190f68c5 7344 struct dpll *clock = &crtc_state->dpll;
eb1cbe48 7345
190f68c5 7346 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
2a8f64ca 7347
a93e255f
ACO
7348 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7349 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
eb1cbe48
DV
7350
7351 dpll = DPLL_VGA_MODE_DIS;
7352
a93e255f 7353 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
eb1cbe48
DV
7354 dpll |= DPLLB_MODE_LVDS;
7355 else
7356 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 7357
ef1b460d 7358 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
190f68c5 7359 dpll |= (crtc_state->pixel_multiplier - 1)
198a037f 7360 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 7361 }
198a037f
DV
7362
7363 if (is_sdvo)
4a33e48d 7364 dpll |= DPLL_SDVO_HIGH_SPEED;
198a037f 7365
190f68c5 7366 if (crtc_state->has_dp_encoder)
4a33e48d 7367 dpll |= DPLL_SDVO_HIGH_SPEED;
eb1cbe48
DV
7368
7369 /* compute bitmask from p1 value */
7370 if (IS_PINEVIEW(dev))
7371 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7372 else {
7373 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7374 if (IS_G4X(dev) && reduced_clock)
7375 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7376 }
7377 switch (clock->p2) {
7378 case 5:
7379 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7380 break;
7381 case 7:
7382 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7383 break;
7384 case 10:
7385 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7386 break;
7387 case 14:
7388 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7389 break;
7390 }
7391 if (INTEL_INFO(dev)->gen >= 4)
7392 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7393
190f68c5 7394 if (crtc_state->sdvo_tv_clock)
eb1cbe48 7395 dpll |= PLL_REF_INPUT_TVCLKINBC;
a93e255f 7396 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV
7397 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7398 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7399 else
7400 dpll |= PLL_REF_INPUT_DREFCLK;
7401
7402 dpll |= DPLL_VCO_ENABLE;
190f68c5 7403 crtc_state->dpll_hw_state.dpll = dpll;
8bcc2795 7404
eb1cbe48 7405 if (INTEL_INFO(dev)->gen >= 4) {
190f68c5 7406 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
ef1b460d 7407 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
190f68c5 7408 crtc_state->dpll_hw_state.dpll_md = dpll_md;
eb1cbe48
DV
7409 }
7410}
7411
f47709a9 7412static void i8xx_update_pll(struct intel_crtc *crtc,
190f68c5 7413 struct intel_crtc_state *crtc_state,
f47709a9 7414 intel_clock_t *reduced_clock,
eb1cbe48
DV
7415 int num_connectors)
7416{
f47709a9 7417 struct drm_device *dev = crtc->base.dev;
eb1cbe48 7418 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48 7419 u32 dpll;
190f68c5 7420 struct dpll *clock = &crtc_state->dpll;
eb1cbe48 7421
190f68c5 7422 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
2a8f64ca 7423
eb1cbe48
DV
7424 dpll = DPLL_VGA_MODE_DIS;
7425
a93e255f 7426 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV
7427 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7428 } else {
7429 if (clock->p1 == 2)
7430 dpll |= PLL_P1_DIVIDE_BY_TWO;
7431 else
7432 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7433 if (clock->p2 == 4)
7434 dpll |= PLL_P2_DIVIDE_BY_4;
7435 }
7436
a93e255f 7437 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
4a33e48d
DV
7438 dpll |= DPLL_DVO_2X_MODE;
7439
a93e255f 7440 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV
7441 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7442 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7443 else
7444 dpll |= PLL_REF_INPUT_DREFCLK;
7445
7446 dpll |= DPLL_VCO_ENABLE;
190f68c5 7447 crtc_state->dpll_hw_state.dpll = dpll;
eb1cbe48
DV
7448}
7449
8a654f3b 7450static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
b0e77b9c
PZ
7451{
7452 struct drm_device *dev = intel_crtc->base.dev;
7453 struct drm_i915_private *dev_priv = dev->dev_private;
7454 enum pipe pipe = intel_crtc->pipe;
6e3c9717 7455 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8a654f3b 7456 struct drm_display_mode *adjusted_mode =
6e3c9717 7457 &intel_crtc->config->base.adjusted_mode;
1caea6e9
VS
7458 uint32_t crtc_vtotal, crtc_vblank_end;
7459 int vsyncshift = 0;
4d8a62ea
DV
7460
7461 /* We need to be careful not to changed the adjusted mode, for otherwise
7462 * the hw state checker will get angry at the mismatch. */
7463 crtc_vtotal = adjusted_mode->crtc_vtotal;
7464 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
b0e77b9c 7465
609aeaca 7466 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
b0e77b9c 7467 /* the chip adds 2 halflines automatically */
4d8a62ea
DV
7468 crtc_vtotal -= 1;
7469 crtc_vblank_end -= 1;
609aeaca 7470
409ee761 7471 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
609aeaca
VS
7472 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7473 else
7474 vsyncshift = adjusted_mode->crtc_hsync_start -
7475 adjusted_mode->crtc_htotal / 2;
1caea6e9
VS
7476 if (vsyncshift < 0)
7477 vsyncshift += adjusted_mode->crtc_htotal;
b0e77b9c
PZ
7478 }
7479
7480 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 7481 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 7482
fe2b8f9d 7483 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ
7484 (adjusted_mode->crtc_hdisplay - 1) |
7485 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 7486 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ
7487 (adjusted_mode->crtc_hblank_start - 1) |
7488 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 7489 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ
7490 (adjusted_mode->crtc_hsync_start - 1) |
7491 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7492
fe2b8f9d 7493 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c 7494 (adjusted_mode->crtc_vdisplay - 1) |
4d8a62ea 7495 ((crtc_vtotal - 1) << 16));
fe2b8f9d 7496 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c 7497 (adjusted_mode->crtc_vblank_start - 1) |
4d8a62ea 7498 ((crtc_vblank_end - 1) << 16));
fe2b8f9d 7499 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ
7500 (adjusted_mode->crtc_vsync_start - 1) |
7501 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7502
b5e508d4
PZ
7503 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7504 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7505 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7506 * bits. */
7507 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7508 (pipe == PIPE_B || pipe == PIPE_C))
7509 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7510
b0e77b9c
PZ
7511 /* pipesrc controls the size that is scaled from, which should
7512 * always be the user's requested size.
7513 */
7514 I915_WRITE(PIPESRC(pipe),
6e3c9717
ACO
7515 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7516 (intel_crtc->config->pipe_src_h - 1));
b0e77b9c
PZ
7517}
7518
1bd1bd80 7519static void intel_get_pipe_timings(struct intel_crtc *crtc,
5cec258b 7520 struct intel_crtc_state *pipe_config)
1bd1bd80
DV
7521{
7522 struct drm_device *dev = crtc->base.dev;
7523 struct drm_i915_private *dev_priv = dev->dev_private;
7524 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7525 uint32_t tmp;
7526
7527 tmp = I915_READ(HTOTAL(cpu_transcoder));
2d112de7
ACO
7528 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7529 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7530 tmp = I915_READ(HBLANK(cpu_transcoder));
2d112de7
ACO
7531 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7532 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7533 tmp = I915_READ(HSYNC(cpu_transcoder));
2d112de7
ACO
7534 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7535 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80
DV
7536
7537 tmp = I915_READ(VTOTAL(cpu_transcoder));
2d112de7
ACO
7538 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7539 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7540 tmp = I915_READ(VBLANK(cpu_transcoder));
2d112de7
ACO
7541 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7542 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7543 tmp = I915_READ(VSYNC(cpu_transcoder));
2d112de7
ACO
7544 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7545 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80
DV
7546
7547 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
2d112de7
ACO
7548 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7549 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7550 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
1bd1bd80
DV
7551 }
7552
7553 tmp = I915_READ(PIPESRC(crtc->pipe));
37327abd
VS
7554 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7555 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7556
2d112de7
ACO
7557 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7558 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
1bd1bd80
DV
7559}
7560
f6a83288 7561void intel_mode_from_pipe_config(struct drm_display_mode *mode,
5cec258b 7562 struct intel_crtc_state *pipe_config)
babea61d 7563{
2d112de7
ACO
7564 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7565 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7566 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7567 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
babea61d 7568
2d112de7
ACO
7569 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7570 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7571 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7572 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
babea61d 7573
2d112de7 7574 mode->flags = pipe_config->base.adjusted_mode.flags;
babea61d 7575
2d112de7
ACO
7576 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7577 mode->flags |= pipe_config->base.adjusted_mode.flags;
babea61d
JB
7578}
7579
84b046f3
DV
7580static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7581{
7582 struct drm_device *dev = intel_crtc->base.dev;
7583 struct drm_i915_private *dev_priv = dev->dev_private;
7584 uint32_t pipeconf;
7585
9f11a9e4 7586 pipeconf = 0;
84b046f3 7587
b6b5d049
VS
7588 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7589 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7590 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
67c72a12 7591
6e3c9717 7592 if (intel_crtc->config->double_wide)
cf532bb2 7593 pipeconf |= PIPECONF_DOUBLE_WIDE;
84b046f3 7594
ff9ce46e
DV
7595 /* only g4x and later have fancy bpc/dither controls */
7596 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
ff9ce46e 7597 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6e3c9717 7598 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
ff9ce46e 7599 pipeconf |= PIPECONF_DITHER_EN |
84b046f3 7600 PIPECONF_DITHER_TYPE_SP;
84b046f3 7601
6e3c9717 7602 switch (intel_crtc->config->pipe_bpp) {
ff9ce46e
DV
7603 case 18:
7604 pipeconf |= PIPECONF_6BPC;
7605 break;
7606 case 24:
7607 pipeconf |= PIPECONF_8BPC;
7608 break;
7609 case 30:
7610 pipeconf |= PIPECONF_10BPC;
7611 break;
7612 default:
7613 /* Case prevented by intel_choose_pipe_bpp_dither. */
7614 BUG();
84b046f3
DV
7615 }
7616 }
7617
7618 if (HAS_PIPE_CXSR(dev)) {
7619 if (intel_crtc->lowfreq_avail) {
7620 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7621 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7622 } else {
7623 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
84b046f3
DV
7624 }
7625 }
7626
6e3c9717 7627 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
efc2cfff 7628 if (INTEL_INFO(dev)->gen < 4 ||
409ee761 7629 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
efc2cfff
VS
7630 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7631 else
7632 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7633 } else
84b046f3
DV
7634 pipeconf |= PIPECONF_PROGRESSIVE;
7635
6e3c9717 7636 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
9f11a9e4 7637 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
9c8e09b7 7638
84b046f3
DV
7639 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7640 POSTING_READ(PIPECONF(intel_crtc->pipe));
7641}
7642
190f68c5
ACO
7643static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7644 struct intel_crtc_state *crtc_state)
79e53945 7645{
c7653199 7646 struct drm_device *dev = crtc->base.dev;
79e53945 7647 struct drm_i915_private *dev_priv = dev->dev_private;
c751ce4f 7648 int refclk, num_connectors = 0;
652c393a 7649 intel_clock_t clock, reduced_clock;
a16af721 7650 bool ok, has_reduced_clock = false;
e9fd1c02 7651 bool is_lvds = false, is_dsi = false;
5eddb70b 7652 struct intel_encoder *encoder;
d4906093 7653 const intel_limit_t *limit;
55bb9992 7654 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 7655 struct drm_connector *connector;
55bb9992
ACO
7656 struct drm_connector_state *connector_state;
7657 int i;
79e53945 7658
dd3cd74a
ACO
7659 memset(&crtc_state->dpll_hw_state, 0,
7660 sizeof(crtc_state->dpll_hw_state));
7661
da3ced29 7662 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO
7663 if (connector_state->crtc != &crtc->base)
7664 continue;
7665
7666 encoder = to_intel_encoder(connector_state->best_encoder);
7667
5eddb70b 7668 switch (encoder->type) {
79e53945
JB
7669 case INTEL_OUTPUT_LVDS:
7670 is_lvds = true;
7671 break;
e9fd1c02
JN
7672 case INTEL_OUTPUT_DSI:
7673 is_dsi = true;
7674 break;
6847d71b
PZ
7675 default:
7676 break;
79e53945 7677 }
43565a06 7678
c751ce4f 7679 num_connectors++;
79e53945
JB
7680 }
7681
f2335330 7682 if (is_dsi)
5b18e57c 7683 return 0;
f2335330 7684
190f68c5 7685 if (!crtc_state->clock_set) {
a93e255f 7686 refclk = i9xx_get_refclk(crtc_state, num_connectors);
79e53945 7687
e9fd1c02
JN
7688 /*
7689 * Returns a set of divisors for the desired target clock with
7690 * the given refclk, or FALSE. The returned values represent
7691 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7692 * 2) / p1 / p2.
7693 */
a93e255f
ACO
7694 limit = intel_limit(crtc_state, refclk);
7695 ok = dev_priv->display.find_dpll(limit, crtc_state,
190f68c5 7696 crtc_state->port_clock,
e9fd1c02 7697 refclk, NULL, &clock);
f2335330 7698 if (!ok) {
e9fd1c02
JN
7699 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7700 return -EINVAL;
7701 }
79e53945 7702
f2335330
JN
7703 if (is_lvds && dev_priv->lvds_downclock_avail) {
7704 /*
7705 * Ensure we match the reduced clock's P to the target
7706 * clock. If the clocks don't match, we can't switch
7707 * the display clock by using the FP0/FP1. In such case
7708 * we will disable the LVDS downclock feature.
7709 */
7710 has_reduced_clock =
a93e255f 7711 dev_priv->display.find_dpll(limit, crtc_state,
f2335330
JN
7712 dev_priv->lvds_downclock,
7713 refclk, &clock,
7714 &reduced_clock);
7715 }
7716 /* Compat-code for transition, will disappear. */
190f68c5
ACO
7717 crtc_state->dpll.n = clock.n;
7718 crtc_state->dpll.m1 = clock.m1;
7719 crtc_state->dpll.m2 = clock.m2;
7720 crtc_state->dpll.p1 = clock.p1;
7721 crtc_state->dpll.p2 = clock.p2;
f47709a9 7722 }
7026d4ac 7723
e9fd1c02 7724 if (IS_GEN2(dev)) {
190f68c5 7725 i8xx_update_pll(crtc, crtc_state,
2a8f64ca
VP
7726 has_reduced_clock ? &reduced_clock : NULL,
7727 num_connectors);
9d556c99 7728 } else if (IS_CHERRYVIEW(dev)) {
190f68c5 7729 chv_update_pll(crtc, crtc_state);
e9fd1c02 7730 } else if (IS_VALLEYVIEW(dev)) {
190f68c5 7731 vlv_update_pll(crtc, crtc_state);
e9fd1c02 7732 } else {
190f68c5 7733 i9xx_update_pll(crtc, crtc_state,
eb1cbe48 7734 has_reduced_clock ? &reduced_clock : NULL,
eba905b2 7735 num_connectors);
e9fd1c02 7736 }
79e53945 7737
c8f7a0db 7738 return 0;
f564048e
EA
7739}
7740
2fa2fe9a 7741static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5cec258b 7742 struct intel_crtc_state *pipe_config)
2fa2fe9a
DV
7743{
7744 struct drm_device *dev = crtc->base.dev;
7745 struct drm_i915_private *dev_priv = dev->dev_private;
7746 uint32_t tmp;
7747
dc9e7dec
VS
7748 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7749 return;
7750
2fa2fe9a 7751 tmp = I915_READ(PFIT_CONTROL);
06922821
DV
7752 if (!(tmp & PFIT_ENABLE))
7753 return;
2fa2fe9a 7754
06922821 7755 /* Check whether the pfit is attached to our pipe. */
2fa2fe9a
DV
7756 if (INTEL_INFO(dev)->gen < 4) {
7757 if (crtc->pipe != PIPE_B)
7758 return;
2fa2fe9a
DV
7759 } else {
7760 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7761 return;
7762 }
7763
06922821 7764 pipe_config->gmch_pfit.control = tmp;
2fa2fe9a
DV
7765 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7766 if (INTEL_INFO(dev)->gen < 5)
7767 pipe_config->gmch_pfit.lvds_border_bits =
7768 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7769}
7770
acbec814 7771static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 7772 struct intel_crtc_state *pipe_config)
acbec814
JB
7773{
7774 struct drm_device *dev = crtc->base.dev;
7775 struct drm_i915_private *dev_priv = dev->dev_private;
7776 int pipe = pipe_config->cpu_transcoder;
7777 intel_clock_t clock;
7778 u32 mdiv;
662c6ecb 7779 int refclk = 100000;
acbec814 7780
f573de5a
SK
7781 /* In case of MIPI DPLL will not even be used */
7782 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
7783 return;
7784
a580516d 7785 mutex_lock(&dev_priv->sb_lock);
ab3c759a 7786 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
a580516d 7787 mutex_unlock(&dev_priv->sb_lock);
acbec814
JB
7788
7789 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7790 clock.m2 = mdiv & DPIO_M2DIV_MASK;
7791 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7792 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7793 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7794
f646628b 7795 vlv_clock(refclk, &clock);
acbec814 7796
f646628b
VS
7797 /* clock.dot is the fast clock */
7798 pipe_config->port_clock = clock.dot / 5;
acbec814
JB
7799}
7800
5724dbd1
DL
7801static void
7802i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7803 struct intel_initial_plane_config *plane_config)
1ad292b5
JB
7804{
7805 struct drm_device *dev = crtc->base.dev;
7806 struct drm_i915_private *dev_priv = dev->dev_private;
7807 u32 val, base, offset;
7808 int pipe = crtc->pipe, plane = crtc->plane;
7809 int fourcc, pixel_format;
6761dd31 7810 unsigned int aligned_height;
b113d5ee 7811 struct drm_framebuffer *fb;
1b842c89 7812 struct intel_framebuffer *intel_fb;
1ad292b5 7813
42a7b088
DL
7814 val = I915_READ(DSPCNTR(plane));
7815 if (!(val & DISPLAY_PLANE_ENABLE))
7816 return;
7817
d9806c9f 7818 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 7819 if (!intel_fb) {
1ad292b5
JB
7820 DRM_DEBUG_KMS("failed to alloc fb\n");
7821 return;
7822 }
7823
1b842c89
DL
7824 fb = &intel_fb->base;
7825
18c5247e
DV
7826 if (INTEL_INFO(dev)->gen >= 4) {
7827 if (val & DISPPLANE_TILED) {
49af449b 7828 plane_config->tiling = I915_TILING_X;
18c5247e
DV
7829 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7830 }
7831 }
1ad292b5
JB
7832
7833 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
b35d63fa 7834 fourcc = i9xx_format_to_fourcc(pixel_format);
b113d5ee
DL
7835 fb->pixel_format = fourcc;
7836 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
1ad292b5
JB
7837
7838 if (INTEL_INFO(dev)->gen >= 4) {
49af449b 7839 if (plane_config->tiling)
1ad292b5
JB
7840 offset = I915_READ(DSPTILEOFF(plane));
7841 else
7842 offset = I915_READ(DSPLINOFF(plane));
7843 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7844 } else {
7845 base = I915_READ(DSPADDR(plane));
7846 }
7847 plane_config->base = base;
7848
7849 val = I915_READ(PIPESRC(pipe));
b113d5ee
DL
7850 fb->width = ((val >> 16) & 0xfff) + 1;
7851 fb->height = ((val >> 0) & 0xfff) + 1;
1ad292b5
JB
7852
7853 val = I915_READ(DSPSTRIDE(pipe));
b113d5ee 7854 fb->pitches[0] = val & 0xffffffc0;
1ad292b5 7855
b113d5ee 7856 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV
7857 fb->pixel_format,
7858 fb->modifier[0]);
1ad292b5 7859
f37b5c2b 7860 plane_config->size = fb->pitches[0] * aligned_height;
1ad292b5 7861
2844a921
DL
7862 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7863 pipe_name(pipe), plane, fb->width, fb->height,
7864 fb->bits_per_pixel, base, fb->pitches[0],
7865 plane_config->size);
1ad292b5 7866
2d14030b 7867 plane_config->fb = intel_fb;
1ad292b5
JB
7868}
7869
70b23a98 7870static void chv_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 7871 struct intel_crtc_state *pipe_config)
70b23a98
VS
7872{
7873 struct drm_device *dev = crtc->base.dev;
7874 struct drm_i915_private *dev_priv = dev->dev_private;
7875 int pipe = pipe_config->cpu_transcoder;
7876 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7877 intel_clock_t clock;
7878 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
7879 int refclk = 100000;
7880
a580516d 7881 mutex_lock(&dev_priv->sb_lock);
70b23a98
VS
7882 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
7883 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
7884 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
7885 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
a580516d 7886 mutex_unlock(&dev_priv->sb_lock);
70b23a98
VS
7887
7888 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
7889 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
7890 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
7891 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
7892 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
7893
7894 chv_clock(refclk, &clock);
7895
7896 /* clock.dot is the fast clock */
7897 pipe_config->port_clock = clock.dot / 5;
7898}
7899
0e8ffe1b 7900static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5cec258b 7901 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV
7902{
7903 struct drm_device *dev = crtc->base.dev;
7904 struct drm_i915_private *dev_priv = dev->dev_private;
7905 uint32_t tmp;
7906
f458ebbc
DV
7907 if (!intel_display_power_is_enabled(dev_priv,
7908 POWER_DOMAIN_PIPE(crtc->pipe)))
b5482bd0
ID
7909 return false;
7910
e143a21c 7911 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 7912 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 7913
0e8ffe1b
DV
7914 tmp = I915_READ(PIPECONF(crtc->pipe));
7915 if (!(tmp & PIPECONF_ENABLE))
7916 return false;
7917
42571aef
VS
7918 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
7919 switch (tmp & PIPECONF_BPC_MASK) {
7920 case PIPECONF_6BPC:
7921 pipe_config->pipe_bpp = 18;
7922 break;
7923 case PIPECONF_8BPC:
7924 pipe_config->pipe_bpp = 24;
7925 break;
7926 case PIPECONF_10BPC:
7927 pipe_config->pipe_bpp = 30;
7928 break;
7929 default:
7930 break;
7931 }
7932 }
7933
b5a9fa09
DV
7934 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
7935 pipe_config->limited_color_range = true;
7936
282740f7
VS
7937 if (INTEL_INFO(dev)->gen < 4)
7938 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
7939
1bd1bd80
DV
7940 intel_get_pipe_timings(crtc, pipe_config);
7941
2fa2fe9a
DV
7942 i9xx_get_pfit_config(crtc, pipe_config);
7943
6c49f241
DV
7944 if (INTEL_INFO(dev)->gen >= 4) {
7945 tmp = I915_READ(DPLL_MD(crtc->pipe));
7946 pipe_config->pixel_multiplier =
7947 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
7948 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8bcc2795 7949 pipe_config->dpll_hw_state.dpll_md = tmp;
6c49f241
DV
7950 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7951 tmp = I915_READ(DPLL(crtc->pipe));
7952 pipe_config->pixel_multiplier =
7953 ((tmp & SDVO_MULTIPLIER_MASK)
7954 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
7955 } else {
7956 /* Note that on i915G/GM the pixel multiplier is in the sdvo
7957 * port and will be fixed up in the encoder->get_config
7958 * function. */
7959 pipe_config->pixel_multiplier = 1;
7960 }
8bcc2795
DV
7961 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
7962 if (!IS_VALLEYVIEW(dev)) {
1c4e0274
VS
7963 /*
7964 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
7965 * on 830. Filter it out here so that we don't
7966 * report errors due to that.
7967 */
7968 if (IS_I830(dev))
7969 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
7970
8bcc2795
DV
7971 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
7972 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
165e901c
VS
7973 } else {
7974 /* Mask out read-only status bits. */
7975 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
7976 DPLL_PORTC_READY_MASK |
7977 DPLL_PORTB_READY_MASK);
8bcc2795 7978 }
6c49f241 7979
70b23a98
VS
7980 if (IS_CHERRYVIEW(dev))
7981 chv_crtc_clock_get(crtc, pipe_config);
7982 else if (IS_VALLEYVIEW(dev))
acbec814
JB
7983 vlv_crtc_clock_get(crtc, pipe_config);
7984 else
7985 i9xx_crtc_clock_get(crtc, pipe_config);
18442d08 7986
0e8ffe1b
DV
7987 return true;
7988}
7989
dde86e2d 7990static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB
7991{
7992 struct drm_i915_private *dev_priv = dev->dev_private;
13d83a67 7993 struct intel_encoder *encoder;
74cfd7ac 7994 u32 val, final;
13d83a67 7995 bool has_lvds = false;
199e5d79 7996 bool has_cpu_edp = false;
199e5d79 7997 bool has_panel = false;
99eb6a01
KP
7998 bool has_ck505 = false;
7999 bool can_ssc = false;
13d83a67
JB
8000
8001 /* We need to take the global config into account */
b2784e15 8002 for_each_intel_encoder(dev, encoder) {
199e5d79
KP
8003 switch (encoder->type) {
8004 case INTEL_OUTPUT_LVDS:
8005 has_panel = true;
8006 has_lvds = true;
8007 break;
8008 case INTEL_OUTPUT_EDP:
8009 has_panel = true;
2de6905f 8010 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
199e5d79
KP
8011 has_cpu_edp = true;
8012 break;
6847d71b
PZ
8013 default:
8014 break;
13d83a67
JB
8015 }
8016 }
8017
99eb6a01 8018 if (HAS_PCH_IBX(dev)) {
41aa3448 8019 has_ck505 = dev_priv->vbt.display_clock_mode;
99eb6a01
KP
8020 can_ssc = has_ck505;
8021 } else {
8022 has_ck505 = false;
8023 can_ssc = true;
8024 }
8025
2de6905f
ID
8026 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8027 has_panel, has_lvds, has_ck505);
13d83a67
JB
8028
8029 /* Ironlake: try to setup display ref clock before DPLL
8030 * enabling. This is only under driver's control after
8031 * PCH B stepping, previous chipset stepping should be
8032 * ignoring this setting.
8033 */
74cfd7ac
CW
8034 val = I915_READ(PCH_DREF_CONTROL);
8035
8036 /* As we must carefully and slowly disable/enable each source in turn,
8037 * compute the final state we want first and check if we need to
8038 * make any changes at all.
8039 */
8040 final = val;
8041 final &= ~DREF_NONSPREAD_SOURCE_MASK;
8042 if (has_ck505)
8043 final |= DREF_NONSPREAD_CK505_ENABLE;
8044 else
8045 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8046
8047 final &= ~DREF_SSC_SOURCE_MASK;
8048 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8049 final &= ~DREF_SSC1_ENABLE;
8050
8051 if (has_panel) {
8052 final |= DREF_SSC_SOURCE_ENABLE;
8053
8054 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8055 final |= DREF_SSC1_ENABLE;
8056
8057 if (has_cpu_edp) {
8058 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8059 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8060 else
8061 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8062 } else
8063 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8064 } else {
8065 final |= DREF_SSC_SOURCE_DISABLE;
8066 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8067 }
8068
8069 if (final == val)
8070 return;
8071
13d83a67 8072 /* Always enable nonspread source */
74cfd7ac 8073 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 8074
99eb6a01 8075 if (has_ck505)
74cfd7ac 8076 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 8077 else
74cfd7ac 8078 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 8079
199e5d79 8080 if (has_panel) {
74cfd7ac
CW
8081 val &= ~DREF_SSC_SOURCE_MASK;
8082 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 8083
199e5d79 8084 /* SSC must be turned on before enabling the CPU output */
99eb6a01 8085 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 8086 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 8087 val |= DREF_SSC1_ENABLE;
e77166b5 8088 } else
74cfd7ac 8089 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP
8090
8091 /* Get SSC going before enabling the outputs */
74cfd7ac 8092 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP
8093 POSTING_READ(PCH_DREF_CONTROL);
8094 udelay(200);
8095
74cfd7ac 8096 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB
8097
8098 /* Enable CPU source on CPU attached eDP */
199e5d79 8099 if (has_cpu_edp) {
99eb6a01 8100 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 8101 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 8102 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
eba905b2 8103 } else
74cfd7ac 8104 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 8105 } else
74cfd7ac 8106 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 8107
74cfd7ac 8108 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP
8109 POSTING_READ(PCH_DREF_CONTROL);
8110 udelay(200);
8111 } else {
8112 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8113
74cfd7ac 8114 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP
8115
8116 /* Turn off CPU output */
74cfd7ac 8117 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 8118
74cfd7ac 8119 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP
8120 POSTING_READ(PCH_DREF_CONTROL);
8121 udelay(200);
8122
8123 /* Turn off the SSC source */
74cfd7ac
CW
8124 val &= ~DREF_SSC_SOURCE_MASK;
8125 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP
8126
8127 /* Turn off SSC1 */
74cfd7ac 8128 val &= ~DREF_SSC1_ENABLE;
199e5d79 8129
74cfd7ac 8130 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB
8131 POSTING_READ(PCH_DREF_CONTROL);
8132 udelay(200);
8133 }
74cfd7ac
CW
8134
8135 BUG_ON(val != final);
13d83a67
JB
8136}
8137
f31f2d55 8138static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
dde86e2d 8139{
f31f2d55 8140 uint32_t tmp;
dde86e2d 8141
0ff066a9
PZ
8142 tmp = I915_READ(SOUTH_CHICKEN2);
8143 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8144 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 8145
0ff066a9
PZ
8146 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8147 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8148 DRM_ERROR("FDI mPHY reset assert timeout\n");
dde86e2d 8149
0ff066a9
PZ
8150 tmp = I915_READ(SOUTH_CHICKEN2);
8151 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8152 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 8153
0ff066a9
PZ
8154 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8155 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8156 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
f31f2d55
PZ
8157}
8158
8159/* WaMPhyProgramming:hsw */
8160static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8161{
8162 uint32_t tmp;
dde86e2d
PZ
8163
8164 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8165 tmp &= ~(0xFF << 24);
8166 tmp |= (0x12 << 24);
8167 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8168
dde86e2d
PZ
8169 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8170 tmp |= (1 << 11);
8171 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8172
8173 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8174 tmp |= (1 << 11);
8175 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8176
dde86e2d
PZ
8177 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8178 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8179 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8180
8181 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8182 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8183 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8184
0ff066a9
PZ
8185 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8186 tmp &= ~(7 << 13);
8187 tmp |= (5 << 13);
8188 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
dde86e2d 8189
0ff066a9
PZ
8190 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8191 tmp &= ~(7 << 13);
8192 tmp |= (5 << 13);
8193 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
dde86e2d
PZ
8194
8195 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8196 tmp &= ~0xFF;
8197 tmp |= 0x1C;
8198 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8199
8200 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8201 tmp &= ~0xFF;
8202 tmp |= 0x1C;
8203 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8204
8205 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8206 tmp &= ~(0xFF << 16);
8207 tmp |= (0x1C << 16);
8208 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8209
8210 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8211 tmp &= ~(0xFF << 16);
8212 tmp |= (0x1C << 16);
8213 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8214
0ff066a9
PZ
8215 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8216 tmp |= (1 << 27);
8217 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
dde86e2d 8218
0ff066a9
PZ
8219 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8220 tmp |= (1 << 27);
8221 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
dde86e2d 8222
0ff066a9
PZ
8223 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8224 tmp &= ~(0xF << 28);
8225 tmp |= (4 << 28);
8226 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
dde86e2d 8227
0ff066a9
PZ
8228 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8229 tmp &= ~(0xF << 28);
8230 tmp |= (4 << 28);
8231 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
f31f2d55
PZ
8232}
8233
2fa86a1f
PZ
8234/* Implements 3 different sequences from BSpec chapter "Display iCLK
8235 * Programming" based on the parameters passed:
8236 * - Sequence to enable CLKOUT_DP
8237 * - Sequence to enable CLKOUT_DP without spread
8238 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8239 */
8240static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8241 bool with_fdi)
f31f2d55
PZ
8242{
8243 struct drm_i915_private *dev_priv = dev->dev_private;
2fa86a1f
PZ
8244 uint32_t reg, tmp;
8245
8246 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8247 with_spread = true;
8248 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
8249 with_fdi, "LP PCH doesn't have FDI\n"))
8250 with_fdi = false;
f31f2d55 8251
a580516d 8252 mutex_lock(&dev_priv->sb_lock);
f31f2d55
PZ
8253
8254 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8255 tmp &= ~SBI_SSCCTL_DISABLE;
8256 tmp |= SBI_SSCCTL_PATHALT;
8257 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8258
8259 udelay(24);
8260
2fa86a1f
PZ
8261 if (with_spread) {
8262 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8263 tmp &= ~SBI_SSCCTL_PATHALT;
8264 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
f31f2d55 8265
2fa86a1f
PZ
8266 if (with_fdi) {
8267 lpt_reset_fdi_mphy(dev_priv);
8268 lpt_program_fdi_mphy(dev_priv);
8269 }
8270 }
dde86e2d 8271
2fa86a1f
PZ
8272 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8273 SBI_GEN0 : SBI_DBUFF0;
8274 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8275 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8276 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
c00db246 8277
a580516d 8278 mutex_unlock(&dev_priv->sb_lock);
dde86e2d
PZ
8279}
8280
47701c3b
PZ
8281/* Sequence to disable CLKOUT_DP */
8282static void lpt_disable_clkout_dp(struct drm_device *dev)
8283{
8284 struct drm_i915_private *dev_priv = dev->dev_private;
8285 uint32_t reg, tmp;
8286
a580516d 8287 mutex_lock(&dev_priv->sb_lock);
47701c3b
PZ
8288
8289 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8290 SBI_GEN0 : SBI_DBUFF0;
8291 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8292 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8293 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8294
8295 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8296 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8297 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8298 tmp |= SBI_SSCCTL_PATHALT;
8299 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8300 udelay(32);
8301 }
8302 tmp |= SBI_SSCCTL_DISABLE;
8303 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8304 }
8305
a580516d 8306 mutex_unlock(&dev_priv->sb_lock);
47701c3b
PZ
8307}
8308
bf8fa3d3
PZ
8309static void lpt_init_pch_refclk(struct drm_device *dev)
8310{
bf8fa3d3
PZ
8311 struct intel_encoder *encoder;
8312 bool has_vga = false;
8313
b2784e15 8314 for_each_intel_encoder(dev, encoder) {
bf8fa3d3
PZ
8315 switch (encoder->type) {
8316 case INTEL_OUTPUT_ANALOG:
8317 has_vga = true;
8318 break;
6847d71b
PZ
8319 default:
8320 break;
bf8fa3d3
PZ
8321 }
8322 }
8323
47701c3b
PZ
8324 if (has_vga)
8325 lpt_enable_clkout_dp(dev, true, true);
8326 else
8327 lpt_disable_clkout_dp(dev);
bf8fa3d3
PZ
8328}
8329
dde86e2d
PZ
8330/*
8331 * Initialize reference clocks when the driver loads
8332 */
8333void intel_init_pch_refclk(struct drm_device *dev)
8334{
8335 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8336 ironlake_init_pch_refclk(dev);
8337 else if (HAS_PCH_LPT(dev))
8338 lpt_init_pch_refclk(dev);
8339}
8340
55bb9992 8341static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
d9d444cb 8342{
55bb9992 8343 struct drm_device *dev = crtc_state->base.crtc->dev;
d9d444cb 8344 struct drm_i915_private *dev_priv = dev->dev_private;
55bb9992 8345 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 8346 struct drm_connector *connector;
55bb9992 8347 struct drm_connector_state *connector_state;
d9d444cb 8348 struct intel_encoder *encoder;
55bb9992 8349 int num_connectors = 0, i;
d9d444cb
JB
8350 bool is_lvds = false;
8351
da3ced29 8352 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO
8353 if (connector_state->crtc != crtc_state->base.crtc)
8354 continue;
8355
8356 encoder = to_intel_encoder(connector_state->best_encoder);
8357
d9d444cb
JB
8358 switch (encoder->type) {
8359 case INTEL_OUTPUT_LVDS:
8360 is_lvds = true;
8361 break;
6847d71b
PZ
8362 default:
8363 break;
d9d444cb
JB
8364 }
8365 num_connectors++;
8366 }
8367
8368 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
e91e941b 8369 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
41aa3448 8370 dev_priv->vbt.lvds_ssc_freq);
e91e941b 8371 return dev_priv->vbt.lvds_ssc_freq;
d9d444cb
JB
8372 }
8373
8374 return 120000;
8375}
8376
6ff93609 8377static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 8378{
c8203565 8379 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB
8380 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8381 int pipe = intel_crtc->pipe;
c8203565
PZ
8382 uint32_t val;
8383
78114071 8384 val = 0;
c8203565 8385
6e3c9717 8386 switch (intel_crtc->config->pipe_bpp) {
c8203565 8387 case 18:
dfd07d72 8388 val |= PIPECONF_6BPC;
c8203565
PZ
8389 break;
8390 case 24:
dfd07d72 8391 val |= PIPECONF_8BPC;
c8203565
PZ
8392 break;
8393 case 30:
dfd07d72 8394 val |= PIPECONF_10BPC;
c8203565
PZ
8395 break;
8396 case 36:
dfd07d72 8397 val |= PIPECONF_12BPC;
c8203565
PZ
8398 break;
8399 default:
cc769b62
PZ
8400 /* Case prevented by intel_choose_pipe_bpp_dither. */
8401 BUG();
c8203565
PZ
8402 }
8403
6e3c9717 8404 if (intel_crtc->config->dither)
c8203565
PZ
8405 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8406
6e3c9717 8407 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ
8408 val |= PIPECONF_INTERLACED_ILK;
8409 else
8410 val |= PIPECONF_PROGRESSIVE;
8411
6e3c9717 8412 if (intel_crtc->config->limited_color_range)
3685a8f3 8413 val |= PIPECONF_COLOR_RANGE_SELECT;
3685a8f3 8414
c8203565
PZ
8415 I915_WRITE(PIPECONF(pipe), val);
8416 POSTING_READ(PIPECONF(pipe));
8417}
8418
86d3efce
VS
8419/*
8420 * Set up the pipe CSC unit.
8421 *
8422 * Currently only full range RGB to limited range RGB conversion
8423 * is supported, but eventually this should handle various
8424 * RGB<->YCbCr scenarios as well.
8425 */
50f3b016 8426static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS
8427{
8428 struct drm_device *dev = crtc->dev;
8429 struct drm_i915_private *dev_priv = dev->dev_private;
8430 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8431 int pipe = intel_crtc->pipe;
8432 uint16_t coeff = 0x7800; /* 1.0 */
8433
8434 /*
8435 * TODO: Check what kind of values actually come out of the pipe
8436 * with these coeff/postoff values and adjust to get the best
8437 * accuracy. Perhaps we even need to take the bpc value into
8438 * consideration.
8439 */
8440
6e3c9717 8441 if (intel_crtc->config->limited_color_range)
86d3efce
VS
8442 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8443
8444 /*
8445 * GY/GU and RY/RU should be the other way around according
8446 * to BSpec, but reality doesn't agree. Just set them up in
8447 * a way that results in the correct picture.
8448 */
8449 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8450 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8451
8452 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8453 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8454
8455 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8456 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8457
8458 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8459 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8460 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8461
8462 if (INTEL_INFO(dev)->gen > 6) {
8463 uint16_t postoff = 0;
8464
6e3c9717 8465 if (intel_crtc->config->limited_color_range)
32cf0cb0 8466 postoff = (16 * (1 << 12) / 255) & 0x1fff;
86d3efce
VS
8467
8468 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8469 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8470 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8471
8472 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8473 } else {
8474 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8475
6e3c9717 8476 if (intel_crtc->config->limited_color_range)
86d3efce
VS
8477 mode |= CSC_BLACK_SCREEN_OFFSET;
8478
8479 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8480 }
8481}
8482
6ff93609 8483static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38 8484{
756f85cf
PZ
8485 struct drm_device *dev = crtc->dev;
8486 struct drm_i915_private *dev_priv = dev->dev_private;
ee2b0b38 8487 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
756f85cf 8488 enum pipe pipe = intel_crtc->pipe;
6e3c9717 8489 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
ee2b0b38
PZ
8490 uint32_t val;
8491
3eff4faa 8492 val = 0;
ee2b0b38 8493
6e3c9717 8494 if (IS_HASWELL(dev) && intel_crtc->config->dither)
ee2b0b38
PZ
8495 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8496
6e3c9717 8497 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ
8498 val |= PIPECONF_INTERLACED_ILK;
8499 else
8500 val |= PIPECONF_PROGRESSIVE;
8501
702e7a56
PZ
8502 I915_WRITE(PIPECONF(cpu_transcoder), val);
8503 POSTING_READ(PIPECONF(cpu_transcoder));
3eff4faa
DV
8504
8505 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8506 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
756f85cf 8507
3cdf122c 8508 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
756f85cf
PZ
8509 val = 0;
8510
6e3c9717 8511 switch (intel_crtc->config->pipe_bpp) {
756f85cf
PZ
8512 case 18:
8513 val |= PIPEMISC_DITHER_6_BPC;
8514 break;
8515 case 24:
8516 val |= PIPEMISC_DITHER_8_BPC;
8517 break;
8518 case 30:
8519 val |= PIPEMISC_DITHER_10_BPC;
8520 break;
8521 case 36:
8522 val |= PIPEMISC_DITHER_12_BPC;
8523 break;
8524 default:
8525 /* Case prevented by pipe_config_set_bpp. */
8526 BUG();
8527 }
8528
6e3c9717 8529 if (intel_crtc->config->dither)
756f85cf
PZ
8530 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8531
8532 I915_WRITE(PIPEMISC(pipe), val);
8533 }
ee2b0b38
PZ
8534}
8535
6591c6e4 8536static bool ironlake_compute_clocks(struct drm_crtc *crtc,
190f68c5 8537 struct intel_crtc_state *crtc_state,
6591c6e4
PZ
8538 intel_clock_t *clock,
8539 bool *has_reduced_clock,
8540 intel_clock_t *reduced_clock)
8541{
8542 struct drm_device *dev = crtc->dev;
8543 struct drm_i915_private *dev_priv = dev->dev_private;
6591c6e4 8544 int refclk;
d4906093 8545 const intel_limit_t *limit;
a16af721 8546 bool ret, is_lvds = false;
79e53945 8547
a93e255f 8548 is_lvds = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS);
79e53945 8549
55bb9992 8550 refclk = ironlake_get_refclk(crtc_state);
79e53945 8551
d4906093
ML
8552 /*
8553 * Returns a set of divisors for the desired target clock with the given
8554 * refclk, or FALSE. The returned values represent the clock equation:
8555 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8556 */
a93e255f
ACO
8557 limit = intel_limit(crtc_state, refclk);
8558 ret = dev_priv->display.find_dpll(limit, crtc_state,
190f68c5 8559 crtc_state->port_clock,
ee9300bb 8560 refclk, NULL, clock);
6591c6e4
PZ
8561 if (!ret)
8562 return false;
cda4b7d3 8563
ddc9003c 8564 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP
8565 /*
8566 * Ensure we match the reduced clock's P to the target clock.
8567 * If the clocks don't match, we can't switch the display clock
8568 * by using the FP0/FP1. In such case we will disable the LVDS
8569 * downclock feature.
8570 */
ee9300bb 8571 *has_reduced_clock =
a93e255f 8572 dev_priv->display.find_dpll(limit, crtc_state,
ee9300bb
DV
8573 dev_priv->lvds_downclock,
8574 refclk, clock,
8575 reduced_clock);
652c393a 8576 }
61e9653f 8577
6591c6e4
PZ
8578 return true;
8579}
8580
d4b1931c
PZ
8581int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8582{
8583 /*
8584 * Account for spread spectrum to avoid
8585 * oversubscribing the link. Max center spread
8586 * is 2.5%; use 5% for safety's sake.
8587 */
8588 u32 bps = target_clock * bpp * 21 / 20;
619d4d04 8589 return DIV_ROUND_UP(bps, link_bw * 8);
d4b1931c
PZ
8590}
8591
7429e9d4 8592static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6cf86a5e 8593{
7429e9d4 8594 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
f48d8f23
PZ
8595}
8596
de13a2e3 8597static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
190f68c5 8598 struct intel_crtc_state *crtc_state,
7429e9d4 8599 u32 *fp,
9a7c7890 8600 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 8601{
de13a2e3 8602 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB
8603 struct drm_device *dev = crtc->dev;
8604 struct drm_i915_private *dev_priv = dev->dev_private;
55bb9992 8605 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 8606 struct drm_connector *connector;
55bb9992
ACO
8607 struct drm_connector_state *connector_state;
8608 struct intel_encoder *encoder;
de13a2e3 8609 uint32_t dpll;
55bb9992 8610 int factor, num_connectors = 0, i;
09ede541 8611 bool is_lvds = false, is_sdvo = false;
79e53945 8612
da3ced29 8613 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO
8614 if (connector_state->crtc != crtc_state->base.crtc)
8615 continue;
8616
8617 encoder = to_intel_encoder(connector_state->best_encoder);
8618
8619 switch (encoder->type) {
79e53945
JB
8620 case INTEL_OUTPUT_LVDS:
8621 is_lvds = true;
8622 break;
8623 case INTEL_OUTPUT_SDVO:
7d57382e 8624 case INTEL_OUTPUT_HDMI:
79e53945 8625 is_sdvo = true;
79e53945 8626 break;
6847d71b
PZ
8627 default:
8628 break;
79e53945 8629 }
43565a06 8630
c751ce4f 8631 num_connectors++;
79e53945 8632 }
79e53945 8633
c1858123 8634 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA
8635 factor = 21;
8636 if (is_lvds) {
8637 if ((intel_panel_use_ssc(dev_priv) &&
e91e941b 8638 dev_priv->vbt.lvds_ssc_freq == 100000) ||
f0b44056 8639 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297 8640 factor = 25;
190f68c5 8641 } else if (crtc_state->sdvo_tv_clock)
8febb297 8642 factor = 20;
c1858123 8643
190f68c5 8644 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
7d0ac5b7 8645 *fp |= FP_CB_TUNE;
2c07245f 8646
9a7c7890
DV
8647 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8648 *fp2 |= FP_CB_TUNE;
8649
5eddb70b 8650 dpll = 0;
2c07245f 8651
a07d6787
EA
8652 if (is_lvds)
8653 dpll |= DPLLB_MODE_LVDS;
8654 else
8655 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f 8656
190f68c5 8657 dpll |= (crtc_state->pixel_multiplier - 1)
ef1b460d 8658 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
198a037f
DV
8659
8660 if (is_sdvo)
4a33e48d 8661 dpll |= DPLL_SDVO_HIGH_SPEED;
190f68c5 8662 if (crtc_state->has_dp_encoder)
4a33e48d 8663 dpll |= DPLL_SDVO_HIGH_SPEED;
79e53945 8664
a07d6787 8665 /* compute bitmask from p1 value */
190f68c5 8666 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 8667 /* also FPA1 */
190f68c5 8668 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 8669
190f68c5 8670 switch (crtc_state->dpll.p2) {
a07d6787
EA
8671 case 5:
8672 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8673 break;
8674 case 7:
8675 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8676 break;
8677 case 10:
8678 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8679 break;
8680 case 14:
8681 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8682 break;
79e53945
JB
8683 }
8684
b4c09f3b 8685 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 8686 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB
8687 else
8688 dpll |= PLL_REF_INPUT_DREFCLK;
8689
959e16d6 8690 return dpll | DPLL_VCO_ENABLE;
de13a2e3
PZ
8691}
8692
190f68c5
ACO
8693static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8694 struct intel_crtc_state *crtc_state)
de13a2e3 8695{
c7653199 8696 struct drm_device *dev = crtc->base.dev;
de13a2e3 8697 intel_clock_t clock, reduced_clock;
cbbab5bd 8698 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 8699 bool ok, has_reduced_clock = false;
8b47047b 8700 bool is_lvds = false;
e2b78267 8701 struct intel_shared_dpll *pll;
de13a2e3 8702
dd3cd74a
ACO
8703 memset(&crtc_state->dpll_hw_state, 0,
8704 sizeof(crtc_state->dpll_hw_state));
8705
409ee761 8706 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
79e53945 8707
5dc5298b
PZ
8708 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8709 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 8710
190f68c5 8711 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
de13a2e3 8712 &has_reduced_clock, &reduced_clock);
190f68c5 8713 if (!ok && !crtc_state->clock_set) {
de13a2e3
PZ
8714 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8715 return -EINVAL;
79e53945 8716 }
f47709a9 8717 /* Compat-code for transition, will disappear. */
190f68c5
ACO
8718 if (!crtc_state->clock_set) {
8719 crtc_state->dpll.n = clock.n;
8720 crtc_state->dpll.m1 = clock.m1;
8721 crtc_state->dpll.m2 = clock.m2;
8722 crtc_state->dpll.p1 = clock.p1;
8723 crtc_state->dpll.p2 = clock.p2;
f47709a9 8724 }
79e53945 8725
5dc5298b 8726 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
190f68c5
ACO
8727 if (crtc_state->has_pch_encoder) {
8728 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
cbbab5bd 8729 if (has_reduced_clock)
7429e9d4 8730 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 8731
190f68c5 8732 dpll = ironlake_compute_dpll(crtc, crtc_state,
cbbab5bd
DV
8733 &fp, &reduced_clock,
8734 has_reduced_clock ? &fp2 : NULL);
8735
190f68c5
ACO
8736 crtc_state->dpll_hw_state.dpll = dpll;
8737 crtc_state->dpll_hw_state.fp0 = fp;
66e985c0 8738 if (has_reduced_clock)
190f68c5 8739 crtc_state->dpll_hw_state.fp1 = fp2;
66e985c0 8740 else
190f68c5 8741 crtc_state->dpll_hw_state.fp1 = fp;
66e985c0 8742
190f68c5 8743 pll = intel_get_shared_dpll(crtc, crtc_state);
ee7b9f93 8744 if (pll == NULL) {
84f44ce7 8745 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
c7653199 8746 pipe_name(crtc->pipe));
4b645f14
JB
8747 return -EINVAL;
8748 }
3fb37703 8749 }
79e53945 8750
ab585dea 8751 if (is_lvds && has_reduced_clock)
c7653199 8752 crtc->lowfreq_avail = true;
bcd644e0 8753 else
c7653199 8754 crtc->lowfreq_avail = false;
e2b78267 8755
c8f7a0db 8756 return 0;
79e53945
JB
8757}
8758
eb14cb74
VS
8759static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8760 struct intel_link_m_n *m_n)
8761{
8762 struct drm_device *dev = crtc->base.dev;
8763 struct drm_i915_private *dev_priv = dev->dev_private;
8764 enum pipe pipe = crtc->pipe;
8765
8766 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8767 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8768 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8769 & ~TU_SIZE_MASK;
8770 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8771 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8772 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8773}
8774
8775static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8776 enum transcoder transcoder,
b95af8be
VK
8777 struct intel_link_m_n *m_n,
8778 struct intel_link_m_n *m2_n2)
72419203
DV
8779{
8780 struct drm_device *dev = crtc->base.dev;
8781 struct drm_i915_private *dev_priv = dev->dev_private;
eb14cb74 8782 enum pipe pipe = crtc->pipe;
72419203 8783
eb14cb74
VS
8784 if (INTEL_INFO(dev)->gen >= 5) {
8785 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8786 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8787 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8788 & ~TU_SIZE_MASK;
8789 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8790 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8791 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
b95af8be
VK
8792 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8793 * gen < 8) and if DRRS is supported (to make sure the
8794 * registers are not unnecessarily read).
8795 */
8796 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
6e3c9717 8797 crtc->config->has_drrs) {
b95af8be
VK
8798 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8799 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8800 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8801 & ~TU_SIZE_MASK;
8802 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8803 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8804 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8805 }
eb14cb74
VS
8806 } else {
8807 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8808 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8809 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8810 & ~TU_SIZE_MASK;
8811 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8812 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8813 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8814 }
8815}
8816
8817void intel_dp_get_m_n(struct intel_crtc *crtc,
5cec258b 8818 struct intel_crtc_state *pipe_config)
eb14cb74 8819{
681a8504 8820 if (pipe_config->has_pch_encoder)
eb14cb74
VS
8821 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8822 else
8823 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
b95af8be
VK
8824 &pipe_config->dp_m_n,
8825 &pipe_config->dp_m2_n2);
eb14cb74 8826}
72419203 8827
eb14cb74 8828static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5cec258b 8829 struct intel_crtc_state *pipe_config)
eb14cb74
VS
8830{
8831 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
b95af8be 8832 &pipe_config->fdi_m_n, NULL);
72419203
DV
8833}
8834
bd2e244f 8835static void skylake_get_pfit_config(struct intel_crtc *crtc,
5cec258b 8836 struct intel_crtc_state *pipe_config)
bd2e244f
JB
8837{
8838 struct drm_device *dev = crtc->base.dev;
8839 struct drm_i915_private *dev_priv = dev->dev_private;
a1b2278e
CK
8840 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8841 uint32_t ps_ctrl = 0;
8842 int id = -1;
8843 int i;
bd2e244f 8844
a1b2278e
CK
8845 /* find scaler attached to this pipe */
8846 for (i = 0; i < crtc->num_scalers; i++) {
8847 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
8848 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
8849 id = i;
8850 pipe_config->pch_pfit.enabled = true;
8851 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
8852 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
8853 break;
8854 }
8855 }
bd2e244f 8856
a1b2278e
CK
8857 scaler_state->scaler_id = id;
8858 if (id >= 0) {
8859 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
8860 } else {
8861 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
bd2e244f
JB
8862 }
8863}
8864
5724dbd1
DL
8865static void
8866skylake_get_initial_plane_config(struct intel_crtc *crtc,
8867 struct intel_initial_plane_config *plane_config)
bc8d7dff
DL
8868{
8869 struct drm_device *dev = crtc->base.dev;
8870 struct drm_i915_private *dev_priv = dev->dev_private;
40f46283 8871 u32 val, base, offset, stride_mult, tiling;
bc8d7dff
DL
8872 int pipe = crtc->pipe;
8873 int fourcc, pixel_format;
6761dd31 8874 unsigned int aligned_height;
bc8d7dff 8875 struct drm_framebuffer *fb;
1b842c89 8876 struct intel_framebuffer *intel_fb;
bc8d7dff 8877
d9806c9f 8878 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 8879 if (!intel_fb) {
bc8d7dff
DL
8880 DRM_DEBUG_KMS("failed to alloc fb\n");
8881 return;
8882 }
8883
1b842c89
DL
8884 fb = &intel_fb->base;
8885
bc8d7dff 8886 val = I915_READ(PLANE_CTL(pipe, 0));
42a7b088
DL
8887 if (!(val & PLANE_CTL_ENABLE))
8888 goto error;
8889
bc8d7dff
DL
8890 pixel_format = val & PLANE_CTL_FORMAT_MASK;
8891 fourcc = skl_format_to_fourcc(pixel_format,
8892 val & PLANE_CTL_ORDER_RGBX,
8893 val & PLANE_CTL_ALPHA_MASK);
8894 fb->pixel_format = fourcc;
8895 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8896
40f46283
DL
8897 tiling = val & PLANE_CTL_TILED_MASK;
8898 switch (tiling) {
8899 case PLANE_CTL_TILED_LINEAR:
8900 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
8901 break;
8902 case PLANE_CTL_TILED_X:
8903 plane_config->tiling = I915_TILING_X;
8904 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8905 break;
8906 case PLANE_CTL_TILED_Y:
8907 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
8908 break;
8909 case PLANE_CTL_TILED_YF:
8910 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
8911 break;
8912 default:
8913 MISSING_CASE(tiling);
8914 goto error;
8915 }
8916
bc8d7dff
DL
8917 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
8918 plane_config->base = base;
8919
8920 offset = I915_READ(PLANE_OFFSET(pipe, 0));
8921
8922 val = I915_READ(PLANE_SIZE(pipe, 0));
8923 fb->height = ((val >> 16) & 0xfff) + 1;
8924 fb->width = ((val >> 0) & 0x1fff) + 1;
8925
8926 val = I915_READ(PLANE_STRIDE(pipe, 0));
40f46283
DL
8927 stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
8928 fb->pixel_format);
bc8d7dff
DL
8929 fb->pitches[0] = (val & 0x3ff) * stride_mult;
8930
8931 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV
8932 fb->pixel_format,
8933 fb->modifier[0]);
bc8d7dff 8934
f37b5c2b 8935 plane_config->size = fb->pitches[0] * aligned_height;
bc8d7dff
DL
8936
8937 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8938 pipe_name(pipe), fb->width, fb->height,
8939 fb->bits_per_pixel, base, fb->pitches[0],
8940 plane_config->size);
8941
2d14030b 8942 plane_config->fb = intel_fb;
bc8d7dff
DL
8943 return;
8944
8945error:
8946 kfree(fb);
8947}
8948
2fa2fe9a 8949static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5cec258b 8950 struct intel_crtc_state *pipe_config)
2fa2fe9a
DV
8951{
8952 struct drm_device *dev = crtc->base.dev;
8953 struct drm_i915_private *dev_priv = dev->dev_private;
8954 uint32_t tmp;
8955
8956 tmp = I915_READ(PF_CTL(crtc->pipe));
8957
8958 if (tmp & PF_ENABLE) {
fd4daa9c 8959 pipe_config->pch_pfit.enabled = true;
2fa2fe9a
DV
8960 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
8961 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
cb8b2a30
DV
8962
8963 /* We currently do not free assignements of panel fitters on
8964 * ivb/hsw (since we don't use the higher upscaling modes which
8965 * differentiates them) so just WARN about this case for now. */
8966 if (IS_GEN7(dev)) {
8967 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
8968 PF_PIPE_SEL_IVB(crtc->pipe));
8969 }
2fa2fe9a 8970 }
79e53945
JB
8971}
8972
5724dbd1
DL
8973static void
8974ironlake_get_initial_plane_config(struct intel_crtc *crtc,
8975 struct intel_initial_plane_config *plane_config)
4c6baa59
JB
8976{
8977 struct drm_device *dev = crtc->base.dev;
8978 struct drm_i915_private *dev_priv = dev->dev_private;
8979 u32 val, base, offset;
aeee5a49 8980 int pipe = crtc->pipe;
4c6baa59 8981 int fourcc, pixel_format;
6761dd31 8982 unsigned int aligned_height;
b113d5ee 8983 struct drm_framebuffer *fb;
1b842c89 8984 struct intel_framebuffer *intel_fb;
4c6baa59 8985
42a7b088
DL
8986 val = I915_READ(DSPCNTR(pipe));
8987 if (!(val & DISPLAY_PLANE_ENABLE))
8988 return;
8989
d9806c9f 8990 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 8991 if (!intel_fb) {
4c6baa59
JB
8992 DRM_DEBUG_KMS("failed to alloc fb\n");
8993 return;
8994 }
8995
1b842c89
DL
8996 fb = &intel_fb->base;
8997
18c5247e
DV
8998 if (INTEL_INFO(dev)->gen >= 4) {
8999 if (val & DISPPLANE_TILED) {
49af449b 9000 plane_config->tiling = I915_TILING_X;
18c5247e
DV
9001 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9002 }
9003 }
4c6baa59
JB
9004
9005 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
b35d63fa 9006 fourcc = i9xx_format_to_fourcc(pixel_format);
b113d5ee
DL
9007 fb->pixel_format = fourcc;
9008 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
4c6baa59 9009
aeee5a49 9010 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
4c6baa59 9011 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
aeee5a49 9012 offset = I915_READ(DSPOFFSET(pipe));
4c6baa59 9013 } else {
49af449b 9014 if (plane_config->tiling)
aeee5a49 9015 offset = I915_READ(DSPTILEOFF(pipe));
4c6baa59 9016 else
aeee5a49 9017 offset = I915_READ(DSPLINOFF(pipe));
4c6baa59
JB
9018 }
9019 plane_config->base = base;
9020
9021 val = I915_READ(PIPESRC(pipe));
b113d5ee
DL
9022 fb->width = ((val >> 16) & 0xfff) + 1;
9023 fb->height = ((val >> 0) & 0xfff) + 1;
4c6baa59
JB
9024
9025 val = I915_READ(DSPSTRIDE(pipe));
b113d5ee 9026 fb->pitches[0] = val & 0xffffffc0;
4c6baa59 9027
b113d5ee 9028 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV
9029 fb->pixel_format,
9030 fb->modifier[0]);
4c6baa59 9031
f37b5c2b 9032 plane_config->size = fb->pitches[0] * aligned_height;
4c6baa59 9033
2844a921
DL
9034 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9035 pipe_name(pipe), fb->width, fb->height,
9036 fb->bits_per_pixel, base, fb->pitches[0],
9037 plane_config->size);
b113d5ee 9038
2d14030b 9039 plane_config->fb = intel_fb;
4c6baa59
JB
9040}
9041
0e8ffe1b 9042static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5cec258b 9043 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV
9044{
9045 struct drm_device *dev = crtc->base.dev;
9046 struct drm_i915_private *dev_priv = dev->dev_private;
9047 uint32_t tmp;
9048
f458ebbc
DV
9049 if (!intel_display_power_is_enabled(dev_priv,
9050 POWER_DOMAIN_PIPE(crtc->pipe)))
930e8c9e
PZ
9051 return false;
9052
e143a21c 9053 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 9054 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 9055
0e8ffe1b
DV
9056 tmp = I915_READ(PIPECONF(crtc->pipe));
9057 if (!(tmp & PIPECONF_ENABLE))
9058 return false;
9059
42571aef
VS
9060 switch (tmp & PIPECONF_BPC_MASK) {
9061 case PIPECONF_6BPC:
9062 pipe_config->pipe_bpp = 18;
9063 break;
9064 case PIPECONF_8BPC:
9065 pipe_config->pipe_bpp = 24;
9066 break;
9067 case PIPECONF_10BPC:
9068 pipe_config->pipe_bpp = 30;
9069 break;
9070 case PIPECONF_12BPC:
9071 pipe_config->pipe_bpp = 36;
9072 break;
9073 default:
9074 break;
9075 }
9076
b5a9fa09
DV
9077 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9078 pipe_config->limited_color_range = true;
9079
ab9412ba 9080 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
66e985c0
DV
9081 struct intel_shared_dpll *pll;
9082
88adfff1
DV
9083 pipe_config->has_pch_encoder = true;
9084
627eb5a3
DV
9085 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9086 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9087 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV
9088
9089 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6c49f241 9090
c0d43d62 9091 if (HAS_PCH_IBX(dev_priv->dev)) {
d94ab068
DV
9092 pipe_config->shared_dpll =
9093 (enum intel_dpll_id) crtc->pipe;
c0d43d62
DV
9094 } else {
9095 tmp = I915_READ(PCH_DPLL_SEL);
9096 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9097 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
9098 else
9099 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
9100 }
66e985c0
DV
9101
9102 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9103
9104 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9105 &pipe_config->dpll_hw_state));
c93f54cf
DV
9106
9107 tmp = pipe_config->dpll_hw_state.dpll;
9108 pipe_config->pixel_multiplier =
9109 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9110 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
18442d08
VS
9111
9112 ironlake_pch_clock_get(crtc, pipe_config);
6c49f241
DV
9113 } else {
9114 pipe_config->pixel_multiplier = 1;
627eb5a3
DV
9115 }
9116
1bd1bd80
DV
9117 intel_get_pipe_timings(crtc, pipe_config);
9118
2fa2fe9a
DV
9119 ironlake_get_pfit_config(crtc, pipe_config);
9120
0e8ffe1b
DV
9121 return true;
9122}
9123
be256dc7
PZ
9124static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9125{
9126 struct drm_device *dev = dev_priv->dev;
be256dc7 9127 struct intel_crtc *crtc;
be256dc7 9128
d3fcc808 9129 for_each_intel_crtc(dev, crtc)
e2c719b7 9130 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
be256dc7
PZ
9131 pipe_name(crtc->pipe));
9132
e2c719b7
RC
9133 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9134 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9135 I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9136 I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9137 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9138 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
be256dc7 9139 "CPU PWM1 enabled\n");
c5107b87 9140 if (IS_HASWELL(dev))
e2c719b7 9141 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
c5107b87 9142 "CPU PWM2 enabled\n");
e2c719b7 9143 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
be256dc7 9144 "PCH PWM1 enabled\n");
e2c719b7 9145 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
be256dc7 9146 "Utility pin enabled\n");
e2c719b7 9147 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
be256dc7 9148
9926ada1
PZ
9149 /*
9150 * In theory we can still leave IRQs enabled, as long as only the HPD
9151 * interrupts remain enabled. We used to check for that, but since it's
9152 * gen-specific and since we only disable LCPLL after we fully disable
9153 * the interrupts, the check below should be enough.
9154 */
e2c719b7 9155 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
be256dc7
PZ
9156}
9157
9ccd5aeb
PZ
9158static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9159{
9160 struct drm_device *dev = dev_priv->dev;
9161
9162 if (IS_HASWELL(dev))
9163 return I915_READ(D_COMP_HSW);
9164 else
9165 return I915_READ(D_COMP_BDW);
9166}
9167
3c4c9b81
PZ
9168static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9169{
9170 struct drm_device *dev = dev_priv->dev;
9171
9172 if (IS_HASWELL(dev)) {
9173 mutex_lock(&dev_priv->rps.hw_lock);
9174 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9175 val))
f475dadf 9176 DRM_ERROR("Failed to write to D_COMP\n");
3c4c9b81
PZ
9177 mutex_unlock(&dev_priv->rps.hw_lock);
9178 } else {
9ccd5aeb
PZ
9179 I915_WRITE(D_COMP_BDW, val);
9180 POSTING_READ(D_COMP_BDW);
3c4c9b81 9181 }
be256dc7
PZ
9182}
9183
9184/*
9185 * This function implements pieces of two sequences from BSpec:
9186 * - Sequence for display software to disable LCPLL
9187 * - Sequence for display software to allow package C8+
9188 * The steps implemented here are just the steps that actually touch the LCPLL
9189 * register. Callers should take care of disabling all the display engine
9190 * functions, doing the mode unset, fixing interrupts, etc.
9191 */
6ff58d53
PZ
9192static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9193 bool switch_to_fclk, bool allow_power_down)
be256dc7
PZ
9194{
9195 uint32_t val;
9196
9197 assert_can_disable_lcpll(dev_priv);
9198
9199 val = I915_READ(LCPLL_CTL);
9200
9201 if (switch_to_fclk) {
9202 val |= LCPLL_CD_SOURCE_FCLK;
9203 I915_WRITE(LCPLL_CTL, val);
9204
9205 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9206 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9207 DRM_ERROR("Switching to FCLK failed\n");
9208
9209 val = I915_READ(LCPLL_CTL);
9210 }
9211
9212 val |= LCPLL_PLL_DISABLE;
9213 I915_WRITE(LCPLL_CTL, val);
9214 POSTING_READ(LCPLL_CTL);
9215
9216 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9217 DRM_ERROR("LCPLL still locked\n");
9218
9ccd5aeb 9219 val = hsw_read_dcomp(dev_priv);
be256dc7 9220 val |= D_COMP_COMP_DISABLE;
3c4c9b81 9221 hsw_write_dcomp(dev_priv, val);
be256dc7
PZ
9222 ndelay(100);
9223
9ccd5aeb
PZ
9224 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9225 1))
be256dc7
PZ
9226 DRM_ERROR("D_COMP RCOMP still in progress\n");
9227
9228 if (allow_power_down) {
9229 val = I915_READ(LCPLL_CTL);
9230 val |= LCPLL_POWER_DOWN_ALLOW;
9231 I915_WRITE(LCPLL_CTL, val);
9232 POSTING_READ(LCPLL_CTL);
9233 }
9234}
9235
9236/*
9237 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9238 * source.
9239 */
6ff58d53 9240static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
be256dc7
PZ
9241{
9242 uint32_t val;
9243
9244 val = I915_READ(LCPLL_CTL);
9245
9246 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9247 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9248 return;
9249
a8a8bd54
PZ
9250 /*
9251 * Make sure we're not on PC8 state before disabling PC8, otherwise
9252 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
a8a8bd54 9253 */
59bad947 9254 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
215733fa 9255
be256dc7
PZ
9256 if (val & LCPLL_POWER_DOWN_ALLOW) {
9257 val &= ~LCPLL_POWER_DOWN_ALLOW;
9258 I915_WRITE(LCPLL_CTL, val);
35d8f2eb 9259 POSTING_READ(LCPLL_CTL);
be256dc7
PZ
9260 }
9261
9ccd5aeb 9262 val = hsw_read_dcomp(dev_priv);
be256dc7
PZ
9263 val |= D_COMP_COMP_FORCE;
9264 val &= ~D_COMP_COMP_DISABLE;
3c4c9b81 9265 hsw_write_dcomp(dev_priv, val);
be256dc7
PZ
9266
9267 val = I915_READ(LCPLL_CTL);
9268 val &= ~LCPLL_PLL_DISABLE;
9269 I915_WRITE(LCPLL_CTL, val);
9270
9271 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9272 DRM_ERROR("LCPLL not locked yet\n");
9273
9274 if (val & LCPLL_CD_SOURCE_FCLK) {
9275 val = I915_READ(LCPLL_CTL);
9276 val &= ~LCPLL_CD_SOURCE_FCLK;
9277 I915_WRITE(LCPLL_CTL, val);
9278
9279 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9280 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9281 DRM_ERROR("Switching back to LCPLL failed\n");
9282 }
215733fa 9283
59bad947 9284 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
be256dc7
PZ
9285}
9286
765dab67
PZ
9287/*
9288 * Package states C8 and deeper are really deep PC states that can only be
9289 * reached when all the devices on the system allow it, so even if the graphics
9290 * device allows PC8+, it doesn't mean the system will actually get to these
9291 * states. Our driver only allows PC8+ when going into runtime PM.
9292 *
9293 * The requirements for PC8+ are that all the outputs are disabled, the power
9294 * well is disabled and most interrupts are disabled, and these are also
9295 * requirements for runtime PM. When these conditions are met, we manually do
9296 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9297 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9298 * hang the machine.
9299 *
9300 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9301 * the state of some registers, so when we come back from PC8+ we need to
9302 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9303 * need to take care of the registers kept by RC6. Notice that this happens even
9304 * if we don't put the device in PCI D3 state (which is what currently happens
9305 * because of the runtime PM support).
9306 *
9307 * For more, read "Display Sequences for Package C8" on the hardware
9308 * documentation.
9309 */
a14cb6fc 9310void hsw_enable_pc8(struct drm_i915_private *dev_priv)
c67a470b 9311{
c67a470b
PZ
9312 struct drm_device *dev = dev_priv->dev;
9313 uint32_t val;
9314
c67a470b
PZ
9315 DRM_DEBUG_KMS("Enabling package C8+\n");
9316
c67a470b
PZ
9317 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9318 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9319 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9320 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9321 }
9322
9323 lpt_disable_clkout_dp(dev);
c67a470b
PZ
9324 hsw_disable_lcpll(dev_priv, true, true);
9325}
9326
a14cb6fc 9327void hsw_disable_pc8(struct drm_i915_private *dev_priv)
c67a470b
PZ
9328{
9329 struct drm_device *dev = dev_priv->dev;
9330 uint32_t val;
9331
c67a470b
PZ
9332 DRM_DEBUG_KMS("Disabling package C8+\n");
9333
9334 hsw_restore_lcpll(dev_priv);
c67a470b
PZ
9335 lpt_init_pch_refclk(dev);
9336
9337 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9338 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9339 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9340 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9341 }
9342
9343 intel_prepare_ddi(dev);
c67a470b
PZ
9344}
9345
a821fc46 9346static void broxton_modeset_global_resources(struct drm_atomic_state *old_state)
f8437dd1 9347{
a821fc46 9348 struct drm_device *dev = old_state->dev;
f8437dd1 9349 struct drm_i915_private *dev_priv = dev->dev_private;
a821fc46 9350 int max_pixclk = intel_mode_max_pixclk(dev, NULL);
f8437dd1
VK
9351 int req_cdclk;
9352
9353 /* see the comment in valleyview_modeset_global_resources */
9354 if (WARN_ON(max_pixclk < 0))
9355 return;
9356
9357 req_cdclk = broxton_calc_cdclk(dev_priv, max_pixclk);
9358
9359 if (req_cdclk != dev_priv->cdclk_freq)
9360 broxton_set_cdclk(dev, req_cdclk);
9361}
9362
190f68c5
ACO
9363static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9364 struct intel_crtc_state *crtc_state)
09b4ddf9 9365{
190f68c5 9366 if (!intel_ddi_pll_select(crtc, crtc_state))
6441ab5f 9367 return -EINVAL;
716c2e55 9368
c7653199 9369 crtc->lowfreq_avail = false;
644cef34 9370
c8f7a0db 9371 return 0;
79e53945
JB
9372}
9373
3760b59c
S
9374static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9375 enum port port,
9376 struct intel_crtc_state *pipe_config)
9377{
9378 switch (port) {
9379 case PORT_A:
9380 pipe_config->ddi_pll_sel = SKL_DPLL0;
9381 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9382 break;
9383 case PORT_B:
9384 pipe_config->ddi_pll_sel = SKL_DPLL1;
9385 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9386 break;
9387 case PORT_C:
9388 pipe_config->ddi_pll_sel = SKL_DPLL2;
9389 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9390 break;
9391 default:
9392 DRM_ERROR("Incorrect port type\n");
9393 }
9394}
9395
96b7dfb7
S
9396static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9397 enum port port,
5cec258b 9398 struct intel_crtc_state *pipe_config)
96b7dfb7 9399{
3148ade7 9400 u32 temp, dpll_ctl1;
96b7dfb7
S
9401
9402 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9403 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9404
9405 switch (pipe_config->ddi_pll_sel) {
3148ade7
DL
9406 case SKL_DPLL0:
9407 /*
9408 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9409 * of the shared DPLL framework and thus needs to be read out
9410 * separately
9411 */
9412 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9413 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9414 break;
96b7dfb7
S
9415 case SKL_DPLL1:
9416 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9417 break;
9418 case SKL_DPLL2:
9419 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9420 break;
9421 case SKL_DPLL3:
9422 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9423 break;
96b7dfb7
S
9424 }
9425}
9426
7d2c8175
DL
9427static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9428 enum port port,
5cec258b 9429 struct intel_crtc_state *pipe_config)
7d2c8175
DL
9430{
9431 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9432
9433 switch (pipe_config->ddi_pll_sel) {
9434 case PORT_CLK_SEL_WRPLL1:
9435 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9436 break;
9437 case PORT_CLK_SEL_WRPLL2:
9438 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9439 break;
9440 }
9441}
9442
26804afd 9443static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
5cec258b 9444 struct intel_crtc_state *pipe_config)
26804afd
DV
9445{
9446 struct drm_device *dev = crtc->base.dev;
9447 struct drm_i915_private *dev_priv = dev->dev_private;
d452c5b6 9448 struct intel_shared_dpll *pll;
26804afd
DV
9449 enum port port;
9450 uint32_t tmp;
9451
9452 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9453
9454 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9455
96b7dfb7
S
9456 if (IS_SKYLAKE(dev))
9457 skylake_get_ddi_pll(dev_priv, port, pipe_config);
3760b59c
S
9458 else if (IS_BROXTON(dev))
9459 bxt_get_ddi_pll(dev_priv, port, pipe_config);
96b7dfb7
S
9460 else
9461 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9cd86933 9462
d452c5b6
DV
9463 if (pipe_config->shared_dpll >= 0) {
9464 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9465
9466 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9467 &pipe_config->dpll_hw_state));
9468 }
9469
26804afd
DV
9470 /*
9471 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9472 * DDI E. So just check whether this pipe is wired to DDI E and whether
9473 * the PCH transcoder is on.
9474 */
ca370455
DL
9475 if (INTEL_INFO(dev)->gen < 9 &&
9476 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
26804afd
DV
9477 pipe_config->has_pch_encoder = true;
9478
9479 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9480 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9481 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9482
9483 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9484 }
9485}
9486
0e8ffe1b 9487static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5cec258b 9488 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV
9489{
9490 struct drm_device *dev = crtc->base.dev;
9491 struct drm_i915_private *dev_priv = dev->dev_private;
2fa2fe9a 9492 enum intel_display_power_domain pfit_domain;
0e8ffe1b
DV
9493 uint32_t tmp;
9494
f458ebbc 9495 if (!intel_display_power_is_enabled(dev_priv,
b5482bd0
ID
9496 POWER_DOMAIN_PIPE(crtc->pipe)))
9497 return false;
9498
e143a21c 9499 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62
DV
9500 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9501
eccb140b
DV
9502 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9503 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9504 enum pipe trans_edp_pipe;
9505 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9506 default:
9507 WARN(1, "unknown pipe linked to edp transcoder\n");
9508 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9509 case TRANS_DDI_EDP_INPUT_A_ON:
9510 trans_edp_pipe = PIPE_A;
9511 break;
9512 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9513 trans_edp_pipe = PIPE_B;
9514 break;
9515 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9516 trans_edp_pipe = PIPE_C;
9517 break;
9518 }
9519
9520 if (trans_edp_pipe == crtc->pipe)
9521 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9522 }
9523
f458ebbc 9524 if (!intel_display_power_is_enabled(dev_priv,
eccb140b 9525 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
2bfce950
PZ
9526 return false;
9527
eccb140b 9528 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
0e8ffe1b
DV
9529 if (!(tmp & PIPECONF_ENABLE))
9530 return false;
9531
26804afd 9532 haswell_get_ddi_port_state(crtc, pipe_config);
627eb5a3 9533
1bd1bd80
DV
9534 intel_get_pipe_timings(crtc, pipe_config);
9535
a1b2278e
CK
9536 if (INTEL_INFO(dev)->gen >= 9) {
9537 skl_init_scalers(dev, crtc, pipe_config);
9538 }
9539
2fa2fe9a 9540 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
af99ceda
CK
9541
9542 if (INTEL_INFO(dev)->gen >= 9) {
9543 pipe_config->scaler_state.scaler_id = -1;
9544 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9545 }
9546
bd2e244f 9547 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
ff6d9f55 9548 if (INTEL_INFO(dev)->gen == 9)
bd2e244f 9549 skylake_get_pfit_config(crtc, pipe_config);
ff6d9f55 9550 else if (INTEL_INFO(dev)->gen < 9)
bd2e244f 9551 ironlake_get_pfit_config(crtc, pipe_config);
ff6d9f55
JB
9552 else
9553 MISSING_CASE(INTEL_INFO(dev)->gen);
bd2e244f 9554 }
88adfff1 9555
e59150dc
JB
9556 if (IS_HASWELL(dev))
9557 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9558 (I915_READ(IPS_CTL) & IPS_ENABLE);
42db64ef 9559
ebb69c95
CT
9560 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
9561 pipe_config->pixel_multiplier =
9562 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9563 } else {
9564 pipe_config->pixel_multiplier = 1;
9565 }
6c49f241 9566
0e8ffe1b
DV
9567 return true;
9568}
9569
560b85bb
CW
9570static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
9571{
9572 struct drm_device *dev = crtc->dev;
9573 struct drm_i915_private *dev_priv = dev->dev_private;
9574 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
dc41c154 9575 uint32_t cntl = 0, size = 0;
560b85bb 9576
dc41c154 9577 if (base) {
3dd512fb
MR
9578 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
9579 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
dc41c154
VS
9580 unsigned int stride = roundup_pow_of_two(width) * 4;
9581
9582 switch (stride) {
9583 default:
9584 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9585 width, stride);
9586 stride = 256;
9587 /* fallthrough */
9588 case 256:
9589 case 512:
9590 case 1024:
9591 case 2048:
9592 break;
4b0e333e
CW
9593 }
9594
dc41c154
VS
9595 cntl |= CURSOR_ENABLE |
9596 CURSOR_GAMMA_ENABLE |
9597 CURSOR_FORMAT_ARGB |
9598 CURSOR_STRIDE(stride);
9599
9600 size = (height << 12) | width;
4b0e333e 9601 }
560b85bb 9602
dc41c154
VS
9603 if (intel_crtc->cursor_cntl != 0 &&
9604 (intel_crtc->cursor_base != base ||
9605 intel_crtc->cursor_size != size ||
9606 intel_crtc->cursor_cntl != cntl)) {
9607 /* On these chipsets we can only modify the base/size/stride
9608 * whilst the cursor is disabled.
9609 */
9610 I915_WRITE(_CURACNTR, 0);
4b0e333e 9611 POSTING_READ(_CURACNTR);
dc41c154 9612 intel_crtc->cursor_cntl = 0;
4b0e333e 9613 }
560b85bb 9614
99d1f387 9615 if (intel_crtc->cursor_base != base) {
9db4a9c7 9616 I915_WRITE(_CURABASE, base);
99d1f387
VS
9617 intel_crtc->cursor_base = base;
9618 }
4726e0b0 9619
dc41c154
VS
9620 if (intel_crtc->cursor_size != size) {
9621 I915_WRITE(CURSIZE, size);
9622 intel_crtc->cursor_size = size;
4b0e333e 9623 }
560b85bb 9624
4b0e333e 9625 if (intel_crtc->cursor_cntl != cntl) {
4b0e333e
CW
9626 I915_WRITE(_CURACNTR, cntl);
9627 POSTING_READ(_CURACNTR);
4b0e333e 9628 intel_crtc->cursor_cntl = cntl;
560b85bb 9629 }
560b85bb
CW
9630}
9631
560b85bb 9632static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
65a21cd6
JB
9633{
9634 struct drm_device *dev = crtc->dev;
9635 struct drm_i915_private *dev_priv = dev->dev_private;
9636 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9637 int pipe = intel_crtc->pipe;
4b0e333e
CW
9638 uint32_t cntl;
9639
9640 cntl = 0;
9641 if (base) {
9642 cntl = MCURSOR_GAMMA_ENABLE;
3dd512fb 9643 switch (intel_crtc->base.cursor->state->crtc_w) {
4726e0b0
SK
9644 case 64:
9645 cntl |= CURSOR_MODE_64_ARGB_AX;
9646 break;
9647 case 128:
9648 cntl |= CURSOR_MODE_128_ARGB_AX;
9649 break;
9650 case 256:
9651 cntl |= CURSOR_MODE_256_ARGB_AX;
9652 break;
9653 default:
3dd512fb 9654 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
4726e0b0 9655 return;
65a21cd6 9656 }
4b0e333e 9657 cntl |= pipe << 28; /* Connect to correct pipe */
47bf17a7
VS
9658
9659 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
9660 cntl |= CURSOR_PIPE_CSC_ENABLE;
4b0e333e 9661 }
65a21cd6 9662
8e7d688b 9663 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
4398ad45
VS
9664 cntl |= CURSOR_ROTATE_180;
9665
4b0e333e
CW
9666 if (intel_crtc->cursor_cntl != cntl) {
9667 I915_WRITE(CURCNTR(pipe), cntl);
9668 POSTING_READ(CURCNTR(pipe));
9669 intel_crtc->cursor_cntl = cntl;
65a21cd6 9670 }
4b0e333e 9671
65a21cd6 9672 /* and commit changes on next vblank */
5efb3e28
VS
9673 I915_WRITE(CURBASE(pipe), base);
9674 POSTING_READ(CURBASE(pipe));
99d1f387
VS
9675
9676 intel_crtc->cursor_base = base;
65a21cd6
JB
9677}
9678
cda4b7d3 9679/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW
9680static void intel_crtc_update_cursor(struct drm_crtc *crtc,
9681 bool on)
cda4b7d3
CW
9682{
9683 struct drm_device *dev = crtc->dev;
9684 struct drm_i915_private *dev_priv = dev->dev_private;
9685 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9686 int pipe = intel_crtc->pipe;
3d7d6510
MR
9687 int x = crtc->cursor_x;
9688 int y = crtc->cursor_y;
d6e4db15 9689 u32 base = 0, pos = 0;
cda4b7d3 9690
d6e4db15 9691 if (on)
cda4b7d3 9692 base = intel_crtc->cursor_addr;
cda4b7d3 9693
6e3c9717 9694 if (x >= intel_crtc->config->pipe_src_w)
d6e4db15
VS
9695 base = 0;
9696
6e3c9717 9697 if (y >= intel_crtc->config->pipe_src_h)
cda4b7d3
CW
9698 base = 0;
9699
9700 if (x < 0) {
3dd512fb 9701 if (x + intel_crtc->base.cursor->state->crtc_w <= 0)
cda4b7d3
CW
9702 base = 0;
9703
9704 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9705 x = -x;
9706 }
9707 pos |= x << CURSOR_X_SHIFT;
9708
9709 if (y < 0) {
3dd512fb 9710 if (y + intel_crtc->base.cursor->state->crtc_h <= 0)
cda4b7d3
CW
9711 base = 0;
9712
9713 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
9714 y = -y;
9715 }
9716 pos |= y << CURSOR_Y_SHIFT;
9717
4b0e333e 9718 if (base == 0 && intel_crtc->cursor_base == 0)
cda4b7d3
CW
9719 return;
9720
5efb3e28
VS
9721 I915_WRITE(CURPOS(pipe), pos);
9722
4398ad45
VS
9723 /* ILK+ do this automagically */
9724 if (HAS_GMCH_DISPLAY(dev) &&
8e7d688b 9725 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
3dd512fb
MR
9726 base += (intel_crtc->base.cursor->state->crtc_h *
9727 intel_crtc->base.cursor->state->crtc_w - 1) * 4;
4398ad45
VS
9728 }
9729
8ac54669 9730 if (IS_845G(dev) || IS_I865G(dev))
5efb3e28
VS
9731 i845_update_cursor(crtc, base);
9732 else
9733 i9xx_update_cursor(crtc, base);
cda4b7d3
CW
9734}
9735
dc41c154
VS
9736static bool cursor_size_ok(struct drm_device *dev,
9737 uint32_t width, uint32_t height)
9738{
9739 if (width == 0 || height == 0)
9740 return false;
9741
9742 /*
9743 * 845g/865g are special in that they are only limited by
9744 * the width of their cursors, the height is arbitrary up to
9745 * the precision of the register. Everything else requires
9746 * square cursors, limited to a few power-of-two sizes.
9747 */
9748 if (IS_845G(dev) || IS_I865G(dev)) {
9749 if ((width & 63) != 0)
9750 return false;
9751
9752 if (width > (IS_845G(dev) ? 64 : 512))
9753 return false;
9754
9755 if (height > 1023)
9756 return false;
9757 } else {
9758 switch (width | height) {
9759 case 256:
9760 case 128:
9761 if (IS_GEN2(dev))
9762 return false;
9763 case 64:
9764 break;
9765 default:
9766 return false;
9767 }
9768 }
9769
9770 return true;
9771}
9772
79e53945 9773static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 9774 u16 *blue, uint32_t start, uint32_t size)
79e53945 9775{
7203425a 9776 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 9777 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 9778
7203425a 9779 for (i = start; i < end; i++) {
79e53945
JB
9780 intel_crtc->lut_r[i] = red[i] >> 8;
9781 intel_crtc->lut_g[i] = green[i] >> 8;
9782 intel_crtc->lut_b[i] = blue[i] >> 8;
9783 }
9784
9785 intel_crtc_load_lut(crtc);
9786}
9787
79e53945
JB
9788/* VESA 640x480x72Hz mode to set on the pipe */
9789static struct drm_display_mode load_detect_mode = {
9790 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
9791 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
9792};
9793
a8bb6818
DV
9794struct drm_framebuffer *
9795__intel_framebuffer_create(struct drm_device *dev,
9796 struct drm_mode_fb_cmd2 *mode_cmd,
9797 struct drm_i915_gem_object *obj)
d2dff872
CW
9798{
9799 struct intel_framebuffer *intel_fb;
9800 int ret;
9801
9802 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9803 if (!intel_fb) {
6ccb81f2 9804 drm_gem_object_unreference(&obj->base);
d2dff872
CW
9805 return ERR_PTR(-ENOMEM);
9806 }
9807
9808 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
dd4916c5
DV
9809 if (ret)
9810 goto err;
d2dff872
CW
9811
9812 return &intel_fb->base;
dd4916c5 9813err:
6ccb81f2 9814 drm_gem_object_unreference(&obj->base);
dd4916c5
DV
9815 kfree(intel_fb);
9816
9817 return ERR_PTR(ret);
d2dff872
CW
9818}
9819
b5ea642a 9820static struct drm_framebuffer *
a8bb6818
DV
9821intel_framebuffer_create(struct drm_device *dev,
9822 struct drm_mode_fb_cmd2 *mode_cmd,
9823 struct drm_i915_gem_object *obj)
9824{
9825 struct drm_framebuffer *fb;
9826 int ret;
9827
9828 ret = i915_mutex_lock_interruptible(dev);
9829 if (ret)
9830 return ERR_PTR(ret);
9831 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
9832 mutex_unlock(&dev->struct_mutex);
9833
9834 return fb;
9835}
9836
d2dff872
CW
9837static u32
9838intel_framebuffer_pitch_for_width(int width, int bpp)
9839{
9840 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
9841 return ALIGN(pitch, 64);
9842}
9843
9844static u32
9845intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
9846{
9847 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
1267a26b 9848 return PAGE_ALIGN(pitch * mode->vdisplay);
d2dff872
CW
9849}
9850
9851static struct drm_framebuffer *
9852intel_framebuffer_create_for_mode(struct drm_device *dev,
9853 struct drm_display_mode *mode,
9854 int depth, int bpp)
9855{
9856 struct drm_i915_gem_object *obj;
0fed39bd 9857 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW
9858
9859 obj = i915_gem_alloc_object(dev,
9860 intel_framebuffer_size_for_mode(mode, bpp));
9861 if (obj == NULL)
9862 return ERR_PTR(-ENOMEM);
9863
9864 mode_cmd.width = mode->hdisplay;
9865 mode_cmd.height = mode->vdisplay;
308e5bcb
JB
9866 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
9867 bpp);
5ca0c34a 9868 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW
9869
9870 return intel_framebuffer_create(dev, &mode_cmd, obj);
9871}
9872
9873static struct drm_framebuffer *
9874mode_fits_in_fbdev(struct drm_device *dev,
9875 struct drm_display_mode *mode)
9876{
4520f53a 9877#ifdef CONFIG_DRM_I915_FBDEV
d2dff872
CW
9878 struct drm_i915_private *dev_priv = dev->dev_private;
9879 struct drm_i915_gem_object *obj;
9880 struct drm_framebuffer *fb;
9881
4c0e5528 9882 if (!dev_priv->fbdev)
d2dff872
CW
9883 return NULL;
9884
4c0e5528 9885 if (!dev_priv->fbdev->fb)
d2dff872
CW
9886 return NULL;
9887
4c0e5528
DV
9888 obj = dev_priv->fbdev->fb->obj;
9889 BUG_ON(!obj);
9890
8bcd4553 9891 fb = &dev_priv->fbdev->fb->base;
01f2c773
VS
9892 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
9893 fb->bits_per_pixel))
d2dff872
CW
9894 return NULL;
9895
01f2c773 9896 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW
9897 return NULL;
9898
9899 return fb;
4520f53a
DV
9900#else
9901 return NULL;
9902#endif
d2dff872
CW
9903}
9904
d3a40d1b
ACO
9905static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
9906 struct drm_crtc *crtc,
9907 struct drm_display_mode *mode,
9908 struct drm_framebuffer *fb,
9909 int x, int y)
9910{
9911 struct drm_plane_state *plane_state;
9912 int hdisplay, vdisplay;
9913 int ret;
9914
9915 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
9916 if (IS_ERR(plane_state))
9917 return PTR_ERR(plane_state);
9918
9919 if (mode)
9920 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
9921 else
9922 hdisplay = vdisplay = 0;
9923
9924 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
9925 if (ret)
9926 return ret;
9927 drm_atomic_set_fb_for_plane(plane_state, fb);
9928 plane_state->crtc_x = 0;
9929 plane_state->crtc_y = 0;
9930 plane_state->crtc_w = hdisplay;
9931 plane_state->crtc_h = vdisplay;
9932 plane_state->src_x = x << 16;
9933 plane_state->src_y = y << 16;
9934 plane_state->src_w = hdisplay << 16;
9935 plane_state->src_h = vdisplay << 16;
9936
9937 return 0;
9938}
9939
d2434ab7 9940bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 9941 struct drm_display_mode *mode,
51fd371b
RC
9942 struct intel_load_detect_pipe *old,
9943 struct drm_modeset_acquire_ctx *ctx)
79e53945
JB
9944{
9945 struct intel_crtc *intel_crtc;
d2434ab7
DV
9946 struct intel_encoder *intel_encoder =
9947 intel_attached_encoder(connector);
79e53945 9948 struct drm_crtc *possible_crtc;
4ef69c7a 9949 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB
9950 struct drm_crtc *crtc = NULL;
9951 struct drm_device *dev = encoder->dev;
94352cf9 9952 struct drm_framebuffer *fb;
51fd371b 9953 struct drm_mode_config *config = &dev->mode_config;
83a57153 9954 struct drm_atomic_state *state = NULL;
944b0c76 9955 struct drm_connector_state *connector_state;
4be07317 9956 struct intel_crtc_state *crtc_state;
51fd371b 9957 int ret, i = -1;
79e53945 9958
d2dff872 9959 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
c23cc417 9960 connector->base.id, connector->name,
8e329a03 9961 encoder->base.id, encoder->name);
d2dff872 9962
51fd371b
RC
9963retry:
9964 ret = drm_modeset_lock(&config->connection_mutex, ctx);
9965 if (ret)
9966 goto fail_unlock;
6e9f798d 9967
79e53945
JB
9968 /*
9969 * Algorithm gets a little messy:
7a5e4805 9970 *
79e53945
JB
9971 * - if the connector already has an assigned crtc, use it (but make
9972 * sure it's on first)
7a5e4805 9973 *
79e53945
JB
9974 * - try to find the first unused crtc that can drive this connector,
9975 * and use that if we find one
79e53945
JB
9976 */
9977
9978 /* See if we already have a CRTC for this connector */
9979 if (encoder->crtc) {
9980 crtc = encoder->crtc;
8261b191 9981
51fd371b 9982 ret = drm_modeset_lock(&crtc->mutex, ctx);
4d02e2de
DV
9983 if (ret)
9984 goto fail_unlock;
9985 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
51fd371b
RC
9986 if (ret)
9987 goto fail_unlock;
7b24056b 9988
24218aac 9989 old->dpms_mode = connector->dpms;
8261b191
CW
9990 old->load_detect_temp = false;
9991
9992 /* Make sure the crtc and connector are running */
24218aac
DV
9993 if (connector->dpms != DRM_MODE_DPMS_ON)
9994 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 9995
7173188d 9996 return true;
79e53945
JB
9997 }
9998
9999 /* Find an unused one (if possible) */
70e1e0ec 10000 for_each_crtc(dev, possible_crtc) {
79e53945
JB
10001 i++;
10002 if (!(encoder->possible_crtcs & (1 << i)))
10003 continue;
83d65738 10004 if (possible_crtc->state->enable)
a459249c
VS
10005 continue;
10006 /* This can occur when applying the pipe A quirk on resume. */
10007 if (to_intel_crtc(possible_crtc)->new_enabled)
10008 continue;
10009
10010 crtc = possible_crtc;
10011 break;
79e53945
JB
10012 }
10013
10014 /*
10015 * If we didn't find an unused CRTC, don't use any.
10016 */
10017 if (!crtc) {
7173188d 10018 DRM_DEBUG_KMS("no pipe available for load-detect\n");
51fd371b 10019 goto fail_unlock;
79e53945
JB
10020 }
10021
51fd371b
RC
10022 ret = drm_modeset_lock(&crtc->mutex, ctx);
10023 if (ret)
4d02e2de
DV
10024 goto fail_unlock;
10025 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10026 if (ret)
51fd371b 10027 goto fail_unlock;
fc303101
DV
10028 intel_encoder->new_crtc = to_intel_crtc(crtc);
10029 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB
10030
10031 intel_crtc = to_intel_crtc(crtc);
412b61d8 10032 intel_crtc->new_enabled = true;
24218aac 10033 old->dpms_mode = connector->dpms;
8261b191 10034 old->load_detect_temp = true;
d2dff872 10035 old->release_fb = NULL;
79e53945 10036
83a57153
ACO
10037 state = drm_atomic_state_alloc(dev);
10038 if (!state)
10039 return false;
10040
10041 state->acquire_ctx = ctx;
10042
944b0c76
ACO
10043 connector_state = drm_atomic_get_connector_state(state, connector);
10044 if (IS_ERR(connector_state)) {
10045 ret = PTR_ERR(connector_state);
10046 goto fail;
10047 }
10048
10049 connector_state->crtc = crtc;
10050 connector_state->best_encoder = &intel_encoder->base;
10051
4be07317
ACO
10052 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10053 if (IS_ERR(crtc_state)) {
10054 ret = PTR_ERR(crtc_state);
10055 goto fail;
10056 }
10057
49d6fa21 10058 crtc_state->base.active = crtc_state->base.enable = true;
4be07317 10059
6492711d
CW
10060 if (!mode)
10061 mode = &load_detect_mode;
79e53945 10062
d2dff872
CW
10063 /* We need a framebuffer large enough to accommodate all accesses
10064 * that the plane may generate whilst we perform load detection.
10065 * We can not rely on the fbcon either being present (we get called
10066 * during its initialisation to detect all boot displays, or it may
10067 * not even exist) or that it is large enough to satisfy the
10068 * requested mode.
10069 */
94352cf9
DV
10070 fb = mode_fits_in_fbdev(dev, mode);
10071 if (fb == NULL) {
d2dff872 10072 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV
10073 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10074 old->release_fb = fb;
d2dff872
CW
10075 } else
10076 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 10077 if (IS_ERR(fb)) {
d2dff872 10078 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
412b61d8 10079 goto fail;
79e53945 10080 }
79e53945 10081
d3a40d1b
ACO
10082 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10083 if (ret)
10084 goto fail;
10085
8c7b5ccb
ACO
10086 drm_mode_copy(&crtc_state->base.mode, mode);
10087
10088 if (intel_set_mode(crtc, state)) {
6492711d 10089 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW
10090 if (old->release_fb)
10091 old->release_fb->funcs->destroy(old->release_fb);
412b61d8 10092 goto fail;
79e53945 10093 }
9128b040 10094 crtc->primary->crtc = crtc;
7173188d 10095
79e53945 10096 /* let the connector get through one full cycle before testing */
9d0498a2 10097 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 10098 return true;
412b61d8
VS
10099
10100 fail:
83d65738 10101 intel_crtc->new_enabled = crtc->state->enable;
51fd371b 10102fail_unlock:
e5d958ef
ACO
10103 drm_atomic_state_free(state);
10104 state = NULL;
83a57153 10105
51fd371b
RC
10106 if (ret == -EDEADLK) {
10107 drm_modeset_backoff(ctx);
10108 goto retry;
10109 }
10110
412b61d8 10111 return false;
79e53945
JB
10112}
10113
d2434ab7 10114void intel_release_load_detect_pipe(struct drm_connector *connector,
49172fee
ACO
10115 struct intel_load_detect_pipe *old,
10116 struct drm_modeset_acquire_ctx *ctx)
79e53945 10117{
83a57153 10118 struct drm_device *dev = connector->dev;
d2434ab7
DV
10119 struct intel_encoder *intel_encoder =
10120 intel_attached_encoder(connector);
4ef69c7a 10121 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 10122 struct drm_crtc *crtc = encoder->crtc;
412b61d8 10123 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83a57153 10124 struct drm_atomic_state *state;
944b0c76 10125 struct drm_connector_state *connector_state;
4be07317 10126 struct intel_crtc_state *crtc_state;
d3a40d1b 10127 int ret;
79e53945 10128
d2dff872 10129 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
c23cc417 10130 connector->base.id, connector->name,
8e329a03 10131 encoder->base.id, encoder->name);
d2dff872 10132
8261b191 10133 if (old->load_detect_temp) {
83a57153 10134 state = drm_atomic_state_alloc(dev);
944b0c76
ACO
10135 if (!state)
10136 goto fail;
83a57153
ACO
10137
10138 state->acquire_ctx = ctx;
10139
944b0c76
ACO
10140 connector_state = drm_atomic_get_connector_state(state, connector);
10141 if (IS_ERR(connector_state))
10142 goto fail;
10143
4be07317
ACO
10144 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10145 if (IS_ERR(crtc_state))
10146 goto fail;
10147
fc303101
DV
10148 to_intel_connector(connector)->new_encoder = NULL;
10149 intel_encoder->new_crtc = NULL;
412b61d8 10150 intel_crtc->new_enabled = false;
944b0c76
ACO
10151
10152 connector_state->best_encoder = NULL;
10153 connector_state->crtc = NULL;
10154
49d6fa21 10155 crtc_state->base.enable = crtc_state->base.active = false;
4be07317 10156
d3a40d1b
ACO
10157 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
10158 0, 0);
10159 if (ret)
10160 goto fail;
10161
2bfb4627
ACO
10162 ret = intel_set_mode(crtc, state);
10163 if (ret)
10164 goto fail;
d2dff872 10165
36206361
DV
10166 if (old->release_fb) {
10167 drm_framebuffer_unregister_private(old->release_fb);
10168 drm_framebuffer_unreference(old->release_fb);
10169 }
d2dff872 10170
0622a53c 10171 return;
79e53945
JB
10172 }
10173
c751ce4f 10174 /* Switch crtc and encoder back off if necessary */
24218aac
DV
10175 if (old->dpms_mode != DRM_MODE_DPMS_ON)
10176 connector->funcs->dpms(connector, old->dpms_mode);
944b0c76
ACO
10177
10178 return;
10179fail:
10180 DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
10181 drm_atomic_state_free(state);
79e53945
JB
10182}
10183
da4a1efa 10184static int i9xx_pll_refclk(struct drm_device *dev,
5cec258b 10185 const struct intel_crtc_state *pipe_config)
da4a1efa
VS
10186{
10187 struct drm_i915_private *dev_priv = dev->dev_private;
10188 u32 dpll = pipe_config->dpll_hw_state.dpll;
10189
10190 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
e91e941b 10191 return dev_priv->vbt.lvds_ssc_freq;
da4a1efa
VS
10192 else if (HAS_PCH_SPLIT(dev))
10193 return 120000;
10194 else if (!IS_GEN2(dev))
10195 return 96000;
10196 else
10197 return 48000;
10198}
10199
79e53945 10200/* Returns the clock of the currently programmed mode of the given pipe. */
f1f644dc 10201static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 10202 struct intel_crtc_state *pipe_config)
79e53945 10203{
f1f644dc 10204 struct drm_device *dev = crtc->base.dev;
79e53945 10205 struct drm_i915_private *dev_priv = dev->dev_private;
f1f644dc 10206 int pipe = pipe_config->cpu_transcoder;
293623f7 10207 u32 dpll = pipe_config->dpll_hw_state.dpll;
79e53945
JB
10208 u32 fp;
10209 intel_clock_t clock;
da4a1efa 10210 int refclk = i9xx_pll_refclk(dev, pipe_config);
79e53945
JB
10211
10212 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
293623f7 10213 fp = pipe_config->dpll_hw_state.fp0;
79e53945 10214 else
293623f7 10215 fp = pipe_config->dpll_hw_state.fp1;
79e53945
JB
10216
10217 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ
10218 if (IS_PINEVIEW(dev)) {
10219 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10220 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL
10221 } else {
10222 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10223 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10224 }
10225
a6c45cf0 10226 if (!IS_GEN2(dev)) {
f2b115e6
AJ
10227 if (IS_PINEVIEW(dev))
10228 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10229 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL
10230 else
10231 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB
10232 DPLL_FPA01_P1_POST_DIV_SHIFT);
10233
10234 switch (dpll & DPLL_MODE_MASK) {
10235 case DPLLB_MODE_DAC_SERIAL:
10236 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10237 5 : 10;
10238 break;
10239 case DPLLB_MODE_LVDS:
10240 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10241 7 : 14;
10242 break;
10243 default:
28c97730 10244 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945 10245 "mode\n", (int)(dpll & DPLL_MODE_MASK));
f1f644dc 10246 return;
79e53945
JB
10247 }
10248
ac58c3f0 10249 if (IS_PINEVIEW(dev))
da4a1efa 10250 pineview_clock(refclk, &clock);
ac58c3f0 10251 else
da4a1efa 10252 i9xx_clock(refclk, &clock);
79e53945 10253 } else {
0fb58223 10254 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
b1c560d1 10255 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
79e53945
JB
10256
10257 if (is_lvds) {
10258 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10259 DPLL_FPA01_P1_POST_DIV_SHIFT);
b1c560d1
VS
10260
10261 if (lvds & LVDS_CLKB_POWER_UP)
10262 clock.p2 = 7;
10263 else
10264 clock.p2 = 14;
79e53945
JB
10265 } else {
10266 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10267 clock.p1 = 2;
10268 else {
10269 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10270 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10271 }
10272 if (dpll & PLL_P2_DIVIDE_BY_4)
10273 clock.p2 = 4;
10274 else
10275 clock.p2 = 2;
79e53945 10276 }
da4a1efa
VS
10277
10278 i9xx_clock(refclk, &clock);
79e53945
JB
10279 }
10280
18442d08
VS
10281 /*
10282 * This value includes pixel_multiplier. We will use
241bfc38 10283 * port_clock to compute adjusted_mode.crtc_clock in the
18442d08
VS
10284 * encoder's get_config() function.
10285 */
10286 pipe_config->port_clock = clock.dot;
f1f644dc
JB
10287}
10288
6878da05
VS
10289int intel_dotclock_calculate(int link_freq,
10290 const struct intel_link_m_n *m_n)
f1f644dc 10291{
f1f644dc
JB
10292 /*
10293 * The calculation for the data clock is:
1041a02f 10294 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
f1f644dc 10295 * But we want to avoid losing precison if possible, so:
1041a02f 10296 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
f1f644dc
JB
10297 *
10298 * and the link clock is simpler:
1041a02f 10299 * link_clock = (m * link_clock) / n
f1f644dc
JB
10300 */
10301
6878da05
VS
10302 if (!m_n->link_n)
10303 return 0;
f1f644dc 10304
6878da05
VS
10305 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10306}
f1f644dc 10307
18442d08 10308static void ironlake_pch_clock_get(struct intel_crtc *crtc,
5cec258b 10309 struct intel_crtc_state *pipe_config)
6878da05
VS
10310{
10311 struct drm_device *dev = crtc->base.dev;
79e53945 10312
18442d08
VS
10313 /* read out port_clock from the DPLL */
10314 i9xx_crtc_clock_get(crtc, pipe_config);
f1f644dc 10315
f1f644dc 10316 /*
18442d08 10317 * This value does not include pixel_multiplier.
241bfc38 10318 * We will check that port_clock and adjusted_mode.crtc_clock
18442d08
VS
10319 * agree once we know their relationship in the encoder's
10320 * get_config() function.
79e53945 10321 */
2d112de7 10322 pipe_config->base.adjusted_mode.crtc_clock =
18442d08
VS
10323 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10324 &pipe_config->fdi_m_n);
79e53945
JB
10325}
10326
10327/** Returns the currently programmed mode of the given pipe. */
10328struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10329 struct drm_crtc *crtc)
10330{
548f245b 10331 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 10332 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 10333 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
79e53945 10334 struct drm_display_mode *mode;
5cec258b 10335 struct intel_crtc_state pipe_config;
fe2b8f9d
PZ
10336 int htot = I915_READ(HTOTAL(cpu_transcoder));
10337 int hsync = I915_READ(HSYNC(cpu_transcoder));
10338 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10339 int vsync = I915_READ(VSYNC(cpu_transcoder));
293623f7 10340 enum pipe pipe = intel_crtc->pipe;
79e53945
JB
10341
10342 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10343 if (!mode)
10344 return NULL;
10345
f1f644dc
JB
10346 /*
10347 * Construct a pipe_config sufficient for getting the clock info
10348 * back out of crtc_clock_get.
10349 *
10350 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10351 * to use a real value here instead.
10352 */
293623f7 10353 pipe_config.cpu_transcoder = (enum transcoder) pipe;
f1f644dc 10354 pipe_config.pixel_multiplier = 1;
293623f7
VS
10355 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10356 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10357 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
f1f644dc
JB
10358 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10359
773ae034 10360 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
79e53945
JB
10361 mode->hdisplay = (htot & 0xffff) + 1;
10362 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10363 mode->hsync_start = (hsync & 0xffff) + 1;
10364 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10365 mode->vdisplay = (vtot & 0xffff) + 1;
10366 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10367 mode->vsync_start = (vsync & 0xffff) + 1;
10368 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10369
10370 drm_mode_set_name(mode);
79e53945
JB
10371
10372 return mode;
10373}
10374
652c393a
JB
10375static void intel_decrease_pllclock(struct drm_crtc *crtc)
10376{
10377 struct drm_device *dev = crtc->dev;
fbee40df 10378 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 10379 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 10380
baff296c 10381 if (!HAS_GMCH_DISPLAY(dev))
652c393a
JB
10382 return;
10383
10384 if (!dev_priv->lvds_downclock_avail)
10385 return;
10386
10387 /*
10388 * Since this is called by a timer, we should never get here in
10389 * the manual case.
10390 */
10391 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV
10392 int pipe = intel_crtc->pipe;
10393 int dpll_reg = DPLL(pipe);
10394 int dpll;
f6e5b160 10395
44d98a61 10396 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 10397
8ac5a6d5 10398 assert_panel_unlocked(dev_priv, pipe);
652c393a 10399
dc257cf1 10400 dpll = I915_READ(dpll_reg);
652c393a
JB
10401 dpll |= DISPLAY_RATE_SELECT_FPA1;
10402 I915_WRITE(dpll_reg, dpll);
9d0498a2 10403 intel_wait_for_vblank(dev, pipe);
652c393a
JB
10404 dpll = I915_READ(dpll_reg);
10405 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 10406 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB
10407 }
10408
10409}
10410
f047e395
CW
10411void intel_mark_busy(struct drm_device *dev)
10412{
c67a470b
PZ
10413 struct drm_i915_private *dev_priv = dev->dev_private;
10414
f62a0076
CW
10415 if (dev_priv->mm.busy)
10416 return;
10417
43694d69 10418 intel_runtime_pm_get(dev_priv);
c67a470b 10419 i915_update_gfx_val(dev_priv);
43cf3bf0
CW
10420 if (INTEL_INFO(dev)->gen >= 6)
10421 gen6_rps_busy(dev_priv);
f62a0076 10422 dev_priv->mm.busy = true;
f047e395
CW
10423}
10424
10425void intel_mark_idle(struct drm_device *dev)
652c393a 10426{
c67a470b 10427 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 10428 struct drm_crtc *crtc;
652c393a 10429
f62a0076
CW
10430 if (!dev_priv->mm.busy)
10431 return;
10432
10433 dev_priv->mm.busy = false;
10434
70e1e0ec 10435 for_each_crtc(dev, crtc) {
f4510a27 10436 if (!crtc->primary->fb)
652c393a
JB
10437 continue;
10438
725a5b54 10439 intel_decrease_pllclock(crtc);
652c393a 10440 }
b29c19b6 10441
3d13ef2e 10442 if (INTEL_INFO(dev)->gen >= 6)
b29c19b6 10443 gen6_rps_idle(dev->dev_private);
bb4cdd53 10444
43694d69 10445 intel_runtime_pm_put(dev_priv);
652c393a
JB
10446}
10447
79e53945
JB
10448static void intel_crtc_destroy(struct drm_crtc *crtc)
10449{
10450 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV
10451 struct drm_device *dev = crtc->dev;
10452 struct intel_unpin_work *work;
67e77c5a 10453
5e2d7afc 10454 spin_lock_irq(&dev->event_lock);
67e77c5a
DV
10455 work = intel_crtc->unpin_work;
10456 intel_crtc->unpin_work = NULL;
5e2d7afc 10457 spin_unlock_irq(&dev->event_lock);
67e77c5a
DV
10458
10459 if (work) {
10460 cancel_work_sync(&work->work);
10461 kfree(work);
10462 }
79e53945
JB
10463
10464 drm_crtc_cleanup(crtc);
67e77c5a 10465
79e53945
JB
10466 kfree(intel_crtc);
10467}
10468
6b95a207
KH
10469static void intel_unpin_work_fn(struct work_struct *__work)
10470{
10471 struct intel_unpin_work *work =
10472 container_of(__work, struct intel_unpin_work, work);
b4a98e57 10473 struct drm_device *dev = work->crtc->dev;
f99d7069 10474 enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
6b95a207 10475
b4a98e57 10476 mutex_lock(&dev->struct_mutex);
82bc3b2d 10477 intel_unpin_fb_obj(work->old_fb, work->crtc->primary->state);
05394f39 10478 drm_gem_object_unreference(&work->pending_flip_obj->base);
d9e86c0e 10479
7ff0ebcc 10480 intel_fbc_update(dev);
f06cc1b9
JH
10481
10482 if (work->flip_queued_req)
146d84f0 10483 i915_gem_request_assign(&work->flip_queued_req, NULL);
b4a98e57
CW
10484 mutex_unlock(&dev->struct_mutex);
10485
f99d7069 10486 intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
89ed88ba 10487 drm_framebuffer_unreference(work->old_fb);
f99d7069 10488
b4a98e57
CW
10489 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
10490 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
10491
6b95a207
KH
10492 kfree(work);
10493}
10494
1afe3e9d 10495static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 10496 struct drm_crtc *crtc)
6b95a207 10497{
6b95a207
KH
10498 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10499 struct intel_unpin_work *work;
6b95a207
KH
10500 unsigned long flags;
10501
10502 /* Ignore early vblank irqs */
10503 if (intel_crtc == NULL)
10504 return;
10505
f326038a
DV
10506 /*
10507 * This is called both by irq handlers and the reset code (to complete
10508 * lost pageflips) so needs the full irqsave spinlocks.
10509 */
6b95a207
KH
10510 spin_lock_irqsave(&dev->event_lock, flags);
10511 work = intel_crtc->unpin_work;
e7d841ca
CW
10512
10513 /* Ensure we don't miss a work->pending update ... */
10514 smp_rmb();
10515
10516 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH
10517 spin_unlock_irqrestore(&dev->event_lock, flags);
10518 return;
10519 }
10520
d6bbafa1 10521 page_flip_completed(intel_crtc);
0af7e4df 10522
6b95a207 10523 spin_unlock_irqrestore(&dev->event_lock, flags);
6b95a207
KH
10524}
10525
1afe3e9d
JB
10526void intel_finish_page_flip(struct drm_device *dev, int pipe)
10527{
fbee40df 10528 struct drm_i915_private *dev_priv = dev->dev_private;
1afe3e9d
JB
10529 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10530
49b14a5c 10531 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB
10532}
10533
10534void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10535{
fbee40df 10536 struct drm_i915_private *dev_priv = dev->dev_private;
1afe3e9d
JB
10537 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10538
49b14a5c 10539 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB
10540}
10541
75f7f3ec
VS
10542/* Is 'a' after or equal to 'b'? */
10543static bool g4x_flip_count_after_eq(u32 a, u32 b)
10544{
10545 return !((a - b) & 0x80000000);
10546}
10547
10548static bool page_flip_finished(struct intel_crtc *crtc)
10549{
10550 struct drm_device *dev = crtc->base.dev;
10551 struct drm_i915_private *dev_priv = dev->dev_private;
10552
bdfa7542
VS
10553 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10554 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10555 return true;
10556
75f7f3ec
VS
10557 /*
10558 * The relevant registers doen't exist on pre-ctg.
10559 * As the flip done interrupt doesn't trigger for mmio
10560 * flips on gmch platforms, a flip count check isn't
10561 * really needed there. But since ctg has the registers,
10562 * include it in the check anyway.
10563 */
10564 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10565 return true;
10566
10567 /*
10568 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10569 * used the same base address. In that case the mmio flip might
10570 * have completed, but the CS hasn't even executed the flip yet.
10571 *
10572 * A flip count check isn't enough as the CS might have updated
10573 * the base address just after start of vblank, but before we
10574 * managed to process the interrupt. This means we'd complete the
10575 * CS flip too soon.
10576 *
10577 * Combining both checks should get us a good enough result. It may
10578 * still happen that the CS flip has been executed, but has not
10579 * yet actually completed. But in case the base address is the same
10580 * anyway, we don't really care.
10581 */
10582 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10583 crtc->unpin_work->gtt_offset &&
10584 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
10585 crtc->unpin_work->flip_count);
10586}
10587
6b95a207
KH
10588void intel_prepare_page_flip(struct drm_device *dev, int plane)
10589{
fbee40df 10590 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH
10591 struct intel_crtc *intel_crtc =
10592 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10593 unsigned long flags;
10594
f326038a
DV
10595
10596 /*
10597 * This is called both by irq handlers and the reset code (to complete
10598 * lost pageflips) so needs the full irqsave spinlocks.
10599 *
10600 * NB: An MMIO update of the plane base pointer will also
e7d841ca
CW
10601 * generate a page-flip completion irq, i.e. every modeset
10602 * is also accompanied by a spurious intel_prepare_page_flip().
10603 */
6b95a207 10604 spin_lock_irqsave(&dev->event_lock, flags);
75f7f3ec 10605 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
e7d841ca 10606 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH
10607 spin_unlock_irqrestore(&dev->event_lock, flags);
10608}
10609
eba905b2 10610static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
e7d841ca
CW
10611{
10612 /* Ensure that the work item is consistent when activating it ... */
10613 smp_wmb();
10614 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
10615 /* and that it is marked active as soon as the irq could fire. */
10616 smp_wmb();
10617}
10618
8c9f3aaf
JB
10619static int intel_gen2_queue_flip(struct drm_device *dev,
10620 struct drm_crtc *crtc,
10621 struct drm_framebuffer *fb,
ed8d1975 10622 struct drm_i915_gem_object *obj,
a4872ba6 10623 struct intel_engine_cs *ring,
ed8d1975 10624 uint32_t flags)
8c9f3aaf 10625{
8c9f3aaf 10626 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf
JB
10627 u32 flip_mask;
10628 int ret;
10629
6d90c952 10630 ret = intel_ring_begin(ring, 6);
8c9f3aaf 10631 if (ret)
4fa62c89 10632 return ret;
8c9f3aaf
JB
10633
10634 /* Can't queue multiple flips, so wait for the previous
10635 * one to finish before executing the next.
10636 */
10637 if (intel_crtc->plane)
10638 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10639 else
10640 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV
10641 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10642 intel_ring_emit(ring, MI_NOOP);
10643 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10644 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10645 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 10646 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
6d90c952 10647 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW
10648
10649 intel_mark_page_flip_active(intel_crtc);
09246732 10650 __intel_ring_advance(ring);
83d4092b 10651 return 0;
8c9f3aaf
JB
10652}
10653
10654static int intel_gen3_queue_flip(struct drm_device *dev,
10655 struct drm_crtc *crtc,
10656 struct drm_framebuffer *fb,
ed8d1975 10657 struct drm_i915_gem_object *obj,
a4872ba6 10658 struct intel_engine_cs *ring,
ed8d1975 10659 uint32_t flags)
8c9f3aaf 10660{
8c9f3aaf 10661 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf
JB
10662 u32 flip_mask;
10663 int ret;
10664
6d90c952 10665 ret = intel_ring_begin(ring, 6);
8c9f3aaf 10666 if (ret)
4fa62c89 10667 return ret;
8c9f3aaf
JB
10668
10669 if (intel_crtc->plane)
10670 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10671 else
10672 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV
10673 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10674 intel_ring_emit(ring, MI_NOOP);
10675 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
10676 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10677 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 10678 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
6d90c952
DV
10679 intel_ring_emit(ring, MI_NOOP);
10680
e7d841ca 10681 intel_mark_page_flip_active(intel_crtc);
09246732 10682 __intel_ring_advance(ring);
83d4092b 10683 return 0;
8c9f3aaf
JB
10684}
10685
10686static int intel_gen4_queue_flip(struct drm_device *dev,
10687 struct drm_crtc *crtc,
10688 struct drm_framebuffer *fb,
ed8d1975 10689 struct drm_i915_gem_object *obj,
a4872ba6 10690 struct intel_engine_cs *ring,
ed8d1975 10691 uint32_t flags)
8c9f3aaf
JB
10692{
10693 struct drm_i915_private *dev_priv = dev->dev_private;
10694 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10695 uint32_t pf, pipesrc;
10696 int ret;
10697
6d90c952 10698 ret = intel_ring_begin(ring, 4);
8c9f3aaf 10699 if (ret)
4fa62c89 10700 return ret;
8c9f3aaf
JB
10701
10702 /* i965+ uses the linear or tiled offsets from the
10703 * Display Registers (which do not change across a page-flip)
10704 * so we need only reprogram the base address.
10705 */
6d90c952
DV
10706 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10707 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10708 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 10709 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
c2c75131 10710 obj->tiling_mode);
8c9f3aaf
JB
10711
10712 /* XXX Enabling the panel-fitter across page-flip is so far
10713 * untested on non-native modes, so ignore it for now.
10714 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
10715 */
10716 pf = 0;
10717 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 10718 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW
10719
10720 intel_mark_page_flip_active(intel_crtc);
09246732 10721 __intel_ring_advance(ring);
83d4092b 10722 return 0;
8c9f3aaf
JB
10723}
10724
10725static int intel_gen6_queue_flip(struct drm_device *dev,
10726 struct drm_crtc *crtc,
10727 struct drm_framebuffer *fb,
ed8d1975 10728 struct drm_i915_gem_object *obj,
a4872ba6 10729 struct intel_engine_cs *ring,
ed8d1975 10730 uint32_t flags)
8c9f3aaf
JB
10731{
10732 struct drm_i915_private *dev_priv = dev->dev_private;
10733 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10734 uint32_t pf, pipesrc;
10735 int ret;
10736
6d90c952 10737 ret = intel_ring_begin(ring, 4);
8c9f3aaf 10738 if (ret)
4fa62c89 10739 return ret;
8c9f3aaf 10740
6d90c952
DV
10741 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10742 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10743 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
75f7f3ec 10744 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
8c9f3aaf 10745
dc257cf1
DV
10746 /* Contrary to the suggestions in the documentation,
10747 * "Enable Panel Fitter" does not seem to be required when page
10748 * flipping with a non-native mode, and worse causes a normal
10749 * modeset to fail.
10750 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
10751 */
10752 pf = 0;
8c9f3aaf 10753 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 10754 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW
10755
10756 intel_mark_page_flip_active(intel_crtc);
09246732 10757 __intel_ring_advance(ring);
83d4092b 10758 return 0;
8c9f3aaf
JB
10759}
10760
7c9017e5
JB
10761static int intel_gen7_queue_flip(struct drm_device *dev,
10762 struct drm_crtc *crtc,
10763 struct drm_framebuffer *fb,
ed8d1975 10764 struct drm_i915_gem_object *obj,
a4872ba6 10765 struct intel_engine_cs *ring,
ed8d1975 10766 uint32_t flags)
7c9017e5 10767{
7c9017e5 10768 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cb05d8de 10769 uint32_t plane_bit = 0;
ffe74d75
CW
10770 int len, ret;
10771
eba905b2 10772 switch (intel_crtc->plane) {
cb05d8de
DV
10773 case PLANE_A:
10774 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
10775 break;
10776 case PLANE_B:
10777 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
10778 break;
10779 case PLANE_C:
10780 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
10781 break;
10782 default:
10783 WARN_ONCE(1, "unknown plane in flip command\n");
4fa62c89 10784 return -ENODEV;
cb05d8de
DV
10785 }
10786
ffe74d75 10787 len = 4;
f476828a 10788 if (ring->id == RCS) {
ffe74d75 10789 len += 6;
f476828a
DL
10790 /*
10791 * On Gen 8, SRM is now taking an extra dword to accommodate
10792 * 48bits addresses, and we need a NOOP for the batch size to
10793 * stay even.
10794 */
10795 if (IS_GEN8(dev))
10796 len += 2;
10797 }
ffe74d75 10798
f66fab8e
VS
10799 /*
10800 * BSpec MI_DISPLAY_FLIP for IVB:
10801 * "The full packet must be contained within the same cache line."
10802 *
10803 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
10804 * cacheline, if we ever start emitting more commands before
10805 * the MI_DISPLAY_FLIP we may need to first emit everything else,
10806 * then do the cacheline alignment, and finally emit the
10807 * MI_DISPLAY_FLIP.
10808 */
10809 ret = intel_ring_cacheline_align(ring);
10810 if (ret)
4fa62c89 10811 return ret;
f66fab8e 10812
ffe74d75 10813 ret = intel_ring_begin(ring, len);
7c9017e5 10814 if (ret)
4fa62c89 10815 return ret;
7c9017e5 10816
ffe74d75
CW
10817 /* Unmask the flip-done completion message. Note that the bspec says that
10818 * we should do this for both the BCS and RCS, and that we must not unmask
10819 * more than one flip event at any time (or ensure that one flip message
10820 * can be sent by waiting for flip-done prior to queueing new flips).
10821 * Experimentation says that BCS works despite DERRMR masking all
10822 * flip-done completion events and that unmasking all planes at once
10823 * for the RCS also doesn't appear to drop events. Setting the DERRMR
10824 * to zero does lead to lockups within MI_DISPLAY_FLIP.
10825 */
10826 if (ring->id == RCS) {
10827 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
10828 intel_ring_emit(ring, DERRMR);
10829 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
10830 DERRMR_PIPEB_PRI_FLIP_DONE |
10831 DERRMR_PIPEC_PRI_FLIP_DONE));
f476828a
DL
10832 if (IS_GEN8(dev))
10833 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
10834 MI_SRM_LRM_GLOBAL_GTT);
10835 else
10836 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
10837 MI_SRM_LRM_GLOBAL_GTT);
ffe74d75
CW
10838 intel_ring_emit(ring, DERRMR);
10839 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
f476828a
DL
10840 if (IS_GEN8(dev)) {
10841 intel_ring_emit(ring, 0);
10842 intel_ring_emit(ring, MI_NOOP);
10843 }
ffe74d75
CW
10844 }
10845
cb05d8de 10846 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 10847 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
75f7f3ec 10848 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
7c9017e5 10849 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW
10850
10851 intel_mark_page_flip_active(intel_crtc);
09246732 10852 __intel_ring_advance(ring);
83d4092b 10853 return 0;
7c9017e5
JB
10854}
10855
84c33a64
SG
10856static bool use_mmio_flip(struct intel_engine_cs *ring,
10857 struct drm_i915_gem_object *obj)
10858{
10859 /*
10860 * This is not being used for older platforms, because
10861 * non-availability of flip done interrupt forces us to use
10862 * CS flips. Older platforms derive flip done using some clever
10863 * tricks involving the flip_pending status bits and vblank irqs.
10864 * So using MMIO flips there would disrupt this mechanism.
10865 */
10866
8e09bf83
CW
10867 if (ring == NULL)
10868 return true;
10869
84c33a64
SG
10870 if (INTEL_INFO(ring->dev)->gen < 5)
10871 return false;
10872
10873 if (i915.use_mmio_flip < 0)
10874 return false;
10875 else if (i915.use_mmio_flip > 0)
10876 return true;
14bf993e
OM
10877 else if (i915.enable_execlists)
10878 return true;
84c33a64 10879 else
b4716185 10880 return ring != i915_gem_request_get_ring(obj->last_write_req);
84c33a64
SG
10881}
10882
ff944564
DL
10883static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
10884{
10885 struct drm_device *dev = intel_crtc->base.dev;
10886 struct drm_i915_private *dev_priv = dev->dev_private;
10887 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
ff944564
DL
10888 const enum pipe pipe = intel_crtc->pipe;
10889 u32 ctl, stride;
10890
10891 ctl = I915_READ(PLANE_CTL(pipe, 0));
10892 ctl &= ~PLANE_CTL_TILED_MASK;
2ebef630
TU
10893 switch (fb->modifier[0]) {
10894 case DRM_FORMAT_MOD_NONE:
10895 break;
10896 case I915_FORMAT_MOD_X_TILED:
ff944564 10897 ctl |= PLANE_CTL_TILED_X;
2ebef630
TU
10898 break;
10899 case I915_FORMAT_MOD_Y_TILED:
10900 ctl |= PLANE_CTL_TILED_Y;
10901 break;
10902 case I915_FORMAT_MOD_Yf_TILED:
10903 ctl |= PLANE_CTL_TILED_YF;
10904 break;
10905 default:
10906 MISSING_CASE(fb->modifier[0]);
10907 }
ff944564
DL
10908
10909 /*
10910 * The stride is either expressed as a multiple of 64 bytes chunks for
10911 * linear buffers or in number of tiles for tiled buffers.
10912 */
2ebef630
TU
10913 stride = fb->pitches[0] /
10914 intel_fb_stride_alignment(dev, fb->modifier[0],
10915 fb->pixel_format);
ff944564
DL
10916
10917 /*
10918 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
10919 * PLANE_SURF updates, the update is then guaranteed to be atomic.
10920 */
10921 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
10922 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
10923
10924 I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
10925 POSTING_READ(PLANE_SURF(pipe, 0));
10926}
10927
10928static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
84c33a64
SG
10929{
10930 struct drm_device *dev = intel_crtc->base.dev;
10931 struct drm_i915_private *dev_priv = dev->dev_private;
10932 struct intel_framebuffer *intel_fb =
10933 to_intel_framebuffer(intel_crtc->base.primary->fb);
10934 struct drm_i915_gem_object *obj = intel_fb->obj;
10935 u32 dspcntr;
10936 u32 reg;
10937
84c33a64
SG
10938 reg = DSPCNTR(intel_crtc->plane);
10939 dspcntr = I915_READ(reg);
10940
c5d97472
DL
10941 if (obj->tiling_mode != I915_TILING_NONE)
10942 dspcntr |= DISPPLANE_TILED;
10943 else
10944 dspcntr &= ~DISPPLANE_TILED;
10945
84c33a64
SG
10946 I915_WRITE(reg, dspcntr);
10947
10948 I915_WRITE(DSPSURF(intel_crtc->plane),
10949 intel_crtc->unpin_work->gtt_offset);
10950 POSTING_READ(DSPSURF(intel_crtc->plane));
84c33a64 10951
ff944564
DL
10952}
10953
10954/*
10955 * XXX: This is the temporary way to update the plane registers until we get
10956 * around to using the usual plane update functions for MMIO flips
10957 */
10958static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
10959{
10960 struct drm_device *dev = intel_crtc->base.dev;
10961 bool atomic_update;
10962 u32 start_vbl_count;
10963
10964 intel_mark_page_flip_active(intel_crtc);
10965
10966 atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
10967
10968 if (INTEL_INFO(dev)->gen >= 9)
10969 skl_do_mmio_flip(intel_crtc);
10970 else
10971 /* use_mmio_flip() retricts MMIO flips to ilk+ */
10972 ilk_do_mmio_flip(intel_crtc);
10973
9362c7c5
ACO
10974 if (atomic_update)
10975 intel_pipe_update_end(intel_crtc, start_vbl_count);
84c33a64
SG
10976}
10977
9362c7c5 10978static void intel_mmio_flip_work_func(struct work_struct *work)
84c33a64 10979{
b2cfe0ab
CW
10980 struct intel_mmio_flip *mmio_flip =
10981 container_of(work, struct intel_mmio_flip, work);
84c33a64 10982
eed29a5b
DV
10983 if (mmio_flip->req)
10984 WARN_ON(__i915_wait_request(mmio_flip->req,
b2cfe0ab 10985 mmio_flip->crtc->reset_counter,
bcafc4e3
CW
10986 false, NULL,
10987 &mmio_flip->i915->rps.mmioflips));
84c33a64 10988
b2cfe0ab
CW
10989 intel_do_mmio_flip(mmio_flip->crtc);
10990
eed29a5b 10991 i915_gem_request_unreference__unlocked(mmio_flip->req);
b2cfe0ab 10992 kfree(mmio_flip);
84c33a64
SG
10993}
10994
10995static int intel_queue_mmio_flip(struct drm_device *dev,
10996 struct drm_crtc *crtc,
10997 struct drm_framebuffer *fb,
10998 struct drm_i915_gem_object *obj,
10999 struct intel_engine_cs *ring,
11000 uint32_t flags)
11001{
b2cfe0ab
CW
11002 struct intel_mmio_flip *mmio_flip;
11003
11004 mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11005 if (mmio_flip == NULL)
11006 return -ENOMEM;
84c33a64 11007
bcafc4e3 11008 mmio_flip->i915 = to_i915(dev);
eed29a5b 11009 mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
b2cfe0ab 11010 mmio_flip->crtc = to_intel_crtc(crtc);
536f5b5e 11011
b2cfe0ab
CW
11012 INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11013 schedule_work(&mmio_flip->work);
84c33a64 11014
84c33a64
SG
11015 return 0;
11016}
11017
8c9f3aaf
JB
11018static int intel_default_queue_flip(struct drm_device *dev,
11019 struct drm_crtc *crtc,
11020 struct drm_framebuffer *fb,
ed8d1975 11021 struct drm_i915_gem_object *obj,
a4872ba6 11022 struct intel_engine_cs *ring,
ed8d1975 11023 uint32_t flags)
8c9f3aaf
JB
11024{
11025 return -ENODEV;
11026}
11027
d6bbafa1
CW
11028static bool __intel_pageflip_stall_check(struct drm_device *dev,
11029 struct drm_crtc *crtc)
11030{
11031 struct drm_i915_private *dev_priv = dev->dev_private;
11032 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11033 struct intel_unpin_work *work = intel_crtc->unpin_work;
11034 u32 addr;
11035
11036 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11037 return true;
11038
11039 if (!work->enable_stall_check)
11040 return false;
11041
11042 if (work->flip_ready_vblank == 0) {
3a8a946e
DV
11043 if (work->flip_queued_req &&
11044 !i915_gem_request_completed(work->flip_queued_req, true))
d6bbafa1
CW
11045 return false;
11046
1e3feefd 11047 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
d6bbafa1
CW
11048 }
11049
1e3feefd 11050 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
d6bbafa1
CW
11051 return false;
11052
11053 /* Potential stall - if we see that the flip has happened,
11054 * assume a missed interrupt. */
11055 if (INTEL_INFO(dev)->gen >= 4)
11056 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11057 else
11058 addr = I915_READ(DSPADDR(intel_crtc->plane));
11059
11060 /* There is a potential issue here with a false positive after a flip
11061 * to the same address. We could address this by checking for a
11062 * non-incrementing frame counter.
11063 */
11064 return addr == work->gtt_offset;
11065}
11066
11067void intel_check_page_flip(struct drm_device *dev, int pipe)
11068{
11069 struct drm_i915_private *dev_priv = dev->dev_private;
11070 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11071 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6ad790c0 11072 struct intel_unpin_work *work;
f326038a 11073
6c51d46f 11074 WARN_ON(!in_interrupt());
d6bbafa1
CW
11075
11076 if (crtc == NULL)
11077 return;
11078
f326038a 11079 spin_lock(&dev->event_lock);
6ad790c0
CW
11080 work = intel_crtc->unpin_work;
11081 if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
d6bbafa1 11082 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
6ad790c0 11083 work->flip_queued_vblank, drm_vblank_count(dev, pipe));
d6bbafa1 11084 page_flip_completed(intel_crtc);
6ad790c0 11085 work = NULL;
d6bbafa1 11086 }
6ad790c0
CW
11087 if (work != NULL &&
11088 drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11089 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
f326038a 11090 spin_unlock(&dev->event_lock);
d6bbafa1
CW
11091}
11092
6b95a207
KH
11093static int intel_crtc_page_flip(struct drm_crtc *crtc,
11094 struct drm_framebuffer *fb,
ed8d1975
KP
11095 struct drm_pending_vblank_event *event,
11096 uint32_t page_flip_flags)
6b95a207
KH
11097{
11098 struct drm_device *dev = crtc->dev;
11099 struct drm_i915_private *dev_priv = dev->dev_private;
f4510a27 11100 struct drm_framebuffer *old_fb = crtc->primary->fb;
2ff8fde1 11101 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
6b95a207 11102 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
455a6808 11103 struct drm_plane *primary = crtc->primary;
a071fa00 11104 enum pipe pipe = intel_crtc->pipe;
6b95a207 11105 struct intel_unpin_work *work;
a4872ba6 11106 struct intel_engine_cs *ring;
cf5d8a46 11107 bool mmio_flip;
52e68630 11108 int ret;
6b95a207 11109
2ff8fde1
MR
11110 /*
11111 * drm_mode_page_flip_ioctl() should already catch this, but double
11112 * check to be safe. In the future we may enable pageflipping from
11113 * a disabled primary plane.
11114 */
11115 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11116 return -EBUSY;
11117
e6a595d2 11118 /* Can't change pixel format via MI display flips. */
f4510a27 11119 if (fb->pixel_format != crtc->primary->fb->pixel_format)
e6a595d2
VS
11120 return -EINVAL;
11121
11122 /*
11123 * TILEOFF/LINOFF registers can't be changed via MI display flips.
11124 * Note that pitch changes could also affect these register.
11125 */
11126 if (INTEL_INFO(dev)->gen > 3 &&
f4510a27
MR
11127 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11128 fb->pitches[0] != crtc->primary->fb->pitches[0]))
e6a595d2
VS
11129 return -EINVAL;
11130
f900db47
CW
11131 if (i915_terminally_wedged(&dev_priv->gpu_error))
11132 goto out_hang;
11133
b14c5679 11134 work = kzalloc(sizeof(*work), GFP_KERNEL);
6b95a207
KH
11135 if (work == NULL)
11136 return -ENOMEM;
11137
6b95a207 11138 work->event = event;
b4a98e57 11139 work->crtc = crtc;
ab8d6675 11140 work->old_fb = old_fb;
6b95a207
KH
11141 INIT_WORK(&work->work, intel_unpin_work_fn);
11142
87b6b101 11143 ret = drm_crtc_vblank_get(crtc);
7317c75e
JB
11144 if (ret)
11145 goto free_work;
11146
6b95a207 11147 /* We borrow the event spin lock for protecting unpin_work */
5e2d7afc 11148 spin_lock_irq(&dev->event_lock);
6b95a207 11149 if (intel_crtc->unpin_work) {
d6bbafa1
CW
11150 /* Before declaring the flip queue wedged, check if
11151 * the hardware completed the operation behind our backs.
11152 */
11153 if (__intel_pageflip_stall_check(dev, crtc)) {
11154 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11155 page_flip_completed(intel_crtc);
11156 } else {
11157 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
5e2d7afc 11158 spin_unlock_irq(&dev->event_lock);
468f0b44 11159
d6bbafa1
CW
11160 drm_crtc_vblank_put(crtc);
11161 kfree(work);
11162 return -EBUSY;
11163 }
6b95a207
KH
11164 }
11165 intel_crtc->unpin_work = work;
5e2d7afc 11166 spin_unlock_irq(&dev->event_lock);
6b95a207 11167
b4a98e57
CW
11168 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11169 flush_workqueue(dev_priv->wq);
11170
75dfca80 11171 /* Reference the objects for the scheduled work. */
ab8d6675 11172 drm_framebuffer_reference(work->old_fb);
05394f39 11173 drm_gem_object_reference(&obj->base);
6b95a207 11174
f4510a27 11175 crtc->primary->fb = fb;
afd65eb4 11176 update_state_fb(crtc->primary);
1ed1f968 11177
e1f99ce6 11178 work->pending_flip_obj = obj;
e1f99ce6 11179
89ed88ba
CW
11180 ret = i915_mutex_lock_interruptible(dev);
11181 if (ret)
11182 goto cleanup;
11183
b4a98e57 11184 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 11185 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 11186
75f7f3ec 11187 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
a071fa00 11188 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
75f7f3ec 11189
4fa62c89
VS
11190 if (IS_VALLEYVIEW(dev)) {
11191 ring = &dev_priv->ring[BCS];
ab8d6675 11192 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
8e09bf83
CW
11193 /* vlv: DISPLAY_FLIP fails to change tiling */
11194 ring = NULL;
48bf5b2d 11195 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
2a92d5bc 11196 ring = &dev_priv->ring[BCS];
4fa62c89 11197 } else if (INTEL_INFO(dev)->gen >= 7) {
b4716185 11198 ring = i915_gem_request_get_ring(obj->last_write_req);
4fa62c89
VS
11199 if (ring == NULL || ring->id != RCS)
11200 ring = &dev_priv->ring[BCS];
11201 } else {
11202 ring = &dev_priv->ring[RCS];
11203 }
11204
cf5d8a46
CW
11205 mmio_flip = use_mmio_flip(ring, obj);
11206
11207 /* When using CS flips, we want to emit semaphores between rings.
11208 * However, when using mmio flips we will create a task to do the
11209 * synchronisation, so all we want here is to pin the framebuffer
11210 * into the display plane and skip any waits.
11211 */
82bc3b2d 11212 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
cf5d8a46 11213 crtc->primary->state,
b4716185 11214 mmio_flip ? i915_gem_request_get_ring(obj->last_write_req) : ring);
8c9f3aaf
JB
11215 if (ret)
11216 goto cleanup_pending;
6b95a207 11217
121920fa
TU
11218 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj)
11219 + intel_crtc->dspaddr_offset;
4fa62c89 11220
cf5d8a46 11221 if (mmio_flip) {
84c33a64
SG
11222 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
11223 page_flip_flags);
d6bbafa1
CW
11224 if (ret)
11225 goto cleanup_unpin;
11226
f06cc1b9
JH
11227 i915_gem_request_assign(&work->flip_queued_req,
11228 obj->last_write_req);
d6bbafa1 11229 } else {
d94b5030
CW
11230 if (obj->last_write_req) {
11231 ret = i915_gem_check_olr(obj->last_write_req);
11232 if (ret)
11233 goto cleanup_unpin;
11234 }
11235
84c33a64 11236 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
d6bbafa1
CW
11237 page_flip_flags);
11238 if (ret)
11239 goto cleanup_unpin;
11240
f06cc1b9
JH
11241 i915_gem_request_assign(&work->flip_queued_req,
11242 intel_ring_get_request(ring));
d6bbafa1
CW
11243 }
11244
1e3feefd 11245 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
d6bbafa1 11246 work->enable_stall_check = true;
4fa62c89 11247
ab8d6675 11248 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
a071fa00
DV
11249 INTEL_FRONTBUFFER_PRIMARY(pipe));
11250
7ff0ebcc 11251 intel_fbc_disable(dev);
f99d7069 11252 intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
6b95a207
KH
11253 mutex_unlock(&dev->struct_mutex);
11254
e5510fac
JB
11255 trace_i915_flip_request(intel_crtc->plane, obj);
11256
6b95a207 11257 return 0;
96b099fd 11258
4fa62c89 11259cleanup_unpin:
82bc3b2d 11260 intel_unpin_fb_obj(fb, crtc->primary->state);
8c9f3aaf 11261cleanup_pending:
b4a98e57 11262 atomic_dec(&intel_crtc->unpin_work_count);
89ed88ba
CW
11263 mutex_unlock(&dev->struct_mutex);
11264cleanup:
f4510a27 11265 crtc->primary->fb = old_fb;
afd65eb4 11266 update_state_fb(crtc->primary);
89ed88ba
CW
11267
11268 drm_gem_object_unreference_unlocked(&obj->base);
ab8d6675 11269 drm_framebuffer_unreference(work->old_fb);
96b099fd 11270
5e2d7afc 11271 spin_lock_irq(&dev->event_lock);
96b099fd 11272 intel_crtc->unpin_work = NULL;
5e2d7afc 11273 spin_unlock_irq(&dev->event_lock);
96b099fd 11274
87b6b101 11275 drm_crtc_vblank_put(crtc);
7317c75e 11276free_work:
96b099fd
CW
11277 kfree(work);
11278
f900db47
CW
11279 if (ret == -EIO) {
11280out_hang:
53a366b9 11281 ret = intel_plane_restore(primary);
f0d3dad3 11282 if (ret == 0 && event) {
5e2d7afc 11283 spin_lock_irq(&dev->event_lock);
a071fa00 11284 drm_send_vblank_event(dev, pipe, event);
5e2d7afc 11285 spin_unlock_irq(&dev->event_lock);
f0d3dad3 11286 }
f900db47 11287 }
96b099fd 11288 return ret;
6b95a207
KH
11289}
11290
65b38e0d 11291static const struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW
11292 .mode_set_base_atomic = intel_pipe_set_base_atomic,
11293 .load_lut = intel_crtc_load_lut,
ea2c67bb
MR
11294 .atomic_begin = intel_begin_crtc_commit,
11295 .atomic_flush = intel_finish_crtc_commit,
f6e5b160
CW
11296};
11297
9a935856
DV
11298/**
11299 * intel_modeset_update_staged_output_state
11300 *
11301 * Updates the staged output configuration state, e.g. after we've read out the
11302 * current hw state.
11303 */
11304static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 11305{
7668851f 11306 struct intel_crtc *crtc;
9a935856
DV
11307 struct intel_encoder *encoder;
11308 struct intel_connector *connector;
f6e5b160 11309
3a3371ff 11310 for_each_intel_connector(dev, connector) {
9a935856
DV
11311 connector->new_encoder =
11312 to_intel_encoder(connector->base.encoder);
11313 }
f6e5b160 11314
b2784e15 11315 for_each_intel_encoder(dev, encoder) {
9a935856
DV
11316 encoder->new_crtc =
11317 to_intel_crtc(encoder->base.crtc);
11318 }
7668851f 11319
d3fcc808 11320 for_each_intel_crtc(dev, crtc) {
83d65738 11321 crtc->new_enabled = crtc->base.state->enable;
7668851f 11322 }
f6e5b160
CW
11323}
11324
d29b2f9d
ACO
11325/* Transitional helper to copy current connector/encoder state to
11326 * connector->state. This is needed so that code that is partially
11327 * converted to atomic does the right thing.
11328 */
11329static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11330{
11331 struct intel_connector *connector;
11332
11333 for_each_intel_connector(dev, connector) {
11334 if (connector->base.encoder) {
11335 connector->base.state->best_encoder =
11336 connector->base.encoder;
11337 connector->base.state->crtc =
11338 connector->base.encoder->crtc;
11339 } else {
11340 connector->base.state->best_encoder = NULL;
11341 connector->base.state->crtc = NULL;
11342 }
11343 }
11344}
11345
a821fc46 11346/* Fixup legacy state after an atomic state swap.
9a935856 11347 */
a821fc46 11348static void intel_modeset_fixup_state(struct drm_atomic_state *state)
9a935856 11349{
a821fc46 11350 struct intel_crtc *crtc;
9a935856 11351 struct intel_encoder *encoder;
a821fc46 11352 struct intel_connector *connector;
d5432a9d 11353
a821fc46
ACO
11354 for_each_intel_connector(state->dev, connector) {
11355 connector->base.encoder = connector->base.state->best_encoder;
11356 if (connector->base.encoder)
11357 connector->base.encoder->crtc =
11358 connector->base.state->crtc;
9a935856 11359 }
f6e5b160 11360
d5432a9d
ACO
11361 /* Update crtc of disabled encoders */
11362 for_each_intel_encoder(state->dev, encoder) {
11363 int num_connectors = 0;
11364
a821fc46
ACO
11365 for_each_intel_connector(state->dev, connector)
11366 if (connector->base.encoder == &encoder->base)
d5432a9d
ACO
11367 num_connectors++;
11368
11369 if (num_connectors == 0)
11370 encoder->base.crtc = NULL;
9a935856 11371 }
7668851f 11372
a821fc46
ACO
11373 for_each_intel_crtc(state->dev, crtc) {
11374 crtc->base.enabled = crtc->base.state->enable;
11375 crtc->config = to_intel_crtc_state(crtc->base.state);
7668851f 11376 }
d29b2f9d 11377
d5432a9d
ACO
11378 /* Copy the new configuration to the staged state, to keep the few
11379 * pieces of code that haven't been converted yet happy */
11380 intel_modeset_update_staged_output_state(state->dev);
9a935856
DV
11381}
11382
050f7aeb 11383static void
eba905b2 11384connected_sink_compute_bpp(struct intel_connector *connector,
5cec258b 11385 struct intel_crtc_state *pipe_config)
050f7aeb
DV
11386{
11387 int bpp = pipe_config->pipe_bpp;
11388
11389 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11390 connector->base.base.id,
c23cc417 11391 connector->base.name);
050f7aeb
DV
11392
11393 /* Don't use an invalid EDID bpc value */
11394 if (connector->base.display_info.bpc &&
11395 connector->base.display_info.bpc * 3 < bpp) {
11396 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11397 bpp, connector->base.display_info.bpc*3);
11398 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11399 }
11400
11401 /* Clamp bpp to 8 on screens without EDID 1.4 */
11402 if (connector->base.display_info.bpc == 0 && bpp > 24) {
11403 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11404 bpp);
11405 pipe_config->pipe_bpp = 24;
11406 }
11407}
11408
4e53c2e0 11409static int
050f7aeb 11410compute_baseline_pipe_bpp(struct intel_crtc *crtc,
5cec258b 11411 struct intel_crtc_state *pipe_config)
4e53c2e0 11412{
050f7aeb 11413 struct drm_device *dev = crtc->base.dev;
1486017f 11414 struct drm_atomic_state *state;
da3ced29
ACO
11415 struct drm_connector *connector;
11416 struct drm_connector_state *connector_state;
1486017f 11417 int bpp, i;
4e53c2e0 11418
d328c9d7 11419 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
4e53c2e0 11420 bpp = 10*3;
d328c9d7
DV
11421 else if (INTEL_INFO(dev)->gen >= 5)
11422 bpp = 12*3;
11423 else
11424 bpp = 8*3;
11425
4e53c2e0 11426
4e53c2e0
DV
11427 pipe_config->pipe_bpp = bpp;
11428
1486017f
ACO
11429 state = pipe_config->base.state;
11430
4e53c2e0 11431 /* Clamp display bpp to EDID value */
da3ced29
ACO
11432 for_each_connector_in_state(state, connector, connector_state, i) {
11433 if (connector_state->crtc != &crtc->base)
4e53c2e0
DV
11434 continue;
11435
da3ced29
ACO
11436 connected_sink_compute_bpp(to_intel_connector(connector),
11437 pipe_config);
4e53c2e0
DV
11438 }
11439
11440 return bpp;
11441}
11442
644db711
DV
11443static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11444{
11445 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11446 "type: 0x%x flags: 0x%x\n",
1342830c 11447 mode->crtc_clock,
644db711
DV
11448 mode->crtc_hdisplay, mode->crtc_hsync_start,
11449 mode->crtc_hsync_end, mode->crtc_htotal,
11450 mode->crtc_vdisplay, mode->crtc_vsync_start,
11451 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11452}
11453
c0b03411 11454static void intel_dump_pipe_config(struct intel_crtc *crtc,
5cec258b 11455 struct intel_crtc_state *pipe_config,
c0b03411
DV
11456 const char *context)
11457{
6a60cd87
CK
11458 struct drm_device *dev = crtc->base.dev;
11459 struct drm_plane *plane;
11460 struct intel_plane *intel_plane;
11461 struct intel_plane_state *state;
11462 struct drm_framebuffer *fb;
11463
11464 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
11465 context, pipe_config, pipe_name(crtc->pipe));
c0b03411
DV
11466
11467 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
11468 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
11469 pipe_config->pipe_bpp, pipe_config->dither);
11470 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11471 pipe_config->has_pch_encoder,
11472 pipe_config->fdi_lanes,
11473 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
11474 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
11475 pipe_config->fdi_m_n.tu);
eb14cb74
VS
11476 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11477 pipe_config->has_dp_encoder,
11478 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
11479 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
11480 pipe_config->dp_m_n.tu);
b95af8be
VK
11481
11482 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
11483 pipe_config->has_dp_encoder,
11484 pipe_config->dp_m2_n2.gmch_m,
11485 pipe_config->dp_m2_n2.gmch_n,
11486 pipe_config->dp_m2_n2.link_m,
11487 pipe_config->dp_m2_n2.link_n,
11488 pipe_config->dp_m2_n2.tu);
11489
55072d19
DV
11490 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11491 pipe_config->has_audio,
11492 pipe_config->has_infoframe);
11493
c0b03411 11494 DRM_DEBUG_KMS("requested mode:\n");
2d112de7 11495 drm_mode_debug_printmodeline(&pipe_config->base.mode);
c0b03411 11496 DRM_DEBUG_KMS("adjusted mode:\n");
2d112de7
ACO
11497 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
11498 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
d71b8d4a 11499 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
37327abd
VS
11500 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
11501 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
0ec463d3
TU
11502 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
11503 crtc->num_scalers,
11504 pipe_config->scaler_state.scaler_users,
11505 pipe_config->scaler_state.scaler_id);
c0b03411
DV
11506 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11507 pipe_config->gmch_pfit.control,
11508 pipe_config->gmch_pfit.pgm_ratios,
11509 pipe_config->gmch_pfit.lvds_border_bits);
fd4daa9c 11510 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
c0b03411 11511 pipe_config->pch_pfit.pos,
fd4daa9c
CW
11512 pipe_config->pch_pfit.size,
11513 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
42db64ef 11514 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
cf532bb2 11515 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
6a60cd87 11516
415ff0f6
TU
11517 if (IS_BROXTON(dev)) {
11518 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, "
11519 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
11520 "pll6: 0x%x, pll8: 0x%x, pcsdw12: 0x%x\n",
11521 pipe_config->ddi_pll_sel,
11522 pipe_config->dpll_hw_state.ebb0,
11523 pipe_config->dpll_hw_state.pll0,
11524 pipe_config->dpll_hw_state.pll1,
11525 pipe_config->dpll_hw_state.pll2,
11526 pipe_config->dpll_hw_state.pll3,
11527 pipe_config->dpll_hw_state.pll6,
11528 pipe_config->dpll_hw_state.pll8,
11529 pipe_config->dpll_hw_state.pcsdw12);
11530 } else if (IS_SKYLAKE(dev)) {
11531 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
11532 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
11533 pipe_config->ddi_pll_sel,
11534 pipe_config->dpll_hw_state.ctrl1,
11535 pipe_config->dpll_hw_state.cfgcr1,
11536 pipe_config->dpll_hw_state.cfgcr2);
11537 } else if (HAS_DDI(dev)) {
11538 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x\n",
11539 pipe_config->ddi_pll_sel,
11540 pipe_config->dpll_hw_state.wrpll);
11541 } else {
11542 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
11543 "fp0: 0x%x, fp1: 0x%x\n",
11544 pipe_config->dpll_hw_state.dpll,
11545 pipe_config->dpll_hw_state.dpll_md,
11546 pipe_config->dpll_hw_state.fp0,
11547 pipe_config->dpll_hw_state.fp1);
11548 }
11549
6a60cd87
CK
11550 DRM_DEBUG_KMS("planes on this crtc\n");
11551 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
11552 intel_plane = to_intel_plane(plane);
11553 if (intel_plane->pipe != crtc->pipe)
11554 continue;
11555
11556 state = to_intel_plane_state(plane->state);
11557 fb = state->base.fb;
11558 if (!fb) {
11559 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
11560 "disabled, scaler_id = %d\n",
11561 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
11562 plane->base.id, intel_plane->pipe,
11563 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
11564 drm_plane_index(plane), state->scaler_id);
11565 continue;
11566 }
11567
11568 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
11569 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
11570 plane->base.id, intel_plane->pipe,
11571 crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
11572 drm_plane_index(plane));
11573 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
11574 fb->base.id, fb->width, fb->height, fb->pixel_format);
11575 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
11576 state->scaler_id,
11577 state->src.x1 >> 16, state->src.y1 >> 16,
11578 drm_rect_width(&state->src) >> 16,
11579 drm_rect_height(&state->src) >> 16,
11580 state->dst.x1, state->dst.y1,
11581 drm_rect_width(&state->dst), drm_rect_height(&state->dst));
11582 }
c0b03411
DV
11583}
11584
bc079e8b
VS
11585static bool encoders_cloneable(const struct intel_encoder *a,
11586 const struct intel_encoder *b)
accfc0c5 11587{
bc079e8b
VS
11588 /* masks could be asymmetric, so check both ways */
11589 return a == b || (a->cloneable & (1 << b->type) &&
11590 b->cloneable & (1 << a->type));
11591}
11592
98a221da
ACO
11593static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11594 struct intel_crtc *crtc,
bc079e8b
VS
11595 struct intel_encoder *encoder)
11596{
bc079e8b 11597 struct intel_encoder *source_encoder;
da3ced29 11598 struct drm_connector *connector;
98a221da
ACO
11599 struct drm_connector_state *connector_state;
11600 int i;
bc079e8b 11601
da3ced29 11602 for_each_connector_in_state(state, connector, connector_state, i) {
98a221da 11603 if (connector_state->crtc != &crtc->base)
bc079e8b
VS
11604 continue;
11605
98a221da
ACO
11606 source_encoder =
11607 to_intel_encoder(connector_state->best_encoder);
bc079e8b
VS
11608 if (!encoders_cloneable(encoder, source_encoder))
11609 return false;
11610 }
11611
11612 return true;
11613}
11614
98a221da
ACO
11615static bool check_encoder_cloning(struct drm_atomic_state *state,
11616 struct intel_crtc *crtc)
bc079e8b 11617{
accfc0c5 11618 struct intel_encoder *encoder;
da3ced29 11619 struct drm_connector *connector;
98a221da
ACO
11620 struct drm_connector_state *connector_state;
11621 int i;
accfc0c5 11622
da3ced29 11623 for_each_connector_in_state(state, connector, connector_state, i) {
98a221da
ACO
11624 if (connector_state->crtc != &crtc->base)
11625 continue;
11626
11627 encoder = to_intel_encoder(connector_state->best_encoder);
11628 if (!check_single_encoder_cloning(state, crtc, encoder))
bc079e8b 11629 return false;
accfc0c5
DV
11630 }
11631
bc079e8b 11632 return true;
accfc0c5
DV
11633}
11634
5448a00d 11635static bool check_digital_port_conflicts(struct drm_atomic_state *state)
00f0b378 11636{
5448a00d
ACO
11637 struct drm_device *dev = state->dev;
11638 struct intel_encoder *encoder;
da3ced29 11639 struct drm_connector *connector;
5448a00d 11640 struct drm_connector_state *connector_state;
00f0b378 11641 unsigned int used_ports = 0;
5448a00d 11642 int i;
00f0b378
VS
11643
11644 /*
11645 * Walk the connector list instead of the encoder
11646 * list to detect the problem on ddi platforms
11647 * where there's just one encoder per digital port.
11648 */
da3ced29 11649 for_each_connector_in_state(state, connector, connector_state, i) {
5448a00d 11650 if (!connector_state->best_encoder)
00f0b378
VS
11651 continue;
11652
5448a00d
ACO
11653 encoder = to_intel_encoder(connector_state->best_encoder);
11654
11655 WARN_ON(!connector_state->crtc);
00f0b378
VS
11656
11657 switch (encoder->type) {
11658 unsigned int port_mask;
11659 case INTEL_OUTPUT_UNKNOWN:
11660 if (WARN_ON(!HAS_DDI(dev)))
11661 break;
11662 case INTEL_OUTPUT_DISPLAYPORT:
11663 case INTEL_OUTPUT_HDMI:
11664 case INTEL_OUTPUT_EDP:
11665 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
11666
11667 /* the same port mustn't appear more than once */
11668 if (used_ports & port_mask)
11669 return false;
11670
11671 used_ports |= port_mask;
11672 default:
11673 break;
11674 }
11675 }
11676
11677 return true;
11678}
11679
83a57153
ACO
11680static void
11681clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
11682{
11683 struct drm_crtc_state tmp_state;
663a3640 11684 struct intel_crtc_scaler_state scaler_state;
4978cc93
ACO
11685 struct intel_dpll_hw_state dpll_hw_state;
11686 enum intel_dpll_id shared_dpll;
8504c74c 11687 uint32_t ddi_pll_sel;
83a57153 11688
7546a384
ACO
11689 /* FIXME: before the switch to atomic started, a new pipe_config was
11690 * kzalloc'd. Code that depends on any field being zero should be
11691 * fixed, so that the crtc_state can be safely duplicated. For now,
11692 * only fields that are know to not cause problems are preserved. */
11693
83a57153 11694 tmp_state = crtc_state->base;
663a3640 11695 scaler_state = crtc_state->scaler_state;
4978cc93
ACO
11696 shared_dpll = crtc_state->shared_dpll;
11697 dpll_hw_state = crtc_state->dpll_hw_state;
8504c74c 11698 ddi_pll_sel = crtc_state->ddi_pll_sel;
4978cc93 11699
83a57153 11700 memset(crtc_state, 0, sizeof *crtc_state);
4978cc93 11701
83a57153 11702 crtc_state->base = tmp_state;
663a3640 11703 crtc_state->scaler_state = scaler_state;
4978cc93
ACO
11704 crtc_state->shared_dpll = shared_dpll;
11705 crtc_state->dpll_hw_state = dpll_hw_state;
8504c74c 11706 crtc_state->ddi_pll_sel = ddi_pll_sel;
83a57153
ACO
11707}
11708
548ee15b 11709static int
b8cecdf5 11710intel_modeset_pipe_config(struct drm_crtc *crtc,
548ee15b
ACO
11711 struct drm_atomic_state *state,
11712 struct intel_crtc_state *pipe_config)
ee7b9f93 11713{
7758a113 11714 struct intel_encoder *encoder;
da3ced29 11715 struct drm_connector *connector;
0b901879 11716 struct drm_connector_state *connector_state;
d328c9d7 11717 int base_bpp, ret = -EINVAL;
0b901879 11718 int i;
e29c22c0 11719 bool retry = true;
ee7b9f93 11720
98a221da 11721 if (!check_encoder_cloning(state, to_intel_crtc(crtc))) {
accfc0c5 11722 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
548ee15b 11723 return -EINVAL;
accfc0c5
DV
11724 }
11725
5448a00d 11726 if (!check_digital_port_conflicts(state)) {
00f0b378 11727 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
548ee15b 11728 return -EINVAL;
00f0b378
VS
11729 }
11730
83a57153 11731 clear_intel_crtc_state(pipe_config);
7758a113 11732
e143a21c
DV
11733 pipe_config->cpu_transcoder =
11734 (enum transcoder) to_intel_crtc(crtc)->pipe;
b8cecdf5 11735
2960bc9c
ID
11736 /*
11737 * Sanitize sync polarity flags based on requested ones. If neither
11738 * positive or negative polarity is requested, treat this as meaning
11739 * negative polarity.
11740 */
2d112de7 11741 if (!(pipe_config->base.adjusted_mode.flags &
2960bc9c 11742 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
2d112de7 11743 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
2960bc9c 11744
2d112de7 11745 if (!(pipe_config->base.adjusted_mode.flags &
2960bc9c 11746 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
2d112de7 11747 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
2960bc9c 11748
050f7aeb
DV
11749 /* Compute a starting value for pipe_config->pipe_bpp taking the source
11750 * plane pixel format and any sink constraints into account. Returns the
11751 * source plane bpp so that dithering can be selected on mismatches
11752 * after encoders and crtc also have had their say. */
d328c9d7
DV
11753 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
11754 pipe_config);
11755 if (base_bpp < 0)
4e53c2e0
DV
11756 goto fail;
11757
e41a56be
VS
11758 /*
11759 * Determine the real pipe dimensions. Note that stereo modes can
11760 * increase the actual pipe size due to the frame doubling and
11761 * insertion of additional space for blanks between the frame. This
11762 * is stored in the crtc timings. We use the requested mode to do this
11763 * computation to clearly distinguish it from the adjusted mode, which
11764 * can be changed by the connectors in the below retry loop.
11765 */
2d112de7 11766 drm_crtc_get_hv_timing(&pipe_config->base.mode,
ecb7e16b
GP
11767 &pipe_config->pipe_src_w,
11768 &pipe_config->pipe_src_h);
e41a56be 11769
e29c22c0 11770encoder_retry:
ef1b460d 11771 /* Ensure the port clock defaults are reset when retrying. */
ff9a6750 11772 pipe_config->port_clock = 0;
ef1b460d 11773 pipe_config->pixel_multiplier = 1;
ff9a6750 11774
135c81b8 11775 /* Fill in default crtc timings, allow encoders to overwrite them. */
2d112de7
ACO
11776 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
11777 CRTC_STEREO_DOUBLE);
135c81b8 11778
7758a113
DV
11779 /* Pass our mode to the connectors and the CRTC to give them a chance to
11780 * adjust it according to limitations or connector properties, and also
11781 * a chance to reject the mode entirely.
47f1c6c9 11782 */
da3ced29 11783 for_each_connector_in_state(state, connector, connector_state, i) {
0b901879 11784 if (connector_state->crtc != crtc)
7758a113 11785 continue;
7ae89233 11786
0b901879
ACO
11787 encoder = to_intel_encoder(connector_state->best_encoder);
11788
efea6e8e
DV
11789 if (!(encoder->compute_config(encoder, pipe_config))) {
11790 DRM_DEBUG_KMS("Encoder config failure\n");
7758a113
DV
11791 goto fail;
11792 }
ee7b9f93 11793 }
47f1c6c9 11794
ff9a6750
DV
11795 /* Set default port clock if not overwritten by the encoder. Needs to be
11796 * done afterwards in case the encoder adjusts the mode. */
11797 if (!pipe_config->port_clock)
2d112de7 11798 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
241bfc38 11799 * pipe_config->pixel_multiplier;
ff9a6750 11800
a43f6e0f 11801 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
e29c22c0 11802 if (ret < 0) {
7758a113
DV
11803 DRM_DEBUG_KMS("CRTC fixup failed\n");
11804 goto fail;
ee7b9f93 11805 }
e29c22c0
DV
11806
11807 if (ret == RETRY) {
11808 if (WARN(!retry, "loop in pipe configuration computation\n")) {
11809 ret = -EINVAL;
11810 goto fail;
11811 }
11812
11813 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
11814 retry = false;
11815 goto encoder_retry;
11816 }
11817
d328c9d7 11818 pipe_config->dither = pipe_config->pipe_bpp != base_bpp;
4e53c2e0 11819 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
d328c9d7 11820 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
4e53c2e0 11821
548ee15b 11822 return 0;
7758a113 11823fail:
548ee15b 11824 return ret;
ee7b9f93 11825}
47f1c6c9 11826
ea9d758d 11827static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 11828{
ea9d758d 11829 struct drm_encoder *encoder;
f6e5b160 11830 struct drm_device *dev = crtc->dev;
f6e5b160 11831
ea9d758d
DV
11832 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
11833 if (encoder->crtc == crtc)
11834 return true;
11835
11836 return false;
11837}
11838
0a9ab303
ACO
11839static bool
11840needs_modeset(struct drm_crtc_state *state)
11841{
11842 return state->mode_changed || state->active_changed;
11843}
11844
ea9d758d 11845static void
0a9ab303 11846intel_modeset_update_state(struct drm_atomic_state *state)
ea9d758d 11847{
0a9ab303 11848 struct drm_device *dev = state->dev;
ba41c0de 11849 struct drm_i915_private *dev_priv = dev->dev_private;
ea9d758d 11850 struct intel_encoder *intel_encoder;
0a9ab303
ACO
11851 struct drm_crtc *crtc;
11852 struct drm_crtc_state *crtc_state;
ea9d758d 11853 struct drm_connector *connector;
0a9ab303 11854 int i;
ea9d758d 11855
ba41c0de
DV
11856 intel_shared_dpll_commit(dev_priv);
11857
b2784e15 11858 for_each_intel_encoder(dev, intel_encoder) {
ea9d758d
DV
11859 if (!intel_encoder->base.crtc)
11860 continue;
11861
0a9ab303
ACO
11862 for_each_crtc_in_state(state, crtc, crtc_state, i)
11863 if (crtc == intel_encoder->base.crtc)
11864 break;
11865
11866 if (crtc != intel_encoder->base.crtc)
11867 continue;
ea9d758d 11868
0a9ab303 11869 if (crtc_state->enable && needs_modeset(crtc_state))
ea9d758d
DV
11870 intel_encoder->connectors_active = false;
11871 }
11872
a821fc46
ACO
11873 drm_atomic_helper_swap_state(state->dev, state);
11874 intel_modeset_fixup_state(state);
ea9d758d 11875
7668851f 11876 /* Double check state. */
0a9ab303
ACO
11877 for_each_crtc(dev, crtc) {
11878 WARN_ON(crtc->state->enable != intel_crtc_in_use(crtc));
ea9d758d
DV
11879 }
11880
11881 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11882 if (!connector->encoder || !connector->encoder->crtc)
11883 continue;
11884
0a9ab303
ACO
11885 for_each_crtc_in_state(state, crtc, crtc_state, i)
11886 if (crtc == connector->encoder->crtc)
11887 break;
11888
11889 if (crtc != connector->encoder->crtc)
11890 continue;
ea9d758d 11891
a821fc46 11892 if (crtc->state->enable && needs_modeset(crtc->state)) {
68d34720
DV
11893 struct drm_property *dpms_property =
11894 dev->mode_config.dpms_property;
11895
ea9d758d 11896 connector->dpms = DRM_MODE_DPMS_ON;
662595df 11897 drm_object_property_set_value(&connector->base,
68d34720
DV
11898 dpms_property,
11899 DRM_MODE_DPMS_ON);
ea9d758d
DV
11900
11901 intel_encoder = to_intel_encoder(connector->encoder);
11902 intel_encoder->connectors_active = true;
11903 }
11904 }
11905
11906}
11907
3bd26263 11908static bool intel_fuzzy_clock_check(int clock1, int clock2)
f1f644dc 11909{
3bd26263 11910 int diff;
f1f644dc
JB
11911
11912 if (clock1 == clock2)
11913 return true;
11914
11915 if (!clock1 || !clock2)
11916 return false;
11917
11918 diff = abs(clock1 - clock2);
11919
11920 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
11921 return true;
11922
11923 return false;
11924}
11925
25c5b266
DV
11926#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
11927 list_for_each_entry((intel_crtc), \
11928 &(dev)->mode_config.crtc_list, \
11929 base.head) \
0973f18f 11930 if (mask & (1 <<(intel_crtc)->pipe))
25c5b266 11931
0e8ffe1b 11932static bool
2fa2fe9a 11933intel_pipe_config_compare(struct drm_device *dev,
5cec258b
ACO
11934 struct intel_crtc_state *current_config,
11935 struct intel_crtc_state *pipe_config)
0e8ffe1b 11936{
66e985c0
DV
11937#define PIPE_CONF_CHECK_X(name) \
11938 if (current_config->name != pipe_config->name) { \
11939 DRM_ERROR("mismatch in " #name " " \
11940 "(expected 0x%08x, found 0x%08x)\n", \
11941 current_config->name, \
11942 pipe_config->name); \
11943 return false; \
11944 }
11945
08a24034
DV
11946#define PIPE_CONF_CHECK_I(name) \
11947 if (current_config->name != pipe_config->name) { \
11948 DRM_ERROR("mismatch in " #name " " \
11949 "(expected %i, found %i)\n", \
11950 current_config->name, \
11951 pipe_config->name); \
11952 return false; \
88adfff1
DV
11953 }
11954
b95af8be
VK
11955/* This is required for BDW+ where there is only one set of registers for
11956 * switching between high and low RR.
11957 * This macro can be used whenever a comparison has to be made between one
11958 * hw state and multiple sw state variables.
11959 */
11960#define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
11961 if ((current_config->name != pipe_config->name) && \
11962 (current_config->alt_name != pipe_config->name)) { \
11963 DRM_ERROR("mismatch in " #name " " \
11964 "(expected %i or %i, found %i)\n", \
11965 current_config->name, \
11966 current_config->alt_name, \
11967 pipe_config->name); \
11968 return false; \
11969 }
11970
1bd1bd80
DV
11971#define PIPE_CONF_CHECK_FLAGS(name, mask) \
11972 if ((current_config->name ^ pipe_config->name) & (mask)) { \
6f02488e 11973 DRM_ERROR("mismatch in " #name "(" #mask ") " \
1bd1bd80
DV
11974 "(expected %i, found %i)\n", \
11975 current_config->name & (mask), \
11976 pipe_config->name & (mask)); \
11977 return false; \
11978 }
11979
5e550656
VS
11980#define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
11981 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
11982 DRM_ERROR("mismatch in " #name " " \
11983 "(expected %i, found %i)\n", \
11984 current_config->name, \
11985 pipe_config->name); \
11986 return false; \
11987 }
11988
bb760063
DV
11989#define PIPE_CONF_QUIRK(quirk) \
11990 ((current_config->quirks | pipe_config->quirks) & (quirk))
11991
eccb140b
DV
11992 PIPE_CONF_CHECK_I(cpu_transcoder);
11993
08a24034
DV
11994 PIPE_CONF_CHECK_I(has_pch_encoder);
11995 PIPE_CONF_CHECK_I(fdi_lanes);
72419203
DV
11996 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
11997 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
11998 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
11999 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
12000 PIPE_CONF_CHECK_I(fdi_m_n.tu);
08a24034 12001
eb14cb74 12002 PIPE_CONF_CHECK_I(has_dp_encoder);
b95af8be
VK
12003
12004 if (INTEL_INFO(dev)->gen < 8) {
12005 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
12006 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
12007 PIPE_CONF_CHECK_I(dp_m_n.link_m);
12008 PIPE_CONF_CHECK_I(dp_m_n.link_n);
12009 PIPE_CONF_CHECK_I(dp_m_n.tu);
12010
12011 if (current_config->has_drrs) {
12012 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
12013 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
12014 PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
12015 PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
12016 PIPE_CONF_CHECK_I(dp_m2_n2.tu);
12017 }
12018 } else {
12019 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
12020 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
12021 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
12022 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
12023 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
12024 }
eb14cb74 12025
2d112de7
ACO
12026 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12027 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12028 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12029 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12030 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12031 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
1bd1bd80 12032
2d112de7
ACO
12033 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12034 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12035 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12036 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12037 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12038 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
1bd1bd80 12039
c93f54cf 12040 PIPE_CONF_CHECK_I(pixel_multiplier);
6897b4b5 12041 PIPE_CONF_CHECK_I(has_hdmi_sink);
b5a9fa09
DV
12042 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12043 IS_VALLEYVIEW(dev))
12044 PIPE_CONF_CHECK_I(limited_color_range);
e43823ec 12045 PIPE_CONF_CHECK_I(has_infoframe);
6c49f241 12046
9ed109a7
DV
12047 PIPE_CONF_CHECK_I(has_audio);
12048
2d112de7 12049 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
1bd1bd80
DV
12050 DRM_MODE_FLAG_INTERLACE);
12051
bb760063 12052 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
2d112de7 12053 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 12054 DRM_MODE_FLAG_PHSYNC);
2d112de7 12055 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 12056 DRM_MODE_FLAG_NHSYNC);
2d112de7 12057 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 12058 DRM_MODE_FLAG_PVSYNC);
2d112de7 12059 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063
DV
12060 DRM_MODE_FLAG_NVSYNC);
12061 }
045ac3b5 12062
37327abd
VS
12063 PIPE_CONF_CHECK_I(pipe_src_w);
12064 PIPE_CONF_CHECK_I(pipe_src_h);
1bd1bd80 12065
9953599b
DV
12066 /*
12067 * FIXME: BIOS likes to set up a cloned config with lvds+external
12068 * screen. Since we don't yet re-compute the pipe config when moving
12069 * just the lvds port away to another pipe the sw tracking won't match.
12070 *
12071 * Proper atomic modesets with recomputed global state will fix this.
12072 * Until then just don't check gmch state for inherited modes.
12073 */
12074 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
12075 PIPE_CONF_CHECK_I(gmch_pfit.control);
12076 /* pfit ratios are autocomputed by the hw on gen4+ */
12077 if (INTEL_INFO(dev)->gen < 4)
12078 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
12079 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
12080 }
12081
fd4daa9c
CW
12082 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12083 if (current_config->pch_pfit.enabled) {
12084 PIPE_CONF_CHECK_I(pch_pfit.pos);
12085 PIPE_CONF_CHECK_I(pch_pfit.size);
12086 }
2fa2fe9a 12087
a1b2278e
CK
12088 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12089
e59150dc
JB
12090 /* BDW+ don't expose a synchronous way to read the state */
12091 if (IS_HASWELL(dev))
12092 PIPE_CONF_CHECK_I(ips_enabled);
42db64ef 12093
282740f7
VS
12094 PIPE_CONF_CHECK_I(double_wide);
12095
26804afd
DV
12096 PIPE_CONF_CHECK_X(ddi_pll_sel);
12097
c0d43d62 12098 PIPE_CONF_CHECK_I(shared_dpll);
66e985c0 12099 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8bcc2795 12100 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
66e985c0
DV
12101 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12102 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
d452c5b6 12103 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
3f4cd19f
DL
12104 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12105 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12106 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
c0d43d62 12107
42571aef
VS
12108 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12109 PIPE_CONF_CHECK_I(pipe_bpp);
12110
2d112de7 12111 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
a9a7e98a 12112 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
5e550656 12113
66e985c0 12114#undef PIPE_CONF_CHECK_X
08a24034 12115#undef PIPE_CONF_CHECK_I
b95af8be 12116#undef PIPE_CONF_CHECK_I_ALT
1bd1bd80 12117#undef PIPE_CONF_CHECK_FLAGS
5e550656 12118#undef PIPE_CONF_CHECK_CLOCK_FUZZY
bb760063 12119#undef PIPE_CONF_QUIRK
88adfff1 12120
0e8ffe1b
DV
12121 return true;
12122}
12123
08db6652
DL
12124static void check_wm_state(struct drm_device *dev)
12125{
12126 struct drm_i915_private *dev_priv = dev->dev_private;
12127 struct skl_ddb_allocation hw_ddb, *sw_ddb;
12128 struct intel_crtc *intel_crtc;
12129 int plane;
12130
12131 if (INTEL_INFO(dev)->gen < 9)
12132 return;
12133
12134 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12135 sw_ddb = &dev_priv->wm.skl_hw.ddb;
12136
12137 for_each_intel_crtc(dev, intel_crtc) {
12138 struct skl_ddb_entry *hw_entry, *sw_entry;
12139 const enum pipe pipe = intel_crtc->pipe;
12140
12141 if (!intel_crtc->active)
12142 continue;
12143
12144 /* planes */
dd740780 12145 for_each_plane(dev_priv, pipe, plane) {
08db6652
DL
12146 hw_entry = &hw_ddb.plane[pipe][plane];
12147 sw_entry = &sw_ddb->plane[pipe][plane];
12148
12149 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12150 continue;
12151
12152 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12153 "(expected (%u,%u), found (%u,%u))\n",
12154 pipe_name(pipe), plane + 1,
12155 sw_entry->start, sw_entry->end,
12156 hw_entry->start, hw_entry->end);
12157 }
12158
12159 /* cursor */
12160 hw_entry = &hw_ddb.cursor[pipe];
12161 sw_entry = &sw_ddb->cursor[pipe];
12162
12163 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12164 continue;
12165
12166 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12167 "(expected (%u,%u), found (%u,%u))\n",
12168 pipe_name(pipe),
12169 sw_entry->start, sw_entry->end,
12170 hw_entry->start, hw_entry->end);
12171 }
12172}
12173
91d1b4bd
DV
12174static void
12175check_connector_state(struct drm_device *dev)
8af6cf88 12176{
8af6cf88
DV
12177 struct intel_connector *connector;
12178
3a3371ff 12179 for_each_intel_connector(dev, connector) {
8af6cf88
DV
12180 /* This also checks the encoder/connector hw state with the
12181 * ->get_hw_state callbacks. */
12182 intel_connector_check_state(connector);
12183
e2c719b7 12184 I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder,
8af6cf88
DV
12185 "connector's staged encoder doesn't match current encoder\n");
12186 }
91d1b4bd
DV
12187}
12188
12189static void
12190check_encoder_state(struct drm_device *dev)
12191{
12192 struct intel_encoder *encoder;
12193 struct intel_connector *connector;
8af6cf88 12194
b2784e15 12195 for_each_intel_encoder(dev, encoder) {
8af6cf88
DV
12196 bool enabled = false;
12197 bool active = false;
12198 enum pipe pipe, tracked_pipe;
12199
12200 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12201 encoder->base.base.id,
8e329a03 12202 encoder->base.name);
8af6cf88 12203
e2c719b7 12204 I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc,
8af6cf88 12205 "encoder's stage crtc doesn't match current crtc\n");
e2c719b7 12206 I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc,
8af6cf88
DV
12207 "encoder's active_connectors set, but no crtc\n");
12208
3a3371ff 12209 for_each_intel_connector(dev, connector) {
8af6cf88
DV
12210 if (connector->base.encoder != &encoder->base)
12211 continue;
12212 enabled = true;
12213 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
12214 active = true;
12215 }
0e32b39c
DA
12216 /*
12217 * for MST connectors if we unplug the connector is gone
12218 * away but the encoder is still connected to a crtc
12219 * until a modeset happens in response to the hotplug.
12220 */
12221 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
12222 continue;
12223
e2c719b7 12224 I915_STATE_WARN(!!encoder->base.crtc != enabled,
8af6cf88
DV
12225 "encoder's enabled state mismatch "
12226 "(expected %i, found %i)\n",
12227 !!encoder->base.crtc, enabled);
e2c719b7 12228 I915_STATE_WARN(active && !encoder->base.crtc,
8af6cf88
DV
12229 "active encoder with no crtc\n");
12230
e2c719b7 12231 I915_STATE_WARN(encoder->connectors_active != active,
8af6cf88
DV
12232 "encoder's computed active state doesn't match tracked active state "
12233 "(expected %i, found %i)\n", active, encoder->connectors_active);
12234
12235 active = encoder->get_hw_state(encoder, &pipe);
e2c719b7 12236 I915_STATE_WARN(active != encoder->connectors_active,
8af6cf88
DV
12237 "encoder's hw state doesn't match sw tracking "
12238 "(expected %i, found %i)\n",
12239 encoder->connectors_active, active);
12240
12241 if (!encoder->base.crtc)
12242 continue;
12243
12244 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
e2c719b7 12245 I915_STATE_WARN(active && pipe != tracked_pipe,
8af6cf88
DV
12246 "active encoder's pipe doesn't match"
12247 "(expected %i, found %i)\n",
12248 tracked_pipe, pipe);
12249
12250 }
91d1b4bd
DV
12251}
12252
12253static void
12254check_crtc_state(struct drm_device *dev)
12255{
fbee40df 12256 struct drm_i915_private *dev_priv = dev->dev_private;
91d1b4bd
DV
12257 struct intel_crtc *crtc;
12258 struct intel_encoder *encoder;
5cec258b 12259 struct intel_crtc_state pipe_config;
8af6cf88 12260
d3fcc808 12261 for_each_intel_crtc(dev, crtc) {
8af6cf88
DV
12262 bool enabled = false;
12263 bool active = false;
12264
045ac3b5
JB
12265 memset(&pipe_config, 0, sizeof(pipe_config));
12266
8af6cf88
DV
12267 DRM_DEBUG_KMS("[CRTC:%d]\n",
12268 crtc->base.base.id);
12269
83d65738 12270 I915_STATE_WARN(crtc->active && !crtc->base.state->enable,
8af6cf88
DV
12271 "active crtc, but not enabled in sw tracking\n");
12272
b2784e15 12273 for_each_intel_encoder(dev, encoder) {
8af6cf88
DV
12274 if (encoder->base.crtc != &crtc->base)
12275 continue;
12276 enabled = true;
12277 if (encoder->connectors_active)
12278 active = true;
12279 }
6c49f241 12280
e2c719b7 12281 I915_STATE_WARN(active != crtc->active,
8af6cf88
DV
12282 "crtc's computed active state doesn't match tracked active state "
12283 "(expected %i, found %i)\n", active, crtc->active);
83d65738 12284 I915_STATE_WARN(enabled != crtc->base.state->enable,
8af6cf88 12285 "crtc's computed enabled state doesn't match tracked enabled state "
83d65738
MR
12286 "(expected %i, found %i)\n", enabled,
12287 crtc->base.state->enable);
8af6cf88 12288
0e8ffe1b
DV
12289 active = dev_priv->display.get_pipe_config(crtc,
12290 &pipe_config);
d62cf62a 12291
b6b5d049
VS
12292 /* hw state is inconsistent with the pipe quirk */
12293 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12294 (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
d62cf62a
DV
12295 active = crtc->active;
12296
b2784e15 12297 for_each_intel_encoder(dev, encoder) {
3eaba51c 12298 enum pipe pipe;
6c49f241
DV
12299 if (encoder->base.crtc != &crtc->base)
12300 continue;
1d37b689 12301 if (encoder->get_hw_state(encoder, &pipe))
6c49f241
DV
12302 encoder->get_config(encoder, &pipe_config);
12303 }
12304
e2c719b7 12305 I915_STATE_WARN(crtc->active != active,
0e8ffe1b
DV
12306 "crtc active state doesn't match with hw state "
12307 "(expected %i, found %i)\n", crtc->active, active);
12308
c0b03411 12309 if (active &&
6e3c9717 12310 !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) {
e2c719b7 12311 I915_STATE_WARN(1, "pipe state doesn't match!\n");
c0b03411
DV
12312 intel_dump_pipe_config(crtc, &pipe_config,
12313 "[hw state]");
6e3c9717 12314 intel_dump_pipe_config(crtc, crtc->config,
c0b03411
DV
12315 "[sw state]");
12316 }
8af6cf88
DV
12317 }
12318}
12319
91d1b4bd
DV
12320static void
12321check_shared_dpll_state(struct drm_device *dev)
12322{
fbee40df 12323 struct drm_i915_private *dev_priv = dev->dev_private;
91d1b4bd
DV
12324 struct intel_crtc *crtc;
12325 struct intel_dpll_hw_state dpll_hw_state;
12326 int i;
5358901f
DV
12327
12328 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12329 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12330 int enabled_crtcs = 0, active_crtcs = 0;
12331 bool active;
12332
12333 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12334
12335 DRM_DEBUG_KMS("%s\n", pll->name);
12336
12337 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
12338
e2c719b7 12339 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
5358901f 12340 "more active pll users than references: %i vs %i\n",
3e369b76 12341 pll->active, hweight32(pll->config.crtc_mask));
e2c719b7 12342 I915_STATE_WARN(pll->active && !pll->on,
5358901f 12343 "pll in active use but not on in sw tracking\n");
e2c719b7 12344 I915_STATE_WARN(pll->on && !pll->active,
35c95375 12345 "pll in on but not on in use in sw tracking\n");
e2c719b7 12346 I915_STATE_WARN(pll->on != active,
5358901f
DV
12347 "pll on state mismatch (expected %i, found %i)\n",
12348 pll->on, active);
12349
d3fcc808 12350 for_each_intel_crtc(dev, crtc) {
83d65738 12351 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
5358901f
DV
12352 enabled_crtcs++;
12353 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12354 active_crtcs++;
12355 }
e2c719b7 12356 I915_STATE_WARN(pll->active != active_crtcs,
5358901f
DV
12357 "pll active crtcs mismatch (expected %i, found %i)\n",
12358 pll->active, active_crtcs);
e2c719b7 12359 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
5358901f 12360 "pll enabled crtcs mismatch (expected %i, found %i)\n",
3e369b76 12361 hweight32(pll->config.crtc_mask), enabled_crtcs);
66e985c0 12362
e2c719b7 12363 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
66e985c0
DV
12364 sizeof(dpll_hw_state)),
12365 "pll hw state mismatch\n");
5358901f 12366 }
8af6cf88
DV
12367}
12368
91d1b4bd
DV
12369void
12370intel_modeset_check_state(struct drm_device *dev)
12371{
08db6652 12372 check_wm_state(dev);
91d1b4bd
DV
12373 check_connector_state(dev);
12374 check_encoder_state(dev);
12375 check_crtc_state(dev);
12376 check_shared_dpll_state(dev);
12377}
12378
5cec258b 12379void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
18442d08
VS
12380 int dotclock)
12381{
12382 /*
12383 * FDI already provided one idea for the dotclock.
12384 * Yell if the encoder disagrees.
12385 */
2d112de7 12386 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
18442d08 12387 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
2d112de7 12388 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
18442d08
VS
12389}
12390
80715b2f
VS
12391static void update_scanline_offset(struct intel_crtc *crtc)
12392{
12393 struct drm_device *dev = crtc->base.dev;
12394
12395 /*
12396 * The scanline counter increments at the leading edge of hsync.
12397 *
12398 * On most platforms it starts counting from vtotal-1 on the
12399 * first active line. That means the scanline counter value is
12400 * always one less than what we would expect. Ie. just after
12401 * start of vblank, which also occurs at start of hsync (on the
12402 * last active line), the scanline counter will read vblank_start-1.
12403 *
12404 * On gen2 the scanline counter starts counting from 1 instead
12405 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12406 * to keep the value positive), instead of adding one.
12407 *
12408 * On HSW+ the behaviour of the scanline counter depends on the output
12409 * type. For DP ports it behaves like most other platforms, but on HDMI
12410 * there's an extra 1 line difference. So we need to add two instead of
12411 * one to the value.
12412 */
12413 if (IS_GEN2(dev)) {
6e3c9717 12414 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
80715b2f
VS
12415 int vtotal;
12416
12417 vtotal = mode->crtc_vtotal;
12418 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
12419 vtotal /= 2;
12420
12421 crtc->scanline_offset = vtotal - 1;
12422 } else if (HAS_DDI(dev) &&
409ee761 12423 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
80715b2f
VS
12424 crtc->scanline_offset = 2;
12425 } else
12426 crtc->scanline_offset = 1;
12427}
12428
5cec258b 12429static struct intel_crtc_state *
7f27126e 12430intel_modeset_compute_config(struct drm_crtc *crtc,
0a9ab303 12431 struct drm_atomic_state *state)
7f27126e 12432{
548ee15b 12433 struct intel_crtc_state *pipe_config;
0b901879
ACO
12434 int ret = 0;
12435
12436 ret = drm_atomic_add_affected_connectors(state, crtc);
12437 if (ret)
12438 return ERR_PTR(ret);
7f27126e 12439
8c7b5ccb
ACO
12440 ret = drm_atomic_helper_check_modeset(state->dev, state);
12441 if (ret)
12442 return ERR_PTR(ret);
7f27126e 12443
7f27126e
JB
12444 /*
12445 * Note this needs changes when we start tracking multiple modes
12446 * and crtcs. At that point we'll need to compute the whole config
12447 * (i.e. one pipe_config for each crtc) rather than just the one
12448 * for this crtc.
12449 */
548ee15b
ACO
12450 pipe_config = intel_atomic_get_crtc_state(state, to_intel_crtc(crtc));
12451 if (IS_ERR(pipe_config))
12452 return pipe_config;
83a57153 12453
4fed33f6 12454 if (!pipe_config->base.enable)
548ee15b 12455 return pipe_config;
7f27126e 12456
8c7b5ccb 12457 ret = intel_modeset_pipe_config(crtc, state, pipe_config);
548ee15b
ACO
12458 if (ret)
12459 return ERR_PTR(ret);
12460
8d8c9b51
ACO
12461 /* Check things that can only be changed through modeset */
12462 if (pipe_config->has_audio !=
12463 to_intel_crtc(crtc)->config->has_audio)
12464 pipe_config->base.mode_changed = true;
12465
12466 /*
12467 * Note we have an issue here with infoframes: current code
12468 * only updates them on the full mode set path per hw
12469 * requirements. So here we should be checking for any
12470 * required changes and forcing a mode set.
12471 */
12472
548ee15b 12473 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,"[modeset]");
db7542dd 12474
8c7b5ccb
ACO
12475 ret = drm_atomic_helper_check_planes(state->dev, state);
12476 if (ret)
12477 return ERR_PTR(ret);
12478
548ee15b 12479 return pipe_config;
7f27126e
JB
12480}
12481
0a9ab303 12482static int __intel_set_mode_setup_plls(struct drm_atomic_state *state)
ed6739ef 12483{
225da59b 12484 struct drm_device *dev = state->dev;
ed6739ef 12485 struct drm_i915_private *dev_priv = to_i915(dev);
0a9ab303 12486 unsigned clear_pipes = 0;
ed6739ef 12487 struct intel_crtc *intel_crtc;
0a9ab303
ACO
12488 struct intel_crtc_state *intel_crtc_state;
12489 struct drm_crtc *crtc;
12490 struct drm_crtc_state *crtc_state;
ed6739ef 12491 int ret = 0;
0a9ab303 12492 int i;
ed6739ef
ACO
12493
12494 if (!dev_priv->display.crtc_compute_clock)
12495 return 0;
12496
0a9ab303
ACO
12497 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12498 intel_crtc = to_intel_crtc(crtc);
4978cc93 12499 intel_crtc_state = to_intel_crtc_state(crtc_state);
0a9ab303 12500
4978cc93 12501 if (needs_modeset(crtc_state)) {
0a9ab303 12502 clear_pipes |= 1 << intel_crtc->pipe;
4978cc93 12503 intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
4978cc93 12504 }
0a9ab303
ACO
12505 }
12506
ed6739ef
ACO
12507 ret = intel_shared_dpll_start_config(dev_priv, clear_pipes);
12508 if (ret)
12509 goto done;
12510
0a9ab303
ACO
12511 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12512 if (!needs_modeset(crtc_state) || !crtc_state->enable)
225da59b
ACO
12513 continue;
12514
0a9ab303
ACO
12515 intel_crtc = to_intel_crtc(crtc);
12516 intel_crtc_state = to_intel_crtc_state(crtc_state);
12517
ed6739ef 12518 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
0a9ab303 12519 intel_crtc_state);
ed6739ef
ACO
12520 if (ret) {
12521 intel_shared_dpll_abort_config(dev_priv);
12522 goto done;
12523 }
12524 }
12525
12526done:
12527 return ret;
12528}
12529
054518dd
ACO
12530/* Code that should eventually be part of atomic_check() */
12531static int __intel_set_mode_checks(struct drm_atomic_state *state)
12532{
12533 struct drm_device *dev = state->dev;
12534 int ret;
12535
12536 /*
12537 * See if the config requires any additional preparation, e.g.
12538 * to adjust global state with pipes off. We need to do this
12539 * here so we can get the modeset_pipe updated config for the new
12540 * mode set on this crtc. For other crtcs we need to use the
12541 * adjusted_mode bits in the crtc directly.
12542 */
12543 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
12544 ret = valleyview_modeset_global_pipes(state);
12545 if (ret)
12546 return ret;
12547 }
12548
12549 ret = __intel_set_mode_setup_plls(state);
12550 if (ret)
12551 return ret;
12552
12553 return 0;
12554}
12555
0a9ab303 12556static int __intel_set_mode(struct drm_crtc *modeset_crtc,
0a9ab303 12557 struct intel_crtc_state *pipe_config)
a6778b3c 12558{
0a9ab303 12559 struct drm_device *dev = modeset_crtc->dev;
fbee40df 12560 struct drm_i915_private *dev_priv = dev->dev_private;
304603f4 12561 struct drm_atomic_state *state = pipe_config->base.state;
0a9ab303
ACO
12562 struct drm_crtc *crtc;
12563 struct drm_crtc_state *crtc_state;
c0c36b94 12564 int ret = 0;
0a9ab303 12565 int i;
a6778b3c 12566
054518dd
ACO
12567 ret = __intel_set_mode_checks(state);
12568 if (ret < 0)
12569 return ret;
12570
d4afb8cc
ACO
12571 ret = drm_atomic_helper_prepare_planes(dev, state);
12572 if (ret)
12573 return ret;
12574
0a9ab303
ACO
12575 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12576 if (!needs_modeset(crtc_state))
12577 continue;
460da916 12578
0a9ab303
ACO
12579 if (!crtc_state->enable) {
12580 intel_crtc_disable(crtc);
12581 } else if (crtc->state->enable) {
12582 intel_crtc_disable_planes(crtc);
12583 dev_priv->display.crtc_disable(crtc);
ce22dba9 12584 }
ea9d758d 12585 }
a6778b3c 12586
6c4c86f5
DV
12587 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
12588 * to set it here already despite that we pass it down the callchain.
7f27126e
JB
12589 *
12590 * Note we'll need to fix this up when we start tracking multiple
12591 * pipes; here we assume a single modeset_pipe and only track the
12592 * single crtc and mode.
f6e5b160 12593 */
0a9ab303 12594 if (pipe_config->base.enable && needs_modeset(&pipe_config->base)) {
8c7b5ccb 12595 modeset_crtc->mode = pipe_config->base.mode;
c326c0a9
VS
12596
12597 /*
12598 * Calculate and store various constants which
12599 * are later needed by vblank and swap-completion
12600 * timestamping. They are derived from true hwmode.
12601 */
0a9ab303 12602 drm_calc_timestamping_constants(modeset_crtc,
2d112de7 12603 &pipe_config->base.adjusted_mode);
b8cecdf5 12604 }
7758a113 12605
ea9d758d
DV
12606 /* Only after disabling all output pipelines that will be changed can we
12607 * update the the output configuration. */
0a9ab303 12608 intel_modeset_update_state(state);
f6e5b160 12609
a821fc46
ACO
12610 /* The state has been swaped above, so state actually contains the
12611 * old state now. */
12612
304603f4 12613 modeset_update_crtc_power_domains(state);
47fab737 12614
d4afb8cc 12615 drm_atomic_helper_commit_planes(dev, state);
a6778b3c
DV
12616
12617 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
0a9ab303 12618 for_each_crtc_in_state(state, crtc, crtc_state, i) {
a821fc46 12619 if (!needs_modeset(crtc->state) || !crtc->state->enable)
0a9ab303
ACO
12620 continue;
12621
12622 update_scanline_offset(to_intel_crtc(crtc));
80715b2f 12623
0a9ab303
ACO
12624 dev_priv->display.crtc_enable(crtc);
12625 intel_crtc_enable_planes(crtc);
80715b2f 12626 }
a6778b3c 12627
a6778b3c 12628 /* FIXME: add subpixel order */
83a57153 12629
d4afb8cc
ACO
12630 drm_atomic_helper_cleanup_planes(dev, state);
12631
2bfb4627
ACO
12632 drm_atomic_state_free(state);
12633
9eb45f22 12634 return 0;
f6e5b160
CW
12635}
12636
0a9ab303 12637static int intel_set_mode_with_config(struct drm_crtc *crtc,
0a9ab303 12638 struct intel_crtc_state *pipe_config)
f30da187
DV
12639{
12640 int ret;
12641
8c7b5ccb 12642 ret = __intel_set_mode(crtc, pipe_config);
f30da187
DV
12643
12644 if (ret == 0)
12645 intel_modeset_check_state(crtc->dev);
12646
12647 return ret;
12648}
12649
7f27126e 12650static int intel_set_mode(struct drm_crtc *crtc,
83a57153 12651 struct drm_atomic_state *state)
7f27126e 12652{
5cec258b 12653 struct intel_crtc_state *pipe_config;
83a57153 12654 int ret = 0;
7f27126e 12655
8c7b5ccb 12656 pipe_config = intel_modeset_compute_config(crtc, state);
83a57153
ACO
12657 if (IS_ERR(pipe_config)) {
12658 ret = PTR_ERR(pipe_config);
12659 goto out;
12660 }
12661
8c7b5ccb 12662 ret = intel_set_mode_with_config(crtc, pipe_config);
83a57153
ACO
12663 if (ret)
12664 goto out;
7f27126e 12665
83a57153
ACO
12666out:
12667 return ret;
7f27126e
JB
12668}
12669
c0c36b94
CW
12670void intel_crtc_restore_mode(struct drm_crtc *crtc)
12671{
83a57153
ACO
12672 struct drm_device *dev = crtc->dev;
12673 struct drm_atomic_state *state;
4be07317 12674 struct intel_crtc *intel_crtc;
83a57153
ACO
12675 struct intel_encoder *encoder;
12676 struct intel_connector *connector;
12677 struct drm_connector_state *connector_state;
4be07317 12678 struct intel_crtc_state *crtc_state;
2bfb4627 12679 int ret;
83a57153
ACO
12680
12681 state = drm_atomic_state_alloc(dev);
12682 if (!state) {
12683 DRM_DEBUG_KMS("[CRTC:%d] mode restore failed, out of memory",
12684 crtc->base.id);
12685 return;
12686 }
12687
12688 state->acquire_ctx = dev->mode_config.acquire_ctx;
12689
12690 /* The force restore path in the HW readout code relies on the staged
12691 * config still keeping the user requested config while the actual
12692 * state has been overwritten by the configuration read from HW. We
12693 * need to copy the staged config to the atomic state, otherwise the
12694 * mode set will just reapply the state the HW is already in. */
12695 for_each_intel_encoder(dev, encoder) {
12696 if (&encoder->new_crtc->base != crtc)
12697 continue;
12698
12699 for_each_intel_connector(dev, connector) {
12700 if (connector->new_encoder != encoder)
12701 continue;
12702
12703 connector_state = drm_atomic_get_connector_state(state, &connector->base);
12704 if (IS_ERR(connector_state)) {
12705 DRM_DEBUG_KMS("Failed to add [CONNECTOR:%d:%s] to state: %ld\n",
12706 connector->base.base.id,
12707 connector->base.name,
12708 PTR_ERR(connector_state));
12709 continue;
12710 }
12711
12712 connector_state->crtc = crtc;
12713 connector_state->best_encoder = &encoder->base;
12714 }
12715 }
12716
4be07317
ACO
12717 for_each_intel_crtc(dev, intel_crtc) {
12718 if (intel_crtc->new_enabled == intel_crtc->base.enabled)
12719 continue;
12720
12721 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
12722 if (IS_ERR(crtc_state)) {
12723 DRM_DEBUG_KMS("Failed to add [CRTC:%d] to state: %ld\n",
12724 intel_crtc->base.base.id,
12725 PTR_ERR(crtc_state));
12726 continue;
12727 }
12728
49d6fa21
ML
12729 crtc_state->base.active = crtc_state->base.enable =
12730 intel_crtc->new_enabled;
8c7b5ccb
ACO
12731
12732 if (&intel_crtc->base == crtc)
12733 drm_mode_copy(&crtc_state->base.mode, &crtc->mode);
4be07317
ACO
12734 }
12735
d3a40d1b
ACO
12736 intel_modeset_setup_plane_state(state, crtc, &crtc->mode,
12737 crtc->primary->fb, crtc->x, crtc->y);
12738
2bfb4627
ACO
12739 ret = intel_set_mode(crtc, state);
12740 if (ret)
12741 drm_atomic_state_free(state);
c0c36b94
CW
12742}
12743
25c5b266
DV
12744#undef for_each_intel_crtc_masked
12745
b7885264
ACO
12746static bool intel_connector_in_mode_set(struct intel_connector *connector,
12747 struct drm_mode_set *set)
12748{
12749 int ro;
12750
12751 for (ro = 0; ro < set->num_connectors; ro++)
12752 if (set->connectors[ro] == &connector->base)
12753 return true;
12754
12755 return false;
12756}
12757
2e431051 12758static int
9a935856
DV
12759intel_modeset_stage_output_state(struct drm_device *dev,
12760 struct drm_mode_set *set,
944b0c76 12761 struct drm_atomic_state *state)
50f56119 12762{
9a935856 12763 struct intel_connector *connector;
d5432a9d 12764 struct drm_connector *drm_connector;
944b0c76 12765 struct drm_connector_state *connector_state;
d5432a9d
ACO
12766 struct drm_crtc *crtc;
12767 struct drm_crtc_state *crtc_state;
12768 int i, ret;
50f56119 12769
9abdda74 12770 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV
12771 * of connectors. For paranoia, double-check this. */
12772 WARN_ON(!set->fb && (set->num_connectors != 0));
12773 WARN_ON(set->fb && (set->num_connectors == 0));
12774
3a3371ff 12775 for_each_intel_connector(dev, connector) {
b7885264
ACO
12776 bool in_mode_set = intel_connector_in_mode_set(connector, set);
12777
d5432a9d
ACO
12778 if (!in_mode_set && connector->base.state->crtc != set->crtc)
12779 continue;
12780
12781 connector_state =
12782 drm_atomic_get_connector_state(state, &connector->base);
12783 if (IS_ERR(connector_state))
12784 return PTR_ERR(connector_state);
12785
b7885264
ACO
12786 if (in_mode_set) {
12787 int pipe = to_intel_crtc(set->crtc)->pipe;
d5432a9d
ACO
12788 connector_state->best_encoder =
12789 &intel_find_encoder(connector, pipe)->base;
50f56119
DV
12790 }
12791
d5432a9d 12792 if (connector->base.state->crtc != set->crtc)
b7885264
ACO
12793 continue;
12794
9a935856
DV
12795 /* If we disable the crtc, disable all its connectors. Also, if
12796 * the connector is on the changing crtc but not on the new
12797 * connector list, disable it. */
b7885264 12798 if (!set->fb || !in_mode_set) {
d5432a9d 12799 connector_state->best_encoder = NULL;
9a935856
DV
12800
12801 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
12802 connector->base.base.id,
c23cc417 12803 connector->base.name);
9a935856 12804 }
50f56119 12805 }
9a935856 12806 /* connector->new_encoder is now updated for all connectors. */
50f56119 12807
d5432a9d
ACO
12808 for_each_connector_in_state(state, drm_connector, connector_state, i) {
12809 connector = to_intel_connector(drm_connector);
12810
12811 if (!connector_state->best_encoder) {
12812 ret = drm_atomic_set_crtc_for_connector(connector_state,
12813 NULL);
12814 if (ret)
12815 return ret;
7668851f 12816
50f56119 12817 continue;
d5432a9d 12818 }
50f56119 12819
d5432a9d
ACO
12820 if (intel_connector_in_mode_set(connector, set)) {
12821 struct drm_crtc *crtc = connector->base.state->crtc;
12822
12823 /* If this connector was in a previous crtc, add it
12824 * to the state. We might need to disable it. */
12825 if (crtc) {
12826 crtc_state =
12827 drm_atomic_get_crtc_state(state, crtc);
12828 if (IS_ERR(crtc_state))
12829 return PTR_ERR(crtc_state);
12830 }
12831
12832 ret = drm_atomic_set_crtc_for_connector(connector_state,
12833 set->crtc);
12834 if (ret)
12835 return ret;
12836 }
50f56119
DV
12837
12838 /* Make sure the new CRTC will work with the encoder */
d5432a9d
ACO
12839 if (!drm_encoder_crtc_ok(connector_state->best_encoder,
12840 connector_state->crtc)) {
5e2b584e 12841 return -EINVAL;
50f56119 12842 }
944b0c76 12843
9a935856
DV
12844 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
12845 connector->base.base.id,
c23cc417 12846 connector->base.name,
d5432a9d 12847 connector_state->crtc->base.id);
944b0c76 12848
d5432a9d
ACO
12849 if (connector_state->best_encoder != &connector->encoder->base)
12850 connector->encoder =
12851 to_intel_encoder(connector_state->best_encoder);
0e32b39c 12852 }
7668851f 12853
d5432a9d 12854 for_each_crtc_in_state(state, crtc, crtc_state, i) {
49d6fa21
ML
12855 bool has_connectors;
12856
d5432a9d
ACO
12857 ret = drm_atomic_add_affected_connectors(state, crtc);
12858 if (ret)
12859 return ret;
4be07317 12860
49d6fa21
ML
12861 has_connectors = !!drm_atomic_connectors_for_crtc(state, crtc);
12862 if (has_connectors != crtc_state->enable)
12863 crtc_state->enable =
12864 crtc_state->active = has_connectors;
7668851f
VS
12865 }
12866
8c7b5ccb
ACO
12867 ret = intel_modeset_setup_plane_state(state, set->crtc, set->mode,
12868 set->fb, set->x, set->y);
12869 if (ret)
12870 return ret;
12871
12872 crtc_state = drm_atomic_get_crtc_state(state, set->crtc);
12873 if (IS_ERR(crtc_state))
12874 return PTR_ERR(crtc_state);
12875
12876 if (set->mode)
12877 drm_mode_copy(&crtc_state->mode, set->mode);
12878
12879 if (set->num_connectors)
12880 crtc_state->active = true;
12881
2e431051
DV
12882 return 0;
12883}
12884
bb546623
ACO
12885static bool primary_plane_visible(struct drm_crtc *crtc)
12886{
12887 struct intel_plane_state *plane_state =
12888 to_intel_plane_state(crtc->primary->state);
12889
12890 return plane_state->visible;
12891}
12892
2e431051
DV
12893static int intel_crtc_set_config(struct drm_mode_set *set)
12894{
12895 struct drm_device *dev;
83a57153 12896 struct drm_atomic_state *state = NULL;
5cec258b 12897 struct intel_crtc_state *pipe_config;
bb546623 12898 bool primary_plane_was_visible;
2e431051 12899 int ret;
2e431051 12900
8d3e375e
DV
12901 BUG_ON(!set);
12902 BUG_ON(!set->crtc);
12903 BUG_ON(!set->crtc->helper_private);
2e431051 12904
7e53f3a4
DV
12905 /* Enforce sane interface api - has been abused by the fb helper. */
12906 BUG_ON(!set->mode && set->fb);
12907 BUG_ON(set->fb && set->num_connectors == 0);
431e50f7 12908
2e431051
DV
12909 if (set->fb) {
12910 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
12911 set->crtc->base.id, set->fb->base.id,
12912 (int)set->num_connectors, set->x, set->y);
12913 } else {
12914 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV
12915 }
12916
12917 dev = set->crtc->dev;
12918
83a57153 12919 state = drm_atomic_state_alloc(dev);
7cbf41d6
ACO
12920 if (!state)
12921 return -ENOMEM;
83a57153
ACO
12922
12923 state->acquire_ctx = dev->mode_config.acquire_ctx;
12924
462a425a 12925 ret = intel_modeset_stage_output_state(dev, set, state);
2e431051 12926 if (ret)
7cbf41d6 12927 goto out;
2e431051 12928
8c7b5ccb 12929 pipe_config = intel_modeset_compute_config(set->crtc, state);
20664591 12930 if (IS_ERR(pipe_config)) {
6ac0483b 12931 ret = PTR_ERR(pipe_config);
7cbf41d6 12932 goto out;
20664591 12933 }
50f52756 12934
1f9954d0
JB
12935 intel_update_pipe_size(to_intel_crtc(set->crtc));
12936
bb546623
ACO
12937 primary_plane_was_visible = primary_plane_visible(set->crtc);
12938
8c7b5ccb 12939 ret = intel_set_mode_with_config(set->crtc, pipe_config);
bb546623
ACO
12940
12941 if (ret == 0 &&
12942 pipe_config->base.enable &&
12943 pipe_config->base.planes_changed &&
12944 !needs_modeset(&pipe_config->base)) {
3b150f08 12945 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
3b150f08
MR
12946
12947 /*
12948 * We need to make sure the primary plane is re-enabled if it
12949 * has previously been turned off.
12950 */
bb546623
ACO
12951 if (ret == 0 && !primary_plane_was_visible &&
12952 primary_plane_visible(set->crtc)) {
3b150f08 12953 WARN_ON(!intel_crtc->active);
87d4300a 12954 intel_post_enable_primary(set->crtc);
3b150f08
MR
12955 }
12956
7ca51a3a
JB
12957 /*
12958 * In the fastboot case this may be our only check of the
12959 * state after boot. It would be better to only do it on
12960 * the first update, but we don't have a nice way of doing that
12961 * (and really, set_config isn't used much for high freq page
12962 * flipping, so increasing its cost here shouldn't be a big
12963 * deal).
12964 */
d330a953 12965 if (i915.fastboot && ret == 0)
7ca51a3a 12966 intel_modeset_check_state(set->crtc->dev);
50f56119
DV
12967 }
12968
2d05eae1 12969 if (ret) {
bf67dfeb
DV
12970 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
12971 set->crtc->base.id, ret);
2d05eae1 12972 }
50f56119 12973
7cbf41d6 12974out:
2bfb4627
ACO
12975 if (ret)
12976 drm_atomic_state_free(state);
50f56119
DV
12977 return ret;
12978}
f6e5b160
CW
12979
12980static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160 12981 .gamma_set = intel_crtc_gamma_set,
50f56119 12982 .set_config = intel_crtc_set_config,
f6e5b160
CW
12983 .destroy = intel_crtc_destroy,
12984 .page_flip = intel_crtc_page_flip,
1356837e
MR
12985 .atomic_duplicate_state = intel_crtc_duplicate_state,
12986 .atomic_destroy_state = intel_crtc_destroy_state,
f6e5b160
CW
12987};
12988
5358901f
DV
12989static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
12990 struct intel_shared_dpll *pll,
12991 struct intel_dpll_hw_state *hw_state)
ee7b9f93 12992{
5358901f 12993 uint32_t val;
ee7b9f93 12994
f458ebbc 12995 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
bd2bb1b9
PZ
12996 return false;
12997
5358901f 12998 val = I915_READ(PCH_DPLL(pll->id));
66e985c0
DV
12999 hw_state->dpll = val;
13000 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
13001 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
5358901f
DV
13002
13003 return val & DPLL_VCO_ENABLE;
13004}
13005
15bdd4cf
DV
13006static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
13007 struct intel_shared_dpll *pll)
13008{
3e369b76
ACO
13009 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
13010 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
15bdd4cf
DV
13011}
13012
e7b903d2
DV
13013static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
13014 struct intel_shared_dpll *pll)
13015{
e7b903d2 13016 /* PCH refclock must be enabled first */
89eff4be 13017 ibx_assert_pch_refclk_enabled(dev_priv);
e7b903d2 13018
3e369b76 13019 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
15bdd4cf
DV
13020
13021 /* Wait for the clocks to stabilize. */
13022 POSTING_READ(PCH_DPLL(pll->id));
13023 udelay(150);
13024
13025 /* The pixel multiplier can only be updated once the
13026 * DPLL is enabled and the clocks are stable.
13027 *
13028 * So write it again.
13029 */
3e369b76 13030 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
15bdd4cf 13031 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV
13032 udelay(200);
13033}
13034
13035static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
13036 struct intel_shared_dpll *pll)
13037{
13038 struct drm_device *dev = dev_priv->dev;
13039 struct intel_crtc *crtc;
e7b903d2
DV
13040
13041 /* Make sure no transcoder isn't still depending on us. */
d3fcc808 13042 for_each_intel_crtc(dev, crtc) {
e7b903d2
DV
13043 if (intel_crtc_to_shared_dpll(crtc) == pll)
13044 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
ee7b9f93
JB
13045 }
13046
15bdd4cf
DV
13047 I915_WRITE(PCH_DPLL(pll->id), 0);
13048 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV
13049 udelay(200);
13050}
13051
46edb027
DV
13052static char *ibx_pch_dpll_names[] = {
13053 "PCH DPLL A",
13054 "PCH DPLL B",
13055};
13056
7c74ade1 13057static void ibx_pch_dpll_init(struct drm_device *dev)
ee7b9f93 13058{
e7b903d2 13059 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93
JB
13060 int i;
13061
7c74ade1 13062 dev_priv->num_shared_dpll = 2;
ee7b9f93 13063
e72f9fbf 13064 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
46edb027
DV
13065 dev_priv->shared_dplls[i].id = i;
13066 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
15bdd4cf 13067 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
e7b903d2
DV
13068 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
13069 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
5358901f
DV
13070 dev_priv->shared_dplls[i].get_hw_state =
13071 ibx_pch_dpll_get_hw_state;
ee7b9f93
JB
13072 }
13073}
13074
7c74ade1
DV
13075static void intel_shared_dpll_init(struct drm_device *dev)
13076{
e7b903d2 13077 struct drm_i915_private *dev_priv = dev->dev_private;
7c74ade1 13078
9cd86933
DV
13079 if (HAS_DDI(dev))
13080 intel_ddi_pll_init(dev);
13081 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7c74ade1
DV
13082 ibx_pch_dpll_init(dev);
13083 else
13084 dev_priv->num_shared_dpll = 0;
13085
13086 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
7c74ade1
DV
13087}
13088
1fc0a8f7
TU
13089/**
13090 * intel_wm_need_update - Check whether watermarks need updating
13091 * @plane: drm plane
13092 * @state: new plane state
13093 *
13094 * Check current plane state versus the new one to determine whether
13095 * watermarks need to be recalculated.
13096 *
13097 * Returns true or false.
13098 */
13099bool intel_wm_need_update(struct drm_plane *plane,
13100 struct drm_plane_state *state)
13101{
13102 /* Update watermarks on tiling changes. */
13103 if (!plane->state->fb || !state->fb ||
13104 plane->state->fb->modifier[0] != state->fb->modifier[0] ||
13105 plane->state->rotation != state->rotation)
13106 return true;
13107
13108 return false;
13109}
13110
6beb8c23
MR
13111/**
13112 * intel_prepare_plane_fb - Prepare fb for usage on plane
13113 * @plane: drm plane to prepare for
13114 * @fb: framebuffer to prepare for presentation
13115 *
13116 * Prepares a framebuffer for usage on a display plane. Generally this
13117 * involves pinning the underlying object and updating the frontbuffer tracking
13118 * bits. Some older platforms need special physical address handling for
13119 * cursor planes.
13120 *
13121 * Returns 0 on success, negative error code on failure.
13122 */
13123int
13124intel_prepare_plane_fb(struct drm_plane *plane,
d136dfee
TU
13125 struct drm_framebuffer *fb,
13126 const struct drm_plane_state *new_state)
465c120c
MR
13127{
13128 struct drm_device *dev = plane->dev;
6beb8c23
MR
13129 struct intel_plane *intel_plane = to_intel_plane(plane);
13130 enum pipe pipe = intel_plane->pipe;
13131 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13132 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
13133 unsigned frontbuffer_bits = 0;
13134 int ret = 0;
465c120c 13135
ea2c67bb 13136 if (!obj)
465c120c
MR
13137 return 0;
13138
6beb8c23
MR
13139 switch (plane->type) {
13140 case DRM_PLANE_TYPE_PRIMARY:
13141 frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(pipe);
13142 break;
13143 case DRM_PLANE_TYPE_CURSOR:
13144 frontbuffer_bits = INTEL_FRONTBUFFER_CURSOR(pipe);
13145 break;
13146 case DRM_PLANE_TYPE_OVERLAY:
13147 frontbuffer_bits = INTEL_FRONTBUFFER_SPRITE(pipe);
13148 break;
13149 }
465c120c 13150
6beb8c23 13151 mutex_lock(&dev->struct_mutex);
465c120c 13152
6beb8c23
MR
13153 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13154 INTEL_INFO(dev)->cursor_needs_physical) {
13155 int align = IS_I830(dev) ? 16 * 1024 : 256;
13156 ret = i915_gem_object_attach_phys(obj, align);
13157 if (ret)
13158 DRM_DEBUG_KMS("failed to attach phys object\n");
13159 } else {
82bc3b2d 13160 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL);
6beb8c23 13161 }
465c120c 13162
6beb8c23
MR
13163 if (ret == 0)
13164 i915_gem_track_fb(old_obj, obj, frontbuffer_bits);
fdd508a6 13165
4c34574f 13166 mutex_unlock(&dev->struct_mutex);
465c120c 13167
6beb8c23
MR
13168 return ret;
13169}
13170
38f3ce3a
MR
13171/**
13172 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13173 * @plane: drm plane to clean up for
13174 * @fb: old framebuffer that was on plane
13175 *
13176 * Cleans up a framebuffer that has just been removed from a plane.
13177 */
13178void
13179intel_cleanup_plane_fb(struct drm_plane *plane,
d136dfee
TU
13180 struct drm_framebuffer *fb,
13181 const struct drm_plane_state *old_state)
38f3ce3a
MR
13182{
13183 struct drm_device *dev = plane->dev;
13184 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13185
13186 if (WARN_ON(!obj))
13187 return;
13188
13189 if (plane->type != DRM_PLANE_TYPE_CURSOR ||
13190 !INTEL_INFO(dev)->cursor_needs_physical) {
13191 mutex_lock(&dev->struct_mutex);
82bc3b2d 13192 intel_unpin_fb_obj(fb, old_state);
38f3ce3a
MR
13193 mutex_unlock(&dev->struct_mutex);
13194 }
465c120c
MR
13195}
13196
6156a456
CK
13197int
13198skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13199{
13200 int max_scale;
13201 struct drm_device *dev;
13202 struct drm_i915_private *dev_priv;
13203 int crtc_clock, cdclk;
13204
13205 if (!intel_crtc || !crtc_state)
13206 return DRM_PLANE_HELPER_NO_SCALING;
13207
13208 dev = intel_crtc->base.dev;
13209 dev_priv = dev->dev_private;
13210 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13211 cdclk = dev_priv->display.get_display_clock_speed(dev);
13212
13213 if (!crtc_clock || !cdclk)
13214 return DRM_PLANE_HELPER_NO_SCALING;
13215
13216 /*
13217 * skl max scale is lower of:
13218 * close to 3 but not 3, -1 is for that purpose
13219 * or
13220 * cdclk/crtc_clock
13221 */
13222 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13223
13224 return max_scale;
13225}
13226
465c120c 13227static int
3c692a41
GP
13228intel_check_primary_plane(struct drm_plane *plane,
13229 struct intel_plane_state *state)
13230{
32b7eeec
MR
13231 struct drm_device *dev = plane->dev;
13232 struct drm_i915_private *dev_priv = dev->dev_private;
2b875c22 13233 struct drm_crtc *crtc = state->base.crtc;
ea2c67bb 13234 struct intel_crtc *intel_crtc;
6156a456 13235 struct intel_crtc_state *crtc_state;
2b875c22 13236 struct drm_framebuffer *fb = state->base.fb;
3c692a41
GP
13237 struct drm_rect *dest = &state->dst;
13238 struct drm_rect *src = &state->src;
13239 const struct drm_rect *clip = &state->clip;
d8106366 13240 bool can_position = false;
6156a456
CK
13241 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13242 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
465c120c
MR
13243 int ret;
13244
ea2c67bb
MR
13245 crtc = crtc ? crtc : plane->crtc;
13246 intel_crtc = to_intel_crtc(crtc);
6156a456
CK
13247 crtc_state = state->base.state ?
13248 intel_atomic_get_crtc_state(state->base.state, intel_crtc) : NULL;
ea2c67bb 13249
6156a456 13250 if (INTEL_INFO(dev)->gen >= 9) {
225c228a
CK
13251 /* use scaler when colorkey is not required */
13252 if (to_intel_plane(plane)->ckey.flags == I915_SET_COLORKEY_NONE) {
13253 min_scale = 1;
13254 max_scale = skl_max_scale(intel_crtc, crtc_state);
13255 }
d8106366 13256 can_position = true;
6156a456 13257 }
d8106366 13258
c59cb179
MR
13259 ret = drm_plane_helper_check_update(plane, crtc, fb,
13260 src, dest, clip,
6156a456
CK
13261 min_scale,
13262 max_scale,
d8106366
SJ
13263 can_position, true,
13264 &state->visible);
c59cb179
MR
13265 if (ret)
13266 return ret;
465c120c 13267
32b7eeec 13268 if (intel_crtc->active) {
b70709a6
ML
13269 struct intel_plane_state *old_state =
13270 to_intel_plane_state(plane->state);
13271
32b7eeec
MR
13272 intel_crtc->atomic.wait_for_flips = true;
13273
13274 /*
13275 * FBC does not work on some platforms for rotated
13276 * planes, so disable it when rotation is not 0 and
13277 * update it when rotation is set back to 0.
13278 *
13279 * FIXME: This is redundant with the fbc update done in
13280 * the primary plane enable function except that that
13281 * one is done too late. We eventually need to unify
13282 * this.
13283 */
b70709a6 13284 if (state->visible &&
32b7eeec 13285 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
e35fef21 13286 dev_priv->fbc.crtc == intel_crtc &&
8e7d688b 13287 state->base.rotation != BIT(DRM_ROTATE_0)) {
32b7eeec
MR
13288 intel_crtc->atomic.disable_fbc = true;
13289 }
13290
b70709a6 13291 if (state->visible && !old_state->visible) {
32b7eeec
MR
13292 /*
13293 * BDW signals flip done immediately if the plane
13294 * is disabled, even if the plane enable is already
13295 * armed to occur at the next vblank :(
13296 */
b70709a6 13297 if (IS_BROADWELL(dev))
32b7eeec
MR
13298 intel_crtc->atomic.wait_vblank = true;
13299 }
13300
13301 intel_crtc->atomic.fb_bits |=
13302 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
13303
13304 intel_crtc->atomic.update_fbc = true;
0fda6568 13305
1fc0a8f7 13306 if (intel_wm_need_update(plane, &state->base))
0fda6568 13307 intel_crtc->atomic.update_wm = true;
ccc759dc
GP
13308 }
13309
6156a456
CK
13310 if (INTEL_INFO(dev)->gen >= 9) {
13311 ret = skl_update_scaler_users(intel_crtc, crtc_state,
13312 to_intel_plane(plane), state, 0);
13313 if (ret)
13314 return ret;
13315 }
13316
14af293f
GP
13317 return 0;
13318}
13319
13320static void
13321intel_commit_primary_plane(struct drm_plane *plane,
13322 struct intel_plane_state *state)
13323{
2b875c22
MR
13324 struct drm_crtc *crtc = state->base.crtc;
13325 struct drm_framebuffer *fb = state->base.fb;
13326 struct drm_device *dev = plane->dev;
14af293f 13327 struct drm_i915_private *dev_priv = dev->dev_private;
ea2c67bb 13328 struct intel_crtc *intel_crtc;
14af293f
GP
13329 struct drm_rect *src = &state->src;
13330
ea2c67bb
MR
13331 crtc = crtc ? crtc : plane->crtc;
13332 intel_crtc = to_intel_crtc(crtc);
cf4c7c12
MR
13333
13334 plane->fb = fb;
9dc806fc
MR
13335 crtc->x = src->x1 >> 16;
13336 crtc->y = src->y1 >> 16;
ccc759dc 13337
ccc759dc 13338 if (intel_crtc->active) {
27321ae8 13339 if (state->visible)
ccc759dc
GP
13340 /* FIXME: kill this fastboot hack */
13341 intel_update_pipe_size(intel_crtc);
465c120c 13342
27321ae8
ML
13343 dev_priv->display.update_primary_plane(crtc, plane->fb,
13344 crtc->x, crtc->y);
ccc759dc 13345 }
465c120c
MR
13346}
13347
a8ad0d8e
ML
13348static void
13349intel_disable_primary_plane(struct drm_plane *plane,
13350 struct drm_crtc *crtc,
13351 bool force)
13352{
13353 struct drm_device *dev = plane->dev;
13354 struct drm_i915_private *dev_priv = dev->dev_private;
13355
a8ad0d8e
ML
13356 dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
13357}
13358
32b7eeec 13359static void intel_begin_crtc_commit(struct drm_crtc *crtc)
3c692a41 13360{
32b7eeec 13361 struct drm_device *dev = crtc->dev;
140fd38d 13362 struct drm_i915_private *dev_priv = dev->dev_private;
3c692a41 13363 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ea2c67bb
MR
13364 struct intel_plane *intel_plane;
13365 struct drm_plane *p;
13366 unsigned fb_bits = 0;
13367
13368 /* Track fb's for any planes being disabled */
13369 list_for_each_entry(p, &dev->mode_config.plane_list, head) {
13370 intel_plane = to_intel_plane(p);
13371
13372 if (intel_crtc->atomic.disabled_planes &
13373 (1 << drm_plane_index(p))) {
13374 switch (p->type) {
13375 case DRM_PLANE_TYPE_PRIMARY:
13376 fb_bits = INTEL_FRONTBUFFER_PRIMARY(intel_plane->pipe);
13377 break;
13378 case DRM_PLANE_TYPE_CURSOR:
13379 fb_bits = INTEL_FRONTBUFFER_CURSOR(intel_plane->pipe);
13380 break;
13381 case DRM_PLANE_TYPE_OVERLAY:
13382 fb_bits = INTEL_FRONTBUFFER_SPRITE(intel_plane->pipe);
13383 break;
13384 }
3c692a41 13385
ea2c67bb
MR
13386 mutex_lock(&dev->struct_mutex);
13387 i915_gem_track_fb(intel_fb_obj(p->fb), NULL, fb_bits);
13388 mutex_unlock(&dev->struct_mutex);
13389 }
13390 }
3c692a41 13391
32b7eeec
MR
13392 if (intel_crtc->atomic.wait_for_flips)
13393 intel_crtc_wait_for_pending_flips(crtc);
3c692a41 13394
32b7eeec
MR
13395 if (intel_crtc->atomic.disable_fbc)
13396 intel_fbc_disable(dev);
3c692a41 13397
32b7eeec
MR
13398 if (intel_crtc->atomic.pre_disable_primary)
13399 intel_pre_disable_primary(crtc);
3c692a41 13400
32b7eeec
MR
13401 if (intel_crtc->atomic.update_wm)
13402 intel_update_watermarks(crtc);
3c692a41 13403
32b7eeec 13404 intel_runtime_pm_get(dev_priv);
3c692a41 13405
c34c9ee4
MR
13406 /* Perform vblank evasion around commit operation */
13407 if (intel_crtc->active)
13408 intel_crtc->atomic.evade =
13409 intel_pipe_update_start(intel_crtc,
13410 &intel_crtc->atomic.start_vbl_count);
32b7eeec
MR
13411}
13412
13413static void intel_finish_crtc_commit(struct drm_crtc *crtc)
13414{
13415 struct drm_device *dev = crtc->dev;
13416 struct drm_i915_private *dev_priv = dev->dev_private;
13417 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13418 struct drm_plane *p;
13419
c34c9ee4
MR
13420 if (intel_crtc->atomic.evade)
13421 intel_pipe_update_end(intel_crtc,
13422 intel_crtc->atomic.start_vbl_count);
3c692a41 13423
140fd38d 13424 intel_runtime_pm_put(dev_priv);
3c692a41 13425
32b7eeec
MR
13426 if (intel_crtc->atomic.wait_vblank)
13427 intel_wait_for_vblank(dev, intel_crtc->pipe);
13428
13429 intel_frontbuffer_flip(dev, intel_crtc->atomic.fb_bits);
13430
13431 if (intel_crtc->atomic.update_fbc) {
ccc759dc 13432 mutex_lock(&dev->struct_mutex);
7ff0ebcc 13433 intel_fbc_update(dev);
ccc759dc 13434 mutex_unlock(&dev->struct_mutex);
38f3ce3a 13435 }
3c692a41 13436
32b7eeec
MR
13437 if (intel_crtc->atomic.post_enable_primary)
13438 intel_post_enable_primary(crtc);
3c692a41 13439
32b7eeec
MR
13440 drm_for_each_legacy_plane(p, &dev->mode_config.plane_list)
13441 if (intel_crtc->atomic.update_sprite_watermarks & drm_plane_index(p))
13442 intel_update_sprite_watermarks(p, crtc, 0, 0, 0,
13443 false, false);
13444
13445 memset(&intel_crtc->atomic, 0, sizeof(intel_crtc->atomic));
3c692a41
GP
13446}
13447
cf4c7c12 13448/**
4a3b8769
MR
13449 * intel_plane_destroy - destroy a plane
13450 * @plane: plane to destroy
cf4c7c12 13451 *
4a3b8769
MR
13452 * Common destruction function for all types of planes (primary, cursor,
13453 * sprite).
cf4c7c12 13454 */
4a3b8769 13455void intel_plane_destroy(struct drm_plane *plane)
465c120c
MR
13456{
13457 struct intel_plane *intel_plane = to_intel_plane(plane);
13458 drm_plane_cleanup(plane);
13459 kfree(intel_plane);
13460}
13461
65a3fea0 13462const struct drm_plane_funcs intel_plane_funcs = {
70a101f8
MR
13463 .update_plane = drm_atomic_helper_update_plane,
13464 .disable_plane = drm_atomic_helper_disable_plane,
3d7d6510 13465 .destroy = intel_plane_destroy,
c196e1d6 13466 .set_property = drm_atomic_helper_plane_set_property,
a98b3431
MR
13467 .atomic_get_property = intel_plane_atomic_get_property,
13468 .atomic_set_property = intel_plane_atomic_set_property,
ea2c67bb
MR
13469 .atomic_duplicate_state = intel_plane_duplicate_state,
13470 .atomic_destroy_state = intel_plane_destroy_state,
13471
465c120c
MR
13472};
13473
13474static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13475 int pipe)
13476{
13477 struct intel_plane *primary;
8e7d688b 13478 struct intel_plane_state *state;
465c120c
MR
13479 const uint32_t *intel_primary_formats;
13480 int num_formats;
13481
13482 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13483 if (primary == NULL)
13484 return NULL;
13485
8e7d688b
MR
13486 state = intel_create_plane_state(&primary->base);
13487 if (!state) {
ea2c67bb
MR
13488 kfree(primary);
13489 return NULL;
13490 }
8e7d688b 13491 primary->base.state = &state->base;
ea2c67bb 13492
465c120c
MR
13493 primary->can_scale = false;
13494 primary->max_downscale = 1;
6156a456
CK
13495 if (INTEL_INFO(dev)->gen >= 9) {
13496 primary->can_scale = true;
af99ceda 13497 state->scaler_id = -1;
6156a456 13498 }
465c120c
MR
13499 primary->pipe = pipe;
13500 primary->plane = pipe;
c59cb179
MR
13501 primary->check_plane = intel_check_primary_plane;
13502 primary->commit_plane = intel_commit_primary_plane;
a8ad0d8e 13503 primary->disable_plane = intel_disable_primary_plane;
08e221fb 13504 primary->ckey.flags = I915_SET_COLORKEY_NONE;
465c120c
MR
13505 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13506 primary->plane = !pipe;
13507
6c0fd451
DL
13508 if (INTEL_INFO(dev)->gen >= 9) {
13509 intel_primary_formats = skl_primary_formats;
13510 num_formats = ARRAY_SIZE(skl_primary_formats);
13511 } else if (INTEL_INFO(dev)->gen >= 4) {
568db4f2
DL
13512 intel_primary_formats = i965_primary_formats;
13513 num_formats = ARRAY_SIZE(i965_primary_formats);
6c0fd451
DL
13514 } else {
13515 intel_primary_formats = i8xx_primary_formats;
13516 num_formats = ARRAY_SIZE(i8xx_primary_formats);
465c120c
MR
13517 }
13518
13519 drm_universal_plane_init(dev, &primary->base, 0,
65a3fea0 13520 &intel_plane_funcs,
465c120c
MR
13521 intel_primary_formats, num_formats,
13522 DRM_PLANE_TYPE_PRIMARY);
48404c1e 13523
3b7a5119
SJ
13524 if (INTEL_INFO(dev)->gen >= 4)
13525 intel_create_rotation_property(dev, primary);
48404c1e 13526
ea2c67bb
MR
13527 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13528
465c120c
MR
13529 return &primary->base;
13530}
13531
3b7a5119
SJ
13532void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13533{
13534 if (!dev->mode_config.rotation_property) {
13535 unsigned long flags = BIT(DRM_ROTATE_0) |
13536 BIT(DRM_ROTATE_180);
13537
13538 if (INTEL_INFO(dev)->gen >= 9)
13539 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13540
13541 dev->mode_config.rotation_property =
13542 drm_mode_create_rotation_property(dev, flags);
13543 }
13544 if (dev->mode_config.rotation_property)
13545 drm_object_attach_property(&plane->base.base,
13546 dev->mode_config.rotation_property,
13547 plane->base.state->rotation);
13548}
13549
3d7d6510 13550static int
852e787c
GP
13551intel_check_cursor_plane(struct drm_plane *plane,
13552 struct intel_plane_state *state)
3d7d6510 13553{
2b875c22 13554 struct drm_crtc *crtc = state->base.crtc;
ea2c67bb 13555 struct drm_device *dev = plane->dev;
2b875c22 13556 struct drm_framebuffer *fb = state->base.fb;
852e787c
GP
13557 struct drm_rect *dest = &state->dst;
13558 struct drm_rect *src = &state->src;
13559 const struct drm_rect *clip = &state->clip;
757f9a3e 13560 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
ea2c67bb 13561 struct intel_crtc *intel_crtc;
757f9a3e
GP
13562 unsigned stride;
13563 int ret;
3d7d6510 13564
ea2c67bb
MR
13565 crtc = crtc ? crtc : plane->crtc;
13566 intel_crtc = to_intel_crtc(crtc);
13567
757f9a3e 13568 ret = drm_plane_helper_check_update(plane, crtc, fb,
852e787c 13569 src, dest, clip,
3d7d6510
MR
13570 DRM_PLANE_HELPER_NO_SCALING,
13571 DRM_PLANE_HELPER_NO_SCALING,
852e787c 13572 true, true, &state->visible);
757f9a3e
GP
13573 if (ret)
13574 return ret;
13575
13576
13577 /* if we want to turn off the cursor ignore width and height */
13578 if (!obj)
32b7eeec 13579 goto finish;
757f9a3e 13580
757f9a3e 13581 /* Check for which cursor types we support */
ea2c67bb
MR
13582 if (!cursor_size_ok(dev, state->base.crtc_w, state->base.crtc_h)) {
13583 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13584 state->base.crtc_w, state->base.crtc_h);
757f9a3e
GP
13585 return -EINVAL;
13586 }
13587
ea2c67bb
MR
13588 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13589 if (obj->base.size < stride * state->base.crtc_h) {
757f9a3e
GP
13590 DRM_DEBUG_KMS("buffer is too small\n");
13591 return -ENOMEM;
13592 }
13593
3a656b54 13594 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
757f9a3e
GP
13595 DRM_DEBUG_KMS("cursor cannot be tiled\n");
13596 ret = -EINVAL;
13597 }
757f9a3e 13598
32b7eeec
MR
13599finish:
13600 if (intel_crtc->active) {
3749f463 13601 if (plane->state->crtc_w != state->base.crtc_w)
32b7eeec
MR
13602 intel_crtc->atomic.update_wm = true;
13603
13604 intel_crtc->atomic.fb_bits |=
13605 INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe);
13606 }
13607
757f9a3e 13608 return ret;
852e787c 13609}
3d7d6510 13610
a8ad0d8e
ML
13611static void
13612intel_disable_cursor_plane(struct drm_plane *plane,
13613 struct drm_crtc *crtc,
13614 bool force)
13615{
13616 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13617
13618 if (!force) {
13619 plane->fb = NULL;
13620 intel_crtc->cursor_bo = NULL;
13621 intel_crtc->cursor_addr = 0;
13622 }
13623
13624 intel_crtc_update_cursor(crtc, false);
13625}
13626
f4a2cf29 13627static void
852e787c
GP
13628intel_commit_cursor_plane(struct drm_plane *plane,
13629 struct intel_plane_state *state)
13630{
2b875c22 13631 struct drm_crtc *crtc = state->base.crtc;
ea2c67bb
MR
13632 struct drm_device *dev = plane->dev;
13633 struct intel_crtc *intel_crtc;
2b875c22 13634 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
a912f12f 13635 uint32_t addr;
852e787c 13636
ea2c67bb
MR
13637 crtc = crtc ? crtc : plane->crtc;
13638 intel_crtc = to_intel_crtc(crtc);
13639
2b875c22 13640 plane->fb = state->base.fb;
ea2c67bb
MR
13641 crtc->cursor_x = state->base.crtc_x;
13642 crtc->cursor_y = state->base.crtc_y;
13643
a912f12f
GP
13644 if (intel_crtc->cursor_bo == obj)
13645 goto update;
4ed91096 13646
f4a2cf29 13647 if (!obj)
a912f12f 13648 addr = 0;
f4a2cf29 13649 else if (!INTEL_INFO(dev)->cursor_needs_physical)
a912f12f 13650 addr = i915_gem_obj_ggtt_offset(obj);
f4a2cf29 13651 else
a912f12f 13652 addr = obj->phys_handle->busaddr;
852e787c 13653
a912f12f
GP
13654 intel_crtc->cursor_addr = addr;
13655 intel_crtc->cursor_bo = obj;
13656update:
852e787c 13657
32b7eeec 13658 if (intel_crtc->active)
a912f12f 13659 intel_crtc_update_cursor(crtc, state->visible);
852e787c
GP
13660}
13661
3d7d6510
MR
13662static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
13663 int pipe)
13664{
13665 struct intel_plane *cursor;
8e7d688b 13666 struct intel_plane_state *state;
3d7d6510
MR
13667
13668 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13669 if (cursor == NULL)
13670 return NULL;
13671
8e7d688b
MR
13672 state = intel_create_plane_state(&cursor->base);
13673 if (!state) {
ea2c67bb
MR
13674 kfree(cursor);
13675 return NULL;
13676 }
8e7d688b 13677 cursor->base.state = &state->base;
ea2c67bb 13678
3d7d6510
MR
13679 cursor->can_scale = false;
13680 cursor->max_downscale = 1;
13681 cursor->pipe = pipe;
13682 cursor->plane = pipe;
c59cb179
MR
13683 cursor->check_plane = intel_check_cursor_plane;
13684 cursor->commit_plane = intel_commit_cursor_plane;
a8ad0d8e 13685 cursor->disable_plane = intel_disable_cursor_plane;
3d7d6510
MR
13686
13687 drm_universal_plane_init(dev, &cursor->base, 0,
65a3fea0 13688 &intel_plane_funcs,
3d7d6510
MR
13689 intel_cursor_formats,
13690 ARRAY_SIZE(intel_cursor_formats),
13691 DRM_PLANE_TYPE_CURSOR);
4398ad45
VS
13692
13693 if (INTEL_INFO(dev)->gen >= 4) {
13694 if (!dev->mode_config.rotation_property)
13695 dev->mode_config.rotation_property =
13696 drm_mode_create_rotation_property(dev,
13697 BIT(DRM_ROTATE_0) |
13698 BIT(DRM_ROTATE_180));
13699 if (dev->mode_config.rotation_property)
13700 drm_object_attach_property(&cursor->base.base,
13701 dev->mode_config.rotation_property,
8e7d688b 13702 state->base.rotation);
4398ad45
VS
13703 }
13704
af99ceda
CK
13705 if (INTEL_INFO(dev)->gen >=9)
13706 state->scaler_id = -1;
13707
ea2c67bb
MR
13708 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13709
3d7d6510
MR
13710 return &cursor->base;
13711}
13712
549e2bfb
CK
13713static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
13714 struct intel_crtc_state *crtc_state)
13715{
13716 int i;
13717 struct intel_scaler *intel_scaler;
13718 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
13719
13720 for (i = 0; i < intel_crtc->num_scalers; i++) {
13721 intel_scaler = &scaler_state->scalers[i];
13722 intel_scaler->in_use = 0;
13723 intel_scaler->id = i;
13724
13725 intel_scaler->mode = PS_SCALER_MODE_DYN;
13726 }
13727
13728 scaler_state->scaler_id = -1;
13729}
13730
b358d0a6 13731static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 13732{
fbee40df 13733 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 13734 struct intel_crtc *intel_crtc;
f5de6e07 13735 struct intel_crtc_state *crtc_state = NULL;
3d7d6510
MR
13736 struct drm_plane *primary = NULL;
13737 struct drm_plane *cursor = NULL;
465c120c 13738 int i, ret;
79e53945 13739
955382f3 13740 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
79e53945
JB
13741 if (intel_crtc == NULL)
13742 return;
13743
f5de6e07
ACO
13744 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13745 if (!crtc_state)
13746 goto fail;
550acefd
ACO
13747 intel_crtc->config = crtc_state;
13748 intel_crtc->base.state = &crtc_state->base;
07878248 13749 crtc_state->base.crtc = &intel_crtc->base;
f5de6e07 13750
549e2bfb
CK
13751 /* initialize shared scalers */
13752 if (INTEL_INFO(dev)->gen >= 9) {
13753 if (pipe == PIPE_C)
13754 intel_crtc->num_scalers = 1;
13755 else
13756 intel_crtc->num_scalers = SKL_NUM_SCALERS;
13757
13758 skl_init_scalers(dev, intel_crtc, crtc_state);
13759 }
13760
465c120c 13761 primary = intel_primary_plane_create(dev, pipe);
3d7d6510
MR
13762 if (!primary)
13763 goto fail;
13764
13765 cursor = intel_cursor_plane_create(dev, pipe);
13766 if (!cursor)
13767 goto fail;
13768
465c120c 13769 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
3d7d6510
MR
13770 cursor, &intel_crtc_funcs);
13771 if (ret)
13772 goto fail;
79e53945
JB
13773
13774 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB
13775 for (i = 0; i < 256; i++) {
13776 intel_crtc->lut_r[i] = i;
13777 intel_crtc->lut_g[i] = i;
13778 intel_crtc->lut_b[i] = i;
13779 }
13780
1f1c2e24
VS
13781 /*
13782 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
8c0f92e1 13783 * is hooked to pipe B. Hence we want plane A feeding pipe B.
1f1c2e24 13784 */
80824003
JB
13785 intel_crtc->pipe = pipe;
13786 intel_crtc->plane = pipe;
3a77c4c4 13787 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
28c97730 13788 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 13789 intel_crtc->plane = !pipe;
80824003
JB
13790 }
13791
4b0e333e
CW
13792 intel_crtc->cursor_base = ~0;
13793 intel_crtc->cursor_cntl = ~0;
dc41c154 13794 intel_crtc->cursor_size = ~0;
8d7849db 13795
22fd0fab
JB
13796 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
13797 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
13798 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
13799 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
13800
79e53945 13801 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
87b6b101
DV
13802
13803 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
3d7d6510
MR
13804 return;
13805
13806fail:
13807 if (primary)
13808 drm_plane_cleanup(primary);
13809 if (cursor)
13810 drm_plane_cleanup(cursor);
f5de6e07 13811 kfree(crtc_state);
3d7d6510 13812 kfree(intel_crtc);
79e53945
JB
13813}
13814
752aa88a
JB
13815enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
13816{
13817 struct drm_encoder *encoder = connector->base.encoder;
6e9f798d 13818 struct drm_device *dev = connector->base.dev;
752aa88a 13819
51fd371b 13820 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
752aa88a 13821
d3babd3f 13822 if (!encoder || WARN_ON(!encoder->crtc))
752aa88a
JB
13823 return INVALID_PIPE;
13824
13825 return to_intel_crtc(encoder->crtc)->pipe;
13826}
13827
08d7b3d1 13828int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 13829 struct drm_file *file)
08d7b3d1 13830{
08d7b3d1 13831 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7707e653 13832 struct drm_crtc *drmmode_crtc;
c05422d5 13833 struct intel_crtc *crtc;
08d7b3d1 13834
7707e653 13835 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
08d7b3d1 13836
7707e653 13837 if (!drmmode_crtc) {
08d7b3d1 13838 DRM_ERROR("no such CRTC id\n");
3f2c2057 13839 return -ENOENT;
08d7b3d1
CW
13840 }
13841
7707e653 13842 crtc = to_intel_crtc(drmmode_crtc);
c05422d5 13843 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 13844
c05422d5 13845 return 0;
08d7b3d1
CW
13846}
13847
66a9278e 13848static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 13849{
66a9278e
DV
13850 struct drm_device *dev = encoder->base.dev;
13851 struct intel_encoder *source_encoder;
79e53945 13852 int index_mask = 0;
79e53945
JB
13853 int entry = 0;
13854
b2784e15 13855 for_each_intel_encoder(dev, source_encoder) {
bc079e8b 13856 if (encoders_cloneable(encoder, source_encoder))
66a9278e
DV
13857 index_mask |= (1 << entry);
13858
79e53945
JB
13859 entry++;
13860 }
4ef69c7a 13861
79e53945
JB
13862 return index_mask;
13863}
13864
4d302442
CW
13865static bool has_edp_a(struct drm_device *dev)
13866{
13867 struct drm_i915_private *dev_priv = dev->dev_private;
13868
13869 if (!IS_MOBILE(dev))
13870 return false;
13871
13872 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
13873 return false;
13874
e3589908 13875 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
4d302442
CW
13876 return false;
13877
13878 return true;
13879}
13880
84b4e042
JB
13881static bool intel_crt_present(struct drm_device *dev)
13882{
13883 struct drm_i915_private *dev_priv = dev->dev_private;
13884
884497ed
DL
13885 if (INTEL_INFO(dev)->gen >= 9)
13886 return false;
13887
cf404ce4 13888 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
84b4e042
JB
13889 return false;
13890
13891 if (IS_CHERRYVIEW(dev))
13892 return false;
13893
13894 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
13895 return false;
13896
13897 return true;
13898}
13899
79e53945
JB
13900static void intel_setup_outputs(struct drm_device *dev)
13901{
725e30ad 13902 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 13903 struct intel_encoder *encoder;
cb0953d7 13904 bool dpd_is_edp = false;
79e53945 13905
c9093354 13906 intel_lvds_init(dev);
79e53945 13907
84b4e042 13908 if (intel_crt_present(dev))
79935fca 13909 intel_crt_init(dev);
cb0953d7 13910
c776eb2e
VK
13911 if (IS_BROXTON(dev)) {
13912 /*
13913 * FIXME: Broxton doesn't support port detection via the
13914 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
13915 * detect the ports.
13916 */
13917 intel_ddi_init(dev, PORT_A);
13918 intel_ddi_init(dev, PORT_B);
13919 intel_ddi_init(dev, PORT_C);
13920 } else if (HAS_DDI(dev)) {
0e72a5b5
ED
13921 int found;
13922
de31facd
JB
13923 /*
13924 * Haswell uses DDI functions to detect digital outputs.
13925 * On SKL pre-D0 the strap isn't connected, so we assume
13926 * it's there.
13927 */
0e72a5b5 13928 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
de31facd
JB
13929 /* WaIgnoreDDIAStrap: skl */
13930 if (found ||
13931 (IS_SKYLAKE(dev) && INTEL_REVID(dev) < SKL_REVID_D0))
0e72a5b5
ED
13932 intel_ddi_init(dev, PORT_A);
13933
13934 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
13935 * register */
13936 found = I915_READ(SFUSE_STRAP);
13937
13938 if (found & SFUSE_STRAP_DDIB_DETECTED)
13939 intel_ddi_init(dev, PORT_B);
13940 if (found & SFUSE_STRAP_DDIC_DETECTED)
13941 intel_ddi_init(dev, PORT_C);
13942 if (found & SFUSE_STRAP_DDID_DETECTED)
13943 intel_ddi_init(dev, PORT_D);
13944 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 13945 int found;
5d8a7752 13946 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
270b3042
DV
13947
13948 if (has_edp_a(dev))
13949 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 13950
dc0fa718 13951 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 13952 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 13953 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 13954 if (!found)
e2debe91 13955 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 13956 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 13957 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW
13958 }
13959
dc0fa718 13960 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 13961 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 13962
dc0fa718 13963 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 13964 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 13965
5eb08b69 13966 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 13967 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 13968
270b3042 13969 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 13970 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 13971 } else if (IS_VALLEYVIEW(dev)) {
e17ac6db
VS
13972 /*
13973 * The DP_DETECTED bit is the latched state of the DDC
13974 * SDA pin at boot. However since eDP doesn't require DDC
13975 * (no way to plug in a DP->HDMI dongle) the DDC pins for
13976 * eDP ports may have been muxed to an alternate function.
13977 * Thus we can't rely on the DP_DETECTED bit alone to detect
13978 * eDP ports. Consult the VBT as well as DP_DETECTED to
13979 * detect eDP ports.
13980 */
d2182a66
VS
13981 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
13982 !intel_dp_is_edp(dev, PORT_B))
585a94b8
AB
13983 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
13984 PORT_B);
e17ac6db
VS
13985 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
13986 intel_dp_is_edp(dev, PORT_B))
13987 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
585a94b8 13988
d2182a66
VS
13989 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
13990 !intel_dp_is_edp(dev, PORT_C))
6f6005a5
JB
13991 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
13992 PORT_C);
e17ac6db
VS
13993 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
13994 intel_dp_is_edp(dev, PORT_C))
13995 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
19c03924 13996
9418c1f1 13997 if (IS_CHERRYVIEW(dev)) {
e17ac6db 13998 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
9418c1f1
VS
13999 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
14000 PORT_D);
e17ac6db
VS
14001 /* eDP not supported on port D, so don't check VBT */
14002 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
14003 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
9418c1f1
VS
14004 }
14005
3cfca973 14006 intel_dsi_init(dev);
103a196f 14007 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 14008 bool found = false;
7d57382e 14009
e2debe91 14010 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 14011 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 14012 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
b01f2c3a
JB
14013 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
14014 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 14015 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 14016 }
27185ae1 14017
e7281eab 14018 if (!found && SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 14019 intel_dp_init(dev, DP_B, PORT_B);
725e30ad 14020 }
13520b05
KH
14021
14022 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 14023
e2debe91 14024 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 14025 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 14026 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 14027 }
27185ae1 14028
e2debe91 14029 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 14030
b01f2c3a
JB
14031 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
14032 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 14033 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a 14034 }
e7281eab 14035 if (SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 14036 intel_dp_init(dev, DP_C, PORT_C);
725e30ad 14037 }
27185ae1 14038
b01f2c3a 14039 if (SUPPORTS_INTEGRATED_DP(dev) &&
e7281eab 14040 (I915_READ(DP_D) & DP_DETECTED))
ab9d7c30 14041 intel_dp_init(dev, DP_D, PORT_D);
bad720ff 14042 } else if (IS_GEN2(dev))
79e53945
JB
14043 intel_dvo_init(dev);
14044
103a196f 14045 if (SUPPORTS_TV(dev))
79e53945
JB
14046 intel_tv_init(dev);
14047
0bc12bcb 14048 intel_psr_init(dev);
7c8f8a70 14049
b2784e15 14050 for_each_intel_encoder(dev, encoder) {
4ef69c7a
CW
14051 encoder->base.possible_crtcs = encoder->crtc_mask;
14052 encoder->base.possible_clones =
66a9278e 14053 intel_encoder_clones(encoder);
79e53945 14054 }
47356eb6 14055
dde86e2d 14056 intel_init_pch_refclk(dev);
270b3042
DV
14057
14058 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB
14059}
14060
14061static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14062{
60a5ca01 14063 struct drm_device *dev = fb->dev;
79e53945 14064 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945 14065
ef2d633e 14066 drm_framebuffer_cleanup(fb);
60a5ca01 14067 mutex_lock(&dev->struct_mutex);
ef2d633e 14068 WARN_ON(!intel_fb->obj->framebuffer_references--);
60a5ca01
VS
14069 drm_gem_object_unreference(&intel_fb->obj->base);
14070 mutex_unlock(&dev->struct_mutex);
79e53945
JB
14071 kfree(intel_fb);
14072}
14073
14074static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 14075 struct drm_file *file,
79e53945
JB
14076 unsigned int *handle)
14077{
14078 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 14079 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 14080
05394f39 14081 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB
14082}
14083
14084static const struct drm_framebuffer_funcs intel_fb_funcs = {
14085 .destroy = intel_user_framebuffer_destroy,
14086 .create_handle = intel_user_framebuffer_create_handle,
14087};
14088
b321803d
DL
14089static
14090u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14091 uint32_t pixel_format)
14092{
14093 u32 gen = INTEL_INFO(dev)->gen;
14094
14095 if (gen >= 9) {
14096 /* "The stride in bytes must not exceed the of the size of 8K
14097 * pixels and 32K bytes."
14098 */
14099 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
14100 } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
14101 return 32*1024;
14102 } else if (gen >= 4) {
14103 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14104 return 16*1024;
14105 else
14106 return 32*1024;
14107 } else if (gen >= 3) {
14108 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14109 return 8*1024;
14110 else
14111 return 16*1024;
14112 } else {
14113 /* XXX DSPC is limited to 4k tiled */
14114 return 8*1024;
14115 }
14116}
14117
b5ea642a
DV
14118static int intel_framebuffer_init(struct drm_device *dev,
14119 struct intel_framebuffer *intel_fb,
14120 struct drm_mode_fb_cmd2 *mode_cmd,
14121 struct drm_i915_gem_object *obj)
79e53945 14122{
6761dd31 14123 unsigned int aligned_height;
79e53945 14124 int ret;
b321803d 14125 u32 pitch_limit, stride_alignment;
79e53945 14126
dd4916c5
DV
14127 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14128
2a80eada
DV
14129 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14130 /* Enforce that fb modifier and tiling mode match, but only for
14131 * X-tiled. This is needed for FBC. */
14132 if (!!(obj->tiling_mode == I915_TILING_X) !=
14133 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14134 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14135 return -EINVAL;
14136 }
14137 } else {
14138 if (obj->tiling_mode == I915_TILING_X)
14139 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14140 else if (obj->tiling_mode == I915_TILING_Y) {
14141 DRM_DEBUG("No Y tiling for legacy addfb\n");
14142 return -EINVAL;
14143 }
14144 }
14145
9a8f0a12
TU
14146 /* Passed in modifier sanity checking. */
14147 switch (mode_cmd->modifier[0]) {
14148 case I915_FORMAT_MOD_Y_TILED:
14149 case I915_FORMAT_MOD_Yf_TILED:
14150 if (INTEL_INFO(dev)->gen < 9) {
14151 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14152 mode_cmd->modifier[0]);
14153 return -EINVAL;
14154 }
14155 case DRM_FORMAT_MOD_NONE:
14156 case I915_FORMAT_MOD_X_TILED:
14157 break;
14158 default:
c0f40428
JB
14159 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14160 mode_cmd->modifier[0]);
57cd6508 14161 return -EINVAL;
c16ed4be 14162 }
57cd6508 14163
b321803d
DL
14164 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
14165 mode_cmd->pixel_format);
14166 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14167 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14168 mode_cmd->pitches[0], stride_alignment);
57cd6508 14169 return -EINVAL;
c16ed4be 14170 }
57cd6508 14171
b321803d
DL
14172 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14173 mode_cmd->pixel_format);
a35cdaa0 14174 if (mode_cmd->pitches[0] > pitch_limit) {
b321803d
DL
14175 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14176 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
2a80eada 14177 "tiled" : "linear",
a35cdaa0 14178 mode_cmd->pitches[0], pitch_limit);
5d7bd705 14179 return -EINVAL;
c16ed4be 14180 }
5d7bd705 14181
2a80eada 14182 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
c16ed4be
CW
14183 mode_cmd->pitches[0] != obj->stride) {
14184 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14185 mode_cmd->pitches[0], obj->stride);
5d7bd705 14186 return -EINVAL;
c16ed4be 14187 }
5d7bd705 14188
57779d06 14189 /* Reject formats not supported by any plane early. */
308e5bcb 14190 switch (mode_cmd->pixel_format) {
57779d06 14191 case DRM_FORMAT_C8:
04b3924d
VS
14192 case DRM_FORMAT_RGB565:
14193 case DRM_FORMAT_XRGB8888:
14194 case DRM_FORMAT_ARGB8888:
57779d06
VS
14195 break;
14196 case DRM_FORMAT_XRGB1555:
c16ed4be 14197 if (INTEL_INFO(dev)->gen > 3) {
4ee62c76
VS
14198 DRM_DEBUG("unsupported pixel format: %s\n",
14199 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14200 return -EINVAL;
c16ed4be 14201 }
57779d06 14202 break;
57779d06 14203 case DRM_FORMAT_ABGR8888:
6c0fd451
DL
14204 if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) {
14205 DRM_DEBUG("unsupported pixel format: %s\n",
14206 drm_get_format_name(mode_cmd->pixel_format));
14207 return -EINVAL;
14208 }
14209 break;
14210 case DRM_FORMAT_XBGR8888:
04b3924d 14211 case DRM_FORMAT_XRGB2101010:
57779d06 14212 case DRM_FORMAT_XBGR2101010:
c16ed4be 14213 if (INTEL_INFO(dev)->gen < 4) {
4ee62c76
VS
14214 DRM_DEBUG("unsupported pixel format: %s\n",
14215 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14216 return -EINVAL;
c16ed4be 14217 }
b5626747 14218 break;
7531208b
DL
14219 case DRM_FORMAT_ABGR2101010:
14220 if (!IS_VALLEYVIEW(dev)) {
14221 DRM_DEBUG("unsupported pixel format: %s\n",
14222 drm_get_format_name(mode_cmd->pixel_format));
14223 return -EINVAL;
14224 }
14225 break;
04b3924d
VS
14226 case DRM_FORMAT_YUYV:
14227 case DRM_FORMAT_UYVY:
14228 case DRM_FORMAT_YVYU:
14229 case DRM_FORMAT_VYUY:
c16ed4be 14230 if (INTEL_INFO(dev)->gen < 5) {
4ee62c76
VS
14231 DRM_DEBUG("unsupported pixel format: %s\n",
14232 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14233 return -EINVAL;
c16ed4be 14234 }
57cd6508
CW
14235 break;
14236 default:
4ee62c76
VS
14237 DRM_DEBUG("unsupported pixel format: %s\n",
14238 drm_get_format_name(mode_cmd->pixel_format));
57cd6508
CW
14239 return -EINVAL;
14240 }
14241
90f9a336
VS
14242 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14243 if (mode_cmd->offsets[0] != 0)
14244 return -EINVAL;
14245
ec2c981e 14246 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
091df6cb
DV
14247 mode_cmd->pixel_format,
14248 mode_cmd->modifier[0]);
53155c0a
DV
14249 /* FIXME drm helper for size checks (especially planar formats)? */
14250 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14251 return -EINVAL;
14252
c7d73f6a
DV
14253 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14254 intel_fb->obj = obj;
80075d49 14255 intel_fb->obj->framebuffer_references++;
c7d73f6a 14256
79e53945
JB
14257 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14258 if (ret) {
14259 DRM_ERROR("framebuffer init failed %d\n", ret);
14260 return ret;
14261 }
14262
79e53945
JB
14263 return 0;
14264}
14265
79e53945
JB
14266static struct drm_framebuffer *
14267intel_user_framebuffer_create(struct drm_device *dev,
14268 struct drm_file *filp,
308e5bcb 14269 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 14270{
05394f39 14271 struct drm_i915_gem_object *obj;
79e53945 14272
308e5bcb
JB
14273 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14274 mode_cmd->handles[0]));
c8725226 14275 if (&obj->base == NULL)
cce13ff7 14276 return ERR_PTR(-ENOENT);
79e53945 14277
d2dff872 14278 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB
14279}
14280
4520f53a 14281#ifndef CONFIG_DRM_I915_FBDEV
0632fef6 14282static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
4520f53a
DV
14283{
14284}
14285#endif
14286
79e53945 14287static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 14288 .fb_create = intel_user_framebuffer_create,
0632fef6 14289 .output_poll_changed = intel_fbdev_output_poll_changed,
5ee67f1c
MR
14290 .atomic_check = intel_atomic_check,
14291 .atomic_commit = intel_atomic_commit,
79e53945
JB
14292};
14293
e70236a8
JB
14294/* Set up chip specific display functions */
14295static void intel_init_display(struct drm_device *dev)
14296{
14297 struct drm_i915_private *dev_priv = dev->dev_private;
14298
ee9300bb
DV
14299 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14300 dev_priv->display.find_dpll = g4x_find_best_dpll;
ef9348c8
CML
14301 else if (IS_CHERRYVIEW(dev))
14302 dev_priv->display.find_dpll = chv_find_best_dpll;
ee9300bb
DV
14303 else if (IS_VALLEYVIEW(dev))
14304 dev_priv->display.find_dpll = vlv_find_best_dpll;
14305 else if (IS_PINEVIEW(dev))
14306 dev_priv->display.find_dpll = pnv_find_best_dpll;
14307 else
14308 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14309
bc8d7dff
DL
14310 if (INTEL_INFO(dev)->gen >= 9) {
14311 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
5724dbd1
DL
14312 dev_priv->display.get_initial_plane_config =
14313 skylake_get_initial_plane_config;
bc8d7dff
DL
14314 dev_priv->display.crtc_compute_clock =
14315 haswell_crtc_compute_clock;
14316 dev_priv->display.crtc_enable = haswell_crtc_enable;
14317 dev_priv->display.crtc_disable = haswell_crtc_disable;
14318 dev_priv->display.off = ironlake_crtc_off;
14319 dev_priv->display.update_primary_plane =
14320 skylake_update_primary_plane;
14321 } else if (HAS_DDI(dev)) {
0e8ffe1b 14322 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
5724dbd1
DL
14323 dev_priv->display.get_initial_plane_config =
14324 ironlake_get_initial_plane_config;
797d0259
ACO
14325 dev_priv->display.crtc_compute_clock =
14326 haswell_crtc_compute_clock;
4f771f10
PZ
14327 dev_priv->display.crtc_enable = haswell_crtc_enable;
14328 dev_priv->display.crtc_disable = haswell_crtc_disable;
df8ad70c 14329 dev_priv->display.off = ironlake_crtc_off;
bc8d7dff
DL
14330 dev_priv->display.update_primary_plane =
14331 ironlake_update_primary_plane;
09b4ddf9 14332 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 14333 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
5724dbd1
DL
14334 dev_priv->display.get_initial_plane_config =
14335 ironlake_get_initial_plane_config;
3fb37703
ACO
14336 dev_priv->display.crtc_compute_clock =
14337 ironlake_crtc_compute_clock;
76e5a89c
DV
14338 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14339 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 14340 dev_priv->display.off = ironlake_crtc_off;
262ca2b0
MR
14341 dev_priv->display.update_primary_plane =
14342 ironlake_update_primary_plane;
89b667f8
JB
14343 } else if (IS_VALLEYVIEW(dev)) {
14344 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
5724dbd1
DL
14345 dev_priv->display.get_initial_plane_config =
14346 i9xx_get_initial_plane_config;
d6dfee7a 14347 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
89b667f8
JB
14348 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14349 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14350 dev_priv->display.off = i9xx_crtc_off;
262ca2b0
MR
14351 dev_priv->display.update_primary_plane =
14352 i9xx_update_primary_plane;
f564048e 14353 } else {
0e8ffe1b 14354 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
5724dbd1
DL
14355 dev_priv->display.get_initial_plane_config =
14356 i9xx_get_initial_plane_config;
d6dfee7a 14357 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
76e5a89c
DV
14358 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14359 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 14360 dev_priv->display.off = i9xx_crtc_off;
262ca2b0
MR
14361 dev_priv->display.update_primary_plane =
14362 i9xx_update_primary_plane;
f564048e 14363 }
e70236a8 14364
e70236a8 14365 /* Returns the core display clock speed */
1652d19e
VS
14366 if (IS_SKYLAKE(dev))
14367 dev_priv->display.get_display_clock_speed =
14368 skylake_get_display_clock_speed;
14369 else if (IS_BROADWELL(dev))
14370 dev_priv->display.get_display_clock_speed =
14371 broadwell_get_display_clock_speed;
14372 else if (IS_HASWELL(dev))
14373 dev_priv->display.get_display_clock_speed =
14374 haswell_get_display_clock_speed;
14375 else if (IS_VALLEYVIEW(dev))
25eb05fc
JB
14376 dev_priv->display.get_display_clock_speed =
14377 valleyview_get_display_clock_speed;
b37a6434
VS
14378 else if (IS_GEN5(dev))
14379 dev_priv->display.get_display_clock_speed =
14380 ilk_get_display_clock_speed;
a7c66cd8
VS
14381 else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
14382 IS_GEN6(dev) || IS_IVYBRIDGE(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB
14383 dev_priv->display.get_display_clock_speed =
14384 i945_get_display_clock_speed;
14385 else if (IS_I915G(dev))
14386 dev_priv->display.get_display_clock_speed =
14387 i915_get_display_clock_speed;
257a7ffc 14388 else if (IS_I945GM(dev) || IS_845G(dev))
e70236a8
JB
14389 dev_priv->display.get_display_clock_speed =
14390 i9xx_misc_get_display_clock_speed;
257a7ffc
DV
14391 else if (IS_PINEVIEW(dev))
14392 dev_priv->display.get_display_clock_speed =
14393 pnv_get_display_clock_speed;
e70236a8
JB
14394 else if (IS_I915GM(dev))
14395 dev_priv->display.get_display_clock_speed =
14396 i915gm_get_display_clock_speed;
14397 else if (IS_I865G(dev))
14398 dev_priv->display.get_display_clock_speed =
14399 i865_get_display_clock_speed;
f0f8a9ce 14400 else if (IS_I85X(dev))
e70236a8
JB
14401 dev_priv->display.get_display_clock_speed =
14402 i855_get_display_clock_speed;
14403 else /* 852, 830 */
14404 dev_priv->display.get_display_clock_speed =
14405 i830_get_display_clock_speed;
14406
7c10a2b5 14407 if (IS_GEN5(dev)) {
3bb11b53 14408 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
3bb11b53
SJ
14409 } else if (IS_GEN6(dev)) {
14410 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
3bb11b53
SJ
14411 } else if (IS_IVYBRIDGE(dev)) {
14412 /* FIXME: detect B0+ stepping and use auto training */
14413 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
059b2fe9 14414 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
3bb11b53 14415 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
30a970c6
JB
14416 } else if (IS_VALLEYVIEW(dev)) {
14417 dev_priv->display.modeset_global_resources =
14418 valleyview_modeset_global_resources;
f8437dd1
VK
14419 } else if (IS_BROXTON(dev)) {
14420 dev_priv->display.modeset_global_resources =
14421 broxton_modeset_global_resources;
e70236a8 14422 }
8c9f3aaf 14423
8c9f3aaf
JB
14424 switch (INTEL_INFO(dev)->gen) {
14425 case 2:
14426 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14427 break;
14428
14429 case 3:
14430 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14431 break;
14432
14433 case 4:
14434 case 5:
14435 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14436 break;
14437
14438 case 6:
14439 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14440 break;
7c9017e5 14441 case 7:
4e0bbc31 14442 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
7c9017e5
JB
14443 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14444 break;
830c81db 14445 case 9:
ba343e02
TU
14446 /* Drop through - unsupported since execlist only. */
14447 default:
14448 /* Default just returns -ENODEV to indicate unsupported */
14449 dev_priv->display.queue_flip = intel_default_queue_flip;
8c9f3aaf 14450 }
7bd688cd
JN
14451
14452 intel_panel_init_backlight_funcs(dev);
e39b999a
VS
14453
14454 mutex_init(&dev_priv->pps_mutex);
e70236a8
JB
14455}
14456
b690e96c
JB
14457/*
14458 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14459 * resume, or other times. This quirk makes sure that's the case for
14460 * affected systems.
14461 */
0206e353 14462static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB
14463{
14464 struct drm_i915_private *dev_priv = dev->dev_private;
14465
14466 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 14467 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB
14468}
14469
b6b5d049
VS
14470static void quirk_pipeb_force(struct drm_device *dev)
14471{
14472 struct drm_i915_private *dev_priv = dev->dev_private;
14473
14474 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14475 DRM_INFO("applying pipe b force quirk\n");
14476}
14477
435793df
KP
14478/*
14479 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14480 */
14481static void quirk_ssc_force_disable(struct drm_device *dev)
14482{
14483 struct drm_i915_private *dev_priv = dev->dev_private;
14484 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 14485 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP
14486}
14487
4dca20ef 14488/*
5a15ab5b
CE
14489 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14490 * brightness value
4dca20ef
CE
14491 */
14492static void quirk_invert_brightness(struct drm_device *dev)
14493{
14494 struct drm_i915_private *dev_priv = dev->dev_private;
14495 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 14496 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP
14497}
14498
9c72cc6f
SD
14499/* Some VBT's incorrectly indicate no backlight is present */
14500static void quirk_backlight_present(struct drm_device *dev)
14501{
14502 struct drm_i915_private *dev_priv = dev->dev_private;
14503 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14504 DRM_INFO("applying backlight present quirk\n");
14505}
14506
b690e96c
JB
14507struct intel_quirk {
14508 int device;
14509 int subsystem_vendor;
14510 int subsystem_device;
14511 void (*hook)(struct drm_device *dev);
14512};
14513
5f85f176
EE
14514/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14515struct intel_dmi_quirk {
14516 void (*hook)(struct drm_device *dev);
14517 const struct dmi_system_id (*dmi_id_list)[];
14518};
14519
14520static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14521{
14522 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14523 return 1;
14524}
14525
14526static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14527 {
14528 .dmi_id_list = &(const struct dmi_system_id[]) {
14529 {
14530 .callback = intel_dmi_reverse_brightness,
14531 .ident = "NCR Corporation",
14532 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14533 DMI_MATCH(DMI_PRODUCT_NAME, ""),
14534 },
14535 },
14536 { } /* terminating entry */
14537 },
14538 .hook = quirk_invert_brightness,
14539 },
14540};
14541
c43b5634 14542static struct intel_quirk intel_quirks[] = {
b690e96c
JB
14543 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14544 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14545
b690e96c
JB
14546 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14547 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14548
5f080c0f
VS
14549 /* 830 needs to leave pipe A & dpll A up */
14550 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14551
b6b5d049
VS
14552 /* 830 needs to leave pipe B & dpll B up */
14553 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14554
435793df
KP
14555 /* Lenovo U160 cannot use SSC on LVDS */
14556 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS
14557
14558 /* Sony Vaio Y cannot use SSC on LVDS */
14559 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b 14560
be505f64
AH
14561 /* Acer Aspire 5734Z must invert backlight brightness */
14562 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14563
14564 /* Acer/eMachines G725 */
14565 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14566
14567 /* Acer/eMachines e725 */
14568 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14569
14570 /* Acer/Packard Bell NCL20 */
14571 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14572
14573 /* Acer Aspire 4736Z */
14574 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
0f540c3a
JN
14575
14576 /* Acer Aspire 5336 */
14577 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
2e93a1aa
SD
14578
14579 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14580 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
d4967d8c 14581
dfb3d47b
SD
14582 /* Acer C720 Chromebook (Core i3 4005U) */
14583 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14584
b2a9601c 14585 /* Apple Macbook 2,1 (Core 2 T7400) */
14586 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14587
d4967d8c
SD
14588 /* Toshiba CB35 Chromebook (Celeron 2955U) */
14589 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
724cb06f
SD
14590
14591 /* HP Chromebook 14 (Celeron 2955U) */
14592 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
cf6f0af9
JN
14593
14594 /* Dell Chromebook 11 */
14595 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
b690e96c
JB
14596};
14597
14598static void intel_init_quirks(struct drm_device *dev)
14599{
14600 struct pci_dev *d = dev->pdev;
14601 int i;
14602
14603 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14604 struct intel_quirk *q = &intel_quirks[i];
14605
14606 if (d->device == q->device &&
14607 (d->subsystem_vendor == q->subsystem_vendor ||
14608 q->subsystem_vendor == PCI_ANY_ID) &&
14609 (d->subsystem_device == q->subsystem_device ||
14610 q->subsystem_device == PCI_ANY_ID))
14611 q->hook(dev);
14612 }
5f85f176
EE
14613 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14614 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14615 intel_dmi_quirks[i].hook(dev);
14616 }
b690e96c
JB
14617}
14618
9cce37f4
JB
14619/* Disable the VGA plane that we never use */
14620static void i915_disable_vga(struct drm_device *dev)
14621{
14622 struct drm_i915_private *dev_priv = dev->dev_private;
14623 u8 sr1;
766aa1c4 14624 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4 14625
2b37c616 14626 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
9cce37f4 14627 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 14628 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB
14629 sr1 = inb(VGA_SR_DATA);
14630 outb(sr1 | 1<<5, VGA_SR_DATA);
14631 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
14632 udelay(300);
14633
01f5a626 14634 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9cce37f4
JB
14635 POSTING_READ(vga_reg);
14636}
14637
f817586c
DV
14638void intel_modeset_init_hw(struct drm_device *dev)
14639{
a8f78b58
ED
14640 intel_prepare_ddi(dev);
14641
f8bf63fd
VS
14642 if (IS_VALLEYVIEW(dev))
14643 vlv_update_cdclk(dev);
14644
f817586c
DV
14645 intel_init_clock_gating(dev);
14646
8090c6b9 14647 intel_enable_gt_powersave(dev);
f817586c
DV
14648}
14649
79e53945
JB
14650void intel_modeset_init(struct drm_device *dev)
14651{
652c393a 14652 struct drm_i915_private *dev_priv = dev->dev_private;
1fe47785 14653 int sprite, ret;
8cc87b75 14654 enum pipe pipe;
46f297fb 14655 struct intel_crtc *crtc;
79e53945
JB
14656
14657 drm_mode_config_init(dev);
14658
14659 dev->mode_config.min_width = 0;
14660 dev->mode_config.min_height = 0;
14661
019d96cb
DA
14662 dev->mode_config.preferred_depth = 24;
14663 dev->mode_config.prefer_shadow = 1;
14664
25bab385
TU
14665 dev->mode_config.allow_fb_modifiers = true;
14666
e6ecefaa 14667 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 14668
b690e96c
JB
14669 intel_init_quirks(dev);
14670
1fa61106
ED
14671 intel_init_pm(dev);
14672
e3c74757
BW
14673 if (INTEL_INFO(dev)->num_pipes == 0)
14674 return;
14675
e70236a8 14676 intel_init_display(dev);
7c10a2b5 14677 intel_init_audio(dev);
e70236a8 14678
a6c45cf0
CW
14679 if (IS_GEN2(dev)) {
14680 dev->mode_config.max_width = 2048;
14681 dev->mode_config.max_height = 2048;
14682 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP
14683 dev->mode_config.max_width = 4096;
14684 dev->mode_config.max_height = 4096;
79e53945 14685 } else {
a6c45cf0
CW
14686 dev->mode_config.max_width = 8192;
14687 dev->mode_config.max_height = 8192;
79e53945 14688 }
068be561 14689
dc41c154
VS
14690 if (IS_845G(dev) || IS_I865G(dev)) {
14691 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
14692 dev->mode_config.cursor_height = 1023;
14693 } else if (IS_GEN2(dev)) {
068be561
DL
14694 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
14695 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
14696 } else {
14697 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
14698 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
14699 }
14700
5d4545ae 14701 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 14702
28c97730 14703 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW
14704 INTEL_INFO(dev)->num_pipes,
14705 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 14706
055e393f 14707 for_each_pipe(dev_priv, pipe) {
8cc87b75 14708 intel_crtc_init(dev, pipe);
3bdcfc0c 14709 for_each_sprite(dev_priv, pipe, sprite) {
1fe47785 14710 ret = intel_plane_init(dev, pipe, sprite);
7f1f3851 14711 if (ret)
06da8da2 14712 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
1fe47785 14713 pipe_name(pipe), sprite_name(pipe, sprite), ret);
7f1f3851 14714 }
79e53945
JB
14715 }
14716
f42bb70d
JB
14717 intel_init_dpio(dev);
14718
e72f9fbf 14719 intel_shared_dpll_init(dev);
ee7b9f93 14720
9cce37f4
JB
14721 /* Just disable it once at startup */
14722 i915_disable_vga(dev);
79e53945 14723 intel_setup_outputs(dev);
11be49eb
CW
14724
14725 /* Just in case the BIOS is doing something questionable. */
7ff0ebcc 14726 intel_fbc_disable(dev);
fa9fa083 14727
6e9f798d 14728 drm_modeset_lock_all(dev);
fa9fa083 14729 intel_modeset_setup_hw_state(dev, false);
6e9f798d 14730 drm_modeset_unlock_all(dev);
46f297fb 14731
d3fcc808 14732 for_each_intel_crtc(dev, crtc) {
46f297fb
JB
14733 if (!crtc->active)
14734 continue;
14735
46f297fb 14736 /*
46f297fb
JB
14737 * Note that reserving the BIOS fb up front prevents us
14738 * from stuffing other stolen allocations like the ring
14739 * on top. This prevents some ugliness at boot time, and
14740 * can even allow for smooth boot transitions if the BIOS
14741 * fb is large enough for the active pipe configuration.
14742 */
5724dbd1
DL
14743 if (dev_priv->display.get_initial_plane_config) {
14744 dev_priv->display.get_initial_plane_config(crtc,
46f297fb
JB
14745 &crtc->plane_config);
14746 /*
14747 * If the fb is shared between multiple heads, we'll
14748 * just get the first one.
14749 */
f6936e29 14750 intel_find_initial_plane_obj(crtc, &crtc->plane_config);
46f297fb 14751 }
46f297fb 14752 }
2c7111db
CW
14753}
14754
7fad798e
DV
14755static void intel_enable_pipe_a(struct drm_device *dev)
14756{
14757 struct intel_connector *connector;
14758 struct drm_connector *crt = NULL;
14759 struct intel_load_detect_pipe load_detect_temp;
208bf9fd 14760 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
7fad798e
DV
14761
14762 /* We can't just switch on the pipe A, we need to set things up with a
14763 * proper mode and output configuration. As a gross hack, enable pipe A
14764 * by enabling the load detect pipe once. */
3a3371ff 14765 for_each_intel_connector(dev, connector) {
7fad798e
DV
14766 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
14767 crt = &connector->base;
14768 break;
14769 }
14770 }
14771
14772 if (!crt)
14773 return;
14774
208bf9fd 14775 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
49172fee 14776 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
7fad798e
DV
14777}
14778
fa555837
DV
14779static bool
14780intel_check_plane_mapping(struct intel_crtc *crtc)
14781{
7eb552ae
BW
14782 struct drm_device *dev = crtc->base.dev;
14783 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV
14784 u32 reg, val;
14785
7eb552ae 14786 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV
14787 return true;
14788
14789 reg = DSPCNTR(!crtc->plane);
14790 val = I915_READ(reg);
14791
14792 if ((val & DISPLAY_PLANE_ENABLE) &&
14793 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
14794 return false;
14795
14796 return true;
14797}
14798
24929352
DV
14799static void intel_sanitize_crtc(struct intel_crtc *crtc)
14800{
14801 struct drm_device *dev = crtc->base.dev;
14802 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 14803 u32 reg;
24929352 14804
24929352 14805 /* Clear any frame start delays used for debugging left by the BIOS */
6e3c9717 14806 reg = PIPECONF(crtc->config->cpu_transcoder);
24929352
DV
14807 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
14808
d3eaf884 14809 /* restore vblank interrupts to correct state */
9625604c 14810 drm_crtc_vblank_reset(&crtc->base);
d297e103
VS
14811 if (crtc->active) {
14812 update_scanline_offset(crtc);
9625604c
DV
14813 drm_crtc_vblank_on(&crtc->base);
14814 }
d3eaf884 14815
24929352 14816 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV
14817 * disable the crtc (and hence change the state) if it is wrong. Note
14818 * that gen4+ has a fixed plane -> pipe mapping. */
14819 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV
14820 struct intel_connector *connector;
14821 bool plane;
14822
24929352
DV
14823 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
14824 crtc->base.base.id);
14825
14826 /* Pipe has the wrong plane attached and the plane is active.
14827 * Temporarily change the plane mapping and disable everything
14828 * ... */
14829 plane = crtc->plane;
b70709a6 14830 to_intel_plane_state(crtc->base.primary->state)->visible = true;
24929352 14831 crtc->plane = !plane;
ce22dba9 14832 intel_crtc_disable_planes(&crtc->base);
24929352
DV
14833 dev_priv->display.crtc_disable(&crtc->base);
14834 crtc->plane = plane;
14835
14836 /* ... and break all links. */
3a3371ff 14837 for_each_intel_connector(dev, connector) {
24929352
DV
14838 if (connector->encoder->base.crtc != &crtc->base)
14839 continue;
14840
7f1950fb
EE
14841 connector->base.dpms = DRM_MODE_DPMS_OFF;
14842 connector->base.encoder = NULL;
24929352 14843 }
7f1950fb
EE
14844 /* multiple connectors may have the same encoder:
14845 * handle them and break crtc link separately */
3a3371ff 14846 for_each_intel_connector(dev, connector)
7f1950fb
EE
14847 if (connector->encoder->base.crtc == &crtc->base) {
14848 connector->encoder->base.crtc = NULL;
14849 connector->encoder->connectors_active = false;
14850 }
24929352
DV
14851
14852 WARN_ON(crtc->active);
83d65738 14853 crtc->base.state->enable = false;
49d6fa21 14854 crtc->base.state->active = false;
24929352
DV
14855 crtc->base.enabled = false;
14856 }
24929352 14857
7fad798e
DV
14858 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
14859 crtc->pipe == PIPE_A && !crtc->active) {
14860 /* BIOS forgot to enable pipe A, this mostly happens after
14861 * resume. Force-enable the pipe to fix this, the update_dpms
14862 * call below we restore the pipe to the right state, but leave
14863 * the required bits on. */
14864 intel_enable_pipe_a(dev);
14865 }
14866
24929352
DV
14867 /* Adjust the state of the output pipe according to whether we
14868 * have active connectors/encoders. */
14869 intel_crtc_update_dpms(&crtc->base);
14870
83d65738 14871 if (crtc->active != crtc->base.state->enable) {
24929352
DV
14872 struct intel_encoder *encoder;
14873
14874 /* This can happen either due to bugs in the get_hw_state
14875 * functions or because the pipe is force-enabled due to the
14876 * pipe A quirk. */
14877 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
14878 crtc->base.base.id,
83d65738 14879 crtc->base.state->enable ? "enabled" : "disabled",
24929352
DV
14880 crtc->active ? "enabled" : "disabled");
14881
83d65738 14882 crtc->base.state->enable = crtc->active;
49d6fa21 14883 crtc->base.state->active = crtc->active;
24929352
DV
14884 crtc->base.enabled = crtc->active;
14885
14886 /* Because we only establish the connector -> encoder ->
14887 * crtc links if something is active, this means the
14888 * crtc is now deactivated. Break the links. connector
14889 * -> encoder links are only establish when things are
14890 * actually up, hence no need to break them. */
14891 WARN_ON(crtc->active);
14892
14893 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
14894 WARN_ON(encoder->connectors_active);
14895 encoder->base.crtc = NULL;
14896 }
14897 }
c5ab3bc0 14898
a3ed6aad 14899 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
4cc31489
DV
14900 /*
14901 * We start out with underrun reporting disabled to avoid races.
14902 * For correct bookkeeping mark this on active crtcs.
14903 *
c5ab3bc0
DV
14904 * Also on gmch platforms we dont have any hardware bits to
14905 * disable the underrun reporting. Which means we need to start
14906 * out with underrun reporting disabled also on inactive pipes,
14907 * since otherwise we'll complain about the garbage we read when
14908 * e.g. coming up after runtime pm.
14909 *
4cc31489
DV
14910 * No protection against concurrent access is required - at
14911 * worst a fifo underrun happens which also sets this to false.
14912 */
14913 crtc->cpu_fifo_underrun_disabled = true;
14914 crtc->pch_fifo_underrun_disabled = true;
14915 }
24929352
DV
14916}
14917
14918static void intel_sanitize_encoder(struct intel_encoder *encoder)
14919{
14920 struct intel_connector *connector;
14921 struct drm_device *dev = encoder->base.dev;
14922
14923 /* We need to check both for a crtc link (meaning that the
14924 * encoder is active and trying to read from a pipe) and the
14925 * pipe itself being active. */
14926 bool has_active_crtc = encoder->base.crtc &&
14927 to_intel_crtc(encoder->base.crtc)->active;
14928
14929 if (encoder->connectors_active && !has_active_crtc) {
14930 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
14931 encoder->base.base.id,
8e329a03 14932 encoder->base.name);
24929352
DV
14933
14934 /* Connector is active, but has no active pipe. This is
14935 * fallout from our resume register restoring. Disable
14936 * the encoder manually again. */
14937 if (encoder->base.crtc) {
14938 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
14939 encoder->base.base.id,
8e329a03 14940 encoder->base.name);
24929352 14941 encoder->disable(encoder);
a62d1497
VS
14942 if (encoder->post_disable)
14943 encoder->post_disable(encoder);
24929352 14944 }
7f1950fb
EE
14945 encoder->base.crtc = NULL;
14946 encoder->connectors_active = false;
24929352
DV
14947
14948 /* Inconsistent output/port/pipe state happens presumably due to
14949 * a bug in one of the get_hw_state functions. Or someplace else
14950 * in our code, like the register restore mess on resume. Clamp
14951 * things to off as a safer default. */
3a3371ff 14952 for_each_intel_connector(dev, connector) {
24929352
DV
14953 if (connector->encoder != encoder)
14954 continue;
7f1950fb
EE
14955 connector->base.dpms = DRM_MODE_DPMS_OFF;
14956 connector->base.encoder = NULL;
24929352
DV
14957 }
14958 }
14959 /* Enabled encoders without active connectors will be fixed in
14960 * the crtc fixup. */
14961}
14962
04098753 14963void i915_redisable_vga_power_on(struct drm_device *dev)
0fde901f
KM
14964{
14965 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 14966 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f 14967
04098753
ID
14968 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
14969 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
14970 i915_disable_vga(dev);
14971 }
14972}
14973
14974void i915_redisable_vga(struct drm_device *dev)
14975{
14976 struct drm_i915_private *dev_priv = dev->dev_private;
14977
8dc8a27c
PZ
14978 /* This function can be called both from intel_modeset_setup_hw_state or
14979 * at a very early point in our resume sequence, where the power well
14980 * structures are not yet restored. Since this function is at a very
14981 * paranoid "someone might have enabled VGA while we were not looking"
14982 * level, just check if the power well is enabled instead of trying to
14983 * follow the "don't touch the power well if we don't need it" policy
14984 * the rest of the driver uses. */
f458ebbc 14985 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
8dc8a27c
PZ
14986 return;
14987
04098753 14988 i915_redisable_vga_power_on(dev);
0fde901f
KM
14989}
14990
98ec7739
VS
14991static bool primary_get_hw_state(struct intel_crtc *crtc)
14992{
14993 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
14994
14995 if (!crtc->active)
14996 return false;
14997
14998 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
14999}
15000
30e984df 15001static void intel_modeset_readout_hw_state(struct drm_device *dev)
24929352
DV
15002{
15003 struct drm_i915_private *dev_priv = dev->dev_private;
15004 enum pipe pipe;
24929352
DV
15005 struct intel_crtc *crtc;
15006 struct intel_encoder *encoder;
15007 struct intel_connector *connector;
5358901f 15008 int i;
24929352 15009
d3fcc808 15010 for_each_intel_crtc(dev, crtc) {
b70709a6
ML
15011 struct drm_plane *primary = crtc->base.primary;
15012 struct intel_plane_state *plane_state;
15013
6e3c9717 15014 memset(crtc->config, 0, sizeof(*crtc->config));
3b117c8f 15015
6e3c9717 15016 crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
9953599b 15017
0e8ffe1b 15018 crtc->active = dev_priv->display.get_pipe_config(crtc,
6e3c9717 15019 crtc->config);
24929352 15020
83d65738 15021 crtc->base.state->enable = crtc->active;
49d6fa21 15022 crtc->base.state->active = crtc->active;
24929352 15023 crtc->base.enabled = crtc->active;
b70709a6
ML
15024
15025 plane_state = to_intel_plane_state(primary->state);
15026 plane_state->visible = primary_get_hw_state(crtc);
24929352
DV
15027
15028 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15029 crtc->base.base.id,
15030 crtc->active ? "enabled" : "disabled");
15031 }
15032
5358901f
DV
15033 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15034 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15035
3e369b76
ACO
15036 pll->on = pll->get_hw_state(dev_priv, pll,
15037 &pll->config.hw_state);
5358901f 15038 pll->active = 0;
3e369b76 15039 pll->config.crtc_mask = 0;
d3fcc808 15040 for_each_intel_crtc(dev, crtc) {
1e6f2ddc 15041 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
5358901f 15042 pll->active++;
3e369b76 15043 pll->config.crtc_mask |= 1 << crtc->pipe;
1e6f2ddc 15044 }
5358901f 15045 }
5358901f 15046
1e6f2ddc 15047 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
3e369b76 15048 pll->name, pll->config.crtc_mask, pll->on);
bd2bb1b9 15049
3e369b76 15050 if (pll->config.crtc_mask)
bd2bb1b9 15051 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5358901f
DV
15052 }
15053
b2784e15 15054 for_each_intel_encoder(dev, encoder) {
24929352
DV
15055 pipe = 0;
15056
15057 if (encoder->get_hw_state(encoder, &pipe)) {
045ac3b5
JB
15058 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15059 encoder->base.crtc = &crtc->base;
6e3c9717 15060 encoder->get_config(encoder, crtc->config);
24929352
DV
15061 } else {
15062 encoder->base.crtc = NULL;
15063 }
15064
15065 encoder->connectors_active = false;
6f2bcceb 15066 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
24929352 15067 encoder->base.base.id,
8e329a03 15068 encoder->base.name,
24929352 15069 encoder->base.crtc ? "enabled" : "disabled",
6f2bcceb 15070 pipe_name(pipe));
24929352
DV
15071 }
15072
3a3371ff 15073 for_each_intel_connector(dev, connector) {
24929352
DV
15074 if (connector->get_hw_state(connector)) {
15075 connector->base.dpms = DRM_MODE_DPMS_ON;
15076 connector->encoder->connectors_active = true;
15077 connector->base.encoder = &connector->encoder->base;
15078 } else {
15079 connector->base.dpms = DRM_MODE_DPMS_OFF;
15080 connector->base.encoder = NULL;
15081 }
15082 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15083 connector->base.base.id,
c23cc417 15084 connector->base.name,
24929352
DV
15085 connector->base.encoder ? "enabled" : "disabled");
15086 }
30e984df
DV
15087}
15088
15089/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
15090 * and i915 state tracking structures. */
15091void intel_modeset_setup_hw_state(struct drm_device *dev,
15092 bool force_restore)
15093{
15094 struct drm_i915_private *dev_priv = dev->dev_private;
15095 enum pipe pipe;
30e984df
DV
15096 struct intel_crtc *crtc;
15097 struct intel_encoder *encoder;
35c95375 15098 int i;
30e984df
DV
15099
15100 intel_modeset_readout_hw_state(dev);
24929352 15101
babea61d
JB
15102 /*
15103 * Now that we have the config, copy it to each CRTC struct
15104 * Note that this could go away if we move to using crtc_config
15105 * checking everywhere.
15106 */
d3fcc808 15107 for_each_intel_crtc(dev, crtc) {
d330a953 15108 if (crtc->active && i915.fastboot) {
6e3c9717
ACO
15109 intel_mode_from_pipe_config(&crtc->base.mode,
15110 crtc->config);
babea61d
JB
15111 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
15112 crtc->base.base.id);
15113 drm_mode_debug_printmodeline(&crtc->base.mode);
15114 }
15115 }
15116
24929352 15117 /* HW state is read out, now we need to sanitize this mess. */
b2784e15 15118 for_each_intel_encoder(dev, encoder) {
24929352
DV
15119 intel_sanitize_encoder(encoder);
15120 }
15121
055e393f 15122 for_each_pipe(dev_priv, pipe) {
24929352
DV
15123 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15124 intel_sanitize_crtc(crtc);
6e3c9717
ACO
15125 intel_dump_pipe_config(crtc, crtc->config,
15126 "[setup_hw_state]");
24929352 15127 }
9a935856 15128
d29b2f9d
ACO
15129 intel_modeset_update_connector_atomic_state(dev);
15130
35c95375
DV
15131 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15132 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15133
15134 if (!pll->on || pll->active)
15135 continue;
15136
15137 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15138
15139 pll->disable(dev_priv, pll);
15140 pll->on = false;
15141 }
15142
3078999f
PB
15143 if (IS_GEN9(dev))
15144 skl_wm_get_hw_state(dev);
15145 else if (HAS_PCH_SPLIT(dev))
243e6a44
VS
15146 ilk_wm_get_hw_state(dev);
15147
45e2b5f6 15148 if (force_restore) {
7d0bc1ea
VS
15149 i915_redisable_vga(dev);
15150
f30da187
DV
15151 /*
15152 * We need to use raw interfaces for restoring state to avoid
15153 * checking (bogus) intermediate states.
15154 */
055e393f 15155 for_each_pipe(dev_priv, pipe) {
b5644d05
JB
15156 struct drm_crtc *crtc =
15157 dev_priv->pipe_to_crtc_mapping[pipe];
f30da187 15158
83a57153 15159 intel_crtc_restore_mode(crtc);
45e2b5f6
DV
15160 }
15161 } else {
15162 intel_modeset_update_staged_output_state(dev);
15163 }
8af6cf88
DV
15164
15165 intel_modeset_check_state(dev);
2c7111db
CW
15166}
15167
15168void intel_modeset_gem_init(struct drm_device *dev)
15169{
92122789 15170 struct drm_i915_private *dev_priv = dev->dev_private;
484b41dd 15171 struct drm_crtc *c;
2ff8fde1 15172 struct drm_i915_gem_object *obj;
e0d6149b 15173 int ret;
484b41dd 15174
ae48434c
ID
15175 mutex_lock(&dev->struct_mutex);
15176 intel_init_gt_powersave(dev);
15177 mutex_unlock(&dev->struct_mutex);
15178
92122789
JB
15179 /*
15180 * There may be no VBT; and if the BIOS enabled SSC we can
15181 * just keep using it to avoid unnecessary flicker. Whereas if the
15182 * BIOS isn't using it, don't assume it will work even if the VBT
15183 * indicates as much.
15184 */
15185 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
15186 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15187 DREF_SSC1_ENABLE);
15188
1833b134 15189 intel_modeset_init_hw(dev);
02e792fb
DV
15190
15191 intel_setup_overlay(dev);
484b41dd
JB
15192
15193 /*
15194 * Make sure any fbs we allocated at startup are properly
15195 * pinned & fenced. When we do the allocation it's too early
15196 * for this.
15197 */
70e1e0ec 15198 for_each_crtc(dev, c) {
2ff8fde1
MR
15199 obj = intel_fb_obj(c->primary->fb);
15200 if (obj == NULL)
484b41dd
JB
15201 continue;
15202
e0d6149b
TU
15203 mutex_lock(&dev->struct_mutex);
15204 ret = intel_pin_and_fence_fb_obj(c->primary,
15205 c->primary->fb,
15206 c->primary->state,
15207 NULL);
15208 mutex_unlock(&dev->struct_mutex);
15209 if (ret) {
484b41dd
JB
15210 DRM_ERROR("failed to pin boot fb on pipe %d\n",
15211 to_intel_crtc(c)->pipe);
66e514c1
DA
15212 drm_framebuffer_unreference(c->primary->fb);
15213 c->primary->fb = NULL;
afd65eb4 15214 update_state_fb(c->primary);
484b41dd
JB
15215 }
15216 }
0962c3c9
VS
15217
15218 intel_backlight_register(dev);
79e53945
JB
15219}
15220
4932e2c3
ID
15221void intel_connector_unregister(struct intel_connector *intel_connector)
15222{
15223 struct drm_connector *connector = &intel_connector->base;
15224
15225 intel_panel_destroy_backlight(connector);
34ea3d38 15226 drm_connector_unregister(connector);
4932e2c3
ID
15227}
15228
79e53945
JB
15229void intel_modeset_cleanup(struct drm_device *dev)
15230{
652c393a 15231 struct drm_i915_private *dev_priv = dev->dev_private;
d9255d57 15232 struct drm_connector *connector;
652c393a 15233
2eb5252e
ID
15234 intel_disable_gt_powersave(dev);
15235
0962c3c9
VS
15236 intel_backlight_unregister(dev);
15237
fd0c0642
DV
15238 /*
15239 * Interrupts and polling as the first thing to avoid creating havoc.
2eb5252e 15240 * Too much stuff here (turning of connectors, ...) would
fd0c0642
DV
15241 * experience fancy races otherwise.
15242 */
2aeb7d3a 15243 intel_irq_uninstall(dev_priv);
eb21b92b 15244
fd0c0642
DV
15245 /*
15246 * Due to the hpd irq storm handling the hotplug work can re-arm the
15247 * poll handlers. Hence disable polling after hpd handling is shut down.
15248 */
f87ea761 15249 drm_kms_helper_poll_fini(dev);
fd0c0642 15250
652c393a
JB
15251 mutex_lock(&dev->struct_mutex);
15252
723bfd70
JB
15253 intel_unregister_dsm_handler();
15254
7ff0ebcc 15255 intel_fbc_disable(dev);
e70236a8 15256
69341a5e
KH
15257 mutex_unlock(&dev->struct_mutex);
15258
1630fe75
CW
15259 /* flush any delayed tasks or pending work */
15260 flush_scheduled_work();
15261
db31af1d
JN
15262 /* destroy the backlight and sysfs files before encoders/connectors */
15263 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4932e2c3
ID
15264 struct intel_connector *intel_connector;
15265
15266 intel_connector = to_intel_connector(connector);
15267 intel_connector->unregister(intel_connector);
db31af1d 15268 }
d9255d57 15269
79e53945 15270 drm_mode_config_cleanup(dev);
4d7bb011
DV
15271
15272 intel_cleanup_overlay(dev);
ae48434c
ID
15273
15274 mutex_lock(&dev->struct_mutex);
15275 intel_cleanup_gt_powersave(dev);
15276 mutex_unlock(&dev->struct_mutex);
79e53945
JB
15277}
15278
f1c79df3
ZW
15279/*
15280 * Return which encoder is currently attached for connector.
15281 */
df0e9248 15282struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 15283{
df0e9248
CW
15284 return &intel_attached_encoder(connector)->base;
15285}
f1c79df3 15286
df0e9248
CW
15287void intel_connector_attach_encoder(struct intel_connector *connector,
15288 struct intel_encoder *encoder)
15289{
15290 connector->encoder = encoder;
15291 drm_mode_connector_attach_encoder(&connector->base,
15292 &encoder->base);
79e53945 15293}
28d52043
DA
15294
15295/*
15296 * set vga decode state - true == enable VGA decode
15297 */
15298int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15299{
15300 struct drm_i915_private *dev_priv = dev->dev_private;
a885b3cc 15301 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
28d52043
DA
15302 u16 gmch_ctrl;
15303
75fa041d
CW
15304 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15305 DRM_ERROR("failed to read control word\n");
15306 return -EIO;
15307 }
15308
c0cc8a55
CW
15309 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15310 return 0;
15311
28d52043
DA
15312 if (state)
15313 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15314 else
15315 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
75fa041d
CW
15316
15317 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15318 DRM_ERROR("failed to write control word\n");
15319 return -EIO;
15320 }
15321
28d52043
DA
15322 return 0;
15323}
c4a1d9e4 15324
c4a1d9e4 15325struct intel_display_error_state {
ff57f1b0
PZ
15326
15327 u32 power_well_driver;
15328
63b66e5b
CW
15329 int num_transcoders;
15330
c4a1d9e4
CW
15331 struct intel_cursor_error_state {
15332 u32 control;
15333 u32 position;
15334 u32 base;
15335 u32 size;
52331309 15336 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW
15337
15338 struct intel_pipe_error_state {
ddf9c536 15339 bool power_domain_on;
c4a1d9e4 15340 u32 source;
f301b1e1 15341 u32 stat;
52331309 15342 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW
15343
15344 struct intel_plane_error_state {
15345 u32 control;
15346 u32 stride;
15347 u32 size;
15348 u32 pos;
15349 u32 addr;
15350 u32 surface;
15351 u32 tile_offset;
52331309 15352 } plane[I915_MAX_PIPES];
63b66e5b
CW
15353
15354 struct intel_transcoder_error_state {
ddf9c536 15355 bool power_domain_on;
63b66e5b
CW
15356 enum transcoder cpu_transcoder;
15357
15358 u32 conf;
15359
15360 u32 htotal;
15361 u32 hblank;
15362 u32 hsync;
15363 u32 vtotal;
15364 u32 vblank;
15365 u32 vsync;
15366 } transcoder[4];
c4a1d9e4
CW
15367};
15368
15369struct intel_display_error_state *
15370intel_display_capture_error_state(struct drm_device *dev)
15371{
fbee40df 15372 struct drm_i915_private *dev_priv = dev->dev_private;
c4a1d9e4 15373 struct intel_display_error_state *error;
63b66e5b
CW
15374 int transcoders[] = {
15375 TRANSCODER_A,
15376 TRANSCODER_B,
15377 TRANSCODER_C,
15378 TRANSCODER_EDP,
15379 };
c4a1d9e4
CW
15380 int i;
15381
63b66e5b
CW
15382 if (INTEL_INFO(dev)->num_pipes == 0)
15383 return NULL;
15384
9d1cb914 15385 error = kzalloc(sizeof(*error), GFP_ATOMIC);
c4a1d9e4
CW
15386 if (error == NULL)
15387 return NULL;
15388
190be112 15389 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ff57f1b0
PZ
15390 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15391
055e393f 15392 for_each_pipe(dev_priv, i) {
ddf9c536 15393 error->pipe[i].power_domain_on =
f458ebbc
DV
15394 __intel_display_power_is_enabled(dev_priv,
15395 POWER_DOMAIN_PIPE(i));
ddf9c536 15396 if (!error->pipe[i].power_domain_on)
9d1cb914
PZ
15397 continue;
15398
5efb3e28
VS
15399 error->cursor[i].control = I915_READ(CURCNTR(i));
15400 error->cursor[i].position = I915_READ(CURPOS(i));
15401 error->cursor[i].base = I915_READ(CURBASE(i));
c4a1d9e4
CW
15402
15403 error->plane[i].control = I915_READ(DSPCNTR(i));
15404 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 15405 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 15406 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ
15407 error->plane[i].pos = I915_READ(DSPPOS(i));
15408 }
ca291363
PZ
15409 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15410 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW
15411 if (INTEL_INFO(dev)->gen >= 4) {
15412 error->plane[i].surface = I915_READ(DSPSURF(i));
15413 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15414 }
15415
c4a1d9e4 15416 error->pipe[i].source = I915_READ(PIPESRC(i));
f301b1e1 15417
3abfce77 15418 if (HAS_GMCH_DISPLAY(dev))
f301b1e1 15419 error->pipe[i].stat = I915_READ(PIPESTAT(i));
63b66e5b
CW
15420 }
15421
15422 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
15423 if (HAS_DDI(dev_priv->dev))
15424 error->num_transcoders++; /* Account for eDP. */
15425
15426 for (i = 0; i < error->num_transcoders; i++) {
15427 enum transcoder cpu_transcoder = transcoders[i];
15428
ddf9c536 15429 error->transcoder[i].power_domain_on =
f458ebbc 15430 __intel_display_power_is_enabled(dev_priv,
38cc1daf 15431 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
ddf9c536 15432 if (!error->transcoder[i].power_domain_on)
9d1cb914
PZ
15433 continue;
15434
63b66e5b
CW
15435 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15436
15437 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15438 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15439 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15440 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15441 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15442 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15443 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW
15444 }
15445
15446 return error;
15447}
15448
edc3d884
MK
15449#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15450
c4a1d9e4 15451void
edc3d884 15452intel_display_print_error_state(struct drm_i915_error_state_buf *m,
c4a1d9e4
CW
15453 struct drm_device *dev,
15454 struct intel_display_error_state *error)
15455{
055e393f 15456 struct drm_i915_private *dev_priv = dev->dev_private;
c4a1d9e4
CW
15457 int i;
15458
63b66e5b
CW
15459 if (!error)
15460 return;
15461
edc3d884 15462 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
190be112 15463 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
edc3d884 15464 err_printf(m, "PWR_WELL_CTL2: %08x\n",
ff57f1b0 15465 error->power_well_driver);
055e393f 15466 for_each_pipe(dev_priv, i) {
edc3d884 15467 err_printf(m, "Pipe [%d]:\n", i);
ddf9c536
ID
15468 err_printf(m, " Power: %s\n",
15469 error->pipe[i].power_domain_on ? "on" : "off");
edc3d884 15470 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
f301b1e1 15471 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
edc3d884
MK
15472
15473 err_printf(m, "Plane [%d]:\n", i);
15474 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
15475 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 15476 if (INTEL_INFO(dev)->gen <= 3) {
edc3d884
MK
15477 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
15478 err_printf(m, " POS: %08x\n", error->plane[i].pos);
80ca378b 15479 }
4b71a570 15480 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
edc3d884 15481 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4 15482 if (INTEL_INFO(dev)->gen >= 4) {
edc3d884
MK
15483 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
15484 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
c4a1d9e4
CW
15485 }
15486
edc3d884
MK
15487 err_printf(m, "Cursor [%d]:\n", i);
15488 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
15489 err_printf(m, " POS: %08x\n", error->cursor[i].position);
15490 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
c4a1d9e4 15491 }
63b66e5b
CW
15492
15493 for (i = 0; i < error->num_transcoders; i++) {
1cf84bb6 15494 err_printf(m, "CPU transcoder: %c\n",
63b66e5b 15495 transcoder_name(error->transcoder[i].cpu_transcoder));
ddf9c536
ID
15496 err_printf(m, " Power: %s\n",
15497 error->transcoder[i].power_domain_on ? "on" : "off");
63b66e5b
CW
15498 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
15499 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
15500 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
15501 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
15502 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
15503 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
15504 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
15505 }
c4a1d9e4 15506}
e2fcdaa9
VS
15507
15508void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
15509{
15510 struct intel_crtc *crtc;
15511
15512 for_each_intel_crtc(dev, crtc) {
15513 struct intel_unpin_work *work;
e2fcdaa9 15514
5e2d7afc 15515 spin_lock_irq(&dev->event_lock);
e2fcdaa9
VS
15516
15517 work = crtc->unpin_work;
15518
15519 if (work && work->event &&
15520 work->event->base.file_priv == file) {
15521 kfree(work->event);
15522 work->event = NULL;
15523 }
15524
5e2d7afc 15525 spin_unlock_irq(&dev->event_lock);
e2fcdaa9
VS
15526 }
15527}