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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
618563e3 | 27 | #include <linux/dmi.h> |
c1c7af60 JB |
28 | #include <linux/module.h> |
29 | #include <linux/input.h> | |
79e53945 | 30 | #include <linux/i2c.h> |
7662c8bd | 31 | #include <linux/kernel.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
9cce37f4 | 33 | #include <linux/vgaarb.h> |
e0dac65e | 34 | #include <drm/drm_edid.h> |
760285e7 | 35 | #include <drm/drmP.h> |
79e53945 | 36 | #include "intel_drv.h" |
760285e7 | 37 | #include <drm/i915_drm.h> |
79e53945 | 38 | #include "i915_drv.h" |
e5510fac | 39 | #include "i915_trace.h" |
319c1d42 | 40 | #include <drm/drm_atomic.h> |
c196e1d6 | 41 | #include <drm/drm_atomic_helper.h> |
760285e7 DH |
42 | #include <drm/drm_dp_helper.h> |
43 | #include <drm/drm_crtc_helper.h> | |
465c120c MR |
44 | #include <drm/drm_plane_helper.h> |
45 | #include <drm/drm_rect.h> | |
c0f372b3 | 46 | #include <linux/dma_remapping.h> |
79e53945 | 47 | |
465c120c | 48 | /* Primary plane formats for gen <= 3 */ |
568db4f2 | 49 | static const uint32_t i8xx_primary_formats[] = { |
67fe7dc5 DL |
50 | DRM_FORMAT_C8, |
51 | DRM_FORMAT_RGB565, | |
465c120c | 52 | DRM_FORMAT_XRGB1555, |
67fe7dc5 | 53 | DRM_FORMAT_XRGB8888, |
465c120c MR |
54 | }; |
55 | ||
56 | /* Primary plane formats for gen >= 4 */ | |
568db4f2 | 57 | static const uint32_t i965_primary_formats[] = { |
6c0fd451 DL |
58 | DRM_FORMAT_C8, |
59 | DRM_FORMAT_RGB565, | |
60 | DRM_FORMAT_XRGB8888, | |
61 | DRM_FORMAT_XBGR8888, | |
62 | DRM_FORMAT_XRGB2101010, | |
63 | DRM_FORMAT_XBGR2101010, | |
64 | }; | |
65 | ||
66 | static const uint32_t skl_primary_formats[] = { | |
67fe7dc5 DL |
67 | DRM_FORMAT_C8, |
68 | DRM_FORMAT_RGB565, | |
69 | DRM_FORMAT_XRGB8888, | |
465c120c | 70 | DRM_FORMAT_XBGR8888, |
67fe7dc5 | 71 | DRM_FORMAT_ARGB8888, |
465c120c MR |
72 | DRM_FORMAT_ABGR8888, |
73 | DRM_FORMAT_XRGB2101010, | |
465c120c | 74 | DRM_FORMAT_XBGR2101010, |
465c120c MR |
75 | }; |
76 | ||
3d7d6510 MR |
77 | /* Cursor formats */ |
78 | static const uint32_t intel_cursor_formats[] = { | |
79 | DRM_FORMAT_ARGB8888, | |
80 | }; | |
81 | ||
6b383a7f | 82 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on); |
79e53945 | 83 | |
f1f644dc | 84 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 85 | struct intel_crtc_state *pipe_config); |
18442d08 | 86 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 87 | struct intel_crtc_state *pipe_config); |
f1f644dc | 88 | |
568c634a | 89 | static int intel_set_mode(struct drm_atomic_state *state); |
eb1bfe80 JB |
90 | static int intel_framebuffer_init(struct drm_device *dev, |
91 | struct intel_framebuffer *ifb, | |
92 | struct drm_mode_fb_cmd2 *mode_cmd, | |
93 | struct drm_i915_gem_object *obj); | |
5b18e57c DV |
94 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc); |
95 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc); | |
29407aab | 96 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, |
f769cd24 VK |
97 | struct intel_link_m_n *m_n, |
98 | struct intel_link_m_n *m2_n2); | |
29407aab | 99 | static void ironlake_set_pipeconf(struct drm_crtc *crtc); |
229fca97 DV |
100 | static void haswell_set_pipeconf(struct drm_crtc *crtc); |
101 | static void intel_set_pipe_csc(struct drm_crtc *crtc); | |
d288f65f | 102 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 103 | const struct intel_crtc_state *pipe_config); |
d288f65f | 104 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 105 | const struct intel_crtc_state *pipe_config); |
ea2c67bb MR |
106 | static void intel_begin_crtc_commit(struct drm_crtc *crtc); |
107 | static void intel_finish_crtc_commit(struct drm_crtc *crtc); | |
549e2bfb CK |
108 | static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc, |
109 | struct intel_crtc_state *crtc_state); | |
5ab7b0b7 ID |
110 | static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state, |
111 | int num_connectors); | |
ce22dba9 ML |
112 | static void intel_crtc_enable_planes(struct drm_crtc *crtc); |
113 | static void intel_crtc_disable_planes(struct drm_crtc *crtc); | |
e7457a9a | 114 | |
0e32b39c DA |
115 | static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe) |
116 | { | |
117 | if (!connector->mst_port) | |
118 | return connector->encoder; | |
119 | else | |
120 | return &connector->mst_port->mst_encoders[pipe]->base; | |
121 | } | |
122 | ||
79e53945 | 123 | typedef struct { |
0206e353 | 124 | int min, max; |
79e53945 JB |
125 | } intel_range_t; |
126 | ||
127 | typedef struct { | |
0206e353 AJ |
128 | int dot_limit; |
129 | int p2_slow, p2_fast; | |
79e53945 JB |
130 | } intel_p2_t; |
131 | ||
d4906093 ML |
132 | typedef struct intel_limit intel_limit_t; |
133 | struct intel_limit { | |
0206e353 AJ |
134 | intel_range_t dot, vco, n, m, m1, m2, p, p1; |
135 | intel_p2_t p2; | |
d4906093 | 136 | }; |
79e53945 | 137 | |
d2acd215 DV |
138 | int |
139 | intel_pch_rawclk(struct drm_device *dev) | |
140 | { | |
141 | struct drm_i915_private *dev_priv = dev->dev_private; | |
142 | ||
143 | WARN_ON(!HAS_PCH_SPLIT(dev)); | |
144 | ||
145 | return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK; | |
146 | } | |
147 | ||
021357ac CW |
148 | static inline u32 /* units of 100MHz */ |
149 | intel_fdi_link_freq(struct drm_device *dev) | |
150 | { | |
8b99e68c CW |
151 | if (IS_GEN5(dev)) { |
152 | struct drm_i915_private *dev_priv = dev->dev_private; | |
153 | return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2; | |
154 | } else | |
155 | return 27; | |
021357ac CW |
156 | } |
157 | ||
5d536e28 | 158 | static const intel_limit_t intel_limits_i8xx_dac = { |
0206e353 | 159 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 160 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 161 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
162 | .m = { .min = 96, .max = 140 }, |
163 | .m1 = { .min = 18, .max = 26 }, | |
164 | .m2 = { .min = 6, .max = 16 }, | |
165 | .p = { .min = 4, .max = 128 }, | |
166 | .p1 = { .min = 2, .max = 33 }, | |
273e27ca EA |
167 | .p2 = { .dot_limit = 165000, |
168 | .p2_slow = 4, .p2_fast = 2 }, | |
e4b36699 KP |
169 | }; |
170 | ||
5d536e28 DV |
171 | static const intel_limit_t intel_limits_i8xx_dvo = { |
172 | .dot = { .min = 25000, .max = 350000 }, | |
9c333719 | 173 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 174 | .n = { .min = 2, .max = 16 }, |
5d536e28 DV |
175 | .m = { .min = 96, .max = 140 }, |
176 | .m1 = { .min = 18, .max = 26 }, | |
177 | .m2 = { .min = 6, .max = 16 }, | |
178 | .p = { .min = 4, .max = 128 }, | |
179 | .p1 = { .min = 2, .max = 33 }, | |
180 | .p2 = { .dot_limit = 165000, | |
181 | .p2_slow = 4, .p2_fast = 4 }, | |
182 | }; | |
183 | ||
e4b36699 | 184 | static const intel_limit_t intel_limits_i8xx_lvds = { |
0206e353 | 185 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 186 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 187 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
188 | .m = { .min = 96, .max = 140 }, |
189 | .m1 = { .min = 18, .max = 26 }, | |
190 | .m2 = { .min = 6, .max = 16 }, | |
191 | .p = { .min = 4, .max = 128 }, | |
192 | .p1 = { .min = 1, .max = 6 }, | |
273e27ca EA |
193 | .p2 = { .dot_limit = 165000, |
194 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 | 195 | }; |
273e27ca | 196 | |
e4b36699 | 197 | static const intel_limit_t intel_limits_i9xx_sdvo = { |
0206e353 AJ |
198 | .dot = { .min = 20000, .max = 400000 }, |
199 | .vco = { .min = 1400000, .max = 2800000 }, | |
200 | .n = { .min = 1, .max = 6 }, | |
201 | .m = { .min = 70, .max = 120 }, | |
4f7dfb67 PJ |
202 | .m1 = { .min = 8, .max = 18 }, |
203 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
204 | .p = { .min = 5, .max = 80 }, |
205 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
206 | .p2 = { .dot_limit = 200000, |
207 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
208 | }; |
209 | ||
210 | static const intel_limit_t intel_limits_i9xx_lvds = { | |
0206e353 AJ |
211 | .dot = { .min = 20000, .max = 400000 }, |
212 | .vco = { .min = 1400000, .max = 2800000 }, | |
213 | .n = { .min = 1, .max = 6 }, | |
214 | .m = { .min = 70, .max = 120 }, | |
53a7d2d1 PJ |
215 | .m1 = { .min = 8, .max = 18 }, |
216 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
217 | .p = { .min = 7, .max = 98 }, |
218 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
219 | .p2 = { .dot_limit = 112000, |
220 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 KP |
221 | }; |
222 | ||
273e27ca | 223 | |
e4b36699 | 224 | static const intel_limit_t intel_limits_g4x_sdvo = { |
273e27ca EA |
225 | .dot = { .min = 25000, .max = 270000 }, |
226 | .vco = { .min = 1750000, .max = 3500000}, | |
227 | .n = { .min = 1, .max = 4 }, | |
228 | .m = { .min = 104, .max = 138 }, | |
229 | .m1 = { .min = 17, .max = 23 }, | |
230 | .m2 = { .min = 5, .max = 11 }, | |
231 | .p = { .min = 10, .max = 30 }, | |
232 | .p1 = { .min = 1, .max = 3}, | |
233 | .p2 = { .dot_limit = 270000, | |
234 | .p2_slow = 10, | |
235 | .p2_fast = 10 | |
044c7c41 | 236 | }, |
e4b36699 KP |
237 | }; |
238 | ||
239 | static const intel_limit_t intel_limits_g4x_hdmi = { | |
273e27ca EA |
240 | .dot = { .min = 22000, .max = 400000 }, |
241 | .vco = { .min = 1750000, .max = 3500000}, | |
242 | .n = { .min = 1, .max = 4 }, | |
243 | .m = { .min = 104, .max = 138 }, | |
244 | .m1 = { .min = 16, .max = 23 }, | |
245 | .m2 = { .min = 5, .max = 11 }, | |
246 | .p = { .min = 5, .max = 80 }, | |
247 | .p1 = { .min = 1, .max = 8}, | |
248 | .p2 = { .dot_limit = 165000, | |
249 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
250 | }; |
251 | ||
252 | static const intel_limit_t intel_limits_g4x_single_channel_lvds = { | |
273e27ca EA |
253 | .dot = { .min = 20000, .max = 115000 }, |
254 | .vco = { .min = 1750000, .max = 3500000 }, | |
255 | .n = { .min = 1, .max = 3 }, | |
256 | .m = { .min = 104, .max = 138 }, | |
257 | .m1 = { .min = 17, .max = 23 }, | |
258 | .m2 = { .min = 5, .max = 11 }, | |
259 | .p = { .min = 28, .max = 112 }, | |
260 | .p1 = { .min = 2, .max = 8 }, | |
261 | .p2 = { .dot_limit = 0, | |
262 | .p2_slow = 14, .p2_fast = 14 | |
044c7c41 | 263 | }, |
e4b36699 KP |
264 | }; |
265 | ||
266 | static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { | |
273e27ca EA |
267 | .dot = { .min = 80000, .max = 224000 }, |
268 | .vco = { .min = 1750000, .max = 3500000 }, | |
269 | .n = { .min = 1, .max = 3 }, | |
270 | .m = { .min = 104, .max = 138 }, | |
271 | .m1 = { .min = 17, .max = 23 }, | |
272 | .m2 = { .min = 5, .max = 11 }, | |
273 | .p = { .min = 14, .max = 42 }, | |
274 | .p1 = { .min = 2, .max = 6 }, | |
275 | .p2 = { .dot_limit = 0, | |
276 | .p2_slow = 7, .p2_fast = 7 | |
044c7c41 | 277 | }, |
e4b36699 KP |
278 | }; |
279 | ||
f2b115e6 | 280 | static const intel_limit_t intel_limits_pineview_sdvo = { |
0206e353 AJ |
281 | .dot = { .min = 20000, .max = 400000}, |
282 | .vco = { .min = 1700000, .max = 3500000 }, | |
273e27ca | 283 | /* Pineview's Ncounter is a ring counter */ |
0206e353 AJ |
284 | .n = { .min = 3, .max = 6 }, |
285 | .m = { .min = 2, .max = 256 }, | |
273e27ca | 286 | /* Pineview only has one combined m divider, which we treat as m2. */ |
0206e353 AJ |
287 | .m1 = { .min = 0, .max = 0 }, |
288 | .m2 = { .min = 0, .max = 254 }, | |
289 | .p = { .min = 5, .max = 80 }, | |
290 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
291 | .p2 = { .dot_limit = 200000, |
292 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
293 | }; |
294 | ||
f2b115e6 | 295 | static const intel_limit_t intel_limits_pineview_lvds = { |
0206e353 AJ |
296 | .dot = { .min = 20000, .max = 400000 }, |
297 | .vco = { .min = 1700000, .max = 3500000 }, | |
298 | .n = { .min = 3, .max = 6 }, | |
299 | .m = { .min = 2, .max = 256 }, | |
300 | .m1 = { .min = 0, .max = 0 }, | |
301 | .m2 = { .min = 0, .max = 254 }, | |
302 | .p = { .min = 7, .max = 112 }, | |
303 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
304 | .p2 = { .dot_limit = 112000, |
305 | .p2_slow = 14, .p2_fast = 14 }, | |
e4b36699 KP |
306 | }; |
307 | ||
273e27ca EA |
308 | /* Ironlake / Sandybridge |
309 | * | |
310 | * We calculate clock using (register_value + 2) for N/M1/M2, so here | |
311 | * the range value for them is (actual_value - 2). | |
312 | */ | |
b91ad0ec | 313 | static const intel_limit_t intel_limits_ironlake_dac = { |
273e27ca EA |
314 | .dot = { .min = 25000, .max = 350000 }, |
315 | .vco = { .min = 1760000, .max = 3510000 }, | |
316 | .n = { .min = 1, .max = 5 }, | |
317 | .m = { .min = 79, .max = 127 }, | |
318 | .m1 = { .min = 12, .max = 22 }, | |
319 | .m2 = { .min = 5, .max = 9 }, | |
320 | .p = { .min = 5, .max = 80 }, | |
321 | .p1 = { .min = 1, .max = 8 }, | |
322 | .p2 = { .dot_limit = 225000, | |
323 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
324 | }; |
325 | ||
b91ad0ec | 326 | static const intel_limit_t intel_limits_ironlake_single_lvds = { |
273e27ca EA |
327 | .dot = { .min = 25000, .max = 350000 }, |
328 | .vco = { .min = 1760000, .max = 3510000 }, | |
329 | .n = { .min = 1, .max = 3 }, | |
330 | .m = { .min = 79, .max = 118 }, | |
331 | .m1 = { .min = 12, .max = 22 }, | |
332 | .m2 = { .min = 5, .max = 9 }, | |
333 | .p = { .min = 28, .max = 112 }, | |
334 | .p1 = { .min = 2, .max = 8 }, | |
335 | .p2 = { .dot_limit = 225000, | |
336 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
337 | }; |
338 | ||
339 | static const intel_limit_t intel_limits_ironlake_dual_lvds = { | |
273e27ca EA |
340 | .dot = { .min = 25000, .max = 350000 }, |
341 | .vco = { .min = 1760000, .max = 3510000 }, | |
342 | .n = { .min = 1, .max = 3 }, | |
343 | .m = { .min = 79, .max = 127 }, | |
344 | .m1 = { .min = 12, .max = 22 }, | |
345 | .m2 = { .min = 5, .max = 9 }, | |
346 | .p = { .min = 14, .max = 56 }, | |
347 | .p1 = { .min = 2, .max = 8 }, | |
348 | .p2 = { .dot_limit = 225000, | |
349 | .p2_slow = 7, .p2_fast = 7 }, | |
b91ad0ec ZW |
350 | }; |
351 | ||
273e27ca | 352 | /* LVDS 100mhz refclk limits. */ |
b91ad0ec | 353 | static const intel_limit_t intel_limits_ironlake_single_lvds_100m = { |
273e27ca EA |
354 | .dot = { .min = 25000, .max = 350000 }, |
355 | .vco = { .min = 1760000, .max = 3510000 }, | |
356 | .n = { .min = 1, .max = 2 }, | |
357 | .m = { .min = 79, .max = 126 }, | |
358 | .m1 = { .min = 12, .max = 22 }, | |
359 | .m2 = { .min = 5, .max = 9 }, | |
360 | .p = { .min = 28, .max = 112 }, | |
0206e353 | 361 | .p1 = { .min = 2, .max = 8 }, |
273e27ca EA |
362 | .p2 = { .dot_limit = 225000, |
363 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
364 | }; |
365 | ||
366 | static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = { | |
273e27ca EA |
367 | .dot = { .min = 25000, .max = 350000 }, |
368 | .vco = { .min = 1760000, .max = 3510000 }, | |
369 | .n = { .min = 1, .max = 3 }, | |
370 | .m = { .min = 79, .max = 126 }, | |
371 | .m1 = { .min = 12, .max = 22 }, | |
372 | .m2 = { .min = 5, .max = 9 }, | |
373 | .p = { .min = 14, .max = 42 }, | |
0206e353 | 374 | .p1 = { .min = 2, .max = 6 }, |
273e27ca EA |
375 | .p2 = { .dot_limit = 225000, |
376 | .p2_slow = 7, .p2_fast = 7 }, | |
4547668a ZY |
377 | }; |
378 | ||
dc730512 | 379 | static const intel_limit_t intel_limits_vlv = { |
f01b7962 VS |
380 | /* |
381 | * These are the data rate limits (measured in fast clocks) | |
382 | * since those are the strictest limits we have. The fast | |
383 | * clock and actual rate limits are more relaxed, so checking | |
384 | * them would make no difference. | |
385 | */ | |
386 | .dot = { .min = 25000 * 5, .max = 270000 * 5 }, | |
75e53986 | 387 | .vco = { .min = 4000000, .max = 6000000 }, |
a0c4da24 | 388 | .n = { .min = 1, .max = 7 }, |
a0c4da24 JB |
389 | .m1 = { .min = 2, .max = 3 }, |
390 | .m2 = { .min = 11, .max = 156 }, | |
b99ab663 | 391 | .p1 = { .min = 2, .max = 3 }, |
5fdc9c49 | 392 | .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */ |
a0c4da24 JB |
393 | }; |
394 | ||
ef9348c8 CML |
395 | static const intel_limit_t intel_limits_chv = { |
396 | /* | |
397 | * These are the data rate limits (measured in fast clocks) | |
398 | * since those are the strictest limits we have. The fast | |
399 | * clock and actual rate limits are more relaxed, so checking | |
400 | * them would make no difference. | |
401 | */ | |
402 | .dot = { .min = 25000 * 5, .max = 540000 * 5}, | |
17fe1021 | 403 | .vco = { .min = 4800000, .max = 6480000 }, |
ef9348c8 CML |
404 | .n = { .min = 1, .max = 1 }, |
405 | .m1 = { .min = 2, .max = 2 }, | |
406 | .m2 = { .min = 24 << 22, .max = 175 << 22 }, | |
407 | .p1 = { .min = 2, .max = 4 }, | |
408 | .p2 = { .p2_slow = 1, .p2_fast = 14 }, | |
409 | }; | |
410 | ||
5ab7b0b7 ID |
411 | static const intel_limit_t intel_limits_bxt = { |
412 | /* FIXME: find real dot limits */ | |
413 | .dot = { .min = 0, .max = INT_MAX }, | |
414 | .vco = { .min = 4800000, .max = 6480000 }, | |
415 | .n = { .min = 1, .max = 1 }, | |
416 | .m1 = { .min = 2, .max = 2 }, | |
417 | /* FIXME: find real m2 limits */ | |
418 | .m2 = { .min = 2 << 22, .max = 255 << 22 }, | |
419 | .p1 = { .min = 2, .max = 4 }, | |
420 | .p2 = { .p2_slow = 1, .p2_fast = 20 }, | |
421 | }; | |
422 | ||
6b4bf1c4 VS |
423 | static void vlv_clock(int refclk, intel_clock_t *clock) |
424 | { | |
425 | clock->m = clock->m1 * clock->m2; | |
426 | clock->p = clock->p1 * clock->p2; | |
ed5ca77e VS |
427 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
428 | return; | |
fb03ac01 VS |
429 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
430 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
6b4bf1c4 VS |
431 | } |
432 | ||
cdba954e ACO |
433 | static bool |
434 | needs_modeset(struct drm_crtc_state *state) | |
435 | { | |
436 | return state->mode_changed || state->active_changed; | |
437 | } | |
438 | ||
e0638cdf PZ |
439 | /** |
440 | * Returns whether any output on the specified pipe is of the specified type | |
441 | */ | |
4093561b | 442 | bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type) |
e0638cdf | 443 | { |
409ee761 | 444 | struct drm_device *dev = crtc->base.dev; |
e0638cdf PZ |
445 | struct intel_encoder *encoder; |
446 | ||
409ee761 | 447 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) |
e0638cdf PZ |
448 | if (encoder->type == type) |
449 | return true; | |
450 | ||
451 | return false; | |
452 | } | |
453 | ||
d0737e1d ACO |
454 | /** |
455 | * Returns whether any output on the specified pipe will have the specified | |
456 | * type after a staged modeset is complete, i.e., the same as | |
457 | * intel_pipe_has_type() but looking at encoder->new_crtc instead of | |
458 | * encoder->crtc. | |
459 | */ | |
a93e255f ACO |
460 | static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state, |
461 | int type) | |
d0737e1d | 462 | { |
a93e255f | 463 | struct drm_atomic_state *state = crtc_state->base.state; |
da3ced29 | 464 | struct drm_connector *connector; |
a93e255f | 465 | struct drm_connector_state *connector_state; |
d0737e1d | 466 | struct intel_encoder *encoder; |
a93e255f ACO |
467 | int i, num_connectors = 0; |
468 | ||
da3ced29 | 469 | for_each_connector_in_state(state, connector, connector_state, i) { |
a93e255f ACO |
470 | if (connector_state->crtc != crtc_state->base.crtc) |
471 | continue; | |
472 | ||
473 | num_connectors++; | |
d0737e1d | 474 | |
a93e255f ACO |
475 | encoder = to_intel_encoder(connector_state->best_encoder); |
476 | if (encoder->type == type) | |
d0737e1d | 477 | return true; |
a93e255f ACO |
478 | } |
479 | ||
480 | WARN_ON(num_connectors == 0); | |
d0737e1d ACO |
481 | |
482 | return false; | |
483 | } | |
484 | ||
a93e255f ACO |
485 | static const intel_limit_t * |
486 | intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk) | |
2c07245f | 487 | { |
a93e255f | 488 | struct drm_device *dev = crtc_state->base.crtc->dev; |
2c07245f | 489 | const intel_limit_t *limit; |
b91ad0ec | 490 | |
a93e255f | 491 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
1974cad0 | 492 | if (intel_is_dual_link_lvds(dev)) { |
1b894b59 | 493 | if (refclk == 100000) |
b91ad0ec ZW |
494 | limit = &intel_limits_ironlake_dual_lvds_100m; |
495 | else | |
496 | limit = &intel_limits_ironlake_dual_lvds; | |
497 | } else { | |
1b894b59 | 498 | if (refclk == 100000) |
b91ad0ec ZW |
499 | limit = &intel_limits_ironlake_single_lvds_100m; |
500 | else | |
501 | limit = &intel_limits_ironlake_single_lvds; | |
502 | } | |
c6bb3538 | 503 | } else |
b91ad0ec | 504 | limit = &intel_limits_ironlake_dac; |
2c07245f ZW |
505 | |
506 | return limit; | |
507 | } | |
508 | ||
a93e255f ACO |
509 | static const intel_limit_t * |
510 | intel_g4x_limit(struct intel_crtc_state *crtc_state) | |
044c7c41 | 511 | { |
a93e255f | 512 | struct drm_device *dev = crtc_state->base.crtc->dev; |
044c7c41 ML |
513 | const intel_limit_t *limit; |
514 | ||
a93e255f | 515 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
1974cad0 | 516 | if (intel_is_dual_link_lvds(dev)) |
e4b36699 | 517 | limit = &intel_limits_g4x_dual_channel_lvds; |
044c7c41 | 518 | else |
e4b36699 | 519 | limit = &intel_limits_g4x_single_channel_lvds; |
a93e255f ACO |
520 | } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) || |
521 | intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) { | |
e4b36699 | 522 | limit = &intel_limits_g4x_hdmi; |
a93e255f | 523 | } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) { |
e4b36699 | 524 | limit = &intel_limits_g4x_sdvo; |
044c7c41 | 525 | } else /* The option is for other outputs */ |
e4b36699 | 526 | limit = &intel_limits_i9xx_sdvo; |
044c7c41 ML |
527 | |
528 | return limit; | |
529 | } | |
530 | ||
a93e255f ACO |
531 | static const intel_limit_t * |
532 | intel_limit(struct intel_crtc_state *crtc_state, int refclk) | |
79e53945 | 533 | { |
a93e255f | 534 | struct drm_device *dev = crtc_state->base.crtc->dev; |
79e53945 JB |
535 | const intel_limit_t *limit; |
536 | ||
5ab7b0b7 ID |
537 | if (IS_BROXTON(dev)) |
538 | limit = &intel_limits_bxt; | |
539 | else if (HAS_PCH_SPLIT(dev)) | |
a93e255f | 540 | limit = intel_ironlake_limit(crtc_state, refclk); |
2c07245f | 541 | else if (IS_G4X(dev)) { |
a93e255f | 542 | limit = intel_g4x_limit(crtc_state); |
f2b115e6 | 543 | } else if (IS_PINEVIEW(dev)) { |
a93e255f | 544 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
f2b115e6 | 545 | limit = &intel_limits_pineview_lvds; |
2177832f | 546 | else |
f2b115e6 | 547 | limit = &intel_limits_pineview_sdvo; |
ef9348c8 CML |
548 | } else if (IS_CHERRYVIEW(dev)) { |
549 | limit = &intel_limits_chv; | |
a0c4da24 | 550 | } else if (IS_VALLEYVIEW(dev)) { |
dc730512 | 551 | limit = &intel_limits_vlv; |
a6c45cf0 | 552 | } else if (!IS_GEN2(dev)) { |
a93e255f | 553 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
a6c45cf0 CW |
554 | limit = &intel_limits_i9xx_lvds; |
555 | else | |
556 | limit = &intel_limits_i9xx_sdvo; | |
79e53945 | 557 | } else { |
a93e255f | 558 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
e4b36699 | 559 | limit = &intel_limits_i8xx_lvds; |
a93e255f | 560 | else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO)) |
e4b36699 | 561 | limit = &intel_limits_i8xx_dvo; |
5d536e28 DV |
562 | else |
563 | limit = &intel_limits_i8xx_dac; | |
79e53945 JB |
564 | } |
565 | return limit; | |
566 | } | |
567 | ||
f2b115e6 AJ |
568 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
569 | static void pineview_clock(int refclk, intel_clock_t *clock) | |
79e53945 | 570 | { |
2177832f SL |
571 | clock->m = clock->m2 + 2; |
572 | clock->p = clock->p1 * clock->p2; | |
ed5ca77e VS |
573 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
574 | return; | |
fb03ac01 VS |
575 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
576 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
2177832f SL |
577 | } |
578 | ||
7429e9d4 DV |
579 | static uint32_t i9xx_dpll_compute_m(struct dpll *dpll) |
580 | { | |
581 | return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); | |
582 | } | |
583 | ||
ac58c3f0 | 584 | static void i9xx_clock(int refclk, intel_clock_t *clock) |
2177832f | 585 | { |
7429e9d4 | 586 | clock->m = i9xx_dpll_compute_m(clock); |
79e53945 | 587 | clock->p = clock->p1 * clock->p2; |
ed5ca77e VS |
588 | if (WARN_ON(clock->n + 2 == 0 || clock->p == 0)) |
589 | return; | |
fb03ac01 VS |
590 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2); |
591 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
79e53945 JB |
592 | } |
593 | ||
ef9348c8 CML |
594 | static void chv_clock(int refclk, intel_clock_t *clock) |
595 | { | |
596 | clock->m = clock->m1 * clock->m2; | |
597 | clock->p = clock->p1 * clock->p2; | |
598 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
599 | return; | |
600 | clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m, | |
601 | clock->n << 22); | |
602 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
603 | } | |
604 | ||
7c04d1d9 | 605 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
79e53945 JB |
606 | /** |
607 | * Returns whether the given set of divisors are valid for a given refclk with | |
608 | * the given connectors. | |
609 | */ | |
610 | ||
1b894b59 CW |
611 | static bool intel_PLL_is_valid(struct drm_device *dev, |
612 | const intel_limit_t *limit, | |
613 | const intel_clock_t *clock) | |
79e53945 | 614 | { |
f01b7962 VS |
615 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
616 | INTELPllInvalid("n out of range\n"); | |
79e53945 | 617 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
0206e353 | 618 | INTELPllInvalid("p1 out of range\n"); |
79e53945 | 619 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
0206e353 | 620 | INTELPllInvalid("m2 out of range\n"); |
79e53945 | 621 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
0206e353 | 622 | INTELPllInvalid("m1 out of range\n"); |
f01b7962 | 623 | |
5ab7b0b7 | 624 | if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) |
f01b7962 VS |
625 | if (clock->m1 <= clock->m2) |
626 | INTELPllInvalid("m1 <= m2\n"); | |
627 | ||
5ab7b0b7 | 628 | if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) { |
f01b7962 VS |
629 | if (clock->p < limit->p.min || limit->p.max < clock->p) |
630 | INTELPllInvalid("p out of range\n"); | |
631 | if (clock->m < limit->m.min || limit->m.max < clock->m) | |
632 | INTELPllInvalid("m out of range\n"); | |
633 | } | |
634 | ||
79e53945 | 635 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
0206e353 | 636 | INTELPllInvalid("vco out of range\n"); |
79e53945 JB |
637 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
638 | * connector, etc., rather than just a single range. | |
639 | */ | |
640 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) | |
0206e353 | 641 | INTELPllInvalid("dot out of range\n"); |
79e53945 JB |
642 | |
643 | return true; | |
644 | } | |
645 | ||
d4906093 | 646 | static bool |
a93e255f ACO |
647 | i9xx_find_best_dpll(const intel_limit_t *limit, |
648 | struct intel_crtc_state *crtc_state, | |
cec2f356 SP |
649 | int target, int refclk, intel_clock_t *match_clock, |
650 | intel_clock_t *best_clock) | |
79e53945 | 651 | { |
a93e255f | 652 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 653 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 654 | intel_clock_t clock; |
79e53945 JB |
655 | int err = target; |
656 | ||
a93e255f | 657 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
79e53945 | 658 | /* |
a210b028 DV |
659 | * For LVDS just rely on its current settings for dual-channel. |
660 | * We haven't figured out how to reliably set up different | |
661 | * single/dual channel state, if we even can. | |
79e53945 | 662 | */ |
1974cad0 | 663 | if (intel_is_dual_link_lvds(dev)) |
79e53945 JB |
664 | clock.p2 = limit->p2.p2_fast; |
665 | else | |
666 | clock.p2 = limit->p2.p2_slow; | |
667 | } else { | |
668 | if (target < limit->p2.dot_limit) | |
669 | clock.p2 = limit->p2.p2_slow; | |
670 | else | |
671 | clock.p2 = limit->p2.p2_fast; | |
672 | } | |
673 | ||
0206e353 | 674 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 675 | |
42158660 ZY |
676 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
677 | clock.m1++) { | |
678 | for (clock.m2 = limit->m2.min; | |
679 | clock.m2 <= limit->m2.max; clock.m2++) { | |
c0efc387 | 680 | if (clock.m2 >= clock.m1) |
42158660 ZY |
681 | break; |
682 | for (clock.n = limit->n.min; | |
683 | clock.n <= limit->n.max; clock.n++) { | |
684 | for (clock.p1 = limit->p1.min; | |
685 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
686 | int this_err; |
687 | ||
ac58c3f0 DV |
688 | i9xx_clock(refclk, &clock); |
689 | if (!intel_PLL_is_valid(dev, limit, | |
690 | &clock)) | |
691 | continue; | |
692 | if (match_clock && | |
693 | clock.p != match_clock->p) | |
694 | continue; | |
695 | ||
696 | this_err = abs(clock.dot - target); | |
697 | if (this_err < err) { | |
698 | *best_clock = clock; | |
699 | err = this_err; | |
700 | } | |
701 | } | |
702 | } | |
703 | } | |
704 | } | |
705 | ||
706 | return (err != target); | |
707 | } | |
708 | ||
709 | static bool | |
a93e255f ACO |
710 | pnv_find_best_dpll(const intel_limit_t *limit, |
711 | struct intel_crtc_state *crtc_state, | |
ee9300bb DV |
712 | int target, int refclk, intel_clock_t *match_clock, |
713 | intel_clock_t *best_clock) | |
79e53945 | 714 | { |
a93e255f | 715 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 716 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 717 | intel_clock_t clock; |
79e53945 JB |
718 | int err = target; |
719 | ||
a93e255f | 720 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
79e53945 | 721 | /* |
a210b028 DV |
722 | * For LVDS just rely on its current settings for dual-channel. |
723 | * We haven't figured out how to reliably set up different | |
724 | * single/dual channel state, if we even can. | |
79e53945 | 725 | */ |
1974cad0 | 726 | if (intel_is_dual_link_lvds(dev)) |
79e53945 JB |
727 | clock.p2 = limit->p2.p2_fast; |
728 | else | |
729 | clock.p2 = limit->p2.p2_slow; | |
730 | } else { | |
731 | if (target < limit->p2.dot_limit) | |
732 | clock.p2 = limit->p2.p2_slow; | |
733 | else | |
734 | clock.p2 = limit->p2.p2_fast; | |
735 | } | |
736 | ||
0206e353 | 737 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 738 | |
42158660 ZY |
739 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
740 | clock.m1++) { | |
741 | for (clock.m2 = limit->m2.min; | |
742 | clock.m2 <= limit->m2.max; clock.m2++) { | |
42158660 ZY |
743 | for (clock.n = limit->n.min; |
744 | clock.n <= limit->n.max; clock.n++) { | |
745 | for (clock.p1 = limit->p1.min; | |
746 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
747 | int this_err; |
748 | ||
ac58c3f0 | 749 | pineview_clock(refclk, &clock); |
1b894b59 CW |
750 | if (!intel_PLL_is_valid(dev, limit, |
751 | &clock)) | |
79e53945 | 752 | continue; |
cec2f356 SP |
753 | if (match_clock && |
754 | clock.p != match_clock->p) | |
755 | continue; | |
79e53945 JB |
756 | |
757 | this_err = abs(clock.dot - target); | |
758 | if (this_err < err) { | |
759 | *best_clock = clock; | |
760 | err = this_err; | |
761 | } | |
762 | } | |
763 | } | |
764 | } | |
765 | } | |
766 | ||
767 | return (err != target); | |
768 | } | |
769 | ||
d4906093 | 770 | static bool |
a93e255f ACO |
771 | g4x_find_best_dpll(const intel_limit_t *limit, |
772 | struct intel_crtc_state *crtc_state, | |
ee9300bb DV |
773 | int target, int refclk, intel_clock_t *match_clock, |
774 | intel_clock_t *best_clock) | |
d4906093 | 775 | { |
a93e255f | 776 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 777 | struct drm_device *dev = crtc->base.dev; |
d4906093 ML |
778 | intel_clock_t clock; |
779 | int max_n; | |
780 | bool found; | |
6ba770dc AJ |
781 | /* approximately equals target * 0.00585 */ |
782 | int err_most = (target >> 8) + (target >> 9); | |
d4906093 ML |
783 | found = false; |
784 | ||
a93e255f | 785 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
1974cad0 | 786 | if (intel_is_dual_link_lvds(dev)) |
d4906093 ML |
787 | clock.p2 = limit->p2.p2_fast; |
788 | else | |
789 | clock.p2 = limit->p2.p2_slow; | |
790 | } else { | |
791 | if (target < limit->p2.dot_limit) | |
792 | clock.p2 = limit->p2.p2_slow; | |
793 | else | |
794 | clock.p2 = limit->p2.p2_fast; | |
795 | } | |
796 | ||
797 | memset(best_clock, 0, sizeof(*best_clock)); | |
798 | max_n = limit->n.max; | |
f77f13e2 | 799 | /* based on hardware requirement, prefer smaller n to precision */ |
d4906093 | 800 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
f77f13e2 | 801 | /* based on hardware requirement, prefere larger m1,m2 */ |
d4906093 ML |
802 | for (clock.m1 = limit->m1.max; |
803 | clock.m1 >= limit->m1.min; clock.m1--) { | |
804 | for (clock.m2 = limit->m2.max; | |
805 | clock.m2 >= limit->m2.min; clock.m2--) { | |
806 | for (clock.p1 = limit->p1.max; | |
807 | clock.p1 >= limit->p1.min; clock.p1--) { | |
808 | int this_err; | |
809 | ||
ac58c3f0 | 810 | i9xx_clock(refclk, &clock); |
1b894b59 CW |
811 | if (!intel_PLL_is_valid(dev, limit, |
812 | &clock)) | |
d4906093 | 813 | continue; |
1b894b59 CW |
814 | |
815 | this_err = abs(clock.dot - target); | |
d4906093 ML |
816 | if (this_err < err_most) { |
817 | *best_clock = clock; | |
818 | err_most = this_err; | |
819 | max_n = clock.n; | |
820 | found = true; | |
821 | } | |
822 | } | |
823 | } | |
824 | } | |
825 | } | |
2c07245f ZW |
826 | return found; |
827 | } | |
828 | ||
d5dd62bd ID |
829 | /* |
830 | * Check if the calculated PLL configuration is more optimal compared to the | |
831 | * best configuration and error found so far. Return the calculated error. | |
832 | */ | |
833 | static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq, | |
834 | const intel_clock_t *calculated_clock, | |
835 | const intel_clock_t *best_clock, | |
836 | unsigned int best_error_ppm, | |
837 | unsigned int *error_ppm) | |
838 | { | |
9ca3ba01 ID |
839 | /* |
840 | * For CHV ignore the error and consider only the P value. | |
841 | * Prefer a bigger P value based on HW requirements. | |
842 | */ | |
843 | if (IS_CHERRYVIEW(dev)) { | |
844 | *error_ppm = 0; | |
845 | ||
846 | return calculated_clock->p > best_clock->p; | |
847 | } | |
848 | ||
24be4e46 ID |
849 | if (WARN_ON_ONCE(!target_freq)) |
850 | return false; | |
851 | ||
d5dd62bd ID |
852 | *error_ppm = div_u64(1000000ULL * |
853 | abs(target_freq - calculated_clock->dot), | |
854 | target_freq); | |
855 | /* | |
856 | * Prefer a better P value over a better (smaller) error if the error | |
857 | * is small. Ensure this preference for future configurations too by | |
858 | * setting the error to 0. | |
859 | */ | |
860 | if (*error_ppm < 100 && calculated_clock->p > best_clock->p) { | |
861 | *error_ppm = 0; | |
862 | ||
863 | return true; | |
864 | } | |
865 | ||
866 | return *error_ppm + 10 < best_error_ppm; | |
867 | } | |
868 | ||
a0c4da24 | 869 | static bool |
a93e255f ACO |
870 | vlv_find_best_dpll(const intel_limit_t *limit, |
871 | struct intel_crtc_state *crtc_state, | |
ee9300bb DV |
872 | int target, int refclk, intel_clock_t *match_clock, |
873 | intel_clock_t *best_clock) | |
a0c4da24 | 874 | { |
a93e255f | 875 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 876 | struct drm_device *dev = crtc->base.dev; |
6b4bf1c4 | 877 | intel_clock_t clock; |
69e4f900 | 878 | unsigned int bestppm = 1000000; |
27e639bf VS |
879 | /* min update 19.2 MHz */ |
880 | int max_n = min(limit->n.max, refclk / 19200); | |
49e497ef | 881 | bool found = false; |
a0c4da24 | 882 | |
6b4bf1c4 VS |
883 | target *= 5; /* fast clock */ |
884 | ||
885 | memset(best_clock, 0, sizeof(*best_clock)); | |
a0c4da24 JB |
886 | |
887 | /* based on hardware requirement, prefer smaller n to precision */ | |
27e639bf | 888 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
811bbf05 | 889 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { |
889059d8 | 890 | for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow; |
c1a9ae43 | 891 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { |
6b4bf1c4 | 892 | clock.p = clock.p1 * clock.p2; |
a0c4da24 | 893 | /* based on hardware requirement, prefer bigger m1,m2 values */ |
6b4bf1c4 | 894 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { |
d5dd62bd | 895 | unsigned int ppm; |
69e4f900 | 896 | |
6b4bf1c4 VS |
897 | clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n, |
898 | refclk * clock.m1); | |
899 | ||
900 | vlv_clock(refclk, &clock); | |
43b0ac53 | 901 | |
f01b7962 VS |
902 | if (!intel_PLL_is_valid(dev, limit, |
903 | &clock)) | |
43b0ac53 VS |
904 | continue; |
905 | ||
d5dd62bd ID |
906 | if (!vlv_PLL_is_optimal(dev, target, |
907 | &clock, | |
908 | best_clock, | |
909 | bestppm, &ppm)) | |
910 | continue; | |
6b4bf1c4 | 911 | |
d5dd62bd ID |
912 | *best_clock = clock; |
913 | bestppm = ppm; | |
914 | found = true; | |
a0c4da24 JB |
915 | } |
916 | } | |
917 | } | |
918 | } | |
a0c4da24 | 919 | |
49e497ef | 920 | return found; |
a0c4da24 | 921 | } |
a4fc5ed6 | 922 | |
ef9348c8 | 923 | static bool |
a93e255f ACO |
924 | chv_find_best_dpll(const intel_limit_t *limit, |
925 | struct intel_crtc_state *crtc_state, | |
ef9348c8 CML |
926 | int target, int refclk, intel_clock_t *match_clock, |
927 | intel_clock_t *best_clock) | |
928 | { | |
a93e255f | 929 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 930 | struct drm_device *dev = crtc->base.dev; |
9ca3ba01 | 931 | unsigned int best_error_ppm; |
ef9348c8 CML |
932 | intel_clock_t clock; |
933 | uint64_t m2; | |
934 | int found = false; | |
935 | ||
936 | memset(best_clock, 0, sizeof(*best_clock)); | |
9ca3ba01 | 937 | best_error_ppm = 1000000; |
ef9348c8 CML |
938 | |
939 | /* | |
940 | * Based on hardware doc, the n always set to 1, and m1 always | |
941 | * set to 2. If requires to support 200Mhz refclk, we need to | |
942 | * revisit this because n may not 1 anymore. | |
943 | */ | |
944 | clock.n = 1, clock.m1 = 2; | |
945 | target *= 5; /* fast clock */ | |
946 | ||
947 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { | |
948 | for (clock.p2 = limit->p2.p2_fast; | |
949 | clock.p2 >= limit->p2.p2_slow; | |
950 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { | |
9ca3ba01 | 951 | unsigned int error_ppm; |
ef9348c8 CML |
952 | |
953 | clock.p = clock.p1 * clock.p2; | |
954 | ||
955 | m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p * | |
956 | clock.n) << 22, refclk * clock.m1); | |
957 | ||
958 | if (m2 > INT_MAX/clock.m1) | |
959 | continue; | |
960 | ||
961 | clock.m2 = m2; | |
962 | ||
963 | chv_clock(refclk, &clock); | |
964 | ||
965 | if (!intel_PLL_is_valid(dev, limit, &clock)) | |
966 | continue; | |
967 | ||
9ca3ba01 ID |
968 | if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock, |
969 | best_error_ppm, &error_ppm)) | |
970 | continue; | |
971 | ||
972 | *best_clock = clock; | |
973 | best_error_ppm = error_ppm; | |
974 | found = true; | |
ef9348c8 CML |
975 | } |
976 | } | |
977 | ||
978 | return found; | |
979 | } | |
980 | ||
5ab7b0b7 ID |
981 | bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock, |
982 | intel_clock_t *best_clock) | |
983 | { | |
984 | int refclk = i9xx_get_refclk(crtc_state, 0); | |
985 | ||
986 | return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state, | |
987 | target_clock, refclk, NULL, best_clock); | |
988 | } | |
989 | ||
20ddf665 VS |
990 | bool intel_crtc_active(struct drm_crtc *crtc) |
991 | { | |
992 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
993 | ||
994 | /* Be paranoid as we can arrive here with only partial | |
995 | * state retrieved from the hardware during setup. | |
996 | * | |
241bfc38 | 997 | * We can ditch the adjusted_mode.crtc_clock check as soon |
20ddf665 VS |
998 | * as Haswell has gained clock readout/fastboot support. |
999 | * | |
66e514c1 | 1000 | * We can ditch the crtc->primary->fb check as soon as we can |
20ddf665 | 1001 | * properly reconstruct framebuffers. |
c3d1f436 MR |
1002 | * |
1003 | * FIXME: The intel_crtc->active here should be switched to | |
1004 | * crtc->state->active once we have proper CRTC states wired up | |
1005 | * for atomic. | |
20ddf665 | 1006 | */ |
c3d1f436 | 1007 | return intel_crtc->active && crtc->primary->state->fb && |
6e3c9717 | 1008 | intel_crtc->config->base.adjusted_mode.crtc_clock; |
20ddf665 VS |
1009 | } |
1010 | ||
a5c961d1 PZ |
1011 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
1012 | enum pipe pipe) | |
1013 | { | |
1014 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
1015 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1016 | ||
6e3c9717 | 1017 | return intel_crtc->config->cpu_transcoder; |
a5c961d1 PZ |
1018 | } |
1019 | ||
fbf49ea2 VS |
1020 | static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe) |
1021 | { | |
1022 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1023 | u32 reg = PIPEDSL(pipe); | |
1024 | u32 line1, line2; | |
1025 | u32 line_mask; | |
1026 | ||
1027 | if (IS_GEN2(dev)) | |
1028 | line_mask = DSL_LINEMASK_GEN2; | |
1029 | else | |
1030 | line_mask = DSL_LINEMASK_GEN3; | |
1031 | ||
1032 | line1 = I915_READ(reg) & line_mask; | |
1033 | mdelay(5); | |
1034 | line2 = I915_READ(reg) & line_mask; | |
1035 | ||
1036 | return line1 == line2; | |
1037 | } | |
1038 | ||
ab7ad7f6 KP |
1039 | /* |
1040 | * intel_wait_for_pipe_off - wait for pipe to turn off | |
575f7ab7 | 1041 | * @crtc: crtc whose pipe to wait for |
9d0498a2 JB |
1042 | * |
1043 | * After disabling a pipe, we can't wait for vblank in the usual way, | |
1044 | * spinning on the vblank interrupt status bit, since we won't actually | |
1045 | * see an interrupt when the pipe is disabled. | |
1046 | * | |
ab7ad7f6 KP |
1047 | * On Gen4 and above: |
1048 | * wait for the pipe register state bit to turn off | |
1049 | * | |
1050 | * Otherwise: | |
1051 | * wait for the display line value to settle (it usually | |
1052 | * ends up stopping at the start of the next frame). | |
58e10eb9 | 1053 | * |
9d0498a2 | 1054 | */ |
575f7ab7 | 1055 | static void intel_wait_for_pipe_off(struct intel_crtc *crtc) |
9d0498a2 | 1056 | { |
575f7ab7 | 1057 | struct drm_device *dev = crtc->base.dev; |
9d0498a2 | 1058 | struct drm_i915_private *dev_priv = dev->dev_private; |
6e3c9717 | 1059 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 1060 | enum pipe pipe = crtc->pipe; |
ab7ad7f6 KP |
1061 | |
1062 | if (INTEL_INFO(dev)->gen >= 4) { | |
702e7a56 | 1063 | int reg = PIPECONF(cpu_transcoder); |
ab7ad7f6 KP |
1064 | |
1065 | /* Wait for the Pipe State to go off */ | |
58e10eb9 CW |
1066 | if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, |
1067 | 100)) | |
284637d9 | 1068 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1069 | } else { |
ab7ad7f6 | 1070 | /* Wait for the display line to settle */ |
fbf49ea2 | 1071 | if (wait_for(pipe_dsl_stopped(dev, pipe), 100)) |
284637d9 | 1072 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1073 | } |
79e53945 JB |
1074 | } |
1075 | ||
b0ea7d37 DL |
1076 | /* |
1077 | * ibx_digital_port_connected - is the specified port connected? | |
1078 | * @dev_priv: i915 private structure | |
1079 | * @port: the port to test | |
1080 | * | |
1081 | * Returns true if @port is connected, false otherwise. | |
1082 | */ | |
1083 | bool ibx_digital_port_connected(struct drm_i915_private *dev_priv, | |
1084 | struct intel_digital_port *port) | |
1085 | { | |
1086 | u32 bit; | |
1087 | ||
c36346e3 | 1088 | if (HAS_PCH_IBX(dev_priv->dev)) { |
eba905b2 | 1089 | switch (port->port) { |
c36346e3 DL |
1090 | case PORT_B: |
1091 | bit = SDE_PORTB_HOTPLUG; | |
1092 | break; | |
1093 | case PORT_C: | |
1094 | bit = SDE_PORTC_HOTPLUG; | |
1095 | break; | |
1096 | case PORT_D: | |
1097 | bit = SDE_PORTD_HOTPLUG; | |
1098 | break; | |
1099 | default: | |
1100 | return true; | |
1101 | } | |
1102 | } else { | |
eba905b2 | 1103 | switch (port->port) { |
c36346e3 DL |
1104 | case PORT_B: |
1105 | bit = SDE_PORTB_HOTPLUG_CPT; | |
1106 | break; | |
1107 | case PORT_C: | |
1108 | bit = SDE_PORTC_HOTPLUG_CPT; | |
1109 | break; | |
1110 | case PORT_D: | |
1111 | bit = SDE_PORTD_HOTPLUG_CPT; | |
1112 | break; | |
1113 | default: | |
1114 | return true; | |
1115 | } | |
b0ea7d37 DL |
1116 | } |
1117 | ||
1118 | return I915_READ(SDEISR) & bit; | |
1119 | } | |
1120 | ||
b24e7179 JB |
1121 | static const char *state_string(bool enabled) |
1122 | { | |
1123 | return enabled ? "on" : "off"; | |
1124 | } | |
1125 | ||
1126 | /* Only for pre-ILK configs */ | |
55607e8a DV |
1127 | void assert_pll(struct drm_i915_private *dev_priv, |
1128 | enum pipe pipe, bool state) | |
b24e7179 JB |
1129 | { |
1130 | int reg; | |
1131 | u32 val; | |
1132 | bool cur_state; | |
1133 | ||
1134 | reg = DPLL(pipe); | |
1135 | val = I915_READ(reg); | |
1136 | cur_state = !!(val & DPLL_VCO_ENABLE); | |
e2c719b7 | 1137 | I915_STATE_WARN(cur_state != state, |
b24e7179 JB |
1138 | "PLL state assertion failure (expected %s, current %s)\n", |
1139 | state_string(state), state_string(cur_state)); | |
1140 | } | |
b24e7179 | 1141 | |
23538ef1 JN |
1142 | /* XXX: the dsi pll is shared between MIPI DSI ports */ |
1143 | static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state) | |
1144 | { | |
1145 | u32 val; | |
1146 | bool cur_state; | |
1147 | ||
a580516d | 1148 | mutex_lock(&dev_priv->sb_lock); |
23538ef1 | 1149 | val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); |
a580516d | 1150 | mutex_unlock(&dev_priv->sb_lock); |
23538ef1 JN |
1151 | |
1152 | cur_state = val & DSI_PLL_VCO_EN; | |
e2c719b7 | 1153 | I915_STATE_WARN(cur_state != state, |
23538ef1 JN |
1154 | "DSI PLL state assertion failure (expected %s, current %s)\n", |
1155 | state_string(state), state_string(cur_state)); | |
1156 | } | |
1157 | #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true) | |
1158 | #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false) | |
1159 | ||
55607e8a | 1160 | struct intel_shared_dpll * |
e2b78267 DV |
1161 | intel_crtc_to_shared_dpll(struct intel_crtc *crtc) |
1162 | { | |
1163 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
1164 | ||
6e3c9717 | 1165 | if (crtc->config->shared_dpll < 0) |
e2b78267 DV |
1166 | return NULL; |
1167 | ||
6e3c9717 | 1168 | return &dev_priv->shared_dplls[crtc->config->shared_dpll]; |
e2b78267 DV |
1169 | } |
1170 | ||
040484af | 1171 | /* For ILK+ */ |
55607e8a DV |
1172 | void assert_shared_dpll(struct drm_i915_private *dev_priv, |
1173 | struct intel_shared_dpll *pll, | |
1174 | bool state) | |
040484af | 1175 | { |
040484af | 1176 | bool cur_state; |
5358901f | 1177 | struct intel_dpll_hw_state hw_state; |
040484af | 1178 | |
92b27b08 | 1179 | if (WARN (!pll, |
46edb027 | 1180 | "asserting DPLL %s with no DPLL\n", state_string(state))) |
ee7b9f93 | 1181 | return; |
ee7b9f93 | 1182 | |
5358901f | 1183 | cur_state = pll->get_hw_state(dev_priv, pll, &hw_state); |
e2c719b7 | 1184 | I915_STATE_WARN(cur_state != state, |
5358901f DV |
1185 | "%s assertion failure (expected %s, current %s)\n", |
1186 | pll->name, state_string(state), state_string(cur_state)); | |
040484af | 1187 | } |
040484af JB |
1188 | |
1189 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, | |
1190 | enum pipe pipe, bool state) | |
1191 | { | |
1192 | int reg; | |
1193 | u32 val; | |
1194 | bool cur_state; | |
ad80a810 PZ |
1195 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1196 | pipe); | |
040484af | 1197 | |
affa9354 PZ |
1198 | if (HAS_DDI(dev_priv->dev)) { |
1199 | /* DDI does not have a specific FDI_TX register */ | |
ad80a810 | 1200 | reg = TRANS_DDI_FUNC_CTL(cpu_transcoder); |
bf507ef7 | 1201 | val = I915_READ(reg); |
ad80a810 | 1202 | cur_state = !!(val & TRANS_DDI_FUNC_ENABLE); |
bf507ef7 ED |
1203 | } else { |
1204 | reg = FDI_TX_CTL(pipe); | |
1205 | val = I915_READ(reg); | |
1206 | cur_state = !!(val & FDI_TX_ENABLE); | |
1207 | } | |
e2c719b7 | 1208 | I915_STATE_WARN(cur_state != state, |
040484af JB |
1209 | "FDI TX state assertion failure (expected %s, current %s)\n", |
1210 | state_string(state), state_string(cur_state)); | |
1211 | } | |
1212 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) | |
1213 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) | |
1214 | ||
1215 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, | |
1216 | enum pipe pipe, bool state) | |
1217 | { | |
1218 | int reg; | |
1219 | u32 val; | |
1220 | bool cur_state; | |
1221 | ||
d63fa0dc PZ |
1222 | reg = FDI_RX_CTL(pipe); |
1223 | val = I915_READ(reg); | |
1224 | cur_state = !!(val & FDI_RX_ENABLE); | |
e2c719b7 | 1225 | I915_STATE_WARN(cur_state != state, |
040484af JB |
1226 | "FDI RX state assertion failure (expected %s, current %s)\n", |
1227 | state_string(state), state_string(cur_state)); | |
1228 | } | |
1229 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) | |
1230 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) | |
1231 | ||
1232 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, | |
1233 | enum pipe pipe) | |
1234 | { | |
1235 | int reg; | |
1236 | u32 val; | |
1237 | ||
1238 | /* ILK FDI PLL is always enabled */ | |
3d13ef2e | 1239 | if (INTEL_INFO(dev_priv->dev)->gen == 5) |
040484af JB |
1240 | return; |
1241 | ||
bf507ef7 | 1242 | /* On Haswell, DDI ports are responsible for the FDI PLL setup */ |
affa9354 | 1243 | if (HAS_DDI(dev_priv->dev)) |
bf507ef7 ED |
1244 | return; |
1245 | ||
040484af JB |
1246 | reg = FDI_TX_CTL(pipe); |
1247 | val = I915_READ(reg); | |
e2c719b7 | 1248 | I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); |
040484af JB |
1249 | } |
1250 | ||
55607e8a DV |
1251 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, |
1252 | enum pipe pipe, bool state) | |
040484af JB |
1253 | { |
1254 | int reg; | |
1255 | u32 val; | |
55607e8a | 1256 | bool cur_state; |
040484af JB |
1257 | |
1258 | reg = FDI_RX_CTL(pipe); | |
1259 | val = I915_READ(reg); | |
55607e8a | 1260 | cur_state = !!(val & FDI_RX_PLL_ENABLE); |
e2c719b7 | 1261 | I915_STATE_WARN(cur_state != state, |
55607e8a DV |
1262 | "FDI RX PLL assertion failure (expected %s, current %s)\n", |
1263 | state_string(state), state_string(cur_state)); | |
040484af JB |
1264 | } |
1265 | ||
b680c37a DV |
1266 | void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
1267 | enum pipe pipe) | |
ea0760cf | 1268 | { |
bedd4dba JN |
1269 | struct drm_device *dev = dev_priv->dev; |
1270 | int pp_reg; | |
ea0760cf JB |
1271 | u32 val; |
1272 | enum pipe panel_pipe = PIPE_A; | |
0de3b485 | 1273 | bool locked = true; |
ea0760cf | 1274 | |
bedd4dba JN |
1275 | if (WARN_ON(HAS_DDI(dev))) |
1276 | return; | |
1277 | ||
1278 | if (HAS_PCH_SPLIT(dev)) { | |
1279 | u32 port_sel; | |
1280 | ||
ea0760cf | 1281 | pp_reg = PCH_PP_CONTROL; |
bedd4dba JN |
1282 | port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK; |
1283 | ||
1284 | if (port_sel == PANEL_PORT_SELECT_LVDS && | |
1285 | I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT) | |
1286 | panel_pipe = PIPE_B; | |
1287 | /* XXX: else fix for eDP */ | |
1288 | } else if (IS_VALLEYVIEW(dev)) { | |
1289 | /* presumably write lock depends on pipe, not port select */ | |
1290 | pp_reg = VLV_PIPE_PP_CONTROL(pipe); | |
1291 | panel_pipe = pipe; | |
ea0760cf JB |
1292 | } else { |
1293 | pp_reg = PP_CONTROL; | |
bedd4dba JN |
1294 | if (I915_READ(LVDS) & LVDS_PIPEB_SELECT) |
1295 | panel_pipe = PIPE_B; | |
ea0760cf JB |
1296 | } |
1297 | ||
1298 | val = I915_READ(pp_reg); | |
1299 | if (!(val & PANEL_POWER_ON) || | |
ec49ba2d | 1300 | ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS)) |
ea0760cf JB |
1301 | locked = false; |
1302 | ||
e2c719b7 | 1303 | I915_STATE_WARN(panel_pipe == pipe && locked, |
ea0760cf | 1304 | "panel assertion failure, pipe %c regs locked\n", |
9db4a9c7 | 1305 | pipe_name(pipe)); |
ea0760cf JB |
1306 | } |
1307 | ||
93ce0ba6 JN |
1308 | static void assert_cursor(struct drm_i915_private *dev_priv, |
1309 | enum pipe pipe, bool state) | |
1310 | { | |
1311 | struct drm_device *dev = dev_priv->dev; | |
1312 | bool cur_state; | |
1313 | ||
d9d82081 | 1314 | if (IS_845G(dev) || IS_I865G(dev)) |
93ce0ba6 | 1315 | cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE; |
d9d82081 | 1316 | else |
5efb3e28 | 1317 | cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; |
93ce0ba6 | 1318 | |
e2c719b7 | 1319 | I915_STATE_WARN(cur_state != state, |
93ce0ba6 JN |
1320 | "cursor on pipe %c assertion failure (expected %s, current %s)\n", |
1321 | pipe_name(pipe), state_string(state), state_string(cur_state)); | |
1322 | } | |
1323 | #define assert_cursor_enabled(d, p) assert_cursor(d, p, true) | |
1324 | #define assert_cursor_disabled(d, p) assert_cursor(d, p, false) | |
1325 | ||
b840d907 JB |
1326 | void assert_pipe(struct drm_i915_private *dev_priv, |
1327 | enum pipe pipe, bool state) | |
b24e7179 JB |
1328 | { |
1329 | int reg; | |
1330 | u32 val; | |
63d7bbe9 | 1331 | bool cur_state; |
702e7a56 PZ |
1332 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1333 | pipe); | |
b24e7179 | 1334 | |
b6b5d049 VS |
1335 | /* if we need the pipe quirk it must be always on */ |
1336 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
1337 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
8e636784 DV |
1338 | state = true; |
1339 | ||
f458ebbc | 1340 | if (!intel_display_power_is_enabled(dev_priv, |
b97186f0 | 1341 | POWER_DOMAIN_TRANSCODER(cpu_transcoder))) { |
69310161 PZ |
1342 | cur_state = false; |
1343 | } else { | |
1344 | reg = PIPECONF(cpu_transcoder); | |
1345 | val = I915_READ(reg); | |
1346 | cur_state = !!(val & PIPECONF_ENABLE); | |
1347 | } | |
1348 | ||
e2c719b7 | 1349 | I915_STATE_WARN(cur_state != state, |
63d7bbe9 | 1350 | "pipe %c assertion failure (expected %s, current %s)\n", |
9db4a9c7 | 1351 | pipe_name(pipe), state_string(state), state_string(cur_state)); |
b24e7179 JB |
1352 | } |
1353 | ||
931872fc CW |
1354 | static void assert_plane(struct drm_i915_private *dev_priv, |
1355 | enum plane plane, bool state) | |
b24e7179 JB |
1356 | { |
1357 | int reg; | |
1358 | u32 val; | |
931872fc | 1359 | bool cur_state; |
b24e7179 JB |
1360 | |
1361 | reg = DSPCNTR(plane); | |
1362 | val = I915_READ(reg); | |
931872fc | 1363 | cur_state = !!(val & DISPLAY_PLANE_ENABLE); |
e2c719b7 | 1364 | I915_STATE_WARN(cur_state != state, |
931872fc CW |
1365 | "plane %c assertion failure (expected %s, current %s)\n", |
1366 | plane_name(plane), state_string(state), state_string(cur_state)); | |
b24e7179 JB |
1367 | } |
1368 | ||
931872fc CW |
1369 | #define assert_plane_enabled(d, p) assert_plane(d, p, true) |
1370 | #define assert_plane_disabled(d, p) assert_plane(d, p, false) | |
1371 | ||
b24e7179 JB |
1372 | static void assert_planes_disabled(struct drm_i915_private *dev_priv, |
1373 | enum pipe pipe) | |
1374 | { | |
653e1026 | 1375 | struct drm_device *dev = dev_priv->dev; |
b24e7179 JB |
1376 | int reg, i; |
1377 | u32 val; | |
1378 | int cur_pipe; | |
1379 | ||
653e1026 VS |
1380 | /* Primary planes are fixed to pipes on gen4+ */ |
1381 | if (INTEL_INFO(dev)->gen >= 4) { | |
28c05794 AJ |
1382 | reg = DSPCNTR(pipe); |
1383 | val = I915_READ(reg); | |
e2c719b7 | 1384 | I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE, |
28c05794 AJ |
1385 | "plane %c assertion failure, should be disabled but not\n", |
1386 | plane_name(pipe)); | |
19ec1358 | 1387 | return; |
28c05794 | 1388 | } |
19ec1358 | 1389 | |
b24e7179 | 1390 | /* Need to check both planes against the pipe */ |
055e393f | 1391 | for_each_pipe(dev_priv, i) { |
b24e7179 JB |
1392 | reg = DSPCNTR(i); |
1393 | val = I915_READ(reg); | |
1394 | cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> | |
1395 | DISPPLANE_SEL_PIPE_SHIFT; | |
e2c719b7 | 1396 | I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, |
9db4a9c7 JB |
1397 | "plane %c assertion failure, should be off on pipe %c but is still active\n", |
1398 | plane_name(i), pipe_name(pipe)); | |
b24e7179 JB |
1399 | } |
1400 | } | |
1401 | ||
19332d7a JB |
1402 | static void assert_sprites_disabled(struct drm_i915_private *dev_priv, |
1403 | enum pipe pipe) | |
1404 | { | |
20674eef | 1405 | struct drm_device *dev = dev_priv->dev; |
1fe47785 | 1406 | int reg, sprite; |
19332d7a JB |
1407 | u32 val; |
1408 | ||
7feb8b88 | 1409 | if (INTEL_INFO(dev)->gen >= 9) { |
3bdcfc0c | 1410 | for_each_sprite(dev_priv, pipe, sprite) { |
7feb8b88 | 1411 | val = I915_READ(PLANE_CTL(pipe, sprite)); |
e2c719b7 | 1412 | I915_STATE_WARN(val & PLANE_CTL_ENABLE, |
7feb8b88 DL |
1413 | "plane %d assertion failure, should be off on pipe %c but is still active\n", |
1414 | sprite, pipe_name(pipe)); | |
1415 | } | |
1416 | } else if (IS_VALLEYVIEW(dev)) { | |
3bdcfc0c | 1417 | for_each_sprite(dev_priv, pipe, sprite) { |
1fe47785 | 1418 | reg = SPCNTR(pipe, sprite); |
20674eef | 1419 | val = I915_READ(reg); |
e2c719b7 | 1420 | I915_STATE_WARN(val & SP_ENABLE, |
20674eef | 1421 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
1fe47785 | 1422 | sprite_name(pipe, sprite), pipe_name(pipe)); |
20674eef VS |
1423 | } |
1424 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
1425 | reg = SPRCTL(pipe); | |
19332d7a | 1426 | val = I915_READ(reg); |
e2c719b7 | 1427 | I915_STATE_WARN(val & SPRITE_ENABLE, |
06da8da2 | 1428 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef VS |
1429 | plane_name(pipe), pipe_name(pipe)); |
1430 | } else if (INTEL_INFO(dev)->gen >= 5) { | |
1431 | reg = DVSCNTR(pipe); | |
19332d7a | 1432 | val = I915_READ(reg); |
e2c719b7 | 1433 | I915_STATE_WARN(val & DVS_ENABLE, |
06da8da2 | 1434 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef | 1435 | plane_name(pipe), pipe_name(pipe)); |
19332d7a JB |
1436 | } |
1437 | } | |
1438 | ||
08c71e5e VS |
1439 | static void assert_vblank_disabled(struct drm_crtc *crtc) |
1440 | { | |
e2c719b7 | 1441 | if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0)) |
08c71e5e VS |
1442 | drm_crtc_vblank_put(crtc); |
1443 | } | |
1444 | ||
89eff4be | 1445 | static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv) |
92f2584a JB |
1446 | { |
1447 | u32 val; | |
1448 | bool enabled; | |
1449 | ||
e2c719b7 | 1450 | I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev))); |
9d82aa17 | 1451 | |
92f2584a JB |
1452 | val = I915_READ(PCH_DREF_CONTROL); |
1453 | enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK | | |
1454 | DREF_SUPERSPREAD_SOURCE_MASK)); | |
e2c719b7 | 1455 | I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n"); |
92f2584a JB |
1456 | } |
1457 | ||
ab9412ba DV |
1458 | static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, |
1459 | enum pipe pipe) | |
92f2584a JB |
1460 | { |
1461 | int reg; | |
1462 | u32 val; | |
1463 | bool enabled; | |
1464 | ||
ab9412ba | 1465 | reg = PCH_TRANSCONF(pipe); |
92f2584a JB |
1466 | val = I915_READ(reg); |
1467 | enabled = !!(val & TRANS_ENABLE); | |
e2c719b7 | 1468 | I915_STATE_WARN(enabled, |
9db4a9c7 JB |
1469 | "transcoder assertion failed, should be off on pipe %c but is still active\n", |
1470 | pipe_name(pipe)); | |
92f2584a JB |
1471 | } |
1472 | ||
4e634389 KP |
1473 | static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, |
1474 | enum pipe pipe, u32 port_sel, u32 val) | |
f0575e92 KP |
1475 | { |
1476 | if ((val & DP_PORT_EN) == 0) | |
1477 | return false; | |
1478 | ||
1479 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1480 | u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe); | |
1481 | u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg); | |
1482 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) | |
1483 | return false; | |
44f37d1f CML |
1484 | } else if (IS_CHERRYVIEW(dev_priv->dev)) { |
1485 | if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe)) | |
1486 | return false; | |
f0575e92 KP |
1487 | } else { |
1488 | if ((val & DP_PIPE_MASK) != (pipe << 30)) | |
1489 | return false; | |
1490 | } | |
1491 | return true; | |
1492 | } | |
1493 | ||
1519b995 KP |
1494 | static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, |
1495 | enum pipe pipe, u32 val) | |
1496 | { | |
dc0fa718 | 1497 | if ((val & SDVO_ENABLE) == 0) |
1519b995 KP |
1498 | return false; |
1499 | ||
1500 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
dc0fa718 | 1501 | if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe)) |
1519b995 | 1502 | return false; |
44f37d1f CML |
1503 | } else if (IS_CHERRYVIEW(dev_priv->dev)) { |
1504 | if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe)) | |
1505 | return false; | |
1519b995 | 1506 | } else { |
dc0fa718 | 1507 | if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe)) |
1519b995 KP |
1508 | return false; |
1509 | } | |
1510 | return true; | |
1511 | } | |
1512 | ||
1513 | static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, | |
1514 | enum pipe pipe, u32 val) | |
1515 | { | |
1516 | if ((val & LVDS_PORT_EN) == 0) | |
1517 | return false; | |
1518 | ||
1519 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1520 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1521 | return false; | |
1522 | } else { | |
1523 | if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) | |
1524 | return false; | |
1525 | } | |
1526 | return true; | |
1527 | } | |
1528 | ||
1529 | static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, | |
1530 | enum pipe pipe, u32 val) | |
1531 | { | |
1532 | if ((val & ADPA_DAC_ENABLE) == 0) | |
1533 | return false; | |
1534 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1535 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1536 | return false; | |
1537 | } else { | |
1538 | if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) | |
1539 | return false; | |
1540 | } | |
1541 | return true; | |
1542 | } | |
1543 | ||
291906f1 | 1544 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
f0575e92 | 1545 | enum pipe pipe, int reg, u32 port_sel) |
291906f1 | 1546 | { |
47a05eca | 1547 | u32 val = I915_READ(reg); |
e2c719b7 | 1548 | I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
291906f1 | 1549 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1550 | reg, pipe_name(pipe)); |
de9a35ab | 1551 | |
e2c719b7 | 1552 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0 |
75c5da27 | 1553 | && (val & DP_PIPEB_SELECT), |
de9a35ab | 1554 | "IBX PCH dp port still using transcoder B\n"); |
291906f1 JB |
1555 | } |
1556 | ||
1557 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, | |
1558 | enum pipe pipe, int reg) | |
1559 | { | |
47a05eca | 1560 | u32 val = I915_READ(reg); |
e2c719b7 | 1561 | I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val), |
23c99e77 | 1562 | "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1563 | reg, pipe_name(pipe)); |
de9a35ab | 1564 | |
e2c719b7 | 1565 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0 |
75c5da27 | 1566 | && (val & SDVO_PIPE_B_SELECT), |
de9a35ab | 1567 | "IBX PCH hdmi port still using transcoder B\n"); |
291906f1 JB |
1568 | } |
1569 | ||
1570 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, | |
1571 | enum pipe pipe) | |
1572 | { | |
1573 | int reg; | |
1574 | u32 val; | |
291906f1 | 1575 | |
f0575e92 KP |
1576 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
1577 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); | |
1578 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); | |
291906f1 JB |
1579 | |
1580 | reg = PCH_ADPA; | |
1581 | val = I915_READ(reg); | |
e2c719b7 | 1582 | I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1583 | "PCH VGA enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1584 | pipe_name(pipe)); |
291906f1 JB |
1585 | |
1586 | reg = PCH_LVDS; | |
1587 | val = I915_READ(reg); | |
e2c719b7 | 1588 | I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1589 | "PCH LVDS enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1590 | pipe_name(pipe)); |
291906f1 | 1591 | |
e2debe91 PZ |
1592 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB); |
1593 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC); | |
1594 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID); | |
291906f1 JB |
1595 | } |
1596 | ||
40e9cf64 JB |
1597 | static void intel_init_dpio(struct drm_device *dev) |
1598 | { | |
1599 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1600 | ||
1601 | if (!IS_VALLEYVIEW(dev)) | |
1602 | return; | |
1603 | ||
a09caddd CML |
1604 | /* |
1605 | * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C), | |
1606 | * CHV x1 PHY (DP/HDMI D) | |
1607 | * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C) | |
1608 | */ | |
1609 | if (IS_CHERRYVIEW(dev)) { | |
1610 | DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2; | |
1611 | DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO; | |
1612 | } else { | |
1613 | DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO; | |
1614 | } | |
5382f5f3 JB |
1615 | } |
1616 | ||
d288f65f | 1617 | static void vlv_enable_pll(struct intel_crtc *crtc, |
5cec258b | 1618 | const struct intel_crtc_state *pipe_config) |
87442f73 | 1619 | { |
426115cf DV |
1620 | struct drm_device *dev = crtc->base.dev; |
1621 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1622 | int reg = DPLL(crtc->pipe); | |
d288f65f | 1623 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
87442f73 | 1624 | |
426115cf | 1625 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87442f73 DV |
1626 | |
1627 | /* No really, not for ILK+ */ | |
1628 | BUG_ON(!IS_VALLEYVIEW(dev_priv->dev)); | |
1629 | ||
1630 | /* PLL is protected by panel, make sure we can write it */ | |
6a9e7363 | 1631 | if (IS_MOBILE(dev_priv->dev)) |
426115cf | 1632 | assert_panel_unlocked(dev_priv, crtc->pipe); |
87442f73 | 1633 | |
426115cf DV |
1634 | I915_WRITE(reg, dpll); |
1635 | POSTING_READ(reg); | |
1636 | udelay(150); | |
1637 | ||
1638 | if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) | |
1639 | DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe); | |
1640 | ||
d288f65f | 1641 | I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md); |
426115cf | 1642 | POSTING_READ(DPLL_MD(crtc->pipe)); |
87442f73 DV |
1643 | |
1644 | /* We do this three times for luck */ | |
426115cf | 1645 | I915_WRITE(reg, dpll); |
87442f73 DV |
1646 | POSTING_READ(reg); |
1647 | udelay(150); /* wait for warmup */ | |
426115cf | 1648 | I915_WRITE(reg, dpll); |
87442f73 DV |
1649 | POSTING_READ(reg); |
1650 | udelay(150); /* wait for warmup */ | |
426115cf | 1651 | I915_WRITE(reg, dpll); |
87442f73 DV |
1652 | POSTING_READ(reg); |
1653 | udelay(150); /* wait for warmup */ | |
1654 | } | |
1655 | ||
d288f65f | 1656 | static void chv_enable_pll(struct intel_crtc *crtc, |
5cec258b | 1657 | const struct intel_crtc_state *pipe_config) |
9d556c99 CML |
1658 | { |
1659 | struct drm_device *dev = crtc->base.dev; | |
1660 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1661 | int pipe = crtc->pipe; | |
1662 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
9d556c99 CML |
1663 | u32 tmp; |
1664 | ||
1665 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
1666 | ||
1667 | BUG_ON(!IS_CHERRYVIEW(dev_priv->dev)); | |
1668 | ||
a580516d | 1669 | mutex_lock(&dev_priv->sb_lock); |
9d556c99 CML |
1670 | |
1671 | /* Enable back the 10bit clock to display controller */ | |
1672 | tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1673 | tmp |= DPIO_DCLKP_EN; | |
1674 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp); | |
1675 | ||
54433e91 VS |
1676 | mutex_unlock(&dev_priv->sb_lock); |
1677 | ||
9d556c99 CML |
1678 | /* |
1679 | * Need to wait > 100ns between dclkp clock enable bit and PLL enable. | |
1680 | */ | |
1681 | udelay(1); | |
1682 | ||
1683 | /* Enable PLL */ | |
d288f65f | 1684 | I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); |
9d556c99 CML |
1685 | |
1686 | /* Check PLL is locked */ | |
a11b0703 | 1687 | if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) |
9d556c99 CML |
1688 | DRM_ERROR("PLL %d failed to lock\n", pipe); |
1689 | ||
a11b0703 | 1690 | /* not sure when this should be written */ |
d288f65f | 1691 | I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); |
a11b0703 | 1692 | POSTING_READ(DPLL_MD(pipe)); |
9d556c99 CML |
1693 | } |
1694 | ||
1c4e0274 VS |
1695 | static int intel_num_dvo_pipes(struct drm_device *dev) |
1696 | { | |
1697 | struct intel_crtc *crtc; | |
1698 | int count = 0; | |
1699 | ||
1700 | for_each_intel_crtc(dev, crtc) | |
3538b9df | 1701 | count += crtc->base.state->active && |
409ee761 | 1702 | intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO); |
1c4e0274 VS |
1703 | |
1704 | return count; | |
1705 | } | |
1706 | ||
66e3d5c0 | 1707 | static void i9xx_enable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1708 | { |
66e3d5c0 DV |
1709 | struct drm_device *dev = crtc->base.dev; |
1710 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1711 | int reg = DPLL(crtc->pipe); | |
6e3c9717 | 1712 | u32 dpll = crtc->config->dpll_hw_state.dpll; |
63d7bbe9 | 1713 | |
66e3d5c0 | 1714 | assert_pipe_disabled(dev_priv, crtc->pipe); |
58c6eaa2 | 1715 | |
63d7bbe9 | 1716 | /* No really, not for ILK+ */ |
3d13ef2e | 1717 | BUG_ON(INTEL_INFO(dev)->gen >= 5); |
63d7bbe9 JB |
1718 | |
1719 | /* PLL is protected by panel, make sure we can write it */ | |
66e3d5c0 DV |
1720 | if (IS_MOBILE(dev) && !IS_I830(dev)) |
1721 | assert_panel_unlocked(dev_priv, crtc->pipe); | |
63d7bbe9 | 1722 | |
1c4e0274 VS |
1723 | /* Enable DVO 2x clock on both PLLs if necessary */ |
1724 | if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) { | |
1725 | /* | |
1726 | * It appears to be important that we don't enable this | |
1727 | * for the current pipe before otherwise configuring the | |
1728 | * PLL. No idea how this should be handled if multiple | |
1729 | * DVO outputs are enabled simultaneosly. | |
1730 | */ | |
1731 | dpll |= DPLL_DVO_2X_MODE; | |
1732 | I915_WRITE(DPLL(!crtc->pipe), | |
1733 | I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE); | |
1734 | } | |
66e3d5c0 DV |
1735 | |
1736 | /* Wait for the clocks to stabilize. */ | |
1737 | POSTING_READ(reg); | |
1738 | udelay(150); | |
1739 | ||
1740 | if (INTEL_INFO(dev)->gen >= 4) { | |
1741 | I915_WRITE(DPLL_MD(crtc->pipe), | |
6e3c9717 | 1742 | crtc->config->dpll_hw_state.dpll_md); |
66e3d5c0 DV |
1743 | } else { |
1744 | /* The pixel multiplier can only be updated once the | |
1745 | * DPLL is enabled and the clocks are stable. | |
1746 | * | |
1747 | * So write it again. | |
1748 | */ | |
1749 | I915_WRITE(reg, dpll); | |
1750 | } | |
63d7bbe9 JB |
1751 | |
1752 | /* We do this three times for luck */ | |
66e3d5c0 | 1753 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1754 | POSTING_READ(reg); |
1755 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1756 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1757 | POSTING_READ(reg); |
1758 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1759 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1760 | POSTING_READ(reg); |
1761 | udelay(150); /* wait for warmup */ | |
1762 | } | |
1763 | ||
1764 | /** | |
50b44a44 | 1765 | * i9xx_disable_pll - disable a PLL |
63d7bbe9 JB |
1766 | * @dev_priv: i915 private structure |
1767 | * @pipe: pipe PLL to disable | |
1768 | * | |
1769 | * Disable the PLL for @pipe, making sure the pipe is off first. | |
1770 | * | |
1771 | * Note! This is for pre-ILK only. | |
1772 | */ | |
1c4e0274 | 1773 | static void i9xx_disable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1774 | { |
1c4e0274 VS |
1775 | struct drm_device *dev = crtc->base.dev; |
1776 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1777 | enum pipe pipe = crtc->pipe; | |
1778 | ||
1779 | /* Disable DVO 2x clock on both PLLs if necessary */ | |
1780 | if (IS_I830(dev) && | |
409ee761 | 1781 | intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) && |
3538b9df | 1782 | !intel_num_dvo_pipes(dev)) { |
1c4e0274 VS |
1783 | I915_WRITE(DPLL(PIPE_B), |
1784 | I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE); | |
1785 | I915_WRITE(DPLL(PIPE_A), | |
1786 | I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE); | |
1787 | } | |
1788 | ||
b6b5d049 VS |
1789 | /* Don't disable pipe or pipe PLLs if needed */ |
1790 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
1791 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
63d7bbe9 JB |
1792 | return; |
1793 | ||
1794 | /* Make sure the pipe isn't still relying on us */ | |
1795 | assert_pipe_disabled(dev_priv, pipe); | |
1796 | ||
50b44a44 DV |
1797 | I915_WRITE(DPLL(pipe), 0); |
1798 | POSTING_READ(DPLL(pipe)); | |
63d7bbe9 JB |
1799 | } |
1800 | ||
f6071166 JB |
1801 | static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
1802 | { | |
1803 | u32 val = 0; | |
1804 | ||
1805 | /* Make sure the pipe isn't still relying on us */ | |
1806 | assert_pipe_disabled(dev_priv, pipe); | |
1807 | ||
e5cbfbfb ID |
1808 | /* |
1809 | * Leave integrated clock source and reference clock enabled for pipe B. | |
1810 | * The latter is needed for VGA hotplug / manual detection. | |
1811 | */ | |
f6071166 | 1812 | if (pipe == PIPE_B) |
e5cbfbfb | 1813 | val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV; |
f6071166 JB |
1814 | I915_WRITE(DPLL(pipe), val); |
1815 | POSTING_READ(DPLL(pipe)); | |
076ed3b2 CML |
1816 | |
1817 | } | |
1818 | ||
1819 | static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) | |
1820 | { | |
d752048d | 1821 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
076ed3b2 CML |
1822 | u32 val; |
1823 | ||
a11b0703 VS |
1824 | /* Make sure the pipe isn't still relying on us */ |
1825 | assert_pipe_disabled(dev_priv, pipe); | |
076ed3b2 | 1826 | |
a11b0703 | 1827 | /* Set PLL en = 0 */ |
d17ec4ce | 1828 | val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV; |
a11b0703 VS |
1829 | if (pipe != PIPE_A) |
1830 | val |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
1831 | I915_WRITE(DPLL(pipe), val); | |
1832 | POSTING_READ(DPLL(pipe)); | |
d752048d | 1833 | |
a580516d | 1834 | mutex_lock(&dev_priv->sb_lock); |
d752048d VS |
1835 | |
1836 | /* Disable 10bit clock to display controller */ | |
1837 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1838 | val &= ~DPIO_DCLKP_EN; | |
1839 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val); | |
1840 | ||
61407f6d VS |
1841 | /* disable left/right clock distribution */ |
1842 | if (pipe != PIPE_B) { | |
1843 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); | |
1844 | val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); | |
1845 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); | |
1846 | } else { | |
1847 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); | |
1848 | val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); | |
1849 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); | |
1850 | } | |
1851 | ||
a580516d | 1852 | mutex_unlock(&dev_priv->sb_lock); |
f6071166 JB |
1853 | } |
1854 | ||
e4607fcf | 1855 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, |
9b6de0a1 VS |
1856 | struct intel_digital_port *dport, |
1857 | unsigned int expected_mask) | |
89b667f8 JB |
1858 | { |
1859 | u32 port_mask; | |
00fc31b7 | 1860 | int dpll_reg; |
89b667f8 | 1861 | |
e4607fcf CML |
1862 | switch (dport->port) { |
1863 | case PORT_B: | |
89b667f8 | 1864 | port_mask = DPLL_PORTB_READY_MASK; |
00fc31b7 | 1865 | dpll_reg = DPLL(0); |
e4607fcf CML |
1866 | break; |
1867 | case PORT_C: | |
89b667f8 | 1868 | port_mask = DPLL_PORTC_READY_MASK; |
00fc31b7 | 1869 | dpll_reg = DPLL(0); |
9b6de0a1 | 1870 | expected_mask <<= 4; |
00fc31b7 CML |
1871 | break; |
1872 | case PORT_D: | |
1873 | port_mask = DPLL_PORTD_READY_MASK; | |
1874 | dpll_reg = DPIO_PHY_STATUS; | |
e4607fcf CML |
1875 | break; |
1876 | default: | |
1877 | BUG(); | |
1878 | } | |
89b667f8 | 1879 | |
9b6de0a1 VS |
1880 | if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000)) |
1881 | WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n", | |
1882 | port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask); | |
89b667f8 JB |
1883 | } |
1884 | ||
b14b1055 DV |
1885 | static void intel_prepare_shared_dpll(struct intel_crtc *crtc) |
1886 | { | |
1887 | struct drm_device *dev = crtc->base.dev; | |
1888 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1889 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); | |
1890 | ||
be19f0ff CW |
1891 | if (WARN_ON(pll == NULL)) |
1892 | return; | |
1893 | ||
3e369b76 | 1894 | WARN_ON(!pll->config.crtc_mask); |
b14b1055 DV |
1895 | if (pll->active == 0) { |
1896 | DRM_DEBUG_DRIVER("setting up %s\n", pll->name); | |
1897 | WARN_ON(pll->on); | |
1898 | assert_shared_dpll_disabled(dev_priv, pll); | |
1899 | ||
1900 | pll->mode_set(dev_priv, pll); | |
1901 | } | |
1902 | } | |
1903 | ||
92f2584a | 1904 | /** |
85b3894f | 1905 | * intel_enable_shared_dpll - enable PCH PLL |
92f2584a JB |
1906 | * @dev_priv: i915 private structure |
1907 | * @pipe: pipe PLL to enable | |
1908 | * | |
1909 | * The PCH PLL needs to be enabled before the PCH transcoder, since it | |
1910 | * drives the transcoder clock. | |
1911 | */ | |
85b3894f | 1912 | static void intel_enable_shared_dpll(struct intel_crtc *crtc) |
92f2584a | 1913 | { |
3d13ef2e DL |
1914 | struct drm_device *dev = crtc->base.dev; |
1915 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2b78267 | 1916 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
92f2584a | 1917 | |
87a875bb | 1918 | if (WARN_ON(pll == NULL)) |
48da64a8 CW |
1919 | return; |
1920 | ||
3e369b76 | 1921 | if (WARN_ON(pll->config.crtc_mask == 0)) |
48da64a8 | 1922 | return; |
ee7b9f93 | 1923 | |
74dd6928 | 1924 | DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n", |
46edb027 | 1925 | pll->name, pll->active, pll->on, |
e2b78267 | 1926 | crtc->base.base.id); |
92f2584a | 1927 | |
cdbd2316 DV |
1928 | if (pll->active++) { |
1929 | WARN_ON(!pll->on); | |
e9d6944e | 1930 | assert_shared_dpll_enabled(dev_priv, pll); |
ee7b9f93 JB |
1931 | return; |
1932 | } | |
f4a091c7 | 1933 | WARN_ON(pll->on); |
ee7b9f93 | 1934 | |
bd2bb1b9 PZ |
1935 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); |
1936 | ||
46edb027 | 1937 | DRM_DEBUG_KMS("enabling %s\n", pll->name); |
e7b903d2 | 1938 | pll->enable(dev_priv, pll); |
ee7b9f93 | 1939 | pll->on = true; |
92f2584a JB |
1940 | } |
1941 | ||
f6daaec2 | 1942 | static void intel_disable_shared_dpll(struct intel_crtc *crtc) |
92f2584a | 1943 | { |
3d13ef2e DL |
1944 | struct drm_device *dev = crtc->base.dev; |
1945 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2b78267 | 1946 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
4c609cb8 | 1947 | |
92f2584a | 1948 | /* PCH only available on ILK+ */ |
3d13ef2e | 1949 | BUG_ON(INTEL_INFO(dev)->gen < 5); |
87a875bb | 1950 | if (WARN_ON(pll == NULL)) |
ee7b9f93 | 1951 | return; |
92f2584a | 1952 | |
3e369b76 | 1953 | if (WARN_ON(pll->config.crtc_mask == 0)) |
48da64a8 | 1954 | return; |
7a419866 | 1955 | |
46edb027 DV |
1956 | DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n", |
1957 | pll->name, pll->active, pll->on, | |
e2b78267 | 1958 | crtc->base.base.id); |
7a419866 | 1959 | |
48da64a8 | 1960 | if (WARN_ON(pll->active == 0)) { |
e9d6944e | 1961 | assert_shared_dpll_disabled(dev_priv, pll); |
48da64a8 CW |
1962 | return; |
1963 | } | |
1964 | ||
e9d6944e | 1965 | assert_shared_dpll_enabled(dev_priv, pll); |
f4a091c7 | 1966 | WARN_ON(!pll->on); |
cdbd2316 | 1967 | if (--pll->active) |
7a419866 | 1968 | return; |
ee7b9f93 | 1969 | |
46edb027 | 1970 | DRM_DEBUG_KMS("disabling %s\n", pll->name); |
e7b903d2 | 1971 | pll->disable(dev_priv, pll); |
ee7b9f93 | 1972 | pll->on = false; |
bd2bb1b9 PZ |
1973 | |
1974 | intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); | |
92f2584a JB |
1975 | } |
1976 | ||
b8a4f404 PZ |
1977 | static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
1978 | enum pipe pipe) | |
040484af | 1979 | { |
23670b32 | 1980 | struct drm_device *dev = dev_priv->dev; |
7c26e5c6 | 1981 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
e2b78267 | 1982 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
23670b32 | 1983 | uint32_t reg, val, pipeconf_val; |
040484af JB |
1984 | |
1985 | /* PCH only available on ILK+ */ | |
55522f37 | 1986 | BUG_ON(!HAS_PCH_SPLIT(dev)); |
040484af JB |
1987 | |
1988 | /* Make sure PCH DPLL is enabled */ | |
e72f9fbf | 1989 | assert_shared_dpll_enabled(dev_priv, |
e9d6944e | 1990 | intel_crtc_to_shared_dpll(intel_crtc)); |
040484af JB |
1991 | |
1992 | /* FDI must be feeding us bits for PCH ports */ | |
1993 | assert_fdi_tx_enabled(dev_priv, pipe); | |
1994 | assert_fdi_rx_enabled(dev_priv, pipe); | |
1995 | ||
23670b32 DV |
1996 | if (HAS_PCH_CPT(dev)) { |
1997 | /* Workaround: Set the timing override bit before enabling the | |
1998 | * pch transcoder. */ | |
1999 | reg = TRANS_CHICKEN2(pipe); | |
2000 | val = I915_READ(reg); | |
2001 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; | |
2002 | I915_WRITE(reg, val); | |
59c859d6 | 2003 | } |
23670b32 | 2004 | |
ab9412ba | 2005 | reg = PCH_TRANSCONF(pipe); |
040484af | 2006 | val = I915_READ(reg); |
5f7f726d | 2007 | pipeconf_val = I915_READ(PIPECONF(pipe)); |
e9bcff5c JB |
2008 | |
2009 | if (HAS_PCH_IBX(dev_priv->dev)) { | |
2010 | /* | |
2011 | * make the BPC in transcoder be consistent with | |
2012 | * that in pipeconf reg. | |
2013 | */ | |
dfd07d72 DV |
2014 | val &= ~PIPECONF_BPC_MASK; |
2015 | val |= pipeconf_val & PIPECONF_BPC_MASK; | |
e9bcff5c | 2016 | } |
5f7f726d PZ |
2017 | |
2018 | val &= ~TRANS_INTERLACE_MASK; | |
2019 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) | |
7c26e5c6 | 2020 | if (HAS_PCH_IBX(dev_priv->dev) && |
409ee761 | 2021 | intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
7c26e5c6 PZ |
2022 | val |= TRANS_LEGACY_INTERLACED_ILK; |
2023 | else | |
2024 | val |= TRANS_INTERLACED; | |
5f7f726d PZ |
2025 | else |
2026 | val |= TRANS_PROGRESSIVE; | |
2027 | ||
040484af JB |
2028 | I915_WRITE(reg, val | TRANS_ENABLE); |
2029 | if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100)) | |
4bb6f1f3 | 2030 | DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe)); |
040484af JB |
2031 | } |
2032 | ||
8fb033d7 | 2033 | static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
937bb610 | 2034 | enum transcoder cpu_transcoder) |
040484af | 2035 | { |
8fb033d7 | 2036 | u32 val, pipeconf_val; |
8fb033d7 PZ |
2037 | |
2038 | /* PCH only available on ILK+ */ | |
55522f37 | 2039 | BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev)); |
8fb033d7 | 2040 | |
8fb033d7 | 2041 | /* FDI must be feeding us bits for PCH ports */ |
1a240d4d | 2042 | assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); |
937bb610 | 2043 | assert_fdi_rx_enabled(dev_priv, TRANSCODER_A); |
8fb033d7 | 2044 | |
223a6fdf PZ |
2045 | /* Workaround: set timing override bit. */ |
2046 | val = I915_READ(_TRANSA_CHICKEN2); | |
23670b32 | 2047 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
223a6fdf PZ |
2048 | I915_WRITE(_TRANSA_CHICKEN2, val); |
2049 | ||
25f3ef11 | 2050 | val = TRANS_ENABLE; |
937bb610 | 2051 | pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); |
8fb033d7 | 2052 | |
9a76b1c6 PZ |
2053 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == |
2054 | PIPECONF_INTERLACED_ILK) | |
a35f2679 | 2055 | val |= TRANS_INTERLACED; |
8fb033d7 PZ |
2056 | else |
2057 | val |= TRANS_PROGRESSIVE; | |
2058 | ||
ab9412ba DV |
2059 | I915_WRITE(LPT_TRANSCONF, val); |
2060 | if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100)) | |
937bb610 | 2061 | DRM_ERROR("Failed to enable PCH transcoder\n"); |
8fb033d7 PZ |
2062 | } |
2063 | ||
b8a4f404 PZ |
2064 | static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, |
2065 | enum pipe pipe) | |
040484af | 2066 | { |
23670b32 DV |
2067 | struct drm_device *dev = dev_priv->dev; |
2068 | uint32_t reg, val; | |
040484af JB |
2069 | |
2070 | /* FDI relies on the transcoder */ | |
2071 | assert_fdi_tx_disabled(dev_priv, pipe); | |
2072 | assert_fdi_rx_disabled(dev_priv, pipe); | |
2073 | ||
291906f1 JB |
2074 | /* Ports must be off as well */ |
2075 | assert_pch_ports_disabled(dev_priv, pipe); | |
2076 | ||
ab9412ba | 2077 | reg = PCH_TRANSCONF(pipe); |
040484af JB |
2078 | val = I915_READ(reg); |
2079 | val &= ~TRANS_ENABLE; | |
2080 | I915_WRITE(reg, val); | |
2081 | /* wait for PCH transcoder off, transcoder state */ | |
2082 | if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50)) | |
4bb6f1f3 | 2083 | DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe)); |
23670b32 DV |
2084 | |
2085 | if (!HAS_PCH_IBX(dev)) { | |
2086 | /* Workaround: Clear the timing override chicken bit again. */ | |
2087 | reg = TRANS_CHICKEN2(pipe); | |
2088 | val = I915_READ(reg); | |
2089 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; | |
2090 | I915_WRITE(reg, val); | |
2091 | } | |
040484af JB |
2092 | } |
2093 | ||
ab4d966c | 2094 | static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) |
8fb033d7 | 2095 | { |
8fb033d7 PZ |
2096 | u32 val; |
2097 | ||
ab9412ba | 2098 | val = I915_READ(LPT_TRANSCONF); |
8fb033d7 | 2099 | val &= ~TRANS_ENABLE; |
ab9412ba | 2100 | I915_WRITE(LPT_TRANSCONF, val); |
8fb033d7 | 2101 | /* wait for PCH transcoder off, transcoder state */ |
ab9412ba | 2102 | if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50)) |
8a52fd9f | 2103 | DRM_ERROR("Failed to disable PCH transcoder\n"); |
223a6fdf PZ |
2104 | |
2105 | /* Workaround: clear timing override bit. */ | |
2106 | val = I915_READ(_TRANSA_CHICKEN2); | |
23670b32 | 2107 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
223a6fdf | 2108 | I915_WRITE(_TRANSA_CHICKEN2, val); |
040484af JB |
2109 | } |
2110 | ||
b24e7179 | 2111 | /** |
309cfea8 | 2112 | * intel_enable_pipe - enable a pipe, asserting requirements |
0372264a | 2113 | * @crtc: crtc responsible for the pipe |
b24e7179 | 2114 | * |
0372264a | 2115 | * Enable @crtc's pipe, making sure that various hardware specific requirements |
b24e7179 | 2116 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. |
b24e7179 | 2117 | */ |
e1fdc473 | 2118 | static void intel_enable_pipe(struct intel_crtc *crtc) |
b24e7179 | 2119 | { |
0372264a PZ |
2120 | struct drm_device *dev = crtc->base.dev; |
2121 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2122 | enum pipe pipe = crtc->pipe; | |
702e7a56 PZ |
2123 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
2124 | pipe); | |
1a240d4d | 2125 | enum pipe pch_transcoder; |
b24e7179 JB |
2126 | int reg; |
2127 | u32 val; | |
2128 | ||
58c6eaa2 | 2129 | assert_planes_disabled(dev_priv, pipe); |
93ce0ba6 | 2130 | assert_cursor_disabled(dev_priv, pipe); |
58c6eaa2 DV |
2131 | assert_sprites_disabled(dev_priv, pipe); |
2132 | ||
681e5811 | 2133 | if (HAS_PCH_LPT(dev_priv->dev)) |
cc391bbb PZ |
2134 | pch_transcoder = TRANSCODER_A; |
2135 | else | |
2136 | pch_transcoder = pipe; | |
2137 | ||
b24e7179 JB |
2138 | /* |
2139 | * A pipe without a PLL won't actually be able to drive bits from | |
2140 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't | |
2141 | * need the check. | |
2142 | */ | |
50360403 | 2143 | if (HAS_GMCH_DISPLAY(dev_priv->dev)) |
409ee761 | 2144 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) |
23538ef1 JN |
2145 | assert_dsi_pll_enabled(dev_priv); |
2146 | else | |
2147 | assert_pll_enabled(dev_priv, pipe); | |
040484af | 2148 | else { |
6e3c9717 | 2149 | if (crtc->config->has_pch_encoder) { |
040484af | 2150 | /* if driving the PCH, we need FDI enabled */ |
cc391bbb | 2151 | assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder); |
1a240d4d DV |
2152 | assert_fdi_tx_pll_enabled(dev_priv, |
2153 | (enum pipe) cpu_transcoder); | |
040484af JB |
2154 | } |
2155 | /* FIXME: assert CPU port conditions for SNB+ */ | |
2156 | } | |
b24e7179 | 2157 | |
702e7a56 | 2158 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 2159 | val = I915_READ(reg); |
7ad25d48 | 2160 | if (val & PIPECONF_ENABLE) { |
b6b5d049 VS |
2161 | WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
2162 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))); | |
00d70b15 | 2163 | return; |
7ad25d48 | 2164 | } |
00d70b15 CW |
2165 | |
2166 | I915_WRITE(reg, val | PIPECONF_ENABLE); | |
851855d8 | 2167 | POSTING_READ(reg); |
b24e7179 JB |
2168 | } |
2169 | ||
2170 | /** | |
309cfea8 | 2171 | * intel_disable_pipe - disable a pipe, asserting requirements |
575f7ab7 | 2172 | * @crtc: crtc whose pipes is to be disabled |
b24e7179 | 2173 | * |
575f7ab7 VS |
2174 | * Disable the pipe of @crtc, making sure that various hardware |
2175 | * specific requirements are met, if applicable, e.g. plane | |
2176 | * disabled, panel fitter off, etc. | |
b24e7179 JB |
2177 | * |
2178 | * Will wait until the pipe has shut down before returning. | |
2179 | */ | |
575f7ab7 | 2180 | static void intel_disable_pipe(struct intel_crtc *crtc) |
b24e7179 | 2181 | { |
575f7ab7 | 2182 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
6e3c9717 | 2183 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 2184 | enum pipe pipe = crtc->pipe; |
b24e7179 JB |
2185 | int reg; |
2186 | u32 val; | |
2187 | ||
2188 | /* | |
2189 | * Make sure planes won't keep trying to pump pixels to us, | |
2190 | * or we might hang the display. | |
2191 | */ | |
2192 | assert_planes_disabled(dev_priv, pipe); | |
93ce0ba6 | 2193 | assert_cursor_disabled(dev_priv, pipe); |
19332d7a | 2194 | assert_sprites_disabled(dev_priv, pipe); |
b24e7179 | 2195 | |
702e7a56 | 2196 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 2197 | val = I915_READ(reg); |
00d70b15 CW |
2198 | if ((val & PIPECONF_ENABLE) == 0) |
2199 | return; | |
2200 | ||
67adc644 VS |
2201 | /* |
2202 | * Double wide has implications for planes | |
2203 | * so best keep it disabled when not needed. | |
2204 | */ | |
6e3c9717 | 2205 | if (crtc->config->double_wide) |
67adc644 VS |
2206 | val &= ~PIPECONF_DOUBLE_WIDE; |
2207 | ||
2208 | /* Don't disable pipe or pipe PLLs if needed */ | |
b6b5d049 VS |
2209 | if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) && |
2210 | !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
67adc644 VS |
2211 | val &= ~PIPECONF_ENABLE; |
2212 | ||
2213 | I915_WRITE(reg, val); | |
2214 | if ((val & PIPECONF_ENABLE) == 0) | |
2215 | intel_wait_for_pipe_off(crtc); | |
b24e7179 JB |
2216 | } |
2217 | ||
2218 | /** | |
262ca2b0 | 2219 | * intel_enable_primary_hw_plane - enable the primary plane on a given pipe |
fdd508a6 VS |
2220 | * @plane: plane to be enabled |
2221 | * @crtc: crtc for the plane | |
b24e7179 | 2222 | * |
fdd508a6 | 2223 | * Enable @plane on @crtc, making sure that the pipe is running first. |
b24e7179 | 2224 | */ |
fdd508a6 VS |
2225 | static void intel_enable_primary_hw_plane(struct drm_plane *plane, |
2226 | struct drm_crtc *crtc) | |
b24e7179 | 2227 | { |
fdd508a6 VS |
2228 | struct drm_device *dev = plane->dev; |
2229 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2230 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
b24e7179 JB |
2231 | |
2232 | /* If the pipe isn't enabled, we can't pump pixels and may hang */ | |
fdd508a6 | 2233 | assert_pipe_enabled(dev_priv, intel_crtc->pipe); |
b70709a6 | 2234 | to_intel_plane_state(plane->state)->visible = true; |
939c2fe8 | 2235 | |
fdd508a6 VS |
2236 | dev_priv->display.update_primary_plane(crtc, plane->fb, |
2237 | crtc->x, crtc->y); | |
b24e7179 JB |
2238 | } |
2239 | ||
693db184 CW |
2240 | static bool need_vtd_wa(struct drm_device *dev) |
2241 | { | |
2242 | #ifdef CONFIG_INTEL_IOMMU | |
2243 | if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped) | |
2244 | return true; | |
2245 | #endif | |
2246 | return false; | |
2247 | } | |
2248 | ||
50470bb0 | 2249 | unsigned int |
6761dd31 TU |
2250 | intel_tile_height(struct drm_device *dev, uint32_t pixel_format, |
2251 | uint64_t fb_format_modifier) | |
a57ce0b2 | 2252 | { |
6761dd31 TU |
2253 | unsigned int tile_height; |
2254 | uint32_t pixel_bytes; | |
a57ce0b2 | 2255 | |
b5d0e9bf DL |
2256 | switch (fb_format_modifier) { |
2257 | case DRM_FORMAT_MOD_NONE: | |
2258 | tile_height = 1; | |
2259 | break; | |
2260 | case I915_FORMAT_MOD_X_TILED: | |
2261 | tile_height = IS_GEN2(dev) ? 16 : 8; | |
2262 | break; | |
2263 | case I915_FORMAT_MOD_Y_TILED: | |
2264 | tile_height = 32; | |
2265 | break; | |
2266 | case I915_FORMAT_MOD_Yf_TILED: | |
6761dd31 TU |
2267 | pixel_bytes = drm_format_plane_cpp(pixel_format, 0); |
2268 | switch (pixel_bytes) { | |
b5d0e9bf | 2269 | default: |
6761dd31 | 2270 | case 1: |
b5d0e9bf DL |
2271 | tile_height = 64; |
2272 | break; | |
6761dd31 TU |
2273 | case 2: |
2274 | case 4: | |
b5d0e9bf DL |
2275 | tile_height = 32; |
2276 | break; | |
6761dd31 | 2277 | case 8: |
b5d0e9bf DL |
2278 | tile_height = 16; |
2279 | break; | |
6761dd31 | 2280 | case 16: |
b5d0e9bf DL |
2281 | WARN_ONCE(1, |
2282 | "128-bit pixels are not supported for display!"); | |
2283 | tile_height = 16; | |
2284 | break; | |
2285 | } | |
2286 | break; | |
2287 | default: | |
2288 | MISSING_CASE(fb_format_modifier); | |
2289 | tile_height = 1; | |
2290 | break; | |
2291 | } | |
091df6cb | 2292 | |
6761dd31 TU |
2293 | return tile_height; |
2294 | } | |
2295 | ||
2296 | unsigned int | |
2297 | intel_fb_align_height(struct drm_device *dev, unsigned int height, | |
2298 | uint32_t pixel_format, uint64_t fb_format_modifier) | |
2299 | { | |
2300 | return ALIGN(height, intel_tile_height(dev, pixel_format, | |
2301 | fb_format_modifier)); | |
a57ce0b2 JB |
2302 | } |
2303 | ||
f64b98cd TU |
2304 | static int |
2305 | intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb, | |
2306 | const struct drm_plane_state *plane_state) | |
2307 | { | |
50470bb0 | 2308 | struct intel_rotation_info *info = &view->rotation_info; |
50470bb0 | 2309 | |
f64b98cd TU |
2310 | *view = i915_ggtt_view_normal; |
2311 | ||
50470bb0 TU |
2312 | if (!plane_state) |
2313 | return 0; | |
2314 | ||
121920fa | 2315 | if (!intel_rotation_90_or_270(plane_state->rotation)) |
50470bb0 TU |
2316 | return 0; |
2317 | ||
9abc4648 | 2318 | *view = i915_ggtt_view_rotated; |
50470bb0 TU |
2319 | |
2320 | info->height = fb->height; | |
2321 | info->pixel_format = fb->pixel_format; | |
2322 | info->pitch = fb->pitches[0]; | |
2323 | info->fb_modifier = fb->modifier[0]; | |
2324 | ||
f64b98cd TU |
2325 | return 0; |
2326 | } | |
2327 | ||
127bd2ac | 2328 | int |
850c4cdc TU |
2329 | intel_pin_and_fence_fb_obj(struct drm_plane *plane, |
2330 | struct drm_framebuffer *fb, | |
82bc3b2d | 2331 | const struct drm_plane_state *plane_state, |
a4872ba6 | 2332 | struct intel_engine_cs *pipelined) |
6b95a207 | 2333 | { |
850c4cdc | 2334 | struct drm_device *dev = fb->dev; |
ce453d81 | 2335 | struct drm_i915_private *dev_priv = dev->dev_private; |
850c4cdc | 2336 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
f64b98cd | 2337 | struct i915_ggtt_view view; |
6b95a207 KH |
2338 | u32 alignment; |
2339 | int ret; | |
2340 | ||
ebcdd39e MR |
2341 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
2342 | ||
7b911adc TU |
2343 | switch (fb->modifier[0]) { |
2344 | case DRM_FORMAT_MOD_NONE: | |
1fada4cc DL |
2345 | if (INTEL_INFO(dev)->gen >= 9) |
2346 | alignment = 256 * 1024; | |
2347 | else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) | |
534843da | 2348 | alignment = 128 * 1024; |
a6c45cf0 | 2349 | else if (INTEL_INFO(dev)->gen >= 4) |
534843da CW |
2350 | alignment = 4 * 1024; |
2351 | else | |
2352 | alignment = 64 * 1024; | |
6b95a207 | 2353 | break; |
7b911adc | 2354 | case I915_FORMAT_MOD_X_TILED: |
1fada4cc DL |
2355 | if (INTEL_INFO(dev)->gen >= 9) |
2356 | alignment = 256 * 1024; | |
2357 | else { | |
2358 | /* pin() will align the object as required by fence */ | |
2359 | alignment = 0; | |
2360 | } | |
6b95a207 | 2361 | break; |
7b911adc | 2362 | case I915_FORMAT_MOD_Y_TILED: |
1327b9a1 DL |
2363 | case I915_FORMAT_MOD_Yf_TILED: |
2364 | if (WARN_ONCE(INTEL_INFO(dev)->gen < 9, | |
2365 | "Y tiling bo slipped through, driver bug!\n")) | |
2366 | return -EINVAL; | |
2367 | alignment = 1 * 1024 * 1024; | |
2368 | break; | |
6b95a207 | 2369 | default: |
7b911adc TU |
2370 | MISSING_CASE(fb->modifier[0]); |
2371 | return -EINVAL; | |
6b95a207 KH |
2372 | } |
2373 | ||
f64b98cd TU |
2374 | ret = intel_fill_fb_ggtt_view(&view, fb, plane_state); |
2375 | if (ret) | |
2376 | return ret; | |
2377 | ||
693db184 CW |
2378 | /* Note that the w/a also requires 64 PTE of padding following the |
2379 | * bo. We currently fill all unused PTE with the shadow page and so | |
2380 | * we should always have valid PTE following the scanout preventing | |
2381 | * the VT-d warning. | |
2382 | */ | |
2383 | if (need_vtd_wa(dev) && alignment < 256 * 1024) | |
2384 | alignment = 256 * 1024; | |
2385 | ||
d6dd6843 PZ |
2386 | /* |
2387 | * Global gtt pte registers are special registers which actually forward | |
2388 | * writes to a chunk of system memory. Which means that there is no risk | |
2389 | * that the register values disappear as soon as we call | |
2390 | * intel_runtime_pm_put(), so it is correct to wrap only the | |
2391 | * pin/unpin/fence and not more. | |
2392 | */ | |
2393 | intel_runtime_pm_get(dev_priv); | |
2394 | ||
ce453d81 | 2395 | dev_priv->mm.interruptible = false; |
e6617330 | 2396 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined, |
f64b98cd | 2397 | &view); |
48b956c5 | 2398 | if (ret) |
ce453d81 | 2399 | goto err_interruptible; |
6b95a207 KH |
2400 | |
2401 | /* Install a fence for tiled scan-out. Pre-i965 always needs a | |
2402 | * fence, whereas 965+ only requires a fence if using | |
2403 | * framebuffer compression. For simplicity, we always install | |
2404 | * a fence as the cost is not that onerous. | |
2405 | */ | |
06d98131 | 2406 | ret = i915_gem_object_get_fence(obj); |
9a5a53b3 CW |
2407 | if (ret) |
2408 | goto err_unpin; | |
1690e1eb | 2409 | |
9a5a53b3 | 2410 | i915_gem_object_pin_fence(obj); |
6b95a207 | 2411 | |
ce453d81 | 2412 | dev_priv->mm.interruptible = true; |
d6dd6843 | 2413 | intel_runtime_pm_put(dev_priv); |
6b95a207 | 2414 | return 0; |
48b956c5 CW |
2415 | |
2416 | err_unpin: | |
f64b98cd | 2417 | i915_gem_object_unpin_from_display_plane(obj, &view); |
ce453d81 CW |
2418 | err_interruptible: |
2419 | dev_priv->mm.interruptible = true; | |
d6dd6843 | 2420 | intel_runtime_pm_put(dev_priv); |
48b956c5 | 2421 | return ret; |
6b95a207 KH |
2422 | } |
2423 | ||
82bc3b2d TU |
2424 | static void intel_unpin_fb_obj(struct drm_framebuffer *fb, |
2425 | const struct drm_plane_state *plane_state) | |
1690e1eb | 2426 | { |
82bc3b2d | 2427 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
f64b98cd TU |
2428 | struct i915_ggtt_view view; |
2429 | int ret; | |
82bc3b2d | 2430 | |
ebcdd39e MR |
2431 | WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex)); |
2432 | ||
f64b98cd TU |
2433 | ret = intel_fill_fb_ggtt_view(&view, fb, plane_state); |
2434 | WARN_ONCE(ret, "Couldn't get view from plane state!"); | |
2435 | ||
1690e1eb | 2436 | i915_gem_object_unpin_fence(obj); |
f64b98cd | 2437 | i915_gem_object_unpin_from_display_plane(obj, &view); |
1690e1eb CW |
2438 | } |
2439 | ||
c2c75131 DV |
2440 | /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel |
2441 | * is assumed to be a power-of-two. */ | |
bc752862 CW |
2442 | unsigned long intel_gen4_compute_page_offset(int *x, int *y, |
2443 | unsigned int tiling_mode, | |
2444 | unsigned int cpp, | |
2445 | unsigned int pitch) | |
c2c75131 | 2446 | { |
bc752862 CW |
2447 | if (tiling_mode != I915_TILING_NONE) { |
2448 | unsigned int tile_rows, tiles; | |
c2c75131 | 2449 | |
bc752862 CW |
2450 | tile_rows = *y / 8; |
2451 | *y %= 8; | |
c2c75131 | 2452 | |
bc752862 CW |
2453 | tiles = *x / (512/cpp); |
2454 | *x %= 512/cpp; | |
2455 | ||
2456 | return tile_rows * pitch * 8 + tiles * 4096; | |
2457 | } else { | |
2458 | unsigned int offset; | |
2459 | ||
2460 | offset = *y * pitch + *x * cpp; | |
2461 | *y = 0; | |
2462 | *x = (offset & 4095) / cpp; | |
2463 | return offset & -4096; | |
2464 | } | |
c2c75131 DV |
2465 | } |
2466 | ||
b35d63fa | 2467 | static int i9xx_format_to_fourcc(int format) |
46f297fb JB |
2468 | { |
2469 | switch (format) { | |
2470 | case DISPPLANE_8BPP: | |
2471 | return DRM_FORMAT_C8; | |
2472 | case DISPPLANE_BGRX555: | |
2473 | return DRM_FORMAT_XRGB1555; | |
2474 | case DISPPLANE_BGRX565: | |
2475 | return DRM_FORMAT_RGB565; | |
2476 | default: | |
2477 | case DISPPLANE_BGRX888: | |
2478 | return DRM_FORMAT_XRGB8888; | |
2479 | case DISPPLANE_RGBX888: | |
2480 | return DRM_FORMAT_XBGR8888; | |
2481 | case DISPPLANE_BGRX101010: | |
2482 | return DRM_FORMAT_XRGB2101010; | |
2483 | case DISPPLANE_RGBX101010: | |
2484 | return DRM_FORMAT_XBGR2101010; | |
2485 | } | |
2486 | } | |
2487 | ||
bc8d7dff DL |
2488 | static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha) |
2489 | { | |
2490 | switch (format) { | |
2491 | case PLANE_CTL_FORMAT_RGB_565: | |
2492 | return DRM_FORMAT_RGB565; | |
2493 | default: | |
2494 | case PLANE_CTL_FORMAT_XRGB_8888: | |
2495 | if (rgb_order) { | |
2496 | if (alpha) | |
2497 | return DRM_FORMAT_ABGR8888; | |
2498 | else | |
2499 | return DRM_FORMAT_XBGR8888; | |
2500 | } else { | |
2501 | if (alpha) | |
2502 | return DRM_FORMAT_ARGB8888; | |
2503 | else | |
2504 | return DRM_FORMAT_XRGB8888; | |
2505 | } | |
2506 | case PLANE_CTL_FORMAT_XRGB_2101010: | |
2507 | if (rgb_order) | |
2508 | return DRM_FORMAT_XBGR2101010; | |
2509 | else | |
2510 | return DRM_FORMAT_XRGB2101010; | |
2511 | } | |
2512 | } | |
2513 | ||
5724dbd1 | 2514 | static bool |
f6936e29 DV |
2515 | intel_alloc_initial_plane_obj(struct intel_crtc *crtc, |
2516 | struct intel_initial_plane_config *plane_config) | |
46f297fb JB |
2517 | { |
2518 | struct drm_device *dev = crtc->base.dev; | |
2519 | struct drm_i915_gem_object *obj = NULL; | |
2520 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; | |
2d14030b | 2521 | struct drm_framebuffer *fb = &plane_config->fb->base; |
f37b5c2b DV |
2522 | u32 base_aligned = round_down(plane_config->base, PAGE_SIZE); |
2523 | u32 size_aligned = round_up(plane_config->base + plane_config->size, | |
2524 | PAGE_SIZE); | |
2525 | ||
2526 | size_aligned -= base_aligned; | |
46f297fb | 2527 | |
ff2652ea CW |
2528 | if (plane_config->size == 0) |
2529 | return false; | |
2530 | ||
f37b5c2b DV |
2531 | obj = i915_gem_object_create_stolen_for_preallocated(dev, |
2532 | base_aligned, | |
2533 | base_aligned, | |
2534 | size_aligned); | |
46f297fb | 2535 | if (!obj) |
484b41dd | 2536 | return false; |
46f297fb | 2537 | |
49af449b DL |
2538 | obj->tiling_mode = plane_config->tiling; |
2539 | if (obj->tiling_mode == I915_TILING_X) | |
6bf129df | 2540 | obj->stride = fb->pitches[0]; |
46f297fb | 2541 | |
6bf129df DL |
2542 | mode_cmd.pixel_format = fb->pixel_format; |
2543 | mode_cmd.width = fb->width; | |
2544 | mode_cmd.height = fb->height; | |
2545 | mode_cmd.pitches[0] = fb->pitches[0]; | |
18c5247e DV |
2546 | mode_cmd.modifier[0] = fb->modifier[0]; |
2547 | mode_cmd.flags = DRM_MODE_FB_MODIFIERS; | |
46f297fb JB |
2548 | |
2549 | mutex_lock(&dev->struct_mutex); | |
6bf129df | 2550 | if (intel_framebuffer_init(dev, to_intel_framebuffer(fb), |
484b41dd | 2551 | &mode_cmd, obj)) { |
46f297fb JB |
2552 | DRM_DEBUG_KMS("intel fb init failed\n"); |
2553 | goto out_unref_obj; | |
2554 | } | |
46f297fb | 2555 | mutex_unlock(&dev->struct_mutex); |
484b41dd | 2556 | |
f6936e29 | 2557 | DRM_DEBUG_KMS("initial plane fb obj %p\n", obj); |
484b41dd | 2558 | return true; |
46f297fb JB |
2559 | |
2560 | out_unref_obj: | |
2561 | drm_gem_object_unreference(&obj->base); | |
2562 | mutex_unlock(&dev->struct_mutex); | |
484b41dd JB |
2563 | return false; |
2564 | } | |
2565 | ||
afd65eb4 MR |
2566 | /* Update plane->state->fb to match plane->fb after driver-internal updates */ |
2567 | static void | |
2568 | update_state_fb(struct drm_plane *plane) | |
2569 | { | |
2570 | if (plane->fb == plane->state->fb) | |
2571 | return; | |
2572 | ||
2573 | if (plane->state->fb) | |
2574 | drm_framebuffer_unreference(plane->state->fb); | |
2575 | plane->state->fb = plane->fb; | |
2576 | if (plane->state->fb) | |
2577 | drm_framebuffer_reference(plane->state->fb); | |
2578 | } | |
2579 | ||
5724dbd1 | 2580 | static void |
f6936e29 DV |
2581 | intel_find_initial_plane_obj(struct intel_crtc *intel_crtc, |
2582 | struct intel_initial_plane_config *plane_config) | |
484b41dd JB |
2583 | { |
2584 | struct drm_device *dev = intel_crtc->base.dev; | |
d9ceb816 | 2585 | struct drm_i915_private *dev_priv = dev->dev_private; |
484b41dd JB |
2586 | struct drm_crtc *c; |
2587 | struct intel_crtc *i; | |
2ff8fde1 | 2588 | struct drm_i915_gem_object *obj; |
88595ac9 DV |
2589 | struct drm_plane *primary = intel_crtc->base.primary; |
2590 | struct drm_framebuffer *fb; | |
484b41dd | 2591 | |
2d14030b | 2592 | if (!plane_config->fb) |
484b41dd JB |
2593 | return; |
2594 | ||
f6936e29 | 2595 | if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) { |
88595ac9 DV |
2596 | fb = &plane_config->fb->base; |
2597 | goto valid_fb; | |
f55548b5 | 2598 | } |
484b41dd | 2599 | |
2d14030b | 2600 | kfree(plane_config->fb); |
484b41dd JB |
2601 | |
2602 | /* | |
2603 | * Failed to alloc the obj, check to see if we should share | |
2604 | * an fb with another CRTC instead | |
2605 | */ | |
70e1e0ec | 2606 | for_each_crtc(dev, c) { |
484b41dd JB |
2607 | i = to_intel_crtc(c); |
2608 | ||
2609 | if (c == &intel_crtc->base) | |
2610 | continue; | |
2611 | ||
2ff8fde1 MR |
2612 | if (!i->active) |
2613 | continue; | |
2614 | ||
88595ac9 DV |
2615 | fb = c->primary->fb; |
2616 | if (!fb) | |
484b41dd JB |
2617 | continue; |
2618 | ||
88595ac9 | 2619 | obj = intel_fb_obj(fb); |
2ff8fde1 | 2620 | if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) { |
88595ac9 DV |
2621 | drm_framebuffer_reference(fb); |
2622 | goto valid_fb; | |
484b41dd JB |
2623 | } |
2624 | } | |
88595ac9 DV |
2625 | |
2626 | return; | |
2627 | ||
2628 | valid_fb: | |
2629 | obj = intel_fb_obj(fb); | |
2630 | if (obj->tiling_mode != I915_TILING_NONE) | |
2631 | dev_priv->preserve_bios_swizzle = true; | |
2632 | ||
2633 | primary->fb = fb; | |
36750f28 | 2634 | primary->crtc = primary->state->crtc = &intel_crtc->base; |
88595ac9 | 2635 | update_state_fb(primary); |
36750f28 | 2636 | intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary)); |
88595ac9 | 2637 | obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe); |
46f297fb JB |
2638 | } |
2639 | ||
29b9bde6 DV |
2640 | static void i9xx_update_primary_plane(struct drm_crtc *crtc, |
2641 | struct drm_framebuffer *fb, | |
2642 | int x, int y) | |
81255565 JB |
2643 | { |
2644 | struct drm_device *dev = crtc->dev; | |
2645 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2646 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
b70709a6 ML |
2647 | struct drm_plane *primary = crtc->primary; |
2648 | bool visible = to_intel_plane_state(primary->state)->visible; | |
c9ba6fad | 2649 | struct drm_i915_gem_object *obj; |
81255565 | 2650 | int plane = intel_crtc->plane; |
e506a0c6 | 2651 | unsigned long linear_offset; |
81255565 | 2652 | u32 dspcntr; |
f45651ba | 2653 | u32 reg = DSPCNTR(plane); |
48404c1e | 2654 | int pixel_size; |
f45651ba | 2655 | |
b70709a6 | 2656 | if (!visible || !fb) { |
fdd508a6 VS |
2657 | I915_WRITE(reg, 0); |
2658 | if (INTEL_INFO(dev)->gen >= 4) | |
2659 | I915_WRITE(DSPSURF(plane), 0); | |
2660 | else | |
2661 | I915_WRITE(DSPADDR(plane), 0); | |
2662 | POSTING_READ(reg); | |
2663 | return; | |
2664 | } | |
2665 | ||
c9ba6fad VS |
2666 | obj = intel_fb_obj(fb); |
2667 | if (WARN_ON(obj == NULL)) | |
2668 | return; | |
2669 | ||
2670 | pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); | |
2671 | ||
f45651ba VS |
2672 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
2673 | ||
fdd508a6 | 2674 | dspcntr |= DISPLAY_PLANE_ENABLE; |
f45651ba VS |
2675 | |
2676 | if (INTEL_INFO(dev)->gen < 4) { | |
2677 | if (intel_crtc->pipe == PIPE_B) | |
2678 | dspcntr |= DISPPLANE_SEL_PIPE_B; | |
2679 | ||
2680 | /* pipesrc and dspsize control the size that is scaled from, | |
2681 | * which should always be the user's requested size. | |
2682 | */ | |
2683 | I915_WRITE(DSPSIZE(plane), | |
6e3c9717 ACO |
2684 | ((intel_crtc->config->pipe_src_h - 1) << 16) | |
2685 | (intel_crtc->config->pipe_src_w - 1)); | |
f45651ba | 2686 | I915_WRITE(DSPPOS(plane), 0); |
c14b0485 VS |
2687 | } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) { |
2688 | I915_WRITE(PRIMSIZE(plane), | |
6e3c9717 ACO |
2689 | ((intel_crtc->config->pipe_src_h - 1) << 16) | |
2690 | (intel_crtc->config->pipe_src_w - 1)); | |
c14b0485 VS |
2691 | I915_WRITE(PRIMPOS(plane), 0); |
2692 | I915_WRITE(PRIMCNSTALPHA(plane), 0); | |
f45651ba | 2693 | } |
81255565 | 2694 | |
57779d06 VS |
2695 | switch (fb->pixel_format) { |
2696 | case DRM_FORMAT_C8: | |
81255565 JB |
2697 | dspcntr |= DISPPLANE_8BPP; |
2698 | break; | |
57779d06 | 2699 | case DRM_FORMAT_XRGB1555: |
57779d06 | 2700 | dspcntr |= DISPPLANE_BGRX555; |
81255565 | 2701 | break; |
57779d06 VS |
2702 | case DRM_FORMAT_RGB565: |
2703 | dspcntr |= DISPPLANE_BGRX565; | |
2704 | break; | |
2705 | case DRM_FORMAT_XRGB8888: | |
57779d06 VS |
2706 | dspcntr |= DISPPLANE_BGRX888; |
2707 | break; | |
2708 | case DRM_FORMAT_XBGR8888: | |
57779d06 VS |
2709 | dspcntr |= DISPPLANE_RGBX888; |
2710 | break; | |
2711 | case DRM_FORMAT_XRGB2101010: | |
57779d06 VS |
2712 | dspcntr |= DISPPLANE_BGRX101010; |
2713 | break; | |
2714 | case DRM_FORMAT_XBGR2101010: | |
57779d06 | 2715 | dspcntr |= DISPPLANE_RGBX101010; |
81255565 JB |
2716 | break; |
2717 | default: | |
baba133a | 2718 | BUG(); |
81255565 | 2719 | } |
57779d06 | 2720 | |
f45651ba VS |
2721 | if (INTEL_INFO(dev)->gen >= 4 && |
2722 | obj->tiling_mode != I915_TILING_NONE) | |
2723 | dspcntr |= DISPPLANE_TILED; | |
81255565 | 2724 | |
de1aa629 VS |
2725 | if (IS_G4X(dev)) |
2726 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; | |
2727 | ||
b9897127 | 2728 | linear_offset = y * fb->pitches[0] + x * pixel_size; |
81255565 | 2729 | |
c2c75131 DV |
2730 | if (INTEL_INFO(dev)->gen >= 4) { |
2731 | intel_crtc->dspaddr_offset = | |
bc752862 | 2732 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
b9897127 | 2733 | pixel_size, |
bc752862 | 2734 | fb->pitches[0]); |
c2c75131 DV |
2735 | linear_offset -= intel_crtc->dspaddr_offset; |
2736 | } else { | |
e506a0c6 | 2737 | intel_crtc->dspaddr_offset = linear_offset; |
c2c75131 | 2738 | } |
e506a0c6 | 2739 | |
8e7d688b | 2740 | if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) { |
48404c1e SJ |
2741 | dspcntr |= DISPPLANE_ROTATE_180; |
2742 | ||
6e3c9717 ACO |
2743 | x += (intel_crtc->config->pipe_src_w - 1); |
2744 | y += (intel_crtc->config->pipe_src_h - 1); | |
48404c1e SJ |
2745 | |
2746 | /* Finding the last pixel of the last line of the display | |
2747 | data and adding to linear_offset*/ | |
2748 | linear_offset += | |
6e3c9717 ACO |
2749 | (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] + |
2750 | (intel_crtc->config->pipe_src_w - 1) * pixel_size; | |
48404c1e SJ |
2751 | } |
2752 | ||
2753 | I915_WRITE(reg, dspcntr); | |
2754 | ||
01f2c773 | 2755 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
a6c45cf0 | 2756 | if (INTEL_INFO(dev)->gen >= 4) { |
85ba7b7d DV |
2757 | I915_WRITE(DSPSURF(plane), |
2758 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
5eddb70b | 2759 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
e506a0c6 | 2760 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
5eddb70b | 2761 | } else |
f343c5f6 | 2762 | I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset); |
5eddb70b | 2763 | POSTING_READ(reg); |
17638cd6 JB |
2764 | } |
2765 | ||
29b9bde6 DV |
2766 | static void ironlake_update_primary_plane(struct drm_crtc *crtc, |
2767 | struct drm_framebuffer *fb, | |
2768 | int x, int y) | |
17638cd6 JB |
2769 | { |
2770 | struct drm_device *dev = crtc->dev; | |
2771 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2772 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
b70709a6 ML |
2773 | struct drm_plane *primary = crtc->primary; |
2774 | bool visible = to_intel_plane_state(primary->state)->visible; | |
c9ba6fad | 2775 | struct drm_i915_gem_object *obj; |
17638cd6 | 2776 | int plane = intel_crtc->plane; |
e506a0c6 | 2777 | unsigned long linear_offset; |
17638cd6 | 2778 | u32 dspcntr; |
f45651ba | 2779 | u32 reg = DSPCNTR(plane); |
48404c1e | 2780 | int pixel_size; |
f45651ba | 2781 | |
b70709a6 | 2782 | if (!visible || !fb) { |
fdd508a6 VS |
2783 | I915_WRITE(reg, 0); |
2784 | I915_WRITE(DSPSURF(plane), 0); | |
2785 | POSTING_READ(reg); | |
2786 | return; | |
2787 | } | |
2788 | ||
c9ba6fad VS |
2789 | obj = intel_fb_obj(fb); |
2790 | if (WARN_ON(obj == NULL)) | |
2791 | return; | |
2792 | ||
2793 | pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); | |
2794 | ||
f45651ba VS |
2795 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
2796 | ||
fdd508a6 | 2797 | dspcntr |= DISPLAY_PLANE_ENABLE; |
f45651ba VS |
2798 | |
2799 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
2800 | dspcntr |= DISPPLANE_PIPE_CSC_ENABLE; | |
17638cd6 | 2801 | |
57779d06 VS |
2802 | switch (fb->pixel_format) { |
2803 | case DRM_FORMAT_C8: | |
17638cd6 JB |
2804 | dspcntr |= DISPPLANE_8BPP; |
2805 | break; | |
57779d06 VS |
2806 | case DRM_FORMAT_RGB565: |
2807 | dspcntr |= DISPPLANE_BGRX565; | |
17638cd6 | 2808 | break; |
57779d06 | 2809 | case DRM_FORMAT_XRGB8888: |
57779d06 VS |
2810 | dspcntr |= DISPPLANE_BGRX888; |
2811 | break; | |
2812 | case DRM_FORMAT_XBGR8888: | |
57779d06 VS |
2813 | dspcntr |= DISPPLANE_RGBX888; |
2814 | break; | |
2815 | case DRM_FORMAT_XRGB2101010: | |
57779d06 VS |
2816 | dspcntr |= DISPPLANE_BGRX101010; |
2817 | break; | |
2818 | case DRM_FORMAT_XBGR2101010: | |
57779d06 | 2819 | dspcntr |= DISPPLANE_RGBX101010; |
17638cd6 JB |
2820 | break; |
2821 | default: | |
baba133a | 2822 | BUG(); |
17638cd6 JB |
2823 | } |
2824 | ||
2825 | if (obj->tiling_mode != I915_TILING_NONE) | |
2826 | dspcntr |= DISPPLANE_TILED; | |
17638cd6 | 2827 | |
f45651ba | 2828 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) |
1f5d76db | 2829 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; |
17638cd6 | 2830 | |
b9897127 | 2831 | linear_offset = y * fb->pitches[0] + x * pixel_size; |
c2c75131 | 2832 | intel_crtc->dspaddr_offset = |
bc752862 | 2833 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
b9897127 | 2834 | pixel_size, |
bc752862 | 2835 | fb->pitches[0]); |
c2c75131 | 2836 | linear_offset -= intel_crtc->dspaddr_offset; |
8e7d688b | 2837 | if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) { |
48404c1e SJ |
2838 | dspcntr |= DISPPLANE_ROTATE_180; |
2839 | ||
2840 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) { | |
6e3c9717 ACO |
2841 | x += (intel_crtc->config->pipe_src_w - 1); |
2842 | y += (intel_crtc->config->pipe_src_h - 1); | |
48404c1e SJ |
2843 | |
2844 | /* Finding the last pixel of the last line of the display | |
2845 | data and adding to linear_offset*/ | |
2846 | linear_offset += | |
6e3c9717 ACO |
2847 | (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] + |
2848 | (intel_crtc->config->pipe_src_w - 1) * pixel_size; | |
48404c1e SJ |
2849 | } |
2850 | } | |
2851 | ||
2852 | I915_WRITE(reg, dspcntr); | |
17638cd6 | 2853 | |
01f2c773 | 2854 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
85ba7b7d DV |
2855 | I915_WRITE(DSPSURF(plane), |
2856 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
b3dc685e | 2857 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
bc1c91eb DL |
2858 | I915_WRITE(DSPOFFSET(plane), (y << 16) | x); |
2859 | } else { | |
2860 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); | |
2861 | I915_WRITE(DSPLINOFF(plane), linear_offset); | |
2862 | } | |
17638cd6 | 2863 | POSTING_READ(reg); |
17638cd6 JB |
2864 | } |
2865 | ||
b321803d DL |
2866 | u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier, |
2867 | uint32_t pixel_format) | |
2868 | { | |
2869 | u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8; | |
2870 | ||
2871 | /* | |
2872 | * The stride is either expressed as a multiple of 64 bytes | |
2873 | * chunks for linear buffers or in number of tiles for tiled | |
2874 | * buffers. | |
2875 | */ | |
2876 | switch (fb_modifier) { | |
2877 | case DRM_FORMAT_MOD_NONE: | |
2878 | return 64; | |
2879 | case I915_FORMAT_MOD_X_TILED: | |
2880 | if (INTEL_INFO(dev)->gen == 2) | |
2881 | return 128; | |
2882 | return 512; | |
2883 | case I915_FORMAT_MOD_Y_TILED: | |
2884 | /* No need to check for old gens and Y tiling since this is | |
2885 | * about the display engine and those will be blocked before | |
2886 | * we get here. | |
2887 | */ | |
2888 | return 128; | |
2889 | case I915_FORMAT_MOD_Yf_TILED: | |
2890 | if (bits_per_pixel == 8) | |
2891 | return 64; | |
2892 | else | |
2893 | return 128; | |
2894 | default: | |
2895 | MISSING_CASE(fb_modifier); | |
2896 | return 64; | |
2897 | } | |
2898 | } | |
2899 | ||
121920fa TU |
2900 | unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane, |
2901 | struct drm_i915_gem_object *obj) | |
2902 | { | |
9abc4648 | 2903 | const struct i915_ggtt_view *view = &i915_ggtt_view_normal; |
121920fa TU |
2904 | |
2905 | if (intel_rotation_90_or_270(intel_plane->base.state->rotation)) | |
9abc4648 | 2906 | view = &i915_ggtt_view_rotated; |
121920fa TU |
2907 | |
2908 | return i915_gem_obj_ggtt_offset_view(obj, view); | |
2909 | } | |
2910 | ||
a1b2278e CK |
2911 | /* |
2912 | * This function detaches (aka. unbinds) unused scalers in hardware | |
2913 | */ | |
2914 | void skl_detach_scalers(struct intel_crtc *intel_crtc) | |
2915 | { | |
2916 | struct drm_device *dev; | |
2917 | struct drm_i915_private *dev_priv; | |
2918 | struct intel_crtc_scaler_state *scaler_state; | |
2919 | int i; | |
2920 | ||
2921 | if (!intel_crtc || !intel_crtc->config) | |
2922 | return; | |
2923 | ||
2924 | dev = intel_crtc->base.dev; | |
2925 | dev_priv = dev->dev_private; | |
2926 | scaler_state = &intel_crtc->config->scaler_state; | |
2927 | ||
2928 | /* loop through and disable scalers that aren't in use */ | |
2929 | for (i = 0; i < intel_crtc->num_scalers; i++) { | |
2930 | if (!scaler_state->scalers[i].in_use) { | |
2931 | I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, i), 0); | |
2932 | I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, i), 0); | |
2933 | I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, i), 0); | |
2934 | DRM_DEBUG_KMS("CRTC:%d Disabled scaler id %u.%u\n", | |
2935 | intel_crtc->base.base.id, intel_crtc->pipe, i); | |
2936 | } | |
2937 | } | |
2938 | } | |
2939 | ||
6156a456 | 2940 | u32 skl_plane_ctl_format(uint32_t pixel_format) |
70d21f0e | 2941 | { |
6156a456 | 2942 | switch (pixel_format) { |
d161cf7a | 2943 | case DRM_FORMAT_C8: |
c34ce3d1 | 2944 | return PLANE_CTL_FORMAT_INDEXED; |
70d21f0e | 2945 | case DRM_FORMAT_RGB565: |
c34ce3d1 | 2946 | return PLANE_CTL_FORMAT_RGB_565; |
70d21f0e | 2947 | case DRM_FORMAT_XBGR8888: |
c34ce3d1 | 2948 | return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX; |
6156a456 | 2949 | case DRM_FORMAT_XRGB8888: |
c34ce3d1 | 2950 | return PLANE_CTL_FORMAT_XRGB_8888; |
6156a456 CK |
2951 | /* |
2952 | * XXX: For ARBG/ABGR formats we default to expecting scanout buffers | |
2953 | * to be already pre-multiplied. We need to add a knob (or a different | |
2954 | * DRM_FORMAT) for user-space to configure that. | |
2955 | */ | |
f75fb42a | 2956 | case DRM_FORMAT_ABGR8888: |
c34ce3d1 | 2957 | return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX | |
6156a456 | 2958 | PLANE_CTL_ALPHA_SW_PREMULTIPLY; |
6156a456 | 2959 | case DRM_FORMAT_ARGB8888: |
c34ce3d1 | 2960 | return PLANE_CTL_FORMAT_XRGB_8888 | |
6156a456 | 2961 | PLANE_CTL_ALPHA_SW_PREMULTIPLY; |
70d21f0e | 2962 | case DRM_FORMAT_XRGB2101010: |
c34ce3d1 | 2963 | return PLANE_CTL_FORMAT_XRGB_2101010; |
70d21f0e | 2964 | case DRM_FORMAT_XBGR2101010: |
c34ce3d1 | 2965 | return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010; |
6156a456 | 2966 | case DRM_FORMAT_YUYV: |
c34ce3d1 | 2967 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV; |
6156a456 | 2968 | case DRM_FORMAT_YVYU: |
c34ce3d1 | 2969 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU; |
6156a456 | 2970 | case DRM_FORMAT_UYVY: |
c34ce3d1 | 2971 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY; |
6156a456 | 2972 | case DRM_FORMAT_VYUY: |
c34ce3d1 | 2973 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY; |
70d21f0e | 2974 | default: |
4249eeef | 2975 | MISSING_CASE(pixel_format); |
70d21f0e | 2976 | } |
8cfcba41 | 2977 | |
c34ce3d1 | 2978 | return 0; |
6156a456 | 2979 | } |
70d21f0e | 2980 | |
6156a456 CK |
2981 | u32 skl_plane_ctl_tiling(uint64_t fb_modifier) |
2982 | { | |
6156a456 | 2983 | switch (fb_modifier) { |
30af77c4 | 2984 | case DRM_FORMAT_MOD_NONE: |
70d21f0e | 2985 | break; |
30af77c4 | 2986 | case I915_FORMAT_MOD_X_TILED: |
c34ce3d1 | 2987 | return PLANE_CTL_TILED_X; |
b321803d | 2988 | case I915_FORMAT_MOD_Y_TILED: |
c34ce3d1 | 2989 | return PLANE_CTL_TILED_Y; |
b321803d | 2990 | case I915_FORMAT_MOD_Yf_TILED: |
c34ce3d1 | 2991 | return PLANE_CTL_TILED_YF; |
70d21f0e | 2992 | default: |
6156a456 | 2993 | MISSING_CASE(fb_modifier); |
70d21f0e | 2994 | } |
8cfcba41 | 2995 | |
c34ce3d1 | 2996 | return 0; |
6156a456 | 2997 | } |
70d21f0e | 2998 | |
6156a456 CK |
2999 | u32 skl_plane_ctl_rotation(unsigned int rotation) |
3000 | { | |
3b7a5119 | 3001 | switch (rotation) { |
6156a456 CK |
3002 | case BIT(DRM_ROTATE_0): |
3003 | break; | |
1e8df167 SJ |
3004 | /* |
3005 | * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr | |
3006 | * while i915 HW rotation is clockwise, thats why this swapping. | |
3007 | */ | |
3b7a5119 | 3008 | case BIT(DRM_ROTATE_90): |
1e8df167 | 3009 | return PLANE_CTL_ROTATE_270; |
3b7a5119 | 3010 | case BIT(DRM_ROTATE_180): |
c34ce3d1 | 3011 | return PLANE_CTL_ROTATE_180; |
3b7a5119 | 3012 | case BIT(DRM_ROTATE_270): |
1e8df167 | 3013 | return PLANE_CTL_ROTATE_90; |
6156a456 CK |
3014 | default: |
3015 | MISSING_CASE(rotation); | |
3016 | } | |
3017 | ||
c34ce3d1 | 3018 | return 0; |
6156a456 CK |
3019 | } |
3020 | ||
3021 | static void skylake_update_primary_plane(struct drm_crtc *crtc, | |
3022 | struct drm_framebuffer *fb, | |
3023 | int x, int y) | |
3024 | { | |
3025 | struct drm_device *dev = crtc->dev; | |
3026 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3027 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
b70709a6 ML |
3028 | struct drm_plane *plane = crtc->primary; |
3029 | bool visible = to_intel_plane_state(plane->state)->visible; | |
6156a456 CK |
3030 | struct drm_i915_gem_object *obj; |
3031 | int pipe = intel_crtc->pipe; | |
3032 | u32 plane_ctl, stride_div, stride; | |
3033 | u32 tile_height, plane_offset, plane_size; | |
3034 | unsigned int rotation; | |
3035 | int x_offset, y_offset; | |
3036 | unsigned long surf_addr; | |
6156a456 CK |
3037 | struct intel_crtc_state *crtc_state = intel_crtc->config; |
3038 | struct intel_plane_state *plane_state; | |
3039 | int src_x = 0, src_y = 0, src_w = 0, src_h = 0; | |
3040 | int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0; | |
3041 | int scaler_id = -1; | |
3042 | ||
6156a456 CK |
3043 | plane_state = to_intel_plane_state(plane->state); |
3044 | ||
b70709a6 | 3045 | if (!visible || !fb) { |
6156a456 CK |
3046 | I915_WRITE(PLANE_CTL(pipe, 0), 0); |
3047 | I915_WRITE(PLANE_SURF(pipe, 0), 0); | |
3048 | POSTING_READ(PLANE_CTL(pipe, 0)); | |
3049 | return; | |
3b7a5119 | 3050 | } |
70d21f0e | 3051 | |
6156a456 CK |
3052 | plane_ctl = PLANE_CTL_ENABLE | |
3053 | PLANE_CTL_PIPE_GAMMA_ENABLE | | |
3054 | PLANE_CTL_PIPE_CSC_ENABLE; | |
3055 | ||
3056 | plane_ctl |= skl_plane_ctl_format(fb->pixel_format); | |
3057 | plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]); | |
3058 | plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE; | |
3059 | ||
3060 | rotation = plane->state->rotation; | |
3061 | plane_ctl |= skl_plane_ctl_rotation(rotation); | |
3062 | ||
b321803d DL |
3063 | obj = intel_fb_obj(fb); |
3064 | stride_div = intel_fb_stride_alignment(dev, fb->modifier[0], | |
3065 | fb->pixel_format); | |
3b7a5119 SJ |
3066 | surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj); |
3067 | ||
6156a456 CK |
3068 | /* |
3069 | * FIXME: intel_plane_state->src, dst aren't set when transitional | |
3070 | * update_plane helpers are called from legacy paths. | |
3071 | * Once full atomic crtc is available, below check can be avoided. | |
3072 | */ | |
3073 | if (drm_rect_width(&plane_state->src)) { | |
3074 | scaler_id = plane_state->scaler_id; | |
3075 | src_x = plane_state->src.x1 >> 16; | |
3076 | src_y = plane_state->src.y1 >> 16; | |
3077 | src_w = drm_rect_width(&plane_state->src) >> 16; | |
3078 | src_h = drm_rect_height(&plane_state->src) >> 16; | |
3079 | dst_x = plane_state->dst.x1; | |
3080 | dst_y = plane_state->dst.y1; | |
3081 | dst_w = drm_rect_width(&plane_state->dst); | |
3082 | dst_h = drm_rect_height(&plane_state->dst); | |
3083 | ||
3084 | WARN_ON(x != src_x || y != src_y); | |
3085 | } else { | |
3086 | src_w = intel_crtc->config->pipe_src_w; | |
3087 | src_h = intel_crtc->config->pipe_src_h; | |
3088 | } | |
3089 | ||
3b7a5119 SJ |
3090 | if (intel_rotation_90_or_270(rotation)) { |
3091 | /* stride = Surface height in tiles */ | |
2614f17d | 3092 | tile_height = intel_tile_height(dev, fb->pixel_format, |
3b7a5119 SJ |
3093 | fb->modifier[0]); |
3094 | stride = DIV_ROUND_UP(fb->height, tile_height); | |
6156a456 | 3095 | x_offset = stride * tile_height - y - src_h; |
3b7a5119 | 3096 | y_offset = x; |
6156a456 | 3097 | plane_size = (src_w - 1) << 16 | (src_h - 1); |
3b7a5119 SJ |
3098 | } else { |
3099 | stride = fb->pitches[0] / stride_div; | |
3100 | x_offset = x; | |
3101 | y_offset = y; | |
6156a456 | 3102 | plane_size = (src_h - 1) << 16 | (src_w - 1); |
3b7a5119 SJ |
3103 | } |
3104 | plane_offset = y_offset << 16 | x_offset; | |
b321803d | 3105 | |
70d21f0e | 3106 | I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl); |
3b7a5119 SJ |
3107 | I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset); |
3108 | I915_WRITE(PLANE_SIZE(pipe, 0), plane_size); | |
3109 | I915_WRITE(PLANE_STRIDE(pipe, 0), stride); | |
6156a456 CK |
3110 | |
3111 | if (scaler_id >= 0) { | |
3112 | uint32_t ps_ctrl = 0; | |
3113 | ||
3114 | WARN_ON(!dst_w || !dst_h); | |
3115 | ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) | | |
3116 | crtc_state->scaler_state.scalers[scaler_id].mode; | |
3117 | I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl); | |
3118 | I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0); | |
3119 | I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y); | |
3120 | I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h); | |
3121 | I915_WRITE(PLANE_POS(pipe, 0), 0); | |
3122 | } else { | |
3123 | I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x); | |
3124 | } | |
3125 | ||
121920fa | 3126 | I915_WRITE(PLANE_SURF(pipe, 0), surf_addr); |
70d21f0e DL |
3127 | |
3128 | POSTING_READ(PLANE_SURF(pipe, 0)); | |
3129 | } | |
3130 | ||
17638cd6 JB |
3131 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ |
3132 | static int | |
3133 | intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, | |
3134 | int x, int y, enum mode_set_atomic state) | |
3135 | { | |
3136 | struct drm_device *dev = crtc->dev; | |
3137 | struct drm_i915_private *dev_priv = dev->dev_private; | |
17638cd6 | 3138 | |
6b8e6ed0 CW |
3139 | if (dev_priv->display.disable_fbc) |
3140 | dev_priv->display.disable_fbc(dev); | |
81255565 | 3141 | |
29b9bde6 DV |
3142 | dev_priv->display.update_primary_plane(crtc, fb, x, y); |
3143 | ||
3144 | return 0; | |
81255565 JB |
3145 | } |
3146 | ||
7514747d | 3147 | static void intel_complete_page_flips(struct drm_device *dev) |
96a02917 | 3148 | { |
96a02917 VS |
3149 | struct drm_crtc *crtc; |
3150 | ||
70e1e0ec | 3151 | for_each_crtc(dev, crtc) { |
96a02917 VS |
3152 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3153 | enum plane plane = intel_crtc->plane; | |
3154 | ||
3155 | intel_prepare_page_flip(dev, plane); | |
3156 | intel_finish_page_flip_plane(dev, plane); | |
3157 | } | |
7514747d VS |
3158 | } |
3159 | ||
3160 | static void intel_update_primary_planes(struct drm_device *dev) | |
3161 | { | |
3162 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3163 | struct drm_crtc *crtc; | |
96a02917 | 3164 | |
70e1e0ec | 3165 | for_each_crtc(dev, crtc) { |
96a02917 VS |
3166 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3167 | ||
51fd371b | 3168 | drm_modeset_lock(&crtc->mutex, NULL); |
947fdaad CW |
3169 | /* |
3170 | * FIXME: Once we have proper support for primary planes (and | |
3171 | * disabling them without disabling the entire crtc) allow again | |
66e514c1 | 3172 | * a NULL crtc->primary->fb. |
947fdaad | 3173 | */ |
f4510a27 | 3174 | if (intel_crtc->active && crtc->primary->fb) |
262ca2b0 | 3175 | dev_priv->display.update_primary_plane(crtc, |
66e514c1 | 3176 | crtc->primary->fb, |
262ca2b0 MR |
3177 | crtc->x, |
3178 | crtc->y); | |
51fd371b | 3179 | drm_modeset_unlock(&crtc->mutex); |
96a02917 VS |
3180 | } |
3181 | } | |
3182 | ||
7514747d VS |
3183 | void intel_prepare_reset(struct drm_device *dev) |
3184 | { | |
3185 | /* no reset support for gen2 */ | |
3186 | if (IS_GEN2(dev)) | |
3187 | return; | |
3188 | ||
3189 | /* reset doesn't touch the display */ | |
3190 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) | |
3191 | return; | |
3192 | ||
3193 | drm_modeset_lock_all(dev); | |
f98ce92f VS |
3194 | /* |
3195 | * Disabling the crtcs gracefully seems nicer. Also the | |
3196 | * g33 docs say we should at least disable all the planes. | |
3197 | */ | |
6b72d486 | 3198 | intel_display_suspend(dev); |
7514747d VS |
3199 | } |
3200 | ||
3201 | void intel_finish_reset(struct drm_device *dev) | |
3202 | { | |
3203 | struct drm_i915_private *dev_priv = to_i915(dev); | |
3204 | ||
3205 | /* | |
3206 | * Flips in the rings will be nuked by the reset, | |
3207 | * so complete all pending flips so that user space | |
3208 | * will get its events and not get stuck. | |
3209 | */ | |
3210 | intel_complete_page_flips(dev); | |
3211 | ||
3212 | /* no reset support for gen2 */ | |
3213 | if (IS_GEN2(dev)) | |
3214 | return; | |
3215 | ||
3216 | /* reset doesn't touch the display */ | |
3217 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) { | |
3218 | /* | |
3219 | * Flips in the rings have been nuked by the reset, | |
3220 | * so update the base address of all primary | |
3221 | * planes to the the last fb to make sure we're | |
3222 | * showing the correct fb after a reset. | |
3223 | */ | |
3224 | intel_update_primary_planes(dev); | |
3225 | return; | |
3226 | } | |
3227 | ||
3228 | /* | |
3229 | * The display has been reset as well, | |
3230 | * so need a full re-initialization. | |
3231 | */ | |
3232 | intel_runtime_pm_disable_interrupts(dev_priv); | |
3233 | intel_runtime_pm_enable_interrupts(dev_priv); | |
3234 | ||
3235 | intel_modeset_init_hw(dev); | |
3236 | ||
3237 | spin_lock_irq(&dev_priv->irq_lock); | |
3238 | if (dev_priv->display.hpd_irq_setup) | |
3239 | dev_priv->display.hpd_irq_setup(dev); | |
3240 | spin_unlock_irq(&dev_priv->irq_lock); | |
3241 | ||
3242 | intel_modeset_setup_hw_state(dev, true); | |
3243 | ||
3244 | intel_hpd_init(dev_priv); | |
3245 | ||
3246 | drm_modeset_unlock_all(dev); | |
3247 | } | |
3248 | ||
2e2f351d | 3249 | static void |
14667a4b CW |
3250 | intel_finish_fb(struct drm_framebuffer *old_fb) |
3251 | { | |
2ff8fde1 | 3252 | struct drm_i915_gem_object *obj = intel_fb_obj(old_fb); |
2e2f351d | 3253 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
14667a4b CW |
3254 | bool was_interruptible = dev_priv->mm.interruptible; |
3255 | int ret; | |
3256 | ||
14667a4b CW |
3257 | /* Big Hammer, we also need to ensure that any pending |
3258 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the | |
3259 | * current scanout is retired before unpinning the old | |
2e2f351d CW |
3260 | * framebuffer. Note that we rely on userspace rendering |
3261 | * into the buffer attached to the pipe they are waiting | |
3262 | * on. If not, userspace generates a GPU hang with IPEHR | |
3263 | * point to the MI_WAIT_FOR_EVENT. | |
14667a4b CW |
3264 | * |
3265 | * This should only fail upon a hung GPU, in which case we | |
3266 | * can safely continue. | |
3267 | */ | |
3268 | dev_priv->mm.interruptible = false; | |
2e2f351d | 3269 | ret = i915_gem_object_wait_rendering(obj, true); |
14667a4b CW |
3270 | dev_priv->mm.interruptible = was_interruptible; |
3271 | ||
2e2f351d | 3272 | WARN_ON(ret); |
14667a4b CW |
3273 | } |
3274 | ||
7d5e3799 CW |
3275 | static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) |
3276 | { | |
3277 | struct drm_device *dev = crtc->dev; | |
3278 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3279 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7d5e3799 CW |
3280 | bool pending; |
3281 | ||
3282 | if (i915_reset_in_progress(&dev_priv->gpu_error) || | |
3283 | intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) | |
3284 | return false; | |
3285 | ||
5e2d7afc | 3286 | spin_lock_irq(&dev->event_lock); |
7d5e3799 | 3287 | pending = to_intel_crtc(crtc)->unpin_work != NULL; |
5e2d7afc | 3288 | spin_unlock_irq(&dev->event_lock); |
7d5e3799 CW |
3289 | |
3290 | return pending; | |
3291 | } | |
3292 | ||
e30e8f75 GP |
3293 | static void intel_update_pipe_size(struct intel_crtc *crtc) |
3294 | { | |
3295 | struct drm_device *dev = crtc->base.dev; | |
3296 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3297 | const struct drm_display_mode *adjusted_mode; | |
3298 | ||
3299 | if (!i915.fastboot) | |
3300 | return; | |
3301 | ||
3302 | /* | |
3303 | * Update pipe size and adjust fitter if needed: the reason for this is | |
3304 | * that in compute_mode_changes we check the native mode (not the pfit | |
3305 | * mode) to see if we can flip rather than do a full mode set. In the | |
3306 | * fastboot case, we'll flip, but if we don't update the pipesrc and | |
3307 | * pfit state, we'll end up with a big fb scanned out into the wrong | |
3308 | * sized surface. | |
3309 | * | |
3310 | * To fix this properly, we need to hoist the checks up into | |
3311 | * compute_mode_changes (or above), check the actual pfit state and | |
3312 | * whether the platform allows pfit disable with pipe active, and only | |
3313 | * then update the pipesrc and pfit state, even on the flip path. | |
3314 | */ | |
3315 | ||
6e3c9717 | 3316 | adjusted_mode = &crtc->config->base.adjusted_mode; |
e30e8f75 GP |
3317 | |
3318 | I915_WRITE(PIPESRC(crtc->pipe), | |
3319 | ((adjusted_mode->crtc_hdisplay - 1) << 16) | | |
3320 | (adjusted_mode->crtc_vdisplay - 1)); | |
6e3c9717 | 3321 | if (!crtc->config->pch_pfit.enabled && |
409ee761 ACO |
3322 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || |
3323 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) { | |
e30e8f75 GP |
3324 | I915_WRITE(PF_CTL(crtc->pipe), 0); |
3325 | I915_WRITE(PF_WIN_POS(crtc->pipe), 0); | |
3326 | I915_WRITE(PF_WIN_SZ(crtc->pipe), 0); | |
3327 | } | |
6e3c9717 ACO |
3328 | crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay; |
3329 | crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay; | |
e30e8f75 GP |
3330 | } |
3331 | ||
5e84e1a4 ZW |
3332 | static void intel_fdi_normal_train(struct drm_crtc *crtc) |
3333 | { | |
3334 | struct drm_device *dev = crtc->dev; | |
3335 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3336 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3337 | int pipe = intel_crtc->pipe; | |
3338 | u32 reg, temp; | |
3339 | ||
3340 | /* enable normal train */ | |
3341 | reg = FDI_TX_CTL(pipe); | |
3342 | temp = I915_READ(reg); | |
61e499bf | 3343 | if (IS_IVYBRIDGE(dev)) { |
357555c0 JB |
3344 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3345 | temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; | |
61e499bf KP |
3346 | } else { |
3347 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3348 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; | |
357555c0 | 3349 | } |
5e84e1a4 ZW |
3350 | I915_WRITE(reg, temp); |
3351 | ||
3352 | reg = FDI_RX_CTL(pipe); | |
3353 | temp = I915_READ(reg); | |
3354 | if (HAS_PCH_CPT(dev)) { | |
3355 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3356 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; | |
3357 | } else { | |
3358 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3359 | temp |= FDI_LINK_TRAIN_NONE; | |
3360 | } | |
3361 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); | |
3362 | ||
3363 | /* wait one idle pattern time */ | |
3364 | POSTING_READ(reg); | |
3365 | udelay(1000); | |
357555c0 JB |
3366 | |
3367 | /* IVB wants error correction enabled */ | |
3368 | if (IS_IVYBRIDGE(dev)) | |
3369 | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | | |
3370 | FDI_FE_ERRC_ENABLE); | |
5e84e1a4 ZW |
3371 | } |
3372 | ||
8db9d77b ZW |
3373 | /* The FDI link training functions for ILK/Ibexpeak. */ |
3374 | static void ironlake_fdi_link_train(struct drm_crtc *crtc) | |
3375 | { | |
3376 | struct drm_device *dev = crtc->dev; | |
3377 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3378 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3379 | int pipe = intel_crtc->pipe; | |
5eddb70b | 3380 | u32 reg, temp, tries; |
8db9d77b | 3381 | |
1c8562f6 | 3382 | /* FDI needs bits from pipe first */ |
0fc932b8 | 3383 | assert_pipe_enabled(dev_priv, pipe); |
0fc932b8 | 3384 | |
e1a44743 AJ |
3385 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3386 | for train result */ | |
5eddb70b CW |
3387 | reg = FDI_RX_IMR(pipe); |
3388 | temp = I915_READ(reg); | |
e1a44743 AJ |
3389 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3390 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3391 | I915_WRITE(reg, temp); |
3392 | I915_READ(reg); | |
e1a44743 AJ |
3393 | udelay(150); |
3394 | ||
8db9d77b | 3395 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3396 | reg = FDI_TX_CTL(pipe); |
3397 | temp = I915_READ(reg); | |
627eb5a3 | 3398 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3399 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
8db9d77b ZW |
3400 | temp &= ~FDI_LINK_TRAIN_NONE; |
3401 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b | 3402 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3403 | |
5eddb70b CW |
3404 | reg = FDI_RX_CTL(pipe); |
3405 | temp = I915_READ(reg); | |
8db9d77b ZW |
3406 | temp &= ~FDI_LINK_TRAIN_NONE; |
3407 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b CW |
3408 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3409 | ||
3410 | POSTING_READ(reg); | |
8db9d77b ZW |
3411 | udelay(150); |
3412 | ||
5b2adf89 | 3413 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
8f5718a6 DV |
3414 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
3415 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | | |
3416 | FDI_RX_PHASE_SYNC_POINTER_EN); | |
5b2adf89 | 3417 | |
5eddb70b | 3418 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3419 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3420 | temp = I915_READ(reg); |
8db9d77b ZW |
3421 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3422 | ||
3423 | if ((temp & FDI_RX_BIT_LOCK)) { | |
3424 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
5eddb70b | 3425 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
8db9d77b ZW |
3426 | break; |
3427 | } | |
8db9d77b | 3428 | } |
e1a44743 | 3429 | if (tries == 5) |
5eddb70b | 3430 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3431 | |
3432 | /* Train 2 */ | |
5eddb70b CW |
3433 | reg = FDI_TX_CTL(pipe); |
3434 | temp = I915_READ(reg); | |
8db9d77b ZW |
3435 | temp &= ~FDI_LINK_TRAIN_NONE; |
3436 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3437 | I915_WRITE(reg, temp); |
8db9d77b | 3438 | |
5eddb70b CW |
3439 | reg = FDI_RX_CTL(pipe); |
3440 | temp = I915_READ(reg); | |
8db9d77b ZW |
3441 | temp &= ~FDI_LINK_TRAIN_NONE; |
3442 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3443 | I915_WRITE(reg, temp); |
8db9d77b | 3444 | |
5eddb70b CW |
3445 | POSTING_READ(reg); |
3446 | udelay(150); | |
8db9d77b | 3447 | |
5eddb70b | 3448 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3449 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3450 | temp = I915_READ(reg); |
8db9d77b ZW |
3451 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3452 | ||
3453 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
5eddb70b | 3454 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
8db9d77b ZW |
3455 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
3456 | break; | |
3457 | } | |
8db9d77b | 3458 | } |
e1a44743 | 3459 | if (tries == 5) |
5eddb70b | 3460 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3461 | |
3462 | DRM_DEBUG_KMS("FDI train done\n"); | |
5c5313c8 | 3463 | |
8db9d77b ZW |
3464 | } |
3465 | ||
0206e353 | 3466 | static const int snb_b_fdi_train_param[] = { |
8db9d77b ZW |
3467 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
3468 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, | |
3469 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, | |
3470 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, | |
3471 | }; | |
3472 | ||
3473 | /* The FDI link training functions for SNB/Cougarpoint. */ | |
3474 | static void gen6_fdi_link_train(struct drm_crtc *crtc) | |
3475 | { | |
3476 | struct drm_device *dev = crtc->dev; | |
3477 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3478 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3479 | int pipe = intel_crtc->pipe; | |
fa37d39e | 3480 | u32 reg, temp, i, retry; |
8db9d77b | 3481 | |
e1a44743 AJ |
3482 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3483 | for train result */ | |
5eddb70b CW |
3484 | reg = FDI_RX_IMR(pipe); |
3485 | temp = I915_READ(reg); | |
e1a44743 AJ |
3486 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3487 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3488 | I915_WRITE(reg, temp); |
3489 | ||
3490 | POSTING_READ(reg); | |
e1a44743 AJ |
3491 | udelay(150); |
3492 | ||
8db9d77b | 3493 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3494 | reg = FDI_TX_CTL(pipe); |
3495 | temp = I915_READ(reg); | |
627eb5a3 | 3496 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3497 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
8db9d77b ZW |
3498 | temp &= ~FDI_LINK_TRAIN_NONE; |
3499 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3500 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3501 | /* SNB-B */ | |
3502 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
5eddb70b | 3503 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3504 | |
d74cf324 DV |
3505 | I915_WRITE(FDI_RX_MISC(pipe), |
3506 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
3507 | ||
5eddb70b CW |
3508 | reg = FDI_RX_CTL(pipe); |
3509 | temp = I915_READ(reg); | |
8db9d77b ZW |
3510 | if (HAS_PCH_CPT(dev)) { |
3511 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3512 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3513 | } else { | |
3514 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3515 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3516 | } | |
5eddb70b CW |
3517 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3518 | ||
3519 | POSTING_READ(reg); | |
8db9d77b ZW |
3520 | udelay(150); |
3521 | ||
0206e353 | 3522 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3523 | reg = FDI_TX_CTL(pipe); |
3524 | temp = I915_READ(reg); | |
8db9d77b ZW |
3525 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3526 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3527 | I915_WRITE(reg, temp); |
3528 | ||
3529 | POSTING_READ(reg); | |
8db9d77b ZW |
3530 | udelay(500); |
3531 | ||
fa37d39e SP |
3532 | for (retry = 0; retry < 5; retry++) { |
3533 | reg = FDI_RX_IIR(pipe); | |
3534 | temp = I915_READ(reg); | |
3535 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3536 | if (temp & FDI_RX_BIT_LOCK) { | |
3537 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3538 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
3539 | break; | |
3540 | } | |
3541 | udelay(50); | |
8db9d77b | 3542 | } |
fa37d39e SP |
3543 | if (retry < 5) |
3544 | break; | |
8db9d77b ZW |
3545 | } |
3546 | if (i == 4) | |
5eddb70b | 3547 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3548 | |
3549 | /* Train 2 */ | |
5eddb70b CW |
3550 | reg = FDI_TX_CTL(pipe); |
3551 | temp = I915_READ(reg); | |
8db9d77b ZW |
3552 | temp &= ~FDI_LINK_TRAIN_NONE; |
3553 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3554 | if (IS_GEN6(dev)) { | |
3555 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3556 | /* SNB-B */ | |
3557 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
3558 | } | |
5eddb70b | 3559 | I915_WRITE(reg, temp); |
8db9d77b | 3560 | |
5eddb70b CW |
3561 | reg = FDI_RX_CTL(pipe); |
3562 | temp = I915_READ(reg); | |
8db9d77b ZW |
3563 | if (HAS_PCH_CPT(dev)) { |
3564 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3565 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
3566 | } else { | |
3567 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3568 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3569 | } | |
5eddb70b CW |
3570 | I915_WRITE(reg, temp); |
3571 | ||
3572 | POSTING_READ(reg); | |
8db9d77b ZW |
3573 | udelay(150); |
3574 | ||
0206e353 | 3575 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3576 | reg = FDI_TX_CTL(pipe); |
3577 | temp = I915_READ(reg); | |
8db9d77b ZW |
3578 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3579 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3580 | I915_WRITE(reg, temp); |
3581 | ||
3582 | POSTING_READ(reg); | |
8db9d77b ZW |
3583 | udelay(500); |
3584 | ||
fa37d39e SP |
3585 | for (retry = 0; retry < 5; retry++) { |
3586 | reg = FDI_RX_IIR(pipe); | |
3587 | temp = I915_READ(reg); | |
3588 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3589 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
3590 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3591 | DRM_DEBUG_KMS("FDI train 2 done.\n"); | |
3592 | break; | |
3593 | } | |
3594 | udelay(50); | |
8db9d77b | 3595 | } |
fa37d39e SP |
3596 | if (retry < 5) |
3597 | break; | |
8db9d77b ZW |
3598 | } |
3599 | if (i == 4) | |
5eddb70b | 3600 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3601 | |
3602 | DRM_DEBUG_KMS("FDI train done.\n"); | |
3603 | } | |
3604 | ||
357555c0 JB |
3605 | /* Manual link training for Ivy Bridge A0 parts */ |
3606 | static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) | |
3607 | { | |
3608 | struct drm_device *dev = crtc->dev; | |
3609 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3610 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3611 | int pipe = intel_crtc->pipe; | |
139ccd3f | 3612 | u32 reg, temp, i, j; |
357555c0 JB |
3613 | |
3614 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit | |
3615 | for train result */ | |
3616 | reg = FDI_RX_IMR(pipe); | |
3617 | temp = I915_READ(reg); | |
3618 | temp &= ~FDI_RX_SYMBOL_LOCK; | |
3619 | temp &= ~FDI_RX_BIT_LOCK; | |
3620 | I915_WRITE(reg, temp); | |
3621 | ||
3622 | POSTING_READ(reg); | |
3623 | udelay(150); | |
3624 | ||
01a415fd DV |
3625 | DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n", |
3626 | I915_READ(FDI_RX_IIR(pipe))); | |
3627 | ||
139ccd3f JB |
3628 | /* Try each vswing and preemphasis setting twice before moving on */ |
3629 | for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) { | |
3630 | /* disable first in case we need to retry */ | |
3631 | reg = FDI_TX_CTL(pipe); | |
3632 | temp = I915_READ(reg); | |
3633 | temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); | |
3634 | temp &= ~FDI_TX_ENABLE; | |
3635 | I915_WRITE(reg, temp); | |
357555c0 | 3636 | |
139ccd3f JB |
3637 | reg = FDI_RX_CTL(pipe); |
3638 | temp = I915_READ(reg); | |
3639 | temp &= ~FDI_LINK_TRAIN_AUTO; | |
3640 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3641 | temp &= ~FDI_RX_ENABLE; | |
3642 | I915_WRITE(reg, temp); | |
357555c0 | 3643 | |
139ccd3f | 3644 | /* enable CPU FDI TX and PCH FDI RX */ |
357555c0 JB |
3645 | reg = FDI_TX_CTL(pipe); |
3646 | temp = I915_READ(reg); | |
139ccd3f | 3647 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3648 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
139ccd3f | 3649 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; |
357555c0 | 3650 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
139ccd3f JB |
3651 | temp |= snb_b_fdi_train_param[j/2]; |
3652 | temp |= FDI_COMPOSITE_SYNC; | |
3653 | I915_WRITE(reg, temp | FDI_TX_ENABLE); | |
357555c0 | 3654 | |
139ccd3f JB |
3655 | I915_WRITE(FDI_RX_MISC(pipe), |
3656 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
357555c0 | 3657 | |
139ccd3f | 3658 | reg = FDI_RX_CTL(pipe); |
357555c0 | 3659 | temp = I915_READ(reg); |
139ccd3f JB |
3660 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
3661 | temp |= FDI_COMPOSITE_SYNC; | |
3662 | I915_WRITE(reg, temp | FDI_RX_ENABLE); | |
357555c0 | 3663 | |
139ccd3f JB |
3664 | POSTING_READ(reg); |
3665 | udelay(1); /* should be 0.5us */ | |
357555c0 | 3666 | |
139ccd3f JB |
3667 | for (i = 0; i < 4; i++) { |
3668 | reg = FDI_RX_IIR(pipe); | |
3669 | temp = I915_READ(reg); | |
3670 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 3671 | |
139ccd3f JB |
3672 | if (temp & FDI_RX_BIT_LOCK || |
3673 | (I915_READ(reg) & FDI_RX_BIT_LOCK)) { | |
3674 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3675 | DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", | |
3676 | i); | |
3677 | break; | |
3678 | } | |
3679 | udelay(1); /* should be 0.5us */ | |
3680 | } | |
3681 | if (i == 4) { | |
3682 | DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2); | |
3683 | continue; | |
3684 | } | |
357555c0 | 3685 | |
139ccd3f | 3686 | /* Train 2 */ |
357555c0 JB |
3687 | reg = FDI_TX_CTL(pipe); |
3688 | temp = I915_READ(reg); | |
139ccd3f JB |
3689 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3690 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; | |
3691 | I915_WRITE(reg, temp); | |
3692 | ||
3693 | reg = FDI_RX_CTL(pipe); | |
3694 | temp = I915_READ(reg); | |
3695 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3696 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
357555c0 JB |
3697 | I915_WRITE(reg, temp); |
3698 | ||
3699 | POSTING_READ(reg); | |
139ccd3f | 3700 | udelay(2); /* should be 1.5us */ |
357555c0 | 3701 | |
139ccd3f JB |
3702 | for (i = 0; i < 4; i++) { |
3703 | reg = FDI_RX_IIR(pipe); | |
3704 | temp = I915_READ(reg); | |
3705 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 3706 | |
139ccd3f JB |
3707 | if (temp & FDI_RX_SYMBOL_LOCK || |
3708 | (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) { | |
3709 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3710 | DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", | |
3711 | i); | |
3712 | goto train_done; | |
3713 | } | |
3714 | udelay(2); /* should be 1.5us */ | |
357555c0 | 3715 | } |
139ccd3f JB |
3716 | if (i == 4) |
3717 | DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2); | |
357555c0 | 3718 | } |
357555c0 | 3719 | |
139ccd3f | 3720 | train_done: |
357555c0 JB |
3721 | DRM_DEBUG_KMS("FDI train done.\n"); |
3722 | } | |
3723 | ||
88cefb6c | 3724 | static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) |
2c07245f | 3725 | { |
88cefb6c | 3726 | struct drm_device *dev = intel_crtc->base.dev; |
2c07245f | 3727 | struct drm_i915_private *dev_priv = dev->dev_private; |
2c07245f | 3728 | int pipe = intel_crtc->pipe; |
5eddb70b | 3729 | u32 reg, temp; |
79e53945 | 3730 | |
c64e311e | 3731 | |
c98e9dcf | 3732 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
5eddb70b CW |
3733 | reg = FDI_RX_CTL(pipe); |
3734 | temp = I915_READ(reg); | |
627eb5a3 | 3735 | temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16)); |
6e3c9717 | 3736 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
dfd07d72 | 3737 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
5eddb70b CW |
3738 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); |
3739 | ||
3740 | POSTING_READ(reg); | |
c98e9dcf JB |
3741 | udelay(200); |
3742 | ||
3743 | /* Switch from Rawclk to PCDclk */ | |
5eddb70b CW |
3744 | temp = I915_READ(reg); |
3745 | I915_WRITE(reg, temp | FDI_PCDCLK); | |
3746 | ||
3747 | POSTING_READ(reg); | |
c98e9dcf JB |
3748 | udelay(200); |
3749 | ||
20749730 PZ |
3750 | /* Enable CPU FDI TX PLL, always on for Ironlake */ |
3751 | reg = FDI_TX_CTL(pipe); | |
3752 | temp = I915_READ(reg); | |
3753 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { | |
3754 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); | |
5eddb70b | 3755 | |
20749730 PZ |
3756 | POSTING_READ(reg); |
3757 | udelay(100); | |
6be4a607 | 3758 | } |
0e23b99d JB |
3759 | } |
3760 | ||
88cefb6c DV |
3761 | static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc) |
3762 | { | |
3763 | struct drm_device *dev = intel_crtc->base.dev; | |
3764 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3765 | int pipe = intel_crtc->pipe; | |
3766 | u32 reg, temp; | |
3767 | ||
3768 | /* Switch from PCDclk to Rawclk */ | |
3769 | reg = FDI_RX_CTL(pipe); | |
3770 | temp = I915_READ(reg); | |
3771 | I915_WRITE(reg, temp & ~FDI_PCDCLK); | |
3772 | ||
3773 | /* Disable CPU FDI TX PLL */ | |
3774 | reg = FDI_TX_CTL(pipe); | |
3775 | temp = I915_READ(reg); | |
3776 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); | |
3777 | ||
3778 | POSTING_READ(reg); | |
3779 | udelay(100); | |
3780 | ||
3781 | reg = FDI_RX_CTL(pipe); | |
3782 | temp = I915_READ(reg); | |
3783 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); | |
3784 | ||
3785 | /* Wait for the clocks to turn off. */ | |
3786 | POSTING_READ(reg); | |
3787 | udelay(100); | |
3788 | } | |
3789 | ||
0fc932b8 JB |
3790 | static void ironlake_fdi_disable(struct drm_crtc *crtc) |
3791 | { | |
3792 | struct drm_device *dev = crtc->dev; | |
3793 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3794 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3795 | int pipe = intel_crtc->pipe; | |
3796 | u32 reg, temp; | |
3797 | ||
3798 | /* disable CPU FDI tx and PCH FDI rx */ | |
3799 | reg = FDI_TX_CTL(pipe); | |
3800 | temp = I915_READ(reg); | |
3801 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); | |
3802 | POSTING_READ(reg); | |
3803 | ||
3804 | reg = FDI_RX_CTL(pipe); | |
3805 | temp = I915_READ(reg); | |
3806 | temp &= ~(0x7 << 16); | |
dfd07d72 | 3807 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
3808 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); |
3809 | ||
3810 | POSTING_READ(reg); | |
3811 | udelay(100); | |
3812 | ||
3813 | /* Ironlake workaround, disable clock pointer after downing FDI */ | |
eba905b2 | 3814 | if (HAS_PCH_IBX(dev)) |
6f06ce18 | 3815 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
0fc932b8 JB |
3816 | |
3817 | /* still set train pattern 1 */ | |
3818 | reg = FDI_TX_CTL(pipe); | |
3819 | temp = I915_READ(reg); | |
3820 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3821 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3822 | I915_WRITE(reg, temp); | |
3823 | ||
3824 | reg = FDI_RX_CTL(pipe); | |
3825 | temp = I915_READ(reg); | |
3826 | if (HAS_PCH_CPT(dev)) { | |
3827 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3828 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3829 | } else { | |
3830 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3831 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3832 | } | |
3833 | /* BPC in FDI rx is consistent with that in PIPECONF */ | |
3834 | temp &= ~(0x07 << 16); | |
dfd07d72 | 3835 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
3836 | I915_WRITE(reg, temp); |
3837 | ||
3838 | POSTING_READ(reg); | |
3839 | udelay(100); | |
3840 | } | |
3841 | ||
5dce5b93 CW |
3842 | bool intel_has_pending_fb_unpin(struct drm_device *dev) |
3843 | { | |
3844 | struct intel_crtc *crtc; | |
3845 | ||
3846 | /* Note that we don't need to be called with mode_config.lock here | |
3847 | * as our list of CRTC objects is static for the lifetime of the | |
3848 | * device and so cannot disappear as we iterate. Similarly, we can | |
3849 | * happily treat the predicates as racy, atomic checks as userspace | |
3850 | * cannot claim and pin a new fb without at least acquring the | |
3851 | * struct_mutex and so serialising with us. | |
3852 | */ | |
d3fcc808 | 3853 | for_each_intel_crtc(dev, crtc) { |
5dce5b93 CW |
3854 | if (atomic_read(&crtc->unpin_work_count) == 0) |
3855 | continue; | |
3856 | ||
3857 | if (crtc->unpin_work) | |
3858 | intel_wait_for_vblank(dev, crtc->pipe); | |
3859 | ||
3860 | return true; | |
3861 | } | |
3862 | ||
3863 | return false; | |
3864 | } | |
3865 | ||
d6bbafa1 CW |
3866 | static void page_flip_completed(struct intel_crtc *intel_crtc) |
3867 | { | |
3868 | struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); | |
3869 | struct intel_unpin_work *work = intel_crtc->unpin_work; | |
3870 | ||
3871 | /* ensure that the unpin work is consistent wrt ->pending. */ | |
3872 | smp_rmb(); | |
3873 | intel_crtc->unpin_work = NULL; | |
3874 | ||
3875 | if (work->event) | |
3876 | drm_send_vblank_event(intel_crtc->base.dev, | |
3877 | intel_crtc->pipe, | |
3878 | work->event); | |
3879 | ||
3880 | drm_crtc_vblank_put(&intel_crtc->base); | |
3881 | ||
3882 | wake_up_all(&dev_priv->pending_flip_queue); | |
3883 | queue_work(dev_priv->wq, &work->work); | |
3884 | ||
3885 | trace_i915_flip_complete(intel_crtc->plane, | |
3886 | work->pending_flip_obj); | |
3887 | } | |
3888 | ||
46a55d30 | 3889 | void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) |
e6c3a2a6 | 3890 | { |
0f91128d | 3891 | struct drm_device *dev = crtc->dev; |
5bb61643 | 3892 | struct drm_i915_private *dev_priv = dev->dev_private; |
e6c3a2a6 | 3893 | |
2c10d571 | 3894 | WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue)); |
9c787942 CW |
3895 | if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue, |
3896 | !intel_crtc_has_pending_flip(crtc), | |
3897 | 60*HZ) == 0)) { | |
3898 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2c10d571 | 3899 | |
5e2d7afc | 3900 | spin_lock_irq(&dev->event_lock); |
9c787942 CW |
3901 | if (intel_crtc->unpin_work) { |
3902 | WARN_ONCE(1, "Removing stuck page flip\n"); | |
3903 | page_flip_completed(intel_crtc); | |
3904 | } | |
5e2d7afc | 3905 | spin_unlock_irq(&dev->event_lock); |
9c787942 | 3906 | } |
5bb61643 | 3907 | |
975d568a CW |
3908 | if (crtc->primary->fb) { |
3909 | mutex_lock(&dev->struct_mutex); | |
3910 | intel_finish_fb(crtc->primary->fb); | |
3911 | mutex_unlock(&dev->struct_mutex); | |
3912 | } | |
e6c3a2a6 CW |
3913 | } |
3914 | ||
e615efe4 ED |
3915 | /* Program iCLKIP clock to the desired frequency */ |
3916 | static void lpt_program_iclkip(struct drm_crtc *crtc) | |
3917 | { | |
3918 | struct drm_device *dev = crtc->dev; | |
3919 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6e3c9717 | 3920 | int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock; |
e615efe4 ED |
3921 | u32 divsel, phaseinc, auxdiv, phasedir = 0; |
3922 | u32 temp; | |
3923 | ||
a580516d | 3924 | mutex_lock(&dev_priv->sb_lock); |
09153000 | 3925 | |
e615efe4 ED |
3926 | /* It is necessary to ungate the pixclk gate prior to programming |
3927 | * the divisors, and gate it back when it is done. | |
3928 | */ | |
3929 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE); | |
3930 | ||
3931 | /* Disable SSCCTL */ | |
3932 | intel_sbi_write(dev_priv, SBI_SSCCTL6, | |
988d6ee8 PZ |
3933 | intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) | |
3934 | SBI_SSCCTL_DISABLE, | |
3935 | SBI_ICLK); | |
e615efe4 ED |
3936 | |
3937 | /* 20MHz is a corner case which is out of range for the 7-bit divisor */ | |
12d7ceed | 3938 | if (clock == 20000) { |
e615efe4 ED |
3939 | auxdiv = 1; |
3940 | divsel = 0x41; | |
3941 | phaseinc = 0x20; | |
3942 | } else { | |
3943 | /* The iCLK virtual clock root frequency is in MHz, | |
241bfc38 DL |
3944 | * but the adjusted_mode->crtc_clock in in KHz. To get the |
3945 | * divisors, it is necessary to divide one by another, so we | |
e615efe4 ED |
3946 | * convert the virtual clock precision to KHz here for higher |
3947 | * precision. | |
3948 | */ | |
3949 | u32 iclk_virtual_root_freq = 172800 * 1000; | |
3950 | u32 iclk_pi_range = 64; | |
3951 | u32 desired_divisor, msb_divisor_value, pi_value; | |
3952 | ||
12d7ceed | 3953 | desired_divisor = (iclk_virtual_root_freq / clock); |
e615efe4 ED |
3954 | msb_divisor_value = desired_divisor / iclk_pi_range; |
3955 | pi_value = desired_divisor % iclk_pi_range; | |
3956 | ||
3957 | auxdiv = 0; | |
3958 | divsel = msb_divisor_value - 2; | |
3959 | phaseinc = pi_value; | |
3960 | } | |
3961 | ||
3962 | /* This should not happen with any sane values */ | |
3963 | WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) & | |
3964 | ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); | |
3965 | WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) & | |
3966 | ~SBI_SSCDIVINTPHASE_INCVAL_MASK); | |
3967 | ||
3968 | DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", | |
12d7ceed | 3969 | clock, |
e615efe4 ED |
3970 | auxdiv, |
3971 | divsel, | |
3972 | phasedir, | |
3973 | phaseinc); | |
3974 | ||
3975 | /* Program SSCDIVINTPHASE6 */ | |
988d6ee8 | 3976 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); |
e615efe4 ED |
3977 | temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK; |
3978 | temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); | |
3979 | temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK; | |
3980 | temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc); | |
3981 | temp |= SBI_SSCDIVINTPHASE_DIR(phasedir); | |
3982 | temp |= SBI_SSCDIVINTPHASE_PROPAGATE; | |
988d6ee8 | 3983 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK); |
e615efe4 ED |
3984 | |
3985 | /* Program SSCAUXDIV */ | |
988d6ee8 | 3986 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); |
e615efe4 ED |
3987 | temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1); |
3988 | temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv); | |
988d6ee8 | 3989 | intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK); |
e615efe4 ED |
3990 | |
3991 | /* Enable modulator and associated divider */ | |
988d6ee8 | 3992 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); |
e615efe4 | 3993 | temp &= ~SBI_SSCCTL_DISABLE; |
988d6ee8 | 3994 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); |
e615efe4 ED |
3995 | |
3996 | /* Wait for initialization time */ | |
3997 | udelay(24); | |
3998 | ||
3999 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE); | |
09153000 | 4000 | |
a580516d | 4001 | mutex_unlock(&dev_priv->sb_lock); |
e615efe4 ED |
4002 | } |
4003 | ||
275f01b2 DV |
4004 | static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc, |
4005 | enum pipe pch_transcoder) | |
4006 | { | |
4007 | struct drm_device *dev = crtc->base.dev; | |
4008 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6e3c9717 | 4009 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
275f01b2 DV |
4010 | |
4011 | I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder), | |
4012 | I915_READ(HTOTAL(cpu_transcoder))); | |
4013 | I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder), | |
4014 | I915_READ(HBLANK(cpu_transcoder))); | |
4015 | I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder), | |
4016 | I915_READ(HSYNC(cpu_transcoder))); | |
4017 | ||
4018 | I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder), | |
4019 | I915_READ(VTOTAL(cpu_transcoder))); | |
4020 | I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder), | |
4021 | I915_READ(VBLANK(cpu_transcoder))); | |
4022 | I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder), | |
4023 | I915_READ(VSYNC(cpu_transcoder))); | |
4024 | I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder), | |
4025 | I915_READ(VSYNCSHIFT(cpu_transcoder))); | |
4026 | } | |
4027 | ||
003632d9 | 4028 | static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable) |
1fbc0d78 DV |
4029 | { |
4030 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4031 | uint32_t temp; | |
4032 | ||
4033 | temp = I915_READ(SOUTH_CHICKEN1); | |
003632d9 | 4034 | if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable) |
1fbc0d78 DV |
4035 | return; |
4036 | ||
4037 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); | |
4038 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
4039 | ||
003632d9 ACO |
4040 | temp &= ~FDI_BC_BIFURCATION_SELECT; |
4041 | if (enable) | |
4042 | temp |= FDI_BC_BIFURCATION_SELECT; | |
4043 | ||
4044 | DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis"); | |
1fbc0d78 DV |
4045 | I915_WRITE(SOUTH_CHICKEN1, temp); |
4046 | POSTING_READ(SOUTH_CHICKEN1); | |
4047 | } | |
4048 | ||
4049 | static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc) | |
4050 | { | |
4051 | struct drm_device *dev = intel_crtc->base.dev; | |
1fbc0d78 DV |
4052 | |
4053 | switch (intel_crtc->pipe) { | |
4054 | case PIPE_A: | |
4055 | break; | |
4056 | case PIPE_B: | |
6e3c9717 | 4057 | if (intel_crtc->config->fdi_lanes > 2) |
003632d9 | 4058 | cpt_set_fdi_bc_bifurcation(dev, false); |
1fbc0d78 | 4059 | else |
003632d9 | 4060 | cpt_set_fdi_bc_bifurcation(dev, true); |
1fbc0d78 DV |
4061 | |
4062 | break; | |
4063 | case PIPE_C: | |
003632d9 | 4064 | cpt_set_fdi_bc_bifurcation(dev, true); |
1fbc0d78 DV |
4065 | |
4066 | break; | |
4067 | default: | |
4068 | BUG(); | |
4069 | } | |
4070 | } | |
4071 | ||
f67a559d JB |
4072 | /* |
4073 | * Enable PCH resources required for PCH ports: | |
4074 | * - PCH PLLs | |
4075 | * - FDI training & RX/TX | |
4076 | * - update transcoder timings | |
4077 | * - DP transcoding bits | |
4078 | * - transcoder | |
4079 | */ | |
4080 | static void ironlake_pch_enable(struct drm_crtc *crtc) | |
0e23b99d JB |
4081 | { |
4082 | struct drm_device *dev = crtc->dev; | |
4083 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4084 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4085 | int pipe = intel_crtc->pipe; | |
ee7b9f93 | 4086 | u32 reg, temp; |
2c07245f | 4087 | |
ab9412ba | 4088 | assert_pch_transcoder_disabled(dev_priv, pipe); |
e7e164db | 4089 | |
1fbc0d78 DV |
4090 | if (IS_IVYBRIDGE(dev)) |
4091 | ivybridge_update_fdi_bc_bifurcation(intel_crtc); | |
4092 | ||
cd986abb DV |
4093 | /* Write the TU size bits before fdi link training, so that error |
4094 | * detection works. */ | |
4095 | I915_WRITE(FDI_RX_TUSIZE1(pipe), | |
4096 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); | |
4097 | ||
c98e9dcf | 4098 | /* For PCH output, training FDI link */ |
674cf967 | 4099 | dev_priv->display.fdi_link_train(crtc); |
2c07245f | 4100 | |
3ad8a208 DV |
4101 | /* We need to program the right clock selection before writing the pixel |
4102 | * mutliplier into the DPLL. */ | |
303b81e0 | 4103 | if (HAS_PCH_CPT(dev)) { |
ee7b9f93 | 4104 | u32 sel; |
4b645f14 | 4105 | |
c98e9dcf | 4106 | temp = I915_READ(PCH_DPLL_SEL); |
11887397 DV |
4107 | temp |= TRANS_DPLL_ENABLE(pipe); |
4108 | sel = TRANS_DPLLB_SEL(pipe); | |
6e3c9717 | 4109 | if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B) |
ee7b9f93 JB |
4110 | temp |= sel; |
4111 | else | |
4112 | temp &= ~sel; | |
c98e9dcf | 4113 | I915_WRITE(PCH_DPLL_SEL, temp); |
c98e9dcf | 4114 | } |
5eddb70b | 4115 | |
3ad8a208 DV |
4116 | /* XXX: pch pll's can be enabled any time before we enable the PCH |
4117 | * transcoder, and we actually should do this to not upset any PCH | |
4118 | * transcoder that already use the clock when we share it. | |
4119 | * | |
4120 | * Note that enable_shared_dpll tries to do the right thing, but | |
4121 | * get_shared_dpll unconditionally resets the pll - we need that to have | |
4122 | * the right LVDS enable sequence. */ | |
85b3894f | 4123 | intel_enable_shared_dpll(intel_crtc); |
3ad8a208 | 4124 | |
d9b6cb56 JB |
4125 | /* set transcoder timing, panel must allow it */ |
4126 | assert_panel_unlocked(dev_priv, pipe); | |
275f01b2 | 4127 | ironlake_pch_transcoder_set_timings(intel_crtc, pipe); |
8db9d77b | 4128 | |
303b81e0 | 4129 | intel_fdi_normal_train(crtc); |
5e84e1a4 | 4130 | |
c98e9dcf | 4131 | /* For PCH DP, enable TRANS_DP_CTL */ |
6e3c9717 | 4132 | if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) { |
dfd07d72 | 4133 | u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; |
5eddb70b CW |
4134 | reg = TRANS_DP_CTL(pipe); |
4135 | temp = I915_READ(reg); | |
4136 | temp &= ~(TRANS_DP_PORT_SEL_MASK | | |
220cad3c EA |
4137 | TRANS_DP_SYNC_MASK | |
4138 | TRANS_DP_BPC_MASK); | |
e3ef4479 | 4139 | temp |= TRANS_DP_OUTPUT_ENABLE; |
9325c9f0 | 4140 | temp |= bpc << 9; /* same format but at 11:9 */ |
c98e9dcf JB |
4141 | |
4142 | if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC) | |
5eddb70b | 4143 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
c98e9dcf | 4144 | if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC) |
5eddb70b | 4145 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
c98e9dcf JB |
4146 | |
4147 | switch (intel_trans_dp_port_sel(crtc)) { | |
4148 | case PCH_DP_B: | |
5eddb70b | 4149 | temp |= TRANS_DP_PORT_SEL_B; |
c98e9dcf JB |
4150 | break; |
4151 | case PCH_DP_C: | |
5eddb70b | 4152 | temp |= TRANS_DP_PORT_SEL_C; |
c98e9dcf JB |
4153 | break; |
4154 | case PCH_DP_D: | |
5eddb70b | 4155 | temp |= TRANS_DP_PORT_SEL_D; |
c98e9dcf JB |
4156 | break; |
4157 | default: | |
e95d41e1 | 4158 | BUG(); |
32f9d658 | 4159 | } |
2c07245f | 4160 | |
5eddb70b | 4161 | I915_WRITE(reg, temp); |
6be4a607 | 4162 | } |
b52eb4dc | 4163 | |
b8a4f404 | 4164 | ironlake_enable_pch_transcoder(dev_priv, pipe); |
f67a559d JB |
4165 | } |
4166 | ||
1507e5bd PZ |
4167 | static void lpt_pch_enable(struct drm_crtc *crtc) |
4168 | { | |
4169 | struct drm_device *dev = crtc->dev; | |
4170 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4171 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6e3c9717 | 4172 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
1507e5bd | 4173 | |
ab9412ba | 4174 | assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A); |
1507e5bd | 4175 | |
8c52b5e8 | 4176 | lpt_program_iclkip(crtc); |
1507e5bd | 4177 | |
0540e488 | 4178 | /* Set transcoder timing. */ |
275f01b2 | 4179 | ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A); |
1507e5bd | 4180 | |
937bb610 | 4181 | lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); |
f67a559d JB |
4182 | } |
4183 | ||
190f68c5 ACO |
4184 | struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc, |
4185 | struct intel_crtc_state *crtc_state) | |
ee7b9f93 | 4186 | { |
e2b78267 | 4187 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
8bd31e67 | 4188 | struct intel_shared_dpll *pll; |
de419ab6 | 4189 | struct intel_shared_dpll_config *shared_dpll; |
e2b78267 | 4190 | enum intel_dpll_id i; |
ee7b9f93 | 4191 | |
de419ab6 ML |
4192 | shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state); |
4193 | ||
98b6bd99 DV |
4194 | if (HAS_PCH_IBX(dev_priv->dev)) { |
4195 | /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */ | |
d94ab068 | 4196 | i = (enum intel_dpll_id) crtc->pipe; |
e72f9fbf | 4197 | pll = &dev_priv->shared_dplls[i]; |
98b6bd99 | 4198 | |
46edb027 DV |
4199 | DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n", |
4200 | crtc->base.base.id, pll->name); | |
98b6bd99 | 4201 | |
de419ab6 | 4202 | WARN_ON(shared_dpll[i].crtc_mask); |
f2a69f44 | 4203 | |
98b6bd99 DV |
4204 | goto found; |
4205 | } | |
4206 | ||
bcddf610 S |
4207 | if (IS_BROXTON(dev_priv->dev)) { |
4208 | /* PLL is attached to port in bxt */ | |
4209 | struct intel_encoder *encoder; | |
4210 | struct intel_digital_port *intel_dig_port; | |
4211 | ||
4212 | encoder = intel_ddi_get_crtc_new_encoder(crtc_state); | |
4213 | if (WARN_ON(!encoder)) | |
4214 | return NULL; | |
4215 | ||
4216 | intel_dig_port = enc_to_dig_port(&encoder->base); | |
4217 | /* 1:1 mapping between ports and PLLs */ | |
4218 | i = (enum intel_dpll_id)intel_dig_port->port; | |
4219 | pll = &dev_priv->shared_dplls[i]; | |
4220 | DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n", | |
4221 | crtc->base.base.id, pll->name); | |
de419ab6 | 4222 | WARN_ON(shared_dpll[i].crtc_mask); |
bcddf610 S |
4223 | |
4224 | goto found; | |
4225 | } | |
4226 | ||
e72f9fbf DV |
4227 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
4228 | pll = &dev_priv->shared_dplls[i]; | |
ee7b9f93 JB |
4229 | |
4230 | /* Only want to check enabled timings first */ | |
de419ab6 | 4231 | if (shared_dpll[i].crtc_mask == 0) |
ee7b9f93 JB |
4232 | continue; |
4233 | ||
190f68c5 | 4234 | if (memcmp(&crtc_state->dpll_hw_state, |
de419ab6 ML |
4235 | &shared_dpll[i].hw_state, |
4236 | sizeof(crtc_state->dpll_hw_state)) == 0) { | |
8bd31e67 | 4237 | DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n", |
1e6f2ddc | 4238 | crtc->base.base.id, pll->name, |
de419ab6 | 4239 | shared_dpll[i].crtc_mask, |
8bd31e67 | 4240 | pll->active); |
ee7b9f93 JB |
4241 | goto found; |
4242 | } | |
4243 | } | |
4244 | ||
4245 | /* Ok no matching timings, maybe there's a free one? */ | |
e72f9fbf DV |
4246 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
4247 | pll = &dev_priv->shared_dplls[i]; | |
de419ab6 | 4248 | if (shared_dpll[i].crtc_mask == 0) { |
46edb027 DV |
4249 | DRM_DEBUG_KMS("CRTC:%d allocated %s\n", |
4250 | crtc->base.base.id, pll->name); | |
ee7b9f93 JB |
4251 | goto found; |
4252 | } | |
4253 | } | |
4254 | ||
4255 | return NULL; | |
4256 | ||
4257 | found: | |
de419ab6 ML |
4258 | if (shared_dpll[i].crtc_mask == 0) |
4259 | shared_dpll[i].hw_state = | |
4260 | crtc_state->dpll_hw_state; | |
f2a69f44 | 4261 | |
190f68c5 | 4262 | crtc_state->shared_dpll = i; |
46edb027 DV |
4263 | DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name, |
4264 | pipe_name(crtc->pipe)); | |
ee7b9f93 | 4265 | |
de419ab6 | 4266 | shared_dpll[i].crtc_mask |= 1 << crtc->pipe; |
e04c7350 | 4267 | |
ee7b9f93 JB |
4268 | return pll; |
4269 | } | |
4270 | ||
de419ab6 | 4271 | static void intel_shared_dpll_commit(struct drm_atomic_state *state) |
8bd31e67 | 4272 | { |
de419ab6 ML |
4273 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
4274 | struct intel_shared_dpll_config *shared_dpll; | |
8bd31e67 ACO |
4275 | struct intel_shared_dpll *pll; |
4276 | enum intel_dpll_id i; | |
4277 | ||
de419ab6 ML |
4278 | if (!to_intel_atomic_state(state)->dpll_set) |
4279 | return; | |
8bd31e67 | 4280 | |
de419ab6 | 4281 | shared_dpll = to_intel_atomic_state(state)->shared_dpll; |
8bd31e67 ACO |
4282 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
4283 | pll = &dev_priv->shared_dplls[i]; | |
de419ab6 | 4284 | pll->config = shared_dpll[i]; |
8bd31e67 ACO |
4285 | } |
4286 | } | |
4287 | ||
a1520318 | 4288 | static void cpt_verify_modeset(struct drm_device *dev, int pipe) |
d4270e57 JB |
4289 | { |
4290 | struct drm_i915_private *dev_priv = dev->dev_private; | |
23670b32 | 4291 | int dslreg = PIPEDSL(pipe); |
d4270e57 JB |
4292 | u32 temp; |
4293 | ||
4294 | temp = I915_READ(dslreg); | |
4295 | udelay(500); | |
4296 | if (wait_for(I915_READ(dslreg) != temp, 5)) { | |
d4270e57 | 4297 | if (wait_for(I915_READ(dslreg) != temp, 5)) |
84f44ce7 | 4298 | DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe)); |
d4270e57 JB |
4299 | } |
4300 | } | |
4301 | ||
a1b2278e CK |
4302 | /** |
4303 | * skl_update_scaler_users - Stages update to crtc's scaler state | |
4304 | * @intel_crtc: crtc | |
4305 | * @crtc_state: crtc_state | |
4306 | * @plane: plane (NULL indicates crtc is requesting update) | |
4307 | * @plane_state: plane's state | |
4308 | * @force_detach: request unconditional detachment of scaler | |
4309 | * | |
4310 | * This function updates scaler state for requested plane or crtc. | |
4311 | * To request scaler usage update for a plane, caller shall pass plane pointer. | |
4312 | * To request scaler usage update for crtc, caller shall pass plane pointer | |
4313 | * as NULL. | |
4314 | * | |
4315 | * Return | |
4316 | * 0 - scaler_usage updated successfully | |
4317 | * error - requested scaling cannot be supported or other error condition | |
4318 | */ | |
4319 | int | |
4320 | skl_update_scaler_users( | |
4321 | struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state, | |
4322 | struct intel_plane *intel_plane, struct intel_plane_state *plane_state, | |
4323 | int force_detach) | |
4324 | { | |
4325 | int need_scaling; | |
4326 | int idx; | |
4327 | int src_w, src_h, dst_w, dst_h; | |
4328 | int *scaler_id; | |
4329 | struct drm_framebuffer *fb; | |
4330 | struct intel_crtc_scaler_state *scaler_state; | |
6156a456 | 4331 | unsigned int rotation; |
a1b2278e CK |
4332 | |
4333 | if (!intel_crtc || !crtc_state) | |
4334 | return 0; | |
4335 | ||
4336 | scaler_state = &crtc_state->scaler_state; | |
4337 | ||
4338 | idx = intel_plane ? drm_plane_index(&intel_plane->base) : SKL_CRTC_INDEX; | |
4339 | fb = intel_plane ? plane_state->base.fb : NULL; | |
4340 | ||
4341 | if (intel_plane) { | |
4342 | src_w = drm_rect_width(&plane_state->src) >> 16; | |
4343 | src_h = drm_rect_height(&plane_state->src) >> 16; | |
4344 | dst_w = drm_rect_width(&plane_state->dst); | |
4345 | dst_h = drm_rect_height(&plane_state->dst); | |
4346 | scaler_id = &plane_state->scaler_id; | |
6156a456 | 4347 | rotation = plane_state->base.rotation; |
a1b2278e CK |
4348 | } else { |
4349 | struct drm_display_mode *adjusted_mode = | |
4350 | &crtc_state->base.adjusted_mode; | |
4351 | src_w = crtc_state->pipe_src_w; | |
4352 | src_h = crtc_state->pipe_src_h; | |
4353 | dst_w = adjusted_mode->hdisplay; | |
4354 | dst_h = adjusted_mode->vdisplay; | |
4355 | scaler_id = &scaler_state->scaler_id; | |
6156a456 | 4356 | rotation = DRM_ROTATE_0; |
a1b2278e | 4357 | } |
6156a456 CK |
4358 | |
4359 | need_scaling = intel_rotation_90_or_270(rotation) ? | |
4360 | (src_h != dst_w || src_w != dst_h): | |
4361 | (src_w != dst_w || src_h != dst_h); | |
a1b2278e CK |
4362 | |
4363 | /* | |
4364 | * if plane is being disabled or scaler is no more required or force detach | |
4365 | * - free scaler binded to this plane/crtc | |
4366 | * - in order to do this, update crtc->scaler_usage | |
4367 | * | |
4368 | * Here scaler state in crtc_state is set free so that | |
4369 | * scaler can be assigned to other user. Actual register | |
4370 | * update to free the scaler is done in plane/panel-fit programming. | |
4371 | * For this purpose crtc/plane_state->scaler_id isn't reset here. | |
4372 | */ | |
4373 | if (force_detach || !need_scaling || (intel_plane && | |
4374 | (!fb || !plane_state->visible))) { | |
4375 | if (*scaler_id >= 0) { | |
4376 | scaler_state->scaler_users &= ~(1 << idx); | |
4377 | scaler_state->scalers[*scaler_id].in_use = 0; | |
4378 | ||
4379 | DRM_DEBUG_KMS("Staged freeing scaler id %d.%d from %s:%d " | |
4380 | "crtc_state = %p scaler_users = 0x%x\n", | |
4381 | intel_crtc->pipe, *scaler_id, intel_plane ? "PLANE" : "CRTC", | |
4382 | intel_plane ? intel_plane->base.base.id : | |
4383 | intel_crtc->base.base.id, crtc_state, | |
4384 | scaler_state->scaler_users); | |
4385 | *scaler_id = -1; | |
4386 | } | |
4387 | return 0; | |
4388 | } | |
4389 | ||
4390 | /* range checks */ | |
4391 | if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H || | |
4392 | dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H || | |
4393 | ||
4394 | src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H || | |
4395 | dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) { | |
4396 | DRM_DEBUG_KMS("%s:%d scaler_user index %u.%u: src %ux%u dst %ux%u " | |
4397 | "size is out of scaler range\n", | |
4398 | intel_plane ? "PLANE" : "CRTC", | |
4399 | intel_plane ? intel_plane->base.base.id : intel_crtc->base.base.id, | |
4400 | intel_crtc->pipe, idx, src_w, src_h, dst_w, dst_h); | |
4401 | return -EINVAL; | |
4402 | } | |
4403 | ||
4404 | /* check colorkey */ | |
225c228a CK |
4405 | if (WARN_ON(intel_plane && |
4406 | intel_plane->ckey.flags != I915_SET_COLORKEY_NONE)) { | |
4407 | DRM_DEBUG_KMS("PLANE:%d scaling %ux%u->%ux%u not allowed with colorkey", | |
4408 | intel_plane->base.base.id, src_w, src_h, dst_w, dst_h); | |
a1b2278e CK |
4409 | return -EINVAL; |
4410 | } | |
4411 | ||
4412 | /* Check src format */ | |
4413 | if (intel_plane) { | |
4414 | switch (fb->pixel_format) { | |
4415 | case DRM_FORMAT_RGB565: | |
4416 | case DRM_FORMAT_XBGR8888: | |
4417 | case DRM_FORMAT_XRGB8888: | |
4418 | case DRM_FORMAT_ABGR8888: | |
4419 | case DRM_FORMAT_ARGB8888: | |
4420 | case DRM_FORMAT_XRGB2101010: | |
a1b2278e | 4421 | case DRM_FORMAT_XBGR2101010: |
a1b2278e CK |
4422 | case DRM_FORMAT_YUYV: |
4423 | case DRM_FORMAT_YVYU: | |
4424 | case DRM_FORMAT_UYVY: | |
4425 | case DRM_FORMAT_VYUY: | |
4426 | break; | |
4427 | default: | |
4428 | DRM_DEBUG_KMS("PLANE:%d FB:%d unsupported scaling format 0x%x\n", | |
4429 | intel_plane->base.base.id, fb->base.id, fb->pixel_format); | |
4430 | return -EINVAL; | |
4431 | } | |
4432 | } | |
4433 | ||
4434 | /* mark this plane as a scaler user in crtc_state */ | |
4435 | scaler_state->scaler_users |= (1 << idx); | |
4436 | DRM_DEBUG_KMS("%s:%d staged scaling request for %ux%u->%ux%u " | |
4437 | "crtc_state = %p scaler_users = 0x%x\n", | |
4438 | intel_plane ? "PLANE" : "CRTC", | |
4439 | intel_plane ? intel_plane->base.base.id : intel_crtc->base.base.id, | |
4440 | src_w, src_h, dst_w, dst_h, crtc_state, scaler_state->scaler_users); | |
4441 | return 0; | |
4442 | } | |
4443 | ||
4444 | static void skylake_pfit_update(struct intel_crtc *crtc, int enable) | |
bd2e244f JB |
4445 | { |
4446 | struct drm_device *dev = crtc->base.dev; | |
4447 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4448 | int pipe = crtc->pipe; | |
a1b2278e CK |
4449 | struct intel_crtc_scaler_state *scaler_state = |
4450 | &crtc->config->scaler_state; | |
4451 | ||
4452 | DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config); | |
4453 | ||
4454 | /* To update pfit, first update scaler state */ | |
4455 | skl_update_scaler_users(crtc, crtc->config, NULL, NULL, !enable); | |
4456 | intel_atomic_setup_scalers(crtc->base.dev, crtc, crtc->config); | |
4457 | skl_detach_scalers(crtc); | |
4458 | if (!enable) | |
4459 | return; | |
bd2e244f | 4460 | |
6e3c9717 | 4461 | if (crtc->config->pch_pfit.enabled) { |
a1b2278e CK |
4462 | int id; |
4463 | ||
4464 | if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) { | |
4465 | DRM_ERROR("Requesting pfit without getting a scaler first\n"); | |
4466 | return; | |
4467 | } | |
4468 | ||
4469 | id = scaler_state->scaler_id; | |
4470 | I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN | | |
4471 | PS_FILTER_MEDIUM | scaler_state->scalers[id].mode); | |
4472 | I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos); | |
4473 | I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size); | |
4474 | ||
4475 | DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id); | |
bd2e244f JB |
4476 | } |
4477 | } | |
4478 | ||
b074cec8 JB |
4479 | static void ironlake_pfit_enable(struct intel_crtc *crtc) |
4480 | { | |
4481 | struct drm_device *dev = crtc->base.dev; | |
4482 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4483 | int pipe = crtc->pipe; | |
4484 | ||
6e3c9717 | 4485 | if (crtc->config->pch_pfit.enabled) { |
b074cec8 JB |
4486 | /* Force use of hard-coded filter coefficients |
4487 | * as some pre-programmed values are broken, | |
4488 | * e.g. x201. | |
4489 | */ | |
4490 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) | |
4491 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | | |
4492 | PF_PIPE_SEL_IVB(pipe)); | |
4493 | else | |
4494 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); | |
6e3c9717 ACO |
4495 | I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos); |
4496 | I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size); | |
d4270e57 JB |
4497 | } |
4498 | } | |
4499 | ||
4a3b8769 | 4500 | static void intel_enable_sprite_planes(struct drm_crtc *crtc) |
bb53d4ae VS |
4501 | { |
4502 | struct drm_device *dev = crtc->dev; | |
4503 | enum pipe pipe = to_intel_crtc(crtc)->pipe; | |
af2b653b | 4504 | struct drm_plane *plane; |
bb53d4ae VS |
4505 | struct intel_plane *intel_plane; |
4506 | ||
af2b653b MR |
4507 | drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) { |
4508 | intel_plane = to_intel_plane(plane); | |
bb53d4ae VS |
4509 | if (intel_plane->pipe == pipe) |
4510 | intel_plane_restore(&intel_plane->base); | |
af2b653b | 4511 | } |
bb53d4ae VS |
4512 | } |
4513 | ||
20bc8673 | 4514 | void hsw_enable_ips(struct intel_crtc *crtc) |
d77e4531 | 4515 | { |
cea165c3 VS |
4516 | struct drm_device *dev = crtc->base.dev; |
4517 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d77e4531 | 4518 | |
6e3c9717 | 4519 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4520 | return; |
4521 | ||
cea165c3 VS |
4522 | /* We can only enable IPS after we enable a plane and wait for a vblank */ |
4523 | intel_wait_for_vblank(dev, crtc->pipe); | |
4524 | ||
d77e4531 | 4525 | assert_plane_enabled(dev_priv, crtc->plane); |
cea165c3 | 4526 | if (IS_BROADWELL(dev)) { |
2a114cc1 BW |
4527 | mutex_lock(&dev_priv->rps.hw_lock); |
4528 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000)); | |
4529 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4530 | /* Quoting Art Runyan: "its not safe to expect any particular | |
4531 | * value in IPS_CTL bit 31 after enabling IPS through the | |
e59150dc JB |
4532 | * mailbox." Moreover, the mailbox may return a bogus state, |
4533 | * so we need to just enable it and continue on. | |
2a114cc1 BW |
4534 | */ |
4535 | } else { | |
4536 | I915_WRITE(IPS_CTL, IPS_ENABLE); | |
4537 | /* The bit only becomes 1 in the next vblank, so this wait here | |
4538 | * is essentially intel_wait_for_vblank. If we don't have this | |
4539 | * and don't wait for vblanks until the end of crtc_enable, then | |
4540 | * the HW state readout code will complain that the expected | |
4541 | * IPS_CTL value is not the one we read. */ | |
4542 | if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50)) | |
4543 | DRM_ERROR("Timed out waiting for IPS enable\n"); | |
4544 | } | |
d77e4531 PZ |
4545 | } |
4546 | ||
20bc8673 | 4547 | void hsw_disable_ips(struct intel_crtc *crtc) |
d77e4531 PZ |
4548 | { |
4549 | struct drm_device *dev = crtc->base.dev; | |
4550 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4551 | ||
6e3c9717 | 4552 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4553 | return; |
4554 | ||
4555 | assert_plane_enabled(dev_priv, crtc->plane); | |
23d0b130 | 4556 | if (IS_BROADWELL(dev)) { |
2a114cc1 BW |
4557 | mutex_lock(&dev_priv->rps.hw_lock); |
4558 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0)); | |
4559 | mutex_unlock(&dev_priv->rps.hw_lock); | |
23d0b130 BW |
4560 | /* wait for pcode to finish disabling IPS, which may take up to 42ms */ |
4561 | if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42)) | |
4562 | DRM_ERROR("Timed out waiting for IPS disable\n"); | |
e59150dc | 4563 | } else { |
2a114cc1 | 4564 | I915_WRITE(IPS_CTL, 0); |
e59150dc JB |
4565 | POSTING_READ(IPS_CTL); |
4566 | } | |
d77e4531 PZ |
4567 | |
4568 | /* We need to wait for a vblank before we can disable the plane. */ | |
4569 | intel_wait_for_vblank(dev, crtc->pipe); | |
4570 | } | |
4571 | ||
4572 | /** Loads the palette/gamma unit for the CRTC with the prepared values */ | |
4573 | static void intel_crtc_load_lut(struct drm_crtc *crtc) | |
4574 | { | |
4575 | struct drm_device *dev = crtc->dev; | |
4576 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4577 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4578 | enum pipe pipe = intel_crtc->pipe; | |
4579 | int palreg = PALETTE(pipe); | |
4580 | int i; | |
4581 | bool reenable_ips = false; | |
4582 | ||
4583 | /* The clocks have to be on to load the palette. */ | |
53d9f4e9 | 4584 | if (!crtc->state->active) |
d77e4531 PZ |
4585 | return; |
4586 | ||
50360403 | 4587 | if (HAS_GMCH_DISPLAY(dev_priv->dev)) { |
409ee761 | 4588 | if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) |
d77e4531 PZ |
4589 | assert_dsi_pll_enabled(dev_priv); |
4590 | else | |
4591 | assert_pll_enabled(dev_priv, pipe); | |
4592 | } | |
4593 | ||
4594 | /* use legacy palette for Ironlake */ | |
7a1db49a | 4595 | if (!HAS_GMCH_DISPLAY(dev)) |
d77e4531 PZ |
4596 | palreg = LGC_PALETTE(pipe); |
4597 | ||
4598 | /* Workaround : Do not read or write the pipe palette/gamma data while | |
4599 | * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled. | |
4600 | */ | |
6e3c9717 | 4601 | if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled && |
d77e4531 PZ |
4602 | ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) == |
4603 | GAMMA_MODE_MODE_SPLIT)) { | |
4604 | hsw_disable_ips(intel_crtc); | |
4605 | reenable_ips = true; | |
4606 | } | |
4607 | ||
4608 | for (i = 0; i < 256; i++) { | |
4609 | I915_WRITE(palreg + 4 * i, | |
4610 | (intel_crtc->lut_r[i] << 16) | | |
4611 | (intel_crtc->lut_g[i] << 8) | | |
4612 | intel_crtc->lut_b[i]); | |
4613 | } | |
4614 | ||
4615 | if (reenable_ips) | |
4616 | hsw_enable_ips(intel_crtc); | |
4617 | } | |
4618 | ||
7cac945f | 4619 | static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc) |
d3eedb1a | 4620 | { |
7cac945f | 4621 | if (intel_crtc->overlay) { |
d3eedb1a VS |
4622 | struct drm_device *dev = intel_crtc->base.dev; |
4623 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4624 | ||
4625 | mutex_lock(&dev->struct_mutex); | |
4626 | dev_priv->mm.interruptible = false; | |
4627 | (void) intel_overlay_switch_off(intel_crtc->overlay); | |
4628 | dev_priv->mm.interruptible = true; | |
4629 | mutex_unlock(&dev->struct_mutex); | |
4630 | } | |
4631 | ||
4632 | /* Let userspace switch the overlay on again. In most cases userspace | |
4633 | * has to recompute where to put it anyway. | |
4634 | */ | |
4635 | } | |
4636 | ||
87d4300a ML |
4637 | /** |
4638 | * intel_post_enable_primary - Perform operations after enabling primary plane | |
4639 | * @crtc: the CRTC whose primary plane was just enabled | |
4640 | * | |
4641 | * Performs potentially sleeping operations that must be done after the primary | |
4642 | * plane is enabled, such as updating FBC and IPS. Note that this may be | |
4643 | * called due to an explicit primary plane update, or due to an implicit | |
4644 | * re-enable that is caused when a sprite plane is updated to no longer | |
4645 | * completely hide the primary plane. | |
4646 | */ | |
4647 | static void | |
4648 | intel_post_enable_primary(struct drm_crtc *crtc) | |
a5c4d7bc VS |
4649 | { |
4650 | struct drm_device *dev = crtc->dev; | |
87d4300a | 4651 | struct drm_i915_private *dev_priv = dev->dev_private; |
a5c4d7bc VS |
4652 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4653 | int pipe = intel_crtc->pipe; | |
a5c4d7bc | 4654 | |
87d4300a ML |
4655 | /* |
4656 | * BDW signals flip done immediately if the plane | |
4657 | * is disabled, even if the plane enable is already | |
4658 | * armed to occur at the next vblank :( | |
4659 | */ | |
4660 | if (IS_BROADWELL(dev)) | |
4661 | intel_wait_for_vblank(dev, pipe); | |
a5c4d7bc | 4662 | |
87d4300a ML |
4663 | /* |
4664 | * FIXME IPS should be fine as long as one plane is | |
4665 | * enabled, but in practice it seems to have problems | |
4666 | * when going from primary only to sprite only and vice | |
4667 | * versa. | |
4668 | */ | |
a5c4d7bc VS |
4669 | hsw_enable_ips(intel_crtc); |
4670 | ||
4671 | mutex_lock(&dev->struct_mutex); | |
7ff0ebcc | 4672 | intel_fbc_update(dev); |
a5c4d7bc | 4673 | mutex_unlock(&dev->struct_mutex); |
f99d7069 DV |
4674 | |
4675 | /* | |
87d4300a ML |
4676 | * Gen2 reports pipe underruns whenever all planes are disabled. |
4677 | * So don't enable underrun reporting before at least some planes | |
4678 | * are enabled. | |
4679 | * FIXME: Need to fix the logic to work when we turn off all planes | |
4680 | * but leave the pipe running. | |
f99d7069 | 4681 | */ |
87d4300a ML |
4682 | if (IS_GEN2(dev)) |
4683 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
4684 | ||
4685 | /* Underruns don't raise interrupts, so check manually. */ | |
4686 | if (HAS_GMCH_DISPLAY(dev)) | |
4687 | i9xx_check_fifo_underruns(dev_priv); | |
a5c4d7bc VS |
4688 | } |
4689 | ||
87d4300a ML |
4690 | /** |
4691 | * intel_pre_disable_primary - Perform operations before disabling primary plane | |
4692 | * @crtc: the CRTC whose primary plane is to be disabled | |
4693 | * | |
4694 | * Performs potentially sleeping operations that must be done before the | |
4695 | * primary plane is disabled, such as updating FBC and IPS. Note that this may | |
4696 | * be called due to an explicit primary plane update, or due to an implicit | |
4697 | * disable that is caused when a sprite plane completely hides the primary | |
4698 | * plane. | |
4699 | */ | |
4700 | static void | |
4701 | intel_pre_disable_primary(struct drm_crtc *crtc) | |
a5c4d7bc VS |
4702 | { |
4703 | struct drm_device *dev = crtc->dev; | |
4704 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4705 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4706 | int pipe = intel_crtc->pipe; | |
a5c4d7bc | 4707 | |
87d4300a ML |
4708 | /* |
4709 | * Gen2 reports pipe underruns whenever all planes are disabled. | |
4710 | * So diasble underrun reporting before all the planes get disabled. | |
4711 | * FIXME: Need to fix the logic to work when we turn off all planes | |
4712 | * but leave the pipe running. | |
4713 | */ | |
4714 | if (IS_GEN2(dev)) | |
4715 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
a5c4d7bc | 4716 | |
87d4300a ML |
4717 | /* |
4718 | * Vblank time updates from the shadow to live plane control register | |
4719 | * are blocked if the memory self-refresh mode is active at that | |
4720 | * moment. So to make sure the plane gets truly disabled, disable | |
4721 | * first the self-refresh mode. The self-refresh enable bit in turn | |
4722 | * will be checked/applied by the HW only at the next frame start | |
4723 | * event which is after the vblank start event, so we need to have a | |
4724 | * wait-for-vblank between disabling the plane and the pipe. | |
4725 | */ | |
4726 | if (HAS_GMCH_DISPLAY(dev)) | |
4727 | intel_set_memory_cxsr(dev_priv, false); | |
4728 | ||
4729 | mutex_lock(&dev->struct_mutex); | |
e35fef21 | 4730 | if (dev_priv->fbc.crtc == intel_crtc) |
7ff0ebcc | 4731 | intel_fbc_disable(dev); |
87d4300a | 4732 | mutex_unlock(&dev->struct_mutex); |
a5c4d7bc | 4733 | |
87d4300a ML |
4734 | /* |
4735 | * FIXME IPS should be fine as long as one plane is | |
4736 | * enabled, but in practice it seems to have problems | |
4737 | * when going from primary only to sprite only and vice | |
4738 | * versa. | |
4739 | */ | |
a5c4d7bc | 4740 | hsw_disable_ips(intel_crtc); |
87d4300a ML |
4741 | } |
4742 | ||
4743 | static void intel_crtc_enable_planes(struct drm_crtc *crtc) | |
4744 | { | |
2d847d45 RV |
4745 | struct drm_device *dev = crtc->dev; |
4746 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4747 | int pipe = intel_crtc->pipe; | |
4748 | ||
87d4300a ML |
4749 | intel_enable_primary_hw_plane(crtc->primary, crtc); |
4750 | intel_enable_sprite_planes(crtc); | |
4751 | intel_crtc_update_cursor(crtc, true); | |
87d4300a ML |
4752 | |
4753 | intel_post_enable_primary(crtc); | |
2d847d45 RV |
4754 | |
4755 | /* | |
4756 | * FIXME: Once we grow proper nuclear flip support out of this we need | |
4757 | * to compute the mask of flip planes precisely. For the time being | |
4758 | * consider this a flip to a NULL plane. | |
4759 | */ | |
4760 | intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe)); | |
87d4300a ML |
4761 | } |
4762 | ||
4763 | static void intel_crtc_disable_planes(struct drm_crtc *crtc) | |
4764 | { | |
4765 | struct drm_device *dev = crtc->dev; | |
4766 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4767 | struct intel_plane *intel_plane; | |
4768 | int pipe = intel_crtc->pipe; | |
4769 | ||
4770 | intel_crtc_wait_for_pending_flips(crtc); | |
4771 | ||
4772 | intel_pre_disable_primary(crtc); | |
a5c4d7bc | 4773 | |
7cac945f | 4774 | intel_crtc_dpms_overlay_disable(intel_crtc); |
27321ae8 ML |
4775 | for_each_intel_plane(dev, intel_plane) { |
4776 | if (intel_plane->pipe == pipe) { | |
4777 | struct drm_crtc *from = intel_plane->base.crtc; | |
4778 | ||
4779 | intel_plane->disable_plane(&intel_plane->base, | |
4780 | from ?: crtc, true); | |
4781 | } | |
4782 | } | |
f98551ae | 4783 | |
f99d7069 DV |
4784 | /* |
4785 | * FIXME: Once we grow proper nuclear flip support out of this we need | |
4786 | * to compute the mask of flip planes precisely. For the time being | |
4787 | * consider this a flip to a NULL plane. | |
4788 | */ | |
4789 | intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe)); | |
a5c4d7bc VS |
4790 | } |
4791 | ||
f67a559d JB |
4792 | static void ironlake_crtc_enable(struct drm_crtc *crtc) |
4793 | { | |
4794 | struct drm_device *dev = crtc->dev; | |
4795 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4796 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 4797 | struct intel_encoder *encoder; |
f67a559d | 4798 | int pipe = intel_crtc->pipe; |
f67a559d | 4799 | |
53d9f4e9 | 4800 | if (WARN_ON(intel_crtc->active)) |
f67a559d JB |
4801 | return; |
4802 | ||
6e3c9717 | 4803 | if (intel_crtc->config->has_pch_encoder) |
b14b1055 DV |
4804 | intel_prepare_shared_dpll(intel_crtc); |
4805 | ||
6e3c9717 | 4806 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 4807 | intel_dp_set_m_n(intel_crtc, M1_N1); |
29407aab DV |
4808 | |
4809 | intel_set_pipe_timings(intel_crtc); | |
4810 | ||
6e3c9717 | 4811 | if (intel_crtc->config->has_pch_encoder) { |
29407aab | 4812 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 4813 | &intel_crtc->config->fdi_m_n, NULL); |
29407aab DV |
4814 | } |
4815 | ||
4816 | ironlake_set_pipeconf(crtc); | |
4817 | ||
f67a559d | 4818 | intel_crtc->active = true; |
8664281b | 4819 | |
a72e4c9f DV |
4820 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4821 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); | |
8664281b | 4822 | |
f6736a1a | 4823 | for_each_encoder_on_crtc(dev, crtc, encoder) |
952735ee DV |
4824 | if (encoder->pre_enable) |
4825 | encoder->pre_enable(encoder); | |
f67a559d | 4826 | |
6e3c9717 | 4827 | if (intel_crtc->config->has_pch_encoder) { |
fff367c7 DV |
4828 | /* Note: FDI PLL enabling _must_ be done before we enable the |
4829 | * cpu pipes, hence this is separate from all the other fdi/pch | |
4830 | * enabling. */ | |
88cefb6c | 4831 | ironlake_fdi_pll_enable(intel_crtc); |
46b6f814 DV |
4832 | } else { |
4833 | assert_fdi_tx_disabled(dev_priv, pipe); | |
4834 | assert_fdi_rx_disabled(dev_priv, pipe); | |
4835 | } | |
f67a559d | 4836 | |
b074cec8 | 4837 | ironlake_pfit_enable(intel_crtc); |
f67a559d | 4838 | |
9c54c0dd JB |
4839 | /* |
4840 | * On ILK+ LUT must be loaded before the pipe is running but with | |
4841 | * clocks enabled | |
4842 | */ | |
4843 | intel_crtc_load_lut(crtc); | |
4844 | ||
f37fcc2a | 4845 | intel_update_watermarks(crtc); |
e1fdc473 | 4846 | intel_enable_pipe(intel_crtc); |
f67a559d | 4847 | |
6e3c9717 | 4848 | if (intel_crtc->config->has_pch_encoder) |
f67a559d | 4849 | ironlake_pch_enable(crtc); |
c98e9dcf | 4850 | |
f9b61ff6 DV |
4851 | assert_vblank_disabled(crtc); |
4852 | drm_crtc_vblank_on(crtc); | |
4853 | ||
fa5c73b1 DV |
4854 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4855 | encoder->enable(encoder); | |
61b77ddd DV |
4856 | |
4857 | if (HAS_PCH_CPT(dev)) | |
a1520318 | 4858 | cpt_verify_modeset(dev, intel_crtc->pipe); |
6be4a607 JB |
4859 | } |
4860 | ||
42db64ef PZ |
4861 | /* IPS only exists on ULT machines and is tied to pipe A. */ |
4862 | static bool hsw_crtc_supports_ips(struct intel_crtc *crtc) | |
4863 | { | |
f5adf94e | 4864 | return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A; |
42db64ef PZ |
4865 | } |
4866 | ||
4f771f10 PZ |
4867 | static void haswell_crtc_enable(struct drm_crtc *crtc) |
4868 | { | |
4869 | struct drm_device *dev = crtc->dev; | |
4870 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4871 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4872 | struct intel_encoder *encoder; | |
99d736a2 ML |
4873 | int pipe = intel_crtc->pipe, hsw_workaround_pipe; |
4874 | struct intel_crtc_state *pipe_config = | |
4875 | to_intel_crtc_state(crtc->state); | |
4f771f10 | 4876 | |
53d9f4e9 | 4877 | if (WARN_ON(intel_crtc->active)) |
4f771f10 PZ |
4878 | return; |
4879 | ||
df8ad70c DV |
4880 | if (intel_crtc_to_shared_dpll(intel_crtc)) |
4881 | intel_enable_shared_dpll(intel_crtc); | |
4882 | ||
6e3c9717 | 4883 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 4884 | intel_dp_set_m_n(intel_crtc, M1_N1); |
229fca97 DV |
4885 | |
4886 | intel_set_pipe_timings(intel_crtc); | |
4887 | ||
6e3c9717 ACO |
4888 | if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) { |
4889 | I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder), | |
4890 | intel_crtc->config->pixel_multiplier - 1); | |
ebb69c95 CT |
4891 | } |
4892 | ||
6e3c9717 | 4893 | if (intel_crtc->config->has_pch_encoder) { |
229fca97 | 4894 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 4895 | &intel_crtc->config->fdi_m_n, NULL); |
229fca97 DV |
4896 | } |
4897 | ||
4898 | haswell_set_pipeconf(crtc); | |
4899 | ||
4900 | intel_set_pipe_csc(crtc); | |
4901 | ||
4f771f10 | 4902 | intel_crtc->active = true; |
8664281b | 4903 | |
a72e4c9f | 4904 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4f771f10 PZ |
4905 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4906 | if (encoder->pre_enable) | |
4907 | encoder->pre_enable(encoder); | |
4908 | ||
6e3c9717 | 4909 | if (intel_crtc->config->has_pch_encoder) { |
a72e4c9f DV |
4910 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
4911 | true); | |
4fe9467d ID |
4912 | dev_priv->display.fdi_link_train(crtc); |
4913 | } | |
4914 | ||
1f544388 | 4915 | intel_ddi_enable_pipe_clock(intel_crtc); |
4f771f10 | 4916 | |
ff6d9f55 | 4917 | if (INTEL_INFO(dev)->gen == 9) |
a1b2278e | 4918 | skylake_pfit_update(intel_crtc, 1); |
ff6d9f55 | 4919 | else if (INTEL_INFO(dev)->gen < 9) |
bd2e244f | 4920 | ironlake_pfit_enable(intel_crtc); |
ff6d9f55 JB |
4921 | else |
4922 | MISSING_CASE(INTEL_INFO(dev)->gen); | |
4f771f10 PZ |
4923 | |
4924 | /* | |
4925 | * On ILK+ LUT must be loaded before the pipe is running but with | |
4926 | * clocks enabled | |
4927 | */ | |
4928 | intel_crtc_load_lut(crtc); | |
4929 | ||
1f544388 | 4930 | intel_ddi_set_pipe_settings(crtc); |
8228c251 | 4931 | intel_ddi_enable_transcoder_func(crtc); |
4f771f10 | 4932 | |
f37fcc2a | 4933 | intel_update_watermarks(crtc); |
e1fdc473 | 4934 | intel_enable_pipe(intel_crtc); |
42db64ef | 4935 | |
6e3c9717 | 4936 | if (intel_crtc->config->has_pch_encoder) |
1507e5bd | 4937 | lpt_pch_enable(crtc); |
4f771f10 | 4938 | |
6e3c9717 | 4939 | if (intel_crtc->config->dp_encoder_is_mst) |
0e32b39c DA |
4940 | intel_ddi_set_vc_payload_alloc(crtc, true); |
4941 | ||
f9b61ff6 DV |
4942 | assert_vblank_disabled(crtc); |
4943 | drm_crtc_vblank_on(crtc); | |
4944 | ||
8807e55b | 4945 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4f771f10 | 4946 | encoder->enable(encoder); |
8807e55b JN |
4947 | intel_opregion_notify_encoder(encoder, true); |
4948 | } | |
4f771f10 | 4949 | |
e4916946 PZ |
4950 | /* If we change the relative order between pipe/planes enabling, we need |
4951 | * to change the workaround. */ | |
99d736a2 ML |
4952 | hsw_workaround_pipe = pipe_config->hsw_workaround_pipe; |
4953 | if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) { | |
4954 | intel_wait_for_vblank(dev, hsw_workaround_pipe); | |
4955 | intel_wait_for_vblank(dev, hsw_workaround_pipe); | |
4956 | } | |
4f771f10 PZ |
4957 | } |
4958 | ||
3f8dce3a DV |
4959 | static void ironlake_pfit_disable(struct intel_crtc *crtc) |
4960 | { | |
4961 | struct drm_device *dev = crtc->base.dev; | |
4962 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4963 | int pipe = crtc->pipe; | |
4964 | ||
4965 | /* To avoid upsetting the power well on haswell only disable the pfit if | |
4966 | * it's in use. The hw state code will make sure we get this right. */ | |
6e3c9717 | 4967 | if (crtc->config->pch_pfit.enabled) { |
3f8dce3a DV |
4968 | I915_WRITE(PF_CTL(pipe), 0); |
4969 | I915_WRITE(PF_WIN_POS(pipe), 0); | |
4970 | I915_WRITE(PF_WIN_SZ(pipe), 0); | |
4971 | } | |
4972 | } | |
4973 | ||
6be4a607 JB |
4974 | static void ironlake_crtc_disable(struct drm_crtc *crtc) |
4975 | { | |
4976 | struct drm_device *dev = crtc->dev; | |
4977 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4978 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 4979 | struct intel_encoder *encoder; |
6be4a607 | 4980 | int pipe = intel_crtc->pipe; |
5eddb70b | 4981 | u32 reg, temp; |
b52eb4dc | 4982 | |
53d9f4e9 | 4983 | if (WARN_ON(!intel_crtc->active)) |
f7abfe8b CW |
4984 | return; |
4985 | ||
ea9d758d DV |
4986 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4987 | encoder->disable(encoder); | |
4988 | ||
f9b61ff6 DV |
4989 | drm_crtc_vblank_off(crtc); |
4990 | assert_vblank_disabled(crtc); | |
4991 | ||
6e3c9717 | 4992 | if (intel_crtc->config->has_pch_encoder) |
a72e4c9f | 4993 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); |
d925c59a | 4994 | |
575f7ab7 | 4995 | intel_disable_pipe(intel_crtc); |
32f9d658 | 4996 | |
3f8dce3a | 4997 | ironlake_pfit_disable(intel_crtc); |
2c07245f | 4998 | |
5a74f70a VS |
4999 | if (intel_crtc->config->has_pch_encoder) |
5000 | ironlake_fdi_disable(crtc); | |
5001 | ||
bf49ec8c DV |
5002 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5003 | if (encoder->post_disable) | |
5004 | encoder->post_disable(encoder); | |
2c07245f | 5005 | |
6e3c9717 | 5006 | if (intel_crtc->config->has_pch_encoder) { |
d925c59a | 5007 | ironlake_disable_pch_transcoder(dev_priv, pipe); |
6be4a607 | 5008 | |
d925c59a DV |
5009 | if (HAS_PCH_CPT(dev)) { |
5010 | /* disable TRANS_DP_CTL */ | |
5011 | reg = TRANS_DP_CTL(pipe); | |
5012 | temp = I915_READ(reg); | |
5013 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | | |
5014 | TRANS_DP_PORT_SEL_MASK); | |
5015 | temp |= TRANS_DP_PORT_SEL_NONE; | |
5016 | I915_WRITE(reg, temp); | |
5017 | ||
5018 | /* disable DPLL_SEL */ | |
5019 | temp = I915_READ(PCH_DPLL_SEL); | |
11887397 | 5020 | temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe)); |
d925c59a | 5021 | I915_WRITE(PCH_DPLL_SEL, temp); |
9db4a9c7 | 5022 | } |
e3421a18 | 5023 | |
d925c59a | 5024 | /* disable PCH DPLL */ |
e72f9fbf | 5025 | intel_disable_shared_dpll(intel_crtc); |
8db9d77b | 5026 | |
d925c59a DV |
5027 | ironlake_fdi_pll_disable(intel_crtc); |
5028 | } | |
6b383a7f | 5029 | |
f7abfe8b | 5030 | intel_crtc->active = false; |
46ba614c | 5031 | intel_update_watermarks(crtc); |
d1ebd816 BW |
5032 | |
5033 | mutex_lock(&dev->struct_mutex); | |
7ff0ebcc | 5034 | intel_fbc_update(dev); |
d1ebd816 | 5035 | mutex_unlock(&dev->struct_mutex); |
6be4a607 | 5036 | } |
1b3c7a47 | 5037 | |
4f771f10 | 5038 | static void haswell_crtc_disable(struct drm_crtc *crtc) |
ee7b9f93 | 5039 | { |
4f771f10 PZ |
5040 | struct drm_device *dev = crtc->dev; |
5041 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee7b9f93 | 5042 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4f771f10 | 5043 | struct intel_encoder *encoder; |
6e3c9717 | 5044 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
ee7b9f93 | 5045 | |
53d9f4e9 | 5046 | if (WARN_ON(!intel_crtc->active)) |
4f771f10 PZ |
5047 | return; |
5048 | ||
8807e55b JN |
5049 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
5050 | intel_opregion_notify_encoder(encoder, false); | |
4f771f10 | 5051 | encoder->disable(encoder); |
8807e55b | 5052 | } |
4f771f10 | 5053 | |
f9b61ff6 DV |
5054 | drm_crtc_vblank_off(crtc); |
5055 | assert_vblank_disabled(crtc); | |
5056 | ||
6e3c9717 | 5057 | if (intel_crtc->config->has_pch_encoder) |
a72e4c9f DV |
5058 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
5059 | false); | |
575f7ab7 | 5060 | intel_disable_pipe(intel_crtc); |
4f771f10 | 5061 | |
6e3c9717 | 5062 | if (intel_crtc->config->dp_encoder_is_mst) |
a4bf214f VS |
5063 | intel_ddi_set_vc_payload_alloc(crtc, false); |
5064 | ||
ad80a810 | 5065 | intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); |
4f771f10 | 5066 | |
ff6d9f55 | 5067 | if (INTEL_INFO(dev)->gen == 9) |
a1b2278e | 5068 | skylake_pfit_update(intel_crtc, 0); |
ff6d9f55 | 5069 | else if (INTEL_INFO(dev)->gen < 9) |
bd2e244f | 5070 | ironlake_pfit_disable(intel_crtc); |
ff6d9f55 JB |
5071 | else |
5072 | MISSING_CASE(INTEL_INFO(dev)->gen); | |
4f771f10 | 5073 | |
1f544388 | 5074 | intel_ddi_disable_pipe_clock(intel_crtc); |
4f771f10 | 5075 | |
6e3c9717 | 5076 | if (intel_crtc->config->has_pch_encoder) { |
ab4d966c | 5077 | lpt_disable_pch_transcoder(dev_priv); |
1ad960f2 | 5078 | intel_ddi_fdi_disable(crtc); |
83616634 | 5079 | } |
4f771f10 | 5080 | |
97b040aa ID |
5081 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5082 | if (encoder->post_disable) | |
5083 | encoder->post_disable(encoder); | |
5084 | ||
4f771f10 | 5085 | intel_crtc->active = false; |
46ba614c | 5086 | intel_update_watermarks(crtc); |
4f771f10 PZ |
5087 | |
5088 | mutex_lock(&dev->struct_mutex); | |
7ff0ebcc | 5089 | intel_fbc_update(dev); |
4f771f10 | 5090 | mutex_unlock(&dev->struct_mutex); |
df8ad70c DV |
5091 | |
5092 | if (intel_crtc_to_shared_dpll(intel_crtc)) | |
5093 | intel_disable_shared_dpll(intel_crtc); | |
4f771f10 PZ |
5094 | } |
5095 | ||
2dd24552 JB |
5096 | static void i9xx_pfit_enable(struct intel_crtc *crtc) |
5097 | { | |
5098 | struct drm_device *dev = crtc->base.dev; | |
5099 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6e3c9717 | 5100 | struct intel_crtc_state *pipe_config = crtc->config; |
2dd24552 | 5101 | |
681a8504 | 5102 | if (!pipe_config->gmch_pfit.control) |
2dd24552 JB |
5103 | return; |
5104 | ||
2dd24552 | 5105 | /* |
c0b03411 DV |
5106 | * The panel fitter should only be adjusted whilst the pipe is disabled, |
5107 | * according to register description and PRM. | |
2dd24552 | 5108 | */ |
c0b03411 DV |
5109 | WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE); |
5110 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
2dd24552 | 5111 | |
b074cec8 JB |
5112 | I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios); |
5113 | I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control); | |
5a80c45c DV |
5114 | |
5115 | /* Border color in case we don't scale up to the full screen. Black by | |
5116 | * default, change to something else for debugging. */ | |
5117 | I915_WRITE(BCLRPAT(crtc->pipe), 0); | |
2dd24552 JB |
5118 | } |
5119 | ||
d05410f9 DA |
5120 | static enum intel_display_power_domain port_to_power_domain(enum port port) |
5121 | { | |
5122 | switch (port) { | |
5123 | case PORT_A: | |
5124 | return POWER_DOMAIN_PORT_DDI_A_4_LANES; | |
5125 | case PORT_B: | |
5126 | return POWER_DOMAIN_PORT_DDI_B_4_LANES; | |
5127 | case PORT_C: | |
5128 | return POWER_DOMAIN_PORT_DDI_C_4_LANES; | |
5129 | case PORT_D: | |
5130 | return POWER_DOMAIN_PORT_DDI_D_4_LANES; | |
5131 | default: | |
5132 | WARN_ON_ONCE(1); | |
5133 | return POWER_DOMAIN_PORT_OTHER; | |
5134 | } | |
5135 | } | |
5136 | ||
77d22dca ID |
5137 | #define for_each_power_domain(domain, mask) \ |
5138 | for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \ | |
5139 | if ((1 << (domain)) & (mask)) | |
5140 | ||
319be8ae ID |
5141 | enum intel_display_power_domain |
5142 | intel_display_port_power_domain(struct intel_encoder *intel_encoder) | |
5143 | { | |
5144 | struct drm_device *dev = intel_encoder->base.dev; | |
5145 | struct intel_digital_port *intel_dig_port; | |
5146 | ||
5147 | switch (intel_encoder->type) { | |
5148 | case INTEL_OUTPUT_UNKNOWN: | |
5149 | /* Only DDI platforms should ever use this output type */ | |
5150 | WARN_ON_ONCE(!HAS_DDI(dev)); | |
5151 | case INTEL_OUTPUT_DISPLAYPORT: | |
5152 | case INTEL_OUTPUT_HDMI: | |
5153 | case INTEL_OUTPUT_EDP: | |
5154 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
d05410f9 | 5155 | return port_to_power_domain(intel_dig_port->port); |
0e32b39c DA |
5156 | case INTEL_OUTPUT_DP_MST: |
5157 | intel_dig_port = enc_to_mst(&intel_encoder->base)->primary; | |
5158 | return port_to_power_domain(intel_dig_port->port); | |
319be8ae ID |
5159 | case INTEL_OUTPUT_ANALOG: |
5160 | return POWER_DOMAIN_PORT_CRT; | |
5161 | case INTEL_OUTPUT_DSI: | |
5162 | return POWER_DOMAIN_PORT_DSI; | |
5163 | default: | |
5164 | return POWER_DOMAIN_PORT_OTHER; | |
5165 | } | |
5166 | } | |
5167 | ||
5168 | static unsigned long get_crtc_power_domains(struct drm_crtc *crtc) | |
77d22dca | 5169 | { |
319be8ae ID |
5170 | struct drm_device *dev = crtc->dev; |
5171 | struct intel_encoder *intel_encoder; | |
5172 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5173 | enum pipe pipe = intel_crtc->pipe; | |
77d22dca ID |
5174 | unsigned long mask; |
5175 | enum transcoder transcoder; | |
5176 | ||
5177 | transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe); | |
5178 | ||
5179 | mask = BIT(POWER_DOMAIN_PIPE(pipe)); | |
5180 | mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder)); | |
6e3c9717 ACO |
5181 | if (intel_crtc->config->pch_pfit.enabled || |
5182 | intel_crtc->config->pch_pfit.force_thru) | |
77d22dca ID |
5183 | mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe)); |
5184 | ||
319be8ae ID |
5185 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) |
5186 | mask |= BIT(intel_display_port_power_domain(intel_encoder)); | |
5187 | ||
77d22dca ID |
5188 | return mask; |
5189 | } | |
5190 | ||
679dacd4 | 5191 | static void modeset_update_crtc_power_domains(struct drm_atomic_state *state) |
77d22dca | 5192 | { |
679dacd4 | 5193 | struct drm_device *dev = state->dev; |
77d22dca ID |
5194 | struct drm_i915_private *dev_priv = dev->dev_private; |
5195 | unsigned long pipe_domains[I915_MAX_PIPES] = { 0, }; | |
5196 | struct intel_crtc *crtc; | |
5197 | ||
5198 | /* | |
5199 | * First get all needed power domains, then put all unneeded, to avoid | |
5200 | * any unnecessary toggling of the power wells. | |
5201 | */ | |
d3fcc808 | 5202 | for_each_intel_crtc(dev, crtc) { |
77d22dca ID |
5203 | enum intel_display_power_domain domain; |
5204 | ||
83d65738 | 5205 | if (!crtc->base.state->enable) |
77d22dca ID |
5206 | continue; |
5207 | ||
319be8ae | 5208 | pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base); |
77d22dca ID |
5209 | |
5210 | for_each_power_domain(domain, pipe_domains[crtc->pipe]) | |
5211 | intel_display_power_get(dev_priv, domain); | |
5212 | } | |
5213 | ||
50f6e502 | 5214 | if (dev_priv->display.modeset_global_resources) |
679dacd4 | 5215 | dev_priv->display.modeset_global_resources(state); |
50f6e502 | 5216 | |
d3fcc808 | 5217 | for_each_intel_crtc(dev, crtc) { |
77d22dca ID |
5218 | enum intel_display_power_domain domain; |
5219 | ||
5220 | for_each_power_domain(domain, crtc->enabled_power_domains) | |
5221 | intel_display_power_put(dev_priv, domain); | |
5222 | ||
5223 | crtc->enabled_power_domains = pipe_domains[crtc->pipe]; | |
5224 | } | |
5225 | ||
5226 | intel_display_set_init_power(dev_priv, false); | |
5227 | } | |
5228 | ||
560a7ae4 DL |
5229 | static void intel_update_max_cdclk(struct drm_device *dev) |
5230 | { | |
5231 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5232 | ||
5233 | if (IS_SKYLAKE(dev)) { | |
5234 | u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK; | |
5235 | ||
5236 | if (limit == SKL_DFSM_CDCLK_LIMIT_675) | |
5237 | dev_priv->max_cdclk_freq = 675000; | |
5238 | else if (limit == SKL_DFSM_CDCLK_LIMIT_540) | |
5239 | dev_priv->max_cdclk_freq = 540000; | |
5240 | else if (limit == SKL_DFSM_CDCLK_LIMIT_450) | |
5241 | dev_priv->max_cdclk_freq = 450000; | |
5242 | else | |
5243 | dev_priv->max_cdclk_freq = 337500; | |
5244 | } else if (IS_BROADWELL(dev)) { | |
5245 | /* | |
5246 | * FIXME with extra cooling we can allow | |
5247 | * 540 MHz for ULX and 675 Mhz for ULT. | |
5248 | * How can we know if extra cooling is | |
5249 | * available? PCI ID, VTB, something else? | |
5250 | */ | |
5251 | if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
5252 | dev_priv->max_cdclk_freq = 450000; | |
5253 | else if (IS_BDW_ULX(dev)) | |
5254 | dev_priv->max_cdclk_freq = 450000; | |
5255 | else if (IS_BDW_ULT(dev)) | |
5256 | dev_priv->max_cdclk_freq = 540000; | |
5257 | else | |
5258 | dev_priv->max_cdclk_freq = 675000; | |
5259 | } else if (IS_VALLEYVIEW(dev)) { | |
5260 | dev_priv->max_cdclk_freq = 400000; | |
5261 | } else { | |
5262 | /* otherwise assume cdclk is fixed */ | |
5263 | dev_priv->max_cdclk_freq = dev_priv->cdclk_freq; | |
5264 | } | |
5265 | ||
5266 | DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n", | |
5267 | dev_priv->max_cdclk_freq); | |
5268 | } | |
5269 | ||
5270 | static void intel_update_cdclk(struct drm_device *dev) | |
5271 | { | |
5272 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5273 | ||
5274 | dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev); | |
5275 | DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n", | |
5276 | dev_priv->cdclk_freq); | |
5277 | ||
5278 | /* | |
5279 | * Program the gmbus_freq based on the cdclk frequency. | |
5280 | * BSpec erroneously claims we should aim for 4MHz, but | |
5281 | * in fact 1MHz is the correct frequency. | |
5282 | */ | |
5283 | if (IS_VALLEYVIEW(dev)) { | |
5284 | /* | |
5285 | * Program the gmbus_freq based on the cdclk frequency. | |
5286 | * BSpec erroneously claims we should aim for 4MHz, but | |
5287 | * in fact 1MHz is the correct frequency. | |
5288 | */ | |
5289 | I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000)); | |
5290 | } | |
5291 | ||
5292 | if (dev_priv->max_cdclk_freq == 0) | |
5293 | intel_update_max_cdclk(dev); | |
5294 | } | |
5295 | ||
70d0c574 | 5296 | static void broxton_set_cdclk(struct drm_device *dev, int frequency) |
f8437dd1 VK |
5297 | { |
5298 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5299 | uint32_t divider; | |
5300 | uint32_t ratio; | |
5301 | uint32_t current_freq; | |
5302 | int ret; | |
5303 | ||
5304 | /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */ | |
5305 | switch (frequency) { | |
5306 | case 144000: | |
5307 | divider = BXT_CDCLK_CD2X_DIV_SEL_4; | |
5308 | ratio = BXT_DE_PLL_RATIO(60); | |
5309 | break; | |
5310 | case 288000: | |
5311 | divider = BXT_CDCLK_CD2X_DIV_SEL_2; | |
5312 | ratio = BXT_DE_PLL_RATIO(60); | |
5313 | break; | |
5314 | case 384000: | |
5315 | divider = BXT_CDCLK_CD2X_DIV_SEL_1_5; | |
5316 | ratio = BXT_DE_PLL_RATIO(60); | |
5317 | break; | |
5318 | case 576000: | |
5319 | divider = BXT_CDCLK_CD2X_DIV_SEL_1; | |
5320 | ratio = BXT_DE_PLL_RATIO(60); | |
5321 | break; | |
5322 | case 624000: | |
5323 | divider = BXT_CDCLK_CD2X_DIV_SEL_1; | |
5324 | ratio = BXT_DE_PLL_RATIO(65); | |
5325 | break; | |
5326 | case 19200: | |
5327 | /* | |
5328 | * Bypass frequency with DE PLL disabled. Init ratio, divider | |
5329 | * to suppress GCC warning. | |
5330 | */ | |
5331 | ratio = 0; | |
5332 | divider = 0; | |
5333 | break; | |
5334 | default: | |
5335 | DRM_ERROR("unsupported CDCLK freq %d", frequency); | |
5336 | ||
5337 | return; | |
5338 | } | |
5339 | ||
5340 | mutex_lock(&dev_priv->rps.hw_lock); | |
5341 | /* Inform power controller of upcoming frequency change */ | |
5342 | ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, | |
5343 | 0x80000000); | |
5344 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5345 | ||
5346 | if (ret) { | |
5347 | DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n", | |
5348 | ret, frequency); | |
5349 | return; | |
5350 | } | |
5351 | ||
5352 | current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK; | |
5353 | /* convert from .1 fixpoint MHz with -1MHz offset to kHz */ | |
5354 | current_freq = current_freq * 500 + 1000; | |
5355 | ||
5356 | /* | |
5357 | * DE PLL has to be disabled when | |
5358 | * - setting to 19.2MHz (bypass, PLL isn't used) | |
5359 | * - before setting to 624MHz (PLL needs toggling) | |
5360 | * - before setting to any frequency from 624MHz (PLL needs toggling) | |
5361 | */ | |
5362 | if (frequency == 19200 || frequency == 624000 || | |
5363 | current_freq == 624000) { | |
5364 | I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE); | |
5365 | /* Timeout 200us */ | |
5366 | if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK), | |
5367 | 1)) | |
5368 | DRM_ERROR("timout waiting for DE PLL unlock\n"); | |
5369 | } | |
5370 | ||
5371 | if (frequency != 19200) { | |
5372 | uint32_t val; | |
5373 | ||
5374 | val = I915_READ(BXT_DE_PLL_CTL); | |
5375 | val &= ~BXT_DE_PLL_RATIO_MASK; | |
5376 | val |= ratio; | |
5377 | I915_WRITE(BXT_DE_PLL_CTL, val); | |
5378 | ||
5379 | I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE); | |
5380 | /* Timeout 200us */ | |
5381 | if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1)) | |
5382 | DRM_ERROR("timeout waiting for DE PLL lock\n"); | |
5383 | ||
5384 | val = I915_READ(CDCLK_CTL); | |
5385 | val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK; | |
5386 | val |= divider; | |
5387 | /* | |
5388 | * Disable SSA Precharge when CD clock frequency < 500 MHz, | |
5389 | * enable otherwise. | |
5390 | */ | |
5391 | val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE; | |
5392 | if (frequency >= 500000) | |
5393 | val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; | |
5394 | ||
5395 | val &= ~CDCLK_FREQ_DECIMAL_MASK; | |
5396 | /* convert from kHz to .1 fixpoint MHz with -1MHz offset */ | |
5397 | val |= (frequency - 1000) / 500; | |
5398 | I915_WRITE(CDCLK_CTL, val); | |
5399 | } | |
5400 | ||
5401 | mutex_lock(&dev_priv->rps.hw_lock); | |
5402 | ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, | |
5403 | DIV_ROUND_UP(frequency, 25000)); | |
5404 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5405 | ||
5406 | if (ret) { | |
5407 | DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n", | |
5408 | ret, frequency); | |
5409 | return; | |
5410 | } | |
5411 | ||
a47871bd | 5412 | intel_update_cdclk(dev); |
f8437dd1 VK |
5413 | } |
5414 | ||
5415 | void broxton_init_cdclk(struct drm_device *dev) | |
5416 | { | |
5417 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5418 | uint32_t val; | |
5419 | ||
5420 | /* | |
5421 | * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT | |
5422 | * or else the reset will hang because there is no PCH to respond. | |
5423 | * Move the handshake programming to initialization sequence. | |
5424 | * Previously was left up to BIOS. | |
5425 | */ | |
5426 | val = I915_READ(HSW_NDE_RSTWRN_OPT); | |
5427 | val &= ~RESET_PCH_HANDSHAKE_ENABLE; | |
5428 | I915_WRITE(HSW_NDE_RSTWRN_OPT, val); | |
5429 | ||
5430 | /* Enable PG1 for cdclk */ | |
5431 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); | |
5432 | ||
5433 | /* check if cd clock is enabled */ | |
5434 | if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) { | |
5435 | DRM_DEBUG_KMS("Display already initialized\n"); | |
5436 | return; | |
5437 | } | |
5438 | ||
5439 | /* | |
5440 | * FIXME: | |
5441 | * - The initial CDCLK needs to be read from VBT. | |
5442 | * Need to make this change after VBT has changes for BXT. | |
5443 | * - check if setting the max (or any) cdclk freq is really necessary | |
5444 | * here, it belongs to modeset time | |
5445 | */ | |
5446 | broxton_set_cdclk(dev, 624000); | |
5447 | ||
5448 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST); | |
22e02c0b VS |
5449 | POSTING_READ(DBUF_CTL); |
5450 | ||
f8437dd1 VK |
5451 | udelay(10); |
5452 | ||
5453 | if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE)) | |
5454 | DRM_ERROR("DBuf power enable timeout!\n"); | |
5455 | } | |
5456 | ||
5457 | void broxton_uninit_cdclk(struct drm_device *dev) | |
5458 | { | |
5459 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5460 | ||
5461 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST); | |
22e02c0b VS |
5462 | POSTING_READ(DBUF_CTL); |
5463 | ||
f8437dd1 VK |
5464 | udelay(10); |
5465 | ||
5466 | if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE) | |
5467 | DRM_ERROR("DBuf power disable timeout!\n"); | |
5468 | ||
5469 | /* Set minimum (bypass) frequency, in effect turning off the DE PLL */ | |
5470 | broxton_set_cdclk(dev, 19200); | |
5471 | ||
5472 | intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); | |
5473 | } | |
5474 | ||
5d96d8af DL |
5475 | static const struct skl_cdclk_entry { |
5476 | unsigned int freq; | |
5477 | unsigned int vco; | |
5478 | } skl_cdclk_frequencies[] = { | |
5479 | { .freq = 308570, .vco = 8640 }, | |
5480 | { .freq = 337500, .vco = 8100 }, | |
5481 | { .freq = 432000, .vco = 8640 }, | |
5482 | { .freq = 450000, .vco = 8100 }, | |
5483 | { .freq = 540000, .vco = 8100 }, | |
5484 | { .freq = 617140, .vco = 8640 }, | |
5485 | { .freq = 675000, .vco = 8100 }, | |
5486 | }; | |
5487 | ||
5488 | static unsigned int skl_cdclk_decimal(unsigned int freq) | |
5489 | { | |
5490 | return (freq - 1000) / 500; | |
5491 | } | |
5492 | ||
5493 | static unsigned int skl_cdclk_get_vco(unsigned int freq) | |
5494 | { | |
5495 | unsigned int i; | |
5496 | ||
5497 | for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) { | |
5498 | const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i]; | |
5499 | ||
5500 | if (e->freq == freq) | |
5501 | return e->vco; | |
5502 | } | |
5503 | ||
5504 | return 8100; | |
5505 | } | |
5506 | ||
5507 | static void | |
5508 | skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco) | |
5509 | { | |
5510 | unsigned int min_freq; | |
5511 | u32 val; | |
5512 | ||
5513 | /* select the minimum CDCLK before enabling DPLL 0 */ | |
5514 | val = I915_READ(CDCLK_CTL); | |
5515 | val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK; | |
5516 | val |= CDCLK_FREQ_337_308; | |
5517 | ||
5518 | if (required_vco == 8640) | |
5519 | min_freq = 308570; | |
5520 | else | |
5521 | min_freq = 337500; | |
5522 | ||
5523 | val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq); | |
5524 | ||
5525 | I915_WRITE(CDCLK_CTL, val); | |
5526 | POSTING_READ(CDCLK_CTL); | |
5527 | ||
5528 | /* | |
5529 | * We always enable DPLL0 with the lowest link rate possible, but still | |
5530 | * taking into account the VCO required to operate the eDP panel at the | |
5531 | * desired frequency. The usual DP link rates operate with a VCO of | |
5532 | * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640. | |
5533 | * The modeset code is responsible for the selection of the exact link | |
5534 | * rate later on, with the constraint of choosing a frequency that | |
5535 | * works with required_vco. | |
5536 | */ | |
5537 | val = I915_READ(DPLL_CTRL1); | |
5538 | ||
5539 | val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) | | |
5540 | DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)); | |
5541 | val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0); | |
5542 | if (required_vco == 8640) | |
5543 | val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, | |
5544 | SKL_DPLL0); | |
5545 | else | |
5546 | val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, | |
5547 | SKL_DPLL0); | |
5548 | ||
5549 | I915_WRITE(DPLL_CTRL1, val); | |
5550 | POSTING_READ(DPLL_CTRL1); | |
5551 | ||
5552 | I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE); | |
5553 | ||
5554 | if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5)) | |
5555 | DRM_ERROR("DPLL0 not locked\n"); | |
5556 | } | |
5557 | ||
5558 | static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv) | |
5559 | { | |
5560 | int ret; | |
5561 | u32 val; | |
5562 | ||
5563 | /* inform PCU we want to change CDCLK */ | |
5564 | val = SKL_CDCLK_PREPARE_FOR_CHANGE; | |
5565 | mutex_lock(&dev_priv->rps.hw_lock); | |
5566 | ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val); | |
5567 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5568 | ||
5569 | return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE); | |
5570 | } | |
5571 | ||
5572 | static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv) | |
5573 | { | |
5574 | unsigned int i; | |
5575 | ||
5576 | for (i = 0; i < 15; i++) { | |
5577 | if (skl_cdclk_pcu_ready(dev_priv)) | |
5578 | return true; | |
5579 | udelay(10); | |
5580 | } | |
5581 | ||
5582 | return false; | |
5583 | } | |
5584 | ||
5585 | static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq) | |
5586 | { | |
560a7ae4 | 5587 | struct drm_device *dev = dev_priv->dev; |
5d96d8af DL |
5588 | u32 freq_select, pcu_ack; |
5589 | ||
5590 | DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq); | |
5591 | ||
5592 | if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) { | |
5593 | DRM_ERROR("failed to inform PCU about cdclk change\n"); | |
5594 | return; | |
5595 | } | |
5596 | ||
5597 | /* set CDCLK_CTL */ | |
5598 | switch(freq) { | |
5599 | case 450000: | |
5600 | case 432000: | |
5601 | freq_select = CDCLK_FREQ_450_432; | |
5602 | pcu_ack = 1; | |
5603 | break; | |
5604 | case 540000: | |
5605 | freq_select = CDCLK_FREQ_540; | |
5606 | pcu_ack = 2; | |
5607 | break; | |
5608 | case 308570: | |
5609 | case 337500: | |
5610 | default: | |
5611 | freq_select = CDCLK_FREQ_337_308; | |
5612 | pcu_ack = 0; | |
5613 | break; | |
5614 | case 617140: | |
5615 | case 675000: | |
5616 | freq_select = CDCLK_FREQ_675_617; | |
5617 | pcu_ack = 3; | |
5618 | break; | |
5619 | } | |
5620 | ||
5621 | I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq)); | |
5622 | POSTING_READ(CDCLK_CTL); | |
5623 | ||
5624 | /* inform PCU of the change */ | |
5625 | mutex_lock(&dev_priv->rps.hw_lock); | |
5626 | sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack); | |
5627 | mutex_unlock(&dev_priv->rps.hw_lock); | |
560a7ae4 DL |
5628 | |
5629 | intel_update_cdclk(dev); | |
5d96d8af DL |
5630 | } |
5631 | ||
5632 | void skl_uninit_cdclk(struct drm_i915_private *dev_priv) | |
5633 | { | |
5634 | /* disable DBUF power */ | |
5635 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST); | |
5636 | POSTING_READ(DBUF_CTL); | |
5637 | ||
5638 | udelay(10); | |
5639 | ||
5640 | if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE) | |
5641 | DRM_ERROR("DBuf power disable timeout\n"); | |
5642 | ||
5643 | /* disable DPLL0 */ | |
5644 | I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE); | |
5645 | if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1)) | |
5646 | DRM_ERROR("Couldn't disable DPLL0\n"); | |
5647 | ||
5648 | intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); | |
5649 | } | |
5650 | ||
5651 | void skl_init_cdclk(struct drm_i915_private *dev_priv) | |
5652 | { | |
5653 | u32 val; | |
5654 | unsigned int required_vco; | |
5655 | ||
5656 | /* enable PCH reset handshake */ | |
5657 | val = I915_READ(HSW_NDE_RSTWRN_OPT); | |
5658 | I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE); | |
5659 | ||
5660 | /* enable PG1 and Misc I/O */ | |
5661 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); | |
5662 | ||
5663 | /* DPLL0 already enabed !? */ | |
5664 | if (I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE) { | |
5665 | DRM_DEBUG_DRIVER("DPLL0 already running\n"); | |
5666 | return; | |
5667 | } | |
5668 | ||
5669 | /* enable DPLL0 */ | |
5670 | required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk); | |
5671 | skl_dpll0_enable(dev_priv, required_vco); | |
5672 | ||
5673 | /* set CDCLK to the frequency the BIOS chose */ | |
5674 | skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk); | |
5675 | ||
5676 | /* enable DBUF power */ | |
5677 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST); | |
5678 | POSTING_READ(DBUF_CTL); | |
5679 | ||
5680 | udelay(10); | |
5681 | ||
5682 | if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE)) | |
5683 | DRM_ERROR("DBuf power enable timeout\n"); | |
5684 | } | |
5685 | ||
dfcab17e | 5686 | /* returns HPLL frequency in kHz */ |
f8bf63fd | 5687 | static int valleyview_get_vco(struct drm_i915_private *dev_priv) |
30a970c6 | 5688 | { |
586f49dc | 5689 | int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; |
30a970c6 | 5690 | |
586f49dc | 5691 | /* Obtain SKU information */ |
a580516d | 5692 | mutex_lock(&dev_priv->sb_lock); |
586f49dc JB |
5693 | hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & |
5694 | CCK_FUSE_HPLL_FREQ_MASK; | |
a580516d | 5695 | mutex_unlock(&dev_priv->sb_lock); |
30a970c6 | 5696 | |
dfcab17e | 5697 | return vco_freq[hpll_freq] * 1000; |
30a970c6 JB |
5698 | } |
5699 | ||
5700 | /* Adjust CDclk dividers to allow high res or save power if possible */ | |
5701 | static void valleyview_set_cdclk(struct drm_device *dev, int cdclk) | |
5702 | { | |
5703 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5704 | u32 val, cmd; | |
5705 | ||
164dfd28 VK |
5706 | WARN_ON(dev_priv->display.get_display_clock_speed(dev) |
5707 | != dev_priv->cdclk_freq); | |
d60c4473 | 5708 | |
dfcab17e | 5709 | if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */ |
30a970c6 | 5710 | cmd = 2; |
dfcab17e | 5711 | else if (cdclk == 266667) |
30a970c6 JB |
5712 | cmd = 1; |
5713 | else | |
5714 | cmd = 0; | |
5715 | ||
5716 | mutex_lock(&dev_priv->rps.hw_lock); | |
5717 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
5718 | val &= ~DSPFREQGUAR_MASK; | |
5719 | val |= (cmd << DSPFREQGUAR_SHIFT); | |
5720 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
5721 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
5722 | DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT), | |
5723 | 50)) { | |
5724 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
5725 | } | |
5726 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5727 | ||
54433e91 VS |
5728 | mutex_lock(&dev_priv->sb_lock); |
5729 | ||
dfcab17e | 5730 | if (cdclk == 400000) { |
6bcda4f0 | 5731 | u32 divider; |
30a970c6 | 5732 | |
6bcda4f0 | 5733 | divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; |
30a970c6 | 5734 | |
30a970c6 JB |
5735 | /* adjust cdclk divider */ |
5736 | val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); | |
9cf33db5 | 5737 | val &= ~DISPLAY_FREQUENCY_VALUES; |
30a970c6 JB |
5738 | val |= divider; |
5739 | vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val); | |
a877e801 VS |
5740 | |
5741 | if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) & | |
5742 | DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT), | |
5743 | 50)) | |
5744 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
30a970c6 JB |
5745 | } |
5746 | ||
30a970c6 JB |
5747 | /* adjust self-refresh exit latency value */ |
5748 | val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC); | |
5749 | val &= ~0x7f; | |
5750 | ||
5751 | /* | |
5752 | * For high bandwidth configs, we set a higher latency in the bunit | |
5753 | * so that the core display fetch happens in time to avoid underruns. | |
5754 | */ | |
dfcab17e | 5755 | if (cdclk == 400000) |
30a970c6 JB |
5756 | val |= 4500 / 250; /* 4.5 usec */ |
5757 | else | |
5758 | val |= 3000 / 250; /* 3.0 usec */ | |
5759 | vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val); | |
54433e91 | 5760 | |
a580516d | 5761 | mutex_unlock(&dev_priv->sb_lock); |
30a970c6 | 5762 | |
b6283055 | 5763 | intel_update_cdclk(dev); |
30a970c6 JB |
5764 | } |
5765 | ||
383c5a6a VS |
5766 | static void cherryview_set_cdclk(struct drm_device *dev, int cdclk) |
5767 | { | |
5768 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5769 | u32 val, cmd; | |
5770 | ||
164dfd28 VK |
5771 | WARN_ON(dev_priv->display.get_display_clock_speed(dev) |
5772 | != dev_priv->cdclk_freq); | |
383c5a6a VS |
5773 | |
5774 | switch (cdclk) { | |
383c5a6a VS |
5775 | case 333333: |
5776 | case 320000: | |
383c5a6a | 5777 | case 266667: |
383c5a6a | 5778 | case 200000: |
383c5a6a VS |
5779 | break; |
5780 | default: | |
5f77eeb0 | 5781 | MISSING_CASE(cdclk); |
383c5a6a VS |
5782 | return; |
5783 | } | |
5784 | ||
9d0d3fda VS |
5785 | /* |
5786 | * Specs are full of misinformation, but testing on actual | |
5787 | * hardware has shown that we just need to write the desired | |
5788 | * CCK divider into the Punit register. | |
5789 | */ | |
5790 | cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; | |
5791 | ||
383c5a6a VS |
5792 | mutex_lock(&dev_priv->rps.hw_lock); |
5793 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
5794 | val &= ~DSPFREQGUAR_MASK_CHV; | |
5795 | val |= (cmd << DSPFREQGUAR_SHIFT_CHV); | |
5796 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
5797 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
5798 | DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV), | |
5799 | 50)) { | |
5800 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
5801 | } | |
5802 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5803 | ||
b6283055 | 5804 | intel_update_cdclk(dev); |
383c5a6a VS |
5805 | } |
5806 | ||
30a970c6 JB |
5807 | static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv, |
5808 | int max_pixclk) | |
5809 | { | |
6bcda4f0 | 5810 | int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000; |
6cca3195 | 5811 | int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90; |
29dc7ef3 | 5812 | |
30a970c6 JB |
5813 | /* |
5814 | * Really only a few cases to deal with, as only 4 CDclks are supported: | |
5815 | * 200MHz | |
5816 | * 267MHz | |
29dc7ef3 | 5817 | * 320/333MHz (depends on HPLL freq) |
6cca3195 VS |
5818 | * 400MHz (VLV only) |
5819 | * So we check to see whether we're above 90% (VLV) or 95% (CHV) | |
5820 | * of the lower bin and adjust if needed. | |
e37c67a1 VS |
5821 | * |
5822 | * We seem to get an unstable or solid color picture at 200MHz. | |
5823 | * Not sure what's wrong. For now use 200MHz only when all pipes | |
5824 | * are off. | |
30a970c6 | 5825 | */ |
6cca3195 VS |
5826 | if (!IS_CHERRYVIEW(dev_priv) && |
5827 | max_pixclk > freq_320*limit/100) | |
dfcab17e | 5828 | return 400000; |
6cca3195 | 5829 | else if (max_pixclk > 266667*limit/100) |
29dc7ef3 | 5830 | return freq_320; |
e37c67a1 | 5831 | else if (max_pixclk > 0) |
dfcab17e | 5832 | return 266667; |
e37c67a1 VS |
5833 | else |
5834 | return 200000; | |
30a970c6 JB |
5835 | } |
5836 | ||
f8437dd1 VK |
5837 | static int broxton_calc_cdclk(struct drm_i915_private *dev_priv, |
5838 | int max_pixclk) | |
5839 | { | |
5840 | /* | |
5841 | * FIXME: | |
5842 | * - remove the guardband, it's not needed on BXT | |
5843 | * - set 19.2MHz bypass frequency if there are no active pipes | |
5844 | */ | |
5845 | if (max_pixclk > 576000*9/10) | |
5846 | return 624000; | |
5847 | else if (max_pixclk > 384000*9/10) | |
5848 | return 576000; | |
5849 | else if (max_pixclk > 288000*9/10) | |
5850 | return 384000; | |
5851 | else if (max_pixclk > 144000*9/10) | |
5852 | return 288000; | |
5853 | else | |
5854 | return 144000; | |
5855 | } | |
5856 | ||
a821fc46 ACO |
5857 | /* Compute the max pixel clock for new configuration. Uses atomic state if |
5858 | * that's non-NULL, look at current state otherwise. */ | |
5859 | static int intel_mode_max_pixclk(struct drm_device *dev, | |
5860 | struct drm_atomic_state *state) | |
30a970c6 | 5861 | { |
30a970c6 | 5862 | struct intel_crtc *intel_crtc; |
304603f4 | 5863 | struct intel_crtc_state *crtc_state; |
30a970c6 JB |
5864 | int max_pixclk = 0; |
5865 | ||
d3fcc808 | 5866 | for_each_intel_crtc(dev, intel_crtc) { |
a821fc46 ACO |
5867 | if (state) |
5868 | crtc_state = | |
5869 | intel_atomic_get_crtc_state(state, intel_crtc); | |
5870 | else | |
5871 | crtc_state = intel_crtc->config; | |
304603f4 ACO |
5872 | if (IS_ERR(crtc_state)) |
5873 | return PTR_ERR(crtc_state); | |
5874 | ||
5875 | if (!crtc_state->base.enable) | |
5876 | continue; | |
5877 | ||
5878 | max_pixclk = max(max_pixclk, | |
5879 | crtc_state->base.adjusted_mode.crtc_clock); | |
30a970c6 JB |
5880 | } |
5881 | ||
5882 | return max_pixclk; | |
5883 | } | |
5884 | ||
0a9ab303 | 5885 | static int valleyview_modeset_global_pipes(struct drm_atomic_state *state) |
30a970c6 | 5886 | { |
304603f4 | 5887 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
0a9ab303 ACO |
5888 | struct drm_crtc *crtc; |
5889 | struct drm_crtc_state *crtc_state; | |
a821fc46 | 5890 | int max_pixclk = intel_mode_max_pixclk(state->dev, state); |
85a96e7a | 5891 | int cdclk, ret = 0; |
30a970c6 | 5892 | |
304603f4 ACO |
5893 | if (max_pixclk < 0) |
5894 | return max_pixclk; | |
30a970c6 | 5895 | |
f8437dd1 VK |
5896 | if (IS_VALLEYVIEW(dev_priv)) |
5897 | cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk); | |
5898 | else | |
5899 | cdclk = broxton_calc_cdclk(dev_priv, max_pixclk); | |
5900 | ||
5901 | if (cdclk == dev_priv->cdclk_freq) | |
304603f4 | 5902 | return 0; |
30a970c6 | 5903 | |
0a9ab303 ACO |
5904 | /* add all active pipes to the state */ |
5905 | for_each_crtc(state->dev, crtc) { | |
0a9ab303 ACO |
5906 | crtc_state = drm_atomic_get_crtc_state(state, crtc); |
5907 | if (IS_ERR(crtc_state)) | |
5908 | return PTR_ERR(crtc_state); | |
0a9ab303 | 5909 | |
85a96e7a ML |
5910 | if (!crtc_state->active || needs_modeset(crtc_state)) |
5911 | continue; | |
304603f4 | 5912 | |
85a96e7a ML |
5913 | crtc_state->mode_changed = true; |
5914 | ||
5915 | ret = drm_atomic_add_affected_connectors(state, crtc); | |
5916 | if (ret) | |
5917 | break; | |
5918 | ||
5919 | ret = drm_atomic_add_affected_planes(state, crtc); | |
5920 | if (ret) | |
5921 | break; | |
5922 | } | |
5923 | ||
5924 | return ret; | |
30a970c6 JB |
5925 | } |
5926 | ||
1e69cd74 VS |
5927 | static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv) |
5928 | { | |
5929 | unsigned int credits, default_credits; | |
5930 | ||
5931 | if (IS_CHERRYVIEW(dev_priv)) | |
5932 | default_credits = PFI_CREDIT(12); | |
5933 | else | |
5934 | default_credits = PFI_CREDIT(8); | |
5935 | ||
164dfd28 | 5936 | if (DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 1000) >= dev_priv->rps.cz_freq) { |
1e69cd74 VS |
5937 | /* CHV suggested value is 31 or 63 */ |
5938 | if (IS_CHERRYVIEW(dev_priv)) | |
5939 | credits = PFI_CREDIT_31; | |
5940 | else | |
5941 | credits = PFI_CREDIT(15); | |
5942 | } else { | |
5943 | credits = default_credits; | |
5944 | } | |
5945 | ||
5946 | /* | |
5947 | * WA - write default credits before re-programming | |
5948 | * FIXME: should we also set the resend bit here? | |
5949 | */ | |
5950 | I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | | |
5951 | default_credits); | |
5952 | ||
5953 | I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | | |
5954 | credits | PFI_CREDIT_RESEND); | |
5955 | ||
5956 | /* | |
5957 | * FIXME is this guaranteed to clear | |
5958 | * immediately or should we poll for it? | |
5959 | */ | |
5960 | WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND); | |
5961 | } | |
5962 | ||
a821fc46 | 5963 | static void valleyview_modeset_global_resources(struct drm_atomic_state *old_state) |
30a970c6 | 5964 | { |
a821fc46 | 5965 | struct drm_device *dev = old_state->dev; |
30a970c6 | 5966 | struct drm_i915_private *dev_priv = dev->dev_private; |
a821fc46 | 5967 | int max_pixclk = intel_mode_max_pixclk(dev, NULL); |
304603f4 ACO |
5968 | int req_cdclk; |
5969 | ||
a821fc46 ACO |
5970 | /* The path in intel_mode_max_pixclk() with a NULL atomic state should |
5971 | * never fail. */ | |
304603f4 ACO |
5972 | if (WARN_ON(max_pixclk < 0)) |
5973 | return; | |
30a970c6 | 5974 | |
304603f4 | 5975 | req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk); |
30a970c6 | 5976 | |
164dfd28 | 5977 | if (req_cdclk != dev_priv->cdclk_freq) { |
738c05c0 ID |
5978 | /* |
5979 | * FIXME: We can end up here with all power domains off, yet | |
5980 | * with a CDCLK frequency other than the minimum. To account | |
5981 | * for this take the PIPE-A power domain, which covers the HW | |
5982 | * blocks needed for the following programming. This can be | |
5983 | * removed once it's guaranteed that we get here either with | |
5984 | * the minimum CDCLK set, or the required power domains | |
5985 | * enabled. | |
5986 | */ | |
5987 | intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A); | |
5988 | ||
383c5a6a VS |
5989 | if (IS_CHERRYVIEW(dev)) |
5990 | cherryview_set_cdclk(dev, req_cdclk); | |
5991 | else | |
5992 | valleyview_set_cdclk(dev, req_cdclk); | |
738c05c0 | 5993 | |
1e69cd74 VS |
5994 | vlv_program_pfi_credits(dev_priv); |
5995 | ||
738c05c0 | 5996 | intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A); |
383c5a6a | 5997 | } |
30a970c6 JB |
5998 | } |
5999 | ||
89b667f8 JB |
6000 | static void valleyview_crtc_enable(struct drm_crtc *crtc) |
6001 | { | |
6002 | struct drm_device *dev = crtc->dev; | |
a72e4c9f | 6003 | struct drm_i915_private *dev_priv = to_i915(dev); |
89b667f8 JB |
6004 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6005 | struct intel_encoder *encoder; | |
6006 | int pipe = intel_crtc->pipe; | |
23538ef1 | 6007 | bool is_dsi; |
89b667f8 | 6008 | |
53d9f4e9 | 6009 | if (WARN_ON(intel_crtc->active)) |
89b667f8 JB |
6010 | return; |
6011 | ||
409ee761 | 6012 | is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI); |
8525a235 | 6013 | |
1ae0d137 VS |
6014 | if (!is_dsi) { |
6015 | if (IS_CHERRYVIEW(dev)) | |
6e3c9717 | 6016 | chv_prepare_pll(intel_crtc, intel_crtc->config); |
1ae0d137 | 6017 | else |
6e3c9717 | 6018 | vlv_prepare_pll(intel_crtc, intel_crtc->config); |
1ae0d137 | 6019 | } |
5b18e57c | 6020 | |
6e3c9717 | 6021 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 6022 | intel_dp_set_m_n(intel_crtc, M1_N1); |
5b18e57c DV |
6023 | |
6024 | intel_set_pipe_timings(intel_crtc); | |
6025 | ||
c14b0485 VS |
6026 | if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) { |
6027 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6028 | ||
6029 | I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY); | |
6030 | I915_WRITE(CHV_CANVAS(pipe), 0); | |
6031 | } | |
6032 | ||
5b18e57c DV |
6033 | i9xx_set_pipeconf(intel_crtc); |
6034 | ||
89b667f8 | 6035 | intel_crtc->active = true; |
89b667f8 | 6036 | |
a72e4c9f | 6037 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4a3436e8 | 6038 | |
89b667f8 JB |
6039 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6040 | if (encoder->pre_pll_enable) | |
6041 | encoder->pre_pll_enable(encoder); | |
6042 | ||
9d556c99 CML |
6043 | if (!is_dsi) { |
6044 | if (IS_CHERRYVIEW(dev)) | |
6e3c9717 | 6045 | chv_enable_pll(intel_crtc, intel_crtc->config); |
9d556c99 | 6046 | else |
6e3c9717 | 6047 | vlv_enable_pll(intel_crtc, intel_crtc->config); |
9d556c99 | 6048 | } |
89b667f8 JB |
6049 | |
6050 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
6051 | if (encoder->pre_enable) | |
6052 | encoder->pre_enable(encoder); | |
6053 | ||
2dd24552 JB |
6054 | i9xx_pfit_enable(intel_crtc); |
6055 | ||
63cbb074 VS |
6056 | intel_crtc_load_lut(crtc); |
6057 | ||
f37fcc2a | 6058 | intel_update_watermarks(crtc); |
e1fdc473 | 6059 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 6060 | |
4b3a9526 VS |
6061 | assert_vblank_disabled(crtc); |
6062 | drm_crtc_vblank_on(crtc); | |
6063 | ||
f9b61ff6 DV |
6064 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6065 | encoder->enable(encoder); | |
89b667f8 JB |
6066 | } |
6067 | ||
f13c2ef3 DV |
6068 | static void i9xx_set_pll_dividers(struct intel_crtc *crtc) |
6069 | { | |
6070 | struct drm_device *dev = crtc->base.dev; | |
6071 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6072 | ||
6e3c9717 ACO |
6073 | I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0); |
6074 | I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1); | |
f13c2ef3 DV |
6075 | } |
6076 | ||
0b8765c6 | 6077 | static void i9xx_crtc_enable(struct drm_crtc *crtc) |
79e53945 JB |
6078 | { |
6079 | struct drm_device *dev = crtc->dev; | |
a72e4c9f | 6080 | struct drm_i915_private *dev_priv = to_i915(dev); |
79e53945 | 6081 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
ef9c3aee | 6082 | struct intel_encoder *encoder; |
79e53945 | 6083 | int pipe = intel_crtc->pipe; |
79e53945 | 6084 | |
53d9f4e9 | 6085 | if (WARN_ON(intel_crtc->active)) |
f7abfe8b CW |
6086 | return; |
6087 | ||
f13c2ef3 DV |
6088 | i9xx_set_pll_dividers(intel_crtc); |
6089 | ||
6e3c9717 | 6090 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 6091 | intel_dp_set_m_n(intel_crtc, M1_N1); |
5b18e57c DV |
6092 | |
6093 | intel_set_pipe_timings(intel_crtc); | |
6094 | ||
5b18e57c DV |
6095 | i9xx_set_pipeconf(intel_crtc); |
6096 | ||
f7abfe8b | 6097 | intel_crtc->active = true; |
6b383a7f | 6098 | |
4a3436e8 | 6099 | if (!IS_GEN2(dev)) |
a72e4c9f | 6100 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4a3436e8 | 6101 | |
9d6d9f19 MK |
6102 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6103 | if (encoder->pre_enable) | |
6104 | encoder->pre_enable(encoder); | |
6105 | ||
f6736a1a DV |
6106 | i9xx_enable_pll(intel_crtc); |
6107 | ||
2dd24552 JB |
6108 | i9xx_pfit_enable(intel_crtc); |
6109 | ||
63cbb074 VS |
6110 | intel_crtc_load_lut(crtc); |
6111 | ||
f37fcc2a | 6112 | intel_update_watermarks(crtc); |
e1fdc473 | 6113 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 6114 | |
4b3a9526 VS |
6115 | assert_vblank_disabled(crtc); |
6116 | drm_crtc_vblank_on(crtc); | |
6117 | ||
f9b61ff6 DV |
6118 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6119 | encoder->enable(encoder); | |
0b8765c6 | 6120 | } |
79e53945 | 6121 | |
87476d63 DV |
6122 | static void i9xx_pfit_disable(struct intel_crtc *crtc) |
6123 | { | |
6124 | struct drm_device *dev = crtc->base.dev; | |
6125 | struct drm_i915_private *dev_priv = dev->dev_private; | |
87476d63 | 6126 | |
6e3c9717 | 6127 | if (!crtc->config->gmch_pfit.control) |
328d8e82 | 6128 | return; |
87476d63 | 6129 | |
328d8e82 | 6130 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87476d63 | 6131 | |
328d8e82 DV |
6132 | DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", |
6133 | I915_READ(PFIT_CONTROL)); | |
6134 | I915_WRITE(PFIT_CONTROL, 0); | |
87476d63 DV |
6135 | } |
6136 | ||
0b8765c6 JB |
6137 | static void i9xx_crtc_disable(struct drm_crtc *crtc) |
6138 | { | |
6139 | struct drm_device *dev = crtc->dev; | |
6140 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6141 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 6142 | struct intel_encoder *encoder; |
0b8765c6 | 6143 | int pipe = intel_crtc->pipe; |
ef9c3aee | 6144 | |
53d9f4e9 | 6145 | if (WARN_ON(!intel_crtc->active)) |
f7abfe8b CW |
6146 | return; |
6147 | ||
6304cd91 VS |
6148 | /* |
6149 | * On gen2 planes are double buffered but the pipe isn't, so we must | |
6150 | * wait for planes to fully turn off before disabling the pipe. | |
564ed191 ID |
6151 | * We also need to wait on all gmch platforms because of the |
6152 | * self-refresh mode constraint explained above. | |
6304cd91 | 6153 | */ |
564ed191 | 6154 | intel_wait_for_vblank(dev, pipe); |
6304cd91 | 6155 | |
4b3a9526 VS |
6156 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6157 | encoder->disable(encoder); | |
6158 | ||
f9b61ff6 DV |
6159 | drm_crtc_vblank_off(crtc); |
6160 | assert_vblank_disabled(crtc); | |
6161 | ||
575f7ab7 | 6162 | intel_disable_pipe(intel_crtc); |
24a1f16d | 6163 | |
87476d63 | 6164 | i9xx_pfit_disable(intel_crtc); |
24a1f16d | 6165 | |
89b667f8 JB |
6166 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6167 | if (encoder->post_disable) | |
6168 | encoder->post_disable(encoder); | |
6169 | ||
409ee761 | 6170 | if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) { |
076ed3b2 CML |
6171 | if (IS_CHERRYVIEW(dev)) |
6172 | chv_disable_pll(dev_priv, pipe); | |
6173 | else if (IS_VALLEYVIEW(dev)) | |
6174 | vlv_disable_pll(dev_priv, pipe); | |
6175 | else | |
1c4e0274 | 6176 | i9xx_disable_pll(intel_crtc); |
076ed3b2 | 6177 | } |
0b8765c6 | 6178 | |
4a3436e8 | 6179 | if (!IS_GEN2(dev)) |
a72e4c9f | 6180 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); |
4a3436e8 | 6181 | |
f7abfe8b | 6182 | intel_crtc->active = false; |
46ba614c | 6183 | intel_update_watermarks(crtc); |
f37fcc2a | 6184 | |
efa9624e | 6185 | mutex_lock(&dev->struct_mutex); |
7ff0ebcc | 6186 | intel_fbc_update(dev); |
efa9624e | 6187 | mutex_unlock(&dev->struct_mutex); |
0b8765c6 JB |
6188 | } |
6189 | ||
6b72d486 ML |
6190 | /* |
6191 | * turn all crtc's off, but do not adjust state | |
6192 | * This has to be paired with a call to intel_modeset_setup_hw_state. | |
6193 | */ | |
06ea0b08 | 6194 | int intel_display_suspend(struct drm_device *dev) |
6b72d486 | 6195 | { |
06ea0b08 ML |
6196 | struct drm_mode_config *config = &dev->mode_config; |
6197 | struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx; | |
6198 | struct drm_atomic_state *state; | |
6b72d486 | 6199 | struct drm_crtc *crtc; |
06ea0b08 ML |
6200 | unsigned crtc_mask = 0; |
6201 | int ret = 0; | |
6202 | ||
6203 | if (WARN_ON(!ctx)) | |
6204 | return 0; | |
6205 | ||
6206 | lockdep_assert_held(&ctx->ww_ctx); | |
6207 | state = drm_atomic_state_alloc(dev); | |
6208 | if (WARN_ON(!state)) | |
6209 | return -ENOMEM; | |
6210 | ||
6211 | state->acquire_ctx = ctx; | |
6212 | state->allow_modeset = true; | |
6b72d486 ML |
6213 | |
6214 | for_each_crtc(dev, crtc) { | |
06ea0b08 ML |
6215 | struct drm_crtc_state *crtc_state = |
6216 | drm_atomic_get_crtc_state(state, crtc); | |
6b72d486 | 6217 | |
06ea0b08 ML |
6218 | ret = PTR_ERR_OR_ZERO(crtc_state); |
6219 | if (ret) | |
6220 | goto free; | |
6221 | ||
6222 | if (!crtc_state->active) | |
6b72d486 ML |
6223 | continue; |
6224 | ||
06ea0b08 ML |
6225 | crtc_state->active = false; |
6226 | crtc_mask |= 1 << drm_crtc_index(crtc); | |
6227 | } | |
6b72d486 | 6228 | |
06ea0b08 ML |
6229 | if (crtc_mask) { |
6230 | ret = intel_set_mode(state); | |
6231 | ||
6232 | if (!ret) { | |
6233 | for_each_crtc(dev, crtc) | |
6234 | if (crtc_mask & (1 << drm_crtc_index(crtc))) | |
6235 | crtc->state->active = true; | |
6236 | ||
6237 | return ret; | |
6238 | } | |
6b72d486 | 6239 | } |
06ea0b08 ML |
6240 | |
6241 | free: | |
6242 | if (ret) | |
6243 | DRM_ERROR("Suspending crtc's failed with %i\n", ret); | |
6244 | drm_atomic_state_free(state); | |
6245 | return ret; | |
6b72d486 ML |
6246 | } |
6247 | ||
b04c5bd6 | 6248 | /* Master function to enable/disable CRTC and corresponding power wells */ |
5da76e94 | 6249 | int intel_crtc_control(struct drm_crtc *crtc, bool enable) |
976f8a20 DV |
6250 | { |
6251 | struct drm_device *dev = crtc->dev; | |
5da76e94 ML |
6252 | struct drm_mode_config *config = &dev->mode_config; |
6253 | struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx; | |
0e572fe7 | 6254 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5da76e94 ML |
6255 | struct intel_crtc_state *pipe_config; |
6256 | struct drm_atomic_state *state; | |
6257 | int ret; | |
976f8a20 | 6258 | |
1b509259 | 6259 | if (enable == intel_crtc->active) |
5da76e94 | 6260 | return 0; |
1b509259 ML |
6261 | |
6262 | if (enable && !crtc->state->enable) | |
5da76e94 | 6263 | return 0; |
1b509259 | 6264 | |
5da76e94 ML |
6265 | /* this function should be called with drm_modeset_lock_all for now */ |
6266 | if (WARN_ON(!ctx)) | |
6267 | return -EIO; | |
6268 | lockdep_assert_held(&ctx->ww_ctx); | |
1b509259 | 6269 | |
5da76e94 ML |
6270 | state = drm_atomic_state_alloc(dev); |
6271 | if (WARN_ON(!state)) | |
6272 | return -ENOMEM; | |
1b509259 | 6273 | |
5da76e94 ML |
6274 | state->acquire_ctx = ctx; |
6275 | state->allow_modeset = true; | |
6276 | ||
6277 | pipe_config = intel_atomic_get_crtc_state(state, intel_crtc); | |
6278 | if (IS_ERR(pipe_config)) { | |
6279 | ret = PTR_ERR(pipe_config); | |
6280 | goto err; | |
0e572fe7 | 6281 | } |
5da76e94 ML |
6282 | pipe_config->base.active = enable; |
6283 | ||
6284 | ret = intel_set_mode(state); | |
6285 | if (!ret) | |
6286 | return ret; | |
6287 | ||
6288 | err: | |
6289 | DRM_ERROR("Updating crtc active failed with %i\n", ret); | |
6290 | drm_atomic_state_free(state); | |
6291 | return ret; | |
b04c5bd6 BF |
6292 | } |
6293 | ||
6294 | /** | |
6295 | * Sets the power management mode of the pipe and plane. | |
6296 | */ | |
6297 | void intel_crtc_update_dpms(struct drm_crtc *crtc) | |
6298 | { | |
6299 | struct drm_device *dev = crtc->dev; | |
6300 | struct intel_encoder *intel_encoder; | |
6301 | bool enable = false; | |
6302 | ||
6303 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) | |
6304 | enable |= intel_encoder->connectors_active; | |
6305 | ||
6306 | intel_crtc_control(crtc, enable); | |
976f8a20 DV |
6307 | } |
6308 | ||
ea5b213a | 6309 | void intel_encoder_destroy(struct drm_encoder *encoder) |
7e7d76c3 | 6310 | { |
4ef69c7a | 6311 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
ea5b213a | 6312 | |
ea5b213a CW |
6313 | drm_encoder_cleanup(encoder); |
6314 | kfree(intel_encoder); | |
7e7d76c3 JB |
6315 | } |
6316 | ||
9237329d | 6317 | /* Simple dpms helper for encoders with just one connector, no cloning and only |
5ab432ef DV |
6318 | * one kind of off state. It clamps all !ON modes to fully OFF and changes the |
6319 | * state of the entire output pipe. */ | |
9237329d | 6320 | static void intel_encoder_dpms(struct intel_encoder *encoder, int mode) |
7e7d76c3 | 6321 | { |
5ab432ef DV |
6322 | if (mode == DRM_MODE_DPMS_ON) { |
6323 | encoder->connectors_active = true; | |
6324 | ||
b2cabb0e | 6325 | intel_crtc_update_dpms(encoder->base.crtc); |
5ab432ef DV |
6326 | } else { |
6327 | encoder->connectors_active = false; | |
6328 | ||
b2cabb0e | 6329 | intel_crtc_update_dpms(encoder->base.crtc); |
5ab432ef | 6330 | } |
79e53945 JB |
6331 | } |
6332 | ||
0a91ca29 DV |
6333 | /* Cross check the actual hw state with our own modeset state tracking (and it's |
6334 | * internal consistency). */ | |
b980514c | 6335 | static void intel_connector_check_state(struct intel_connector *connector) |
79e53945 | 6336 | { |
0a91ca29 DV |
6337 | if (connector->get_hw_state(connector)) { |
6338 | struct intel_encoder *encoder = connector->encoder; | |
6339 | struct drm_crtc *crtc; | |
6340 | bool encoder_enabled; | |
6341 | enum pipe pipe; | |
6342 | ||
6343 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", | |
6344 | connector->base.base.id, | |
c23cc417 | 6345 | connector->base.name); |
0a91ca29 | 6346 | |
0e32b39c DA |
6347 | /* there is no real hw state for MST connectors */ |
6348 | if (connector->mst_port) | |
6349 | return; | |
6350 | ||
e2c719b7 | 6351 | I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF, |
0a91ca29 | 6352 | "wrong connector dpms state\n"); |
e2c719b7 | 6353 | I915_STATE_WARN(connector->base.encoder != &encoder->base, |
0a91ca29 | 6354 | "active connector not linked to encoder\n"); |
0a91ca29 | 6355 | |
36cd7444 | 6356 | if (encoder) { |
e2c719b7 | 6357 | I915_STATE_WARN(!encoder->connectors_active, |
36cd7444 DA |
6358 | "encoder->connectors_active not set\n"); |
6359 | ||
6360 | encoder_enabled = encoder->get_hw_state(encoder, &pipe); | |
e2c719b7 RC |
6361 | I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n"); |
6362 | if (I915_STATE_WARN_ON(!encoder->base.crtc)) | |
36cd7444 | 6363 | return; |
0a91ca29 | 6364 | |
36cd7444 | 6365 | crtc = encoder->base.crtc; |
0a91ca29 | 6366 | |
83d65738 MR |
6367 | I915_STATE_WARN(!crtc->state->enable, |
6368 | "crtc not enabled\n"); | |
e2c719b7 RC |
6369 | I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n"); |
6370 | I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe, | |
36cd7444 DA |
6371 | "encoder active on the wrong pipe\n"); |
6372 | } | |
0a91ca29 | 6373 | } |
79e53945 JB |
6374 | } |
6375 | ||
08d9bc92 ACO |
6376 | int intel_connector_init(struct intel_connector *connector) |
6377 | { | |
6378 | struct drm_connector_state *connector_state; | |
6379 | ||
6380 | connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL); | |
6381 | if (!connector_state) | |
6382 | return -ENOMEM; | |
6383 | ||
6384 | connector->base.state = connector_state; | |
6385 | return 0; | |
6386 | } | |
6387 | ||
6388 | struct intel_connector *intel_connector_alloc(void) | |
6389 | { | |
6390 | struct intel_connector *connector; | |
6391 | ||
6392 | connector = kzalloc(sizeof *connector, GFP_KERNEL); | |
6393 | if (!connector) | |
6394 | return NULL; | |
6395 | ||
6396 | if (intel_connector_init(connector) < 0) { | |
6397 | kfree(connector); | |
6398 | return NULL; | |
6399 | } | |
6400 | ||
6401 | return connector; | |
6402 | } | |
6403 | ||
5ab432ef DV |
6404 | /* Even simpler default implementation, if there's really no special case to |
6405 | * consider. */ | |
6406 | void intel_connector_dpms(struct drm_connector *connector, int mode) | |
79e53945 | 6407 | { |
5ab432ef DV |
6408 | /* All the simple cases only support two dpms states. */ |
6409 | if (mode != DRM_MODE_DPMS_ON) | |
6410 | mode = DRM_MODE_DPMS_OFF; | |
d4270e57 | 6411 | |
5ab432ef DV |
6412 | if (mode == connector->dpms) |
6413 | return; | |
6414 | ||
6415 | connector->dpms = mode; | |
6416 | ||
6417 | /* Only need to change hw state when actually enabled */ | |
c9976dcf CW |
6418 | if (connector->encoder) |
6419 | intel_encoder_dpms(to_intel_encoder(connector->encoder), mode); | |
0a91ca29 | 6420 | |
b980514c | 6421 | intel_modeset_check_state(connector->dev); |
79e53945 JB |
6422 | } |
6423 | ||
f0947c37 DV |
6424 | /* Simple connector->get_hw_state implementation for encoders that support only |
6425 | * one connector and no cloning and hence the encoder state determines the state | |
6426 | * of the connector. */ | |
6427 | bool intel_connector_get_hw_state(struct intel_connector *connector) | |
ea5b213a | 6428 | { |
24929352 | 6429 | enum pipe pipe = 0; |
f0947c37 | 6430 | struct intel_encoder *encoder = connector->encoder; |
ea5b213a | 6431 | |
f0947c37 | 6432 | return encoder->get_hw_state(encoder, &pipe); |
ea5b213a CW |
6433 | } |
6434 | ||
6d293983 | 6435 | static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state) |
d272ddfa | 6436 | { |
6d293983 ACO |
6437 | if (crtc_state->base.enable && crtc_state->has_pch_encoder) |
6438 | return crtc_state->fdi_lanes; | |
d272ddfa VS |
6439 | |
6440 | return 0; | |
6441 | } | |
6442 | ||
6d293983 | 6443 | static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, |
5cec258b | 6444 | struct intel_crtc_state *pipe_config) |
1857e1da | 6445 | { |
6d293983 ACO |
6446 | struct drm_atomic_state *state = pipe_config->base.state; |
6447 | struct intel_crtc *other_crtc; | |
6448 | struct intel_crtc_state *other_crtc_state; | |
6449 | ||
1857e1da DV |
6450 | DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n", |
6451 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6452 | if (pipe_config->fdi_lanes > 4) { | |
6453 | DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n", | |
6454 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6455 | return -EINVAL; |
1857e1da DV |
6456 | } |
6457 | ||
bafb6553 | 6458 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
1857e1da DV |
6459 | if (pipe_config->fdi_lanes > 2) { |
6460 | DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n", | |
6461 | pipe_config->fdi_lanes); | |
6d293983 | 6462 | return -EINVAL; |
1857e1da | 6463 | } else { |
6d293983 | 6464 | return 0; |
1857e1da DV |
6465 | } |
6466 | } | |
6467 | ||
6468 | if (INTEL_INFO(dev)->num_pipes == 2) | |
6d293983 | 6469 | return 0; |
1857e1da DV |
6470 | |
6471 | /* Ivybridge 3 pipe is really complicated */ | |
6472 | switch (pipe) { | |
6473 | case PIPE_A: | |
6d293983 | 6474 | return 0; |
1857e1da | 6475 | case PIPE_B: |
6d293983 ACO |
6476 | if (pipe_config->fdi_lanes <= 2) |
6477 | return 0; | |
6478 | ||
6479 | other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C)); | |
6480 | other_crtc_state = | |
6481 | intel_atomic_get_crtc_state(state, other_crtc); | |
6482 | if (IS_ERR(other_crtc_state)) | |
6483 | return PTR_ERR(other_crtc_state); | |
6484 | ||
6485 | if (pipe_required_fdi_lanes(other_crtc_state) > 0) { | |
1857e1da DV |
6486 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", |
6487 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6488 | return -EINVAL; |
1857e1da | 6489 | } |
6d293983 | 6490 | return 0; |
1857e1da | 6491 | case PIPE_C: |
251cc67c VS |
6492 | if (pipe_config->fdi_lanes > 2) { |
6493 | DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n", | |
6494 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6495 | return -EINVAL; |
251cc67c | 6496 | } |
6d293983 ACO |
6497 | |
6498 | other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B)); | |
6499 | other_crtc_state = | |
6500 | intel_atomic_get_crtc_state(state, other_crtc); | |
6501 | if (IS_ERR(other_crtc_state)) | |
6502 | return PTR_ERR(other_crtc_state); | |
6503 | ||
6504 | if (pipe_required_fdi_lanes(other_crtc_state) > 2) { | |
1857e1da | 6505 | DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n"); |
6d293983 | 6506 | return -EINVAL; |
1857e1da | 6507 | } |
6d293983 | 6508 | return 0; |
1857e1da DV |
6509 | default: |
6510 | BUG(); | |
6511 | } | |
6512 | } | |
6513 | ||
e29c22c0 DV |
6514 | #define RETRY 1 |
6515 | static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, | |
5cec258b | 6516 | struct intel_crtc_state *pipe_config) |
877d48d5 | 6517 | { |
1857e1da | 6518 | struct drm_device *dev = intel_crtc->base.dev; |
2d112de7 | 6519 | struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
6d293983 ACO |
6520 | int lane, link_bw, fdi_dotclock, ret; |
6521 | bool needs_recompute = false; | |
877d48d5 | 6522 | |
e29c22c0 | 6523 | retry: |
877d48d5 DV |
6524 | /* FDI is a binary signal running at ~2.7GHz, encoding |
6525 | * each output octet as 10 bits. The actual frequency | |
6526 | * is stored as a divider into a 100MHz clock, and the | |
6527 | * mode pixel clock is stored in units of 1KHz. | |
6528 | * Hence the bw of each lane in terms of the mode signal | |
6529 | * is: | |
6530 | */ | |
6531 | link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10; | |
6532 | ||
241bfc38 | 6533 | fdi_dotclock = adjusted_mode->crtc_clock; |
877d48d5 | 6534 | |
2bd89a07 | 6535 | lane = ironlake_get_lanes_required(fdi_dotclock, link_bw, |
877d48d5 DV |
6536 | pipe_config->pipe_bpp); |
6537 | ||
6538 | pipe_config->fdi_lanes = lane; | |
6539 | ||
2bd89a07 | 6540 | intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, |
877d48d5 | 6541 | link_bw, &pipe_config->fdi_m_n); |
1857e1da | 6542 | |
6d293983 ACO |
6543 | ret = ironlake_check_fdi_lanes(intel_crtc->base.dev, |
6544 | intel_crtc->pipe, pipe_config); | |
6545 | if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) { | |
e29c22c0 DV |
6546 | pipe_config->pipe_bpp -= 2*3; |
6547 | DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n", | |
6548 | pipe_config->pipe_bpp); | |
6549 | needs_recompute = true; | |
6550 | pipe_config->bw_constrained = true; | |
6551 | ||
6552 | goto retry; | |
6553 | } | |
6554 | ||
6555 | if (needs_recompute) | |
6556 | return RETRY; | |
6557 | ||
6d293983 | 6558 | return ret; |
877d48d5 DV |
6559 | } |
6560 | ||
8cfb3407 VS |
6561 | static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv, |
6562 | struct intel_crtc_state *pipe_config) | |
6563 | { | |
6564 | if (pipe_config->pipe_bpp > 24) | |
6565 | return false; | |
6566 | ||
6567 | /* HSW can handle pixel rate up to cdclk? */ | |
6568 | if (IS_HASWELL(dev_priv->dev)) | |
6569 | return true; | |
6570 | ||
6571 | /* | |
b432e5cf VS |
6572 | * We compare against max which means we must take |
6573 | * the increased cdclk requirement into account when | |
6574 | * calculating the new cdclk. | |
6575 | * | |
6576 | * Should measure whether using a lower cdclk w/o IPS | |
8cfb3407 VS |
6577 | */ |
6578 | return ilk_pipe_pixel_rate(pipe_config) <= | |
6579 | dev_priv->max_cdclk_freq * 95 / 100; | |
6580 | } | |
6581 | ||
42db64ef | 6582 | static void hsw_compute_ips_config(struct intel_crtc *crtc, |
5cec258b | 6583 | struct intel_crtc_state *pipe_config) |
42db64ef | 6584 | { |
8cfb3407 VS |
6585 | struct drm_device *dev = crtc->base.dev; |
6586 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6587 | ||
d330a953 | 6588 | pipe_config->ips_enabled = i915.enable_ips && |
8cfb3407 VS |
6589 | hsw_crtc_supports_ips(crtc) && |
6590 | pipe_config_supports_ips(dev_priv, pipe_config); | |
42db64ef PZ |
6591 | } |
6592 | ||
a43f6e0f | 6593 | static int intel_crtc_compute_config(struct intel_crtc *crtc, |
5cec258b | 6594 | struct intel_crtc_state *pipe_config) |
79e53945 | 6595 | { |
a43f6e0f | 6596 | struct drm_device *dev = crtc->base.dev; |
8bd31e67 | 6597 | struct drm_i915_private *dev_priv = dev->dev_private; |
2d112de7 | 6598 | struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
d03c93d4 | 6599 | int ret; |
89749350 | 6600 | |
ad3a4479 | 6601 | /* FIXME should check pixel clock limits on all platforms */ |
cf532bb2 | 6602 | if (INTEL_INFO(dev)->gen < 4) { |
44913155 | 6603 | int clock_limit = dev_priv->max_cdclk_freq; |
cf532bb2 VS |
6604 | |
6605 | /* | |
6606 | * Enable pixel doubling when the dot clock | |
6607 | * is > 90% of the (display) core speed. | |
6608 | * | |
b397c96b VS |
6609 | * GDG double wide on either pipe, |
6610 | * otherwise pipe A only. | |
cf532bb2 | 6611 | */ |
b397c96b | 6612 | if ((crtc->pipe == PIPE_A || IS_I915G(dev)) && |
241bfc38 | 6613 | adjusted_mode->crtc_clock > clock_limit * 9 / 10) { |
ad3a4479 | 6614 | clock_limit *= 2; |
cf532bb2 | 6615 | pipe_config->double_wide = true; |
ad3a4479 VS |
6616 | } |
6617 | ||
241bfc38 | 6618 | if (adjusted_mode->crtc_clock > clock_limit * 9 / 10) |
e29c22c0 | 6619 | return -EINVAL; |
2c07245f | 6620 | } |
89749350 | 6621 | |
1d1d0e27 VS |
6622 | /* |
6623 | * Pipe horizontal size must be even in: | |
6624 | * - DVO ganged mode | |
6625 | * - LVDS dual channel mode | |
6626 | * - Double wide pipe | |
6627 | */ | |
a93e255f | 6628 | if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) && |
1d1d0e27 VS |
6629 | intel_is_dual_link_lvds(dev)) || pipe_config->double_wide) |
6630 | pipe_config->pipe_src_w &= ~1; | |
6631 | ||
8693a824 DL |
6632 | /* Cantiga+ cannot handle modes with a hsync front porch of 0. |
6633 | * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. | |
44f46b42 CW |
6634 | */ |
6635 | if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) && | |
6636 | adjusted_mode->hsync_start == adjusted_mode->hdisplay) | |
e29c22c0 | 6637 | return -EINVAL; |
44f46b42 | 6638 | |
f5adf94e | 6639 | if (HAS_IPS(dev)) |
a43f6e0f DV |
6640 | hsw_compute_ips_config(crtc, pipe_config); |
6641 | ||
877d48d5 | 6642 | if (pipe_config->has_pch_encoder) |
a43f6e0f | 6643 | return ironlake_fdi_compute_config(crtc, pipe_config); |
877d48d5 | 6644 | |
d03c93d4 CK |
6645 | /* FIXME: remove below call once atomic mode set is place and all crtc |
6646 | * related checks called from atomic_crtc_check function */ | |
6647 | ret = 0; | |
6648 | DRM_DEBUG_KMS("intel_crtc = %p drm_state (pipe_config->base.state) = %p\n", | |
6649 | crtc, pipe_config->base.state); | |
6650 | ret = intel_atomic_setup_scalers(dev, crtc, pipe_config); | |
6651 | ||
6652 | return ret; | |
79e53945 JB |
6653 | } |
6654 | ||
1652d19e VS |
6655 | static int skylake_get_display_clock_speed(struct drm_device *dev) |
6656 | { | |
6657 | struct drm_i915_private *dev_priv = to_i915(dev); | |
6658 | uint32_t lcpll1 = I915_READ(LCPLL1_CTL); | |
6659 | uint32_t cdctl = I915_READ(CDCLK_CTL); | |
6660 | uint32_t linkrate; | |
6661 | ||
414355a7 | 6662 | if (!(lcpll1 & LCPLL_PLL_ENABLE)) |
1652d19e | 6663 | return 24000; /* 24MHz is the cd freq with NSSC ref */ |
1652d19e VS |
6664 | |
6665 | if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540) | |
6666 | return 540000; | |
6667 | ||
6668 | linkrate = (I915_READ(DPLL_CTRL1) & | |
71cd8423 | 6669 | DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1; |
1652d19e | 6670 | |
71cd8423 DL |
6671 | if (linkrate == DPLL_CTRL1_LINK_RATE_2160 || |
6672 | linkrate == DPLL_CTRL1_LINK_RATE_1080) { | |
1652d19e VS |
6673 | /* vco 8640 */ |
6674 | switch (cdctl & CDCLK_FREQ_SEL_MASK) { | |
6675 | case CDCLK_FREQ_450_432: | |
6676 | return 432000; | |
6677 | case CDCLK_FREQ_337_308: | |
6678 | return 308570; | |
6679 | case CDCLK_FREQ_675_617: | |
6680 | return 617140; | |
6681 | default: | |
6682 | WARN(1, "Unknown cd freq selection\n"); | |
6683 | } | |
6684 | } else { | |
6685 | /* vco 8100 */ | |
6686 | switch (cdctl & CDCLK_FREQ_SEL_MASK) { | |
6687 | case CDCLK_FREQ_450_432: | |
6688 | return 450000; | |
6689 | case CDCLK_FREQ_337_308: | |
6690 | return 337500; | |
6691 | case CDCLK_FREQ_675_617: | |
6692 | return 675000; | |
6693 | default: | |
6694 | WARN(1, "Unknown cd freq selection\n"); | |
6695 | } | |
6696 | } | |
6697 | ||
6698 | /* error case, do as if DPLL0 isn't enabled */ | |
6699 | return 24000; | |
6700 | } | |
6701 | ||
6702 | static int broadwell_get_display_clock_speed(struct drm_device *dev) | |
6703 | { | |
6704 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6705 | uint32_t lcpll = I915_READ(LCPLL_CTL); | |
6706 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; | |
6707 | ||
6708 | if (lcpll & LCPLL_CD_SOURCE_FCLK) | |
6709 | return 800000; | |
6710 | else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
6711 | return 450000; | |
6712 | else if (freq == LCPLL_CLK_FREQ_450) | |
6713 | return 450000; | |
6714 | else if (freq == LCPLL_CLK_FREQ_54O_BDW) | |
6715 | return 540000; | |
6716 | else if (freq == LCPLL_CLK_FREQ_337_5_BDW) | |
6717 | return 337500; | |
6718 | else | |
6719 | return 675000; | |
6720 | } | |
6721 | ||
6722 | static int haswell_get_display_clock_speed(struct drm_device *dev) | |
6723 | { | |
6724 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6725 | uint32_t lcpll = I915_READ(LCPLL_CTL); | |
6726 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; | |
6727 | ||
6728 | if (lcpll & LCPLL_CD_SOURCE_FCLK) | |
6729 | return 800000; | |
6730 | else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
6731 | return 450000; | |
6732 | else if (freq == LCPLL_CLK_FREQ_450) | |
6733 | return 450000; | |
6734 | else if (IS_HSW_ULT(dev)) | |
6735 | return 337500; | |
6736 | else | |
6737 | return 540000; | |
79e53945 JB |
6738 | } |
6739 | ||
25eb05fc JB |
6740 | static int valleyview_get_display_clock_speed(struct drm_device *dev) |
6741 | { | |
d197b7d3 | 6742 | struct drm_i915_private *dev_priv = dev->dev_private; |
d197b7d3 VS |
6743 | u32 val; |
6744 | int divider; | |
6745 | ||
6bcda4f0 VS |
6746 | if (dev_priv->hpll_freq == 0) |
6747 | dev_priv->hpll_freq = valleyview_get_vco(dev_priv); | |
6748 | ||
a580516d | 6749 | mutex_lock(&dev_priv->sb_lock); |
d197b7d3 | 6750 | val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); |
a580516d | 6751 | mutex_unlock(&dev_priv->sb_lock); |
d197b7d3 VS |
6752 | |
6753 | divider = val & DISPLAY_FREQUENCY_VALUES; | |
6754 | ||
7d007f40 VS |
6755 | WARN((val & DISPLAY_FREQUENCY_STATUS) != |
6756 | (divider << DISPLAY_FREQUENCY_STATUS_SHIFT), | |
6757 | "cdclk change in progress\n"); | |
6758 | ||
6bcda4f0 | 6759 | return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1); |
25eb05fc JB |
6760 | } |
6761 | ||
b37a6434 VS |
6762 | static int ilk_get_display_clock_speed(struct drm_device *dev) |
6763 | { | |
6764 | return 450000; | |
6765 | } | |
6766 | ||
e70236a8 JB |
6767 | static int i945_get_display_clock_speed(struct drm_device *dev) |
6768 | { | |
6769 | return 400000; | |
6770 | } | |
79e53945 | 6771 | |
e70236a8 | 6772 | static int i915_get_display_clock_speed(struct drm_device *dev) |
79e53945 | 6773 | { |
e907f170 | 6774 | return 333333; |
e70236a8 | 6775 | } |
79e53945 | 6776 | |
e70236a8 JB |
6777 | static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) |
6778 | { | |
6779 | return 200000; | |
6780 | } | |
79e53945 | 6781 | |
257a7ffc DV |
6782 | static int pnv_get_display_clock_speed(struct drm_device *dev) |
6783 | { | |
6784 | u16 gcfgc = 0; | |
6785 | ||
6786 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); | |
6787 | ||
6788 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
6789 | case GC_DISPLAY_CLOCK_267_MHZ_PNV: | |
e907f170 | 6790 | return 266667; |
257a7ffc | 6791 | case GC_DISPLAY_CLOCK_333_MHZ_PNV: |
e907f170 | 6792 | return 333333; |
257a7ffc | 6793 | case GC_DISPLAY_CLOCK_444_MHZ_PNV: |
e907f170 | 6794 | return 444444; |
257a7ffc DV |
6795 | case GC_DISPLAY_CLOCK_200_MHZ_PNV: |
6796 | return 200000; | |
6797 | default: | |
6798 | DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc); | |
6799 | case GC_DISPLAY_CLOCK_133_MHZ_PNV: | |
e907f170 | 6800 | return 133333; |
257a7ffc | 6801 | case GC_DISPLAY_CLOCK_167_MHZ_PNV: |
e907f170 | 6802 | return 166667; |
257a7ffc DV |
6803 | } |
6804 | } | |
6805 | ||
e70236a8 JB |
6806 | static int i915gm_get_display_clock_speed(struct drm_device *dev) |
6807 | { | |
6808 | u16 gcfgc = 0; | |
79e53945 | 6809 | |
e70236a8 JB |
6810 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
6811 | ||
6812 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) | |
e907f170 | 6813 | return 133333; |
e70236a8 JB |
6814 | else { |
6815 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
6816 | case GC_DISPLAY_CLOCK_333_MHZ: | |
e907f170 | 6817 | return 333333; |
e70236a8 JB |
6818 | default: |
6819 | case GC_DISPLAY_CLOCK_190_200_MHZ: | |
6820 | return 190000; | |
79e53945 | 6821 | } |
e70236a8 JB |
6822 | } |
6823 | } | |
6824 | ||
6825 | static int i865_get_display_clock_speed(struct drm_device *dev) | |
6826 | { | |
e907f170 | 6827 | return 266667; |
e70236a8 JB |
6828 | } |
6829 | ||
1b1d2716 | 6830 | static int i85x_get_display_clock_speed(struct drm_device *dev) |
e70236a8 JB |
6831 | { |
6832 | u16 hpllcc = 0; | |
1b1d2716 | 6833 | |
65cd2b3f VS |
6834 | /* |
6835 | * 852GM/852GMV only supports 133 MHz and the HPLLCC | |
6836 | * encoding is different :( | |
6837 | * FIXME is this the right way to detect 852GM/852GMV? | |
6838 | */ | |
6839 | if (dev->pdev->revision == 0x1) | |
6840 | return 133333; | |
6841 | ||
1b1d2716 VS |
6842 | pci_bus_read_config_word(dev->pdev->bus, |
6843 | PCI_DEVFN(0, 3), HPLLCC, &hpllcc); | |
6844 | ||
e70236a8 JB |
6845 | /* Assume that the hardware is in the high speed state. This |
6846 | * should be the default. | |
6847 | */ | |
6848 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { | |
6849 | case GC_CLOCK_133_200: | |
1b1d2716 | 6850 | case GC_CLOCK_133_200_2: |
e70236a8 JB |
6851 | case GC_CLOCK_100_200: |
6852 | return 200000; | |
6853 | case GC_CLOCK_166_250: | |
6854 | return 250000; | |
6855 | case GC_CLOCK_100_133: | |
e907f170 | 6856 | return 133333; |
1b1d2716 VS |
6857 | case GC_CLOCK_133_266: |
6858 | case GC_CLOCK_133_266_2: | |
6859 | case GC_CLOCK_166_266: | |
6860 | return 266667; | |
e70236a8 | 6861 | } |
79e53945 | 6862 | |
e70236a8 JB |
6863 | /* Shouldn't happen */ |
6864 | return 0; | |
6865 | } | |
79e53945 | 6866 | |
e70236a8 JB |
6867 | static int i830_get_display_clock_speed(struct drm_device *dev) |
6868 | { | |
e907f170 | 6869 | return 133333; |
79e53945 JB |
6870 | } |
6871 | ||
34edce2f VS |
6872 | static unsigned int intel_hpll_vco(struct drm_device *dev) |
6873 | { | |
6874 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6875 | static const unsigned int blb_vco[8] = { | |
6876 | [0] = 3200000, | |
6877 | [1] = 4000000, | |
6878 | [2] = 5333333, | |
6879 | [3] = 4800000, | |
6880 | [4] = 6400000, | |
6881 | }; | |
6882 | static const unsigned int pnv_vco[8] = { | |
6883 | [0] = 3200000, | |
6884 | [1] = 4000000, | |
6885 | [2] = 5333333, | |
6886 | [3] = 4800000, | |
6887 | [4] = 2666667, | |
6888 | }; | |
6889 | static const unsigned int cl_vco[8] = { | |
6890 | [0] = 3200000, | |
6891 | [1] = 4000000, | |
6892 | [2] = 5333333, | |
6893 | [3] = 6400000, | |
6894 | [4] = 3333333, | |
6895 | [5] = 3566667, | |
6896 | [6] = 4266667, | |
6897 | }; | |
6898 | static const unsigned int elk_vco[8] = { | |
6899 | [0] = 3200000, | |
6900 | [1] = 4000000, | |
6901 | [2] = 5333333, | |
6902 | [3] = 4800000, | |
6903 | }; | |
6904 | static const unsigned int ctg_vco[8] = { | |
6905 | [0] = 3200000, | |
6906 | [1] = 4000000, | |
6907 | [2] = 5333333, | |
6908 | [3] = 6400000, | |
6909 | [4] = 2666667, | |
6910 | [5] = 4266667, | |
6911 | }; | |
6912 | const unsigned int *vco_table; | |
6913 | unsigned int vco; | |
6914 | uint8_t tmp = 0; | |
6915 | ||
6916 | /* FIXME other chipsets? */ | |
6917 | if (IS_GM45(dev)) | |
6918 | vco_table = ctg_vco; | |
6919 | else if (IS_G4X(dev)) | |
6920 | vco_table = elk_vco; | |
6921 | else if (IS_CRESTLINE(dev)) | |
6922 | vco_table = cl_vco; | |
6923 | else if (IS_PINEVIEW(dev)) | |
6924 | vco_table = pnv_vco; | |
6925 | else if (IS_G33(dev)) | |
6926 | vco_table = blb_vco; | |
6927 | else | |
6928 | return 0; | |
6929 | ||
6930 | tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO); | |
6931 | ||
6932 | vco = vco_table[tmp & 0x7]; | |
6933 | if (vco == 0) | |
6934 | DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp); | |
6935 | else | |
6936 | DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco); | |
6937 | ||
6938 | return vco; | |
6939 | } | |
6940 | ||
6941 | static int gm45_get_display_clock_speed(struct drm_device *dev) | |
6942 | { | |
6943 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev); | |
6944 | uint16_t tmp = 0; | |
6945 | ||
6946 | pci_read_config_word(dev->pdev, GCFGC, &tmp); | |
6947 | ||
6948 | cdclk_sel = (tmp >> 12) & 0x1; | |
6949 | ||
6950 | switch (vco) { | |
6951 | case 2666667: | |
6952 | case 4000000: | |
6953 | case 5333333: | |
6954 | return cdclk_sel ? 333333 : 222222; | |
6955 | case 3200000: | |
6956 | return cdclk_sel ? 320000 : 228571; | |
6957 | default: | |
6958 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp); | |
6959 | return 222222; | |
6960 | } | |
6961 | } | |
6962 | ||
6963 | static int i965gm_get_display_clock_speed(struct drm_device *dev) | |
6964 | { | |
6965 | static const uint8_t div_3200[] = { 16, 10, 8 }; | |
6966 | static const uint8_t div_4000[] = { 20, 12, 10 }; | |
6967 | static const uint8_t div_5333[] = { 24, 16, 14 }; | |
6968 | const uint8_t *div_table; | |
6969 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev); | |
6970 | uint16_t tmp = 0; | |
6971 | ||
6972 | pci_read_config_word(dev->pdev, GCFGC, &tmp); | |
6973 | ||
6974 | cdclk_sel = ((tmp >> 8) & 0x1f) - 1; | |
6975 | ||
6976 | if (cdclk_sel >= ARRAY_SIZE(div_3200)) | |
6977 | goto fail; | |
6978 | ||
6979 | switch (vco) { | |
6980 | case 3200000: | |
6981 | div_table = div_3200; | |
6982 | break; | |
6983 | case 4000000: | |
6984 | div_table = div_4000; | |
6985 | break; | |
6986 | case 5333333: | |
6987 | div_table = div_5333; | |
6988 | break; | |
6989 | default: | |
6990 | goto fail; | |
6991 | } | |
6992 | ||
6993 | return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]); | |
6994 | ||
6995 | fail: | |
6996 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp); | |
6997 | return 200000; | |
6998 | } | |
6999 | ||
7000 | static int g33_get_display_clock_speed(struct drm_device *dev) | |
7001 | { | |
7002 | static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 }; | |
7003 | static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 }; | |
7004 | static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 }; | |
7005 | static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 }; | |
7006 | const uint8_t *div_table; | |
7007 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev); | |
7008 | uint16_t tmp = 0; | |
7009 | ||
7010 | pci_read_config_word(dev->pdev, GCFGC, &tmp); | |
7011 | ||
7012 | cdclk_sel = (tmp >> 4) & 0x7; | |
7013 | ||
7014 | if (cdclk_sel >= ARRAY_SIZE(div_3200)) | |
7015 | goto fail; | |
7016 | ||
7017 | switch (vco) { | |
7018 | case 3200000: | |
7019 | div_table = div_3200; | |
7020 | break; | |
7021 | case 4000000: | |
7022 | div_table = div_4000; | |
7023 | break; | |
7024 | case 4800000: | |
7025 | div_table = div_4800; | |
7026 | break; | |
7027 | case 5333333: | |
7028 | div_table = div_5333; | |
7029 | break; | |
7030 | default: | |
7031 | goto fail; | |
7032 | } | |
7033 | ||
7034 | return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]); | |
7035 | ||
7036 | fail: | |
7037 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp); | |
7038 | return 190476; | |
7039 | } | |
7040 | ||
2c07245f | 7041 | static void |
a65851af | 7042 | intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den) |
2c07245f | 7043 | { |
a65851af VS |
7044 | while (*num > DATA_LINK_M_N_MASK || |
7045 | *den > DATA_LINK_M_N_MASK) { | |
2c07245f ZW |
7046 | *num >>= 1; |
7047 | *den >>= 1; | |
7048 | } | |
7049 | } | |
7050 | ||
a65851af VS |
7051 | static void compute_m_n(unsigned int m, unsigned int n, |
7052 | uint32_t *ret_m, uint32_t *ret_n) | |
7053 | { | |
7054 | *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); | |
7055 | *ret_m = div_u64((uint64_t) m * *ret_n, n); | |
7056 | intel_reduce_m_n_ratio(ret_m, ret_n); | |
7057 | } | |
7058 | ||
e69d0bc1 DV |
7059 | void |
7060 | intel_link_compute_m_n(int bits_per_pixel, int nlanes, | |
7061 | int pixel_clock, int link_clock, | |
7062 | struct intel_link_m_n *m_n) | |
2c07245f | 7063 | { |
e69d0bc1 | 7064 | m_n->tu = 64; |
a65851af VS |
7065 | |
7066 | compute_m_n(bits_per_pixel * pixel_clock, | |
7067 | link_clock * nlanes * 8, | |
7068 | &m_n->gmch_m, &m_n->gmch_n); | |
7069 | ||
7070 | compute_m_n(pixel_clock, link_clock, | |
7071 | &m_n->link_m, &m_n->link_n); | |
2c07245f ZW |
7072 | } |
7073 | ||
a7615030 CW |
7074 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
7075 | { | |
d330a953 JN |
7076 | if (i915.panel_use_ssc >= 0) |
7077 | return i915.panel_use_ssc != 0; | |
41aa3448 | 7078 | return dev_priv->vbt.lvds_use_ssc |
435793df | 7079 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
a7615030 CW |
7080 | } |
7081 | ||
a93e255f ACO |
7082 | static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state, |
7083 | int num_connectors) | |
c65d77d8 | 7084 | { |
a93e255f | 7085 | struct drm_device *dev = crtc_state->base.crtc->dev; |
c65d77d8 JB |
7086 | struct drm_i915_private *dev_priv = dev->dev_private; |
7087 | int refclk; | |
7088 | ||
a93e255f ACO |
7089 | WARN_ON(!crtc_state->base.state); |
7090 | ||
5ab7b0b7 | 7091 | if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) { |
9a0ea498 | 7092 | refclk = 100000; |
a93e255f | 7093 | } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
c65d77d8 | 7094 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) { |
e91e941b VS |
7095 | refclk = dev_priv->vbt.lvds_ssc_freq; |
7096 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
c65d77d8 JB |
7097 | } else if (!IS_GEN2(dev)) { |
7098 | refclk = 96000; | |
7099 | } else { | |
7100 | refclk = 48000; | |
7101 | } | |
7102 | ||
7103 | return refclk; | |
7104 | } | |
7105 | ||
7429e9d4 | 7106 | static uint32_t pnv_dpll_compute_fp(struct dpll *dpll) |
c65d77d8 | 7107 | { |
7df00d7a | 7108 | return (1 << dpll->n) << 16 | dpll->m2; |
7429e9d4 | 7109 | } |
f47709a9 | 7110 | |
7429e9d4 DV |
7111 | static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll) |
7112 | { | |
7113 | return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; | |
c65d77d8 JB |
7114 | } |
7115 | ||
f47709a9 | 7116 | static void i9xx_update_pll_dividers(struct intel_crtc *crtc, |
190f68c5 | 7117 | struct intel_crtc_state *crtc_state, |
a7516a05 JB |
7118 | intel_clock_t *reduced_clock) |
7119 | { | |
f47709a9 | 7120 | struct drm_device *dev = crtc->base.dev; |
a7516a05 JB |
7121 | u32 fp, fp2 = 0; |
7122 | ||
7123 | if (IS_PINEVIEW(dev)) { | |
190f68c5 | 7124 | fp = pnv_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 7125 | if (reduced_clock) |
7429e9d4 | 7126 | fp2 = pnv_dpll_compute_fp(reduced_clock); |
a7516a05 | 7127 | } else { |
190f68c5 | 7128 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 7129 | if (reduced_clock) |
7429e9d4 | 7130 | fp2 = i9xx_dpll_compute_fp(reduced_clock); |
a7516a05 JB |
7131 | } |
7132 | ||
190f68c5 | 7133 | crtc_state->dpll_hw_state.fp0 = fp; |
a7516a05 | 7134 | |
f47709a9 | 7135 | crtc->lowfreq_avail = false; |
a93e255f | 7136 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ab585dea | 7137 | reduced_clock) { |
190f68c5 | 7138 | crtc_state->dpll_hw_state.fp1 = fp2; |
f47709a9 | 7139 | crtc->lowfreq_avail = true; |
a7516a05 | 7140 | } else { |
190f68c5 | 7141 | crtc_state->dpll_hw_state.fp1 = fp; |
a7516a05 JB |
7142 | } |
7143 | } | |
7144 | ||
5e69f97f CML |
7145 | static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe |
7146 | pipe) | |
89b667f8 JB |
7147 | { |
7148 | u32 reg_val; | |
7149 | ||
7150 | /* | |
7151 | * PLLB opamp always calibrates to max value of 0x3f, force enable it | |
7152 | * and set it to a reasonable value instead. | |
7153 | */ | |
ab3c759a | 7154 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 JB |
7155 | reg_val &= 0xffffff00; |
7156 | reg_val |= 0x00000030; | |
ab3c759a | 7157 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 7158 | |
ab3c759a | 7159 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
7160 | reg_val &= 0x8cffffff; |
7161 | reg_val = 0x8c000000; | |
ab3c759a | 7162 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 | 7163 | |
ab3c759a | 7164 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 | 7165 | reg_val &= 0xffffff00; |
ab3c759a | 7166 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 7167 | |
ab3c759a | 7168 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
7169 | reg_val &= 0x00ffffff; |
7170 | reg_val |= 0xb0000000; | |
ab3c759a | 7171 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 JB |
7172 | } |
7173 | ||
b551842d DV |
7174 | static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, |
7175 | struct intel_link_m_n *m_n) | |
7176 | { | |
7177 | struct drm_device *dev = crtc->base.dev; | |
7178 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7179 | int pipe = crtc->pipe; | |
7180 | ||
e3b95f1e DV |
7181 | I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
7182 | I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n); | |
7183 | I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m); | |
7184 | I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n); | |
b551842d DV |
7185 | } |
7186 | ||
7187 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, | |
f769cd24 VK |
7188 | struct intel_link_m_n *m_n, |
7189 | struct intel_link_m_n *m2_n2) | |
b551842d DV |
7190 | { |
7191 | struct drm_device *dev = crtc->base.dev; | |
7192 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7193 | int pipe = crtc->pipe; | |
6e3c9717 | 7194 | enum transcoder transcoder = crtc->config->cpu_transcoder; |
b551842d DV |
7195 | |
7196 | if (INTEL_INFO(dev)->gen >= 5) { | |
7197 | I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); | |
7198 | I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); | |
7199 | I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); | |
7200 | I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n); | |
f769cd24 VK |
7201 | /* M2_N2 registers to be set only for gen < 8 (M2_N2 available |
7202 | * for gen < 8) and if DRRS is supported (to make sure the | |
7203 | * registers are not unnecessarily accessed). | |
7204 | */ | |
44395bfe | 7205 | if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) && |
6e3c9717 | 7206 | crtc->config->has_drrs) { |
f769cd24 VK |
7207 | I915_WRITE(PIPE_DATA_M2(transcoder), |
7208 | TU_SIZE(m2_n2->tu) | m2_n2->gmch_m); | |
7209 | I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n); | |
7210 | I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m); | |
7211 | I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n); | |
7212 | } | |
b551842d | 7213 | } else { |
e3b95f1e DV |
7214 | I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
7215 | I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n); | |
7216 | I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m); | |
7217 | I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n); | |
b551842d DV |
7218 | } |
7219 | } | |
7220 | ||
fe3cd48d | 7221 | void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n) |
03afc4a2 | 7222 | { |
fe3cd48d R |
7223 | struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL; |
7224 | ||
7225 | if (m_n == M1_N1) { | |
7226 | dp_m_n = &crtc->config->dp_m_n; | |
7227 | dp_m2_n2 = &crtc->config->dp_m2_n2; | |
7228 | } else if (m_n == M2_N2) { | |
7229 | ||
7230 | /* | |
7231 | * M2_N2 registers are not supported. Hence m2_n2 divider value | |
7232 | * needs to be programmed into M1_N1. | |
7233 | */ | |
7234 | dp_m_n = &crtc->config->dp_m2_n2; | |
7235 | } else { | |
7236 | DRM_ERROR("Unsupported divider value\n"); | |
7237 | return; | |
7238 | } | |
7239 | ||
6e3c9717 ACO |
7240 | if (crtc->config->has_pch_encoder) |
7241 | intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n); | |
03afc4a2 | 7242 | else |
fe3cd48d | 7243 | intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2); |
03afc4a2 DV |
7244 | } |
7245 | ||
d288f65f | 7246 | static void vlv_update_pll(struct intel_crtc *crtc, |
5cec258b | 7247 | struct intel_crtc_state *pipe_config) |
bdd4b6a6 DV |
7248 | { |
7249 | u32 dpll, dpll_md; | |
7250 | ||
7251 | /* | |
7252 | * Enable DPIO clock input. We should never disable the reference | |
7253 | * clock for pipe B, since VGA hotplug / manual detection depends | |
7254 | * on it. | |
7255 | */ | |
7256 | dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV | | |
7257 | DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV; | |
7258 | /* We should never disable this, set it here for state tracking */ | |
7259 | if (crtc->pipe == PIPE_B) | |
7260 | dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
7261 | dpll |= DPLL_VCO_ENABLE; | |
d288f65f | 7262 | pipe_config->dpll_hw_state.dpll = dpll; |
bdd4b6a6 | 7263 | |
d288f65f | 7264 | dpll_md = (pipe_config->pixel_multiplier - 1) |
bdd4b6a6 | 7265 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
d288f65f | 7266 | pipe_config->dpll_hw_state.dpll_md = dpll_md; |
bdd4b6a6 DV |
7267 | } |
7268 | ||
d288f65f | 7269 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 7270 | const struct intel_crtc_state *pipe_config) |
a0c4da24 | 7271 | { |
f47709a9 | 7272 | struct drm_device *dev = crtc->base.dev; |
a0c4da24 | 7273 | struct drm_i915_private *dev_priv = dev->dev_private; |
f47709a9 | 7274 | int pipe = crtc->pipe; |
bdd4b6a6 | 7275 | u32 mdiv; |
a0c4da24 | 7276 | u32 bestn, bestm1, bestm2, bestp1, bestp2; |
bdd4b6a6 | 7277 | u32 coreclk, reg_val; |
a0c4da24 | 7278 | |
a580516d | 7279 | mutex_lock(&dev_priv->sb_lock); |
09153000 | 7280 | |
d288f65f VS |
7281 | bestn = pipe_config->dpll.n; |
7282 | bestm1 = pipe_config->dpll.m1; | |
7283 | bestm2 = pipe_config->dpll.m2; | |
7284 | bestp1 = pipe_config->dpll.p1; | |
7285 | bestp2 = pipe_config->dpll.p2; | |
a0c4da24 | 7286 | |
89b667f8 JB |
7287 | /* See eDP HDMI DPIO driver vbios notes doc */ |
7288 | ||
7289 | /* PLL B needs special handling */ | |
bdd4b6a6 | 7290 | if (pipe == PIPE_B) |
5e69f97f | 7291 | vlv_pllb_recal_opamp(dev_priv, pipe); |
89b667f8 JB |
7292 | |
7293 | /* Set up Tx target for periodic Rcomp update */ | |
ab3c759a | 7294 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f); |
89b667f8 JB |
7295 | |
7296 | /* Disable target IRef on PLL */ | |
ab3c759a | 7297 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe)); |
89b667f8 | 7298 | reg_val &= 0x00ffffff; |
ab3c759a | 7299 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val); |
89b667f8 JB |
7300 | |
7301 | /* Disable fast lock */ | |
ab3c759a | 7302 | vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610); |
89b667f8 JB |
7303 | |
7304 | /* Set idtafcrecal before PLL is enabled */ | |
a0c4da24 JB |
7305 | mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); |
7306 | mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); | |
7307 | mdiv |= ((bestn << DPIO_N_SHIFT)); | |
a0c4da24 | 7308 | mdiv |= (1 << DPIO_K_SHIFT); |
7df5080b JB |
7309 | |
7310 | /* | |
7311 | * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, | |
7312 | * but we don't support that). | |
7313 | * Note: don't use the DAC post divider as it seems unstable. | |
7314 | */ | |
7315 | mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); | |
ab3c759a | 7316 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 7317 | |
a0c4da24 | 7318 | mdiv |= DPIO_ENABLE_CALIBRATION; |
ab3c759a | 7319 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 7320 | |
89b667f8 | 7321 | /* Set HBR and RBR LPF coefficients */ |
d288f65f | 7322 | if (pipe_config->port_clock == 162000 || |
409ee761 ACO |
7323 | intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) || |
7324 | intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) | |
ab3c759a | 7325 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
885b0120 | 7326 | 0x009f0003); |
89b667f8 | 7327 | else |
ab3c759a | 7328 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
89b667f8 JB |
7329 | 0x00d0000f); |
7330 | ||
681a8504 | 7331 | if (pipe_config->has_dp_encoder) { |
89b667f8 | 7332 | /* Use SSC source */ |
bdd4b6a6 | 7333 | if (pipe == PIPE_A) |
ab3c759a | 7334 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7335 | 0x0df40000); |
7336 | else | |
ab3c759a | 7337 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7338 | 0x0df70000); |
7339 | } else { /* HDMI or VGA */ | |
7340 | /* Use bend source */ | |
bdd4b6a6 | 7341 | if (pipe == PIPE_A) |
ab3c759a | 7342 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7343 | 0x0df70000); |
7344 | else | |
ab3c759a | 7345 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7346 | 0x0df40000); |
7347 | } | |
a0c4da24 | 7348 | |
ab3c759a | 7349 | coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)); |
89b667f8 | 7350 | coreclk = (coreclk & 0x0000ff00) | 0x01c00000; |
409ee761 ACO |
7351 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || |
7352 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) | |
89b667f8 | 7353 | coreclk |= 0x01000000; |
ab3c759a | 7354 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk); |
a0c4da24 | 7355 | |
ab3c759a | 7356 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000); |
a580516d | 7357 | mutex_unlock(&dev_priv->sb_lock); |
a0c4da24 JB |
7358 | } |
7359 | ||
d288f65f | 7360 | static void chv_update_pll(struct intel_crtc *crtc, |
5cec258b | 7361 | struct intel_crtc_state *pipe_config) |
1ae0d137 | 7362 | { |
d288f65f | 7363 | pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV | |
1ae0d137 VS |
7364 | DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS | |
7365 | DPLL_VCO_ENABLE; | |
7366 | if (crtc->pipe != PIPE_A) | |
d288f65f | 7367 | pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; |
1ae0d137 | 7368 | |
d288f65f VS |
7369 | pipe_config->dpll_hw_state.dpll_md = |
7370 | (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
1ae0d137 VS |
7371 | } |
7372 | ||
d288f65f | 7373 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 7374 | const struct intel_crtc_state *pipe_config) |
9d556c99 CML |
7375 | { |
7376 | struct drm_device *dev = crtc->base.dev; | |
7377 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7378 | int pipe = crtc->pipe; | |
7379 | int dpll_reg = DPLL(crtc->pipe); | |
7380 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
9cbe40c1 | 7381 | u32 loopfilter, tribuf_calcntr; |
9d556c99 | 7382 | u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac; |
a945ce7e | 7383 | u32 dpio_val; |
9cbe40c1 | 7384 | int vco; |
9d556c99 | 7385 | |
d288f65f VS |
7386 | bestn = pipe_config->dpll.n; |
7387 | bestm2_frac = pipe_config->dpll.m2 & 0x3fffff; | |
7388 | bestm1 = pipe_config->dpll.m1; | |
7389 | bestm2 = pipe_config->dpll.m2 >> 22; | |
7390 | bestp1 = pipe_config->dpll.p1; | |
7391 | bestp2 = pipe_config->dpll.p2; | |
9cbe40c1 | 7392 | vco = pipe_config->dpll.vco; |
a945ce7e | 7393 | dpio_val = 0; |
9cbe40c1 | 7394 | loopfilter = 0; |
9d556c99 CML |
7395 | |
7396 | /* | |
7397 | * Enable Refclk and SSC | |
7398 | */ | |
a11b0703 | 7399 | I915_WRITE(dpll_reg, |
d288f65f | 7400 | pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); |
a11b0703 | 7401 | |
a580516d | 7402 | mutex_lock(&dev_priv->sb_lock); |
9d556c99 | 7403 | |
9d556c99 CML |
7404 | /* p1 and p2 divider */ |
7405 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port), | |
7406 | 5 << DPIO_CHV_S1_DIV_SHIFT | | |
7407 | bestp1 << DPIO_CHV_P1_DIV_SHIFT | | |
7408 | bestp2 << DPIO_CHV_P2_DIV_SHIFT | | |
7409 | 1 << DPIO_CHV_K_DIV_SHIFT); | |
7410 | ||
7411 | /* Feedback post-divider - m2 */ | |
7412 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2); | |
7413 | ||
7414 | /* Feedback refclk divider - n and m1 */ | |
7415 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port), | |
7416 | DPIO_CHV_M1_DIV_BY_2 | | |
7417 | 1 << DPIO_CHV_N_DIV_SHIFT); | |
7418 | ||
7419 | /* M2 fraction division */ | |
a945ce7e VP |
7420 | if (bestm2_frac) |
7421 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac); | |
9d556c99 CML |
7422 | |
7423 | /* M2 fraction division enable */ | |
a945ce7e VP |
7424 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); |
7425 | dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN); | |
7426 | dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT); | |
7427 | if (bestm2_frac) | |
7428 | dpio_val |= DPIO_CHV_FRAC_DIV_EN; | |
7429 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val); | |
9d556c99 | 7430 | |
de3a0fde VP |
7431 | /* Program digital lock detect threshold */ |
7432 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port)); | |
7433 | dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK | | |
7434 | DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE); | |
7435 | dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT); | |
7436 | if (!bestm2_frac) | |
7437 | dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE; | |
7438 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val); | |
7439 | ||
9d556c99 | 7440 | /* Loop filter */ |
9cbe40c1 VP |
7441 | if (vco == 5400000) { |
7442 | loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7443 | loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT); | |
7444 | loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7445 | tribuf_calcntr = 0x9; | |
7446 | } else if (vco <= 6200000) { | |
7447 | loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7448 | loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT); | |
7449 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7450 | tribuf_calcntr = 0x9; | |
7451 | } else if (vco <= 6480000) { | |
7452 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7453 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
7454 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7455 | tribuf_calcntr = 0x8; | |
7456 | } else { | |
7457 | /* Not supported. Apply the same limits as in the max case */ | |
7458 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7459 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
7460 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7461 | tribuf_calcntr = 0; | |
7462 | } | |
9d556c99 CML |
7463 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter); |
7464 | ||
968040b2 | 7465 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port)); |
9cbe40c1 VP |
7466 | dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK; |
7467 | dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT); | |
7468 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val); | |
7469 | ||
9d556c99 CML |
7470 | /* AFC Recal */ |
7471 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), | |
7472 | vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) | | |
7473 | DPIO_AFC_RECAL); | |
7474 | ||
a580516d | 7475 | mutex_unlock(&dev_priv->sb_lock); |
9d556c99 CML |
7476 | } |
7477 | ||
d288f65f VS |
7478 | /** |
7479 | * vlv_force_pll_on - forcibly enable just the PLL | |
7480 | * @dev_priv: i915 private structure | |
7481 | * @pipe: pipe PLL to enable | |
7482 | * @dpll: PLL configuration | |
7483 | * | |
7484 | * Enable the PLL for @pipe using the supplied @dpll config. To be used | |
7485 | * in cases where we need the PLL enabled even when @pipe is not going to | |
7486 | * be enabled. | |
7487 | */ | |
7488 | void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe, | |
7489 | const struct dpll *dpll) | |
7490 | { | |
7491 | struct intel_crtc *crtc = | |
7492 | to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe)); | |
5cec258b | 7493 | struct intel_crtc_state pipe_config = { |
a93e255f | 7494 | .base.crtc = &crtc->base, |
d288f65f VS |
7495 | .pixel_multiplier = 1, |
7496 | .dpll = *dpll, | |
7497 | }; | |
7498 | ||
7499 | if (IS_CHERRYVIEW(dev)) { | |
7500 | chv_update_pll(crtc, &pipe_config); | |
7501 | chv_prepare_pll(crtc, &pipe_config); | |
7502 | chv_enable_pll(crtc, &pipe_config); | |
7503 | } else { | |
7504 | vlv_update_pll(crtc, &pipe_config); | |
7505 | vlv_prepare_pll(crtc, &pipe_config); | |
7506 | vlv_enable_pll(crtc, &pipe_config); | |
7507 | } | |
7508 | } | |
7509 | ||
7510 | /** | |
7511 | * vlv_force_pll_off - forcibly disable just the PLL | |
7512 | * @dev_priv: i915 private structure | |
7513 | * @pipe: pipe PLL to disable | |
7514 | * | |
7515 | * Disable the PLL for @pipe. To be used in cases where we need | |
7516 | * the PLL enabled even when @pipe is not going to be enabled. | |
7517 | */ | |
7518 | void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe) | |
7519 | { | |
7520 | if (IS_CHERRYVIEW(dev)) | |
7521 | chv_disable_pll(to_i915(dev), pipe); | |
7522 | else | |
7523 | vlv_disable_pll(to_i915(dev), pipe); | |
7524 | } | |
7525 | ||
f47709a9 | 7526 | static void i9xx_update_pll(struct intel_crtc *crtc, |
190f68c5 | 7527 | struct intel_crtc_state *crtc_state, |
f47709a9 | 7528 | intel_clock_t *reduced_clock, |
eb1cbe48 DV |
7529 | int num_connectors) |
7530 | { | |
f47709a9 | 7531 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 7532 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 DV |
7533 | u32 dpll; |
7534 | bool is_sdvo; | |
190f68c5 | 7535 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 7536 | |
190f68c5 | 7537 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 7538 | |
a93e255f ACO |
7539 | is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) || |
7540 | intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI); | |
eb1cbe48 DV |
7541 | |
7542 | dpll = DPLL_VGA_MODE_DIS; | |
7543 | ||
a93e255f | 7544 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
eb1cbe48 DV |
7545 | dpll |= DPLLB_MODE_LVDS; |
7546 | else | |
7547 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
6cc5f341 | 7548 | |
ef1b460d | 7549 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
190f68c5 | 7550 | dpll |= (crtc_state->pixel_multiplier - 1) |
198a037f | 7551 | << SDVO_MULTIPLIER_SHIFT_HIRES; |
eb1cbe48 | 7552 | } |
198a037f DV |
7553 | |
7554 | if (is_sdvo) | |
4a33e48d | 7555 | dpll |= DPLL_SDVO_HIGH_SPEED; |
198a037f | 7556 | |
190f68c5 | 7557 | if (crtc_state->has_dp_encoder) |
4a33e48d | 7558 | dpll |= DPLL_SDVO_HIGH_SPEED; |
eb1cbe48 DV |
7559 | |
7560 | /* compute bitmask from p1 value */ | |
7561 | if (IS_PINEVIEW(dev)) | |
7562 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; | |
7563 | else { | |
7564 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
7565 | if (IS_G4X(dev) && reduced_clock) | |
7566 | dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; | |
7567 | } | |
7568 | switch (clock->p2) { | |
7569 | case 5: | |
7570 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
7571 | break; | |
7572 | case 7: | |
7573 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
7574 | break; | |
7575 | case 10: | |
7576 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
7577 | break; | |
7578 | case 14: | |
7579 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
7580 | break; | |
7581 | } | |
7582 | if (INTEL_INFO(dev)->gen >= 4) | |
7583 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); | |
7584 | ||
190f68c5 | 7585 | if (crtc_state->sdvo_tv_clock) |
eb1cbe48 | 7586 | dpll |= PLL_REF_INPUT_TVCLKINBC; |
a93e255f | 7587 | else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
eb1cbe48 DV |
7588 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
7589 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
7590 | else | |
7591 | dpll |= PLL_REF_INPUT_DREFCLK; | |
7592 | ||
7593 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 7594 | crtc_state->dpll_hw_state.dpll = dpll; |
8bcc2795 | 7595 | |
eb1cbe48 | 7596 | if (INTEL_INFO(dev)->gen >= 4) { |
190f68c5 | 7597 | u32 dpll_md = (crtc_state->pixel_multiplier - 1) |
ef1b460d | 7598 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
190f68c5 | 7599 | crtc_state->dpll_hw_state.dpll_md = dpll_md; |
eb1cbe48 DV |
7600 | } |
7601 | } | |
7602 | ||
f47709a9 | 7603 | static void i8xx_update_pll(struct intel_crtc *crtc, |
190f68c5 | 7604 | struct intel_crtc_state *crtc_state, |
f47709a9 | 7605 | intel_clock_t *reduced_clock, |
eb1cbe48 DV |
7606 | int num_connectors) |
7607 | { | |
f47709a9 | 7608 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 7609 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 | 7610 | u32 dpll; |
190f68c5 | 7611 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 7612 | |
190f68c5 | 7613 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 7614 | |
eb1cbe48 DV |
7615 | dpll = DPLL_VGA_MODE_DIS; |
7616 | ||
a93e255f | 7617 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
eb1cbe48 DV |
7618 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
7619 | } else { | |
7620 | if (clock->p1 == 2) | |
7621 | dpll |= PLL_P1_DIVIDE_BY_TWO; | |
7622 | else | |
7623 | dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
7624 | if (clock->p2 == 4) | |
7625 | dpll |= PLL_P2_DIVIDE_BY_4; | |
7626 | } | |
7627 | ||
a93e255f | 7628 | if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO)) |
4a33e48d DV |
7629 | dpll |= DPLL_DVO_2X_MODE; |
7630 | ||
a93e255f | 7631 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
eb1cbe48 DV |
7632 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
7633 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
7634 | else | |
7635 | dpll |= PLL_REF_INPUT_DREFCLK; | |
7636 | ||
7637 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 7638 | crtc_state->dpll_hw_state.dpll = dpll; |
eb1cbe48 DV |
7639 | } |
7640 | ||
8a654f3b | 7641 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) |
b0e77b9c PZ |
7642 | { |
7643 | struct drm_device *dev = intel_crtc->base.dev; | |
7644 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7645 | enum pipe pipe = intel_crtc->pipe; | |
6e3c9717 | 7646 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
8a654f3b | 7647 | struct drm_display_mode *adjusted_mode = |
6e3c9717 | 7648 | &intel_crtc->config->base.adjusted_mode; |
1caea6e9 VS |
7649 | uint32_t crtc_vtotal, crtc_vblank_end; |
7650 | int vsyncshift = 0; | |
4d8a62ea DV |
7651 | |
7652 | /* We need to be careful not to changed the adjusted mode, for otherwise | |
7653 | * the hw state checker will get angry at the mismatch. */ | |
7654 | crtc_vtotal = adjusted_mode->crtc_vtotal; | |
7655 | crtc_vblank_end = adjusted_mode->crtc_vblank_end; | |
b0e77b9c | 7656 | |
609aeaca | 7657 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
b0e77b9c | 7658 | /* the chip adds 2 halflines automatically */ |
4d8a62ea DV |
7659 | crtc_vtotal -= 1; |
7660 | crtc_vblank_end -= 1; | |
609aeaca | 7661 | |
409ee761 | 7662 | if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
609aeaca VS |
7663 | vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; |
7664 | else | |
7665 | vsyncshift = adjusted_mode->crtc_hsync_start - | |
7666 | adjusted_mode->crtc_htotal / 2; | |
1caea6e9 VS |
7667 | if (vsyncshift < 0) |
7668 | vsyncshift += adjusted_mode->crtc_htotal; | |
b0e77b9c PZ |
7669 | } |
7670 | ||
7671 | if (INTEL_INFO(dev)->gen > 3) | |
fe2b8f9d | 7672 | I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift); |
b0e77b9c | 7673 | |
fe2b8f9d | 7674 | I915_WRITE(HTOTAL(cpu_transcoder), |
b0e77b9c PZ |
7675 | (adjusted_mode->crtc_hdisplay - 1) | |
7676 | ((adjusted_mode->crtc_htotal - 1) << 16)); | |
fe2b8f9d | 7677 | I915_WRITE(HBLANK(cpu_transcoder), |
b0e77b9c PZ |
7678 | (adjusted_mode->crtc_hblank_start - 1) | |
7679 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); | |
fe2b8f9d | 7680 | I915_WRITE(HSYNC(cpu_transcoder), |
b0e77b9c PZ |
7681 | (adjusted_mode->crtc_hsync_start - 1) | |
7682 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); | |
7683 | ||
fe2b8f9d | 7684 | I915_WRITE(VTOTAL(cpu_transcoder), |
b0e77b9c | 7685 | (adjusted_mode->crtc_vdisplay - 1) | |
4d8a62ea | 7686 | ((crtc_vtotal - 1) << 16)); |
fe2b8f9d | 7687 | I915_WRITE(VBLANK(cpu_transcoder), |
b0e77b9c | 7688 | (adjusted_mode->crtc_vblank_start - 1) | |
4d8a62ea | 7689 | ((crtc_vblank_end - 1) << 16)); |
fe2b8f9d | 7690 | I915_WRITE(VSYNC(cpu_transcoder), |
b0e77b9c PZ |
7691 | (adjusted_mode->crtc_vsync_start - 1) | |
7692 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); | |
7693 | ||
b5e508d4 PZ |
7694 | /* Workaround: when the EDP input selection is B, the VTOTAL_B must be |
7695 | * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is | |
7696 | * documented on the DDI_FUNC_CTL register description, EDP Input Select | |
7697 | * bits. */ | |
7698 | if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP && | |
7699 | (pipe == PIPE_B || pipe == PIPE_C)) | |
7700 | I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder))); | |
7701 | ||
b0e77b9c PZ |
7702 | /* pipesrc controls the size that is scaled from, which should |
7703 | * always be the user's requested size. | |
7704 | */ | |
7705 | I915_WRITE(PIPESRC(pipe), | |
6e3c9717 ACO |
7706 | ((intel_crtc->config->pipe_src_w - 1) << 16) | |
7707 | (intel_crtc->config->pipe_src_h - 1)); | |
b0e77b9c PZ |
7708 | } |
7709 | ||
1bd1bd80 | 7710 | static void intel_get_pipe_timings(struct intel_crtc *crtc, |
5cec258b | 7711 | struct intel_crtc_state *pipe_config) |
1bd1bd80 DV |
7712 | { |
7713 | struct drm_device *dev = crtc->base.dev; | |
7714 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7715 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; | |
7716 | uint32_t tmp; | |
7717 | ||
7718 | tmp = I915_READ(HTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
7719 | pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; |
7720 | pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7721 | tmp = I915_READ(HBLANK(cpu_transcoder)); |
2d112de7 ACO |
7722 | pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1; |
7723 | pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7724 | tmp = I915_READ(HSYNC(cpu_transcoder)); |
2d112de7 ACO |
7725 | pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; |
7726 | pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
7727 | |
7728 | tmp = I915_READ(VTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
7729 | pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; |
7730 | pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7731 | tmp = I915_READ(VBLANK(cpu_transcoder)); |
2d112de7 ACO |
7732 | pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1; |
7733 | pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7734 | tmp = I915_READ(VSYNC(cpu_transcoder)); |
2d112de7 ACO |
7735 | pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; |
7736 | pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
7737 | |
7738 | if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) { | |
2d112de7 ACO |
7739 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; |
7740 | pipe_config->base.adjusted_mode.crtc_vtotal += 1; | |
7741 | pipe_config->base.adjusted_mode.crtc_vblank_end += 1; | |
1bd1bd80 DV |
7742 | } |
7743 | ||
7744 | tmp = I915_READ(PIPESRC(crtc->pipe)); | |
37327abd VS |
7745 | pipe_config->pipe_src_h = (tmp & 0xffff) + 1; |
7746 | pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1; | |
7747 | ||
2d112de7 ACO |
7748 | pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h; |
7749 | pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w; | |
1bd1bd80 DV |
7750 | } |
7751 | ||
f6a83288 | 7752 | void intel_mode_from_pipe_config(struct drm_display_mode *mode, |
5cec258b | 7753 | struct intel_crtc_state *pipe_config) |
babea61d | 7754 | { |
2d112de7 ACO |
7755 | mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay; |
7756 | mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal; | |
7757 | mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start; | |
7758 | mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end; | |
babea61d | 7759 | |
2d112de7 ACO |
7760 | mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay; |
7761 | mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal; | |
7762 | mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start; | |
7763 | mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end; | |
babea61d | 7764 | |
2d112de7 | 7765 | mode->flags = pipe_config->base.adjusted_mode.flags; |
babea61d | 7766 | |
2d112de7 ACO |
7767 | mode->clock = pipe_config->base.adjusted_mode.crtc_clock; |
7768 | mode->flags |= pipe_config->base.adjusted_mode.flags; | |
babea61d JB |
7769 | } |
7770 | ||
84b046f3 DV |
7771 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) |
7772 | { | |
7773 | struct drm_device *dev = intel_crtc->base.dev; | |
7774 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7775 | uint32_t pipeconf; | |
7776 | ||
9f11a9e4 | 7777 | pipeconf = 0; |
84b046f3 | 7778 | |
b6b5d049 VS |
7779 | if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
7780 | (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
7781 | pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE; | |
67c72a12 | 7782 | |
6e3c9717 | 7783 | if (intel_crtc->config->double_wide) |
cf532bb2 | 7784 | pipeconf |= PIPECONF_DOUBLE_WIDE; |
84b046f3 | 7785 | |
ff9ce46e DV |
7786 | /* only g4x and later have fancy bpc/dither controls */ |
7787 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { | |
ff9ce46e | 7788 | /* Bspec claims that we can't use dithering for 30bpp pipes. */ |
6e3c9717 | 7789 | if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30) |
ff9ce46e | 7790 | pipeconf |= PIPECONF_DITHER_EN | |
84b046f3 | 7791 | PIPECONF_DITHER_TYPE_SP; |
84b046f3 | 7792 | |
6e3c9717 | 7793 | switch (intel_crtc->config->pipe_bpp) { |
ff9ce46e DV |
7794 | case 18: |
7795 | pipeconf |= PIPECONF_6BPC; | |
7796 | break; | |
7797 | case 24: | |
7798 | pipeconf |= PIPECONF_8BPC; | |
7799 | break; | |
7800 | case 30: | |
7801 | pipeconf |= PIPECONF_10BPC; | |
7802 | break; | |
7803 | default: | |
7804 | /* Case prevented by intel_choose_pipe_bpp_dither. */ | |
7805 | BUG(); | |
84b046f3 DV |
7806 | } |
7807 | } | |
7808 | ||
7809 | if (HAS_PIPE_CXSR(dev)) { | |
7810 | if (intel_crtc->lowfreq_avail) { | |
7811 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); | |
7812 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; | |
7813 | } else { | |
7814 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); | |
84b046f3 DV |
7815 | } |
7816 | } | |
7817 | ||
6e3c9717 | 7818 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { |
efc2cfff | 7819 | if (INTEL_INFO(dev)->gen < 4 || |
409ee761 | 7820 | intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
efc2cfff VS |
7821 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; |
7822 | else | |
7823 | pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT; | |
7824 | } else | |
84b046f3 DV |
7825 | pipeconf |= PIPECONF_PROGRESSIVE; |
7826 | ||
6e3c9717 | 7827 | if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range) |
9f11a9e4 | 7828 | pipeconf |= PIPECONF_COLOR_RANGE_SELECT; |
9c8e09b7 | 7829 | |
84b046f3 DV |
7830 | I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); |
7831 | POSTING_READ(PIPECONF(intel_crtc->pipe)); | |
7832 | } | |
7833 | ||
190f68c5 ACO |
7834 | static int i9xx_crtc_compute_clock(struct intel_crtc *crtc, |
7835 | struct intel_crtc_state *crtc_state) | |
79e53945 | 7836 | { |
c7653199 | 7837 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 7838 | struct drm_i915_private *dev_priv = dev->dev_private; |
c751ce4f | 7839 | int refclk, num_connectors = 0; |
652c393a | 7840 | intel_clock_t clock, reduced_clock; |
a16af721 | 7841 | bool ok, has_reduced_clock = false; |
e9fd1c02 | 7842 | bool is_lvds = false, is_dsi = false; |
5eddb70b | 7843 | struct intel_encoder *encoder; |
d4906093 | 7844 | const intel_limit_t *limit; |
55bb9992 | 7845 | struct drm_atomic_state *state = crtc_state->base.state; |
da3ced29 | 7846 | struct drm_connector *connector; |
55bb9992 ACO |
7847 | struct drm_connector_state *connector_state; |
7848 | int i; | |
79e53945 | 7849 | |
dd3cd74a ACO |
7850 | memset(&crtc_state->dpll_hw_state, 0, |
7851 | sizeof(crtc_state->dpll_hw_state)); | |
7852 | ||
da3ced29 | 7853 | for_each_connector_in_state(state, connector, connector_state, i) { |
55bb9992 ACO |
7854 | if (connector_state->crtc != &crtc->base) |
7855 | continue; | |
7856 | ||
7857 | encoder = to_intel_encoder(connector_state->best_encoder); | |
7858 | ||
5eddb70b | 7859 | switch (encoder->type) { |
79e53945 JB |
7860 | case INTEL_OUTPUT_LVDS: |
7861 | is_lvds = true; | |
7862 | break; | |
e9fd1c02 JN |
7863 | case INTEL_OUTPUT_DSI: |
7864 | is_dsi = true; | |
7865 | break; | |
6847d71b PZ |
7866 | default: |
7867 | break; | |
79e53945 | 7868 | } |
43565a06 | 7869 | |
c751ce4f | 7870 | num_connectors++; |
79e53945 JB |
7871 | } |
7872 | ||
f2335330 | 7873 | if (is_dsi) |
5b18e57c | 7874 | return 0; |
f2335330 | 7875 | |
190f68c5 | 7876 | if (!crtc_state->clock_set) { |
a93e255f | 7877 | refclk = i9xx_get_refclk(crtc_state, num_connectors); |
79e53945 | 7878 | |
e9fd1c02 JN |
7879 | /* |
7880 | * Returns a set of divisors for the desired target clock with | |
7881 | * the given refclk, or FALSE. The returned values represent | |
7882 | * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + | |
7883 | * 2) / p1 / p2. | |
7884 | */ | |
a93e255f ACO |
7885 | limit = intel_limit(crtc_state, refclk); |
7886 | ok = dev_priv->display.find_dpll(limit, crtc_state, | |
190f68c5 | 7887 | crtc_state->port_clock, |
e9fd1c02 | 7888 | refclk, NULL, &clock); |
f2335330 | 7889 | if (!ok) { |
e9fd1c02 JN |
7890 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
7891 | return -EINVAL; | |
7892 | } | |
79e53945 | 7893 | |
f2335330 JN |
7894 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
7895 | /* | |
7896 | * Ensure we match the reduced clock's P to the target | |
7897 | * clock. If the clocks don't match, we can't switch | |
7898 | * the display clock by using the FP0/FP1. In such case | |
7899 | * we will disable the LVDS downclock feature. | |
7900 | */ | |
7901 | has_reduced_clock = | |
a93e255f | 7902 | dev_priv->display.find_dpll(limit, crtc_state, |
f2335330 JN |
7903 | dev_priv->lvds_downclock, |
7904 | refclk, &clock, | |
7905 | &reduced_clock); | |
7906 | } | |
7907 | /* Compat-code for transition, will disappear. */ | |
190f68c5 ACO |
7908 | crtc_state->dpll.n = clock.n; |
7909 | crtc_state->dpll.m1 = clock.m1; | |
7910 | crtc_state->dpll.m2 = clock.m2; | |
7911 | crtc_state->dpll.p1 = clock.p1; | |
7912 | crtc_state->dpll.p2 = clock.p2; | |
f47709a9 | 7913 | } |
7026d4ac | 7914 | |
e9fd1c02 | 7915 | if (IS_GEN2(dev)) { |
190f68c5 | 7916 | i8xx_update_pll(crtc, crtc_state, |
2a8f64ca VP |
7917 | has_reduced_clock ? &reduced_clock : NULL, |
7918 | num_connectors); | |
9d556c99 | 7919 | } else if (IS_CHERRYVIEW(dev)) { |
190f68c5 | 7920 | chv_update_pll(crtc, crtc_state); |
e9fd1c02 | 7921 | } else if (IS_VALLEYVIEW(dev)) { |
190f68c5 | 7922 | vlv_update_pll(crtc, crtc_state); |
e9fd1c02 | 7923 | } else { |
190f68c5 | 7924 | i9xx_update_pll(crtc, crtc_state, |
eb1cbe48 | 7925 | has_reduced_clock ? &reduced_clock : NULL, |
eba905b2 | 7926 | num_connectors); |
e9fd1c02 | 7927 | } |
79e53945 | 7928 | |
c8f7a0db | 7929 | return 0; |
f564048e EA |
7930 | } |
7931 | ||
2fa2fe9a | 7932 | static void i9xx_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 7933 | struct intel_crtc_state *pipe_config) |
2fa2fe9a DV |
7934 | { |
7935 | struct drm_device *dev = crtc->base.dev; | |
7936 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7937 | uint32_t tmp; | |
7938 | ||
dc9e7dec VS |
7939 | if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev))) |
7940 | return; | |
7941 | ||
2fa2fe9a | 7942 | tmp = I915_READ(PFIT_CONTROL); |
06922821 DV |
7943 | if (!(tmp & PFIT_ENABLE)) |
7944 | return; | |
2fa2fe9a | 7945 | |
06922821 | 7946 | /* Check whether the pfit is attached to our pipe. */ |
2fa2fe9a DV |
7947 | if (INTEL_INFO(dev)->gen < 4) { |
7948 | if (crtc->pipe != PIPE_B) | |
7949 | return; | |
2fa2fe9a DV |
7950 | } else { |
7951 | if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) | |
7952 | return; | |
7953 | } | |
7954 | ||
06922821 | 7955 | pipe_config->gmch_pfit.control = tmp; |
2fa2fe9a DV |
7956 | pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS); |
7957 | if (INTEL_INFO(dev)->gen < 5) | |
7958 | pipe_config->gmch_pfit.lvds_border_bits = | |
7959 | I915_READ(LVDS) & LVDS_BORDER_ENABLE; | |
7960 | } | |
7961 | ||
acbec814 | 7962 | static void vlv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 7963 | struct intel_crtc_state *pipe_config) |
acbec814 JB |
7964 | { |
7965 | struct drm_device *dev = crtc->base.dev; | |
7966 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7967 | int pipe = pipe_config->cpu_transcoder; | |
7968 | intel_clock_t clock; | |
7969 | u32 mdiv; | |
662c6ecb | 7970 | int refclk = 100000; |
acbec814 | 7971 | |
f573de5a SK |
7972 | /* In case of MIPI DPLL will not even be used */ |
7973 | if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)) | |
7974 | return; | |
7975 | ||
a580516d | 7976 | mutex_lock(&dev_priv->sb_lock); |
ab3c759a | 7977 | mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); |
a580516d | 7978 | mutex_unlock(&dev_priv->sb_lock); |
acbec814 JB |
7979 | |
7980 | clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; | |
7981 | clock.m2 = mdiv & DPIO_M2DIV_MASK; | |
7982 | clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; | |
7983 | clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; | |
7984 | clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; | |
7985 | ||
f646628b | 7986 | vlv_clock(refclk, &clock); |
acbec814 | 7987 | |
f646628b VS |
7988 | /* clock.dot is the fast clock */ |
7989 | pipe_config->port_clock = clock.dot / 5; | |
acbec814 JB |
7990 | } |
7991 | ||
5724dbd1 DL |
7992 | static void |
7993 | i9xx_get_initial_plane_config(struct intel_crtc *crtc, | |
7994 | struct intel_initial_plane_config *plane_config) | |
1ad292b5 JB |
7995 | { |
7996 | struct drm_device *dev = crtc->base.dev; | |
7997 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7998 | u32 val, base, offset; | |
7999 | int pipe = crtc->pipe, plane = crtc->plane; | |
8000 | int fourcc, pixel_format; | |
6761dd31 | 8001 | unsigned int aligned_height; |
b113d5ee | 8002 | struct drm_framebuffer *fb; |
1b842c89 | 8003 | struct intel_framebuffer *intel_fb; |
1ad292b5 | 8004 | |
42a7b088 DL |
8005 | val = I915_READ(DSPCNTR(plane)); |
8006 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
8007 | return; | |
8008 | ||
d9806c9f | 8009 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 8010 | if (!intel_fb) { |
1ad292b5 JB |
8011 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
8012 | return; | |
8013 | } | |
8014 | ||
1b842c89 DL |
8015 | fb = &intel_fb->base; |
8016 | ||
18c5247e DV |
8017 | if (INTEL_INFO(dev)->gen >= 4) { |
8018 | if (val & DISPPLANE_TILED) { | |
49af449b | 8019 | plane_config->tiling = I915_TILING_X; |
18c5247e DV |
8020 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; |
8021 | } | |
8022 | } | |
1ad292b5 JB |
8023 | |
8024 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 8025 | fourcc = i9xx_format_to_fourcc(pixel_format); |
b113d5ee DL |
8026 | fb->pixel_format = fourcc; |
8027 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
1ad292b5 JB |
8028 | |
8029 | if (INTEL_INFO(dev)->gen >= 4) { | |
49af449b | 8030 | if (plane_config->tiling) |
1ad292b5 JB |
8031 | offset = I915_READ(DSPTILEOFF(plane)); |
8032 | else | |
8033 | offset = I915_READ(DSPLINOFF(plane)); | |
8034 | base = I915_READ(DSPSURF(plane)) & 0xfffff000; | |
8035 | } else { | |
8036 | base = I915_READ(DSPADDR(plane)); | |
8037 | } | |
8038 | plane_config->base = base; | |
8039 | ||
8040 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
8041 | fb->width = ((val >> 16) & 0xfff) + 1; |
8042 | fb->height = ((val >> 0) & 0xfff) + 1; | |
1ad292b5 JB |
8043 | |
8044 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 8045 | fb->pitches[0] = val & 0xffffffc0; |
1ad292b5 | 8046 | |
b113d5ee | 8047 | aligned_height = intel_fb_align_height(dev, fb->height, |
091df6cb DV |
8048 | fb->pixel_format, |
8049 | fb->modifier[0]); | |
1ad292b5 | 8050 | |
f37b5c2b | 8051 | plane_config->size = fb->pitches[0] * aligned_height; |
1ad292b5 | 8052 | |
2844a921 DL |
8053 | DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
8054 | pipe_name(pipe), plane, fb->width, fb->height, | |
8055 | fb->bits_per_pixel, base, fb->pitches[0], | |
8056 | plane_config->size); | |
1ad292b5 | 8057 | |
2d14030b | 8058 | plane_config->fb = intel_fb; |
1ad292b5 JB |
8059 | } |
8060 | ||
70b23a98 | 8061 | static void chv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 8062 | struct intel_crtc_state *pipe_config) |
70b23a98 VS |
8063 | { |
8064 | struct drm_device *dev = crtc->base.dev; | |
8065 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8066 | int pipe = pipe_config->cpu_transcoder; | |
8067 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
8068 | intel_clock_t clock; | |
8069 | u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2; | |
8070 | int refclk = 100000; | |
8071 | ||
a580516d | 8072 | mutex_lock(&dev_priv->sb_lock); |
70b23a98 VS |
8073 | cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)); |
8074 | pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); | |
8075 | pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); | |
8076 | pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); | |
a580516d | 8077 | mutex_unlock(&dev_priv->sb_lock); |
70b23a98 VS |
8078 | |
8079 | clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; | |
8080 | clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff); | |
8081 | clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf; | |
8082 | clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7; | |
8083 | clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f; | |
8084 | ||
8085 | chv_clock(refclk, &clock); | |
8086 | ||
8087 | /* clock.dot is the fast clock */ | |
8088 | pipe_config->port_clock = clock.dot / 5; | |
8089 | } | |
8090 | ||
0e8ffe1b | 8091 | static bool i9xx_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 8092 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
8093 | { |
8094 | struct drm_device *dev = crtc->base.dev; | |
8095 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8096 | uint32_t tmp; | |
8097 | ||
f458ebbc DV |
8098 | if (!intel_display_power_is_enabled(dev_priv, |
8099 | POWER_DOMAIN_PIPE(crtc->pipe))) | |
b5482bd0 ID |
8100 | return false; |
8101 | ||
e143a21c | 8102 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 | 8103 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
eccb140b | 8104 | |
0e8ffe1b DV |
8105 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
8106 | if (!(tmp & PIPECONF_ENABLE)) | |
8107 | return false; | |
8108 | ||
42571aef VS |
8109 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { |
8110 | switch (tmp & PIPECONF_BPC_MASK) { | |
8111 | case PIPECONF_6BPC: | |
8112 | pipe_config->pipe_bpp = 18; | |
8113 | break; | |
8114 | case PIPECONF_8BPC: | |
8115 | pipe_config->pipe_bpp = 24; | |
8116 | break; | |
8117 | case PIPECONF_10BPC: | |
8118 | pipe_config->pipe_bpp = 30; | |
8119 | break; | |
8120 | default: | |
8121 | break; | |
8122 | } | |
8123 | } | |
8124 | ||
b5a9fa09 DV |
8125 | if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT)) |
8126 | pipe_config->limited_color_range = true; | |
8127 | ||
282740f7 VS |
8128 | if (INTEL_INFO(dev)->gen < 4) |
8129 | pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; | |
8130 | ||
1bd1bd80 DV |
8131 | intel_get_pipe_timings(crtc, pipe_config); |
8132 | ||
2fa2fe9a DV |
8133 | i9xx_get_pfit_config(crtc, pipe_config); |
8134 | ||
6c49f241 DV |
8135 | if (INTEL_INFO(dev)->gen >= 4) { |
8136 | tmp = I915_READ(DPLL_MD(crtc->pipe)); | |
8137 | pipe_config->pixel_multiplier = | |
8138 | ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) | |
8139 | >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; | |
8bcc2795 | 8140 | pipe_config->dpll_hw_state.dpll_md = tmp; |
6c49f241 DV |
8141 | } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
8142 | tmp = I915_READ(DPLL(crtc->pipe)); | |
8143 | pipe_config->pixel_multiplier = | |
8144 | ((tmp & SDVO_MULTIPLIER_MASK) | |
8145 | >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; | |
8146 | } else { | |
8147 | /* Note that on i915G/GM the pixel multiplier is in the sdvo | |
8148 | * port and will be fixed up in the encoder->get_config | |
8149 | * function. */ | |
8150 | pipe_config->pixel_multiplier = 1; | |
8151 | } | |
8bcc2795 DV |
8152 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); |
8153 | if (!IS_VALLEYVIEW(dev)) { | |
1c4e0274 VS |
8154 | /* |
8155 | * DPLL_DVO_2X_MODE must be enabled for both DPLLs | |
8156 | * on 830. Filter it out here so that we don't | |
8157 | * report errors due to that. | |
8158 | */ | |
8159 | if (IS_I830(dev)) | |
8160 | pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE; | |
8161 | ||
8bcc2795 DV |
8162 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); |
8163 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); | |
165e901c VS |
8164 | } else { |
8165 | /* Mask out read-only status bits. */ | |
8166 | pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | | |
8167 | DPLL_PORTC_READY_MASK | | |
8168 | DPLL_PORTB_READY_MASK); | |
8bcc2795 | 8169 | } |
6c49f241 | 8170 | |
70b23a98 VS |
8171 | if (IS_CHERRYVIEW(dev)) |
8172 | chv_crtc_clock_get(crtc, pipe_config); | |
8173 | else if (IS_VALLEYVIEW(dev)) | |
acbec814 JB |
8174 | vlv_crtc_clock_get(crtc, pipe_config); |
8175 | else | |
8176 | i9xx_crtc_clock_get(crtc, pipe_config); | |
18442d08 | 8177 | |
0e8ffe1b DV |
8178 | return true; |
8179 | } | |
8180 | ||
dde86e2d | 8181 | static void ironlake_init_pch_refclk(struct drm_device *dev) |
13d83a67 JB |
8182 | { |
8183 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13d83a67 | 8184 | struct intel_encoder *encoder; |
74cfd7ac | 8185 | u32 val, final; |
13d83a67 | 8186 | bool has_lvds = false; |
199e5d79 | 8187 | bool has_cpu_edp = false; |
199e5d79 | 8188 | bool has_panel = false; |
99eb6a01 KP |
8189 | bool has_ck505 = false; |
8190 | bool can_ssc = false; | |
13d83a67 JB |
8191 | |
8192 | /* We need to take the global config into account */ | |
b2784e15 | 8193 | for_each_intel_encoder(dev, encoder) { |
199e5d79 KP |
8194 | switch (encoder->type) { |
8195 | case INTEL_OUTPUT_LVDS: | |
8196 | has_panel = true; | |
8197 | has_lvds = true; | |
8198 | break; | |
8199 | case INTEL_OUTPUT_EDP: | |
8200 | has_panel = true; | |
2de6905f | 8201 | if (enc_to_dig_port(&encoder->base)->port == PORT_A) |
199e5d79 KP |
8202 | has_cpu_edp = true; |
8203 | break; | |
6847d71b PZ |
8204 | default: |
8205 | break; | |
13d83a67 JB |
8206 | } |
8207 | } | |
8208 | ||
99eb6a01 | 8209 | if (HAS_PCH_IBX(dev)) { |
41aa3448 | 8210 | has_ck505 = dev_priv->vbt.display_clock_mode; |
99eb6a01 KP |
8211 | can_ssc = has_ck505; |
8212 | } else { | |
8213 | has_ck505 = false; | |
8214 | can_ssc = true; | |
8215 | } | |
8216 | ||
2de6905f ID |
8217 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n", |
8218 | has_panel, has_lvds, has_ck505); | |
13d83a67 JB |
8219 | |
8220 | /* Ironlake: try to setup display ref clock before DPLL | |
8221 | * enabling. This is only under driver's control after | |
8222 | * PCH B stepping, previous chipset stepping should be | |
8223 | * ignoring this setting. | |
8224 | */ | |
74cfd7ac CW |
8225 | val = I915_READ(PCH_DREF_CONTROL); |
8226 | ||
8227 | /* As we must carefully and slowly disable/enable each source in turn, | |
8228 | * compute the final state we want first and check if we need to | |
8229 | * make any changes at all. | |
8230 | */ | |
8231 | final = val; | |
8232 | final &= ~DREF_NONSPREAD_SOURCE_MASK; | |
8233 | if (has_ck505) | |
8234 | final |= DREF_NONSPREAD_CK505_ENABLE; | |
8235 | else | |
8236 | final |= DREF_NONSPREAD_SOURCE_ENABLE; | |
8237 | ||
8238 | final &= ~DREF_SSC_SOURCE_MASK; | |
8239 | final &= ~DREF_CPU_SOURCE_OUTPUT_MASK; | |
8240 | final &= ~DREF_SSC1_ENABLE; | |
8241 | ||
8242 | if (has_panel) { | |
8243 | final |= DREF_SSC_SOURCE_ENABLE; | |
8244 | ||
8245 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
8246 | final |= DREF_SSC1_ENABLE; | |
8247 | ||
8248 | if (has_cpu_edp) { | |
8249 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
8250 | final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; | |
8251 | else | |
8252 | final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; | |
8253 | } else | |
8254 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
8255 | } else { | |
8256 | final |= DREF_SSC_SOURCE_DISABLE; | |
8257 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
8258 | } | |
8259 | ||
8260 | if (final == val) | |
8261 | return; | |
8262 | ||
13d83a67 | 8263 | /* Always enable nonspread source */ |
74cfd7ac | 8264 | val &= ~DREF_NONSPREAD_SOURCE_MASK; |
13d83a67 | 8265 | |
99eb6a01 | 8266 | if (has_ck505) |
74cfd7ac | 8267 | val |= DREF_NONSPREAD_CK505_ENABLE; |
99eb6a01 | 8268 | else |
74cfd7ac | 8269 | val |= DREF_NONSPREAD_SOURCE_ENABLE; |
13d83a67 | 8270 | |
199e5d79 | 8271 | if (has_panel) { |
74cfd7ac CW |
8272 | val &= ~DREF_SSC_SOURCE_MASK; |
8273 | val |= DREF_SSC_SOURCE_ENABLE; | |
13d83a67 | 8274 | |
199e5d79 | 8275 | /* SSC must be turned on before enabling the CPU output */ |
99eb6a01 | 8276 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 8277 | DRM_DEBUG_KMS("Using SSC on panel\n"); |
74cfd7ac | 8278 | val |= DREF_SSC1_ENABLE; |
e77166b5 | 8279 | } else |
74cfd7ac | 8280 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 KP |
8281 | |
8282 | /* Get SSC going before enabling the outputs */ | |
74cfd7ac | 8283 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
8284 | POSTING_READ(PCH_DREF_CONTROL); |
8285 | udelay(200); | |
8286 | ||
74cfd7ac | 8287 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
13d83a67 JB |
8288 | |
8289 | /* Enable CPU source on CPU attached eDP */ | |
199e5d79 | 8290 | if (has_cpu_edp) { |
99eb6a01 | 8291 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 8292 | DRM_DEBUG_KMS("Using SSC on eDP\n"); |
74cfd7ac | 8293 | val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
eba905b2 | 8294 | } else |
74cfd7ac | 8295 | val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
199e5d79 | 8296 | } else |
74cfd7ac | 8297 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 8298 | |
74cfd7ac | 8299 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
8300 | POSTING_READ(PCH_DREF_CONTROL); |
8301 | udelay(200); | |
8302 | } else { | |
8303 | DRM_DEBUG_KMS("Disabling SSC entirely\n"); | |
8304 | ||
74cfd7ac | 8305 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
199e5d79 KP |
8306 | |
8307 | /* Turn off CPU output */ | |
74cfd7ac | 8308 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 8309 | |
74cfd7ac | 8310 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
8311 | POSTING_READ(PCH_DREF_CONTROL); |
8312 | udelay(200); | |
8313 | ||
8314 | /* Turn off the SSC source */ | |
74cfd7ac CW |
8315 | val &= ~DREF_SSC_SOURCE_MASK; |
8316 | val |= DREF_SSC_SOURCE_DISABLE; | |
199e5d79 KP |
8317 | |
8318 | /* Turn off SSC1 */ | |
74cfd7ac | 8319 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 | 8320 | |
74cfd7ac | 8321 | I915_WRITE(PCH_DREF_CONTROL, val); |
13d83a67 JB |
8322 | POSTING_READ(PCH_DREF_CONTROL); |
8323 | udelay(200); | |
8324 | } | |
74cfd7ac CW |
8325 | |
8326 | BUG_ON(val != final); | |
13d83a67 JB |
8327 | } |
8328 | ||
f31f2d55 | 8329 | static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv) |
dde86e2d | 8330 | { |
f31f2d55 | 8331 | uint32_t tmp; |
dde86e2d | 8332 | |
0ff066a9 PZ |
8333 | tmp = I915_READ(SOUTH_CHICKEN2); |
8334 | tmp |= FDI_MPHY_IOSFSB_RESET_CTL; | |
8335 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 8336 | |
0ff066a9 PZ |
8337 | if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) & |
8338 | FDI_MPHY_IOSFSB_RESET_STATUS, 100)) | |
8339 | DRM_ERROR("FDI mPHY reset assert timeout\n"); | |
dde86e2d | 8340 | |
0ff066a9 PZ |
8341 | tmp = I915_READ(SOUTH_CHICKEN2); |
8342 | tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL; | |
8343 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 8344 | |
0ff066a9 PZ |
8345 | if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) & |
8346 | FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100)) | |
8347 | DRM_ERROR("FDI mPHY reset de-assert timeout\n"); | |
f31f2d55 PZ |
8348 | } |
8349 | ||
8350 | /* WaMPhyProgramming:hsw */ | |
8351 | static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv) | |
8352 | { | |
8353 | uint32_t tmp; | |
dde86e2d PZ |
8354 | |
8355 | tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY); | |
8356 | tmp &= ~(0xFF << 24); | |
8357 | tmp |= (0x12 << 24); | |
8358 | intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY); | |
8359 | ||
dde86e2d PZ |
8360 | tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY); |
8361 | tmp |= (1 << 11); | |
8362 | intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY); | |
8363 | ||
8364 | tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY); | |
8365 | tmp |= (1 << 11); | |
8366 | intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY); | |
8367 | ||
dde86e2d PZ |
8368 | tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY); |
8369 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
8370 | intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY); | |
8371 | ||
8372 | tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY); | |
8373 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
8374 | intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY); | |
8375 | ||
0ff066a9 PZ |
8376 | tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY); |
8377 | tmp &= ~(7 << 13); | |
8378 | tmp |= (5 << 13); | |
8379 | intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY); | |
dde86e2d | 8380 | |
0ff066a9 PZ |
8381 | tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY); |
8382 | tmp &= ~(7 << 13); | |
8383 | tmp |= (5 << 13); | |
8384 | intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY); | |
dde86e2d PZ |
8385 | |
8386 | tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY); | |
8387 | tmp &= ~0xFF; | |
8388 | tmp |= 0x1C; | |
8389 | intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY); | |
8390 | ||
8391 | tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY); | |
8392 | tmp &= ~0xFF; | |
8393 | tmp |= 0x1C; | |
8394 | intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY); | |
8395 | ||
8396 | tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY); | |
8397 | tmp &= ~(0xFF << 16); | |
8398 | tmp |= (0x1C << 16); | |
8399 | intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY); | |
8400 | ||
8401 | tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY); | |
8402 | tmp &= ~(0xFF << 16); | |
8403 | tmp |= (0x1C << 16); | |
8404 | intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY); | |
8405 | ||
0ff066a9 PZ |
8406 | tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY); |
8407 | tmp |= (1 << 27); | |
8408 | intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY); | |
dde86e2d | 8409 | |
0ff066a9 PZ |
8410 | tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY); |
8411 | tmp |= (1 << 27); | |
8412 | intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY); | |
dde86e2d | 8413 | |
0ff066a9 PZ |
8414 | tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY); |
8415 | tmp &= ~(0xF << 28); | |
8416 | tmp |= (4 << 28); | |
8417 | intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY); | |
dde86e2d | 8418 | |
0ff066a9 PZ |
8419 | tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY); |
8420 | tmp &= ~(0xF << 28); | |
8421 | tmp |= (4 << 28); | |
8422 | intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY); | |
f31f2d55 PZ |
8423 | } |
8424 | ||
2fa86a1f PZ |
8425 | /* Implements 3 different sequences from BSpec chapter "Display iCLK |
8426 | * Programming" based on the parameters passed: | |
8427 | * - Sequence to enable CLKOUT_DP | |
8428 | * - Sequence to enable CLKOUT_DP without spread | |
8429 | * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O | |
8430 | */ | |
8431 | static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread, | |
8432 | bool with_fdi) | |
f31f2d55 PZ |
8433 | { |
8434 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2fa86a1f PZ |
8435 | uint32_t reg, tmp; |
8436 | ||
8437 | if (WARN(with_fdi && !with_spread, "FDI requires downspread\n")) | |
8438 | with_spread = true; | |
8439 | if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE && | |
8440 | with_fdi, "LP PCH doesn't have FDI\n")) | |
8441 | with_fdi = false; | |
f31f2d55 | 8442 | |
a580516d | 8443 | mutex_lock(&dev_priv->sb_lock); |
f31f2d55 PZ |
8444 | |
8445 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
8446 | tmp &= ~SBI_SSCCTL_DISABLE; | |
8447 | tmp |= SBI_SSCCTL_PATHALT; | |
8448 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8449 | ||
8450 | udelay(24); | |
8451 | ||
2fa86a1f PZ |
8452 | if (with_spread) { |
8453 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
8454 | tmp &= ~SBI_SSCCTL_PATHALT; | |
8455 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
f31f2d55 | 8456 | |
2fa86a1f PZ |
8457 | if (with_fdi) { |
8458 | lpt_reset_fdi_mphy(dev_priv); | |
8459 | lpt_program_fdi_mphy(dev_priv); | |
8460 | } | |
8461 | } | |
dde86e2d | 8462 | |
2fa86a1f PZ |
8463 | reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ? |
8464 | SBI_GEN0 : SBI_DBUFF0; | |
8465 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); | |
8466 | tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
8467 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
c00db246 | 8468 | |
a580516d | 8469 | mutex_unlock(&dev_priv->sb_lock); |
dde86e2d PZ |
8470 | } |
8471 | ||
47701c3b PZ |
8472 | /* Sequence to disable CLKOUT_DP */ |
8473 | static void lpt_disable_clkout_dp(struct drm_device *dev) | |
8474 | { | |
8475 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8476 | uint32_t reg, tmp; | |
8477 | ||
a580516d | 8478 | mutex_lock(&dev_priv->sb_lock); |
47701c3b PZ |
8479 | |
8480 | reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ? | |
8481 | SBI_GEN0 : SBI_DBUFF0; | |
8482 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); | |
8483 | tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
8484 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
8485 | ||
8486 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
8487 | if (!(tmp & SBI_SSCCTL_DISABLE)) { | |
8488 | if (!(tmp & SBI_SSCCTL_PATHALT)) { | |
8489 | tmp |= SBI_SSCCTL_PATHALT; | |
8490 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8491 | udelay(32); | |
8492 | } | |
8493 | tmp |= SBI_SSCCTL_DISABLE; | |
8494 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8495 | } | |
8496 | ||
a580516d | 8497 | mutex_unlock(&dev_priv->sb_lock); |
47701c3b PZ |
8498 | } |
8499 | ||
bf8fa3d3 PZ |
8500 | static void lpt_init_pch_refclk(struct drm_device *dev) |
8501 | { | |
bf8fa3d3 PZ |
8502 | struct intel_encoder *encoder; |
8503 | bool has_vga = false; | |
8504 | ||
b2784e15 | 8505 | for_each_intel_encoder(dev, encoder) { |
bf8fa3d3 PZ |
8506 | switch (encoder->type) { |
8507 | case INTEL_OUTPUT_ANALOG: | |
8508 | has_vga = true; | |
8509 | break; | |
6847d71b PZ |
8510 | default: |
8511 | break; | |
bf8fa3d3 PZ |
8512 | } |
8513 | } | |
8514 | ||
47701c3b PZ |
8515 | if (has_vga) |
8516 | lpt_enable_clkout_dp(dev, true, true); | |
8517 | else | |
8518 | lpt_disable_clkout_dp(dev); | |
bf8fa3d3 PZ |
8519 | } |
8520 | ||
dde86e2d PZ |
8521 | /* |
8522 | * Initialize reference clocks when the driver loads | |
8523 | */ | |
8524 | void intel_init_pch_refclk(struct drm_device *dev) | |
8525 | { | |
8526 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
8527 | ironlake_init_pch_refclk(dev); | |
8528 | else if (HAS_PCH_LPT(dev)) | |
8529 | lpt_init_pch_refclk(dev); | |
8530 | } | |
8531 | ||
55bb9992 | 8532 | static int ironlake_get_refclk(struct intel_crtc_state *crtc_state) |
d9d444cb | 8533 | { |
55bb9992 | 8534 | struct drm_device *dev = crtc_state->base.crtc->dev; |
d9d444cb | 8535 | struct drm_i915_private *dev_priv = dev->dev_private; |
55bb9992 | 8536 | struct drm_atomic_state *state = crtc_state->base.state; |
da3ced29 | 8537 | struct drm_connector *connector; |
55bb9992 | 8538 | struct drm_connector_state *connector_state; |
d9d444cb | 8539 | struct intel_encoder *encoder; |
55bb9992 | 8540 | int num_connectors = 0, i; |
d9d444cb JB |
8541 | bool is_lvds = false; |
8542 | ||
da3ced29 | 8543 | for_each_connector_in_state(state, connector, connector_state, i) { |
55bb9992 ACO |
8544 | if (connector_state->crtc != crtc_state->base.crtc) |
8545 | continue; | |
8546 | ||
8547 | encoder = to_intel_encoder(connector_state->best_encoder); | |
8548 | ||
d9d444cb JB |
8549 | switch (encoder->type) { |
8550 | case INTEL_OUTPUT_LVDS: | |
8551 | is_lvds = true; | |
8552 | break; | |
6847d71b PZ |
8553 | default: |
8554 | break; | |
d9d444cb JB |
8555 | } |
8556 | num_connectors++; | |
8557 | } | |
8558 | ||
8559 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) { | |
e91e941b | 8560 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", |
41aa3448 | 8561 | dev_priv->vbt.lvds_ssc_freq); |
e91e941b | 8562 | return dev_priv->vbt.lvds_ssc_freq; |
d9d444cb JB |
8563 | } |
8564 | ||
8565 | return 120000; | |
8566 | } | |
8567 | ||
6ff93609 | 8568 | static void ironlake_set_pipeconf(struct drm_crtc *crtc) |
79e53945 | 8569 | { |
c8203565 | 8570 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
79e53945 JB |
8571 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8572 | int pipe = intel_crtc->pipe; | |
c8203565 PZ |
8573 | uint32_t val; |
8574 | ||
78114071 | 8575 | val = 0; |
c8203565 | 8576 | |
6e3c9717 | 8577 | switch (intel_crtc->config->pipe_bpp) { |
c8203565 | 8578 | case 18: |
dfd07d72 | 8579 | val |= PIPECONF_6BPC; |
c8203565 PZ |
8580 | break; |
8581 | case 24: | |
dfd07d72 | 8582 | val |= PIPECONF_8BPC; |
c8203565 PZ |
8583 | break; |
8584 | case 30: | |
dfd07d72 | 8585 | val |= PIPECONF_10BPC; |
c8203565 PZ |
8586 | break; |
8587 | case 36: | |
dfd07d72 | 8588 | val |= PIPECONF_12BPC; |
c8203565 PZ |
8589 | break; |
8590 | default: | |
cc769b62 PZ |
8591 | /* Case prevented by intel_choose_pipe_bpp_dither. */ |
8592 | BUG(); | |
c8203565 PZ |
8593 | } |
8594 | ||
6e3c9717 | 8595 | if (intel_crtc->config->dither) |
c8203565 PZ |
8596 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
8597 | ||
6e3c9717 | 8598 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
c8203565 PZ |
8599 | val |= PIPECONF_INTERLACED_ILK; |
8600 | else | |
8601 | val |= PIPECONF_PROGRESSIVE; | |
8602 | ||
6e3c9717 | 8603 | if (intel_crtc->config->limited_color_range) |
3685a8f3 | 8604 | val |= PIPECONF_COLOR_RANGE_SELECT; |
3685a8f3 | 8605 | |
c8203565 PZ |
8606 | I915_WRITE(PIPECONF(pipe), val); |
8607 | POSTING_READ(PIPECONF(pipe)); | |
8608 | } | |
8609 | ||
86d3efce VS |
8610 | /* |
8611 | * Set up the pipe CSC unit. | |
8612 | * | |
8613 | * Currently only full range RGB to limited range RGB conversion | |
8614 | * is supported, but eventually this should handle various | |
8615 | * RGB<->YCbCr scenarios as well. | |
8616 | */ | |
50f3b016 | 8617 | static void intel_set_pipe_csc(struct drm_crtc *crtc) |
86d3efce VS |
8618 | { |
8619 | struct drm_device *dev = crtc->dev; | |
8620 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8621 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8622 | int pipe = intel_crtc->pipe; | |
8623 | uint16_t coeff = 0x7800; /* 1.0 */ | |
8624 | ||
8625 | /* | |
8626 | * TODO: Check what kind of values actually come out of the pipe | |
8627 | * with these coeff/postoff values and adjust to get the best | |
8628 | * accuracy. Perhaps we even need to take the bpc value into | |
8629 | * consideration. | |
8630 | */ | |
8631 | ||
6e3c9717 | 8632 | if (intel_crtc->config->limited_color_range) |
86d3efce VS |
8633 | coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */ |
8634 | ||
8635 | /* | |
8636 | * GY/GU and RY/RU should be the other way around according | |
8637 | * to BSpec, but reality doesn't agree. Just set them up in | |
8638 | * a way that results in the correct picture. | |
8639 | */ | |
8640 | I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16); | |
8641 | I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0); | |
8642 | ||
8643 | I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff); | |
8644 | I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0); | |
8645 | ||
8646 | I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0); | |
8647 | I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16); | |
8648 | ||
8649 | I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0); | |
8650 | I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0); | |
8651 | I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0); | |
8652 | ||
8653 | if (INTEL_INFO(dev)->gen > 6) { | |
8654 | uint16_t postoff = 0; | |
8655 | ||
6e3c9717 | 8656 | if (intel_crtc->config->limited_color_range) |
32cf0cb0 | 8657 | postoff = (16 * (1 << 12) / 255) & 0x1fff; |
86d3efce VS |
8658 | |
8659 | I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff); | |
8660 | I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff); | |
8661 | I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff); | |
8662 | ||
8663 | I915_WRITE(PIPE_CSC_MODE(pipe), 0); | |
8664 | } else { | |
8665 | uint32_t mode = CSC_MODE_YUV_TO_RGB; | |
8666 | ||
6e3c9717 | 8667 | if (intel_crtc->config->limited_color_range) |
86d3efce VS |
8668 | mode |= CSC_BLACK_SCREEN_OFFSET; |
8669 | ||
8670 | I915_WRITE(PIPE_CSC_MODE(pipe), mode); | |
8671 | } | |
8672 | } | |
8673 | ||
6ff93609 | 8674 | static void haswell_set_pipeconf(struct drm_crtc *crtc) |
ee2b0b38 | 8675 | { |
756f85cf PZ |
8676 | struct drm_device *dev = crtc->dev; |
8677 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee2b0b38 | 8678 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
756f85cf | 8679 | enum pipe pipe = intel_crtc->pipe; |
6e3c9717 | 8680 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
ee2b0b38 PZ |
8681 | uint32_t val; |
8682 | ||
3eff4faa | 8683 | val = 0; |
ee2b0b38 | 8684 | |
6e3c9717 | 8685 | if (IS_HASWELL(dev) && intel_crtc->config->dither) |
ee2b0b38 PZ |
8686 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
8687 | ||
6e3c9717 | 8688 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
ee2b0b38 PZ |
8689 | val |= PIPECONF_INTERLACED_ILK; |
8690 | else | |
8691 | val |= PIPECONF_PROGRESSIVE; | |
8692 | ||
702e7a56 PZ |
8693 | I915_WRITE(PIPECONF(cpu_transcoder), val); |
8694 | POSTING_READ(PIPECONF(cpu_transcoder)); | |
3eff4faa DV |
8695 | |
8696 | I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT); | |
8697 | POSTING_READ(GAMMA_MODE(intel_crtc->pipe)); | |
756f85cf | 8698 | |
3cdf122c | 8699 | if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) { |
756f85cf PZ |
8700 | val = 0; |
8701 | ||
6e3c9717 | 8702 | switch (intel_crtc->config->pipe_bpp) { |
756f85cf PZ |
8703 | case 18: |
8704 | val |= PIPEMISC_DITHER_6_BPC; | |
8705 | break; | |
8706 | case 24: | |
8707 | val |= PIPEMISC_DITHER_8_BPC; | |
8708 | break; | |
8709 | case 30: | |
8710 | val |= PIPEMISC_DITHER_10_BPC; | |
8711 | break; | |
8712 | case 36: | |
8713 | val |= PIPEMISC_DITHER_12_BPC; | |
8714 | break; | |
8715 | default: | |
8716 | /* Case prevented by pipe_config_set_bpp. */ | |
8717 | BUG(); | |
8718 | } | |
8719 | ||
6e3c9717 | 8720 | if (intel_crtc->config->dither) |
756f85cf PZ |
8721 | val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; |
8722 | ||
8723 | I915_WRITE(PIPEMISC(pipe), val); | |
8724 | } | |
ee2b0b38 PZ |
8725 | } |
8726 | ||
6591c6e4 | 8727 | static bool ironlake_compute_clocks(struct drm_crtc *crtc, |
190f68c5 | 8728 | struct intel_crtc_state *crtc_state, |
6591c6e4 PZ |
8729 | intel_clock_t *clock, |
8730 | bool *has_reduced_clock, | |
8731 | intel_clock_t *reduced_clock) | |
8732 | { | |
8733 | struct drm_device *dev = crtc->dev; | |
8734 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6591c6e4 | 8735 | int refclk; |
d4906093 | 8736 | const intel_limit_t *limit; |
a16af721 | 8737 | bool ret, is_lvds = false; |
79e53945 | 8738 | |
a93e255f | 8739 | is_lvds = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS); |
79e53945 | 8740 | |
55bb9992 | 8741 | refclk = ironlake_get_refclk(crtc_state); |
79e53945 | 8742 | |
d4906093 ML |
8743 | /* |
8744 | * Returns a set of divisors for the desired target clock with the given | |
8745 | * refclk, or FALSE. The returned values represent the clock equation: | |
8746 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
8747 | */ | |
a93e255f ACO |
8748 | limit = intel_limit(crtc_state, refclk); |
8749 | ret = dev_priv->display.find_dpll(limit, crtc_state, | |
190f68c5 | 8750 | crtc_state->port_clock, |
ee9300bb | 8751 | refclk, NULL, clock); |
6591c6e4 PZ |
8752 | if (!ret) |
8753 | return false; | |
cda4b7d3 | 8754 | |
ddc9003c | 8755 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
cec2f356 SP |
8756 | /* |
8757 | * Ensure we match the reduced clock's P to the target clock. | |
8758 | * If the clocks don't match, we can't switch the display clock | |
8759 | * by using the FP0/FP1. In such case we will disable the LVDS | |
8760 | * downclock feature. | |
8761 | */ | |
ee9300bb | 8762 | *has_reduced_clock = |
a93e255f | 8763 | dev_priv->display.find_dpll(limit, crtc_state, |
ee9300bb DV |
8764 | dev_priv->lvds_downclock, |
8765 | refclk, clock, | |
8766 | reduced_clock); | |
652c393a | 8767 | } |
61e9653f | 8768 | |
6591c6e4 PZ |
8769 | return true; |
8770 | } | |
8771 | ||
d4b1931c PZ |
8772 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) |
8773 | { | |
8774 | /* | |
8775 | * Account for spread spectrum to avoid | |
8776 | * oversubscribing the link. Max center spread | |
8777 | * is 2.5%; use 5% for safety's sake. | |
8778 | */ | |
8779 | u32 bps = target_clock * bpp * 21 / 20; | |
619d4d04 | 8780 | return DIV_ROUND_UP(bps, link_bw * 8); |
d4b1931c PZ |
8781 | } |
8782 | ||
7429e9d4 | 8783 | static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor) |
6cf86a5e | 8784 | { |
7429e9d4 | 8785 | return i9xx_dpll_compute_m(dpll) < factor * dpll->n; |
f48d8f23 PZ |
8786 | } |
8787 | ||
de13a2e3 | 8788 | static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc, |
190f68c5 | 8789 | struct intel_crtc_state *crtc_state, |
7429e9d4 | 8790 | u32 *fp, |
9a7c7890 | 8791 | intel_clock_t *reduced_clock, u32 *fp2) |
79e53945 | 8792 | { |
de13a2e3 | 8793 | struct drm_crtc *crtc = &intel_crtc->base; |
79e53945 JB |
8794 | struct drm_device *dev = crtc->dev; |
8795 | struct drm_i915_private *dev_priv = dev->dev_private; | |
55bb9992 | 8796 | struct drm_atomic_state *state = crtc_state->base.state; |
da3ced29 | 8797 | struct drm_connector *connector; |
55bb9992 ACO |
8798 | struct drm_connector_state *connector_state; |
8799 | struct intel_encoder *encoder; | |
de13a2e3 | 8800 | uint32_t dpll; |
55bb9992 | 8801 | int factor, num_connectors = 0, i; |
09ede541 | 8802 | bool is_lvds = false, is_sdvo = false; |
79e53945 | 8803 | |
da3ced29 | 8804 | for_each_connector_in_state(state, connector, connector_state, i) { |
55bb9992 ACO |
8805 | if (connector_state->crtc != crtc_state->base.crtc) |
8806 | continue; | |
8807 | ||
8808 | encoder = to_intel_encoder(connector_state->best_encoder); | |
8809 | ||
8810 | switch (encoder->type) { | |
79e53945 JB |
8811 | case INTEL_OUTPUT_LVDS: |
8812 | is_lvds = true; | |
8813 | break; | |
8814 | case INTEL_OUTPUT_SDVO: | |
7d57382e | 8815 | case INTEL_OUTPUT_HDMI: |
79e53945 | 8816 | is_sdvo = true; |
79e53945 | 8817 | break; |
6847d71b PZ |
8818 | default: |
8819 | break; | |
79e53945 | 8820 | } |
43565a06 | 8821 | |
c751ce4f | 8822 | num_connectors++; |
79e53945 | 8823 | } |
79e53945 | 8824 | |
c1858123 | 8825 | /* Enable autotuning of the PLL clock (if permissible) */ |
8febb297 EA |
8826 | factor = 21; |
8827 | if (is_lvds) { | |
8828 | if ((intel_panel_use_ssc(dev_priv) && | |
e91e941b | 8829 | dev_priv->vbt.lvds_ssc_freq == 100000) || |
f0b44056 | 8830 | (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev))) |
8febb297 | 8831 | factor = 25; |
190f68c5 | 8832 | } else if (crtc_state->sdvo_tv_clock) |
8febb297 | 8833 | factor = 20; |
c1858123 | 8834 | |
190f68c5 | 8835 | if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor)) |
7d0ac5b7 | 8836 | *fp |= FP_CB_TUNE; |
2c07245f | 8837 | |
9a7c7890 DV |
8838 | if (fp2 && (reduced_clock->m < factor * reduced_clock->n)) |
8839 | *fp2 |= FP_CB_TUNE; | |
8840 | ||
5eddb70b | 8841 | dpll = 0; |
2c07245f | 8842 | |
a07d6787 EA |
8843 | if (is_lvds) |
8844 | dpll |= DPLLB_MODE_LVDS; | |
8845 | else | |
8846 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
198a037f | 8847 | |
190f68c5 | 8848 | dpll |= (crtc_state->pixel_multiplier - 1) |
ef1b460d | 8849 | << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; |
198a037f DV |
8850 | |
8851 | if (is_sdvo) | |
4a33e48d | 8852 | dpll |= DPLL_SDVO_HIGH_SPEED; |
190f68c5 | 8853 | if (crtc_state->has_dp_encoder) |
4a33e48d | 8854 | dpll |= DPLL_SDVO_HIGH_SPEED; |
79e53945 | 8855 | |
a07d6787 | 8856 | /* compute bitmask from p1 value */ |
190f68c5 | 8857 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
a07d6787 | 8858 | /* also FPA1 */ |
190f68c5 | 8859 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
a07d6787 | 8860 | |
190f68c5 | 8861 | switch (crtc_state->dpll.p2) { |
a07d6787 EA |
8862 | case 5: |
8863 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
8864 | break; | |
8865 | case 7: | |
8866 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
8867 | break; | |
8868 | case 10: | |
8869 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
8870 | break; | |
8871 | case 14: | |
8872 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
8873 | break; | |
79e53945 JB |
8874 | } |
8875 | ||
b4c09f3b | 8876 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
43565a06 | 8877 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
79e53945 JB |
8878 | else |
8879 | dpll |= PLL_REF_INPUT_DREFCLK; | |
8880 | ||
959e16d6 | 8881 | return dpll | DPLL_VCO_ENABLE; |
de13a2e3 PZ |
8882 | } |
8883 | ||
190f68c5 ACO |
8884 | static int ironlake_crtc_compute_clock(struct intel_crtc *crtc, |
8885 | struct intel_crtc_state *crtc_state) | |
de13a2e3 | 8886 | { |
c7653199 | 8887 | struct drm_device *dev = crtc->base.dev; |
de13a2e3 | 8888 | intel_clock_t clock, reduced_clock; |
cbbab5bd | 8889 | u32 dpll = 0, fp = 0, fp2 = 0; |
e2f12b07 | 8890 | bool ok, has_reduced_clock = false; |
8b47047b | 8891 | bool is_lvds = false; |
e2b78267 | 8892 | struct intel_shared_dpll *pll; |
de13a2e3 | 8893 | |
dd3cd74a ACO |
8894 | memset(&crtc_state->dpll_hw_state, 0, |
8895 | sizeof(crtc_state->dpll_hw_state)); | |
8896 | ||
409ee761 | 8897 | is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS); |
79e53945 | 8898 | |
5dc5298b PZ |
8899 | WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)), |
8900 | "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev)); | |
a07d6787 | 8901 | |
190f68c5 | 8902 | ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock, |
de13a2e3 | 8903 | &has_reduced_clock, &reduced_clock); |
190f68c5 | 8904 | if (!ok && !crtc_state->clock_set) { |
de13a2e3 PZ |
8905 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
8906 | return -EINVAL; | |
79e53945 | 8907 | } |
f47709a9 | 8908 | /* Compat-code for transition, will disappear. */ |
190f68c5 ACO |
8909 | if (!crtc_state->clock_set) { |
8910 | crtc_state->dpll.n = clock.n; | |
8911 | crtc_state->dpll.m1 = clock.m1; | |
8912 | crtc_state->dpll.m2 = clock.m2; | |
8913 | crtc_state->dpll.p1 = clock.p1; | |
8914 | crtc_state->dpll.p2 = clock.p2; | |
f47709a9 | 8915 | } |
79e53945 | 8916 | |
5dc5298b | 8917 | /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ |
190f68c5 ACO |
8918 | if (crtc_state->has_pch_encoder) { |
8919 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); | |
cbbab5bd | 8920 | if (has_reduced_clock) |
7429e9d4 | 8921 | fp2 = i9xx_dpll_compute_fp(&reduced_clock); |
cbbab5bd | 8922 | |
190f68c5 | 8923 | dpll = ironlake_compute_dpll(crtc, crtc_state, |
cbbab5bd DV |
8924 | &fp, &reduced_clock, |
8925 | has_reduced_clock ? &fp2 : NULL); | |
8926 | ||
190f68c5 ACO |
8927 | crtc_state->dpll_hw_state.dpll = dpll; |
8928 | crtc_state->dpll_hw_state.fp0 = fp; | |
66e985c0 | 8929 | if (has_reduced_clock) |
190f68c5 | 8930 | crtc_state->dpll_hw_state.fp1 = fp2; |
66e985c0 | 8931 | else |
190f68c5 | 8932 | crtc_state->dpll_hw_state.fp1 = fp; |
66e985c0 | 8933 | |
190f68c5 | 8934 | pll = intel_get_shared_dpll(crtc, crtc_state); |
ee7b9f93 | 8935 | if (pll == NULL) { |
84f44ce7 | 8936 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", |
c7653199 | 8937 | pipe_name(crtc->pipe)); |
4b645f14 JB |
8938 | return -EINVAL; |
8939 | } | |
3fb37703 | 8940 | } |
79e53945 | 8941 | |
ab585dea | 8942 | if (is_lvds && has_reduced_clock) |
c7653199 | 8943 | crtc->lowfreq_avail = true; |
bcd644e0 | 8944 | else |
c7653199 | 8945 | crtc->lowfreq_avail = false; |
e2b78267 | 8946 | |
c8f7a0db | 8947 | return 0; |
79e53945 JB |
8948 | } |
8949 | ||
eb14cb74 VS |
8950 | static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc, |
8951 | struct intel_link_m_n *m_n) | |
8952 | { | |
8953 | struct drm_device *dev = crtc->base.dev; | |
8954 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8955 | enum pipe pipe = crtc->pipe; | |
8956 | ||
8957 | m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe)); | |
8958 | m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe)); | |
8959 | m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
8960 | & ~TU_SIZE_MASK; | |
8961 | m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe)); | |
8962 | m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
8963 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
8964 | } | |
8965 | ||
8966 | static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, | |
8967 | enum transcoder transcoder, | |
b95af8be VK |
8968 | struct intel_link_m_n *m_n, |
8969 | struct intel_link_m_n *m2_n2) | |
72419203 DV |
8970 | { |
8971 | struct drm_device *dev = crtc->base.dev; | |
8972 | struct drm_i915_private *dev_priv = dev->dev_private; | |
eb14cb74 | 8973 | enum pipe pipe = crtc->pipe; |
72419203 | 8974 | |
eb14cb74 VS |
8975 | if (INTEL_INFO(dev)->gen >= 5) { |
8976 | m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder)); | |
8977 | m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder)); | |
8978 | m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder)) | |
8979 | & ~TU_SIZE_MASK; | |
8980 | m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder)); | |
8981 | m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder)) | |
8982 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
b95af8be VK |
8983 | /* Read M2_N2 registers only for gen < 8 (M2_N2 available for |
8984 | * gen < 8) and if DRRS is supported (to make sure the | |
8985 | * registers are not unnecessarily read). | |
8986 | */ | |
8987 | if (m2_n2 && INTEL_INFO(dev)->gen < 8 && | |
6e3c9717 | 8988 | crtc->config->has_drrs) { |
b95af8be VK |
8989 | m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder)); |
8990 | m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder)); | |
8991 | m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder)) | |
8992 | & ~TU_SIZE_MASK; | |
8993 | m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder)); | |
8994 | m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder)) | |
8995 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
8996 | } | |
eb14cb74 VS |
8997 | } else { |
8998 | m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe)); | |
8999 | m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe)); | |
9000 | m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe)) | |
9001 | & ~TU_SIZE_MASK; | |
9002 | m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe)); | |
9003 | m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe)) | |
9004 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
9005 | } | |
9006 | } | |
9007 | ||
9008 | void intel_dp_get_m_n(struct intel_crtc *crtc, | |
5cec258b | 9009 | struct intel_crtc_state *pipe_config) |
eb14cb74 | 9010 | { |
681a8504 | 9011 | if (pipe_config->has_pch_encoder) |
eb14cb74 VS |
9012 | intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n); |
9013 | else | |
9014 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be VK |
9015 | &pipe_config->dp_m_n, |
9016 | &pipe_config->dp_m2_n2); | |
eb14cb74 | 9017 | } |
72419203 | 9018 | |
eb14cb74 | 9019 | static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc, |
5cec258b | 9020 | struct intel_crtc_state *pipe_config) |
eb14cb74 VS |
9021 | { |
9022 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be | 9023 | &pipe_config->fdi_m_n, NULL); |
72419203 DV |
9024 | } |
9025 | ||
bd2e244f | 9026 | static void skylake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 9027 | struct intel_crtc_state *pipe_config) |
bd2e244f JB |
9028 | { |
9029 | struct drm_device *dev = crtc->base.dev; | |
9030 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a1b2278e CK |
9031 | struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state; |
9032 | uint32_t ps_ctrl = 0; | |
9033 | int id = -1; | |
9034 | int i; | |
bd2e244f | 9035 | |
a1b2278e CK |
9036 | /* find scaler attached to this pipe */ |
9037 | for (i = 0; i < crtc->num_scalers; i++) { | |
9038 | ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i)); | |
9039 | if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) { | |
9040 | id = i; | |
9041 | pipe_config->pch_pfit.enabled = true; | |
9042 | pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i)); | |
9043 | pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i)); | |
9044 | break; | |
9045 | } | |
9046 | } | |
bd2e244f | 9047 | |
a1b2278e CK |
9048 | scaler_state->scaler_id = id; |
9049 | if (id >= 0) { | |
9050 | scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX); | |
9051 | } else { | |
9052 | scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX); | |
bd2e244f JB |
9053 | } |
9054 | } | |
9055 | ||
5724dbd1 DL |
9056 | static void |
9057 | skylake_get_initial_plane_config(struct intel_crtc *crtc, | |
9058 | struct intel_initial_plane_config *plane_config) | |
bc8d7dff DL |
9059 | { |
9060 | struct drm_device *dev = crtc->base.dev; | |
9061 | struct drm_i915_private *dev_priv = dev->dev_private; | |
40f46283 | 9062 | u32 val, base, offset, stride_mult, tiling; |
bc8d7dff DL |
9063 | int pipe = crtc->pipe; |
9064 | int fourcc, pixel_format; | |
6761dd31 | 9065 | unsigned int aligned_height; |
bc8d7dff | 9066 | struct drm_framebuffer *fb; |
1b842c89 | 9067 | struct intel_framebuffer *intel_fb; |
bc8d7dff | 9068 | |
d9806c9f | 9069 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 9070 | if (!intel_fb) { |
bc8d7dff DL |
9071 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
9072 | return; | |
9073 | } | |
9074 | ||
1b842c89 DL |
9075 | fb = &intel_fb->base; |
9076 | ||
bc8d7dff | 9077 | val = I915_READ(PLANE_CTL(pipe, 0)); |
42a7b088 DL |
9078 | if (!(val & PLANE_CTL_ENABLE)) |
9079 | goto error; | |
9080 | ||
bc8d7dff DL |
9081 | pixel_format = val & PLANE_CTL_FORMAT_MASK; |
9082 | fourcc = skl_format_to_fourcc(pixel_format, | |
9083 | val & PLANE_CTL_ORDER_RGBX, | |
9084 | val & PLANE_CTL_ALPHA_MASK); | |
9085 | fb->pixel_format = fourcc; | |
9086 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
9087 | ||
40f46283 DL |
9088 | tiling = val & PLANE_CTL_TILED_MASK; |
9089 | switch (tiling) { | |
9090 | case PLANE_CTL_TILED_LINEAR: | |
9091 | fb->modifier[0] = DRM_FORMAT_MOD_NONE; | |
9092 | break; | |
9093 | case PLANE_CTL_TILED_X: | |
9094 | plane_config->tiling = I915_TILING_X; | |
9095 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; | |
9096 | break; | |
9097 | case PLANE_CTL_TILED_Y: | |
9098 | fb->modifier[0] = I915_FORMAT_MOD_Y_TILED; | |
9099 | break; | |
9100 | case PLANE_CTL_TILED_YF: | |
9101 | fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED; | |
9102 | break; | |
9103 | default: | |
9104 | MISSING_CASE(tiling); | |
9105 | goto error; | |
9106 | } | |
9107 | ||
bc8d7dff DL |
9108 | base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000; |
9109 | plane_config->base = base; | |
9110 | ||
9111 | offset = I915_READ(PLANE_OFFSET(pipe, 0)); | |
9112 | ||
9113 | val = I915_READ(PLANE_SIZE(pipe, 0)); | |
9114 | fb->height = ((val >> 16) & 0xfff) + 1; | |
9115 | fb->width = ((val >> 0) & 0x1fff) + 1; | |
9116 | ||
9117 | val = I915_READ(PLANE_STRIDE(pipe, 0)); | |
40f46283 DL |
9118 | stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0], |
9119 | fb->pixel_format); | |
bc8d7dff DL |
9120 | fb->pitches[0] = (val & 0x3ff) * stride_mult; |
9121 | ||
9122 | aligned_height = intel_fb_align_height(dev, fb->height, | |
091df6cb DV |
9123 | fb->pixel_format, |
9124 | fb->modifier[0]); | |
bc8d7dff | 9125 | |
f37b5c2b | 9126 | plane_config->size = fb->pitches[0] * aligned_height; |
bc8d7dff DL |
9127 | |
9128 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", | |
9129 | pipe_name(pipe), fb->width, fb->height, | |
9130 | fb->bits_per_pixel, base, fb->pitches[0], | |
9131 | plane_config->size); | |
9132 | ||
2d14030b | 9133 | plane_config->fb = intel_fb; |
bc8d7dff DL |
9134 | return; |
9135 | ||
9136 | error: | |
9137 | kfree(fb); | |
9138 | } | |
9139 | ||
2fa2fe9a | 9140 | static void ironlake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 9141 | struct intel_crtc_state *pipe_config) |
2fa2fe9a DV |
9142 | { |
9143 | struct drm_device *dev = crtc->base.dev; | |
9144 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9145 | uint32_t tmp; | |
9146 | ||
9147 | tmp = I915_READ(PF_CTL(crtc->pipe)); | |
9148 | ||
9149 | if (tmp & PF_ENABLE) { | |
fd4daa9c | 9150 | pipe_config->pch_pfit.enabled = true; |
2fa2fe9a DV |
9151 | pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe)); |
9152 | pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe)); | |
cb8b2a30 DV |
9153 | |
9154 | /* We currently do not free assignements of panel fitters on | |
9155 | * ivb/hsw (since we don't use the higher upscaling modes which | |
9156 | * differentiates them) so just WARN about this case for now. */ | |
9157 | if (IS_GEN7(dev)) { | |
9158 | WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) != | |
9159 | PF_PIPE_SEL_IVB(crtc->pipe)); | |
9160 | } | |
2fa2fe9a | 9161 | } |
79e53945 JB |
9162 | } |
9163 | ||
5724dbd1 DL |
9164 | static void |
9165 | ironlake_get_initial_plane_config(struct intel_crtc *crtc, | |
9166 | struct intel_initial_plane_config *plane_config) | |
4c6baa59 JB |
9167 | { |
9168 | struct drm_device *dev = crtc->base.dev; | |
9169 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9170 | u32 val, base, offset; | |
aeee5a49 | 9171 | int pipe = crtc->pipe; |
4c6baa59 | 9172 | int fourcc, pixel_format; |
6761dd31 | 9173 | unsigned int aligned_height; |
b113d5ee | 9174 | struct drm_framebuffer *fb; |
1b842c89 | 9175 | struct intel_framebuffer *intel_fb; |
4c6baa59 | 9176 | |
42a7b088 DL |
9177 | val = I915_READ(DSPCNTR(pipe)); |
9178 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
9179 | return; | |
9180 | ||
d9806c9f | 9181 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 9182 | if (!intel_fb) { |
4c6baa59 JB |
9183 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
9184 | return; | |
9185 | } | |
9186 | ||
1b842c89 DL |
9187 | fb = &intel_fb->base; |
9188 | ||
18c5247e DV |
9189 | if (INTEL_INFO(dev)->gen >= 4) { |
9190 | if (val & DISPPLANE_TILED) { | |
49af449b | 9191 | plane_config->tiling = I915_TILING_X; |
18c5247e DV |
9192 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; |
9193 | } | |
9194 | } | |
4c6baa59 JB |
9195 | |
9196 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 9197 | fourcc = i9xx_format_to_fourcc(pixel_format); |
b113d5ee DL |
9198 | fb->pixel_format = fourcc; |
9199 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
4c6baa59 | 9200 | |
aeee5a49 | 9201 | base = I915_READ(DSPSURF(pipe)) & 0xfffff000; |
4c6baa59 | 9202 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
aeee5a49 | 9203 | offset = I915_READ(DSPOFFSET(pipe)); |
4c6baa59 | 9204 | } else { |
49af449b | 9205 | if (plane_config->tiling) |
aeee5a49 | 9206 | offset = I915_READ(DSPTILEOFF(pipe)); |
4c6baa59 | 9207 | else |
aeee5a49 | 9208 | offset = I915_READ(DSPLINOFF(pipe)); |
4c6baa59 JB |
9209 | } |
9210 | plane_config->base = base; | |
9211 | ||
9212 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
9213 | fb->width = ((val >> 16) & 0xfff) + 1; |
9214 | fb->height = ((val >> 0) & 0xfff) + 1; | |
4c6baa59 JB |
9215 | |
9216 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 9217 | fb->pitches[0] = val & 0xffffffc0; |
4c6baa59 | 9218 | |
b113d5ee | 9219 | aligned_height = intel_fb_align_height(dev, fb->height, |
091df6cb DV |
9220 | fb->pixel_format, |
9221 | fb->modifier[0]); | |
4c6baa59 | 9222 | |
f37b5c2b | 9223 | plane_config->size = fb->pitches[0] * aligned_height; |
4c6baa59 | 9224 | |
2844a921 DL |
9225 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
9226 | pipe_name(pipe), fb->width, fb->height, | |
9227 | fb->bits_per_pixel, base, fb->pitches[0], | |
9228 | plane_config->size); | |
b113d5ee | 9229 | |
2d14030b | 9230 | plane_config->fb = intel_fb; |
4c6baa59 JB |
9231 | } |
9232 | ||
0e8ffe1b | 9233 | static bool ironlake_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 9234 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
9235 | { |
9236 | struct drm_device *dev = crtc->base.dev; | |
9237 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9238 | uint32_t tmp; | |
9239 | ||
f458ebbc DV |
9240 | if (!intel_display_power_is_enabled(dev_priv, |
9241 | POWER_DOMAIN_PIPE(crtc->pipe))) | |
930e8c9e PZ |
9242 | return false; |
9243 | ||
e143a21c | 9244 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 | 9245 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
eccb140b | 9246 | |
0e8ffe1b DV |
9247 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
9248 | if (!(tmp & PIPECONF_ENABLE)) | |
9249 | return false; | |
9250 | ||
42571aef VS |
9251 | switch (tmp & PIPECONF_BPC_MASK) { |
9252 | case PIPECONF_6BPC: | |
9253 | pipe_config->pipe_bpp = 18; | |
9254 | break; | |
9255 | case PIPECONF_8BPC: | |
9256 | pipe_config->pipe_bpp = 24; | |
9257 | break; | |
9258 | case PIPECONF_10BPC: | |
9259 | pipe_config->pipe_bpp = 30; | |
9260 | break; | |
9261 | case PIPECONF_12BPC: | |
9262 | pipe_config->pipe_bpp = 36; | |
9263 | break; | |
9264 | default: | |
9265 | break; | |
9266 | } | |
9267 | ||
b5a9fa09 DV |
9268 | if (tmp & PIPECONF_COLOR_RANGE_SELECT) |
9269 | pipe_config->limited_color_range = true; | |
9270 | ||
ab9412ba | 9271 | if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { |
66e985c0 DV |
9272 | struct intel_shared_dpll *pll; |
9273 | ||
88adfff1 DV |
9274 | pipe_config->has_pch_encoder = true; |
9275 | ||
627eb5a3 DV |
9276 | tmp = I915_READ(FDI_RX_CTL(crtc->pipe)); |
9277 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
9278 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
72419203 DV |
9279 | |
9280 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
6c49f241 | 9281 | |
c0d43d62 | 9282 | if (HAS_PCH_IBX(dev_priv->dev)) { |
d94ab068 DV |
9283 | pipe_config->shared_dpll = |
9284 | (enum intel_dpll_id) crtc->pipe; | |
c0d43d62 DV |
9285 | } else { |
9286 | tmp = I915_READ(PCH_DPLL_SEL); | |
9287 | if (tmp & TRANS_DPLLB_SEL(crtc->pipe)) | |
9288 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B; | |
9289 | else | |
9290 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A; | |
9291 | } | |
66e985c0 DV |
9292 | |
9293 | pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; | |
9294 | ||
9295 | WARN_ON(!pll->get_hw_state(dev_priv, pll, | |
9296 | &pipe_config->dpll_hw_state)); | |
c93f54cf DV |
9297 | |
9298 | tmp = pipe_config->dpll_hw_state.dpll; | |
9299 | pipe_config->pixel_multiplier = | |
9300 | ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK) | |
9301 | >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1; | |
18442d08 VS |
9302 | |
9303 | ironlake_pch_clock_get(crtc, pipe_config); | |
6c49f241 DV |
9304 | } else { |
9305 | pipe_config->pixel_multiplier = 1; | |
627eb5a3 DV |
9306 | } |
9307 | ||
1bd1bd80 DV |
9308 | intel_get_pipe_timings(crtc, pipe_config); |
9309 | ||
2fa2fe9a DV |
9310 | ironlake_get_pfit_config(crtc, pipe_config); |
9311 | ||
0e8ffe1b DV |
9312 | return true; |
9313 | } | |
9314 | ||
be256dc7 PZ |
9315 | static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) |
9316 | { | |
9317 | struct drm_device *dev = dev_priv->dev; | |
be256dc7 | 9318 | struct intel_crtc *crtc; |
be256dc7 | 9319 | |
d3fcc808 | 9320 | for_each_intel_crtc(dev, crtc) |
e2c719b7 | 9321 | I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n", |
be256dc7 PZ |
9322 | pipe_name(crtc->pipe)); |
9323 | ||
e2c719b7 RC |
9324 | I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n"); |
9325 | I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n"); | |
9326 | I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n"); | |
9327 | I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n"); | |
9328 | I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n"); | |
9329 | I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, | |
be256dc7 | 9330 | "CPU PWM1 enabled\n"); |
c5107b87 | 9331 | if (IS_HASWELL(dev)) |
e2c719b7 | 9332 | I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, |
c5107b87 | 9333 | "CPU PWM2 enabled\n"); |
e2c719b7 | 9334 | I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, |
be256dc7 | 9335 | "PCH PWM1 enabled\n"); |
e2c719b7 | 9336 | I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, |
be256dc7 | 9337 | "Utility pin enabled\n"); |
e2c719b7 | 9338 | I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n"); |
be256dc7 | 9339 | |
9926ada1 PZ |
9340 | /* |
9341 | * In theory we can still leave IRQs enabled, as long as only the HPD | |
9342 | * interrupts remain enabled. We used to check for that, but since it's | |
9343 | * gen-specific and since we only disable LCPLL after we fully disable | |
9344 | * the interrupts, the check below should be enough. | |
9345 | */ | |
e2c719b7 | 9346 | I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n"); |
be256dc7 PZ |
9347 | } |
9348 | ||
9ccd5aeb PZ |
9349 | static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv) |
9350 | { | |
9351 | struct drm_device *dev = dev_priv->dev; | |
9352 | ||
9353 | if (IS_HASWELL(dev)) | |
9354 | return I915_READ(D_COMP_HSW); | |
9355 | else | |
9356 | return I915_READ(D_COMP_BDW); | |
9357 | } | |
9358 | ||
3c4c9b81 PZ |
9359 | static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val) |
9360 | { | |
9361 | struct drm_device *dev = dev_priv->dev; | |
9362 | ||
9363 | if (IS_HASWELL(dev)) { | |
9364 | mutex_lock(&dev_priv->rps.hw_lock); | |
9365 | if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, | |
9366 | val)) | |
f475dadf | 9367 | DRM_ERROR("Failed to write to D_COMP\n"); |
3c4c9b81 PZ |
9368 | mutex_unlock(&dev_priv->rps.hw_lock); |
9369 | } else { | |
9ccd5aeb PZ |
9370 | I915_WRITE(D_COMP_BDW, val); |
9371 | POSTING_READ(D_COMP_BDW); | |
3c4c9b81 | 9372 | } |
be256dc7 PZ |
9373 | } |
9374 | ||
9375 | /* | |
9376 | * This function implements pieces of two sequences from BSpec: | |
9377 | * - Sequence for display software to disable LCPLL | |
9378 | * - Sequence for display software to allow package C8+ | |
9379 | * The steps implemented here are just the steps that actually touch the LCPLL | |
9380 | * register. Callers should take care of disabling all the display engine | |
9381 | * functions, doing the mode unset, fixing interrupts, etc. | |
9382 | */ | |
6ff58d53 PZ |
9383 | static void hsw_disable_lcpll(struct drm_i915_private *dev_priv, |
9384 | bool switch_to_fclk, bool allow_power_down) | |
be256dc7 PZ |
9385 | { |
9386 | uint32_t val; | |
9387 | ||
9388 | assert_can_disable_lcpll(dev_priv); | |
9389 | ||
9390 | val = I915_READ(LCPLL_CTL); | |
9391 | ||
9392 | if (switch_to_fclk) { | |
9393 | val |= LCPLL_CD_SOURCE_FCLK; | |
9394 | I915_WRITE(LCPLL_CTL, val); | |
9395 | ||
9396 | if (wait_for_atomic_us(I915_READ(LCPLL_CTL) & | |
9397 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
9398 | DRM_ERROR("Switching to FCLK failed\n"); | |
9399 | ||
9400 | val = I915_READ(LCPLL_CTL); | |
9401 | } | |
9402 | ||
9403 | val |= LCPLL_PLL_DISABLE; | |
9404 | I915_WRITE(LCPLL_CTL, val); | |
9405 | POSTING_READ(LCPLL_CTL); | |
9406 | ||
9407 | if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1)) | |
9408 | DRM_ERROR("LCPLL still locked\n"); | |
9409 | ||
9ccd5aeb | 9410 | val = hsw_read_dcomp(dev_priv); |
be256dc7 | 9411 | val |= D_COMP_COMP_DISABLE; |
3c4c9b81 | 9412 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
9413 | ndelay(100); |
9414 | ||
9ccd5aeb PZ |
9415 | if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0, |
9416 | 1)) | |
be256dc7 PZ |
9417 | DRM_ERROR("D_COMP RCOMP still in progress\n"); |
9418 | ||
9419 | if (allow_power_down) { | |
9420 | val = I915_READ(LCPLL_CTL); | |
9421 | val |= LCPLL_POWER_DOWN_ALLOW; | |
9422 | I915_WRITE(LCPLL_CTL, val); | |
9423 | POSTING_READ(LCPLL_CTL); | |
9424 | } | |
9425 | } | |
9426 | ||
9427 | /* | |
9428 | * Fully restores LCPLL, disallowing power down and switching back to LCPLL | |
9429 | * source. | |
9430 | */ | |
6ff58d53 | 9431 | static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) |
be256dc7 PZ |
9432 | { |
9433 | uint32_t val; | |
9434 | ||
9435 | val = I915_READ(LCPLL_CTL); | |
9436 | ||
9437 | if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK | | |
9438 | LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK) | |
9439 | return; | |
9440 | ||
a8a8bd54 PZ |
9441 | /* |
9442 | * Make sure we're not on PC8 state before disabling PC8, otherwise | |
9443 | * we'll hang the machine. To prevent PC8 state, just enable force_wake. | |
a8a8bd54 | 9444 | */ |
59bad947 | 9445 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
215733fa | 9446 | |
be256dc7 PZ |
9447 | if (val & LCPLL_POWER_DOWN_ALLOW) { |
9448 | val &= ~LCPLL_POWER_DOWN_ALLOW; | |
9449 | I915_WRITE(LCPLL_CTL, val); | |
35d8f2eb | 9450 | POSTING_READ(LCPLL_CTL); |
be256dc7 PZ |
9451 | } |
9452 | ||
9ccd5aeb | 9453 | val = hsw_read_dcomp(dev_priv); |
be256dc7 PZ |
9454 | val |= D_COMP_COMP_FORCE; |
9455 | val &= ~D_COMP_COMP_DISABLE; | |
3c4c9b81 | 9456 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
9457 | |
9458 | val = I915_READ(LCPLL_CTL); | |
9459 | val &= ~LCPLL_PLL_DISABLE; | |
9460 | I915_WRITE(LCPLL_CTL, val); | |
9461 | ||
9462 | if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5)) | |
9463 | DRM_ERROR("LCPLL not locked yet\n"); | |
9464 | ||
9465 | if (val & LCPLL_CD_SOURCE_FCLK) { | |
9466 | val = I915_READ(LCPLL_CTL); | |
9467 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
9468 | I915_WRITE(LCPLL_CTL, val); | |
9469 | ||
9470 | if (wait_for_atomic_us((I915_READ(LCPLL_CTL) & | |
9471 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
9472 | DRM_ERROR("Switching back to LCPLL failed\n"); | |
9473 | } | |
215733fa | 9474 | |
59bad947 | 9475 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
b6283055 | 9476 | intel_update_cdclk(dev_priv->dev); |
be256dc7 PZ |
9477 | } |
9478 | ||
765dab67 PZ |
9479 | /* |
9480 | * Package states C8 and deeper are really deep PC states that can only be | |
9481 | * reached when all the devices on the system allow it, so even if the graphics | |
9482 | * device allows PC8+, it doesn't mean the system will actually get to these | |
9483 | * states. Our driver only allows PC8+ when going into runtime PM. | |
9484 | * | |
9485 | * The requirements for PC8+ are that all the outputs are disabled, the power | |
9486 | * well is disabled and most interrupts are disabled, and these are also | |
9487 | * requirements for runtime PM. When these conditions are met, we manually do | |
9488 | * the other conditions: disable the interrupts, clocks and switch LCPLL refclk | |
9489 | * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard | |
9490 | * hang the machine. | |
9491 | * | |
9492 | * When we really reach PC8 or deeper states (not just when we allow it) we lose | |
9493 | * the state of some registers, so when we come back from PC8+ we need to | |
9494 | * restore this state. We don't get into PC8+ if we're not in RC6, so we don't | |
9495 | * need to take care of the registers kept by RC6. Notice that this happens even | |
9496 | * if we don't put the device in PCI D3 state (which is what currently happens | |
9497 | * because of the runtime PM support). | |
9498 | * | |
9499 | * For more, read "Display Sequences for Package C8" on the hardware | |
9500 | * documentation. | |
9501 | */ | |
a14cb6fc | 9502 | void hsw_enable_pc8(struct drm_i915_private *dev_priv) |
c67a470b | 9503 | { |
c67a470b PZ |
9504 | struct drm_device *dev = dev_priv->dev; |
9505 | uint32_t val; | |
9506 | ||
c67a470b PZ |
9507 | DRM_DEBUG_KMS("Enabling package C8+\n"); |
9508 | ||
c67a470b PZ |
9509 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { |
9510 | val = I915_READ(SOUTH_DSPCLK_GATE_D); | |
9511 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; | |
9512 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
9513 | } | |
9514 | ||
9515 | lpt_disable_clkout_dp(dev); | |
c67a470b PZ |
9516 | hsw_disable_lcpll(dev_priv, true, true); |
9517 | } | |
9518 | ||
a14cb6fc | 9519 | void hsw_disable_pc8(struct drm_i915_private *dev_priv) |
c67a470b PZ |
9520 | { |
9521 | struct drm_device *dev = dev_priv->dev; | |
9522 | uint32_t val; | |
9523 | ||
c67a470b PZ |
9524 | DRM_DEBUG_KMS("Disabling package C8+\n"); |
9525 | ||
9526 | hsw_restore_lcpll(dev_priv); | |
c67a470b PZ |
9527 | lpt_init_pch_refclk(dev); |
9528 | ||
9529 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { | |
9530 | val = I915_READ(SOUTH_DSPCLK_GATE_D); | |
9531 | val |= PCH_LP_PARTITION_LEVEL_DISABLE; | |
9532 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
9533 | } | |
9534 | ||
9535 | intel_prepare_ddi(dev); | |
c67a470b PZ |
9536 | } |
9537 | ||
a821fc46 | 9538 | static void broxton_modeset_global_resources(struct drm_atomic_state *old_state) |
f8437dd1 | 9539 | { |
a821fc46 | 9540 | struct drm_device *dev = old_state->dev; |
f8437dd1 | 9541 | struct drm_i915_private *dev_priv = dev->dev_private; |
a821fc46 | 9542 | int max_pixclk = intel_mode_max_pixclk(dev, NULL); |
f8437dd1 VK |
9543 | int req_cdclk; |
9544 | ||
9545 | /* see the comment in valleyview_modeset_global_resources */ | |
9546 | if (WARN_ON(max_pixclk < 0)) | |
9547 | return; | |
9548 | ||
9549 | req_cdclk = broxton_calc_cdclk(dev_priv, max_pixclk); | |
9550 | ||
9551 | if (req_cdclk != dev_priv->cdclk_freq) | |
9552 | broxton_set_cdclk(dev, req_cdclk); | |
9553 | } | |
9554 | ||
b432e5cf VS |
9555 | /* compute the max rate for new configuration */ |
9556 | static int ilk_max_pixel_rate(struct drm_i915_private *dev_priv) | |
9557 | { | |
9558 | struct drm_device *dev = dev_priv->dev; | |
9559 | struct intel_crtc *intel_crtc; | |
9560 | struct drm_crtc *crtc; | |
9561 | int max_pixel_rate = 0; | |
9562 | int pixel_rate; | |
9563 | ||
9564 | for_each_crtc(dev, crtc) { | |
9565 | if (!crtc->state->enable) | |
9566 | continue; | |
9567 | ||
9568 | intel_crtc = to_intel_crtc(crtc); | |
9569 | pixel_rate = ilk_pipe_pixel_rate(intel_crtc->config); | |
9570 | ||
9571 | /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ | |
9572 | if (IS_BROADWELL(dev) && intel_crtc->config->ips_enabled) | |
9573 | pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95); | |
9574 | ||
9575 | max_pixel_rate = max(max_pixel_rate, pixel_rate); | |
9576 | } | |
9577 | ||
9578 | return max_pixel_rate; | |
9579 | } | |
9580 | ||
9581 | static void broadwell_set_cdclk(struct drm_device *dev, int cdclk) | |
9582 | { | |
9583 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9584 | uint32_t val, data; | |
9585 | int ret; | |
9586 | ||
9587 | if (WARN((I915_READ(LCPLL_CTL) & | |
9588 | (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK | | |
9589 | LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE | | |
9590 | LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW | | |
9591 | LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK, | |
9592 | "trying to change cdclk frequency with cdclk not enabled\n")) | |
9593 | return; | |
9594 | ||
9595 | mutex_lock(&dev_priv->rps.hw_lock); | |
9596 | ret = sandybridge_pcode_write(dev_priv, | |
9597 | BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0); | |
9598 | mutex_unlock(&dev_priv->rps.hw_lock); | |
9599 | if (ret) { | |
9600 | DRM_ERROR("failed to inform pcode about cdclk change\n"); | |
9601 | return; | |
9602 | } | |
9603 | ||
9604 | val = I915_READ(LCPLL_CTL); | |
9605 | val |= LCPLL_CD_SOURCE_FCLK; | |
9606 | I915_WRITE(LCPLL_CTL, val); | |
9607 | ||
9608 | if (wait_for_atomic_us(I915_READ(LCPLL_CTL) & | |
9609 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
9610 | DRM_ERROR("Switching to FCLK failed\n"); | |
9611 | ||
9612 | val = I915_READ(LCPLL_CTL); | |
9613 | val &= ~LCPLL_CLK_FREQ_MASK; | |
9614 | ||
9615 | switch (cdclk) { | |
9616 | case 450000: | |
9617 | val |= LCPLL_CLK_FREQ_450; | |
9618 | data = 0; | |
9619 | break; | |
9620 | case 540000: | |
9621 | val |= LCPLL_CLK_FREQ_54O_BDW; | |
9622 | data = 1; | |
9623 | break; | |
9624 | case 337500: | |
9625 | val |= LCPLL_CLK_FREQ_337_5_BDW; | |
9626 | data = 2; | |
9627 | break; | |
9628 | case 675000: | |
9629 | val |= LCPLL_CLK_FREQ_675_BDW; | |
9630 | data = 3; | |
9631 | break; | |
9632 | default: | |
9633 | WARN(1, "invalid cdclk frequency\n"); | |
9634 | return; | |
9635 | } | |
9636 | ||
9637 | I915_WRITE(LCPLL_CTL, val); | |
9638 | ||
9639 | val = I915_READ(LCPLL_CTL); | |
9640 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
9641 | I915_WRITE(LCPLL_CTL, val); | |
9642 | ||
9643 | if (wait_for_atomic_us((I915_READ(LCPLL_CTL) & | |
9644 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
9645 | DRM_ERROR("Switching back to LCPLL failed\n"); | |
9646 | ||
9647 | mutex_lock(&dev_priv->rps.hw_lock); | |
9648 | sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data); | |
9649 | mutex_unlock(&dev_priv->rps.hw_lock); | |
9650 | ||
9651 | intel_update_cdclk(dev); | |
9652 | ||
9653 | WARN(cdclk != dev_priv->cdclk_freq, | |
9654 | "cdclk requested %d kHz but got %d kHz\n", | |
9655 | cdclk, dev_priv->cdclk_freq); | |
9656 | } | |
9657 | ||
9658 | static int broadwell_calc_cdclk(struct drm_i915_private *dev_priv, | |
9659 | int max_pixel_rate) | |
9660 | { | |
9661 | int cdclk; | |
9662 | ||
9663 | /* | |
9664 | * FIXME should also account for plane ratio | |
9665 | * once 64bpp pixel formats are supported. | |
9666 | */ | |
9667 | if (max_pixel_rate > 540000) | |
9668 | cdclk = 675000; | |
9669 | else if (max_pixel_rate > 450000) | |
9670 | cdclk = 540000; | |
9671 | else if (max_pixel_rate > 337500) | |
9672 | cdclk = 450000; | |
9673 | else | |
9674 | cdclk = 337500; | |
9675 | ||
9676 | /* | |
9677 | * FIXME move the cdclk caclulation to | |
9678 | * compute_config() so we can fail gracegully. | |
9679 | */ | |
9680 | if (cdclk > dev_priv->max_cdclk_freq) { | |
9681 | DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n", | |
9682 | cdclk, dev_priv->max_cdclk_freq); | |
9683 | cdclk = dev_priv->max_cdclk_freq; | |
9684 | } | |
9685 | ||
9686 | return cdclk; | |
9687 | } | |
9688 | ||
9689 | static int broadwell_modeset_global_pipes(struct drm_atomic_state *state) | |
9690 | { | |
9691 | struct drm_i915_private *dev_priv = to_i915(state->dev); | |
9692 | struct drm_crtc *crtc; | |
9693 | struct drm_crtc_state *crtc_state; | |
9694 | int max_pixclk = ilk_max_pixel_rate(dev_priv); | |
9695 | int cdclk, i; | |
9696 | ||
9697 | cdclk = broadwell_calc_cdclk(dev_priv, max_pixclk); | |
9698 | ||
9699 | if (cdclk == dev_priv->cdclk_freq) | |
9700 | return 0; | |
9701 | ||
9702 | /* add all active pipes to the state */ | |
9703 | for_each_crtc(state->dev, crtc) { | |
9704 | if (!crtc->state->enable) | |
9705 | continue; | |
9706 | ||
9707 | crtc_state = drm_atomic_get_crtc_state(state, crtc); | |
9708 | if (IS_ERR(crtc_state)) | |
9709 | return PTR_ERR(crtc_state); | |
9710 | } | |
9711 | ||
9712 | /* disable/enable all currently active pipes while we change cdclk */ | |
9713 | for_each_crtc_in_state(state, crtc, crtc_state, i) | |
9714 | if (crtc_state->enable) | |
9715 | crtc_state->mode_changed = true; | |
9716 | ||
9717 | return 0; | |
9718 | } | |
9719 | ||
9720 | static void broadwell_modeset_global_resources(struct drm_atomic_state *state) | |
9721 | { | |
9722 | struct drm_device *dev = state->dev; | |
9723 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9724 | int max_pixel_rate = ilk_max_pixel_rate(dev_priv); | |
9725 | int req_cdclk = broadwell_calc_cdclk(dev_priv, max_pixel_rate); | |
9726 | ||
9727 | if (req_cdclk != dev_priv->cdclk_freq) | |
9728 | broadwell_set_cdclk(dev, req_cdclk); | |
9729 | } | |
9730 | ||
190f68c5 ACO |
9731 | static int haswell_crtc_compute_clock(struct intel_crtc *crtc, |
9732 | struct intel_crtc_state *crtc_state) | |
09b4ddf9 | 9733 | { |
190f68c5 | 9734 | if (!intel_ddi_pll_select(crtc, crtc_state)) |
6441ab5f | 9735 | return -EINVAL; |
716c2e55 | 9736 | |
c7653199 | 9737 | crtc->lowfreq_avail = false; |
644cef34 | 9738 | |
c8f7a0db | 9739 | return 0; |
79e53945 JB |
9740 | } |
9741 | ||
3760b59c S |
9742 | static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv, |
9743 | enum port port, | |
9744 | struct intel_crtc_state *pipe_config) | |
9745 | { | |
9746 | switch (port) { | |
9747 | case PORT_A: | |
9748 | pipe_config->ddi_pll_sel = SKL_DPLL0; | |
9749 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1; | |
9750 | break; | |
9751 | case PORT_B: | |
9752 | pipe_config->ddi_pll_sel = SKL_DPLL1; | |
9753 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2; | |
9754 | break; | |
9755 | case PORT_C: | |
9756 | pipe_config->ddi_pll_sel = SKL_DPLL2; | |
9757 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3; | |
9758 | break; | |
9759 | default: | |
9760 | DRM_ERROR("Incorrect port type\n"); | |
9761 | } | |
9762 | } | |
9763 | ||
96b7dfb7 S |
9764 | static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv, |
9765 | enum port port, | |
5cec258b | 9766 | struct intel_crtc_state *pipe_config) |
96b7dfb7 | 9767 | { |
3148ade7 | 9768 | u32 temp, dpll_ctl1; |
96b7dfb7 S |
9769 | |
9770 | temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port); | |
9771 | pipe_config->ddi_pll_sel = temp >> (port * 3 + 1); | |
9772 | ||
9773 | switch (pipe_config->ddi_pll_sel) { | |
3148ade7 DL |
9774 | case SKL_DPLL0: |
9775 | /* | |
9776 | * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part | |
9777 | * of the shared DPLL framework and thus needs to be read out | |
9778 | * separately | |
9779 | */ | |
9780 | dpll_ctl1 = I915_READ(DPLL_CTRL1); | |
9781 | pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f; | |
9782 | break; | |
96b7dfb7 S |
9783 | case SKL_DPLL1: |
9784 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1; | |
9785 | break; | |
9786 | case SKL_DPLL2: | |
9787 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2; | |
9788 | break; | |
9789 | case SKL_DPLL3: | |
9790 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3; | |
9791 | break; | |
96b7dfb7 S |
9792 | } |
9793 | } | |
9794 | ||
7d2c8175 DL |
9795 | static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv, |
9796 | enum port port, | |
5cec258b | 9797 | struct intel_crtc_state *pipe_config) |
7d2c8175 DL |
9798 | { |
9799 | pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port)); | |
9800 | ||
9801 | switch (pipe_config->ddi_pll_sel) { | |
9802 | case PORT_CLK_SEL_WRPLL1: | |
9803 | pipe_config->shared_dpll = DPLL_ID_WRPLL1; | |
9804 | break; | |
9805 | case PORT_CLK_SEL_WRPLL2: | |
9806 | pipe_config->shared_dpll = DPLL_ID_WRPLL2; | |
9807 | break; | |
9808 | } | |
9809 | } | |
9810 | ||
26804afd | 9811 | static void haswell_get_ddi_port_state(struct intel_crtc *crtc, |
5cec258b | 9812 | struct intel_crtc_state *pipe_config) |
26804afd DV |
9813 | { |
9814 | struct drm_device *dev = crtc->base.dev; | |
9815 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d452c5b6 | 9816 | struct intel_shared_dpll *pll; |
26804afd DV |
9817 | enum port port; |
9818 | uint32_t tmp; | |
9819 | ||
9820 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); | |
9821 | ||
9822 | port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT; | |
9823 | ||
96b7dfb7 S |
9824 | if (IS_SKYLAKE(dev)) |
9825 | skylake_get_ddi_pll(dev_priv, port, pipe_config); | |
3760b59c S |
9826 | else if (IS_BROXTON(dev)) |
9827 | bxt_get_ddi_pll(dev_priv, port, pipe_config); | |
96b7dfb7 S |
9828 | else |
9829 | haswell_get_ddi_pll(dev_priv, port, pipe_config); | |
9cd86933 | 9830 | |
d452c5b6 DV |
9831 | if (pipe_config->shared_dpll >= 0) { |
9832 | pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; | |
9833 | ||
9834 | WARN_ON(!pll->get_hw_state(dev_priv, pll, | |
9835 | &pipe_config->dpll_hw_state)); | |
9836 | } | |
9837 | ||
26804afd DV |
9838 | /* |
9839 | * Haswell has only FDI/PCH transcoder A. It is which is connected to | |
9840 | * DDI E. So just check whether this pipe is wired to DDI E and whether | |
9841 | * the PCH transcoder is on. | |
9842 | */ | |
ca370455 DL |
9843 | if (INTEL_INFO(dev)->gen < 9 && |
9844 | (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) { | |
26804afd DV |
9845 | pipe_config->has_pch_encoder = true; |
9846 | ||
9847 | tmp = I915_READ(FDI_RX_CTL(PIPE_A)); | |
9848 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
9849 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
9850 | ||
9851 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
9852 | } | |
9853 | } | |
9854 | ||
0e8ffe1b | 9855 | static bool haswell_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 9856 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
9857 | { |
9858 | struct drm_device *dev = crtc->base.dev; | |
9859 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2fa2fe9a | 9860 | enum intel_display_power_domain pfit_domain; |
0e8ffe1b DV |
9861 | uint32_t tmp; |
9862 | ||
f458ebbc | 9863 | if (!intel_display_power_is_enabled(dev_priv, |
b5482bd0 ID |
9864 | POWER_DOMAIN_PIPE(crtc->pipe))) |
9865 | return false; | |
9866 | ||
e143a21c | 9867 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 DV |
9868 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
9869 | ||
eccb140b DV |
9870 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); |
9871 | if (tmp & TRANS_DDI_FUNC_ENABLE) { | |
9872 | enum pipe trans_edp_pipe; | |
9873 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { | |
9874 | default: | |
9875 | WARN(1, "unknown pipe linked to edp transcoder\n"); | |
9876 | case TRANS_DDI_EDP_INPUT_A_ONOFF: | |
9877 | case TRANS_DDI_EDP_INPUT_A_ON: | |
9878 | trans_edp_pipe = PIPE_A; | |
9879 | break; | |
9880 | case TRANS_DDI_EDP_INPUT_B_ONOFF: | |
9881 | trans_edp_pipe = PIPE_B; | |
9882 | break; | |
9883 | case TRANS_DDI_EDP_INPUT_C_ONOFF: | |
9884 | trans_edp_pipe = PIPE_C; | |
9885 | break; | |
9886 | } | |
9887 | ||
9888 | if (trans_edp_pipe == crtc->pipe) | |
9889 | pipe_config->cpu_transcoder = TRANSCODER_EDP; | |
9890 | } | |
9891 | ||
f458ebbc | 9892 | if (!intel_display_power_is_enabled(dev_priv, |
eccb140b | 9893 | POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder))) |
2bfce950 PZ |
9894 | return false; |
9895 | ||
eccb140b | 9896 | tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder)); |
0e8ffe1b DV |
9897 | if (!(tmp & PIPECONF_ENABLE)) |
9898 | return false; | |
9899 | ||
26804afd | 9900 | haswell_get_ddi_port_state(crtc, pipe_config); |
627eb5a3 | 9901 | |
1bd1bd80 DV |
9902 | intel_get_pipe_timings(crtc, pipe_config); |
9903 | ||
a1b2278e CK |
9904 | if (INTEL_INFO(dev)->gen >= 9) { |
9905 | skl_init_scalers(dev, crtc, pipe_config); | |
9906 | } | |
9907 | ||
2fa2fe9a | 9908 | pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); |
af99ceda CK |
9909 | |
9910 | if (INTEL_INFO(dev)->gen >= 9) { | |
9911 | pipe_config->scaler_state.scaler_id = -1; | |
9912 | pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX); | |
9913 | } | |
9914 | ||
bd2e244f | 9915 | if (intel_display_power_is_enabled(dev_priv, pfit_domain)) { |
ff6d9f55 | 9916 | if (INTEL_INFO(dev)->gen == 9) |
bd2e244f | 9917 | skylake_get_pfit_config(crtc, pipe_config); |
ff6d9f55 | 9918 | else if (INTEL_INFO(dev)->gen < 9) |
bd2e244f | 9919 | ironlake_get_pfit_config(crtc, pipe_config); |
ff6d9f55 JB |
9920 | else |
9921 | MISSING_CASE(INTEL_INFO(dev)->gen); | |
bd2e244f | 9922 | } |
88adfff1 | 9923 | |
e59150dc JB |
9924 | if (IS_HASWELL(dev)) |
9925 | pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) && | |
9926 | (I915_READ(IPS_CTL) & IPS_ENABLE); | |
42db64ef | 9927 | |
ebb69c95 CT |
9928 | if (pipe_config->cpu_transcoder != TRANSCODER_EDP) { |
9929 | pipe_config->pixel_multiplier = | |
9930 | I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1; | |
9931 | } else { | |
9932 | pipe_config->pixel_multiplier = 1; | |
9933 | } | |
6c49f241 | 9934 | |
0e8ffe1b DV |
9935 | return true; |
9936 | } | |
9937 | ||
560b85bb CW |
9938 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base) |
9939 | { | |
9940 | struct drm_device *dev = crtc->dev; | |
9941 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9942 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
dc41c154 | 9943 | uint32_t cntl = 0, size = 0; |
560b85bb | 9944 | |
dc41c154 | 9945 | if (base) { |
3dd512fb MR |
9946 | unsigned int width = intel_crtc->base.cursor->state->crtc_w; |
9947 | unsigned int height = intel_crtc->base.cursor->state->crtc_h; | |
dc41c154 VS |
9948 | unsigned int stride = roundup_pow_of_two(width) * 4; |
9949 | ||
9950 | switch (stride) { | |
9951 | default: | |
9952 | WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n", | |
9953 | width, stride); | |
9954 | stride = 256; | |
9955 | /* fallthrough */ | |
9956 | case 256: | |
9957 | case 512: | |
9958 | case 1024: | |
9959 | case 2048: | |
9960 | break; | |
4b0e333e CW |
9961 | } |
9962 | ||
dc41c154 VS |
9963 | cntl |= CURSOR_ENABLE | |
9964 | CURSOR_GAMMA_ENABLE | | |
9965 | CURSOR_FORMAT_ARGB | | |
9966 | CURSOR_STRIDE(stride); | |
9967 | ||
9968 | size = (height << 12) | width; | |
4b0e333e | 9969 | } |
560b85bb | 9970 | |
dc41c154 VS |
9971 | if (intel_crtc->cursor_cntl != 0 && |
9972 | (intel_crtc->cursor_base != base || | |
9973 | intel_crtc->cursor_size != size || | |
9974 | intel_crtc->cursor_cntl != cntl)) { | |
9975 | /* On these chipsets we can only modify the base/size/stride | |
9976 | * whilst the cursor is disabled. | |
9977 | */ | |
9978 | I915_WRITE(_CURACNTR, 0); | |
4b0e333e | 9979 | POSTING_READ(_CURACNTR); |
dc41c154 | 9980 | intel_crtc->cursor_cntl = 0; |
4b0e333e | 9981 | } |
560b85bb | 9982 | |
99d1f387 | 9983 | if (intel_crtc->cursor_base != base) { |
9db4a9c7 | 9984 | I915_WRITE(_CURABASE, base); |
99d1f387 VS |
9985 | intel_crtc->cursor_base = base; |
9986 | } | |
4726e0b0 | 9987 | |
dc41c154 VS |
9988 | if (intel_crtc->cursor_size != size) { |
9989 | I915_WRITE(CURSIZE, size); | |
9990 | intel_crtc->cursor_size = size; | |
4b0e333e | 9991 | } |
560b85bb | 9992 | |
4b0e333e | 9993 | if (intel_crtc->cursor_cntl != cntl) { |
4b0e333e CW |
9994 | I915_WRITE(_CURACNTR, cntl); |
9995 | POSTING_READ(_CURACNTR); | |
4b0e333e | 9996 | intel_crtc->cursor_cntl = cntl; |
560b85bb | 9997 | } |
560b85bb CW |
9998 | } |
9999 | ||
560b85bb | 10000 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base) |
65a21cd6 JB |
10001 | { |
10002 | struct drm_device *dev = crtc->dev; | |
10003 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10004 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
10005 | int pipe = intel_crtc->pipe; | |
4b0e333e CW |
10006 | uint32_t cntl; |
10007 | ||
10008 | cntl = 0; | |
10009 | if (base) { | |
10010 | cntl = MCURSOR_GAMMA_ENABLE; | |
3dd512fb | 10011 | switch (intel_crtc->base.cursor->state->crtc_w) { |
4726e0b0 SK |
10012 | case 64: |
10013 | cntl |= CURSOR_MODE_64_ARGB_AX; | |
10014 | break; | |
10015 | case 128: | |
10016 | cntl |= CURSOR_MODE_128_ARGB_AX; | |
10017 | break; | |
10018 | case 256: | |
10019 | cntl |= CURSOR_MODE_256_ARGB_AX; | |
10020 | break; | |
10021 | default: | |
3dd512fb | 10022 | MISSING_CASE(intel_crtc->base.cursor->state->crtc_w); |
4726e0b0 | 10023 | return; |
65a21cd6 | 10024 | } |
4b0e333e | 10025 | cntl |= pipe << 28; /* Connect to correct pipe */ |
47bf17a7 VS |
10026 | |
10027 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
10028 | cntl |= CURSOR_PIPE_CSC_ENABLE; | |
4b0e333e | 10029 | } |
65a21cd6 | 10030 | |
8e7d688b | 10031 | if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) |
4398ad45 VS |
10032 | cntl |= CURSOR_ROTATE_180; |
10033 | ||
4b0e333e CW |
10034 | if (intel_crtc->cursor_cntl != cntl) { |
10035 | I915_WRITE(CURCNTR(pipe), cntl); | |
10036 | POSTING_READ(CURCNTR(pipe)); | |
10037 | intel_crtc->cursor_cntl = cntl; | |
65a21cd6 | 10038 | } |
4b0e333e | 10039 | |
65a21cd6 | 10040 | /* and commit changes on next vblank */ |
5efb3e28 VS |
10041 | I915_WRITE(CURBASE(pipe), base); |
10042 | POSTING_READ(CURBASE(pipe)); | |
99d1f387 VS |
10043 | |
10044 | intel_crtc->cursor_base = base; | |
65a21cd6 JB |
10045 | } |
10046 | ||
cda4b7d3 | 10047 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
6b383a7f CW |
10048 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, |
10049 | bool on) | |
cda4b7d3 CW |
10050 | { |
10051 | struct drm_device *dev = crtc->dev; | |
10052 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10053 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
10054 | int pipe = intel_crtc->pipe; | |
3d7d6510 MR |
10055 | int x = crtc->cursor_x; |
10056 | int y = crtc->cursor_y; | |
d6e4db15 | 10057 | u32 base = 0, pos = 0; |
cda4b7d3 | 10058 | |
d6e4db15 | 10059 | if (on) |
cda4b7d3 | 10060 | base = intel_crtc->cursor_addr; |
cda4b7d3 | 10061 | |
6e3c9717 | 10062 | if (x >= intel_crtc->config->pipe_src_w) |
d6e4db15 VS |
10063 | base = 0; |
10064 | ||
6e3c9717 | 10065 | if (y >= intel_crtc->config->pipe_src_h) |
cda4b7d3 CW |
10066 | base = 0; |
10067 | ||
10068 | if (x < 0) { | |
3dd512fb | 10069 | if (x + intel_crtc->base.cursor->state->crtc_w <= 0) |
cda4b7d3 CW |
10070 | base = 0; |
10071 | ||
10072 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; | |
10073 | x = -x; | |
10074 | } | |
10075 | pos |= x << CURSOR_X_SHIFT; | |
10076 | ||
10077 | if (y < 0) { | |
3dd512fb | 10078 | if (y + intel_crtc->base.cursor->state->crtc_h <= 0) |
cda4b7d3 CW |
10079 | base = 0; |
10080 | ||
10081 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; | |
10082 | y = -y; | |
10083 | } | |
10084 | pos |= y << CURSOR_Y_SHIFT; | |
10085 | ||
4b0e333e | 10086 | if (base == 0 && intel_crtc->cursor_base == 0) |
cda4b7d3 CW |
10087 | return; |
10088 | ||
5efb3e28 VS |
10089 | I915_WRITE(CURPOS(pipe), pos); |
10090 | ||
4398ad45 VS |
10091 | /* ILK+ do this automagically */ |
10092 | if (HAS_GMCH_DISPLAY(dev) && | |
8e7d688b | 10093 | crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) { |
3dd512fb MR |
10094 | base += (intel_crtc->base.cursor->state->crtc_h * |
10095 | intel_crtc->base.cursor->state->crtc_w - 1) * 4; | |
4398ad45 VS |
10096 | } |
10097 | ||
8ac54669 | 10098 | if (IS_845G(dev) || IS_I865G(dev)) |
5efb3e28 VS |
10099 | i845_update_cursor(crtc, base); |
10100 | else | |
10101 | i9xx_update_cursor(crtc, base); | |
cda4b7d3 CW |
10102 | } |
10103 | ||
dc41c154 VS |
10104 | static bool cursor_size_ok(struct drm_device *dev, |
10105 | uint32_t width, uint32_t height) | |
10106 | { | |
10107 | if (width == 0 || height == 0) | |
10108 | return false; | |
10109 | ||
10110 | /* | |
10111 | * 845g/865g are special in that they are only limited by | |
10112 | * the width of their cursors, the height is arbitrary up to | |
10113 | * the precision of the register. Everything else requires | |
10114 | * square cursors, limited to a few power-of-two sizes. | |
10115 | */ | |
10116 | if (IS_845G(dev) || IS_I865G(dev)) { | |
10117 | if ((width & 63) != 0) | |
10118 | return false; | |
10119 | ||
10120 | if (width > (IS_845G(dev) ? 64 : 512)) | |
10121 | return false; | |
10122 | ||
10123 | if (height > 1023) | |
10124 | return false; | |
10125 | } else { | |
10126 | switch (width | height) { | |
10127 | case 256: | |
10128 | case 128: | |
10129 | if (IS_GEN2(dev)) | |
10130 | return false; | |
10131 | case 64: | |
10132 | break; | |
10133 | default: | |
10134 | return false; | |
10135 | } | |
10136 | } | |
10137 | ||
10138 | return true; | |
10139 | } | |
10140 | ||
79e53945 | 10141 | static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
7203425a | 10142 | u16 *blue, uint32_t start, uint32_t size) |
79e53945 | 10143 | { |
7203425a | 10144 | int end = (start + size > 256) ? 256 : start + size, i; |
79e53945 | 10145 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 10146 | |
7203425a | 10147 | for (i = start; i < end; i++) { |
79e53945 JB |
10148 | intel_crtc->lut_r[i] = red[i] >> 8; |
10149 | intel_crtc->lut_g[i] = green[i] >> 8; | |
10150 | intel_crtc->lut_b[i] = blue[i] >> 8; | |
10151 | } | |
10152 | ||
10153 | intel_crtc_load_lut(crtc); | |
10154 | } | |
10155 | ||
79e53945 JB |
10156 | /* VESA 640x480x72Hz mode to set on the pipe */ |
10157 | static struct drm_display_mode load_detect_mode = { | |
10158 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, | |
10159 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), | |
10160 | }; | |
10161 | ||
a8bb6818 DV |
10162 | struct drm_framebuffer * |
10163 | __intel_framebuffer_create(struct drm_device *dev, | |
10164 | struct drm_mode_fb_cmd2 *mode_cmd, | |
10165 | struct drm_i915_gem_object *obj) | |
d2dff872 CW |
10166 | { |
10167 | struct intel_framebuffer *intel_fb; | |
10168 | int ret; | |
10169 | ||
10170 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); | |
10171 | if (!intel_fb) { | |
6ccb81f2 | 10172 | drm_gem_object_unreference(&obj->base); |
d2dff872 CW |
10173 | return ERR_PTR(-ENOMEM); |
10174 | } | |
10175 | ||
10176 | ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); | |
dd4916c5 DV |
10177 | if (ret) |
10178 | goto err; | |
d2dff872 CW |
10179 | |
10180 | return &intel_fb->base; | |
dd4916c5 | 10181 | err: |
6ccb81f2 | 10182 | drm_gem_object_unreference(&obj->base); |
dd4916c5 DV |
10183 | kfree(intel_fb); |
10184 | ||
10185 | return ERR_PTR(ret); | |
d2dff872 CW |
10186 | } |
10187 | ||
b5ea642a | 10188 | static struct drm_framebuffer * |
a8bb6818 DV |
10189 | intel_framebuffer_create(struct drm_device *dev, |
10190 | struct drm_mode_fb_cmd2 *mode_cmd, | |
10191 | struct drm_i915_gem_object *obj) | |
10192 | { | |
10193 | struct drm_framebuffer *fb; | |
10194 | int ret; | |
10195 | ||
10196 | ret = i915_mutex_lock_interruptible(dev); | |
10197 | if (ret) | |
10198 | return ERR_PTR(ret); | |
10199 | fb = __intel_framebuffer_create(dev, mode_cmd, obj); | |
10200 | mutex_unlock(&dev->struct_mutex); | |
10201 | ||
10202 | return fb; | |
10203 | } | |
10204 | ||
d2dff872 CW |
10205 | static u32 |
10206 | intel_framebuffer_pitch_for_width(int width, int bpp) | |
10207 | { | |
10208 | u32 pitch = DIV_ROUND_UP(width * bpp, 8); | |
10209 | return ALIGN(pitch, 64); | |
10210 | } | |
10211 | ||
10212 | static u32 | |
10213 | intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) | |
10214 | { | |
10215 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); | |
1267a26b | 10216 | return PAGE_ALIGN(pitch * mode->vdisplay); |
d2dff872 CW |
10217 | } |
10218 | ||
10219 | static struct drm_framebuffer * | |
10220 | intel_framebuffer_create_for_mode(struct drm_device *dev, | |
10221 | struct drm_display_mode *mode, | |
10222 | int depth, int bpp) | |
10223 | { | |
10224 | struct drm_i915_gem_object *obj; | |
0fed39bd | 10225 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; |
d2dff872 CW |
10226 | |
10227 | obj = i915_gem_alloc_object(dev, | |
10228 | intel_framebuffer_size_for_mode(mode, bpp)); | |
10229 | if (obj == NULL) | |
10230 | return ERR_PTR(-ENOMEM); | |
10231 | ||
10232 | mode_cmd.width = mode->hdisplay; | |
10233 | mode_cmd.height = mode->vdisplay; | |
308e5bcb JB |
10234 | mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, |
10235 | bpp); | |
5ca0c34a | 10236 | mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); |
d2dff872 CW |
10237 | |
10238 | return intel_framebuffer_create(dev, &mode_cmd, obj); | |
10239 | } | |
10240 | ||
10241 | static struct drm_framebuffer * | |
10242 | mode_fits_in_fbdev(struct drm_device *dev, | |
10243 | struct drm_display_mode *mode) | |
10244 | { | |
4520f53a | 10245 | #ifdef CONFIG_DRM_I915_FBDEV |
d2dff872 CW |
10246 | struct drm_i915_private *dev_priv = dev->dev_private; |
10247 | struct drm_i915_gem_object *obj; | |
10248 | struct drm_framebuffer *fb; | |
10249 | ||
4c0e5528 | 10250 | if (!dev_priv->fbdev) |
d2dff872 CW |
10251 | return NULL; |
10252 | ||
4c0e5528 | 10253 | if (!dev_priv->fbdev->fb) |
d2dff872 CW |
10254 | return NULL; |
10255 | ||
4c0e5528 DV |
10256 | obj = dev_priv->fbdev->fb->obj; |
10257 | BUG_ON(!obj); | |
10258 | ||
8bcd4553 | 10259 | fb = &dev_priv->fbdev->fb->base; |
01f2c773 VS |
10260 | if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, |
10261 | fb->bits_per_pixel)) | |
d2dff872 CW |
10262 | return NULL; |
10263 | ||
01f2c773 | 10264 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
d2dff872 CW |
10265 | return NULL; |
10266 | ||
10267 | return fb; | |
4520f53a DV |
10268 | #else |
10269 | return NULL; | |
10270 | #endif | |
d2dff872 CW |
10271 | } |
10272 | ||
d3a40d1b ACO |
10273 | static int intel_modeset_setup_plane_state(struct drm_atomic_state *state, |
10274 | struct drm_crtc *crtc, | |
10275 | struct drm_display_mode *mode, | |
10276 | struct drm_framebuffer *fb, | |
10277 | int x, int y) | |
10278 | { | |
10279 | struct drm_plane_state *plane_state; | |
10280 | int hdisplay, vdisplay; | |
10281 | int ret; | |
10282 | ||
10283 | plane_state = drm_atomic_get_plane_state(state, crtc->primary); | |
10284 | if (IS_ERR(plane_state)) | |
10285 | return PTR_ERR(plane_state); | |
10286 | ||
10287 | if (mode) | |
10288 | drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay); | |
10289 | else | |
10290 | hdisplay = vdisplay = 0; | |
10291 | ||
10292 | ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL); | |
10293 | if (ret) | |
10294 | return ret; | |
10295 | drm_atomic_set_fb_for_plane(plane_state, fb); | |
10296 | plane_state->crtc_x = 0; | |
10297 | plane_state->crtc_y = 0; | |
10298 | plane_state->crtc_w = hdisplay; | |
10299 | plane_state->crtc_h = vdisplay; | |
10300 | plane_state->src_x = x << 16; | |
10301 | plane_state->src_y = y << 16; | |
10302 | plane_state->src_w = hdisplay << 16; | |
10303 | plane_state->src_h = vdisplay << 16; | |
10304 | ||
10305 | return 0; | |
10306 | } | |
10307 | ||
d2434ab7 | 10308 | bool intel_get_load_detect_pipe(struct drm_connector *connector, |
7173188d | 10309 | struct drm_display_mode *mode, |
51fd371b RC |
10310 | struct intel_load_detect_pipe *old, |
10311 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 JB |
10312 | { |
10313 | struct intel_crtc *intel_crtc; | |
d2434ab7 DV |
10314 | struct intel_encoder *intel_encoder = |
10315 | intel_attached_encoder(connector); | |
79e53945 | 10316 | struct drm_crtc *possible_crtc; |
4ef69c7a | 10317 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
10318 | struct drm_crtc *crtc = NULL; |
10319 | struct drm_device *dev = encoder->dev; | |
94352cf9 | 10320 | struct drm_framebuffer *fb; |
51fd371b | 10321 | struct drm_mode_config *config = &dev->mode_config; |
83a57153 | 10322 | struct drm_atomic_state *state = NULL; |
944b0c76 | 10323 | struct drm_connector_state *connector_state; |
4be07317 | 10324 | struct intel_crtc_state *crtc_state; |
51fd371b | 10325 | int ret, i = -1; |
79e53945 | 10326 | |
d2dff872 | 10327 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 10328 | connector->base.id, connector->name, |
8e329a03 | 10329 | encoder->base.id, encoder->name); |
d2dff872 | 10330 | |
51fd371b RC |
10331 | retry: |
10332 | ret = drm_modeset_lock(&config->connection_mutex, ctx); | |
10333 | if (ret) | |
37ade417 | 10334 | goto fail; |
6e9f798d | 10335 | |
79e53945 JB |
10336 | /* |
10337 | * Algorithm gets a little messy: | |
7a5e4805 | 10338 | * |
79e53945 JB |
10339 | * - if the connector already has an assigned crtc, use it (but make |
10340 | * sure it's on first) | |
7a5e4805 | 10341 | * |
79e53945 JB |
10342 | * - try to find the first unused crtc that can drive this connector, |
10343 | * and use that if we find one | |
79e53945 JB |
10344 | */ |
10345 | ||
10346 | /* See if we already have a CRTC for this connector */ | |
10347 | if (encoder->crtc) { | |
10348 | crtc = encoder->crtc; | |
8261b191 | 10349 | |
51fd371b | 10350 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
4d02e2de | 10351 | if (ret) |
37ade417 | 10352 | goto fail; |
4d02e2de | 10353 | ret = drm_modeset_lock(&crtc->primary->mutex, ctx); |
51fd371b | 10354 | if (ret) |
37ade417 | 10355 | goto fail; |
7b24056b | 10356 | |
24218aac | 10357 | old->dpms_mode = connector->dpms; |
8261b191 CW |
10358 | old->load_detect_temp = false; |
10359 | ||
10360 | /* Make sure the crtc and connector are running */ | |
24218aac DV |
10361 | if (connector->dpms != DRM_MODE_DPMS_ON) |
10362 | connector->funcs->dpms(connector, DRM_MODE_DPMS_ON); | |
8261b191 | 10363 | |
7173188d | 10364 | return true; |
79e53945 JB |
10365 | } |
10366 | ||
10367 | /* Find an unused one (if possible) */ | |
70e1e0ec | 10368 | for_each_crtc(dev, possible_crtc) { |
79e53945 JB |
10369 | i++; |
10370 | if (!(encoder->possible_crtcs & (1 << i))) | |
10371 | continue; | |
83d65738 | 10372 | if (possible_crtc->state->enable) |
a459249c | 10373 | continue; |
a459249c VS |
10374 | |
10375 | crtc = possible_crtc; | |
10376 | break; | |
79e53945 JB |
10377 | } |
10378 | ||
10379 | /* | |
10380 | * If we didn't find an unused CRTC, don't use any. | |
10381 | */ | |
10382 | if (!crtc) { | |
7173188d | 10383 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
37ade417 | 10384 | goto fail; |
79e53945 JB |
10385 | } |
10386 | ||
51fd371b RC |
10387 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
10388 | if (ret) | |
37ade417 | 10389 | goto fail; |
4d02e2de DV |
10390 | ret = drm_modeset_lock(&crtc->primary->mutex, ctx); |
10391 | if (ret) | |
37ade417 | 10392 | goto fail; |
79e53945 JB |
10393 | |
10394 | intel_crtc = to_intel_crtc(crtc); | |
24218aac | 10395 | old->dpms_mode = connector->dpms; |
8261b191 | 10396 | old->load_detect_temp = true; |
d2dff872 | 10397 | old->release_fb = NULL; |
79e53945 | 10398 | |
83a57153 ACO |
10399 | state = drm_atomic_state_alloc(dev); |
10400 | if (!state) | |
10401 | return false; | |
10402 | ||
10403 | state->acquire_ctx = ctx; | |
10404 | ||
944b0c76 ACO |
10405 | connector_state = drm_atomic_get_connector_state(state, connector); |
10406 | if (IS_ERR(connector_state)) { | |
10407 | ret = PTR_ERR(connector_state); | |
10408 | goto fail; | |
10409 | } | |
10410 | ||
10411 | connector_state->crtc = crtc; | |
10412 | connector_state->best_encoder = &intel_encoder->base; | |
10413 | ||
4be07317 ACO |
10414 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); |
10415 | if (IS_ERR(crtc_state)) { | |
10416 | ret = PTR_ERR(crtc_state); | |
10417 | goto fail; | |
10418 | } | |
10419 | ||
49d6fa21 | 10420 | crtc_state->base.active = crtc_state->base.enable = true; |
4be07317 | 10421 | |
6492711d CW |
10422 | if (!mode) |
10423 | mode = &load_detect_mode; | |
79e53945 | 10424 | |
d2dff872 CW |
10425 | /* We need a framebuffer large enough to accommodate all accesses |
10426 | * that the plane may generate whilst we perform load detection. | |
10427 | * We can not rely on the fbcon either being present (we get called | |
10428 | * during its initialisation to detect all boot displays, or it may | |
10429 | * not even exist) or that it is large enough to satisfy the | |
10430 | * requested mode. | |
10431 | */ | |
94352cf9 DV |
10432 | fb = mode_fits_in_fbdev(dev, mode); |
10433 | if (fb == NULL) { | |
d2dff872 | 10434 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); |
94352cf9 DV |
10435 | fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); |
10436 | old->release_fb = fb; | |
d2dff872 CW |
10437 | } else |
10438 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); | |
94352cf9 | 10439 | if (IS_ERR(fb)) { |
d2dff872 | 10440 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); |
412b61d8 | 10441 | goto fail; |
79e53945 | 10442 | } |
79e53945 | 10443 | |
d3a40d1b ACO |
10444 | ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0); |
10445 | if (ret) | |
10446 | goto fail; | |
10447 | ||
8c7b5ccb ACO |
10448 | drm_mode_copy(&crtc_state->base.mode, mode); |
10449 | ||
568c634a | 10450 | if (intel_set_mode(state)) { |
6492711d | 10451 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
d2dff872 CW |
10452 | if (old->release_fb) |
10453 | old->release_fb->funcs->destroy(old->release_fb); | |
412b61d8 | 10454 | goto fail; |
79e53945 | 10455 | } |
9128b040 | 10456 | crtc->primary->crtc = crtc; |
7173188d | 10457 | |
79e53945 | 10458 | /* let the connector get through one full cycle before testing */ |
9d0498a2 | 10459 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
7173188d | 10460 | return true; |
412b61d8 | 10461 | |
37ade417 | 10462 | fail: |
e5d958ef ACO |
10463 | drm_atomic_state_free(state); |
10464 | state = NULL; | |
83a57153 | 10465 | |
51fd371b RC |
10466 | if (ret == -EDEADLK) { |
10467 | drm_modeset_backoff(ctx); | |
10468 | goto retry; | |
10469 | } | |
10470 | ||
412b61d8 | 10471 | return false; |
79e53945 JB |
10472 | } |
10473 | ||
d2434ab7 | 10474 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
49172fee ACO |
10475 | struct intel_load_detect_pipe *old, |
10476 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 | 10477 | { |
83a57153 | 10478 | struct drm_device *dev = connector->dev; |
d2434ab7 DV |
10479 | struct intel_encoder *intel_encoder = |
10480 | intel_attached_encoder(connector); | |
4ef69c7a | 10481 | struct drm_encoder *encoder = &intel_encoder->base; |
7b24056b | 10482 | struct drm_crtc *crtc = encoder->crtc; |
412b61d8 | 10483 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
83a57153 | 10484 | struct drm_atomic_state *state; |
944b0c76 | 10485 | struct drm_connector_state *connector_state; |
4be07317 | 10486 | struct intel_crtc_state *crtc_state; |
d3a40d1b | 10487 | int ret; |
79e53945 | 10488 | |
d2dff872 | 10489 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 10490 | connector->base.id, connector->name, |
8e329a03 | 10491 | encoder->base.id, encoder->name); |
d2dff872 | 10492 | |
8261b191 | 10493 | if (old->load_detect_temp) { |
83a57153 | 10494 | state = drm_atomic_state_alloc(dev); |
944b0c76 ACO |
10495 | if (!state) |
10496 | goto fail; | |
83a57153 ACO |
10497 | |
10498 | state->acquire_ctx = ctx; | |
10499 | ||
944b0c76 ACO |
10500 | connector_state = drm_atomic_get_connector_state(state, connector); |
10501 | if (IS_ERR(connector_state)) | |
10502 | goto fail; | |
10503 | ||
4be07317 ACO |
10504 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); |
10505 | if (IS_ERR(crtc_state)) | |
10506 | goto fail; | |
10507 | ||
944b0c76 ACO |
10508 | connector_state->best_encoder = NULL; |
10509 | connector_state->crtc = NULL; | |
10510 | ||
49d6fa21 | 10511 | crtc_state->base.enable = crtc_state->base.active = false; |
4be07317 | 10512 | |
d3a40d1b ACO |
10513 | ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL, |
10514 | 0, 0); | |
10515 | if (ret) | |
10516 | goto fail; | |
10517 | ||
568c634a | 10518 | ret = intel_set_mode(state); |
2bfb4627 ACO |
10519 | if (ret) |
10520 | goto fail; | |
d2dff872 | 10521 | |
36206361 DV |
10522 | if (old->release_fb) { |
10523 | drm_framebuffer_unregister_private(old->release_fb); | |
10524 | drm_framebuffer_unreference(old->release_fb); | |
10525 | } | |
d2dff872 | 10526 | |
0622a53c | 10527 | return; |
79e53945 JB |
10528 | } |
10529 | ||
c751ce4f | 10530 | /* Switch crtc and encoder back off if necessary */ |
24218aac DV |
10531 | if (old->dpms_mode != DRM_MODE_DPMS_ON) |
10532 | connector->funcs->dpms(connector, old->dpms_mode); | |
944b0c76 ACO |
10533 | |
10534 | return; | |
10535 | fail: | |
10536 | DRM_DEBUG_KMS("Couldn't release load detect pipe.\n"); | |
10537 | drm_atomic_state_free(state); | |
79e53945 JB |
10538 | } |
10539 | ||
da4a1efa | 10540 | static int i9xx_pll_refclk(struct drm_device *dev, |
5cec258b | 10541 | const struct intel_crtc_state *pipe_config) |
da4a1efa VS |
10542 | { |
10543 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10544 | u32 dpll = pipe_config->dpll_hw_state.dpll; | |
10545 | ||
10546 | if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) | |
e91e941b | 10547 | return dev_priv->vbt.lvds_ssc_freq; |
da4a1efa VS |
10548 | else if (HAS_PCH_SPLIT(dev)) |
10549 | return 120000; | |
10550 | else if (!IS_GEN2(dev)) | |
10551 | return 96000; | |
10552 | else | |
10553 | return 48000; | |
10554 | } | |
10555 | ||
79e53945 | 10556 | /* Returns the clock of the currently programmed mode of the given pipe. */ |
f1f644dc | 10557 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 10558 | struct intel_crtc_state *pipe_config) |
79e53945 | 10559 | { |
f1f644dc | 10560 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 10561 | struct drm_i915_private *dev_priv = dev->dev_private; |
f1f644dc | 10562 | int pipe = pipe_config->cpu_transcoder; |
293623f7 | 10563 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
79e53945 JB |
10564 | u32 fp; |
10565 | intel_clock_t clock; | |
da4a1efa | 10566 | int refclk = i9xx_pll_refclk(dev, pipe_config); |
79e53945 JB |
10567 | |
10568 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) | |
293623f7 | 10569 | fp = pipe_config->dpll_hw_state.fp0; |
79e53945 | 10570 | else |
293623f7 | 10571 | fp = pipe_config->dpll_hw_state.fp1; |
79e53945 JB |
10572 | |
10573 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; | |
f2b115e6 AJ |
10574 | if (IS_PINEVIEW(dev)) { |
10575 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; | |
10576 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
2177832f SL |
10577 | } else { |
10578 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; | |
10579 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
10580 | } | |
10581 | ||
a6c45cf0 | 10582 | if (!IS_GEN2(dev)) { |
f2b115e6 AJ |
10583 | if (IS_PINEVIEW(dev)) |
10584 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> | |
10585 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); | |
2177832f SL |
10586 | else |
10587 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> | |
79e53945 JB |
10588 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
10589 | ||
10590 | switch (dpll & DPLL_MODE_MASK) { | |
10591 | case DPLLB_MODE_DAC_SERIAL: | |
10592 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? | |
10593 | 5 : 10; | |
10594 | break; | |
10595 | case DPLLB_MODE_LVDS: | |
10596 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? | |
10597 | 7 : 14; | |
10598 | break; | |
10599 | default: | |
28c97730 | 10600 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
79e53945 | 10601 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
f1f644dc | 10602 | return; |
79e53945 JB |
10603 | } |
10604 | ||
ac58c3f0 | 10605 | if (IS_PINEVIEW(dev)) |
da4a1efa | 10606 | pineview_clock(refclk, &clock); |
ac58c3f0 | 10607 | else |
da4a1efa | 10608 | i9xx_clock(refclk, &clock); |
79e53945 | 10609 | } else { |
0fb58223 | 10610 | u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS); |
b1c560d1 | 10611 | bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN); |
79e53945 JB |
10612 | |
10613 | if (is_lvds) { | |
10614 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> | |
10615 | DPLL_FPA01_P1_POST_DIV_SHIFT); | |
b1c560d1 VS |
10616 | |
10617 | if (lvds & LVDS_CLKB_POWER_UP) | |
10618 | clock.p2 = 7; | |
10619 | else | |
10620 | clock.p2 = 14; | |
79e53945 JB |
10621 | } else { |
10622 | if (dpll & PLL_P1_DIVIDE_BY_TWO) | |
10623 | clock.p1 = 2; | |
10624 | else { | |
10625 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> | |
10626 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; | |
10627 | } | |
10628 | if (dpll & PLL_P2_DIVIDE_BY_4) | |
10629 | clock.p2 = 4; | |
10630 | else | |
10631 | clock.p2 = 2; | |
79e53945 | 10632 | } |
da4a1efa VS |
10633 | |
10634 | i9xx_clock(refclk, &clock); | |
79e53945 JB |
10635 | } |
10636 | ||
18442d08 VS |
10637 | /* |
10638 | * This value includes pixel_multiplier. We will use | |
241bfc38 | 10639 | * port_clock to compute adjusted_mode.crtc_clock in the |
18442d08 VS |
10640 | * encoder's get_config() function. |
10641 | */ | |
10642 | pipe_config->port_clock = clock.dot; | |
f1f644dc JB |
10643 | } |
10644 | ||
6878da05 VS |
10645 | int intel_dotclock_calculate(int link_freq, |
10646 | const struct intel_link_m_n *m_n) | |
f1f644dc | 10647 | { |
f1f644dc JB |
10648 | /* |
10649 | * The calculation for the data clock is: | |
1041a02f | 10650 | * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp |
f1f644dc | 10651 | * But we want to avoid losing precison if possible, so: |
1041a02f | 10652 | * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) |
f1f644dc JB |
10653 | * |
10654 | * and the link clock is simpler: | |
1041a02f | 10655 | * link_clock = (m * link_clock) / n |
f1f644dc JB |
10656 | */ |
10657 | ||
6878da05 VS |
10658 | if (!m_n->link_n) |
10659 | return 0; | |
f1f644dc | 10660 | |
6878da05 VS |
10661 | return div_u64((u64)m_n->link_m * link_freq, m_n->link_n); |
10662 | } | |
f1f644dc | 10663 | |
18442d08 | 10664 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 10665 | struct intel_crtc_state *pipe_config) |
6878da05 VS |
10666 | { |
10667 | struct drm_device *dev = crtc->base.dev; | |
79e53945 | 10668 | |
18442d08 VS |
10669 | /* read out port_clock from the DPLL */ |
10670 | i9xx_crtc_clock_get(crtc, pipe_config); | |
f1f644dc | 10671 | |
f1f644dc | 10672 | /* |
18442d08 | 10673 | * This value does not include pixel_multiplier. |
241bfc38 | 10674 | * We will check that port_clock and adjusted_mode.crtc_clock |
18442d08 VS |
10675 | * agree once we know their relationship in the encoder's |
10676 | * get_config() function. | |
79e53945 | 10677 | */ |
2d112de7 | 10678 | pipe_config->base.adjusted_mode.crtc_clock = |
18442d08 VS |
10679 | intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000, |
10680 | &pipe_config->fdi_m_n); | |
79e53945 JB |
10681 | } |
10682 | ||
10683 | /** Returns the currently programmed mode of the given pipe. */ | |
10684 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
10685 | struct drm_crtc *crtc) | |
10686 | { | |
548f245b | 10687 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 10688 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6e3c9717 | 10689 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
79e53945 | 10690 | struct drm_display_mode *mode; |
5cec258b | 10691 | struct intel_crtc_state pipe_config; |
fe2b8f9d PZ |
10692 | int htot = I915_READ(HTOTAL(cpu_transcoder)); |
10693 | int hsync = I915_READ(HSYNC(cpu_transcoder)); | |
10694 | int vtot = I915_READ(VTOTAL(cpu_transcoder)); | |
10695 | int vsync = I915_READ(VSYNC(cpu_transcoder)); | |
293623f7 | 10696 | enum pipe pipe = intel_crtc->pipe; |
79e53945 JB |
10697 | |
10698 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); | |
10699 | if (!mode) | |
10700 | return NULL; | |
10701 | ||
f1f644dc JB |
10702 | /* |
10703 | * Construct a pipe_config sufficient for getting the clock info | |
10704 | * back out of crtc_clock_get. | |
10705 | * | |
10706 | * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need | |
10707 | * to use a real value here instead. | |
10708 | */ | |
293623f7 | 10709 | pipe_config.cpu_transcoder = (enum transcoder) pipe; |
f1f644dc | 10710 | pipe_config.pixel_multiplier = 1; |
293623f7 VS |
10711 | pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe)); |
10712 | pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe)); | |
10713 | pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe)); | |
f1f644dc JB |
10714 | i9xx_crtc_clock_get(intel_crtc, &pipe_config); |
10715 | ||
773ae034 | 10716 | mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier; |
79e53945 JB |
10717 | mode->hdisplay = (htot & 0xffff) + 1; |
10718 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; | |
10719 | mode->hsync_start = (hsync & 0xffff) + 1; | |
10720 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; | |
10721 | mode->vdisplay = (vtot & 0xffff) + 1; | |
10722 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; | |
10723 | mode->vsync_start = (vsync & 0xffff) + 1; | |
10724 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; | |
10725 | ||
10726 | drm_mode_set_name(mode); | |
79e53945 JB |
10727 | |
10728 | return mode; | |
10729 | } | |
10730 | ||
652c393a JB |
10731 | static void intel_decrease_pllclock(struct drm_crtc *crtc) |
10732 | { | |
10733 | struct drm_device *dev = crtc->dev; | |
fbee40df | 10734 | struct drm_i915_private *dev_priv = dev->dev_private; |
652c393a | 10735 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
652c393a | 10736 | |
baff296c | 10737 | if (!HAS_GMCH_DISPLAY(dev)) |
652c393a JB |
10738 | return; |
10739 | ||
10740 | if (!dev_priv->lvds_downclock_avail) | |
10741 | return; | |
10742 | ||
10743 | /* | |
10744 | * Since this is called by a timer, we should never get here in | |
10745 | * the manual case. | |
10746 | */ | |
10747 | if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) { | |
dc257cf1 DV |
10748 | int pipe = intel_crtc->pipe; |
10749 | int dpll_reg = DPLL(pipe); | |
10750 | int dpll; | |
f6e5b160 | 10751 | |
44d98a61 | 10752 | DRM_DEBUG_DRIVER("downclocking LVDS\n"); |
652c393a | 10753 | |
8ac5a6d5 | 10754 | assert_panel_unlocked(dev_priv, pipe); |
652c393a | 10755 | |
dc257cf1 | 10756 | dpll = I915_READ(dpll_reg); |
652c393a JB |
10757 | dpll |= DISPLAY_RATE_SELECT_FPA1; |
10758 | I915_WRITE(dpll_reg, dpll); | |
9d0498a2 | 10759 | intel_wait_for_vblank(dev, pipe); |
652c393a JB |
10760 | dpll = I915_READ(dpll_reg); |
10761 | if (!(dpll & DISPLAY_RATE_SELECT_FPA1)) | |
44d98a61 | 10762 | DRM_DEBUG_DRIVER("failed to downclock LVDS!\n"); |
652c393a JB |
10763 | } |
10764 | ||
10765 | } | |
10766 | ||
f047e395 CW |
10767 | void intel_mark_busy(struct drm_device *dev) |
10768 | { | |
c67a470b PZ |
10769 | struct drm_i915_private *dev_priv = dev->dev_private; |
10770 | ||
f62a0076 CW |
10771 | if (dev_priv->mm.busy) |
10772 | return; | |
10773 | ||
43694d69 | 10774 | intel_runtime_pm_get(dev_priv); |
c67a470b | 10775 | i915_update_gfx_val(dev_priv); |
43cf3bf0 CW |
10776 | if (INTEL_INFO(dev)->gen >= 6) |
10777 | gen6_rps_busy(dev_priv); | |
f62a0076 | 10778 | dev_priv->mm.busy = true; |
f047e395 CW |
10779 | } |
10780 | ||
10781 | void intel_mark_idle(struct drm_device *dev) | |
652c393a | 10782 | { |
c67a470b | 10783 | struct drm_i915_private *dev_priv = dev->dev_private; |
652c393a | 10784 | struct drm_crtc *crtc; |
652c393a | 10785 | |
f62a0076 CW |
10786 | if (!dev_priv->mm.busy) |
10787 | return; | |
10788 | ||
10789 | dev_priv->mm.busy = false; | |
10790 | ||
70e1e0ec | 10791 | for_each_crtc(dev, crtc) { |
f4510a27 | 10792 | if (!crtc->primary->fb) |
652c393a JB |
10793 | continue; |
10794 | ||
725a5b54 | 10795 | intel_decrease_pllclock(crtc); |
652c393a | 10796 | } |
b29c19b6 | 10797 | |
3d13ef2e | 10798 | if (INTEL_INFO(dev)->gen >= 6) |
b29c19b6 | 10799 | gen6_rps_idle(dev->dev_private); |
bb4cdd53 | 10800 | |
43694d69 | 10801 | intel_runtime_pm_put(dev_priv); |
652c393a JB |
10802 | } |
10803 | ||
79e53945 JB |
10804 | static void intel_crtc_destroy(struct drm_crtc *crtc) |
10805 | { | |
10806 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
67e77c5a DV |
10807 | struct drm_device *dev = crtc->dev; |
10808 | struct intel_unpin_work *work; | |
67e77c5a | 10809 | |
5e2d7afc | 10810 | spin_lock_irq(&dev->event_lock); |
67e77c5a DV |
10811 | work = intel_crtc->unpin_work; |
10812 | intel_crtc->unpin_work = NULL; | |
5e2d7afc | 10813 | spin_unlock_irq(&dev->event_lock); |
67e77c5a DV |
10814 | |
10815 | if (work) { | |
10816 | cancel_work_sync(&work->work); | |
10817 | kfree(work); | |
10818 | } | |
79e53945 JB |
10819 | |
10820 | drm_crtc_cleanup(crtc); | |
67e77c5a | 10821 | |
79e53945 JB |
10822 | kfree(intel_crtc); |
10823 | } | |
10824 | ||
6b95a207 KH |
10825 | static void intel_unpin_work_fn(struct work_struct *__work) |
10826 | { | |
10827 | struct intel_unpin_work *work = | |
10828 | container_of(__work, struct intel_unpin_work, work); | |
b4a98e57 | 10829 | struct drm_device *dev = work->crtc->dev; |
f99d7069 | 10830 | enum pipe pipe = to_intel_crtc(work->crtc)->pipe; |
6b95a207 | 10831 | |
b4a98e57 | 10832 | mutex_lock(&dev->struct_mutex); |
82bc3b2d | 10833 | intel_unpin_fb_obj(work->old_fb, work->crtc->primary->state); |
05394f39 | 10834 | drm_gem_object_unreference(&work->pending_flip_obj->base); |
d9e86c0e | 10835 | |
7ff0ebcc | 10836 | intel_fbc_update(dev); |
f06cc1b9 JH |
10837 | |
10838 | if (work->flip_queued_req) | |
146d84f0 | 10839 | i915_gem_request_assign(&work->flip_queued_req, NULL); |
b4a98e57 CW |
10840 | mutex_unlock(&dev->struct_mutex); |
10841 | ||
f99d7069 | 10842 | intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe)); |
89ed88ba | 10843 | drm_framebuffer_unreference(work->old_fb); |
f99d7069 | 10844 | |
b4a98e57 CW |
10845 | BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0); |
10846 | atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count); | |
10847 | ||
6b95a207 KH |
10848 | kfree(work); |
10849 | } | |
10850 | ||
1afe3e9d | 10851 | static void do_intel_finish_page_flip(struct drm_device *dev, |
49b14a5c | 10852 | struct drm_crtc *crtc) |
6b95a207 | 10853 | { |
6b95a207 KH |
10854 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
10855 | struct intel_unpin_work *work; | |
6b95a207 KH |
10856 | unsigned long flags; |
10857 | ||
10858 | /* Ignore early vblank irqs */ | |
10859 | if (intel_crtc == NULL) | |
10860 | return; | |
10861 | ||
f326038a DV |
10862 | /* |
10863 | * This is called both by irq handlers and the reset code (to complete | |
10864 | * lost pageflips) so needs the full irqsave spinlocks. | |
10865 | */ | |
6b95a207 KH |
10866 | spin_lock_irqsave(&dev->event_lock, flags); |
10867 | work = intel_crtc->unpin_work; | |
e7d841ca CW |
10868 | |
10869 | /* Ensure we don't miss a work->pending update ... */ | |
10870 | smp_rmb(); | |
10871 | ||
10872 | if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { | |
6b95a207 KH |
10873 | spin_unlock_irqrestore(&dev->event_lock, flags); |
10874 | return; | |
10875 | } | |
10876 | ||
d6bbafa1 | 10877 | page_flip_completed(intel_crtc); |
0af7e4df | 10878 | |
6b95a207 | 10879 | spin_unlock_irqrestore(&dev->event_lock, flags); |
6b95a207 KH |
10880 | } |
10881 | ||
1afe3e9d JB |
10882 | void intel_finish_page_flip(struct drm_device *dev, int pipe) |
10883 | { | |
fbee40df | 10884 | struct drm_i915_private *dev_priv = dev->dev_private; |
1afe3e9d JB |
10885 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
10886 | ||
49b14a5c | 10887 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
10888 | } |
10889 | ||
10890 | void intel_finish_page_flip_plane(struct drm_device *dev, int plane) | |
10891 | { | |
fbee40df | 10892 | struct drm_i915_private *dev_priv = dev->dev_private; |
1afe3e9d JB |
10893 | struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane]; |
10894 | ||
49b14a5c | 10895 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
10896 | } |
10897 | ||
75f7f3ec VS |
10898 | /* Is 'a' after or equal to 'b'? */ |
10899 | static bool g4x_flip_count_after_eq(u32 a, u32 b) | |
10900 | { | |
10901 | return !((a - b) & 0x80000000); | |
10902 | } | |
10903 | ||
10904 | static bool page_flip_finished(struct intel_crtc *crtc) | |
10905 | { | |
10906 | struct drm_device *dev = crtc->base.dev; | |
10907 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10908 | ||
bdfa7542 VS |
10909 | if (i915_reset_in_progress(&dev_priv->gpu_error) || |
10910 | crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) | |
10911 | return true; | |
10912 | ||
75f7f3ec VS |
10913 | /* |
10914 | * The relevant registers doen't exist on pre-ctg. | |
10915 | * As the flip done interrupt doesn't trigger for mmio | |
10916 | * flips on gmch platforms, a flip count check isn't | |
10917 | * really needed there. But since ctg has the registers, | |
10918 | * include it in the check anyway. | |
10919 | */ | |
10920 | if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev)) | |
10921 | return true; | |
10922 | ||
10923 | /* | |
10924 | * A DSPSURFLIVE check isn't enough in case the mmio and CS flips | |
10925 | * used the same base address. In that case the mmio flip might | |
10926 | * have completed, but the CS hasn't even executed the flip yet. | |
10927 | * | |
10928 | * A flip count check isn't enough as the CS might have updated | |
10929 | * the base address just after start of vblank, but before we | |
10930 | * managed to process the interrupt. This means we'd complete the | |
10931 | * CS flip too soon. | |
10932 | * | |
10933 | * Combining both checks should get us a good enough result. It may | |
10934 | * still happen that the CS flip has been executed, but has not | |
10935 | * yet actually completed. But in case the base address is the same | |
10936 | * anyway, we don't really care. | |
10937 | */ | |
10938 | return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) == | |
10939 | crtc->unpin_work->gtt_offset && | |
10940 | g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)), | |
10941 | crtc->unpin_work->flip_count); | |
10942 | } | |
10943 | ||
6b95a207 KH |
10944 | void intel_prepare_page_flip(struct drm_device *dev, int plane) |
10945 | { | |
fbee40df | 10946 | struct drm_i915_private *dev_priv = dev->dev_private; |
6b95a207 KH |
10947 | struct intel_crtc *intel_crtc = |
10948 | to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]); | |
10949 | unsigned long flags; | |
10950 | ||
f326038a DV |
10951 | |
10952 | /* | |
10953 | * This is called both by irq handlers and the reset code (to complete | |
10954 | * lost pageflips) so needs the full irqsave spinlocks. | |
10955 | * | |
10956 | * NB: An MMIO update of the plane base pointer will also | |
e7d841ca CW |
10957 | * generate a page-flip completion irq, i.e. every modeset |
10958 | * is also accompanied by a spurious intel_prepare_page_flip(). | |
10959 | */ | |
6b95a207 | 10960 | spin_lock_irqsave(&dev->event_lock, flags); |
75f7f3ec | 10961 | if (intel_crtc->unpin_work && page_flip_finished(intel_crtc)) |
e7d841ca | 10962 | atomic_inc_not_zero(&intel_crtc->unpin_work->pending); |
6b95a207 KH |
10963 | spin_unlock_irqrestore(&dev->event_lock, flags); |
10964 | } | |
10965 | ||
eba905b2 | 10966 | static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc) |
e7d841ca CW |
10967 | { |
10968 | /* Ensure that the work item is consistent when activating it ... */ | |
10969 | smp_wmb(); | |
10970 | atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING); | |
10971 | /* and that it is marked active as soon as the irq could fire. */ | |
10972 | smp_wmb(); | |
10973 | } | |
10974 | ||
8c9f3aaf JB |
10975 | static int intel_gen2_queue_flip(struct drm_device *dev, |
10976 | struct drm_crtc *crtc, | |
10977 | struct drm_framebuffer *fb, | |
ed8d1975 | 10978 | struct drm_i915_gem_object *obj, |
a4872ba6 | 10979 | struct intel_engine_cs *ring, |
ed8d1975 | 10980 | uint32_t flags) |
8c9f3aaf | 10981 | { |
8c9f3aaf | 10982 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8c9f3aaf JB |
10983 | u32 flip_mask; |
10984 | int ret; | |
10985 | ||
6d90c952 | 10986 | ret = intel_ring_begin(ring, 6); |
8c9f3aaf | 10987 | if (ret) |
4fa62c89 | 10988 | return ret; |
8c9f3aaf JB |
10989 | |
10990 | /* Can't queue multiple flips, so wait for the previous | |
10991 | * one to finish before executing the next. | |
10992 | */ | |
10993 | if (intel_crtc->plane) | |
10994 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
10995 | else | |
10996 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
10997 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
10998 | intel_ring_emit(ring, MI_NOOP); | |
10999 | intel_ring_emit(ring, MI_DISPLAY_FLIP | | |
11000 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
11001 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 11002 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
6d90c952 | 11003 | intel_ring_emit(ring, 0); /* aux display base address, unused */ |
e7d841ca CW |
11004 | |
11005 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 11006 | __intel_ring_advance(ring); |
83d4092b | 11007 | return 0; |
8c9f3aaf JB |
11008 | } |
11009 | ||
11010 | static int intel_gen3_queue_flip(struct drm_device *dev, | |
11011 | struct drm_crtc *crtc, | |
11012 | struct drm_framebuffer *fb, | |
ed8d1975 | 11013 | struct drm_i915_gem_object *obj, |
a4872ba6 | 11014 | struct intel_engine_cs *ring, |
ed8d1975 | 11015 | uint32_t flags) |
8c9f3aaf | 11016 | { |
8c9f3aaf | 11017 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8c9f3aaf JB |
11018 | u32 flip_mask; |
11019 | int ret; | |
11020 | ||
6d90c952 | 11021 | ret = intel_ring_begin(ring, 6); |
8c9f3aaf | 11022 | if (ret) |
4fa62c89 | 11023 | return ret; |
8c9f3aaf JB |
11024 | |
11025 | if (intel_crtc->plane) | |
11026 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
11027 | else | |
11028 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
11029 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
11030 | intel_ring_emit(ring, MI_NOOP); | |
11031 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | | |
11032 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
11033 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 11034 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
6d90c952 DV |
11035 | intel_ring_emit(ring, MI_NOOP); |
11036 | ||
e7d841ca | 11037 | intel_mark_page_flip_active(intel_crtc); |
09246732 | 11038 | __intel_ring_advance(ring); |
83d4092b | 11039 | return 0; |
8c9f3aaf JB |
11040 | } |
11041 | ||
11042 | static int intel_gen4_queue_flip(struct drm_device *dev, | |
11043 | struct drm_crtc *crtc, | |
11044 | struct drm_framebuffer *fb, | |
ed8d1975 | 11045 | struct drm_i915_gem_object *obj, |
a4872ba6 | 11046 | struct intel_engine_cs *ring, |
ed8d1975 | 11047 | uint32_t flags) |
8c9f3aaf JB |
11048 | { |
11049 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11050 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11051 | uint32_t pf, pipesrc; | |
11052 | int ret; | |
11053 | ||
6d90c952 | 11054 | ret = intel_ring_begin(ring, 4); |
8c9f3aaf | 11055 | if (ret) |
4fa62c89 | 11056 | return ret; |
8c9f3aaf JB |
11057 | |
11058 | /* i965+ uses the linear or tiled offsets from the | |
11059 | * Display Registers (which do not change across a page-flip) | |
11060 | * so we need only reprogram the base address. | |
11061 | */ | |
6d90c952 DV |
11062 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
11063 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
11064 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 11065 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset | |
c2c75131 | 11066 | obj->tiling_mode); |
8c9f3aaf JB |
11067 | |
11068 | /* XXX Enabling the panel-fitter across page-flip is so far | |
11069 | * untested on non-native modes, so ignore it for now. | |
11070 | * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; | |
11071 | */ | |
11072 | pf = 0; | |
11073 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; | |
6d90c952 | 11074 | intel_ring_emit(ring, pf | pipesrc); |
e7d841ca CW |
11075 | |
11076 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 11077 | __intel_ring_advance(ring); |
83d4092b | 11078 | return 0; |
8c9f3aaf JB |
11079 | } |
11080 | ||
11081 | static int intel_gen6_queue_flip(struct drm_device *dev, | |
11082 | struct drm_crtc *crtc, | |
11083 | struct drm_framebuffer *fb, | |
ed8d1975 | 11084 | struct drm_i915_gem_object *obj, |
a4872ba6 | 11085 | struct intel_engine_cs *ring, |
ed8d1975 | 11086 | uint32_t flags) |
8c9f3aaf JB |
11087 | { |
11088 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11089 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11090 | uint32_t pf, pipesrc; | |
11091 | int ret; | |
11092 | ||
6d90c952 | 11093 | ret = intel_ring_begin(ring, 4); |
8c9f3aaf | 11094 | if (ret) |
4fa62c89 | 11095 | return ret; |
8c9f3aaf | 11096 | |
6d90c952 DV |
11097 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
11098 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
11099 | intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode); | |
75f7f3ec | 11100 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
8c9f3aaf | 11101 | |
dc257cf1 DV |
11102 | /* Contrary to the suggestions in the documentation, |
11103 | * "Enable Panel Fitter" does not seem to be required when page | |
11104 | * flipping with a non-native mode, and worse causes a normal | |
11105 | * modeset to fail. | |
11106 | * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; | |
11107 | */ | |
11108 | pf = 0; | |
8c9f3aaf | 11109 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; |
6d90c952 | 11110 | intel_ring_emit(ring, pf | pipesrc); |
e7d841ca CW |
11111 | |
11112 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 11113 | __intel_ring_advance(ring); |
83d4092b | 11114 | return 0; |
8c9f3aaf JB |
11115 | } |
11116 | ||
7c9017e5 JB |
11117 | static int intel_gen7_queue_flip(struct drm_device *dev, |
11118 | struct drm_crtc *crtc, | |
11119 | struct drm_framebuffer *fb, | |
ed8d1975 | 11120 | struct drm_i915_gem_object *obj, |
a4872ba6 | 11121 | struct intel_engine_cs *ring, |
ed8d1975 | 11122 | uint32_t flags) |
7c9017e5 | 11123 | { |
7c9017e5 | 11124 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
cb05d8de | 11125 | uint32_t plane_bit = 0; |
ffe74d75 CW |
11126 | int len, ret; |
11127 | ||
eba905b2 | 11128 | switch (intel_crtc->plane) { |
cb05d8de DV |
11129 | case PLANE_A: |
11130 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A; | |
11131 | break; | |
11132 | case PLANE_B: | |
11133 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B; | |
11134 | break; | |
11135 | case PLANE_C: | |
11136 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C; | |
11137 | break; | |
11138 | default: | |
11139 | WARN_ONCE(1, "unknown plane in flip command\n"); | |
4fa62c89 | 11140 | return -ENODEV; |
cb05d8de DV |
11141 | } |
11142 | ||
ffe74d75 | 11143 | len = 4; |
f476828a | 11144 | if (ring->id == RCS) { |
ffe74d75 | 11145 | len += 6; |
f476828a DL |
11146 | /* |
11147 | * On Gen 8, SRM is now taking an extra dword to accommodate | |
11148 | * 48bits addresses, and we need a NOOP for the batch size to | |
11149 | * stay even. | |
11150 | */ | |
11151 | if (IS_GEN8(dev)) | |
11152 | len += 2; | |
11153 | } | |
ffe74d75 | 11154 | |
f66fab8e VS |
11155 | /* |
11156 | * BSpec MI_DISPLAY_FLIP for IVB: | |
11157 | * "The full packet must be contained within the same cache line." | |
11158 | * | |
11159 | * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same | |
11160 | * cacheline, if we ever start emitting more commands before | |
11161 | * the MI_DISPLAY_FLIP we may need to first emit everything else, | |
11162 | * then do the cacheline alignment, and finally emit the | |
11163 | * MI_DISPLAY_FLIP. | |
11164 | */ | |
11165 | ret = intel_ring_cacheline_align(ring); | |
11166 | if (ret) | |
4fa62c89 | 11167 | return ret; |
f66fab8e | 11168 | |
ffe74d75 | 11169 | ret = intel_ring_begin(ring, len); |
7c9017e5 | 11170 | if (ret) |
4fa62c89 | 11171 | return ret; |
7c9017e5 | 11172 | |
ffe74d75 CW |
11173 | /* Unmask the flip-done completion message. Note that the bspec says that |
11174 | * we should do this for both the BCS and RCS, and that we must not unmask | |
11175 | * more than one flip event at any time (or ensure that one flip message | |
11176 | * can be sent by waiting for flip-done prior to queueing new flips). | |
11177 | * Experimentation says that BCS works despite DERRMR masking all | |
11178 | * flip-done completion events and that unmasking all planes at once | |
11179 | * for the RCS also doesn't appear to drop events. Setting the DERRMR | |
11180 | * to zero does lead to lockups within MI_DISPLAY_FLIP. | |
11181 | */ | |
11182 | if (ring->id == RCS) { | |
11183 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
11184 | intel_ring_emit(ring, DERRMR); | |
11185 | intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE | | |
11186 | DERRMR_PIPEB_PRI_FLIP_DONE | | |
11187 | DERRMR_PIPEC_PRI_FLIP_DONE)); | |
f476828a DL |
11188 | if (IS_GEN8(dev)) |
11189 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) | | |
11190 | MI_SRM_LRM_GLOBAL_GTT); | |
11191 | else | |
11192 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) | | |
11193 | MI_SRM_LRM_GLOBAL_GTT); | |
ffe74d75 CW |
11194 | intel_ring_emit(ring, DERRMR); |
11195 | intel_ring_emit(ring, ring->scratch.gtt_offset + 256); | |
f476828a DL |
11196 | if (IS_GEN8(dev)) { |
11197 | intel_ring_emit(ring, 0); | |
11198 | intel_ring_emit(ring, MI_NOOP); | |
11199 | } | |
ffe74d75 CW |
11200 | } |
11201 | ||
cb05d8de | 11202 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit); |
01f2c773 | 11203 | intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode)); |
75f7f3ec | 11204 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
7c9017e5 | 11205 | intel_ring_emit(ring, (MI_NOOP)); |
e7d841ca CW |
11206 | |
11207 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 11208 | __intel_ring_advance(ring); |
83d4092b | 11209 | return 0; |
7c9017e5 JB |
11210 | } |
11211 | ||
84c33a64 SG |
11212 | static bool use_mmio_flip(struct intel_engine_cs *ring, |
11213 | struct drm_i915_gem_object *obj) | |
11214 | { | |
11215 | /* | |
11216 | * This is not being used for older platforms, because | |
11217 | * non-availability of flip done interrupt forces us to use | |
11218 | * CS flips. Older platforms derive flip done using some clever | |
11219 | * tricks involving the flip_pending status bits and vblank irqs. | |
11220 | * So using MMIO flips there would disrupt this mechanism. | |
11221 | */ | |
11222 | ||
8e09bf83 CW |
11223 | if (ring == NULL) |
11224 | return true; | |
11225 | ||
84c33a64 SG |
11226 | if (INTEL_INFO(ring->dev)->gen < 5) |
11227 | return false; | |
11228 | ||
11229 | if (i915.use_mmio_flip < 0) | |
11230 | return false; | |
11231 | else if (i915.use_mmio_flip > 0) | |
11232 | return true; | |
14bf993e OM |
11233 | else if (i915.enable_execlists) |
11234 | return true; | |
84c33a64 | 11235 | else |
b4716185 | 11236 | return ring != i915_gem_request_get_ring(obj->last_write_req); |
84c33a64 SG |
11237 | } |
11238 | ||
ff944564 DL |
11239 | static void skl_do_mmio_flip(struct intel_crtc *intel_crtc) |
11240 | { | |
11241 | struct drm_device *dev = intel_crtc->base.dev; | |
11242 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11243 | struct drm_framebuffer *fb = intel_crtc->base.primary->fb; | |
ff944564 DL |
11244 | const enum pipe pipe = intel_crtc->pipe; |
11245 | u32 ctl, stride; | |
11246 | ||
11247 | ctl = I915_READ(PLANE_CTL(pipe, 0)); | |
11248 | ctl &= ~PLANE_CTL_TILED_MASK; | |
2ebef630 TU |
11249 | switch (fb->modifier[0]) { |
11250 | case DRM_FORMAT_MOD_NONE: | |
11251 | break; | |
11252 | case I915_FORMAT_MOD_X_TILED: | |
ff944564 | 11253 | ctl |= PLANE_CTL_TILED_X; |
2ebef630 TU |
11254 | break; |
11255 | case I915_FORMAT_MOD_Y_TILED: | |
11256 | ctl |= PLANE_CTL_TILED_Y; | |
11257 | break; | |
11258 | case I915_FORMAT_MOD_Yf_TILED: | |
11259 | ctl |= PLANE_CTL_TILED_YF; | |
11260 | break; | |
11261 | default: | |
11262 | MISSING_CASE(fb->modifier[0]); | |
11263 | } | |
ff944564 DL |
11264 | |
11265 | /* | |
11266 | * The stride is either expressed as a multiple of 64 bytes chunks for | |
11267 | * linear buffers or in number of tiles for tiled buffers. | |
11268 | */ | |
2ebef630 TU |
11269 | stride = fb->pitches[0] / |
11270 | intel_fb_stride_alignment(dev, fb->modifier[0], | |
11271 | fb->pixel_format); | |
ff944564 DL |
11272 | |
11273 | /* | |
11274 | * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on | |
11275 | * PLANE_SURF updates, the update is then guaranteed to be atomic. | |
11276 | */ | |
11277 | I915_WRITE(PLANE_CTL(pipe, 0), ctl); | |
11278 | I915_WRITE(PLANE_STRIDE(pipe, 0), stride); | |
11279 | ||
11280 | I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset); | |
11281 | POSTING_READ(PLANE_SURF(pipe, 0)); | |
11282 | } | |
11283 | ||
11284 | static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc) | |
84c33a64 SG |
11285 | { |
11286 | struct drm_device *dev = intel_crtc->base.dev; | |
11287 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11288 | struct intel_framebuffer *intel_fb = | |
11289 | to_intel_framebuffer(intel_crtc->base.primary->fb); | |
11290 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
11291 | u32 dspcntr; | |
11292 | u32 reg; | |
11293 | ||
84c33a64 SG |
11294 | reg = DSPCNTR(intel_crtc->plane); |
11295 | dspcntr = I915_READ(reg); | |
11296 | ||
c5d97472 DL |
11297 | if (obj->tiling_mode != I915_TILING_NONE) |
11298 | dspcntr |= DISPPLANE_TILED; | |
11299 | else | |
11300 | dspcntr &= ~DISPPLANE_TILED; | |
11301 | ||
84c33a64 SG |
11302 | I915_WRITE(reg, dspcntr); |
11303 | ||
11304 | I915_WRITE(DSPSURF(intel_crtc->plane), | |
11305 | intel_crtc->unpin_work->gtt_offset); | |
11306 | POSTING_READ(DSPSURF(intel_crtc->plane)); | |
84c33a64 | 11307 | |
ff944564 DL |
11308 | } |
11309 | ||
11310 | /* | |
11311 | * XXX: This is the temporary way to update the plane registers until we get | |
11312 | * around to using the usual plane update functions for MMIO flips | |
11313 | */ | |
11314 | static void intel_do_mmio_flip(struct intel_crtc *intel_crtc) | |
11315 | { | |
11316 | struct drm_device *dev = intel_crtc->base.dev; | |
11317 | bool atomic_update; | |
11318 | u32 start_vbl_count; | |
11319 | ||
11320 | intel_mark_page_flip_active(intel_crtc); | |
11321 | ||
11322 | atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count); | |
11323 | ||
11324 | if (INTEL_INFO(dev)->gen >= 9) | |
11325 | skl_do_mmio_flip(intel_crtc); | |
11326 | else | |
11327 | /* use_mmio_flip() retricts MMIO flips to ilk+ */ | |
11328 | ilk_do_mmio_flip(intel_crtc); | |
11329 | ||
9362c7c5 ACO |
11330 | if (atomic_update) |
11331 | intel_pipe_update_end(intel_crtc, start_vbl_count); | |
84c33a64 SG |
11332 | } |
11333 | ||
9362c7c5 | 11334 | static void intel_mmio_flip_work_func(struct work_struct *work) |
84c33a64 | 11335 | { |
b2cfe0ab CW |
11336 | struct intel_mmio_flip *mmio_flip = |
11337 | container_of(work, struct intel_mmio_flip, work); | |
84c33a64 | 11338 | |
eed29a5b DV |
11339 | if (mmio_flip->req) |
11340 | WARN_ON(__i915_wait_request(mmio_flip->req, | |
b2cfe0ab | 11341 | mmio_flip->crtc->reset_counter, |
bcafc4e3 CW |
11342 | false, NULL, |
11343 | &mmio_flip->i915->rps.mmioflips)); | |
84c33a64 | 11344 | |
b2cfe0ab CW |
11345 | intel_do_mmio_flip(mmio_flip->crtc); |
11346 | ||
eed29a5b | 11347 | i915_gem_request_unreference__unlocked(mmio_flip->req); |
b2cfe0ab | 11348 | kfree(mmio_flip); |
84c33a64 SG |
11349 | } |
11350 | ||
11351 | static int intel_queue_mmio_flip(struct drm_device *dev, | |
11352 | struct drm_crtc *crtc, | |
11353 | struct drm_framebuffer *fb, | |
11354 | struct drm_i915_gem_object *obj, | |
11355 | struct intel_engine_cs *ring, | |
11356 | uint32_t flags) | |
11357 | { | |
b2cfe0ab CW |
11358 | struct intel_mmio_flip *mmio_flip; |
11359 | ||
11360 | mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL); | |
11361 | if (mmio_flip == NULL) | |
11362 | return -ENOMEM; | |
84c33a64 | 11363 | |
bcafc4e3 | 11364 | mmio_flip->i915 = to_i915(dev); |
eed29a5b | 11365 | mmio_flip->req = i915_gem_request_reference(obj->last_write_req); |
b2cfe0ab | 11366 | mmio_flip->crtc = to_intel_crtc(crtc); |
536f5b5e | 11367 | |
b2cfe0ab CW |
11368 | INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func); |
11369 | schedule_work(&mmio_flip->work); | |
84c33a64 | 11370 | |
84c33a64 SG |
11371 | return 0; |
11372 | } | |
11373 | ||
8c9f3aaf JB |
11374 | static int intel_default_queue_flip(struct drm_device *dev, |
11375 | struct drm_crtc *crtc, | |
11376 | struct drm_framebuffer *fb, | |
ed8d1975 | 11377 | struct drm_i915_gem_object *obj, |
a4872ba6 | 11378 | struct intel_engine_cs *ring, |
ed8d1975 | 11379 | uint32_t flags) |
8c9f3aaf JB |
11380 | { |
11381 | return -ENODEV; | |
11382 | } | |
11383 | ||
d6bbafa1 CW |
11384 | static bool __intel_pageflip_stall_check(struct drm_device *dev, |
11385 | struct drm_crtc *crtc) | |
11386 | { | |
11387 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11388 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11389 | struct intel_unpin_work *work = intel_crtc->unpin_work; | |
11390 | u32 addr; | |
11391 | ||
11392 | if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE) | |
11393 | return true; | |
11394 | ||
11395 | if (!work->enable_stall_check) | |
11396 | return false; | |
11397 | ||
11398 | if (work->flip_ready_vblank == 0) { | |
3a8a946e DV |
11399 | if (work->flip_queued_req && |
11400 | !i915_gem_request_completed(work->flip_queued_req, true)) | |
d6bbafa1 CW |
11401 | return false; |
11402 | ||
1e3feefd | 11403 | work->flip_ready_vblank = drm_crtc_vblank_count(crtc); |
d6bbafa1 CW |
11404 | } |
11405 | ||
1e3feefd | 11406 | if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3) |
d6bbafa1 CW |
11407 | return false; |
11408 | ||
11409 | /* Potential stall - if we see that the flip has happened, | |
11410 | * assume a missed interrupt. */ | |
11411 | if (INTEL_INFO(dev)->gen >= 4) | |
11412 | addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane))); | |
11413 | else | |
11414 | addr = I915_READ(DSPADDR(intel_crtc->plane)); | |
11415 | ||
11416 | /* There is a potential issue here with a false positive after a flip | |
11417 | * to the same address. We could address this by checking for a | |
11418 | * non-incrementing frame counter. | |
11419 | */ | |
11420 | return addr == work->gtt_offset; | |
11421 | } | |
11422 | ||
11423 | void intel_check_page_flip(struct drm_device *dev, int pipe) | |
11424 | { | |
11425 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11426 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
11427 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6ad790c0 | 11428 | struct intel_unpin_work *work; |
f326038a | 11429 | |
6c51d46f | 11430 | WARN_ON(!in_interrupt()); |
d6bbafa1 CW |
11431 | |
11432 | if (crtc == NULL) | |
11433 | return; | |
11434 | ||
f326038a | 11435 | spin_lock(&dev->event_lock); |
6ad790c0 CW |
11436 | work = intel_crtc->unpin_work; |
11437 | if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) { | |
d6bbafa1 | 11438 | WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n", |
6ad790c0 | 11439 | work->flip_queued_vblank, drm_vblank_count(dev, pipe)); |
d6bbafa1 | 11440 | page_flip_completed(intel_crtc); |
6ad790c0 | 11441 | work = NULL; |
d6bbafa1 | 11442 | } |
6ad790c0 CW |
11443 | if (work != NULL && |
11444 | drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1) | |
11445 | intel_queue_rps_boost_for_request(dev, work->flip_queued_req); | |
f326038a | 11446 | spin_unlock(&dev->event_lock); |
d6bbafa1 CW |
11447 | } |
11448 | ||
6b95a207 KH |
11449 | static int intel_crtc_page_flip(struct drm_crtc *crtc, |
11450 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
11451 | struct drm_pending_vblank_event *event, |
11452 | uint32_t page_flip_flags) | |
6b95a207 KH |
11453 | { |
11454 | struct drm_device *dev = crtc->dev; | |
11455 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f4510a27 | 11456 | struct drm_framebuffer *old_fb = crtc->primary->fb; |
2ff8fde1 | 11457 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
6b95a207 | 11458 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
455a6808 | 11459 | struct drm_plane *primary = crtc->primary; |
a071fa00 | 11460 | enum pipe pipe = intel_crtc->pipe; |
6b95a207 | 11461 | struct intel_unpin_work *work; |
a4872ba6 | 11462 | struct intel_engine_cs *ring; |
cf5d8a46 | 11463 | bool mmio_flip; |
52e68630 | 11464 | int ret; |
6b95a207 | 11465 | |
2ff8fde1 MR |
11466 | /* |
11467 | * drm_mode_page_flip_ioctl() should already catch this, but double | |
11468 | * check to be safe. In the future we may enable pageflipping from | |
11469 | * a disabled primary plane. | |
11470 | */ | |
11471 | if (WARN_ON(intel_fb_obj(old_fb) == NULL)) | |
11472 | return -EBUSY; | |
11473 | ||
e6a595d2 | 11474 | /* Can't change pixel format via MI display flips. */ |
f4510a27 | 11475 | if (fb->pixel_format != crtc->primary->fb->pixel_format) |
e6a595d2 VS |
11476 | return -EINVAL; |
11477 | ||
11478 | /* | |
11479 | * TILEOFF/LINOFF registers can't be changed via MI display flips. | |
11480 | * Note that pitch changes could also affect these register. | |
11481 | */ | |
11482 | if (INTEL_INFO(dev)->gen > 3 && | |
f4510a27 MR |
11483 | (fb->offsets[0] != crtc->primary->fb->offsets[0] || |
11484 | fb->pitches[0] != crtc->primary->fb->pitches[0])) | |
e6a595d2 VS |
11485 | return -EINVAL; |
11486 | ||
f900db47 CW |
11487 | if (i915_terminally_wedged(&dev_priv->gpu_error)) |
11488 | goto out_hang; | |
11489 | ||
b14c5679 | 11490 | work = kzalloc(sizeof(*work), GFP_KERNEL); |
6b95a207 KH |
11491 | if (work == NULL) |
11492 | return -ENOMEM; | |
11493 | ||
6b95a207 | 11494 | work->event = event; |
b4a98e57 | 11495 | work->crtc = crtc; |
ab8d6675 | 11496 | work->old_fb = old_fb; |
6b95a207 KH |
11497 | INIT_WORK(&work->work, intel_unpin_work_fn); |
11498 | ||
87b6b101 | 11499 | ret = drm_crtc_vblank_get(crtc); |
7317c75e JB |
11500 | if (ret) |
11501 | goto free_work; | |
11502 | ||
6b95a207 | 11503 | /* We borrow the event spin lock for protecting unpin_work */ |
5e2d7afc | 11504 | spin_lock_irq(&dev->event_lock); |
6b95a207 | 11505 | if (intel_crtc->unpin_work) { |
d6bbafa1 CW |
11506 | /* Before declaring the flip queue wedged, check if |
11507 | * the hardware completed the operation behind our backs. | |
11508 | */ | |
11509 | if (__intel_pageflip_stall_check(dev, crtc)) { | |
11510 | DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n"); | |
11511 | page_flip_completed(intel_crtc); | |
11512 | } else { | |
11513 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); | |
5e2d7afc | 11514 | spin_unlock_irq(&dev->event_lock); |
468f0b44 | 11515 | |
d6bbafa1 CW |
11516 | drm_crtc_vblank_put(crtc); |
11517 | kfree(work); | |
11518 | return -EBUSY; | |
11519 | } | |
6b95a207 KH |
11520 | } |
11521 | intel_crtc->unpin_work = work; | |
5e2d7afc | 11522 | spin_unlock_irq(&dev->event_lock); |
6b95a207 | 11523 | |
b4a98e57 CW |
11524 | if (atomic_read(&intel_crtc->unpin_work_count) >= 2) |
11525 | flush_workqueue(dev_priv->wq); | |
11526 | ||
75dfca80 | 11527 | /* Reference the objects for the scheduled work. */ |
ab8d6675 | 11528 | drm_framebuffer_reference(work->old_fb); |
05394f39 | 11529 | drm_gem_object_reference(&obj->base); |
6b95a207 | 11530 | |
f4510a27 | 11531 | crtc->primary->fb = fb; |
afd65eb4 | 11532 | update_state_fb(crtc->primary); |
1ed1f968 | 11533 | |
e1f99ce6 | 11534 | work->pending_flip_obj = obj; |
e1f99ce6 | 11535 | |
89ed88ba CW |
11536 | ret = i915_mutex_lock_interruptible(dev); |
11537 | if (ret) | |
11538 | goto cleanup; | |
11539 | ||
b4a98e57 | 11540 | atomic_inc(&intel_crtc->unpin_work_count); |
10d83730 | 11541 | intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
e1f99ce6 | 11542 | |
75f7f3ec | 11543 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) |
a071fa00 | 11544 | work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1; |
75f7f3ec | 11545 | |
4fa62c89 VS |
11546 | if (IS_VALLEYVIEW(dev)) { |
11547 | ring = &dev_priv->ring[BCS]; | |
ab8d6675 | 11548 | if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode) |
8e09bf83 CW |
11549 | /* vlv: DISPLAY_FLIP fails to change tiling */ |
11550 | ring = NULL; | |
48bf5b2d | 11551 | } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) { |
2a92d5bc | 11552 | ring = &dev_priv->ring[BCS]; |
4fa62c89 | 11553 | } else if (INTEL_INFO(dev)->gen >= 7) { |
b4716185 | 11554 | ring = i915_gem_request_get_ring(obj->last_write_req); |
4fa62c89 VS |
11555 | if (ring == NULL || ring->id != RCS) |
11556 | ring = &dev_priv->ring[BCS]; | |
11557 | } else { | |
11558 | ring = &dev_priv->ring[RCS]; | |
11559 | } | |
11560 | ||
cf5d8a46 CW |
11561 | mmio_flip = use_mmio_flip(ring, obj); |
11562 | ||
11563 | /* When using CS flips, we want to emit semaphores between rings. | |
11564 | * However, when using mmio flips we will create a task to do the | |
11565 | * synchronisation, so all we want here is to pin the framebuffer | |
11566 | * into the display plane and skip any waits. | |
11567 | */ | |
82bc3b2d | 11568 | ret = intel_pin_and_fence_fb_obj(crtc->primary, fb, |
cf5d8a46 | 11569 | crtc->primary->state, |
b4716185 | 11570 | mmio_flip ? i915_gem_request_get_ring(obj->last_write_req) : ring); |
8c9f3aaf JB |
11571 | if (ret) |
11572 | goto cleanup_pending; | |
6b95a207 | 11573 | |
121920fa TU |
11574 | work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj) |
11575 | + intel_crtc->dspaddr_offset; | |
4fa62c89 | 11576 | |
cf5d8a46 | 11577 | if (mmio_flip) { |
84c33a64 SG |
11578 | ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring, |
11579 | page_flip_flags); | |
d6bbafa1 CW |
11580 | if (ret) |
11581 | goto cleanup_unpin; | |
11582 | ||
f06cc1b9 JH |
11583 | i915_gem_request_assign(&work->flip_queued_req, |
11584 | obj->last_write_req); | |
d6bbafa1 | 11585 | } else { |
d94b5030 CW |
11586 | if (obj->last_write_req) { |
11587 | ret = i915_gem_check_olr(obj->last_write_req); | |
11588 | if (ret) | |
11589 | goto cleanup_unpin; | |
11590 | } | |
11591 | ||
84c33a64 | 11592 | ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring, |
d6bbafa1 CW |
11593 | page_flip_flags); |
11594 | if (ret) | |
11595 | goto cleanup_unpin; | |
11596 | ||
f06cc1b9 JH |
11597 | i915_gem_request_assign(&work->flip_queued_req, |
11598 | intel_ring_get_request(ring)); | |
d6bbafa1 CW |
11599 | } |
11600 | ||
1e3feefd | 11601 | work->flip_queued_vblank = drm_crtc_vblank_count(crtc); |
d6bbafa1 | 11602 | work->enable_stall_check = true; |
4fa62c89 | 11603 | |
ab8d6675 | 11604 | i915_gem_track_fb(intel_fb_obj(work->old_fb), obj, |
a071fa00 DV |
11605 | INTEL_FRONTBUFFER_PRIMARY(pipe)); |
11606 | ||
7ff0ebcc | 11607 | intel_fbc_disable(dev); |
f99d7069 | 11608 | intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe)); |
6b95a207 KH |
11609 | mutex_unlock(&dev->struct_mutex); |
11610 | ||
e5510fac JB |
11611 | trace_i915_flip_request(intel_crtc->plane, obj); |
11612 | ||
6b95a207 | 11613 | return 0; |
96b099fd | 11614 | |
4fa62c89 | 11615 | cleanup_unpin: |
82bc3b2d | 11616 | intel_unpin_fb_obj(fb, crtc->primary->state); |
8c9f3aaf | 11617 | cleanup_pending: |
b4a98e57 | 11618 | atomic_dec(&intel_crtc->unpin_work_count); |
89ed88ba CW |
11619 | mutex_unlock(&dev->struct_mutex); |
11620 | cleanup: | |
f4510a27 | 11621 | crtc->primary->fb = old_fb; |
afd65eb4 | 11622 | update_state_fb(crtc->primary); |
89ed88ba CW |
11623 | |
11624 | drm_gem_object_unreference_unlocked(&obj->base); | |
ab8d6675 | 11625 | drm_framebuffer_unreference(work->old_fb); |
96b099fd | 11626 | |
5e2d7afc | 11627 | spin_lock_irq(&dev->event_lock); |
96b099fd | 11628 | intel_crtc->unpin_work = NULL; |
5e2d7afc | 11629 | spin_unlock_irq(&dev->event_lock); |
96b099fd | 11630 | |
87b6b101 | 11631 | drm_crtc_vblank_put(crtc); |
7317c75e | 11632 | free_work: |
96b099fd CW |
11633 | kfree(work); |
11634 | ||
f900db47 CW |
11635 | if (ret == -EIO) { |
11636 | out_hang: | |
53a366b9 | 11637 | ret = intel_plane_restore(primary); |
f0d3dad3 | 11638 | if (ret == 0 && event) { |
5e2d7afc | 11639 | spin_lock_irq(&dev->event_lock); |
a071fa00 | 11640 | drm_send_vblank_event(dev, pipe, event); |
5e2d7afc | 11641 | spin_unlock_irq(&dev->event_lock); |
f0d3dad3 | 11642 | } |
f900db47 | 11643 | } |
96b099fd | 11644 | return ret; |
6b95a207 KH |
11645 | } |
11646 | ||
65b38e0d | 11647 | static const struct drm_crtc_helper_funcs intel_helper_funcs = { |
f6e5b160 CW |
11648 | .mode_set_base_atomic = intel_pipe_set_base_atomic, |
11649 | .load_lut = intel_crtc_load_lut, | |
ea2c67bb MR |
11650 | .atomic_begin = intel_begin_crtc_commit, |
11651 | .atomic_flush = intel_finish_crtc_commit, | |
f6e5b160 CW |
11652 | }; |
11653 | ||
d29b2f9d ACO |
11654 | /* Transitional helper to copy current connector/encoder state to |
11655 | * connector->state. This is needed so that code that is partially | |
11656 | * converted to atomic does the right thing. | |
11657 | */ | |
11658 | static void intel_modeset_update_connector_atomic_state(struct drm_device *dev) | |
11659 | { | |
11660 | struct intel_connector *connector; | |
11661 | ||
11662 | for_each_intel_connector(dev, connector) { | |
11663 | if (connector->base.encoder) { | |
11664 | connector->base.state->best_encoder = | |
11665 | connector->base.encoder; | |
11666 | connector->base.state->crtc = | |
11667 | connector->base.encoder->crtc; | |
11668 | } else { | |
11669 | connector->base.state->best_encoder = NULL; | |
11670 | connector->base.state->crtc = NULL; | |
11671 | } | |
11672 | } | |
11673 | } | |
11674 | ||
050f7aeb | 11675 | static void |
eba905b2 | 11676 | connected_sink_compute_bpp(struct intel_connector *connector, |
5cec258b | 11677 | struct intel_crtc_state *pipe_config) |
050f7aeb DV |
11678 | { |
11679 | int bpp = pipe_config->pipe_bpp; | |
11680 | ||
11681 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n", | |
11682 | connector->base.base.id, | |
c23cc417 | 11683 | connector->base.name); |
050f7aeb DV |
11684 | |
11685 | /* Don't use an invalid EDID bpc value */ | |
11686 | if (connector->base.display_info.bpc && | |
11687 | connector->base.display_info.bpc * 3 < bpp) { | |
11688 | DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n", | |
11689 | bpp, connector->base.display_info.bpc*3); | |
11690 | pipe_config->pipe_bpp = connector->base.display_info.bpc*3; | |
11691 | } | |
11692 | ||
11693 | /* Clamp bpp to 8 on screens without EDID 1.4 */ | |
11694 | if (connector->base.display_info.bpc == 0 && bpp > 24) { | |
11695 | DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n", | |
11696 | bpp); | |
11697 | pipe_config->pipe_bpp = 24; | |
11698 | } | |
11699 | } | |
11700 | ||
4e53c2e0 | 11701 | static int |
050f7aeb | 11702 | compute_baseline_pipe_bpp(struct intel_crtc *crtc, |
5cec258b | 11703 | struct intel_crtc_state *pipe_config) |
4e53c2e0 | 11704 | { |
050f7aeb | 11705 | struct drm_device *dev = crtc->base.dev; |
1486017f | 11706 | struct drm_atomic_state *state; |
da3ced29 ACO |
11707 | struct drm_connector *connector; |
11708 | struct drm_connector_state *connector_state; | |
1486017f | 11709 | int bpp, i; |
4e53c2e0 | 11710 | |
d328c9d7 | 11711 | if ((IS_G4X(dev) || IS_VALLEYVIEW(dev))) |
4e53c2e0 | 11712 | bpp = 10*3; |
d328c9d7 DV |
11713 | else if (INTEL_INFO(dev)->gen >= 5) |
11714 | bpp = 12*3; | |
11715 | else | |
11716 | bpp = 8*3; | |
11717 | ||
4e53c2e0 | 11718 | |
4e53c2e0 DV |
11719 | pipe_config->pipe_bpp = bpp; |
11720 | ||
1486017f ACO |
11721 | state = pipe_config->base.state; |
11722 | ||
4e53c2e0 | 11723 | /* Clamp display bpp to EDID value */ |
da3ced29 ACO |
11724 | for_each_connector_in_state(state, connector, connector_state, i) { |
11725 | if (connector_state->crtc != &crtc->base) | |
4e53c2e0 DV |
11726 | continue; |
11727 | ||
da3ced29 ACO |
11728 | connected_sink_compute_bpp(to_intel_connector(connector), |
11729 | pipe_config); | |
4e53c2e0 DV |
11730 | } |
11731 | ||
11732 | return bpp; | |
11733 | } | |
11734 | ||
644db711 DV |
11735 | static void intel_dump_crtc_timings(const struct drm_display_mode *mode) |
11736 | { | |
11737 | DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, " | |
11738 | "type: 0x%x flags: 0x%x\n", | |
1342830c | 11739 | mode->crtc_clock, |
644db711 DV |
11740 | mode->crtc_hdisplay, mode->crtc_hsync_start, |
11741 | mode->crtc_hsync_end, mode->crtc_htotal, | |
11742 | mode->crtc_vdisplay, mode->crtc_vsync_start, | |
11743 | mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags); | |
11744 | } | |
11745 | ||
c0b03411 | 11746 | static void intel_dump_pipe_config(struct intel_crtc *crtc, |
5cec258b | 11747 | struct intel_crtc_state *pipe_config, |
c0b03411 DV |
11748 | const char *context) |
11749 | { | |
6a60cd87 CK |
11750 | struct drm_device *dev = crtc->base.dev; |
11751 | struct drm_plane *plane; | |
11752 | struct intel_plane *intel_plane; | |
11753 | struct intel_plane_state *state; | |
11754 | struct drm_framebuffer *fb; | |
11755 | ||
11756 | DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id, | |
11757 | context, pipe_config, pipe_name(crtc->pipe)); | |
c0b03411 DV |
11758 | |
11759 | DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder)); | |
11760 | DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n", | |
11761 | pipe_config->pipe_bpp, pipe_config->dither); | |
11762 | DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", | |
11763 | pipe_config->has_pch_encoder, | |
11764 | pipe_config->fdi_lanes, | |
11765 | pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n, | |
11766 | pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n, | |
11767 | pipe_config->fdi_m_n.tu); | |
eb14cb74 VS |
11768 | DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", |
11769 | pipe_config->has_dp_encoder, | |
11770 | pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n, | |
11771 | pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n, | |
11772 | pipe_config->dp_m_n.tu); | |
b95af8be VK |
11773 | |
11774 | DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n", | |
11775 | pipe_config->has_dp_encoder, | |
11776 | pipe_config->dp_m2_n2.gmch_m, | |
11777 | pipe_config->dp_m2_n2.gmch_n, | |
11778 | pipe_config->dp_m2_n2.link_m, | |
11779 | pipe_config->dp_m2_n2.link_n, | |
11780 | pipe_config->dp_m2_n2.tu); | |
11781 | ||
55072d19 DV |
11782 | DRM_DEBUG_KMS("audio: %i, infoframes: %i\n", |
11783 | pipe_config->has_audio, | |
11784 | pipe_config->has_infoframe); | |
11785 | ||
c0b03411 | 11786 | DRM_DEBUG_KMS("requested mode:\n"); |
2d112de7 | 11787 | drm_mode_debug_printmodeline(&pipe_config->base.mode); |
c0b03411 | 11788 | DRM_DEBUG_KMS("adjusted mode:\n"); |
2d112de7 ACO |
11789 | drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode); |
11790 | intel_dump_crtc_timings(&pipe_config->base.adjusted_mode); | |
d71b8d4a | 11791 | DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock); |
37327abd VS |
11792 | DRM_DEBUG_KMS("pipe src size: %dx%d\n", |
11793 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); | |
0ec463d3 TU |
11794 | DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n", |
11795 | crtc->num_scalers, | |
11796 | pipe_config->scaler_state.scaler_users, | |
11797 | pipe_config->scaler_state.scaler_id); | |
c0b03411 DV |
11798 | DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", |
11799 | pipe_config->gmch_pfit.control, | |
11800 | pipe_config->gmch_pfit.pgm_ratios, | |
11801 | pipe_config->gmch_pfit.lvds_border_bits); | |
fd4daa9c | 11802 | DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n", |
c0b03411 | 11803 | pipe_config->pch_pfit.pos, |
fd4daa9c CW |
11804 | pipe_config->pch_pfit.size, |
11805 | pipe_config->pch_pfit.enabled ? "enabled" : "disabled"); | |
42db64ef | 11806 | DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled); |
cf532bb2 | 11807 | DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide); |
6a60cd87 | 11808 | |
415ff0f6 TU |
11809 | if (IS_BROXTON(dev)) { |
11810 | DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, " | |
11811 | "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, " | |
11812 | "pll6: 0x%x, pll8: 0x%x, pcsdw12: 0x%x\n", | |
11813 | pipe_config->ddi_pll_sel, | |
11814 | pipe_config->dpll_hw_state.ebb0, | |
11815 | pipe_config->dpll_hw_state.pll0, | |
11816 | pipe_config->dpll_hw_state.pll1, | |
11817 | pipe_config->dpll_hw_state.pll2, | |
11818 | pipe_config->dpll_hw_state.pll3, | |
11819 | pipe_config->dpll_hw_state.pll6, | |
11820 | pipe_config->dpll_hw_state.pll8, | |
11821 | pipe_config->dpll_hw_state.pcsdw12); | |
11822 | } else if (IS_SKYLAKE(dev)) { | |
11823 | DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: " | |
11824 | "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n", | |
11825 | pipe_config->ddi_pll_sel, | |
11826 | pipe_config->dpll_hw_state.ctrl1, | |
11827 | pipe_config->dpll_hw_state.cfgcr1, | |
11828 | pipe_config->dpll_hw_state.cfgcr2); | |
11829 | } else if (HAS_DDI(dev)) { | |
11830 | DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x\n", | |
11831 | pipe_config->ddi_pll_sel, | |
11832 | pipe_config->dpll_hw_state.wrpll); | |
11833 | } else { | |
11834 | DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, " | |
11835 | "fp0: 0x%x, fp1: 0x%x\n", | |
11836 | pipe_config->dpll_hw_state.dpll, | |
11837 | pipe_config->dpll_hw_state.dpll_md, | |
11838 | pipe_config->dpll_hw_state.fp0, | |
11839 | pipe_config->dpll_hw_state.fp1); | |
11840 | } | |
11841 | ||
6a60cd87 CK |
11842 | DRM_DEBUG_KMS("planes on this crtc\n"); |
11843 | list_for_each_entry(plane, &dev->mode_config.plane_list, head) { | |
11844 | intel_plane = to_intel_plane(plane); | |
11845 | if (intel_plane->pipe != crtc->pipe) | |
11846 | continue; | |
11847 | ||
11848 | state = to_intel_plane_state(plane->state); | |
11849 | fb = state->base.fb; | |
11850 | if (!fb) { | |
11851 | DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d " | |
11852 | "disabled, scaler_id = %d\n", | |
11853 | plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD", | |
11854 | plane->base.id, intel_plane->pipe, | |
11855 | (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1, | |
11856 | drm_plane_index(plane), state->scaler_id); | |
11857 | continue; | |
11858 | } | |
11859 | ||
11860 | DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled", | |
11861 | plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD", | |
11862 | plane->base.id, intel_plane->pipe, | |
11863 | crtc->base.primary == plane ? 0 : intel_plane->plane + 1, | |
11864 | drm_plane_index(plane)); | |
11865 | DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x", | |
11866 | fb->base.id, fb->width, fb->height, fb->pixel_format); | |
11867 | DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n", | |
11868 | state->scaler_id, | |
11869 | state->src.x1 >> 16, state->src.y1 >> 16, | |
11870 | drm_rect_width(&state->src) >> 16, | |
11871 | drm_rect_height(&state->src) >> 16, | |
11872 | state->dst.x1, state->dst.y1, | |
11873 | drm_rect_width(&state->dst), drm_rect_height(&state->dst)); | |
11874 | } | |
c0b03411 DV |
11875 | } |
11876 | ||
bc079e8b VS |
11877 | static bool encoders_cloneable(const struct intel_encoder *a, |
11878 | const struct intel_encoder *b) | |
accfc0c5 | 11879 | { |
bc079e8b VS |
11880 | /* masks could be asymmetric, so check both ways */ |
11881 | return a == b || (a->cloneable & (1 << b->type) && | |
11882 | b->cloneable & (1 << a->type)); | |
11883 | } | |
11884 | ||
98a221da ACO |
11885 | static bool check_single_encoder_cloning(struct drm_atomic_state *state, |
11886 | struct intel_crtc *crtc, | |
bc079e8b VS |
11887 | struct intel_encoder *encoder) |
11888 | { | |
bc079e8b | 11889 | struct intel_encoder *source_encoder; |
da3ced29 | 11890 | struct drm_connector *connector; |
98a221da ACO |
11891 | struct drm_connector_state *connector_state; |
11892 | int i; | |
bc079e8b | 11893 | |
da3ced29 | 11894 | for_each_connector_in_state(state, connector, connector_state, i) { |
98a221da | 11895 | if (connector_state->crtc != &crtc->base) |
bc079e8b VS |
11896 | continue; |
11897 | ||
98a221da ACO |
11898 | source_encoder = |
11899 | to_intel_encoder(connector_state->best_encoder); | |
bc079e8b VS |
11900 | if (!encoders_cloneable(encoder, source_encoder)) |
11901 | return false; | |
11902 | } | |
11903 | ||
11904 | return true; | |
11905 | } | |
11906 | ||
98a221da ACO |
11907 | static bool check_encoder_cloning(struct drm_atomic_state *state, |
11908 | struct intel_crtc *crtc) | |
bc079e8b | 11909 | { |
accfc0c5 | 11910 | struct intel_encoder *encoder; |
da3ced29 | 11911 | struct drm_connector *connector; |
98a221da ACO |
11912 | struct drm_connector_state *connector_state; |
11913 | int i; | |
accfc0c5 | 11914 | |
da3ced29 | 11915 | for_each_connector_in_state(state, connector, connector_state, i) { |
98a221da ACO |
11916 | if (connector_state->crtc != &crtc->base) |
11917 | continue; | |
11918 | ||
11919 | encoder = to_intel_encoder(connector_state->best_encoder); | |
11920 | if (!check_single_encoder_cloning(state, crtc, encoder)) | |
bc079e8b | 11921 | return false; |
accfc0c5 DV |
11922 | } |
11923 | ||
bc079e8b | 11924 | return true; |
accfc0c5 DV |
11925 | } |
11926 | ||
5448a00d | 11927 | static bool check_digital_port_conflicts(struct drm_atomic_state *state) |
00f0b378 | 11928 | { |
5448a00d ACO |
11929 | struct drm_device *dev = state->dev; |
11930 | struct intel_encoder *encoder; | |
da3ced29 | 11931 | struct drm_connector *connector; |
5448a00d | 11932 | struct drm_connector_state *connector_state; |
00f0b378 | 11933 | unsigned int used_ports = 0; |
5448a00d | 11934 | int i; |
00f0b378 VS |
11935 | |
11936 | /* | |
11937 | * Walk the connector list instead of the encoder | |
11938 | * list to detect the problem on ddi platforms | |
11939 | * where there's just one encoder per digital port. | |
11940 | */ | |
da3ced29 | 11941 | for_each_connector_in_state(state, connector, connector_state, i) { |
5448a00d | 11942 | if (!connector_state->best_encoder) |
00f0b378 VS |
11943 | continue; |
11944 | ||
5448a00d ACO |
11945 | encoder = to_intel_encoder(connector_state->best_encoder); |
11946 | ||
11947 | WARN_ON(!connector_state->crtc); | |
00f0b378 VS |
11948 | |
11949 | switch (encoder->type) { | |
11950 | unsigned int port_mask; | |
11951 | case INTEL_OUTPUT_UNKNOWN: | |
11952 | if (WARN_ON(!HAS_DDI(dev))) | |
11953 | break; | |
11954 | case INTEL_OUTPUT_DISPLAYPORT: | |
11955 | case INTEL_OUTPUT_HDMI: | |
11956 | case INTEL_OUTPUT_EDP: | |
11957 | port_mask = 1 << enc_to_dig_port(&encoder->base)->port; | |
11958 | ||
11959 | /* the same port mustn't appear more than once */ | |
11960 | if (used_ports & port_mask) | |
11961 | return false; | |
11962 | ||
11963 | used_ports |= port_mask; | |
11964 | default: | |
11965 | break; | |
11966 | } | |
11967 | } | |
11968 | ||
11969 | return true; | |
11970 | } | |
11971 | ||
83a57153 ACO |
11972 | static void |
11973 | clear_intel_crtc_state(struct intel_crtc_state *crtc_state) | |
11974 | { | |
11975 | struct drm_crtc_state tmp_state; | |
663a3640 | 11976 | struct intel_crtc_scaler_state scaler_state; |
4978cc93 ACO |
11977 | struct intel_dpll_hw_state dpll_hw_state; |
11978 | enum intel_dpll_id shared_dpll; | |
8504c74c | 11979 | uint32_t ddi_pll_sel; |
83a57153 | 11980 | |
7546a384 ACO |
11981 | /* FIXME: before the switch to atomic started, a new pipe_config was |
11982 | * kzalloc'd. Code that depends on any field being zero should be | |
11983 | * fixed, so that the crtc_state can be safely duplicated. For now, | |
11984 | * only fields that are know to not cause problems are preserved. */ | |
11985 | ||
83a57153 | 11986 | tmp_state = crtc_state->base; |
663a3640 | 11987 | scaler_state = crtc_state->scaler_state; |
4978cc93 ACO |
11988 | shared_dpll = crtc_state->shared_dpll; |
11989 | dpll_hw_state = crtc_state->dpll_hw_state; | |
8504c74c | 11990 | ddi_pll_sel = crtc_state->ddi_pll_sel; |
4978cc93 | 11991 | |
83a57153 | 11992 | memset(crtc_state, 0, sizeof *crtc_state); |
4978cc93 | 11993 | |
83a57153 | 11994 | crtc_state->base = tmp_state; |
663a3640 | 11995 | crtc_state->scaler_state = scaler_state; |
4978cc93 ACO |
11996 | crtc_state->shared_dpll = shared_dpll; |
11997 | crtc_state->dpll_hw_state = dpll_hw_state; | |
8504c74c | 11998 | crtc_state->ddi_pll_sel = ddi_pll_sel; |
83a57153 ACO |
11999 | } |
12000 | ||
548ee15b | 12001 | static int |
b8cecdf5 | 12002 | intel_modeset_pipe_config(struct drm_crtc *crtc, |
568c634a | 12003 | struct drm_atomic_state *state) |
ee7b9f93 | 12004 | { |
568c634a ACO |
12005 | struct drm_crtc_state *crtc_state; |
12006 | struct intel_crtc_state *pipe_config; | |
7758a113 | 12007 | struct intel_encoder *encoder; |
da3ced29 | 12008 | struct drm_connector *connector; |
0b901879 | 12009 | struct drm_connector_state *connector_state; |
d328c9d7 | 12010 | int base_bpp, ret = -EINVAL; |
0b901879 | 12011 | int i; |
e29c22c0 | 12012 | bool retry = true; |
ee7b9f93 | 12013 | |
98a221da | 12014 | if (!check_encoder_cloning(state, to_intel_crtc(crtc))) { |
accfc0c5 | 12015 | DRM_DEBUG_KMS("rejecting invalid cloning configuration\n"); |
548ee15b | 12016 | return -EINVAL; |
accfc0c5 DV |
12017 | } |
12018 | ||
5448a00d | 12019 | if (!check_digital_port_conflicts(state)) { |
00f0b378 | 12020 | DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n"); |
548ee15b | 12021 | return -EINVAL; |
00f0b378 VS |
12022 | } |
12023 | ||
568c634a ACO |
12024 | crtc_state = drm_atomic_get_existing_crtc_state(state, crtc); |
12025 | if (WARN_ON(!crtc_state)) | |
12026 | return -EINVAL; | |
12027 | ||
12028 | pipe_config = to_intel_crtc_state(crtc_state); | |
12029 | ||
cdba954e ACO |
12030 | /* |
12031 | * XXX: Add all connectors to make the crtc state match the encoders. | |
12032 | */ | |
12033 | if (!needs_modeset(&pipe_config->base)) { | |
12034 | ret = drm_atomic_add_affected_connectors(state, crtc); | |
12035 | if (ret) | |
12036 | return ret; | |
12037 | } | |
12038 | ||
83a57153 | 12039 | clear_intel_crtc_state(pipe_config); |
7758a113 | 12040 | |
e143a21c DV |
12041 | pipe_config->cpu_transcoder = |
12042 | (enum transcoder) to_intel_crtc(crtc)->pipe; | |
b8cecdf5 | 12043 | |
2960bc9c ID |
12044 | /* |
12045 | * Sanitize sync polarity flags based on requested ones. If neither | |
12046 | * positive or negative polarity is requested, treat this as meaning | |
12047 | * negative polarity. | |
12048 | */ | |
2d112de7 | 12049 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 12050 | (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) |
2d112de7 | 12051 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; |
2960bc9c | 12052 | |
2d112de7 | 12053 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 12054 | (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) |
2d112de7 | 12055 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; |
2960bc9c | 12056 | |
050f7aeb DV |
12057 | /* Compute a starting value for pipe_config->pipe_bpp taking the source |
12058 | * plane pixel format and any sink constraints into account. Returns the | |
12059 | * source plane bpp so that dithering can be selected on mismatches | |
12060 | * after encoders and crtc also have had their say. */ | |
d328c9d7 DV |
12061 | base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc), |
12062 | pipe_config); | |
12063 | if (base_bpp < 0) | |
4e53c2e0 DV |
12064 | goto fail; |
12065 | ||
e41a56be VS |
12066 | /* |
12067 | * Determine the real pipe dimensions. Note that stereo modes can | |
12068 | * increase the actual pipe size due to the frame doubling and | |
12069 | * insertion of additional space for blanks between the frame. This | |
12070 | * is stored in the crtc timings. We use the requested mode to do this | |
12071 | * computation to clearly distinguish it from the adjusted mode, which | |
12072 | * can be changed by the connectors in the below retry loop. | |
12073 | */ | |
2d112de7 | 12074 | drm_crtc_get_hv_timing(&pipe_config->base.mode, |
ecb7e16b GP |
12075 | &pipe_config->pipe_src_w, |
12076 | &pipe_config->pipe_src_h); | |
e41a56be | 12077 | |
e29c22c0 | 12078 | encoder_retry: |
ef1b460d | 12079 | /* Ensure the port clock defaults are reset when retrying. */ |
ff9a6750 | 12080 | pipe_config->port_clock = 0; |
ef1b460d | 12081 | pipe_config->pixel_multiplier = 1; |
ff9a6750 | 12082 | |
135c81b8 | 12083 | /* Fill in default crtc timings, allow encoders to overwrite them. */ |
2d112de7 ACO |
12084 | drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode, |
12085 | CRTC_STEREO_DOUBLE); | |
135c81b8 | 12086 | |
7758a113 DV |
12087 | /* Pass our mode to the connectors and the CRTC to give them a chance to |
12088 | * adjust it according to limitations or connector properties, and also | |
12089 | * a chance to reject the mode entirely. | |
47f1c6c9 | 12090 | */ |
da3ced29 | 12091 | for_each_connector_in_state(state, connector, connector_state, i) { |
0b901879 | 12092 | if (connector_state->crtc != crtc) |
7758a113 | 12093 | continue; |
7ae89233 | 12094 | |
0b901879 ACO |
12095 | encoder = to_intel_encoder(connector_state->best_encoder); |
12096 | ||
efea6e8e DV |
12097 | if (!(encoder->compute_config(encoder, pipe_config))) { |
12098 | DRM_DEBUG_KMS("Encoder config failure\n"); | |
7758a113 DV |
12099 | goto fail; |
12100 | } | |
ee7b9f93 | 12101 | } |
47f1c6c9 | 12102 | |
ff9a6750 DV |
12103 | /* Set default port clock if not overwritten by the encoder. Needs to be |
12104 | * done afterwards in case the encoder adjusts the mode. */ | |
12105 | if (!pipe_config->port_clock) | |
2d112de7 | 12106 | pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock |
241bfc38 | 12107 | * pipe_config->pixel_multiplier; |
ff9a6750 | 12108 | |
a43f6e0f | 12109 | ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); |
e29c22c0 | 12110 | if (ret < 0) { |
7758a113 DV |
12111 | DRM_DEBUG_KMS("CRTC fixup failed\n"); |
12112 | goto fail; | |
ee7b9f93 | 12113 | } |
e29c22c0 DV |
12114 | |
12115 | if (ret == RETRY) { | |
12116 | if (WARN(!retry, "loop in pipe configuration computation\n")) { | |
12117 | ret = -EINVAL; | |
12118 | goto fail; | |
12119 | } | |
12120 | ||
12121 | DRM_DEBUG_KMS("CRTC bw constrained, retrying\n"); | |
12122 | retry = false; | |
12123 | goto encoder_retry; | |
12124 | } | |
12125 | ||
d328c9d7 | 12126 | pipe_config->dither = pipe_config->pipe_bpp != base_bpp; |
4e53c2e0 | 12127 | DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n", |
d328c9d7 | 12128 | base_bpp, pipe_config->pipe_bpp, pipe_config->dither); |
4e53c2e0 | 12129 | |
cdba954e ACO |
12130 | /* Check if we need to force a modeset */ |
12131 | if (pipe_config->has_audio != | |
85a96e7a | 12132 | to_intel_crtc_state(crtc->state)->has_audio) { |
cdba954e | 12133 | pipe_config->base.mode_changed = true; |
85a96e7a ML |
12134 | ret = drm_atomic_add_affected_planes(state, crtc); |
12135 | } | |
cdba954e ACO |
12136 | |
12137 | /* | |
12138 | * Note we have an issue here with infoframes: current code | |
12139 | * only updates them on the full mode set path per hw | |
12140 | * requirements. So here we should be checking for any | |
12141 | * required changes and forcing a mode set. | |
12142 | */ | |
7758a113 | 12143 | fail: |
548ee15b | 12144 | return ret; |
ee7b9f93 | 12145 | } |
47f1c6c9 | 12146 | |
ea9d758d | 12147 | static bool intel_crtc_in_use(struct drm_crtc *crtc) |
f6e5b160 | 12148 | { |
ea9d758d | 12149 | struct drm_encoder *encoder; |
f6e5b160 | 12150 | struct drm_device *dev = crtc->dev; |
f6e5b160 | 12151 | |
ea9d758d DV |
12152 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) |
12153 | if (encoder->crtc == crtc) | |
12154 | return true; | |
12155 | ||
12156 | return false; | |
12157 | } | |
12158 | ||
12159 | static void | |
0a9ab303 | 12160 | intel_modeset_update_state(struct drm_atomic_state *state) |
ea9d758d | 12161 | { |
0a9ab303 | 12162 | struct drm_device *dev = state->dev; |
ea9d758d | 12163 | struct intel_encoder *intel_encoder; |
0a9ab303 ACO |
12164 | struct drm_crtc *crtc; |
12165 | struct drm_crtc_state *crtc_state; | |
ea9d758d DV |
12166 | struct drm_connector *connector; |
12167 | ||
de419ab6 | 12168 | intel_shared_dpll_commit(state); |
ba41c0de | 12169 | |
b2784e15 | 12170 | for_each_intel_encoder(dev, intel_encoder) { |
ea9d758d DV |
12171 | if (!intel_encoder->base.crtc) |
12172 | continue; | |
12173 | ||
69024de8 ML |
12174 | crtc = intel_encoder->base.crtc; |
12175 | crtc_state = drm_atomic_get_existing_crtc_state(state, crtc); | |
12176 | if (!crtc_state || !needs_modeset(crtc->state)) | |
12177 | continue; | |
ea9d758d | 12178 | |
69024de8 | 12179 | intel_encoder->connectors_active = false; |
ea9d758d DV |
12180 | } |
12181 | ||
3cb480bc | 12182 | drm_atomic_helper_update_legacy_modeset_state(state->dev, state); |
ea9d758d | 12183 | |
7668851f | 12184 | /* Double check state. */ |
0a9ab303 ACO |
12185 | for_each_crtc(dev, crtc) { |
12186 | WARN_ON(crtc->state->enable != intel_crtc_in_use(crtc)); | |
3cb480bc ML |
12187 | |
12188 | to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state); | |
fc467a22 ML |
12189 | |
12190 | /* Update hwmode for vblank functions */ | |
12191 | if (crtc->state->active) | |
12192 | crtc->hwmode = crtc->state->adjusted_mode; | |
12193 | else | |
12194 | crtc->hwmode.crtc_clock = 0; | |
ea9d758d DV |
12195 | } |
12196 | ||
12197 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
12198 | if (!connector->encoder || !connector->encoder->crtc) | |
12199 | continue; | |
12200 | ||
69024de8 ML |
12201 | crtc = connector->encoder->crtc; |
12202 | crtc_state = drm_atomic_get_existing_crtc_state(state, crtc); | |
12203 | if (!crtc_state || !needs_modeset(crtc->state)) | |
12204 | continue; | |
ea9d758d | 12205 | |
53d9f4e9 | 12206 | if (crtc->state->active) { |
69024de8 ML |
12207 | struct drm_property *dpms_property = |
12208 | dev->mode_config.dpms_property; | |
68d34720 | 12209 | |
69024de8 ML |
12210 | connector->dpms = DRM_MODE_DPMS_ON; |
12211 | drm_object_property_set_value(&connector->base, dpms_property, DRM_MODE_DPMS_ON); | |
ea9d758d | 12212 | |
69024de8 ML |
12213 | intel_encoder = to_intel_encoder(connector->encoder); |
12214 | intel_encoder->connectors_active = true; | |
12215 | } else | |
12216 | connector->dpms = DRM_MODE_DPMS_OFF; | |
ea9d758d | 12217 | } |
ea9d758d DV |
12218 | } |
12219 | ||
3bd26263 | 12220 | static bool intel_fuzzy_clock_check(int clock1, int clock2) |
f1f644dc | 12221 | { |
3bd26263 | 12222 | int diff; |
f1f644dc JB |
12223 | |
12224 | if (clock1 == clock2) | |
12225 | return true; | |
12226 | ||
12227 | if (!clock1 || !clock2) | |
12228 | return false; | |
12229 | ||
12230 | diff = abs(clock1 - clock2); | |
12231 | ||
12232 | if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) | |
12233 | return true; | |
12234 | ||
12235 | return false; | |
12236 | } | |
12237 | ||
25c5b266 DV |
12238 | #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \ |
12239 | list_for_each_entry((intel_crtc), \ | |
12240 | &(dev)->mode_config.crtc_list, \ | |
12241 | base.head) \ | |
0973f18f | 12242 | if (mask & (1 <<(intel_crtc)->pipe)) |
25c5b266 | 12243 | |
0e8ffe1b | 12244 | static bool |
2fa2fe9a | 12245 | intel_pipe_config_compare(struct drm_device *dev, |
5cec258b ACO |
12246 | struct intel_crtc_state *current_config, |
12247 | struct intel_crtc_state *pipe_config) | |
0e8ffe1b | 12248 | { |
66e985c0 DV |
12249 | #define PIPE_CONF_CHECK_X(name) \ |
12250 | if (current_config->name != pipe_config->name) { \ | |
12251 | DRM_ERROR("mismatch in " #name " " \ | |
12252 | "(expected 0x%08x, found 0x%08x)\n", \ | |
12253 | current_config->name, \ | |
12254 | pipe_config->name); \ | |
12255 | return false; \ | |
12256 | } | |
12257 | ||
08a24034 DV |
12258 | #define PIPE_CONF_CHECK_I(name) \ |
12259 | if (current_config->name != pipe_config->name) { \ | |
12260 | DRM_ERROR("mismatch in " #name " " \ | |
12261 | "(expected %i, found %i)\n", \ | |
12262 | current_config->name, \ | |
12263 | pipe_config->name); \ | |
12264 | return false; \ | |
88adfff1 DV |
12265 | } |
12266 | ||
b95af8be VK |
12267 | /* This is required for BDW+ where there is only one set of registers for |
12268 | * switching between high and low RR. | |
12269 | * This macro can be used whenever a comparison has to be made between one | |
12270 | * hw state and multiple sw state variables. | |
12271 | */ | |
12272 | #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \ | |
12273 | if ((current_config->name != pipe_config->name) && \ | |
12274 | (current_config->alt_name != pipe_config->name)) { \ | |
12275 | DRM_ERROR("mismatch in " #name " " \ | |
12276 | "(expected %i or %i, found %i)\n", \ | |
12277 | current_config->name, \ | |
12278 | current_config->alt_name, \ | |
12279 | pipe_config->name); \ | |
12280 | return false; \ | |
12281 | } | |
12282 | ||
1bd1bd80 DV |
12283 | #define PIPE_CONF_CHECK_FLAGS(name, mask) \ |
12284 | if ((current_config->name ^ pipe_config->name) & (mask)) { \ | |
6f02488e | 12285 | DRM_ERROR("mismatch in " #name "(" #mask ") " \ |
1bd1bd80 DV |
12286 | "(expected %i, found %i)\n", \ |
12287 | current_config->name & (mask), \ | |
12288 | pipe_config->name & (mask)); \ | |
12289 | return false; \ | |
12290 | } | |
12291 | ||
5e550656 VS |
12292 | #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \ |
12293 | if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \ | |
12294 | DRM_ERROR("mismatch in " #name " " \ | |
12295 | "(expected %i, found %i)\n", \ | |
12296 | current_config->name, \ | |
12297 | pipe_config->name); \ | |
12298 | return false; \ | |
12299 | } | |
12300 | ||
bb760063 DV |
12301 | #define PIPE_CONF_QUIRK(quirk) \ |
12302 | ((current_config->quirks | pipe_config->quirks) & (quirk)) | |
12303 | ||
eccb140b DV |
12304 | PIPE_CONF_CHECK_I(cpu_transcoder); |
12305 | ||
08a24034 DV |
12306 | PIPE_CONF_CHECK_I(has_pch_encoder); |
12307 | PIPE_CONF_CHECK_I(fdi_lanes); | |
72419203 DV |
12308 | PIPE_CONF_CHECK_I(fdi_m_n.gmch_m); |
12309 | PIPE_CONF_CHECK_I(fdi_m_n.gmch_n); | |
12310 | PIPE_CONF_CHECK_I(fdi_m_n.link_m); | |
12311 | PIPE_CONF_CHECK_I(fdi_m_n.link_n); | |
12312 | PIPE_CONF_CHECK_I(fdi_m_n.tu); | |
08a24034 | 12313 | |
eb14cb74 | 12314 | PIPE_CONF_CHECK_I(has_dp_encoder); |
b95af8be VK |
12315 | |
12316 | if (INTEL_INFO(dev)->gen < 8) { | |
12317 | PIPE_CONF_CHECK_I(dp_m_n.gmch_m); | |
12318 | PIPE_CONF_CHECK_I(dp_m_n.gmch_n); | |
12319 | PIPE_CONF_CHECK_I(dp_m_n.link_m); | |
12320 | PIPE_CONF_CHECK_I(dp_m_n.link_n); | |
12321 | PIPE_CONF_CHECK_I(dp_m_n.tu); | |
12322 | ||
12323 | if (current_config->has_drrs) { | |
12324 | PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m); | |
12325 | PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n); | |
12326 | PIPE_CONF_CHECK_I(dp_m2_n2.link_m); | |
12327 | PIPE_CONF_CHECK_I(dp_m2_n2.link_n); | |
12328 | PIPE_CONF_CHECK_I(dp_m2_n2.tu); | |
12329 | } | |
12330 | } else { | |
12331 | PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m); | |
12332 | PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n); | |
12333 | PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m); | |
12334 | PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n); | |
12335 | PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu); | |
12336 | } | |
eb14cb74 | 12337 | |
2d112de7 ACO |
12338 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay); |
12339 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal); | |
12340 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start); | |
12341 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end); | |
12342 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start); | |
12343 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end); | |
1bd1bd80 | 12344 | |
2d112de7 ACO |
12345 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay); |
12346 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal); | |
12347 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start); | |
12348 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end); | |
12349 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start); | |
12350 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end); | |
1bd1bd80 | 12351 | |
c93f54cf | 12352 | PIPE_CONF_CHECK_I(pixel_multiplier); |
6897b4b5 | 12353 | PIPE_CONF_CHECK_I(has_hdmi_sink); |
b5a9fa09 DV |
12354 | if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) || |
12355 | IS_VALLEYVIEW(dev)) | |
12356 | PIPE_CONF_CHECK_I(limited_color_range); | |
e43823ec | 12357 | PIPE_CONF_CHECK_I(has_infoframe); |
6c49f241 | 12358 | |
9ed109a7 DV |
12359 | PIPE_CONF_CHECK_I(has_audio); |
12360 | ||
2d112de7 | 12361 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
1bd1bd80 DV |
12362 | DRM_MODE_FLAG_INTERLACE); |
12363 | ||
bb760063 | 12364 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { |
2d112de7 | 12365 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 12366 | DRM_MODE_FLAG_PHSYNC); |
2d112de7 | 12367 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 12368 | DRM_MODE_FLAG_NHSYNC); |
2d112de7 | 12369 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 12370 | DRM_MODE_FLAG_PVSYNC); |
2d112de7 | 12371 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 DV |
12372 | DRM_MODE_FLAG_NVSYNC); |
12373 | } | |
045ac3b5 | 12374 | |
37327abd VS |
12375 | PIPE_CONF_CHECK_I(pipe_src_w); |
12376 | PIPE_CONF_CHECK_I(pipe_src_h); | |
1bd1bd80 | 12377 | |
9953599b DV |
12378 | /* |
12379 | * FIXME: BIOS likes to set up a cloned config with lvds+external | |
12380 | * screen. Since we don't yet re-compute the pipe config when moving | |
12381 | * just the lvds port away to another pipe the sw tracking won't match. | |
12382 | * | |
12383 | * Proper atomic modesets with recomputed global state will fix this. | |
12384 | * Until then just don't check gmch state for inherited modes. | |
12385 | */ | |
12386 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) { | |
12387 | PIPE_CONF_CHECK_I(gmch_pfit.control); | |
12388 | /* pfit ratios are autocomputed by the hw on gen4+ */ | |
12389 | if (INTEL_INFO(dev)->gen < 4) | |
12390 | PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios); | |
12391 | PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits); | |
12392 | } | |
12393 | ||
fd4daa9c CW |
12394 | PIPE_CONF_CHECK_I(pch_pfit.enabled); |
12395 | if (current_config->pch_pfit.enabled) { | |
12396 | PIPE_CONF_CHECK_I(pch_pfit.pos); | |
12397 | PIPE_CONF_CHECK_I(pch_pfit.size); | |
12398 | } | |
2fa2fe9a | 12399 | |
a1b2278e CK |
12400 | PIPE_CONF_CHECK_I(scaler_state.scaler_id); |
12401 | ||
e59150dc JB |
12402 | /* BDW+ don't expose a synchronous way to read the state */ |
12403 | if (IS_HASWELL(dev)) | |
12404 | PIPE_CONF_CHECK_I(ips_enabled); | |
42db64ef | 12405 | |
282740f7 VS |
12406 | PIPE_CONF_CHECK_I(double_wide); |
12407 | ||
26804afd DV |
12408 | PIPE_CONF_CHECK_X(ddi_pll_sel); |
12409 | ||
c0d43d62 | 12410 | PIPE_CONF_CHECK_I(shared_dpll); |
66e985c0 | 12411 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll); |
8bcc2795 | 12412 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); |
66e985c0 DV |
12413 | PIPE_CONF_CHECK_X(dpll_hw_state.fp0); |
12414 | PIPE_CONF_CHECK_X(dpll_hw_state.fp1); | |
d452c5b6 | 12415 | PIPE_CONF_CHECK_X(dpll_hw_state.wrpll); |
3f4cd19f DL |
12416 | PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1); |
12417 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1); | |
12418 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2); | |
c0d43d62 | 12419 | |
42571aef VS |
12420 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) |
12421 | PIPE_CONF_CHECK_I(pipe_bpp); | |
12422 | ||
2d112de7 | 12423 | PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock); |
a9a7e98a | 12424 | PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); |
5e550656 | 12425 | |
66e985c0 | 12426 | #undef PIPE_CONF_CHECK_X |
08a24034 | 12427 | #undef PIPE_CONF_CHECK_I |
b95af8be | 12428 | #undef PIPE_CONF_CHECK_I_ALT |
1bd1bd80 | 12429 | #undef PIPE_CONF_CHECK_FLAGS |
5e550656 | 12430 | #undef PIPE_CONF_CHECK_CLOCK_FUZZY |
bb760063 | 12431 | #undef PIPE_CONF_QUIRK |
88adfff1 | 12432 | |
0e8ffe1b DV |
12433 | return true; |
12434 | } | |
12435 | ||
08db6652 DL |
12436 | static void check_wm_state(struct drm_device *dev) |
12437 | { | |
12438 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12439 | struct skl_ddb_allocation hw_ddb, *sw_ddb; | |
12440 | struct intel_crtc *intel_crtc; | |
12441 | int plane; | |
12442 | ||
12443 | if (INTEL_INFO(dev)->gen < 9) | |
12444 | return; | |
12445 | ||
12446 | skl_ddb_get_hw_state(dev_priv, &hw_ddb); | |
12447 | sw_ddb = &dev_priv->wm.skl_hw.ddb; | |
12448 | ||
12449 | for_each_intel_crtc(dev, intel_crtc) { | |
12450 | struct skl_ddb_entry *hw_entry, *sw_entry; | |
12451 | const enum pipe pipe = intel_crtc->pipe; | |
12452 | ||
12453 | if (!intel_crtc->active) | |
12454 | continue; | |
12455 | ||
12456 | /* planes */ | |
dd740780 | 12457 | for_each_plane(dev_priv, pipe, plane) { |
08db6652 DL |
12458 | hw_entry = &hw_ddb.plane[pipe][plane]; |
12459 | sw_entry = &sw_ddb->plane[pipe][plane]; | |
12460 | ||
12461 | if (skl_ddb_entry_equal(hw_entry, sw_entry)) | |
12462 | continue; | |
12463 | ||
12464 | DRM_ERROR("mismatch in DDB state pipe %c plane %d " | |
12465 | "(expected (%u,%u), found (%u,%u))\n", | |
12466 | pipe_name(pipe), plane + 1, | |
12467 | sw_entry->start, sw_entry->end, | |
12468 | hw_entry->start, hw_entry->end); | |
12469 | } | |
12470 | ||
12471 | /* cursor */ | |
12472 | hw_entry = &hw_ddb.cursor[pipe]; | |
12473 | sw_entry = &sw_ddb->cursor[pipe]; | |
12474 | ||
12475 | if (skl_ddb_entry_equal(hw_entry, sw_entry)) | |
12476 | continue; | |
12477 | ||
12478 | DRM_ERROR("mismatch in DDB state pipe %c cursor " | |
12479 | "(expected (%u,%u), found (%u,%u))\n", | |
12480 | pipe_name(pipe), | |
12481 | sw_entry->start, sw_entry->end, | |
12482 | hw_entry->start, hw_entry->end); | |
12483 | } | |
12484 | } | |
12485 | ||
91d1b4bd DV |
12486 | static void |
12487 | check_connector_state(struct drm_device *dev) | |
8af6cf88 | 12488 | { |
8af6cf88 DV |
12489 | struct intel_connector *connector; |
12490 | ||
3a3371ff | 12491 | for_each_intel_connector(dev, connector) { |
37ade417 ACO |
12492 | struct drm_encoder *encoder = connector->base.encoder; |
12493 | struct drm_connector_state *state = connector->base.state; | |
12494 | ||
8af6cf88 DV |
12495 | /* This also checks the encoder/connector hw state with the |
12496 | * ->get_hw_state callbacks. */ | |
12497 | intel_connector_check_state(connector); | |
12498 | ||
37ade417 | 12499 | I915_STATE_WARN(state->best_encoder != encoder, |
8af6cf88 DV |
12500 | "connector's staged encoder doesn't match current encoder\n"); |
12501 | } | |
91d1b4bd DV |
12502 | } |
12503 | ||
12504 | static void | |
12505 | check_encoder_state(struct drm_device *dev) | |
12506 | { | |
12507 | struct intel_encoder *encoder; | |
12508 | struct intel_connector *connector; | |
8af6cf88 | 12509 | |
b2784e15 | 12510 | for_each_intel_encoder(dev, encoder) { |
8af6cf88 DV |
12511 | bool enabled = false; |
12512 | bool active = false; | |
12513 | enum pipe pipe, tracked_pipe; | |
12514 | ||
12515 | DRM_DEBUG_KMS("[ENCODER:%d:%s]\n", | |
12516 | encoder->base.base.id, | |
8e329a03 | 12517 | encoder->base.name); |
8af6cf88 | 12518 | |
e2c719b7 | 12519 | I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc, |
8af6cf88 DV |
12520 | "encoder's active_connectors set, but no crtc\n"); |
12521 | ||
3a3371ff | 12522 | for_each_intel_connector(dev, connector) { |
8af6cf88 DV |
12523 | if (connector->base.encoder != &encoder->base) |
12524 | continue; | |
12525 | enabled = true; | |
12526 | if (connector->base.dpms != DRM_MODE_DPMS_OFF) | |
12527 | active = true; | |
37ade417 ACO |
12528 | |
12529 | I915_STATE_WARN(connector->base.state->crtc != encoder->base.crtc, | |
12530 | "encoder's stage crtc doesn't match current crtc\n"); | |
8af6cf88 | 12531 | } |
0e32b39c DA |
12532 | /* |
12533 | * for MST connectors if we unplug the connector is gone | |
12534 | * away but the encoder is still connected to a crtc | |
12535 | * until a modeset happens in response to the hotplug. | |
12536 | */ | |
12537 | if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST) | |
12538 | continue; | |
12539 | ||
e2c719b7 | 12540 | I915_STATE_WARN(!!encoder->base.crtc != enabled, |
8af6cf88 DV |
12541 | "encoder's enabled state mismatch " |
12542 | "(expected %i, found %i)\n", | |
12543 | !!encoder->base.crtc, enabled); | |
e2c719b7 | 12544 | I915_STATE_WARN(active && !encoder->base.crtc, |
8af6cf88 DV |
12545 | "active encoder with no crtc\n"); |
12546 | ||
e2c719b7 | 12547 | I915_STATE_WARN(encoder->connectors_active != active, |
8af6cf88 DV |
12548 | "encoder's computed active state doesn't match tracked active state " |
12549 | "(expected %i, found %i)\n", active, encoder->connectors_active); | |
12550 | ||
12551 | active = encoder->get_hw_state(encoder, &pipe); | |
e2c719b7 | 12552 | I915_STATE_WARN(active != encoder->connectors_active, |
8af6cf88 DV |
12553 | "encoder's hw state doesn't match sw tracking " |
12554 | "(expected %i, found %i)\n", | |
12555 | encoder->connectors_active, active); | |
12556 | ||
12557 | if (!encoder->base.crtc) | |
12558 | continue; | |
12559 | ||
12560 | tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe; | |
e2c719b7 | 12561 | I915_STATE_WARN(active && pipe != tracked_pipe, |
8af6cf88 DV |
12562 | "active encoder's pipe doesn't match" |
12563 | "(expected %i, found %i)\n", | |
12564 | tracked_pipe, pipe); | |
12565 | ||
12566 | } | |
91d1b4bd DV |
12567 | } |
12568 | ||
12569 | static void | |
12570 | check_crtc_state(struct drm_device *dev) | |
12571 | { | |
fbee40df | 12572 | struct drm_i915_private *dev_priv = dev->dev_private; |
91d1b4bd DV |
12573 | struct intel_crtc *crtc; |
12574 | struct intel_encoder *encoder; | |
5cec258b | 12575 | struct intel_crtc_state pipe_config; |
8af6cf88 | 12576 | |
d3fcc808 | 12577 | for_each_intel_crtc(dev, crtc) { |
8af6cf88 DV |
12578 | bool enabled = false; |
12579 | bool active = false; | |
12580 | ||
045ac3b5 JB |
12581 | memset(&pipe_config, 0, sizeof(pipe_config)); |
12582 | ||
8af6cf88 DV |
12583 | DRM_DEBUG_KMS("[CRTC:%d]\n", |
12584 | crtc->base.base.id); | |
12585 | ||
83d65738 | 12586 | I915_STATE_WARN(crtc->active && !crtc->base.state->enable, |
8af6cf88 DV |
12587 | "active crtc, but not enabled in sw tracking\n"); |
12588 | ||
b2784e15 | 12589 | for_each_intel_encoder(dev, encoder) { |
8af6cf88 DV |
12590 | if (encoder->base.crtc != &crtc->base) |
12591 | continue; | |
12592 | enabled = true; | |
12593 | if (encoder->connectors_active) | |
12594 | active = true; | |
12595 | } | |
6c49f241 | 12596 | |
e2c719b7 | 12597 | I915_STATE_WARN(active != crtc->active, |
8af6cf88 DV |
12598 | "crtc's computed active state doesn't match tracked active state " |
12599 | "(expected %i, found %i)\n", active, crtc->active); | |
83d65738 | 12600 | I915_STATE_WARN(enabled != crtc->base.state->enable, |
8af6cf88 | 12601 | "crtc's computed enabled state doesn't match tracked enabled state " |
83d65738 MR |
12602 | "(expected %i, found %i)\n", enabled, |
12603 | crtc->base.state->enable); | |
8af6cf88 | 12604 | |
0e8ffe1b DV |
12605 | active = dev_priv->display.get_pipe_config(crtc, |
12606 | &pipe_config); | |
d62cf62a | 12607 | |
b6b5d049 VS |
12608 | /* hw state is inconsistent with the pipe quirk */ |
12609 | if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
12610 | (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
d62cf62a DV |
12611 | active = crtc->active; |
12612 | ||
b2784e15 | 12613 | for_each_intel_encoder(dev, encoder) { |
3eaba51c | 12614 | enum pipe pipe; |
6c49f241 DV |
12615 | if (encoder->base.crtc != &crtc->base) |
12616 | continue; | |
1d37b689 | 12617 | if (encoder->get_hw_state(encoder, &pipe)) |
6c49f241 DV |
12618 | encoder->get_config(encoder, &pipe_config); |
12619 | } | |
12620 | ||
e2c719b7 | 12621 | I915_STATE_WARN(crtc->active != active, |
0e8ffe1b DV |
12622 | "crtc active state doesn't match with hw state " |
12623 | "(expected %i, found %i)\n", crtc->active, active); | |
12624 | ||
53d9f4e9 ML |
12625 | I915_STATE_WARN(crtc->active != crtc->base.state->active, |
12626 | "transitional active state does not match atomic hw state " | |
12627 | "(expected %i, found %i)\n", crtc->base.state->active, crtc->active); | |
12628 | ||
c0b03411 | 12629 | if (active && |
6e3c9717 | 12630 | !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) { |
e2c719b7 | 12631 | I915_STATE_WARN(1, "pipe state doesn't match!\n"); |
c0b03411 DV |
12632 | intel_dump_pipe_config(crtc, &pipe_config, |
12633 | "[hw state]"); | |
6e3c9717 | 12634 | intel_dump_pipe_config(crtc, crtc->config, |
c0b03411 DV |
12635 | "[sw state]"); |
12636 | } | |
8af6cf88 DV |
12637 | } |
12638 | } | |
12639 | ||
91d1b4bd DV |
12640 | static void |
12641 | check_shared_dpll_state(struct drm_device *dev) | |
12642 | { | |
fbee40df | 12643 | struct drm_i915_private *dev_priv = dev->dev_private; |
91d1b4bd DV |
12644 | struct intel_crtc *crtc; |
12645 | struct intel_dpll_hw_state dpll_hw_state; | |
12646 | int i; | |
5358901f DV |
12647 | |
12648 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
12649 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
12650 | int enabled_crtcs = 0, active_crtcs = 0; | |
12651 | bool active; | |
12652 | ||
12653 | memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); | |
12654 | ||
12655 | DRM_DEBUG_KMS("%s\n", pll->name); | |
12656 | ||
12657 | active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state); | |
12658 | ||
e2c719b7 | 12659 | I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask), |
5358901f | 12660 | "more active pll users than references: %i vs %i\n", |
3e369b76 | 12661 | pll->active, hweight32(pll->config.crtc_mask)); |
e2c719b7 | 12662 | I915_STATE_WARN(pll->active && !pll->on, |
5358901f | 12663 | "pll in active use but not on in sw tracking\n"); |
e2c719b7 | 12664 | I915_STATE_WARN(pll->on && !pll->active, |
35c95375 | 12665 | "pll in on but not on in use in sw tracking\n"); |
e2c719b7 | 12666 | I915_STATE_WARN(pll->on != active, |
5358901f DV |
12667 | "pll on state mismatch (expected %i, found %i)\n", |
12668 | pll->on, active); | |
12669 | ||
d3fcc808 | 12670 | for_each_intel_crtc(dev, crtc) { |
83d65738 | 12671 | if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll) |
5358901f DV |
12672 | enabled_crtcs++; |
12673 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) | |
12674 | active_crtcs++; | |
12675 | } | |
e2c719b7 | 12676 | I915_STATE_WARN(pll->active != active_crtcs, |
5358901f DV |
12677 | "pll active crtcs mismatch (expected %i, found %i)\n", |
12678 | pll->active, active_crtcs); | |
e2c719b7 | 12679 | I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs, |
5358901f | 12680 | "pll enabled crtcs mismatch (expected %i, found %i)\n", |
3e369b76 | 12681 | hweight32(pll->config.crtc_mask), enabled_crtcs); |
66e985c0 | 12682 | |
e2c719b7 | 12683 | I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state, |
66e985c0 DV |
12684 | sizeof(dpll_hw_state)), |
12685 | "pll hw state mismatch\n"); | |
5358901f | 12686 | } |
8af6cf88 DV |
12687 | } |
12688 | ||
91d1b4bd DV |
12689 | void |
12690 | intel_modeset_check_state(struct drm_device *dev) | |
12691 | { | |
08db6652 | 12692 | check_wm_state(dev); |
91d1b4bd DV |
12693 | check_connector_state(dev); |
12694 | check_encoder_state(dev); | |
12695 | check_crtc_state(dev); | |
12696 | check_shared_dpll_state(dev); | |
12697 | } | |
12698 | ||
5cec258b | 12699 | void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config, |
18442d08 VS |
12700 | int dotclock) |
12701 | { | |
12702 | /* | |
12703 | * FDI already provided one idea for the dotclock. | |
12704 | * Yell if the encoder disagrees. | |
12705 | */ | |
2d112de7 | 12706 | WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock), |
18442d08 | 12707 | "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n", |
2d112de7 | 12708 | pipe_config->base.adjusted_mode.crtc_clock, dotclock); |
18442d08 VS |
12709 | } |
12710 | ||
80715b2f VS |
12711 | static void update_scanline_offset(struct intel_crtc *crtc) |
12712 | { | |
12713 | struct drm_device *dev = crtc->base.dev; | |
12714 | ||
12715 | /* | |
12716 | * The scanline counter increments at the leading edge of hsync. | |
12717 | * | |
12718 | * On most platforms it starts counting from vtotal-1 on the | |
12719 | * first active line. That means the scanline counter value is | |
12720 | * always one less than what we would expect. Ie. just after | |
12721 | * start of vblank, which also occurs at start of hsync (on the | |
12722 | * last active line), the scanline counter will read vblank_start-1. | |
12723 | * | |
12724 | * On gen2 the scanline counter starts counting from 1 instead | |
12725 | * of vtotal-1, so we have to subtract one (or rather add vtotal-1 | |
12726 | * to keep the value positive), instead of adding one. | |
12727 | * | |
12728 | * On HSW+ the behaviour of the scanline counter depends on the output | |
12729 | * type. For DP ports it behaves like most other platforms, but on HDMI | |
12730 | * there's an extra 1 line difference. So we need to add two instead of | |
12731 | * one to the value. | |
12732 | */ | |
12733 | if (IS_GEN2(dev)) { | |
6e3c9717 | 12734 | const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode; |
80715b2f VS |
12735 | int vtotal; |
12736 | ||
12737 | vtotal = mode->crtc_vtotal; | |
12738 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) | |
12739 | vtotal /= 2; | |
12740 | ||
12741 | crtc->scanline_offset = vtotal - 1; | |
12742 | } else if (HAS_DDI(dev) && | |
409ee761 | 12743 | intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) { |
80715b2f VS |
12744 | crtc->scanline_offset = 2; |
12745 | } else | |
12746 | crtc->scanline_offset = 1; | |
12747 | } | |
12748 | ||
c347a676 | 12749 | static int intel_modeset_setup_plls(struct drm_atomic_state *state) |
ed6739ef | 12750 | { |
225da59b | 12751 | struct drm_device *dev = state->dev; |
ed6739ef | 12752 | struct drm_i915_private *dev_priv = to_i915(dev); |
0a9ab303 | 12753 | unsigned clear_pipes = 0; |
ed6739ef | 12754 | struct intel_crtc *intel_crtc; |
0a9ab303 ACO |
12755 | struct intel_crtc_state *intel_crtc_state; |
12756 | struct drm_crtc *crtc; | |
12757 | struct drm_crtc_state *crtc_state; | |
ed6739ef | 12758 | int ret = 0; |
0a9ab303 | 12759 | int i; |
ed6739ef ACO |
12760 | |
12761 | if (!dev_priv->display.crtc_compute_clock) | |
12762 | return 0; | |
12763 | ||
0a9ab303 ACO |
12764 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
12765 | intel_crtc = to_intel_crtc(crtc); | |
4978cc93 | 12766 | intel_crtc_state = to_intel_crtc_state(crtc_state); |
0a9ab303 | 12767 | |
4978cc93 | 12768 | if (needs_modeset(crtc_state)) { |
0a9ab303 | 12769 | clear_pipes |= 1 << intel_crtc->pipe; |
4978cc93 | 12770 | intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE; |
4978cc93 | 12771 | } |
0a9ab303 ACO |
12772 | } |
12773 | ||
de419ab6 ML |
12774 | if (clear_pipes) { |
12775 | struct intel_shared_dpll_config *shared_dpll = | |
12776 | intel_atomic_get_shared_dpll_state(state); | |
12777 | ||
12778 | for (i = 0; i < dev_priv->num_shared_dpll; i++) | |
12779 | shared_dpll[i].crtc_mask &= ~clear_pipes; | |
12780 | } | |
ed6739ef | 12781 | |
0a9ab303 ACO |
12782 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
12783 | if (!needs_modeset(crtc_state) || !crtc_state->enable) | |
225da59b ACO |
12784 | continue; |
12785 | ||
0a9ab303 ACO |
12786 | intel_crtc = to_intel_crtc(crtc); |
12787 | intel_crtc_state = to_intel_crtc_state(crtc_state); | |
12788 | ||
ed6739ef | 12789 | ret = dev_priv->display.crtc_compute_clock(intel_crtc, |
0a9ab303 | 12790 | intel_crtc_state); |
de419ab6 ML |
12791 | if (ret) |
12792 | return ret; | |
ed6739ef ACO |
12793 | } |
12794 | ||
ed6739ef ACO |
12795 | return ret; |
12796 | } | |
12797 | ||
99d736a2 ML |
12798 | /* |
12799 | * This implements the workaround described in the "notes" section of the mode | |
12800 | * set sequence documentation. When going from no pipes or single pipe to | |
12801 | * multiple pipes, and planes are enabled after the pipe, we need to wait at | |
12802 | * least 2 vblanks on the first pipe before enabling planes on the second pipe. | |
12803 | */ | |
12804 | static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state) | |
12805 | { | |
12806 | struct drm_crtc_state *crtc_state; | |
12807 | struct intel_crtc *intel_crtc; | |
12808 | struct drm_crtc *crtc; | |
12809 | struct intel_crtc_state *first_crtc_state = NULL; | |
12810 | struct intel_crtc_state *other_crtc_state = NULL; | |
12811 | enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE; | |
12812 | int i; | |
12813 | ||
12814 | /* look at all crtc's that are going to be enabled in during modeset */ | |
12815 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
12816 | intel_crtc = to_intel_crtc(crtc); | |
12817 | ||
12818 | if (!crtc_state->active || !needs_modeset(crtc_state)) | |
12819 | continue; | |
12820 | ||
12821 | if (first_crtc_state) { | |
12822 | other_crtc_state = to_intel_crtc_state(crtc_state); | |
12823 | break; | |
12824 | } else { | |
12825 | first_crtc_state = to_intel_crtc_state(crtc_state); | |
12826 | first_pipe = intel_crtc->pipe; | |
12827 | } | |
12828 | } | |
12829 | ||
12830 | /* No workaround needed? */ | |
12831 | if (!first_crtc_state) | |
12832 | return 0; | |
12833 | ||
12834 | /* w/a possibly needed, check how many crtc's are already enabled. */ | |
12835 | for_each_intel_crtc(state->dev, intel_crtc) { | |
12836 | struct intel_crtc_state *pipe_config; | |
12837 | ||
12838 | pipe_config = intel_atomic_get_crtc_state(state, intel_crtc); | |
12839 | if (IS_ERR(pipe_config)) | |
12840 | return PTR_ERR(pipe_config); | |
12841 | ||
12842 | pipe_config->hsw_workaround_pipe = INVALID_PIPE; | |
12843 | ||
12844 | if (!pipe_config->base.active || | |
12845 | needs_modeset(&pipe_config->base)) | |
12846 | continue; | |
12847 | ||
12848 | /* 2 or more enabled crtcs means no need for w/a */ | |
12849 | if (enabled_pipe != INVALID_PIPE) | |
12850 | return 0; | |
12851 | ||
12852 | enabled_pipe = intel_crtc->pipe; | |
12853 | } | |
12854 | ||
12855 | if (enabled_pipe != INVALID_PIPE) | |
12856 | first_crtc_state->hsw_workaround_pipe = enabled_pipe; | |
12857 | else if (other_crtc_state) | |
12858 | other_crtc_state->hsw_workaround_pipe = first_pipe; | |
12859 | ||
12860 | return 0; | |
12861 | } | |
12862 | ||
054518dd | 12863 | /* Code that should eventually be part of atomic_check() */ |
c347a676 | 12864 | static int intel_modeset_checks(struct drm_atomic_state *state) |
054518dd ACO |
12865 | { |
12866 | struct drm_device *dev = state->dev; | |
12867 | int ret; | |
12868 | ||
12869 | /* | |
12870 | * See if the config requires any additional preparation, e.g. | |
12871 | * to adjust global state with pipes off. We need to do this | |
12872 | * here so we can get the modeset_pipe updated config for the new | |
12873 | * mode set on this crtc. For other crtcs we need to use the | |
12874 | * adjusted_mode bits in the crtc directly. | |
12875 | */ | |
b432e5cf VS |
12876 | if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev) || IS_BROADWELL(dev)) { |
12877 | if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) | |
12878 | ret = valleyview_modeset_global_pipes(state); | |
12879 | else | |
12880 | ret = broadwell_modeset_global_pipes(state); | |
12881 | ||
054518dd ACO |
12882 | if (ret) |
12883 | return ret; | |
12884 | } | |
12885 | ||
99d736a2 ML |
12886 | ret = intel_modeset_setup_plls(state); |
12887 | if (ret) | |
12888 | return ret; | |
12889 | ||
12890 | if (IS_HASWELL(dev)) | |
12891 | ret = haswell_mode_set_planes_workaround(state); | |
12892 | ||
12893 | return ret; | |
c347a676 ACO |
12894 | } |
12895 | ||
12896 | static int | |
12897 | intel_modeset_compute_config(struct drm_atomic_state *state) | |
12898 | { | |
12899 | struct drm_crtc *crtc; | |
12900 | struct drm_crtc_state *crtc_state; | |
12901 | int ret, i; | |
12902 | ||
12903 | ret = drm_atomic_helper_check_modeset(state->dev, state); | |
054518dd ACO |
12904 | if (ret) |
12905 | return ret; | |
12906 | ||
c347a676 ACO |
12907 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
12908 | if (!crtc_state->enable && | |
12909 | WARN_ON(crtc_state->active)) | |
12910 | crtc_state->active = false; | |
12911 | ||
12912 | if (!crtc_state->enable) | |
12913 | continue; | |
12914 | ||
12915 | ret = intel_modeset_pipe_config(crtc, state); | |
12916 | if (ret) | |
12917 | return ret; | |
12918 | ||
12919 | intel_dump_pipe_config(to_intel_crtc(crtc), | |
12920 | to_intel_crtc_state(crtc_state), | |
12921 | "[modeset]"); | |
12922 | } | |
12923 | ||
12924 | ret = intel_modeset_checks(state); | |
12925 | if (ret) | |
12926 | return ret; | |
12927 | ||
12928 | return drm_atomic_helper_check_planes(state->dev, state); | |
054518dd ACO |
12929 | } |
12930 | ||
c72d969b | 12931 | static int __intel_set_mode(struct drm_atomic_state *state) |
a6778b3c | 12932 | { |
c72d969b | 12933 | struct drm_device *dev = state->dev; |
fbee40df | 12934 | struct drm_i915_private *dev_priv = dev->dev_private; |
0a9ab303 ACO |
12935 | struct drm_crtc *crtc; |
12936 | struct drm_crtc_state *crtc_state; | |
c0c36b94 | 12937 | int ret = 0; |
0a9ab303 | 12938 | int i; |
a6778b3c | 12939 | |
d4afb8cc ACO |
12940 | ret = drm_atomic_helper_prepare_planes(dev, state); |
12941 | if (ret) | |
12942 | return ret; | |
12943 | ||
1c5e19f8 ML |
12944 | drm_atomic_helper_swap_state(dev, state); |
12945 | ||
0a9ab303 | 12946 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
1c5e19f8 | 12947 | if (!needs_modeset(crtc->state) || !crtc_state->active) |
0a9ab303 | 12948 | continue; |
460da916 | 12949 | |
69024de8 ML |
12950 | intel_crtc_disable_planes(crtc); |
12951 | dev_priv->display.crtc_disable(crtc); | |
ea9d758d | 12952 | } |
a6778b3c | 12953 | |
ea9d758d DV |
12954 | /* Only after disabling all output pipelines that will be changed can we |
12955 | * update the the output configuration. */ | |
0a9ab303 | 12956 | intel_modeset_update_state(state); |
f6e5b160 | 12957 | |
a821fc46 ACO |
12958 | /* The state has been swaped above, so state actually contains the |
12959 | * old state now. */ | |
12960 | ||
304603f4 | 12961 | modeset_update_crtc_power_domains(state); |
47fab737 | 12962 | |
a6778b3c | 12963 | /* Now enable the clocks, plane, pipe, and connectors that we set up. */ |
0a9ab303 | 12964 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
5ac1c4bc ML |
12965 | drm_atomic_helper_commit_planes_on_crtc(crtc_state); |
12966 | ||
53d9f4e9 | 12967 | if (!needs_modeset(crtc->state) || !crtc->state->active) |
0a9ab303 ACO |
12968 | continue; |
12969 | ||
12970 | update_scanline_offset(to_intel_crtc(crtc)); | |
80715b2f | 12971 | |
0a9ab303 ACO |
12972 | dev_priv->display.crtc_enable(crtc); |
12973 | intel_crtc_enable_planes(crtc); | |
80715b2f | 12974 | } |
a6778b3c | 12975 | |
a6778b3c | 12976 | /* FIXME: add subpixel order */ |
83a57153 | 12977 | |
d4afb8cc ACO |
12978 | drm_atomic_helper_cleanup_planes(dev, state); |
12979 | ||
2bfb4627 ACO |
12980 | drm_atomic_state_free(state); |
12981 | ||
9eb45f22 | 12982 | return 0; |
f6e5b160 CW |
12983 | } |
12984 | ||
568c634a | 12985 | static int intel_set_mode_checked(struct drm_atomic_state *state) |
f30da187 | 12986 | { |
568c634a | 12987 | struct drm_device *dev = state->dev; |
f30da187 DV |
12988 | int ret; |
12989 | ||
568c634a | 12990 | ret = __intel_set_mode(state); |
f30da187 | 12991 | if (ret == 0) |
568c634a | 12992 | intel_modeset_check_state(dev); |
f30da187 DV |
12993 | |
12994 | return ret; | |
12995 | } | |
12996 | ||
568c634a | 12997 | static int intel_set_mode(struct drm_atomic_state *state) |
7f27126e | 12998 | { |
568c634a | 12999 | int ret; |
83a57153 | 13000 | |
568c634a | 13001 | ret = intel_modeset_compute_config(state); |
83a57153 | 13002 | if (ret) |
568c634a | 13003 | return ret; |
7f27126e | 13004 | |
568c634a | 13005 | return intel_set_mode_checked(state); |
7f27126e JB |
13006 | } |
13007 | ||
c0c36b94 CW |
13008 | void intel_crtc_restore_mode(struct drm_crtc *crtc) |
13009 | { | |
83a57153 ACO |
13010 | struct drm_device *dev = crtc->dev; |
13011 | struct drm_atomic_state *state; | |
4be07317 | 13012 | struct intel_crtc *intel_crtc; |
83a57153 ACO |
13013 | struct intel_encoder *encoder; |
13014 | struct intel_connector *connector; | |
13015 | struct drm_connector_state *connector_state; | |
4be07317 | 13016 | struct intel_crtc_state *crtc_state; |
2bfb4627 | 13017 | int ret; |
83a57153 ACO |
13018 | |
13019 | state = drm_atomic_state_alloc(dev); | |
13020 | if (!state) { | |
13021 | DRM_DEBUG_KMS("[CRTC:%d] mode restore failed, out of memory", | |
13022 | crtc->base.id); | |
13023 | return; | |
13024 | } | |
13025 | ||
13026 | state->acquire_ctx = dev->mode_config.acquire_ctx; | |
13027 | ||
13028 | /* The force restore path in the HW readout code relies on the staged | |
13029 | * config still keeping the user requested config while the actual | |
13030 | * state has been overwritten by the configuration read from HW. We | |
13031 | * need to copy the staged config to the atomic state, otherwise the | |
13032 | * mode set will just reapply the state the HW is already in. */ | |
13033 | for_each_intel_encoder(dev, encoder) { | |
37ade417 | 13034 | if (encoder->base.crtc != crtc) |
83a57153 ACO |
13035 | continue; |
13036 | ||
13037 | for_each_intel_connector(dev, connector) { | |
37ade417 | 13038 | if (connector->base.state->best_encoder != &encoder->base) |
83a57153 ACO |
13039 | continue; |
13040 | ||
13041 | connector_state = drm_atomic_get_connector_state(state, &connector->base); | |
13042 | if (IS_ERR(connector_state)) { | |
13043 | DRM_DEBUG_KMS("Failed to add [CONNECTOR:%d:%s] to state: %ld\n", | |
13044 | connector->base.base.id, | |
13045 | connector->base.name, | |
13046 | PTR_ERR(connector_state)); | |
13047 | continue; | |
13048 | } | |
13049 | ||
13050 | connector_state->crtc = crtc; | |
83a57153 ACO |
13051 | } |
13052 | } | |
13053 | ||
4be07317 | 13054 | for_each_intel_crtc(dev, intel_crtc) { |
4be07317 ACO |
13055 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); |
13056 | if (IS_ERR(crtc_state)) { | |
13057 | DRM_DEBUG_KMS("Failed to add [CRTC:%d] to state: %ld\n", | |
13058 | intel_crtc->base.base.id, | |
13059 | PTR_ERR(crtc_state)); | |
13060 | continue; | |
13061 | } | |
13062 | ||
8c7b5ccb ACO |
13063 | if (&intel_crtc->base == crtc) |
13064 | drm_mode_copy(&crtc_state->base.mode, &crtc->mode); | |
4be07317 ACO |
13065 | } |
13066 | ||
d3a40d1b ACO |
13067 | intel_modeset_setup_plane_state(state, crtc, &crtc->mode, |
13068 | crtc->primary->fb, crtc->x, crtc->y); | |
13069 | ||
568c634a | 13070 | ret = intel_set_mode(state); |
2bfb4627 ACO |
13071 | if (ret) |
13072 | drm_atomic_state_free(state); | |
c0c36b94 CW |
13073 | } |
13074 | ||
25c5b266 DV |
13075 | #undef for_each_intel_crtc_masked |
13076 | ||
b7885264 ACO |
13077 | static bool intel_connector_in_mode_set(struct intel_connector *connector, |
13078 | struct drm_mode_set *set) | |
13079 | { | |
13080 | int ro; | |
13081 | ||
13082 | for (ro = 0; ro < set->num_connectors; ro++) | |
13083 | if (set->connectors[ro] == &connector->base) | |
13084 | return true; | |
13085 | ||
13086 | return false; | |
13087 | } | |
13088 | ||
2e431051 | 13089 | static int |
9a935856 DV |
13090 | intel_modeset_stage_output_state(struct drm_device *dev, |
13091 | struct drm_mode_set *set, | |
944b0c76 | 13092 | struct drm_atomic_state *state) |
50f56119 | 13093 | { |
9a935856 | 13094 | struct intel_connector *connector; |
d5432a9d | 13095 | struct drm_connector *drm_connector; |
944b0c76 | 13096 | struct drm_connector_state *connector_state; |
d5432a9d ACO |
13097 | struct drm_crtc *crtc; |
13098 | struct drm_crtc_state *crtc_state; | |
13099 | int i, ret; | |
50f56119 | 13100 | |
9abdda74 | 13101 | /* The upper layers ensure that we either disable a crtc or have a list |
9a935856 DV |
13102 | * of connectors. For paranoia, double-check this. */ |
13103 | WARN_ON(!set->fb && (set->num_connectors != 0)); | |
13104 | WARN_ON(set->fb && (set->num_connectors == 0)); | |
13105 | ||
3a3371ff | 13106 | for_each_intel_connector(dev, connector) { |
b7885264 ACO |
13107 | bool in_mode_set = intel_connector_in_mode_set(connector, set); |
13108 | ||
d5432a9d ACO |
13109 | if (!in_mode_set && connector->base.state->crtc != set->crtc) |
13110 | continue; | |
13111 | ||
13112 | connector_state = | |
13113 | drm_atomic_get_connector_state(state, &connector->base); | |
13114 | if (IS_ERR(connector_state)) | |
13115 | return PTR_ERR(connector_state); | |
13116 | ||
b7885264 ACO |
13117 | if (in_mode_set) { |
13118 | int pipe = to_intel_crtc(set->crtc)->pipe; | |
d5432a9d ACO |
13119 | connector_state->best_encoder = |
13120 | &intel_find_encoder(connector, pipe)->base; | |
50f56119 DV |
13121 | } |
13122 | ||
d5432a9d | 13123 | if (connector->base.state->crtc != set->crtc) |
b7885264 ACO |
13124 | continue; |
13125 | ||
9a935856 DV |
13126 | /* If we disable the crtc, disable all its connectors. Also, if |
13127 | * the connector is on the changing crtc but not on the new | |
13128 | * connector list, disable it. */ | |
b7885264 | 13129 | if (!set->fb || !in_mode_set) { |
d5432a9d | 13130 | connector_state->best_encoder = NULL; |
9a935856 DV |
13131 | |
13132 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n", | |
13133 | connector->base.base.id, | |
c23cc417 | 13134 | connector->base.name); |
9a935856 | 13135 | } |
50f56119 | 13136 | } |
9a935856 | 13137 | /* connector->new_encoder is now updated for all connectors. */ |
50f56119 | 13138 | |
d5432a9d ACO |
13139 | for_each_connector_in_state(state, drm_connector, connector_state, i) { |
13140 | connector = to_intel_connector(drm_connector); | |
13141 | ||
13142 | if (!connector_state->best_encoder) { | |
13143 | ret = drm_atomic_set_crtc_for_connector(connector_state, | |
13144 | NULL); | |
13145 | if (ret) | |
13146 | return ret; | |
7668851f | 13147 | |
50f56119 | 13148 | continue; |
d5432a9d | 13149 | } |
50f56119 | 13150 | |
d5432a9d ACO |
13151 | if (intel_connector_in_mode_set(connector, set)) { |
13152 | struct drm_crtc *crtc = connector->base.state->crtc; | |
13153 | ||
13154 | /* If this connector was in a previous crtc, add it | |
13155 | * to the state. We might need to disable it. */ | |
13156 | if (crtc) { | |
13157 | crtc_state = | |
13158 | drm_atomic_get_crtc_state(state, crtc); | |
13159 | if (IS_ERR(crtc_state)) | |
13160 | return PTR_ERR(crtc_state); | |
13161 | } | |
13162 | ||
13163 | ret = drm_atomic_set_crtc_for_connector(connector_state, | |
13164 | set->crtc); | |
13165 | if (ret) | |
13166 | return ret; | |
13167 | } | |
50f56119 DV |
13168 | |
13169 | /* Make sure the new CRTC will work with the encoder */ | |
d5432a9d ACO |
13170 | if (!drm_encoder_crtc_ok(connector_state->best_encoder, |
13171 | connector_state->crtc)) { | |
5e2b584e | 13172 | return -EINVAL; |
50f56119 | 13173 | } |
944b0c76 | 13174 | |
9a935856 DV |
13175 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n", |
13176 | connector->base.base.id, | |
c23cc417 | 13177 | connector->base.name, |
d5432a9d | 13178 | connector_state->crtc->base.id); |
944b0c76 | 13179 | |
d5432a9d ACO |
13180 | if (connector_state->best_encoder != &connector->encoder->base) |
13181 | connector->encoder = | |
13182 | to_intel_encoder(connector_state->best_encoder); | |
0e32b39c | 13183 | } |
7668851f | 13184 | |
d5432a9d | 13185 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
49d6fa21 ML |
13186 | bool has_connectors; |
13187 | ||
d5432a9d ACO |
13188 | ret = drm_atomic_add_affected_connectors(state, crtc); |
13189 | if (ret) | |
13190 | return ret; | |
4be07317 | 13191 | |
49d6fa21 ML |
13192 | has_connectors = !!drm_atomic_connectors_for_crtc(state, crtc); |
13193 | if (has_connectors != crtc_state->enable) | |
13194 | crtc_state->enable = | |
13195 | crtc_state->active = has_connectors; | |
7668851f VS |
13196 | } |
13197 | ||
8c7b5ccb ACO |
13198 | ret = intel_modeset_setup_plane_state(state, set->crtc, set->mode, |
13199 | set->fb, set->x, set->y); | |
13200 | if (ret) | |
13201 | return ret; | |
13202 | ||
13203 | crtc_state = drm_atomic_get_crtc_state(state, set->crtc); | |
13204 | if (IS_ERR(crtc_state)) | |
13205 | return PTR_ERR(crtc_state); | |
13206 | ||
13207 | if (set->mode) | |
13208 | drm_mode_copy(&crtc_state->mode, set->mode); | |
13209 | ||
13210 | if (set->num_connectors) | |
13211 | crtc_state->active = true; | |
13212 | ||
2e431051 DV |
13213 | return 0; |
13214 | } | |
13215 | ||
13216 | static int intel_crtc_set_config(struct drm_mode_set *set) | |
13217 | { | |
13218 | struct drm_device *dev; | |
83a57153 | 13219 | struct drm_atomic_state *state = NULL; |
2e431051 | 13220 | int ret; |
2e431051 | 13221 | |
8d3e375e DV |
13222 | BUG_ON(!set); |
13223 | BUG_ON(!set->crtc); | |
13224 | BUG_ON(!set->crtc->helper_private); | |
2e431051 | 13225 | |
7e53f3a4 DV |
13226 | /* Enforce sane interface api - has been abused by the fb helper. */ |
13227 | BUG_ON(!set->mode && set->fb); | |
13228 | BUG_ON(set->fb && set->num_connectors == 0); | |
431e50f7 | 13229 | |
2e431051 DV |
13230 | if (set->fb) { |
13231 | DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n", | |
13232 | set->crtc->base.id, set->fb->base.id, | |
13233 | (int)set->num_connectors, set->x, set->y); | |
13234 | } else { | |
13235 | DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id); | |
2e431051 DV |
13236 | } |
13237 | ||
13238 | dev = set->crtc->dev; | |
13239 | ||
83a57153 | 13240 | state = drm_atomic_state_alloc(dev); |
7cbf41d6 ACO |
13241 | if (!state) |
13242 | return -ENOMEM; | |
83a57153 ACO |
13243 | |
13244 | state->acquire_ctx = dev->mode_config.acquire_ctx; | |
13245 | ||
462a425a | 13246 | ret = intel_modeset_stage_output_state(dev, set, state); |
2e431051 | 13247 | if (ret) |
7cbf41d6 | 13248 | goto out; |
2e431051 | 13249 | |
568c634a ACO |
13250 | ret = intel_modeset_compute_config(state); |
13251 | if (ret) | |
7cbf41d6 | 13252 | goto out; |
50f52756 | 13253 | |
1f9954d0 JB |
13254 | intel_update_pipe_size(to_intel_crtc(set->crtc)); |
13255 | ||
568c634a | 13256 | ret = intel_set_mode_checked(state); |
2d05eae1 | 13257 | if (ret) { |
bf67dfeb DV |
13258 | DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n", |
13259 | set->crtc->base.id, ret); | |
2d05eae1 | 13260 | } |
50f56119 | 13261 | |
7cbf41d6 | 13262 | out: |
2bfb4627 ACO |
13263 | if (ret) |
13264 | drm_atomic_state_free(state); | |
50f56119 DV |
13265 | return ret; |
13266 | } | |
f6e5b160 CW |
13267 | |
13268 | static const struct drm_crtc_funcs intel_crtc_funcs = { | |
f6e5b160 | 13269 | .gamma_set = intel_crtc_gamma_set, |
50f56119 | 13270 | .set_config = intel_crtc_set_config, |
f6e5b160 CW |
13271 | .destroy = intel_crtc_destroy, |
13272 | .page_flip = intel_crtc_page_flip, | |
1356837e MR |
13273 | .atomic_duplicate_state = intel_crtc_duplicate_state, |
13274 | .atomic_destroy_state = intel_crtc_destroy_state, | |
f6e5b160 CW |
13275 | }; |
13276 | ||
5358901f DV |
13277 | static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv, |
13278 | struct intel_shared_dpll *pll, | |
13279 | struct intel_dpll_hw_state *hw_state) | |
ee7b9f93 | 13280 | { |
5358901f | 13281 | uint32_t val; |
ee7b9f93 | 13282 | |
f458ebbc | 13283 | if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS)) |
bd2bb1b9 PZ |
13284 | return false; |
13285 | ||
5358901f | 13286 | val = I915_READ(PCH_DPLL(pll->id)); |
66e985c0 DV |
13287 | hw_state->dpll = val; |
13288 | hw_state->fp0 = I915_READ(PCH_FP0(pll->id)); | |
13289 | hw_state->fp1 = I915_READ(PCH_FP1(pll->id)); | |
5358901f DV |
13290 | |
13291 | return val & DPLL_VCO_ENABLE; | |
13292 | } | |
13293 | ||
15bdd4cf DV |
13294 | static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv, |
13295 | struct intel_shared_dpll *pll) | |
13296 | { | |
3e369b76 ACO |
13297 | I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0); |
13298 | I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1); | |
15bdd4cf DV |
13299 | } |
13300 | ||
e7b903d2 DV |
13301 | static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv, |
13302 | struct intel_shared_dpll *pll) | |
13303 | { | |
e7b903d2 | 13304 | /* PCH refclock must be enabled first */ |
89eff4be | 13305 | ibx_assert_pch_refclk_enabled(dev_priv); |
e7b903d2 | 13306 | |
3e369b76 | 13307 | I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll); |
15bdd4cf DV |
13308 | |
13309 | /* Wait for the clocks to stabilize. */ | |
13310 | POSTING_READ(PCH_DPLL(pll->id)); | |
13311 | udelay(150); | |
13312 | ||
13313 | /* The pixel multiplier can only be updated once the | |
13314 | * DPLL is enabled and the clocks are stable. | |
13315 | * | |
13316 | * So write it again. | |
13317 | */ | |
3e369b76 | 13318 | I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll); |
15bdd4cf | 13319 | POSTING_READ(PCH_DPLL(pll->id)); |
e7b903d2 DV |
13320 | udelay(200); |
13321 | } | |
13322 | ||
13323 | static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv, | |
13324 | struct intel_shared_dpll *pll) | |
13325 | { | |
13326 | struct drm_device *dev = dev_priv->dev; | |
13327 | struct intel_crtc *crtc; | |
e7b903d2 DV |
13328 | |
13329 | /* Make sure no transcoder isn't still depending on us. */ | |
d3fcc808 | 13330 | for_each_intel_crtc(dev, crtc) { |
e7b903d2 DV |
13331 | if (intel_crtc_to_shared_dpll(crtc) == pll) |
13332 | assert_pch_transcoder_disabled(dev_priv, crtc->pipe); | |
ee7b9f93 JB |
13333 | } |
13334 | ||
15bdd4cf DV |
13335 | I915_WRITE(PCH_DPLL(pll->id), 0); |
13336 | POSTING_READ(PCH_DPLL(pll->id)); | |
e7b903d2 DV |
13337 | udelay(200); |
13338 | } | |
13339 | ||
46edb027 DV |
13340 | static char *ibx_pch_dpll_names[] = { |
13341 | "PCH DPLL A", | |
13342 | "PCH DPLL B", | |
13343 | }; | |
13344 | ||
7c74ade1 | 13345 | static void ibx_pch_dpll_init(struct drm_device *dev) |
ee7b9f93 | 13346 | { |
e7b903d2 | 13347 | struct drm_i915_private *dev_priv = dev->dev_private; |
ee7b9f93 JB |
13348 | int i; |
13349 | ||
7c74ade1 | 13350 | dev_priv->num_shared_dpll = 2; |
ee7b9f93 | 13351 | |
e72f9fbf | 13352 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
46edb027 DV |
13353 | dev_priv->shared_dplls[i].id = i; |
13354 | dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i]; | |
15bdd4cf | 13355 | dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set; |
e7b903d2 DV |
13356 | dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable; |
13357 | dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable; | |
5358901f DV |
13358 | dev_priv->shared_dplls[i].get_hw_state = |
13359 | ibx_pch_dpll_get_hw_state; | |
ee7b9f93 JB |
13360 | } |
13361 | } | |
13362 | ||
7c74ade1 DV |
13363 | static void intel_shared_dpll_init(struct drm_device *dev) |
13364 | { | |
e7b903d2 | 13365 | struct drm_i915_private *dev_priv = dev->dev_private; |
7c74ade1 | 13366 | |
b6283055 VS |
13367 | intel_update_cdclk(dev); |
13368 | ||
9cd86933 DV |
13369 | if (HAS_DDI(dev)) |
13370 | intel_ddi_pll_init(dev); | |
13371 | else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
7c74ade1 DV |
13372 | ibx_pch_dpll_init(dev); |
13373 | else | |
13374 | dev_priv->num_shared_dpll = 0; | |
13375 | ||
13376 | BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS); | |
7c74ade1 DV |
13377 | } |
13378 | ||
1fc0a8f7 TU |
13379 | /** |
13380 | * intel_wm_need_update - Check whether watermarks need updating | |
13381 | * @plane: drm plane | |
13382 | * @state: new plane state | |
13383 | * | |
13384 | * Check current plane state versus the new one to determine whether | |
13385 | * watermarks need to be recalculated. | |
13386 | * | |
13387 | * Returns true or false. | |
13388 | */ | |
13389 | bool intel_wm_need_update(struct drm_plane *plane, | |
13390 | struct drm_plane_state *state) | |
13391 | { | |
13392 | /* Update watermarks on tiling changes. */ | |
13393 | if (!plane->state->fb || !state->fb || | |
13394 | plane->state->fb->modifier[0] != state->fb->modifier[0] || | |
13395 | plane->state->rotation != state->rotation) | |
13396 | return true; | |
13397 | ||
13398 | return false; | |
13399 | } | |
13400 | ||
6beb8c23 MR |
13401 | /** |
13402 | * intel_prepare_plane_fb - Prepare fb for usage on plane | |
13403 | * @plane: drm plane to prepare for | |
13404 | * @fb: framebuffer to prepare for presentation | |
13405 | * | |
13406 | * Prepares a framebuffer for usage on a display plane. Generally this | |
13407 | * involves pinning the underlying object and updating the frontbuffer tracking | |
13408 | * bits. Some older platforms need special physical address handling for | |
13409 | * cursor planes. | |
13410 | * | |
13411 | * Returns 0 on success, negative error code on failure. | |
13412 | */ | |
13413 | int | |
13414 | intel_prepare_plane_fb(struct drm_plane *plane, | |
d136dfee TU |
13415 | struct drm_framebuffer *fb, |
13416 | const struct drm_plane_state *new_state) | |
465c120c MR |
13417 | { |
13418 | struct drm_device *dev = plane->dev; | |
6beb8c23 MR |
13419 | struct intel_plane *intel_plane = to_intel_plane(plane); |
13420 | enum pipe pipe = intel_plane->pipe; | |
13421 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
13422 | struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb); | |
13423 | unsigned frontbuffer_bits = 0; | |
13424 | int ret = 0; | |
465c120c | 13425 | |
ea2c67bb | 13426 | if (!obj) |
465c120c MR |
13427 | return 0; |
13428 | ||
6beb8c23 MR |
13429 | switch (plane->type) { |
13430 | case DRM_PLANE_TYPE_PRIMARY: | |
13431 | frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(pipe); | |
13432 | break; | |
13433 | case DRM_PLANE_TYPE_CURSOR: | |
13434 | frontbuffer_bits = INTEL_FRONTBUFFER_CURSOR(pipe); | |
13435 | break; | |
13436 | case DRM_PLANE_TYPE_OVERLAY: | |
13437 | frontbuffer_bits = INTEL_FRONTBUFFER_SPRITE(pipe); | |
13438 | break; | |
13439 | } | |
465c120c | 13440 | |
6beb8c23 | 13441 | mutex_lock(&dev->struct_mutex); |
465c120c | 13442 | |
6beb8c23 MR |
13443 | if (plane->type == DRM_PLANE_TYPE_CURSOR && |
13444 | INTEL_INFO(dev)->cursor_needs_physical) { | |
13445 | int align = IS_I830(dev) ? 16 * 1024 : 256; | |
13446 | ret = i915_gem_object_attach_phys(obj, align); | |
13447 | if (ret) | |
13448 | DRM_DEBUG_KMS("failed to attach phys object\n"); | |
13449 | } else { | |
82bc3b2d | 13450 | ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL); |
6beb8c23 | 13451 | } |
465c120c | 13452 | |
6beb8c23 MR |
13453 | if (ret == 0) |
13454 | i915_gem_track_fb(old_obj, obj, frontbuffer_bits); | |
fdd508a6 | 13455 | |
4c34574f | 13456 | mutex_unlock(&dev->struct_mutex); |
465c120c | 13457 | |
6beb8c23 MR |
13458 | return ret; |
13459 | } | |
13460 | ||
38f3ce3a MR |
13461 | /** |
13462 | * intel_cleanup_plane_fb - Cleans up an fb after plane use | |
13463 | * @plane: drm plane to clean up for | |
13464 | * @fb: old framebuffer that was on plane | |
13465 | * | |
13466 | * Cleans up a framebuffer that has just been removed from a plane. | |
13467 | */ | |
13468 | void | |
13469 | intel_cleanup_plane_fb(struct drm_plane *plane, | |
d136dfee TU |
13470 | struct drm_framebuffer *fb, |
13471 | const struct drm_plane_state *old_state) | |
38f3ce3a MR |
13472 | { |
13473 | struct drm_device *dev = plane->dev; | |
13474 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
13475 | ||
13476 | if (WARN_ON(!obj)) | |
13477 | return; | |
13478 | ||
13479 | if (plane->type != DRM_PLANE_TYPE_CURSOR || | |
13480 | !INTEL_INFO(dev)->cursor_needs_physical) { | |
13481 | mutex_lock(&dev->struct_mutex); | |
82bc3b2d | 13482 | intel_unpin_fb_obj(fb, old_state); |
38f3ce3a MR |
13483 | mutex_unlock(&dev->struct_mutex); |
13484 | } | |
465c120c MR |
13485 | } |
13486 | ||
6156a456 CK |
13487 | int |
13488 | skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state) | |
13489 | { | |
13490 | int max_scale; | |
13491 | struct drm_device *dev; | |
13492 | struct drm_i915_private *dev_priv; | |
13493 | int crtc_clock, cdclk; | |
13494 | ||
13495 | if (!intel_crtc || !crtc_state) | |
13496 | return DRM_PLANE_HELPER_NO_SCALING; | |
13497 | ||
13498 | dev = intel_crtc->base.dev; | |
13499 | dev_priv = dev->dev_private; | |
13500 | crtc_clock = crtc_state->base.adjusted_mode.crtc_clock; | |
13501 | cdclk = dev_priv->display.get_display_clock_speed(dev); | |
13502 | ||
13503 | if (!crtc_clock || !cdclk) | |
13504 | return DRM_PLANE_HELPER_NO_SCALING; | |
13505 | ||
13506 | /* | |
13507 | * skl max scale is lower of: | |
13508 | * close to 3 but not 3, -1 is for that purpose | |
13509 | * or | |
13510 | * cdclk/crtc_clock | |
13511 | */ | |
13512 | max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock)); | |
13513 | ||
13514 | return max_scale; | |
13515 | } | |
13516 | ||
465c120c | 13517 | static int |
3c692a41 GP |
13518 | intel_check_primary_plane(struct drm_plane *plane, |
13519 | struct intel_plane_state *state) | |
13520 | { | |
32b7eeec MR |
13521 | struct drm_device *dev = plane->dev; |
13522 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2b875c22 | 13523 | struct drm_crtc *crtc = state->base.crtc; |
ea2c67bb | 13524 | struct intel_crtc *intel_crtc; |
6156a456 | 13525 | struct intel_crtc_state *crtc_state; |
2b875c22 | 13526 | struct drm_framebuffer *fb = state->base.fb; |
3c692a41 GP |
13527 | struct drm_rect *dest = &state->dst; |
13528 | struct drm_rect *src = &state->src; | |
13529 | const struct drm_rect *clip = &state->clip; | |
d8106366 | 13530 | bool can_position = false; |
6156a456 CK |
13531 | int max_scale = DRM_PLANE_HELPER_NO_SCALING; |
13532 | int min_scale = DRM_PLANE_HELPER_NO_SCALING; | |
465c120c MR |
13533 | int ret; |
13534 | ||
ea2c67bb MR |
13535 | crtc = crtc ? crtc : plane->crtc; |
13536 | intel_crtc = to_intel_crtc(crtc); | |
6156a456 CK |
13537 | crtc_state = state->base.state ? |
13538 | intel_atomic_get_crtc_state(state->base.state, intel_crtc) : NULL; | |
ea2c67bb | 13539 | |
6156a456 | 13540 | if (INTEL_INFO(dev)->gen >= 9) { |
225c228a CK |
13541 | /* use scaler when colorkey is not required */ |
13542 | if (to_intel_plane(plane)->ckey.flags == I915_SET_COLORKEY_NONE) { | |
13543 | min_scale = 1; | |
13544 | max_scale = skl_max_scale(intel_crtc, crtc_state); | |
13545 | } | |
d8106366 | 13546 | can_position = true; |
6156a456 | 13547 | } |
d8106366 | 13548 | |
c59cb179 MR |
13549 | ret = drm_plane_helper_check_update(plane, crtc, fb, |
13550 | src, dest, clip, | |
6156a456 CK |
13551 | min_scale, |
13552 | max_scale, | |
d8106366 SJ |
13553 | can_position, true, |
13554 | &state->visible); | |
c59cb179 MR |
13555 | if (ret) |
13556 | return ret; | |
465c120c | 13557 | |
32b7eeec | 13558 | if (intel_crtc->active) { |
b70709a6 ML |
13559 | struct intel_plane_state *old_state = |
13560 | to_intel_plane_state(plane->state); | |
13561 | ||
32b7eeec MR |
13562 | intel_crtc->atomic.wait_for_flips = true; |
13563 | ||
13564 | /* | |
13565 | * FBC does not work on some platforms for rotated | |
13566 | * planes, so disable it when rotation is not 0 and | |
13567 | * update it when rotation is set back to 0. | |
13568 | * | |
13569 | * FIXME: This is redundant with the fbc update done in | |
13570 | * the primary plane enable function except that that | |
13571 | * one is done too late. We eventually need to unify | |
13572 | * this. | |
13573 | */ | |
b70709a6 | 13574 | if (state->visible && |
32b7eeec | 13575 | INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) && |
e35fef21 | 13576 | dev_priv->fbc.crtc == intel_crtc && |
8e7d688b | 13577 | state->base.rotation != BIT(DRM_ROTATE_0)) { |
32b7eeec MR |
13578 | intel_crtc->atomic.disable_fbc = true; |
13579 | } | |
13580 | ||
b70709a6 | 13581 | if (state->visible && !old_state->visible) { |
32b7eeec MR |
13582 | /* |
13583 | * BDW signals flip done immediately if the plane | |
13584 | * is disabled, even if the plane enable is already | |
13585 | * armed to occur at the next vblank :( | |
13586 | */ | |
b70709a6 | 13587 | if (IS_BROADWELL(dev)) |
32b7eeec | 13588 | intel_crtc->atomic.wait_vblank = true; |
fb9d6cf8 ML |
13589 | |
13590 | if (crtc_state && !needs_modeset(&crtc_state->base)) | |
13591 | intel_crtc->atomic.post_enable_primary = true; | |
32b7eeec MR |
13592 | } |
13593 | ||
fb9d6cf8 ML |
13594 | if (!state->visible && old_state->visible && |
13595 | crtc_state && !needs_modeset(&crtc_state->base)) | |
13596 | intel_crtc->atomic.pre_disable_primary = true; | |
13597 | ||
32b7eeec MR |
13598 | intel_crtc->atomic.fb_bits |= |
13599 | INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe); | |
13600 | ||
13601 | intel_crtc->atomic.update_fbc = true; | |
0fda6568 | 13602 | |
1fc0a8f7 | 13603 | if (intel_wm_need_update(plane, &state->base)) |
0fda6568 | 13604 | intel_crtc->atomic.update_wm = true; |
ccc759dc GP |
13605 | } |
13606 | ||
6156a456 CK |
13607 | if (INTEL_INFO(dev)->gen >= 9) { |
13608 | ret = skl_update_scaler_users(intel_crtc, crtc_state, | |
13609 | to_intel_plane(plane), state, 0); | |
13610 | if (ret) | |
13611 | return ret; | |
13612 | } | |
13613 | ||
14af293f GP |
13614 | return 0; |
13615 | } | |
13616 | ||
13617 | static void | |
13618 | intel_commit_primary_plane(struct drm_plane *plane, | |
13619 | struct intel_plane_state *state) | |
13620 | { | |
2b875c22 MR |
13621 | struct drm_crtc *crtc = state->base.crtc; |
13622 | struct drm_framebuffer *fb = state->base.fb; | |
13623 | struct drm_device *dev = plane->dev; | |
14af293f | 13624 | struct drm_i915_private *dev_priv = dev->dev_private; |
ea2c67bb | 13625 | struct intel_crtc *intel_crtc; |
14af293f GP |
13626 | struct drm_rect *src = &state->src; |
13627 | ||
ea2c67bb MR |
13628 | crtc = crtc ? crtc : plane->crtc; |
13629 | intel_crtc = to_intel_crtc(crtc); | |
cf4c7c12 MR |
13630 | |
13631 | plane->fb = fb; | |
9dc806fc MR |
13632 | crtc->x = src->x1 >> 16; |
13633 | crtc->y = src->y1 >> 16; | |
ccc759dc | 13634 | |
ccc759dc | 13635 | if (intel_crtc->active) { |
27321ae8 | 13636 | if (state->visible) |
ccc759dc GP |
13637 | /* FIXME: kill this fastboot hack */ |
13638 | intel_update_pipe_size(intel_crtc); | |
465c120c | 13639 | |
27321ae8 ML |
13640 | dev_priv->display.update_primary_plane(crtc, plane->fb, |
13641 | crtc->x, crtc->y); | |
ccc759dc | 13642 | } |
465c120c MR |
13643 | } |
13644 | ||
a8ad0d8e ML |
13645 | static void |
13646 | intel_disable_primary_plane(struct drm_plane *plane, | |
13647 | struct drm_crtc *crtc, | |
13648 | bool force) | |
13649 | { | |
13650 | struct drm_device *dev = plane->dev; | |
13651 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13652 | ||
a8ad0d8e ML |
13653 | dev_priv->display.update_primary_plane(crtc, NULL, 0, 0); |
13654 | } | |
13655 | ||
32b7eeec | 13656 | static void intel_begin_crtc_commit(struct drm_crtc *crtc) |
3c692a41 | 13657 | { |
32b7eeec | 13658 | struct drm_device *dev = crtc->dev; |
140fd38d | 13659 | struct drm_i915_private *dev_priv = dev->dev_private; |
3c692a41 | 13660 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5c2db188 | 13661 | struct drm_crtc_state *crtc_state = intel_crtc->base.state; |
ea2c67bb MR |
13662 | struct intel_plane *intel_plane; |
13663 | struct drm_plane *p; | |
13664 | unsigned fb_bits = 0; | |
13665 | ||
13666 | /* Track fb's for any planes being disabled */ | |
13667 | list_for_each_entry(p, &dev->mode_config.plane_list, head) { | |
13668 | intel_plane = to_intel_plane(p); | |
13669 | ||
13670 | if (intel_crtc->atomic.disabled_planes & | |
13671 | (1 << drm_plane_index(p))) { | |
13672 | switch (p->type) { | |
13673 | case DRM_PLANE_TYPE_PRIMARY: | |
13674 | fb_bits = INTEL_FRONTBUFFER_PRIMARY(intel_plane->pipe); | |
13675 | break; | |
13676 | case DRM_PLANE_TYPE_CURSOR: | |
13677 | fb_bits = INTEL_FRONTBUFFER_CURSOR(intel_plane->pipe); | |
13678 | break; | |
13679 | case DRM_PLANE_TYPE_OVERLAY: | |
13680 | fb_bits = INTEL_FRONTBUFFER_SPRITE(intel_plane->pipe); | |
13681 | break; | |
13682 | } | |
3c692a41 | 13683 | |
ea2c67bb MR |
13684 | mutex_lock(&dev->struct_mutex); |
13685 | i915_gem_track_fb(intel_fb_obj(p->fb), NULL, fb_bits); | |
13686 | mutex_unlock(&dev->struct_mutex); | |
13687 | } | |
13688 | } | |
3c692a41 | 13689 | |
32b7eeec MR |
13690 | if (intel_crtc->atomic.wait_for_flips) |
13691 | intel_crtc_wait_for_pending_flips(crtc); | |
3c692a41 | 13692 | |
32b7eeec MR |
13693 | if (intel_crtc->atomic.disable_fbc) |
13694 | intel_fbc_disable(dev); | |
3c692a41 | 13695 | |
32b7eeec MR |
13696 | if (intel_crtc->atomic.pre_disable_primary) |
13697 | intel_pre_disable_primary(crtc); | |
3c692a41 | 13698 | |
32b7eeec MR |
13699 | if (intel_crtc->atomic.update_wm) |
13700 | intel_update_watermarks(crtc); | |
3c692a41 | 13701 | |
32b7eeec | 13702 | intel_runtime_pm_get(dev_priv); |
3c692a41 | 13703 | |
c34c9ee4 | 13704 | /* Perform vblank evasion around commit operation */ |
5c2db188 | 13705 | if (crtc_state->active && !needs_modeset(crtc_state)) |
c34c9ee4 MR |
13706 | intel_crtc->atomic.evade = |
13707 | intel_pipe_update_start(intel_crtc, | |
13708 | &intel_crtc->atomic.start_vbl_count); | |
32b7eeec MR |
13709 | } |
13710 | ||
13711 | static void intel_finish_crtc_commit(struct drm_crtc *crtc) | |
13712 | { | |
13713 | struct drm_device *dev = crtc->dev; | |
13714 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13715 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
13716 | struct drm_plane *p; | |
13717 | ||
c34c9ee4 MR |
13718 | if (intel_crtc->atomic.evade) |
13719 | intel_pipe_update_end(intel_crtc, | |
13720 | intel_crtc->atomic.start_vbl_count); | |
3c692a41 | 13721 | |
140fd38d | 13722 | intel_runtime_pm_put(dev_priv); |
3c692a41 | 13723 | |
8a8f7f44 | 13724 | if (intel_crtc->atomic.wait_vblank && intel_crtc->active) |
32b7eeec MR |
13725 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
13726 | ||
13727 | intel_frontbuffer_flip(dev, intel_crtc->atomic.fb_bits); | |
13728 | ||
13729 | if (intel_crtc->atomic.update_fbc) { | |
ccc759dc | 13730 | mutex_lock(&dev->struct_mutex); |
7ff0ebcc | 13731 | intel_fbc_update(dev); |
ccc759dc | 13732 | mutex_unlock(&dev->struct_mutex); |
38f3ce3a | 13733 | } |
3c692a41 | 13734 | |
32b7eeec MR |
13735 | if (intel_crtc->atomic.post_enable_primary) |
13736 | intel_post_enable_primary(crtc); | |
3c692a41 | 13737 | |
32b7eeec MR |
13738 | drm_for_each_legacy_plane(p, &dev->mode_config.plane_list) |
13739 | if (intel_crtc->atomic.update_sprite_watermarks & drm_plane_index(p)) | |
13740 | intel_update_sprite_watermarks(p, crtc, 0, 0, 0, | |
13741 | false, false); | |
13742 | ||
13743 | memset(&intel_crtc->atomic, 0, sizeof(intel_crtc->atomic)); | |
3c692a41 GP |
13744 | } |
13745 | ||
cf4c7c12 | 13746 | /** |
4a3b8769 MR |
13747 | * intel_plane_destroy - destroy a plane |
13748 | * @plane: plane to destroy | |
cf4c7c12 | 13749 | * |
4a3b8769 MR |
13750 | * Common destruction function for all types of planes (primary, cursor, |
13751 | * sprite). | |
cf4c7c12 | 13752 | */ |
4a3b8769 | 13753 | void intel_plane_destroy(struct drm_plane *plane) |
465c120c MR |
13754 | { |
13755 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
13756 | drm_plane_cleanup(plane); | |
13757 | kfree(intel_plane); | |
13758 | } | |
13759 | ||
65a3fea0 | 13760 | const struct drm_plane_funcs intel_plane_funcs = { |
70a101f8 MR |
13761 | .update_plane = drm_atomic_helper_update_plane, |
13762 | .disable_plane = drm_atomic_helper_disable_plane, | |
3d7d6510 | 13763 | .destroy = intel_plane_destroy, |
c196e1d6 | 13764 | .set_property = drm_atomic_helper_plane_set_property, |
a98b3431 MR |
13765 | .atomic_get_property = intel_plane_atomic_get_property, |
13766 | .atomic_set_property = intel_plane_atomic_set_property, | |
ea2c67bb MR |
13767 | .atomic_duplicate_state = intel_plane_duplicate_state, |
13768 | .atomic_destroy_state = intel_plane_destroy_state, | |
13769 | ||
465c120c MR |
13770 | }; |
13771 | ||
13772 | static struct drm_plane *intel_primary_plane_create(struct drm_device *dev, | |
13773 | int pipe) | |
13774 | { | |
13775 | struct intel_plane *primary; | |
8e7d688b | 13776 | struct intel_plane_state *state; |
465c120c MR |
13777 | const uint32_t *intel_primary_formats; |
13778 | int num_formats; | |
13779 | ||
13780 | primary = kzalloc(sizeof(*primary), GFP_KERNEL); | |
13781 | if (primary == NULL) | |
13782 | return NULL; | |
13783 | ||
8e7d688b MR |
13784 | state = intel_create_plane_state(&primary->base); |
13785 | if (!state) { | |
ea2c67bb MR |
13786 | kfree(primary); |
13787 | return NULL; | |
13788 | } | |
8e7d688b | 13789 | primary->base.state = &state->base; |
ea2c67bb | 13790 | |
465c120c MR |
13791 | primary->can_scale = false; |
13792 | primary->max_downscale = 1; | |
6156a456 CK |
13793 | if (INTEL_INFO(dev)->gen >= 9) { |
13794 | primary->can_scale = true; | |
af99ceda | 13795 | state->scaler_id = -1; |
6156a456 | 13796 | } |
465c120c MR |
13797 | primary->pipe = pipe; |
13798 | primary->plane = pipe; | |
c59cb179 MR |
13799 | primary->check_plane = intel_check_primary_plane; |
13800 | primary->commit_plane = intel_commit_primary_plane; | |
a8ad0d8e | 13801 | primary->disable_plane = intel_disable_primary_plane; |
08e221fb | 13802 | primary->ckey.flags = I915_SET_COLORKEY_NONE; |
465c120c MR |
13803 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) |
13804 | primary->plane = !pipe; | |
13805 | ||
6c0fd451 DL |
13806 | if (INTEL_INFO(dev)->gen >= 9) { |
13807 | intel_primary_formats = skl_primary_formats; | |
13808 | num_formats = ARRAY_SIZE(skl_primary_formats); | |
13809 | } else if (INTEL_INFO(dev)->gen >= 4) { | |
568db4f2 DL |
13810 | intel_primary_formats = i965_primary_formats; |
13811 | num_formats = ARRAY_SIZE(i965_primary_formats); | |
6c0fd451 DL |
13812 | } else { |
13813 | intel_primary_formats = i8xx_primary_formats; | |
13814 | num_formats = ARRAY_SIZE(i8xx_primary_formats); | |
465c120c MR |
13815 | } |
13816 | ||
13817 | drm_universal_plane_init(dev, &primary->base, 0, | |
65a3fea0 | 13818 | &intel_plane_funcs, |
465c120c MR |
13819 | intel_primary_formats, num_formats, |
13820 | DRM_PLANE_TYPE_PRIMARY); | |
48404c1e | 13821 | |
3b7a5119 SJ |
13822 | if (INTEL_INFO(dev)->gen >= 4) |
13823 | intel_create_rotation_property(dev, primary); | |
48404c1e | 13824 | |
ea2c67bb MR |
13825 | drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs); |
13826 | ||
465c120c MR |
13827 | return &primary->base; |
13828 | } | |
13829 | ||
3b7a5119 SJ |
13830 | void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane) |
13831 | { | |
13832 | if (!dev->mode_config.rotation_property) { | |
13833 | unsigned long flags = BIT(DRM_ROTATE_0) | | |
13834 | BIT(DRM_ROTATE_180); | |
13835 | ||
13836 | if (INTEL_INFO(dev)->gen >= 9) | |
13837 | flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270); | |
13838 | ||
13839 | dev->mode_config.rotation_property = | |
13840 | drm_mode_create_rotation_property(dev, flags); | |
13841 | } | |
13842 | if (dev->mode_config.rotation_property) | |
13843 | drm_object_attach_property(&plane->base.base, | |
13844 | dev->mode_config.rotation_property, | |
13845 | plane->base.state->rotation); | |
13846 | } | |
13847 | ||
3d7d6510 | 13848 | static int |
852e787c GP |
13849 | intel_check_cursor_plane(struct drm_plane *plane, |
13850 | struct intel_plane_state *state) | |
3d7d6510 | 13851 | { |
2b875c22 | 13852 | struct drm_crtc *crtc = state->base.crtc; |
ea2c67bb | 13853 | struct drm_device *dev = plane->dev; |
2b875c22 | 13854 | struct drm_framebuffer *fb = state->base.fb; |
852e787c GP |
13855 | struct drm_rect *dest = &state->dst; |
13856 | struct drm_rect *src = &state->src; | |
13857 | const struct drm_rect *clip = &state->clip; | |
757f9a3e | 13858 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
ea2c67bb | 13859 | struct intel_crtc *intel_crtc; |
757f9a3e GP |
13860 | unsigned stride; |
13861 | int ret; | |
3d7d6510 | 13862 | |
ea2c67bb MR |
13863 | crtc = crtc ? crtc : plane->crtc; |
13864 | intel_crtc = to_intel_crtc(crtc); | |
13865 | ||
757f9a3e | 13866 | ret = drm_plane_helper_check_update(plane, crtc, fb, |
852e787c | 13867 | src, dest, clip, |
3d7d6510 MR |
13868 | DRM_PLANE_HELPER_NO_SCALING, |
13869 | DRM_PLANE_HELPER_NO_SCALING, | |
852e787c | 13870 | true, true, &state->visible); |
757f9a3e GP |
13871 | if (ret) |
13872 | return ret; | |
13873 | ||
13874 | ||
13875 | /* if we want to turn off the cursor ignore width and height */ | |
13876 | if (!obj) | |
32b7eeec | 13877 | goto finish; |
757f9a3e | 13878 | |
757f9a3e | 13879 | /* Check for which cursor types we support */ |
ea2c67bb MR |
13880 | if (!cursor_size_ok(dev, state->base.crtc_w, state->base.crtc_h)) { |
13881 | DRM_DEBUG("Cursor dimension %dx%d not supported\n", | |
13882 | state->base.crtc_w, state->base.crtc_h); | |
757f9a3e GP |
13883 | return -EINVAL; |
13884 | } | |
13885 | ||
ea2c67bb MR |
13886 | stride = roundup_pow_of_two(state->base.crtc_w) * 4; |
13887 | if (obj->base.size < stride * state->base.crtc_h) { | |
757f9a3e GP |
13888 | DRM_DEBUG_KMS("buffer is too small\n"); |
13889 | return -ENOMEM; | |
13890 | } | |
13891 | ||
3a656b54 | 13892 | if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) { |
757f9a3e GP |
13893 | DRM_DEBUG_KMS("cursor cannot be tiled\n"); |
13894 | ret = -EINVAL; | |
13895 | } | |
757f9a3e | 13896 | |
32b7eeec MR |
13897 | finish: |
13898 | if (intel_crtc->active) { | |
3749f463 | 13899 | if (plane->state->crtc_w != state->base.crtc_w) |
32b7eeec MR |
13900 | intel_crtc->atomic.update_wm = true; |
13901 | ||
13902 | intel_crtc->atomic.fb_bits |= | |
13903 | INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe); | |
13904 | } | |
13905 | ||
757f9a3e | 13906 | return ret; |
852e787c | 13907 | } |
3d7d6510 | 13908 | |
a8ad0d8e ML |
13909 | static void |
13910 | intel_disable_cursor_plane(struct drm_plane *plane, | |
13911 | struct drm_crtc *crtc, | |
13912 | bool force) | |
13913 | { | |
13914 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
13915 | ||
13916 | if (!force) { | |
13917 | plane->fb = NULL; | |
13918 | intel_crtc->cursor_bo = NULL; | |
13919 | intel_crtc->cursor_addr = 0; | |
13920 | } | |
13921 | ||
13922 | intel_crtc_update_cursor(crtc, false); | |
13923 | } | |
13924 | ||
f4a2cf29 | 13925 | static void |
852e787c GP |
13926 | intel_commit_cursor_plane(struct drm_plane *plane, |
13927 | struct intel_plane_state *state) | |
13928 | { | |
2b875c22 | 13929 | struct drm_crtc *crtc = state->base.crtc; |
ea2c67bb MR |
13930 | struct drm_device *dev = plane->dev; |
13931 | struct intel_crtc *intel_crtc; | |
2b875c22 | 13932 | struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb); |
a912f12f | 13933 | uint32_t addr; |
852e787c | 13934 | |
ea2c67bb MR |
13935 | crtc = crtc ? crtc : plane->crtc; |
13936 | intel_crtc = to_intel_crtc(crtc); | |
13937 | ||
2b875c22 | 13938 | plane->fb = state->base.fb; |
ea2c67bb MR |
13939 | crtc->cursor_x = state->base.crtc_x; |
13940 | crtc->cursor_y = state->base.crtc_y; | |
13941 | ||
a912f12f GP |
13942 | if (intel_crtc->cursor_bo == obj) |
13943 | goto update; | |
4ed91096 | 13944 | |
f4a2cf29 | 13945 | if (!obj) |
a912f12f | 13946 | addr = 0; |
f4a2cf29 | 13947 | else if (!INTEL_INFO(dev)->cursor_needs_physical) |
a912f12f | 13948 | addr = i915_gem_obj_ggtt_offset(obj); |
f4a2cf29 | 13949 | else |
a912f12f | 13950 | addr = obj->phys_handle->busaddr; |
852e787c | 13951 | |
a912f12f GP |
13952 | intel_crtc->cursor_addr = addr; |
13953 | intel_crtc->cursor_bo = obj; | |
13954 | update: | |
852e787c | 13955 | |
32b7eeec | 13956 | if (intel_crtc->active) |
a912f12f | 13957 | intel_crtc_update_cursor(crtc, state->visible); |
852e787c GP |
13958 | } |
13959 | ||
3d7d6510 MR |
13960 | static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev, |
13961 | int pipe) | |
13962 | { | |
13963 | struct intel_plane *cursor; | |
8e7d688b | 13964 | struct intel_plane_state *state; |
3d7d6510 MR |
13965 | |
13966 | cursor = kzalloc(sizeof(*cursor), GFP_KERNEL); | |
13967 | if (cursor == NULL) | |
13968 | return NULL; | |
13969 | ||
8e7d688b MR |
13970 | state = intel_create_plane_state(&cursor->base); |
13971 | if (!state) { | |
ea2c67bb MR |
13972 | kfree(cursor); |
13973 | return NULL; | |
13974 | } | |
8e7d688b | 13975 | cursor->base.state = &state->base; |
ea2c67bb | 13976 | |
3d7d6510 MR |
13977 | cursor->can_scale = false; |
13978 | cursor->max_downscale = 1; | |
13979 | cursor->pipe = pipe; | |
13980 | cursor->plane = pipe; | |
c59cb179 MR |
13981 | cursor->check_plane = intel_check_cursor_plane; |
13982 | cursor->commit_plane = intel_commit_cursor_plane; | |
a8ad0d8e | 13983 | cursor->disable_plane = intel_disable_cursor_plane; |
3d7d6510 MR |
13984 | |
13985 | drm_universal_plane_init(dev, &cursor->base, 0, | |
65a3fea0 | 13986 | &intel_plane_funcs, |
3d7d6510 MR |
13987 | intel_cursor_formats, |
13988 | ARRAY_SIZE(intel_cursor_formats), | |
13989 | DRM_PLANE_TYPE_CURSOR); | |
4398ad45 VS |
13990 | |
13991 | if (INTEL_INFO(dev)->gen >= 4) { | |
13992 | if (!dev->mode_config.rotation_property) | |
13993 | dev->mode_config.rotation_property = | |
13994 | drm_mode_create_rotation_property(dev, | |
13995 | BIT(DRM_ROTATE_0) | | |
13996 | BIT(DRM_ROTATE_180)); | |
13997 | if (dev->mode_config.rotation_property) | |
13998 | drm_object_attach_property(&cursor->base.base, | |
13999 | dev->mode_config.rotation_property, | |
8e7d688b | 14000 | state->base.rotation); |
4398ad45 VS |
14001 | } |
14002 | ||
af99ceda CK |
14003 | if (INTEL_INFO(dev)->gen >=9) |
14004 | state->scaler_id = -1; | |
14005 | ||
ea2c67bb MR |
14006 | drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs); |
14007 | ||
3d7d6510 MR |
14008 | return &cursor->base; |
14009 | } | |
14010 | ||
549e2bfb CK |
14011 | static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc, |
14012 | struct intel_crtc_state *crtc_state) | |
14013 | { | |
14014 | int i; | |
14015 | struct intel_scaler *intel_scaler; | |
14016 | struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state; | |
14017 | ||
14018 | for (i = 0; i < intel_crtc->num_scalers; i++) { | |
14019 | intel_scaler = &scaler_state->scalers[i]; | |
14020 | intel_scaler->in_use = 0; | |
14021 | intel_scaler->id = i; | |
14022 | ||
14023 | intel_scaler->mode = PS_SCALER_MODE_DYN; | |
14024 | } | |
14025 | ||
14026 | scaler_state->scaler_id = -1; | |
14027 | } | |
14028 | ||
b358d0a6 | 14029 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
79e53945 | 14030 | { |
fbee40df | 14031 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 14032 | struct intel_crtc *intel_crtc; |
f5de6e07 | 14033 | struct intel_crtc_state *crtc_state = NULL; |
3d7d6510 MR |
14034 | struct drm_plane *primary = NULL; |
14035 | struct drm_plane *cursor = NULL; | |
465c120c | 14036 | int i, ret; |
79e53945 | 14037 | |
955382f3 | 14038 | intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL); |
79e53945 JB |
14039 | if (intel_crtc == NULL) |
14040 | return; | |
14041 | ||
f5de6e07 ACO |
14042 | crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL); |
14043 | if (!crtc_state) | |
14044 | goto fail; | |
550acefd ACO |
14045 | intel_crtc->config = crtc_state; |
14046 | intel_crtc->base.state = &crtc_state->base; | |
07878248 | 14047 | crtc_state->base.crtc = &intel_crtc->base; |
f5de6e07 | 14048 | |
549e2bfb CK |
14049 | /* initialize shared scalers */ |
14050 | if (INTEL_INFO(dev)->gen >= 9) { | |
14051 | if (pipe == PIPE_C) | |
14052 | intel_crtc->num_scalers = 1; | |
14053 | else | |
14054 | intel_crtc->num_scalers = SKL_NUM_SCALERS; | |
14055 | ||
14056 | skl_init_scalers(dev, intel_crtc, crtc_state); | |
14057 | } | |
14058 | ||
465c120c | 14059 | primary = intel_primary_plane_create(dev, pipe); |
3d7d6510 MR |
14060 | if (!primary) |
14061 | goto fail; | |
14062 | ||
14063 | cursor = intel_cursor_plane_create(dev, pipe); | |
14064 | if (!cursor) | |
14065 | goto fail; | |
14066 | ||
465c120c | 14067 | ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary, |
3d7d6510 MR |
14068 | cursor, &intel_crtc_funcs); |
14069 | if (ret) | |
14070 | goto fail; | |
79e53945 JB |
14071 | |
14072 | drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256); | |
79e53945 JB |
14073 | for (i = 0; i < 256; i++) { |
14074 | intel_crtc->lut_r[i] = i; | |
14075 | intel_crtc->lut_g[i] = i; | |
14076 | intel_crtc->lut_b[i] = i; | |
14077 | } | |
14078 | ||
1f1c2e24 VS |
14079 | /* |
14080 | * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port | |
8c0f92e1 | 14081 | * is hooked to pipe B. Hence we want plane A feeding pipe B. |
1f1c2e24 | 14082 | */ |
80824003 JB |
14083 | intel_crtc->pipe = pipe; |
14084 | intel_crtc->plane = pipe; | |
3a77c4c4 | 14085 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) { |
28c97730 | 14086 | DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); |
e2e767ab | 14087 | intel_crtc->plane = !pipe; |
80824003 JB |
14088 | } |
14089 | ||
4b0e333e CW |
14090 | intel_crtc->cursor_base = ~0; |
14091 | intel_crtc->cursor_cntl = ~0; | |
dc41c154 | 14092 | intel_crtc->cursor_size = ~0; |
8d7849db | 14093 | |
22fd0fab JB |
14094 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
14095 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); | |
14096 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; | |
14097 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; | |
14098 | ||
79e53945 | 14099 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
87b6b101 DV |
14100 | |
14101 | WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe); | |
3d7d6510 MR |
14102 | return; |
14103 | ||
14104 | fail: | |
14105 | if (primary) | |
14106 | drm_plane_cleanup(primary); | |
14107 | if (cursor) | |
14108 | drm_plane_cleanup(cursor); | |
f5de6e07 | 14109 | kfree(crtc_state); |
3d7d6510 | 14110 | kfree(intel_crtc); |
79e53945 JB |
14111 | } |
14112 | ||
752aa88a JB |
14113 | enum pipe intel_get_pipe_from_connector(struct intel_connector *connector) |
14114 | { | |
14115 | struct drm_encoder *encoder = connector->base.encoder; | |
6e9f798d | 14116 | struct drm_device *dev = connector->base.dev; |
752aa88a | 14117 | |
51fd371b | 14118 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); |
752aa88a | 14119 | |
d3babd3f | 14120 | if (!encoder || WARN_ON(!encoder->crtc)) |
752aa88a JB |
14121 | return INVALID_PIPE; |
14122 | ||
14123 | return to_intel_crtc(encoder->crtc)->pipe; | |
14124 | } | |
14125 | ||
08d7b3d1 | 14126 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
05394f39 | 14127 | struct drm_file *file) |
08d7b3d1 | 14128 | { |
08d7b3d1 | 14129 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; |
7707e653 | 14130 | struct drm_crtc *drmmode_crtc; |
c05422d5 | 14131 | struct intel_crtc *crtc; |
08d7b3d1 | 14132 | |
7707e653 | 14133 | drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id); |
08d7b3d1 | 14134 | |
7707e653 | 14135 | if (!drmmode_crtc) { |
08d7b3d1 | 14136 | DRM_ERROR("no such CRTC id\n"); |
3f2c2057 | 14137 | return -ENOENT; |
08d7b3d1 CW |
14138 | } |
14139 | ||
7707e653 | 14140 | crtc = to_intel_crtc(drmmode_crtc); |
c05422d5 | 14141 | pipe_from_crtc_id->pipe = crtc->pipe; |
08d7b3d1 | 14142 | |
c05422d5 | 14143 | return 0; |
08d7b3d1 CW |
14144 | } |
14145 | ||
66a9278e | 14146 | static int intel_encoder_clones(struct intel_encoder *encoder) |
79e53945 | 14147 | { |
66a9278e DV |
14148 | struct drm_device *dev = encoder->base.dev; |
14149 | struct intel_encoder *source_encoder; | |
79e53945 | 14150 | int index_mask = 0; |
79e53945 JB |
14151 | int entry = 0; |
14152 | ||
b2784e15 | 14153 | for_each_intel_encoder(dev, source_encoder) { |
bc079e8b | 14154 | if (encoders_cloneable(encoder, source_encoder)) |
66a9278e DV |
14155 | index_mask |= (1 << entry); |
14156 | ||
79e53945 JB |
14157 | entry++; |
14158 | } | |
4ef69c7a | 14159 | |
79e53945 JB |
14160 | return index_mask; |
14161 | } | |
14162 | ||
4d302442 CW |
14163 | static bool has_edp_a(struct drm_device *dev) |
14164 | { | |
14165 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14166 | ||
14167 | if (!IS_MOBILE(dev)) | |
14168 | return false; | |
14169 | ||
14170 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) | |
14171 | return false; | |
14172 | ||
e3589908 | 14173 | if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE)) |
4d302442 CW |
14174 | return false; |
14175 | ||
14176 | return true; | |
14177 | } | |
14178 | ||
84b4e042 JB |
14179 | static bool intel_crt_present(struct drm_device *dev) |
14180 | { | |
14181 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14182 | ||
884497ed DL |
14183 | if (INTEL_INFO(dev)->gen >= 9) |
14184 | return false; | |
14185 | ||
cf404ce4 | 14186 | if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev)) |
84b4e042 JB |
14187 | return false; |
14188 | ||
14189 | if (IS_CHERRYVIEW(dev)) | |
14190 | return false; | |
14191 | ||
14192 | if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support) | |
14193 | return false; | |
14194 | ||
14195 | return true; | |
14196 | } | |
14197 | ||
79e53945 JB |
14198 | static void intel_setup_outputs(struct drm_device *dev) |
14199 | { | |
725e30ad | 14200 | struct drm_i915_private *dev_priv = dev->dev_private; |
4ef69c7a | 14201 | struct intel_encoder *encoder; |
cb0953d7 | 14202 | bool dpd_is_edp = false; |
79e53945 | 14203 | |
c9093354 | 14204 | intel_lvds_init(dev); |
79e53945 | 14205 | |
84b4e042 | 14206 | if (intel_crt_present(dev)) |
79935fca | 14207 | intel_crt_init(dev); |
cb0953d7 | 14208 | |
c776eb2e VK |
14209 | if (IS_BROXTON(dev)) { |
14210 | /* | |
14211 | * FIXME: Broxton doesn't support port detection via the | |
14212 | * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to | |
14213 | * detect the ports. | |
14214 | */ | |
14215 | intel_ddi_init(dev, PORT_A); | |
14216 | intel_ddi_init(dev, PORT_B); | |
14217 | intel_ddi_init(dev, PORT_C); | |
14218 | } else if (HAS_DDI(dev)) { | |
0e72a5b5 ED |
14219 | int found; |
14220 | ||
de31facd JB |
14221 | /* |
14222 | * Haswell uses DDI functions to detect digital outputs. | |
14223 | * On SKL pre-D0 the strap isn't connected, so we assume | |
14224 | * it's there. | |
14225 | */ | |
0e72a5b5 | 14226 | found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED; |
de31facd JB |
14227 | /* WaIgnoreDDIAStrap: skl */ |
14228 | if (found || | |
14229 | (IS_SKYLAKE(dev) && INTEL_REVID(dev) < SKL_REVID_D0)) | |
0e72a5b5 ED |
14230 | intel_ddi_init(dev, PORT_A); |
14231 | ||
14232 | /* DDI B, C and D detection is indicated by the SFUSE_STRAP | |
14233 | * register */ | |
14234 | found = I915_READ(SFUSE_STRAP); | |
14235 | ||
14236 | if (found & SFUSE_STRAP_DDIB_DETECTED) | |
14237 | intel_ddi_init(dev, PORT_B); | |
14238 | if (found & SFUSE_STRAP_DDIC_DETECTED) | |
14239 | intel_ddi_init(dev, PORT_C); | |
14240 | if (found & SFUSE_STRAP_DDID_DETECTED) | |
14241 | intel_ddi_init(dev, PORT_D); | |
14242 | } else if (HAS_PCH_SPLIT(dev)) { | |
cb0953d7 | 14243 | int found; |
5d8a7752 | 14244 | dpd_is_edp = intel_dp_is_edp(dev, PORT_D); |
270b3042 DV |
14245 | |
14246 | if (has_edp_a(dev)) | |
14247 | intel_dp_init(dev, DP_A, PORT_A); | |
cb0953d7 | 14248 | |
dc0fa718 | 14249 | if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) { |
461ed3ca | 14250 | /* PCH SDVOB multiplex with HDMIB */ |
eef4eacb | 14251 | found = intel_sdvo_init(dev, PCH_SDVOB, true); |
30ad48b7 | 14252 | if (!found) |
e2debe91 | 14253 | intel_hdmi_init(dev, PCH_HDMIB, PORT_B); |
5eb08b69 | 14254 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
ab9d7c30 | 14255 | intel_dp_init(dev, PCH_DP_B, PORT_B); |
30ad48b7 ZW |
14256 | } |
14257 | ||
dc0fa718 | 14258 | if (I915_READ(PCH_HDMIC) & SDVO_DETECTED) |
e2debe91 | 14259 | intel_hdmi_init(dev, PCH_HDMIC, PORT_C); |
30ad48b7 | 14260 | |
dc0fa718 | 14261 | if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED) |
e2debe91 | 14262 | intel_hdmi_init(dev, PCH_HDMID, PORT_D); |
30ad48b7 | 14263 | |
5eb08b69 | 14264 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
ab9d7c30 | 14265 | intel_dp_init(dev, PCH_DP_C, PORT_C); |
5eb08b69 | 14266 | |
270b3042 | 14267 | if (I915_READ(PCH_DP_D) & DP_DETECTED) |
ab9d7c30 | 14268 | intel_dp_init(dev, PCH_DP_D, PORT_D); |
4a87d65d | 14269 | } else if (IS_VALLEYVIEW(dev)) { |
e17ac6db VS |
14270 | /* |
14271 | * The DP_DETECTED bit is the latched state of the DDC | |
14272 | * SDA pin at boot. However since eDP doesn't require DDC | |
14273 | * (no way to plug in a DP->HDMI dongle) the DDC pins for | |
14274 | * eDP ports may have been muxed to an alternate function. | |
14275 | * Thus we can't rely on the DP_DETECTED bit alone to detect | |
14276 | * eDP ports. Consult the VBT as well as DP_DETECTED to | |
14277 | * detect eDP ports. | |
14278 | */ | |
d2182a66 VS |
14279 | if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED && |
14280 | !intel_dp_is_edp(dev, PORT_B)) | |
585a94b8 AB |
14281 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB, |
14282 | PORT_B); | |
e17ac6db VS |
14283 | if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED || |
14284 | intel_dp_is_edp(dev, PORT_B)) | |
14285 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B); | |
585a94b8 | 14286 | |
d2182a66 VS |
14287 | if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED && |
14288 | !intel_dp_is_edp(dev, PORT_C)) | |
6f6005a5 JB |
14289 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC, |
14290 | PORT_C); | |
e17ac6db VS |
14291 | if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED || |
14292 | intel_dp_is_edp(dev, PORT_C)) | |
14293 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C); | |
19c03924 | 14294 | |
9418c1f1 | 14295 | if (IS_CHERRYVIEW(dev)) { |
e17ac6db | 14296 | if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED) |
9418c1f1 VS |
14297 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID, |
14298 | PORT_D); | |
e17ac6db VS |
14299 | /* eDP not supported on port D, so don't check VBT */ |
14300 | if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED) | |
14301 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D); | |
9418c1f1 VS |
14302 | } |
14303 | ||
3cfca973 | 14304 | intel_dsi_init(dev); |
103a196f | 14305 | } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) { |
27185ae1 | 14306 | bool found = false; |
7d57382e | 14307 | |
e2debe91 | 14308 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 14309 | DRM_DEBUG_KMS("probing SDVOB\n"); |
e2debe91 | 14310 | found = intel_sdvo_init(dev, GEN3_SDVOB, true); |
b01f2c3a JB |
14311 | if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) { |
14312 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); | |
e2debe91 | 14313 | intel_hdmi_init(dev, GEN4_HDMIB, PORT_B); |
b01f2c3a | 14314 | } |
27185ae1 | 14315 | |
e7281eab | 14316 | if (!found && SUPPORTS_INTEGRATED_DP(dev)) |
ab9d7c30 | 14317 | intel_dp_init(dev, DP_B, PORT_B); |
725e30ad | 14318 | } |
13520b05 KH |
14319 | |
14320 | /* Before G4X SDVOC doesn't have its own detect register */ | |
13520b05 | 14321 | |
e2debe91 | 14322 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 14323 | DRM_DEBUG_KMS("probing SDVOC\n"); |
e2debe91 | 14324 | found = intel_sdvo_init(dev, GEN3_SDVOC, false); |
b01f2c3a | 14325 | } |
27185ae1 | 14326 | |
e2debe91 | 14327 | if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) { |
27185ae1 | 14328 | |
b01f2c3a JB |
14329 | if (SUPPORTS_INTEGRATED_HDMI(dev)) { |
14330 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); | |
e2debe91 | 14331 | intel_hdmi_init(dev, GEN4_HDMIC, PORT_C); |
b01f2c3a | 14332 | } |
e7281eab | 14333 | if (SUPPORTS_INTEGRATED_DP(dev)) |
ab9d7c30 | 14334 | intel_dp_init(dev, DP_C, PORT_C); |
725e30ad | 14335 | } |
27185ae1 | 14336 | |
b01f2c3a | 14337 | if (SUPPORTS_INTEGRATED_DP(dev) && |
e7281eab | 14338 | (I915_READ(DP_D) & DP_DETECTED)) |
ab9d7c30 | 14339 | intel_dp_init(dev, DP_D, PORT_D); |
bad720ff | 14340 | } else if (IS_GEN2(dev)) |
79e53945 JB |
14341 | intel_dvo_init(dev); |
14342 | ||
103a196f | 14343 | if (SUPPORTS_TV(dev)) |
79e53945 JB |
14344 | intel_tv_init(dev); |
14345 | ||
0bc12bcb | 14346 | intel_psr_init(dev); |
7c8f8a70 | 14347 | |
b2784e15 | 14348 | for_each_intel_encoder(dev, encoder) { |
4ef69c7a CW |
14349 | encoder->base.possible_crtcs = encoder->crtc_mask; |
14350 | encoder->base.possible_clones = | |
66a9278e | 14351 | intel_encoder_clones(encoder); |
79e53945 | 14352 | } |
47356eb6 | 14353 | |
dde86e2d | 14354 | intel_init_pch_refclk(dev); |
270b3042 DV |
14355 | |
14356 | drm_helper_move_panel_connectors_to_head(dev); | |
79e53945 JB |
14357 | } |
14358 | ||
14359 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) | |
14360 | { | |
60a5ca01 | 14361 | struct drm_device *dev = fb->dev; |
79e53945 | 14362 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
79e53945 | 14363 | |
ef2d633e | 14364 | drm_framebuffer_cleanup(fb); |
60a5ca01 | 14365 | mutex_lock(&dev->struct_mutex); |
ef2d633e | 14366 | WARN_ON(!intel_fb->obj->framebuffer_references--); |
60a5ca01 VS |
14367 | drm_gem_object_unreference(&intel_fb->obj->base); |
14368 | mutex_unlock(&dev->struct_mutex); | |
79e53945 JB |
14369 | kfree(intel_fb); |
14370 | } | |
14371 | ||
14372 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
05394f39 | 14373 | struct drm_file *file, |
79e53945 JB |
14374 | unsigned int *handle) |
14375 | { | |
14376 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 14377 | struct drm_i915_gem_object *obj = intel_fb->obj; |
79e53945 | 14378 | |
05394f39 | 14379 | return drm_gem_handle_create(file, &obj->base, handle); |
79e53945 JB |
14380 | } |
14381 | ||
14382 | static const struct drm_framebuffer_funcs intel_fb_funcs = { | |
14383 | .destroy = intel_user_framebuffer_destroy, | |
14384 | .create_handle = intel_user_framebuffer_create_handle, | |
14385 | }; | |
14386 | ||
b321803d DL |
14387 | static |
14388 | u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier, | |
14389 | uint32_t pixel_format) | |
14390 | { | |
14391 | u32 gen = INTEL_INFO(dev)->gen; | |
14392 | ||
14393 | if (gen >= 9) { | |
14394 | /* "The stride in bytes must not exceed the of the size of 8K | |
14395 | * pixels and 32K bytes." | |
14396 | */ | |
14397 | return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768); | |
14398 | } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) { | |
14399 | return 32*1024; | |
14400 | } else if (gen >= 4) { | |
14401 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
14402 | return 16*1024; | |
14403 | else | |
14404 | return 32*1024; | |
14405 | } else if (gen >= 3) { | |
14406 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
14407 | return 8*1024; | |
14408 | else | |
14409 | return 16*1024; | |
14410 | } else { | |
14411 | /* XXX DSPC is limited to 4k tiled */ | |
14412 | return 8*1024; | |
14413 | } | |
14414 | } | |
14415 | ||
b5ea642a DV |
14416 | static int intel_framebuffer_init(struct drm_device *dev, |
14417 | struct intel_framebuffer *intel_fb, | |
14418 | struct drm_mode_fb_cmd2 *mode_cmd, | |
14419 | struct drm_i915_gem_object *obj) | |
79e53945 | 14420 | { |
6761dd31 | 14421 | unsigned int aligned_height; |
79e53945 | 14422 | int ret; |
b321803d | 14423 | u32 pitch_limit, stride_alignment; |
79e53945 | 14424 | |
dd4916c5 DV |
14425 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
14426 | ||
2a80eada DV |
14427 | if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) { |
14428 | /* Enforce that fb modifier and tiling mode match, but only for | |
14429 | * X-tiled. This is needed for FBC. */ | |
14430 | if (!!(obj->tiling_mode == I915_TILING_X) != | |
14431 | !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) { | |
14432 | DRM_DEBUG("tiling_mode doesn't match fb modifier\n"); | |
14433 | return -EINVAL; | |
14434 | } | |
14435 | } else { | |
14436 | if (obj->tiling_mode == I915_TILING_X) | |
14437 | mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED; | |
14438 | else if (obj->tiling_mode == I915_TILING_Y) { | |
14439 | DRM_DEBUG("No Y tiling for legacy addfb\n"); | |
14440 | return -EINVAL; | |
14441 | } | |
14442 | } | |
14443 | ||
9a8f0a12 TU |
14444 | /* Passed in modifier sanity checking. */ |
14445 | switch (mode_cmd->modifier[0]) { | |
14446 | case I915_FORMAT_MOD_Y_TILED: | |
14447 | case I915_FORMAT_MOD_Yf_TILED: | |
14448 | if (INTEL_INFO(dev)->gen < 9) { | |
14449 | DRM_DEBUG("Unsupported tiling 0x%llx!\n", | |
14450 | mode_cmd->modifier[0]); | |
14451 | return -EINVAL; | |
14452 | } | |
14453 | case DRM_FORMAT_MOD_NONE: | |
14454 | case I915_FORMAT_MOD_X_TILED: | |
14455 | break; | |
14456 | default: | |
c0f40428 JB |
14457 | DRM_DEBUG("Unsupported fb modifier 0x%llx!\n", |
14458 | mode_cmd->modifier[0]); | |
57cd6508 | 14459 | return -EINVAL; |
c16ed4be | 14460 | } |
57cd6508 | 14461 | |
b321803d DL |
14462 | stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0], |
14463 | mode_cmd->pixel_format); | |
14464 | if (mode_cmd->pitches[0] & (stride_alignment - 1)) { | |
14465 | DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n", | |
14466 | mode_cmd->pitches[0], stride_alignment); | |
57cd6508 | 14467 | return -EINVAL; |
c16ed4be | 14468 | } |
57cd6508 | 14469 | |
b321803d DL |
14470 | pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0], |
14471 | mode_cmd->pixel_format); | |
a35cdaa0 | 14472 | if (mode_cmd->pitches[0] > pitch_limit) { |
b321803d DL |
14473 | DRM_DEBUG("%s pitch (%u) must be at less than %d\n", |
14474 | mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ? | |
2a80eada | 14475 | "tiled" : "linear", |
a35cdaa0 | 14476 | mode_cmd->pitches[0], pitch_limit); |
5d7bd705 | 14477 | return -EINVAL; |
c16ed4be | 14478 | } |
5d7bd705 | 14479 | |
2a80eada | 14480 | if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED && |
c16ed4be CW |
14481 | mode_cmd->pitches[0] != obj->stride) { |
14482 | DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n", | |
14483 | mode_cmd->pitches[0], obj->stride); | |
5d7bd705 | 14484 | return -EINVAL; |
c16ed4be | 14485 | } |
5d7bd705 | 14486 | |
57779d06 | 14487 | /* Reject formats not supported by any plane early. */ |
308e5bcb | 14488 | switch (mode_cmd->pixel_format) { |
57779d06 | 14489 | case DRM_FORMAT_C8: |
04b3924d VS |
14490 | case DRM_FORMAT_RGB565: |
14491 | case DRM_FORMAT_XRGB8888: | |
14492 | case DRM_FORMAT_ARGB8888: | |
57779d06 VS |
14493 | break; |
14494 | case DRM_FORMAT_XRGB1555: | |
c16ed4be | 14495 | if (INTEL_INFO(dev)->gen > 3) { |
4ee62c76 VS |
14496 | DRM_DEBUG("unsupported pixel format: %s\n", |
14497 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 14498 | return -EINVAL; |
c16ed4be | 14499 | } |
57779d06 | 14500 | break; |
57779d06 | 14501 | case DRM_FORMAT_ABGR8888: |
6c0fd451 DL |
14502 | if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) { |
14503 | DRM_DEBUG("unsupported pixel format: %s\n", | |
14504 | drm_get_format_name(mode_cmd->pixel_format)); | |
14505 | return -EINVAL; | |
14506 | } | |
14507 | break; | |
14508 | case DRM_FORMAT_XBGR8888: | |
04b3924d | 14509 | case DRM_FORMAT_XRGB2101010: |
57779d06 | 14510 | case DRM_FORMAT_XBGR2101010: |
c16ed4be | 14511 | if (INTEL_INFO(dev)->gen < 4) { |
4ee62c76 VS |
14512 | DRM_DEBUG("unsupported pixel format: %s\n", |
14513 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 14514 | return -EINVAL; |
c16ed4be | 14515 | } |
b5626747 | 14516 | break; |
7531208b DL |
14517 | case DRM_FORMAT_ABGR2101010: |
14518 | if (!IS_VALLEYVIEW(dev)) { | |
14519 | DRM_DEBUG("unsupported pixel format: %s\n", | |
14520 | drm_get_format_name(mode_cmd->pixel_format)); | |
14521 | return -EINVAL; | |
14522 | } | |
14523 | break; | |
04b3924d VS |
14524 | case DRM_FORMAT_YUYV: |
14525 | case DRM_FORMAT_UYVY: | |
14526 | case DRM_FORMAT_YVYU: | |
14527 | case DRM_FORMAT_VYUY: | |
c16ed4be | 14528 | if (INTEL_INFO(dev)->gen < 5) { |
4ee62c76 VS |
14529 | DRM_DEBUG("unsupported pixel format: %s\n", |
14530 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 14531 | return -EINVAL; |
c16ed4be | 14532 | } |
57cd6508 CW |
14533 | break; |
14534 | default: | |
4ee62c76 VS |
14535 | DRM_DEBUG("unsupported pixel format: %s\n", |
14536 | drm_get_format_name(mode_cmd->pixel_format)); | |
57cd6508 CW |
14537 | return -EINVAL; |
14538 | } | |
14539 | ||
90f9a336 VS |
14540 | /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ |
14541 | if (mode_cmd->offsets[0] != 0) | |
14542 | return -EINVAL; | |
14543 | ||
ec2c981e | 14544 | aligned_height = intel_fb_align_height(dev, mode_cmd->height, |
091df6cb DV |
14545 | mode_cmd->pixel_format, |
14546 | mode_cmd->modifier[0]); | |
53155c0a DV |
14547 | /* FIXME drm helper for size checks (especially planar formats)? */ |
14548 | if (obj->base.size < aligned_height * mode_cmd->pitches[0]) | |
14549 | return -EINVAL; | |
14550 | ||
c7d73f6a DV |
14551 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); |
14552 | intel_fb->obj = obj; | |
80075d49 | 14553 | intel_fb->obj->framebuffer_references++; |
c7d73f6a | 14554 | |
79e53945 JB |
14555 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); |
14556 | if (ret) { | |
14557 | DRM_ERROR("framebuffer init failed %d\n", ret); | |
14558 | return ret; | |
14559 | } | |
14560 | ||
79e53945 JB |
14561 | return 0; |
14562 | } | |
14563 | ||
79e53945 JB |
14564 | static struct drm_framebuffer * |
14565 | intel_user_framebuffer_create(struct drm_device *dev, | |
14566 | struct drm_file *filp, | |
308e5bcb | 14567 | struct drm_mode_fb_cmd2 *mode_cmd) |
79e53945 | 14568 | { |
05394f39 | 14569 | struct drm_i915_gem_object *obj; |
79e53945 | 14570 | |
308e5bcb JB |
14571 | obj = to_intel_bo(drm_gem_object_lookup(dev, filp, |
14572 | mode_cmd->handles[0])); | |
c8725226 | 14573 | if (&obj->base == NULL) |
cce13ff7 | 14574 | return ERR_PTR(-ENOENT); |
79e53945 | 14575 | |
d2dff872 | 14576 | return intel_framebuffer_create(dev, mode_cmd, obj); |
79e53945 JB |
14577 | } |
14578 | ||
4520f53a | 14579 | #ifndef CONFIG_DRM_I915_FBDEV |
0632fef6 | 14580 | static inline void intel_fbdev_output_poll_changed(struct drm_device *dev) |
4520f53a DV |
14581 | { |
14582 | } | |
14583 | #endif | |
14584 | ||
79e53945 | 14585 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
79e53945 | 14586 | .fb_create = intel_user_framebuffer_create, |
0632fef6 | 14587 | .output_poll_changed = intel_fbdev_output_poll_changed, |
5ee67f1c MR |
14588 | .atomic_check = intel_atomic_check, |
14589 | .atomic_commit = intel_atomic_commit, | |
de419ab6 ML |
14590 | .atomic_state_alloc = intel_atomic_state_alloc, |
14591 | .atomic_state_clear = intel_atomic_state_clear, | |
79e53945 JB |
14592 | }; |
14593 | ||
e70236a8 JB |
14594 | /* Set up chip specific display functions */ |
14595 | static void intel_init_display(struct drm_device *dev) | |
14596 | { | |
14597 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14598 | ||
ee9300bb DV |
14599 | if (HAS_PCH_SPLIT(dev) || IS_G4X(dev)) |
14600 | dev_priv->display.find_dpll = g4x_find_best_dpll; | |
ef9348c8 CML |
14601 | else if (IS_CHERRYVIEW(dev)) |
14602 | dev_priv->display.find_dpll = chv_find_best_dpll; | |
ee9300bb DV |
14603 | else if (IS_VALLEYVIEW(dev)) |
14604 | dev_priv->display.find_dpll = vlv_find_best_dpll; | |
14605 | else if (IS_PINEVIEW(dev)) | |
14606 | dev_priv->display.find_dpll = pnv_find_best_dpll; | |
14607 | else | |
14608 | dev_priv->display.find_dpll = i9xx_find_best_dpll; | |
14609 | ||
bc8d7dff DL |
14610 | if (INTEL_INFO(dev)->gen >= 9) { |
14611 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; | |
5724dbd1 DL |
14612 | dev_priv->display.get_initial_plane_config = |
14613 | skylake_get_initial_plane_config; | |
bc8d7dff DL |
14614 | dev_priv->display.crtc_compute_clock = |
14615 | haswell_crtc_compute_clock; | |
14616 | dev_priv->display.crtc_enable = haswell_crtc_enable; | |
14617 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
bc8d7dff DL |
14618 | dev_priv->display.update_primary_plane = |
14619 | skylake_update_primary_plane; | |
14620 | } else if (HAS_DDI(dev)) { | |
0e8ffe1b | 14621 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
5724dbd1 DL |
14622 | dev_priv->display.get_initial_plane_config = |
14623 | ironlake_get_initial_plane_config; | |
797d0259 ACO |
14624 | dev_priv->display.crtc_compute_clock = |
14625 | haswell_crtc_compute_clock; | |
4f771f10 PZ |
14626 | dev_priv->display.crtc_enable = haswell_crtc_enable; |
14627 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
bc8d7dff DL |
14628 | dev_priv->display.update_primary_plane = |
14629 | ironlake_update_primary_plane; | |
09b4ddf9 | 14630 | } else if (HAS_PCH_SPLIT(dev)) { |
0e8ffe1b | 14631 | dev_priv->display.get_pipe_config = ironlake_get_pipe_config; |
5724dbd1 DL |
14632 | dev_priv->display.get_initial_plane_config = |
14633 | ironlake_get_initial_plane_config; | |
3fb37703 ACO |
14634 | dev_priv->display.crtc_compute_clock = |
14635 | ironlake_crtc_compute_clock; | |
76e5a89c DV |
14636 | dev_priv->display.crtc_enable = ironlake_crtc_enable; |
14637 | dev_priv->display.crtc_disable = ironlake_crtc_disable; | |
262ca2b0 MR |
14638 | dev_priv->display.update_primary_plane = |
14639 | ironlake_update_primary_plane; | |
89b667f8 JB |
14640 | } else if (IS_VALLEYVIEW(dev)) { |
14641 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
5724dbd1 DL |
14642 | dev_priv->display.get_initial_plane_config = |
14643 | i9xx_get_initial_plane_config; | |
d6dfee7a | 14644 | dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; |
89b667f8 JB |
14645 | dev_priv->display.crtc_enable = valleyview_crtc_enable; |
14646 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
262ca2b0 MR |
14647 | dev_priv->display.update_primary_plane = |
14648 | i9xx_update_primary_plane; | |
f564048e | 14649 | } else { |
0e8ffe1b | 14650 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
5724dbd1 DL |
14651 | dev_priv->display.get_initial_plane_config = |
14652 | i9xx_get_initial_plane_config; | |
d6dfee7a | 14653 | dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; |
76e5a89c DV |
14654 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
14655 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
262ca2b0 MR |
14656 | dev_priv->display.update_primary_plane = |
14657 | i9xx_update_primary_plane; | |
f564048e | 14658 | } |
e70236a8 | 14659 | |
e70236a8 | 14660 | /* Returns the core display clock speed */ |
1652d19e VS |
14661 | if (IS_SKYLAKE(dev)) |
14662 | dev_priv->display.get_display_clock_speed = | |
14663 | skylake_get_display_clock_speed; | |
14664 | else if (IS_BROADWELL(dev)) | |
14665 | dev_priv->display.get_display_clock_speed = | |
14666 | broadwell_get_display_clock_speed; | |
14667 | else if (IS_HASWELL(dev)) | |
14668 | dev_priv->display.get_display_clock_speed = | |
14669 | haswell_get_display_clock_speed; | |
14670 | else if (IS_VALLEYVIEW(dev)) | |
25eb05fc JB |
14671 | dev_priv->display.get_display_clock_speed = |
14672 | valleyview_get_display_clock_speed; | |
b37a6434 VS |
14673 | else if (IS_GEN5(dev)) |
14674 | dev_priv->display.get_display_clock_speed = | |
14675 | ilk_get_display_clock_speed; | |
a7c66cd8 | 14676 | else if (IS_I945G(dev) || IS_BROADWATER(dev) || |
34edce2f | 14677 | IS_GEN6(dev) || IS_IVYBRIDGE(dev)) |
e70236a8 JB |
14678 | dev_priv->display.get_display_clock_speed = |
14679 | i945_get_display_clock_speed; | |
34edce2f VS |
14680 | else if (IS_GM45(dev)) |
14681 | dev_priv->display.get_display_clock_speed = | |
14682 | gm45_get_display_clock_speed; | |
14683 | else if (IS_CRESTLINE(dev)) | |
14684 | dev_priv->display.get_display_clock_speed = | |
14685 | i965gm_get_display_clock_speed; | |
14686 | else if (IS_PINEVIEW(dev)) | |
14687 | dev_priv->display.get_display_clock_speed = | |
14688 | pnv_get_display_clock_speed; | |
14689 | else if (IS_G33(dev) || IS_G4X(dev)) | |
14690 | dev_priv->display.get_display_clock_speed = | |
14691 | g33_get_display_clock_speed; | |
e70236a8 JB |
14692 | else if (IS_I915G(dev)) |
14693 | dev_priv->display.get_display_clock_speed = | |
14694 | i915_get_display_clock_speed; | |
257a7ffc | 14695 | else if (IS_I945GM(dev) || IS_845G(dev)) |
e70236a8 JB |
14696 | dev_priv->display.get_display_clock_speed = |
14697 | i9xx_misc_get_display_clock_speed; | |
257a7ffc DV |
14698 | else if (IS_PINEVIEW(dev)) |
14699 | dev_priv->display.get_display_clock_speed = | |
14700 | pnv_get_display_clock_speed; | |
e70236a8 JB |
14701 | else if (IS_I915GM(dev)) |
14702 | dev_priv->display.get_display_clock_speed = | |
14703 | i915gm_get_display_clock_speed; | |
14704 | else if (IS_I865G(dev)) | |
14705 | dev_priv->display.get_display_clock_speed = | |
14706 | i865_get_display_clock_speed; | |
f0f8a9ce | 14707 | else if (IS_I85X(dev)) |
e70236a8 | 14708 | dev_priv->display.get_display_clock_speed = |
1b1d2716 | 14709 | i85x_get_display_clock_speed; |
623e01e5 VS |
14710 | else { /* 830 */ |
14711 | WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n"); | |
e70236a8 JB |
14712 | dev_priv->display.get_display_clock_speed = |
14713 | i830_get_display_clock_speed; | |
623e01e5 | 14714 | } |
e70236a8 | 14715 | |
7c10a2b5 | 14716 | if (IS_GEN5(dev)) { |
3bb11b53 | 14717 | dev_priv->display.fdi_link_train = ironlake_fdi_link_train; |
3bb11b53 SJ |
14718 | } else if (IS_GEN6(dev)) { |
14719 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; | |
3bb11b53 SJ |
14720 | } else if (IS_IVYBRIDGE(dev)) { |
14721 | /* FIXME: detect B0+ stepping and use auto training */ | |
14722 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; | |
059b2fe9 | 14723 | } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
3bb11b53 | 14724 | dev_priv->display.fdi_link_train = hsw_fdi_link_train; |
b432e5cf VS |
14725 | if (IS_BROADWELL(dev)) |
14726 | dev_priv->display.modeset_global_resources = | |
14727 | broadwell_modeset_global_resources; | |
30a970c6 JB |
14728 | } else if (IS_VALLEYVIEW(dev)) { |
14729 | dev_priv->display.modeset_global_resources = | |
14730 | valleyview_modeset_global_resources; | |
f8437dd1 VK |
14731 | } else if (IS_BROXTON(dev)) { |
14732 | dev_priv->display.modeset_global_resources = | |
14733 | broxton_modeset_global_resources; | |
e70236a8 | 14734 | } |
8c9f3aaf | 14735 | |
8c9f3aaf JB |
14736 | switch (INTEL_INFO(dev)->gen) { |
14737 | case 2: | |
14738 | dev_priv->display.queue_flip = intel_gen2_queue_flip; | |
14739 | break; | |
14740 | ||
14741 | case 3: | |
14742 | dev_priv->display.queue_flip = intel_gen3_queue_flip; | |
14743 | break; | |
14744 | ||
14745 | case 4: | |
14746 | case 5: | |
14747 | dev_priv->display.queue_flip = intel_gen4_queue_flip; | |
14748 | break; | |
14749 | ||
14750 | case 6: | |
14751 | dev_priv->display.queue_flip = intel_gen6_queue_flip; | |
14752 | break; | |
7c9017e5 | 14753 | case 7: |
4e0bbc31 | 14754 | case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */ |
7c9017e5 JB |
14755 | dev_priv->display.queue_flip = intel_gen7_queue_flip; |
14756 | break; | |
830c81db | 14757 | case 9: |
ba343e02 TU |
14758 | /* Drop through - unsupported since execlist only. */ |
14759 | default: | |
14760 | /* Default just returns -ENODEV to indicate unsupported */ | |
14761 | dev_priv->display.queue_flip = intel_default_queue_flip; | |
8c9f3aaf | 14762 | } |
7bd688cd JN |
14763 | |
14764 | intel_panel_init_backlight_funcs(dev); | |
e39b999a VS |
14765 | |
14766 | mutex_init(&dev_priv->pps_mutex); | |
e70236a8 JB |
14767 | } |
14768 | ||
b690e96c JB |
14769 | /* |
14770 | * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, | |
14771 | * resume, or other times. This quirk makes sure that's the case for | |
14772 | * affected systems. | |
14773 | */ | |
0206e353 | 14774 | static void quirk_pipea_force(struct drm_device *dev) |
b690e96c JB |
14775 | { |
14776 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14777 | ||
14778 | dev_priv->quirks |= QUIRK_PIPEA_FORCE; | |
bc0daf48 | 14779 | DRM_INFO("applying pipe a force quirk\n"); |
b690e96c JB |
14780 | } |
14781 | ||
b6b5d049 VS |
14782 | static void quirk_pipeb_force(struct drm_device *dev) |
14783 | { | |
14784 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14785 | ||
14786 | dev_priv->quirks |= QUIRK_PIPEB_FORCE; | |
14787 | DRM_INFO("applying pipe b force quirk\n"); | |
14788 | } | |
14789 | ||
435793df KP |
14790 | /* |
14791 | * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason | |
14792 | */ | |
14793 | static void quirk_ssc_force_disable(struct drm_device *dev) | |
14794 | { | |
14795 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14796 | dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; | |
bc0daf48 | 14797 | DRM_INFO("applying lvds SSC disable quirk\n"); |
435793df KP |
14798 | } |
14799 | ||
4dca20ef | 14800 | /* |
5a15ab5b CE |
14801 | * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight |
14802 | * brightness value | |
4dca20ef CE |
14803 | */ |
14804 | static void quirk_invert_brightness(struct drm_device *dev) | |
14805 | { | |
14806 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14807 | dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; | |
bc0daf48 | 14808 | DRM_INFO("applying inverted panel brightness quirk\n"); |
435793df KP |
14809 | } |
14810 | ||
9c72cc6f SD |
14811 | /* Some VBT's incorrectly indicate no backlight is present */ |
14812 | static void quirk_backlight_present(struct drm_device *dev) | |
14813 | { | |
14814 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14815 | dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT; | |
14816 | DRM_INFO("applying backlight present quirk\n"); | |
14817 | } | |
14818 | ||
b690e96c JB |
14819 | struct intel_quirk { |
14820 | int device; | |
14821 | int subsystem_vendor; | |
14822 | int subsystem_device; | |
14823 | void (*hook)(struct drm_device *dev); | |
14824 | }; | |
14825 | ||
5f85f176 EE |
14826 | /* For systems that don't have a meaningful PCI subdevice/subvendor ID */ |
14827 | struct intel_dmi_quirk { | |
14828 | void (*hook)(struct drm_device *dev); | |
14829 | const struct dmi_system_id (*dmi_id_list)[]; | |
14830 | }; | |
14831 | ||
14832 | static int intel_dmi_reverse_brightness(const struct dmi_system_id *id) | |
14833 | { | |
14834 | DRM_INFO("Backlight polarity reversed on %s\n", id->ident); | |
14835 | return 1; | |
14836 | } | |
14837 | ||
14838 | static const struct intel_dmi_quirk intel_dmi_quirks[] = { | |
14839 | { | |
14840 | .dmi_id_list = &(const struct dmi_system_id[]) { | |
14841 | { | |
14842 | .callback = intel_dmi_reverse_brightness, | |
14843 | .ident = "NCR Corporation", | |
14844 | .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"), | |
14845 | DMI_MATCH(DMI_PRODUCT_NAME, ""), | |
14846 | }, | |
14847 | }, | |
14848 | { } /* terminating entry */ | |
14849 | }, | |
14850 | .hook = quirk_invert_brightness, | |
14851 | }, | |
14852 | }; | |
14853 | ||
c43b5634 | 14854 | static struct intel_quirk intel_quirks[] = { |
b690e96c JB |
14855 | /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ |
14856 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, | |
14857 | ||
b690e96c JB |
14858 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ |
14859 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, | |
14860 | ||
5f080c0f VS |
14861 | /* 830 needs to leave pipe A & dpll A up */ |
14862 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, | |
14863 | ||
b6b5d049 VS |
14864 | /* 830 needs to leave pipe B & dpll B up */ |
14865 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force }, | |
14866 | ||
435793df KP |
14867 | /* Lenovo U160 cannot use SSC on LVDS */ |
14868 | { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, | |
070d329a MAS |
14869 | |
14870 | /* Sony Vaio Y cannot use SSC on LVDS */ | |
14871 | { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, | |
5a15ab5b | 14872 | |
be505f64 AH |
14873 | /* Acer Aspire 5734Z must invert backlight brightness */ |
14874 | { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness }, | |
14875 | ||
14876 | /* Acer/eMachines G725 */ | |
14877 | { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness }, | |
14878 | ||
14879 | /* Acer/eMachines e725 */ | |
14880 | { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness }, | |
14881 | ||
14882 | /* Acer/Packard Bell NCL20 */ | |
14883 | { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness }, | |
14884 | ||
14885 | /* Acer Aspire 4736Z */ | |
14886 | { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness }, | |
0f540c3a JN |
14887 | |
14888 | /* Acer Aspire 5336 */ | |
14889 | { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness }, | |
2e93a1aa SD |
14890 | |
14891 | /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */ | |
14892 | { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present }, | |
d4967d8c | 14893 | |
dfb3d47b SD |
14894 | /* Acer C720 Chromebook (Core i3 4005U) */ |
14895 | { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present }, | |
14896 | ||
b2a9601c | 14897 | /* Apple Macbook 2,1 (Core 2 T7400) */ |
14898 | { 0x27a2, 0x8086, 0x7270, quirk_backlight_present }, | |
14899 | ||
d4967d8c SD |
14900 | /* Toshiba CB35 Chromebook (Celeron 2955U) */ |
14901 | { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present }, | |
724cb06f SD |
14902 | |
14903 | /* HP Chromebook 14 (Celeron 2955U) */ | |
14904 | { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present }, | |
cf6f0af9 JN |
14905 | |
14906 | /* Dell Chromebook 11 */ | |
14907 | { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present }, | |
b690e96c JB |
14908 | }; |
14909 | ||
14910 | static void intel_init_quirks(struct drm_device *dev) | |
14911 | { | |
14912 | struct pci_dev *d = dev->pdev; | |
14913 | int i; | |
14914 | ||
14915 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { | |
14916 | struct intel_quirk *q = &intel_quirks[i]; | |
14917 | ||
14918 | if (d->device == q->device && | |
14919 | (d->subsystem_vendor == q->subsystem_vendor || | |
14920 | q->subsystem_vendor == PCI_ANY_ID) && | |
14921 | (d->subsystem_device == q->subsystem_device || | |
14922 | q->subsystem_device == PCI_ANY_ID)) | |
14923 | q->hook(dev); | |
14924 | } | |
5f85f176 EE |
14925 | for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) { |
14926 | if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0) | |
14927 | intel_dmi_quirks[i].hook(dev); | |
14928 | } | |
b690e96c JB |
14929 | } |
14930 | ||
9cce37f4 JB |
14931 | /* Disable the VGA plane that we never use */ |
14932 | static void i915_disable_vga(struct drm_device *dev) | |
14933 | { | |
14934 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14935 | u8 sr1; | |
766aa1c4 | 14936 | u32 vga_reg = i915_vgacntrl_reg(dev); |
9cce37f4 | 14937 | |
2b37c616 | 14938 | /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */ |
9cce37f4 | 14939 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); |
3fdcf431 | 14940 | outb(SR01, VGA_SR_INDEX); |
9cce37f4 JB |
14941 | sr1 = inb(VGA_SR_DATA); |
14942 | outb(sr1 | 1<<5, VGA_SR_DATA); | |
14943 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); | |
14944 | udelay(300); | |
14945 | ||
01f5a626 | 14946 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); |
9cce37f4 JB |
14947 | POSTING_READ(vga_reg); |
14948 | } | |
14949 | ||
f817586c DV |
14950 | void intel_modeset_init_hw(struct drm_device *dev) |
14951 | { | |
b6283055 | 14952 | intel_update_cdclk(dev); |
a8f78b58 | 14953 | intel_prepare_ddi(dev); |
f817586c | 14954 | intel_init_clock_gating(dev); |
8090c6b9 | 14955 | intel_enable_gt_powersave(dev); |
f817586c DV |
14956 | } |
14957 | ||
79e53945 JB |
14958 | void intel_modeset_init(struct drm_device *dev) |
14959 | { | |
652c393a | 14960 | struct drm_i915_private *dev_priv = dev->dev_private; |
1fe47785 | 14961 | int sprite, ret; |
8cc87b75 | 14962 | enum pipe pipe; |
46f297fb | 14963 | struct intel_crtc *crtc; |
79e53945 JB |
14964 | |
14965 | drm_mode_config_init(dev); | |
14966 | ||
14967 | dev->mode_config.min_width = 0; | |
14968 | dev->mode_config.min_height = 0; | |
14969 | ||
019d96cb DA |
14970 | dev->mode_config.preferred_depth = 24; |
14971 | dev->mode_config.prefer_shadow = 1; | |
14972 | ||
25bab385 TU |
14973 | dev->mode_config.allow_fb_modifiers = true; |
14974 | ||
e6ecefaa | 14975 | dev->mode_config.funcs = &intel_mode_funcs; |
79e53945 | 14976 | |
b690e96c JB |
14977 | intel_init_quirks(dev); |
14978 | ||
1fa61106 ED |
14979 | intel_init_pm(dev); |
14980 | ||
e3c74757 BW |
14981 | if (INTEL_INFO(dev)->num_pipes == 0) |
14982 | return; | |
14983 | ||
e70236a8 | 14984 | intel_init_display(dev); |
7c10a2b5 | 14985 | intel_init_audio(dev); |
e70236a8 | 14986 | |
a6c45cf0 CW |
14987 | if (IS_GEN2(dev)) { |
14988 | dev->mode_config.max_width = 2048; | |
14989 | dev->mode_config.max_height = 2048; | |
14990 | } else if (IS_GEN3(dev)) { | |
5e4d6fa7 KP |
14991 | dev->mode_config.max_width = 4096; |
14992 | dev->mode_config.max_height = 4096; | |
79e53945 | 14993 | } else { |
a6c45cf0 CW |
14994 | dev->mode_config.max_width = 8192; |
14995 | dev->mode_config.max_height = 8192; | |
79e53945 | 14996 | } |
068be561 | 14997 | |
dc41c154 VS |
14998 | if (IS_845G(dev) || IS_I865G(dev)) { |
14999 | dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512; | |
15000 | dev->mode_config.cursor_height = 1023; | |
15001 | } else if (IS_GEN2(dev)) { | |
068be561 DL |
15002 | dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH; |
15003 | dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT; | |
15004 | } else { | |
15005 | dev->mode_config.cursor_width = MAX_CURSOR_WIDTH; | |
15006 | dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT; | |
15007 | } | |
15008 | ||
5d4545ae | 15009 | dev->mode_config.fb_base = dev_priv->gtt.mappable_base; |
79e53945 | 15010 | |
28c97730 | 15011 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
7eb552ae BW |
15012 | INTEL_INFO(dev)->num_pipes, |
15013 | INTEL_INFO(dev)->num_pipes > 1 ? "s" : ""); | |
79e53945 | 15014 | |
055e393f | 15015 | for_each_pipe(dev_priv, pipe) { |
8cc87b75 | 15016 | intel_crtc_init(dev, pipe); |
3bdcfc0c | 15017 | for_each_sprite(dev_priv, pipe, sprite) { |
1fe47785 | 15018 | ret = intel_plane_init(dev, pipe, sprite); |
7f1f3851 | 15019 | if (ret) |
06da8da2 | 15020 | DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n", |
1fe47785 | 15021 | pipe_name(pipe), sprite_name(pipe, sprite), ret); |
7f1f3851 | 15022 | } |
79e53945 JB |
15023 | } |
15024 | ||
f42bb70d JB |
15025 | intel_init_dpio(dev); |
15026 | ||
e72f9fbf | 15027 | intel_shared_dpll_init(dev); |
ee7b9f93 | 15028 | |
9cce37f4 JB |
15029 | /* Just disable it once at startup */ |
15030 | i915_disable_vga(dev); | |
79e53945 | 15031 | intel_setup_outputs(dev); |
11be49eb CW |
15032 | |
15033 | /* Just in case the BIOS is doing something questionable. */ | |
7ff0ebcc | 15034 | intel_fbc_disable(dev); |
fa9fa083 | 15035 | |
6e9f798d | 15036 | drm_modeset_lock_all(dev); |
fa9fa083 | 15037 | intel_modeset_setup_hw_state(dev, false); |
6e9f798d | 15038 | drm_modeset_unlock_all(dev); |
46f297fb | 15039 | |
d3fcc808 | 15040 | for_each_intel_crtc(dev, crtc) { |
46f297fb JB |
15041 | if (!crtc->active) |
15042 | continue; | |
15043 | ||
46f297fb | 15044 | /* |
46f297fb JB |
15045 | * Note that reserving the BIOS fb up front prevents us |
15046 | * from stuffing other stolen allocations like the ring | |
15047 | * on top. This prevents some ugliness at boot time, and | |
15048 | * can even allow for smooth boot transitions if the BIOS | |
15049 | * fb is large enough for the active pipe configuration. | |
15050 | */ | |
5724dbd1 DL |
15051 | if (dev_priv->display.get_initial_plane_config) { |
15052 | dev_priv->display.get_initial_plane_config(crtc, | |
46f297fb JB |
15053 | &crtc->plane_config); |
15054 | /* | |
15055 | * If the fb is shared between multiple heads, we'll | |
15056 | * just get the first one. | |
15057 | */ | |
f6936e29 | 15058 | intel_find_initial_plane_obj(crtc, &crtc->plane_config); |
46f297fb | 15059 | } |
46f297fb | 15060 | } |
2c7111db CW |
15061 | } |
15062 | ||
7fad798e DV |
15063 | static void intel_enable_pipe_a(struct drm_device *dev) |
15064 | { | |
15065 | struct intel_connector *connector; | |
15066 | struct drm_connector *crt = NULL; | |
15067 | struct intel_load_detect_pipe load_detect_temp; | |
208bf9fd | 15068 | struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx; |
7fad798e DV |
15069 | |
15070 | /* We can't just switch on the pipe A, we need to set things up with a | |
15071 | * proper mode and output configuration. As a gross hack, enable pipe A | |
15072 | * by enabling the load detect pipe once. */ | |
3a3371ff | 15073 | for_each_intel_connector(dev, connector) { |
7fad798e DV |
15074 | if (connector->encoder->type == INTEL_OUTPUT_ANALOG) { |
15075 | crt = &connector->base; | |
15076 | break; | |
15077 | } | |
15078 | } | |
15079 | ||
15080 | if (!crt) | |
15081 | return; | |
15082 | ||
208bf9fd | 15083 | if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx)) |
49172fee | 15084 | intel_release_load_detect_pipe(crt, &load_detect_temp, ctx); |
7fad798e DV |
15085 | } |
15086 | ||
fa555837 DV |
15087 | static bool |
15088 | intel_check_plane_mapping(struct intel_crtc *crtc) | |
15089 | { | |
7eb552ae BW |
15090 | struct drm_device *dev = crtc->base.dev; |
15091 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fa555837 DV |
15092 | u32 reg, val; |
15093 | ||
7eb552ae | 15094 | if (INTEL_INFO(dev)->num_pipes == 1) |
fa555837 DV |
15095 | return true; |
15096 | ||
15097 | reg = DSPCNTR(!crtc->plane); | |
15098 | val = I915_READ(reg); | |
15099 | ||
15100 | if ((val & DISPLAY_PLANE_ENABLE) && | |
15101 | (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) | |
15102 | return false; | |
15103 | ||
15104 | return true; | |
15105 | } | |
15106 | ||
24929352 DV |
15107 | static void intel_sanitize_crtc(struct intel_crtc *crtc) |
15108 | { | |
15109 | struct drm_device *dev = crtc->base.dev; | |
15110 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fa555837 | 15111 | u32 reg; |
24929352 | 15112 | |
24929352 | 15113 | /* Clear any frame start delays used for debugging left by the BIOS */ |
6e3c9717 | 15114 | reg = PIPECONF(crtc->config->cpu_transcoder); |
24929352 DV |
15115 | I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); |
15116 | ||
d3eaf884 | 15117 | /* restore vblank interrupts to correct state */ |
9625604c | 15118 | drm_crtc_vblank_reset(&crtc->base); |
d297e103 VS |
15119 | if (crtc->active) { |
15120 | update_scanline_offset(crtc); | |
9625604c DV |
15121 | drm_crtc_vblank_on(&crtc->base); |
15122 | } | |
d3eaf884 | 15123 | |
24929352 | 15124 | /* We need to sanitize the plane -> pipe mapping first because this will |
fa555837 DV |
15125 | * disable the crtc (and hence change the state) if it is wrong. Note |
15126 | * that gen4+ has a fixed plane -> pipe mapping. */ | |
15127 | if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) { | |
24929352 DV |
15128 | struct intel_connector *connector; |
15129 | bool plane; | |
15130 | ||
24929352 DV |
15131 | DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n", |
15132 | crtc->base.base.id); | |
15133 | ||
15134 | /* Pipe has the wrong plane attached and the plane is active. | |
15135 | * Temporarily change the plane mapping and disable everything | |
15136 | * ... */ | |
15137 | plane = crtc->plane; | |
b70709a6 | 15138 | to_intel_plane_state(crtc->base.primary->state)->visible = true; |
37ade417 | 15139 | crtc->base.primary->crtc = &crtc->base; |
24929352 | 15140 | crtc->plane = !plane; |
1b509259 | 15141 | intel_crtc_control(&crtc->base, false); |
24929352 DV |
15142 | crtc->plane = plane; |
15143 | ||
15144 | /* ... and break all links. */ | |
3a3371ff | 15145 | for_each_intel_connector(dev, connector) { |
24929352 DV |
15146 | if (connector->encoder->base.crtc != &crtc->base) |
15147 | continue; | |
15148 | ||
7f1950fb EE |
15149 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
15150 | connector->base.encoder = NULL; | |
24929352 | 15151 | } |
7f1950fb EE |
15152 | /* multiple connectors may have the same encoder: |
15153 | * handle them and break crtc link separately */ | |
3a3371ff | 15154 | for_each_intel_connector(dev, connector) |
7f1950fb EE |
15155 | if (connector->encoder->base.crtc == &crtc->base) { |
15156 | connector->encoder->base.crtc = NULL; | |
15157 | connector->encoder->connectors_active = false; | |
15158 | } | |
24929352 DV |
15159 | |
15160 | WARN_ON(crtc->active); | |
83d65738 | 15161 | crtc->base.state->enable = false; |
49d6fa21 | 15162 | crtc->base.state->active = false; |
24929352 DV |
15163 | crtc->base.enabled = false; |
15164 | } | |
24929352 | 15165 | |
7fad798e DV |
15166 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
15167 | crtc->pipe == PIPE_A && !crtc->active) { | |
15168 | /* BIOS forgot to enable pipe A, this mostly happens after | |
15169 | * resume. Force-enable the pipe to fix this, the update_dpms | |
15170 | * call below we restore the pipe to the right state, but leave | |
15171 | * the required bits on. */ | |
15172 | intel_enable_pipe_a(dev); | |
15173 | } | |
15174 | ||
24929352 DV |
15175 | /* Adjust the state of the output pipe according to whether we |
15176 | * have active connectors/encoders. */ | |
15177 | intel_crtc_update_dpms(&crtc->base); | |
15178 | ||
53d9f4e9 | 15179 | if (crtc->active != crtc->base.state->active) { |
24929352 DV |
15180 | struct intel_encoder *encoder; |
15181 | ||
15182 | /* This can happen either due to bugs in the get_hw_state | |
15183 | * functions or because the pipe is force-enabled due to the | |
15184 | * pipe A quirk. */ | |
15185 | DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n", | |
15186 | crtc->base.base.id, | |
83d65738 | 15187 | crtc->base.state->enable ? "enabled" : "disabled", |
24929352 DV |
15188 | crtc->active ? "enabled" : "disabled"); |
15189 | ||
83d65738 | 15190 | crtc->base.state->enable = crtc->active; |
49d6fa21 | 15191 | crtc->base.state->active = crtc->active; |
24929352 DV |
15192 | crtc->base.enabled = crtc->active; |
15193 | ||
15194 | /* Because we only establish the connector -> encoder -> | |
15195 | * crtc links if something is active, this means the | |
15196 | * crtc is now deactivated. Break the links. connector | |
15197 | * -> encoder links are only establish when things are | |
15198 | * actually up, hence no need to break them. */ | |
15199 | WARN_ON(crtc->active); | |
15200 | ||
15201 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) { | |
15202 | WARN_ON(encoder->connectors_active); | |
15203 | encoder->base.crtc = NULL; | |
15204 | } | |
15205 | } | |
c5ab3bc0 | 15206 | |
a3ed6aad | 15207 | if (crtc->active || HAS_GMCH_DISPLAY(dev)) { |
4cc31489 DV |
15208 | /* |
15209 | * We start out with underrun reporting disabled to avoid races. | |
15210 | * For correct bookkeeping mark this on active crtcs. | |
15211 | * | |
c5ab3bc0 DV |
15212 | * Also on gmch platforms we dont have any hardware bits to |
15213 | * disable the underrun reporting. Which means we need to start | |
15214 | * out with underrun reporting disabled also on inactive pipes, | |
15215 | * since otherwise we'll complain about the garbage we read when | |
15216 | * e.g. coming up after runtime pm. | |
15217 | * | |
4cc31489 DV |
15218 | * No protection against concurrent access is required - at |
15219 | * worst a fifo underrun happens which also sets this to false. | |
15220 | */ | |
15221 | crtc->cpu_fifo_underrun_disabled = true; | |
15222 | crtc->pch_fifo_underrun_disabled = true; | |
15223 | } | |
24929352 DV |
15224 | } |
15225 | ||
15226 | static void intel_sanitize_encoder(struct intel_encoder *encoder) | |
15227 | { | |
15228 | struct intel_connector *connector; | |
15229 | struct drm_device *dev = encoder->base.dev; | |
15230 | ||
15231 | /* We need to check both for a crtc link (meaning that the | |
15232 | * encoder is active and trying to read from a pipe) and the | |
15233 | * pipe itself being active. */ | |
15234 | bool has_active_crtc = encoder->base.crtc && | |
15235 | to_intel_crtc(encoder->base.crtc)->active; | |
15236 | ||
15237 | if (encoder->connectors_active && !has_active_crtc) { | |
15238 | DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n", | |
15239 | encoder->base.base.id, | |
8e329a03 | 15240 | encoder->base.name); |
24929352 DV |
15241 | |
15242 | /* Connector is active, but has no active pipe. This is | |
15243 | * fallout from our resume register restoring. Disable | |
15244 | * the encoder manually again. */ | |
15245 | if (encoder->base.crtc) { | |
15246 | DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n", | |
15247 | encoder->base.base.id, | |
8e329a03 | 15248 | encoder->base.name); |
24929352 | 15249 | encoder->disable(encoder); |
a62d1497 VS |
15250 | if (encoder->post_disable) |
15251 | encoder->post_disable(encoder); | |
24929352 | 15252 | } |
7f1950fb EE |
15253 | encoder->base.crtc = NULL; |
15254 | encoder->connectors_active = false; | |
24929352 DV |
15255 | |
15256 | /* Inconsistent output/port/pipe state happens presumably due to | |
15257 | * a bug in one of the get_hw_state functions. Or someplace else | |
15258 | * in our code, like the register restore mess on resume. Clamp | |
15259 | * things to off as a safer default. */ | |
3a3371ff | 15260 | for_each_intel_connector(dev, connector) { |
24929352 DV |
15261 | if (connector->encoder != encoder) |
15262 | continue; | |
7f1950fb EE |
15263 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
15264 | connector->base.encoder = NULL; | |
24929352 DV |
15265 | } |
15266 | } | |
15267 | /* Enabled encoders without active connectors will be fixed in | |
15268 | * the crtc fixup. */ | |
15269 | } | |
15270 | ||
04098753 | 15271 | void i915_redisable_vga_power_on(struct drm_device *dev) |
0fde901f KM |
15272 | { |
15273 | struct drm_i915_private *dev_priv = dev->dev_private; | |
766aa1c4 | 15274 | u32 vga_reg = i915_vgacntrl_reg(dev); |
0fde901f | 15275 | |
04098753 ID |
15276 | if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) { |
15277 | DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n"); | |
15278 | i915_disable_vga(dev); | |
15279 | } | |
15280 | } | |
15281 | ||
15282 | void i915_redisable_vga(struct drm_device *dev) | |
15283 | { | |
15284 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15285 | ||
8dc8a27c PZ |
15286 | /* This function can be called both from intel_modeset_setup_hw_state or |
15287 | * at a very early point in our resume sequence, where the power well | |
15288 | * structures are not yet restored. Since this function is at a very | |
15289 | * paranoid "someone might have enabled VGA while we were not looking" | |
15290 | * level, just check if the power well is enabled instead of trying to | |
15291 | * follow the "don't touch the power well if we don't need it" policy | |
15292 | * the rest of the driver uses. */ | |
f458ebbc | 15293 | if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA)) |
8dc8a27c PZ |
15294 | return; |
15295 | ||
04098753 | 15296 | i915_redisable_vga_power_on(dev); |
0fde901f KM |
15297 | } |
15298 | ||
98ec7739 VS |
15299 | static bool primary_get_hw_state(struct intel_crtc *crtc) |
15300 | { | |
15301 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
15302 | ||
37ade417 | 15303 | if (!crtc->base.enabled) |
98ec7739 VS |
15304 | return false; |
15305 | ||
15306 | return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE; | |
15307 | } | |
15308 | ||
37ade417 ACO |
15309 | static int readout_hw_crtc_state(struct drm_atomic_state *state, |
15310 | struct intel_crtc *crtc) | |
24929352 | 15311 | { |
37ade417 ACO |
15312 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
15313 | struct intel_crtc_state *crtc_state; | |
15314 | struct drm_plane *primary = crtc->base.primary; | |
15315 | struct drm_plane_state *drm_plane_state; | |
15316 | struct intel_plane_state *plane_state; | |
15317 | int ret; | |
24929352 | 15318 | |
37ade417 ACO |
15319 | crtc_state = intel_atomic_get_crtc_state(state, crtc); |
15320 | if (IS_ERR(crtc_state)) | |
15321 | return PTR_ERR(crtc_state); | |
b70709a6 | 15322 | |
37ade417 ACO |
15323 | ret = drm_atomic_add_affected_planes(state, &crtc->base); |
15324 | if (ret) | |
15325 | return ret; | |
3b117c8f | 15326 | |
37ade417 ACO |
15327 | memset(crtc_state, 0, sizeof(*crtc_state)); |
15328 | crtc_state->base.crtc = &crtc->base; | |
15329 | crtc_state->base.state = state; | |
9953599b | 15330 | |
37ade417 | 15331 | crtc_state->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE; |
24929352 | 15332 | |
37ade417 ACO |
15333 | crtc_state->base.enable = crtc_state->base.active = |
15334 | crtc->base.enabled = dev_priv->display.get_pipe_config(crtc, crtc_state); | |
b70709a6 | 15335 | |
37ade417 ACO |
15336 | /* update transitional state */ |
15337 | crtc->active = crtc_state->base.active; | |
15338 | crtc->config = crtc_state; | |
24929352 | 15339 | |
37ade417 ACO |
15340 | drm_plane_state = drm_atomic_get_plane_state(state, primary); |
15341 | if (IS_ERR(drm_plane_state)) | |
15342 | return PTR_ERR(drm_plane_state); | |
15343 | ||
15344 | plane_state = to_intel_plane_state(drm_plane_state); | |
15345 | plane_state->visible = primary_get_hw_state(crtc); | |
15346 | ||
15347 | if (plane_state->visible) { | |
15348 | primary->crtc = &crtc->base; | |
15349 | crtc_state->base.plane_mask |= 1 << drm_plane_index(primary); | |
15350 | } else | |
15351 | crtc_state->base.plane_mask &= ~(1 << drm_plane_index(primary)); | |
15352 | ||
15353 | DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n", | |
15354 | crtc->base.base.id, | |
15355 | crtc_state->base.active ? "enabled" : "disabled"); | |
15356 | ||
15357 | return 0; | |
15358 | } | |
24929352 | 15359 | |
37ade417 ACO |
15360 | static int readout_hw_pll_state(struct drm_atomic_state *state) |
15361 | { | |
15362 | struct drm_i915_private *dev_priv = to_i915(state->dev); | |
15363 | struct intel_shared_dpll_config *shared_dpll; | |
15364 | struct intel_crtc *crtc; | |
15365 | struct intel_crtc_state *crtc_state; | |
15366 | int i; | |
15367 | ||
15368 | shared_dpll = intel_atomic_get_shared_dpll_state(state); | |
5358901f DV |
15369 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
15370 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
15371 | ||
3e369b76 | 15372 | pll->on = pll->get_hw_state(dev_priv, pll, |
37ade417 ACO |
15373 | &shared_dpll[i].hw_state); |
15374 | ||
5358901f | 15375 | pll->active = 0; |
37ade417 ACO |
15376 | shared_dpll[i].crtc_mask = 0; |
15377 | ||
15378 | for_each_intel_crtc(state->dev, crtc) { | |
15379 | crtc_state = intel_atomic_get_crtc_state(state, crtc); | |
15380 | if (IS_ERR(crtc_state)) | |
15381 | return PTR_ERR(crtc_state); | |
15382 | ||
15383 | if (crtc_state->base.active && | |
15384 | crtc_state->shared_dpll == i) { | |
5358901f | 15385 | pll->active++; |
37ade417 ACO |
15386 | shared_dpll[i].crtc_mask |= |
15387 | 1 << crtc->pipe; | |
1e6f2ddc | 15388 | } |
5358901f | 15389 | } |
5358901f | 15390 | |
1e6f2ddc | 15391 | DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n", |
37ade417 ACO |
15392 | pll->name, shared_dpll[i].crtc_mask, |
15393 | pll->on); | |
bd2bb1b9 | 15394 | |
37ade417 | 15395 | if (shared_dpll[i].crtc_mask) |
bd2bb1b9 | 15396 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); |
5358901f DV |
15397 | } |
15398 | ||
37ade417 ACO |
15399 | return 0; |
15400 | } | |
24929352 | 15401 | |
37ade417 ACO |
15402 | static struct drm_connector_state * |
15403 | get_connector_state_for_encoder(struct drm_atomic_state *state, | |
15404 | struct intel_encoder *encoder) | |
15405 | { | |
15406 | struct drm_connector *connector; | |
15407 | struct drm_connector_state *connector_state; | |
15408 | int i; | |
24929352 | 15409 | |
37ade417 ACO |
15410 | for_each_connector_in_state(state, connector, connector_state, i) |
15411 | if (connector_state->best_encoder == &encoder->base) | |
15412 | return connector_state; | |
15413 | ||
15414 | return NULL; | |
15415 | } | |
15416 | ||
15417 | static int readout_hw_connector_encoder_state(struct drm_atomic_state *state) | |
15418 | { | |
15419 | struct drm_device *dev = state->dev; | |
15420 | struct drm_i915_private *dev_priv = to_i915(state->dev); | |
15421 | struct intel_crtc *crtc; | |
15422 | struct drm_crtc_state *drm_crtc_state; | |
15423 | struct intel_crtc_state *crtc_state; | |
15424 | struct intel_encoder *encoder; | |
15425 | struct intel_connector *connector; | |
15426 | struct drm_connector_state *connector_state; | |
15427 | enum pipe pipe; | |
24929352 | 15428 | |
3a3371ff | 15429 | for_each_intel_connector(dev, connector) { |
37ade417 ACO |
15430 | connector_state = |
15431 | drm_atomic_get_connector_state(state, &connector->base); | |
15432 | if (IS_ERR(connector_state)) | |
15433 | return PTR_ERR(connector_state); | |
15434 | ||
24929352 DV |
15435 | if (connector->get_hw_state(connector)) { |
15436 | connector->base.dpms = DRM_MODE_DPMS_ON; | |
24929352 DV |
15437 | connector->base.encoder = &connector->encoder->base; |
15438 | } else { | |
15439 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
15440 | connector->base.encoder = NULL; | |
15441 | } | |
37ade417 ACO |
15442 | |
15443 | /* We'll update the crtc field when reading encoder state */ | |
15444 | connector_state->crtc = NULL; | |
15445 | ||
15446 | connector_state->best_encoder = connector->base.encoder; | |
15447 | ||
24929352 DV |
15448 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n", |
15449 | connector->base.base.id, | |
c23cc417 | 15450 | connector->base.name, |
24929352 DV |
15451 | connector->base.encoder ? "enabled" : "disabled"); |
15452 | } | |
37ade417 ACO |
15453 | |
15454 | for_each_intel_encoder(dev, encoder) { | |
15455 | pipe = 0; | |
15456 | ||
15457 | connector_state = | |
15458 | get_connector_state_for_encoder(state, encoder); | |
15459 | ||
15460 | encoder->connectors_active = !!connector_state; | |
15461 | ||
15462 | if (encoder->get_hw_state(encoder, &pipe)) { | |
15463 | encoder->base.crtc = | |
15464 | dev_priv->pipe_to_crtc_mapping[pipe]; | |
15465 | crtc = to_intel_crtc(encoder->base.crtc); | |
15466 | ||
15467 | drm_crtc_state = | |
15468 | state->crtc_states[drm_crtc_index(&crtc->base)]; | |
15469 | crtc_state = to_intel_crtc_state(drm_crtc_state); | |
15470 | ||
15471 | encoder->get_config(encoder, crtc_state); | |
15472 | ||
15473 | if (connector_state) | |
15474 | connector_state->crtc = &crtc->base; | |
15475 | } else { | |
15476 | encoder->base.crtc = NULL; | |
15477 | } | |
15478 | ||
15479 | DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n", | |
15480 | encoder->base.base.id, | |
15481 | encoder->base.name, | |
15482 | encoder->base.crtc ? "enabled" : "disabled", | |
15483 | pipe_name(pipe)); | |
15484 | } | |
15485 | ||
15486 | return 0; | |
15487 | } | |
15488 | ||
15489 | static struct drm_atomic_state * | |
15490 | intel_modeset_readout_hw_state(struct drm_device *dev) | |
15491 | { | |
15492 | struct intel_crtc *crtc; | |
15493 | int ret = 0; | |
15494 | ||
15495 | struct drm_atomic_state *state; | |
15496 | ||
15497 | state = drm_atomic_state_alloc(dev); | |
15498 | if (!state) | |
15499 | return ERR_PTR(-ENOMEM); | |
15500 | ||
15501 | state->acquire_ctx = dev->mode_config.acquire_ctx; | |
15502 | ||
15503 | for_each_intel_crtc(dev, crtc) { | |
15504 | ret = readout_hw_crtc_state(state, crtc); | |
15505 | if (ret) | |
15506 | goto err_free; | |
15507 | } | |
15508 | ||
15509 | ret = readout_hw_pll_state(state); | |
15510 | if (ret) | |
15511 | goto err_free; | |
15512 | ||
15513 | ret = readout_hw_connector_encoder_state(state); | |
15514 | if (ret) | |
15515 | goto err_free; | |
15516 | ||
15517 | return state; | |
15518 | ||
15519 | err_free: | |
15520 | drm_atomic_state_free(state); | |
15521 | return ERR_PTR(ret); | |
30e984df DV |
15522 | } |
15523 | ||
15524 | /* Scan out the current hw modeset state, sanitizes it and maps it into the drm | |
15525 | * and i915 state tracking structures. */ | |
15526 | void intel_modeset_setup_hw_state(struct drm_device *dev, | |
15527 | bool force_restore) | |
15528 | { | |
15529 | struct drm_i915_private *dev_priv = dev->dev_private; | |
37ade417 ACO |
15530 | struct drm_crtc *crtc; |
15531 | struct drm_crtc_state *crtc_state; | |
30e984df | 15532 | struct intel_encoder *encoder; |
37ade417 ACO |
15533 | struct drm_atomic_state *state; |
15534 | struct intel_shared_dpll_config shared_dplls[I915_NUM_PLLS]; | |
35c95375 | 15535 | int i; |
30e984df | 15536 | |
37ade417 ACO |
15537 | state = intel_modeset_readout_hw_state(dev); |
15538 | if (IS_ERR(state)) { | |
15539 | DRM_ERROR("Failed to read out hw state\n"); | |
15540 | return; | |
babea61d JB |
15541 | } |
15542 | ||
37ade417 ACO |
15543 | drm_atomic_helper_swap_state(dev, state); |
15544 | ||
15545 | /* swap sw/hw dpll state */ | |
15546 | intel_atomic_duplicate_dpll_state(dev_priv, shared_dplls); | |
15547 | intel_shared_dpll_commit(state); | |
15548 | memcpy(to_intel_atomic_state(state)->shared_dpll, | |
15549 | shared_dplls, sizeof(*shared_dplls) * dev_priv->num_shared_dpll); | |
15550 | ||
24929352 | 15551 | /* HW state is read out, now we need to sanitize this mess. */ |
b2784e15 | 15552 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
15553 | intel_sanitize_encoder(encoder); |
15554 | } | |
15555 | ||
37ade417 ACO |
15556 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
15557 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
15558 | ||
15559 | /* prevent unnneeded restores with force_restore */ | |
15560 | crtc_state->active_changed = | |
15561 | crtc_state->mode_changed = | |
15562 | crtc_state->planes_changed = false; | |
15563 | ||
15564 | if (crtc->enabled) { | |
15565 | intel_mode_from_pipe_config(&crtc->state->mode, | |
15566 | to_intel_crtc_state(crtc->state)); | |
15567 | ||
15568 | drm_mode_copy(&crtc->mode, &crtc->state->mode); | |
15569 | drm_mode_copy(&crtc->hwmode, | |
15570 | &crtc->state->adjusted_mode); | |
15571 | } | |
15572 | ||
15573 | intel_sanitize_crtc(intel_crtc); | |
15574 | ||
15575 | /* | |
15576 | * sanitize_crtc may have forced an update of crtc->state, | |
15577 | * so reload in intel_dump_pipe_config | |
15578 | */ | |
15579 | intel_dump_pipe_config(intel_crtc, | |
15580 | to_intel_crtc_state(crtc->state), | |
6e3c9717 | 15581 | "[setup_hw_state]"); |
24929352 | 15582 | } |
9a935856 | 15583 | |
d29b2f9d ACO |
15584 | intel_modeset_update_connector_atomic_state(dev); |
15585 | ||
35c95375 DV |
15586 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
15587 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
15588 | ||
15589 | if (!pll->on || pll->active) | |
15590 | continue; | |
15591 | ||
15592 | DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name); | |
15593 | ||
15594 | pll->disable(dev_priv, pll); | |
15595 | pll->on = false; | |
15596 | } | |
15597 | ||
3078999f PB |
15598 | if (IS_GEN9(dev)) |
15599 | skl_wm_get_hw_state(dev); | |
15600 | else if (HAS_PCH_SPLIT(dev)) | |
243e6a44 VS |
15601 | ilk_wm_get_hw_state(dev); |
15602 | ||
45e2b5f6 | 15603 | if (force_restore) { |
37ade417 | 15604 | int ret; |
7d0bc1ea | 15605 | |
37ade417 | 15606 | i915_redisable_vga(dev); |
f30da187 | 15607 | |
37ade417 ACO |
15608 | ret = intel_set_mode(state); |
15609 | if (ret) { | |
15610 | DRM_ERROR("Failed to restore previous mode\n"); | |
15611 | drm_atomic_state_free(state); | |
45e2b5f6 DV |
15612 | } |
15613 | } else { | |
37ade417 | 15614 | drm_atomic_state_free(state); |
45e2b5f6 | 15615 | } |
8af6cf88 DV |
15616 | |
15617 | intel_modeset_check_state(dev); | |
2c7111db CW |
15618 | } |
15619 | ||
15620 | void intel_modeset_gem_init(struct drm_device *dev) | |
15621 | { | |
92122789 | 15622 | struct drm_i915_private *dev_priv = dev->dev_private; |
484b41dd | 15623 | struct drm_crtc *c; |
2ff8fde1 | 15624 | struct drm_i915_gem_object *obj; |
e0d6149b | 15625 | int ret; |
484b41dd | 15626 | |
ae48434c ID |
15627 | mutex_lock(&dev->struct_mutex); |
15628 | intel_init_gt_powersave(dev); | |
15629 | mutex_unlock(&dev->struct_mutex); | |
15630 | ||
92122789 JB |
15631 | /* |
15632 | * There may be no VBT; and if the BIOS enabled SSC we can | |
15633 | * just keep using it to avoid unnecessary flicker. Whereas if the | |
15634 | * BIOS isn't using it, don't assume it will work even if the VBT | |
15635 | * indicates as much. | |
15636 | */ | |
15637 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
15638 | dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) & | |
15639 | DREF_SSC1_ENABLE); | |
15640 | ||
1833b134 | 15641 | intel_modeset_init_hw(dev); |
02e792fb DV |
15642 | |
15643 | intel_setup_overlay(dev); | |
484b41dd JB |
15644 | |
15645 | /* | |
15646 | * Make sure any fbs we allocated at startup are properly | |
15647 | * pinned & fenced. When we do the allocation it's too early | |
15648 | * for this. | |
15649 | */ | |
70e1e0ec | 15650 | for_each_crtc(dev, c) { |
2ff8fde1 MR |
15651 | obj = intel_fb_obj(c->primary->fb); |
15652 | if (obj == NULL) | |
484b41dd JB |
15653 | continue; |
15654 | ||
e0d6149b TU |
15655 | mutex_lock(&dev->struct_mutex); |
15656 | ret = intel_pin_and_fence_fb_obj(c->primary, | |
15657 | c->primary->fb, | |
15658 | c->primary->state, | |
15659 | NULL); | |
15660 | mutex_unlock(&dev->struct_mutex); | |
15661 | if (ret) { | |
484b41dd JB |
15662 | DRM_ERROR("failed to pin boot fb on pipe %d\n", |
15663 | to_intel_crtc(c)->pipe); | |
66e514c1 DA |
15664 | drm_framebuffer_unreference(c->primary->fb); |
15665 | c->primary->fb = NULL; | |
36750f28 | 15666 | c->primary->crtc = c->primary->state->crtc = NULL; |
afd65eb4 | 15667 | update_state_fb(c->primary); |
36750f28 | 15668 | c->state->plane_mask &= ~(1 << drm_plane_index(c->primary)); |
484b41dd JB |
15669 | } |
15670 | } | |
0962c3c9 VS |
15671 | |
15672 | intel_backlight_register(dev); | |
79e53945 JB |
15673 | } |
15674 | ||
4932e2c3 ID |
15675 | void intel_connector_unregister(struct intel_connector *intel_connector) |
15676 | { | |
15677 | struct drm_connector *connector = &intel_connector->base; | |
15678 | ||
15679 | intel_panel_destroy_backlight(connector); | |
34ea3d38 | 15680 | drm_connector_unregister(connector); |
4932e2c3 ID |
15681 | } |
15682 | ||
79e53945 JB |
15683 | void intel_modeset_cleanup(struct drm_device *dev) |
15684 | { | |
652c393a | 15685 | struct drm_i915_private *dev_priv = dev->dev_private; |
d9255d57 | 15686 | struct drm_connector *connector; |
652c393a | 15687 | |
2eb5252e ID |
15688 | intel_disable_gt_powersave(dev); |
15689 | ||
0962c3c9 VS |
15690 | intel_backlight_unregister(dev); |
15691 | ||
fd0c0642 DV |
15692 | /* |
15693 | * Interrupts and polling as the first thing to avoid creating havoc. | |
2eb5252e | 15694 | * Too much stuff here (turning of connectors, ...) would |
fd0c0642 DV |
15695 | * experience fancy races otherwise. |
15696 | */ | |
2aeb7d3a | 15697 | intel_irq_uninstall(dev_priv); |
eb21b92b | 15698 | |
fd0c0642 DV |
15699 | /* |
15700 | * Due to the hpd irq storm handling the hotplug work can re-arm the | |
15701 | * poll handlers. Hence disable polling after hpd handling is shut down. | |
15702 | */ | |
f87ea761 | 15703 | drm_kms_helper_poll_fini(dev); |
fd0c0642 | 15704 | |
652c393a JB |
15705 | mutex_lock(&dev->struct_mutex); |
15706 | ||
723bfd70 JB |
15707 | intel_unregister_dsm_handler(); |
15708 | ||
7ff0ebcc | 15709 | intel_fbc_disable(dev); |
e70236a8 | 15710 | |
69341a5e KH |
15711 | mutex_unlock(&dev->struct_mutex); |
15712 | ||
1630fe75 CW |
15713 | /* flush any delayed tasks or pending work */ |
15714 | flush_scheduled_work(); | |
15715 | ||
db31af1d JN |
15716 | /* destroy the backlight and sysfs files before encoders/connectors */ |
15717 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
4932e2c3 ID |
15718 | struct intel_connector *intel_connector; |
15719 | ||
15720 | intel_connector = to_intel_connector(connector); | |
15721 | intel_connector->unregister(intel_connector); | |
db31af1d | 15722 | } |
d9255d57 | 15723 | |
79e53945 | 15724 | drm_mode_config_cleanup(dev); |
4d7bb011 DV |
15725 | |
15726 | intel_cleanup_overlay(dev); | |
ae48434c ID |
15727 | |
15728 | mutex_lock(&dev->struct_mutex); | |
15729 | intel_cleanup_gt_powersave(dev); | |
15730 | mutex_unlock(&dev->struct_mutex); | |
79e53945 JB |
15731 | } |
15732 | ||
f1c79df3 ZW |
15733 | /* |
15734 | * Return which encoder is currently attached for connector. | |
15735 | */ | |
df0e9248 | 15736 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector) |
79e53945 | 15737 | { |
df0e9248 CW |
15738 | return &intel_attached_encoder(connector)->base; |
15739 | } | |
f1c79df3 | 15740 | |
df0e9248 CW |
15741 | void intel_connector_attach_encoder(struct intel_connector *connector, |
15742 | struct intel_encoder *encoder) | |
15743 | { | |
15744 | connector->encoder = encoder; | |
15745 | drm_mode_connector_attach_encoder(&connector->base, | |
15746 | &encoder->base); | |
79e53945 | 15747 | } |
28d52043 DA |
15748 | |
15749 | /* | |
15750 | * set vga decode state - true == enable VGA decode | |
15751 | */ | |
15752 | int intel_modeset_vga_set_state(struct drm_device *dev, bool state) | |
15753 | { | |
15754 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a885b3cc | 15755 | unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; |
28d52043 DA |
15756 | u16 gmch_ctrl; |
15757 | ||
75fa041d CW |
15758 | if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) { |
15759 | DRM_ERROR("failed to read control word\n"); | |
15760 | return -EIO; | |
15761 | } | |
15762 | ||
c0cc8a55 CW |
15763 | if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state) |
15764 | return 0; | |
15765 | ||
28d52043 DA |
15766 | if (state) |
15767 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; | |
15768 | else | |
15769 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; | |
75fa041d CW |
15770 | |
15771 | if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) { | |
15772 | DRM_ERROR("failed to write control word\n"); | |
15773 | return -EIO; | |
15774 | } | |
15775 | ||
28d52043 DA |
15776 | return 0; |
15777 | } | |
c4a1d9e4 | 15778 | |
c4a1d9e4 | 15779 | struct intel_display_error_state { |
ff57f1b0 PZ |
15780 | |
15781 | u32 power_well_driver; | |
15782 | ||
63b66e5b CW |
15783 | int num_transcoders; |
15784 | ||
c4a1d9e4 CW |
15785 | struct intel_cursor_error_state { |
15786 | u32 control; | |
15787 | u32 position; | |
15788 | u32 base; | |
15789 | u32 size; | |
52331309 | 15790 | } cursor[I915_MAX_PIPES]; |
c4a1d9e4 CW |
15791 | |
15792 | struct intel_pipe_error_state { | |
ddf9c536 | 15793 | bool power_domain_on; |
c4a1d9e4 | 15794 | u32 source; |
f301b1e1 | 15795 | u32 stat; |
52331309 | 15796 | } pipe[I915_MAX_PIPES]; |
c4a1d9e4 CW |
15797 | |
15798 | struct intel_plane_error_state { | |
15799 | u32 control; | |
15800 | u32 stride; | |
15801 | u32 size; | |
15802 | u32 pos; | |
15803 | u32 addr; | |
15804 | u32 surface; | |
15805 | u32 tile_offset; | |
52331309 | 15806 | } plane[I915_MAX_PIPES]; |
63b66e5b CW |
15807 | |
15808 | struct intel_transcoder_error_state { | |
ddf9c536 | 15809 | bool power_domain_on; |
63b66e5b CW |
15810 | enum transcoder cpu_transcoder; |
15811 | ||
15812 | u32 conf; | |
15813 | ||
15814 | u32 htotal; | |
15815 | u32 hblank; | |
15816 | u32 hsync; | |
15817 | u32 vtotal; | |
15818 | u32 vblank; | |
15819 | u32 vsync; | |
15820 | } transcoder[4]; | |
c4a1d9e4 CW |
15821 | }; |
15822 | ||
15823 | struct intel_display_error_state * | |
15824 | intel_display_capture_error_state(struct drm_device *dev) | |
15825 | { | |
fbee40df | 15826 | struct drm_i915_private *dev_priv = dev->dev_private; |
c4a1d9e4 | 15827 | struct intel_display_error_state *error; |
63b66e5b CW |
15828 | int transcoders[] = { |
15829 | TRANSCODER_A, | |
15830 | TRANSCODER_B, | |
15831 | TRANSCODER_C, | |
15832 | TRANSCODER_EDP, | |
15833 | }; | |
c4a1d9e4 CW |
15834 | int i; |
15835 | ||
63b66e5b CW |
15836 | if (INTEL_INFO(dev)->num_pipes == 0) |
15837 | return NULL; | |
15838 | ||
9d1cb914 | 15839 | error = kzalloc(sizeof(*error), GFP_ATOMIC); |
c4a1d9e4 CW |
15840 | if (error == NULL) |
15841 | return NULL; | |
15842 | ||
190be112 | 15843 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
ff57f1b0 PZ |
15844 | error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER); |
15845 | ||
055e393f | 15846 | for_each_pipe(dev_priv, i) { |
ddf9c536 | 15847 | error->pipe[i].power_domain_on = |
f458ebbc DV |
15848 | __intel_display_power_is_enabled(dev_priv, |
15849 | POWER_DOMAIN_PIPE(i)); | |
ddf9c536 | 15850 | if (!error->pipe[i].power_domain_on) |
9d1cb914 PZ |
15851 | continue; |
15852 | ||
5efb3e28 VS |
15853 | error->cursor[i].control = I915_READ(CURCNTR(i)); |
15854 | error->cursor[i].position = I915_READ(CURPOS(i)); | |
15855 | error->cursor[i].base = I915_READ(CURBASE(i)); | |
c4a1d9e4 CW |
15856 | |
15857 | error->plane[i].control = I915_READ(DSPCNTR(i)); | |
15858 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); | |
80ca378b | 15859 | if (INTEL_INFO(dev)->gen <= 3) { |
51889b35 | 15860 | error->plane[i].size = I915_READ(DSPSIZE(i)); |
80ca378b PZ |
15861 | error->plane[i].pos = I915_READ(DSPPOS(i)); |
15862 | } | |
ca291363 PZ |
15863 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
15864 | error->plane[i].addr = I915_READ(DSPADDR(i)); | |
c4a1d9e4 CW |
15865 | if (INTEL_INFO(dev)->gen >= 4) { |
15866 | error->plane[i].surface = I915_READ(DSPSURF(i)); | |
15867 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); | |
15868 | } | |
15869 | ||
c4a1d9e4 | 15870 | error->pipe[i].source = I915_READ(PIPESRC(i)); |
f301b1e1 | 15871 | |
3abfce77 | 15872 | if (HAS_GMCH_DISPLAY(dev)) |
f301b1e1 | 15873 | error->pipe[i].stat = I915_READ(PIPESTAT(i)); |
63b66e5b CW |
15874 | } |
15875 | ||
15876 | error->num_transcoders = INTEL_INFO(dev)->num_pipes; | |
15877 | if (HAS_DDI(dev_priv->dev)) | |
15878 | error->num_transcoders++; /* Account for eDP. */ | |
15879 | ||
15880 | for (i = 0; i < error->num_transcoders; i++) { | |
15881 | enum transcoder cpu_transcoder = transcoders[i]; | |
15882 | ||
ddf9c536 | 15883 | error->transcoder[i].power_domain_on = |
f458ebbc | 15884 | __intel_display_power_is_enabled(dev_priv, |
38cc1daf | 15885 | POWER_DOMAIN_TRANSCODER(cpu_transcoder)); |
ddf9c536 | 15886 | if (!error->transcoder[i].power_domain_on) |
9d1cb914 PZ |
15887 | continue; |
15888 | ||
63b66e5b CW |
15889 | error->transcoder[i].cpu_transcoder = cpu_transcoder; |
15890 | ||
15891 | error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder)); | |
15892 | error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder)); | |
15893 | error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder)); | |
15894 | error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder)); | |
15895 | error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder)); | |
15896 | error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder)); | |
15897 | error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder)); | |
c4a1d9e4 CW |
15898 | } |
15899 | ||
15900 | return error; | |
15901 | } | |
15902 | ||
edc3d884 MK |
15903 | #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) |
15904 | ||
c4a1d9e4 | 15905 | void |
edc3d884 | 15906 | intel_display_print_error_state(struct drm_i915_error_state_buf *m, |
c4a1d9e4 CW |
15907 | struct drm_device *dev, |
15908 | struct intel_display_error_state *error) | |
15909 | { | |
055e393f | 15910 | struct drm_i915_private *dev_priv = dev->dev_private; |
c4a1d9e4 CW |
15911 | int i; |
15912 | ||
63b66e5b CW |
15913 | if (!error) |
15914 | return; | |
15915 | ||
edc3d884 | 15916 | err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes); |
190be112 | 15917 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
edc3d884 | 15918 | err_printf(m, "PWR_WELL_CTL2: %08x\n", |
ff57f1b0 | 15919 | error->power_well_driver); |
055e393f | 15920 | for_each_pipe(dev_priv, i) { |
edc3d884 | 15921 | err_printf(m, "Pipe [%d]:\n", i); |
ddf9c536 ID |
15922 | err_printf(m, " Power: %s\n", |
15923 | error->pipe[i].power_domain_on ? "on" : "off"); | |
edc3d884 | 15924 | err_printf(m, " SRC: %08x\n", error->pipe[i].source); |
f301b1e1 | 15925 | err_printf(m, " STAT: %08x\n", error->pipe[i].stat); |
edc3d884 MK |
15926 | |
15927 | err_printf(m, "Plane [%d]:\n", i); | |
15928 | err_printf(m, " CNTR: %08x\n", error->plane[i].control); | |
15929 | err_printf(m, " STRIDE: %08x\n", error->plane[i].stride); | |
80ca378b | 15930 | if (INTEL_INFO(dev)->gen <= 3) { |
edc3d884 MK |
15931 | err_printf(m, " SIZE: %08x\n", error->plane[i].size); |
15932 | err_printf(m, " POS: %08x\n", error->plane[i].pos); | |
80ca378b | 15933 | } |
4b71a570 | 15934 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
edc3d884 | 15935 | err_printf(m, " ADDR: %08x\n", error->plane[i].addr); |
c4a1d9e4 | 15936 | if (INTEL_INFO(dev)->gen >= 4) { |
edc3d884 MK |
15937 | err_printf(m, " SURF: %08x\n", error->plane[i].surface); |
15938 | err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); | |
c4a1d9e4 CW |
15939 | } |
15940 | ||
edc3d884 MK |
15941 | err_printf(m, "Cursor [%d]:\n", i); |
15942 | err_printf(m, " CNTR: %08x\n", error->cursor[i].control); | |
15943 | err_printf(m, " POS: %08x\n", error->cursor[i].position); | |
15944 | err_printf(m, " BASE: %08x\n", error->cursor[i].base); | |
c4a1d9e4 | 15945 | } |
63b66e5b CW |
15946 | |
15947 | for (i = 0; i < error->num_transcoders; i++) { | |
1cf84bb6 | 15948 | err_printf(m, "CPU transcoder: %c\n", |
63b66e5b | 15949 | transcoder_name(error->transcoder[i].cpu_transcoder)); |
ddf9c536 ID |
15950 | err_printf(m, " Power: %s\n", |
15951 | error->transcoder[i].power_domain_on ? "on" : "off"); | |
63b66e5b CW |
15952 | err_printf(m, " CONF: %08x\n", error->transcoder[i].conf); |
15953 | err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal); | |
15954 | err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank); | |
15955 | err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync); | |
15956 | err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal); | |
15957 | err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank); | |
15958 | err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync); | |
15959 | } | |
c4a1d9e4 | 15960 | } |
e2fcdaa9 VS |
15961 | |
15962 | void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file) | |
15963 | { | |
15964 | struct intel_crtc *crtc; | |
15965 | ||
15966 | for_each_intel_crtc(dev, crtc) { | |
15967 | struct intel_unpin_work *work; | |
e2fcdaa9 | 15968 | |
5e2d7afc | 15969 | spin_lock_irq(&dev->event_lock); |
e2fcdaa9 VS |
15970 | |
15971 | work = crtc->unpin_work; | |
15972 | ||
15973 | if (work && work->event && | |
15974 | work->event->base.file_priv == file) { | |
15975 | kfree(work->event); | |
15976 | work->event = NULL; | |
15977 | } | |
15978 | ||
5e2d7afc | 15979 | spin_unlock_irq(&dev->event_lock); |
e2fcdaa9 VS |
15980 | } |
15981 | } |