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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
618563e3 | 27 | #include <linux/dmi.h> |
c1c7af60 JB |
28 | #include <linux/module.h> |
29 | #include <linux/input.h> | |
79e53945 | 30 | #include <linux/i2c.h> |
7662c8bd | 31 | #include <linux/kernel.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
9cce37f4 | 33 | #include <linux/vgaarb.h> |
e0dac65e | 34 | #include <drm/drm_edid.h> |
760285e7 | 35 | #include <drm/drmP.h> |
79e53945 | 36 | #include "intel_drv.h" |
760285e7 | 37 | #include <drm/i915_drm.h> |
79e53945 | 38 | #include "i915_drv.h" |
e5510fac | 39 | #include "i915_trace.h" |
319c1d42 | 40 | #include <drm/drm_atomic.h> |
c196e1d6 | 41 | #include <drm/drm_atomic_helper.h> |
760285e7 DH |
42 | #include <drm/drm_dp_helper.h> |
43 | #include <drm/drm_crtc_helper.h> | |
465c120c MR |
44 | #include <drm/drm_plane_helper.h> |
45 | #include <drm/drm_rect.h> | |
c0f372b3 | 46 | #include <linux/dma_remapping.h> |
79e53945 | 47 | |
465c120c | 48 | /* Primary plane formats for gen <= 3 */ |
568db4f2 | 49 | static const uint32_t i8xx_primary_formats[] = { |
67fe7dc5 DL |
50 | DRM_FORMAT_C8, |
51 | DRM_FORMAT_RGB565, | |
465c120c | 52 | DRM_FORMAT_XRGB1555, |
67fe7dc5 | 53 | DRM_FORMAT_XRGB8888, |
465c120c MR |
54 | }; |
55 | ||
56 | /* Primary plane formats for gen >= 4 */ | |
568db4f2 | 57 | static const uint32_t i965_primary_formats[] = { |
6c0fd451 DL |
58 | DRM_FORMAT_C8, |
59 | DRM_FORMAT_RGB565, | |
60 | DRM_FORMAT_XRGB8888, | |
61 | DRM_FORMAT_XBGR8888, | |
62 | DRM_FORMAT_XRGB2101010, | |
63 | DRM_FORMAT_XBGR2101010, | |
64 | }; | |
65 | ||
66 | static const uint32_t skl_primary_formats[] = { | |
67fe7dc5 DL |
67 | DRM_FORMAT_C8, |
68 | DRM_FORMAT_RGB565, | |
69 | DRM_FORMAT_XRGB8888, | |
465c120c | 70 | DRM_FORMAT_XBGR8888, |
67fe7dc5 | 71 | DRM_FORMAT_ARGB8888, |
465c120c MR |
72 | DRM_FORMAT_ABGR8888, |
73 | DRM_FORMAT_XRGB2101010, | |
465c120c | 74 | DRM_FORMAT_XBGR2101010, |
465c120c MR |
75 | }; |
76 | ||
3d7d6510 MR |
77 | /* Cursor formats */ |
78 | static const uint32_t intel_cursor_formats[] = { | |
79 | DRM_FORMAT_ARGB8888, | |
80 | }; | |
81 | ||
6b383a7f | 82 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on); |
79e53945 | 83 | |
f1f644dc | 84 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 85 | struct intel_crtc_state *pipe_config); |
18442d08 | 86 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 87 | struct intel_crtc_state *pipe_config); |
f1f644dc | 88 | |
8c7b5ccb | 89 | static int intel_set_mode(struct drm_crtc *crtc, |
83a57153 | 90 | struct drm_atomic_state *state); |
eb1bfe80 JB |
91 | static int intel_framebuffer_init(struct drm_device *dev, |
92 | struct intel_framebuffer *ifb, | |
93 | struct drm_mode_fb_cmd2 *mode_cmd, | |
94 | struct drm_i915_gem_object *obj); | |
5b18e57c DV |
95 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc); |
96 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc); | |
29407aab | 97 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, |
f769cd24 VK |
98 | struct intel_link_m_n *m_n, |
99 | struct intel_link_m_n *m2_n2); | |
29407aab | 100 | static void ironlake_set_pipeconf(struct drm_crtc *crtc); |
229fca97 DV |
101 | static void haswell_set_pipeconf(struct drm_crtc *crtc); |
102 | static void intel_set_pipe_csc(struct drm_crtc *crtc); | |
d288f65f | 103 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 104 | const struct intel_crtc_state *pipe_config); |
d288f65f | 105 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 106 | const struct intel_crtc_state *pipe_config); |
ea2c67bb MR |
107 | static void intel_begin_crtc_commit(struct drm_crtc *crtc); |
108 | static void intel_finish_crtc_commit(struct drm_crtc *crtc); | |
549e2bfb CK |
109 | static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc, |
110 | struct intel_crtc_state *crtc_state); | |
5ab7b0b7 ID |
111 | static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state, |
112 | int num_connectors); | |
ce22dba9 ML |
113 | static void intel_crtc_enable_planes(struct drm_crtc *crtc); |
114 | static void intel_crtc_disable_planes(struct drm_crtc *crtc); | |
e7457a9a | 115 | |
0e32b39c DA |
116 | static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe) |
117 | { | |
118 | if (!connector->mst_port) | |
119 | return connector->encoder; | |
120 | else | |
121 | return &connector->mst_port->mst_encoders[pipe]->base; | |
122 | } | |
123 | ||
79e53945 | 124 | typedef struct { |
0206e353 | 125 | int min, max; |
79e53945 JB |
126 | } intel_range_t; |
127 | ||
128 | typedef struct { | |
0206e353 AJ |
129 | int dot_limit; |
130 | int p2_slow, p2_fast; | |
79e53945 JB |
131 | } intel_p2_t; |
132 | ||
d4906093 ML |
133 | typedef struct intel_limit intel_limit_t; |
134 | struct intel_limit { | |
0206e353 AJ |
135 | intel_range_t dot, vco, n, m, m1, m2, p, p1; |
136 | intel_p2_t p2; | |
d4906093 | 137 | }; |
79e53945 | 138 | |
d2acd215 DV |
139 | int |
140 | intel_pch_rawclk(struct drm_device *dev) | |
141 | { | |
142 | struct drm_i915_private *dev_priv = dev->dev_private; | |
143 | ||
144 | WARN_ON(!HAS_PCH_SPLIT(dev)); | |
145 | ||
146 | return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK; | |
147 | } | |
148 | ||
021357ac CW |
149 | static inline u32 /* units of 100MHz */ |
150 | intel_fdi_link_freq(struct drm_device *dev) | |
151 | { | |
8b99e68c CW |
152 | if (IS_GEN5(dev)) { |
153 | struct drm_i915_private *dev_priv = dev->dev_private; | |
154 | return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2; | |
155 | } else | |
156 | return 27; | |
021357ac CW |
157 | } |
158 | ||
5d536e28 | 159 | static const intel_limit_t intel_limits_i8xx_dac = { |
0206e353 | 160 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 161 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 162 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
163 | .m = { .min = 96, .max = 140 }, |
164 | .m1 = { .min = 18, .max = 26 }, | |
165 | .m2 = { .min = 6, .max = 16 }, | |
166 | .p = { .min = 4, .max = 128 }, | |
167 | .p1 = { .min = 2, .max = 33 }, | |
273e27ca EA |
168 | .p2 = { .dot_limit = 165000, |
169 | .p2_slow = 4, .p2_fast = 2 }, | |
e4b36699 KP |
170 | }; |
171 | ||
5d536e28 DV |
172 | static const intel_limit_t intel_limits_i8xx_dvo = { |
173 | .dot = { .min = 25000, .max = 350000 }, | |
9c333719 | 174 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 175 | .n = { .min = 2, .max = 16 }, |
5d536e28 DV |
176 | .m = { .min = 96, .max = 140 }, |
177 | .m1 = { .min = 18, .max = 26 }, | |
178 | .m2 = { .min = 6, .max = 16 }, | |
179 | .p = { .min = 4, .max = 128 }, | |
180 | .p1 = { .min = 2, .max = 33 }, | |
181 | .p2 = { .dot_limit = 165000, | |
182 | .p2_slow = 4, .p2_fast = 4 }, | |
183 | }; | |
184 | ||
e4b36699 | 185 | static const intel_limit_t intel_limits_i8xx_lvds = { |
0206e353 | 186 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 187 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 188 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
189 | .m = { .min = 96, .max = 140 }, |
190 | .m1 = { .min = 18, .max = 26 }, | |
191 | .m2 = { .min = 6, .max = 16 }, | |
192 | .p = { .min = 4, .max = 128 }, | |
193 | .p1 = { .min = 1, .max = 6 }, | |
273e27ca EA |
194 | .p2 = { .dot_limit = 165000, |
195 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 | 196 | }; |
273e27ca | 197 | |
e4b36699 | 198 | static const intel_limit_t intel_limits_i9xx_sdvo = { |
0206e353 AJ |
199 | .dot = { .min = 20000, .max = 400000 }, |
200 | .vco = { .min = 1400000, .max = 2800000 }, | |
201 | .n = { .min = 1, .max = 6 }, | |
202 | .m = { .min = 70, .max = 120 }, | |
4f7dfb67 PJ |
203 | .m1 = { .min = 8, .max = 18 }, |
204 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
205 | .p = { .min = 5, .max = 80 }, |
206 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
207 | .p2 = { .dot_limit = 200000, |
208 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
209 | }; |
210 | ||
211 | static const intel_limit_t intel_limits_i9xx_lvds = { | |
0206e353 AJ |
212 | .dot = { .min = 20000, .max = 400000 }, |
213 | .vco = { .min = 1400000, .max = 2800000 }, | |
214 | .n = { .min = 1, .max = 6 }, | |
215 | .m = { .min = 70, .max = 120 }, | |
53a7d2d1 PJ |
216 | .m1 = { .min = 8, .max = 18 }, |
217 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
218 | .p = { .min = 7, .max = 98 }, |
219 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
220 | .p2 = { .dot_limit = 112000, |
221 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 KP |
222 | }; |
223 | ||
273e27ca | 224 | |
e4b36699 | 225 | static const intel_limit_t intel_limits_g4x_sdvo = { |
273e27ca EA |
226 | .dot = { .min = 25000, .max = 270000 }, |
227 | .vco = { .min = 1750000, .max = 3500000}, | |
228 | .n = { .min = 1, .max = 4 }, | |
229 | .m = { .min = 104, .max = 138 }, | |
230 | .m1 = { .min = 17, .max = 23 }, | |
231 | .m2 = { .min = 5, .max = 11 }, | |
232 | .p = { .min = 10, .max = 30 }, | |
233 | .p1 = { .min = 1, .max = 3}, | |
234 | .p2 = { .dot_limit = 270000, | |
235 | .p2_slow = 10, | |
236 | .p2_fast = 10 | |
044c7c41 | 237 | }, |
e4b36699 KP |
238 | }; |
239 | ||
240 | static const intel_limit_t intel_limits_g4x_hdmi = { | |
273e27ca EA |
241 | .dot = { .min = 22000, .max = 400000 }, |
242 | .vco = { .min = 1750000, .max = 3500000}, | |
243 | .n = { .min = 1, .max = 4 }, | |
244 | .m = { .min = 104, .max = 138 }, | |
245 | .m1 = { .min = 16, .max = 23 }, | |
246 | .m2 = { .min = 5, .max = 11 }, | |
247 | .p = { .min = 5, .max = 80 }, | |
248 | .p1 = { .min = 1, .max = 8}, | |
249 | .p2 = { .dot_limit = 165000, | |
250 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
251 | }; |
252 | ||
253 | static const intel_limit_t intel_limits_g4x_single_channel_lvds = { | |
273e27ca EA |
254 | .dot = { .min = 20000, .max = 115000 }, |
255 | .vco = { .min = 1750000, .max = 3500000 }, | |
256 | .n = { .min = 1, .max = 3 }, | |
257 | .m = { .min = 104, .max = 138 }, | |
258 | .m1 = { .min = 17, .max = 23 }, | |
259 | .m2 = { .min = 5, .max = 11 }, | |
260 | .p = { .min = 28, .max = 112 }, | |
261 | .p1 = { .min = 2, .max = 8 }, | |
262 | .p2 = { .dot_limit = 0, | |
263 | .p2_slow = 14, .p2_fast = 14 | |
044c7c41 | 264 | }, |
e4b36699 KP |
265 | }; |
266 | ||
267 | static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { | |
273e27ca EA |
268 | .dot = { .min = 80000, .max = 224000 }, |
269 | .vco = { .min = 1750000, .max = 3500000 }, | |
270 | .n = { .min = 1, .max = 3 }, | |
271 | .m = { .min = 104, .max = 138 }, | |
272 | .m1 = { .min = 17, .max = 23 }, | |
273 | .m2 = { .min = 5, .max = 11 }, | |
274 | .p = { .min = 14, .max = 42 }, | |
275 | .p1 = { .min = 2, .max = 6 }, | |
276 | .p2 = { .dot_limit = 0, | |
277 | .p2_slow = 7, .p2_fast = 7 | |
044c7c41 | 278 | }, |
e4b36699 KP |
279 | }; |
280 | ||
f2b115e6 | 281 | static const intel_limit_t intel_limits_pineview_sdvo = { |
0206e353 AJ |
282 | .dot = { .min = 20000, .max = 400000}, |
283 | .vco = { .min = 1700000, .max = 3500000 }, | |
273e27ca | 284 | /* Pineview's Ncounter is a ring counter */ |
0206e353 AJ |
285 | .n = { .min = 3, .max = 6 }, |
286 | .m = { .min = 2, .max = 256 }, | |
273e27ca | 287 | /* Pineview only has one combined m divider, which we treat as m2. */ |
0206e353 AJ |
288 | .m1 = { .min = 0, .max = 0 }, |
289 | .m2 = { .min = 0, .max = 254 }, | |
290 | .p = { .min = 5, .max = 80 }, | |
291 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
292 | .p2 = { .dot_limit = 200000, |
293 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
294 | }; |
295 | ||
f2b115e6 | 296 | static const intel_limit_t intel_limits_pineview_lvds = { |
0206e353 AJ |
297 | .dot = { .min = 20000, .max = 400000 }, |
298 | .vco = { .min = 1700000, .max = 3500000 }, | |
299 | .n = { .min = 3, .max = 6 }, | |
300 | .m = { .min = 2, .max = 256 }, | |
301 | .m1 = { .min = 0, .max = 0 }, | |
302 | .m2 = { .min = 0, .max = 254 }, | |
303 | .p = { .min = 7, .max = 112 }, | |
304 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
305 | .p2 = { .dot_limit = 112000, |
306 | .p2_slow = 14, .p2_fast = 14 }, | |
e4b36699 KP |
307 | }; |
308 | ||
273e27ca EA |
309 | /* Ironlake / Sandybridge |
310 | * | |
311 | * We calculate clock using (register_value + 2) for N/M1/M2, so here | |
312 | * the range value for them is (actual_value - 2). | |
313 | */ | |
b91ad0ec | 314 | static const intel_limit_t intel_limits_ironlake_dac = { |
273e27ca EA |
315 | .dot = { .min = 25000, .max = 350000 }, |
316 | .vco = { .min = 1760000, .max = 3510000 }, | |
317 | .n = { .min = 1, .max = 5 }, | |
318 | .m = { .min = 79, .max = 127 }, | |
319 | .m1 = { .min = 12, .max = 22 }, | |
320 | .m2 = { .min = 5, .max = 9 }, | |
321 | .p = { .min = 5, .max = 80 }, | |
322 | .p1 = { .min = 1, .max = 8 }, | |
323 | .p2 = { .dot_limit = 225000, | |
324 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
325 | }; |
326 | ||
b91ad0ec | 327 | static const intel_limit_t intel_limits_ironlake_single_lvds = { |
273e27ca EA |
328 | .dot = { .min = 25000, .max = 350000 }, |
329 | .vco = { .min = 1760000, .max = 3510000 }, | |
330 | .n = { .min = 1, .max = 3 }, | |
331 | .m = { .min = 79, .max = 118 }, | |
332 | .m1 = { .min = 12, .max = 22 }, | |
333 | .m2 = { .min = 5, .max = 9 }, | |
334 | .p = { .min = 28, .max = 112 }, | |
335 | .p1 = { .min = 2, .max = 8 }, | |
336 | .p2 = { .dot_limit = 225000, | |
337 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
338 | }; |
339 | ||
340 | static const intel_limit_t intel_limits_ironlake_dual_lvds = { | |
273e27ca EA |
341 | .dot = { .min = 25000, .max = 350000 }, |
342 | .vco = { .min = 1760000, .max = 3510000 }, | |
343 | .n = { .min = 1, .max = 3 }, | |
344 | .m = { .min = 79, .max = 127 }, | |
345 | .m1 = { .min = 12, .max = 22 }, | |
346 | .m2 = { .min = 5, .max = 9 }, | |
347 | .p = { .min = 14, .max = 56 }, | |
348 | .p1 = { .min = 2, .max = 8 }, | |
349 | .p2 = { .dot_limit = 225000, | |
350 | .p2_slow = 7, .p2_fast = 7 }, | |
b91ad0ec ZW |
351 | }; |
352 | ||
273e27ca | 353 | /* LVDS 100mhz refclk limits. */ |
b91ad0ec | 354 | static const intel_limit_t intel_limits_ironlake_single_lvds_100m = { |
273e27ca EA |
355 | .dot = { .min = 25000, .max = 350000 }, |
356 | .vco = { .min = 1760000, .max = 3510000 }, | |
357 | .n = { .min = 1, .max = 2 }, | |
358 | .m = { .min = 79, .max = 126 }, | |
359 | .m1 = { .min = 12, .max = 22 }, | |
360 | .m2 = { .min = 5, .max = 9 }, | |
361 | .p = { .min = 28, .max = 112 }, | |
0206e353 | 362 | .p1 = { .min = 2, .max = 8 }, |
273e27ca EA |
363 | .p2 = { .dot_limit = 225000, |
364 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
365 | }; |
366 | ||
367 | static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = { | |
273e27ca EA |
368 | .dot = { .min = 25000, .max = 350000 }, |
369 | .vco = { .min = 1760000, .max = 3510000 }, | |
370 | .n = { .min = 1, .max = 3 }, | |
371 | .m = { .min = 79, .max = 126 }, | |
372 | .m1 = { .min = 12, .max = 22 }, | |
373 | .m2 = { .min = 5, .max = 9 }, | |
374 | .p = { .min = 14, .max = 42 }, | |
0206e353 | 375 | .p1 = { .min = 2, .max = 6 }, |
273e27ca EA |
376 | .p2 = { .dot_limit = 225000, |
377 | .p2_slow = 7, .p2_fast = 7 }, | |
4547668a ZY |
378 | }; |
379 | ||
dc730512 | 380 | static const intel_limit_t intel_limits_vlv = { |
f01b7962 VS |
381 | /* |
382 | * These are the data rate limits (measured in fast clocks) | |
383 | * since those are the strictest limits we have. The fast | |
384 | * clock and actual rate limits are more relaxed, so checking | |
385 | * them would make no difference. | |
386 | */ | |
387 | .dot = { .min = 25000 * 5, .max = 270000 * 5 }, | |
75e53986 | 388 | .vco = { .min = 4000000, .max = 6000000 }, |
a0c4da24 | 389 | .n = { .min = 1, .max = 7 }, |
a0c4da24 JB |
390 | .m1 = { .min = 2, .max = 3 }, |
391 | .m2 = { .min = 11, .max = 156 }, | |
b99ab663 | 392 | .p1 = { .min = 2, .max = 3 }, |
5fdc9c49 | 393 | .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */ |
a0c4da24 JB |
394 | }; |
395 | ||
ef9348c8 CML |
396 | static const intel_limit_t intel_limits_chv = { |
397 | /* | |
398 | * These are the data rate limits (measured in fast clocks) | |
399 | * since those are the strictest limits we have. The fast | |
400 | * clock and actual rate limits are more relaxed, so checking | |
401 | * them would make no difference. | |
402 | */ | |
403 | .dot = { .min = 25000 * 5, .max = 540000 * 5}, | |
17fe1021 | 404 | .vco = { .min = 4800000, .max = 6480000 }, |
ef9348c8 CML |
405 | .n = { .min = 1, .max = 1 }, |
406 | .m1 = { .min = 2, .max = 2 }, | |
407 | .m2 = { .min = 24 << 22, .max = 175 << 22 }, | |
408 | .p1 = { .min = 2, .max = 4 }, | |
409 | .p2 = { .p2_slow = 1, .p2_fast = 14 }, | |
410 | }; | |
411 | ||
5ab7b0b7 ID |
412 | static const intel_limit_t intel_limits_bxt = { |
413 | /* FIXME: find real dot limits */ | |
414 | .dot = { .min = 0, .max = INT_MAX }, | |
415 | .vco = { .min = 4800000, .max = 6480000 }, | |
416 | .n = { .min = 1, .max = 1 }, | |
417 | .m1 = { .min = 2, .max = 2 }, | |
418 | /* FIXME: find real m2 limits */ | |
419 | .m2 = { .min = 2 << 22, .max = 255 << 22 }, | |
420 | .p1 = { .min = 2, .max = 4 }, | |
421 | .p2 = { .p2_slow = 1, .p2_fast = 20 }, | |
422 | }; | |
423 | ||
6b4bf1c4 VS |
424 | static void vlv_clock(int refclk, intel_clock_t *clock) |
425 | { | |
426 | clock->m = clock->m1 * clock->m2; | |
427 | clock->p = clock->p1 * clock->p2; | |
ed5ca77e VS |
428 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
429 | return; | |
fb03ac01 VS |
430 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
431 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
6b4bf1c4 VS |
432 | } |
433 | ||
e0638cdf PZ |
434 | /** |
435 | * Returns whether any output on the specified pipe is of the specified type | |
436 | */ | |
4093561b | 437 | bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type) |
e0638cdf | 438 | { |
409ee761 | 439 | struct drm_device *dev = crtc->base.dev; |
e0638cdf PZ |
440 | struct intel_encoder *encoder; |
441 | ||
409ee761 | 442 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) |
e0638cdf PZ |
443 | if (encoder->type == type) |
444 | return true; | |
445 | ||
446 | return false; | |
447 | } | |
448 | ||
d0737e1d ACO |
449 | /** |
450 | * Returns whether any output on the specified pipe will have the specified | |
451 | * type after a staged modeset is complete, i.e., the same as | |
452 | * intel_pipe_has_type() but looking at encoder->new_crtc instead of | |
453 | * encoder->crtc. | |
454 | */ | |
a93e255f ACO |
455 | static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state, |
456 | int type) | |
d0737e1d | 457 | { |
a93e255f | 458 | struct drm_atomic_state *state = crtc_state->base.state; |
da3ced29 | 459 | struct drm_connector *connector; |
a93e255f | 460 | struct drm_connector_state *connector_state; |
d0737e1d | 461 | struct intel_encoder *encoder; |
a93e255f ACO |
462 | int i, num_connectors = 0; |
463 | ||
da3ced29 | 464 | for_each_connector_in_state(state, connector, connector_state, i) { |
a93e255f ACO |
465 | if (connector_state->crtc != crtc_state->base.crtc) |
466 | continue; | |
467 | ||
468 | num_connectors++; | |
d0737e1d | 469 | |
a93e255f ACO |
470 | encoder = to_intel_encoder(connector_state->best_encoder); |
471 | if (encoder->type == type) | |
d0737e1d | 472 | return true; |
a93e255f ACO |
473 | } |
474 | ||
475 | WARN_ON(num_connectors == 0); | |
d0737e1d ACO |
476 | |
477 | return false; | |
478 | } | |
479 | ||
a93e255f ACO |
480 | static const intel_limit_t * |
481 | intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk) | |
2c07245f | 482 | { |
a93e255f | 483 | struct drm_device *dev = crtc_state->base.crtc->dev; |
2c07245f | 484 | const intel_limit_t *limit; |
b91ad0ec | 485 | |
a93e255f | 486 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
1974cad0 | 487 | if (intel_is_dual_link_lvds(dev)) { |
1b894b59 | 488 | if (refclk == 100000) |
b91ad0ec ZW |
489 | limit = &intel_limits_ironlake_dual_lvds_100m; |
490 | else | |
491 | limit = &intel_limits_ironlake_dual_lvds; | |
492 | } else { | |
1b894b59 | 493 | if (refclk == 100000) |
b91ad0ec ZW |
494 | limit = &intel_limits_ironlake_single_lvds_100m; |
495 | else | |
496 | limit = &intel_limits_ironlake_single_lvds; | |
497 | } | |
c6bb3538 | 498 | } else |
b91ad0ec | 499 | limit = &intel_limits_ironlake_dac; |
2c07245f ZW |
500 | |
501 | return limit; | |
502 | } | |
503 | ||
a93e255f ACO |
504 | static const intel_limit_t * |
505 | intel_g4x_limit(struct intel_crtc_state *crtc_state) | |
044c7c41 | 506 | { |
a93e255f | 507 | struct drm_device *dev = crtc_state->base.crtc->dev; |
044c7c41 ML |
508 | const intel_limit_t *limit; |
509 | ||
a93e255f | 510 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
1974cad0 | 511 | if (intel_is_dual_link_lvds(dev)) |
e4b36699 | 512 | limit = &intel_limits_g4x_dual_channel_lvds; |
044c7c41 | 513 | else |
e4b36699 | 514 | limit = &intel_limits_g4x_single_channel_lvds; |
a93e255f ACO |
515 | } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) || |
516 | intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) { | |
e4b36699 | 517 | limit = &intel_limits_g4x_hdmi; |
a93e255f | 518 | } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) { |
e4b36699 | 519 | limit = &intel_limits_g4x_sdvo; |
044c7c41 | 520 | } else /* The option is for other outputs */ |
e4b36699 | 521 | limit = &intel_limits_i9xx_sdvo; |
044c7c41 ML |
522 | |
523 | return limit; | |
524 | } | |
525 | ||
a93e255f ACO |
526 | static const intel_limit_t * |
527 | intel_limit(struct intel_crtc_state *crtc_state, int refclk) | |
79e53945 | 528 | { |
a93e255f | 529 | struct drm_device *dev = crtc_state->base.crtc->dev; |
79e53945 JB |
530 | const intel_limit_t *limit; |
531 | ||
5ab7b0b7 ID |
532 | if (IS_BROXTON(dev)) |
533 | limit = &intel_limits_bxt; | |
534 | else if (HAS_PCH_SPLIT(dev)) | |
a93e255f | 535 | limit = intel_ironlake_limit(crtc_state, refclk); |
2c07245f | 536 | else if (IS_G4X(dev)) { |
a93e255f | 537 | limit = intel_g4x_limit(crtc_state); |
f2b115e6 | 538 | } else if (IS_PINEVIEW(dev)) { |
a93e255f | 539 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
f2b115e6 | 540 | limit = &intel_limits_pineview_lvds; |
2177832f | 541 | else |
f2b115e6 | 542 | limit = &intel_limits_pineview_sdvo; |
ef9348c8 CML |
543 | } else if (IS_CHERRYVIEW(dev)) { |
544 | limit = &intel_limits_chv; | |
a0c4da24 | 545 | } else if (IS_VALLEYVIEW(dev)) { |
dc730512 | 546 | limit = &intel_limits_vlv; |
a6c45cf0 | 547 | } else if (!IS_GEN2(dev)) { |
a93e255f | 548 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
a6c45cf0 CW |
549 | limit = &intel_limits_i9xx_lvds; |
550 | else | |
551 | limit = &intel_limits_i9xx_sdvo; | |
79e53945 | 552 | } else { |
a93e255f | 553 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
e4b36699 | 554 | limit = &intel_limits_i8xx_lvds; |
a93e255f | 555 | else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO)) |
e4b36699 | 556 | limit = &intel_limits_i8xx_dvo; |
5d536e28 DV |
557 | else |
558 | limit = &intel_limits_i8xx_dac; | |
79e53945 JB |
559 | } |
560 | return limit; | |
561 | } | |
562 | ||
f2b115e6 AJ |
563 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
564 | static void pineview_clock(int refclk, intel_clock_t *clock) | |
79e53945 | 565 | { |
2177832f SL |
566 | clock->m = clock->m2 + 2; |
567 | clock->p = clock->p1 * clock->p2; | |
ed5ca77e VS |
568 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
569 | return; | |
fb03ac01 VS |
570 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
571 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
2177832f SL |
572 | } |
573 | ||
7429e9d4 DV |
574 | static uint32_t i9xx_dpll_compute_m(struct dpll *dpll) |
575 | { | |
576 | return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); | |
577 | } | |
578 | ||
ac58c3f0 | 579 | static void i9xx_clock(int refclk, intel_clock_t *clock) |
2177832f | 580 | { |
7429e9d4 | 581 | clock->m = i9xx_dpll_compute_m(clock); |
79e53945 | 582 | clock->p = clock->p1 * clock->p2; |
ed5ca77e VS |
583 | if (WARN_ON(clock->n + 2 == 0 || clock->p == 0)) |
584 | return; | |
fb03ac01 VS |
585 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2); |
586 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
79e53945 JB |
587 | } |
588 | ||
ef9348c8 CML |
589 | static void chv_clock(int refclk, intel_clock_t *clock) |
590 | { | |
591 | clock->m = clock->m1 * clock->m2; | |
592 | clock->p = clock->p1 * clock->p2; | |
593 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
594 | return; | |
595 | clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m, | |
596 | clock->n << 22); | |
597 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
598 | } | |
599 | ||
7c04d1d9 | 600 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
79e53945 JB |
601 | /** |
602 | * Returns whether the given set of divisors are valid for a given refclk with | |
603 | * the given connectors. | |
604 | */ | |
605 | ||
1b894b59 CW |
606 | static bool intel_PLL_is_valid(struct drm_device *dev, |
607 | const intel_limit_t *limit, | |
608 | const intel_clock_t *clock) | |
79e53945 | 609 | { |
f01b7962 VS |
610 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
611 | INTELPllInvalid("n out of range\n"); | |
79e53945 | 612 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
0206e353 | 613 | INTELPllInvalid("p1 out of range\n"); |
79e53945 | 614 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
0206e353 | 615 | INTELPllInvalid("m2 out of range\n"); |
79e53945 | 616 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
0206e353 | 617 | INTELPllInvalid("m1 out of range\n"); |
f01b7962 | 618 | |
5ab7b0b7 | 619 | if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) |
f01b7962 VS |
620 | if (clock->m1 <= clock->m2) |
621 | INTELPllInvalid("m1 <= m2\n"); | |
622 | ||
5ab7b0b7 | 623 | if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) { |
f01b7962 VS |
624 | if (clock->p < limit->p.min || limit->p.max < clock->p) |
625 | INTELPllInvalid("p out of range\n"); | |
626 | if (clock->m < limit->m.min || limit->m.max < clock->m) | |
627 | INTELPllInvalid("m out of range\n"); | |
628 | } | |
629 | ||
79e53945 | 630 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
0206e353 | 631 | INTELPllInvalid("vco out of range\n"); |
79e53945 JB |
632 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
633 | * connector, etc., rather than just a single range. | |
634 | */ | |
635 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) | |
0206e353 | 636 | INTELPllInvalid("dot out of range\n"); |
79e53945 JB |
637 | |
638 | return true; | |
639 | } | |
640 | ||
d4906093 | 641 | static bool |
a93e255f ACO |
642 | i9xx_find_best_dpll(const intel_limit_t *limit, |
643 | struct intel_crtc_state *crtc_state, | |
cec2f356 SP |
644 | int target, int refclk, intel_clock_t *match_clock, |
645 | intel_clock_t *best_clock) | |
79e53945 | 646 | { |
a93e255f | 647 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 648 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 649 | intel_clock_t clock; |
79e53945 JB |
650 | int err = target; |
651 | ||
a93e255f | 652 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
79e53945 | 653 | /* |
a210b028 DV |
654 | * For LVDS just rely on its current settings for dual-channel. |
655 | * We haven't figured out how to reliably set up different | |
656 | * single/dual channel state, if we even can. | |
79e53945 | 657 | */ |
1974cad0 | 658 | if (intel_is_dual_link_lvds(dev)) |
79e53945 JB |
659 | clock.p2 = limit->p2.p2_fast; |
660 | else | |
661 | clock.p2 = limit->p2.p2_slow; | |
662 | } else { | |
663 | if (target < limit->p2.dot_limit) | |
664 | clock.p2 = limit->p2.p2_slow; | |
665 | else | |
666 | clock.p2 = limit->p2.p2_fast; | |
667 | } | |
668 | ||
0206e353 | 669 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 670 | |
42158660 ZY |
671 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
672 | clock.m1++) { | |
673 | for (clock.m2 = limit->m2.min; | |
674 | clock.m2 <= limit->m2.max; clock.m2++) { | |
c0efc387 | 675 | if (clock.m2 >= clock.m1) |
42158660 ZY |
676 | break; |
677 | for (clock.n = limit->n.min; | |
678 | clock.n <= limit->n.max; clock.n++) { | |
679 | for (clock.p1 = limit->p1.min; | |
680 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
681 | int this_err; |
682 | ||
ac58c3f0 DV |
683 | i9xx_clock(refclk, &clock); |
684 | if (!intel_PLL_is_valid(dev, limit, | |
685 | &clock)) | |
686 | continue; | |
687 | if (match_clock && | |
688 | clock.p != match_clock->p) | |
689 | continue; | |
690 | ||
691 | this_err = abs(clock.dot - target); | |
692 | if (this_err < err) { | |
693 | *best_clock = clock; | |
694 | err = this_err; | |
695 | } | |
696 | } | |
697 | } | |
698 | } | |
699 | } | |
700 | ||
701 | return (err != target); | |
702 | } | |
703 | ||
704 | static bool | |
a93e255f ACO |
705 | pnv_find_best_dpll(const intel_limit_t *limit, |
706 | struct intel_crtc_state *crtc_state, | |
ee9300bb DV |
707 | int target, int refclk, intel_clock_t *match_clock, |
708 | intel_clock_t *best_clock) | |
79e53945 | 709 | { |
a93e255f | 710 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 711 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 712 | intel_clock_t clock; |
79e53945 JB |
713 | int err = target; |
714 | ||
a93e255f | 715 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
79e53945 | 716 | /* |
a210b028 DV |
717 | * For LVDS just rely on its current settings for dual-channel. |
718 | * We haven't figured out how to reliably set up different | |
719 | * single/dual channel state, if we even can. | |
79e53945 | 720 | */ |
1974cad0 | 721 | if (intel_is_dual_link_lvds(dev)) |
79e53945 JB |
722 | clock.p2 = limit->p2.p2_fast; |
723 | else | |
724 | clock.p2 = limit->p2.p2_slow; | |
725 | } else { | |
726 | if (target < limit->p2.dot_limit) | |
727 | clock.p2 = limit->p2.p2_slow; | |
728 | else | |
729 | clock.p2 = limit->p2.p2_fast; | |
730 | } | |
731 | ||
0206e353 | 732 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 733 | |
42158660 ZY |
734 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
735 | clock.m1++) { | |
736 | for (clock.m2 = limit->m2.min; | |
737 | clock.m2 <= limit->m2.max; clock.m2++) { | |
42158660 ZY |
738 | for (clock.n = limit->n.min; |
739 | clock.n <= limit->n.max; clock.n++) { | |
740 | for (clock.p1 = limit->p1.min; | |
741 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
742 | int this_err; |
743 | ||
ac58c3f0 | 744 | pineview_clock(refclk, &clock); |
1b894b59 CW |
745 | if (!intel_PLL_is_valid(dev, limit, |
746 | &clock)) | |
79e53945 | 747 | continue; |
cec2f356 SP |
748 | if (match_clock && |
749 | clock.p != match_clock->p) | |
750 | continue; | |
79e53945 JB |
751 | |
752 | this_err = abs(clock.dot - target); | |
753 | if (this_err < err) { | |
754 | *best_clock = clock; | |
755 | err = this_err; | |
756 | } | |
757 | } | |
758 | } | |
759 | } | |
760 | } | |
761 | ||
762 | return (err != target); | |
763 | } | |
764 | ||
d4906093 | 765 | static bool |
a93e255f ACO |
766 | g4x_find_best_dpll(const intel_limit_t *limit, |
767 | struct intel_crtc_state *crtc_state, | |
ee9300bb DV |
768 | int target, int refclk, intel_clock_t *match_clock, |
769 | intel_clock_t *best_clock) | |
d4906093 | 770 | { |
a93e255f | 771 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 772 | struct drm_device *dev = crtc->base.dev; |
d4906093 ML |
773 | intel_clock_t clock; |
774 | int max_n; | |
775 | bool found; | |
6ba770dc AJ |
776 | /* approximately equals target * 0.00585 */ |
777 | int err_most = (target >> 8) + (target >> 9); | |
d4906093 ML |
778 | found = false; |
779 | ||
a93e255f | 780 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
1974cad0 | 781 | if (intel_is_dual_link_lvds(dev)) |
d4906093 ML |
782 | clock.p2 = limit->p2.p2_fast; |
783 | else | |
784 | clock.p2 = limit->p2.p2_slow; | |
785 | } else { | |
786 | if (target < limit->p2.dot_limit) | |
787 | clock.p2 = limit->p2.p2_slow; | |
788 | else | |
789 | clock.p2 = limit->p2.p2_fast; | |
790 | } | |
791 | ||
792 | memset(best_clock, 0, sizeof(*best_clock)); | |
793 | max_n = limit->n.max; | |
f77f13e2 | 794 | /* based on hardware requirement, prefer smaller n to precision */ |
d4906093 | 795 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
f77f13e2 | 796 | /* based on hardware requirement, prefere larger m1,m2 */ |
d4906093 ML |
797 | for (clock.m1 = limit->m1.max; |
798 | clock.m1 >= limit->m1.min; clock.m1--) { | |
799 | for (clock.m2 = limit->m2.max; | |
800 | clock.m2 >= limit->m2.min; clock.m2--) { | |
801 | for (clock.p1 = limit->p1.max; | |
802 | clock.p1 >= limit->p1.min; clock.p1--) { | |
803 | int this_err; | |
804 | ||
ac58c3f0 | 805 | i9xx_clock(refclk, &clock); |
1b894b59 CW |
806 | if (!intel_PLL_is_valid(dev, limit, |
807 | &clock)) | |
d4906093 | 808 | continue; |
1b894b59 CW |
809 | |
810 | this_err = abs(clock.dot - target); | |
d4906093 ML |
811 | if (this_err < err_most) { |
812 | *best_clock = clock; | |
813 | err_most = this_err; | |
814 | max_n = clock.n; | |
815 | found = true; | |
816 | } | |
817 | } | |
818 | } | |
819 | } | |
820 | } | |
2c07245f ZW |
821 | return found; |
822 | } | |
823 | ||
d5dd62bd ID |
824 | /* |
825 | * Check if the calculated PLL configuration is more optimal compared to the | |
826 | * best configuration and error found so far. Return the calculated error. | |
827 | */ | |
828 | static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq, | |
829 | const intel_clock_t *calculated_clock, | |
830 | const intel_clock_t *best_clock, | |
831 | unsigned int best_error_ppm, | |
832 | unsigned int *error_ppm) | |
833 | { | |
9ca3ba01 ID |
834 | /* |
835 | * For CHV ignore the error and consider only the P value. | |
836 | * Prefer a bigger P value based on HW requirements. | |
837 | */ | |
838 | if (IS_CHERRYVIEW(dev)) { | |
839 | *error_ppm = 0; | |
840 | ||
841 | return calculated_clock->p > best_clock->p; | |
842 | } | |
843 | ||
24be4e46 ID |
844 | if (WARN_ON_ONCE(!target_freq)) |
845 | return false; | |
846 | ||
d5dd62bd ID |
847 | *error_ppm = div_u64(1000000ULL * |
848 | abs(target_freq - calculated_clock->dot), | |
849 | target_freq); | |
850 | /* | |
851 | * Prefer a better P value over a better (smaller) error if the error | |
852 | * is small. Ensure this preference for future configurations too by | |
853 | * setting the error to 0. | |
854 | */ | |
855 | if (*error_ppm < 100 && calculated_clock->p > best_clock->p) { | |
856 | *error_ppm = 0; | |
857 | ||
858 | return true; | |
859 | } | |
860 | ||
861 | return *error_ppm + 10 < best_error_ppm; | |
862 | } | |
863 | ||
a0c4da24 | 864 | static bool |
a93e255f ACO |
865 | vlv_find_best_dpll(const intel_limit_t *limit, |
866 | struct intel_crtc_state *crtc_state, | |
ee9300bb DV |
867 | int target, int refclk, intel_clock_t *match_clock, |
868 | intel_clock_t *best_clock) | |
a0c4da24 | 869 | { |
a93e255f | 870 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 871 | struct drm_device *dev = crtc->base.dev; |
6b4bf1c4 | 872 | intel_clock_t clock; |
69e4f900 | 873 | unsigned int bestppm = 1000000; |
27e639bf VS |
874 | /* min update 19.2 MHz */ |
875 | int max_n = min(limit->n.max, refclk / 19200); | |
49e497ef | 876 | bool found = false; |
a0c4da24 | 877 | |
6b4bf1c4 VS |
878 | target *= 5; /* fast clock */ |
879 | ||
880 | memset(best_clock, 0, sizeof(*best_clock)); | |
a0c4da24 JB |
881 | |
882 | /* based on hardware requirement, prefer smaller n to precision */ | |
27e639bf | 883 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
811bbf05 | 884 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { |
889059d8 | 885 | for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow; |
c1a9ae43 | 886 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { |
6b4bf1c4 | 887 | clock.p = clock.p1 * clock.p2; |
a0c4da24 | 888 | /* based on hardware requirement, prefer bigger m1,m2 values */ |
6b4bf1c4 | 889 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { |
d5dd62bd | 890 | unsigned int ppm; |
69e4f900 | 891 | |
6b4bf1c4 VS |
892 | clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n, |
893 | refclk * clock.m1); | |
894 | ||
895 | vlv_clock(refclk, &clock); | |
43b0ac53 | 896 | |
f01b7962 VS |
897 | if (!intel_PLL_is_valid(dev, limit, |
898 | &clock)) | |
43b0ac53 VS |
899 | continue; |
900 | ||
d5dd62bd ID |
901 | if (!vlv_PLL_is_optimal(dev, target, |
902 | &clock, | |
903 | best_clock, | |
904 | bestppm, &ppm)) | |
905 | continue; | |
6b4bf1c4 | 906 | |
d5dd62bd ID |
907 | *best_clock = clock; |
908 | bestppm = ppm; | |
909 | found = true; | |
a0c4da24 JB |
910 | } |
911 | } | |
912 | } | |
913 | } | |
a0c4da24 | 914 | |
49e497ef | 915 | return found; |
a0c4da24 | 916 | } |
a4fc5ed6 | 917 | |
ef9348c8 | 918 | static bool |
a93e255f ACO |
919 | chv_find_best_dpll(const intel_limit_t *limit, |
920 | struct intel_crtc_state *crtc_state, | |
ef9348c8 CML |
921 | int target, int refclk, intel_clock_t *match_clock, |
922 | intel_clock_t *best_clock) | |
923 | { | |
a93e255f | 924 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 925 | struct drm_device *dev = crtc->base.dev; |
9ca3ba01 | 926 | unsigned int best_error_ppm; |
ef9348c8 CML |
927 | intel_clock_t clock; |
928 | uint64_t m2; | |
929 | int found = false; | |
930 | ||
931 | memset(best_clock, 0, sizeof(*best_clock)); | |
9ca3ba01 | 932 | best_error_ppm = 1000000; |
ef9348c8 CML |
933 | |
934 | /* | |
935 | * Based on hardware doc, the n always set to 1, and m1 always | |
936 | * set to 2. If requires to support 200Mhz refclk, we need to | |
937 | * revisit this because n may not 1 anymore. | |
938 | */ | |
939 | clock.n = 1, clock.m1 = 2; | |
940 | target *= 5; /* fast clock */ | |
941 | ||
942 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { | |
943 | for (clock.p2 = limit->p2.p2_fast; | |
944 | clock.p2 >= limit->p2.p2_slow; | |
945 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { | |
9ca3ba01 | 946 | unsigned int error_ppm; |
ef9348c8 CML |
947 | |
948 | clock.p = clock.p1 * clock.p2; | |
949 | ||
950 | m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p * | |
951 | clock.n) << 22, refclk * clock.m1); | |
952 | ||
953 | if (m2 > INT_MAX/clock.m1) | |
954 | continue; | |
955 | ||
956 | clock.m2 = m2; | |
957 | ||
958 | chv_clock(refclk, &clock); | |
959 | ||
960 | if (!intel_PLL_is_valid(dev, limit, &clock)) | |
961 | continue; | |
962 | ||
9ca3ba01 ID |
963 | if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock, |
964 | best_error_ppm, &error_ppm)) | |
965 | continue; | |
966 | ||
967 | *best_clock = clock; | |
968 | best_error_ppm = error_ppm; | |
969 | found = true; | |
ef9348c8 CML |
970 | } |
971 | } | |
972 | ||
973 | return found; | |
974 | } | |
975 | ||
5ab7b0b7 ID |
976 | bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock, |
977 | intel_clock_t *best_clock) | |
978 | { | |
979 | int refclk = i9xx_get_refclk(crtc_state, 0); | |
980 | ||
981 | return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state, | |
982 | target_clock, refclk, NULL, best_clock); | |
983 | } | |
984 | ||
20ddf665 VS |
985 | bool intel_crtc_active(struct drm_crtc *crtc) |
986 | { | |
987 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
988 | ||
989 | /* Be paranoid as we can arrive here with only partial | |
990 | * state retrieved from the hardware during setup. | |
991 | * | |
241bfc38 | 992 | * We can ditch the adjusted_mode.crtc_clock check as soon |
20ddf665 VS |
993 | * as Haswell has gained clock readout/fastboot support. |
994 | * | |
66e514c1 | 995 | * We can ditch the crtc->primary->fb check as soon as we can |
20ddf665 | 996 | * properly reconstruct framebuffers. |
c3d1f436 MR |
997 | * |
998 | * FIXME: The intel_crtc->active here should be switched to | |
999 | * crtc->state->active once we have proper CRTC states wired up | |
1000 | * for atomic. | |
20ddf665 | 1001 | */ |
c3d1f436 | 1002 | return intel_crtc->active && crtc->primary->state->fb && |
6e3c9717 | 1003 | intel_crtc->config->base.adjusted_mode.crtc_clock; |
20ddf665 VS |
1004 | } |
1005 | ||
a5c961d1 PZ |
1006 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
1007 | enum pipe pipe) | |
1008 | { | |
1009 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
1010 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1011 | ||
6e3c9717 | 1012 | return intel_crtc->config->cpu_transcoder; |
a5c961d1 PZ |
1013 | } |
1014 | ||
fbf49ea2 VS |
1015 | static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe) |
1016 | { | |
1017 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1018 | u32 reg = PIPEDSL(pipe); | |
1019 | u32 line1, line2; | |
1020 | u32 line_mask; | |
1021 | ||
1022 | if (IS_GEN2(dev)) | |
1023 | line_mask = DSL_LINEMASK_GEN2; | |
1024 | else | |
1025 | line_mask = DSL_LINEMASK_GEN3; | |
1026 | ||
1027 | line1 = I915_READ(reg) & line_mask; | |
1028 | mdelay(5); | |
1029 | line2 = I915_READ(reg) & line_mask; | |
1030 | ||
1031 | return line1 == line2; | |
1032 | } | |
1033 | ||
ab7ad7f6 KP |
1034 | /* |
1035 | * intel_wait_for_pipe_off - wait for pipe to turn off | |
575f7ab7 | 1036 | * @crtc: crtc whose pipe to wait for |
9d0498a2 JB |
1037 | * |
1038 | * After disabling a pipe, we can't wait for vblank in the usual way, | |
1039 | * spinning on the vblank interrupt status bit, since we won't actually | |
1040 | * see an interrupt when the pipe is disabled. | |
1041 | * | |
ab7ad7f6 KP |
1042 | * On Gen4 and above: |
1043 | * wait for the pipe register state bit to turn off | |
1044 | * | |
1045 | * Otherwise: | |
1046 | * wait for the display line value to settle (it usually | |
1047 | * ends up stopping at the start of the next frame). | |
58e10eb9 | 1048 | * |
9d0498a2 | 1049 | */ |
575f7ab7 | 1050 | static void intel_wait_for_pipe_off(struct intel_crtc *crtc) |
9d0498a2 | 1051 | { |
575f7ab7 | 1052 | struct drm_device *dev = crtc->base.dev; |
9d0498a2 | 1053 | struct drm_i915_private *dev_priv = dev->dev_private; |
6e3c9717 | 1054 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 1055 | enum pipe pipe = crtc->pipe; |
ab7ad7f6 KP |
1056 | |
1057 | if (INTEL_INFO(dev)->gen >= 4) { | |
702e7a56 | 1058 | int reg = PIPECONF(cpu_transcoder); |
ab7ad7f6 KP |
1059 | |
1060 | /* Wait for the Pipe State to go off */ | |
58e10eb9 CW |
1061 | if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, |
1062 | 100)) | |
284637d9 | 1063 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1064 | } else { |
ab7ad7f6 | 1065 | /* Wait for the display line to settle */ |
fbf49ea2 | 1066 | if (wait_for(pipe_dsl_stopped(dev, pipe), 100)) |
284637d9 | 1067 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1068 | } |
79e53945 JB |
1069 | } |
1070 | ||
b0ea7d37 DL |
1071 | /* |
1072 | * ibx_digital_port_connected - is the specified port connected? | |
1073 | * @dev_priv: i915 private structure | |
1074 | * @port: the port to test | |
1075 | * | |
1076 | * Returns true if @port is connected, false otherwise. | |
1077 | */ | |
1078 | bool ibx_digital_port_connected(struct drm_i915_private *dev_priv, | |
1079 | struct intel_digital_port *port) | |
1080 | { | |
1081 | u32 bit; | |
1082 | ||
c36346e3 | 1083 | if (HAS_PCH_IBX(dev_priv->dev)) { |
eba905b2 | 1084 | switch (port->port) { |
c36346e3 DL |
1085 | case PORT_B: |
1086 | bit = SDE_PORTB_HOTPLUG; | |
1087 | break; | |
1088 | case PORT_C: | |
1089 | bit = SDE_PORTC_HOTPLUG; | |
1090 | break; | |
1091 | case PORT_D: | |
1092 | bit = SDE_PORTD_HOTPLUG; | |
1093 | break; | |
1094 | default: | |
1095 | return true; | |
1096 | } | |
1097 | } else { | |
eba905b2 | 1098 | switch (port->port) { |
c36346e3 DL |
1099 | case PORT_B: |
1100 | bit = SDE_PORTB_HOTPLUG_CPT; | |
1101 | break; | |
1102 | case PORT_C: | |
1103 | bit = SDE_PORTC_HOTPLUG_CPT; | |
1104 | break; | |
1105 | case PORT_D: | |
1106 | bit = SDE_PORTD_HOTPLUG_CPT; | |
1107 | break; | |
1108 | default: | |
1109 | return true; | |
1110 | } | |
b0ea7d37 DL |
1111 | } |
1112 | ||
1113 | return I915_READ(SDEISR) & bit; | |
1114 | } | |
1115 | ||
b24e7179 JB |
1116 | static const char *state_string(bool enabled) |
1117 | { | |
1118 | return enabled ? "on" : "off"; | |
1119 | } | |
1120 | ||
1121 | /* Only for pre-ILK configs */ | |
55607e8a DV |
1122 | void assert_pll(struct drm_i915_private *dev_priv, |
1123 | enum pipe pipe, bool state) | |
b24e7179 JB |
1124 | { |
1125 | int reg; | |
1126 | u32 val; | |
1127 | bool cur_state; | |
1128 | ||
1129 | reg = DPLL(pipe); | |
1130 | val = I915_READ(reg); | |
1131 | cur_state = !!(val & DPLL_VCO_ENABLE); | |
e2c719b7 | 1132 | I915_STATE_WARN(cur_state != state, |
b24e7179 JB |
1133 | "PLL state assertion failure (expected %s, current %s)\n", |
1134 | state_string(state), state_string(cur_state)); | |
1135 | } | |
b24e7179 | 1136 | |
23538ef1 JN |
1137 | /* XXX: the dsi pll is shared between MIPI DSI ports */ |
1138 | static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state) | |
1139 | { | |
1140 | u32 val; | |
1141 | bool cur_state; | |
1142 | ||
a580516d | 1143 | mutex_lock(&dev_priv->sb_lock); |
23538ef1 | 1144 | val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); |
a580516d | 1145 | mutex_unlock(&dev_priv->sb_lock); |
23538ef1 JN |
1146 | |
1147 | cur_state = val & DSI_PLL_VCO_EN; | |
e2c719b7 | 1148 | I915_STATE_WARN(cur_state != state, |
23538ef1 JN |
1149 | "DSI PLL state assertion failure (expected %s, current %s)\n", |
1150 | state_string(state), state_string(cur_state)); | |
1151 | } | |
1152 | #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true) | |
1153 | #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false) | |
1154 | ||
55607e8a | 1155 | struct intel_shared_dpll * |
e2b78267 DV |
1156 | intel_crtc_to_shared_dpll(struct intel_crtc *crtc) |
1157 | { | |
1158 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
1159 | ||
6e3c9717 | 1160 | if (crtc->config->shared_dpll < 0) |
e2b78267 DV |
1161 | return NULL; |
1162 | ||
6e3c9717 | 1163 | return &dev_priv->shared_dplls[crtc->config->shared_dpll]; |
e2b78267 DV |
1164 | } |
1165 | ||
040484af | 1166 | /* For ILK+ */ |
55607e8a DV |
1167 | void assert_shared_dpll(struct drm_i915_private *dev_priv, |
1168 | struct intel_shared_dpll *pll, | |
1169 | bool state) | |
040484af | 1170 | { |
040484af | 1171 | bool cur_state; |
5358901f | 1172 | struct intel_dpll_hw_state hw_state; |
040484af | 1173 | |
92b27b08 | 1174 | if (WARN (!pll, |
46edb027 | 1175 | "asserting DPLL %s with no DPLL\n", state_string(state))) |
ee7b9f93 | 1176 | return; |
ee7b9f93 | 1177 | |
5358901f | 1178 | cur_state = pll->get_hw_state(dev_priv, pll, &hw_state); |
e2c719b7 | 1179 | I915_STATE_WARN(cur_state != state, |
5358901f DV |
1180 | "%s assertion failure (expected %s, current %s)\n", |
1181 | pll->name, state_string(state), state_string(cur_state)); | |
040484af | 1182 | } |
040484af JB |
1183 | |
1184 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, | |
1185 | enum pipe pipe, bool state) | |
1186 | { | |
1187 | int reg; | |
1188 | u32 val; | |
1189 | bool cur_state; | |
ad80a810 PZ |
1190 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1191 | pipe); | |
040484af | 1192 | |
affa9354 PZ |
1193 | if (HAS_DDI(dev_priv->dev)) { |
1194 | /* DDI does not have a specific FDI_TX register */ | |
ad80a810 | 1195 | reg = TRANS_DDI_FUNC_CTL(cpu_transcoder); |
bf507ef7 | 1196 | val = I915_READ(reg); |
ad80a810 | 1197 | cur_state = !!(val & TRANS_DDI_FUNC_ENABLE); |
bf507ef7 ED |
1198 | } else { |
1199 | reg = FDI_TX_CTL(pipe); | |
1200 | val = I915_READ(reg); | |
1201 | cur_state = !!(val & FDI_TX_ENABLE); | |
1202 | } | |
e2c719b7 | 1203 | I915_STATE_WARN(cur_state != state, |
040484af JB |
1204 | "FDI TX state assertion failure (expected %s, current %s)\n", |
1205 | state_string(state), state_string(cur_state)); | |
1206 | } | |
1207 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) | |
1208 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) | |
1209 | ||
1210 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, | |
1211 | enum pipe pipe, bool state) | |
1212 | { | |
1213 | int reg; | |
1214 | u32 val; | |
1215 | bool cur_state; | |
1216 | ||
d63fa0dc PZ |
1217 | reg = FDI_RX_CTL(pipe); |
1218 | val = I915_READ(reg); | |
1219 | cur_state = !!(val & FDI_RX_ENABLE); | |
e2c719b7 | 1220 | I915_STATE_WARN(cur_state != state, |
040484af JB |
1221 | "FDI RX state assertion failure (expected %s, current %s)\n", |
1222 | state_string(state), state_string(cur_state)); | |
1223 | } | |
1224 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) | |
1225 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) | |
1226 | ||
1227 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, | |
1228 | enum pipe pipe) | |
1229 | { | |
1230 | int reg; | |
1231 | u32 val; | |
1232 | ||
1233 | /* ILK FDI PLL is always enabled */ | |
3d13ef2e | 1234 | if (INTEL_INFO(dev_priv->dev)->gen == 5) |
040484af JB |
1235 | return; |
1236 | ||
bf507ef7 | 1237 | /* On Haswell, DDI ports are responsible for the FDI PLL setup */ |
affa9354 | 1238 | if (HAS_DDI(dev_priv->dev)) |
bf507ef7 ED |
1239 | return; |
1240 | ||
040484af JB |
1241 | reg = FDI_TX_CTL(pipe); |
1242 | val = I915_READ(reg); | |
e2c719b7 | 1243 | I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); |
040484af JB |
1244 | } |
1245 | ||
55607e8a DV |
1246 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, |
1247 | enum pipe pipe, bool state) | |
040484af JB |
1248 | { |
1249 | int reg; | |
1250 | u32 val; | |
55607e8a | 1251 | bool cur_state; |
040484af JB |
1252 | |
1253 | reg = FDI_RX_CTL(pipe); | |
1254 | val = I915_READ(reg); | |
55607e8a | 1255 | cur_state = !!(val & FDI_RX_PLL_ENABLE); |
e2c719b7 | 1256 | I915_STATE_WARN(cur_state != state, |
55607e8a DV |
1257 | "FDI RX PLL assertion failure (expected %s, current %s)\n", |
1258 | state_string(state), state_string(cur_state)); | |
040484af JB |
1259 | } |
1260 | ||
b680c37a DV |
1261 | void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
1262 | enum pipe pipe) | |
ea0760cf | 1263 | { |
bedd4dba JN |
1264 | struct drm_device *dev = dev_priv->dev; |
1265 | int pp_reg; | |
ea0760cf JB |
1266 | u32 val; |
1267 | enum pipe panel_pipe = PIPE_A; | |
0de3b485 | 1268 | bool locked = true; |
ea0760cf | 1269 | |
bedd4dba JN |
1270 | if (WARN_ON(HAS_DDI(dev))) |
1271 | return; | |
1272 | ||
1273 | if (HAS_PCH_SPLIT(dev)) { | |
1274 | u32 port_sel; | |
1275 | ||
ea0760cf | 1276 | pp_reg = PCH_PP_CONTROL; |
bedd4dba JN |
1277 | port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK; |
1278 | ||
1279 | if (port_sel == PANEL_PORT_SELECT_LVDS && | |
1280 | I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT) | |
1281 | panel_pipe = PIPE_B; | |
1282 | /* XXX: else fix for eDP */ | |
1283 | } else if (IS_VALLEYVIEW(dev)) { | |
1284 | /* presumably write lock depends on pipe, not port select */ | |
1285 | pp_reg = VLV_PIPE_PP_CONTROL(pipe); | |
1286 | panel_pipe = pipe; | |
ea0760cf JB |
1287 | } else { |
1288 | pp_reg = PP_CONTROL; | |
bedd4dba JN |
1289 | if (I915_READ(LVDS) & LVDS_PIPEB_SELECT) |
1290 | panel_pipe = PIPE_B; | |
ea0760cf JB |
1291 | } |
1292 | ||
1293 | val = I915_READ(pp_reg); | |
1294 | if (!(val & PANEL_POWER_ON) || | |
ec49ba2d | 1295 | ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS)) |
ea0760cf JB |
1296 | locked = false; |
1297 | ||
e2c719b7 | 1298 | I915_STATE_WARN(panel_pipe == pipe && locked, |
ea0760cf | 1299 | "panel assertion failure, pipe %c regs locked\n", |
9db4a9c7 | 1300 | pipe_name(pipe)); |
ea0760cf JB |
1301 | } |
1302 | ||
93ce0ba6 JN |
1303 | static void assert_cursor(struct drm_i915_private *dev_priv, |
1304 | enum pipe pipe, bool state) | |
1305 | { | |
1306 | struct drm_device *dev = dev_priv->dev; | |
1307 | bool cur_state; | |
1308 | ||
d9d82081 | 1309 | if (IS_845G(dev) || IS_I865G(dev)) |
93ce0ba6 | 1310 | cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE; |
d9d82081 | 1311 | else |
5efb3e28 | 1312 | cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; |
93ce0ba6 | 1313 | |
e2c719b7 | 1314 | I915_STATE_WARN(cur_state != state, |
93ce0ba6 JN |
1315 | "cursor on pipe %c assertion failure (expected %s, current %s)\n", |
1316 | pipe_name(pipe), state_string(state), state_string(cur_state)); | |
1317 | } | |
1318 | #define assert_cursor_enabled(d, p) assert_cursor(d, p, true) | |
1319 | #define assert_cursor_disabled(d, p) assert_cursor(d, p, false) | |
1320 | ||
b840d907 JB |
1321 | void assert_pipe(struct drm_i915_private *dev_priv, |
1322 | enum pipe pipe, bool state) | |
b24e7179 JB |
1323 | { |
1324 | int reg; | |
1325 | u32 val; | |
63d7bbe9 | 1326 | bool cur_state; |
702e7a56 PZ |
1327 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1328 | pipe); | |
b24e7179 | 1329 | |
b6b5d049 VS |
1330 | /* if we need the pipe quirk it must be always on */ |
1331 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
1332 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
8e636784 DV |
1333 | state = true; |
1334 | ||
f458ebbc | 1335 | if (!intel_display_power_is_enabled(dev_priv, |
b97186f0 | 1336 | POWER_DOMAIN_TRANSCODER(cpu_transcoder))) { |
69310161 PZ |
1337 | cur_state = false; |
1338 | } else { | |
1339 | reg = PIPECONF(cpu_transcoder); | |
1340 | val = I915_READ(reg); | |
1341 | cur_state = !!(val & PIPECONF_ENABLE); | |
1342 | } | |
1343 | ||
e2c719b7 | 1344 | I915_STATE_WARN(cur_state != state, |
63d7bbe9 | 1345 | "pipe %c assertion failure (expected %s, current %s)\n", |
9db4a9c7 | 1346 | pipe_name(pipe), state_string(state), state_string(cur_state)); |
b24e7179 JB |
1347 | } |
1348 | ||
931872fc CW |
1349 | static void assert_plane(struct drm_i915_private *dev_priv, |
1350 | enum plane plane, bool state) | |
b24e7179 JB |
1351 | { |
1352 | int reg; | |
1353 | u32 val; | |
931872fc | 1354 | bool cur_state; |
b24e7179 JB |
1355 | |
1356 | reg = DSPCNTR(plane); | |
1357 | val = I915_READ(reg); | |
931872fc | 1358 | cur_state = !!(val & DISPLAY_PLANE_ENABLE); |
e2c719b7 | 1359 | I915_STATE_WARN(cur_state != state, |
931872fc CW |
1360 | "plane %c assertion failure (expected %s, current %s)\n", |
1361 | plane_name(plane), state_string(state), state_string(cur_state)); | |
b24e7179 JB |
1362 | } |
1363 | ||
931872fc CW |
1364 | #define assert_plane_enabled(d, p) assert_plane(d, p, true) |
1365 | #define assert_plane_disabled(d, p) assert_plane(d, p, false) | |
1366 | ||
b24e7179 JB |
1367 | static void assert_planes_disabled(struct drm_i915_private *dev_priv, |
1368 | enum pipe pipe) | |
1369 | { | |
653e1026 | 1370 | struct drm_device *dev = dev_priv->dev; |
b24e7179 JB |
1371 | int reg, i; |
1372 | u32 val; | |
1373 | int cur_pipe; | |
1374 | ||
653e1026 VS |
1375 | /* Primary planes are fixed to pipes on gen4+ */ |
1376 | if (INTEL_INFO(dev)->gen >= 4) { | |
28c05794 AJ |
1377 | reg = DSPCNTR(pipe); |
1378 | val = I915_READ(reg); | |
e2c719b7 | 1379 | I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE, |
28c05794 AJ |
1380 | "plane %c assertion failure, should be disabled but not\n", |
1381 | plane_name(pipe)); | |
19ec1358 | 1382 | return; |
28c05794 | 1383 | } |
19ec1358 | 1384 | |
b24e7179 | 1385 | /* Need to check both planes against the pipe */ |
055e393f | 1386 | for_each_pipe(dev_priv, i) { |
b24e7179 JB |
1387 | reg = DSPCNTR(i); |
1388 | val = I915_READ(reg); | |
1389 | cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> | |
1390 | DISPPLANE_SEL_PIPE_SHIFT; | |
e2c719b7 | 1391 | I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, |
9db4a9c7 JB |
1392 | "plane %c assertion failure, should be off on pipe %c but is still active\n", |
1393 | plane_name(i), pipe_name(pipe)); | |
b24e7179 JB |
1394 | } |
1395 | } | |
1396 | ||
19332d7a JB |
1397 | static void assert_sprites_disabled(struct drm_i915_private *dev_priv, |
1398 | enum pipe pipe) | |
1399 | { | |
20674eef | 1400 | struct drm_device *dev = dev_priv->dev; |
1fe47785 | 1401 | int reg, sprite; |
19332d7a JB |
1402 | u32 val; |
1403 | ||
7feb8b88 | 1404 | if (INTEL_INFO(dev)->gen >= 9) { |
3bdcfc0c | 1405 | for_each_sprite(dev_priv, pipe, sprite) { |
7feb8b88 | 1406 | val = I915_READ(PLANE_CTL(pipe, sprite)); |
e2c719b7 | 1407 | I915_STATE_WARN(val & PLANE_CTL_ENABLE, |
7feb8b88 DL |
1408 | "plane %d assertion failure, should be off on pipe %c but is still active\n", |
1409 | sprite, pipe_name(pipe)); | |
1410 | } | |
1411 | } else if (IS_VALLEYVIEW(dev)) { | |
3bdcfc0c | 1412 | for_each_sprite(dev_priv, pipe, sprite) { |
1fe47785 | 1413 | reg = SPCNTR(pipe, sprite); |
20674eef | 1414 | val = I915_READ(reg); |
e2c719b7 | 1415 | I915_STATE_WARN(val & SP_ENABLE, |
20674eef | 1416 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
1fe47785 | 1417 | sprite_name(pipe, sprite), pipe_name(pipe)); |
20674eef VS |
1418 | } |
1419 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
1420 | reg = SPRCTL(pipe); | |
19332d7a | 1421 | val = I915_READ(reg); |
e2c719b7 | 1422 | I915_STATE_WARN(val & SPRITE_ENABLE, |
06da8da2 | 1423 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef VS |
1424 | plane_name(pipe), pipe_name(pipe)); |
1425 | } else if (INTEL_INFO(dev)->gen >= 5) { | |
1426 | reg = DVSCNTR(pipe); | |
19332d7a | 1427 | val = I915_READ(reg); |
e2c719b7 | 1428 | I915_STATE_WARN(val & DVS_ENABLE, |
06da8da2 | 1429 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef | 1430 | plane_name(pipe), pipe_name(pipe)); |
19332d7a JB |
1431 | } |
1432 | } | |
1433 | ||
08c71e5e VS |
1434 | static void assert_vblank_disabled(struct drm_crtc *crtc) |
1435 | { | |
e2c719b7 | 1436 | if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0)) |
08c71e5e VS |
1437 | drm_crtc_vblank_put(crtc); |
1438 | } | |
1439 | ||
89eff4be | 1440 | static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv) |
92f2584a JB |
1441 | { |
1442 | u32 val; | |
1443 | bool enabled; | |
1444 | ||
e2c719b7 | 1445 | I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev))); |
9d82aa17 | 1446 | |
92f2584a JB |
1447 | val = I915_READ(PCH_DREF_CONTROL); |
1448 | enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK | | |
1449 | DREF_SUPERSPREAD_SOURCE_MASK)); | |
e2c719b7 | 1450 | I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n"); |
92f2584a JB |
1451 | } |
1452 | ||
ab9412ba DV |
1453 | static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, |
1454 | enum pipe pipe) | |
92f2584a JB |
1455 | { |
1456 | int reg; | |
1457 | u32 val; | |
1458 | bool enabled; | |
1459 | ||
ab9412ba | 1460 | reg = PCH_TRANSCONF(pipe); |
92f2584a JB |
1461 | val = I915_READ(reg); |
1462 | enabled = !!(val & TRANS_ENABLE); | |
e2c719b7 | 1463 | I915_STATE_WARN(enabled, |
9db4a9c7 JB |
1464 | "transcoder assertion failed, should be off on pipe %c but is still active\n", |
1465 | pipe_name(pipe)); | |
92f2584a JB |
1466 | } |
1467 | ||
4e634389 KP |
1468 | static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, |
1469 | enum pipe pipe, u32 port_sel, u32 val) | |
f0575e92 KP |
1470 | { |
1471 | if ((val & DP_PORT_EN) == 0) | |
1472 | return false; | |
1473 | ||
1474 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1475 | u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe); | |
1476 | u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg); | |
1477 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) | |
1478 | return false; | |
44f37d1f CML |
1479 | } else if (IS_CHERRYVIEW(dev_priv->dev)) { |
1480 | if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe)) | |
1481 | return false; | |
f0575e92 KP |
1482 | } else { |
1483 | if ((val & DP_PIPE_MASK) != (pipe << 30)) | |
1484 | return false; | |
1485 | } | |
1486 | return true; | |
1487 | } | |
1488 | ||
1519b995 KP |
1489 | static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, |
1490 | enum pipe pipe, u32 val) | |
1491 | { | |
dc0fa718 | 1492 | if ((val & SDVO_ENABLE) == 0) |
1519b995 KP |
1493 | return false; |
1494 | ||
1495 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
dc0fa718 | 1496 | if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe)) |
1519b995 | 1497 | return false; |
44f37d1f CML |
1498 | } else if (IS_CHERRYVIEW(dev_priv->dev)) { |
1499 | if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe)) | |
1500 | return false; | |
1519b995 | 1501 | } else { |
dc0fa718 | 1502 | if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe)) |
1519b995 KP |
1503 | return false; |
1504 | } | |
1505 | return true; | |
1506 | } | |
1507 | ||
1508 | static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, | |
1509 | enum pipe pipe, u32 val) | |
1510 | { | |
1511 | if ((val & LVDS_PORT_EN) == 0) | |
1512 | return false; | |
1513 | ||
1514 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1515 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1516 | return false; | |
1517 | } else { | |
1518 | if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) | |
1519 | return false; | |
1520 | } | |
1521 | return true; | |
1522 | } | |
1523 | ||
1524 | static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, | |
1525 | enum pipe pipe, u32 val) | |
1526 | { | |
1527 | if ((val & ADPA_DAC_ENABLE) == 0) | |
1528 | return false; | |
1529 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1530 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1531 | return false; | |
1532 | } else { | |
1533 | if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) | |
1534 | return false; | |
1535 | } | |
1536 | return true; | |
1537 | } | |
1538 | ||
291906f1 | 1539 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
f0575e92 | 1540 | enum pipe pipe, int reg, u32 port_sel) |
291906f1 | 1541 | { |
47a05eca | 1542 | u32 val = I915_READ(reg); |
e2c719b7 | 1543 | I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
291906f1 | 1544 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1545 | reg, pipe_name(pipe)); |
de9a35ab | 1546 | |
e2c719b7 | 1547 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0 |
75c5da27 | 1548 | && (val & DP_PIPEB_SELECT), |
de9a35ab | 1549 | "IBX PCH dp port still using transcoder B\n"); |
291906f1 JB |
1550 | } |
1551 | ||
1552 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, | |
1553 | enum pipe pipe, int reg) | |
1554 | { | |
47a05eca | 1555 | u32 val = I915_READ(reg); |
e2c719b7 | 1556 | I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val), |
23c99e77 | 1557 | "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1558 | reg, pipe_name(pipe)); |
de9a35ab | 1559 | |
e2c719b7 | 1560 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0 |
75c5da27 | 1561 | && (val & SDVO_PIPE_B_SELECT), |
de9a35ab | 1562 | "IBX PCH hdmi port still using transcoder B\n"); |
291906f1 JB |
1563 | } |
1564 | ||
1565 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, | |
1566 | enum pipe pipe) | |
1567 | { | |
1568 | int reg; | |
1569 | u32 val; | |
291906f1 | 1570 | |
f0575e92 KP |
1571 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
1572 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); | |
1573 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); | |
291906f1 JB |
1574 | |
1575 | reg = PCH_ADPA; | |
1576 | val = I915_READ(reg); | |
e2c719b7 | 1577 | I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1578 | "PCH VGA enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1579 | pipe_name(pipe)); |
291906f1 JB |
1580 | |
1581 | reg = PCH_LVDS; | |
1582 | val = I915_READ(reg); | |
e2c719b7 | 1583 | I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1584 | "PCH LVDS enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1585 | pipe_name(pipe)); |
291906f1 | 1586 | |
e2debe91 PZ |
1587 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB); |
1588 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC); | |
1589 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID); | |
291906f1 JB |
1590 | } |
1591 | ||
40e9cf64 JB |
1592 | static void intel_init_dpio(struct drm_device *dev) |
1593 | { | |
1594 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1595 | ||
1596 | if (!IS_VALLEYVIEW(dev)) | |
1597 | return; | |
1598 | ||
a09caddd CML |
1599 | /* |
1600 | * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C), | |
1601 | * CHV x1 PHY (DP/HDMI D) | |
1602 | * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C) | |
1603 | */ | |
1604 | if (IS_CHERRYVIEW(dev)) { | |
1605 | DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2; | |
1606 | DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO; | |
1607 | } else { | |
1608 | DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO; | |
1609 | } | |
5382f5f3 JB |
1610 | } |
1611 | ||
d288f65f | 1612 | static void vlv_enable_pll(struct intel_crtc *crtc, |
5cec258b | 1613 | const struct intel_crtc_state *pipe_config) |
87442f73 | 1614 | { |
426115cf DV |
1615 | struct drm_device *dev = crtc->base.dev; |
1616 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1617 | int reg = DPLL(crtc->pipe); | |
d288f65f | 1618 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
87442f73 | 1619 | |
426115cf | 1620 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87442f73 DV |
1621 | |
1622 | /* No really, not for ILK+ */ | |
1623 | BUG_ON(!IS_VALLEYVIEW(dev_priv->dev)); | |
1624 | ||
1625 | /* PLL is protected by panel, make sure we can write it */ | |
6a9e7363 | 1626 | if (IS_MOBILE(dev_priv->dev)) |
426115cf | 1627 | assert_panel_unlocked(dev_priv, crtc->pipe); |
87442f73 | 1628 | |
426115cf DV |
1629 | I915_WRITE(reg, dpll); |
1630 | POSTING_READ(reg); | |
1631 | udelay(150); | |
1632 | ||
1633 | if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) | |
1634 | DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe); | |
1635 | ||
d288f65f | 1636 | I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md); |
426115cf | 1637 | POSTING_READ(DPLL_MD(crtc->pipe)); |
87442f73 DV |
1638 | |
1639 | /* We do this three times for luck */ | |
426115cf | 1640 | I915_WRITE(reg, dpll); |
87442f73 DV |
1641 | POSTING_READ(reg); |
1642 | udelay(150); /* wait for warmup */ | |
426115cf | 1643 | I915_WRITE(reg, dpll); |
87442f73 DV |
1644 | POSTING_READ(reg); |
1645 | udelay(150); /* wait for warmup */ | |
426115cf | 1646 | I915_WRITE(reg, dpll); |
87442f73 DV |
1647 | POSTING_READ(reg); |
1648 | udelay(150); /* wait for warmup */ | |
1649 | } | |
1650 | ||
d288f65f | 1651 | static void chv_enable_pll(struct intel_crtc *crtc, |
5cec258b | 1652 | const struct intel_crtc_state *pipe_config) |
9d556c99 CML |
1653 | { |
1654 | struct drm_device *dev = crtc->base.dev; | |
1655 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1656 | int pipe = crtc->pipe; | |
1657 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
9d556c99 CML |
1658 | u32 tmp; |
1659 | ||
1660 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
1661 | ||
1662 | BUG_ON(!IS_CHERRYVIEW(dev_priv->dev)); | |
1663 | ||
a580516d | 1664 | mutex_lock(&dev_priv->sb_lock); |
9d556c99 CML |
1665 | |
1666 | /* Enable back the 10bit clock to display controller */ | |
1667 | tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1668 | tmp |= DPIO_DCLKP_EN; | |
1669 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp); | |
1670 | ||
54433e91 VS |
1671 | mutex_unlock(&dev_priv->sb_lock); |
1672 | ||
9d556c99 CML |
1673 | /* |
1674 | * Need to wait > 100ns between dclkp clock enable bit and PLL enable. | |
1675 | */ | |
1676 | udelay(1); | |
1677 | ||
1678 | /* Enable PLL */ | |
d288f65f | 1679 | I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); |
9d556c99 CML |
1680 | |
1681 | /* Check PLL is locked */ | |
a11b0703 | 1682 | if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) |
9d556c99 CML |
1683 | DRM_ERROR("PLL %d failed to lock\n", pipe); |
1684 | ||
a11b0703 | 1685 | /* not sure when this should be written */ |
d288f65f | 1686 | I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); |
a11b0703 | 1687 | POSTING_READ(DPLL_MD(pipe)); |
9d556c99 CML |
1688 | } |
1689 | ||
1c4e0274 VS |
1690 | static int intel_num_dvo_pipes(struct drm_device *dev) |
1691 | { | |
1692 | struct intel_crtc *crtc; | |
1693 | int count = 0; | |
1694 | ||
1695 | for_each_intel_crtc(dev, crtc) | |
1696 | count += crtc->active && | |
409ee761 | 1697 | intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO); |
1c4e0274 VS |
1698 | |
1699 | return count; | |
1700 | } | |
1701 | ||
66e3d5c0 | 1702 | static void i9xx_enable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1703 | { |
66e3d5c0 DV |
1704 | struct drm_device *dev = crtc->base.dev; |
1705 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1706 | int reg = DPLL(crtc->pipe); | |
6e3c9717 | 1707 | u32 dpll = crtc->config->dpll_hw_state.dpll; |
63d7bbe9 | 1708 | |
66e3d5c0 | 1709 | assert_pipe_disabled(dev_priv, crtc->pipe); |
58c6eaa2 | 1710 | |
63d7bbe9 | 1711 | /* No really, not for ILK+ */ |
3d13ef2e | 1712 | BUG_ON(INTEL_INFO(dev)->gen >= 5); |
63d7bbe9 JB |
1713 | |
1714 | /* PLL is protected by panel, make sure we can write it */ | |
66e3d5c0 DV |
1715 | if (IS_MOBILE(dev) && !IS_I830(dev)) |
1716 | assert_panel_unlocked(dev_priv, crtc->pipe); | |
63d7bbe9 | 1717 | |
1c4e0274 VS |
1718 | /* Enable DVO 2x clock on both PLLs if necessary */ |
1719 | if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) { | |
1720 | /* | |
1721 | * It appears to be important that we don't enable this | |
1722 | * for the current pipe before otherwise configuring the | |
1723 | * PLL. No idea how this should be handled if multiple | |
1724 | * DVO outputs are enabled simultaneosly. | |
1725 | */ | |
1726 | dpll |= DPLL_DVO_2X_MODE; | |
1727 | I915_WRITE(DPLL(!crtc->pipe), | |
1728 | I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE); | |
1729 | } | |
66e3d5c0 DV |
1730 | |
1731 | /* Wait for the clocks to stabilize. */ | |
1732 | POSTING_READ(reg); | |
1733 | udelay(150); | |
1734 | ||
1735 | if (INTEL_INFO(dev)->gen >= 4) { | |
1736 | I915_WRITE(DPLL_MD(crtc->pipe), | |
6e3c9717 | 1737 | crtc->config->dpll_hw_state.dpll_md); |
66e3d5c0 DV |
1738 | } else { |
1739 | /* The pixel multiplier can only be updated once the | |
1740 | * DPLL is enabled and the clocks are stable. | |
1741 | * | |
1742 | * So write it again. | |
1743 | */ | |
1744 | I915_WRITE(reg, dpll); | |
1745 | } | |
63d7bbe9 JB |
1746 | |
1747 | /* We do this three times for luck */ | |
66e3d5c0 | 1748 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1749 | POSTING_READ(reg); |
1750 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1751 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1752 | POSTING_READ(reg); |
1753 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1754 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1755 | POSTING_READ(reg); |
1756 | udelay(150); /* wait for warmup */ | |
1757 | } | |
1758 | ||
1759 | /** | |
50b44a44 | 1760 | * i9xx_disable_pll - disable a PLL |
63d7bbe9 JB |
1761 | * @dev_priv: i915 private structure |
1762 | * @pipe: pipe PLL to disable | |
1763 | * | |
1764 | * Disable the PLL for @pipe, making sure the pipe is off first. | |
1765 | * | |
1766 | * Note! This is for pre-ILK only. | |
1767 | */ | |
1c4e0274 | 1768 | static void i9xx_disable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1769 | { |
1c4e0274 VS |
1770 | struct drm_device *dev = crtc->base.dev; |
1771 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1772 | enum pipe pipe = crtc->pipe; | |
1773 | ||
1774 | /* Disable DVO 2x clock on both PLLs if necessary */ | |
1775 | if (IS_I830(dev) && | |
409ee761 | 1776 | intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) && |
1c4e0274 VS |
1777 | intel_num_dvo_pipes(dev) == 1) { |
1778 | I915_WRITE(DPLL(PIPE_B), | |
1779 | I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE); | |
1780 | I915_WRITE(DPLL(PIPE_A), | |
1781 | I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE); | |
1782 | } | |
1783 | ||
b6b5d049 VS |
1784 | /* Don't disable pipe or pipe PLLs if needed */ |
1785 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
1786 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
63d7bbe9 JB |
1787 | return; |
1788 | ||
1789 | /* Make sure the pipe isn't still relying on us */ | |
1790 | assert_pipe_disabled(dev_priv, pipe); | |
1791 | ||
50b44a44 DV |
1792 | I915_WRITE(DPLL(pipe), 0); |
1793 | POSTING_READ(DPLL(pipe)); | |
63d7bbe9 JB |
1794 | } |
1795 | ||
f6071166 JB |
1796 | static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
1797 | { | |
1798 | u32 val = 0; | |
1799 | ||
1800 | /* Make sure the pipe isn't still relying on us */ | |
1801 | assert_pipe_disabled(dev_priv, pipe); | |
1802 | ||
e5cbfbfb ID |
1803 | /* |
1804 | * Leave integrated clock source and reference clock enabled for pipe B. | |
1805 | * The latter is needed for VGA hotplug / manual detection. | |
1806 | */ | |
f6071166 | 1807 | if (pipe == PIPE_B) |
e5cbfbfb | 1808 | val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV; |
f6071166 JB |
1809 | I915_WRITE(DPLL(pipe), val); |
1810 | POSTING_READ(DPLL(pipe)); | |
076ed3b2 CML |
1811 | |
1812 | } | |
1813 | ||
1814 | static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) | |
1815 | { | |
d752048d | 1816 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
076ed3b2 CML |
1817 | u32 val; |
1818 | ||
a11b0703 VS |
1819 | /* Make sure the pipe isn't still relying on us */ |
1820 | assert_pipe_disabled(dev_priv, pipe); | |
076ed3b2 | 1821 | |
a11b0703 | 1822 | /* Set PLL en = 0 */ |
d17ec4ce | 1823 | val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV; |
a11b0703 VS |
1824 | if (pipe != PIPE_A) |
1825 | val |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
1826 | I915_WRITE(DPLL(pipe), val); | |
1827 | POSTING_READ(DPLL(pipe)); | |
d752048d | 1828 | |
a580516d | 1829 | mutex_lock(&dev_priv->sb_lock); |
d752048d VS |
1830 | |
1831 | /* Disable 10bit clock to display controller */ | |
1832 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1833 | val &= ~DPIO_DCLKP_EN; | |
1834 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val); | |
1835 | ||
61407f6d VS |
1836 | /* disable left/right clock distribution */ |
1837 | if (pipe != PIPE_B) { | |
1838 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); | |
1839 | val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); | |
1840 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); | |
1841 | } else { | |
1842 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); | |
1843 | val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); | |
1844 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); | |
1845 | } | |
1846 | ||
a580516d | 1847 | mutex_unlock(&dev_priv->sb_lock); |
f6071166 JB |
1848 | } |
1849 | ||
e4607fcf | 1850 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, |
9b6de0a1 VS |
1851 | struct intel_digital_port *dport, |
1852 | unsigned int expected_mask) | |
89b667f8 JB |
1853 | { |
1854 | u32 port_mask; | |
00fc31b7 | 1855 | int dpll_reg; |
89b667f8 | 1856 | |
e4607fcf CML |
1857 | switch (dport->port) { |
1858 | case PORT_B: | |
89b667f8 | 1859 | port_mask = DPLL_PORTB_READY_MASK; |
00fc31b7 | 1860 | dpll_reg = DPLL(0); |
e4607fcf CML |
1861 | break; |
1862 | case PORT_C: | |
89b667f8 | 1863 | port_mask = DPLL_PORTC_READY_MASK; |
00fc31b7 | 1864 | dpll_reg = DPLL(0); |
9b6de0a1 | 1865 | expected_mask <<= 4; |
00fc31b7 CML |
1866 | break; |
1867 | case PORT_D: | |
1868 | port_mask = DPLL_PORTD_READY_MASK; | |
1869 | dpll_reg = DPIO_PHY_STATUS; | |
e4607fcf CML |
1870 | break; |
1871 | default: | |
1872 | BUG(); | |
1873 | } | |
89b667f8 | 1874 | |
9b6de0a1 VS |
1875 | if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000)) |
1876 | WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n", | |
1877 | port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask); | |
89b667f8 JB |
1878 | } |
1879 | ||
b14b1055 DV |
1880 | static void intel_prepare_shared_dpll(struct intel_crtc *crtc) |
1881 | { | |
1882 | struct drm_device *dev = crtc->base.dev; | |
1883 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1884 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); | |
1885 | ||
be19f0ff CW |
1886 | if (WARN_ON(pll == NULL)) |
1887 | return; | |
1888 | ||
3e369b76 | 1889 | WARN_ON(!pll->config.crtc_mask); |
b14b1055 DV |
1890 | if (pll->active == 0) { |
1891 | DRM_DEBUG_DRIVER("setting up %s\n", pll->name); | |
1892 | WARN_ON(pll->on); | |
1893 | assert_shared_dpll_disabled(dev_priv, pll); | |
1894 | ||
1895 | pll->mode_set(dev_priv, pll); | |
1896 | } | |
1897 | } | |
1898 | ||
92f2584a | 1899 | /** |
85b3894f | 1900 | * intel_enable_shared_dpll - enable PCH PLL |
92f2584a JB |
1901 | * @dev_priv: i915 private structure |
1902 | * @pipe: pipe PLL to enable | |
1903 | * | |
1904 | * The PCH PLL needs to be enabled before the PCH transcoder, since it | |
1905 | * drives the transcoder clock. | |
1906 | */ | |
85b3894f | 1907 | static void intel_enable_shared_dpll(struct intel_crtc *crtc) |
92f2584a | 1908 | { |
3d13ef2e DL |
1909 | struct drm_device *dev = crtc->base.dev; |
1910 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2b78267 | 1911 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
92f2584a | 1912 | |
87a875bb | 1913 | if (WARN_ON(pll == NULL)) |
48da64a8 CW |
1914 | return; |
1915 | ||
3e369b76 | 1916 | if (WARN_ON(pll->config.crtc_mask == 0)) |
48da64a8 | 1917 | return; |
ee7b9f93 | 1918 | |
74dd6928 | 1919 | DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n", |
46edb027 | 1920 | pll->name, pll->active, pll->on, |
e2b78267 | 1921 | crtc->base.base.id); |
92f2584a | 1922 | |
cdbd2316 DV |
1923 | if (pll->active++) { |
1924 | WARN_ON(!pll->on); | |
e9d6944e | 1925 | assert_shared_dpll_enabled(dev_priv, pll); |
ee7b9f93 JB |
1926 | return; |
1927 | } | |
f4a091c7 | 1928 | WARN_ON(pll->on); |
ee7b9f93 | 1929 | |
bd2bb1b9 PZ |
1930 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); |
1931 | ||
46edb027 | 1932 | DRM_DEBUG_KMS("enabling %s\n", pll->name); |
e7b903d2 | 1933 | pll->enable(dev_priv, pll); |
ee7b9f93 | 1934 | pll->on = true; |
92f2584a JB |
1935 | } |
1936 | ||
f6daaec2 | 1937 | static void intel_disable_shared_dpll(struct intel_crtc *crtc) |
92f2584a | 1938 | { |
3d13ef2e DL |
1939 | struct drm_device *dev = crtc->base.dev; |
1940 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2b78267 | 1941 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
4c609cb8 | 1942 | |
92f2584a | 1943 | /* PCH only available on ILK+ */ |
3d13ef2e | 1944 | BUG_ON(INTEL_INFO(dev)->gen < 5); |
87a875bb | 1945 | if (WARN_ON(pll == NULL)) |
ee7b9f93 | 1946 | return; |
92f2584a | 1947 | |
3e369b76 | 1948 | if (WARN_ON(pll->config.crtc_mask == 0)) |
48da64a8 | 1949 | return; |
7a419866 | 1950 | |
46edb027 DV |
1951 | DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n", |
1952 | pll->name, pll->active, pll->on, | |
e2b78267 | 1953 | crtc->base.base.id); |
7a419866 | 1954 | |
48da64a8 | 1955 | if (WARN_ON(pll->active == 0)) { |
e9d6944e | 1956 | assert_shared_dpll_disabled(dev_priv, pll); |
48da64a8 CW |
1957 | return; |
1958 | } | |
1959 | ||
e9d6944e | 1960 | assert_shared_dpll_enabled(dev_priv, pll); |
f4a091c7 | 1961 | WARN_ON(!pll->on); |
cdbd2316 | 1962 | if (--pll->active) |
7a419866 | 1963 | return; |
ee7b9f93 | 1964 | |
46edb027 | 1965 | DRM_DEBUG_KMS("disabling %s\n", pll->name); |
e7b903d2 | 1966 | pll->disable(dev_priv, pll); |
ee7b9f93 | 1967 | pll->on = false; |
bd2bb1b9 PZ |
1968 | |
1969 | intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); | |
92f2584a JB |
1970 | } |
1971 | ||
b8a4f404 PZ |
1972 | static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
1973 | enum pipe pipe) | |
040484af | 1974 | { |
23670b32 | 1975 | struct drm_device *dev = dev_priv->dev; |
7c26e5c6 | 1976 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
e2b78267 | 1977 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
23670b32 | 1978 | uint32_t reg, val, pipeconf_val; |
040484af JB |
1979 | |
1980 | /* PCH only available on ILK+ */ | |
55522f37 | 1981 | BUG_ON(!HAS_PCH_SPLIT(dev)); |
040484af JB |
1982 | |
1983 | /* Make sure PCH DPLL is enabled */ | |
e72f9fbf | 1984 | assert_shared_dpll_enabled(dev_priv, |
e9d6944e | 1985 | intel_crtc_to_shared_dpll(intel_crtc)); |
040484af JB |
1986 | |
1987 | /* FDI must be feeding us bits for PCH ports */ | |
1988 | assert_fdi_tx_enabled(dev_priv, pipe); | |
1989 | assert_fdi_rx_enabled(dev_priv, pipe); | |
1990 | ||
23670b32 DV |
1991 | if (HAS_PCH_CPT(dev)) { |
1992 | /* Workaround: Set the timing override bit before enabling the | |
1993 | * pch transcoder. */ | |
1994 | reg = TRANS_CHICKEN2(pipe); | |
1995 | val = I915_READ(reg); | |
1996 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1997 | I915_WRITE(reg, val); | |
59c859d6 | 1998 | } |
23670b32 | 1999 | |
ab9412ba | 2000 | reg = PCH_TRANSCONF(pipe); |
040484af | 2001 | val = I915_READ(reg); |
5f7f726d | 2002 | pipeconf_val = I915_READ(PIPECONF(pipe)); |
e9bcff5c JB |
2003 | |
2004 | if (HAS_PCH_IBX(dev_priv->dev)) { | |
2005 | /* | |
2006 | * make the BPC in transcoder be consistent with | |
2007 | * that in pipeconf reg. | |
2008 | */ | |
dfd07d72 DV |
2009 | val &= ~PIPECONF_BPC_MASK; |
2010 | val |= pipeconf_val & PIPECONF_BPC_MASK; | |
e9bcff5c | 2011 | } |
5f7f726d PZ |
2012 | |
2013 | val &= ~TRANS_INTERLACE_MASK; | |
2014 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) | |
7c26e5c6 | 2015 | if (HAS_PCH_IBX(dev_priv->dev) && |
409ee761 | 2016 | intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
7c26e5c6 PZ |
2017 | val |= TRANS_LEGACY_INTERLACED_ILK; |
2018 | else | |
2019 | val |= TRANS_INTERLACED; | |
5f7f726d PZ |
2020 | else |
2021 | val |= TRANS_PROGRESSIVE; | |
2022 | ||
040484af JB |
2023 | I915_WRITE(reg, val | TRANS_ENABLE); |
2024 | if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100)) | |
4bb6f1f3 | 2025 | DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe)); |
040484af JB |
2026 | } |
2027 | ||
8fb033d7 | 2028 | static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
937bb610 | 2029 | enum transcoder cpu_transcoder) |
040484af | 2030 | { |
8fb033d7 | 2031 | u32 val, pipeconf_val; |
8fb033d7 PZ |
2032 | |
2033 | /* PCH only available on ILK+ */ | |
55522f37 | 2034 | BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev)); |
8fb033d7 | 2035 | |
8fb033d7 | 2036 | /* FDI must be feeding us bits for PCH ports */ |
1a240d4d | 2037 | assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); |
937bb610 | 2038 | assert_fdi_rx_enabled(dev_priv, TRANSCODER_A); |
8fb033d7 | 2039 | |
223a6fdf PZ |
2040 | /* Workaround: set timing override bit. */ |
2041 | val = I915_READ(_TRANSA_CHICKEN2); | |
23670b32 | 2042 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
223a6fdf PZ |
2043 | I915_WRITE(_TRANSA_CHICKEN2, val); |
2044 | ||
25f3ef11 | 2045 | val = TRANS_ENABLE; |
937bb610 | 2046 | pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); |
8fb033d7 | 2047 | |
9a76b1c6 PZ |
2048 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == |
2049 | PIPECONF_INTERLACED_ILK) | |
a35f2679 | 2050 | val |= TRANS_INTERLACED; |
8fb033d7 PZ |
2051 | else |
2052 | val |= TRANS_PROGRESSIVE; | |
2053 | ||
ab9412ba DV |
2054 | I915_WRITE(LPT_TRANSCONF, val); |
2055 | if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100)) | |
937bb610 | 2056 | DRM_ERROR("Failed to enable PCH transcoder\n"); |
8fb033d7 PZ |
2057 | } |
2058 | ||
b8a4f404 PZ |
2059 | static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, |
2060 | enum pipe pipe) | |
040484af | 2061 | { |
23670b32 DV |
2062 | struct drm_device *dev = dev_priv->dev; |
2063 | uint32_t reg, val; | |
040484af JB |
2064 | |
2065 | /* FDI relies on the transcoder */ | |
2066 | assert_fdi_tx_disabled(dev_priv, pipe); | |
2067 | assert_fdi_rx_disabled(dev_priv, pipe); | |
2068 | ||
291906f1 JB |
2069 | /* Ports must be off as well */ |
2070 | assert_pch_ports_disabled(dev_priv, pipe); | |
2071 | ||
ab9412ba | 2072 | reg = PCH_TRANSCONF(pipe); |
040484af JB |
2073 | val = I915_READ(reg); |
2074 | val &= ~TRANS_ENABLE; | |
2075 | I915_WRITE(reg, val); | |
2076 | /* wait for PCH transcoder off, transcoder state */ | |
2077 | if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50)) | |
4bb6f1f3 | 2078 | DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe)); |
23670b32 DV |
2079 | |
2080 | if (!HAS_PCH_IBX(dev)) { | |
2081 | /* Workaround: Clear the timing override chicken bit again. */ | |
2082 | reg = TRANS_CHICKEN2(pipe); | |
2083 | val = I915_READ(reg); | |
2084 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; | |
2085 | I915_WRITE(reg, val); | |
2086 | } | |
040484af JB |
2087 | } |
2088 | ||
ab4d966c | 2089 | static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) |
8fb033d7 | 2090 | { |
8fb033d7 PZ |
2091 | u32 val; |
2092 | ||
ab9412ba | 2093 | val = I915_READ(LPT_TRANSCONF); |
8fb033d7 | 2094 | val &= ~TRANS_ENABLE; |
ab9412ba | 2095 | I915_WRITE(LPT_TRANSCONF, val); |
8fb033d7 | 2096 | /* wait for PCH transcoder off, transcoder state */ |
ab9412ba | 2097 | if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50)) |
8a52fd9f | 2098 | DRM_ERROR("Failed to disable PCH transcoder\n"); |
223a6fdf PZ |
2099 | |
2100 | /* Workaround: clear timing override bit. */ | |
2101 | val = I915_READ(_TRANSA_CHICKEN2); | |
23670b32 | 2102 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
223a6fdf | 2103 | I915_WRITE(_TRANSA_CHICKEN2, val); |
040484af JB |
2104 | } |
2105 | ||
b24e7179 | 2106 | /** |
309cfea8 | 2107 | * intel_enable_pipe - enable a pipe, asserting requirements |
0372264a | 2108 | * @crtc: crtc responsible for the pipe |
b24e7179 | 2109 | * |
0372264a | 2110 | * Enable @crtc's pipe, making sure that various hardware specific requirements |
b24e7179 | 2111 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. |
b24e7179 | 2112 | */ |
e1fdc473 | 2113 | static void intel_enable_pipe(struct intel_crtc *crtc) |
b24e7179 | 2114 | { |
0372264a PZ |
2115 | struct drm_device *dev = crtc->base.dev; |
2116 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2117 | enum pipe pipe = crtc->pipe; | |
702e7a56 PZ |
2118 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
2119 | pipe); | |
1a240d4d | 2120 | enum pipe pch_transcoder; |
b24e7179 JB |
2121 | int reg; |
2122 | u32 val; | |
2123 | ||
58c6eaa2 | 2124 | assert_planes_disabled(dev_priv, pipe); |
93ce0ba6 | 2125 | assert_cursor_disabled(dev_priv, pipe); |
58c6eaa2 DV |
2126 | assert_sprites_disabled(dev_priv, pipe); |
2127 | ||
681e5811 | 2128 | if (HAS_PCH_LPT(dev_priv->dev)) |
cc391bbb PZ |
2129 | pch_transcoder = TRANSCODER_A; |
2130 | else | |
2131 | pch_transcoder = pipe; | |
2132 | ||
b24e7179 JB |
2133 | /* |
2134 | * A pipe without a PLL won't actually be able to drive bits from | |
2135 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't | |
2136 | * need the check. | |
2137 | */ | |
50360403 | 2138 | if (HAS_GMCH_DISPLAY(dev_priv->dev)) |
409ee761 | 2139 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) |
23538ef1 JN |
2140 | assert_dsi_pll_enabled(dev_priv); |
2141 | else | |
2142 | assert_pll_enabled(dev_priv, pipe); | |
040484af | 2143 | else { |
6e3c9717 | 2144 | if (crtc->config->has_pch_encoder) { |
040484af | 2145 | /* if driving the PCH, we need FDI enabled */ |
cc391bbb | 2146 | assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder); |
1a240d4d DV |
2147 | assert_fdi_tx_pll_enabled(dev_priv, |
2148 | (enum pipe) cpu_transcoder); | |
040484af JB |
2149 | } |
2150 | /* FIXME: assert CPU port conditions for SNB+ */ | |
2151 | } | |
b24e7179 | 2152 | |
702e7a56 | 2153 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 2154 | val = I915_READ(reg); |
7ad25d48 | 2155 | if (val & PIPECONF_ENABLE) { |
b6b5d049 VS |
2156 | WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
2157 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))); | |
00d70b15 | 2158 | return; |
7ad25d48 | 2159 | } |
00d70b15 CW |
2160 | |
2161 | I915_WRITE(reg, val | PIPECONF_ENABLE); | |
851855d8 | 2162 | POSTING_READ(reg); |
b24e7179 JB |
2163 | } |
2164 | ||
2165 | /** | |
309cfea8 | 2166 | * intel_disable_pipe - disable a pipe, asserting requirements |
575f7ab7 | 2167 | * @crtc: crtc whose pipes is to be disabled |
b24e7179 | 2168 | * |
575f7ab7 VS |
2169 | * Disable the pipe of @crtc, making sure that various hardware |
2170 | * specific requirements are met, if applicable, e.g. plane | |
2171 | * disabled, panel fitter off, etc. | |
b24e7179 JB |
2172 | * |
2173 | * Will wait until the pipe has shut down before returning. | |
2174 | */ | |
575f7ab7 | 2175 | static void intel_disable_pipe(struct intel_crtc *crtc) |
b24e7179 | 2176 | { |
575f7ab7 | 2177 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
6e3c9717 | 2178 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 2179 | enum pipe pipe = crtc->pipe; |
b24e7179 JB |
2180 | int reg; |
2181 | u32 val; | |
2182 | ||
2183 | /* | |
2184 | * Make sure planes won't keep trying to pump pixels to us, | |
2185 | * or we might hang the display. | |
2186 | */ | |
2187 | assert_planes_disabled(dev_priv, pipe); | |
93ce0ba6 | 2188 | assert_cursor_disabled(dev_priv, pipe); |
19332d7a | 2189 | assert_sprites_disabled(dev_priv, pipe); |
b24e7179 | 2190 | |
702e7a56 | 2191 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 2192 | val = I915_READ(reg); |
00d70b15 CW |
2193 | if ((val & PIPECONF_ENABLE) == 0) |
2194 | return; | |
2195 | ||
67adc644 VS |
2196 | /* |
2197 | * Double wide has implications for planes | |
2198 | * so best keep it disabled when not needed. | |
2199 | */ | |
6e3c9717 | 2200 | if (crtc->config->double_wide) |
67adc644 VS |
2201 | val &= ~PIPECONF_DOUBLE_WIDE; |
2202 | ||
2203 | /* Don't disable pipe or pipe PLLs if needed */ | |
b6b5d049 VS |
2204 | if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) && |
2205 | !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
67adc644 VS |
2206 | val &= ~PIPECONF_ENABLE; |
2207 | ||
2208 | I915_WRITE(reg, val); | |
2209 | if ((val & PIPECONF_ENABLE) == 0) | |
2210 | intel_wait_for_pipe_off(crtc); | |
b24e7179 JB |
2211 | } |
2212 | ||
2213 | /** | |
262ca2b0 | 2214 | * intel_enable_primary_hw_plane - enable the primary plane on a given pipe |
fdd508a6 VS |
2215 | * @plane: plane to be enabled |
2216 | * @crtc: crtc for the plane | |
b24e7179 | 2217 | * |
fdd508a6 | 2218 | * Enable @plane on @crtc, making sure that the pipe is running first. |
b24e7179 | 2219 | */ |
fdd508a6 VS |
2220 | static void intel_enable_primary_hw_plane(struct drm_plane *plane, |
2221 | struct drm_crtc *crtc) | |
b24e7179 | 2222 | { |
fdd508a6 VS |
2223 | struct drm_device *dev = plane->dev; |
2224 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2225 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
b24e7179 JB |
2226 | |
2227 | /* If the pipe isn't enabled, we can't pump pixels and may hang */ | |
fdd508a6 | 2228 | assert_pipe_enabled(dev_priv, intel_crtc->pipe); |
b70709a6 | 2229 | to_intel_plane_state(plane->state)->visible = true; |
939c2fe8 | 2230 | |
fdd508a6 VS |
2231 | dev_priv->display.update_primary_plane(crtc, plane->fb, |
2232 | crtc->x, crtc->y); | |
b24e7179 JB |
2233 | } |
2234 | ||
693db184 CW |
2235 | static bool need_vtd_wa(struct drm_device *dev) |
2236 | { | |
2237 | #ifdef CONFIG_INTEL_IOMMU | |
2238 | if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped) | |
2239 | return true; | |
2240 | #endif | |
2241 | return false; | |
2242 | } | |
2243 | ||
50470bb0 | 2244 | unsigned int |
6761dd31 TU |
2245 | intel_tile_height(struct drm_device *dev, uint32_t pixel_format, |
2246 | uint64_t fb_format_modifier) | |
a57ce0b2 | 2247 | { |
6761dd31 TU |
2248 | unsigned int tile_height; |
2249 | uint32_t pixel_bytes; | |
a57ce0b2 | 2250 | |
b5d0e9bf DL |
2251 | switch (fb_format_modifier) { |
2252 | case DRM_FORMAT_MOD_NONE: | |
2253 | tile_height = 1; | |
2254 | break; | |
2255 | case I915_FORMAT_MOD_X_TILED: | |
2256 | tile_height = IS_GEN2(dev) ? 16 : 8; | |
2257 | break; | |
2258 | case I915_FORMAT_MOD_Y_TILED: | |
2259 | tile_height = 32; | |
2260 | break; | |
2261 | case I915_FORMAT_MOD_Yf_TILED: | |
6761dd31 TU |
2262 | pixel_bytes = drm_format_plane_cpp(pixel_format, 0); |
2263 | switch (pixel_bytes) { | |
b5d0e9bf | 2264 | default: |
6761dd31 | 2265 | case 1: |
b5d0e9bf DL |
2266 | tile_height = 64; |
2267 | break; | |
6761dd31 TU |
2268 | case 2: |
2269 | case 4: | |
b5d0e9bf DL |
2270 | tile_height = 32; |
2271 | break; | |
6761dd31 | 2272 | case 8: |
b5d0e9bf DL |
2273 | tile_height = 16; |
2274 | break; | |
6761dd31 | 2275 | case 16: |
b5d0e9bf DL |
2276 | WARN_ONCE(1, |
2277 | "128-bit pixels are not supported for display!"); | |
2278 | tile_height = 16; | |
2279 | break; | |
2280 | } | |
2281 | break; | |
2282 | default: | |
2283 | MISSING_CASE(fb_format_modifier); | |
2284 | tile_height = 1; | |
2285 | break; | |
2286 | } | |
091df6cb | 2287 | |
6761dd31 TU |
2288 | return tile_height; |
2289 | } | |
2290 | ||
2291 | unsigned int | |
2292 | intel_fb_align_height(struct drm_device *dev, unsigned int height, | |
2293 | uint32_t pixel_format, uint64_t fb_format_modifier) | |
2294 | { | |
2295 | return ALIGN(height, intel_tile_height(dev, pixel_format, | |
2296 | fb_format_modifier)); | |
a57ce0b2 JB |
2297 | } |
2298 | ||
f64b98cd TU |
2299 | static int |
2300 | intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb, | |
2301 | const struct drm_plane_state *plane_state) | |
2302 | { | |
50470bb0 | 2303 | struct intel_rotation_info *info = &view->rotation_info; |
50470bb0 | 2304 | |
f64b98cd TU |
2305 | *view = i915_ggtt_view_normal; |
2306 | ||
50470bb0 TU |
2307 | if (!plane_state) |
2308 | return 0; | |
2309 | ||
121920fa | 2310 | if (!intel_rotation_90_or_270(plane_state->rotation)) |
50470bb0 TU |
2311 | return 0; |
2312 | ||
9abc4648 | 2313 | *view = i915_ggtt_view_rotated; |
50470bb0 TU |
2314 | |
2315 | info->height = fb->height; | |
2316 | info->pixel_format = fb->pixel_format; | |
2317 | info->pitch = fb->pitches[0]; | |
2318 | info->fb_modifier = fb->modifier[0]; | |
2319 | ||
f64b98cd TU |
2320 | return 0; |
2321 | } | |
2322 | ||
127bd2ac | 2323 | int |
850c4cdc TU |
2324 | intel_pin_and_fence_fb_obj(struct drm_plane *plane, |
2325 | struct drm_framebuffer *fb, | |
82bc3b2d | 2326 | const struct drm_plane_state *plane_state, |
a4872ba6 | 2327 | struct intel_engine_cs *pipelined) |
6b95a207 | 2328 | { |
850c4cdc | 2329 | struct drm_device *dev = fb->dev; |
ce453d81 | 2330 | struct drm_i915_private *dev_priv = dev->dev_private; |
850c4cdc | 2331 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
f64b98cd | 2332 | struct i915_ggtt_view view; |
6b95a207 KH |
2333 | u32 alignment; |
2334 | int ret; | |
2335 | ||
ebcdd39e MR |
2336 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
2337 | ||
7b911adc TU |
2338 | switch (fb->modifier[0]) { |
2339 | case DRM_FORMAT_MOD_NONE: | |
1fada4cc DL |
2340 | if (INTEL_INFO(dev)->gen >= 9) |
2341 | alignment = 256 * 1024; | |
2342 | else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) | |
534843da | 2343 | alignment = 128 * 1024; |
a6c45cf0 | 2344 | else if (INTEL_INFO(dev)->gen >= 4) |
534843da CW |
2345 | alignment = 4 * 1024; |
2346 | else | |
2347 | alignment = 64 * 1024; | |
6b95a207 | 2348 | break; |
7b911adc | 2349 | case I915_FORMAT_MOD_X_TILED: |
1fada4cc DL |
2350 | if (INTEL_INFO(dev)->gen >= 9) |
2351 | alignment = 256 * 1024; | |
2352 | else { | |
2353 | /* pin() will align the object as required by fence */ | |
2354 | alignment = 0; | |
2355 | } | |
6b95a207 | 2356 | break; |
7b911adc | 2357 | case I915_FORMAT_MOD_Y_TILED: |
1327b9a1 DL |
2358 | case I915_FORMAT_MOD_Yf_TILED: |
2359 | if (WARN_ONCE(INTEL_INFO(dev)->gen < 9, | |
2360 | "Y tiling bo slipped through, driver bug!\n")) | |
2361 | return -EINVAL; | |
2362 | alignment = 1 * 1024 * 1024; | |
2363 | break; | |
6b95a207 | 2364 | default: |
7b911adc TU |
2365 | MISSING_CASE(fb->modifier[0]); |
2366 | return -EINVAL; | |
6b95a207 KH |
2367 | } |
2368 | ||
f64b98cd TU |
2369 | ret = intel_fill_fb_ggtt_view(&view, fb, plane_state); |
2370 | if (ret) | |
2371 | return ret; | |
2372 | ||
693db184 CW |
2373 | /* Note that the w/a also requires 64 PTE of padding following the |
2374 | * bo. We currently fill all unused PTE with the shadow page and so | |
2375 | * we should always have valid PTE following the scanout preventing | |
2376 | * the VT-d warning. | |
2377 | */ | |
2378 | if (need_vtd_wa(dev) && alignment < 256 * 1024) | |
2379 | alignment = 256 * 1024; | |
2380 | ||
d6dd6843 PZ |
2381 | /* |
2382 | * Global gtt pte registers are special registers which actually forward | |
2383 | * writes to a chunk of system memory. Which means that there is no risk | |
2384 | * that the register values disappear as soon as we call | |
2385 | * intel_runtime_pm_put(), so it is correct to wrap only the | |
2386 | * pin/unpin/fence and not more. | |
2387 | */ | |
2388 | intel_runtime_pm_get(dev_priv); | |
2389 | ||
ce453d81 | 2390 | dev_priv->mm.interruptible = false; |
e6617330 | 2391 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined, |
f64b98cd | 2392 | &view); |
48b956c5 | 2393 | if (ret) |
ce453d81 | 2394 | goto err_interruptible; |
6b95a207 KH |
2395 | |
2396 | /* Install a fence for tiled scan-out. Pre-i965 always needs a | |
2397 | * fence, whereas 965+ only requires a fence if using | |
2398 | * framebuffer compression. For simplicity, we always install | |
2399 | * a fence as the cost is not that onerous. | |
2400 | */ | |
06d98131 | 2401 | ret = i915_gem_object_get_fence(obj); |
9a5a53b3 CW |
2402 | if (ret) |
2403 | goto err_unpin; | |
1690e1eb | 2404 | |
9a5a53b3 | 2405 | i915_gem_object_pin_fence(obj); |
6b95a207 | 2406 | |
ce453d81 | 2407 | dev_priv->mm.interruptible = true; |
d6dd6843 | 2408 | intel_runtime_pm_put(dev_priv); |
6b95a207 | 2409 | return 0; |
48b956c5 CW |
2410 | |
2411 | err_unpin: | |
f64b98cd | 2412 | i915_gem_object_unpin_from_display_plane(obj, &view); |
ce453d81 CW |
2413 | err_interruptible: |
2414 | dev_priv->mm.interruptible = true; | |
d6dd6843 | 2415 | intel_runtime_pm_put(dev_priv); |
48b956c5 | 2416 | return ret; |
6b95a207 KH |
2417 | } |
2418 | ||
82bc3b2d TU |
2419 | static void intel_unpin_fb_obj(struct drm_framebuffer *fb, |
2420 | const struct drm_plane_state *plane_state) | |
1690e1eb | 2421 | { |
82bc3b2d | 2422 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
f64b98cd TU |
2423 | struct i915_ggtt_view view; |
2424 | int ret; | |
82bc3b2d | 2425 | |
ebcdd39e MR |
2426 | WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex)); |
2427 | ||
f64b98cd TU |
2428 | ret = intel_fill_fb_ggtt_view(&view, fb, plane_state); |
2429 | WARN_ONCE(ret, "Couldn't get view from plane state!"); | |
2430 | ||
1690e1eb | 2431 | i915_gem_object_unpin_fence(obj); |
f64b98cd | 2432 | i915_gem_object_unpin_from_display_plane(obj, &view); |
1690e1eb CW |
2433 | } |
2434 | ||
c2c75131 DV |
2435 | /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel |
2436 | * is assumed to be a power-of-two. */ | |
bc752862 CW |
2437 | unsigned long intel_gen4_compute_page_offset(int *x, int *y, |
2438 | unsigned int tiling_mode, | |
2439 | unsigned int cpp, | |
2440 | unsigned int pitch) | |
c2c75131 | 2441 | { |
bc752862 CW |
2442 | if (tiling_mode != I915_TILING_NONE) { |
2443 | unsigned int tile_rows, tiles; | |
c2c75131 | 2444 | |
bc752862 CW |
2445 | tile_rows = *y / 8; |
2446 | *y %= 8; | |
c2c75131 | 2447 | |
bc752862 CW |
2448 | tiles = *x / (512/cpp); |
2449 | *x %= 512/cpp; | |
2450 | ||
2451 | return tile_rows * pitch * 8 + tiles * 4096; | |
2452 | } else { | |
2453 | unsigned int offset; | |
2454 | ||
2455 | offset = *y * pitch + *x * cpp; | |
2456 | *y = 0; | |
2457 | *x = (offset & 4095) / cpp; | |
2458 | return offset & -4096; | |
2459 | } | |
c2c75131 DV |
2460 | } |
2461 | ||
b35d63fa | 2462 | static int i9xx_format_to_fourcc(int format) |
46f297fb JB |
2463 | { |
2464 | switch (format) { | |
2465 | case DISPPLANE_8BPP: | |
2466 | return DRM_FORMAT_C8; | |
2467 | case DISPPLANE_BGRX555: | |
2468 | return DRM_FORMAT_XRGB1555; | |
2469 | case DISPPLANE_BGRX565: | |
2470 | return DRM_FORMAT_RGB565; | |
2471 | default: | |
2472 | case DISPPLANE_BGRX888: | |
2473 | return DRM_FORMAT_XRGB8888; | |
2474 | case DISPPLANE_RGBX888: | |
2475 | return DRM_FORMAT_XBGR8888; | |
2476 | case DISPPLANE_BGRX101010: | |
2477 | return DRM_FORMAT_XRGB2101010; | |
2478 | case DISPPLANE_RGBX101010: | |
2479 | return DRM_FORMAT_XBGR2101010; | |
2480 | } | |
2481 | } | |
2482 | ||
bc8d7dff DL |
2483 | static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha) |
2484 | { | |
2485 | switch (format) { | |
2486 | case PLANE_CTL_FORMAT_RGB_565: | |
2487 | return DRM_FORMAT_RGB565; | |
2488 | default: | |
2489 | case PLANE_CTL_FORMAT_XRGB_8888: | |
2490 | if (rgb_order) { | |
2491 | if (alpha) | |
2492 | return DRM_FORMAT_ABGR8888; | |
2493 | else | |
2494 | return DRM_FORMAT_XBGR8888; | |
2495 | } else { | |
2496 | if (alpha) | |
2497 | return DRM_FORMAT_ARGB8888; | |
2498 | else | |
2499 | return DRM_FORMAT_XRGB8888; | |
2500 | } | |
2501 | case PLANE_CTL_FORMAT_XRGB_2101010: | |
2502 | if (rgb_order) | |
2503 | return DRM_FORMAT_XBGR2101010; | |
2504 | else | |
2505 | return DRM_FORMAT_XRGB2101010; | |
2506 | } | |
2507 | } | |
2508 | ||
5724dbd1 | 2509 | static bool |
f6936e29 DV |
2510 | intel_alloc_initial_plane_obj(struct intel_crtc *crtc, |
2511 | struct intel_initial_plane_config *plane_config) | |
46f297fb JB |
2512 | { |
2513 | struct drm_device *dev = crtc->base.dev; | |
2514 | struct drm_i915_gem_object *obj = NULL; | |
2515 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; | |
2d14030b | 2516 | struct drm_framebuffer *fb = &plane_config->fb->base; |
f37b5c2b DV |
2517 | u32 base_aligned = round_down(plane_config->base, PAGE_SIZE); |
2518 | u32 size_aligned = round_up(plane_config->base + plane_config->size, | |
2519 | PAGE_SIZE); | |
2520 | ||
2521 | size_aligned -= base_aligned; | |
46f297fb | 2522 | |
ff2652ea CW |
2523 | if (plane_config->size == 0) |
2524 | return false; | |
2525 | ||
f37b5c2b DV |
2526 | obj = i915_gem_object_create_stolen_for_preallocated(dev, |
2527 | base_aligned, | |
2528 | base_aligned, | |
2529 | size_aligned); | |
46f297fb | 2530 | if (!obj) |
484b41dd | 2531 | return false; |
46f297fb | 2532 | |
49af449b DL |
2533 | obj->tiling_mode = plane_config->tiling; |
2534 | if (obj->tiling_mode == I915_TILING_X) | |
6bf129df | 2535 | obj->stride = fb->pitches[0]; |
46f297fb | 2536 | |
6bf129df DL |
2537 | mode_cmd.pixel_format = fb->pixel_format; |
2538 | mode_cmd.width = fb->width; | |
2539 | mode_cmd.height = fb->height; | |
2540 | mode_cmd.pitches[0] = fb->pitches[0]; | |
18c5247e DV |
2541 | mode_cmd.modifier[0] = fb->modifier[0]; |
2542 | mode_cmd.flags = DRM_MODE_FB_MODIFIERS; | |
46f297fb JB |
2543 | |
2544 | mutex_lock(&dev->struct_mutex); | |
6bf129df | 2545 | if (intel_framebuffer_init(dev, to_intel_framebuffer(fb), |
484b41dd | 2546 | &mode_cmd, obj)) { |
46f297fb JB |
2547 | DRM_DEBUG_KMS("intel fb init failed\n"); |
2548 | goto out_unref_obj; | |
2549 | } | |
46f297fb | 2550 | mutex_unlock(&dev->struct_mutex); |
484b41dd | 2551 | |
f6936e29 | 2552 | DRM_DEBUG_KMS("initial plane fb obj %p\n", obj); |
484b41dd | 2553 | return true; |
46f297fb JB |
2554 | |
2555 | out_unref_obj: | |
2556 | drm_gem_object_unreference(&obj->base); | |
2557 | mutex_unlock(&dev->struct_mutex); | |
484b41dd JB |
2558 | return false; |
2559 | } | |
2560 | ||
afd65eb4 MR |
2561 | /* Update plane->state->fb to match plane->fb after driver-internal updates */ |
2562 | static void | |
2563 | update_state_fb(struct drm_plane *plane) | |
2564 | { | |
2565 | if (plane->fb == plane->state->fb) | |
2566 | return; | |
2567 | ||
2568 | if (plane->state->fb) | |
2569 | drm_framebuffer_unreference(plane->state->fb); | |
2570 | plane->state->fb = plane->fb; | |
2571 | if (plane->state->fb) | |
2572 | drm_framebuffer_reference(plane->state->fb); | |
2573 | } | |
2574 | ||
5724dbd1 | 2575 | static void |
f6936e29 DV |
2576 | intel_find_initial_plane_obj(struct intel_crtc *intel_crtc, |
2577 | struct intel_initial_plane_config *plane_config) | |
484b41dd JB |
2578 | { |
2579 | struct drm_device *dev = intel_crtc->base.dev; | |
d9ceb816 | 2580 | struct drm_i915_private *dev_priv = dev->dev_private; |
484b41dd JB |
2581 | struct drm_crtc *c; |
2582 | struct intel_crtc *i; | |
2ff8fde1 | 2583 | struct drm_i915_gem_object *obj; |
88595ac9 DV |
2584 | struct drm_plane *primary = intel_crtc->base.primary; |
2585 | struct drm_framebuffer *fb; | |
484b41dd | 2586 | |
2d14030b | 2587 | if (!plane_config->fb) |
484b41dd JB |
2588 | return; |
2589 | ||
f6936e29 | 2590 | if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) { |
88595ac9 DV |
2591 | fb = &plane_config->fb->base; |
2592 | goto valid_fb; | |
f55548b5 | 2593 | } |
484b41dd | 2594 | |
2d14030b | 2595 | kfree(plane_config->fb); |
484b41dd JB |
2596 | |
2597 | /* | |
2598 | * Failed to alloc the obj, check to see if we should share | |
2599 | * an fb with another CRTC instead | |
2600 | */ | |
70e1e0ec | 2601 | for_each_crtc(dev, c) { |
484b41dd JB |
2602 | i = to_intel_crtc(c); |
2603 | ||
2604 | if (c == &intel_crtc->base) | |
2605 | continue; | |
2606 | ||
2ff8fde1 MR |
2607 | if (!i->active) |
2608 | continue; | |
2609 | ||
88595ac9 DV |
2610 | fb = c->primary->fb; |
2611 | if (!fb) | |
484b41dd JB |
2612 | continue; |
2613 | ||
88595ac9 | 2614 | obj = intel_fb_obj(fb); |
2ff8fde1 | 2615 | if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) { |
88595ac9 DV |
2616 | drm_framebuffer_reference(fb); |
2617 | goto valid_fb; | |
484b41dd JB |
2618 | } |
2619 | } | |
88595ac9 DV |
2620 | |
2621 | return; | |
2622 | ||
2623 | valid_fb: | |
2624 | obj = intel_fb_obj(fb); | |
2625 | if (obj->tiling_mode != I915_TILING_NONE) | |
2626 | dev_priv->preserve_bios_swizzle = true; | |
2627 | ||
2628 | primary->fb = fb; | |
2629 | primary->state->crtc = &intel_crtc->base; | |
2630 | primary->crtc = &intel_crtc->base; | |
2631 | update_state_fb(primary); | |
2632 | obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe); | |
46f297fb JB |
2633 | } |
2634 | ||
29b9bde6 DV |
2635 | static void i9xx_update_primary_plane(struct drm_crtc *crtc, |
2636 | struct drm_framebuffer *fb, | |
2637 | int x, int y) | |
81255565 JB |
2638 | { |
2639 | struct drm_device *dev = crtc->dev; | |
2640 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2641 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
b70709a6 ML |
2642 | struct drm_plane *primary = crtc->primary; |
2643 | bool visible = to_intel_plane_state(primary->state)->visible; | |
c9ba6fad | 2644 | struct drm_i915_gem_object *obj; |
81255565 | 2645 | int plane = intel_crtc->plane; |
e506a0c6 | 2646 | unsigned long linear_offset; |
81255565 | 2647 | u32 dspcntr; |
f45651ba | 2648 | u32 reg = DSPCNTR(plane); |
48404c1e | 2649 | int pixel_size; |
f45651ba | 2650 | |
b70709a6 | 2651 | if (!visible || !fb) { |
fdd508a6 VS |
2652 | I915_WRITE(reg, 0); |
2653 | if (INTEL_INFO(dev)->gen >= 4) | |
2654 | I915_WRITE(DSPSURF(plane), 0); | |
2655 | else | |
2656 | I915_WRITE(DSPADDR(plane), 0); | |
2657 | POSTING_READ(reg); | |
2658 | return; | |
2659 | } | |
2660 | ||
c9ba6fad VS |
2661 | obj = intel_fb_obj(fb); |
2662 | if (WARN_ON(obj == NULL)) | |
2663 | return; | |
2664 | ||
2665 | pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); | |
2666 | ||
f45651ba VS |
2667 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
2668 | ||
fdd508a6 | 2669 | dspcntr |= DISPLAY_PLANE_ENABLE; |
f45651ba VS |
2670 | |
2671 | if (INTEL_INFO(dev)->gen < 4) { | |
2672 | if (intel_crtc->pipe == PIPE_B) | |
2673 | dspcntr |= DISPPLANE_SEL_PIPE_B; | |
2674 | ||
2675 | /* pipesrc and dspsize control the size that is scaled from, | |
2676 | * which should always be the user's requested size. | |
2677 | */ | |
2678 | I915_WRITE(DSPSIZE(plane), | |
6e3c9717 ACO |
2679 | ((intel_crtc->config->pipe_src_h - 1) << 16) | |
2680 | (intel_crtc->config->pipe_src_w - 1)); | |
f45651ba | 2681 | I915_WRITE(DSPPOS(plane), 0); |
c14b0485 VS |
2682 | } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) { |
2683 | I915_WRITE(PRIMSIZE(plane), | |
6e3c9717 ACO |
2684 | ((intel_crtc->config->pipe_src_h - 1) << 16) | |
2685 | (intel_crtc->config->pipe_src_w - 1)); | |
c14b0485 VS |
2686 | I915_WRITE(PRIMPOS(plane), 0); |
2687 | I915_WRITE(PRIMCNSTALPHA(plane), 0); | |
f45651ba | 2688 | } |
81255565 | 2689 | |
57779d06 VS |
2690 | switch (fb->pixel_format) { |
2691 | case DRM_FORMAT_C8: | |
81255565 JB |
2692 | dspcntr |= DISPPLANE_8BPP; |
2693 | break; | |
57779d06 | 2694 | case DRM_FORMAT_XRGB1555: |
57779d06 | 2695 | dspcntr |= DISPPLANE_BGRX555; |
81255565 | 2696 | break; |
57779d06 VS |
2697 | case DRM_FORMAT_RGB565: |
2698 | dspcntr |= DISPPLANE_BGRX565; | |
2699 | break; | |
2700 | case DRM_FORMAT_XRGB8888: | |
57779d06 VS |
2701 | dspcntr |= DISPPLANE_BGRX888; |
2702 | break; | |
2703 | case DRM_FORMAT_XBGR8888: | |
57779d06 VS |
2704 | dspcntr |= DISPPLANE_RGBX888; |
2705 | break; | |
2706 | case DRM_FORMAT_XRGB2101010: | |
57779d06 VS |
2707 | dspcntr |= DISPPLANE_BGRX101010; |
2708 | break; | |
2709 | case DRM_FORMAT_XBGR2101010: | |
57779d06 | 2710 | dspcntr |= DISPPLANE_RGBX101010; |
81255565 JB |
2711 | break; |
2712 | default: | |
baba133a | 2713 | BUG(); |
81255565 | 2714 | } |
57779d06 | 2715 | |
f45651ba VS |
2716 | if (INTEL_INFO(dev)->gen >= 4 && |
2717 | obj->tiling_mode != I915_TILING_NONE) | |
2718 | dspcntr |= DISPPLANE_TILED; | |
81255565 | 2719 | |
de1aa629 VS |
2720 | if (IS_G4X(dev)) |
2721 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; | |
2722 | ||
b9897127 | 2723 | linear_offset = y * fb->pitches[0] + x * pixel_size; |
81255565 | 2724 | |
c2c75131 DV |
2725 | if (INTEL_INFO(dev)->gen >= 4) { |
2726 | intel_crtc->dspaddr_offset = | |
bc752862 | 2727 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
b9897127 | 2728 | pixel_size, |
bc752862 | 2729 | fb->pitches[0]); |
c2c75131 DV |
2730 | linear_offset -= intel_crtc->dspaddr_offset; |
2731 | } else { | |
e506a0c6 | 2732 | intel_crtc->dspaddr_offset = linear_offset; |
c2c75131 | 2733 | } |
e506a0c6 | 2734 | |
8e7d688b | 2735 | if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) { |
48404c1e SJ |
2736 | dspcntr |= DISPPLANE_ROTATE_180; |
2737 | ||
6e3c9717 ACO |
2738 | x += (intel_crtc->config->pipe_src_w - 1); |
2739 | y += (intel_crtc->config->pipe_src_h - 1); | |
48404c1e SJ |
2740 | |
2741 | /* Finding the last pixel of the last line of the display | |
2742 | data and adding to linear_offset*/ | |
2743 | linear_offset += | |
6e3c9717 ACO |
2744 | (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] + |
2745 | (intel_crtc->config->pipe_src_w - 1) * pixel_size; | |
48404c1e SJ |
2746 | } |
2747 | ||
2748 | I915_WRITE(reg, dspcntr); | |
2749 | ||
01f2c773 | 2750 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
a6c45cf0 | 2751 | if (INTEL_INFO(dev)->gen >= 4) { |
85ba7b7d DV |
2752 | I915_WRITE(DSPSURF(plane), |
2753 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
5eddb70b | 2754 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
e506a0c6 | 2755 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
5eddb70b | 2756 | } else |
f343c5f6 | 2757 | I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset); |
5eddb70b | 2758 | POSTING_READ(reg); |
17638cd6 JB |
2759 | } |
2760 | ||
29b9bde6 DV |
2761 | static void ironlake_update_primary_plane(struct drm_crtc *crtc, |
2762 | struct drm_framebuffer *fb, | |
2763 | int x, int y) | |
17638cd6 JB |
2764 | { |
2765 | struct drm_device *dev = crtc->dev; | |
2766 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2767 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
b70709a6 ML |
2768 | struct drm_plane *primary = crtc->primary; |
2769 | bool visible = to_intel_plane_state(primary->state)->visible; | |
c9ba6fad | 2770 | struct drm_i915_gem_object *obj; |
17638cd6 | 2771 | int plane = intel_crtc->plane; |
e506a0c6 | 2772 | unsigned long linear_offset; |
17638cd6 | 2773 | u32 dspcntr; |
f45651ba | 2774 | u32 reg = DSPCNTR(plane); |
48404c1e | 2775 | int pixel_size; |
f45651ba | 2776 | |
b70709a6 | 2777 | if (!visible || !fb) { |
fdd508a6 VS |
2778 | I915_WRITE(reg, 0); |
2779 | I915_WRITE(DSPSURF(plane), 0); | |
2780 | POSTING_READ(reg); | |
2781 | return; | |
2782 | } | |
2783 | ||
c9ba6fad VS |
2784 | obj = intel_fb_obj(fb); |
2785 | if (WARN_ON(obj == NULL)) | |
2786 | return; | |
2787 | ||
2788 | pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); | |
2789 | ||
f45651ba VS |
2790 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
2791 | ||
fdd508a6 | 2792 | dspcntr |= DISPLAY_PLANE_ENABLE; |
f45651ba VS |
2793 | |
2794 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
2795 | dspcntr |= DISPPLANE_PIPE_CSC_ENABLE; | |
17638cd6 | 2796 | |
57779d06 VS |
2797 | switch (fb->pixel_format) { |
2798 | case DRM_FORMAT_C8: | |
17638cd6 JB |
2799 | dspcntr |= DISPPLANE_8BPP; |
2800 | break; | |
57779d06 VS |
2801 | case DRM_FORMAT_RGB565: |
2802 | dspcntr |= DISPPLANE_BGRX565; | |
17638cd6 | 2803 | break; |
57779d06 | 2804 | case DRM_FORMAT_XRGB8888: |
57779d06 VS |
2805 | dspcntr |= DISPPLANE_BGRX888; |
2806 | break; | |
2807 | case DRM_FORMAT_XBGR8888: | |
57779d06 VS |
2808 | dspcntr |= DISPPLANE_RGBX888; |
2809 | break; | |
2810 | case DRM_FORMAT_XRGB2101010: | |
57779d06 VS |
2811 | dspcntr |= DISPPLANE_BGRX101010; |
2812 | break; | |
2813 | case DRM_FORMAT_XBGR2101010: | |
57779d06 | 2814 | dspcntr |= DISPPLANE_RGBX101010; |
17638cd6 JB |
2815 | break; |
2816 | default: | |
baba133a | 2817 | BUG(); |
17638cd6 JB |
2818 | } |
2819 | ||
2820 | if (obj->tiling_mode != I915_TILING_NONE) | |
2821 | dspcntr |= DISPPLANE_TILED; | |
17638cd6 | 2822 | |
f45651ba | 2823 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) |
1f5d76db | 2824 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; |
17638cd6 | 2825 | |
b9897127 | 2826 | linear_offset = y * fb->pitches[0] + x * pixel_size; |
c2c75131 | 2827 | intel_crtc->dspaddr_offset = |
bc752862 | 2828 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
b9897127 | 2829 | pixel_size, |
bc752862 | 2830 | fb->pitches[0]); |
c2c75131 | 2831 | linear_offset -= intel_crtc->dspaddr_offset; |
8e7d688b | 2832 | if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) { |
48404c1e SJ |
2833 | dspcntr |= DISPPLANE_ROTATE_180; |
2834 | ||
2835 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) { | |
6e3c9717 ACO |
2836 | x += (intel_crtc->config->pipe_src_w - 1); |
2837 | y += (intel_crtc->config->pipe_src_h - 1); | |
48404c1e SJ |
2838 | |
2839 | /* Finding the last pixel of the last line of the display | |
2840 | data and adding to linear_offset*/ | |
2841 | linear_offset += | |
6e3c9717 ACO |
2842 | (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] + |
2843 | (intel_crtc->config->pipe_src_w - 1) * pixel_size; | |
48404c1e SJ |
2844 | } |
2845 | } | |
2846 | ||
2847 | I915_WRITE(reg, dspcntr); | |
17638cd6 | 2848 | |
01f2c773 | 2849 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
85ba7b7d DV |
2850 | I915_WRITE(DSPSURF(plane), |
2851 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
b3dc685e | 2852 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
bc1c91eb DL |
2853 | I915_WRITE(DSPOFFSET(plane), (y << 16) | x); |
2854 | } else { | |
2855 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); | |
2856 | I915_WRITE(DSPLINOFF(plane), linear_offset); | |
2857 | } | |
17638cd6 | 2858 | POSTING_READ(reg); |
17638cd6 JB |
2859 | } |
2860 | ||
b321803d DL |
2861 | u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier, |
2862 | uint32_t pixel_format) | |
2863 | { | |
2864 | u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8; | |
2865 | ||
2866 | /* | |
2867 | * The stride is either expressed as a multiple of 64 bytes | |
2868 | * chunks for linear buffers or in number of tiles for tiled | |
2869 | * buffers. | |
2870 | */ | |
2871 | switch (fb_modifier) { | |
2872 | case DRM_FORMAT_MOD_NONE: | |
2873 | return 64; | |
2874 | case I915_FORMAT_MOD_X_TILED: | |
2875 | if (INTEL_INFO(dev)->gen == 2) | |
2876 | return 128; | |
2877 | return 512; | |
2878 | case I915_FORMAT_MOD_Y_TILED: | |
2879 | /* No need to check for old gens and Y tiling since this is | |
2880 | * about the display engine and those will be blocked before | |
2881 | * we get here. | |
2882 | */ | |
2883 | return 128; | |
2884 | case I915_FORMAT_MOD_Yf_TILED: | |
2885 | if (bits_per_pixel == 8) | |
2886 | return 64; | |
2887 | else | |
2888 | return 128; | |
2889 | default: | |
2890 | MISSING_CASE(fb_modifier); | |
2891 | return 64; | |
2892 | } | |
2893 | } | |
2894 | ||
121920fa TU |
2895 | unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane, |
2896 | struct drm_i915_gem_object *obj) | |
2897 | { | |
9abc4648 | 2898 | const struct i915_ggtt_view *view = &i915_ggtt_view_normal; |
121920fa TU |
2899 | |
2900 | if (intel_rotation_90_or_270(intel_plane->base.state->rotation)) | |
9abc4648 | 2901 | view = &i915_ggtt_view_rotated; |
121920fa TU |
2902 | |
2903 | return i915_gem_obj_ggtt_offset_view(obj, view); | |
2904 | } | |
2905 | ||
a1b2278e CK |
2906 | /* |
2907 | * This function detaches (aka. unbinds) unused scalers in hardware | |
2908 | */ | |
2909 | void skl_detach_scalers(struct intel_crtc *intel_crtc) | |
2910 | { | |
2911 | struct drm_device *dev; | |
2912 | struct drm_i915_private *dev_priv; | |
2913 | struct intel_crtc_scaler_state *scaler_state; | |
2914 | int i; | |
2915 | ||
2916 | if (!intel_crtc || !intel_crtc->config) | |
2917 | return; | |
2918 | ||
2919 | dev = intel_crtc->base.dev; | |
2920 | dev_priv = dev->dev_private; | |
2921 | scaler_state = &intel_crtc->config->scaler_state; | |
2922 | ||
2923 | /* loop through and disable scalers that aren't in use */ | |
2924 | for (i = 0; i < intel_crtc->num_scalers; i++) { | |
2925 | if (!scaler_state->scalers[i].in_use) { | |
2926 | I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, i), 0); | |
2927 | I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, i), 0); | |
2928 | I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, i), 0); | |
2929 | DRM_DEBUG_KMS("CRTC:%d Disabled scaler id %u.%u\n", | |
2930 | intel_crtc->base.base.id, intel_crtc->pipe, i); | |
2931 | } | |
2932 | } | |
2933 | } | |
2934 | ||
6156a456 | 2935 | u32 skl_plane_ctl_format(uint32_t pixel_format) |
70d21f0e | 2936 | { |
6156a456 | 2937 | switch (pixel_format) { |
d161cf7a | 2938 | case DRM_FORMAT_C8: |
c34ce3d1 | 2939 | return PLANE_CTL_FORMAT_INDEXED; |
70d21f0e | 2940 | case DRM_FORMAT_RGB565: |
c34ce3d1 | 2941 | return PLANE_CTL_FORMAT_RGB_565; |
70d21f0e | 2942 | case DRM_FORMAT_XBGR8888: |
c34ce3d1 | 2943 | return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX; |
6156a456 | 2944 | case DRM_FORMAT_XRGB8888: |
c34ce3d1 | 2945 | return PLANE_CTL_FORMAT_XRGB_8888; |
6156a456 CK |
2946 | /* |
2947 | * XXX: For ARBG/ABGR formats we default to expecting scanout buffers | |
2948 | * to be already pre-multiplied. We need to add a knob (or a different | |
2949 | * DRM_FORMAT) for user-space to configure that. | |
2950 | */ | |
f75fb42a | 2951 | case DRM_FORMAT_ABGR8888: |
c34ce3d1 | 2952 | return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX | |
6156a456 | 2953 | PLANE_CTL_ALPHA_SW_PREMULTIPLY; |
6156a456 | 2954 | case DRM_FORMAT_ARGB8888: |
c34ce3d1 | 2955 | return PLANE_CTL_FORMAT_XRGB_8888 | |
6156a456 | 2956 | PLANE_CTL_ALPHA_SW_PREMULTIPLY; |
70d21f0e | 2957 | case DRM_FORMAT_XRGB2101010: |
c34ce3d1 | 2958 | return PLANE_CTL_FORMAT_XRGB_2101010; |
70d21f0e | 2959 | case DRM_FORMAT_XBGR2101010: |
c34ce3d1 | 2960 | return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010; |
6156a456 | 2961 | case DRM_FORMAT_YUYV: |
c34ce3d1 | 2962 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV; |
6156a456 | 2963 | case DRM_FORMAT_YVYU: |
c34ce3d1 | 2964 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU; |
6156a456 | 2965 | case DRM_FORMAT_UYVY: |
c34ce3d1 | 2966 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY; |
6156a456 | 2967 | case DRM_FORMAT_VYUY: |
c34ce3d1 | 2968 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY; |
70d21f0e | 2969 | default: |
4249eeef | 2970 | MISSING_CASE(pixel_format); |
70d21f0e | 2971 | } |
8cfcba41 | 2972 | |
c34ce3d1 | 2973 | return 0; |
6156a456 | 2974 | } |
70d21f0e | 2975 | |
6156a456 CK |
2976 | u32 skl_plane_ctl_tiling(uint64_t fb_modifier) |
2977 | { | |
6156a456 | 2978 | switch (fb_modifier) { |
30af77c4 | 2979 | case DRM_FORMAT_MOD_NONE: |
70d21f0e | 2980 | break; |
30af77c4 | 2981 | case I915_FORMAT_MOD_X_TILED: |
c34ce3d1 | 2982 | return PLANE_CTL_TILED_X; |
b321803d | 2983 | case I915_FORMAT_MOD_Y_TILED: |
c34ce3d1 | 2984 | return PLANE_CTL_TILED_Y; |
b321803d | 2985 | case I915_FORMAT_MOD_Yf_TILED: |
c34ce3d1 | 2986 | return PLANE_CTL_TILED_YF; |
70d21f0e | 2987 | default: |
6156a456 | 2988 | MISSING_CASE(fb_modifier); |
70d21f0e | 2989 | } |
8cfcba41 | 2990 | |
c34ce3d1 | 2991 | return 0; |
6156a456 | 2992 | } |
70d21f0e | 2993 | |
6156a456 CK |
2994 | u32 skl_plane_ctl_rotation(unsigned int rotation) |
2995 | { | |
3b7a5119 | 2996 | switch (rotation) { |
6156a456 CK |
2997 | case BIT(DRM_ROTATE_0): |
2998 | break; | |
1e8df167 SJ |
2999 | /* |
3000 | * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr | |
3001 | * while i915 HW rotation is clockwise, thats why this swapping. | |
3002 | */ | |
3b7a5119 | 3003 | case BIT(DRM_ROTATE_90): |
1e8df167 | 3004 | return PLANE_CTL_ROTATE_270; |
3b7a5119 | 3005 | case BIT(DRM_ROTATE_180): |
c34ce3d1 | 3006 | return PLANE_CTL_ROTATE_180; |
3b7a5119 | 3007 | case BIT(DRM_ROTATE_270): |
1e8df167 | 3008 | return PLANE_CTL_ROTATE_90; |
6156a456 CK |
3009 | default: |
3010 | MISSING_CASE(rotation); | |
3011 | } | |
3012 | ||
c34ce3d1 | 3013 | return 0; |
6156a456 CK |
3014 | } |
3015 | ||
3016 | static void skylake_update_primary_plane(struct drm_crtc *crtc, | |
3017 | struct drm_framebuffer *fb, | |
3018 | int x, int y) | |
3019 | { | |
3020 | struct drm_device *dev = crtc->dev; | |
3021 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3022 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
b70709a6 ML |
3023 | struct drm_plane *plane = crtc->primary; |
3024 | bool visible = to_intel_plane_state(plane->state)->visible; | |
6156a456 CK |
3025 | struct drm_i915_gem_object *obj; |
3026 | int pipe = intel_crtc->pipe; | |
3027 | u32 plane_ctl, stride_div, stride; | |
3028 | u32 tile_height, plane_offset, plane_size; | |
3029 | unsigned int rotation; | |
3030 | int x_offset, y_offset; | |
3031 | unsigned long surf_addr; | |
6156a456 CK |
3032 | struct intel_crtc_state *crtc_state = intel_crtc->config; |
3033 | struct intel_plane_state *plane_state; | |
3034 | int src_x = 0, src_y = 0, src_w = 0, src_h = 0; | |
3035 | int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0; | |
3036 | int scaler_id = -1; | |
3037 | ||
6156a456 CK |
3038 | plane_state = to_intel_plane_state(plane->state); |
3039 | ||
b70709a6 | 3040 | if (!visible || !fb) { |
6156a456 CK |
3041 | I915_WRITE(PLANE_CTL(pipe, 0), 0); |
3042 | I915_WRITE(PLANE_SURF(pipe, 0), 0); | |
3043 | POSTING_READ(PLANE_CTL(pipe, 0)); | |
3044 | return; | |
3b7a5119 | 3045 | } |
70d21f0e | 3046 | |
6156a456 CK |
3047 | plane_ctl = PLANE_CTL_ENABLE | |
3048 | PLANE_CTL_PIPE_GAMMA_ENABLE | | |
3049 | PLANE_CTL_PIPE_CSC_ENABLE; | |
3050 | ||
3051 | plane_ctl |= skl_plane_ctl_format(fb->pixel_format); | |
3052 | plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]); | |
3053 | plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE; | |
3054 | ||
3055 | rotation = plane->state->rotation; | |
3056 | plane_ctl |= skl_plane_ctl_rotation(rotation); | |
3057 | ||
b321803d DL |
3058 | obj = intel_fb_obj(fb); |
3059 | stride_div = intel_fb_stride_alignment(dev, fb->modifier[0], | |
3060 | fb->pixel_format); | |
3b7a5119 SJ |
3061 | surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj); |
3062 | ||
6156a456 CK |
3063 | /* |
3064 | * FIXME: intel_plane_state->src, dst aren't set when transitional | |
3065 | * update_plane helpers are called from legacy paths. | |
3066 | * Once full atomic crtc is available, below check can be avoided. | |
3067 | */ | |
3068 | if (drm_rect_width(&plane_state->src)) { | |
3069 | scaler_id = plane_state->scaler_id; | |
3070 | src_x = plane_state->src.x1 >> 16; | |
3071 | src_y = plane_state->src.y1 >> 16; | |
3072 | src_w = drm_rect_width(&plane_state->src) >> 16; | |
3073 | src_h = drm_rect_height(&plane_state->src) >> 16; | |
3074 | dst_x = plane_state->dst.x1; | |
3075 | dst_y = plane_state->dst.y1; | |
3076 | dst_w = drm_rect_width(&plane_state->dst); | |
3077 | dst_h = drm_rect_height(&plane_state->dst); | |
3078 | ||
3079 | WARN_ON(x != src_x || y != src_y); | |
3080 | } else { | |
3081 | src_w = intel_crtc->config->pipe_src_w; | |
3082 | src_h = intel_crtc->config->pipe_src_h; | |
3083 | } | |
3084 | ||
3b7a5119 SJ |
3085 | if (intel_rotation_90_or_270(rotation)) { |
3086 | /* stride = Surface height in tiles */ | |
2614f17d | 3087 | tile_height = intel_tile_height(dev, fb->pixel_format, |
3b7a5119 SJ |
3088 | fb->modifier[0]); |
3089 | stride = DIV_ROUND_UP(fb->height, tile_height); | |
6156a456 | 3090 | x_offset = stride * tile_height - y - src_h; |
3b7a5119 | 3091 | y_offset = x; |
6156a456 | 3092 | plane_size = (src_w - 1) << 16 | (src_h - 1); |
3b7a5119 SJ |
3093 | } else { |
3094 | stride = fb->pitches[0] / stride_div; | |
3095 | x_offset = x; | |
3096 | y_offset = y; | |
6156a456 | 3097 | plane_size = (src_h - 1) << 16 | (src_w - 1); |
3b7a5119 SJ |
3098 | } |
3099 | plane_offset = y_offset << 16 | x_offset; | |
b321803d | 3100 | |
70d21f0e | 3101 | I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl); |
3b7a5119 SJ |
3102 | I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset); |
3103 | I915_WRITE(PLANE_SIZE(pipe, 0), plane_size); | |
3104 | I915_WRITE(PLANE_STRIDE(pipe, 0), stride); | |
6156a456 CK |
3105 | |
3106 | if (scaler_id >= 0) { | |
3107 | uint32_t ps_ctrl = 0; | |
3108 | ||
3109 | WARN_ON(!dst_w || !dst_h); | |
3110 | ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) | | |
3111 | crtc_state->scaler_state.scalers[scaler_id].mode; | |
3112 | I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl); | |
3113 | I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0); | |
3114 | I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y); | |
3115 | I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h); | |
3116 | I915_WRITE(PLANE_POS(pipe, 0), 0); | |
3117 | } else { | |
3118 | I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x); | |
3119 | } | |
3120 | ||
121920fa | 3121 | I915_WRITE(PLANE_SURF(pipe, 0), surf_addr); |
70d21f0e DL |
3122 | |
3123 | POSTING_READ(PLANE_SURF(pipe, 0)); | |
3124 | } | |
3125 | ||
17638cd6 JB |
3126 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ |
3127 | static int | |
3128 | intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, | |
3129 | int x, int y, enum mode_set_atomic state) | |
3130 | { | |
3131 | struct drm_device *dev = crtc->dev; | |
3132 | struct drm_i915_private *dev_priv = dev->dev_private; | |
17638cd6 | 3133 | |
6b8e6ed0 CW |
3134 | if (dev_priv->display.disable_fbc) |
3135 | dev_priv->display.disable_fbc(dev); | |
81255565 | 3136 | |
29b9bde6 DV |
3137 | dev_priv->display.update_primary_plane(crtc, fb, x, y); |
3138 | ||
3139 | return 0; | |
81255565 JB |
3140 | } |
3141 | ||
7514747d | 3142 | static void intel_complete_page_flips(struct drm_device *dev) |
96a02917 | 3143 | { |
96a02917 VS |
3144 | struct drm_crtc *crtc; |
3145 | ||
70e1e0ec | 3146 | for_each_crtc(dev, crtc) { |
96a02917 VS |
3147 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3148 | enum plane plane = intel_crtc->plane; | |
3149 | ||
3150 | intel_prepare_page_flip(dev, plane); | |
3151 | intel_finish_page_flip_plane(dev, plane); | |
3152 | } | |
7514747d VS |
3153 | } |
3154 | ||
3155 | static void intel_update_primary_planes(struct drm_device *dev) | |
3156 | { | |
3157 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3158 | struct drm_crtc *crtc; | |
96a02917 | 3159 | |
70e1e0ec | 3160 | for_each_crtc(dev, crtc) { |
96a02917 VS |
3161 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3162 | ||
51fd371b | 3163 | drm_modeset_lock(&crtc->mutex, NULL); |
947fdaad CW |
3164 | /* |
3165 | * FIXME: Once we have proper support for primary planes (and | |
3166 | * disabling them without disabling the entire crtc) allow again | |
66e514c1 | 3167 | * a NULL crtc->primary->fb. |
947fdaad | 3168 | */ |
f4510a27 | 3169 | if (intel_crtc->active && crtc->primary->fb) |
262ca2b0 | 3170 | dev_priv->display.update_primary_plane(crtc, |
66e514c1 | 3171 | crtc->primary->fb, |
262ca2b0 MR |
3172 | crtc->x, |
3173 | crtc->y); | |
51fd371b | 3174 | drm_modeset_unlock(&crtc->mutex); |
96a02917 VS |
3175 | } |
3176 | } | |
3177 | ||
ce22dba9 ML |
3178 | void intel_crtc_reset(struct intel_crtc *crtc) |
3179 | { | |
3180 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
3181 | ||
3182 | if (!crtc->active) | |
3183 | return; | |
3184 | ||
3185 | intel_crtc_disable_planes(&crtc->base); | |
3186 | dev_priv->display.crtc_disable(&crtc->base); | |
3187 | dev_priv->display.crtc_enable(&crtc->base); | |
3188 | intel_crtc_enable_planes(&crtc->base); | |
3189 | } | |
3190 | ||
7514747d VS |
3191 | void intel_prepare_reset(struct drm_device *dev) |
3192 | { | |
f98ce92f VS |
3193 | struct drm_i915_private *dev_priv = to_i915(dev); |
3194 | struct intel_crtc *crtc; | |
3195 | ||
7514747d VS |
3196 | /* no reset support for gen2 */ |
3197 | if (IS_GEN2(dev)) | |
3198 | return; | |
3199 | ||
3200 | /* reset doesn't touch the display */ | |
3201 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) | |
3202 | return; | |
3203 | ||
3204 | drm_modeset_lock_all(dev); | |
f98ce92f VS |
3205 | |
3206 | /* | |
3207 | * Disabling the crtcs gracefully seems nicer. Also the | |
3208 | * g33 docs say we should at least disable all the planes. | |
3209 | */ | |
3210 | for_each_intel_crtc(dev, crtc) { | |
ce22dba9 ML |
3211 | if (!crtc->active) |
3212 | continue; | |
3213 | ||
3214 | intel_crtc_disable_planes(&crtc->base); | |
3215 | dev_priv->display.crtc_disable(&crtc->base); | |
f98ce92f | 3216 | } |
7514747d VS |
3217 | } |
3218 | ||
3219 | void intel_finish_reset(struct drm_device *dev) | |
3220 | { | |
3221 | struct drm_i915_private *dev_priv = to_i915(dev); | |
3222 | ||
3223 | /* | |
3224 | * Flips in the rings will be nuked by the reset, | |
3225 | * so complete all pending flips so that user space | |
3226 | * will get its events and not get stuck. | |
3227 | */ | |
3228 | intel_complete_page_flips(dev); | |
3229 | ||
3230 | /* no reset support for gen2 */ | |
3231 | if (IS_GEN2(dev)) | |
3232 | return; | |
3233 | ||
3234 | /* reset doesn't touch the display */ | |
3235 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) { | |
3236 | /* | |
3237 | * Flips in the rings have been nuked by the reset, | |
3238 | * so update the base address of all primary | |
3239 | * planes to the the last fb to make sure we're | |
3240 | * showing the correct fb after a reset. | |
3241 | */ | |
3242 | intel_update_primary_planes(dev); | |
3243 | return; | |
3244 | } | |
3245 | ||
3246 | /* | |
3247 | * The display has been reset as well, | |
3248 | * so need a full re-initialization. | |
3249 | */ | |
3250 | intel_runtime_pm_disable_interrupts(dev_priv); | |
3251 | intel_runtime_pm_enable_interrupts(dev_priv); | |
3252 | ||
3253 | intel_modeset_init_hw(dev); | |
3254 | ||
3255 | spin_lock_irq(&dev_priv->irq_lock); | |
3256 | if (dev_priv->display.hpd_irq_setup) | |
3257 | dev_priv->display.hpd_irq_setup(dev); | |
3258 | spin_unlock_irq(&dev_priv->irq_lock); | |
3259 | ||
3260 | intel_modeset_setup_hw_state(dev, true); | |
3261 | ||
3262 | intel_hpd_init(dev_priv); | |
3263 | ||
3264 | drm_modeset_unlock_all(dev); | |
3265 | } | |
3266 | ||
2e2f351d | 3267 | static void |
14667a4b CW |
3268 | intel_finish_fb(struct drm_framebuffer *old_fb) |
3269 | { | |
2ff8fde1 | 3270 | struct drm_i915_gem_object *obj = intel_fb_obj(old_fb); |
2e2f351d | 3271 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
14667a4b CW |
3272 | bool was_interruptible = dev_priv->mm.interruptible; |
3273 | int ret; | |
3274 | ||
14667a4b CW |
3275 | /* Big Hammer, we also need to ensure that any pending |
3276 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the | |
3277 | * current scanout is retired before unpinning the old | |
2e2f351d CW |
3278 | * framebuffer. Note that we rely on userspace rendering |
3279 | * into the buffer attached to the pipe they are waiting | |
3280 | * on. If not, userspace generates a GPU hang with IPEHR | |
3281 | * point to the MI_WAIT_FOR_EVENT. | |
14667a4b CW |
3282 | * |
3283 | * This should only fail upon a hung GPU, in which case we | |
3284 | * can safely continue. | |
3285 | */ | |
3286 | dev_priv->mm.interruptible = false; | |
2e2f351d | 3287 | ret = i915_gem_object_wait_rendering(obj, true); |
14667a4b CW |
3288 | dev_priv->mm.interruptible = was_interruptible; |
3289 | ||
2e2f351d | 3290 | WARN_ON(ret); |
14667a4b CW |
3291 | } |
3292 | ||
7d5e3799 CW |
3293 | static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) |
3294 | { | |
3295 | struct drm_device *dev = crtc->dev; | |
3296 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3297 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7d5e3799 CW |
3298 | bool pending; |
3299 | ||
3300 | if (i915_reset_in_progress(&dev_priv->gpu_error) || | |
3301 | intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) | |
3302 | return false; | |
3303 | ||
5e2d7afc | 3304 | spin_lock_irq(&dev->event_lock); |
7d5e3799 | 3305 | pending = to_intel_crtc(crtc)->unpin_work != NULL; |
5e2d7afc | 3306 | spin_unlock_irq(&dev->event_lock); |
7d5e3799 CW |
3307 | |
3308 | return pending; | |
3309 | } | |
3310 | ||
e30e8f75 GP |
3311 | static void intel_update_pipe_size(struct intel_crtc *crtc) |
3312 | { | |
3313 | struct drm_device *dev = crtc->base.dev; | |
3314 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3315 | const struct drm_display_mode *adjusted_mode; | |
3316 | ||
3317 | if (!i915.fastboot) | |
3318 | return; | |
3319 | ||
3320 | /* | |
3321 | * Update pipe size and adjust fitter if needed: the reason for this is | |
3322 | * that in compute_mode_changes we check the native mode (not the pfit | |
3323 | * mode) to see if we can flip rather than do a full mode set. In the | |
3324 | * fastboot case, we'll flip, but if we don't update the pipesrc and | |
3325 | * pfit state, we'll end up with a big fb scanned out into the wrong | |
3326 | * sized surface. | |
3327 | * | |
3328 | * To fix this properly, we need to hoist the checks up into | |
3329 | * compute_mode_changes (or above), check the actual pfit state and | |
3330 | * whether the platform allows pfit disable with pipe active, and only | |
3331 | * then update the pipesrc and pfit state, even on the flip path. | |
3332 | */ | |
3333 | ||
6e3c9717 | 3334 | adjusted_mode = &crtc->config->base.adjusted_mode; |
e30e8f75 GP |
3335 | |
3336 | I915_WRITE(PIPESRC(crtc->pipe), | |
3337 | ((adjusted_mode->crtc_hdisplay - 1) << 16) | | |
3338 | (adjusted_mode->crtc_vdisplay - 1)); | |
6e3c9717 | 3339 | if (!crtc->config->pch_pfit.enabled && |
409ee761 ACO |
3340 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || |
3341 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) { | |
e30e8f75 GP |
3342 | I915_WRITE(PF_CTL(crtc->pipe), 0); |
3343 | I915_WRITE(PF_WIN_POS(crtc->pipe), 0); | |
3344 | I915_WRITE(PF_WIN_SZ(crtc->pipe), 0); | |
3345 | } | |
6e3c9717 ACO |
3346 | crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay; |
3347 | crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay; | |
e30e8f75 GP |
3348 | } |
3349 | ||
5e84e1a4 ZW |
3350 | static void intel_fdi_normal_train(struct drm_crtc *crtc) |
3351 | { | |
3352 | struct drm_device *dev = crtc->dev; | |
3353 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3354 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3355 | int pipe = intel_crtc->pipe; | |
3356 | u32 reg, temp; | |
3357 | ||
3358 | /* enable normal train */ | |
3359 | reg = FDI_TX_CTL(pipe); | |
3360 | temp = I915_READ(reg); | |
61e499bf | 3361 | if (IS_IVYBRIDGE(dev)) { |
357555c0 JB |
3362 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3363 | temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; | |
61e499bf KP |
3364 | } else { |
3365 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3366 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; | |
357555c0 | 3367 | } |
5e84e1a4 ZW |
3368 | I915_WRITE(reg, temp); |
3369 | ||
3370 | reg = FDI_RX_CTL(pipe); | |
3371 | temp = I915_READ(reg); | |
3372 | if (HAS_PCH_CPT(dev)) { | |
3373 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3374 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; | |
3375 | } else { | |
3376 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3377 | temp |= FDI_LINK_TRAIN_NONE; | |
3378 | } | |
3379 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); | |
3380 | ||
3381 | /* wait one idle pattern time */ | |
3382 | POSTING_READ(reg); | |
3383 | udelay(1000); | |
357555c0 JB |
3384 | |
3385 | /* IVB wants error correction enabled */ | |
3386 | if (IS_IVYBRIDGE(dev)) | |
3387 | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | | |
3388 | FDI_FE_ERRC_ENABLE); | |
5e84e1a4 ZW |
3389 | } |
3390 | ||
8db9d77b ZW |
3391 | /* The FDI link training functions for ILK/Ibexpeak. */ |
3392 | static void ironlake_fdi_link_train(struct drm_crtc *crtc) | |
3393 | { | |
3394 | struct drm_device *dev = crtc->dev; | |
3395 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3396 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3397 | int pipe = intel_crtc->pipe; | |
5eddb70b | 3398 | u32 reg, temp, tries; |
8db9d77b | 3399 | |
1c8562f6 | 3400 | /* FDI needs bits from pipe first */ |
0fc932b8 | 3401 | assert_pipe_enabled(dev_priv, pipe); |
0fc932b8 | 3402 | |
e1a44743 AJ |
3403 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3404 | for train result */ | |
5eddb70b CW |
3405 | reg = FDI_RX_IMR(pipe); |
3406 | temp = I915_READ(reg); | |
e1a44743 AJ |
3407 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3408 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3409 | I915_WRITE(reg, temp); |
3410 | I915_READ(reg); | |
e1a44743 AJ |
3411 | udelay(150); |
3412 | ||
8db9d77b | 3413 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3414 | reg = FDI_TX_CTL(pipe); |
3415 | temp = I915_READ(reg); | |
627eb5a3 | 3416 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3417 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
8db9d77b ZW |
3418 | temp &= ~FDI_LINK_TRAIN_NONE; |
3419 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b | 3420 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3421 | |
5eddb70b CW |
3422 | reg = FDI_RX_CTL(pipe); |
3423 | temp = I915_READ(reg); | |
8db9d77b ZW |
3424 | temp &= ~FDI_LINK_TRAIN_NONE; |
3425 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b CW |
3426 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3427 | ||
3428 | POSTING_READ(reg); | |
8db9d77b ZW |
3429 | udelay(150); |
3430 | ||
5b2adf89 | 3431 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
8f5718a6 DV |
3432 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
3433 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | | |
3434 | FDI_RX_PHASE_SYNC_POINTER_EN); | |
5b2adf89 | 3435 | |
5eddb70b | 3436 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3437 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3438 | temp = I915_READ(reg); |
8db9d77b ZW |
3439 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3440 | ||
3441 | if ((temp & FDI_RX_BIT_LOCK)) { | |
3442 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
5eddb70b | 3443 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
8db9d77b ZW |
3444 | break; |
3445 | } | |
8db9d77b | 3446 | } |
e1a44743 | 3447 | if (tries == 5) |
5eddb70b | 3448 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3449 | |
3450 | /* Train 2 */ | |
5eddb70b CW |
3451 | reg = FDI_TX_CTL(pipe); |
3452 | temp = I915_READ(reg); | |
8db9d77b ZW |
3453 | temp &= ~FDI_LINK_TRAIN_NONE; |
3454 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3455 | I915_WRITE(reg, temp); |
8db9d77b | 3456 | |
5eddb70b CW |
3457 | reg = FDI_RX_CTL(pipe); |
3458 | temp = I915_READ(reg); | |
8db9d77b ZW |
3459 | temp &= ~FDI_LINK_TRAIN_NONE; |
3460 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3461 | I915_WRITE(reg, temp); |
8db9d77b | 3462 | |
5eddb70b CW |
3463 | POSTING_READ(reg); |
3464 | udelay(150); | |
8db9d77b | 3465 | |
5eddb70b | 3466 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3467 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3468 | temp = I915_READ(reg); |
8db9d77b ZW |
3469 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3470 | ||
3471 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
5eddb70b | 3472 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
8db9d77b ZW |
3473 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
3474 | break; | |
3475 | } | |
8db9d77b | 3476 | } |
e1a44743 | 3477 | if (tries == 5) |
5eddb70b | 3478 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3479 | |
3480 | DRM_DEBUG_KMS("FDI train done\n"); | |
5c5313c8 | 3481 | |
8db9d77b ZW |
3482 | } |
3483 | ||
0206e353 | 3484 | static const int snb_b_fdi_train_param[] = { |
8db9d77b ZW |
3485 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
3486 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, | |
3487 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, | |
3488 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, | |
3489 | }; | |
3490 | ||
3491 | /* The FDI link training functions for SNB/Cougarpoint. */ | |
3492 | static void gen6_fdi_link_train(struct drm_crtc *crtc) | |
3493 | { | |
3494 | struct drm_device *dev = crtc->dev; | |
3495 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3496 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3497 | int pipe = intel_crtc->pipe; | |
fa37d39e | 3498 | u32 reg, temp, i, retry; |
8db9d77b | 3499 | |
e1a44743 AJ |
3500 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3501 | for train result */ | |
5eddb70b CW |
3502 | reg = FDI_RX_IMR(pipe); |
3503 | temp = I915_READ(reg); | |
e1a44743 AJ |
3504 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3505 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3506 | I915_WRITE(reg, temp); |
3507 | ||
3508 | POSTING_READ(reg); | |
e1a44743 AJ |
3509 | udelay(150); |
3510 | ||
8db9d77b | 3511 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3512 | reg = FDI_TX_CTL(pipe); |
3513 | temp = I915_READ(reg); | |
627eb5a3 | 3514 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3515 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
8db9d77b ZW |
3516 | temp &= ~FDI_LINK_TRAIN_NONE; |
3517 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3518 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3519 | /* SNB-B */ | |
3520 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
5eddb70b | 3521 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3522 | |
d74cf324 DV |
3523 | I915_WRITE(FDI_RX_MISC(pipe), |
3524 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
3525 | ||
5eddb70b CW |
3526 | reg = FDI_RX_CTL(pipe); |
3527 | temp = I915_READ(reg); | |
8db9d77b ZW |
3528 | if (HAS_PCH_CPT(dev)) { |
3529 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3530 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3531 | } else { | |
3532 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3533 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3534 | } | |
5eddb70b CW |
3535 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3536 | ||
3537 | POSTING_READ(reg); | |
8db9d77b ZW |
3538 | udelay(150); |
3539 | ||
0206e353 | 3540 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3541 | reg = FDI_TX_CTL(pipe); |
3542 | temp = I915_READ(reg); | |
8db9d77b ZW |
3543 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3544 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3545 | I915_WRITE(reg, temp); |
3546 | ||
3547 | POSTING_READ(reg); | |
8db9d77b ZW |
3548 | udelay(500); |
3549 | ||
fa37d39e SP |
3550 | for (retry = 0; retry < 5; retry++) { |
3551 | reg = FDI_RX_IIR(pipe); | |
3552 | temp = I915_READ(reg); | |
3553 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3554 | if (temp & FDI_RX_BIT_LOCK) { | |
3555 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3556 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
3557 | break; | |
3558 | } | |
3559 | udelay(50); | |
8db9d77b | 3560 | } |
fa37d39e SP |
3561 | if (retry < 5) |
3562 | break; | |
8db9d77b ZW |
3563 | } |
3564 | if (i == 4) | |
5eddb70b | 3565 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3566 | |
3567 | /* Train 2 */ | |
5eddb70b CW |
3568 | reg = FDI_TX_CTL(pipe); |
3569 | temp = I915_READ(reg); | |
8db9d77b ZW |
3570 | temp &= ~FDI_LINK_TRAIN_NONE; |
3571 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3572 | if (IS_GEN6(dev)) { | |
3573 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3574 | /* SNB-B */ | |
3575 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
3576 | } | |
5eddb70b | 3577 | I915_WRITE(reg, temp); |
8db9d77b | 3578 | |
5eddb70b CW |
3579 | reg = FDI_RX_CTL(pipe); |
3580 | temp = I915_READ(reg); | |
8db9d77b ZW |
3581 | if (HAS_PCH_CPT(dev)) { |
3582 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3583 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
3584 | } else { | |
3585 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3586 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3587 | } | |
5eddb70b CW |
3588 | I915_WRITE(reg, temp); |
3589 | ||
3590 | POSTING_READ(reg); | |
8db9d77b ZW |
3591 | udelay(150); |
3592 | ||
0206e353 | 3593 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3594 | reg = FDI_TX_CTL(pipe); |
3595 | temp = I915_READ(reg); | |
8db9d77b ZW |
3596 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3597 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3598 | I915_WRITE(reg, temp); |
3599 | ||
3600 | POSTING_READ(reg); | |
8db9d77b ZW |
3601 | udelay(500); |
3602 | ||
fa37d39e SP |
3603 | for (retry = 0; retry < 5; retry++) { |
3604 | reg = FDI_RX_IIR(pipe); | |
3605 | temp = I915_READ(reg); | |
3606 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3607 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
3608 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3609 | DRM_DEBUG_KMS("FDI train 2 done.\n"); | |
3610 | break; | |
3611 | } | |
3612 | udelay(50); | |
8db9d77b | 3613 | } |
fa37d39e SP |
3614 | if (retry < 5) |
3615 | break; | |
8db9d77b ZW |
3616 | } |
3617 | if (i == 4) | |
5eddb70b | 3618 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3619 | |
3620 | DRM_DEBUG_KMS("FDI train done.\n"); | |
3621 | } | |
3622 | ||
357555c0 JB |
3623 | /* Manual link training for Ivy Bridge A0 parts */ |
3624 | static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) | |
3625 | { | |
3626 | struct drm_device *dev = crtc->dev; | |
3627 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3628 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3629 | int pipe = intel_crtc->pipe; | |
139ccd3f | 3630 | u32 reg, temp, i, j; |
357555c0 JB |
3631 | |
3632 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit | |
3633 | for train result */ | |
3634 | reg = FDI_RX_IMR(pipe); | |
3635 | temp = I915_READ(reg); | |
3636 | temp &= ~FDI_RX_SYMBOL_LOCK; | |
3637 | temp &= ~FDI_RX_BIT_LOCK; | |
3638 | I915_WRITE(reg, temp); | |
3639 | ||
3640 | POSTING_READ(reg); | |
3641 | udelay(150); | |
3642 | ||
01a415fd DV |
3643 | DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n", |
3644 | I915_READ(FDI_RX_IIR(pipe))); | |
3645 | ||
139ccd3f JB |
3646 | /* Try each vswing and preemphasis setting twice before moving on */ |
3647 | for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) { | |
3648 | /* disable first in case we need to retry */ | |
3649 | reg = FDI_TX_CTL(pipe); | |
3650 | temp = I915_READ(reg); | |
3651 | temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); | |
3652 | temp &= ~FDI_TX_ENABLE; | |
3653 | I915_WRITE(reg, temp); | |
357555c0 | 3654 | |
139ccd3f JB |
3655 | reg = FDI_RX_CTL(pipe); |
3656 | temp = I915_READ(reg); | |
3657 | temp &= ~FDI_LINK_TRAIN_AUTO; | |
3658 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3659 | temp &= ~FDI_RX_ENABLE; | |
3660 | I915_WRITE(reg, temp); | |
357555c0 | 3661 | |
139ccd3f | 3662 | /* enable CPU FDI TX and PCH FDI RX */ |
357555c0 JB |
3663 | reg = FDI_TX_CTL(pipe); |
3664 | temp = I915_READ(reg); | |
139ccd3f | 3665 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3666 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
139ccd3f | 3667 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; |
357555c0 | 3668 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
139ccd3f JB |
3669 | temp |= snb_b_fdi_train_param[j/2]; |
3670 | temp |= FDI_COMPOSITE_SYNC; | |
3671 | I915_WRITE(reg, temp | FDI_TX_ENABLE); | |
357555c0 | 3672 | |
139ccd3f JB |
3673 | I915_WRITE(FDI_RX_MISC(pipe), |
3674 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
357555c0 | 3675 | |
139ccd3f | 3676 | reg = FDI_RX_CTL(pipe); |
357555c0 | 3677 | temp = I915_READ(reg); |
139ccd3f JB |
3678 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
3679 | temp |= FDI_COMPOSITE_SYNC; | |
3680 | I915_WRITE(reg, temp | FDI_RX_ENABLE); | |
357555c0 | 3681 | |
139ccd3f JB |
3682 | POSTING_READ(reg); |
3683 | udelay(1); /* should be 0.5us */ | |
357555c0 | 3684 | |
139ccd3f JB |
3685 | for (i = 0; i < 4; i++) { |
3686 | reg = FDI_RX_IIR(pipe); | |
3687 | temp = I915_READ(reg); | |
3688 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 3689 | |
139ccd3f JB |
3690 | if (temp & FDI_RX_BIT_LOCK || |
3691 | (I915_READ(reg) & FDI_RX_BIT_LOCK)) { | |
3692 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3693 | DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", | |
3694 | i); | |
3695 | break; | |
3696 | } | |
3697 | udelay(1); /* should be 0.5us */ | |
3698 | } | |
3699 | if (i == 4) { | |
3700 | DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2); | |
3701 | continue; | |
3702 | } | |
357555c0 | 3703 | |
139ccd3f | 3704 | /* Train 2 */ |
357555c0 JB |
3705 | reg = FDI_TX_CTL(pipe); |
3706 | temp = I915_READ(reg); | |
139ccd3f JB |
3707 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3708 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; | |
3709 | I915_WRITE(reg, temp); | |
3710 | ||
3711 | reg = FDI_RX_CTL(pipe); | |
3712 | temp = I915_READ(reg); | |
3713 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3714 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
357555c0 JB |
3715 | I915_WRITE(reg, temp); |
3716 | ||
3717 | POSTING_READ(reg); | |
139ccd3f | 3718 | udelay(2); /* should be 1.5us */ |
357555c0 | 3719 | |
139ccd3f JB |
3720 | for (i = 0; i < 4; i++) { |
3721 | reg = FDI_RX_IIR(pipe); | |
3722 | temp = I915_READ(reg); | |
3723 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 3724 | |
139ccd3f JB |
3725 | if (temp & FDI_RX_SYMBOL_LOCK || |
3726 | (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) { | |
3727 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3728 | DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", | |
3729 | i); | |
3730 | goto train_done; | |
3731 | } | |
3732 | udelay(2); /* should be 1.5us */ | |
357555c0 | 3733 | } |
139ccd3f JB |
3734 | if (i == 4) |
3735 | DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2); | |
357555c0 | 3736 | } |
357555c0 | 3737 | |
139ccd3f | 3738 | train_done: |
357555c0 JB |
3739 | DRM_DEBUG_KMS("FDI train done.\n"); |
3740 | } | |
3741 | ||
88cefb6c | 3742 | static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) |
2c07245f | 3743 | { |
88cefb6c | 3744 | struct drm_device *dev = intel_crtc->base.dev; |
2c07245f | 3745 | struct drm_i915_private *dev_priv = dev->dev_private; |
2c07245f | 3746 | int pipe = intel_crtc->pipe; |
5eddb70b | 3747 | u32 reg, temp; |
79e53945 | 3748 | |
c64e311e | 3749 | |
c98e9dcf | 3750 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
5eddb70b CW |
3751 | reg = FDI_RX_CTL(pipe); |
3752 | temp = I915_READ(reg); | |
627eb5a3 | 3753 | temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16)); |
6e3c9717 | 3754 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
dfd07d72 | 3755 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
5eddb70b CW |
3756 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); |
3757 | ||
3758 | POSTING_READ(reg); | |
c98e9dcf JB |
3759 | udelay(200); |
3760 | ||
3761 | /* Switch from Rawclk to PCDclk */ | |
5eddb70b CW |
3762 | temp = I915_READ(reg); |
3763 | I915_WRITE(reg, temp | FDI_PCDCLK); | |
3764 | ||
3765 | POSTING_READ(reg); | |
c98e9dcf JB |
3766 | udelay(200); |
3767 | ||
20749730 PZ |
3768 | /* Enable CPU FDI TX PLL, always on for Ironlake */ |
3769 | reg = FDI_TX_CTL(pipe); | |
3770 | temp = I915_READ(reg); | |
3771 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { | |
3772 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); | |
5eddb70b | 3773 | |
20749730 PZ |
3774 | POSTING_READ(reg); |
3775 | udelay(100); | |
6be4a607 | 3776 | } |
0e23b99d JB |
3777 | } |
3778 | ||
88cefb6c DV |
3779 | static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc) |
3780 | { | |
3781 | struct drm_device *dev = intel_crtc->base.dev; | |
3782 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3783 | int pipe = intel_crtc->pipe; | |
3784 | u32 reg, temp; | |
3785 | ||
3786 | /* Switch from PCDclk to Rawclk */ | |
3787 | reg = FDI_RX_CTL(pipe); | |
3788 | temp = I915_READ(reg); | |
3789 | I915_WRITE(reg, temp & ~FDI_PCDCLK); | |
3790 | ||
3791 | /* Disable CPU FDI TX PLL */ | |
3792 | reg = FDI_TX_CTL(pipe); | |
3793 | temp = I915_READ(reg); | |
3794 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); | |
3795 | ||
3796 | POSTING_READ(reg); | |
3797 | udelay(100); | |
3798 | ||
3799 | reg = FDI_RX_CTL(pipe); | |
3800 | temp = I915_READ(reg); | |
3801 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); | |
3802 | ||
3803 | /* Wait for the clocks to turn off. */ | |
3804 | POSTING_READ(reg); | |
3805 | udelay(100); | |
3806 | } | |
3807 | ||
0fc932b8 JB |
3808 | static void ironlake_fdi_disable(struct drm_crtc *crtc) |
3809 | { | |
3810 | struct drm_device *dev = crtc->dev; | |
3811 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3812 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3813 | int pipe = intel_crtc->pipe; | |
3814 | u32 reg, temp; | |
3815 | ||
3816 | /* disable CPU FDI tx and PCH FDI rx */ | |
3817 | reg = FDI_TX_CTL(pipe); | |
3818 | temp = I915_READ(reg); | |
3819 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); | |
3820 | POSTING_READ(reg); | |
3821 | ||
3822 | reg = FDI_RX_CTL(pipe); | |
3823 | temp = I915_READ(reg); | |
3824 | temp &= ~(0x7 << 16); | |
dfd07d72 | 3825 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
3826 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); |
3827 | ||
3828 | POSTING_READ(reg); | |
3829 | udelay(100); | |
3830 | ||
3831 | /* Ironlake workaround, disable clock pointer after downing FDI */ | |
eba905b2 | 3832 | if (HAS_PCH_IBX(dev)) |
6f06ce18 | 3833 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
0fc932b8 JB |
3834 | |
3835 | /* still set train pattern 1 */ | |
3836 | reg = FDI_TX_CTL(pipe); | |
3837 | temp = I915_READ(reg); | |
3838 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3839 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3840 | I915_WRITE(reg, temp); | |
3841 | ||
3842 | reg = FDI_RX_CTL(pipe); | |
3843 | temp = I915_READ(reg); | |
3844 | if (HAS_PCH_CPT(dev)) { | |
3845 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3846 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3847 | } else { | |
3848 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3849 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3850 | } | |
3851 | /* BPC in FDI rx is consistent with that in PIPECONF */ | |
3852 | temp &= ~(0x07 << 16); | |
dfd07d72 | 3853 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
3854 | I915_WRITE(reg, temp); |
3855 | ||
3856 | POSTING_READ(reg); | |
3857 | udelay(100); | |
3858 | } | |
3859 | ||
5dce5b93 CW |
3860 | bool intel_has_pending_fb_unpin(struct drm_device *dev) |
3861 | { | |
3862 | struct intel_crtc *crtc; | |
3863 | ||
3864 | /* Note that we don't need to be called with mode_config.lock here | |
3865 | * as our list of CRTC objects is static for the lifetime of the | |
3866 | * device and so cannot disappear as we iterate. Similarly, we can | |
3867 | * happily treat the predicates as racy, atomic checks as userspace | |
3868 | * cannot claim and pin a new fb without at least acquring the | |
3869 | * struct_mutex and so serialising with us. | |
3870 | */ | |
d3fcc808 | 3871 | for_each_intel_crtc(dev, crtc) { |
5dce5b93 CW |
3872 | if (atomic_read(&crtc->unpin_work_count) == 0) |
3873 | continue; | |
3874 | ||
3875 | if (crtc->unpin_work) | |
3876 | intel_wait_for_vblank(dev, crtc->pipe); | |
3877 | ||
3878 | return true; | |
3879 | } | |
3880 | ||
3881 | return false; | |
3882 | } | |
3883 | ||
d6bbafa1 CW |
3884 | static void page_flip_completed(struct intel_crtc *intel_crtc) |
3885 | { | |
3886 | struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); | |
3887 | struct intel_unpin_work *work = intel_crtc->unpin_work; | |
3888 | ||
3889 | /* ensure that the unpin work is consistent wrt ->pending. */ | |
3890 | smp_rmb(); | |
3891 | intel_crtc->unpin_work = NULL; | |
3892 | ||
3893 | if (work->event) | |
3894 | drm_send_vblank_event(intel_crtc->base.dev, | |
3895 | intel_crtc->pipe, | |
3896 | work->event); | |
3897 | ||
3898 | drm_crtc_vblank_put(&intel_crtc->base); | |
3899 | ||
3900 | wake_up_all(&dev_priv->pending_flip_queue); | |
3901 | queue_work(dev_priv->wq, &work->work); | |
3902 | ||
3903 | trace_i915_flip_complete(intel_crtc->plane, | |
3904 | work->pending_flip_obj); | |
3905 | } | |
3906 | ||
46a55d30 | 3907 | void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) |
e6c3a2a6 | 3908 | { |
0f91128d | 3909 | struct drm_device *dev = crtc->dev; |
5bb61643 | 3910 | struct drm_i915_private *dev_priv = dev->dev_private; |
e6c3a2a6 | 3911 | |
2c10d571 | 3912 | WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue)); |
9c787942 CW |
3913 | if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue, |
3914 | !intel_crtc_has_pending_flip(crtc), | |
3915 | 60*HZ) == 0)) { | |
3916 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2c10d571 | 3917 | |
5e2d7afc | 3918 | spin_lock_irq(&dev->event_lock); |
9c787942 CW |
3919 | if (intel_crtc->unpin_work) { |
3920 | WARN_ONCE(1, "Removing stuck page flip\n"); | |
3921 | page_flip_completed(intel_crtc); | |
3922 | } | |
5e2d7afc | 3923 | spin_unlock_irq(&dev->event_lock); |
9c787942 | 3924 | } |
5bb61643 | 3925 | |
975d568a CW |
3926 | if (crtc->primary->fb) { |
3927 | mutex_lock(&dev->struct_mutex); | |
3928 | intel_finish_fb(crtc->primary->fb); | |
3929 | mutex_unlock(&dev->struct_mutex); | |
3930 | } | |
e6c3a2a6 CW |
3931 | } |
3932 | ||
e615efe4 ED |
3933 | /* Program iCLKIP clock to the desired frequency */ |
3934 | static void lpt_program_iclkip(struct drm_crtc *crtc) | |
3935 | { | |
3936 | struct drm_device *dev = crtc->dev; | |
3937 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6e3c9717 | 3938 | int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock; |
e615efe4 ED |
3939 | u32 divsel, phaseinc, auxdiv, phasedir = 0; |
3940 | u32 temp; | |
3941 | ||
a580516d | 3942 | mutex_lock(&dev_priv->sb_lock); |
09153000 | 3943 | |
e615efe4 ED |
3944 | /* It is necessary to ungate the pixclk gate prior to programming |
3945 | * the divisors, and gate it back when it is done. | |
3946 | */ | |
3947 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE); | |
3948 | ||
3949 | /* Disable SSCCTL */ | |
3950 | intel_sbi_write(dev_priv, SBI_SSCCTL6, | |
988d6ee8 PZ |
3951 | intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) | |
3952 | SBI_SSCCTL_DISABLE, | |
3953 | SBI_ICLK); | |
e615efe4 ED |
3954 | |
3955 | /* 20MHz is a corner case which is out of range for the 7-bit divisor */ | |
12d7ceed | 3956 | if (clock == 20000) { |
e615efe4 ED |
3957 | auxdiv = 1; |
3958 | divsel = 0x41; | |
3959 | phaseinc = 0x20; | |
3960 | } else { | |
3961 | /* The iCLK virtual clock root frequency is in MHz, | |
241bfc38 DL |
3962 | * but the adjusted_mode->crtc_clock in in KHz. To get the |
3963 | * divisors, it is necessary to divide one by another, so we | |
e615efe4 ED |
3964 | * convert the virtual clock precision to KHz here for higher |
3965 | * precision. | |
3966 | */ | |
3967 | u32 iclk_virtual_root_freq = 172800 * 1000; | |
3968 | u32 iclk_pi_range = 64; | |
3969 | u32 desired_divisor, msb_divisor_value, pi_value; | |
3970 | ||
12d7ceed | 3971 | desired_divisor = (iclk_virtual_root_freq / clock); |
e615efe4 ED |
3972 | msb_divisor_value = desired_divisor / iclk_pi_range; |
3973 | pi_value = desired_divisor % iclk_pi_range; | |
3974 | ||
3975 | auxdiv = 0; | |
3976 | divsel = msb_divisor_value - 2; | |
3977 | phaseinc = pi_value; | |
3978 | } | |
3979 | ||
3980 | /* This should not happen with any sane values */ | |
3981 | WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) & | |
3982 | ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); | |
3983 | WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) & | |
3984 | ~SBI_SSCDIVINTPHASE_INCVAL_MASK); | |
3985 | ||
3986 | DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", | |
12d7ceed | 3987 | clock, |
e615efe4 ED |
3988 | auxdiv, |
3989 | divsel, | |
3990 | phasedir, | |
3991 | phaseinc); | |
3992 | ||
3993 | /* Program SSCDIVINTPHASE6 */ | |
988d6ee8 | 3994 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); |
e615efe4 ED |
3995 | temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK; |
3996 | temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); | |
3997 | temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK; | |
3998 | temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc); | |
3999 | temp |= SBI_SSCDIVINTPHASE_DIR(phasedir); | |
4000 | temp |= SBI_SSCDIVINTPHASE_PROPAGATE; | |
988d6ee8 | 4001 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK); |
e615efe4 ED |
4002 | |
4003 | /* Program SSCAUXDIV */ | |
988d6ee8 | 4004 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); |
e615efe4 ED |
4005 | temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1); |
4006 | temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv); | |
988d6ee8 | 4007 | intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK); |
e615efe4 ED |
4008 | |
4009 | /* Enable modulator and associated divider */ | |
988d6ee8 | 4010 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); |
e615efe4 | 4011 | temp &= ~SBI_SSCCTL_DISABLE; |
988d6ee8 | 4012 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); |
e615efe4 ED |
4013 | |
4014 | /* Wait for initialization time */ | |
4015 | udelay(24); | |
4016 | ||
4017 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE); | |
09153000 | 4018 | |
a580516d | 4019 | mutex_unlock(&dev_priv->sb_lock); |
e615efe4 ED |
4020 | } |
4021 | ||
275f01b2 DV |
4022 | static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc, |
4023 | enum pipe pch_transcoder) | |
4024 | { | |
4025 | struct drm_device *dev = crtc->base.dev; | |
4026 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6e3c9717 | 4027 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
275f01b2 DV |
4028 | |
4029 | I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder), | |
4030 | I915_READ(HTOTAL(cpu_transcoder))); | |
4031 | I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder), | |
4032 | I915_READ(HBLANK(cpu_transcoder))); | |
4033 | I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder), | |
4034 | I915_READ(HSYNC(cpu_transcoder))); | |
4035 | ||
4036 | I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder), | |
4037 | I915_READ(VTOTAL(cpu_transcoder))); | |
4038 | I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder), | |
4039 | I915_READ(VBLANK(cpu_transcoder))); | |
4040 | I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder), | |
4041 | I915_READ(VSYNC(cpu_transcoder))); | |
4042 | I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder), | |
4043 | I915_READ(VSYNCSHIFT(cpu_transcoder))); | |
4044 | } | |
4045 | ||
003632d9 | 4046 | static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable) |
1fbc0d78 DV |
4047 | { |
4048 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4049 | uint32_t temp; | |
4050 | ||
4051 | temp = I915_READ(SOUTH_CHICKEN1); | |
003632d9 | 4052 | if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable) |
1fbc0d78 DV |
4053 | return; |
4054 | ||
4055 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); | |
4056 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
4057 | ||
003632d9 ACO |
4058 | temp &= ~FDI_BC_BIFURCATION_SELECT; |
4059 | if (enable) | |
4060 | temp |= FDI_BC_BIFURCATION_SELECT; | |
4061 | ||
4062 | DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis"); | |
1fbc0d78 DV |
4063 | I915_WRITE(SOUTH_CHICKEN1, temp); |
4064 | POSTING_READ(SOUTH_CHICKEN1); | |
4065 | } | |
4066 | ||
4067 | static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc) | |
4068 | { | |
4069 | struct drm_device *dev = intel_crtc->base.dev; | |
1fbc0d78 DV |
4070 | |
4071 | switch (intel_crtc->pipe) { | |
4072 | case PIPE_A: | |
4073 | break; | |
4074 | case PIPE_B: | |
6e3c9717 | 4075 | if (intel_crtc->config->fdi_lanes > 2) |
003632d9 | 4076 | cpt_set_fdi_bc_bifurcation(dev, false); |
1fbc0d78 | 4077 | else |
003632d9 | 4078 | cpt_set_fdi_bc_bifurcation(dev, true); |
1fbc0d78 DV |
4079 | |
4080 | break; | |
4081 | case PIPE_C: | |
003632d9 | 4082 | cpt_set_fdi_bc_bifurcation(dev, true); |
1fbc0d78 DV |
4083 | |
4084 | break; | |
4085 | default: | |
4086 | BUG(); | |
4087 | } | |
4088 | } | |
4089 | ||
f67a559d JB |
4090 | /* |
4091 | * Enable PCH resources required for PCH ports: | |
4092 | * - PCH PLLs | |
4093 | * - FDI training & RX/TX | |
4094 | * - update transcoder timings | |
4095 | * - DP transcoding bits | |
4096 | * - transcoder | |
4097 | */ | |
4098 | static void ironlake_pch_enable(struct drm_crtc *crtc) | |
0e23b99d JB |
4099 | { |
4100 | struct drm_device *dev = crtc->dev; | |
4101 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4102 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4103 | int pipe = intel_crtc->pipe; | |
ee7b9f93 | 4104 | u32 reg, temp; |
2c07245f | 4105 | |
ab9412ba | 4106 | assert_pch_transcoder_disabled(dev_priv, pipe); |
e7e164db | 4107 | |
1fbc0d78 DV |
4108 | if (IS_IVYBRIDGE(dev)) |
4109 | ivybridge_update_fdi_bc_bifurcation(intel_crtc); | |
4110 | ||
cd986abb DV |
4111 | /* Write the TU size bits before fdi link training, so that error |
4112 | * detection works. */ | |
4113 | I915_WRITE(FDI_RX_TUSIZE1(pipe), | |
4114 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); | |
4115 | ||
c98e9dcf | 4116 | /* For PCH output, training FDI link */ |
674cf967 | 4117 | dev_priv->display.fdi_link_train(crtc); |
2c07245f | 4118 | |
3ad8a208 DV |
4119 | /* We need to program the right clock selection before writing the pixel |
4120 | * mutliplier into the DPLL. */ | |
303b81e0 | 4121 | if (HAS_PCH_CPT(dev)) { |
ee7b9f93 | 4122 | u32 sel; |
4b645f14 | 4123 | |
c98e9dcf | 4124 | temp = I915_READ(PCH_DPLL_SEL); |
11887397 DV |
4125 | temp |= TRANS_DPLL_ENABLE(pipe); |
4126 | sel = TRANS_DPLLB_SEL(pipe); | |
6e3c9717 | 4127 | if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B) |
ee7b9f93 JB |
4128 | temp |= sel; |
4129 | else | |
4130 | temp &= ~sel; | |
c98e9dcf | 4131 | I915_WRITE(PCH_DPLL_SEL, temp); |
c98e9dcf | 4132 | } |
5eddb70b | 4133 | |
3ad8a208 DV |
4134 | /* XXX: pch pll's can be enabled any time before we enable the PCH |
4135 | * transcoder, and we actually should do this to not upset any PCH | |
4136 | * transcoder that already use the clock when we share it. | |
4137 | * | |
4138 | * Note that enable_shared_dpll tries to do the right thing, but | |
4139 | * get_shared_dpll unconditionally resets the pll - we need that to have | |
4140 | * the right LVDS enable sequence. */ | |
85b3894f | 4141 | intel_enable_shared_dpll(intel_crtc); |
3ad8a208 | 4142 | |
d9b6cb56 JB |
4143 | /* set transcoder timing, panel must allow it */ |
4144 | assert_panel_unlocked(dev_priv, pipe); | |
275f01b2 | 4145 | ironlake_pch_transcoder_set_timings(intel_crtc, pipe); |
8db9d77b | 4146 | |
303b81e0 | 4147 | intel_fdi_normal_train(crtc); |
5e84e1a4 | 4148 | |
c98e9dcf | 4149 | /* For PCH DP, enable TRANS_DP_CTL */ |
6e3c9717 | 4150 | if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) { |
dfd07d72 | 4151 | u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; |
5eddb70b CW |
4152 | reg = TRANS_DP_CTL(pipe); |
4153 | temp = I915_READ(reg); | |
4154 | temp &= ~(TRANS_DP_PORT_SEL_MASK | | |
220cad3c EA |
4155 | TRANS_DP_SYNC_MASK | |
4156 | TRANS_DP_BPC_MASK); | |
e3ef4479 | 4157 | temp |= TRANS_DP_OUTPUT_ENABLE; |
9325c9f0 | 4158 | temp |= bpc << 9; /* same format but at 11:9 */ |
c98e9dcf JB |
4159 | |
4160 | if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC) | |
5eddb70b | 4161 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
c98e9dcf | 4162 | if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC) |
5eddb70b | 4163 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
c98e9dcf JB |
4164 | |
4165 | switch (intel_trans_dp_port_sel(crtc)) { | |
4166 | case PCH_DP_B: | |
5eddb70b | 4167 | temp |= TRANS_DP_PORT_SEL_B; |
c98e9dcf JB |
4168 | break; |
4169 | case PCH_DP_C: | |
5eddb70b | 4170 | temp |= TRANS_DP_PORT_SEL_C; |
c98e9dcf JB |
4171 | break; |
4172 | case PCH_DP_D: | |
5eddb70b | 4173 | temp |= TRANS_DP_PORT_SEL_D; |
c98e9dcf JB |
4174 | break; |
4175 | default: | |
e95d41e1 | 4176 | BUG(); |
32f9d658 | 4177 | } |
2c07245f | 4178 | |
5eddb70b | 4179 | I915_WRITE(reg, temp); |
6be4a607 | 4180 | } |
b52eb4dc | 4181 | |
b8a4f404 | 4182 | ironlake_enable_pch_transcoder(dev_priv, pipe); |
f67a559d JB |
4183 | } |
4184 | ||
1507e5bd PZ |
4185 | static void lpt_pch_enable(struct drm_crtc *crtc) |
4186 | { | |
4187 | struct drm_device *dev = crtc->dev; | |
4188 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4189 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6e3c9717 | 4190 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
1507e5bd | 4191 | |
ab9412ba | 4192 | assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A); |
1507e5bd | 4193 | |
8c52b5e8 | 4194 | lpt_program_iclkip(crtc); |
1507e5bd | 4195 | |
0540e488 | 4196 | /* Set transcoder timing. */ |
275f01b2 | 4197 | ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A); |
1507e5bd | 4198 | |
937bb610 | 4199 | lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); |
f67a559d JB |
4200 | } |
4201 | ||
716c2e55 | 4202 | void intel_put_shared_dpll(struct intel_crtc *crtc) |
ee7b9f93 | 4203 | { |
e2b78267 | 4204 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
ee7b9f93 JB |
4205 | |
4206 | if (pll == NULL) | |
4207 | return; | |
4208 | ||
3e369b76 | 4209 | if (!(pll->config.crtc_mask & (1 << crtc->pipe))) { |
1e6f2ddc | 4210 | WARN(1, "bad %s crtc mask\n", pll->name); |
ee7b9f93 JB |
4211 | return; |
4212 | } | |
4213 | ||
3e369b76 ACO |
4214 | pll->config.crtc_mask &= ~(1 << crtc->pipe); |
4215 | if (pll->config.crtc_mask == 0) { | |
f4a091c7 DV |
4216 | WARN_ON(pll->on); |
4217 | WARN_ON(pll->active); | |
4218 | } | |
4219 | ||
6e3c9717 | 4220 | crtc->config->shared_dpll = DPLL_ID_PRIVATE; |
ee7b9f93 JB |
4221 | } |
4222 | ||
190f68c5 ACO |
4223 | struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc, |
4224 | struct intel_crtc_state *crtc_state) | |
ee7b9f93 | 4225 | { |
e2b78267 | 4226 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
8bd31e67 | 4227 | struct intel_shared_dpll *pll; |
e2b78267 | 4228 | enum intel_dpll_id i; |
ee7b9f93 | 4229 | |
98b6bd99 DV |
4230 | if (HAS_PCH_IBX(dev_priv->dev)) { |
4231 | /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */ | |
d94ab068 | 4232 | i = (enum intel_dpll_id) crtc->pipe; |
e72f9fbf | 4233 | pll = &dev_priv->shared_dplls[i]; |
98b6bd99 | 4234 | |
46edb027 DV |
4235 | DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n", |
4236 | crtc->base.base.id, pll->name); | |
98b6bd99 | 4237 | |
8bd31e67 | 4238 | WARN_ON(pll->new_config->crtc_mask); |
f2a69f44 | 4239 | |
98b6bd99 DV |
4240 | goto found; |
4241 | } | |
4242 | ||
bcddf610 S |
4243 | if (IS_BROXTON(dev_priv->dev)) { |
4244 | /* PLL is attached to port in bxt */ | |
4245 | struct intel_encoder *encoder; | |
4246 | struct intel_digital_port *intel_dig_port; | |
4247 | ||
4248 | encoder = intel_ddi_get_crtc_new_encoder(crtc_state); | |
4249 | if (WARN_ON(!encoder)) | |
4250 | return NULL; | |
4251 | ||
4252 | intel_dig_port = enc_to_dig_port(&encoder->base); | |
4253 | /* 1:1 mapping between ports and PLLs */ | |
4254 | i = (enum intel_dpll_id)intel_dig_port->port; | |
4255 | pll = &dev_priv->shared_dplls[i]; | |
4256 | DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n", | |
4257 | crtc->base.base.id, pll->name); | |
4258 | WARN_ON(pll->new_config->crtc_mask); | |
4259 | ||
4260 | goto found; | |
4261 | } | |
4262 | ||
e72f9fbf DV |
4263 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
4264 | pll = &dev_priv->shared_dplls[i]; | |
ee7b9f93 JB |
4265 | |
4266 | /* Only want to check enabled timings first */ | |
8bd31e67 | 4267 | if (pll->new_config->crtc_mask == 0) |
ee7b9f93 JB |
4268 | continue; |
4269 | ||
190f68c5 | 4270 | if (memcmp(&crtc_state->dpll_hw_state, |
8bd31e67 ACO |
4271 | &pll->new_config->hw_state, |
4272 | sizeof(pll->new_config->hw_state)) == 0) { | |
4273 | DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n", | |
1e6f2ddc | 4274 | crtc->base.base.id, pll->name, |
8bd31e67 ACO |
4275 | pll->new_config->crtc_mask, |
4276 | pll->active); | |
ee7b9f93 JB |
4277 | goto found; |
4278 | } | |
4279 | } | |
4280 | ||
4281 | /* Ok no matching timings, maybe there's a free one? */ | |
e72f9fbf DV |
4282 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
4283 | pll = &dev_priv->shared_dplls[i]; | |
8bd31e67 | 4284 | if (pll->new_config->crtc_mask == 0) { |
46edb027 DV |
4285 | DRM_DEBUG_KMS("CRTC:%d allocated %s\n", |
4286 | crtc->base.base.id, pll->name); | |
ee7b9f93 JB |
4287 | goto found; |
4288 | } | |
4289 | } | |
4290 | ||
4291 | return NULL; | |
4292 | ||
4293 | found: | |
8bd31e67 | 4294 | if (pll->new_config->crtc_mask == 0) |
190f68c5 | 4295 | pll->new_config->hw_state = crtc_state->dpll_hw_state; |
f2a69f44 | 4296 | |
190f68c5 | 4297 | crtc_state->shared_dpll = i; |
46edb027 DV |
4298 | DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name, |
4299 | pipe_name(crtc->pipe)); | |
ee7b9f93 | 4300 | |
8bd31e67 | 4301 | pll->new_config->crtc_mask |= 1 << crtc->pipe; |
e04c7350 | 4302 | |
ee7b9f93 JB |
4303 | return pll; |
4304 | } | |
4305 | ||
8bd31e67 ACO |
4306 | /** |
4307 | * intel_shared_dpll_start_config - start a new PLL staged config | |
4308 | * @dev_priv: DRM device | |
4309 | * @clear_pipes: mask of pipes that will have their PLLs freed | |
4310 | * | |
4311 | * Starts a new PLL staged config, copying the current config but | |
4312 | * releasing the references of pipes specified in clear_pipes. | |
4313 | */ | |
4314 | static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv, | |
4315 | unsigned clear_pipes) | |
4316 | { | |
4317 | struct intel_shared_dpll *pll; | |
4318 | enum intel_dpll_id i; | |
4319 | ||
4320 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
4321 | pll = &dev_priv->shared_dplls[i]; | |
4322 | ||
4323 | pll->new_config = kmemdup(&pll->config, sizeof pll->config, | |
4324 | GFP_KERNEL); | |
4325 | if (!pll->new_config) | |
4326 | goto cleanup; | |
4327 | ||
4328 | pll->new_config->crtc_mask &= ~clear_pipes; | |
4329 | } | |
4330 | ||
4331 | return 0; | |
4332 | ||
4333 | cleanup: | |
4334 | while (--i >= 0) { | |
4335 | pll = &dev_priv->shared_dplls[i]; | |
f354d733 | 4336 | kfree(pll->new_config); |
8bd31e67 ACO |
4337 | pll->new_config = NULL; |
4338 | } | |
4339 | ||
4340 | return -ENOMEM; | |
4341 | } | |
4342 | ||
4343 | static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv) | |
4344 | { | |
4345 | struct intel_shared_dpll *pll; | |
4346 | enum intel_dpll_id i; | |
4347 | ||
4348 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
4349 | pll = &dev_priv->shared_dplls[i]; | |
4350 | ||
4351 | WARN_ON(pll->new_config == &pll->config); | |
4352 | ||
4353 | pll->config = *pll->new_config; | |
4354 | kfree(pll->new_config); | |
4355 | pll->new_config = NULL; | |
4356 | } | |
4357 | } | |
4358 | ||
4359 | static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv) | |
4360 | { | |
4361 | struct intel_shared_dpll *pll; | |
4362 | enum intel_dpll_id i; | |
4363 | ||
4364 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
4365 | pll = &dev_priv->shared_dplls[i]; | |
4366 | ||
4367 | WARN_ON(pll->new_config == &pll->config); | |
4368 | ||
4369 | kfree(pll->new_config); | |
4370 | pll->new_config = NULL; | |
4371 | } | |
4372 | } | |
4373 | ||
a1520318 | 4374 | static void cpt_verify_modeset(struct drm_device *dev, int pipe) |
d4270e57 JB |
4375 | { |
4376 | struct drm_i915_private *dev_priv = dev->dev_private; | |
23670b32 | 4377 | int dslreg = PIPEDSL(pipe); |
d4270e57 JB |
4378 | u32 temp; |
4379 | ||
4380 | temp = I915_READ(dslreg); | |
4381 | udelay(500); | |
4382 | if (wait_for(I915_READ(dslreg) != temp, 5)) { | |
d4270e57 | 4383 | if (wait_for(I915_READ(dslreg) != temp, 5)) |
84f44ce7 | 4384 | DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe)); |
d4270e57 JB |
4385 | } |
4386 | } | |
4387 | ||
a1b2278e CK |
4388 | /** |
4389 | * skl_update_scaler_users - Stages update to crtc's scaler state | |
4390 | * @intel_crtc: crtc | |
4391 | * @crtc_state: crtc_state | |
4392 | * @plane: plane (NULL indicates crtc is requesting update) | |
4393 | * @plane_state: plane's state | |
4394 | * @force_detach: request unconditional detachment of scaler | |
4395 | * | |
4396 | * This function updates scaler state for requested plane or crtc. | |
4397 | * To request scaler usage update for a plane, caller shall pass plane pointer. | |
4398 | * To request scaler usage update for crtc, caller shall pass plane pointer | |
4399 | * as NULL. | |
4400 | * | |
4401 | * Return | |
4402 | * 0 - scaler_usage updated successfully | |
4403 | * error - requested scaling cannot be supported or other error condition | |
4404 | */ | |
4405 | int | |
4406 | skl_update_scaler_users( | |
4407 | struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state, | |
4408 | struct intel_plane *intel_plane, struct intel_plane_state *plane_state, | |
4409 | int force_detach) | |
4410 | { | |
4411 | int need_scaling; | |
4412 | int idx; | |
4413 | int src_w, src_h, dst_w, dst_h; | |
4414 | int *scaler_id; | |
4415 | struct drm_framebuffer *fb; | |
4416 | struct intel_crtc_scaler_state *scaler_state; | |
6156a456 | 4417 | unsigned int rotation; |
a1b2278e CK |
4418 | |
4419 | if (!intel_crtc || !crtc_state) | |
4420 | return 0; | |
4421 | ||
4422 | scaler_state = &crtc_state->scaler_state; | |
4423 | ||
4424 | idx = intel_plane ? drm_plane_index(&intel_plane->base) : SKL_CRTC_INDEX; | |
4425 | fb = intel_plane ? plane_state->base.fb : NULL; | |
4426 | ||
4427 | if (intel_plane) { | |
4428 | src_w = drm_rect_width(&plane_state->src) >> 16; | |
4429 | src_h = drm_rect_height(&plane_state->src) >> 16; | |
4430 | dst_w = drm_rect_width(&plane_state->dst); | |
4431 | dst_h = drm_rect_height(&plane_state->dst); | |
4432 | scaler_id = &plane_state->scaler_id; | |
6156a456 | 4433 | rotation = plane_state->base.rotation; |
a1b2278e CK |
4434 | } else { |
4435 | struct drm_display_mode *adjusted_mode = | |
4436 | &crtc_state->base.adjusted_mode; | |
4437 | src_w = crtc_state->pipe_src_w; | |
4438 | src_h = crtc_state->pipe_src_h; | |
4439 | dst_w = adjusted_mode->hdisplay; | |
4440 | dst_h = adjusted_mode->vdisplay; | |
4441 | scaler_id = &scaler_state->scaler_id; | |
6156a456 | 4442 | rotation = DRM_ROTATE_0; |
a1b2278e | 4443 | } |
6156a456 CK |
4444 | |
4445 | need_scaling = intel_rotation_90_or_270(rotation) ? | |
4446 | (src_h != dst_w || src_w != dst_h): | |
4447 | (src_w != dst_w || src_h != dst_h); | |
a1b2278e CK |
4448 | |
4449 | /* | |
4450 | * if plane is being disabled or scaler is no more required or force detach | |
4451 | * - free scaler binded to this plane/crtc | |
4452 | * - in order to do this, update crtc->scaler_usage | |
4453 | * | |
4454 | * Here scaler state in crtc_state is set free so that | |
4455 | * scaler can be assigned to other user. Actual register | |
4456 | * update to free the scaler is done in plane/panel-fit programming. | |
4457 | * For this purpose crtc/plane_state->scaler_id isn't reset here. | |
4458 | */ | |
4459 | if (force_detach || !need_scaling || (intel_plane && | |
4460 | (!fb || !plane_state->visible))) { | |
4461 | if (*scaler_id >= 0) { | |
4462 | scaler_state->scaler_users &= ~(1 << idx); | |
4463 | scaler_state->scalers[*scaler_id].in_use = 0; | |
4464 | ||
4465 | DRM_DEBUG_KMS("Staged freeing scaler id %d.%d from %s:%d " | |
4466 | "crtc_state = %p scaler_users = 0x%x\n", | |
4467 | intel_crtc->pipe, *scaler_id, intel_plane ? "PLANE" : "CRTC", | |
4468 | intel_plane ? intel_plane->base.base.id : | |
4469 | intel_crtc->base.base.id, crtc_state, | |
4470 | scaler_state->scaler_users); | |
4471 | *scaler_id = -1; | |
4472 | } | |
4473 | return 0; | |
4474 | } | |
4475 | ||
4476 | /* range checks */ | |
4477 | if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H || | |
4478 | dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H || | |
4479 | ||
4480 | src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H || | |
4481 | dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) { | |
4482 | DRM_DEBUG_KMS("%s:%d scaler_user index %u.%u: src %ux%u dst %ux%u " | |
4483 | "size is out of scaler range\n", | |
4484 | intel_plane ? "PLANE" : "CRTC", | |
4485 | intel_plane ? intel_plane->base.base.id : intel_crtc->base.base.id, | |
4486 | intel_crtc->pipe, idx, src_w, src_h, dst_w, dst_h); | |
4487 | return -EINVAL; | |
4488 | } | |
4489 | ||
4490 | /* check colorkey */ | |
225c228a CK |
4491 | if (WARN_ON(intel_plane && |
4492 | intel_plane->ckey.flags != I915_SET_COLORKEY_NONE)) { | |
4493 | DRM_DEBUG_KMS("PLANE:%d scaling %ux%u->%ux%u not allowed with colorkey", | |
4494 | intel_plane->base.base.id, src_w, src_h, dst_w, dst_h); | |
a1b2278e CK |
4495 | return -EINVAL; |
4496 | } | |
4497 | ||
4498 | /* Check src format */ | |
4499 | if (intel_plane) { | |
4500 | switch (fb->pixel_format) { | |
4501 | case DRM_FORMAT_RGB565: | |
4502 | case DRM_FORMAT_XBGR8888: | |
4503 | case DRM_FORMAT_XRGB8888: | |
4504 | case DRM_FORMAT_ABGR8888: | |
4505 | case DRM_FORMAT_ARGB8888: | |
4506 | case DRM_FORMAT_XRGB2101010: | |
a1b2278e | 4507 | case DRM_FORMAT_XBGR2101010: |
a1b2278e CK |
4508 | case DRM_FORMAT_YUYV: |
4509 | case DRM_FORMAT_YVYU: | |
4510 | case DRM_FORMAT_UYVY: | |
4511 | case DRM_FORMAT_VYUY: | |
4512 | break; | |
4513 | default: | |
4514 | DRM_DEBUG_KMS("PLANE:%d FB:%d unsupported scaling format 0x%x\n", | |
4515 | intel_plane->base.base.id, fb->base.id, fb->pixel_format); | |
4516 | return -EINVAL; | |
4517 | } | |
4518 | } | |
4519 | ||
4520 | /* mark this plane as a scaler user in crtc_state */ | |
4521 | scaler_state->scaler_users |= (1 << idx); | |
4522 | DRM_DEBUG_KMS("%s:%d staged scaling request for %ux%u->%ux%u " | |
4523 | "crtc_state = %p scaler_users = 0x%x\n", | |
4524 | intel_plane ? "PLANE" : "CRTC", | |
4525 | intel_plane ? intel_plane->base.base.id : intel_crtc->base.base.id, | |
4526 | src_w, src_h, dst_w, dst_h, crtc_state, scaler_state->scaler_users); | |
4527 | return 0; | |
4528 | } | |
4529 | ||
4530 | static void skylake_pfit_update(struct intel_crtc *crtc, int enable) | |
bd2e244f JB |
4531 | { |
4532 | struct drm_device *dev = crtc->base.dev; | |
4533 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4534 | int pipe = crtc->pipe; | |
a1b2278e CK |
4535 | struct intel_crtc_scaler_state *scaler_state = |
4536 | &crtc->config->scaler_state; | |
4537 | ||
4538 | DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config); | |
4539 | ||
4540 | /* To update pfit, first update scaler state */ | |
4541 | skl_update_scaler_users(crtc, crtc->config, NULL, NULL, !enable); | |
4542 | intel_atomic_setup_scalers(crtc->base.dev, crtc, crtc->config); | |
4543 | skl_detach_scalers(crtc); | |
4544 | if (!enable) | |
4545 | return; | |
bd2e244f | 4546 | |
6e3c9717 | 4547 | if (crtc->config->pch_pfit.enabled) { |
a1b2278e CK |
4548 | int id; |
4549 | ||
4550 | if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) { | |
4551 | DRM_ERROR("Requesting pfit without getting a scaler first\n"); | |
4552 | return; | |
4553 | } | |
4554 | ||
4555 | id = scaler_state->scaler_id; | |
4556 | I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN | | |
4557 | PS_FILTER_MEDIUM | scaler_state->scalers[id].mode); | |
4558 | I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos); | |
4559 | I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size); | |
4560 | ||
4561 | DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id); | |
bd2e244f JB |
4562 | } |
4563 | } | |
4564 | ||
b074cec8 JB |
4565 | static void ironlake_pfit_enable(struct intel_crtc *crtc) |
4566 | { | |
4567 | struct drm_device *dev = crtc->base.dev; | |
4568 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4569 | int pipe = crtc->pipe; | |
4570 | ||
6e3c9717 | 4571 | if (crtc->config->pch_pfit.enabled) { |
b074cec8 JB |
4572 | /* Force use of hard-coded filter coefficients |
4573 | * as some pre-programmed values are broken, | |
4574 | * e.g. x201. | |
4575 | */ | |
4576 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) | |
4577 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | | |
4578 | PF_PIPE_SEL_IVB(pipe)); | |
4579 | else | |
4580 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); | |
6e3c9717 ACO |
4581 | I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos); |
4582 | I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size); | |
d4270e57 JB |
4583 | } |
4584 | } | |
4585 | ||
4a3b8769 | 4586 | static void intel_enable_sprite_planes(struct drm_crtc *crtc) |
bb53d4ae VS |
4587 | { |
4588 | struct drm_device *dev = crtc->dev; | |
4589 | enum pipe pipe = to_intel_crtc(crtc)->pipe; | |
af2b653b | 4590 | struct drm_plane *plane; |
bb53d4ae VS |
4591 | struct intel_plane *intel_plane; |
4592 | ||
af2b653b MR |
4593 | drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) { |
4594 | intel_plane = to_intel_plane(plane); | |
bb53d4ae VS |
4595 | if (intel_plane->pipe == pipe) |
4596 | intel_plane_restore(&intel_plane->base); | |
af2b653b | 4597 | } |
bb53d4ae VS |
4598 | } |
4599 | ||
20bc8673 | 4600 | void hsw_enable_ips(struct intel_crtc *crtc) |
d77e4531 | 4601 | { |
cea165c3 VS |
4602 | struct drm_device *dev = crtc->base.dev; |
4603 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d77e4531 | 4604 | |
6e3c9717 | 4605 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4606 | return; |
4607 | ||
cea165c3 VS |
4608 | /* We can only enable IPS after we enable a plane and wait for a vblank */ |
4609 | intel_wait_for_vblank(dev, crtc->pipe); | |
4610 | ||
d77e4531 | 4611 | assert_plane_enabled(dev_priv, crtc->plane); |
cea165c3 | 4612 | if (IS_BROADWELL(dev)) { |
2a114cc1 BW |
4613 | mutex_lock(&dev_priv->rps.hw_lock); |
4614 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000)); | |
4615 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4616 | /* Quoting Art Runyan: "its not safe to expect any particular | |
4617 | * value in IPS_CTL bit 31 after enabling IPS through the | |
e59150dc JB |
4618 | * mailbox." Moreover, the mailbox may return a bogus state, |
4619 | * so we need to just enable it and continue on. | |
2a114cc1 BW |
4620 | */ |
4621 | } else { | |
4622 | I915_WRITE(IPS_CTL, IPS_ENABLE); | |
4623 | /* The bit only becomes 1 in the next vblank, so this wait here | |
4624 | * is essentially intel_wait_for_vblank. If we don't have this | |
4625 | * and don't wait for vblanks until the end of crtc_enable, then | |
4626 | * the HW state readout code will complain that the expected | |
4627 | * IPS_CTL value is not the one we read. */ | |
4628 | if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50)) | |
4629 | DRM_ERROR("Timed out waiting for IPS enable\n"); | |
4630 | } | |
d77e4531 PZ |
4631 | } |
4632 | ||
20bc8673 | 4633 | void hsw_disable_ips(struct intel_crtc *crtc) |
d77e4531 PZ |
4634 | { |
4635 | struct drm_device *dev = crtc->base.dev; | |
4636 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4637 | ||
6e3c9717 | 4638 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4639 | return; |
4640 | ||
4641 | assert_plane_enabled(dev_priv, crtc->plane); | |
23d0b130 | 4642 | if (IS_BROADWELL(dev)) { |
2a114cc1 BW |
4643 | mutex_lock(&dev_priv->rps.hw_lock); |
4644 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0)); | |
4645 | mutex_unlock(&dev_priv->rps.hw_lock); | |
23d0b130 BW |
4646 | /* wait for pcode to finish disabling IPS, which may take up to 42ms */ |
4647 | if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42)) | |
4648 | DRM_ERROR("Timed out waiting for IPS disable\n"); | |
e59150dc | 4649 | } else { |
2a114cc1 | 4650 | I915_WRITE(IPS_CTL, 0); |
e59150dc JB |
4651 | POSTING_READ(IPS_CTL); |
4652 | } | |
d77e4531 PZ |
4653 | |
4654 | /* We need to wait for a vblank before we can disable the plane. */ | |
4655 | intel_wait_for_vblank(dev, crtc->pipe); | |
4656 | } | |
4657 | ||
4658 | /** Loads the palette/gamma unit for the CRTC with the prepared values */ | |
4659 | static void intel_crtc_load_lut(struct drm_crtc *crtc) | |
4660 | { | |
4661 | struct drm_device *dev = crtc->dev; | |
4662 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4663 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4664 | enum pipe pipe = intel_crtc->pipe; | |
4665 | int palreg = PALETTE(pipe); | |
4666 | int i; | |
4667 | bool reenable_ips = false; | |
4668 | ||
4669 | /* The clocks have to be on to load the palette. */ | |
83d65738 | 4670 | if (!crtc->state->enable || !intel_crtc->active) |
d77e4531 PZ |
4671 | return; |
4672 | ||
50360403 | 4673 | if (HAS_GMCH_DISPLAY(dev_priv->dev)) { |
409ee761 | 4674 | if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) |
d77e4531 PZ |
4675 | assert_dsi_pll_enabled(dev_priv); |
4676 | else | |
4677 | assert_pll_enabled(dev_priv, pipe); | |
4678 | } | |
4679 | ||
4680 | /* use legacy palette for Ironlake */ | |
7a1db49a | 4681 | if (!HAS_GMCH_DISPLAY(dev)) |
d77e4531 PZ |
4682 | palreg = LGC_PALETTE(pipe); |
4683 | ||
4684 | /* Workaround : Do not read or write the pipe palette/gamma data while | |
4685 | * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled. | |
4686 | */ | |
6e3c9717 | 4687 | if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled && |
d77e4531 PZ |
4688 | ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) == |
4689 | GAMMA_MODE_MODE_SPLIT)) { | |
4690 | hsw_disable_ips(intel_crtc); | |
4691 | reenable_ips = true; | |
4692 | } | |
4693 | ||
4694 | for (i = 0; i < 256; i++) { | |
4695 | I915_WRITE(palreg + 4 * i, | |
4696 | (intel_crtc->lut_r[i] << 16) | | |
4697 | (intel_crtc->lut_g[i] << 8) | | |
4698 | intel_crtc->lut_b[i]); | |
4699 | } | |
4700 | ||
4701 | if (reenable_ips) | |
4702 | hsw_enable_ips(intel_crtc); | |
4703 | } | |
4704 | ||
7cac945f | 4705 | static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc) |
d3eedb1a | 4706 | { |
7cac945f | 4707 | if (intel_crtc->overlay) { |
d3eedb1a VS |
4708 | struct drm_device *dev = intel_crtc->base.dev; |
4709 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4710 | ||
4711 | mutex_lock(&dev->struct_mutex); | |
4712 | dev_priv->mm.interruptible = false; | |
4713 | (void) intel_overlay_switch_off(intel_crtc->overlay); | |
4714 | dev_priv->mm.interruptible = true; | |
4715 | mutex_unlock(&dev->struct_mutex); | |
4716 | } | |
4717 | ||
4718 | /* Let userspace switch the overlay on again. In most cases userspace | |
4719 | * has to recompute where to put it anyway. | |
4720 | */ | |
4721 | } | |
4722 | ||
87d4300a ML |
4723 | /** |
4724 | * intel_post_enable_primary - Perform operations after enabling primary plane | |
4725 | * @crtc: the CRTC whose primary plane was just enabled | |
4726 | * | |
4727 | * Performs potentially sleeping operations that must be done after the primary | |
4728 | * plane is enabled, such as updating FBC and IPS. Note that this may be | |
4729 | * called due to an explicit primary plane update, or due to an implicit | |
4730 | * re-enable that is caused when a sprite plane is updated to no longer | |
4731 | * completely hide the primary plane. | |
4732 | */ | |
4733 | static void | |
4734 | intel_post_enable_primary(struct drm_crtc *crtc) | |
a5c4d7bc VS |
4735 | { |
4736 | struct drm_device *dev = crtc->dev; | |
87d4300a | 4737 | struct drm_i915_private *dev_priv = dev->dev_private; |
a5c4d7bc VS |
4738 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4739 | int pipe = intel_crtc->pipe; | |
a5c4d7bc | 4740 | |
87d4300a ML |
4741 | /* |
4742 | * BDW signals flip done immediately if the plane | |
4743 | * is disabled, even if the plane enable is already | |
4744 | * armed to occur at the next vblank :( | |
4745 | */ | |
4746 | if (IS_BROADWELL(dev)) | |
4747 | intel_wait_for_vblank(dev, pipe); | |
a5c4d7bc | 4748 | |
87d4300a ML |
4749 | /* |
4750 | * FIXME IPS should be fine as long as one plane is | |
4751 | * enabled, but in practice it seems to have problems | |
4752 | * when going from primary only to sprite only and vice | |
4753 | * versa. | |
4754 | */ | |
a5c4d7bc VS |
4755 | hsw_enable_ips(intel_crtc); |
4756 | ||
4757 | mutex_lock(&dev->struct_mutex); | |
7ff0ebcc | 4758 | intel_fbc_update(dev); |
a5c4d7bc | 4759 | mutex_unlock(&dev->struct_mutex); |
f99d7069 DV |
4760 | |
4761 | /* | |
87d4300a ML |
4762 | * Gen2 reports pipe underruns whenever all planes are disabled. |
4763 | * So don't enable underrun reporting before at least some planes | |
4764 | * are enabled. | |
4765 | * FIXME: Need to fix the logic to work when we turn off all planes | |
4766 | * but leave the pipe running. | |
f99d7069 | 4767 | */ |
87d4300a ML |
4768 | if (IS_GEN2(dev)) |
4769 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
4770 | ||
4771 | /* Underruns don't raise interrupts, so check manually. */ | |
4772 | if (HAS_GMCH_DISPLAY(dev)) | |
4773 | i9xx_check_fifo_underruns(dev_priv); | |
a5c4d7bc VS |
4774 | } |
4775 | ||
87d4300a ML |
4776 | /** |
4777 | * intel_pre_disable_primary - Perform operations before disabling primary plane | |
4778 | * @crtc: the CRTC whose primary plane is to be disabled | |
4779 | * | |
4780 | * Performs potentially sleeping operations that must be done before the | |
4781 | * primary plane is disabled, such as updating FBC and IPS. Note that this may | |
4782 | * be called due to an explicit primary plane update, or due to an implicit | |
4783 | * disable that is caused when a sprite plane completely hides the primary | |
4784 | * plane. | |
4785 | */ | |
4786 | static void | |
4787 | intel_pre_disable_primary(struct drm_crtc *crtc) | |
a5c4d7bc VS |
4788 | { |
4789 | struct drm_device *dev = crtc->dev; | |
4790 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4791 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4792 | int pipe = intel_crtc->pipe; | |
a5c4d7bc | 4793 | |
87d4300a ML |
4794 | /* |
4795 | * Gen2 reports pipe underruns whenever all planes are disabled. | |
4796 | * So diasble underrun reporting before all the planes get disabled. | |
4797 | * FIXME: Need to fix the logic to work when we turn off all planes | |
4798 | * but leave the pipe running. | |
4799 | */ | |
4800 | if (IS_GEN2(dev)) | |
4801 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
a5c4d7bc | 4802 | |
87d4300a ML |
4803 | /* |
4804 | * Vblank time updates from the shadow to live plane control register | |
4805 | * are blocked if the memory self-refresh mode is active at that | |
4806 | * moment. So to make sure the plane gets truly disabled, disable | |
4807 | * first the self-refresh mode. The self-refresh enable bit in turn | |
4808 | * will be checked/applied by the HW only at the next frame start | |
4809 | * event which is after the vblank start event, so we need to have a | |
4810 | * wait-for-vblank between disabling the plane and the pipe. | |
4811 | */ | |
4812 | if (HAS_GMCH_DISPLAY(dev)) | |
4813 | intel_set_memory_cxsr(dev_priv, false); | |
4814 | ||
4815 | mutex_lock(&dev->struct_mutex); | |
e35fef21 | 4816 | if (dev_priv->fbc.crtc == intel_crtc) |
7ff0ebcc | 4817 | intel_fbc_disable(dev); |
87d4300a | 4818 | mutex_unlock(&dev->struct_mutex); |
a5c4d7bc | 4819 | |
87d4300a ML |
4820 | /* |
4821 | * FIXME IPS should be fine as long as one plane is | |
4822 | * enabled, but in practice it seems to have problems | |
4823 | * when going from primary only to sprite only and vice | |
4824 | * versa. | |
4825 | */ | |
a5c4d7bc | 4826 | hsw_disable_ips(intel_crtc); |
87d4300a ML |
4827 | } |
4828 | ||
4829 | static void intel_crtc_enable_planes(struct drm_crtc *crtc) | |
4830 | { | |
87d4300a ML |
4831 | intel_enable_primary_hw_plane(crtc->primary, crtc); |
4832 | intel_enable_sprite_planes(crtc); | |
4833 | intel_crtc_update_cursor(crtc, true); | |
87d4300a ML |
4834 | |
4835 | intel_post_enable_primary(crtc); | |
4836 | } | |
4837 | ||
4838 | static void intel_crtc_disable_planes(struct drm_crtc *crtc) | |
4839 | { | |
4840 | struct drm_device *dev = crtc->dev; | |
4841 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4842 | struct intel_plane *intel_plane; | |
4843 | int pipe = intel_crtc->pipe; | |
4844 | ||
4845 | intel_crtc_wait_for_pending_flips(crtc); | |
4846 | ||
4847 | intel_pre_disable_primary(crtc); | |
a5c4d7bc | 4848 | |
7cac945f | 4849 | intel_crtc_dpms_overlay_disable(intel_crtc); |
27321ae8 ML |
4850 | for_each_intel_plane(dev, intel_plane) { |
4851 | if (intel_plane->pipe == pipe) { | |
4852 | struct drm_crtc *from = intel_plane->base.crtc; | |
4853 | ||
4854 | intel_plane->disable_plane(&intel_plane->base, | |
4855 | from ?: crtc, true); | |
4856 | } | |
4857 | } | |
f98551ae | 4858 | |
f99d7069 DV |
4859 | /* |
4860 | * FIXME: Once we grow proper nuclear flip support out of this we need | |
4861 | * to compute the mask of flip planes precisely. For the time being | |
4862 | * consider this a flip to a NULL plane. | |
4863 | */ | |
4864 | intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe)); | |
a5c4d7bc VS |
4865 | } |
4866 | ||
f67a559d JB |
4867 | static void ironlake_crtc_enable(struct drm_crtc *crtc) |
4868 | { | |
4869 | struct drm_device *dev = crtc->dev; | |
4870 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4871 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 4872 | struct intel_encoder *encoder; |
f67a559d | 4873 | int pipe = intel_crtc->pipe; |
f67a559d | 4874 | |
83d65738 | 4875 | WARN_ON(!crtc->state->enable); |
08a48469 | 4876 | |
f67a559d JB |
4877 | if (intel_crtc->active) |
4878 | return; | |
4879 | ||
6e3c9717 | 4880 | if (intel_crtc->config->has_pch_encoder) |
b14b1055 DV |
4881 | intel_prepare_shared_dpll(intel_crtc); |
4882 | ||
6e3c9717 | 4883 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 4884 | intel_dp_set_m_n(intel_crtc, M1_N1); |
29407aab DV |
4885 | |
4886 | intel_set_pipe_timings(intel_crtc); | |
4887 | ||
6e3c9717 | 4888 | if (intel_crtc->config->has_pch_encoder) { |
29407aab | 4889 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 4890 | &intel_crtc->config->fdi_m_n, NULL); |
29407aab DV |
4891 | } |
4892 | ||
4893 | ironlake_set_pipeconf(crtc); | |
4894 | ||
f67a559d | 4895 | intel_crtc->active = true; |
8664281b | 4896 | |
a72e4c9f DV |
4897 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4898 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); | |
8664281b | 4899 | |
f6736a1a | 4900 | for_each_encoder_on_crtc(dev, crtc, encoder) |
952735ee DV |
4901 | if (encoder->pre_enable) |
4902 | encoder->pre_enable(encoder); | |
f67a559d | 4903 | |
6e3c9717 | 4904 | if (intel_crtc->config->has_pch_encoder) { |
fff367c7 DV |
4905 | /* Note: FDI PLL enabling _must_ be done before we enable the |
4906 | * cpu pipes, hence this is separate from all the other fdi/pch | |
4907 | * enabling. */ | |
88cefb6c | 4908 | ironlake_fdi_pll_enable(intel_crtc); |
46b6f814 DV |
4909 | } else { |
4910 | assert_fdi_tx_disabled(dev_priv, pipe); | |
4911 | assert_fdi_rx_disabled(dev_priv, pipe); | |
4912 | } | |
f67a559d | 4913 | |
b074cec8 | 4914 | ironlake_pfit_enable(intel_crtc); |
f67a559d | 4915 | |
9c54c0dd JB |
4916 | /* |
4917 | * On ILK+ LUT must be loaded before the pipe is running but with | |
4918 | * clocks enabled | |
4919 | */ | |
4920 | intel_crtc_load_lut(crtc); | |
4921 | ||
f37fcc2a | 4922 | intel_update_watermarks(crtc); |
e1fdc473 | 4923 | intel_enable_pipe(intel_crtc); |
f67a559d | 4924 | |
6e3c9717 | 4925 | if (intel_crtc->config->has_pch_encoder) |
f67a559d | 4926 | ironlake_pch_enable(crtc); |
c98e9dcf | 4927 | |
f9b61ff6 DV |
4928 | assert_vblank_disabled(crtc); |
4929 | drm_crtc_vblank_on(crtc); | |
4930 | ||
fa5c73b1 DV |
4931 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4932 | encoder->enable(encoder); | |
61b77ddd DV |
4933 | |
4934 | if (HAS_PCH_CPT(dev)) | |
a1520318 | 4935 | cpt_verify_modeset(dev, intel_crtc->pipe); |
6be4a607 JB |
4936 | } |
4937 | ||
42db64ef PZ |
4938 | /* IPS only exists on ULT machines and is tied to pipe A. */ |
4939 | static bool hsw_crtc_supports_ips(struct intel_crtc *crtc) | |
4940 | { | |
f5adf94e | 4941 | return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A; |
42db64ef PZ |
4942 | } |
4943 | ||
e4916946 PZ |
4944 | /* |
4945 | * This implements the workaround described in the "notes" section of the mode | |
4946 | * set sequence documentation. When going from no pipes or single pipe to | |
4947 | * multiple pipes, and planes are enabled after the pipe, we need to wait at | |
4948 | * least 2 vblanks on the first pipe before enabling planes on the second pipe. | |
4949 | */ | |
4950 | static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc) | |
4951 | { | |
4952 | struct drm_device *dev = crtc->base.dev; | |
4953 | struct intel_crtc *crtc_it, *other_active_crtc = NULL; | |
4954 | ||
4955 | /* We want to get the other_active_crtc only if there's only 1 other | |
4956 | * active crtc. */ | |
d3fcc808 | 4957 | for_each_intel_crtc(dev, crtc_it) { |
e4916946 PZ |
4958 | if (!crtc_it->active || crtc_it == crtc) |
4959 | continue; | |
4960 | ||
4961 | if (other_active_crtc) | |
4962 | return; | |
4963 | ||
4964 | other_active_crtc = crtc_it; | |
4965 | } | |
4966 | if (!other_active_crtc) | |
4967 | return; | |
4968 | ||
4969 | intel_wait_for_vblank(dev, other_active_crtc->pipe); | |
4970 | intel_wait_for_vblank(dev, other_active_crtc->pipe); | |
4971 | } | |
4972 | ||
4f771f10 PZ |
4973 | static void haswell_crtc_enable(struct drm_crtc *crtc) |
4974 | { | |
4975 | struct drm_device *dev = crtc->dev; | |
4976 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4977 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4978 | struct intel_encoder *encoder; | |
4979 | int pipe = intel_crtc->pipe; | |
4f771f10 | 4980 | |
83d65738 | 4981 | WARN_ON(!crtc->state->enable); |
4f771f10 PZ |
4982 | |
4983 | if (intel_crtc->active) | |
4984 | return; | |
4985 | ||
df8ad70c DV |
4986 | if (intel_crtc_to_shared_dpll(intel_crtc)) |
4987 | intel_enable_shared_dpll(intel_crtc); | |
4988 | ||
6e3c9717 | 4989 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 4990 | intel_dp_set_m_n(intel_crtc, M1_N1); |
229fca97 DV |
4991 | |
4992 | intel_set_pipe_timings(intel_crtc); | |
4993 | ||
6e3c9717 ACO |
4994 | if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) { |
4995 | I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder), | |
4996 | intel_crtc->config->pixel_multiplier - 1); | |
ebb69c95 CT |
4997 | } |
4998 | ||
6e3c9717 | 4999 | if (intel_crtc->config->has_pch_encoder) { |
229fca97 | 5000 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 5001 | &intel_crtc->config->fdi_m_n, NULL); |
229fca97 DV |
5002 | } |
5003 | ||
5004 | haswell_set_pipeconf(crtc); | |
5005 | ||
5006 | intel_set_pipe_csc(crtc); | |
5007 | ||
4f771f10 | 5008 | intel_crtc->active = true; |
8664281b | 5009 | |
a72e4c9f | 5010 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4f771f10 PZ |
5011 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5012 | if (encoder->pre_enable) | |
5013 | encoder->pre_enable(encoder); | |
5014 | ||
6e3c9717 | 5015 | if (intel_crtc->config->has_pch_encoder) { |
a72e4c9f DV |
5016 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
5017 | true); | |
4fe9467d ID |
5018 | dev_priv->display.fdi_link_train(crtc); |
5019 | } | |
5020 | ||
1f544388 | 5021 | intel_ddi_enable_pipe_clock(intel_crtc); |
4f771f10 | 5022 | |
ff6d9f55 | 5023 | if (INTEL_INFO(dev)->gen == 9) |
a1b2278e | 5024 | skylake_pfit_update(intel_crtc, 1); |
ff6d9f55 | 5025 | else if (INTEL_INFO(dev)->gen < 9) |
bd2e244f | 5026 | ironlake_pfit_enable(intel_crtc); |
ff6d9f55 JB |
5027 | else |
5028 | MISSING_CASE(INTEL_INFO(dev)->gen); | |
4f771f10 PZ |
5029 | |
5030 | /* | |
5031 | * On ILK+ LUT must be loaded before the pipe is running but with | |
5032 | * clocks enabled | |
5033 | */ | |
5034 | intel_crtc_load_lut(crtc); | |
5035 | ||
1f544388 | 5036 | intel_ddi_set_pipe_settings(crtc); |
8228c251 | 5037 | intel_ddi_enable_transcoder_func(crtc); |
4f771f10 | 5038 | |
f37fcc2a | 5039 | intel_update_watermarks(crtc); |
e1fdc473 | 5040 | intel_enable_pipe(intel_crtc); |
42db64ef | 5041 | |
6e3c9717 | 5042 | if (intel_crtc->config->has_pch_encoder) |
1507e5bd | 5043 | lpt_pch_enable(crtc); |
4f771f10 | 5044 | |
6e3c9717 | 5045 | if (intel_crtc->config->dp_encoder_is_mst) |
0e32b39c DA |
5046 | intel_ddi_set_vc_payload_alloc(crtc, true); |
5047 | ||
f9b61ff6 DV |
5048 | assert_vblank_disabled(crtc); |
5049 | drm_crtc_vblank_on(crtc); | |
5050 | ||
8807e55b | 5051 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4f771f10 | 5052 | encoder->enable(encoder); |
8807e55b JN |
5053 | intel_opregion_notify_encoder(encoder, true); |
5054 | } | |
4f771f10 | 5055 | |
e4916946 PZ |
5056 | /* If we change the relative order between pipe/planes enabling, we need |
5057 | * to change the workaround. */ | |
5058 | haswell_mode_set_planes_workaround(intel_crtc); | |
4f771f10 PZ |
5059 | } |
5060 | ||
3f8dce3a DV |
5061 | static void ironlake_pfit_disable(struct intel_crtc *crtc) |
5062 | { | |
5063 | struct drm_device *dev = crtc->base.dev; | |
5064 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5065 | int pipe = crtc->pipe; | |
5066 | ||
5067 | /* To avoid upsetting the power well on haswell only disable the pfit if | |
5068 | * it's in use. The hw state code will make sure we get this right. */ | |
6e3c9717 | 5069 | if (crtc->config->pch_pfit.enabled) { |
3f8dce3a DV |
5070 | I915_WRITE(PF_CTL(pipe), 0); |
5071 | I915_WRITE(PF_WIN_POS(pipe), 0); | |
5072 | I915_WRITE(PF_WIN_SZ(pipe), 0); | |
5073 | } | |
5074 | } | |
5075 | ||
6be4a607 JB |
5076 | static void ironlake_crtc_disable(struct drm_crtc *crtc) |
5077 | { | |
5078 | struct drm_device *dev = crtc->dev; | |
5079 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5080 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 5081 | struct intel_encoder *encoder; |
6be4a607 | 5082 | int pipe = intel_crtc->pipe; |
5eddb70b | 5083 | u32 reg, temp; |
b52eb4dc | 5084 | |
f7abfe8b CW |
5085 | if (!intel_crtc->active) |
5086 | return; | |
5087 | ||
ea9d758d DV |
5088 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5089 | encoder->disable(encoder); | |
5090 | ||
f9b61ff6 DV |
5091 | drm_crtc_vblank_off(crtc); |
5092 | assert_vblank_disabled(crtc); | |
5093 | ||
6e3c9717 | 5094 | if (intel_crtc->config->has_pch_encoder) |
a72e4c9f | 5095 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); |
d925c59a | 5096 | |
575f7ab7 | 5097 | intel_disable_pipe(intel_crtc); |
32f9d658 | 5098 | |
3f8dce3a | 5099 | ironlake_pfit_disable(intel_crtc); |
2c07245f | 5100 | |
5a74f70a VS |
5101 | if (intel_crtc->config->has_pch_encoder) |
5102 | ironlake_fdi_disable(crtc); | |
5103 | ||
bf49ec8c DV |
5104 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5105 | if (encoder->post_disable) | |
5106 | encoder->post_disable(encoder); | |
2c07245f | 5107 | |
6e3c9717 | 5108 | if (intel_crtc->config->has_pch_encoder) { |
d925c59a | 5109 | ironlake_disable_pch_transcoder(dev_priv, pipe); |
6be4a607 | 5110 | |
d925c59a DV |
5111 | if (HAS_PCH_CPT(dev)) { |
5112 | /* disable TRANS_DP_CTL */ | |
5113 | reg = TRANS_DP_CTL(pipe); | |
5114 | temp = I915_READ(reg); | |
5115 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | | |
5116 | TRANS_DP_PORT_SEL_MASK); | |
5117 | temp |= TRANS_DP_PORT_SEL_NONE; | |
5118 | I915_WRITE(reg, temp); | |
5119 | ||
5120 | /* disable DPLL_SEL */ | |
5121 | temp = I915_READ(PCH_DPLL_SEL); | |
11887397 | 5122 | temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe)); |
d925c59a | 5123 | I915_WRITE(PCH_DPLL_SEL, temp); |
9db4a9c7 | 5124 | } |
e3421a18 | 5125 | |
d925c59a | 5126 | /* disable PCH DPLL */ |
e72f9fbf | 5127 | intel_disable_shared_dpll(intel_crtc); |
8db9d77b | 5128 | |
d925c59a DV |
5129 | ironlake_fdi_pll_disable(intel_crtc); |
5130 | } | |
6b383a7f | 5131 | |
f7abfe8b | 5132 | intel_crtc->active = false; |
46ba614c | 5133 | intel_update_watermarks(crtc); |
d1ebd816 BW |
5134 | |
5135 | mutex_lock(&dev->struct_mutex); | |
7ff0ebcc | 5136 | intel_fbc_update(dev); |
d1ebd816 | 5137 | mutex_unlock(&dev->struct_mutex); |
6be4a607 | 5138 | } |
1b3c7a47 | 5139 | |
4f771f10 | 5140 | static void haswell_crtc_disable(struct drm_crtc *crtc) |
ee7b9f93 | 5141 | { |
4f771f10 PZ |
5142 | struct drm_device *dev = crtc->dev; |
5143 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee7b9f93 | 5144 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4f771f10 | 5145 | struct intel_encoder *encoder; |
6e3c9717 | 5146 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
ee7b9f93 | 5147 | |
4f771f10 PZ |
5148 | if (!intel_crtc->active) |
5149 | return; | |
5150 | ||
8807e55b JN |
5151 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
5152 | intel_opregion_notify_encoder(encoder, false); | |
4f771f10 | 5153 | encoder->disable(encoder); |
8807e55b | 5154 | } |
4f771f10 | 5155 | |
f9b61ff6 DV |
5156 | drm_crtc_vblank_off(crtc); |
5157 | assert_vblank_disabled(crtc); | |
5158 | ||
6e3c9717 | 5159 | if (intel_crtc->config->has_pch_encoder) |
a72e4c9f DV |
5160 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
5161 | false); | |
575f7ab7 | 5162 | intel_disable_pipe(intel_crtc); |
4f771f10 | 5163 | |
6e3c9717 | 5164 | if (intel_crtc->config->dp_encoder_is_mst) |
a4bf214f VS |
5165 | intel_ddi_set_vc_payload_alloc(crtc, false); |
5166 | ||
ad80a810 | 5167 | intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); |
4f771f10 | 5168 | |
ff6d9f55 | 5169 | if (INTEL_INFO(dev)->gen == 9) |
a1b2278e | 5170 | skylake_pfit_update(intel_crtc, 0); |
ff6d9f55 | 5171 | else if (INTEL_INFO(dev)->gen < 9) |
bd2e244f | 5172 | ironlake_pfit_disable(intel_crtc); |
ff6d9f55 JB |
5173 | else |
5174 | MISSING_CASE(INTEL_INFO(dev)->gen); | |
4f771f10 | 5175 | |
1f544388 | 5176 | intel_ddi_disable_pipe_clock(intel_crtc); |
4f771f10 | 5177 | |
6e3c9717 | 5178 | if (intel_crtc->config->has_pch_encoder) { |
ab4d966c | 5179 | lpt_disable_pch_transcoder(dev_priv); |
1ad960f2 | 5180 | intel_ddi_fdi_disable(crtc); |
83616634 | 5181 | } |
4f771f10 | 5182 | |
97b040aa ID |
5183 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5184 | if (encoder->post_disable) | |
5185 | encoder->post_disable(encoder); | |
5186 | ||
4f771f10 | 5187 | intel_crtc->active = false; |
46ba614c | 5188 | intel_update_watermarks(crtc); |
4f771f10 PZ |
5189 | |
5190 | mutex_lock(&dev->struct_mutex); | |
7ff0ebcc | 5191 | intel_fbc_update(dev); |
4f771f10 | 5192 | mutex_unlock(&dev->struct_mutex); |
df8ad70c DV |
5193 | |
5194 | if (intel_crtc_to_shared_dpll(intel_crtc)) | |
5195 | intel_disable_shared_dpll(intel_crtc); | |
4f771f10 PZ |
5196 | } |
5197 | ||
ee7b9f93 JB |
5198 | static void ironlake_crtc_off(struct drm_crtc *crtc) |
5199 | { | |
5200 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
e72f9fbf | 5201 | intel_put_shared_dpll(intel_crtc); |
ee7b9f93 JB |
5202 | } |
5203 | ||
6441ab5f | 5204 | |
2dd24552 JB |
5205 | static void i9xx_pfit_enable(struct intel_crtc *crtc) |
5206 | { | |
5207 | struct drm_device *dev = crtc->base.dev; | |
5208 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6e3c9717 | 5209 | struct intel_crtc_state *pipe_config = crtc->config; |
2dd24552 | 5210 | |
681a8504 | 5211 | if (!pipe_config->gmch_pfit.control) |
2dd24552 JB |
5212 | return; |
5213 | ||
2dd24552 | 5214 | /* |
c0b03411 DV |
5215 | * The panel fitter should only be adjusted whilst the pipe is disabled, |
5216 | * according to register description and PRM. | |
2dd24552 | 5217 | */ |
c0b03411 DV |
5218 | WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE); |
5219 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
2dd24552 | 5220 | |
b074cec8 JB |
5221 | I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios); |
5222 | I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control); | |
5a80c45c DV |
5223 | |
5224 | /* Border color in case we don't scale up to the full screen. Black by | |
5225 | * default, change to something else for debugging. */ | |
5226 | I915_WRITE(BCLRPAT(crtc->pipe), 0); | |
2dd24552 JB |
5227 | } |
5228 | ||
d05410f9 DA |
5229 | static enum intel_display_power_domain port_to_power_domain(enum port port) |
5230 | { | |
5231 | switch (port) { | |
5232 | case PORT_A: | |
5233 | return POWER_DOMAIN_PORT_DDI_A_4_LANES; | |
5234 | case PORT_B: | |
5235 | return POWER_DOMAIN_PORT_DDI_B_4_LANES; | |
5236 | case PORT_C: | |
5237 | return POWER_DOMAIN_PORT_DDI_C_4_LANES; | |
5238 | case PORT_D: | |
5239 | return POWER_DOMAIN_PORT_DDI_D_4_LANES; | |
5240 | default: | |
5241 | WARN_ON_ONCE(1); | |
5242 | return POWER_DOMAIN_PORT_OTHER; | |
5243 | } | |
5244 | } | |
5245 | ||
77d22dca ID |
5246 | #define for_each_power_domain(domain, mask) \ |
5247 | for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \ | |
5248 | if ((1 << (domain)) & (mask)) | |
5249 | ||
319be8ae ID |
5250 | enum intel_display_power_domain |
5251 | intel_display_port_power_domain(struct intel_encoder *intel_encoder) | |
5252 | { | |
5253 | struct drm_device *dev = intel_encoder->base.dev; | |
5254 | struct intel_digital_port *intel_dig_port; | |
5255 | ||
5256 | switch (intel_encoder->type) { | |
5257 | case INTEL_OUTPUT_UNKNOWN: | |
5258 | /* Only DDI platforms should ever use this output type */ | |
5259 | WARN_ON_ONCE(!HAS_DDI(dev)); | |
5260 | case INTEL_OUTPUT_DISPLAYPORT: | |
5261 | case INTEL_OUTPUT_HDMI: | |
5262 | case INTEL_OUTPUT_EDP: | |
5263 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
d05410f9 | 5264 | return port_to_power_domain(intel_dig_port->port); |
0e32b39c DA |
5265 | case INTEL_OUTPUT_DP_MST: |
5266 | intel_dig_port = enc_to_mst(&intel_encoder->base)->primary; | |
5267 | return port_to_power_domain(intel_dig_port->port); | |
319be8ae ID |
5268 | case INTEL_OUTPUT_ANALOG: |
5269 | return POWER_DOMAIN_PORT_CRT; | |
5270 | case INTEL_OUTPUT_DSI: | |
5271 | return POWER_DOMAIN_PORT_DSI; | |
5272 | default: | |
5273 | return POWER_DOMAIN_PORT_OTHER; | |
5274 | } | |
5275 | } | |
5276 | ||
5277 | static unsigned long get_crtc_power_domains(struct drm_crtc *crtc) | |
77d22dca | 5278 | { |
319be8ae ID |
5279 | struct drm_device *dev = crtc->dev; |
5280 | struct intel_encoder *intel_encoder; | |
5281 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5282 | enum pipe pipe = intel_crtc->pipe; | |
77d22dca ID |
5283 | unsigned long mask; |
5284 | enum transcoder transcoder; | |
5285 | ||
5286 | transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe); | |
5287 | ||
5288 | mask = BIT(POWER_DOMAIN_PIPE(pipe)); | |
5289 | mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder)); | |
6e3c9717 ACO |
5290 | if (intel_crtc->config->pch_pfit.enabled || |
5291 | intel_crtc->config->pch_pfit.force_thru) | |
77d22dca ID |
5292 | mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe)); |
5293 | ||
319be8ae ID |
5294 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) |
5295 | mask |= BIT(intel_display_port_power_domain(intel_encoder)); | |
5296 | ||
77d22dca ID |
5297 | return mask; |
5298 | } | |
5299 | ||
679dacd4 | 5300 | static void modeset_update_crtc_power_domains(struct drm_atomic_state *state) |
77d22dca | 5301 | { |
679dacd4 | 5302 | struct drm_device *dev = state->dev; |
77d22dca ID |
5303 | struct drm_i915_private *dev_priv = dev->dev_private; |
5304 | unsigned long pipe_domains[I915_MAX_PIPES] = { 0, }; | |
5305 | struct intel_crtc *crtc; | |
5306 | ||
5307 | /* | |
5308 | * First get all needed power domains, then put all unneeded, to avoid | |
5309 | * any unnecessary toggling of the power wells. | |
5310 | */ | |
d3fcc808 | 5311 | for_each_intel_crtc(dev, crtc) { |
77d22dca ID |
5312 | enum intel_display_power_domain domain; |
5313 | ||
83d65738 | 5314 | if (!crtc->base.state->enable) |
77d22dca ID |
5315 | continue; |
5316 | ||
319be8ae | 5317 | pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base); |
77d22dca ID |
5318 | |
5319 | for_each_power_domain(domain, pipe_domains[crtc->pipe]) | |
5320 | intel_display_power_get(dev_priv, domain); | |
5321 | } | |
5322 | ||
50f6e502 | 5323 | if (dev_priv->display.modeset_global_resources) |
679dacd4 | 5324 | dev_priv->display.modeset_global_resources(state); |
50f6e502 | 5325 | |
d3fcc808 | 5326 | for_each_intel_crtc(dev, crtc) { |
77d22dca ID |
5327 | enum intel_display_power_domain domain; |
5328 | ||
5329 | for_each_power_domain(domain, crtc->enabled_power_domains) | |
5330 | intel_display_power_put(dev_priv, domain); | |
5331 | ||
5332 | crtc->enabled_power_domains = pipe_domains[crtc->pipe]; | |
5333 | } | |
5334 | ||
5335 | intel_display_set_init_power(dev_priv, false); | |
5336 | } | |
5337 | ||
f8437dd1 VK |
5338 | void broxton_set_cdclk(struct drm_device *dev, int frequency) |
5339 | { | |
5340 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5341 | uint32_t divider; | |
5342 | uint32_t ratio; | |
5343 | uint32_t current_freq; | |
5344 | int ret; | |
5345 | ||
5346 | /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */ | |
5347 | switch (frequency) { | |
5348 | case 144000: | |
5349 | divider = BXT_CDCLK_CD2X_DIV_SEL_4; | |
5350 | ratio = BXT_DE_PLL_RATIO(60); | |
5351 | break; | |
5352 | case 288000: | |
5353 | divider = BXT_CDCLK_CD2X_DIV_SEL_2; | |
5354 | ratio = BXT_DE_PLL_RATIO(60); | |
5355 | break; | |
5356 | case 384000: | |
5357 | divider = BXT_CDCLK_CD2X_DIV_SEL_1_5; | |
5358 | ratio = BXT_DE_PLL_RATIO(60); | |
5359 | break; | |
5360 | case 576000: | |
5361 | divider = BXT_CDCLK_CD2X_DIV_SEL_1; | |
5362 | ratio = BXT_DE_PLL_RATIO(60); | |
5363 | break; | |
5364 | case 624000: | |
5365 | divider = BXT_CDCLK_CD2X_DIV_SEL_1; | |
5366 | ratio = BXT_DE_PLL_RATIO(65); | |
5367 | break; | |
5368 | case 19200: | |
5369 | /* | |
5370 | * Bypass frequency with DE PLL disabled. Init ratio, divider | |
5371 | * to suppress GCC warning. | |
5372 | */ | |
5373 | ratio = 0; | |
5374 | divider = 0; | |
5375 | break; | |
5376 | default: | |
5377 | DRM_ERROR("unsupported CDCLK freq %d", frequency); | |
5378 | ||
5379 | return; | |
5380 | } | |
5381 | ||
5382 | mutex_lock(&dev_priv->rps.hw_lock); | |
5383 | /* Inform power controller of upcoming frequency change */ | |
5384 | ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, | |
5385 | 0x80000000); | |
5386 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5387 | ||
5388 | if (ret) { | |
5389 | DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n", | |
5390 | ret, frequency); | |
5391 | return; | |
5392 | } | |
5393 | ||
5394 | current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK; | |
5395 | /* convert from .1 fixpoint MHz with -1MHz offset to kHz */ | |
5396 | current_freq = current_freq * 500 + 1000; | |
5397 | ||
5398 | /* | |
5399 | * DE PLL has to be disabled when | |
5400 | * - setting to 19.2MHz (bypass, PLL isn't used) | |
5401 | * - before setting to 624MHz (PLL needs toggling) | |
5402 | * - before setting to any frequency from 624MHz (PLL needs toggling) | |
5403 | */ | |
5404 | if (frequency == 19200 || frequency == 624000 || | |
5405 | current_freq == 624000) { | |
5406 | I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE); | |
5407 | /* Timeout 200us */ | |
5408 | if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK), | |
5409 | 1)) | |
5410 | DRM_ERROR("timout waiting for DE PLL unlock\n"); | |
5411 | } | |
5412 | ||
5413 | if (frequency != 19200) { | |
5414 | uint32_t val; | |
5415 | ||
5416 | val = I915_READ(BXT_DE_PLL_CTL); | |
5417 | val &= ~BXT_DE_PLL_RATIO_MASK; | |
5418 | val |= ratio; | |
5419 | I915_WRITE(BXT_DE_PLL_CTL, val); | |
5420 | ||
5421 | I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE); | |
5422 | /* Timeout 200us */ | |
5423 | if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1)) | |
5424 | DRM_ERROR("timeout waiting for DE PLL lock\n"); | |
5425 | ||
5426 | val = I915_READ(CDCLK_CTL); | |
5427 | val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK; | |
5428 | val |= divider; | |
5429 | /* | |
5430 | * Disable SSA Precharge when CD clock frequency < 500 MHz, | |
5431 | * enable otherwise. | |
5432 | */ | |
5433 | val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE; | |
5434 | if (frequency >= 500000) | |
5435 | val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; | |
5436 | ||
5437 | val &= ~CDCLK_FREQ_DECIMAL_MASK; | |
5438 | /* convert from kHz to .1 fixpoint MHz with -1MHz offset */ | |
5439 | val |= (frequency - 1000) / 500; | |
5440 | I915_WRITE(CDCLK_CTL, val); | |
5441 | } | |
5442 | ||
5443 | mutex_lock(&dev_priv->rps.hw_lock); | |
5444 | ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, | |
5445 | DIV_ROUND_UP(frequency, 25000)); | |
5446 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5447 | ||
5448 | if (ret) { | |
5449 | DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n", | |
5450 | ret, frequency); | |
5451 | return; | |
5452 | } | |
5453 | ||
5454 | dev_priv->cdclk_freq = frequency; | |
5455 | } | |
5456 | ||
5457 | void broxton_init_cdclk(struct drm_device *dev) | |
5458 | { | |
5459 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5460 | uint32_t val; | |
5461 | ||
5462 | /* | |
5463 | * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT | |
5464 | * or else the reset will hang because there is no PCH to respond. | |
5465 | * Move the handshake programming to initialization sequence. | |
5466 | * Previously was left up to BIOS. | |
5467 | */ | |
5468 | val = I915_READ(HSW_NDE_RSTWRN_OPT); | |
5469 | val &= ~RESET_PCH_HANDSHAKE_ENABLE; | |
5470 | I915_WRITE(HSW_NDE_RSTWRN_OPT, val); | |
5471 | ||
5472 | /* Enable PG1 for cdclk */ | |
5473 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); | |
5474 | ||
5475 | /* check if cd clock is enabled */ | |
5476 | if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) { | |
5477 | DRM_DEBUG_KMS("Display already initialized\n"); | |
5478 | return; | |
5479 | } | |
5480 | ||
5481 | /* | |
5482 | * FIXME: | |
5483 | * - The initial CDCLK needs to be read from VBT. | |
5484 | * Need to make this change after VBT has changes for BXT. | |
5485 | * - check if setting the max (or any) cdclk freq is really necessary | |
5486 | * here, it belongs to modeset time | |
5487 | */ | |
5488 | broxton_set_cdclk(dev, 624000); | |
5489 | ||
5490 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST); | |
22e02c0b VS |
5491 | POSTING_READ(DBUF_CTL); |
5492 | ||
f8437dd1 VK |
5493 | udelay(10); |
5494 | ||
5495 | if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE)) | |
5496 | DRM_ERROR("DBuf power enable timeout!\n"); | |
5497 | } | |
5498 | ||
5499 | void broxton_uninit_cdclk(struct drm_device *dev) | |
5500 | { | |
5501 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5502 | ||
5503 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST); | |
22e02c0b VS |
5504 | POSTING_READ(DBUF_CTL); |
5505 | ||
f8437dd1 VK |
5506 | udelay(10); |
5507 | ||
5508 | if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE) | |
5509 | DRM_ERROR("DBuf power disable timeout!\n"); | |
5510 | ||
5511 | /* Set minimum (bypass) frequency, in effect turning off the DE PLL */ | |
5512 | broxton_set_cdclk(dev, 19200); | |
5513 | ||
5514 | intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); | |
5515 | } | |
5516 | ||
5d96d8af DL |
5517 | static const struct skl_cdclk_entry { |
5518 | unsigned int freq; | |
5519 | unsigned int vco; | |
5520 | } skl_cdclk_frequencies[] = { | |
5521 | { .freq = 308570, .vco = 8640 }, | |
5522 | { .freq = 337500, .vco = 8100 }, | |
5523 | { .freq = 432000, .vco = 8640 }, | |
5524 | { .freq = 450000, .vco = 8100 }, | |
5525 | { .freq = 540000, .vco = 8100 }, | |
5526 | { .freq = 617140, .vco = 8640 }, | |
5527 | { .freq = 675000, .vco = 8100 }, | |
5528 | }; | |
5529 | ||
5530 | static unsigned int skl_cdclk_decimal(unsigned int freq) | |
5531 | { | |
5532 | return (freq - 1000) / 500; | |
5533 | } | |
5534 | ||
5535 | static unsigned int skl_cdclk_get_vco(unsigned int freq) | |
5536 | { | |
5537 | unsigned int i; | |
5538 | ||
5539 | for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) { | |
5540 | const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i]; | |
5541 | ||
5542 | if (e->freq == freq) | |
5543 | return e->vco; | |
5544 | } | |
5545 | ||
5546 | return 8100; | |
5547 | } | |
5548 | ||
5549 | static void | |
5550 | skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco) | |
5551 | { | |
5552 | unsigned int min_freq; | |
5553 | u32 val; | |
5554 | ||
5555 | /* select the minimum CDCLK before enabling DPLL 0 */ | |
5556 | val = I915_READ(CDCLK_CTL); | |
5557 | val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK; | |
5558 | val |= CDCLK_FREQ_337_308; | |
5559 | ||
5560 | if (required_vco == 8640) | |
5561 | min_freq = 308570; | |
5562 | else | |
5563 | min_freq = 337500; | |
5564 | ||
5565 | val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq); | |
5566 | ||
5567 | I915_WRITE(CDCLK_CTL, val); | |
5568 | POSTING_READ(CDCLK_CTL); | |
5569 | ||
5570 | /* | |
5571 | * We always enable DPLL0 with the lowest link rate possible, but still | |
5572 | * taking into account the VCO required to operate the eDP panel at the | |
5573 | * desired frequency. The usual DP link rates operate with a VCO of | |
5574 | * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640. | |
5575 | * The modeset code is responsible for the selection of the exact link | |
5576 | * rate later on, with the constraint of choosing a frequency that | |
5577 | * works with required_vco. | |
5578 | */ | |
5579 | val = I915_READ(DPLL_CTRL1); | |
5580 | ||
5581 | val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) | | |
5582 | DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)); | |
5583 | val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0); | |
5584 | if (required_vco == 8640) | |
5585 | val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, | |
5586 | SKL_DPLL0); | |
5587 | else | |
5588 | val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, | |
5589 | SKL_DPLL0); | |
5590 | ||
5591 | I915_WRITE(DPLL_CTRL1, val); | |
5592 | POSTING_READ(DPLL_CTRL1); | |
5593 | ||
5594 | I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE); | |
5595 | ||
5596 | if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5)) | |
5597 | DRM_ERROR("DPLL0 not locked\n"); | |
5598 | } | |
5599 | ||
5600 | static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv) | |
5601 | { | |
5602 | int ret; | |
5603 | u32 val; | |
5604 | ||
5605 | /* inform PCU we want to change CDCLK */ | |
5606 | val = SKL_CDCLK_PREPARE_FOR_CHANGE; | |
5607 | mutex_lock(&dev_priv->rps.hw_lock); | |
5608 | ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val); | |
5609 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5610 | ||
5611 | return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE); | |
5612 | } | |
5613 | ||
5614 | static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv) | |
5615 | { | |
5616 | unsigned int i; | |
5617 | ||
5618 | for (i = 0; i < 15; i++) { | |
5619 | if (skl_cdclk_pcu_ready(dev_priv)) | |
5620 | return true; | |
5621 | udelay(10); | |
5622 | } | |
5623 | ||
5624 | return false; | |
5625 | } | |
5626 | ||
5627 | static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq) | |
5628 | { | |
5629 | u32 freq_select, pcu_ack; | |
5630 | ||
5631 | DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq); | |
5632 | ||
5633 | if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) { | |
5634 | DRM_ERROR("failed to inform PCU about cdclk change\n"); | |
5635 | return; | |
5636 | } | |
5637 | ||
5638 | /* set CDCLK_CTL */ | |
5639 | switch(freq) { | |
5640 | case 450000: | |
5641 | case 432000: | |
5642 | freq_select = CDCLK_FREQ_450_432; | |
5643 | pcu_ack = 1; | |
5644 | break; | |
5645 | case 540000: | |
5646 | freq_select = CDCLK_FREQ_540; | |
5647 | pcu_ack = 2; | |
5648 | break; | |
5649 | case 308570: | |
5650 | case 337500: | |
5651 | default: | |
5652 | freq_select = CDCLK_FREQ_337_308; | |
5653 | pcu_ack = 0; | |
5654 | break; | |
5655 | case 617140: | |
5656 | case 675000: | |
5657 | freq_select = CDCLK_FREQ_675_617; | |
5658 | pcu_ack = 3; | |
5659 | break; | |
5660 | } | |
5661 | ||
5662 | I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq)); | |
5663 | POSTING_READ(CDCLK_CTL); | |
5664 | ||
5665 | /* inform PCU of the change */ | |
5666 | mutex_lock(&dev_priv->rps.hw_lock); | |
5667 | sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack); | |
5668 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5669 | } | |
5670 | ||
5671 | void skl_uninit_cdclk(struct drm_i915_private *dev_priv) | |
5672 | { | |
5673 | /* disable DBUF power */ | |
5674 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST); | |
5675 | POSTING_READ(DBUF_CTL); | |
5676 | ||
5677 | udelay(10); | |
5678 | ||
5679 | if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE) | |
5680 | DRM_ERROR("DBuf power disable timeout\n"); | |
5681 | ||
5682 | /* disable DPLL0 */ | |
5683 | I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE); | |
5684 | if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1)) | |
5685 | DRM_ERROR("Couldn't disable DPLL0\n"); | |
5686 | ||
5687 | intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); | |
5688 | } | |
5689 | ||
5690 | void skl_init_cdclk(struct drm_i915_private *dev_priv) | |
5691 | { | |
5692 | u32 val; | |
5693 | unsigned int required_vco; | |
5694 | ||
5695 | /* enable PCH reset handshake */ | |
5696 | val = I915_READ(HSW_NDE_RSTWRN_OPT); | |
5697 | I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE); | |
5698 | ||
5699 | /* enable PG1 and Misc I/O */ | |
5700 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); | |
5701 | ||
5702 | /* DPLL0 already enabed !? */ | |
5703 | if (I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE) { | |
5704 | DRM_DEBUG_DRIVER("DPLL0 already running\n"); | |
5705 | return; | |
5706 | } | |
5707 | ||
5708 | /* enable DPLL0 */ | |
5709 | required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk); | |
5710 | skl_dpll0_enable(dev_priv, required_vco); | |
5711 | ||
5712 | /* set CDCLK to the frequency the BIOS chose */ | |
5713 | skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk); | |
5714 | ||
5715 | /* enable DBUF power */ | |
5716 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST); | |
5717 | POSTING_READ(DBUF_CTL); | |
5718 | ||
5719 | udelay(10); | |
5720 | ||
5721 | if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE)) | |
5722 | DRM_ERROR("DBuf power enable timeout\n"); | |
5723 | } | |
5724 | ||
dfcab17e | 5725 | /* returns HPLL frequency in kHz */ |
f8bf63fd | 5726 | static int valleyview_get_vco(struct drm_i915_private *dev_priv) |
30a970c6 | 5727 | { |
586f49dc | 5728 | int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; |
30a970c6 | 5729 | |
586f49dc | 5730 | /* Obtain SKU information */ |
a580516d | 5731 | mutex_lock(&dev_priv->sb_lock); |
586f49dc JB |
5732 | hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & |
5733 | CCK_FUSE_HPLL_FREQ_MASK; | |
a580516d | 5734 | mutex_unlock(&dev_priv->sb_lock); |
30a970c6 | 5735 | |
dfcab17e | 5736 | return vco_freq[hpll_freq] * 1000; |
30a970c6 JB |
5737 | } |
5738 | ||
f8bf63fd VS |
5739 | static void vlv_update_cdclk(struct drm_device *dev) |
5740 | { | |
5741 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5742 | ||
164dfd28 | 5743 | dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev); |
43dc52c3 | 5744 | DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n", |
164dfd28 | 5745 | dev_priv->cdclk_freq); |
f8bf63fd VS |
5746 | |
5747 | /* | |
5748 | * Program the gmbus_freq based on the cdclk frequency. | |
5749 | * BSpec erroneously claims we should aim for 4MHz, but | |
5750 | * in fact 1MHz is the correct frequency. | |
5751 | */ | |
164dfd28 | 5752 | I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000)); |
f8bf63fd VS |
5753 | } |
5754 | ||
30a970c6 JB |
5755 | /* Adjust CDclk dividers to allow high res or save power if possible */ |
5756 | static void valleyview_set_cdclk(struct drm_device *dev, int cdclk) | |
5757 | { | |
5758 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5759 | u32 val, cmd; | |
5760 | ||
164dfd28 VK |
5761 | WARN_ON(dev_priv->display.get_display_clock_speed(dev) |
5762 | != dev_priv->cdclk_freq); | |
d60c4473 | 5763 | |
dfcab17e | 5764 | if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */ |
30a970c6 | 5765 | cmd = 2; |
dfcab17e | 5766 | else if (cdclk == 266667) |
30a970c6 JB |
5767 | cmd = 1; |
5768 | else | |
5769 | cmd = 0; | |
5770 | ||
5771 | mutex_lock(&dev_priv->rps.hw_lock); | |
5772 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
5773 | val &= ~DSPFREQGUAR_MASK; | |
5774 | val |= (cmd << DSPFREQGUAR_SHIFT); | |
5775 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
5776 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
5777 | DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT), | |
5778 | 50)) { | |
5779 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
5780 | } | |
5781 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5782 | ||
54433e91 VS |
5783 | mutex_lock(&dev_priv->sb_lock); |
5784 | ||
dfcab17e | 5785 | if (cdclk == 400000) { |
6bcda4f0 | 5786 | u32 divider; |
30a970c6 | 5787 | |
6bcda4f0 | 5788 | divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; |
30a970c6 | 5789 | |
30a970c6 JB |
5790 | /* adjust cdclk divider */ |
5791 | val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); | |
9cf33db5 | 5792 | val &= ~DISPLAY_FREQUENCY_VALUES; |
30a970c6 JB |
5793 | val |= divider; |
5794 | vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val); | |
a877e801 VS |
5795 | |
5796 | if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) & | |
5797 | DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT), | |
5798 | 50)) | |
5799 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
30a970c6 JB |
5800 | } |
5801 | ||
30a970c6 JB |
5802 | /* adjust self-refresh exit latency value */ |
5803 | val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC); | |
5804 | val &= ~0x7f; | |
5805 | ||
5806 | /* | |
5807 | * For high bandwidth configs, we set a higher latency in the bunit | |
5808 | * so that the core display fetch happens in time to avoid underruns. | |
5809 | */ | |
dfcab17e | 5810 | if (cdclk == 400000) |
30a970c6 JB |
5811 | val |= 4500 / 250; /* 4.5 usec */ |
5812 | else | |
5813 | val |= 3000 / 250; /* 3.0 usec */ | |
5814 | vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val); | |
54433e91 | 5815 | |
a580516d | 5816 | mutex_unlock(&dev_priv->sb_lock); |
30a970c6 | 5817 | |
f8bf63fd | 5818 | vlv_update_cdclk(dev); |
30a970c6 JB |
5819 | } |
5820 | ||
383c5a6a VS |
5821 | static void cherryview_set_cdclk(struct drm_device *dev, int cdclk) |
5822 | { | |
5823 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5824 | u32 val, cmd; | |
5825 | ||
164dfd28 VK |
5826 | WARN_ON(dev_priv->display.get_display_clock_speed(dev) |
5827 | != dev_priv->cdclk_freq); | |
383c5a6a VS |
5828 | |
5829 | switch (cdclk) { | |
383c5a6a VS |
5830 | case 333333: |
5831 | case 320000: | |
383c5a6a | 5832 | case 266667: |
383c5a6a | 5833 | case 200000: |
383c5a6a VS |
5834 | break; |
5835 | default: | |
5f77eeb0 | 5836 | MISSING_CASE(cdclk); |
383c5a6a VS |
5837 | return; |
5838 | } | |
5839 | ||
9d0d3fda VS |
5840 | /* |
5841 | * Specs are full of misinformation, but testing on actual | |
5842 | * hardware has shown that we just need to write the desired | |
5843 | * CCK divider into the Punit register. | |
5844 | */ | |
5845 | cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; | |
5846 | ||
383c5a6a VS |
5847 | mutex_lock(&dev_priv->rps.hw_lock); |
5848 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
5849 | val &= ~DSPFREQGUAR_MASK_CHV; | |
5850 | val |= (cmd << DSPFREQGUAR_SHIFT_CHV); | |
5851 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
5852 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
5853 | DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV), | |
5854 | 50)) { | |
5855 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
5856 | } | |
5857 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5858 | ||
5859 | vlv_update_cdclk(dev); | |
5860 | } | |
5861 | ||
30a970c6 JB |
5862 | static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv, |
5863 | int max_pixclk) | |
5864 | { | |
6bcda4f0 | 5865 | int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000; |
6cca3195 | 5866 | int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90; |
29dc7ef3 | 5867 | |
30a970c6 JB |
5868 | /* |
5869 | * Really only a few cases to deal with, as only 4 CDclks are supported: | |
5870 | * 200MHz | |
5871 | * 267MHz | |
29dc7ef3 | 5872 | * 320/333MHz (depends on HPLL freq) |
6cca3195 VS |
5873 | * 400MHz (VLV only) |
5874 | * So we check to see whether we're above 90% (VLV) or 95% (CHV) | |
5875 | * of the lower bin and adjust if needed. | |
e37c67a1 VS |
5876 | * |
5877 | * We seem to get an unstable or solid color picture at 200MHz. | |
5878 | * Not sure what's wrong. For now use 200MHz only when all pipes | |
5879 | * are off. | |
30a970c6 | 5880 | */ |
6cca3195 VS |
5881 | if (!IS_CHERRYVIEW(dev_priv) && |
5882 | max_pixclk > freq_320*limit/100) | |
dfcab17e | 5883 | return 400000; |
6cca3195 | 5884 | else if (max_pixclk > 266667*limit/100) |
29dc7ef3 | 5885 | return freq_320; |
e37c67a1 | 5886 | else if (max_pixclk > 0) |
dfcab17e | 5887 | return 266667; |
e37c67a1 VS |
5888 | else |
5889 | return 200000; | |
30a970c6 JB |
5890 | } |
5891 | ||
f8437dd1 VK |
5892 | static int broxton_calc_cdclk(struct drm_i915_private *dev_priv, |
5893 | int max_pixclk) | |
5894 | { | |
5895 | /* | |
5896 | * FIXME: | |
5897 | * - remove the guardband, it's not needed on BXT | |
5898 | * - set 19.2MHz bypass frequency if there are no active pipes | |
5899 | */ | |
5900 | if (max_pixclk > 576000*9/10) | |
5901 | return 624000; | |
5902 | else if (max_pixclk > 384000*9/10) | |
5903 | return 576000; | |
5904 | else if (max_pixclk > 288000*9/10) | |
5905 | return 384000; | |
5906 | else if (max_pixclk > 144000*9/10) | |
5907 | return 288000; | |
5908 | else | |
5909 | return 144000; | |
5910 | } | |
5911 | ||
a821fc46 ACO |
5912 | /* Compute the max pixel clock for new configuration. Uses atomic state if |
5913 | * that's non-NULL, look at current state otherwise. */ | |
5914 | static int intel_mode_max_pixclk(struct drm_device *dev, | |
5915 | struct drm_atomic_state *state) | |
30a970c6 | 5916 | { |
30a970c6 | 5917 | struct intel_crtc *intel_crtc; |
304603f4 | 5918 | struct intel_crtc_state *crtc_state; |
30a970c6 JB |
5919 | int max_pixclk = 0; |
5920 | ||
d3fcc808 | 5921 | for_each_intel_crtc(dev, intel_crtc) { |
a821fc46 ACO |
5922 | if (state) |
5923 | crtc_state = | |
5924 | intel_atomic_get_crtc_state(state, intel_crtc); | |
5925 | else | |
5926 | crtc_state = intel_crtc->config; | |
304603f4 ACO |
5927 | if (IS_ERR(crtc_state)) |
5928 | return PTR_ERR(crtc_state); | |
5929 | ||
5930 | if (!crtc_state->base.enable) | |
5931 | continue; | |
5932 | ||
5933 | max_pixclk = max(max_pixclk, | |
5934 | crtc_state->base.adjusted_mode.crtc_clock); | |
30a970c6 JB |
5935 | } |
5936 | ||
5937 | return max_pixclk; | |
5938 | } | |
5939 | ||
0a9ab303 | 5940 | static int valleyview_modeset_global_pipes(struct drm_atomic_state *state) |
30a970c6 | 5941 | { |
304603f4 | 5942 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
0a9ab303 ACO |
5943 | struct drm_crtc *crtc; |
5944 | struct drm_crtc_state *crtc_state; | |
a821fc46 | 5945 | int max_pixclk = intel_mode_max_pixclk(state->dev, state); |
0a9ab303 | 5946 | int cdclk, i; |
30a970c6 | 5947 | |
304603f4 ACO |
5948 | if (max_pixclk < 0) |
5949 | return max_pixclk; | |
30a970c6 | 5950 | |
f8437dd1 VK |
5951 | if (IS_VALLEYVIEW(dev_priv)) |
5952 | cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk); | |
5953 | else | |
5954 | cdclk = broxton_calc_cdclk(dev_priv, max_pixclk); | |
5955 | ||
5956 | if (cdclk == dev_priv->cdclk_freq) | |
304603f4 | 5957 | return 0; |
30a970c6 | 5958 | |
0a9ab303 ACO |
5959 | /* add all active pipes to the state */ |
5960 | for_each_crtc(state->dev, crtc) { | |
5961 | if (!crtc->state->enable) | |
5962 | continue; | |
5963 | ||
5964 | crtc_state = drm_atomic_get_crtc_state(state, crtc); | |
5965 | if (IS_ERR(crtc_state)) | |
5966 | return PTR_ERR(crtc_state); | |
5967 | } | |
5968 | ||
2f2d7aa1 | 5969 | /* disable/enable all currently active pipes while we change cdclk */ |
0a9ab303 ACO |
5970 | for_each_crtc_in_state(state, crtc, crtc_state, i) |
5971 | if (crtc_state->enable) | |
5972 | crtc_state->mode_changed = true; | |
304603f4 ACO |
5973 | |
5974 | return 0; | |
30a970c6 JB |
5975 | } |
5976 | ||
1e69cd74 VS |
5977 | static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv) |
5978 | { | |
5979 | unsigned int credits, default_credits; | |
5980 | ||
5981 | if (IS_CHERRYVIEW(dev_priv)) | |
5982 | default_credits = PFI_CREDIT(12); | |
5983 | else | |
5984 | default_credits = PFI_CREDIT(8); | |
5985 | ||
164dfd28 | 5986 | if (DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 1000) >= dev_priv->rps.cz_freq) { |
1e69cd74 VS |
5987 | /* CHV suggested value is 31 or 63 */ |
5988 | if (IS_CHERRYVIEW(dev_priv)) | |
5989 | credits = PFI_CREDIT_31; | |
5990 | else | |
5991 | credits = PFI_CREDIT(15); | |
5992 | } else { | |
5993 | credits = default_credits; | |
5994 | } | |
5995 | ||
5996 | /* | |
5997 | * WA - write default credits before re-programming | |
5998 | * FIXME: should we also set the resend bit here? | |
5999 | */ | |
6000 | I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | | |
6001 | default_credits); | |
6002 | ||
6003 | I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | | |
6004 | credits | PFI_CREDIT_RESEND); | |
6005 | ||
6006 | /* | |
6007 | * FIXME is this guaranteed to clear | |
6008 | * immediately or should we poll for it? | |
6009 | */ | |
6010 | WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND); | |
6011 | } | |
6012 | ||
a821fc46 | 6013 | static void valleyview_modeset_global_resources(struct drm_atomic_state *old_state) |
30a970c6 | 6014 | { |
a821fc46 | 6015 | struct drm_device *dev = old_state->dev; |
30a970c6 | 6016 | struct drm_i915_private *dev_priv = dev->dev_private; |
a821fc46 | 6017 | int max_pixclk = intel_mode_max_pixclk(dev, NULL); |
304603f4 ACO |
6018 | int req_cdclk; |
6019 | ||
a821fc46 ACO |
6020 | /* The path in intel_mode_max_pixclk() with a NULL atomic state should |
6021 | * never fail. */ | |
304603f4 ACO |
6022 | if (WARN_ON(max_pixclk < 0)) |
6023 | return; | |
30a970c6 | 6024 | |
304603f4 | 6025 | req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk); |
30a970c6 | 6026 | |
164dfd28 | 6027 | if (req_cdclk != dev_priv->cdclk_freq) { |
738c05c0 ID |
6028 | /* |
6029 | * FIXME: We can end up here with all power domains off, yet | |
6030 | * with a CDCLK frequency other than the minimum. To account | |
6031 | * for this take the PIPE-A power domain, which covers the HW | |
6032 | * blocks needed for the following programming. This can be | |
6033 | * removed once it's guaranteed that we get here either with | |
6034 | * the minimum CDCLK set, or the required power domains | |
6035 | * enabled. | |
6036 | */ | |
6037 | intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A); | |
6038 | ||
383c5a6a VS |
6039 | if (IS_CHERRYVIEW(dev)) |
6040 | cherryview_set_cdclk(dev, req_cdclk); | |
6041 | else | |
6042 | valleyview_set_cdclk(dev, req_cdclk); | |
738c05c0 | 6043 | |
1e69cd74 VS |
6044 | vlv_program_pfi_credits(dev_priv); |
6045 | ||
738c05c0 | 6046 | intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A); |
383c5a6a | 6047 | } |
30a970c6 JB |
6048 | } |
6049 | ||
89b667f8 JB |
6050 | static void valleyview_crtc_enable(struct drm_crtc *crtc) |
6051 | { | |
6052 | struct drm_device *dev = crtc->dev; | |
a72e4c9f | 6053 | struct drm_i915_private *dev_priv = to_i915(dev); |
89b667f8 JB |
6054 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6055 | struct intel_encoder *encoder; | |
6056 | int pipe = intel_crtc->pipe; | |
23538ef1 | 6057 | bool is_dsi; |
89b667f8 | 6058 | |
83d65738 | 6059 | WARN_ON(!crtc->state->enable); |
89b667f8 JB |
6060 | |
6061 | if (intel_crtc->active) | |
6062 | return; | |
6063 | ||
409ee761 | 6064 | is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI); |
8525a235 | 6065 | |
1ae0d137 VS |
6066 | if (!is_dsi) { |
6067 | if (IS_CHERRYVIEW(dev)) | |
6e3c9717 | 6068 | chv_prepare_pll(intel_crtc, intel_crtc->config); |
1ae0d137 | 6069 | else |
6e3c9717 | 6070 | vlv_prepare_pll(intel_crtc, intel_crtc->config); |
1ae0d137 | 6071 | } |
5b18e57c | 6072 | |
6e3c9717 | 6073 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 6074 | intel_dp_set_m_n(intel_crtc, M1_N1); |
5b18e57c DV |
6075 | |
6076 | intel_set_pipe_timings(intel_crtc); | |
6077 | ||
c14b0485 VS |
6078 | if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) { |
6079 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6080 | ||
6081 | I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY); | |
6082 | I915_WRITE(CHV_CANVAS(pipe), 0); | |
6083 | } | |
6084 | ||
5b18e57c DV |
6085 | i9xx_set_pipeconf(intel_crtc); |
6086 | ||
89b667f8 | 6087 | intel_crtc->active = true; |
89b667f8 | 6088 | |
a72e4c9f | 6089 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4a3436e8 | 6090 | |
89b667f8 JB |
6091 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6092 | if (encoder->pre_pll_enable) | |
6093 | encoder->pre_pll_enable(encoder); | |
6094 | ||
9d556c99 CML |
6095 | if (!is_dsi) { |
6096 | if (IS_CHERRYVIEW(dev)) | |
6e3c9717 | 6097 | chv_enable_pll(intel_crtc, intel_crtc->config); |
9d556c99 | 6098 | else |
6e3c9717 | 6099 | vlv_enable_pll(intel_crtc, intel_crtc->config); |
9d556c99 | 6100 | } |
89b667f8 JB |
6101 | |
6102 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
6103 | if (encoder->pre_enable) | |
6104 | encoder->pre_enable(encoder); | |
6105 | ||
2dd24552 JB |
6106 | i9xx_pfit_enable(intel_crtc); |
6107 | ||
63cbb074 VS |
6108 | intel_crtc_load_lut(crtc); |
6109 | ||
f37fcc2a | 6110 | intel_update_watermarks(crtc); |
e1fdc473 | 6111 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 6112 | |
4b3a9526 VS |
6113 | assert_vblank_disabled(crtc); |
6114 | drm_crtc_vblank_on(crtc); | |
6115 | ||
f9b61ff6 DV |
6116 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6117 | encoder->enable(encoder); | |
89b667f8 JB |
6118 | } |
6119 | ||
f13c2ef3 DV |
6120 | static void i9xx_set_pll_dividers(struct intel_crtc *crtc) |
6121 | { | |
6122 | struct drm_device *dev = crtc->base.dev; | |
6123 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6124 | ||
6e3c9717 ACO |
6125 | I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0); |
6126 | I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1); | |
f13c2ef3 DV |
6127 | } |
6128 | ||
0b8765c6 | 6129 | static void i9xx_crtc_enable(struct drm_crtc *crtc) |
79e53945 JB |
6130 | { |
6131 | struct drm_device *dev = crtc->dev; | |
a72e4c9f | 6132 | struct drm_i915_private *dev_priv = to_i915(dev); |
79e53945 | 6133 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
ef9c3aee | 6134 | struct intel_encoder *encoder; |
79e53945 | 6135 | int pipe = intel_crtc->pipe; |
79e53945 | 6136 | |
83d65738 | 6137 | WARN_ON(!crtc->state->enable); |
08a48469 | 6138 | |
f7abfe8b CW |
6139 | if (intel_crtc->active) |
6140 | return; | |
6141 | ||
f13c2ef3 DV |
6142 | i9xx_set_pll_dividers(intel_crtc); |
6143 | ||
6e3c9717 | 6144 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 6145 | intel_dp_set_m_n(intel_crtc, M1_N1); |
5b18e57c DV |
6146 | |
6147 | intel_set_pipe_timings(intel_crtc); | |
6148 | ||
5b18e57c DV |
6149 | i9xx_set_pipeconf(intel_crtc); |
6150 | ||
f7abfe8b | 6151 | intel_crtc->active = true; |
6b383a7f | 6152 | |
4a3436e8 | 6153 | if (!IS_GEN2(dev)) |
a72e4c9f | 6154 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4a3436e8 | 6155 | |
9d6d9f19 MK |
6156 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6157 | if (encoder->pre_enable) | |
6158 | encoder->pre_enable(encoder); | |
6159 | ||
f6736a1a DV |
6160 | i9xx_enable_pll(intel_crtc); |
6161 | ||
2dd24552 JB |
6162 | i9xx_pfit_enable(intel_crtc); |
6163 | ||
63cbb074 VS |
6164 | intel_crtc_load_lut(crtc); |
6165 | ||
f37fcc2a | 6166 | intel_update_watermarks(crtc); |
e1fdc473 | 6167 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 6168 | |
4b3a9526 VS |
6169 | assert_vblank_disabled(crtc); |
6170 | drm_crtc_vblank_on(crtc); | |
6171 | ||
f9b61ff6 DV |
6172 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6173 | encoder->enable(encoder); | |
0b8765c6 | 6174 | } |
79e53945 | 6175 | |
87476d63 DV |
6176 | static void i9xx_pfit_disable(struct intel_crtc *crtc) |
6177 | { | |
6178 | struct drm_device *dev = crtc->base.dev; | |
6179 | struct drm_i915_private *dev_priv = dev->dev_private; | |
87476d63 | 6180 | |
6e3c9717 | 6181 | if (!crtc->config->gmch_pfit.control) |
328d8e82 | 6182 | return; |
87476d63 | 6183 | |
328d8e82 | 6184 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87476d63 | 6185 | |
328d8e82 DV |
6186 | DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", |
6187 | I915_READ(PFIT_CONTROL)); | |
6188 | I915_WRITE(PFIT_CONTROL, 0); | |
87476d63 DV |
6189 | } |
6190 | ||
0b8765c6 JB |
6191 | static void i9xx_crtc_disable(struct drm_crtc *crtc) |
6192 | { | |
6193 | struct drm_device *dev = crtc->dev; | |
6194 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6195 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 6196 | struct intel_encoder *encoder; |
0b8765c6 | 6197 | int pipe = intel_crtc->pipe; |
ef9c3aee | 6198 | |
f7abfe8b CW |
6199 | if (!intel_crtc->active) |
6200 | return; | |
6201 | ||
6304cd91 VS |
6202 | /* |
6203 | * On gen2 planes are double buffered but the pipe isn't, so we must | |
6204 | * wait for planes to fully turn off before disabling the pipe. | |
564ed191 ID |
6205 | * We also need to wait on all gmch platforms because of the |
6206 | * self-refresh mode constraint explained above. | |
6304cd91 | 6207 | */ |
564ed191 | 6208 | intel_wait_for_vblank(dev, pipe); |
6304cd91 | 6209 | |
4b3a9526 VS |
6210 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6211 | encoder->disable(encoder); | |
6212 | ||
f9b61ff6 DV |
6213 | drm_crtc_vblank_off(crtc); |
6214 | assert_vblank_disabled(crtc); | |
6215 | ||
575f7ab7 | 6216 | intel_disable_pipe(intel_crtc); |
24a1f16d | 6217 | |
87476d63 | 6218 | i9xx_pfit_disable(intel_crtc); |
24a1f16d | 6219 | |
89b667f8 JB |
6220 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6221 | if (encoder->post_disable) | |
6222 | encoder->post_disable(encoder); | |
6223 | ||
409ee761 | 6224 | if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) { |
076ed3b2 CML |
6225 | if (IS_CHERRYVIEW(dev)) |
6226 | chv_disable_pll(dev_priv, pipe); | |
6227 | else if (IS_VALLEYVIEW(dev)) | |
6228 | vlv_disable_pll(dev_priv, pipe); | |
6229 | else | |
1c4e0274 | 6230 | i9xx_disable_pll(intel_crtc); |
076ed3b2 | 6231 | } |
0b8765c6 | 6232 | |
4a3436e8 | 6233 | if (!IS_GEN2(dev)) |
a72e4c9f | 6234 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); |
4a3436e8 | 6235 | |
f7abfe8b | 6236 | intel_crtc->active = false; |
46ba614c | 6237 | intel_update_watermarks(crtc); |
f37fcc2a | 6238 | |
efa9624e | 6239 | mutex_lock(&dev->struct_mutex); |
7ff0ebcc | 6240 | intel_fbc_update(dev); |
efa9624e | 6241 | mutex_unlock(&dev->struct_mutex); |
0b8765c6 JB |
6242 | } |
6243 | ||
ee7b9f93 JB |
6244 | static void i9xx_crtc_off(struct drm_crtc *crtc) |
6245 | { | |
6246 | } | |
6247 | ||
b04c5bd6 BF |
6248 | /* Master function to enable/disable CRTC and corresponding power wells */ |
6249 | void intel_crtc_control(struct drm_crtc *crtc, bool enable) | |
976f8a20 DV |
6250 | { |
6251 | struct drm_device *dev = crtc->dev; | |
6252 | struct drm_i915_private *dev_priv = dev->dev_private; | |
0e572fe7 | 6253 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
0e572fe7 DV |
6254 | enum intel_display_power_domain domain; |
6255 | unsigned long domains; | |
976f8a20 | 6256 | |
0e572fe7 DV |
6257 | if (enable) { |
6258 | if (!intel_crtc->active) { | |
e1e9fb84 DV |
6259 | domains = get_crtc_power_domains(crtc); |
6260 | for_each_power_domain(domain, domains) | |
6261 | intel_display_power_get(dev_priv, domain); | |
6262 | intel_crtc->enabled_power_domains = domains; | |
0e572fe7 DV |
6263 | |
6264 | dev_priv->display.crtc_enable(crtc); | |
ce22dba9 | 6265 | intel_crtc_enable_planes(crtc); |
0e572fe7 DV |
6266 | } |
6267 | } else { | |
6268 | if (intel_crtc->active) { | |
ce22dba9 | 6269 | intel_crtc_disable_planes(crtc); |
0e572fe7 DV |
6270 | dev_priv->display.crtc_disable(crtc); |
6271 | ||
e1e9fb84 DV |
6272 | domains = intel_crtc->enabled_power_domains; |
6273 | for_each_power_domain(domain, domains) | |
6274 | intel_display_power_put(dev_priv, domain); | |
6275 | intel_crtc->enabled_power_domains = 0; | |
0e572fe7 DV |
6276 | } |
6277 | } | |
b04c5bd6 BF |
6278 | } |
6279 | ||
6280 | /** | |
6281 | * Sets the power management mode of the pipe and plane. | |
6282 | */ | |
6283 | void intel_crtc_update_dpms(struct drm_crtc *crtc) | |
6284 | { | |
6285 | struct drm_device *dev = crtc->dev; | |
6286 | struct intel_encoder *intel_encoder; | |
6287 | bool enable = false; | |
6288 | ||
6289 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) | |
6290 | enable |= intel_encoder->connectors_active; | |
6291 | ||
6292 | intel_crtc_control(crtc, enable); | |
0f63cca2 ACO |
6293 | |
6294 | crtc->state->active = enable; | |
976f8a20 DV |
6295 | } |
6296 | ||
cdd59983 CW |
6297 | static void intel_crtc_disable(struct drm_crtc *crtc) |
6298 | { | |
cdd59983 | 6299 | struct drm_device *dev = crtc->dev; |
976f8a20 | 6300 | struct drm_connector *connector; |
ee7b9f93 | 6301 | struct drm_i915_private *dev_priv = dev->dev_private; |
cdd59983 | 6302 | |
976f8a20 | 6303 | /* crtc should still be enabled when we disable it. */ |
83d65738 | 6304 | WARN_ON(!crtc->state->enable); |
976f8a20 | 6305 | |
ce22dba9 | 6306 | intel_crtc_disable_planes(crtc); |
976f8a20 | 6307 | dev_priv->display.crtc_disable(crtc); |
ee7b9f93 JB |
6308 | dev_priv->display.off(crtc); |
6309 | ||
70a101f8 | 6310 | drm_plane_helper_disable(crtc->primary); |
976f8a20 DV |
6311 | |
6312 | /* Update computed state. */ | |
6313 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
6314 | if (!connector->encoder || !connector->encoder->crtc) | |
6315 | continue; | |
6316 | ||
6317 | if (connector->encoder->crtc != crtc) | |
6318 | continue; | |
6319 | ||
6320 | connector->dpms = DRM_MODE_DPMS_OFF; | |
6321 | to_intel_encoder(connector->encoder)->connectors_active = false; | |
cdd59983 CW |
6322 | } |
6323 | } | |
6324 | ||
ea5b213a | 6325 | void intel_encoder_destroy(struct drm_encoder *encoder) |
7e7d76c3 | 6326 | { |
4ef69c7a | 6327 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
ea5b213a | 6328 | |
ea5b213a CW |
6329 | drm_encoder_cleanup(encoder); |
6330 | kfree(intel_encoder); | |
7e7d76c3 JB |
6331 | } |
6332 | ||
9237329d | 6333 | /* Simple dpms helper for encoders with just one connector, no cloning and only |
5ab432ef DV |
6334 | * one kind of off state. It clamps all !ON modes to fully OFF and changes the |
6335 | * state of the entire output pipe. */ | |
9237329d | 6336 | static void intel_encoder_dpms(struct intel_encoder *encoder, int mode) |
7e7d76c3 | 6337 | { |
5ab432ef DV |
6338 | if (mode == DRM_MODE_DPMS_ON) { |
6339 | encoder->connectors_active = true; | |
6340 | ||
b2cabb0e | 6341 | intel_crtc_update_dpms(encoder->base.crtc); |
5ab432ef DV |
6342 | } else { |
6343 | encoder->connectors_active = false; | |
6344 | ||
b2cabb0e | 6345 | intel_crtc_update_dpms(encoder->base.crtc); |
5ab432ef | 6346 | } |
79e53945 JB |
6347 | } |
6348 | ||
0a91ca29 DV |
6349 | /* Cross check the actual hw state with our own modeset state tracking (and it's |
6350 | * internal consistency). */ | |
b980514c | 6351 | static void intel_connector_check_state(struct intel_connector *connector) |
79e53945 | 6352 | { |
0a91ca29 DV |
6353 | if (connector->get_hw_state(connector)) { |
6354 | struct intel_encoder *encoder = connector->encoder; | |
6355 | struct drm_crtc *crtc; | |
6356 | bool encoder_enabled; | |
6357 | enum pipe pipe; | |
6358 | ||
6359 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", | |
6360 | connector->base.base.id, | |
c23cc417 | 6361 | connector->base.name); |
0a91ca29 | 6362 | |
0e32b39c DA |
6363 | /* there is no real hw state for MST connectors */ |
6364 | if (connector->mst_port) | |
6365 | return; | |
6366 | ||
e2c719b7 | 6367 | I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF, |
0a91ca29 | 6368 | "wrong connector dpms state\n"); |
e2c719b7 | 6369 | I915_STATE_WARN(connector->base.encoder != &encoder->base, |
0a91ca29 | 6370 | "active connector not linked to encoder\n"); |
0a91ca29 | 6371 | |
36cd7444 | 6372 | if (encoder) { |
e2c719b7 | 6373 | I915_STATE_WARN(!encoder->connectors_active, |
36cd7444 DA |
6374 | "encoder->connectors_active not set\n"); |
6375 | ||
6376 | encoder_enabled = encoder->get_hw_state(encoder, &pipe); | |
e2c719b7 RC |
6377 | I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n"); |
6378 | if (I915_STATE_WARN_ON(!encoder->base.crtc)) | |
36cd7444 | 6379 | return; |
0a91ca29 | 6380 | |
36cd7444 | 6381 | crtc = encoder->base.crtc; |
0a91ca29 | 6382 | |
83d65738 MR |
6383 | I915_STATE_WARN(!crtc->state->enable, |
6384 | "crtc not enabled\n"); | |
e2c719b7 RC |
6385 | I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n"); |
6386 | I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe, | |
36cd7444 DA |
6387 | "encoder active on the wrong pipe\n"); |
6388 | } | |
0a91ca29 | 6389 | } |
79e53945 JB |
6390 | } |
6391 | ||
08d9bc92 ACO |
6392 | int intel_connector_init(struct intel_connector *connector) |
6393 | { | |
6394 | struct drm_connector_state *connector_state; | |
6395 | ||
6396 | connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL); | |
6397 | if (!connector_state) | |
6398 | return -ENOMEM; | |
6399 | ||
6400 | connector->base.state = connector_state; | |
6401 | return 0; | |
6402 | } | |
6403 | ||
6404 | struct intel_connector *intel_connector_alloc(void) | |
6405 | { | |
6406 | struct intel_connector *connector; | |
6407 | ||
6408 | connector = kzalloc(sizeof *connector, GFP_KERNEL); | |
6409 | if (!connector) | |
6410 | return NULL; | |
6411 | ||
6412 | if (intel_connector_init(connector) < 0) { | |
6413 | kfree(connector); | |
6414 | return NULL; | |
6415 | } | |
6416 | ||
6417 | return connector; | |
6418 | } | |
6419 | ||
5ab432ef DV |
6420 | /* Even simpler default implementation, if there's really no special case to |
6421 | * consider. */ | |
6422 | void intel_connector_dpms(struct drm_connector *connector, int mode) | |
79e53945 | 6423 | { |
5ab432ef DV |
6424 | /* All the simple cases only support two dpms states. */ |
6425 | if (mode != DRM_MODE_DPMS_ON) | |
6426 | mode = DRM_MODE_DPMS_OFF; | |
d4270e57 | 6427 | |
5ab432ef DV |
6428 | if (mode == connector->dpms) |
6429 | return; | |
6430 | ||
6431 | connector->dpms = mode; | |
6432 | ||
6433 | /* Only need to change hw state when actually enabled */ | |
c9976dcf CW |
6434 | if (connector->encoder) |
6435 | intel_encoder_dpms(to_intel_encoder(connector->encoder), mode); | |
0a91ca29 | 6436 | |
b980514c | 6437 | intel_modeset_check_state(connector->dev); |
79e53945 JB |
6438 | } |
6439 | ||
f0947c37 DV |
6440 | /* Simple connector->get_hw_state implementation for encoders that support only |
6441 | * one connector and no cloning and hence the encoder state determines the state | |
6442 | * of the connector. */ | |
6443 | bool intel_connector_get_hw_state(struct intel_connector *connector) | |
ea5b213a | 6444 | { |
24929352 | 6445 | enum pipe pipe = 0; |
f0947c37 | 6446 | struct intel_encoder *encoder = connector->encoder; |
ea5b213a | 6447 | |
f0947c37 | 6448 | return encoder->get_hw_state(encoder, &pipe); |
ea5b213a CW |
6449 | } |
6450 | ||
6d293983 | 6451 | static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state) |
d272ddfa | 6452 | { |
6d293983 ACO |
6453 | if (crtc_state->base.enable && crtc_state->has_pch_encoder) |
6454 | return crtc_state->fdi_lanes; | |
d272ddfa VS |
6455 | |
6456 | return 0; | |
6457 | } | |
6458 | ||
6d293983 | 6459 | static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, |
5cec258b | 6460 | struct intel_crtc_state *pipe_config) |
1857e1da | 6461 | { |
6d293983 ACO |
6462 | struct drm_atomic_state *state = pipe_config->base.state; |
6463 | struct intel_crtc *other_crtc; | |
6464 | struct intel_crtc_state *other_crtc_state; | |
6465 | ||
1857e1da DV |
6466 | DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n", |
6467 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6468 | if (pipe_config->fdi_lanes > 4) { | |
6469 | DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n", | |
6470 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6471 | return -EINVAL; |
1857e1da DV |
6472 | } |
6473 | ||
bafb6553 | 6474 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
1857e1da DV |
6475 | if (pipe_config->fdi_lanes > 2) { |
6476 | DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n", | |
6477 | pipe_config->fdi_lanes); | |
6d293983 | 6478 | return -EINVAL; |
1857e1da | 6479 | } else { |
6d293983 | 6480 | return 0; |
1857e1da DV |
6481 | } |
6482 | } | |
6483 | ||
6484 | if (INTEL_INFO(dev)->num_pipes == 2) | |
6d293983 | 6485 | return 0; |
1857e1da DV |
6486 | |
6487 | /* Ivybridge 3 pipe is really complicated */ | |
6488 | switch (pipe) { | |
6489 | case PIPE_A: | |
6d293983 | 6490 | return 0; |
1857e1da | 6491 | case PIPE_B: |
6d293983 ACO |
6492 | if (pipe_config->fdi_lanes <= 2) |
6493 | return 0; | |
6494 | ||
6495 | other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C)); | |
6496 | other_crtc_state = | |
6497 | intel_atomic_get_crtc_state(state, other_crtc); | |
6498 | if (IS_ERR(other_crtc_state)) | |
6499 | return PTR_ERR(other_crtc_state); | |
6500 | ||
6501 | if (pipe_required_fdi_lanes(other_crtc_state) > 0) { | |
1857e1da DV |
6502 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", |
6503 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6504 | return -EINVAL; |
1857e1da | 6505 | } |
6d293983 | 6506 | return 0; |
1857e1da | 6507 | case PIPE_C: |
251cc67c VS |
6508 | if (pipe_config->fdi_lanes > 2) { |
6509 | DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n", | |
6510 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6511 | return -EINVAL; |
251cc67c | 6512 | } |
6d293983 ACO |
6513 | |
6514 | other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B)); | |
6515 | other_crtc_state = | |
6516 | intel_atomic_get_crtc_state(state, other_crtc); | |
6517 | if (IS_ERR(other_crtc_state)) | |
6518 | return PTR_ERR(other_crtc_state); | |
6519 | ||
6520 | if (pipe_required_fdi_lanes(other_crtc_state) > 2) { | |
1857e1da | 6521 | DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n"); |
6d293983 | 6522 | return -EINVAL; |
1857e1da | 6523 | } |
6d293983 | 6524 | return 0; |
1857e1da DV |
6525 | default: |
6526 | BUG(); | |
6527 | } | |
6528 | } | |
6529 | ||
e29c22c0 DV |
6530 | #define RETRY 1 |
6531 | static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, | |
5cec258b | 6532 | struct intel_crtc_state *pipe_config) |
877d48d5 | 6533 | { |
1857e1da | 6534 | struct drm_device *dev = intel_crtc->base.dev; |
2d112de7 | 6535 | struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
6d293983 ACO |
6536 | int lane, link_bw, fdi_dotclock, ret; |
6537 | bool needs_recompute = false; | |
877d48d5 | 6538 | |
e29c22c0 | 6539 | retry: |
877d48d5 DV |
6540 | /* FDI is a binary signal running at ~2.7GHz, encoding |
6541 | * each output octet as 10 bits. The actual frequency | |
6542 | * is stored as a divider into a 100MHz clock, and the | |
6543 | * mode pixel clock is stored in units of 1KHz. | |
6544 | * Hence the bw of each lane in terms of the mode signal | |
6545 | * is: | |
6546 | */ | |
6547 | link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10; | |
6548 | ||
241bfc38 | 6549 | fdi_dotclock = adjusted_mode->crtc_clock; |
877d48d5 | 6550 | |
2bd89a07 | 6551 | lane = ironlake_get_lanes_required(fdi_dotclock, link_bw, |
877d48d5 DV |
6552 | pipe_config->pipe_bpp); |
6553 | ||
6554 | pipe_config->fdi_lanes = lane; | |
6555 | ||
2bd89a07 | 6556 | intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, |
877d48d5 | 6557 | link_bw, &pipe_config->fdi_m_n); |
1857e1da | 6558 | |
6d293983 ACO |
6559 | ret = ironlake_check_fdi_lanes(intel_crtc->base.dev, |
6560 | intel_crtc->pipe, pipe_config); | |
6561 | if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) { | |
e29c22c0 DV |
6562 | pipe_config->pipe_bpp -= 2*3; |
6563 | DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n", | |
6564 | pipe_config->pipe_bpp); | |
6565 | needs_recompute = true; | |
6566 | pipe_config->bw_constrained = true; | |
6567 | ||
6568 | goto retry; | |
6569 | } | |
6570 | ||
6571 | if (needs_recompute) | |
6572 | return RETRY; | |
6573 | ||
6d293983 | 6574 | return ret; |
877d48d5 DV |
6575 | } |
6576 | ||
42db64ef | 6577 | static void hsw_compute_ips_config(struct intel_crtc *crtc, |
5cec258b | 6578 | struct intel_crtc_state *pipe_config) |
42db64ef | 6579 | { |
d330a953 | 6580 | pipe_config->ips_enabled = i915.enable_ips && |
3c4ca58c | 6581 | hsw_crtc_supports_ips(crtc) && |
b6dfdc9b | 6582 | pipe_config->pipe_bpp <= 24; |
42db64ef PZ |
6583 | } |
6584 | ||
a43f6e0f | 6585 | static int intel_crtc_compute_config(struct intel_crtc *crtc, |
5cec258b | 6586 | struct intel_crtc_state *pipe_config) |
79e53945 | 6587 | { |
a43f6e0f | 6588 | struct drm_device *dev = crtc->base.dev; |
8bd31e67 | 6589 | struct drm_i915_private *dev_priv = dev->dev_private; |
2d112de7 | 6590 | struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
d03c93d4 | 6591 | int ret; |
89749350 | 6592 | |
ad3a4479 | 6593 | /* FIXME should check pixel clock limits on all platforms */ |
cf532bb2 | 6594 | if (INTEL_INFO(dev)->gen < 4) { |
cf532bb2 VS |
6595 | int clock_limit = |
6596 | dev_priv->display.get_display_clock_speed(dev); | |
6597 | ||
6598 | /* | |
6599 | * Enable pixel doubling when the dot clock | |
6600 | * is > 90% of the (display) core speed. | |
6601 | * | |
b397c96b VS |
6602 | * GDG double wide on either pipe, |
6603 | * otherwise pipe A only. | |
cf532bb2 | 6604 | */ |
b397c96b | 6605 | if ((crtc->pipe == PIPE_A || IS_I915G(dev)) && |
241bfc38 | 6606 | adjusted_mode->crtc_clock > clock_limit * 9 / 10) { |
ad3a4479 | 6607 | clock_limit *= 2; |
cf532bb2 | 6608 | pipe_config->double_wide = true; |
ad3a4479 VS |
6609 | } |
6610 | ||
241bfc38 | 6611 | if (adjusted_mode->crtc_clock > clock_limit * 9 / 10) |
e29c22c0 | 6612 | return -EINVAL; |
2c07245f | 6613 | } |
89749350 | 6614 | |
1d1d0e27 VS |
6615 | /* |
6616 | * Pipe horizontal size must be even in: | |
6617 | * - DVO ganged mode | |
6618 | * - LVDS dual channel mode | |
6619 | * - Double wide pipe | |
6620 | */ | |
a93e255f | 6621 | if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) && |
1d1d0e27 VS |
6622 | intel_is_dual_link_lvds(dev)) || pipe_config->double_wide) |
6623 | pipe_config->pipe_src_w &= ~1; | |
6624 | ||
8693a824 DL |
6625 | /* Cantiga+ cannot handle modes with a hsync front porch of 0. |
6626 | * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. | |
44f46b42 CW |
6627 | */ |
6628 | if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) && | |
6629 | adjusted_mode->hsync_start == adjusted_mode->hdisplay) | |
e29c22c0 | 6630 | return -EINVAL; |
44f46b42 | 6631 | |
f5adf94e | 6632 | if (HAS_IPS(dev)) |
a43f6e0f DV |
6633 | hsw_compute_ips_config(crtc, pipe_config); |
6634 | ||
877d48d5 | 6635 | if (pipe_config->has_pch_encoder) |
a43f6e0f | 6636 | return ironlake_fdi_compute_config(crtc, pipe_config); |
877d48d5 | 6637 | |
d03c93d4 CK |
6638 | /* FIXME: remove below call once atomic mode set is place and all crtc |
6639 | * related checks called from atomic_crtc_check function */ | |
6640 | ret = 0; | |
6641 | DRM_DEBUG_KMS("intel_crtc = %p drm_state (pipe_config->base.state) = %p\n", | |
6642 | crtc, pipe_config->base.state); | |
6643 | ret = intel_atomic_setup_scalers(dev, crtc, pipe_config); | |
6644 | ||
6645 | return ret; | |
79e53945 JB |
6646 | } |
6647 | ||
1652d19e VS |
6648 | static int skylake_get_display_clock_speed(struct drm_device *dev) |
6649 | { | |
6650 | struct drm_i915_private *dev_priv = to_i915(dev); | |
6651 | uint32_t lcpll1 = I915_READ(LCPLL1_CTL); | |
6652 | uint32_t cdctl = I915_READ(CDCLK_CTL); | |
6653 | uint32_t linkrate; | |
6654 | ||
6655 | if (!(lcpll1 & LCPLL_PLL_ENABLE)) { | |
6656 | WARN(1, "LCPLL1 not enabled\n"); | |
6657 | return 24000; /* 24MHz is the cd freq with NSSC ref */ | |
6658 | } | |
6659 | ||
6660 | if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540) | |
6661 | return 540000; | |
6662 | ||
6663 | linkrate = (I915_READ(DPLL_CTRL1) & | |
71cd8423 | 6664 | DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1; |
1652d19e | 6665 | |
71cd8423 DL |
6666 | if (linkrate == DPLL_CTRL1_LINK_RATE_2160 || |
6667 | linkrate == DPLL_CTRL1_LINK_RATE_1080) { | |
1652d19e VS |
6668 | /* vco 8640 */ |
6669 | switch (cdctl & CDCLK_FREQ_SEL_MASK) { | |
6670 | case CDCLK_FREQ_450_432: | |
6671 | return 432000; | |
6672 | case CDCLK_FREQ_337_308: | |
6673 | return 308570; | |
6674 | case CDCLK_FREQ_675_617: | |
6675 | return 617140; | |
6676 | default: | |
6677 | WARN(1, "Unknown cd freq selection\n"); | |
6678 | } | |
6679 | } else { | |
6680 | /* vco 8100 */ | |
6681 | switch (cdctl & CDCLK_FREQ_SEL_MASK) { | |
6682 | case CDCLK_FREQ_450_432: | |
6683 | return 450000; | |
6684 | case CDCLK_FREQ_337_308: | |
6685 | return 337500; | |
6686 | case CDCLK_FREQ_675_617: | |
6687 | return 675000; | |
6688 | default: | |
6689 | WARN(1, "Unknown cd freq selection\n"); | |
6690 | } | |
6691 | } | |
6692 | ||
6693 | /* error case, do as if DPLL0 isn't enabled */ | |
6694 | return 24000; | |
6695 | } | |
6696 | ||
6697 | static int broadwell_get_display_clock_speed(struct drm_device *dev) | |
6698 | { | |
6699 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6700 | uint32_t lcpll = I915_READ(LCPLL_CTL); | |
6701 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; | |
6702 | ||
6703 | if (lcpll & LCPLL_CD_SOURCE_FCLK) | |
6704 | return 800000; | |
6705 | else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
6706 | return 450000; | |
6707 | else if (freq == LCPLL_CLK_FREQ_450) | |
6708 | return 450000; | |
6709 | else if (freq == LCPLL_CLK_FREQ_54O_BDW) | |
6710 | return 540000; | |
6711 | else if (freq == LCPLL_CLK_FREQ_337_5_BDW) | |
6712 | return 337500; | |
6713 | else | |
6714 | return 675000; | |
6715 | } | |
6716 | ||
6717 | static int haswell_get_display_clock_speed(struct drm_device *dev) | |
6718 | { | |
6719 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6720 | uint32_t lcpll = I915_READ(LCPLL_CTL); | |
6721 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; | |
6722 | ||
6723 | if (lcpll & LCPLL_CD_SOURCE_FCLK) | |
6724 | return 800000; | |
6725 | else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
6726 | return 450000; | |
6727 | else if (freq == LCPLL_CLK_FREQ_450) | |
6728 | return 450000; | |
6729 | else if (IS_HSW_ULT(dev)) | |
6730 | return 337500; | |
6731 | else | |
6732 | return 540000; | |
79e53945 JB |
6733 | } |
6734 | ||
25eb05fc JB |
6735 | static int valleyview_get_display_clock_speed(struct drm_device *dev) |
6736 | { | |
d197b7d3 | 6737 | struct drm_i915_private *dev_priv = dev->dev_private; |
d197b7d3 VS |
6738 | u32 val; |
6739 | int divider; | |
6740 | ||
6bcda4f0 VS |
6741 | if (dev_priv->hpll_freq == 0) |
6742 | dev_priv->hpll_freq = valleyview_get_vco(dev_priv); | |
6743 | ||
a580516d | 6744 | mutex_lock(&dev_priv->sb_lock); |
d197b7d3 | 6745 | val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); |
a580516d | 6746 | mutex_unlock(&dev_priv->sb_lock); |
d197b7d3 VS |
6747 | |
6748 | divider = val & DISPLAY_FREQUENCY_VALUES; | |
6749 | ||
7d007f40 VS |
6750 | WARN((val & DISPLAY_FREQUENCY_STATUS) != |
6751 | (divider << DISPLAY_FREQUENCY_STATUS_SHIFT), | |
6752 | "cdclk change in progress\n"); | |
6753 | ||
6bcda4f0 | 6754 | return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1); |
25eb05fc JB |
6755 | } |
6756 | ||
b37a6434 VS |
6757 | static int ilk_get_display_clock_speed(struct drm_device *dev) |
6758 | { | |
6759 | return 450000; | |
6760 | } | |
6761 | ||
e70236a8 JB |
6762 | static int i945_get_display_clock_speed(struct drm_device *dev) |
6763 | { | |
6764 | return 400000; | |
6765 | } | |
79e53945 | 6766 | |
e70236a8 | 6767 | static int i915_get_display_clock_speed(struct drm_device *dev) |
79e53945 | 6768 | { |
e907f170 | 6769 | return 333333; |
e70236a8 | 6770 | } |
79e53945 | 6771 | |
e70236a8 JB |
6772 | static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) |
6773 | { | |
6774 | return 200000; | |
6775 | } | |
79e53945 | 6776 | |
257a7ffc DV |
6777 | static int pnv_get_display_clock_speed(struct drm_device *dev) |
6778 | { | |
6779 | u16 gcfgc = 0; | |
6780 | ||
6781 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); | |
6782 | ||
6783 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
6784 | case GC_DISPLAY_CLOCK_267_MHZ_PNV: | |
e907f170 | 6785 | return 266667; |
257a7ffc | 6786 | case GC_DISPLAY_CLOCK_333_MHZ_PNV: |
e907f170 | 6787 | return 333333; |
257a7ffc | 6788 | case GC_DISPLAY_CLOCK_444_MHZ_PNV: |
e907f170 | 6789 | return 444444; |
257a7ffc DV |
6790 | case GC_DISPLAY_CLOCK_200_MHZ_PNV: |
6791 | return 200000; | |
6792 | default: | |
6793 | DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc); | |
6794 | case GC_DISPLAY_CLOCK_133_MHZ_PNV: | |
e907f170 | 6795 | return 133333; |
257a7ffc | 6796 | case GC_DISPLAY_CLOCK_167_MHZ_PNV: |
e907f170 | 6797 | return 166667; |
257a7ffc DV |
6798 | } |
6799 | } | |
6800 | ||
e70236a8 JB |
6801 | static int i915gm_get_display_clock_speed(struct drm_device *dev) |
6802 | { | |
6803 | u16 gcfgc = 0; | |
79e53945 | 6804 | |
e70236a8 JB |
6805 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
6806 | ||
6807 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) | |
e907f170 | 6808 | return 133333; |
e70236a8 JB |
6809 | else { |
6810 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
6811 | case GC_DISPLAY_CLOCK_333_MHZ: | |
e907f170 | 6812 | return 333333; |
e70236a8 JB |
6813 | default: |
6814 | case GC_DISPLAY_CLOCK_190_200_MHZ: | |
6815 | return 190000; | |
79e53945 | 6816 | } |
e70236a8 JB |
6817 | } |
6818 | } | |
6819 | ||
6820 | static int i865_get_display_clock_speed(struct drm_device *dev) | |
6821 | { | |
e907f170 | 6822 | return 266667; |
e70236a8 JB |
6823 | } |
6824 | ||
1b1d2716 | 6825 | static int i85x_get_display_clock_speed(struct drm_device *dev) |
e70236a8 JB |
6826 | { |
6827 | u16 hpllcc = 0; | |
1b1d2716 | 6828 | |
65cd2b3f VS |
6829 | /* |
6830 | * 852GM/852GMV only supports 133 MHz and the HPLLCC | |
6831 | * encoding is different :( | |
6832 | * FIXME is this the right way to detect 852GM/852GMV? | |
6833 | */ | |
6834 | if (dev->pdev->revision == 0x1) | |
6835 | return 133333; | |
6836 | ||
1b1d2716 VS |
6837 | pci_bus_read_config_word(dev->pdev->bus, |
6838 | PCI_DEVFN(0, 3), HPLLCC, &hpllcc); | |
6839 | ||
e70236a8 JB |
6840 | /* Assume that the hardware is in the high speed state. This |
6841 | * should be the default. | |
6842 | */ | |
6843 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { | |
6844 | case GC_CLOCK_133_200: | |
1b1d2716 | 6845 | case GC_CLOCK_133_200_2: |
e70236a8 JB |
6846 | case GC_CLOCK_100_200: |
6847 | return 200000; | |
6848 | case GC_CLOCK_166_250: | |
6849 | return 250000; | |
6850 | case GC_CLOCK_100_133: | |
e907f170 | 6851 | return 133333; |
1b1d2716 VS |
6852 | case GC_CLOCK_133_266: |
6853 | case GC_CLOCK_133_266_2: | |
6854 | case GC_CLOCK_166_266: | |
6855 | return 266667; | |
e70236a8 | 6856 | } |
79e53945 | 6857 | |
e70236a8 JB |
6858 | /* Shouldn't happen */ |
6859 | return 0; | |
6860 | } | |
79e53945 | 6861 | |
e70236a8 JB |
6862 | static int i830_get_display_clock_speed(struct drm_device *dev) |
6863 | { | |
e907f170 | 6864 | return 133333; |
79e53945 JB |
6865 | } |
6866 | ||
2c07245f | 6867 | static void |
a65851af | 6868 | intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den) |
2c07245f | 6869 | { |
a65851af VS |
6870 | while (*num > DATA_LINK_M_N_MASK || |
6871 | *den > DATA_LINK_M_N_MASK) { | |
2c07245f ZW |
6872 | *num >>= 1; |
6873 | *den >>= 1; | |
6874 | } | |
6875 | } | |
6876 | ||
a65851af VS |
6877 | static void compute_m_n(unsigned int m, unsigned int n, |
6878 | uint32_t *ret_m, uint32_t *ret_n) | |
6879 | { | |
6880 | *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); | |
6881 | *ret_m = div_u64((uint64_t) m * *ret_n, n); | |
6882 | intel_reduce_m_n_ratio(ret_m, ret_n); | |
6883 | } | |
6884 | ||
e69d0bc1 DV |
6885 | void |
6886 | intel_link_compute_m_n(int bits_per_pixel, int nlanes, | |
6887 | int pixel_clock, int link_clock, | |
6888 | struct intel_link_m_n *m_n) | |
2c07245f | 6889 | { |
e69d0bc1 | 6890 | m_n->tu = 64; |
a65851af VS |
6891 | |
6892 | compute_m_n(bits_per_pixel * pixel_clock, | |
6893 | link_clock * nlanes * 8, | |
6894 | &m_n->gmch_m, &m_n->gmch_n); | |
6895 | ||
6896 | compute_m_n(pixel_clock, link_clock, | |
6897 | &m_n->link_m, &m_n->link_n); | |
2c07245f ZW |
6898 | } |
6899 | ||
a7615030 CW |
6900 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
6901 | { | |
d330a953 JN |
6902 | if (i915.panel_use_ssc >= 0) |
6903 | return i915.panel_use_ssc != 0; | |
41aa3448 | 6904 | return dev_priv->vbt.lvds_use_ssc |
435793df | 6905 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
a7615030 CW |
6906 | } |
6907 | ||
a93e255f ACO |
6908 | static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state, |
6909 | int num_connectors) | |
c65d77d8 | 6910 | { |
a93e255f | 6911 | struct drm_device *dev = crtc_state->base.crtc->dev; |
c65d77d8 JB |
6912 | struct drm_i915_private *dev_priv = dev->dev_private; |
6913 | int refclk; | |
6914 | ||
a93e255f ACO |
6915 | WARN_ON(!crtc_state->base.state); |
6916 | ||
5ab7b0b7 | 6917 | if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) { |
9a0ea498 | 6918 | refclk = 100000; |
a93e255f | 6919 | } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
c65d77d8 | 6920 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) { |
e91e941b VS |
6921 | refclk = dev_priv->vbt.lvds_ssc_freq; |
6922 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
c65d77d8 JB |
6923 | } else if (!IS_GEN2(dev)) { |
6924 | refclk = 96000; | |
6925 | } else { | |
6926 | refclk = 48000; | |
6927 | } | |
6928 | ||
6929 | return refclk; | |
6930 | } | |
6931 | ||
7429e9d4 | 6932 | static uint32_t pnv_dpll_compute_fp(struct dpll *dpll) |
c65d77d8 | 6933 | { |
7df00d7a | 6934 | return (1 << dpll->n) << 16 | dpll->m2; |
7429e9d4 | 6935 | } |
f47709a9 | 6936 | |
7429e9d4 DV |
6937 | static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll) |
6938 | { | |
6939 | return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; | |
c65d77d8 JB |
6940 | } |
6941 | ||
f47709a9 | 6942 | static void i9xx_update_pll_dividers(struct intel_crtc *crtc, |
190f68c5 | 6943 | struct intel_crtc_state *crtc_state, |
a7516a05 JB |
6944 | intel_clock_t *reduced_clock) |
6945 | { | |
f47709a9 | 6946 | struct drm_device *dev = crtc->base.dev; |
a7516a05 JB |
6947 | u32 fp, fp2 = 0; |
6948 | ||
6949 | if (IS_PINEVIEW(dev)) { | |
190f68c5 | 6950 | fp = pnv_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 6951 | if (reduced_clock) |
7429e9d4 | 6952 | fp2 = pnv_dpll_compute_fp(reduced_clock); |
a7516a05 | 6953 | } else { |
190f68c5 | 6954 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 6955 | if (reduced_clock) |
7429e9d4 | 6956 | fp2 = i9xx_dpll_compute_fp(reduced_clock); |
a7516a05 JB |
6957 | } |
6958 | ||
190f68c5 | 6959 | crtc_state->dpll_hw_state.fp0 = fp; |
a7516a05 | 6960 | |
f47709a9 | 6961 | crtc->lowfreq_avail = false; |
a93e255f | 6962 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ab585dea | 6963 | reduced_clock) { |
190f68c5 | 6964 | crtc_state->dpll_hw_state.fp1 = fp2; |
f47709a9 | 6965 | crtc->lowfreq_avail = true; |
a7516a05 | 6966 | } else { |
190f68c5 | 6967 | crtc_state->dpll_hw_state.fp1 = fp; |
a7516a05 JB |
6968 | } |
6969 | } | |
6970 | ||
5e69f97f CML |
6971 | static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe |
6972 | pipe) | |
89b667f8 JB |
6973 | { |
6974 | u32 reg_val; | |
6975 | ||
6976 | /* | |
6977 | * PLLB opamp always calibrates to max value of 0x3f, force enable it | |
6978 | * and set it to a reasonable value instead. | |
6979 | */ | |
ab3c759a | 6980 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 JB |
6981 | reg_val &= 0xffffff00; |
6982 | reg_val |= 0x00000030; | |
ab3c759a | 6983 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 6984 | |
ab3c759a | 6985 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
6986 | reg_val &= 0x8cffffff; |
6987 | reg_val = 0x8c000000; | |
ab3c759a | 6988 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 | 6989 | |
ab3c759a | 6990 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 | 6991 | reg_val &= 0xffffff00; |
ab3c759a | 6992 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 6993 | |
ab3c759a | 6994 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
6995 | reg_val &= 0x00ffffff; |
6996 | reg_val |= 0xb0000000; | |
ab3c759a | 6997 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 JB |
6998 | } |
6999 | ||
b551842d DV |
7000 | static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, |
7001 | struct intel_link_m_n *m_n) | |
7002 | { | |
7003 | struct drm_device *dev = crtc->base.dev; | |
7004 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7005 | int pipe = crtc->pipe; | |
7006 | ||
e3b95f1e DV |
7007 | I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
7008 | I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n); | |
7009 | I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m); | |
7010 | I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n); | |
b551842d DV |
7011 | } |
7012 | ||
7013 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, | |
f769cd24 VK |
7014 | struct intel_link_m_n *m_n, |
7015 | struct intel_link_m_n *m2_n2) | |
b551842d DV |
7016 | { |
7017 | struct drm_device *dev = crtc->base.dev; | |
7018 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7019 | int pipe = crtc->pipe; | |
6e3c9717 | 7020 | enum transcoder transcoder = crtc->config->cpu_transcoder; |
b551842d DV |
7021 | |
7022 | if (INTEL_INFO(dev)->gen >= 5) { | |
7023 | I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); | |
7024 | I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); | |
7025 | I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); | |
7026 | I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n); | |
f769cd24 VK |
7027 | /* M2_N2 registers to be set only for gen < 8 (M2_N2 available |
7028 | * for gen < 8) and if DRRS is supported (to make sure the | |
7029 | * registers are not unnecessarily accessed). | |
7030 | */ | |
44395bfe | 7031 | if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) && |
6e3c9717 | 7032 | crtc->config->has_drrs) { |
f769cd24 VK |
7033 | I915_WRITE(PIPE_DATA_M2(transcoder), |
7034 | TU_SIZE(m2_n2->tu) | m2_n2->gmch_m); | |
7035 | I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n); | |
7036 | I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m); | |
7037 | I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n); | |
7038 | } | |
b551842d | 7039 | } else { |
e3b95f1e DV |
7040 | I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
7041 | I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n); | |
7042 | I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m); | |
7043 | I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n); | |
b551842d DV |
7044 | } |
7045 | } | |
7046 | ||
fe3cd48d | 7047 | void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n) |
03afc4a2 | 7048 | { |
fe3cd48d R |
7049 | struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL; |
7050 | ||
7051 | if (m_n == M1_N1) { | |
7052 | dp_m_n = &crtc->config->dp_m_n; | |
7053 | dp_m2_n2 = &crtc->config->dp_m2_n2; | |
7054 | } else if (m_n == M2_N2) { | |
7055 | ||
7056 | /* | |
7057 | * M2_N2 registers are not supported. Hence m2_n2 divider value | |
7058 | * needs to be programmed into M1_N1. | |
7059 | */ | |
7060 | dp_m_n = &crtc->config->dp_m2_n2; | |
7061 | } else { | |
7062 | DRM_ERROR("Unsupported divider value\n"); | |
7063 | return; | |
7064 | } | |
7065 | ||
6e3c9717 ACO |
7066 | if (crtc->config->has_pch_encoder) |
7067 | intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n); | |
03afc4a2 | 7068 | else |
fe3cd48d | 7069 | intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2); |
03afc4a2 DV |
7070 | } |
7071 | ||
d288f65f | 7072 | static void vlv_update_pll(struct intel_crtc *crtc, |
5cec258b | 7073 | struct intel_crtc_state *pipe_config) |
bdd4b6a6 DV |
7074 | { |
7075 | u32 dpll, dpll_md; | |
7076 | ||
7077 | /* | |
7078 | * Enable DPIO clock input. We should never disable the reference | |
7079 | * clock for pipe B, since VGA hotplug / manual detection depends | |
7080 | * on it. | |
7081 | */ | |
7082 | dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV | | |
7083 | DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV; | |
7084 | /* We should never disable this, set it here for state tracking */ | |
7085 | if (crtc->pipe == PIPE_B) | |
7086 | dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
7087 | dpll |= DPLL_VCO_ENABLE; | |
d288f65f | 7088 | pipe_config->dpll_hw_state.dpll = dpll; |
bdd4b6a6 | 7089 | |
d288f65f | 7090 | dpll_md = (pipe_config->pixel_multiplier - 1) |
bdd4b6a6 | 7091 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
d288f65f | 7092 | pipe_config->dpll_hw_state.dpll_md = dpll_md; |
bdd4b6a6 DV |
7093 | } |
7094 | ||
d288f65f | 7095 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 7096 | const struct intel_crtc_state *pipe_config) |
a0c4da24 | 7097 | { |
f47709a9 | 7098 | struct drm_device *dev = crtc->base.dev; |
a0c4da24 | 7099 | struct drm_i915_private *dev_priv = dev->dev_private; |
f47709a9 | 7100 | int pipe = crtc->pipe; |
bdd4b6a6 | 7101 | u32 mdiv; |
a0c4da24 | 7102 | u32 bestn, bestm1, bestm2, bestp1, bestp2; |
bdd4b6a6 | 7103 | u32 coreclk, reg_val; |
a0c4da24 | 7104 | |
a580516d | 7105 | mutex_lock(&dev_priv->sb_lock); |
09153000 | 7106 | |
d288f65f VS |
7107 | bestn = pipe_config->dpll.n; |
7108 | bestm1 = pipe_config->dpll.m1; | |
7109 | bestm2 = pipe_config->dpll.m2; | |
7110 | bestp1 = pipe_config->dpll.p1; | |
7111 | bestp2 = pipe_config->dpll.p2; | |
a0c4da24 | 7112 | |
89b667f8 JB |
7113 | /* See eDP HDMI DPIO driver vbios notes doc */ |
7114 | ||
7115 | /* PLL B needs special handling */ | |
bdd4b6a6 | 7116 | if (pipe == PIPE_B) |
5e69f97f | 7117 | vlv_pllb_recal_opamp(dev_priv, pipe); |
89b667f8 JB |
7118 | |
7119 | /* Set up Tx target for periodic Rcomp update */ | |
ab3c759a | 7120 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f); |
89b667f8 JB |
7121 | |
7122 | /* Disable target IRef on PLL */ | |
ab3c759a | 7123 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe)); |
89b667f8 | 7124 | reg_val &= 0x00ffffff; |
ab3c759a | 7125 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val); |
89b667f8 JB |
7126 | |
7127 | /* Disable fast lock */ | |
ab3c759a | 7128 | vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610); |
89b667f8 JB |
7129 | |
7130 | /* Set idtafcrecal before PLL is enabled */ | |
a0c4da24 JB |
7131 | mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); |
7132 | mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); | |
7133 | mdiv |= ((bestn << DPIO_N_SHIFT)); | |
a0c4da24 | 7134 | mdiv |= (1 << DPIO_K_SHIFT); |
7df5080b JB |
7135 | |
7136 | /* | |
7137 | * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, | |
7138 | * but we don't support that). | |
7139 | * Note: don't use the DAC post divider as it seems unstable. | |
7140 | */ | |
7141 | mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); | |
ab3c759a | 7142 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 7143 | |
a0c4da24 | 7144 | mdiv |= DPIO_ENABLE_CALIBRATION; |
ab3c759a | 7145 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 7146 | |
89b667f8 | 7147 | /* Set HBR and RBR LPF coefficients */ |
d288f65f | 7148 | if (pipe_config->port_clock == 162000 || |
409ee761 ACO |
7149 | intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) || |
7150 | intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) | |
ab3c759a | 7151 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
885b0120 | 7152 | 0x009f0003); |
89b667f8 | 7153 | else |
ab3c759a | 7154 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
89b667f8 JB |
7155 | 0x00d0000f); |
7156 | ||
681a8504 | 7157 | if (pipe_config->has_dp_encoder) { |
89b667f8 | 7158 | /* Use SSC source */ |
bdd4b6a6 | 7159 | if (pipe == PIPE_A) |
ab3c759a | 7160 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7161 | 0x0df40000); |
7162 | else | |
ab3c759a | 7163 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7164 | 0x0df70000); |
7165 | } else { /* HDMI or VGA */ | |
7166 | /* Use bend source */ | |
bdd4b6a6 | 7167 | if (pipe == PIPE_A) |
ab3c759a | 7168 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7169 | 0x0df70000); |
7170 | else | |
ab3c759a | 7171 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7172 | 0x0df40000); |
7173 | } | |
a0c4da24 | 7174 | |
ab3c759a | 7175 | coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)); |
89b667f8 | 7176 | coreclk = (coreclk & 0x0000ff00) | 0x01c00000; |
409ee761 ACO |
7177 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || |
7178 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) | |
89b667f8 | 7179 | coreclk |= 0x01000000; |
ab3c759a | 7180 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk); |
a0c4da24 | 7181 | |
ab3c759a | 7182 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000); |
a580516d | 7183 | mutex_unlock(&dev_priv->sb_lock); |
a0c4da24 JB |
7184 | } |
7185 | ||
d288f65f | 7186 | static void chv_update_pll(struct intel_crtc *crtc, |
5cec258b | 7187 | struct intel_crtc_state *pipe_config) |
1ae0d137 | 7188 | { |
d288f65f | 7189 | pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV | |
1ae0d137 VS |
7190 | DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS | |
7191 | DPLL_VCO_ENABLE; | |
7192 | if (crtc->pipe != PIPE_A) | |
d288f65f | 7193 | pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; |
1ae0d137 | 7194 | |
d288f65f VS |
7195 | pipe_config->dpll_hw_state.dpll_md = |
7196 | (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
1ae0d137 VS |
7197 | } |
7198 | ||
d288f65f | 7199 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 7200 | const struct intel_crtc_state *pipe_config) |
9d556c99 CML |
7201 | { |
7202 | struct drm_device *dev = crtc->base.dev; | |
7203 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7204 | int pipe = crtc->pipe; | |
7205 | int dpll_reg = DPLL(crtc->pipe); | |
7206 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
9cbe40c1 | 7207 | u32 loopfilter, tribuf_calcntr; |
9d556c99 | 7208 | u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac; |
a945ce7e | 7209 | u32 dpio_val; |
9cbe40c1 | 7210 | int vco; |
9d556c99 | 7211 | |
d288f65f VS |
7212 | bestn = pipe_config->dpll.n; |
7213 | bestm2_frac = pipe_config->dpll.m2 & 0x3fffff; | |
7214 | bestm1 = pipe_config->dpll.m1; | |
7215 | bestm2 = pipe_config->dpll.m2 >> 22; | |
7216 | bestp1 = pipe_config->dpll.p1; | |
7217 | bestp2 = pipe_config->dpll.p2; | |
9cbe40c1 | 7218 | vco = pipe_config->dpll.vco; |
a945ce7e | 7219 | dpio_val = 0; |
9cbe40c1 | 7220 | loopfilter = 0; |
9d556c99 CML |
7221 | |
7222 | /* | |
7223 | * Enable Refclk and SSC | |
7224 | */ | |
a11b0703 | 7225 | I915_WRITE(dpll_reg, |
d288f65f | 7226 | pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); |
a11b0703 | 7227 | |
a580516d | 7228 | mutex_lock(&dev_priv->sb_lock); |
9d556c99 | 7229 | |
9d556c99 CML |
7230 | /* p1 and p2 divider */ |
7231 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port), | |
7232 | 5 << DPIO_CHV_S1_DIV_SHIFT | | |
7233 | bestp1 << DPIO_CHV_P1_DIV_SHIFT | | |
7234 | bestp2 << DPIO_CHV_P2_DIV_SHIFT | | |
7235 | 1 << DPIO_CHV_K_DIV_SHIFT); | |
7236 | ||
7237 | /* Feedback post-divider - m2 */ | |
7238 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2); | |
7239 | ||
7240 | /* Feedback refclk divider - n and m1 */ | |
7241 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port), | |
7242 | DPIO_CHV_M1_DIV_BY_2 | | |
7243 | 1 << DPIO_CHV_N_DIV_SHIFT); | |
7244 | ||
7245 | /* M2 fraction division */ | |
a945ce7e VP |
7246 | if (bestm2_frac) |
7247 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac); | |
9d556c99 CML |
7248 | |
7249 | /* M2 fraction division enable */ | |
a945ce7e VP |
7250 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); |
7251 | dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN); | |
7252 | dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT); | |
7253 | if (bestm2_frac) | |
7254 | dpio_val |= DPIO_CHV_FRAC_DIV_EN; | |
7255 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val); | |
9d556c99 | 7256 | |
de3a0fde VP |
7257 | /* Program digital lock detect threshold */ |
7258 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port)); | |
7259 | dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK | | |
7260 | DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE); | |
7261 | dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT); | |
7262 | if (!bestm2_frac) | |
7263 | dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE; | |
7264 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val); | |
7265 | ||
9d556c99 | 7266 | /* Loop filter */ |
9cbe40c1 VP |
7267 | if (vco == 5400000) { |
7268 | loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7269 | loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT); | |
7270 | loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7271 | tribuf_calcntr = 0x9; | |
7272 | } else if (vco <= 6200000) { | |
7273 | loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7274 | loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT); | |
7275 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7276 | tribuf_calcntr = 0x9; | |
7277 | } else if (vco <= 6480000) { | |
7278 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7279 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
7280 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7281 | tribuf_calcntr = 0x8; | |
7282 | } else { | |
7283 | /* Not supported. Apply the same limits as in the max case */ | |
7284 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7285 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
7286 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7287 | tribuf_calcntr = 0; | |
7288 | } | |
9d556c99 CML |
7289 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter); |
7290 | ||
968040b2 | 7291 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port)); |
9cbe40c1 VP |
7292 | dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK; |
7293 | dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT); | |
7294 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val); | |
7295 | ||
9d556c99 CML |
7296 | /* AFC Recal */ |
7297 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), | |
7298 | vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) | | |
7299 | DPIO_AFC_RECAL); | |
7300 | ||
a580516d | 7301 | mutex_unlock(&dev_priv->sb_lock); |
9d556c99 CML |
7302 | } |
7303 | ||
d288f65f VS |
7304 | /** |
7305 | * vlv_force_pll_on - forcibly enable just the PLL | |
7306 | * @dev_priv: i915 private structure | |
7307 | * @pipe: pipe PLL to enable | |
7308 | * @dpll: PLL configuration | |
7309 | * | |
7310 | * Enable the PLL for @pipe using the supplied @dpll config. To be used | |
7311 | * in cases where we need the PLL enabled even when @pipe is not going to | |
7312 | * be enabled. | |
7313 | */ | |
7314 | void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe, | |
7315 | const struct dpll *dpll) | |
7316 | { | |
7317 | struct intel_crtc *crtc = | |
7318 | to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe)); | |
5cec258b | 7319 | struct intel_crtc_state pipe_config = { |
a93e255f | 7320 | .base.crtc = &crtc->base, |
d288f65f VS |
7321 | .pixel_multiplier = 1, |
7322 | .dpll = *dpll, | |
7323 | }; | |
7324 | ||
7325 | if (IS_CHERRYVIEW(dev)) { | |
7326 | chv_update_pll(crtc, &pipe_config); | |
7327 | chv_prepare_pll(crtc, &pipe_config); | |
7328 | chv_enable_pll(crtc, &pipe_config); | |
7329 | } else { | |
7330 | vlv_update_pll(crtc, &pipe_config); | |
7331 | vlv_prepare_pll(crtc, &pipe_config); | |
7332 | vlv_enable_pll(crtc, &pipe_config); | |
7333 | } | |
7334 | } | |
7335 | ||
7336 | /** | |
7337 | * vlv_force_pll_off - forcibly disable just the PLL | |
7338 | * @dev_priv: i915 private structure | |
7339 | * @pipe: pipe PLL to disable | |
7340 | * | |
7341 | * Disable the PLL for @pipe. To be used in cases where we need | |
7342 | * the PLL enabled even when @pipe is not going to be enabled. | |
7343 | */ | |
7344 | void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe) | |
7345 | { | |
7346 | if (IS_CHERRYVIEW(dev)) | |
7347 | chv_disable_pll(to_i915(dev), pipe); | |
7348 | else | |
7349 | vlv_disable_pll(to_i915(dev), pipe); | |
7350 | } | |
7351 | ||
f47709a9 | 7352 | static void i9xx_update_pll(struct intel_crtc *crtc, |
190f68c5 | 7353 | struct intel_crtc_state *crtc_state, |
f47709a9 | 7354 | intel_clock_t *reduced_clock, |
eb1cbe48 DV |
7355 | int num_connectors) |
7356 | { | |
f47709a9 | 7357 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 7358 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 DV |
7359 | u32 dpll; |
7360 | bool is_sdvo; | |
190f68c5 | 7361 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 7362 | |
190f68c5 | 7363 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 7364 | |
a93e255f ACO |
7365 | is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) || |
7366 | intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI); | |
eb1cbe48 DV |
7367 | |
7368 | dpll = DPLL_VGA_MODE_DIS; | |
7369 | ||
a93e255f | 7370 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
eb1cbe48 DV |
7371 | dpll |= DPLLB_MODE_LVDS; |
7372 | else | |
7373 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
6cc5f341 | 7374 | |
ef1b460d | 7375 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
190f68c5 | 7376 | dpll |= (crtc_state->pixel_multiplier - 1) |
198a037f | 7377 | << SDVO_MULTIPLIER_SHIFT_HIRES; |
eb1cbe48 | 7378 | } |
198a037f DV |
7379 | |
7380 | if (is_sdvo) | |
4a33e48d | 7381 | dpll |= DPLL_SDVO_HIGH_SPEED; |
198a037f | 7382 | |
190f68c5 | 7383 | if (crtc_state->has_dp_encoder) |
4a33e48d | 7384 | dpll |= DPLL_SDVO_HIGH_SPEED; |
eb1cbe48 DV |
7385 | |
7386 | /* compute bitmask from p1 value */ | |
7387 | if (IS_PINEVIEW(dev)) | |
7388 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; | |
7389 | else { | |
7390 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
7391 | if (IS_G4X(dev) && reduced_clock) | |
7392 | dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; | |
7393 | } | |
7394 | switch (clock->p2) { | |
7395 | case 5: | |
7396 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
7397 | break; | |
7398 | case 7: | |
7399 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
7400 | break; | |
7401 | case 10: | |
7402 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
7403 | break; | |
7404 | case 14: | |
7405 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
7406 | break; | |
7407 | } | |
7408 | if (INTEL_INFO(dev)->gen >= 4) | |
7409 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); | |
7410 | ||
190f68c5 | 7411 | if (crtc_state->sdvo_tv_clock) |
eb1cbe48 | 7412 | dpll |= PLL_REF_INPUT_TVCLKINBC; |
a93e255f | 7413 | else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
eb1cbe48 DV |
7414 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
7415 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
7416 | else | |
7417 | dpll |= PLL_REF_INPUT_DREFCLK; | |
7418 | ||
7419 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 7420 | crtc_state->dpll_hw_state.dpll = dpll; |
8bcc2795 | 7421 | |
eb1cbe48 | 7422 | if (INTEL_INFO(dev)->gen >= 4) { |
190f68c5 | 7423 | u32 dpll_md = (crtc_state->pixel_multiplier - 1) |
ef1b460d | 7424 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
190f68c5 | 7425 | crtc_state->dpll_hw_state.dpll_md = dpll_md; |
eb1cbe48 DV |
7426 | } |
7427 | } | |
7428 | ||
f47709a9 | 7429 | static void i8xx_update_pll(struct intel_crtc *crtc, |
190f68c5 | 7430 | struct intel_crtc_state *crtc_state, |
f47709a9 | 7431 | intel_clock_t *reduced_clock, |
eb1cbe48 DV |
7432 | int num_connectors) |
7433 | { | |
f47709a9 | 7434 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 7435 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 | 7436 | u32 dpll; |
190f68c5 | 7437 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 7438 | |
190f68c5 | 7439 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 7440 | |
eb1cbe48 DV |
7441 | dpll = DPLL_VGA_MODE_DIS; |
7442 | ||
a93e255f | 7443 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
eb1cbe48 DV |
7444 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
7445 | } else { | |
7446 | if (clock->p1 == 2) | |
7447 | dpll |= PLL_P1_DIVIDE_BY_TWO; | |
7448 | else | |
7449 | dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
7450 | if (clock->p2 == 4) | |
7451 | dpll |= PLL_P2_DIVIDE_BY_4; | |
7452 | } | |
7453 | ||
a93e255f | 7454 | if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO)) |
4a33e48d DV |
7455 | dpll |= DPLL_DVO_2X_MODE; |
7456 | ||
a93e255f | 7457 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
eb1cbe48 DV |
7458 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
7459 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
7460 | else | |
7461 | dpll |= PLL_REF_INPUT_DREFCLK; | |
7462 | ||
7463 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 7464 | crtc_state->dpll_hw_state.dpll = dpll; |
eb1cbe48 DV |
7465 | } |
7466 | ||
8a654f3b | 7467 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) |
b0e77b9c PZ |
7468 | { |
7469 | struct drm_device *dev = intel_crtc->base.dev; | |
7470 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7471 | enum pipe pipe = intel_crtc->pipe; | |
6e3c9717 | 7472 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
8a654f3b | 7473 | struct drm_display_mode *adjusted_mode = |
6e3c9717 | 7474 | &intel_crtc->config->base.adjusted_mode; |
1caea6e9 VS |
7475 | uint32_t crtc_vtotal, crtc_vblank_end; |
7476 | int vsyncshift = 0; | |
4d8a62ea DV |
7477 | |
7478 | /* We need to be careful not to changed the adjusted mode, for otherwise | |
7479 | * the hw state checker will get angry at the mismatch. */ | |
7480 | crtc_vtotal = adjusted_mode->crtc_vtotal; | |
7481 | crtc_vblank_end = adjusted_mode->crtc_vblank_end; | |
b0e77b9c | 7482 | |
609aeaca | 7483 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
b0e77b9c | 7484 | /* the chip adds 2 halflines automatically */ |
4d8a62ea DV |
7485 | crtc_vtotal -= 1; |
7486 | crtc_vblank_end -= 1; | |
609aeaca | 7487 | |
409ee761 | 7488 | if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
609aeaca VS |
7489 | vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; |
7490 | else | |
7491 | vsyncshift = adjusted_mode->crtc_hsync_start - | |
7492 | adjusted_mode->crtc_htotal / 2; | |
1caea6e9 VS |
7493 | if (vsyncshift < 0) |
7494 | vsyncshift += adjusted_mode->crtc_htotal; | |
b0e77b9c PZ |
7495 | } |
7496 | ||
7497 | if (INTEL_INFO(dev)->gen > 3) | |
fe2b8f9d | 7498 | I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift); |
b0e77b9c | 7499 | |
fe2b8f9d | 7500 | I915_WRITE(HTOTAL(cpu_transcoder), |
b0e77b9c PZ |
7501 | (adjusted_mode->crtc_hdisplay - 1) | |
7502 | ((adjusted_mode->crtc_htotal - 1) << 16)); | |
fe2b8f9d | 7503 | I915_WRITE(HBLANK(cpu_transcoder), |
b0e77b9c PZ |
7504 | (adjusted_mode->crtc_hblank_start - 1) | |
7505 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); | |
fe2b8f9d | 7506 | I915_WRITE(HSYNC(cpu_transcoder), |
b0e77b9c PZ |
7507 | (adjusted_mode->crtc_hsync_start - 1) | |
7508 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); | |
7509 | ||
fe2b8f9d | 7510 | I915_WRITE(VTOTAL(cpu_transcoder), |
b0e77b9c | 7511 | (adjusted_mode->crtc_vdisplay - 1) | |
4d8a62ea | 7512 | ((crtc_vtotal - 1) << 16)); |
fe2b8f9d | 7513 | I915_WRITE(VBLANK(cpu_transcoder), |
b0e77b9c | 7514 | (adjusted_mode->crtc_vblank_start - 1) | |
4d8a62ea | 7515 | ((crtc_vblank_end - 1) << 16)); |
fe2b8f9d | 7516 | I915_WRITE(VSYNC(cpu_transcoder), |
b0e77b9c PZ |
7517 | (adjusted_mode->crtc_vsync_start - 1) | |
7518 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); | |
7519 | ||
b5e508d4 PZ |
7520 | /* Workaround: when the EDP input selection is B, the VTOTAL_B must be |
7521 | * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is | |
7522 | * documented on the DDI_FUNC_CTL register description, EDP Input Select | |
7523 | * bits. */ | |
7524 | if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP && | |
7525 | (pipe == PIPE_B || pipe == PIPE_C)) | |
7526 | I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder))); | |
7527 | ||
b0e77b9c PZ |
7528 | /* pipesrc controls the size that is scaled from, which should |
7529 | * always be the user's requested size. | |
7530 | */ | |
7531 | I915_WRITE(PIPESRC(pipe), | |
6e3c9717 ACO |
7532 | ((intel_crtc->config->pipe_src_w - 1) << 16) | |
7533 | (intel_crtc->config->pipe_src_h - 1)); | |
b0e77b9c PZ |
7534 | } |
7535 | ||
1bd1bd80 | 7536 | static void intel_get_pipe_timings(struct intel_crtc *crtc, |
5cec258b | 7537 | struct intel_crtc_state *pipe_config) |
1bd1bd80 DV |
7538 | { |
7539 | struct drm_device *dev = crtc->base.dev; | |
7540 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7541 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; | |
7542 | uint32_t tmp; | |
7543 | ||
7544 | tmp = I915_READ(HTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
7545 | pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; |
7546 | pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7547 | tmp = I915_READ(HBLANK(cpu_transcoder)); |
2d112de7 ACO |
7548 | pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1; |
7549 | pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7550 | tmp = I915_READ(HSYNC(cpu_transcoder)); |
2d112de7 ACO |
7551 | pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; |
7552 | pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
7553 | |
7554 | tmp = I915_READ(VTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
7555 | pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; |
7556 | pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7557 | tmp = I915_READ(VBLANK(cpu_transcoder)); |
2d112de7 ACO |
7558 | pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1; |
7559 | pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7560 | tmp = I915_READ(VSYNC(cpu_transcoder)); |
2d112de7 ACO |
7561 | pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; |
7562 | pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
7563 | |
7564 | if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) { | |
2d112de7 ACO |
7565 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; |
7566 | pipe_config->base.adjusted_mode.crtc_vtotal += 1; | |
7567 | pipe_config->base.adjusted_mode.crtc_vblank_end += 1; | |
1bd1bd80 DV |
7568 | } |
7569 | ||
7570 | tmp = I915_READ(PIPESRC(crtc->pipe)); | |
37327abd VS |
7571 | pipe_config->pipe_src_h = (tmp & 0xffff) + 1; |
7572 | pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1; | |
7573 | ||
2d112de7 ACO |
7574 | pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h; |
7575 | pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w; | |
1bd1bd80 DV |
7576 | } |
7577 | ||
f6a83288 | 7578 | void intel_mode_from_pipe_config(struct drm_display_mode *mode, |
5cec258b | 7579 | struct intel_crtc_state *pipe_config) |
babea61d | 7580 | { |
2d112de7 ACO |
7581 | mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay; |
7582 | mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal; | |
7583 | mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start; | |
7584 | mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end; | |
babea61d | 7585 | |
2d112de7 ACO |
7586 | mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay; |
7587 | mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal; | |
7588 | mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start; | |
7589 | mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end; | |
babea61d | 7590 | |
2d112de7 | 7591 | mode->flags = pipe_config->base.adjusted_mode.flags; |
babea61d | 7592 | |
2d112de7 ACO |
7593 | mode->clock = pipe_config->base.adjusted_mode.crtc_clock; |
7594 | mode->flags |= pipe_config->base.adjusted_mode.flags; | |
babea61d JB |
7595 | } |
7596 | ||
84b046f3 DV |
7597 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) |
7598 | { | |
7599 | struct drm_device *dev = intel_crtc->base.dev; | |
7600 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7601 | uint32_t pipeconf; | |
7602 | ||
9f11a9e4 | 7603 | pipeconf = 0; |
84b046f3 | 7604 | |
b6b5d049 VS |
7605 | if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
7606 | (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
7607 | pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE; | |
67c72a12 | 7608 | |
6e3c9717 | 7609 | if (intel_crtc->config->double_wide) |
cf532bb2 | 7610 | pipeconf |= PIPECONF_DOUBLE_WIDE; |
84b046f3 | 7611 | |
ff9ce46e DV |
7612 | /* only g4x and later have fancy bpc/dither controls */ |
7613 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { | |
ff9ce46e | 7614 | /* Bspec claims that we can't use dithering for 30bpp pipes. */ |
6e3c9717 | 7615 | if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30) |
ff9ce46e | 7616 | pipeconf |= PIPECONF_DITHER_EN | |
84b046f3 | 7617 | PIPECONF_DITHER_TYPE_SP; |
84b046f3 | 7618 | |
6e3c9717 | 7619 | switch (intel_crtc->config->pipe_bpp) { |
ff9ce46e DV |
7620 | case 18: |
7621 | pipeconf |= PIPECONF_6BPC; | |
7622 | break; | |
7623 | case 24: | |
7624 | pipeconf |= PIPECONF_8BPC; | |
7625 | break; | |
7626 | case 30: | |
7627 | pipeconf |= PIPECONF_10BPC; | |
7628 | break; | |
7629 | default: | |
7630 | /* Case prevented by intel_choose_pipe_bpp_dither. */ | |
7631 | BUG(); | |
84b046f3 DV |
7632 | } |
7633 | } | |
7634 | ||
7635 | if (HAS_PIPE_CXSR(dev)) { | |
7636 | if (intel_crtc->lowfreq_avail) { | |
7637 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); | |
7638 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; | |
7639 | } else { | |
7640 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); | |
84b046f3 DV |
7641 | } |
7642 | } | |
7643 | ||
6e3c9717 | 7644 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { |
efc2cfff | 7645 | if (INTEL_INFO(dev)->gen < 4 || |
409ee761 | 7646 | intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
efc2cfff VS |
7647 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; |
7648 | else | |
7649 | pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT; | |
7650 | } else | |
84b046f3 DV |
7651 | pipeconf |= PIPECONF_PROGRESSIVE; |
7652 | ||
6e3c9717 | 7653 | if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range) |
9f11a9e4 | 7654 | pipeconf |= PIPECONF_COLOR_RANGE_SELECT; |
9c8e09b7 | 7655 | |
84b046f3 DV |
7656 | I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); |
7657 | POSTING_READ(PIPECONF(intel_crtc->pipe)); | |
7658 | } | |
7659 | ||
190f68c5 ACO |
7660 | static int i9xx_crtc_compute_clock(struct intel_crtc *crtc, |
7661 | struct intel_crtc_state *crtc_state) | |
79e53945 | 7662 | { |
c7653199 | 7663 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 7664 | struct drm_i915_private *dev_priv = dev->dev_private; |
c751ce4f | 7665 | int refclk, num_connectors = 0; |
652c393a | 7666 | intel_clock_t clock, reduced_clock; |
a16af721 | 7667 | bool ok, has_reduced_clock = false; |
e9fd1c02 | 7668 | bool is_lvds = false, is_dsi = false; |
5eddb70b | 7669 | struct intel_encoder *encoder; |
d4906093 | 7670 | const intel_limit_t *limit; |
55bb9992 | 7671 | struct drm_atomic_state *state = crtc_state->base.state; |
da3ced29 | 7672 | struct drm_connector *connector; |
55bb9992 ACO |
7673 | struct drm_connector_state *connector_state; |
7674 | int i; | |
79e53945 | 7675 | |
dd3cd74a ACO |
7676 | memset(&crtc_state->dpll_hw_state, 0, |
7677 | sizeof(crtc_state->dpll_hw_state)); | |
7678 | ||
da3ced29 | 7679 | for_each_connector_in_state(state, connector, connector_state, i) { |
55bb9992 ACO |
7680 | if (connector_state->crtc != &crtc->base) |
7681 | continue; | |
7682 | ||
7683 | encoder = to_intel_encoder(connector_state->best_encoder); | |
7684 | ||
5eddb70b | 7685 | switch (encoder->type) { |
79e53945 JB |
7686 | case INTEL_OUTPUT_LVDS: |
7687 | is_lvds = true; | |
7688 | break; | |
e9fd1c02 JN |
7689 | case INTEL_OUTPUT_DSI: |
7690 | is_dsi = true; | |
7691 | break; | |
6847d71b PZ |
7692 | default: |
7693 | break; | |
79e53945 | 7694 | } |
43565a06 | 7695 | |
c751ce4f | 7696 | num_connectors++; |
79e53945 JB |
7697 | } |
7698 | ||
f2335330 | 7699 | if (is_dsi) |
5b18e57c | 7700 | return 0; |
f2335330 | 7701 | |
190f68c5 | 7702 | if (!crtc_state->clock_set) { |
a93e255f | 7703 | refclk = i9xx_get_refclk(crtc_state, num_connectors); |
79e53945 | 7704 | |
e9fd1c02 JN |
7705 | /* |
7706 | * Returns a set of divisors for the desired target clock with | |
7707 | * the given refclk, or FALSE. The returned values represent | |
7708 | * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + | |
7709 | * 2) / p1 / p2. | |
7710 | */ | |
a93e255f ACO |
7711 | limit = intel_limit(crtc_state, refclk); |
7712 | ok = dev_priv->display.find_dpll(limit, crtc_state, | |
190f68c5 | 7713 | crtc_state->port_clock, |
e9fd1c02 | 7714 | refclk, NULL, &clock); |
f2335330 | 7715 | if (!ok) { |
e9fd1c02 JN |
7716 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
7717 | return -EINVAL; | |
7718 | } | |
79e53945 | 7719 | |
f2335330 JN |
7720 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
7721 | /* | |
7722 | * Ensure we match the reduced clock's P to the target | |
7723 | * clock. If the clocks don't match, we can't switch | |
7724 | * the display clock by using the FP0/FP1. In such case | |
7725 | * we will disable the LVDS downclock feature. | |
7726 | */ | |
7727 | has_reduced_clock = | |
a93e255f | 7728 | dev_priv->display.find_dpll(limit, crtc_state, |
f2335330 JN |
7729 | dev_priv->lvds_downclock, |
7730 | refclk, &clock, | |
7731 | &reduced_clock); | |
7732 | } | |
7733 | /* Compat-code for transition, will disappear. */ | |
190f68c5 ACO |
7734 | crtc_state->dpll.n = clock.n; |
7735 | crtc_state->dpll.m1 = clock.m1; | |
7736 | crtc_state->dpll.m2 = clock.m2; | |
7737 | crtc_state->dpll.p1 = clock.p1; | |
7738 | crtc_state->dpll.p2 = clock.p2; | |
f47709a9 | 7739 | } |
7026d4ac | 7740 | |
e9fd1c02 | 7741 | if (IS_GEN2(dev)) { |
190f68c5 | 7742 | i8xx_update_pll(crtc, crtc_state, |
2a8f64ca VP |
7743 | has_reduced_clock ? &reduced_clock : NULL, |
7744 | num_connectors); | |
9d556c99 | 7745 | } else if (IS_CHERRYVIEW(dev)) { |
190f68c5 | 7746 | chv_update_pll(crtc, crtc_state); |
e9fd1c02 | 7747 | } else if (IS_VALLEYVIEW(dev)) { |
190f68c5 | 7748 | vlv_update_pll(crtc, crtc_state); |
e9fd1c02 | 7749 | } else { |
190f68c5 | 7750 | i9xx_update_pll(crtc, crtc_state, |
eb1cbe48 | 7751 | has_reduced_clock ? &reduced_clock : NULL, |
eba905b2 | 7752 | num_connectors); |
e9fd1c02 | 7753 | } |
79e53945 | 7754 | |
c8f7a0db | 7755 | return 0; |
f564048e EA |
7756 | } |
7757 | ||
2fa2fe9a | 7758 | static void i9xx_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 7759 | struct intel_crtc_state *pipe_config) |
2fa2fe9a DV |
7760 | { |
7761 | struct drm_device *dev = crtc->base.dev; | |
7762 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7763 | uint32_t tmp; | |
7764 | ||
dc9e7dec VS |
7765 | if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev))) |
7766 | return; | |
7767 | ||
2fa2fe9a | 7768 | tmp = I915_READ(PFIT_CONTROL); |
06922821 DV |
7769 | if (!(tmp & PFIT_ENABLE)) |
7770 | return; | |
2fa2fe9a | 7771 | |
06922821 | 7772 | /* Check whether the pfit is attached to our pipe. */ |
2fa2fe9a DV |
7773 | if (INTEL_INFO(dev)->gen < 4) { |
7774 | if (crtc->pipe != PIPE_B) | |
7775 | return; | |
2fa2fe9a DV |
7776 | } else { |
7777 | if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) | |
7778 | return; | |
7779 | } | |
7780 | ||
06922821 | 7781 | pipe_config->gmch_pfit.control = tmp; |
2fa2fe9a DV |
7782 | pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS); |
7783 | if (INTEL_INFO(dev)->gen < 5) | |
7784 | pipe_config->gmch_pfit.lvds_border_bits = | |
7785 | I915_READ(LVDS) & LVDS_BORDER_ENABLE; | |
7786 | } | |
7787 | ||
acbec814 | 7788 | static void vlv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 7789 | struct intel_crtc_state *pipe_config) |
acbec814 JB |
7790 | { |
7791 | struct drm_device *dev = crtc->base.dev; | |
7792 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7793 | int pipe = pipe_config->cpu_transcoder; | |
7794 | intel_clock_t clock; | |
7795 | u32 mdiv; | |
662c6ecb | 7796 | int refclk = 100000; |
acbec814 | 7797 | |
f573de5a SK |
7798 | /* In case of MIPI DPLL will not even be used */ |
7799 | if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)) | |
7800 | return; | |
7801 | ||
a580516d | 7802 | mutex_lock(&dev_priv->sb_lock); |
ab3c759a | 7803 | mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); |
a580516d | 7804 | mutex_unlock(&dev_priv->sb_lock); |
acbec814 JB |
7805 | |
7806 | clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; | |
7807 | clock.m2 = mdiv & DPIO_M2DIV_MASK; | |
7808 | clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; | |
7809 | clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; | |
7810 | clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; | |
7811 | ||
f646628b | 7812 | vlv_clock(refclk, &clock); |
acbec814 | 7813 | |
f646628b VS |
7814 | /* clock.dot is the fast clock */ |
7815 | pipe_config->port_clock = clock.dot / 5; | |
acbec814 JB |
7816 | } |
7817 | ||
5724dbd1 DL |
7818 | static void |
7819 | i9xx_get_initial_plane_config(struct intel_crtc *crtc, | |
7820 | struct intel_initial_plane_config *plane_config) | |
1ad292b5 JB |
7821 | { |
7822 | struct drm_device *dev = crtc->base.dev; | |
7823 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7824 | u32 val, base, offset; | |
7825 | int pipe = crtc->pipe, plane = crtc->plane; | |
7826 | int fourcc, pixel_format; | |
6761dd31 | 7827 | unsigned int aligned_height; |
b113d5ee | 7828 | struct drm_framebuffer *fb; |
1b842c89 | 7829 | struct intel_framebuffer *intel_fb; |
1ad292b5 | 7830 | |
42a7b088 DL |
7831 | val = I915_READ(DSPCNTR(plane)); |
7832 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
7833 | return; | |
7834 | ||
d9806c9f | 7835 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 7836 | if (!intel_fb) { |
1ad292b5 JB |
7837 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
7838 | return; | |
7839 | } | |
7840 | ||
1b842c89 DL |
7841 | fb = &intel_fb->base; |
7842 | ||
18c5247e DV |
7843 | if (INTEL_INFO(dev)->gen >= 4) { |
7844 | if (val & DISPPLANE_TILED) { | |
49af449b | 7845 | plane_config->tiling = I915_TILING_X; |
18c5247e DV |
7846 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; |
7847 | } | |
7848 | } | |
1ad292b5 JB |
7849 | |
7850 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 7851 | fourcc = i9xx_format_to_fourcc(pixel_format); |
b113d5ee DL |
7852 | fb->pixel_format = fourcc; |
7853 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
1ad292b5 JB |
7854 | |
7855 | if (INTEL_INFO(dev)->gen >= 4) { | |
49af449b | 7856 | if (plane_config->tiling) |
1ad292b5 JB |
7857 | offset = I915_READ(DSPTILEOFF(plane)); |
7858 | else | |
7859 | offset = I915_READ(DSPLINOFF(plane)); | |
7860 | base = I915_READ(DSPSURF(plane)) & 0xfffff000; | |
7861 | } else { | |
7862 | base = I915_READ(DSPADDR(plane)); | |
7863 | } | |
7864 | plane_config->base = base; | |
7865 | ||
7866 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
7867 | fb->width = ((val >> 16) & 0xfff) + 1; |
7868 | fb->height = ((val >> 0) & 0xfff) + 1; | |
1ad292b5 JB |
7869 | |
7870 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 7871 | fb->pitches[0] = val & 0xffffffc0; |
1ad292b5 | 7872 | |
b113d5ee | 7873 | aligned_height = intel_fb_align_height(dev, fb->height, |
091df6cb DV |
7874 | fb->pixel_format, |
7875 | fb->modifier[0]); | |
1ad292b5 | 7876 | |
f37b5c2b | 7877 | plane_config->size = fb->pitches[0] * aligned_height; |
1ad292b5 | 7878 | |
2844a921 DL |
7879 | DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
7880 | pipe_name(pipe), plane, fb->width, fb->height, | |
7881 | fb->bits_per_pixel, base, fb->pitches[0], | |
7882 | plane_config->size); | |
1ad292b5 | 7883 | |
2d14030b | 7884 | plane_config->fb = intel_fb; |
1ad292b5 JB |
7885 | } |
7886 | ||
70b23a98 | 7887 | static void chv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 7888 | struct intel_crtc_state *pipe_config) |
70b23a98 VS |
7889 | { |
7890 | struct drm_device *dev = crtc->base.dev; | |
7891 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7892 | int pipe = pipe_config->cpu_transcoder; | |
7893 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
7894 | intel_clock_t clock; | |
7895 | u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2; | |
7896 | int refclk = 100000; | |
7897 | ||
a580516d | 7898 | mutex_lock(&dev_priv->sb_lock); |
70b23a98 VS |
7899 | cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)); |
7900 | pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); | |
7901 | pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); | |
7902 | pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); | |
a580516d | 7903 | mutex_unlock(&dev_priv->sb_lock); |
70b23a98 VS |
7904 | |
7905 | clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; | |
7906 | clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff); | |
7907 | clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf; | |
7908 | clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7; | |
7909 | clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f; | |
7910 | ||
7911 | chv_clock(refclk, &clock); | |
7912 | ||
7913 | /* clock.dot is the fast clock */ | |
7914 | pipe_config->port_clock = clock.dot / 5; | |
7915 | } | |
7916 | ||
0e8ffe1b | 7917 | static bool i9xx_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 7918 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
7919 | { |
7920 | struct drm_device *dev = crtc->base.dev; | |
7921 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7922 | uint32_t tmp; | |
7923 | ||
f458ebbc DV |
7924 | if (!intel_display_power_is_enabled(dev_priv, |
7925 | POWER_DOMAIN_PIPE(crtc->pipe))) | |
b5482bd0 ID |
7926 | return false; |
7927 | ||
e143a21c | 7928 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 | 7929 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
eccb140b | 7930 | |
0e8ffe1b DV |
7931 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
7932 | if (!(tmp & PIPECONF_ENABLE)) | |
7933 | return false; | |
7934 | ||
42571aef VS |
7935 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { |
7936 | switch (tmp & PIPECONF_BPC_MASK) { | |
7937 | case PIPECONF_6BPC: | |
7938 | pipe_config->pipe_bpp = 18; | |
7939 | break; | |
7940 | case PIPECONF_8BPC: | |
7941 | pipe_config->pipe_bpp = 24; | |
7942 | break; | |
7943 | case PIPECONF_10BPC: | |
7944 | pipe_config->pipe_bpp = 30; | |
7945 | break; | |
7946 | default: | |
7947 | break; | |
7948 | } | |
7949 | } | |
7950 | ||
b5a9fa09 DV |
7951 | if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT)) |
7952 | pipe_config->limited_color_range = true; | |
7953 | ||
282740f7 VS |
7954 | if (INTEL_INFO(dev)->gen < 4) |
7955 | pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; | |
7956 | ||
1bd1bd80 DV |
7957 | intel_get_pipe_timings(crtc, pipe_config); |
7958 | ||
2fa2fe9a DV |
7959 | i9xx_get_pfit_config(crtc, pipe_config); |
7960 | ||
6c49f241 DV |
7961 | if (INTEL_INFO(dev)->gen >= 4) { |
7962 | tmp = I915_READ(DPLL_MD(crtc->pipe)); | |
7963 | pipe_config->pixel_multiplier = | |
7964 | ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) | |
7965 | >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; | |
8bcc2795 | 7966 | pipe_config->dpll_hw_state.dpll_md = tmp; |
6c49f241 DV |
7967 | } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
7968 | tmp = I915_READ(DPLL(crtc->pipe)); | |
7969 | pipe_config->pixel_multiplier = | |
7970 | ((tmp & SDVO_MULTIPLIER_MASK) | |
7971 | >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; | |
7972 | } else { | |
7973 | /* Note that on i915G/GM the pixel multiplier is in the sdvo | |
7974 | * port and will be fixed up in the encoder->get_config | |
7975 | * function. */ | |
7976 | pipe_config->pixel_multiplier = 1; | |
7977 | } | |
8bcc2795 DV |
7978 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); |
7979 | if (!IS_VALLEYVIEW(dev)) { | |
1c4e0274 VS |
7980 | /* |
7981 | * DPLL_DVO_2X_MODE must be enabled for both DPLLs | |
7982 | * on 830. Filter it out here so that we don't | |
7983 | * report errors due to that. | |
7984 | */ | |
7985 | if (IS_I830(dev)) | |
7986 | pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE; | |
7987 | ||
8bcc2795 DV |
7988 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); |
7989 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); | |
165e901c VS |
7990 | } else { |
7991 | /* Mask out read-only status bits. */ | |
7992 | pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | | |
7993 | DPLL_PORTC_READY_MASK | | |
7994 | DPLL_PORTB_READY_MASK); | |
8bcc2795 | 7995 | } |
6c49f241 | 7996 | |
70b23a98 VS |
7997 | if (IS_CHERRYVIEW(dev)) |
7998 | chv_crtc_clock_get(crtc, pipe_config); | |
7999 | else if (IS_VALLEYVIEW(dev)) | |
acbec814 JB |
8000 | vlv_crtc_clock_get(crtc, pipe_config); |
8001 | else | |
8002 | i9xx_crtc_clock_get(crtc, pipe_config); | |
18442d08 | 8003 | |
0e8ffe1b DV |
8004 | return true; |
8005 | } | |
8006 | ||
dde86e2d | 8007 | static void ironlake_init_pch_refclk(struct drm_device *dev) |
13d83a67 JB |
8008 | { |
8009 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13d83a67 | 8010 | struct intel_encoder *encoder; |
74cfd7ac | 8011 | u32 val, final; |
13d83a67 | 8012 | bool has_lvds = false; |
199e5d79 | 8013 | bool has_cpu_edp = false; |
199e5d79 | 8014 | bool has_panel = false; |
99eb6a01 KP |
8015 | bool has_ck505 = false; |
8016 | bool can_ssc = false; | |
13d83a67 JB |
8017 | |
8018 | /* We need to take the global config into account */ | |
b2784e15 | 8019 | for_each_intel_encoder(dev, encoder) { |
199e5d79 KP |
8020 | switch (encoder->type) { |
8021 | case INTEL_OUTPUT_LVDS: | |
8022 | has_panel = true; | |
8023 | has_lvds = true; | |
8024 | break; | |
8025 | case INTEL_OUTPUT_EDP: | |
8026 | has_panel = true; | |
2de6905f | 8027 | if (enc_to_dig_port(&encoder->base)->port == PORT_A) |
199e5d79 KP |
8028 | has_cpu_edp = true; |
8029 | break; | |
6847d71b PZ |
8030 | default: |
8031 | break; | |
13d83a67 JB |
8032 | } |
8033 | } | |
8034 | ||
99eb6a01 | 8035 | if (HAS_PCH_IBX(dev)) { |
41aa3448 | 8036 | has_ck505 = dev_priv->vbt.display_clock_mode; |
99eb6a01 KP |
8037 | can_ssc = has_ck505; |
8038 | } else { | |
8039 | has_ck505 = false; | |
8040 | can_ssc = true; | |
8041 | } | |
8042 | ||
2de6905f ID |
8043 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n", |
8044 | has_panel, has_lvds, has_ck505); | |
13d83a67 JB |
8045 | |
8046 | /* Ironlake: try to setup display ref clock before DPLL | |
8047 | * enabling. This is only under driver's control after | |
8048 | * PCH B stepping, previous chipset stepping should be | |
8049 | * ignoring this setting. | |
8050 | */ | |
74cfd7ac CW |
8051 | val = I915_READ(PCH_DREF_CONTROL); |
8052 | ||
8053 | /* As we must carefully and slowly disable/enable each source in turn, | |
8054 | * compute the final state we want first and check if we need to | |
8055 | * make any changes at all. | |
8056 | */ | |
8057 | final = val; | |
8058 | final &= ~DREF_NONSPREAD_SOURCE_MASK; | |
8059 | if (has_ck505) | |
8060 | final |= DREF_NONSPREAD_CK505_ENABLE; | |
8061 | else | |
8062 | final |= DREF_NONSPREAD_SOURCE_ENABLE; | |
8063 | ||
8064 | final &= ~DREF_SSC_SOURCE_MASK; | |
8065 | final &= ~DREF_CPU_SOURCE_OUTPUT_MASK; | |
8066 | final &= ~DREF_SSC1_ENABLE; | |
8067 | ||
8068 | if (has_panel) { | |
8069 | final |= DREF_SSC_SOURCE_ENABLE; | |
8070 | ||
8071 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
8072 | final |= DREF_SSC1_ENABLE; | |
8073 | ||
8074 | if (has_cpu_edp) { | |
8075 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
8076 | final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; | |
8077 | else | |
8078 | final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; | |
8079 | } else | |
8080 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
8081 | } else { | |
8082 | final |= DREF_SSC_SOURCE_DISABLE; | |
8083 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
8084 | } | |
8085 | ||
8086 | if (final == val) | |
8087 | return; | |
8088 | ||
13d83a67 | 8089 | /* Always enable nonspread source */ |
74cfd7ac | 8090 | val &= ~DREF_NONSPREAD_SOURCE_MASK; |
13d83a67 | 8091 | |
99eb6a01 | 8092 | if (has_ck505) |
74cfd7ac | 8093 | val |= DREF_NONSPREAD_CK505_ENABLE; |
99eb6a01 | 8094 | else |
74cfd7ac | 8095 | val |= DREF_NONSPREAD_SOURCE_ENABLE; |
13d83a67 | 8096 | |
199e5d79 | 8097 | if (has_panel) { |
74cfd7ac CW |
8098 | val &= ~DREF_SSC_SOURCE_MASK; |
8099 | val |= DREF_SSC_SOURCE_ENABLE; | |
13d83a67 | 8100 | |
199e5d79 | 8101 | /* SSC must be turned on before enabling the CPU output */ |
99eb6a01 | 8102 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 8103 | DRM_DEBUG_KMS("Using SSC on panel\n"); |
74cfd7ac | 8104 | val |= DREF_SSC1_ENABLE; |
e77166b5 | 8105 | } else |
74cfd7ac | 8106 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 KP |
8107 | |
8108 | /* Get SSC going before enabling the outputs */ | |
74cfd7ac | 8109 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
8110 | POSTING_READ(PCH_DREF_CONTROL); |
8111 | udelay(200); | |
8112 | ||
74cfd7ac | 8113 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
13d83a67 JB |
8114 | |
8115 | /* Enable CPU source on CPU attached eDP */ | |
199e5d79 | 8116 | if (has_cpu_edp) { |
99eb6a01 | 8117 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 8118 | DRM_DEBUG_KMS("Using SSC on eDP\n"); |
74cfd7ac | 8119 | val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
eba905b2 | 8120 | } else |
74cfd7ac | 8121 | val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
199e5d79 | 8122 | } else |
74cfd7ac | 8123 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 8124 | |
74cfd7ac | 8125 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
8126 | POSTING_READ(PCH_DREF_CONTROL); |
8127 | udelay(200); | |
8128 | } else { | |
8129 | DRM_DEBUG_KMS("Disabling SSC entirely\n"); | |
8130 | ||
74cfd7ac | 8131 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
199e5d79 KP |
8132 | |
8133 | /* Turn off CPU output */ | |
74cfd7ac | 8134 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 8135 | |
74cfd7ac | 8136 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
8137 | POSTING_READ(PCH_DREF_CONTROL); |
8138 | udelay(200); | |
8139 | ||
8140 | /* Turn off the SSC source */ | |
74cfd7ac CW |
8141 | val &= ~DREF_SSC_SOURCE_MASK; |
8142 | val |= DREF_SSC_SOURCE_DISABLE; | |
199e5d79 KP |
8143 | |
8144 | /* Turn off SSC1 */ | |
74cfd7ac | 8145 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 | 8146 | |
74cfd7ac | 8147 | I915_WRITE(PCH_DREF_CONTROL, val); |
13d83a67 JB |
8148 | POSTING_READ(PCH_DREF_CONTROL); |
8149 | udelay(200); | |
8150 | } | |
74cfd7ac CW |
8151 | |
8152 | BUG_ON(val != final); | |
13d83a67 JB |
8153 | } |
8154 | ||
f31f2d55 | 8155 | static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv) |
dde86e2d | 8156 | { |
f31f2d55 | 8157 | uint32_t tmp; |
dde86e2d | 8158 | |
0ff066a9 PZ |
8159 | tmp = I915_READ(SOUTH_CHICKEN2); |
8160 | tmp |= FDI_MPHY_IOSFSB_RESET_CTL; | |
8161 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 8162 | |
0ff066a9 PZ |
8163 | if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) & |
8164 | FDI_MPHY_IOSFSB_RESET_STATUS, 100)) | |
8165 | DRM_ERROR("FDI mPHY reset assert timeout\n"); | |
dde86e2d | 8166 | |
0ff066a9 PZ |
8167 | tmp = I915_READ(SOUTH_CHICKEN2); |
8168 | tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL; | |
8169 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 8170 | |
0ff066a9 PZ |
8171 | if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) & |
8172 | FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100)) | |
8173 | DRM_ERROR("FDI mPHY reset de-assert timeout\n"); | |
f31f2d55 PZ |
8174 | } |
8175 | ||
8176 | /* WaMPhyProgramming:hsw */ | |
8177 | static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv) | |
8178 | { | |
8179 | uint32_t tmp; | |
dde86e2d PZ |
8180 | |
8181 | tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY); | |
8182 | tmp &= ~(0xFF << 24); | |
8183 | tmp |= (0x12 << 24); | |
8184 | intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY); | |
8185 | ||
dde86e2d PZ |
8186 | tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY); |
8187 | tmp |= (1 << 11); | |
8188 | intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY); | |
8189 | ||
8190 | tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY); | |
8191 | tmp |= (1 << 11); | |
8192 | intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY); | |
8193 | ||
dde86e2d PZ |
8194 | tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY); |
8195 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
8196 | intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY); | |
8197 | ||
8198 | tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY); | |
8199 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
8200 | intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY); | |
8201 | ||
0ff066a9 PZ |
8202 | tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY); |
8203 | tmp &= ~(7 << 13); | |
8204 | tmp |= (5 << 13); | |
8205 | intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY); | |
dde86e2d | 8206 | |
0ff066a9 PZ |
8207 | tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY); |
8208 | tmp &= ~(7 << 13); | |
8209 | tmp |= (5 << 13); | |
8210 | intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY); | |
dde86e2d PZ |
8211 | |
8212 | tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY); | |
8213 | tmp &= ~0xFF; | |
8214 | tmp |= 0x1C; | |
8215 | intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY); | |
8216 | ||
8217 | tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY); | |
8218 | tmp &= ~0xFF; | |
8219 | tmp |= 0x1C; | |
8220 | intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY); | |
8221 | ||
8222 | tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY); | |
8223 | tmp &= ~(0xFF << 16); | |
8224 | tmp |= (0x1C << 16); | |
8225 | intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY); | |
8226 | ||
8227 | tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY); | |
8228 | tmp &= ~(0xFF << 16); | |
8229 | tmp |= (0x1C << 16); | |
8230 | intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY); | |
8231 | ||
0ff066a9 PZ |
8232 | tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY); |
8233 | tmp |= (1 << 27); | |
8234 | intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY); | |
dde86e2d | 8235 | |
0ff066a9 PZ |
8236 | tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY); |
8237 | tmp |= (1 << 27); | |
8238 | intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY); | |
dde86e2d | 8239 | |
0ff066a9 PZ |
8240 | tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY); |
8241 | tmp &= ~(0xF << 28); | |
8242 | tmp |= (4 << 28); | |
8243 | intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY); | |
dde86e2d | 8244 | |
0ff066a9 PZ |
8245 | tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY); |
8246 | tmp &= ~(0xF << 28); | |
8247 | tmp |= (4 << 28); | |
8248 | intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY); | |
f31f2d55 PZ |
8249 | } |
8250 | ||
2fa86a1f PZ |
8251 | /* Implements 3 different sequences from BSpec chapter "Display iCLK |
8252 | * Programming" based on the parameters passed: | |
8253 | * - Sequence to enable CLKOUT_DP | |
8254 | * - Sequence to enable CLKOUT_DP without spread | |
8255 | * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O | |
8256 | */ | |
8257 | static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread, | |
8258 | bool with_fdi) | |
f31f2d55 PZ |
8259 | { |
8260 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2fa86a1f PZ |
8261 | uint32_t reg, tmp; |
8262 | ||
8263 | if (WARN(with_fdi && !with_spread, "FDI requires downspread\n")) | |
8264 | with_spread = true; | |
8265 | if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE && | |
8266 | with_fdi, "LP PCH doesn't have FDI\n")) | |
8267 | with_fdi = false; | |
f31f2d55 | 8268 | |
a580516d | 8269 | mutex_lock(&dev_priv->sb_lock); |
f31f2d55 PZ |
8270 | |
8271 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
8272 | tmp &= ~SBI_SSCCTL_DISABLE; | |
8273 | tmp |= SBI_SSCCTL_PATHALT; | |
8274 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8275 | ||
8276 | udelay(24); | |
8277 | ||
2fa86a1f PZ |
8278 | if (with_spread) { |
8279 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
8280 | tmp &= ~SBI_SSCCTL_PATHALT; | |
8281 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
f31f2d55 | 8282 | |
2fa86a1f PZ |
8283 | if (with_fdi) { |
8284 | lpt_reset_fdi_mphy(dev_priv); | |
8285 | lpt_program_fdi_mphy(dev_priv); | |
8286 | } | |
8287 | } | |
dde86e2d | 8288 | |
2fa86a1f PZ |
8289 | reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ? |
8290 | SBI_GEN0 : SBI_DBUFF0; | |
8291 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); | |
8292 | tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
8293 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
c00db246 | 8294 | |
a580516d | 8295 | mutex_unlock(&dev_priv->sb_lock); |
dde86e2d PZ |
8296 | } |
8297 | ||
47701c3b PZ |
8298 | /* Sequence to disable CLKOUT_DP */ |
8299 | static void lpt_disable_clkout_dp(struct drm_device *dev) | |
8300 | { | |
8301 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8302 | uint32_t reg, tmp; | |
8303 | ||
a580516d | 8304 | mutex_lock(&dev_priv->sb_lock); |
47701c3b PZ |
8305 | |
8306 | reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ? | |
8307 | SBI_GEN0 : SBI_DBUFF0; | |
8308 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); | |
8309 | tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
8310 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
8311 | ||
8312 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
8313 | if (!(tmp & SBI_SSCCTL_DISABLE)) { | |
8314 | if (!(tmp & SBI_SSCCTL_PATHALT)) { | |
8315 | tmp |= SBI_SSCCTL_PATHALT; | |
8316 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8317 | udelay(32); | |
8318 | } | |
8319 | tmp |= SBI_SSCCTL_DISABLE; | |
8320 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8321 | } | |
8322 | ||
a580516d | 8323 | mutex_unlock(&dev_priv->sb_lock); |
47701c3b PZ |
8324 | } |
8325 | ||
bf8fa3d3 PZ |
8326 | static void lpt_init_pch_refclk(struct drm_device *dev) |
8327 | { | |
bf8fa3d3 PZ |
8328 | struct intel_encoder *encoder; |
8329 | bool has_vga = false; | |
8330 | ||
b2784e15 | 8331 | for_each_intel_encoder(dev, encoder) { |
bf8fa3d3 PZ |
8332 | switch (encoder->type) { |
8333 | case INTEL_OUTPUT_ANALOG: | |
8334 | has_vga = true; | |
8335 | break; | |
6847d71b PZ |
8336 | default: |
8337 | break; | |
bf8fa3d3 PZ |
8338 | } |
8339 | } | |
8340 | ||
47701c3b PZ |
8341 | if (has_vga) |
8342 | lpt_enable_clkout_dp(dev, true, true); | |
8343 | else | |
8344 | lpt_disable_clkout_dp(dev); | |
bf8fa3d3 PZ |
8345 | } |
8346 | ||
dde86e2d PZ |
8347 | /* |
8348 | * Initialize reference clocks when the driver loads | |
8349 | */ | |
8350 | void intel_init_pch_refclk(struct drm_device *dev) | |
8351 | { | |
8352 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
8353 | ironlake_init_pch_refclk(dev); | |
8354 | else if (HAS_PCH_LPT(dev)) | |
8355 | lpt_init_pch_refclk(dev); | |
8356 | } | |
8357 | ||
55bb9992 | 8358 | static int ironlake_get_refclk(struct intel_crtc_state *crtc_state) |
d9d444cb | 8359 | { |
55bb9992 | 8360 | struct drm_device *dev = crtc_state->base.crtc->dev; |
d9d444cb | 8361 | struct drm_i915_private *dev_priv = dev->dev_private; |
55bb9992 | 8362 | struct drm_atomic_state *state = crtc_state->base.state; |
da3ced29 | 8363 | struct drm_connector *connector; |
55bb9992 | 8364 | struct drm_connector_state *connector_state; |
d9d444cb | 8365 | struct intel_encoder *encoder; |
55bb9992 | 8366 | int num_connectors = 0, i; |
d9d444cb JB |
8367 | bool is_lvds = false; |
8368 | ||
da3ced29 | 8369 | for_each_connector_in_state(state, connector, connector_state, i) { |
55bb9992 ACO |
8370 | if (connector_state->crtc != crtc_state->base.crtc) |
8371 | continue; | |
8372 | ||
8373 | encoder = to_intel_encoder(connector_state->best_encoder); | |
8374 | ||
d9d444cb JB |
8375 | switch (encoder->type) { |
8376 | case INTEL_OUTPUT_LVDS: | |
8377 | is_lvds = true; | |
8378 | break; | |
6847d71b PZ |
8379 | default: |
8380 | break; | |
d9d444cb JB |
8381 | } |
8382 | num_connectors++; | |
8383 | } | |
8384 | ||
8385 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) { | |
e91e941b | 8386 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", |
41aa3448 | 8387 | dev_priv->vbt.lvds_ssc_freq); |
e91e941b | 8388 | return dev_priv->vbt.lvds_ssc_freq; |
d9d444cb JB |
8389 | } |
8390 | ||
8391 | return 120000; | |
8392 | } | |
8393 | ||
6ff93609 | 8394 | static void ironlake_set_pipeconf(struct drm_crtc *crtc) |
79e53945 | 8395 | { |
c8203565 | 8396 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
79e53945 JB |
8397 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8398 | int pipe = intel_crtc->pipe; | |
c8203565 PZ |
8399 | uint32_t val; |
8400 | ||
78114071 | 8401 | val = 0; |
c8203565 | 8402 | |
6e3c9717 | 8403 | switch (intel_crtc->config->pipe_bpp) { |
c8203565 | 8404 | case 18: |
dfd07d72 | 8405 | val |= PIPECONF_6BPC; |
c8203565 PZ |
8406 | break; |
8407 | case 24: | |
dfd07d72 | 8408 | val |= PIPECONF_8BPC; |
c8203565 PZ |
8409 | break; |
8410 | case 30: | |
dfd07d72 | 8411 | val |= PIPECONF_10BPC; |
c8203565 PZ |
8412 | break; |
8413 | case 36: | |
dfd07d72 | 8414 | val |= PIPECONF_12BPC; |
c8203565 PZ |
8415 | break; |
8416 | default: | |
cc769b62 PZ |
8417 | /* Case prevented by intel_choose_pipe_bpp_dither. */ |
8418 | BUG(); | |
c8203565 PZ |
8419 | } |
8420 | ||
6e3c9717 | 8421 | if (intel_crtc->config->dither) |
c8203565 PZ |
8422 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
8423 | ||
6e3c9717 | 8424 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
c8203565 PZ |
8425 | val |= PIPECONF_INTERLACED_ILK; |
8426 | else | |
8427 | val |= PIPECONF_PROGRESSIVE; | |
8428 | ||
6e3c9717 | 8429 | if (intel_crtc->config->limited_color_range) |
3685a8f3 | 8430 | val |= PIPECONF_COLOR_RANGE_SELECT; |
3685a8f3 | 8431 | |
c8203565 PZ |
8432 | I915_WRITE(PIPECONF(pipe), val); |
8433 | POSTING_READ(PIPECONF(pipe)); | |
8434 | } | |
8435 | ||
86d3efce VS |
8436 | /* |
8437 | * Set up the pipe CSC unit. | |
8438 | * | |
8439 | * Currently only full range RGB to limited range RGB conversion | |
8440 | * is supported, but eventually this should handle various | |
8441 | * RGB<->YCbCr scenarios as well. | |
8442 | */ | |
50f3b016 | 8443 | static void intel_set_pipe_csc(struct drm_crtc *crtc) |
86d3efce VS |
8444 | { |
8445 | struct drm_device *dev = crtc->dev; | |
8446 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8447 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8448 | int pipe = intel_crtc->pipe; | |
8449 | uint16_t coeff = 0x7800; /* 1.0 */ | |
8450 | ||
8451 | /* | |
8452 | * TODO: Check what kind of values actually come out of the pipe | |
8453 | * with these coeff/postoff values and adjust to get the best | |
8454 | * accuracy. Perhaps we even need to take the bpc value into | |
8455 | * consideration. | |
8456 | */ | |
8457 | ||
6e3c9717 | 8458 | if (intel_crtc->config->limited_color_range) |
86d3efce VS |
8459 | coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */ |
8460 | ||
8461 | /* | |
8462 | * GY/GU and RY/RU should be the other way around according | |
8463 | * to BSpec, but reality doesn't agree. Just set them up in | |
8464 | * a way that results in the correct picture. | |
8465 | */ | |
8466 | I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16); | |
8467 | I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0); | |
8468 | ||
8469 | I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff); | |
8470 | I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0); | |
8471 | ||
8472 | I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0); | |
8473 | I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16); | |
8474 | ||
8475 | I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0); | |
8476 | I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0); | |
8477 | I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0); | |
8478 | ||
8479 | if (INTEL_INFO(dev)->gen > 6) { | |
8480 | uint16_t postoff = 0; | |
8481 | ||
6e3c9717 | 8482 | if (intel_crtc->config->limited_color_range) |
32cf0cb0 | 8483 | postoff = (16 * (1 << 12) / 255) & 0x1fff; |
86d3efce VS |
8484 | |
8485 | I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff); | |
8486 | I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff); | |
8487 | I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff); | |
8488 | ||
8489 | I915_WRITE(PIPE_CSC_MODE(pipe), 0); | |
8490 | } else { | |
8491 | uint32_t mode = CSC_MODE_YUV_TO_RGB; | |
8492 | ||
6e3c9717 | 8493 | if (intel_crtc->config->limited_color_range) |
86d3efce VS |
8494 | mode |= CSC_BLACK_SCREEN_OFFSET; |
8495 | ||
8496 | I915_WRITE(PIPE_CSC_MODE(pipe), mode); | |
8497 | } | |
8498 | } | |
8499 | ||
6ff93609 | 8500 | static void haswell_set_pipeconf(struct drm_crtc *crtc) |
ee2b0b38 | 8501 | { |
756f85cf PZ |
8502 | struct drm_device *dev = crtc->dev; |
8503 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee2b0b38 | 8504 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
756f85cf | 8505 | enum pipe pipe = intel_crtc->pipe; |
6e3c9717 | 8506 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
ee2b0b38 PZ |
8507 | uint32_t val; |
8508 | ||
3eff4faa | 8509 | val = 0; |
ee2b0b38 | 8510 | |
6e3c9717 | 8511 | if (IS_HASWELL(dev) && intel_crtc->config->dither) |
ee2b0b38 PZ |
8512 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
8513 | ||
6e3c9717 | 8514 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
ee2b0b38 PZ |
8515 | val |= PIPECONF_INTERLACED_ILK; |
8516 | else | |
8517 | val |= PIPECONF_PROGRESSIVE; | |
8518 | ||
702e7a56 PZ |
8519 | I915_WRITE(PIPECONF(cpu_transcoder), val); |
8520 | POSTING_READ(PIPECONF(cpu_transcoder)); | |
3eff4faa DV |
8521 | |
8522 | I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT); | |
8523 | POSTING_READ(GAMMA_MODE(intel_crtc->pipe)); | |
756f85cf | 8524 | |
3cdf122c | 8525 | if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) { |
756f85cf PZ |
8526 | val = 0; |
8527 | ||
6e3c9717 | 8528 | switch (intel_crtc->config->pipe_bpp) { |
756f85cf PZ |
8529 | case 18: |
8530 | val |= PIPEMISC_DITHER_6_BPC; | |
8531 | break; | |
8532 | case 24: | |
8533 | val |= PIPEMISC_DITHER_8_BPC; | |
8534 | break; | |
8535 | case 30: | |
8536 | val |= PIPEMISC_DITHER_10_BPC; | |
8537 | break; | |
8538 | case 36: | |
8539 | val |= PIPEMISC_DITHER_12_BPC; | |
8540 | break; | |
8541 | default: | |
8542 | /* Case prevented by pipe_config_set_bpp. */ | |
8543 | BUG(); | |
8544 | } | |
8545 | ||
6e3c9717 | 8546 | if (intel_crtc->config->dither) |
756f85cf PZ |
8547 | val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; |
8548 | ||
8549 | I915_WRITE(PIPEMISC(pipe), val); | |
8550 | } | |
ee2b0b38 PZ |
8551 | } |
8552 | ||
6591c6e4 | 8553 | static bool ironlake_compute_clocks(struct drm_crtc *crtc, |
190f68c5 | 8554 | struct intel_crtc_state *crtc_state, |
6591c6e4 PZ |
8555 | intel_clock_t *clock, |
8556 | bool *has_reduced_clock, | |
8557 | intel_clock_t *reduced_clock) | |
8558 | { | |
8559 | struct drm_device *dev = crtc->dev; | |
8560 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6591c6e4 | 8561 | int refclk; |
d4906093 | 8562 | const intel_limit_t *limit; |
a16af721 | 8563 | bool ret, is_lvds = false; |
79e53945 | 8564 | |
a93e255f | 8565 | is_lvds = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS); |
79e53945 | 8566 | |
55bb9992 | 8567 | refclk = ironlake_get_refclk(crtc_state); |
79e53945 | 8568 | |
d4906093 ML |
8569 | /* |
8570 | * Returns a set of divisors for the desired target clock with the given | |
8571 | * refclk, or FALSE. The returned values represent the clock equation: | |
8572 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
8573 | */ | |
a93e255f ACO |
8574 | limit = intel_limit(crtc_state, refclk); |
8575 | ret = dev_priv->display.find_dpll(limit, crtc_state, | |
190f68c5 | 8576 | crtc_state->port_clock, |
ee9300bb | 8577 | refclk, NULL, clock); |
6591c6e4 PZ |
8578 | if (!ret) |
8579 | return false; | |
cda4b7d3 | 8580 | |
ddc9003c | 8581 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
cec2f356 SP |
8582 | /* |
8583 | * Ensure we match the reduced clock's P to the target clock. | |
8584 | * If the clocks don't match, we can't switch the display clock | |
8585 | * by using the FP0/FP1. In such case we will disable the LVDS | |
8586 | * downclock feature. | |
8587 | */ | |
ee9300bb | 8588 | *has_reduced_clock = |
a93e255f | 8589 | dev_priv->display.find_dpll(limit, crtc_state, |
ee9300bb DV |
8590 | dev_priv->lvds_downclock, |
8591 | refclk, clock, | |
8592 | reduced_clock); | |
652c393a | 8593 | } |
61e9653f | 8594 | |
6591c6e4 PZ |
8595 | return true; |
8596 | } | |
8597 | ||
d4b1931c PZ |
8598 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) |
8599 | { | |
8600 | /* | |
8601 | * Account for spread spectrum to avoid | |
8602 | * oversubscribing the link. Max center spread | |
8603 | * is 2.5%; use 5% for safety's sake. | |
8604 | */ | |
8605 | u32 bps = target_clock * bpp * 21 / 20; | |
619d4d04 | 8606 | return DIV_ROUND_UP(bps, link_bw * 8); |
d4b1931c PZ |
8607 | } |
8608 | ||
7429e9d4 | 8609 | static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor) |
6cf86a5e | 8610 | { |
7429e9d4 | 8611 | return i9xx_dpll_compute_m(dpll) < factor * dpll->n; |
f48d8f23 PZ |
8612 | } |
8613 | ||
de13a2e3 | 8614 | static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc, |
190f68c5 | 8615 | struct intel_crtc_state *crtc_state, |
7429e9d4 | 8616 | u32 *fp, |
9a7c7890 | 8617 | intel_clock_t *reduced_clock, u32 *fp2) |
79e53945 | 8618 | { |
de13a2e3 | 8619 | struct drm_crtc *crtc = &intel_crtc->base; |
79e53945 JB |
8620 | struct drm_device *dev = crtc->dev; |
8621 | struct drm_i915_private *dev_priv = dev->dev_private; | |
55bb9992 | 8622 | struct drm_atomic_state *state = crtc_state->base.state; |
da3ced29 | 8623 | struct drm_connector *connector; |
55bb9992 ACO |
8624 | struct drm_connector_state *connector_state; |
8625 | struct intel_encoder *encoder; | |
de13a2e3 | 8626 | uint32_t dpll; |
55bb9992 | 8627 | int factor, num_connectors = 0, i; |
09ede541 | 8628 | bool is_lvds = false, is_sdvo = false; |
79e53945 | 8629 | |
da3ced29 | 8630 | for_each_connector_in_state(state, connector, connector_state, i) { |
55bb9992 ACO |
8631 | if (connector_state->crtc != crtc_state->base.crtc) |
8632 | continue; | |
8633 | ||
8634 | encoder = to_intel_encoder(connector_state->best_encoder); | |
8635 | ||
8636 | switch (encoder->type) { | |
79e53945 JB |
8637 | case INTEL_OUTPUT_LVDS: |
8638 | is_lvds = true; | |
8639 | break; | |
8640 | case INTEL_OUTPUT_SDVO: | |
7d57382e | 8641 | case INTEL_OUTPUT_HDMI: |
79e53945 | 8642 | is_sdvo = true; |
79e53945 | 8643 | break; |
6847d71b PZ |
8644 | default: |
8645 | break; | |
79e53945 | 8646 | } |
43565a06 | 8647 | |
c751ce4f | 8648 | num_connectors++; |
79e53945 | 8649 | } |
79e53945 | 8650 | |
c1858123 | 8651 | /* Enable autotuning of the PLL clock (if permissible) */ |
8febb297 EA |
8652 | factor = 21; |
8653 | if (is_lvds) { | |
8654 | if ((intel_panel_use_ssc(dev_priv) && | |
e91e941b | 8655 | dev_priv->vbt.lvds_ssc_freq == 100000) || |
f0b44056 | 8656 | (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev))) |
8febb297 | 8657 | factor = 25; |
190f68c5 | 8658 | } else if (crtc_state->sdvo_tv_clock) |
8febb297 | 8659 | factor = 20; |
c1858123 | 8660 | |
190f68c5 | 8661 | if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor)) |
7d0ac5b7 | 8662 | *fp |= FP_CB_TUNE; |
2c07245f | 8663 | |
9a7c7890 DV |
8664 | if (fp2 && (reduced_clock->m < factor * reduced_clock->n)) |
8665 | *fp2 |= FP_CB_TUNE; | |
8666 | ||
5eddb70b | 8667 | dpll = 0; |
2c07245f | 8668 | |
a07d6787 EA |
8669 | if (is_lvds) |
8670 | dpll |= DPLLB_MODE_LVDS; | |
8671 | else | |
8672 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
198a037f | 8673 | |
190f68c5 | 8674 | dpll |= (crtc_state->pixel_multiplier - 1) |
ef1b460d | 8675 | << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; |
198a037f DV |
8676 | |
8677 | if (is_sdvo) | |
4a33e48d | 8678 | dpll |= DPLL_SDVO_HIGH_SPEED; |
190f68c5 | 8679 | if (crtc_state->has_dp_encoder) |
4a33e48d | 8680 | dpll |= DPLL_SDVO_HIGH_SPEED; |
79e53945 | 8681 | |
a07d6787 | 8682 | /* compute bitmask from p1 value */ |
190f68c5 | 8683 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
a07d6787 | 8684 | /* also FPA1 */ |
190f68c5 | 8685 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
a07d6787 | 8686 | |
190f68c5 | 8687 | switch (crtc_state->dpll.p2) { |
a07d6787 EA |
8688 | case 5: |
8689 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
8690 | break; | |
8691 | case 7: | |
8692 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
8693 | break; | |
8694 | case 10: | |
8695 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
8696 | break; | |
8697 | case 14: | |
8698 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
8699 | break; | |
79e53945 JB |
8700 | } |
8701 | ||
b4c09f3b | 8702 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
43565a06 | 8703 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
79e53945 JB |
8704 | else |
8705 | dpll |= PLL_REF_INPUT_DREFCLK; | |
8706 | ||
959e16d6 | 8707 | return dpll | DPLL_VCO_ENABLE; |
de13a2e3 PZ |
8708 | } |
8709 | ||
190f68c5 ACO |
8710 | static int ironlake_crtc_compute_clock(struct intel_crtc *crtc, |
8711 | struct intel_crtc_state *crtc_state) | |
de13a2e3 | 8712 | { |
c7653199 | 8713 | struct drm_device *dev = crtc->base.dev; |
de13a2e3 | 8714 | intel_clock_t clock, reduced_clock; |
cbbab5bd | 8715 | u32 dpll = 0, fp = 0, fp2 = 0; |
e2f12b07 | 8716 | bool ok, has_reduced_clock = false; |
8b47047b | 8717 | bool is_lvds = false; |
e2b78267 | 8718 | struct intel_shared_dpll *pll; |
de13a2e3 | 8719 | |
dd3cd74a ACO |
8720 | memset(&crtc_state->dpll_hw_state, 0, |
8721 | sizeof(crtc_state->dpll_hw_state)); | |
8722 | ||
409ee761 | 8723 | is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS); |
79e53945 | 8724 | |
5dc5298b PZ |
8725 | WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)), |
8726 | "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev)); | |
a07d6787 | 8727 | |
190f68c5 | 8728 | ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock, |
de13a2e3 | 8729 | &has_reduced_clock, &reduced_clock); |
190f68c5 | 8730 | if (!ok && !crtc_state->clock_set) { |
de13a2e3 PZ |
8731 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
8732 | return -EINVAL; | |
79e53945 | 8733 | } |
f47709a9 | 8734 | /* Compat-code for transition, will disappear. */ |
190f68c5 ACO |
8735 | if (!crtc_state->clock_set) { |
8736 | crtc_state->dpll.n = clock.n; | |
8737 | crtc_state->dpll.m1 = clock.m1; | |
8738 | crtc_state->dpll.m2 = clock.m2; | |
8739 | crtc_state->dpll.p1 = clock.p1; | |
8740 | crtc_state->dpll.p2 = clock.p2; | |
f47709a9 | 8741 | } |
79e53945 | 8742 | |
5dc5298b | 8743 | /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ |
190f68c5 ACO |
8744 | if (crtc_state->has_pch_encoder) { |
8745 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); | |
cbbab5bd | 8746 | if (has_reduced_clock) |
7429e9d4 | 8747 | fp2 = i9xx_dpll_compute_fp(&reduced_clock); |
cbbab5bd | 8748 | |
190f68c5 | 8749 | dpll = ironlake_compute_dpll(crtc, crtc_state, |
cbbab5bd DV |
8750 | &fp, &reduced_clock, |
8751 | has_reduced_clock ? &fp2 : NULL); | |
8752 | ||
190f68c5 ACO |
8753 | crtc_state->dpll_hw_state.dpll = dpll; |
8754 | crtc_state->dpll_hw_state.fp0 = fp; | |
66e985c0 | 8755 | if (has_reduced_clock) |
190f68c5 | 8756 | crtc_state->dpll_hw_state.fp1 = fp2; |
66e985c0 | 8757 | else |
190f68c5 | 8758 | crtc_state->dpll_hw_state.fp1 = fp; |
66e985c0 | 8759 | |
190f68c5 | 8760 | pll = intel_get_shared_dpll(crtc, crtc_state); |
ee7b9f93 | 8761 | if (pll == NULL) { |
84f44ce7 | 8762 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", |
c7653199 | 8763 | pipe_name(crtc->pipe)); |
4b645f14 JB |
8764 | return -EINVAL; |
8765 | } | |
3fb37703 | 8766 | } |
79e53945 | 8767 | |
ab585dea | 8768 | if (is_lvds && has_reduced_clock) |
c7653199 | 8769 | crtc->lowfreq_avail = true; |
bcd644e0 | 8770 | else |
c7653199 | 8771 | crtc->lowfreq_avail = false; |
e2b78267 | 8772 | |
c8f7a0db | 8773 | return 0; |
79e53945 JB |
8774 | } |
8775 | ||
eb14cb74 VS |
8776 | static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc, |
8777 | struct intel_link_m_n *m_n) | |
8778 | { | |
8779 | struct drm_device *dev = crtc->base.dev; | |
8780 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8781 | enum pipe pipe = crtc->pipe; | |
8782 | ||
8783 | m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe)); | |
8784 | m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe)); | |
8785 | m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
8786 | & ~TU_SIZE_MASK; | |
8787 | m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe)); | |
8788 | m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
8789 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
8790 | } | |
8791 | ||
8792 | static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, | |
8793 | enum transcoder transcoder, | |
b95af8be VK |
8794 | struct intel_link_m_n *m_n, |
8795 | struct intel_link_m_n *m2_n2) | |
72419203 DV |
8796 | { |
8797 | struct drm_device *dev = crtc->base.dev; | |
8798 | struct drm_i915_private *dev_priv = dev->dev_private; | |
eb14cb74 | 8799 | enum pipe pipe = crtc->pipe; |
72419203 | 8800 | |
eb14cb74 VS |
8801 | if (INTEL_INFO(dev)->gen >= 5) { |
8802 | m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder)); | |
8803 | m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder)); | |
8804 | m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder)) | |
8805 | & ~TU_SIZE_MASK; | |
8806 | m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder)); | |
8807 | m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder)) | |
8808 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
b95af8be VK |
8809 | /* Read M2_N2 registers only for gen < 8 (M2_N2 available for |
8810 | * gen < 8) and if DRRS is supported (to make sure the | |
8811 | * registers are not unnecessarily read). | |
8812 | */ | |
8813 | if (m2_n2 && INTEL_INFO(dev)->gen < 8 && | |
6e3c9717 | 8814 | crtc->config->has_drrs) { |
b95af8be VK |
8815 | m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder)); |
8816 | m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder)); | |
8817 | m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder)) | |
8818 | & ~TU_SIZE_MASK; | |
8819 | m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder)); | |
8820 | m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder)) | |
8821 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
8822 | } | |
eb14cb74 VS |
8823 | } else { |
8824 | m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe)); | |
8825 | m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe)); | |
8826 | m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe)) | |
8827 | & ~TU_SIZE_MASK; | |
8828 | m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe)); | |
8829 | m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe)) | |
8830 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
8831 | } | |
8832 | } | |
8833 | ||
8834 | void intel_dp_get_m_n(struct intel_crtc *crtc, | |
5cec258b | 8835 | struct intel_crtc_state *pipe_config) |
eb14cb74 | 8836 | { |
681a8504 | 8837 | if (pipe_config->has_pch_encoder) |
eb14cb74 VS |
8838 | intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n); |
8839 | else | |
8840 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be VK |
8841 | &pipe_config->dp_m_n, |
8842 | &pipe_config->dp_m2_n2); | |
eb14cb74 | 8843 | } |
72419203 | 8844 | |
eb14cb74 | 8845 | static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc, |
5cec258b | 8846 | struct intel_crtc_state *pipe_config) |
eb14cb74 VS |
8847 | { |
8848 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be | 8849 | &pipe_config->fdi_m_n, NULL); |
72419203 DV |
8850 | } |
8851 | ||
bd2e244f | 8852 | static void skylake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 8853 | struct intel_crtc_state *pipe_config) |
bd2e244f JB |
8854 | { |
8855 | struct drm_device *dev = crtc->base.dev; | |
8856 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a1b2278e CK |
8857 | struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state; |
8858 | uint32_t ps_ctrl = 0; | |
8859 | int id = -1; | |
8860 | int i; | |
bd2e244f | 8861 | |
a1b2278e CK |
8862 | /* find scaler attached to this pipe */ |
8863 | for (i = 0; i < crtc->num_scalers; i++) { | |
8864 | ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i)); | |
8865 | if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) { | |
8866 | id = i; | |
8867 | pipe_config->pch_pfit.enabled = true; | |
8868 | pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i)); | |
8869 | pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i)); | |
8870 | break; | |
8871 | } | |
8872 | } | |
bd2e244f | 8873 | |
a1b2278e CK |
8874 | scaler_state->scaler_id = id; |
8875 | if (id >= 0) { | |
8876 | scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX); | |
8877 | } else { | |
8878 | scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX); | |
bd2e244f JB |
8879 | } |
8880 | } | |
8881 | ||
5724dbd1 DL |
8882 | static void |
8883 | skylake_get_initial_plane_config(struct intel_crtc *crtc, | |
8884 | struct intel_initial_plane_config *plane_config) | |
bc8d7dff DL |
8885 | { |
8886 | struct drm_device *dev = crtc->base.dev; | |
8887 | struct drm_i915_private *dev_priv = dev->dev_private; | |
40f46283 | 8888 | u32 val, base, offset, stride_mult, tiling; |
bc8d7dff DL |
8889 | int pipe = crtc->pipe; |
8890 | int fourcc, pixel_format; | |
6761dd31 | 8891 | unsigned int aligned_height; |
bc8d7dff | 8892 | struct drm_framebuffer *fb; |
1b842c89 | 8893 | struct intel_framebuffer *intel_fb; |
bc8d7dff | 8894 | |
d9806c9f | 8895 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 8896 | if (!intel_fb) { |
bc8d7dff DL |
8897 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
8898 | return; | |
8899 | } | |
8900 | ||
1b842c89 DL |
8901 | fb = &intel_fb->base; |
8902 | ||
bc8d7dff | 8903 | val = I915_READ(PLANE_CTL(pipe, 0)); |
42a7b088 DL |
8904 | if (!(val & PLANE_CTL_ENABLE)) |
8905 | goto error; | |
8906 | ||
bc8d7dff DL |
8907 | pixel_format = val & PLANE_CTL_FORMAT_MASK; |
8908 | fourcc = skl_format_to_fourcc(pixel_format, | |
8909 | val & PLANE_CTL_ORDER_RGBX, | |
8910 | val & PLANE_CTL_ALPHA_MASK); | |
8911 | fb->pixel_format = fourcc; | |
8912 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
8913 | ||
40f46283 DL |
8914 | tiling = val & PLANE_CTL_TILED_MASK; |
8915 | switch (tiling) { | |
8916 | case PLANE_CTL_TILED_LINEAR: | |
8917 | fb->modifier[0] = DRM_FORMAT_MOD_NONE; | |
8918 | break; | |
8919 | case PLANE_CTL_TILED_X: | |
8920 | plane_config->tiling = I915_TILING_X; | |
8921 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; | |
8922 | break; | |
8923 | case PLANE_CTL_TILED_Y: | |
8924 | fb->modifier[0] = I915_FORMAT_MOD_Y_TILED; | |
8925 | break; | |
8926 | case PLANE_CTL_TILED_YF: | |
8927 | fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED; | |
8928 | break; | |
8929 | default: | |
8930 | MISSING_CASE(tiling); | |
8931 | goto error; | |
8932 | } | |
8933 | ||
bc8d7dff DL |
8934 | base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000; |
8935 | plane_config->base = base; | |
8936 | ||
8937 | offset = I915_READ(PLANE_OFFSET(pipe, 0)); | |
8938 | ||
8939 | val = I915_READ(PLANE_SIZE(pipe, 0)); | |
8940 | fb->height = ((val >> 16) & 0xfff) + 1; | |
8941 | fb->width = ((val >> 0) & 0x1fff) + 1; | |
8942 | ||
8943 | val = I915_READ(PLANE_STRIDE(pipe, 0)); | |
40f46283 DL |
8944 | stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0], |
8945 | fb->pixel_format); | |
bc8d7dff DL |
8946 | fb->pitches[0] = (val & 0x3ff) * stride_mult; |
8947 | ||
8948 | aligned_height = intel_fb_align_height(dev, fb->height, | |
091df6cb DV |
8949 | fb->pixel_format, |
8950 | fb->modifier[0]); | |
bc8d7dff | 8951 | |
f37b5c2b | 8952 | plane_config->size = fb->pitches[0] * aligned_height; |
bc8d7dff DL |
8953 | |
8954 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", | |
8955 | pipe_name(pipe), fb->width, fb->height, | |
8956 | fb->bits_per_pixel, base, fb->pitches[0], | |
8957 | plane_config->size); | |
8958 | ||
2d14030b | 8959 | plane_config->fb = intel_fb; |
bc8d7dff DL |
8960 | return; |
8961 | ||
8962 | error: | |
8963 | kfree(fb); | |
8964 | } | |
8965 | ||
2fa2fe9a | 8966 | static void ironlake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 8967 | struct intel_crtc_state *pipe_config) |
2fa2fe9a DV |
8968 | { |
8969 | struct drm_device *dev = crtc->base.dev; | |
8970 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8971 | uint32_t tmp; | |
8972 | ||
8973 | tmp = I915_READ(PF_CTL(crtc->pipe)); | |
8974 | ||
8975 | if (tmp & PF_ENABLE) { | |
fd4daa9c | 8976 | pipe_config->pch_pfit.enabled = true; |
2fa2fe9a DV |
8977 | pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe)); |
8978 | pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe)); | |
cb8b2a30 DV |
8979 | |
8980 | /* We currently do not free assignements of panel fitters on | |
8981 | * ivb/hsw (since we don't use the higher upscaling modes which | |
8982 | * differentiates them) so just WARN about this case for now. */ | |
8983 | if (IS_GEN7(dev)) { | |
8984 | WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) != | |
8985 | PF_PIPE_SEL_IVB(crtc->pipe)); | |
8986 | } | |
2fa2fe9a | 8987 | } |
79e53945 JB |
8988 | } |
8989 | ||
5724dbd1 DL |
8990 | static void |
8991 | ironlake_get_initial_plane_config(struct intel_crtc *crtc, | |
8992 | struct intel_initial_plane_config *plane_config) | |
4c6baa59 JB |
8993 | { |
8994 | struct drm_device *dev = crtc->base.dev; | |
8995 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8996 | u32 val, base, offset; | |
aeee5a49 | 8997 | int pipe = crtc->pipe; |
4c6baa59 | 8998 | int fourcc, pixel_format; |
6761dd31 | 8999 | unsigned int aligned_height; |
b113d5ee | 9000 | struct drm_framebuffer *fb; |
1b842c89 | 9001 | struct intel_framebuffer *intel_fb; |
4c6baa59 | 9002 | |
42a7b088 DL |
9003 | val = I915_READ(DSPCNTR(pipe)); |
9004 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
9005 | return; | |
9006 | ||
d9806c9f | 9007 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 9008 | if (!intel_fb) { |
4c6baa59 JB |
9009 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
9010 | return; | |
9011 | } | |
9012 | ||
1b842c89 DL |
9013 | fb = &intel_fb->base; |
9014 | ||
18c5247e DV |
9015 | if (INTEL_INFO(dev)->gen >= 4) { |
9016 | if (val & DISPPLANE_TILED) { | |
49af449b | 9017 | plane_config->tiling = I915_TILING_X; |
18c5247e DV |
9018 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; |
9019 | } | |
9020 | } | |
4c6baa59 JB |
9021 | |
9022 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 9023 | fourcc = i9xx_format_to_fourcc(pixel_format); |
b113d5ee DL |
9024 | fb->pixel_format = fourcc; |
9025 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
4c6baa59 | 9026 | |
aeee5a49 | 9027 | base = I915_READ(DSPSURF(pipe)) & 0xfffff000; |
4c6baa59 | 9028 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
aeee5a49 | 9029 | offset = I915_READ(DSPOFFSET(pipe)); |
4c6baa59 | 9030 | } else { |
49af449b | 9031 | if (plane_config->tiling) |
aeee5a49 | 9032 | offset = I915_READ(DSPTILEOFF(pipe)); |
4c6baa59 | 9033 | else |
aeee5a49 | 9034 | offset = I915_READ(DSPLINOFF(pipe)); |
4c6baa59 JB |
9035 | } |
9036 | plane_config->base = base; | |
9037 | ||
9038 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
9039 | fb->width = ((val >> 16) & 0xfff) + 1; |
9040 | fb->height = ((val >> 0) & 0xfff) + 1; | |
4c6baa59 JB |
9041 | |
9042 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 9043 | fb->pitches[0] = val & 0xffffffc0; |
4c6baa59 | 9044 | |
b113d5ee | 9045 | aligned_height = intel_fb_align_height(dev, fb->height, |
091df6cb DV |
9046 | fb->pixel_format, |
9047 | fb->modifier[0]); | |
4c6baa59 | 9048 | |
f37b5c2b | 9049 | plane_config->size = fb->pitches[0] * aligned_height; |
4c6baa59 | 9050 | |
2844a921 DL |
9051 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
9052 | pipe_name(pipe), fb->width, fb->height, | |
9053 | fb->bits_per_pixel, base, fb->pitches[0], | |
9054 | plane_config->size); | |
b113d5ee | 9055 | |
2d14030b | 9056 | plane_config->fb = intel_fb; |
4c6baa59 JB |
9057 | } |
9058 | ||
0e8ffe1b | 9059 | static bool ironlake_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 9060 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
9061 | { |
9062 | struct drm_device *dev = crtc->base.dev; | |
9063 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9064 | uint32_t tmp; | |
9065 | ||
f458ebbc DV |
9066 | if (!intel_display_power_is_enabled(dev_priv, |
9067 | POWER_DOMAIN_PIPE(crtc->pipe))) | |
930e8c9e PZ |
9068 | return false; |
9069 | ||
e143a21c | 9070 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 | 9071 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
eccb140b | 9072 | |
0e8ffe1b DV |
9073 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
9074 | if (!(tmp & PIPECONF_ENABLE)) | |
9075 | return false; | |
9076 | ||
42571aef VS |
9077 | switch (tmp & PIPECONF_BPC_MASK) { |
9078 | case PIPECONF_6BPC: | |
9079 | pipe_config->pipe_bpp = 18; | |
9080 | break; | |
9081 | case PIPECONF_8BPC: | |
9082 | pipe_config->pipe_bpp = 24; | |
9083 | break; | |
9084 | case PIPECONF_10BPC: | |
9085 | pipe_config->pipe_bpp = 30; | |
9086 | break; | |
9087 | case PIPECONF_12BPC: | |
9088 | pipe_config->pipe_bpp = 36; | |
9089 | break; | |
9090 | default: | |
9091 | break; | |
9092 | } | |
9093 | ||
b5a9fa09 DV |
9094 | if (tmp & PIPECONF_COLOR_RANGE_SELECT) |
9095 | pipe_config->limited_color_range = true; | |
9096 | ||
ab9412ba | 9097 | if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { |
66e985c0 DV |
9098 | struct intel_shared_dpll *pll; |
9099 | ||
88adfff1 DV |
9100 | pipe_config->has_pch_encoder = true; |
9101 | ||
627eb5a3 DV |
9102 | tmp = I915_READ(FDI_RX_CTL(crtc->pipe)); |
9103 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
9104 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
72419203 DV |
9105 | |
9106 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
6c49f241 | 9107 | |
c0d43d62 | 9108 | if (HAS_PCH_IBX(dev_priv->dev)) { |
d94ab068 DV |
9109 | pipe_config->shared_dpll = |
9110 | (enum intel_dpll_id) crtc->pipe; | |
c0d43d62 DV |
9111 | } else { |
9112 | tmp = I915_READ(PCH_DPLL_SEL); | |
9113 | if (tmp & TRANS_DPLLB_SEL(crtc->pipe)) | |
9114 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B; | |
9115 | else | |
9116 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A; | |
9117 | } | |
66e985c0 DV |
9118 | |
9119 | pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; | |
9120 | ||
9121 | WARN_ON(!pll->get_hw_state(dev_priv, pll, | |
9122 | &pipe_config->dpll_hw_state)); | |
c93f54cf DV |
9123 | |
9124 | tmp = pipe_config->dpll_hw_state.dpll; | |
9125 | pipe_config->pixel_multiplier = | |
9126 | ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK) | |
9127 | >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1; | |
18442d08 VS |
9128 | |
9129 | ironlake_pch_clock_get(crtc, pipe_config); | |
6c49f241 DV |
9130 | } else { |
9131 | pipe_config->pixel_multiplier = 1; | |
627eb5a3 DV |
9132 | } |
9133 | ||
1bd1bd80 DV |
9134 | intel_get_pipe_timings(crtc, pipe_config); |
9135 | ||
2fa2fe9a DV |
9136 | ironlake_get_pfit_config(crtc, pipe_config); |
9137 | ||
0e8ffe1b DV |
9138 | return true; |
9139 | } | |
9140 | ||
be256dc7 PZ |
9141 | static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) |
9142 | { | |
9143 | struct drm_device *dev = dev_priv->dev; | |
be256dc7 | 9144 | struct intel_crtc *crtc; |
be256dc7 | 9145 | |
d3fcc808 | 9146 | for_each_intel_crtc(dev, crtc) |
e2c719b7 | 9147 | I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n", |
be256dc7 PZ |
9148 | pipe_name(crtc->pipe)); |
9149 | ||
e2c719b7 RC |
9150 | I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n"); |
9151 | I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n"); | |
9152 | I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n"); | |
9153 | I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n"); | |
9154 | I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n"); | |
9155 | I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, | |
be256dc7 | 9156 | "CPU PWM1 enabled\n"); |
c5107b87 | 9157 | if (IS_HASWELL(dev)) |
e2c719b7 | 9158 | I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, |
c5107b87 | 9159 | "CPU PWM2 enabled\n"); |
e2c719b7 | 9160 | I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, |
be256dc7 | 9161 | "PCH PWM1 enabled\n"); |
e2c719b7 | 9162 | I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, |
be256dc7 | 9163 | "Utility pin enabled\n"); |
e2c719b7 | 9164 | I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n"); |
be256dc7 | 9165 | |
9926ada1 PZ |
9166 | /* |
9167 | * In theory we can still leave IRQs enabled, as long as only the HPD | |
9168 | * interrupts remain enabled. We used to check for that, but since it's | |
9169 | * gen-specific and since we only disable LCPLL after we fully disable | |
9170 | * the interrupts, the check below should be enough. | |
9171 | */ | |
e2c719b7 | 9172 | I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n"); |
be256dc7 PZ |
9173 | } |
9174 | ||
9ccd5aeb PZ |
9175 | static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv) |
9176 | { | |
9177 | struct drm_device *dev = dev_priv->dev; | |
9178 | ||
9179 | if (IS_HASWELL(dev)) | |
9180 | return I915_READ(D_COMP_HSW); | |
9181 | else | |
9182 | return I915_READ(D_COMP_BDW); | |
9183 | } | |
9184 | ||
3c4c9b81 PZ |
9185 | static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val) |
9186 | { | |
9187 | struct drm_device *dev = dev_priv->dev; | |
9188 | ||
9189 | if (IS_HASWELL(dev)) { | |
9190 | mutex_lock(&dev_priv->rps.hw_lock); | |
9191 | if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, | |
9192 | val)) | |
f475dadf | 9193 | DRM_ERROR("Failed to write to D_COMP\n"); |
3c4c9b81 PZ |
9194 | mutex_unlock(&dev_priv->rps.hw_lock); |
9195 | } else { | |
9ccd5aeb PZ |
9196 | I915_WRITE(D_COMP_BDW, val); |
9197 | POSTING_READ(D_COMP_BDW); | |
3c4c9b81 | 9198 | } |
be256dc7 PZ |
9199 | } |
9200 | ||
9201 | /* | |
9202 | * This function implements pieces of two sequences from BSpec: | |
9203 | * - Sequence for display software to disable LCPLL | |
9204 | * - Sequence for display software to allow package C8+ | |
9205 | * The steps implemented here are just the steps that actually touch the LCPLL | |
9206 | * register. Callers should take care of disabling all the display engine | |
9207 | * functions, doing the mode unset, fixing interrupts, etc. | |
9208 | */ | |
6ff58d53 PZ |
9209 | static void hsw_disable_lcpll(struct drm_i915_private *dev_priv, |
9210 | bool switch_to_fclk, bool allow_power_down) | |
be256dc7 PZ |
9211 | { |
9212 | uint32_t val; | |
9213 | ||
9214 | assert_can_disable_lcpll(dev_priv); | |
9215 | ||
9216 | val = I915_READ(LCPLL_CTL); | |
9217 | ||
9218 | if (switch_to_fclk) { | |
9219 | val |= LCPLL_CD_SOURCE_FCLK; | |
9220 | I915_WRITE(LCPLL_CTL, val); | |
9221 | ||
9222 | if (wait_for_atomic_us(I915_READ(LCPLL_CTL) & | |
9223 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
9224 | DRM_ERROR("Switching to FCLK failed\n"); | |
9225 | ||
9226 | val = I915_READ(LCPLL_CTL); | |
9227 | } | |
9228 | ||
9229 | val |= LCPLL_PLL_DISABLE; | |
9230 | I915_WRITE(LCPLL_CTL, val); | |
9231 | POSTING_READ(LCPLL_CTL); | |
9232 | ||
9233 | if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1)) | |
9234 | DRM_ERROR("LCPLL still locked\n"); | |
9235 | ||
9ccd5aeb | 9236 | val = hsw_read_dcomp(dev_priv); |
be256dc7 | 9237 | val |= D_COMP_COMP_DISABLE; |
3c4c9b81 | 9238 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
9239 | ndelay(100); |
9240 | ||
9ccd5aeb PZ |
9241 | if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0, |
9242 | 1)) | |
be256dc7 PZ |
9243 | DRM_ERROR("D_COMP RCOMP still in progress\n"); |
9244 | ||
9245 | if (allow_power_down) { | |
9246 | val = I915_READ(LCPLL_CTL); | |
9247 | val |= LCPLL_POWER_DOWN_ALLOW; | |
9248 | I915_WRITE(LCPLL_CTL, val); | |
9249 | POSTING_READ(LCPLL_CTL); | |
9250 | } | |
9251 | } | |
9252 | ||
9253 | /* | |
9254 | * Fully restores LCPLL, disallowing power down and switching back to LCPLL | |
9255 | * source. | |
9256 | */ | |
6ff58d53 | 9257 | static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) |
be256dc7 PZ |
9258 | { |
9259 | uint32_t val; | |
9260 | ||
9261 | val = I915_READ(LCPLL_CTL); | |
9262 | ||
9263 | if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK | | |
9264 | LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK) | |
9265 | return; | |
9266 | ||
a8a8bd54 PZ |
9267 | /* |
9268 | * Make sure we're not on PC8 state before disabling PC8, otherwise | |
9269 | * we'll hang the machine. To prevent PC8 state, just enable force_wake. | |
a8a8bd54 | 9270 | */ |
59bad947 | 9271 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
215733fa | 9272 | |
be256dc7 PZ |
9273 | if (val & LCPLL_POWER_DOWN_ALLOW) { |
9274 | val &= ~LCPLL_POWER_DOWN_ALLOW; | |
9275 | I915_WRITE(LCPLL_CTL, val); | |
35d8f2eb | 9276 | POSTING_READ(LCPLL_CTL); |
be256dc7 PZ |
9277 | } |
9278 | ||
9ccd5aeb | 9279 | val = hsw_read_dcomp(dev_priv); |
be256dc7 PZ |
9280 | val |= D_COMP_COMP_FORCE; |
9281 | val &= ~D_COMP_COMP_DISABLE; | |
3c4c9b81 | 9282 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
9283 | |
9284 | val = I915_READ(LCPLL_CTL); | |
9285 | val &= ~LCPLL_PLL_DISABLE; | |
9286 | I915_WRITE(LCPLL_CTL, val); | |
9287 | ||
9288 | if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5)) | |
9289 | DRM_ERROR("LCPLL not locked yet\n"); | |
9290 | ||
9291 | if (val & LCPLL_CD_SOURCE_FCLK) { | |
9292 | val = I915_READ(LCPLL_CTL); | |
9293 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
9294 | I915_WRITE(LCPLL_CTL, val); | |
9295 | ||
9296 | if (wait_for_atomic_us((I915_READ(LCPLL_CTL) & | |
9297 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
9298 | DRM_ERROR("Switching back to LCPLL failed\n"); | |
9299 | } | |
215733fa | 9300 | |
59bad947 | 9301 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
be256dc7 PZ |
9302 | } |
9303 | ||
765dab67 PZ |
9304 | /* |
9305 | * Package states C8 and deeper are really deep PC states that can only be | |
9306 | * reached when all the devices on the system allow it, so even if the graphics | |
9307 | * device allows PC8+, it doesn't mean the system will actually get to these | |
9308 | * states. Our driver only allows PC8+ when going into runtime PM. | |
9309 | * | |
9310 | * The requirements for PC8+ are that all the outputs are disabled, the power | |
9311 | * well is disabled and most interrupts are disabled, and these are also | |
9312 | * requirements for runtime PM. When these conditions are met, we manually do | |
9313 | * the other conditions: disable the interrupts, clocks and switch LCPLL refclk | |
9314 | * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard | |
9315 | * hang the machine. | |
9316 | * | |
9317 | * When we really reach PC8 or deeper states (not just when we allow it) we lose | |
9318 | * the state of some registers, so when we come back from PC8+ we need to | |
9319 | * restore this state. We don't get into PC8+ if we're not in RC6, so we don't | |
9320 | * need to take care of the registers kept by RC6. Notice that this happens even | |
9321 | * if we don't put the device in PCI D3 state (which is what currently happens | |
9322 | * because of the runtime PM support). | |
9323 | * | |
9324 | * For more, read "Display Sequences for Package C8" on the hardware | |
9325 | * documentation. | |
9326 | */ | |
a14cb6fc | 9327 | void hsw_enable_pc8(struct drm_i915_private *dev_priv) |
c67a470b | 9328 | { |
c67a470b PZ |
9329 | struct drm_device *dev = dev_priv->dev; |
9330 | uint32_t val; | |
9331 | ||
c67a470b PZ |
9332 | DRM_DEBUG_KMS("Enabling package C8+\n"); |
9333 | ||
c67a470b PZ |
9334 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { |
9335 | val = I915_READ(SOUTH_DSPCLK_GATE_D); | |
9336 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; | |
9337 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
9338 | } | |
9339 | ||
9340 | lpt_disable_clkout_dp(dev); | |
c67a470b PZ |
9341 | hsw_disable_lcpll(dev_priv, true, true); |
9342 | } | |
9343 | ||
a14cb6fc | 9344 | void hsw_disable_pc8(struct drm_i915_private *dev_priv) |
c67a470b PZ |
9345 | { |
9346 | struct drm_device *dev = dev_priv->dev; | |
9347 | uint32_t val; | |
9348 | ||
c67a470b PZ |
9349 | DRM_DEBUG_KMS("Disabling package C8+\n"); |
9350 | ||
9351 | hsw_restore_lcpll(dev_priv); | |
c67a470b PZ |
9352 | lpt_init_pch_refclk(dev); |
9353 | ||
9354 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { | |
9355 | val = I915_READ(SOUTH_DSPCLK_GATE_D); | |
9356 | val |= PCH_LP_PARTITION_LEVEL_DISABLE; | |
9357 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
9358 | } | |
9359 | ||
9360 | intel_prepare_ddi(dev); | |
c67a470b PZ |
9361 | } |
9362 | ||
a821fc46 | 9363 | static void broxton_modeset_global_resources(struct drm_atomic_state *old_state) |
f8437dd1 | 9364 | { |
a821fc46 | 9365 | struct drm_device *dev = old_state->dev; |
f8437dd1 | 9366 | struct drm_i915_private *dev_priv = dev->dev_private; |
a821fc46 | 9367 | int max_pixclk = intel_mode_max_pixclk(dev, NULL); |
f8437dd1 VK |
9368 | int req_cdclk; |
9369 | ||
9370 | /* see the comment in valleyview_modeset_global_resources */ | |
9371 | if (WARN_ON(max_pixclk < 0)) | |
9372 | return; | |
9373 | ||
9374 | req_cdclk = broxton_calc_cdclk(dev_priv, max_pixclk); | |
9375 | ||
9376 | if (req_cdclk != dev_priv->cdclk_freq) | |
9377 | broxton_set_cdclk(dev, req_cdclk); | |
9378 | } | |
9379 | ||
190f68c5 ACO |
9380 | static int haswell_crtc_compute_clock(struct intel_crtc *crtc, |
9381 | struct intel_crtc_state *crtc_state) | |
09b4ddf9 | 9382 | { |
190f68c5 | 9383 | if (!intel_ddi_pll_select(crtc, crtc_state)) |
6441ab5f | 9384 | return -EINVAL; |
716c2e55 | 9385 | |
c7653199 | 9386 | crtc->lowfreq_avail = false; |
644cef34 | 9387 | |
c8f7a0db | 9388 | return 0; |
79e53945 JB |
9389 | } |
9390 | ||
3760b59c S |
9391 | static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv, |
9392 | enum port port, | |
9393 | struct intel_crtc_state *pipe_config) | |
9394 | { | |
9395 | switch (port) { | |
9396 | case PORT_A: | |
9397 | pipe_config->ddi_pll_sel = SKL_DPLL0; | |
9398 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1; | |
9399 | break; | |
9400 | case PORT_B: | |
9401 | pipe_config->ddi_pll_sel = SKL_DPLL1; | |
9402 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2; | |
9403 | break; | |
9404 | case PORT_C: | |
9405 | pipe_config->ddi_pll_sel = SKL_DPLL2; | |
9406 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3; | |
9407 | break; | |
9408 | default: | |
9409 | DRM_ERROR("Incorrect port type\n"); | |
9410 | } | |
9411 | } | |
9412 | ||
96b7dfb7 S |
9413 | static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv, |
9414 | enum port port, | |
5cec258b | 9415 | struct intel_crtc_state *pipe_config) |
96b7dfb7 | 9416 | { |
3148ade7 | 9417 | u32 temp, dpll_ctl1; |
96b7dfb7 S |
9418 | |
9419 | temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port); | |
9420 | pipe_config->ddi_pll_sel = temp >> (port * 3 + 1); | |
9421 | ||
9422 | switch (pipe_config->ddi_pll_sel) { | |
3148ade7 DL |
9423 | case SKL_DPLL0: |
9424 | /* | |
9425 | * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part | |
9426 | * of the shared DPLL framework and thus needs to be read out | |
9427 | * separately | |
9428 | */ | |
9429 | dpll_ctl1 = I915_READ(DPLL_CTRL1); | |
9430 | pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f; | |
9431 | break; | |
96b7dfb7 S |
9432 | case SKL_DPLL1: |
9433 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1; | |
9434 | break; | |
9435 | case SKL_DPLL2: | |
9436 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2; | |
9437 | break; | |
9438 | case SKL_DPLL3: | |
9439 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3; | |
9440 | break; | |
96b7dfb7 S |
9441 | } |
9442 | } | |
9443 | ||
7d2c8175 DL |
9444 | static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv, |
9445 | enum port port, | |
5cec258b | 9446 | struct intel_crtc_state *pipe_config) |
7d2c8175 DL |
9447 | { |
9448 | pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port)); | |
9449 | ||
9450 | switch (pipe_config->ddi_pll_sel) { | |
9451 | case PORT_CLK_SEL_WRPLL1: | |
9452 | pipe_config->shared_dpll = DPLL_ID_WRPLL1; | |
9453 | break; | |
9454 | case PORT_CLK_SEL_WRPLL2: | |
9455 | pipe_config->shared_dpll = DPLL_ID_WRPLL2; | |
9456 | break; | |
9457 | } | |
9458 | } | |
9459 | ||
26804afd | 9460 | static void haswell_get_ddi_port_state(struct intel_crtc *crtc, |
5cec258b | 9461 | struct intel_crtc_state *pipe_config) |
26804afd DV |
9462 | { |
9463 | struct drm_device *dev = crtc->base.dev; | |
9464 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d452c5b6 | 9465 | struct intel_shared_dpll *pll; |
26804afd DV |
9466 | enum port port; |
9467 | uint32_t tmp; | |
9468 | ||
9469 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); | |
9470 | ||
9471 | port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT; | |
9472 | ||
96b7dfb7 S |
9473 | if (IS_SKYLAKE(dev)) |
9474 | skylake_get_ddi_pll(dev_priv, port, pipe_config); | |
3760b59c S |
9475 | else if (IS_BROXTON(dev)) |
9476 | bxt_get_ddi_pll(dev_priv, port, pipe_config); | |
96b7dfb7 S |
9477 | else |
9478 | haswell_get_ddi_pll(dev_priv, port, pipe_config); | |
9cd86933 | 9479 | |
d452c5b6 DV |
9480 | if (pipe_config->shared_dpll >= 0) { |
9481 | pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; | |
9482 | ||
9483 | WARN_ON(!pll->get_hw_state(dev_priv, pll, | |
9484 | &pipe_config->dpll_hw_state)); | |
9485 | } | |
9486 | ||
26804afd DV |
9487 | /* |
9488 | * Haswell has only FDI/PCH transcoder A. It is which is connected to | |
9489 | * DDI E. So just check whether this pipe is wired to DDI E and whether | |
9490 | * the PCH transcoder is on. | |
9491 | */ | |
ca370455 DL |
9492 | if (INTEL_INFO(dev)->gen < 9 && |
9493 | (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) { | |
26804afd DV |
9494 | pipe_config->has_pch_encoder = true; |
9495 | ||
9496 | tmp = I915_READ(FDI_RX_CTL(PIPE_A)); | |
9497 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
9498 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
9499 | ||
9500 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
9501 | } | |
9502 | } | |
9503 | ||
0e8ffe1b | 9504 | static bool haswell_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 9505 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
9506 | { |
9507 | struct drm_device *dev = crtc->base.dev; | |
9508 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2fa2fe9a | 9509 | enum intel_display_power_domain pfit_domain; |
0e8ffe1b DV |
9510 | uint32_t tmp; |
9511 | ||
f458ebbc | 9512 | if (!intel_display_power_is_enabled(dev_priv, |
b5482bd0 ID |
9513 | POWER_DOMAIN_PIPE(crtc->pipe))) |
9514 | return false; | |
9515 | ||
e143a21c | 9516 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 DV |
9517 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
9518 | ||
eccb140b DV |
9519 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); |
9520 | if (tmp & TRANS_DDI_FUNC_ENABLE) { | |
9521 | enum pipe trans_edp_pipe; | |
9522 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { | |
9523 | default: | |
9524 | WARN(1, "unknown pipe linked to edp transcoder\n"); | |
9525 | case TRANS_DDI_EDP_INPUT_A_ONOFF: | |
9526 | case TRANS_DDI_EDP_INPUT_A_ON: | |
9527 | trans_edp_pipe = PIPE_A; | |
9528 | break; | |
9529 | case TRANS_DDI_EDP_INPUT_B_ONOFF: | |
9530 | trans_edp_pipe = PIPE_B; | |
9531 | break; | |
9532 | case TRANS_DDI_EDP_INPUT_C_ONOFF: | |
9533 | trans_edp_pipe = PIPE_C; | |
9534 | break; | |
9535 | } | |
9536 | ||
9537 | if (trans_edp_pipe == crtc->pipe) | |
9538 | pipe_config->cpu_transcoder = TRANSCODER_EDP; | |
9539 | } | |
9540 | ||
f458ebbc | 9541 | if (!intel_display_power_is_enabled(dev_priv, |
eccb140b | 9542 | POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder))) |
2bfce950 PZ |
9543 | return false; |
9544 | ||
eccb140b | 9545 | tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder)); |
0e8ffe1b DV |
9546 | if (!(tmp & PIPECONF_ENABLE)) |
9547 | return false; | |
9548 | ||
26804afd | 9549 | haswell_get_ddi_port_state(crtc, pipe_config); |
627eb5a3 | 9550 | |
1bd1bd80 DV |
9551 | intel_get_pipe_timings(crtc, pipe_config); |
9552 | ||
a1b2278e CK |
9553 | if (INTEL_INFO(dev)->gen >= 9) { |
9554 | skl_init_scalers(dev, crtc, pipe_config); | |
9555 | } | |
9556 | ||
2fa2fe9a | 9557 | pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); |
af99ceda CK |
9558 | |
9559 | if (INTEL_INFO(dev)->gen >= 9) { | |
9560 | pipe_config->scaler_state.scaler_id = -1; | |
9561 | pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX); | |
9562 | } | |
9563 | ||
bd2e244f | 9564 | if (intel_display_power_is_enabled(dev_priv, pfit_domain)) { |
ff6d9f55 | 9565 | if (INTEL_INFO(dev)->gen == 9) |
bd2e244f | 9566 | skylake_get_pfit_config(crtc, pipe_config); |
ff6d9f55 | 9567 | else if (INTEL_INFO(dev)->gen < 9) |
bd2e244f | 9568 | ironlake_get_pfit_config(crtc, pipe_config); |
ff6d9f55 JB |
9569 | else |
9570 | MISSING_CASE(INTEL_INFO(dev)->gen); | |
bd2e244f | 9571 | } |
88adfff1 | 9572 | |
e59150dc JB |
9573 | if (IS_HASWELL(dev)) |
9574 | pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) && | |
9575 | (I915_READ(IPS_CTL) & IPS_ENABLE); | |
42db64ef | 9576 | |
ebb69c95 CT |
9577 | if (pipe_config->cpu_transcoder != TRANSCODER_EDP) { |
9578 | pipe_config->pixel_multiplier = | |
9579 | I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1; | |
9580 | } else { | |
9581 | pipe_config->pixel_multiplier = 1; | |
9582 | } | |
6c49f241 | 9583 | |
0e8ffe1b DV |
9584 | return true; |
9585 | } | |
9586 | ||
560b85bb CW |
9587 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base) |
9588 | { | |
9589 | struct drm_device *dev = crtc->dev; | |
9590 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9591 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
dc41c154 | 9592 | uint32_t cntl = 0, size = 0; |
560b85bb | 9593 | |
dc41c154 | 9594 | if (base) { |
3dd512fb MR |
9595 | unsigned int width = intel_crtc->base.cursor->state->crtc_w; |
9596 | unsigned int height = intel_crtc->base.cursor->state->crtc_h; | |
dc41c154 VS |
9597 | unsigned int stride = roundup_pow_of_two(width) * 4; |
9598 | ||
9599 | switch (stride) { | |
9600 | default: | |
9601 | WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n", | |
9602 | width, stride); | |
9603 | stride = 256; | |
9604 | /* fallthrough */ | |
9605 | case 256: | |
9606 | case 512: | |
9607 | case 1024: | |
9608 | case 2048: | |
9609 | break; | |
4b0e333e CW |
9610 | } |
9611 | ||
dc41c154 VS |
9612 | cntl |= CURSOR_ENABLE | |
9613 | CURSOR_GAMMA_ENABLE | | |
9614 | CURSOR_FORMAT_ARGB | | |
9615 | CURSOR_STRIDE(stride); | |
9616 | ||
9617 | size = (height << 12) | width; | |
4b0e333e | 9618 | } |
560b85bb | 9619 | |
dc41c154 VS |
9620 | if (intel_crtc->cursor_cntl != 0 && |
9621 | (intel_crtc->cursor_base != base || | |
9622 | intel_crtc->cursor_size != size || | |
9623 | intel_crtc->cursor_cntl != cntl)) { | |
9624 | /* On these chipsets we can only modify the base/size/stride | |
9625 | * whilst the cursor is disabled. | |
9626 | */ | |
9627 | I915_WRITE(_CURACNTR, 0); | |
4b0e333e | 9628 | POSTING_READ(_CURACNTR); |
dc41c154 | 9629 | intel_crtc->cursor_cntl = 0; |
4b0e333e | 9630 | } |
560b85bb | 9631 | |
99d1f387 | 9632 | if (intel_crtc->cursor_base != base) { |
9db4a9c7 | 9633 | I915_WRITE(_CURABASE, base); |
99d1f387 VS |
9634 | intel_crtc->cursor_base = base; |
9635 | } | |
4726e0b0 | 9636 | |
dc41c154 VS |
9637 | if (intel_crtc->cursor_size != size) { |
9638 | I915_WRITE(CURSIZE, size); | |
9639 | intel_crtc->cursor_size = size; | |
4b0e333e | 9640 | } |
560b85bb | 9641 | |
4b0e333e | 9642 | if (intel_crtc->cursor_cntl != cntl) { |
4b0e333e CW |
9643 | I915_WRITE(_CURACNTR, cntl); |
9644 | POSTING_READ(_CURACNTR); | |
4b0e333e | 9645 | intel_crtc->cursor_cntl = cntl; |
560b85bb | 9646 | } |
560b85bb CW |
9647 | } |
9648 | ||
560b85bb | 9649 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base) |
65a21cd6 JB |
9650 | { |
9651 | struct drm_device *dev = crtc->dev; | |
9652 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9653 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
9654 | int pipe = intel_crtc->pipe; | |
4b0e333e CW |
9655 | uint32_t cntl; |
9656 | ||
9657 | cntl = 0; | |
9658 | if (base) { | |
9659 | cntl = MCURSOR_GAMMA_ENABLE; | |
3dd512fb | 9660 | switch (intel_crtc->base.cursor->state->crtc_w) { |
4726e0b0 SK |
9661 | case 64: |
9662 | cntl |= CURSOR_MODE_64_ARGB_AX; | |
9663 | break; | |
9664 | case 128: | |
9665 | cntl |= CURSOR_MODE_128_ARGB_AX; | |
9666 | break; | |
9667 | case 256: | |
9668 | cntl |= CURSOR_MODE_256_ARGB_AX; | |
9669 | break; | |
9670 | default: | |
3dd512fb | 9671 | MISSING_CASE(intel_crtc->base.cursor->state->crtc_w); |
4726e0b0 | 9672 | return; |
65a21cd6 | 9673 | } |
4b0e333e | 9674 | cntl |= pipe << 28; /* Connect to correct pipe */ |
47bf17a7 VS |
9675 | |
9676 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
9677 | cntl |= CURSOR_PIPE_CSC_ENABLE; | |
4b0e333e | 9678 | } |
65a21cd6 | 9679 | |
8e7d688b | 9680 | if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) |
4398ad45 VS |
9681 | cntl |= CURSOR_ROTATE_180; |
9682 | ||
4b0e333e CW |
9683 | if (intel_crtc->cursor_cntl != cntl) { |
9684 | I915_WRITE(CURCNTR(pipe), cntl); | |
9685 | POSTING_READ(CURCNTR(pipe)); | |
9686 | intel_crtc->cursor_cntl = cntl; | |
65a21cd6 | 9687 | } |
4b0e333e | 9688 | |
65a21cd6 | 9689 | /* and commit changes on next vblank */ |
5efb3e28 VS |
9690 | I915_WRITE(CURBASE(pipe), base); |
9691 | POSTING_READ(CURBASE(pipe)); | |
99d1f387 VS |
9692 | |
9693 | intel_crtc->cursor_base = base; | |
65a21cd6 JB |
9694 | } |
9695 | ||
cda4b7d3 | 9696 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
6b383a7f CW |
9697 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, |
9698 | bool on) | |
cda4b7d3 CW |
9699 | { |
9700 | struct drm_device *dev = crtc->dev; | |
9701 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9702 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
9703 | int pipe = intel_crtc->pipe; | |
3d7d6510 MR |
9704 | int x = crtc->cursor_x; |
9705 | int y = crtc->cursor_y; | |
d6e4db15 | 9706 | u32 base = 0, pos = 0; |
cda4b7d3 | 9707 | |
d6e4db15 | 9708 | if (on) |
cda4b7d3 | 9709 | base = intel_crtc->cursor_addr; |
cda4b7d3 | 9710 | |
6e3c9717 | 9711 | if (x >= intel_crtc->config->pipe_src_w) |
d6e4db15 VS |
9712 | base = 0; |
9713 | ||
6e3c9717 | 9714 | if (y >= intel_crtc->config->pipe_src_h) |
cda4b7d3 CW |
9715 | base = 0; |
9716 | ||
9717 | if (x < 0) { | |
3dd512fb | 9718 | if (x + intel_crtc->base.cursor->state->crtc_w <= 0) |
cda4b7d3 CW |
9719 | base = 0; |
9720 | ||
9721 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; | |
9722 | x = -x; | |
9723 | } | |
9724 | pos |= x << CURSOR_X_SHIFT; | |
9725 | ||
9726 | if (y < 0) { | |
3dd512fb | 9727 | if (y + intel_crtc->base.cursor->state->crtc_h <= 0) |
cda4b7d3 CW |
9728 | base = 0; |
9729 | ||
9730 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; | |
9731 | y = -y; | |
9732 | } | |
9733 | pos |= y << CURSOR_Y_SHIFT; | |
9734 | ||
4b0e333e | 9735 | if (base == 0 && intel_crtc->cursor_base == 0) |
cda4b7d3 CW |
9736 | return; |
9737 | ||
5efb3e28 VS |
9738 | I915_WRITE(CURPOS(pipe), pos); |
9739 | ||
4398ad45 VS |
9740 | /* ILK+ do this automagically */ |
9741 | if (HAS_GMCH_DISPLAY(dev) && | |
8e7d688b | 9742 | crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) { |
3dd512fb MR |
9743 | base += (intel_crtc->base.cursor->state->crtc_h * |
9744 | intel_crtc->base.cursor->state->crtc_w - 1) * 4; | |
4398ad45 VS |
9745 | } |
9746 | ||
8ac54669 | 9747 | if (IS_845G(dev) || IS_I865G(dev)) |
5efb3e28 VS |
9748 | i845_update_cursor(crtc, base); |
9749 | else | |
9750 | i9xx_update_cursor(crtc, base); | |
cda4b7d3 CW |
9751 | } |
9752 | ||
dc41c154 VS |
9753 | static bool cursor_size_ok(struct drm_device *dev, |
9754 | uint32_t width, uint32_t height) | |
9755 | { | |
9756 | if (width == 0 || height == 0) | |
9757 | return false; | |
9758 | ||
9759 | /* | |
9760 | * 845g/865g are special in that they are only limited by | |
9761 | * the width of their cursors, the height is arbitrary up to | |
9762 | * the precision of the register. Everything else requires | |
9763 | * square cursors, limited to a few power-of-two sizes. | |
9764 | */ | |
9765 | if (IS_845G(dev) || IS_I865G(dev)) { | |
9766 | if ((width & 63) != 0) | |
9767 | return false; | |
9768 | ||
9769 | if (width > (IS_845G(dev) ? 64 : 512)) | |
9770 | return false; | |
9771 | ||
9772 | if (height > 1023) | |
9773 | return false; | |
9774 | } else { | |
9775 | switch (width | height) { | |
9776 | case 256: | |
9777 | case 128: | |
9778 | if (IS_GEN2(dev)) | |
9779 | return false; | |
9780 | case 64: | |
9781 | break; | |
9782 | default: | |
9783 | return false; | |
9784 | } | |
9785 | } | |
9786 | ||
9787 | return true; | |
9788 | } | |
9789 | ||
79e53945 | 9790 | static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
7203425a | 9791 | u16 *blue, uint32_t start, uint32_t size) |
79e53945 | 9792 | { |
7203425a | 9793 | int end = (start + size > 256) ? 256 : start + size, i; |
79e53945 | 9794 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 9795 | |
7203425a | 9796 | for (i = start; i < end; i++) { |
79e53945 JB |
9797 | intel_crtc->lut_r[i] = red[i] >> 8; |
9798 | intel_crtc->lut_g[i] = green[i] >> 8; | |
9799 | intel_crtc->lut_b[i] = blue[i] >> 8; | |
9800 | } | |
9801 | ||
9802 | intel_crtc_load_lut(crtc); | |
9803 | } | |
9804 | ||
79e53945 JB |
9805 | /* VESA 640x480x72Hz mode to set on the pipe */ |
9806 | static struct drm_display_mode load_detect_mode = { | |
9807 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, | |
9808 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), | |
9809 | }; | |
9810 | ||
a8bb6818 DV |
9811 | struct drm_framebuffer * |
9812 | __intel_framebuffer_create(struct drm_device *dev, | |
9813 | struct drm_mode_fb_cmd2 *mode_cmd, | |
9814 | struct drm_i915_gem_object *obj) | |
d2dff872 CW |
9815 | { |
9816 | struct intel_framebuffer *intel_fb; | |
9817 | int ret; | |
9818 | ||
9819 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); | |
9820 | if (!intel_fb) { | |
6ccb81f2 | 9821 | drm_gem_object_unreference(&obj->base); |
d2dff872 CW |
9822 | return ERR_PTR(-ENOMEM); |
9823 | } | |
9824 | ||
9825 | ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); | |
dd4916c5 DV |
9826 | if (ret) |
9827 | goto err; | |
d2dff872 CW |
9828 | |
9829 | return &intel_fb->base; | |
dd4916c5 | 9830 | err: |
6ccb81f2 | 9831 | drm_gem_object_unreference(&obj->base); |
dd4916c5 DV |
9832 | kfree(intel_fb); |
9833 | ||
9834 | return ERR_PTR(ret); | |
d2dff872 CW |
9835 | } |
9836 | ||
b5ea642a | 9837 | static struct drm_framebuffer * |
a8bb6818 DV |
9838 | intel_framebuffer_create(struct drm_device *dev, |
9839 | struct drm_mode_fb_cmd2 *mode_cmd, | |
9840 | struct drm_i915_gem_object *obj) | |
9841 | { | |
9842 | struct drm_framebuffer *fb; | |
9843 | int ret; | |
9844 | ||
9845 | ret = i915_mutex_lock_interruptible(dev); | |
9846 | if (ret) | |
9847 | return ERR_PTR(ret); | |
9848 | fb = __intel_framebuffer_create(dev, mode_cmd, obj); | |
9849 | mutex_unlock(&dev->struct_mutex); | |
9850 | ||
9851 | return fb; | |
9852 | } | |
9853 | ||
d2dff872 CW |
9854 | static u32 |
9855 | intel_framebuffer_pitch_for_width(int width, int bpp) | |
9856 | { | |
9857 | u32 pitch = DIV_ROUND_UP(width * bpp, 8); | |
9858 | return ALIGN(pitch, 64); | |
9859 | } | |
9860 | ||
9861 | static u32 | |
9862 | intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) | |
9863 | { | |
9864 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); | |
1267a26b | 9865 | return PAGE_ALIGN(pitch * mode->vdisplay); |
d2dff872 CW |
9866 | } |
9867 | ||
9868 | static struct drm_framebuffer * | |
9869 | intel_framebuffer_create_for_mode(struct drm_device *dev, | |
9870 | struct drm_display_mode *mode, | |
9871 | int depth, int bpp) | |
9872 | { | |
9873 | struct drm_i915_gem_object *obj; | |
0fed39bd | 9874 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; |
d2dff872 CW |
9875 | |
9876 | obj = i915_gem_alloc_object(dev, | |
9877 | intel_framebuffer_size_for_mode(mode, bpp)); | |
9878 | if (obj == NULL) | |
9879 | return ERR_PTR(-ENOMEM); | |
9880 | ||
9881 | mode_cmd.width = mode->hdisplay; | |
9882 | mode_cmd.height = mode->vdisplay; | |
308e5bcb JB |
9883 | mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, |
9884 | bpp); | |
5ca0c34a | 9885 | mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); |
d2dff872 CW |
9886 | |
9887 | return intel_framebuffer_create(dev, &mode_cmd, obj); | |
9888 | } | |
9889 | ||
9890 | static struct drm_framebuffer * | |
9891 | mode_fits_in_fbdev(struct drm_device *dev, | |
9892 | struct drm_display_mode *mode) | |
9893 | { | |
4520f53a | 9894 | #ifdef CONFIG_DRM_I915_FBDEV |
d2dff872 CW |
9895 | struct drm_i915_private *dev_priv = dev->dev_private; |
9896 | struct drm_i915_gem_object *obj; | |
9897 | struct drm_framebuffer *fb; | |
9898 | ||
4c0e5528 | 9899 | if (!dev_priv->fbdev) |
d2dff872 CW |
9900 | return NULL; |
9901 | ||
4c0e5528 | 9902 | if (!dev_priv->fbdev->fb) |
d2dff872 CW |
9903 | return NULL; |
9904 | ||
4c0e5528 DV |
9905 | obj = dev_priv->fbdev->fb->obj; |
9906 | BUG_ON(!obj); | |
9907 | ||
8bcd4553 | 9908 | fb = &dev_priv->fbdev->fb->base; |
01f2c773 VS |
9909 | if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, |
9910 | fb->bits_per_pixel)) | |
d2dff872 CW |
9911 | return NULL; |
9912 | ||
01f2c773 | 9913 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
d2dff872 CW |
9914 | return NULL; |
9915 | ||
9916 | return fb; | |
4520f53a DV |
9917 | #else |
9918 | return NULL; | |
9919 | #endif | |
d2dff872 CW |
9920 | } |
9921 | ||
d3a40d1b ACO |
9922 | static int intel_modeset_setup_plane_state(struct drm_atomic_state *state, |
9923 | struct drm_crtc *crtc, | |
9924 | struct drm_display_mode *mode, | |
9925 | struct drm_framebuffer *fb, | |
9926 | int x, int y) | |
9927 | { | |
9928 | struct drm_plane_state *plane_state; | |
9929 | int hdisplay, vdisplay; | |
9930 | int ret; | |
9931 | ||
9932 | plane_state = drm_atomic_get_plane_state(state, crtc->primary); | |
9933 | if (IS_ERR(plane_state)) | |
9934 | return PTR_ERR(plane_state); | |
9935 | ||
9936 | if (mode) | |
9937 | drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay); | |
9938 | else | |
9939 | hdisplay = vdisplay = 0; | |
9940 | ||
9941 | ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL); | |
9942 | if (ret) | |
9943 | return ret; | |
9944 | drm_atomic_set_fb_for_plane(plane_state, fb); | |
9945 | plane_state->crtc_x = 0; | |
9946 | plane_state->crtc_y = 0; | |
9947 | plane_state->crtc_w = hdisplay; | |
9948 | plane_state->crtc_h = vdisplay; | |
9949 | plane_state->src_x = x << 16; | |
9950 | plane_state->src_y = y << 16; | |
9951 | plane_state->src_w = hdisplay << 16; | |
9952 | plane_state->src_h = vdisplay << 16; | |
9953 | ||
9954 | return 0; | |
9955 | } | |
9956 | ||
d2434ab7 | 9957 | bool intel_get_load_detect_pipe(struct drm_connector *connector, |
7173188d | 9958 | struct drm_display_mode *mode, |
51fd371b RC |
9959 | struct intel_load_detect_pipe *old, |
9960 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 JB |
9961 | { |
9962 | struct intel_crtc *intel_crtc; | |
d2434ab7 DV |
9963 | struct intel_encoder *intel_encoder = |
9964 | intel_attached_encoder(connector); | |
79e53945 | 9965 | struct drm_crtc *possible_crtc; |
4ef69c7a | 9966 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
9967 | struct drm_crtc *crtc = NULL; |
9968 | struct drm_device *dev = encoder->dev; | |
94352cf9 | 9969 | struct drm_framebuffer *fb; |
51fd371b | 9970 | struct drm_mode_config *config = &dev->mode_config; |
83a57153 | 9971 | struct drm_atomic_state *state = NULL; |
944b0c76 | 9972 | struct drm_connector_state *connector_state; |
4be07317 | 9973 | struct intel_crtc_state *crtc_state; |
51fd371b | 9974 | int ret, i = -1; |
79e53945 | 9975 | |
d2dff872 | 9976 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 9977 | connector->base.id, connector->name, |
8e329a03 | 9978 | encoder->base.id, encoder->name); |
d2dff872 | 9979 | |
51fd371b RC |
9980 | retry: |
9981 | ret = drm_modeset_lock(&config->connection_mutex, ctx); | |
9982 | if (ret) | |
9983 | goto fail_unlock; | |
6e9f798d | 9984 | |
79e53945 JB |
9985 | /* |
9986 | * Algorithm gets a little messy: | |
7a5e4805 | 9987 | * |
79e53945 JB |
9988 | * - if the connector already has an assigned crtc, use it (but make |
9989 | * sure it's on first) | |
7a5e4805 | 9990 | * |
79e53945 JB |
9991 | * - try to find the first unused crtc that can drive this connector, |
9992 | * and use that if we find one | |
79e53945 JB |
9993 | */ |
9994 | ||
9995 | /* See if we already have a CRTC for this connector */ | |
9996 | if (encoder->crtc) { | |
9997 | crtc = encoder->crtc; | |
8261b191 | 9998 | |
51fd371b | 9999 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
4d02e2de DV |
10000 | if (ret) |
10001 | goto fail_unlock; | |
10002 | ret = drm_modeset_lock(&crtc->primary->mutex, ctx); | |
51fd371b RC |
10003 | if (ret) |
10004 | goto fail_unlock; | |
7b24056b | 10005 | |
24218aac | 10006 | old->dpms_mode = connector->dpms; |
8261b191 CW |
10007 | old->load_detect_temp = false; |
10008 | ||
10009 | /* Make sure the crtc and connector are running */ | |
24218aac DV |
10010 | if (connector->dpms != DRM_MODE_DPMS_ON) |
10011 | connector->funcs->dpms(connector, DRM_MODE_DPMS_ON); | |
8261b191 | 10012 | |
7173188d | 10013 | return true; |
79e53945 JB |
10014 | } |
10015 | ||
10016 | /* Find an unused one (if possible) */ | |
70e1e0ec | 10017 | for_each_crtc(dev, possible_crtc) { |
79e53945 JB |
10018 | i++; |
10019 | if (!(encoder->possible_crtcs & (1 << i))) | |
10020 | continue; | |
83d65738 | 10021 | if (possible_crtc->state->enable) |
a459249c VS |
10022 | continue; |
10023 | /* This can occur when applying the pipe A quirk on resume. */ | |
10024 | if (to_intel_crtc(possible_crtc)->new_enabled) | |
10025 | continue; | |
10026 | ||
10027 | crtc = possible_crtc; | |
10028 | break; | |
79e53945 JB |
10029 | } |
10030 | ||
10031 | /* | |
10032 | * If we didn't find an unused CRTC, don't use any. | |
10033 | */ | |
10034 | if (!crtc) { | |
7173188d | 10035 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
51fd371b | 10036 | goto fail_unlock; |
79e53945 JB |
10037 | } |
10038 | ||
51fd371b RC |
10039 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
10040 | if (ret) | |
4d02e2de DV |
10041 | goto fail_unlock; |
10042 | ret = drm_modeset_lock(&crtc->primary->mutex, ctx); | |
10043 | if (ret) | |
51fd371b | 10044 | goto fail_unlock; |
fc303101 DV |
10045 | intel_encoder->new_crtc = to_intel_crtc(crtc); |
10046 | to_intel_connector(connector)->new_encoder = intel_encoder; | |
79e53945 JB |
10047 | |
10048 | intel_crtc = to_intel_crtc(crtc); | |
412b61d8 | 10049 | intel_crtc->new_enabled = true; |
24218aac | 10050 | old->dpms_mode = connector->dpms; |
8261b191 | 10051 | old->load_detect_temp = true; |
d2dff872 | 10052 | old->release_fb = NULL; |
79e53945 | 10053 | |
83a57153 ACO |
10054 | state = drm_atomic_state_alloc(dev); |
10055 | if (!state) | |
10056 | return false; | |
10057 | ||
10058 | state->acquire_ctx = ctx; | |
10059 | ||
944b0c76 ACO |
10060 | connector_state = drm_atomic_get_connector_state(state, connector); |
10061 | if (IS_ERR(connector_state)) { | |
10062 | ret = PTR_ERR(connector_state); | |
10063 | goto fail; | |
10064 | } | |
10065 | ||
10066 | connector_state->crtc = crtc; | |
10067 | connector_state->best_encoder = &intel_encoder->base; | |
10068 | ||
4be07317 ACO |
10069 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); |
10070 | if (IS_ERR(crtc_state)) { | |
10071 | ret = PTR_ERR(crtc_state); | |
10072 | goto fail; | |
10073 | } | |
10074 | ||
49d6fa21 | 10075 | crtc_state->base.active = crtc_state->base.enable = true; |
4be07317 | 10076 | |
6492711d CW |
10077 | if (!mode) |
10078 | mode = &load_detect_mode; | |
79e53945 | 10079 | |
d2dff872 CW |
10080 | /* We need a framebuffer large enough to accommodate all accesses |
10081 | * that the plane may generate whilst we perform load detection. | |
10082 | * We can not rely on the fbcon either being present (we get called | |
10083 | * during its initialisation to detect all boot displays, or it may | |
10084 | * not even exist) or that it is large enough to satisfy the | |
10085 | * requested mode. | |
10086 | */ | |
94352cf9 DV |
10087 | fb = mode_fits_in_fbdev(dev, mode); |
10088 | if (fb == NULL) { | |
d2dff872 | 10089 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); |
94352cf9 DV |
10090 | fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); |
10091 | old->release_fb = fb; | |
d2dff872 CW |
10092 | } else |
10093 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); | |
94352cf9 | 10094 | if (IS_ERR(fb)) { |
d2dff872 | 10095 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); |
412b61d8 | 10096 | goto fail; |
79e53945 | 10097 | } |
79e53945 | 10098 | |
d3a40d1b ACO |
10099 | ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0); |
10100 | if (ret) | |
10101 | goto fail; | |
10102 | ||
8c7b5ccb ACO |
10103 | drm_mode_copy(&crtc_state->base.mode, mode); |
10104 | ||
10105 | if (intel_set_mode(crtc, state)) { | |
6492711d | 10106 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
d2dff872 CW |
10107 | if (old->release_fb) |
10108 | old->release_fb->funcs->destroy(old->release_fb); | |
412b61d8 | 10109 | goto fail; |
79e53945 | 10110 | } |
9128b040 | 10111 | crtc->primary->crtc = crtc; |
7173188d | 10112 | |
79e53945 | 10113 | /* let the connector get through one full cycle before testing */ |
9d0498a2 | 10114 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
7173188d | 10115 | return true; |
412b61d8 VS |
10116 | |
10117 | fail: | |
83d65738 | 10118 | intel_crtc->new_enabled = crtc->state->enable; |
51fd371b | 10119 | fail_unlock: |
e5d958ef ACO |
10120 | drm_atomic_state_free(state); |
10121 | state = NULL; | |
83a57153 | 10122 | |
51fd371b RC |
10123 | if (ret == -EDEADLK) { |
10124 | drm_modeset_backoff(ctx); | |
10125 | goto retry; | |
10126 | } | |
10127 | ||
412b61d8 | 10128 | return false; |
79e53945 JB |
10129 | } |
10130 | ||
d2434ab7 | 10131 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
49172fee ACO |
10132 | struct intel_load_detect_pipe *old, |
10133 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 | 10134 | { |
83a57153 | 10135 | struct drm_device *dev = connector->dev; |
d2434ab7 DV |
10136 | struct intel_encoder *intel_encoder = |
10137 | intel_attached_encoder(connector); | |
4ef69c7a | 10138 | struct drm_encoder *encoder = &intel_encoder->base; |
7b24056b | 10139 | struct drm_crtc *crtc = encoder->crtc; |
412b61d8 | 10140 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
83a57153 | 10141 | struct drm_atomic_state *state; |
944b0c76 | 10142 | struct drm_connector_state *connector_state; |
4be07317 | 10143 | struct intel_crtc_state *crtc_state; |
d3a40d1b | 10144 | int ret; |
79e53945 | 10145 | |
d2dff872 | 10146 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 10147 | connector->base.id, connector->name, |
8e329a03 | 10148 | encoder->base.id, encoder->name); |
d2dff872 | 10149 | |
8261b191 | 10150 | if (old->load_detect_temp) { |
83a57153 | 10151 | state = drm_atomic_state_alloc(dev); |
944b0c76 ACO |
10152 | if (!state) |
10153 | goto fail; | |
83a57153 ACO |
10154 | |
10155 | state->acquire_ctx = ctx; | |
10156 | ||
944b0c76 ACO |
10157 | connector_state = drm_atomic_get_connector_state(state, connector); |
10158 | if (IS_ERR(connector_state)) | |
10159 | goto fail; | |
10160 | ||
4be07317 ACO |
10161 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); |
10162 | if (IS_ERR(crtc_state)) | |
10163 | goto fail; | |
10164 | ||
fc303101 DV |
10165 | to_intel_connector(connector)->new_encoder = NULL; |
10166 | intel_encoder->new_crtc = NULL; | |
412b61d8 | 10167 | intel_crtc->new_enabled = false; |
944b0c76 ACO |
10168 | |
10169 | connector_state->best_encoder = NULL; | |
10170 | connector_state->crtc = NULL; | |
10171 | ||
49d6fa21 | 10172 | crtc_state->base.enable = crtc_state->base.active = false; |
4be07317 | 10173 | |
d3a40d1b ACO |
10174 | ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL, |
10175 | 0, 0); | |
10176 | if (ret) | |
10177 | goto fail; | |
10178 | ||
2bfb4627 ACO |
10179 | ret = intel_set_mode(crtc, state); |
10180 | if (ret) | |
10181 | goto fail; | |
d2dff872 | 10182 | |
36206361 DV |
10183 | if (old->release_fb) { |
10184 | drm_framebuffer_unregister_private(old->release_fb); | |
10185 | drm_framebuffer_unreference(old->release_fb); | |
10186 | } | |
d2dff872 | 10187 | |
0622a53c | 10188 | return; |
79e53945 JB |
10189 | } |
10190 | ||
c751ce4f | 10191 | /* Switch crtc and encoder back off if necessary */ |
24218aac DV |
10192 | if (old->dpms_mode != DRM_MODE_DPMS_ON) |
10193 | connector->funcs->dpms(connector, old->dpms_mode); | |
944b0c76 ACO |
10194 | |
10195 | return; | |
10196 | fail: | |
10197 | DRM_DEBUG_KMS("Couldn't release load detect pipe.\n"); | |
10198 | drm_atomic_state_free(state); | |
79e53945 JB |
10199 | } |
10200 | ||
da4a1efa | 10201 | static int i9xx_pll_refclk(struct drm_device *dev, |
5cec258b | 10202 | const struct intel_crtc_state *pipe_config) |
da4a1efa VS |
10203 | { |
10204 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10205 | u32 dpll = pipe_config->dpll_hw_state.dpll; | |
10206 | ||
10207 | if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) | |
e91e941b | 10208 | return dev_priv->vbt.lvds_ssc_freq; |
da4a1efa VS |
10209 | else if (HAS_PCH_SPLIT(dev)) |
10210 | return 120000; | |
10211 | else if (!IS_GEN2(dev)) | |
10212 | return 96000; | |
10213 | else | |
10214 | return 48000; | |
10215 | } | |
10216 | ||
79e53945 | 10217 | /* Returns the clock of the currently programmed mode of the given pipe. */ |
f1f644dc | 10218 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 10219 | struct intel_crtc_state *pipe_config) |
79e53945 | 10220 | { |
f1f644dc | 10221 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 10222 | struct drm_i915_private *dev_priv = dev->dev_private; |
f1f644dc | 10223 | int pipe = pipe_config->cpu_transcoder; |
293623f7 | 10224 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
79e53945 JB |
10225 | u32 fp; |
10226 | intel_clock_t clock; | |
da4a1efa | 10227 | int refclk = i9xx_pll_refclk(dev, pipe_config); |
79e53945 JB |
10228 | |
10229 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) | |
293623f7 | 10230 | fp = pipe_config->dpll_hw_state.fp0; |
79e53945 | 10231 | else |
293623f7 | 10232 | fp = pipe_config->dpll_hw_state.fp1; |
79e53945 JB |
10233 | |
10234 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; | |
f2b115e6 AJ |
10235 | if (IS_PINEVIEW(dev)) { |
10236 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; | |
10237 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
2177832f SL |
10238 | } else { |
10239 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; | |
10240 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
10241 | } | |
10242 | ||
a6c45cf0 | 10243 | if (!IS_GEN2(dev)) { |
f2b115e6 AJ |
10244 | if (IS_PINEVIEW(dev)) |
10245 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> | |
10246 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); | |
2177832f SL |
10247 | else |
10248 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> | |
79e53945 JB |
10249 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
10250 | ||
10251 | switch (dpll & DPLL_MODE_MASK) { | |
10252 | case DPLLB_MODE_DAC_SERIAL: | |
10253 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? | |
10254 | 5 : 10; | |
10255 | break; | |
10256 | case DPLLB_MODE_LVDS: | |
10257 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? | |
10258 | 7 : 14; | |
10259 | break; | |
10260 | default: | |
28c97730 | 10261 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
79e53945 | 10262 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
f1f644dc | 10263 | return; |
79e53945 JB |
10264 | } |
10265 | ||
ac58c3f0 | 10266 | if (IS_PINEVIEW(dev)) |
da4a1efa | 10267 | pineview_clock(refclk, &clock); |
ac58c3f0 | 10268 | else |
da4a1efa | 10269 | i9xx_clock(refclk, &clock); |
79e53945 | 10270 | } else { |
0fb58223 | 10271 | u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS); |
b1c560d1 | 10272 | bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN); |
79e53945 JB |
10273 | |
10274 | if (is_lvds) { | |
10275 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> | |
10276 | DPLL_FPA01_P1_POST_DIV_SHIFT); | |
b1c560d1 VS |
10277 | |
10278 | if (lvds & LVDS_CLKB_POWER_UP) | |
10279 | clock.p2 = 7; | |
10280 | else | |
10281 | clock.p2 = 14; | |
79e53945 JB |
10282 | } else { |
10283 | if (dpll & PLL_P1_DIVIDE_BY_TWO) | |
10284 | clock.p1 = 2; | |
10285 | else { | |
10286 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> | |
10287 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; | |
10288 | } | |
10289 | if (dpll & PLL_P2_DIVIDE_BY_4) | |
10290 | clock.p2 = 4; | |
10291 | else | |
10292 | clock.p2 = 2; | |
79e53945 | 10293 | } |
da4a1efa VS |
10294 | |
10295 | i9xx_clock(refclk, &clock); | |
79e53945 JB |
10296 | } |
10297 | ||
18442d08 VS |
10298 | /* |
10299 | * This value includes pixel_multiplier. We will use | |
241bfc38 | 10300 | * port_clock to compute adjusted_mode.crtc_clock in the |
18442d08 VS |
10301 | * encoder's get_config() function. |
10302 | */ | |
10303 | pipe_config->port_clock = clock.dot; | |
f1f644dc JB |
10304 | } |
10305 | ||
6878da05 VS |
10306 | int intel_dotclock_calculate(int link_freq, |
10307 | const struct intel_link_m_n *m_n) | |
f1f644dc | 10308 | { |
f1f644dc JB |
10309 | /* |
10310 | * The calculation for the data clock is: | |
1041a02f | 10311 | * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp |
f1f644dc | 10312 | * But we want to avoid losing precison if possible, so: |
1041a02f | 10313 | * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) |
f1f644dc JB |
10314 | * |
10315 | * and the link clock is simpler: | |
1041a02f | 10316 | * link_clock = (m * link_clock) / n |
f1f644dc JB |
10317 | */ |
10318 | ||
6878da05 VS |
10319 | if (!m_n->link_n) |
10320 | return 0; | |
f1f644dc | 10321 | |
6878da05 VS |
10322 | return div_u64((u64)m_n->link_m * link_freq, m_n->link_n); |
10323 | } | |
f1f644dc | 10324 | |
18442d08 | 10325 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 10326 | struct intel_crtc_state *pipe_config) |
6878da05 VS |
10327 | { |
10328 | struct drm_device *dev = crtc->base.dev; | |
79e53945 | 10329 | |
18442d08 VS |
10330 | /* read out port_clock from the DPLL */ |
10331 | i9xx_crtc_clock_get(crtc, pipe_config); | |
f1f644dc | 10332 | |
f1f644dc | 10333 | /* |
18442d08 | 10334 | * This value does not include pixel_multiplier. |
241bfc38 | 10335 | * We will check that port_clock and adjusted_mode.crtc_clock |
18442d08 VS |
10336 | * agree once we know their relationship in the encoder's |
10337 | * get_config() function. | |
79e53945 | 10338 | */ |
2d112de7 | 10339 | pipe_config->base.adjusted_mode.crtc_clock = |
18442d08 VS |
10340 | intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000, |
10341 | &pipe_config->fdi_m_n); | |
79e53945 JB |
10342 | } |
10343 | ||
10344 | /** Returns the currently programmed mode of the given pipe. */ | |
10345 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
10346 | struct drm_crtc *crtc) | |
10347 | { | |
548f245b | 10348 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 10349 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6e3c9717 | 10350 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
79e53945 | 10351 | struct drm_display_mode *mode; |
5cec258b | 10352 | struct intel_crtc_state pipe_config; |
fe2b8f9d PZ |
10353 | int htot = I915_READ(HTOTAL(cpu_transcoder)); |
10354 | int hsync = I915_READ(HSYNC(cpu_transcoder)); | |
10355 | int vtot = I915_READ(VTOTAL(cpu_transcoder)); | |
10356 | int vsync = I915_READ(VSYNC(cpu_transcoder)); | |
293623f7 | 10357 | enum pipe pipe = intel_crtc->pipe; |
79e53945 JB |
10358 | |
10359 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); | |
10360 | if (!mode) | |
10361 | return NULL; | |
10362 | ||
f1f644dc JB |
10363 | /* |
10364 | * Construct a pipe_config sufficient for getting the clock info | |
10365 | * back out of crtc_clock_get. | |
10366 | * | |
10367 | * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need | |
10368 | * to use a real value here instead. | |
10369 | */ | |
293623f7 | 10370 | pipe_config.cpu_transcoder = (enum transcoder) pipe; |
f1f644dc | 10371 | pipe_config.pixel_multiplier = 1; |
293623f7 VS |
10372 | pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe)); |
10373 | pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe)); | |
10374 | pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe)); | |
f1f644dc JB |
10375 | i9xx_crtc_clock_get(intel_crtc, &pipe_config); |
10376 | ||
773ae034 | 10377 | mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier; |
79e53945 JB |
10378 | mode->hdisplay = (htot & 0xffff) + 1; |
10379 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; | |
10380 | mode->hsync_start = (hsync & 0xffff) + 1; | |
10381 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; | |
10382 | mode->vdisplay = (vtot & 0xffff) + 1; | |
10383 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; | |
10384 | mode->vsync_start = (vsync & 0xffff) + 1; | |
10385 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; | |
10386 | ||
10387 | drm_mode_set_name(mode); | |
79e53945 JB |
10388 | |
10389 | return mode; | |
10390 | } | |
10391 | ||
652c393a JB |
10392 | static void intel_decrease_pllclock(struct drm_crtc *crtc) |
10393 | { | |
10394 | struct drm_device *dev = crtc->dev; | |
fbee40df | 10395 | struct drm_i915_private *dev_priv = dev->dev_private; |
652c393a | 10396 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
652c393a | 10397 | |
baff296c | 10398 | if (!HAS_GMCH_DISPLAY(dev)) |
652c393a JB |
10399 | return; |
10400 | ||
10401 | if (!dev_priv->lvds_downclock_avail) | |
10402 | return; | |
10403 | ||
10404 | /* | |
10405 | * Since this is called by a timer, we should never get here in | |
10406 | * the manual case. | |
10407 | */ | |
10408 | if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) { | |
dc257cf1 DV |
10409 | int pipe = intel_crtc->pipe; |
10410 | int dpll_reg = DPLL(pipe); | |
10411 | int dpll; | |
f6e5b160 | 10412 | |
44d98a61 | 10413 | DRM_DEBUG_DRIVER("downclocking LVDS\n"); |
652c393a | 10414 | |
8ac5a6d5 | 10415 | assert_panel_unlocked(dev_priv, pipe); |
652c393a | 10416 | |
dc257cf1 | 10417 | dpll = I915_READ(dpll_reg); |
652c393a JB |
10418 | dpll |= DISPLAY_RATE_SELECT_FPA1; |
10419 | I915_WRITE(dpll_reg, dpll); | |
9d0498a2 | 10420 | intel_wait_for_vblank(dev, pipe); |
652c393a JB |
10421 | dpll = I915_READ(dpll_reg); |
10422 | if (!(dpll & DISPLAY_RATE_SELECT_FPA1)) | |
44d98a61 | 10423 | DRM_DEBUG_DRIVER("failed to downclock LVDS!\n"); |
652c393a JB |
10424 | } |
10425 | ||
10426 | } | |
10427 | ||
f047e395 CW |
10428 | void intel_mark_busy(struct drm_device *dev) |
10429 | { | |
c67a470b PZ |
10430 | struct drm_i915_private *dev_priv = dev->dev_private; |
10431 | ||
f62a0076 CW |
10432 | if (dev_priv->mm.busy) |
10433 | return; | |
10434 | ||
43694d69 | 10435 | intel_runtime_pm_get(dev_priv); |
c67a470b | 10436 | i915_update_gfx_val(dev_priv); |
43cf3bf0 CW |
10437 | if (INTEL_INFO(dev)->gen >= 6) |
10438 | gen6_rps_busy(dev_priv); | |
f62a0076 | 10439 | dev_priv->mm.busy = true; |
f047e395 CW |
10440 | } |
10441 | ||
10442 | void intel_mark_idle(struct drm_device *dev) | |
652c393a | 10443 | { |
c67a470b | 10444 | struct drm_i915_private *dev_priv = dev->dev_private; |
652c393a | 10445 | struct drm_crtc *crtc; |
652c393a | 10446 | |
f62a0076 CW |
10447 | if (!dev_priv->mm.busy) |
10448 | return; | |
10449 | ||
10450 | dev_priv->mm.busy = false; | |
10451 | ||
70e1e0ec | 10452 | for_each_crtc(dev, crtc) { |
f4510a27 | 10453 | if (!crtc->primary->fb) |
652c393a JB |
10454 | continue; |
10455 | ||
725a5b54 | 10456 | intel_decrease_pllclock(crtc); |
652c393a | 10457 | } |
b29c19b6 | 10458 | |
3d13ef2e | 10459 | if (INTEL_INFO(dev)->gen >= 6) |
b29c19b6 | 10460 | gen6_rps_idle(dev->dev_private); |
bb4cdd53 | 10461 | |
43694d69 | 10462 | intel_runtime_pm_put(dev_priv); |
652c393a JB |
10463 | } |
10464 | ||
79e53945 JB |
10465 | static void intel_crtc_destroy(struct drm_crtc *crtc) |
10466 | { | |
10467 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
67e77c5a DV |
10468 | struct drm_device *dev = crtc->dev; |
10469 | struct intel_unpin_work *work; | |
67e77c5a | 10470 | |
5e2d7afc | 10471 | spin_lock_irq(&dev->event_lock); |
67e77c5a DV |
10472 | work = intel_crtc->unpin_work; |
10473 | intel_crtc->unpin_work = NULL; | |
5e2d7afc | 10474 | spin_unlock_irq(&dev->event_lock); |
67e77c5a DV |
10475 | |
10476 | if (work) { | |
10477 | cancel_work_sync(&work->work); | |
10478 | kfree(work); | |
10479 | } | |
79e53945 JB |
10480 | |
10481 | drm_crtc_cleanup(crtc); | |
67e77c5a | 10482 | |
79e53945 JB |
10483 | kfree(intel_crtc); |
10484 | } | |
10485 | ||
6b95a207 KH |
10486 | static void intel_unpin_work_fn(struct work_struct *__work) |
10487 | { | |
10488 | struct intel_unpin_work *work = | |
10489 | container_of(__work, struct intel_unpin_work, work); | |
b4a98e57 | 10490 | struct drm_device *dev = work->crtc->dev; |
f99d7069 | 10491 | enum pipe pipe = to_intel_crtc(work->crtc)->pipe; |
6b95a207 | 10492 | |
b4a98e57 | 10493 | mutex_lock(&dev->struct_mutex); |
82bc3b2d | 10494 | intel_unpin_fb_obj(work->old_fb, work->crtc->primary->state); |
05394f39 | 10495 | drm_gem_object_unreference(&work->pending_flip_obj->base); |
d9e86c0e | 10496 | |
7ff0ebcc | 10497 | intel_fbc_update(dev); |
f06cc1b9 JH |
10498 | |
10499 | if (work->flip_queued_req) | |
146d84f0 | 10500 | i915_gem_request_assign(&work->flip_queued_req, NULL); |
b4a98e57 CW |
10501 | mutex_unlock(&dev->struct_mutex); |
10502 | ||
f99d7069 | 10503 | intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe)); |
89ed88ba | 10504 | drm_framebuffer_unreference(work->old_fb); |
f99d7069 | 10505 | |
b4a98e57 CW |
10506 | BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0); |
10507 | atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count); | |
10508 | ||
6b95a207 KH |
10509 | kfree(work); |
10510 | } | |
10511 | ||
1afe3e9d | 10512 | static void do_intel_finish_page_flip(struct drm_device *dev, |
49b14a5c | 10513 | struct drm_crtc *crtc) |
6b95a207 | 10514 | { |
6b95a207 KH |
10515 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
10516 | struct intel_unpin_work *work; | |
6b95a207 KH |
10517 | unsigned long flags; |
10518 | ||
10519 | /* Ignore early vblank irqs */ | |
10520 | if (intel_crtc == NULL) | |
10521 | return; | |
10522 | ||
f326038a DV |
10523 | /* |
10524 | * This is called both by irq handlers and the reset code (to complete | |
10525 | * lost pageflips) so needs the full irqsave spinlocks. | |
10526 | */ | |
6b95a207 KH |
10527 | spin_lock_irqsave(&dev->event_lock, flags); |
10528 | work = intel_crtc->unpin_work; | |
e7d841ca CW |
10529 | |
10530 | /* Ensure we don't miss a work->pending update ... */ | |
10531 | smp_rmb(); | |
10532 | ||
10533 | if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { | |
6b95a207 KH |
10534 | spin_unlock_irqrestore(&dev->event_lock, flags); |
10535 | return; | |
10536 | } | |
10537 | ||
d6bbafa1 | 10538 | page_flip_completed(intel_crtc); |
0af7e4df | 10539 | |
6b95a207 | 10540 | spin_unlock_irqrestore(&dev->event_lock, flags); |
6b95a207 KH |
10541 | } |
10542 | ||
1afe3e9d JB |
10543 | void intel_finish_page_flip(struct drm_device *dev, int pipe) |
10544 | { | |
fbee40df | 10545 | struct drm_i915_private *dev_priv = dev->dev_private; |
1afe3e9d JB |
10546 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
10547 | ||
49b14a5c | 10548 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
10549 | } |
10550 | ||
10551 | void intel_finish_page_flip_plane(struct drm_device *dev, int plane) | |
10552 | { | |
fbee40df | 10553 | struct drm_i915_private *dev_priv = dev->dev_private; |
1afe3e9d JB |
10554 | struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane]; |
10555 | ||
49b14a5c | 10556 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
10557 | } |
10558 | ||
75f7f3ec VS |
10559 | /* Is 'a' after or equal to 'b'? */ |
10560 | static bool g4x_flip_count_after_eq(u32 a, u32 b) | |
10561 | { | |
10562 | return !((a - b) & 0x80000000); | |
10563 | } | |
10564 | ||
10565 | static bool page_flip_finished(struct intel_crtc *crtc) | |
10566 | { | |
10567 | struct drm_device *dev = crtc->base.dev; | |
10568 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10569 | ||
bdfa7542 VS |
10570 | if (i915_reset_in_progress(&dev_priv->gpu_error) || |
10571 | crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) | |
10572 | return true; | |
10573 | ||
75f7f3ec VS |
10574 | /* |
10575 | * The relevant registers doen't exist on pre-ctg. | |
10576 | * As the flip done interrupt doesn't trigger for mmio | |
10577 | * flips on gmch platforms, a flip count check isn't | |
10578 | * really needed there. But since ctg has the registers, | |
10579 | * include it in the check anyway. | |
10580 | */ | |
10581 | if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev)) | |
10582 | return true; | |
10583 | ||
10584 | /* | |
10585 | * A DSPSURFLIVE check isn't enough in case the mmio and CS flips | |
10586 | * used the same base address. In that case the mmio flip might | |
10587 | * have completed, but the CS hasn't even executed the flip yet. | |
10588 | * | |
10589 | * A flip count check isn't enough as the CS might have updated | |
10590 | * the base address just after start of vblank, but before we | |
10591 | * managed to process the interrupt. This means we'd complete the | |
10592 | * CS flip too soon. | |
10593 | * | |
10594 | * Combining both checks should get us a good enough result. It may | |
10595 | * still happen that the CS flip has been executed, but has not | |
10596 | * yet actually completed. But in case the base address is the same | |
10597 | * anyway, we don't really care. | |
10598 | */ | |
10599 | return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) == | |
10600 | crtc->unpin_work->gtt_offset && | |
10601 | g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)), | |
10602 | crtc->unpin_work->flip_count); | |
10603 | } | |
10604 | ||
6b95a207 KH |
10605 | void intel_prepare_page_flip(struct drm_device *dev, int plane) |
10606 | { | |
fbee40df | 10607 | struct drm_i915_private *dev_priv = dev->dev_private; |
6b95a207 KH |
10608 | struct intel_crtc *intel_crtc = |
10609 | to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]); | |
10610 | unsigned long flags; | |
10611 | ||
f326038a DV |
10612 | |
10613 | /* | |
10614 | * This is called both by irq handlers and the reset code (to complete | |
10615 | * lost pageflips) so needs the full irqsave spinlocks. | |
10616 | * | |
10617 | * NB: An MMIO update of the plane base pointer will also | |
e7d841ca CW |
10618 | * generate a page-flip completion irq, i.e. every modeset |
10619 | * is also accompanied by a spurious intel_prepare_page_flip(). | |
10620 | */ | |
6b95a207 | 10621 | spin_lock_irqsave(&dev->event_lock, flags); |
75f7f3ec | 10622 | if (intel_crtc->unpin_work && page_flip_finished(intel_crtc)) |
e7d841ca | 10623 | atomic_inc_not_zero(&intel_crtc->unpin_work->pending); |
6b95a207 KH |
10624 | spin_unlock_irqrestore(&dev->event_lock, flags); |
10625 | } | |
10626 | ||
eba905b2 | 10627 | static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc) |
e7d841ca CW |
10628 | { |
10629 | /* Ensure that the work item is consistent when activating it ... */ | |
10630 | smp_wmb(); | |
10631 | atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING); | |
10632 | /* and that it is marked active as soon as the irq could fire. */ | |
10633 | smp_wmb(); | |
10634 | } | |
10635 | ||
8c9f3aaf JB |
10636 | static int intel_gen2_queue_flip(struct drm_device *dev, |
10637 | struct drm_crtc *crtc, | |
10638 | struct drm_framebuffer *fb, | |
ed8d1975 | 10639 | struct drm_i915_gem_object *obj, |
a4872ba6 | 10640 | struct intel_engine_cs *ring, |
ed8d1975 | 10641 | uint32_t flags) |
8c9f3aaf | 10642 | { |
8c9f3aaf | 10643 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8c9f3aaf JB |
10644 | u32 flip_mask; |
10645 | int ret; | |
10646 | ||
6d90c952 | 10647 | ret = intel_ring_begin(ring, 6); |
8c9f3aaf | 10648 | if (ret) |
4fa62c89 | 10649 | return ret; |
8c9f3aaf JB |
10650 | |
10651 | /* Can't queue multiple flips, so wait for the previous | |
10652 | * one to finish before executing the next. | |
10653 | */ | |
10654 | if (intel_crtc->plane) | |
10655 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
10656 | else | |
10657 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
10658 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
10659 | intel_ring_emit(ring, MI_NOOP); | |
10660 | intel_ring_emit(ring, MI_DISPLAY_FLIP | | |
10661 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
10662 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 10663 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
6d90c952 | 10664 | intel_ring_emit(ring, 0); /* aux display base address, unused */ |
e7d841ca CW |
10665 | |
10666 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 10667 | __intel_ring_advance(ring); |
83d4092b | 10668 | return 0; |
8c9f3aaf JB |
10669 | } |
10670 | ||
10671 | static int intel_gen3_queue_flip(struct drm_device *dev, | |
10672 | struct drm_crtc *crtc, | |
10673 | struct drm_framebuffer *fb, | |
ed8d1975 | 10674 | struct drm_i915_gem_object *obj, |
a4872ba6 | 10675 | struct intel_engine_cs *ring, |
ed8d1975 | 10676 | uint32_t flags) |
8c9f3aaf | 10677 | { |
8c9f3aaf | 10678 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8c9f3aaf JB |
10679 | u32 flip_mask; |
10680 | int ret; | |
10681 | ||
6d90c952 | 10682 | ret = intel_ring_begin(ring, 6); |
8c9f3aaf | 10683 | if (ret) |
4fa62c89 | 10684 | return ret; |
8c9f3aaf JB |
10685 | |
10686 | if (intel_crtc->plane) | |
10687 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
10688 | else | |
10689 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
10690 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
10691 | intel_ring_emit(ring, MI_NOOP); | |
10692 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | | |
10693 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
10694 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 10695 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
6d90c952 DV |
10696 | intel_ring_emit(ring, MI_NOOP); |
10697 | ||
e7d841ca | 10698 | intel_mark_page_flip_active(intel_crtc); |
09246732 | 10699 | __intel_ring_advance(ring); |
83d4092b | 10700 | return 0; |
8c9f3aaf JB |
10701 | } |
10702 | ||
10703 | static int intel_gen4_queue_flip(struct drm_device *dev, | |
10704 | struct drm_crtc *crtc, | |
10705 | struct drm_framebuffer *fb, | |
ed8d1975 | 10706 | struct drm_i915_gem_object *obj, |
a4872ba6 | 10707 | struct intel_engine_cs *ring, |
ed8d1975 | 10708 | uint32_t flags) |
8c9f3aaf JB |
10709 | { |
10710 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10711 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
10712 | uint32_t pf, pipesrc; | |
10713 | int ret; | |
10714 | ||
6d90c952 | 10715 | ret = intel_ring_begin(ring, 4); |
8c9f3aaf | 10716 | if (ret) |
4fa62c89 | 10717 | return ret; |
8c9f3aaf JB |
10718 | |
10719 | /* i965+ uses the linear or tiled offsets from the | |
10720 | * Display Registers (which do not change across a page-flip) | |
10721 | * so we need only reprogram the base address. | |
10722 | */ | |
6d90c952 DV |
10723 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
10724 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
10725 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 10726 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset | |
c2c75131 | 10727 | obj->tiling_mode); |
8c9f3aaf JB |
10728 | |
10729 | /* XXX Enabling the panel-fitter across page-flip is so far | |
10730 | * untested on non-native modes, so ignore it for now. | |
10731 | * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; | |
10732 | */ | |
10733 | pf = 0; | |
10734 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; | |
6d90c952 | 10735 | intel_ring_emit(ring, pf | pipesrc); |
e7d841ca CW |
10736 | |
10737 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 10738 | __intel_ring_advance(ring); |
83d4092b | 10739 | return 0; |
8c9f3aaf JB |
10740 | } |
10741 | ||
10742 | static int intel_gen6_queue_flip(struct drm_device *dev, | |
10743 | struct drm_crtc *crtc, | |
10744 | struct drm_framebuffer *fb, | |
ed8d1975 | 10745 | struct drm_i915_gem_object *obj, |
a4872ba6 | 10746 | struct intel_engine_cs *ring, |
ed8d1975 | 10747 | uint32_t flags) |
8c9f3aaf JB |
10748 | { |
10749 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10750 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
10751 | uint32_t pf, pipesrc; | |
10752 | int ret; | |
10753 | ||
6d90c952 | 10754 | ret = intel_ring_begin(ring, 4); |
8c9f3aaf | 10755 | if (ret) |
4fa62c89 | 10756 | return ret; |
8c9f3aaf | 10757 | |
6d90c952 DV |
10758 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
10759 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
10760 | intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode); | |
75f7f3ec | 10761 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
8c9f3aaf | 10762 | |
dc257cf1 DV |
10763 | /* Contrary to the suggestions in the documentation, |
10764 | * "Enable Panel Fitter" does not seem to be required when page | |
10765 | * flipping with a non-native mode, and worse causes a normal | |
10766 | * modeset to fail. | |
10767 | * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; | |
10768 | */ | |
10769 | pf = 0; | |
8c9f3aaf | 10770 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; |
6d90c952 | 10771 | intel_ring_emit(ring, pf | pipesrc); |
e7d841ca CW |
10772 | |
10773 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 10774 | __intel_ring_advance(ring); |
83d4092b | 10775 | return 0; |
8c9f3aaf JB |
10776 | } |
10777 | ||
7c9017e5 JB |
10778 | static int intel_gen7_queue_flip(struct drm_device *dev, |
10779 | struct drm_crtc *crtc, | |
10780 | struct drm_framebuffer *fb, | |
ed8d1975 | 10781 | struct drm_i915_gem_object *obj, |
a4872ba6 | 10782 | struct intel_engine_cs *ring, |
ed8d1975 | 10783 | uint32_t flags) |
7c9017e5 | 10784 | { |
7c9017e5 | 10785 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
cb05d8de | 10786 | uint32_t plane_bit = 0; |
ffe74d75 CW |
10787 | int len, ret; |
10788 | ||
eba905b2 | 10789 | switch (intel_crtc->plane) { |
cb05d8de DV |
10790 | case PLANE_A: |
10791 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A; | |
10792 | break; | |
10793 | case PLANE_B: | |
10794 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B; | |
10795 | break; | |
10796 | case PLANE_C: | |
10797 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C; | |
10798 | break; | |
10799 | default: | |
10800 | WARN_ONCE(1, "unknown plane in flip command\n"); | |
4fa62c89 | 10801 | return -ENODEV; |
cb05d8de DV |
10802 | } |
10803 | ||
ffe74d75 | 10804 | len = 4; |
f476828a | 10805 | if (ring->id == RCS) { |
ffe74d75 | 10806 | len += 6; |
f476828a DL |
10807 | /* |
10808 | * On Gen 8, SRM is now taking an extra dword to accommodate | |
10809 | * 48bits addresses, and we need a NOOP for the batch size to | |
10810 | * stay even. | |
10811 | */ | |
10812 | if (IS_GEN8(dev)) | |
10813 | len += 2; | |
10814 | } | |
ffe74d75 | 10815 | |
f66fab8e VS |
10816 | /* |
10817 | * BSpec MI_DISPLAY_FLIP for IVB: | |
10818 | * "The full packet must be contained within the same cache line." | |
10819 | * | |
10820 | * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same | |
10821 | * cacheline, if we ever start emitting more commands before | |
10822 | * the MI_DISPLAY_FLIP we may need to first emit everything else, | |
10823 | * then do the cacheline alignment, and finally emit the | |
10824 | * MI_DISPLAY_FLIP. | |
10825 | */ | |
10826 | ret = intel_ring_cacheline_align(ring); | |
10827 | if (ret) | |
4fa62c89 | 10828 | return ret; |
f66fab8e | 10829 | |
ffe74d75 | 10830 | ret = intel_ring_begin(ring, len); |
7c9017e5 | 10831 | if (ret) |
4fa62c89 | 10832 | return ret; |
7c9017e5 | 10833 | |
ffe74d75 CW |
10834 | /* Unmask the flip-done completion message. Note that the bspec says that |
10835 | * we should do this for both the BCS and RCS, and that we must not unmask | |
10836 | * more than one flip event at any time (or ensure that one flip message | |
10837 | * can be sent by waiting for flip-done prior to queueing new flips). | |
10838 | * Experimentation says that BCS works despite DERRMR masking all | |
10839 | * flip-done completion events and that unmasking all planes at once | |
10840 | * for the RCS also doesn't appear to drop events. Setting the DERRMR | |
10841 | * to zero does lead to lockups within MI_DISPLAY_FLIP. | |
10842 | */ | |
10843 | if (ring->id == RCS) { | |
10844 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
10845 | intel_ring_emit(ring, DERRMR); | |
10846 | intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE | | |
10847 | DERRMR_PIPEB_PRI_FLIP_DONE | | |
10848 | DERRMR_PIPEC_PRI_FLIP_DONE)); | |
f476828a DL |
10849 | if (IS_GEN8(dev)) |
10850 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) | | |
10851 | MI_SRM_LRM_GLOBAL_GTT); | |
10852 | else | |
10853 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) | | |
10854 | MI_SRM_LRM_GLOBAL_GTT); | |
ffe74d75 CW |
10855 | intel_ring_emit(ring, DERRMR); |
10856 | intel_ring_emit(ring, ring->scratch.gtt_offset + 256); | |
f476828a DL |
10857 | if (IS_GEN8(dev)) { |
10858 | intel_ring_emit(ring, 0); | |
10859 | intel_ring_emit(ring, MI_NOOP); | |
10860 | } | |
ffe74d75 CW |
10861 | } |
10862 | ||
cb05d8de | 10863 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit); |
01f2c773 | 10864 | intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode)); |
75f7f3ec | 10865 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
7c9017e5 | 10866 | intel_ring_emit(ring, (MI_NOOP)); |
e7d841ca CW |
10867 | |
10868 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 10869 | __intel_ring_advance(ring); |
83d4092b | 10870 | return 0; |
7c9017e5 JB |
10871 | } |
10872 | ||
84c33a64 SG |
10873 | static bool use_mmio_flip(struct intel_engine_cs *ring, |
10874 | struct drm_i915_gem_object *obj) | |
10875 | { | |
10876 | /* | |
10877 | * This is not being used for older platforms, because | |
10878 | * non-availability of flip done interrupt forces us to use | |
10879 | * CS flips. Older platforms derive flip done using some clever | |
10880 | * tricks involving the flip_pending status bits and vblank irqs. | |
10881 | * So using MMIO flips there would disrupt this mechanism. | |
10882 | */ | |
10883 | ||
8e09bf83 CW |
10884 | if (ring == NULL) |
10885 | return true; | |
10886 | ||
84c33a64 SG |
10887 | if (INTEL_INFO(ring->dev)->gen < 5) |
10888 | return false; | |
10889 | ||
10890 | if (i915.use_mmio_flip < 0) | |
10891 | return false; | |
10892 | else if (i915.use_mmio_flip > 0) | |
10893 | return true; | |
14bf993e OM |
10894 | else if (i915.enable_execlists) |
10895 | return true; | |
84c33a64 | 10896 | else |
b4716185 | 10897 | return ring != i915_gem_request_get_ring(obj->last_write_req); |
84c33a64 SG |
10898 | } |
10899 | ||
ff944564 DL |
10900 | static void skl_do_mmio_flip(struct intel_crtc *intel_crtc) |
10901 | { | |
10902 | struct drm_device *dev = intel_crtc->base.dev; | |
10903 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10904 | struct drm_framebuffer *fb = intel_crtc->base.primary->fb; | |
ff944564 DL |
10905 | const enum pipe pipe = intel_crtc->pipe; |
10906 | u32 ctl, stride; | |
10907 | ||
10908 | ctl = I915_READ(PLANE_CTL(pipe, 0)); | |
10909 | ctl &= ~PLANE_CTL_TILED_MASK; | |
2ebef630 TU |
10910 | switch (fb->modifier[0]) { |
10911 | case DRM_FORMAT_MOD_NONE: | |
10912 | break; | |
10913 | case I915_FORMAT_MOD_X_TILED: | |
ff944564 | 10914 | ctl |= PLANE_CTL_TILED_X; |
2ebef630 TU |
10915 | break; |
10916 | case I915_FORMAT_MOD_Y_TILED: | |
10917 | ctl |= PLANE_CTL_TILED_Y; | |
10918 | break; | |
10919 | case I915_FORMAT_MOD_Yf_TILED: | |
10920 | ctl |= PLANE_CTL_TILED_YF; | |
10921 | break; | |
10922 | default: | |
10923 | MISSING_CASE(fb->modifier[0]); | |
10924 | } | |
ff944564 DL |
10925 | |
10926 | /* | |
10927 | * The stride is either expressed as a multiple of 64 bytes chunks for | |
10928 | * linear buffers or in number of tiles for tiled buffers. | |
10929 | */ | |
2ebef630 TU |
10930 | stride = fb->pitches[0] / |
10931 | intel_fb_stride_alignment(dev, fb->modifier[0], | |
10932 | fb->pixel_format); | |
ff944564 DL |
10933 | |
10934 | /* | |
10935 | * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on | |
10936 | * PLANE_SURF updates, the update is then guaranteed to be atomic. | |
10937 | */ | |
10938 | I915_WRITE(PLANE_CTL(pipe, 0), ctl); | |
10939 | I915_WRITE(PLANE_STRIDE(pipe, 0), stride); | |
10940 | ||
10941 | I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset); | |
10942 | POSTING_READ(PLANE_SURF(pipe, 0)); | |
10943 | } | |
10944 | ||
10945 | static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc) | |
84c33a64 SG |
10946 | { |
10947 | struct drm_device *dev = intel_crtc->base.dev; | |
10948 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10949 | struct intel_framebuffer *intel_fb = | |
10950 | to_intel_framebuffer(intel_crtc->base.primary->fb); | |
10951 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
10952 | u32 dspcntr; | |
10953 | u32 reg; | |
10954 | ||
84c33a64 SG |
10955 | reg = DSPCNTR(intel_crtc->plane); |
10956 | dspcntr = I915_READ(reg); | |
10957 | ||
c5d97472 DL |
10958 | if (obj->tiling_mode != I915_TILING_NONE) |
10959 | dspcntr |= DISPPLANE_TILED; | |
10960 | else | |
10961 | dspcntr &= ~DISPPLANE_TILED; | |
10962 | ||
84c33a64 SG |
10963 | I915_WRITE(reg, dspcntr); |
10964 | ||
10965 | I915_WRITE(DSPSURF(intel_crtc->plane), | |
10966 | intel_crtc->unpin_work->gtt_offset); | |
10967 | POSTING_READ(DSPSURF(intel_crtc->plane)); | |
84c33a64 | 10968 | |
ff944564 DL |
10969 | } |
10970 | ||
10971 | /* | |
10972 | * XXX: This is the temporary way to update the plane registers until we get | |
10973 | * around to using the usual plane update functions for MMIO flips | |
10974 | */ | |
10975 | static void intel_do_mmio_flip(struct intel_crtc *intel_crtc) | |
10976 | { | |
10977 | struct drm_device *dev = intel_crtc->base.dev; | |
10978 | bool atomic_update; | |
10979 | u32 start_vbl_count; | |
10980 | ||
10981 | intel_mark_page_flip_active(intel_crtc); | |
10982 | ||
10983 | atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count); | |
10984 | ||
10985 | if (INTEL_INFO(dev)->gen >= 9) | |
10986 | skl_do_mmio_flip(intel_crtc); | |
10987 | else | |
10988 | /* use_mmio_flip() retricts MMIO flips to ilk+ */ | |
10989 | ilk_do_mmio_flip(intel_crtc); | |
10990 | ||
9362c7c5 ACO |
10991 | if (atomic_update) |
10992 | intel_pipe_update_end(intel_crtc, start_vbl_count); | |
84c33a64 SG |
10993 | } |
10994 | ||
9362c7c5 | 10995 | static void intel_mmio_flip_work_func(struct work_struct *work) |
84c33a64 | 10996 | { |
b2cfe0ab CW |
10997 | struct intel_mmio_flip *mmio_flip = |
10998 | container_of(work, struct intel_mmio_flip, work); | |
84c33a64 | 10999 | |
eed29a5b DV |
11000 | if (mmio_flip->req) |
11001 | WARN_ON(__i915_wait_request(mmio_flip->req, | |
b2cfe0ab | 11002 | mmio_flip->crtc->reset_counter, |
bcafc4e3 CW |
11003 | false, NULL, |
11004 | &mmio_flip->i915->rps.mmioflips)); | |
84c33a64 | 11005 | |
b2cfe0ab CW |
11006 | intel_do_mmio_flip(mmio_flip->crtc); |
11007 | ||
eed29a5b | 11008 | i915_gem_request_unreference__unlocked(mmio_flip->req); |
b2cfe0ab | 11009 | kfree(mmio_flip); |
84c33a64 SG |
11010 | } |
11011 | ||
11012 | static int intel_queue_mmio_flip(struct drm_device *dev, | |
11013 | struct drm_crtc *crtc, | |
11014 | struct drm_framebuffer *fb, | |
11015 | struct drm_i915_gem_object *obj, | |
11016 | struct intel_engine_cs *ring, | |
11017 | uint32_t flags) | |
11018 | { | |
b2cfe0ab CW |
11019 | struct intel_mmio_flip *mmio_flip; |
11020 | ||
11021 | mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL); | |
11022 | if (mmio_flip == NULL) | |
11023 | return -ENOMEM; | |
84c33a64 | 11024 | |
bcafc4e3 | 11025 | mmio_flip->i915 = to_i915(dev); |
eed29a5b | 11026 | mmio_flip->req = i915_gem_request_reference(obj->last_write_req); |
b2cfe0ab | 11027 | mmio_flip->crtc = to_intel_crtc(crtc); |
536f5b5e | 11028 | |
b2cfe0ab CW |
11029 | INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func); |
11030 | schedule_work(&mmio_flip->work); | |
84c33a64 | 11031 | |
84c33a64 SG |
11032 | return 0; |
11033 | } | |
11034 | ||
8c9f3aaf JB |
11035 | static int intel_default_queue_flip(struct drm_device *dev, |
11036 | struct drm_crtc *crtc, | |
11037 | struct drm_framebuffer *fb, | |
ed8d1975 | 11038 | struct drm_i915_gem_object *obj, |
a4872ba6 | 11039 | struct intel_engine_cs *ring, |
ed8d1975 | 11040 | uint32_t flags) |
8c9f3aaf JB |
11041 | { |
11042 | return -ENODEV; | |
11043 | } | |
11044 | ||
d6bbafa1 CW |
11045 | static bool __intel_pageflip_stall_check(struct drm_device *dev, |
11046 | struct drm_crtc *crtc) | |
11047 | { | |
11048 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11049 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11050 | struct intel_unpin_work *work = intel_crtc->unpin_work; | |
11051 | u32 addr; | |
11052 | ||
11053 | if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE) | |
11054 | return true; | |
11055 | ||
11056 | if (!work->enable_stall_check) | |
11057 | return false; | |
11058 | ||
11059 | if (work->flip_ready_vblank == 0) { | |
3a8a946e DV |
11060 | if (work->flip_queued_req && |
11061 | !i915_gem_request_completed(work->flip_queued_req, true)) | |
d6bbafa1 CW |
11062 | return false; |
11063 | ||
1e3feefd | 11064 | work->flip_ready_vblank = drm_crtc_vblank_count(crtc); |
d6bbafa1 CW |
11065 | } |
11066 | ||
1e3feefd | 11067 | if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3) |
d6bbafa1 CW |
11068 | return false; |
11069 | ||
11070 | /* Potential stall - if we see that the flip has happened, | |
11071 | * assume a missed interrupt. */ | |
11072 | if (INTEL_INFO(dev)->gen >= 4) | |
11073 | addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane))); | |
11074 | else | |
11075 | addr = I915_READ(DSPADDR(intel_crtc->plane)); | |
11076 | ||
11077 | /* There is a potential issue here with a false positive after a flip | |
11078 | * to the same address. We could address this by checking for a | |
11079 | * non-incrementing frame counter. | |
11080 | */ | |
11081 | return addr == work->gtt_offset; | |
11082 | } | |
11083 | ||
11084 | void intel_check_page_flip(struct drm_device *dev, int pipe) | |
11085 | { | |
11086 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11087 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
11088 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6ad790c0 | 11089 | struct intel_unpin_work *work; |
f326038a | 11090 | |
6c51d46f | 11091 | WARN_ON(!in_interrupt()); |
d6bbafa1 CW |
11092 | |
11093 | if (crtc == NULL) | |
11094 | return; | |
11095 | ||
f326038a | 11096 | spin_lock(&dev->event_lock); |
6ad790c0 CW |
11097 | work = intel_crtc->unpin_work; |
11098 | if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) { | |
d6bbafa1 | 11099 | WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n", |
6ad790c0 | 11100 | work->flip_queued_vblank, drm_vblank_count(dev, pipe)); |
d6bbafa1 | 11101 | page_flip_completed(intel_crtc); |
6ad790c0 | 11102 | work = NULL; |
d6bbafa1 | 11103 | } |
6ad790c0 CW |
11104 | if (work != NULL && |
11105 | drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1) | |
11106 | intel_queue_rps_boost_for_request(dev, work->flip_queued_req); | |
f326038a | 11107 | spin_unlock(&dev->event_lock); |
d6bbafa1 CW |
11108 | } |
11109 | ||
6b95a207 KH |
11110 | static int intel_crtc_page_flip(struct drm_crtc *crtc, |
11111 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
11112 | struct drm_pending_vblank_event *event, |
11113 | uint32_t page_flip_flags) | |
6b95a207 KH |
11114 | { |
11115 | struct drm_device *dev = crtc->dev; | |
11116 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f4510a27 | 11117 | struct drm_framebuffer *old_fb = crtc->primary->fb; |
2ff8fde1 | 11118 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
6b95a207 | 11119 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
455a6808 | 11120 | struct drm_plane *primary = crtc->primary; |
a071fa00 | 11121 | enum pipe pipe = intel_crtc->pipe; |
6b95a207 | 11122 | struct intel_unpin_work *work; |
a4872ba6 | 11123 | struct intel_engine_cs *ring; |
cf5d8a46 | 11124 | bool mmio_flip; |
52e68630 | 11125 | int ret; |
6b95a207 | 11126 | |
2ff8fde1 MR |
11127 | /* |
11128 | * drm_mode_page_flip_ioctl() should already catch this, but double | |
11129 | * check to be safe. In the future we may enable pageflipping from | |
11130 | * a disabled primary plane. | |
11131 | */ | |
11132 | if (WARN_ON(intel_fb_obj(old_fb) == NULL)) | |
11133 | return -EBUSY; | |
11134 | ||
e6a595d2 | 11135 | /* Can't change pixel format via MI display flips. */ |
f4510a27 | 11136 | if (fb->pixel_format != crtc->primary->fb->pixel_format) |
e6a595d2 VS |
11137 | return -EINVAL; |
11138 | ||
11139 | /* | |
11140 | * TILEOFF/LINOFF registers can't be changed via MI display flips. | |
11141 | * Note that pitch changes could also affect these register. | |
11142 | */ | |
11143 | if (INTEL_INFO(dev)->gen > 3 && | |
f4510a27 MR |
11144 | (fb->offsets[0] != crtc->primary->fb->offsets[0] || |
11145 | fb->pitches[0] != crtc->primary->fb->pitches[0])) | |
e6a595d2 VS |
11146 | return -EINVAL; |
11147 | ||
f900db47 CW |
11148 | if (i915_terminally_wedged(&dev_priv->gpu_error)) |
11149 | goto out_hang; | |
11150 | ||
b14c5679 | 11151 | work = kzalloc(sizeof(*work), GFP_KERNEL); |
6b95a207 KH |
11152 | if (work == NULL) |
11153 | return -ENOMEM; | |
11154 | ||
6b95a207 | 11155 | work->event = event; |
b4a98e57 | 11156 | work->crtc = crtc; |
ab8d6675 | 11157 | work->old_fb = old_fb; |
6b95a207 KH |
11158 | INIT_WORK(&work->work, intel_unpin_work_fn); |
11159 | ||
87b6b101 | 11160 | ret = drm_crtc_vblank_get(crtc); |
7317c75e JB |
11161 | if (ret) |
11162 | goto free_work; | |
11163 | ||
6b95a207 | 11164 | /* We borrow the event spin lock for protecting unpin_work */ |
5e2d7afc | 11165 | spin_lock_irq(&dev->event_lock); |
6b95a207 | 11166 | if (intel_crtc->unpin_work) { |
d6bbafa1 CW |
11167 | /* Before declaring the flip queue wedged, check if |
11168 | * the hardware completed the operation behind our backs. | |
11169 | */ | |
11170 | if (__intel_pageflip_stall_check(dev, crtc)) { | |
11171 | DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n"); | |
11172 | page_flip_completed(intel_crtc); | |
11173 | } else { | |
11174 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); | |
5e2d7afc | 11175 | spin_unlock_irq(&dev->event_lock); |
468f0b44 | 11176 | |
d6bbafa1 CW |
11177 | drm_crtc_vblank_put(crtc); |
11178 | kfree(work); | |
11179 | return -EBUSY; | |
11180 | } | |
6b95a207 KH |
11181 | } |
11182 | intel_crtc->unpin_work = work; | |
5e2d7afc | 11183 | spin_unlock_irq(&dev->event_lock); |
6b95a207 | 11184 | |
b4a98e57 CW |
11185 | if (atomic_read(&intel_crtc->unpin_work_count) >= 2) |
11186 | flush_workqueue(dev_priv->wq); | |
11187 | ||
75dfca80 | 11188 | /* Reference the objects for the scheduled work. */ |
ab8d6675 | 11189 | drm_framebuffer_reference(work->old_fb); |
05394f39 | 11190 | drm_gem_object_reference(&obj->base); |
6b95a207 | 11191 | |
f4510a27 | 11192 | crtc->primary->fb = fb; |
afd65eb4 | 11193 | update_state_fb(crtc->primary); |
1ed1f968 | 11194 | |
e1f99ce6 | 11195 | work->pending_flip_obj = obj; |
e1f99ce6 | 11196 | |
89ed88ba CW |
11197 | ret = i915_mutex_lock_interruptible(dev); |
11198 | if (ret) | |
11199 | goto cleanup; | |
11200 | ||
b4a98e57 | 11201 | atomic_inc(&intel_crtc->unpin_work_count); |
10d83730 | 11202 | intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
e1f99ce6 | 11203 | |
75f7f3ec | 11204 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) |
a071fa00 | 11205 | work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1; |
75f7f3ec | 11206 | |
4fa62c89 VS |
11207 | if (IS_VALLEYVIEW(dev)) { |
11208 | ring = &dev_priv->ring[BCS]; | |
ab8d6675 | 11209 | if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode) |
8e09bf83 CW |
11210 | /* vlv: DISPLAY_FLIP fails to change tiling */ |
11211 | ring = NULL; | |
48bf5b2d | 11212 | } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) { |
2a92d5bc | 11213 | ring = &dev_priv->ring[BCS]; |
4fa62c89 | 11214 | } else if (INTEL_INFO(dev)->gen >= 7) { |
b4716185 | 11215 | ring = i915_gem_request_get_ring(obj->last_write_req); |
4fa62c89 VS |
11216 | if (ring == NULL || ring->id != RCS) |
11217 | ring = &dev_priv->ring[BCS]; | |
11218 | } else { | |
11219 | ring = &dev_priv->ring[RCS]; | |
11220 | } | |
11221 | ||
cf5d8a46 CW |
11222 | mmio_flip = use_mmio_flip(ring, obj); |
11223 | ||
11224 | /* When using CS flips, we want to emit semaphores between rings. | |
11225 | * However, when using mmio flips we will create a task to do the | |
11226 | * synchronisation, so all we want here is to pin the framebuffer | |
11227 | * into the display plane and skip any waits. | |
11228 | */ | |
82bc3b2d | 11229 | ret = intel_pin_and_fence_fb_obj(crtc->primary, fb, |
cf5d8a46 | 11230 | crtc->primary->state, |
b4716185 | 11231 | mmio_flip ? i915_gem_request_get_ring(obj->last_write_req) : ring); |
8c9f3aaf JB |
11232 | if (ret) |
11233 | goto cleanup_pending; | |
6b95a207 | 11234 | |
121920fa TU |
11235 | work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj) |
11236 | + intel_crtc->dspaddr_offset; | |
4fa62c89 | 11237 | |
cf5d8a46 | 11238 | if (mmio_flip) { |
84c33a64 SG |
11239 | ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring, |
11240 | page_flip_flags); | |
d6bbafa1 CW |
11241 | if (ret) |
11242 | goto cleanup_unpin; | |
11243 | ||
f06cc1b9 JH |
11244 | i915_gem_request_assign(&work->flip_queued_req, |
11245 | obj->last_write_req); | |
d6bbafa1 | 11246 | } else { |
d94b5030 CW |
11247 | if (obj->last_write_req) { |
11248 | ret = i915_gem_check_olr(obj->last_write_req); | |
11249 | if (ret) | |
11250 | goto cleanup_unpin; | |
11251 | } | |
11252 | ||
84c33a64 | 11253 | ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring, |
d6bbafa1 CW |
11254 | page_flip_flags); |
11255 | if (ret) | |
11256 | goto cleanup_unpin; | |
11257 | ||
f06cc1b9 JH |
11258 | i915_gem_request_assign(&work->flip_queued_req, |
11259 | intel_ring_get_request(ring)); | |
d6bbafa1 CW |
11260 | } |
11261 | ||
1e3feefd | 11262 | work->flip_queued_vblank = drm_crtc_vblank_count(crtc); |
d6bbafa1 | 11263 | work->enable_stall_check = true; |
4fa62c89 | 11264 | |
ab8d6675 | 11265 | i915_gem_track_fb(intel_fb_obj(work->old_fb), obj, |
a071fa00 DV |
11266 | INTEL_FRONTBUFFER_PRIMARY(pipe)); |
11267 | ||
7ff0ebcc | 11268 | intel_fbc_disable(dev); |
f99d7069 | 11269 | intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe)); |
6b95a207 KH |
11270 | mutex_unlock(&dev->struct_mutex); |
11271 | ||
e5510fac JB |
11272 | trace_i915_flip_request(intel_crtc->plane, obj); |
11273 | ||
6b95a207 | 11274 | return 0; |
96b099fd | 11275 | |
4fa62c89 | 11276 | cleanup_unpin: |
82bc3b2d | 11277 | intel_unpin_fb_obj(fb, crtc->primary->state); |
8c9f3aaf | 11278 | cleanup_pending: |
b4a98e57 | 11279 | atomic_dec(&intel_crtc->unpin_work_count); |
89ed88ba CW |
11280 | mutex_unlock(&dev->struct_mutex); |
11281 | cleanup: | |
f4510a27 | 11282 | crtc->primary->fb = old_fb; |
afd65eb4 | 11283 | update_state_fb(crtc->primary); |
89ed88ba CW |
11284 | |
11285 | drm_gem_object_unreference_unlocked(&obj->base); | |
ab8d6675 | 11286 | drm_framebuffer_unreference(work->old_fb); |
96b099fd | 11287 | |
5e2d7afc | 11288 | spin_lock_irq(&dev->event_lock); |
96b099fd | 11289 | intel_crtc->unpin_work = NULL; |
5e2d7afc | 11290 | spin_unlock_irq(&dev->event_lock); |
96b099fd | 11291 | |
87b6b101 | 11292 | drm_crtc_vblank_put(crtc); |
7317c75e | 11293 | free_work: |
96b099fd CW |
11294 | kfree(work); |
11295 | ||
f900db47 CW |
11296 | if (ret == -EIO) { |
11297 | out_hang: | |
53a366b9 | 11298 | ret = intel_plane_restore(primary); |
f0d3dad3 | 11299 | if (ret == 0 && event) { |
5e2d7afc | 11300 | spin_lock_irq(&dev->event_lock); |
a071fa00 | 11301 | drm_send_vblank_event(dev, pipe, event); |
5e2d7afc | 11302 | spin_unlock_irq(&dev->event_lock); |
f0d3dad3 | 11303 | } |
f900db47 | 11304 | } |
96b099fd | 11305 | return ret; |
6b95a207 KH |
11306 | } |
11307 | ||
65b38e0d | 11308 | static const struct drm_crtc_helper_funcs intel_helper_funcs = { |
f6e5b160 CW |
11309 | .mode_set_base_atomic = intel_pipe_set_base_atomic, |
11310 | .load_lut = intel_crtc_load_lut, | |
ea2c67bb MR |
11311 | .atomic_begin = intel_begin_crtc_commit, |
11312 | .atomic_flush = intel_finish_crtc_commit, | |
f6e5b160 CW |
11313 | }; |
11314 | ||
9a935856 DV |
11315 | /** |
11316 | * intel_modeset_update_staged_output_state | |
11317 | * | |
11318 | * Updates the staged output configuration state, e.g. after we've read out the | |
11319 | * current hw state. | |
11320 | */ | |
11321 | static void intel_modeset_update_staged_output_state(struct drm_device *dev) | |
f6e5b160 | 11322 | { |
7668851f | 11323 | struct intel_crtc *crtc; |
9a935856 DV |
11324 | struct intel_encoder *encoder; |
11325 | struct intel_connector *connector; | |
f6e5b160 | 11326 | |
3a3371ff | 11327 | for_each_intel_connector(dev, connector) { |
9a935856 DV |
11328 | connector->new_encoder = |
11329 | to_intel_encoder(connector->base.encoder); | |
11330 | } | |
f6e5b160 | 11331 | |
b2784e15 | 11332 | for_each_intel_encoder(dev, encoder) { |
9a935856 DV |
11333 | encoder->new_crtc = |
11334 | to_intel_crtc(encoder->base.crtc); | |
11335 | } | |
7668851f | 11336 | |
d3fcc808 | 11337 | for_each_intel_crtc(dev, crtc) { |
83d65738 | 11338 | crtc->new_enabled = crtc->base.state->enable; |
7668851f | 11339 | } |
f6e5b160 CW |
11340 | } |
11341 | ||
d29b2f9d ACO |
11342 | /* Transitional helper to copy current connector/encoder state to |
11343 | * connector->state. This is needed so that code that is partially | |
11344 | * converted to atomic does the right thing. | |
11345 | */ | |
11346 | static void intel_modeset_update_connector_atomic_state(struct drm_device *dev) | |
11347 | { | |
11348 | struct intel_connector *connector; | |
11349 | ||
11350 | for_each_intel_connector(dev, connector) { | |
11351 | if (connector->base.encoder) { | |
11352 | connector->base.state->best_encoder = | |
11353 | connector->base.encoder; | |
11354 | connector->base.state->crtc = | |
11355 | connector->base.encoder->crtc; | |
11356 | } else { | |
11357 | connector->base.state->best_encoder = NULL; | |
11358 | connector->base.state->crtc = NULL; | |
11359 | } | |
11360 | } | |
11361 | } | |
11362 | ||
a821fc46 | 11363 | /* Fixup legacy state after an atomic state swap. |
9a935856 | 11364 | */ |
a821fc46 | 11365 | static void intel_modeset_fixup_state(struct drm_atomic_state *state) |
9a935856 | 11366 | { |
a821fc46 | 11367 | struct intel_crtc *crtc; |
9a935856 | 11368 | struct intel_encoder *encoder; |
a821fc46 | 11369 | struct intel_connector *connector; |
d5432a9d | 11370 | |
a821fc46 ACO |
11371 | for_each_intel_connector(state->dev, connector) { |
11372 | connector->base.encoder = connector->base.state->best_encoder; | |
11373 | if (connector->base.encoder) | |
11374 | connector->base.encoder->crtc = | |
11375 | connector->base.state->crtc; | |
9a935856 | 11376 | } |
f6e5b160 | 11377 | |
d5432a9d ACO |
11378 | /* Update crtc of disabled encoders */ |
11379 | for_each_intel_encoder(state->dev, encoder) { | |
11380 | int num_connectors = 0; | |
11381 | ||
a821fc46 ACO |
11382 | for_each_intel_connector(state->dev, connector) |
11383 | if (connector->base.encoder == &encoder->base) | |
d5432a9d ACO |
11384 | num_connectors++; |
11385 | ||
11386 | if (num_connectors == 0) | |
11387 | encoder->base.crtc = NULL; | |
9a935856 | 11388 | } |
7668851f | 11389 | |
a821fc46 ACO |
11390 | for_each_intel_crtc(state->dev, crtc) { |
11391 | crtc->base.enabled = crtc->base.state->enable; | |
11392 | crtc->config = to_intel_crtc_state(crtc->base.state); | |
7668851f | 11393 | } |
d29b2f9d | 11394 | |
d5432a9d ACO |
11395 | /* Copy the new configuration to the staged state, to keep the few |
11396 | * pieces of code that haven't been converted yet happy */ | |
11397 | intel_modeset_update_staged_output_state(state->dev); | |
9a935856 DV |
11398 | } |
11399 | ||
050f7aeb | 11400 | static void |
eba905b2 | 11401 | connected_sink_compute_bpp(struct intel_connector *connector, |
5cec258b | 11402 | struct intel_crtc_state *pipe_config) |
050f7aeb DV |
11403 | { |
11404 | int bpp = pipe_config->pipe_bpp; | |
11405 | ||
11406 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n", | |
11407 | connector->base.base.id, | |
c23cc417 | 11408 | connector->base.name); |
050f7aeb DV |
11409 | |
11410 | /* Don't use an invalid EDID bpc value */ | |
11411 | if (connector->base.display_info.bpc && | |
11412 | connector->base.display_info.bpc * 3 < bpp) { | |
11413 | DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n", | |
11414 | bpp, connector->base.display_info.bpc*3); | |
11415 | pipe_config->pipe_bpp = connector->base.display_info.bpc*3; | |
11416 | } | |
11417 | ||
11418 | /* Clamp bpp to 8 on screens without EDID 1.4 */ | |
11419 | if (connector->base.display_info.bpc == 0 && bpp > 24) { | |
11420 | DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n", | |
11421 | bpp); | |
11422 | pipe_config->pipe_bpp = 24; | |
11423 | } | |
11424 | } | |
11425 | ||
4e53c2e0 | 11426 | static int |
050f7aeb | 11427 | compute_baseline_pipe_bpp(struct intel_crtc *crtc, |
5cec258b | 11428 | struct intel_crtc_state *pipe_config) |
4e53c2e0 | 11429 | { |
050f7aeb | 11430 | struct drm_device *dev = crtc->base.dev; |
1486017f | 11431 | struct drm_atomic_state *state; |
da3ced29 ACO |
11432 | struct drm_connector *connector; |
11433 | struct drm_connector_state *connector_state; | |
1486017f | 11434 | int bpp, i; |
4e53c2e0 | 11435 | |
d328c9d7 | 11436 | if ((IS_G4X(dev) || IS_VALLEYVIEW(dev))) |
4e53c2e0 | 11437 | bpp = 10*3; |
d328c9d7 DV |
11438 | else if (INTEL_INFO(dev)->gen >= 5) |
11439 | bpp = 12*3; | |
11440 | else | |
11441 | bpp = 8*3; | |
11442 | ||
4e53c2e0 | 11443 | |
4e53c2e0 DV |
11444 | pipe_config->pipe_bpp = bpp; |
11445 | ||
1486017f ACO |
11446 | state = pipe_config->base.state; |
11447 | ||
4e53c2e0 | 11448 | /* Clamp display bpp to EDID value */ |
da3ced29 ACO |
11449 | for_each_connector_in_state(state, connector, connector_state, i) { |
11450 | if (connector_state->crtc != &crtc->base) | |
4e53c2e0 DV |
11451 | continue; |
11452 | ||
da3ced29 ACO |
11453 | connected_sink_compute_bpp(to_intel_connector(connector), |
11454 | pipe_config); | |
4e53c2e0 DV |
11455 | } |
11456 | ||
11457 | return bpp; | |
11458 | } | |
11459 | ||
644db711 DV |
11460 | static void intel_dump_crtc_timings(const struct drm_display_mode *mode) |
11461 | { | |
11462 | DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, " | |
11463 | "type: 0x%x flags: 0x%x\n", | |
1342830c | 11464 | mode->crtc_clock, |
644db711 DV |
11465 | mode->crtc_hdisplay, mode->crtc_hsync_start, |
11466 | mode->crtc_hsync_end, mode->crtc_htotal, | |
11467 | mode->crtc_vdisplay, mode->crtc_vsync_start, | |
11468 | mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags); | |
11469 | } | |
11470 | ||
c0b03411 | 11471 | static void intel_dump_pipe_config(struct intel_crtc *crtc, |
5cec258b | 11472 | struct intel_crtc_state *pipe_config, |
c0b03411 DV |
11473 | const char *context) |
11474 | { | |
6a60cd87 CK |
11475 | struct drm_device *dev = crtc->base.dev; |
11476 | struct drm_plane *plane; | |
11477 | struct intel_plane *intel_plane; | |
11478 | struct intel_plane_state *state; | |
11479 | struct drm_framebuffer *fb; | |
11480 | ||
11481 | DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id, | |
11482 | context, pipe_config, pipe_name(crtc->pipe)); | |
c0b03411 DV |
11483 | |
11484 | DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder)); | |
11485 | DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n", | |
11486 | pipe_config->pipe_bpp, pipe_config->dither); | |
11487 | DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", | |
11488 | pipe_config->has_pch_encoder, | |
11489 | pipe_config->fdi_lanes, | |
11490 | pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n, | |
11491 | pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n, | |
11492 | pipe_config->fdi_m_n.tu); | |
eb14cb74 VS |
11493 | DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", |
11494 | pipe_config->has_dp_encoder, | |
11495 | pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n, | |
11496 | pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n, | |
11497 | pipe_config->dp_m_n.tu); | |
b95af8be VK |
11498 | |
11499 | DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n", | |
11500 | pipe_config->has_dp_encoder, | |
11501 | pipe_config->dp_m2_n2.gmch_m, | |
11502 | pipe_config->dp_m2_n2.gmch_n, | |
11503 | pipe_config->dp_m2_n2.link_m, | |
11504 | pipe_config->dp_m2_n2.link_n, | |
11505 | pipe_config->dp_m2_n2.tu); | |
11506 | ||
55072d19 DV |
11507 | DRM_DEBUG_KMS("audio: %i, infoframes: %i\n", |
11508 | pipe_config->has_audio, | |
11509 | pipe_config->has_infoframe); | |
11510 | ||
c0b03411 | 11511 | DRM_DEBUG_KMS("requested mode:\n"); |
2d112de7 | 11512 | drm_mode_debug_printmodeline(&pipe_config->base.mode); |
c0b03411 | 11513 | DRM_DEBUG_KMS("adjusted mode:\n"); |
2d112de7 ACO |
11514 | drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode); |
11515 | intel_dump_crtc_timings(&pipe_config->base.adjusted_mode); | |
d71b8d4a | 11516 | DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock); |
37327abd VS |
11517 | DRM_DEBUG_KMS("pipe src size: %dx%d\n", |
11518 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); | |
0ec463d3 TU |
11519 | DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n", |
11520 | crtc->num_scalers, | |
11521 | pipe_config->scaler_state.scaler_users, | |
11522 | pipe_config->scaler_state.scaler_id); | |
c0b03411 DV |
11523 | DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", |
11524 | pipe_config->gmch_pfit.control, | |
11525 | pipe_config->gmch_pfit.pgm_ratios, | |
11526 | pipe_config->gmch_pfit.lvds_border_bits); | |
fd4daa9c | 11527 | DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n", |
c0b03411 | 11528 | pipe_config->pch_pfit.pos, |
fd4daa9c CW |
11529 | pipe_config->pch_pfit.size, |
11530 | pipe_config->pch_pfit.enabled ? "enabled" : "disabled"); | |
42db64ef | 11531 | DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled); |
cf532bb2 | 11532 | DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide); |
6a60cd87 | 11533 | |
415ff0f6 TU |
11534 | if (IS_BROXTON(dev)) { |
11535 | DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, " | |
11536 | "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, " | |
11537 | "pll6: 0x%x, pll8: 0x%x, pcsdw12: 0x%x\n", | |
11538 | pipe_config->ddi_pll_sel, | |
11539 | pipe_config->dpll_hw_state.ebb0, | |
11540 | pipe_config->dpll_hw_state.pll0, | |
11541 | pipe_config->dpll_hw_state.pll1, | |
11542 | pipe_config->dpll_hw_state.pll2, | |
11543 | pipe_config->dpll_hw_state.pll3, | |
11544 | pipe_config->dpll_hw_state.pll6, | |
11545 | pipe_config->dpll_hw_state.pll8, | |
11546 | pipe_config->dpll_hw_state.pcsdw12); | |
11547 | } else if (IS_SKYLAKE(dev)) { | |
11548 | DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: " | |
11549 | "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n", | |
11550 | pipe_config->ddi_pll_sel, | |
11551 | pipe_config->dpll_hw_state.ctrl1, | |
11552 | pipe_config->dpll_hw_state.cfgcr1, | |
11553 | pipe_config->dpll_hw_state.cfgcr2); | |
11554 | } else if (HAS_DDI(dev)) { | |
11555 | DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x\n", | |
11556 | pipe_config->ddi_pll_sel, | |
11557 | pipe_config->dpll_hw_state.wrpll); | |
11558 | } else { | |
11559 | DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, " | |
11560 | "fp0: 0x%x, fp1: 0x%x\n", | |
11561 | pipe_config->dpll_hw_state.dpll, | |
11562 | pipe_config->dpll_hw_state.dpll_md, | |
11563 | pipe_config->dpll_hw_state.fp0, | |
11564 | pipe_config->dpll_hw_state.fp1); | |
11565 | } | |
11566 | ||
6a60cd87 CK |
11567 | DRM_DEBUG_KMS("planes on this crtc\n"); |
11568 | list_for_each_entry(plane, &dev->mode_config.plane_list, head) { | |
11569 | intel_plane = to_intel_plane(plane); | |
11570 | if (intel_plane->pipe != crtc->pipe) | |
11571 | continue; | |
11572 | ||
11573 | state = to_intel_plane_state(plane->state); | |
11574 | fb = state->base.fb; | |
11575 | if (!fb) { | |
11576 | DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d " | |
11577 | "disabled, scaler_id = %d\n", | |
11578 | plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD", | |
11579 | plane->base.id, intel_plane->pipe, | |
11580 | (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1, | |
11581 | drm_plane_index(plane), state->scaler_id); | |
11582 | continue; | |
11583 | } | |
11584 | ||
11585 | DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled", | |
11586 | plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD", | |
11587 | plane->base.id, intel_plane->pipe, | |
11588 | crtc->base.primary == plane ? 0 : intel_plane->plane + 1, | |
11589 | drm_plane_index(plane)); | |
11590 | DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x", | |
11591 | fb->base.id, fb->width, fb->height, fb->pixel_format); | |
11592 | DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n", | |
11593 | state->scaler_id, | |
11594 | state->src.x1 >> 16, state->src.y1 >> 16, | |
11595 | drm_rect_width(&state->src) >> 16, | |
11596 | drm_rect_height(&state->src) >> 16, | |
11597 | state->dst.x1, state->dst.y1, | |
11598 | drm_rect_width(&state->dst), drm_rect_height(&state->dst)); | |
11599 | } | |
c0b03411 DV |
11600 | } |
11601 | ||
bc079e8b VS |
11602 | static bool encoders_cloneable(const struct intel_encoder *a, |
11603 | const struct intel_encoder *b) | |
accfc0c5 | 11604 | { |
bc079e8b VS |
11605 | /* masks could be asymmetric, so check both ways */ |
11606 | return a == b || (a->cloneable & (1 << b->type) && | |
11607 | b->cloneable & (1 << a->type)); | |
11608 | } | |
11609 | ||
98a221da ACO |
11610 | static bool check_single_encoder_cloning(struct drm_atomic_state *state, |
11611 | struct intel_crtc *crtc, | |
bc079e8b VS |
11612 | struct intel_encoder *encoder) |
11613 | { | |
bc079e8b | 11614 | struct intel_encoder *source_encoder; |
da3ced29 | 11615 | struct drm_connector *connector; |
98a221da ACO |
11616 | struct drm_connector_state *connector_state; |
11617 | int i; | |
bc079e8b | 11618 | |
da3ced29 | 11619 | for_each_connector_in_state(state, connector, connector_state, i) { |
98a221da | 11620 | if (connector_state->crtc != &crtc->base) |
bc079e8b VS |
11621 | continue; |
11622 | ||
98a221da ACO |
11623 | source_encoder = |
11624 | to_intel_encoder(connector_state->best_encoder); | |
bc079e8b VS |
11625 | if (!encoders_cloneable(encoder, source_encoder)) |
11626 | return false; | |
11627 | } | |
11628 | ||
11629 | return true; | |
11630 | } | |
11631 | ||
98a221da ACO |
11632 | static bool check_encoder_cloning(struct drm_atomic_state *state, |
11633 | struct intel_crtc *crtc) | |
bc079e8b | 11634 | { |
accfc0c5 | 11635 | struct intel_encoder *encoder; |
da3ced29 | 11636 | struct drm_connector *connector; |
98a221da ACO |
11637 | struct drm_connector_state *connector_state; |
11638 | int i; | |
accfc0c5 | 11639 | |
da3ced29 | 11640 | for_each_connector_in_state(state, connector, connector_state, i) { |
98a221da ACO |
11641 | if (connector_state->crtc != &crtc->base) |
11642 | continue; | |
11643 | ||
11644 | encoder = to_intel_encoder(connector_state->best_encoder); | |
11645 | if (!check_single_encoder_cloning(state, crtc, encoder)) | |
bc079e8b | 11646 | return false; |
accfc0c5 DV |
11647 | } |
11648 | ||
bc079e8b | 11649 | return true; |
accfc0c5 DV |
11650 | } |
11651 | ||
5448a00d | 11652 | static bool check_digital_port_conflicts(struct drm_atomic_state *state) |
00f0b378 | 11653 | { |
5448a00d ACO |
11654 | struct drm_device *dev = state->dev; |
11655 | struct intel_encoder *encoder; | |
da3ced29 | 11656 | struct drm_connector *connector; |
5448a00d | 11657 | struct drm_connector_state *connector_state; |
00f0b378 | 11658 | unsigned int used_ports = 0; |
5448a00d | 11659 | int i; |
00f0b378 VS |
11660 | |
11661 | /* | |
11662 | * Walk the connector list instead of the encoder | |
11663 | * list to detect the problem on ddi platforms | |
11664 | * where there's just one encoder per digital port. | |
11665 | */ | |
da3ced29 | 11666 | for_each_connector_in_state(state, connector, connector_state, i) { |
5448a00d | 11667 | if (!connector_state->best_encoder) |
00f0b378 VS |
11668 | continue; |
11669 | ||
5448a00d ACO |
11670 | encoder = to_intel_encoder(connector_state->best_encoder); |
11671 | ||
11672 | WARN_ON(!connector_state->crtc); | |
00f0b378 VS |
11673 | |
11674 | switch (encoder->type) { | |
11675 | unsigned int port_mask; | |
11676 | case INTEL_OUTPUT_UNKNOWN: | |
11677 | if (WARN_ON(!HAS_DDI(dev))) | |
11678 | break; | |
11679 | case INTEL_OUTPUT_DISPLAYPORT: | |
11680 | case INTEL_OUTPUT_HDMI: | |
11681 | case INTEL_OUTPUT_EDP: | |
11682 | port_mask = 1 << enc_to_dig_port(&encoder->base)->port; | |
11683 | ||
11684 | /* the same port mustn't appear more than once */ | |
11685 | if (used_ports & port_mask) | |
11686 | return false; | |
11687 | ||
11688 | used_ports |= port_mask; | |
11689 | default: | |
11690 | break; | |
11691 | } | |
11692 | } | |
11693 | ||
11694 | return true; | |
11695 | } | |
11696 | ||
83a57153 ACO |
11697 | static void |
11698 | clear_intel_crtc_state(struct intel_crtc_state *crtc_state) | |
11699 | { | |
11700 | struct drm_crtc_state tmp_state; | |
663a3640 | 11701 | struct intel_crtc_scaler_state scaler_state; |
4978cc93 ACO |
11702 | struct intel_dpll_hw_state dpll_hw_state; |
11703 | enum intel_dpll_id shared_dpll; | |
8504c74c | 11704 | uint32_t ddi_pll_sel; |
83a57153 | 11705 | |
7546a384 ACO |
11706 | /* FIXME: before the switch to atomic started, a new pipe_config was |
11707 | * kzalloc'd. Code that depends on any field being zero should be | |
11708 | * fixed, so that the crtc_state can be safely duplicated. For now, | |
11709 | * only fields that are know to not cause problems are preserved. */ | |
11710 | ||
83a57153 | 11711 | tmp_state = crtc_state->base; |
663a3640 | 11712 | scaler_state = crtc_state->scaler_state; |
4978cc93 ACO |
11713 | shared_dpll = crtc_state->shared_dpll; |
11714 | dpll_hw_state = crtc_state->dpll_hw_state; | |
8504c74c | 11715 | ddi_pll_sel = crtc_state->ddi_pll_sel; |
4978cc93 | 11716 | |
83a57153 | 11717 | memset(crtc_state, 0, sizeof *crtc_state); |
4978cc93 | 11718 | |
83a57153 | 11719 | crtc_state->base = tmp_state; |
663a3640 | 11720 | crtc_state->scaler_state = scaler_state; |
4978cc93 ACO |
11721 | crtc_state->shared_dpll = shared_dpll; |
11722 | crtc_state->dpll_hw_state = dpll_hw_state; | |
8504c74c | 11723 | crtc_state->ddi_pll_sel = ddi_pll_sel; |
83a57153 ACO |
11724 | } |
11725 | ||
548ee15b | 11726 | static int |
b8cecdf5 | 11727 | intel_modeset_pipe_config(struct drm_crtc *crtc, |
548ee15b ACO |
11728 | struct drm_atomic_state *state, |
11729 | struct intel_crtc_state *pipe_config) | |
ee7b9f93 | 11730 | { |
7758a113 | 11731 | struct intel_encoder *encoder; |
da3ced29 | 11732 | struct drm_connector *connector; |
0b901879 | 11733 | struct drm_connector_state *connector_state; |
d328c9d7 | 11734 | int base_bpp, ret = -EINVAL; |
0b901879 | 11735 | int i; |
e29c22c0 | 11736 | bool retry = true; |
ee7b9f93 | 11737 | |
98a221da | 11738 | if (!check_encoder_cloning(state, to_intel_crtc(crtc))) { |
accfc0c5 | 11739 | DRM_DEBUG_KMS("rejecting invalid cloning configuration\n"); |
548ee15b | 11740 | return -EINVAL; |
accfc0c5 DV |
11741 | } |
11742 | ||
5448a00d | 11743 | if (!check_digital_port_conflicts(state)) { |
00f0b378 | 11744 | DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n"); |
548ee15b | 11745 | return -EINVAL; |
00f0b378 VS |
11746 | } |
11747 | ||
83a57153 | 11748 | clear_intel_crtc_state(pipe_config); |
7758a113 | 11749 | |
e143a21c DV |
11750 | pipe_config->cpu_transcoder = |
11751 | (enum transcoder) to_intel_crtc(crtc)->pipe; | |
b8cecdf5 | 11752 | |
2960bc9c ID |
11753 | /* |
11754 | * Sanitize sync polarity flags based on requested ones. If neither | |
11755 | * positive or negative polarity is requested, treat this as meaning | |
11756 | * negative polarity. | |
11757 | */ | |
2d112de7 | 11758 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 11759 | (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) |
2d112de7 | 11760 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; |
2960bc9c | 11761 | |
2d112de7 | 11762 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 11763 | (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) |
2d112de7 | 11764 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; |
2960bc9c | 11765 | |
050f7aeb DV |
11766 | /* Compute a starting value for pipe_config->pipe_bpp taking the source |
11767 | * plane pixel format and any sink constraints into account. Returns the | |
11768 | * source plane bpp so that dithering can be selected on mismatches | |
11769 | * after encoders and crtc also have had their say. */ | |
d328c9d7 DV |
11770 | base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc), |
11771 | pipe_config); | |
11772 | if (base_bpp < 0) | |
4e53c2e0 DV |
11773 | goto fail; |
11774 | ||
e41a56be VS |
11775 | /* |
11776 | * Determine the real pipe dimensions. Note that stereo modes can | |
11777 | * increase the actual pipe size due to the frame doubling and | |
11778 | * insertion of additional space for blanks between the frame. This | |
11779 | * is stored in the crtc timings. We use the requested mode to do this | |
11780 | * computation to clearly distinguish it from the adjusted mode, which | |
11781 | * can be changed by the connectors in the below retry loop. | |
11782 | */ | |
2d112de7 | 11783 | drm_crtc_get_hv_timing(&pipe_config->base.mode, |
ecb7e16b GP |
11784 | &pipe_config->pipe_src_w, |
11785 | &pipe_config->pipe_src_h); | |
e41a56be | 11786 | |
e29c22c0 | 11787 | encoder_retry: |
ef1b460d | 11788 | /* Ensure the port clock defaults are reset when retrying. */ |
ff9a6750 | 11789 | pipe_config->port_clock = 0; |
ef1b460d | 11790 | pipe_config->pixel_multiplier = 1; |
ff9a6750 | 11791 | |
135c81b8 | 11792 | /* Fill in default crtc timings, allow encoders to overwrite them. */ |
2d112de7 ACO |
11793 | drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode, |
11794 | CRTC_STEREO_DOUBLE); | |
135c81b8 | 11795 | |
7758a113 DV |
11796 | /* Pass our mode to the connectors and the CRTC to give them a chance to |
11797 | * adjust it according to limitations or connector properties, and also | |
11798 | * a chance to reject the mode entirely. | |
47f1c6c9 | 11799 | */ |
da3ced29 | 11800 | for_each_connector_in_state(state, connector, connector_state, i) { |
0b901879 | 11801 | if (connector_state->crtc != crtc) |
7758a113 | 11802 | continue; |
7ae89233 | 11803 | |
0b901879 ACO |
11804 | encoder = to_intel_encoder(connector_state->best_encoder); |
11805 | ||
efea6e8e DV |
11806 | if (!(encoder->compute_config(encoder, pipe_config))) { |
11807 | DRM_DEBUG_KMS("Encoder config failure\n"); | |
7758a113 DV |
11808 | goto fail; |
11809 | } | |
ee7b9f93 | 11810 | } |
47f1c6c9 | 11811 | |
ff9a6750 DV |
11812 | /* Set default port clock if not overwritten by the encoder. Needs to be |
11813 | * done afterwards in case the encoder adjusts the mode. */ | |
11814 | if (!pipe_config->port_clock) | |
2d112de7 | 11815 | pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock |
241bfc38 | 11816 | * pipe_config->pixel_multiplier; |
ff9a6750 | 11817 | |
a43f6e0f | 11818 | ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); |
e29c22c0 | 11819 | if (ret < 0) { |
7758a113 DV |
11820 | DRM_DEBUG_KMS("CRTC fixup failed\n"); |
11821 | goto fail; | |
ee7b9f93 | 11822 | } |
e29c22c0 DV |
11823 | |
11824 | if (ret == RETRY) { | |
11825 | if (WARN(!retry, "loop in pipe configuration computation\n")) { | |
11826 | ret = -EINVAL; | |
11827 | goto fail; | |
11828 | } | |
11829 | ||
11830 | DRM_DEBUG_KMS("CRTC bw constrained, retrying\n"); | |
11831 | retry = false; | |
11832 | goto encoder_retry; | |
11833 | } | |
11834 | ||
d328c9d7 | 11835 | pipe_config->dither = pipe_config->pipe_bpp != base_bpp; |
4e53c2e0 | 11836 | DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n", |
d328c9d7 | 11837 | base_bpp, pipe_config->pipe_bpp, pipe_config->dither); |
4e53c2e0 | 11838 | |
548ee15b | 11839 | return 0; |
7758a113 | 11840 | fail: |
548ee15b | 11841 | return ret; |
ee7b9f93 | 11842 | } |
47f1c6c9 | 11843 | |
ea9d758d | 11844 | static bool intel_crtc_in_use(struct drm_crtc *crtc) |
f6e5b160 | 11845 | { |
ea9d758d | 11846 | struct drm_encoder *encoder; |
f6e5b160 | 11847 | struct drm_device *dev = crtc->dev; |
f6e5b160 | 11848 | |
ea9d758d DV |
11849 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) |
11850 | if (encoder->crtc == crtc) | |
11851 | return true; | |
11852 | ||
11853 | return false; | |
11854 | } | |
11855 | ||
0a9ab303 ACO |
11856 | static bool |
11857 | needs_modeset(struct drm_crtc_state *state) | |
11858 | { | |
11859 | return state->mode_changed || state->active_changed; | |
11860 | } | |
11861 | ||
ea9d758d | 11862 | static void |
0a9ab303 | 11863 | intel_modeset_update_state(struct drm_atomic_state *state) |
ea9d758d | 11864 | { |
0a9ab303 | 11865 | struct drm_device *dev = state->dev; |
ba41c0de | 11866 | struct drm_i915_private *dev_priv = dev->dev_private; |
ea9d758d | 11867 | struct intel_encoder *intel_encoder; |
0a9ab303 ACO |
11868 | struct drm_crtc *crtc; |
11869 | struct drm_crtc_state *crtc_state; | |
ea9d758d | 11870 | struct drm_connector *connector; |
0a9ab303 | 11871 | int i; |
ea9d758d | 11872 | |
ba41c0de DV |
11873 | intel_shared_dpll_commit(dev_priv); |
11874 | ||
b2784e15 | 11875 | for_each_intel_encoder(dev, intel_encoder) { |
ea9d758d DV |
11876 | if (!intel_encoder->base.crtc) |
11877 | continue; | |
11878 | ||
0a9ab303 ACO |
11879 | for_each_crtc_in_state(state, crtc, crtc_state, i) |
11880 | if (crtc == intel_encoder->base.crtc) | |
11881 | break; | |
11882 | ||
11883 | if (crtc != intel_encoder->base.crtc) | |
11884 | continue; | |
ea9d758d | 11885 | |
0a9ab303 | 11886 | if (crtc_state->enable && needs_modeset(crtc_state)) |
ea9d758d DV |
11887 | intel_encoder->connectors_active = false; |
11888 | } | |
11889 | ||
a821fc46 ACO |
11890 | drm_atomic_helper_swap_state(state->dev, state); |
11891 | intel_modeset_fixup_state(state); | |
ea9d758d | 11892 | |
7668851f | 11893 | /* Double check state. */ |
0a9ab303 ACO |
11894 | for_each_crtc(dev, crtc) { |
11895 | WARN_ON(crtc->state->enable != intel_crtc_in_use(crtc)); | |
ea9d758d DV |
11896 | } |
11897 | ||
11898 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
11899 | if (!connector->encoder || !connector->encoder->crtc) | |
11900 | continue; | |
11901 | ||
0a9ab303 ACO |
11902 | for_each_crtc_in_state(state, crtc, crtc_state, i) |
11903 | if (crtc == connector->encoder->crtc) | |
11904 | break; | |
11905 | ||
11906 | if (crtc != connector->encoder->crtc) | |
11907 | continue; | |
ea9d758d | 11908 | |
a821fc46 | 11909 | if (crtc->state->enable && needs_modeset(crtc->state)) { |
68d34720 DV |
11910 | struct drm_property *dpms_property = |
11911 | dev->mode_config.dpms_property; | |
11912 | ||
ea9d758d | 11913 | connector->dpms = DRM_MODE_DPMS_ON; |
662595df | 11914 | drm_object_property_set_value(&connector->base, |
68d34720 DV |
11915 | dpms_property, |
11916 | DRM_MODE_DPMS_ON); | |
ea9d758d DV |
11917 | |
11918 | intel_encoder = to_intel_encoder(connector->encoder); | |
11919 | intel_encoder->connectors_active = true; | |
11920 | } | |
11921 | } | |
11922 | ||
11923 | } | |
11924 | ||
3bd26263 | 11925 | static bool intel_fuzzy_clock_check(int clock1, int clock2) |
f1f644dc | 11926 | { |
3bd26263 | 11927 | int diff; |
f1f644dc JB |
11928 | |
11929 | if (clock1 == clock2) | |
11930 | return true; | |
11931 | ||
11932 | if (!clock1 || !clock2) | |
11933 | return false; | |
11934 | ||
11935 | diff = abs(clock1 - clock2); | |
11936 | ||
11937 | if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) | |
11938 | return true; | |
11939 | ||
11940 | return false; | |
11941 | } | |
11942 | ||
25c5b266 DV |
11943 | #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \ |
11944 | list_for_each_entry((intel_crtc), \ | |
11945 | &(dev)->mode_config.crtc_list, \ | |
11946 | base.head) \ | |
0973f18f | 11947 | if (mask & (1 <<(intel_crtc)->pipe)) |
25c5b266 | 11948 | |
0e8ffe1b | 11949 | static bool |
2fa2fe9a | 11950 | intel_pipe_config_compare(struct drm_device *dev, |
5cec258b ACO |
11951 | struct intel_crtc_state *current_config, |
11952 | struct intel_crtc_state *pipe_config) | |
0e8ffe1b | 11953 | { |
66e985c0 DV |
11954 | #define PIPE_CONF_CHECK_X(name) \ |
11955 | if (current_config->name != pipe_config->name) { \ | |
11956 | DRM_ERROR("mismatch in " #name " " \ | |
11957 | "(expected 0x%08x, found 0x%08x)\n", \ | |
11958 | current_config->name, \ | |
11959 | pipe_config->name); \ | |
11960 | return false; \ | |
11961 | } | |
11962 | ||
08a24034 DV |
11963 | #define PIPE_CONF_CHECK_I(name) \ |
11964 | if (current_config->name != pipe_config->name) { \ | |
11965 | DRM_ERROR("mismatch in " #name " " \ | |
11966 | "(expected %i, found %i)\n", \ | |
11967 | current_config->name, \ | |
11968 | pipe_config->name); \ | |
11969 | return false; \ | |
88adfff1 DV |
11970 | } |
11971 | ||
b95af8be VK |
11972 | /* This is required for BDW+ where there is only one set of registers for |
11973 | * switching between high and low RR. | |
11974 | * This macro can be used whenever a comparison has to be made between one | |
11975 | * hw state and multiple sw state variables. | |
11976 | */ | |
11977 | #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \ | |
11978 | if ((current_config->name != pipe_config->name) && \ | |
11979 | (current_config->alt_name != pipe_config->name)) { \ | |
11980 | DRM_ERROR("mismatch in " #name " " \ | |
11981 | "(expected %i or %i, found %i)\n", \ | |
11982 | current_config->name, \ | |
11983 | current_config->alt_name, \ | |
11984 | pipe_config->name); \ | |
11985 | return false; \ | |
11986 | } | |
11987 | ||
1bd1bd80 DV |
11988 | #define PIPE_CONF_CHECK_FLAGS(name, mask) \ |
11989 | if ((current_config->name ^ pipe_config->name) & (mask)) { \ | |
6f02488e | 11990 | DRM_ERROR("mismatch in " #name "(" #mask ") " \ |
1bd1bd80 DV |
11991 | "(expected %i, found %i)\n", \ |
11992 | current_config->name & (mask), \ | |
11993 | pipe_config->name & (mask)); \ | |
11994 | return false; \ | |
11995 | } | |
11996 | ||
5e550656 VS |
11997 | #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \ |
11998 | if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \ | |
11999 | DRM_ERROR("mismatch in " #name " " \ | |
12000 | "(expected %i, found %i)\n", \ | |
12001 | current_config->name, \ | |
12002 | pipe_config->name); \ | |
12003 | return false; \ | |
12004 | } | |
12005 | ||
bb760063 DV |
12006 | #define PIPE_CONF_QUIRK(quirk) \ |
12007 | ((current_config->quirks | pipe_config->quirks) & (quirk)) | |
12008 | ||
eccb140b DV |
12009 | PIPE_CONF_CHECK_I(cpu_transcoder); |
12010 | ||
08a24034 DV |
12011 | PIPE_CONF_CHECK_I(has_pch_encoder); |
12012 | PIPE_CONF_CHECK_I(fdi_lanes); | |
72419203 DV |
12013 | PIPE_CONF_CHECK_I(fdi_m_n.gmch_m); |
12014 | PIPE_CONF_CHECK_I(fdi_m_n.gmch_n); | |
12015 | PIPE_CONF_CHECK_I(fdi_m_n.link_m); | |
12016 | PIPE_CONF_CHECK_I(fdi_m_n.link_n); | |
12017 | PIPE_CONF_CHECK_I(fdi_m_n.tu); | |
08a24034 | 12018 | |
eb14cb74 | 12019 | PIPE_CONF_CHECK_I(has_dp_encoder); |
b95af8be VK |
12020 | |
12021 | if (INTEL_INFO(dev)->gen < 8) { | |
12022 | PIPE_CONF_CHECK_I(dp_m_n.gmch_m); | |
12023 | PIPE_CONF_CHECK_I(dp_m_n.gmch_n); | |
12024 | PIPE_CONF_CHECK_I(dp_m_n.link_m); | |
12025 | PIPE_CONF_CHECK_I(dp_m_n.link_n); | |
12026 | PIPE_CONF_CHECK_I(dp_m_n.tu); | |
12027 | ||
12028 | if (current_config->has_drrs) { | |
12029 | PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m); | |
12030 | PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n); | |
12031 | PIPE_CONF_CHECK_I(dp_m2_n2.link_m); | |
12032 | PIPE_CONF_CHECK_I(dp_m2_n2.link_n); | |
12033 | PIPE_CONF_CHECK_I(dp_m2_n2.tu); | |
12034 | } | |
12035 | } else { | |
12036 | PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m); | |
12037 | PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n); | |
12038 | PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m); | |
12039 | PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n); | |
12040 | PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu); | |
12041 | } | |
eb14cb74 | 12042 | |
2d112de7 ACO |
12043 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay); |
12044 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal); | |
12045 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start); | |
12046 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end); | |
12047 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start); | |
12048 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end); | |
1bd1bd80 | 12049 | |
2d112de7 ACO |
12050 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay); |
12051 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal); | |
12052 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start); | |
12053 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end); | |
12054 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start); | |
12055 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end); | |
1bd1bd80 | 12056 | |
c93f54cf | 12057 | PIPE_CONF_CHECK_I(pixel_multiplier); |
6897b4b5 | 12058 | PIPE_CONF_CHECK_I(has_hdmi_sink); |
b5a9fa09 DV |
12059 | if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) || |
12060 | IS_VALLEYVIEW(dev)) | |
12061 | PIPE_CONF_CHECK_I(limited_color_range); | |
e43823ec | 12062 | PIPE_CONF_CHECK_I(has_infoframe); |
6c49f241 | 12063 | |
9ed109a7 DV |
12064 | PIPE_CONF_CHECK_I(has_audio); |
12065 | ||
2d112de7 | 12066 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
1bd1bd80 DV |
12067 | DRM_MODE_FLAG_INTERLACE); |
12068 | ||
bb760063 | 12069 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { |
2d112de7 | 12070 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 12071 | DRM_MODE_FLAG_PHSYNC); |
2d112de7 | 12072 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 12073 | DRM_MODE_FLAG_NHSYNC); |
2d112de7 | 12074 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 12075 | DRM_MODE_FLAG_PVSYNC); |
2d112de7 | 12076 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 DV |
12077 | DRM_MODE_FLAG_NVSYNC); |
12078 | } | |
045ac3b5 | 12079 | |
37327abd VS |
12080 | PIPE_CONF_CHECK_I(pipe_src_w); |
12081 | PIPE_CONF_CHECK_I(pipe_src_h); | |
1bd1bd80 | 12082 | |
9953599b DV |
12083 | /* |
12084 | * FIXME: BIOS likes to set up a cloned config with lvds+external | |
12085 | * screen. Since we don't yet re-compute the pipe config when moving | |
12086 | * just the lvds port away to another pipe the sw tracking won't match. | |
12087 | * | |
12088 | * Proper atomic modesets with recomputed global state will fix this. | |
12089 | * Until then just don't check gmch state for inherited modes. | |
12090 | */ | |
12091 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) { | |
12092 | PIPE_CONF_CHECK_I(gmch_pfit.control); | |
12093 | /* pfit ratios are autocomputed by the hw on gen4+ */ | |
12094 | if (INTEL_INFO(dev)->gen < 4) | |
12095 | PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios); | |
12096 | PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits); | |
12097 | } | |
12098 | ||
fd4daa9c CW |
12099 | PIPE_CONF_CHECK_I(pch_pfit.enabled); |
12100 | if (current_config->pch_pfit.enabled) { | |
12101 | PIPE_CONF_CHECK_I(pch_pfit.pos); | |
12102 | PIPE_CONF_CHECK_I(pch_pfit.size); | |
12103 | } | |
2fa2fe9a | 12104 | |
a1b2278e CK |
12105 | PIPE_CONF_CHECK_I(scaler_state.scaler_id); |
12106 | ||
e59150dc JB |
12107 | /* BDW+ don't expose a synchronous way to read the state */ |
12108 | if (IS_HASWELL(dev)) | |
12109 | PIPE_CONF_CHECK_I(ips_enabled); | |
42db64ef | 12110 | |
282740f7 VS |
12111 | PIPE_CONF_CHECK_I(double_wide); |
12112 | ||
26804afd DV |
12113 | PIPE_CONF_CHECK_X(ddi_pll_sel); |
12114 | ||
c0d43d62 | 12115 | PIPE_CONF_CHECK_I(shared_dpll); |
66e985c0 | 12116 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll); |
8bcc2795 | 12117 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); |
66e985c0 DV |
12118 | PIPE_CONF_CHECK_X(dpll_hw_state.fp0); |
12119 | PIPE_CONF_CHECK_X(dpll_hw_state.fp1); | |
d452c5b6 | 12120 | PIPE_CONF_CHECK_X(dpll_hw_state.wrpll); |
3f4cd19f DL |
12121 | PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1); |
12122 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1); | |
12123 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2); | |
c0d43d62 | 12124 | |
42571aef VS |
12125 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) |
12126 | PIPE_CONF_CHECK_I(pipe_bpp); | |
12127 | ||
2d112de7 | 12128 | PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock); |
a9a7e98a | 12129 | PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); |
5e550656 | 12130 | |
66e985c0 | 12131 | #undef PIPE_CONF_CHECK_X |
08a24034 | 12132 | #undef PIPE_CONF_CHECK_I |
b95af8be | 12133 | #undef PIPE_CONF_CHECK_I_ALT |
1bd1bd80 | 12134 | #undef PIPE_CONF_CHECK_FLAGS |
5e550656 | 12135 | #undef PIPE_CONF_CHECK_CLOCK_FUZZY |
bb760063 | 12136 | #undef PIPE_CONF_QUIRK |
88adfff1 | 12137 | |
0e8ffe1b DV |
12138 | return true; |
12139 | } | |
12140 | ||
08db6652 DL |
12141 | static void check_wm_state(struct drm_device *dev) |
12142 | { | |
12143 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12144 | struct skl_ddb_allocation hw_ddb, *sw_ddb; | |
12145 | struct intel_crtc *intel_crtc; | |
12146 | int plane; | |
12147 | ||
12148 | if (INTEL_INFO(dev)->gen < 9) | |
12149 | return; | |
12150 | ||
12151 | skl_ddb_get_hw_state(dev_priv, &hw_ddb); | |
12152 | sw_ddb = &dev_priv->wm.skl_hw.ddb; | |
12153 | ||
12154 | for_each_intel_crtc(dev, intel_crtc) { | |
12155 | struct skl_ddb_entry *hw_entry, *sw_entry; | |
12156 | const enum pipe pipe = intel_crtc->pipe; | |
12157 | ||
12158 | if (!intel_crtc->active) | |
12159 | continue; | |
12160 | ||
12161 | /* planes */ | |
dd740780 | 12162 | for_each_plane(dev_priv, pipe, plane) { |
08db6652 DL |
12163 | hw_entry = &hw_ddb.plane[pipe][plane]; |
12164 | sw_entry = &sw_ddb->plane[pipe][plane]; | |
12165 | ||
12166 | if (skl_ddb_entry_equal(hw_entry, sw_entry)) | |
12167 | continue; | |
12168 | ||
12169 | DRM_ERROR("mismatch in DDB state pipe %c plane %d " | |
12170 | "(expected (%u,%u), found (%u,%u))\n", | |
12171 | pipe_name(pipe), plane + 1, | |
12172 | sw_entry->start, sw_entry->end, | |
12173 | hw_entry->start, hw_entry->end); | |
12174 | } | |
12175 | ||
12176 | /* cursor */ | |
12177 | hw_entry = &hw_ddb.cursor[pipe]; | |
12178 | sw_entry = &sw_ddb->cursor[pipe]; | |
12179 | ||
12180 | if (skl_ddb_entry_equal(hw_entry, sw_entry)) | |
12181 | continue; | |
12182 | ||
12183 | DRM_ERROR("mismatch in DDB state pipe %c cursor " | |
12184 | "(expected (%u,%u), found (%u,%u))\n", | |
12185 | pipe_name(pipe), | |
12186 | sw_entry->start, sw_entry->end, | |
12187 | hw_entry->start, hw_entry->end); | |
12188 | } | |
12189 | } | |
12190 | ||
91d1b4bd DV |
12191 | static void |
12192 | check_connector_state(struct drm_device *dev) | |
8af6cf88 | 12193 | { |
8af6cf88 DV |
12194 | struct intel_connector *connector; |
12195 | ||
3a3371ff | 12196 | for_each_intel_connector(dev, connector) { |
8af6cf88 DV |
12197 | /* This also checks the encoder/connector hw state with the |
12198 | * ->get_hw_state callbacks. */ | |
12199 | intel_connector_check_state(connector); | |
12200 | ||
e2c719b7 | 12201 | I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder, |
8af6cf88 DV |
12202 | "connector's staged encoder doesn't match current encoder\n"); |
12203 | } | |
91d1b4bd DV |
12204 | } |
12205 | ||
12206 | static void | |
12207 | check_encoder_state(struct drm_device *dev) | |
12208 | { | |
12209 | struct intel_encoder *encoder; | |
12210 | struct intel_connector *connector; | |
8af6cf88 | 12211 | |
b2784e15 | 12212 | for_each_intel_encoder(dev, encoder) { |
8af6cf88 DV |
12213 | bool enabled = false; |
12214 | bool active = false; | |
12215 | enum pipe pipe, tracked_pipe; | |
12216 | ||
12217 | DRM_DEBUG_KMS("[ENCODER:%d:%s]\n", | |
12218 | encoder->base.base.id, | |
8e329a03 | 12219 | encoder->base.name); |
8af6cf88 | 12220 | |
e2c719b7 | 12221 | I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc, |
8af6cf88 | 12222 | "encoder's stage crtc doesn't match current crtc\n"); |
e2c719b7 | 12223 | I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc, |
8af6cf88 DV |
12224 | "encoder's active_connectors set, but no crtc\n"); |
12225 | ||
3a3371ff | 12226 | for_each_intel_connector(dev, connector) { |
8af6cf88 DV |
12227 | if (connector->base.encoder != &encoder->base) |
12228 | continue; | |
12229 | enabled = true; | |
12230 | if (connector->base.dpms != DRM_MODE_DPMS_OFF) | |
12231 | active = true; | |
12232 | } | |
0e32b39c DA |
12233 | /* |
12234 | * for MST connectors if we unplug the connector is gone | |
12235 | * away but the encoder is still connected to a crtc | |
12236 | * until a modeset happens in response to the hotplug. | |
12237 | */ | |
12238 | if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST) | |
12239 | continue; | |
12240 | ||
e2c719b7 | 12241 | I915_STATE_WARN(!!encoder->base.crtc != enabled, |
8af6cf88 DV |
12242 | "encoder's enabled state mismatch " |
12243 | "(expected %i, found %i)\n", | |
12244 | !!encoder->base.crtc, enabled); | |
e2c719b7 | 12245 | I915_STATE_WARN(active && !encoder->base.crtc, |
8af6cf88 DV |
12246 | "active encoder with no crtc\n"); |
12247 | ||
e2c719b7 | 12248 | I915_STATE_WARN(encoder->connectors_active != active, |
8af6cf88 DV |
12249 | "encoder's computed active state doesn't match tracked active state " |
12250 | "(expected %i, found %i)\n", active, encoder->connectors_active); | |
12251 | ||
12252 | active = encoder->get_hw_state(encoder, &pipe); | |
e2c719b7 | 12253 | I915_STATE_WARN(active != encoder->connectors_active, |
8af6cf88 DV |
12254 | "encoder's hw state doesn't match sw tracking " |
12255 | "(expected %i, found %i)\n", | |
12256 | encoder->connectors_active, active); | |
12257 | ||
12258 | if (!encoder->base.crtc) | |
12259 | continue; | |
12260 | ||
12261 | tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe; | |
e2c719b7 | 12262 | I915_STATE_WARN(active && pipe != tracked_pipe, |
8af6cf88 DV |
12263 | "active encoder's pipe doesn't match" |
12264 | "(expected %i, found %i)\n", | |
12265 | tracked_pipe, pipe); | |
12266 | ||
12267 | } | |
91d1b4bd DV |
12268 | } |
12269 | ||
12270 | static void | |
12271 | check_crtc_state(struct drm_device *dev) | |
12272 | { | |
fbee40df | 12273 | struct drm_i915_private *dev_priv = dev->dev_private; |
91d1b4bd DV |
12274 | struct intel_crtc *crtc; |
12275 | struct intel_encoder *encoder; | |
5cec258b | 12276 | struct intel_crtc_state pipe_config; |
8af6cf88 | 12277 | |
d3fcc808 | 12278 | for_each_intel_crtc(dev, crtc) { |
8af6cf88 DV |
12279 | bool enabled = false; |
12280 | bool active = false; | |
12281 | ||
045ac3b5 JB |
12282 | memset(&pipe_config, 0, sizeof(pipe_config)); |
12283 | ||
8af6cf88 DV |
12284 | DRM_DEBUG_KMS("[CRTC:%d]\n", |
12285 | crtc->base.base.id); | |
12286 | ||
83d65738 | 12287 | I915_STATE_WARN(crtc->active && !crtc->base.state->enable, |
8af6cf88 DV |
12288 | "active crtc, but not enabled in sw tracking\n"); |
12289 | ||
b2784e15 | 12290 | for_each_intel_encoder(dev, encoder) { |
8af6cf88 DV |
12291 | if (encoder->base.crtc != &crtc->base) |
12292 | continue; | |
12293 | enabled = true; | |
12294 | if (encoder->connectors_active) | |
12295 | active = true; | |
12296 | } | |
6c49f241 | 12297 | |
e2c719b7 | 12298 | I915_STATE_WARN(active != crtc->active, |
8af6cf88 DV |
12299 | "crtc's computed active state doesn't match tracked active state " |
12300 | "(expected %i, found %i)\n", active, crtc->active); | |
83d65738 | 12301 | I915_STATE_WARN(enabled != crtc->base.state->enable, |
8af6cf88 | 12302 | "crtc's computed enabled state doesn't match tracked enabled state " |
83d65738 MR |
12303 | "(expected %i, found %i)\n", enabled, |
12304 | crtc->base.state->enable); | |
8af6cf88 | 12305 | |
0e8ffe1b DV |
12306 | active = dev_priv->display.get_pipe_config(crtc, |
12307 | &pipe_config); | |
d62cf62a | 12308 | |
b6b5d049 VS |
12309 | /* hw state is inconsistent with the pipe quirk */ |
12310 | if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
12311 | (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
d62cf62a DV |
12312 | active = crtc->active; |
12313 | ||
b2784e15 | 12314 | for_each_intel_encoder(dev, encoder) { |
3eaba51c | 12315 | enum pipe pipe; |
6c49f241 DV |
12316 | if (encoder->base.crtc != &crtc->base) |
12317 | continue; | |
1d37b689 | 12318 | if (encoder->get_hw_state(encoder, &pipe)) |
6c49f241 DV |
12319 | encoder->get_config(encoder, &pipe_config); |
12320 | } | |
12321 | ||
e2c719b7 | 12322 | I915_STATE_WARN(crtc->active != active, |
0e8ffe1b DV |
12323 | "crtc active state doesn't match with hw state " |
12324 | "(expected %i, found %i)\n", crtc->active, active); | |
12325 | ||
c0b03411 | 12326 | if (active && |
6e3c9717 | 12327 | !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) { |
e2c719b7 | 12328 | I915_STATE_WARN(1, "pipe state doesn't match!\n"); |
c0b03411 DV |
12329 | intel_dump_pipe_config(crtc, &pipe_config, |
12330 | "[hw state]"); | |
6e3c9717 | 12331 | intel_dump_pipe_config(crtc, crtc->config, |
c0b03411 DV |
12332 | "[sw state]"); |
12333 | } | |
8af6cf88 DV |
12334 | } |
12335 | } | |
12336 | ||
91d1b4bd DV |
12337 | static void |
12338 | check_shared_dpll_state(struct drm_device *dev) | |
12339 | { | |
fbee40df | 12340 | struct drm_i915_private *dev_priv = dev->dev_private; |
91d1b4bd DV |
12341 | struct intel_crtc *crtc; |
12342 | struct intel_dpll_hw_state dpll_hw_state; | |
12343 | int i; | |
5358901f DV |
12344 | |
12345 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
12346 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
12347 | int enabled_crtcs = 0, active_crtcs = 0; | |
12348 | bool active; | |
12349 | ||
12350 | memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); | |
12351 | ||
12352 | DRM_DEBUG_KMS("%s\n", pll->name); | |
12353 | ||
12354 | active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state); | |
12355 | ||
e2c719b7 | 12356 | I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask), |
5358901f | 12357 | "more active pll users than references: %i vs %i\n", |
3e369b76 | 12358 | pll->active, hweight32(pll->config.crtc_mask)); |
e2c719b7 | 12359 | I915_STATE_WARN(pll->active && !pll->on, |
5358901f | 12360 | "pll in active use but not on in sw tracking\n"); |
e2c719b7 | 12361 | I915_STATE_WARN(pll->on && !pll->active, |
35c95375 | 12362 | "pll in on but not on in use in sw tracking\n"); |
e2c719b7 | 12363 | I915_STATE_WARN(pll->on != active, |
5358901f DV |
12364 | "pll on state mismatch (expected %i, found %i)\n", |
12365 | pll->on, active); | |
12366 | ||
d3fcc808 | 12367 | for_each_intel_crtc(dev, crtc) { |
83d65738 | 12368 | if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll) |
5358901f DV |
12369 | enabled_crtcs++; |
12370 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) | |
12371 | active_crtcs++; | |
12372 | } | |
e2c719b7 | 12373 | I915_STATE_WARN(pll->active != active_crtcs, |
5358901f DV |
12374 | "pll active crtcs mismatch (expected %i, found %i)\n", |
12375 | pll->active, active_crtcs); | |
e2c719b7 | 12376 | I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs, |
5358901f | 12377 | "pll enabled crtcs mismatch (expected %i, found %i)\n", |
3e369b76 | 12378 | hweight32(pll->config.crtc_mask), enabled_crtcs); |
66e985c0 | 12379 | |
e2c719b7 | 12380 | I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state, |
66e985c0 DV |
12381 | sizeof(dpll_hw_state)), |
12382 | "pll hw state mismatch\n"); | |
5358901f | 12383 | } |
8af6cf88 DV |
12384 | } |
12385 | ||
91d1b4bd DV |
12386 | void |
12387 | intel_modeset_check_state(struct drm_device *dev) | |
12388 | { | |
08db6652 | 12389 | check_wm_state(dev); |
91d1b4bd DV |
12390 | check_connector_state(dev); |
12391 | check_encoder_state(dev); | |
12392 | check_crtc_state(dev); | |
12393 | check_shared_dpll_state(dev); | |
12394 | } | |
12395 | ||
5cec258b | 12396 | void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config, |
18442d08 VS |
12397 | int dotclock) |
12398 | { | |
12399 | /* | |
12400 | * FDI already provided one idea for the dotclock. | |
12401 | * Yell if the encoder disagrees. | |
12402 | */ | |
2d112de7 | 12403 | WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock), |
18442d08 | 12404 | "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n", |
2d112de7 | 12405 | pipe_config->base.adjusted_mode.crtc_clock, dotclock); |
18442d08 VS |
12406 | } |
12407 | ||
80715b2f VS |
12408 | static void update_scanline_offset(struct intel_crtc *crtc) |
12409 | { | |
12410 | struct drm_device *dev = crtc->base.dev; | |
12411 | ||
12412 | /* | |
12413 | * The scanline counter increments at the leading edge of hsync. | |
12414 | * | |
12415 | * On most platforms it starts counting from vtotal-1 on the | |
12416 | * first active line. That means the scanline counter value is | |
12417 | * always one less than what we would expect. Ie. just after | |
12418 | * start of vblank, which also occurs at start of hsync (on the | |
12419 | * last active line), the scanline counter will read vblank_start-1. | |
12420 | * | |
12421 | * On gen2 the scanline counter starts counting from 1 instead | |
12422 | * of vtotal-1, so we have to subtract one (or rather add vtotal-1 | |
12423 | * to keep the value positive), instead of adding one. | |
12424 | * | |
12425 | * On HSW+ the behaviour of the scanline counter depends on the output | |
12426 | * type. For DP ports it behaves like most other platforms, but on HDMI | |
12427 | * there's an extra 1 line difference. So we need to add two instead of | |
12428 | * one to the value. | |
12429 | */ | |
12430 | if (IS_GEN2(dev)) { | |
6e3c9717 | 12431 | const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode; |
80715b2f VS |
12432 | int vtotal; |
12433 | ||
12434 | vtotal = mode->crtc_vtotal; | |
12435 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) | |
12436 | vtotal /= 2; | |
12437 | ||
12438 | crtc->scanline_offset = vtotal - 1; | |
12439 | } else if (HAS_DDI(dev) && | |
409ee761 | 12440 | intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) { |
80715b2f VS |
12441 | crtc->scanline_offset = 2; |
12442 | } else | |
12443 | crtc->scanline_offset = 1; | |
12444 | } | |
12445 | ||
5cec258b | 12446 | static struct intel_crtc_state * |
7f27126e | 12447 | intel_modeset_compute_config(struct drm_crtc *crtc, |
0a9ab303 | 12448 | struct drm_atomic_state *state) |
7f27126e | 12449 | { |
548ee15b | 12450 | struct intel_crtc_state *pipe_config; |
0b901879 ACO |
12451 | int ret = 0; |
12452 | ||
12453 | ret = drm_atomic_add_affected_connectors(state, crtc); | |
12454 | if (ret) | |
12455 | return ERR_PTR(ret); | |
7f27126e | 12456 | |
8c7b5ccb ACO |
12457 | ret = drm_atomic_helper_check_modeset(state->dev, state); |
12458 | if (ret) | |
12459 | return ERR_PTR(ret); | |
7f27126e | 12460 | |
7f27126e JB |
12461 | /* |
12462 | * Note this needs changes when we start tracking multiple modes | |
12463 | * and crtcs. At that point we'll need to compute the whole config | |
12464 | * (i.e. one pipe_config for each crtc) rather than just the one | |
12465 | * for this crtc. | |
12466 | */ | |
548ee15b ACO |
12467 | pipe_config = intel_atomic_get_crtc_state(state, to_intel_crtc(crtc)); |
12468 | if (IS_ERR(pipe_config)) | |
12469 | return pipe_config; | |
83a57153 | 12470 | |
4fed33f6 | 12471 | if (!pipe_config->base.enable) |
548ee15b | 12472 | return pipe_config; |
7f27126e | 12473 | |
8c7b5ccb | 12474 | ret = intel_modeset_pipe_config(crtc, state, pipe_config); |
548ee15b ACO |
12475 | if (ret) |
12476 | return ERR_PTR(ret); | |
12477 | ||
8d8c9b51 ACO |
12478 | /* Check things that can only be changed through modeset */ |
12479 | if (pipe_config->has_audio != | |
12480 | to_intel_crtc(crtc)->config->has_audio) | |
12481 | pipe_config->base.mode_changed = true; | |
12482 | ||
12483 | /* | |
12484 | * Note we have an issue here with infoframes: current code | |
12485 | * only updates them on the full mode set path per hw | |
12486 | * requirements. So here we should be checking for any | |
12487 | * required changes and forcing a mode set. | |
12488 | */ | |
12489 | ||
548ee15b | 12490 | intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,"[modeset]"); |
db7542dd | 12491 | |
8c7b5ccb ACO |
12492 | ret = drm_atomic_helper_check_planes(state->dev, state); |
12493 | if (ret) | |
12494 | return ERR_PTR(ret); | |
12495 | ||
548ee15b | 12496 | return pipe_config; |
7f27126e JB |
12497 | } |
12498 | ||
0a9ab303 | 12499 | static int __intel_set_mode_setup_plls(struct drm_atomic_state *state) |
ed6739ef | 12500 | { |
225da59b | 12501 | struct drm_device *dev = state->dev; |
ed6739ef | 12502 | struct drm_i915_private *dev_priv = to_i915(dev); |
0a9ab303 | 12503 | unsigned clear_pipes = 0; |
ed6739ef | 12504 | struct intel_crtc *intel_crtc; |
0a9ab303 ACO |
12505 | struct intel_crtc_state *intel_crtc_state; |
12506 | struct drm_crtc *crtc; | |
12507 | struct drm_crtc_state *crtc_state; | |
ed6739ef | 12508 | int ret = 0; |
0a9ab303 | 12509 | int i; |
ed6739ef ACO |
12510 | |
12511 | if (!dev_priv->display.crtc_compute_clock) | |
12512 | return 0; | |
12513 | ||
0a9ab303 ACO |
12514 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
12515 | intel_crtc = to_intel_crtc(crtc); | |
4978cc93 | 12516 | intel_crtc_state = to_intel_crtc_state(crtc_state); |
0a9ab303 | 12517 | |
4978cc93 | 12518 | if (needs_modeset(crtc_state)) { |
0a9ab303 | 12519 | clear_pipes |= 1 << intel_crtc->pipe; |
4978cc93 | 12520 | intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE; |
4978cc93 | 12521 | } |
0a9ab303 ACO |
12522 | } |
12523 | ||
ed6739ef ACO |
12524 | ret = intel_shared_dpll_start_config(dev_priv, clear_pipes); |
12525 | if (ret) | |
12526 | goto done; | |
12527 | ||
0a9ab303 ACO |
12528 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
12529 | if (!needs_modeset(crtc_state) || !crtc_state->enable) | |
225da59b ACO |
12530 | continue; |
12531 | ||
0a9ab303 ACO |
12532 | intel_crtc = to_intel_crtc(crtc); |
12533 | intel_crtc_state = to_intel_crtc_state(crtc_state); | |
12534 | ||
ed6739ef | 12535 | ret = dev_priv->display.crtc_compute_clock(intel_crtc, |
0a9ab303 | 12536 | intel_crtc_state); |
ed6739ef ACO |
12537 | if (ret) { |
12538 | intel_shared_dpll_abort_config(dev_priv); | |
12539 | goto done; | |
12540 | } | |
12541 | } | |
12542 | ||
12543 | done: | |
12544 | return ret; | |
12545 | } | |
12546 | ||
054518dd ACO |
12547 | /* Code that should eventually be part of atomic_check() */ |
12548 | static int __intel_set_mode_checks(struct drm_atomic_state *state) | |
12549 | { | |
12550 | struct drm_device *dev = state->dev; | |
12551 | int ret; | |
12552 | ||
12553 | /* | |
12554 | * See if the config requires any additional preparation, e.g. | |
12555 | * to adjust global state with pipes off. We need to do this | |
12556 | * here so we can get the modeset_pipe updated config for the new | |
12557 | * mode set on this crtc. For other crtcs we need to use the | |
12558 | * adjusted_mode bits in the crtc directly. | |
12559 | */ | |
12560 | if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) { | |
12561 | ret = valleyview_modeset_global_pipes(state); | |
12562 | if (ret) | |
12563 | return ret; | |
12564 | } | |
12565 | ||
12566 | ret = __intel_set_mode_setup_plls(state); | |
12567 | if (ret) | |
12568 | return ret; | |
12569 | ||
12570 | return 0; | |
12571 | } | |
12572 | ||
0a9ab303 | 12573 | static int __intel_set_mode(struct drm_crtc *modeset_crtc, |
0a9ab303 | 12574 | struct intel_crtc_state *pipe_config) |
a6778b3c | 12575 | { |
0a9ab303 | 12576 | struct drm_device *dev = modeset_crtc->dev; |
fbee40df | 12577 | struct drm_i915_private *dev_priv = dev->dev_private; |
304603f4 | 12578 | struct drm_atomic_state *state = pipe_config->base.state; |
0a9ab303 ACO |
12579 | struct drm_crtc *crtc; |
12580 | struct drm_crtc_state *crtc_state; | |
c0c36b94 | 12581 | int ret = 0; |
0a9ab303 | 12582 | int i; |
a6778b3c | 12583 | |
054518dd ACO |
12584 | ret = __intel_set_mode_checks(state); |
12585 | if (ret < 0) | |
12586 | return ret; | |
12587 | ||
d4afb8cc ACO |
12588 | ret = drm_atomic_helper_prepare_planes(dev, state); |
12589 | if (ret) | |
12590 | return ret; | |
12591 | ||
0a9ab303 ACO |
12592 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
12593 | if (!needs_modeset(crtc_state)) | |
12594 | continue; | |
460da916 | 12595 | |
0a9ab303 ACO |
12596 | if (!crtc_state->enable) { |
12597 | intel_crtc_disable(crtc); | |
12598 | } else if (crtc->state->enable) { | |
12599 | intel_crtc_disable_planes(crtc); | |
12600 | dev_priv->display.crtc_disable(crtc); | |
ce22dba9 | 12601 | } |
ea9d758d | 12602 | } |
a6778b3c | 12603 | |
6c4c86f5 DV |
12604 | /* crtc->mode is already used by the ->mode_set callbacks, hence we need |
12605 | * to set it here already despite that we pass it down the callchain. | |
7f27126e JB |
12606 | * |
12607 | * Note we'll need to fix this up when we start tracking multiple | |
12608 | * pipes; here we assume a single modeset_pipe and only track the | |
12609 | * single crtc and mode. | |
f6e5b160 | 12610 | */ |
0a9ab303 | 12611 | if (pipe_config->base.enable && needs_modeset(&pipe_config->base)) { |
8c7b5ccb | 12612 | modeset_crtc->mode = pipe_config->base.mode; |
c326c0a9 VS |
12613 | |
12614 | /* | |
12615 | * Calculate and store various constants which | |
12616 | * are later needed by vblank and swap-completion | |
12617 | * timestamping. They are derived from true hwmode. | |
12618 | */ | |
0a9ab303 | 12619 | drm_calc_timestamping_constants(modeset_crtc, |
2d112de7 | 12620 | &pipe_config->base.adjusted_mode); |
b8cecdf5 | 12621 | } |
7758a113 | 12622 | |
ea9d758d DV |
12623 | /* Only after disabling all output pipelines that will be changed can we |
12624 | * update the the output configuration. */ | |
0a9ab303 | 12625 | intel_modeset_update_state(state); |
f6e5b160 | 12626 | |
a821fc46 ACO |
12627 | /* The state has been swaped above, so state actually contains the |
12628 | * old state now. */ | |
12629 | ||
304603f4 | 12630 | modeset_update_crtc_power_domains(state); |
47fab737 | 12631 | |
d4afb8cc | 12632 | drm_atomic_helper_commit_planes(dev, state); |
a6778b3c DV |
12633 | |
12634 | /* Now enable the clocks, plane, pipe, and connectors that we set up. */ | |
0a9ab303 | 12635 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
a821fc46 | 12636 | if (!needs_modeset(crtc->state) || !crtc->state->enable) |
0a9ab303 ACO |
12637 | continue; |
12638 | ||
12639 | update_scanline_offset(to_intel_crtc(crtc)); | |
80715b2f | 12640 | |
0a9ab303 ACO |
12641 | dev_priv->display.crtc_enable(crtc); |
12642 | intel_crtc_enable_planes(crtc); | |
80715b2f | 12643 | } |
a6778b3c | 12644 | |
a6778b3c | 12645 | /* FIXME: add subpixel order */ |
83a57153 | 12646 | |
d4afb8cc ACO |
12647 | drm_atomic_helper_cleanup_planes(dev, state); |
12648 | ||
2bfb4627 ACO |
12649 | drm_atomic_state_free(state); |
12650 | ||
9eb45f22 | 12651 | return 0; |
f6e5b160 CW |
12652 | } |
12653 | ||
0a9ab303 | 12654 | static int intel_set_mode_with_config(struct drm_crtc *crtc, |
0a9ab303 | 12655 | struct intel_crtc_state *pipe_config) |
f30da187 DV |
12656 | { |
12657 | int ret; | |
12658 | ||
8c7b5ccb | 12659 | ret = __intel_set_mode(crtc, pipe_config); |
f30da187 DV |
12660 | |
12661 | if (ret == 0) | |
12662 | intel_modeset_check_state(crtc->dev); | |
12663 | ||
12664 | return ret; | |
12665 | } | |
12666 | ||
7f27126e | 12667 | static int intel_set_mode(struct drm_crtc *crtc, |
83a57153 | 12668 | struct drm_atomic_state *state) |
7f27126e | 12669 | { |
5cec258b | 12670 | struct intel_crtc_state *pipe_config; |
83a57153 | 12671 | int ret = 0; |
7f27126e | 12672 | |
8c7b5ccb | 12673 | pipe_config = intel_modeset_compute_config(crtc, state); |
83a57153 ACO |
12674 | if (IS_ERR(pipe_config)) { |
12675 | ret = PTR_ERR(pipe_config); | |
12676 | goto out; | |
12677 | } | |
12678 | ||
8c7b5ccb | 12679 | ret = intel_set_mode_with_config(crtc, pipe_config); |
83a57153 ACO |
12680 | if (ret) |
12681 | goto out; | |
7f27126e | 12682 | |
83a57153 ACO |
12683 | out: |
12684 | return ret; | |
7f27126e JB |
12685 | } |
12686 | ||
c0c36b94 CW |
12687 | void intel_crtc_restore_mode(struct drm_crtc *crtc) |
12688 | { | |
83a57153 ACO |
12689 | struct drm_device *dev = crtc->dev; |
12690 | struct drm_atomic_state *state; | |
4be07317 | 12691 | struct intel_crtc *intel_crtc; |
83a57153 ACO |
12692 | struct intel_encoder *encoder; |
12693 | struct intel_connector *connector; | |
12694 | struct drm_connector_state *connector_state; | |
4be07317 | 12695 | struct intel_crtc_state *crtc_state; |
2bfb4627 | 12696 | int ret; |
83a57153 ACO |
12697 | |
12698 | state = drm_atomic_state_alloc(dev); | |
12699 | if (!state) { | |
12700 | DRM_DEBUG_KMS("[CRTC:%d] mode restore failed, out of memory", | |
12701 | crtc->base.id); | |
12702 | return; | |
12703 | } | |
12704 | ||
12705 | state->acquire_ctx = dev->mode_config.acquire_ctx; | |
12706 | ||
12707 | /* The force restore path in the HW readout code relies on the staged | |
12708 | * config still keeping the user requested config while the actual | |
12709 | * state has been overwritten by the configuration read from HW. We | |
12710 | * need to copy the staged config to the atomic state, otherwise the | |
12711 | * mode set will just reapply the state the HW is already in. */ | |
12712 | for_each_intel_encoder(dev, encoder) { | |
12713 | if (&encoder->new_crtc->base != crtc) | |
12714 | continue; | |
12715 | ||
12716 | for_each_intel_connector(dev, connector) { | |
12717 | if (connector->new_encoder != encoder) | |
12718 | continue; | |
12719 | ||
12720 | connector_state = drm_atomic_get_connector_state(state, &connector->base); | |
12721 | if (IS_ERR(connector_state)) { | |
12722 | DRM_DEBUG_KMS("Failed to add [CONNECTOR:%d:%s] to state: %ld\n", | |
12723 | connector->base.base.id, | |
12724 | connector->base.name, | |
12725 | PTR_ERR(connector_state)); | |
12726 | continue; | |
12727 | } | |
12728 | ||
12729 | connector_state->crtc = crtc; | |
12730 | connector_state->best_encoder = &encoder->base; | |
12731 | } | |
12732 | } | |
12733 | ||
4be07317 ACO |
12734 | for_each_intel_crtc(dev, intel_crtc) { |
12735 | if (intel_crtc->new_enabled == intel_crtc->base.enabled) | |
12736 | continue; | |
12737 | ||
12738 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); | |
12739 | if (IS_ERR(crtc_state)) { | |
12740 | DRM_DEBUG_KMS("Failed to add [CRTC:%d] to state: %ld\n", | |
12741 | intel_crtc->base.base.id, | |
12742 | PTR_ERR(crtc_state)); | |
12743 | continue; | |
12744 | } | |
12745 | ||
49d6fa21 ML |
12746 | crtc_state->base.active = crtc_state->base.enable = |
12747 | intel_crtc->new_enabled; | |
8c7b5ccb ACO |
12748 | |
12749 | if (&intel_crtc->base == crtc) | |
12750 | drm_mode_copy(&crtc_state->base.mode, &crtc->mode); | |
4be07317 ACO |
12751 | } |
12752 | ||
d3a40d1b ACO |
12753 | intel_modeset_setup_plane_state(state, crtc, &crtc->mode, |
12754 | crtc->primary->fb, crtc->x, crtc->y); | |
12755 | ||
2bfb4627 ACO |
12756 | ret = intel_set_mode(crtc, state); |
12757 | if (ret) | |
12758 | drm_atomic_state_free(state); | |
c0c36b94 CW |
12759 | } |
12760 | ||
25c5b266 DV |
12761 | #undef for_each_intel_crtc_masked |
12762 | ||
b7885264 ACO |
12763 | static bool intel_connector_in_mode_set(struct intel_connector *connector, |
12764 | struct drm_mode_set *set) | |
12765 | { | |
12766 | int ro; | |
12767 | ||
12768 | for (ro = 0; ro < set->num_connectors; ro++) | |
12769 | if (set->connectors[ro] == &connector->base) | |
12770 | return true; | |
12771 | ||
12772 | return false; | |
12773 | } | |
12774 | ||
2e431051 | 12775 | static int |
9a935856 DV |
12776 | intel_modeset_stage_output_state(struct drm_device *dev, |
12777 | struct drm_mode_set *set, | |
944b0c76 | 12778 | struct drm_atomic_state *state) |
50f56119 | 12779 | { |
9a935856 | 12780 | struct intel_connector *connector; |
d5432a9d | 12781 | struct drm_connector *drm_connector; |
944b0c76 | 12782 | struct drm_connector_state *connector_state; |
d5432a9d ACO |
12783 | struct drm_crtc *crtc; |
12784 | struct drm_crtc_state *crtc_state; | |
12785 | int i, ret; | |
50f56119 | 12786 | |
9abdda74 | 12787 | /* The upper layers ensure that we either disable a crtc or have a list |
9a935856 DV |
12788 | * of connectors. For paranoia, double-check this. */ |
12789 | WARN_ON(!set->fb && (set->num_connectors != 0)); | |
12790 | WARN_ON(set->fb && (set->num_connectors == 0)); | |
12791 | ||
3a3371ff | 12792 | for_each_intel_connector(dev, connector) { |
b7885264 ACO |
12793 | bool in_mode_set = intel_connector_in_mode_set(connector, set); |
12794 | ||
d5432a9d ACO |
12795 | if (!in_mode_set && connector->base.state->crtc != set->crtc) |
12796 | continue; | |
12797 | ||
12798 | connector_state = | |
12799 | drm_atomic_get_connector_state(state, &connector->base); | |
12800 | if (IS_ERR(connector_state)) | |
12801 | return PTR_ERR(connector_state); | |
12802 | ||
b7885264 ACO |
12803 | if (in_mode_set) { |
12804 | int pipe = to_intel_crtc(set->crtc)->pipe; | |
d5432a9d ACO |
12805 | connector_state->best_encoder = |
12806 | &intel_find_encoder(connector, pipe)->base; | |
50f56119 DV |
12807 | } |
12808 | ||
d5432a9d | 12809 | if (connector->base.state->crtc != set->crtc) |
b7885264 ACO |
12810 | continue; |
12811 | ||
9a935856 DV |
12812 | /* If we disable the crtc, disable all its connectors. Also, if |
12813 | * the connector is on the changing crtc but not on the new | |
12814 | * connector list, disable it. */ | |
b7885264 | 12815 | if (!set->fb || !in_mode_set) { |
d5432a9d | 12816 | connector_state->best_encoder = NULL; |
9a935856 DV |
12817 | |
12818 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n", | |
12819 | connector->base.base.id, | |
c23cc417 | 12820 | connector->base.name); |
9a935856 | 12821 | } |
50f56119 | 12822 | } |
9a935856 | 12823 | /* connector->new_encoder is now updated for all connectors. */ |
50f56119 | 12824 | |
d5432a9d ACO |
12825 | for_each_connector_in_state(state, drm_connector, connector_state, i) { |
12826 | connector = to_intel_connector(drm_connector); | |
12827 | ||
12828 | if (!connector_state->best_encoder) { | |
12829 | ret = drm_atomic_set_crtc_for_connector(connector_state, | |
12830 | NULL); | |
12831 | if (ret) | |
12832 | return ret; | |
7668851f | 12833 | |
50f56119 | 12834 | continue; |
d5432a9d | 12835 | } |
50f56119 | 12836 | |
d5432a9d ACO |
12837 | if (intel_connector_in_mode_set(connector, set)) { |
12838 | struct drm_crtc *crtc = connector->base.state->crtc; | |
12839 | ||
12840 | /* If this connector was in a previous crtc, add it | |
12841 | * to the state. We might need to disable it. */ | |
12842 | if (crtc) { | |
12843 | crtc_state = | |
12844 | drm_atomic_get_crtc_state(state, crtc); | |
12845 | if (IS_ERR(crtc_state)) | |
12846 | return PTR_ERR(crtc_state); | |
12847 | } | |
12848 | ||
12849 | ret = drm_atomic_set_crtc_for_connector(connector_state, | |
12850 | set->crtc); | |
12851 | if (ret) | |
12852 | return ret; | |
12853 | } | |
50f56119 DV |
12854 | |
12855 | /* Make sure the new CRTC will work with the encoder */ | |
d5432a9d ACO |
12856 | if (!drm_encoder_crtc_ok(connector_state->best_encoder, |
12857 | connector_state->crtc)) { | |
5e2b584e | 12858 | return -EINVAL; |
50f56119 | 12859 | } |
944b0c76 | 12860 | |
9a935856 DV |
12861 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n", |
12862 | connector->base.base.id, | |
c23cc417 | 12863 | connector->base.name, |
d5432a9d | 12864 | connector_state->crtc->base.id); |
944b0c76 | 12865 | |
d5432a9d ACO |
12866 | if (connector_state->best_encoder != &connector->encoder->base) |
12867 | connector->encoder = | |
12868 | to_intel_encoder(connector_state->best_encoder); | |
0e32b39c | 12869 | } |
7668851f | 12870 | |
d5432a9d | 12871 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
49d6fa21 ML |
12872 | bool has_connectors; |
12873 | ||
d5432a9d ACO |
12874 | ret = drm_atomic_add_affected_connectors(state, crtc); |
12875 | if (ret) | |
12876 | return ret; | |
4be07317 | 12877 | |
49d6fa21 ML |
12878 | has_connectors = !!drm_atomic_connectors_for_crtc(state, crtc); |
12879 | if (has_connectors != crtc_state->enable) | |
12880 | crtc_state->enable = | |
12881 | crtc_state->active = has_connectors; | |
7668851f VS |
12882 | } |
12883 | ||
8c7b5ccb ACO |
12884 | ret = intel_modeset_setup_plane_state(state, set->crtc, set->mode, |
12885 | set->fb, set->x, set->y); | |
12886 | if (ret) | |
12887 | return ret; | |
12888 | ||
12889 | crtc_state = drm_atomic_get_crtc_state(state, set->crtc); | |
12890 | if (IS_ERR(crtc_state)) | |
12891 | return PTR_ERR(crtc_state); | |
12892 | ||
12893 | if (set->mode) | |
12894 | drm_mode_copy(&crtc_state->mode, set->mode); | |
12895 | ||
12896 | if (set->num_connectors) | |
12897 | crtc_state->active = true; | |
12898 | ||
2e431051 DV |
12899 | return 0; |
12900 | } | |
12901 | ||
bb546623 ACO |
12902 | static bool primary_plane_visible(struct drm_crtc *crtc) |
12903 | { | |
12904 | struct intel_plane_state *plane_state = | |
12905 | to_intel_plane_state(crtc->primary->state); | |
12906 | ||
12907 | return plane_state->visible; | |
12908 | } | |
12909 | ||
2e431051 DV |
12910 | static int intel_crtc_set_config(struct drm_mode_set *set) |
12911 | { | |
12912 | struct drm_device *dev; | |
83a57153 | 12913 | struct drm_atomic_state *state = NULL; |
5cec258b | 12914 | struct intel_crtc_state *pipe_config; |
bb546623 | 12915 | bool primary_plane_was_visible; |
2e431051 | 12916 | int ret; |
2e431051 | 12917 | |
8d3e375e DV |
12918 | BUG_ON(!set); |
12919 | BUG_ON(!set->crtc); | |
12920 | BUG_ON(!set->crtc->helper_private); | |
2e431051 | 12921 | |
7e53f3a4 DV |
12922 | /* Enforce sane interface api - has been abused by the fb helper. */ |
12923 | BUG_ON(!set->mode && set->fb); | |
12924 | BUG_ON(set->fb && set->num_connectors == 0); | |
431e50f7 | 12925 | |
2e431051 DV |
12926 | if (set->fb) { |
12927 | DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n", | |
12928 | set->crtc->base.id, set->fb->base.id, | |
12929 | (int)set->num_connectors, set->x, set->y); | |
12930 | } else { | |
12931 | DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id); | |
2e431051 DV |
12932 | } |
12933 | ||
12934 | dev = set->crtc->dev; | |
12935 | ||
83a57153 | 12936 | state = drm_atomic_state_alloc(dev); |
7cbf41d6 ACO |
12937 | if (!state) |
12938 | return -ENOMEM; | |
83a57153 ACO |
12939 | |
12940 | state->acquire_ctx = dev->mode_config.acquire_ctx; | |
12941 | ||
462a425a | 12942 | ret = intel_modeset_stage_output_state(dev, set, state); |
2e431051 | 12943 | if (ret) |
7cbf41d6 | 12944 | goto out; |
2e431051 | 12945 | |
8c7b5ccb | 12946 | pipe_config = intel_modeset_compute_config(set->crtc, state); |
20664591 | 12947 | if (IS_ERR(pipe_config)) { |
6ac0483b | 12948 | ret = PTR_ERR(pipe_config); |
7cbf41d6 | 12949 | goto out; |
20664591 | 12950 | } |
50f52756 | 12951 | |
1f9954d0 JB |
12952 | intel_update_pipe_size(to_intel_crtc(set->crtc)); |
12953 | ||
bb546623 ACO |
12954 | primary_plane_was_visible = primary_plane_visible(set->crtc); |
12955 | ||
8c7b5ccb | 12956 | ret = intel_set_mode_with_config(set->crtc, pipe_config); |
bb546623 ACO |
12957 | |
12958 | if (ret == 0 && | |
12959 | pipe_config->base.enable && | |
12960 | pipe_config->base.planes_changed && | |
12961 | !needs_modeset(&pipe_config->base)) { | |
3b150f08 | 12962 | struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc); |
3b150f08 MR |
12963 | |
12964 | /* | |
12965 | * We need to make sure the primary plane is re-enabled if it | |
12966 | * has previously been turned off. | |
12967 | */ | |
bb546623 ACO |
12968 | if (ret == 0 && !primary_plane_was_visible && |
12969 | primary_plane_visible(set->crtc)) { | |
3b150f08 | 12970 | WARN_ON(!intel_crtc->active); |
87d4300a | 12971 | intel_post_enable_primary(set->crtc); |
3b150f08 MR |
12972 | } |
12973 | ||
7ca51a3a JB |
12974 | /* |
12975 | * In the fastboot case this may be our only check of the | |
12976 | * state after boot. It would be better to only do it on | |
12977 | * the first update, but we don't have a nice way of doing that | |
12978 | * (and really, set_config isn't used much for high freq page | |
12979 | * flipping, so increasing its cost here shouldn't be a big | |
12980 | * deal). | |
12981 | */ | |
d330a953 | 12982 | if (i915.fastboot && ret == 0) |
7ca51a3a | 12983 | intel_modeset_check_state(set->crtc->dev); |
50f56119 DV |
12984 | } |
12985 | ||
2d05eae1 | 12986 | if (ret) { |
bf67dfeb DV |
12987 | DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n", |
12988 | set->crtc->base.id, ret); | |
2d05eae1 | 12989 | } |
50f56119 | 12990 | |
7cbf41d6 | 12991 | out: |
2bfb4627 ACO |
12992 | if (ret) |
12993 | drm_atomic_state_free(state); | |
50f56119 DV |
12994 | return ret; |
12995 | } | |
f6e5b160 CW |
12996 | |
12997 | static const struct drm_crtc_funcs intel_crtc_funcs = { | |
f6e5b160 | 12998 | .gamma_set = intel_crtc_gamma_set, |
50f56119 | 12999 | .set_config = intel_crtc_set_config, |
f6e5b160 CW |
13000 | .destroy = intel_crtc_destroy, |
13001 | .page_flip = intel_crtc_page_flip, | |
1356837e MR |
13002 | .atomic_duplicate_state = intel_crtc_duplicate_state, |
13003 | .atomic_destroy_state = intel_crtc_destroy_state, | |
f6e5b160 CW |
13004 | }; |
13005 | ||
5358901f DV |
13006 | static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv, |
13007 | struct intel_shared_dpll *pll, | |
13008 | struct intel_dpll_hw_state *hw_state) | |
ee7b9f93 | 13009 | { |
5358901f | 13010 | uint32_t val; |
ee7b9f93 | 13011 | |
f458ebbc | 13012 | if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS)) |
bd2bb1b9 PZ |
13013 | return false; |
13014 | ||
5358901f | 13015 | val = I915_READ(PCH_DPLL(pll->id)); |
66e985c0 DV |
13016 | hw_state->dpll = val; |
13017 | hw_state->fp0 = I915_READ(PCH_FP0(pll->id)); | |
13018 | hw_state->fp1 = I915_READ(PCH_FP1(pll->id)); | |
5358901f DV |
13019 | |
13020 | return val & DPLL_VCO_ENABLE; | |
13021 | } | |
13022 | ||
15bdd4cf DV |
13023 | static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv, |
13024 | struct intel_shared_dpll *pll) | |
13025 | { | |
3e369b76 ACO |
13026 | I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0); |
13027 | I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1); | |
15bdd4cf DV |
13028 | } |
13029 | ||
e7b903d2 DV |
13030 | static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv, |
13031 | struct intel_shared_dpll *pll) | |
13032 | { | |
e7b903d2 | 13033 | /* PCH refclock must be enabled first */ |
89eff4be | 13034 | ibx_assert_pch_refclk_enabled(dev_priv); |
e7b903d2 | 13035 | |
3e369b76 | 13036 | I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll); |
15bdd4cf DV |
13037 | |
13038 | /* Wait for the clocks to stabilize. */ | |
13039 | POSTING_READ(PCH_DPLL(pll->id)); | |
13040 | udelay(150); | |
13041 | ||
13042 | /* The pixel multiplier can only be updated once the | |
13043 | * DPLL is enabled and the clocks are stable. | |
13044 | * | |
13045 | * So write it again. | |
13046 | */ | |
3e369b76 | 13047 | I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll); |
15bdd4cf | 13048 | POSTING_READ(PCH_DPLL(pll->id)); |
e7b903d2 DV |
13049 | udelay(200); |
13050 | } | |
13051 | ||
13052 | static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv, | |
13053 | struct intel_shared_dpll *pll) | |
13054 | { | |
13055 | struct drm_device *dev = dev_priv->dev; | |
13056 | struct intel_crtc *crtc; | |
e7b903d2 DV |
13057 | |
13058 | /* Make sure no transcoder isn't still depending on us. */ | |
d3fcc808 | 13059 | for_each_intel_crtc(dev, crtc) { |
e7b903d2 DV |
13060 | if (intel_crtc_to_shared_dpll(crtc) == pll) |
13061 | assert_pch_transcoder_disabled(dev_priv, crtc->pipe); | |
ee7b9f93 JB |
13062 | } |
13063 | ||
15bdd4cf DV |
13064 | I915_WRITE(PCH_DPLL(pll->id), 0); |
13065 | POSTING_READ(PCH_DPLL(pll->id)); | |
e7b903d2 DV |
13066 | udelay(200); |
13067 | } | |
13068 | ||
46edb027 DV |
13069 | static char *ibx_pch_dpll_names[] = { |
13070 | "PCH DPLL A", | |
13071 | "PCH DPLL B", | |
13072 | }; | |
13073 | ||
7c74ade1 | 13074 | static void ibx_pch_dpll_init(struct drm_device *dev) |
ee7b9f93 | 13075 | { |
e7b903d2 | 13076 | struct drm_i915_private *dev_priv = dev->dev_private; |
ee7b9f93 JB |
13077 | int i; |
13078 | ||
7c74ade1 | 13079 | dev_priv->num_shared_dpll = 2; |
ee7b9f93 | 13080 | |
e72f9fbf | 13081 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
46edb027 DV |
13082 | dev_priv->shared_dplls[i].id = i; |
13083 | dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i]; | |
15bdd4cf | 13084 | dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set; |
e7b903d2 DV |
13085 | dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable; |
13086 | dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable; | |
5358901f DV |
13087 | dev_priv->shared_dplls[i].get_hw_state = |
13088 | ibx_pch_dpll_get_hw_state; | |
ee7b9f93 JB |
13089 | } |
13090 | } | |
13091 | ||
7c74ade1 DV |
13092 | static void intel_shared_dpll_init(struct drm_device *dev) |
13093 | { | |
e7b903d2 | 13094 | struct drm_i915_private *dev_priv = dev->dev_private; |
7c74ade1 | 13095 | |
9cd86933 DV |
13096 | if (HAS_DDI(dev)) |
13097 | intel_ddi_pll_init(dev); | |
13098 | else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
7c74ade1 DV |
13099 | ibx_pch_dpll_init(dev); |
13100 | else | |
13101 | dev_priv->num_shared_dpll = 0; | |
13102 | ||
13103 | BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS); | |
7c74ade1 DV |
13104 | } |
13105 | ||
1fc0a8f7 TU |
13106 | /** |
13107 | * intel_wm_need_update - Check whether watermarks need updating | |
13108 | * @plane: drm plane | |
13109 | * @state: new plane state | |
13110 | * | |
13111 | * Check current plane state versus the new one to determine whether | |
13112 | * watermarks need to be recalculated. | |
13113 | * | |
13114 | * Returns true or false. | |
13115 | */ | |
13116 | bool intel_wm_need_update(struct drm_plane *plane, | |
13117 | struct drm_plane_state *state) | |
13118 | { | |
13119 | /* Update watermarks on tiling changes. */ | |
13120 | if (!plane->state->fb || !state->fb || | |
13121 | plane->state->fb->modifier[0] != state->fb->modifier[0] || | |
13122 | plane->state->rotation != state->rotation) | |
13123 | return true; | |
13124 | ||
13125 | return false; | |
13126 | } | |
13127 | ||
6beb8c23 MR |
13128 | /** |
13129 | * intel_prepare_plane_fb - Prepare fb for usage on plane | |
13130 | * @plane: drm plane to prepare for | |
13131 | * @fb: framebuffer to prepare for presentation | |
13132 | * | |
13133 | * Prepares a framebuffer for usage on a display plane. Generally this | |
13134 | * involves pinning the underlying object and updating the frontbuffer tracking | |
13135 | * bits. Some older platforms need special physical address handling for | |
13136 | * cursor planes. | |
13137 | * | |
13138 | * Returns 0 on success, negative error code on failure. | |
13139 | */ | |
13140 | int | |
13141 | intel_prepare_plane_fb(struct drm_plane *plane, | |
d136dfee TU |
13142 | struct drm_framebuffer *fb, |
13143 | const struct drm_plane_state *new_state) | |
465c120c MR |
13144 | { |
13145 | struct drm_device *dev = plane->dev; | |
6beb8c23 MR |
13146 | struct intel_plane *intel_plane = to_intel_plane(plane); |
13147 | enum pipe pipe = intel_plane->pipe; | |
13148 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
13149 | struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb); | |
13150 | unsigned frontbuffer_bits = 0; | |
13151 | int ret = 0; | |
465c120c | 13152 | |
ea2c67bb | 13153 | if (!obj) |
465c120c MR |
13154 | return 0; |
13155 | ||
6beb8c23 MR |
13156 | switch (plane->type) { |
13157 | case DRM_PLANE_TYPE_PRIMARY: | |
13158 | frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(pipe); | |
13159 | break; | |
13160 | case DRM_PLANE_TYPE_CURSOR: | |
13161 | frontbuffer_bits = INTEL_FRONTBUFFER_CURSOR(pipe); | |
13162 | break; | |
13163 | case DRM_PLANE_TYPE_OVERLAY: | |
13164 | frontbuffer_bits = INTEL_FRONTBUFFER_SPRITE(pipe); | |
13165 | break; | |
13166 | } | |
465c120c | 13167 | |
6beb8c23 | 13168 | mutex_lock(&dev->struct_mutex); |
465c120c | 13169 | |
6beb8c23 MR |
13170 | if (plane->type == DRM_PLANE_TYPE_CURSOR && |
13171 | INTEL_INFO(dev)->cursor_needs_physical) { | |
13172 | int align = IS_I830(dev) ? 16 * 1024 : 256; | |
13173 | ret = i915_gem_object_attach_phys(obj, align); | |
13174 | if (ret) | |
13175 | DRM_DEBUG_KMS("failed to attach phys object\n"); | |
13176 | } else { | |
82bc3b2d | 13177 | ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL); |
6beb8c23 | 13178 | } |
465c120c | 13179 | |
6beb8c23 MR |
13180 | if (ret == 0) |
13181 | i915_gem_track_fb(old_obj, obj, frontbuffer_bits); | |
fdd508a6 | 13182 | |
4c34574f | 13183 | mutex_unlock(&dev->struct_mutex); |
465c120c | 13184 | |
6beb8c23 MR |
13185 | return ret; |
13186 | } | |
13187 | ||
38f3ce3a MR |
13188 | /** |
13189 | * intel_cleanup_plane_fb - Cleans up an fb after plane use | |
13190 | * @plane: drm plane to clean up for | |
13191 | * @fb: old framebuffer that was on plane | |
13192 | * | |
13193 | * Cleans up a framebuffer that has just been removed from a plane. | |
13194 | */ | |
13195 | void | |
13196 | intel_cleanup_plane_fb(struct drm_plane *plane, | |
d136dfee TU |
13197 | struct drm_framebuffer *fb, |
13198 | const struct drm_plane_state *old_state) | |
38f3ce3a MR |
13199 | { |
13200 | struct drm_device *dev = plane->dev; | |
13201 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
13202 | ||
13203 | if (WARN_ON(!obj)) | |
13204 | return; | |
13205 | ||
13206 | if (plane->type != DRM_PLANE_TYPE_CURSOR || | |
13207 | !INTEL_INFO(dev)->cursor_needs_physical) { | |
13208 | mutex_lock(&dev->struct_mutex); | |
82bc3b2d | 13209 | intel_unpin_fb_obj(fb, old_state); |
38f3ce3a MR |
13210 | mutex_unlock(&dev->struct_mutex); |
13211 | } | |
465c120c MR |
13212 | } |
13213 | ||
6156a456 CK |
13214 | int |
13215 | skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state) | |
13216 | { | |
13217 | int max_scale; | |
13218 | struct drm_device *dev; | |
13219 | struct drm_i915_private *dev_priv; | |
13220 | int crtc_clock, cdclk; | |
13221 | ||
13222 | if (!intel_crtc || !crtc_state) | |
13223 | return DRM_PLANE_HELPER_NO_SCALING; | |
13224 | ||
13225 | dev = intel_crtc->base.dev; | |
13226 | dev_priv = dev->dev_private; | |
13227 | crtc_clock = crtc_state->base.adjusted_mode.crtc_clock; | |
13228 | cdclk = dev_priv->display.get_display_clock_speed(dev); | |
13229 | ||
13230 | if (!crtc_clock || !cdclk) | |
13231 | return DRM_PLANE_HELPER_NO_SCALING; | |
13232 | ||
13233 | /* | |
13234 | * skl max scale is lower of: | |
13235 | * close to 3 but not 3, -1 is for that purpose | |
13236 | * or | |
13237 | * cdclk/crtc_clock | |
13238 | */ | |
13239 | max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock)); | |
13240 | ||
13241 | return max_scale; | |
13242 | } | |
13243 | ||
465c120c | 13244 | static int |
3c692a41 GP |
13245 | intel_check_primary_plane(struct drm_plane *plane, |
13246 | struct intel_plane_state *state) | |
13247 | { | |
32b7eeec MR |
13248 | struct drm_device *dev = plane->dev; |
13249 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2b875c22 | 13250 | struct drm_crtc *crtc = state->base.crtc; |
ea2c67bb | 13251 | struct intel_crtc *intel_crtc; |
6156a456 | 13252 | struct intel_crtc_state *crtc_state; |
2b875c22 | 13253 | struct drm_framebuffer *fb = state->base.fb; |
3c692a41 GP |
13254 | struct drm_rect *dest = &state->dst; |
13255 | struct drm_rect *src = &state->src; | |
13256 | const struct drm_rect *clip = &state->clip; | |
d8106366 | 13257 | bool can_position = false; |
6156a456 CK |
13258 | int max_scale = DRM_PLANE_HELPER_NO_SCALING; |
13259 | int min_scale = DRM_PLANE_HELPER_NO_SCALING; | |
465c120c MR |
13260 | int ret; |
13261 | ||
ea2c67bb MR |
13262 | crtc = crtc ? crtc : plane->crtc; |
13263 | intel_crtc = to_intel_crtc(crtc); | |
6156a456 CK |
13264 | crtc_state = state->base.state ? |
13265 | intel_atomic_get_crtc_state(state->base.state, intel_crtc) : NULL; | |
ea2c67bb | 13266 | |
6156a456 | 13267 | if (INTEL_INFO(dev)->gen >= 9) { |
225c228a CK |
13268 | /* use scaler when colorkey is not required */ |
13269 | if (to_intel_plane(plane)->ckey.flags == I915_SET_COLORKEY_NONE) { | |
13270 | min_scale = 1; | |
13271 | max_scale = skl_max_scale(intel_crtc, crtc_state); | |
13272 | } | |
d8106366 | 13273 | can_position = true; |
6156a456 | 13274 | } |
d8106366 | 13275 | |
c59cb179 MR |
13276 | ret = drm_plane_helper_check_update(plane, crtc, fb, |
13277 | src, dest, clip, | |
6156a456 CK |
13278 | min_scale, |
13279 | max_scale, | |
d8106366 SJ |
13280 | can_position, true, |
13281 | &state->visible); | |
c59cb179 MR |
13282 | if (ret) |
13283 | return ret; | |
465c120c | 13284 | |
32b7eeec | 13285 | if (intel_crtc->active) { |
b70709a6 ML |
13286 | struct intel_plane_state *old_state = |
13287 | to_intel_plane_state(plane->state); | |
13288 | ||
32b7eeec MR |
13289 | intel_crtc->atomic.wait_for_flips = true; |
13290 | ||
13291 | /* | |
13292 | * FBC does not work on some platforms for rotated | |
13293 | * planes, so disable it when rotation is not 0 and | |
13294 | * update it when rotation is set back to 0. | |
13295 | * | |
13296 | * FIXME: This is redundant with the fbc update done in | |
13297 | * the primary plane enable function except that that | |
13298 | * one is done too late. We eventually need to unify | |
13299 | * this. | |
13300 | */ | |
b70709a6 | 13301 | if (state->visible && |
32b7eeec | 13302 | INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) && |
e35fef21 | 13303 | dev_priv->fbc.crtc == intel_crtc && |
8e7d688b | 13304 | state->base.rotation != BIT(DRM_ROTATE_0)) { |
32b7eeec MR |
13305 | intel_crtc->atomic.disable_fbc = true; |
13306 | } | |
13307 | ||
b70709a6 | 13308 | if (state->visible && !old_state->visible) { |
32b7eeec MR |
13309 | /* |
13310 | * BDW signals flip done immediately if the plane | |
13311 | * is disabled, even if the plane enable is already | |
13312 | * armed to occur at the next vblank :( | |
13313 | */ | |
b70709a6 | 13314 | if (IS_BROADWELL(dev)) |
32b7eeec MR |
13315 | intel_crtc->atomic.wait_vblank = true; |
13316 | } | |
13317 | ||
13318 | intel_crtc->atomic.fb_bits |= | |
13319 | INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe); | |
13320 | ||
13321 | intel_crtc->atomic.update_fbc = true; | |
0fda6568 | 13322 | |
1fc0a8f7 | 13323 | if (intel_wm_need_update(plane, &state->base)) |
0fda6568 | 13324 | intel_crtc->atomic.update_wm = true; |
ccc759dc GP |
13325 | } |
13326 | ||
6156a456 CK |
13327 | if (INTEL_INFO(dev)->gen >= 9) { |
13328 | ret = skl_update_scaler_users(intel_crtc, crtc_state, | |
13329 | to_intel_plane(plane), state, 0); | |
13330 | if (ret) | |
13331 | return ret; | |
13332 | } | |
13333 | ||
14af293f GP |
13334 | return 0; |
13335 | } | |
13336 | ||
13337 | static void | |
13338 | intel_commit_primary_plane(struct drm_plane *plane, | |
13339 | struct intel_plane_state *state) | |
13340 | { | |
2b875c22 MR |
13341 | struct drm_crtc *crtc = state->base.crtc; |
13342 | struct drm_framebuffer *fb = state->base.fb; | |
13343 | struct drm_device *dev = plane->dev; | |
14af293f | 13344 | struct drm_i915_private *dev_priv = dev->dev_private; |
ea2c67bb | 13345 | struct intel_crtc *intel_crtc; |
14af293f GP |
13346 | struct drm_rect *src = &state->src; |
13347 | ||
ea2c67bb MR |
13348 | crtc = crtc ? crtc : plane->crtc; |
13349 | intel_crtc = to_intel_crtc(crtc); | |
cf4c7c12 MR |
13350 | |
13351 | plane->fb = fb; | |
9dc806fc MR |
13352 | crtc->x = src->x1 >> 16; |
13353 | crtc->y = src->y1 >> 16; | |
ccc759dc | 13354 | |
ccc759dc | 13355 | if (intel_crtc->active) { |
27321ae8 | 13356 | if (state->visible) |
ccc759dc GP |
13357 | /* FIXME: kill this fastboot hack */ |
13358 | intel_update_pipe_size(intel_crtc); | |
465c120c | 13359 | |
27321ae8 ML |
13360 | dev_priv->display.update_primary_plane(crtc, plane->fb, |
13361 | crtc->x, crtc->y); | |
ccc759dc | 13362 | } |
465c120c MR |
13363 | } |
13364 | ||
a8ad0d8e ML |
13365 | static void |
13366 | intel_disable_primary_plane(struct drm_plane *plane, | |
13367 | struct drm_crtc *crtc, | |
13368 | bool force) | |
13369 | { | |
13370 | struct drm_device *dev = plane->dev; | |
13371 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13372 | ||
a8ad0d8e ML |
13373 | dev_priv->display.update_primary_plane(crtc, NULL, 0, 0); |
13374 | } | |
13375 | ||
32b7eeec | 13376 | static void intel_begin_crtc_commit(struct drm_crtc *crtc) |
3c692a41 | 13377 | { |
32b7eeec | 13378 | struct drm_device *dev = crtc->dev; |
140fd38d | 13379 | struct drm_i915_private *dev_priv = dev->dev_private; |
3c692a41 | 13380 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
ea2c67bb MR |
13381 | struct intel_plane *intel_plane; |
13382 | struct drm_plane *p; | |
13383 | unsigned fb_bits = 0; | |
13384 | ||
13385 | /* Track fb's for any planes being disabled */ | |
13386 | list_for_each_entry(p, &dev->mode_config.plane_list, head) { | |
13387 | intel_plane = to_intel_plane(p); | |
13388 | ||
13389 | if (intel_crtc->atomic.disabled_planes & | |
13390 | (1 << drm_plane_index(p))) { | |
13391 | switch (p->type) { | |
13392 | case DRM_PLANE_TYPE_PRIMARY: | |
13393 | fb_bits = INTEL_FRONTBUFFER_PRIMARY(intel_plane->pipe); | |
13394 | break; | |
13395 | case DRM_PLANE_TYPE_CURSOR: | |
13396 | fb_bits = INTEL_FRONTBUFFER_CURSOR(intel_plane->pipe); | |
13397 | break; | |
13398 | case DRM_PLANE_TYPE_OVERLAY: | |
13399 | fb_bits = INTEL_FRONTBUFFER_SPRITE(intel_plane->pipe); | |
13400 | break; | |
13401 | } | |
3c692a41 | 13402 | |
ea2c67bb MR |
13403 | mutex_lock(&dev->struct_mutex); |
13404 | i915_gem_track_fb(intel_fb_obj(p->fb), NULL, fb_bits); | |
13405 | mutex_unlock(&dev->struct_mutex); | |
13406 | } | |
13407 | } | |
3c692a41 | 13408 | |
32b7eeec MR |
13409 | if (intel_crtc->atomic.wait_for_flips) |
13410 | intel_crtc_wait_for_pending_flips(crtc); | |
3c692a41 | 13411 | |
32b7eeec MR |
13412 | if (intel_crtc->atomic.disable_fbc) |
13413 | intel_fbc_disable(dev); | |
3c692a41 | 13414 | |
32b7eeec MR |
13415 | if (intel_crtc->atomic.pre_disable_primary) |
13416 | intel_pre_disable_primary(crtc); | |
3c692a41 | 13417 | |
32b7eeec MR |
13418 | if (intel_crtc->atomic.update_wm) |
13419 | intel_update_watermarks(crtc); | |
3c692a41 | 13420 | |
32b7eeec | 13421 | intel_runtime_pm_get(dev_priv); |
3c692a41 | 13422 | |
c34c9ee4 MR |
13423 | /* Perform vblank evasion around commit operation */ |
13424 | if (intel_crtc->active) | |
13425 | intel_crtc->atomic.evade = | |
13426 | intel_pipe_update_start(intel_crtc, | |
13427 | &intel_crtc->atomic.start_vbl_count); | |
32b7eeec MR |
13428 | } |
13429 | ||
13430 | static void intel_finish_crtc_commit(struct drm_crtc *crtc) | |
13431 | { | |
13432 | struct drm_device *dev = crtc->dev; | |
13433 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13434 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
13435 | struct drm_plane *p; | |
13436 | ||
c34c9ee4 MR |
13437 | if (intel_crtc->atomic.evade) |
13438 | intel_pipe_update_end(intel_crtc, | |
13439 | intel_crtc->atomic.start_vbl_count); | |
3c692a41 | 13440 | |
140fd38d | 13441 | intel_runtime_pm_put(dev_priv); |
3c692a41 | 13442 | |
32b7eeec MR |
13443 | if (intel_crtc->atomic.wait_vblank) |
13444 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
13445 | ||
13446 | intel_frontbuffer_flip(dev, intel_crtc->atomic.fb_bits); | |
13447 | ||
13448 | if (intel_crtc->atomic.update_fbc) { | |
ccc759dc | 13449 | mutex_lock(&dev->struct_mutex); |
7ff0ebcc | 13450 | intel_fbc_update(dev); |
ccc759dc | 13451 | mutex_unlock(&dev->struct_mutex); |
38f3ce3a | 13452 | } |
3c692a41 | 13453 | |
32b7eeec MR |
13454 | if (intel_crtc->atomic.post_enable_primary) |
13455 | intel_post_enable_primary(crtc); | |
3c692a41 | 13456 | |
32b7eeec MR |
13457 | drm_for_each_legacy_plane(p, &dev->mode_config.plane_list) |
13458 | if (intel_crtc->atomic.update_sprite_watermarks & drm_plane_index(p)) | |
13459 | intel_update_sprite_watermarks(p, crtc, 0, 0, 0, | |
13460 | false, false); | |
13461 | ||
13462 | memset(&intel_crtc->atomic, 0, sizeof(intel_crtc->atomic)); | |
3c692a41 GP |
13463 | } |
13464 | ||
cf4c7c12 | 13465 | /** |
4a3b8769 MR |
13466 | * intel_plane_destroy - destroy a plane |
13467 | * @plane: plane to destroy | |
cf4c7c12 | 13468 | * |
4a3b8769 MR |
13469 | * Common destruction function for all types of planes (primary, cursor, |
13470 | * sprite). | |
cf4c7c12 | 13471 | */ |
4a3b8769 | 13472 | void intel_plane_destroy(struct drm_plane *plane) |
465c120c MR |
13473 | { |
13474 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
13475 | drm_plane_cleanup(plane); | |
13476 | kfree(intel_plane); | |
13477 | } | |
13478 | ||
65a3fea0 | 13479 | const struct drm_plane_funcs intel_plane_funcs = { |
70a101f8 MR |
13480 | .update_plane = drm_atomic_helper_update_plane, |
13481 | .disable_plane = drm_atomic_helper_disable_plane, | |
3d7d6510 | 13482 | .destroy = intel_plane_destroy, |
c196e1d6 | 13483 | .set_property = drm_atomic_helper_plane_set_property, |
a98b3431 MR |
13484 | .atomic_get_property = intel_plane_atomic_get_property, |
13485 | .atomic_set_property = intel_plane_atomic_set_property, | |
ea2c67bb MR |
13486 | .atomic_duplicate_state = intel_plane_duplicate_state, |
13487 | .atomic_destroy_state = intel_plane_destroy_state, | |
13488 | ||
465c120c MR |
13489 | }; |
13490 | ||
13491 | static struct drm_plane *intel_primary_plane_create(struct drm_device *dev, | |
13492 | int pipe) | |
13493 | { | |
13494 | struct intel_plane *primary; | |
8e7d688b | 13495 | struct intel_plane_state *state; |
465c120c MR |
13496 | const uint32_t *intel_primary_formats; |
13497 | int num_formats; | |
13498 | ||
13499 | primary = kzalloc(sizeof(*primary), GFP_KERNEL); | |
13500 | if (primary == NULL) | |
13501 | return NULL; | |
13502 | ||
8e7d688b MR |
13503 | state = intel_create_plane_state(&primary->base); |
13504 | if (!state) { | |
ea2c67bb MR |
13505 | kfree(primary); |
13506 | return NULL; | |
13507 | } | |
8e7d688b | 13508 | primary->base.state = &state->base; |
ea2c67bb | 13509 | |
465c120c MR |
13510 | primary->can_scale = false; |
13511 | primary->max_downscale = 1; | |
6156a456 CK |
13512 | if (INTEL_INFO(dev)->gen >= 9) { |
13513 | primary->can_scale = true; | |
af99ceda | 13514 | state->scaler_id = -1; |
6156a456 | 13515 | } |
465c120c MR |
13516 | primary->pipe = pipe; |
13517 | primary->plane = pipe; | |
c59cb179 MR |
13518 | primary->check_plane = intel_check_primary_plane; |
13519 | primary->commit_plane = intel_commit_primary_plane; | |
a8ad0d8e | 13520 | primary->disable_plane = intel_disable_primary_plane; |
08e221fb | 13521 | primary->ckey.flags = I915_SET_COLORKEY_NONE; |
465c120c MR |
13522 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) |
13523 | primary->plane = !pipe; | |
13524 | ||
6c0fd451 DL |
13525 | if (INTEL_INFO(dev)->gen >= 9) { |
13526 | intel_primary_formats = skl_primary_formats; | |
13527 | num_formats = ARRAY_SIZE(skl_primary_formats); | |
13528 | } else if (INTEL_INFO(dev)->gen >= 4) { | |
568db4f2 DL |
13529 | intel_primary_formats = i965_primary_formats; |
13530 | num_formats = ARRAY_SIZE(i965_primary_formats); | |
6c0fd451 DL |
13531 | } else { |
13532 | intel_primary_formats = i8xx_primary_formats; | |
13533 | num_formats = ARRAY_SIZE(i8xx_primary_formats); | |
465c120c MR |
13534 | } |
13535 | ||
13536 | drm_universal_plane_init(dev, &primary->base, 0, | |
65a3fea0 | 13537 | &intel_plane_funcs, |
465c120c MR |
13538 | intel_primary_formats, num_formats, |
13539 | DRM_PLANE_TYPE_PRIMARY); | |
48404c1e | 13540 | |
3b7a5119 SJ |
13541 | if (INTEL_INFO(dev)->gen >= 4) |
13542 | intel_create_rotation_property(dev, primary); | |
48404c1e | 13543 | |
ea2c67bb MR |
13544 | drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs); |
13545 | ||
465c120c MR |
13546 | return &primary->base; |
13547 | } | |
13548 | ||
3b7a5119 SJ |
13549 | void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane) |
13550 | { | |
13551 | if (!dev->mode_config.rotation_property) { | |
13552 | unsigned long flags = BIT(DRM_ROTATE_0) | | |
13553 | BIT(DRM_ROTATE_180); | |
13554 | ||
13555 | if (INTEL_INFO(dev)->gen >= 9) | |
13556 | flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270); | |
13557 | ||
13558 | dev->mode_config.rotation_property = | |
13559 | drm_mode_create_rotation_property(dev, flags); | |
13560 | } | |
13561 | if (dev->mode_config.rotation_property) | |
13562 | drm_object_attach_property(&plane->base.base, | |
13563 | dev->mode_config.rotation_property, | |
13564 | plane->base.state->rotation); | |
13565 | } | |
13566 | ||
3d7d6510 | 13567 | static int |
852e787c GP |
13568 | intel_check_cursor_plane(struct drm_plane *plane, |
13569 | struct intel_plane_state *state) | |
3d7d6510 | 13570 | { |
2b875c22 | 13571 | struct drm_crtc *crtc = state->base.crtc; |
ea2c67bb | 13572 | struct drm_device *dev = plane->dev; |
2b875c22 | 13573 | struct drm_framebuffer *fb = state->base.fb; |
852e787c GP |
13574 | struct drm_rect *dest = &state->dst; |
13575 | struct drm_rect *src = &state->src; | |
13576 | const struct drm_rect *clip = &state->clip; | |
757f9a3e | 13577 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
ea2c67bb | 13578 | struct intel_crtc *intel_crtc; |
757f9a3e GP |
13579 | unsigned stride; |
13580 | int ret; | |
3d7d6510 | 13581 | |
ea2c67bb MR |
13582 | crtc = crtc ? crtc : plane->crtc; |
13583 | intel_crtc = to_intel_crtc(crtc); | |
13584 | ||
757f9a3e | 13585 | ret = drm_plane_helper_check_update(plane, crtc, fb, |
852e787c | 13586 | src, dest, clip, |
3d7d6510 MR |
13587 | DRM_PLANE_HELPER_NO_SCALING, |
13588 | DRM_PLANE_HELPER_NO_SCALING, | |
852e787c | 13589 | true, true, &state->visible); |
757f9a3e GP |
13590 | if (ret) |
13591 | return ret; | |
13592 | ||
13593 | ||
13594 | /* if we want to turn off the cursor ignore width and height */ | |
13595 | if (!obj) | |
32b7eeec | 13596 | goto finish; |
757f9a3e | 13597 | |
757f9a3e | 13598 | /* Check for which cursor types we support */ |
ea2c67bb MR |
13599 | if (!cursor_size_ok(dev, state->base.crtc_w, state->base.crtc_h)) { |
13600 | DRM_DEBUG("Cursor dimension %dx%d not supported\n", | |
13601 | state->base.crtc_w, state->base.crtc_h); | |
757f9a3e GP |
13602 | return -EINVAL; |
13603 | } | |
13604 | ||
ea2c67bb MR |
13605 | stride = roundup_pow_of_two(state->base.crtc_w) * 4; |
13606 | if (obj->base.size < stride * state->base.crtc_h) { | |
757f9a3e GP |
13607 | DRM_DEBUG_KMS("buffer is too small\n"); |
13608 | return -ENOMEM; | |
13609 | } | |
13610 | ||
3a656b54 | 13611 | if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) { |
757f9a3e GP |
13612 | DRM_DEBUG_KMS("cursor cannot be tiled\n"); |
13613 | ret = -EINVAL; | |
13614 | } | |
757f9a3e | 13615 | |
32b7eeec MR |
13616 | finish: |
13617 | if (intel_crtc->active) { | |
3749f463 | 13618 | if (plane->state->crtc_w != state->base.crtc_w) |
32b7eeec MR |
13619 | intel_crtc->atomic.update_wm = true; |
13620 | ||
13621 | intel_crtc->atomic.fb_bits |= | |
13622 | INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe); | |
13623 | } | |
13624 | ||
757f9a3e | 13625 | return ret; |
852e787c | 13626 | } |
3d7d6510 | 13627 | |
a8ad0d8e ML |
13628 | static void |
13629 | intel_disable_cursor_plane(struct drm_plane *plane, | |
13630 | struct drm_crtc *crtc, | |
13631 | bool force) | |
13632 | { | |
13633 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
13634 | ||
13635 | if (!force) { | |
13636 | plane->fb = NULL; | |
13637 | intel_crtc->cursor_bo = NULL; | |
13638 | intel_crtc->cursor_addr = 0; | |
13639 | } | |
13640 | ||
13641 | intel_crtc_update_cursor(crtc, false); | |
13642 | } | |
13643 | ||
f4a2cf29 | 13644 | static void |
852e787c GP |
13645 | intel_commit_cursor_plane(struct drm_plane *plane, |
13646 | struct intel_plane_state *state) | |
13647 | { | |
2b875c22 | 13648 | struct drm_crtc *crtc = state->base.crtc; |
ea2c67bb MR |
13649 | struct drm_device *dev = plane->dev; |
13650 | struct intel_crtc *intel_crtc; | |
2b875c22 | 13651 | struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb); |
a912f12f | 13652 | uint32_t addr; |
852e787c | 13653 | |
ea2c67bb MR |
13654 | crtc = crtc ? crtc : plane->crtc; |
13655 | intel_crtc = to_intel_crtc(crtc); | |
13656 | ||
2b875c22 | 13657 | plane->fb = state->base.fb; |
ea2c67bb MR |
13658 | crtc->cursor_x = state->base.crtc_x; |
13659 | crtc->cursor_y = state->base.crtc_y; | |
13660 | ||
a912f12f GP |
13661 | if (intel_crtc->cursor_bo == obj) |
13662 | goto update; | |
4ed91096 | 13663 | |
f4a2cf29 | 13664 | if (!obj) |
a912f12f | 13665 | addr = 0; |
f4a2cf29 | 13666 | else if (!INTEL_INFO(dev)->cursor_needs_physical) |
a912f12f | 13667 | addr = i915_gem_obj_ggtt_offset(obj); |
f4a2cf29 | 13668 | else |
a912f12f | 13669 | addr = obj->phys_handle->busaddr; |
852e787c | 13670 | |
a912f12f GP |
13671 | intel_crtc->cursor_addr = addr; |
13672 | intel_crtc->cursor_bo = obj; | |
13673 | update: | |
852e787c | 13674 | |
32b7eeec | 13675 | if (intel_crtc->active) |
a912f12f | 13676 | intel_crtc_update_cursor(crtc, state->visible); |
852e787c GP |
13677 | } |
13678 | ||
3d7d6510 MR |
13679 | static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev, |
13680 | int pipe) | |
13681 | { | |
13682 | struct intel_plane *cursor; | |
8e7d688b | 13683 | struct intel_plane_state *state; |
3d7d6510 MR |
13684 | |
13685 | cursor = kzalloc(sizeof(*cursor), GFP_KERNEL); | |
13686 | if (cursor == NULL) | |
13687 | return NULL; | |
13688 | ||
8e7d688b MR |
13689 | state = intel_create_plane_state(&cursor->base); |
13690 | if (!state) { | |
ea2c67bb MR |
13691 | kfree(cursor); |
13692 | return NULL; | |
13693 | } | |
8e7d688b | 13694 | cursor->base.state = &state->base; |
ea2c67bb | 13695 | |
3d7d6510 MR |
13696 | cursor->can_scale = false; |
13697 | cursor->max_downscale = 1; | |
13698 | cursor->pipe = pipe; | |
13699 | cursor->plane = pipe; | |
c59cb179 MR |
13700 | cursor->check_plane = intel_check_cursor_plane; |
13701 | cursor->commit_plane = intel_commit_cursor_plane; | |
a8ad0d8e | 13702 | cursor->disable_plane = intel_disable_cursor_plane; |
3d7d6510 MR |
13703 | |
13704 | drm_universal_plane_init(dev, &cursor->base, 0, | |
65a3fea0 | 13705 | &intel_plane_funcs, |
3d7d6510 MR |
13706 | intel_cursor_formats, |
13707 | ARRAY_SIZE(intel_cursor_formats), | |
13708 | DRM_PLANE_TYPE_CURSOR); | |
4398ad45 VS |
13709 | |
13710 | if (INTEL_INFO(dev)->gen >= 4) { | |
13711 | if (!dev->mode_config.rotation_property) | |
13712 | dev->mode_config.rotation_property = | |
13713 | drm_mode_create_rotation_property(dev, | |
13714 | BIT(DRM_ROTATE_0) | | |
13715 | BIT(DRM_ROTATE_180)); | |
13716 | if (dev->mode_config.rotation_property) | |
13717 | drm_object_attach_property(&cursor->base.base, | |
13718 | dev->mode_config.rotation_property, | |
8e7d688b | 13719 | state->base.rotation); |
4398ad45 VS |
13720 | } |
13721 | ||
af99ceda CK |
13722 | if (INTEL_INFO(dev)->gen >=9) |
13723 | state->scaler_id = -1; | |
13724 | ||
ea2c67bb MR |
13725 | drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs); |
13726 | ||
3d7d6510 MR |
13727 | return &cursor->base; |
13728 | } | |
13729 | ||
549e2bfb CK |
13730 | static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc, |
13731 | struct intel_crtc_state *crtc_state) | |
13732 | { | |
13733 | int i; | |
13734 | struct intel_scaler *intel_scaler; | |
13735 | struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state; | |
13736 | ||
13737 | for (i = 0; i < intel_crtc->num_scalers; i++) { | |
13738 | intel_scaler = &scaler_state->scalers[i]; | |
13739 | intel_scaler->in_use = 0; | |
13740 | intel_scaler->id = i; | |
13741 | ||
13742 | intel_scaler->mode = PS_SCALER_MODE_DYN; | |
13743 | } | |
13744 | ||
13745 | scaler_state->scaler_id = -1; | |
13746 | } | |
13747 | ||
b358d0a6 | 13748 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
79e53945 | 13749 | { |
fbee40df | 13750 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 13751 | struct intel_crtc *intel_crtc; |
f5de6e07 | 13752 | struct intel_crtc_state *crtc_state = NULL; |
3d7d6510 MR |
13753 | struct drm_plane *primary = NULL; |
13754 | struct drm_plane *cursor = NULL; | |
465c120c | 13755 | int i, ret; |
79e53945 | 13756 | |
955382f3 | 13757 | intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL); |
79e53945 JB |
13758 | if (intel_crtc == NULL) |
13759 | return; | |
13760 | ||
f5de6e07 ACO |
13761 | crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL); |
13762 | if (!crtc_state) | |
13763 | goto fail; | |
550acefd ACO |
13764 | intel_crtc->config = crtc_state; |
13765 | intel_crtc->base.state = &crtc_state->base; | |
07878248 | 13766 | crtc_state->base.crtc = &intel_crtc->base; |
f5de6e07 | 13767 | |
549e2bfb CK |
13768 | /* initialize shared scalers */ |
13769 | if (INTEL_INFO(dev)->gen >= 9) { | |
13770 | if (pipe == PIPE_C) | |
13771 | intel_crtc->num_scalers = 1; | |
13772 | else | |
13773 | intel_crtc->num_scalers = SKL_NUM_SCALERS; | |
13774 | ||
13775 | skl_init_scalers(dev, intel_crtc, crtc_state); | |
13776 | } | |
13777 | ||
465c120c | 13778 | primary = intel_primary_plane_create(dev, pipe); |
3d7d6510 MR |
13779 | if (!primary) |
13780 | goto fail; | |
13781 | ||
13782 | cursor = intel_cursor_plane_create(dev, pipe); | |
13783 | if (!cursor) | |
13784 | goto fail; | |
13785 | ||
465c120c | 13786 | ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary, |
3d7d6510 MR |
13787 | cursor, &intel_crtc_funcs); |
13788 | if (ret) | |
13789 | goto fail; | |
79e53945 JB |
13790 | |
13791 | drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256); | |
79e53945 JB |
13792 | for (i = 0; i < 256; i++) { |
13793 | intel_crtc->lut_r[i] = i; | |
13794 | intel_crtc->lut_g[i] = i; | |
13795 | intel_crtc->lut_b[i] = i; | |
13796 | } | |
13797 | ||
1f1c2e24 VS |
13798 | /* |
13799 | * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port | |
8c0f92e1 | 13800 | * is hooked to pipe B. Hence we want plane A feeding pipe B. |
1f1c2e24 | 13801 | */ |
80824003 JB |
13802 | intel_crtc->pipe = pipe; |
13803 | intel_crtc->plane = pipe; | |
3a77c4c4 | 13804 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) { |
28c97730 | 13805 | DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); |
e2e767ab | 13806 | intel_crtc->plane = !pipe; |
80824003 JB |
13807 | } |
13808 | ||
4b0e333e CW |
13809 | intel_crtc->cursor_base = ~0; |
13810 | intel_crtc->cursor_cntl = ~0; | |
dc41c154 | 13811 | intel_crtc->cursor_size = ~0; |
8d7849db | 13812 | |
22fd0fab JB |
13813 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
13814 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); | |
13815 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; | |
13816 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; | |
13817 | ||
79e53945 | 13818 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
87b6b101 DV |
13819 | |
13820 | WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe); | |
3d7d6510 MR |
13821 | return; |
13822 | ||
13823 | fail: | |
13824 | if (primary) | |
13825 | drm_plane_cleanup(primary); | |
13826 | if (cursor) | |
13827 | drm_plane_cleanup(cursor); | |
f5de6e07 | 13828 | kfree(crtc_state); |
3d7d6510 | 13829 | kfree(intel_crtc); |
79e53945 JB |
13830 | } |
13831 | ||
752aa88a JB |
13832 | enum pipe intel_get_pipe_from_connector(struct intel_connector *connector) |
13833 | { | |
13834 | struct drm_encoder *encoder = connector->base.encoder; | |
6e9f798d | 13835 | struct drm_device *dev = connector->base.dev; |
752aa88a | 13836 | |
51fd371b | 13837 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); |
752aa88a | 13838 | |
d3babd3f | 13839 | if (!encoder || WARN_ON(!encoder->crtc)) |
752aa88a JB |
13840 | return INVALID_PIPE; |
13841 | ||
13842 | return to_intel_crtc(encoder->crtc)->pipe; | |
13843 | } | |
13844 | ||
08d7b3d1 | 13845 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
05394f39 | 13846 | struct drm_file *file) |
08d7b3d1 | 13847 | { |
08d7b3d1 | 13848 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; |
7707e653 | 13849 | struct drm_crtc *drmmode_crtc; |
c05422d5 | 13850 | struct intel_crtc *crtc; |
08d7b3d1 | 13851 | |
7707e653 | 13852 | drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id); |
08d7b3d1 | 13853 | |
7707e653 | 13854 | if (!drmmode_crtc) { |
08d7b3d1 | 13855 | DRM_ERROR("no such CRTC id\n"); |
3f2c2057 | 13856 | return -ENOENT; |
08d7b3d1 CW |
13857 | } |
13858 | ||
7707e653 | 13859 | crtc = to_intel_crtc(drmmode_crtc); |
c05422d5 | 13860 | pipe_from_crtc_id->pipe = crtc->pipe; |
08d7b3d1 | 13861 | |
c05422d5 | 13862 | return 0; |
08d7b3d1 CW |
13863 | } |
13864 | ||
66a9278e | 13865 | static int intel_encoder_clones(struct intel_encoder *encoder) |
79e53945 | 13866 | { |
66a9278e DV |
13867 | struct drm_device *dev = encoder->base.dev; |
13868 | struct intel_encoder *source_encoder; | |
79e53945 | 13869 | int index_mask = 0; |
79e53945 JB |
13870 | int entry = 0; |
13871 | ||
b2784e15 | 13872 | for_each_intel_encoder(dev, source_encoder) { |
bc079e8b | 13873 | if (encoders_cloneable(encoder, source_encoder)) |
66a9278e DV |
13874 | index_mask |= (1 << entry); |
13875 | ||
79e53945 JB |
13876 | entry++; |
13877 | } | |
4ef69c7a | 13878 | |
79e53945 JB |
13879 | return index_mask; |
13880 | } | |
13881 | ||
4d302442 CW |
13882 | static bool has_edp_a(struct drm_device *dev) |
13883 | { | |
13884 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13885 | ||
13886 | if (!IS_MOBILE(dev)) | |
13887 | return false; | |
13888 | ||
13889 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) | |
13890 | return false; | |
13891 | ||
e3589908 | 13892 | if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE)) |
4d302442 CW |
13893 | return false; |
13894 | ||
13895 | return true; | |
13896 | } | |
13897 | ||
84b4e042 JB |
13898 | static bool intel_crt_present(struct drm_device *dev) |
13899 | { | |
13900 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13901 | ||
884497ed DL |
13902 | if (INTEL_INFO(dev)->gen >= 9) |
13903 | return false; | |
13904 | ||
cf404ce4 | 13905 | if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev)) |
84b4e042 JB |
13906 | return false; |
13907 | ||
13908 | if (IS_CHERRYVIEW(dev)) | |
13909 | return false; | |
13910 | ||
13911 | if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support) | |
13912 | return false; | |
13913 | ||
13914 | return true; | |
13915 | } | |
13916 | ||
79e53945 JB |
13917 | static void intel_setup_outputs(struct drm_device *dev) |
13918 | { | |
725e30ad | 13919 | struct drm_i915_private *dev_priv = dev->dev_private; |
4ef69c7a | 13920 | struct intel_encoder *encoder; |
cb0953d7 | 13921 | bool dpd_is_edp = false; |
79e53945 | 13922 | |
c9093354 | 13923 | intel_lvds_init(dev); |
79e53945 | 13924 | |
84b4e042 | 13925 | if (intel_crt_present(dev)) |
79935fca | 13926 | intel_crt_init(dev); |
cb0953d7 | 13927 | |
c776eb2e VK |
13928 | if (IS_BROXTON(dev)) { |
13929 | /* | |
13930 | * FIXME: Broxton doesn't support port detection via the | |
13931 | * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to | |
13932 | * detect the ports. | |
13933 | */ | |
13934 | intel_ddi_init(dev, PORT_A); | |
13935 | intel_ddi_init(dev, PORT_B); | |
13936 | intel_ddi_init(dev, PORT_C); | |
13937 | } else if (HAS_DDI(dev)) { | |
0e72a5b5 ED |
13938 | int found; |
13939 | ||
de31facd JB |
13940 | /* |
13941 | * Haswell uses DDI functions to detect digital outputs. | |
13942 | * On SKL pre-D0 the strap isn't connected, so we assume | |
13943 | * it's there. | |
13944 | */ | |
0e72a5b5 | 13945 | found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED; |
de31facd JB |
13946 | /* WaIgnoreDDIAStrap: skl */ |
13947 | if (found || | |
13948 | (IS_SKYLAKE(dev) && INTEL_REVID(dev) < SKL_REVID_D0)) | |
0e72a5b5 ED |
13949 | intel_ddi_init(dev, PORT_A); |
13950 | ||
13951 | /* DDI B, C and D detection is indicated by the SFUSE_STRAP | |
13952 | * register */ | |
13953 | found = I915_READ(SFUSE_STRAP); | |
13954 | ||
13955 | if (found & SFUSE_STRAP_DDIB_DETECTED) | |
13956 | intel_ddi_init(dev, PORT_B); | |
13957 | if (found & SFUSE_STRAP_DDIC_DETECTED) | |
13958 | intel_ddi_init(dev, PORT_C); | |
13959 | if (found & SFUSE_STRAP_DDID_DETECTED) | |
13960 | intel_ddi_init(dev, PORT_D); | |
13961 | } else if (HAS_PCH_SPLIT(dev)) { | |
cb0953d7 | 13962 | int found; |
5d8a7752 | 13963 | dpd_is_edp = intel_dp_is_edp(dev, PORT_D); |
270b3042 DV |
13964 | |
13965 | if (has_edp_a(dev)) | |
13966 | intel_dp_init(dev, DP_A, PORT_A); | |
cb0953d7 | 13967 | |
dc0fa718 | 13968 | if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) { |
461ed3ca | 13969 | /* PCH SDVOB multiplex with HDMIB */ |
eef4eacb | 13970 | found = intel_sdvo_init(dev, PCH_SDVOB, true); |
30ad48b7 | 13971 | if (!found) |
e2debe91 | 13972 | intel_hdmi_init(dev, PCH_HDMIB, PORT_B); |
5eb08b69 | 13973 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
ab9d7c30 | 13974 | intel_dp_init(dev, PCH_DP_B, PORT_B); |
30ad48b7 ZW |
13975 | } |
13976 | ||
dc0fa718 | 13977 | if (I915_READ(PCH_HDMIC) & SDVO_DETECTED) |
e2debe91 | 13978 | intel_hdmi_init(dev, PCH_HDMIC, PORT_C); |
30ad48b7 | 13979 | |
dc0fa718 | 13980 | if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED) |
e2debe91 | 13981 | intel_hdmi_init(dev, PCH_HDMID, PORT_D); |
30ad48b7 | 13982 | |
5eb08b69 | 13983 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
ab9d7c30 | 13984 | intel_dp_init(dev, PCH_DP_C, PORT_C); |
5eb08b69 | 13985 | |
270b3042 | 13986 | if (I915_READ(PCH_DP_D) & DP_DETECTED) |
ab9d7c30 | 13987 | intel_dp_init(dev, PCH_DP_D, PORT_D); |
4a87d65d | 13988 | } else if (IS_VALLEYVIEW(dev)) { |
e17ac6db VS |
13989 | /* |
13990 | * The DP_DETECTED bit is the latched state of the DDC | |
13991 | * SDA pin at boot. However since eDP doesn't require DDC | |
13992 | * (no way to plug in a DP->HDMI dongle) the DDC pins for | |
13993 | * eDP ports may have been muxed to an alternate function. | |
13994 | * Thus we can't rely on the DP_DETECTED bit alone to detect | |
13995 | * eDP ports. Consult the VBT as well as DP_DETECTED to | |
13996 | * detect eDP ports. | |
13997 | */ | |
d2182a66 VS |
13998 | if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED && |
13999 | !intel_dp_is_edp(dev, PORT_B)) | |
585a94b8 AB |
14000 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB, |
14001 | PORT_B); | |
e17ac6db VS |
14002 | if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED || |
14003 | intel_dp_is_edp(dev, PORT_B)) | |
14004 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B); | |
585a94b8 | 14005 | |
d2182a66 VS |
14006 | if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED && |
14007 | !intel_dp_is_edp(dev, PORT_C)) | |
6f6005a5 JB |
14008 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC, |
14009 | PORT_C); | |
e17ac6db VS |
14010 | if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED || |
14011 | intel_dp_is_edp(dev, PORT_C)) | |
14012 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C); | |
19c03924 | 14013 | |
9418c1f1 | 14014 | if (IS_CHERRYVIEW(dev)) { |
e17ac6db | 14015 | if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED) |
9418c1f1 VS |
14016 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID, |
14017 | PORT_D); | |
e17ac6db VS |
14018 | /* eDP not supported on port D, so don't check VBT */ |
14019 | if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED) | |
14020 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D); | |
9418c1f1 VS |
14021 | } |
14022 | ||
3cfca973 | 14023 | intel_dsi_init(dev); |
103a196f | 14024 | } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) { |
27185ae1 | 14025 | bool found = false; |
7d57382e | 14026 | |
e2debe91 | 14027 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 14028 | DRM_DEBUG_KMS("probing SDVOB\n"); |
e2debe91 | 14029 | found = intel_sdvo_init(dev, GEN3_SDVOB, true); |
b01f2c3a JB |
14030 | if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) { |
14031 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); | |
e2debe91 | 14032 | intel_hdmi_init(dev, GEN4_HDMIB, PORT_B); |
b01f2c3a | 14033 | } |
27185ae1 | 14034 | |
e7281eab | 14035 | if (!found && SUPPORTS_INTEGRATED_DP(dev)) |
ab9d7c30 | 14036 | intel_dp_init(dev, DP_B, PORT_B); |
725e30ad | 14037 | } |
13520b05 KH |
14038 | |
14039 | /* Before G4X SDVOC doesn't have its own detect register */ | |
13520b05 | 14040 | |
e2debe91 | 14041 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 14042 | DRM_DEBUG_KMS("probing SDVOC\n"); |
e2debe91 | 14043 | found = intel_sdvo_init(dev, GEN3_SDVOC, false); |
b01f2c3a | 14044 | } |
27185ae1 | 14045 | |
e2debe91 | 14046 | if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) { |
27185ae1 | 14047 | |
b01f2c3a JB |
14048 | if (SUPPORTS_INTEGRATED_HDMI(dev)) { |
14049 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); | |
e2debe91 | 14050 | intel_hdmi_init(dev, GEN4_HDMIC, PORT_C); |
b01f2c3a | 14051 | } |
e7281eab | 14052 | if (SUPPORTS_INTEGRATED_DP(dev)) |
ab9d7c30 | 14053 | intel_dp_init(dev, DP_C, PORT_C); |
725e30ad | 14054 | } |
27185ae1 | 14055 | |
b01f2c3a | 14056 | if (SUPPORTS_INTEGRATED_DP(dev) && |
e7281eab | 14057 | (I915_READ(DP_D) & DP_DETECTED)) |
ab9d7c30 | 14058 | intel_dp_init(dev, DP_D, PORT_D); |
bad720ff | 14059 | } else if (IS_GEN2(dev)) |
79e53945 JB |
14060 | intel_dvo_init(dev); |
14061 | ||
103a196f | 14062 | if (SUPPORTS_TV(dev)) |
79e53945 JB |
14063 | intel_tv_init(dev); |
14064 | ||
0bc12bcb | 14065 | intel_psr_init(dev); |
7c8f8a70 | 14066 | |
b2784e15 | 14067 | for_each_intel_encoder(dev, encoder) { |
4ef69c7a CW |
14068 | encoder->base.possible_crtcs = encoder->crtc_mask; |
14069 | encoder->base.possible_clones = | |
66a9278e | 14070 | intel_encoder_clones(encoder); |
79e53945 | 14071 | } |
47356eb6 | 14072 | |
dde86e2d | 14073 | intel_init_pch_refclk(dev); |
270b3042 DV |
14074 | |
14075 | drm_helper_move_panel_connectors_to_head(dev); | |
79e53945 JB |
14076 | } |
14077 | ||
14078 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) | |
14079 | { | |
60a5ca01 | 14080 | struct drm_device *dev = fb->dev; |
79e53945 | 14081 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
79e53945 | 14082 | |
ef2d633e | 14083 | drm_framebuffer_cleanup(fb); |
60a5ca01 | 14084 | mutex_lock(&dev->struct_mutex); |
ef2d633e | 14085 | WARN_ON(!intel_fb->obj->framebuffer_references--); |
60a5ca01 VS |
14086 | drm_gem_object_unreference(&intel_fb->obj->base); |
14087 | mutex_unlock(&dev->struct_mutex); | |
79e53945 JB |
14088 | kfree(intel_fb); |
14089 | } | |
14090 | ||
14091 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
05394f39 | 14092 | struct drm_file *file, |
79e53945 JB |
14093 | unsigned int *handle) |
14094 | { | |
14095 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 14096 | struct drm_i915_gem_object *obj = intel_fb->obj; |
79e53945 | 14097 | |
05394f39 | 14098 | return drm_gem_handle_create(file, &obj->base, handle); |
79e53945 JB |
14099 | } |
14100 | ||
14101 | static const struct drm_framebuffer_funcs intel_fb_funcs = { | |
14102 | .destroy = intel_user_framebuffer_destroy, | |
14103 | .create_handle = intel_user_framebuffer_create_handle, | |
14104 | }; | |
14105 | ||
b321803d DL |
14106 | static |
14107 | u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier, | |
14108 | uint32_t pixel_format) | |
14109 | { | |
14110 | u32 gen = INTEL_INFO(dev)->gen; | |
14111 | ||
14112 | if (gen >= 9) { | |
14113 | /* "The stride in bytes must not exceed the of the size of 8K | |
14114 | * pixels and 32K bytes." | |
14115 | */ | |
14116 | return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768); | |
14117 | } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) { | |
14118 | return 32*1024; | |
14119 | } else if (gen >= 4) { | |
14120 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
14121 | return 16*1024; | |
14122 | else | |
14123 | return 32*1024; | |
14124 | } else if (gen >= 3) { | |
14125 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
14126 | return 8*1024; | |
14127 | else | |
14128 | return 16*1024; | |
14129 | } else { | |
14130 | /* XXX DSPC is limited to 4k tiled */ | |
14131 | return 8*1024; | |
14132 | } | |
14133 | } | |
14134 | ||
b5ea642a DV |
14135 | static int intel_framebuffer_init(struct drm_device *dev, |
14136 | struct intel_framebuffer *intel_fb, | |
14137 | struct drm_mode_fb_cmd2 *mode_cmd, | |
14138 | struct drm_i915_gem_object *obj) | |
79e53945 | 14139 | { |
6761dd31 | 14140 | unsigned int aligned_height; |
79e53945 | 14141 | int ret; |
b321803d | 14142 | u32 pitch_limit, stride_alignment; |
79e53945 | 14143 | |
dd4916c5 DV |
14144 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
14145 | ||
2a80eada DV |
14146 | if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) { |
14147 | /* Enforce that fb modifier and tiling mode match, but only for | |
14148 | * X-tiled. This is needed for FBC. */ | |
14149 | if (!!(obj->tiling_mode == I915_TILING_X) != | |
14150 | !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) { | |
14151 | DRM_DEBUG("tiling_mode doesn't match fb modifier\n"); | |
14152 | return -EINVAL; | |
14153 | } | |
14154 | } else { | |
14155 | if (obj->tiling_mode == I915_TILING_X) | |
14156 | mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED; | |
14157 | else if (obj->tiling_mode == I915_TILING_Y) { | |
14158 | DRM_DEBUG("No Y tiling for legacy addfb\n"); | |
14159 | return -EINVAL; | |
14160 | } | |
14161 | } | |
14162 | ||
9a8f0a12 TU |
14163 | /* Passed in modifier sanity checking. */ |
14164 | switch (mode_cmd->modifier[0]) { | |
14165 | case I915_FORMAT_MOD_Y_TILED: | |
14166 | case I915_FORMAT_MOD_Yf_TILED: | |
14167 | if (INTEL_INFO(dev)->gen < 9) { | |
14168 | DRM_DEBUG("Unsupported tiling 0x%llx!\n", | |
14169 | mode_cmd->modifier[0]); | |
14170 | return -EINVAL; | |
14171 | } | |
14172 | case DRM_FORMAT_MOD_NONE: | |
14173 | case I915_FORMAT_MOD_X_TILED: | |
14174 | break; | |
14175 | default: | |
c0f40428 JB |
14176 | DRM_DEBUG("Unsupported fb modifier 0x%llx!\n", |
14177 | mode_cmd->modifier[0]); | |
57cd6508 | 14178 | return -EINVAL; |
c16ed4be | 14179 | } |
57cd6508 | 14180 | |
b321803d DL |
14181 | stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0], |
14182 | mode_cmd->pixel_format); | |
14183 | if (mode_cmd->pitches[0] & (stride_alignment - 1)) { | |
14184 | DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n", | |
14185 | mode_cmd->pitches[0], stride_alignment); | |
57cd6508 | 14186 | return -EINVAL; |
c16ed4be | 14187 | } |
57cd6508 | 14188 | |
b321803d DL |
14189 | pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0], |
14190 | mode_cmd->pixel_format); | |
a35cdaa0 | 14191 | if (mode_cmd->pitches[0] > pitch_limit) { |
b321803d DL |
14192 | DRM_DEBUG("%s pitch (%u) must be at less than %d\n", |
14193 | mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ? | |
2a80eada | 14194 | "tiled" : "linear", |
a35cdaa0 | 14195 | mode_cmd->pitches[0], pitch_limit); |
5d7bd705 | 14196 | return -EINVAL; |
c16ed4be | 14197 | } |
5d7bd705 | 14198 | |
2a80eada | 14199 | if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED && |
c16ed4be CW |
14200 | mode_cmd->pitches[0] != obj->stride) { |
14201 | DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n", | |
14202 | mode_cmd->pitches[0], obj->stride); | |
5d7bd705 | 14203 | return -EINVAL; |
c16ed4be | 14204 | } |
5d7bd705 | 14205 | |
57779d06 | 14206 | /* Reject formats not supported by any plane early. */ |
308e5bcb | 14207 | switch (mode_cmd->pixel_format) { |
57779d06 | 14208 | case DRM_FORMAT_C8: |
04b3924d VS |
14209 | case DRM_FORMAT_RGB565: |
14210 | case DRM_FORMAT_XRGB8888: | |
14211 | case DRM_FORMAT_ARGB8888: | |
57779d06 VS |
14212 | break; |
14213 | case DRM_FORMAT_XRGB1555: | |
c16ed4be | 14214 | if (INTEL_INFO(dev)->gen > 3) { |
4ee62c76 VS |
14215 | DRM_DEBUG("unsupported pixel format: %s\n", |
14216 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 14217 | return -EINVAL; |
c16ed4be | 14218 | } |
57779d06 | 14219 | break; |
57779d06 | 14220 | case DRM_FORMAT_ABGR8888: |
6c0fd451 DL |
14221 | if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) { |
14222 | DRM_DEBUG("unsupported pixel format: %s\n", | |
14223 | drm_get_format_name(mode_cmd->pixel_format)); | |
14224 | return -EINVAL; | |
14225 | } | |
14226 | break; | |
14227 | case DRM_FORMAT_XBGR8888: | |
04b3924d | 14228 | case DRM_FORMAT_XRGB2101010: |
57779d06 | 14229 | case DRM_FORMAT_XBGR2101010: |
c16ed4be | 14230 | if (INTEL_INFO(dev)->gen < 4) { |
4ee62c76 VS |
14231 | DRM_DEBUG("unsupported pixel format: %s\n", |
14232 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 14233 | return -EINVAL; |
c16ed4be | 14234 | } |
b5626747 | 14235 | break; |
7531208b DL |
14236 | case DRM_FORMAT_ABGR2101010: |
14237 | if (!IS_VALLEYVIEW(dev)) { | |
14238 | DRM_DEBUG("unsupported pixel format: %s\n", | |
14239 | drm_get_format_name(mode_cmd->pixel_format)); | |
14240 | return -EINVAL; | |
14241 | } | |
14242 | break; | |
04b3924d VS |
14243 | case DRM_FORMAT_YUYV: |
14244 | case DRM_FORMAT_UYVY: | |
14245 | case DRM_FORMAT_YVYU: | |
14246 | case DRM_FORMAT_VYUY: | |
c16ed4be | 14247 | if (INTEL_INFO(dev)->gen < 5) { |
4ee62c76 VS |
14248 | DRM_DEBUG("unsupported pixel format: %s\n", |
14249 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 14250 | return -EINVAL; |
c16ed4be | 14251 | } |
57cd6508 CW |
14252 | break; |
14253 | default: | |
4ee62c76 VS |
14254 | DRM_DEBUG("unsupported pixel format: %s\n", |
14255 | drm_get_format_name(mode_cmd->pixel_format)); | |
57cd6508 CW |
14256 | return -EINVAL; |
14257 | } | |
14258 | ||
90f9a336 VS |
14259 | /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ |
14260 | if (mode_cmd->offsets[0] != 0) | |
14261 | return -EINVAL; | |
14262 | ||
ec2c981e | 14263 | aligned_height = intel_fb_align_height(dev, mode_cmd->height, |
091df6cb DV |
14264 | mode_cmd->pixel_format, |
14265 | mode_cmd->modifier[0]); | |
53155c0a DV |
14266 | /* FIXME drm helper for size checks (especially planar formats)? */ |
14267 | if (obj->base.size < aligned_height * mode_cmd->pitches[0]) | |
14268 | return -EINVAL; | |
14269 | ||
c7d73f6a DV |
14270 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); |
14271 | intel_fb->obj = obj; | |
80075d49 | 14272 | intel_fb->obj->framebuffer_references++; |
c7d73f6a | 14273 | |
79e53945 JB |
14274 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); |
14275 | if (ret) { | |
14276 | DRM_ERROR("framebuffer init failed %d\n", ret); | |
14277 | return ret; | |
14278 | } | |
14279 | ||
79e53945 JB |
14280 | return 0; |
14281 | } | |
14282 | ||
79e53945 JB |
14283 | static struct drm_framebuffer * |
14284 | intel_user_framebuffer_create(struct drm_device *dev, | |
14285 | struct drm_file *filp, | |
308e5bcb | 14286 | struct drm_mode_fb_cmd2 *mode_cmd) |
79e53945 | 14287 | { |
05394f39 | 14288 | struct drm_i915_gem_object *obj; |
79e53945 | 14289 | |
308e5bcb JB |
14290 | obj = to_intel_bo(drm_gem_object_lookup(dev, filp, |
14291 | mode_cmd->handles[0])); | |
c8725226 | 14292 | if (&obj->base == NULL) |
cce13ff7 | 14293 | return ERR_PTR(-ENOENT); |
79e53945 | 14294 | |
d2dff872 | 14295 | return intel_framebuffer_create(dev, mode_cmd, obj); |
79e53945 JB |
14296 | } |
14297 | ||
4520f53a | 14298 | #ifndef CONFIG_DRM_I915_FBDEV |
0632fef6 | 14299 | static inline void intel_fbdev_output_poll_changed(struct drm_device *dev) |
4520f53a DV |
14300 | { |
14301 | } | |
14302 | #endif | |
14303 | ||
79e53945 | 14304 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
79e53945 | 14305 | .fb_create = intel_user_framebuffer_create, |
0632fef6 | 14306 | .output_poll_changed = intel_fbdev_output_poll_changed, |
5ee67f1c MR |
14307 | .atomic_check = intel_atomic_check, |
14308 | .atomic_commit = intel_atomic_commit, | |
79e53945 JB |
14309 | }; |
14310 | ||
e70236a8 JB |
14311 | /* Set up chip specific display functions */ |
14312 | static void intel_init_display(struct drm_device *dev) | |
14313 | { | |
14314 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14315 | ||
ee9300bb DV |
14316 | if (HAS_PCH_SPLIT(dev) || IS_G4X(dev)) |
14317 | dev_priv->display.find_dpll = g4x_find_best_dpll; | |
ef9348c8 CML |
14318 | else if (IS_CHERRYVIEW(dev)) |
14319 | dev_priv->display.find_dpll = chv_find_best_dpll; | |
ee9300bb DV |
14320 | else if (IS_VALLEYVIEW(dev)) |
14321 | dev_priv->display.find_dpll = vlv_find_best_dpll; | |
14322 | else if (IS_PINEVIEW(dev)) | |
14323 | dev_priv->display.find_dpll = pnv_find_best_dpll; | |
14324 | else | |
14325 | dev_priv->display.find_dpll = i9xx_find_best_dpll; | |
14326 | ||
bc8d7dff DL |
14327 | if (INTEL_INFO(dev)->gen >= 9) { |
14328 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; | |
5724dbd1 DL |
14329 | dev_priv->display.get_initial_plane_config = |
14330 | skylake_get_initial_plane_config; | |
bc8d7dff DL |
14331 | dev_priv->display.crtc_compute_clock = |
14332 | haswell_crtc_compute_clock; | |
14333 | dev_priv->display.crtc_enable = haswell_crtc_enable; | |
14334 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
14335 | dev_priv->display.off = ironlake_crtc_off; | |
14336 | dev_priv->display.update_primary_plane = | |
14337 | skylake_update_primary_plane; | |
14338 | } else if (HAS_DDI(dev)) { | |
0e8ffe1b | 14339 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
5724dbd1 DL |
14340 | dev_priv->display.get_initial_plane_config = |
14341 | ironlake_get_initial_plane_config; | |
797d0259 ACO |
14342 | dev_priv->display.crtc_compute_clock = |
14343 | haswell_crtc_compute_clock; | |
4f771f10 PZ |
14344 | dev_priv->display.crtc_enable = haswell_crtc_enable; |
14345 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
df8ad70c | 14346 | dev_priv->display.off = ironlake_crtc_off; |
bc8d7dff DL |
14347 | dev_priv->display.update_primary_plane = |
14348 | ironlake_update_primary_plane; | |
09b4ddf9 | 14349 | } else if (HAS_PCH_SPLIT(dev)) { |
0e8ffe1b | 14350 | dev_priv->display.get_pipe_config = ironlake_get_pipe_config; |
5724dbd1 DL |
14351 | dev_priv->display.get_initial_plane_config = |
14352 | ironlake_get_initial_plane_config; | |
3fb37703 ACO |
14353 | dev_priv->display.crtc_compute_clock = |
14354 | ironlake_crtc_compute_clock; | |
76e5a89c DV |
14355 | dev_priv->display.crtc_enable = ironlake_crtc_enable; |
14356 | dev_priv->display.crtc_disable = ironlake_crtc_disable; | |
ee7b9f93 | 14357 | dev_priv->display.off = ironlake_crtc_off; |
262ca2b0 MR |
14358 | dev_priv->display.update_primary_plane = |
14359 | ironlake_update_primary_plane; | |
89b667f8 JB |
14360 | } else if (IS_VALLEYVIEW(dev)) { |
14361 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
5724dbd1 DL |
14362 | dev_priv->display.get_initial_plane_config = |
14363 | i9xx_get_initial_plane_config; | |
d6dfee7a | 14364 | dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; |
89b667f8 JB |
14365 | dev_priv->display.crtc_enable = valleyview_crtc_enable; |
14366 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
14367 | dev_priv->display.off = i9xx_crtc_off; | |
262ca2b0 MR |
14368 | dev_priv->display.update_primary_plane = |
14369 | i9xx_update_primary_plane; | |
f564048e | 14370 | } else { |
0e8ffe1b | 14371 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
5724dbd1 DL |
14372 | dev_priv->display.get_initial_plane_config = |
14373 | i9xx_get_initial_plane_config; | |
d6dfee7a | 14374 | dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; |
76e5a89c DV |
14375 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
14376 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
ee7b9f93 | 14377 | dev_priv->display.off = i9xx_crtc_off; |
262ca2b0 MR |
14378 | dev_priv->display.update_primary_plane = |
14379 | i9xx_update_primary_plane; | |
f564048e | 14380 | } |
e70236a8 | 14381 | |
e70236a8 | 14382 | /* Returns the core display clock speed */ |
1652d19e VS |
14383 | if (IS_SKYLAKE(dev)) |
14384 | dev_priv->display.get_display_clock_speed = | |
14385 | skylake_get_display_clock_speed; | |
14386 | else if (IS_BROADWELL(dev)) | |
14387 | dev_priv->display.get_display_clock_speed = | |
14388 | broadwell_get_display_clock_speed; | |
14389 | else if (IS_HASWELL(dev)) | |
14390 | dev_priv->display.get_display_clock_speed = | |
14391 | haswell_get_display_clock_speed; | |
14392 | else if (IS_VALLEYVIEW(dev)) | |
25eb05fc JB |
14393 | dev_priv->display.get_display_clock_speed = |
14394 | valleyview_get_display_clock_speed; | |
b37a6434 VS |
14395 | else if (IS_GEN5(dev)) |
14396 | dev_priv->display.get_display_clock_speed = | |
14397 | ilk_get_display_clock_speed; | |
a7c66cd8 VS |
14398 | else if (IS_I945G(dev) || IS_BROADWATER(dev) || |
14399 | IS_GEN6(dev) || IS_IVYBRIDGE(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev))) | |
e70236a8 JB |
14400 | dev_priv->display.get_display_clock_speed = |
14401 | i945_get_display_clock_speed; | |
14402 | else if (IS_I915G(dev)) | |
14403 | dev_priv->display.get_display_clock_speed = | |
14404 | i915_get_display_clock_speed; | |
257a7ffc | 14405 | else if (IS_I945GM(dev) || IS_845G(dev)) |
e70236a8 JB |
14406 | dev_priv->display.get_display_clock_speed = |
14407 | i9xx_misc_get_display_clock_speed; | |
257a7ffc DV |
14408 | else if (IS_PINEVIEW(dev)) |
14409 | dev_priv->display.get_display_clock_speed = | |
14410 | pnv_get_display_clock_speed; | |
e70236a8 JB |
14411 | else if (IS_I915GM(dev)) |
14412 | dev_priv->display.get_display_clock_speed = | |
14413 | i915gm_get_display_clock_speed; | |
14414 | else if (IS_I865G(dev)) | |
14415 | dev_priv->display.get_display_clock_speed = | |
14416 | i865_get_display_clock_speed; | |
f0f8a9ce | 14417 | else if (IS_I85X(dev)) |
e70236a8 | 14418 | dev_priv->display.get_display_clock_speed = |
1b1d2716 VS |
14419 | i85x_get_display_clock_speed; |
14420 | else /* 830 */ | |
e70236a8 JB |
14421 | dev_priv->display.get_display_clock_speed = |
14422 | i830_get_display_clock_speed; | |
14423 | ||
7c10a2b5 | 14424 | if (IS_GEN5(dev)) { |
3bb11b53 | 14425 | dev_priv->display.fdi_link_train = ironlake_fdi_link_train; |
3bb11b53 SJ |
14426 | } else if (IS_GEN6(dev)) { |
14427 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; | |
3bb11b53 SJ |
14428 | } else if (IS_IVYBRIDGE(dev)) { |
14429 | /* FIXME: detect B0+ stepping and use auto training */ | |
14430 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; | |
059b2fe9 | 14431 | } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
3bb11b53 | 14432 | dev_priv->display.fdi_link_train = hsw_fdi_link_train; |
30a970c6 JB |
14433 | } else if (IS_VALLEYVIEW(dev)) { |
14434 | dev_priv->display.modeset_global_resources = | |
14435 | valleyview_modeset_global_resources; | |
f8437dd1 VK |
14436 | } else if (IS_BROXTON(dev)) { |
14437 | dev_priv->display.modeset_global_resources = | |
14438 | broxton_modeset_global_resources; | |
e70236a8 | 14439 | } |
8c9f3aaf | 14440 | |
8c9f3aaf JB |
14441 | switch (INTEL_INFO(dev)->gen) { |
14442 | case 2: | |
14443 | dev_priv->display.queue_flip = intel_gen2_queue_flip; | |
14444 | break; | |
14445 | ||
14446 | case 3: | |
14447 | dev_priv->display.queue_flip = intel_gen3_queue_flip; | |
14448 | break; | |
14449 | ||
14450 | case 4: | |
14451 | case 5: | |
14452 | dev_priv->display.queue_flip = intel_gen4_queue_flip; | |
14453 | break; | |
14454 | ||
14455 | case 6: | |
14456 | dev_priv->display.queue_flip = intel_gen6_queue_flip; | |
14457 | break; | |
7c9017e5 | 14458 | case 7: |
4e0bbc31 | 14459 | case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */ |
7c9017e5 JB |
14460 | dev_priv->display.queue_flip = intel_gen7_queue_flip; |
14461 | break; | |
830c81db | 14462 | case 9: |
ba343e02 TU |
14463 | /* Drop through - unsupported since execlist only. */ |
14464 | default: | |
14465 | /* Default just returns -ENODEV to indicate unsupported */ | |
14466 | dev_priv->display.queue_flip = intel_default_queue_flip; | |
8c9f3aaf | 14467 | } |
7bd688cd JN |
14468 | |
14469 | intel_panel_init_backlight_funcs(dev); | |
e39b999a VS |
14470 | |
14471 | mutex_init(&dev_priv->pps_mutex); | |
e70236a8 JB |
14472 | } |
14473 | ||
b690e96c JB |
14474 | /* |
14475 | * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, | |
14476 | * resume, or other times. This quirk makes sure that's the case for | |
14477 | * affected systems. | |
14478 | */ | |
0206e353 | 14479 | static void quirk_pipea_force(struct drm_device *dev) |
b690e96c JB |
14480 | { |
14481 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14482 | ||
14483 | dev_priv->quirks |= QUIRK_PIPEA_FORCE; | |
bc0daf48 | 14484 | DRM_INFO("applying pipe a force quirk\n"); |
b690e96c JB |
14485 | } |
14486 | ||
b6b5d049 VS |
14487 | static void quirk_pipeb_force(struct drm_device *dev) |
14488 | { | |
14489 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14490 | ||
14491 | dev_priv->quirks |= QUIRK_PIPEB_FORCE; | |
14492 | DRM_INFO("applying pipe b force quirk\n"); | |
14493 | } | |
14494 | ||
435793df KP |
14495 | /* |
14496 | * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason | |
14497 | */ | |
14498 | static void quirk_ssc_force_disable(struct drm_device *dev) | |
14499 | { | |
14500 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14501 | dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; | |
bc0daf48 | 14502 | DRM_INFO("applying lvds SSC disable quirk\n"); |
435793df KP |
14503 | } |
14504 | ||
4dca20ef | 14505 | /* |
5a15ab5b CE |
14506 | * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight |
14507 | * brightness value | |
4dca20ef CE |
14508 | */ |
14509 | static void quirk_invert_brightness(struct drm_device *dev) | |
14510 | { | |
14511 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14512 | dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; | |
bc0daf48 | 14513 | DRM_INFO("applying inverted panel brightness quirk\n"); |
435793df KP |
14514 | } |
14515 | ||
9c72cc6f SD |
14516 | /* Some VBT's incorrectly indicate no backlight is present */ |
14517 | static void quirk_backlight_present(struct drm_device *dev) | |
14518 | { | |
14519 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14520 | dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT; | |
14521 | DRM_INFO("applying backlight present quirk\n"); | |
14522 | } | |
14523 | ||
b690e96c JB |
14524 | struct intel_quirk { |
14525 | int device; | |
14526 | int subsystem_vendor; | |
14527 | int subsystem_device; | |
14528 | void (*hook)(struct drm_device *dev); | |
14529 | }; | |
14530 | ||
5f85f176 EE |
14531 | /* For systems that don't have a meaningful PCI subdevice/subvendor ID */ |
14532 | struct intel_dmi_quirk { | |
14533 | void (*hook)(struct drm_device *dev); | |
14534 | const struct dmi_system_id (*dmi_id_list)[]; | |
14535 | }; | |
14536 | ||
14537 | static int intel_dmi_reverse_brightness(const struct dmi_system_id *id) | |
14538 | { | |
14539 | DRM_INFO("Backlight polarity reversed on %s\n", id->ident); | |
14540 | return 1; | |
14541 | } | |
14542 | ||
14543 | static const struct intel_dmi_quirk intel_dmi_quirks[] = { | |
14544 | { | |
14545 | .dmi_id_list = &(const struct dmi_system_id[]) { | |
14546 | { | |
14547 | .callback = intel_dmi_reverse_brightness, | |
14548 | .ident = "NCR Corporation", | |
14549 | .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"), | |
14550 | DMI_MATCH(DMI_PRODUCT_NAME, ""), | |
14551 | }, | |
14552 | }, | |
14553 | { } /* terminating entry */ | |
14554 | }, | |
14555 | .hook = quirk_invert_brightness, | |
14556 | }, | |
14557 | }; | |
14558 | ||
c43b5634 | 14559 | static struct intel_quirk intel_quirks[] = { |
b690e96c JB |
14560 | /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ |
14561 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, | |
14562 | ||
b690e96c JB |
14563 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ |
14564 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, | |
14565 | ||
5f080c0f VS |
14566 | /* 830 needs to leave pipe A & dpll A up */ |
14567 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, | |
14568 | ||
b6b5d049 VS |
14569 | /* 830 needs to leave pipe B & dpll B up */ |
14570 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force }, | |
14571 | ||
435793df KP |
14572 | /* Lenovo U160 cannot use SSC on LVDS */ |
14573 | { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, | |
070d329a MAS |
14574 | |
14575 | /* Sony Vaio Y cannot use SSC on LVDS */ | |
14576 | { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, | |
5a15ab5b | 14577 | |
be505f64 AH |
14578 | /* Acer Aspire 5734Z must invert backlight brightness */ |
14579 | { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness }, | |
14580 | ||
14581 | /* Acer/eMachines G725 */ | |
14582 | { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness }, | |
14583 | ||
14584 | /* Acer/eMachines e725 */ | |
14585 | { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness }, | |
14586 | ||
14587 | /* Acer/Packard Bell NCL20 */ | |
14588 | { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness }, | |
14589 | ||
14590 | /* Acer Aspire 4736Z */ | |
14591 | { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness }, | |
0f540c3a JN |
14592 | |
14593 | /* Acer Aspire 5336 */ | |
14594 | { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness }, | |
2e93a1aa SD |
14595 | |
14596 | /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */ | |
14597 | { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present }, | |
d4967d8c | 14598 | |
dfb3d47b SD |
14599 | /* Acer C720 Chromebook (Core i3 4005U) */ |
14600 | { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present }, | |
14601 | ||
b2a9601c | 14602 | /* Apple Macbook 2,1 (Core 2 T7400) */ |
14603 | { 0x27a2, 0x8086, 0x7270, quirk_backlight_present }, | |
14604 | ||
d4967d8c SD |
14605 | /* Toshiba CB35 Chromebook (Celeron 2955U) */ |
14606 | { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present }, | |
724cb06f SD |
14607 | |
14608 | /* HP Chromebook 14 (Celeron 2955U) */ | |
14609 | { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present }, | |
cf6f0af9 JN |
14610 | |
14611 | /* Dell Chromebook 11 */ | |
14612 | { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present }, | |
b690e96c JB |
14613 | }; |
14614 | ||
14615 | static void intel_init_quirks(struct drm_device *dev) | |
14616 | { | |
14617 | struct pci_dev *d = dev->pdev; | |
14618 | int i; | |
14619 | ||
14620 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { | |
14621 | struct intel_quirk *q = &intel_quirks[i]; | |
14622 | ||
14623 | if (d->device == q->device && | |
14624 | (d->subsystem_vendor == q->subsystem_vendor || | |
14625 | q->subsystem_vendor == PCI_ANY_ID) && | |
14626 | (d->subsystem_device == q->subsystem_device || | |
14627 | q->subsystem_device == PCI_ANY_ID)) | |
14628 | q->hook(dev); | |
14629 | } | |
5f85f176 EE |
14630 | for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) { |
14631 | if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0) | |
14632 | intel_dmi_quirks[i].hook(dev); | |
14633 | } | |
b690e96c JB |
14634 | } |
14635 | ||
9cce37f4 JB |
14636 | /* Disable the VGA plane that we never use */ |
14637 | static void i915_disable_vga(struct drm_device *dev) | |
14638 | { | |
14639 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14640 | u8 sr1; | |
766aa1c4 | 14641 | u32 vga_reg = i915_vgacntrl_reg(dev); |
9cce37f4 | 14642 | |
2b37c616 | 14643 | /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */ |
9cce37f4 | 14644 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); |
3fdcf431 | 14645 | outb(SR01, VGA_SR_INDEX); |
9cce37f4 JB |
14646 | sr1 = inb(VGA_SR_DATA); |
14647 | outb(sr1 | 1<<5, VGA_SR_DATA); | |
14648 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); | |
14649 | udelay(300); | |
14650 | ||
01f5a626 | 14651 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); |
9cce37f4 JB |
14652 | POSTING_READ(vga_reg); |
14653 | } | |
14654 | ||
f817586c DV |
14655 | void intel_modeset_init_hw(struct drm_device *dev) |
14656 | { | |
a8f78b58 ED |
14657 | intel_prepare_ddi(dev); |
14658 | ||
f8bf63fd VS |
14659 | if (IS_VALLEYVIEW(dev)) |
14660 | vlv_update_cdclk(dev); | |
14661 | ||
f817586c DV |
14662 | intel_init_clock_gating(dev); |
14663 | ||
8090c6b9 | 14664 | intel_enable_gt_powersave(dev); |
f817586c DV |
14665 | } |
14666 | ||
79e53945 JB |
14667 | void intel_modeset_init(struct drm_device *dev) |
14668 | { | |
652c393a | 14669 | struct drm_i915_private *dev_priv = dev->dev_private; |
1fe47785 | 14670 | int sprite, ret; |
8cc87b75 | 14671 | enum pipe pipe; |
46f297fb | 14672 | struct intel_crtc *crtc; |
79e53945 JB |
14673 | |
14674 | drm_mode_config_init(dev); | |
14675 | ||
14676 | dev->mode_config.min_width = 0; | |
14677 | dev->mode_config.min_height = 0; | |
14678 | ||
019d96cb DA |
14679 | dev->mode_config.preferred_depth = 24; |
14680 | dev->mode_config.prefer_shadow = 1; | |
14681 | ||
25bab385 TU |
14682 | dev->mode_config.allow_fb_modifiers = true; |
14683 | ||
e6ecefaa | 14684 | dev->mode_config.funcs = &intel_mode_funcs; |
79e53945 | 14685 | |
b690e96c JB |
14686 | intel_init_quirks(dev); |
14687 | ||
1fa61106 ED |
14688 | intel_init_pm(dev); |
14689 | ||
e3c74757 BW |
14690 | if (INTEL_INFO(dev)->num_pipes == 0) |
14691 | return; | |
14692 | ||
e70236a8 | 14693 | intel_init_display(dev); |
7c10a2b5 | 14694 | intel_init_audio(dev); |
e70236a8 | 14695 | |
a6c45cf0 CW |
14696 | if (IS_GEN2(dev)) { |
14697 | dev->mode_config.max_width = 2048; | |
14698 | dev->mode_config.max_height = 2048; | |
14699 | } else if (IS_GEN3(dev)) { | |
5e4d6fa7 KP |
14700 | dev->mode_config.max_width = 4096; |
14701 | dev->mode_config.max_height = 4096; | |
79e53945 | 14702 | } else { |
a6c45cf0 CW |
14703 | dev->mode_config.max_width = 8192; |
14704 | dev->mode_config.max_height = 8192; | |
79e53945 | 14705 | } |
068be561 | 14706 | |
dc41c154 VS |
14707 | if (IS_845G(dev) || IS_I865G(dev)) { |
14708 | dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512; | |
14709 | dev->mode_config.cursor_height = 1023; | |
14710 | } else if (IS_GEN2(dev)) { | |
068be561 DL |
14711 | dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH; |
14712 | dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT; | |
14713 | } else { | |
14714 | dev->mode_config.cursor_width = MAX_CURSOR_WIDTH; | |
14715 | dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT; | |
14716 | } | |
14717 | ||
5d4545ae | 14718 | dev->mode_config.fb_base = dev_priv->gtt.mappable_base; |
79e53945 | 14719 | |
28c97730 | 14720 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
7eb552ae BW |
14721 | INTEL_INFO(dev)->num_pipes, |
14722 | INTEL_INFO(dev)->num_pipes > 1 ? "s" : ""); | |
79e53945 | 14723 | |
055e393f | 14724 | for_each_pipe(dev_priv, pipe) { |
8cc87b75 | 14725 | intel_crtc_init(dev, pipe); |
3bdcfc0c | 14726 | for_each_sprite(dev_priv, pipe, sprite) { |
1fe47785 | 14727 | ret = intel_plane_init(dev, pipe, sprite); |
7f1f3851 | 14728 | if (ret) |
06da8da2 | 14729 | DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n", |
1fe47785 | 14730 | pipe_name(pipe), sprite_name(pipe, sprite), ret); |
7f1f3851 | 14731 | } |
79e53945 JB |
14732 | } |
14733 | ||
f42bb70d JB |
14734 | intel_init_dpio(dev); |
14735 | ||
e72f9fbf | 14736 | intel_shared_dpll_init(dev); |
ee7b9f93 | 14737 | |
9cce37f4 JB |
14738 | /* Just disable it once at startup */ |
14739 | i915_disable_vga(dev); | |
79e53945 | 14740 | intel_setup_outputs(dev); |
11be49eb CW |
14741 | |
14742 | /* Just in case the BIOS is doing something questionable. */ | |
7ff0ebcc | 14743 | intel_fbc_disable(dev); |
fa9fa083 | 14744 | |
6e9f798d | 14745 | drm_modeset_lock_all(dev); |
fa9fa083 | 14746 | intel_modeset_setup_hw_state(dev, false); |
6e9f798d | 14747 | drm_modeset_unlock_all(dev); |
46f297fb | 14748 | |
d3fcc808 | 14749 | for_each_intel_crtc(dev, crtc) { |
46f297fb JB |
14750 | if (!crtc->active) |
14751 | continue; | |
14752 | ||
46f297fb | 14753 | /* |
46f297fb JB |
14754 | * Note that reserving the BIOS fb up front prevents us |
14755 | * from stuffing other stolen allocations like the ring | |
14756 | * on top. This prevents some ugliness at boot time, and | |
14757 | * can even allow for smooth boot transitions if the BIOS | |
14758 | * fb is large enough for the active pipe configuration. | |
14759 | */ | |
5724dbd1 DL |
14760 | if (dev_priv->display.get_initial_plane_config) { |
14761 | dev_priv->display.get_initial_plane_config(crtc, | |
46f297fb JB |
14762 | &crtc->plane_config); |
14763 | /* | |
14764 | * If the fb is shared between multiple heads, we'll | |
14765 | * just get the first one. | |
14766 | */ | |
f6936e29 | 14767 | intel_find_initial_plane_obj(crtc, &crtc->plane_config); |
46f297fb | 14768 | } |
46f297fb | 14769 | } |
2c7111db CW |
14770 | } |
14771 | ||
7fad798e DV |
14772 | static void intel_enable_pipe_a(struct drm_device *dev) |
14773 | { | |
14774 | struct intel_connector *connector; | |
14775 | struct drm_connector *crt = NULL; | |
14776 | struct intel_load_detect_pipe load_detect_temp; | |
208bf9fd | 14777 | struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx; |
7fad798e DV |
14778 | |
14779 | /* We can't just switch on the pipe A, we need to set things up with a | |
14780 | * proper mode and output configuration. As a gross hack, enable pipe A | |
14781 | * by enabling the load detect pipe once. */ | |
3a3371ff | 14782 | for_each_intel_connector(dev, connector) { |
7fad798e DV |
14783 | if (connector->encoder->type == INTEL_OUTPUT_ANALOG) { |
14784 | crt = &connector->base; | |
14785 | break; | |
14786 | } | |
14787 | } | |
14788 | ||
14789 | if (!crt) | |
14790 | return; | |
14791 | ||
208bf9fd | 14792 | if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx)) |
49172fee | 14793 | intel_release_load_detect_pipe(crt, &load_detect_temp, ctx); |
7fad798e DV |
14794 | } |
14795 | ||
fa555837 DV |
14796 | static bool |
14797 | intel_check_plane_mapping(struct intel_crtc *crtc) | |
14798 | { | |
7eb552ae BW |
14799 | struct drm_device *dev = crtc->base.dev; |
14800 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fa555837 DV |
14801 | u32 reg, val; |
14802 | ||
7eb552ae | 14803 | if (INTEL_INFO(dev)->num_pipes == 1) |
fa555837 DV |
14804 | return true; |
14805 | ||
14806 | reg = DSPCNTR(!crtc->plane); | |
14807 | val = I915_READ(reg); | |
14808 | ||
14809 | if ((val & DISPLAY_PLANE_ENABLE) && | |
14810 | (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) | |
14811 | return false; | |
14812 | ||
14813 | return true; | |
14814 | } | |
14815 | ||
24929352 DV |
14816 | static void intel_sanitize_crtc(struct intel_crtc *crtc) |
14817 | { | |
14818 | struct drm_device *dev = crtc->base.dev; | |
14819 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fa555837 | 14820 | u32 reg; |
24929352 | 14821 | |
24929352 | 14822 | /* Clear any frame start delays used for debugging left by the BIOS */ |
6e3c9717 | 14823 | reg = PIPECONF(crtc->config->cpu_transcoder); |
24929352 DV |
14824 | I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); |
14825 | ||
d3eaf884 | 14826 | /* restore vblank interrupts to correct state */ |
9625604c | 14827 | drm_crtc_vblank_reset(&crtc->base); |
d297e103 VS |
14828 | if (crtc->active) { |
14829 | update_scanline_offset(crtc); | |
9625604c DV |
14830 | drm_crtc_vblank_on(&crtc->base); |
14831 | } | |
d3eaf884 | 14832 | |
24929352 | 14833 | /* We need to sanitize the plane -> pipe mapping first because this will |
fa555837 DV |
14834 | * disable the crtc (and hence change the state) if it is wrong. Note |
14835 | * that gen4+ has a fixed plane -> pipe mapping. */ | |
14836 | if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) { | |
24929352 DV |
14837 | struct intel_connector *connector; |
14838 | bool plane; | |
14839 | ||
24929352 DV |
14840 | DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n", |
14841 | crtc->base.base.id); | |
14842 | ||
14843 | /* Pipe has the wrong plane attached and the plane is active. | |
14844 | * Temporarily change the plane mapping and disable everything | |
14845 | * ... */ | |
14846 | plane = crtc->plane; | |
b70709a6 | 14847 | to_intel_plane_state(crtc->base.primary->state)->visible = true; |
24929352 | 14848 | crtc->plane = !plane; |
ce22dba9 | 14849 | intel_crtc_disable_planes(&crtc->base); |
24929352 DV |
14850 | dev_priv->display.crtc_disable(&crtc->base); |
14851 | crtc->plane = plane; | |
14852 | ||
14853 | /* ... and break all links. */ | |
3a3371ff | 14854 | for_each_intel_connector(dev, connector) { |
24929352 DV |
14855 | if (connector->encoder->base.crtc != &crtc->base) |
14856 | continue; | |
14857 | ||
7f1950fb EE |
14858 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
14859 | connector->base.encoder = NULL; | |
24929352 | 14860 | } |
7f1950fb EE |
14861 | /* multiple connectors may have the same encoder: |
14862 | * handle them and break crtc link separately */ | |
3a3371ff | 14863 | for_each_intel_connector(dev, connector) |
7f1950fb EE |
14864 | if (connector->encoder->base.crtc == &crtc->base) { |
14865 | connector->encoder->base.crtc = NULL; | |
14866 | connector->encoder->connectors_active = false; | |
14867 | } | |
24929352 DV |
14868 | |
14869 | WARN_ON(crtc->active); | |
83d65738 | 14870 | crtc->base.state->enable = false; |
49d6fa21 | 14871 | crtc->base.state->active = false; |
24929352 DV |
14872 | crtc->base.enabled = false; |
14873 | } | |
24929352 | 14874 | |
7fad798e DV |
14875 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
14876 | crtc->pipe == PIPE_A && !crtc->active) { | |
14877 | /* BIOS forgot to enable pipe A, this mostly happens after | |
14878 | * resume. Force-enable the pipe to fix this, the update_dpms | |
14879 | * call below we restore the pipe to the right state, but leave | |
14880 | * the required bits on. */ | |
14881 | intel_enable_pipe_a(dev); | |
14882 | } | |
14883 | ||
24929352 DV |
14884 | /* Adjust the state of the output pipe according to whether we |
14885 | * have active connectors/encoders. */ | |
14886 | intel_crtc_update_dpms(&crtc->base); | |
14887 | ||
83d65738 | 14888 | if (crtc->active != crtc->base.state->enable) { |
24929352 DV |
14889 | struct intel_encoder *encoder; |
14890 | ||
14891 | /* This can happen either due to bugs in the get_hw_state | |
14892 | * functions or because the pipe is force-enabled due to the | |
14893 | * pipe A quirk. */ | |
14894 | DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n", | |
14895 | crtc->base.base.id, | |
83d65738 | 14896 | crtc->base.state->enable ? "enabled" : "disabled", |
24929352 DV |
14897 | crtc->active ? "enabled" : "disabled"); |
14898 | ||
83d65738 | 14899 | crtc->base.state->enable = crtc->active; |
49d6fa21 | 14900 | crtc->base.state->active = crtc->active; |
24929352 DV |
14901 | crtc->base.enabled = crtc->active; |
14902 | ||
14903 | /* Because we only establish the connector -> encoder -> | |
14904 | * crtc links if something is active, this means the | |
14905 | * crtc is now deactivated. Break the links. connector | |
14906 | * -> encoder links are only establish when things are | |
14907 | * actually up, hence no need to break them. */ | |
14908 | WARN_ON(crtc->active); | |
14909 | ||
14910 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) { | |
14911 | WARN_ON(encoder->connectors_active); | |
14912 | encoder->base.crtc = NULL; | |
14913 | } | |
14914 | } | |
c5ab3bc0 | 14915 | |
a3ed6aad | 14916 | if (crtc->active || HAS_GMCH_DISPLAY(dev)) { |
4cc31489 DV |
14917 | /* |
14918 | * We start out with underrun reporting disabled to avoid races. | |
14919 | * For correct bookkeeping mark this on active crtcs. | |
14920 | * | |
c5ab3bc0 DV |
14921 | * Also on gmch platforms we dont have any hardware bits to |
14922 | * disable the underrun reporting. Which means we need to start | |
14923 | * out with underrun reporting disabled also on inactive pipes, | |
14924 | * since otherwise we'll complain about the garbage we read when | |
14925 | * e.g. coming up after runtime pm. | |
14926 | * | |
4cc31489 DV |
14927 | * No protection against concurrent access is required - at |
14928 | * worst a fifo underrun happens which also sets this to false. | |
14929 | */ | |
14930 | crtc->cpu_fifo_underrun_disabled = true; | |
14931 | crtc->pch_fifo_underrun_disabled = true; | |
14932 | } | |
24929352 DV |
14933 | } |
14934 | ||
14935 | static void intel_sanitize_encoder(struct intel_encoder *encoder) | |
14936 | { | |
14937 | struct intel_connector *connector; | |
14938 | struct drm_device *dev = encoder->base.dev; | |
14939 | ||
14940 | /* We need to check both for a crtc link (meaning that the | |
14941 | * encoder is active and trying to read from a pipe) and the | |
14942 | * pipe itself being active. */ | |
14943 | bool has_active_crtc = encoder->base.crtc && | |
14944 | to_intel_crtc(encoder->base.crtc)->active; | |
14945 | ||
14946 | if (encoder->connectors_active && !has_active_crtc) { | |
14947 | DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n", | |
14948 | encoder->base.base.id, | |
8e329a03 | 14949 | encoder->base.name); |
24929352 DV |
14950 | |
14951 | /* Connector is active, but has no active pipe. This is | |
14952 | * fallout from our resume register restoring. Disable | |
14953 | * the encoder manually again. */ | |
14954 | if (encoder->base.crtc) { | |
14955 | DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n", | |
14956 | encoder->base.base.id, | |
8e329a03 | 14957 | encoder->base.name); |
24929352 | 14958 | encoder->disable(encoder); |
a62d1497 VS |
14959 | if (encoder->post_disable) |
14960 | encoder->post_disable(encoder); | |
24929352 | 14961 | } |
7f1950fb EE |
14962 | encoder->base.crtc = NULL; |
14963 | encoder->connectors_active = false; | |
24929352 DV |
14964 | |
14965 | /* Inconsistent output/port/pipe state happens presumably due to | |
14966 | * a bug in one of the get_hw_state functions. Or someplace else | |
14967 | * in our code, like the register restore mess on resume. Clamp | |
14968 | * things to off as a safer default. */ | |
3a3371ff | 14969 | for_each_intel_connector(dev, connector) { |
24929352 DV |
14970 | if (connector->encoder != encoder) |
14971 | continue; | |
7f1950fb EE |
14972 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
14973 | connector->base.encoder = NULL; | |
24929352 DV |
14974 | } |
14975 | } | |
14976 | /* Enabled encoders without active connectors will be fixed in | |
14977 | * the crtc fixup. */ | |
14978 | } | |
14979 | ||
04098753 | 14980 | void i915_redisable_vga_power_on(struct drm_device *dev) |
0fde901f KM |
14981 | { |
14982 | struct drm_i915_private *dev_priv = dev->dev_private; | |
766aa1c4 | 14983 | u32 vga_reg = i915_vgacntrl_reg(dev); |
0fde901f | 14984 | |
04098753 ID |
14985 | if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) { |
14986 | DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n"); | |
14987 | i915_disable_vga(dev); | |
14988 | } | |
14989 | } | |
14990 | ||
14991 | void i915_redisable_vga(struct drm_device *dev) | |
14992 | { | |
14993 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14994 | ||
8dc8a27c PZ |
14995 | /* This function can be called both from intel_modeset_setup_hw_state or |
14996 | * at a very early point in our resume sequence, where the power well | |
14997 | * structures are not yet restored. Since this function is at a very | |
14998 | * paranoid "someone might have enabled VGA while we were not looking" | |
14999 | * level, just check if the power well is enabled instead of trying to | |
15000 | * follow the "don't touch the power well if we don't need it" policy | |
15001 | * the rest of the driver uses. */ | |
f458ebbc | 15002 | if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA)) |
8dc8a27c PZ |
15003 | return; |
15004 | ||
04098753 | 15005 | i915_redisable_vga_power_on(dev); |
0fde901f KM |
15006 | } |
15007 | ||
98ec7739 VS |
15008 | static bool primary_get_hw_state(struct intel_crtc *crtc) |
15009 | { | |
15010 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
15011 | ||
15012 | if (!crtc->active) | |
15013 | return false; | |
15014 | ||
15015 | return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE; | |
15016 | } | |
15017 | ||
30e984df | 15018 | static void intel_modeset_readout_hw_state(struct drm_device *dev) |
24929352 DV |
15019 | { |
15020 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15021 | enum pipe pipe; | |
24929352 DV |
15022 | struct intel_crtc *crtc; |
15023 | struct intel_encoder *encoder; | |
15024 | struct intel_connector *connector; | |
5358901f | 15025 | int i; |
24929352 | 15026 | |
d3fcc808 | 15027 | for_each_intel_crtc(dev, crtc) { |
b70709a6 ML |
15028 | struct drm_plane *primary = crtc->base.primary; |
15029 | struct intel_plane_state *plane_state; | |
15030 | ||
6e3c9717 | 15031 | memset(crtc->config, 0, sizeof(*crtc->config)); |
3b117c8f | 15032 | |
6e3c9717 | 15033 | crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE; |
9953599b | 15034 | |
0e8ffe1b | 15035 | crtc->active = dev_priv->display.get_pipe_config(crtc, |
6e3c9717 | 15036 | crtc->config); |
24929352 | 15037 | |
83d65738 | 15038 | crtc->base.state->enable = crtc->active; |
49d6fa21 | 15039 | crtc->base.state->active = crtc->active; |
24929352 | 15040 | crtc->base.enabled = crtc->active; |
b70709a6 ML |
15041 | |
15042 | plane_state = to_intel_plane_state(primary->state); | |
15043 | plane_state->visible = primary_get_hw_state(crtc); | |
24929352 DV |
15044 | |
15045 | DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n", | |
15046 | crtc->base.base.id, | |
15047 | crtc->active ? "enabled" : "disabled"); | |
15048 | } | |
15049 | ||
5358901f DV |
15050 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
15051 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
15052 | ||
3e369b76 ACO |
15053 | pll->on = pll->get_hw_state(dev_priv, pll, |
15054 | &pll->config.hw_state); | |
5358901f | 15055 | pll->active = 0; |
3e369b76 | 15056 | pll->config.crtc_mask = 0; |
d3fcc808 | 15057 | for_each_intel_crtc(dev, crtc) { |
1e6f2ddc | 15058 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) { |
5358901f | 15059 | pll->active++; |
3e369b76 | 15060 | pll->config.crtc_mask |= 1 << crtc->pipe; |
1e6f2ddc | 15061 | } |
5358901f | 15062 | } |
5358901f | 15063 | |
1e6f2ddc | 15064 | DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n", |
3e369b76 | 15065 | pll->name, pll->config.crtc_mask, pll->on); |
bd2bb1b9 | 15066 | |
3e369b76 | 15067 | if (pll->config.crtc_mask) |
bd2bb1b9 | 15068 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); |
5358901f DV |
15069 | } |
15070 | ||
b2784e15 | 15071 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
15072 | pipe = 0; |
15073 | ||
15074 | if (encoder->get_hw_state(encoder, &pipe)) { | |
045ac3b5 JB |
15075 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
15076 | encoder->base.crtc = &crtc->base; | |
6e3c9717 | 15077 | encoder->get_config(encoder, crtc->config); |
24929352 DV |
15078 | } else { |
15079 | encoder->base.crtc = NULL; | |
15080 | } | |
15081 | ||
15082 | encoder->connectors_active = false; | |
6f2bcceb | 15083 | DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n", |
24929352 | 15084 | encoder->base.base.id, |
8e329a03 | 15085 | encoder->base.name, |
24929352 | 15086 | encoder->base.crtc ? "enabled" : "disabled", |
6f2bcceb | 15087 | pipe_name(pipe)); |
24929352 DV |
15088 | } |
15089 | ||
3a3371ff | 15090 | for_each_intel_connector(dev, connector) { |
24929352 DV |
15091 | if (connector->get_hw_state(connector)) { |
15092 | connector->base.dpms = DRM_MODE_DPMS_ON; | |
15093 | connector->encoder->connectors_active = true; | |
15094 | connector->base.encoder = &connector->encoder->base; | |
15095 | } else { | |
15096 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
15097 | connector->base.encoder = NULL; | |
15098 | } | |
15099 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n", | |
15100 | connector->base.base.id, | |
c23cc417 | 15101 | connector->base.name, |
24929352 DV |
15102 | connector->base.encoder ? "enabled" : "disabled"); |
15103 | } | |
30e984df DV |
15104 | } |
15105 | ||
15106 | /* Scan out the current hw modeset state, sanitizes it and maps it into the drm | |
15107 | * and i915 state tracking structures. */ | |
15108 | void intel_modeset_setup_hw_state(struct drm_device *dev, | |
15109 | bool force_restore) | |
15110 | { | |
15111 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15112 | enum pipe pipe; | |
30e984df DV |
15113 | struct intel_crtc *crtc; |
15114 | struct intel_encoder *encoder; | |
35c95375 | 15115 | int i; |
30e984df DV |
15116 | |
15117 | intel_modeset_readout_hw_state(dev); | |
24929352 | 15118 | |
babea61d JB |
15119 | /* |
15120 | * Now that we have the config, copy it to each CRTC struct | |
15121 | * Note that this could go away if we move to using crtc_config | |
15122 | * checking everywhere. | |
15123 | */ | |
d3fcc808 | 15124 | for_each_intel_crtc(dev, crtc) { |
d330a953 | 15125 | if (crtc->active && i915.fastboot) { |
6e3c9717 ACO |
15126 | intel_mode_from_pipe_config(&crtc->base.mode, |
15127 | crtc->config); | |
babea61d JB |
15128 | DRM_DEBUG_KMS("[CRTC:%d] found active mode: ", |
15129 | crtc->base.base.id); | |
15130 | drm_mode_debug_printmodeline(&crtc->base.mode); | |
15131 | } | |
15132 | } | |
15133 | ||
24929352 | 15134 | /* HW state is read out, now we need to sanitize this mess. */ |
b2784e15 | 15135 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
15136 | intel_sanitize_encoder(encoder); |
15137 | } | |
15138 | ||
055e393f | 15139 | for_each_pipe(dev_priv, pipe) { |
24929352 DV |
15140 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
15141 | intel_sanitize_crtc(crtc); | |
6e3c9717 ACO |
15142 | intel_dump_pipe_config(crtc, crtc->config, |
15143 | "[setup_hw_state]"); | |
24929352 | 15144 | } |
9a935856 | 15145 | |
d29b2f9d ACO |
15146 | intel_modeset_update_connector_atomic_state(dev); |
15147 | ||
35c95375 DV |
15148 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
15149 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
15150 | ||
15151 | if (!pll->on || pll->active) | |
15152 | continue; | |
15153 | ||
15154 | DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name); | |
15155 | ||
15156 | pll->disable(dev_priv, pll); | |
15157 | pll->on = false; | |
15158 | } | |
15159 | ||
3078999f PB |
15160 | if (IS_GEN9(dev)) |
15161 | skl_wm_get_hw_state(dev); | |
15162 | else if (HAS_PCH_SPLIT(dev)) | |
243e6a44 VS |
15163 | ilk_wm_get_hw_state(dev); |
15164 | ||
45e2b5f6 | 15165 | if (force_restore) { |
7d0bc1ea VS |
15166 | i915_redisable_vga(dev); |
15167 | ||
f30da187 DV |
15168 | /* |
15169 | * We need to use raw interfaces for restoring state to avoid | |
15170 | * checking (bogus) intermediate states. | |
15171 | */ | |
055e393f | 15172 | for_each_pipe(dev_priv, pipe) { |
b5644d05 JB |
15173 | struct drm_crtc *crtc = |
15174 | dev_priv->pipe_to_crtc_mapping[pipe]; | |
f30da187 | 15175 | |
83a57153 | 15176 | intel_crtc_restore_mode(crtc); |
45e2b5f6 DV |
15177 | } |
15178 | } else { | |
15179 | intel_modeset_update_staged_output_state(dev); | |
15180 | } | |
8af6cf88 DV |
15181 | |
15182 | intel_modeset_check_state(dev); | |
2c7111db CW |
15183 | } |
15184 | ||
15185 | void intel_modeset_gem_init(struct drm_device *dev) | |
15186 | { | |
92122789 | 15187 | struct drm_i915_private *dev_priv = dev->dev_private; |
484b41dd | 15188 | struct drm_crtc *c; |
2ff8fde1 | 15189 | struct drm_i915_gem_object *obj; |
e0d6149b | 15190 | int ret; |
484b41dd | 15191 | |
ae48434c ID |
15192 | mutex_lock(&dev->struct_mutex); |
15193 | intel_init_gt_powersave(dev); | |
15194 | mutex_unlock(&dev->struct_mutex); | |
15195 | ||
92122789 JB |
15196 | /* |
15197 | * There may be no VBT; and if the BIOS enabled SSC we can | |
15198 | * just keep using it to avoid unnecessary flicker. Whereas if the | |
15199 | * BIOS isn't using it, don't assume it will work even if the VBT | |
15200 | * indicates as much. | |
15201 | */ | |
15202 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
15203 | dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) & | |
15204 | DREF_SSC1_ENABLE); | |
15205 | ||
1833b134 | 15206 | intel_modeset_init_hw(dev); |
02e792fb DV |
15207 | |
15208 | intel_setup_overlay(dev); | |
484b41dd JB |
15209 | |
15210 | /* | |
15211 | * Make sure any fbs we allocated at startup are properly | |
15212 | * pinned & fenced. When we do the allocation it's too early | |
15213 | * for this. | |
15214 | */ | |
70e1e0ec | 15215 | for_each_crtc(dev, c) { |
2ff8fde1 MR |
15216 | obj = intel_fb_obj(c->primary->fb); |
15217 | if (obj == NULL) | |
484b41dd JB |
15218 | continue; |
15219 | ||
e0d6149b TU |
15220 | mutex_lock(&dev->struct_mutex); |
15221 | ret = intel_pin_and_fence_fb_obj(c->primary, | |
15222 | c->primary->fb, | |
15223 | c->primary->state, | |
15224 | NULL); | |
15225 | mutex_unlock(&dev->struct_mutex); | |
15226 | if (ret) { | |
484b41dd JB |
15227 | DRM_ERROR("failed to pin boot fb on pipe %d\n", |
15228 | to_intel_crtc(c)->pipe); | |
66e514c1 DA |
15229 | drm_framebuffer_unreference(c->primary->fb); |
15230 | c->primary->fb = NULL; | |
afd65eb4 | 15231 | update_state_fb(c->primary); |
484b41dd JB |
15232 | } |
15233 | } | |
0962c3c9 VS |
15234 | |
15235 | intel_backlight_register(dev); | |
79e53945 JB |
15236 | } |
15237 | ||
4932e2c3 ID |
15238 | void intel_connector_unregister(struct intel_connector *intel_connector) |
15239 | { | |
15240 | struct drm_connector *connector = &intel_connector->base; | |
15241 | ||
15242 | intel_panel_destroy_backlight(connector); | |
34ea3d38 | 15243 | drm_connector_unregister(connector); |
4932e2c3 ID |
15244 | } |
15245 | ||
79e53945 JB |
15246 | void intel_modeset_cleanup(struct drm_device *dev) |
15247 | { | |
652c393a | 15248 | struct drm_i915_private *dev_priv = dev->dev_private; |
d9255d57 | 15249 | struct drm_connector *connector; |
652c393a | 15250 | |
2eb5252e ID |
15251 | intel_disable_gt_powersave(dev); |
15252 | ||
0962c3c9 VS |
15253 | intel_backlight_unregister(dev); |
15254 | ||
fd0c0642 DV |
15255 | /* |
15256 | * Interrupts and polling as the first thing to avoid creating havoc. | |
2eb5252e | 15257 | * Too much stuff here (turning of connectors, ...) would |
fd0c0642 DV |
15258 | * experience fancy races otherwise. |
15259 | */ | |
2aeb7d3a | 15260 | intel_irq_uninstall(dev_priv); |
eb21b92b | 15261 | |
fd0c0642 DV |
15262 | /* |
15263 | * Due to the hpd irq storm handling the hotplug work can re-arm the | |
15264 | * poll handlers. Hence disable polling after hpd handling is shut down. | |
15265 | */ | |
f87ea761 | 15266 | drm_kms_helper_poll_fini(dev); |
fd0c0642 | 15267 | |
652c393a JB |
15268 | mutex_lock(&dev->struct_mutex); |
15269 | ||
723bfd70 JB |
15270 | intel_unregister_dsm_handler(); |
15271 | ||
7ff0ebcc | 15272 | intel_fbc_disable(dev); |
e70236a8 | 15273 | |
69341a5e KH |
15274 | mutex_unlock(&dev->struct_mutex); |
15275 | ||
1630fe75 CW |
15276 | /* flush any delayed tasks or pending work */ |
15277 | flush_scheduled_work(); | |
15278 | ||
db31af1d JN |
15279 | /* destroy the backlight and sysfs files before encoders/connectors */ |
15280 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
4932e2c3 ID |
15281 | struct intel_connector *intel_connector; |
15282 | ||
15283 | intel_connector = to_intel_connector(connector); | |
15284 | intel_connector->unregister(intel_connector); | |
db31af1d | 15285 | } |
d9255d57 | 15286 | |
79e53945 | 15287 | drm_mode_config_cleanup(dev); |
4d7bb011 DV |
15288 | |
15289 | intel_cleanup_overlay(dev); | |
ae48434c ID |
15290 | |
15291 | mutex_lock(&dev->struct_mutex); | |
15292 | intel_cleanup_gt_powersave(dev); | |
15293 | mutex_unlock(&dev->struct_mutex); | |
79e53945 JB |
15294 | } |
15295 | ||
f1c79df3 ZW |
15296 | /* |
15297 | * Return which encoder is currently attached for connector. | |
15298 | */ | |
df0e9248 | 15299 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector) |
79e53945 | 15300 | { |
df0e9248 CW |
15301 | return &intel_attached_encoder(connector)->base; |
15302 | } | |
f1c79df3 | 15303 | |
df0e9248 CW |
15304 | void intel_connector_attach_encoder(struct intel_connector *connector, |
15305 | struct intel_encoder *encoder) | |
15306 | { | |
15307 | connector->encoder = encoder; | |
15308 | drm_mode_connector_attach_encoder(&connector->base, | |
15309 | &encoder->base); | |
79e53945 | 15310 | } |
28d52043 DA |
15311 | |
15312 | /* | |
15313 | * set vga decode state - true == enable VGA decode | |
15314 | */ | |
15315 | int intel_modeset_vga_set_state(struct drm_device *dev, bool state) | |
15316 | { | |
15317 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a885b3cc | 15318 | unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; |
28d52043 DA |
15319 | u16 gmch_ctrl; |
15320 | ||
75fa041d CW |
15321 | if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) { |
15322 | DRM_ERROR("failed to read control word\n"); | |
15323 | return -EIO; | |
15324 | } | |
15325 | ||
c0cc8a55 CW |
15326 | if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state) |
15327 | return 0; | |
15328 | ||
28d52043 DA |
15329 | if (state) |
15330 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; | |
15331 | else | |
15332 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; | |
75fa041d CW |
15333 | |
15334 | if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) { | |
15335 | DRM_ERROR("failed to write control word\n"); | |
15336 | return -EIO; | |
15337 | } | |
15338 | ||
28d52043 DA |
15339 | return 0; |
15340 | } | |
c4a1d9e4 | 15341 | |
c4a1d9e4 | 15342 | struct intel_display_error_state { |
ff57f1b0 PZ |
15343 | |
15344 | u32 power_well_driver; | |
15345 | ||
63b66e5b CW |
15346 | int num_transcoders; |
15347 | ||
c4a1d9e4 CW |
15348 | struct intel_cursor_error_state { |
15349 | u32 control; | |
15350 | u32 position; | |
15351 | u32 base; | |
15352 | u32 size; | |
52331309 | 15353 | } cursor[I915_MAX_PIPES]; |
c4a1d9e4 CW |
15354 | |
15355 | struct intel_pipe_error_state { | |
ddf9c536 | 15356 | bool power_domain_on; |
c4a1d9e4 | 15357 | u32 source; |
f301b1e1 | 15358 | u32 stat; |
52331309 | 15359 | } pipe[I915_MAX_PIPES]; |
c4a1d9e4 CW |
15360 | |
15361 | struct intel_plane_error_state { | |
15362 | u32 control; | |
15363 | u32 stride; | |
15364 | u32 size; | |
15365 | u32 pos; | |
15366 | u32 addr; | |
15367 | u32 surface; | |
15368 | u32 tile_offset; | |
52331309 | 15369 | } plane[I915_MAX_PIPES]; |
63b66e5b CW |
15370 | |
15371 | struct intel_transcoder_error_state { | |
ddf9c536 | 15372 | bool power_domain_on; |
63b66e5b CW |
15373 | enum transcoder cpu_transcoder; |
15374 | ||
15375 | u32 conf; | |
15376 | ||
15377 | u32 htotal; | |
15378 | u32 hblank; | |
15379 | u32 hsync; | |
15380 | u32 vtotal; | |
15381 | u32 vblank; | |
15382 | u32 vsync; | |
15383 | } transcoder[4]; | |
c4a1d9e4 CW |
15384 | }; |
15385 | ||
15386 | struct intel_display_error_state * | |
15387 | intel_display_capture_error_state(struct drm_device *dev) | |
15388 | { | |
fbee40df | 15389 | struct drm_i915_private *dev_priv = dev->dev_private; |
c4a1d9e4 | 15390 | struct intel_display_error_state *error; |
63b66e5b CW |
15391 | int transcoders[] = { |
15392 | TRANSCODER_A, | |
15393 | TRANSCODER_B, | |
15394 | TRANSCODER_C, | |
15395 | TRANSCODER_EDP, | |
15396 | }; | |
c4a1d9e4 CW |
15397 | int i; |
15398 | ||
63b66e5b CW |
15399 | if (INTEL_INFO(dev)->num_pipes == 0) |
15400 | return NULL; | |
15401 | ||
9d1cb914 | 15402 | error = kzalloc(sizeof(*error), GFP_ATOMIC); |
c4a1d9e4 CW |
15403 | if (error == NULL) |
15404 | return NULL; | |
15405 | ||
190be112 | 15406 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
ff57f1b0 PZ |
15407 | error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER); |
15408 | ||
055e393f | 15409 | for_each_pipe(dev_priv, i) { |
ddf9c536 | 15410 | error->pipe[i].power_domain_on = |
f458ebbc DV |
15411 | __intel_display_power_is_enabled(dev_priv, |
15412 | POWER_DOMAIN_PIPE(i)); | |
ddf9c536 | 15413 | if (!error->pipe[i].power_domain_on) |
9d1cb914 PZ |
15414 | continue; |
15415 | ||
5efb3e28 VS |
15416 | error->cursor[i].control = I915_READ(CURCNTR(i)); |
15417 | error->cursor[i].position = I915_READ(CURPOS(i)); | |
15418 | error->cursor[i].base = I915_READ(CURBASE(i)); | |
c4a1d9e4 CW |
15419 | |
15420 | error->plane[i].control = I915_READ(DSPCNTR(i)); | |
15421 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); | |
80ca378b | 15422 | if (INTEL_INFO(dev)->gen <= 3) { |
51889b35 | 15423 | error->plane[i].size = I915_READ(DSPSIZE(i)); |
80ca378b PZ |
15424 | error->plane[i].pos = I915_READ(DSPPOS(i)); |
15425 | } | |
ca291363 PZ |
15426 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
15427 | error->plane[i].addr = I915_READ(DSPADDR(i)); | |
c4a1d9e4 CW |
15428 | if (INTEL_INFO(dev)->gen >= 4) { |
15429 | error->plane[i].surface = I915_READ(DSPSURF(i)); | |
15430 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); | |
15431 | } | |
15432 | ||
c4a1d9e4 | 15433 | error->pipe[i].source = I915_READ(PIPESRC(i)); |
f301b1e1 | 15434 | |
3abfce77 | 15435 | if (HAS_GMCH_DISPLAY(dev)) |
f301b1e1 | 15436 | error->pipe[i].stat = I915_READ(PIPESTAT(i)); |
63b66e5b CW |
15437 | } |
15438 | ||
15439 | error->num_transcoders = INTEL_INFO(dev)->num_pipes; | |
15440 | if (HAS_DDI(dev_priv->dev)) | |
15441 | error->num_transcoders++; /* Account for eDP. */ | |
15442 | ||
15443 | for (i = 0; i < error->num_transcoders; i++) { | |
15444 | enum transcoder cpu_transcoder = transcoders[i]; | |
15445 | ||
ddf9c536 | 15446 | error->transcoder[i].power_domain_on = |
f458ebbc | 15447 | __intel_display_power_is_enabled(dev_priv, |
38cc1daf | 15448 | POWER_DOMAIN_TRANSCODER(cpu_transcoder)); |
ddf9c536 | 15449 | if (!error->transcoder[i].power_domain_on) |
9d1cb914 PZ |
15450 | continue; |
15451 | ||
63b66e5b CW |
15452 | error->transcoder[i].cpu_transcoder = cpu_transcoder; |
15453 | ||
15454 | error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder)); | |
15455 | error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder)); | |
15456 | error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder)); | |
15457 | error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder)); | |
15458 | error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder)); | |
15459 | error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder)); | |
15460 | error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder)); | |
c4a1d9e4 CW |
15461 | } |
15462 | ||
15463 | return error; | |
15464 | } | |
15465 | ||
edc3d884 MK |
15466 | #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) |
15467 | ||
c4a1d9e4 | 15468 | void |
edc3d884 | 15469 | intel_display_print_error_state(struct drm_i915_error_state_buf *m, |
c4a1d9e4 CW |
15470 | struct drm_device *dev, |
15471 | struct intel_display_error_state *error) | |
15472 | { | |
055e393f | 15473 | struct drm_i915_private *dev_priv = dev->dev_private; |
c4a1d9e4 CW |
15474 | int i; |
15475 | ||
63b66e5b CW |
15476 | if (!error) |
15477 | return; | |
15478 | ||
edc3d884 | 15479 | err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes); |
190be112 | 15480 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
edc3d884 | 15481 | err_printf(m, "PWR_WELL_CTL2: %08x\n", |
ff57f1b0 | 15482 | error->power_well_driver); |
055e393f | 15483 | for_each_pipe(dev_priv, i) { |
edc3d884 | 15484 | err_printf(m, "Pipe [%d]:\n", i); |
ddf9c536 ID |
15485 | err_printf(m, " Power: %s\n", |
15486 | error->pipe[i].power_domain_on ? "on" : "off"); | |
edc3d884 | 15487 | err_printf(m, " SRC: %08x\n", error->pipe[i].source); |
f301b1e1 | 15488 | err_printf(m, " STAT: %08x\n", error->pipe[i].stat); |
edc3d884 MK |
15489 | |
15490 | err_printf(m, "Plane [%d]:\n", i); | |
15491 | err_printf(m, " CNTR: %08x\n", error->plane[i].control); | |
15492 | err_printf(m, " STRIDE: %08x\n", error->plane[i].stride); | |
80ca378b | 15493 | if (INTEL_INFO(dev)->gen <= 3) { |
edc3d884 MK |
15494 | err_printf(m, " SIZE: %08x\n", error->plane[i].size); |
15495 | err_printf(m, " POS: %08x\n", error->plane[i].pos); | |
80ca378b | 15496 | } |
4b71a570 | 15497 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
edc3d884 | 15498 | err_printf(m, " ADDR: %08x\n", error->plane[i].addr); |
c4a1d9e4 | 15499 | if (INTEL_INFO(dev)->gen >= 4) { |
edc3d884 MK |
15500 | err_printf(m, " SURF: %08x\n", error->plane[i].surface); |
15501 | err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); | |
c4a1d9e4 CW |
15502 | } |
15503 | ||
edc3d884 MK |
15504 | err_printf(m, "Cursor [%d]:\n", i); |
15505 | err_printf(m, " CNTR: %08x\n", error->cursor[i].control); | |
15506 | err_printf(m, " POS: %08x\n", error->cursor[i].position); | |
15507 | err_printf(m, " BASE: %08x\n", error->cursor[i].base); | |
c4a1d9e4 | 15508 | } |
63b66e5b CW |
15509 | |
15510 | for (i = 0; i < error->num_transcoders; i++) { | |
1cf84bb6 | 15511 | err_printf(m, "CPU transcoder: %c\n", |
63b66e5b | 15512 | transcoder_name(error->transcoder[i].cpu_transcoder)); |
ddf9c536 ID |
15513 | err_printf(m, " Power: %s\n", |
15514 | error->transcoder[i].power_domain_on ? "on" : "off"); | |
63b66e5b CW |
15515 | err_printf(m, " CONF: %08x\n", error->transcoder[i].conf); |
15516 | err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal); | |
15517 | err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank); | |
15518 | err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync); | |
15519 | err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal); | |
15520 | err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank); | |
15521 | err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync); | |
15522 | } | |
c4a1d9e4 | 15523 | } |
e2fcdaa9 VS |
15524 | |
15525 | void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file) | |
15526 | { | |
15527 | struct intel_crtc *crtc; | |
15528 | ||
15529 | for_each_intel_crtc(dev, crtc) { | |
15530 | struct intel_unpin_work *work; | |
e2fcdaa9 | 15531 | |
5e2d7afc | 15532 | spin_lock_irq(&dev->event_lock); |
e2fcdaa9 VS |
15533 | |
15534 | work = crtc->unpin_work; | |
15535 | ||
15536 | if (work && work->event && | |
15537 | work->event->base.file_priv == file) { | |
15538 | kfree(work->event); | |
15539 | work->event = NULL; | |
15540 | } | |
15541 | ||
5e2d7afc | 15542 | spin_unlock_irq(&dev->event_lock); |
e2fcdaa9 VS |
15543 | } |
15544 | } |