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drm/i915: Remove the COMMON_PRIMARY_FORMATS defines
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
319c1d42 40#include <drm/drm_atomic.h>
c196e1d6 41#include <drm/drm_atomic_helper.h>
760285e7
DH		 42#include <drm/drm_dp_helper.h>
43#include <drm/drm_crtc_helper.h>
465c120c
MR		 44#include <drm/drm_plane_helper.h>
45#include <drm/drm_rect.h>
c0f372b3 46#include <linux/dma_remapping.h>
79e53945 47
465c120c 48/* Primary plane formats for gen <= 3 */
568db4f2 49static const uint32_t i8xx_primary_formats[] = {
67fe7dc5
DL		 50 DRM_FORMAT_C8,
51 DRM_FORMAT_RGB565,
465c120c
MR		 52 DRM_FORMAT_XRGB1555,
53 DRM_FORMAT_ARGB1555,
67fe7dc5
DL		 54 DRM_FORMAT_XRGB8888,
55 DRM_FORMAT_ARGB8888,
465c120c
MR		 56};
57
58/* Primary plane formats for gen >= 4 */
568db4f2 59static const uint32_t i965_primary_formats[] = {
67fe7dc5
DL		 60 DRM_FORMAT_C8,
61 DRM_FORMAT_RGB565,
62 DRM_FORMAT_XRGB8888,
465c120c 63 DRM_FORMAT_XBGR8888,
67fe7dc5 64 DRM_FORMAT_ARGB8888,
465c120c
MR		 65 DRM_FORMAT_ABGR8888,
66 DRM_FORMAT_XRGB2101010,
67 DRM_FORMAT_ARGB2101010,
68 DRM_FORMAT_XBGR2101010,
69 DRM_FORMAT_ABGR2101010,
70};
71
3d7d6510
MR		 72/* Cursor formats */
73static const uint32_t intel_cursor_formats[] = {
74 DRM_FORMAT_ARGB8888,
75};
76
6b383a7f 77static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 78
f1f644dc 79static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 80 struct intel_crtc_state *pipe_config);
18442d08 81static void ironlake_pch_clock_get(struct intel_crtc *crtc,
5cec258b 82 struct intel_crtc_state *pipe_config);
f1f644dc 83
8c7b5ccb 84static int intel_set_mode(struct drm_crtc *crtc,
83a57153 85 struct drm_atomic_state *state);
eb1bfe80
JB		 86static int intel_framebuffer_init(struct drm_device *dev,
87 struct intel_framebuffer *ifb,
88 struct drm_mode_fb_cmd2 *mode_cmd,
89 struct drm_i915_gem_object *obj);
5b18e57c
DV		 90static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
91static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
29407aab 92static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
f769cd24
VK		 93 struct intel_link_m_n *m_n,
94 struct intel_link_m_n *m2_n2);
29407aab 95static void ironlake_set_pipeconf(struct drm_crtc *crtc);
229fca97
DV		 96static void haswell_set_pipeconf(struct drm_crtc *crtc);
97static void intel_set_pipe_csc(struct drm_crtc *crtc);
d288f65f 98static void vlv_prepare_pll(struct intel_crtc *crtc,
5cec258b 99 const struct intel_crtc_state *pipe_config);
d288f65f 100static void chv_prepare_pll(struct intel_crtc *crtc,
5cec258b 101 const struct intel_crtc_state *pipe_config);
ea2c67bb
MR		 102static void intel_begin_crtc_commit(struct drm_crtc *crtc);
103static void intel_finish_crtc_commit(struct drm_crtc *crtc);
549e2bfb
CK		 104static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
105 struct intel_crtc_state *crtc_state);
5ab7b0b7
ID		 106static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
107 int num_connectors);
ce22dba9
ML		 108static void intel_crtc_enable_planes(struct drm_crtc *crtc);
109static void intel_crtc_disable_planes(struct drm_crtc *crtc);
e7457a9a 110
0e32b39c
DA		 111static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
112{
113 if (!connector->mst_port)
114 return connector->encoder;
115 else
116 return &connector->mst_port->mst_encoders[pipe]->base;
117}
118
79e53945 119typedef struct {
0206e353 120 int min, max;
79e53945
JB		 121} intel_range_t;
122
123typedef struct {
0206e353
AJ		 124 int dot_limit;
125 int p2_slow, p2_fast;
79e53945
JB		 126} intel_p2_t;
127
d4906093
ML		 128typedef struct intel_limit intel_limit_t;
129struct intel_limit {
0206e353
AJ		 130 intel_range_t dot, vco, n, m, m1, m2, p, p1;
131 intel_p2_t p2;
d4906093 132};
79e53945 133
d2acd215
DV		 134int
135intel_pch_rawclk(struct drm_device *dev)
136{
137 struct drm_i915_private *dev_priv = dev->dev_private;
138
139 WARN_ON(!HAS_PCH_SPLIT(dev));
140
141 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
142}
143
021357ac
CW		 144static inline u32 /* units of 100MHz */
145intel_fdi_link_freq(struct drm_device *dev)
146{
8b99e68c
CW		 147 if (IS_GEN5(dev)) {
148 struct drm_i915_private *dev_priv = dev->dev_private;
149 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
150 } else
151 return 27;
021357ac
CW		 152}
153
5d536e28 154static const intel_limit_t intel_limits_i8xx_dac = {
0206e353 155 .dot = { .min = 25000, .max = 350000 },
9c333719 156 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 157 .n = { .min = 2, .max = 16 },
0206e353
AJ		 158 .m = { .min = 96, .max = 140 },
159 .m1 = { .min = 18, .max = 26 },
160 .m2 = { .min = 6, .max = 16 },
161 .p = { .min = 4, .max = 128 },
162 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 163 .p2 = { .dot_limit = 165000,
164 .p2_slow = 4, .p2_fast = 2 },
e4b36699
KP		 165};
166
5d536e28
DV		 167static const intel_limit_t intel_limits_i8xx_dvo = {
168 .dot = { .min = 25000, .max = 350000 },
9c333719 169 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 170 .n = { .min = 2, .max = 16 },
5d536e28
DV		 171 .m = { .min = 96, .max = 140 },
172 .m1 = { .min = 18, .max = 26 },
173 .m2 = { .min = 6, .max = 16 },
174 .p = { .min = 4, .max = 128 },
175 .p1 = { .min = 2, .max = 33 },
176 .p2 = { .dot_limit = 165000,
177 .p2_slow = 4, .p2_fast = 4 },
178};
179
e4b36699 180static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353 181 .dot = { .min = 25000, .max = 350000 },
9c333719 182 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 183 .n = { .min = 2, .max = 16 },
0206e353
AJ		 184 .m = { .min = 96, .max = 140 },
185 .m1 = { .min = 18, .max = 26 },
186 .m2 = { .min = 6, .max = 16 },
187 .p = { .min = 4, .max = 128 },
188 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 189 .p2 = { .dot_limit = 165000,
190 .p2_slow = 14, .p2_fast = 7 },
e4b36699 191};
273e27ca 192
e4b36699 193static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 194 .dot = { .min = 20000, .max = 400000 },
195 .vco = { .min = 1400000, .max = 2800000 },
196 .n = { .min = 1, .max = 6 },
197 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 198 .m1 = { .min = 8, .max = 18 },
199 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 200 .p = { .min = 5, .max = 80 },
201 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 202 .p2 = { .dot_limit = 200000,
203 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 204};
205
206static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 207 .dot = { .min = 20000, .max = 400000 },
208 .vco = { .min = 1400000, .max = 2800000 },
209 .n = { .min = 1, .max = 6 },
210 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 211 .m1 = { .min = 8, .max = 18 },
212 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 213 .p = { .min = 7, .max = 98 },
214 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 215 .p2 = { .dot_limit = 112000,
216 .p2_slow = 14, .p2_fast = 7 },
e4b36699
KP		 217};
218
273e27ca 219
e4b36699 220static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 221 .dot = { .min = 25000, .max = 270000 },
222 .vco = { .min = 1750000, .max = 3500000},
223 .n = { .min = 1, .max = 4 },
224 .m = { .min = 104, .max = 138 },
225 .m1 = { .min = 17, .max = 23 },
226 .m2 = { .min = 5, .max = 11 },
227 .p = { .min = 10, .max = 30 },
228 .p1 = { .min = 1, .max = 3},
229 .p2 = { .dot_limit = 270000,
230 .p2_slow = 10,
231 .p2_fast = 10
044c7c41 232 },
e4b36699
KP		 233};
234
235static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 236 .dot = { .min = 22000, .max = 400000 },
237 .vco = { .min = 1750000, .max = 3500000},
238 .n = { .min = 1, .max = 4 },
239 .m = { .min = 104, .max = 138 },
240 .m1 = { .min = 16, .max = 23 },
241 .m2 = { .min = 5, .max = 11 },
242 .p = { .min = 5, .max = 80 },
243 .p1 = { .min = 1, .max = 8},
244 .p2 = { .dot_limit = 165000,
245 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 246};
247
248static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 249 .dot = { .min = 20000, .max = 115000 },
250 .vco = { .min = 1750000, .max = 3500000 },
251 .n = { .min = 1, .max = 3 },
252 .m = { .min = 104, .max = 138 },
253 .m1 = { .min = 17, .max = 23 },
254 .m2 = { .min = 5, .max = 11 },
255 .p = { .min = 28, .max = 112 },
256 .p1 = { .min = 2, .max = 8 },
257 .p2 = { .dot_limit = 0,
258 .p2_slow = 14, .p2_fast = 14
044c7c41 259 },
e4b36699
KP		 260};
261
262static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 263 .dot = { .min = 80000, .max = 224000 },
264 .vco = { .min = 1750000, .max = 3500000 },
265 .n = { .min = 1, .max = 3 },
266 .m = { .min = 104, .max = 138 },
267 .m1 = { .min = 17, .max = 23 },
268 .m2 = { .min = 5, .max = 11 },
269 .p = { .min = 14, .max = 42 },
270 .p1 = { .min = 2, .max = 6 },
271 .p2 = { .dot_limit = 0,
272 .p2_slow = 7, .p2_fast = 7
044c7c41 273 },
e4b36699
KP		 274};
275
f2b115e6 276static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 277 .dot = { .min = 20000, .max = 400000},
278 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 279 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 280 .n = { .min = 3, .max = 6 },
281 .m = { .min = 2, .max = 256 },
273e27ca 282 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 283 .m1 = { .min = 0, .max = 0 },
284 .m2 = { .min = 0, .max = 254 },
285 .p = { .min = 5, .max = 80 },
286 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 287 .p2 = { .dot_limit = 200000,
288 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 289};
290
f2b115e6 291static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 292 .dot = { .min = 20000, .max = 400000 },
293 .vco = { .min = 1700000, .max = 3500000 },
294 .n = { .min = 3, .max = 6 },
295 .m = { .min = 2, .max = 256 },
296 .m1 = { .min = 0, .max = 0 },
297 .m2 = { .min = 0, .max = 254 },
298 .p = { .min = 7, .max = 112 },
299 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 300 .p2 = { .dot_limit = 112000,
301 .p2_slow = 14, .p2_fast = 14 },
e4b36699
KP		 302};
303
273e27ca
EA		 304/* Ironlake / Sandybridge
305 *
306 * We calculate clock using (register_value + 2) for N/M1/M2, so here
307 * the range value for them is (actual_value - 2).
308 */
b91ad0ec 309static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 310 .dot = { .min = 25000, .max = 350000 },
311 .vco = { .min = 1760000, .max = 3510000 },
312 .n = { .min = 1, .max = 5 },
313 .m = { .min = 79, .max = 127 },
314 .m1 = { .min = 12, .max = 22 },
315 .m2 = { .min = 5, .max = 9 },
316 .p = { .min = 5, .max = 80 },
317 .p1 = { .min = 1, .max = 8 },
318 .p2 = { .dot_limit = 225000,
319 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 320};
321
b91ad0ec 322static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 323 .dot = { .min = 25000, .max = 350000 },
324 .vco = { .min = 1760000, .max = 3510000 },
325 .n = { .min = 1, .max = 3 },
326 .m = { .min = 79, .max = 118 },
327 .m1 = { .min = 12, .max = 22 },
328 .m2 = { .min = 5, .max = 9 },
329 .p = { .min = 28, .max = 112 },
330 .p1 = { .min = 2, .max = 8 },
331 .p2 = { .dot_limit = 225000,
332 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 333};
334
335static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 336 .dot = { .min = 25000, .max = 350000 },
337 .vco = { .min = 1760000, .max = 3510000 },
338 .n = { .min = 1, .max = 3 },
339 .m = { .min = 79, .max = 127 },
340 .m1 = { .min = 12, .max = 22 },
341 .m2 = { .min = 5, .max = 9 },
342 .p = { .min = 14, .max = 56 },
343 .p1 = { .min = 2, .max = 8 },
344 .p2 = { .dot_limit = 225000,
345 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 346};
347
273e27ca 348/* LVDS 100mhz refclk limits. */
b91ad0ec 349static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 350 .dot = { .min = 25000, .max = 350000 },
351 .vco = { .min = 1760000, .max = 3510000 },
352 .n = { .min = 1, .max = 2 },
353 .m = { .min = 79, .max = 126 },
354 .m1 = { .min = 12, .max = 22 },
355 .m2 = { .min = 5, .max = 9 },
356 .p = { .min = 28, .max = 112 },
0206e353 357 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 358 .p2 = { .dot_limit = 225000,
359 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 360};
361
362static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 363 .dot = { .min = 25000, .max = 350000 },
364 .vco = { .min = 1760000, .max = 3510000 },
365 .n = { .min = 1, .max = 3 },
366 .m = { .min = 79, .max = 126 },
367 .m1 = { .min = 12, .max = 22 },
368 .m2 = { .min = 5, .max = 9 },
369 .p = { .min = 14, .max = 42 },
0206e353 370 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 371 .p2 = { .dot_limit = 225000,
372 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 373};
374
dc730512 375static const intel_limit_t intel_limits_vlv = {
f01b7962
VS		 376 /*
377 * These are the data rate limits (measured in fast clocks)
378 * since those are the strictest limits we have. The fast
379 * clock and actual rate limits are more relaxed, so checking
380 * them would make no difference.
381 */
382 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
75e53986 383 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 384 .n = { .min = 1, .max = 7 },
a0c4da24
JB		 385 .m1 = { .min = 2, .max = 3 },
386 .m2 = { .min = 11, .max = 156 },
b99ab663 387 .p1 = { .min = 2, .max = 3 },
5fdc9c49 388 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
a0c4da24
JB		 389};
390
ef9348c8
CML		 391static const intel_limit_t intel_limits_chv = {
392 /*
393 * These are the data rate limits (measured in fast clocks)
394 * since those are the strictest limits we have. The fast
395 * clock and actual rate limits are more relaxed, so checking
396 * them would make no difference.
397 */
398 .dot = { .min = 25000 * 5, .max = 540000 * 5},
17fe1021 399 .vco = { .min = 4800000, .max = 6480000 },
ef9348c8
CML		 400 .n = { .min = 1, .max = 1 },
401 .m1 = { .min = 2, .max = 2 },
402 .m2 = { .min = 24 << 22, .max = 175 << 22 },
403 .p1 = { .min = 2, .max = 4 },
404 .p2 = { .p2_slow = 1, .p2_fast = 14 },
405};
406
5ab7b0b7
ID		 407static const intel_limit_t intel_limits_bxt = {
408 /* FIXME: find real dot limits */
409 .dot = { .min = 0, .max = INT_MAX },
410 .vco = { .min = 4800000, .max = 6480000 },
411 .n = { .min = 1, .max = 1 },
412 .m1 = { .min = 2, .max = 2 },
413 /* FIXME: find real m2 limits */
414 .m2 = { .min = 2 << 22, .max = 255 << 22 },
415 .p1 = { .min = 2, .max = 4 },
416 .p2 = { .p2_slow = 1, .p2_fast = 20 },
417};
418
6b4bf1c4
VS		 419static void vlv_clock(int refclk, intel_clock_t *clock)
420{
421 clock->m = clock->m1 * clock->m2;
422 clock->p = clock->p1 * clock->p2;
ed5ca77e
VS		 423 if (WARN_ON(clock->n == 0 || clock->p == 0))
424 return;
fb03ac01
VS		 425 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
426 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
6b4bf1c4
VS		 427}
428
e0638cdf
PZ		 429/**
430 * Returns whether any output on the specified pipe is of the specified type
431 */
4093561b 432bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
e0638cdf 433{
409ee761 434 struct drm_device *dev = crtc->base.dev;
e0638cdf
PZ		 435 struct intel_encoder *encoder;
436
409ee761 437 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
e0638cdf
PZ		 438 if (encoder->type == type)
439 return true;
440
441 return false;
442}
443
d0737e1d
ACO		 444/**
445 * Returns whether any output on the specified pipe will have the specified
446 * type after a staged modeset is complete, i.e., the same as
447 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
448 * encoder->crtc.
449 */
a93e255f
ACO		 450static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
451 int type)
d0737e1d 452{
a93e255f 453 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 454 struct drm_connector *connector;
a93e255f 455 struct drm_connector_state *connector_state;
d0737e1d 456 struct intel_encoder *encoder;
a93e255f
ACO		 457 int i, num_connectors = 0;
458
da3ced29 459 for_each_connector_in_state(state, connector, connector_state, i) {
a93e255f
ACO		 460 if (connector_state->crtc != crtc_state->base.crtc)
461 continue;
462
463 num_connectors++;
d0737e1d 464
a93e255f
ACO		 465 encoder = to_intel_encoder(connector_state->best_encoder);
466 if (encoder->type == type)
d0737e1d 467 return true;
a93e255f
ACO		 468 }
469
470 WARN_ON(num_connectors == 0);
d0737e1d
ACO		 471
472 return false;
473}
474
a93e255f
ACO		 475static const intel_limit_t *
476intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
2c07245f 477{
a93e255f 478 struct drm_device *dev = crtc_state->base.crtc->dev;
2c07245f 479 const intel_limit_t *limit;
b91ad0ec 480
a93e255f 481 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 482 if (intel_is_dual_link_lvds(dev)) {
1b894b59 483 if (refclk == 100000)
b91ad0ec
ZW		 484 limit = &intel_limits_ironlake_dual_lvds_100m;
485 else
486 limit = &intel_limits_ironlake_dual_lvds;
487 } else {
1b894b59 488 if (refclk == 100000)
b91ad0ec
ZW		 489 limit = &intel_limits_ironlake_single_lvds_100m;
490 else
491 limit = &intel_limits_ironlake_single_lvds;
492 }
c6bb3538 493 } else
b91ad0ec 494 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 495
496 return limit;
497}
498
a93e255f
ACO		 499static const intel_limit_t *
500intel_g4x_limit(struct intel_crtc_state *crtc_state)
044c7c41 501{
a93e255f 502 struct drm_device *dev = crtc_state->base.crtc->dev;
044c7c41
ML		 503 const intel_limit_t *limit;
504
a93e255f 505 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 506 if (intel_is_dual_link_lvds(dev))
e4b36699 507 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 508 else
e4b36699 509 limit = &intel_limits_g4x_single_channel_lvds;
a93e255f
ACO		 510 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
511 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
e4b36699 512 limit = &intel_limits_g4x_hdmi;
a93e255f 513 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
e4b36699 514 limit = &intel_limits_g4x_sdvo;
044c7c41 515 } else /* The option is for other outputs */
e4b36699 516 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 517
518 return limit;
519}
520
a93e255f
ACO		 521static const intel_limit_t *
522intel_limit(struct intel_crtc_state *crtc_state, int refclk)
79e53945 523{
a93e255f 524 struct drm_device *dev = crtc_state->base.crtc->dev;
79e53945
JB		 525 const intel_limit_t *limit;
526
5ab7b0b7
ID		 527 if (IS_BROXTON(dev))
528 limit = &intel_limits_bxt;
529 else if (HAS_PCH_SPLIT(dev))
a93e255f 530 limit = intel_ironlake_limit(crtc_state, refclk);
2c07245f 531 else if (IS_G4X(dev)) {
a93e255f 532 limit = intel_g4x_limit(crtc_state);
f2b115e6 533 } else if (IS_PINEVIEW(dev)) {
a93e255f 534 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
f2b115e6 535 limit = &intel_limits_pineview_lvds;
2177832f 536 else
f2b115e6 537 limit = &intel_limits_pineview_sdvo;
ef9348c8
CML		 538 } else if (IS_CHERRYVIEW(dev)) {
539 limit = &intel_limits_chv;
a0c4da24 540 } else if (IS_VALLEYVIEW(dev)) {
dc730512 541 limit = &intel_limits_vlv;
a6c45cf0 542 } else if (!IS_GEN2(dev)) {
a93e255f 543 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
a6c45cf0
CW		 544 limit = &intel_limits_i9xx_lvds;
545 else
546 limit = &intel_limits_i9xx_sdvo;
79e53945 547 } else {
a93e255f 548 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
e4b36699 549 limit = &intel_limits_i8xx_lvds;
a93e255f 550 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
e4b36699 551 limit = &intel_limits_i8xx_dvo;
5d536e28
DV		 552 else
553 limit = &intel_limits_i8xx_dac;
79e53945
JB		 554 }
555 return limit;
556}
557
f2b115e6
AJ		 558/* m1 is reserved as 0 in Pineview, n is a ring counter */
559static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 560{
2177832f
SL		 561 clock->m = clock->m2 + 2;
562 clock->p = clock->p1 * clock->p2;
ed5ca77e
VS		 563 if (WARN_ON(clock->n == 0 || clock->p == 0))
564 return;
fb03ac01
VS		 565 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
566 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
2177832f
SL		 567}
568
7429e9d4
DV		 569static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
570{
571 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
572}
573
ac58c3f0 574static void i9xx_clock(int refclk, intel_clock_t *clock)
2177832f 575{
7429e9d4 576 clock->m = i9xx_dpll_compute_m(clock);
79e53945 577 clock->p = clock->p1 * clock->p2;
ed5ca77e
VS		 578 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
579 return;
fb03ac01
VS		 580 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
581 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
79e53945
JB		 582}
583
ef9348c8
CML		 584static void chv_clock(int refclk, intel_clock_t *clock)
585{
586 clock->m = clock->m1 * clock->m2;
587 clock->p = clock->p1 * clock->p2;
588 if (WARN_ON(clock->n == 0 || clock->p == 0))
589 return;
590 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
591 clock->n << 22);
592 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
593}
594
7c04d1d9 595#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 596/**
597 * Returns whether the given set of divisors are valid for a given refclk with
598 * the given connectors.
599 */
600
1b894b59
CW		 601static bool intel_PLL_is_valid(struct drm_device *dev,
602 const intel_limit_t *limit,
603 const intel_clock_t *clock)
79e53945 604{
f01b7962
VS		 605 if (clock->n < limit->n.min || limit->n.max < clock->n)
606 INTELPllInvalid("n out of range\n");
79e53945 607 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 608 INTELPllInvalid("p1 out of range\n");
79e53945 609 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 610 INTELPllInvalid("m2 out of range\n");
79e53945 611 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 612 INTELPllInvalid("m1 out of range\n");
f01b7962 613
5ab7b0b7 614 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
f01b7962
VS		 615 if (clock->m1 <= clock->m2)
616 INTELPllInvalid("m1 <= m2\n");
617
5ab7b0b7 618 if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
f01b7962
VS		 619 if (clock->p < limit->p.min || limit->p.max < clock->p)
620 INTELPllInvalid("p out of range\n");
621 if (clock->m < limit->m.min || limit->m.max < clock->m)
622 INTELPllInvalid("m out of range\n");
623 }
624
79e53945 625 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 626 INTELPllInvalid("vco out of range\n");
79e53945
JB		 627 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
628 * connector, etc., rather than just a single range.
629 */
630 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 631 INTELPllInvalid("dot out of range\n");
79e53945
JB		 632
633 return true;
634}
635
d4906093 636static bool
a93e255f
ACO		 637i9xx_find_best_dpll(const intel_limit_t *limit,
638 struct intel_crtc_state *crtc_state,
cec2f356
SP		 639 int target, int refclk, intel_clock_t *match_clock,
640 intel_clock_t *best_clock)
79e53945 641{
a93e255f 642 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 643 struct drm_device *dev = crtc->base.dev;
79e53945 644 intel_clock_t clock;
79e53945
JB		 645 int err = target;
646
a93e255f 647 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
79e53945 648 /*
a210b028
DV		 649 * For LVDS just rely on its current settings for dual-channel.
650 * We haven't figured out how to reliably set up different
651 * single/dual channel state, if we even can.
79e53945 652 */
1974cad0 653 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 654 clock.p2 = limit->p2.p2_fast;
655 else
656 clock.p2 = limit->p2.p2_slow;
657 } else {
658 if (target < limit->p2.dot_limit)
659 clock.p2 = limit->p2.p2_slow;
660 else
661 clock.p2 = limit->p2.p2_fast;
662 }
663
0206e353 664 memset(best_clock, 0, sizeof(*best_clock));
79e53945 665
42158660
ZY		 666 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
667 clock.m1++) {
668 for (clock.m2 = limit->m2.min;
669 clock.m2 <= limit->m2.max; clock.m2++) {
c0efc387 670 if (clock.m2 >= clock.m1)
42158660
ZY		 671 break;
672 for (clock.n = limit->n.min;
673 clock.n <= limit->n.max; clock.n++) {
674 for (clock.p1 = limit->p1.min;
675 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 676 int this_err;
677
ac58c3f0
DV		 678 i9xx_clock(refclk, &clock);
679 if (!intel_PLL_is_valid(dev, limit,
680 &clock))
681 continue;
682 if (match_clock &&
683 clock.p != match_clock->p)
684 continue;
685
686 this_err = abs(clock.dot - target);
687 if (this_err < err) {
688 *best_clock = clock;
689 err = this_err;
690 }
691 }
692 }
693 }
694 }
695
696 return (err != target);
697}
698
699static bool
a93e255f
ACO		 700pnv_find_best_dpll(const intel_limit_t *limit,
701 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 702 int target, int refclk, intel_clock_t *match_clock,
703 intel_clock_t *best_clock)
79e53945 704{
a93e255f 705 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 706 struct drm_device *dev = crtc->base.dev;
79e53945 707 intel_clock_t clock;
79e53945
JB		 708 int err = target;
709
a93e255f 710 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
79e53945 711 /*
a210b028
DV		 712 * For LVDS just rely on its current settings for dual-channel.
713 * We haven't figured out how to reliably set up different
714 * single/dual channel state, if we even can.
79e53945 715 */
1974cad0 716 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 717 clock.p2 = limit->p2.p2_fast;
718 else
719 clock.p2 = limit->p2.p2_slow;
720 } else {
721 if (target < limit->p2.dot_limit)
722 clock.p2 = limit->p2.p2_slow;
723 else
724 clock.p2 = limit->p2.p2_fast;
725 }
726
0206e353 727 memset(best_clock, 0, sizeof(*best_clock));
79e53945 728
42158660
ZY		 729 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
730 clock.m1++) {
731 for (clock.m2 = limit->m2.min;
732 clock.m2 <= limit->m2.max; clock.m2++) {
42158660
ZY		 733 for (clock.n = limit->n.min;
734 clock.n <= limit->n.max; clock.n++) {
735 for (clock.p1 = limit->p1.min;
736 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 737 int this_err;
738
ac58c3f0 739 pineview_clock(refclk, &clock);
1b894b59
CW		 740 if (!intel_PLL_is_valid(dev, limit,
741 &clock))
79e53945 742 continue;
cec2f356
SP		 743 if (match_clock &&
744 clock.p != match_clock->p)
745 continue;
79e53945
JB		 746
747 this_err = abs(clock.dot - target);
748 if (this_err < err) {
749 *best_clock = clock;
750 err = this_err;
751 }
752 }
753 }
754 }
755 }
756
757 return (err != target);
758}
759
d4906093 760static bool
a93e255f
ACO		 761g4x_find_best_dpll(const intel_limit_t *limit,
762 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 763 int target, int refclk, intel_clock_t *match_clock,
764 intel_clock_t *best_clock)
d4906093 765{
a93e255f 766 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 767 struct drm_device *dev = crtc->base.dev;
d4906093
ML		 768 intel_clock_t clock;
769 int max_n;
770 bool found;
6ba770dc
AJ		 771 /* approximately equals target * 0.00585 */
772 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 773 found = false;
774
a93e255f 775 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 776 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 777 clock.p2 = limit->p2.p2_fast;
778 else
779 clock.p2 = limit->p2.p2_slow;
780 } else {
781 if (target < limit->p2.dot_limit)
782 clock.p2 = limit->p2.p2_slow;
783 else
784 clock.p2 = limit->p2.p2_fast;
785 }
786
787 memset(best_clock, 0, sizeof(*best_clock));
788 max_n = limit->n.max;
f77f13e2 789 /* based on hardware requirement, prefer smaller n to precision */
d4906093 790 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 791 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 792 for (clock.m1 = limit->m1.max;
793 clock.m1 >= limit->m1.min; clock.m1--) {
794 for (clock.m2 = limit->m2.max;
795 clock.m2 >= limit->m2.min; clock.m2--) {
796 for (clock.p1 = limit->p1.max;
797 clock.p1 >= limit->p1.min; clock.p1--) {
798 int this_err;
799
ac58c3f0 800 i9xx_clock(refclk, &clock);
1b894b59
CW		 801 if (!intel_PLL_is_valid(dev, limit,
802 &clock))
d4906093 803 continue;
1b894b59
CW		 804
805 this_err = abs(clock.dot - target);
d4906093
ML		 806 if (this_err < err_most) {
807 *best_clock = clock;
808 err_most = this_err;
809 max_n = clock.n;
810 found = true;
811 }
812 }
813 }
814 }
815 }
2c07245f
ZW		 816 return found;
817}
818
d5dd62bd
ID		 819/*
820 * Check if the calculated PLL configuration is more optimal compared to the
821 * best configuration and error found so far. Return the calculated error.
822 */
823static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
824 const intel_clock_t *calculated_clock,
825 const intel_clock_t *best_clock,
826 unsigned int best_error_ppm,
827 unsigned int *error_ppm)
828{
9ca3ba01
ID		 829 /*
830 * For CHV ignore the error and consider only the P value.
831 * Prefer a bigger P value based on HW requirements.
832 */
833 if (IS_CHERRYVIEW(dev)) {
834 *error_ppm = 0;
835
836 return calculated_clock->p > best_clock->p;
837 }
838
24be4e46
ID		 839 if (WARN_ON_ONCE(!target_freq))
840 return false;
841
d5dd62bd
ID		 842 *error_ppm = div_u64(1000000ULL *
843 abs(target_freq - calculated_clock->dot),
844 target_freq);
845 /*
846 * Prefer a better P value over a better (smaller) error if the error
847 * is small. Ensure this preference for future configurations too by
848 * setting the error to 0.
849 */
850 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
851 *error_ppm = 0;
852
853 return true;
854 }
855
856 return *error_ppm + 10 < best_error_ppm;
857}
858
a0c4da24 859static bool
a93e255f
ACO		 860vlv_find_best_dpll(const intel_limit_t *limit,
861 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 862 int target, int refclk, intel_clock_t *match_clock,
863 intel_clock_t *best_clock)
a0c4da24 864{
a93e255f 865 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 866 struct drm_device *dev = crtc->base.dev;
6b4bf1c4 867 intel_clock_t clock;
69e4f900 868 unsigned int bestppm = 1000000;
27e639bf
VS		 869 /* min update 19.2 MHz */
870 int max_n = min(limit->n.max, refclk / 19200);
49e497ef 871 bool found = false;
a0c4da24 872
6b4bf1c4
VS		 873 target *= 5; /* fast clock */
874
875 memset(best_clock, 0, sizeof(*best_clock));
a0c4da24
JB		 876
877 /* based on hardware requirement, prefer smaller n to precision */
27e639bf 878 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
811bbf05 879 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
889059d8 880 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
c1a9ae43 881 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
6b4bf1c4 882 clock.p = clock.p1 * clock.p2;
a0c4da24 883 /* based on hardware requirement, prefer bigger m1,m2 values */
6b4bf1c4 884 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
d5dd62bd 885 unsigned int ppm;
69e4f900 886
6b4bf1c4
VS		 887 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
888 refclk * clock.m1);
889
890 vlv_clock(refclk, &clock);
43b0ac53 891
f01b7962
VS		 892 if (!intel_PLL_is_valid(dev, limit,
893 &clock))
43b0ac53
VS		 894 continue;
895
d5dd62bd
ID		 896 if (!vlv_PLL_is_optimal(dev, target,
897 &clock,
898 best_clock,
899 bestppm, &ppm))
900 continue;
6b4bf1c4 901
d5dd62bd
ID		 902 *best_clock = clock;
903 bestppm = ppm;
904 found = true;
a0c4da24
JB		 905 }
906 }
907 }
908 }
a0c4da24 909
49e497ef 910 return found;
a0c4da24 911}
a4fc5ed6 912
ef9348c8 913static bool
a93e255f
ACO		 914chv_find_best_dpll(const intel_limit_t *limit,
915 struct intel_crtc_state *crtc_state,
ef9348c8
CML		 916 int target, int refclk, intel_clock_t *match_clock,
917 intel_clock_t *best_clock)
918{
a93e255f 919 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 920 struct drm_device *dev = crtc->base.dev;
9ca3ba01 921 unsigned int best_error_ppm;
ef9348c8
CML		 922 intel_clock_t clock;
923 uint64_t m2;
924 int found = false;
925
926 memset(best_clock, 0, sizeof(*best_clock));
9ca3ba01 927 best_error_ppm = 1000000;
ef9348c8
CML		 928
929 /*
930 * Based on hardware doc, the n always set to 1, and m1 always
931 * set to 2. If requires to support 200Mhz refclk, we need to
932 * revisit this because n may not 1 anymore.
933 */
934 clock.n = 1, clock.m1 = 2;
935 target *= 5; /* fast clock */
936
937 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
938 for (clock.p2 = limit->p2.p2_fast;
939 clock.p2 >= limit->p2.p2_slow;
940 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
9ca3ba01 941 unsigned int error_ppm;
ef9348c8
CML		 942
943 clock.p = clock.p1 * clock.p2;
944
945 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
946 clock.n) << 22, refclk * clock.m1);
947
948 if (m2 > INT_MAX/clock.m1)
949 continue;
950
951 clock.m2 = m2;
952
953 chv_clock(refclk, &clock);
954
955 if (!intel_PLL_is_valid(dev, limit, &clock))
956 continue;
957
9ca3ba01
ID		 958 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
959 best_error_ppm, &error_ppm))
960 continue;
961
962 *best_clock = clock;
963 best_error_ppm = error_ppm;
964 found = true;
ef9348c8
CML		 965 }
966 }
967
968 return found;
969}
970
5ab7b0b7
ID		 971bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
972 intel_clock_t *best_clock)
973{
974 int refclk = i9xx_get_refclk(crtc_state, 0);
975
976 return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
977 target_clock, refclk, NULL, best_clock);
978}
979
20ddf665
VS		 980bool intel_crtc_active(struct drm_crtc *crtc)
981{
982 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
983
984 /* Be paranoid as we can arrive here with only partial
985 * state retrieved from the hardware during setup.
986 *
241bfc38 987 * We can ditch the adjusted_mode.crtc_clock check as soon
20ddf665
VS		 988 * as Haswell has gained clock readout/fastboot support.
989 *
66e514c1 990 * We can ditch the crtc->primary->fb check as soon as we can
20ddf665 991 * properly reconstruct framebuffers.
c3d1f436
MR		 992 *
993 * FIXME: The intel_crtc->active here should be switched to
994 * crtc->state->active once we have proper CRTC states wired up
995 * for atomic.
20ddf665 996 */
c3d1f436 997 return intel_crtc->active && crtc->primary->state->fb &&
6e3c9717 998 intel_crtc->config->base.adjusted_mode.crtc_clock;
20ddf665
VS		 999}
1000
a5c961d1
PZ		 1001enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1002 enum pipe pipe)
1003{
1004 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1005 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1006
6e3c9717 1007 return intel_crtc->config->cpu_transcoder;
a5c961d1
PZ		 1008}
1009
fbf49ea2
VS		 1010static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1011{
1012 struct drm_i915_private *dev_priv = dev->dev_private;
1013 u32 reg = PIPEDSL(pipe);
1014 u32 line1, line2;
1015 u32 line_mask;
1016
1017 if (IS_GEN2(dev))
1018 line_mask = DSL_LINEMASK_GEN2;
1019 else
1020 line_mask = DSL_LINEMASK_GEN3;
1021
1022 line1 = I915_READ(reg) & line_mask;
1023 mdelay(5);
1024 line2 = I915_READ(reg) & line_mask;
1025
1026 return line1 == line2;
1027}
1028
ab7ad7f6
KP		 1029/*
1030 * intel_wait_for_pipe_off - wait for pipe to turn off
575f7ab7 1031 * @crtc: crtc whose pipe to wait for
9d0498a2
JB		 1032 *
1033 * After disabling a pipe, we can't wait for vblank in the usual way,
1034 * spinning on the vblank interrupt status bit, since we won't actually
1035 * see an interrupt when the pipe is disabled.
1036 *
ab7ad7f6
KP		 1037 * On Gen4 and above:
1038 * wait for the pipe register state bit to turn off
1039 *
1040 * Otherwise:
1041 * wait for the display line value to settle (it usually
1042 * ends up stopping at the start of the next frame).
58e10eb9 1043 *
9d0498a2 1044 */
575f7ab7 1045static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
9d0498a2 1046{
575f7ab7 1047 struct drm_device *dev = crtc->base.dev;
9d0498a2 1048 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 1049 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
575f7ab7 1050 enum pipe pipe = crtc->pipe;
ab7ad7f6
KP		 1051
1052 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 1053 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 1054
1055 /* Wait for the Pipe State to go off */
58e10eb9
CW		 1056 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1057 100))
284637d9 1058 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1059 } else {
ab7ad7f6 1060 /* Wait for the display line to settle */
fbf49ea2 1061 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
284637d9 1062 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1063 }
79e53945
JB		 1064}
1065
b0ea7d37
DL		 1066/*
1067 * ibx_digital_port_connected - is the specified port connected?
1068 * @dev_priv: i915 private structure
1069 * @port: the port to test
1070 *
1071 * Returns true if @port is connected, false otherwise.
1072 */
1073bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1074 struct intel_digital_port *port)
1075{
1076 u32 bit;
1077
c36346e3 1078 if (HAS_PCH_IBX(dev_priv->dev)) {
eba905b2 1079 switch (port->port) {
c36346e3
DL		 1080 case PORT_B:
1081 bit = SDE_PORTB_HOTPLUG;
1082 break;
1083 case PORT_C:
1084 bit = SDE_PORTC_HOTPLUG;
1085 break;
1086 case PORT_D:
1087 bit = SDE_PORTD_HOTPLUG;
1088 break;
1089 default:
1090 return true;
1091 }
1092 } else {
eba905b2 1093 switch (port->port) {
c36346e3
DL		 1094 case PORT_B:
1095 bit = SDE_PORTB_HOTPLUG_CPT;
1096 break;
1097 case PORT_C:
1098 bit = SDE_PORTC_HOTPLUG_CPT;
1099 break;
1100 case PORT_D:
1101 bit = SDE_PORTD_HOTPLUG_CPT;
1102 break;
1103 default:
1104 return true;
1105 }
b0ea7d37
DL		 1106 }
1107
1108 return I915_READ(SDEISR) & bit;
1109}
1110
b24e7179
JB		 1111static const char *state_string(bool enabled)
1112{
1113 return enabled ? "on" : "off";
1114}
1115
1116/* Only for pre-ILK configs */
55607e8a
DV		 1117void assert_pll(struct drm_i915_private *dev_priv,
1118 enum pipe pipe, bool state)
b24e7179
JB		 1119{
1120 int reg;
1121 u32 val;
1122 bool cur_state;
1123
1124 reg = DPLL(pipe);
1125 val = I915_READ(reg);
1126 cur_state = !!(val & DPLL_VCO_ENABLE);
e2c719b7 1127 I915_STATE_WARN(cur_state != state,
b24e7179
JB		 1128 "PLL state assertion failure (expected %s, current %s)\n",
1129 state_string(state), state_string(cur_state));
1130}
b24e7179 1131
23538ef1
JN		 1132/* XXX: the dsi pll is shared between MIPI DSI ports */
1133static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1134{
1135 u32 val;
1136 bool cur_state;
1137
1138 mutex_lock(&dev_priv->dpio_lock);
1139 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1140 mutex_unlock(&dev_priv->dpio_lock);
1141
1142 cur_state = val & DSI_PLL_VCO_EN;
e2c719b7 1143 I915_STATE_WARN(cur_state != state,
23538ef1
JN		 1144 "DSI PLL state assertion failure (expected %s, current %s)\n",
1145 state_string(state), state_string(cur_state));
1146}
1147#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1148#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1149
55607e8a 1150struct intel_shared_dpll *
e2b78267
DV		 1151intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1152{
1153 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1154
6e3c9717 1155 if (crtc->config->shared_dpll < 0)
e2b78267
DV		 1156 return NULL;
1157
6e3c9717 1158 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
e2b78267
DV		 1159}
1160
040484af 1161/* For ILK+ */
55607e8a
DV		 1162void assert_shared_dpll(struct drm_i915_private *dev_priv,
1163 struct intel_shared_dpll *pll,
1164 bool state)
040484af 1165{
040484af 1166 bool cur_state;
5358901f 1167 struct intel_dpll_hw_state hw_state;
040484af 1168
92b27b08 1169 if (WARN (!pll,
46edb027 1170 "asserting DPLL %s with no DPLL\n", state_string(state)))
ee7b9f93 1171 return;
ee7b9f93 1172
5358901f 1173 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
e2c719b7 1174 I915_STATE_WARN(cur_state != state,
5358901f
DV		 1175 "%s assertion failure (expected %s, current %s)\n",
1176 pll->name, state_string(state), state_string(cur_state));
040484af 1177}
040484af
JB		 1178
1179static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1180 enum pipe pipe, bool state)
1181{
1182 int reg;
1183 u32 val;
1184 bool cur_state;
ad80a810
PZ		 1185 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1186 pipe);
040484af 1187
affa9354
PZ		 1188 if (HAS_DDI(dev_priv->dev)) {
1189 /* DDI does not have a specific FDI_TX register */
ad80a810 1190 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 1191 val = I915_READ(reg);
ad80a810 1192 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 1193 } else {
1194 reg = FDI_TX_CTL(pipe);
1195 val = I915_READ(reg);
1196 cur_state = !!(val & FDI_TX_ENABLE);
1197 }
e2c719b7 1198 I915_STATE_WARN(cur_state != state,
040484af
JB		 1199 "FDI TX state assertion failure (expected %s, current %s)\n",
1200 state_string(state), state_string(cur_state));
1201}
1202#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1203#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1204
1205static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1206 enum pipe pipe, bool state)
1207{
1208 int reg;
1209 u32 val;
1210 bool cur_state;
1211
d63fa0dc
PZ		 1212 reg = FDI_RX_CTL(pipe);
1213 val = I915_READ(reg);
1214 cur_state = !!(val & FDI_RX_ENABLE);
e2c719b7 1215 I915_STATE_WARN(cur_state != state,
040484af
JB		 1216 "FDI RX state assertion failure (expected %s, current %s)\n",
1217 state_string(state), state_string(cur_state));
1218}
1219#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1220#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1221
1222static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1223 enum pipe pipe)
1224{
1225 int reg;
1226 u32 val;
1227
1228 /* ILK FDI PLL is always enabled */
3d13ef2e 1229 if (INTEL_INFO(dev_priv->dev)->gen == 5)
040484af
JB		 1230 return;
1231
bf507ef7 1232 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1233 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1234 return;
1235
040484af
JB		 1236 reg = FDI_TX_CTL(pipe);
1237 val = I915_READ(reg);
e2c719b7 1238 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
040484af
JB		 1239}
1240
55607e8a
DV		 1241void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1242 enum pipe pipe, bool state)
040484af
JB		 1243{
1244 int reg;
1245 u32 val;
55607e8a 1246 bool cur_state;
040484af
JB		 1247
1248 reg = FDI_RX_CTL(pipe);
1249 val = I915_READ(reg);
55607e8a 1250 cur_state = !!(val & FDI_RX_PLL_ENABLE);
e2c719b7 1251 I915_STATE_WARN(cur_state != state,
55607e8a
DV		 1252 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1253 state_string(state), state_string(cur_state));
040484af
JB		 1254}
1255
b680c37a
DV		 1256void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1257 enum pipe pipe)
ea0760cf 1258{
bedd4dba
JN		 1259 struct drm_device *dev = dev_priv->dev;
1260 int pp_reg;
ea0760cf
JB		 1261 u32 val;
1262 enum pipe panel_pipe = PIPE_A;
0de3b485 1263 bool locked = true;
ea0760cf 1264
bedd4dba
JN		 1265 if (WARN_ON(HAS_DDI(dev)))
1266 return;
1267
1268 if (HAS_PCH_SPLIT(dev)) {
1269 u32 port_sel;
1270
ea0760cf 1271 pp_reg = PCH_PP_CONTROL;
bedd4dba
JN		 1272 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1273
1274 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1275 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1276 panel_pipe = PIPE_B;
1277 /* XXX: else fix for eDP */
1278 } else if (IS_VALLEYVIEW(dev)) {
1279 /* presumably write lock depends on pipe, not port select */
1280 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1281 panel_pipe = pipe;
ea0760cf
JB		 1282 } else {
1283 pp_reg = PP_CONTROL;
bedd4dba
JN		 1284 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1285 panel_pipe = PIPE_B;
ea0760cf
JB		 1286 }
1287
1288 val = I915_READ(pp_reg);
1289 if (!(val & PANEL_POWER_ON) ||
ec49ba2d 1290 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
ea0760cf
JB		 1291 locked = false;
1292
e2c719b7 1293 I915_STATE_WARN(panel_pipe == pipe && locked,
ea0760cf 1294 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1295 pipe_name(pipe));
ea0760cf
JB		 1296}
1297
93ce0ba6
JN		 1298static void assert_cursor(struct drm_i915_private *dev_priv,
1299 enum pipe pipe, bool state)
1300{
1301 struct drm_device *dev = dev_priv->dev;
1302 bool cur_state;
1303
d9d82081 1304 if (IS_845G(dev) || IS_I865G(dev))
93ce0ba6 1305 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
d9d82081 1306 else
5efb3e28 1307 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
93ce0ba6 1308
e2c719b7 1309 I915_STATE_WARN(cur_state != state,
93ce0ba6
JN		 1310 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1311 pipe_name(pipe), state_string(state), state_string(cur_state));
1312}
1313#define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1314#define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1315
b840d907
JB		 1316void assert_pipe(struct drm_i915_private *dev_priv,
1317 enum pipe pipe, bool state)
b24e7179
JB		 1318{
1319 int reg;
1320 u32 val;
63d7bbe9 1321 bool cur_state;
702e7a56
PZ		 1322 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1323 pipe);
b24e7179 1324
b6b5d049
VS		 1325 /* if we need the pipe quirk it must be always on */
1326 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1327 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
8e636784
DV		 1328 state = true;
1329
f458ebbc 1330 if (!intel_display_power_is_enabled(dev_priv,
b97186f0 1331 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
69310161
PZ		 1332 cur_state = false;
1333 } else {
1334 reg = PIPECONF(cpu_transcoder);
1335 val = I915_READ(reg);
1336 cur_state = !!(val & PIPECONF_ENABLE);
1337 }
1338
e2c719b7 1339 I915_STATE_WARN(cur_state != state,
63d7bbe9 1340 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1341 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1342}
1343
931872fc
CW		 1344static void assert_plane(struct drm_i915_private *dev_priv,
1345 enum plane plane, bool state)
b24e7179
JB		 1346{
1347 int reg;
1348 u32 val;
931872fc 1349 bool cur_state;
b24e7179
JB		 1350
1351 reg = DSPCNTR(plane);
1352 val = I915_READ(reg);
931872fc 1353 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
e2c719b7 1354 I915_STATE_WARN(cur_state != state,
931872fc
CW		 1355 "plane %c assertion failure (expected %s, current %s)\n",
1356 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1357}
1358
931872fc
CW		 1359#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1360#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1361
b24e7179
JB		 1362static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1363 enum pipe pipe)
1364{
653e1026 1365 struct drm_device *dev = dev_priv->dev;
b24e7179
JB		 1366 int reg, i;
1367 u32 val;
1368 int cur_pipe;
1369
653e1026
VS		 1370 /* Primary planes are fixed to pipes on gen4+ */
1371 if (INTEL_INFO(dev)->gen >= 4) {
28c05794
AJ		 1372 reg = DSPCNTR(pipe);
1373 val = I915_READ(reg);
e2c719b7 1374 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
28c05794
AJ		 1375 "plane %c assertion failure, should be disabled but not\n",
1376 plane_name(pipe));
19ec1358 1377 return;
28c05794 1378 }
19ec1358 1379
b24e7179 1380 /* Need to check both planes against the pipe */
055e393f 1381 for_each_pipe(dev_priv, i) {
b24e7179
JB		 1382 reg = DSPCNTR(i);
1383 val = I915_READ(reg);
1384 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1385 DISPPLANE_SEL_PIPE_SHIFT;
e2c719b7 1386 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1387 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1388 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1389 }
1390}
1391
19332d7a
JB		 1392static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1393 enum pipe pipe)
1394{
20674eef 1395 struct drm_device *dev = dev_priv->dev;
1fe47785 1396 int reg, sprite;
19332d7a
JB		 1397 u32 val;
1398
7feb8b88 1399 if (INTEL_INFO(dev)->gen >= 9) {
3bdcfc0c 1400 for_each_sprite(dev_priv, pipe, sprite) {
7feb8b88 1401 val = I915_READ(PLANE_CTL(pipe, sprite));
e2c719b7 1402 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
7feb8b88
DL		 1403 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1404 sprite, pipe_name(pipe));
1405 }
1406 } else if (IS_VALLEYVIEW(dev)) {
3bdcfc0c 1407 for_each_sprite(dev_priv, pipe, sprite) {
1fe47785 1408 reg = SPCNTR(pipe, sprite);
20674eef 1409 val = I915_READ(reg);
e2c719b7 1410 I915_STATE_WARN(val & SP_ENABLE,
20674eef 1411 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1fe47785 1412 sprite_name(pipe, sprite), pipe_name(pipe));
20674eef
VS		 1413 }
1414 } else if (INTEL_INFO(dev)->gen >= 7) {
1415 reg = SPRCTL(pipe);
19332d7a 1416 val = I915_READ(reg);
e2c719b7 1417 I915_STATE_WARN(val & SPRITE_ENABLE,
06da8da2 1418 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef
VS		 1419 plane_name(pipe), pipe_name(pipe));
1420 } else if (INTEL_INFO(dev)->gen >= 5) {
1421 reg = DVSCNTR(pipe);
19332d7a 1422 val = I915_READ(reg);
e2c719b7 1423 I915_STATE_WARN(val & DVS_ENABLE,
06da8da2 1424 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef 1425 plane_name(pipe), pipe_name(pipe));
19332d7a
JB		 1426 }
1427}
1428
08c71e5e
VS		 1429static void assert_vblank_disabled(struct drm_crtc *crtc)
1430{
e2c719b7 1431 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
08c71e5e
VS		 1432 drm_crtc_vblank_put(crtc);
1433}
1434
89eff4be 1435static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
92f2584a
JB		 1436{
1437 u32 val;
1438 bool enabled;
1439
e2c719b7 1440 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
9d82aa17 1441
92f2584a
JB		 1442 val = I915_READ(PCH_DREF_CONTROL);
1443 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1444 DREF_SUPERSPREAD_SOURCE_MASK));
e2c719b7 1445 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
92f2584a
JB		 1446}
1447
ab9412ba
DV		 1448static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1449 enum pipe pipe)
92f2584a
JB		 1450{
1451 int reg;
1452 u32 val;
1453 bool enabled;
1454
ab9412ba 1455 reg = PCH_TRANSCONF(pipe);
92f2584a
JB		 1456 val = I915_READ(reg);
1457 enabled = !!(val & TRANS_ENABLE);
e2c719b7 1458 I915_STATE_WARN(enabled,
9db4a9c7
JB		 1459 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1460 pipe_name(pipe));
92f2584a
JB		 1461}
1462
4e634389
KP		 1463static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1464 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1465{
1466 if ((val & DP_PORT_EN) == 0)
1467 return false;
1468
1469 if (HAS_PCH_CPT(dev_priv->dev)) {
1470 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1471 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1472 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1473 return false;
44f37d1f
CML		 1474 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1475 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1476 return false;
f0575e92
KP		 1477 } else {
1478 if ((val & DP_PIPE_MASK) != (pipe << 30))
1479 return false;
1480 }
1481 return true;
1482}
1483
1519b995
KP		 1484static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1485 enum pipe pipe, u32 val)
1486{
dc0fa718 1487 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1488 return false;
1489
1490 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1491 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995 1492 return false;
44f37d1f
CML		 1493 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1494 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1495 return false;
1519b995 1496 } else {
dc0fa718 1497 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1498 return false;
1499 }
1500 return true;
1501}
1502
1503static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1504 enum pipe pipe, u32 val)
1505{
1506 if ((val & LVDS_PORT_EN) == 0)
1507 return false;
1508
1509 if (HAS_PCH_CPT(dev_priv->dev)) {
1510 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1511 return false;
1512 } else {
1513 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1514 return false;
1515 }
1516 return true;
1517}
1518
1519static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1520 enum pipe pipe, u32 val)
1521{
1522 if ((val & ADPA_DAC_ENABLE) == 0)
1523 return false;
1524 if (HAS_PCH_CPT(dev_priv->dev)) {
1525 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1526 return false;
1527 } else {
1528 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1529 return false;
1530 }
1531 return true;
1532}
1533
291906f1 1534static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1535 enum pipe pipe, int reg, u32 port_sel)
291906f1 1536{
47a05eca 1537 u32 val = I915_READ(reg);
e2c719b7 1538 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1539 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1540 reg, pipe_name(pipe));
de9a35ab 1541
e2c719b7 1542 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
75c5da27 1543 && (val & DP_PIPEB_SELECT),
de9a35ab 1544 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1545}
1546
1547static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1548 enum pipe pipe, int reg)
1549{
47a05eca 1550 u32 val = I915_READ(reg);
e2c719b7 1551 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1552 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1553 reg, pipe_name(pipe));
de9a35ab 1554
e2c719b7 1555 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1556 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1557 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1558}
1559
1560static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1561 enum pipe pipe)
1562{
1563 int reg;
1564 u32 val;
291906f1 1565
f0575e92
KP		 1566 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1567 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1568 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1569
1570 reg = PCH_ADPA;
1571 val = I915_READ(reg);
e2c719b7 1572 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1573 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1574 pipe_name(pipe));
291906f1
JB		 1575
1576 reg = PCH_LVDS;
1577 val = I915_READ(reg);
e2c719b7 1578 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1579 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1580 pipe_name(pipe));
291906f1 1581
e2debe91
PZ		 1582 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1583 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1584 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1585}
1586
40e9cf64
JB		 1587static void intel_init_dpio(struct drm_device *dev)
1588{
1589 struct drm_i915_private *dev_priv = dev->dev_private;
1590
1591 if (!IS_VALLEYVIEW(dev))
1592 return;
1593
a09caddd
CML		 1594 /*
1595 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1596 * CHV x1 PHY (DP/HDMI D)
1597 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1598 */
1599 if (IS_CHERRYVIEW(dev)) {
1600 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1601 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1602 } else {
1603 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1604 }
5382f5f3
JB		 1605}
1606
d288f65f 1607static void vlv_enable_pll(struct intel_crtc *crtc,
5cec258b 1608 const struct intel_crtc_state *pipe_config)
87442f73 1609{
426115cf
DV		 1610 struct drm_device *dev = crtc->base.dev;
1611 struct drm_i915_private *dev_priv = dev->dev_private;
1612 int reg = DPLL(crtc->pipe);
d288f65f 1613 u32 dpll = pipe_config->dpll_hw_state.dpll;
87442f73 1614
426115cf 1615 assert_pipe_disabled(dev_priv, crtc->pipe);
87442f73
DV		 1616
1617 /* No really, not for ILK+ */
1618 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1619
1620 /* PLL is protected by panel, make sure we can write it */
6a9e7363 1621 if (IS_MOBILE(dev_priv->dev))
426115cf 1622 assert_panel_unlocked(dev_priv, crtc->pipe);
87442f73 1623
426115cf
DV		 1624 I915_WRITE(reg, dpll);
1625 POSTING_READ(reg);
1626 udelay(150);
1627
1628 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1629 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1630
d288f65f 1631 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
426115cf 1632 POSTING_READ(DPLL_MD(crtc->pipe));
87442f73
DV		 1633
1634 /* We do this three times for luck */
426115cf 1635 I915_WRITE(reg, dpll);
87442f73
DV		 1636 POSTING_READ(reg);
1637 udelay(150); /* wait for warmup */
426115cf 1638 I915_WRITE(reg, dpll);
87442f73
DV		 1639 POSTING_READ(reg);
1640 udelay(150); /* wait for warmup */
426115cf 1641 I915_WRITE(reg, dpll);
87442f73
DV		 1642 POSTING_READ(reg);
1643 udelay(150); /* wait for warmup */
1644}
1645
d288f65f 1646static void chv_enable_pll(struct intel_crtc *crtc,
5cec258b 1647 const struct intel_crtc_state *pipe_config)
9d556c99
CML		 1648{
1649 struct drm_device *dev = crtc->base.dev;
1650 struct drm_i915_private *dev_priv = dev->dev_private;
1651 int pipe = crtc->pipe;
1652 enum dpio_channel port = vlv_pipe_to_channel(pipe);
9d556c99
CML		 1653 u32 tmp;
1654
1655 assert_pipe_disabled(dev_priv, crtc->pipe);
1656
1657 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1658
1659 mutex_lock(&dev_priv->dpio_lock);
1660
1661 /* Enable back the 10bit clock to display controller */
1662 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1663 tmp |= DPIO_DCLKP_EN;
1664 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1665
1666 /*
1667 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1668 */
1669 udelay(1);
1670
1671 /* Enable PLL */
d288f65f 1672 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
9d556c99
CML		 1673
1674 /* Check PLL is locked */
a11b0703 1675 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
9d556c99
CML		 1676 DRM_ERROR("PLL %d failed to lock\n", pipe);
1677
a11b0703 1678 /* not sure when this should be written */
d288f65f 1679 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
a11b0703
VS		 1680 POSTING_READ(DPLL_MD(pipe));
1681
9d556c99
CML		 1682 mutex_unlock(&dev_priv->dpio_lock);
1683}
1684
1c4e0274
VS		 1685static int intel_num_dvo_pipes(struct drm_device *dev)
1686{
1687 struct intel_crtc *crtc;
1688 int count = 0;
1689
1690 for_each_intel_crtc(dev, crtc)
1691 count += crtc->active &&
409ee761 1692 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1c4e0274
VS		 1693
1694 return count;
1695}
1696
66e3d5c0 1697static void i9xx_enable_pll(struct intel_crtc *crtc)
63d7bbe9 1698{
66e3d5c0
DV		 1699 struct drm_device *dev = crtc->base.dev;
1700 struct drm_i915_private *dev_priv = dev->dev_private;
1701 int reg = DPLL(crtc->pipe);
6e3c9717 1702 u32 dpll = crtc->config->dpll_hw_state.dpll;
63d7bbe9 1703
66e3d5c0 1704 assert_pipe_disabled(dev_priv, crtc->pipe);
58c6eaa2 1705
63d7bbe9 1706 /* No really, not for ILK+ */
3d13ef2e 1707 BUG_ON(INTEL_INFO(dev)->gen >= 5);
63d7bbe9
JB		 1708
1709 /* PLL is protected by panel, make sure we can write it */
66e3d5c0
DV		 1710 if (IS_MOBILE(dev) && !IS_I830(dev))
1711 assert_panel_unlocked(dev_priv, crtc->pipe);
63d7bbe9 1712
1c4e0274
VS		 1713 /* Enable DVO 2x clock on both PLLs if necessary */
1714 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1715 /*
1716 * It appears to be important that we don't enable this
1717 * for the current pipe before otherwise configuring the
1718 * PLL. No idea how this should be handled if multiple
1719 * DVO outputs are enabled simultaneosly.
1720 */
1721 dpll |= DPLL_DVO_2X_MODE;
1722 I915_WRITE(DPLL(!crtc->pipe),
1723 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1724 }
66e3d5c0
DV		 1725
1726 /* Wait for the clocks to stabilize. */
1727 POSTING_READ(reg);
1728 udelay(150);
1729
1730 if (INTEL_INFO(dev)->gen >= 4) {
1731 I915_WRITE(DPLL_MD(crtc->pipe),
6e3c9717 1732 crtc->config->dpll_hw_state.dpll_md);
66e3d5c0
DV		 1733 } else {
1734 /* The pixel multiplier can only be updated once the
1735 * DPLL is enabled and the clocks are stable.
1736 *
1737 * So write it again.
1738 */
1739 I915_WRITE(reg, dpll);
1740 }
63d7bbe9
JB		 1741
1742 /* We do this three times for luck */
66e3d5c0 1743 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1744 POSTING_READ(reg);
1745 udelay(150); /* wait for warmup */
66e3d5c0 1746 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1747 POSTING_READ(reg);
1748 udelay(150); /* wait for warmup */
66e3d5c0 1749 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1750 POSTING_READ(reg);
1751 udelay(150); /* wait for warmup */
1752}
1753
1754/**
50b44a44 1755 * i9xx_disable_pll - disable a PLL
63d7bbe9
JB		 1756 * @dev_priv: i915 private structure
1757 * @pipe: pipe PLL to disable
1758 *
1759 * Disable the PLL for @pipe, making sure the pipe is off first.
1760 *
1761 * Note! This is for pre-ILK only.
1762 */
1c4e0274 1763static void i9xx_disable_pll(struct intel_crtc *crtc)
63d7bbe9 1764{
1c4e0274
VS		 1765 struct drm_device *dev = crtc->base.dev;
1766 struct drm_i915_private *dev_priv = dev->dev_private;
1767 enum pipe pipe = crtc->pipe;
1768
1769 /* Disable DVO 2x clock on both PLLs if necessary */
1770 if (IS_I830(dev) &&
409ee761 1771 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1c4e0274
VS		 1772 intel_num_dvo_pipes(dev) == 1) {
1773 I915_WRITE(DPLL(PIPE_B),
1774 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1775 I915_WRITE(DPLL(PIPE_A),
1776 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1777 }
1778
b6b5d049
VS		 1779 /* Don't disable pipe or pipe PLLs if needed */
1780 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1781 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
63d7bbe9
JB		 1782 return;
1783
1784 /* Make sure the pipe isn't still relying on us */
1785 assert_pipe_disabled(dev_priv, pipe);
1786
50b44a44
DV		 1787 I915_WRITE(DPLL(pipe), 0);
1788 POSTING_READ(DPLL(pipe));
63d7bbe9
JB		 1789}
1790
f6071166
JB		 1791static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1792{
1793 u32 val = 0;
1794
1795 /* Make sure the pipe isn't still relying on us */
1796 assert_pipe_disabled(dev_priv, pipe);
1797
e5cbfbfb
ID		 1798 /*
1799 * Leave integrated clock source and reference clock enabled for pipe B.
1800 * The latter is needed for VGA hotplug / manual detection.
1801 */
f6071166 1802 if (pipe == PIPE_B)
e5cbfbfb 1803 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
f6071166
JB		 1804 I915_WRITE(DPLL(pipe), val);
1805 POSTING_READ(DPLL(pipe));
076ed3b2
CML		 1806
1807}
1808
1809static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1810{
d752048d 1811 enum dpio_channel port = vlv_pipe_to_channel(pipe);
076ed3b2
CML		 1812 u32 val;
1813
a11b0703
VS		 1814 /* Make sure the pipe isn't still relying on us */
1815 assert_pipe_disabled(dev_priv, pipe);
076ed3b2 1816
a11b0703 1817 /* Set PLL en = 0 */
d17ec4ce 1818 val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
a11b0703
VS		 1819 if (pipe != PIPE_A)
1820 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1821 I915_WRITE(DPLL(pipe), val);
1822 POSTING_READ(DPLL(pipe));
d752048d
VS		 1823
1824 mutex_lock(&dev_priv->dpio_lock);
1825
1826 /* Disable 10bit clock to display controller */
1827 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1828 val &= ~DPIO_DCLKP_EN;
1829 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1830
61407f6d
VS		 1831 /* disable left/right clock distribution */
1832 if (pipe != PIPE_B) {
1833 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1834 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1835 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1836 } else {
1837 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1838 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1839 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1840 }
1841
d752048d 1842 mutex_unlock(&dev_priv->dpio_lock);
f6071166
JB		 1843}
1844
e4607fcf 1845void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
9b6de0a1
VS		 1846 struct intel_digital_port *dport,
1847 unsigned int expected_mask)
89b667f8
JB		 1848{
1849 u32 port_mask;
00fc31b7 1850 int dpll_reg;
89b667f8 1851
e4607fcf
CML		 1852 switch (dport->port) {
1853 case PORT_B:
89b667f8 1854 port_mask = DPLL_PORTB_READY_MASK;
00fc31b7 1855 dpll_reg = DPLL(0);
e4607fcf
CML		 1856 break;
1857 case PORT_C:
89b667f8 1858 port_mask = DPLL_PORTC_READY_MASK;
00fc31b7 1859 dpll_reg = DPLL(0);
9b6de0a1 1860 expected_mask <<= 4;
00fc31b7
CML		 1861 break;
1862 case PORT_D:
1863 port_mask = DPLL_PORTD_READY_MASK;
1864 dpll_reg = DPIO_PHY_STATUS;
e4607fcf
CML		 1865 break;
1866 default:
1867 BUG();
1868 }
89b667f8 1869
9b6de0a1
VS		 1870 if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1871 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1872 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
89b667f8
JB		 1873}
1874
b14b1055
DV		 1875static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1876{
1877 struct drm_device *dev = crtc->base.dev;
1878 struct drm_i915_private *dev_priv = dev->dev_private;
1879 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1880
be19f0ff
CW		 1881 if (WARN_ON(pll == NULL))
1882 return;
1883
3e369b76 1884 WARN_ON(!pll->config.crtc_mask);
b14b1055
DV		 1885 if (pll->active == 0) {
1886 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1887 WARN_ON(pll->on);
1888 assert_shared_dpll_disabled(dev_priv, pll);
1889
1890 pll->mode_set(dev_priv, pll);
1891 }
1892}
1893
92f2584a 1894/**
85b3894f 1895 * intel_enable_shared_dpll - enable PCH PLL
92f2584a
JB		 1896 * @dev_priv: i915 private structure
1897 * @pipe: pipe PLL to enable
1898 *
1899 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1900 * drives the transcoder clock.
1901 */
85b3894f 1902static void intel_enable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1903{
3d13ef2e
DL		 1904 struct drm_device *dev = crtc->base.dev;
1905 struct drm_i915_private *dev_priv = dev->dev_private;
e2b78267 1906 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
92f2584a 1907
87a875bb 1908 if (WARN_ON(pll == NULL))
48da64a8
CW		 1909 return;
1910
3e369b76 1911 if (WARN_ON(pll->config.crtc_mask == 0))
48da64a8 1912 return;
ee7b9f93 1913
74dd6928 1914 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
46edb027 1915 pll->name, pll->active, pll->on,
e2b78267 1916 crtc->base.base.id);
92f2584a 1917
cdbd2316
DV		 1918 if (pll->active++) {
1919 WARN_ON(!pll->on);
e9d6944e 1920 assert_shared_dpll_enabled(dev_priv, pll);
ee7b9f93
JB		 1921 return;
1922 }
f4a091c7 1923 WARN_ON(pll->on);
ee7b9f93 1924
bd2bb1b9
PZ		 1925 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1926
46edb027 1927 DRM_DEBUG_KMS("enabling %s\n", pll->name);
e7b903d2 1928 pll->enable(dev_priv, pll);
ee7b9f93 1929 pll->on = true;
92f2584a
JB		 1930}
1931
f6daaec2 1932static void intel_disable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1933{
3d13ef2e
DL		 1934 struct drm_device *dev = crtc->base.dev;
1935 struct drm_i915_private *dev_priv = dev->dev_private;
e2b78267 1936 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4c609cb8 1937
92f2584a 1938 /* PCH only available on ILK+ */
3d13ef2e 1939 BUG_ON(INTEL_INFO(dev)->gen < 5);
87a875bb 1940 if (WARN_ON(pll == NULL))
ee7b9f93 1941 return;
92f2584a 1942
3e369b76 1943 if (WARN_ON(pll->config.crtc_mask == 0))
48da64a8 1944 return;
7a419866 1945
46edb027
DV		 1946 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1947 pll->name, pll->active, pll->on,
e2b78267 1948 crtc->base.base.id);
7a419866 1949
48da64a8 1950 if (WARN_ON(pll->active == 0)) {
e9d6944e 1951 assert_shared_dpll_disabled(dev_priv, pll);
48da64a8
CW		 1952 return;
1953 }
1954
e9d6944e 1955 assert_shared_dpll_enabled(dev_priv, pll);
f4a091c7 1956 WARN_ON(!pll->on);
cdbd2316 1957 if (--pll->active)
7a419866 1958 return;
ee7b9f93 1959
46edb027 1960 DRM_DEBUG_KMS("disabling %s\n", pll->name);
e7b903d2 1961 pll->disable(dev_priv, pll);
ee7b9f93 1962 pll->on = false;
bd2bb1b9
PZ		 1963
1964 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
92f2584a
JB		 1965}
1966
b8a4f404
PZ		 1967static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1968 enum pipe pipe)
040484af 1969{
23670b32 1970 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1971 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
e2b78267 1972 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
23670b32 1973 uint32_t reg, val, pipeconf_val;
040484af
JB		 1974
1975 /* PCH only available on ILK+ */
55522f37 1976 BUG_ON(!HAS_PCH_SPLIT(dev));
040484af
JB		 1977
1978 /* Make sure PCH DPLL is enabled */
e72f9fbf 1979 assert_shared_dpll_enabled(dev_priv,
e9d6944e 1980 intel_crtc_to_shared_dpll(intel_crtc));
040484af
JB		 1981
1982 /* FDI must be feeding us bits for PCH ports */
1983 assert_fdi_tx_enabled(dev_priv, pipe);
1984 assert_fdi_rx_enabled(dev_priv, pipe);
1985
23670b32
DV		 1986 if (HAS_PCH_CPT(dev)) {
1987 /* Workaround: Set the timing override bit before enabling the
1988 * pch transcoder. */
1989 reg = TRANS_CHICKEN2(pipe);
1990 val = I915_READ(reg);
1991 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1992 I915_WRITE(reg, val);
59c859d6 1993 }
23670b32 1994
ab9412ba 1995 reg = PCH_TRANSCONF(pipe);
040484af 1996 val = I915_READ(reg);
5f7f726d 1997 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1998
1999 if (HAS_PCH_IBX(dev_priv->dev)) {
2000 /*
2001 * make the BPC in transcoder be consistent with
2002 * that in pipeconf reg.
2003 */
dfd07d72
DV		 2004 val &= ~PIPECONF_BPC_MASK;
2005 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 2006 }
5f7f726d
PZ		 2007
2008 val &= ~TRANS_INTERLACE_MASK;
2009 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6 2010 if (HAS_PCH_IBX(dev_priv->dev) &&
409ee761 2011 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7c26e5c6
PZ		 2012 val |= TRANS_LEGACY_INTERLACED_ILK;
2013 else
2014 val |= TRANS_INTERLACED;
5f7f726d
PZ		 2015 else
2016 val |= TRANS_PROGRESSIVE;
2017
040484af
JB		 2018 I915_WRITE(reg, val | TRANS_ENABLE);
2019 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 2020 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 2021}
2022
8fb033d7 2023static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 2024 enum transcoder cpu_transcoder)
040484af 2025{
8fb033d7 2026 u32 val, pipeconf_val;
8fb033d7
PZ		 2027
2028 /* PCH only available on ILK+ */
55522f37 2029 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
8fb033d7 2030
8fb033d7 2031 /* FDI must be feeding us bits for PCH ports */
1a240d4d 2032 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 2033 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 2034
223a6fdf
PZ		 2035 /* Workaround: set timing override bit. */
2036 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 2037 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 2038 I915_WRITE(_TRANSA_CHICKEN2, val);
2039
25f3ef11 2040 val = TRANS_ENABLE;
937bb610 2041 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 2042
9a76b1c6
PZ		 2043 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2044 PIPECONF_INTERLACED_ILK)
a35f2679 2045 val |= TRANS_INTERLACED;
8fb033d7
PZ		 2046 else
2047 val |= TRANS_PROGRESSIVE;
2048
ab9412ba
DV		 2049 I915_WRITE(LPT_TRANSCONF, val);
2050 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
937bb610 2051 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 2052}
2053
b8a4f404
PZ		 2054static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2055 enum pipe pipe)
040484af 2056{
23670b32
DV		 2057 struct drm_device *dev = dev_priv->dev;
2058 uint32_t reg, val;
040484af
JB		 2059
2060 /* FDI relies on the transcoder */
2061 assert_fdi_tx_disabled(dev_priv, pipe);
2062 assert_fdi_rx_disabled(dev_priv, pipe);
2063
291906f1
JB		 2064 /* Ports must be off as well */
2065 assert_pch_ports_disabled(dev_priv, pipe);
2066
ab9412ba 2067 reg = PCH_TRANSCONF(pipe);
040484af
JB		 2068 val = I915_READ(reg);
2069 val &= ~TRANS_ENABLE;
2070 I915_WRITE(reg, val);
2071 /* wait for PCH transcoder off, transcoder state */
2072 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 2073 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV		 2074
2075 if (!HAS_PCH_IBX(dev)) {
2076 /* Workaround: Clear the timing override chicken bit again. */
2077 reg = TRANS_CHICKEN2(pipe);
2078 val = I915_READ(reg);
2079 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2080 I915_WRITE(reg, val);
2081 }
040484af
JB		 2082}
2083
ab4d966c 2084static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 2085{
8fb033d7
PZ		 2086 u32 val;
2087
ab9412ba 2088 val = I915_READ(LPT_TRANSCONF);
8fb033d7 2089 val &= ~TRANS_ENABLE;
ab9412ba 2090 I915_WRITE(LPT_TRANSCONF, val);
8fb033d7 2091 /* wait for PCH transcoder off, transcoder state */
ab9412ba 2092 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
8a52fd9f 2093 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 2094
2095 /* Workaround: clear timing override bit. */
2096 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 2097 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 2098 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 2099}
2100
b24e7179 2101/**
309cfea8 2102 * intel_enable_pipe - enable a pipe, asserting requirements
0372264a 2103 * @crtc: crtc responsible for the pipe
b24e7179 2104 *
0372264a 2105 * Enable @crtc's pipe, making sure that various hardware specific requirements
b24e7179 2106 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
b24e7179 2107 */
e1fdc473 2108static void intel_enable_pipe(struct intel_crtc *crtc)
b24e7179 2109{
0372264a
PZ		 2110 struct drm_device *dev = crtc->base.dev;
2111 struct drm_i915_private *dev_priv = dev->dev_private;
2112 enum pipe pipe = crtc->pipe;
702e7a56
PZ		 2113 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2114 pipe);
1a240d4d 2115 enum pipe pch_transcoder;
b24e7179
JB		 2116 int reg;
2117 u32 val;
2118
58c6eaa2 2119 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 2120 assert_cursor_disabled(dev_priv, pipe);
58c6eaa2
DV		 2121 assert_sprites_disabled(dev_priv, pipe);
2122
681e5811 2123 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 2124 pch_transcoder = TRANSCODER_A;
2125 else
2126 pch_transcoder = pipe;
2127
b24e7179
JB		 2128 /*
2129 * A pipe without a PLL won't actually be able to drive bits from
2130 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2131 * need the check.
2132 */
50360403 2133 if (HAS_GMCH_DISPLAY(dev_priv->dev))
409ee761 2134 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
23538ef1
JN		 2135 assert_dsi_pll_enabled(dev_priv);
2136 else
2137 assert_pll_enabled(dev_priv, pipe);
040484af 2138 else {
6e3c9717 2139 if (crtc->config->has_pch_encoder) {
040484af 2140 /* if driving the PCH, we need FDI enabled */
cc391bbb 2141 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 2142 assert_fdi_tx_pll_enabled(dev_priv,
2143 (enum pipe) cpu_transcoder);
040484af
JB		 2144 }
2145 /* FIXME: assert CPU port conditions for SNB+ */
2146 }
b24e7179 2147
702e7a56 2148 reg = PIPECONF(cpu_transcoder);
b24e7179 2149 val = I915_READ(reg);
7ad25d48 2150 if (val & PIPECONF_ENABLE) {
b6b5d049
VS		 2151 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2152 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
00d70b15 2153 return;
7ad25d48 2154 }
00d70b15
CW		 2155
2156 I915_WRITE(reg, val | PIPECONF_ENABLE);
851855d8 2157 POSTING_READ(reg);
b24e7179
JB		 2158}
2159
2160/**
309cfea8 2161 * intel_disable_pipe - disable a pipe, asserting requirements
575f7ab7 2162 * @crtc: crtc whose pipes is to be disabled
b24e7179 2163 *
575f7ab7
VS		 2164 * Disable the pipe of @crtc, making sure that various hardware
2165 * specific requirements are met, if applicable, e.g. plane
2166 * disabled, panel fitter off, etc.
b24e7179
JB		 2167 *
2168 * Will wait until the pipe has shut down before returning.
2169 */
575f7ab7 2170static void intel_disable_pipe(struct intel_crtc *crtc)
b24e7179 2171{
575f7ab7 2172 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
6e3c9717 2173 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
575f7ab7 2174 enum pipe pipe = crtc->pipe;
b24e7179
JB		 2175 int reg;
2176 u32 val;
2177
2178 /*
2179 * Make sure planes won't keep trying to pump pixels to us,
2180 * or we might hang the display.
2181 */
2182 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 2183 assert_cursor_disabled(dev_priv, pipe);
19332d7a 2184 assert_sprites_disabled(dev_priv, pipe);
b24e7179 2185
702e7a56 2186 reg = PIPECONF(cpu_transcoder);
b24e7179 2187 val = I915_READ(reg);
00d70b15
CW		 2188 if ((val & PIPECONF_ENABLE) == 0)
2189 return;
2190
67adc644
VS		 2191 /*
2192 * Double wide has implications for planes
2193 * so best keep it disabled when not needed.
2194 */
6e3c9717 2195 if (crtc->config->double_wide)
67adc644
VS		 2196 val &= ~PIPECONF_DOUBLE_WIDE;
2197
2198 /* Don't disable pipe or pipe PLLs if needed */
b6b5d049
VS		 2199 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2200 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
67adc644
VS		 2201 val &= ~PIPECONF_ENABLE;
2202
2203 I915_WRITE(reg, val);
2204 if ((val & PIPECONF_ENABLE) == 0)
2205 intel_wait_for_pipe_off(crtc);
b24e7179
JB		 2206}
2207
d74362c9
KP		 2208/*
2209 * Plane regs are double buffered, going from enabled->disabled needs a
2210 * trigger in order to latch. The display address reg provides this.
2211 */
1dba99f4
VS		 2212void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2213 enum plane plane)
d74362c9 2214{
3d13ef2e
DL		 2215 struct drm_device *dev = dev_priv->dev;
2216 u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
1dba99f4
VS		 2217
2218 I915_WRITE(reg, I915_READ(reg));
2219 POSTING_READ(reg);
d74362c9
KP		 2220}
2221
b24e7179 2222/**
262ca2b0 2223 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
fdd508a6
VS		 2224 * @plane: plane to be enabled
2225 * @crtc: crtc for the plane
b24e7179 2226 *
fdd508a6 2227 * Enable @plane on @crtc, making sure that the pipe is running first.
b24e7179 2228 */
fdd508a6
VS		 2229static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2230 struct drm_crtc *crtc)
b24e7179 2231{
fdd508a6
VS		 2232 struct drm_device *dev = plane->dev;
2233 struct drm_i915_private *dev_priv = dev->dev_private;
2234 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b24e7179
JB		 2235
2236 /* If the pipe isn't enabled, we can't pump pixels and may hang */
fdd508a6 2237 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
b70709a6 2238 to_intel_plane_state(plane->state)->visible = true;
939c2fe8 2239
fdd508a6
VS		 2240 dev_priv->display.update_primary_plane(crtc, plane->fb,
2241 crtc->x, crtc->y);
b24e7179
JB		 2242}
2243
693db184
CW		 2244static bool need_vtd_wa(struct drm_device *dev)
2245{
2246#ifdef CONFIG_INTEL_IOMMU
2247 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2248 return true;
2249#endif
2250 return false;
2251}
2252
50470bb0 2253unsigned int
6761dd31
TU		 2254intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2255 uint64_t fb_format_modifier)
a57ce0b2 2256{
6761dd31
TU		 2257 unsigned int tile_height;
2258 uint32_t pixel_bytes;
a57ce0b2 2259
b5d0e9bf
DL		 2260 switch (fb_format_modifier) {
2261 case DRM_FORMAT_MOD_NONE:
2262 tile_height = 1;
2263 break;
2264 case I915_FORMAT_MOD_X_TILED:
2265 tile_height = IS_GEN2(dev) ? 16 : 8;
2266 break;
2267 case I915_FORMAT_MOD_Y_TILED:
2268 tile_height = 32;
2269 break;
2270 case I915_FORMAT_MOD_Yf_TILED:
6761dd31
TU		 2271 pixel_bytes = drm_format_plane_cpp(pixel_format, 0);
2272 switch (pixel_bytes) {
b5d0e9bf 2273 default:
6761dd31 2274 case 1:
b5d0e9bf
DL		 2275 tile_height = 64;
2276 break;
6761dd31
TU		 2277 case 2:
2278 case 4:
b5d0e9bf
DL		 2279 tile_height = 32;
2280 break;
6761dd31 2281 case 8:
b5d0e9bf
DL		 2282 tile_height = 16;
2283 break;
6761dd31 2284 case 16:
b5d0e9bf
DL		 2285 WARN_ONCE(1,
2286 "128-bit pixels are not supported for display!");
2287 tile_height = 16;
2288 break;
2289 }
2290 break;
2291 default:
2292 MISSING_CASE(fb_format_modifier);
2293 tile_height = 1;
2294 break;
2295 }
091df6cb 2296
6761dd31
TU		 2297 return tile_height;
2298}
2299
2300unsigned int
2301intel_fb_align_height(struct drm_device *dev, unsigned int height,
2302 uint32_t pixel_format, uint64_t fb_format_modifier)
2303{
2304 return ALIGN(height, intel_tile_height(dev, pixel_format,
2305 fb_format_modifier));
a57ce0b2
JB		 2306}
2307
f64b98cd
TU		 2308static int
2309intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2310 const struct drm_plane_state *plane_state)
2311{
50470bb0 2312 struct intel_rotation_info *info = &view->rotation_info;
50470bb0 2313
f64b98cd
TU		 2314 *view = i915_ggtt_view_normal;
2315
50470bb0
TU		 2316 if (!plane_state)
2317 return 0;
2318
121920fa 2319 if (!intel_rotation_90_or_270(plane_state->rotation))
50470bb0
TU		 2320 return 0;
2321
9abc4648 2322 *view = i915_ggtt_view_rotated;
50470bb0
TU		 2323
2324 info->height = fb->height;
2325 info->pixel_format = fb->pixel_format;
2326 info->pitch = fb->pitches[0];
2327 info->fb_modifier = fb->modifier[0];
2328
f64b98cd
TU		 2329 return 0;
2330}
2331
127bd2ac 2332int
850c4cdc
TU		 2333intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2334 struct drm_framebuffer *fb,
82bc3b2d 2335 const struct drm_plane_state *plane_state,
a4872ba6 2336 struct intel_engine_cs *pipelined)
6b95a207 2337{
850c4cdc 2338 struct drm_device *dev = fb->dev;
ce453d81 2339 struct drm_i915_private *dev_priv = dev->dev_private;
850c4cdc 2340 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
f64b98cd 2341 struct i915_ggtt_view view;
6b95a207
KH		 2342 u32 alignment;
2343 int ret;
2344
ebcdd39e
MR		 2345 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2346
7b911adc
TU		 2347 switch (fb->modifier[0]) {
2348 case DRM_FORMAT_MOD_NONE:
1fada4cc
DL		 2349 if (INTEL_INFO(dev)->gen >= 9)
2350 alignment = 256 * 1024;
2351 else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
534843da 2352 alignment = 128 * 1024;
a6c45cf0 2353 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 2354 alignment = 4 * 1024;
2355 else
2356 alignment = 64 * 1024;
6b95a207 2357 break;
7b911adc 2358 case I915_FORMAT_MOD_X_TILED:
1fada4cc
DL		 2359 if (INTEL_INFO(dev)->gen >= 9)
2360 alignment = 256 * 1024;
2361 else {
2362 /* pin() will align the object as required by fence */
2363 alignment = 0;
2364 }
6b95a207 2365 break;
7b911adc 2366 case I915_FORMAT_MOD_Y_TILED:
1327b9a1
DL		 2367 case I915_FORMAT_MOD_Yf_TILED:
2368 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2369 "Y tiling bo slipped through, driver bug!\n"))
2370 return -EINVAL;
2371 alignment = 1 * 1024 * 1024;
2372 break;
6b95a207 2373 default:
7b911adc
TU		 2374 MISSING_CASE(fb->modifier[0]);
2375 return -EINVAL;
6b95a207
KH		 2376 }
2377
f64b98cd
TU		 2378 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2379 if (ret)
2380 return ret;
2381
693db184
CW		 2382 /* Note that the w/a also requires 64 PTE of padding following the
2383 * bo. We currently fill all unused PTE with the shadow page and so
2384 * we should always have valid PTE following the scanout preventing
2385 * the VT-d warning.
2386 */
2387 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2388 alignment = 256 * 1024;
2389
d6dd6843
PZ		 2390 /*
2391 * Global gtt pte registers are special registers which actually forward
2392 * writes to a chunk of system memory. Which means that there is no risk
2393 * that the register values disappear as soon as we call
2394 * intel_runtime_pm_put(), so it is correct to wrap only the
2395 * pin/unpin/fence and not more.
2396 */
2397 intel_runtime_pm_get(dev_priv);
2398
ce453d81 2399 dev_priv->mm.interruptible = false;
e6617330 2400 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
f64b98cd 2401 &view);
48b956c5 2402 if (ret)
ce453d81 2403 goto err_interruptible;
6b95a207
KH		 2404
2405 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2406 * fence, whereas 965+ only requires a fence if using
2407 * framebuffer compression. For simplicity, we always install
2408 * a fence as the cost is not that onerous.
2409 */
06d98131 2410 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 2411 if (ret)
2412 goto err_unpin;
1690e1eb 2413
9a5a53b3 2414 i915_gem_object_pin_fence(obj);
6b95a207 2415
ce453d81 2416 dev_priv->mm.interruptible = true;
d6dd6843 2417 intel_runtime_pm_put(dev_priv);
6b95a207 2418 return 0;
48b956c5
CW		 2419
2420err_unpin:
f64b98cd 2421 i915_gem_object_unpin_from_display_plane(obj, &view);
ce453d81
CW		 2422err_interruptible:
2423 dev_priv->mm.interruptible = true;
d6dd6843 2424 intel_runtime_pm_put(dev_priv);
48b956c5 2425 return ret;
6b95a207
KH		 2426}
2427
82bc3b2d
TU		 2428static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2429 const struct drm_plane_state *plane_state)
1690e1eb 2430{
82bc3b2d 2431 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
f64b98cd
TU		 2432 struct i915_ggtt_view view;
2433 int ret;
82bc3b2d 2434
ebcdd39e
MR		 2435 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2436
f64b98cd
TU		 2437 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2438 WARN_ONCE(ret, "Couldn't get view from plane state!");
2439
1690e1eb 2440 i915_gem_object_unpin_fence(obj);
f64b98cd 2441 i915_gem_object_unpin_from_display_plane(obj, &view);
1690e1eb
CW		 2442}
2443
c2c75131
DV		 2444/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2445 * is assumed to be a power-of-two. */
bc752862
CW		 2446unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2447 unsigned int tiling_mode,
2448 unsigned int cpp,
2449 unsigned int pitch)
c2c75131 2450{
bc752862
CW		 2451 if (tiling_mode != I915_TILING_NONE) {
2452 unsigned int tile_rows, tiles;
c2c75131 2453
bc752862
CW		 2454 tile_rows = *y / 8;
2455 *y %= 8;
c2c75131 2456
bc752862
CW		 2457 tiles = *x / (512/cpp);
2458 *x %= 512/cpp;
2459
2460 return tile_rows * pitch * 8 + tiles * 4096;
2461 } else {
2462 unsigned int offset;
2463
2464 offset = *y * pitch + *x * cpp;
2465 *y = 0;
2466 *x = (offset & 4095) / cpp;
2467 return offset & -4096;
2468 }
c2c75131
DV		 2469}
2470
b35d63fa 2471static int i9xx_format_to_fourcc(int format)
46f297fb
JB		 2472{
2473 switch (format) {
2474 case DISPPLANE_8BPP:
2475 return DRM_FORMAT_C8;
2476 case DISPPLANE_BGRX555:
2477 return DRM_FORMAT_XRGB1555;
2478 case DISPPLANE_BGRX565:
2479 return DRM_FORMAT_RGB565;
2480 default:
2481 case DISPPLANE_BGRX888:
2482 return DRM_FORMAT_XRGB8888;
2483 case DISPPLANE_RGBX888:
2484 return DRM_FORMAT_XBGR8888;
2485 case DISPPLANE_BGRX101010:
2486 return DRM_FORMAT_XRGB2101010;
2487 case DISPPLANE_RGBX101010:
2488 return DRM_FORMAT_XBGR2101010;
2489 }
2490}
2491
bc8d7dff
DL		 2492static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2493{
2494 switch (format) {
2495 case PLANE_CTL_FORMAT_RGB_565:
2496 return DRM_FORMAT_RGB565;
2497 default:
2498 case PLANE_CTL_FORMAT_XRGB_8888:
2499 if (rgb_order) {
2500 if (alpha)
2501 return DRM_FORMAT_ABGR8888;
2502 else
2503 return DRM_FORMAT_XBGR8888;
2504 } else {
2505 if (alpha)
2506 return DRM_FORMAT_ARGB8888;
2507 else
2508 return DRM_FORMAT_XRGB8888;
2509 }
2510 case PLANE_CTL_FORMAT_XRGB_2101010:
2511 if (rgb_order)
2512 return DRM_FORMAT_XBGR2101010;
2513 else
2514 return DRM_FORMAT_XRGB2101010;
2515 }
2516}
2517
5724dbd1 2518static bool
f6936e29
DV		 2519intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2520 struct intel_initial_plane_config *plane_config)
46f297fb
JB		 2521{
2522 struct drm_device *dev = crtc->base.dev;
2523 struct drm_i915_gem_object *obj = NULL;
2524 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2d14030b 2525 struct drm_framebuffer *fb = &plane_config->fb->base;
f37b5c2b
DV		 2526 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2527 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2528 PAGE_SIZE);
2529
2530 size_aligned -= base_aligned;
46f297fb 2531
ff2652ea
CW		 2532 if (plane_config->size == 0)
2533 return false;
2534
f37b5c2b
DV		 2535 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2536 base_aligned,
2537 base_aligned,
2538 size_aligned);
46f297fb 2539 if (!obj)
484b41dd 2540 return false;
46f297fb 2541
49af449b
DL		 2542 obj->tiling_mode = plane_config->tiling;
2543 if (obj->tiling_mode == I915_TILING_X)
6bf129df 2544 obj->stride = fb->pitches[0];
46f297fb 2545
6bf129df
DL		 2546 mode_cmd.pixel_format = fb->pixel_format;
2547 mode_cmd.width = fb->width;
2548 mode_cmd.height = fb->height;
2549 mode_cmd.pitches[0] = fb->pitches[0];
18c5247e
DV		 2550 mode_cmd.modifier[0] = fb->modifier[0];
2551 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
46f297fb
JB		 2552
2553 mutex_lock(&dev->struct_mutex);
6bf129df 2554 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
484b41dd 2555 &mode_cmd, obj)) {
46f297fb
JB		 2556 DRM_DEBUG_KMS("intel fb init failed\n");
2557 goto out_unref_obj;
2558 }
46f297fb 2559 mutex_unlock(&dev->struct_mutex);
484b41dd 2560
f6936e29 2561 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
484b41dd 2562 return true;
46f297fb
JB		 2563
2564out_unref_obj:
2565 drm_gem_object_unreference(&obj->base);
2566 mutex_unlock(&dev->struct_mutex);
484b41dd
JB		 2567 return false;
2568}
2569
afd65eb4
MR		 2570/* Update plane->state->fb to match plane->fb after driver-internal updates */
2571static void
2572update_state_fb(struct drm_plane *plane)
2573{
2574 if (plane->fb == plane->state->fb)
2575 return;
2576
2577 if (plane->state->fb)
2578 drm_framebuffer_unreference(plane->state->fb);
2579 plane->state->fb = plane->fb;
2580 if (plane->state->fb)
2581 drm_framebuffer_reference(plane->state->fb);
2582}
2583
5724dbd1 2584static void
f6936e29
DV		 2585intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2586 struct intel_initial_plane_config *plane_config)
484b41dd
JB		 2587{
2588 struct drm_device *dev = intel_crtc->base.dev;
d9ceb816 2589 struct drm_i915_private *dev_priv = dev->dev_private;
484b41dd
JB		 2590 struct drm_crtc *c;
2591 struct intel_crtc *i;
2ff8fde1 2592 struct drm_i915_gem_object *obj;
88595ac9
DV		 2593 struct drm_plane *primary = intel_crtc->base.primary;
2594 struct drm_framebuffer *fb;
484b41dd 2595
2d14030b 2596 if (!plane_config->fb)
484b41dd
JB		 2597 return;
2598
f6936e29 2599 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
88595ac9
DV		 2600 fb = &plane_config->fb->base;
2601 goto valid_fb;
f55548b5 2602 }
484b41dd 2603
2d14030b 2604 kfree(plane_config->fb);
484b41dd
JB		 2605
2606 /*
2607 * Failed to alloc the obj, check to see if we should share
2608 * an fb with another CRTC instead
2609 */
70e1e0ec 2610 for_each_crtc(dev, c) {
484b41dd
JB		 2611 i = to_intel_crtc(c);
2612
2613 if (c == &intel_crtc->base)
2614 continue;
2615
2ff8fde1
MR		 2616 if (!i->active)
2617 continue;
2618
88595ac9
DV		 2619 fb = c->primary->fb;
2620 if (!fb)
484b41dd
JB		 2621 continue;
2622
88595ac9 2623 obj = intel_fb_obj(fb);
2ff8fde1 2624 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
88595ac9
DV		 2625 drm_framebuffer_reference(fb);
2626 goto valid_fb;
484b41dd
JB		 2627 }
2628 }
88595ac9
DV		 2629
2630 return;
2631
2632valid_fb:
2633 obj = intel_fb_obj(fb);
2634 if (obj->tiling_mode != I915_TILING_NONE)
2635 dev_priv->preserve_bios_swizzle = true;
2636
2637 primary->fb = fb;
2638 primary->state->crtc = &intel_crtc->base;
2639 primary->crtc = &intel_crtc->base;
2640 update_state_fb(primary);
2641 obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
46f297fb
JB		 2642}
2643
29b9bde6
DV		 2644static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2645 struct drm_framebuffer *fb,
2646 int x, int y)
81255565
JB		 2647{
2648 struct drm_device *dev = crtc->dev;
2649 struct drm_i915_private *dev_priv = dev->dev_private;
2650 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML		 2651 struct drm_plane *primary = crtc->primary;
2652 bool visible = to_intel_plane_state(primary->state)->visible;
c9ba6fad 2653 struct drm_i915_gem_object *obj;
81255565 2654 int plane = intel_crtc->plane;
e506a0c6 2655 unsigned long linear_offset;
81255565 2656 u32 dspcntr;
f45651ba 2657 u32 reg = DSPCNTR(plane);
48404c1e 2658 int pixel_size;
f45651ba 2659
b70709a6 2660 if (!visible || !fb) {
fdd508a6
VS		 2661 I915_WRITE(reg, 0);
2662 if (INTEL_INFO(dev)->gen >= 4)
2663 I915_WRITE(DSPSURF(plane), 0);
2664 else
2665 I915_WRITE(DSPADDR(plane), 0);
2666 POSTING_READ(reg);
2667 return;
2668 }
2669
c9ba6fad
VS		 2670 obj = intel_fb_obj(fb);
2671 if (WARN_ON(obj == NULL))
2672 return;
2673
2674 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2675
f45651ba
VS		 2676 dspcntr = DISPPLANE_GAMMA_ENABLE;
2677
fdd508a6 2678 dspcntr |= DISPLAY_PLANE_ENABLE;
f45651ba
VS		 2679
2680 if (INTEL_INFO(dev)->gen < 4) {
2681 if (intel_crtc->pipe == PIPE_B)
2682 dspcntr |= DISPPLANE_SEL_PIPE_B;
2683
2684 /* pipesrc and dspsize control the size that is scaled from,
2685 * which should always be the user's requested size.
2686 */
2687 I915_WRITE(DSPSIZE(plane),
6e3c9717
ACO		 2688 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2689 (intel_crtc->config->pipe_src_w - 1));
f45651ba 2690 I915_WRITE(DSPPOS(plane), 0);
c14b0485
VS		 2691 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2692 I915_WRITE(PRIMSIZE(plane),
6e3c9717
ACO		 2693 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2694 (intel_crtc->config->pipe_src_w - 1));
c14b0485
VS		 2695 I915_WRITE(PRIMPOS(plane), 0);
2696 I915_WRITE(PRIMCNSTALPHA(plane), 0);
f45651ba 2697 }
81255565 2698
57779d06
VS		 2699 switch (fb->pixel_format) {
2700 case DRM_FORMAT_C8:
81255565
JB		 2701 dspcntr |= DISPPLANE_8BPP;
2702 break;
57779d06
VS		 2703 case DRM_FORMAT_XRGB1555:
2704 case DRM_FORMAT_ARGB1555:
2705 dspcntr |= DISPPLANE_BGRX555;
81255565 2706 break;
57779d06
VS		 2707 case DRM_FORMAT_RGB565:
2708 dspcntr |= DISPPLANE_BGRX565;
2709 break;
2710 case DRM_FORMAT_XRGB8888:
2711 case DRM_FORMAT_ARGB8888:
2712 dspcntr |= DISPPLANE_BGRX888;
2713 break;
2714 case DRM_FORMAT_XBGR8888:
2715 case DRM_FORMAT_ABGR8888:
2716 dspcntr |= DISPPLANE_RGBX888;
2717 break;
2718 case DRM_FORMAT_XRGB2101010:
2719 case DRM_FORMAT_ARGB2101010:
2720 dspcntr |= DISPPLANE_BGRX101010;
2721 break;
2722 case DRM_FORMAT_XBGR2101010:
2723 case DRM_FORMAT_ABGR2101010:
2724 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2725 break;
2726 default:
baba133a 2727 BUG();
81255565 2728 }
57779d06 2729
f45651ba
VS		 2730 if (INTEL_INFO(dev)->gen >= 4 &&
2731 obj->tiling_mode != I915_TILING_NONE)
2732 dspcntr |= DISPPLANE_TILED;
81255565 2733
de1aa629
VS		 2734 if (IS_G4X(dev))
2735 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2736
b9897127 2737 linear_offset = y * fb->pitches[0] + x * pixel_size;
81255565 2738
c2c75131
DV		 2739 if (INTEL_INFO(dev)->gen >= 4) {
2740 intel_crtc->dspaddr_offset =
bc752862 2741 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
b9897127 2742 pixel_size,
bc752862 2743 fb->pitches[0]);
c2c75131
DV		 2744 linear_offset -= intel_crtc->dspaddr_offset;
2745 } else {
e506a0c6 2746 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2747 }
e506a0c6 2748
8e7d688b 2749 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
48404c1e
SJ		 2750 dspcntr |= DISPPLANE_ROTATE_180;
2751
6e3c9717
ACO		 2752 x += (intel_crtc->config->pipe_src_w - 1);
2753 y += (intel_crtc->config->pipe_src_h - 1);
48404c1e
SJ		 2754
2755 /* Finding the last pixel of the last line of the display
2756 data and adding to linear_offset*/
2757 linear_offset +=
6e3c9717
ACO		 2758 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2759 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
48404c1e
SJ		 2760 }
2761
2762 I915_WRITE(reg, dspcntr);
2763
01f2c773 2764 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2765 if (INTEL_INFO(dev)->gen >= 4) {
85ba7b7d
DV		 2766 I915_WRITE(DSPSURF(plane),
2767 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
5eddb70b 2768 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2769 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2770 } else
f343c5f6 2771 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
5eddb70b 2772 POSTING_READ(reg);
17638cd6
JB		 2773}
2774
29b9bde6
DV		 2775static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2776 struct drm_framebuffer *fb,
2777 int x, int y)
17638cd6
JB		 2778{
2779 struct drm_device *dev = crtc->dev;
2780 struct drm_i915_private *dev_priv = dev->dev_private;
2781 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML		 2782 struct drm_plane *primary = crtc->primary;
2783 bool visible = to_intel_plane_state(primary->state)->visible;
c9ba6fad 2784 struct drm_i915_gem_object *obj;
17638cd6 2785 int plane = intel_crtc->plane;
e506a0c6 2786 unsigned long linear_offset;
17638cd6 2787 u32 dspcntr;
f45651ba 2788 u32 reg = DSPCNTR(plane);
48404c1e 2789 int pixel_size;
f45651ba 2790
b70709a6 2791 if (!visible || !fb) {
fdd508a6
VS		 2792 I915_WRITE(reg, 0);
2793 I915_WRITE(DSPSURF(plane), 0);
2794 POSTING_READ(reg);
2795 return;
2796 }
2797
c9ba6fad
VS		 2798 obj = intel_fb_obj(fb);
2799 if (WARN_ON(obj == NULL))
2800 return;
2801
2802 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2803
f45651ba
VS		 2804 dspcntr = DISPPLANE_GAMMA_ENABLE;
2805
fdd508a6 2806 dspcntr |= DISPLAY_PLANE_ENABLE;
f45651ba
VS		 2807
2808 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2809 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
17638cd6 2810
57779d06
VS		 2811 switch (fb->pixel_format) {
2812 case DRM_FORMAT_C8:
17638cd6
JB		 2813 dspcntr |= DISPPLANE_8BPP;
2814 break;
57779d06
VS		 2815 case DRM_FORMAT_RGB565:
2816 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2817 break;
57779d06
VS		 2818 case DRM_FORMAT_XRGB8888:
2819 case DRM_FORMAT_ARGB8888:
2820 dspcntr |= DISPPLANE_BGRX888;
2821 break;
2822 case DRM_FORMAT_XBGR8888:
2823 case DRM_FORMAT_ABGR8888:
2824 dspcntr |= DISPPLANE_RGBX888;
2825 break;
2826 case DRM_FORMAT_XRGB2101010:
2827 case DRM_FORMAT_ARGB2101010:
2828 dspcntr |= DISPPLANE_BGRX101010;
2829 break;
2830 case DRM_FORMAT_XBGR2101010:
2831 case DRM_FORMAT_ABGR2101010:
2832 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2833 break;
2834 default:
baba133a 2835 BUG();
17638cd6
JB		 2836 }
2837
2838 if (obj->tiling_mode != I915_TILING_NONE)
2839 dspcntr |= DISPPLANE_TILED;
17638cd6 2840
f45651ba 2841 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
1f5d76db 2842 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
17638cd6 2843
b9897127 2844 linear_offset = y * fb->pitches[0] + x * pixel_size;
c2c75131 2845 intel_crtc->dspaddr_offset =
bc752862 2846 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
b9897127 2847 pixel_size,
bc752862 2848 fb->pitches[0]);
c2c75131 2849 linear_offset -= intel_crtc->dspaddr_offset;
8e7d688b 2850 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
48404c1e
SJ		 2851 dspcntr |= DISPPLANE_ROTATE_180;
2852
2853 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
6e3c9717
ACO		 2854 x += (intel_crtc->config->pipe_src_w - 1);
2855 y += (intel_crtc->config->pipe_src_h - 1);
48404c1e
SJ		 2856
2857 /* Finding the last pixel of the last line of the display
2858 data and adding to linear_offset*/
2859 linear_offset +=
6e3c9717
ACO		 2860 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2861 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
48404c1e
SJ		 2862 }
2863 }
2864
2865 I915_WRITE(reg, dspcntr);
17638cd6 2866
01f2c773 2867 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
85ba7b7d
DV		 2868 I915_WRITE(DSPSURF(plane),
2869 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
b3dc685e 2870 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
bc1c91eb
DL		 2871 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2872 } else {
2873 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2874 I915_WRITE(DSPLINOFF(plane), linear_offset);
2875 }
17638cd6 2876 POSTING_READ(reg);
17638cd6
JB		 2877}
2878
b321803d
DL		 2879u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2880 uint32_t pixel_format)
2881{
2882 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2883
2884 /*
2885 * The stride is either expressed as a multiple of 64 bytes
2886 * chunks for linear buffers or in number of tiles for tiled
2887 * buffers.
2888 */
2889 switch (fb_modifier) {
2890 case DRM_FORMAT_MOD_NONE:
2891 return 64;
2892 case I915_FORMAT_MOD_X_TILED:
2893 if (INTEL_INFO(dev)->gen == 2)
2894 return 128;
2895 return 512;
2896 case I915_FORMAT_MOD_Y_TILED:
2897 /* No need to check for old gens and Y tiling since this is
2898 * about the display engine and those will be blocked before
2899 * we get here.
2900 */
2901 return 128;
2902 case I915_FORMAT_MOD_Yf_TILED:
2903 if (bits_per_pixel == 8)
2904 return 64;
2905 else
2906 return 128;
2907 default:
2908 MISSING_CASE(fb_modifier);
2909 return 64;
2910 }
2911}
2912
121920fa
TU		 2913unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
2914 struct drm_i915_gem_object *obj)
2915{
9abc4648 2916 const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
121920fa
TU		 2917
2918 if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
9abc4648 2919 view = &i915_ggtt_view_rotated;
121920fa
TU		 2920
2921 return i915_gem_obj_ggtt_offset_view(obj, view);
2922}
2923
a1b2278e
CK		 2924/*
2925 * This function detaches (aka. unbinds) unused scalers in hardware
2926 */
2927void skl_detach_scalers(struct intel_crtc *intel_crtc)
2928{
2929 struct drm_device *dev;
2930 struct drm_i915_private *dev_priv;
2931 struct intel_crtc_scaler_state *scaler_state;
2932 int i;
2933
2934 if (!intel_crtc || !intel_crtc->config)
2935 return;
2936
2937 dev = intel_crtc->base.dev;
2938 dev_priv = dev->dev_private;
2939 scaler_state = &intel_crtc->config->scaler_state;
2940
2941 /* loop through and disable scalers that aren't in use */
2942 for (i = 0; i < intel_crtc->num_scalers; i++) {
2943 if (!scaler_state->scalers[i].in_use) {
2944 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, i), 0);
2945 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, i), 0);
2946 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, i), 0);
2947 DRM_DEBUG_KMS("CRTC:%d Disabled scaler id %u.%u\n",
2948 intel_crtc->base.base.id, intel_crtc->pipe, i);
2949 }
2950 }
2951}
2952
6156a456 2953u32 skl_plane_ctl_format(uint32_t pixel_format)
70d21f0e 2954{
6156a456 2955 switch (pixel_format) {
d161cf7a 2956 case DRM_FORMAT_C8:
c34ce3d1 2957 return PLANE_CTL_FORMAT_INDEXED;
70d21f0e 2958 case DRM_FORMAT_RGB565:
c34ce3d1 2959 return PLANE_CTL_FORMAT_RGB_565;
70d21f0e 2960 case DRM_FORMAT_XBGR8888:
c34ce3d1 2961 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
6156a456 2962 case DRM_FORMAT_XRGB8888:
c34ce3d1 2963 return PLANE_CTL_FORMAT_XRGB_8888;
6156a456
CK		 2964 /*
2965 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2966 * to be already pre-multiplied. We need to add a knob (or a different
2967 * DRM_FORMAT) for user-space to configure that.
2968 */
f75fb42a 2969 case DRM_FORMAT_ABGR8888:
c34ce3d1 2970 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
6156a456 2971 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
6156a456 2972 case DRM_FORMAT_ARGB8888:
c34ce3d1 2973 return PLANE_CTL_FORMAT_XRGB_8888 |
6156a456 2974 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
70d21f0e 2975 case DRM_FORMAT_XRGB2101010:
c34ce3d1 2976 return PLANE_CTL_FORMAT_XRGB_2101010;
70d21f0e 2977 case DRM_FORMAT_XBGR2101010:
c34ce3d1 2978 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
6156a456 2979 case DRM_FORMAT_YUYV:
c34ce3d1 2980 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
6156a456 2981 case DRM_FORMAT_YVYU:
c34ce3d1 2982 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
6156a456 2983 case DRM_FORMAT_UYVY:
c34ce3d1 2984 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
6156a456 2985 case DRM_FORMAT_VYUY:
c34ce3d1 2986 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
70d21f0e 2987 default:
4249eeef 2988 MISSING_CASE(pixel_format);
70d21f0e 2989 }
8cfcba41 2990
c34ce3d1 2991 return 0;
6156a456 2992}
70d21f0e 2993
6156a456
CK		 2994u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
2995{
6156a456 2996 switch (fb_modifier) {
30af77c4 2997 case DRM_FORMAT_MOD_NONE:
70d21f0e 2998 break;
30af77c4 2999 case I915_FORMAT_MOD_X_TILED:
c34ce3d1 3000 return PLANE_CTL_TILED_X;
b321803d 3001 case I915_FORMAT_MOD_Y_TILED:
c34ce3d1 3002 return PLANE_CTL_TILED_Y;
b321803d 3003 case I915_FORMAT_MOD_Yf_TILED:
c34ce3d1 3004 return PLANE_CTL_TILED_YF;
70d21f0e 3005 default:
6156a456 3006 MISSING_CASE(fb_modifier);
70d21f0e 3007 }
8cfcba41 3008
c34ce3d1 3009 return 0;
6156a456 3010}
70d21f0e 3011
6156a456
CK		 3012u32 skl_plane_ctl_rotation(unsigned int rotation)
3013{
3b7a5119 3014 switch (rotation) {
6156a456
CK		 3015 case BIT(DRM_ROTATE_0):
3016 break;
3b7a5119 3017 case BIT(DRM_ROTATE_90):
c34ce3d1 3018 return PLANE_CTL_ROTATE_90;
3b7a5119 3019 case BIT(DRM_ROTATE_180):
c34ce3d1 3020 return PLANE_CTL_ROTATE_180;
3b7a5119 3021 case BIT(DRM_ROTATE_270):
c34ce3d1 3022 return PLANE_CTL_ROTATE_270;
6156a456
CK		 3023 default:
3024 MISSING_CASE(rotation);
3025 }
3026
c34ce3d1 3027 return 0;
6156a456
CK		 3028}
3029
3030static void skylake_update_primary_plane(struct drm_crtc *crtc,
3031 struct drm_framebuffer *fb,
3032 int x, int y)
3033{
3034 struct drm_device *dev = crtc->dev;
3035 struct drm_i915_private *dev_priv = dev->dev_private;
3036 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML		 3037 struct drm_plane *plane = crtc->primary;
3038 bool visible = to_intel_plane_state(plane->state)->visible;
6156a456
CK		 3039 struct drm_i915_gem_object *obj;
3040 int pipe = intel_crtc->pipe;
3041 u32 plane_ctl, stride_div, stride;
3042 u32 tile_height, plane_offset, plane_size;
3043 unsigned int rotation;
3044 int x_offset, y_offset;
3045 unsigned long surf_addr;
6156a456
CK		 3046 struct intel_crtc_state *crtc_state = intel_crtc->config;
3047 struct intel_plane_state *plane_state;
3048 int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3049 int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3050 int scaler_id = -1;
3051
6156a456
CK		 3052 plane_state = to_intel_plane_state(plane->state);
3053
b70709a6 3054 if (!visible || !fb) {
6156a456
CK		 3055 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3056 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3057 POSTING_READ(PLANE_CTL(pipe, 0));
3058 return;
3b7a5119 3059 }
70d21f0e 3060
6156a456
CK		 3061 plane_ctl = PLANE_CTL_ENABLE |
3062 PLANE_CTL_PIPE_GAMMA_ENABLE |
3063 PLANE_CTL_PIPE_CSC_ENABLE;
3064
3065 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3066 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3067 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3068
3069 rotation = plane->state->rotation;
3070 plane_ctl |= skl_plane_ctl_rotation(rotation);
3071
b321803d
DL		 3072 obj = intel_fb_obj(fb);
3073 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3074 fb->pixel_format);
3b7a5119
SJ		 3075 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj);
3076
6156a456
CK		 3077 /*
3078 * FIXME: intel_plane_state->src, dst aren't set when transitional
3079 * update_plane helpers are called from legacy paths.
3080 * Once full atomic crtc is available, below check can be avoided.
3081 */
3082 if (drm_rect_width(&plane_state->src)) {
3083 scaler_id = plane_state->scaler_id;
3084 src_x = plane_state->src.x1 >> 16;
3085 src_y = plane_state->src.y1 >> 16;
3086 src_w = drm_rect_width(&plane_state->src) >> 16;
3087 src_h = drm_rect_height(&plane_state->src) >> 16;
3088 dst_x = plane_state->dst.x1;
3089 dst_y = plane_state->dst.y1;
3090 dst_w = drm_rect_width(&plane_state->dst);
3091 dst_h = drm_rect_height(&plane_state->dst);
3092
3093 WARN_ON(x != src_x || y != src_y);
3094 } else {
3095 src_w = intel_crtc->config->pipe_src_w;
3096 src_h = intel_crtc->config->pipe_src_h;
3097 }
3098
3b7a5119
SJ		 3099 if (intel_rotation_90_or_270(rotation)) {
3100 /* stride = Surface height in tiles */
2614f17d 3101 tile_height = intel_tile_height(dev, fb->pixel_format,
3b7a5119
SJ		 3102 fb->modifier[0]);
3103 stride = DIV_ROUND_UP(fb->height, tile_height);
6156a456 3104 x_offset = stride * tile_height - y - src_h;
3b7a5119 3105 y_offset = x;
6156a456 3106 plane_size = (src_w - 1) << 16 | (src_h - 1);
3b7a5119
SJ		 3107 } else {
3108 stride = fb->pitches[0] / stride_div;
3109 x_offset = x;
3110 y_offset = y;
6156a456 3111 plane_size = (src_h - 1) << 16 | (src_w - 1);
3b7a5119
SJ		 3112 }
3113 plane_offset = y_offset << 16 | x_offset;
b321803d 3114
70d21f0e 3115 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3b7a5119
SJ		 3116 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3117 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3118 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
6156a456
CK		 3119
3120 if (scaler_id >= 0) {
3121 uint32_t ps_ctrl = 0;
3122
3123 WARN_ON(!dst_w || !dst_h);
3124 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3125 crtc_state->scaler_state.scalers[scaler_id].mode;
3126 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3127 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3128 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3129 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3130 I915_WRITE(PLANE_POS(pipe, 0), 0);
3131 } else {
3132 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3133 }
3134
121920fa 3135 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
70d21f0e
DL		 3136
3137 POSTING_READ(PLANE_SURF(pipe, 0));
3138}
3139
17638cd6
JB		 3140/* Assume fb object is pinned & idle & fenced and just update base pointers */
3141static int
3142intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3143 int x, int y, enum mode_set_atomic state)
3144{
3145 struct drm_device *dev = crtc->dev;
3146 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 3147
6b8e6ed0
CW		 3148 if (dev_priv->display.disable_fbc)
3149 dev_priv->display.disable_fbc(dev);
81255565 3150
29b9bde6
DV		 3151 dev_priv->display.update_primary_plane(crtc, fb, x, y);
3152
3153 return 0;
81255565
JB		 3154}
3155
7514747d 3156static void intel_complete_page_flips(struct drm_device *dev)
96a02917 3157{
96a02917
VS		 3158 struct drm_crtc *crtc;
3159
70e1e0ec 3160 for_each_crtc(dev, crtc) {
96a02917
VS		 3161 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3162 enum plane plane = intel_crtc->plane;
3163
3164 intel_prepare_page_flip(dev, plane);
3165 intel_finish_page_flip_plane(dev, plane);
3166 }
7514747d
VS		 3167}
3168
3169static void intel_update_primary_planes(struct drm_device *dev)
3170{
3171 struct drm_i915_private *dev_priv = dev->dev_private;
3172 struct drm_crtc *crtc;
96a02917 3173
70e1e0ec 3174 for_each_crtc(dev, crtc) {
96a02917
VS		 3175 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3176
51fd371b 3177 drm_modeset_lock(&crtc->mutex, NULL);
947fdaad
CW		 3178 /*
3179 * FIXME: Once we have proper support for primary planes (and
3180 * disabling them without disabling the entire crtc) allow again
66e514c1 3181 * a NULL crtc->primary->fb.
947fdaad 3182 */
f4510a27 3183 if (intel_crtc->active && crtc->primary->fb)
262ca2b0 3184 dev_priv->display.update_primary_plane(crtc,
66e514c1 3185 crtc->primary->fb,
262ca2b0
MR		 3186 crtc->x,
3187 crtc->y);
51fd371b 3188 drm_modeset_unlock(&crtc->mutex);
96a02917
VS		 3189 }
3190}
3191
ce22dba9
ML		 3192void intel_crtc_reset(struct intel_crtc *crtc)
3193{
3194 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3195
3196 if (!crtc->active)
3197 return;
3198
3199 intel_crtc_disable_planes(&crtc->base);
3200 dev_priv->display.crtc_disable(&crtc->base);
3201 dev_priv->display.crtc_enable(&crtc->base);
3202 intel_crtc_enable_planes(&crtc->base);
3203}
3204
7514747d
VS		 3205void intel_prepare_reset(struct drm_device *dev)
3206{
f98ce92f
VS		 3207 struct drm_i915_private *dev_priv = to_i915(dev);
3208 struct intel_crtc *crtc;
3209
7514747d
VS		 3210 /* no reset support for gen2 */
3211 if (IS_GEN2(dev))
3212 return;
3213
3214 /* reset doesn't touch the display */
3215 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3216 return;
3217
3218 drm_modeset_lock_all(dev);
f98ce92f
VS		 3219
3220 /*
3221 * Disabling the crtcs gracefully seems nicer. Also the
3222 * g33 docs say we should at least disable all the planes.
3223 */
3224 for_each_intel_crtc(dev, crtc) {
ce22dba9
ML		 3225 if (!crtc->active)
3226 continue;
3227
3228 intel_crtc_disable_planes(&crtc->base);
3229 dev_priv->display.crtc_disable(&crtc->base);
f98ce92f 3230 }
7514747d
VS		 3231}
3232
3233void intel_finish_reset(struct drm_device *dev)
3234{
3235 struct drm_i915_private *dev_priv = to_i915(dev);
3236
3237 /*
3238 * Flips in the rings will be nuked by the reset,
3239 * so complete all pending flips so that user space
3240 * will get its events and not get stuck.
3241 */
3242 intel_complete_page_flips(dev);
3243
3244 /* no reset support for gen2 */
3245 if (IS_GEN2(dev))
3246 return;
3247
3248 /* reset doesn't touch the display */
3249 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3250 /*
3251 * Flips in the rings have been nuked by the reset,
3252 * so update the base address of all primary
3253 * planes to the the last fb to make sure we're
3254 * showing the correct fb after a reset.
3255 */
3256 intel_update_primary_planes(dev);
3257 return;
3258 }
3259
3260 /*
3261 * The display has been reset as well,
3262 * so need a full re-initialization.
3263 */
3264 intel_runtime_pm_disable_interrupts(dev_priv);
3265 intel_runtime_pm_enable_interrupts(dev_priv);
3266
3267 intel_modeset_init_hw(dev);
3268
3269 spin_lock_irq(&dev_priv->irq_lock);
3270 if (dev_priv->display.hpd_irq_setup)
3271 dev_priv->display.hpd_irq_setup(dev);
3272 spin_unlock_irq(&dev_priv->irq_lock);
3273
3274 intel_modeset_setup_hw_state(dev, true);
3275
3276 intel_hpd_init(dev_priv);
3277
3278 drm_modeset_unlock_all(dev);
3279}
3280
2e2f351d 3281static void
14667a4b
CW		 3282intel_finish_fb(struct drm_framebuffer *old_fb)
3283{
2ff8fde1 3284 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
2e2f351d 3285 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
14667a4b
CW		 3286 bool was_interruptible = dev_priv->mm.interruptible;
3287 int ret;
3288
14667a4b
CW		 3289 /* Big Hammer, we also need to ensure that any pending
3290 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3291 * current scanout is retired before unpinning the old
2e2f351d
CW		 3292 * framebuffer. Note that we rely on userspace rendering
3293 * into the buffer attached to the pipe they are waiting
3294 * on. If not, userspace generates a GPU hang with IPEHR
3295 * point to the MI_WAIT_FOR_EVENT.
14667a4b
CW		 3296 *
3297 * This should only fail upon a hung GPU, in which case we
3298 * can safely continue.
3299 */
3300 dev_priv->mm.interruptible = false;
2e2f351d 3301 ret = i915_gem_object_wait_rendering(obj, true);
14667a4b
CW		 3302 dev_priv->mm.interruptible = was_interruptible;
3303
2e2f351d 3304 WARN_ON(ret);
14667a4b
CW		 3305}
3306
7d5e3799
CW		 3307static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3308{
3309 struct drm_device *dev = crtc->dev;
3310 struct drm_i915_private *dev_priv = dev->dev_private;
3311 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7d5e3799
CW		 3312 bool pending;
3313
3314 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3315 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3316 return false;
3317
5e2d7afc 3318 spin_lock_irq(&dev->event_lock);
7d5e3799 3319 pending = to_intel_crtc(crtc)->unpin_work != NULL;
5e2d7afc 3320 spin_unlock_irq(&dev->event_lock);
7d5e3799
CW		 3321
3322 return pending;
3323}
3324
e30e8f75
GP		 3325static void intel_update_pipe_size(struct intel_crtc *crtc)
3326{
3327 struct drm_device *dev = crtc->base.dev;
3328 struct drm_i915_private *dev_priv = dev->dev_private;
3329 const struct drm_display_mode *adjusted_mode;
3330
3331 if (!i915.fastboot)
3332 return;
3333
3334 /*
3335 * Update pipe size and adjust fitter if needed: the reason for this is
3336 * that in compute_mode_changes we check the native mode (not the pfit
3337 * mode) to see if we can flip rather than do a full mode set. In the
3338 * fastboot case, we'll flip, but if we don't update the pipesrc and
3339 * pfit state, we'll end up with a big fb scanned out into the wrong
3340 * sized surface.
3341 *
3342 * To fix this properly, we need to hoist the checks up into
3343 * compute_mode_changes (or above), check the actual pfit state and
3344 * whether the platform allows pfit disable with pipe active, and only
3345 * then update the pipesrc and pfit state, even on the flip path.
3346 */
3347
6e3c9717 3348 adjusted_mode = &crtc->config->base.adjusted_mode;
e30e8f75
GP		 3349
3350 I915_WRITE(PIPESRC(crtc->pipe),
3351 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3352 (adjusted_mode->crtc_vdisplay - 1));
6e3c9717 3353 if (!crtc->config->pch_pfit.enabled &&
409ee761
ACO		 3354 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3355 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
e30e8f75
GP		 3356 I915_WRITE(PF_CTL(crtc->pipe), 0);
3357 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3358 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3359 }
6e3c9717
ACO		 3360 crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3361 crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
e30e8f75
GP		 3362}
3363
5e84e1a4
ZW		 3364static void intel_fdi_normal_train(struct drm_crtc *crtc)
3365{
3366 struct drm_device *dev = crtc->dev;
3367 struct drm_i915_private *dev_priv = dev->dev_private;
3368 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3369 int pipe = intel_crtc->pipe;
3370 u32 reg, temp;
3371
3372 /* enable normal train */
3373 reg = FDI_TX_CTL(pipe);
3374 temp = I915_READ(reg);
61e499bf 3375 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 3376 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3377 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 3378 } else {
3379 temp &= ~FDI_LINK_TRAIN_NONE;
3380 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 3381 }
5e84e1a4
ZW		 3382 I915_WRITE(reg, temp);
3383
3384 reg = FDI_RX_CTL(pipe);
3385 temp = I915_READ(reg);
3386 if (HAS_PCH_CPT(dev)) {
3387 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3388 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3389 } else {
3390 temp &= ~FDI_LINK_TRAIN_NONE;
3391 temp |= FDI_LINK_TRAIN_NONE;
3392 }
3393 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3394
3395 /* wait one idle pattern time */
3396 POSTING_READ(reg);
3397 udelay(1000);
357555c0
JB		 3398
3399 /* IVB wants error correction enabled */
3400 if (IS_IVYBRIDGE(dev))
3401 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3402 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 3403}
3404
8db9d77b
ZW		 3405/* The FDI link training functions for ILK/Ibexpeak. */
3406static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3407{
3408 struct drm_device *dev = crtc->dev;
3409 struct drm_i915_private *dev_priv = dev->dev_private;
3410 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3411 int pipe = intel_crtc->pipe;
5eddb70b 3412 u32 reg, temp, tries;
8db9d77b 3413
1c8562f6 3414 /* FDI needs bits from pipe first */
0fc932b8 3415 assert_pipe_enabled(dev_priv, pipe);
0fc932b8 3416
e1a44743
AJ		 3417 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3418 for train result */
5eddb70b
CW		 3419 reg = FDI_RX_IMR(pipe);
3420 temp = I915_READ(reg);
e1a44743
AJ		 3421 temp &= ~FDI_RX_SYMBOL_LOCK;
3422 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 3423 I915_WRITE(reg, temp);
3424 I915_READ(reg);
e1a44743
AJ		 3425 udelay(150);
3426
8db9d77b 3427 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 3428 reg = FDI_TX_CTL(pipe);
3429 temp = I915_READ(reg);
627eb5a3 3430 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3431 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
8db9d77b
ZW		 3432 temp &= ~FDI_LINK_TRAIN_NONE;
3433 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 3434 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 3435
5eddb70b
CW		 3436 reg = FDI_RX_CTL(pipe);
3437 temp = I915_READ(reg);
8db9d77b
ZW		 3438 temp &= ~FDI_LINK_TRAIN_NONE;
3439 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 3440 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3441
3442 POSTING_READ(reg);
8db9d77b
ZW		 3443 udelay(150);
3444
5b2adf89 3445 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 3446 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3447 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3448 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 3449
5eddb70b 3450 reg = FDI_RX_IIR(pipe);
e1a44743 3451 for (tries = 0; tries < 5; tries++) {
5eddb70b 3452 temp = I915_READ(reg);
8db9d77b
ZW		 3453 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3454
3455 if ((temp & FDI_RX_BIT_LOCK)) {
3456 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 3457 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 3458 break;
3459 }
8db9d77b 3460 }
e1a44743 3461 if (tries == 5)
5eddb70b 3462 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 3463
3464 /* Train 2 */
5eddb70b
CW		 3465 reg = FDI_TX_CTL(pipe);
3466 temp = I915_READ(reg);
8db9d77b
ZW		 3467 temp &= ~FDI_LINK_TRAIN_NONE;
3468 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 3469 I915_WRITE(reg, temp);
8db9d77b 3470
5eddb70b
CW		 3471 reg = FDI_RX_CTL(pipe);
3472 temp = I915_READ(reg);
8db9d77b
ZW		 3473 temp &= ~FDI_LINK_TRAIN_NONE;
3474 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 3475 I915_WRITE(reg, temp);
8db9d77b 3476
5eddb70b
CW		 3477 POSTING_READ(reg);
3478 udelay(150);
8db9d77b 3479
5eddb70b 3480 reg = FDI_RX_IIR(pipe);
e1a44743 3481 for (tries = 0; tries < 5; tries++) {
5eddb70b 3482 temp = I915_READ(reg);
8db9d77b
ZW		 3483 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3484
3485 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 3486 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 3487 DRM_DEBUG_KMS("FDI train 2 done.\n");
3488 break;
3489 }
8db9d77b 3490 }
e1a44743 3491 if (tries == 5)
5eddb70b 3492 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 3493
3494 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 3495
8db9d77b
ZW		 3496}
3497
0206e353 3498static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 3499 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3500 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3501 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3502 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3503};
3504
3505/* The FDI link training functions for SNB/Cougarpoint. */
3506static void gen6_fdi_link_train(struct drm_crtc *crtc)
3507{
3508 struct drm_device *dev = crtc->dev;
3509 struct drm_i915_private *dev_priv = dev->dev_private;
3510 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3511 int pipe = intel_crtc->pipe;
fa37d39e 3512 u32 reg, temp, i, retry;
8db9d77b 3513
e1a44743
AJ		 3514 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3515 for train result */
5eddb70b
CW		 3516 reg = FDI_RX_IMR(pipe);
3517 temp = I915_READ(reg);
e1a44743
AJ		 3518 temp &= ~FDI_RX_SYMBOL_LOCK;
3519 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 3520 I915_WRITE(reg, temp);
3521
3522 POSTING_READ(reg);
e1a44743
AJ		 3523 udelay(150);
3524
8db9d77b 3525 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 3526 reg = FDI_TX_CTL(pipe);
3527 temp = I915_READ(reg);
627eb5a3 3528 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3529 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
8db9d77b
ZW		 3530 temp &= ~FDI_LINK_TRAIN_NONE;
3531 temp |= FDI_LINK_TRAIN_PATTERN_1;
3532 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3533 /* SNB-B */
3534 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 3535 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 3536
d74cf324
DV		 3537 I915_WRITE(FDI_RX_MISC(pipe),
3538 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3539
5eddb70b
CW		 3540 reg = FDI_RX_CTL(pipe);
3541 temp = I915_READ(reg);
8db9d77b
ZW		 3542 if (HAS_PCH_CPT(dev)) {
3543 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3544 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3545 } else {
3546 temp &= ~FDI_LINK_TRAIN_NONE;
3547 temp |= FDI_LINK_TRAIN_PATTERN_1;
3548 }
5eddb70b
CW		 3549 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3550
3551 POSTING_READ(reg);
8db9d77b
ZW		 3552 udelay(150);
3553
0206e353 3554 for (i = 0; i < 4; i++) {
5eddb70b
CW		 3555 reg = FDI_TX_CTL(pipe);
3556 temp = I915_READ(reg);
8db9d77b
ZW		 3557 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3558 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 3559 I915_WRITE(reg, temp);
3560
3561 POSTING_READ(reg);
8db9d77b
ZW		 3562 udelay(500);
3563
fa37d39e
SP		 3564 for (retry = 0; retry < 5; retry++) {
3565 reg = FDI_RX_IIR(pipe);
3566 temp = I915_READ(reg);
3567 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3568 if (temp & FDI_RX_BIT_LOCK) {
3569 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3570 DRM_DEBUG_KMS("FDI train 1 done.\n");
3571 break;
3572 }
3573 udelay(50);
8db9d77b 3574 }
fa37d39e
SP		 3575 if (retry < 5)
3576 break;
8db9d77b
ZW		 3577 }
3578 if (i == 4)
5eddb70b 3579 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 3580
3581 /* Train 2 */
5eddb70b
CW		 3582 reg = FDI_TX_CTL(pipe);
3583 temp = I915_READ(reg);
8db9d77b
ZW		 3584 temp &= ~FDI_LINK_TRAIN_NONE;
3585 temp |= FDI_LINK_TRAIN_PATTERN_2;
3586 if (IS_GEN6(dev)) {
3587 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3588 /* SNB-B */
3589 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3590 }
5eddb70b 3591 I915_WRITE(reg, temp);
8db9d77b 3592
5eddb70b
CW		 3593 reg = FDI_RX_CTL(pipe);
3594 temp = I915_READ(reg);
8db9d77b
ZW		 3595 if (HAS_PCH_CPT(dev)) {
3596 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3597 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3598 } else {
3599 temp &= ~FDI_LINK_TRAIN_NONE;
3600 temp |= FDI_LINK_TRAIN_PATTERN_2;
3601 }
5eddb70b
CW		 3602 I915_WRITE(reg, temp);
3603
3604 POSTING_READ(reg);
8db9d77b
ZW		 3605 udelay(150);
3606
0206e353 3607 for (i = 0; i < 4; i++) {
5eddb70b
CW		 3608 reg = FDI_TX_CTL(pipe);
3609 temp = I915_READ(reg);
8db9d77b
ZW		 3610 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3611 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 3612 I915_WRITE(reg, temp);
3613
3614 POSTING_READ(reg);
8db9d77b
ZW		 3615 udelay(500);
3616
fa37d39e
SP		 3617 for (retry = 0; retry < 5; retry++) {
3618 reg = FDI_RX_IIR(pipe);
3619 temp = I915_READ(reg);
3620 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3621 if (temp & FDI_RX_SYMBOL_LOCK) {
3622 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3623 DRM_DEBUG_KMS("FDI train 2 done.\n");
3624 break;
3625 }
3626 udelay(50);
8db9d77b 3627 }
fa37d39e
SP		 3628 if (retry < 5)
3629 break;
8db9d77b
ZW		 3630 }
3631 if (i == 4)
5eddb70b 3632 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 3633
3634 DRM_DEBUG_KMS("FDI train done.\n");
3635}
3636
357555c0
JB		 3637/* Manual link training for Ivy Bridge A0 parts */
3638static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3639{
3640 struct drm_device *dev = crtc->dev;
3641 struct drm_i915_private *dev_priv = dev->dev_private;
3642 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3643 int pipe = intel_crtc->pipe;
139ccd3f 3644 u32 reg, temp, i, j;
357555c0
JB		 3645
3646 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3647 for train result */
3648 reg = FDI_RX_IMR(pipe);
3649 temp = I915_READ(reg);
3650 temp &= ~FDI_RX_SYMBOL_LOCK;
3651 temp &= ~FDI_RX_BIT_LOCK;
3652 I915_WRITE(reg, temp);
3653
3654 POSTING_READ(reg);
3655 udelay(150);
3656
01a415fd
DV		 3657 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3658 I915_READ(FDI_RX_IIR(pipe)));
3659
139ccd3f
JB		 3660 /* Try each vswing and preemphasis setting twice before moving on */
3661 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3662 /* disable first in case we need to retry */
3663 reg = FDI_TX_CTL(pipe);
3664 temp = I915_READ(reg);
3665 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3666 temp &= ~FDI_TX_ENABLE;
3667 I915_WRITE(reg, temp);
357555c0 3668
139ccd3f
JB		 3669 reg = FDI_RX_CTL(pipe);
3670 temp = I915_READ(reg);
3671 temp &= ~FDI_LINK_TRAIN_AUTO;
3672 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3673 temp &= ~FDI_RX_ENABLE;
3674 I915_WRITE(reg, temp);
357555c0 3675
139ccd3f 3676 /* enable CPU FDI TX and PCH FDI RX */
357555c0
JB		 3677 reg = FDI_TX_CTL(pipe);
3678 temp = I915_READ(reg);
139ccd3f 3679 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3680 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
139ccd3f 3681 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
357555c0 3682 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
139ccd3f
JB		 3683 temp |= snb_b_fdi_train_param[j/2];
3684 temp |= FDI_COMPOSITE_SYNC;
3685 I915_WRITE(reg, temp | FDI_TX_ENABLE);
357555c0 3686
139ccd3f
JB		 3687 I915_WRITE(FDI_RX_MISC(pipe),
3688 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
357555c0 3689
139ccd3f 3690 reg = FDI_RX_CTL(pipe);
357555c0 3691 temp = I915_READ(reg);
139ccd3f
JB		 3692 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3693 temp |= FDI_COMPOSITE_SYNC;
3694 I915_WRITE(reg, temp | FDI_RX_ENABLE);
357555c0 3695
139ccd3f
JB		 3696 POSTING_READ(reg);
3697 udelay(1); /* should be 0.5us */
357555c0 3698
139ccd3f
JB		 3699 for (i = 0; i < 4; i++) {
3700 reg = FDI_RX_IIR(pipe);
3701 temp = I915_READ(reg);
3702 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 3703
139ccd3f
JB		 3704 if (temp & FDI_RX_BIT_LOCK ||
3705 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3706 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3707 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3708 i);
3709 break;
3710 }
3711 udelay(1); /* should be 0.5us */
3712 }
3713 if (i == 4) {
3714 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3715 continue;
3716 }
357555c0 3717
139ccd3f 3718 /* Train 2 */
357555c0
JB		 3719 reg = FDI_TX_CTL(pipe);
3720 temp = I915_READ(reg);
139ccd3f
JB		 3721 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3722 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3723 I915_WRITE(reg, temp);
3724
3725 reg = FDI_RX_CTL(pipe);
3726 temp = I915_READ(reg);
3727 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3728 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
357555c0
JB		 3729 I915_WRITE(reg, temp);
3730
3731 POSTING_READ(reg);
139ccd3f 3732 udelay(2); /* should be 1.5us */
357555c0 3733
139ccd3f
JB		 3734 for (i = 0; i < 4; i++) {
3735 reg = FDI_RX_IIR(pipe);
3736 temp = I915_READ(reg);
3737 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 3738
139ccd3f
JB		 3739 if (temp & FDI_RX_SYMBOL_LOCK ||
3740 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3741 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3742 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3743 i);
3744 goto train_done;
3745 }
3746 udelay(2); /* should be 1.5us */
357555c0 3747 }
139ccd3f
JB		 3748 if (i == 4)
3749 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
357555c0 3750 }
357555c0 3751
139ccd3f 3752train_done:
357555c0
JB		 3753 DRM_DEBUG_KMS("FDI train done.\n");
3754}
3755
88cefb6c 3756static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 3757{
88cefb6c 3758 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 3759 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 3760 int pipe = intel_crtc->pipe;
5eddb70b 3761 u32 reg, temp;
79e53945 3762
c64e311e 3763
c98e9dcf 3764 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 3765 reg = FDI_RX_CTL(pipe);
3766 temp = I915_READ(reg);
627eb5a3 3767 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
6e3c9717 3768 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
dfd07d72 3769 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 3770 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3771
3772 POSTING_READ(reg);
c98e9dcf
JB		 3773 udelay(200);
3774
3775 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 3776 temp = I915_READ(reg);
3777 I915_WRITE(reg, temp | FDI_PCDCLK);
3778
3779 POSTING_READ(reg);
c98e9dcf
JB		 3780 udelay(200);
3781
20749730
PZ		 3782 /* Enable CPU FDI TX PLL, always on for Ironlake */
3783 reg = FDI_TX_CTL(pipe);
3784 temp = I915_READ(reg);
3785 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3786 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 3787
20749730
PZ		 3788 POSTING_READ(reg);
3789 udelay(100);
6be4a607 3790 }
0e23b99d
JB		 3791}
3792
88cefb6c
DV		 3793static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3794{
3795 struct drm_device *dev = intel_crtc->base.dev;
3796 struct drm_i915_private *dev_priv = dev->dev_private;
3797 int pipe = intel_crtc->pipe;
3798 u32 reg, temp;
3799
3800 /* Switch from PCDclk to Rawclk */
3801 reg = FDI_RX_CTL(pipe);
3802 temp = I915_READ(reg);
3803 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3804
3805 /* Disable CPU FDI TX PLL */
3806 reg = FDI_TX_CTL(pipe);
3807 temp = I915_READ(reg);
3808 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3809
3810 POSTING_READ(reg);
3811 udelay(100);
3812
3813 reg = FDI_RX_CTL(pipe);
3814 temp = I915_READ(reg);
3815 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3816
3817 /* Wait for the clocks to turn off. */
3818 POSTING_READ(reg);
3819 udelay(100);
3820}
3821
0fc932b8
JB		 3822static void ironlake_fdi_disable(struct drm_crtc *crtc)
3823{
3824 struct drm_device *dev = crtc->dev;
3825 struct drm_i915_private *dev_priv = dev->dev_private;
3826 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3827 int pipe = intel_crtc->pipe;
3828 u32 reg, temp;
3829
3830 /* disable CPU FDI tx and PCH FDI rx */
3831 reg = FDI_TX_CTL(pipe);
3832 temp = I915_READ(reg);
3833 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3834 POSTING_READ(reg);
3835
3836 reg = FDI_RX_CTL(pipe);
3837 temp = I915_READ(reg);
3838 temp &= ~(0x7 << 16);
dfd07d72 3839 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 3840 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3841
3842 POSTING_READ(reg);
3843 udelay(100);
3844
3845 /* Ironlake workaround, disable clock pointer after downing FDI */
eba905b2 3846 if (HAS_PCH_IBX(dev))
6f06ce18 3847 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
0fc932b8
JB		 3848
3849 /* still set train pattern 1 */
3850 reg = FDI_TX_CTL(pipe);
3851 temp = I915_READ(reg);
3852 temp &= ~FDI_LINK_TRAIN_NONE;
3853 temp |= FDI_LINK_TRAIN_PATTERN_1;
3854 I915_WRITE(reg, temp);
3855
3856 reg = FDI_RX_CTL(pipe);
3857 temp = I915_READ(reg);
3858 if (HAS_PCH_CPT(dev)) {
3859 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3860 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3861 } else {
3862 temp &= ~FDI_LINK_TRAIN_NONE;
3863 temp |= FDI_LINK_TRAIN_PATTERN_1;
3864 }
3865 /* BPC in FDI rx is consistent with that in PIPECONF */
3866 temp &= ~(0x07 << 16);
dfd07d72 3867 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 3868 I915_WRITE(reg, temp);
3869
3870 POSTING_READ(reg);
3871 udelay(100);
3872}
3873
5dce5b93
CW		 3874bool intel_has_pending_fb_unpin(struct drm_device *dev)
3875{
3876 struct intel_crtc *crtc;
3877
3878 /* Note that we don't need to be called with mode_config.lock here
3879 * as our list of CRTC objects is static for the lifetime of the
3880 * device and so cannot disappear as we iterate. Similarly, we can
3881 * happily treat the predicates as racy, atomic checks as userspace
3882 * cannot claim and pin a new fb without at least acquring the
3883 * struct_mutex and so serialising with us.
3884 */
d3fcc808 3885 for_each_intel_crtc(dev, crtc) {
5dce5b93
CW		 3886 if (atomic_read(&crtc->unpin_work_count) == 0)
3887 continue;
3888
3889 if (crtc->unpin_work)
3890 intel_wait_for_vblank(dev, crtc->pipe);
3891
3892 return true;
3893 }
3894
3895 return false;
3896}
3897
d6bbafa1
CW		 3898static void page_flip_completed(struct intel_crtc *intel_crtc)
3899{
3900 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3901 struct intel_unpin_work *work = intel_crtc->unpin_work;
3902
3903 /* ensure that the unpin work is consistent wrt ->pending. */
3904 smp_rmb();
3905 intel_crtc->unpin_work = NULL;
3906
3907 if (work->event)
3908 drm_send_vblank_event(intel_crtc->base.dev,
3909 intel_crtc->pipe,
3910 work->event);
3911
3912 drm_crtc_vblank_put(&intel_crtc->base);
3913
3914 wake_up_all(&dev_priv->pending_flip_queue);
3915 queue_work(dev_priv->wq, &work->work);
3916
3917 trace_i915_flip_complete(intel_crtc->plane,
3918 work->pending_flip_obj);
3919}
3920
46a55d30 3921void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
e6c3a2a6 3922{
0f91128d 3923 struct drm_device *dev = crtc->dev;
5bb61643 3924 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6 3925
2c10d571 3926 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
9c787942
CW		 3927 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3928 !intel_crtc_has_pending_flip(crtc),
3929 60*HZ) == 0)) {
3930 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2c10d571 3931
5e2d7afc 3932 spin_lock_irq(&dev->event_lock);
9c787942
CW		 3933 if (intel_crtc->unpin_work) {
3934 WARN_ONCE(1, "Removing stuck page flip\n");
3935 page_flip_completed(intel_crtc);
3936 }
5e2d7afc 3937 spin_unlock_irq(&dev->event_lock);
9c787942 3938 }
5bb61643 3939
975d568a
CW		 3940 if (crtc->primary->fb) {
3941 mutex_lock(&dev->struct_mutex);
3942 intel_finish_fb(crtc->primary->fb);
3943 mutex_unlock(&dev->struct_mutex);
3944 }
e6c3a2a6
CW		 3945}
3946
e615efe4
ED		 3947/* Program iCLKIP clock to the desired frequency */
3948static void lpt_program_iclkip(struct drm_crtc *crtc)
3949{
3950 struct drm_device *dev = crtc->dev;
3951 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 3952 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
e615efe4
ED		 3953 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3954 u32 temp;
3955
09153000
DV		 3956 mutex_lock(&dev_priv->dpio_lock);
3957
e615efe4
ED		 3958 /* It is necessary to ungate the pixclk gate prior to programming
3959 * the divisors, and gate it back when it is done.
3960 */
3961 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3962
3963 /* Disable SSCCTL */
3964 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 3965 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3966 SBI_SSCCTL_DISABLE,
3967 SBI_ICLK);
e615efe4
ED		 3968
3969 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
12d7ceed 3970 if (clock == 20000) {
e615efe4
ED		 3971 auxdiv = 1;
3972 divsel = 0x41;
3973 phaseinc = 0x20;
3974 } else {
3975 /* The iCLK virtual clock root frequency is in MHz,
241bfc38
DL		 3976 * but the adjusted_mode->crtc_clock in in KHz. To get the
3977 * divisors, it is necessary to divide one by another, so we
e615efe4
ED		 3978 * convert the virtual clock precision to KHz here for higher
3979 * precision.
3980 */
3981 u32 iclk_virtual_root_freq = 172800 * 1000;
3982 u32 iclk_pi_range = 64;
3983 u32 desired_divisor, msb_divisor_value, pi_value;
3984
12d7ceed 3985 desired_divisor = (iclk_virtual_root_freq / clock);
e615efe4
ED		 3986 msb_divisor_value = desired_divisor / iclk_pi_range;
3987 pi_value = desired_divisor % iclk_pi_range;
3988
3989 auxdiv = 0;
3990 divsel = msb_divisor_value - 2;
3991 phaseinc = pi_value;
3992 }
3993
3994 /* This should not happen with any sane values */
3995 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3996 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3997 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3998 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3999
4000 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
12d7ceed 4001 clock,
e615efe4
ED		 4002 auxdiv,
4003 divsel,
4004 phasedir,
4005 phaseinc);
4006
4007 /* Program SSCDIVINTPHASE6 */
988d6ee8 4008 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 4009 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4010 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4011 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4012 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4013 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4014 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 4015 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 4016
4017 /* Program SSCAUXDIV */
988d6ee8 4018 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 4019 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4020 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 4021 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 4022
4023 /* Enable modulator and associated divider */
988d6ee8 4024 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 4025 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 4026 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 4027
4028 /* Wait for initialization time */
4029 udelay(24);
4030
4031 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000
DV		 4032
4033 mutex_unlock(&dev_priv->dpio_lock);
e615efe4
ED		 4034}
4035
275f01b2
DV		 4036static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4037 enum pipe pch_transcoder)
4038{
4039 struct drm_device *dev = crtc->base.dev;
4040 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 4041 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
275f01b2
DV		 4042
4043 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4044 I915_READ(HTOTAL(cpu_transcoder)));
4045 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4046 I915_READ(HBLANK(cpu_transcoder)));
4047 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4048 I915_READ(HSYNC(cpu_transcoder)));
4049
4050 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4051 I915_READ(VTOTAL(cpu_transcoder)));
4052 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4053 I915_READ(VBLANK(cpu_transcoder)));
4054 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4055 I915_READ(VSYNC(cpu_transcoder)));
4056 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4057 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4058}
4059
003632d9 4060static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
1fbc0d78
DV		 4061{
4062 struct drm_i915_private *dev_priv = dev->dev_private;
4063 uint32_t temp;
4064
4065 temp = I915_READ(SOUTH_CHICKEN1);
003632d9 4066 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
1fbc0d78
DV		 4067 return;
4068
4069 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4070 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4071
003632d9
ACO		 4072 temp &= ~FDI_BC_BIFURCATION_SELECT;
4073 if (enable)
4074 temp |= FDI_BC_BIFURCATION_SELECT;
4075
4076 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
1fbc0d78
DV		 4077 I915_WRITE(SOUTH_CHICKEN1, temp);
4078 POSTING_READ(SOUTH_CHICKEN1);
4079}
4080
4081static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4082{
4083 struct drm_device *dev = intel_crtc->base.dev;
1fbc0d78
DV		 4084
4085 switch (intel_crtc->pipe) {
4086 case PIPE_A:
4087 break;
4088 case PIPE_B:
6e3c9717 4089 if (intel_crtc->config->fdi_lanes > 2)
003632d9 4090 cpt_set_fdi_bc_bifurcation(dev, false);
1fbc0d78 4091 else
003632d9 4092 cpt_set_fdi_bc_bifurcation(dev, true);
1fbc0d78
DV		 4093
4094 break;
4095 case PIPE_C:
003632d9 4096 cpt_set_fdi_bc_bifurcation(dev, true);
1fbc0d78
DV		 4097
4098 break;
4099 default:
4100 BUG();
4101 }
4102}
4103
f67a559d
JB		 4104/*
4105 * Enable PCH resources required for PCH ports:
4106 * - PCH PLLs
4107 * - FDI training & RX/TX
4108 * - update transcoder timings
4109 * - DP transcoding bits
4110 * - transcoder
4111 */
4112static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 4113{
4114 struct drm_device *dev = crtc->dev;
4115 struct drm_i915_private *dev_priv = dev->dev_private;
4116 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4117 int pipe = intel_crtc->pipe;
ee7b9f93 4118 u32 reg, temp;
2c07245f 4119
ab9412ba 4120 assert_pch_transcoder_disabled(dev_priv, pipe);
e7e164db 4121
1fbc0d78
DV		 4122 if (IS_IVYBRIDGE(dev))
4123 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4124
cd986abb
DV		 4125 /* Write the TU size bits before fdi link training, so that error
4126 * detection works. */
4127 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4128 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4129
c98e9dcf 4130 /* For PCH output, training FDI link */
674cf967 4131 dev_priv->display.fdi_link_train(crtc);
2c07245f 4132
3ad8a208
DV		 4133 /* We need to program the right clock selection before writing the pixel
4134 * mutliplier into the DPLL. */
303b81e0 4135 if (HAS_PCH_CPT(dev)) {
ee7b9f93 4136 u32 sel;
4b645f14 4137
c98e9dcf 4138 temp = I915_READ(PCH_DPLL_SEL);
11887397
DV		 4139 temp |= TRANS_DPLL_ENABLE(pipe);
4140 sel = TRANS_DPLLB_SEL(pipe);
6e3c9717 4141 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
ee7b9f93
JB		 4142 temp |= sel;
4143 else
4144 temp &= ~sel;
c98e9dcf 4145 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 4146 }
5eddb70b 4147
3ad8a208
DV		 4148 /* XXX: pch pll's can be enabled any time before we enable the PCH
4149 * transcoder, and we actually should do this to not upset any PCH
4150 * transcoder that already use the clock when we share it.
4151 *
4152 * Note that enable_shared_dpll tries to do the right thing, but
4153 * get_shared_dpll unconditionally resets the pll - we need that to have
4154 * the right LVDS enable sequence. */
85b3894f 4155 intel_enable_shared_dpll(intel_crtc);
3ad8a208 4156
d9b6cb56
JB		 4157 /* set transcoder timing, panel must allow it */
4158 assert_panel_unlocked(dev_priv, pipe);
275f01b2 4159 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
8db9d77b 4160
303b81e0 4161 intel_fdi_normal_train(crtc);
5e84e1a4 4162
c98e9dcf 4163 /* For PCH DP, enable TRANS_DP_CTL */
6e3c9717 4164 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
dfd07d72 4165 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 4166 reg = TRANS_DP_CTL(pipe);
4167 temp = I915_READ(reg);
4168 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 4169 TRANS_DP_SYNC_MASK |
4170 TRANS_DP_BPC_MASK);
5eddb70b
CW		 4171 temp |= (TRANS_DP_OUTPUT_ENABLE |
4172 TRANS_DP_ENH_FRAMING);
9325c9f0 4173 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 4174
4175 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 4176 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 4177 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 4178 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 4179
4180 switch (intel_trans_dp_port_sel(crtc)) {
4181 case PCH_DP_B:
5eddb70b 4182 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 4183 break;
4184 case PCH_DP_C:
5eddb70b 4185 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 4186 break;
4187 case PCH_DP_D:
5eddb70b 4188 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 4189 break;
4190 default:
e95d41e1 4191 BUG();
32f9d658 4192 }
2c07245f 4193
5eddb70b 4194 I915_WRITE(reg, temp);
6be4a607 4195 }
b52eb4dc 4196
b8a4f404 4197 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 4198}
4199
1507e5bd
PZ		 4200static void lpt_pch_enable(struct drm_crtc *crtc)
4201{
4202 struct drm_device *dev = crtc->dev;
4203 struct drm_i915_private *dev_priv = dev->dev_private;
4204 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 4205 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1507e5bd 4206
ab9412ba 4207 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 4208
8c52b5e8 4209 lpt_program_iclkip(crtc);
1507e5bd 4210
0540e488 4211 /* Set transcoder timing. */
275f01b2 4212 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
1507e5bd 4213
937bb610 4214 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 4215}
4216
716c2e55 4217void intel_put_shared_dpll(struct intel_crtc *crtc)
ee7b9f93 4218{
e2b78267 4219 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
ee7b9f93
JB		 4220
4221 if (pll == NULL)
4222 return;
4223
3e369b76 4224 if (!(pll->config.crtc_mask & (1 << crtc->pipe))) {
1e6f2ddc 4225 WARN(1, "bad %s crtc mask\n", pll->name);
ee7b9f93
JB		 4226 return;
4227 }
4228
3e369b76
ACO		 4229 pll->config.crtc_mask &= ~(1 << crtc->pipe);
4230 if (pll->config.crtc_mask == 0) {
f4a091c7
DV		 4231 WARN_ON(pll->on);
4232 WARN_ON(pll->active);
4233 }
4234
6e3c9717 4235 crtc->config->shared_dpll = DPLL_ID_PRIVATE;
ee7b9f93
JB		 4236}
4237
190f68c5
ACO		 4238struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4239 struct intel_crtc_state *crtc_state)
ee7b9f93 4240{
e2b78267 4241 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8bd31e67 4242 struct intel_shared_dpll *pll;
e2b78267 4243 enum intel_dpll_id i;
ee7b9f93 4244
98b6bd99
DV		 4245 if (HAS_PCH_IBX(dev_priv->dev)) {
4246 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
d94ab068 4247 i = (enum intel_dpll_id) crtc->pipe;
e72f9fbf 4248 pll = &dev_priv->shared_dplls[i];
98b6bd99 4249
46edb027
DV		 4250 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4251 crtc->base.base.id, pll->name);
98b6bd99 4252
8bd31e67 4253 WARN_ON(pll->new_config->crtc_mask);
f2a69f44 4254
98b6bd99
DV		 4255 goto found;
4256 }
4257
bcddf610
S		 4258 if (IS_BROXTON(dev_priv->dev)) {
4259 /* PLL is attached to port in bxt */
4260 struct intel_encoder *encoder;
4261 struct intel_digital_port *intel_dig_port;
4262
4263 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4264 if (WARN_ON(!encoder))
4265 return NULL;
4266
4267 intel_dig_port = enc_to_dig_port(&encoder->base);
4268 /* 1:1 mapping between ports and PLLs */
4269 i = (enum intel_dpll_id)intel_dig_port->port;
4270 pll = &dev_priv->shared_dplls[i];
4271 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4272 crtc->base.base.id, pll->name);
4273 WARN_ON(pll->new_config->crtc_mask);
4274
4275 goto found;
4276 }
4277
e72f9fbf
DV		 4278 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4279 pll = &dev_priv->shared_dplls[i];
ee7b9f93
JB		 4280
4281 /* Only want to check enabled timings first */
8bd31e67 4282 if (pll->new_config->crtc_mask == 0)
ee7b9f93
JB		 4283 continue;
4284
190f68c5 4285 if (memcmp(&crtc_state->dpll_hw_state,
8bd31e67
ACO		 4286 &pll->new_config->hw_state,
4287 sizeof(pll->new_config->hw_state)) == 0) {
4288 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
1e6f2ddc 4289 crtc->base.base.id, pll->name,
8bd31e67
ACO		 4290 pll->new_config->crtc_mask,
4291 pll->active);
ee7b9f93
JB		 4292 goto found;
4293 }
4294 }
4295
4296 /* Ok no matching timings, maybe there's a free one? */
e72f9fbf
DV		 4297 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4298 pll = &dev_priv->shared_dplls[i];
8bd31e67 4299 if (pll->new_config->crtc_mask == 0) {
46edb027
DV		 4300 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4301 crtc->base.base.id, pll->name);
ee7b9f93
JB		 4302 goto found;
4303 }
4304 }
4305
4306 return NULL;
4307
4308found:
8bd31e67 4309 if (pll->new_config->crtc_mask == 0)
190f68c5 4310 pll->new_config->hw_state = crtc_state->dpll_hw_state;
f2a69f44 4311
190f68c5 4312 crtc_state->shared_dpll = i;
46edb027
DV		 4313 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4314 pipe_name(crtc->pipe));
ee7b9f93 4315
8bd31e67 4316 pll->new_config->crtc_mask |= 1 << crtc->pipe;
e04c7350 4317
ee7b9f93
JB		 4318 return pll;
4319}
4320
8bd31e67
ACO		 4321/**
4322 * intel_shared_dpll_start_config - start a new PLL staged config
4323 * @dev_priv: DRM device
4324 * @clear_pipes: mask of pipes that will have their PLLs freed
4325 *
4326 * Starts a new PLL staged config, copying the current config but
4327 * releasing the references of pipes specified in clear_pipes.
4328 */
4329static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv,
4330 unsigned clear_pipes)
4331{
4332 struct intel_shared_dpll *pll;
4333 enum intel_dpll_id i;
4334
4335 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4336 pll = &dev_priv->shared_dplls[i];
4337
4338 pll->new_config = kmemdup(&pll->config, sizeof pll->config,
4339 GFP_KERNEL);
4340 if (!pll->new_config)
4341 goto cleanup;
4342
4343 pll->new_config->crtc_mask &= ~clear_pipes;
4344 }
4345
4346 return 0;
4347
4348cleanup:
4349 while (--i >= 0) {
4350 pll = &dev_priv->shared_dplls[i];
f354d733 4351 kfree(pll->new_config);
8bd31e67
ACO		 4352 pll->new_config = NULL;
4353 }
4354
4355 return -ENOMEM;
4356}
4357
4358static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv)
4359{
4360 struct intel_shared_dpll *pll;
4361 enum intel_dpll_id i;
4362
4363 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4364 pll = &dev_priv->shared_dplls[i];
4365
4366 WARN_ON(pll->new_config == &pll->config);
4367
4368 pll->config = *pll->new_config;
4369 kfree(pll->new_config);
4370 pll->new_config = NULL;
4371 }
4372}
4373
4374static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv)
4375{
4376 struct intel_shared_dpll *pll;
4377 enum intel_dpll_id i;
4378
4379 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4380 pll = &dev_priv->shared_dplls[i];
4381
4382 WARN_ON(pll->new_config == &pll->config);
4383
4384 kfree(pll->new_config);
4385 pll->new_config = NULL;
4386 }
4387}
4388
a1520318 4389static void cpt_verify_modeset(struct drm_device *dev, int pipe)
d4270e57
JB		 4390{
4391 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 4392 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 4393 u32 temp;
4394
4395 temp = I915_READ(dslreg);
4396 udelay(500);
4397 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 4398 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 4399 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 4400 }
4401}
4402
a1b2278e
CK		 4403/**
4404 * skl_update_scaler_users - Stages update to crtc's scaler state
4405 * @intel_crtc: crtc
4406 * @crtc_state: crtc_state
4407 * @plane: plane (NULL indicates crtc is requesting update)
4408 * @plane_state: plane's state
4409 * @force_detach: request unconditional detachment of scaler
4410 *
4411 * This function updates scaler state for requested plane or crtc.
4412 * To request scaler usage update for a plane, caller shall pass plane pointer.
4413 * To request scaler usage update for crtc, caller shall pass plane pointer
4414 * as NULL.
4415 *
4416 * Return
4417 * 0 - scaler_usage updated successfully
4418 * error - requested scaling cannot be supported or other error condition
4419 */
4420int
4421skl_update_scaler_users(
4422 struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state,
4423 struct intel_plane *intel_plane, struct intel_plane_state *plane_state,
4424 int force_detach)
4425{
4426 int need_scaling;
4427 int idx;
4428 int src_w, src_h, dst_w, dst_h;
4429 int *scaler_id;
4430 struct drm_framebuffer *fb;
4431 struct intel_crtc_scaler_state *scaler_state;
6156a456 4432 unsigned int rotation;
a1b2278e
CK		 4433
4434 if (!intel_crtc || !crtc_state)
4435 return 0;
4436
4437 scaler_state = &crtc_state->scaler_state;
4438
4439 idx = intel_plane ? drm_plane_index(&intel_plane->base) : SKL_CRTC_INDEX;
4440 fb = intel_plane ? plane_state->base.fb : NULL;
4441
4442 if (intel_plane) {
4443 src_w = drm_rect_width(&plane_state->src) >> 16;
4444 src_h = drm_rect_height(&plane_state->src) >> 16;
4445 dst_w = drm_rect_width(&plane_state->dst);
4446 dst_h = drm_rect_height(&plane_state->dst);
4447 scaler_id = &plane_state->scaler_id;
6156a456 4448 rotation = plane_state->base.rotation;
a1b2278e
CK		 4449 } else {
4450 struct drm_display_mode *adjusted_mode =
4451 &crtc_state->base.adjusted_mode;
4452 src_w = crtc_state->pipe_src_w;
4453 src_h = crtc_state->pipe_src_h;
4454 dst_w = adjusted_mode->hdisplay;
4455 dst_h = adjusted_mode->vdisplay;
4456 scaler_id = &scaler_state->scaler_id;
6156a456 4457 rotation = DRM_ROTATE_0;
a1b2278e 4458 }
6156a456
CK		 4459
4460 need_scaling = intel_rotation_90_or_270(rotation) ?
4461 (src_h != dst_w || src_w != dst_h):
4462 (src_w != dst_w || src_h != dst_h);
a1b2278e
CK		 4463
4464 /*
4465 * if plane is being disabled or scaler is no more required or force detach
4466 * - free scaler binded to this plane/crtc
4467 * - in order to do this, update crtc->scaler_usage
4468 *
4469 * Here scaler state in crtc_state is set free so that
4470 * scaler can be assigned to other user. Actual register
4471 * update to free the scaler is done in plane/panel-fit programming.
4472 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4473 */
4474 if (force_detach || !need_scaling || (intel_plane &&
4475 (!fb || !plane_state->visible))) {
4476 if (*scaler_id >= 0) {
4477 scaler_state->scaler_users &= ~(1 << idx);
4478 scaler_state->scalers[*scaler_id].in_use = 0;
4479
4480 DRM_DEBUG_KMS("Staged freeing scaler id %d.%d from %s:%d "
4481 "crtc_state = %p scaler_users = 0x%x\n",
4482 intel_crtc->pipe, *scaler_id, intel_plane ? "PLANE" : "CRTC",
4483 intel_plane ? intel_plane->base.base.id :
4484 intel_crtc->base.base.id, crtc_state,
4485 scaler_state->scaler_users);
4486 *scaler_id = -1;
4487 }
4488 return 0;
4489 }
4490
4491 /* range checks */
4492 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4493 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4494
4495 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4496 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4497 DRM_DEBUG_KMS("%s:%d scaler_user index %u.%u: src %ux%u dst %ux%u "
4498 "size is out of scaler range\n",
4499 intel_plane ? "PLANE" : "CRTC",
4500 intel_plane ? intel_plane->base.base.id : intel_crtc->base.base.id,
4501 intel_crtc->pipe, idx, src_w, src_h, dst_w, dst_h);
4502 return -EINVAL;
4503 }
4504
4505 /* check colorkey */
4506 if (intel_plane && intel_plane->ckey.flags != I915_SET_COLORKEY_NONE) {
4507 DRM_DEBUG_KMS("PLANE:%d scaling with color key not allowed",
4508 intel_plane->base.base.id);
4509 return -EINVAL;
4510 }
4511
4512 /* Check src format */
4513 if (intel_plane) {
4514 switch (fb->pixel_format) {
4515 case DRM_FORMAT_RGB565:
4516 case DRM_FORMAT_XBGR8888:
4517 case DRM_FORMAT_XRGB8888:
4518 case DRM_FORMAT_ABGR8888:
4519 case DRM_FORMAT_ARGB8888:
4520 case DRM_FORMAT_XRGB2101010:
4521 case DRM_FORMAT_ARGB2101010:
4522 case DRM_FORMAT_XBGR2101010:
4523 case DRM_FORMAT_ABGR2101010:
4524 case DRM_FORMAT_YUYV:
4525 case DRM_FORMAT_YVYU:
4526 case DRM_FORMAT_UYVY:
4527 case DRM_FORMAT_VYUY:
4528 break;
4529 default:
4530 DRM_DEBUG_KMS("PLANE:%d FB:%d unsupported scaling format 0x%x\n",
4531 intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4532 return -EINVAL;
4533 }
4534 }
4535
4536 /* mark this plane as a scaler user in crtc_state */
4537 scaler_state->scaler_users |= (1 << idx);
4538 DRM_DEBUG_KMS("%s:%d staged scaling request for %ux%u->%ux%u "
4539 "crtc_state = %p scaler_users = 0x%x\n",
4540 intel_plane ? "PLANE" : "CRTC",
4541 intel_plane ? intel_plane->base.base.id : intel_crtc->base.base.id,
4542 src_w, src_h, dst_w, dst_h, crtc_state, scaler_state->scaler_users);
4543 return 0;
4544}
4545
4546static void skylake_pfit_update(struct intel_crtc *crtc, int enable)
bd2e244f
JB		 4547{
4548 struct drm_device *dev = crtc->base.dev;
4549 struct drm_i915_private *dev_priv = dev->dev_private;
4550 int pipe = crtc->pipe;
a1b2278e
CK		 4551 struct intel_crtc_scaler_state *scaler_state =
4552 &crtc->config->scaler_state;
4553
4554 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4555
4556 /* To update pfit, first update scaler state */
4557 skl_update_scaler_users(crtc, crtc->config, NULL, NULL, !enable);
4558 intel_atomic_setup_scalers(crtc->base.dev, crtc, crtc->config);
4559 skl_detach_scalers(crtc);
4560 if (!enable)
4561 return;
bd2e244f 4562
6e3c9717 4563 if (crtc->config->pch_pfit.enabled) {
a1b2278e
CK		 4564 int id;
4565
4566 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4567 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4568 return;
4569 }
4570
4571 id = scaler_state->scaler_id;
4572 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4573 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4574 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4575 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4576
4577 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
bd2e244f
JB		 4578 }
4579}
4580
b074cec8
JB		 4581static void ironlake_pfit_enable(struct intel_crtc *crtc)
4582{
4583 struct drm_device *dev = crtc->base.dev;
4584 struct drm_i915_private *dev_priv = dev->dev_private;
4585 int pipe = crtc->pipe;
4586
6e3c9717 4587 if (crtc->config->pch_pfit.enabled) {
b074cec8
JB		 4588 /* Force use of hard-coded filter coefficients
4589 * as some pre-programmed values are broken,
4590 * e.g. x201.
4591 */
4592 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4593 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4594 PF_PIPE_SEL_IVB(pipe));
4595 else
4596 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
6e3c9717
ACO		 4597 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4598 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
d4270e57
JB		 4599 }
4600}
4601
4a3b8769 4602static void intel_enable_sprite_planes(struct drm_crtc *crtc)
bb53d4ae
VS		 4603{
4604 struct drm_device *dev = crtc->dev;
4605 enum pipe pipe = to_intel_crtc(crtc)->pipe;
af2b653b 4606 struct drm_plane *plane;
bb53d4ae
VS		 4607 struct intel_plane *intel_plane;
4608
af2b653b
MR		 4609 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4610 intel_plane = to_intel_plane(plane);
bb53d4ae
VS		 4611 if (intel_plane->pipe == pipe)
4612 intel_plane_restore(&intel_plane->base);
af2b653b 4613 }
bb53d4ae
VS		 4614}
4615
20bc8673 4616void hsw_enable_ips(struct intel_crtc *crtc)
d77e4531 4617{
cea165c3
VS		 4618 struct drm_device *dev = crtc->base.dev;
4619 struct drm_i915_private *dev_priv = dev->dev_private;
d77e4531 4620
6e3c9717 4621 if (!crtc->config->ips_enabled)
d77e4531
PZ		 4622 return;
4623
cea165c3
VS		 4624 /* We can only enable IPS after we enable a plane and wait for a vblank */
4625 intel_wait_for_vblank(dev, crtc->pipe);
4626
d77e4531 4627 assert_plane_enabled(dev_priv, crtc->plane);
cea165c3 4628 if (IS_BROADWELL(dev)) {
2a114cc1
BW		 4629 mutex_lock(&dev_priv->rps.hw_lock);
4630 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4631 mutex_unlock(&dev_priv->rps.hw_lock);
4632 /* Quoting Art Runyan: "its not safe to expect any particular
4633 * value in IPS_CTL bit 31 after enabling IPS through the
e59150dc
JB		 4634 * mailbox." Moreover, the mailbox may return a bogus state,
4635 * so we need to just enable it and continue on.
2a114cc1
BW		 4636 */
4637 } else {
4638 I915_WRITE(IPS_CTL, IPS_ENABLE);
4639 /* The bit only becomes 1 in the next vblank, so this wait here
4640 * is essentially intel_wait_for_vblank. If we don't have this
4641 * and don't wait for vblanks until the end of crtc_enable, then
4642 * the HW state readout code will complain that the expected
4643 * IPS_CTL value is not the one we read. */
4644 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4645 DRM_ERROR("Timed out waiting for IPS enable\n");
4646 }
d77e4531
PZ		 4647}
4648
20bc8673 4649void hsw_disable_ips(struct intel_crtc *crtc)
d77e4531
PZ		 4650{
4651 struct drm_device *dev = crtc->base.dev;
4652 struct drm_i915_private *dev_priv = dev->dev_private;
4653
6e3c9717 4654 if (!crtc->config->ips_enabled)
d77e4531
PZ		 4655 return;
4656
4657 assert_plane_enabled(dev_priv, crtc->plane);
23d0b130 4658 if (IS_BROADWELL(dev)) {
2a114cc1
BW		 4659 mutex_lock(&dev_priv->rps.hw_lock);
4660 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4661 mutex_unlock(&dev_priv->rps.hw_lock);
23d0b130
BW		 4662 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4663 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4664 DRM_ERROR("Timed out waiting for IPS disable\n");
e59150dc 4665 } else {
2a114cc1 4666 I915_WRITE(IPS_CTL, 0);
e59150dc
JB		 4667 POSTING_READ(IPS_CTL);
4668 }
d77e4531
PZ		 4669
4670 /* We need to wait for a vblank before we can disable the plane. */
4671 intel_wait_for_vblank(dev, crtc->pipe);
4672}
4673
4674/** Loads the palette/gamma unit for the CRTC with the prepared values */
4675static void intel_crtc_load_lut(struct drm_crtc *crtc)
4676{
4677 struct drm_device *dev = crtc->dev;
4678 struct drm_i915_private *dev_priv = dev->dev_private;
4679 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4680 enum pipe pipe = intel_crtc->pipe;
4681 int palreg = PALETTE(pipe);
4682 int i;
4683 bool reenable_ips = false;
4684
4685 /* The clocks have to be on to load the palette. */
83d65738 4686 if (!crtc->state->enable || !intel_crtc->active)
d77e4531
PZ		 4687 return;
4688
50360403 4689 if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
409ee761 4690 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
d77e4531
PZ		 4691 assert_dsi_pll_enabled(dev_priv);
4692 else
4693 assert_pll_enabled(dev_priv, pipe);
4694 }
4695
4696 /* use legacy palette for Ironlake */
7a1db49a 4697 if (!HAS_GMCH_DISPLAY(dev))
d77e4531
PZ		 4698 palreg = LGC_PALETTE(pipe);
4699
4700 /* Workaround : Do not read or write the pipe palette/gamma data while
4701 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4702 */
6e3c9717 4703 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
d77e4531
PZ		 4704 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4705 GAMMA_MODE_MODE_SPLIT)) {
4706 hsw_disable_ips(intel_crtc);
4707 reenable_ips = true;
4708 }
4709
4710 for (i = 0; i < 256; i++) {
4711 I915_WRITE(palreg + 4 * i,
4712 (intel_crtc->lut_r[i] << 16) |
4713 (intel_crtc->lut_g[i] << 8) |
4714 intel_crtc->lut_b[i]);
4715 }
4716
4717 if (reenable_ips)
4718 hsw_enable_ips(intel_crtc);
4719}
4720
7cac945f 4721static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
d3eedb1a 4722{
7cac945f 4723 if (intel_crtc->overlay) {
d3eedb1a
VS		 4724 struct drm_device *dev = intel_crtc->base.dev;
4725 struct drm_i915_private *dev_priv = dev->dev_private;
4726
4727 mutex_lock(&dev->struct_mutex);
4728 dev_priv->mm.interruptible = false;
4729 (void) intel_overlay_switch_off(intel_crtc->overlay);
4730 dev_priv->mm.interruptible = true;
4731 mutex_unlock(&dev->struct_mutex);
4732 }
4733
4734 /* Let userspace switch the overlay on again. In most cases userspace
4735 * has to recompute where to put it anyway.
4736 */
4737}
4738
87d4300a
ML		 4739/**
4740 * intel_post_enable_primary - Perform operations after enabling primary plane
4741 * @crtc: the CRTC whose primary plane was just enabled
4742 *
4743 * Performs potentially sleeping operations that must be done after the primary
4744 * plane is enabled, such as updating FBC and IPS. Note that this may be
4745 * called due to an explicit primary plane update, or due to an implicit
4746 * re-enable that is caused when a sprite plane is updated to no longer
4747 * completely hide the primary plane.
4748 */
4749static void
4750intel_post_enable_primary(struct drm_crtc *crtc)
a5c4d7bc
VS		 4751{
4752 struct drm_device *dev = crtc->dev;
87d4300a 4753 struct drm_i915_private *dev_priv = dev->dev_private;
a5c4d7bc
VS		 4754 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4755 int pipe = intel_crtc->pipe;
a5c4d7bc 4756
87d4300a
ML		 4757 /*
4758 * BDW signals flip done immediately if the plane
4759 * is disabled, even if the plane enable is already
4760 * armed to occur at the next vblank :(
4761 */
4762 if (IS_BROADWELL(dev))
4763 intel_wait_for_vblank(dev, pipe);
a5c4d7bc 4764
87d4300a
ML		 4765 /*
4766 * FIXME IPS should be fine as long as one plane is
4767 * enabled, but in practice it seems to have problems
4768 * when going from primary only to sprite only and vice
4769 * versa.
4770 */
a5c4d7bc
VS		 4771 hsw_enable_ips(intel_crtc);
4772
4773 mutex_lock(&dev->struct_mutex);
7ff0ebcc 4774 intel_fbc_update(dev);
a5c4d7bc 4775 mutex_unlock(&dev->struct_mutex);
f99d7069
DV		 4776
4777 /*
87d4300a
ML		 4778 * Gen2 reports pipe underruns whenever all planes are disabled.
4779 * So don't enable underrun reporting before at least some planes
4780 * are enabled.
4781 * FIXME: Need to fix the logic to work when we turn off all planes
4782 * but leave the pipe running.
f99d7069 4783 */
87d4300a
ML		 4784 if (IS_GEN2(dev))
4785 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4786
4787 /* Underruns don't raise interrupts, so check manually. */
4788 if (HAS_GMCH_DISPLAY(dev))
4789 i9xx_check_fifo_underruns(dev_priv);
a5c4d7bc
VS		 4790}
4791
87d4300a
ML		 4792/**
4793 * intel_pre_disable_primary - Perform operations before disabling primary plane
4794 * @crtc: the CRTC whose primary plane is to be disabled
4795 *
4796 * Performs potentially sleeping operations that must be done before the
4797 * primary plane is disabled, such as updating FBC and IPS. Note that this may
4798 * be called due to an explicit primary plane update, or due to an implicit
4799 * disable that is caused when a sprite plane completely hides the primary
4800 * plane.
4801 */
4802static void
4803intel_pre_disable_primary(struct drm_crtc *crtc)
a5c4d7bc
VS		 4804{
4805 struct drm_device *dev = crtc->dev;
4806 struct drm_i915_private *dev_priv = dev->dev_private;
4807 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4808 int pipe = intel_crtc->pipe;
a5c4d7bc 4809
87d4300a
ML		 4810 /*
4811 * Gen2 reports pipe underruns whenever all planes are disabled.
4812 * So diasble underrun reporting before all the planes get disabled.
4813 * FIXME: Need to fix the logic to work when we turn off all planes
4814 * but leave the pipe running.
4815 */
4816 if (IS_GEN2(dev))
4817 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
a5c4d7bc 4818
87d4300a
ML		 4819 /*
4820 * Vblank time updates from the shadow to live plane control register
4821 * are blocked if the memory self-refresh mode is active at that
4822 * moment. So to make sure the plane gets truly disabled, disable
4823 * first the self-refresh mode. The self-refresh enable bit in turn
4824 * will be checked/applied by the HW only at the next frame start
4825 * event which is after the vblank start event, so we need to have a
4826 * wait-for-vblank between disabling the plane and the pipe.
4827 */
4828 if (HAS_GMCH_DISPLAY(dev))
4829 intel_set_memory_cxsr(dev_priv, false);
4830
4831 mutex_lock(&dev->struct_mutex);
e35fef21 4832 if (dev_priv->fbc.crtc == intel_crtc)
7ff0ebcc 4833 intel_fbc_disable(dev);
87d4300a 4834 mutex_unlock(&dev->struct_mutex);
a5c4d7bc 4835
87d4300a
ML		 4836 /*
4837 * FIXME IPS should be fine as long as one plane is
4838 * enabled, but in practice it seems to have problems
4839 * when going from primary only to sprite only and vice
4840 * versa.
4841 */
a5c4d7bc 4842 hsw_disable_ips(intel_crtc);
87d4300a
ML		 4843}
4844
4845static void intel_crtc_enable_planes(struct drm_crtc *crtc)
4846{
87d4300a
ML		 4847 intel_enable_primary_hw_plane(crtc->primary, crtc);
4848 intel_enable_sprite_planes(crtc);
4849 intel_crtc_update_cursor(crtc, true);
87d4300a
ML		 4850
4851 intel_post_enable_primary(crtc);
4852}
4853
4854static void intel_crtc_disable_planes(struct drm_crtc *crtc)
4855{
4856 struct drm_device *dev = crtc->dev;
4857 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4858 struct intel_plane *intel_plane;
4859 int pipe = intel_crtc->pipe;
4860
4861 intel_crtc_wait_for_pending_flips(crtc);
4862
4863 intel_pre_disable_primary(crtc);
a5c4d7bc 4864
7cac945f 4865 intel_crtc_dpms_overlay_disable(intel_crtc);
27321ae8
ML		 4866 for_each_intel_plane(dev, intel_plane) {
4867 if (intel_plane->pipe == pipe) {
4868 struct drm_crtc *from = intel_plane->base.crtc;
4869
4870 intel_plane->disable_plane(&intel_plane->base,
4871 from ?: crtc, true);
4872 }
4873 }
f98551ae 4874
f99d7069
DV		 4875 /*
4876 * FIXME: Once we grow proper nuclear flip support out of this we need
4877 * to compute the mask of flip planes precisely. For the time being
4878 * consider this a flip to a NULL plane.
4879 */
4880 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
a5c4d7bc
VS		 4881}
4882
f67a559d
JB		 4883static void ironlake_crtc_enable(struct drm_crtc *crtc)
4884{
4885 struct drm_device *dev = crtc->dev;
4886 struct drm_i915_private *dev_priv = dev->dev_private;
4887 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 4888 struct intel_encoder *encoder;
f67a559d 4889 int pipe = intel_crtc->pipe;
f67a559d 4890
83d65738 4891 WARN_ON(!crtc->state->enable);
08a48469 4892
f67a559d
JB		 4893 if (intel_crtc->active)
4894 return;
4895
6e3c9717 4896 if (intel_crtc->config->has_pch_encoder)
b14b1055
DV		 4897 intel_prepare_shared_dpll(intel_crtc);
4898
6e3c9717 4899 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 4900 intel_dp_set_m_n(intel_crtc, M1_N1);
29407aab
DV		 4901
4902 intel_set_pipe_timings(intel_crtc);
4903
6e3c9717 4904 if (intel_crtc->config->has_pch_encoder) {
29407aab 4905 intel_cpu_transcoder_set_m_n(intel_crtc,
6e3c9717 4906 &intel_crtc->config->fdi_m_n, NULL);
29407aab
DV		 4907 }
4908
4909 ironlake_set_pipeconf(crtc);
4910
f67a559d 4911 intel_crtc->active = true;
8664281b 4912
a72e4c9f
DV		 4913 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4914 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
8664281b 4915
f6736a1a 4916 for_each_encoder_on_crtc(dev, crtc, encoder)
952735ee
DV		 4917 if (encoder->pre_enable)
4918 encoder->pre_enable(encoder);
f67a559d 4919
6e3c9717 4920 if (intel_crtc->config->has_pch_encoder) {
fff367c7
DV		 4921 /* Note: FDI PLL enabling _must_ be done before we enable the
4922 * cpu pipes, hence this is separate from all the other fdi/pch
4923 * enabling. */
88cefb6c 4924 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 4925 } else {
4926 assert_fdi_tx_disabled(dev_priv, pipe);
4927 assert_fdi_rx_disabled(dev_priv, pipe);
4928 }
f67a559d 4929
b074cec8 4930 ironlake_pfit_enable(intel_crtc);
f67a559d 4931
9c54c0dd
JB		 4932 /*
4933 * On ILK+ LUT must be loaded before the pipe is running but with
4934 * clocks enabled
4935 */
4936 intel_crtc_load_lut(crtc);
4937
f37fcc2a 4938 intel_update_watermarks(crtc);
e1fdc473 4939 intel_enable_pipe(intel_crtc);
f67a559d 4940
6e3c9717 4941 if (intel_crtc->config->has_pch_encoder)
f67a559d 4942 ironlake_pch_enable(crtc);
c98e9dcf 4943
f9b61ff6
DV		 4944 assert_vblank_disabled(crtc);
4945 drm_crtc_vblank_on(crtc);
4946
fa5c73b1
DV		 4947 for_each_encoder_on_crtc(dev, crtc, encoder)
4948 encoder->enable(encoder);
61b77ddd
DV		 4949
4950 if (HAS_PCH_CPT(dev))
a1520318 4951 cpt_verify_modeset(dev, intel_crtc->pipe);
6be4a607
JB		 4952}
4953
42db64ef
PZ		 4954/* IPS only exists on ULT machines and is tied to pipe A. */
4955static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4956{
f5adf94e 4957 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
42db64ef
PZ		 4958}
4959
e4916946
PZ		 4960/*
4961 * This implements the workaround described in the "notes" section of the mode
4962 * set sequence documentation. When going from no pipes or single pipe to
4963 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4964 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4965 */
4966static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4967{
4968 struct drm_device *dev = crtc->base.dev;
4969 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4970
4971 /* We want to get the other_active_crtc only if there's only 1 other
4972 * active crtc. */
d3fcc808 4973 for_each_intel_crtc(dev, crtc_it) {
e4916946
PZ		 4974 if (!crtc_it->active || crtc_it == crtc)
4975 continue;
4976
4977 if (other_active_crtc)
4978 return;
4979
4980 other_active_crtc = crtc_it;
4981 }
4982 if (!other_active_crtc)
4983 return;
4984
4985 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4986 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4987}
4988
4f771f10
PZ		 4989static void haswell_crtc_enable(struct drm_crtc *crtc)
4990{
4991 struct drm_device *dev = crtc->dev;
4992 struct drm_i915_private *dev_priv = dev->dev_private;
4993 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4994 struct intel_encoder *encoder;
4995 int pipe = intel_crtc->pipe;
4f771f10 4996
83d65738 4997 WARN_ON(!crtc->state->enable);
4f771f10
PZ		 4998
4999 if (intel_crtc->active)
5000 return;
5001
df8ad70c
DV		 5002 if (intel_crtc_to_shared_dpll(intel_crtc))
5003 intel_enable_shared_dpll(intel_crtc);
5004
6e3c9717 5005 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 5006 intel_dp_set_m_n(intel_crtc, M1_N1);
229fca97
DV		 5007
5008 intel_set_pipe_timings(intel_crtc);
5009
6e3c9717
ACO		 5010 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
5011 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
5012 intel_crtc->config->pixel_multiplier - 1);
ebb69c95
CT		 5013 }
5014
6e3c9717 5015 if (intel_crtc->config->has_pch_encoder) {
229fca97 5016 intel_cpu_transcoder_set_m_n(intel_crtc,
6e3c9717 5017 &intel_crtc->config->fdi_m_n, NULL);
229fca97
DV		 5018 }
5019
5020 haswell_set_pipeconf(crtc);
5021
5022 intel_set_pipe_csc(crtc);
5023
4f771f10 5024 intel_crtc->active = true;
8664281b 5025
a72e4c9f 5026 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4f771f10
PZ		 5027 for_each_encoder_on_crtc(dev, crtc, encoder)
5028 if (encoder->pre_enable)
5029 encoder->pre_enable(encoder);
5030
6e3c9717 5031 if (intel_crtc->config->has_pch_encoder) {
a72e4c9f
DV		 5032 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5033 true);
4fe9467d
ID		 5034 dev_priv->display.fdi_link_train(crtc);
5035 }
5036
1f544388 5037 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 5038
ff6d9f55 5039 if (INTEL_INFO(dev)->gen == 9)
a1b2278e 5040 skylake_pfit_update(intel_crtc, 1);
ff6d9f55 5041 else if (INTEL_INFO(dev)->gen < 9)
bd2e244f 5042 ironlake_pfit_enable(intel_crtc);
ff6d9f55
JB		 5043 else
5044 MISSING_CASE(INTEL_INFO(dev)->gen);
4f771f10
PZ		 5045
5046 /*
5047 * On ILK+ LUT must be loaded before the pipe is running but with
5048 * clocks enabled
5049 */
5050 intel_crtc_load_lut(crtc);
5051
1f544388 5052 intel_ddi_set_pipe_settings(crtc);
8228c251 5053 intel_ddi_enable_transcoder_func(crtc);
4f771f10 5054
f37fcc2a 5055 intel_update_watermarks(crtc);
e1fdc473 5056 intel_enable_pipe(intel_crtc);
42db64ef 5057
6e3c9717 5058 if (intel_crtc->config->has_pch_encoder)
1507e5bd 5059 lpt_pch_enable(crtc);
4f771f10 5060
6e3c9717 5061 if (intel_crtc->config->dp_encoder_is_mst)
0e32b39c
DA		 5062 intel_ddi_set_vc_payload_alloc(crtc, true);
5063
f9b61ff6
DV		 5064 assert_vblank_disabled(crtc);
5065 drm_crtc_vblank_on(crtc);
5066
8807e55b 5067 for_each_encoder_on_crtc(dev, crtc, encoder) {
4f771f10 5068 encoder->enable(encoder);
8807e55b
JN		 5069 intel_opregion_notify_encoder(encoder, true);
5070 }
4f771f10 5071
e4916946
PZ		 5072 /* If we change the relative order between pipe/planes enabling, we need
5073 * to change the workaround. */
5074 haswell_mode_set_planes_workaround(intel_crtc);
4f771f10
PZ		 5075}
5076
3f8dce3a
DV		 5077static void ironlake_pfit_disable(struct intel_crtc *crtc)
5078{
5079 struct drm_device *dev = crtc->base.dev;
5080 struct drm_i915_private *dev_priv = dev->dev_private;
5081 int pipe = crtc->pipe;
5082
5083 /* To avoid upsetting the power well on haswell only disable the pfit if
5084 * it's in use. The hw state code will make sure we get this right. */
6e3c9717 5085 if (crtc->config->pch_pfit.enabled) {
3f8dce3a
DV		 5086 I915_WRITE(PF_CTL(pipe), 0);
5087 I915_WRITE(PF_WIN_POS(pipe), 0);
5088 I915_WRITE(PF_WIN_SZ(pipe), 0);
5089 }
5090}
5091
6be4a607
JB		 5092static void ironlake_crtc_disable(struct drm_crtc *crtc)
5093{
5094 struct drm_device *dev = crtc->dev;
5095 struct drm_i915_private *dev_priv = dev->dev_private;
5096 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 5097 struct intel_encoder *encoder;
6be4a607 5098 int pipe = intel_crtc->pipe;
5eddb70b 5099 u32 reg, temp;
b52eb4dc 5100
f7abfe8b
CW		 5101 if (!intel_crtc->active)
5102 return;
5103
ea9d758d
DV		 5104 for_each_encoder_on_crtc(dev, crtc, encoder)
5105 encoder->disable(encoder);
5106
f9b61ff6
DV		 5107 drm_crtc_vblank_off(crtc);
5108 assert_vblank_disabled(crtc);
5109
6e3c9717 5110 if (intel_crtc->config->has_pch_encoder)
a72e4c9f 5111 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
d925c59a 5112
575f7ab7 5113 intel_disable_pipe(intel_crtc);
32f9d658 5114
3f8dce3a 5115 ironlake_pfit_disable(intel_crtc);
2c07245f 5116
bf49ec8c
DV		 5117 for_each_encoder_on_crtc(dev, crtc, encoder)
5118 if (encoder->post_disable)
5119 encoder->post_disable(encoder);
2c07245f 5120
6e3c9717 5121 if (intel_crtc->config->has_pch_encoder) {
d925c59a 5122 ironlake_fdi_disable(crtc);
913d8d11 5123
d925c59a 5124 ironlake_disable_pch_transcoder(dev_priv, pipe);
6be4a607 5125
d925c59a
DV		 5126 if (HAS_PCH_CPT(dev)) {
5127 /* disable TRANS_DP_CTL */
5128 reg = TRANS_DP_CTL(pipe);
5129 temp = I915_READ(reg);
5130 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5131 TRANS_DP_PORT_SEL_MASK);
5132 temp |= TRANS_DP_PORT_SEL_NONE;
5133 I915_WRITE(reg, temp);
5134
5135 /* disable DPLL_SEL */
5136 temp = I915_READ(PCH_DPLL_SEL);
11887397 5137 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
d925c59a 5138 I915_WRITE(PCH_DPLL_SEL, temp);
9db4a9c7 5139 }
e3421a18 5140
d925c59a 5141 /* disable PCH DPLL */
e72f9fbf 5142 intel_disable_shared_dpll(intel_crtc);
8db9d77b 5143
d925c59a
DV		 5144 ironlake_fdi_pll_disable(intel_crtc);
5145 }
6b383a7f 5146
f7abfe8b 5147 intel_crtc->active = false;
46ba614c 5148 intel_update_watermarks(crtc);
d1ebd816
BW		 5149
5150 mutex_lock(&dev->struct_mutex);
7ff0ebcc 5151 intel_fbc_update(dev);
d1ebd816 5152 mutex_unlock(&dev->struct_mutex);
6be4a607 5153}
1b3c7a47 5154
4f771f10 5155static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 5156{
4f771f10
PZ		 5157 struct drm_device *dev = crtc->dev;
5158 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 5159 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10 5160 struct intel_encoder *encoder;
6e3c9717 5161 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
ee7b9f93 5162
4f771f10
PZ		 5163 if (!intel_crtc->active)
5164 return;
5165
8807e55b
JN		 5166 for_each_encoder_on_crtc(dev, crtc, encoder) {
5167 intel_opregion_notify_encoder(encoder, false);
4f771f10 5168 encoder->disable(encoder);
8807e55b 5169 }
4f771f10 5170
f9b61ff6
DV		 5171 drm_crtc_vblank_off(crtc);
5172 assert_vblank_disabled(crtc);
5173
6e3c9717 5174 if (intel_crtc->config->has_pch_encoder)
a72e4c9f
DV		 5175 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5176 false);
575f7ab7 5177 intel_disable_pipe(intel_crtc);
4f771f10 5178
6e3c9717 5179 if (intel_crtc->config->dp_encoder_is_mst)
a4bf214f
VS		 5180 intel_ddi_set_vc_payload_alloc(crtc, false);
5181
ad80a810 5182 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 5183
ff6d9f55 5184 if (INTEL_INFO(dev)->gen == 9)
a1b2278e 5185 skylake_pfit_update(intel_crtc, 0);
ff6d9f55 5186 else if (INTEL_INFO(dev)->gen < 9)
bd2e244f 5187 ironlake_pfit_disable(intel_crtc);
ff6d9f55
JB		 5188 else
5189 MISSING_CASE(INTEL_INFO(dev)->gen);
4f771f10 5190
1f544388 5191 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10 5192
6e3c9717 5193 if (intel_crtc->config->has_pch_encoder) {
ab4d966c 5194 lpt_disable_pch_transcoder(dev_priv);
1ad960f2 5195 intel_ddi_fdi_disable(crtc);
83616634 5196 }
4f771f10 5197
97b040aa
ID		 5198 for_each_encoder_on_crtc(dev, crtc, encoder)
5199 if (encoder->post_disable)
5200 encoder->post_disable(encoder);
5201
4f771f10 5202 intel_crtc->active = false;
46ba614c 5203 intel_update_watermarks(crtc);
4f771f10
PZ		 5204
5205 mutex_lock(&dev->struct_mutex);
7ff0ebcc 5206 intel_fbc_update(dev);
4f771f10 5207 mutex_unlock(&dev->struct_mutex);
df8ad70c
DV		 5208
5209 if (intel_crtc_to_shared_dpll(intel_crtc))
5210 intel_disable_shared_dpll(intel_crtc);
4f771f10
PZ		 5211}
5212
ee7b9f93
JB		 5213static void ironlake_crtc_off(struct drm_crtc *crtc)
5214{
5215 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
e72f9fbf 5216 intel_put_shared_dpll(intel_crtc);
ee7b9f93
JB		 5217}
5218
6441ab5f 5219
2dd24552
JB		 5220static void i9xx_pfit_enable(struct intel_crtc *crtc)
5221{
5222 struct drm_device *dev = crtc->base.dev;
5223 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 5224 struct intel_crtc_state *pipe_config = crtc->config;
2dd24552 5225
681a8504 5226 if (!pipe_config->gmch_pfit.control)
2dd24552
JB		 5227 return;
5228
2dd24552 5229 /*
c0b03411
DV		 5230 * The panel fitter should only be adjusted whilst the pipe is disabled,
5231 * according to register description and PRM.
2dd24552 5232 */
c0b03411
DV		 5233 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5234 assert_pipe_disabled(dev_priv, crtc->pipe);
2dd24552 5235
b074cec8
JB		 5236 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5237 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5a80c45c
DV		 5238
5239 /* Border color in case we don't scale up to the full screen. Black by
5240 * default, change to something else for debugging. */
5241 I915_WRITE(BCLRPAT(crtc->pipe), 0);
2dd24552
JB		 5242}
5243
d05410f9
DA		 5244static enum intel_display_power_domain port_to_power_domain(enum port port)
5245{
5246 switch (port) {
5247 case PORT_A:
5248 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
5249 case PORT_B:
5250 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
5251 case PORT_C:
5252 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
5253 case PORT_D:
5254 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
5255 default:
5256 WARN_ON_ONCE(1);
5257 return POWER_DOMAIN_PORT_OTHER;
5258 }
5259}
5260
77d22dca
ID		 5261#define for_each_power_domain(domain, mask) \
5262 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
5263 if ((1 << (domain)) & (mask))
5264
319be8ae
ID		 5265enum intel_display_power_domain
5266intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5267{
5268 struct drm_device *dev = intel_encoder->base.dev;
5269 struct intel_digital_port *intel_dig_port;
5270
5271 switch (intel_encoder->type) {
5272 case INTEL_OUTPUT_UNKNOWN:
5273 /* Only DDI platforms should ever use this output type */
5274 WARN_ON_ONCE(!HAS_DDI(dev));
5275 case INTEL_OUTPUT_DISPLAYPORT:
5276 case INTEL_OUTPUT_HDMI:
5277 case INTEL_OUTPUT_EDP:
5278 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
d05410f9 5279 return port_to_power_domain(intel_dig_port->port);
0e32b39c
DA		 5280 case INTEL_OUTPUT_DP_MST:
5281 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5282 return port_to_power_domain(intel_dig_port->port);
319be8ae
ID		 5283 case INTEL_OUTPUT_ANALOG:
5284 return POWER_DOMAIN_PORT_CRT;
5285 case INTEL_OUTPUT_DSI:
5286 return POWER_DOMAIN_PORT_DSI;
5287 default:
5288 return POWER_DOMAIN_PORT_OTHER;
5289 }
5290}
5291
5292static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
77d22dca 5293{
319be8ae
ID		 5294 struct drm_device *dev = crtc->dev;
5295 struct intel_encoder *intel_encoder;
5296 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5297 enum pipe pipe = intel_crtc->pipe;
77d22dca
ID		 5298 unsigned long mask;
5299 enum transcoder transcoder;
5300
5301 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
5302
5303 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5304 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
6e3c9717
ACO		 5305 if (intel_crtc->config->pch_pfit.enabled ||
5306 intel_crtc->config->pch_pfit.force_thru)
77d22dca
ID		 5307 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5308
319be8ae
ID		 5309 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5310 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5311
77d22dca
ID		 5312 return mask;
5313}
5314
679dacd4 5315static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
77d22dca 5316{
679dacd4 5317 struct drm_device *dev = state->dev;
77d22dca
ID		 5318 struct drm_i915_private *dev_priv = dev->dev_private;
5319 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
5320 struct intel_crtc *crtc;
5321
5322 /*
5323 * First get all needed power domains, then put all unneeded, to avoid
5324 * any unnecessary toggling of the power wells.
5325 */
d3fcc808 5326 for_each_intel_crtc(dev, crtc) {
77d22dca
ID		 5327 enum intel_display_power_domain domain;
5328
83d65738 5329 if (!crtc->base.state->enable)
77d22dca
ID		 5330 continue;
5331
319be8ae 5332 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
77d22dca
ID		 5333
5334 for_each_power_domain(domain, pipe_domains[crtc->pipe])
5335 intel_display_power_get(dev_priv, domain);
5336 }
5337
50f6e502 5338 if (dev_priv->display.modeset_global_resources)
679dacd4 5339 dev_priv->display.modeset_global_resources(state);
50f6e502 5340
d3fcc808 5341 for_each_intel_crtc(dev, crtc) {
77d22dca
ID		 5342 enum intel_display_power_domain domain;
5343
5344 for_each_power_domain(domain, crtc->enabled_power_domains)
5345 intel_display_power_put(dev_priv, domain);
5346
5347 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
5348 }
5349
5350 intel_display_set_init_power(dev_priv, false);
5351}
5352
f8437dd1
VK		 5353void broxton_set_cdclk(struct drm_device *dev, int frequency)
5354{
5355 struct drm_i915_private *dev_priv = dev->dev_private;
5356 uint32_t divider;
5357 uint32_t ratio;
5358 uint32_t current_freq;
5359 int ret;
5360
5361 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5362 switch (frequency) {
5363 case 144000:
5364 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5365 ratio = BXT_DE_PLL_RATIO(60);
5366 break;
5367 case 288000:
5368 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5369 ratio = BXT_DE_PLL_RATIO(60);
5370 break;
5371 case 384000:
5372 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5373 ratio = BXT_DE_PLL_RATIO(60);
5374 break;
5375 case 576000:
5376 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5377 ratio = BXT_DE_PLL_RATIO(60);
5378 break;
5379 case 624000:
5380 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5381 ratio = BXT_DE_PLL_RATIO(65);
5382 break;
5383 case 19200:
5384 /*
5385 * Bypass frequency with DE PLL disabled. Init ratio, divider
5386 * to suppress GCC warning.
5387 */
5388 ratio = 0;
5389 divider = 0;
5390 break;
5391 default:
5392 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5393
5394 return;
5395 }
5396
5397 mutex_lock(&dev_priv->rps.hw_lock);
5398 /* Inform power controller of upcoming frequency change */
5399 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5400 0x80000000);
5401 mutex_unlock(&dev_priv->rps.hw_lock);
5402
5403 if (ret) {
5404 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5405 ret, frequency);
5406 return;
5407 }
5408
5409 current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5410 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5411 current_freq = current_freq * 500 + 1000;
5412
5413 /*
5414 * DE PLL has to be disabled when
5415 * - setting to 19.2MHz (bypass, PLL isn't used)
5416 * - before setting to 624MHz (PLL needs toggling)
5417 * - before setting to any frequency from 624MHz (PLL needs toggling)
5418 */
5419 if (frequency == 19200 || frequency == 624000 ||
5420 current_freq == 624000) {
5421 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5422 /* Timeout 200us */
5423 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5424 1))
5425 DRM_ERROR("timout waiting for DE PLL unlock\n");
5426 }
5427
5428 if (frequency != 19200) {
5429 uint32_t val;
5430
5431 val = I915_READ(BXT_DE_PLL_CTL);
5432 val &= ~BXT_DE_PLL_RATIO_MASK;
5433 val |= ratio;
5434 I915_WRITE(BXT_DE_PLL_CTL, val);
5435
5436 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5437 /* Timeout 200us */
5438 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5439 DRM_ERROR("timeout waiting for DE PLL lock\n");
5440
5441 val = I915_READ(CDCLK_CTL);
5442 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5443 val |= divider;
5444 /*
5445 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5446 * enable otherwise.
5447 */
5448 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5449 if (frequency >= 500000)
5450 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5451
5452 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5453 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5454 val |= (frequency - 1000) / 500;
5455 I915_WRITE(CDCLK_CTL, val);
5456 }
5457
5458 mutex_lock(&dev_priv->rps.hw_lock);
5459 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5460 DIV_ROUND_UP(frequency, 25000));
5461 mutex_unlock(&dev_priv->rps.hw_lock);
5462
5463 if (ret) {
5464 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5465 ret, frequency);
5466 return;
5467 }
5468
5469 dev_priv->cdclk_freq = frequency;
5470}
5471
5472void broxton_init_cdclk(struct drm_device *dev)
5473{
5474 struct drm_i915_private *dev_priv = dev->dev_private;
5475 uint32_t val;
5476
5477 /*
5478 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5479 * or else the reset will hang because there is no PCH to respond.
5480 * Move the handshake programming to initialization sequence.
5481 * Previously was left up to BIOS.
5482 */
5483 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5484 val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5485 I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5486
5487 /* Enable PG1 for cdclk */
5488 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5489
5490 /* check if cd clock is enabled */
5491 if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5492 DRM_DEBUG_KMS("Display already initialized\n");
5493 return;
5494 }
5495
5496 /*
5497 * FIXME:
5498 * - The initial CDCLK needs to be read from VBT.
5499 * Need to make this change after VBT has changes for BXT.
5500 * - check if setting the max (or any) cdclk freq is really necessary
5501 * here, it belongs to modeset time
5502 */
5503 broxton_set_cdclk(dev, 624000);
5504
5505 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
22e02c0b
VS		 5506 POSTING_READ(DBUF_CTL);
5507
f8437dd1
VK		 5508 udelay(10);
5509
5510 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5511 DRM_ERROR("DBuf power enable timeout!\n");
5512}
5513
5514void broxton_uninit_cdclk(struct drm_device *dev)
5515{
5516 struct drm_i915_private *dev_priv = dev->dev_private;
5517
5518 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
22e02c0b
VS		 5519 POSTING_READ(DBUF_CTL);
5520
f8437dd1
VK		 5521 udelay(10);
5522
5523 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5524 DRM_ERROR("DBuf power disable timeout!\n");
5525
5526 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5527 broxton_set_cdclk(dev, 19200);
5528
5529 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5530}
5531
dfcab17e 5532/* returns HPLL frequency in kHz */
f8bf63fd 5533static int valleyview_get_vco(struct drm_i915_private *dev_priv)
30a970c6 5534{
586f49dc 5535 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
30a970c6 5536
586f49dc
JB		 5537 /* Obtain SKU information */
5538 mutex_lock(&dev_priv->dpio_lock);
5539 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
5540 CCK_FUSE_HPLL_FREQ_MASK;
5541 mutex_unlock(&dev_priv->dpio_lock);
30a970c6 5542
dfcab17e 5543 return vco_freq[hpll_freq] * 1000;
30a970c6
JB		 5544}
5545
f8bf63fd
VS		 5546static void vlv_update_cdclk(struct drm_device *dev)
5547{
5548 struct drm_i915_private *dev_priv = dev->dev_private;
5549
164dfd28 5550 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
43dc52c3 5551 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
164dfd28 5552 dev_priv->cdclk_freq);
f8bf63fd
VS		 5553
5554 /*
5555 * Program the gmbus_freq based on the cdclk frequency.
5556 * BSpec erroneously claims we should aim for 4MHz, but
5557 * in fact 1MHz is the correct frequency.
5558 */
164dfd28 5559 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
f8bf63fd
VS		 5560}
5561
30a970c6
JB		 5562/* Adjust CDclk dividers to allow high res or save power if possible */
5563static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5564{
5565 struct drm_i915_private *dev_priv = dev->dev_private;
5566 u32 val, cmd;
5567
164dfd28
VK		 5568 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5569 != dev_priv->cdclk_freq);
d60c4473 5570
dfcab17e 5571 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
30a970c6 5572 cmd = 2;
dfcab17e 5573 else if (cdclk == 266667)
30a970c6
JB		 5574 cmd = 1;
5575 else
5576 cmd = 0;
5577
5578 mutex_lock(&dev_priv->rps.hw_lock);
5579 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5580 val &= ~DSPFREQGUAR_MASK;
5581 val |= (cmd << DSPFREQGUAR_SHIFT);
5582 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5583 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5584 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5585 50)) {
5586 DRM_ERROR("timed out waiting for CDclk change\n");
5587 }
5588 mutex_unlock(&dev_priv->rps.hw_lock);
5589
dfcab17e 5590 if (cdclk == 400000) {
6bcda4f0 5591 u32 divider;
30a970c6 5592
6bcda4f0 5593 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
30a970c6
JB		 5594
5595 mutex_lock(&dev_priv->dpio_lock);
5596 /* adjust cdclk divider */
5597 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
9cf33db5 5598 val &= ~DISPLAY_FREQUENCY_VALUES;
30a970c6
JB		 5599 val |= divider;
5600 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
a877e801
VS		 5601
5602 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5603 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5604 50))
5605 DRM_ERROR("timed out waiting for CDclk change\n");
30a970c6
JB		 5606 mutex_unlock(&dev_priv->dpio_lock);
5607 }
5608
5609 mutex_lock(&dev_priv->dpio_lock);
5610 /* adjust self-refresh exit latency value */
5611 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5612 val &= ~0x7f;
5613
5614 /*
5615 * For high bandwidth configs, we set a higher latency in the bunit
5616 * so that the core display fetch happens in time to avoid underruns.
5617 */
dfcab17e 5618 if (cdclk == 400000)
30a970c6
JB		 5619 val |= 4500 / 250; /* 4.5 usec */
5620 else
5621 val |= 3000 / 250; /* 3.0 usec */
5622 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5623 mutex_unlock(&dev_priv->dpio_lock);
5624
f8bf63fd 5625 vlv_update_cdclk(dev);
30a970c6
JB		 5626}
5627
383c5a6a
VS		 5628static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5629{
5630 struct drm_i915_private *dev_priv = dev->dev_private;
5631 u32 val, cmd;
5632
164dfd28
VK		 5633 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5634 != dev_priv->cdclk_freq);
383c5a6a
VS		 5635
5636 switch (cdclk) {
383c5a6a
VS		 5637 case 333333:
5638 case 320000:
383c5a6a 5639 case 266667:
383c5a6a 5640 case 200000:
383c5a6a
VS		 5641 break;
5642 default:
5f77eeb0 5643 MISSING_CASE(cdclk);
383c5a6a
VS		 5644 return;
5645 }
5646
9d0d3fda
VS		 5647 /*
5648 * Specs are full of misinformation, but testing on actual
5649 * hardware has shown that we just need to write the desired
5650 * CCK divider into the Punit register.
5651 */
5652 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5653
383c5a6a
VS		 5654 mutex_lock(&dev_priv->rps.hw_lock);
5655 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5656 val &= ~DSPFREQGUAR_MASK_CHV;
5657 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5658 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5659 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5660 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5661 50)) {
5662 DRM_ERROR("timed out waiting for CDclk change\n");
5663 }
5664 mutex_unlock(&dev_priv->rps.hw_lock);
5665
5666 vlv_update_cdclk(dev);
5667}
5668
30a970c6
JB		 5669static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5670 int max_pixclk)
5671{
6bcda4f0 5672 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
6cca3195 5673 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
29dc7ef3 5674
30a970c6
JB		 5675 /*
5676 * Really only a few cases to deal with, as only 4 CDclks are supported:
5677 * 200MHz
5678 * 267MHz
29dc7ef3 5679 * 320/333MHz (depends on HPLL freq)
6cca3195
VS		 5680 * 400MHz (VLV only)
5681 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5682 * of the lower bin and adjust if needed.
e37c67a1
VS		 5683 *
5684 * We seem to get an unstable or solid color picture at 200MHz.
5685 * Not sure what's wrong. For now use 200MHz only when all pipes
5686 * are off.
30a970c6 5687 */
6cca3195
VS		 5688 if (!IS_CHERRYVIEW(dev_priv) &&
5689 max_pixclk > freq_320*limit/100)
dfcab17e 5690 return 400000;
6cca3195 5691 else if (max_pixclk > 266667*limit/100)
29dc7ef3 5692 return freq_320;
e37c67a1 5693 else if (max_pixclk > 0)
dfcab17e 5694 return 266667;
e37c67a1
VS		 5695 else
5696 return 200000;
30a970c6
JB		 5697}
5698
f8437dd1
VK		 5699static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5700 int max_pixclk)
5701{
5702 /*
5703 * FIXME:
5704 * - remove the guardband, it's not needed on BXT
5705 * - set 19.2MHz bypass frequency if there are no active pipes
5706 */
5707 if (max_pixclk > 576000*9/10)
5708 return 624000;
5709 else if (max_pixclk > 384000*9/10)
5710 return 576000;
5711 else if (max_pixclk > 288000*9/10)
5712 return 384000;
5713 else if (max_pixclk > 144000*9/10)
5714 return 288000;
5715 else
5716 return 144000;
5717}
5718
a821fc46
ACO		 5719/* Compute the max pixel clock for new configuration. Uses atomic state if
5720 * that's non-NULL, look at current state otherwise. */
5721static int intel_mode_max_pixclk(struct drm_device *dev,
5722 struct drm_atomic_state *state)
30a970c6 5723{
30a970c6 5724 struct intel_crtc *intel_crtc;
304603f4 5725 struct intel_crtc_state *crtc_state;
30a970c6
JB		 5726 int max_pixclk = 0;
5727
d3fcc808 5728 for_each_intel_crtc(dev, intel_crtc) {
a821fc46
ACO		 5729 if (state)
5730 crtc_state =
5731 intel_atomic_get_crtc_state(state, intel_crtc);
5732 else
5733 crtc_state = intel_crtc->config;
304603f4
ACO		 5734 if (IS_ERR(crtc_state))
5735 return PTR_ERR(crtc_state);
5736
5737 if (!crtc_state->base.enable)
5738 continue;
5739
5740 max_pixclk = max(max_pixclk,
5741 crtc_state->base.adjusted_mode.crtc_clock);
30a970c6
JB		 5742 }
5743
5744 return max_pixclk;
5745}
5746
0a9ab303 5747static int valleyview_modeset_global_pipes(struct drm_atomic_state *state)
30a970c6 5748{
304603f4 5749 struct drm_i915_private *dev_priv = to_i915(state->dev);
0a9ab303
ACO		 5750 struct drm_crtc *crtc;
5751 struct drm_crtc_state *crtc_state;
a821fc46 5752 int max_pixclk = intel_mode_max_pixclk(state->dev, state);
0a9ab303 5753 int cdclk, i;
30a970c6 5754
304603f4
ACO		 5755 if (max_pixclk < 0)
5756 return max_pixclk;
30a970c6 5757
f8437dd1
VK		 5758 if (IS_VALLEYVIEW(dev_priv))
5759 cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
5760 else
5761 cdclk = broxton_calc_cdclk(dev_priv, max_pixclk);
5762
5763 if (cdclk == dev_priv->cdclk_freq)
304603f4 5764 return 0;
30a970c6 5765
0a9ab303
ACO		 5766 /* add all active pipes to the state */
5767 for_each_crtc(state->dev, crtc) {
5768 if (!crtc->state->enable)
5769 continue;
5770
5771 crtc_state = drm_atomic_get_crtc_state(state, crtc);
5772 if (IS_ERR(crtc_state))
5773 return PTR_ERR(crtc_state);
5774 }
5775
2f2d7aa1 5776 /* disable/enable all currently active pipes while we change cdclk */
0a9ab303
ACO		 5777 for_each_crtc_in_state(state, crtc, crtc_state, i)
5778 if (crtc_state->enable)
5779 crtc_state->mode_changed = true;
304603f4
ACO		 5780
5781 return 0;
30a970c6
JB		 5782}
5783
1e69cd74
VS		 5784static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5785{
5786 unsigned int credits, default_credits;
5787
5788 if (IS_CHERRYVIEW(dev_priv))
5789 default_credits = PFI_CREDIT(12);
5790 else
5791 default_credits = PFI_CREDIT(8);
5792
164dfd28 5793 if (DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
1e69cd74
VS		 5794 /* CHV suggested value is 31 or 63 */
5795 if (IS_CHERRYVIEW(dev_priv))
5796 credits = PFI_CREDIT_31;
5797 else
5798 credits = PFI_CREDIT(15);
5799 } else {
5800 credits = default_credits;
5801 }
5802
5803 /*
5804 * WA - write default credits before re-programming
5805 * FIXME: should we also set the resend bit here?
5806 */
5807 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5808 default_credits);
5809
5810 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5811 credits | PFI_CREDIT_RESEND);
5812
5813 /*
5814 * FIXME is this guaranteed to clear
5815 * immediately or should we poll for it?
5816 */
5817 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
5818}
5819
a821fc46 5820static void valleyview_modeset_global_resources(struct drm_atomic_state *old_state)
30a970c6 5821{
a821fc46 5822 struct drm_device *dev = old_state->dev;
30a970c6 5823 struct drm_i915_private *dev_priv = dev->dev_private;
a821fc46 5824 int max_pixclk = intel_mode_max_pixclk(dev, NULL);
304603f4
ACO		 5825 int req_cdclk;
5826
a821fc46
ACO		 5827 /* The path in intel_mode_max_pixclk() with a NULL atomic state should
5828 * never fail. */
304603f4
ACO		 5829 if (WARN_ON(max_pixclk < 0))
5830 return;
30a970c6 5831
304603f4 5832 req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
30a970c6 5833
164dfd28 5834 if (req_cdclk != dev_priv->cdclk_freq) {
738c05c0
ID		 5835 /*
5836 * FIXME: We can end up here with all power domains off, yet
5837 * with a CDCLK frequency other than the minimum. To account
5838 * for this take the PIPE-A power domain, which covers the HW
5839 * blocks needed for the following programming. This can be
5840 * removed once it's guaranteed that we get here either with
5841 * the minimum CDCLK set, or the required power domains
5842 * enabled.
5843 */
5844 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
5845
383c5a6a
VS		 5846 if (IS_CHERRYVIEW(dev))
5847 cherryview_set_cdclk(dev, req_cdclk);
5848 else
5849 valleyview_set_cdclk(dev, req_cdclk);
738c05c0 5850
1e69cd74
VS		 5851 vlv_program_pfi_credits(dev_priv);
5852
738c05c0 5853 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
383c5a6a 5854 }
30a970c6
JB		 5855}
5856
89b667f8
JB		 5857static void valleyview_crtc_enable(struct drm_crtc *crtc)
5858{
5859 struct drm_device *dev = crtc->dev;
a72e4c9f 5860 struct drm_i915_private *dev_priv = to_i915(dev);
89b667f8
JB		 5861 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5862 struct intel_encoder *encoder;
5863 int pipe = intel_crtc->pipe;
23538ef1 5864 bool is_dsi;
89b667f8 5865
83d65738 5866 WARN_ON(!crtc->state->enable);
89b667f8
JB		 5867
5868 if (intel_crtc->active)
5869 return;
5870
409ee761 5871 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
8525a235 5872
1ae0d137
VS		 5873 if (!is_dsi) {
5874 if (IS_CHERRYVIEW(dev))
6e3c9717 5875 chv_prepare_pll(intel_crtc, intel_crtc->config);
1ae0d137 5876 else
6e3c9717 5877 vlv_prepare_pll(intel_crtc, intel_crtc->config);
1ae0d137 5878 }
5b18e57c 5879
6e3c9717 5880 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 5881 intel_dp_set_m_n(intel_crtc, M1_N1);
5b18e57c
DV		 5882
5883 intel_set_pipe_timings(intel_crtc);
5884
c14b0485
VS		 5885 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
5886 struct drm_i915_private *dev_priv = dev->dev_private;
5887
5888 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
5889 I915_WRITE(CHV_CANVAS(pipe), 0);
5890 }
5891
5b18e57c
DV		 5892 i9xx_set_pipeconf(intel_crtc);
5893
89b667f8 5894 intel_crtc->active = true;
89b667f8 5895
a72e4c9f 5896 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 5897
89b667f8
JB		 5898 for_each_encoder_on_crtc(dev, crtc, encoder)
5899 if (encoder->pre_pll_enable)
5900 encoder->pre_pll_enable(encoder);
5901
9d556c99
CML		 5902 if (!is_dsi) {
5903 if (IS_CHERRYVIEW(dev))
6e3c9717 5904 chv_enable_pll(intel_crtc, intel_crtc->config);
9d556c99 5905 else
6e3c9717 5906 vlv_enable_pll(intel_crtc, intel_crtc->config);
9d556c99 5907 }
89b667f8
JB		 5908
5909 for_each_encoder_on_crtc(dev, crtc, encoder)
5910 if (encoder->pre_enable)
5911 encoder->pre_enable(encoder);
5912
2dd24552
JB		 5913 i9xx_pfit_enable(intel_crtc);
5914
63cbb074
VS		 5915 intel_crtc_load_lut(crtc);
5916
f37fcc2a 5917 intel_update_watermarks(crtc);
e1fdc473 5918 intel_enable_pipe(intel_crtc);
be6a6f8e 5919
4b3a9526
VS		 5920 assert_vblank_disabled(crtc);
5921 drm_crtc_vblank_on(crtc);
5922
f9b61ff6
DV		 5923 for_each_encoder_on_crtc(dev, crtc, encoder)
5924 encoder->enable(encoder);
89b667f8
JB		 5925}
5926
f13c2ef3
DV		 5927static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
5928{
5929 struct drm_device *dev = crtc->base.dev;
5930 struct drm_i915_private *dev_priv = dev->dev_private;
5931
6e3c9717
ACO		 5932 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
5933 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
f13c2ef3
DV		 5934}
5935
0b8765c6 5936static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 5937{
5938 struct drm_device *dev = crtc->dev;
a72e4c9f 5939 struct drm_i915_private *dev_priv = to_i915(dev);
79e53945 5940 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 5941 struct intel_encoder *encoder;
79e53945 5942 int pipe = intel_crtc->pipe;
79e53945 5943
83d65738 5944 WARN_ON(!crtc->state->enable);
08a48469 5945
f7abfe8b
CW		 5946 if (intel_crtc->active)
5947 return;
5948
f13c2ef3
DV		 5949 i9xx_set_pll_dividers(intel_crtc);
5950
6e3c9717 5951 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 5952 intel_dp_set_m_n(intel_crtc, M1_N1);
5b18e57c
DV		 5953
5954 intel_set_pipe_timings(intel_crtc);
5955
5b18e57c
DV		 5956 i9xx_set_pipeconf(intel_crtc);
5957
f7abfe8b 5958 intel_crtc->active = true;
6b383a7f 5959
4a3436e8 5960 if (!IS_GEN2(dev))
a72e4c9f 5961 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 5962
9d6d9f19
MK		 5963 for_each_encoder_on_crtc(dev, crtc, encoder)
5964 if (encoder->pre_enable)
5965 encoder->pre_enable(encoder);
5966
f6736a1a
DV		 5967 i9xx_enable_pll(intel_crtc);
5968
2dd24552
JB		 5969 i9xx_pfit_enable(intel_crtc);
5970
63cbb074
VS		 5971 intel_crtc_load_lut(crtc);
5972
f37fcc2a 5973 intel_update_watermarks(crtc);
e1fdc473 5974 intel_enable_pipe(intel_crtc);
be6a6f8e 5975
4b3a9526
VS		 5976 assert_vblank_disabled(crtc);
5977 drm_crtc_vblank_on(crtc);
5978
f9b61ff6
DV		 5979 for_each_encoder_on_crtc(dev, crtc, encoder)
5980 encoder->enable(encoder);
0b8765c6 5981}
79e53945 5982
87476d63
DV		 5983static void i9xx_pfit_disable(struct intel_crtc *crtc)
5984{
5985 struct drm_device *dev = crtc->base.dev;
5986 struct drm_i915_private *dev_priv = dev->dev_private;
87476d63 5987
6e3c9717 5988 if (!crtc->config->gmch_pfit.control)
328d8e82 5989 return;
87476d63 5990
328d8e82 5991 assert_pipe_disabled(dev_priv, crtc->pipe);
87476d63 5992
328d8e82
DV		 5993 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5994 I915_READ(PFIT_CONTROL));
5995 I915_WRITE(PFIT_CONTROL, 0);
87476d63
DV		 5996}
5997
0b8765c6
JB		 5998static void i9xx_crtc_disable(struct drm_crtc *crtc)
5999{
6000 struct drm_device *dev = crtc->dev;
6001 struct drm_i915_private *dev_priv = dev->dev_private;
6002 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 6003 struct intel_encoder *encoder;
0b8765c6 6004 int pipe = intel_crtc->pipe;
ef9c3aee 6005
f7abfe8b
CW		 6006 if (!intel_crtc->active)
6007 return;
6008
6304cd91
VS		 6009 /*
6010 * On gen2 planes are double buffered but the pipe isn't, so we must
6011 * wait for planes to fully turn off before disabling the pipe.
564ed191
ID		 6012 * We also need to wait on all gmch platforms because of the
6013 * self-refresh mode constraint explained above.
6304cd91 6014 */
564ed191 6015 intel_wait_for_vblank(dev, pipe);
6304cd91 6016
4b3a9526
VS		 6017 for_each_encoder_on_crtc(dev, crtc, encoder)
6018 encoder->disable(encoder);
6019
f9b61ff6
DV		 6020 drm_crtc_vblank_off(crtc);
6021 assert_vblank_disabled(crtc);
6022
575f7ab7 6023 intel_disable_pipe(intel_crtc);
24a1f16d 6024
87476d63 6025 i9xx_pfit_disable(intel_crtc);
24a1f16d 6026
89b667f8
JB		 6027 for_each_encoder_on_crtc(dev, crtc, encoder)
6028 if (encoder->post_disable)
6029 encoder->post_disable(encoder);
6030
409ee761 6031 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
076ed3b2
CML		 6032 if (IS_CHERRYVIEW(dev))
6033 chv_disable_pll(dev_priv, pipe);
6034 else if (IS_VALLEYVIEW(dev))
6035 vlv_disable_pll(dev_priv, pipe);
6036 else
1c4e0274 6037 i9xx_disable_pll(intel_crtc);
076ed3b2 6038 }
0b8765c6 6039
4a3436e8 6040 if (!IS_GEN2(dev))
a72e4c9f 6041 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4a3436e8 6042
f7abfe8b 6043 intel_crtc->active = false;
46ba614c 6044 intel_update_watermarks(crtc);
f37fcc2a 6045
efa9624e 6046 mutex_lock(&dev->struct_mutex);
7ff0ebcc 6047 intel_fbc_update(dev);
efa9624e 6048 mutex_unlock(&dev->struct_mutex);
0b8765c6
JB		 6049}
6050
ee7b9f93
JB		 6051static void i9xx_crtc_off(struct drm_crtc *crtc)
6052{
6053}
6054
b04c5bd6
BF		 6055/* Master function to enable/disable CRTC and corresponding power wells */
6056void intel_crtc_control(struct drm_crtc *crtc, bool enable)
976f8a20
DV		 6057{
6058 struct drm_device *dev = crtc->dev;
6059 struct drm_i915_private *dev_priv = dev->dev_private;
0e572fe7 6060 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
0e572fe7
DV		 6061 enum intel_display_power_domain domain;
6062 unsigned long domains;
976f8a20 6063
0e572fe7
DV		 6064 if (enable) {
6065 if (!intel_crtc->active) {
e1e9fb84
DV		 6066 domains = get_crtc_power_domains(crtc);
6067 for_each_power_domain(domain, domains)
6068 intel_display_power_get(dev_priv, domain);
6069 intel_crtc->enabled_power_domains = domains;
0e572fe7
DV		 6070
6071 dev_priv->display.crtc_enable(crtc);
ce22dba9 6072 intel_crtc_enable_planes(crtc);
0e572fe7
DV		 6073 }
6074 } else {
6075 if (intel_crtc->active) {
ce22dba9 6076 intel_crtc_disable_planes(crtc);
0e572fe7
DV		 6077 dev_priv->display.crtc_disable(crtc);
6078
e1e9fb84
DV		 6079 domains = intel_crtc->enabled_power_domains;
6080 for_each_power_domain(domain, domains)
6081 intel_display_power_put(dev_priv, domain);
6082 intel_crtc->enabled_power_domains = 0;
0e572fe7
DV		 6083 }
6084 }
b04c5bd6
BF		 6085}
6086
6087/**
6088 * Sets the power management mode of the pipe and plane.
6089 */
6090void intel_crtc_update_dpms(struct drm_crtc *crtc)
6091{
6092 struct drm_device *dev = crtc->dev;
6093 struct intel_encoder *intel_encoder;
6094 bool enable = false;
6095
6096 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
6097 enable |= intel_encoder->connectors_active;
6098
6099 intel_crtc_control(crtc, enable);
0f63cca2
ACO		 6100
6101 crtc->state->active = enable;
976f8a20
DV		 6102}
6103
cdd59983
CW		 6104static void intel_crtc_disable(struct drm_crtc *crtc)
6105{
cdd59983 6106 struct drm_device *dev = crtc->dev;
976f8a20 6107 struct drm_connector *connector;
ee7b9f93 6108 struct drm_i915_private *dev_priv = dev->dev_private;
cdd59983 6109
976f8a20 6110 /* crtc should still be enabled when we disable it. */
83d65738 6111 WARN_ON(!crtc->state->enable);
976f8a20 6112
ce22dba9 6113 intel_crtc_disable_planes(crtc);
976f8a20 6114 dev_priv->display.crtc_disable(crtc);
ee7b9f93
JB		 6115 dev_priv->display.off(crtc);
6116
70a101f8 6117 drm_plane_helper_disable(crtc->primary);
976f8a20
DV		 6118
6119 /* Update computed state. */
6120 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
6121 if (!connector->encoder || !connector->encoder->crtc)
6122 continue;
6123
6124 if (connector->encoder->crtc != crtc)
6125 continue;
6126
6127 connector->dpms = DRM_MODE_DPMS_OFF;
6128 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 6129 }
6130}
6131
ea5b213a 6132void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 6133{
4ef69c7a 6134 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 6135
ea5b213a
CW		 6136 drm_encoder_cleanup(encoder);
6137 kfree(intel_encoder);
7e7d76c3
JB		 6138}
6139
9237329d 6140/* Simple dpms helper for encoders with just one connector, no cloning and only
5ab432ef
DV		 6141 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
6142 * state of the entire output pipe. */
9237329d 6143static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 6144{
5ab432ef
DV		 6145 if (mode == DRM_MODE_DPMS_ON) {
6146 encoder->connectors_active = true;
6147
b2cabb0e 6148 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 6149 } else {
6150 encoder->connectors_active = false;
6151
b2cabb0e 6152 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 6153 }
79e53945
JB		 6154}
6155
0a91ca29
DV		 6156/* Cross check the actual hw state with our own modeset state tracking (and it's
6157 * internal consistency). */
b980514c 6158static void intel_connector_check_state(struct intel_connector *connector)
79e53945 6159{
0a91ca29
DV		 6160 if (connector->get_hw_state(connector)) {
6161 struct intel_encoder *encoder = connector->encoder;
6162 struct drm_crtc *crtc;
6163 bool encoder_enabled;
6164 enum pipe pipe;
6165
6166 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6167 connector->base.base.id,
c23cc417 6168 connector->base.name);
0a91ca29 6169
0e32b39c
DA		 6170 /* there is no real hw state for MST connectors */
6171 if (connector->mst_port)
6172 return;
6173
e2c719b7 6174 I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
0a91ca29 6175 "wrong connector dpms state\n");
e2c719b7 6176 I915_STATE_WARN(connector->base.encoder != &encoder->base,
0a91ca29 6177 "active connector not linked to encoder\n");
0a91ca29 6178
36cd7444 6179 if (encoder) {
e2c719b7 6180 I915_STATE_WARN(!encoder->connectors_active,
36cd7444
DA		 6181 "encoder->connectors_active not set\n");
6182
6183 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
e2c719b7
RC		 6184 I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n");
6185 if (I915_STATE_WARN_ON(!encoder->base.crtc))
36cd7444 6186 return;
0a91ca29 6187
36cd7444 6188 crtc = encoder->base.crtc;
0a91ca29 6189
83d65738
MR		 6190 I915_STATE_WARN(!crtc->state->enable,
6191 "crtc not enabled\n");
e2c719b7
RC		 6192 I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
6193 I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe,
36cd7444
DA		 6194 "encoder active on the wrong pipe\n");
6195 }
0a91ca29 6196 }
79e53945
JB		 6197}
6198
08d9bc92
ACO		 6199int intel_connector_init(struct intel_connector *connector)
6200{
6201 struct drm_connector_state *connector_state;
6202
6203 connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6204 if (!connector_state)
6205 return -ENOMEM;
6206
6207 connector->base.state = connector_state;
6208 return 0;
6209}
6210
6211struct intel_connector *intel_connector_alloc(void)
6212{
6213 struct intel_connector *connector;
6214
6215 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6216 if (!connector)
6217 return NULL;
6218
6219 if (intel_connector_init(connector) < 0) {
6220 kfree(connector);
6221 return NULL;
6222 }
6223
6224 return connector;
6225}
6226
5ab432ef
DV		 6227/* Even simpler default implementation, if there's really no special case to
6228 * consider. */
6229void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 6230{
5ab432ef
DV		 6231 /* All the simple cases only support two dpms states. */
6232 if (mode != DRM_MODE_DPMS_ON)
6233 mode = DRM_MODE_DPMS_OFF;
d4270e57 6234
5ab432ef
DV		 6235 if (mode == connector->dpms)
6236 return;
6237
6238 connector->dpms = mode;
6239
6240 /* Only need to change hw state when actually enabled */
c9976dcf
CW		 6241 if (connector->encoder)
6242 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
0a91ca29 6243
b980514c 6244 intel_modeset_check_state(connector->dev);
79e53945
JB		 6245}
6246
f0947c37
DV		 6247/* Simple connector->get_hw_state implementation for encoders that support only
6248 * one connector and no cloning and hence the encoder state determines the state
6249 * of the connector. */
6250bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 6251{
24929352 6252 enum pipe pipe = 0;
f0947c37 6253 struct intel_encoder *encoder = connector->encoder;
ea5b213a 6254
f0947c37 6255 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 6256}
6257
6d293983 6258static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
d272ddfa 6259{
6d293983
ACO		 6260 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6261 return crtc_state->fdi_lanes;
d272ddfa
VS		 6262
6263 return 0;
6264}
6265
6d293983 6266static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5cec258b 6267 struct intel_crtc_state *pipe_config)
1857e1da 6268{
6d293983
ACO		 6269 struct drm_atomic_state *state = pipe_config->base.state;
6270 struct intel_crtc *other_crtc;
6271 struct intel_crtc_state *other_crtc_state;
6272
1857e1da
DV		 6273 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6274 pipe_name(pipe), pipe_config->fdi_lanes);
6275 if (pipe_config->fdi_lanes > 4) {
6276 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6277 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6278 return -EINVAL;
1857e1da
DV		 6279 }
6280
bafb6553 6281 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
1857e1da
DV		 6282 if (pipe_config->fdi_lanes > 2) {
6283 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6284 pipe_config->fdi_lanes);
6d293983 6285 return -EINVAL;
1857e1da 6286 } else {
6d293983 6287 return 0;
1857e1da
DV		 6288 }
6289 }
6290
6291 if (INTEL_INFO(dev)->num_pipes == 2)
6d293983 6292 return 0;
1857e1da
DV		 6293
6294 /* Ivybridge 3 pipe is really complicated */
6295 switch (pipe) {
6296 case PIPE_A:
6d293983 6297 return 0;
1857e1da 6298 case PIPE_B:
6d293983
ACO		 6299 if (pipe_config->fdi_lanes <= 2)
6300 return 0;
6301
6302 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6303 other_crtc_state =
6304 intel_atomic_get_crtc_state(state, other_crtc);
6305 if (IS_ERR(other_crtc_state))
6306 return PTR_ERR(other_crtc_state);
6307
6308 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
1857e1da
DV		 6309 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6310 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6311 return -EINVAL;
1857e1da 6312 }
6d293983 6313 return 0;
1857e1da 6314 case PIPE_C:
251cc67c
VS		 6315 if (pipe_config->fdi_lanes > 2) {
6316 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6317 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6318 return -EINVAL;
251cc67c 6319 }
6d293983
ACO		 6320
6321 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6322 other_crtc_state =
6323 intel_atomic_get_crtc_state(state, other_crtc);
6324 if (IS_ERR(other_crtc_state))
6325 return PTR_ERR(other_crtc_state);
6326
6327 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
1857e1da 6328 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6d293983 6329 return -EINVAL;
1857e1da 6330 }
6d293983 6331 return 0;
1857e1da
DV		 6332 default:
6333 BUG();
6334 }
6335}
6336
e29c22c0
DV		 6337#define RETRY 1
6338static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5cec258b 6339 struct intel_crtc_state *pipe_config)
877d48d5 6340{
1857e1da 6341 struct drm_device *dev = intel_crtc->base.dev;
2d112de7 6342 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6d293983
ACO		 6343 int lane, link_bw, fdi_dotclock, ret;
6344 bool needs_recompute = false;
877d48d5 6345
e29c22c0 6346retry:
877d48d5
DV		 6347 /* FDI is a binary signal running at ~2.7GHz, encoding
6348 * each output octet as 10 bits. The actual frequency
6349 * is stored as a divider into a 100MHz clock, and the
6350 * mode pixel clock is stored in units of 1KHz.
6351 * Hence the bw of each lane in terms of the mode signal
6352 * is:
6353 */
6354 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6355
241bfc38 6356 fdi_dotclock = adjusted_mode->crtc_clock;
877d48d5 6357
2bd89a07 6358 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
877d48d5
DV		 6359 pipe_config->pipe_bpp);
6360
6361 pipe_config->fdi_lanes = lane;
6362
2bd89a07 6363 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
877d48d5 6364 link_bw, &pipe_config->fdi_m_n);
1857e1da 6365
6d293983
ACO		 6366 ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6367 intel_crtc->pipe, pipe_config);
6368 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
e29c22c0
DV		 6369 pipe_config->pipe_bpp -= 2*3;
6370 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6371 pipe_config->pipe_bpp);
6372 needs_recompute = true;
6373 pipe_config->bw_constrained = true;
6374
6375 goto retry;
6376 }
6377
6378 if (needs_recompute)
6379 return RETRY;
6380
6d293983 6381 return ret;
877d48d5
DV		 6382}
6383
42db64ef 6384static void hsw_compute_ips_config(struct intel_crtc *crtc,
5cec258b 6385 struct intel_crtc_state *pipe_config)
42db64ef 6386{
d330a953 6387 pipe_config->ips_enabled = i915.enable_ips &&
3c4ca58c 6388 hsw_crtc_supports_ips(crtc) &&
b6dfdc9b 6389 pipe_config->pipe_bpp <= 24;
42db64ef
PZ		 6390}
6391
a43f6e0f 6392static int intel_crtc_compute_config(struct intel_crtc *crtc,
5cec258b 6393 struct intel_crtc_state *pipe_config)
79e53945 6394{
a43f6e0f 6395 struct drm_device *dev = crtc->base.dev;
8bd31e67 6396 struct drm_i915_private *dev_priv = dev->dev_private;
2d112de7 6397 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
d03c93d4 6398 int ret;
89749350 6399
ad3a4479 6400 /* FIXME should check pixel clock limits on all platforms */
cf532bb2 6401 if (INTEL_INFO(dev)->gen < 4) {
cf532bb2
VS		 6402 int clock_limit =
6403 dev_priv->display.get_display_clock_speed(dev);
6404
6405 /*
6406 * Enable pixel doubling when the dot clock
6407 * is > 90% of the (display) core speed.
6408 *
b397c96b
VS		 6409 * GDG double wide on either pipe,
6410 * otherwise pipe A only.
cf532bb2 6411 */
b397c96b 6412 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
241bfc38 6413 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
ad3a4479 6414 clock_limit *= 2;
cf532bb2 6415 pipe_config->double_wide = true;
ad3a4479
VS		 6416 }
6417
241bfc38 6418 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
e29c22c0 6419 return -EINVAL;
2c07245f 6420 }
89749350 6421
1d1d0e27
VS		 6422 /*
6423 * Pipe horizontal size must be even in:
6424 * - DVO ganged mode
6425 * - LVDS dual channel mode
6426 * - Double wide pipe
6427 */
a93e255f 6428 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
1d1d0e27
VS		 6429 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6430 pipe_config->pipe_src_w &= ~1;
6431
8693a824
DL		 6432 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6433 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
44f46b42
CW		 6434 */
6435 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6436 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
e29c22c0 6437 return -EINVAL;
44f46b42 6438
f5adf94e 6439 if (HAS_IPS(dev))
a43f6e0f
DV		 6440 hsw_compute_ips_config(crtc, pipe_config);
6441
877d48d5 6442 if (pipe_config->has_pch_encoder)
a43f6e0f 6443 return ironlake_fdi_compute_config(crtc, pipe_config);
877d48d5 6444
d03c93d4
CK		 6445 /* FIXME: remove below call once atomic mode set is place and all crtc
6446 * related checks called from atomic_crtc_check function */
6447 ret = 0;
6448 DRM_DEBUG_KMS("intel_crtc = %p drm_state (pipe_config->base.state) = %p\n",
6449 crtc, pipe_config->base.state);
6450 ret = intel_atomic_setup_scalers(dev, crtc, pipe_config);
6451
6452 return ret;
79e53945
JB		 6453}
6454
1652d19e
VS		 6455static int skylake_get_display_clock_speed(struct drm_device *dev)
6456{
6457 struct drm_i915_private *dev_priv = to_i915(dev);
6458 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6459 uint32_t cdctl = I915_READ(CDCLK_CTL);
6460 uint32_t linkrate;
6461
6462 if (!(lcpll1 & LCPLL_PLL_ENABLE)) {
6463 WARN(1, "LCPLL1 not enabled\n");
6464 return 24000; /* 24MHz is the cd freq with NSSC ref */
6465 }
6466
6467 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6468 return 540000;
6469
6470 linkrate = (I915_READ(DPLL_CTRL1) &
71cd8423 6471 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
1652d19e 6472
71cd8423
DL		 6473 if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6474 linkrate == DPLL_CTRL1_LINK_RATE_1080) {
1652d19e
VS		 6475 /* vco 8640 */
6476 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6477 case CDCLK_FREQ_450_432:
6478 return 432000;
6479 case CDCLK_FREQ_337_308:
6480 return 308570;
6481 case CDCLK_FREQ_675_617:
6482 return 617140;
6483 default:
6484 WARN(1, "Unknown cd freq selection\n");
6485 }
6486 } else {
6487 /* vco 8100 */
6488 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6489 case CDCLK_FREQ_450_432:
6490 return 450000;
6491 case CDCLK_FREQ_337_308:
6492 return 337500;
6493 case CDCLK_FREQ_675_617:
6494 return 675000;
6495 default:
6496 WARN(1, "Unknown cd freq selection\n");
6497 }
6498 }
6499
6500 /* error case, do as if DPLL0 isn't enabled */
6501 return 24000;
6502}
6503
6504static int broadwell_get_display_clock_speed(struct drm_device *dev)
6505{
6506 struct drm_i915_private *dev_priv = dev->dev_private;
6507 uint32_t lcpll = I915_READ(LCPLL_CTL);
6508 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6509
6510 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6511 return 800000;
6512 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6513 return 450000;
6514 else if (freq == LCPLL_CLK_FREQ_450)
6515 return 450000;
6516 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6517 return 540000;
6518 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6519 return 337500;
6520 else
6521 return 675000;
6522}
6523
6524static int haswell_get_display_clock_speed(struct drm_device *dev)
6525{
6526 struct drm_i915_private *dev_priv = dev->dev_private;
6527 uint32_t lcpll = I915_READ(LCPLL_CTL);
6528 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6529
6530 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6531 return 800000;
6532 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6533 return 450000;
6534 else if (freq == LCPLL_CLK_FREQ_450)
6535 return 450000;
6536 else if (IS_HSW_ULT(dev))
6537 return 337500;
6538 else
6539 return 540000;
79e53945
JB		 6540}
6541
25eb05fc
JB		 6542static int valleyview_get_display_clock_speed(struct drm_device *dev)
6543{
d197b7d3 6544 struct drm_i915_private *dev_priv = dev->dev_private;
d197b7d3
VS		 6545 u32 val;
6546 int divider;
6547
6bcda4f0
VS		 6548 if (dev_priv->hpll_freq == 0)
6549 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
6550
d197b7d3
VS		 6551 mutex_lock(&dev_priv->dpio_lock);
6552 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
6553 mutex_unlock(&dev_priv->dpio_lock);
6554
6555 divider = val & DISPLAY_FREQUENCY_VALUES;
6556
7d007f40
VS		 6557 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
6558 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
6559 "cdclk change in progress\n");
6560
6bcda4f0 6561 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
25eb05fc
JB		 6562}
6563
b37a6434
VS		 6564static int ilk_get_display_clock_speed(struct drm_device *dev)
6565{
6566 return 450000;
6567}
6568
e70236a8
JB		 6569static int i945_get_display_clock_speed(struct drm_device *dev)
6570{
6571 return 400000;
6572}
79e53945 6573
e70236a8 6574static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 6575{
e907f170 6576 return 333333;
e70236a8 6577}
79e53945 6578
e70236a8
JB		 6579static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6580{
6581 return 200000;
6582}
79e53945 6583
257a7ffc
DV		 6584static int pnv_get_display_clock_speed(struct drm_device *dev)
6585{
6586 u16 gcfgc = 0;
6587
6588 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6589
6590 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6591 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
e907f170 6592 return 266667;
257a7ffc 6593 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
e907f170 6594 return 333333;
257a7ffc 6595 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
e907f170 6596 return 444444;
257a7ffc
DV		 6597 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6598 return 200000;
6599 default:
6600 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6601 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
e907f170 6602 return 133333;
257a7ffc 6603 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
e907f170 6604 return 166667;
257a7ffc
DV		 6605 }
6606}
6607
e70236a8
JB		 6608static int i915gm_get_display_clock_speed(struct drm_device *dev)
6609{
6610 u16 gcfgc = 0;
79e53945 6611
e70236a8
JB		 6612 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6613
6614 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
e907f170 6615 return 133333;
e70236a8
JB		 6616 else {
6617 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6618 case GC_DISPLAY_CLOCK_333_MHZ:
e907f170 6619 return 333333;
e70236a8
JB		 6620 default:
6621 case GC_DISPLAY_CLOCK_190_200_MHZ:
6622 return 190000;
79e53945 6623 }
e70236a8
JB		 6624 }
6625}
6626
6627static int i865_get_display_clock_speed(struct drm_device *dev)
6628{
e907f170 6629 return 266667;
e70236a8
JB		 6630}
6631
6632static int i855_get_display_clock_speed(struct drm_device *dev)
6633{
6634 u16 hpllcc = 0;
6635 /* Assume that the hardware is in the high speed state. This
6636 * should be the default.
6637 */
6638 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6639 case GC_CLOCK_133_200:
6640 case GC_CLOCK_100_200:
6641 return 200000;
6642 case GC_CLOCK_166_250:
6643 return 250000;
6644 case GC_CLOCK_100_133:
e907f170 6645 return 133333;
e70236a8 6646 }
79e53945 6647
e70236a8
JB		 6648 /* Shouldn't happen */
6649 return 0;
6650}
79e53945 6651
e70236a8
JB		 6652static int i830_get_display_clock_speed(struct drm_device *dev)
6653{
e907f170 6654 return 133333;
79e53945
JB		 6655}
6656
2c07245f 6657static void
a65851af 6658intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
2c07245f 6659{
a65851af
VS		 6660 while (*num > DATA_LINK_M_N_MASK ||
6661 *den > DATA_LINK_M_N_MASK) {
2c07245f
ZW		 6662 *num >>= 1;
6663 *den >>= 1;
6664 }
6665}
6666
a65851af
VS		 6667static void compute_m_n(unsigned int m, unsigned int n,
6668 uint32_t *ret_m, uint32_t *ret_n)
6669{
6670 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
6671 *ret_m = div_u64((uint64_t) m * *ret_n, n);
6672 intel_reduce_m_n_ratio(ret_m, ret_n);
6673}
6674
e69d0bc1
DV		 6675void
6676intel_link_compute_m_n(int bits_per_pixel, int nlanes,
6677 int pixel_clock, int link_clock,
6678 struct intel_link_m_n *m_n)
2c07245f 6679{
e69d0bc1 6680 m_n->tu = 64;
a65851af
VS		 6681
6682 compute_m_n(bits_per_pixel * pixel_clock,
6683 link_clock * nlanes * 8,
6684 &m_n->gmch_m, &m_n->gmch_n);
6685
6686 compute_m_n(pixel_clock, link_clock,
6687 &m_n->link_m, &m_n->link_n);
2c07245f
ZW		 6688}
6689
a7615030
CW		 6690static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
6691{
d330a953
JN		 6692 if (i915.panel_use_ssc >= 0)
6693 return i915.panel_use_ssc != 0;
41aa3448 6694 return dev_priv->vbt.lvds_use_ssc
435793df 6695 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 6696}
6697
a93e255f
ACO		 6698static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
6699 int num_connectors)
c65d77d8 6700{
a93e255f 6701 struct drm_device *dev = crtc_state->base.crtc->dev;
c65d77d8
JB		 6702 struct drm_i915_private *dev_priv = dev->dev_private;
6703 int refclk;
6704
a93e255f
ACO		 6705 WARN_ON(!crtc_state->base.state);
6706
5ab7b0b7 6707 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
9a0ea498 6708 refclk = 100000;
a93e255f 6709 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
c65d77d8 6710 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
e91e941b
VS		 6711 refclk = dev_priv->vbt.lvds_ssc_freq;
6712 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
c65d77d8
JB		 6713 } else if (!IS_GEN2(dev)) {
6714 refclk = 96000;
6715 } else {
6716 refclk = 48000;
6717 }
6718
6719 return refclk;
6720}
6721
7429e9d4 6722static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
c65d77d8 6723{
7df00d7a 6724 return (1 << dpll->n) << 16 | dpll->m2;
7429e9d4 6725}
f47709a9 6726
7429e9d4
DV		 6727static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
6728{
6729 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
c65d77d8
JB		 6730}
6731
f47709a9 6732static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
190f68c5 6733 struct intel_crtc_state *crtc_state,
a7516a05
JB		 6734 intel_clock_t *reduced_clock)
6735{
f47709a9 6736 struct drm_device *dev = crtc->base.dev;
a7516a05
JB		 6737 u32 fp, fp2 = 0;
6738
6739 if (IS_PINEVIEW(dev)) {
190f68c5 6740 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
a7516a05 6741 if (reduced_clock)
7429e9d4 6742 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 6743 } else {
190f68c5 6744 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
a7516a05 6745 if (reduced_clock)
7429e9d4 6746 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB		 6747 }
6748
190f68c5 6749 crtc_state->dpll_hw_state.fp0 = fp;
a7516a05 6750
f47709a9 6751 crtc->lowfreq_avail = false;
a93e255f 6752 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
ab585dea 6753 reduced_clock) {
190f68c5 6754 crtc_state->dpll_hw_state.fp1 = fp2;
f47709a9 6755 crtc->lowfreq_avail = true;
a7516a05 6756 } else {
190f68c5 6757 crtc_state->dpll_hw_state.fp1 = fp;
a7516a05
JB		 6758 }
6759}
6760
5e69f97f
CML		 6761static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
6762 pipe)
89b667f8
JB		 6763{
6764 u32 reg_val;
6765
6766 /*
6767 * PLLB opamp always calibrates to max value of 0x3f, force enable it
6768 * and set it to a reasonable value instead.
6769 */
ab3c759a 6770 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
89b667f8
JB		 6771 reg_val &= 0xffffff00;
6772 reg_val |= 0x00000030;
ab3c759a 6773 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
89b667f8 6774
ab3c759a 6775 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
89b667f8
JB		 6776 reg_val &= 0x8cffffff;
6777 reg_val = 0x8c000000;
ab3c759a 6778 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
89b667f8 6779
ab3c759a 6780 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
89b667f8 6781 reg_val &= 0xffffff00;
ab3c759a 6782 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
89b667f8 6783
ab3c759a 6784 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
89b667f8
JB		 6785 reg_val &= 0x00ffffff;
6786 reg_val |= 0xb0000000;
ab3c759a 6787 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
89b667f8
JB		 6788}
6789
b551842d
DV		 6790static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
6791 struct intel_link_m_n *m_n)
6792{
6793 struct drm_device *dev = crtc->base.dev;
6794 struct drm_i915_private *dev_priv = dev->dev_private;
6795 int pipe = crtc->pipe;
6796
e3b95f1e
DV		 6797 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6798 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
6799 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
6800 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
b551842d
DV		 6801}
6802
6803static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
f769cd24
VK		 6804 struct intel_link_m_n *m_n,
6805 struct intel_link_m_n *m2_n2)
b551842d
DV		 6806{
6807 struct drm_device *dev = crtc->base.dev;
6808 struct drm_i915_private *dev_priv = dev->dev_private;
6809 int pipe = crtc->pipe;
6e3c9717 6810 enum transcoder transcoder = crtc->config->cpu_transcoder;
b551842d
DV		 6811
6812 if (INTEL_INFO(dev)->gen >= 5) {
6813 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
6814 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
6815 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
6816 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
f769cd24
VK		 6817 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
6818 * for gen < 8) and if DRRS is supported (to make sure the
6819 * registers are not unnecessarily accessed).
6820 */
44395bfe 6821 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
6e3c9717 6822 crtc->config->has_drrs) {
f769cd24
VK		 6823 I915_WRITE(PIPE_DATA_M2(transcoder),
6824 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
6825 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
6826 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
6827 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
6828 }
b551842d 6829 } else {
e3b95f1e
DV		 6830 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6831 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
6832 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
6833 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
b551842d
DV		 6834 }
6835}
6836
fe3cd48d 6837void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
03afc4a2 6838{
fe3cd48d
R		 6839 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
6840
6841 if (m_n == M1_N1) {
6842 dp_m_n = &crtc->config->dp_m_n;
6843 dp_m2_n2 = &crtc->config->dp_m2_n2;
6844 } else if (m_n == M2_N2) {
6845
6846 /*
6847 * M2_N2 registers are not supported. Hence m2_n2 divider value
6848 * needs to be programmed into M1_N1.
6849 */
6850 dp_m_n = &crtc->config->dp_m2_n2;
6851 } else {
6852 DRM_ERROR("Unsupported divider value\n");
6853 return;
6854 }
6855
6e3c9717
ACO		 6856 if (crtc->config->has_pch_encoder)
6857 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
03afc4a2 6858 else
fe3cd48d 6859 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
03afc4a2
DV		 6860}
6861
d288f65f 6862static void vlv_update_pll(struct intel_crtc *crtc,
5cec258b 6863 struct intel_crtc_state *pipe_config)
bdd4b6a6
DV		 6864{
6865 u32 dpll, dpll_md;
6866
6867 /*
6868 * Enable DPIO clock input. We should never disable the reference
6869 * clock for pipe B, since VGA hotplug / manual detection depends
6870 * on it.
6871 */
6872 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
6873 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
6874 /* We should never disable this, set it here for state tracking */
6875 if (crtc->pipe == PIPE_B)
6876 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6877 dpll |= DPLL_VCO_ENABLE;
d288f65f 6878 pipe_config->dpll_hw_state.dpll = dpll;
bdd4b6a6 6879
d288f65f 6880 dpll_md = (pipe_config->pixel_multiplier - 1)
bdd4b6a6 6881 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
d288f65f 6882 pipe_config->dpll_hw_state.dpll_md = dpll_md;
bdd4b6a6
DV		 6883}
6884
d288f65f 6885static void vlv_prepare_pll(struct intel_crtc *crtc,
5cec258b 6886 const struct intel_crtc_state *pipe_config)
a0c4da24 6887{
f47709a9 6888 struct drm_device *dev = crtc->base.dev;
a0c4da24 6889 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 6890 int pipe = crtc->pipe;
bdd4b6a6 6891 u32 mdiv;
a0c4da24 6892 u32 bestn, bestm1, bestm2, bestp1, bestp2;
bdd4b6a6 6893 u32 coreclk, reg_val;
a0c4da24 6894
09153000
DV		 6895 mutex_lock(&dev_priv->dpio_lock);
6896
d288f65f
VS		 6897 bestn = pipe_config->dpll.n;
6898 bestm1 = pipe_config->dpll.m1;
6899 bestm2 = pipe_config->dpll.m2;
6900 bestp1 = pipe_config->dpll.p1;
6901 bestp2 = pipe_config->dpll.p2;
a0c4da24 6902
89b667f8
JB		 6903 /* See eDP HDMI DPIO driver vbios notes doc */
6904
6905 /* PLL B needs special handling */
bdd4b6a6 6906 if (pipe == PIPE_B)
5e69f97f 6907 vlv_pllb_recal_opamp(dev_priv, pipe);
89b667f8
JB		 6908
6909 /* Set up Tx target for periodic Rcomp update */
ab3c759a 6910 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
89b667f8
JB		 6911
6912 /* Disable target IRef on PLL */
ab3c759a 6913 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
89b667f8 6914 reg_val &= 0x00ffffff;
ab3c759a 6915 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
89b667f8
JB		 6916
6917 /* Disable fast lock */
ab3c759a 6918 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
89b667f8
JB		 6919
6920 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 6921 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
6922 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
6923 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 6924 mdiv |= (1 << DPIO_K_SHIFT);
7df5080b
JB		 6925
6926 /*
6927 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
6928 * but we don't support that).
6929 * Note: don't use the DAC post divider as it seems unstable.
6930 */
6931 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
ab3c759a 6932 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
a0c4da24 6933
a0c4da24 6934 mdiv |= DPIO_ENABLE_CALIBRATION;
ab3c759a 6935 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
a0c4da24 6936
89b667f8 6937 /* Set HBR and RBR LPF coefficients */
d288f65f 6938 if (pipe_config->port_clock == 162000 ||
409ee761
ACO		 6939 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
6940 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
ab3c759a 6941 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
885b0120 6942 0x009f0003);
89b667f8 6943 else
ab3c759a 6944 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
89b667f8
JB		 6945 0x00d0000f);
6946
681a8504 6947 if (pipe_config->has_dp_encoder) {
89b667f8 6948 /* Use SSC source */
bdd4b6a6 6949 if (pipe == PIPE_A)
ab3c759a 6950 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 6951 0x0df40000);
6952 else
ab3c759a 6953 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 6954 0x0df70000);
6955 } else { /* HDMI or VGA */
6956 /* Use bend source */
bdd4b6a6 6957 if (pipe == PIPE_A)
ab3c759a 6958 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 6959 0x0df70000);
6960 else
ab3c759a 6961 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 6962 0x0df40000);
6963 }
a0c4da24 6964
ab3c759a 6965 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
89b667f8 6966 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
409ee761
ACO		 6967 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
6968 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
89b667f8 6969 coreclk |= 0x01000000;
ab3c759a 6970 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
a0c4da24 6971
ab3c759a 6972 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
09153000 6973 mutex_unlock(&dev_priv->dpio_lock);
a0c4da24
JB		 6974}
6975
d288f65f 6976static void chv_update_pll(struct intel_crtc *crtc,
5cec258b 6977 struct intel_crtc_state *pipe_config)
1ae0d137 6978{
d288f65f 6979 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
1ae0d137
VS		 6980 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
6981 DPLL_VCO_ENABLE;
6982 if (crtc->pipe != PIPE_A)
d288f65f 6983 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
1ae0d137 6984
d288f65f
VS		 6985 pipe_config->dpll_hw_state.dpll_md =
6986 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
1ae0d137
VS		 6987}
6988
d288f65f 6989static void chv_prepare_pll(struct intel_crtc *crtc,
5cec258b 6990 const struct intel_crtc_state *pipe_config)
9d556c99
CML		 6991{
6992 struct drm_device *dev = crtc->base.dev;
6993 struct drm_i915_private *dev_priv = dev->dev_private;
6994 int pipe = crtc->pipe;
6995 int dpll_reg = DPLL(crtc->pipe);
6996 enum dpio_channel port = vlv_pipe_to_channel(pipe);
9cbe40c1 6997 u32 loopfilter, tribuf_calcntr;
9d556c99 6998 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
a945ce7e 6999 u32 dpio_val;
9cbe40c1 7000 int vco;
9d556c99 7001
d288f65f
VS		 7002 bestn = pipe_config->dpll.n;
7003 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7004 bestm1 = pipe_config->dpll.m1;
7005 bestm2 = pipe_config->dpll.m2 >> 22;
7006 bestp1 = pipe_config->dpll.p1;
7007 bestp2 = pipe_config->dpll.p2;
9cbe40c1 7008 vco = pipe_config->dpll.vco;
a945ce7e 7009 dpio_val = 0;
9cbe40c1 7010 loopfilter = 0;
9d556c99
CML		 7011
7012 /*
7013 * Enable Refclk and SSC
7014 */
a11b0703 7015 I915_WRITE(dpll_reg,
d288f65f 7016 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
a11b0703
VS		 7017
7018 mutex_lock(&dev_priv->dpio_lock);
9d556c99 7019
9d556c99
CML		 7020 /* p1 and p2 divider */
7021 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7022 5 << DPIO_CHV_S1_DIV_SHIFT |
7023 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7024 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7025 1 << DPIO_CHV_K_DIV_SHIFT);
7026
7027 /* Feedback post-divider - m2 */
7028 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7029
7030 /* Feedback refclk divider - n and m1 */
7031 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7032 DPIO_CHV_M1_DIV_BY_2 |
7033 1 << DPIO_CHV_N_DIV_SHIFT);
7034
7035 /* M2 fraction division */
a945ce7e
VP		 7036 if (bestm2_frac)
7037 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
9d556c99
CML		 7038
7039 /* M2 fraction division enable */
a945ce7e
VP		 7040 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7041 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7042 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7043 if (bestm2_frac)
7044 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7045 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
9d556c99 7046
de3a0fde
VP		 7047 /* Program digital lock detect threshold */
7048 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7049 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7050 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7051 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7052 if (!bestm2_frac)
7053 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7054 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7055
9d556c99 7056 /* Loop filter */
9cbe40c1
VP		 7057 if (vco == 5400000) {
7058 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7059 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7060 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7061 tribuf_calcntr = 0x9;
7062 } else if (vco <= 6200000) {
7063 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7064 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7065 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7066 tribuf_calcntr = 0x9;
7067 } else if (vco <= 6480000) {
7068 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7069 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7070 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7071 tribuf_calcntr = 0x8;
7072 } else {
7073 /* Not supported. Apply the same limits as in the max case */
7074 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7075 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7076 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7077 tribuf_calcntr = 0;
7078 }
9d556c99
CML		 7079 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7080
968040b2 7081 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
9cbe40c1
VP		 7082 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7083 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7084 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7085
9d556c99
CML		 7086 /* AFC Recal */
7087 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7088 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7089 DPIO_AFC_RECAL);
7090
7091 mutex_unlock(&dev_priv->dpio_lock);
7092}
7093
d288f65f
VS		 7094/**
7095 * vlv_force_pll_on - forcibly enable just the PLL
7096 * @dev_priv: i915 private structure
7097 * @pipe: pipe PLL to enable
7098 * @dpll: PLL configuration
7099 *
7100 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7101 * in cases where we need the PLL enabled even when @pipe is not going to
7102 * be enabled.
7103 */
7104void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7105 const struct dpll *dpll)
7106{
7107 struct intel_crtc *crtc =
7108 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
5cec258b 7109 struct intel_crtc_state pipe_config = {
a93e255f 7110 .base.crtc = &crtc->base,
d288f65f
VS		 7111 .pixel_multiplier = 1,
7112 .dpll = *dpll,
7113 };
7114
7115 if (IS_CHERRYVIEW(dev)) {
7116 chv_update_pll(crtc, &pipe_config);
7117 chv_prepare_pll(crtc, &pipe_config);
7118 chv_enable_pll(crtc, &pipe_config);
7119 } else {
7120 vlv_update_pll(crtc, &pipe_config);
7121 vlv_prepare_pll(crtc, &pipe_config);
7122 vlv_enable_pll(crtc, &pipe_config);
7123 }
7124}
7125
7126/**
7127 * vlv_force_pll_off - forcibly disable just the PLL
7128 * @dev_priv: i915 private structure
7129 * @pipe: pipe PLL to disable
7130 *
7131 * Disable the PLL for @pipe. To be used in cases where we need
7132 * the PLL enabled even when @pipe is not going to be enabled.
7133 */
7134void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7135{
7136 if (IS_CHERRYVIEW(dev))
7137 chv_disable_pll(to_i915(dev), pipe);
7138 else
7139 vlv_disable_pll(to_i915(dev), pipe);
7140}
7141
f47709a9 7142static void i9xx_update_pll(struct intel_crtc *crtc,
190f68c5 7143 struct intel_crtc_state *crtc_state,
f47709a9 7144 intel_clock_t *reduced_clock,
eb1cbe48
DV		 7145 int num_connectors)
7146{
f47709a9 7147 struct drm_device *dev = crtc->base.dev;
eb1cbe48 7148 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48
DV		 7149 u32 dpll;
7150 bool is_sdvo;
190f68c5 7151 struct dpll *clock = &crtc_state->dpll;
eb1cbe48 7152
190f68c5 7153 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
2a8f64ca 7154
a93e255f
ACO		 7155 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7156 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 7157
7158 dpll = DPLL_VGA_MODE_DIS;
7159
a93e255f 7160 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 7161 dpll |= DPLLB_MODE_LVDS;
7162 else
7163 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 7164
ef1b460d 7165 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
190f68c5 7166 dpll |= (crtc_state->pixel_multiplier - 1)
198a037f 7167 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 7168 }
198a037f
DV		 7169
7170 if (is_sdvo)
4a33e48d 7171 dpll |= DPLL_SDVO_HIGH_SPEED;
198a037f 7172
190f68c5 7173 if (crtc_state->has_dp_encoder)
4a33e48d 7174 dpll |= DPLL_SDVO_HIGH_SPEED;
eb1cbe48
DV		 7175
7176 /* compute bitmask from p1 value */
7177 if (IS_PINEVIEW(dev))
7178 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7179 else {
7180 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7181 if (IS_G4X(dev) && reduced_clock)
7182 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7183 }
7184 switch (clock->p2) {
7185 case 5:
7186 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7187 break;
7188 case 7:
7189 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7190 break;
7191 case 10:
7192 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7193 break;
7194 case 14:
7195 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7196 break;
7197 }
7198 if (INTEL_INFO(dev)->gen >= 4)
7199 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7200
190f68c5 7201 if (crtc_state->sdvo_tv_clock)
eb1cbe48 7202 dpll |= PLL_REF_INPUT_TVCLKINBC;
a93e255f 7203 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 7204 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7205 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7206 else
7207 dpll |= PLL_REF_INPUT_DREFCLK;
7208
7209 dpll |= DPLL_VCO_ENABLE;
190f68c5 7210 crtc_state->dpll_hw_state.dpll = dpll;
8bcc2795 7211
eb1cbe48 7212 if (INTEL_INFO(dev)->gen >= 4) {
190f68c5 7213 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
ef1b460d 7214 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
190f68c5 7215 crtc_state->dpll_hw_state.dpll_md = dpll_md;
eb1cbe48
DV		 7216 }
7217}
7218
f47709a9 7219static void i8xx_update_pll(struct intel_crtc *crtc,
190f68c5 7220 struct intel_crtc_state *crtc_state,
f47709a9 7221 intel_clock_t *reduced_clock,
eb1cbe48
DV		 7222 int num_connectors)
7223{
f47709a9 7224 struct drm_device *dev = crtc->base.dev;
eb1cbe48 7225 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48 7226 u32 dpll;
190f68c5 7227 struct dpll *clock = &crtc_state->dpll;
eb1cbe48 7228
190f68c5 7229 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
2a8f64ca 7230
eb1cbe48
DV		 7231 dpll = DPLL_VGA_MODE_DIS;
7232
a93e255f 7233 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 7234 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7235 } else {
7236 if (clock->p1 == 2)
7237 dpll |= PLL_P1_DIVIDE_BY_TWO;
7238 else
7239 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7240 if (clock->p2 == 4)
7241 dpll |= PLL_P2_DIVIDE_BY_4;
7242 }
7243
a93e255f 7244 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
4a33e48d
DV		 7245 dpll |= DPLL_DVO_2X_MODE;
7246
a93e255f 7247 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 7248 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7249 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7250 else
7251 dpll |= PLL_REF_INPUT_DREFCLK;
7252
7253 dpll |= DPLL_VCO_ENABLE;
190f68c5 7254 crtc_state->dpll_hw_state.dpll = dpll;
eb1cbe48
DV		 7255}
7256
8a654f3b 7257static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
b0e77b9c
PZ		 7258{
7259 struct drm_device *dev = intel_crtc->base.dev;
7260 struct drm_i915_private *dev_priv = dev->dev_private;
7261 enum pipe pipe = intel_crtc->pipe;
6e3c9717 7262 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8a654f3b 7263 struct drm_display_mode *adjusted_mode =
6e3c9717 7264 &intel_crtc->config->base.adjusted_mode;
1caea6e9
VS		 7265 uint32_t crtc_vtotal, crtc_vblank_end;
7266 int vsyncshift = 0;
4d8a62ea
DV		 7267
7268 /* We need to be careful not to changed the adjusted mode, for otherwise
7269 * the hw state checker will get angry at the mismatch. */
7270 crtc_vtotal = adjusted_mode->crtc_vtotal;
7271 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
b0e77b9c 7272
609aeaca 7273 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
b0e77b9c 7274 /* the chip adds 2 halflines automatically */
4d8a62ea
DV		 7275 crtc_vtotal -= 1;
7276 crtc_vblank_end -= 1;
609aeaca 7277
409ee761 7278 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
609aeaca
VS		 7279 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7280 else
7281 vsyncshift = adjusted_mode->crtc_hsync_start -
7282 adjusted_mode->crtc_htotal / 2;
1caea6e9
VS		 7283 if (vsyncshift < 0)
7284 vsyncshift += adjusted_mode->crtc_htotal;
b0e77b9c
PZ		 7285 }
7286
7287 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 7288 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 7289
fe2b8f9d 7290 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 7291 (adjusted_mode->crtc_hdisplay - 1) |
7292 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 7293 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 7294 (adjusted_mode->crtc_hblank_start - 1) |
7295 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 7296 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 7297 (adjusted_mode->crtc_hsync_start - 1) |
7298 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7299
fe2b8f9d 7300 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c 7301 (adjusted_mode->crtc_vdisplay - 1) |
4d8a62ea 7302 ((crtc_vtotal - 1) << 16));
fe2b8f9d 7303 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c 7304 (adjusted_mode->crtc_vblank_start - 1) |
4d8a62ea 7305 ((crtc_vblank_end - 1) << 16));
fe2b8f9d 7306 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 7307 (adjusted_mode->crtc_vsync_start - 1) |
7308 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7309
b5e508d4
PZ		 7310 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7311 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7312 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7313 * bits. */
7314 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7315 (pipe == PIPE_B || pipe == PIPE_C))
7316 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7317
b0e77b9c
PZ		 7318 /* pipesrc controls the size that is scaled from, which should
7319 * always be the user's requested size.
7320 */
7321 I915_WRITE(PIPESRC(pipe),
6e3c9717
ACO		 7322 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7323 (intel_crtc->config->pipe_src_h - 1));
b0e77b9c
PZ		 7324}
7325
1bd1bd80 7326static void intel_get_pipe_timings(struct intel_crtc *crtc,
5cec258b 7327 struct intel_crtc_state *pipe_config)
1bd1bd80
DV		 7328{
7329 struct drm_device *dev = crtc->base.dev;
7330 struct drm_i915_private *dev_priv = dev->dev_private;
7331 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7332 uint32_t tmp;
7333
7334 tmp = I915_READ(HTOTAL(cpu_transcoder));
2d112de7
ACO		 7335 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7336 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7337 tmp = I915_READ(HBLANK(cpu_transcoder));
2d112de7
ACO		 7338 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7339 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7340 tmp = I915_READ(HSYNC(cpu_transcoder));
2d112de7
ACO		 7341 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7342 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80
DV		 7343
7344 tmp = I915_READ(VTOTAL(cpu_transcoder));
2d112de7
ACO		 7345 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7346 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7347 tmp = I915_READ(VBLANK(cpu_transcoder));
2d112de7
ACO		 7348 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7349 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7350 tmp = I915_READ(VSYNC(cpu_transcoder));
2d112de7
ACO		 7351 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7352 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80
DV		 7353
7354 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
2d112de7
ACO		 7355 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7356 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7357 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
1bd1bd80
DV		 7358 }
7359
7360 tmp = I915_READ(PIPESRC(crtc->pipe));
37327abd
VS		 7361 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7362 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7363
2d112de7
ACO		 7364 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7365 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
1bd1bd80
DV		 7366}
7367
f6a83288 7368void intel_mode_from_pipe_config(struct drm_display_mode *mode,
5cec258b 7369 struct intel_crtc_state *pipe_config)
babea61d 7370{
2d112de7
ACO		 7371 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7372 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7373 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7374 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
babea61d 7375
2d112de7
ACO		 7376 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7377 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7378 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7379 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
babea61d 7380
2d112de7 7381 mode->flags = pipe_config->base.adjusted_mode.flags;
babea61d 7382
2d112de7
ACO		 7383 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7384 mode->flags |= pipe_config->base.adjusted_mode.flags;
babea61d
JB		 7385}
7386
84b046f3
DV		 7387static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7388{
7389 struct drm_device *dev = intel_crtc->base.dev;
7390 struct drm_i915_private *dev_priv = dev->dev_private;
7391 uint32_t pipeconf;
7392
9f11a9e4 7393 pipeconf = 0;
84b046f3 7394
b6b5d049
VS		 7395 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7396 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7397 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
67c72a12 7398
6e3c9717 7399 if (intel_crtc->config->double_wide)
cf532bb2 7400 pipeconf |= PIPECONF_DOUBLE_WIDE;
84b046f3 7401
ff9ce46e
DV		 7402 /* only g4x and later have fancy bpc/dither controls */
7403 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
ff9ce46e 7404 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6e3c9717 7405 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
ff9ce46e 7406 pipeconf |= PIPECONF_DITHER_EN |
84b046f3 7407 PIPECONF_DITHER_TYPE_SP;
84b046f3 7408
6e3c9717 7409 switch (intel_crtc->config->pipe_bpp) {
ff9ce46e
DV		 7410 case 18:
7411 pipeconf |= PIPECONF_6BPC;
7412 break;
7413 case 24:
7414 pipeconf |= PIPECONF_8BPC;
7415 break;
7416 case 30:
7417 pipeconf |= PIPECONF_10BPC;
7418 break;
7419 default:
7420 /* Case prevented by intel_choose_pipe_bpp_dither. */
7421 BUG();
84b046f3
DV		 7422 }
7423 }
7424
7425 if (HAS_PIPE_CXSR(dev)) {
7426 if (intel_crtc->lowfreq_avail) {
7427 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7428 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7429 } else {
7430 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
84b046f3
DV		 7431 }
7432 }
7433
6e3c9717 7434 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
efc2cfff 7435 if (INTEL_INFO(dev)->gen < 4 ||
409ee761 7436 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
efc2cfff
VS		 7437 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7438 else
7439 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7440 } else
84b046f3
DV		 7441 pipeconf |= PIPECONF_PROGRESSIVE;
7442
6e3c9717 7443 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
9f11a9e4 7444 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
9c8e09b7 7445
84b046f3
DV		 7446 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7447 POSTING_READ(PIPECONF(intel_crtc->pipe));
7448}
7449
190f68c5
ACO		 7450static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7451 struct intel_crtc_state *crtc_state)
79e53945 7452{
c7653199 7453 struct drm_device *dev = crtc->base.dev;
79e53945 7454 struct drm_i915_private *dev_priv = dev->dev_private;
c751ce4f 7455 int refclk, num_connectors = 0;
652c393a 7456 intel_clock_t clock, reduced_clock;
a16af721 7457 bool ok, has_reduced_clock = false;
e9fd1c02 7458 bool is_lvds = false, is_dsi = false;
5eddb70b 7459 struct intel_encoder *encoder;
d4906093 7460 const intel_limit_t *limit;
55bb9992 7461 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 7462 struct drm_connector *connector;
55bb9992
ACO		 7463 struct drm_connector_state *connector_state;
7464 int i;
79e53945 7465
dd3cd74a
ACO		 7466 memset(&crtc_state->dpll_hw_state, 0,
7467 sizeof(crtc_state->dpll_hw_state));
7468
da3ced29 7469 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO		 7470 if (connector_state->crtc != &crtc->base)
7471 continue;
7472
7473 encoder = to_intel_encoder(connector_state->best_encoder);
7474
5eddb70b 7475 switch (encoder->type) {
79e53945
JB		 7476 case INTEL_OUTPUT_LVDS:
7477 is_lvds = true;
7478 break;
e9fd1c02
JN		 7479 case INTEL_OUTPUT_DSI:
7480 is_dsi = true;
7481 break;
6847d71b
PZ		 7482 default:
7483 break;
79e53945 7484 }
43565a06 7485
c751ce4f 7486 num_connectors++;
79e53945
JB		 7487 }
7488
f2335330 7489 if (is_dsi)
5b18e57c 7490 return 0;
f2335330 7491
190f68c5 7492 if (!crtc_state->clock_set) {
a93e255f 7493 refclk = i9xx_get_refclk(crtc_state, num_connectors);
79e53945 7494
e9fd1c02
JN		 7495 /*
7496 * Returns a set of divisors for the desired target clock with
7497 * the given refclk, or FALSE. The returned values represent
7498 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7499 * 2) / p1 / p2.
7500 */
a93e255f
ACO		 7501 limit = intel_limit(crtc_state, refclk);
7502 ok = dev_priv->display.find_dpll(limit, crtc_state,
190f68c5 7503 crtc_state->port_clock,
e9fd1c02 7504 refclk, NULL, &clock);
f2335330 7505 if (!ok) {
e9fd1c02
JN		 7506 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7507 return -EINVAL;
7508 }
79e53945 7509
f2335330
JN		 7510 if (is_lvds && dev_priv->lvds_downclock_avail) {
7511 /*
7512 * Ensure we match the reduced clock's P to the target
7513 * clock. If the clocks don't match, we can't switch
7514 * the display clock by using the FP0/FP1. In such case
7515 * we will disable the LVDS downclock feature.
7516 */
7517 has_reduced_clock =
a93e255f 7518 dev_priv->display.find_dpll(limit, crtc_state,
f2335330
JN		 7519 dev_priv->lvds_downclock,
7520 refclk, &clock,
7521 &reduced_clock);
7522 }
7523 /* Compat-code for transition, will disappear. */
190f68c5
ACO		 7524 crtc_state->dpll.n = clock.n;
7525 crtc_state->dpll.m1 = clock.m1;
7526 crtc_state->dpll.m2 = clock.m2;
7527 crtc_state->dpll.p1 = clock.p1;
7528 crtc_state->dpll.p2 = clock.p2;
f47709a9 7529 }
7026d4ac 7530
e9fd1c02 7531 if (IS_GEN2(dev)) {
190f68c5 7532 i8xx_update_pll(crtc, crtc_state,
2a8f64ca
VP		 7533 has_reduced_clock ? &reduced_clock : NULL,
7534 num_connectors);
9d556c99 7535 } else if (IS_CHERRYVIEW(dev)) {
190f68c5 7536 chv_update_pll(crtc, crtc_state);
e9fd1c02 7537 } else if (IS_VALLEYVIEW(dev)) {
190f68c5 7538 vlv_update_pll(crtc, crtc_state);
e9fd1c02 7539 } else {
190f68c5 7540 i9xx_update_pll(crtc, crtc_state,
eb1cbe48 7541 has_reduced_clock ? &reduced_clock : NULL,
eba905b2 7542 num_connectors);
e9fd1c02 7543 }
79e53945 7544
c8f7a0db 7545 return 0;
f564048e
EA		 7546}
7547
2fa2fe9a 7548static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5cec258b 7549 struct intel_crtc_state *pipe_config)
2fa2fe9a
DV		 7550{
7551 struct drm_device *dev = crtc->base.dev;
7552 struct drm_i915_private *dev_priv = dev->dev_private;
7553 uint32_t tmp;
7554
dc9e7dec
VS		 7555 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7556 return;
7557
2fa2fe9a 7558 tmp = I915_READ(PFIT_CONTROL);
06922821
DV		 7559 if (!(tmp & PFIT_ENABLE))
7560 return;
2fa2fe9a 7561
06922821 7562 /* Check whether the pfit is attached to our pipe. */
2fa2fe9a
DV		 7563 if (INTEL_INFO(dev)->gen < 4) {
7564 if (crtc->pipe != PIPE_B)
7565 return;
2fa2fe9a
DV		 7566 } else {
7567 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7568 return;
7569 }
7570
06922821 7571 pipe_config->gmch_pfit.control = tmp;
2fa2fe9a
DV		 7572 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7573 if (INTEL_INFO(dev)->gen < 5)
7574 pipe_config->gmch_pfit.lvds_border_bits =
7575 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7576}
7577
acbec814 7578static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 7579 struct intel_crtc_state *pipe_config)
acbec814
JB		 7580{
7581 struct drm_device *dev = crtc->base.dev;
7582 struct drm_i915_private *dev_priv = dev->dev_private;
7583 int pipe = pipe_config->cpu_transcoder;
7584 intel_clock_t clock;
7585 u32 mdiv;
662c6ecb 7586 int refclk = 100000;
acbec814 7587
f573de5a
SK		 7588 /* In case of MIPI DPLL will not even be used */
7589 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
7590 return;
7591
acbec814 7592 mutex_lock(&dev_priv->dpio_lock);
ab3c759a 7593 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
acbec814
JB		 7594 mutex_unlock(&dev_priv->dpio_lock);
7595
7596 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7597 clock.m2 = mdiv & DPIO_M2DIV_MASK;
7598 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7599 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7600 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7601
f646628b 7602 vlv_clock(refclk, &clock);
acbec814 7603
f646628b
VS		 7604 /* clock.dot is the fast clock */
7605 pipe_config->port_clock = clock.dot / 5;
acbec814
JB		 7606}
7607
5724dbd1
DL		 7608static void
7609i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7610 struct intel_initial_plane_config *plane_config)
1ad292b5
JB		 7611{
7612 struct drm_device *dev = crtc->base.dev;
7613 struct drm_i915_private *dev_priv = dev->dev_private;
7614 u32 val, base, offset;
7615 int pipe = crtc->pipe, plane = crtc->plane;
7616 int fourcc, pixel_format;
6761dd31 7617 unsigned int aligned_height;
b113d5ee 7618 struct drm_framebuffer *fb;
1b842c89 7619 struct intel_framebuffer *intel_fb;
1ad292b5 7620
42a7b088
DL		 7621 val = I915_READ(DSPCNTR(plane));
7622 if (!(val & DISPLAY_PLANE_ENABLE))
7623 return;
7624
d9806c9f 7625 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 7626 if (!intel_fb) {
1ad292b5
JB		 7627 DRM_DEBUG_KMS("failed to alloc fb\n");
7628 return;
7629 }
7630
1b842c89
DL		 7631 fb = &intel_fb->base;
7632
18c5247e
DV		 7633 if (INTEL_INFO(dev)->gen >= 4) {
7634 if (val & DISPPLANE_TILED) {
49af449b 7635 plane_config->tiling = I915_TILING_X;
18c5247e
DV		 7636 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7637 }
7638 }
1ad292b5
JB		 7639
7640 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
b35d63fa 7641 fourcc = i9xx_format_to_fourcc(pixel_format);
b113d5ee
DL		 7642 fb->pixel_format = fourcc;
7643 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
1ad292b5
JB		 7644
7645 if (INTEL_INFO(dev)->gen >= 4) {
49af449b 7646 if (plane_config->tiling)
1ad292b5
JB		 7647 offset = I915_READ(DSPTILEOFF(plane));
7648 else
7649 offset = I915_READ(DSPLINOFF(plane));
7650 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7651 } else {
7652 base = I915_READ(DSPADDR(plane));
7653 }
7654 plane_config->base = base;
7655
7656 val = I915_READ(PIPESRC(pipe));
b113d5ee
DL		 7657 fb->width = ((val >> 16) & 0xfff) + 1;
7658 fb->height = ((val >> 0) & 0xfff) + 1;
1ad292b5
JB		 7659
7660 val = I915_READ(DSPSTRIDE(pipe));
b113d5ee 7661 fb->pitches[0] = val & 0xffffffc0;
1ad292b5 7662
b113d5ee 7663 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 7664 fb->pixel_format,
7665 fb->modifier[0]);
1ad292b5 7666
f37b5c2b 7667 plane_config->size = fb->pitches[0] * aligned_height;
1ad292b5 7668
2844a921
DL		 7669 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7670 pipe_name(pipe), plane, fb->width, fb->height,
7671 fb->bits_per_pixel, base, fb->pitches[0],
7672 plane_config->size);
1ad292b5 7673
2d14030b 7674 plane_config->fb = intel_fb;
1ad292b5
JB		 7675}
7676
70b23a98 7677static void chv_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 7678 struct intel_crtc_state *pipe_config)
70b23a98
VS		 7679{
7680 struct drm_device *dev = crtc->base.dev;
7681 struct drm_i915_private *dev_priv = dev->dev_private;
7682 int pipe = pipe_config->cpu_transcoder;
7683 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7684 intel_clock_t clock;
7685 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
7686 int refclk = 100000;
7687
7688 mutex_lock(&dev_priv->dpio_lock);
7689 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
7690 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
7691 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
7692 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
7693 mutex_unlock(&dev_priv->dpio_lock);
7694
7695 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
7696 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
7697 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
7698 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
7699 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
7700
7701 chv_clock(refclk, &clock);
7702
7703 /* clock.dot is the fast clock */
7704 pipe_config->port_clock = clock.dot / 5;
7705}
7706
0e8ffe1b 7707static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5cec258b 7708 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 7709{
7710 struct drm_device *dev = crtc->base.dev;
7711 struct drm_i915_private *dev_priv = dev->dev_private;
7712 uint32_t tmp;
7713
f458ebbc
DV		 7714 if (!intel_display_power_is_enabled(dev_priv,
7715 POWER_DOMAIN_PIPE(crtc->pipe)))
b5482bd0
ID		 7716 return false;
7717
e143a21c 7718 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 7719 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 7720
0e8ffe1b
DV		 7721 tmp = I915_READ(PIPECONF(crtc->pipe));
7722 if (!(tmp & PIPECONF_ENABLE))
7723 return false;
7724
42571aef
VS		 7725 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
7726 switch (tmp & PIPECONF_BPC_MASK) {
7727 case PIPECONF_6BPC:
7728 pipe_config->pipe_bpp = 18;
7729 break;
7730 case PIPECONF_8BPC:
7731 pipe_config->pipe_bpp = 24;
7732 break;
7733 case PIPECONF_10BPC:
7734 pipe_config->pipe_bpp = 30;
7735 break;
7736 default:
7737 break;
7738 }
7739 }
7740
b5a9fa09
DV		 7741 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
7742 pipe_config->limited_color_range = true;
7743
282740f7
VS		 7744 if (INTEL_INFO(dev)->gen < 4)
7745 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
7746
1bd1bd80
DV		 7747 intel_get_pipe_timings(crtc, pipe_config);
7748
2fa2fe9a
DV		 7749 i9xx_get_pfit_config(crtc, pipe_config);
7750
6c49f241
DV		 7751 if (INTEL_INFO(dev)->gen >= 4) {
7752 tmp = I915_READ(DPLL_MD(crtc->pipe));
7753 pipe_config->pixel_multiplier =
7754 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
7755 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8bcc2795 7756 pipe_config->dpll_hw_state.dpll_md = tmp;
6c49f241
DV		 7757 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7758 tmp = I915_READ(DPLL(crtc->pipe));
7759 pipe_config->pixel_multiplier =
7760 ((tmp & SDVO_MULTIPLIER_MASK)
7761 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
7762 } else {
7763 /* Note that on i915G/GM the pixel multiplier is in the sdvo
7764 * port and will be fixed up in the encoder->get_config
7765 * function. */
7766 pipe_config->pixel_multiplier = 1;
7767 }
8bcc2795
DV		 7768 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
7769 if (!IS_VALLEYVIEW(dev)) {
1c4e0274
VS		 7770 /*
7771 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
7772 * on 830. Filter it out here so that we don't
7773 * report errors due to that.
7774 */
7775 if (IS_I830(dev))
7776 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
7777
8bcc2795
DV		 7778 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
7779 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
165e901c
VS		 7780 } else {
7781 /* Mask out read-only status bits. */
7782 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
7783 DPLL_PORTC_READY_MASK |
7784 DPLL_PORTB_READY_MASK);
8bcc2795 7785 }
6c49f241 7786
70b23a98
VS		 7787 if (IS_CHERRYVIEW(dev))
7788 chv_crtc_clock_get(crtc, pipe_config);
7789 else if (IS_VALLEYVIEW(dev))
acbec814
JB		 7790 vlv_crtc_clock_get(crtc, pipe_config);
7791 else
7792 i9xx_crtc_clock_get(crtc, pipe_config);
18442d08 7793
0e8ffe1b
DV		 7794 return true;
7795}
7796
dde86e2d 7797static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 7798{
7799 struct drm_i915_private *dev_priv = dev->dev_private;
13d83a67 7800 struct intel_encoder *encoder;
74cfd7ac 7801 u32 val, final;
13d83a67 7802 bool has_lvds = false;
199e5d79 7803 bool has_cpu_edp = false;
199e5d79 7804 bool has_panel = false;
99eb6a01
KP		 7805 bool has_ck505 = false;
7806 bool can_ssc = false;
13d83a67
JB		 7807
7808 /* We need to take the global config into account */
b2784e15 7809 for_each_intel_encoder(dev, encoder) {
199e5d79
KP		 7810 switch (encoder->type) {
7811 case INTEL_OUTPUT_LVDS:
7812 has_panel = true;
7813 has_lvds = true;
7814 break;
7815 case INTEL_OUTPUT_EDP:
7816 has_panel = true;
2de6905f 7817 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
199e5d79
KP		 7818 has_cpu_edp = true;
7819 break;
6847d71b
PZ		 7820 default:
7821 break;
13d83a67
JB		 7822 }
7823 }
7824
99eb6a01 7825 if (HAS_PCH_IBX(dev)) {
41aa3448 7826 has_ck505 = dev_priv->vbt.display_clock_mode;
99eb6a01
KP		 7827 can_ssc = has_ck505;
7828 } else {
7829 has_ck505 = false;
7830 can_ssc = true;
7831 }
7832
2de6905f
ID		 7833 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
7834 has_panel, has_lvds, has_ck505);
13d83a67
JB		 7835
7836 /* Ironlake: try to setup display ref clock before DPLL
7837 * enabling. This is only under driver's control after
7838 * PCH B stepping, previous chipset stepping should be
7839 * ignoring this setting.
7840 */
74cfd7ac
CW		 7841 val = I915_READ(PCH_DREF_CONTROL);
7842
7843 /* As we must carefully and slowly disable/enable each source in turn,
7844 * compute the final state we want first and check if we need to
7845 * make any changes at all.
7846 */
7847 final = val;
7848 final &= ~DREF_NONSPREAD_SOURCE_MASK;
7849 if (has_ck505)
7850 final |= DREF_NONSPREAD_CK505_ENABLE;
7851 else
7852 final |= DREF_NONSPREAD_SOURCE_ENABLE;
7853
7854 final &= ~DREF_SSC_SOURCE_MASK;
7855 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7856 final &= ~DREF_SSC1_ENABLE;
7857
7858 if (has_panel) {
7859 final |= DREF_SSC_SOURCE_ENABLE;
7860
7861 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7862 final |= DREF_SSC1_ENABLE;
7863
7864 if (has_cpu_edp) {
7865 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7866 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7867 else
7868 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7869 } else
7870 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7871 } else {
7872 final |= DREF_SSC_SOURCE_DISABLE;
7873 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7874 }
7875
7876 if (final == val)
7877 return;
7878
13d83a67 7879 /* Always enable nonspread source */
74cfd7ac 7880 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 7881
99eb6a01 7882 if (has_ck505)
74cfd7ac 7883 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 7884 else
74cfd7ac 7885 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 7886
199e5d79 7887 if (has_panel) {
74cfd7ac
CW		 7888 val &= ~DREF_SSC_SOURCE_MASK;
7889 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 7890
199e5d79 7891 /* SSC must be turned on before enabling the CPU output */
99eb6a01 7892 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 7893 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 7894 val |= DREF_SSC1_ENABLE;
e77166b5 7895 } else
74cfd7ac 7896 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 7897
7898 /* Get SSC going before enabling the outputs */
74cfd7ac 7899 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 7900 POSTING_READ(PCH_DREF_CONTROL);
7901 udelay(200);
7902
74cfd7ac 7903 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 7904
7905 /* Enable CPU source on CPU attached eDP */
199e5d79 7906 if (has_cpu_edp) {
99eb6a01 7907 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 7908 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 7909 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
eba905b2 7910 } else
74cfd7ac 7911 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 7912 } else
74cfd7ac 7913 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 7914
74cfd7ac 7915 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 7916 POSTING_READ(PCH_DREF_CONTROL);
7917 udelay(200);
7918 } else {
7919 DRM_DEBUG_KMS("Disabling SSC entirely\n");
7920
74cfd7ac 7921 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 7922
7923 /* Turn off CPU output */
74cfd7ac 7924 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 7925
74cfd7ac 7926 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 7927 POSTING_READ(PCH_DREF_CONTROL);
7928 udelay(200);
7929
7930 /* Turn off the SSC source */
74cfd7ac
CW		 7931 val &= ~DREF_SSC_SOURCE_MASK;
7932 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 7933
7934 /* Turn off SSC1 */
74cfd7ac 7935 val &= ~DREF_SSC1_ENABLE;
199e5d79 7936
74cfd7ac 7937 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 7938 POSTING_READ(PCH_DREF_CONTROL);
7939 udelay(200);
7940 }
74cfd7ac
CW		 7941
7942 BUG_ON(val != final);
13d83a67
JB		 7943}
7944
f31f2d55 7945static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
dde86e2d 7946{
f31f2d55 7947 uint32_t tmp;
dde86e2d 7948
0ff066a9
PZ		 7949 tmp = I915_READ(SOUTH_CHICKEN2);
7950 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
7951 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 7952
0ff066a9
PZ		 7953 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
7954 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
7955 DRM_ERROR("FDI mPHY reset assert timeout\n");
dde86e2d 7956
0ff066a9
PZ		 7957 tmp = I915_READ(SOUTH_CHICKEN2);
7958 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
7959 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 7960
0ff066a9
PZ		 7961 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
7962 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
7963 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
f31f2d55
PZ		 7964}
7965
7966/* WaMPhyProgramming:hsw */
7967static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
7968{
7969 uint32_t tmp;
dde86e2d
PZ		 7970
7971 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
7972 tmp &= ~(0xFF << 24);
7973 tmp |= (0x12 << 24);
7974 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
7975
dde86e2d
PZ		 7976 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
7977 tmp |= (1 << 11);
7978 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
7979
7980 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
7981 tmp |= (1 << 11);
7982 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
7983
dde86e2d
PZ		 7984 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
7985 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7986 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
7987
7988 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
7989 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7990 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
7991
0ff066a9
PZ		 7992 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
7993 tmp &= ~(7 << 13);
7994 tmp |= (5 << 13);
7995 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
dde86e2d 7996
0ff066a9
PZ		 7997 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
7998 tmp &= ~(7 << 13);
7999 tmp |= (5 << 13);
8000 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
dde86e2d
PZ		 8001
8002 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8003 tmp &= ~0xFF;
8004 tmp |= 0x1C;
8005 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8006
8007 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8008 tmp &= ~0xFF;
8009 tmp |= 0x1C;
8010 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8011
8012 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8013 tmp &= ~(0xFF << 16);
8014 tmp |= (0x1C << 16);
8015 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8016
8017 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8018 tmp &= ~(0xFF << 16);
8019 tmp |= (0x1C << 16);
8020 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8021
0ff066a9
PZ		 8022 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8023 tmp |= (1 << 27);
8024 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
dde86e2d 8025
0ff066a9
PZ		 8026 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8027 tmp |= (1 << 27);
8028 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
dde86e2d 8029
0ff066a9
PZ		 8030 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8031 tmp &= ~(0xF << 28);
8032 tmp |= (4 << 28);
8033 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
dde86e2d 8034
0ff066a9
PZ		 8035 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8036 tmp &= ~(0xF << 28);
8037 tmp |= (4 << 28);
8038 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
f31f2d55
PZ		 8039}
8040
2fa86a1f
PZ		 8041/* Implements 3 different sequences from BSpec chapter "Display iCLK
8042 * Programming" based on the parameters passed:
8043 * - Sequence to enable CLKOUT_DP
8044 * - Sequence to enable CLKOUT_DP without spread
8045 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8046 */
8047static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8048 bool with_fdi)
f31f2d55
PZ		 8049{
8050 struct drm_i915_private *dev_priv = dev->dev_private;
2fa86a1f
PZ		 8051 uint32_t reg, tmp;
8052
8053 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8054 with_spread = true;
8055 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
8056 with_fdi, "LP PCH doesn't have FDI\n"))
8057 with_fdi = false;
f31f2d55
PZ		 8058
8059 mutex_lock(&dev_priv->dpio_lock);
8060
8061 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8062 tmp &= ~SBI_SSCCTL_DISABLE;
8063 tmp |= SBI_SSCCTL_PATHALT;
8064 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8065
8066 udelay(24);
8067
2fa86a1f
PZ		 8068 if (with_spread) {
8069 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8070 tmp &= ~SBI_SSCCTL_PATHALT;
8071 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
f31f2d55 8072
2fa86a1f
PZ		 8073 if (with_fdi) {
8074 lpt_reset_fdi_mphy(dev_priv);
8075 lpt_program_fdi_mphy(dev_priv);
8076 }
8077 }
dde86e2d 8078
2fa86a1f
PZ		 8079 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8080 SBI_GEN0 : SBI_DBUFF0;
8081 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8082 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8083 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
c00db246
DV		 8084
8085 mutex_unlock(&dev_priv->dpio_lock);
dde86e2d
PZ		 8086}
8087
47701c3b
PZ		 8088/* Sequence to disable CLKOUT_DP */
8089static void lpt_disable_clkout_dp(struct drm_device *dev)
8090{
8091 struct drm_i915_private *dev_priv = dev->dev_private;
8092 uint32_t reg, tmp;
8093
8094 mutex_lock(&dev_priv->dpio_lock);
8095
8096 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8097 SBI_GEN0 : SBI_DBUFF0;
8098 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8099 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8100 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8101
8102 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8103 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8104 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8105 tmp |= SBI_SSCCTL_PATHALT;
8106 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8107 udelay(32);
8108 }
8109 tmp |= SBI_SSCCTL_DISABLE;
8110 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8111 }
8112
8113 mutex_unlock(&dev_priv->dpio_lock);
8114}
8115
bf8fa3d3
PZ		 8116static void lpt_init_pch_refclk(struct drm_device *dev)
8117{
bf8fa3d3
PZ		 8118 struct intel_encoder *encoder;
8119 bool has_vga = false;
8120
b2784e15 8121 for_each_intel_encoder(dev, encoder) {
bf8fa3d3
PZ		 8122 switch (encoder->type) {
8123 case INTEL_OUTPUT_ANALOG:
8124 has_vga = true;
8125 break;
6847d71b
PZ		 8126 default:
8127 break;
bf8fa3d3
PZ		 8128 }
8129 }
8130
47701c3b
PZ		 8131 if (has_vga)
8132 lpt_enable_clkout_dp(dev, true, true);
8133 else
8134 lpt_disable_clkout_dp(dev);
bf8fa3d3
PZ		 8135}
8136
dde86e2d
PZ		 8137/*
8138 * Initialize reference clocks when the driver loads
8139 */
8140void intel_init_pch_refclk(struct drm_device *dev)
8141{
8142 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8143 ironlake_init_pch_refclk(dev);
8144 else if (HAS_PCH_LPT(dev))
8145 lpt_init_pch_refclk(dev);
8146}
8147
55bb9992 8148static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
d9d444cb 8149{
55bb9992 8150 struct drm_device *dev = crtc_state->base.crtc->dev;
d9d444cb 8151 struct drm_i915_private *dev_priv = dev->dev_private;
55bb9992 8152 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 8153 struct drm_connector *connector;
55bb9992 8154 struct drm_connector_state *connector_state;
d9d444cb 8155 struct intel_encoder *encoder;
55bb9992 8156 int num_connectors = 0, i;
d9d444cb
JB		 8157 bool is_lvds = false;
8158
da3ced29 8159 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO		 8160 if (connector_state->crtc != crtc_state->base.crtc)
8161 continue;
8162
8163 encoder = to_intel_encoder(connector_state->best_encoder);
8164
d9d444cb
JB		 8165 switch (encoder->type) {
8166 case INTEL_OUTPUT_LVDS:
8167 is_lvds = true;
8168 break;
6847d71b
PZ		 8169 default:
8170 break;
d9d444cb
JB		 8171 }
8172 num_connectors++;
8173 }
8174
8175 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
e91e941b 8176 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
41aa3448 8177 dev_priv->vbt.lvds_ssc_freq);
e91e941b 8178 return dev_priv->vbt.lvds_ssc_freq;
d9d444cb
JB		 8179 }
8180
8181 return 120000;
8182}
8183
6ff93609 8184static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 8185{
c8203565 8186 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 8187 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8188 int pipe = intel_crtc->pipe;
c8203565
PZ		 8189 uint32_t val;
8190
78114071 8191 val = 0;
c8203565 8192
6e3c9717 8193 switch (intel_crtc->config->pipe_bpp) {
c8203565 8194 case 18:
dfd07d72 8195 val |= PIPECONF_6BPC;
c8203565
PZ		 8196 break;
8197 case 24:
dfd07d72 8198 val |= PIPECONF_8BPC;
c8203565
PZ		 8199 break;
8200 case 30:
dfd07d72 8201 val |= PIPECONF_10BPC;
c8203565
PZ		 8202 break;
8203 case 36:
dfd07d72 8204 val |= PIPECONF_12BPC;
c8203565
PZ		 8205 break;
8206 default:
cc769b62
PZ		 8207 /* Case prevented by intel_choose_pipe_bpp_dither. */
8208 BUG();
c8203565
PZ		 8209 }
8210
6e3c9717 8211 if (intel_crtc->config->dither)
c8203565
PZ		 8212 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8213
6e3c9717 8214 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ		 8215 val |= PIPECONF_INTERLACED_ILK;
8216 else
8217 val |= PIPECONF_PROGRESSIVE;
8218
6e3c9717 8219 if (intel_crtc->config->limited_color_range)
3685a8f3 8220 val |= PIPECONF_COLOR_RANGE_SELECT;
3685a8f3 8221
c8203565
PZ		 8222 I915_WRITE(PIPECONF(pipe), val);
8223 POSTING_READ(PIPECONF(pipe));
8224}
8225
86d3efce
VS		 8226/*
8227 * Set up the pipe CSC unit.
8228 *
8229 * Currently only full range RGB to limited range RGB conversion
8230 * is supported, but eventually this should handle various
8231 * RGB<->YCbCr scenarios as well.
8232 */
50f3b016 8233static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 8234{
8235 struct drm_device *dev = crtc->dev;
8236 struct drm_i915_private *dev_priv = dev->dev_private;
8237 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8238 int pipe = intel_crtc->pipe;
8239 uint16_t coeff = 0x7800; /* 1.0 */
8240
8241 /*
8242 * TODO: Check what kind of values actually come out of the pipe
8243 * with these coeff/postoff values and adjust to get the best
8244 * accuracy. Perhaps we even need to take the bpc value into
8245 * consideration.
8246 */
8247
6e3c9717 8248 if (intel_crtc->config->limited_color_range)
86d3efce
VS		 8249 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8250
8251 /*
8252 * GY/GU and RY/RU should be the other way around according
8253 * to BSpec, but reality doesn't agree. Just set them up in
8254 * a way that results in the correct picture.
8255 */
8256 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8257 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8258
8259 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8260 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8261
8262 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8263 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8264
8265 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8266 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8267 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8268
8269 if (INTEL_INFO(dev)->gen > 6) {
8270 uint16_t postoff = 0;
8271
6e3c9717 8272 if (intel_crtc->config->limited_color_range)
32cf0cb0 8273 postoff = (16 * (1 << 12) / 255) & 0x1fff;
86d3efce
VS		 8274
8275 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8276 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8277 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8278
8279 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8280 } else {
8281 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8282
6e3c9717 8283 if (intel_crtc->config->limited_color_range)
86d3efce
VS		 8284 mode |= CSC_BLACK_SCREEN_OFFSET;
8285
8286 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8287 }
8288}
8289
6ff93609 8290static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38 8291{
756f85cf
PZ		 8292 struct drm_device *dev = crtc->dev;
8293 struct drm_i915_private *dev_priv = dev->dev_private;
ee2b0b38 8294 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
756f85cf 8295 enum pipe pipe = intel_crtc->pipe;
6e3c9717 8296 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
ee2b0b38
PZ		 8297 uint32_t val;
8298
3eff4faa 8299 val = 0;
ee2b0b38 8300
6e3c9717 8301 if (IS_HASWELL(dev) && intel_crtc->config->dither)
ee2b0b38
PZ		 8302 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8303
6e3c9717 8304 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ		 8305 val |= PIPECONF_INTERLACED_ILK;
8306 else
8307 val |= PIPECONF_PROGRESSIVE;
8308
702e7a56
PZ		 8309 I915_WRITE(PIPECONF(cpu_transcoder), val);
8310 POSTING_READ(PIPECONF(cpu_transcoder));
3eff4faa
DV		 8311
8312 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8313 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
756f85cf 8314
3cdf122c 8315 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
756f85cf
PZ		 8316 val = 0;
8317
6e3c9717 8318 switch (intel_crtc->config->pipe_bpp) {
756f85cf
PZ		 8319 case 18:
8320 val |= PIPEMISC_DITHER_6_BPC;
8321 break;
8322 case 24:
8323 val |= PIPEMISC_DITHER_8_BPC;
8324 break;
8325 case 30:
8326 val |= PIPEMISC_DITHER_10_BPC;
8327 break;
8328 case 36:
8329 val |= PIPEMISC_DITHER_12_BPC;
8330 break;
8331 default:
8332 /* Case prevented by pipe_config_set_bpp. */
8333 BUG();
8334 }
8335
6e3c9717 8336 if (intel_crtc->config->dither)
756f85cf
PZ		 8337 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8338
8339 I915_WRITE(PIPEMISC(pipe), val);
8340 }
ee2b0b38
PZ		 8341}
8342
6591c6e4 8343static bool ironlake_compute_clocks(struct drm_crtc *crtc,
190f68c5 8344 struct intel_crtc_state *crtc_state,
6591c6e4
PZ		 8345 intel_clock_t *clock,
8346 bool *has_reduced_clock,
8347 intel_clock_t *reduced_clock)
8348{
8349 struct drm_device *dev = crtc->dev;
8350 struct drm_i915_private *dev_priv = dev->dev_private;
6591c6e4 8351 int refclk;
d4906093 8352 const intel_limit_t *limit;
a16af721 8353 bool ret, is_lvds = false;
79e53945 8354
a93e255f 8355 is_lvds = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS);
79e53945 8356
55bb9992 8357 refclk = ironlake_get_refclk(crtc_state);
79e53945 8358
d4906093
ML		 8359 /*
8360 * Returns a set of divisors for the desired target clock with the given
8361 * refclk, or FALSE. The returned values represent the clock equation:
8362 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8363 */
a93e255f
ACO		 8364 limit = intel_limit(crtc_state, refclk);
8365 ret = dev_priv->display.find_dpll(limit, crtc_state,
190f68c5 8366 crtc_state->port_clock,
ee9300bb 8367 refclk, NULL, clock);
6591c6e4
PZ		 8368 if (!ret)
8369 return false;
cda4b7d3 8370
ddc9003c 8371 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 8372 /*
8373 * Ensure we match the reduced clock's P to the target clock.
8374 * If the clocks don't match, we can't switch the display clock
8375 * by using the FP0/FP1. In such case we will disable the LVDS
8376 * downclock feature.
8377 */
ee9300bb 8378 *has_reduced_clock =
a93e255f 8379 dev_priv->display.find_dpll(limit, crtc_state,
ee9300bb
DV		 8380 dev_priv->lvds_downclock,
8381 refclk, clock,
8382 reduced_clock);
652c393a 8383 }
61e9653f 8384
6591c6e4
PZ		 8385 return true;
8386}
8387
d4b1931c
PZ		 8388int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8389{
8390 /*
8391 * Account for spread spectrum to avoid
8392 * oversubscribing the link. Max center spread
8393 * is 2.5%; use 5% for safety's sake.
8394 */
8395 u32 bps = target_clock * bpp * 21 / 20;
619d4d04 8396 return DIV_ROUND_UP(bps, link_bw * 8);
d4b1931c
PZ		 8397}
8398
7429e9d4 8399static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6cf86a5e 8400{
7429e9d4 8401 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
f48d8f23
PZ		 8402}
8403
de13a2e3 8404static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
190f68c5 8405 struct intel_crtc_state *crtc_state,
7429e9d4 8406 u32 *fp,
9a7c7890 8407 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 8408{
de13a2e3 8409 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 8410 struct drm_device *dev = crtc->dev;
8411 struct drm_i915_private *dev_priv = dev->dev_private;
55bb9992 8412 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 8413 struct drm_connector *connector;
55bb9992
ACO		 8414 struct drm_connector_state *connector_state;
8415 struct intel_encoder *encoder;
de13a2e3 8416 uint32_t dpll;
55bb9992 8417 int factor, num_connectors = 0, i;
09ede541 8418 bool is_lvds = false, is_sdvo = false;
79e53945 8419
da3ced29 8420 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO		 8421 if (connector_state->crtc != crtc_state->base.crtc)
8422 continue;
8423
8424 encoder = to_intel_encoder(connector_state->best_encoder);
8425
8426 switch (encoder->type) {
79e53945
JB		 8427 case INTEL_OUTPUT_LVDS:
8428 is_lvds = true;
8429 break;
8430 case INTEL_OUTPUT_SDVO:
7d57382e 8431 case INTEL_OUTPUT_HDMI:
79e53945 8432 is_sdvo = true;
79e53945 8433 break;
6847d71b
PZ		 8434 default:
8435 break;
79e53945 8436 }
43565a06 8437
c751ce4f 8438 num_connectors++;
79e53945 8439 }
79e53945 8440
c1858123 8441 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 8442 factor = 21;
8443 if (is_lvds) {
8444 if ((intel_panel_use_ssc(dev_priv) &&
e91e941b 8445 dev_priv->vbt.lvds_ssc_freq == 100000) ||
f0b44056 8446 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297 8447 factor = 25;
190f68c5 8448 } else if (crtc_state->sdvo_tv_clock)
8febb297 8449 factor = 20;
c1858123 8450
190f68c5 8451 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
7d0ac5b7 8452 *fp |= FP_CB_TUNE;
2c07245f 8453
9a7c7890
DV		 8454 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8455 *fp2 |= FP_CB_TUNE;
8456
5eddb70b 8457 dpll = 0;
2c07245f 8458
a07d6787
EA		 8459 if (is_lvds)
8460 dpll |= DPLLB_MODE_LVDS;
8461 else
8462 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f 8463
190f68c5 8464 dpll |= (crtc_state->pixel_multiplier - 1)
ef1b460d 8465 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
198a037f
DV		 8466
8467 if (is_sdvo)
4a33e48d 8468 dpll |= DPLL_SDVO_HIGH_SPEED;
190f68c5 8469 if (crtc_state->has_dp_encoder)
4a33e48d 8470 dpll |= DPLL_SDVO_HIGH_SPEED;
79e53945 8471
a07d6787 8472 /* compute bitmask from p1 value */
190f68c5 8473 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 8474 /* also FPA1 */
190f68c5 8475 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 8476
190f68c5 8477 switch (crtc_state->dpll.p2) {
a07d6787
EA		 8478 case 5:
8479 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8480 break;
8481 case 7:
8482 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8483 break;
8484 case 10:
8485 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8486 break;
8487 case 14:
8488 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8489 break;
79e53945
JB		 8490 }
8491
b4c09f3b 8492 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 8493 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 8494 else
8495 dpll |= PLL_REF_INPUT_DREFCLK;
8496
959e16d6 8497 return dpll | DPLL_VCO_ENABLE;
de13a2e3
PZ		 8498}
8499
190f68c5
ACO		 8500static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8501 struct intel_crtc_state *crtc_state)
de13a2e3 8502{
c7653199 8503 struct drm_device *dev = crtc->base.dev;
de13a2e3 8504 intel_clock_t clock, reduced_clock;
cbbab5bd 8505 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 8506 bool ok, has_reduced_clock = false;
8b47047b 8507 bool is_lvds = false;
e2b78267 8508 struct intel_shared_dpll *pll;
de13a2e3 8509
dd3cd74a
ACO		 8510 memset(&crtc_state->dpll_hw_state, 0,
8511 sizeof(crtc_state->dpll_hw_state));
8512
409ee761 8513 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
79e53945 8514
5dc5298b
PZ		 8515 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8516 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 8517
190f68c5 8518 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
de13a2e3 8519 &has_reduced_clock, &reduced_clock);
190f68c5 8520 if (!ok && !crtc_state->clock_set) {
de13a2e3
PZ		 8521 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8522 return -EINVAL;
79e53945 8523 }
f47709a9 8524 /* Compat-code for transition, will disappear. */
190f68c5
ACO		 8525 if (!crtc_state->clock_set) {
8526 crtc_state->dpll.n = clock.n;
8527 crtc_state->dpll.m1 = clock.m1;
8528 crtc_state->dpll.m2 = clock.m2;
8529 crtc_state->dpll.p1 = clock.p1;
8530 crtc_state->dpll.p2 = clock.p2;
f47709a9 8531 }
79e53945 8532
5dc5298b 8533 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
190f68c5
ACO		 8534 if (crtc_state->has_pch_encoder) {
8535 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
cbbab5bd 8536 if (has_reduced_clock)
7429e9d4 8537 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 8538
190f68c5 8539 dpll = ironlake_compute_dpll(crtc, crtc_state,
cbbab5bd
DV		 8540 &fp, &reduced_clock,
8541 has_reduced_clock ? &fp2 : NULL);
8542
190f68c5
ACO		 8543 crtc_state->dpll_hw_state.dpll = dpll;
8544 crtc_state->dpll_hw_state.fp0 = fp;
66e985c0 8545 if (has_reduced_clock)
190f68c5 8546 crtc_state->dpll_hw_state.fp1 = fp2;
66e985c0 8547 else
190f68c5 8548 crtc_state->dpll_hw_state.fp1 = fp;
66e985c0 8549
190f68c5 8550 pll = intel_get_shared_dpll(crtc, crtc_state);
ee7b9f93 8551 if (pll == NULL) {
84f44ce7 8552 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
c7653199 8553 pipe_name(crtc->pipe));
4b645f14
JB		 8554 return -EINVAL;
8555 }
3fb37703 8556 }
79e53945 8557
ab585dea 8558 if (is_lvds && has_reduced_clock)
c7653199 8559 crtc->lowfreq_avail = true;
bcd644e0 8560 else
c7653199 8561 crtc->lowfreq_avail = false;
e2b78267 8562
c8f7a0db 8563 return 0;
79e53945
JB		 8564}
8565
eb14cb74
VS		 8566static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8567 struct intel_link_m_n *m_n)
8568{
8569 struct drm_device *dev = crtc->base.dev;
8570 struct drm_i915_private *dev_priv = dev->dev_private;
8571 enum pipe pipe = crtc->pipe;
8572
8573 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8574 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8575 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8576 & ~TU_SIZE_MASK;
8577 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8578 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8579 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8580}
8581
8582static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8583 enum transcoder transcoder,
b95af8be
VK		 8584 struct intel_link_m_n *m_n,
8585 struct intel_link_m_n *m2_n2)
72419203
DV		 8586{
8587 struct drm_device *dev = crtc->base.dev;
8588 struct drm_i915_private *dev_priv = dev->dev_private;
eb14cb74 8589 enum pipe pipe = crtc->pipe;
72419203 8590
eb14cb74
VS		 8591 if (INTEL_INFO(dev)->gen >= 5) {
8592 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8593 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8594 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8595 & ~TU_SIZE_MASK;
8596 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8597 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8598 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
b95af8be
VK		 8599 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8600 * gen < 8) and if DRRS is supported (to make sure the
8601 * registers are not unnecessarily read).
8602 */
8603 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
6e3c9717 8604 crtc->config->has_drrs) {
b95af8be
VK		 8605 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8606 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8607 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8608 & ~TU_SIZE_MASK;
8609 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8610 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8611 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8612 }
eb14cb74
VS		 8613 } else {
8614 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8615 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8616 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8617 & ~TU_SIZE_MASK;
8618 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8619 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8620 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8621 }
8622}
8623
8624void intel_dp_get_m_n(struct intel_crtc *crtc,
5cec258b 8625 struct intel_crtc_state *pipe_config)
eb14cb74 8626{
681a8504 8627 if (pipe_config->has_pch_encoder)
eb14cb74
VS		 8628 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8629 else
8630 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
b95af8be
VK		 8631 &pipe_config->dp_m_n,
8632 &pipe_config->dp_m2_n2);
eb14cb74 8633}
72419203 8634
eb14cb74 8635static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5cec258b 8636 struct intel_crtc_state *pipe_config)
eb14cb74
VS		 8637{
8638 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
b95af8be 8639 &pipe_config->fdi_m_n, NULL);
72419203
DV		 8640}
8641
bd2e244f 8642static void skylake_get_pfit_config(struct intel_crtc *crtc,
5cec258b 8643 struct intel_crtc_state *pipe_config)
bd2e244f
JB		 8644{
8645 struct drm_device *dev = crtc->base.dev;
8646 struct drm_i915_private *dev_priv = dev->dev_private;
a1b2278e
CK		 8647 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8648 uint32_t ps_ctrl = 0;
8649 int id = -1;
8650 int i;
bd2e244f 8651
a1b2278e
CK		 8652 /* find scaler attached to this pipe */
8653 for (i = 0; i < crtc->num_scalers; i++) {
8654 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
8655 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
8656 id = i;
8657 pipe_config->pch_pfit.enabled = true;
8658 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
8659 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
8660 break;
8661 }
8662 }
bd2e244f 8663
a1b2278e
CK		 8664 scaler_state->scaler_id = id;
8665 if (id >= 0) {
8666 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
8667 } else {
8668 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
bd2e244f
JB		 8669 }
8670}
8671
5724dbd1
DL		 8672static void
8673skylake_get_initial_plane_config(struct intel_crtc *crtc,
8674 struct intel_initial_plane_config *plane_config)
bc8d7dff
DL		 8675{
8676 struct drm_device *dev = crtc->base.dev;
8677 struct drm_i915_private *dev_priv = dev->dev_private;
40f46283 8678 u32 val, base, offset, stride_mult, tiling;
bc8d7dff
DL		 8679 int pipe = crtc->pipe;
8680 int fourcc, pixel_format;
6761dd31 8681 unsigned int aligned_height;
bc8d7dff 8682 struct drm_framebuffer *fb;
1b842c89 8683 struct intel_framebuffer *intel_fb;
bc8d7dff 8684
d9806c9f 8685 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 8686 if (!intel_fb) {
bc8d7dff
DL		 8687 DRM_DEBUG_KMS("failed to alloc fb\n");
8688 return;
8689 }
8690
1b842c89
DL		 8691 fb = &intel_fb->base;
8692
bc8d7dff 8693 val = I915_READ(PLANE_CTL(pipe, 0));
42a7b088
DL		 8694 if (!(val & PLANE_CTL_ENABLE))
8695 goto error;
8696
bc8d7dff
DL		 8697 pixel_format = val & PLANE_CTL_FORMAT_MASK;
8698 fourcc = skl_format_to_fourcc(pixel_format,
8699 val & PLANE_CTL_ORDER_RGBX,
8700 val & PLANE_CTL_ALPHA_MASK);
8701 fb->pixel_format = fourcc;
8702 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8703
40f46283
DL		 8704 tiling = val & PLANE_CTL_TILED_MASK;
8705 switch (tiling) {
8706 case PLANE_CTL_TILED_LINEAR:
8707 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
8708 break;
8709 case PLANE_CTL_TILED_X:
8710 plane_config->tiling = I915_TILING_X;
8711 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8712 break;
8713 case PLANE_CTL_TILED_Y:
8714 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
8715 break;
8716 case PLANE_CTL_TILED_YF:
8717 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
8718 break;
8719 default:
8720 MISSING_CASE(tiling);
8721 goto error;
8722 }
8723
bc8d7dff
DL		 8724 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
8725 plane_config->base = base;
8726
8727 offset = I915_READ(PLANE_OFFSET(pipe, 0));
8728
8729 val = I915_READ(PLANE_SIZE(pipe, 0));
8730 fb->height = ((val >> 16) & 0xfff) + 1;
8731 fb->width = ((val >> 0) & 0x1fff) + 1;
8732
8733 val = I915_READ(PLANE_STRIDE(pipe, 0));
40f46283
DL		 8734 stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
8735 fb->pixel_format);
bc8d7dff
DL		 8736 fb->pitches[0] = (val & 0x3ff) * stride_mult;
8737
8738 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 8739 fb->pixel_format,
8740 fb->modifier[0]);
bc8d7dff 8741
f37b5c2b 8742 plane_config->size = fb->pitches[0] * aligned_height;
bc8d7dff
DL		 8743
8744 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8745 pipe_name(pipe), fb->width, fb->height,
8746 fb->bits_per_pixel, base, fb->pitches[0],
8747 plane_config->size);
8748
2d14030b 8749 plane_config->fb = intel_fb;
bc8d7dff
DL		 8750 return;
8751
8752error:
8753 kfree(fb);
8754}
8755
2fa2fe9a 8756static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5cec258b 8757 struct intel_crtc_state *pipe_config)
2fa2fe9a
DV		 8758{
8759 struct drm_device *dev = crtc->base.dev;
8760 struct drm_i915_private *dev_priv = dev->dev_private;
8761 uint32_t tmp;
8762
8763 tmp = I915_READ(PF_CTL(crtc->pipe));
8764
8765 if (tmp & PF_ENABLE) {
fd4daa9c 8766 pipe_config->pch_pfit.enabled = true;
2fa2fe9a
DV		 8767 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
8768 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
cb8b2a30
DV		 8769
8770 /* We currently do not free assignements of panel fitters on
8771 * ivb/hsw (since we don't use the higher upscaling modes which
8772 * differentiates them) so just WARN about this case for now. */
8773 if (IS_GEN7(dev)) {
8774 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
8775 PF_PIPE_SEL_IVB(crtc->pipe));
8776 }
2fa2fe9a 8777 }
79e53945
JB		 8778}
8779
5724dbd1
DL		 8780static void
8781ironlake_get_initial_plane_config(struct intel_crtc *crtc,
8782 struct intel_initial_plane_config *plane_config)
4c6baa59
JB		 8783{
8784 struct drm_device *dev = crtc->base.dev;
8785 struct drm_i915_private *dev_priv = dev->dev_private;
8786 u32 val, base, offset;
aeee5a49 8787 int pipe = crtc->pipe;
4c6baa59 8788 int fourcc, pixel_format;
6761dd31 8789 unsigned int aligned_height;
b113d5ee 8790 struct drm_framebuffer *fb;
1b842c89 8791 struct intel_framebuffer *intel_fb;
4c6baa59 8792
42a7b088
DL		 8793 val = I915_READ(DSPCNTR(pipe));
8794 if (!(val & DISPLAY_PLANE_ENABLE))
8795 return;
8796
d9806c9f 8797 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 8798 if (!intel_fb) {
4c6baa59
JB		 8799 DRM_DEBUG_KMS("failed to alloc fb\n");
8800 return;
8801 }
8802
1b842c89
DL		 8803 fb = &intel_fb->base;
8804
18c5247e
DV		 8805 if (INTEL_INFO(dev)->gen >= 4) {
8806 if (val & DISPPLANE_TILED) {
49af449b 8807 plane_config->tiling = I915_TILING_X;
18c5247e
DV		 8808 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8809 }
8810 }
4c6baa59
JB		 8811
8812 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
b35d63fa 8813 fourcc = i9xx_format_to_fourcc(pixel_format);
b113d5ee
DL		 8814 fb->pixel_format = fourcc;
8815 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
4c6baa59 8816
aeee5a49 8817 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
4c6baa59 8818 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
aeee5a49 8819 offset = I915_READ(DSPOFFSET(pipe));
4c6baa59 8820 } else {
49af449b 8821 if (plane_config->tiling)
aeee5a49 8822 offset = I915_READ(DSPTILEOFF(pipe));
4c6baa59 8823 else
aeee5a49 8824 offset = I915_READ(DSPLINOFF(pipe));
4c6baa59
JB		 8825 }
8826 plane_config->base = base;
8827
8828 val = I915_READ(PIPESRC(pipe));
b113d5ee
DL		 8829 fb->width = ((val >> 16) & 0xfff) + 1;
8830 fb->height = ((val >> 0) & 0xfff) + 1;
4c6baa59
JB		 8831
8832 val = I915_READ(DSPSTRIDE(pipe));
b113d5ee 8833 fb->pitches[0] = val & 0xffffffc0;
4c6baa59 8834
b113d5ee 8835 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 8836 fb->pixel_format,
8837 fb->modifier[0]);
4c6baa59 8838
f37b5c2b 8839 plane_config->size = fb->pitches[0] * aligned_height;
4c6baa59 8840
2844a921
DL		 8841 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8842 pipe_name(pipe), fb->width, fb->height,
8843 fb->bits_per_pixel, base, fb->pitches[0],
8844 plane_config->size);
b113d5ee 8845
2d14030b 8846 plane_config->fb = intel_fb;
4c6baa59
JB		 8847}
8848
0e8ffe1b 8849static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5cec258b 8850 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 8851{
8852 struct drm_device *dev = crtc->base.dev;
8853 struct drm_i915_private *dev_priv = dev->dev_private;
8854 uint32_t tmp;
8855
f458ebbc
DV		 8856 if (!intel_display_power_is_enabled(dev_priv,
8857 POWER_DOMAIN_PIPE(crtc->pipe)))
930e8c9e
PZ		 8858 return false;
8859
e143a21c 8860 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 8861 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 8862
0e8ffe1b
DV		 8863 tmp = I915_READ(PIPECONF(crtc->pipe));
8864 if (!(tmp & PIPECONF_ENABLE))
8865 return false;
8866
42571aef
VS		 8867 switch (tmp & PIPECONF_BPC_MASK) {
8868 case PIPECONF_6BPC:
8869 pipe_config->pipe_bpp = 18;
8870 break;
8871 case PIPECONF_8BPC:
8872 pipe_config->pipe_bpp = 24;
8873 break;
8874 case PIPECONF_10BPC:
8875 pipe_config->pipe_bpp = 30;
8876 break;
8877 case PIPECONF_12BPC:
8878 pipe_config->pipe_bpp = 36;
8879 break;
8880 default:
8881 break;
8882 }
8883
b5a9fa09
DV		 8884 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
8885 pipe_config->limited_color_range = true;
8886
ab9412ba 8887 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
66e985c0
DV		 8888 struct intel_shared_dpll *pll;
8889
88adfff1
DV		 8890 pipe_config->has_pch_encoder = true;
8891
627eb5a3
DV		 8892 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
8893 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8894 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 8895
8896 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6c49f241 8897
c0d43d62 8898 if (HAS_PCH_IBX(dev_priv->dev)) {
d94ab068
DV		 8899 pipe_config->shared_dpll =
8900 (enum intel_dpll_id) crtc->pipe;
c0d43d62
DV		 8901 } else {
8902 tmp = I915_READ(PCH_DPLL_SEL);
8903 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
8904 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
8905 else
8906 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
8907 }
66e985c0
DV		 8908
8909 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
8910
8911 WARN_ON(!pll->get_hw_state(dev_priv, pll,
8912 &pipe_config->dpll_hw_state));
c93f54cf
DV		 8913
8914 tmp = pipe_config->dpll_hw_state.dpll;
8915 pipe_config->pixel_multiplier =
8916 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
8917 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
18442d08
VS		 8918
8919 ironlake_pch_clock_get(crtc, pipe_config);
6c49f241
DV		 8920 } else {
8921 pipe_config->pixel_multiplier = 1;
627eb5a3
DV		 8922 }
8923
1bd1bd80
DV		 8924 intel_get_pipe_timings(crtc, pipe_config);
8925
2fa2fe9a
DV		 8926 ironlake_get_pfit_config(crtc, pipe_config);
8927
0e8ffe1b
DV		 8928 return true;
8929}
8930
be256dc7
PZ		 8931static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
8932{
8933 struct drm_device *dev = dev_priv->dev;
be256dc7 8934 struct intel_crtc *crtc;
be256dc7 8935
d3fcc808 8936 for_each_intel_crtc(dev, crtc)
e2c719b7 8937 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
be256dc7
PZ		 8938 pipe_name(crtc->pipe));
8939
e2c719b7
RC		 8940 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
8941 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
8942 I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
8943 I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
8944 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
8945 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
be256dc7 8946 "CPU PWM1 enabled\n");
c5107b87 8947 if (IS_HASWELL(dev))
e2c719b7 8948 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
c5107b87 8949 "CPU PWM2 enabled\n");
e2c719b7 8950 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
be256dc7 8951 "PCH PWM1 enabled\n");
e2c719b7 8952 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
be256dc7 8953 "Utility pin enabled\n");
e2c719b7 8954 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
be256dc7 8955
9926ada1
PZ		 8956 /*
8957 * In theory we can still leave IRQs enabled, as long as only the HPD
8958 * interrupts remain enabled. We used to check for that, but since it's
8959 * gen-specific and since we only disable LCPLL after we fully disable
8960 * the interrupts, the check below should be enough.
8961 */
e2c719b7 8962 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
be256dc7
PZ		 8963}
8964
9ccd5aeb
PZ		 8965static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
8966{
8967 struct drm_device *dev = dev_priv->dev;
8968
8969 if (IS_HASWELL(dev))
8970 return I915_READ(D_COMP_HSW);
8971 else
8972 return I915_READ(D_COMP_BDW);
8973}
8974
3c4c9b81
PZ		 8975static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
8976{
8977 struct drm_device *dev = dev_priv->dev;
8978
8979 if (IS_HASWELL(dev)) {
8980 mutex_lock(&dev_priv->rps.hw_lock);
8981 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
8982 val))
f475dadf 8983 DRM_ERROR("Failed to write to D_COMP\n");
3c4c9b81
PZ		 8984 mutex_unlock(&dev_priv->rps.hw_lock);
8985 } else {
9ccd5aeb
PZ		 8986 I915_WRITE(D_COMP_BDW, val);
8987 POSTING_READ(D_COMP_BDW);
3c4c9b81 8988 }
be256dc7
PZ		 8989}
8990
8991/*
8992 * This function implements pieces of two sequences from BSpec:
8993 * - Sequence for display software to disable LCPLL
8994 * - Sequence for display software to allow package C8+
8995 * The steps implemented here are just the steps that actually touch the LCPLL
8996 * register. Callers should take care of disabling all the display engine
8997 * functions, doing the mode unset, fixing interrupts, etc.
8998 */
6ff58d53
PZ		 8999static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9000 bool switch_to_fclk, bool allow_power_down)
be256dc7
PZ		 9001{
9002 uint32_t val;
9003
9004 assert_can_disable_lcpll(dev_priv);
9005
9006 val = I915_READ(LCPLL_CTL);
9007
9008 if (switch_to_fclk) {
9009 val |= LCPLL_CD_SOURCE_FCLK;
9010 I915_WRITE(LCPLL_CTL, val);
9011
9012 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9013 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9014 DRM_ERROR("Switching to FCLK failed\n");
9015
9016 val = I915_READ(LCPLL_CTL);
9017 }
9018
9019 val |= LCPLL_PLL_DISABLE;
9020 I915_WRITE(LCPLL_CTL, val);
9021 POSTING_READ(LCPLL_CTL);
9022
9023 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9024 DRM_ERROR("LCPLL still locked\n");
9025
9ccd5aeb 9026 val = hsw_read_dcomp(dev_priv);
be256dc7 9027 val |= D_COMP_COMP_DISABLE;
3c4c9b81 9028 hsw_write_dcomp(dev_priv, val);
be256dc7
PZ		 9029 ndelay(100);
9030
9ccd5aeb
PZ		 9031 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9032 1))
be256dc7
PZ		 9033 DRM_ERROR("D_COMP RCOMP still in progress\n");
9034
9035 if (allow_power_down) {
9036 val = I915_READ(LCPLL_CTL);
9037 val |= LCPLL_POWER_DOWN_ALLOW;
9038 I915_WRITE(LCPLL_CTL, val);
9039 POSTING_READ(LCPLL_CTL);
9040 }
9041}
9042
9043/*
9044 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9045 * source.
9046 */
6ff58d53 9047static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
be256dc7
PZ		 9048{
9049 uint32_t val;
9050
9051 val = I915_READ(LCPLL_CTL);
9052
9053 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9054 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9055 return;
9056
a8a8bd54
PZ		 9057 /*
9058 * Make sure we're not on PC8 state before disabling PC8, otherwise
9059 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
a8a8bd54 9060 */
59bad947 9061 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
215733fa 9062
be256dc7
PZ		 9063 if (val & LCPLL_POWER_DOWN_ALLOW) {
9064 val &= ~LCPLL_POWER_DOWN_ALLOW;
9065 I915_WRITE(LCPLL_CTL, val);
35d8f2eb 9066 POSTING_READ(LCPLL_CTL);
be256dc7
PZ		 9067 }
9068
9ccd5aeb 9069 val = hsw_read_dcomp(dev_priv);
be256dc7
PZ		 9070 val |= D_COMP_COMP_FORCE;
9071 val &= ~D_COMP_COMP_DISABLE;
3c4c9b81 9072 hsw_write_dcomp(dev_priv, val);
be256dc7
PZ		 9073
9074 val = I915_READ(LCPLL_CTL);
9075 val &= ~LCPLL_PLL_DISABLE;
9076 I915_WRITE(LCPLL_CTL, val);
9077
9078 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9079 DRM_ERROR("LCPLL not locked yet\n");
9080
9081 if (val & LCPLL_CD_SOURCE_FCLK) {
9082 val = I915_READ(LCPLL_CTL);
9083 val &= ~LCPLL_CD_SOURCE_FCLK;
9084 I915_WRITE(LCPLL_CTL, val);
9085
9086 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9087 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9088 DRM_ERROR("Switching back to LCPLL failed\n");
9089 }
215733fa 9090
59bad947 9091 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
be256dc7
PZ		 9092}
9093
765dab67
PZ		 9094/*
9095 * Package states C8 and deeper are really deep PC states that can only be
9096 * reached when all the devices on the system allow it, so even if the graphics
9097 * device allows PC8+, it doesn't mean the system will actually get to these
9098 * states. Our driver only allows PC8+ when going into runtime PM.
9099 *
9100 * The requirements for PC8+ are that all the outputs are disabled, the power
9101 * well is disabled and most interrupts are disabled, and these are also
9102 * requirements for runtime PM. When these conditions are met, we manually do
9103 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9104 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9105 * hang the machine.
9106 *
9107 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9108 * the state of some registers, so when we come back from PC8+ we need to
9109 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9110 * need to take care of the registers kept by RC6. Notice that this happens even
9111 * if we don't put the device in PCI D3 state (which is what currently happens
9112 * because of the runtime PM support).
9113 *
9114 * For more, read "Display Sequences for Package C8" on the hardware
9115 * documentation.
9116 */
a14cb6fc 9117void hsw_enable_pc8(struct drm_i915_private *dev_priv)
c67a470b 9118{
c67a470b
PZ		 9119 struct drm_device *dev = dev_priv->dev;
9120 uint32_t val;
9121
c67a470b
PZ		 9122 DRM_DEBUG_KMS("Enabling package C8+\n");
9123
c67a470b
PZ		 9124 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9125 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9126 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9127 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9128 }
9129
9130 lpt_disable_clkout_dp(dev);
c67a470b
PZ		 9131 hsw_disable_lcpll(dev_priv, true, true);
9132}
9133
a14cb6fc 9134void hsw_disable_pc8(struct drm_i915_private *dev_priv)
c67a470b
PZ		 9135{
9136 struct drm_device *dev = dev_priv->dev;
9137 uint32_t val;
9138
c67a470b
PZ		 9139 DRM_DEBUG_KMS("Disabling package C8+\n");
9140
9141 hsw_restore_lcpll(dev_priv);
c67a470b
PZ		 9142 lpt_init_pch_refclk(dev);
9143
9144 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9145 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9146 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9147 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9148 }
9149
9150 intel_prepare_ddi(dev);
c67a470b
PZ		 9151}
9152
a821fc46 9153static void broxton_modeset_global_resources(struct drm_atomic_state *old_state)
f8437dd1 9154{
a821fc46 9155 struct drm_device *dev = old_state->dev;
f8437dd1 9156 struct drm_i915_private *dev_priv = dev->dev_private;
a821fc46 9157 int max_pixclk = intel_mode_max_pixclk(dev, NULL);
f8437dd1
VK		 9158 int req_cdclk;
9159
9160 /* see the comment in valleyview_modeset_global_resources */
9161 if (WARN_ON(max_pixclk < 0))
9162 return;
9163
9164 req_cdclk = broxton_calc_cdclk(dev_priv, max_pixclk);
9165
9166 if (req_cdclk != dev_priv->cdclk_freq)
9167 broxton_set_cdclk(dev, req_cdclk);
9168}
9169
190f68c5
ACO		 9170static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9171 struct intel_crtc_state *crtc_state)
09b4ddf9 9172{
190f68c5 9173 if (!intel_ddi_pll_select(crtc, crtc_state))
6441ab5f 9174 return -EINVAL;
716c2e55 9175
c7653199 9176 crtc->lowfreq_avail = false;
644cef34 9177
c8f7a0db 9178 return 0;
79e53945
JB		 9179}
9180
3760b59c
S		 9181static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9182 enum port port,
9183 struct intel_crtc_state *pipe_config)
9184{
9185 switch (port) {
9186 case PORT_A:
9187 pipe_config->ddi_pll_sel = SKL_DPLL0;
9188 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9189 break;
9190 case PORT_B:
9191 pipe_config->ddi_pll_sel = SKL_DPLL1;
9192 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9193 break;
9194 case PORT_C:
9195 pipe_config->ddi_pll_sel = SKL_DPLL2;
9196 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9197 break;
9198 default:
9199 DRM_ERROR("Incorrect port type\n");
9200 }
9201}
9202
96b7dfb7
S		 9203static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9204 enum port port,
5cec258b 9205 struct intel_crtc_state *pipe_config)
96b7dfb7 9206{
3148ade7 9207 u32 temp, dpll_ctl1;
96b7dfb7
S		 9208
9209 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9210 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9211
9212 switch (pipe_config->ddi_pll_sel) {
3148ade7
DL		 9213 case SKL_DPLL0:
9214 /*
9215 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9216 * of the shared DPLL framework and thus needs to be read out
9217 * separately
9218 */
9219 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9220 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9221 break;
96b7dfb7
S		 9222 case SKL_DPLL1:
9223 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9224 break;
9225 case SKL_DPLL2:
9226 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9227 break;
9228 case SKL_DPLL3:
9229 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9230 break;
96b7dfb7
S		 9231 }
9232}
9233
7d2c8175
DL		 9234static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9235 enum port port,
5cec258b 9236 struct intel_crtc_state *pipe_config)
7d2c8175
DL		 9237{
9238 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9239
9240 switch (pipe_config->ddi_pll_sel) {
9241 case PORT_CLK_SEL_WRPLL1:
9242 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9243 break;
9244 case PORT_CLK_SEL_WRPLL2:
9245 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9246 break;
9247 }
9248}
9249
26804afd 9250static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
5cec258b 9251 struct intel_crtc_state *pipe_config)
26804afd
DV		 9252{
9253 struct drm_device *dev = crtc->base.dev;
9254 struct drm_i915_private *dev_priv = dev->dev_private;
d452c5b6 9255 struct intel_shared_dpll *pll;
26804afd
DV		 9256 enum port port;
9257 uint32_t tmp;
9258
9259 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9260
9261 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9262
96b7dfb7
S		 9263 if (IS_SKYLAKE(dev))
9264 skylake_get_ddi_pll(dev_priv, port, pipe_config);
3760b59c
S		 9265 else if (IS_BROXTON(dev))
9266 bxt_get_ddi_pll(dev_priv, port, pipe_config);
96b7dfb7
S		 9267 else
9268 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9cd86933 9269
d452c5b6
DV		 9270 if (pipe_config->shared_dpll >= 0) {
9271 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9272
9273 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9274 &pipe_config->dpll_hw_state));
9275 }
9276
26804afd
DV		 9277 /*
9278 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9279 * DDI E. So just check whether this pipe is wired to DDI E and whether
9280 * the PCH transcoder is on.
9281 */
ca370455
DL		 9282 if (INTEL_INFO(dev)->gen < 9 &&
9283 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
26804afd
DV		 9284 pipe_config->has_pch_encoder = true;
9285
9286 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9287 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9288 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9289
9290 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9291 }
9292}
9293
0e8ffe1b 9294static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5cec258b 9295 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 9296{
9297 struct drm_device *dev = crtc->base.dev;
9298 struct drm_i915_private *dev_priv = dev->dev_private;
2fa2fe9a 9299 enum intel_display_power_domain pfit_domain;
0e8ffe1b
DV		 9300 uint32_t tmp;
9301
f458ebbc 9302 if (!intel_display_power_is_enabled(dev_priv,
b5482bd0
ID		 9303 POWER_DOMAIN_PIPE(crtc->pipe)))
9304 return false;
9305
e143a21c 9306 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62
DV		 9307 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9308
eccb140b
DV		 9309 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9310 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9311 enum pipe trans_edp_pipe;
9312 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9313 default:
9314 WARN(1, "unknown pipe linked to edp transcoder\n");
9315 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9316 case TRANS_DDI_EDP_INPUT_A_ON:
9317 trans_edp_pipe = PIPE_A;
9318 break;
9319 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9320 trans_edp_pipe = PIPE_B;
9321 break;
9322 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9323 trans_edp_pipe = PIPE_C;
9324 break;
9325 }
9326
9327 if (trans_edp_pipe == crtc->pipe)
9328 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9329 }
9330
f458ebbc 9331 if (!intel_display_power_is_enabled(dev_priv,
eccb140b 9332 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
2bfce950
PZ		 9333 return false;
9334
eccb140b 9335 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
0e8ffe1b
DV		 9336 if (!(tmp & PIPECONF_ENABLE))
9337 return false;
9338
26804afd 9339 haswell_get_ddi_port_state(crtc, pipe_config);
627eb5a3 9340
1bd1bd80
DV		 9341 intel_get_pipe_timings(crtc, pipe_config);
9342
a1b2278e
CK		 9343 if (INTEL_INFO(dev)->gen >= 9) {
9344 skl_init_scalers(dev, crtc, pipe_config);
9345 }
9346
2fa2fe9a 9347 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
af99ceda
CK		 9348
9349 if (INTEL_INFO(dev)->gen >= 9) {
9350 pipe_config->scaler_state.scaler_id = -1;
9351 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9352 }
9353
bd2e244f 9354 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
ff6d9f55 9355 if (INTEL_INFO(dev)->gen == 9)
bd2e244f 9356 skylake_get_pfit_config(crtc, pipe_config);
ff6d9f55 9357 else if (INTEL_INFO(dev)->gen < 9)
bd2e244f 9358 ironlake_get_pfit_config(crtc, pipe_config);
ff6d9f55
JB		 9359 else
9360 MISSING_CASE(INTEL_INFO(dev)->gen);
bd2e244f 9361 }
88adfff1 9362
e59150dc
JB		 9363 if (IS_HASWELL(dev))
9364 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9365 (I915_READ(IPS_CTL) & IPS_ENABLE);
42db64ef 9366
ebb69c95
CT		 9367 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
9368 pipe_config->pixel_multiplier =
9369 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9370 } else {
9371 pipe_config->pixel_multiplier = 1;
9372 }
6c49f241 9373
0e8ffe1b
DV		 9374 return true;
9375}
9376
560b85bb
CW		 9377static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
9378{
9379 struct drm_device *dev = crtc->dev;
9380 struct drm_i915_private *dev_priv = dev->dev_private;
9381 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
dc41c154 9382 uint32_t cntl = 0, size = 0;
560b85bb 9383
dc41c154 9384 if (base) {
3dd512fb
MR		 9385 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
9386 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
dc41c154
VS		 9387 unsigned int stride = roundup_pow_of_two(width) * 4;
9388
9389 switch (stride) {
9390 default:
9391 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9392 width, stride);
9393 stride = 256;
9394 /* fallthrough */
9395 case 256:
9396 case 512:
9397 case 1024:
9398 case 2048:
9399 break;
4b0e333e
CW		 9400 }
9401
dc41c154
VS		 9402 cntl |= CURSOR_ENABLE |
9403 CURSOR_GAMMA_ENABLE |
9404 CURSOR_FORMAT_ARGB |
9405 CURSOR_STRIDE(stride);
9406
9407 size = (height << 12) | width;
4b0e333e 9408 }
560b85bb 9409
dc41c154
VS		 9410 if (intel_crtc->cursor_cntl != 0 &&
9411 (intel_crtc->cursor_base != base ||
9412 intel_crtc->cursor_size != size ||
9413 intel_crtc->cursor_cntl != cntl)) {
9414 /* On these chipsets we can only modify the base/size/stride
9415 * whilst the cursor is disabled.
9416 */
9417 I915_WRITE(_CURACNTR, 0);
4b0e333e 9418 POSTING_READ(_CURACNTR);
dc41c154 9419 intel_crtc->cursor_cntl = 0;
4b0e333e 9420 }
560b85bb 9421
99d1f387 9422 if (intel_crtc->cursor_base != base) {
9db4a9c7 9423 I915_WRITE(_CURABASE, base);
99d1f387
VS		 9424 intel_crtc->cursor_base = base;
9425 }
4726e0b0 9426
dc41c154
VS		 9427 if (intel_crtc->cursor_size != size) {
9428 I915_WRITE(CURSIZE, size);
9429 intel_crtc->cursor_size = size;
4b0e333e 9430 }
560b85bb 9431
4b0e333e 9432 if (intel_crtc->cursor_cntl != cntl) {
4b0e333e
CW		 9433 I915_WRITE(_CURACNTR, cntl);
9434 POSTING_READ(_CURACNTR);
4b0e333e 9435 intel_crtc->cursor_cntl = cntl;
560b85bb 9436 }
560b85bb
CW		 9437}
9438
560b85bb 9439static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
65a21cd6
JB		 9440{
9441 struct drm_device *dev = crtc->dev;
9442 struct drm_i915_private *dev_priv = dev->dev_private;
9443 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9444 int pipe = intel_crtc->pipe;
4b0e333e
CW		 9445 uint32_t cntl;
9446
9447 cntl = 0;
9448 if (base) {
9449 cntl = MCURSOR_GAMMA_ENABLE;
3dd512fb 9450 switch (intel_crtc->base.cursor->state->crtc_w) {
4726e0b0
SK		 9451 case 64:
9452 cntl |= CURSOR_MODE_64_ARGB_AX;
9453 break;
9454 case 128:
9455 cntl |= CURSOR_MODE_128_ARGB_AX;
9456 break;
9457 case 256:
9458 cntl |= CURSOR_MODE_256_ARGB_AX;
9459 break;
9460 default:
3dd512fb 9461 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
4726e0b0 9462 return;
65a21cd6 9463 }
4b0e333e 9464 cntl |= pipe << 28; /* Connect to correct pipe */
47bf17a7
VS		 9465
9466 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
9467 cntl |= CURSOR_PIPE_CSC_ENABLE;
4b0e333e 9468 }
65a21cd6 9469
8e7d688b 9470 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
4398ad45
VS		 9471 cntl |= CURSOR_ROTATE_180;
9472
4b0e333e
CW		 9473 if (intel_crtc->cursor_cntl != cntl) {
9474 I915_WRITE(CURCNTR(pipe), cntl);
9475 POSTING_READ(CURCNTR(pipe));
9476 intel_crtc->cursor_cntl = cntl;
65a21cd6 9477 }
4b0e333e 9478
65a21cd6 9479 /* and commit changes on next vblank */
5efb3e28
VS		 9480 I915_WRITE(CURBASE(pipe), base);
9481 POSTING_READ(CURBASE(pipe));
99d1f387
VS		 9482
9483 intel_crtc->cursor_base = base;
65a21cd6
JB		 9484}
9485
cda4b7d3 9486/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 9487static void intel_crtc_update_cursor(struct drm_crtc *crtc,
9488 bool on)
cda4b7d3
CW		 9489{
9490 struct drm_device *dev = crtc->dev;
9491 struct drm_i915_private *dev_priv = dev->dev_private;
9492 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9493 int pipe = intel_crtc->pipe;
3d7d6510
MR		 9494 int x = crtc->cursor_x;
9495 int y = crtc->cursor_y;
d6e4db15 9496 u32 base = 0, pos = 0;
cda4b7d3 9497
d6e4db15 9498 if (on)
cda4b7d3 9499 base = intel_crtc->cursor_addr;
cda4b7d3 9500
6e3c9717 9501 if (x >= intel_crtc->config->pipe_src_w)
d6e4db15
VS		 9502 base = 0;
9503
6e3c9717 9504 if (y >= intel_crtc->config->pipe_src_h)
cda4b7d3
CW		 9505 base = 0;
9506
9507 if (x < 0) {
3dd512fb 9508 if (x + intel_crtc->base.cursor->state->crtc_w <= 0)
cda4b7d3
CW		 9509 base = 0;
9510
9511 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9512 x = -x;
9513 }
9514 pos |= x << CURSOR_X_SHIFT;
9515
9516 if (y < 0) {
3dd512fb 9517 if (y + intel_crtc->base.cursor->state->crtc_h <= 0)
cda4b7d3
CW		 9518 base = 0;
9519
9520 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
9521 y = -y;
9522 }
9523 pos |= y << CURSOR_Y_SHIFT;
9524
4b0e333e 9525 if (base == 0 && intel_crtc->cursor_base == 0)
cda4b7d3
CW		 9526 return;
9527
5efb3e28
VS		 9528 I915_WRITE(CURPOS(pipe), pos);
9529
4398ad45
VS		 9530 /* ILK+ do this automagically */
9531 if (HAS_GMCH_DISPLAY(dev) &&
8e7d688b 9532 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
3dd512fb
MR		 9533 base += (intel_crtc->base.cursor->state->crtc_h *
9534 intel_crtc->base.cursor->state->crtc_w - 1) * 4;
4398ad45
VS		 9535 }
9536
8ac54669 9537 if (IS_845G(dev) || IS_I865G(dev))
5efb3e28
VS		 9538 i845_update_cursor(crtc, base);
9539 else
9540 i9xx_update_cursor(crtc, base);
cda4b7d3
CW		 9541}
9542
dc41c154
VS		 9543static bool cursor_size_ok(struct drm_device *dev,
9544 uint32_t width, uint32_t height)
9545{
9546 if (width == 0 || height == 0)
9547 return false;
9548
9549 /*
9550 * 845g/865g are special in that they are only limited by
9551 * the width of their cursors, the height is arbitrary up to
9552 * the precision of the register. Everything else requires
9553 * square cursors, limited to a few power-of-two sizes.
9554 */
9555 if (IS_845G(dev) || IS_I865G(dev)) {
9556 if ((width & 63) != 0)
9557 return false;
9558
9559 if (width > (IS_845G(dev) ? 64 : 512))
9560 return false;
9561
9562 if (height > 1023)
9563 return false;
9564 } else {
9565 switch (width | height) {
9566 case 256:
9567 case 128:
9568 if (IS_GEN2(dev))
9569 return false;
9570 case 64:
9571 break;
9572 default:
9573 return false;
9574 }
9575 }
9576
9577 return true;
9578}
9579
79e53945 9580static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 9581 u16 *blue, uint32_t start, uint32_t size)
79e53945 9582{
7203425a 9583 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 9584 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 9585
7203425a 9586 for (i = start; i < end; i++) {
79e53945
JB		 9587 intel_crtc->lut_r[i] = red[i] >> 8;
9588 intel_crtc->lut_g[i] = green[i] >> 8;
9589 intel_crtc->lut_b[i] = blue[i] >> 8;
9590 }
9591
9592 intel_crtc_load_lut(crtc);
9593}
9594
79e53945
JB		 9595/* VESA 640x480x72Hz mode to set on the pipe */
9596static struct drm_display_mode load_detect_mode = {
9597 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
9598 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
9599};
9600
a8bb6818
DV		 9601struct drm_framebuffer *
9602__intel_framebuffer_create(struct drm_device *dev,
9603 struct drm_mode_fb_cmd2 *mode_cmd,
9604 struct drm_i915_gem_object *obj)
d2dff872
CW		 9605{
9606 struct intel_framebuffer *intel_fb;
9607 int ret;
9608
9609 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9610 if (!intel_fb) {
6ccb81f2 9611 drm_gem_object_unreference(&obj->base);
d2dff872
CW		 9612 return ERR_PTR(-ENOMEM);
9613 }
9614
9615 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
dd4916c5
DV		 9616 if (ret)
9617 goto err;
d2dff872
CW		 9618
9619 return &intel_fb->base;
dd4916c5 9620err:
6ccb81f2 9621 drm_gem_object_unreference(&obj->base);
dd4916c5
DV		 9622 kfree(intel_fb);
9623
9624 return ERR_PTR(ret);
d2dff872
CW		 9625}
9626
b5ea642a 9627static struct drm_framebuffer *
a8bb6818
DV		 9628intel_framebuffer_create(struct drm_device *dev,
9629 struct drm_mode_fb_cmd2 *mode_cmd,
9630 struct drm_i915_gem_object *obj)
9631{
9632 struct drm_framebuffer *fb;
9633 int ret;
9634
9635 ret = i915_mutex_lock_interruptible(dev);
9636 if (ret)
9637 return ERR_PTR(ret);
9638 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
9639 mutex_unlock(&dev->struct_mutex);
9640
9641 return fb;
9642}
9643
d2dff872
CW		 9644static u32
9645intel_framebuffer_pitch_for_width(int width, int bpp)
9646{
9647 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
9648 return ALIGN(pitch, 64);
9649}
9650
9651static u32
9652intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
9653{
9654 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
1267a26b 9655 return PAGE_ALIGN(pitch * mode->vdisplay);
d2dff872
CW		 9656}
9657
9658static struct drm_framebuffer *
9659intel_framebuffer_create_for_mode(struct drm_device *dev,
9660 struct drm_display_mode *mode,
9661 int depth, int bpp)
9662{
9663 struct drm_i915_gem_object *obj;
0fed39bd 9664 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 9665
9666 obj = i915_gem_alloc_object(dev,
9667 intel_framebuffer_size_for_mode(mode, bpp));
9668 if (obj == NULL)
9669 return ERR_PTR(-ENOMEM);
9670
9671 mode_cmd.width = mode->hdisplay;
9672 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 9673 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
9674 bpp);
5ca0c34a 9675 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 9676
9677 return intel_framebuffer_create(dev, &mode_cmd, obj);
9678}
9679
9680static struct drm_framebuffer *
9681mode_fits_in_fbdev(struct drm_device *dev,
9682 struct drm_display_mode *mode)
9683{
4520f53a 9684#ifdef CONFIG_DRM_I915_FBDEV
d2dff872
CW		 9685 struct drm_i915_private *dev_priv = dev->dev_private;
9686 struct drm_i915_gem_object *obj;
9687 struct drm_framebuffer *fb;
9688
4c0e5528 9689 if (!dev_priv->fbdev)
d2dff872
CW		 9690 return NULL;
9691
4c0e5528 9692 if (!dev_priv->fbdev->fb)
d2dff872
CW		 9693 return NULL;
9694
4c0e5528
DV		 9695 obj = dev_priv->fbdev->fb->obj;
9696 BUG_ON(!obj);
9697
8bcd4553 9698 fb = &dev_priv->fbdev->fb->base;
01f2c773
VS		 9699 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
9700 fb->bits_per_pixel))
d2dff872
CW		 9701 return NULL;
9702
01f2c773 9703 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 9704 return NULL;
9705
9706 return fb;
4520f53a
DV		 9707#else
9708 return NULL;
9709#endif
d2dff872
CW		 9710}
9711
d3a40d1b
ACO		 9712static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
9713 struct drm_crtc *crtc,
9714 struct drm_display_mode *mode,
9715 struct drm_framebuffer *fb,
9716 int x, int y)
9717{
9718 struct drm_plane_state *plane_state;
9719 int hdisplay, vdisplay;
9720 int ret;
9721
9722 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
9723 if (IS_ERR(plane_state))
9724 return PTR_ERR(plane_state);
9725
9726 if (mode)
9727 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
9728 else
9729 hdisplay = vdisplay = 0;
9730
9731 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
9732 if (ret)
9733 return ret;
9734 drm_atomic_set_fb_for_plane(plane_state, fb);
9735 plane_state->crtc_x = 0;
9736 plane_state->crtc_y = 0;
9737 plane_state->crtc_w = hdisplay;
9738 plane_state->crtc_h = vdisplay;
9739 plane_state->src_x = x << 16;
9740 plane_state->src_y = y << 16;
9741 plane_state->src_w = hdisplay << 16;
9742 plane_state->src_h = vdisplay << 16;
9743
9744 return 0;
9745}
9746
d2434ab7 9747bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 9748 struct drm_display_mode *mode,
51fd371b
RC		 9749 struct intel_load_detect_pipe *old,
9750 struct drm_modeset_acquire_ctx *ctx)
79e53945
JB		 9751{
9752 struct intel_crtc *intel_crtc;
d2434ab7
DV		 9753 struct intel_encoder *intel_encoder =
9754 intel_attached_encoder(connector);
79e53945 9755 struct drm_crtc *possible_crtc;
4ef69c7a 9756 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 9757 struct drm_crtc *crtc = NULL;
9758 struct drm_device *dev = encoder->dev;
94352cf9 9759 struct drm_framebuffer *fb;
51fd371b 9760 struct drm_mode_config *config = &dev->mode_config;
83a57153 9761 struct drm_atomic_state *state = NULL;
944b0c76 9762 struct drm_connector_state *connector_state;
4be07317 9763 struct intel_crtc_state *crtc_state;
51fd371b 9764 int ret, i = -1;
79e53945 9765
d2dff872 9766 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
c23cc417 9767 connector->base.id, connector->name,
8e329a03 9768 encoder->base.id, encoder->name);
d2dff872 9769
51fd371b
RC		 9770retry:
9771 ret = drm_modeset_lock(&config->connection_mutex, ctx);
9772 if (ret)
9773 goto fail_unlock;
6e9f798d 9774
79e53945
JB		 9775 /*
9776 * Algorithm gets a little messy:
7a5e4805 9777 *
79e53945
JB		 9778 * - if the connector already has an assigned crtc, use it (but make
9779 * sure it's on first)
7a5e4805 9780 *
79e53945
JB		 9781 * - try to find the first unused crtc that can drive this connector,
9782 * and use that if we find one
79e53945
JB		 9783 */
9784
9785 /* See if we already have a CRTC for this connector */
9786 if (encoder->crtc) {
9787 crtc = encoder->crtc;
8261b191 9788
51fd371b 9789 ret = drm_modeset_lock(&crtc->mutex, ctx);
4d02e2de
DV		 9790 if (ret)
9791 goto fail_unlock;
9792 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
51fd371b
RC		 9793 if (ret)
9794 goto fail_unlock;
7b24056b 9795
24218aac 9796 old->dpms_mode = connector->dpms;
8261b191
CW		 9797 old->load_detect_temp = false;
9798
9799 /* Make sure the crtc and connector are running */
24218aac
DV		 9800 if (connector->dpms != DRM_MODE_DPMS_ON)
9801 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 9802
7173188d 9803 return true;
79e53945
JB		 9804 }
9805
9806 /* Find an unused one (if possible) */
70e1e0ec 9807 for_each_crtc(dev, possible_crtc) {
79e53945
JB		 9808 i++;
9809 if (!(encoder->possible_crtcs & (1 << i)))
9810 continue;
83d65738 9811 if (possible_crtc->state->enable)
a459249c
VS		 9812 continue;
9813 /* This can occur when applying the pipe A quirk on resume. */
9814 if (to_intel_crtc(possible_crtc)->new_enabled)
9815 continue;
9816
9817 crtc = possible_crtc;
9818 break;
79e53945
JB		 9819 }
9820
9821 /*
9822 * If we didn't find an unused CRTC, don't use any.
9823 */
9824 if (!crtc) {
7173188d 9825 DRM_DEBUG_KMS("no pipe available for load-detect\n");
51fd371b 9826 goto fail_unlock;
79e53945
JB		 9827 }
9828
51fd371b
RC		 9829 ret = drm_modeset_lock(&crtc->mutex, ctx);
9830 if (ret)
4d02e2de
DV		 9831 goto fail_unlock;
9832 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
9833 if (ret)
51fd371b 9834 goto fail_unlock;
fc303101
DV		 9835 intel_encoder->new_crtc = to_intel_crtc(crtc);
9836 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 9837
9838 intel_crtc = to_intel_crtc(crtc);
412b61d8 9839 intel_crtc->new_enabled = true;
24218aac 9840 old->dpms_mode = connector->dpms;
8261b191 9841 old->load_detect_temp = true;
d2dff872 9842 old->release_fb = NULL;
79e53945 9843
83a57153
ACO		 9844 state = drm_atomic_state_alloc(dev);
9845 if (!state)
9846 return false;
9847
9848 state->acquire_ctx = ctx;
9849
944b0c76
ACO		 9850 connector_state = drm_atomic_get_connector_state(state, connector);
9851 if (IS_ERR(connector_state)) {
9852 ret = PTR_ERR(connector_state);
9853 goto fail;
9854 }
9855
9856 connector_state->crtc = crtc;
9857 connector_state->best_encoder = &intel_encoder->base;
9858
4be07317
ACO		 9859 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9860 if (IS_ERR(crtc_state)) {
9861 ret = PTR_ERR(crtc_state);
9862 goto fail;
9863 }
9864
49d6fa21 9865 crtc_state->base.active = crtc_state->base.enable = true;
4be07317 9866
6492711d
CW		 9867 if (!mode)
9868 mode = &load_detect_mode;
79e53945 9869
d2dff872
CW		 9870 /* We need a framebuffer large enough to accommodate all accesses
9871 * that the plane may generate whilst we perform load detection.
9872 * We can not rely on the fbcon either being present (we get called
9873 * during its initialisation to detect all boot displays, or it may
9874 * not even exist) or that it is large enough to satisfy the
9875 * requested mode.
9876 */
94352cf9
DV		 9877 fb = mode_fits_in_fbdev(dev, mode);
9878 if (fb == NULL) {
d2dff872 9879 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 9880 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
9881 old->release_fb = fb;
d2dff872
CW		 9882 } else
9883 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 9884 if (IS_ERR(fb)) {
d2dff872 9885 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
412b61d8 9886 goto fail;
79e53945 9887 }
79e53945 9888
d3a40d1b
ACO		 9889 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
9890 if (ret)
9891 goto fail;
9892
8c7b5ccb
ACO		 9893 drm_mode_copy(&crtc_state->base.mode, mode);
9894
9895 if (intel_set_mode(crtc, state)) {
6492711d 9896 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 9897 if (old->release_fb)
9898 old->release_fb->funcs->destroy(old->release_fb);
412b61d8 9899 goto fail;
79e53945 9900 }
9128b040 9901 crtc->primary->crtc = crtc;
7173188d 9902
79e53945 9903 /* let the connector get through one full cycle before testing */
9d0498a2 9904 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 9905 return true;
412b61d8
VS		 9906
9907 fail:
83d65738 9908 intel_crtc->new_enabled = crtc->state->enable;
51fd371b 9909fail_unlock:
e5d958ef
ACO		 9910 drm_atomic_state_free(state);
9911 state = NULL;
83a57153 9912
51fd371b
RC		 9913 if (ret == -EDEADLK) {
9914 drm_modeset_backoff(ctx);
9915 goto retry;
9916 }
9917
412b61d8 9918 return false;
79e53945
JB		 9919}
9920
d2434ab7 9921void intel_release_load_detect_pipe(struct drm_connector *connector,
49172fee
ACO		 9922 struct intel_load_detect_pipe *old,
9923 struct drm_modeset_acquire_ctx *ctx)
79e53945 9924{
83a57153 9925 struct drm_device *dev = connector->dev;
d2434ab7
DV		 9926 struct intel_encoder *intel_encoder =
9927 intel_attached_encoder(connector);
4ef69c7a 9928 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 9929 struct drm_crtc *crtc = encoder->crtc;
412b61d8 9930 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83a57153 9931 struct drm_atomic_state *state;
944b0c76 9932 struct drm_connector_state *connector_state;
4be07317 9933 struct intel_crtc_state *crtc_state;
d3a40d1b 9934 int ret;
79e53945 9935
d2dff872 9936 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
c23cc417 9937 connector->base.id, connector->name,
8e329a03 9938 encoder->base.id, encoder->name);
d2dff872 9939
8261b191 9940 if (old->load_detect_temp) {
83a57153 9941 state = drm_atomic_state_alloc(dev);
944b0c76
ACO		 9942 if (!state)
9943 goto fail;
83a57153
ACO		 9944
9945 state->acquire_ctx = ctx;
9946
944b0c76
ACO		 9947 connector_state = drm_atomic_get_connector_state(state, connector);
9948 if (IS_ERR(connector_state))
9949 goto fail;
9950
4be07317
ACO		 9951 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9952 if (IS_ERR(crtc_state))
9953 goto fail;
9954
fc303101
DV		 9955 to_intel_connector(connector)->new_encoder = NULL;
9956 intel_encoder->new_crtc = NULL;
412b61d8 9957 intel_crtc->new_enabled = false;
944b0c76
ACO		 9958
9959 connector_state->best_encoder = NULL;
9960 connector_state->crtc = NULL;
9961
49d6fa21 9962 crtc_state->base.enable = crtc_state->base.active = false;
4be07317 9963
d3a40d1b
ACO		 9964 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
9965 0, 0);
9966 if (ret)
9967 goto fail;
9968
2bfb4627
ACO		 9969 ret = intel_set_mode(crtc, state);
9970 if (ret)
9971 goto fail;
d2dff872 9972
36206361
DV		 9973 if (old->release_fb) {
9974 drm_framebuffer_unregister_private(old->release_fb);
9975 drm_framebuffer_unreference(old->release_fb);
9976 }
d2dff872 9977
0622a53c 9978 return;
79e53945
JB		 9979 }
9980
c751ce4f 9981 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 9982 if (old->dpms_mode != DRM_MODE_DPMS_ON)
9983 connector->funcs->dpms(connector, old->dpms_mode);
944b0c76
ACO		 9984
9985 return;
9986fail:
9987 DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
9988 drm_atomic_state_free(state);
79e53945
JB		 9989}
9990
da4a1efa 9991static int i9xx_pll_refclk(struct drm_device *dev,
5cec258b 9992 const struct intel_crtc_state *pipe_config)
da4a1efa
VS		 9993{
9994 struct drm_i915_private *dev_priv = dev->dev_private;
9995 u32 dpll = pipe_config->dpll_hw_state.dpll;
9996
9997 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
e91e941b 9998 return dev_priv->vbt.lvds_ssc_freq;
da4a1efa
VS		 9999 else if (HAS_PCH_SPLIT(dev))
10000 return 120000;
10001 else if (!IS_GEN2(dev))
10002 return 96000;
10003 else
10004 return 48000;
10005}
10006
79e53945 10007/* Returns the clock of the currently programmed mode of the given pipe. */
f1f644dc 10008static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 10009 struct intel_crtc_state *pipe_config)
79e53945 10010{
f1f644dc 10011 struct drm_device *dev = crtc->base.dev;
79e53945 10012 struct drm_i915_private *dev_priv = dev->dev_private;
f1f644dc 10013 int pipe = pipe_config->cpu_transcoder;
293623f7 10014 u32 dpll = pipe_config->dpll_hw_state.dpll;
79e53945
JB		 10015 u32 fp;
10016 intel_clock_t clock;
da4a1efa 10017 int refclk = i9xx_pll_refclk(dev, pipe_config);
79e53945
JB		 10018
10019 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
293623f7 10020 fp = pipe_config->dpll_hw_state.fp0;
79e53945 10021 else
293623f7 10022 fp = pipe_config->dpll_hw_state.fp1;
79e53945
JB		 10023
10024 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 10025 if (IS_PINEVIEW(dev)) {
10026 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10027 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 10028 } else {
10029 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10030 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10031 }
10032
a6c45cf0 10033 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 10034 if (IS_PINEVIEW(dev))
10035 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10036 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 10037 else
10038 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 10039 DPLL_FPA01_P1_POST_DIV_SHIFT);
10040
10041 switch (dpll & DPLL_MODE_MASK) {
10042 case DPLLB_MODE_DAC_SERIAL:
10043 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10044 5 : 10;
10045 break;
10046 case DPLLB_MODE_LVDS:
10047 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10048 7 : 14;
10049 break;
10050 default:
28c97730 10051 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945 10052 "mode\n", (int)(dpll & DPLL_MODE_MASK));
f1f644dc 10053 return;
79e53945
JB		 10054 }
10055
ac58c3f0 10056 if (IS_PINEVIEW(dev))
da4a1efa 10057 pineview_clock(refclk, &clock);
ac58c3f0 10058 else
da4a1efa 10059 i9xx_clock(refclk, &clock);
79e53945 10060 } else {
0fb58223 10061 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
b1c560d1 10062 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
79e53945
JB		 10063
10064 if (is_lvds) {
10065 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10066 DPLL_FPA01_P1_POST_DIV_SHIFT);
b1c560d1
VS		 10067
10068 if (lvds & LVDS_CLKB_POWER_UP)
10069 clock.p2 = 7;
10070 else
10071 clock.p2 = 14;
79e53945
JB		 10072 } else {
10073 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10074 clock.p1 = 2;
10075 else {
10076 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10077 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10078 }
10079 if (dpll & PLL_P2_DIVIDE_BY_4)
10080 clock.p2 = 4;
10081 else
10082 clock.p2 = 2;
79e53945 10083 }
da4a1efa
VS		 10084
10085 i9xx_clock(refclk, &clock);
79e53945
JB		 10086 }
10087
18442d08
VS		 10088 /*
10089 * This value includes pixel_multiplier. We will use
241bfc38 10090 * port_clock to compute adjusted_mode.crtc_clock in the
18442d08
VS		 10091 * encoder's get_config() function.
10092 */
10093 pipe_config->port_clock = clock.dot;
f1f644dc
JB		 10094}
10095
6878da05
VS		 10096int intel_dotclock_calculate(int link_freq,
10097 const struct intel_link_m_n *m_n)
f1f644dc 10098{
f1f644dc
JB		 10099 /*
10100 * The calculation for the data clock is:
1041a02f 10101 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
f1f644dc 10102 * But we want to avoid losing precison if possible, so:
1041a02f 10103 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
f1f644dc
JB		 10104 *
10105 * and the link clock is simpler:
1041a02f 10106 * link_clock = (m * link_clock) / n
f1f644dc
JB		 10107 */
10108
6878da05
VS		 10109 if (!m_n->link_n)
10110 return 0;
f1f644dc 10111
6878da05
VS		 10112 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10113}
f1f644dc 10114
18442d08 10115static void ironlake_pch_clock_get(struct intel_crtc *crtc,
5cec258b 10116 struct intel_crtc_state *pipe_config)
6878da05
VS		 10117{
10118 struct drm_device *dev = crtc->base.dev;
79e53945 10119
18442d08
VS		 10120 /* read out port_clock from the DPLL */
10121 i9xx_crtc_clock_get(crtc, pipe_config);
f1f644dc 10122
f1f644dc 10123 /*
18442d08 10124 * This value does not include pixel_multiplier.
241bfc38 10125 * We will check that port_clock and adjusted_mode.crtc_clock
18442d08
VS		 10126 * agree once we know their relationship in the encoder's
10127 * get_config() function.
79e53945 10128 */
2d112de7 10129 pipe_config->base.adjusted_mode.crtc_clock =
18442d08
VS		 10130 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10131 &pipe_config->fdi_m_n);
79e53945
JB		 10132}
10133
10134/** Returns the currently programmed mode of the given pipe. */
10135struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10136 struct drm_crtc *crtc)
10137{
548f245b 10138 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 10139 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 10140 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
79e53945 10141 struct drm_display_mode *mode;
5cec258b 10142 struct intel_crtc_state pipe_config;
fe2b8f9d
PZ		 10143 int htot = I915_READ(HTOTAL(cpu_transcoder));
10144 int hsync = I915_READ(HSYNC(cpu_transcoder));
10145 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10146 int vsync = I915_READ(VSYNC(cpu_transcoder));
293623f7 10147 enum pipe pipe = intel_crtc->pipe;
79e53945
JB		 10148
10149 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10150 if (!mode)
10151 return NULL;
10152
f1f644dc
JB		 10153 /*
10154 * Construct a pipe_config sufficient for getting the clock info
10155 * back out of crtc_clock_get.
10156 *
10157 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10158 * to use a real value here instead.
10159 */
293623f7 10160 pipe_config.cpu_transcoder = (enum transcoder) pipe;
f1f644dc 10161 pipe_config.pixel_multiplier = 1;
293623f7
VS		 10162 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10163 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10164 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
f1f644dc
JB		 10165 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10166
773ae034 10167 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
79e53945
JB		 10168 mode->hdisplay = (htot & 0xffff) + 1;
10169 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10170 mode->hsync_start = (hsync & 0xffff) + 1;
10171 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10172 mode->vdisplay = (vtot & 0xffff) + 1;
10173 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10174 mode->vsync_start = (vsync & 0xffff) + 1;
10175 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10176
10177 drm_mode_set_name(mode);
79e53945
JB		 10178
10179 return mode;
10180}
10181
652c393a
JB		 10182static void intel_decrease_pllclock(struct drm_crtc *crtc)
10183{
10184 struct drm_device *dev = crtc->dev;
fbee40df 10185 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 10186 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 10187
baff296c 10188 if (!HAS_GMCH_DISPLAY(dev))
652c393a
JB		 10189 return;
10190
10191 if (!dev_priv->lvds_downclock_avail)
10192 return;
10193
10194 /*
10195 * Since this is called by a timer, we should never get here in
10196 * the manual case.
10197 */
10198 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 10199 int pipe = intel_crtc->pipe;
10200 int dpll_reg = DPLL(pipe);
10201 int dpll;
f6e5b160 10202
44d98a61 10203 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 10204
8ac5a6d5 10205 assert_panel_unlocked(dev_priv, pipe);
652c393a 10206
dc257cf1 10207 dpll = I915_READ(dpll_reg);
652c393a
JB		 10208 dpll |= DISPLAY_RATE_SELECT_FPA1;
10209 I915_WRITE(dpll_reg, dpll);
9d0498a2 10210 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 10211 dpll = I915_READ(dpll_reg);
10212 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 10213 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 10214 }
10215
10216}
10217
f047e395
CW		 10218void intel_mark_busy(struct drm_device *dev)
10219{
c67a470b
PZ		 10220 struct drm_i915_private *dev_priv = dev->dev_private;
10221
f62a0076
CW		 10222 if (dev_priv->mm.busy)
10223 return;
10224
43694d69 10225 intel_runtime_pm_get(dev_priv);
c67a470b 10226 i915_update_gfx_val(dev_priv);
43cf3bf0
CW		 10227 if (INTEL_INFO(dev)->gen >= 6)
10228 gen6_rps_busy(dev_priv);
f62a0076 10229 dev_priv->mm.busy = true;
f047e395
CW		 10230}
10231
10232void intel_mark_idle(struct drm_device *dev)
652c393a 10233{
c67a470b 10234 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 10235 struct drm_crtc *crtc;
652c393a 10236
f62a0076
CW		 10237 if (!dev_priv->mm.busy)
10238 return;
10239
10240 dev_priv->mm.busy = false;
10241
70e1e0ec 10242 for_each_crtc(dev, crtc) {
f4510a27 10243 if (!crtc->primary->fb)
652c393a
JB		 10244 continue;
10245
725a5b54 10246 intel_decrease_pllclock(crtc);
652c393a 10247 }
b29c19b6 10248
3d13ef2e 10249 if (INTEL_INFO(dev)->gen >= 6)
b29c19b6 10250 gen6_rps_idle(dev->dev_private);
bb4cdd53 10251
43694d69 10252 intel_runtime_pm_put(dev_priv);
652c393a
JB		 10253}
10254
79e53945
JB		 10255static void intel_crtc_destroy(struct drm_crtc *crtc)
10256{
10257 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 10258 struct drm_device *dev = crtc->dev;
10259 struct intel_unpin_work *work;
67e77c5a 10260
5e2d7afc 10261 spin_lock_irq(&dev->event_lock);
67e77c5a
DV		 10262 work = intel_crtc->unpin_work;
10263 intel_crtc->unpin_work = NULL;
5e2d7afc 10264 spin_unlock_irq(&dev->event_lock);
67e77c5a
DV		 10265
10266 if (work) {
10267 cancel_work_sync(&work->work);
10268 kfree(work);
10269 }
79e53945
JB		 10270
10271 drm_crtc_cleanup(crtc);
67e77c5a 10272
79e53945
JB		 10273 kfree(intel_crtc);
10274}
10275
6b95a207
KH		 10276static void intel_unpin_work_fn(struct work_struct *__work)
10277{
10278 struct intel_unpin_work *work =
10279 container_of(__work, struct intel_unpin_work, work);
b4a98e57 10280 struct drm_device *dev = work->crtc->dev;
f99d7069 10281 enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
6b95a207 10282
b4a98e57 10283 mutex_lock(&dev->struct_mutex);
82bc3b2d 10284 intel_unpin_fb_obj(work->old_fb, work->crtc->primary->state);
05394f39 10285 drm_gem_object_unreference(&work->pending_flip_obj->base);
d9e86c0e 10286
7ff0ebcc 10287 intel_fbc_update(dev);
f06cc1b9
JH		 10288
10289 if (work->flip_queued_req)
146d84f0 10290 i915_gem_request_assign(&work->flip_queued_req, NULL);
b4a98e57
CW		 10291 mutex_unlock(&dev->struct_mutex);
10292
f99d7069 10293 intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
89ed88ba 10294 drm_framebuffer_unreference(work->old_fb);
f99d7069 10295
b4a98e57
CW		 10296 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
10297 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
10298
6b95a207
KH		 10299 kfree(work);
10300}
10301
1afe3e9d 10302static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 10303 struct drm_crtc *crtc)
6b95a207 10304{
6b95a207
KH		 10305 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10306 struct intel_unpin_work *work;
6b95a207
KH		 10307 unsigned long flags;
10308
10309 /* Ignore early vblank irqs */
10310 if (intel_crtc == NULL)
10311 return;
10312
f326038a
DV		 10313 /*
10314 * This is called both by irq handlers and the reset code (to complete
10315 * lost pageflips) so needs the full irqsave spinlocks.
10316 */
6b95a207
KH		 10317 spin_lock_irqsave(&dev->event_lock, flags);
10318 work = intel_crtc->unpin_work;
e7d841ca
CW		 10319
10320 /* Ensure we don't miss a work->pending update ... */
10321 smp_rmb();
10322
10323 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 10324 spin_unlock_irqrestore(&dev->event_lock, flags);
10325 return;
10326 }
10327
d6bbafa1 10328 page_flip_completed(intel_crtc);
0af7e4df 10329
6b95a207 10330 spin_unlock_irqrestore(&dev->event_lock, flags);
6b95a207
KH		 10331}
10332
1afe3e9d
JB		 10333void intel_finish_page_flip(struct drm_device *dev, int pipe)
10334{
fbee40df 10335 struct drm_i915_private *dev_priv = dev->dev_private;
1afe3e9d
JB		 10336 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10337
49b14a5c 10338 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 10339}
10340
10341void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10342{
fbee40df 10343 struct drm_i915_private *dev_priv = dev->dev_private;
1afe3e9d
JB		 10344 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10345
49b14a5c 10346 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 10347}
10348
75f7f3ec
VS		 10349/* Is 'a' after or equal to 'b'? */
10350static bool g4x_flip_count_after_eq(u32 a, u32 b)
10351{
10352 return !((a - b) & 0x80000000);
10353}
10354
10355static bool page_flip_finished(struct intel_crtc *crtc)
10356{
10357 struct drm_device *dev = crtc->base.dev;
10358 struct drm_i915_private *dev_priv = dev->dev_private;
10359
bdfa7542
VS		 10360 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10361 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10362 return true;
10363
75f7f3ec
VS		 10364 /*
10365 * The relevant registers doen't exist on pre-ctg.
10366 * As the flip done interrupt doesn't trigger for mmio
10367 * flips on gmch platforms, a flip count check isn't
10368 * really needed there. But since ctg has the registers,
10369 * include it in the check anyway.
10370 */
10371 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10372 return true;
10373
10374 /*
10375 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10376 * used the same base address. In that case the mmio flip might
10377 * have completed, but the CS hasn't even executed the flip yet.
10378 *
10379 * A flip count check isn't enough as the CS might have updated
10380 * the base address just after start of vblank, but before we
10381 * managed to process the interrupt. This means we'd complete the
10382 * CS flip too soon.
10383 *
10384 * Combining both checks should get us a good enough result. It may
10385 * still happen that the CS flip has been executed, but has not
10386 * yet actually completed. But in case the base address is the same
10387 * anyway, we don't really care.
10388 */
10389 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10390 crtc->unpin_work->gtt_offset &&
10391 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
10392 crtc->unpin_work->flip_count);
10393}
10394
6b95a207
KH		 10395void intel_prepare_page_flip(struct drm_device *dev, int plane)
10396{
fbee40df 10397 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 10398 struct intel_crtc *intel_crtc =
10399 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10400 unsigned long flags;
10401
f326038a
DV		 10402
10403 /*
10404 * This is called both by irq handlers and the reset code (to complete
10405 * lost pageflips) so needs the full irqsave spinlocks.
10406 *
10407 * NB: An MMIO update of the plane base pointer will also
e7d841ca
CW		 10408 * generate a page-flip completion irq, i.e. every modeset
10409 * is also accompanied by a spurious intel_prepare_page_flip().
10410 */
6b95a207 10411 spin_lock_irqsave(&dev->event_lock, flags);
75f7f3ec 10412 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
e7d841ca 10413 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 10414 spin_unlock_irqrestore(&dev->event_lock, flags);
10415}
10416
eba905b2 10417static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
e7d841ca
CW		 10418{
10419 /* Ensure that the work item is consistent when activating it ... */
10420 smp_wmb();
10421 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
10422 /* and that it is marked active as soon as the irq could fire. */
10423 smp_wmb();
10424}
10425
8c9f3aaf
JB		 10426static int intel_gen2_queue_flip(struct drm_device *dev,
10427 struct drm_crtc *crtc,
10428 struct drm_framebuffer *fb,
ed8d1975 10429 struct drm_i915_gem_object *obj,
a4872ba6 10430 struct intel_engine_cs *ring,
ed8d1975 10431 uint32_t flags)
8c9f3aaf 10432{
8c9f3aaf 10433 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf
JB		 10434 u32 flip_mask;
10435 int ret;
10436
6d90c952 10437 ret = intel_ring_begin(ring, 6);
8c9f3aaf 10438 if (ret)
4fa62c89 10439 return ret;
8c9f3aaf
JB		 10440
10441 /* Can't queue multiple flips, so wait for the previous
10442 * one to finish before executing the next.
10443 */
10444 if (intel_crtc->plane)
10445 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10446 else
10447 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 10448 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10449 intel_ring_emit(ring, MI_NOOP);
10450 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10451 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10452 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 10453 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
6d90c952 10454 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 10455
10456 intel_mark_page_flip_active(intel_crtc);
09246732 10457 __intel_ring_advance(ring);
83d4092b 10458 return 0;
8c9f3aaf
JB		 10459}
10460
10461static int intel_gen3_queue_flip(struct drm_device *dev,
10462 struct drm_crtc *crtc,
10463 struct drm_framebuffer *fb,
ed8d1975 10464 struct drm_i915_gem_object *obj,
a4872ba6 10465 struct intel_engine_cs *ring,
ed8d1975 10466 uint32_t flags)
8c9f3aaf 10467{
8c9f3aaf 10468 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf
JB		 10469 u32 flip_mask;
10470 int ret;
10471
6d90c952 10472 ret = intel_ring_begin(ring, 6);
8c9f3aaf 10473 if (ret)
4fa62c89 10474 return ret;
8c9f3aaf
JB		 10475
10476 if (intel_crtc->plane)
10477 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10478 else
10479 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 10480 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10481 intel_ring_emit(ring, MI_NOOP);
10482 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
10483 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10484 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 10485 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
6d90c952
DV		 10486 intel_ring_emit(ring, MI_NOOP);
10487
e7d841ca 10488 intel_mark_page_flip_active(intel_crtc);
09246732 10489 __intel_ring_advance(ring);
83d4092b 10490 return 0;
8c9f3aaf
JB		 10491}
10492
10493static int intel_gen4_queue_flip(struct drm_device *dev,
10494 struct drm_crtc *crtc,
10495 struct drm_framebuffer *fb,
ed8d1975 10496 struct drm_i915_gem_object *obj,
a4872ba6 10497 struct intel_engine_cs *ring,
ed8d1975 10498 uint32_t flags)
8c9f3aaf
JB		 10499{
10500 struct drm_i915_private *dev_priv = dev->dev_private;
10501 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10502 uint32_t pf, pipesrc;
10503 int ret;
10504
6d90c952 10505 ret = intel_ring_begin(ring, 4);
8c9f3aaf 10506 if (ret)
4fa62c89 10507 return ret;
8c9f3aaf
JB		 10508
10509 /* i965+ uses the linear or tiled offsets from the
10510 * Display Registers (which do not change across a page-flip)
10511 * so we need only reprogram the base address.
10512 */
6d90c952
DV		 10513 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10514 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10515 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 10516 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
c2c75131 10517 obj->tiling_mode);
8c9f3aaf
JB		 10518
10519 /* XXX Enabling the panel-fitter across page-flip is so far
10520 * untested on non-native modes, so ignore it for now.
10521 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
10522 */
10523 pf = 0;
10524 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 10525 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 10526
10527 intel_mark_page_flip_active(intel_crtc);
09246732 10528 __intel_ring_advance(ring);
83d4092b 10529 return 0;
8c9f3aaf
JB		 10530}
10531
10532static int intel_gen6_queue_flip(struct drm_device *dev,
10533 struct drm_crtc *crtc,
10534 struct drm_framebuffer *fb,
ed8d1975 10535 struct drm_i915_gem_object *obj,
a4872ba6 10536 struct intel_engine_cs *ring,
ed8d1975 10537 uint32_t flags)
8c9f3aaf
JB		 10538{
10539 struct drm_i915_private *dev_priv = dev->dev_private;
10540 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10541 uint32_t pf, pipesrc;
10542 int ret;
10543
6d90c952 10544 ret = intel_ring_begin(ring, 4);
8c9f3aaf 10545 if (ret)
4fa62c89 10546 return ret;
8c9f3aaf 10547
6d90c952
DV		 10548 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10549 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10550 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
75f7f3ec 10551 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
8c9f3aaf 10552
dc257cf1
DV		 10553 /* Contrary to the suggestions in the documentation,
10554 * "Enable Panel Fitter" does not seem to be required when page
10555 * flipping with a non-native mode, and worse causes a normal
10556 * modeset to fail.
10557 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
10558 */
10559 pf = 0;
8c9f3aaf 10560 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 10561 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 10562
10563 intel_mark_page_flip_active(intel_crtc);
09246732 10564 __intel_ring_advance(ring);
83d4092b 10565 return 0;
8c9f3aaf
JB		 10566}
10567
7c9017e5
JB		 10568static int intel_gen7_queue_flip(struct drm_device *dev,
10569 struct drm_crtc *crtc,
10570 struct drm_framebuffer *fb,
ed8d1975 10571 struct drm_i915_gem_object *obj,
a4872ba6 10572 struct intel_engine_cs *ring,
ed8d1975 10573 uint32_t flags)
7c9017e5 10574{
7c9017e5 10575 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cb05d8de 10576 uint32_t plane_bit = 0;
ffe74d75
CW		 10577 int len, ret;
10578
eba905b2 10579 switch (intel_crtc->plane) {
cb05d8de
DV		 10580 case PLANE_A:
10581 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
10582 break;
10583 case PLANE_B:
10584 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
10585 break;
10586 case PLANE_C:
10587 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
10588 break;
10589 default:
10590 WARN_ONCE(1, "unknown plane in flip command\n");
4fa62c89 10591 return -ENODEV;
cb05d8de
DV		 10592 }
10593
ffe74d75 10594 len = 4;
f476828a 10595 if (ring->id == RCS) {
ffe74d75 10596 len += 6;
f476828a
DL		 10597 /*
10598 * On Gen 8, SRM is now taking an extra dword to accommodate
10599 * 48bits addresses, and we need a NOOP for the batch size to
10600 * stay even.
10601 */
10602 if (IS_GEN8(dev))
10603 len += 2;
10604 }
ffe74d75 10605
f66fab8e
VS		 10606 /*
10607 * BSpec MI_DISPLAY_FLIP for IVB:
10608 * "The full packet must be contained within the same cache line."
10609 *
10610 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
10611 * cacheline, if we ever start emitting more commands before
10612 * the MI_DISPLAY_FLIP we may need to first emit everything else,
10613 * then do the cacheline alignment, and finally emit the
10614 * MI_DISPLAY_FLIP.
10615 */
10616 ret = intel_ring_cacheline_align(ring);
10617 if (ret)
4fa62c89 10618 return ret;
f66fab8e 10619
ffe74d75 10620 ret = intel_ring_begin(ring, len);
7c9017e5 10621 if (ret)
4fa62c89 10622 return ret;
7c9017e5 10623
ffe74d75
CW		 10624 /* Unmask the flip-done completion message. Note that the bspec says that
10625 * we should do this for both the BCS and RCS, and that we must not unmask
10626 * more than one flip event at any time (or ensure that one flip message
10627 * can be sent by waiting for flip-done prior to queueing new flips).
10628 * Experimentation says that BCS works despite DERRMR masking all
10629 * flip-done completion events and that unmasking all planes at once
10630 * for the RCS also doesn't appear to drop events. Setting the DERRMR
10631 * to zero does lead to lockups within MI_DISPLAY_FLIP.
10632 */
10633 if (ring->id == RCS) {
10634 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
10635 intel_ring_emit(ring, DERRMR);
10636 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
10637 DERRMR_PIPEB_PRI_FLIP_DONE |
10638 DERRMR_PIPEC_PRI_FLIP_DONE));
f476828a
DL		 10639 if (IS_GEN8(dev))
10640 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
10641 MI_SRM_LRM_GLOBAL_GTT);
10642 else
10643 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
10644 MI_SRM_LRM_GLOBAL_GTT);
ffe74d75
CW		 10645 intel_ring_emit(ring, DERRMR);
10646 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
f476828a
DL		 10647 if (IS_GEN8(dev)) {
10648 intel_ring_emit(ring, 0);
10649 intel_ring_emit(ring, MI_NOOP);
10650 }
ffe74d75
CW		 10651 }
10652
cb05d8de 10653 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 10654 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
75f7f3ec 10655 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
7c9017e5 10656 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 10657
10658 intel_mark_page_flip_active(intel_crtc);
09246732 10659 __intel_ring_advance(ring);
83d4092b 10660 return 0;
7c9017e5
JB		 10661}
10662
84c33a64
SG		 10663static bool use_mmio_flip(struct intel_engine_cs *ring,
10664 struct drm_i915_gem_object *obj)
10665{
10666 /*
10667 * This is not being used for older platforms, because
10668 * non-availability of flip done interrupt forces us to use
10669 * CS flips. Older platforms derive flip done using some clever
10670 * tricks involving the flip_pending status bits and vblank irqs.
10671 * So using MMIO flips there would disrupt this mechanism.
10672 */
10673
8e09bf83
CW		 10674 if (ring == NULL)
10675 return true;
10676
84c33a64
SG		 10677 if (INTEL_INFO(ring->dev)->gen < 5)
10678 return false;
10679
10680 if (i915.use_mmio_flip < 0)
10681 return false;
10682 else if (i915.use_mmio_flip > 0)
10683 return true;
14bf993e
OM		 10684 else if (i915.enable_execlists)
10685 return true;
84c33a64 10686 else
41c52415 10687 return ring != i915_gem_request_get_ring(obj->last_read_req);
84c33a64
SG		 10688}
10689
ff944564
DL		 10690static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
10691{
10692 struct drm_device *dev = intel_crtc->base.dev;
10693 struct drm_i915_private *dev_priv = dev->dev_private;
10694 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
ff944564
DL		 10695 const enum pipe pipe = intel_crtc->pipe;
10696 u32 ctl, stride;
10697
10698 ctl = I915_READ(PLANE_CTL(pipe, 0));
10699 ctl &= ~PLANE_CTL_TILED_MASK;
2ebef630
TU		 10700 switch (fb->modifier[0]) {
10701 case DRM_FORMAT_MOD_NONE:
10702 break;
10703 case I915_FORMAT_MOD_X_TILED:
ff944564 10704 ctl |= PLANE_CTL_TILED_X;
2ebef630
TU		 10705 break;
10706 case I915_FORMAT_MOD_Y_TILED:
10707 ctl |= PLANE_CTL_TILED_Y;
10708 break;
10709 case I915_FORMAT_MOD_Yf_TILED:
10710 ctl |= PLANE_CTL_TILED_YF;
10711 break;
10712 default:
10713 MISSING_CASE(fb->modifier[0]);
10714 }
ff944564
DL		 10715
10716 /*
10717 * The stride is either expressed as a multiple of 64 bytes chunks for
10718 * linear buffers or in number of tiles for tiled buffers.
10719 */
2ebef630
TU		 10720 stride = fb->pitches[0] /
10721 intel_fb_stride_alignment(dev, fb->modifier[0],
10722 fb->pixel_format);
ff944564
DL		 10723
10724 /*
10725 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
10726 * PLANE_SURF updates, the update is then guaranteed to be atomic.
10727 */
10728 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
10729 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
10730
10731 I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
10732 POSTING_READ(PLANE_SURF(pipe, 0));
10733}
10734
10735static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
84c33a64
SG		 10736{
10737 struct drm_device *dev = intel_crtc->base.dev;
10738 struct drm_i915_private *dev_priv = dev->dev_private;
10739 struct intel_framebuffer *intel_fb =
10740 to_intel_framebuffer(intel_crtc->base.primary->fb);
10741 struct drm_i915_gem_object *obj = intel_fb->obj;
10742 u32 dspcntr;
10743 u32 reg;
10744
84c33a64
SG		 10745 reg = DSPCNTR(intel_crtc->plane);
10746 dspcntr = I915_READ(reg);
10747
c5d97472
DL		 10748 if (obj->tiling_mode != I915_TILING_NONE)
10749 dspcntr |= DISPPLANE_TILED;
10750 else
10751 dspcntr &= ~DISPPLANE_TILED;
10752
84c33a64
SG		 10753 I915_WRITE(reg, dspcntr);
10754
10755 I915_WRITE(DSPSURF(intel_crtc->plane),
10756 intel_crtc->unpin_work->gtt_offset);
10757 POSTING_READ(DSPSURF(intel_crtc->plane));
84c33a64 10758
ff944564
DL		 10759}
10760
10761/*
10762 * XXX: This is the temporary way to update the plane registers until we get
10763 * around to using the usual plane update functions for MMIO flips
10764 */
10765static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
10766{
10767 struct drm_device *dev = intel_crtc->base.dev;
10768 bool atomic_update;
10769 u32 start_vbl_count;
10770
10771 intel_mark_page_flip_active(intel_crtc);
10772
10773 atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
10774
10775 if (INTEL_INFO(dev)->gen >= 9)
10776 skl_do_mmio_flip(intel_crtc);
10777 else
10778 /* use_mmio_flip() retricts MMIO flips to ilk+ */
10779 ilk_do_mmio_flip(intel_crtc);
10780
9362c7c5
ACO		 10781 if (atomic_update)
10782 intel_pipe_update_end(intel_crtc, start_vbl_count);
84c33a64
SG		 10783}
10784
9362c7c5 10785static void intel_mmio_flip_work_func(struct work_struct *work)
84c33a64 10786{
b2cfe0ab
CW		 10787 struct intel_mmio_flip *mmio_flip =
10788 container_of(work, struct intel_mmio_flip, work);
84c33a64 10789
b2cfe0ab
CW		 10790 if (mmio_flip->rq)
10791 WARN_ON(__i915_wait_request(mmio_flip->rq,
10792 mmio_flip->crtc->reset_counter,
10793 false, NULL, NULL));
84c33a64 10794
b2cfe0ab
CW		 10795 intel_do_mmio_flip(mmio_flip->crtc);
10796
10797 i915_gem_request_unreference__unlocked(mmio_flip->rq);
10798 kfree(mmio_flip);
84c33a64
SG		 10799}
10800
10801static int intel_queue_mmio_flip(struct drm_device *dev,
10802 struct drm_crtc *crtc,
10803 struct drm_framebuffer *fb,
10804 struct drm_i915_gem_object *obj,
10805 struct intel_engine_cs *ring,
10806 uint32_t flags)
10807{
b2cfe0ab
CW		 10808 struct intel_mmio_flip *mmio_flip;
10809
10810 mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
10811 if (mmio_flip == NULL)
10812 return -ENOMEM;
84c33a64 10813
b2cfe0ab
CW		 10814 mmio_flip->rq = i915_gem_request_reference(obj->last_write_req);
10815 mmio_flip->crtc = to_intel_crtc(crtc);
536f5b5e 10816
b2cfe0ab
CW		 10817 INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
10818 schedule_work(&mmio_flip->work);
84c33a64 10819
84c33a64
SG		 10820 return 0;
10821}
10822
8c9f3aaf
JB		 10823static int intel_default_queue_flip(struct drm_device *dev,
10824 struct drm_crtc *crtc,
10825 struct drm_framebuffer *fb,
ed8d1975 10826 struct drm_i915_gem_object *obj,
a4872ba6 10827 struct intel_engine_cs *ring,
ed8d1975 10828 uint32_t flags)
8c9f3aaf
JB		 10829{
10830 return -ENODEV;
10831}
10832
d6bbafa1
CW		 10833static bool __intel_pageflip_stall_check(struct drm_device *dev,
10834 struct drm_crtc *crtc)
10835{
10836 struct drm_i915_private *dev_priv = dev->dev_private;
10837 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10838 struct intel_unpin_work *work = intel_crtc->unpin_work;
10839 u32 addr;
10840
10841 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
10842 return true;
10843
10844 if (!work->enable_stall_check)
10845 return false;
10846
10847 if (work->flip_ready_vblank == 0) {
3a8a946e
DV		 10848 if (work->flip_queued_req &&
10849 !i915_gem_request_completed(work->flip_queued_req, true))
d6bbafa1
CW		 10850 return false;
10851
1e3feefd 10852 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
d6bbafa1
CW		 10853 }
10854
1e3feefd 10855 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
d6bbafa1
CW		 10856 return false;
10857
10858 /* Potential stall - if we see that the flip has happened,
10859 * assume a missed interrupt. */
10860 if (INTEL_INFO(dev)->gen >= 4)
10861 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
10862 else
10863 addr = I915_READ(DSPADDR(intel_crtc->plane));
10864
10865 /* There is a potential issue here with a false positive after a flip
10866 * to the same address. We could address this by checking for a
10867 * non-incrementing frame counter.
10868 */
10869 return addr == work->gtt_offset;
10870}
10871
10872void intel_check_page_flip(struct drm_device *dev, int pipe)
10873{
10874 struct drm_i915_private *dev_priv = dev->dev_private;
10875 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10876 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6ad790c0 10877 struct intel_unpin_work *work;
f326038a 10878
6c51d46f 10879 WARN_ON(!in_interrupt());
d6bbafa1
CW		 10880
10881 if (crtc == NULL)
10882 return;
10883
f326038a 10884 spin_lock(&dev->event_lock);
6ad790c0
CW		 10885 work = intel_crtc->unpin_work;
10886 if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
d6bbafa1 10887 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
6ad790c0 10888 work->flip_queued_vblank, drm_vblank_count(dev, pipe));
d6bbafa1 10889 page_flip_completed(intel_crtc);
6ad790c0 10890 work = NULL;
d6bbafa1 10891 }
6ad790c0
CW		 10892 if (work != NULL &&
10893 drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
10894 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
f326038a 10895 spin_unlock(&dev->event_lock);
d6bbafa1
CW		 10896}
10897
6b95a207
KH		 10898static int intel_crtc_page_flip(struct drm_crtc *crtc,
10899 struct drm_framebuffer *fb,
ed8d1975
KP		 10900 struct drm_pending_vblank_event *event,
10901 uint32_t page_flip_flags)
6b95a207
KH		 10902{
10903 struct drm_device *dev = crtc->dev;
10904 struct drm_i915_private *dev_priv = dev->dev_private;
f4510a27 10905 struct drm_framebuffer *old_fb = crtc->primary->fb;
2ff8fde1 10906 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
6b95a207 10907 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
455a6808 10908 struct drm_plane *primary = crtc->primary;
a071fa00 10909 enum pipe pipe = intel_crtc->pipe;
6b95a207 10910 struct intel_unpin_work *work;
a4872ba6 10911 struct intel_engine_cs *ring;
cf5d8a46 10912 bool mmio_flip;
52e68630 10913 int ret;
6b95a207 10914
2ff8fde1
MR		 10915 /*
10916 * drm_mode_page_flip_ioctl() should already catch this, but double
10917 * check to be safe. In the future we may enable pageflipping from
10918 * a disabled primary plane.
10919 */
10920 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
10921 return -EBUSY;
10922
e6a595d2 10923 /* Can't change pixel format via MI display flips. */
f4510a27 10924 if (fb->pixel_format != crtc->primary->fb->pixel_format)
e6a595d2
VS		 10925 return -EINVAL;
10926
10927 /*
10928 * TILEOFF/LINOFF registers can't be changed via MI display flips.
10929 * Note that pitch changes could also affect these register.
10930 */
10931 if (INTEL_INFO(dev)->gen > 3 &&
f4510a27
MR		 10932 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
10933 fb->pitches[0] != crtc->primary->fb->pitches[0]))
e6a595d2
VS		 10934 return -EINVAL;
10935
f900db47
CW		 10936 if (i915_terminally_wedged(&dev_priv->gpu_error))
10937 goto out_hang;
10938
b14c5679 10939 work = kzalloc(sizeof(*work), GFP_KERNEL);
6b95a207
KH		 10940 if (work == NULL)
10941 return -ENOMEM;
10942
6b95a207 10943 work->event = event;
b4a98e57 10944 work->crtc = crtc;
ab8d6675 10945 work->old_fb = old_fb;
6b95a207
KH		 10946 INIT_WORK(&work->work, intel_unpin_work_fn);
10947
87b6b101 10948 ret = drm_crtc_vblank_get(crtc);
7317c75e
JB		 10949 if (ret)
10950 goto free_work;
10951
6b95a207 10952 /* We borrow the event spin lock for protecting unpin_work */
5e2d7afc 10953 spin_lock_irq(&dev->event_lock);
6b95a207 10954 if (intel_crtc->unpin_work) {
d6bbafa1
CW		 10955 /* Before declaring the flip queue wedged, check if
10956 * the hardware completed the operation behind our backs.
10957 */
10958 if (__intel_pageflip_stall_check(dev, crtc)) {
10959 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
10960 page_flip_completed(intel_crtc);
10961 } else {
10962 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
5e2d7afc 10963 spin_unlock_irq(&dev->event_lock);
468f0b44 10964
d6bbafa1
CW		 10965 drm_crtc_vblank_put(crtc);
10966 kfree(work);
10967 return -EBUSY;
10968 }
6b95a207
KH		 10969 }
10970 intel_crtc->unpin_work = work;
5e2d7afc 10971 spin_unlock_irq(&dev->event_lock);
6b95a207 10972
b4a98e57
CW		 10973 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
10974 flush_workqueue(dev_priv->wq);
10975
75dfca80 10976 /* Reference the objects for the scheduled work. */
ab8d6675 10977 drm_framebuffer_reference(work->old_fb);
05394f39 10978 drm_gem_object_reference(&obj->base);
6b95a207 10979
f4510a27 10980 crtc->primary->fb = fb;
afd65eb4 10981 update_state_fb(crtc->primary);
1ed1f968 10982
e1f99ce6 10983 work->pending_flip_obj = obj;
e1f99ce6 10984
89ed88ba
CW		 10985 ret = i915_mutex_lock_interruptible(dev);
10986 if (ret)
10987 goto cleanup;
10988
b4a98e57 10989 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 10990 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 10991
75f7f3ec 10992 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
a071fa00 10993 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
75f7f3ec 10994
4fa62c89
VS		 10995 if (IS_VALLEYVIEW(dev)) {
10996 ring = &dev_priv->ring[BCS];
ab8d6675 10997 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
8e09bf83
CW		 10998 /* vlv: DISPLAY_FLIP fails to change tiling */
10999 ring = NULL;
48bf5b2d 11000 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
2a92d5bc 11001 ring = &dev_priv->ring[BCS];
4fa62c89 11002 } else if (INTEL_INFO(dev)->gen >= 7) {
41c52415 11003 ring = i915_gem_request_get_ring(obj->last_read_req);
4fa62c89
VS		 11004 if (ring == NULL || ring->id != RCS)
11005 ring = &dev_priv->ring[BCS];
11006 } else {
11007 ring = &dev_priv->ring[RCS];
11008 }
11009
cf5d8a46
CW		 11010 mmio_flip = use_mmio_flip(ring, obj);
11011
11012 /* When using CS flips, we want to emit semaphores between rings.
11013 * However, when using mmio flips we will create a task to do the
11014 * synchronisation, so all we want here is to pin the framebuffer
11015 * into the display plane and skip any waits.
11016 */
82bc3b2d 11017 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
cf5d8a46
CW		 11018 crtc->primary->state,
11019 mmio_flip ? i915_gem_request_get_ring(obj->last_read_req) : ring);
8c9f3aaf
JB		 11020 if (ret)
11021 goto cleanup_pending;
6b95a207 11022
121920fa
TU		 11023 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj)
11024 + intel_crtc->dspaddr_offset;
4fa62c89 11025
cf5d8a46 11026 if (mmio_flip) {
84c33a64
SG		 11027 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
11028 page_flip_flags);
d6bbafa1
CW		 11029 if (ret)
11030 goto cleanup_unpin;
11031
f06cc1b9
JH		 11032 i915_gem_request_assign(&work->flip_queued_req,
11033 obj->last_write_req);
d6bbafa1 11034 } else {
d94b5030
CW		 11035 if (obj->last_write_req) {
11036 ret = i915_gem_check_olr(obj->last_write_req);
11037 if (ret)
11038 goto cleanup_unpin;
11039 }
11040
84c33a64 11041 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
d6bbafa1
CW		 11042 page_flip_flags);
11043 if (ret)
11044 goto cleanup_unpin;
11045
f06cc1b9
JH		 11046 i915_gem_request_assign(&work->flip_queued_req,
11047 intel_ring_get_request(ring));
d6bbafa1
CW		 11048 }
11049
1e3feefd 11050 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
d6bbafa1 11051 work->enable_stall_check = true;
4fa62c89 11052
ab8d6675 11053 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
a071fa00
DV		 11054 INTEL_FRONTBUFFER_PRIMARY(pipe));
11055
7ff0ebcc 11056 intel_fbc_disable(dev);
f99d7069 11057 intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
6b95a207
KH		 11058 mutex_unlock(&dev->struct_mutex);
11059
e5510fac
JB		 11060 trace_i915_flip_request(intel_crtc->plane, obj);
11061
6b95a207 11062 return 0;
96b099fd 11063
4fa62c89 11064cleanup_unpin:
82bc3b2d 11065 intel_unpin_fb_obj(fb, crtc->primary->state);
8c9f3aaf 11066cleanup_pending:
b4a98e57 11067 atomic_dec(&intel_crtc->unpin_work_count);
89ed88ba
CW		 11068 mutex_unlock(&dev->struct_mutex);
11069cleanup:
f4510a27 11070 crtc->primary->fb = old_fb;
afd65eb4 11071 update_state_fb(crtc->primary);
89ed88ba
CW		 11072
11073 drm_gem_object_unreference_unlocked(&obj->base);
ab8d6675 11074 drm_framebuffer_unreference(work->old_fb);
96b099fd 11075
5e2d7afc 11076 spin_lock_irq(&dev->event_lock);
96b099fd 11077 intel_crtc->unpin_work = NULL;
5e2d7afc 11078 spin_unlock_irq(&dev->event_lock);
96b099fd 11079
87b6b101 11080 drm_crtc_vblank_put(crtc);
7317c75e 11081free_work:
96b099fd
CW		 11082 kfree(work);
11083
f900db47
CW		 11084 if (ret == -EIO) {
11085out_hang:
53a366b9 11086 ret = intel_plane_restore(primary);
f0d3dad3 11087 if (ret == 0 && event) {
5e2d7afc 11088 spin_lock_irq(&dev->event_lock);
a071fa00 11089 drm_send_vblank_event(dev, pipe, event);
5e2d7afc 11090 spin_unlock_irq(&dev->event_lock);
f0d3dad3 11091 }
f900db47 11092 }
96b099fd 11093 return ret;
6b95a207
KH		 11094}
11095
65b38e0d 11096static const struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 11097 .mode_set_base_atomic = intel_pipe_set_base_atomic,
11098 .load_lut = intel_crtc_load_lut,
ea2c67bb
MR		 11099 .atomic_begin = intel_begin_crtc_commit,
11100 .atomic_flush = intel_finish_crtc_commit,
f6e5b160
CW		 11101};
11102
9a935856
DV		 11103/**
11104 * intel_modeset_update_staged_output_state
11105 *
11106 * Updates the staged output configuration state, e.g. after we've read out the
11107 * current hw state.
11108 */
11109static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 11110{
7668851f 11111 struct intel_crtc *crtc;
9a935856
DV		 11112 struct intel_encoder *encoder;
11113 struct intel_connector *connector;
f6e5b160 11114
3a3371ff 11115 for_each_intel_connector(dev, connector) {
9a935856
DV		 11116 connector->new_encoder =
11117 to_intel_encoder(connector->base.encoder);
11118 }
f6e5b160 11119
b2784e15 11120 for_each_intel_encoder(dev, encoder) {
9a935856
DV		 11121 encoder->new_crtc =
11122 to_intel_crtc(encoder->base.crtc);
11123 }
7668851f 11124
d3fcc808 11125 for_each_intel_crtc(dev, crtc) {
83d65738 11126 crtc->new_enabled = crtc->base.state->enable;
7668851f 11127 }
f6e5b160
CW		 11128}
11129
d29b2f9d
ACO		 11130/* Transitional helper to copy current connector/encoder state to
11131 * connector->state. This is needed so that code that is partially
11132 * converted to atomic does the right thing.
11133 */
11134static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11135{
11136 struct intel_connector *connector;
11137
11138 for_each_intel_connector(dev, connector) {
11139 if (connector->base.encoder) {
11140 connector->base.state->best_encoder =
11141 connector->base.encoder;
11142 connector->base.state->crtc =
11143 connector->base.encoder->crtc;
11144 } else {
11145 connector->base.state->best_encoder = NULL;
11146 connector->base.state->crtc = NULL;
11147 }
11148 }
11149}
11150
a821fc46 11151/* Fixup legacy state after an atomic state swap.
9a935856 11152 */
a821fc46 11153static void intel_modeset_fixup_state(struct drm_atomic_state *state)
9a935856 11154{
a821fc46 11155 struct intel_crtc *crtc;
9a935856 11156 struct intel_encoder *encoder;
a821fc46 11157 struct intel_connector *connector;
d5432a9d 11158
a821fc46
ACO		 11159 for_each_intel_connector(state->dev, connector) {
11160 connector->base.encoder = connector->base.state->best_encoder;
11161 if (connector->base.encoder)
11162 connector->base.encoder->crtc =
11163 connector->base.state->crtc;
9a935856 11164 }
f6e5b160 11165
d5432a9d
ACO		 11166 /* Update crtc of disabled encoders */
11167 for_each_intel_encoder(state->dev, encoder) {
11168 int num_connectors = 0;
11169
a821fc46
ACO		 11170 for_each_intel_connector(state->dev, connector)
11171 if (connector->base.encoder == &encoder->base)
d5432a9d
ACO		 11172 num_connectors++;
11173
11174 if (num_connectors == 0)
11175 encoder->base.crtc = NULL;
9a935856 11176 }
7668851f 11177
a821fc46
ACO		 11178 for_each_intel_crtc(state->dev, crtc) {
11179 crtc->base.enabled = crtc->base.state->enable;
11180 crtc->config = to_intel_crtc_state(crtc->base.state);
7668851f 11181 }
d29b2f9d 11182
d5432a9d
ACO		 11183 /* Copy the new configuration to the staged state, to keep the few
11184 * pieces of code that haven't been converted yet happy */
11185 intel_modeset_update_staged_output_state(state->dev);
9a935856
DV		 11186}
11187
050f7aeb 11188static void
eba905b2 11189connected_sink_compute_bpp(struct intel_connector *connector,
5cec258b 11190 struct intel_crtc_state *pipe_config)
050f7aeb
DV		 11191{
11192 int bpp = pipe_config->pipe_bpp;
11193
11194 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11195 connector->base.base.id,
c23cc417 11196 connector->base.name);
050f7aeb
DV		 11197
11198 /* Don't use an invalid EDID bpc value */
11199 if (connector->base.display_info.bpc &&
11200 connector->base.display_info.bpc * 3 < bpp) {
11201 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11202 bpp, connector->base.display_info.bpc*3);
11203 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11204 }
11205
11206 /* Clamp bpp to 8 on screens without EDID 1.4 */
11207 if (connector->base.display_info.bpc == 0 && bpp > 24) {
11208 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11209 bpp);
11210 pipe_config->pipe_bpp = 24;
11211 }
11212}
11213
4e53c2e0 11214static int
050f7aeb 11215compute_baseline_pipe_bpp(struct intel_crtc *crtc,
5cec258b 11216 struct intel_crtc_state *pipe_config)
4e53c2e0 11217{
050f7aeb 11218 struct drm_device *dev = crtc->base.dev;
1486017f 11219 struct drm_atomic_state *state;
da3ced29
ACO		 11220 struct drm_connector *connector;
11221 struct drm_connector_state *connector_state;
1486017f 11222 int bpp, i;
4e53c2e0 11223
d328c9d7 11224 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
4e53c2e0 11225 bpp = 10*3;
d328c9d7
DV		 11226 else if (INTEL_INFO(dev)->gen >= 5)
11227 bpp = 12*3;
11228 else
11229 bpp = 8*3;
11230
4e53c2e0 11231
4e53c2e0
DV		 11232 pipe_config->pipe_bpp = bpp;
11233
1486017f
ACO		 11234 state = pipe_config->base.state;
11235
4e53c2e0 11236 /* Clamp display bpp to EDID value */
da3ced29
ACO		 11237 for_each_connector_in_state(state, connector, connector_state, i) {
11238 if (connector_state->crtc != &crtc->base)
4e53c2e0
DV		 11239 continue;
11240
da3ced29
ACO		 11241 connected_sink_compute_bpp(to_intel_connector(connector),
11242 pipe_config);
4e53c2e0
DV		 11243 }
11244
11245 return bpp;
11246}
11247
644db711
DV		 11248static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11249{
11250 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11251 "type: 0x%x flags: 0x%x\n",
1342830c 11252 mode->crtc_clock,
644db711
DV		 11253 mode->crtc_hdisplay, mode->crtc_hsync_start,
11254 mode->crtc_hsync_end, mode->crtc_htotal,
11255 mode->crtc_vdisplay, mode->crtc_vsync_start,
11256 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11257}
11258
c0b03411 11259static void intel_dump_pipe_config(struct intel_crtc *crtc,
5cec258b 11260 struct intel_crtc_state *pipe_config,
c0b03411
DV		 11261 const char *context)
11262{
6a60cd87
CK		 11263 struct drm_device *dev = crtc->base.dev;
11264 struct drm_plane *plane;
11265 struct intel_plane *intel_plane;
11266 struct intel_plane_state *state;
11267 struct drm_framebuffer *fb;
11268
11269 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
11270 context, pipe_config, pipe_name(crtc->pipe));
c0b03411
DV		 11271
11272 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
11273 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
11274 pipe_config->pipe_bpp, pipe_config->dither);
11275 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11276 pipe_config->has_pch_encoder,
11277 pipe_config->fdi_lanes,
11278 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
11279 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
11280 pipe_config->fdi_m_n.tu);
eb14cb74
VS		 11281 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11282 pipe_config->has_dp_encoder,
11283 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
11284 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
11285 pipe_config->dp_m_n.tu);
b95af8be
VK		 11286
11287 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
11288 pipe_config->has_dp_encoder,
11289 pipe_config->dp_m2_n2.gmch_m,
11290 pipe_config->dp_m2_n2.gmch_n,
11291 pipe_config->dp_m2_n2.link_m,
11292 pipe_config->dp_m2_n2.link_n,
11293 pipe_config->dp_m2_n2.tu);
11294
55072d19
DV		 11295 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11296 pipe_config->has_audio,
11297 pipe_config->has_infoframe);
11298
c0b03411 11299 DRM_DEBUG_KMS("requested mode:\n");
2d112de7 11300 drm_mode_debug_printmodeline(&pipe_config->base.mode);
c0b03411 11301 DRM_DEBUG_KMS("adjusted mode:\n");
2d112de7
ACO		 11302 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
11303 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
d71b8d4a 11304 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
37327abd
VS		 11305 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
11306 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
0ec463d3
TU		 11307 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
11308 crtc->num_scalers,
11309 pipe_config->scaler_state.scaler_users,
11310 pipe_config->scaler_state.scaler_id);
c0b03411
DV		 11311 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11312 pipe_config->gmch_pfit.control,
11313 pipe_config->gmch_pfit.pgm_ratios,
11314 pipe_config->gmch_pfit.lvds_border_bits);
fd4daa9c 11315 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
c0b03411 11316 pipe_config->pch_pfit.pos,
fd4daa9c
CW		 11317 pipe_config->pch_pfit.size,
11318 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
42db64ef 11319 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
cf532bb2 11320 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
6a60cd87 11321
415ff0f6
TU		 11322 if (IS_BROXTON(dev)) {
11323 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, "
11324 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
11325 "pll6: 0x%x, pll8: 0x%x, pcsdw12: 0x%x\n",
11326 pipe_config->ddi_pll_sel,
11327 pipe_config->dpll_hw_state.ebb0,
11328 pipe_config->dpll_hw_state.pll0,
11329 pipe_config->dpll_hw_state.pll1,
11330 pipe_config->dpll_hw_state.pll2,
11331 pipe_config->dpll_hw_state.pll3,
11332 pipe_config->dpll_hw_state.pll6,
11333 pipe_config->dpll_hw_state.pll8,
11334 pipe_config->dpll_hw_state.pcsdw12);
11335 } else if (IS_SKYLAKE(dev)) {
11336 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
11337 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
11338 pipe_config->ddi_pll_sel,
11339 pipe_config->dpll_hw_state.ctrl1,
11340 pipe_config->dpll_hw_state.cfgcr1,
11341 pipe_config->dpll_hw_state.cfgcr2);
11342 } else if (HAS_DDI(dev)) {
11343 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x\n",
11344 pipe_config->ddi_pll_sel,
11345 pipe_config->dpll_hw_state.wrpll);
11346 } else {
11347 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
11348 "fp0: 0x%x, fp1: 0x%x\n",
11349 pipe_config->dpll_hw_state.dpll,
11350 pipe_config->dpll_hw_state.dpll_md,
11351 pipe_config->dpll_hw_state.fp0,
11352 pipe_config->dpll_hw_state.fp1);
11353 }
11354
6a60cd87
CK		 11355 DRM_DEBUG_KMS("planes on this crtc\n");
11356 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
11357 intel_plane = to_intel_plane(plane);
11358 if (intel_plane->pipe != crtc->pipe)
11359 continue;
11360
11361 state = to_intel_plane_state(plane->state);
11362 fb = state->base.fb;
11363 if (!fb) {
11364 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
11365 "disabled, scaler_id = %d\n",
11366 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
11367 plane->base.id, intel_plane->pipe,
11368 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
11369 drm_plane_index(plane), state->scaler_id);
11370 continue;
11371 }
11372
11373 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
11374 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
11375 plane->base.id, intel_plane->pipe,
11376 crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
11377 drm_plane_index(plane));
11378 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
11379 fb->base.id, fb->width, fb->height, fb->pixel_format);
11380 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
11381 state->scaler_id,
11382 state->src.x1 >> 16, state->src.y1 >> 16,
11383 drm_rect_width(&state->src) >> 16,
11384 drm_rect_height(&state->src) >> 16,
11385 state->dst.x1, state->dst.y1,
11386 drm_rect_width(&state->dst), drm_rect_height(&state->dst));
11387 }
c0b03411
DV		 11388}
11389
bc079e8b
VS		 11390static bool encoders_cloneable(const struct intel_encoder *a,
11391 const struct intel_encoder *b)
accfc0c5 11392{
bc079e8b
VS		 11393 /* masks could be asymmetric, so check both ways */
11394 return a == b || (a->cloneable & (1 << b->type) &&
11395 b->cloneable & (1 << a->type));
11396}
11397
98a221da
ACO		 11398static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11399 struct intel_crtc *crtc,
bc079e8b
VS		 11400 struct intel_encoder *encoder)
11401{
bc079e8b 11402 struct intel_encoder *source_encoder;
da3ced29 11403 struct drm_connector *connector;
98a221da
ACO		 11404 struct drm_connector_state *connector_state;
11405 int i;
bc079e8b 11406
da3ced29 11407 for_each_connector_in_state(state, connector, connector_state, i) {
98a221da 11408 if (connector_state->crtc != &crtc->base)
bc079e8b
VS		 11409 continue;
11410
98a221da
ACO		 11411 source_encoder =
11412 to_intel_encoder(connector_state->best_encoder);
bc079e8b
VS		 11413 if (!encoders_cloneable(encoder, source_encoder))
11414 return false;
11415 }
11416
11417 return true;
11418}
11419
98a221da
ACO		 11420static bool check_encoder_cloning(struct drm_atomic_state *state,
11421 struct intel_crtc *crtc)
bc079e8b 11422{
accfc0c5 11423 struct intel_encoder *encoder;
da3ced29 11424 struct drm_connector *connector;
98a221da
ACO		 11425 struct drm_connector_state *connector_state;
11426 int i;
accfc0c5 11427
da3ced29 11428 for_each_connector_in_state(state, connector, connector_state, i) {
98a221da
ACO		 11429 if (connector_state->crtc != &crtc->base)
11430 continue;
11431
11432 encoder = to_intel_encoder(connector_state->best_encoder);
11433 if (!check_single_encoder_cloning(state, crtc, encoder))
bc079e8b 11434 return false;
accfc0c5
DV		 11435 }
11436
bc079e8b 11437 return true;
accfc0c5
DV		 11438}
11439
5448a00d 11440static bool check_digital_port_conflicts(struct drm_atomic_state *state)
00f0b378 11441{
5448a00d
ACO		 11442 struct drm_device *dev = state->dev;
11443 struct intel_encoder *encoder;
da3ced29 11444 struct drm_connector *connector;
5448a00d 11445 struct drm_connector_state *connector_state;
00f0b378 11446 unsigned int used_ports = 0;
5448a00d 11447 int i;
00f0b378
VS		 11448
11449 /*
11450 * Walk the connector list instead of the encoder
11451 * list to detect the problem on ddi platforms
11452 * where there's just one encoder per digital port.
11453 */
da3ced29 11454 for_each_connector_in_state(state, connector, connector_state, i) {
5448a00d 11455 if (!connector_state->best_encoder)
00f0b378
VS		 11456 continue;
11457
5448a00d
ACO		 11458 encoder = to_intel_encoder(connector_state->best_encoder);
11459
11460 WARN_ON(!connector_state->crtc);
00f0b378
VS		 11461
11462 switch (encoder->type) {
11463 unsigned int port_mask;
11464 case INTEL_OUTPUT_UNKNOWN:
11465 if (WARN_ON(!HAS_DDI(dev)))
11466 break;
11467 case INTEL_OUTPUT_DISPLAYPORT:
11468 case INTEL_OUTPUT_HDMI:
11469 case INTEL_OUTPUT_EDP:
11470 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
11471
11472 /* the same port mustn't appear more than once */
11473 if (used_ports & port_mask)
11474 return false;
11475
11476 used_ports |= port_mask;
11477 default:
11478 break;
11479 }
11480 }
11481
11482 return true;
11483}
11484
83a57153
ACO		 11485static void
11486clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
11487{
11488 struct drm_crtc_state tmp_state;
663a3640 11489 struct intel_crtc_scaler_state scaler_state;
4978cc93
ACO		 11490 struct intel_dpll_hw_state dpll_hw_state;
11491 enum intel_dpll_id shared_dpll;
8504c74c 11492 uint32_t ddi_pll_sel;
83a57153 11493
663a3640 11494 /* Clear only the intel specific part of the crtc state excluding scalers */
83a57153 11495 tmp_state = crtc_state->base;
663a3640 11496 scaler_state = crtc_state->scaler_state;
4978cc93
ACO		 11497 shared_dpll = crtc_state->shared_dpll;
11498 dpll_hw_state = crtc_state->dpll_hw_state;
8504c74c 11499 ddi_pll_sel = crtc_state->ddi_pll_sel;
4978cc93 11500
83a57153 11501 memset(crtc_state, 0, sizeof *crtc_state);
4978cc93 11502
83a57153 11503 crtc_state->base = tmp_state;
663a3640 11504 crtc_state->scaler_state = scaler_state;
4978cc93
ACO		 11505 crtc_state->shared_dpll = shared_dpll;
11506 crtc_state->dpll_hw_state = dpll_hw_state;
8504c74c 11507 crtc_state->ddi_pll_sel = ddi_pll_sel;
83a57153
ACO		 11508}
11509
548ee15b 11510static int
b8cecdf5 11511intel_modeset_pipe_config(struct drm_crtc *crtc,
548ee15b
ACO		 11512 struct drm_atomic_state *state,
11513 struct intel_crtc_state *pipe_config)
ee7b9f93 11514{
7758a113 11515 struct intel_encoder *encoder;
da3ced29 11516 struct drm_connector *connector;
0b901879 11517 struct drm_connector_state *connector_state;
d328c9d7 11518 int base_bpp, ret = -EINVAL;
0b901879 11519 int i;
e29c22c0 11520 bool retry = true;
ee7b9f93 11521
98a221da 11522 if (!check_encoder_cloning(state, to_intel_crtc(crtc))) {
accfc0c5 11523 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
548ee15b 11524 return -EINVAL;
accfc0c5
DV		 11525 }
11526
5448a00d 11527 if (!check_digital_port_conflicts(state)) {
00f0b378 11528 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
548ee15b 11529 return -EINVAL;
00f0b378
VS		 11530 }
11531
83a57153 11532 clear_intel_crtc_state(pipe_config);
7758a113 11533
e143a21c
DV		 11534 pipe_config->cpu_transcoder =
11535 (enum transcoder) to_intel_crtc(crtc)->pipe;
b8cecdf5 11536
2960bc9c
ID		 11537 /*
11538 * Sanitize sync polarity flags based on requested ones. If neither
11539 * positive or negative polarity is requested, treat this as meaning
11540 * negative polarity.
11541 */
2d112de7 11542 if (!(pipe_config->base.adjusted_mode.flags &
2960bc9c 11543 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
2d112de7 11544 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
2960bc9c 11545
2d112de7 11546 if (!(pipe_config->base.adjusted_mode.flags &
2960bc9c 11547 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
2d112de7 11548 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
2960bc9c 11549
050f7aeb
DV		 11550 /* Compute a starting value for pipe_config->pipe_bpp taking the source
11551 * plane pixel format and any sink constraints into account. Returns the
11552 * source plane bpp so that dithering can be selected on mismatches
11553 * after encoders and crtc also have had their say. */
d328c9d7
DV		 11554 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
11555 pipe_config);
11556 if (base_bpp < 0)
4e53c2e0
DV		 11557 goto fail;
11558
e41a56be
VS		 11559 /*
11560 * Determine the real pipe dimensions. Note that stereo modes can
11561 * increase the actual pipe size due to the frame doubling and
11562 * insertion of additional space for blanks between the frame. This
11563 * is stored in the crtc timings. We use the requested mode to do this
11564 * computation to clearly distinguish it from the adjusted mode, which
11565 * can be changed by the connectors in the below retry loop.
11566 */
2d112de7 11567 drm_crtc_get_hv_timing(&pipe_config->base.mode,
ecb7e16b
GP		 11568 &pipe_config->pipe_src_w,
11569 &pipe_config->pipe_src_h);
e41a56be 11570
e29c22c0 11571encoder_retry:
ef1b460d 11572 /* Ensure the port clock defaults are reset when retrying. */
ff9a6750 11573 pipe_config->port_clock = 0;
ef1b460d 11574 pipe_config->pixel_multiplier = 1;
ff9a6750 11575
135c81b8 11576 /* Fill in default crtc timings, allow encoders to overwrite them. */
2d112de7
ACO		 11577 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
11578 CRTC_STEREO_DOUBLE);
135c81b8 11579
7758a113
DV		 11580 /* Pass our mode to the connectors and the CRTC to give them a chance to
11581 * adjust it according to limitations or connector properties, and also
11582 * a chance to reject the mode entirely.
47f1c6c9 11583 */
da3ced29 11584 for_each_connector_in_state(state, connector, connector_state, i) {
0b901879 11585 if (connector_state->crtc != crtc)
7758a113 11586 continue;
7ae89233 11587
0b901879
ACO		 11588 encoder = to_intel_encoder(connector_state->best_encoder);
11589
efea6e8e
DV		 11590 if (!(encoder->compute_config(encoder, pipe_config))) {
11591 DRM_DEBUG_KMS("Encoder config failure\n");
7758a113
DV		 11592 goto fail;
11593 }
ee7b9f93 11594 }
47f1c6c9 11595
ff9a6750
DV		 11596 /* Set default port clock if not overwritten by the encoder. Needs to be
11597 * done afterwards in case the encoder adjusts the mode. */
11598 if (!pipe_config->port_clock)
2d112de7 11599 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
241bfc38 11600 * pipe_config->pixel_multiplier;
ff9a6750 11601
a43f6e0f 11602 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
e29c22c0 11603 if (ret < 0) {
7758a113
DV		 11604 DRM_DEBUG_KMS("CRTC fixup failed\n");
11605 goto fail;
ee7b9f93 11606 }
e29c22c0
DV		 11607
11608 if (ret == RETRY) {
11609 if (WARN(!retry, "loop in pipe configuration computation\n")) {
11610 ret = -EINVAL;
11611 goto fail;
11612 }
11613
11614 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
11615 retry = false;
11616 goto encoder_retry;
11617 }
11618
d328c9d7 11619 pipe_config->dither = pipe_config->pipe_bpp != base_bpp;
4e53c2e0 11620 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
d328c9d7 11621 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
4e53c2e0 11622
548ee15b 11623 return 0;
7758a113 11624fail:
548ee15b 11625 return ret;
ee7b9f93 11626}
47f1c6c9 11627
ea9d758d 11628static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 11629{
ea9d758d 11630 struct drm_encoder *encoder;
f6e5b160 11631 struct drm_device *dev = crtc->dev;
f6e5b160 11632
ea9d758d
DV		 11633 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
11634 if (encoder->crtc == crtc)
11635 return true;
11636
11637 return false;
11638}
11639
0a9ab303
ACO		 11640static bool
11641needs_modeset(struct drm_crtc_state *state)
11642{
11643 return state->mode_changed || state->active_changed;
11644}
11645
ea9d758d 11646static void
0a9ab303 11647intel_modeset_update_state(struct drm_atomic_state *state)
ea9d758d 11648{
0a9ab303 11649 struct drm_device *dev = state->dev;
ba41c0de 11650 struct drm_i915_private *dev_priv = dev->dev_private;
ea9d758d 11651 struct intel_encoder *intel_encoder;
0a9ab303
ACO		 11652 struct drm_crtc *crtc;
11653 struct drm_crtc_state *crtc_state;
ea9d758d 11654 struct drm_connector *connector;
0a9ab303 11655 int i;
ea9d758d 11656
ba41c0de
DV		 11657 intel_shared_dpll_commit(dev_priv);
11658
b2784e15 11659 for_each_intel_encoder(dev, intel_encoder) {
ea9d758d
DV		 11660 if (!intel_encoder->base.crtc)
11661 continue;
11662
0a9ab303
ACO		 11663 for_each_crtc_in_state(state, crtc, crtc_state, i)
11664 if (crtc == intel_encoder->base.crtc)
11665 break;
11666
11667 if (crtc != intel_encoder->base.crtc)
11668 continue;
ea9d758d 11669
0a9ab303 11670 if (crtc_state->enable && needs_modeset(crtc_state))
ea9d758d
DV		 11671 intel_encoder->connectors_active = false;
11672 }
11673
a821fc46
ACO		 11674 drm_atomic_helper_swap_state(state->dev, state);
11675 intel_modeset_fixup_state(state);
ea9d758d 11676
7668851f 11677 /* Double check state. */
0a9ab303
ACO		 11678 for_each_crtc(dev, crtc) {
11679 WARN_ON(crtc->state->enable != intel_crtc_in_use(crtc));
ea9d758d
DV		 11680 }
11681
11682 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11683 if (!connector->encoder || !connector->encoder->crtc)
11684 continue;
11685
0a9ab303
ACO		 11686 for_each_crtc_in_state(state, crtc, crtc_state, i)
11687 if (crtc == connector->encoder->crtc)
11688 break;
11689
11690 if (crtc != connector->encoder->crtc)
11691 continue;
ea9d758d 11692
a821fc46 11693 if (crtc->state->enable && needs_modeset(crtc->state)) {
68d34720
DV		 11694 struct drm_property *dpms_property =
11695 dev->mode_config.dpms_property;
11696
ea9d758d 11697 connector->dpms = DRM_MODE_DPMS_ON;
662595df 11698 drm_object_property_set_value(&connector->base,
68d34720
DV		 11699 dpms_property,
11700 DRM_MODE_DPMS_ON);
ea9d758d
DV		 11701
11702 intel_encoder = to_intel_encoder(connector->encoder);
11703 intel_encoder->connectors_active = true;
11704 }
11705 }
11706
11707}
11708
3bd26263 11709static bool intel_fuzzy_clock_check(int clock1, int clock2)
f1f644dc 11710{
3bd26263 11711 int diff;
f1f644dc
JB		 11712
11713 if (clock1 == clock2)
11714 return true;
11715
11716 if (!clock1 || !clock2)
11717 return false;
11718
11719 diff = abs(clock1 - clock2);
11720
11721 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
11722 return true;
11723
11724 return false;
11725}
11726
25c5b266
DV		 11727#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
11728 list_for_each_entry((intel_crtc), \
11729 &(dev)->mode_config.crtc_list, \
11730 base.head) \
0973f18f 11731 if (mask & (1 <<(intel_crtc)->pipe))
25c5b266 11732
0e8ffe1b 11733static bool
2fa2fe9a 11734intel_pipe_config_compare(struct drm_device *dev,
5cec258b
ACO		 11735 struct intel_crtc_state *current_config,
11736 struct intel_crtc_state *pipe_config)
0e8ffe1b 11737{
66e985c0
DV		 11738#define PIPE_CONF_CHECK_X(name) \
11739 if (current_config->name != pipe_config->name) { \
11740 DRM_ERROR("mismatch in " #name " " \
11741 "(expected 0x%08x, found 0x%08x)\n", \
11742 current_config->name, \
11743 pipe_config->name); \
11744 return false; \
11745 }
11746
08a24034
DV		 11747#define PIPE_CONF_CHECK_I(name) \
11748 if (current_config->name != pipe_config->name) { \
11749 DRM_ERROR("mismatch in " #name " " \
11750 "(expected %i, found %i)\n", \
11751 current_config->name, \
11752 pipe_config->name); \
11753 return false; \
88adfff1
DV		 11754 }
11755
b95af8be
VK		 11756/* This is required for BDW+ where there is only one set of registers for
11757 * switching between high and low RR.
11758 * This macro can be used whenever a comparison has to be made between one
11759 * hw state and multiple sw state variables.
11760 */
11761#define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
11762 if ((current_config->name != pipe_config->name) && \
11763 (current_config->alt_name != pipe_config->name)) { \
11764 DRM_ERROR("mismatch in " #name " " \
11765 "(expected %i or %i, found %i)\n", \
11766 current_config->name, \
11767 current_config->alt_name, \
11768 pipe_config->name); \
11769 return false; \
11770 }
11771
1bd1bd80
DV		 11772#define PIPE_CONF_CHECK_FLAGS(name, mask) \
11773 if ((current_config->name ^ pipe_config->name) & (mask)) { \
6f02488e 11774 DRM_ERROR("mismatch in " #name "(" #mask ") " \
1bd1bd80
DV		 11775 "(expected %i, found %i)\n", \
11776 current_config->name & (mask), \
11777 pipe_config->name & (mask)); \
11778 return false; \
11779 }
11780
5e550656
VS		 11781#define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
11782 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
11783 DRM_ERROR("mismatch in " #name " " \
11784 "(expected %i, found %i)\n", \
11785 current_config->name, \
11786 pipe_config->name); \
11787 return false; \
11788 }
11789
bb760063
DV		 11790#define PIPE_CONF_QUIRK(quirk) \
11791 ((current_config->quirks | pipe_config->quirks) & (quirk))
11792
eccb140b
DV		 11793 PIPE_CONF_CHECK_I(cpu_transcoder);
11794
08a24034
DV		 11795 PIPE_CONF_CHECK_I(has_pch_encoder);
11796 PIPE_CONF_CHECK_I(fdi_lanes);
72419203
DV		 11797 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
11798 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
11799 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
11800 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
11801 PIPE_CONF_CHECK_I(fdi_m_n.tu);
08a24034 11802
eb14cb74 11803 PIPE_CONF_CHECK_I(has_dp_encoder);
b95af8be
VK		 11804
11805 if (INTEL_INFO(dev)->gen < 8) {
11806 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
11807 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
11808 PIPE_CONF_CHECK_I(dp_m_n.link_m);
11809 PIPE_CONF_CHECK_I(dp_m_n.link_n);
11810 PIPE_CONF_CHECK_I(dp_m_n.tu);
11811
11812 if (current_config->has_drrs) {
11813 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
11814 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
11815 PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
11816 PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
11817 PIPE_CONF_CHECK_I(dp_m2_n2.tu);
11818 }
11819 } else {
11820 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
11821 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
11822 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
11823 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
11824 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
11825 }
eb14cb74 11826
2d112de7
ACO		 11827 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
11828 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
11829 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
11830 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
11831 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
11832 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
1bd1bd80 11833
2d112de7
ACO		 11834 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
11835 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
11836 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
11837 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
11838 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
11839 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
1bd1bd80 11840
c93f54cf 11841 PIPE_CONF_CHECK_I(pixel_multiplier);
6897b4b5 11842 PIPE_CONF_CHECK_I(has_hdmi_sink);
b5a9fa09
DV		 11843 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
11844 IS_VALLEYVIEW(dev))
11845 PIPE_CONF_CHECK_I(limited_color_range);
e43823ec 11846 PIPE_CONF_CHECK_I(has_infoframe);
6c49f241 11847
9ed109a7
DV		 11848 PIPE_CONF_CHECK_I(has_audio);
11849
2d112de7 11850 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
1bd1bd80
DV		 11851 DRM_MODE_FLAG_INTERLACE);
11852
bb760063 11853 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
2d112de7 11854 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 11855 DRM_MODE_FLAG_PHSYNC);
2d112de7 11856 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 11857 DRM_MODE_FLAG_NHSYNC);
2d112de7 11858 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 11859 DRM_MODE_FLAG_PVSYNC);
2d112de7 11860 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063
DV		 11861 DRM_MODE_FLAG_NVSYNC);
11862 }
045ac3b5 11863
37327abd
VS		 11864 PIPE_CONF_CHECK_I(pipe_src_w);
11865 PIPE_CONF_CHECK_I(pipe_src_h);
1bd1bd80 11866
9953599b
DV		 11867 /*
11868 * FIXME: BIOS likes to set up a cloned config with lvds+external
11869 * screen. Since we don't yet re-compute the pipe config when moving
11870 * just the lvds port away to another pipe the sw tracking won't match.
11871 *
11872 * Proper atomic modesets with recomputed global state will fix this.
11873 * Until then just don't check gmch state for inherited modes.
11874 */
11875 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
11876 PIPE_CONF_CHECK_I(gmch_pfit.control);
11877 /* pfit ratios are autocomputed by the hw on gen4+ */
11878 if (INTEL_INFO(dev)->gen < 4)
11879 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
11880 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
11881 }
11882
fd4daa9c
CW		 11883 PIPE_CONF_CHECK_I(pch_pfit.enabled);
11884 if (current_config->pch_pfit.enabled) {
11885 PIPE_CONF_CHECK_I(pch_pfit.pos);
11886 PIPE_CONF_CHECK_I(pch_pfit.size);
11887 }
2fa2fe9a 11888
a1b2278e
CK		 11889 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
11890
e59150dc
JB		 11891 /* BDW+ don't expose a synchronous way to read the state */
11892 if (IS_HASWELL(dev))
11893 PIPE_CONF_CHECK_I(ips_enabled);
42db64ef 11894
282740f7
VS		 11895 PIPE_CONF_CHECK_I(double_wide);
11896
26804afd
DV		 11897 PIPE_CONF_CHECK_X(ddi_pll_sel);
11898
c0d43d62 11899 PIPE_CONF_CHECK_I(shared_dpll);
66e985c0 11900 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8bcc2795 11901 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
66e985c0
DV		 11902 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
11903 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
d452c5b6 11904 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
3f4cd19f
DL		 11905 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
11906 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
11907 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
c0d43d62 11908
42571aef
VS		 11909 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
11910 PIPE_CONF_CHECK_I(pipe_bpp);
11911
2d112de7 11912 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
a9a7e98a 11913 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
5e550656 11914
66e985c0 11915#undef PIPE_CONF_CHECK_X
08a24034 11916#undef PIPE_CONF_CHECK_I
b95af8be 11917#undef PIPE_CONF_CHECK_I_ALT
1bd1bd80 11918#undef PIPE_CONF_CHECK_FLAGS
5e550656 11919#undef PIPE_CONF_CHECK_CLOCK_FUZZY
bb760063 11920#undef PIPE_CONF_QUIRK
88adfff1 11921
0e8ffe1b
DV		 11922 return true;
11923}
11924
08db6652
DL		 11925static void check_wm_state(struct drm_device *dev)
11926{
11927 struct drm_i915_private *dev_priv = dev->dev_private;
11928 struct skl_ddb_allocation hw_ddb, *sw_ddb;
11929 struct intel_crtc *intel_crtc;
11930 int plane;
11931
11932 if (INTEL_INFO(dev)->gen < 9)
11933 return;
11934
11935 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
11936 sw_ddb = &dev_priv->wm.skl_hw.ddb;
11937
11938 for_each_intel_crtc(dev, intel_crtc) {
11939 struct skl_ddb_entry *hw_entry, *sw_entry;
11940 const enum pipe pipe = intel_crtc->pipe;
11941
11942 if (!intel_crtc->active)
11943 continue;
11944
11945 /* planes */
dd740780 11946 for_each_plane(dev_priv, pipe, plane) {
08db6652
DL		 11947 hw_entry = &hw_ddb.plane[pipe][plane];
11948 sw_entry = &sw_ddb->plane[pipe][plane];
11949
11950 if (skl_ddb_entry_equal(hw_entry, sw_entry))
11951 continue;
11952
11953 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
11954 "(expected (%u,%u), found (%u,%u))\n",
11955 pipe_name(pipe), plane + 1,
11956 sw_entry->start, sw_entry->end,
11957 hw_entry->start, hw_entry->end);
11958 }
11959
11960 /* cursor */
11961 hw_entry = &hw_ddb.cursor[pipe];
11962 sw_entry = &sw_ddb->cursor[pipe];
11963
11964 if (skl_ddb_entry_equal(hw_entry, sw_entry))
11965 continue;
11966
11967 DRM_ERROR("mismatch in DDB state pipe %c cursor "
11968 "(expected (%u,%u), found (%u,%u))\n",
11969 pipe_name(pipe),
11970 sw_entry->start, sw_entry->end,
11971 hw_entry->start, hw_entry->end);
11972 }
11973}
11974
91d1b4bd
DV		 11975static void
11976check_connector_state(struct drm_device *dev)
8af6cf88 11977{
8af6cf88
DV		 11978 struct intel_connector *connector;
11979
3a3371ff 11980 for_each_intel_connector(dev, connector) {
8af6cf88
DV		 11981 /* This also checks the encoder/connector hw state with the
11982 * ->get_hw_state callbacks. */
11983 intel_connector_check_state(connector);
11984
e2c719b7 11985 I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder,
8af6cf88
DV		 11986 "connector's staged encoder doesn't match current encoder\n");
11987 }
91d1b4bd
DV		 11988}
11989
11990static void
11991check_encoder_state(struct drm_device *dev)
11992{
11993 struct intel_encoder *encoder;
11994 struct intel_connector *connector;
8af6cf88 11995
b2784e15 11996 for_each_intel_encoder(dev, encoder) {
8af6cf88
DV		 11997 bool enabled = false;
11998 bool active = false;
11999 enum pipe pipe, tracked_pipe;
12000
12001 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12002 encoder->base.base.id,
8e329a03 12003 encoder->base.name);
8af6cf88 12004
e2c719b7 12005 I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc,
8af6cf88 12006 "encoder's stage crtc doesn't match current crtc\n");
e2c719b7 12007 I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc,
8af6cf88
DV		 12008 "encoder's active_connectors set, but no crtc\n");
12009
3a3371ff 12010 for_each_intel_connector(dev, connector) {
8af6cf88
DV		 12011 if (connector->base.encoder != &encoder->base)
12012 continue;
12013 enabled = true;
12014 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
12015 active = true;
12016 }
0e32b39c
DA		 12017 /*
12018 * for MST connectors if we unplug the connector is gone
12019 * away but the encoder is still connected to a crtc
12020 * until a modeset happens in response to the hotplug.
12021 */
12022 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
12023 continue;
12024
e2c719b7 12025 I915_STATE_WARN(!!encoder->base.crtc != enabled,
8af6cf88
DV		 12026 "encoder's enabled state mismatch "
12027 "(expected %i, found %i)\n",
12028 !!encoder->base.crtc, enabled);
e2c719b7 12029 I915_STATE_WARN(active && !encoder->base.crtc,
8af6cf88
DV		 12030 "active encoder with no crtc\n");
12031
e2c719b7 12032 I915_STATE_WARN(encoder->connectors_active != active,
8af6cf88
DV		 12033 "encoder's computed active state doesn't match tracked active state "
12034 "(expected %i, found %i)\n", active, encoder->connectors_active);
12035
12036 active = encoder->get_hw_state(encoder, &pipe);
e2c719b7 12037 I915_STATE_WARN(active != encoder->connectors_active,
8af6cf88
DV		 12038 "encoder's hw state doesn't match sw tracking "
12039 "(expected %i, found %i)\n",
12040 encoder->connectors_active, active);
12041
12042 if (!encoder->base.crtc)
12043 continue;
12044
12045 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
e2c719b7 12046 I915_STATE_WARN(active && pipe != tracked_pipe,
8af6cf88
DV		 12047 "active encoder's pipe doesn't match"
12048 "(expected %i, found %i)\n",
12049 tracked_pipe, pipe);
12050
12051 }
91d1b4bd
DV		 12052}
12053
12054static void
12055check_crtc_state(struct drm_device *dev)
12056{
fbee40df 12057 struct drm_i915_private *dev_priv = dev->dev_private;
91d1b4bd
DV		 12058 struct intel_crtc *crtc;
12059 struct intel_encoder *encoder;
5cec258b 12060 struct intel_crtc_state pipe_config;
8af6cf88 12061
d3fcc808 12062 for_each_intel_crtc(dev, crtc) {
8af6cf88
DV		 12063 bool enabled = false;
12064 bool active = false;
12065
045ac3b5
JB		 12066 memset(&pipe_config, 0, sizeof(pipe_config));
12067
8af6cf88
DV		 12068 DRM_DEBUG_KMS("[CRTC:%d]\n",
12069 crtc->base.base.id);
12070
83d65738 12071 I915_STATE_WARN(crtc->active && !crtc->base.state->enable,
8af6cf88
DV		 12072 "active crtc, but not enabled in sw tracking\n");
12073
b2784e15 12074 for_each_intel_encoder(dev, encoder) {
8af6cf88
DV		 12075 if (encoder->base.crtc != &crtc->base)
12076 continue;
12077 enabled = true;
12078 if (encoder->connectors_active)
12079 active = true;
12080 }
6c49f241 12081
e2c719b7 12082 I915_STATE_WARN(active != crtc->active,
8af6cf88
DV		 12083 "crtc's computed active state doesn't match tracked active state "
12084 "(expected %i, found %i)\n", active, crtc->active);
83d65738 12085 I915_STATE_WARN(enabled != crtc->base.state->enable,
8af6cf88 12086 "crtc's computed enabled state doesn't match tracked enabled state "
83d65738
MR		 12087 "(expected %i, found %i)\n", enabled,
12088 crtc->base.state->enable);
8af6cf88 12089
0e8ffe1b
DV		 12090 active = dev_priv->display.get_pipe_config(crtc,
12091 &pipe_config);
d62cf62a 12092
b6b5d049
VS		 12093 /* hw state is inconsistent with the pipe quirk */
12094 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12095 (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
d62cf62a
DV		 12096 active = crtc->active;
12097
b2784e15 12098 for_each_intel_encoder(dev, encoder) {
3eaba51c 12099 enum pipe pipe;
6c49f241
DV		 12100 if (encoder->base.crtc != &crtc->base)
12101 continue;
1d37b689 12102 if (encoder->get_hw_state(encoder, &pipe))
6c49f241
DV		 12103 encoder->get_config(encoder, &pipe_config);
12104 }
12105
e2c719b7 12106 I915_STATE_WARN(crtc->active != active,
0e8ffe1b
DV		 12107 "crtc active state doesn't match with hw state "
12108 "(expected %i, found %i)\n", crtc->active, active);
12109
c0b03411 12110 if (active &&
6e3c9717 12111 !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) {
e2c719b7 12112 I915_STATE_WARN(1, "pipe state doesn't match!\n");
c0b03411
DV		 12113 intel_dump_pipe_config(crtc, &pipe_config,
12114 "[hw state]");
6e3c9717 12115 intel_dump_pipe_config(crtc, crtc->config,
c0b03411
DV		 12116 "[sw state]");
12117 }
8af6cf88
DV		 12118 }
12119}
12120
91d1b4bd
DV		 12121static void
12122check_shared_dpll_state(struct drm_device *dev)
12123{
fbee40df 12124 struct drm_i915_private *dev_priv = dev->dev_private;
91d1b4bd
DV		 12125 struct intel_crtc *crtc;
12126 struct intel_dpll_hw_state dpll_hw_state;
12127 int i;
5358901f
DV		 12128
12129 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12130 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12131 int enabled_crtcs = 0, active_crtcs = 0;
12132 bool active;
12133
12134 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12135
12136 DRM_DEBUG_KMS("%s\n", pll->name);
12137
12138 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
12139
e2c719b7 12140 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
5358901f 12141 "more active pll users than references: %i vs %i\n",
3e369b76 12142 pll->active, hweight32(pll->config.crtc_mask));
e2c719b7 12143 I915_STATE_WARN(pll->active && !pll->on,
5358901f 12144 "pll in active use but not on in sw tracking\n");
e2c719b7 12145 I915_STATE_WARN(pll->on && !pll->active,
35c95375 12146 "pll in on but not on in use in sw tracking\n");
e2c719b7 12147 I915_STATE_WARN(pll->on != active,
5358901f
DV		 12148 "pll on state mismatch (expected %i, found %i)\n",
12149 pll->on, active);
12150
d3fcc808 12151 for_each_intel_crtc(dev, crtc) {
83d65738 12152 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
5358901f
DV		 12153 enabled_crtcs++;
12154 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12155 active_crtcs++;
12156 }
e2c719b7 12157 I915_STATE_WARN(pll->active != active_crtcs,
5358901f
DV		 12158 "pll active crtcs mismatch (expected %i, found %i)\n",
12159 pll->active, active_crtcs);
e2c719b7 12160 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
5358901f 12161 "pll enabled crtcs mismatch (expected %i, found %i)\n",
3e369b76 12162 hweight32(pll->config.crtc_mask), enabled_crtcs);
66e985c0 12163
e2c719b7 12164 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
66e985c0
DV		 12165 sizeof(dpll_hw_state)),
12166 "pll hw state mismatch\n");
5358901f 12167 }
8af6cf88
DV		 12168}
12169
91d1b4bd
DV		 12170void
12171intel_modeset_check_state(struct drm_device *dev)
12172{
08db6652 12173 check_wm_state(dev);
91d1b4bd
DV		 12174 check_connector_state(dev);
12175 check_encoder_state(dev);
12176 check_crtc_state(dev);
12177 check_shared_dpll_state(dev);
12178}
12179
5cec258b 12180void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
18442d08
VS		 12181 int dotclock)
12182{
12183 /*
12184 * FDI already provided one idea for the dotclock.
12185 * Yell if the encoder disagrees.
12186 */
2d112de7 12187 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
18442d08 12188 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
2d112de7 12189 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
18442d08
VS		 12190}
12191
80715b2f
VS		 12192static void update_scanline_offset(struct intel_crtc *crtc)
12193{
12194 struct drm_device *dev = crtc->base.dev;
12195
12196 /*
12197 * The scanline counter increments at the leading edge of hsync.
12198 *
12199 * On most platforms it starts counting from vtotal-1 on the
12200 * first active line. That means the scanline counter value is
12201 * always one less than what we would expect. Ie. just after
12202 * start of vblank, which also occurs at start of hsync (on the
12203 * last active line), the scanline counter will read vblank_start-1.
12204 *
12205 * On gen2 the scanline counter starts counting from 1 instead
12206 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12207 * to keep the value positive), instead of adding one.
12208 *
12209 * On HSW+ the behaviour of the scanline counter depends on the output
12210 * type. For DP ports it behaves like most other platforms, but on HDMI
12211 * there's an extra 1 line difference. So we need to add two instead of
12212 * one to the value.
12213 */
12214 if (IS_GEN2(dev)) {
6e3c9717 12215 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
80715b2f
VS		 12216 int vtotal;
12217
12218 vtotal = mode->crtc_vtotal;
12219 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
12220 vtotal /= 2;
12221
12222 crtc->scanline_offset = vtotal - 1;
12223 } else if (HAS_DDI(dev) &&
409ee761 12224 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
80715b2f
VS		 12225 crtc->scanline_offset = 2;
12226 } else
12227 crtc->scanline_offset = 1;
12228}
12229
5cec258b 12230static struct intel_crtc_state *
7f27126e 12231intel_modeset_compute_config(struct drm_crtc *crtc,
0a9ab303 12232 struct drm_atomic_state *state)
7f27126e 12233{
548ee15b 12234 struct intel_crtc_state *pipe_config;
0b901879
ACO		 12235 int ret = 0;
12236
12237 ret = drm_atomic_add_affected_connectors(state, crtc);
12238 if (ret)
12239 return ERR_PTR(ret);
7f27126e 12240
8c7b5ccb
ACO		 12241 ret = drm_atomic_helper_check_modeset(state->dev, state);
12242 if (ret)
12243 return ERR_PTR(ret);
7f27126e 12244
7f27126e
JB		 12245 /*
12246 * Note this needs changes when we start tracking multiple modes
12247 * and crtcs. At that point we'll need to compute the whole config
12248 * (i.e. one pipe_config for each crtc) rather than just the one
12249 * for this crtc.
12250 */
548ee15b
ACO		 12251 pipe_config = intel_atomic_get_crtc_state(state, to_intel_crtc(crtc));
12252 if (IS_ERR(pipe_config))
12253 return pipe_config;
83a57153 12254
4fed33f6 12255 if (!pipe_config->base.enable)
548ee15b 12256 return pipe_config;
7f27126e 12257
8c7b5ccb 12258 ret = intel_modeset_pipe_config(crtc, state, pipe_config);
548ee15b
ACO		 12259 if (ret)
12260 return ERR_PTR(ret);
12261
8d8c9b51
ACO		 12262 /* Check things that can only be changed through modeset */
12263 if (pipe_config->has_audio !=
12264 to_intel_crtc(crtc)->config->has_audio)
12265 pipe_config->base.mode_changed = true;
12266
12267 /*
12268 * Note we have an issue here with infoframes: current code
12269 * only updates them on the full mode set path per hw
12270 * requirements. So here we should be checking for any
12271 * required changes and forcing a mode set.
12272 */
12273
548ee15b 12274 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,"[modeset]");
db7542dd 12275
8c7b5ccb
ACO		 12276 ret = drm_atomic_helper_check_planes(state->dev, state);
12277 if (ret)
12278 return ERR_PTR(ret);
12279
548ee15b 12280 return pipe_config;
7f27126e
JB		 12281}
12282
0a9ab303 12283static int __intel_set_mode_setup_plls(struct drm_atomic_state *state)
ed6739ef 12284{
225da59b 12285 struct drm_device *dev = state->dev;
ed6739ef 12286 struct drm_i915_private *dev_priv = to_i915(dev);
0a9ab303 12287 unsigned clear_pipes = 0;
ed6739ef 12288 struct intel_crtc *intel_crtc;
0a9ab303
ACO		 12289 struct intel_crtc_state *intel_crtc_state;
12290 struct drm_crtc *crtc;
12291 struct drm_crtc_state *crtc_state;
ed6739ef 12292 int ret = 0;
0a9ab303 12293 int i;
ed6739ef
ACO		 12294
12295 if (!dev_priv->display.crtc_compute_clock)
12296 return 0;
12297
0a9ab303
ACO		 12298 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12299 intel_crtc = to_intel_crtc(crtc);
4978cc93 12300 intel_crtc_state = to_intel_crtc_state(crtc_state);
0a9ab303 12301
4978cc93 12302 if (needs_modeset(crtc_state)) {
0a9ab303 12303 clear_pipes |= 1 << intel_crtc->pipe;
4978cc93 12304 intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
4978cc93 12305 }
0a9ab303
ACO		 12306 }
12307
ed6739ef
ACO		 12308 ret = intel_shared_dpll_start_config(dev_priv, clear_pipes);
12309 if (ret)
12310 goto done;
12311
0a9ab303
ACO		 12312 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12313 if (!needs_modeset(crtc_state) || !crtc_state->enable)
225da59b
ACO		 12314 continue;
12315
0a9ab303
ACO		 12316 intel_crtc = to_intel_crtc(crtc);
12317 intel_crtc_state = to_intel_crtc_state(crtc_state);
12318
ed6739ef 12319 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
0a9ab303 12320 intel_crtc_state);
ed6739ef
ACO		 12321 if (ret) {
12322 intel_shared_dpll_abort_config(dev_priv);
12323 goto done;
12324 }
12325 }
12326
12327done:
12328 return ret;
12329}
12330
054518dd
ACO		 12331/* Code that should eventually be part of atomic_check() */
12332static int __intel_set_mode_checks(struct drm_atomic_state *state)
12333{
12334 struct drm_device *dev = state->dev;
12335 int ret;
12336
12337 /*
12338 * See if the config requires any additional preparation, e.g.
12339 * to adjust global state with pipes off. We need to do this
12340 * here so we can get the modeset_pipe updated config for the new
12341 * mode set on this crtc. For other crtcs we need to use the
12342 * adjusted_mode bits in the crtc directly.
12343 */
12344 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
12345 ret = valleyview_modeset_global_pipes(state);
12346 if (ret)
12347 return ret;
12348 }
12349
12350 ret = __intel_set_mode_setup_plls(state);
12351 if (ret)
12352 return ret;
12353
12354 return 0;
12355}
12356
0a9ab303 12357static int __intel_set_mode(struct drm_crtc *modeset_crtc,
0a9ab303 12358 struct intel_crtc_state *pipe_config)
a6778b3c 12359{
0a9ab303 12360 struct drm_device *dev = modeset_crtc->dev;
fbee40df 12361 struct drm_i915_private *dev_priv = dev->dev_private;
304603f4 12362 struct drm_atomic_state *state = pipe_config->base.state;
0a9ab303
ACO		 12363 struct drm_crtc *crtc;
12364 struct drm_crtc_state *crtc_state;
c0c36b94 12365 int ret = 0;
0a9ab303 12366 int i;
a6778b3c 12367
054518dd
ACO		 12368 ret = __intel_set_mode_checks(state);
12369 if (ret < 0)
12370 return ret;
12371
d4afb8cc
ACO		 12372 ret = drm_atomic_helper_prepare_planes(dev, state);
12373 if (ret)
12374 return ret;
12375
0a9ab303
ACO		 12376 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12377 if (!needs_modeset(crtc_state))
12378 continue;
460da916 12379
0a9ab303
ACO		 12380 if (!crtc_state->enable) {
12381 intel_crtc_disable(crtc);
12382 } else if (crtc->state->enable) {
12383 intel_crtc_disable_planes(crtc);
12384 dev_priv->display.crtc_disable(crtc);
ce22dba9 12385 }
ea9d758d 12386 }
a6778b3c 12387
6c4c86f5
DV		 12388 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
12389 * to set it here already despite that we pass it down the callchain.
7f27126e
JB		 12390 *
12391 * Note we'll need to fix this up when we start tracking multiple
12392 * pipes; here we assume a single modeset_pipe and only track the
12393 * single crtc and mode.
f6e5b160 12394 */
0a9ab303 12395 if (pipe_config->base.enable && needs_modeset(&pipe_config->base)) {
8c7b5ccb 12396 modeset_crtc->mode = pipe_config->base.mode;
c326c0a9
VS		 12397
12398 /*
12399 * Calculate and store various constants which
12400 * are later needed by vblank and swap-completion
12401 * timestamping. They are derived from true hwmode.
12402 */
0a9ab303 12403 drm_calc_timestamping_constants(modeset_crtc,
2d112de7 12404 &pipe_config->base.adjusted_mode);
b8cecdf5 12405 }
7758a113 12406
ea9d758d
DV		 12407 /* Only after disabling all output pipelines that will be changed can we
12408 * update the the output configuration. */
0a9ab303 12409 intel_modeset_update_state(state);
f6e5b160 12410
a821fc46
ACO		 12411 /* The state has been swaped above, so state actually contains the
12412 * old state now. */
12413
304603f4 12414 modeset_update_crtc_power_domains(state);
47fab737 12415
d4afb8cc 12416 drm_atomic_helper_commit_planes(dev, state);
a6778b3c
DV		 12417
12418 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
0a9ab303 12419 for_each_crtc_in_state(state, crtc, crtc_state, i) {
a821fc46 12420 if (!needs_modeset(crtc->state) || !crtc->state->enable)
0a9ab303
ACO		 12421 continue;
12422
12423 update_scanline_offset(to_intel_crtc(crtc));
80715b2f 12424
0a9ab303
ACO		 12425 dev_priv->display.crtc_enable(crtc);
12426 intel_crtc_enable_planes(crtc);
80715b2f 12427 }
a6778b3c 12428
a6778b3c 12429 /* FIXME: add subpixel order */
83a57153 12430
d4afb8cc
ACO		 12431 drm_atomic_helper_cleanup_planes(dev, state);
12432
2bfb4627
ACO		 12433 drm_atomic_state_free(state);
12434
9eb45f22 12435 return 0;
f6e5b160
CW		 12436}
12437
0a9ab303 12438static int intel_set_mode_with_config(struct drm_crtc *crtc,
0a9ab303 12439 struct intel_crtc_state *pipe_config)
f30da187
DV		 12440{
12441 int ret;
12442
8c7b5ccb 12443 ret = __intel_set_mode(crtc, pipe_config);
f30da187
DV		 12444
12445 if (ret == 0)
12446 intel_modeset_check_state(crtc->dev);
12447
12448 return ret;
12449}
12450
7f27126e 12451static int intel_set_mode(struct drm_crtc *crtc,
83a57153 12452 struct drm_atomic_state *state)
7f27126e 12453{
5cec258b 12454 struct intel_crtc_state *pipe_config;
83a57153 12455 int ret = 0;
7f27126e 12456
8c7b5ccb 12457 pipe_config = intel_modeset_compute_config(crtc, state);
83a57153
ACO		 12458 if (IS_ERR(pipe_config)) {
12459 ret = PTR_ERR(pipe_config);
12460 goto out;
12461 }
12462
8c7b5ccb 12463 ret = intel_set_mode_with_config(crtc, pipe_config);
83a57153
ACO		 12464 if (ret)
12465 goto out;
7f27126e 12466
83a57153
ACO		 12467out:
12468 return ret;
7f27126e
JB		 12469}
12470
c0c36b94
CW		 12471void intel_crtc_restore_mode(struct drm_crtc *crtc)
12472{
83a57153
ACO		 12473 struct drm_device *dev = crtc->dev;
12474 struct drm_atomic_state *state;
4be07317 12475 struct intel_crtc *intel_crtc;
83a57153
ACO		 12476 struct intel_encoder *encoder;
12477 struct intel_connector *connector;
12478 struct drm_connector_state *connector_state;
4be07317 12479 struct intel_crtc_state *crtc_state;
2bfb4627 12480 int ret;
83a57153
ACO		 12481
12482 state = drm_atomic_state_alloc(dev);
12483 if (!state) {
12484 DRM_DEBUG_KMS("[CRTC:%d] mode restore failed, out of memory",
12485 crtc->base.id);
12486 return;
12487 }
12488
12489 state->acquire_ctx = dev->mode_config.acquire_ctx;
12490
12491 /* The force restore path in the HW readout code relies on the staged
12492 * config still keeping the user requested config while the actual
12493 * state has been overwritten by the configuration read from HW. We
12494 * need to copy the staged config to the atomic state, otherwise the
12495 * mode set will just reapply the state the HW is already in. */
12496 for_each_intel_encoder(dev, encoder) {
12497 if (&encoder->new_crtc->base != crtc)
12498 continue;
12499
12500 for_each_intel_connector(dev, connector) {
12501 if (connector->new_encoder != encoder)
12502 continue;
12503
12504 connector_state = drm_atomic_get_connector_state(state, &connector->base);
12505 if (IS_ERR(connector_state)) {
12506 DRM_DEBUG_KMS("Failed to add [CONNECTOR:%d:%s] to state: %ld\n",
12507 connector->base.base.id,
12508 connector->base.name,
12509 PTR_ERR(connector_state));
12510 continue;
12511 }
12512
12513 connector_state->crtc = crtc;
12514 connector_state->best_encoder = &encoder->base;
12515 }
12516 }
12517
4be07317
ACO		 12518 for_each_intel_crtc(dev, intel_crtc) {
12519 if (intel_crtc->new_enabled == intel_crtc->base.enabled)
12520 continue;
12521
12522 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
12523 if (IS_ERR(crtc_state)) {
12524 DRM_DEBUG_KMS("Failed to add [CRTC:%d] to state: %ld\n",
12525 intel_crtc->base.base.id,
12526 PTR_ERR(crtc_state));
12527 continue;
12528 }
12529
49d6fa21
ML		 12530 crtc_state->base.active = crtc_state->base.enable =
12531 intel_crtc->new_enabled;
8c7b5ccb
ACO		 12532
12533 if (&intel_crtc->base == crtc)
12534 drm_mode_copy(&crtc_state->base.mode, &crtc->mode);
4be07317
ACO		 12535 }
12536
d3a40d1b
ACO		 12537 intel_modeset_setup_plane_state(state, crtc, &crtc->mode,
12538 crtc->primary->fb, crtc->x, crtc->y);
12539
2bfb4627
ACO		 12540 ret = intel_set_mode(crtc, state);
12541 if (ret)
12542 drm_atomic_state_free(state);
c0c36b94
CW		 12543}
12544
25c5b266
DV		 12545#undef for_each_intel_crtc_masked
12546
b7885264
ACO		 12547static bool intel_connector_in_mode_set(struct intel_connector *connector,
12548 struct drm_mode_set *set)
12549{
12550 int ro;
12551
12552 for (ro = 0; ro < set->num_connectors; ro++)
12553 if (set->connectors[ro] == &connector->base)
12554 return true;
12555
12556 return false;
12557}
12558
2e431051 12559static int
9a935856
DV		 12560intel_modeset_stage_output_state(struct drm_device *dev,
12561 struct drm_mode_set *set,
944b0c76 12562 struct drm_atomic_state *state)
50f56119 12563{
9a935856 12564 struct intel_connector *connector;
d5432a9d 12565 struct drm_connector *drm_connector;
944b0c76 12566 struct drm_connector_state *connector_state;
d5432a9d
ACO		 12567 struct drm_crtc *crtc;
12568 struct drm_crtc_state *crtc_state;
12569 int i, ret;
50f56119 12570
9abdda74 12571 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 12572 * of connectors. For paranoia, double-check this. */
12573 WARN_ON(!set->fb && (set->num_connectors != 0));
12574 WARN_ON(set->fb && (set->num_connectors == 0));
12575
3a3371ff 12576 for_each_intel_connector(dev, connector) {
b7885264
ACO		 12577 bool in_mode_set = intel_connector_in_mode_set(connector, set);
12578
d5432a9d
ACO		 12579 if (!in_mode_set && connector->base.state->crtc != set->crtc)
12580 continue;
12581
12582 connector_state =
12583 drm_atomic_get_connector_state(state, &connector->base);
12584 if (IS_ERR(connector_state))
12585 return PTR_ERR(connector_state);
12586
b7885264
ACO		 12587 if (in_mode_set) {
12588 int pipe = to_intel_crtc(set->crtc)->pipe;
d5432a9d
ACO		 12589 connector_state->best_encoder =
12590 &intel_find_encoder(connector, pipe)->base;
50f56119
DV		 12591 }
12592
d5432a9d 12593 if (connector->base.state->crtc != set->crtc)
b7885264
ACO		 12594 continue;
12595
9a935856
DV		 12596 /* If we disable the crtc, disable all its connectors. Also, if
12597 * the connector is on the changing crtc but not on the new
12598 * connector list, disable it. */
b7885264 12599 if (!set->fb || !in_mode_set) {
d5432a9d 12600 connector_state->best_encoder = NULL;
9a935856
DV		 12601
12602 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
12603 connector->base.base.id,
c23cc417 12604 connector->base.name);
9a935856 12605 }
50f56119 12606 }
9a935856 12607 /* connector->new_encoder is now updated for all connectors. */
50f56119 12608
d5432a9d
ACO		 12609 for_each_connector_in_state(state, drm_connector, connector_state, i) {
12610 connector = to_intel_connector(drm_connector);
12611
12612 if (!connector_state->best_encoder) {
12613 ret = drm_atomic_set_crtc_for_connector(connector_state,
12614 NULL);
12615 if (ret)
12616 return ret;
7668851f 12617
50f56119 12618 continue;
d5432a9d 12619 }
50f56119 12620
d5432a9d
ACO		 12621 if (intel_connector_in_mode_set(connector, set)) {
12622 struct drm_crtc *crtc = connector->base.state->crtc;
12623
12624 /* If this connector was in a previous crtc, add it
12625 * to the state. We might need to disable it. */
12626 if (crtc) {
12627 crtc_state =
12628 drm_atomic_get_crtc_state(state, crtc);
12629 if (IS_ERR(crtc_state))
12630 return PTR_ERR(crtc_state);
12631 }
12632
12633 ret = drm_atomic_set_crtc_for_connector(connector_state,
12634 set->crtc);
12635 if (ret)
12636 return ret;
12637 }
50f56119
DV		 12638
12639 /* Make sure the new CRTC will work with the encoder */
d5432a9d
ACO		 12640 if (!drm_encoder_crtc_ok(connector_state->best_encoder,
12641 connector_state->crtc)) {
5e2b584e 12642 return -EINVAL;
50f56119 12643 }
944b0c76 12644
9a935856
DV		 12645 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
12646 connector->base.base.id,
c23cc417 12647 connector->base.name,
d5432a9d 12648 connector_state->crtc->base.id);
944b0c76 12649
d5432a9d
ACO		 12650 if (connector_state->best_encoder != &connector->encoder->base)
12651 connector->encoder =
12652 to_intel_encoder(connector_state->best_encoder);
0e32b39c 12653 }
7668851f 12654
d5432a9d 12655 for_each_crtc_in_state(state, crtc, crtc_state, i) {
49d6fa21
ML		 12656 bool has_connectors;
12657
d5432a9d
ACO		 12658 ret = drm_atomic_add_affected_connectors(state, crtc);
12659 if (ret)
12660 return ret;
4be07317 12661
49d6fa21
ML		 12662 has_connectors = !!drm_atomic_connectors_for_crtc(state, crtc);
12663 if (has_connectors != crtc_state->enable)
12664 crtc_state->enable =
12665 crtc_state->active = has_connectors;
7668851f
VS		 12666 }
12667
8c7b5ccb
ACO		 12668 ret = intel_modeset_setup_plane_state(state, set->crtc, set->mode,
12669 set->fb, set->x, set->y);
12670 if (ret)
12671 return ret;
12672
12673 crtc_state = drm_atomic_get_crtc_state(state, set->crtc);
12674 if (IS_ERR(crtc_state))
12675 return PTR_ERR(crtc_state);
12676
12677 if (set->mode)
12678 drm_mode_copy(&crtc_state->mode, set->mode);
12679
12680 if (set->num_connectors)
12681 crtc_state->active = true;
12682
2e431051
DV		 12683 return 0;
12684}
12685
bb546623
ACO		 12686static bool primary_plane_visible(struct drm_crtc *crtc)
12687{
12688 struct intel_plane_state *plane_state =
12689 to_intel_plane_state(crtc->primary->state);
12690
12691 return plane_state->visible;
12692}
12693
2e431051
DV		 12694static int intel_crtc_set_config(struct drm_mode_set *set)
12695{
12696 struct drm_device *dev;
83a57153 12697 struct drm_atomic_state *state = NULL;
5cec258b 12698 struct intel_crtc_state *pipe_config;
bb546623 12699 bool primary_plane_was_visible;
2e431051 12700 int ret;
2e431051 12701
8d3e375e
DV		 12702 BUG_ON(!set);
12703 BUG_ON(!set->crtc);
12704 BUG_ON(!set->crtc->helper_private);
2e431051 12705
7e53f3a4
DV		 12706 /* Enforce sane interface api - has been abused by the fb helper. */
12707 BUG_ON(!set->mode && set->fb);
12708 BUG_ON(set->fb && set->num_connectors == 0);
431e50f7 12709
2e431051
DV		 12710 if (set->fb) {
12711 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
12712 set->crtc->base.id, set->fb->base.id,
12713 (int)set->num_connectors, set->x, set->y);
12714 } else {
12715 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 12716 }
12717
12718 dev = set->crtc->dev;
12719
83a57153 12720 state = drm_atomic_state_alloc(dev);
7cbf41d6
ACO		 12721 if (!state)
12722 return -ENOMEM;
83a57153
ACO		 12723
12724 state->acquire_ctx = dev->mode_config.acquire_ctx;
12725
462a425a 12726 ret = intel_modeset_stage_output_state(dev, set, state);
2e431051 12727 if (ret)
7cbf41d6 12728 goto out;
2e431051 12729
8c7b5ccb 12730 pipe_config = intel_modeset_compute_config(set->crtc, state);
20664591 12731 if (IS_ERR(pipe_config)) {
6ac0483b 12732 ret = PTR_ERR(pipe_config);
7cbf41d6 12733 goto out;
20664591 12734 }
50f52756 12735
1f9954d0
JB		 12736 intel_update_pipe_size(to_intel_crtc(set->crtc));
12737
bb546623
ACO		 12738 primary_plane_was_visible = primary_plane_visible(set->crtc);
12739
8c7b5ccb 12740 ret = intel_set_mode_with_config(set->crtc, pipe_config);
bb546623
ACO		 12741
12742 if (ret == 0 &&
12743 pipe_config->base.enable &&
12744 pipe_config->base.planes_changed &&
12745 !needs_modeset(&pipe_config->base)) {
3b150f08 12746 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
3b150f08
MR		 12747
12748 /*
12749 * We need to make sure the primary plane is re-enabled if it
12750 * has previously been turned off.
12751 */
bb546623
ACO		 12752 if (ret == 0 && !primary_plane_was_visible &&
12753 primary_plane_visible(set->crtc)) {
3b150f08 12754 WARN_ON(!intel_crtc->active);
87d4300a 12755 intel_post_enable_primary(set->crtc);
3b150f08
MR		 12756 }
12757
7ca51a3a
JB		 12758 /*
12759 * In the fastboot case this may be our only check of the
12760 * state after boot. It would be better to only do it on
12761 * the first update, but we don't have a nice way of doing that
12762 * (and really, set_config isn't used much for high freq page
12763 * flipping, so increasing its cost here shouldn't be a big
12764 * deal).
12765 */
d330a953 12766 if (i915.fastboot && ret == 0)
7ca51a3a 12767 intel_modeset_check_state(set->crtc->dev);
50f56119
DV		 12768 }
12769
2d05eae1 12770 if (ret) {
bf67dfeb
DV		 12771 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
12772 set->crtc->base.id, ret);
2d05eae1 12773 }
50f56119 12774
7cbf41d6 12775out:
2bfb4627
ACO		 12776 if (ret)
12777 drm_atomic_state_free(state);
50f56119
DV		 12778 return ret;
12779}
f6e5b160
CW		 12780
12781static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160 12782 .gamma_set = intel_crtc_gamma_set,
50f56119 12783 .set_config = intel_crtc_set_config,
f6e5b160
CW		 12784 .destroy = intel_crtc_destroy,
12785 .page_flip = intel_crtc_page_flip,
1356837e
MR		 12786 .atomic_duplicate_state = intel_crtc_duplicate_state,
12787 .atomic_destroy_state = intel_crtc_destroy_state,
f6e5b160
CW		 12788};
12789
5358901f
DV		 12790static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
12791 struct intel_shared_dpll *pll,
12792 struct intel_dpll_hw_state *hw_state)
ee7b9f93 12793{
5358901f 12794 uint32_t val;
ee7b9f93 12795
f458ebbc 12796 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
bd2bb1b9
PZ		 12797 return false;
12798
5358901f 12799 val = I915_READ(PCH_DPLL(pll->id));
66e985c0
DV		 12800 hw_state->dpll = val;
12801 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
12802 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
5358901f
DV		 12803
12804 return val & DPLL_VCO_ENABLE;
12805}
12806
15bdd4cf
DV		 12807static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
12808 struct intel_shared_dpll *pll)
12809{
3e369b76
ACO		 12810 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
12811 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
15bdd4cf
DV		 12812}
12813
e7b903d2
DV		 12814static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
12815 struct intel_shared_dpll *pll)
12816{
e7b903d2 12817 /* PCH refclock must be enabled first */
89eff4be 12818 ibx_assert_pch_refclk_enabled(dev_priv);
e7b903d2 12819
3e369b76 12820 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
15bdd4cf
DV		 12821
12822 /* Wait for the clocks to stabilize. */
12823 POSTING_READ(PCH_DPLL(pll->id));
12824 udelay(150);
12825
12826 /* The pixel multiplier can only be updated once the
12827 * DPLL is enabled and the clocks are stable.
12828 *
12829 * So write it again.
12830 */
3e369b76 12831 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
15bdd4cf 12832 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 12833 udelay(200);
12834}
12835
12836static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
12837 struct intel_shared_dpll *pll)
12838{
12839 struct drm_device *dev = dev_priv->dev;
12840 struct intel_crtc *crtc;
e7b903d2
DV		 12841
12842 /* Make sure no transcoder isn't still depending on us. */
d3fcc808 12843 for_each_intel_crtc(dev, crtc) {
e7b903d2
DV		 12844 if (intel_crtc_to_shared_dpll(crtc) == pll)
12845 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
ee7b9f93
JB		 12846 }
12847
15bdd4cf
DV		 12848 I915_WRITE(PCH_DPLL(pll->id), 0);
12849 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 12850 udelay(200);
12851}
12852
46edb027
DV		 12853static char *ibx_pch_dpll_names[] = {
12854 "PCH DPLL A",
12855 "PCH DPLL B",
12856};
12857
7c74ade1 12858static void ibx_pch_dpll_init(struct drm_device *dev)
ee7b9f93 12859{
e7b903d2 12860 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93
JB		 12861 int i;
12862
7c74ade1 12863 dev_priv->num_shared_dpll = 2;
ee7b9f93 12864
e72f9fbf 12865 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
46edb027
DV		 12866 dev_priv->shared_dplls[i].id = i;
12867 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
15bdd4cf 12868 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
e7b903d2
DV		 12869 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
12870 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
5358901f
DV		 12871 dev_priv->shared_dplls[i].get_hw_state =
12872 ibx_pch_dpll_get_hw_state;
ee7b9f93
JB		 12873 }
12874}
12875
7c74ade1
DV		 12876static void intel_shared_dpll_init(struct drm_device *dev)
12877{
e7b903d2 12878 struct drm_i915_private *dev_priv = dev->dev_private;
7c74ade1 12879
9cd86933
DV		 12880 if (HAS_DDI(dev))
12881 intel_ddi_pll_init(dev);
12882 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7c74ade1
DV		 12883 ibx_pch_dpll_init(dev);
12884 else
12885 dev_priv->num_shared_dpll = 0;
12886
12887 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
7c74ade1
DV		 12888}
12889
1fc0a8f7
TU		 12890/**
12891 * intel_wm_need_update - Check whether watermarks need updating
12892 * @plane: drm plane
12893 * @state: new plane state
12894 *
12895 * Check current plane state versus the new one to determine whether
12896 * watermarks need to be recalculated.
12897 *
12898 * Returns true or false.
12899 */
12900bool intel_wm_need_update(struct drm_plane *plane,
12901 struct drm_plane_state *state)
12902{
12903 /* Update watermarks on tiling changes. */
12904 if (!plane->state->fb || !state->fb ||
12905 plane->state->fb->modifier[0] != state->fb->modifier[0] ||
12906 plane->state->rotation != state->rotation)
12907 return true;
12908
12909 return false;
12910}
12911
6beb8c23
MR		 12912/**
12913 * intel_prepare_plane_fb - Prepare fb for usage on plane
12914 * @plane: drm plane to prepare for
12915 * @fb: framebuffer to prepare for presentation
12916 *
12917 * Prepares a framebuffer for usage on a display plane. Generally this
12918 * involves pinning the underlying object and updating the frontbuffer tracking
12919 * bits. Some older platforms need special physical address handling for
12920 * cursor planes.
12921 *
12922 * Returns 0 on success, negative error code on failure.
12923 */
12924int
12925intel_prepare_plane_fb(struct drm_plane *plane,
d136dfee
TU		 12926 struct drm_framebuffer *fb,
12927 const struct drm_plane_state *new_state)
465c120c
MR		 12928{
12929 struct drm_device *dev = plane->dev;
6beb8c23
MR		 12930 struct intel_plane *intel_plane = to_intel_plane(plane);
12931 enum pipe pipe = intel_plane->pipe;
12932 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12933 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
12934 unsigned frontbuffer_bits = 0;
12935 int ret = 0;
465c120c 12936
ea2c67bb 12937 if (!obj)
465c120c
MR		 12938 return 0;
12939
6beb8c23
MR		 12940 switch (plane->type) {
12941 case DRM_PLANE_TYPE_PRIMARY:
12942 frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(pipe);
12943 break;
12944 case DRM_PLANE_TYPE_CURSOR:
12945 frontbuffer_bits = INTEL_FRONTBUFFER_CURSOR(pipe);
12946 break;
12947 case DRM_PLANE_TYPE_OVERLAY:
12948 frontbuffer_bits = INTEL_FRONTBUFFER_SPRITE(pipe);
12949 break;
12950 }
465c120c 12951
6beb8c23 12952 mutex_lock(&dev->struct_mutex);
465c120c 12953
6beb8c23
MR		 12954 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
12955 INTEL_INFO(dev)->cursor_needs_physical) {
12956 int align = IS_I830(dev) ? 16 * 1024 : 256;
12957 ret = i915_gem_object_attach_phys(obj, align);
12958 if (ret)
12959 DRM_DEBUG_KMS("failed to attach phys object\n");
12960 } else {
82bc3b2d 12961 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL);
6beb8c23 12962 }
465c120c 12963
6beb8c23
MR		 12964 if (ret == 0)
12965 i915_gem_track_fb(old_obj, obj, frontbuffer_bits);
fdd508a6 12966
4c34574f 12967 mutex_unlock(&dev->struct_mutex);
465c120c 12968
6beb8c23
MR		 12969 return ret;
12970}
12971
38f3ce3a
MR		 12972/**
12973 * intel_cleanup_plane_fb - Cleans up an fb after plane use
12974 * @plane: drm plane to clean up for
12975 * @fb: old framebuffer that was on plane
12976 *
12977 * Cleans up a framebuffer that has just been removed from a plane.
12978 */
12979void
12980intel_cleanup_plane_fb(struct drm_plane *plane,
d136dfee
TU		 12981 struct drm_framebuffer *fb,
12982 const struct drm_plane_state *old_state)
38f3ce3a
MR		 12983{
12984 struct drm_device *dev = plane->dev;
12985 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12986
12987 if (WARN_ON(!obj))
12988 return;
12989
12990 if (plane->type != DRM_PLANE_TYPE_CURSOR ||
12991 !INTEL_INFO(dev)->cursor_needs_physical) {
12992 mutex_lock(&dev->struct_mutex);
82bc3b2d 12993 intel_unpin_fb_obj(fb, old_state);
38f3ce3a
MR		 12994 mutex_unlock(&dev->struct_mutex);
12995 }
465c120c
MR		 12996}
12997
6156a456
CK		 12998int
12999skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13000{
13001 int max_scale;
13002 struct drm_device *dev;
13003 struct drm_i915_private *dev_priv;
13004 int crtc_clock, cdclk;
13005
13006 if (!intel_crtc || !crtc_state)
13007 return DRM_PLANE_HELPER_NO_SCALING;
13008
13009 dev = intel_crtc->base.dev;
13010 dev_priv = dev->dev_private;
13011 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13012 cdclk = dev_priv->display.get_display_clock_speed(dev);
13013
13014 if (!crtc_clock || !cdclk)
13015 return DRM_PLANE_HELPER_NO_SCALING;
13016
13017 /*
13018 * skl max scale is lower of:
13019 * close to 3 but not 3, -1 is for that purpose
13020 * or
13021 * cdclk/crtc_clock
13022 */
13023 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13024
13025 return max_scale;
13026}
13027
465c120c 13028static int
3c692a41
GP		 13029intel_check_primary_plane(struct drm_plane *plane,
13030 struct intel_plane_state *state)
13031{
32b7eeec
MR		 13032 struct drm_device *dev = plane->dev;
13033 struct drm_i915_private *dev_priv = dev->dev_private;
2b875c22 13034 struct drm_crtc *crtc = state->base.crtc;
ea2c67bb 13035 struct intel_crtc *intel_crtc;
6156a456 13036 struct intel_crtc_state *crtc_state;
2b875c22 13037 struct drm_framebuffer *fb = state->base.fb;
3c692a41
GP		 13038 struct drm_rect *dest = &state->dst;
13039 struct drm_rect *src = &state->src;
13040 const struct drm_rect *clip = &state->clip;
d8106366 13041 bool can_position = false;
6156a456
CK		 13042 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13043 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
465c120c
MR		 13044 int ret;
13045
ea2c67bb
MR		 13046 crtc = crtc ? crtc : plane->crtc;
13047 intel_crtc = to_intel_crtc(crtc);
6156a456
CK		 13048 crtc_state = state->base.state ?
13049 intel_atomic_get_crtc_state(state->base.state, intel_crtc) : NULL;
ea2c67bb 13050
6156a456
CK		 13051 if (INTEL_INFO(dev)->gen >= 9) {
13052 min_scale = 1;
13053 max_scale = skl_max_scale(intel_crtc, crtc_state);
d8106366 13054 can_position = true;
6156a456 13055 }
d8106366 13056
c59cb179
MR		 13057 ret = drm_plane_helper_check_update(plane, crtc, fb,
13058 src, dest, clip,
6156a456
CK		 13059 min_scale,
13060 max_scale,
d8106366
SJ		 13061 can_position, true,
13062 &state->visible);
c59cb179
MR		 13063 if (ret)
13064 return ret;
465c120c 13065
32b7eeec 13066 if (intel_crtc->active) {
b70709a6
ML		 13067 struct intel_plane_state *old_state =
13068 to_intel_plane_state(plane->state);
13069
32b7eeec
MR		 13070 intel_crtc->atomic.wait_for_flips = true;
13071
13072 /*
13073 * FBC does not work on some platforms for rotated
13074 * planes, so disable it when rotation is not 0 and
13075 * update it when rotation is set back to 0.
13076 *
13077 * FIXME: This is redundant with the fbc update done in
13078 * the primary plane enable function except that that
13079 * one is done too late. We eventually need to unify
13080 * this.
13081 */
b70709a6 13082 if (state->visible &&
32b7eeec 13083 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
e35fef21 13084 dev_priv->fbc.crtc == intel_crtc &&
8e7d688b 13085 state->base.rotation != BIT(DRM_ROTATE_0)) {
32b7eeec
MR		 13086 intel_crtc->atomic.disable_fbc = true;
13087 }
13088
b70709a6 13089 if (state->visible && !old_state->visible) {
32b7eeec
MR		 13090 /*
13091 * BDW signals flip done immediately if the plane
13092 * is disabled, even if the plane enable is already
13093 * armed to occur at the next vblank :(
13094 */
b70709a6 13095 if (IS_BROADWELL(dev))
32b7eeec
MR		 13096 intel_crtc->atomic.wait_vblank = true;
13097 }
13098
13099 intel_crtc->atomic.fb_bits |=
13100 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
13101
13102 intel_crtc->atomic.update_fbc = true;
0fda6568 13103
1fc0a8f7 13104 if (intel_wm_need_update(plane, &state->base))
0fda6568 13105 intel_crtc->atomic.update_wm = true;
ccc759dc
GP		 13106 }
13107
6156a456
CK		 13108 if (INTEL_INFO(dev)->gen >= 9) {
13109 ret = skl_update_scaler_users(intel_crtc, crtc_state,
13110 to_intel_plane(plane), state, 0);
13111 if (ret)
13112 return ret;
13113 }
13114
14af293f
GP		 13115 return 0;
13116}
13117
13118static void
13119intel_commit_primary_plane(struct drm_plane *plane,
13120 struct intel_plane_state *state)
13121{
2b875c22
MR		 13122 struct drm_crtc *crtc = state->base.crtc;
13123 struct drm_framebuffer *fb = state->base.fb;
13124 struct drm_device *dev = plane->dev;
14af293f 13125 struct drm_i915_private *dev_priv = dev->dev_private;
ea2c67bb 13126 struct intel_crtc *intel_crtc;
14af293f
GP		 13127 struct drm_rect *src = &state->src;
13128
ea2c67bb
MR		 13129 crtc = crtc ? crtc : plane->crtc;
13130 intel_crtc = to_intel_crtc(crtc);
cf4c7c12
MR		 13131
13132 plane->fb = fb;
9dc806fc
MR		 13133 crtc->x = src->x1 >> 16;
13134 crtc->y = src->y1 >> 16;
ccc759dc 13135
ccc759dc 13136 if (intel_crtc->active) {
27321ae8 13137 if (state->visible)
ccc759dc
GP		 13138 /* FIXME: kill this fastboot hack */
13139 intel_update_pipe_size(intel_crtc);
465c120c 13140
27321ae8
ML		 13141 dev_priv->display.update_primary_plane(crtc, plane->fb,
13142 crtc->x, crtc->y);
ccc759dc 13143 }
465c120c
MR		 13144}
13145
a8ad0d8e
ML		 13146static void
13147intel_disable_primary_plane(struct drm_plane *plane,
13148 struct drm_crtc *crtc,
13149 bool force)
13150{
13151 struct drm_device *dev = plane->dev;
13152 struct drm_i915_private *dev_priv = dev->dev_private;
13153
a8ad0d8e
ML		 13154 dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
13155}
13156
32b7eeec 13157static void intel_begin_crtc_commit(struct drm_crtc *crtc)
3c692a41 13158{
32b7eeec 13159 struct drm_device *dev = crtc->dev;
140fd38d 13160 struct drm_i915_private *dev_priv = dev->dev_private;
3c692a41 13161 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ea2c67bb
MR		 13162 struct intel_plane *intel_plane;
13163 struct drm_plane *p;
13164 unsigned fb_bits = 0;
13165
13166 /* Track fb's for any planes being disabled */
13167 list_for_each_entry(p, &dev->mode_config.plane_list, head) {
13168 intel_plane = to_intel_plane(p);
13169
13170 if (intel_crtc->atomic.disabled_planes &
13171 (1 << drm_plane_index(p))) {
13172 switch (p->type) {
13173 case DRM_PLANE_TYPE_PRIMARY:
13174 fb_bits = INTEL_FRONTBUFFER_PRIMARY(intel_plane->pipe);
13175 break;
13176 case DRM_PLANE_TYPE_CURSOR:
13177 fb_bits = INTEL_FRONTBUFFER_CURSOR(intel_plane->pipe);
13178 break;
13179 case DRM_PLANE_TYPE_OVERLAY:
13180 fb_bits = INTEL_FRONTBUFFER_SPRITE(intel_plane->pipe);
13181 break;
13182 }
3c692a41 13183
ea2c67bb
MR		 13184 mutex_lock(&dev->struct_mutex);
13185 i915_gem_track_fb(intel_fb_obj(p->fb), NULL, fb_bits);
13186 mutex_unlock(&dev->struct_mutex);
13187 }
13188 }
3c692a41 13189
32b7eeec
MR		 13190 if (intel_crtc->atomic.wait_for_flips)
13191 intel_crtc_wait_for_pending_flips(crtc);
3c692a41 13192
32b7eeec
MR		 13193 if (intel_crtc->atomic.disable_fbc)
13194 intel_fbc_disable(dev);
3c692a41 13195
32b7eeec
MR		 13196 if (intel_crtc->atomic.pre_disable_primary)
13197 intel_pre_disable_primary(crtc);
3c692a41 13198
32b7eeec
MR		 13199 if (intel_crtc->atomic.update_wm)
13200 intel_update_watermarks(crtc);
3c692a41 13201
32b7eeec 13202 intel_runtime_pm_get(dev_priv);
3c692a41 13203
c34c9ee4
MR		 13204 /* Perform vblank evasion around commit operation */
13205 if (intel_crtc->active)
13206 intel_crtc->atomic.evade =
13207 intel_pipe_update_start(intel_crtc,
13208 &intel_crtc->atomic.start_vbl_count);
32b7eeec
MR		 13209}
13210
13211static void intel_finish_crtc_commit(struct drm_crtc *crtc)
13212{
13213 struct drm_device *dev = crtc->dev;
13214 struct drm_i915_private *dev_priv = dev->dev_private;
13215 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13216 struct drm_plane *p;
13217
c34c9ee4
MR		 13218 if (intel_crtc->atomic.evade)
13219 intel_pipe_update_end(intel_crtc,
13220 intel_crtc->atomic.start_vbl_count);
3c692a41 13221
140fd38d 13222 intel_runtime_pm_put(dev_priv);
3c692a41 13223
32b7eeec
MR		 13224 if (intel_crtc->atomic.wait_vblank)
13225 intel_wait_for_vblank(dev, intel_crtc->pipe);
13226
13227 intel_frontbuffer_flip(dev, intel_crtc->atomic.fb_bits);
13228
13229 if (intel_crtc->atomic.update_fbc) {
ccc759dc 13230 mutex_lock(&dev->struct_mutex);
7ff0ebcc 13231 intel_fbc_update(dev);
ccc759dc 13232 mutex_unlock(&dev->struct_mutex);
38f3ce3a 13233 }
3c692a41 13234
32b7eeec
MR		 13235 if (intel_crtc->atomic.post_enable_primary)
13236 intel_post_enable_primary(crtc);
3c692a41 13237
32b7eeec
MR		 13238 drm_for_each_legacy_plane(p, &dev->mode_config.plane_list)
13239 if (intel_crtc->atomic.update_sprite_watermarks & drm_plane_index(p))
13240 intel_update_sprite_watermarks(p, crtc, 0, 0, 0,
13241 false, false);
13242
13243 memset(&intel_crtc->atomic, 0, sizeof(intel_crtc->atomic));
3c692a41
GP		 13244}
13245
cf4c7c12 13246/**
4a3b8769
MR		 13247 * intel_plane_destroy - destroy a plane
13248 * @plane: plane to destroy
cf4c7c12 13249 *
4a3b8769
MR		 13250 * Common destruction function for all types of planes (primary, cursor,
13251 * sprite).
cf4c7c12 13252 */
4a3b8769 13253void intel_plane_destroy(struct drm_plane *plane)
465c120c
MR		 13254{
13255 struct intel_plane *intel_plane = to_intel_plane(plane);
13256 drm_plane_cleanup(plane);
13257 kfree(intel_plane);
13258}
13259
65a3fea0 13260const struct drm_plane_funcs intel_plane_funcs = {
70a101f8
MR		 13261 .update_plane = drm_atomic_helper_update_plane,
13262 .disable_plane = drm_atomic_helper_disable_plane,
3d7d6510 13263 .destroy = intel_plane_destroy,
c196e1d6 13264 .set_property = drm_atomic_helper_plane_set_property,
a98b3431
MR		 13265 .atomic_get_property = intel_plane_atomic_get_property,
13266 .atomic_set_property = intel_plane_atomic_set_property,
ea2c67bb
MR		 13267 .atomic_duplicate_state = intel_plane_duplicate_state,
13268 .atomic_destroy_state = intel_plane_destroy_state,
13269
465c120c
MR		 13270};
13271
13272static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13273 int pipe)
13274{
13275 struct intel_plane *primary;
8e7d688b 13276 struct intel_plane_state *state;
465c120c
MR		 13277 const uint32_t *intel_primary_formats;
13278 int num_formats;
13279
13280 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13281 if (primary == NULL)
13282 return NULL;
13283
8e7d688b
MR		 13284 state = intel_create_plane_state(&primary->base);
13285 if (!state) {
ea2c67bb
MR		 13286 kfree(primary);
13287 return NULL;
13288 }
8e7d688b 13289 primary->base.state = &state->base;
ea2c67bb 13290
465c120c
MR		 13291 primary->can_scale = false;
13292 primary->max_downscale = 1;
6156a456
CK		 13293 if (INTEL_INFO(dev)->gen >= 9) {
13294 primary->can_scale = true;
af99ceda 13295 state->scaler_id = -1;
6156a456 13296 }
465c120c
MR		 13297 primary->pipe = pipe;
13298 primary->plane = pipe;
c59cb179
MR		 13299 primary->check_plane = intel_check_primary_plane;
13300 primary->commit_plane = intel_commit_primary_plane;
a8ad0d8e 13301 primary->disable_plane = intel_disable_primary_plane;
08e221fb 13302 primary->ckey.flags = I915_SET_COLORKEY_NONE;
465c120c
MR		 13303 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13304 primary->plane = !pipe;
13305
13306 if (INTEL_INFO(dev)->gen <= 3) {
568db4f2
DL		 13307 intel_primary_formats = i8xx_primary_formats;
13308 num_formats = ARRAY_SIZE(i8xx_primary_formats);
465c120c 13309 } else {
568db4f2
DL		 13310 intel_primary_formats = i965_primary_formats;
13311 num_formats = ARRAY_SIZE(i965_primary_formats);
465c120c
MR		 13312 }
13313
13314 drm_universal_plane_init(dev, &primary->base, 0,
65a3fea0 13315 &intel_plane_funcs,
465c120c
MR		 13316 intel_primary_formats, num_formats,
13317 DRM_PLANE_TYPE_PRIMARY);
48404c1e 13318
3b7a5119
SJ		 13319 if (INTEL_INFO(dev)->gen >= 4)
13320 intel_create_rotation_property(dev, primary);
48404c1e 13321
ea2c67bb
MR		 13322 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13323
465c120c
MR		 13324 return &primary->base;
13325}
13326
3b7a5119
SJ		 13327void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13328{
13329 if (!dev->mode_config.rotation_property) {
13330 unsigned long flags = BIT(DRM_ROTATE_0) |
13331 BIT(DRM_ROTATE_180);
13332
13333 if (INTEL_INFO(dev)->gen >= 9)
13334 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13335
13336 dev->mode_config.rotation_property =
13337 drm_mode_create_rotation_property(dev, flags);
13338 }
13339 if (dev->mode_config.rotation_property)
13340 drm_object_attach_property(&plane->base.base,
13341 dev->mode_config.rotation_property,
13342 plane->base.state->rotation);
13343}
13344
3d7d6510 13345static int
852e787c
GP		 13346intel_check_cursor_plane(struct drm_plane *plane,
13347 struct intel_plane_state *state)
3d7d6510 13348{
2b875c22 13349 struct drm_crtc *crtc = state->base.crtc;
ea2c67bb 13350 struct drm_device *dev = plane->dev;
2b875c22 13351 struct drm_framebuffer *fb = state->base.fb;
852e787c
GP		 13352 struct drm_rect *dest = &state->dst;
13353 struct drm_rect *src = &state->src;
13354 const struct drm_rect *clip = &state->clip;
757f9a3e 13355 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
ea2c67bb 13356 struct intel_crtc *intel_crtc;
757f9a3e
GP		 13357 unsigned stride;
13358 int ret;
3d7d6510 13359
ea2c67bb
MR		 13360 crtc = crtc ? crtc : plane->crtc;
13361 intel_crtc = to_intel_crtc(crtc);
13362
757f9a3e 13363 ret = drm_plane_helper_check_update(plane, crtc, fb,
852e787c 13364 src, dest, clip,
3d7d6510
MR		 13365 DRM_PLANE_HELPER_NO_SCALING,
13366 DRM_PLANE_HELPER_NO_SCALING,
852e787c 13367 true, true, &state->visible);
757f9a3e
GP		 13368 if (ret)
13369 return ret;
13370
13371
13372 /* if we want to turn off the cursor ignore width and height */
13373 if (!obj)
32b7eeec 13374 goto finish;
757f9a3e 13375
757f9a3e 13376 /* Check for which cursor types we support */
ea2c67bb
MR		 13377 if (!cursor_size_ok(dev, state->base.crtc_w, state->base.crtc_h)) {
13378 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13379 state->base.crtc_w, state->base.crtc_h);
757f9a3e
GP		 13380 return -EINVAL;
13381 }
13382
ea2c67bb
MR		 13383 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13384 if (obj->base.size < stride * state->base.crtc_h) {
757f9a3e
GP		 13385 DRM_DEBUG_KMS("buffer is too small\n");
13386 return -ENOMEM;
13387 }
13388
3a656b54 13389 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
757f9a3e
GP		 13390 DRM_DEBUG_KMS("cursor cannot be tiled\n");
13391 ret = -EINVAL;
13392 }
757f9a3e 13393
32b7eeec
MR		 13394finish:
13395 if (intel_crtc->active) {
3749f463 13396 if (plane->state->crtc_w != state->base.crtc_w)
32b7eeec
MR		 13397 intel_crtc->atomic.update_wm = true;
13398
13399 intel_crtc->atomic.fb_bits |=
13400 INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe);
13401 }
13402
757f9a3e 13403 return ret;
852e787c 13404}
3d7d6510 13405
a8ad0d8e
ML		 13406static void
13407intel_disable_cursor_plane(struct drm_plane *plane,
13408 struct drm_crtc *crtc,
13409 bool force)
13410{
13411 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13412
13413 if (!force) {
13414 plane->fb = NULL;
13415 intel_crtc->cursor_bo = NULL;
13416 intel_crtc->cursor_addr = 0;
13417 }
13418
13419 intel_crtc_update_cursor(crtc, false);
13420}
13421
f4a2cf29 13422static void
852e787c
GP		 13423intel_commit_cursor_plane(struct drm_plane *plane,
13424 struct intel_plane_state *state)
13425{
2b875c22 13426 struct drm_crtc *crtc = state->base.crtc;
ea2c67bb
MR		 13427 struct drm_device *dev = plane->dev;
13428 struct intel_crtc *intel_crtc;
2b875c22 13429 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
a912f12f 13430 uint32_t addr;
852e787c 13431
ea2c67bb
MR		 13432 crtc = crtc ? crtc : plane->crtc;
13433 intel_crtc = to_intel_crtc(crtc);
13434
2b875c22 13435 plane->fb = state->base.fb;
ea2c67bb
MR		 13436 crtc->cursor_x = state->base.crtc_x;
13437 crtc->cursor_y = state->base.crtc_y;
13438
a912f12f
GP		 13439 if (intel_crtc->cursor_bo == obj)
13440 goto update;
4ed91096 13441
f4a2cf29 13442 if (!obj)
a912f12f 13443 addr = 0;
f4a2cf29 13444 else if (!INTEL_INFO(dev)->cursor_needs_physical)
a912f12f 13445 addr = i915_gem_obj_ggtt_offset(obj);
f4a2cf29 13446 else
a912f12f 13447 addr = obj->phys_handle->busaddr;
852e787c 13448
a912f12f
GP		 13449 intel_crtc->cursor_addr = addr;
13450 intel_crtc->cursor_bo = obj;
13451update:
852e787c 13452
32b7eeec 13453 if (intel_crtc->active)
a912f12f 13454 intel_crtc_update_cursor(crtc, state->visible);
852e787c
GP		 13455}
13456
3d7d6510
MR		 13457static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
13458 int pipe)
13459{
13460 struct intel_plane *cursor;
8e7d688b 13461 struct intel_plane_state *state;
3d7d6510
MR		 13462
13463 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13464 if (cursor == NULL)
13465 return NULL;
13466
8e7d688b
MR		 13467 state = intel_create_plane_state(&cursor->base);
13468 if (!state) {
ea2c67bb
MR		 13469 kfree(cursor);
13470 return NULL;
13471 }
8e7d688b 13472 cursor->base.state = &state->base;
ea2c67bb 13473
3d7d6510
MR		 13474 cursor->can_scale = false;
13475 cursor->max_downscale = 1;
13476 cursor->pipe = pipe;
13477 cursor->plane = pipe;
c59cb179
MR		 13478 cursor->check_plane = intel_check_cursor_plane;
13479 cursor->commit_plane = intel_commit_cursor_plane;
a8ad0d8e 13480 cursor->disable_plane = intel_disable_cursor_plane;
3d7d6510
MR		 13481
13482 drm_universal_plane_init(dev, &cursor->base, 0,
65a3fea0 13483 &intel_plane_funcs,
3d7d6510
MR		 13484 intel_cursor_formats,
13485 ARRAY_SIZE(intel_cursor_formats),
13486 DRM_PLANE_TYPE_CURSOR);
4398ad45
VS		 13487
13488 if (INTEL_INFO(dev)->gen >= 4) {
13489 if (!dev->mode_config.rotation_property)
13490 dev->mode_config.rotation_property =
13491 drm_mode_create_rotation_property(dev,
13492 BIT(DRM_ROTATE_0) |
13493 BIT(DRM_ROTATE_180));
13494 if (dev->mode_config.rotation_property)
13495 drm_object_attach_property(&cursor->base.base,
13496 dev->mode_config.rotation_property,
8e7d688b 13497 state->base.rotation);
4398ad45
VS		 13498 }
13499
af99ceda
CK		 13500 if (INTEL_INFO(dev)->gen >=9)
13501 state->scaler_id = -1;
13502
ea2c67bb
MR		 13503 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13504
3d7d6510
MR		 13505 return &cursor->base;
13506}
13507
549e2bfb
CK		 13508static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
13509 struct intel_crtc_state *crtc_state)
13510{
13511 int i;
13512 struct intel_scaler *intel_scaler;
13513 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
13514
13515 for (i = 0; i < intel_crtc->num_scalers; i++) {
13516 intel_scaler = &scaler_state->scalers[i];
13517 intel_scaler->in_use = 0;
13518 intel_scaler->id = i;
13519
13520 intel_scaler->mode = PS_SCALER_MODE_DYN;
13521 }
13522
13523 scaler_state->scaler_id = -1;
13524}
13525
b358d0a6 13526static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 13527{
fbee40df 13528 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 13529 struct intel_crtc *intel_crtc;
f5de6e07 13530 struct intel_crtc_state *crtc_state = NULL;
3d7d6510
MR		 13531 struct drm_plane *primary = NULL;
13532 struct drm_plane *cursor = NULL;
465c120c 13533 int i, ret;
79e53945 13534
955382f3 13535 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
79e53945
JB		 13536 if (intel_crtc == NULL)
13537 return;
13538
f5de6e07
ACO		 13539 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13540 if (!crtc_state)
13541 goto fail;
550acefd
ACO		 13542 intel_crtc->config = crtc_state;
13543 intel_crtc->base.state = &crtc_state->base;
07878248 13544 crtc_state->base.crtc = &intel_crtc->base;
f5de6e07 13545
549e2bfb
CK		 13546 /* initialize shared scalers */
13547 if (INTEL_INFO(dev)->gen >= 9) {
13548 if (pipe == PIPE_C)
13549 intel_crtc->num_scalers = 1;
13550 else
13551 intel_crtc->num_scalers = SKL_NUM_SCALERS;
13552
13553 skl_init_scalers(dev, intel_crtc, crtc_state);
13554 }
13555
465c120c 13556 primary = intel_primary_plane_create(dev, pipe);
3d7d6510
MR		 13557 if (!primary)
13558 goto fail;
13559
13560 cursor = intel_cursor_plane_create(dev, pipe);
13561 if (!cursor)
13562 goto fail;
13563
465c120c 13564 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
3d7d6510
MR		 13565 cursor, &intel_crtc_funcs);
13566 if (ret)
13567 goto fail;
79e53945
JB		 13568
13569 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 13570 for (i = 0; i < 256; i++) {
13571 intel_crtc->lut_r[i] = i;
13572 intel_crtc->lut_g[i] = i;
13573 intel_crtc->lut_b[i] = i;
13574 }
13575
1f1c2e24
VS		 13576 /*
13577 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
8c0f92e1 13578 * is hooked to pipe B. Hence we want plane A feeding pipe B.
1f1c2e24 13579 */
80824003
JB		 13580 intel_crtc->pipe = pipe;
13581 intel_crtc->plane = pipe;
3a77c4c4 13582 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
28c97730 13583 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 13584 intel_crtc->plane = !pipe;
80824003
JB		 13585 }
13586
4b0e333e
CW		 13587 intel_crtc->cursor_base = ~0;
13588 intel_crtc->cursor_cntl = ~0;
dc41c154 13589 intel_crtc->cursor_size = ~0;
8d7849db 13590
22fd0fab
JB		 13591 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
13592 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
13593 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
13594 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
13595
79e53945 13596 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
87b6b101
DV		 13597
13598 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
3d7d6510
MR		 13599 return;
13600
13601fail:
13602 if (primary)
13603 drm_plane_cleanup(primary);
13604 if (cursor)
13605 drm_plane_cleanup(cursor);
f5de6e07 13606 kfree(crtc_state);
3d7d6510 13607 kfree(intel_crtc);
79e53945
JB		 13608}
13609
752aa88a
JB		 13610enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
13611{
13612 struct drm_encoder *encoder = connector->base.encoder;
6e9f798d 13613 struct drm_device *dev = connector->base.dev;
752aa88a 13614
51fd371b 13615 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
752aa88a 13616
d3babd3f 13617 if (!encoder || WARN_ON(!encoder->crtc))
752aa88a
JB		 13618 return INVALID_PIPE;
13619
13620 return to_intel_crtc(encoder->crtc)->pipe;
13621}
13622
08d7b3d1 13623int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 13624 struct drm_file *file)
08d7b3d1 13625{
08d7b3d1 13626 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7707e653 13627 struct drm_crtc *drmmode_crtc;
c05422d5 13628 struct intel_crtc *crtc;
08d7b3d1 13629
7707e653 13630 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
08d7b3d1 13631
7707e653 13632 if (!drmmode_crtc) {
08d7b3d1 13633 DRM_ERROR("no such CRTC id\n");
3f2c2057 13634 return -ENOENT;
08d7b3d1
CW		 13635 }
13636
7707e653 13637 crtc = to_intel_crtc(drmmode_crtc);
c05422d5 13638 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 13639
c05422d5 13640 return 0;
08d7b3d1
CW		 13641}
13642
66a9278e 13643static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 13644{
66a9278e
DV		 13645 struct drm_device *dev = encoder->base.dev;
13646 struct intel_encoder *source_encoder;
79e53945 13647 int index_mask = 0;
79e53945
JB		 13648 int entry = 0;
13649
b2784e15 13650 for_each_intel_encoder(dev, source_encoder) {
bc079e8b 13651 if (encoders_cloneable(encoder, source_encoder))
66a9278e
DV		 13652 index_mask |= (1 << entry);
13653
79e53945
JB		 13654 entry++;
13655 }
4ef69c7a 13656
79e53945
JB		 13657 return index_mask;
13658}
13659
4d302442
CW		 13660static bool has_edp_a(struct drm_device *dev)
13661{
13662 struct drm_i915_private *dev_priv = dev->dev_private;
13663
13664 if (!IS_MOBILE(dev))
13665 return false;
13666
13667 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
13668 return false;
13669
e3589908 13670 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
4d302442
CW		 13671 return false;
13672
13673 return true;
13674}
13675
84b4e042
JB		 13676static bool intel_crt_present(struct drm_device *dev)
13677{
13678 struct drm_i915_private *dev_priv = dev->dev_private;
13679
884497ed
DL		 13680 if (INTEL_INFO(dev)->gen >= 9)
13681 return false;
13682
cf404ce4 13683 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
84b4e042
JB		 13684 return false;
13685
13686 if (IS_CHERRYVIEW(dev))
13687 return false;
13688
13689 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
13690 return false;
13691
13692 return true;
13693}
13694
79e53945
JB		 13695static void intel_setup_outputs(struct drm_device *dev)
13696{
725e30ad 13697 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 13698 struct intel_encoder *encoder;
cb0953d7 13699 bool dpd_is_edp = false;
79e53945 13700
c9093354 13701 intel_lvds_init(dev);
79e53945 13702
84b4e042 13703 if (intel_crt_present(dev))
79935fca 13704 intel_crt_init(dev);
cb0953d7 13705
c776eb2e
VK		 13706 if (IS_BROXTON(dev)) {
13707 /*
13708 * FIXME: Broxton doesn't support port detection via the
13709 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
13710 * detect the ports.
13711 */
13712 intel_ddi_init(dev, PORT_A);
13713 intel_ddi_init(dev, PORT_B);
13714 intel_ddi_init(dev, PORT_C);
13715 } else if (HAS_DDI(dev)) {
0e72a5b5
ED		 13716 int found;
13717
de31facd
JB		 13718 /*
13719 * Haswell uses DDI functions to detect digital outputs.
13720 * On SKL pre-D0 the strap isn't connected, so we assume
13721 * it's there.
13722 */
0e72a5b5 13723 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
de31facd
JB		 13724 /* WaIgnoreDDIAStrap: skl */
13725 if (found ||
13726 (IS_SKYLAKE(dev) && INTEL_REVID(dev) < SKL_REVID_D0))
0e72a5b5
ED		 13727 intel_ddi_init(dev, PORT_A);
13728
13729 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
13730 * register */
13731 found = I915_READ(SFUSE_STRAP);
13732
13733 if (found & SFUSE_STRAP_DDIB_DETECTED)
13734 intel_ddi_init(dev, PORT_B);
13735 if (found & SFUSE_STRAP_DDIC_DETECTED)
13736 intel_ddi_init(dev, PORT_C);
13737 if (found & SFUSE_STRAP_DDID_DETECTED)
13738 intel_ddi_init(dev, PORT_D);
13739 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 13740 int found;
5d8a7752 13741 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
270b3042
DV		 13742
13743 if (has_edp_a(dev))
13744 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 13745
dc0fa718 13746 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 13747 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 13748 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 13749 if (!found)
e2debe91 13750 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 13751 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 13752 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 13753 }
13754
dc0fa718 13755 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 13756 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 13757
dc0fa718 13758 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 13759 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 13760
5eb08b69 13761 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 13762 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 13763
270b3042 13764 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 13765 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 13766 } else if (IS_VALLEYVIEW(dev)) {
e17ac6db
VS		 13767 /*
13768 * The DP_DETECTED bit is the latched state of the DDC
13769 * SDA pin at boot. However since eDP doesn't require DDC
13770 * (no way to plug in a DP->HDMI dongle) the DDC pins for
13771 * eDP ports may have been muxed to an alternate function.
13772 * Thus we can't rely on the DP_DETECTED bit alone to detect
13773 * eDP ports. Consult the VBT as well as DP_DETECTED to
13774 * detect eDP ports.
13775 */
d2182a66
VS		 13776 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
13777 !intel_dp_is_edp(dev, PORT_B))
585a94b8
AB		 13778 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
13779 PORT_B);
e17ac6db
VS		 13780 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
13781 intel_dp_is_edp(dev, PORT_B))
13782 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
585a94b8 13783
d2182a66
VS		 13784 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
13785 !intel_dp_is_edp(dev, PORT_C))
6f6005a5
JB		 13786 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
13787 PORT_C);
e17ac6db
VS		 13788 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
13789 intel_dp_is_edp(dev, PORT_C))
13790 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
19c03924 13791
9418c1f1 13792 if (IS_CHERRYVIEW(dev)) {
e17ac6db 13793 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
9418c1f1
VS		 13794 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
13795 PORT_D);
e17ac6db
VS		 13796 /* eDP not supported on port D, so don't check VBT */
13797 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
13798 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
9418c1f1
VS		 13799 }
13800
3cfca973 13801 intel_dsi_init(dev);
103a196f 13802 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 13803 bool found = false;
7d57382e 13804
e2debe91 13805 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 13806 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 13807 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
b01f2c3a
JB		 13808 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
13809 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 13810 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 13811 }
27185ae1 13812
e7281eab 13813 if (!found && SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 13814 intel_dp_init(dev, DP_B, PORT_B);
725e30ad 13815 }
13520b05
KH		 13816
13817 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 13818
e2debe91 13819 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 13820 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 13821 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 13822 }
27185ae1 13823
e2debe91 13824 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 13825
b01f2c3a
JB		 13826 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
13827 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 13828 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a 13829 }
e7281eab 13830 if (SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 13831 intel_dp_init(dev, DP_C, PORT_C);
725e30ad 13832 }
27185ae1 13833
b01f2c3a 13834 if (SUPPORTS_INTEGRATED_DP(dev) &&
e7281eab 13835 (I915_READ(DP_D) & DP_DETECTED))
ab9d7c30 13836 intel_dp_init(dev, DP_D, PORT_D);
bad720ff 13837 } else if (IS_GEN2(dev))
79e53945
JB		 13838 intel_dvo_init(dev);
13839
103a196f 13840 if (SUPPORTS_TV(dev))
79e53945
JB		 13841 intel_tv_init(dev);
13842
0bc12bcb 13843 intel_psr_init(dev);
7c8f8a70 13844
b2784e15 13845 for_each_intel_encoder(dev, encoder) {
4ef69c7a
CW		 13846 encoder->base.possible_crtcs = encoder->crtc_mask;
13847 encoder->base.possible_clones =
66a9278e 13848 intel_encoder_clones(encoder);
79e53945 13849 }
47356eb6 13850
dde86e2d 13851 intel_init_pch_refclk(dev);
270b3042
DV		 13852
13853 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 13854}
13855
13856static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
13857{
60a5ca01 13858 struct drm_device *dev = fb->dev;
79e53945 13859 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945 13860
ef2d633e 13861 drm_framebuffer_cleanup(fb);
60a5ca01 13862 mutex_lock(&dev->struct_mutex);
ef2d633e 13863 WARN_ON(!intel_fb->obj->framebuffer_references--);
60a5ca01
VS		 13864 drm_gem_object_unreference(&intel_fb->obj->base);
13865 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 13866 kfree(intel_fb);
13867}
13868
13869static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 13870 struct drm_file *file,
79e53945
JB		 13871 unsigned int *handle)
13872{
13873 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 13874 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 13875
05394f39 13876 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 13877}
13878
13879static const struct drm_framebuffer_funcs intel_fb_funcs = {
13880 .destroy = intel_user_framebuffer_destroy,
13881 .create_handle = intel_user_framebuffer_create_handle,
13882};
13883
b321803d
DL		 13884static
13885u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
13886 uint32_t pixel_format)
13887{
13888 u32 gen = INTEL_INFO(dev)->gen;
13889
13890 if (gen >= 9) {
13891 /* "The stride in bytes must not exceed the of the size of 8K
13892 * pixels and 32K bytes."
13893 */
13894 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
13895 } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
13896 return 32*1024;
13897 } else if (gen >= 4) {
13898 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
13899 return 16*1024;
13900 else
13901 return 32*1024;
13902 } else if (gen >= 3) {
13903 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
13904 return 8*1024;
13905 else
13906 return 16*1024;
13907 } else {
13908 /* XXX DSPC is limited to 4k tiled */
13909 return 8*1024;
13910 }
13911}
13912
b5ea642a
DV		 13913static int intel_framebuffer_init(struct drm_device *dev,
13914 struct intel_framebuffer *intel_fb,
13915 struct drm_mode_fb_cmd2 *mode_cmd,
13916 struct drm_i915_gem_object *obj)
79e53945 13917{
6761dd31 13918 unsigned int aligned_height;
79e53945 13919 int ret;
b321803d 13920 u32 pitch_limit, stride_alignment;
79e53945 13921
dd4916c5
DV		 13922 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
13923
2a80eada
DV		 13924 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
13925 /* Enforce that fb modifier and tiling mode match, but only for
13926 * X-tiled. This is needed for FBC. */
13927 if (!!(obj->tiling_mode == I915_TILING_X) !=
13928 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
13929 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
13930 return -EINVAL;
13931 }
13932 } else {
13933 if (obj->tiling_mode == I915_TILING_X)
13934 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
13935 else if (obj->tiling_mode == I915_TILING_Y) {
13936 DRM_DEBUG("No Y tiling for legacy addfb\n");
13937 return -EINVAL;
13938 }
13939 }
13940
9a8f0a12
TU		 13941 /* Passed in modifier sanity checking. */
13942 switch (mode_cmd->modifier[0]) {
13943 case I915_FORMAT_MOD_Y_TILED:
13944 case I915_FORMAT_MOD_Yf_TILED:
13945 if (INTEL_INFO(dev)->gen < 9) {
13946 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
13947 mode_cmd->modifier[0]);
13948 return -EINVAL;
13949 }
13950 case DRM_FORMAT_MOD_NONE:
13951 case I915_FORMAT_MOD_X_TILED:
13952 break;
13953 default:
c0f40428
JB		 13954 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
13955 mode_cmd->modifier[0]);
57cd6508 13956 return -EINVAL;
c16ed4be 13957 }
57cd6508 13958
b321803d
DL		 13959 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
13960 mode_cmd->pixel_format);
13961 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
13962 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
13963 mode_cmd->pitches[0], stride_alignment);
57cd6508 13964 return -EINVAL;
c16ed4be 13965 }
57cd6508 13966
b321803d
DL		 13967 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
13968 mode_cmd->pixel_format);
a35cdaa0 13969 if (mode_cmd->pitches[0] > pitch_limit) {
b321803d
DL		 13970 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
13971 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
2a80eada 13972 "tiled" : "linear",
a35cdaa0 13973 mode_cmd->pitches[0], pitch_limit);
5d7bd705 13974 return -EINVAL;
c16ed4be 13975 }
5d7bd705 13976
2a80eada 13977 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
c16ed4be
CW		 13978 mode_cmd->pitches[0] != obj->stride) {
13979 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
13980 mode_cmd->pitches[0], obj->stride);
5d7bd705 13981 return -EINVAL;
c16ed4be 13982 }
5d7bd705 13983
57779d06 13984 /* Reject formats not supported by any plane early. */
308e5bcb 13985 switch (mode_cmd->pixel_format) {
57779d06 13986 case DRM_FORMAT_C8:
04b3924d
VS		 13987 case DRM_FORMAT_RGB565:
13988 case DRM_FORMAT_XRGB8888:
13989 case DRM_FORMAT_ARGB8888:
57779d06
VS		 13990 break;
13991 case DRM_FORMAT_XRGB1555:
13992 case DRM_FORMAT_ARGB1555:
c16ed4be 13993 if (INTEL_INFO(dev)->gen > 3) {
4ee62c76
VS		 13994 DRM_DEBUG("unsupported pixel format: %s\n",
13995 drm_get_format_name(mode_cmd->pixel_format));
57779d06 13996 return -EINVAL;
c16ed4be 13997 }
57779d06
VS		 13998 break;
13999 case DRM_FORMAT_XBGR8888:
14000 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 14001 case DRM_FORMAT_XRGB2101010:
14002 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 14003 case DRM_FORMAT_XBGR2101010:
14004 case DRM_FORMAT_ABGR2101010:
c16ed4be 14005 if (INTEL_INFO(dev)->gen < 4) {
4ee62c76
VS		 14006 DRM_DEBUG("unsupported pixel format: %s\n",
14007 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14008 return -EINVAL;
c16ed4be 14009 }
b5626747 14010 break;
04b3924d
VS		 14011 case DRM_FORMAT_YUYV:
14012 case DRM_FORMAT_UYVY:
14013 case DRM_FORMAT_YVYU:
14014 case DRM_FORMAT_VYUY:
c16ed4be 14015 if (INTEL_INFO(dev)->gen < 5) {
4ee62c76
VS		 14016 DRM_DEBUG("unsupported pixel format: %s\n",
14017 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14018 return -EINVAL;
c16ed4be 14019 }
57cd6508
CW		 14020 break;
14021 default:
4ee62c76
VS		 14022 DRM_DEBUG("unsupported pixel format: %s\n",
14023 drm_get_format_name(mode_cmd->pixel_format));
57cd6508
CW		 14024 return -EINVAL;
14025 }
14026
90f9a336
VS		 14027 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14028 if (mode_cmd->offsets[0] != 0)
14029 return -EINVAL;
14030
ec2c981e 14031 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
091df6cb
DV		 14032 mode_cmd->pixel_format,
14033 mode_cmd->modifier[0]);
53155c0a
DV		 14034 /* FIXME drm helper for size checks (especially planar formats)? */
14035 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14036 return -EINVAL;
14037
c7d73f6a
DV		 14038 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14039 intel_fb->obj = obj;
80075d49 14040 intel_fb->obj->framebuffer_references++;
c7d73f6a 14041
79e53945
JB		 14042 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14043 if (ret) {
14044 DRM_ERROR("framebuffer init failed %d\n", ret);
14045 return ret;
14046 }
14047
79e53945
JB		 14048 return 0;
14049}
14050
79e53945
JB		 14051static struct drm_framebuffer *
14052intel_user_framebuffer_create(struct drm_device *dev,
14053 struct drm_file *filp,
308e5bcb 14054 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 14055{
05394f39 14056 struct drm_i915_gem_object *obj;
79e53945 14057
308e5bcb
JB		 14058 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14059 mode_cmd->handles[0]));
c8725226 14060 if (&obj->base == NULL)
cce13ff7 14061 return ERR_PTR(-ENOENT);
79e53945 14062
d2dff872 14063 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 14064}
14065
4520f53a 14066#ifndef CONFIG_DRM_I915_FBDEV
0632fef6 14067static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
4520f53a
DV		 14068{
14069}
14070#endif
14071
79e53945 14072static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 14073 .fb_create = intel_user_framebuffer_create,
0632fef6 14074 .output_poll_changed = intel_fbdev_output_poll_changed,
5ee67f1c
MR		 14075 .atomic_check = intel_atomic_check,
14076 .atomic_commit = intel_atomic_commit,
79e53945
JB		 14077};
14078
e70236a8
JB		 14079/* Set up chip specific display functions */
14080static void intel_init_display(struct drm_device *dev)
14081{
14082 struct drm_i915_private *dev_priv = dev->dev_private;
14083
ee9300bb
DV		 14084 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14085 dev_priv->display.find_dpll = g4x_find_best_dpll;
ef9348c8
CML		 14086 else if (IS_CHERRYVIEW(dev))
14087 dev_priv->display.find_dpll = chv_find_best_dpll;
ee9300bb
DV		 14088 else if (IS_VALLEYVIEW(dev))
14089 dev_priv->display.find_dpll = vlv_find_best_dpll;
14090 else if (IS_PINEVIEW(dev))
14091 dev_priv->display.find_dpll = pnv_find_best_dpll;
14092 else
14093 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14094
bc8d7dff
DL		 14095 if (INTEL_INFO(dev)->gen >= 9) {
14096 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
5724dbd1
DL		 14097 dev_priv->display.get_initial_plane_config =
14098 skylake_get_initial_plane_config;
bc8d7dff
DL		 14099 dev_priv->display.crtc_compute_clock =
14100 haswell_crtc_compute_clock;
14101 dev_priv->display.crtc_enable = haswell_crtc_enable;
14102 dev_priv->display.crtc_disable = haswell_crtc_disable;
14103 dev_priv->display.off = ironlake_crtc_off;
14104 dev_priv->display.update_primary_plane =
14105 skylake_update_primary_plane;
14106 } else if (HAS_DDI(dev)) {
0e8ffe1b 14107 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
5724dbd1
DL		 14108 dev_priv->display.get_initial_plane_config =
14109 ironlake_get_initial_plane_config;
797d0259
ACO		 14110 dev_priv->display.crtc_compute_clock =
14111 haswell_crtc_compute_clock;
4f771f10
PZ		 14112 dev_priv->display.crtc_enable = haswell_crtc_enable;
14113 dev_priv->display.crtc_disable = haswell_crtc_disable;
df8ad70c 14114 dev_priv->display.off = ironlake_crtc_off;
bc8d7dff
DL		 14115 dev_priv->display.update_primary_plane =
14116 ironlake_update_primary_plane;
09b4ddf9 14117 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 14118 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
5724dbd1
DL		 14119 dev_priv->display.get_initial_plane_config =
14120 ironlake_get_initial_plane_config;
3fb37703
ACO		 14121 dev_priv->display.crtc_compute_clock =
14122 ironlake_crtc_compute_clock;
76e5a89c
DV		 14123 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14124 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 14125 dev_priv->display.off = ironlake_crtc_off;
262ca2b0
MR		 14126 dev_priv->display.update_primary_plane =
14127 ironlake_update_primary_plane;
89b667f8
JB		 14128 } else if (IS_VALLEYVIEW(dev)) {
14129 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
5724dbd1
DL		 14130 dev_priv->display.get_initial_plane_config =
14131 i9xx_get_initial_plane_config;
d6dfee7a 14132 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
89b667f8
JB		 14133 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14134 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14135 dev_priv->display.off = i9xx_crtc_off;
262ca2b0
MR		 14136 dev_priv->display.update_primary_plane =
14137 i9xx_update_primary_plane;
f564048e 14138 } else {
0e8ffe1b 14139 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
5724dbd1
DL		 14140 dev_priv->display.get_initial_plane_config =
14141 i9xx_get_initial_plane_config;
d6dfee7a 14142 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
76e5a89c
DV		 14143 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14144 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 14145 dev_priv->display.off = i9xx_crtc_off;
262ca2b0
MR		 14146 dev_priv->display.update_primary_plane =
14147 i9xx_update_primary_plane;
f564048e 14148 }
e70236a8 14149
e70236a8 14150 /* Returns the core display clock speed */
1652d19e
VS		 14151 if (IS_SKYLAKE(dev))
14152 dev_priv->display.get_display_clock_speed =
14153 skylake_get_display_clock_speed;
14154 else if (IS_BROADWELL(dev))
14155 dev_priv->display.get_display_clock_speed =
14156 broadwell_get_display_clock_speed;
14157 else if (IS_HASWELL(dev))
14158 dev_priv->display.get_display_clock_speed =
14159 haswell_get_display_clock_speed;
14160 else if (IS_VALLEYVIEW(dev))
25eb05fc
JB		 14161 dev_priv->display.get_display_clock_speed =
14162 valleyview_get_display_clock_speed;
b37a6434
VS		 14163 else if (IS_GEN5(dev))
14164 dev_priv->display.get_display_clock_speed =
14165 ilk_get_display_clock_speed;
a7c66cd8
VS		 14166 else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
14167 IS_GEN6(dev) || IS_IVYBRIDGE(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 14168 dev_priv->display.get_display_clock_speed =
14169 i945_get_display_clock_speed;
14170 else if (IS_I915G(dev))
14171 dev_priv->display.get_display_clock_speed =
14172 i915_get_display_clock_speed;
257a7ffc 14173 else if (IS_I945GM(dev) || IS_845G(dev))
e70236a8
JB		 14174 dev_priv->display.get_display_clock_speed =
14175 i9xx_misc_get_display_clock_speed;
257a7ffc
DV		 14176 else if (IS_PINEVIEW(dev))
14177 dev_priv->display.get_display_clock_speed =
14178 pnv_get_display_clock_speed;
e70236a8
JB		 14179 else if (IS_I915GM(dev))
14180 dev_priv->display.get_display_clock_speed =
14181 i915gm_get_display_clock_speed;
14182 else if (IS_I865G(dev))
14183 dev_priv->display.get_display_clock_speed =
14184 i865_get_display_clock_speed;
f0f8a9ce 14185 else if (IS_I85X(dev))
e70236a8
JB		 14186 dev_priv->display.get_display_clock_speed =
14187 i855_get_display_clock_speed;
14188 else /* 852, 830 */
14189 dev_priv->display.get_display_clock_speed =
14190 i830_get_display_clock_speed;
14191
7c10a2b5 14192 if (IS_GEN5(dev)) {
3bb11b53 14193 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
3bb11b53
SJ		 14194 } else if (IS_GEN6(dev)) {
14195 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
3bb11b53
SJ		 14196 } else if (IS_IVYBRIDGE(dev)) {
14197 /* FIXME: detect B0+ stepping and use auto training */
14198 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
059b2fe9 14199 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
3bb11b53 14200 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
30a970c6
JB		 14201 } else if (IS_VALLEYVIEW(dev)) {
14202 dev_priv->display.modeset_global_resources =
14203 valleyview_modeset_global_resources;
f8437dd1
VK		 14204 } else if (IS_BROXTON(dev)) {
14205 dev_priv->display.modeset_global_resources =
14206 broxton_modeset_global_resources;
e70236a8 14207 }
8c9f3aaf 14208
8c9f3aaf
JB		 14209 switch (INTEL_INFO(dev)->gen) {
14210 case 2:
14211 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14212 break;
14213
14214 case 3:
14215 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14216 break;
14217
14218 case 4:
14219 case 5:
14220 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14221 break;
14222
14223 case 6:
14224 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14225 break;
7c9017e5 14226 case 7:
4e0bbc31 14227 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
7c9017e5
JB		 14228 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14229 break;
830c81db 14230 case 9:
ba343e02
TU		 14231 /* Drop through - unsupported since execlist only. */
14232 default:
14233 /* Default just returns -ENODEV to indicate unsupported */
14234 dev_priv->display.queue_flip = intel_default_queue_flip;
8c9f3aaf 14235 }
7bd688cd
JN		 14236
14237 intel_panel_init_backlight_funcs(dev);
e39b999a
VS		 14238
14239 mutex_init(&dev_priv->pps_mutex);
e70236a8
JB		 14240}
14241
b690e96c
JB		 14242/*
14243 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14244 * resume, or other times. This quirk makes sure that's the case for
14245 * affected systems.
14246 */
0206e353 14247static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 14248{
14249 struct drm_i915_private *dev_priv = dev->dev_private;
14250
14251 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 14252 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 14253}
14254
b6b5d049
VS		 14255static void quirk_pipeb_force(struct drm_device *dev)
14256{
14257 struct drm_i915_private *dev_priv = dev->dev_private;
14258
14259 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14260 DRM_INFO("applying pipe b force quirk\n");
14261}
14262
435793df
KP		 14263/*
14264 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14265 */
14266static void quirk_ssc_force_disable(struct drm_device *dev)
14267{
14268 struct drm_i915_private *dev_priv = dev->dev_private;
14269 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 14270 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 14271}
14272
4dca20ef 14273/*
5a15ab5b
CE		 14274 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14275 * brightness value
4dca20ef
CE		 14276 */
14277static void quirk_invert_brightness(struct drm_device *dev)
14278{
14279 struct drm_i915_private *dev_priv = dev->dev_private;
14280 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 14281 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 14282}
14283
9c72cc6f
SD		 14284/* Some VBT's incorrectly indicate no backlight is present */
14285static void quirk_backlight_present(struct drm_device *dev)
14286{
14287 struct drm_i915_private *dev_priv = dev->dev_private;
14288 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14289 DRM_INFO("applying backlight present quirk\n");
14290}
14291
b690e96c
JB		 14292struct intel_quirk {
14293 int device;
14294 int subsystem_vendor;
14295 int subsystem_device;
14296 void (*hook)(struct drm_device *dev);
14297};
14298
5f85f176
EE		 14299/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14300struct intel_dmi_quirk {
14301 void (*hook)(struct drm_device *dev);
14302 const struct dmi_system_id (*dmi_id_list)[];
14303};
14304
14305static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14306{
14307 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14308 return 1;
14309}
14310
14311static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14312 {
14313 .dmi_id_list = &(const struct dmi_system_id[]) {
14314 {
14315 .callback = intel_dmi_reverse_brightness,
14316 .ident = "NCR Corporation",
14317 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14318 DMI_MATCH(DMI_PRODUCT_NAME, ""),
14319 },
14320 },
14321 { } /* terminating entry */
14322 },
14323 .hook = quirk_invert_brightness,
14324 },
14325};
14326
c43b5634 14327static struct intel_quirk intel_quirks[] = {
b690e96c
JB		 14328 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14329 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14330
b690e96c
JB		 14331 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14332 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14333
5f080c0f
VS		 14334 /* 830 needs to leave pipe A & dpll A up */
14335 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14336
b6b5d049
VS		 14337 /* 830 needs to leave pipe B & dpll B up */
14338 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14339
435793df
KP		 14340 /* Lenovo U160 cannot use SSC on LVDS */
14341 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 14342
14343 /* Sony Vaio Y cannot use SSC on LVDS */
14344 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b 14345
be505f64
AH		 14346 /* Acer Aspire 5734Z must invert backlight brightness */
14347 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14348
14349 /* Acer/eMachines G725 */
14350 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14351
14352 /* Acer/eMachines e725 */
14353 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14354
14355 /* Acer/Packard Bell NCL20 */
14356 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14357
14358 /* Acer Aspire 4736Z */
14359 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
0f540c3a
JN		 14360
14361 /* Acer Aspire 5336 */
14362 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
2e93a1aa
SD		 14363
14364 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14365 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
d4967d8c 14366
dfb3d47b
SD		 14367 /* Acer C720 Chromebook (Core i3 4005U) */
14368 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14369
b2a9601c 14370 /* Apple Macbook 2,1 (Core 2 T7400) */
14371 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14372
d4967d8c
SD		 14373 /* Toshiba CB35 Chromebook (Celeron 2955U) */
14374 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
724cb06f
SD		 14375
14376 /* HP Chromebook 14 (Celeron 2955U) */
14377 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
cf6f0af9
JN		 14378
14379 /* Dell Chromebook 11 */
14380 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
b690e96c
JB		 14381};
14382
14383static void intel_init_quirks(struct drm_device *dev)
14384{
14385 struct pci_dev *d = dev->pdev;
14386 int i;
14387
14388 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14389 struct intel_quirk *q = &intel_quirks[i];
14390
14391 if (d->device == q->device &&
14392 (d->subsystem_vendor == q->subsystem_vendor ||
14393 q->subsystem_vendor == PCI_ANY_ID) &&
14394 (d->subsystem_device == q->subsystem_device ||
14395 q->subsystem_device == PCI_ANY_ID))
14396 q->hook(dev);
14397 }
5f85f176
EE		 14398 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14399 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14400 intel_dmi_quirks[i].hook(dev);
14401 }
b690e96c
JB		 14402}
14403
9cce37f4
JB		 14404/* Disable the VGA plane that we never use */
14405static void i915_disable_vga(struct drm_device *dev)
14406{
14407 struct drm_i915_private *dev_priv = dev->dev_private;
14408 u8 sr1;
766aa1c4 14409 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4 14410
2b37c616 14411 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
9cce37f4 14412 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 14413 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 14414 sr1 = inb(VGA_SR_DATA);
14415 outb(sr1 | 1<<5, VGA_SR_DATA);
14416 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
14417 udelay(300);
14418
01f5a626 14419 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9cce37f4
JB		 14420 POSTING_READ(vga_reg);
14421}
14422
f817586c
DV		 14423void intel_modeset_init_hw(struct drm_device *dev)
14424{
a8f78b58
ED		 14425 intel_prepare_ddi(dev);
14426
f8bf63fd
VS		 14427 if (IS_VALLEYVIEW(dev))
14428 vlv_update_cdclk(dev);
14429
f817586c
DV		 14430 intel_init_clock_gating(dev);
14431
8090c6b9 14432 intel_enable_gt_powersave(dev);
f817586c
DV		 14433}
14434
79e53945
JB		 14435void intel_modeset_init(struct drm_device *dev)
14436{
652c393a 14437 struct drm_i915_private *dev_priv = dev->dev_private;
1fe47785 14438 int sprite, ret;
8cc87b75 14439 enum pipe pipe;
46f297fb 14440 struct intel_crtc *crtc;
79e53945
JB		 14441
14442 drm_mode_config_init(dev);
14443
14444 dev->mode_config.min_width = 0;
14445 dev->mode_config.min_height = 0;
14446
019d96cb
DA		 14447 dev->mode_config.preferred_depth = 24;
14448 dev->mode_config.prefer_shadow = 1;
14449
25bab385
TU		 14450 dev->mode_config.allow_fb_modifiers = true;
14451
e6ecefaa 14452 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 14453
b690e96c
JB		 14454 intel_init_quirks(dev);
14455
1fa61106
ED		 14456 intel_init_pm(dev);
14457
e3c74757
BW		 14458 if (INTEL_INFO(dev)->num_pipes == 0)
14459 return;
14460
e70236a8 14461 intel_init_display(dev);
7c10a2b5 14462 intel_init_audio(dev);
e70236a8 14463
a6c45cf0
CW		 14464 if (IS_GEN2(dev)) {
14465 dev->mode_config.max_width = 2048;
14466 dev->mode_config.max_height = 2048;
14467 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 14468 dev->mode_config.max_width = 4096;
14469 dev->mode_config.max_height = 4096;
79e53945 14470 } else {
a6c45cf0
CW		 14471 dev->mode_config.max_width = 8192;
14472 dev->mode_config.max_height = 8192;
79e53945 14473 }
068be561 14474
dc41c154
VS		 14475 if (IS_845G(dev) || IS_I865G(dev)) {
14476 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
14477 dev->mode_config.cursor_height = 1023;
14478 } else if (IS_GEN2(dev)) {
068be561
DL		 14479 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
14480 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
14481 } else {
14482 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
14483 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
14484 }
14485
5d4545ae 14486 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 14487
28c97730 14488 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 14489 INTEL_INFO(dev)->num_pipes,
14490 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 14491
055e393f 14492 for_each_pipe(dev_priv, pipe) {
8cc87b75 14493 intel_crtc_init(dev, pipe);
3bdcfc0c 14494 for_each_sprite(dev_priv, pipe, sprite) {
1fe47785 14495 ret = intel_plane_init(dev, pipe, sprite);
7f1f3851 14496 if (ret)
06da8da2 14497 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
1fe47785 14498 pipe_name(pipe), sprite_name(pipe, sprite), ret);
7f1f3851 14499 }
79e53945
JB		 14500 }
14501
f42bb70d
JB		 14502 intel_init_dpio(dev);
14503
e72f9fbf 14504 intel_shared_dpll_init(dev);
ee7b9f93 14505
9cce37f4
JB		 14506 /* Just disable it once at startup */
14507 i915_disable_vga(dev);
79e53945 14508 intel_setup_outputs(dev);
11be49eb
CW		 14509
14510 /* Just in case the BIOS is doing something questionable. */
7ff0ebcc 14511 intel_fbc_disable(dev);
fa9fa083 14512
6e9f798d 14513 drm_modeset_lock_all(dev);
fa9fa083 14514 intel_modeset_setup_hw_state(dev, false);
6e9f798d 14515 drm_modeset_unlock_all(dev);
46f297fb 14516
d3fcc808 14517 for_each_intel_crtc(dev, crtc) {
46f297fb
JB		 14518 if (!crtc->active)
14519 continue;
14520
46f297fb 14521 /*
46f297fb
JB		 14522 * Note that reserving the BIOS fb up front prevents us
14523 * from stuffing other stolen allocations like the ring
14524 * on top. This prevents some ugliness at boot time, and
14525 * can even allow for smooth boot transitions if the BIOS
14526 * fb is large enough for the active pipe configuration.
14527 */
5724dbd1
DL		 14528 if (dev_priv->display.get_initial_plane_config) {
14529 dev_priv->display.get_initial_plane_config(crtc,
46f297fb
JB		 14530 &crtc->plane_config);
14531 /*
14532 * If the fb is shared between multiple heads, we'll
14533 * just get the first one.
14534 */
f6936e29 14535 intel_find_initial_plane_obj(crtc, &crtc->plane_config);
46f297fb 14536 }
46f297fb 14537 }
2c7111db
CW		 14538}
14539
7fad798e
DV		 14540static void intel_enable_pipe_a(struct drm_device *dev)
14541{
14542 struct intel_connector *connector;
14543 struct drm_connector *crt = NULL;
14544 struct intel_load_detect_pipe load_detect_temp;
208bf9fd 14545 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
7fad798e
DV		 14546
14547 /* We can't just switch on the pipe A, we need to set things up with a
14548 * proper mode and output configuration. As a gross hack, enable pipe A
14549 * by enabling the load detect pipe once. */
3a3371ff 14550 for_each_intel_connector(dev, connector) {
7fad798e
DV		 14551 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
14552 crt = &connector->base;
14553 break;
14554 }
14555 }
14556
14557 if (!crt)
14558 return;
14559
208bf9fd 14560 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
49172fee 14561 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
7fad798e
DV		 14562}
14563
fa555837
DV		 14564static bool
14565intel_check_plane_mapping(struct intel_crtc *crtc)
14566{
7eb552ae
BW		 14567 struct drm_device *dev = crtc->base.dev;
14568 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 14569 u32 reg, val;
14570
7eb552ae 14571 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 14572 return true;
14573
14574 reg = DSPCNTR(!crtc->plane);
14575 val = I915_READ(reg);
14576
14577 if ((val & DISPLAY_PLANE_ENABLE) &&
14578 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
14579 return false;
14580
14581 return true;
14582}
14583
24929352
DV		 14584static void intel_sanitize_crtc(struct intel_crtc *crtc)
14585{
14586 struct drm_device *dev = crtc->base.dev;
14587 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 14588 u32 reg;
24929352 14589
24929352 14590 /* Clear any frame start delays used for debugging left by the BIOS */
6e3c9717 14591 reg = PIPECONF(crtc->config->cpu_transcoder);
24929352
DV		 14592 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
14593
d3eaf884 14594 /* restore vblank interrupts to correct state */
9625604c 14595 drm_crtc_vblank_reset(&crtc->base);
d297e103
VS		 14596 if (crtc->active) {
14597 update_scanline_offset(crtc);
9625604c
DV		 14598 drm_crtc_vblank_on(&crtc->base);
14599 }
d3eaf884 14600
24929352 14601 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 14602 * disable the crtc (and hence change the state) if it is wrong. Note
14603 * that gen4+ has a fixed plane -> pipe mapping. */
14604 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 14605 struct intel_connector *connector;
14606 bool plane;
14607
24929352
DV		 14608 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
14609 crtc->base.base.id);
14610
14611 /* Pipe has the wrong plane attached and the plane is active.
14612 * Temporarily change the plane mapping and disable everything
14613 * ... */
14614 plane = crtc->plane;
b70709a6 14615 to_intel_plane_state(crtc->base.primary->state)->visible = true;
24929352 14616 crtc->plane = !plane;
ce22dba9 14617 intel_crtc_disable_planes(&crtc->base);
24929352
DV		 14618 dev_priv->display.crtc_disable(&crtc->base);
14619 crtc->plane = plane;
14620
14621 /* ... and break all links. */
3a3371ff 14622 for_each_intel_connector(dev, connector) {
24929352
DV		 14623 if (connector->encoder->base.crtc != &crtc->base)
14624 continue;
14625
7f1950fb
EE		 14626 connector->base.dpms = DRM_MODE_DPMS_OFF;
14627 connector->base.encoder = NULL;
24929352 14628 }
7f1950fb
EE		 14629 /* multiple connectors may have the same encoder:
14630 * handle them and break crtc link separately */
3a3371ff 14631 for_each_intel_connector(dev, connector)
7f1950fb
EE		 14632 if (connector->encoder->base.crtc == &crtc->base) {
14633 connector->encoder->base.crtc = NULL;
14634 connector->encoder->connectors_active = false;
14635 }
24929352
DV		 14636
14637 WARN_ON(crtc->active);
83d65738 14638 crtc->base.state->enable = false;
49d6fa21 14639 crtc->base.state->active = false;
24929352
DV		 14640 crtc->base.enabled = false;
14641 }
24929352 14642
7fad798e
DV		 14643 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
14644 crtc->pipe == PIPE_A && !crtc->active) {
14645 /* BIOS forgot to enable pipe A, this mostly happens after
14646 * resume. Force-enable the pipe to fix this, the update_dpms
14647 * call below we restore the pipe to the right state, but leave
14648 * the required bits on. */
14649 intel_enable_pipe_a(dev);
14650 }
14651
24929352
DV		 14652 /* Adjust the state of the output pipe according to whether we
14653 * have active connectors/encoders. */
14654 intel_crtc_update_dpms(&crtc->base);
14655
83d65738 14656 if (crtc->active != crtc->base.state->enable) {
24929352
DV		 14657 struct intel_encoder *encoder;
14658
14659 /* This can happen either due to bugs in the get_hw_state
14660 * functions or because the pipe is force-enabled due to the
14661 * pipe A quirk. */
14662 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
14663 crtc->base.base.id,
83d65738 14664 crtc->base.state->enable ? "enabled" : "disabled",
24929352
DV		 14665 crtc->active ? "enabled" : "disabled");
14666
83d65738 14667 crtc->base.state->enable = crtc->active;
49d6fa21 14668 crtc->base.state->active = crtc->active;
24929352
DV		 14669 crtc->base.enabled = crtc->active;
14670
14671 /* Because we only establish the connector -> encoder ->
14672 * crtc links if something is active, this means the
14673 * crtc is now deactivated. Break the links. connector
14674 * -> encoder links are only establish when things are
14675 * actually up, hence no need to break them. */
14676 WARN_ON(crtc->active);
14677
14678 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
14679 WARN_ON(encoder->connectors_active);
14680 encoder->base.crtc = NULL;
14681 }
14682 }
c5ab3bc0 14683
a3ed6aad 14684 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
4cc31489
DV		 14685 /*
14686 * We start out with underrun reporting disabled to avoid races.
14687 * For correct bookkeeping mark this on active crtcs.
14688 *
c5ab3bc0
DV		 14689 * Also on gmch platforms we dont have any hardware bits to
14690 * disable the underrun reporting. Which means we need to start
14691 * out with underrun reporting disabled also on inactive pipes,
14692 * since otherwise we'll complain about the garbage we read when
14693 * e.g. coming up after runtime pm.
14694 *
4cc31489
DV		 14695 * No protection against concurrent access is required - at
14696 * worst a fifo underrun happens which also sets this to false.
14697 */
14698 crtc->cpu_fifo_underrun_disabled = true;
14699 crtc->pch_fifo_underrun_disabled = true;
14700 }
24929352
DV		 14701}
14702
14703static void intel_sanitize_encoder(struct intel_encoder *encoder)
14704{
14705 struct intel_connector *connector;
14706 struct drm_device *dev = encoder->base.dev;
14707
14708 /* We need to check both for a crtc link (meaning that the
14709 * encoder is active and trying to read from a pipe) and the
14710 * pipe itself being active. */
14711 bool has_active_crtc = encoder->base.crtc &&
14712 to_intel_crtc(encoder->base.crtc)->active;
14713
14714 if (encoder->connectors_active && !has_active_crtc) {
14715 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
14716 encoder->base.base.id,
8e329a03 14717 encoder->base.name);
24929352
DV		 14718
14719 /* Connector is active, but has no active pipe. This is
14720 * fallout from our resume register restoring. Disable
14721 * the encoder manually again. */
14722 if (encoder->base.crtc) {
14723 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
14724 encoder->base.base.id,
8e329a03 14725 encoder->base.name);
24929352 14726 encoder->disable(encoder);
a62d1497
VS		 14727 if (encoder->post_disable)
14728 encoder->post_disable(encoder);
24929352 14729 }
7f1950fb
EE		 14730 encoder->base.crtc = NULL;
14731 encoder->connectors_active = false;
24929352
DV		 14732
14733 /* Inconsistent output/port/pipe state happens presumably due to
14734 * a bug in one of the get_hw_state functions. Or someplace else
14735 * in our code, like the register restore mess on resume. Clamp
14736 * things to off as a safer default. */
3a3371ff 14737 for_each_intel_connector(dev, connector) {
24929352
DV		 14738 if (connector->encoder != encoder)
14739 continue;
7f1950fb
EE		 14740 connector->base.dpms = DRM_MODE_DPMS_OFF;
14741 connector->base.encoder = NULL;
24929352
DV		 14742 }
14743 }
14744 /* Enabled encoders without active connectors will be fixed in
14745 * the crtc fixup. */
14746}
14747
04098753 14748void i915_redisable_vga_power_on(struct drm_device *dev)
0fde901f
KM		 14749{
14750 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 14751 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f 14752
04098753
ID		 14753 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
14754 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
14755 i915_disable_vga(dev);
14756 }
14757}
14758
14759void i915_redisable_vga(struct drm_device *dev)
14760{
14761 struct drm_i915_private *dev_priv = dev->dev_private;
14762
8dc8a27c
PZ		 14763 /* This function can be called both from intel_modeset_setup_hw_state or
14764 * at a very early point in our resume sequence, where the power well
14765 * structures are not yet restored. Since this function is at a very
14766 * paranoid "someone might have enabled VGA while we were not looking"
14767 * level, just check if the power well is enabled instead of trying to
14768 * follow the "don't touch the power well if we don't need it" policy
14769 * the rest of the driver uses. */
f458ebbc 14770 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
8dc8a27c
PZ		 14771 return;
14772
04098753 14773 i915_redisable_vga_power_on(dev);
0fde901f
KM		 14774}
14775
98ec7739
VS		 14776static bool primary_get_hw_state(struct intel_crtc *crtc)
14777{
14778 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
14779
14780 if (!crtc->active)
14781 return false;
14782
14783 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
14784}
14785
30e984df 14786static void intel_modeset_readout_hw_state(struct drm_device *dev)
24929352
DV		 14787{
14788 struct drm_i915_private *dev_priv = dev->dev_private;
14789 enum pipe pipe;
24929352
DV		 14790 struct intel_crtc *crtc;
14791 struct intel_encoder *encoder;
14792 struct intel_connector *connector;
5358901f 14793 int i;
24929352 14794
d3fcc808 14795 for_each_intel_crtc(dev, crtc) {
b70709a6
ML		 14796 struct drm_plane *primary = crtc->base.primary;
14797 struct intel_plane_state *plane_state;
14798
6e3c9717 14799 memset(crtc->config, 0, sizeof(*crtc->config));
3b117c8f 14800
6e3c9717 14801 crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
9953599b 14802
0e8ffe1b 14803 crtc->active = dev_priv->display.get_pipe_config(crtc,
6e3c9717 14804 crtc->config);
24929352 14805
83d65738 14806 crtc->base.state->enable = crtc->active;
49d6fa21 14807 crtc->base.state->active = crtc->active;
24929352 14808 crtc->base.enabled = crtc->active;
b70709a6
ML		 14809
14810 plane_state = to_intel_plane_state(primary->state);
14811 plane_state->visible = primary_get_hw_state(crtc);
24929352
DV		 14812
14813 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
14814 crtc->base.base.id,
14815 crtc->active ? "enabled" : "disabled");
14816 }
14817
5358901f
DV		 14818 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
14819 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
14820
3e369b76
ACO		 14821 pll->on = pll->get_hw_state(dev_priv, pll,
14822 &pll->config.hw_state);
5358901f 14823 pll->active = 0;
3e369b76 14824 pll->config.crtc_mask = 0;
d3fcc808 14825 for_each_intel_crtc(dev, crtc) {
1e6f2ddc 14826 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
5358901f 14827 pll->active++;
3e369b76 14828 pll->config.crtc_mask |= 1 << crtc->pipe;
1e6f2ddc 14829 }
5358901f 14830 }
5358901f 14831
1e6f2ddc 14832 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
3e369b76 14833 pll->name, pll->config.crtc_mask, pll->on);
bd2bb1b9 14834
3e369b76 14835 if (pll->config.crtc_mask)
bd2bb1b9 14836 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5358901f
DV		 14837 }
14838
b2784e15 14839 for_each_intel_encoder(dev, encoder) {
24929352
DV		 14840 pipe = 0;
14841
14842 if (encoder->get_hw_state(encoder, &pipe)) {
045ac3b5
JB		 14843 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
14844 encoder->base.crtc = &crtc->base;
6e3c9717 14845 encoder->get_config(encoder, crtc->config);
24929352
DV		 14846 } else {
14847 encoder->base.crtc = NULL;
14848 }
14849
14850 encoder->connectors_active = false;
6f2bcceb 14851 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
24929352 14852 encoder->base.base.id,
8e329a03 14853 encoder->base.name,
24929352 14854 encoder->base.crtc ? "enabled" : "disabled",
6f2bcceb 14855 pipe_name(pipe));
24929352
DV		 14856 }
14857
3a3371ff 14858 for_each_intel_connector(dev, connector) {
24929352
DV		 14859 if (connector->get_hw_state(connector)) {
14860 connector->base.dpms = DRM_MODE_DPMS_ON;
14861 connector->encoder->connectors_active = true;
14862 connector->base.encoder = &connector->encoder->base;
14863 } else {
14864 connector->base.dpms = DRM_MODE_DPMS_OFF;
14865 connector->base.encoder = NULL;
14866 }
14867 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
14868 connector->base.base.id,
c23cc417 14869 connector->base.name,
24929352
DV		 14870 connector->base.encoder ? "enabled" : "disabled");
14871 }
30e984df
DV		 14872}
14873
14874/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
14875 * and i915 state tracking structures. */
14876void intel_modeset_setup_hw_state(struct drm_device *dev,
14877 bool force_restore)
14878{
14879 struct drm_i915_private *dev_priv = dev->dev_private;
14880 enum pipe pipe;
30e984df
DV		 14881 struct intel_crtc *crtc;
14882 struct intel_encoder *encoder;
35c95375 14883 int i;
30e984df
DV		 14884
14885 intel_modeset_readout_hw_state(dev);
24929352 14886
babea61d
JB		 14887 /*
14888 * Now that we have the config, copy it to each CRTC struct
14889 * Note that this could go away if we move to using crtc_config
14890 * checking everywhere.
14891 */
d3fcc808 14892 for_each_intel_crtc(dev, crtc) {
d330a953 14893 if (crtc->active && i915.fastboot) {
6e3c9717
ACO		 14894 intel_mode_from_pipe_config(&crtc->base.mode,
14895 crtc->config);
babea61d
JB		 14896 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
14897 crtc->base.base.id);
14898 drm_mode_debug_printmodeline(&crtc->base.mode);
14899 }
14900 }
14901
24929352 14902 /* HW state is read out, now we need to sanitize this mess. */
b2784e15 14903 for_each_intel_encoder(dev, encoder) {
24929352
DV		 14904 intel_sanitize_encoder(encoder);
14905 }
14906
055e393f 14907 for_each_pipe(dev_priv, pipe) {
24929352
DV		 14908 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
14909 intel_sanitize_crtc(crtc);
6e3c9717
ACO		 14910 intel_dump_pipe_config(crtc, crtc->config,
14911 "[setup_hw_state]");
24929352 14912 }
9a935856 14913
d29b2f9d
ACO		 14914 intel_modeset_update_connector_atomic_state(dev);
14915
35c95375
DV		 14916 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
14917 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
14918
14919 if (!pll->on || pll->active)
14920 continue;
14921
14922 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
14923
14924 pll->disable(dev_priv, pll);
14925 pll->on = false;
14926 }
14927
3078999f
PB		 14928 if (IS_GEN9(dev))
14929 skl_wm_get_hw_state(dev);
14930 else if (HAS_PCH_SPLIT(dev))
243e6a44
VS		 14931 ilk_wm_get_hw_state(dev);
14932
45e2b5f6 14933 if (force_restore) {
7d0bc1ea
VS		 14934 i915_redisable_vga(dev);
14935
f30da187
DV		 14936 /*
14937 * We need to use raw interfaces for restoring state to avoid
14938 * checking (bogus) intermediate states.
14939 */
055e393f 14940 for_each_pipe(dev_priv, pipe) {
b5644d05
JB		 14941 struct drm_crtc *crtc =
14942 dev_priv->pipe_to_crtc_mapping[pipe];
f30da187 14943
83a57153 14944 intel_crtc_restore_mode(crtc);
45e2b5f6
DV		 14945 }
14946 } else {
14947 intel_modeset_update_staged_output_state(dev);
14948 }
8af6cf88
DV		 14949
14950 intel_modeset_check_state(dev);
2c7111db
CW		 14951}
14952
14953void intel_modeset_gem_init(struct drm_device *dev)
14954{
92122789 14955 struct drm_i915_private *dev_priv = dev->dev_private;
484b41dd 14956 struct drm_crtc *c;
2ff8fde1 14957 struct drm_i915_gem_object *obj;
e0d6149b 14958 int ret;
484b41dd 14959
ae48434c
ID		 14960 mutex_lock(&dev->struct_mutex);
14961 intel_init_gt_powersave(dev);
14962 mutex_unlock(&dev->struct_mutex);
14963
92122789
JB		 14964 /*
14965 * There may be no VBT; and if the BIOS enabled SSC we can
14966 * just keep using it to avoid unnecessary flicker. Whereas if the
14967 * BIOS isn't using it, don't assume it will work even if the VBT
14968 * indicates as much.
14969 */
14970 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
14971 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
14972 DREF_SSC1_ENABLE);
14973
1833b134 14974 intel_modeset_init_hw(dev);
02e792fb
DV		 14975
14976 intel_setup_overlay(dev);
484b41dd
JB		 14977
14978 /*
14979 * Make sure any fbs we allocated at startup are properly
14980 * pinned & fenced. When we do the allocation it's too early
14981 * for this.
14982 */
70e1e0ec 14983 for_each_crtc(dev, c) {
2ff8fde1
MR		 14984 obj = intel_fb_obj(c->primary->fb);
14985 if (obj == NULL)
484b41dd
JB		 14986 continue;
14987
e0d6149b
TU		 14988 mutex_lock(&dev->struct_mutex);
14989 ret = intel_pin_and_fence_fb_obj(c->primary,
14990 c->primary->fb,
14991 c->primary->state,
14992 NULL);
14993 mutex_unlock(&dev->struct_mutex);
14994 if (ret) {
484b41dd
JB		 14995 DRM_ERROR("failed to pin boot fb on pipe %d\n",
14996 to_intel_crtc(c)->pipe);
66e514c1
DA		 14997 drm_framebuffer_unreference(c->primary->fb);
14998 c->primary->fb = NULL;
afd65eb4 14999 update_state_fb(c->primary);
484b41dd
JB		 15000 }
15001 }
0962c3c9
VS		 15002
15003 intel_backlight_register(dev);
79e53945
JB		 15004}
15005
4932e2c3
ID		 15006void intel_connector_unregister(struct intel_connector *intel_connector)
15007{
15008 struct drm_connector *connector = &intel_connector->base;
15009
15010 intel_panel_destroy_backlight(connector);
34ea3d38 15011 drm_connector_unregister(connector);
4932e2c3
ID		 15012}
15013
79e53945
JB		 15014void intel_modeset_cleanup(struct drm_device *dev)
15015{
652c393a 15016 struct drm_i915_private *dev_priv = dev->dev_private;
d9255d57 15017 struct drm_connector *connector;
652c393a 15018
2eb5252e
ID		 15019 intel_disable_gt_powersave(dev);
15020
0962c3c9
VS		 15021 intel_backlight_unregister(dev);
15022
fd0c0642
DV		 15023 /*
15024 * Interrupts and polling as the first thing to avoid creating havoc.
2eb5252e 15025 * Too much stuff here (turning of connectors, ...) would
fd0c0642
DV		 15026 * experience fancy races otherwise.
15027 */
2aeb7d3a 15028 intel_irq_uninstall(dev_priv);
eb21b92b 15029
fd0c0642
DV		 15030 /*
15031 * Due to the hpd irq storm handling the hotplug work can re-arm the
15032 * poll handlers. Hence disable polling after hpd handling is shut down.
15033 */
f87ea761 15034 drm_kms_helper_poll_fini(dev);
fd0c0642 15035
652c393a
JB		 15036 mutex_lock(&dev->struct_mutex);
15037
723bfd70
JB		 15038 intel_unregister_dsm_handler();
15039
7ff0ebcc 15040 intel_fbc_disable(dev);
e70236a8 15041
69341a5e
KH		 15042 mutex_unlock(&dev->struct_mutex);
15043
1630fe75
CW		 15044 /* flush any delayed tasks or pending work */
15045 flush_scheduled_work();
15046
db31af1d
JN		 15047 /* destroy the backlight and sysfs files before encoders/connectors */
15048 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4932e2c3
ID		 15049 struct intel_connector *intel_connector;
15050
15051 intel_connector = to_intel_connector(connector);
15052 intel_connector->unregister(intel_connector);
db31af1d 15053 }
d9255d57 15054
79e53945 15055 drm_mode_config_cleanup(dev);
4d7bb011
DV		 15056
15057 intel_cleanup_overlay(dev);
ae48434c
ID		 15058
15059 mutex_lock(&dev->struct_mutex);
15060 intel_cleanup_gt_powersave(dev);
15061 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 15062}
15063
f1c79df3
ZW		 15064/*
15065 * Return which encoder is currently attached for connector.
15066 */
df0e9248 15067struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 15068{
df0e9248
CW		 15069 return &intel_attached_encoder(connector)->base;
15070}
f1c79df3 15071
df0e9248
CW		 15072void intel_connector_attach_encoder(struct intel_connector *connector,
15073 struct intel_encoder *encoder)
15074{
15075 connector->encoder = encoder;
15076 drm_mode_connector_attach_encoder(&connector->base,
15077 &encoder->base);
79e53945 15078}
28d52043
DA		 15079
15080/*
15081 * set vga decode state - true == enable VGA decode
15082 */
15083int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15084{
15085 struct drm_i915_private *dev_priv = dev->dev_private;
a885b3cc 15086 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
28d52043
DA		 15087 u16 gmch_ctrl;
15088
75fa041d
CW		 15089 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15090 DRM_ERROR("failed to read control word\n");
15091 return -EIO;
15092 }
15093
c0cc8a55
CW		 15094 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15095 return 0;
15096
28d52043
DA		 15097 if (state)
15098 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15099 else
15100 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
75fa041d
CW		 15101
15102 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15103 DRM_ERROR("failed to write control word\n");
15104 return -EIO;
15105 }
15106
28d52043
DA		 15107 return 0;
15108}
c4a1d9e4 15109
c4a1d9e4 15110struct intel_display_error_state {
ff57f1b0
PZ		 15111
15112 u32 power_well_driver;
15113
63b66e5b
CW		 15114 int num_transcoders;
15115
c4a1d9e4
CW		 15116 struct intel_cursor_error_state {
15117 u32 control;
15118 u32 position;
15119 u32 base;
15120 u32 size;
52331309 15121 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 15122
15123 struct intel_pipe_error_state {
ddf9c536 15124 bool power_domain_on;
c4a1d9e4 15125 u32 source;
f301b1e1 15126 u32 stat;
52331309 15127 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 15128
15129 struct intel_plane_error_state {
15130 u32 control;
15131 u32 stride;
15132 u32 size;
15133 u32 pos;
15134 u32 addr;
15135 u32 surface;
15136 u32 tile_offset;
52331309 15137 } plane[I915_MAX_PIPES];
63b66e5b
CW		 15138
15139 struct intel_transcoder_error_state {
ddf9c536 15140 bool power_domain_on;
63b66e5b
CW		 15141 enum transcoder cpu_transcoder;
15142
15143 u32 conf;
15144
15145 u32 htotal;
15146 u32 hblank;
15147 u32 hsync;
15148 u32 vtotal;
15149 u32 vblank;
15150 u32 vsync;
15151 } transcoder[4];
c4a1d9e4
CW		 15152};
15153
15154struct intel_display_error_state *
15155intel_display_capture_error_state(struct drm_device *dev)
15156{
fbee40df 15157 struct drm_i915_private *dev_priv = dev->dev_private;
c4a1d9e4 15158 struct intel_display_error_state *error;
63b66e5b
CW		 15159 int transcoders[] = {
15160 TRANSCODER_A,
15161 TRANSCODER_B,
15162 TRANSCODER_C,
15163 TRANSCODER_EDP,
15164 };
c4a1d9e4
CW		 15165 int i;
15166
63b66e5b
CW		 15167 if (INTEL_INFO(dev)->num_pipes == 0)
15168 return NULL;
15169
9d1cb914 15170 error = kzalloc(sizeof(*error), GFP_ATOMIC);
c4a1d9e4
CW		 15171 if (error == NULL)
15172 return NULL;
15173
190be112 15174 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ff57f1b0
PZ		 15175 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15176
055e393f 15177 for_each_pipe(dev_priv, i) {
ddf9c536 15178 error->pipe[i].power_domain_on =
f458ebbc
DV		 15179 __intel_display_power_is_enabled(dev_priv,
15180 POWER_DOMAIN_PIPE(i));
ddf9c536 15181 if (!error->pipe[i].power_domain_on)
9d1cb914
PZ		 15182 continue;
15183
5efb3e28
VS		 15184 error->cursor[i].control = I915_READ(CURCNTR(i));
15185 error->cursor[i].position = I915_READ(CURPOS(i));
15186 error->cursor[i].base = I915_READ(CURBASE(i));
c4a1d9e4
CW		 15187
15188 error->plane[i].control = I915_READ(DSPCNTR(i));
15189 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 15190 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 15191 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 15192 error->plane[i].pos = I915_READ(DSPPOS(i));
15193 }
ca291363
PZ		 15194 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15195 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 15196 if (INTEL_INFO(dev)->gen >= 4) {
15197 error->plane[i].surface = I915_READ(DSPSURF(i));
15198 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15199 }
15200
c4a1d9e4 15201 error->pipe[i].source = I915_READ(PIPESRC(i));
f301b1e1 15202
3abfce77 15203 if (HAS_GMCH_DISPLAY(dev))
f301b1e1 15204 error->pipe[i].stat = I915_READ(PIPESTAT(i));
63b66e5b
CW		 15205 }
15206
15207 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
15208 if (HAS_DDI(dev_priv->dev))
15209 error->num_transcoders++; /* Account for eDP. */
15210
15211 for (i = 0; i < error->num_transcoders; i++) {
15212 enum transcoder cpu_transcoder = transcoders[i];
15213
ddf9c536 15214 error->transcoder[i].power_domain_on =
f458ebbc 15215 __intel_display_power_is_enabled(dev_priv,
38cc1daf 15216 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
ddf9c536 15217 if (!error->transcoder[i].power_domain_on)
9d1cb914
PZ		 15218 continue;
15219
63b66e5b
CW		 15220 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15221
15222 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15223 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15224 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15225 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15226 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15227 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15228 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 15229 }
15230
15231 return error;
15232}
15233
edc3d884
MK		 15234#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15235
c4a1d9e4 15236void
edc3d884 15237intel_display_print_error_state(struct drm_i915_error_state_buf *m,
c4a1d9e4
CW		 15238 struct drm_device *dev,
15239 struct intel_display_error_state *error)
15240{
055e393f 15241 struct drm_i915_private *dev_priv = dev->dev_private;
c4a1d9e4
CW		 15242 int i;
15243
63b66e5b
CW		 15244 if (!error)
15245 return;
15246
edc3d884 15247 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
190be112 15248 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
edc3d884 15249 err_printf(m, "PWR_WELL_CTL2: %08x\n",
ff57f1b0 15250 error->power_well_driver);
055e393f 15251 for_each_pipe(dev_priv, i) {
edc3d884 15252 err_printf(m, "Pipe [%d]:\n", i);
ddf9c536
ID		 15253 err_printf(m, " Power: %s\n",
15254 error->pipe[i].power_domain_on ? "on" : "off");
edc3d884 15255 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
f301b1e1 15256 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
edc3d884
MK		 15257
15258 err_printf(m, "Plane [%d]:\n", i);
15259 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
15260 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 15261 if (INTEL_INFO(dev)->gen <= 3) {
edc3d884
MK		 15262 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
15263 err_printf(m, " POS: %08x\n", error->plane[i].pos);
80ca378b 15264 }
4b71a570 15265 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
edc3d884 15266 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4 15267 if (INTEL_INFO(dev)->gen >= 4) {
edc3d884
MK		 15268 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
15269 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
c4a1d9e4
CW		 15270 }
15271
edc3d884
MK		 15272 err_printf(m, "Cursor [%d]:\n", i);
15273 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
15274 err_printf(m, " POS: %08x\n", error->cursor[i].position);
15275 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
c4a1d9e4 15276 }
63b66e5b
CW		 15277
15278 for (i = 0; i < error->num_transcoders; i++) {
1cf84bb6 15279 err_printf(m, "CPU transcoder: %c\n",
63b66e5b 15280 transcoder_name(error->transcoder[i].cpu_transcoder));
ddf9c536
ID		 15281 err_printf(m, " Power: %s\n",
15282 error->transcoder[i].power_domain_on ? "on" : "off");
63b66e5b
CW		 15283 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
15284 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
15285 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
15286 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
15287 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
15288 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
15289 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
15290 }
c4a1d9e4 15291}
e2fcdaa9
VS		 15292
15293void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
15294{
15295 struct intel_crtc *crtc;
15296
15297 for_each_intel_crtc(dev, crtc) {
15298 struct intel_unpin_work *work;
e2fcdaa9 15299
5e2d7afc 15300 spin_lock_irq(&dev->event_lock);
e2fcdaa9
VS		 15301
15302 work = crtc->unpin_work;
15303
15304 if (work && work->event &&
15305 work->event->base.file_priv == file) {
15306 kfree(work->event);
15307 work->event = NULL;
15308 }
15309
5e2d7afc 15310 spin_unlock_irq(&dev->event_lock);
e2fcdaa9
VS		 15311 }
15312}
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